1990_National_FACT_Databook 1990 National FACT Databook
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400019
~ National
~ Semiconductor
FACT
DATABOOK
1990 Edition
Descriptions and Family Characteristics
III
Ratings, Specifications, and Waveforms
Design Considerations and
Application Notes
•
Advanced CMOS Datasheets
•
Quiet Series Datasheets
•
FCT Series Datasheets
•
FCT A and B Series Datasheets
Ordering Information and
Physical Dimensions
•
.,
iii
~
~
TRADEMARKS
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LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITIEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
NationalSemlconductorCorporation 2900 Semiconductor Drive, P.O. Box 58090, Santa Clara, California 95052-8090 (408) 721-5000
TWX (910) 339-9240
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right. at any time
without notice, to change said circuitry or specifications.
iv
S'
a
Introduction
Q..
c
~
o·
:s
FACTTM (Fairchild Advanced CMOS Technology) is a very
high-speed, low power CMOS Logic family utilizing a 1.3 ,u.M
Isoplanar silicon gate CMOS process. FACT logic functions
can attain speeds similar to that of Advanced Low Power
Schottky while retaining the advantages of CMOS logic: Ultra
low static power and high noise immunity. FACT offers the
system designer the added benefit of superior line driving
characteristics and excellent ESD and Latch-Up immunity.
FACT Quiet Series, an extension of the FACT family, is a
high speed, low power CMOS family IDEAL for ACMOS applications requiring increased noise margins. Utilizing NSC
Quiet Series Technology, FACT QS features GTOTM outputs
control, undershoot corrector and a split ground bus for superior ACMOS performance. In addition, FACT OS features
improved AC specifications, specifies maximum pin-to-pin
output skew and provides enhanced ESD immunity and
latch-up protection.
FACT FCT, an extension of the FACT family, features 7 ns
propagation delays and 64/48 mA output drive. The series
incorporates National's Ouiet Series Technology to provide
the lowest noise performance of any FCT logic family. FACT
FCTA is the high speed, high drive extension of the FACT
family featuring 5 ns maximum propagation delays and
64/48 mA output drive. In addition, FACT FCTA features
quiet circuitry to provide increased noise margins.
The FACT/FACT OS families consist of devices in two categories:
1. AC/ ACo-standard logic functions with CMOS compatible inputs and TTL and MOS compatible outputs;
2. ACT/ACTO-standard logic functions with TTL compatible inputs and TTL and MOS compatible outputs.
Product Index and Selection Guide
Lists FACT, FACT OS, FACT FCT, and FACT FCTA circuits
currently available, in design or planned. The selection guide
groups the circuits by function.
Section 1 Descriptions and Family
Characteristics . .................... . 1-1
Basic information on FACT performance including technologies.
Section 2
Ratings, Specifications and
Waveforms . ........................ . 2-1
Contains common ratings and speCifications for FACT devices, as well as AC test loads and waveforms.
v
C
o
:g
r-----------------------------------------------------------------------------~
es
:::I
Section 3 Design Considerations . ....... 3·1
Information to assist both TTL and CMOS designers
to get the most out of the FACT family.
Section 4 Advanced CMOS Datasheets .. 4·1
Contains datasheets for currently available and
pending new FACT products.
Section 5 Quiet Series Datasheets . ...... 5·1
Contains datasheets for currently available and
pending new FACT Quiet Series products.
Section 6 FeT Series Datasheets ....... . 6·1
Contains datasheets for currently available and
pending new FACT FCT products.
Section 7 FCT A and B Series
Datasheets . ................. . 7·1
Contains datasheets for currently available and
pending new FACT FCTA products.
Section 8 Ordering Information and
Physical Dimensions . ........ . 8·1
vi
~National
~ Semiconductor
Product Status Definitions
Definition of Terms
Data Sheet Identification
Product Status
Advance Intormatlon
Formative or
In Design
This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Definition
preliminary
First
Production
This data sheet contains preliminary data, and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.
No
Identification
Noted
Full
Production
This data sheet contains final speCifications. National Semiconductor
Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.
National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
vii
Alpha-Numeric Index
54AC174ACOO Quad 2·lnput NAND Gate ............................................ '......... 4·5
54AC/'74AC02 Quad 2·lnput NOR Gate ...................................................... 4·9
54AC/74AC04 H$x Inverter ................... , .. , ..•.......... , ........................... 4-13
54AC17 4AC08 Quad 2-lnput AND Gate ..................................................... 4-17
54AC174AC10 Triple 3-lnput NAND Gate .................................................... 4-21
54AC174AC11 Triple 3-lnput AND Gate. '" ............•........ , ....•...................... 4-25
54AC174AC14 Hex Inverter with Schmitt Trigger Input. ........................................ 4-28
54AC174AC20 Dual4-lnput NAND Gate ..................................................... 4-31
54AC174AC32 Quad 2-lnput OR Gate ... '" ..........•..................•..... , ... , ......... 4-34
54AC174AC74 Dual D Positive Edge-Triggered Flip·Flop ...................................... 4-38
54AC174AC86 Quad 2-lnput Exclusive-OR Gate .............................................. 4-44
54AC174AC109 Dual JK Positive Edge-Triggered Flip-Flop .................................... 4-47
54AC174AC125 Quad TRI-STATE Buffer ................•.....•............................. 4-53
54AC174AC138 1·of-8 Decoder/Demultiplexer .......•...•.... , ......... , ...... , .........•... 4-57
54AC174AC139 DuaI1-of-4 Decoder/Demultiplexer .......................................... 4-63
54AC174AC151 8-lnput Multiplexer ......................................................... 4-68
54AC174AC153 Dual4-lnput Multiplexer ..........•......................................... 4-74
54AC174AC157 Quad 2-lnput Multiplexer .....................•.............................. 4-79
54AC174AC158 Quad 2-lnput Multiplexer .................................................... 4-84
54AC/74AC161 Synchronous Presettable Binary Counter .................................. ; .. 4-B9
54AC174AC163 Synchronous Presettable Binary Counter ..................................... 4-97
54AC174AC169 4-Stage Synchronous Bidirectional Counter ................................ ~ . 4-105
54AC17 4AC17 4 Hex D Flip-Flop with Master Reset .......................................... 4-113
54AC174AC175 Quad D Flip-Flop ......................................................... 4-119
54AC174AC191 Up/Down Counter with Preset and Ripple Clock .............................. 4-125
54AC174AC240 Octal Buffer/Line Driver with TRI-STATE Outputs ............................. 4-132
54AC174AC241 Octal Buffer/Line Driver with TRI·STATE Outputs ..................•.......... 4-136
54AC174AC244 Octal Buffer/Line Driver with TRI-STATE Outputs ............................. 4-140
54AC174AC245 Octal Bidirectional Transceiver with TRI·STATE Inputs/Outputs ................ 4-144
54AC174AC251 B-Input Multiplexer with TRI-STATE Output. .....•............... '" .......... 4-148
54AC174AC253 Dual 4-lnput Multiplexer with TRI-STATE Outputs ............................. 4-154
54AC174AC257 Quad 2-lnput Multiplexer with TRI-STATE Outputs ............................ 4-160
54AC174AC258 Quad 2·lnput Multiplexer with TRI·STATE Outputs ............................ 4-165
54AC174AC273 Octal D Flip-Flop ......•.........•..•...........•..... , .. '" .............. 4-170
54AC174AC280 9·Bit Parity Generator/Checker ...•. '" ..................................... 4-175
54AC174AC299 B-Input Universal Shift/Storage Register with Common Parallel 110 Pins ......... 4-179
54AC174AC367 HexTRI-STATE Buffer .................................................... 4-191
54AC174AC373 Octal Transparent Latch with TRI-STATE Outputs ....•.............•......... 4-197
54AC174AC374 Octal D Flip·Flop with TRI-STArE Outputs ..•............ , .............. " ... 4-203
54AC174AC377 Octal D Flip-Flop with Clock Enable ......................................... 4-209
54AC174AC378 Parallel D Register with Enable ...........•..........•...................... 4-215
54AC174AC520 8~Bit Identity Comparator ...•.........•......•.....................•....... 4-223
54AC174AC521 8-Bitldentity Comparator ....•.••..•.....•....•.........•..... , ..•... '" ... 4-229
54AC174AC540 Octal Buffer/Line Driver with TRI-STATE Outputs ......•...•.................. 4-240
54AC174AC541 Octal Buffer/Line Driver with TRI·STATE Outputs •.•...••..•.•.....•.......... 4·243
54AC174AC574 Octal D Flip-Flop with TRI-STATE Outputs ........•............•............• 4-259
54AC/74AC646 Octal Transceiver/Register with TRI-STATE Outputs .................•........ 4·265
54AC174AC648 Octal Transceiver/Register with TRI·STATE Outputs •......................... 4-272
54AC174AC82110·Bit D Flip-Flop with TRI-STATE Outputs .............. , .•.... , ...•........ 4-294
54AC174AC843 9-Bit Transparent Latch .•....••..........................••............... 4-313
54AC17 4AC899 9-Bit Latchable Transceiver Register with Parity Generator/Checker ..•......... 4-326
viii
Alpha-Numeric
Index(continUed)
54AC174AC2525 Minimum Skew Clock Driver .............................................. 4-338
54AC174AC2526 Minimum Skew Clock Driver with Multiplexed Clock Input ..................... 4-338
54AC174AC2708 64 x 9 First-In, First-Out Memory ........................................... 4-339
54ACQ17 4ACQ240 Quiet Series Octal Buffer/Line Driver with TR I-STATE Outputs ................. 5-7
54ACQ174ACQ241 Quiet Series Octal Buffer/Line Driver with TRI-STATE Outputs ............... 5-12
54ACQ174ACQ244 Quiet Series Octal Buffer/Line Driver with TRI-STATE Outputs ............... 5-17
54ACQ17 4ACQ245 Quiet Series Octal Bidirectional Transceiver with TRI ,STATE Outputs ......... 5-22
54ACQ174ACQ273 Quiet Series Octal D Flip-Flop ....... , , , . " " , , , , , , . , , , , , . , , , , , ... , .. , .... 5-27
54ACQ174ACQ373 Quiet Series Octal Transparent Latch with TRI-STATE Outputs., .. , , .... '" , . 5-32
54ACQ174ACQ374 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs., .... , ............... 5-38
54ACQ174ACQ377 Quiet Series Octal D Flip-Flop with Clock Enable .......... " .......•...... ,. 5-44
54ACQ174ACQ533 Quiet Series Octal Latch with TRI-STATE Outputs. , .. , .. , .. , .....• " ., ,.". 5-45
54ACQ174ACQ534 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs ...................... 5-51
54ACQ17 4ACQ543 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs. , ......... 5-57
54ACQ17 4ACQ544 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs ........ , .. 5-58
54ACQ174ACQ563 Quiet Series Octal Latch with TRI-STATE Outputs, .. , ..... , ............. , .. 5-59
54ACQ/74ACQ564 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs ............ ,., ....... 5-66
54ACQ174ACQ573 Quiet Series Octal Latch with TRI-STATE Outputs .......... , . , ......... , .. , 5-72
54ACQ174ACQ574 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs ................. " ... 5-78
54ACQ174ACQ821 Quiet Series 10-Bit D Flip-Flop with TRI-STATE Outputs ..... , .............. ,5-87
54ACT174ACTOO Quad 2-lnput NAND Gate .............. , ... , ... , ... , ... , ....... , ... , ...... , . 4-5
54ACT174ACT02 Quad 2-lnput NOR Gate ................................... , ................ 4-9
54ACT/74ACT04 Hex Inverter., ..... ,', .. , .. ,., .................. , •... , ......... , ....... ,. 4-13
54ACT174ACT08 Quad 2-lnput AND Gate .......................... , ............ , ..... , .... , 4-17
54ACT174ACT10 Triple 3-lnput NAND Gate ................................................. 4-21
54ACT174ACT32 Quad 2-lnputOR Gate ................................ , ... , ............... 4-34
54ACT174ACT74 Dual D Positive Edge-Triggered Flip-Flop., ..... , .... "." .. " ......... , .. , .. 4-38
54ACT17 4ACT1 09 Dual JK Positive Edge-Triggered Flip-Flop .................................. 4-47
54ACT174ACT125 Quad TRI-STATE Buffer ................ , ........... , .................... 4-53
54ACT174ACT138 1-of-8 Decoder/Demultiplexer ............................................ 4-57
54ACT174ACT139 Dual1-of-4 Decoder/Demultiplexer .. , ....... , ..... , ..... , .. , ..... , ....... , 4-63
54ACT174ACT151 8-lnput Multiplexer .... , .................. , .......... , ................ , ... 4-66
54ACT174ACT153 Dual4-lnput Multiplexer ............•......•.............................. 4-74
54ACT174ACT157 Quad 2-lnput Multiplexer ........................................... , ..... 4-79
54ACT174ACT158 Quad 2-lnput Multiplexer ........................................... , ..... 4-84
54ACT174ACT161 Synchronous Presettable Binary Counter, ....... , , , ..... , . , , ..... , .. , . , . , , . 4-89
54ACT174ACT163 Synchronous Presettable Binary Counter ................................... 4-97
54ACT174ACT169 4-Stage Synchronous Bidirectional Counter .............. , .. , ... , . , ... , .... 4-105
54ACT /7 4ACT17 4 Hex D Flip-Flop with Master Reset ....................... , .... , ...... , .... 4-113
54ACT174ACT175 Quad D Flip-Flop,., •... , .. '...... , ... , .. " ............ , ... , ............. 4-119
54ACT174ACT240 Octal Buffer/Line Driver with TRI-STATE Outputs .. , ... , ...... , ........... , 4-132
54ACT174ACT241 Octal Buffer/Line Driver with TRI-STATE Outputs .......................... 4-136
54ACT174ACT244 Octal Buffer/Line Driver with TRI-STATE Outputs .......................... 4-140
54ACT174ACT245 Octal Bidirectional Transceiver with TRI-STATE Inputs/Outputs ....... , ...... 4-144
54ACT174ACT251 8-lnput Multiplexer with TRI-STATE Output ....................•........... 4-148
54ACT 174ACT253 Dual 4-lnput Multiplexer with TRI-STATE Outputs ................. , , . , ...... 4-154
54ACT174ACT257 Quad 2-lnput Multiplexer with TRI-STATE Outputs ........... , .............. 4-160
54ACT174ACT258 Quad 2-lnput Multiplexer with TRI-STATE Outputs .......•.................. 4-165
54ACT 174ACT299 8-lnput Universal Shift/Storage Register with Common Parallel I/O Pins .....•. 4-179
54ACT174ACT323 8-Bit l)niversal Shift/Storage Register with Synchronous Reset and Common
I/O Pins .......................•...................................•...... '.•.. , ..•.... 4-186
ix
Alpha-Numeric Index (Continued)
54ACT174ACT368 HexTRI-STATE Inverting Buffer ......................................... 4-194
54ACT17 4ACT373 Octal Transparent Latch with TRI-STATE Outputs .......................... 4-197
54ACT174ACT374 Octal D Flip-Flop with TRI-STATE Outputs ................................. 4-203
54ACT17 4ACT377 Octal D Flip-Flop with Clock Enable ....................................... 4-209
54ACT17 4ACT399 Quad 2-Port Register ..............................................•.... 4-219
54ACT 17 4ACT520 8-Bit Identity Comparator ..................................•....•.......• 4-223
54ACT17 4ACT521 8"Bit Identity Comparator ................. ; .............................. 4-229
54ACT17 4ACT534 Octal D Flip-Flop with TRI-STATE Outputs ................... ',' •....•...•.. 4-235
54ACT17 4ACT563 Octal Latch with TRI-STATE Outputs ..................................... 4-246
54ACT174ACT564 Octal D Flip-Flop with TRI-STATE Outputs ................................. 4-251
54ACT174ACT573 Octal Latch with TRI-STATE Outputs ..................................... 4-254
54ACT174ACT574 Octal D Flip-Flop with TRI-STATE Outputs ................................. 4-259
54ACT174ACT646 Octal Transceiver/Register with TRI-STATE Outputs ..................•.... 4-265
54ACT174ACT705 Arithmetic Logic Unit for Digital Signal Processing Applications ............... 4-278
54ACT17 4ACT715 Programmable Video Sync Generator ..................................... 4-279
54ACT174ACT818 8-Bit Diagnostic Register ................................................ 4-288
54ACT174ACT821 10-Bit D Flip-Flop with TRI-STATE Outputs ................................ 4-294
54ACT174ACT823 9-BitD Flip-Flop ....................................................... 4-300
54ACT17 4ACT825 8-Bit D Flip-Flop ....................................................... 4-304
54ACTl74AGT84110-BitTransparent Latch with TRI-STATE Outputs ......................... 4-308
54ACT174ACT843 9-Bit Transparent Latch ................................................. 4-313
54ACT174ACT845 8-Bit Transparent Latch with TRI-STATE Outputs ........................... 4-321
54ACT174ACT899 9-Bit Latchable Transceiver Register with Parity Generator/Checker .......... 4-326
54ACT174ACT2708 64 x 9 First-In, First-Out Memory ........................................ 4-339
54ACT174ACT2725 512 x 9 Firstln, First Out Memory (FIFO) ...... '" ........................ 4-355
54ACT174ACT2726 512 x 9 Bidirectional First-In, First-Out Memory (BiFIFO) .................... 4-356
54ACTQ174ACTQ153 Dual4-lnput Multiplexer ................................................ 5-3
54ACTQ174ACTQ240 Quiet Series Octal Buffer/Line Driver with T81-STATE Outputs .............. 5-7
54ACTQ17 4ACTQ241 Quiet Series Octal Buffer/Line Driver with TRI-STATE Outputs ............. 5-12
54ACTQ174ACTQ244 Quiet Series Octal Buffer/Line Driver with TRI-STATE Outputs ............. 5-17
54ACTQ174ACTQ245 Quiet Series Octal Bidirectional Transceiver with TRI-STATE Outputs ....... 5-22
54ACTQ174ACTQ273 Quiet Series Octal D Flip-Flop .......................................... 5-27
54ACTQ174ACTQ373 Quiet Series Octal Transparent Latch with TRI-STATE Outputs ............. 5-32
54ACTQ174ACTQ374 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs ................... 5-38
54ACTQI74ACTQ377 Quiet Series Octal D Flip-Flop with Clock Enable ......................... 5-44
54ACTQ174ACTQ533 Quiet Series Octal Latch with TRI-STATE Outputs ........................ 5-45
54ACTQ174ACTQ534 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs ................... 5-51
54ACTQ174ACTQ543 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs ........ 5-57
54ACTQ17 4ACTQ544 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs ........ 5-58
54ACTQ174ACTQ563 Quiet Series Octal Latch with TRI-STATE Outputs ........................ 5-59
54ACTQ174ACTQ564 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs ................... 5-66
54ACTQ174ACTQ573 Quiet Series Octal Latch with TRI-STATE Outputs ................ ; ....... 5-72
54ACTQ174ACTQ574 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs .........•......... 5-78
54ACTQ174ACTQ646 Quiet Series Octal Transceiver/Register with TRI-STATE Outputs .......... 5-85
54ACTQ174ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity
Generator/Checker and TRI-STATE Outputs .............................................. 5-86
54ACTQ174ACTQ827 Quiet Series 10-Bit Buffer/Line Driver with TRI-STATE Outputs ............ 5-88
54ACTQ17 4ACTQ841 Quiet Series 1O-Bit Transparent Latch with TRI-STATE Outputs ............ 5-89
54ACTQ17 4ACTQ843 Quiet Series 9-Bit Transparent Latch with TRI-STATE Outputs ............. 5-90
54FCT540 Inverting Octal Buffer/Line Driver with TRI-STATE Outputs ........................... 6-51
54FCT541 Non-Inverting Octal Buffer/Line Driver with TRI-STATE Outputs ...................... 6-55
x
Alpha-Numeric
Index(continUed)
54FCT174FCT138 1-to-8 Multiplexer ................................................... ; ..... 6-3
54FCT174FCT138A 1-to-8 Multiplexer ........................................................ 7-3
54FCT174FCT240 Octal BufferlLine Driver with TRI-STATE Outputs ............................. 6-4
54FCT174FCT240A Octal BufferlLine Driver with TRI-STATE Outputs ........................... 7-4
54FCT174FCT241 Octal BufferlLine Driver with TRI-STATE Outputs ............................. 6-8
54FCT174FCT241 A Octal BufferlLine Driver with TRI-STATE Outputs ........................... 7-8
54FCT174 FCT244 Octal BufferlLine Driver with TRI-STATE Outputs ............................ 6-12
54FCT174FCT244A Octal BufferlLine Driver with TRI-STATE Outputs .......................... 7-12
54FCT174FCT245 Octal BufferlLine Driver with TRI-STATE Outputs ............................ 6-16
54FCT174FCT245A Octal BufferlLine Driver with TRI-STATE Outputs .......................... 7-16
54FCT174FCT273 Octal D Flip-Flop ........................................................ 6-20
54FCT174FCT273A Octal D Flip-Flop ....................................................... 7-20
54FCT174FCT373 Octal Transparent Latch with TRI-STATE Outputs ........................... 6-25
54FCT174FCT373A Octal Transparent Latch with TRI-STATE Outputs .......................... 7-21
54FCT174FCT37 4 Octal D Flip-Flop with TRI-STATE Outputs .................................. 6-30
54FCT174FCT37 4A Octal D Flip-Flop with TRI-STATE Outputs ................................. 7-26
54FCTI74FCT377 Octal D Flip-Flop with Clock Enable ........................................ 6-35
54FCTI74FCT377A Octal D Flip-Flop with Clock Enable ....................................... 7-31
54FCT 17 4FCT521 8-Bit Identity Comparator ................................................. 6-40
54FCT174FCT521A 8-Bit Identity Comparator ................................................ 7-32
54FCT174FCT533 Octal Transparent Latch with TRI-STATE Outputs ........................... 6-41
54FCT174FCT533A Octal Transparent Latch with TRI-STATE Outputs .......................... 7-33
54FCT174FCT534 Octal D Flip-Flop with TRI-STATE Outputs .................................. 6-46
54FCT174FCT534A Octal D Flip-Flop with TRI-STATE Outputs ................................. 7-38
54FCT174FCT543 Octal Registered Transceiver with TRI-STATE Outputs ....................... 6-59
54FCT174FCT543A Octal Registered Transceiver with TRI-STATE Outputs ...................... 7-43
54FCT174FCT544 Octal Registered Transceiver with TRI-STATE Outputs ....................... 6-60
54FCT174FCT544A Octal Registered Transceiver with TRI-STATE Outputs ...................... 7-48
54FCT174FCT563 Octal Transparent Latch with TRI-STATE Outputs ........................... 6-61
54FCT174FCT563A Octal Transparent Latch with TRI-STATE Outputs .......................... 7-53
54FCT174FCT564 Octal D Flip-Flop with TRI-STATE Outputs .................................. 6-66
54FCT174FCT564A Octal D Flip-Flop with TRI-STATE Outputs ................................. 7-58
54FCT 174FCT573 Octal Transparent Latch with TRI-STATE Outputs ........................... 6-70
54FCT174FCT573A Octal Transparent Latch with TRI-STATE Outputs .......................... 7-62
54FCT174FCT574 Octal D Flip-Flop with TRI-STATE Outputs .................................. 6-75
54FCT174FCT57 4A Octal D Flip-Flop with TRI-STATE Outputs ................................. 7-67
54FCT174FCT646 Octal TransceiverIRegister with TRI-STATE Outputs ......................... 6-80
54FCT174FCT646A Octal TransceiverIRegister with TRI-STATE Outputs ....................... 7-72
54FCT174FCT821A 10-Bit D Flip-Flop with TRI-STATE Outputs ................................ 7-73
54FCT 174FCT821 B 1O-Bit D Flip-Flop with TRI-STATE Outputs ................................ 7-73
54FCT174FCT823A 9-Bit D Flip-Flop with TRI-STATE Outputs ................................. 7-74
54FCT174 FCT823B 9-Bit D Flip-Flop with TRI-STATE Outputs ................................. 7-74
54FCT174FCT825A 9-Bit D Flip-Flop with TRI-STATE Outputs ................................. 7-75
54FCT174FCT825B 9-Bit D Flip-Flop with TRI-STATE Outputs ................................. 7-75
54FCT174FCT827A 10-Bit BufferlLine Driver with TRI-STATE Outputs .......................... 7-76
54FCT174FCT827B 1O-Bit BufferlLine Driver with TRI-STATE Outputs .......................... 7-76
54FCT174FCT841A 10-BitTransparent Latch with TRI-STATE Outputs ......................... 7-77
54FCT174FCT841B 10-BitTransparent Latch with TRI-STATE Outputs ......................... 7-77
54FCT174FCT843A 9-BitTransparent Latch with TRI-STATE Outputs ........................... 7-78
54FCT174FCT843B 9-Bit Transparent Latch with TRI-STATE Outputs ........................... 7-78
54FCT174FCT845A 8-Bit Transparent Latch with TRI-STATE Outputs ........................... 7-79
xi
Alpha-Numeric
Index(continUed)
54FCT17 4FCT845B 8-Bit Transparent Latch with TRI-STATE Outputs ........................... 7-79
54FCT174FCT899A 9-Bit Latchable Transceiver with Parity Generator/Checker .................. 7-80
LM1882 Programmable Video Sync Generator .............................................. 4-279
xii
"T1
»
o
~National
--I
en
CD
Semiconductor
iii"
n
O·
FACTTM Selection Guide
:::l
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c
is:
CD
Gates
Function
Device
NAND
Quad 2-lnput
Quad 2-lnput
Triple 3-lnput
Triple 3-lnput
Dual4-lnput
AND
Quad 2-lnput
Quad 2-lnput
Triple 3-lnput
ORINOR/Exclusive-OR
Quad 2-lnput OR
Quad 2-lnput OR
Quad 2-lnput NOR
Quad 2-lnput NOR
Quad 2-lnput Exclusive-OR
Inverter
Hex Inverter
Hex Inverter
Hex Schmitt Trigger Inverter
54AC/74ACOO
54ACT 17 4ACTOO
54AC17 4AC1 0
54ACT174ACT10
54AC17 4AC20
54AC17 4AC08
54ACT 17 4ACT08
54AC/74AC11
54AC17 4AC32
54ACT 17 4ACT32
54AC17 4AC02
54ACT 17 4ACT02
54AC174AC86
54AC174AC04
54ACT 17 4ACT04
54AC174AC14
Registers
Function
Device
Clock
Inputs
Parallel D Register wi Enable
Quad 2-Port Register
Diagnostic and Pipeline Register
54AC/74AC378
54ACT17 4ACT399
54ACT17 4ACT818
No
1("'/"")
2
Parity Generator/Checkers
Function
Device
Parity Generator/Checker
54AC174AC280
Octal Bidirectional Bus Transceiver
wi Parity Generator/Checker
54ACTQ174ACTQ657
Octal Bidirectional Bus Transceiver
54FCT/74FCT657
wi Parity Generator/Checker
9-Bit Registered Transceiver
54ACI7 4AC899
wi Parity Generator/Checker
54ACT 17 4ACT899
9-Bit Registered Transceiver
wi Parity Generator/Checker
54FCT 17 4FCT899
9-Bit Registered Transceiver
wi Parity Generator/Checker
---xiii
Flip-Flops
Function
Dual D
DualD
DualJK
DualJK
HexD
HexD
QuadD
QuadD
OelalD
Oelal D
OelalD
OelalD
OelalD
OelalD
OelalD
Oelal D
Oelal D
Octal D
Oelal D
Oelal D
Oelal D
Oelal D
Octal D
Octal D
OelalD
OelalD
Oelal D
OelalD
OelalD
OelalD
OelalD
OctalD
Oelal D
OelalD
OelalD
OctalD
OelalD
Octal D
Oelal D
OelalD
OctatD
8-BiID
9-BitD
9-BitD
10-Bi1D
10-Bi1D
10-BitD
Device
54AC/74AC74
54ACT/74ACT74
54AC/74AC109
54ACT /7 4ACT1 09
54AC/74AC174
54ACT /7 4ACT174
54AC/74AC175
54ACT/74ACT175
54AC/74AC273
54ACT/74ACTQ273
54FCT /7 4FCT273
54FCT/74FCT273A
54AC/7 4AC374
54ACT/7 4ACT374
54ACQ/74ACQ374
54ACTQ/74ACT037 4
54FCT/7 4FCT374
54FCT/74FCT374A
54AC/74AC377
54ACT/7 4ACT377
54ACQ/74ACQ377
54ACTQ/7 4ACT0377
54FCT/7 4FCT377
54FCT/74FCT377A
54ACT /7 4ACT534
54ACQ/74ACQ534
54ACTQ/7 4ACT0534
54FCT/7 4FCT534
54FCT/7 4FCT534A
54ACT/7 4ACT564
54ACQ/74ACQ564
54ACTQ/74ACTQ564
54FCT/7 4FCT564
54FCT/7 4FCT564A
54AC/74AC57 4
54ACT/74ACT574
54ACQ/74ACQ574
54ACTQ/74ACTQ574
54FCT /7 4FCT574
54FCT/74FCT574A
54ACT174ACT825
54FCT/74FCT825A/B
54ACT/7 4ACT823
54FCT/74FCT823A/B
54ACT/7 4ACT821
54ACQ/74ACQ821
54FCT/74FCT821A/B
TRI·STATEI!)
Outputs
Nlaster
Rept
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
xiv
il!
Latches
Function
Device
TRI-STATE
Outputs
Broadside
Pinout
Octal
Octal
Octal Transparent
Octal Transparent
Octal Transparent
Octal Transparent
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal 0
Octal Transparent
8-Bit Transparent
9-Bit Transparent
9-Bit Transparent
9-Bit Transparent
9-Bit Transparent
1O-Bit Transparent
1O-Bit Transparent
1O-Bit Transparent
54AC/74AC373
54ACT /7 4ACT373
54ACQ/74ACQ373
54ACTQ/7 4ACTQ373
54FCT/7 4FCT373
54FCT174FCT373A
54ACQ/74ACQ533
54ACTQ/74ACTQ533
54FCT/74FCT533
54FCT/7 4FCT533A
54ACT /7 4ACT563
54ACQ/74ACQ563
54ACTQ/7 4ACTQ563
54FCT /7 4FCT563
54FCT/7 4FCT563A
54AC/74AC573
54ACT/7 4ACT573
54ACQ/7 4ACQ573
54ACTQ/74ACTQ573
54FCT 174FCT573
54FCT/74FCT573A
54ACT/7 4ACT845
54FCT/74FCT845A/B
54AC/74AC843
54ACT/7 4ACT843
54ACTQ/74ACTQ843
54FCT/74FCTQ843A/B
54ACT /7 4ACT841
54FCT/74FCT841AlB
54ACTQ/74ACTQ841
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Counters
S
A
Function
Device
4-Bit Binary
4-Bit Binary
4-Bit Binary
4-Bit Binary
4-Bit Binary
4-Bit Binary
4-Bit Binary
54AC/74AC161
54ACT/74ACT161
54AC/74AC163
54ACT/7 4ACT163
54AC/74AC169
54ACT/7 4ACT169
54AC/74AC191
Parallel
Entry
S
S
S
S
S
S
Reset
UfO
TRI-STATE
Outputs
A
A
No
No
No
No
No
No
No
No
No
No
No
S
S
-
-
A
= Synchronous
= Asynchronous
xv
Yes
Yes
Yes
~
en
CD
CD
n
:::!:
0
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c
a:
CD
Buffers/Line Drivers
Function
Quad
Quad
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Hex
Hex
Octal
Octal
Octal
Octal
10-Bit
10-Blt
Device
Enable
Inputs
(Level)
54AC174AC125
54ACT174ACT125
54AC174AC240
54ACT17 4ACT240
54ACQ174ACQ240
54ACTQ/74ACTQ240
54FCT174FCT240
54FCT/74FCT240A
54AC174AC241
54ACT174ACT241
54ACQ174ACQ241
54ACTQ174ACTQ241
54FCT 174FCT241
54FCT/74FCT241A
54AC17 4AC244
54ACT 174ACT244
54ACQ/74ACQ244
54ACTQ174ACTQ244
54FCT174FCT244
54FCT 174FCT244A
54ACT174ACT367
54ACT 174ACT368
54AC/74AC540
54FCT540
54AC17 4AC541
54FCT541
54ACTQ174ACTQ827
54FCT/74FCT827A/B
l(L)
l(L)
2(L)
2(L)
2(L)
2(L)
2(L)
2(L)
l(H) & 1(L)
l(H) & l(L)
l(H)& l(L)
1(H)& l(L)
l(H)& l(L)
l(H)& l(L)
2(L)
2(L)
2(L)
2(L)
2(L)
2(L)
1(L)
1(L)
2(L)
2(L)
l(H)& 1(L)
l(H) & l(L)
2(L)
2(L)
Invertlngl
Non-Inverting
Broadside
Pinout
N
N
I
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
I
I
I
I
I
N
N
N
N
N
N
N
N
N
N
N
N
N
I
I
I
N
N
N
N
L= LOW
H = HIGH
FIFOs
Function
Device
Input
Output
64 x 9 FIFO Memory
64 x 9 FIFO MemQry
512 x 9 FIFO Memory
512 x 9 Bidirectional
FIFO Memory
54AC174AC270B
54ACT 174ACT2708
54ACT174ACT2725
54ACT 174ACT2726
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
TRI-STATE
Outputs
Yes
Yes'
Yes
Yes
Decoders/Demultiplexers
Function
Device
LOW
Enable
ActiveHIGH
Enable
ActiveLOW
Outputs
ActiveAddress
Inputs
1-of-8
1-of-8
1-of-8
1-of-8
DuaI1-of-4
Duall-of-4
54AC/74AC138
54ACT174ACT138
54FCT 174FCT138
54FCT/74FCT138A
54AC174AC139
54ACT174ACT139
2
2
2
2
1& 1
1& 1
1
1
1
1
No
No
8
8
8
8
4&4
4&4
3
3
3
3
2&2
2&2
xvi
~
Arithmetic Functions
en
CD
Function
Device
Features
16 x 16 Multiplier
Arithmetic Logic Unit for DSP
54ACT174ACT1016
54ACT174ACT705
2s Complement & Unsigned Arithmetic
16-Bit ALU and a x a Parallel
Multiplier/Accumulator
a:
CD
Function
Device
Features
Video Sync Generator
54ACT174ACT715
High Speed, Programmable Video
Signal Generation
Shift Registers
Function
Device
Octal Shift/Storage
Octal Shift/Storage
Octal Shift/Storage
Octal Shift/Storage
54AC174AC299
54ACT 174ACT299
54AC174AC323
54ACT /7 4ACT323
No. of
Bits
Reset
Serial
Inputs
TRI-STATE
Outputs
A
A
S
S
2
2
2
2
Yes
Yes
Yes
Yes
a
a
a
a
A = Asynchronous
S = Synchronous
Multiplexers
Device
a-Input
a-Input
a-Input
a-Input
Dual4-lnput
Dual4-lnput
Dual 4-lnput
Dual 4-lnput
Dual4-lnput
Quad 2-lnput
Quad 2-lnput
Quad 2-lnput
Quad 2-lnput
Quad 2-lnput
Quad 2-lnput
Quad 2-lnput
Quad 2-lnput
::::I
G)
C
Video Support
Function
tD
n
O·
54AC174AC151
54ACT174ACT151
54AC174AC251
54ACT174ACT251
54AC/74AC153
54ACT 17 4ACT153
54ACTQ174ACT0153
54AC174AC253
54ACT /7 4ACT253
54AC17 4AC157
54ACT /7 4ACT157
54AC174AC15a
54ACT174ACT15a
54AC/74AC257
54ACT174ACT257
54AC/74AC25a
54ACT174ACT25a
Enable
Inputs
(Level)
True
Output
Complement
Output
l(L)
l(L)
l(L)
l(L)
2(L)
2(L)
2(L)
2(L)
2(L)
l(L)
l(L)
l(L)
l(L)
l(L)
l(L)
l(L)
l(L)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
Yes
Yes
No
No
Yes
Yes
Comparators
Function
Device
Features
Octal Identity Comparator
Octal Identity Comparator
Octal Identity Comparator
Octal Identity Comparator
Octal Identity Comparator
Octal Identity Comparator
54AC174AC520
54ACT /7 4ACT520
54AC174AC521
54ACT/74ACT521
54FCT17 4FCT521
54FCT174FCT521A
Expandable
Expandable
Expandable
Expandable
Expandable
Expandable
xvii
Transceivers/Registered Transceivers
Function
Device
Registered
Octal Bidirectional Transceiver
Octal Bidirectional Transceiver
Octal Bidirectional Transceiver
Octal Bidirectional Transceiver
Octal Bidirectional Transceiver
Octal Bidirectional Transceiver
Octal Bus Transceiver and Register
Octal Bus Transceiver and Register
Octal Bus Transceiver and Register
Octal Bus Transceiver and Register
Octal Bus Transceiver and Register
Octal Bus Transceiver and Register
Octal Bus Transceiver and Register
Octal Registered Transceiver
Octal Registered Transceiver
Octal Registered Transceiver
Octal Registered Transceiver
Octal Registered Transceiver
Octal Registered Transceiver
Octal Registered Transceiver
Octal Registered Transceiver
Octal Bus Transceiver
Octal Bus Bidirectional
Transceiver wI Parity
9-Bit Registered w/Parity
9-Bit Registered wI Parity
9-Bit Registered wI Parity
54AC174AC245
54ACT174ACT245
54ACQ174ACQ245
54ACTQ174ACTQ245
54FCT17 4FCT245
54FCT17 4FCT245A
54AC17 4AC646
54ACT174ACT646
54ACQ/74ACQ646
54ACTQ17 4ACTQ646
54FCT17 4FCT646
54FCT174FCT646A
54AC174AC648
54ACQ/74ACQ543
54ACT174ACTQ543
54FCT174FCT543
54FCT174FCT543A
54ACQ174ACQ544
54ACT174ACTQ544
54FCT174FCT544
54FCT174FCT544A
54ACTQ174ACTQ657
54FCT174FCT657
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
54ACQ/74AC899
54ACTQ17 4ACT899
54FCT174FCT899
Enable
Inputs
(Level)
TRI-5TATE
Output
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
1(L)
1(L)
1(L)
1(L)
1(L)
1(L)
1(L)& 1(H)
1(L) & 1(H)
1(L) & 1(H)
1(L) & 1(H)
1(L) & 1(H)
1(L) & 1(H)
1(L) & 1(H)
2(L)
2(L)
2(L)
2(L)
2(L)
2(L)
2(L)
2(L)
1(L) & 1(H)
1(L) & 1(H)
Yes
Yes
Yes
1 (L) & 1 (H)
1 (L)& 1 (H)
1 (L)& 1 (H)
Yes
Yes
Yes
Yes
Clock Drivers
Function
Device
Multiplexed
Clock
1 to 8 Minimum Skew Clock Driver
1 to 8 Minimum Skew Clock Driver
54AC/74AC2525
54AC/74AC2526
No
Yes
xviii
Section 1
Descriptions and
family Characteristics
Section 1 Contents
Introduction ........................................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power CMOS Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Performance ...................................................................
Multiple Output Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Immunity ....................................................................
Output Characteristics ..............................................................
Dynamic Output Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Choice of Voltage Specifications .....................................................
Power Dissipation ..................................................................
Specification Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitive Loading Effects..........................................................
Latch-Up Immunity... .. .. ...... ... .... .. .. . ..... ...... .. . . .. .. . ............... . .. ..
Electrostatic Discharge (ESD) Sensitivity..............................................
Radiation Tolerance..... . ... ............ .. .... ... .... .... ...... ..... .. .. . . .. .. .....
1·2
1-3
1-3
1-5
1-5
1-5
1-5
1-5
1-9
1-10
1-13
1-15
1-18
1-18
1-20
~
~National
~ Semiconductor
C
(I)
III
....
(')
FACTTM Descriptions and Family Charactel"ustics
-
-6"
0"
::s
III
I»
::s
c..
"T1
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National Semiconductor Advanced
CMOS Technology-FACT-Logic
1/1 Operation from 2V-6V Voo Guaranteed (,ACI'ACO)
Temperature Range
-40'C to +85'C
- Commercial
-Military
- 55'C to + 125'C
EI Improved ESD Protection Network
iii High Current Latch-Up Immunity
III Patented Noise Suppression Circuitry on ACO/ACTO
and FCT/FCTA
II
Fairchild Semiconductor introduced FACT (Fairchild Advanced CMOS Technology) logic, a family of high speed
advanced CMOS circuits, in 1985.
FACT logic offers a unique combination of high speed, low
power dissipation, high noise immunity, wide fanout capability, extended power supply range and high reliability.
This data book describes the product line with device specifications as well as material discussing design considerations and comparing the FACT family to predecessor technologies.
FACT devices have a wide operating voltage range (Voo =
2 Voc to 6 Voc, 'AC/'ACO) and sufficient current drive to
interface with most other logic families available today.
Device designators are as follows:
'AC/'ACO - These are high speed CMOS devices with
CMOS input switching levels and buffered
CMOS outputs that can drive ± 24 rnA of
IOH and IOL current. Industry standard 'AC/
'ACO nomenclature and pinouts are used.
'ACT /'ACTO - These are high speed CMOS devices with a
'FCT /'FCTA
TTL-to-CMOS input buffer stage. These device inputs are designed to interface with
TTL outputs operating with a Voo = 5V
±0.5V with VOH = 2AV and VOL = OAV,
but are functional over the entire FACT operating voltage range of 2.0 Voc to 5.5
Voc. These devices have buffered outputs
devices with no
that will drive CMOS or
additional interface circuitry. 'ACT /' ACTO
devices have the same output structures as
'AC/'ACO devices. 'FCT/'FCTA can drive
+ 64 rnA of IOL and -15 rnA of IOH current.
TTL
Characteristics
Low Power CMOS Operation
• Full Logic Product Line
• Industry Standard Functions and Pinouts for SSI, MSI
and LSI
• Meets or Exceeds JEDEC Standards for 74ACXX
Family
• TTL Inputs on Selected Circuits
• High Performance Outputs
- Common Output Structure for Standard Gates and
Buffer/Drivers
- Output Sink/Source Current of 24 rnA on AC/ ACT
and ACO/ ACTO
- Output Sink/Source Current of 48/64 rnA on
FCT/FCTA
- Transmission Line Driving 500 (Commercial)1750
(Military) Guaranteed
If there is one single characteristic that justifies the existence of CMOS, it is low power dissipation. In the quiescent
state, FACT draws 1000 times less power than the equivalent LS or ALS TTL device. This enhances system reliability;
because costly regulated high current power supplies, heat
sinks and fans are eliminated, FACT logic devices are ideal
for portable systems such as laptop computers and backpack communications systems. Operating power is also
very low for FACT logiC. Power consumption of various
technologies with a clock frequency of 1 MHz is shown below.
FACT
ALS
LS
HC
1-3
= 0.1 mW/Gate
= 1.2mW/Gate
= 2.0 mW/Gate
= 0.1 mW/Gate
o
::r
I»
iil
~
....
(I)
iii"
(;"
III
Interfacing
The 1.3-micron silicon gate CMOS process utilized in this
family has been proven in the field of high performance gate
arrays, CMOS ASIC, and FACT. It has been further enhanced to meet and exceed the JEDEC standards for
74ACXX logic.
In 1989, National Semiconductor introduced the FACT Ouiet Series™ product line. This line of mostly octal bus-oriented logic functions is an enhancement of the original FACT
line. Manufactured on a sub-micron silicon gate CMOS process, the FACT OS devices offer the lowest noise characteristics of any Advanced CMOS process with AC performance that is faster than FACT.
Also in 1989, National Semiconductor introduced its offering
of fast CMOS technology or FACT FCT/FCTA. These product lines offer the fastest speeds of any TTL or CMOS logic,
high DC output current drive, as well as the low noise design
innovations of FACT OS.
For direct replacement of LS, ALS and other TTL devices,
the 'ACT, 'ACTO, 'FCT and 'FCTA circuits with TTL-type
input thresholds are included in the FACT family.
~"
-<
FACT Product Comparlslon
Feature
FACT ACQ/ACTQ
FACT AC/ACT
FACT FCT/FCTA
Dynamic line driving guaranteed to switch on
incident wave into transmission line impedance
as low as 500 at + 85°C; 750 at + 125°C
Yes
Yes
IOLD"OHO: ± 75 mA
IOLD"OHO: ± 75 mA
Guaranteed High Output Drive
IOl"OH: ±24 mA
IOl"OH: ± 24 mA
Very High Speed Frequency
1 ns Internal Gate Delay; ,;; 1 ns Internal Gate Delay; ,;; 1 ns Internal Gate Delay;
up to 200 MHz
up to 100 MHz
up to 100 MHz
Toggle Frequency
Toggle Frequency
Toggle Frequency
IOl: + 64 mA Commercial
(Buffers/Drivers)
+48 mA Military
IOH:-15mA
CMOS Power
5l£W/Gate
5l£W/Gate
CMOS Input Loading
±l1£A
±l1£A
±l1£A
Extended Operating Voltage Range
2.0Vto6.0V
2.0Vt06.0V
2.0Vt06.0V
DCI AC Characteristics Guaranteed
3Vand 5V ±10%
3Vand 5V ± 10%
5V ± 5% Commercial
5V ± 10% Military
Excellent Symmetrical Noise Margin (CMOS
Inputs)
1.55V High; 1.55V Low
1.55V High; 1.55V Low
Dynamic Thresholds (TTL-Compatible Inputs)
Maximum 2.2V High
(VIHO); Minimum 0.8V
Low (VllO)
Guaranteed Latchup Immunity
±100mAat + 125°C
±300 mA at + 125°C
ESD Immunity
MIL Class 2 (2,000V 3,999V); Typical6,000V
MIL Class 2 (2,000V 3,999V); Typical6,000V
Pin-to-Pin Output Propagation Delay Skew
(Maximum)
Wafer Fabrication
51£WGate
Maximum 2.2V High
(VIHO); Minimum 0.8V
Low (VllO)
MIL Class 3 (4,000V
or Greater); Typical6,000V
1.0 ns (tas); Typical 0.5 ns
JAN Class S
DESC Certified
Guaranteed Output Noise Levels
(Maximum)
1.5V VOlP (ground
Bounce); -1.2VVOlV
(Undershoot)
FCTA: -1.2VVOlV
(Undershoot)
FCT: 2.0V VOlP
(Ground Bounce)
-1.2VVOlV
(Undershoot)
Driving Force for JEDEC Standard for Advanced Yes
CMOS
Inherently Radiation Tolerant
Yes
Yes
Inputs Compatible with: CMOS
TIL
AC
ACT
ACO
ACTO
FCT, FCTA
Ful Compatibility (Function, Part Number,
Pinout) with Standard 54/74 Functions
Yes
Yes (;;,8 Bits)
Yes (;;'8 Bits)
1-4
Yes
Low Power CMOS
Operation (Continued)
Noise Immunity
The DC noise immunity of a logic family is also an important
equipment cost factor in terms of decoupling components,
power supply dynamiC resistance and regulation as well as
layout rules for PC boards and signal cables.
500
CL = 50 pF
400
-:c
.3
@
The comparisons shown describe the difference between
the input threshold of a device and the output voltage,
IViL - VoLi/IViH - vOHI at 4.5V Voo·
1 MHz
300
Q
FACT
ALS
LS
HC
.Iii'
200
100
=
=
=
=
1.25V/1.25V
0.4V/0.7V
0.3V/0.7V @ 4.75V Voo
0.8V/1.25V
0
0
Output Characteristics
246
VDD (Volts)
All FACT outputs are buffered to ensure consistent output
voltage and current speCifications across the family. Both
'AC/'ACO and 'ACTI'ACTO device types have the same
output structures. Two clamp diodes are internally connected to the output pin to suppress voltage overshoot and undershoot in noisy system applications which can result from
impedance mismatching. The balanced output design allows for controlled edge rates and equal rise and fall times.
All SSI and MSI devices ('AC, 'ACT, 'ACO or 'ACTO) are
guaranteed to source and sink 24 rnA. FACT FCT and FACT
FCTA are guaranteed to sink 64 rnA (comm)/4B rnA (mil)
and source 15 rnA (comm)/12 rnA (mil). Commercial devices, 74AC/ ACTXXX, are capable of driving 50n transmission
lines, while military grade devices, 54AC/ ACTXXX, can
drive 75n transmission lines.
TLlF/10158-1
FIGURE 1-1. 100 vs Voo
Figure 1-1 illustrates the effects of 100 versus power supply
voltage (Voo) for two load capacitance values: 50 pF and
stray capacitance. The clock frequency was 1 MHz for the
measurements.
AC Performance
In comparison to LS, ALS and HC families, FACT devices
have faster internal gate delays as well as the basic gate
delays. Additionally, as the level of integration increases,
FACT logic leads the way to very high-speed systems.
The examples below describe typical values for a 74XX138,
3-to-8 line decoder and a 74xx244 line driver.
IOL/10H Characteristics
'138
FACTAC
ALS
LS
HC
= 6.0 ns @CL =
= 12.0 ns @CL =
= 22.0 ns @CL =
= 17.5 ns @CL =
50 pF
50 pF
15 pF
50 pF
FACT AC/ACT
= 24 mAl-24 rnA
FACT ACO/ACTO = 24 mAl-24 rnA
FACT FCT/FCTA = 64 mAl-15 rnA
= 24 mAl-15 rnA
= B mAl-0.4 rnA @ 4.75V Voo
ALS
LS
'244
FACT FCTA
FACT ACO
FACTAC
ALS
LS
HC
HC
3.0 ns @CL
4.0 ns @ CL
5.0 ns @CL
7.0 ns@CL
= 12.0 ns@ CL
= 14.0 ns @CL
= 50 pF
= 50 pF
= 50 pF
= 50pF
= 45 pF
= 50 pF
=4 mAl-4 rnA
Dynamic Output Drive
Traditionally, in order to predict what incident wave voltages
would occur in a system, the designer was required to do an
output analysiS using a Bergeron diagram. Not only is this a
long and time consuming operation, but the designer needed to depend upon the accuracy and reliability of the manufacturer-supplied "typical" output IIV curve. Additionally,
there was no way to guarantee that any supplied device
would meet these "typical" performance values across the
operating voltage and temperature limits. Fortunately for the
system deSigners, FACT has taken the necessary steps to
guarantee incident wave switching on transmission lines
with impedances as low as 50n for the commercial temperature range and 75n for the military temperature range.
AC performance specifications are guaranteed at 5.0V
±0.5V and 3.3V ±0.3V. For worst case design at 2.0V Voo
on all device types, the formula below can be used to determine AC performance.
AC performance at 2.0V Voo = 1.9 X AC specification at
3.3V.
Multiple Output Switching
Propagation delay is affected by the number of outputs
switching simultaneously. Typically, devices with more than
one output will follow the rule: for each output switching,
derate the databook specification by 250 ps. This effect typically is not significant on an octal device unless more than
four outputs are switching simultaneously. This derating is
valid for the entire temperature range and 5.0V ± 10% Voo.
Figure 1-2 shows a Bergeron diagram for switching both
HIGH-to-LOW and LOW-to-HIGH. On the right side of the
graph (lOUT> 0), are the VOH and IIH curves for FACT logic
while on the left side (lOUT < 0), are the curves for VOL and
IlL. Although we will only discuss here the LOW-to-HIGH
transition, the information presented may be applied to a
HIGH-to-LOW transition.
1-5
II
o
U
:;;
.;:
r------------------------------------------------------------------------------------------,
Dynamic Output Drive
~
CI:I
5
~
4
o
'CI
C
CI:I
.
""
~
3
0
2
>
o
o
-1
.;:
-2
6
=-SOD.
5
"
HIGH·to·LOW ,..
,
Line 11-- ~OH/IOH
VOJIOL
, Slope=50.n/
"---
-0.1
'.Jt
----
o
,
4
'\
,,
...
rt-....
, , ... LOW·to·HIGH II
"
~
3
~
2
..
I
I
I
I
I
I
I
I
r-.-
I
0
- - RECEIVER
----- DRIVER
-1
0.2
0.1
50 100 150 200 2SO 300 350 400 450
Current (A)
Q
~
Line 2
• Slope
t"':::..:' .......
-0.2
m
1\
••
0
C
a
-........... .
7
,
VIN/IIN
6
.c
'E
Lf
(Continued)
7
TIme (ns)
TL/F/1015B-2
FIGURE 1-2. Gate Driving 500 Line
Reflection Diagram
TLlF/1015B-4
FIGURE 1-3b. Resultant Waveforms Driving
500 Line-Actual
.
Begin analysis at the VOL (quiescent) pOint. This is the inter·
section of the VOLliOL curve for the output and the VINlilN
curve for the input. For CMOS inputs and outputs, this point
will be approximately 100 mV. Then .draw a 500 load line
from this intersection to the VOHliOH curve as shown by
Line 1. This intersection is the voltage that the incident
wave will have. Here it occurs at approximately 3.95V. Then
draw a line with a slope of -500 from this first intersection
point to the VINlilN curve as shown by Line 2. This second
intersection will be the first reflection back from the input
gate. Continue this process of drawing the load lines from
each intersection to the next. Lines terminating on the
VOH"OH curve should have positive slopes while lines ter·
minating on the VINlilN curve should have negative slopes.
7
~
3
,l!
2
:It
o
-1
-1 0 1 2 3 4 5 6 7 8 9 10 11
Time (1 Propagation Dolay/Dlv)
TLlF/1015B-5
FIGURE 1-3c. Resultant Waveforms Driving
500 Line-Theoretical
Figures 1·3a thru 1-3d show the resultant waveforms. Each
division on the time scale represents the propagation delay
of the transmission line.
7
7
6
6
5
5
4
r-
~
3
~
2
II
II
II
I
I
0
-1
I
I
I
I
I
I
I
I
I
&.-
4
Each intersection point predic1s the voltage of each reflect·
ed wave on the transmission line. Intersection pOints on the
VOHliOH curve will be waves travelling from the driver to the
receiver while intersec1ion points on the VINlilN curve will
be waves travelling from the receiver to the driver.
1
- - RECEIVER
----- DRIVER
6
5
4
I
VZR 0
- - RECEIVER
----- DRIVER
I
I
I
I
I
~
3
I
~
2
I
I
I
I
..
I
- - RECEIVER
----- DRIVER
I
0
-1
-1 0 1 2 3 4 5 6 7 8 9 10 11
TIme (1 Propagation Delay /Dlv)
50 100 150 200 250 300 350 400 450
TL/F/1015B-3
TIme (ns)
FIGURE 1-3a. Resultant Waveforms Driving
500 Line-Theoretical
TLlF/1015B-6
FIGURE 1-3d. Resultant Waveforms Driving
500 Line-Actual
1·6
Dynamic Output Drive (Continued)
While this exercise can be done for FACT, it is no longer
necessary. FACT is guaranteed to drive an incident wave of
enough voltage to switch another FACT input.
7
r Voo =5.0V
Voo~
We can calculate what current is required by looking at the
Bergeron diagram. The quiescent voltage on the line will be
within 100 mV of either rail. We know what voltage is required to guarantee a valid voltage at the receiver. This is
either 70% or 30% of Voo. The formula for calculating the
current and voltage required is I(VOQ - VI)/Zoi at VI. For
VOQ = 100 mY, VIH = 3.85V, Voo = 5.5V and Zo = 50n,
the required IOH at 3.85V is 75 mA. For the HIGH-to-LOW
transition, VOQ = 5AV, VIL = 1.65V and Zo = 50n, IOL is
75 mA at 1.65V. FACT's 1/0 specifications include these
limits. For transmission lines with impedances greater than
50n, the current requirements are less and switching is still
guaranteed.
5
4
Voo
~
F=:>
=
4.5V
~
"""""' \\,'r\'\.
\
,
r-..
\
1
o
1\
1
-2
o
It is important to note that the typical 24 mA DC drive specification is not adequate to guarantee incident wave switching. The only way to guarantee this is to guarantee the current required to switch a transmission line from the output
quiescent point to the valid VIN level.
-120
-80
Current (rnA)
-40
-160
-200
TL/F/1015B-29
FIGURE 1-4b. Output Characteristics
VOH/IOH, 'ACTQ244
The following performance charts are provided in order to
aid the designer in determining dynamic output current drive
of FACT devices with various power supply voltages.
7
6 Voo = 5.5V
Voo"'!, 5.0V
7
5
Voo
5
--..:
= 5.5V
Voo..: 5.~
4 Voo = 4.5V
~ 3
...'"
'">
0
2
4
~
3
~"-.. ~
.......
'\. '\ '\
2
\ \ 1\
\ \ \
0
-50
-100
r\.
~" 1\\
o
-200
-150
"
\ \1
o
o
"
t'.....
1
-I
-2
oo
V "
-40
\\
-80
-120
Current (rnA)
-160
-200
TL/F/1015B-30
FIGURE 1-4c. Output Characteristics
VOH/lOH, 'FCT244A
Current (rnA)
TL/F/1015B-7
FIGURE 1-4a. Output Characteristics
VOH/IOH, 'ACOO
1-7
•
Dynamic Output Drive (Continued)
7
7
I-
Voo
= 5.5V
VOO = 5.0V
VOO
,
\.
\.
.....
200
f- Voo - 5.5V
6
5
= 4.5V
-'
--
150
Voo
5
4
4
3
3
\.
2
--..
6
= 5.0V I
Voo = 4.5V
2
,~
--..:: ~
o
o
50
-2
300
200
100
0
TUF/l0158-28
FIGURE 1-5a. Output Characteristics VOl/IOl, 'ACOO
FIGURE 1-5c. Output Characteristics VOl/IOl, 'FCT244A
7
\
\
VDD
6
= 5.0V
V,6 = 4.5V
4
\ \
I",
3
\
2
-
~
5
5
.
~
..'"
~
:'"
~
""~
160
120
80
4
3
2
0
~
-1
0
-2
-0.2
-1
200
= 5.0V. TA = 25"C
7
VDD
\
-2
Current (mA)
TL/F/l0158-8
I
'"
-1
Current (rnA)
1.
Voo = 5.5V
•
~
0
-1
100
~
40
0
-0.1
o
D.2
0.1
Current (rnA)
-2
TL/Fi10158-9
FIGURE 1-6. Input Characteristics VIN/IIN
Current (rnA)
TUF/l0158-27
FIGURE 1-5b. Output Characteristics
VOl/IOl, 'ACTQ244 .
1-8
Choice of Voltage Specifications
FACT Replaces Existing Logic
To obtain better performance and higher density, semiconductor technologies are reducing the vertical and horizontal
dimensions of integrated device structures. Due to a number of electrical limitations in the manufacture of VLSI devices and the need for low voltage operation in memory cards,
it was decided by the JEDEC committee to establish interface standards for devices operating at 3.3V ± 0.3V. To this
end, National Semiconductor guarantees all of its devices
operational at 3.3V ± 0.3V. Note also that AC and DC specifications are guaranteed between 3.0V and 5.5V. Operation
of FACT logic is also guaranteed from 2.0V to 6.0V
'AC/'ACO on VDD.
National Semiconductor's Advanced CMOS family is specifically designed to outperform existing CMOS and Bipolar
logic families. Figure 1-7 shows the relative position of various logic families in speed/power performance. FACT exhibits 1 ns internal propagation delays while consuming
1 /LW of power.
The Logic Family Comparisons table below summarizes the
key performance specifications for various competitive technology logic families.
10
....
..s
Operating Voltage Ranges
FACT
FACT
FACT
ALS
LS
HC
=
=
=
=
=
=
SPEED VS. POWER
8
6
~
2.0V to 6.0V (,AC/'ACO)
5.0V ±10% ('ACT/'ACTO)
5.0V ±5% (,FCTI'FCTA)
5.0V ±10%
5.0V ±5%
2.0V to 6.0V
e LS
eHC
>.
.!!
~
4
'iii
E
:§
eALS
2
eFAST
: ~:g QS/FAcN~ST LSI
0.001
0.3
10.0
3.0
1.0
eAS
Power Per Gat. (mW)
(Not to scale)
TL/F/1015B-10
FIGURE 1·7_ Internal Gate Delays
General Characteristics (All Max Ratings)
Symbol
Characteristics
ALS
FACT
HCMOS
'ACI'ACa
VCC/EE/DD Operating Voltage Range
TA 74 Series Operating
TA 54 Series Temperature Range
VIH(Min)
VIL(Max)
VOH(Min)
VOL (Max)
5 ±10%
5 ±10%
5 ±5%
5 ±10%
5 ±5%
V
-40 to +B5
-55to +125
-40 to +85
-55to +125
-40to+85
-55to +125
Oto +70
-55to +125
·C
V
Input Voltage
(Limits)
Output Voltage
(Limits)
IlL
Output Current
at Vo (Limit)
IOH
IOL
DCM
'FCT/'FCTA
Oto +70
-55 to +125
Input Current
IIH
Units
'ACT/'ACTa
DC Noise Margin
LOW/HIGH (VDD = 4.5V)
2.0
3.15
3.85
2.0
2.0
0.8
0.9
1.65
0.8
0.8
V
2.7
VDD - 0.1
VDD-O.l
VDD - 0.1
VDD - 0.2
V
0.5
0.1
0.1
0.1
0.2
V
20
+1.0
+1.0
+1.0
+5.0
/LA
-200
-1.0
-1.0
-1.0
-5.0
/LA
-0.4
-4.0@VDD - 0.8 -24 @ VDD - 0.8 -24 @VDD - 0.8 -15 mA@2.4V mA
B.O
4.0@0.4V
24@0.44V
24@0.44V
64mA@0.5V
mA
0.4/0.7
0.8/1.25
1.25/1.25
0.7/2.4
0.6/2.3
V
Note: All DC parameters are specified over the commercial temperature range.
Speed/Power Characteristics (All Typical Ratings)
Symbol
Characteristics
ALS
HCMOS
FACTAC
FACT FCTA
IG
Ouiescent Supply Current/Gate
0.2
0.0005
0.0005
0.0005
mA
PG
Power/Gate (Ouiescent)
1.2
0.0025
0.0025
0.0025
mW
Propagation Delay (,244 Typ.)
7.0
14.0
5.0
3.0
ns
Speed Power Product
8.4
0.04
0.01
0.008
pJ
50
50
160
225
MHz
tpd
f max
Clock Frequency D/FF
FIGURE l·B. Logic Family Comparisons
1-9
Units
Propagation Delay (Commercial Temperature Range)
Symbol
Product
tplH/tpHl
74XXOO
tplH/tpHl
(Clock to Q)
74XX74
tplH/tpHl
(Clock to Q)
74XX163
LS
ALS
HCMOS
FACT
Typ
.10.0
5.0
8.0
5.0
ns
Max
-
11.0
23.0
8.5
ns
Typ
30.0
12.0
12.0
8.0
ns
-
Max
Conditions: (LS) Voo ~ 5.0V, CL
(ALS/HC/FACT) Voo
~
~
Units
18.0
44.0
10.5
ns
Typ
27.0
10.0
20.0
5.0
ns
Max
-
20.0
52.0
10.0
ns
15 pF, 25'C;
5.0V ± 10%, CL ~ 50 pF, Over Temp, Max values at O'C to +70"C for ALS, -40"C to +85'C for HC/FACT.
FIGURE 1-8. Logic Family Comparisons (Continued)
Circuit Characteristics
POWER DISSIPATION
Eq. 2B (ACT/ACTO)
One advantage to using CMOS logic is its extremely low
power consumption. During quiescent conditions, FACT will
consume several orders of magnitude less current than its
bipolar counterparts. But DC power consumption is not the
whole picture. Any circuit will have AC power consumption,
whether it is built with CMOS or bipolar technologies.
PDINT
[ (CPO • Vs • f) .Vool
PDINT = Internal Dynamic Power Dissipation
lOOT = Power Supply Current for a TTL HIGH
Input (VIN = 3.4V)
DH
= Duty Cycle for TTL Inputs HIGH
NT
= Number of TTL Inputs at DH
VOO = Power Supply Voltage
CPO = Device Power Dissipation Capacitance
Vs
= Output Voltage Swing
f
= Internal Frequency of Operation
Total power dissipation of FACT device under AC conditions
is a function of three basic sources, quiescent power, internal dynamic power, and output dynamic power dissipation.
Firstly, a FACT device will dissipate power in the quiescent
or static condition. This can be calculated by using the formula: (Note: In many datasheets 100, 6.100, lOOT, and Voo
are referred to as Icc, 6.lcc, ICCT' and Vcc, respectively.
There are no differences.)
Eq. 1
= [(lOOT· DH • NT) • Vool +
Eq. 2C (FCT/FCTA)
POINT = [(6.100. DH • NT) • Vool + [(too· (fcp/2
+ fiN • NIN}) • Vool
PDINT = Internal Dynamic Power Dissipation
Voo = Power Supply Voltage
6.100 = Power Supply Current for a TTL HIGH
Input (VIN = 3.4V)
DH
= Duty Cycle for TTL Inputs HIGH
NT
= Number of TTL Inputs at DH
1000 = Dynamic Current Caused by an Input
Transition Pair (HLM or LHL)
fcp
= Clock Frequency for Registered Devices (Zero for Non-Registered Devices)
fiN
= Input Frequency
NIN
= Number of Inputs at fiN
PDQ = 100.- VOO
PDQ = Quiescent Power Dissipation
100 = Quiescent Power Supply Current Drain
VOO = Power Supply Voltage
Secondly, a FACT device will dissipate power dynamically
by charging and discharging internal capacitance. This can
be calculated by using one of the following two formulas:
Eq. 2A (AC/ ACQ)
PDINT = (CPO • Vs • f) • VOO
PDINT = Internal Dynamic Power
Dissipation
CpO = Device Power Dissipation
Capacitance·
= Output Voltage Swing
Vs
f
= Internal Frequency of
Operation
VOO = Power Supply Voltage
See Section 3 for more information on lOOT or 6.100.
Thirdly, a FACT device will dissipate power dynamically by
charging and discharging any load capacitance. This can be
calculated by using the following formula:
Eq. 3
CPO values are specified for each FACT device and are
measured per JEDEC standards as described later on in
Section 2. On FACT device data sheets, CPO is a typical
value and is given either for the package or for the individual
stages with the device. (See Section 2). For FACT devices,
Vs and Voo are the same value and can be replaced by
V002 in the above formula.
1-10
PDOUT =
PDOUT
Cl
Vs
f
Voo
(Cl • Vs • f) • Voo
Output Power Dissipation
= Load Capacitance
= Output Voltage Swing
= Output Operating Frequency
= Power Supply Voltage
=
In many cases the output frequency is the same as the internal operation frequency. Also Vs is similar to VOO and
can be replaced by V002. In the case of internal and output
frequencies beir,g identical Eq. 2A and Eq. 3 may be combined as follows:
The 100 calculations are as follows:
100 Total
+ Internal Switching 100
Switching (AC load) 100
= Input 100
Input 100
Eq.4 PD = (Cl + CPO) • V002 • f
The total FACT device power dissipation is the sum of the
quiescent power and all of the dynamic power dissipation.
This is best described as:
(lOOT)
Cycle)
(1.5
x
x
(number of TIL inputs)
+ Output
x
(Duty
x
(1)
x
(0.50)
= 3.36 per mA per input being toggled by CP
Output 100
(VSWING X (CLl x (Q freq)
a)Cl = 50 pF
= (5.0) x (50 x 10- 12) x (8
= 2 mA per output toggled at
b)Cl = 100 pF
= (5.0) x (100
The following assumptions have been made:
=
1.100 will be calculated per input/output (as per JEDEC
CPO calculations). The total for the ACTQ374 will be the
calculated 100 x 8.
x
10- 12)
x
10+ 6)
% CP
x (8 x
x
10- 12)
x
= 8 mA per output toggled at
10+ 6)
(8
x
10+ 6)
% CP
Adding Input, Internal and Output 100 together and multiplying by 81/0 per ACTQ374, the approximate worst-case 100
calculations are as follows:
3. The data and clock input signals are derived from TIL
level drivers (OV to 3.0V swing) at 50% duty cycle.
Cl =
4. The clock frequency is 16 MHz.
50 pF
100 total = 48.9 mA or 244.5 mW' at CP
Cl = 100 pF
100 total = 64.9 mA or 324.5 mW' at CP
CL = 150 pF
100 total = 96.9 mA or 484.5 mW' at CP
16 MHz
5. 100 will be calculated for Cl = 50 pF, 100 pF and 150 pF.
6. VOO = 5V.
7. Total POWER dissipation can be obtained by multiplying
total 100 by Voo (5.0V).
16 MHz
= 16 MHz
8. Quiescent 100 will be neglected in the total 100 calculation because it is 1000 times less than dynamic 100.
('Power is obtained by multiplying 100 by Voo)
9. There is no DC load on the outputs, i.e. outputs are either
unterminated or terminated with series or AC shunt termination.
1-11
0'
:::J
UI
II)
:::J
Q.
~
~,
-<
4 mA per output toggled at % CP
c) Cl = 150 pF
= (5.0) x (150
2. Worst case conditions and JEDEC would require that the
data is being toggled at the clock frequency in order to
change the outputs at the maximum rate (% CPl.
n
::::!,
10- 3)
Internal 100 = (VSWING) x (CPO) x (CP freq)
(5.0) x (42 x 10- 12) x (16 x 10+ 6)
PD-rOTAl = PDQ + PDOYNAMIC or
PD-rOTAl = PDQ + PDINT + PDOUT
The following is an exercise in calculating total dynamic 100
for the FACT Advanced CMOS family. The device used as
an example is the ACTQ374. Static 100, lOOT and CPO numbers can be found in the ACTQ374 data sheet. 100 numbers
used will be worst-case commercial guarantees. Room temperature power will be less. These are approximate worstcase calculations.
CD
UI
'0
0.75 mA per input being toggled at TIL levels
Eq. 5
~
C
o
:::T
II)
~
....CD
-fl'
iii'
o
Co)
tl
'':::
~
r---------------------------------------------------------------------------------,
Circuit Characteristics (Continued)
Voo
E
III
.c
o
~
SET
'E
III
LL
"C
I:::
III
SET
a
'74
'74
ClK
ClR
ClK
ClR
ClR
ClR
o
I:::
o
:;:;
c..
'':::
Co)
oQ)
C
I-
o
~
TL/F/101SB"11
FIGURE 1·9, Power Demonstration Circuit Schematic
mW
The circuit shown in Figure 1·9 was used to compare the
power consumption of FACT versus FAST devices.
Two identical circuits were built on the same board and driven from the same input. In .the circuit, the input signal was
driven into four D-type flip-flops which act as divide-by-2
frequency dividers. The outputs from the flip-flops were connected to the inputs of a '138 decoder. This generated eight
non-overlapping clock pulses on the outputs of the '138,
which were then connected to an '04 inverter. The input
frequency was then varied and the power consumption was
measured. Figure 1-10 illustrates the results of these measurements.
450
400
350
300
250
200
V
/'
V
/
V
,/'
/'
/'
150
100
50
..,/
~
>"V
/
V V
..,/
o
o
10
20
30
40
50
60
70
80
MHz
TL/F/101SB-12
FIGURE 1·10, FACT vs FAST Circuit Power
1-12
Circuit Characteristics (Continued)
The FACT circuit dissipates much less power than the FAST
version. It is interesting to note that when the frequency
went to zero, the FACT circuit's power consumption also
went to zero; the FAST circuit continued to dissipate 200
mW.
~
8
vOO = s.ov
7
C
tD
til
6
n
....
s
r-
At first glance, the specifications for FACT logic might appear to be widely spread, possibly indicating wide design
margins are required. However, several effects are reflected
in each specification.
Figures 1-11a through 1-11iillustrate how the data from the
characterization of actual devices is transformed into the
specifications that appear on the data sheet. This data is
taken from the 'XX244.
Figure 1-11a shows the data taken (from one part) on a
typical, single path, tpHL, over temperature at 5.0V; there is
negligible variation in the value of tpHL' The next set of
graphs, Figure 1-11b through 1-11d, depict data taken on
the same device; these sets of curves represents the data
on all paths. The data on this plot indicates only a small
variation for tpHL.
The graphs in Figures 1-11a-dinclude data at 5.0V; Figure
1-11e shows the variation of delay times over the standard
5.0V ± 0.5V voltage range. Note there is only a ± 6% variation in delay time due to voltage effects.
-
AC244
3 I:"'
SPECIFICATION DERIVATION
-6'
0'
:s
Aca244
4
fCT244A
2
til
1
:s
A)
a.
0
-60 -40 -20
0
20
40
60
80
100 120
Temperalure (OC)
TL/F/10158-14
FIGURE 1-11a, tpHL Single Path
a;
a
voo ,= s.ov
7
....
tD
6
--
s
Maximum
4
3
Typical
Minimum
2
1
0
-60 -40 -20
20 40 60
Temperalure (oe)
0
BO 100 120
TL/F/l015B-15
FIGURE 1-11b, tpHL, 'AC244, All Paths
8
voo = s.ov
7
6
s
Uaxlmum
4
With voltage and process effects added (Figures 1-11g,
1-11h, and 1-11iJ, the full range of the specification can be
seen. For reference, the data sheet values are shown on
the graph.
Typical
Minimum
3
2
1
This linear behavior with temperature and voltage is typical
of CMOS. Although the graphs are drawn for a specific device, other part types have very similar graphical representations. Therefore, for performance-critical applications,
where not all variables need to be taken into account at
once, the user can narrow the specifications. For example,
all parts in a critically timed subcircuit are together on a
board, so it may be assumed the devices are at the same
supply and temperature.
0
-60 -40 -20
0 20 40 60
Temperalure (oe)
80
100 120
TLlF/10158-31
FIGURE 1-11c, tpHL, 'ACQ244, All Paths
8
voo = S.ov
7
6
S
4
..:=
Waxfmum
--
3
Typical
-
2 -Wlnlmum
1
0
-60 -40 -20
0
20
40
60
BO 100 120
Temperalure (oe)
TL/F/l015B-32
FIGURE 1-11d. tpHL, 'FCT244A, All Paths
1-13
-<
o
:sA)
8
Now refer to Figure 1-11t which illustrates the process effects on delay time. This graph indicates that the process
effects contribute to the spread in speCifications more than
any other factor in that the effects of the theoretical process
spread can increase or decrease specification times by
30%. Because this 30% spread represents considerably
more than ± 3 standard deviations, this guarantees an increase in the manufacturability and the quality level of FACT
product. To further ensure parts within specification will
pass on testers at the limits of calibration, tester guardbands are incorporated.
~
~.
iii'
( ;'
til
~
:;;
.;::
Circuit Characteristics
(Continued)
1.1
Q)
~cv
Military
1.08
ACTQ244
FCT244A
..c
1.06
1,04
~
1.02
1
.!!:
8!.
0.98
i
o
'E
"0
0.96
cv
0.94
II)
0.92
o
0.9
C
c
a
.;::
]:
Maximum
Typical
.!l
Room temp
c
~
:f.
5.5
u
II)
5.0
Military
MinImum
Commercial
-55
4.5
Commercial
Room temp
>.
-35
-15
Room temp
25
65
45
85
Volts
C
I-
FIGURE l-llh. tpHL, 'ACQ244, with
Voltage and Process Variation
FIGURE I-lIe. Voltage Effects on Delay Times
o
1.4
u.
1.3
.
Military
Commercial
Typical
0.9
0.6
125
TL/F/10158-33
TL/F/10158-16
Q)
105
Temperature (Oe)
65
85
105
125
Temperature (Oe)
TL/F/10158-18
FIGURE l-llg. tpHL, 'AC244, with Voltage
and Process Variation
1-14
Circuit Characteristics (Continued)
The same reasoning can be applied to setup and hold
times. Consider the 'AC74. The setup time is 3.0 ns while
the hold time is 0.5 ns. Theoretically, if these numbers were
violated, the device would malfunction; however, in actuali·
ty, the device probably will not malfunction. Looking at the
typical setup and hold times gives a better understanding of
the device operation.
CAPACITIVE LOADING EFFECTS
In addition to temperature and power supply effects, capaci·
tive loading effects for loads greater than 50 pF should be
taken into account for propagation delays of FACT devices.
Minimum delay numbers may be determined from the table
below. Propagation delay are measured to the 50% point of
the output waveform.
At 25'C and 5.0V, the setup time is 1.0 ns while the hold
time is -1.5 ns. They are virtually the same; a positive set·
up time means the control signal to be valid before the clock
edge, a positive hold time indicates the control signal will be
held valid after the clock edge for the specified time, and a
negative hold time means the control signal can transition
before the clock edge. FACT devices were designed to be
as immune to metastability as possible. This is reflected in
the typical specifications. The true "critical" time where the
input is actually sampled is extremely short: less than 50 ps.
Voltage (V)
Parameter
tpLH
tpHL
By applying the same reasoning as we did to the propaga·
tion delays to the setup and hold times, it becomes obvious
that the spread from setup to hold time (2.5 ns worst·case)
really covers devices across the entire process/tempera·
ture/voltage spread. The real difference between the setup
and hold times for any Single device, at a specified tempera·
ture and voltage, is negligible.
Units
3.0
4.5
5.5
FACTAC
FACT OS
FACT FCTA
31
34
45
22
19
29
19
19
27
ps/pF
FACTAC
FACT OS
FACT FCTA
18
32
17
13
22
13
13
20
12
ps/pF
TA = 25'C
Figures 1-12 and 1-13, describe propagation delays on
FACT devices as affected by variations in power supply volt·
age (VDD) and lumped load capacitance (CLl. Figures 1-14
and 1-15 show the effects of lumped load capacitance on
rise and fall times for FACT devices.
III
1-15
Circuit Characteristics (Continued)
32 Delay (ns)
.
c" = 1000 pF, tpLH
!o ..
30
28
:.....
26
24
18
16
14
12
...... ....
.. -
c" = 1000 pF, IpHL
22
20
.... .
~
CL =470pF, tpLH ~
r-..
- ,-- -.
-.. ---- ----- ... _=
r-:...
I
CL
470 pF, tpHL
r_--_~I-~
'1. =220pF, t,; .. -- 1-0
10
86
4
-----
---. ......
I
~.:~'!.~
---- ----- ----- -----
'1. = Sopr. fpLH
CL =50 pF, IpHL
2
o
3.0
3.5
4.0
4.5
5.0
6.0
5.5
Voo (Volts)
TL/F/l01SB-19
FIGURE 1-12a. Propagation Delay VB VDD ('ACOO)
Oolay (ns)
Oolay (ns)
50.---.----.--~--_,----._--,_--_r--_,
50
~~--+-~~---+--~----+---+----r---;
~
...... ......c" fO
......
\
~
30r---+----r~.t--~----t_--+_--_r--_i
30
..
20r---+-~~
pF. t;LH
.... ......
......
~=1000PF,lpHL
20
.. ....
~r- ....
221 pF.\PLH
•CL =
I-::.....
10
-..
--
10 I----~OPF.tpHl~
_-J
o
6.5
2.5
TL/F/l01SB-SS
1c,,=
.. ....
··1
- ____
3.5
___ Ct.__=
r'1.=50pF.'ru!
_J_+-_~.,
50 rt,.HL
I
4.5
Voo (VoH.)
220 pF. IpHL
•..,-5.5
6.5
TL/F/l01SB-SB
FIGURE 1-12b. Propagation Delay VB VDD ('ACTQ244)
FIGURE 1-12c. Propagation Delay VB VDD ('FCT244A)
1·16
~
Circuit Characteristics (Continued)
22 Delay (ns)
I
20
I
IpLH
VOO =5.0V
18
...."
10
~
,, .....,
,..'"
8
~\~
..
.
. ,"
........~'
..&
k:;;; ~
~~
,~
, 1'>-" ..
" ..... 1'-.. , ,
' ,,'
,
,
~
14
12
,
, k"
, I~"
.....
IpLH
VOO =5.5V
16
4
IpLH
VOO =4.5V
~
¢
tiP
k!:: ~ ~
1\
,
,
,
.
,,~
~~~
,,
CD
,
til
n
:::!.
"2-
O·
:::I
~
til
r( ~ ~ ~
DI
:::I
Co
L
L
~
.
,
,,
, ,,
C
~
H'"
\
\ IpHL
VO O=4.5V _
IpHL
VOO= 5.0V
3
~
-
o
::r
DI
iii
2CD
\ IpHL
YOO= 5.5V
~ ~ P"'"
~
![
~.
2
o 50
100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
Load Capacllance (pr)
TLlF/10158-20
FIGURE 1-13a. Propagation Delay V5 CL ('ACOO)
Delay (ns)
Delay (ns)
35
24
J
IpLH
Voo =4.5V
,. %
, ~
, '/'
22
20
IpLH
Voo =5.0V /
18
/
16
~
25
-lpHL
Voo =4.5V
I
'-lpHL
Voo =5.0V
20
~1~
,,
~,
,
~~
10
~~
8
4
~
?
,, ,
,
~V'
r>'
, , ,,
, , ,
PLH
,, , , ,
YOD= 5.0V
r---,.
,,,
, , , ~'
, , ,, ,
,
,,, , ,, ,
VOO= ~.~~
i';
~.
,, ,
,
, ","
"
, '"
,"
".,. t:;;;;; ~
"
",
Ip L
,,
YOO' 4.5V
,,," "
~ ....&
P"
Ip
Voo=4
YOO=5.5~
12
6
!/
/j P"~
/ ~ ",-
IpLH
14
lfZ.
,
30
15
~
IpHL
VOO= 5.5V
10
1.11'
II
~~
I"
200
400
600
.
800
1000
Load CapacHance (pF)
o
o
200
~ff ~~
Ip~L
Yoo=5.5
r~
I
400
600
800
1000
Load CapacHance (pr)
TL/F/10158-37
FIGURE 1-13b. Propagation Delay V5 CL ('ACTQ244)
TL/F/10158-38
FIGURE 1-13c. Propagation Delay V5 CL ('FCT244A)
1·17
Circuit Characteristics (Continued)
LATCH-UP
A major problem with CMOS has been its sensitivity to
latch-up, usually attributed to high parasitic gains and high
input impedance. FACT logic is guaranteed not to latch-up
with dynamic currents of 100 mA (300 mA for FACT as)
forced into or out of the inputs or the outputs under worst
case conditions (TA = 125°C and Voo = 5.5 Vocl. At room
temperature the parts can typically withstand dynamic currents of close to 1A. For most designs, latch-up will not be a
problem, but the designer should be aware of its causes and
how to prevent it.
10
9
Voo = 5.0V
TA = 25"C
8
7
";i'
FACT OS
6
-5 5
J
4
3
2
FACT devices have been specifically designed to reduce
the possibility of leitch-up occurring; National Semiconductor
accomplished this by lowering th'e gain of the parasitic transistors, reducing substrate and p-well resistivity to increase
external drive current required to cause a parasitic to turn
ON, and careful design and layout to minimize the substrate-injected current coupling to other circuit areas.
0
0
10
20
30
40
Load Capacitance (pF)
50
TLlF/l015B-21
FIGURE 1-14. trlse vs Capacitance
10
8
7
";i'
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY
=
=
Voo 5.0V
TA 25"C
FACT circuits show excellent resistance to ESD-type damage. These logic devices are classified as category "8" of
MIL-STD-883C, test method 3015, and withstand in excess
of 4000V typically. FACT logic is guaranteed to have 2000V
ESD immunity on all inputs and outputs. Some FACT as
and FACT FCT/FCTA are guaranteed to have 4000V ESD
immunitY. FACT parts do not require any special handling
procedures. However, normal handling precautions should
be observed as in the case of any semiconductor device.
Figure 1-17shows the ESD test circuit used in the sensitivity
analysis for this specification. Figure 1-18 is the pulse waveform required to perform the sensitivity test.
FACT QS
6
-5 5
)
4
3
2
0
0
10
20
30
40
Capacitance (pF)
50
L~.. d
TL/F/l015B-22
FIGURE 1-15. tfall vs Capacitance
N-Channel MOS
P-Channel MOS
R2
Rl
>.> R2
N+ Substrate
0.008-0.25 ohm-em
R1!1R 2 ""R2
TL/F/l0158-23
FIGURE 1-16. FACT EPI Process Cross Section with Latch-up Circuit Model
1-18
Circuit Characteristics
(Continued)
the 2000V-3999V range are listed as ESD Class 2. Devices
that result in ESD immunity in the 4000 + V range are listed
as ESD Class 3. Several devices on the FACT as and
FACT FCT/FCTA lines are guaranteed as Class 3 (see individual data sheets).
The test procedure is as follows; five pulses, each of at
least 2000V, are applied to every combination of pins with a
five second cool-down period between each pulse. The polarity is then reversed and the same procedure, pulse and
pin combination used for an additional five discharges. Continue until all pins have been tested. If none of the devices
from the sample population fails the DC and AC test characteristics, the device shall be classified as category B of MILSTD-BB3C, TM-3015. Devices that result in ESD immunity in
Rl
For further specifications of TM-3015, refer to the relevant
standard. The voltage is increased and the testing procedure is again performed; this entire process is repeated until
all pins fail. This is done to thoroughly evaluate all pins.
= 800 kA
(min)
3GA (max)
High Voltage
R2
= 1500A
r-.....--f~=]---------O Relay
Cha~
Discharge
Calibrate
Test
Regulated
High Voltage
Supply
11
DC
Voltmeter
= 100pF
OUT
R3
= 1500A
Waveform
Terminals
TLlF/l0158-24
FIGURE 1-17. ESD Test Circuit
100%
90%
'"=[""
t RISE :S 15 ns
tDECAy :S 350 ns
....E
(R2 + R3) C1 ~ 300 ns
.'"
Of
'">
0
36.8%
10%
TIME
TL/F/l0158-25
FIGURE 1-18. ESD Pulse Waveform
1-19
Circuit Characteristics (Continued)
RADIATION TOLERANCE
Total dose irradiation is presently performed "in-house" using a AECL Gamma Cell 220, Cobalt-60, source (National
Bureau of Standards certified). Step-stress radiation testing
is performed on each part-type per MIL STD BB3 Method
1019.3. After each total dose level, a complete parametric
test (DC and AC) is done and the parametric values evaluated.
Semiconductors subjected to radiation environments undergo degradation in operating life as their exposure to radiation increases. As technology advances, so does the demand for radiation-tolerant devices. National is meeting this
challenge by developing the FACT family into a comprehensive radiation tolerant product for present and future radhard needs. Such applications include:
FACT IS RADIATION TOLERANT
• Space (Commercial and Military)
-
Satellites
-
Space Stations
FACT logic employs the use of thin gate oxides, oxidation
cycles, and annealing steps that enhance the tolerance of
the standard FACT product line.
FACT's epitaxial layer and low-resistivity substrate provide
inherent latch-up immunity under dose rate and single event
phenomenon (SEP) conditions.
• Airborne and Military (Tactical Arena)
-
Fighters/Bombers
-
Missile Systems
-
Ground Based Systems
-
Navigation & Communications
Figure 19 shows a FACT 'AC245 100 supply current versus
total dose radiation. With the exception of 100 and loz, all
FACT devices tested to date suffer no parametric degradation or functional failures up to several hundred krads. Due
to circuit and layout differences, each function has a unique
response to radiation. Relaxed limits for 100 and loz are per
the applicable /750XX slash sheet, standard military drawing (SMD), or datasheet.
• Commercial
- Power Stations
-
Medical
-
Food and Bacterial Control
Radiation tolerant semiconductors increase the useful life of
the product in which they are incorporated. Additionally, radiation tolerant devices reduce shielding requirements and
improve stabilization of parametric performance, resulting in
cost reductions for shielding and weight, reduce power consumption and size.
DOSE RATE TEST RESULTS
Analysis of the FACT 54AC299 B-Bit Universal Shift Register upset test data indicates that minimum upset threshold
levels occurred under the worst-case conditions of a wide
pulse (1 /los), lowest VOD voltage (4.0V DC), and the OUT in
the dynamic operating mode.
Measured minimum upset levels were 1.90 to 2.22 x 109
rad(Si)/sec. Narrow pulse (50 ns) data demonstrated radiation upset levels from 4.40 to 5.66 X 109 rad(Si)/sec under
dynamic operation.
SUMMARY OF TESTING
OOOr---------~~------------_,
~ 500
'?
~
Dose Rate: 215
Temp: 250(;
rad (SI)
--sec
514
Upon completion of radiation upset testing, latchup and survivability tests were performed at + 25'C, + BO'C, + 10o-C,
and + 116'C for VOD = 4.5V DC, 5.0V DC, and 5.5V DC.
Test results indicated no latchup occurred for either narrow
pulse (50 ns) or wide pulse (1 ms) radiation. The radiation
test level for narrow pulse was 1010 rad(Si)/sec at + 25'C.
Due to the heating of the circuit, the highest radiation level
was limited at + 116'C to 7.5 x 109 rad(Si)/sec.
400
8300
..,~
Iii
e
189
200
jll00
a
After completion of latch up and survivability tests, verification of latchup windows was performed. Test results indicate no existence of latchup windows under worst case
conditions for narrow and wide pulse radiation.
100 200 300 400 500 600 700 800 900 1000
Total Ionization - [krad (SI)]
TUF/l0156-26
FIGURE 1-19. Total Dose Response (54AC245)
1-20
Section 2
Ratings, Specifications,
and Waveforms
•
I
Section 2 Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • . • . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . .
Power Dissipation-Test Philosophy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Loading and Waveforms ....•..............................•.....................
Test Conditions... . .... .. . . .. ... . •.. . . ...•. .... ........ ... .... .. ... .. . ... .... . . .. ..
Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Propagation Delays. f max• Set and Hold Times .........................................
Enable and Disable Times . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic Discharge. . . . . . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . • • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2·2
2-3
2-3
2-3
2-4
2-5
2-5
2-5
2-7
2-7
-
::0
III
~National
5'
!IJ
CC
~ Semiconductor
en
'0
(I)
~,
Ratings, Specifications, and Waveforms
::!l
n
III
0'
::s
!IJ
III
Specifying FACTTM Devices
::s
Traditionally, when a semiconductor manufacturer completed a new device for introduction, specifications were based
on the characterization of just a few parts. While these
specifications were appealing to the designer, they were often too tight and, over time, the IC manufacturers had difficulty producing devices to the original specs. This forced
the manufacturer to relax circuit specifications to reflect the
actual performance of the device.
As a result, designers were required to review system designs to ensure the system would remain reliable with the
new specifications. National Semiconductor realized and
understood the problems associated with characterizing devices too aggressively.
pacitance for either the entire device or for just a certain
stage of that device. For example, from the following list, it
is apparent that the CPO value specified for a counter reflects the internal capacitance for the entire device, since
the entire device is being exercised during measurement.
On the other hand, the CPO value specified for an octal line
driver reflects the internal capacitance for only one of eight
stages, since only one input was being switched during test.
Therefore the octal's overall power dissipation should be
calculated for each of the eight stages, individually.
c.
~
lo
...3
en
During the CPO measurements, each output that is being
switched should be loaded with the standard 50 pF and
500n load. All device measurements are made with Voo =
5.0V at 25'C, with TRI-STATE® outputs enabled.
Gates/Buffers/
Switch one input. Bias the remaining
inputs such that one output switches.
Line Drivers:
To provide more realistic and manufacturable specs, National Semiconductor devised a systematic and thorough
process to generate specifications. Devices are selected
from multiple wafer lots to ensure process variations are
taken into account. In addition, the process parameters are
measured and compared to the known process limits. With
more than five years of experience manufacturing FACT
logiC. National Semiconductor can accurately predict how
these wafer lots compare with the best and worse case lots
that can possibly be expected.
This method of characterizing parts more accurately represents the product across time, voltage, temperature and
process rather than portraying the fastest possible device.
Latches:
Switch the Enable and 0 inputs such
that the latch toggles.
Flip-FlopS:
Switch the clock pin while changing 0
(or bias J and K) such that the outputts) change each clock cycle. For
parts with a common clock, exercise
only one flip-flop.
Switch one address pin which changes two outputs.
Switch one address pin with the corresponding data inputs at opposite logic
levels so that the output switches.
Decoders:
Multiplexers:
These specification guidelines allow designers to design
systems more efficiently since the devices used will behave
as documented. Unspecified guard bands no longer need to
be added by the designer to ensure system reliability.
Counters:
Power Dissipation-Test
Philosophy
Shift Registers:
Transceivers:
In an effort to reduce confusion about measuring power dissipation capacitance, CPO, a JEDEC standard test procedure (7 A Appendix E) has been adopted which specifies the
test setup for each type of device. This allows a device to
be exercised in a consistent manner for the purpose of
specification comparison.
The following is a list of different types of logic functions,
along with the input setup conditions under which the CPO
was measured for each type of device. By understanding
how the device was exercised during CPO measurements,
the designer can understand whether the Cpo specified for
that particular device reflects the total power dissipation ca-
Parity Generator:
Priority Encoders:
Switch the clock pin with other inputs
biased such that the device counts.
Switch the clock pin with other inputs
biased such that the device shifts.
Switch one data input. For bidirectional devices enable only one direction.
Switch one input.
Switch the lowest priority input.
AC Loading and Waveforms
LOADING CIRCUIT
Figure 1 shows the AC loading circuit used in characterizing
and specifying propagation delays of all FACT devices (,AC
and 'ACT) unless otherwise specified in the data sheet of a
specific device.
2-3
•
0r---------------------------------------------------------~
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AC Loading and Waveforms (Continued)
The use of this load, which is equivalent to the FAST4l> (Fairchild Advanced Schottky TIL) test jig, differs somewhat
from previous (HCMOS) practice. This provides more meaningful information and minimizes problems of instrumentation and customer correlation. In the past, + 25°C propagation delays for TIL devices were specified with a load of
15 pF to ground; this required great care in building test jigs
to minimize stray capacitance and implied the use of high
impedance, high frequency scope probes. FAST circuits
changed to 50 pF of capacitance, allowing more leeway in
stray capacitance and also loading the device during rising
or falling output transitions. This more closely resembles the
in loading to .be expected in avarage applications and thus
gives the deSigner more useful delay figures. We have incorporated this scheme into the FACT product line. The net
effect of the change in AC load is to increase the average
observed propagation delay by about 1 ns.
Disable parameters (LOW-to-OFF and OFF-ta-LOW) of a
TRI-STATE output. With the switch closed, the pair of 5000.
resistors and the 2 x Voo supply voltage establish a quiescent HIGH level.
Test Conditions
Figures 2a and 2b describe the input signal voltage levels to
be used when testing FACT circuits. The AC test conditions
follow industry convention requiring VIN to range from OV for
a logic LOW to 3.0V for a logic HIGH for 'ACT devices and
OV to Voo for 'AC devices. The DC parameters are normally
tested with VIN at guaranteed input levels, that is VIH to VIL
(see data tables for details). Care must be taken to adequately decouple these high performance parts and to protect the test signals from electrical noise. In an electrically
noisy environment, (e.g., a tester and handler not specifically designed for high speed work), DC input levels may need
to be adjusted to increase the noise margin to allow for the
extra noise in the tester which would not be seen in a system.
Noise immunity testing is performed by raising VIN to the
nominal supply voltage of 5.0V then dropping to a level corresponding to VIH characteristics, and then raising again to
the 5.0V level. Noise tests can also be performed on the VIL
characteristics by raiSing VIN from OV to VIL, then returning
to OV. Both VIH and VIL noise immunity tests should not
induce a switch condition on the appropriate outputs of the
FACT device.
The 5000. resistor to ground can be a high frequency passive probe for a sampling OSCilloscope, which costs much
less than the equivalent high impedance probe. Alternately,
the 5000. resistor to ground can simply be a 4500. resistor
feeding into a 500. coaxial cable leading to a sampling
scope input connector, with the internal 500. termination of
the scope completing the path to ground. This is the preferred scheme for correlation. (See Figure 1.) With this
scheme there should be a matching cable from the device
input pin to the other input of the sampling scope; this also
serves as a 500. termination for the pulse generator that
supplies the input Signal.
Good high frequency wiring practices should be used in
constructing test jigs. Leads on the load capaCitor should be
as short as possible to minimize ripples on the output wave-
Shown in Figure 1 is a second 5000. resistor from the device output to a switch. For most measurements this switch
is open; it is closed for measuring one set of the Enable/
tpLII
tpHL
tPZH
tpHZ
lEST LOAD
o-e 7.OY
5004
5004
tr =3.ons
,,=3.0n.
5011 Scope
TLlF/l0159-11
TLlF/l0159-1
FIGURE 1b. AC Loading Circuit for FCT, FCTA
FIGURE 1a. AC Loading Circuit for AC, ACT, ACO, ACTO
'ACxx, ACOxx Devices
70% Voo
30% Voo
0.tvt:U...L~~~~;:::~-=_::=4:::::_:_-:-+==::::::_
ov
AC Test
DC LOW
Input Levels Input Range
LOW level
Noise
Immunity
DC HIGH
Input Range
HIGH Level
Noise
Immunity
Transition
Region
TLlF/l0159-2
FIGURE 2a. Test Input Signal Levels
2-4
-
r----------------------------------------------------------------------.~
m
Test Conditions (Continued)
5'
'ACTxx, ACTQxx, FCTxx, FCTxxA Devices
CQ
Y'
en
Voo
Voo - O.IV
'tJ
CD
n
::;;
(;'
a0'
3.0V
~
Y'
m
~
2.0V
Q.
O.BV
f
O.IV:t:.L.u-l:':~~~~~~-_!_--_l_-OV
AC Test
DC LOW
Input Levels Input Range
LOW Level
Noise
Immunity
DC HIGH
Input Range
HIGH Level
Noise
Immunity
0'
..,.
Transition
Region
TL/F/10159-3
3
en
FIGURE 2b. Test Input Signal Levels
Package-related causes of output oscillation are not entirely
to blame for problems with input rise and fall time measurements. All testers have Voo and ground leads with a finite
inductance. This inductance needs to be added to the inductance in the package to determine the overall voltage
which will be induced when the outputs change. As the reference for the input signals moves further away from the pin
under test, the test will be more susceptible to problems
caused by the inductance of the leads and stray noise. Any
noise on the input signal will also cause problems. With
FACT logic having gains as high as 100, it merely takes a
50 mV change in the input to generate a full 5V swing on the
output.
form transitions and to minimize undershoot. Generous
ground metal (preferably a ground plane) should be used for
the same reasons. A Voo bypass capacitor should be provided at the test socket, also with minimum lead lengths.
Rise and Fall Times
Input signals should have rise and fall times of 3.0 ns and
signal swing of OV to 3.0V Voo for 'ACT devices or OV to
Voo for 'AC devices. Rise and fall times less than or equal
to 1 ns should be used for testing f max or pulse widths.
CMOS devices, including 4000 Series CMOS, HC, HCT and
FACT families, tend to oscillate when the input rise and fall
times become lengthy. As a direct result of its increased
performance, FACT devices can be more sensitive to slow
input rise and fall times than other lower performance technologies.
Propagation Delays, f max,
Set and Hold Times
It is important to understand why this oscillation occurs.
Consider the outputs, where the problem is initiated. Usually, CMOS outputs drive capacitive loads with low DC leakage. When the output changes from a HIGH level to a LOW
level, or from a LOW level to a HIGH level, this capacitance
has to be charged or discharged. With the present high performance technologies, this charging or discharging takes
place in a very short time, typically 2-3 ns. The requirement
to charge or discharge the capacitive loads quickly creates
a condition where the instantaneous current change
through the output structure is quite high. A voltage is generated across the Voo or ground leads inside the package
due to the inductance of these leads. The internal ground of
the chip will change in reference to the outside world because of this induced voltage.
A 1.0 MHz square wave is recommended for most propagation delay tests. The repetition rate must necessarily be increased for testing f max. A 50% duty cycle should always be
used when testing f max. Two pulse generators are usually
required for testing such parameters as setup time, hold
time, recovery time, etc. See Figures 3, 4, and 8.
Enable and Disable Times
Figures 5, 6 and 11 show that the disable times are measured at the point where the output voltage has risen or
fallen by O.3V from VOL or VOH, respectively. This change
enhances the repeatability of measurements, and gives the
system designer more realistic delay times to use in calculating minimum cycle times. Since the high impedance state
rising or falling waveform is RC-controlled, the first 0.3V of
change is more linear and is less susceptible to external
influences. More importantly, perhaps from the system designer's point of view, a change in voltage of 0.3V is adequate to ensure that a device output has turned OFF. Measuring to a larger change in voltage merely exaggerates the
apparent Disable times and thus penalizes system performance since the designer must use the Enable and Disable
times to devise worst case timing signals to ensure that the
output of one device is disabled before that of another device is enabled. Note that the measurement points have
been changed from the previous 10% and 90% pOints. This
better reflects actual test points and does not change specification limits.
Consider the input. If the internal ground changes, the input
voltage level appears to change to the DUT. If the input rise
time is slow enough, its level might still be in the device
threshold region, or very close to it, when the output
switches. If the internally-induced voltage is large enough, it
is possible to shift the threshold region enough so that it recrosses the input level. If the gain of the device is sufficient
and the input rise or fall time is slow enough, then the device may go into oscillation. As device propagation delays
become shorter, the inputs will have less time to rise or fall
through the threshold region. As device gains increase, the
outputs will swing more, creating more induced voltage. Instantaneous current change will be greater as outputs become quicker, generating more induced voltage.
2-5
•
Waveforms
D~A~~
SAME PHASE
INPUT TRANSITION
~~b~E:k~tpxx
DATA---OUT____
~3V
- - 1.5V
tPH~
t PLH{
OUTPUT
Vmo
LH tpHL
--t.E
-==
---.
TLlF/l0159-4
OPPOSITE PHASE
INPUT TRANSITION
FIGURE 3. Waveform for Inverting and
Non-Inverting Functions for ACt ACT, ACQt ACTQ
OV
~ ~~~
VOL
3V
~~V
TLlF/l0159-12
FIGURE 8. Propagation Delay for FCT, FCTA
CONTROL --"'\.IJ--':"'-'\.I,~-IN
LOW-HIGH-LOW
PULSE
-+=-____-I--'I'\..,l~
CLOCK _ _
HIGH-LOW-HIGH
PULSE
TLlF/l0159-13
OUTPUT
FIGURE 9. Pulse Width for FCT, FCTA
TL/F/l0159-5
FIGURE 4. Propagation Delay, Pulse Width
and tree Waveforms for ACt ACT, ACQt ACTQ
DATA
INPUT
~
l---"""""'~-3V
-1.5V
~ -i'L.II:..L~ _ OV
tsu
TIMING --....;.---""1.,---1--INPUT _________....J'I'-__
+ ___ -
-
3V
1,5V
OV
PRESET ---....,,1,.--4----1--- CLEAR
ETC.
-
3V
1.5V
OV
ASYNCHRONOUS CONTROL
TL/F/l0159-6
FIGURE 5. TRI-STATE Output High Enable
and Disable Times for ACt ACT, ACQt ACTQ
SYNCHRONOUS CONTROL
= .J1:~
.
~AJt
Vmo
PRESET
CLEAR
CLOCK ENABLE
ETC.
~H~~rI-.-"""''''7 -
3V
~ -""'-"'-"--" -
OV
-1.5V
tsu
TL/F/l0159-14
FIGURE 10. Set-Up, Hold
and Release Times for FCT, FCTA
VOL +O.3V
VOL
TLlF/l0159-7
ENABLE
FIGURE 6. TRI-STATE Output Low Enable
and Disable Times for ACt ACT, ACQt ACTQ
DATA---~~~
OUTPUT
NORMALLY
LOW
CONT~:L ----i.S1?~
. INPUT
MR
OR
CLEAR
::E::x
..
:~~I" m::::I....__
ts
OUTPUT
NORMALLY
HIGH
,.:.;Ire::.,c_ _ _ __
LV~m~I_ _ ___
-
Vmo
~
3.5V
-!tPZH
SWITCH
OPEN
TLlF/l0159-15
Nole 1: Diagram shown for input Control Enable·LOW and input Control
TLlF/l0159-8
~
SWITCH
CLOSED
FIGURE 11. Enable and Disable Times for FCT, FCTA
Disable-HIGH
FIGURE 7. Setup Time, Hold Time and
Recovery Time for ACt ACT, ACQt ACTQ
'Vmi
DISABLE
CONTROL
INPUT
Nole 2: Pulse Generator for All Pulses: Rate,;;
2.5 ns; tR ::;: 2.5 ns
50% Voo for 'ACI'ACQ devices; 1.5V for 'ACTI'ACTQ devices
50% Voo for 'ACI'ACT, 'ACQI'ACTQ devices
2-6
1.0
MHz; Zo ,;; 5011; IF ,;;
Electrostatic Discharge
ACTIVE
OUTPUTS
Precautions should be taken to prevent damage to devices
by electrostatic discharge. Static charge tends to accumulate on insulated surfaces such as synthetic fabrics or carpeting, plastic sheets, trays, foam, tubes or bags, and on
ungrounded electrical tools or appliances. The problem is
much worse in a dry atmosphere. In general, it is recommended that individuals take the precaution of touching a
known ground before handling devices. To effectively avoid
electrostatic damage to FACT devices, it is recommended
that individuals wear a grounded wrist strap when handling
devices. More often, handling equipment, which is not properly grounded, causes damage to parts. Ensure that all plastic parts of the tester, which are near the device, are conductive and connected to ground.
=x. ____
•
--'X~---VOH
'----VOL
QUIET
OUTPUT
UNDER TEST ~- - - - - - - - - - - - - - - - - - - VOLP
- - - - - - - - - - - - - • VOL
• - - - - - - - - - - - - - - - - - • VOLV
TL/F/l0159-9
FIGURE 12. Quiet Output Noise Voltage Waveforms
Note A. VOHV and VOlP are measured with respect to ground reference.
Note B. Input pulses have the following characteristics: f = 1 MHz, t, =
3 ns. tf = 3 ns. skew < 150 ps.
FACT Noise Characteristics
VOLPIVOLV and VOHPIVOHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50n coaxial cable plugged into a standard
5MB type connector on the test fixture. Do not use an
active FET probe.
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the noise
characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture or Equivalent
Tektronics Model 7854 Oscilloscope or Equivalent
• Measure VOLP and VOLV on the quiet output LOW during
the HL transition. Measure VOHP and VOHV on the quiet
output HIGH during the LH transition.
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF, 500n.
2. Deskew the word generator so that no two channels have
greater than 150 ps skew between them. This requires
that the oscilloscope be deskewed first. Swap out the
channels that have more than 150 ps of skew until all
channels being used are within 150 ps. It is important to
deskew the word generator channels before testing. This
will ensure that the outputs switch simultaneously.
3. Terminate all inputs and outputs to ensure proper loading
of the outputs and that the input levels are at the correct
voltage.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
VILD and VIHD:
• Monitor one of the switching outputs using a 50n coaxial
cable plugged into a standard 5MB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate. Oscillation is defined as noise
on the output LOW level that exceeds VIL limits, or on
output HIGH levels that exceed VIH limits. The input
LOW voltage level at which oscillation occurs is defined
as VILD.
• Next increase the input HIGH voltage level on the word
generator, VIH until the output begins to oscillate. Oscillation is defined as noise on the output LOW level that
exceeds VIL limits, or on output HIGH levels that exceed
VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
4. Set VDD to 5.0V.
5. Set the word generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
OUT heating and affect the results of the measurement.
6. Set the word generator input levels at OV LOW and 3V
HIGH for ACT/ACTO/FCT/FCTA devices and OV LOW
and 5V HIGH for ACI ACO devices. Verify levels with a
digital volt meter.
@
4504
HP8t80A
WORD
GENERATOR
@
TEK7854
Oscilloscope
504 Inputs
4504
50 F
Probes are grounded as
lit p
close to OUT pins as possible.
'\! '-- Load capacitors are placed
as close to OUT as possible.
FIGURE 13. Simultaneous Switching Test Circuit
2-7
TL/F/l0159-10
•
Section 3
Design Considerations and
Application Notes
Section 3 Contents
Design Considerations for Advanced CMOS Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TTL-Compatible CMOS Designs Require Delta IDD Consideration. . . . . . . . . . . . . . . . . . . . . . . . .
Testing Advanced CMOS Devices with I/O Pins.. . .. .. . . ... .. ... . . .. . . ... .. .. . .. .... . ..
Testing Disable Times ofTRI-STATE Outputs in a Transmission Line Environment. . . .... . ..
AN-SOO Understanding Latch-Up in Advanced CMOS Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-S1O Terminations for Advanced CMOS Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-S40 Understanding and Minimizing Ground Bounce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-S80 Dynamic Thresholds for Advanced CMOS Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-S90 Design Innovations Address Advanced CMOS Logic Noise Considerations .........
3-2
3-3
3-17
3-18
3-19
3-21
3-25
3-30
3-45
3-54
IC
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Design Considerations
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Today's system designer is faced with the problem of keeping ahead when addressing system perlormance and reliability. National Semiconductor's advanced CMOS helps
designers achieve these goals.
24 mA of current under worst case conditions. FACT FCT is
guaranteed to sink 64 mA and source 15 mA. This allows
FACT circuits to drive more loads than standard advanced
Schottky parts; FACT can directly drive FAST®, ALS, AS,
LS, HC and HCT devices.
FACTTM (Fairchild Advanced CMOS Technology) logic was
designed to alleviate many of the drawbacks that are common to current technology logic circuits. FACT logic combines the low static power consumption and the high noise
margins of CMOS with a high fan-out, low input loading and
a 500 transmission line drive capability (comparable to National Semiconductor's FAST bipolar technology family) to
offer a complete family of 1.3-micron SSI, MSI, and LSI devices.
Performance features such as advanced Schottky speeds
at CMOS power levels, advanced Schottky drive, excellent
noise, ESD, and latch-up immunity are characteristics that
designers of state-of-the-art systems require. FACT logic
answers all of these concerns in one family of products. To
fully utilize the advantages provided by FACT, the system
designer should have an understanding of the flexibility as
well as the trade-offs of CMOS design. The following section discusses common design concerns relative to the performance and requirements of FACT.
TLlF/10160-1
FACT devices can be directly driven by both NMOS and
CMOS families, operating at the same rail potential without
special considerations. This is possible due to the low input
loading of FACT product, guaranteed to be less than 1 IJ-A
per input.
Some older technologies, including all existing TTL families,
will not be able to drive FACT AC/ACa circuits directly; this
is due to inadequate output HIGH level capability, which is
guaranteed to 2.4V. There are two simple approaches to the
TTL-to-FACT interface problem. A TTL-to-CMOS converter
can be constructed employing a resistor pull-up to Voo of
approximately 4.7 kO, which is depicted in Figure 3-2. The
correct HIGH level is seen by the CMOS device while not
loading down the TTL driver.
o Interfacing-interboard and technology interfaces, bat-
o
o
o
TIL
FIGURE 3-1. Interfacing FACT to NMOS, CMOS, and TTL
There are six items of interest which need to be evaluated
when implementing FACT devices in new designs:
o
v+
ACMOS
tery backup and power down or live insertl extract systems require some special thought.
Transmission Line Driving-FACT has line driving capabilities superior to all CMOS families and most TTL families.
Noise effects-As edge rates increase, the probability of
crosstalk and ground bounce problems increases. The
enhanced noise immunity and high threshold levels improve FACT's resistance to system-generated problems.
Board Layout-Prudent board layout will ensure that
most noise effects are minimized.
Power Supplies and Decoupling-Maximize ground and
Voo traces to keep Voo/ground impedance as low as
possible; full groundlVoo planes are best. Decouple any
device driving a transmission line; otherwise add one capacitor for every package.
TIL
v+
ACMOS
&I
HC
AC
ACO
o Electromagnetic Interference
TL/F/10160-2
FIGURE 3-2. VIH Pull-Up on TTL Outputs
Interfacing
as
Unfortunately, there will be designs where including a pullup resistor will not be acceptable. In these cases, such as a
terminated TTL bus, National Semiconductor has designed
devices which offer thresholds that are TTL-compatible
(Figure 3-3).
FACT and FACT
devices have outputs which combine
balanced CMOS outputs with high current line driving capability. Each standard output is guaranteed to source or sink
3-3
o
C
o
~
CP
"CI
r---------------------------------------------------------------------------------,
Although all circuit conductors have transmission line properties, these characteristics become more significant when
the edge rates of the drivers are equal to or less than three
times the propagation delay of the line. Significant transmission line properties may be exhibited in an example where
devices have edge rates of 3 ns and lines of 8 inches or
greater, assuming propagation delays of 1.7 nslft for an
unloaded printed circuit trace.
Of the many properties of transmission lines, two are of
major interest to the system designer: Z' 0' the effective
equivalent impedance of the line, and tpde, the effective
propagation delay down the line. It should be noted that the
intrinsic values of line impedance and propagation delay, Zo
and tpd, are geometry-dependent. Once the intrinsic values
are known, the effects of gate loading can be calculated.
The loaded values for Z' 0 and tpde can be calculated with:
Interfacing (Continued)
m
v+
ACMOS
'iii
c
8c
C)
'Xi
o
FCT/FCTA
ACTO
TLlF/l0160-3
FIGURE 3-3. TTL Interfacing to 'ACT
ECl devices cannot directly drive FACT devices. Interfacing
FACT-to-ECL can be accomplished by using a F100124 or
F100324 TTL-to-ECL translator and a F100125 or F100325
ECL-to-TTL translator in addition to following the same rules
on the TTL outputs to CMOS inputs (i.e., a resistor pull-up to
Voo of approximately 4.7 kll).
ACMOS
v+
Z' 0-
+ Co/CL
where CL = intrinsic line capacitance and Co
capacitance due to gate loading.
= additional
The formulas indicate that the loading of lines decreases
the effective impedance of the line and increases the propagation delay. Lines that have a propagation delay greater
than one third the rise time of the Signal driver should be
evaluated for transmission line effects. When performing
transmission line analysis on a bus, only the longest, most
heavily loaded and the shortest, least loaded lines need to
be analyzed. All lines in a bus should be terminated equally;
if one line requires termination, all lines in the bus should be
terminated. This will ensure similar signals on all of the lines.
TLlF/l0160-4
v+
Zo
+ Co/CL
tpde = tpd 41
ECl
FIGURE 3-4a. FACT-to-ECl Translation
ECl
~1
ACMOS
Zs
,.
length of Transmission Une ~ l
TLlF/l0160-5
Distributed Load CapaCitance per Unit Length
FIGURE 3-4b. ECl-to-FACT Translation
~ Co ~
L
N
CL/L
n-l
Characteristic Impedance
It should be understood that for FACT, as with other CMOS
technologies, input levels that are between specified input
values will cause both transistors in the CMOS structure to
be conducting. This will cause a low resistive path from the
supply rail to ground, increasing the power consumption by
several orders of magnitude. It is important that CMOS inputs are always driven as close as possible to the rail.
of a Transmission Une
~ Z· 0
Altered by Oistributed loading
~JCo~co
Zo
~ ~1+9Q
Co
~ p ~ ZZT - Zz:o
T+ a
FIGURE 3-5a. Transmission line
with Distributed loading
Effective Refiection Coefficient at Termination
Line Driving and Termination
With the available high-speed logiC families, designers can
reach new heights in system performance. Yet, these faster
devices require a closer look at transmission line effects.
3-4
cCD
Line Driving and Termination
III
(Continued)
cO'
~
oo
~
III
is:
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.
G
en
(I Zo
TLlF110160-7
=L
=T
• Length of Transmission Line
• Delay of Transmission Line
• Time of Sample ~ t
• Incident Wave Current = 11
• Incident Wave Voltage ~ VI
• Reflected Wave Current ~ IR
• Reflected Wave Voltage ~ VR
• Characteristic Impedance of Line
• Termination Impedance
~
Zo
= ZT
• Voltage at Termination ~ VT
FIGURE 3·5b. Reflections Due to Impedance Mismatching
There are several termination schemes which may be used.
Included are series, parallel, AC parallel, and Thevenin terminations. AC parallel and series terminations are the most
useful for low power applications since they do not consume any DC power. Parallel and Thevenin terminations experience high DC power consumption.
waveform. The first step will be the incident wave, Vi. The
amplitude is dependent upon the output impedance of the
driver, the value of the series resistor, and the impedance of
the line according to the formula
Vi = Voo" Z'o/(Z'o + Rs + Zs)
The amplitude will be one-half the voltage swing if Rs (the
series resistor) plus the output impedance (Zs) of the driver
is equal to the line impedance. Zs for FACT is approximately
170. The second step of the waveform is the reflection from
the end of the line and will have an amplitude equal to that
of the first step. All devices on the line will receive a
SERIES TERMINATIONS
Series terminations are most useful in high-speed applications where most of the loads are at the far end of the line
or especially for single point loads. Loads that are between
the driver and the end of the line will receive a two-step
TLfFfl0160-8
TLfFfl0160-9
b. Series Termination
a. No Termination
===::;-11>-
-t>-----;.
TLfFf10160-10
~
~V
TLfFfl0160-11
c. Parallel Termination
d. AC Parallel Termination
TLfFfl0160-12
e. Thevenin Termination
FIGURE 3·6a. Termination Schemes
3-5
•
11)
c
o
:;:;
Line Driving and
Termination (Continued)
't:I
valid level only after the wave has propagated down the line
and returned to the driver. Therefore, all inputs will see the
full voltage swing within two times the delay of the line.
eCP
'iii
c
o
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c
PARALLEL TERMINATION
'ij
c
Parallel terminations are not generally recommended for
CMOS circuits due to their power consumption, which can
exceed the power consumption of the logic itself. The power consumption of parallel terminations is a function of the
resistor value and the duty cycle of the signal. In addition,
parallel termination tends to bias the output levels of the
driver towards either Voo or ground. While this feature is not
desirable for driving CMOS inputs, it can be useful for driving TTL inputs.
C)
FACT circuits have been designed to drive 500. transmission lines over the full commercial temperature range a'nd
750. transmission lines over the military temperature range.
This is guaranteed by the FACT family's specified dynamic
drive capability of 75 mA source and sink current. This ensures incident wave switching on 500. transmission lines
and is consistent with the 3 ns rated edge transition time.
FACT and FACT OS devices also feature balanced output
totem pole structures to allow equal source and sink current
capability. This gives rise to balanced edge rates and equal
rise and fall times. Balanced drive capability and transition
times eliminate both the need to calculate two different delay times for each signal path and the requirement to correct
signal polarity for the shortest delay time.
FACT FCTtFCTA have very high DC sink current capability
(64 mA, commercial temperature) making the output drive
compatible with popular bus standards such as VMEbus™
and MULTIBUS®.
AC PARALLEL TERMINATION
AC parallel terminations work well for applications where
the delays caused by series terminations are unacceptable.
The terminating effects of AC parallel terminations are similar to the effects of standard parallel terminations. The major difference is that the capacitor blocks any DC current
path and helps to reduce power consumption.
FACT product inputs have been created to take full advantage of high output levels to deliver the maximum noise immunity to the system designer. VIH and VIL for ACt ACO
devices are specified at 70% and 30% of Voo respectively.
The corresponding output levels, VOH and VOL, are specified to be within O.W of the rails, of which the output is
sourcing or sinking 50 ,.,.A or less. These noise margins are
outlined in Figure 3-7.
Thevenin Termination
...L.'----""""'\.
Thevenin terminations are also not generally recommended
due to their power consumption. Like parallel termination, a
DC path to ground is created by the terminating resistors.
The power consumption of a Thevenin termination, though,
will generally not be a function of the signal duty cycle.
Thevenin terminations are more applicable for driving
CMOS inputs because they do not bias the output levels as
paralleled terminations do. It should be noted that lines with
Thevenin terminations should not be left floating since this
will cause the input levels to float between Voo or ground,
increasing power consumption.
Resistor
Resistor
Resistor
Resistor
• Parallel:
• Thevenin:
• Series:
• AC:
70%
50%7"'
---J
~50%
~
TL/F/10160-14
FIGURE 3-7, ACt ACQ Input Threshold
CMOS Bus Loading
CMOS logic devices have clamp diodes from all inputs and
outputs to Voo and ground. While these diodes increase
system reliability by damping out undershoot and overshoot
noise, they can cause problems if power is los~.
Figure 3-8 exemplifies the situation when power is removed.
Any input driven above the Voo pin will forward-bias the
clamp diode. Current can then flow into the device, and out
Voo or any output that is HIGH. Depending upon the system, this current, liN, can be quite high, and may not allow
the bus voltage to reach a valid HIGH state. One possible
solution to eliminate this problem is to place a series resistor in the line. Another possible solution would be to ensure
that the output enable input is inactive, preventing the outputs from turning on and loading down the bus. This may be
accomplished by hardwiring a 4.7 kn pull-up resistor to the
Voo pin of the FACT device.
Zo
2 x Zo
= Zo - Zout
= Zo
=
=
3tr
Capacitor = C ;;, Zo
Figure 3-6b. Suggested Termination Values
60
50 Ohm Palllnel
40
"<'
-S
Jl
lOUT
20
+.::::+=llItmouTPuT
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
TLlF/10160-15
TLlF/10160-13
FIGURE 3·8, Noise Effects
FIGURE 3-6c, FACT 100 vs Termination
3-6
Noise Effects
Crosstalk
FACT offers the best noise immunity of any competing technology available today. With input thresholds specified at
30% and 70% of Voo and outputs that drive to within
100 mV of the rails, FACT AC/ ACO devices offer noise margins approaching 30% of Voo. At 5V Voo, FACT's specified
input and output levels give almost 1.5V of noise margin for
both ground- and Voo-born noise. With realistic input
thresholds closer to 50% of Voo, the actual margins approach 2.5V.
The problem of crosstalk and how to deal with it is becoming more important as system performance and board densities increase. Crosstalk is the coupling of signals from one
line to another. The amplitude of the noise generated on the
inactive line is directly related to the edge rates of the signal
on the active line, the proximity of the two lines and the
distance that the two lines are adjacent.
Crosstalk has two basic causes. Forward crosstalk, Figures
3-9b and 3-9d, is caused by' the wavefront propagating
down the printed circuit trace at two different velocities. This
difference in velocities is due to the difference in the dielectric constants of air (E, = 1.0) and epoxy glass (E, = 4.7).
As the wave propagates down the trace, this difference in
velocities will cause one edge to reach the end before the
other. This delay is the cause of forward crosstalk; it increases with longer trace length, so consequently the magnitude of forward crosstalk will increase with distance.
Reverse crosstalk, Figures 3-9c and 3-ge, is caused by the
mutual inductance and capacitance between the lines which
is a transformer action. Reverse crosstalk increases linearly
with distance up to a critical length. This critical length is the
distance that the signal can travel during its rise or fall time.
Although crosstalk cannot be totally eliminated, there are
some design techniques that can reduce system problems
resulting from crosstalk. FACT's industry-leading noise margins make systems immune to crosstalk-related problems
easier to design. FACT's AC noise margins, shown in Figures 3-10a through 3-10f, exemplify the outstanding immunity to everyday noise which can effect system reliability .
However, even the most advanced technology cannot alone
eliminate noise problems. Good circuit board layout techniques are essential to take full advantage of the superior
performance of FACT circuits.
Well-designed circuit boards also help eliminate manufacturing and testing problems.
Another recommended practice is to segment the board
into a high-speed area, a medium-speed area and a lowspeed area. The circuit areas with high current requirements
(i.e., buffer circuits and high-speed logic) should be as close
to the power supplies as possible; low-speed circuit areas
can be furthest away.
Decoupling capacitors should be adjacent to all buffer
chips; they should be distributed throughout the logic: one
capacitor per chip. Transmission lines need to be terminated to keep reflections minimal. To minimize crosstalk, long
signal lines should not be close together.
•
TLlF/10160-61
• Two parallel signal lines provide mutual inductance and shunt capacitance
FIGURE 3-9a. Where Does Crosstalk Take Place?
3-7
en
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Crosstalk (Continued)
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Active
c0)
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Q
Passive
TLlF/l0160-62
v
• Current through the Characteristic Inductance of Transmission Line = IL
• Capacitively Coupled Current
~
Ie
~
-C dVi/dt
A
• Mutually Induced Current ~ 1M ~ mil
BI------J
• Forward Crosstalk Current = ICF
• As the active signal, Vi. propagates from A to 8 a negative-going spike, Vf.
propagates from C to D, coincident with Vi.
DI-----~,~--
TLlF/l0160-63
FIGURE 3-9b, Forward Crosstalk-Refresher
Active
Passive
Tl/F/l0160-64
v
• Current through the Characteristic Inductance of Transmission Line = IL
A
• Capacitively Coupled CUrrent ~ Ie ~ -C dV11 dt
• Mutually Induced Current
~
• Reverse Crosstalk Current
1M
=
~
mil
Bt-----'
leA
c
• As the active signal. Vi. propagates from A to B a positive pulse appears at
C for a duration twice the coupled line delay T.
Tl/F/l0160-65
FIGURE 3-9c, Reverse Crosstalk-Refresher
3-8
c
m
Crosstalk (Continued)
~.
:::J
o
o
:::J
UI
is:
CD
it
O·
:::J
UI
Time (ns) (5.0 ns/dlv)
lID
---Active Driver
- - - - - Forward Crosstalk
- - - Active Receiver
VertiCal Seql'
Hodzontgl Scgll.
1.0 V/Olv
0.2 V/Olv
1.0 V/Olv
SOns/OIv
S.Ons/Olv
S.Ons/Olv
TUF/10160-16
This figure shows traces taken on a test fixture designed to exaggerate the amplitude of crosstalk pulses.
FIGURE 3-9d. Forward Crosstalk on PCB Traces
~I
.'"
~
I
~
I
I
I
o.ov
,
~\
1---
-tLJ.
•
I
Time (ns) (5.0 ns/dlv)
~)!
---Active Driver
- - - - Reverse Crosstalk
---Active Receiver
Vertlco! Seqla
Horlzontgl Scgla
1.0 V/Olv
0.2 VIDlv
1.0 V/Olv
SOns/OIv
S.Ons/DIv
S.Ons/DIv
TL/F/10160-17
This figure shows traces taken on a test fixture designed to exaggerate the amplitude of crosstalk pulses.
FIGURE 3-ge. Reverse Crosstalk on PCB Traces
3-9
III
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Crosstalk (Continued)
Length = L
I
I1""'>-----Coupled
Line Delay =T_ _ _-I_
Active Line
~~A~""""pa·s·sw·e·L·ln·e·:::J"-P"""""""~I~
Q)
o
TL/F/l0160-18
Noise Pulses at A:
For T > tr Noise
Reaches Max Amplitude
TLlF/l0160-19
ForT
~
O.St,
Noise Just
Reaches Max
at Peak
TL/F/l0160-20
ForT < O.St,
Noise Never
Reaches Full
Amplitude
TL/F/l0160-21
FIGURE 3-9f, partially Coupled Lines
VOO =5.0V
4 Volts from VOO
'"
3
2
TL/F/l0160-22
o
FIGURE 3-10a, High Noise Margin
o
5
HAzlRO
i--
10
SAFE
15
20
25
30
35
40
45
50
Pu Ise Width (ns)
TL/F/l0160-23
FIGURE 3-10b, FACT ACtACa High Noise Margin
3-10
c
m
Crosstalk (Continued)
IS'
:::s
VOLTS FROM VOO
VOLTS
6
Vo~ = 5.0V
5
\,
4
oo
:::s
en
SAFE
a:
CD
ji;
=
o
:::s
HA+D
'"
HAZARD
3
VOO=5.0V
3
I
en
SAFE
2
o
o
o
2
10
12
14
16
18
20
o
5
10
15
20
25
30
35
40
45
50
PULSE WIDTH (ns)
PULSE WIDTH (ns)
TL/F/l0160-25
TLlF/l0160-66
FIGURE 3-10e. FACT ACI ACQ Low Noise Margin
FIGURE 3-10c. FACT ACT/ACTQ/FCT/FCTA
High Noise Margin
VOLTS
3
Voo = 5.0V
\
~r-VOO
V---70%
\....
HAZARD
SAFE
o
o
TL/F/l0160-24
FIGURE 3-10d. Low Noise Margin
2
6
8
10
12
14
16
18
20
PULSE WIDTH (ns)
TL/F/l0160-26
FIGURE 3-10f. FACT ACT/ACTQ/FCT/FCTA
Low Noise Margin
With over 2.0V of noise margins, the FACT family offers
better noise rejection than any other comparable technolo·
gy.
talk can be minimized by line termination. Terminating a line
in its characteristic impedance reduces the amplitude of an
initial crosstalk pulse by 50%. Terminating the line will also
reduce the amount of ringing. Crosstalk problems can also
be reduced by moving lines further apart or by inserting
ground lines or planes between them.
In any deSign, the distance that lines run adjacent to each
other should be kept as short as possible. The best situation
is when the lines are perpendicular to each other. For those
situations where lines must run parallel, the effects of cross•
Synchronous
Signal Plane
-
=
Ground Traces
Synchronous
Signal Trac.s
l1li Synchronous
Signal Plane
•
Ground Plane
II1I1I Asynchronous
Signal Plane
- - Asynchronous Signal Trac.s
on Plan. D can run In
any direction
TL/F/l0160-27
FIGURE 3-11a. Recommended Crosstalk-Avoidance Structure
3-11
•
o
C
~
.-------------------------------------------------------------------------------~
For most power distribution networks, the typical impedance
is between 500 and 1000. This impedance appears In series with the load impedance and will cause a droop in the
Voo at the part. This limits the available voltage swing at the
local node, unless some form of decoupling is used. This
drooping of rails will cause the rise and fall times to become
elongated. Consider the example described in Figure 3-13
to calculate the amount of decoupling necessary. This circuit utilizes an 'AC240 driving a 1000 bus from a point
somewhere in the middle.
Crosstalk (Continued)
r-S--j
CD
~
o
o
c
en
~
Gnd
•
•
•
•
Minimize parallel trace lengths
Maximize distance "5" between traces to minimize crosstalk
Add ground trace ~ between signal traces
Minimize distance h to kesp line Impedance low
Buffer Oulput Sees Net 50n Load.
50n Load Une on 'OH-VOH
Characteristic.
Shows Low-Io-High Step of
Approx. 4.8V.
Data Bus
lOon.
r-
TL/F/l0160-32
FIGURE 3-11 b. PCB Layout Tips
for Crosstalk Avoidance
Ground
Plane
Decoupling Requirements
VOUT
O.W
;:
h
1 of 8
National Semiconductor Advanced CMOS, as with other
high·performance, high-drive logic families, has special decoupling and printed circuit board layout requirements. Adhering to these requirements will ensure the maximum advantages are gained with FACT products.
Local high frequency decoupling is required to supply power
to the chip when it is transitioning from a LOW to HIGH
value. This power is necessary to charge the load capacitance or drive a line impedance. Figure 3-12 displays various Voo and ground layout schemes along with associated
impedances.
....
10H
4•9V
--1 i
Buffer
:--- 4ns
94mA
-1 L
A
100A
TL/F/l0160-44
TL/FI10160-43
Worst·Case Octal Orain = 8
= 0.75 Amp.
x 94 mA
FIGURE 3-13. Octal Buffer Driving a 1000 Bus
d)50A Voo
Impedance
~"
Board
c) 1000 Voo
Impedance
~"
Board
b)68A Voo
Impedance
~ .. Board
a) l00A VOO
Impedance
.032"
Epoxy Glass
e)2A Voo
Impedance
TL/F/l0160-42
FIGURE 3-12. Power Distribution Impedances
3-12
~
Decoupling Requirements (Continued)
Being in the middle of the bus, the driver will see two 100n
loads in parallel, or an effective impedance of 50n. To
switch the line from rail to rail, a drive of 94 mA is needed;
more than 750 mA will be required if all eight lines switch at
once. This instantaneous current requirement will generate
a voltage drop across the impedance of the power lines,
causing the actual Voo at the chip to droop. This droop
limits the voltage swing available to the driver. The net effect of the voltage droop will lengthen device rise and fall
times and slow system operation. A local decoupling capacitor is required to act as a low impedance supply for the
driver chip during high current conditions. It will maintain the
voltage within acceptable limits and keep rise and fall times
to a minimum. The necessary values for decoupling capacitors can be calculated with the formula given in Figure 3-14.
In this example, if the Voo droop is to be kept below 30 mV
and the edge rate equals 4 ns, a 0.10 ,..F capacitor is needed.
It is good practice to distribute decoupling capacitors evenly
through the logic, placing one capacitor for every package.
,
I
I
--~_........
I
I
I
GND
: T~ :
iQ'
:::I
o
o
Zoo
:::I
In
a:
CD
ii1
O·
Q = CV
= CIJ.V/lJ.t
~t: 1!~1J.~0_9
I
:::I
In
Bypass Capacitor
Specify Yoo Droop
C = 0.750 x 4 X 10- 9
0.03
= 30 mY Max
100 X 10-9
Tl/F/l0160-45
= a.100 r.. F
Select Cs ;, 0.10 p.F
FIGURE 3-14, Formula for Calculating
Decoupllng Capacitors
Capacitor Types
Decoupling capacitors need to be of the high K ceramic
type with low equivalent series resistance (ESR), consisting
primarily of series inductance and series resistance. Capacitors using 5ZU dielectric have suitable properties and make
a good choice for decoupling capacitors; they offer minimum cost and effective performance.
-~ -~ ... -~~-~ -~ ~ ... ~~
CaULK (A)
I
TL/F/l0160-28
• Need to decouple board at the pOint 01 power supply enlry
• This capacitor (AI will smooth low frequency bulk switching noise
• A large value electrolytic capacitor is typically used (50 p.F-l00 p.F)
FIGURE 3-15. Board-Level Decoupllng Capacitor
3-13
II)
c
o
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CI
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Q)
C
Electromagnetic Interference
quency domain. To think in terms of EM I, one must think in
terms of the frequency domain. This illustration helps to realize the role of the time domain signal components in the
irequency domain. Notice that ,as the signal's period decreases, duty cycle decreases, or rise/fall time decreases
that the, radiated bandwidth increases.
On the circuit level, in addition to the signal component factors mentioned earlier, radiating area, and the resultant antenna's radiating efficiency also play an important role in
EMI generation. Also, current spikes, power line noise, and
output ringing caused by outputs switching also contribute
to the overall EMI. Good design techniques that moderate
this noise will playa major role in minimizing radiated EMI.
One of the features of advanced CMOS is its fast output
edge rates. For the first time a non-ECl logic family is capable of switching, outputs at ECl speeds: In fact, advanced
CMOS edge rates exceed that of ECL. ECl outputs typically
swing 900 mV in 700 ps, translating into an edge rate of
1.3 V/ns. Advanced CMOS outputs, on the other hand,
swing 5.0V in approximately 3.0 ns, translating into an edge
rate of 1.6 VIns. logic families driving at these speeds,
however, are more prone to generate higher levels of system noise. Electronic systems using advanced CMOS logic,
as with any other high performance logic system, require a
higher level of design considerations.
One element of system noise that will be discussed here is
referred to as Electromagnetic Interference,' or EMI. The
level of EMI generated from a 'system can be greatly reduced with the use of proper Electromagnetic Compatibility
(EMC) design techniques. These design considerations begin at the circuit board level and continue through the system level to the enclosures themselves; EMC needs to be a
concern at the initial system design stage.
OVERALL SYSTEM EMI
System EMI is a function of the current loop area. Some of
the largest loOp areas in a system consist of circuit board
signal transmission lines, backplane transmission lines, and
I/O cables. The current loop areas of the integrated circuit
packages--VDD-to-GND loops--are small in comparison to
those of the transmission lines and I/O cables. Differences
in IC package pinout schemes are much less noticeable in
terms of overall system radiated EM I.
WHAT IS EMI/RFI?
Electromagnetic Inter:ference, or EMI, is an electrical phenomenon where electric ,field energy and magnetic field energy are transmitted from one source to create interference
of transmitted and/or received signals from another source.
This may result in the information becoming distorted.
EMI can be an issue of emissions, that is, energy radiated
from one system to another or within the same system. It
can also be an issue of susceptibility, from high powered
microwave signals or 'nuclear EMP (Electromagnetic
Pulse)-an issue more applicable in the military arena than
commerc'ial. While this section will specifically address radiated energy, many comments may also apply to susceptibility.
The formula used to model the maximum electric field is
listed below. This formula takes into account the antenna
dimension and efficiency as well as the basic signal components.
IEIMax = 1.32 X
W-3~I.A.Freq2
[1
+ G1TD)2
]%':
where,
IEIMax is the maximum E-field in the plane of the loop
I is the current amplitude in milliamps
A is the antenna area in square cm
A is the wavelength at the frequency of interest
D is the observation distance in meters
Freq is the frequency in MHz
and the perimeter of the loop P ..:: A.
Figures 3-18a and 3-18b illustrate lab measurements of radiated emissions from a test board populated with FACT,
FACT as, and a competitor's ACMOS logic. The device
under test is driving a similar device across 26 cm of printed
circuit board trace.
At higher frequencies where, for example, quarter wavelengths approach the lengths of transmission lines common
in typical backplanes and plug-in cards, FACT as with its
innovative noise supressions circuitry radiates substantially
less EMI than other ACMOS logic.
SOURCES OF ELECTROMAGNETIC INTERFERENCE
EMI generation in an electronic system may result from several sources. All mediums of signal transmission-from the
signal origin to its destination-are possible sources of radi- ,
ated EMI. Understanding how each medium-including ICs,
coaxial cables, and connectors-can radiate EMI is paramount ineffective, high performance system design.
As Figure 3-16 illustrates, EMI in a typical electronic circuit
is generated by a current flowing in some current path configured within the circuit. These paths can be either VDD-toGND loops or output transmission lines. The propagating
current pulse creates magnetic field energy, while the voltage drop across the loop area creates electric field energy.
The current path material itself acts as an antenna radiating-or receiving-both the electric and magnetic fields.
CIRCUIT BOARD DESIGN CONSIDERATIONS
EMI generation is a function of several factors. Transmitted
signal frequency, duty cycle, edge rate, and output voltage
swings are the major factors of the resultant EMI levels.
Figure 3-17 illustrates a generalized Fourier transformation
of the transmitted signal from the time domain to the fre-
Original eqUipment manufacturers cannot afford to fail electromagnetic emissions tests. Since these tests are measured outside of the system, precautions to shield the enclosures, I/O cables, and connections are paramount. However, EMI within a system may also cause errors in data trans-
3-14
c
(I)
Electromagnetic Interference (Continued)
mission or unreliable system operation. Therefore, good
EMC design techniques at the circuit board level are just as
necessary.
til
• Decoupling the power supply at the point of entry onto
the printed circuit board is also highly recommended.
The use of a low equivalent series inductance, or ESL,
multilayer ceramic capacitor, 50 ,...F to 100 ,...F, provides
good low to medium frequency filtering and EMI suppression.
o To further suppress power supply noise and associated
EMI throughout the circuit board itself, the use of a low
ESL chip capacitor for each IC is highly recommended.
Because the location of any transient noise on a power
or ground plane would be impossible to predict, and the
IC density of different circuit boards vary dramatically,
every IC on these circuit boards should be adequately
decoupled. A 0.10 ,...F chip capacitor, located as close to
each ground pin as possible, will provide good high frequency power supply noise filtering and added EMI suppression.
Designing a system free of all EMI is an overwhelming task.
However, considering the following design recommendations at the circuit board level forms a good foundation on
which to design a system with good EMC.
o The use of multilayer printed circuit board is a virtual ne-
cessity. Two-sided printed circuit board and wire-wrap
boards provide no shielding of EMI. Two-sided boards
also do not allow the use of power and ground planes.
Instead they require the use of high impedance power
and ground traces. Planes provide impedances several
orders of magnitude lower than that of traces, reducing
transient voltage drops in the power distribution and return loops. As a result of these lower voltage drops, power supply induced EMI can also be reduced.
o In addition to the reduced impedance, these power and
ground planes have an inherent EMI shielding effect that
the large areas of copper provide. With the use of striplines or signal transmission lines sandwiched between
the power and ground planes, the designer can take full
advantage of the planes' shielding capabilities. To maximize this shielding effect, keep the power and ground
plane areas as homogeneous as possible.
o Since plastic provides no EMI shielding, and sockets of
any profile provide plenty of lead length, ICs should be
soldered directly to the board. Solder power and ground
pins directly to the power and ground planes, respectively. Minimize the IC and associated component lead
lengths wherever possible.
o Minimizing the number of simultaneously switching outputs will also help to moderate the current pulse amplitude and output ringing.
o Terminating signal traces longer than 6 inches (typical)
will minimize reflections and ringing due to those reflections.
BACKPLANE CONSIDERATIONS
The above discussion emphasized design techniques for
printed circuit boards. However, because the backplane
may, and usually does, consist of several long signal transmission lines, the same low noise design techniques should
be used.
o Multilayer board techniques should also be applied to the
backplane. If possible, these transmission lines should
be shielded individually. This would allow for a denser
parallel layout of transmission lines as well as providing
good EMC.
o Use multiple ground and power connections from the
backplane to the circuit boards' power and ground
planes to minimize the connection impedance. This will
help to further suppress any source of power supply generated EMI.
SYSTEM CONSIDERATIONS
One of the major sources of radiated system EMI are the
edge connectors, I/O cables, and their associated connectors.
o Use care to ensure that, not only the cables are shielded
and the shield properly grounded, but that the shield totally envelopes both the cable and its connectors. The
shield should seat firmly into a grounded chassis and
touch the chassis a full 360· around the connection. An
open ended cable or an improperly grounded connector
shield will be a prime suspect for out-of-spec EMI emissions and should be avoided. Use shielded coaxial cables whenever possible. If ribbon cable is preferred,
shield all ribbon cables with commercially available ribbon cable shielding. Again, ensure that this shield is
properly attached to the connector shield by a full 360·.
• In choosing or designing the enclosure for the system,
minimize the number of openings in the enclosure. Since
high performance logic now deals with smaller wavelengths than the older technologies, enclosure opening
sizes should also be considered. Keep openings as small
as possible. If openings are necessary (displays, controls, fans, etc.) there are commercially available accessories that offer good built-in EMI shielding.
• Avoid capacitively coupling signals from one transmission line to another-crosstalk-by avoiding long parallel
signal transmission lines. If parallel transmission lines are
unavailable, maximize the distance between the two
lines, or insert a ground trace. Minimizing the spacing
between the signal plane and ground plane will also help
reduce crosstalk. For more details, see section on Crosstalk.
POWER SUPPLY DECOUPLING CONSIDERATIONS
Much of a system's radiated EMI may originate from the
power supply itself. Propagation of power supply noise
throughout a system is a very undersirable situation in any
respect, including EMI. Suppression of this power supply
noise is highly recommended. Oecoupling the power supply
at every level, from the system supply distribution network,
down to the individuallC, is also a necessity when designing
for low noise-and low EMI.
o On the system level, the use of a tantalum or aluminum
electrolytic capacitor in the power supply distribution network is recommended.
• If access panels are necessary, ensure that these panels
are properly sealed with some sort of shielding material
(gaskets, copper brushes, etc.).
• Of course, the enclosure itself should be of a material
that provides good shielding against electric fields.
3-15
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Electromagnetic Interference (Continued)
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Magnetic Field H
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Electric Field E
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z
TL/F/l0160-46
FIGURE 3-16. EMI is Generated by a Current Flowing along Some Path (Loop)
Time Domain: Trapezoidal Pulse Train
Amplitude
(Volts or Amps)
a.9~ F=====::::::;r-,
• T ~
• Tr
Pulse Width HIGH
= Rise Time
• Tf ~ Fall
a.SA I-----~M_-
a.1A 1------1
nme
-----f---+t-+------t-:-f'----f-- (Seconds)
Time
• T ~ Period
• A
= Amplitude
TL/F/l0160-47
Frequency Domain: Worst-Case Upper Bound Approximation
Amplitude (dB)
Linear scale
2A61----.....,.....
__-+-__________
L..-_ _ _ _L..---"-_ _ _ _ _ _ _ _ _ _. -
• " ~ 1st Breakpoint
~ 2nd Breakpoint
• 8 ~ Duly Cycle ~ TIT
•'2
f1
= _1_
1M'
f2
= _1_
Frequency
(Hertz)
Log Scale
IM'r
TL/F/l0160-48
FIGURE 3·17, Time Domain to Frequency Domain Conversion
3-16
0
CD
Electromagnetic Interference (Continued)
UI
/Q'
=
0
0
=
60
UI
c:::::J FACT ACT244 EMI
50
_
FACT ACTQ244 EMI
- - 1/4 Wavelength
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40
30
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20
10
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5
105
205
305
405
505
Frequency (MHz)
(Fundamental Freq. 5 MHz)
=
TL/F/l0160-49
FIGURE 3·18a. FACT Radlatlon-ACTQ244 versus ACT244
60
c:::::J COMPETITOR EMI
_
FACT ACTQ244 EMI
- - 1/4 Wavelength
~
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50
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40
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0
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20
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10
0
5
105
305
205
405
505
Frequency (MHz)
(Fundamental Freq. = 5 MHz)
TL/F/l0160-50
FIGURE 3·18b. FACT Radlatlon-ACTQ244 versus Competition
TTL-Compatible CMOS Designs Require Delta 100 Consideration
The FACT product line is comprised of two types of advanced CMOS input circuits: 'AC/'ACQ and 'ACT/'ACTQ/
'FCT/'FCTA devices. 'ACT/, ACTQ/'FCT/'FCTA indicates
an advanced CMOS device with TIL-type input thresholds
for direct replacement of LS and ALS circuits. As these
'ACT/'ACTQ/'FCT/'FCTA series are used to replace TIL,
the lOOT or Delta 100 specification must be considered; this
spec may be confusing and misleading to the engineer unfamiliar with CMOS. In many datasheets lOOT or Delta 100 are
also referred to as ICCT or Delta Icc. There are no other
differences.
type with an n-channel transistor in a series with a
p-channel transistor as illustrated below.
voo
INPUT PAD
TO
1---" LOGIC
INTERNAL
It is important to understand the concept of Delta 100 and
how to use it within a design. First, consider where Delta 100
initiates. Most CMOS input structures are of the totem pole
TL/F/l0160-52
FIGURE 3·19. CMOS Input Structure
3-17
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TTL-Compatible CMOS
Designs Require Delta 100
Consideration (Continued)
The Delta 100 specification is the increase in 100. For each
input at Voo - 2.1V (approx. TTL VOH level), the Delta 100
value should be added to the quiescent supply current to
arrive at the circuit's worst-case static 100 value.
These two transistors can be modeled as variable resistors
with resistances varying according to the input voltage. The
resistance of an ON transistor is approximately 4 kn while
the resistance of an OFF transistor is generally greater than
500 Mn. When the input to this structure is at either ground
or Voo, one transistor will be ON and one will be OFF. The
total series resistance of this pair will be the combination of
the two individual resistances, greater than 500 Mn. The
leakage current will then be less than 1 pA When the input
is between ground and Voo, the resistance of the ON transistor will increase while the resistance of the OFF transistor
will decrease. The net resistance will drop due to the much
larger value of the OFF resistance. The total series resistance can be as low as Boon. This reduction in series resistance of the input structure will cause a corresponding increase in 100 as current flows through the input structure.
The following graph depicts typical 100 variance with input
voltage for an 'ACT device.
1.0
{ r\
I \
I
!
J
Fortunately, there are several factors which tend to reduce
the increase in 100 per input. Most TTL devices will be able
to drive FACT inputs well beyond the TTL output specification due to FACT's low input loading in a typical system.
FAST logic outputs can drive 'ACT-type inputs down to
200 mV and up to 3.5V. Additionally, the typical 100 increase
per input will be less than the specified limit. As shown in
the graph above, the 100 increase at Voo - 2.1 V is less
than 200 /LA in the typical system. Experiments have shown
that the 100 of an 'ACT240 series device typically increases
only 200 /LA when all of the inputs are connected to a FAST
device instead of ground or Voo.
It is important when designing with FACT, as with any TTLcompatible CMOS technology, that the Delta 100 specification be considered. Designers should be aware of the
spec's significance and that the data book specification is a
worst-case value; most systems will see values that are
much less.
,
Testing Advanced CMOS Devices
with 1/0 Pins
1\
\
There are more and more CMOS families becoming available which can replace TTL circuits. Although testing these
new CMOS units with programs and fixtures which were developed for bipolar devices will yield acceptable results
most of the time, there are some cases where this approach
will cause the test engineer problems.
1\
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/
0.0
"\, 1"'-.
I
o
Such is the case with parts that have a bidirectional pin,
exemplified by the '245 Octal Transceiver. If the proper testIng methods are not followed, these types of parts may not
pass those tests for 100 and input leakage currents, even
when there Is no fault with the devices.
CMOS circuits, unlike their bipolar counterparts, have static
100 specification orders of magnitude less than standard
load currents. Most CMOS 100 specifications are usually
less than 100 /LA. When conducting an 100 test, greater
care must be taken so that other currents will not mask the
actual 100 of the device. These currents are usually sourced
from the inputs and outputs.
5.0
TL/F/10160-53
FIGURE 3-20,100 versus Input Voltage for 'ACT Devices
5.0
('
/
V
/
0.0
o
./
/
I
II 1\
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Since the static 100 requirements of CMOS devices are so
low, output load currents must be prevented from masking
the current load of the device during an 100 test. Even a
standard 500n load resistor will sink 10 mA at 5V, which is
more than twice the 100 level being tested. Thus, most manufacturers will specify that all outputs must be unloaded during 100 tests.
Another area of concern is identified when considering the
inputs of the device. When the input is in the transition region, 100 can be several orders of magnitude greater than
the specification. When the input voltage is in the transition
region, both the n-channel and the p-channel transistors in
the input totem-pole structure will be slightly ON, and a conduction is created from Voo to ground. This conduction path
\
1\
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5.0
TL/F/10160-54
FIGURE 3-21.100 versus liN for 'AC Devices
3-18
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Testing Advanced CMOS Devices
with 1/0 Pins (Continued)
III
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:::I
Testing CMOS circuits is no more difficult than testing their
bipolar counterparts. However, there are some areas of
concern that will be new to many test engineers beginning
to work with CMOS. Becoming familiar with and understanding these areas of concern prior to creating a test philosophy will avert many problems that might otherwise arise later.
leads to the increased IDO current seen in the 100 vs VIN
curve. When the input is at either rail, the input structure no
longer conducts. Most 100 testing is done with all of the
inputs tied to either VOD or ground. If the inputs are allowed
to float, they will typically float to the middle of the transition
region, and the input structure will conduct an order of magnitude more current than the actual 100 of the device under
test which is being measured by the tester.
When testing the 100 of a CMOS '245, problems can arise
depending upon how the test is conducted. Note the structure of the '245's I/O pins illustrated below.
o
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III
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III
Testing Disable Times of
TRI-STATE® Outputs in a
Transmission Line Environment
Traditionally, the disable time of a TRI-STATE buffer has
been measured from the 50% point on the disable input, to
the (VOL + 0.3V) or (VOH - 0.3V) point on the output. On a
bench test site, the output waveform is generated by a load
capacitor and a pull-up/pull-down resistor. This circuit gives
an RC charge/discharge curve as shown below.
TL/F/l0160-55
FIGURE 3-22. '245 I/O Structure
Each I/O pin is connected to both an input device and an
output device. The pin can be viewed as having three
states: input, output and output disabled. However, only two
states actually exist.
The pin is either an input or an output. When testing the 100
of the device, the pins selected as outputs by the T /R signal
must either be enabled and left open or be disabled and tied
to either rail. If the output device is disabled and allowed to
float, the input device will also float, and an excessive
amount of current will flow from VOO to ground. A simple
rule to follow is to treat any output which is disabled as an
input. This will help insure the integrity of an 100 test.
Another area which might precipitate problems is the measurement of the leakages on I/O pins. The I/O pin internal
structure is depicted below.
The pin is internally connected to both an input device and
an output device; the limit for a leakage test must be the
combined liN specification of the input and the loz specification of the output. This combined leakage test is defined
as 10ZT. For FACT devices, liN is specified at ± 1 }J-A while
loz is specified at ± 5 }J-A. Combining these gives a limit of
±6 }J-A for I/O pins. Usually, I/O pins will show leakages
that are less than the loz specification of the output alone.
2
3
4
5
6 7 8
nme {ns}
9
10
11
12
TL/~/l0160-57
FIGURE 3-24. Typical Bench TRI-STATE Waveform
ATE test sites generally are unable to duplicate the bench
test structure. ATE test loads differ because they are usually
programmable and are situated away from the actual device. A commonly used test load is a Wheatstone bridge.
The following figure illustrates the Wheatstone bridge test
structure when used on the MCT 2000 test-system to duplicate the bench load.
•
Voo
OUT
TL/F/l0160-56
TL/F/l0160-56
FIGURE 3-23. I/O Pin Internal Structure
FIGURE 3-25. MeT Wheatstone Bridge Test Load
3-19
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Testing Disable Times of TRI-STATE® Outputs in a
Transmission Line Environment (Continued)
The voltage sourcE! provides a pull-up/pull-down voltage
while the current sources provide IOH and IOL. When devices with slow output slew rates are tested with the ATE load,
the resultant waveforms closely approximate the bench
waveform, and a high degree of correlation can be
achieved. However, when devices with high output slew
rates are tested, different results are observed that make
correlating tester results with bench results more difficult.
This difference is due to the transmission line properties of
the test equipment. Most disable tests are preceded byestablishing a current flow through the output structure. Typically, these currents will be between 5 mA and 20 mAo The
device is then disabled, and a comparator detects when the
output has risen to the (VOL + 0.3V) level or fallen to the
(YOH - 0.3V) level.
Transmission line theory states the voltage level of this current wave is equal to the current in the line times the impedance of the line. With typical currents as low as 5 mA and
impedances of 50n to 60n, this voltage step can be as
minimal as 250 mY. If the comparator was programmed to
the disable measurement points, it would be looking for a
step of approximately 575 mV at 5.5V VDD. Three reflections of the current pulse would be required before the comparator would detect the level. It is this added delay time
caused by the transmission line environment of the ATE
that may cause parts to fail customer's incoming tests, even
though the device meets specifications. The figure below
graphically shows this stepout.
Point A represents the typical 50% measurement point on
tester driven waveforms. Point B reprsents the point at
which the delay time would be measured on a bench test
fixture. Point C represents where the delay time could be
measured on ATE fixtures. The delay time measured on the
ATE fixture can vary from the bench measured delay time to
some greater value, depending upon the voltage level that
the tester is set. If the voltage level of the tester is close to
voltage levels of the plateaus, the results may become nonrepeatable.
Consider the situation where the connection between the
device under test (DUn and the comparator is a transmission line. Visualize the device output as a switch; the effect
is easier to see. There is current flowing through the line,
and then the switch is opened. At the device end, the reflection coefficient changes from 0 to 1. This generates a current edge flowing back down the line equal to the current
flowing in the line prior to the opening of the switch. This
current wave will propagate down the line where it will encounter the high impedance tester load. This will cause the
wave to be reflected back down the line toward the OUT.
The current wave will continue to reflect in the transmission
line until it reaches the voltage applied to the tester load. At
this point, the current sourcE! impedance decreases and it
will dissipate the current. A typical waveshape on a modern
ATE is depicted in Figure 3-26.
Of
2
j
3
4
5
6
7
8
9
10
11
12
ABC
TIm. (ns)
TLlF/l0160-60
FIGURE 3-27" Measurement Stepout
2
3
4
5
6
7
8
9
10
11
12
TIm. (ns)
TLlF/l0160-59
FIGURE 3-26_ Typical ATE TRI-STATE Waveform
3-20
lao
z
Understanding Latch-Up
in Advanced CMOS Logic
National Semiconductor
Application Note 600
Latch-up has long been a bane to CMOS IC applications; its
occurence and theory have been the subjects of numerous
studies and articles. The applications engineer and systems
designer, however, are not so much concerned with the theory and modeling of latch-up as they are with the consequences of latch-up and what has been done by the device
designer and process engineer to render ICs resistant to
latch-up.
this case the depletion layer formed around the reverse-biased PN junction between P-well and the substrate supports the majority of the Vee-Gnd voltage drop. As long as
the MOS source and drain junctions remain reverse-biased,
CMOS is well behaved. In the presence of intense ionizing
radiation, thermal or over-voltage stress, however, current
can be injected into the PNP emitter-base junction, forwardbiasing it and causing current to flow through the substrate
and into the P-well. At this point, the NPN device turns on,
increasing the base drive to the PNP. The circuit next enters
a regenerative phase and begins to draw Significant current
from the external network thus causing most of the undesirable consequences of latch-up. Once established, a latchup site, through the fields generated by the currents being
conducted, may trigger similar action in both elements of
the IC.
Of equal interest are those precautions, if any, which must
be observed to limit the liability of designs to latch-Up.
WHAT IS LATCH-UP?
Latch-up is a failure mechanism of CMOS (and bipolar) integrated circuits characterized by excessive current drain coupled with functional failure, parametric failure and/or device
destruction. It may be a temporary condition that terminates
upon removal of the exciting stimulus, a catastrophic condition that requires the shutdown of the system to clear or a
fatal condition that requires replacement of damaged parts.
Regardless of the severity of the condition, latCh-up is an
undesirable but controllable phenomenon. In many cases,
latch-up is avoidable.
The cause of the latch-up exists in all junction-isolated or
bulk CMOS processes: parasitic PNPN paths. Figure 1, a
basic CMOS cross section, shows the parasitiC NPN and
PNP bipolar transistors which most frequently participate in
latch-up. The P+ sources and drains of the P-channel MOS
devices act as the emitters (and sometimes collectors) of
lateral PNP devices; the N-substrate is the base of this device and collector of a vertical NPN device. The P-well acts
as the collector of the PNP and the base of the NPN. Finally, the N + sources and drains of the N-channel MOS devices serve as the emitter of the NPN. The substrate is normally connected to Vee, the most positive circuit voltage, via an
N + diffusion tap while the P-well is terminated at Gnd, the
most negative circuit voltage, through a P + diffusion.
These power supply connections involve bulk or spreading
resistance to all points of the substrate and P-well.
Normally, only a small leakage current flows between the
substrate and P-well causing only a minute bias to be built
up across the bulk due to the resistivity of the material. In
&,
o
o
WHAT TO DO
As might be expected, latCh-up is highly dependent on the
characteristics of the bipolar devices involved in the latchup loop. Device current gains, emitter effiCiencies, minority
carrier life times and the degree of NPN-PNP circuit coupling are all important factors relating to both the sensitivity
of the particular latch-up device and to the severity of the
failure once it has been excited. Layout geometry and process both contribute significantly to these parameters;
CMOS, like other technologies, has been shrunk to provide
more function per unit area, increaSing susceptibility to
latch-up. All major CMOS vendors have upgraded their processes and/or design rules to compensate for this increased susceptibility, some with more success than others.
The lateral PNP is typically the weak link in the latch-up
loop. As such, various devices can be exploited toward reducing the effectiveness of the PNP to partiCipate in latchup. Guard banding, device placement, the installation of
pseudo-collectors between the P-channel devices and the
P-well, and the use of a low resistivity substrate under an
epitaxial layer are a few of the IC design tactics now being
practiced to reduce the current gain or to control the action
of the lateral PNP structures in state-of-the-art CMOS devices.
P-Channel MOS
•
N-Channel MOS
N Substrate
(6-10 ohm-em)
TLlF/10192-1
FIGURE 1. Basic CMOS Inverter Cross Section with Latch-Up Circuit Model
3-21
tors to distribute thermal stress over a larger area or multiple ICs are all positive-preventive measures to exploit.
Vendors of CMOS ICs have always been aware of the latchup phenomenon and have considerably improved their designs and processes to reduce the danger of latch-up occuring under normal usage. Abnormal applications and misuse
of CMOS ICs may still pose problems that the CMOS vendor has little control over. Hence, CMOS users must be
aware of what they are dOing and those measures which
must be taken to reduce the susceptibility to latch-up. The
use of CMOS at or beyond its rated maximum voltage range
and the presence of inductive transients are applications-related situations which can trigger latch-up. Environment, including thermal stress, poorly regulated or noisy supplies
and radiation incidence can also contribute to or cause
latch-up. The system engineer must consider these situations when using CMOS in designs.
While we have been considering the CMOS device in a generic manner, there are two primary structures used in all
CMOS ICs which have latch-up paths associated with them;
these are the inverter or gate and the transmission switch.
Both structures may be susceptible under the right conditions. While the CMOS inverter can· exhibit latch-up independent of circuit configuration, the transmission switch
usually has lower holding current, and thus, a lower threshold for latch-up, but is dependent on its external connections for latch-up to occur. Figure 2 shows the lumped
equivalent circuit of the inverter. Notice the shunting resistors across the base-emitter junctions of the bipolar transistors: these resistors divert base drive from the bipolars and
as a result increase both the trigger current and holding
current levels required for the structures to participate in
latch-up. A further increase in these current levels can be
achieved by further decreasing the shunt resistance. Diffusing all active components into an epitaxial silicon, under
which would lie a substrate of substantially less resistivity,
will have a dramatic effect on decreasing the shunt resistance, therefore increasing the trigger current and holding
current levels required for latch-Up.
While latch-up is generally recognized as resulting from regenerative switching along a PNPN path, many designers
incorrectly assume that this regenerative action places the
device in a state that can only be recovered from if the
system is powered down. The fact is that there is probably
an equal, if not greater, chance that the regenerative switching, when encountered, will be non-sustaining (the condition, more accurately referred to as current amplification,
will disappear when the triggering stimulus is removed);
over-voltage applied to properly designed input protection
networks is one example of controlled current amplification.
For sustained latch-up to occur, the regeneration loop must
have sufficient gain and the power source must be able to
supply a minimum current. From this we can see that current-limited power supplies might be used to recover from or
reduce the effects of latch-up. Another method uses current-limiting series resistors in the power connections of offending ICs in conjunction with storage capacitors shunting
the devices. Normal switching current will be drawn from the
capacitors while DC current will be limited by the resistors.
THE CIRCUIT CONNECTION
As we have seen above, the external circuit connections are
regular participants in the latch-up process. The current for
latch-up comes from these connections and often the triggering mechanism is external to the latching device. All
three classes of external connections (power, input and output) are important in latch-up. We will now look at how these
connections relate to this process.
Current injection through the power terminals when the
power supply voltage is beyond the maximum rated for the
CMOS device can directly cause latch-up through base collector leakage or breakdown mechanisms. One aspect of
high power supply voltages that is not often recognized is
the effect of field-aiding lateral currents under the emitters
of the PNP devices. This can effect a significant increase in
the beta of these devices, making internally trigger latCh-Up
much more prevalent. Again, the warning to the the system
designer is to avoid using CMOS at maximum rated supply
voltages unless precautions are taken to insure latch-up is
unlikely or is at least acceptable and recoverable. Switching
transients coupled onto power lines has become a problem
In the loop of positive current feedback formed by the parasitic PNP and NPN transistors of the latch-up structures,
regenerative switching may result if sufficient loop gain is
available. One must remember, though, that three conditions are necessary for latch-up to occur.
1) both parasitic bipolars must be biased into the active
state;
2) the product of the parasitic bipolar transistor current
gains (BnpneBpnp) must be sufficient to allow regeneration, i.e., greater than or equal to one;
3) the terminal network must be capable of supplying a current greater than the holding current required by the
PNPN path. In processes utilizing an epitaxial silicon, this
current is usually in excess of 1A.
Vee
If any of these conditions is not met both during the initiation
and in the steady state, then the latch-up condition is either
non-sustaining or cannot be initiated. If the current to the
latched structure is not limited, permanent damage may result. Again, any means to prevent any of these conditions
from being satisfied will protect the circuit from exhibiting
sustained latch-up.
The prevention of biasing the bipolars into the active region
and the limiting of the current which may be supplied by the
network are the two factors which system designers have
under their control. Many of the protective measures long
exercised in discrete and TIL designs may also be applied
to CMOS designs to reduce susceptibility and prevent damage to these systems. Diode clamping of inductive loads,
Signal and supply level regulation, and sharing of large DC
loads by several devices with suitable series limiting resis-
N Channel
MOS
GND
TLlF/10192-2
FIGURE 2. CMOS Inverter with Parasitic Bipolars
3-22
now that CMOS has become a high-speed logic technology.
Attention to power supply decoupling is now a necessity
when designing with high-speed CMOS. Of course, CMOS
processes incorporating an epitaxial silicon over a substrate
of very low resistivity is less prone to latch-up under these
conditions. These recommended precautions should be taken just the same.
Latch-Up Protection Geometries
Every FACTTM IC employs special geometries to isolate every input protection device and every output from active areas on the chip. In this way, structures which would normally
participate in latch-up loops are decoupled and are thus
less troublesome. All devices are scrutinized for potential
latch-up sites and are protected by similar geometries
where any risk is significant.
Latch-up involving input terminals, next to gate oxide rupture, used to be one of the most common failure mechanisms of CMOS. Transients exceeding the power supply
routinely caused either or both of these effects to occur.
Fortunately, CMOS vendors have learned to make better
input protection networks and have learned that proper
placement of these components with respect to the rest of
the chip circuitry is necessary to reduce susceptibility to
latch-up. The system designer should review foreign input
signals to CMOS systems and take precautions necessary
to limit the severity of over/undershoot from these sources.
Measures which could be used to reduce the possibility of
latch-up induced by input signals are: proper termination of
transmission lines driving CMOS, series current limiting resistors, AC coupling with DC restoration to the CMOS supplies, and the addition of Schottky diode clamps to the
CMOS power rails. As an additional measure there are several CMOS circuits which have input protection networks
that can handle overvoltage in one direction or the other
and which are specifically designed to act as interface circuits between other logic families and CMOS. Judicious application of these will also aid in suppressing any tendencies
of CMOS systems to latch-up.
Power Distribution
Careful attention to on-chip power distribution and enhanced termination of P-wells and substrate is used by National Semiconductor to improve latch-up resistance. Our
double metal process affords the advantage in maintaining
low impedance distribution of power and ground potentials
over the entire chip; the potential gradient-caused fields
which often induce or enhance latch-up are thus minimized
while functional performance is enhanced by cleaner onchip power supplies.
Process Design
By design, the FACT process is better both in low latch-up
susceptibility and in enhanced device performance. The
most significant advancement of the FACT process has
been the incorporation of an epitaxial silicon layer. Figure 3
illustrates a modified version of Figure 1, utilizing an epitaxial layer of silicon to contain all of the active components of
the CMOS circuit. This epitaxial layer allows the use of a
separate layer of substrate silicon, of a resistivity some
three orders of magnitude lower than the epitaxial layer. The
effect is also modeled in Figure 3.
As illustrated, the resistivity of the epitaxial silicon, R1, is
on the order of 6 ohm-cm to 10 ohm-em. The underlying
substrate resistivity, R2, is as low as 0.008 ohm-cm to
0.025 ohm-cm. The result is a parallel combination of resistivities, R1 and R2, that is equivalent to R2. What has now
happened is that the gain of the parasitic PNP-NPN circuit
has been dramatically slashed. Under the same latch-up
conditions described earlier, the introduction of the low resistivity substrate now means that at least 10 times more
current is needed to trigger the parasitic PNP-NPN combination.
Finally, attention to CMOS outputs, their loading and the
stresses applied to them will also enable the designer to
generate latch-up free systems. Historically, output terminals of CMOS have been least likely to cause latch-up
though they can participate in latch-up once it is initiated.
The normal mode of failure in this respect is, again, the
application of voltages beyond the CMOS supplies or the
maximum limit for the devices though excessive current has
also been linked to latch-up failure at elevated temperatures. Inductive surges and transmission line reflections are
the most likely sources of output latch-up in CMOS and
should be attended to in the most applicable method, i.e., by
clamping, termination or through dissipative measures.
The active components within the epitaxial layer maintain
the same performance characteristics as those of the active
area illustrated in the non-epitaxial CMOS circuit of Figure 1.
Therefore the introduction of the epitaxial layer to the FACT
process does not reduce any AC, DC, functional or ESD
performance. However, what we have is an advanced
CMOS logic family that is now virtually latch-up immune.
Thus, through innovative and careful layout, attention to
eliminating circuit situations which could be latch-up prone
and by careful selection and maintenance of our advanced
CMOS process, FACT sets the standard for latch-up resistance.
WHAT WE HAVE DONE
National Semiconductor, as an important supplier of advanced CMOS to all segments of the industry, has made a
commitment to provide IC designs which make use of stateof-the-art latch-up suppression techniques in an effort to
support its customers before they need support. The three
most important actions which we have taken to guard our
customers from latch-up are in the areas of layout, power
distribution and process design. These techniques, along
with recognized good design practice, yield a product line
that lives up to the intent of an advanced CMOS family. In
brief review, National Semiconductor's attack on latch-up is
summarized in the following.
3-23
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P-ChBnnel MOS
Input
N-ChBnnel MOS
N+ Substrate
0.008-0.25 ohm-em
TLlF/10192-3
FIGURE 3
3-24
»
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.
National Semiconductor
Application Note 610
Raghu Rao
Terminations for Advanced
CMOS Logic
m
.....
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INTRODUCTION
Advanced CMOS logic such as National Semiconductor's
FACT (Fairchild Advanced CMOS Technology) logic, has
extended CMOS performance to the level of advanced bipolar technologies. While high-performance design rules
that are currently utilized for bipolar designs are also applicable to CMOS, power consumption becomes a new area of
concern in high-performance system designs.
One advantage of using advanced CMOS logic is its low
power consumption. However careless circuit design can
increase power consumption, possibly by several orders of
magnitude. A simple FACT gate typically consumes
625 I-'W/MHz of power; at 10 MHz, this translates to
6.25 mW. A 500 parallel termination on the line will use
over 361 mW with a 50% duty cycle.
The use of high-performance system board design guidelines is important when designing with advanced CMOS
families. Because of advanced CMOS logic edge rates (less
than 3 ns-4 ns), many signal traces will exhibit transmission
line characteristics.
encompasses many traces on a standard PCB. With older
CMOS technologies which have lower edge rates, this criticallength is much longer: 18 inches for 74HC and 5 feet for
CD4000 series and 74C devices. A transmission line terminating into a mismatched impedance could result in transient noise which adversely affects Signal integrity.
The FACT family also features guaranteed line driving capability. The IOLD/IOHD specifications guarantee that a FACT
device can drive incident wave voltage steps into line impedances as low as 500. The IOLD specifications do not
guarantee incident wave switching into bipolar level inputs
since the input low thresholds are 500 mV to 850 mV lower
than CMOS. Due to the relatively linear behavior of the outputs below 1V, CMOS devices can drive incident voltages,
adequate for bipolar inputs, into line impedances as low as
800. For line impedances lower than 800, termination can
be used to provide adequate input levels. Thus besides reducing noise transients, terminations could also be used to
interface between devices from different technologies.
A PCB trace begins to act as a transmission line when the
propagation delay (tpd) across the trace approaches one
third of the driver's edge rate. For advanced CMOS, lines as
short as 6 to 8 inches may exhibit these effects. This rule
Five possible termination schemes are presented with their
impact on power dissipation and noise reduction. Figure 1
illustrates these schemes.
No Termination
~
~
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Series Termination
•+
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Parallel Tormlnation
• •+
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AC Termination
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Thevenln Termination
FIGURE 1_ Termination Schemes
3-25
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NO TERMINATION
No termination is the lowest cost option and features the
easiest design. For line lengths 8 inches or less, this is often
the best choice. For lines longer than 8 inches, transmission
line effects (line delays and ringing) may exist. Figure 2 illustrates the effect of a FACT device driving a 3-foot open-ended coaxial line. Clamp diodes at the inputs of most logic
devices tend to reduce the ringing and overshoots. Often,
these clamp diodes are sufficient to insure reliable system
operation. Figure:3 illustrates the impact of these diodes on
the same 3-foot coaxial line. However, it is not uncommon
to find logic devices like DRAMs, D-to-A converters and
PLDs, that have no input clamp diodes.
2V
PARALLEL TERMINATION
Parallel termination provides an AC and DC current path
back to the power supply for switching currents. While it
effectively reduces ringing (Figure 4), the DC path to ground
or to Vee will dissipate power. The power consumption for
this type of a termination scheme has some important implications. For proper impedance matching the value of this
terminating resistor should be equal to the characteristic impedance of the line.
1 V 2ns
IOns
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TL/F/10218-4
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FIGURE 4. FACT Driving FACT with Parallel Termination
r-----
The DC component to the power consumption is a function
of the signal duty cycle. Signals with lower duty cycles will
dissipate less DC power. Since the load seen by the driving
device is resistive, not capacitive, load capacitance does
not affect power consumption. Therefore, parallel termination dissipates less AC power. Because of this lower AC
power at high frequencies, parallel terminations may consume less power than no termination. Depending upon the
load capacitance, signal duty cycle, and line impedance,
this frequency can be as low as 40 MHz.
TL/F/10218-2
FIGURE 2. Transmission Line Effects
FACT DrIving 3 Foot Open-Ended Coax
There are drawbacks associated with parallel termination.
The maximum DC current allowed into or out of any FACT
output is 50 mAo This limits the allowable resistor values to
greater than 100n. Even though this ringing may not be
excessive, imperfect impedance matching may cause ringing on lines with an impedance less than 100n. However,
because the high-power dissipation of this termination
scheme negates the advantages of advanced CMOS logic,
this is not an intended advanced CMOS application.
••
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Parallel termination tends to unbalance CMOS outputs. Using a resistor to ground, the CMOS device will achieve a
O.OV output low voltage (VOl). But due to the high DC load
In the logic HIGH state, the output high voltage (VOH) will be
degraded (Agure 4). This degraded high level output will be
above the input high voltage (VIH) of both CMOS and bipolar inputs due to the guaranteed dynamic current (VOHD)
specifications (75 mA @ 3.85V, Vee = 5.5V). This lower
VOH level may cause an in¢rease in Icc if the driven device
is CMOS; however, this increase should be minimal.
••
GROUND
RCVR
DRIVER
TL/F/10218-3
FIGURE 3. Effects of Input Clamp DIodes
FACT Driving FACT with no Termination
3-26
THEVENIN TERMINATION
Thevenin termination is similar to parallel termination, except that both pull-up and pull-down resistors are used.
Power consumptions are also similar for both of these
schemes. The difference is that the DC power consumption
is a function of duty cycle and resistor ratios. If the resistors
are matched, DC power consumption is not dependent
upon duty cycle. One advantage Thevenin termination has
over parallel termination is that lines with impedances as
low as 50n can be terminated in their characteristic impedances. For proper impedance matching, the equivalent
thevenin resistance should be the same as the line characteristic impedance.
Thevenin termination does not create unbalanced CMOS
outputs, although it reduces the output swing (Figure 5).
This limited output swing may increase current consumption
in a driven CMOS device however this increase is minimal.
Series termination assumes that any voltage step driven
into a transmission line will double at the receiver. Therefore, the initial voltage step driven into the line is one-half of
the receiver input voltage. The resistor value can be computed by Rs = Zo - RD, where Rs is the resistor value, Zo
is the line impedance and RD is the driver resistance. Figure
6 illustrates the waveforms associated with series termination.
1V
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DRIVER SIDE RESISTOR
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FIGURE 6. FACT Driving FACT with Series Termination
While the device output produces a lull output step, only
half of that is driven into the line. At the receiver end, the
edge doubles, thus recreating the full output swing. The initial step then reflects back, fixing the full output voltage applied on the entire line. A voltage plateau is created at the
input to the line whose width will be twice the line tpd.
Series termination is well suited for lines with a single driver
receiver pair. Series termination limits the initial voltage
step, which offers several benefits: reduced power consumption and decreased cross-coupled radiated noise.
One possible drawback to series termination is that any other receiver located near the driver will see the voltage plateau. Because the plateau level may be very close to the
typical CMOS threshold (50% ofVce), any such input could
see multiple input switching. Combinatorial outputs may oscillate, or clocked inputs may experience multiple clocking.
/
'G~D----::.::.':.':.':.":::::'''RECEIVER
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FIGURE 5. FACT Driving FACT
with Thevenin Termination
Busses using Thevenin termination should not be left floating. A floating bus level is determined by the ratio of the
resistors. If this level is close to any input threshold, output
oscillations and Icc increase may occur. If the bus must be
left floating, the resistor ratio should be chosen so that an
adequate noise margin is insured. The bus could be left
floating by either turning off the driver or by placing the bus
in a high impedance state.
Other terminations which do not introduce DC current paths
may be more suitable to CMOS systems. These include series and AC parallel terminations.
One solution is to choose the resistor value that keeps the
initial voltage step away from the input thresholds. Larger
resistor values will require one or more reflections to settle
out, while still maintaining valid VIN levels at the inputs.
Smaller values will generate overshoot and undershoot.
SERIES TERMINATION
Series termination works by limiting the current that is put
into a line. While other termination circuits dissipate extra
power, series termination reduces power consumption and
dissipates less energy than no termination. This is a recommended termination scheme for the FACT family because
of its low power dissipation.
AC PARALLEL TERMINATION
AC Parallel termination is another technique which blocks
the DC path to ground. A capacitor in series with the parallel
termination resistor blocks the DC path, while maintaining
the AC path. This is a highly recommended termination
scheme for the FACT family because of its negligible DC
power consumption.
3·27
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Understanding and
cc Minimizing Ground Bounce
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As system designers begin to use high performance logic
families to increase system performance, they may run into
new problems which previously did not raise concern when
lower performance devices were utilized. These problems
can generally be avoided by following a few simple rules.
This application note discusses the subject of ground
bounce with respect to high performance CMOS logic families and offers a set of simple guidelines that will eliminate
system problems due to this phenomenon.
Ground bounce has been a concern to some system designers for many years. Its effects can be found in most
bipolar and CMOS logic families. However, ground bounce
has recently become a major issue. Although new advanced
CMOS logiC families have edge rates comparable to advanced bipolar logic devices, CMOS outputs swing almost
from rail to rail while bipolar outputs swing from ground to
approximately 3.0V. These edge rates, coupled with the
greater voltage swings lound in today's advanced CMOS
logic devices, tend to generate more ground bounce noise
than their bipolar counterparts.
In 1982, National Semiconductor, formerly Fairchild Semiconductor, began to develop FACTTM (Fairchild Advanced
CMOS Technology) logiC incorporating more than three
years of experience gained with FAST® (Fairchild Advanced
Schottky TTL) logic into the groundwork. As a result, Fairchild was able to understand the important trade-offs associated with high performance in a logiC family. In the bipolar
world, these trade-ofls were between speed and power; in
the CMOS world, the trade-offs are between speed and
ease of use. Utilizing experience gained from FAST products, the FACT family objectives were defined to provide the
optimum solution, allowing greater system performance
while minimizing system design problems. Using FACT devices does require more attention toward circuit design and
board layout than older, slower technologies. The resulting
advantages-low power and high performance-greatly
outweigh these considerations.
~:>
National Semiconductor
Application Note 640
DEFINING GROUND BOUNCE
As edge rates and drive capability increase in advanced logic families, the effects of intrinsic electrical characteristics
become more pronounced. One of these intrinsic electrical
characteristics is the inductance found in all leadframe materials.
Figure 1a shows a Simple circuit model for a CMOS device
in a leadframe driving a standard test load. The inductor L1
represents the intrinsic inductance in the ground lead of the
package; inductor L2 represents the intrinsic inductance in
the power lead of the package; inductor L3 represents the
intrinsic inductance in the output lead of the package; the
resistor R1 represents the output impedance of the device
output, and the capaCitor and resistor CL and RL represent
the standard test load on the output of the device.
The three waveforms shown in Figures 1b, C, and d depict
how ground bounce is generated. The first waveform shows
the voltage (V) across the load as it is switched from a logic
HIGH to a logic LOW. The output slew rate is dependent
upon the characteristics of the output transistor, and the
inductors L1 and L3, and CL, the load capacitance. The
second waveform shows the current that is generated as
the capacitor discharges [I = -CL • dV/dt)]. The third
waveform shows the voltage that is induced across the inductance in the ground lead due to the changing currents
[VGB = L· (dlldt)].
While these diagrams and figures are useful in explaining
the origins of ground bounce, they are highly theoretical and
idealistic. There are many second and third order effects
which would need to be considered for a complete theoretical analysis. Considering these effects, though, would lead
to highly complex second and third order differential equations which are difficult to solve. The purpose of this application note is to develop a fundamental understanding of
ground bounce and to provide a useful set of design guide·
L2
3
TLlF/l0232-2
b. Output Voltage (V)
TLlF110232-3
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TLlF/10232-1
a. Output Model
TL/F/l0232-4
d. VGB = L. (dlldt)
FIGURE 1. Ground Bounce Circuit Model
3-30
lines. Therefore, we will avoid these lengthy and complex
theoretical discussions wherever possible.
We will not discuss VDD bounce in this application note because its effects parallel those of ground bounce, and the
system problems of VDD bounce are typically of less concern than ground bounce. This is because TTL inputs have
a greater input high noise margin that input low noise margin. For CMOS driving TTL, the input high noise margin approaches 3.5V, and for CMOS driving CMOS, the input high
noise margin approaches 2.5V. In either case, the input high
noise margin is 3 to 5 times greater than any expected VDD
bounce.
In order to change the output from a HIGH to a LOW, current must flow to discharge the load capacitance. This current, as it changes, causes a voltage to be generated
across the inductances in the circuit. The formula for the
voltage across an inductor is V = L • (dl/dt). This induced
voltage creates what is known as ground bounce. Because
the inductor is between the external system ground and the
internal device ground, the induced voltage causes the internal ground to be at a different potential than the external
ground. This shift in potential causes the device inputs and
outputs to behave differently than expected because they
are referenced to the internal device ground, while the devices which are either driving into the inputs or being driven
by the outputs are referenced to the external system
ground. External to the device, ground bounce causes input
thresholds to shift and output levels to change. This situation is very similar to that of large systems where voltages
can develop across expansive ground networks.
•
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CONTRIBUTING FACTORS OF GROUND BOUNCE
While our circuit diagrams shown above are useful for explaining the origins of ground bounce, they are too idealistic
to be used for modeling. In the real world, there are many
other variables which affect the actual shape and amplitude
of the induced voltage. To develop an accurate model, the
resistor must be replaced with a model of the actual transistor. In addition, the period where the transistors are turning
on and off would need to be taken into account. Including
these variables, plus others, would lead to highly complex
differential equations that are nearly impossible to solve except by the most advanced computer programs. Since theoretical analysis of ground bounce is difficult to perform, we
will use empirical data to develop an understanding of
ground bounce and how it is effected.
OTHER CAUSES OF GROUND BOUNCE
Although this discussion is limited to ground bounce generated during HIGH-to-LOW transitions, it should be noted
that the ground bounce is also generated during LOW-toHIGH transitions. This ground bounce is created by the
large gate capacitances associated with the output transistors on the die. Because these gate capacitances are larger
than the gate capacitances of earlier-stage transistors,
more current is generated when they switch. The output
buffer stages of CMOS devices are inverters; thus their inputs are switching HIGH-to-LOW when their outputs are
switching LOW-to-HIGH. It is the currents associated with
switching these inputs to the output transistors that generate ground bounce when the outputs switch LOW-to-HIGH.
This LOW-to-HIGH ground bounce has a much smaller amplitude and therefore does not present the same concern.
There are several factors which affect ground bounce: the
number of outputs switching simultaneously; the location of
the output pin; the location and type of load on the line; the
VDD voltage; the device technology; and the output and
ground inductances. Each of these factors play a critical
role in the generation of ground bounce.
GROUND BOUNCE DEMONSTRATION BOARD
In order to evaluate ground bounce and the factors which
affect it, Fairchild designed a board which allowed side-byside evaluation of ground bounce under varying conditions.
Figure 3 shows the functional block diagram of the board. A
counter generates the changing data lines by counting from
o to 127. The counter can also be configured to count down
from 127 to 0 so that VDD bounce may be evaluated. This
changing data is clocked into an 'AC374 and then passed
into both another 'AC374 and an 'AC244. This was done for
two reasons.
We should also note that everything discussed here concerning ground bounce can be applied to the oppOSite effect, VDD bounce. VDD bounce is the inverse of ground
bounce. As one would expect, there is an intrinsic inductance in the VDD lead as well as the ground lead. The internal VDD potential will collapse toward ground at the beginning of a LOW-to-HIGH transition and then bounce above
the external VDD potential at the end of the transition.
First, the noise generated by the first 'AC374 represents
gound bounce generated by a lightly-loaded circuit. Secondly, being able to choose between either the 'AC37 4 or the
'AC244 to drive the system bus allows us to evaluate both
devices under heavy load conditions. The quiet output from
these two devices drives a line that is connected to the
clock inputs of eight '74 D-type flip-flops and two inverter
inputs. Each flip-flop is configured so that if a valid clock
was encountered, the Q output will go from a "0" to a "1";
each flip-flop acts as qlitch catcher, detecting any ground
bounce noise which violates the flip-flop clock thresholds.
Devices from several common logic families are connected
to this quiet output so that the effect on different technologies can be evaluated.
~
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_GROUND
VBOUNCE
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TL/F/l0232-5
• vee bounce (droop) is the voltage drop across the package
The seven other outputs of the 'AC374 or the 'AC244 drive
a 7 -bit data bus. This data bus is loaded with fourteen devices, which represents a typical heavily-loaded system bus
and allows us to evaluate ground bounce under these conditions.
• Inductance (to Voo) is caused by charging load capacitances
• Voo bounce is less of a concern than ground bounce because TIL-laval
inputs have greater high noise immunity
FIGURE 2. Ground Bounce/Voo Bounce
In addition, VDD bounce is generated during HIGH-to-LOW
transitions for the same reasons that ground bounce is generated during LOW-to-HIGH transitions.
3-31
•
.
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oo:r
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TEST
FIXTURE
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TEST
FIXTURE
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TEST
FIXTURE
2SMHz ClK
TI
AC11374
TEST
FIXTURE
MASTER
RESET
TUF/10232-6
FIGURE 3. Ground Bounce Demonstration Board Block Diagram
TABLE I. Critical Signal Statistics
Signal
Length
CO
LO
RO
# Loads
CL
Termination
Type
Termination
Type
DATA BUS
30 Inch
107 pF
565nH
1.30
14
70j:lF
PARALLEL
500
CLOCK·
28 Inch
103 pF
445nH
1.00
16
80pF
THEVENIN
710/1200
GROUND BOUNCE
7.5 Inch
30pF
117 nH
0.20
10
50pF
AC
260/2000
• Clock generated from seven (7) stage ring oscillator (' AC240)-approximately 25
MHz
TL/F/10232-7
FIGURE 4. Critical Signal Paths
3·32
~
Each device on the bus is configured equivalent to a standard test fixture. Conditions such as output loading, load
placement, power supply voltage, and quiet output pin location were varied to compare ground bounce under different
conditions. Also, some device locations were populated with
different device types and devices from other logic families
to evaluate ground bounce across technologies.
Table I lists the important electrical characteristics for the
critical signal paths. Figure 4 shows the physical layout of
the board and the critical paths. This board was used to
generate the data and waveforms presented in this application note unless otherwise noted.
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TUF/l0232-8
LEAD INDUCTANCE
The impact of the ground inductance on ground bounce
seems to be obvious. For a given dll dt value, the greater
the inductance, the greater the ground bounce. While this
would imply that reducing the ground inductance should reduce the ground bounce, this is not always the case. The
explanation is fairly straightforward.
Ground bounce tends to limit the available AC current in
CMOS outputs by reducing the voltage across the output
impedance, and therefore, reduces the current that will flow.
When the ground lead inductance is reduced, a corresponding increase in the output edge rate of the device occurs.
This is due to the fact that by reducing the inductance in the
ground lead we have increased the available AC current.
This greater dll dt tends to reduce any improvement that the
reduced ground inductance may have generated.
FIGURE 5. Noise vs Package Configuration
Reducing the ground lead inductance is not "the" solution
to ground bounce problems. While a small reduction in
ground bounce can be realized, additional problems, like
increased crosstalk, may occur. A better solution is to reduce the inductance in all leads. Smaller packages, such as
SOIC and LCC/PLCC packages, do reduce ground bounce
over both standard and center-Voo/ground-pinned DIP
packages.
NUMBER OF OUTPUTS SWITCHING
The number of outputs switching simultaneously affects the
amplitude of ground bounce. For a simple model, treat the
output impedances of each active output as resistors and
inductors in parallel. For resistors of equal value in parallel,
the formula for the net resistance is R/n, where R is the
output impedance of each transistor, and n is the number of
resistors. Therefore, as more outputs switch at the same
time, the output resistance is reduced and more ground
bounce will be generated.
Again, it is very difficult to model this effect so we will rely on
empirical results for our analysis. Figure 6 illustrates the effect of increasing the number of outputs switching at the
same time. We can see that as the number goes up, the
amplitude and duration of the ground bounce pulse also
increases. Therefore, devices that have fewer outputs will
have less ground bounce.
National tested FACT to investigate the effect of ground
inductance on ground bounce. This was accomplished by
assembling die from the same manufacturing lot in plastic
DIPs; some were assembled using the standard pinout and
some were assembled with the ground and power pads
connected to the center pins. When the data was analyzed,
it was found that the die assembled with center pin Voo and
ground averaged approximately 10%-15% less ground
bounce than the die assembled with the standard pinouts.
Along with the small reduction in ground bounce, they also
exhibited somewhat faster edge rates with corresponding
decreases in propagation delays.
OTHER PACKAGES
The inductance in the ground lead is not the only inductance in the package; all of the output pins have an associated inductance. The inductances in the outputs also contribute to ground bounce, especially any oscillatory effects.
While just reducing the ground or Voo does not significantly
reduce ground bounce, reducing the inductance in both the
power leads and the outputs does reduce ground bounce.
•
Figure 5 outlines the effect that packaging has on ground
bounce. In order to make the comparison as valid as possible, die from the same wafer were used. This was necessary because the effect of process variations on ground
bounce is greater than the effect of packaging. It can be
seen that packages with smaller power and signal lead inductances tend to reduce ground bounce. It is important to
note that the difference between CDIP and LCC package
ground lead inductance is approximately one order of magnitude (20 nH versus 2 nH), yet the difference in ground
bounce is less than 35%.
,I
- - 1 Output SwHchlng
1,I'
1Vertical Scale: 0.5 V/DIY
------- 3 Outputs Switching
----- 7 Outputs Switching ,Horlzonlal Scale: IOns/DIY
.--_. Ground
I'
TLlF/l0232-9
FIGURE 6. Number of Outputs Switching
3-33
Figure 7 shows the ground bounce generated by an 'AC157
when three of the four outputs are switching with standard
test loads. Here we see only 475 mV of noise on the worstcase pin (pin furthest from the ground pin). This amplitude of
ground bounce is not what we would expect in an actual
system. As we will discuss later, a test fixture lumped load
creates much more ground bounce than distributed system
loads.
Smaller capacitors contain less energy than larger capacitors, and therefore, a larger change in the voltage across
them will occur during the time that the output is turning on.
Because of this, the size of the capacitance tends to limit
the maximum amount of current sinking throughout the output and therefore, the amount of ground bounce. Larger
capacitors, however, do not experience such a large
change in voltage as the outputs turn on. For very large
capacitances, there is almost no change in the voltage
across them, and they behave much like a power supply.
Under these conditions, the maximum amount of current
that will sink through the outputs is limited by the outputs
themselves. Increasing the capacitance does not increase
the current and therefore, does not increase the ground
bounce.
Figure 10 shows the effect of varying only the capacitive
loading on the active output. Here, the filtering effect of the
load can be observed clearly. As the load capacitance is
increased, it filters the signal and reduces the amplitude of
the ground bounce.
Because they generate more AC current during switching,
capacitive loads tend to generate more ground bounce
noise than resistive loads. Fortunately, most actual PCB
traces will be long enough so that they react like an impedance and not lumped capacitive loads.
OUTPUT LOAD
The type and value of the output loading is one of the major
variables that affect the amplitude of the ground bounce.
Figures 8, 9 and 10 show the effects of varying the load
capacitance in a standard test fixture.
In Figure 8, the ground bounce amplitude peaks for a load
capacitance of approximately 60-70 pF, and then drops off
as the capacitance is increased. This drop off is caused by
the filtering effect of the larger capacitors.
For Figure 9, only the load capacitors on the active outputs
were varied. The load on the quiet output was maintained at
50 pF. The amplitude of the ground bounce amplitude increased with increased capacitive loading. However, the
slope of the curve drops off as the capacitance increases.
This is due to the amount of energy that is discharged from
the capacitor during the time that the output transistor is
turning on.
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°0L-~50~1~0-0-1~50--2~00--25~0-3~0-0-3~50--4~00--45~0~500
Qulat Output Load (pF)
Capacitance (pF)
TL/F/l0232-13
TL/F/l0232-12
Ground Bounce Varying Quiet Oulput Load Only
Quiet Output Switching with 'AC241
Other 7 Loads are Standard 5000/50 pF
7 Outputs Driving Lumped Capacitive Loads
FIGURE 10. Fixed Active Load
Figure 12 illustrates what happens when the test load is
moved away from the device output. A standard test load
was connected to the output via 15 inches of circuit trace.
The amplitude of the ground bounce was reduced to 1.1V. '
While this loading is closer to an actual system trace than a
test load, it still generates more ground bounce noise be·
cause of the lumped load that is still on the line.
Monitoring Pin 18
FIGURE 9. Fixed Quiet Load
Figure 11 displays ground bounce when the device is load·
ed with standard 50 pF/500.o. test loads. Each load was
connected directly to the output pin. Under these condi·
tions, which are considered worst case, the measured
ground bounce amplitude was 1.7V.
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----- Ground
VVertlcal Scale: 0.5 V/Dly
Horizontal Scale: to n./OIY
_._.- Quiet Output Nol.a
Vertical Scala: 0.5 V/Dly
Horizontal Scale: 10 na/DIY
TLlF/l0232-14
TLlF/l0232-15
7 Outputs Switching Voo ~ 5V
CL
~
\/' v
~
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_._.- Quiet Output Noise
-['
-.:~-
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----- Ground
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7 Outputs Switching VOO
~ 50 pF
50 pF
~
5V
CL
Worst-Case Output Pin
Worst-Case Output Pin
FIGURE 11. Standard Test Fixture
15' PCB Trace Separating Load from Device
FIGURE 12. Test Fixture Emulating
Transmission Line Effect
3-35
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Figure 13 shows the ground bounce when the load capacitance is reduced to 5 pF. The ground bounce decreased to
1.3V. This circuit represents a short, lightly loaded line.
circuit represents a typical system trace. These figures
show the expected amplitudes of ground bounce in an actual system.
Figures 14 and 15 depict the ground bounce generated by
the 'AC374 and 'AC244 driving the data bus on the board.
This bus is over 30 inches long and has over 200 pF of
capacitance load. The 'AC374 only generated 600, mV of
ground bounce while the 'AC244 generated 500 mV. This
Figure 16 shows the ground bounce which was measured
on a commercially available personal computer motherboard after a 'F244 was removed and replaced with an
'ACT244. For these results, the host processor was removed, and the inputs to the 'ACT244 were connected to
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----- Ground
----- Quiet Output Noise
-----Ground
----- Quiet Output Nol..
Vertical Scalo: 0.5 V/ON
Horizontal Scale: 10 na/DIY
Vertical Scale: 0.5 V/DIy
Horizontal Scalo: 10 na/ON
TLlF/l0232-17
TLlF/l0232-16
7 Outputs Switching VOO = 5V
7 Outputs Switching Voo = 5V
CL
= 5 pF
CL=50pF
Worst·Case Output Pin
Worst-Case Output Pin;
Open Circuit Output (5 pF Parasitic CapacHance)
Ten Loads on Quiet Output Heavy Load
FIGURE 13. Reduced Output Loading
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FIGURE 14. System Quiet Output Noise-'AC374
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----- Ground
----- Quiet Output Noise
.................. _ . .,.J
Vertical Scalo: 0.5 VImy
Horizontal Scale: 10 no/Oly
Ground Bounce
(Doy. 16F Pin 18)
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Vertical Scale: 1.0V/DIy
Horizontal Scale: 10 no/mY
TLlF/l0232-19
TL/F/l0232-18
7 Outputs Switching Voo = 5V
7 Outputs Switching Voo = 5V
CL = 50pF
CL = 50pF
Worst·Case Output Pin;
Worst-Case Output Pin
Ten Loads on Quiet Output Heavy Load
'AC244 Driving 10 Distributed Loads on an Unterminatad Address Bus
FIGURE 16. Quiet Output Noise In
Personal Computer Application
FIGURE 15. System Quiet Output Noise-' AC244
3-36
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TL/F/10232-20
• Commercial PC Address Bus
• No Termination Resistors
• Approximately 50 pF Capacitance Loading
• Replaced 'F244 with 'ACT244
• With 7 Outputs Switching, Quiet Output Noise
= 1.1V
FIGURE 17. PC Circuit Diagram
the board clock source. The logic diagram for this line is
represented in Figure 17. An address bus driver was chosen
because of the length of the line and the number of loads on
it. Here, the ground bounce amplitude was 1.1V. We can
see that this signal line is connected to devices of many
different technologies and functions, including LS and memory products. After the host processor was replaced, the
system exhibited no performance degradation due to the
device replacement.
It can be seen from the previous figures that the type and
location of the output loads have a major effect on ground
bounce. It is also obvious that standard test loads generate
the most ground bounce. Even reducing the capacitive load,
or moving it away from the output still generates more noise
than a typical application.
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OUTPUT PIN LOCATION
The location of the output pin with respect to the device
ground also affects the magnitude of ground bounce. Tests
have shown that outputs located closer to the ground lead
generally have 30% to 50% less noise than pins further
away. The effects of pin location are portrayed in Figures 18
and 19. Figure 18 shows the ground bounce on the worstcase pin, which is the one farthest away from ground. Figure
19 shows the ground bounce on the best-case pin, the one
closest to ground. By choosing outputs close to ground, the
amount of ground bounce may be reduced by nearly half.
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----- Quiet Output Noise
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----- Ground
--_.- Quiet Output Noise
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Vertical Scale: 0.5 VIDiY
Horizontal Scale: IOns/DiY
TLlF/10232-22
7 Outputs Switching Voo
Vertical Scale: 0.5 V/DIy
Horlzon!al Scale: 10 ns/Dly
=
5V
CL=50pF
FIGURE 19_ Quiet Output NoiseBest·Case Output Pin (Pin 9)
TL/F/10232-21
7 Output Switching Voo = 5V
CL=50pF
Standard Test Setup
FIGURE 18_ Quiet Output NoiseWorst·Case Output Pin
3-37
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ct
POWER SUPPLY VOLTAGE EFFECTS
TEST FIXTURES VS REAL SYSTEMS
Because ground bounce is so dependent upon the load the
device is driving, it has proven to be one characteristic of
CMOS devices that does not correlate well between results
taken on standard test fixtures and results seen in actual
systems. This occurs for several reasons. First, the AC loading presented by standard text fixtures is not the same as
the AC loading generated by a system load, and second,
the standard test load creates a LCR tank circuit that tends
to oscillate during edge transitions.
The value of Voo also affects the amplitude of the ground
bounce. By reducing the Voo level, not only is the output
voltage swing reduced, but also the amount of current that
the output can deliver. Both of these tend to reduce ground
bounce.
Figure 20 tabulates the results of varying both Voo and load
capacitance. All of these numbers were taken on a standard
test fixture. Note that while the amplitude of the ground
bounce changes linearly with voltage, it is not merely the
ratio of the voltage levels. Reducing the Voo by 40% (from
5.0V to 3.0V) reduces the ground bounce by almost 60%.
Since the amplitude of the ground bounce decreases faster
than the input threshold, there is a net gain in the noise
margin.
For these reasons, ground bounce data taken on test fixtures is useful for comparative analysis, but is not valid for
predicting actual system performance.
AC LOADING EFFECTS
Standard text fixtures use 50 pF of capacitance and 5000
of resistance to simulate a "typical load," as shown in Figure 22. It is possible to achieve good correlation between
propagation delay data taken using these test loads and
data taken in real systems. Unfortunately, this is not true for
ground bounce. While this lumped load testing was adequate for older, slower technologies, it is not as useful for
the newer, faster logic families. As edge rates go up, more
and more circuit traces react like transmission lines, not
lumped loads. For devices having edge rates of approximately 3 ns, traces longer than 6-8 inches will exhibit transmission line characteristics and cannot be treated as
lumped loads.
Figure 21 represents the same results taken on the ground
bounce demo board. The ground bounce was measured
with Voo = 3.0V. The amount of ground bounce was reduced to 800 mY, even with standard test loads. It should
be pointed out that 'ACXXX devices can be used in a 5V
TTL system with a Voo of 3.3V ±0.3V. Under these conditions, the outputs will still drive an incident wave on a 750
transmission line for the commercial temperature range and
1000 for the military temperature range. With Voo equal to
3.3V, FACT 'ACXXX devices have TTL-compatible inputs
and outputs.
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2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDD (V)
----·Ground
-._-- Quiet Output Noise
TL/F/10232-23
FIGURE 20_ Quiet Output Noise vs Power Supply
Vertical Seale: 0.5 v/Dw
Horizontal Scale: 10ns/D1v
TLlF/10232-24
7 Outputs Switching VDD
~
5V
CL~50pF
Worsl·Case Oulpul Pin
FIGURE 21. Quiet Output Noise-Voo = 3.0V
~
yTL/F/10232-25
FIGURE 22. Standard Test Load
3-38
.
):-
Figures 23a and 23b are models of a capacitive load and a
transmission line load, respectively. In Figure 23a, we replace the capacitor with a power supply. This simulates our
circuit at the time when the output transistor has just turned
on, and the full capacitor voltage is applied across the device. In Figure 23b, the transmission line is replaced with a
resistor to the power supply. This simulates the AC characteristics of the transmission line.
Referring back to Figure 1a, notice the LCR tank circuit that
is formed by the load capacitance, parasitic inductances
and output resistance. Imagine each edge transition as a
single impulse into this tank circuit; it would be expected to
oscillate. Theoretically, the frequency of the oscillation
should be somewhere in the range around 1.3 GHz. Typically, oscillations are observed in the frequency range of
100 MHz to 200 MHz. There are several reasons for this
discrepancy.
The output transistor does not behave like a pure resistance. The transistor tends to limit the available current to
less than 160 mA to 180 mAo Additionally, there are other
parasitic elements associated with the output transistor affecting the frequency of oscillation.
Because most circuit traces react like impedances and not
capacitances, this type of oscillation is not seen when FACT
devices drive typical circuit traces.
Figures 22 and 23 highlight the differences between ground
bounce in a standard test fixture and in a comparable PCB
trace. The results of the test fixture (Figure 24) are much
greater than the results of the PCB circuit trace (Figure 25).
This is due to the greater current requirements caused by
the lumped capacitive load versus a distributed load.
Comparing the two figures, we notice that while the capacitive load applies the full voltage directly to the device output, the transmission line acts like an additional resistance
between the voltage and the device output. Clearly, one
would expect more current to flow with the capacitive load
than with the resistive load. Since the output transistor turns
on just as fast in both cases, the capacitive load will create
a greater dl/dt, causing more voltage to be induced across
the ground lead inductance. Because of this, standard test
fixtures tend to generate two to three times more ground
bounce noise than system printed circuit traces. This is still
true for traces that may have more capacitance than the
50 pF lumped load used in standard test fixtures.
L2
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L1
TEST FIXTURE CIRCUIT _
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LCR TANK EFFECTS
---£
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TL/F/l0232-26
SYSTEM CIRCUIT
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TLlF/l0232-28
TEST FIXTURE MODEL
TL/F/l0232-27
FIGURE 23a. Test Fixture
SYSTEM MODEL
FIGURE 23b. System Models
3-39
Tl/F/10232-29
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----- Ground
----- Quiet Output Noise
V
----- Ground
----- Quiet Output Noise
Vertical Scale: 0.5 V/Dly
Horizontal Scale: IOns/DiY
Vertical Scale: 0.5 V/Dly
Horizontal Scale: 10 ns/Dly
TL/F/I0232-30
7 Outputs Switching Voo
= 5V
CL
TLlF/l0232-31
= 50 pF
7 Outputs Switching Voo
Worst Case Output Pin; Ten Loads on Quiet Output
= 5V; Heavy Load
Worst·Case Output Pin; Ten Loads on Quiet Output
FIGURE 24. Quiet Output-5tandard Test Fixture
FIGURE 25. Quiet Output Nolse-5ystem Bus
The difference in oscillation between a standard test fixture
and a typical circuit trace is also shown. Even though the
circuit trace has more capacitance than the test fixture, it is
not lumped at the output, but distributed along the circuit
trace.
There are four predominant manifestations of ground
bounce which we will discuss: 1) altered device states,
where a device assumes a state that is not intended or expected, 2) undershoot noise on active Signals, 3) propagation delay degradation, and 4) noise on quiet (static) outputs.
For these reasons, ground bounce data taken on test fixtures is useful for comparative analysis, but is not valid for
predicting actual system performance.
ALTERED DEVICE STATES
Of these four symptoms, the most critical is altered device
states. Altered device states occur when a device assumes
a state that is not intended or expected by the system designer. The results can range from glitches on the outputs to
permanently-altered data in registers or counters. Ground
bounce can cause these types of problems when it is great
enough to cause an external signal to be sensed incorrectly
in the device.
MANIFESTATIONS OF GROUND BOUNCE
The problems associated with ground bounce occur because the induced voltage across the ground leads creates
a voltage differential between the external system ground
and the internal device ground. This voltage affects both
inputs and outputs, although differently.
The difference between the external and internal grounds
must be taken into account to arrive at the actual input
threshold. Noise on either the internal ground or Voo will
cause the input thresholds to change. CMOS input thresholds are generally 50 % of the voltage across the input
structure, i.e., if Voo is 5.0V, then the input threshold will be
2.5V. Now, if the ground bounces positively 1.0V, the net
voltage across the input structure will be reduced to 4.0V.
This will cause the input threshold to shift up to 3.0V (1.0V
of ground rise + 50% x 4.0V). Conversely, if the ground
bounces negatively 1.0V, the input threshold will drop down
to 2.0V (-1.0V + 50% X 6.0V). If during this time a quiet
input is held between 2.0V and 3.0V, the input structure will
detect a change of state.
Regarding the outputs, the effect is somewhat different. Any
output that is LOW is essentially tied to the internal ground
through a very low impedance: approximately 10-12n.
Therefore, any output will tend to follow the internal ground
as it shifts with respect to the external ground. This causes
any LOW outputs to also shift with respect to external
ground.
r-DO ..D6
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ClK IN
-- L
ClK OUT
DO .. D6
D 74 0
ClK
ij~
- - - " ' L_ __
ClKIN~
ClKOUT~
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TLlF/10232-39
FIGURE 26. Example of Ground Bounce
3-40
In CMOS devices, the input thresholds are generally a percentage of the voltage across the input structure. Generally,
the input levels are 50% for CMOS level inputs and 30% for
TTL-level inputs. As the internal ground and power levels
shift with respect to the external power and ground planes,
the input thresholds will also shift. If the shift is great
enough to cause the input threshold to go above an external
HIGH Signal (so that the input signal looks LOW) or below
an external LOW signal (so that the input looks HIGH), the
input will detect a change of state. Depending upon the input type, several results can occur.
Figure 28 illustrates the effects of multiple output switching
on the propagation delay of a FACT device. Here we see
that as more outputs switch, the edge rate of those outputs
drops off.
While it is not possible to test this type of parameter in an
ATE environment, National understands its importance to
system designers. Since this type of measurement can be
made in a bench environment, FACT devices are evaluated
during initial device characterization to insure that this propagation delay degradation is less than 250 ps per additional
output switched.
If the input is a synchronous one, such as the data input into
a D-type flip-flop, then the device should not be affected. If
the input is combinatorial, or the data input to a transparent
latch, the output may glitch.
UNDERSHOOT ON ACTIVE SIGNALS
Undershoot noise on active signals is generally created by
impedance mismatches in transmission lines. Yet, it can
also be created by ground bounce. Figure 29 shows the
voltage that is generated across the inductor during the
edge transition. While at the beginning of the transition the
ground bounce is positive, at the end it is negative. This is
due to the currents turning off as the output reaches the end
of its voltage swing.
The effects may be more damaging if the input is asynchronous, such as a clock, preset, set, load, or clear. With these
inputs, data in the internal counters or registers may be corrupted. Most likely, this type of data corruption can usually
cause a system to fail, or generate invalid results.
FACT devices are characterized during initial device evaluation to ensure that the device will not exhibit this problem.
--,
1.1 ns Skew
PROPAGATION DELAY DEGRADATION
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Propagation delay degradation is a phenomenon familiar to
most system designers. As more than one output on a single device is switched, the propagation delay, as measured
to the input threshold level, will become longer. To understand how this happens with CMOS devices, consider Figure 21; any voltage developed across the inductor L1 will
reduce the voltage across the output impedance R1. This, in
turn reduces the current through R1. Since the rate of voltage change across the load capacitance is directly related
to the current available, a decrease in current reduces the
rate at which the output voltage changes, i.e., the edge rate
slows down. This, in turn, slows down the propagation delay
because more time is required for the output to go from one
rail to the input threshold. As additional outputs are switching simultaneously, the voltage across the inductor increases, and the current available to charge or discharge the load
capacitance will be less.
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.. - - -. 1 Output Switching
••• _-. Clock In
V.rtlcal Scal.: 1.0 V/Olt
Horizontal Scar.: 2 "./Div
TL/F/10232-33
FIGURE 28. Propagation Delay vs
Number of Outputs Switching
Unfortunately, the negative ground bounce occurs when the
output is finishing its transition. The output will follow the
internal ground as a quiet output would. This results in the
output undershooting and then returning to ground.
v
TLlF/10232-32
FIGURE 27. Output Model
3-41
...,
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SYNCHRONOUS DATAlADDRESS BUSSES
One of the largest application segments for octal devices is
driving/receiving data and address busses. In these bus applications, the receiver is usually synchronous and latches
in the data on a clock edge. In Figure 29, notice that the
quiet output noise exists only when the active outputs are
switching. In addition, both quiet and active outputs achieve
this stable and valid state within the propagation delay time
specified in the FACT Data Book.
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.---- Qul.t Output NoI,.
....- .... Actlv. Edge
During the time that the data or address is latched in (when
the data is expected to remain stable and valid) the quiet
outputs are as stable and valid as the active outputs. Therefore, valid data will always be clocked in, and in these systems, no additional work is required to achieve maximum
system performance and reliability.
/"
.... /
t'- ·,:o>o;.-:=:C·"c
V.rtlcal Scal.: 1.0 V/Dlv
Horizontal Scal.: 10nl/D1Y
ASYNCHRONOUS CONTROL LINES
A much smaller application segment is driving asynchronous signals. Octal devices, like the '240 series, offer eight
buffers in a 20-pin package. This feature can be useful to
the system designer trying to reduce board size and part
count. It is in these applications that problems are most
likely to occur. However, there are several factors that work
in the designer's favor.
It is important to look at the type of input that is being driven.
CMOS-level inputs have much greater low noise margins
than TTL-level inputs. Standard CMOS inputs have input
thresholds set to 50% of Voo. This means that if Voo
equals 5.0V, there is 2.5V of low noise margin. Test results
show that the ground bounce will never be this great in a
system. In addition, as noted above, the actual ground
bounce noise expected in a real system is less than the AC
noise margins of most TTL families.
Finally, it is very important to note that the duration of the
ground bounce noise spike is short (tyically 2-3 ns @ 0.8V).
Typically, AC noise margins increase with decreasing pulse
width. This is more pronounced in slower technologies. Figure 31 shows the typical low level input noise thresholds of
FAST, Schottky, and Low Power Schottky. For pulse width
typically seen with ground bounce noise, the AC noise margins of FAST and Schottky approach 2.0V and 1.5V respectively. Even LS devices, which have the lowest input thresholds, have AC noise margins that exceed 2.0V for pulse
TLIFll0232-34
FIGURE 29. Quiet Output Noise Concurrent
with Active Edge
Undershoot amplitudes are generally slightly less than the
associated ground bounce. This undershoot noise will generally not be a problem because most standard logic families have input structures, such as clamp diodes, that tend
to damp it out. However, some specialized devices, exemplified by dynamic RAMs, may be sensitive to undershoots
greater than -2.0V.
QUIET OUTPUT NOISE
QUiet, or static, output noise is usually the symptom of
ground bounce that is first noticed by system designers. As
pOinted out earlier, quiet output noise occurs because LOW
outputs tend to follow internal ground. If there is a shift between the external and internal grounds, it will appear as
noise on a quiet output. The effects of this noise can range
from noise on the output signals to system failure. If the
noise is great enough to cross the input threshold on the
next device on the line, this next device may react.
The reaction, of course, will depend upon the type of input.
If the input is synchronous, the ground bounce noise will not
propagate through the input into the device. If the input is
combinatorial or asynchronous, output glitches or corrupted
counters or registers may result. In order to predict the effects of this noise, it is necessary to consider some typical
applications.
As shown earlier, ground bounce amplitude is dependent
upon the number of outputs switching. Therefore, devices
which have fewer outputs will have less noise. Because of
this, our discussions will be limited to octal devices and their
applications.
TLIFll0232-40
FIGURE 30. Application Segments
3-42
Low Level Noise Immunity
Wr-~-r--TO----'----'
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15
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FIGURE 32. Example Circuits
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Output: YOH "'"\
mentioned earlier, outputs closer to the ground pin may
have up to 50% less noise than outputs further away.
Therefore, asynchronous lines should be driven from outputs closer to the device ground pin whenever possible.
/"
2.0Y-V
TL/F/l0232-36
FIGURE 31. AC Noise Thresholds
widths as great as 8 ns. For ground bounce type noise pulses, with widths of 2-3 ns, the LS AC thresholds are well
above 2.0V.
Some other methods, which may be more difficult to implement, include reducing the power supply voltage or using
two power supply voltages. Running the system Voo lower
(closer to 4.5V) will reduce the ground bounce noise levels
of the CMOS devices while not affecting the input thresholds of the TTL devices. In addition, as we stated earlier, the
Voo value for the CMOS devices can be lowered to 3.3V.
This reduces the ground bounce by 60% while maintaining
TTL-compatible inputs and outputs. For a small number of
CMOS devices, a standard zener diode regulated circuit
may be used. For larger numbers of devices, a second
(3.3V) power plane may be added.
Take a moment to summarize the material covered thus far.
While at first glance, the problems associated with quiet output noise may seem to be the most precarious to system
designers, there are many issues that affect them. First, a
large percentage of the octal applications are synchronous
busses. In these applications, quiet output noise will not be
a problem.
There are also several design techniques under the system
designer's control which can be used to minimize ground
bounce noise, thereby eliminating ground bounce-induced
problems.
The first factor that should be considered, in many cases, is
that the need for a buffer can be eliminated. This is due to
the fact that all FACT logic devices feature the same 24 mA
output stages. A quick example will help to clarify this. For
the example, a divide-by-2 clock generator drives a clock
onto a large processor board. Figure 32a shows the circuit
built with ALS devices while Figure 32b shows the same
circuit built with FACT devices. The difference is obvious:
the ALS circuit required a buffer to drive the clock line because the 'ALS74 does not have enough output drive to
drive the line. On the other hand the 'AC74 has the same
drive capability as the 'AC240, so adding the buffer is redundant. In addition, the output of the 'AC74 is double buffered
to isolate the internal logic from noise on the outputs. Removing an additional propagation delay gains performance
advantages besides board space and part count savings. If
it is not possible to remove the buffer, the deSigner can still
insure minimum noise on the output. This can be accomplished with several methods, some of which are discussed
here.
Board-level timing analysis may show that not all of the outputs can switch at the same time. Under these conditions,
the worst-case ground bounce will be reduced (Figure 6). As
It is the smaller segment of asynchronous applications that
are most suspect. Fortunately, only octal devices generate
enough ground bounce noise to be of serious concern. Secondly, if the inputs are CMOS, the input noise margins are
greater than any ground bounce. If the inputs are TTL, the
ground bounce will generally be less than the TTL AC input
noise margins. Additionally, designers have several techniques available to reduce the ground bounce. These include: a) use logic devices that provide buffer-type drive
capability, thereby eliminating the need for these octal buffers (all FACT devices have the same 24 mA outputs); b) do
not have all of the outputs on an octal device switch simUltaneously; c) select outputs closer to the ground pin for driv-
3-43
•
DESIGN RULES
ing asynchronous inputs, and d) reduce the Vee level. Any
or all of these may be used to eliminate the possibility of
system failures due to quiet output noise in the small number of octal applications where these problems might occur.
Most applications require no special precautions.
From this, we can develop a simple set of rules that will
protect any system from problems associated with ground
bounce. This set of design rules listed below is recommended to ensure reliable system operation by providing the optimum power supply connection to the devices. Most designers will recognize these guidelines. These guidelines are the
same ones as those they have been using for years for the
advanced bipolar logic families.
The major pOints of concern regarding ground bounce:
Ground bounce occurs because of the parasitic inductances
found in all conductors.
Ground bounce causes shifts in input thresholds and noise
on outputs.
Use multi-layer boards with Vee and ground planes, with the
device power pins soldered directly to the planes, to insure
the lowest power line impedances possible.
There are many factors which affect the amplitude of the
ground bounce:
Use decoupling capacitors for every device, usually 0.10 /LF
should be adequate. These capacitors should be located as
close to the ground pin as possible.
• Number of outputs switching simultaneously: More outputs mean more ground bounce.
• Type of output load: Lumped capaCitive loads generate 2
to 3 times more gorund bounce than system traces. IncreaSing the capacitive load increases ground bounce to
approximately 60-70 pF. Beyond 70 pF, ground bounce
drops off due to the filtering effect of the load. Moving
the load away from the output reduces the ground
bounce.
Avoid using sockets or wirewrap boards.
Avoid connecting capacitors directly to the outputs.
In addition, observing either one of the following rules is
sufficient to avoid running into any of the problems associated with ground bounce.
Use caution when driving asynchronous TTL-level inputs
from CMOS octal outputs.
• Location of the output pin: Outputs closer to the ground
pin exhibit less ground bounce than those further away.
Use caution when running control lines (set, reset, load,
clock, chip select) which are glitch sensitive through the
same device that drive data or address lines.
• Voltage: Lowering Vee reduces the ground bounce.
• Test fixtures: Standard test fixtures generate 30 to 50%
more ground bounce than a typical system since they
use capacitive loads which increase the AC load and
form LCR tank circuits that oscillate.
While it is desirable to avoid the above conditions, there are
simple precautions available which can minimize ground
bounce noise. These are:
Ground bounce produces several symptoms:
Locate these outputs as close to the ground pin as possible.
• Altered device states. FACT logic does not exhibit this
symptom.
Use the lowest Vee as possible or split the power supply.
Use board design practices which reduce any additive noise
sources, such as crosstalk, reflections, etc.
• Propagation delay degradation. FACT devices are characterized not to degrade more than 250 ps per additional
output switching.
Ground bounce is an unwanted noise source that is found in
most logic families available today. Due to increased edge
rates and voltage swings, ground bounce can be more of a
problem with new Advanced CMOS logiC families. National,
with the vast experience in high performance logic design
gained from its leadership position with the FAST family,
defined FACT logiC so that high performance problems, as
exemplified by ground bounce, were minimized while not
sacrificing performance. By following the simple deSign
guidelines outlined, deSigners can use FACT logiC to maximize system performance while ensuring their systems are
free from the problems associated with ground bounce.
• Undershoot on active outputs. The worst-case undershoot will be approximately equal to the worst-case quiet
output noise.
• Quiet output noise: FACT's worst case quiet output noise
has been measured to be around 500-1100 mV in real
system applications.
3-44
National Semiconductor
Application Note 680
Ray Mentzer
Dynamic Threshold for
Advanced CMOS logic
INTRODUCTION
Most users of digital logic are quite familiar with the threshold specifications found on family logic data sheets. Designers using products with TTL level input thresholds will see
numbers like VIH = 2.0V and VIL = O.SV. These threshold
guarantees are static, a part's response to these levels during switching transients can be undesirable. Through the
course of this paper the reader should gain an understanding for the difference between a static threshold and a dynamic threshold. This paper will also discuss how various
products respond dynamically, how dynamic thresholds are
tested, and specified. lastly, this paper will look at how
FACT Quiet Series™ has addressed and specified dynamic
threshold characteristics.
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TLlF110643-2
I'~
WHAT IS A DYNAMIC THRESHOLD?
If National Semiconductor were able to package its I.C.'s in
"ideal" packages, then dynamic and static thresholds would
be one and the same. However, our package, like that of all
our competitors, is not "ideal" and has a finite amount of
inductance associated with each signal lead. As will be
shown later, it is the inductance in the power leads which
are the primary cause for the non-ideality.
To understand the phenomena of dynamic thresholds the
properties of ground bounce must first be examined. Figure
1 is a representation for a 74XXOO product which includes
package inductance. Figure 2a shows an output pulldown
making an HLlZl transition. In discharging the load capacitor a current Ie equaling C*dv/dt flows into the chip, this
current is approximated versus time in Figure 2b. The
changing current, Ie, generates a voltage across the ground
inductor represented in Figure 2c through the equation
l *di/dt. It is the voltage across the ground inductor, commonly known as ground bounce, which is the cause for static and dynamic thresholds to differ.
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TLlF/l0643-3
FIGURE 2
The threshold of an IC is referenced to its internal ground.
Therefore, voltages induced on the ground inductor are reflected directly as a change in threshold with respect to external ground. Figure 3 shows the effects of ground bounce
on an input threshold. If when the threshold is moving it
crosses the input voltage levels, a problem area exists.
However, having the threshold cross the input level does
not necessarily induce a product failure. The threshold must
cross the input level for a period of time for a false switch to
occur. (Figure 4 shows the voltage time relationship). Note
that in the high speed technologies two things have come
together, faster delays and output edge rates, generally
meaning larger di/dt's, and an ability to react to narrower
pulses.
'00
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TLlFI10643-1
FIGURE 1. A Typical "00" 2-lnput Quad NAND Gate
3-45
•
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sition, the standard 50 pF, 500n load should be used. When
testing with an HL on the output, the TRI-STATE® ZL/LZ
500n to Vee· 2 should be used. Without the pullup resistor,
failure cannot be detected. The LZ and HZ edges create
supply noise by switching off currents being sourced or sunk
by the device. With standard AC loading, their transients are
much less than those of the other edges. Therefore, VIHD
for the chip is guaranteed by the data pins.
Each product subject to VIHDIVILD testing will have multiple
test possibilities. Through the case studies below, the reader should gain an understanding for some of the test tradeoffs.
Case 1: Product =
ACTQ244 test data pins with LH/HL
transitions.
The algorithm for this test is as follows. Maximize the number of outputs switching, N, in this case 8. N - 1 of the
inputs will be transitioning to and from nonthreshold levels,
OV-3V. The last input will transition from 3V to VILD or from
OV to VIHD. Figure 5 shows the four combinations of tests. It
should be noted that values of VILD and VIHD that induce
failure will vary as a function of the test pin. This is due
mostly to voltage drops on the internal power bussing. As a
result, pins farthest from the ground pin, and sometimes the
Vee pin, are likely to be worst case pins.
The test cases discussed in cases 1-3 are all possible test
methods, note there are other possible combinations. In
practice National has found that tests done in conjunction
with HL transitions are worst case, i.e., case 1, and will guarantee VILD and VIHD for the chip.
Case 4: Product = ACTQ374
This class of function, the non-inverting register, will have
very good data and clock pin dynamic threshold characteristics. For instance, take the worst case bounce where all
output are transitioning HL. To accomplish this, all inputs
are LOW on the active edge of clock. If a VIHD test of the
clock were performed, the positive ground bounce at some
level of VIHD will stimulate one, if not multiple, false clocks
to occur. A failure is not detected because the false clock or
clocks merely regenerated an existing low output. The positive ground bounce had the effect of making the logic low
data look lower. Always associated with positive bounce is
negative bounce, which on an HL transition occurs later. If
this negative bounce is able to switch the internal data gate,
setup and hold times have been violated and again failure is
not detected. Reference Figure 6 for a representation of this
scenario.
Case 2: Product = ACTQ244 test data pins with ZLlZH
transitions.
This test will ramp the enable pin from 3V-OV while holding
the input under test at threshold, i.e., have all outputs transitioning ZL, with N - 1 inputs at OV and the input under
test at VILD. The other tests are as follows, N - 1 transitioning ZL pin under test (PUT) at VIHD, all outs going ZH PUT
at VIHD, and N - 1 a ZH switch and PUT at VILD.
Case 3: Product = ACTQ244 test OE pin with HLlLH transitions.
VILD is the parameter to check here. Data inputs should be
switching OV-3V while the OE pin is being stepped up from
OV to VILD. While testing the OE pin with an LH output tran-
~3V
V1HD
3V~ V1LD
OV
OV
TL/F/l0643-6
(a)
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TL/F/l0643-8
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TUF/l0643-7
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FIGURE 5
3-47
VILD
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TL/F/l0643-9
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TL/F/l0643-16
FIGURE 11. 'FCT534A Data/Clock VIH Noise Margin IDT
#5 (PDIP) vs NSC #2 (CDIP) 5.0V Voo @ Room
•
3·53
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• Design Innovations
National Semiconductor
Application Note 690
Michael L. Gilbert
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QUIET-
GROUND BOUNCE NOISE PULSE
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FIGURE 4. Location of Bounce Pulse
3-56
,--------------------------------------------------------------------,
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FIGURE 5. Application Segments
WITHOUT USC
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FIGURE 6. Example of Undershoot
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WITH SPLIT BUS
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TL/F/10655-7
FIGURE 7. Example of Dynamic Threshold Shift
3·57
WHERE CAN DEVICE-GENERATED
NOISE AFFECT SYSTEM PERFORMANCE?
An integrated circuit ground inductor's di/dt is determined
by the number of outputs switching and the capacitive load
on each output. In a system, transmission line effects will
reduce the effective capacitive load the output may actually
drive. In a test fixture, the load is made up of low-dissipation
factor chip capacitors soldered directly to the output pins. In
a system, a finite physical distance separates the various
capacitive loads from each other as well as the driver's output. The net effect of capaCitance distributed along the
transmission line is to lower the effective impedance of the
transmission line. As a result, ground bounce in a system is
typically 50% less than test fixture measurements. Test fixture measurements of ground bounce should only be used
for comparative analysis and characterization.
The magnitude of system ground bounce and the segment
of applications where that bounce may present problems is
very small. Ground bounce occurs concurrently with the
transition of the active outputs of the device. Ground
bounce on quiet output(s) driving synchronous signalssuch as data and address lines-are not of concern since
these signals will not be synchronized or sampled until long
after ground bounce has settled out. See Figure 4.
However, while asynchronous Signals, such as resets, presets, latch enables, and clock lines, typically number far
fewer than synchronous signals in a system they may be
more susceptible to ground bounce.
Since substantial ground bounce voltage levels are only
achieved with six or more outputs switching simultaneously
In the same package, device with eight or more bits, i.e.,
octals, are the primary focus of ground bounce.
Also, noise Signals, such as ground bounce, driven into
CMOS-level inputs generally have no effect due to the higher amount of energy needed to switch CMOS inputs. Typical
voltage levels needed to switch full CMOS inputs are 3.0V
for approximately 2.0 ns; ground bounce levels in a system
or a test fixture do not reach this level. However, ground
bounce on asynchronous signals into TTL-input levels may
cause system errors. Typically TTL inputs need only 1. 7V of
noise of 2.0 ns to switch (e.g. FASTI!> and ALS).
For these reasons, the small segment of applications where
ground bounce noise may compound with system noise levels and possibly affect system performance is where advanced CMOS octals drive asynchronous signals into TTLlevel inputs. See Figure 5. Since the mechanisms are similar, Shifts in dynamic threshold are also a possible concern
in this small segment.
Undershoot, either on quiescent low or high-to-low switching outputs, can create noise problems in some systems by
generating excess ringing on the signal line. As stated earlier, ringing also adds to EMI and crosstalk noise. Additionally, most devices driven by logiC devices have clamp diodes
on their inputs that will limit the input voltage excursions.
However, as devices such as DRAMs, DACs, and PLDs
have no protection and are sensitive to negative voltage
excursions on the input, system faults or damage to these
devices, caused by latch-up, may result. The use of series
resistors can safeguard against such faults.
The system designer may further minimize ground bounce
and undershoot effects by choosing surface mount technology (SMT). SMT package inductance on the order of 2 nH
to 4 nH can reduce ground bounce and undershoot by as
much as 25%, without the board area penalty incurred by
larger non-standard pinout. Also, if the design allows, placing asynchronous signal lines on pins closest to the ground
pin will minimize the noise on these lines-as much. as 20%
less noise than pins furthest from ground.
If device-generated noise is still a critical issue in the system
design, National Semiconductor Corporation has implemented several design improvements that greatly minimize
deVice-generated noise. The result is an extension to the
FACTTM line-FACT Quiet Series or FACT QS.
NEW
TLlF/l0655-6
TL/F/l0655-9
. FIGURE 8_ Split Ground Bus Structure
3-58
~
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en
GTO
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SOFT TURN-ON FOR At
_____ REDUCES VOlP (2NO DERIVATIVE)
VO~
Q
..
~,"S_C_TH_R_ES_H_O_lD_ _ __
USC
CURRENT INJECTED
BY USC REDUCES
VOlV (1ST DERIVATIVE)
lOUT = -CI dVcul/dt
VOlP
VOlV
TL/F/l0655-10
FIGURE 9. National Semiconductor's Proprietary Noise Control Circuitry
DESIGN INNOVATIONS RESOLVE
DEVICE NOISE ISSUES
Resulting from output noise, dynamic threshold shifts are
worst-case under conditions of multiple simultaneously
switching outputs. Values of dynamic thresholds on advanced CMOS without the split ground bus and leadframe
range from O.3V to O.7V.
FACT aulet Series implements patented technological
breakthroughs in device-generated noise suppression as
well as several major perlormance improvements. Design
improvements include a split ground bus and leadframe, a
graduated output N-channel turn-on circuit, and an output
undershoot correction circuit.
The result of the split ground bus and leadframe is a dynamic threshold equivalent to the static threshold. For FACT
ACTO logic, typical dynamic threshold is 1.4V for a logic
low. In this way, output switching noise becomes inconsequent to the input using split ground bussing. National Semiconductor's FACT as, FACT FCT and FACT FCTA logic
lines all incorporate split ground bus and leadframe improvements.
A second design improvement, a graduated output N-channel turn-on circuit (GTOTM), greatly reduces ground bounce.
As Figure 2 illustrated, ground bounce is a function of the
output waveshape, d2v/dt2. Reducing package and chip inductance does have some effect in reducing ground
bounce, but the reduction in ground bounce is not linear
with inductance reduction. Package inductances may
change by an order of magnitude, yet ground bounce is reduced only by as much as 25%.
The first design improvement, a split ground bus and leadframe, addresses dynamic threshold shift. Since the cause
of threshold shift is noise on the IC ground bus created by
simultaneous output switching, separating the output and
input ground buses virtually eliminates dynamic threshold
shift.
FACT as has separate on-chip ground buses for the input
transistors and for the remainder of the internal gates, including the output transistors. FACT as goes one step further to isolate output noise from the inputs by implementing
a split leadframe for the ground pin. Figure 8 illustrates the
change in the ground bus structure. Note that the split leadframe joins just prior to exiting the cavity. Standard pinout,
package quality, and reliability are maintained using this
technique.
3-59
•
Second order effects, such as increases in dll dt as output
reactance is decreased, cause ground bounce reductions to
flatten as inductance is reduced. The cost of reducing inductance on dual-in-line packages is an increased number
of power and ground pins, increased package size, and a
non-standard pinout. Package pinout changes have negligible effect on surface mount devices where inductance is
low to begin with.
The greater reduction in ground bounce is found by rounding the transition point on the high-to-Iow edge, or waveshaping. Figure 9 illustrates the effect of output waves haping on ground bounce. This waveshaping is actually
achieved by combining several design techniques. The two
most notable are the slow decay of the load capacitance
charge through a soft turn-on circuit prior to the actual transition, and the delaying of the actual turn-on of the large
N-channel output transistor.
Since ground bounce levels are more substantial on the
high-to-Iow transition, the low-to-high transition remains unchanged. In addition, design considerations were taken to
ensure the integrity of the high-to-Iow edge rate, and thereby maintain device AC performance.
The third deSign improvement, undershoot corrector circuitry (USCTM), reduces output undershoot, both on the switching and quiescent (at ground) outputs. Undershoot is also a
matter of dil dt. As output edge rates speed up and voltage
swings increase, undershoot increases. Undershoot also increases as the number of simultaneously switching outputs
increases. The result, VOlV, can be seen on both the
switching edges as well as outputs quiescent at ground.
The undershoot correction circuit works by limiting negative
di/dt excursions. The first part of this two-stage circuit senses a high-ta-Iow edge. At a predetermined pOint on that
edge, the undershoot corrector is turned on. The corrector
simply activates a P-channel transistor which sources current into the output. This softens the dil dt that occurs when
the load is depleted of charge. An internal RC timer controls
the duration and decay of the correction.
Should the RC timer time out before undershoot is fully resolved, a differential amplifier, sensing that the output voltage is still below the input ground, keeps the current source
turned on.This two-stage design is more reliable because of
the time required for the current injector to turn on after the
output goes negative.
Because USC operation is affected by package inductance,
plastiC DIP packages react differently than ceramic DIP
packages. Similarly, surface mount devices have a different
correction level. As ground bounce and undershoot decrease with decreasing inductance, the need for undershoot
correction also decreases with decreasing inductance.
Ground bounce on advanced CMOS logic without output
waveshaping is on the order of 2.0V to 3.0V VOlP in a test
fixture environment. In the same environment, FACT as,
with the GTO circuitry, provides VOlP performance in the
range of 1.0V to 1.3V. In a system, 30% to 50% lower
VOlPS should result.
3-60
~
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1
FACT ACTQ244 I •
-2
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TIME (10 n./DIV)
TLlF/l0655-11
FIGURE 10. ACMOS Comparison
5
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4
3
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FIGURE 11. ACMOS Comparison
5
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90
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3
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2
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O.3V
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TI ACT11244
lOT FCT244
lOT FCT244A
FIGURE 12. ACMOS Dynamic Threshold Comparison
3·61
TL/F/l0655-13
r----------------------------------------------------------------------------,
CONTROL CIRCUITRY RESULTS IN LOWER
m
. OUTPUT
NOISE
C)
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c(
Figures 10 and 11 compare three major ACMOS product
lines. These ACMOS manufacturers have different levels of
noise suppression. All measurements were taken using an
industry-accepted fixture and methodology.
FACT as is manufactured on a smaller geometry CMOS
process than standard FACT products. Because of the use
of this technology, FACT as AC speeds are faster than
standard FACT. Propagation delays as well as set-up and
hold times are also specified identically to or faster than
standard FACT.
DESIGN IMPROVEMENTS GO BEYOND NOISE
In addition to improvements which reduce device-generated
noise, FACT as also incorporates design improvements for
greatly enhanced performance and reliability. These parameters include specification of output pin-to-pin propagation
delay skew, higher electrostatic discharge (ESO) immunity,
and higher latchup immunity, than standard FACT products.
Pin-to-pin skew becomes an issue as high-performance logic is designed into clock distribution and other timing-sensitive applications. Since, part-to-part skews are not effected
by variations in VDD or temperature, the only variable that
could effect part-to-part skew is processing variations from
one device to another. Part-to-part skews may be interpreted by subtracting the 25'C, 5.0V - VDD propagation delay
minimum specification from the maximum specification on
most advanced CMOS logic data sheets.
Guaranteed ACMOS logic pin-to-pin skew specifications are
unique to National Semiconductor's FACT as product line.
For clock distribution applications where all outputs tran-
sition to the same state simultaneously, output skew is typically less than 500 ps, with worst case being 1.0 ns. For bus
applications where outputs can transition to either state
simultaneously, typical skew is less than 800 ps, with worst
case being 1.0 ns.
Another performance improvement is higher ESO immunity.
Process improvements for FACT as have improved ESO
immunity to 8,OOOV or better. ESO is specified at 6,DOOV
typical, with worst case being at 4,OOOV minimum. MIL Class
3 (4,OOOV or more) is,guaranteed.
A third performance improvement in National's FACT as is
a higher latch-up immunity specification. As with standard
FACT, the implementation of epitaxial silicon in the FACT
process essentially eliminated latch-up possibility. The currents needed to latch-up devices manufactured on the
FACT processes are typically in excess of 1A. FACT as
latchup immunity is tested to 300 mA on the inputs and up
to 1A on the outputs. Latchup immunity is specified at
300 mA minimum at + 125'C.
REFERENCES AND BIBLIOGRAPHY
"Understanding and Minimizing Ground Bounce", Applications Note 640, National Semiconductor, Corporation, November 1989.
"FACTTM Advanced CMOS Logic Oatabook", National
Semiconductor Corporation, 1989.
"Terminations for Advanced CMOS LogiC", Applications
Note 610, National Semiconductor Corporation, May 1989.
J.L. Norman Violette, Donald R.J. White, and Michael F.
Violette, Electromagnetic Compatibility Handbook, Van
Nostrand Reinhold Co., New York, 1987.
3-62
Section 4
Advanced CMOS
Da~asheets
Section 4 Contents
54AC/74ACOO Quad 2-lnput NAND Gate. . . .... .. ... . ... .... . . . . . ... .... ... .... ... ....
54ACT174ACTOO Quad 2-lnput NAND Gate ...........................................
54AC174AC02 Quad 2-lnput NOR Gate...............................................
54ACT174ACT02 Quad 2-lnput NOR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .
54AC174AC04 Hex Inverter. .. ... ... ... . .. .. ..... ... .. . .. .. .. .. . .. . ...... ...... ..... .
54ACT174ACT04 Hex Inverter.......................................................
54AC174AC08 Quad 2-lnput AND Gate. . . . .. ... .. ... .. . .. .... . . .. ... .... . .. .. ....... .
54ACT174ACT08 Quad 2-lnput AND Gate .............................. , ....... , . . . . . .
54AC174AC10 Triple 3-lnput NAND Gate .. ,. . . .... . .. .. . . .. .. ... .. ... .... . .. ..... .... .
54ACT174ACT10 Triple 3-lnput NAND Gate...........................................
54AC174AC11 Triple 3-lnput AND Gate. .. .. . . ..... .. .. . . .. .. ..... ... .... . . ...... ... . .
54AC174AC14 Hex Inverter with Schmitt Trigger Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54AC174AC20 Dual4-lnput NAND Gate... .. ... .. .... .... .............. ... .. .... . . ... .
54AC174AC32 Quad 2-lnput OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . .
54ACT174ACT32 Quad 2-lnput OR Gate .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54AC174AC74 Dual D Positive Edge-Triggered Flip-Flop.. . . ... .. .. . ...... . .. .. .... . ....
54ACT174ACT74 Dual D Positive Edge-Triggered Flip-Flop..............................
54AC174AC86 Quad 2-lnput Exclusive-OR Gate..... . ... .. .. . .. .. . .. .... ... .. ..... ... .
54AC174AC109 Dual JK Positive Edge-Triggered Flip-Flop. . . .. .. ... .. ... .. .. .. .... . ....
54ACT174ACT109 Dual JK Positive Edge-Triggered Flip-Flop............................
54AC174AC125 Quad TRI-STATE Buffer. .. .... .. ... . ... . . . .. .... . .. ... . . .. .. .... . ....
54ACT/74ACT125 Quad TRI-STATE Buffer...........................................
54ACI74AC1381-of-8 Decoder/Demultiplexer.........................................
54ACTI74ACT1381-of-8 Decoder/Demultiplexer ......................................
54AC174AC139 DuaI1-of-4 Decoder/Demultiplexer ....................................
54ACT174ACT139 DuaI1-of-4 Decoder/Demultiplexer..................................
54AC174AC151 8-lnput Multiplexer...................................................
54ACT174ACT151 8-lnput Multiplexer................................................
54AC17 4AC153 Dual 4-lnput Multiplexer .. ,...........................................
54ACT174ACT153 Dual4-lnput Multiplexer............................................
54AC17 4AC157 Quad 2-lnput Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54ACT174ACT157 Quad 2-lnput Multiplexer .. , ............... , ....... ,................
54AC174AC158 Quad 2-lnput Multiplexer .. , ........... , ....................... , , . . . . . .
54ACT174ACT158 Quad 2-lnput Multiplexer ..................................... , . .. . .
54AC174AC161 Synchronous Presettable Binary Counter . , ... , . , .......... , . . . . . . . . . . . .
54ACT/74ACT161 Synchronous Presettable Binary Counter .......... " ............... ,.
54AC174AC163 Synchronous Presettable Binary Counter. ... .. ..... ... .. ... .. .. .. . .... .
54ACT /7 4ACT163 Synchronous Presettable Binary Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54AC174AC169 4-Stage Synchronous Bidirectional Counter.... .. ... . .. . . ......... ......
54ACT174ACT169 4-Stage Synchronous Bidirectional Counter. . . . . . . . . . . . . . . . . . . . . . . . . ..
54AC17 4AC17 4 Hex D Flip-Flop with Master Reset .. . . .. .. .. .. .. .. . . .. . .. .. . .. .. .. .. ...
54ACT174ACT17 4 Hex D Flip-Flop with Master Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
54AC17 4AC175 Quad D Flip-Flop ....................................................
54ACT174ACT175 Quad D Flip-Flop .................................. , . . . . . . . . . . . . . ..
54AC174AC191 Up/Down Counter with Preset and Ripple Clock..... . .. . .. .. . . . .. . .. ....
54AC174AC240 Octal Buffer/Line Driver with TRI-STATE Outputs........................
54ACT174ACT240 Octal Buffer/Line Driver with TRI-STATE Outputs.....................
54AC174AC241 Octal Buffer/Line Driver with TRI-STATE Outputs.................
4·2
4-5
4-5
4-9
4-9
4-13
4-13
4-17
4-17
4-21
4-21
4-25
4-28
4-31
4-34
4-34
4-38
4-38
4-44
4-47
4-47
4-53
4-53
4-57
4-57
4-63
4-63
4-68
4-68
4-74
4-74
4-79
4-79
4-84
4-84
4-89
4-89
4-97
4-97
4-105
4-105
4-113
4-113
4-119
4-119
4-125
4-132
4-132
4-136
Section 4 Contents (Continued)
54ACT 174ACT241 Octal Buffer/Line Driver with TRI-STATE Outputs ..................... 4-136
54AC174AC244 Octal Buffer/Line Driver with TRI-STATE Outputs........................ 4-140
54ACT174ACT244 Octal Buffer/Line Driver with TRI-STATE Outputs .............•....... 4-140
54AC17 4AC245 Octal Bidirectional Transceiver with TRI-STATE Inputs/Outputs ........... 4-144
54ACT174ACT245 Octal Bidirectional Transceiver with TRI-STATE Inputs/Outputs. . . . . . . .. 4-144
54AC174AC251 8-lnput Multiplexer with TRI-STATE Output.............................. 4-148
54ACT174ACT251 8-lnput Multiplexer with TRI-STATE Output.. .. ... ............ .. ...... 4-148
54AC174AC253 Dual 4-lnput Multiplexer with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . 4-154
54ACT174ACT253 Dual 4-lnput Multiplexer with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . .. 4-154
54AC17 4AC257 Quad 2-lnput Multiplexer with TRI-STATE Outputs ....................... 4-160
54ACT174ACT257 Quad 2-lnput Multiplexer with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . .. 4-160
54AC174AC258 Quad 2-lnput Multiplexer with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . 4-165
54ACT174ACT258 Quad 2-lnput Multiplexer with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . .. 4-165
54AC174AC273 Octal D Flip-Flop .................................................... 4-170
54AC174AC280 9-Bit Parity Generator/Checker. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. 4-175
54AC174AC299 8-lnput Universal Shift/Storage Register with Common Parallel I/O Pins . . .. 4-179
54ACT174ACT299 8-lnput Universal Shift/Storage Register with Common Parallel 110 Pins. . 4-179
54ACT174ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and
Common I/O Pins................................................................ 4-186
54AC174AC367 Hex TRI-STATE Buffer. .. ... ..... .. .... .......... . ... .. .. .. .......... 4-191
54ACT174ACT368 Hex TRI-STATE Inverting Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-194
54AC17 4AC373 Octal Transparent Latch with TRI-STATE Outputs ....................... 4-197
54ACT174ACT373 Octal Transparent Latch with TRI-STATE Outputs. . . . . . . . . . . . . . .. . . . . . 4-197
54AC174AC374 Octal D Flip-Flop with TRI-STATE Outputs..... ... .......... ......... ... 4-203
54ACT174ACT37 4 Octal D Flip-Flop with TRI-STATE Outputs. . . . . . . • . . . . . . . . . . . . . . . . . . .. 4-203
54AC174AC377 Octal D Flip-Flop with Clock Enable..... ... .. ... .. ...... .. .... .. ....... 4-209
54ACT17 4ACT377 Octal D Flip-Flop with Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-209
54AC/74AC378 Parallel D Register with Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-215
54ACT174ACT399 Quad 2-Port Register.............................................. 4-219
54AC174AC520 8-Bit Identity Comparator. .. ... ..... .. ..... ... .. ... ............ .... ... 4-223
54ACT174ACT520 8-Bit Identity Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-223
54AC174AC521 8-Bitldentity Comparator. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . .. . . . .. 4-229
54ACT174ACT521 8-Bit Identity Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-229
54ACT174ACT534 Octal D Flip-Flop with TRI-STATE Outputs............................ 4-235
54AC174AC540 Octal Buffer/Line Driver with TRI-STATE Outputs. . . . . . . . . . . . . . . . . .. . . .. . 4-240
54AC17 4AC541 Octal BufferlLine Driver with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . 4-243
54ACT174ACT563 Octal Latch with TRI-STATE Outputs ................................ 4-246
54ACT174ACT564 Octal D Flip-Flop with TRI-STATE Outputs............................ 4-251
54ACT174ACT573 Octal Latch with TRI-STATE Outputs................................ 4-254
54AC174AC574 Octal D Flip-Flop with TRI-STATE Outputs.............................. 4-259
54ACT174ACT57 4 Octal D Flip-Flop with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-259
54AC174AC646 Octal Transceiver/Register with TRI-STATE Outputs. .. . . . . . . . . . . . .• . . . .. 4-265
54ACT174ACT646 Octal Transceiver/Register with TRI-STATE Outputs .................. 4-265
54AC174AC648 Octal Transceiver/Register with TRI-STATE Outputs.... ... .. .... ... ..... 4-272
54ACT174ACT705 Arithmetic Logic Unit for Digital Signal Processing Applications . . . . . . . . . . 4-278
54ACT17 4ACT715 Programmable Video Sync Generator. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-279
LM1882 Programmable Video Sync Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-279
54ACT174ACT818 8-Bit Diagnostic Register........................................... 4-288
54AC17 4AC821 1O-Bit D Flip-Flop with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-294
54ACT174ACT821 1O-Bit D Flip-Flop with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-294
54ACT174ACT823 9-Bit D Flip-Flop................................................... 4-300
54ACT174ACT825 8-Bit D Flip-Flop................................................... 4-304
4-3
Section 4 Contents (Continued)
54ACTl74ACT84110-BitTransparent Latch with TRI-STATE Outputs.....................
54AC174AC843 9-Bit Transparent Latch ..............................................
54ACT174ACT843 9-BitTransparent Latch............................................
54ACT17 4ACT845 8-Bit Transparent Latch with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . .
54AC174AC899 9-Bit Latchable Transceiver Register with Parity Generator/Checker .......
54ACT174ACT899 9-Bit Latchable Transceiver Register with Parity Generator/Checker. . . ..
54AC174AC2525 Minimum Skew Clock Driver .............•...........................
54AC17 4AC2526 Minimum Skew Clock Driver with Multiplexed Clock Input .. . . . . . . . . . . . . . .
54AC174AC2708 64 x 9 First-In, First-Out Memory ............. " ............ , . . .. . .. ...
54ACT17 4ACT2708 64 x 9 First-In, First-Out Memory .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54ACT174ACT2725 512 x 9 First In, First Out Memory (FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . ..
54ACT174ACT2726 512 x 9 Bidirectional First-In, First-Out Memory (BiFIFO). . . . . . . . . . . . . . .
4-4
4-308
4-313
4-313
4-321
4-326
4-326
4-338
4-338
4-339
4-339
4-355
4-356
r-----------------------------------------------------------------~Q
Q
~National
~ Semiconductor
54AC/74ACOO • 54ACT17 4ACTOO
Quad 2-lnput NAND Gate
General Description
Features
The 'ACt'ACTOO contains four 2-input NAND gates.
• Outputs sourcetsink 24 mA
• 'ACTOO has TTL-compatible inputs
• Standard Military Drawing (SMD)
- 'ACOO: 5962-87549
- 'ACTOO: 5962-87699
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
AO
Pin Assignment
forlCC
B1 NC A1 NC ° 0
[[][l][[]l]]m
00
Bo
Ao
A1
Bo
°1
B1
A2
°2
B2
°0
A1
B1
2
A2
3
B2
5
6
A3
°3
B3
°1
GND
B3
7
TLlF/9911-1
TL/F/9911-3
° 11]]
GND [QJ
Ne I.i]
mBo
mAo
(IlNC
°3 1ll1
B31J.jJ
I@lvcc
IlIDA2
1Bl1lID1iE1i1l1iID
A3NC~NC~
TL/F/9911-2
Pin Names
Description
Inputs
Outputs
4-5
o
o
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specIfIcations.
-0.5V to + 7.0V
Supply Voltage {Vee>
DC Input Diode Current (11K)
-20mA
VI = -0.5V
VI = Vee + 0.5V
+20mA
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
-20mA
Vo = -0.5V
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5V to to Vee + 0.5V
DC Output Source
±50mA
or Sink Current (10)
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGNO)
-65·Cto + 150"C
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
175·C
PDIP
140·C
Nate 1: Absolute maximum ratings ara those values beyond which damage
to the device may occur. The dalabook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and outputlinput loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
Supply Voltage {Vee>
'AC
'ACT
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (IW/At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (AV/At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vt06.0V
4.5Vto 5.5V
OVtoVee
OVtoVee
-40·Cto +85·C
- 55·C to + 125·C
125 mVins
125mV/ns
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
= +2S·C
Typ
VIH
VIL
VOH
liN
74AC
TA =
-40"Cto +8S·C
Units
Conditions
Guaranteed LimIts
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.tV
or Vee - O.tV
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/-LA
3.0
4.5
5.5
VOL
S4AC
TA =
-SS·C to + 12S·C
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc III 3.0V are guaranteed to be less than or equal to the respective limit III S.SV Vee.
lee for S4AC III 2S'C is identical to 74AC @ 25·C.
4-6
lOUT
= - 50 IJA
·VIN
= VILorVIH
10H
-12mA
-24mA
-24mA
lOUT
= 50/-LA
'VIN
= VILorVIH
10L
VI
12mA
24mA
24mA
= Vee,GND
o
o
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA =
-40'Cto +85'C
Typ
tMinimum Dynamic
Output Current
IOLD
IOHD
Maximum Quiescent
Supply Current
Icc
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
80.0
40.0
IJ-A
VIN = Vee
orGND
5.5
4.0
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Icc @ 3.0V are guaranteed to be less than or equal to
Icc for 54AC @ 25'C is identical to 74AC @ 25'C.
Nole: liN and
the respective limit
@
5.5V Vee.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +25'C
TA =
-55'C to + 125'C
TA=
-40'Cto +85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
orVce - O.lV
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = O.W
orVec - O.lV
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
IJ-A
1.6
1.5
mA
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.001
0.001
Conditions
Guaranteed Limits
0.6
lOUT = -50 IJ-A
'VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50 IJ-A
'VIN = VIL or VIH
24mA
24mA
IOL
VI = Vce,GND
VI = Vee - 2.1V
5.5
50
75
mA
5.5
-50
-75
mA
VOHD = 3.85V Min
IJ-A
VIN = Vec
orGND
5.5
4.0
80.0
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Nole:
Units
Icc for 54ACT @ 25'C is identical to 74ACT @ 25'C.
4-7
40.0
VOLD = 1.65V Max
II
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
See Section 2 for waveforms
74AC
S4AC
74AC
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40"C
to +8S'C
CL = SOpF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
3.3
5.0
2.0
1.5
7.0
6.0
9.5
8.0
1.0
1.0
11.0
8.5
2.0
1.5
10.0
8.5
ns
2-3,4
tpHL
Propagation Delay
3.3
5.0
1.5
1.5
5.5
4.5
8.0
6.5
1.0
1.0
9.0
7.0
1.0
1.0
8.5
7.0
ns
2-3,4
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
AC Electrical Characteristics:
See Section 2 for waveforms
74ACT
S4ACT
74ACT
TA = +2S'C
CL = SOpF
TA = -SS'C
to·+12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = 50pF
Parameter
Vee'
(V)
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
5.0
1.5
5.5
9.0
1.0
9.5
1.0
9.5
ns
2-3,4
tpHL
Propagation Delay
5.0
1.5
4.0
7.0
1.0
8.0
1.0
8.0
ns
2-3,4
Symbol
Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
Vee
=
5.0V
CPD
Power Dissipation
Capacitance
30.0
pF
Vee
=
5.0V
4-8
Conditions
.---------------------------------------------------------------------~
c
I\)
~National
~ Semiconductor
54AC/7 4AC02-S4ACT /7 4ACT02
Quad 2-lnput NOR Gate
General Description
Features
The 'AC02/'ACT02 contains four, 2-input NOR gates.
EJ Outputs sourcel sink 24 mA
The information on the ACT02 is Preliminary
Information Only_
III
EI
'ACT02 has TTL-compatible inputs
Standard Military Drawing (SMD)
- AC02: 5962-87612
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEEIIEC
Pin Assignment for
DIP, Flatpak and SOIC
AO
Pin Assignment
forlCC
00
80
00
AI
01
81
Ao
80
A2
O2
82
01
AI
A3
03
83
81
GND
AI NC 0 1 NC
Be
lID IIlI]] I]] [I]
Vee
2
O2
3
82
4
A2
5
03
83
6
7
81[II
GND [j]J
NC [j]
[II Ao
[I] 0 0
[IlNC
A3 1m
83~
Ii]J 02
~Vcc
A3
TLlF/9912-1
TLlF/9912-3
1iJl1i]J1i]J1lZI1i]]
03NC~NC~
TLlF/9912-2
Pin Names
Description
Inputs
Outputs
•
4-9
N
o
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage {Vecl
DC Input Diode Current (lUG
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
-0.5VtotoVee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (lee or IGND)
±50mA
Storage Temperature (Tsm)
2.0Vt06.0V
4.5Vt05.5V
Input Voltage (VI)
OV to Vee
Output Voltage (VO)
OVtoVee
Operating Temperature (TAl
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Diode Current (loKl
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage {Vecl
'AC
'ACT
-0.5Vto +7.0V
- 65'C to + 150'C
-40'Cto +85'C
- 55'C to + 125'C
Minimum Input Edge Rate (AViAt)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (AV/At)
'ACT Devices
VIN from O.BV to 2.0V
Vee @ 4.5V, 5.5V
125mV/ns
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and oulputlinput loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
=
+25'C
Typ
VIH
VIL
VOH
liN
74AC
TA =
- 40'C to + 85'C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = O.tV
or Vee - O.IV
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.IV
or Vee - O.tV
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
3.0
4.5
5.5
VOL
54AC
TA =
- 55'C to + 125'C
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under tesl
tMaximum test duration 2.0 ms, one output loaded at a time.
4-10
lOUT
=
-50/LA
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT
= 50/LA
'VIN
= VIL or VIH
10L
12mA
24mA
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
S4AC
74AC
TA = +2SoC
TA=
-SsoC to + 12SoC
TA=
- 40°C to + 8SoC
Typ
IOLD
IOHD
ICC
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
VOLO = 1.65V Max
Guaranteed Limits
5.5
50
75
mA
5.5
-50
-75
mA
VOHD = 3.85V Min
/LA
VIN = VCC
orGND
5.5
4.0
80.0
•All outputs loaded; thresholds on input associated with output under test
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranleed 10 be less Ihan or equal 10 Ihe respective limit
Icc for 54AC @ 25'C is idenlical to 74AC @ 25'C.
40.0
@
5.5V Vee.
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
S4ACT
74ACT
TA = +2SoC
TA=
-SsoC to + 12SoC
TA =
-40"Cto +8SoC
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
orVCC - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
/LA
1.6
1.5
rnA
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Iccllnput
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
ICC
Maximum Quiescent
Supply Current
0.001
0.001
0.6
lOUT = -50/LA
·VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50/LA
'VIN = VIL or VIH
24 rnA
IOL
24 rnA
VI = Vcc,GND
VI = Vcc - 2.1V
5.5
50
75
rnA
VOLD = 1.65V Max
5.5
-50
-75
rnA
VOHD = 3.85V Min
80.0
40.0
/LA
VIN = Vcc
orGND
5.5
4.0
• All oulputs loaded; Ihresholds on input associated wilh output under test.
tMaximum lesl duralion 2.0 ms, one oulpul loaded al a time.
NOle: Icc for 54ACT @ 25'C Is identical to 74ACT @ 25'C.
4-11
N
CI
AC Electrical Characteristics:
Parameter
Symbol
Vee'
(V)
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25"C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL=50pF
Min
Typ
Max
Min
Max
Min
Max
Units
Fig.
No.
tpLH
Propagation Delay
3.3
5.0
1.5
1.5
5.0
4.0
7.5
6.0
1.0
1.0
9.0
7.0
1.0
1.0
8.0
6.5
ns
2-3,4
tpHL
Propagation Delay
3.3
5.0
1.5
1.5
5.0
4.5
7.5
6.5
1.0
1.0
9.0
7.5
1.0
1.0
8.0
7.0
ns
2-3,4
Units
Fig.
No.
'Voltage Range 3.3 Is 3.3V ± 0.3V
Voltage Range 5.0 I. S.OV ± O.SV
AC Electrical Characteristics:
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25"C
CL = 50pF
TA = -55'C
to + 125'C
CL=50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Min
Parameter
Vee'
Min
Typ
Max
Propagation Delay
5.0
1.0
6.0
8.5
1.0
9.0
ns
2-3,4
Propagation Delay
tpHL
'Voltage Range 5.0 Is S.OV ± o.sv
5.0
1.0
6.5
9.5
1.0
10.0
ns
2-3,4
Symbol
tpLH
(V)
Max
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation Capacitance
30.0
pF
Vee = 5.0V
4-12
Max
~--------------------------------------------------------------------~o
~
~National
~ Semiconductor
54AC/74AC04 • 54ACT17 4ACT04
Hex Inverter
General Description
Features
The 'AC/'ACT04 contains six inverters.
• Outputs source/sink 24 mA
• 'ACT04 has TTL-compatible inputs
• Standard Military Drawing (SMD)
--'AC04: 5962-87609
The information for the ACT04 is preliminary
information only.
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
Ao
°0
AI
°1
A2
°2
A3
°3
A4
°4
As
°5
TLlF/9913-1
14
Ao
Pin Assignment
forLCC
~NCOINCA,
[[)[l]rn:J[IJ[i]
Vee
A3
°0
AI
°1
A2
°2
GND
moo
°3
A.
°21]]
GND IIQI
NC Ii]
IIlAo
°4
As
Os Ii]
BQlVee
As~
IJjJA3
TL/F/9913-3
[I]NC
~1iID1i]J1i1I1i]J
0.
NC ~ NC
03
TL/F/9913-2
Pin Names
Description
Inputs
Outputs
4-13
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
-0.5Vto +7.0V
DC Input Diode Current (111<>
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (10K>
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
DC Output Source
or Sink Current (10)
Supply Voltage (Vecl
'AC
'ACT
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (AVI At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (AVI At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
-20 rnA
+20 rnA
-0.5VtoVee + 0.5V
-20 rnA
+20mA
-0.5V to to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (lee or IGNO)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
PDIP
2.0Vt06.0V
4.5Vt05.5V
±50mA
- 65°C to + 1500C
OVtoVee
OVtoVee
-40°C to +85°C
-55°C to + 125°C
125 mVins
125mVlns
175°C
1400C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specHicatlons should be met wHhout
exception. to ensure that the system design Is reliable over Its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vec
(V)
74AC
54AC
74AC
TA = +25°C
TA=
- 55°C to + 12SOC
TA=
- 40"C to + 8SOC
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
orVee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under test
tMaxlmum test duration 2.0 ms, one output loaded at a time.
4-14
lOUT = - 50 /LA
·VIN = VIL or VIH
-12mA
-24 rnA
10H
-24mA
lOUT = 50/LA
·VIN = VIL or VIH
12mA
24 rnA
10L
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA =
-40'Cto +85'C
Typ
IOLD
IOHD
lee
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
S.S
SO
75
mA
YOLO = 1.65V Max
S.5
-50
-75
mA
YOHD = 3.85V Min
80.0
40.0
p.A
YIN = Vee
orGND
4.0
5.5
'All outputs loaded; thresholds on input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit
Icc for S4AC @ 25'C is identical to 74AC @ 2S'C.
@
S.SV Vcc.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.S
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
orVec - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = O.W
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.S
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
IOL
±0.1
±1.0
±1.0
p.A
VI = Vee,GND
1.6
1.5
mA
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
leellnput
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
lee
Maximum Quiescent
Supply Current
0.001
0.001
Conditions
Units
Guaranteed Limits
0.6
lOUT = - 50 p.A
'VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50 p.A
'VIN = VIL or VIH
24mA
24mA
VI = Vee - 2.W
5.5
SO
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
80.0
40.0
p.A
VIN = Vee
orGND
5.S
4.0
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one oulput loaded at a time.
Note: Icc for 54ACT @ 2S'C is identical to 74ACT @ 2S'C.
4·15
AC Electrical Characteristics:
Symbol
Vee'
Parameter
(V)
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'<:
CL = 50pF
Min
Typ
Max
Min
Max
Min
Max
Units
Fig.
No.
tpLH
Propagation Delay
3.3
5.0
1.5
1.5
4.5
4.0
9.0
7.0
1.0
1.0
11.0
8.5
1.0
1.0
10.0
7.5
ns
2·3,4
tpHL
Propagation Delay
3.3
5.0
1.5
1.5
4.5
3.5
8.5
6.5
1.0
1.0
10.0
7.5
1.0
1.0
9.5
7.0
ns
2·3,4
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 Is 5.0V ± 0.5V
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
Min
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to + 85'C
CL = 50pF
Min
Min
Typ
Max
Max
Max
tpLH
Propagation Delay
5.0
1.0
6.0
8.5
1.0
9.0
ns
2·3,4
tpHL
Propagation Delay
5.0
1.0
5.5
8.0
1.0
8.5
ns
2·3,4
'Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
Vee
= 5.0V
CPD
Power Dissipation
Capacitance
30.0
pF
Vee
= 5.0V
4·16
Conditions
,---------------------------------------------------------------------, 0
0:1
~National
~ Semiconductor
54AC/74AC08 • 54ACT17 4ACT08
Quad 2-lnput AND Gate
General Description
Features
The 'ACI'ACT08 contains four, 2-input AND gates.
The information for the ACTOS is preliminary
information only.
• Outputs source/sink 24 mA
• 'ACT08 has TTL-compatible inputs
• Standard Military Drawing (SMD)
- 'AC08: 5962-87615
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIlEC
Ao
Pin Assignment
for LCC
Bl NC AI NC 00
rn:J[1]rn:J[[J[±]
&;
°0
Bo
AI
IiID
NC !IiI
°3 1ll1
mAo
GND
A2
°2
B2
mBa
°1 00
°1
Bl
[ONC
~Vcc
Ii]]A2
B3~
A3
°3
B3
Jl]J1i]J[§J1i1l1l]J
TL/F/9914-1
TL/F/9914-3
A3NC~NCB2
TLlF/9914-2
Pin Names
Description
An,Sn
On
Inputs
Outputs
4-17
Absolute Maximum Rating (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee>
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
±50mA
Storage Temperature (TSTG)
2.0Vto 6.0V
4.5Vt05.5V
Input Voltage (VI)
OVtoVee
Output Voltage (V0)
OVtoVee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Diode Current (10K>
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage (Vee)
'AC
'ACT
-65'Cto + 150'C
- 40'C to + 85'C
- 55'C to + 125'C
Minimum Input Edge Rate (~V/~t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (~VI~t)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature. and outpullinputloading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
S4AC
74AC
TA = +2S'C
TA =
-SS'C to + 12S'C
TA =
- 40'C to + 8S'C
Typ
VIH
ViL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = O.W
or Vee - O.W
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.W
or Vee - O.W
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
• All outputs loaded; thresholds on input associated with output under test
tMaximum test duration 2.0 ms, one output loaded at a time.
4-18
lOUT = -50/LA
'VIN = VIL orVIH
-12mA
-24mA
IOH
-24mA
lOUT = 50/LA
'VIN = VILorVIH
12mA
24mA
IOL
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
40.0
p.A
VIN = Vcc
orGND
Maximum Quiescent
5.5
4.0
80.0
Supply Current
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Nole: liN and lee @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
Icc for 54AC @ 25'C is Identical to 74AC @ 25'C.
Icc
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'Cto +85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
O.B
O.B
O.B
0.8
O.B
V
VOUT = 0.1V
orVcc - O.IV
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
p.A
1.6
1.5
mA
5.5
50
75
mA
5.5
-50
-75
mA
VOHD = 3.B5V Min
p.A
VIN = Vcc
orGND
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5,5
ICCT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
0.001
0.001
Units
Conditions
Guaranteed Limits
0.6
Maximum Quiescent
5.5
4.0
Supply Current
•All outputs loaded; thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
Nole: lee for 54ACT @ 25'C is Identical to 74ACT @ 25'C.
IcC
80.0
4-19
40.0
lOUT = -50 p.A
·VIN = VIL or VIH
-24mA
-24mA
IOH
lOUT = 50 p.A
·VIN = VIL or VIH
24mA
IOL
24mA
VI = Vcc,GND
VI = Vcc - 2.1V
VOLD = 1.65V Max
AC Electrical Characteristics:
Symbol
Vee'
Parameter
(V)
See Section 2 for waveforms.
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
3.3
5.0
1.5
1.5
7.5
5.5
9.5
7.5
1.0
1.0
12.5
9.0
1.0
1.0
10.0
8.5
ns
2-3,4
tpHL
Propagation Delay
3.3
5.0
1.5
1.5
7.0
5.5
8.5
7.0
1.0
1.0
11.5
8.5
1.0
1.0
9.0
7.5
ns
2-3,4
Units
Fig.
No.
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics:
See Section 2 for waveforms.
74ACT
54ACT
74ACT
TA = +25'C
CL=50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Min
Max
10.0
ns
2-3,4
10.0
ns
2-3,4
Parameter
Vee'
(V)
tpLH
Propagation Delay
5.0
1.0
6.5
9.0
1.0
tpHL
Propagation Delay
5.0
1.0
6.5
9.0
1.0
Symbol
Min
'Voltage Range 5.0 Is 5.0V
Typ
Max
Max
± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CpO
Power Dissipation
Capacitance
20.0
pF
4-20
Vee = 5.0V
r---------------------------------------------------------------------~
~National
~ Semiconductor
54AC/74AC10 CD 54ACT/74ACT10
Triple 3-lnput NAND Gate
General Description
Features
The 'AC/'ACT10 contains three, 3-input NAND gates.
• Outputs source/sink 24 mA
II Standard Military Drawing (SMD)
- 'AC10: 5962-87610
The information for the ACT10 is Preliminary
Information only_
Ordering Code:
See Section 8
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
Ao
&
00
80
Co
AI
01
81
Cl
Ao
Cl NC 81 NC AI
III[§] [[][!]
1
ffiJ
2
Bo
AI 3
m
O2
82
Cl 5
- 6
TLIF/9915-1
Description
Inputs
Outputs
~Vcc
IiIDCo
GND 7
TL/F/9915-3
Pin Names
mNC
°21i11
C2 1l]J
C2
An, Bn, Cn
On
mBa
rIMa
°l
GND [QJ
NC [j)
B1 4
°1
A2
Pin Assignment
forlCC
[1JliIDl!IDllZIl!ID
82 NC A2 NC 00
TL/F/9915-2
4-21
~
o
....o
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
-0.5Vto +7.0V
DC Input Diode Current (111<>
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (10K>
-20mA
Vo = -0.5V
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5Vto to Vee + 0.5V
DC Output Source
±50mA
or Sink Current (Io)
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGND)
Storage Temperature (TSTG)
- 65'C to + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook speeHlcations should be met, without
exception, to ensure that the system design Is reliable over Its power supply,
temperature, and outputlinput loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
Supply Voltage (Vee)
'AC
'ACT
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (AV/At)
'AC Devices
VIN from 30% to 70% of Vce
Vee @3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (AVI At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee@4.5V,5.5V
2.0Vt06.0V
4.5Vt05.5V
OV to Vee
OVtoVee
-40'Cto +85'C
-55'Ctc + 125'C
125 mV/ns
125 mV/ns
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'Cto +85'C
Typ
VIH
VIL
VOH
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.lV
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
±1.0
±1.0
fJoA
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
Maximum Input
5.5
±0.1
Leakage Current
•All outputs loaded; thresholds on input associated with output under test
tMaximum tast duration 2.0 ms, one output toaded at a time.
liN
4-22
lOUT = -50fJoA
·VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50p.A
·VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
....o
DC Characteristics for' AC Family Devices (Continued)
74AC
Symbol
Parameter
Vee
(V)
=
TA
+25'C
Typ
tMinimum Dynamic
Output Current
IOLD
IOHD
Maximum Quiescent
Supply Current
Icc
54AC
74AC
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD
=
1.65V Max
5.5
-50
-75
mA
VOHD
=
3.85V Min
",A
VIN = Vee
orGND
4.0
5.5
80.0
40.0
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: liN and Icc
@
Icc for 54AC
3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
25'C is identical to 74AC @ 25'C.
@
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA =
- 55'C to + 125'C
TA =
- 40'C to + 85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVce - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = O.W
or Vee - O.W
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
",A
1.6
1.5
rnA
Symbol
TA
=
+25'C
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.001
0.001
0.6
lOUT
=
-50 ",A
'VIN
=
VIL or VIH
-24 rnA
-24 rnA
lOUT
=
50 ",A
'VIN
=
VIL or VIH
24mA
24 rnA
IOH
IOL
VI
=
Vee,GND
VI
=
Vee - 2.W
5.5
50
75
rnA
VOLD
=
1.65V Max
5.5
-50
-75
rnA
VOHD
=
3.85V Min
",A
VIN = Vee
orGND
5.5
4.0
80.0
• All outputs loaded; thresholds on input associated with output under test.
@
Conditions
Guaranteed Limits
tMaximum test dUration 2.0 ms. one output loaded at a time.
Note: Icc for 54ACT
Units
25'C is identical to 74ACT
@
25'C.
4-23
40.0
o
.,...
AC Electrical Characteristics:
Symbol
Vee·
(V)
Parameter
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
3.3
5.0
1.5
1.5
6.0
4.5
9.5
7.0
1.0
1.0
11.0
8.5
1.0
1.0
10.5
8.0
ns
2-3,4
tpHL
Propagation Delay
3.3
5.0
1.5
1.5
5.5
4.0
8.5
6.0
1.0
1.0
10.0
7.0
1.0
1.0
10.0
6.5
ns
2-3,4
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
AC Electrical Characteristics:
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Parameter
Vee·
(V)
Min
Typ
Max
Min
Max
tpLH
Propagation Delay
5.0
1.0
6.5
9.0
1.0
10.0
ns
2-3,4
tpHL
Propagation Delay
5.0
1.0
6.5
9.0
1.0
9.5
ns
2-3,4
Symbol
Max
'Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
25.0
pF
4-24
Vee = 5.0V
,---------------------------------------------------------------------,
~National
~ Semiconductor
54AC/74AC11
Triple 3-lnput AND Gate
General Description
Features
The' AC11 contains three 3-input AND gates.
• Outputs source/sink 24 mA
• Standard Military Drawing (SMD)
- 'AC11: 5962-87611
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEE/IEC
Ao
Bo
Co
Al
Bl
C1
Al
°1
GND
C1
2
Co
3
00
4
A2
5
B2
6
°1
IIHl][IIIID III
Vec
AO
Bo
Bl
Pin Assignment
for LCC
C1 NC Bl NC Al
Pin Assignment
for DIP, Flatpak and SOIC
I!c
Cz
7
NC IIil
mBo
mAo
[I]NC
°2irn
C2 §
gQJ Vee
Il]JCo
°1rn:J
GND IlQ]
°2
1iJj[j]J1i]]1i1l1i]]
TL/F/9916-3
A2
B2 NC
Az
NC 00
TL/F/9916-2
B2
C2
TL/F/9916-1
Pin Names
Description
Inputs
Outputs
4-25
~
~
.....
.....
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee>
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
±50mA
-65'C to + 150'C
Storage Temperature (T8TG)
2.0Vt06.0V
4.5Vt05.5V
Input Voltage (VI)
OVtoVcc
Output Voltage (Vo)
OVtoVee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (VO)
Supply Voltage (Vee>
'AC
'ACT
-40'Cto + 85'C
-55'Cto + 125'C
Minimum Input Edge Rate (AV/At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mVlns
Minimum Input Edge Rate (AV/At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125mV/ns
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
S4AC
74AC
TA = +2S'C
TA =
- SS'C to + 12S'C
TA=
- 40'C to + 8S'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-26
lOUT = -50/LA
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50/LA
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vcc.GND
........
DC Characteristics for' AC Family Devices (Continued)
Symbol
Vee
(V)
Parameter
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA =
-40'Cto +85'C
Typ
tMinimum Dynamic
Output Current
IOLD
IOHD
Maximum Quiescent
Supply Current
Icc
@
Guaranteed Limits
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
80.0
40.0
p.A
VIN = Vee
orGND
5.5
2S'C Is Identical to 74AC
AC Characteristics:
Symbol
4.0
@
@
S.SV Vee.
2S'C.
See Section 2 for waveforms
Vee·
(V)
Parameter
Conditions
5.5
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective timlt
Icc for S4AC
Units
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
3.3
5.0
1.5
1.5
5.5
4.0
9.5
8.0
1.0
1.0
11.0
8.5
1.0
1.0
10.0
8.5
ns
2-3,4
tpHL
Propagation Delay
3.3
5.0
1.5
1.5
5.5
4.0
8.5
7.0
1.0
1.0
10.5
8.0
1.0
1.0
9.5
7.5
ns
2-3,4
'Voltage Range 3.3 Is 3.3V ±0.3V
'Voltage Range 5.0 is S.OV ± o.sv
Capacitance
Symbol
Parameter
CIN
Input Capacitance
CPD
Power Dissipation
Capacitance
Typ
Units
4.5
pF
20.0
pF
4-27
Conditions
Vee = 5.0V
Vee = 5.0V
....
~ r---------------------------------------------------------------------------~
~National
~ Semiconductor
54AC/74AC14
Hex Inverter with Schmitt Trigger Input
General Description
The 'AC14 contains six inverter gates each with a Schmitt
trigger input. The 'AC14 contains six logic inverters which
accept standard CMOS input signals and provide standard
CMOS output levels. They are capable of transforming
slowly changing input signals into sharply defined, jitter-free
output signals. In addition, they have a greater noise margin
than conventional inverters.
The 'AC14 has hysteresis between the positive-going and
negative-going input thresholds (typically 1.0V) which is determined internally by tranSistor ratios and is essentially insensitive to temperature and supply voltage variations.
Features
• Outputs source/sink 24 mA
• Standard Military Drawing (SMD)
- 'AC14: 5962-87624
Ordering Code: See Section 8
Connection Diagrams
Logic Symbol
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
Pin Assignment
forlCC
12 NC
.II'
00
I,
.II'
0,
02 [I]
02
GNDIi]]
HC [i]
.II'
12
0,
NC I,
[[)ml!]l]J[!J
10
moo
mlo
[i)NC
03 1m
13
.II'
°3
14
.II'
°4
15
.II'
05
fiQlVcc
lim 15
13 Ii]
~[§JffIDliZlli]]
TLIFI9917-2
04 NC 14 NC
Os
TLIF19917-3
TLIF19917-1
Function Table
Input
Output
A
0
L
H
H
L
4-28
Pin Names
D&scrlption
In
On
Inputs
Outputs
Recommended Operating
Conditions
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
-0.5Vto +7.0V
Supply Voltage (Vee>
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (aV/at)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (aVI at)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
DC Input Diode Current (11K)
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
-20mA
Va = -0.5V
+20mA
Va = Vee + 0.5V
DC Output Voltage (Va)
-0.5V to to Vee + 0.5V
DC Output Source
±50mA
or Sink Current (10)
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGNO)
- 65'C to + 150'C
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to tha davice may occur. Tha datebook spacifications should be mat, without
excaption, to ensura that tha system design Is reliable ovar its power supply,
temparatura, and output/input loading variables. National does not recom·
mend operation of FACnM circuits outsida databook specifications.
2.0Vto 6.0V
4.5Vt05.5V
OVtoVee
OVtoVee
-40'Cto + 85'C
-55'C to + 125'C
125 mV/ns
125 mV/ns
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA = +25'C
Typ
VOH
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
Maximum Low Level
Output Voltage
liN
Maximum Input
Leakage Current
Vt+
Maximum Positive
Threshold
-55'C to
+ 125'C
- 40'C to + 85'C
Units
2.9
4.4
5.4
2.9
4.4
5.4
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
p.A
3.0
4.5
5.5
2.2
3.2
3.9
2.2
3.2
3.9
2.2
3.2
3.9
V
0.5
0.9
1.1
0.5
0.9
1.1
V
3.0
4.5
5.5
0.002
0.001
0.001
Conditions
Guaranteed Limits
3.0
0.5
4.5
0.9
5.5
1.1
•All outputs loaded; thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
Vt-
74AC
TA =
2.9
4.4
5.4
3.0
4.5
5.5
VOL
54AC
TA =
Minimum Negative
Threshold
4·29
lOUT
= -50 p.A
'VIN
= Vil or VIH
V
-12mA
-24mA
-24mA
IOH
lOUT
= 50 p.A
'VIN
= Vil or VIH
IOl
VI
12mA
24mA
24mA
= Vee, GND
TA
= Worst Case
TA
= Worst Case
II
DC Characteristics for' AC Family Devices (Continued)
Vee
(V)
Symbol
Parameter
Vh(max)
Maximum Hysteresis
74AC
S4AC
74AC
TA = +25"C
TA =
-SsoC to + 12SoC
TA=
- 40"C to + 8SoC
Typ
Vh(min)
IOHD
1.2
1.4
1.6
1.2
1.4
1.6
1.2
1.4
1.6
V
Minimum Hysteresis . 3.0
4.5
5.5
0.3
0.4
0.5
0.3
0.4
0.5
0.3
0.4
0.5
V
Maximum Quiescent
Supply Current
Icc
Conditions
Guaranteed Limits
3.0
4.5
5.5
tMinimum Dynamic
Output Current
IOLD
Units
TA = Worst Case
TA = Worst Case
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.85V Min
80.0
40.0
/kA
VIN = Vee
orGND
4.0
5.5
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc
@
Icc for 54AC
3.0V are guaranteed to be less than or equal to the respective limit
@
25"C Is identical to 74AC
@
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
@
5.5V Vee.
25'C.
See Section 2 for waveforms
74AC
S4AC
74AC
TA = +25"C
CL = SOpF
TA = -SSoC
to + 125"C
CL = SOpF
TA = -40"C
to +8SoC
CL = SOpF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
3.3
5.0
1.5
1.5
9.5
7.0
13.5
10.0
1.0
1.0
16.0
12.0
1.5
1.5
15.0
11.0
ns
2·3,4
tpHL
Propagation Delay
3.3
5.0
1.5
1.5
7.5
6.0
11.5
8.5
1.0
1.0
14.0
10.0
1.5
1.5
13.0
9.5
ns
2·3,4
'Voltage Range 3.3 Is 3.3V
Voltage Range 5.0 is 5.0V
± 0.3V
± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
25.0
pF
4·30
Vee = 5.0V
~National
~ Semiconductor
54AC/74AC20
Dual 4-lnput NAND Gate
General Description
Features
The 'AC20 contains four 4-input NAND gates.
• Outputs source/sink 24 rnA
• Standard Military Drawing (SMD)
- 'AC20: 5962-87613
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIIEC
Ao
Pin Assignment
farlCC
Do
It
Bo
Co
Do
NC
Co NC NC
[ID1IJ[ID[[J[i]
Ao-"'+-----,
Bo 2
NC 3
00 [ID
@JBO
Co 4
Do 5
GND IlQI
NC Ii]
lIIAo
00
6
0t 1m
[TINC
@IVcc
Dtli]J
/!IDAt
GND 7
At
Bt
TLlF/991 B-3
Ot
Ct
Ii]] [ffi1i]]1llI1i]]
Ct NC NC NC Bt
TLlF/991 B-2
0,
TL/F/991B-1
Pin Names
Am, B n, Cn, On
On
Description
Inputs
Outputs
II
4-31
CI
N
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee>
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
-0.5Vto to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (ICC or IGNO)
±50mA
Storage Temperature (TSTG)
2.0Vto 6.0V
4.5Vt05.5V
Input Voltage (VI)
OVtoVee
Output Voltage (Va)
OVtoVee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5VtoVee + 0.5V
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
Supply Voltage (Vee>
'AC
'ACT
- 65'C to + 150'C
-40'Cto +85'C
- 55'C to + 125'C
Minimum Input'Edge Rate (av/at)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V. 4.5V. 5.5V
125 mV/ns
Minimum Input Edge Rate (aV/at)
•ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V. 5.5V
125 mVins
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specnications should be met, without
exception, to ensure that the system design is reliable over its power supply.
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = O.W
or Vee - O.W
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.W
or Vee - O.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0,1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±O.1
±1.0
±1.0
/LA
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-32
lOUT = - 50 /LA
'VIN = VIL orVIH
-12mA
-24mA
10H
-24mA
lOUT = 50/LA
·VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee.GND
N
C
DC Characteristics for' AC Family Devices (Continued)
74AC
Symbol
Vcc
(V)
Parameter
TA
= +25'C
54AC
74AC
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
tMinimum Dynamic
Output Current
IOLD
IOHD
Maximum Quiescent
Supply Current
lee
Units
Conditions
Guaranteed Limits
= 1.65V Max
= 3.85V Min
5.5
50
75
rnA
VOLD
5.5
-50
-75
rnA
VOHD
80.0
40.0
p.A
VIN = Vee
orGND
5.5
4.0
·AII outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 rns, one output loaded at a time.
Note
:IIN and ICC @ 3.0V are guaranteed to be less than
Icc for S4AC @ 2S'C is identical to 74AC @ 2S·C.
or equal to the respective limit
AC Electrical Characteristics:
Symbol
Vcc'
(V)
Parameter
@
S.SV Vee.
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
3.3
5.0
2.0
1.5
6.0
5.0
8.5
7.0
1.0
1.0
11.0
8.5
1.5
1.0
10.0
8.0
ns
2-3,4
tpHL
Propagation Delay
3.3
5.0
1.5
1.5
5.0
4.0
7.0
6.0
1.0
1.0
10.5
7.0
1.0
1.0
9.0
7.0
ns
2-3,4
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range S.O is S.OV ± o.sv
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
CPD
Power Dissipation
Capacitance
40.0
pF
= 5.0V
Vee = 5.0V
Vee
•
4-33
N
.---------------------------------------------------------------------~
C')
~National
~ Semiconductor
54AC/74AC32 • 54ACT /7 4ACT32
Quad 2-lnput OR Gate
General Description
Features
The 'ACI'ACT32 contains four, 2-input OR gates.
The information for the ACT32 is Preliminary
information only.
• Outputs source/sink 24 rnA
• 'ACT32 has TTL-compatible inputs
• Standard Military Drawing (SMD)
- 'AC32: 5962-87614
Ordering Code: See Section 8
Connection Diagrams
Logic Symbol
~1
Ao
°0
Bo
A,
0,
B,
A2
°2
B2
Pin Assignment
for LCC
B, NC A, NC 00
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIiEC
Ao
80
00
Vee
A2
82
A,
B,
0,
°2
A3
83
03
GND
A3
OO(I][I)[[)m
0,00
GND [QJ
NC Ii]
[IlBo
[IJAo
[TINC
°3 [j]
83 jj]J
[j]JA2
~Vcc
°3
B3
TL/F/9919-3
TLlF/9919-1
1HI[§]1i]J1i1l1i]J
A3 NC 02 NC B2
TL/F/9919-2
Pin Names
Description
An, Sn
On
Inputs
Outputs
4-34
Absolute Maximum Rating (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee)
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (loKI
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
DC Output Source
or Sink Current (10)
DC Vee or Ground Current
per Output Pin (Icc or IGND)
Storage Temperature (T8TG)
Junction Temperature (TJ)
CDIP
PDIP
Recommended Operating
Conditions
Supply Voltage (Vecl
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
-20mA
+20mA
2.0Vt06.0V
4.5Vt05.5V
OV to Vee
OVtoVee
Operating Temperature (TA>
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (A VI At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V. 4.5V. 5.5V
Minimum Input Edge Rate (AVlAt)
•ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V. 5.5V
-0.5V to Vee + 0.5V
-20mA
+20mA
-0.5Vto to Vee + 0.5V
±50mA
±50mA
- 65'C to + 150'C
-40'Cto +85'C
-55'Cto +125'C
125 mV/ns
125 mV/ns
175'C
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design is reliable over its power supply,
temperature. and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'Cto +85'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - O.W
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.W
or Vee - O.W
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
p.A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
4-35
lOUT = -50pA
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50 p.A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee.GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'Cto +85'C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Units
Conditions
VOLD = 1.65V Max
Guaranteed Limits
5.5
50
75
mA
5.5
-50
-75
mA
VOHD = 3.B5V Min
/LA
VIN = Vcc
orGND
Maximum Quiescent
5.5
4.0
BO.O
Supply Current
'All outputs loaded; thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms. one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ S.SV Vcc.
Icc for S4AC @ 2S'C Is identical to 74AC @ 2S'C.
Icc
40.0
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +25'C
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
orVcc - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
O.B
O.B
O.B
O.B
V
VOUT = O.W
orVcc - O.W
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.B6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
/LA
1.6
1.5
mA
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.B5V Min
BO.O
40.0
/LA
VIN = Vcc
orGND
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
0.001
0.001
Units
Conditions
Guaranteed Limits
0.6
Maximum Quiescent
5.5
4.0
Supply Current
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for S4ACT @ 25'C is idenUcal to 74ACT @ 25'C.
Icc
4·36
lOUT = - 50 /LA
'VIN = VIL or VIH
-24mA
-24mA
IOH
lOUT = 50/LA
'VIN = VIL or VIH
24mA
IOL
24mA
VI = Vcc,GND
VI = Vcc - 2.W
AC Electrical Characteristics:
Symbol
Vec'
(V)
Parameter
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
3.3
5.0
1.5
1.5
7.0
5.5
9.0
7.5
1.0
1.0
12.0
9.0
1.5
1.0
10.0
8.5
ns
2-3,4
tpHL
Propagation Delay
3.3
5.0
1.5
1.5
7.0'
5.0
8.5
7.0
1.0
1.0
11.5
8.5
1.0
1.0
9.0
7.5
ns
2-3,4
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5,0 Is 5,OV ±0,5V
AC Electrical Characteristics:
Symbol
Vec'
Parameter
(V)
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to + 85'C
CL = 50pF
Min
Min
Min
Typ
Max
Max
Max
tpLH
Propagation Delay
5.0
1.0
6.5
9.0
1.0
10.0
ns
2-3,4
tpHL
Propagation Delay
5.0
1.0
6.5
9.0
1.0
10.0
ns
2-3,4
'Voltage Range 5.0 is 5.0V ±0.3V
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
CPO
Power Dissipation
Capacitance
20.0
pF
Conditions
Vee
Vee
= 5.0V
= 5.0V
II
4-37
....~ r-~------------------------------------------------------------------,
~National
~ Semiconductor
54AC/74AC74. 54ACT/74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The 'AC/'ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (a, a) outputs. Information at the input is transferred to the outputs on
the positive edge of the clock pulse. Clock triggering occurs
at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After
the Clock Pulse input threshold voltage has been passed,
the Data input is locked out and information present will not
be transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets to HIGH level
LOW input to CD (Clear) sets to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both
HIGH
a
a
a and a
Features
• Output source/sink 24 mA
• 'ACT74 has TTL-compatible inputs
• Standard Military Drawing (SMD)
- 'AC74: 5962-88520
- 'ACT74: 5962-87525
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
C01 -"'"11-----,
01
CPl
SOl
01
01
TL/F/9920-1
TL/F/9920-2
GND
IEEEIIEC
TlIF/9920-4
Pin Assignment for LCC
01 NC Sol NC CP1
lID [1][§] [[1[1]
rn 0 1
01 III "W---GNO Ii])
NCff]
dboillflll'o,
DONC
021i11
TL/F/9920-3
Pin Names
Description
01,02
CP1, CP2
CD1,CD2
SD1,SD2
01, '01, 02, '02
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
III COl
@I Vee
~C02
02M1
IGlliIDli]IllZIlI§I
Il:!
SD2 NC CP2 NC
TlIF/9920-5
4-38
, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , "-J
""
Truth Table (Each Half)
Inputs
Outputs
So
CD
CP
0
Q
L
H
L
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
.../
.../
L
H
L
H
L
H
H
L
L
H
H
L
H
X
00
00
Q
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
...-r = LOW-to-HIGH Clock Transition
00(00) = Previous 0(0) before LOW-to-HIGH Transition of Clock
Logic Diagram
SD--------------------------------~---------------------,
IO-.....- - Q
D
Cp--------T-----------------------~~~~
10-4--0
CD----------------------------------~--------------------~
TL/F 19920-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-39
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee!
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
±50mA
Storage Temperature (TSTG)
2.0Vto6.0V
4.5Vto5.5V
Input Voltage (VI)
OV to Vcc
Output Voltage (Vo)
OV to Vcc
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5VtoVee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage (Vee!
'AC
'ACT
-65'Cto + 150'C
- 40'C to + 85'C
-55'Cto + 125'C
Minimum Input Edge Rate (AV / At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (AV/At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125mV/ns
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Nole 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply.
temperature. and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
- 55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-40
lOUT = - 50 /LA
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50/LA
'VIN = VIL or VIH
12mA
24mA
IOL
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
74AC
Symbol
Parameter
Vee
(V)
TA
=
+25'C
Typ
IOLD
IOHD
Icc
·'Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
54AC
74AC
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Units
Conditions
Guaranteed Limits
5.5
50
75
rnA
5.5
-50
-75
rnA
= 1.65V Max
VOHD = 3.B5V Min
BO.O
40.0
iJ-A
VIN = Vcc
orGND
5.5
4.0
VOLD
"'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit
Icc for S4AC @ 2S'C is identical to 74AC @ 2S'C.
@
S.SV Vcc.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
t.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - O.lV
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
O.B
O.B
O.B
O.B
V
VOUT = 0.1V
orVcc - O.lV
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.B6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
iJ- A
1.6
1.5
rnA
Symbol
TA
=
+25'C
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.001
0.001
0.6
lOUT
=-
'VIN
=
VIL or VIH
-24 rnA
-24 rnA
lOUT
=
50 iJ-A
'VIN
=
VIL or VIH
24 rnA
24 rnA
IOH
IOL
50 iJ-A
VI
=
Vcc,GND
VI
=
Vcc - 2.1V
= 1.65V Max
= 3.B5V Min
5.5
50
75
rnA
VOLD
5.5
-50
-75
rnA
VOHD
BO.O
40.0
iJ-A
VIN = Vcc
orGND
5.5
4.0
"'All outputs loaded; thresholds on input associated with output under test.
@
Conditions
Guaranteed Limits
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for S4ACT
Units
2S'C is identical to 74ACT
@
2S'C.
4-41
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL=50pF
Min
Min
Units
Fig.
No.
Min
Typ
fmax
Maximum Clock
Frequency
3.3
5.0
100
140
125
160
tpLH
Propagation Delay
COn or SOn to an or On
3.3
5.0
3.5
2.5
8.0
6.0
12.0
9.0
1.0
1.0
13.0
9.5
2.5
2.0
13.0
10.0
ns
2-3,4
tpHL
Propagation Delay
COn or SOn to an or On
3.3
5.0
4.0
3.0
10.5
8.0
12.0
9.5
1.0
1.0
14.0
10.5
3.5
2.5
13.5
10.5
ns
2-3,4
tpLH
Propagation Delay
CP n to an or On
3.3
5.0
4.5
3.5
8.0
6.0
13.5
10.0
1.0
1.0
17.5
12.0
4.0
3.0
16.0
10.5
ns
2-3,4
Propagation Delay
CP n to an or On
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range S.O is S.OV i O.SV
3.3
5.0
3.5
2.5
8.0
6.0
14.0
10.0
1.0
1.0
13.5
10.0
3.5
2.5
14.5
10.5
ns
2-3,4
tpHL
AC Operating Requirements:
Symbol
Parameter
Vee'
(V)
Max
Max
70
95
Max
95
125
MHz
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
t.
Set·up Time, HIGH or LOW
Dnto CP n
3.3
5.0
1.5
1.0
4.0
3.0
5.0
4.0
4.5
3.0
ns
2-7
th
Hold Time, HIGH or LOW
Dn toCPn
3.3
5.0
-2.0
-1.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
2-7
tw
CPn or COn or SOn
Pulse Width
3.3
5.0
3.0
2.5
5.5
4.5
8.0
5.5
7.0
5.0
ns
2-3
3.3
5.0
-2.5
-2.0
0
0
0.5
0.5
0
0
ns
2-3,7
Recovery Time
COn or SOn to CP
'Voltage Range 3.3 Is 3.3V iO.3V
Voltage Range S.O is S.OV iO.SV
tree
4-42
AC Electrical Characteristics:
Symbol
Vee·
(V)
Parameter
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2SoC
CL = SOpF
TA = -SsoC
to + 12SoC
CL = SOpF
TA = -40°C
to +8SoC
CL = SOpF
Min
Min
Min
Typ
Max
Max
Units
Fig.
No.
Max
fmax
Maximum Clock
Frequency
5.0
145
210
tpLH
Propagation Delay
COn or SOn to On or an
5.0
3.0
5.5
9.5
1.0
11.5
2.5
10.5
ns
2-3,4
tpHL
Propagation Delay
COn or SOn to On or an
5.0
3.0
6.0
10.0
1.0
12.5
3.0
11.5
ns
2-3,4
tpLH
Propagation Delay
CPn to On or an
5.0
4.0
7.5
11.0
1.0
14.0
4.0
13.0.
ns
2-3,4
5.0
3.5
6.0
10.0
1.0
12.0
3.0
11.5
ns
2-3,4
Propagation Delay
CPn to On orOn
'Voltage Range 5.0 is 5.0V ± 0.5V
tpHL
AC Operating Requirements:
Symbol
Parameter
Vee·
(V)
85
125
MHz
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2SoC
CL = SOpF
TA = -SsoC
to + 12SoC
CL = SOpF
TA = -40"C
to +8SoC
CL = SOpF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Set-up Time, HIGH or LOW
Dnto CPn
5.0
1.0
3.0
4.0
3.5
ns
2-7
th
Hold Time, HIGH or LOW
Dnto CPn
5.0
-0.5
1.0
1.0
1.0
ns
2-7
Iw
CPn or COn or SOn
Pulse Width
5.0
3.0
5.0
7.0
6.0
ns
2-3
5.0
-2.5
0
0.5
0
ns
2-3,7
Recovery Time
COn or SOn to CP
'Voltage Range 5.0 is 5.0V ± O.5V
tree
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
CPO
Power Dissipation
Capacitance
35.0
pF
4-43
Conditions
Vee
Vee
=
=
5.0V
5.0V
~National
~ Semiconductor
54AC/74AC86
Quad
2~lnput
Exclusive-OR Gate
General Description
Features
The 'AC8S contains four, 2-input exclusive-OR gates.
• Outputs source/sink 24 mA
• Standard Military Drawing (SMD)
- 'AC8S: 5962-89550
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEEIIEC
Pin Assignment
for DIP, Flatpak and SOIC
Pin Assignment
forLCC
0i!:1
Ao
00
Bo
Al
Bl
Bl NC Al NC
°1
Ao
Vee
Bo
00
B2
A2
B2
°2
Al
03
°1
GND
A2
°2
A3
Bl
A3
B3
00
{!Hz] 00 [ID ill
B3
01 II!
GND [QJ
NC [j]
[IlBo
IIIAo
[I]NC
°3 1il1
B3 1i1l
IrIDA2
~Vcc
°3
TL/F/9909-3
TL/F/9909-2
1Bl1iID1iE1iiI!iID
A3 NC 02 NC B2
TL/F/9909-1
Pin Names
Description
Ao-Aa
Bo-Ba
Oo-Oa
Inputs
Inputs
Outputs
4-44
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
Supply Voltage (Vee>
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (AV/At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (AV/At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
-0.5Vto +7.0V
DC Input Diode Current (11K)
VI = 0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
-20mA
+20mA
-0.5VtoVee +0.5V
DC Output Diode Current (10K)
Va = -0.5V
-20mA
+20mA
-0.5V to Vee +0.5V
DC Output Source or Sink Current (10)
±50mA
Va = Vee +0.5V
DC Output Voltage (Va)
DC Vee or Ground Current
Per Output Pin (Icc or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
±50mA
-65'Cto + 150'C
CDIP
PDIP
2.0Vto6.0V
4.5Vto 5.5V
OVtoVee
OVtoVee
-40'Cto +85'C
- 55'C to + 125'C
125 mV/ns
125 mV/ns
175'C
140'C
Nate 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception. to ensure that the system design is reliable over its power supply.
temperature. and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = 25'C
TA=
-55'C to + 125'C
TA=
-40'Cto +85'C
Typ
VIH
VIL
VOH
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
orVcc - O.lV
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.lV
orVcc - O.lV
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
3.0
4.5
5.5
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 20 ms, one output loaded at a time.
4-45
lOUT
V
=
-50,...A
'VIN = VIL or VIH
-12mA
-24mA
IOH
-24mA
lOUT
=
50,...A
·VIN
=
VIL or VIH
12mA
24mA
24mA
IOL
CD
CD
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
S4AC
74AC
TA = 2SoC
TA=
-SSOC to + 12SOC
TA=
- 40"C to + SSOC
Typ
liN
Maximum Input
Leakage Current
loz
Maximum TRI-STATE!!>
IOLD
tMinimum Dynamic
Output Current
IOHD
±1.0
±1.0
/LA
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
40
/LA
VIN = Vee
orGND
Maximum Quiescent
5.5
4.0
80
Supply Current
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 20 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
lee for 54AC @ 25'C Is identicsl to 74AC @ 25'C.
AC Electrical Characteristics:
See Section 2 for Waveforms
74AC
S4AC
74AC
TA = +2SoC
CL = SOpF
TA = -SsoC
to + 12SOC
CL = SOpF
TA = -40"C
to +SsoC
CL = SOpF
Units
Fig.
No.
12.5
9.5
ns
2·3,4
12.5
9.0
ns
2-3,4
Parameter
Vcc'
(V)
Min
Typ
Max
Min
Max
Min
Max
Propagation Delay
Inputs to Outputs
3.3
5.0
2.0
1.5
6.0
4.5
11.5
8.5
1.0
1.0
14.0
10.0
1.5
1.0
Propagation Delay
Inputs to Outputs
'Voltage Range 3.3V is 3.3V ± 0.3V
Voltage Range 5.0V is 5.0V ± 0.5V
3.3
5.0
2.0
1.5
6.5
4.5
11.5
8.5
1.0
1.0
14.0
10.0
1.5
1.0
tpHL
tpLH
Capacitance
Symbol
VI = Vcc,GND
VI (OE) = VIL, VIH
Vo = VCC,GND
ICC
Symbol
Conditions
Guaranteed Limits
±0.1
5.5
Units
Typ
Units
Conditions
CIN
Input Capacitance
Parameter
4.5
pF
Vee = 5.OV
Cpo
Power Dissipation Capacitance
35
pF
Vee = 5.OV
4-46
r------------------------------------------------------------------------,
CD
~National
~ Semiconductor
54AC/74AC109 • 54ACT174ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The 'ACI'ACT109 consists of two high-speed completely
independent transition clocked JK flip-flops. The clocking
operation is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop
(refer to 'AC/' ACT7 4 data sheet) by connecting the J and K
inputs together.
Asynchronous Inputs:
LOW input to So (Set) sets 0 to HIGH level
LOW input to CD (Clear) sets 0 to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and So makes both 0 and
HIGH
0
Features
• Outputs source/sink 24 mA
• 'ACT109 has TTL-compatible inputs
• Standard Military Drawing (SMD)
- 'AC109: 5962-89551
- 'ACT109: 5962-88534
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
TL/F/9923-1
TLlF/9923-2
IEEE/IEC
S01
J1
TL/F/9923-3
°1
CP 1
Pin Assignment
forlCC
01
K1
C01
01 SD1 NC CP1 K1
rn:JlIIl]][IDill
S02
Jz
°2
01 [I]
GND IlQ]
NC (j]
CPz
O2
K2
CO2
TL/F 19923-7
Pin Names
Description
J1, J2, K1, K2
CP1,CP2
C01, C02
S01,S02
0 1, 0 2, 0 1, 0 2
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
~
Q
[I)J 1
rn C01
[J]NC
@IVcc
Ii]] CO2
02 1rn
02 Ii]
1iJl1i]J1l]J1lZI1l]J
SD2 CP2NC
~ ~
TL/F/9923-4
4-47
Truth Table
(each half)
Inputs
Outputs
So
Co
CP
J
K
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
.../
.../
.../
.../
L
L
H
L
H
L
L
H
H
X
X
H
L
L
H
H
H
L
H
Toggle
Qo
00
H
L
Qo
00
Q
H = HIGH Voltage Level
L = LOW Voltage Level
...r = LOW-to-HIGH Transition
X = Immaterial
00(00) = Previous 00(00) before LOW-to-HIG'H Transition of Clock
Logic Diagram
(one half shown)
SD~~------------------------------------'-------------------~
cp--------~------~----------------------~~~~
» ....- - 0
CD--~------------------------------------~------------------~
TL/F/9923-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-48
......
Absolute Maximum Rating
Supply Voltage (Vecl
DC Input Diode Current (1,K)
V, = -0.5V
V, = Vee + 0.5V
DC Input Voltage (V,)
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
-20mA
+20mA
2.0Vto6.0V
4.5Vt05.5V
OVto Vee
OVtoVee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (A V1.6.1)
'AC Devices
Y,N from 30% to 70% of Vee
Vee @3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (AV/At)
'ACT Devices
Y,N from 0.8V to 2.0V
Vee@4.5V.5.5V
-0.5V to Vee + 0.5V
-20mA
+20mA
-0.5V to to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
PDIP
CD
Supply Voltage (Vecl
'AC
'ACT
Input Voltage (V,)
Output Voltage (Vo)
-0.5Vto +7.0V
DC Output Source
or Sink Current (10)
o
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Offlce/Dlstrlbut.'lrs for availability and specifications.
±50mA
-65'Cto +150'C
-40'Cto + 85'C
- 55'C to + 125'C
125mV/ns
125 mV/ns
175'C
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom~
mend operation of FACfTM cirCUIts outside databook speCifications.
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
= +2S'C
Typ
V,H
V,L
VOH
liN
74AC
TA =
-SS'C to + 12S'C
TA =
-40'Cto +8S'C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - O.W
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
VOL
S4AC
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
p.A
•All outputs loaded; thresholds on input associated with output under test.
4-49
= -50 p.A
'V,N
= V,L or V,H
10H
-12mA
-24mA
-24mA
lOUT = 50 p.A
3.0
4.5
5.5
tMaximum test duration 2.0 ms, one output loaded at a time.
lOUT
'V,N = V,L or V,H
12mA
24mA
10L
24mA
V,
= Vee,GND
•
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
- 55'C to + 125'C
TA =
-40'Cto +85'C
Typ
IOLD
IOHO
Icc
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
YOLO = 1.65V Max
5.5
-50
-75
mA
VOHO = 3.B5V Min
BO.O
40.0
/LA
VIN = Vee
orGND
5.5
4.0
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ S.SV Vcc.
Icc for S4AC @ 2S'C Is Identical to 74AC @ 2S·C.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55'C to + 125'C
TA =
- 40'C to + 85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
orVec - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
O.B
O.B
O.B
O.B
V
VOUT = O.W
orVec - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
/LA
1.6
1.5
mA
Symbol
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHO
0.001
0.001
Conditions
Guaranteed Limits
Typ
4.5
5.5
Units
0.6
lOUT = - 50 /LA
'VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50/LA
'VIN = VIL or VIH
24mA
IOL
24mA
VI = Vec,GND
VI = Vec - 2.W
5.5
50
75
mA
YOLO = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
80.0
40.0
/LA
VIN = Vee
orGND
Maximum Quiescent
ICC
5.5
4.0
Supply Current
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for S4ACT @ 2S'C is identical to 74ACT @ 2S·C.
4-50
....
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
o
74AC
S4AC
74AC
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Min
Typ
f max
Maximum Clock
Frequency
3.3
5.0
125
150
150
175
tpLH
Propagation Delay
CPn to an or an
3.3
5.0
4.0
2.5
6.0
Propagation Delay
CPn to an or an
3.3
5.0
3.0
2.0
Propagation Delay
3.3
5.0
3.0
2.5
3.3
5.0
3.0
2.0
tpHL
tpLH
COn or SOn to an or an
tpHL
Propagation Delay
COn or SOn to an or an
'Voltage Range 3.3 Is 3.3V ± 0.3V
Voltage Range 5.0 Is 5.0V ± 0.5V
AC Operating Requirements:
Symbol
ts
th
Min
B.O
Fig.
No.
Max
MHz
1.0
1.0
17.5
12.0
3.5
2.0
16.0
10.5
ns
2·3,4
14.0
10.0
1.0
1.0
13.5
10.0
3.0
1.5
14.5
10.5
ns
2·3,4
6.0
12.0
9.0
1.0
1.0
13.0
9.5
2.5
2.0
13.0
10.0
ns
2·3,4
10.0
7.5
12.0
9.5
1.0
1.0
14.0
10.5
3.0
2.0
13.5
10.5
ns
2·3,4
B.O
6.0
B.O
See Section 2 for waveforms
74AC
S4AC
74AC
TA = +2S'C
CL=SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Typ
Guaranteed Minimum
3.5
2.0
6.5
4.5
8.0
5.5
Hold Time, HIGH or LOW
3.3
5.0
-1.5
-0.5
0
0.5
3.3
5.0
2.0
2.0
4.0
3.5
3.3
5.0
-2.5
-1.5
0
0
Recovery Time
Units
13.5
10.0
3.3
5.0
COn or SOn to CPn
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
Min
100
125
Setup Time, HIGH or LOW
I n or Kn to CPn
Pulse Width
Max
65
95
Vee'
(V)
COn orSOn
tree
Max
Parameter
I n or Kn to CP n
tw
CO
See Section 2 for waveforms
4·51
Units
Fig.
No.
7.5
5.0
ns
2·7
0
0.5
0
0.5
ns
2·7
B.O
5.5
4.5
3.5
ns
2·3
0.5
0.5
0
0
ns
2·3,7
AC Electrical Characteristics:
Symbol
See Section 2 for waveforms
Vee'
(V)
Parameter
74ACT
54ACT
74ACT
TA = +25·C
CL = 50pF
TA = -55·C
to + 125·C
CL = 50pF
TA = -40·C
to +85·C
CL = 50pF
Max
Min
Max
Typ
5.0
145
210
Propagation Delay
CPn to an or 'On
5.0
4.0
7.0
11.0
1.0
14.0
3.5
13.0
ns
2-3,4
tpHL
Propagation Delay
CP n to an or 'On
5.0
3.0
6.0
10.0
1.0
12.0
2.5
11.5
ns
2-3,4
tpLH
Propagation Delay
COn or S'On to an or 'On
5.0
2.5
5.5
9.5
1.0
11.5
2.0
10.5
ns
2-3,4
5.0
2.5
6.0
10.0
1.0
12.5
2.0
11.5
ns
2-3,4
Maximum Clock
Frequency
tpLH
Propagation Delay
COn or S'On to an or 'On
'Voltage Range 5.0 Is 5.0V ± 0.5V
tpHL
AC Operating Requirements:
Symbol
Parameter
Setup Time, HIGH or LOW
I n or Kn to CPn
ts
Hold Time, HIGH or LOW
th
I n or Kn to CP n
Pulse Width
tw
CPn or COn or SOn
Recovery Time
tree
COn or SOn to CPn
'Voltage Range 5.0 is 5.0V ± 0.5V
Min
Fig.
No.
Min
fmax
Max
Units
85
See Section 2 for waveforms
Vee'
(V)
74ACT
54ACT
74ACT
TA = +25·C
CL = 50pF
TA = -55·C
to + 125·C
CL = 50pF
TA = -40·C
to +85·C
CL = 50pF
Typ
Guaranteed Minimum
Units
Fig.
No.
5.0
0.5
2.0
2.5
2.5
ns
2-7
5.0
0
2.0
2.0
2.0
ns
2-7
5.0
3.0
5.0
7.0
6.0
ns
2-3
5.0
-2.5
0
0.5
0
ns
2-3,7
Capacitance
Symbol
MHz
125
Parameter
Typ
Units
CIN
Input CapaCitance
4.5
pF
CPO
Power Dissipation
Capacitance
pF
35.0
4-52
Conditions
Vee
Vee
=
=
5.0V
5.0V
r---------------------------------------------------------------------~
~
I\)
c.n
~National
~ Semiconductor
54AC/74AC125 • 54ACT/74ACT125
Quad Buffer with TRI-STATE® Outputs
General Description
Features
The 'AC/'ACT125 contains four independent non-inverting
buffers with TRI-STATE outputs.
- Outputs source/sink 24 mA
• 'ACT125 has TTL-compatible outputs
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
IEEE/IEC
B, NC
1>1
Bo
Pin Assignment
for LCC and PCC
Ao
AD
Bo
A2
°1
00
B2
A,
B,
°2
A3
0,
B3
GND
°3
Bl
Al
B2
°2
A2
B3
°3
A3
TLlF/l0692-1
TL/F/l0692-2
A,
NC 00
lID IIJIID rn[I]
Vee
°0
o,iID
mBa
GND Ii]]
rn AD
NC IIil
03 Ii]
ITlNC
B3 1i]
IJ]JA2
~Vce
1l]1l]J[j]J!i][j]J
A3 NCO:!NCB2
TLlF/l0692-3
Pin Names
Description
Inputs
Outputs
Function Table
Inputs
Output
An
Bn
On
L
L
H
L
H
L
H
Z
X
H =
L =
Z =
X =
HIGH Voltage Level
LOW Voltage Level
HIGH Impedance
Immaterial
•
4-53
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Ved
DC Input Diode Current (IK)
-20mA
VI = -0.5V
VI = Vee + 0.5V
+20mA
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Va = -0.5V
-20mA
Va = Vee + 0.5V
+20mA
DC Output Voltage (Va)
-0.5VtoVee + 0.5V
DC Output Source
or Sink Current (IO)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGNO)
Storage Temperature (TSTG)
-65°C to + 150"C
Junction Temperature (TJ)
CDIP
175°C
PDIP
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception. to ensure that the system design Is reliable over Its power supply.
temperature. and output/input loading vanables. National does not recom·
mend operation of FACTTM circuits outside databook specHications.
Recommended Operating
Conditions
Supply Voltage (Vee)
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (~V I ~t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (~VI~t)
'ACT Devices
VIN from 0.8V to 2.OV
Vee @ 4.5V, 5.5V
2.OVto 6.0V
4.5Vt05.5V
OVtoVee
OVtoVee
-40"Cto +85°C
- 55°C to + 125°C
125mVlns
125mV/ns
DC Characteristics for' AC Family Devices
Symbol
74AC
S4AC
74AC
TA = +2SoC
TA=
- SsoC to + 12SoC
TA=
-40"Cto +8SOC
Parameter
Vee
(V)
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
orVee - 0.1V
VOH
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
±1.0
±1.0
p.A
3.0
4.5
5.5
VOL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
Conditions
Guaranteed Limits
Typ
VIH
Units
Maximum Input
±0.1
5.5
Leakage Current
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
liN
4·54
lOUT = - 50 p.A
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50p.A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
....
I\)
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vcc
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + 125'C
TA=
- 4D'C to + 85'C
Typ
loz
IOLD
IOHD
Units
Conditions
Guaranteed Limits
Maximum TRI-STATE
Current
5.5
tMinimum Dynamic
Output Current
5.5
50
5.5
-50
160.0
80.0
Maximum Quiescent
Supply Current
Icc
U1
±0.5
5.5
±10.0
8.0
,...A
VI (OE) = VIL, VIH
VI = Vee, VGND
Vo = Vee,GND
75
mA
VOLD = 1.65V Max
-75
mA
VOHD = 3.85V Min
,...A
VIN = Vee
orGND
±5.0
"'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc
@
Icc for 54AC
3.0V are guaranteed to be less than or equal to the respective limit
25°C is identical to 74AC
@
@
@
5.5V VCC.
25°C.
DC Characteristics for' ACT Family Devices
74ACT
Symbol
Parameter
VCC
(V)
54ACT
TA = +25'C
74ACT
TA=
TA =
Units
-55'C to + 125'C -40'Cto + 85'C
Typ
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
4.5
5.5
3.86
4.86
3.70
4.70
3.76
4.76
V
4.5 0.001
5.5 0.001
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
VOL
Maximum Low Level
Output Voltage
lOUT = -50,...A
'VIN = VIL or VIH
-24mA
-24mA
IOH
lOUT = 50,...A
'VIN = VIL or VIH
24mA
IOL
24mA
liN
Maximum Input Leakage Current 5.5
±0.1
±1.0
±1.0
,...A
VI = Vee,GND
loz
Maximum TAl-STATE
Current
±0.5
±10.0
±5.0
,...A
VI = VIL, VIH
Vo = Vee,GND
leeT
Maximum leellnput
5.5
1.6
1.5
mA
VI = Vee - 2.1Vt
fOLD
tMinimum Dynamic
Output Current
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
,...A
VIN = Vee
orGND
fOHD
Icc
5.5
Maximum Quiescent
Supply Current
0.6
5.5
8.0
• All outputs loaded; thresholds on input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
;May be measured per the JEDEC Alternate Method.
Note: Icc for 54ACT
@
25°C is identical to 74ACT
@
25°C.
4-55
AC Electrical Characteristics:
Symbol
Vee·
(V)
Parameter
See Section 2 for Waveforms
74AC
S4AC
74AC
TA = +25"C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Units
Fig.
No.
Min
Typ
Max
Min
Max
tpLH
Propagation Delay
Data to Output
3.3
5.0
1.0
1.0
6.5
5.5
9.0
7.0
1.0
1.0
10.0
7.5
ns
2-3,4
tpHL
Propagation Delay
Data to Output
3.3
5.0
1.0
1.0
6.5
5.0
9.0
7.0
1.0
1.0
10.0
7.5
ns
2-3,4
tpZH
Output Enable Time
3.3
5.0
1.0
1.0
6.0
5.0
10.5
7.0
1.0
1.0
11.0
8.0
ns
2-5
tpZL
Output Enable Time
3.3
5.0
1.0
1.0
7.5
5.5
10.0
8.0
1.0
1.0
11.0
8.5
ns
2-6
tpHZ
Output Disable Time
3.3
5.0
1.0
1.0
7.5
6.5
10.0
9.0
1.0
1.0
10.5
9.5
ns
2-5
tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
7.5
6.5
10.5
9.0
1.0
1.0
11.5
9.5
ns
2-6
Units
Fig.
No.
Min
Max
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SO pF
TA = -40'C
to +8S'C
CL = SOpF
Min
Max
9.0
1.0
10.0
ns
2-3,4
7.0
9.0
1.0
10.0
ns
2-3,4
1.0
6.0
8.5
1.0
9.5
ns
2-5
5.0
1.0
7.0
9.5
1.0
10.5
ns
2-6
5.0
1.0
7.0
9.5
1.0
10.5
ns
2-5
5.0
1.0
7.5
10.0
1.0
10.5
ns
2-6
Min
Typ
Max
S.O
1.0
6.5
Propagation Delay
Data to Output
5.0
1.0
tPZH
Output Enable Time
5.0
tPZL
Output Enable Time
tpHZ
Output Disable Time
tpLZ
Output Disable Time
tpLH
Propagation Delay
Data to Output
tpHL
Min
Max
'Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
Parameter
AC/ACT
Units
Conditions
Typ
CIN
Input Capacitance
CPD
Power Dissipation
Capacitance
4.5
pF
45.0
pF
4·56
Vee
Vee
= 5.0V
= 5.0V
,------------------------------------------------------------------------,
~
Co)
C»
~National
~ Semiconductor
54AC/74AC138. 54ACT/74ACT138
1-of-8 DecoderIDemultiplexer
General Description
Features
The 'ACI'ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar
memory chip select address decoding. The multiple input
enables allow parallel expansion to a 1-of-24 decoder using
just three 'ACI' ACT138 devices or a 1-of-32 decoder using
four' ACI' ACT138 devices and one inverter.
•
•
•
•
•
•
Demultiplexing capability
Multiple input enable for easy expansion
Active LOW mutually exclusive outputs
Outputs source/sink 24 mA
'ACT138 has TTL-compatible inputs
Standard Military Drawing (SMD)
- 'AC138: 5962-87622
- 'ACT138: 5962-87554
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
Pin Assignment
forlCC
Pin Assignment
for DIP, Flatpak and SOIC
E3
[3
TLIF19925-1
IEEEIIEC
BIN/OCT
Ao
Al
A2
2
4
E3
£1
£2
EN
00
01
O2
03
04
AO
Al
A2
£1
1
16
Vee
2
15
00
3
14
4
13
Ez
5
12
E3
07
6
11
7
10
GND
8
9
°1
°2
°3
°4
as
as
Ez NC
£1 ~
[ID!Il[ID[ID!II
07 [ID
[IJA I
GND [QJ
NC [j)
[IlAo
[j]NC
@lVee
Os Ii]
°slill
\.. c..,................................
lim 00
iBlli]]Ji])lIZIJi])
04 03 NC 02 01
TLIFI9925-2
TUF19925-3
°s
OS
°7
TLIF19925-7
Pin Names
Ao-A2
El-E2
Es
0 0-0 7
91
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
4-57
Functional Description
The 'AC/'ACT138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (Ao, Al, A2) and, when
enabled, provides eight mutually exclusive active-LOW outputs (00-07), The 'AC/'ACT138 features three Enable inputs, two active-LOW (El, E2) and one active-HIGH (E3)' All
outputs will be HIGH unless El and E2 are LOW and E3 is
HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines)
decoder with just four' AC/' ACT138 devices and one inverter (see Figure 1). The 'ACI'ACT138 can be used as an 8output demultiplexer by using one of the active LOW Enable
inputs as the data input and the other Enable inputs as
strobes. The Enable inputs which are not used must be permanenlly tied to their appropriate active-HIGH or activeLOW state.
Truth Table
Inputs
Outputs
E1
E2
E3
Ao
A1
A2
00
01
02
03
04
05
06
07
H
X
X
X
H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
TL/F/9925-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-58
Ao
AI
A2
'f04
"T\
15
A3
m
A4
c:
::u
:-"
m
)(
"g
~
tn
<0
I»
:I
U>
1
123
0'
:I
Ao
0'
AI
A2
~
...!i!'"
C
CD
n
0
a.
S·
IC
0 --------------------------------------------------------------------------------------------0
0
31
TLlF/992S-S
8&~
II
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (lee or IGNO)
±50mA
Storage Temperature (TSTG)
+ 150'C
- 65'C to
2.0Vto 6.0V
4.5Vt05.5V
Input Voltage (VI)
OVtoVee
Output Voltage (Vo)
OV to Vee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage (Vecl
'AC
'ACT
-40'Cto +B5'C
- 55'C to + 125'C
Minimum Input Edge Rate (tNll:.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (I:. V I I:.t)
'ACT Devices
VIN from O.BV to 2.0V
Vee @ 4.5V, 5.5V
125 mVl ns
Junction Temperature {TJ}
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system destgn is reliable over its power supply,
temporature. and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
- 55'C to + 12S'C
TA=
-40'Cto +85'C
Typ
VIH
VIL
VOH
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.B5
2.1
3.15
3.B5
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.B6
4.B6
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001 .
0.001
lOUT = - 50 p.A
·VIN = VILorVIH
-12mA
-24mA
10H
-24mA
lOUT = 50 p.A
...
liN
Maximum Input
Leakage Current
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
p.A
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
4-60
·VIN = Vil or VIH
12mA
24mA
10l
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
IOLD
IOHD
ICC
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
",A
VIN = VCC
orGND
5.5
8.0
-All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Nole: tiN and Icc @ 3.0V are guaranleed to be less than or equal to the respective limit @ 5.5V Vec.
ICC lor 54AC @ 25'C Is identical to 74AC @ 25'C.
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +25'C
TA =
- 55'C to + 125'C
TA=
-40'C to +85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
orVcc - 0.1V
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
",A
1.6
1.5
mA
VOH
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Iccllnput
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
ICC
Maximum Quiescent
Supply Current
0.001
0.001
0.6
lOUT = -50 ",A
'VIN = VIL or VIH
-24mA
-24mA
IOH
lOUT = 50 ",A
'VIN = VIL or VIH
24mA
IOL
24mA
VI = Vcc, GND
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
",A
VIN = Vcc
orGND
5.5
8.0
•All outputs loaded; thresholds on inpul associaled with oulpul under test.
tMaximum lesl duration 2.0 ms, one output loaded at a lime.
Note: ICC lor 54ACT @ 25'C is Identical to 74ACT @ 25'C.
4·61
II
AC Electrical Characteristics:
See Section 2 for Waveforms
74AC
S4AC
74AC
TA = +2SOC
CL = SOpF
TA = -SSOC
to + 12S'C
CL = SOpF
TA = -40"C
to +8SOC
CL = SOpF
Units
Fig.
No.
15.0
10.5
ns
2·3,4
1.5
1.5
14.0
10.5
ns
2-3,4
16.5
13.0
1.5
1.5
16.0
12.0
ns
2-3,4
1.0
1.0
15.5
12.0
1.5
1.5
15.0
10.5
ns
2·3,4
15.5
11.0
1.0
1.0
17.0
13.5
1.5
1.5
16.5
12.5
ns
2·3,4
13.0
8.0
1.0
1.0
15.0
11.0
1.5
1.0
14.0
9.5
ns
2·3,4
Units
Fig.
No.
Parameter
Vee'
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
An to On
3.3
5.0
1.5
1.5
8.5
6.5
13.0
9.5
1.0
1.0
16.0
12.0
1.5
1.5
tpHL
Propagation Delay
An to On
3.3
5.0
1.5
1.5
8.0
6.0
12.5
9.0
1.0
1.0
15.0
11.5
tpLH
Propagation Delay
E1orE2toOn
3.3
5.0
1.5
1.5
11.0
8.0
15.0
11.0
1.0
1.0
tpHL
Propagation Delay
E1orE2toOn
3.3
5.0
1.5
1.5
9.5
7.0
13.5
9.5
tpLH
Propagation Delay
E3 toOn
3.3
5.0
1.5
1.5
11.0
8.0
Propagation Delay
E3 toOn
'Voltage Range 3.3 Is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
3.3
5.0
1.5
1.5
8.5
6.0
Symbol
(V)
tpHL
AC Electrical Characteristics:
Symbol
Vee'
Parameter
(V)
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2SOC
CL = SOpF
TA = -SSOC
to + 12S'C
CL=SOpF
TA = -40"C
to +8S'C
CL = SOpF
Min
Typ
Max
Min
Max
Min
Max
5.0
1.5
7.0
10.5
1.0
12.5
1.5
11.5
ns
2·3,4
Propagation Delay
An to On
5.0
1.5
6.5
1.0
12.5
1.5
11.5
ns
2·3,4
tpLH
Propagation Delay
E1orE2toOn
5.0
2.5
8.0
11.5
1.0
13.5
2.0
12.5
ns
2·3,4
tpHL
Propagation Delay
E1 orE2to On
5.0
2.0
7.5
11.5
1.0
12.5
.2.0
12.5
ns
2·3,4
tpLH
Propagation Delay
E3 toOn
5.0
2.5
8.0
12.0
1.0
14.0
2.0
13.0
ns
2·3,4
5.0
2.0
6.5
10.5
1.0
12.0
1.5
11.5
ns
2-3,4
tpLH
Propagation Delay
An to On
tpHL
Propagation Delay
E3 toOn
'Voltage Range 5.0 Is 5.0V ± 0.5V
tpHL
10.5
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
60.0
pF
4·62
Vee = 5.0V
r----------------------------------------------------------------------------.-o
Co)
CD
~National
~ Semiconductor
54AC/74AC139. 54ACT/74ACT139
DuaI1-of-4 Decoder/Demultiplexer
General Description
Features
The 'AC/'ACT139 is a high-speed, duaI1-of-4 decoder/demultiplexer. The device has two independent decoders,
each accepting two inputs and providing four mutually-exclusive active-LOW outputs. Each decoder has an activeLOW Enable input which can be used as a data input for a
4-output demultiplexer. Each half of the 'AC/'ACT139 can
be used as a function generator providing all four minterms
of two variables.
• Multifunction capability
• Two completely independent 1-of-4 decoders
.. Active LOW mutually exclusive outputs
II Outputs source/sink 24 rnA
• 'ACT139 has TTL-compatible inputs
• Standard Military Drawing (SMD)
-'AC139: 5962-87623
-'ACT139: 5962-87553
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEEIIEC
Pin Assignment
for DIP, Flatpak and SOIC
°Oa
DECODER a
TliF/9926-B
16
°la
Ea
°2a
AOa
2
15
Eb
°3a
°Ob
Ala
3
14
°Oa
4
13
Aob
Alb
°lb
°la
5
12
°Ob
°2b
°2a
6
11
°lb
°3b
°3a
GND
7
10
°2b
8
9
TliF/9926-2
VCC
°3b
TliF/9926-3
DECODER b
Pin Assignment
forLCC
~OI. NC Oo.A1•
TliF/9926-1
Pin Names
lID mlID IIDm
Description
~~~~D~~:·
Address Inputs
Enable Inputs
Outputs
NC Ii]
[j]NC
03b~
~VCC
02bllll
IlIDEb
1Hi1i§l1i§]1iZI1i§]
Clb COb NC Alb .lob
TL/F/9926-4
4-63
•
... r---------------------------------------------------------------------------------,
Functional Description
Truth Table
en
C")
The 'AC/'ACT139 is a high-speed dual 1-01-4 decoder/demultiplexer. The device has two independent decoders,
each of which accepts two binary weighted inputs (Ao-Al)
and provides four mutually exclusive active-LOW outputs
(00-03). Each decoder has an active-LOW enable (E).
When E is HIGH all outputs are forced HIGH. The enable
can be used as the data input for a 4-output demultiplexer
application. Each half of the 'AC/'ACT139 generates all four
minterms of two variables. These four minterms are useful
in some applications, replacing multiple gate functions as
shown in Figure a, and thereby reducing the number of
packages required in a logic network.
~3=D-0o
Inputs
Outputs
E
Ao
Al
H
L
L
L
L
X
X
L
H
L
H
L
L
H
H
00
01
02
03
'H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Immaterial
~3D-~
AI
AI
~3D-ol
~3D-ol
AI
AI
A : 3 D - 02
AI
~3D-0'
~3D-03
~3D-~
AI
AI
A,
TL/F/9926-6
FIGURE a. Gate Functions (Each Half)
Logic Diagram
TLlF/9926-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-64
...
Co)
Absolute Maximum Rating
Supply Voltage (Vee)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Va)
Supply Voltage (Vee)
'AC
'ACT
Input Voltage (V,)
Output Voltage (Va)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (6. V/6.t)
'AC Devices
Y,N from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (6.V/6.t)
'ACT Devices
Y,N from O.BV to 2.0V
Vee @ 4.5V, 5.5V
-0.5Vto +7.0V
DC Input Diode Current (1,K)
V, = -0.5V
V, = Vee + 0.5V
DC Input Voltage (V,)
-20mA
+20mA
-0.5V to Vee + 0.5V
-20mA
+20mA
-0.5Vto to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
Storage Temperature (Tsm)
Junction Temperature (TJ)
CDIP
PDIP
CD
Recommended Operating
Conditions
(Note 1)
If Military/ Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
±50mA
- 65·C to + 150·C
2.0Vt06.0V
4.5Vto 5.5V
OVtoVee
OV to Vee
-40·C to + B5·C
-55·Cto + 125·C
125 mV/ns
125 mV/ns
175·C
140·C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
= +2S·C
S4AC
74AC
TA =
-SS·C to + 12S·C
TA=
-40·Cto +8S·C
Typ
V,H
V,L
VOH
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.B5
2.1
3.15
3.B5
2.1
3.15
3.B5
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.B6
4.B6
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
3.0
4.5
5.5
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4·65
lOUT
= -50".A
'V,N
= V,L or V,H
IOH
lOUT
V
-12mA
-24mA
-24mA
= 50".A
'V,N = V,L or V,H
12mA
24mA
IOL
24mA
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + 125'C
TA=
-40'C to +85'C
Typ
liN
Maximum Input
Leakage Current
IOLD
tMinimum Dynamic
Output Current
IOHD
Maximum Quiescent
Supply Current
Icc
Conditions
Guaranteed Limits
±0.1
5.5
Units
±1.0
±1.0
/LA
VI = Vcc,GND
5.5
50
75
mA
VOLO = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vcc
orGND
8.0
5.5
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc
@
Icc for S4AC
3.0V are guaranteed to be less than or equal to the respective limit
@
2S'C is identical to 74AC
@
@
S.SV Vee.
2S'C.
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
orVcc - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
/LA
1.6
1.5
mA
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Iccllnput
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.001
0.001
0.6
lOUT = -50/LA
·VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50/LA
·VIN = VIL or VIH
24mA
IOL
24mA
VI = Vcc,GND
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
p.A
VIN = Vcc
orGND
8.0
5.5
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for S4ACT
@
2S'C is identical to 74ACT
@
2S'C.
4-66
AC Electrical Characteristics:
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Units
Fig.
No.
13.0
9.5
ns
2-3,4
2.5
2.0
11.0
8.5
ns
2-3,4
14.5
11.0
3.5
3.0
13.0
10.0
ns
2-3,4
12.5
10.0
3.0
2.5
11.0
8.5
ns
2-3,4
Units
Fig.
No.
Parameter
Vee·
(V)
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
AntoDn
3.3
5.0
4.0
3.0
8.0
6.5
11.5
8.5
1.0
1.0
14.5
11.0
3.5
2.5
tpHL
Propagation Delay
AntoDn
3.3
5.0
3.0
2.5
7.0
5.5
10.0
7.5
1.0
1.0
12.5
10.0
tpLH
Propagation Delay
EntoDn
3.3
5.0
4.5
3.5
9.5
7.0
12.0
8.5
1.0
1.0
Propagation Delay
En to Dn
'Voltage Range 3.3 Is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
3.3
5.0
4.0
2.5
8.0
6.0
10.0
7.5
1.0
1.0
Symbol
tpHL
AC Electrical Characteristics:
Symbol
Vee·
Parameter
(V)
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl=50pF
Min
Typ
Max
Min
Max
Min
Max
5.0
1.5
6.0
8.5
1.0
12.0
1.5
9.5
ns
2-3,4
Propagation Delay
AntoDn
5.0
1.5
6.0
9.5
1.0
11.0
1.5
10.5
ns
2-3,4
Propagation Delay
EntoDn
5.0
2.5
7.0
10.0
1.0
12.5
2.0
11.0
ns
2-3,4
5.0
2.0
7.0
9.5
1.0
12.0
1.5
10.5
ns
2-3,4
tpLH
Propagation Delay
AntoDn
tpHL
tpLH
Propagation Delay
EntoDn
'Voltage Range 5.0 is 5.0V ±0.5V
tpHL
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CpO
Power Dissipation
Capacitance
40.0
pF
4-67
Vee = 5.0V
~
II)
~
,------------------------------------------------------------------------,
~National
~ semiconductor
54AC/74AC151 • 54ACT/74ACT151
a-Input Multiplexer
General Description
Features
The 'ACI'ACT151 is a high-speed 8-input digital multiplexer.
It provides, in one package, the ability to select one line of
data from up to eight sources. The 'ACI'ACT151 can be
used as a universal function generator to generate any logic
function of four variables. Both true and complementary outputs are provided.
• Outputs source/sink 24. mA
• 'ACT151 has TTL-compatible inputs
• Standard Military Drawing (SMD)
-'AC151: 5962-87691
-'ACT151: 5962-88756
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
I I I I I I I I
-oE
13 12 1, 10 Z-
1
2
3
4
5
6
IEEE/IEC
ZE-
. MUX
GND- 8
-50
-5,
z
-52
Pin Assignment
for DIP, Flatpak and SOIC
z
'------,y~-,.--I----'
TL/F/9927-1
\"../
7
Z Z NC 10 1,
16 I-Vcc
15 1-1.
14 1-15
13 1-16
12 1-17
111-50
10 1-5,
5, -
o} G~
5 2-
2
-z
2
-2
13-
3
4
5
16-
6
il"rn12
~ 11]13
~
NCIIlI~
~ITlNC
S21rn~
• ~Vcc
~ lim 14
S,irn ~
'" '" "'-'" "',
1i]J1im1i]]1iZI1i]]
Inputs
TL/F /9927-6
Description
Data Inputs
Select Inputs
Enable Input
Data Output
Inverted Data Output
TLlF/9927-3
Truth Table
17-1..7_ _ _- - '
Pin Names
GND IiQJ
'II .........
So~NC~15
12-
15-
E[[J~
TLlF/9927-2
100
1, - t
14-
[[J[IJ[[][[][iJ
91-52
E- EN
50-
Pin Assignment
forlCC
52
51
So
Z
H
L
L
L
L
L
L
L
L
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
io
i,
i2
i3
i4
is
is
i7
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
4-68
Outputs
E
Z
L
10
1,
12
13
14
Is
Is
17
r------------------------------------------------------------------------------------------,
Functional Description
-A
The 'AC/'ACT151 is a logic implementation of a single pole,
S-position switch with the switch position controlled by the
state of three 5elect inputs, 50, 51, 52. Both true and complementary outputs are provided. The Enable input (E) is
active LOW. When it is not activated, the complementary
output is HIGH and the true output is LOW regardless of all
other inputs. The logic function provided at the output is:
Z =
The 'AC/'ACT151 provides the ability, in one package to
select from eight sources of data or control information. By
proper manipulation of the inputs, the 'AC/'ACT151 can
provide any logic function of four variables and its complement.
E • (10 • So • SI • S2 + 11 • 50 • SI • S2 +
12 • So • 51 • S2
14 • So • SI • 52
Is • So • 51 • 52
+ 13· 50 • 51 •
+ Is· 50 • SI •
+
52 +
52 +
17· 50 • 51 • 52)
Logic Diagram
12
- l -I
I
-
, ....
-A
U'I
r-
........
r-
0
r-
r
0
r- -
r-
-
r-
T
.... ~
r-
I-
0
.... ~
~
.JJ
~I
-
z z
TL/F/9927-4
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-69
.,..,
....
II)
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee)
DC Input Diode Current (1119
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current {IoKl
-20mA
Vo = -0.5V
Vo = Vee + 0.5V
+20mA
DC Output Voltage (Vo)
-0.5V to to Vee + 0.5V
DC Output Source
±50mA
or Sink Current (10)
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGND)
Storage Temperature (TSTG)
- 65'C to + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design Is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
Supply Voltage (Vee)
'AC
'ACT
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (tN/t.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (t.V/t.t)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vto6.0V
4.5Vto5.5V
OV to Vee
OV to Vee
-40'C to + 85'C
- 55'C to + 125'C
125 mVlns
125 mVlns
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
<
VIH
VIL
VOH
74AC
S4AC
74AC
TA = +25'C
TA=
-S5'C to + 125'C
TA=
- 40'C to + 8S'C
Typ
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
orVee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
±1.0
±1.0
",A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
Maximum Input
±0.1
5.5
Leakage Current
•All outputs loaded; thresholds on input associated with oulput under test.
tMaximum lest duration 2.0 ms, one output loaded at a time.
liN
4-70
lOUT = -50/LA
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50 ",A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
....
....
U1
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA =
TA=
-55°C to + 125°C
TA=
- 40°C to + 85°C
+ 25°C
Typ
IOLD
IOHD
ICC
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
".A
VIN = Vee
orGND
5.5
8.0
• All outputs loaded; thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
Not.: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vcc.
Icc for 54AC @ 25'C is Identical to 74AC @ 25'C
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA =
+ 25°C
TA =
-55°C to + 125°C
TA=
- 40°C to + 85°C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVCC - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
p.A
1.6
1.5
mAo
VI = Vee - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
".A
VIN = Vee
orGND
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
leellnput
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
ICC
Maximum Quiescent
Supply Current
0.001
0.001
8.0
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT
@
25'C is identical to 74ACT
@
Conditions
Guaranteed Limits
0.6
5.5
Units
25'C.
4-71
lOUT = -50".A
'VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50".A
'VIN = VIL or VIH
24mA
IOL
24mA
VI = Vee,GND
.,...
.,...
II)
AC Electrical Characteristics:
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25"C
CL=50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
20.0
15.0
ns
2-3,4
2.5
1.5
20.0
15.0
ns
2-3,4
15.5
12.0
2.0
1.5
14.0
11.0
ns
2-3,4
1.0
1.0
15.5
12.0
1.5
1.5
14.0
11.0
ns
2-3,4
14.0
10.5
1.0
1.0
16.0
12.0
2.0
1.5
15.5
11.0
ns
2-3,4
15.0
11.0
1.0
1.0
18.0
13.0
2.0
1.5
16.0
12.0
ns
2-3,4
Units
Fig.
No.
Parameter
Vee'
(V)
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
SntoZorl
3.3
5.0
3.0
2.5
11.5
B.5
1B.0
13.0
1.0
1.0
22.0
15.5
3.0
2.0
tpHL
Propagation Delay
SntoZorl
3.3
5.0
2.5
2.0
12.0
B.5
1B.0
13.0
1.0
1.0
22.0
15.5
tpLH
Propagation Delay
EtoZorl
3.3
5.0
2.5
2.0
8.0
6.0
13.0
10.0
1.0
1.0
tpHL
Propagation Delay
EtoZorl
3.3
5.0
1.5
1.5
8.5
6.5
13.0
10.0
tpLH
Propagation Delay
In toZ orl
3.3
5.0
2.5
1.5
9.5
7.0
Propagation Delay
In toZ orl
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
3.3
5.0
2.5
1.5
9.5
7.0
Symbol
tpHL
AC Electrical Characteristics:
Symbol
Parameter
Vee·
(V)
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125"C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
Sn toZ
5.0
3.5
12.5
15.5
1.0
19.5
3.0
17.0
ns
2·3,4
tpHL
Propagation Delay
Sn toZ
5.0
3.5
12.5
15.5
1.0
20.0
3.0
16.5
ns
2-3,4
tpLH
Propagation Delay
Sn tol
5.0
3.5
12.5
15.0
1.0
19.5
3.0
16.5
ns
2-3,4
tpHL
Propagation Delay
Sn tol
5.0
4.0
12.5
16.5
1.0
20.0
3.5
18.5
ns
2-3,4
tpLH
Propagation Delay
EtoZ
5.0
2.5
6.0
9.5
1.0
12.0
2.5
10.0
ns.
2·3,4
tpHL
Propagation Delay
EtoZ
5.0
2.5
6.0
9.0
1.0
12.5
2.5
10.0
ns
2-3,4
tpLH
Propagation Delay
Etol
5.0
2.5
6.0
8.5
1.0
12.0
2.5
9.5
ns
2-3,4
tpHL
Propagation Delay
Etol
5.0
3.0
6.5
10.0
1.0
12.5
2.5
10.5
ns
2-3,4
tpLH
Propagation Delay
In toZ
5.0
3.5
7.5
11.5
1.0
15.0
3.0
12.5
ns
2-3,4
tpHL
Propagation Delay
In toZ
5.0
3.5
8.0
12.0
1.0
16.0
3.0
13.5
ns
2-3,4
tpLH
Propagation Delay
In tol
5.0
3.5
8.0
12.0
1.0
15.0
3.0
13.0
ns
2-3,4
5.0
4.0
8.0 .
12.5
1.0
16.0
3.0
14.0
ns
2·3,4
Propagation Delay
In tol
'Voltage Range 5.0 is 5.0V ± 0.5V
tpHL
4-72
r-------------------------------------------------------------------------------------, ...
...
U1
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPD
Power Dissipation
Capacitance
70.0
pF
4·73
Vee = 5.0V
~ r-----------------------------------------------------------------------~
Ln
.....
~National
~ Semiconductor
54AC/74AC153. 54ACT/74ACT153
Dual 4-lnput Multiplexer
General Description
Features
The 'ACI'ACT153 is a high-speed dual 4-input multiplexer
with common select inputs and individual enable inputs for
each section. It can select two lines of data from four sources. The two buffered outputs present data in the true (noninverted) form. In addition to multiplexer operation, the 'AC/
'ACT153 can act as a function generator and generate any
two functions of three variables.
• Outputs source/sink 24 mA
• 'ACT153 has TTL-compatible inputs
• Standard Military Drawings (SMD)
- 'AC153: 5962-87625
- 'ACT153: 5962-87698
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
So
E.
1
16
51
2
15
Eb
E.
13e
12a
3
14
50
4
13
lOa
l 'a
l 'a
5
12
13b
12b
51
TLlF19928-1
Ze
12a
13&
Vee
lOa
6
11
lib
Ze
7
8
10
lab
9
Zb
GND
Eb
TLlF/9928-3
lOb
lib
12b
13b
TLlF/9928-2
Pin Assignment
forLCC
Pin Names
10a-ISa
10b-ISb
SO,SI
Ea
Eb
Za
Zb
'a NC
Description
loa l
~
Sa
OOIIl!ID[I)rn
Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Enable Input
Side B Enable Input
Side A Output
Side B Output
[II 51
[II Ea
[IlNC
Ze []]
GND fj]J
NC Il]
~Vee
Zb 1m
lOb IilI
[j])~
1HI1rn1l]J1ill1iID
lib 12b HC 13b
So
TL/F/9928-4
4-74
r-------------------------------------------------------------------------------------, -"
Functional Description
The 'AC/'ACT153 is a dual4-input multiplexer. It can select
two bits of data from up to four sources under the control of
the common Select inputs (So, 51). The two 4-input multiplexer circuits have individual active-LOW Enables (Ea, Eb)
which can be used to strobe the outputs indepedenlly.
When the Enables (Ea, Eb) are HIGH, the corresponding
outputs Za, Zb) are forced LOW. The 'AC/'ACT153 is the
logic implementation of a 2-pole, 4-position switch, where
the position of the switch is determined by the logic levels
supplied to the Select inputs. The logic equations for the
outputs are shown below.
Za = Ea-(loa-51-50 + 11a-51-So
12a - 51 - So + 13a - 51 - So)
Zb = Eb - (lOb - 51 - 50 + 11b - 51 - So
12b - 51 - So + 13b - 51 - So)
U1
Co)
Truth Table
Select
Inputs
+
+
Inputs (a or b)
Output
So
Sl
E
10
11
12
13
Z
X
X
X
L
L
H
L
L
L
H
L
L
L
L
H
X
X
X
X
L
X
X
X
X
X
X
X
X
L
L
H
L
H
L
L
H
H
L
H
H
H
H
L
L
L
L
L
X
X
X
X
X
H
X
X
X
X
X
L
H
X
X
X
X
X
L
H
H
L
H
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
TL/F/992B-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-75
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
-0.5Vto +7.0V
DC Input Diode Current (11K)
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
-20mA
Vo = -0.5V
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5VtotoVee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGNO)
Storage Temperature (TSTG)
-65'C to + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design Is reliable over Its power supply,
temperature, and output/Input loading variables. National does not recom·
mend operation of FACTTM circuits outside dalabook specifications.
Supply Voltage (Vee)
'AC
'ACT
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (AVlAt)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (AVlAt)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vt06.OV
4.5Vto 5.5V
OV to Vee
OVtoVee
-40'Cto +85'C
- 55'C to + 125'C
125 mV/ns
125 mV/ns
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'Cto +85'C
Typ
VIH
VIL
VOH
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49'
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
±1.0
±1.0
p,A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
Maximum Input
±0.1
5.5
Leakage Current
•All outputs loaded; thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
liN
4·76
lOUT = - 50 p,A
'VIN = VIL or VIH
-12mA
-24mA
IOH
-24mA
lOUT = 50 p,A
'VIN = VIL or VIH
12mA
24mA
IOL
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA =
TA =
-55'C to + 125'C
TA=
- 40'C to + 85'C
+ 25'C
Typ
IOLD
IOHD
IcC
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
160.0
BO.O
/l-A
VIN = Vcc
orGND
5.5
B.O
'All outputs loaded; thresholds on input associated with output under test.
2.0 ms. one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective
Icc for 54AC @ 25'C is identical to 74AC @ 25'C.
tMaximum test duration
limit
@
5.5V Vcc.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA=
+ 25'C
TA =
-55'C to + 125'C
TA =
-40'Cto +85'C
Parameter
Vee
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.lV
orVCC - O.lV
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
O.B
O.B
O.B
O.B
V
VOUT = O.lV
orVcc - O.lV
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.B6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
/l-A
1.6
1.5
mA
Symbol
(V)
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Iccllnput
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.001
0.001
Units
Conditions
Guaranteed Limits
0.6
lOUT = -50/l-A
·VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50/l-A
·VIN = VIL or VIH
24mA
24mA
IOL
VI = Vcc.GND
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
160.0
BO.O
/l-A
VIN = Vee
orGND
5.5
B.O
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: ICC for 54ACT @ 25'C is identical to 74ACT @ 25'C.
4-77
AC Electrical Characteristics:
See Section 2 for Waveforms
74AC
S4AC
74AC
TA = +25"C
CL = SOpF
TA = -S5"C
to + 125"C
CL = SOpF
TA = -400C
to +8SoC
CL = SOpF
Parameter
Vee'
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
Sn toZn
3.3
5.0
2.5
2.0
9.5
6.5
15.0
11.0
1.0
1.0
19.5
14.0
2.5
2.0
tpHL
Propagation Delay
SntoZn
3.3
5.0
3.0
2.5
8.5
6.5
14.5
11.0
1.0
1.0
18.0
13.5
tpLH
Propagation Delay
EtoZn
3.3
5.0
2.5
1.5
8.0
5.5
13.5
9.5
1.0
1.0
tpHL
Propagation Delay
EtoZn
3.3
5.0
2.5
2.0
7.0
5.0
11.0
8.0
tpLH
Propagation Delay
IntoZn
3.3
5.0
2.5
1.5
7.5
5.5
Propagation Delay
IntoZn
'Voltage Range 3.3 Is 3.3V ± 0.3V
Voltage Range S.O Is S.OV ±O.SV
3.3
5.0
1.5
1.5
7.0
5.0
Symbol
(V)
tpHL
AC Electrical Characteristics:
Symbol
Vee'
Parameter
(V)
Units
Fig.
No.
17.5
12.5
ns
2-3,4
2.5
2.0
16.5
12.0
ns
2-3,4
16.5
12.5
2.0
1.5
16.0
11.0
ns
2-3,4
1.0
1.0
14.0
10.0
2.0
1.5
12.5
9.0
ns
2-3,4
12.5
9.0
1.0
1.0
16.0
11.5
2.0
1.5
14.5
10.5
ns
2·3,4
11.5
8.5
1.0
1.0
14.5
10.5
1.5
1.5
13.0
10.0
ns
2·3,4
Units
Fig.
No.
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2SoC
CL = SOpF
TA = -S5"C
to + 12SoC
CL = SOpF
TA = -400C
to +8SoC
CL=SOpF
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
Sn toZn
5.0
3.0
7.0
11.5
1.0
15.0
2.0
13.5
ns
2·3,4
tpHL
Propagation Delay
Sn to Zn
5.0
3.0
7.0
11.5
1.0
14.5
2.5
13.5
ns
2·3,4
tpLH
Propagation Delay
En toZ n
5.0
2.0
6.5
10.5
1.0
13.5
2.0
12.5
ns
2·3,4
tpHL
Propagation Delay
En toZ n
5.0
3.0
6.0
9.5
1.0
11.5
2.5
11.0
ns
2·3,4
tpLH
Propagation Delay
In to Zn
5.0
2.5
5.5
9.5
1.0
12.5
2.0
11.0
ns
2·3,4
5.0
2.0
5.5
9.5
1.0
12.0
2.0
11.0
ns
2·3,4
Propagation Delay
intoZn
'Voltage Range S.O is S.OV ± o.sv
tpHL
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
65.0
pF
Vee = 5.0V
4-78
r----------------------------------------------------------------------------, -"
U1
......
~National
~ semiconductor
54AC/74AC157. 54ACT/74ACT157
Quad 2-lnput Multiplexer
General Description
Features
The 'ACI'ACT157 is a high-speed quad 2-input multiplexer.
Four bits of data from two sources can be selected using
the common Select and Enable inputs. The four outputs
present the selected data in the true (noninverted) form.
The' ACI' ACT157 can also be used as a function generator.
• Outputs source/sink 24 rnA
• 'ACT157 has TTL-compatible inputs
• Standard Military Drawing (SMD)
- 'AC157: 5962-89539
- 'ACT157: 5962-89688
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
s
TL/F/9929-'
IEEEIIEC
lOa
I,.
lab
I'b
lad
I'd
lac
I'e
IOa-lod
11a-lld
E
S
Za-Zd
Vee
2
15
3
14
IDe
Za
4
13
lIe
lOb
5
12
Ze
lIb
6
11
10d
Zb
7
10
lId
GND
8
9
Zd
TLiF/9929-3
Za
Zb
Pin Assignment
forlCC
Zd
lIb lot. NC Za lId
(]]1Zl(]]1]][!]
Ze
TL/F/9929-2
Pin Names
16
IDa
11a
Description
Source 0 Data Inputs
Source 1 Data Inputs
Enable Input
Select Input
Outputs
Zb [[]
GND IiQI
NC [j)
[IlNC
Zd IilI
'ld liM
Ii])E
mlOa
ms
~vcc
1HI1rn11i]Jli1J1i]J
lad Z. NC "e foe
TL/F/9929-4
4-79
III
~
II)
.....
r---------------------------------------------------------------------------------,
Functional Description
The 'AC/'ACT157 is a quad 2-input multiplexer. It selects
four bits of data from two sources under the control of a
common Select input (S). The Enable input iE) is activeLOW. When E is HIGH, all of the outputs (Z) are forced
LOW regardless of all other inputs. The 'ACI'ACT157 is the
logic implementation of a 4-pole, 2-position switch where
the position of the switch is determined by the logic levels
supplied to the Select input. The logic equations for the outputs are shown below:
Zc
Zd
Truth Table
Inputs
S + lOa • 5)
= E • (11 b • S + lOb. 5)
= E • (Ilc • S + loc· 5)
= E· (lld· S + 10d • 5)
Za =
Zb
as a function generator. The 'AC/'ACT157 can generate
any four of the sixteen different functions of two variables
with one variable common. This is useful for implementing
gating functions.
E.
(lla •
A common use of the 'AC/ACT157 is the moving of data
from two groups of registers to four common output busses.
The particular register from which the data comes is determined by the state of the Select input. A less obvious use is
outputs
E
5
10
11
Z
H
L
L
L
L
X
X
X
X
X
L
H
X
X
L
.L
H
L
H
H
H.
L
L
L
H
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Immaterial
Logic Diagram
TL/F/9929-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays•
.:\-80
.....
Absolute Maximum Rating
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-20mA
+20mA
-0.5Vto to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
±50mA
Storage Temperature (T8m)
OV to Vee
OVtoVee
Output Voltage (Va)
-0.5VtoVee + 0.5V
DC Output Source
or Sink Current (10)
.....
2.0Vt06.0V
4.5Vto 5.5V
Input Voltage (VI)
-20mA
+20mA
DC Input Voltage (VI)
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
Supply Voltage (Vecl
'AC
'ACT
-0.5Vto +7.0V
Supply Voltage (Vecl
U1
Recommended Operating
Conditions
(Note 1)
-65'Cto +150'C
-40'Cto +85'C
-55'C to + 125'C
Minimum Input Edge Rate (AV/,M)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (AV / At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
CDIP
175'C
140'C
PDlP
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply.
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outsida databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + 125'C
TA=
-40'Cto +S5'C
Typ
VIH
VIL
VOH
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
±1.0
±1.0
,.,.A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
3.0
4.5
5.5
Maximum Input
±0.1
5.5
Leakage Current
•All outputs loaded; thresholds on input associated with output under test.
liN
tMaximum test duration 2.0 mB, one output loaded at a time.
4-81
lOUT = -50,.,.A
·VIN = VIL or VIH
-12mA
-24 rnA
10H
-24mA
lOUT = 50,.,.A
·VIN = VIL or VIH
12mA
24 rnA
10L
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA =
+ 25'C
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
tMinimum Dynamic
Output Current
IOLD
IOHD
Maximum Quiescent
Supply Current
Icc
Units
Conditions
Guaranteed Limits
5.5
50
75
rnA
VOLD = 1.65V Max
5.5
-50
-75
rnA
VOHD = 3.S5V Min
160.0
so.o
r- A
VIN = Vcc
orGND
s.o
5.5
*AII outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit
Icc for S4AC @ 2S'C is identical to 74AC @ 2S'C.
@
5.5V Vee.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.S
O.S
O.S
O.S
O.S
O.S
V
VOUT = 0.1V
orVcc - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.S6
4.S6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
r-A
1.6
1.5
rnA
Symbol
TA
=
+ 25'C
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
lecT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Ice
Maximum Quiescent
Supply Current
0.001
0.001
0.6
@
= -50 r-A
'VIN
= VIL or VIH
-24 rnA
-24 rnA
IOH
lOUT
= 50 r-A
'VIN
= VIL or VIH
24 rnA
24 rnA
IOL
VI = Vec. GND
VI = Vee - 2.1V
= 1.65V Max
50
75
rnA
YOLO
5.5
-50
-75
rnA
VOHD = 3.S5V Min
160.0
SO.O
r- A
VIN = Vcc
orGND
5.5
S.O
tMaximum test duration 2.0 ms, one output loaded at a time.
ICC for S4ACT
lOUT
5.5
*AII outputs loaded; thresholds on input associated with output under test.
Noto:
Conditions
Guaranteed Limits
Typ
4.5
5.5
Units
2S'C is identical to 74ACT
@
2S'C.
4-S2
....
AC Electrical Characteristics:
U1
......
See Section 2 for waveforms.
74AC
54AC
74AC
TA = +25°C
CL = 50pF
TA = -55°C
to + 125°C
CL = 50pF
TA = -40°C
to +85°C
CL = 50pF
Units
Fig.
No.
13.0
10.0
ns
2-3,4
1.5
1.0
12.0
9.5
ns
2-3,4
16.0
12.0
1.5
1.5
13.0
10.0
ns
2-3,4
1.0
1.0
14.0
11.5
1.5
1.0
12.0
9.5
ns
2-3,4
8.5
6.5
1.0
1.0
11.0
9.0
1.0
1.0
9.0
7.0
ns
2-3,4
8.0
6.5
1.0
1.0
11.0
9.0
1.0
1.0
9.0
7.0
ns
2-3,4
Units
Fig.
No.
Parameter
Vee'
(V)
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
StoZn
3.3
5.0
1.5
1.5
7.0
5.5
11.5
9.0
1.0
1.0
16.0
12.0
1.5
1.5
tpHL
Propagation Delay
StoZn
3.3
5.0
1.5
1.5
6.5
5.0
11.0
8.5
1.0
1.0
14.0
11.5
tpLH
Propagation Delay
i:toZn
3.3
5.0
1.5
1.5
7.0
5.5
11.5
9.0
1.0
1.0
tpHL
Propagation Delay
i:toZn
3.3
5.0
1.5
1.5
6.5
5.5
11.0
9.0
tpLH
Propagation Delay
In to Zn
3.3
5.0
1.5
1.5
5.0
4.0
Propagation Delay
In to Zn
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
3.3
5.0
1.5
1.5
5.0
4.0
Symbol
tpHL
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
See Section 2 for waveforms.
74ACT
54ACT
74ACT
TA = +25°C
CL = 50pF
TA = -55°C
to + 125"C
CL = 50pF
TA = -40"C
to +85°C
CL = 50pF
Min
Typ
Max
Min
Max
Min
Max
5.0
2.0
5.5
9.0
1.0
11.5
1.5
10.0
ns
2-3,4
Propagation Delay
StoZn
5.0
2.0
5.5
9.5
1.0
11.5
2.0
10.5
ns
2·3,4
tpLH
Propagation Delay
i:toZn
5.0
1.5
6.0
10.0
1.0
12.0
1.5
11.5
ns
2-3,4
tpHL
Propagation Delay
i:toZn
5.0
1.5
5.0
8.5
1.0
10.0
1.0
9.0
ns
2-3,4
tpLH
Propagation Delay
In to Zn
5.0
1.5
4.0
7.0
1.0
8.5
1.0
8.5
ns
2-3,4
5.0
1.5
4.5
7.5
1.0
9.0
1.0
8.5
ns
2-3,4
tpLH
Propagation Delay
StoZn
tpHL
Propagation Delay
In to Zn
'Voltage Range 5.0 Is 5.0V ± O.5V
tpHL
Capacitance
Symbol
Parameter
Typ
Units
CIN
input Capacitance
4.5
pF
Vee
=
5.0V
CPD
Power Dissipation
Capacitance
50.0
pF
Vee
=
5.0V
4-83
Conditions
•
~National
~ Semiconductor
54AC/74AC158. 54ACT/74ACT158
Quad 2-lnput Multiplexer
General Description
Features
The 'AC/'ACT15B is a high-speed quad 2-input multiplexer.
It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs
present the selected data in the inverted form. The 'AC/
'ACT15B can also be used as a function generator.
• Outputs source/sink 24 mA
• 'ACT15B has TIL-compatible inputs
• Standard Military Drawing (SMD)
- 'AC15B: 5962-B9729
- 'ACT15B: 5962-BB755
Ordering Code: See Section B
Logic Symbols
-<
Connection Diagrams
I I I I I I I I
E
'0• I,. lOb 'ib 10e 'ie 'Od 'id
-s
Pin Assignment
for DIP, Flatpak and sOle
Pin Assignment
for Lee
'-"
1ID1Zl1ID[ID0
s-
1
'00 - 2
,,. - 3
z.-
y y y y
TL/F/9930-1
141-Ioe
4
131-1'e
121- Ze
'Ob- 5
I'b- 6
I11-10d
Zb- 7
IOI-I'd
GND- 8
91- Zd
lEE/lEe
E
S
TLlF/9930-3
EN
GI
TL/F/9930-2
Pin Names
lOa-lad
11a- lld
E
S
Za-Zd
'ib
161- Vcc
151-E
Description
Source 0 Data Inputs
Source 1 Data Inputs
Enable Input
Select Input
Inverted Outputs
4-B4
lob
NC
Z. I,.
G~g:D~~·
NC Ill!
Zd Ii]]
'id Ii]]
[TINC
gQJ Vee
lim E
~1im1i]]1i1I1i]]
Iod2. NCI,eloc
TL/F/9930-4
....
Functional Description
U1
CO
Truth Table
The 'AC/'ACT15B quad 2-input multiplexer selects four bits
of data from two sources under the control of a common
Select input (S) and presents the data in inverted form at
the four outputs. The Enable input (EO) is active-LOW. When
E is HIGH, all of the outputs (Z) are forced HIGH regardless
of all other inputs. The 'AC/'ACT15B is the logic implementation of a 4-pole, 2-position switch where the position of the
switch is determined by the logic levels supplied to the Select input.
outputs
Inputs
A common use of the 'ACI'ACT15B is the moving of data
from two groups of registers to four common output busses.
The particular register from which the data comes is determined by the state of the Select input. A less obvious use is
as a function generator. The 'AC/'ACT15B can generate
four functions of two variables with one variable common.
This is useful for implementing gating functions.
E
S
10
11
Z
H
L
L
L
L
X
X
L
L
H
H
L
H
X
X
X
X
X
L
H
H
H
L
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
TLiF/9930-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
III
4-B5
Absolute Maximum Rating (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified davlces are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
-:0.5Vto +7.0V
DC Input Diode Current (11K)
-20mA
VI = -0.5V
VI = Vee + 0.5V
+20mA
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
-20mA
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGNO)
Storage Temperature (TSTG)
-65'Cto + 1500C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design Is reliable over its power supply,
temperature, and outputlinput loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
Supply Voltage (Vecl
'AC
'ACT
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TA)
2.0Vt06.0V
4.5Vt05.5V
OV to Vee
OVtoVee
-40'Cto +85'C
- 55'C to + 125'C
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (I:N/b.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (aV/b.t)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125mVlns
125mV/ns
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
S4AC
74AC
TA = +2S'C
TA=
-SS'C to + 12S'C
TA=
-40'Cto +85"C
Typ
VIH
VIL
VOH
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
±1.0
±1.0
".A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
Maximum Input
±0.1
5.5
Leakage Current
•All outputs loaded; thresholds on Input associated with output under tesl
tMaximum test duration 2.0 ms, one output loaded at a time.
liN
4-86
lOUT = -50 p,A
·VIN = VILorVIH
-12mA
-24mA
10H
-24mA
lOUT
= 50".A
·VIN = VILorVIH
12mA
24mA
10L
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + 125'C
TA =
-40'C to +S5'C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Icc
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
p.A
VIN = Vcc
orGND
8.0
5.5
"All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and ICC @ 3.0V are guaranteed to be less than
Icc for 54AC @ 25'C is identical to 74AC @ 25'C.
or equal to the respective limit
@
5.5V Vcc.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55'C to + 125'C
TA =
- 40'C to + 85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = O.lV
orVCC - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
!LA
1.6
1.5
mA
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
ICC
•All
Maximum Quiescent
Supply Current
0.001
0.001
Units
Conditions
Guaranteed Limits
0.6
lOUT = -50 !LA
'VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50 !LA
'VIN = VIL or VIH
24mA
24mA
IOL
VI = Vcc.GND
VI = Vcc - 2.1V
5.5
50
75
mA
5.5
-50
-75
mA
VOHD = 3.85V Min
!LA
VIN = Vcc
orGND
5.5
8.0
160.0
outputs loaded; thresholds on input associated with output under test.
2.0 ms. one output loaded at a time.
Note: ICC for 54ACT @ 25'C is identical to 74ACT @ 25'C.
tMaximum test duration
4-87
80.0
VOLD = 1.65V Max
co
II)
.....
AC Electrical Characteristics:
See Section 2 for waveforms.
74AC
S4AC
74AC
TA = +2SoC
Cl = SOpF
TA = -SsoC
to + 12SoC
Cl = SOpF
TA = -40°C
to +8SoC
Cl = SO pF
Parameter
Vee'
(V)
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
Stoln
3.3
5.0
1.5
1.5
7.0
5.5
11.5
9.0
1.0
1.0
14.0
11.0
1.5
1.0
lPHL
Propagation Delay
Stoln
3.3
5.0
I.S
1.5
7.0
5.5
II.S
9.0
1.0
1.0
14.0
11.0
tpLH
Propagation Delay
"Etoln
3.3
5.0
1.5
1.5
7.5
6.0
12.0
9.5
1.0
1.0
tpHL
Propagation Delay
"Etoln
3.3
5.0
1.5
1.5
7.0
5.5
11.0
8.5
tpLH
Propagation Delay
Intoln
3.3
5.0
1.5
1.5
5.5
4.0
tpHL
Propagation Delay
Intoln
3.3
5.0
1.5
1.5
5.0
4.0
Symbol
Units
Fig.
No.
12.5
9.5
ns
2-3,4
1.5
1.5
12.5
10.0
ns
2-3,4
15.0
12.0
1.5
1.5
13.0
10.5
ns
2-3,4
1.0
1.0
14.0
10.0
1.5
1.0
12.0
9.5
ns
2-3,4
9.0
7.0
1.0
1.0
11.0
8.5
1.5
1.0
10.0
7.5
ns
2-3,4
8.0
6.5
1.0
1.0
10.0
7.5
1.0
1.0
8.5
6.5
ns
2-3,4
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
See Section 2 for waveforms.
74ACT
S4ACT
74ACT
TA = +2SoC
Cl = SO pF
TA = -SsoC
to + 12SoC
Cl = SOpF
TA = -40°C
to +8SoC
Cl = SOpF
Min
Typ
Max
Min
Max
Min
Max
5.0
2.5
6.0
9.5
1.0
12.0
2.0
11.0
ns
2-3,4
Propagation Delay
Stoln
5.0
1.5
5.5
9.0
1.0
11.5
1.5
10.0
ns
2-3,4
tpLH
Propagation Delay
"Etoln
5.0
1.5
5.5
9.5
1.0
11.0
1.5
10.5
ns
2-3,4
tpHL
Propagation Delay
"Etoln
5.0
1.5
5.5
9.5
1.0
11.0
1.5
10.5
ns
2-3,4
tpLH
Propagation Delay
In to In
5.0
1.5
4.5
8.0
1.0
9.5
1.0
8.5
ns
2-3,4
tpHL
Propagation Delay
Intoln
5.0
1.5
4.0
6.5
1.0
8.0
1.0
7.5
ns
2-3,4
tpLH
Propagation Delay
Stoln
tpHL
'Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPD
Power Dissipation
Capacitance
45.0
pF
Vee = 5.0V
4-88
....
....
Q)
~National
~ Semiconductor
54AC/74AC161 • 54ACT/74ACT161
Synchronous Presettable Binary Counter
General Description
Features
The 'AC/'ACT161 are high-speed synchronous modul0-16
binary counters. They are synchronously presettable for application in programmable dividers and have two types of
Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The' AC/
'ACT161 has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW.
•
•
•
•
•
•
Ordering Code:
Synchronous counting and loading
High-speed synchronous expansion
Typical count rate of 125 MHz
Outputs source/sink 24 rnA
'ACT161 has TTL-compatible inputs
Standard Military Drawing (SMD)
- 'AC161: 5962-89561
See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
CTRDlV16
i.iR
i.iR
PE
TC
TC
CET
CEP
CP
16
CP
2
15
Vee
TC
Po
P1
3
14
00
4
13
01
P2
P3
5
12
O2
6
11
Po
00
CEP
7
10
03
CET
P1
P2
P3
01
GND
8
9
PE
TL/F/9931-1
O2
TL/F/9931-3
03
TlIF/9931-2
Pin Assignment
forLCC
P3 P2 NC P1 Po
00 III II][K) III
Pin Names
CEP
CET
CP
MR
PO-P3
PE
00-0 3
TC
CEP 00
GND [Q)
NC !IiI
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Asynchronous Master Reset Input
Parallel Data Inputs
Parallel Enable Inputs
Flip-Flop Outputs
Terminal Count Output
[1]CP
1Ili.iR
[j] NC
@IVee
[j][TC
PEIm
CET
I!ID
iHlli§lli][lllIli][
03 O2 NC 01 00
TLlF/9931-4
4-89
III
~ r---~-------------------------------------------------------------------------------------,
CD
~
Functional Description
The 'AC/'ACT161 counl in modul0-16 binary sequence.
From state 15 (HHHH) they increment to state 0 (LLLL). The
clock inputs of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the outputs (except due
to Master Reset of the '161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the GP input
signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset, parallel
load, count-up and hold. Five control inputs-Master Reset,
Parallel Enable (PE), Count Enable Parallel (GEP) and
Count Enable Trickle (CEn-determine the mode of operation, as shown in the Mode Select Table. A LOW signal on
MR overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be
loaded into the flip-flops on the next rising edge of CPo With
PE and MR HIGH, CEP and CET permit counting when both
are HIGH. Conversely, a LOW signal on either CEP or CET
inhibits counting.
to decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters.
When the Output Enable (OE) is LOW, the parallel data outputs 00-03 are active and follow the flip-flop outputs. A
HIGH signal on OE forces 00-03 to the High Z state but
does not prevent counting, loading or resetting.
a
a
Logic Equations: Count Enable = CEP • GET • PE
TC = 00 • 01 • 02 • 03 • CET
Mode Select Table
PE
CEr
CEP
X
X
X
X
X
H
L
H
X
L
L
H
H
H
The 'AC/'ACT161 use D-type edge-triggered flip-flops and
changing the PE, CEP and CET inputs when the CP is in
either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising
edge of CP, are observed.
X
Action on the Rising
Clock Edge (...r)
Reset (Clear)
Load (Pn ~ an)
Count (Increment)
No Change (Hold)
No Change (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
State Diagram
The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP
and GET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup
time of the last stage. This total delay plus setup time sets
the upper limit on clock frequency. For faster clock rates,
the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that
causes the first stage to tick over from max to min in the Up
mode, or min to max in the Down mode, to start its final
cycle. Since this final cycle requires 16 clocks to complete,
there is plenty of time for the ripple to progress through the
intermediate stages. The critical timing that limits the clock
period is the CP to TC delay of the first stage plus the CEP
to CP setup time of the last stage. The TG output is subject
TL/F/9931-5
TLlF/9931-B
FIGURE 1. Multistage Counter with Ripple Carry
TLlF/9931-9
FIGURE 2. Multistage Counter with Lookahead Carry
4-90
m
i5'
()
~
P2
P,
Po
P3
PE
c
i"
ca
Dl
3
C£P
C£r
~
~
CP
CI'
--t:>cH
I
I
I
------------_.
DUAil A I
iiii
00
0,
02
03
TUF/9931-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
~9~
I
......
CD
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Veel
-0.5Vto +7.0V
DC Input Diode Current (11K)
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (10K)
-20mA
Vo = -0.5V
+20mA
Va = Vee + 0.5V
DC Output Voltage (Va)
-0.5VtoVee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGNO)
Storage Temperature (TSTG)
-65'C to + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception. to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
Supply Voltage (Veel
'AC
'ACT
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (AV/At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (AV/At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vt06.0V
4.5Vto 5.5V
OVtoVee
OVtoVcc
-40'C to + 85'C
-55'Cto + 125'C
125 mV/ns
125 mVlns
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
74AC
Symbol
VIL
VOH
TA =
-55'C to + 125'C
TA =
-40'Cto +85'C
Vee
(V)
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
±1.0
±1.0
!J.A
TA
= +25'C
3.0
4.5
5.5
VOL
74AC
Parameter
Typ
VIH
54AC
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
Units
Conditions
Guaranteed Limits
Maximum Input
5.5
±0.1
Leakage Current
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one oulpulloaded al a time.
liN
4·92
lOUT
= - 5O !J.A
'VIN
= VIL or VIH
10H
-12mA
-24mA
-24mA
lOUT
= 5O!J.A
'VIN
= VIL or VIH
10L
VI
12mA
24mA
24mA
= Vee, GND
.....
en
.....
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
IOlD
IOHD
Icc
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
80.0
40.0
p.A
VIN = Vcc
orGND
4.0
5.5
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 mo. one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
Icc for 54AC @ 25'C is identical to 74AC @ 25·C.
DC Characteristics for' ACT Family Devices
Symbol
74ACT
54ACT
74ACT
TA = +25'C
TA =
-55'C to + 125'C
TA =
-40'Cto + 85'C
Parameter
Vce
(V)
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
0.8
O.B
0.8
O.B
V
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
p.A
1.6
1.5
mA
Typ
VIH
Vil
VOH
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
IcC/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.001
0.001
Units
Conditions
Guaranteed Limits
0.6
VOUT = 0.1V
orVcc - 0.1V
VOUT = 0.1V
orVcc - 0.1V
lOUT = -50 p.A
'VIN = Vil or VIH
-24mA
IOH
-24mA
lOUT = 50 p.A
'VIN = Vil or VIH
24mA
IOl
24mA
VI = Vcc,GND
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
BO.O
40.0
p.A
VIN = Vcc
orGND
5.5
4.0
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 mo. one output loaded at a time.
Note: Icc for 54ACT @ 25'C t~ identical to 74ACT @ 25·C.
4-93
....
co
....
AC Electrical Characteristics:
Symbol
See Section 2 for waveforms
Vcc·
Parameter
(V)
74AC
S4AC
74AC
TA = +2SoC
Cl = SOpF
TA = -SSOC
to + 12SoC
Cl = SOpF
TA = -40"C
to +8SoC
Cl = SOpF
Min
Min
Units
Fig.
No.
Min
Typ
f max
Maximum Count
Frequency
3.3
5.0
70
110
111
167
tpLH
Propagation Delay CP to an
(PE Input HIGH or LOW)
3.3
5.0
2.0
1.5
7.0
5.0
12
9.0
1.0
1.0
15.0
11.0
1.5
1.0
13.5
9.5
ns
2-3,4
tpHL
Propagation Delay CP to
(PE Input HIGH or LOW)
an
3.3
5.0
1.5
1.5
7.0
5.0
12
9.5
1.0
1.0
15.0
11.0
1.5
1.5
13
10
ns
2-3,4
tpLH
Propagation Delay
CP to TC
3.3
5.0
3.0
2.0
9
6
15
10.5
1.0
1.0
18.5
13.0
2.5
1.5
16.5
11.5
ns
2-3,4
tpHL
Propagation Delay
CPtoTC
3.3
5.0
3.5
2.0
8.5
6.5
14
11
1.0
1.0
. 17.5
13.0
.2.5
2.0
15.5
11.5
ns
2-3,4
tpLH
Propagation Delay
CETto TC
3.3
5.0
2.0
1.5
5.5
3.5
9.5
6.5
1.0
1.0
13.0
8.5
1.5
1.0
11
7.5
ns
2-3,4
tpHL
Propagation Delay
CETto TC
3.3
5.0
2.5
2.0
6.5
5
11
8.5
1.0
1.0
14.5
11.0
2.0
1.5
12.5
9.5
ns
2-3,4
tpHL
Propagation Delay
MRtoOn
3.3
5.0
2.0
1.5
6.5
5.5
12
9.5
1.0
1.0
14.5
10.5
1.5
1.5
13.5
10
ns
2-3,4
tpHL
Propagation Delay
MRtoTC
3.3
5.0
3.5
2.5
10
8.5
15
13
1.0
1.0
18.5
14.0
3.0
2.5
17.5
1.3.5
ns
2-3,4
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
4-94
Max
Max
55
80
Max
60
95
MHz
AC Operating Requirements:
....
....
en
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25°C
Cl = 50pF
TA = -55°C
to + 125°C
Cl = 50pF
TA = -40°C
to + 85°C
Cl = 50pF
Parameter
Vee·
(V)
ts
Setup Time, HIGH or LOW
Pn toCP
3.3
5.0
6.0
3.5
13.5
8.5
16.0
10.5
th
Hold Time, HIGH or LOW
PntoCP
3.3
5.0
-7.0
-4.0
-1
0
ts
Setup Time, HIGH or LOW
PEtoCP
3.3
5.0
6.5
4.0
th
Hold Time, HIGH or LOW
PE to CP
3.3
5.0
ts
Setup Time, HIGH or LOW
CEP or CETto CP
th
Units
Fig.
No.
16
10.5
ns
2-7
0.5
1.5
-0.5
0
ns
2-7
11.5
7.5
15.0
10.5
14
8.5
ns
2-7
-6.0
-3.5
0
0.5
-1.0
0.0
0
1
ns
2-7
3.3
5.0
3.0
2.0
6.0
4.5
7.5
5.5
7
5
ns
2-7
Hold Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
-3.5
-2
0
0
2.0
2.0
0
0.5
ns
2-7
tw
Clock Pulse Width
(Load) HIGH or LOW
3.3
5.0
2.0
2.0
3.5
2.5
5.0
5.0
4
3
ns
2-3
tw
Clock Pulse Width
(Count) HIGH or LOW
3.3
5.0
2.0
2.0
4.0
3.0
5.0
5.0
4.5
3.5
ns
2-3
Iw
MR Pulse Width,
LOW
3.3
5.0
3.0
2.5
5.5
4.5
5.0
5.0
7.5
6.0
ns
2-3
-2
-1
-0.5
0
1.5
2.0
0
0.5
ns
2-3,7
Symbol
Typ
i
Recovery Time
MRtoCP
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
tree
AC Electrical Characteristics:
Symbol
Vee·
(V)
Parameter
Guaranteed Minimum
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25°C
Cl = 50pF
TA = -55°C
to + 125°C
Cl = 50pF
TA = -40°C
to +85°C
Cl = 50pF
Min
Units
Fig.
No.
Min
Typ
5.0
115
125
5.0
1.5
5.5
9.5
1.5
10.5
ns
2-3,4
5.0
1.5
6.0
10.5
1.5
11.5
ns
2-3,4
Propagation Delay
CPtoTC
5.0
2.0
7.0
11.0
1.5
12.5
ns
2-3,4
tpHL
Propagation Delay
CP to TC
5.0
1.5
8.0
12.5
1.5
13.5
ns
2-3,4
tpLH
Propagation Delay
CETtoTC
5.0
1.5
5.5
8.5
1.5
10.0
ns
2-3,4
tpHL
Propagation Delay
CETtoTC
5.0
1.5
6.5
9.5
1.5
10.5
ns
2-3,4
tpHL
Propagation Delay
MRtoOn
5.0
1.5
6.0
10.0
1.5
11.0
ns
2-3,4
5.0
2.5
8.0
13.5
2.0
14.5
ns
2-3,4
f max
Maximum Count
Frequency
tplH
Propagation Delay CP to
(PE Input HIGH or LOW)
an
tpHL
Propagation Delay CP to
(PE Input HIGH or LOW)
an
tpLH
Propagation Delay
MRtoTC
'Voltage Range 5.0 is 5.0V ± 0.5V
tpHL
Max
Min
Max
Max
100
4-95
MHz
II
.....
CD
.....
AC Operating Requirements:
Symbol
Parameter
Vcc·
(V)
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Pn toCP
5.0
4.0
9.5
11.5
ns
2-3,4
th
Hold Time, HIGH or LOW
Pn toCP
5.0
-5.0
0
0
ns
2-3,4
ts
Setup Time, HIGH or LOW
PE to CP
5.0
4.0
8.5
9.5
ns
2-3,4
th
Hold Time, HIGH or LOW
PEtoCP
5.0
-5.5
-0.5
-0.5
ns
2-3,4
ts
Setup Time, HIGH or LOW
CEP or CET to CP
5.0
2.5
5.5
6.5
ns
2-3,4
th
Hold Time, HIGH or LOW
CEP or CET to CP
5.0
-3.0
0
0
ns
2-3,4
tv.
Clock Pulse Width
(Load) HIGH or LOW
5.0
2.0
3.0
3.5
ns
2-3
tw
Clock Pulse Width
(Count) HIGH or LOW
5.0
2.0
3.0
3.5
ns
2-3
tw
MR Pulse Width, LOW
5.0
3.0
3.0
7.5
ns
2-3
tree
Recovery Time
MR to CP
5.0
0
0
0.5
ns
2-3,7
'Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPD
Power Dissipation
Capacitance
45.0
pF
4-96
Vee = 5.0V
r--------------------------------------------------------------------------------, ...
en
Co)
~National
~ Semiconductor
54AC/74AC163. 54ACT/74ACT163
Synchronous Presettable Binary Counter
General Description
Features
The 'AC/'ACT163 are high-speed synchronous modul0-16
binary counters. They are synchronously presettable for application in programmable dividers and have two types of
Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The 'AC/
'ACT163 has a Synchronous Reset input that overrides
counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
•
•
•
•
•
•
Synchronous counting and loading
High-speed synchronous expansion
Typical count rate of 125 MHz
Outputs source/sink 24 mA
'ACT163 has TIL-compatible inputs
Standard Military Drawing (SMD)
- 'AC163: 5962-89582
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEEIIEC
Pin Assignment
for DIP, Flatpak and SOIC
CTRDIV16
Sii
PE
Sii
CP
2
15
vcc
TC
CEl
Po
3
14
Qo
CEP
PI
4
13
Ql
CP
P2
P3
5
12
6
11
TC
TC
TL/F/9932-1
Po
00
CEP
7
10
O2
Q3
CEl
PI
01
GND
8
9
PE
P2
P3
02
TLlF/9932-3
03
TL/F/9932-2
Pin Names
CEP
CET
CP
SR
PO-P3
PE
QO-Q3
TC
Pin Assignment
forLCC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Synchronous Reset Input
Parallel Data Inputs
Parallel Enable Input
Flip-Flop Outputs
Terminal Count Output
P3 P2 NC PI Po
[ID[I][IDlIDm
@]CP
CEP [ID
GND IIQ]
NC IIil
rnSii
III NC
PEIi1J
~vcc
@lTC
CEl~
[gJ1IIDJi]J1i2l1i]J
03 O2 NC 01 00
TL/F/9932-4
4-97
•
~
CD
.,...
,---------------------------------------------------------------------------------,
Functional Description
The 'AC/'ACT163 counts in modul0-16 binary sequence.
From state 15 (HHHH) it increments to state 0 (LLLL). The
clock inputs of all flip-flops are driven in parallel through a
outputs occur as a
clock buffer. Thus all changes of the
result of, and synchronous with, the LOW-to-HIGH transition
of the CP input signal. The circuits have four fundamental
modes of .operation, in order of precedence: synchronous
reset, parallel load, count-up and hold. Four control inputsSynchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)-determine the mode of operation, as shown in the Mode Select
Table. A LOW signal on SR overrides counting and parallel
loading and allows all outputs to go LOW on the next rising
edge of CPo A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be
loaded into the flip-flops on the next rising edge of CPo With
PE and SR HIGH, CEP and CET permit counting when both
are HIGH. Conversely, a LOW signal on either CEP or CET
inhibits counting.
to decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. For such applications, the Clocked Carry (CC) output is provided. The
CC output is normally HIGH. When CEP, CET, and TC are
LOW, the CC output will go LOW when the clock next goes
LOW and will stay LOW until the clock goes HIGH again, as
shown in the CC Truth Table. When the Output Enable (OE)
is LOW, the parallel data outputs 00-03 are active and
follow the flip-flop
outputs. A HIGH signal on OE forces
00-03 to the High Z state but does not prevent counting,
loading or resetting.
a
a
Logic Equations: Count Enable = CEP • CET • PE
TC =
CET
ao • a1 • a2 • a3 •
Mode Select Table
The 'ACI'ACT163 uses D-type edge-triggered flip-flops and
changing the SR, PE, CEP and CET inputs when the CP is in
either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup
time of the last stage. This total delay plus setup time sets
the upper limit on clock frequency. For faster clock rates,
the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that
causes the first stage to tick over from max to min in the Up
mode, or min to max in the Down mode, to start its final
cycle. Since this final cycle takes 16 clocks to complete,
there is plenty of time for the ripple to progress through the
intermediate stages. The critical timing that limits the clock
period is the CP to TC delay of the first stage plus the CEP
to CP setup time of the last stage. The TC output is subject
SR
PE
CET
CEP
L
H
H
H
H
X
X
X
X
X
H
L
H
X
L
L
H
H
H
X
Action on the Rising
Clock Edge (.../")
Reset (Clear)
Load (Pn an)
Count (Increment)
No Change (Hold)
No Change (Hold)
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X = Immaterial
State Diagram
TL/F/9932-5
TL/F/9932-8
FIGURE 1
TUF/9932-9
FIGURE 2
4-98
m
0'
(')
'"
C
ii)'
-
Pi:
P,
CQ
p.
P2
P,
iil
3
-L.
CEP
~
C£T
t
10
CP
I
I
-----~ -- --
rt>
f,
-r
~~
I(
CP
I
D
CP
D
Q
Q
r-
I .....
Oa
i
)
~9
)
Y
y
~
L
fi
r0DETAIL A
DETAIL A
I-
t-
~
"
~
._------ ------------_.
DETAIL A
DETAILA I
!II (~13)
a[>--l-{>
Oa
I
Q,
I
Q2
I
Q.
TLlF/9932-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
f!9~
I
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage {Vee>
-0.5Vto +7.0V
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0 ..5V
DC Output Voltage (Vo)
Supply Voltage (Vee)
'AC
'ACT
-20mA
+20mA
- 0.5V to to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
±50mA
-65'Cto +150'C
Storage Temperature (TSTG)
Input Voltage (VI)
OVtoVee
Output Voltage (Vo)
OVtoVee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
2.0Vt06.0V
4.5Vt05.5V
-40'Cto +B5'C
-55'Cto +125'C
Minimum Input Edge Rate (AV/At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125mV/ns
Minimum Input Edge Rate (AV/At)
'ACT Devices
VIN from O.BV to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/Input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
=
+25'C
Typ
VIH
VIL
VOH
liN
74AC
TA =
- 40'C to + 85'C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.B5
2.1
3.15
3.B5
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3,86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
fLA
3.0
4.5
5.5
VOL
54AC
TA =
-55'C to + 125'C
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-100
lOUT
= -
·VIN
=
VIL or VIH
-12mA
-24mA
-24mA
lOUT
=
50 fLA
·VIN
=
VIL or VIH
12mA
24mA
24mA
10H
10L
VI
=
50 fLA
Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + 125'C
TA=
-40"Cto + 85'C
Typ
IOLD
IOHD
Icc
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vcc
orGND
8.0
5.5
* All outputs loaded; thresholds on input associated with output under test.
tMaximum t8St duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranleed to be less than or equal to the respective limit @ S.SV Vee.
Icc for S4AC @ 2S'C is identical to 74AC @ 2S'C.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +25'C
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVce - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
orVCC - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
/LA
1.6
1.5
mA
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
IcC/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
ICC
Maximum Quiescent
Supply Current
0.001
0.001
0.6
lOUT = -50/LA
'VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50)LA
'VIN = VIL or VIH
24mA
24mA
IOL
VI = Vcc,GND
VI = VCC - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
)LA
VIN = VCC
orGND
5.5
8.0
tMaximum test duration 2.0 ms, one output loaded at a time.
@
Conditions
Guaranteed Limits
•All outputs loaded; thresholds on input associated with output under test.
Note: IcC for S4ACT
Units
2S'C is identical to 74ACT @ 2S'C.
4-101
II
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for waveforms
Vcc'
(V)
74AC
S4AC
74AC
TA = +2S'C
CL = SOpF
TA = -S5"C
to + 125"C
CL = SOpF
TA = -40"C
to +8SOC
CL=SOpF
Min
Min
Min
Typ
Max
Max
55
90
Units
Fig.
No.
Max
f max
Maximum Clock
Frequency
3.3
5.0
70
110
95
140
60
95
tpLH
Propagation Delay, CP to On
(PE Input HIGH or LOW)
3.3
5.0
2.0
1.5
7.5
5.5
12.5
9.0
1.0
1.0
13.5
9.5
1.5
1.0
13.5
9.5
ns
2-3,4
tpHl
Propagation Delay, CP to On
(PE Input HIGH or LOW)
3.3
5.0
1.5
1.5
8.5
6.0
12.0
9.5
1.0
1.0
12.5
9.5
1.5
1.5
13.0
10.0
ns
2-3,4
tpLH
Propagation Delay
CPtoTC
3.3
5.0
3.0
2.0 ,
9.5
7.0
15.0
10.5
1.0
1.0
16.5
11.0
2.5
1.5
16.5
11.5
ns
2-3,4
tpHL
Propagation Delay
CP to TC
3.3
5.0
3.5
2.0
11.0
8.0
14.0
11.0
1.0
1.0
15.0
11.0
2.5
2.0
15.5
11.5
ns
2-3,4
tpLH
Propagation Delay
CETto TC
3.3
5.0
2.0
1.5
7.5
5.5
9.5
6.5
1.0
1.0
11.0
7.5
1.5
1.0
11.0
7.5
ns
2-3,4
tpHL
Propagation Delay
CET to TC
3.3
5.0
2.5
2.0
8.5
6.0
11.0
8.5
1.0
1.0
12.0
9.0
2.0
1.5
12.5
9.5
ns
2-3,4
MHz
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements:
Symbol
Parameter
Vcc'
(V)
See Section 2 for waveforms
74AC
S4AC
74AC
TA = +25"C
CL = SOpF
TA = -SS'C
to + 12S'C
Cl = SOpF
TA = -40"C
to +85"C
CL = SOpF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Pn to CP
3.3
5.0
5.5
4.0
13.5
8.5
17.0
11.0
16.0
10.5
ns
2-7
th
Hold Time, HIGH or LOW
PntoCP
3.3
5.0
-7.0
-5.0
-1.0
0
-0.5
0
-0.5
0
ns
2-7
ts
Setup Time, HIGH or LOW
SRtoCP
3.3
5.0
5.5
4.0
14.0
9.5
17.0
12.0
16.5
11.0
ns
2-7
th .
Hold Time, HIGH or LOW
SRtoCP
3.3
5.0
-7.5
-5.5
-1.0
-0.5
-0.5
0
-0.5
0
ns
2-7
ts
Setup Time, HIGH or LOW
PEtoCP
3.3
5.0
5.5
4.0
11.5
7.5
16.0
9.5
14.0
8.5
ns
2-7
th
Hold Time, HIGH or LOW
PE to CP
3.3
5.0
-7.5
-5.0
-1.0
-0.5
-0.5
0
-0.5
0
ns
2-7
ts
Setup Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
3.5
2.5
6.0
4.5
8.0
5.5
7.0
5.0
ns
2-7
th
Hold Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
-4.5
-3.0
0
0
0
0.5
0
0.5
ns
2-7
tw
Clock Pulse Width (Load)
HIGH or LOW
3.3
5.0
3.0
2.0
3.5
2.5
5.0
5.0
4.0
3.0
ns
2-3
tw
Clock Pulse Width (Count)
HIGH or LOW
3.3
5.0
3.0
2.0
4.0
3.0
5.0
5.0
4.5
3.5
ns
2-3
'Voltage Range 3.3 Is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ±0.5V
4-102
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for waveforms
Vcc'
(V)
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Min
Typ
5.0
120
140
Propagation Delay, CP to an
(PE Input HIGH or LOW)
5.0
1.5
5.5
10.0
1.5
11.0
ns
2·3,4
tpHL
Propagation Delay, CP to an
(PE Input HIGH or LOW)
5.0
1.5
6.0
11.0
1.5
12.0
ns
2·3,4
tpLH
Propagation Delay
CP to TC
5.0
2.5
7.0
11.5
2.0
13.5
ns
2·3,4
tpHL
Propagation Delay
CPtoTC
5.0
3.0
8.0
13.5
2.0
15.0
ns
2·3,4
tpLH
Propagation Delay
CETtoTC
5.0
2.0
5.5
9.0
1.5
10.5
ns
2·3,4
tpHL
Propagation Delay
CETtoTC
5.0
2.0
6.0
10.0
2.0
11.0
ns
2·3,4
Maximum Clock
Frequency
tpLH
Max
Fig.
No.
Min
f max
Max
Units
Max
105
MHz
'Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements:
Symbol
Parameter
Vcc'
(V)
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Pn toCP
5.0
4.0
10.0
12.0
ns
2·7
th
Hold Time, HIGH or LOW
PntoCP
5.0
-5.0
0.5
0.5
ns
2·7
ts
Setup Time, HIGH or LOW
SRtoCP
5.0
4.0
10.0
11.5
ns
2·7
th
Hold Time, HIGH or LOW
SRtoCP
5.0
-5.5
-0.5
-0.5
ns
2·7
ts
Setup Time, HIGH or LOW
PEto CP
5.0
4.0
8.5
10.5
ns
2·7
th
Hold Time, HIGH or LOW
PEtoCP
5.0
-5.5
-0.5
0
ns
2·7
ts
Setup Time, HIGH or LOW
CEP or CET to CP
5.0
2.5
5.5
6.5
ns
2·7
th
Hold Time, HIGH or LOW
CEP or CET to CP
5.0
-3.0
0
0.5
ns
2-7
tw
Clock Pulse Width (Load)
HIGH or LOW
5.0
2.0
3.5
3.5
ns
2-3
tw
Clock Pulse Width
(Count) HIGH or LOW
5.0
2.0
3.5
3.5
ns
2-3
'Voltage Range 5.0 is 5.0V ±0.5V
4-103
III
~
CD
.,...
,---------------------------------------------------------------------------------,
Capacitance
Symbol
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPD
Power Dissipation
Capacitance
45.0
pF
Vee = 5.0V
Parameter'
4·104
r---------------------------------------------------------------------------~
~ Semiconductor
54AC/74AC16g e 54ACT/74ACT169
4-Stage Synchronous Bidirectional Counter
General Description
Features
The 'ACI'ACT169 is fully synchronous 4-stage up/down
counter. The 'ACI'ACT169 is a modulo-16 binary counter. It
features a preset capability for programmable operation,
carry lookahead for easy cascading and a u/5 input to control the direction of counting. All state changes, whether in
counting or parallel loading, are initiated by the LOW-toHIGH transition of the Clock.
•
•
•
•
•
Synchronous counting and loading
Built-In lookahead carry capability
Presettable for programmable operation
Outputs source/sink 24 mA
'ACT has TTL-compatible inputs
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
PE
U/O
16
2
15
TC
Po
3
t4
4
13
5
12
02
CEP
PI
P2
P3
00
01
6
11
CP
CEP
7
10
03
CEl
GNO
8
TC
CEl
Po
PE
00
1,70
PI
P2
TLlF/9934-3
01
Pin Assignment
forLCC
02
03
P3
P3 P2 NC PI Po
[I] ['[J[I]
TLlF/9934-2
rn[IJ
rn
Pin Names
CEP
CET
CP
PO-P3
PE
u/5
00-0 3
TC
Vee
CP
U/O
TLlF/9934-1
en
CD
~National
TC
...
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Parallel Data Inputs
Parallel Enable Input
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output
CEP
GNO IiID
NC !IT!
1lJ CP
PErm
~Vee
mu/o
ITl NC
CEl 1m
IIDTC
1ffi1lID1ID1m1ID
03 02 NC 01
00
TL/F/9934-4
4-105
Q) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
....CD
Logic Diagram
Pi:
m
CEi'
p.
-'"
p.
P2
P,
"Vl.g......
~
...
-
--- ---- --_ ... _..
T
-
r
r.Yl.
I
1~1,,
IJ
l~
,,
LD
lil'
~
-,...
-
L..h
1
CP
........
6
I~
CP
BT-
--
Bf-
-
-
UP
DN
DETM A
U
D1;f
ENf
I
y-
---:-t
~
~
rr:l
-
DETAIL A
-
CP
: I e..
~
T
i
UP-
rl
I
O-
DETAIL A
J
t---
ij
F
----_ii ..
.... - ... __ .... - ""'""
~~
o.
~~
~~
0,
~~
O.
02
TLlF/9934 -5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propegation delaya.
Functional Description
Mode Select Table
The 'AC/' ACT169 uses edge-triggered J-K-type flip-flops
and have no constraints on changing the control or data
input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at
least a setup time before the rising edge of the clock and
remain valid for the recommended hold time thereafter. The
parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is
LOW, the data on the PO-P3 inputs enters the flip-flops on
the next rising edge of the Clock. In order for counting to
occur, both CEP and CET must be LOW and PE must be
HIGH; the
input then determines the direction of counting. The Terminal Count (Te) output is normally HIGH and
goes LOW, provided that CET is LOW, when a counter
reaches zero in the Count Down mode or reaches 15 in the
Count Up mode. The TC output state is not a function of the
Count Enable Parallel (CEP) input level. If an illegal state
occurs, the 'AC169 will return to the legitimate sequence
within two counts. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock
signal is not recommended (see logic equations below).
U/O
PE
CEP
CET
L
H
H
H
H
X
X
X
L
L
H
L
L
H
L
X
X
H
X
X
Action on Rising
Clock Edge
Load (P n to an)
Count Up (increment)
Count Down (Decrement)
No Change (Hold)
No Change (Hold)
H = HIGH Voijage Level
L = LOW Voltage Level
X = Immaterial
ufo
State Diagrams
1) Count Enable = CEP-m-PE
- - ... Count Down
2) Up: TC = 00-01-0203-(Up)-CET
3) Down: TC = 00-01-02-03-(Down)-CET
-Count Up
TLlF/9934-6
4-106
....
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
OHlce/Dlstrlbutors for availability and specifications.
DC Input Diode Current (1,K)
V, = -0.5V
V, = Vee + 0.5V
2.0Vto 6.0V
4.5Vto 5.5V
Input Voltage (V,)
-20mA
+20mA
DC Input Voltage (V,)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage (Vecl
'AC
'ACT
-0.5Vto +7.0V
Supply Voltage (Vcc)
-0.5V to to Vee + 0.5V
±50mA
±50mA
Storage Temperature (TSTG)
OVtoVee
Operating Temperature
74AC/ACT
54AC/ACT
-20mA
+20mA
DC Vee or Ground Current
per Output Pin (IcC or IGNO)
OVtoVcc
Output Voltage (VO)
-0.5VtoVee + 0.5V
DC Output Source
or Sink Current (10)
CD
CD
-65'Cto + 150'C
(TAl
-40'Cto +85'C
-55'Cto + 125'C
Minimum Input Edge Rate (aV/at)
'AC Devices
Y,N from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (aV/at)
'ACT Devices
. Y,N from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACnM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-5S'C to + 125'C
TA =
- 40'C to + 85'C
Typ
V,H
V,L
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
lOUT = - 50 /LA
lOUT = 50/LA
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
•All outputs loaded; thresholds on input associated with output under test
tMaximum test duration 2.0 ms, one output loaded at a time.
4-107
·V,N = V,L or V,H
-12mA
-24mA
10H
-24mA
·V,N = V,L or V,H
12mA
24mA
10L
24mA
V, = Vee,GND
•
m
....
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA=
+ 25°C
TA=
-55°C to + 125°C
TA=
-40"Cto +85"C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
80.0
",A
VIN = Vcc
orGND
Maximum Quiescent
5.5
8.0
160.0
Supply Current
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit
Icc for 54AC @ 25'C Is Identical to 74AC @ 25'C.
Icc
@
5.5V Vee.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +25°C
TA =
- 55°C to + 125°C
TA =
- 40°C to + 85°C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
orVcc - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = O.W
orVcc - O.W
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
",A
1.6
1.5
mA
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Icellnput
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
0.001
0.001
Conditions
Guaranteed Limits
0.6
lOUT = -50",A
'VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50 ",A
'VIN = VIL or VIH
24mA
24mA
IOL
VI = Vcc,GND
VI = Vec - 2.W
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
",A
VIN = Vee
orGND
Maximum Quiescent
5.5
8.0
Supply Current
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: Icc for 54ACT @ 25'C is identical to 74ACT @ 25'C.
IcC
Units
4-108
.....
CD
AC Electrical Characteristics:
Symbol
Parameter
Vcc'
(V)
U)
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50 pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to + 85'C
CL = 50pF
Min
Typ
Maximum Clock
Frequency
3.3
5.0
75
100
118
154
tpLH
Propagation Delay
CPtoQn
(PE HIGH or LOW)
3.3
5.0
2.5
1.5
9.5
7.0
13.0
10.0
1.0
1.0
15.0
12.0
2.0
1.5
14.5
11.0
ns
2-3,4
Propagation Delay
CPtoQn
(PE HIGH or LOW)
3.3
5.0
2.5
1.5
10.5
7.5
14.5
11.0
1.0
1.0
16.5
13.0
2.0
1.5
16.0
12.0
ns
2-3,4
tpLH
Propagation Delay
CP to TC
3.3
5.0
4.5
3.0
13.5
9.5
18.0
13.0
1.0
1.0
22.0
16.0
3.5
2.0
22.0
14.0
ns
2-3,4
tpHL
Propagation Delay
CPtoTC
3.3
5.0
3.5
2.5
13.5
9.5
18.0
13.0
1.0
1.0
22.0
16.0
3.0
2.0
20.5
14.5
ns
2-3,4
tpLH
Propagation Delay
CETtoTC
3.3
5.0
3.5
3.0
11.0
8.0
15.0
10.5
1.0
1.0
18.5
13.0
3.0
2.5
16.5
12.0
ns
2-3,4
tpHL
Propagation Delay
CETtoTC
3.3
5.0
3.0
2.0
9.5
7.0
12.5
9.0
1.0
1.0
16.0
11.0
2.5
1.5
14.5
10.0
ns
2-3,4
tpLH
Propagation Delay
U/DtoTC
3.3
5.0
3.5
2.5
11.0
8.0
15.0
10.5
1.0
1.0
18.5
13.0
3.0
2.0
17.0
12.0
ns
2-3,4
Propagation Delay
U/DtoTC
'Voltage Range 3.3 Is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
3.3
5.0
2.5
1.5
10.0
7.0
13.5
9.5
1.0
1.0
16.5 .
12.0
2.0
1.5
15.5
10.5
ns
2-3,4
tpHL
Min
Max
55
75
4-109
Min
Fig.
No.
fmax
tpHL
Max
Units
Max
65
90
MHz
...
I
AC Operating Requirements:
Symbol
Parameter
Vcc·
(V)
See Section 2 for waveforms.
74AC
S4AC
74AC
TA = +25"C
CL = SOpF
TA = -SS·C
to + 125"C
CL = SOpF
TA = -40"C
to +SS·C
CL = SOpF
Typ
Is
Units
Fig.
No.
Guaranteed Minimum
Setup Time,
HIGH or LOW
Pn to CP
3.3
5.0
3.0
1.5
4.5
2.5
7.0
4.5
5.0
2.5
ns
2-7
th
Hold Time, HIGH or LOW
Pn to CP
3.3
5.0
1.5
0.5
0.5
1.5
2.0
2.5
0.5
1.5
ns
2-7
ts
Setup Time,
HIGH or LOW
CEPtoCP
3.3
5.0
7.5
4.5
10.5
7.0
13.5
9.0
12.5
8.0
ns
2-7
th
Hold Time, HIGH or LOW
CEPto CP
3.3
5.0
4.5
2.0
0
0.5
0.5
2.5
0
1.0
ns
2-7
Is
Setup Time,
HIGH or LOW
CETtoCP
3.3
5.0
7.0
4.0
10.0
6.5
13.5
9.5
12.0
8.0
ns
2-7
th
Hold Time, HIGH or LOW
CET to CP
3.3
5.0
6.0
4.0
0
0.5
0.5
2.5
0
1.0
ns
2-7
ts
Setup Time,
HIGH or LOW
PEtoCP
3.3
5.0
3.5
2.0
5.5
3.5
8.5
6.5
6.5
4.0
ns
2-7
th
Hold Time, HIGH or LOW
PE to CP
3.3
5.0
3.5
1.5
0
0.5
0.5
2.0
0
0.5
ns
2-7
ts
Setup Time,
HIGH or LOW
U/OtoCP
3.3
5.0
7.0
4.5
10.0
6.5
13.0
9.0
11.5
7.5
ns
2-7
th
Hold Time, HIGH or LOW
U/OtoCP
3.3
5.0
7.0
4.0
0
0.5
0.5
2.0
0
0.5
ns
2-7
tw
CP Pulse Width,
HIGH or LOW
3.3
5.0
2.0
2.0
3.0
3.0
5.0
5.0
4.0
3.0
ns
2-3
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
4-110
...
Q)
AC Electrical Characteristics:
Symbol
Parameter
Vcc'
(V)
CD
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25'C
Cl = SOpF
TA = -5S'C
to + 12S'C
Cl = SOpF
TA = -40'C
to +8S'C
Cl = 50pF
Min
Typ
Max
Min
Max
Min
Units
Fig.
No.
Max
fmax
Maximum Clock
Frequency
5.0
90
tpLH
Propagation Delay
CPtoO n
(PE HIGH or LOW)
5.0
2.0
6.5
9.0
2.0
10.5
ns
2-3,4
Propagation Delay
CP to On
(PE HIGH or LOW)
5.0
2.0
6.5
9.0
2.0
10.5
ns
2-3,4
tpLH
Propagation Delay
CPtoTC
5.0
3.0
9.0
11.5
3.0
14.0
ns
2-3,4
tpHL
Propagation Delay
CP to TC
5.0
3.0
9.0
11.5
3.0
14.0
ns
2-3,4
tpLH
Propagation Delay
CETto TC
5.0
2.5
7.5
10.0
2.5
11.5
ns
2-3,4
tpHL
Propagation Delay
CETtoTC
5.0
2.5
7.5
10.0
2.5
11.5
ns
2-3,4
tpLH
Propagation Delay
U/D to TC
5.0
2.5
8.0
10.5
2.5
12.0
ns
2-3,4
5.0
2.5
8.0
10.5
2.5
12.0
ns
2-3,4
tpHL
Propagation Delay
U/DtoTC
'Voltage Range 5.0 is 5.0V ±0.5V
tpHL
90
4-111
MHz
AC Operating Requirements:
Symbol
Parameter
Vcc·
(V)
See Section 2 for waveforms
74ACT
S4ACT
74ACT
TA = +2SoC
CL = SOpF
TA = -SsoC
to + 12SoC
CL=SOpF
TA = -40"C
to +8SoC
CL = SOpF
Typ
Units
Fig.
No.
Guaranteed Minimum
Setup Time.
HIGH or LOW
Pn to CP
5.0
2.5
2.5
ns
2-7
th
Hold Time, HIGH or LOW
Pn toCP
5.0
1.5
1.5
ns
2-7
ts
Setup Time,
HIGH or LOW
CEPtoCP
5.0
7.0
7.0
ns
2-7
0
0
ns
2-7
ts
th
Hold Time, HIGH or LOW
CEPtoCP
5.0
Is
SelupTime,
HIGH or LOW
CETtoCP
5.0
7.0
7.0
ns
2-7
Ih
Hold Time, HIGH or LOW
CETtoCP
5.0
0
0
ns
2-7
Is
Setup Time,
HIGH or LOW
PEtoCP
5.0
6.0
6.0
ns
2-7
Ih
Hold Time, HIGH or LOW
PEtoCP
5.0
0.5
0.5
ns
2-7
Is
Setup Time,
HIGH or LOW
u/i5to CP
5.0
7.0
7.0
ns
2-7
Ih
Hold Time, HIGH or LOW
U/DtoCP
5.0
0.5
0.5
ns
2-7
Iw
CP Pulse Width,
HIGH or LOW
5.0
4.0
4.0
ns
2-3
'Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPD
Power Dissipation
Capacitance
60.0
pF
Vee = 5.0V
4-112
,----------------------------------------------------------------------------,
"'"
~National
~ Semiconductor
54AC/74AC174. 54ACT/74ACT174
Hex 0 Flip-Flop with Master Reset
General Description
Features
The 'ACI'ACT174 is a high·speed hex D flip·flop. The de·
vice is used primarily as a 6·bit edge·triggered storage regis·
ter. The information on the D inputs is transferred to storage
during the LOW·to·HIGH clock transition. The device has a
Master Reset to simultaneously clear all flip· flops.
• Outputs source/sink 24 mA
• 'ACT174 has TTL·compatible inputs
• Standard Military Drawing (SMD)
- 'AC174: 5962·87626
- 'ACT174: 5962·87757
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
Mil
CP
cp
--0
MR
TL/F /9935-1
DO
Qo
Mil
1
16
Qo
2
15
Q5
DO
3
14
05
Vcc
01
Q1
01
4
13
04
O2
Q2
5
12
Q4
6
11
03
Q1
O2
03
Q3
Q2
7
10
Q3
04
Q4
GNo
8
9
CP
05
Pin Names
-"
......
Q5
TLiF/9935-3
TL/F/9935-2
Description
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
Pin Assignment
forlCe
Il:z
Q1 NColilo
1IDIlllIDIIDGJ
G~~:O~~
NC [j]
CPIil!
IIINC
@)Vcc
Q3 1Lil
IimQs
~1i]]1i]]1i1l1i]]
~
a. NC 04 Os
TLiF/9935-4
4·113
Functional Description
Truth Table
The 'ACI'ACT174 consists of six edge-triggered D flip-flops
with individual D inputs and Q outputs. The Clock (CP) and
Master Reset (MR) are common to all flip-flops. Each D
input's state is transferred to the corresponding flip-flop's
output following the LOW-to-HIGH Clock (CP) transition. A
LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The 'ACt
'ACT174 is useful for applications where the true output
only is required and the Clock and Master Reset are common to all storage elements.
Inputs
Output
MR
CP
0
Q
L
H
H
H
X
X
.../
.../
L
H
L
L
H
L
X
Q
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
.../" = LOW-ta-HIGH Transition
Logic Diagram
DO
03
00
TLIF19935-5
Please note that this diagram is provided only for the understanding of logiC operations and should not be used to estimate propagation delays.
4-114
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
DC Output Source
or Sink Current (10)
Supply Voltage (Vecl
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (~V I ~t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
-20mA
+20mA
-0.5VtoVee + 0.5V
-20mA
+20mA
-0.5V to to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
PDIP
Minimum Input Edge Rate
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
±50mA
- 65'C to + 150'C
2.0Vto 6.0V
4.5Vt05.5V
OVtoVee
OVtoVee
-40'C to +85'C
-55'C to + 125'C
125 mV/ns
(~V/~t)
125 mV/ns
175'C
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FAcnM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = O.W
or Vee - O.W
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.W
or Vee - O.W
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
lOUT = - 50 /LA
lOUT = 50/LA
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
'All outputs loaded; thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
4·115
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
'VIN = VILorVIH
12mA
24mA
10L
24mA
VI = Vee,GND
•
•........
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
- 55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.S5V Min
160.0
SO.O
/LA
VIN = Vcc
orGND
Maximum Quiescent
Icc
5.5
S.O
Supply Current
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
Icc for 54AC @ 25'C Is identical to 74AC @ 25'C.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55'C to + 125'C
TA =
- 40'C to + 85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - O.lV
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.S
O.S
O.S
O.S
O.S
O.S
V
VOUT = 0.1V
orVcc - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
/LA
1.6
1.5
mA
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
0.001
0.001
Conditions
Guaranteed Limits
0.6
lOUT = -50/LA
·VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50/LA
'VIN = VIL or VIH
24mA
IOL
24mA
VI = Vcc,GND
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
SO.O
/LA
VIN = Vcc
orGND
Maximum Quiescent
5.5
8.0
Supply Current
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT @ 25'C Is Identical to 74ACT @ 25'C.
Icc
Units
4-116
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50 pF
TA = -40'C
to +85'C
CL = 50pF
Min
Min
Units
Fig.
No.
Min
Typ
fmax
Maximum Clock
Frequency
3.3
5.0
90
100
100
125
tpLH
Propagation Delay
CP to On
3.3
5.0
2.0
1.5
9.0
6.0
11.5
8.5
1.0
1.0
14.0
10.5
1.5
1.0
12.5
9.5
ns
2-3,4
tpHL
Propagation Delay
CP to On
3.3
5.0
2.0
1.5
8.5
6.0
11.0
8.0
1.0
1.0
13.0
10.0
1.5
1.0
12.0
9.0
ns
2-3,4
Propagation Delay
MRtoOn
'Voltage Range S.S is S.SV ±O.SV
Voltage Range 5.0 is 5.0V ±0.5V
3.3
5.0
2.5
1.5
9.0
7.0
11.5
9.0
1.0
1.0
13.5
11.0
2.0
1.5
12.5
10.5
ns
2-3,4
tpHL
AC Operating Requirements:
Max
Max
65
90
MHz
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to + 65'C
CL = 50pF
Units
Fig.
No.
7.0
5.5
ns
2-7
3.0
3.0
3.0
3.0
ns
2-7
5.5
5.0
7.0
5.0
7.0
5.0
ns
2-3
1.0
1.0
5.5
5.0
7.0
5.0
7.0
5.0
ns
2-3
0
0
2.5
2.0
3.0
2.0
2.5
2.0
ns
2-3,7
Parameter
Vee'
(V)
ts
Setup Time, HIGH or LOW
Dn toCP
3.3
5.0
2.5
2.0
6.5
5.0
7.5
5.5
th
Hold Time, HIGH or LOW
Dn toCP
3.3
5.0
1.0
0.5
3.0
3.0
tw
MR Pulse Width, LOW
3.3
5.0
1.0
1.0
tw
CP Pulse Width
3.3
5.0
tree
Recovery Time
MRtoCP
3.3
5.0
Symbol
Max
70
100
Typ
Guaranteed Minimum
'Voltage Range S.S Is S.SV ±O.SV
Voltage Range S.O Is S.OV ±O.SV
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50 pF
Min
Min
Min
Typ
Max
Max
Units
Fig.
No.
Max
fmax
Maximum Clock
Frequency
5.0
165
200
tpLH
Propagation Delay
CPtoOn
5.0
1.5
7.0
10.5
1.0
12.5
1.5
11.5
ns
2-3,4
tpHL
Propagation Delay
CPtoO n
5.0
1.5
7.0
10.5
1.0
13.0
1.5
11.5
n5
2-3,4
5.0
1.5
6.5
9.5
1.0
12.0
1.5
11.0
ns
2-3,4
Propagation Delay
MRtoOn
'Voltage Range 5.0 is 5.0V ± O.SV
tpHL
140
95
4-117
MHz
AC Operating Requirements:
Symbol
Parameter
See Section 2 for waveforms
Vee'
(V)
74ACT
54ACT
74ACT
TA = +25"C
CL = 50pF
TA = -55"C
to + 125"C
CL=50pF
TA = -40"C
to +85"C
CL = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
0.5
1.5
3.0
1.5
ns
2-7
th
Hold Time, HIGH or LOW
Dn to CP
5.0
1.0
2.0
2.0
2.0
ns
2-7
tw
MR Pulse Width, LOW
5.0
1.5
3.0
5.0
3.5
ns
2-3
tw
CP Pulse Width, HIGH OR LOW
5.0
1.5
3.0
5.0
3.5
ns
2-3
tree
Recovery Time
MRtoCP
5.0
-1.0
0.5
1.0
0.5
ns
2-3,7
'Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
85.0
pF
Vee = 5.0V
I
4-118
r----------------------------------------------------------------------------, ........
U1
~National
~ Semiconductor
54AC/74AC175. 54ACT/74ACT175
Quad 0 Flip-Flop
General Description
Features
The 'AC/'ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D
inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW.
•
•
•
•
•
•
•
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
Asynchronous common reset
True and complement output
Outputs source/sink 24 mA
'ACT175 has TTL-compatible inputs
Standard Military Drawing (SMD)
- 'AC175: 5962-89552
- 'ACT175: 5962-89693
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
CP
i.1R
16
Vee
-<> MR
00
15
03
00
14
°0
03
03
1
0,
7
13
12
11
10
GNO
8
9
°1
01
TL/F/9936-1
6
°2
O2
°2
CP
IEEE/IEC
TL/F/9936-3
i.1R
CP
Pin Assignment
forLCC
00
00
o,O,NClloiio
rnHil [[I [[I m
00
G~~O~~
0,
0,
0,
°2
°2
ilz
03
Do-Ds
CP
MR
QO-Q3
Cio-Ci3
[i]NC
CPIl]j
0zliID
I1f!vee
!iID03
03
~1iID1iID1iZl1iID
il3
OzDzNC~Q3
TL/F/9936-2
Pin Names
NCIl]
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
4-119
TL/F/9936-4
II
.."
.....
.....
Functional Description
Truth Table
The 'ACI'ACT175 consists of four edge-triggered D flipflops with individual D inputs and Q and Q outputs. The
Clock and Master Reset are common. The four flip-flops will
store the state of their individual D inputs on the LOW-toHIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will
force all Q outputs LOW and Q outputs HIGH independent
of Clock or Data inputs. The' ACI' ACT175 is useful for general logic applications where a common Master Reset and
Clock are acceptable.
Inputs
Outputs
@tn,MR = H
@tn+1
On
Qn
On
L
H
L
H
H
L
H ~ HIGH Vollage Level
L ~ LOW Voltage Level
tn ~ Bit TIme before Clock Pulse
tn + 1 ~ Bit Time after Clock Pulse
Logic Diagram
i.iR
01
CP
o
o
'-----_---+-----t_---+_-----
TC
CLOCK---....--------~~--------...- - - - TLlF/9940-9
FIGURE C. Synchronous N·Stage Counter with Parallel Gated Carry/Borrow
4-127
~
0)
~
,----------------------------------------------------------------------------------------------,
Logic Diagram
TL/F/9940-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-128
.....
.....
(I)
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (10)
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (I1V/l1t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V 4.5V, 5.5V
Minimum Input Edge Rate (I1V/l1t)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V. 5.5V
-20mA
+20mA
-0.5VtoVee + 0.5V
-20mA
+20mA
-0.5V to to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (lee or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
PDIP
2.0Vto 6.0V
Supply Voltage (Vecl
OVtoVee
OVtoVee
-40'Cto +85'C
- 55'C to + 125'C
125 mV/ns
125 mV/ns
±50mA
-65'C to + 150'C
175'C
140'C
Note 1: Absolute maximum ratings arB those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, output/input loading variables. National does not recommend
operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
-All outputs loaded; thresholds on input associated with output under test.
tMaximum test dUration 2.0 m5, one output loaded at a time.
4-129
lOUT = -50/LA
'VIN = VILorVIH
-12mA
-24mA
10H
-24mA
lOUT = 50/LA
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee. GND
,....
,....
G)
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + 125'C
TA=
- 40"C to + 85'C
Typ
IOLD
IOHD
ICC
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
p.A
VIN = VCC
orGND
5.5
8.0
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ S.SV Vee.
Icc for S4AC @ 2S'C is identical to 74AC @ 2S·C.
AC Electrical Characteristics:
Symbol
Parameter
Vee·
(V)
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to + 85'C
CL = 50pF
Min
Typ
Max
Min
Max
Fig.
No.
Max
f max
Maximum Count
Frequency
3.3
5.0
70
90
105
133
tpLH
Propagation Delay
CP to Qn
3.3
5.0
2.0
1.5
8.5
6.0
15.0
11.0
1.0
1.0
16.5
12.0
1.5
1.5
16.0
12.0
ns
2-3,4
tpHL
Propagation Delay
CP to Qn
3.3
5.0
2.5
1.5
8.5
6.0
14.5
10.5
1.0
1.0
16.0
12.0
2.0
1.5
16.0
11.5
ns
2-3,4
tPLH
Propagation Delay
CP to TC
3.3
5.0
3.5
2.5
10.5
7.5
18.0
12.0
1.0
1.0
19.5
14.0
2.5
1.5
20.0
14.0
ns
2-3,4
tpHL
Propagation Delay
CP to TC
3.3
5.0
4.0
2.5
10.5
7.5
17.5
12.5
1.0
1.0
19.0
14.5
3.0
2.0
19.0
13.5
ns
2·3,4
tpLH
Propagation Delay
CPtoRC
.3.3
5.0
2.5
2.0
7.5
5.5
12.0
9.5
1.0
1.0
14.0
10.5
2.0
1.0
13.5
10.5
ns
2·3,4
tpHL
Propagation Delay
CPtoRC
3.3
5.0
2.5
1.5
7.0
5.0
11.5
8.5
1.0
1.0
12.5
9.5
2.0
1.0
12.5
9.5
ns
2·3,4
tpLH
Propagation Delay
CEtoRC
3.3
5.0
2.5
1.5
7.0
5.0
12.0
8.5
1.0
1.0
14.0
10.0
1.5
1.0
13.5
9.5
ns
2·3,4
tpHL
Propagation Delay
CEtoRC
3.3
5.0
2.0
1.5
6.5
5.0
11.0
8.0
1.0
1.0
12.5
9.5
1.5
1.0
12.5
9.0
ns
2·3,4
Propagation Delay
U/DtoRC
3.3
5.0
2.5
1.5
6.5
5.0
12.5
9.0
1.0
1.0
14.5
11.0
2.0
1.0
14.5
10.0
ns
2·3,4
tpHL
Propagation Delay
U/DtoRC
3.3
5.0
2.5
1.5
7.0
5.0
12.0
8.5
1.0
1.0
15.0
11.0
2.0
1.0
13.5
10.0
ns
2·3,4
tpLH
Propagation Delay
U/DtoTC
3.3
5.0
2.0
1.5
7.0
5.0
11.5
8.5
1.0
1.0
14.0
13.5
1.5
1.0
13.5
9.5
ns
2·3,4
Propagation Delay
3.3
5.0
2.0
1.5
6.5
5.0
11.0
8.5
1.0
1.0
13.5
10.0
1.5
1.0
12.5
9.5
ns
2·3,4
3.3
5.0
2.5
2.0
8.0
5.5
13.5
9.5
1.0
1.0
16.5
11.5
2.0
1.0
15.5
10.5
ns
2·3,4
tpLH
tpHL
U/DtoTC
Propagation Delay
PntoQn
'Voltage Range 3.3 Is 3.3V ±0.3V
Voltage Range S.O is S.OV ± O.SV
tpLH
55
80
Min
Units
4·130
65
85
MHz
AC IElectrical Characteristics:
....
....
CD
See Section 2 for waveforms (Continued)
74AC
54AC
74AC
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to + 85'C
Cl = 50pF
Units
Fig.
No.
14.5
10.5
ns
2-3,4
2.5
1.0
17.5
10.5
ns
2-3,4
2.0
1.5
15.5
11.0
ns
2-3,4
Parameter
Vee'
(V)
Min
Typ
Max
Min
Max
Min
Max
tpHL
Propagation Delay
Pn to On
3.3
5.0
2.5
1.5
7.5
5.5
13.0
9.5
1.0
1.0
15.5
10.5
1.5
1.0
tpLH
Propagation Delay
PL to On
3.3
5.0
3.5
2.0
9.5
5.5
14.5
9.5
1.0
1.0
lB.O
12.5
Propagation Delay
PLtoO n
'Voltage Range 3.3 Is 3.3V ±0.3V
Voltage Range 5.0 Is 5.0V ±0.5V
3.3
5.0
3.0
2.0
B.O
6.0
13.5
10.0
1.0
1.0
15.5
11.5
Symbol
tpHL
AC Operating Requirements:
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
Cl = SOpF
TA = -SS'C
to + 12S'C
Cl = SOpF
TA = -40'C
to +8S'C
Cl = SOpF
Units
Fig.
No.
3.0
2.5
ns
2-7
1.5
2.0
1.0
1.0
ns
2-7
6.0
4.0
9.0
6.0
7.0
4.5
ns
2-7
-4.0
-2.5
-0.5
0
0
0.5
-0.5
0
ns
2-7
3.3
5.0
4.0
2.5
B.O
5.5
10.5
7.5
9.0
6.5
ns
2-7
3.3
5.0
-5.0
-3.0
0
0.5
0
1.0
0
0.5
ns
2-7
Parameter
Vee'
(V)
ts
Setup Time, HIGH or LOW
Pn to PL
3.3
5.0
1.0
0.5
3.0
2.0
4.0
3.0
th
Hold Time, HIGH or LOW
PntoPL
3.3
5.0
-1.5
-0.5
0.5
1.0
ts
Setup Time, LOW
CE to CP
3.3
5.0
3.0
1.5
th
Hold TIme, LOW
CEtoCP
3.3
5.0
Setup Time, HIGH or LOW
Symbol
Typ
ts
U/D to CP
Hold Time, HIGH or LOW
th
U/D to CP
Guaranteed Minimum
tw
PL Pulse Width, LOW
3.3
5.0
2.0
1.0
3.5
1.0
5.0
5.0
4.0
1.0
ns
2-3
tw
CP Pulse Width, LOW
3.3
5.0
2.0
2.0
3.5
3.0
6.0
6.0
4.0
4.0
ns
2-3
tree
Recovery Time
PL toCP
3.3
5.0
-0.5
-1.0
0
0
1.5
1.0
0
0
ns
2-3,7
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± o.sv
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
CPO
Power Dissipation
Capacitance
75.0
pF
4-131
Conditions
Vee
Vee
= 5.0V
= 5.0V
•
~Nat1onal
~ Semiconductor
54AC/74AC240 • 54ACT /7 4ACT240
Octal Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The 'AC/'ACT240 is an octal buffer and line driver designed
to be employed as a memory address driver, clock driver
and bus oriented transmitter or receiver which provides improved PC board density.
• Inverting TRI-STATE outputs drive bus lines or buffer
memory address registers
• Outputs source/sink 24 mA
• 'ACT240 has TTL-compatible inputs
II Standard Military Drawing (SMD)
- 'AC240: 5962-87550
- 'ACT240: 5962-87759
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEE/IEC
0E1
10
11
12
13
Pin Assignment
for LCC and PCC
Pin Assignment
for DIP, Flatpak and SOIC
20
OE,
00
10
°1
°4
11
°2
03
19
18
17
Os
13
14
15
°s
Is
°6
17
°7
°4
0E2
00
°7
GND
rn
07 [[J
GND [QJ
17 Ii]
14
16
0,
15
15
14
°2
13
Is
12
03
11
17
°s
12
0E2
13 Os 12 0 s 11
[I] [I] [I] I]][!]
Vee
04
[]] 10
OJ 0E 1
~Vcc
°3 1ll1
IS Ii]
liE 0E2
1Bl[ID[§JIl1I[§J
02 15 0, 14 00
TL/F/9941-S
TLIF 19941-2
TL/F/9941-1
Truth Tables
Pin Names
OE1,OE2
10-17
00-0 7
Description
Inputs
TRI-STATE Output Enable Inputs
Inputs
Outputs
OE,
In
L
L
H
L
H
Outputs
(Pins 12, 14, 16, 18)
H
L
Z
X
Inputs
L
L
H
= HIGH Voltage Level
= LOW Voltage Level
= Immaterial
Z = High Impedance
H
L
X
4-132
Outputs
(Pins 3, 5, 7, 9)
L
H
X
H
L
Z
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VeC>
DC Input Diode Current (1,K)
V, = -0.5V
V, = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (V,)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage (VeC>
'AC
'ACT
-0.5Vto +7.0V
2.0Vt06.0V
4.5Vto 5.5V
Input Voltage (V,)
OVtoVee
Output Voltage (Vo)
OVtoVee
Operating Temperature (TA)
74AC/ACT
-0.5VtoVee + 0.5V
-40·C to + 85·C
-55·Cto + 125·C
54AC/ACT
-20mA
+20mA
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
±50mA
Storage Temperature (TSTG)
-65·Cto +150·C
Minimum Input Edge Rate (tN I At)
'AC Devices
Y,N from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (A V I At)
'ACT Devices
Y,N from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
175·C
CDIP
PDIP
140·C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design Is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vec
(V)
TA
=
+25·C
Typ
V,H
V,L
VOH
liN
74AC
TA =
- 40·C to + 85·C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
,..A
3.0
4.5
5.5
VOL
54AC
TA =
- 55·C to + 125·C
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
"All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-133
lOUT
= -50,..A
·V,N
= V,L or V,H
IOH
-12mA
-24mA
-24mA
lOUT
= 50,..A
·V,N
= VILorV,H
10L
VI
12mA
24mA
24mA
= Vee,GND
II
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25"C
TA=
-55"C to + 125'C
TA=
- 40'C to + 85'C
Typ
loz
IOLD
IOHD
Maximum TRI·STATE
Leakage Current
tMlnlmum Dynamic
Output Current
5.5
Units
Conditions
Guaranteed Limits
±0.5
±10.0
±5.0
Il-A
VI (OE) = VIL, VIH
VI = Vcc,GND
Vo = Vcc,GND
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.85V Min
80.0
Il-A
VIN = Vee
orGND
Maximum Quiescent
5.5
8.0
160.0
Supply Current
•All outputs loaded; thresholds on Input associated with output under tesl
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: liN and lee @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
Icc for 54AC @ 25'C Is Identical to 74AC @ 25'C.
IcC
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55"Cto + 125'C
TA =
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVce - O.IV
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = O.IV
or Vee - o.tv
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
Il-A
loz
Maximum TRI·STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
Il-A
leCT
Maximum
Iccllnput
5.5
1.6
1.5
mA
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.6
lOUT = -50 Il-A
·VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50 Il-A
·VIN = VIL or VIH
24mA
IOL
24mA
VI = Vce,GND
VI = VIL, VIH
Vo = Vee,GND
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vee
orGND
5.5
8.0
•All outputs loaded; thresholds on Input associated with output under teal
tMaximum test duration 2.0 ms. one output loaded at a Ume.
Note: Icc for 54ACT @ 25'C is identical to 74ACT @ 25'C.
4·134
AC Electrical Characteristics:
Vee·
(V)
Parameter
Symbol
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50 pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
Data to Output
3.3
5.0
1.5
1.5
6.0
4.5
8.0
6.5
1.0
1.0
11.0
8.5
1.0
1.0
9.0
7.0
ns
2·3,4
tpHL
Propagation Delay
Data to Output
3.3
5.0
1.5
1.5
5.5
4.5
8.0
6.0
1.0
1.0
10.5
8.0
1.0
1.0
8.5
6.5
ns
2·3,4
tpZH
Output Enable Time
3.3
5.0
1.5
1.5
6.0
5.0
10.5
7.0
1.0
1.0
11.5
9.0
1.0
1.0
11.0
8.0
ns
2·5
tpZL
Output Enable Time
3.3
5.0
1.5
1.5
7.0
5.5
10.0
8.0
1.0
1.0
13.0
10.5
1.0
1.0
11.0
8.5
ns
2·6
tpHZ
Output Disable Time
3.3
5.0
1.5
1.5
7.0
6.5
10.0
9.0
1.0
1.0
12.5
10.5
1.0
1.0
10.5
9.5
ns
2-5
tpLZ
Output Disable Time
3.3
5.0
1.5
1.5
7.5
6.5
10.5
9.0
1.0
1.0
13.5
11.0
1.0
1.0
11.5
9.5
ns
2-6
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V ± O.SV
'Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics:
Symbol
Vee·
(V)
Parameter
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
Cl = 50 pF
TA = -40'C
to + 85'C
Cl = 50pF
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
Data to Output
5.0
1.5
6.0
8.5
1.0
9.5
1.5
9.5
ns
2-3,4
tpHL
Propagation Delay
Data to Output
5.0
1.5
5.5
7.5
1.0
9.0
1.5
8.5
ns
2-3,4
tPZH
Output Enable Time
5.0
1.5
7.0
8.5
1.0
10.0
1.0
9.5
ns
2-5
tPZL
Output Enable Time
5.0
2.0
7.0
9.5
1.0
11.5
1.5
10.5
ns
2-6
tpHZ
Output Disable Time
5.0
2.0
8.0
9.5
1.0
11.0
2.0
10.5
ns
2-5
tpLZ
Output Disable Time
5.0
2.5
6.5
10.0
1.0
11.5
2.0
10.5
ns
2-6
'Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
Vee
=
5.0V
CPO
Power Dissipation
Capacitance
45.0
pF
Vee
=
5.0V
4-135
Conditions
•
~ .-----------------------------------------------------------------------~
'Oil'
N
~National
~ Semiconductor
54AC/74AC241 • 54ACT /7 4ACT241
Octal Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The' ACI' ACT241 is an octal buffer and line driver designed
to be employed as a memory address driver, clock driver
and bus-oriented transmitter or receiver which provides improved PC board density.
• Non-inverting TRI-STATE outputs drive bus lines or
buffer memory address registers
• Outputs source/sink 24 rnA
• 'ACT241 has TTL-compatible inputs
• Standard Military Drawing (SMD)
- 'AC241: 5962-87551
- 'ACT241: 5962-89847
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
20
0E1
19
10
18
13 06 12 05 11
[IJ[Il ([J lID m
Vee
OE2
°5
12
Os
13
°7
GND
°6
[IJ°4
[II 10
°7rI1
GNDilQJ
171TI1
°31i11
IsJi])
°0
17
14
16
°1
15
Is
14
°2
13
Is
12
°3
11
17
°4
11
°4
05
Pin Assignment
for LCC and PCC
m0E1
~Vee
Ii]JOE2
Ii]]lrnli]!@1i]!
02 Is 01 14 00
TL/F/9942-3
TLiF/9942-1
°7
TL/F/9942-2
Truth Tables
Pin
Names
Description
OE1,
OE2
10-17
0 0- 0 7
TRI-STATE Output Enable Input
TRI-STATE Output Enable Input (Active HIGH)
Inputs
Outputs
Inputs
Outputs
(Pins 12, 14, 16, 18)
L
L
L
L
H
H
X
H
Z
Inputs
H
L
H
H
L
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
4-136
Outputs
(Pins 3, 5, 7, 9)
L
H
Z
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
-0.5Vto +7.0V
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
DC Output Source
or Sink Current (10)
DC Vee or Ground Current
per Output Pin (lee or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
PDIP
Supply Voltage (Vecl
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (Tpj
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (AV/ dt)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (AV I At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
-20mA
+20mA
-0.5V to Vee + 0.5V
-20mA
+20mA
-0.5V to to Vee + 0.5V
±50mA
±50mA
- 65'C to + 150'C
2.0Vt06.0V
4.5Vto 5.5V
OVtoVee
OVtoVee
-40'Cto + 85'C
-55'C to + 125'C
125 mV/ns
125mV/ns
175'C
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply.
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
= +25'C
Typ
VIH
VIL
VOH
liN
74AC
TA =
-40'C to +85'C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
p.A
3.0
4.5
5.5
VOL
54AC
TA =
-55'C to + 125'C
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
... All outputs loaded; thresholds on input associated with output under test.
tMaximum lesl duration 2.0 ms. one oulpul loaded al a lime.
4-137
lOUT
= -50 p.A
·VIN
= VIL or VIH
10H
-12mA
-24mA
-24mA
lOUT
= 50 p.A
·VIN
= VIL or VIH
10L
VI
12mA
24mA
24mA
= Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25°C
TA=
-55°C to + 125"C
TA=
- 40"C to + 85°C
Typ
loz
10LD
10HD
Icc
Maximum TRI-STATE
Leakage Current
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Conditions
Guaranteed Limits
±0.5
5.5
Units
±10.0
±5.0
/LA
VI (OE) = VIL, VIH
VI = Vcc,GND
Vo = Vcc,GND
5.5
50
75
rnA
VOLD = 1.65V Max
5.5
-50
-75
rnA
VOHD = 3.S5V Min
160.0
SO.O
/LA
VIN = Vcc
orGND
5.5
S.O
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
Icc for 54AC @ 25'C is identical to 74AC @ 25'C.
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +25°C
TA =
-55°C to + 125°C
TA =
- 40"C to + 85°C
Units
Conditions
Guaranteed Limits
Typ
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
orVcc - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.S
O.S
O.S
O.S
O.S
O.S
V
VOUT = O.W
orVCC - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.S6
4.S6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
10L
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = -50/LA
'VIN = VIL orVIH
-24 rnA
10H
-24 rnA
lOUT = 50/LA
'VIN = VILorVIH
24mA
24 rnA
liN
Maximum Input
Leakage Current
5.5
iO.1
i1.0
i1.0
/LA
VI = Vee,GND
10Z
Maximum TRI-STATE
Leakage Current
5.5
iO.5
i10.0
i5.0
/LA
VI = VIL,VIH
Vo = VcC,GND
ICCT
Maximum
Icc/Input
5.5
1.6
1.5
rnA
10LD
tMinimum Dynamic
Output Current
10HD
Icc
Maximum Quiescent
Supply Current
0.6
VI = Vce - 2.1V
5.5
50
75
rnA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.S5V Min
160.0
SO.O
/LA
VIN = Vce
orGND
5.5
S.O
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT @ 25'C Is identical to 74ACT @ 25'C.
4-13S
AC Electrical Characteristics:
Symbol
Vee'
Parameter
(V)
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl=50pF
TA = -40'C
to +85'C
Cl = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
Data to Output
3.3
5.0
1.5
1.5
6.0
5.0
9.0
7.0
1.0
1.0
12.0
9.5
1.5
1.0
10.0
7.5
ns
2-3,4
tpHL
Propagation Delay
Data to Output
3.3
5.0
1.5
1.5
6.0
4.5
9.0
7.0
1.0
1.0
11.5
9.0
1.0
1.0
10.5
7.5
ns
2-3,4
tPZH
Output Enable Time
3.3
5.0
1.5
1.5
6.5
5.5
12.5
9.0
1.0
1.0
13.0
10.0
1.0
1.0
13.0
9.5
ns
2-5
tPZL
Output Enable Time
3.3
5.0
1.5
1.5
7.0
5.5
12.0
9.0
1.0
1.0
13.0
10.0
1.5
1.0
13.0
9.5
ns
2-6
tpHZ
Output Disable Time
3.3
5.0
2.0
1.5
8.0
6.5
12.0
10.0
1.0
1.0
13.0
11.5
2.0
1.0
12.5
10.5
ns
2-5
tpLZ
Output Disable Time
3.3
5.0
1.5
1.5
7.0
6.0
12.5
10.0
1.0
1.0
13.0
11.5
1.0
1.0
13.5
10.5
ns
2-6
Units
Fig.
No.
'Voltage Range 3.3 Is 3.3V ± 3.3V
Voltage Range 5.0 Is 5.0V ± 0.5V
AC Electrical Characteristics:
Symbol
Vee'
Parameter
(V)
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Min
Typ
Max
Min
Max
Min
Max
5.0
1.5
6.5
9.0
1.0
10.0
1.5
10.0
ns
2-3,4
5.0
1.5
7.0
9.0
1.0
10.0
1.5
10.0
ns
2-3,4
Output Enable TIme
5.0
1.5
6.0
9.0
1.0
11.5
1.0
10.0
ns
2-5
Output Enable Time
5.0
1.5
7.0
10.0
1.0
12.5
1.5
11.0
ns
2-6
tpHZ
Output Disable Time
5.0
1.5
8.0
10.5
1.0
12.5
1.5
11.5
ns
2-5
tpLZ
Output Disable Time
5.0
2.0
7.0
10.5
1.0
12.5
1.5
11.5
ns
2-6
tpLH
Propagation Delay
Data to Output
tpHL
Proragation Delay
Data to Output
tPZH
tPZL
'Voltage Range 5.0 is 5.0V ± O.5V
Capacitance
Parameter
Typ
Units
Conditions
CIN
Symbol
Input Capacitance
4.5
pF
Vee = 5.0V
Cpo
Power Dissipation
Capacitance
45.0
pF
Vee = 5.0V
4-139
III
~National
Semiconductor
54AC/74AC244 • 54ACT /7 4ACT244
Octal Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The'AC/' ACT244 is an octal buffer and line driver designed
to be employed as a memory address driver, clock driver
and bus-oriented transmitter/receiver which provides improved PC board density.
• TRI-STATE outputs drive bus lines or buffer memory
address registers
• Outputs source/sink 24 mA
• 'ACT244 has TTL-compatible inputs
• Standard Military Drawing (SMD)
- 'AC244: 5962-87552
- 'ACT244: 5962-87760
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEE/IEC
OE,
EN
-OE,
I>
10 1,12 13 -
0E2
lo~
-0,
04 4
- 02
115
-03
05"6
12"7
06 8
I>
v-o.
15-
-Os
16 17 -
- 06
~.
....
1
2
v-oo
EN
1.-
Pin Assignment
for LCC and PCC
13 0 6 12 Os I,
[[]11][[]1]]1ll
Pin Assignment
tor DIP, Flatpak and SOIC
13~
07~
GND-
~
~
~
~
......
.r-
-,.
or--
-,.
or--
....::."
.r--
~
1£...,
19
18
17
16
15
'134
~
"YlIf"' ,......-w-
OE2
00
°7 [!]
GNDIiQI
17 Ii]
14
°1
15
°3fi11
16M!
°2
16
12
03
11
17
--=:-:
,,(/f.
-"-'
"""i=-;
l1lil1li
~
1-
rn04
00 10
[j] OE,
~Ycc
1iID0E2
l1li.
[gJB]Jli§lrrnli§l
02 15 0, I. 00
TL/F/994S-S
TL/F/994S-2
-°7
TLlF/994S-1
Truth Tables
Pin Names
'OE,,'OE2
10-17
00-0 7
Outputs
(Pins 12, 14, 16, 18)
Inputs
Description
TRI-STATE Output Enable Inputs·
Inputs
Outputs
OE,
In
L
L
H
L
H
L
H
Z
X
Inputs
H=
L =
X=
Z =
4-140
OE2
In
L
L
H
L
H
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
X
Outputs
(Pins 3, 5,7,9)
L
H
Z
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specIficatIons.
-0.5Vto +7.0V
Supply Voltage (VeC>
DC Input Diode Current (11K)
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (10K)
-20mA
Va = -0.5V
+20mA
Va = Vee + 0.5V
DC Output Voltage (Va)
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (lee or IGND)
-6S'C to + 150'C
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the davice may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
Supply Voltage (VeC>
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (AV/At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.SV, 5.5V
Minimum Input Edge Rate (AV/At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vto 6.0V
4.5Vt05.5V
OVtoVee
OV to Vee
-40'Cto + 85'C
-55'C to + 125'C
125 mV/ns
125 mV/ns
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
=
+25'C
Typ
VIH
VIL
VOH
S4AC
74AC
TA=
-SS'C to + 12S'C
TA =
- 40'C to + 8S'C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3,15
3.8S
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0,1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
±1.0
±1.0
",A
lOUT = -50 ",A
'VIN
3.0
4.5
5.5
VOL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
Maximum Input
±0.1
5.5
Leakage Current
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
liN
4·141
10H
= VIL or VIH
-12mA
-24mA
-24mA
lOUT
= 50 ",A
'VIN
= VIL or VIH
10L
VI
12mA
24mA
24mA
= Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
S4AC
74AC
TA = +25"C
TA=
-SS'C to + 12S'C
TA=
-40'C to + 8S'C
Typ
loz
IOlD
IOHD
Maximum TRI·STATECII>
Current
tMinimum Dynamic
Output Current
5.5
Units
Conditions
Guaranteed Limits
±0.5
±10.0
±5.0
p.A
VI (OE) = Vil. VIH
VI = Vee. VGND
Vo = Vcc.GND
VOlD = 1.65VMax
5.5
50
75
mA
5.5
-50
-75
mA
VOHD = 3.B5V Min
p.A
VIN = Vcc
orGND
Maximum Quiescent
5.5
B.O
160.0
Supply Current
'All outputs loaded; thresholds on input associated with output under test
tMaximum test duration 2.0 me. one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vcc.
Icc for 54AC @ 25'C is Identical to 74AC @ 25'C.
lee
BO.O
DC Characteristics for' ACT Family Devices
74ACT
Symbol
Parameter
Vee
(V)
S4ACT
TA = +25"C
74ACT
TA=
TA=
Units
-S5"Cto + 125"C - 40'C to + 8S'C
Typ
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVCC - 0.1V
Vil
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
O.B
O.B
O.B
O.B
V
Your = 0.1V
orVee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.B6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
liN
Maximum Input Leakage Current 5.5
±0.1
±1.0
±1.0
p.A
VI = Vee.GND
loz
Maximum TRI·STATECII>
Current
5.5
±0.5
±10.0
±5.0
p.A
VI = Vil. VIH
Vo = Vcc.GND
ICCT
Maximum
Icc/Input
5.5
1.6
1.5
mA
IOLD
tMinimum Dynamic
Output Current
4.5
5.5
VOL
IOHD
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
0.6
lOUT = - 50 p.A
'VIN = Vil or VIH
-24mA
IOH
-24mA
lOUT = 50p.A
'VIN = Vil or VIH
24mA
24mA
IOl
VI = Vcc - 2.1V
5.5
50
75
mA
VOlD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
160.0
80.0
p.A
VIN = Vcc
orGND
Maximum Quiescent
5.5
B.O
Supply Current
'All outputs loaded; th~esholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms. one output loaded at a time.
Note: ICC for 54ACT @ 25'C Is Identical to 74ACT @ 25'C..
Icc
4·142
AC Electrical Characteristics:
Vee'
(V)
Parameter
Symbol
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25°C
CL = 50pF
TA = -55°C
to + 125°C
Cl = 50pF
TA = -40°C
to +85°C
Cl = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
Data to Output
3.3
5.0
2.0
1.5
6.5
5.0
9.0
7.0
1.0
1.0
12.5
9.5
1.5
1.0
10.0
7.5
ns
2-3,4
tpHL
Propagation Delay
Data to Output
3.3
5.0
2.0
1.5
6.5
5.0
9.0
7.0
1.0
1.0
12.0
9.0
2.0
1.0
10.0
7.5
ns
2-3,4
tPZH
Output Enable Time
3.3
5.0
2.0
1.5
6.0
5.0
10.5
7.0
1.0
1.0
11.5
9.0
1.5
1.5
11.0
8.0
ns
2·5
tPZL
Output Enable Time
3.3
5.0
2.5
1.5
7.5
5.5
10.0
8.0
1.0
1.0
13.0
10.5
2.0
1.5
11.0
8.5
ns
2-6
tpHZ
Output Disable Time
3.3
5.0
3.0
2.5
7.0
6.5
10.0
9.0
1.0
1.0
12.5
10.5
1.5
1.0
10.5
9.5
ns
2-5
tpLZ
Output Disable Time
3.3
5.0
2.5
2.0
7.5
6.5
10.5
9.0
1.0
1.0
13.0
11.0
2.5
2.0
11.5
9.5
ns
2-6
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range S.O is S.OV ±O.SV
AC Electrical Characteristics:
Vee'
(V)
Parameter
Symbol
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25°C
Cl = 50pF
TA = -55"C
to + 125°C
Cl=50pF
TA = -40°C
to +85°C
Cl = 50pF
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
Data to Output
5.0
2.0
6.5
9.0
1.0
10.0
1.5
10.0
ns
2-3,4
tpHL
Propagation Delay
Data to Output
5.0
2.0
7.0
9.0
1.0
10.0
1.5
10.0
ns
2-3,4
tPZH
Output Enable Time
5.0
1.5
6.0
8.5
1.0
9.5
1.0
9.5
ns
2·5
tPZL
Output Enable Time
5.0
2.0
7.0
9.5
1.0
11.0
1.5
10.5
ns
2·6
tpHZ
Output Disable Time
5.0
2.0
7.0
9.5
1.0
11.0
1.5
10.5
ns
2-5
tpLZ
Output Disable Time
5.0
2.5
7.5
10.0
1.0
11.5
2.0
10.5
ns
2·6
'Voltage Range S.O is S.OV ± o.sv
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPD
Power Dissipation
Capacitance
45.0
pF
4-143
Vee = 5.0V
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
~
N
~National
~ Semiconductor
54AC/74AC245 • 54ACT/7 4ACT245
Octal Bidirectional Transceiver
with TRI-STATE® Inputs/Outputs
General Description
Features
The 'AC/'ACT245 contains eight non-inverting bidirectional
buffers with TRI-STATE outputs and is intended for bus-oriented applications. Current sinking capability is 24 mA at
both the A and B ports. The Transmit/Receive (T/R) input
determines the direction of data flow through the bidirectional transceiver. Transmit (active-HIGH) enables data
from A ports to B ports; Receive (active-LOW) enables data
from B ports to A ports. The Output Enable input, when
HIGH, disables both A and B ports by placing them in a
HIGH Z condition.
•
•
•
•
•
Noninverting buffers
Bidirectional data path
A and B outputs source/sink 24 mA
'ACT245 has TIL-compatible inputs
Standard Military Drawing (SMD)
- 'AC245: 5962-87758
- 'ACT245: 5962-87663
Ordering Code: See Section 8
Connection Diagrams
Logic Symbols
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
OE
T/ii
T/ii
An
BO
TL/F/9944-1
Pin
Names
Description
Output Enable Input
Transmit/Receive Input
Side A TRI-STATE
Inputs or TRI-STATE
Outputs
Side B TRI-STATE
Inputs orTRI-STATE
Outputs
OE
T/R
Ao-A7
Bo-B7
A,
B,
A2
B2
A3
B3
A4
B4
As
Bs
As
Bs
B7
A7
TL/F/9944-2
TL/F/9944-3
Pin Assignment
for LCC and PCC
Truth Table
As As A4 A3 A2
Inputs
OE
T/R
L
L
H
L
H
X
[[J[I][[J[I\[IJ
Outputs
A7
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
GND
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X = Immaterial
m
lim
mAl
Irl'\l'fffl-flfl't1'Hl1\;11l1"'-1 [IJ Ao
B7 Ii]
OJ T/ii
8s llil
§Q] vee
8s 1iA1
lj]JiiE
1l][iIDil]JIilIil]J
84 83 82 B, Bo
TL/F/9944-4
4-144
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Ved
-0.5Vto +7.0V
DC Input Diode Current (1110
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (laid
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
DC Output Source
or Sink Current (10)
Supply Voltage (Ved
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TA)
74AC/ACT
-20mA
+20mA
-0.5V to Vee + 0.5V
OVtoVee
OVtoVee
-40'Cto +85'C
- 55'C to + 125'C
54AC/ACT
-20mA
+20mA
-0.5V to to Vee + 0.5V
Minimum Input Edge Rate (a VI at)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (aV/at)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
±50mA
DC Vee or Ground Current
per Output Pin (ICC or IGNO)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
PDIP
2.0Vt06.0V
4.5Vt05.5V
±50mA
- 65'C to + 150'C
125 mV/ns
125 mV/ns
175'C
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA = +25'C
Typ
VIH
VIL
VOH
liN
74AC
TA=
-55'C to + 125'C
TA =
-40'Cto + 85'C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
3.0
4.5
5.5
VOL
54AC
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
tAil outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-145
lOUT =
-50/LA
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50/LA
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee, GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
- 55'C to + 125'C
TA=
-40'Cto +85'C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Icc
Maximum Quiescent
Supply Current
IOZT
Maximum I/O
Leakage Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
5.5
B.O
160.0
BO.O
/LA
VIN = Vee
orGND
5.5
±0.6
±11.0
±6.0
/LA
VI(OE) = VIL, VIH
VI = Vcc,GND
Vo = Vee,GND
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit
Icc for 54AC @ 25'C is identical to 74AC @ 25'C.
@
5.5V Vee.
DC Characteristics for' ACT Family Devices
74ACT
Symbol
Parameter
Vee
(V)
54ACT
TA = +25'C
74ACT
TA=
TA =
Units
-55'C to + 125'C - 40'C to + 85'C
Typ
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4,5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
orVcc - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
lOUT = 50 !LA
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
IOL
±0.1
±1.0
±1.0
/LA
1.6
1.5
mA
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input Leakage Current
5.5
ICCT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
IOZT
Maximum I/O
Leakage Current
0.001
0.001
0.6
lOUT = -50/LA
'VIN = VIL or VIH
-24mA
IOH
-24mA
'VIN = VILorVIH
24mA
24mA
VI = Vcc,GND
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.85V Min
5.5
8.0
160.0
80.0
/LA
VIN = Vcc
orGND
5.5
±0.6
±11.0
±6.0
/LA
VI (OE) = VIL, VIH
VI = Vcc,GND
Vo = Vcc,GND
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT @ 25'C is identical to 74ACT @ 25'C.
4-146
AC Electrical Characteristics:
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
9.0
7.0
ns
2-3,4
1.0
1.0
9.0
7.0
ns
2-3,4
13.5
10.0
2.0
1.0
12.5
9.0
ns
2-5
1.0
1.0
14.5
10.5
2.0
1.0
13.5
9.5
ns
2-6
12.0
9.0
1.0
1.0
13.5
10.5
1.0
1.0
12.5
10.0
ns
2-5
11.5
9.0
1.0
1.0
14.0
10.5
1.5
1.0
13.0
10.0
ns
2-6
Units
Fig.
No.
Parameter
Vee·
(V)
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
An to Sn or Sn to An
3.3
5.0
1.5
1.5
5.0
3.5
8.5
6.5
1.0
1.0
11.5
8.5
1.0
1.0
tpHL
Propagation Delay
An to Sn or Sn to An
3.3
5.0
1.5
1.5
5.0
3.5
8.5
6.0
1.0
1.0
10.0
7.5
tpZH
Output Enable Time
3.3
5.0
2.5
1.5
7.0
5.0
11.5
8.5
1.0
1.0
tPZL
Output Enable Time
3.3
5.0
2.5
1.5
7.5
5.5
12.0
9.0
tpHZ
Output Disable Time
3.3
5.0
2.0
1.5
6.5
5.5
tpLZ
Output Disable Time
3.3
5.0
2.0
1.5
7.0
5.5
Symbol
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics:
Symbol
Vee·
(V)
Parameter
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Typ
Max
Min
Max
Min
Max
5.0
1.5
4.0
7.5
1.0
9.0
1.5
8.0
ns
2-3,4
5.0
1.5
4.0
8.0
1.0
10.0
1.0
9.0
ns
2-3,4
12.0
1.5
11.0
ns
2-5
13.0
1.5
12.0
ns
2-6
12.0
1.0
11.0
ns
2-5
12.0
1.5
11.0
ns
2-6
tpLH
Propagation Delay
An to Sn or Sn to An
tpHL
Propagation Delay
An to Sn or Sn to An
tPZH
Output Enable Time
5.0
1.5
5.0
10.0
1.0
tPZL
Output Enable Time
5.0
1.5
5.5
10.0
1.0
tpHZ
Output Disable Time
5.0
1.5
5.5
10.0
1.0
tpLZ
Output Disable Time
5.0
2.0
5.0
10.0
1.0
'Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
ClIO
Input/Output
Capacitance
15.0
pF
CPO
Power Dissipation
Capacitance
45.0
pF
4-147
Conditions
Vee
= 5.0V
= 5.0V
Vee
= 5.0V
Vee
•
_ r-------------------------------------------------------------------------,
~
~National
~ Semiconductor
54AC/74AC251 • 54ACT/74ACT251
a-Input Multiplexer with TRI-STATE® Output
General Description
Features
The 'AC/'ACT251 is a high-speed 8-input digital multiplexer.
It provides, In one package, the ability to select one bit of
data from up to eight sources. It can be used as universal
function generator to generate any logic function of four
variables. Both true and complementary outputs are provided.
•
•
•
•
•
•
Multifunctional capability
On-chip select logic decoding
Inverting and non inverting TRI-STATE outputs
Outputs source/sink 24 mA
'ACT251 has TTL-compatible inputs
Standard Military Drawing (SMD)
- 'AC251: 5962-87692
- 'ACT251: 5962-89599
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
_II I I I I I I
-
So
OE-
52
~~= O)G~
-5,
-
-(lOE
z
z
'---..,.y~---rl---I
TLlF/9945-1
Pin Assignment
for DIP, Flatpak and SOIC
IAUX
EN
16 -Vee
15 -'4
14 -15
13 -Is
'2-
',-
S2- 2
10 -
\,....."I
'3- 12
3
4
Z- 5
'0-
0
',-1
v r-- z
vl-i
'2- 2
'3- 3
12 -'7
11 -so
i- 6
OE- 7
10 -SI
GND- 8
'4- 4
9 -S2
'5- 5
's-
TL/F/9945-3
6
'7- 7
1";,,..-----1
Pin Assignment
for LCC
TLlF/9945-2
Pin Names
SO-S2
OE
10- 17
Z
Z
Z Z NC '0 "
[[]m[]][§]1Il
Description
Select Inputs
TRI-STATE Output Enable Input
Multiplexer Inputs
TRI-STATE Multiplexer Output
Complementary TRI-STATE Multiplexer
Output
~~--w-
OE [[)
GND [j]J
NC []]
>
~
>
I: m'2
I: [1:113
II [Il NC
~ @lVcc
S21m>
s,liAI>
~ 1j]]'4
111111111111111,
1Bi[i]JJi]]IilIJi]]
S07 NC 'S5
TL/F/9945-4
4-148
Functional Description
Truth Table
This device is a logical implementation of a single-pole.
8-position switch with the switch position controlled by the
state of three Select inputs. So. SI. S2. Both true and complementary outputs are provided. The Output Enable input
(OE) is active LOW. When it is activated. the logic function
provided at the output is:
Inputs
Z = OE • (10 0 So • SI • S2 + 11 0 So 0 SI • S2 +
12 0 So 0 SI 0 S2 + 13 • So • SI • S2 +
14 • So • SI • S2 + 15· So • SI 0 S2 +
Is 0 So 0 SI • S2 + 17 • So • SI • S2)
When the Output Enable is HIGH. both outputs are in the
high impedance (High Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices
together. When the outputs of the TRI-STATE devices are
tied together. all but one device must be in the high impedance state to avoid high currents that would exceed the
maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active-LOW portion of the enable voltages.
Outputs
OE
52
51
50
Z
H
L
L
L
L
L
L
L
L
X
X
X
Z
Z
L
L
L
L
H
H
H
L
L
H
H
L
L
H
H
H
L
H
L
H
L
H
L
H
io
il
i2
i3
i4
i5
is
i7
10
11
12
13
14
15
Is
17
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
logic Diagram
Z
Z
TL/F/9945-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-149
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee>
DC Input Diode Current (1110
VI = -0.5V
-20mA
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (10K>
Vo = -0.5V
-20mA
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
Supply Voltage (Vee)
'AC
'ACT
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (boV/bot)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (boV I bot)
'ACT Devices
VIN from 0.8V to 2.0V .
Vee @ 4.5V, 5.5V
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGNO)
Storage Temperature (TSTG)
- 65·C to + 150·C
Junction Temperature (TJ)
CDIP
175·C
PDIP
140·C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
e,caption, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACTTM cirCUits outside datebook specifications.
2.0Vto 6.0V
4.5Vt05.5V
OVtoVee
OVtoVee
-40·Cto +85·C
- 55·C to + 125·C
125 mVlns
125 mVlns
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
= +25·C
Typ
VIH
VIL
VOH
74AC
TA =
- 40·C to + 85"C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - O.W
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75 .
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
orVee - O.W
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
±1.0
±1.0
!-,A
3.0
4.5
5.5
VOL
54AC
TA=
-55·C to + 125·C
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
lOUT = -50!-,A
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50!-,A
·VIN
3.0
4.5
5.5
Maximum Input
5.5
±0.1
Leakage Current
•All outputs loaded; thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
liN
4-150
10L
VI
= VILorVIH
12mA
24mA
24mA
= Vee,GND
N
....
U1
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vcc
(V)
74AC
54AC
74AC
TA=
+25'C
TA =
-55'C to + 125'C
TA=
-40'Cto +85'C
Typ
Maximum TRI-STATE®
Current
102
tMinimum Dynamic
Output Current
10LD
10HD
Maximum Quiescent
Supply Current
Icc
5.5
Units
Conditions
Guaranteed Limits
±0.5
±10.0
±5.0
p,A
VI (OE) = VIL, VIH
VI = Vcc, VGND
Vo = Vcc,GND
VOLD = 1.65V Max
5.5
50
75
mA
5.5
-50
-75
mA
VOHD = 3.85V Min
p,A
VIN = Vcc
orGND
5.5
8.0
160.0
80.0
'All outputs loaded; thresholds on input associated with output under lest.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc
@
Icc for S4AC
3.0V are guaranteed to be less than or equal to the respective limit @ S.SV Vee.
2S'C is identical to 74AC @ 2S·C.
@
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vcc
(V)
74ACT
54ACT
74ACT
TA =
+ 25'C
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
O.B
0.8
0.8
0.8
O.B
V
VOUT = 0.1V
orVcc - 0.1V
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
VOH
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = -50p,A
'VIN = VIL or VIH
-24mA
10H
-24mA
lOUT = 50 p,A
'VIN = VIL or VIH
24mA
24mA
10L
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
p,A
VI = Vcc,GND
102
Maximum TRI-STATE®
Current
5.5
±0.5
±10.0
±5.0
p,A
VI = VIL, VIH
Vo = Vcc,GND
ICCT
Maximum
Iccllnput
5.5
1.6
1.5
mA
10LD
tMinimum Dynamic
Output Current
10HD
Icc
Maximum Quiescent
Supply Current
0.6
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
p,A
VIN = Vcc
orGND
8.0
5.5
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for S4ACT
@
VI = Vcc - 2.1V
2S'C is identical to 74ACT
@
2S·C.
4-151
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
SntoZorZ
3.3
5.0
1.5
1.5
11.5
8.5
17.5
12.5
1.0
1.0
21.0
15.5
1.5
1.5
19.0
13.5
ns
2-3,4
tpHL
Propagation Delay
SntoZorZ
3.3
5.0
1.5
1.5
11.0
8.0
17.5
12.5
1.0
1.0
21.0
15.5
1.5
1.5
19.0
13.5
ns
2-3,4
tpLH
Propagation Delay
IntoZorZ
3.3
5.0
1.5
1.5
10.0
7.0
14.0
10.0
1.0
1.0
17.0
12.0
1.5
1.5
15.5
11.0
ns
2-3,4
tpHL
Propagation Delay
In toZ orZ
3.3
5.0
1.5
1.5
9.0
6.5
14.0
10.0
1.0
1.0
16.5
12.0
1.5
1.5
15.5
11.0
ns
2-3,4
tpZH
Output Enable Time
OEtoZorZ
3.3
5.0
1.5
1.5
7.5
5.5
11.0
8.0
1.0
1.0
13.0
10.0
1.5
1.5
12.0
9.0
ns
2-5
tPZL
Output Enable Time
OEtoZorZ
3.3
5.0
1.5
1.5
7.5
5.5
11.0
8.0
1.0
1.0
13.0
10.0
1.5
1.5
12.0
9.0
ns
2-6
tpHZ
Output Disable Time
OEtoZorZ
3.3
5.0
1.5
1.5
8.5
7.0
11.5
9.5
3.5
2.5
14.0
11.0
1.5
1.5
13.0
10.0
ns
2-5
tpLZ
Output Disable Time
OEtoZorZ
3.3
5.0
. 1.5
1.5
7.0
5.5
11.0
8.0
4.0
3.0
13.0
10.0
1.5
1.5
12.0
8.5
ns
2-6
Units
Fig.
No.
'Voltage Range 3.3 Is 3.3V ±0.3V
Voltage Range 5.0 Is 5.0V ±0.5V
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 5DpF
TA = -55'C
to + 125'C
CL = 5DpF
TA = -40'C
to +85'C
CL=5DpF
Min
Typ
Max
Min
Max
Min
Max
5.0
2.5
7.0
15.5
1.0
18.5
2.0
17.0
ns
2-3,4
Propagation Delay
SntoZorZ
5.0
2.5
7.5
16.5
1.0
19.5
2.5
18.5
ns
2-3,4
tpLH
Propagation Delay
IntoZ orZ
5.0
2.5
5.5
12.0
1.0
14.0
2.0
13.0
ns
2-3,4
tpHL
Propagation Delay
In toZ orZ
5.0
2.5
6.5
12.5
1.0
15.0
2.5
14.0
ns
2-3,4
tpZH
Output Enable Time
OEtoZorZ
5.0
1.5
5.0
8.5
1.0
10.0
1.5
9.0
ns
2-5
tPZL
Output Enable Time
OEtoZorZ
5.0
1.5
4.5
8.5
1.0
10.0
1.5
9.5
ns
2-6
tpHZ
Output Disable Time
OEtoZorZ
5.0
2.0
6.0
12.0
1.0
13.5
2.0
13.0
ns
2-5
tpLZ
Output Disable Time
OEtoZorZ
5.0
1.5
4.5
8.5
1.0
9.5
1.5
9.0
ns
2-6
tpLH
Propagation Delay
SntoZorZ
tpHL
'Voltage Range 5.0 is 5.0V ±0.5V
4-152
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
70.0
pF
Vee = 5.0V
III
4-153
~
II)
N
.---------------------------------------------------------------------,
~National
~ semiconductor
54AC/74AC253. 54ACT/74ACT253
Dual4-lnput Multiplexer with TRI-STATE® Outputs
General Description
Features
The 'AC/'ACT253 is a dual 4-input multiplexer with TRISTATE outputs. It can select two bits of data from four
sources using common select inputs. The outputs may be
individually switched to a high impedance state with a HIGH
on the respective Output Enable (DE) inputs, allowing the
outputs to interlace directly with bus oriented systems.
•
•
•
•
•
Multifunction capability
Noninverting TRI-STATE outputs
Outputs source/sink 24 mA
'ACT253 has TIL-compatible inputs
Standard Military Drawing (SMD)
- 'AC253: 5962-87693
- 'ACT253: 5962-87761
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
So
Vee
5,
OEb
So
TL/F/9946-1
OEa
12a
lOa
I'a
Za
13b
12b
lOa
6
II
l,b
12a
Za
7
10
lOb
13a
GND
8
9
Zb
I'a
OEb
TL/F/9946-3
lOb
Zb
I'b
12b
Pin Assignment
forLCC
13b
lOa I'a He 12a 13•
TLlF/9946-2
Pin Names
IOa- 13a
10b-lsb
SO,S,
DEa
OEb
Za,Zb
[ID[1][ID[[Jffi
Za III
Description
~
III 5,
GNDll2I ~
NC [jJ ~
Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Output Enable Input
Side B Output Enable Input
TRI-STATE Outputs
Zb 1m
lOb 1m
mOEa
OJNC
~
S21Vee
~
1lID00b
1BI~1!§J1l1I1lE
I'b 12b NC 13b So
TL/F/9946-4
4-154
Functional Description
+ 11a· 51 • So +
+ ISa a SI • So)
(lab 051 • 50 + lIb· 51 • So +
The 'ACI'ACT253 contains two identical 4-input multiplexers with TRI-STATE outputs. They select two bits from four
sources selected by common Select inputs (So, SI)' The 4input multiplexers have individual Output Enable (OEa, OEb)
inputs which, when HIGH, force the outputs to a high impedance (High Z) state. This device is the logic implementation
of a 2-pole, 4-positlon switch, where the position of the
switch is determined by the logic levels supplied to the two
select inputs. The logic equations for the outputs are shown:
Za = OEa 0 (lOa 0 51 050
12a • SI • 50
Zb = OEb 0
12b • SI • 50 + ISb· SI .. So)
If the outputs of TRI-STATE devices are tied together, all
but one device must be in the high impedance state to avoid
high currents that would exceed the maximum ratings. Designers should ensure that Output Enable Signals to TRISTATE devices whose outputs are tied together are designed so that there is no overlap.
Truth Table
Select
Inputs
Data Inputs
Output
Enable
Outputs
So
SI
10
11
12
13
OE
Z
X
L
L
H
X
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
Z
H
L
L
H
H
H
H
H
H
H
X
X
X
X
X
X
H
X
X
X
X
H
X
X
H
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
Address Inputs So and 5, are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
logic Diagram
TL/F/9946-5
Please nole Ihallhis diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-155
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Diode Current (11K)
VI = -0.5V
-20mA
VI = Vee + 0.5V
+20mA
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (loKI
Va = -0.5V
-20mA
Va = Vee + 0.5V
+20mA
DC Output Voltage (Va)
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (Io)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGNO)
Storage Temperature (TSTG)
- 65'C to + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design Is reliable over Its power supply.
temperaMe, and outputllnput loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
Supply Voltage (Vee)
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature {TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (AV/At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (AV/At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vt06.0V
4.5Vt05.5V
OVtoVee
OVtoVee
-40'Cto +85'C
- 55'C to + 125'C
125 mV/ns
125 mV/ns
DC Characteristics for' AC Family Devices
74AC
Symbol
VIL
VOH
TA=
- 40'C to + a5'C
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - O.IV
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.IV
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
±1.0
±1.0
p.A
TA
= +25'C
3.0
4.5
5.5
VOL
74AC
Parameter
Typ
VIH
54AC
TA =
-55'C to + 125'C
Vee
(V)
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
Units
Conditions
Guaranteed Limits
lOUT = -50 p.A
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50 p.A
'VIN
3.0
4.5
5.5
Maximum Input
5.5
±0.1
Leakage Current
•All outputs loaded; thresholds on input ..sociated with output under lest
tMaximum test duration 2.0 ms, one output loaded at a time.
liN
4-156
10L
VI
= VIL or VIH
12mA
24mA
24mA
= Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vce
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-!i5'C to + 125'C
TA=
-40'Cto +85'C
Typ
loz
10LD
10HD
Maximum TRI-STATE®
Current
tMinimum Dynamic
Output Current
Conditions
Guaranteed Limits
±0.5
5.5
Units
±10.0
±5.0
/LA
VI (OE) = VIL, VIH
VI = Vcc,GND
Vo = Vcc,GND
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.S5V Min
80.0
/LA
VIN = Vcc
orGND
Maximum Quiescent
5.5
8.0
160.0
Supply Current
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vcc.
Icc for 54AC @ 2S'C is identical to 74AC @ 25'C.
Icc
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vce
(V)
74ACT
54ACT
74ACT
TA = +25'C
TA =
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
O.S
0.8
0.8
0.8
V
VOUT = 0.1V
orVcc - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = -50/LA
'VIN = VIL or VIH
-24mA
10H
-24mA
lOUT = 50/LA
'VIN = VIL or VIH
24mA
10L
24mA
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
p.A
VI = Vcc,GND
loz
Maximum TRI-STATE®
Current
5.5
±0.5
±10.0
±5.0
/LA
VI = VIL, VIH
Vo = Vcc,GND
ICCT
Maximum
Iccllnput
5.5
1.6
1.5
mA
10LD
tMinimum Dynamic
Output Current
10HD
Icc
Maximum Quiescent
Supply Current
0.6
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.S5V Min
160.0
SO.O
/LA
VIN = VCC
orGND
5.5
8.0
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT @ 25'C Is idenllcal to 74ACT @ 25'C.
4-157
•
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for waveforms
Vee'
(V)
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Typ
Max
Min
Max
Min
Max
Units
Fig.
No.
tpLH
Propagation Delay
Sn to Zn
3.3
5.0
2.0
2.0
B.5
6.5
15.5
11.0
1.0
1.0
19.5
13.5
2.0
1.5
17.5
12.5
ns
2-3,4
tpHL
Propagation Delay
SntoZn
3.3
5.0
2.5
2.0
9.5
7.0
16.0
11.5
1.0
1.0
20.0
15.0
2.0
1.5
1B.0
13.0
ns
2-3,4
tpLH
Propagation Delay
In to Zn
3.3
5.0
1.5
1.5
7.0
5.5
14.5
10.0
1.0
1.0
19.0
13.0
1.5
1.5
17.0
11.5
ns
2-3,4
tpHL
Propagation Delay
In toZ n
3.3
5.0
2.0
1.5
7.5
5.5
13.0
9.5
1.0
1.0
16.0
12.0
1.5
1.5
15.0
11.0
ns
2-3,4
tPZH
Output Enable Time
3.3
5.0
1.5
1.5
4.5
3.5
B.O
6.0
1.0
1.0
9.5
7.0
1.0
1.0
B.5
6.5
ns
2-5
tpZL
Output Enable Time
3.3
5.0
1.5
1.5
5.0
3.5
8.0
6.0
1.0
1.0
10.0
7.5
1.0
1.0
9.0
7.0
ns
2-6
tpHZ
Output Disable Time
3.3
5.0
2.0
2.0
5.5
5.0
9.5
B.O
1.0
1.0
11.0
9.5
1.5
1.5
10.0
B.5
ns
2-5
tpLZ
Output Disable Time
3.3
5.0
1.5
1.5
5.0
4.0
B.O
7.0
1.0
1.0
9.5
B.O
1.0
1.0
9.0
7.5
ns
2-6
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 Is 5.0V ± 0.5V
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for waveforms
Vee'
(V)
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL=50pF
TA = -40'C
to +85'C
CL=50pF
Min
Typ
Max
Min
Max
Min
Max
5.0
2.0
7.0
11.5
1.0
14.5
2.0
13.0
ns
2-3,4
Propagation Delay
Sn to Zn
5.0
3.0
7.5
13.0
1.0
16.0
2.5
14.5
ns
2-3,4
tpLH
Propagation Delay
In to Zn
5.0
2.5
5.5
10.0
1.0
12.0
2.0
11.0
ns
2-3,4
tpHL
Propagation Delay
In to Zn
5.0
3.5
6.5
11.0
1.0
13.5
3.0
12.5
ns
2-3,4
tPZH
Output Enable Time
5.0
2.0
4.5
7.5
1.0
9.5
1.5
B.5
ns
2-5
tPZL
Output Enable TIme
5.0
2.0
5.0
8.0
1.0
9.5
1.5
9.0
ns
2-6
tpHZ
Output Disable Time
5.0
3.0
6.0
9.5
1.0
11.0
2.5
10.0
ns
2-5
tpLZ
Output Disable Time
5.0
2.5
4.5
7.5
1.0
9.0
2.0
8.5
ns
2-6
tpLH
Propagation Delay
Sn tOZn
tpHL
'VoRage Range 5.0 Is 5.0V ± 0.5V
4-158
Capacitance
Parameter
Typ
Units
Conditions
CIN
Symbol
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
50.0
pF
4-159
Vee = 5.0V
~ r---------------------------------------------------------------------------~
II)
C'\I
~National
~ Semiconductor
54AC/7 4AC257 e 54ACT17 4ACT257
Quad 2-lnput Multiplexer with TRI-STATE® Outputs
General Description
Features
The 'ACI'ACT257 is a quad 2-input multiplexer with TRISTATE outputs. Four bits of data from two sources can be
selected using a Common Data Select input. The four outputs present the selected data in true (noninverted) form.
The outputs may be switched to a high impedance state by
placing a logic HIGH on the common Output Enable (OE)
input, allowing the outputs to interface directly with bus-oriented systems.
•
•
•
•
•
Multiplexer expansion by tying outputs together
Noninverting TRI-STATE outputs
Outputs source/sink 24 mA
'ACT257 has TTL-compatible inputs
Standard Military Drawing (SMD)
- 'AC257: 5962-88703
- 'ACT257: 5962-89689
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
I I I I I I I I
DE-
-(lOE
s-
EH
[
1""----'"1
S-~'
-s
"a-
MUX I>
I
I
I
1
16 -Vee
15
10a- 2
I
Tl/F/9949-1
-DE
14 rlOe
3
-"e
Za- 4
13
10b- 5
12 I-Ze
I'b- 6
Zb- 7
10 rl1d
GHD- 8
9 rZd
11 rlOd
TlIF/9949-3
Pin Assignment
forlCC
TlIF/9949-2
z..
'lb lor, He
'la
lID ill II](]] III
Pin Names
S
10a-IOd
l'a- I'd
Za-Zd
Description
Zb IID
Common Data Select Input
TRI-STATE Output Enable Input
Data Inputs from Source 0
Data Inputs from Source 1
TRI-STATE Multiplexer Outputs
~
GND lim ~
NCIIil~
Zdli]] ~
I'd~>
".".".". "..
1rn1lID1i][1i1I[j]J
'ad Z.
HC 'Ie
'oc
TlIF/9949-4
4-160
Functional Description
The 'AC/'ACT257 is quad 2-input multiplexer with TRISTATE outputs. It selects four bits of data from two sources
under control of a Common Data Select input. When the
Select input is LOW, the lOx inputs are selected and when
Select is HIGH, the 11x inputs are selected. The data on the
selected inputs appears at the outputs in true (noninverted)
form. The device is the logic implementation of a 4-pole, 2position switch where the position of the switch is determined by the logic levels supplied to the Select input. The
logic equations for the outputs are shown below:
(11a 0 S
+ lOa 0 g)
OEo (11boS
OE 0 (11 coS
+ 10b og)
Za = OE
Zb
Zc
=
=
0
mum ratings. Designers should ensure the Output Enable
signals to TRI-STATE devices whose outputs are tied together are designed so there is no overlap.
Truth Table
+ loc 0 g)
Zd = OE 0 (11d 0 S + 10d 0 g)
When the Output Enable (OE) is HIGH, the outputs are
forced to a high impedance state. If the outputs are tied
together, all but one device must be in the high impedance
state to avoid high currents that would exceed the maxi-
H =
L =
X=
Z =
Output
Enable
Select
Input
OE
S
10
11
Z
H
L
L
L
L
X
X
X
X
X
L
H
X
X
Z
L
H
L
H
H
H
L
L
Data
Inputs
Outputs
L
H
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
logic Diagram
10c
TL/F/9949-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-161
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
'AC
'ACT
-0.5V to 7.0V
Supply Voltage (Vecl
DC Input Diode Current (I,,{)
VI = -0.5V
VI = Vee +0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
-0.5VtoVee +0.5V
±50mA
DC Output Source or Sink Current (10)
DC Vee or Ground Current
Per Output Pin (Icc or IGNO)
±50mA
Storage Temperature (T8TG)
Input Voltage (VI)
OV to Vee
Output Voltage (VO)
OVtoVee
Operating Temperature (TA>
74AC/ACT
54AC/ACT
-0.5V to Vee +0.5V
DC Output Diode Current (loKI
Vo = -0.5V
Vo = Vee +0.5V
DC Output Voltage (Vo)
2.0Vt06.0V
4.5Vt05.5V
- 65'C to + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over Us power supply,
temperature, and output/input loading variables. National doe. not recom·
mend operation of FACTTM circuits outside databook specifications.
- 40'C to + 85'C
- 55'C to + 125'C
Minimum Input Edge Rate (A V I b.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125mV/ns
Minimum Input Edge Rate (b.V/b.t)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = O.tv
or Vee - O.tv
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.tv
or Vee - O.tv
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
",A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-162
lOUT = -50 ",A
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50 ",A
'VIN = VILorVIH
12mA
24mA
10L
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA=
+ 25·C
TA=
-55·C to + 125·C
TA=
-40·Cto +85·C
Typ
loz
10LD
10HD
Maximum TRI-STATE
Leakage Current
tMinimum Dynamic
Output Current
Units
Conditions
Guaranteed Limits
±10.0
±5.0
p.A
VI (OE) = VIL, VIH
VI = Vcc,GND
Vo = Vcc,GND
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
p.A
VIN = VCC
orGND
5.5
±0.5
Maximum Quiescent
B.O
160.0
5.5
Supply Current
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test dUration 2.0 ms, one output loaded at a time.
Noto: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vcr;;.
Icc for 54AC @ 25'C is identical to 74AC @ 25'C.
ICC
BO.O
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +25·C
TA=
-55·C to + 125·C
TA=
- 40·C to + 85·C
Typ
Conditions
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
O.B
O.B
O.B
O.B
V
VOUT = 0.1V
orVCC - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.B6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
p.A
10Z
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
p.A
ICCT
Maximum
Icc/Input
5.5
1.6
1.5
mA
10LD
tMinimum Dynamic
Output Current
10HD
0.6
lOUT = - 50 p.A
·VIN = VIL or VIH
-24mA
-24mA
10H
lOUT = 50 p.A
·VIN = VIL or VIH
24mA
24mA
10L
VI = Vcc,GND
VI = VIL, VIH
Vo = Vcc,GND
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
p.A
VIN = VCC
orGND
Maximum Quiescent
ICC
5.5
B.O
Supply Current
•All outputs loaded; thresholds on input associated with output under test.
tMaxlmum test duration 2.0 ma, one output loaded at a time.
Note: Icc for 54ACT @ 25'C is identical to 74ACT @ 25'C.
4-163
AC Electrical Characteristics:
Symbol
Vee'
Parameter
(V)
See Section 2 for waveforms
74AC
54AC
74AC
TA = +25·C
CL = 50pF
TA = -55·C
to + 125·C
Cl = 50pF
TA = -40·C
to +85·C
Cl = 50pF
Units
Fig.
No.
tpLH
Propagation Delay
Into Zn
3.3
5.0
1.5
1.5
5.0
4.0
8.5
6.0
1.0
1.0
11.0
8.0
1.0
1.0
9.0
7.0
ns
2·3,4
tpHL
Propagation Delay
IntoZn
3.3
5.0
1.5
1.5
6.0
4.5
8.5
6.0
1.0
1.0
11.0
8.5
1.0
1.0
9.0
7.0
ns
2·3,4
tpLH
Propagation Delay
StoZn
3.3
5.0
1.5
1.5
7.0
5.0
10.5
7.5
1.0
1.0
14.5
11.0
1.5
1.0
11.5
8.5
ns
2·3,4
tpHL
Propagation Delay
StoZn
3.3
5.0
1.5
1.5
7.5
5.5
10.5
7.5
1.0
1.0
14.5
11.0
1.5
1.0
11.5
8.5
ns
2·3,4
tpZH
Output Enable Time
3.3
5.0
1.5
1.5
6.5
5.0
9.5
7.5
1.0
1.0
13.0
10.0
1.0
1.0
10.5
8.5 .
ns
2·5
tpZL
Output Enable Time
3.3
5.0
1.5
1.5
5.5
5.0
9.0
8.5
1.0
1.0
11.0
9.5
1.0
1.0
10.0
9.5
ns
2·6
tpHZ
Output Disable Time
3.3
5.0
1.5
1.5
5.5
5.0
10.0
9.0
1.0
1.0
13.0
11.0
1.0
1.0
11.0
10.0
ns
2·5
tpLZ
Output Disable Time
3.3
5.0
1.5
1.5
5.5
5.0
9.0
8.0
1.0
1.0
10.5
9.5
1.0
1.0
10.0
9.0
ns
2·6
Units
Fig •
No.
'Voltage Range 3.3 is 3.0V ± 0.3V
Voltage Range 5.0 Is 5.0V ± 0.5V
AC Electrical Characteristics:
.Symbol
Vee'
(V)
Parameter
See Section 2 for waveforms
74ACT
54ACT
74ACT
TA = +25·C
Cl = 50pF
TA = -55·C
to + 125·C
Cl = 50pF
TA = -40·C
to +85·C
Cl=50pF
tpLH
Propagation Delay
In to Zn
5.0
1.5
5.0
7.0
1.0
8.0
1.0
7.5
ns
2·3,4
tpHL
Propagation Delay
In to Zn
5.0
2.0
6.0
7.5
1.0
9.5
1.5
8.5
ns
2·3,4
tpLH
Propagation Delay
StoZ~
5.0
2.0
7.0
9.5
1.0
11.0
1.5
10.5
ns
2·3,4
tpHL
Propagation Delay
StoZn
5.0
2.5
7.0
10.5
1.0
11.5
2.0
11.5
ns
2·3,4
tpZH
Output Enable Time
5.0
2.0
6.0
8.0
1.0
9.5
1.5
9.0
ns
2·5
tpZL
Output Enable Time
5.0
2.0
6.0
8.0
1.0
9.5
1.5
9.0
ns
2·6
tpHZ
Output Disable Time
5.0
2.5
6.5
9.0
1.0
10.5
1.5
10.0
ns
2·5
Output Disable Time
tpLZ
'Voltage Range 5.0 is 5.0V ± 0.5V
5.0
2.0
6.0
7.5
1.0
9.0
1.5
8.5
ns
2·6
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
50.0
pF
Vee = 5.0V
4·164
~National
~ Semiconductor
54AC/74AC258 • 54ACT /7 4ACT258
Quad 2-lnput Multiplexer with TRI-STATE® Outputs
General Description
Features
The 'AC/'ACT258 is a quad 2-input multiplexer with TRISTATE outputs. Four bits of data from two sources can be
selected using a common data select input. The four outputs present the selected data in the complement (inverted)
form. The outputs may be switched to a high impedance
state with a HIGH on the common Output Enable (OE) input,
allowing the outputs to interface directly with bus-oriented
systems.
•
•
•
•
•
Multiplexer expansion by tying outputs together
Inverting TRI-STATE outputs
Outputs source/sink 24 mA
'ACT258 has TTL-compatible inputs
Standard Military Drawing (SMD)
- 'ACT258: 5962-88704
Ordering Code: See Section 8
logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
DE
OE
5
5
TL/F/9950-1
lOa
11a
Za
lab
lIb
lac
lIe
lad
lId
Zb
IDa
11a
Za
lOb
lIb
Zb
2
15
3
14
4
13
5
12
11
GND
Vee
DE
IDe
lIe
Ze
10d
lId
Zd
Ze
TLlF/9950-3
Zd
TLlF/9950-2
Pin Assignment
forLCC
Pin Names
S
OE
lOa-lad
Ila-lld
Za-Zd
Description
lIb lob NC
Common Data Select Input
TRI-STATE Output Enable Input
Data Inputs from Source 0
Data Inputs from Source 1
TRI-STATE Inverting Data Outputs
z.. 11a
IIDIllIIl[ID[!J
Zb [II
GND Ii]J
NC [j]
mlOa
iII 5
[j]NC
gmVee
ii]JDE
Zd 1m
lId 1m
IHIll]Jirnli1lirn
lad
Z. He lIe Ioc
TLlF/9950-4
4-165
III
Functional Description
ensure that Output Enable signals to TRI-STATE devices
whose outputs are tied together are designed so there is no
overlap.
The 'AC/'ACT258 is a quad 2-input multiplexer with TRISTATE outputs. It selects four bits of data from two sources
under control of a common Select input (S). When the Select input is LOW, the lox inputs are selected and when Select is HIGH, the 11x inputs are selected. The data on the
selected inputs appears at the outputs in inverted form. The
'AC/'ACT258 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined
by the logic levels supplied to the Select input. The logic
equations for the outputs are shown below:
Za
Zb
Ze
Zd
= OE· (Ila • S
= OE· (lIb. S
Truth Table
Output
Enable
Select
Input
OE
S
10
11
Z
H
L
L
L
L
X
X
X
X
X
L
H
X
X
Z
H
L
H
L
+ lOa • 5)
+ lab. 5)
+ lac • 5)
+ lad. S)
= OE • (lie • S
= OE • (lid • S
When the Output Enable input (CE) is HIGH, the outputs are
forced to a high impedance state. If the outputs of the TRISTATE devices are tied together, all but one device must be
in the high impedance state to avoid high currents that
would exceed the maximum ratings. Designers should
H=
L=
X=
Z=
H
H
L
L
Data
Inputs
Outputs
L
H
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
Logic Diagram
TL/F/9950-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-166
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/ Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
Supply Voltage (Vecl
'AC
'ACT
-20mA
+20mA
-0.5V to to Vee + O.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
±50mA
Storage Temperature (Tsm)
Input Voltage (VI)
OVtoVee
Output Voltage (Va)
OV to Vee
Operating Temperature (TAl
74AC/ACT
54AC/ACT
-0.5V to Vee + O.5V
DC Output Source
or Sink Current (10)
2.0Vt06.0V
4.5Vt05.5V
-65°C to + 150°C
-40°C to + 85°C
-55°C to + 125°C
Minimum Input Edge Rate (/lV//lt)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (/lV//lt)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
CDIP
175°C
PDIP
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not
recom~
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25°C
TA=
- 55°C to + 125°C
TA=
-40°C to +85°C
VIL
VOH
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = O.lV
or Vee - O.tV
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.lV
or Vee - O.tV
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
VOL
liN
Conditions
Guaranteed Limits
Typ
VIH
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
lOUT = -50",A
lOUT = 50 ",A
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
",A
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4·167
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
·VIN = VILorVIH
12mA
24mA
10L
24mA
VI = Vee,GND
•
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA=
+ 25°C
TA=
-55°C to + 125°C
TA=
-40°C to +85°C
Typ
Maximum TRI-STATE®
Current
loz
tMinimum Dynamic
Output Current
IOLD
IOHD
Maximum Quiescent
Supply Current
ICC
Units
Conditions
Guaranteed Limits
±0.5
5.5
±10.0
±5.0
/LA
VI (OE) = VIL, VIH
VI = Vcc,GND
Vo = Vcc,GND
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vcc
orGND
5.5
8.0
•All outputs loaded; thresholds on input associated wnh output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc
@
3.0V are guaranteed to be less than or equal to the respective limit
@
5.5V Vcc.
Icc for 54AC @ 25'C is identical to 74AC @ 25'C.
DC Characteristics for' ACT Family Devices
74ACT
Symbol
Parameter
Vee
(V)
TA=
+ 25°C
54ACT
74ACT
TA=
TA=
Units
-55°C to + 125°C - 40°C to + 85°C
Typ
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
orVcc - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = -50/LA
·VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50/LA
·VIN = VIL or VIH
24mA
IOL
24mA
liN
Maximum Input Leakage Current
5.5
±0.1
±1.0
±1.0
/LA
VI = Vcc,GND
loz
Maximum TRI-STATE®
Current
5.5
±0.5
±10.0
±5.0
/LA
VI = VIL, VIH
Va = Vcc,GND
Icer
Maximum
Icc/Input
5.5
1.6
1.5
mA
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.6
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = VCC
orGND
5.5
8.0
*AII outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: Icc for 54ACT
@
VI = Vcc - 2.1V
25'C is identical to 74ACT @ 25'C.
4-168
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
See Section 2 for waveforms
74AC
S4AC
74AC
TA = +2SoC
Cl = SOpF
TA = -SsoC
to + 12SoC
Cl = SOpF
TA = -40"C
to +8SoC
Cl = SO pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tplH
Propagation Delay
Intoln
3.3
5.0
2.0
1.5
6.0
4.5
9.5
7.5
1.0
1.0
12.0
9.5
1.5
1.0
11.0
8.5
ns
2·3,4
tpHl
Propagation Delay
Intoln
3.3
5.0
2.0
1.5
5.0
4.0
8.5
6.5
1.0
1.0
10.5
7.5
1.5
1.0
9.5
7.0
ns
2-3,4
tpLH
Propagation Delay
Stoln
3.3
5.0
3.0
2.0
7.5
6.0
12.0
9.5
1.0
1.0
15.0
11.5
2.5
1.5
14.0
10.5
ns
2-3,4
tpHL
Propagation Delay
Stoln
3.3
5.0
2.5
1.5
7.5
5.5
11.5
9.0
1.0
1.0
14.0
10.5
2.0
1.5
13.0
10.0
ns
2-3,4
tPZH
Output Enable Time
3.3
5.0
2.5
1.5
6.0
4.5
9.5
7.5
1.0
1.0
11.5
9.0
2.0
1.5
10.5
8.5
ns
2-5
tpZL
Output Enable Time
3.3
5.0
2.0
1.5
5.5
5.5
9.0
7.0
1.0
1.0
10.5
8.5
1.5
1.0
10.0
8.0
ns
2-6
tpHZ
Output Disable Time
3.3
5.0
2.5
2.0
5.5
5.5
10.0
8.5
1.0
1.0
11.5
9.5
2.0
1.5
11.0
9.0
ns
2-5
tpLZ
Output Disable Time
3.3
5.0
2.0
1.5
5.5
5.0
9.0
7.0
1.0
1.0
10.5
8.5
2.0
1.5
10.0
8.0
ns
2-6
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V
Voltage Range 5.0 is S.OV
±0.3V
±O.SV
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
74ACT
S4ACT
74ACT
TA = +2SoC
Cl = SOpF
TA = -SsoC
to + 12SoC
Cl = SO pF
TA = -40°C
to +8SoC
Cl = SOpF
Min
Typ
Max
Min
Max
Min
Max
5.0
2.0
6.5
8.5
1.0
10.5
1.5
9.5
ns
2-3,4
Propagation Delay
In to In
5.0
2.0
5.5
7.5
1.0
9.0
1.5
8.0
ns
2-3,4
Propagation Delay
Stoln
5.0
3.0
7.5
10.5
1.0
13.0
2.0
11.5
ns
2-3,4
5.0
1.5
7.0
9.5
1.0
12.0
1.5
11.0
ns
2-3,4
2-5
tpLH
Propagation Delay
Intoln
tpHL
tplH
Propagation Delay
tpHL
See Section 2 for waveforms
Stoln
tPZH
Output Enable Time
5.0
2.0
6.5
8.5
1.0
10.5
1.5
9.5
ns
tPZL
Output Enable Time
5.0
2.0
6.5
8.5
1.0
10.0
1.5
9.5
ns
2-6
tpHZ
Output Disable Time
5.0
1.5
7.0
9.0
1.0
10.5
1.0
10.0
ns
2-5
tpLZ
Output Qisable Time
±o.sv
5.0
2.0
6.0
8.0
1.0
10.0
1.5
9.0
ns
2-6
'Voltage Range 5.0 is S.OV
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
Vee
=
5.0V
CPD
Power Dissipation
Capacitance
55.0
pF
Vee
=
5.0V
4-169
Conditions
•
~
r-..
N
r---------------------------------------------------------------------,
~National
~ Semiconductor
54AC/74AC273
Octal D Flip-Flop
General Description
Features
The 'AC273 has eight edge-triggered D-type flip-flops with
individual D inputs and 0 outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
•
•
•
•
•
•
•
•
•
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's 0 output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
Ideal buffer for MaS microprocessor or memory
Eight edge-triggered D flip-flops
Buffered common clock
Buffered, asynchronous master reset
See '377 for clock enable version
See '373 for transparent latch version
See '374 for TRI-STATE version
Outputs source/sink 24 mA
Standard Military Drawing (SMD)
- 'AC273: 5962-87756
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
MR
MR
CP
CP
00
01
°0
MR
TUF/9954-1
°1
°2
03
02
03
°7
2
19
07
°0
3
18
°1
01
O2
4
17
5
16
~
06
06
6
15
7
14
Os
°2
03
8
13
06
07
03
GNO
10
04
°4
Os
06
Vee
00
12
11
TL/F/9954-2
OS
Os
0,
0,
CP
TL/F/9954-3
Pin Assignment
forLCC
Pin Names
0 0- 0 7
MR
CP
0 0- 0 7
pescrlptlon
~Dz°201Dl
IIDIIIIIDI]][!J
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
moo
03 [!]
GND lim
CP [j]
Q4 1il1
04 Ii]
III 00
[TIMR
~Vee
lim 07
~fi§J[§JIi1I[§J
DsOsOeDsD]
TL/F/9954-4
4-170
Mode Select-Function Table
Inputs
Operating Mode
Outputs
MR
CP
On
Reset (Clear)
L
X
X
L
Load '1'
H
.../
H
H
Load '0'
H
.../
L
L
Qn
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Immaterial
.../ ~ LOW·to·HIGH Transition
Logic Diagram
CP
0,
0,
0,
0,
TL/F/9954-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays .
•
4·171
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
Supply Voltage (Vecl
'AC
'ACT
-0.5Vto +7.0V
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
Input Voltage
-20mA
+20mA
DC Input Voltage (VI)
DC Output Voltage (Vo)
-0.5V to to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
±50mA
Storage Temperature (TSTG)
OV to Vee
OV to Vee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-20mA
+20mA
DC Output Source
or Sink Current (10)
-t.J.-I/O,
H-+D4'~1/02
H-+r>lc+--I/O,
H-+r>l.J-I/O,
DS,
CP
TL/F/9893-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-181
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
(Unless Otherwise Specified)
'AC
'ACT
-0.5Vto +7.0V
Supply Voltage (Vee>
DC Input Diode Current (IIIG
V, = -0.5V
V, = Vee +0.5V
-20mA
+20mA
DC Input Voltage (V,)
-0.5VtoVee +0.5V
DC Output Diode Current (loKl
Vo = -0.5V
Vo = Vee +0.5V
-0.5VtoVee +0.5V
DC Output Source or Sink Current (10)
±50mA
DC Vee or Ground Current
Per Output Pin (Icc or IGNO)
±50mA
-65'C to + 150'C
Storage Temperature (TSTG)
Inpu1 Voltage (V,)
OVtoVee
Output Voltage (Vo)
OVtoVee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-20mA
+20mA
DC Output Voltage (Vo)
2.0Vto 6.0V
4.5Vto 5.0V
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Obviously the databook specifications should be
met, without exception, to ensure that the system deSign is reliable over its
power supply, temperature, and output/input loading variables. National
does not recommend operetion of FACTTM circuits outside databook specifi·
- 40'C to + 85'C
- 55'C to + 125'C
Minimum Input Edge Rate (tN/At)
'AC Devices
Y,N from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125mV/ns
Minimum Input Edge Rate (AV/At)
'ACT Devices
Y,N from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
cations.
DC Electrical Characteristics For 'AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = 25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
VIH
V,L
VOH
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - O.W
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.W
or Vee - O.W
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
",A
5.5
±O.5
±10.0
±5.0
",A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
liN
Maximum Input
Leakage Current
loz
Maximum TRI-STATE
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
• All outputs loaded; threshold on input associated with output under test.
tMeximum test duration 20 ms, one output loaded at a time.
4-182
lOUT = -50",A
V
'VIN = V,L or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50 ",A
V
'VIN = V,L or V,H
12mA
24mA
10H
24mA
V, = Vee,GND
V,(OE) = VIL, V,H
V, = Vee,GND
Vo = Vee,GND
DC Electrical Characteristics For 'AC Family Devices
74AC
Symbol
Vee
(V)
Parameter
=
TA
25'C
54AC
74AC
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
tMinimum Dynamic
Output Current
IOLD
IOHO
Icc
Maximum Quiescent
Supply Current
IOlT
Maximum 1/0
Leakage Current
Units
Conditions
Guaranteed Limits
5.5
57
86
mA
YOLO
5.5
-50
-75
mA
VOHO
= 1.65V Max
= 3.85V Min
5.5
8.0
160
80
I-'A
VIN = Vec
orGND
5.5
±0.6
±11.0
±6.0
I-'A
VI(OE) = VIL. VIH
VI = Vcc. GND
Vo = Vcc. GND
"All outputs loaded; threshold on input associated with output under test.
tMaximum test duration 20 ms, one output loaded at a time.
Note: lIN and Icc
Icc for S4AC
@
@
3.0V are guaranteed to be less than or equal to the respective limit
2S'C is identical
to
74AC
@
DC Electrical Characteristics
Vee
(V)
Parameter
5.5V Vee.
For 'ACT Family Devices
74ACT
Symbol
@
2S'C.
=
TA
25'C
Typ
54ACT
74ACT
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Units
Conditions
Guaranteed Limits
VOUT = O.W
or Vee - 0.1V
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
Maximum Low Level
Input Voltage
3.0
4.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
VOH
Minimum High Level
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
lOUT
= -
0.0001
3.86
4.86
3.70
4.70
3.76
4.76
V
'VIN
IOH
=
4.5
5.5
VIL or VIH
-24mA
-24mA
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
V
lOUT
=
5Ol-'A
0.36
0.36
0.50
0.50
0.44
0.44
V
'VIN
10L
=
4.5
5.5
VIL or VIH
24mA
24mA
Maximum Low Level
Output Voltage
VOL
V
VOUT = O.W
or Vee - O.W
50 I-'A
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
I-'A
VI
10l
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
I-'A
VI = VIL. VIH
Vo = Vec. GND
=
Vcc. GND
lecT
Maximum Ice/lnput
5.5
1.6
1.5
mA
VI
10LD
tMinimum Dynamic
Output Current
5.5
50
75
mA
VOLD
5.5
-50
-75
mA
VOHO
10HO
Icc
Maximum Quiescent
Supply Current
10lT
Maximum 1/0
Leakage Current
Note:
Icc limit for S4ACT @ 2S'C
0.6
=
= 1.65V Max
= 3.85V Min
5.5
8.0
160
80
I-'A
VIN = Vee
orGND
5.5
±0.6
±11.0
±6.0
I-'A
VI(OE) = VIL. VIH
VI = Vcc.GND
Vo = VCC.GND
is identical to
74ACT
@
2S'C.
"All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Capacitance
Symbol
Vec - 2.W
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
Vee
=
5.5V
CpO
Power Dissipation
Capacitance
170
pF
Vcc
=
5.5V
4-183
Conditions
en
en
N
AC Electrical Characteristics:
Symbol
Parameter
Vee·
(V)
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25'C
Cl = 50 pF
TA = -55'C
to + 125°C
Cl = 50 pF
TA = -40'C
to + 85°C
Cl = 50 pF
Max
Min
Max
Min
Typ
Maximum Input
Frequency
3.3
5.0
90
130
124
173
tpLH
Propagation Delay
CPtoOOor07
(Shift Left or Right)
3.3
5.0
8.5
5.5
14.0
9.5
20.5
14.0
1.0
1.0
25.5
17.5
7.0
4.5
22.0
15.0
ns
2-3,4
Propagation Delay
CPto 00 or07
(Shift Left or Right)
3.3
5.0
8.5
5.5
14.5
10.0
21.5
14.5
1.0
1.0
26.5
18.0
7.0
5.0
23.0
16.0
ns
2-3,4
tpLH
Propagation Delay
CPto lIOn
3.3
5.0
9.0
6.0
14.5
10.0
20.5
14.5
1.0
1.0
24.5
17.0
7.5
5.0
22.5
16.0
ns
2-3,4
tpHL
Propagation Delay
CPto lIOn
3.3
5.0
10.0
6.5
16.0
11.0
23.0
16.0
1.0
1.0
26.5
18.5
8.5
6.0
24.5
17.5
ns
2-3,4
tpHL
Propagation Delay
MR to 00 or07
3.3
5.0
9.0
5.5
15.5
10.5
22.5
15.5
1.0
1.0
27.0
18.5
7.5
5.0
25.0
17.0
ns
2-3,4
tpHL
Propagation Delay
MR to lIOn
3.3
5.0
9.0
5.5
15.0
10.0
21.5
15.0
1.0
1.0
26.5
18.0
7.5
5.0
24.0
16.5
ns
2-3,4
tPZH
Output Enable Time
OEto lIOn
3.3
5.0
7.0
4.5
12.0
8.5
18.0
12.5
1.0
1.0
22.0
15.0
6.0
4.0
19.5
13.5
ns
2-5
tpZL
Output Enable Time
OEto lIOn
3.3
5.0
7.0
5.0
12.5
8.0
18.0
12.5
1.0
1.0
23.5
16.0
6.0
4.0
20.5
14.0
ns
2-6
tpHZ
Output Disable Time
OEto lIOn
3.3
5.0
6.5
3.5
13.0
9.5
18.5
14.0
1.0
1.0
22.5
17.0
5.5
3.0
19.5
15.0
ns
2-5
1.0
1.0
21.5
16.0
4.5
2.0
19.0
13.5
ns
2-6
Output Disable Time
OEto lIOn
'Voltage Range 3.3 is 3.3V ±0.3V.
Voltage Range 5.0 is 5.0V ±0.5V.
tpLZ
3.3
5.0
5.5
3.5
AC Operating Requirements:
11.5
8.0
Min
Fig.
No.
f max
tpHL
Max
Units
80
105
70
80
17.0
12.5
MHz
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25°C
Cl = 50pF
TA = -55°C
to + 125°C
Cl = 50 pF
TA = -40°C
to + 85°C
Cl = 50 pF
Units
Fig.
No.
8.5
5.5
ns
2-7
2.0
2.5
0.5
1.0
ns
2-7
5.5
3.5
6.0
4.0
6.0
4.0
ns
2-7
-2.0
-1.0
0
1.0
1.5
2.0
0
1.0
ns
2-7
3.3
5.0
2.5
1.5
6.5
4.0
7.5
5.0
7.0
4.5
ns
2-7
Hold Time, HIGH or LOW
DSo or DS7 to CP
3.3
5.0
-2.0
-1.0
0
1.0
1.5
1.5
0.5
1.0
ns
2-7
tw
CP Pulse Width, LOW
3.3
5.0
3.5
2.0
4.5
3.5
5.5
5.0
5.0
3.5
ns
2-3
tw
MR Pulse Width, LOW
3.3
5.0
4.0
2.0
4.5
3.5
5.5
5.0
5.0
3.5
ns
2-3
3.3
5.0
0
0.5
1.5
1.5
2.5
2.5
1.5
1.5
ns
2-3,7
Parameter
Vee·
(V)
ts
Setup Time, HIGH or LOW
SOorS1 toCP
3.3
5.0
3.0
2.0
8.0
5.0
9.5
7.0
th
Hold Time, HIGH or LOW
SOorS1 toCP
3.3
5.0
-3.0
-1.5
0.5
1.0
ts
Setup Time, HIGH or LOW
lIOn to CP
3.3
5.0
2.0
1.0
th
Hold Time, HIGH or LOW
I/0ntoCP
3.3
5.0
ts
Setup Time, HIGH or LOW
DSo or DS7 to CP
th
Symbol
Guaranteed Minimum
Typ
Recovery Time
tree
MRtoCP
'Voltage Range 3.3 is 3.3V ± 0.3V
'Voltage Range 5.0 is 5.0V ± 0.5V
4-184
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
N
CD
CD
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25°C
CL = 50pF
TA = -55°C
to + 125°C
CL = 50pF
TA - -40"C
to +85°C
CL = 50pF
Min
Min
Units
Fig.
No.
Min
Typ
5.0
120
170
Propagation Delay
CPto 00 Or07
(Shift Left or Right)
5.0
4.0
B.5
12.5
1.0
15.5
3.0
14.0
ns
2-3,4
Propagation Delay
CPto 00 or07
(Shift Left or Right)
5.0
4.0
9.0
13.5
1.0
16.0
3.5
15.0
ns
2-3,4
tpLH
Propagation Delay
CPto lIOn
5.0
4.5
B.5
12.5
1.0
15.0
4.5
13.5
ns
2-3,4
lpHL
Propagation Delay
CPto lIOn
5.0
5.0
9.5
15.0
1.0
1B.0
4.5
16.5
ns
2-3,4
tpHL
Propagation Delay
MR to 00 or07
5.0
4.0
14.0
15.0
1.0
1B.0
4.0
1B.0
ns
2-3,4
tpHL
Propagation Delay
MRto lIOn
5.0
4.0
13.0
14.5
1.0
17.5
3.5
17.5
ns
2-3,4
tPZH
Output Enable Time
OEto lIOn
5.0
2.5
B.O
12.0
1.0
14.0
1.5
13.0
ns
2-5
tPZL
Output Enable Time
OEto lIOn
5.0
2.0
B.O
12.0
1.0
14.5
1.5
13.5
ns
2-6
tpHZ
Output Disable Time
OEto lIOn
2.5
2.0
B.5
12.5
1.0
14.5
2.0
13.5
ns
2-5
2.0
2.5
B.O
11.5
1.0
14.0
2.0
12.5
ns
2-6
f max
Maximum Input
Frequency
tpLH
tpHL
Output Disable Time
tpLZ
OEto lIOn
'Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements:
Symbol
Parameter
Vee'
(V)
Max
Max
70
Max
110
MHz
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25°C
CL = 50pF
TA = -55°C
to + 125°C
CL = 50pF
TA - -40°C
to +85°C
CL = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
SOorS1 toCP
5.0
2.0
5.0
6.5
5.5
ns
2-7
th
Hold Time, HIGH or LOW
SOorS1 toCP
5.0
-2.0
1.0
1.5
1.0
ns
2-7
ts
Setup Time, HIGH or LOW
I/0ntoCP
5.0
1.5
4.0
4.5
4.5
ns
2-7
th
Hold Time, HIGH or LOW
I/0ntoCP
5.0
-1.0
1.0
1.5
1.0
ns
2-7
ts
Setup Time, HIGH or LOW
DSo or DS7 to CP
5.0
1.5
4.5
5.5
5.0
ns
2-7
th
Hold Time, HIGH or LOW
DSo or DS7 to CP
5.0
-1.0
1.0
1.5
1.0
ns
2-7
tw
CP Pulse Width
HIGH or LOW
5.0
2.0
4.0
5.0
4.5
ns
2-3
tw
MR Pulse Width, LOW
5.0
2.0
3.5
5.0
3.5
ns
2-3
5.0
0
1.5
1.5
1.5
ns
2-3,7
Recovery Time
MRtoCP
'Voltage Range 5.0 is 5.0V ±0.5V.
tree
4-1B5
•
~
N
~
r----------------------------------------------------------------------------,
~National
~ Semiconductor
54ACT /7 4ACT323
8-Bit Universal Shift/Storage Register
with Synchronous Reset and Common I/O Pins
General Description
Features
The 'ACT323 is an 8-bit universal shiftlstorage register with
TRI-STATE outputs. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for 00 and 07 to allow easy
cascading. Four operation modes are possible: hold (store),
shift left, shift right and parallel load.
• Common parallel 1/0 for reduced pin count
• Additional serial inputs and outputs for expansion
• Four operating modes: shift left, shift right, load and
store
• TRI-STATE outputs for bus-oriented applications
• Outputs sourcelsink 24 mA
• TTL-compatible inputs
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
2
3
4
I/Os
I/O.
OSo
TL/F/9787-1
OE,
o~
00
I>
Z5
I>
1/00
1/0,
I/~
1/00
7
00
GNO
07
I/ar
SR
16
17
10
14
13
12
11
1/02
1/03
1/05
1/03
1/0,
CP
050
TLiF/9787-2
I/O.
1/05
I/Os
Pin Assignment
forLCC
I>
1/07
112
OS7
2••0
C\) VOo I/OsVO. vo.
[[)[1][[)IID!1I
07
TLiF/9787-5
Pin Name
Description
CP
DSo
DS7
SO,SI
SR
OE1,OE2
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Synchronous Reset Input
TRI-STATE Output Enable Inputs
Multiplexed Parallel Data Inputs or
TRI-STATE Parallel Data Outputs
Serial Outputs
1/00-1/07
0 0,07
SR[I]
III OEz
GND Ii]]
!II OE,
OSo !IiI
CP [Z)
m50
I/O, I!]
IiIDs,
~Vcc
~1iID1rn1i1l1im
VOsvo.vo,o,l!S,
TLiF/9787-3
4-186
r-----------------------------------------------------------------------------------------,
~
N
~
Functional Description
The 'ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by So and S1 as shown
in the Mode Select Table. All flip-flop outputs are brought
out through TRI-STATE buffers to separate 1/0 pins that
also serve as data inputs in the parallel load mode. 00 and
07 are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CPo
All other state changes are also initiated by the LOW-toHIGH CP transition. Inputs can change when the clock is in
either state provided only that the recommended setup and
hold times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the
TRI-STATE buffers and puts the 1/0 pins in the high impedance state. In this condition the shift, load, hold and reset
operations can still occur. The TRI-STATE buffers are also
disabled by HIGH signals on both So and S1 in preparation
for a parallel load operation.
Mode Select Table
Inputs
SR 51 So
L
H
H
H
H
X
H
L
H
L
Response
CP
X .../ Synchronous Reset; 00-07 = LOW
H .../ Parallel Load; lIOn - On
H .../ Shift Right; DSo - 00, 00 - 01, etc.
L .../ Shift Left; DS7 - 07, 07 - 06, etc.
L
X Hold
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
.J" = LOW·to·HIGH Clock Transition
•
4-187
Logic Diagram
DS,
1+-1:>--".... 1/0,
1-+-1>.... 1/0.
H-D4"-I/o.
H-D4"-I/o.
H-C>+'-I/O.
H-;>-~1/02
1+-G>t4- 1/00
CP
TUF/9787-4
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-188
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage (Vecl
'AC
'ACT
-20mA
+20mA
-20mA
+20mA
-0.5V to Vee + 0.5V
±50mA
DC Vee or Ground Current
Per Output Pin (lee or IGND)
Storage Temperature (TSTG)
±50mA
-65·C to + 150·C
Junction Temperature (TJ)
CDIP
PDIP
Input Voltage (VI)
OVtoVcc
Output Voltage (Vo)
OV to Vee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Source or
Sink Current (10)
2.0Vto 6.0V
4.5Vto 5.5V
-40·C to + 85·C
- 55·C to + 125·C
Minimum Input Edge Rate (fN/t:.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (t:.V/t:.t)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
175·C
140·C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not racom·
mend operation of FACTTt.t circuits outside databook specifications.
DC Electrical Characteristics For' ACT Family Devices
74ACT
Symbol
Parameter
Vee
(V)
TA
=
+25·C
Typ
54ACT
74ACT
TA =
-55·C to + 125·C
TA =
- 40·C to + 85·C
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - O.lV
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
orVee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
0.1
0.1
0.1
0.1
4.5
5.5
0.36
0.36
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT
=
-50 p.A
'VIN
10H
=
V
VIL or VIH
-24mA
-24mA
0.1
0.1
V
lOUT
=
50 p.A
0.44
0.44
V
'VIN
10L
=
0.50
0.50
VIL or VIH
-24mA
-24mA
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
p.A
VI
loz
Maximum TRI-STATE
Current
5.5
±0.5
±10.0
±5.0
p.A
VI = VIL, VIH
Vo = Vee,GND
10ZT
Maximum I/O
Leakage Current
5.5
±0.6
±11.0
±6.0
p.A
VIIO = Vee or GND
VIN = VIH, VIL
leer
Maximum leellnput
5.5
1.6
1.5
mA
VI
10LD
tMinimum Dynamic Output
Current
5.5
50
75
mA
VOLD
5.5
-50
-75
mA
VOHD
= 1.65V Max
= 3.85V Min
160
80
p.A
=
Vee or GND
10HD
lee
•All
Maximum Quiescent
Supply Current
0.6
5.5
8.0
outputs loaded; thresholds on input associated with output under test
2.0 ms, one output loaded at a time.
S4AeT is identical to 74ACT @ 2S'C.
tMaximum test duration
Note: Icc for
4·189
=
=
VIN
Vcc,GND
Vee - 2.1V
AC Electrical Characteristics:
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = 25'C
CL=50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Min
Fig.
No.
Parameter
Vcc·
(V)
Min
Typ
f max
Maximum Input Frequency
5.0
120
125
tpLH
Propagation Delay
CPtoQOorQ7
5.0
5.0
9.0
12.5
1.0
16.5
4.0
14.0
ns
2-3,4
tpHL
Propagation Delay
CPtoQO orQ7
5.0
5.0
9.0
13.5
1.0
17.0
4.5
15.0
ns
2-3,4
tpLH
Propagation Delay
CPto lIOn
5.0
5.0
8.5
12.5
1.0
16.5
4.5
14.5
ns
2-3,4
tpHL
Propagation Delay
CPtoi/O n
5.0
6.0
10.0
14.5
1.0
18.0
5.0
16.0
ns
2-3,4
tPZH
Output Enable Time
5.0
3.5
7.5
11.0
1.0
15.0
3.0
12.5
ns
2-5
tPZL
Output Enable Time
5.0
3.5
7.5
11.5
1.0
15.5
3.0
13.0
ns
2-6
tpHZ
Output Disable Time
5.0
4.0
8.5
12.5
1.0
15.5
3.0
13.5
ns
2-5
Output Disable Time
tpLZ
'Voltage Range 5.0 Is S.OV ±O.SV
5.0
3.0
8.0
11.5
1.0
15.0
2.5
12.5
ns
2-6
Units
Fig.
No.
Symbol
AC Operating Requirements:
Symbol
Parameter
Vcc·
(V)
Max
Max
Max
110
95
Units
MHz
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = 25'C
CL = 50pF
Vcc = +5.0V
TA = -55'C
to + 125'C
CL = 50pF
Vcc = +5.0V
TA = -40'C
to +85'C
CL = 50pF
Vcc = +5.0V
Typ
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
SOorSl toCP
5.0
2.0
5.0
6.0
5.0
ns
2-7
th
Hold Time, HIGH or LOW
SOorSl toCP
5.0
0
1.5
1.5
1.5
ns
2-7
ts
Setup Time, HIGH or LOW
lIOn, DSO, DS7 to CP
5.0
1.0
4.0
4.5
4.5
ns
2-7
th
Hold Time, HIGH or LOW
lIOn, DSo, DS7 to CP
5.0
0
1.0
1.0
1.0
ns
2-7
ts
Setup Time, HIGH or LOW
SRtoCP
5.0
1.0
2.5
3.0
2.5
ns
2-7
th
Hold Time, HIGH or LOW
SRtoCP
5.0
0
1.0
1.0
1.0
ns
2-7
5.0
2.0
4.0
5.0
4.5
ns
2-3
CP Pulse Width
HIGH or LOW
'Voltage Range 5.0 is S.OV ± o.sv
tw
Capacitance
Symbol
Typ
Units
Conditions
CIN
Input Capacitance
Parameter
4.5
pF
Vee = 5.0V
CPO
Power Dissipation Capacitance
170
pF
Vee = 5.0V
4-190
.---------------------------------------------------------------------~
~National
~ Semiconductor
54ACT17 4ACT367
Hex Buffer with TRI-STATE® Outputs
General Description
Features
The 'ACT367 contains six independent non-inverting buffers
with TRI-STATE outputs.
- Outputs source/sink 24 mA
_ 'ACT has TTL-compatible inputs
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEE/IEe
Pin Assignment
for Lee and pee
Pin Assignment
for DIP, sOle and Flatpak
12 0t NC It 00
rnlllJrn:J[[)1Il
DE t -+--.
10
00
10
It
°t
12
°2
13
°3
14
°4
[1110
°2 [[]
00
It
GND IlQ]
NC [j]
°t
12
°slill
rn DE t
[IJ NC
gQJVcc
[i]JDE2
15 Ii])
°2
'--,,!,---.Ii':w=iilriil....V
GND
!B]@)[j]J[l][j]J
04 14 NC 03 13
TLlF/l0691-2
15
Pin Names
OE1,OE2
In
On
°5
TLlF/l0691-1
Function Table
Inputs
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
Outputs
o
L
L
H
L
H
X
H
L
Z
4-191
TLlF/l0691-3
Description
Output Enable Input (Active LOW)
Input
Output
w
en
......
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5V to + 7.0V
Supply Voltage (Vecl
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage (Vecl
'AC
'ACT
-20mA
+20mA
-20mA
+20mA
-0.5V to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
Storage Temperature (T8TG)
±50mA
- 65"C to + 150"C
Junction Temperature (TJ)
CDIP
PDIP
Input Voltage (VI)
OV to Vee
Output Voltage (Vo)
OV to Vee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
2.OVt06.0V
4.5Vto 5.5V
- 40"C to + 85"C
- 55"C to + 125"C
Minimum Input Edge Rate (IlV/M)
'AC Devices
VIN from 30% to 70% of Vee
Vee @3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (Il V / Ilt)
'ACT Devices
VIN from 0.8V to 2.OV
Vee @4.5V, 5.5V
125 mV/ns
175"C
140"C
Note 1: Absolute maximum ratings are values beyond which damage to the
device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' ACT Family Devices
74ACT
Symbol
Parameter
TA =
+ 25"C
Vee
(V)
54ACT
74ACT
TA =
TA =
Units
-55"C to + 125"C - 40"C to + 85"C
Conditions
Guaranteed Limits
Typ
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
or Vee - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = O.W
or Vee - O.lV
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
",A
VI
VI = VIL, VIH
Vo = Vee,GND
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input Leakage Current
loz
Maximum TRI-STATE
Current
5.5
leeT
Maximum
Icc/Input
5.5
10LD
tMinimum Dynamic
Output Current
10HD
Ice
Maximum Quiescent
Supply Current
0.001
0.001
±0.5
0.6
25'C is identical to 74ACT
1.6
1.5
mA
= VIL or VIH
-24mA
-24mA
10H
lOUT
= 50 ",A
'VIN
=
10L
VI
=
=
VIL or VIH
24mA
24mA
Vee,GND
Vee - 2.1Vtt
= 1.65V Max
= 3.85V Min
50
75
mA
VOLD
-50
-75
mA
VOHD
160.0
80.0
",A
VIN = Vee
orGND
5.5
@
/LA
'VIN
-50 ",A
5.5
8.0
• All outputs loaded; thresholds on input associated with output under test.
@
±5.0
=
5.5
tMaximum test duration 2.0 ms, one output loaded at a time.
Nole: Icc for 54ACT
±10.0
lOUT
25'C
ttMay be measured per the JEDEC alternate method.
4-192
AC Electrical Characteristics:
Symbol
Vcc·
Parameter
(V)
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25°C
Cl = 50pF
TA = -55°C
to + 125°C
Cl = 50pF
TA = -40°C
to +85°C
Cl = 50pF
Min
Min
Max
Min
Typ
Max
Max
Units
Fig.
No.
tplH
Propagation Delay
5.0
1.0
6.5
9.0
1.0
10.0
ns
2-3,4
tpHl
Propagation Delay
5.0
1.0
6.5
9.0
1.0
10.0
ns
2-3,4
tPZH
Output Enable Time
5.0
1.0
8.0
10.5
1.0
11.0
ns
2-5
tpZl
Output Enable Time
5.0
1.0
9.5
12.0
1.0
13.0
ns
2-6
tpHZ
Output Disable Time
5.0
1.0
9.5
12.0
1.0
13.0
ns
2-5
tpLZ
Output Disable Time
5.0
1.0
8.0
10.5
1.0
11.5
ns
2-6
'Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.OV
CPD
Power Dissipation
Capacitance
45.0
pF
Vee = 5.OV
-".
4-193
=
CD
C')
r---------------------------------------------------------------------~
~National
~ semiconductor
54ACT174ACT368
Hex Inverter Buffer with TRI-STATE® Outputs
General Description
Features
The 'ACT368 contains six independent inverting buffers with
TRI-STATE outputs.
• Outputs source/sink 24 mA
• 'ACT has TTL-compatible inputs
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEIIEC
Pin Assignment
for DIP, SOIC and Flatpak
Pin Assignment
for LeC and PCC
12 01 NC II 00
[[]11][[][[J1Il
III 10
mOE I
02 !II
10
GND Ii]]
NC [i]
°0
[TINC
~VCC
0slill
II
Isli]J
°1
12
\:::JofjOlo./'
1llI1mi1iEli]1iE
°2
04 14 NC 03 13
TL/F/l0690-2
13
°3
14
°4
15
TL/F/l0690-3
°5
TLlF/l0690-1
Function Table
Inputs
Output
L
L
H
Pin Names
0
OE
L
H
X
H
L
Z
lim 0E2
OE1,OE2
On
Description
Output Enable Input (Active LOW)
Input
Output
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
4-194
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage {Ved
DC loput Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage {Ved
'AC
'ACT
-0.5Vto +7.0V
Input Voltage (VI)
-20mA
+20mA
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-20mA
+20mA
-0.5V to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (lee or IGND)
±50mA
OV to Vee
OVtoVee
Output Voltage (VO)
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
2.0Vt06.0V
4.5Vto 5.5V
- 65·C to + 150·C
Storage Temperature (T8TG)
Junction Temperature (TJ)
175·C
CDIP
140·C
PDIP
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
- 40·C to + 85·C
- 55·C to + 125·C
Minimum Input Edge Rate (aV/at)
'AC Devices
VIN from 30% to 70% of Vee
Vee @3.3V, 4.5V. 5.5V
125 mV/ns
Minimum Input Edge Rate (aV/at)
'ACT Devices
VIN from 0.8V to 2.OV
Vee @4.5V, 5.5V
125 mV/ns
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics
for 'ACT Family Devices
54ACT
74ACT
Symbol
Parameter
Vee
(V)
TA = +25·C
74ACT
TA=
TA=
Units
-55·C to + 125·C - 400C to + 85·C
Typ
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = -50p.A
·VIN = VIL or VIH
-24mA
10H
-24mA
lOUT = 50p.A
·VIN = VIL or VIH
24mA
10L
24mA
liN
Maximum Input Leakage Current
5.5
±0.1
±1.0
±1.0
p.A
VI = Vee.GND
loz
Maximum TRI·STATE
Current
5.5
±0.5
±10.0
±5.0
p.A
VI = Vlb VIH
Vo = Vee,GND
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4·195
DC Electrical Characteristics
Symbol
Vee
(V)
Parameter
for 'ACT Family Devices (Continued)
74ACT
54ACT
74ACT
TA = +25·C
TA=
-55·C to + 125·C
TA =
- 40·C to + 85·C
Typ
ICCT
Maximum
Iccllnput
IOLD
tMinimum Dynamic
Output Current
IOHD
5.5
Maximum Quiescent
Supply Current
Icc
Units
Conditions
Guaranteed Limits
0.6
1.6
1.5
mA
VI = Vcc - 2.1V
tt
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
160.0
80.0
/LA
VIN= Vee
orGND
5.5
8.0
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
ttMay be measured per the JEDEC Alternate Method.
Note: Icc for 54ACT @ 25'C is identical to 74ACT @ 25'C.
AC Electrical Characteristics:
Symbol
Vee·
(V)
Parameter
Min
74ACT
54ACT
74ACT
TA = +25·C
CL = 50pF
TA = -55·C
to + 125·C
CL = 50pF
TA = -40·C
to +8SOC
CL = 50pF
Max
9.0
10.0
ns
2-3,4
6.0
9.0.
1.0
10.0
ns
2-3,4
B.O
10.0
1.0
11.0
ns
2-5
B.O
12.0
1.0
13.0
ns
2-6
1.0
9.0
12.0
1.0
13.0
ns
2-5
1.0
B.5
11.0
1.0
12.0
ns
2-6
1.0
tpHL
Propagation Delay
5.0
1.0
tpzH
Output Enable Time
5.0
1.0
tPZL
Output Enable Time
5.0
1.0
tpHZ
Output Disable Time
5.0
tpLZ
Output Disable Time
5.0
Max
6.5
Min
Max
'Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Fig.
No.
1.0
5.0
Typ
Units
Min
Propagation Delay
tpLH
See Section 2 for Waveforms
AC/ACT
Units
Conditions
VCC = 5.0V
Typ
CIN
Input Capacitance
4.5
pF
CPO
Power Dissipation
Capacitance
40.0
pF
4-196
VCC = 5.0V
r-------------------------------------------------------------------------,
~ Semiconductor
54AC/74AC373 49 54ACT /7 4ACT373
Octal Transparent latch with TRlaSTATE® Outputs
General Description
Features
The 'AC/'ACT373 consists of eight latches with TRI-STATE
outputs for bus organized system applications. The flip-flops
appear transparent to the data when latch Enable (lE) is
HIGH. When lE is lOW, the data that meets the setup time
is latched. Data appears on the bus when the Output Enable
(OE) is lOW. When OE is HIGH, the bus output is in the
high impedance state.
II Eight latches in a single package
IJ TRI-STATE outputs for bus interfacing
tI Outputs source/sink 24 mA
III 'ACT373 has TTL-compatible inputs
c Standard Military Drawing (SMD)
- 'AC373: 5962-87555
-'ACT373:5962-87556
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIIEC
OE
OE
1
LE
00
2
19
°7
°0
0,
3
18
°7
4
17
Os
0,
5
16
Os
DO
°0
0,
0,
O2
03
04
Vee
°2
03
°2
6
15
°s
O2
7
14
°5
°4
03
8
13
°4
°3
9
12
°4
GNO
10
11
LE
°5
06
°5
°7
°7
Os
TL/F/9958-3
TL/F/995B-2
Pin Names
.....
~
~National
TL/F/9958-1
~
Description
Pin Assignment
forlCC
Data Inputs
latch Enable Input
Output Enable Input
TRI-STATE latch Outputs
03D:z 02 0, 0,
00 [l]OOOO!I]
G~~~D~~
LE IIlI
OJ OE
04 Ii]]
0, ~
!iID07
~Vcc
~1iID1i§J1ilI1iID
DsOs0606~
TLlF/9958-4
4-197
.... r------------------------------------------------------------------------------------------,
~
~
Functional Description
Truth Table
The 'AC/'ACT373 contains eight D-type latches with TRISTATE standard outputs. When the Latch Enable (LE) input
is HIGH, data on the Dn inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance mode
but this does not interfere with entering new data into the
latches.
Inputs
Outputs
LE
OE
On
On
X
H
L
L
L
X
L
H
Z
L
H
X
00
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
00 = Previous 00 before HIGH to Low transition of Latch Enable
Logic Diagram
TL/F/9958-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-198
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
-0.5Vto +7.0V
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (lee or IGNO)
±50mA
-65'C to + 150'C
Storage Temperature (TSTG)
2.0Vt06.0V
4.5Vt05.5V
Input Voltage (VI)
OV to Vee
Output Voltage (VO)
OVtoVee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage (Vecl
'AC
'ACT
-40'Cto + 85'C
-55'C to + 125'C
Minimum Input Edge Rate (AV/At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (A V / At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design is reliable over its power supply.
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA =
-40'Cto +S5'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
",A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
• All outputs loaded. thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
4·199
lOUT = -50 ",A
'VIN = VIL or VIH
-12mA
-24mA
IOH
-24mA
lOUT = 50 ",A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'Cto +85'C
Typ
loz
IOLD
IOHD
Icc
Maximum TRI-STATE®
Current
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
±10.0
±5.0
JJ-A
VI (OE) = VIL, VIH
VI = Vee,GND
Vo = Vee,GND
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHO = 3.B5V Min
160.0
BO.O
JJ-A
VIN = Vee
orGND
±0.5
5.5
B.O
5.5
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than
Icc for 54AC @ 25'C is identical to 74AC @ 25'C.
or equal to the respective limit
@
5.5V Vee.
DC Characteristics for' ACT Family Devices
74ACT
Symbol
Parameter
Vee
(V)
54ACT
TA = +25'C
74ACT
TA =
TA =
Units
-55'C to + 125'C - 40'C to + 85'C
Typ
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
0.8
0.8
O.B
O.B
V
VOUT = 0.1V
orVec - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.B6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = -50 JJ-A
·VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50".A
·VIN = VILorVIH
24mA
IOL
24mA
liN
Maximum Input Leakage Current 5.5
±0.1
±1.0
±1.0
".A
VI = Vee,GND
loz
Maximum TRI-STATE®
Current
5.5
±0.5
±10.0
±5.0
".A
VI = VIL, VIH
Vo = Vee,GND
leeT
Maximum
lecllnput
5.5
1.6
1.5
mA
IOLD
tMinimum Dynamic
Output Current
5.5
50
75
mA
YOLO = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
160.0
BO.O
".A
VIN = Vee
orGND
IOHD
Icc
Maximum Quiescent
Supply Current
5.5
0.6
B.O
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT @
25'C is identical to 74ACT
@
25'C.
4-200
VI = Vee - 2.1V
AC Electrical Characteristics:
Symbol
Parameter
Vee·
(V)
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
On to On
3.3
5.0
1.5
1.5
10.0
7.0
13.5
9.5
1.0
1.0
16.5
11.5
1.5
1.5
15.0
10.5
ns
2·3,4
tpHL
Propagation Delay
Onto On
3.3
5.0
1.5
1.5
9.5
7.0
13.0
9.5
1.0
1.0
16.0
11.5
1.5
1.5
14.5
10.5
ns
2·3,4
tpLH
Propagation Delay
LEtoOn
3.3
5.0
1.5
1.5
10.0
7.5
13.5
9.5
1.0
1.0
16.5
12.0
1.5
1.5
15.0
10.5
ns
2·3,4
tpHL
Propagation Delay
LEtoOn
3.3
5.0
1.5
1.5
9.5
7.0
12.5
9.5
1.0
1.0
15.0
11.0
1.5
1.5
14.0
10.5
ns
2·3,4
tPZH
Output Enable Time
3.3
5.0
1.5
1.5
9.0
7.0
11.5
B.5
1.0
1.0
14.0
10.5
1.0
1.0
13.0
9.5
ns
2·5
tPZL
Output Enable Time
3.3
5.0
1.5
1.5
B.5
6.5
1t.5
B.5
1.0
1.0
13.5
10.0
1.0
1.0
13.0
9.5
ns
2·6
tpHZ
Output Disable Time
3.3
5.0
1.5
1.5
10.0
B.O
12.5
11.0
1.0
1.0
16.0
13.5
1.0
1.0
14.5
12.5
ns
2·5
tpLZ
Output Disable Time
3.3
5.0
1.5
1.5
B.O
6.5
11.5
B.5
1.0
1.0
13.0
10.5
1.0
1.0
12.5
10.0
ns
2-6
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements:
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Parameter
Vee·
(V)
ts
Setup Time, HIGH or LOW
Dn to LE
3.3
5.0
3.5
2.0
5.5
4.0
6.5
5.0
6.0
4.5
ns
2-7
th
Hold Time, HIGH or LOW
Dn to LE
3.3
5.0
-3.0
-1.5
1.0
1.0
1.0
1.0
1.0
1.0
ns
2-7
3.3
5.0
4.0
2.0
5.5
4.0
6.5
5.0
6.0
4.5
ns
2-3
Symbol
Typ
LE Pulse Width,
HIGH
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is S.OV ±O.SV
tw
Guaranteed Minimum
4-201
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
5.0
2.5
8.5
10.0
1.0
12.5
1.5
11.5
ns
2-3,4
Propagation Delay
DntoOn
5.0
2.0
8.0
10.0
1.0
12.5
1.5
11.5
ns
2-3,4
tpLH
Propagation Delay
LEtoO n
5.0
2.5
8.5
11.0
1.0
12.5
2.0
11.5
ns
2-3,4
tpHL
Propagation Delay
LE to On
5.0
2.0
8.0
10.0
1.0
11.5
1.5
11.5
ns
2-3,4
tpZH
Output Enable Time
5.0
2.0
8.0
9.5
1.0
11.5
1.5
10.5
ns
2-5
tPZL
Output Enable Time
5.0
2.0
7.5
9.0
1.0
11.0
1.5
10.5
ns
2-6
tpHZ
Output Disable Time
5.0
2.5
9.0
11.0
1.0
14.0
2.5
12.5
ns
2-5
Output Disable Time
tpLZ
'Voltage Range 5.0 is S.OV ± O.SV
5.0
1.5
7.5
8.5
1.0
11.0
1.0
10.0
ns
2-6
Units
Fig.
No.
tpLH
Propagation Delay
DntoOn
tpHL
AC Operating Requirements:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Typ
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to LE
5.0
3.0
7.0
8.5
8.0
ns
2-7
th
Hold Time, HIGH or LOW
Dnto LE
5.0
0
0
1.0
1.0
ns
2-7
5.0
2.0
7.0
8.5
8.0
ns
2-3
LE Pulse Width, HIGH
tw
'Voltage Range 5.0 Is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
40.0
pF
4-202
Vee = 5.0V
, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , (0)
......
"'"
~National
~ Semiconductor
54AC/7 4AC37 4 • 54ACT17 4ACT37 4
Octal D Flip-Flop with TRI-STATE® Outputs
General Description
Features
The 'ACI'ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and TRI-STATE outputs for bus-oriented applications. A
buffered Clock (CP) and Output Enable (OE) are common to
all flip-flops.
EI
Buffered positive edge-triggered clock
II TRI-STATE outputs for bus-oriented applications
I!II Outputs source/sink 24 rnA
II See '273 for reset version
II See '377 for clock enable version
• See '373 for transparent latch version
II See '574 for broadside pinout version
• See '564 for broadside pinout version with inverted
outputs
iii 'ACT374 has TTL-compatible inputs
II Standard Military Drawing (SMD)
- 'AC374: 5962-87694
- 'ACT374: 5962-87631
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEEIiEC
Pin Assignment
for DIP, Flatpak and SOIC
liE
CP
CP
liE
OE
TL/F/9959-1
°0
20
Vee
19
°7
07
2
DO
°0
01
DO
°1
4
17
O2
01
06
°1
5
16
°6
°2
O2
6
15
7
14
°5
05
8
13
04
12
°4
CP
03
°2
03
04
°4
05
°5
06
03
°6
07
03
°7
GNO
18
10
11
TL/F/9959-2
TLiF19959-3
Pin Names
Do-D7
CP
OE
0 0- 0 7
Description
Pin Assignment
for LCC and PCC
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
TRI-STATE Outputs
03~~0101
[ID
III [IJ[IHIl
moo
0 3 [ID
GNO [j]J
CP [j]
1Il00
lIlliE
gQ]Voc
°4 (g[
04 [j]J
[lID 07
1lllli]][i])[Z)@]
Os
05 ° 6 06
DJ
TL/F/9959-4
4-203
•
..... r---------------------------------------------------------------------------------,
~
CW)
Truth Table
Functional Description
The' ACt' ACT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and TRI-STATE true outputs.
The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of
their individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the eight
flip-flops are available at the outputs. When the OE is HIGH,
the outputs go to the high impedance state. Operation of
the OE input does not affect the state of the flip-flops.
Outputs
Inputs
Dn
CP
OE
On
H
L
../
../
X
X
L
L
H
H
L
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
.../ = LOW-to-HIGH Transition
Logic Diagram
TL/F/9959-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-204
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
DC Output Source
or Sink Current (10)
DC Vee or Ground Current
per Output Pin (ICC or IGNO)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
PDIP
Supply Voltage (Vee)
'AC
'ACT
-0.5Vto +7.0V
2.0Vto 6.0V
4.5Vt05.5V
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-20mA
+20mA
-0.5V to Vee + 0.5V
-20mA
+20mA
-0.5V to to Vee + 0.5V
OVtoVee
OVtoVee
-40'Cto +85'C
- 55'C to + 125'C
Minimum Input Edge Rate (/::.V/M)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (!;'V/!;.t)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
±50mA
±50mA
-65'Cto +150'C
125 mV/ns
125 mV/ns
175'C
140'C
Nate 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply.
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = O.W
or Vee - O.W
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.W
or Vee - O.W
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
",A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
'All outputs loaded; thresholds on input associated with
output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-205
lOUT = -50 ",A
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50 ",A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Maximum TRI-STATE®
Current
loz
tMinimum Dynamic
Output Current
IOLD
IOHD
Maximum Quiescent
Supply Current
Icc
Conditions
Guaranteed Limits
±0.5
5.5
Units
±10.0
±5.0
/LA
VI (OE) = Vil. VIH
VI = Vee. GND
Vo = Vee.GND
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vee
orGND
8.0
5.5
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Icc @ 3.0V are guaranteed to be less than
Icc for S4AC @2S'C is identical to 74AC @ 2S'C.
Nole: liN and
or equal to the respective limit
@
S.SV Vee.
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
Vil
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
/LA
loz
Maximum TRI-STATE@
Current
5.5
±0.5
±10.0
±5.0
/LA
leeT
Maximum
leellnput
5.5
1.6
1.5
mA
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.6
lOUT = 50/LA
'VIN = Vil or VIH
24mA
IOl
24mA
VI = Vee.GND
VI = Vil. VIH
Vo = Vee.GND
VI = Vee - 2.1V
50
75
mA
VOlD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vee
orGND
8.0
5.5
• All outputs loaded; thresholds on input associated with output under test.
@
'VIN = Vil or VIH
-24mA
IOH
-24mA
5.5
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: ICC for S4ACT
lOUT = - 50 /LA
2S'C is identical to 74ACT
@2S'C.
4-206
AC Electrical Characteristics:
See Section 2 for waveforms
74AC
Symbol
Parameter
Vee'
(V)
TA = +2S'C
CL = SOpF
Max
S4AC
74AC
TA = -SS'C
to + 12S'C
CL = SO pF
TA = -40'C
to +8S'C
CL = SOpF
Min
Max
Min
Units
Fig.
No.
Max
Min
Typ
f max
Maximum Clock
Frequency
3.3
5.0
60
100
110
155
tpLH
Propagation Delay
CPtoO n
3.3
5.0
3.0
2.5
11.0
8.0
13.5
9.5
1.0
1.0
16.5
12.0
1.5
1.5
15.5
10.5
ns
2-3,4
tpHL
Propagation Delay
CPtoO n
3.3
5.0
2.5
2.0
10.0
7.0
12.5
9.0
1.0
1.0
15.0
11.0
2.0
1.5
14.0
10.0
ns
2-3,4
tPZH
Output Enable Time
3.3
5.0
3.0
2.0
9.5
7.0
11.5
8.5
1.0
1.0
14.0
10.5
1.5
1.0
13.0
9.5
ns
2-5
tPZL
Output Enable Time
3.3
5.0
2.5
2.0
9.0
6.5
11.5
8.5
1.0
1.0
14.0
10.5
1.5
1.0
13.0
9.5
ns
2-6
tpHZ
Output Disable Time
3.3
5.0
3.0
2.0
10.5
8.0
12.5
11.0
1.0
1.0
16.0
12.5
2.0
2.0
14.5
12.5
ns
2-5
tpLZ
Output Disable Time
3.3
5.0
2.0
1.5
8.0
6.5
11.5
8.5
1.0
1.0
13.0
10.5
1.0
1.0
12.5
10.0
ns
2-6
Units
Fig.
No.
60
95
60
100
MHz
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± O.SV
AC Operating Requirements:
See Section 2 for waveforms
74AC
S4AC
74AC
TA = +2S'C
CL = SO pF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SO pF
Symbol
Parameter
Vee'
(V)
ts
Setup Time, HIGH or LOW
Dn toCP
3.3
5.0
2.0
1.0
5.5
4.0
6.5
5.0
6.0
4.5
ns
2-7
th
Hold Time, HIGH or LOW
Dn toCP
3.3
5.0
-1.0
a
1.0
1.5
1.0
1.5
1.0
1.5
ns
2-7
tw
CP Pulse Width,
HIGH or LOW
3.3
5.0
4.0
2.5
5.5
4.0
6.5
5.0
6.0
4.5
ns
2-3
Typ
Guaranteed Minimum
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
4-207
AC Electrical Characteristics:
Symbol
Vee·
(V)
Parameter
See Section 2 for waveforms
74ACT
S4ACT
74ACT
TA = +2SoC
CL = SOpF
TA = -SsoC
to + 12SoC
CL=SOpF
TA = -40°C
to +8SoC
CL = SOpF
Min
Min
Min
Typ
Max
Max
Units
Fig.
No.
Max
f max
Maximum Clock
Frequency
5.0
100
160
tpLH
Propagation Delay
CPtoO n
5.0
2.0
8.5
10.0
1.0
12.0
2.0
11.5
ns
2·3,4
tpHL
Propagation Delay
CPtoO n
5.0
2.0
8.0
9.5
1.0
11.5
1.5
11.0
ns
2-3,4
tPZH
Output Enable Time
5.0
2.0
8.0
9.5
1.0
11.5
1.5
10.5
ns
2·5
tPZL
Output Enable Time
5.0
1.5
8.0
9.0
1.0
11.5
1.5
10.5
ns
2·6
tpHZ
Output Disable Time
5.0
1.5
8.5
11.5
1.0
13.0
1.0
12.5
ns
2·5
Output Disable Time
'Voltage Range 5.0 Is 5.0V ±0.5V
5.0
1.5
7.0
8.5
1.0
11.0
1.0
10.0
ns
2-6
Units
Fig.
No.
tpLZ
AC Operating Requirements:
Vee·
(V)
90
70
MHz
See Section 2 for waveforms
74ACT
S4ACT
74ACT
TA = +2SoC
CL = SOpF
TA = -SsoC
to + 12SoC
CL == SOpF
TA = -40"C
to +8SoC
CL = SOpF
Symbol
Parameter
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
1.0
5.0
8.S
5.5
ns
2-7
th
Hold Time, HIGH or LOW
Dn to CP
5.0
0
1.5
1.5
1.5
ns
2-7
5.0
2.5
5.0
8.5
5.0
ns
2-3
Typ
CP Pulse Width,
HIGH or LOW
'Voltage Range 5.0 is 5.0V ±0.5V
tw
Guaranteed Minimum
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CpD
Power Dissipation
Capacitance
80.0
pF
4-208
Vee = 5.0V
,----------------------------------------------------------------------------, ......
......
~
~National
~ Semiconductor
54AC/74AC377 • 54ACT17 4ACT377
Octal D Flip-Flop with Clock Enable
General Description
Features
The 'AC/'ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and
outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
II Ideal for addressable register applications
The register is fully edge-triggered. The state of each Dinput, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's
output. The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable operation.
II Buffered common clock
a
a
II Clock enable for address and data synchronization
applications
iii Eight edge-triggered D flip-flops
• Outputs source/sink 24 rnA
III See '273 for master reset version
II See '373 for transparent latch version
1:1 See '374 for TRI-STATE® version
III 'ACT377 has TTL-compatible inputs
IJ Standard Military Drawing (SMD)
--'AC377:5962-BB702
-- 'ACT377: 5962-B7697
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEEIIEC
Pin Assignment
for DIP, Flatpak and SOIC
CE
CE
CP
cp
CE
00
0,
Do
0,
03
04
04
Os
Os
0&
0&
~
07
2
20
Ycc
19
07
07
18
DO
O2
03
O2
TL/F/9961-1
00
0,
4
17
0,
5
16
08
08
02
O2
15
Os
7
14
03
8
13
Os
04
12
04
11
CP
03
GNO
10
TL/F/9961-2
TLlF/9961-3
Pin Names
Do-D7
CE
0 0- 0 7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
Pin Assignment
for LCC
~1l:l020,0,
IIllIllIlrnJl±l
rn
III Do
03
GNO Il])
CP IIil
°4
°4
[2Joo
ITJCE
1il1
~Ycc
1rn
1m 07
1i1I1i]J1i]J1lZi1i]J
DsOsO&O&~
TL/F/9961-4
4-209
•
Mode Select·Functlon Table
Inputs
Operating Mode
Outputs
CP
CE
On
Qn
Load '1'
.../
L
H
H
Load '0'
.../
L
L
L
Hold (Do Nothing)
.../
X
H
H
X
X
No Change
No Change
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
.../ = LOW·ta-HIGH Clock Transition
Logic Diagram
CP
0,
0,
0,
0,
0,
0,
TL/F/9961-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4·210
Co)
Absolute Maximum Rating (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage {Vecl
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
Supply Voltage {Vecl
'AC
'ACT
-0.5Vto +7.0V
DC Input Diode Current {Iu
Va = -0.5V
Va = Vee + 0.5V
2.0Vt06.0V
4.5Vt05.5V
-65'C to + 150'C
-40"Cto +85'C
- 55'C to + 125'C
Minimum Input Edge Rate (/lV//lt)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (/lV//lt)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design Is reliable over Its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'C to + 85'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - O.IV
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.5
0.5
0.5
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
p.A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under test
tMaximum test duration 2.0 ms, one output loaded at a time.
4-217
lOUT = -50 p.A
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50p.A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vcc,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Vee
Parameter
(V)
74AC
54AC
74AC
TA=
+ 25'C
TA=
-55'C to + 125'C
TA =
-40'Cto +85'C
Typ
tMinimum Dynamic
Output Current
IOLD
IOHD
Maximum Quiescent
Supply Current
ICC
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
80.0
40.0
/LA
VIN = VCC
orGND
5.5
4.0
• All outputs loaded; thresholds on input associated with output under test.
tMaxlmum test duration 2.0 ms. one output loaded at a time.
Note: liN and lee @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
lee for 54AC @ 25'C is Identical to 74AC @ 25'C.
AC Electrical Characteristics:
Symbol
Vee'
Parameter
(V)
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50 pF
TA = -40'C
to +85'C
CL = 50pF
Min
Min
Min
Typ
f max
Maximum Clock
Frequency
3.3
5.0
125
160
160
200
tpLH
Propagation Delay
CPtoOn
3.3
5.0
2.5
1.5
8.5
6.0
11.0
8.0
1.5
1.5
12.0
9.0
2.5
1.5
12.5
9.0
ns
2-3,4
Propagation Delay
CP to On
'Voltage Range 3.3 Is 3.3V ± 0.3V
Voltage Range 5.0 Is 5.0V ± 0.5V
3.3
5.0
2.5
1.5
8.0
5.5
10.5
7.5
1.5
1.5
12.0
7.5
2.5
1.5
11.0
8.0
ns
2-3,4
tpHL
AC Operating Requirements:
Max
Max
Fig.
No.
Units
95
95
Max
110
145
MHz
See Section 2 for Waveforms
74AC
54AC
74AC
TA= +2S'C
CL = SOpF
TA = -55'C
to + 12S'C
CL = SOpF
TA = -40'C
to + 85'C
CL = 50pF
Fig.
Parameter
Vee'
(V)
ts
Setup Time, HIGH or LOW
Dn to CP
3.3
5.0
1.5
1.0
3.0
2.0
4.0
4.0
3.5
2.5
ns
2-7
th
Hold Time, HIGH or LOW
Dn to CP
3.3
5.0
1.0
1.0
2.0
2.0
4.0
4.0
2.0
2.0
ns
2-7
ts
Setup Time, HIGH or
LOW,EtoCP
3.3
5.0
0
0
2.0
2.0
2.5
2.5
2.0
2.0
ns
2-7
th
Hold Time, HIGH or
LOW,EtoCP
3.3
5.0
1.0
1.0
2.0
2.0
4.0
4.0
2.0
2.0
ns
2-7
tw
CP Pulse Width
HIGH or LOW
3.3
5.0
3.0
2.0
4.5
3.5
6.5
6.5
5.5
4.0
ns
2-3
Symbol
Typ
Units
Guaranteed Minimum
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
No.
Typ
Units
Conditions
CIN
Input Capacitance
Parameter
4.5
pF
Vee = 5.OV
CPO
Power Dissipation Capacitance
28
pF
Vee = 5.OV
4·218
~---------------------------------------------------------------------------. ~
CD
CD
~National
~ Semiconductor
54ACT17 4ACT399
Quad 2-Port Register
General Description
Features
The 'ACT399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is
accepted. The selected data enters the flip-flop on the rising
edge of the clock.
•
•
•
•
Select inputs from two data sources
Fully positive edge-triggered operation
Outputs source/sink 24 mA
'ACT399 has TTL-compatible inputs
Ordering Code: See Section B
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and sOle
s
Vee
Qa
Qd
lOa
3
14
'Od
'la
4
13
'ld
'lb
5
12
'lc
11
'Oc
Qc
'Ob
Qb
7
GND
8
10
CP
TUF/9789-3
Pin Assignment
for lee
'Db 'lb NC 'la lOa
[!J[[J[§]rn:l1ll
0b lID
GNDIi]f
NCIIil
CPIi1!
0c Ii]
rnOa
mS
~
~
~
~
[IlNC
~VCC
~
fj]f°d
-~I'III'II,
1iJ!1l]I1i]f1IZl1i]f
'Dc 'lc Ne 'ld'O.
TL/F/9789-2
Pin Names
S
CP
lOa-lad
11a-11d
Qa-Qd
Description
Common Select Input
Clock Pulse Input
Data Inputs from Source 0
Data Inputs from Source 1
Register True Outputs
4-219
II
CD
~
r------------------------------------------------------------------------------------------,
Function Table
Functional Description
Inputs
The 'ACT399 is a high-speed quad 2-port register. It selects
four bits of data from either of two sources (Ports) under
control of a common Select input (S). The selected data is
transferred to a 4-bit output register synchronous with the
LOW-to-HIGH transition of the Clock input (CP). The 4-bit
D-type output register is fully edge-triggered. The Data inputs (lOx, 11x) and Select input (S) must be stable only a
setup time prior to and hold time after the LOW-to-HIGH
transition of the Clock input for predictable operation ..
5
10
L
L
H
H
L
H
X
X
Outputs
11
CP
Q
Q
X
X
L
H
../
L
H
L
H
H
L
H
L
../
../
../
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
../" = LOW·to·HIGH Clock Transition
Logic Diagram
10a--------.,
11a
-----+----+--1-1
10b--------++-I
11b
--------+-I--I
10.----------1~H
11.
--------++-1
IOd--------++-I
11d
-----------I
cp--------------------------1
TLlF/9789-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-220
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
'AC
'ACT
-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
-20mA
+20mA
-20mA
+20mA
-0.5V to Vee + 0.5V
DC Output Source or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
±50mA
- 65'C to + 150'C
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
PDIP
Input Voltage (VI)
OV to Vee
Output Voltage (Vo)
OV to Vee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
2.0Vt06.0V
4.5Vto 5.5V
- 40'C to + 85'C
- 55'C to + 125'C
Minimum Input Edge Rate (A V / At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125mV/ns
Minimum Input Edge Rate (A V / At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
+175'C
+140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system deSign is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics for' ACT Family Devices
54ACT
74ACT
TA =
- 55'C to + 125'C
TA =
- 40'C to + 85'C
74ACT
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee -0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.85
3.70
4.70
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
J)-A
VI
=
Vee,GND
=
Vee -2.1V
Symbol
TA
=
25'C
Guaranteed Limits
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
Conditions
Units
V
V
lOUT
=
'VIN
IOH
= VIL or VIH
lOUT
= 50 J)-A
'VIN
IoL
= VIL or VIH
-50 J)-A
-24mA
-24mA
24mA
24mA
liN
Maximum Input
Leakage Current
leeT
Maximum Icc/Input
5.5
1.6
1.5
mA
VI
10LD
tMinimum DynamiC
Output Current
5.5
50
75
mA
VOLD
5.5
-50
-75
mA
VOHD
Maximum Quiescent
Supply Current
5.5
160
80
J)-A
VIN = Vee
or Ground
10HD
Icc
0.6
8.0
*All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2,0 ms, one output loaded at a time,
Note:
Icc for the 54ACT device is identicel
to the
74ACT device at 25'C.
4-221
= 1.65VMax
= 3.85V Min
•
AC Electrical Characteristics:
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25°C
Vee = +5.0V
CL = 50pF
TA. Vee = Mil
CL = 50pF
TA. Vee = Com
CL = 50pF
Fig.
No.
Parameter
Vee'
(V)
Min
Typ
fmax
Input Clock Frequency
5.0
165
' 160
tpLH
Propagation Delay
CPtoQ
5.0
1.5
7.0
8.0
10.0
1.5
8.5
ns
2-3,4
5.0
2.0
6.0
9.0
10.0
2.0
9.5 '
ns
2-3,4
Symbol
Propagation Delay
CPtoQ
'Vortage Range 5.0 is 5.0V ± 0.5V
tpHL
AC Operating Requirements:
Max
Parameter
Vee'
(V)
Max
Min
90
Max
MHz
160
See Section 2 for Waveforms
74ACT
Symbol
Min
Units
TA = +25°C
CL = 50pF
74ACT
54ACT
TA = -55"Cto + 125°C TA = -400Cto +85°C
CL = 50pF
CL=50pF
Units
Fig.
No.
Guaranteed Minimum
Typ
ts
Setup Time, HIGH or LOW
In toCP
5.0
3.0
2.5
3.5
2.5
ns
2-7
th
Hold Time, HIGH or LOW
In toCP
5.0
0
1.0
3.0
1.0
ns
2-7
ts
Setup Time, HIGH or LOW
StoCP
5.0
3.0
4.0
6.0
4.0
ns
2-7
th
Hold Time, HIGH or LOW
StoCP
5.0
-1.0
0.5
2.5
0.5
ns
2-7
5.0
5.5
3.5
5.0
3.5
ns
2-3
CP Pulse Width
HIGH or LOW
'Vortage Range 5.0 is 5.0V ± 0.5V
tw
Capacitance
Typ
Units
Conditions
CrN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation Capacitance
30
pF
Vee = 5.0V
Symbol
Parameter
4·222
r----------------------------------------------------------------------------,
en
N
o
~National
~ Semiconductor
54AC/74AC520 • 54ACT /7 4ACT520
8-Bit Identity Comparator
General Description
Features
The 'AC/'ACT520 are expandable 8-bit comparators. They
compare two words of up to eight bits each and provide a
LOW output when the two words match bit for bit. The expansion input jA ~ B also serves as an active LOW enable
input.
• Compares two 8-bit words in 6.5 ns typ
• Expandable to any word length
III 20-pin package
III Outputs source/sink 24 mA
II 'ACT520 has TIL-compatible inputs
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
I I I I I I I I I I I I I III
'-./
TA=S- 1
20 I-Vcc
Ao- 2
191-°A=S
80 -
3
18 1-87
A1-
4
171-A7
8 1-
5
16 .... 86
A2 -
6
15 t-As
IEEEIIEC
82 -
7
14 t-85
COMP
A3 -
8
13 t-A5
I>
83 -
9
12 t-84
TL/F/10194-1
TA=s....I::I Gl
Ao- 0
GND- 10
11 t-A4
AI TLlF/10194-2
A2 -
A3 -
Pin Assignment
forlCC
A4 -
A3 82 A2 81 AI
1]]1II1]][§J[IJ
A5 -
AsA7 80 -
~
7
83 1]]
GND [Q]
A4 [j]
8 4 1i1l
0
81 -
82 83 -
I
III
~[j]]1lli1lZl1lli
85AsB6A7~
...7_ _ _ _- '
TLlF/10194-3
TL/F/10194-4
Pin Names
[j]J °A=8
~
85 -
Ao-A7
Bo-B7
TA ~ B
OA ~ B
mAo
[j] TA=s
~vcc
A5~
Q
84 -
8s 87 -
mBo
Description
Word A Inputs
Word B Inputs
Expansion or Enable Input
Identity Output
4-223
Truth Table
Inputs
Outputs
iA= B
A,B
OA=B
L
L
H
H
A = B'
A#B
A = B'
A#B
L
H
H
H
H = HIGH Vollage level
l = lOW Vollage level
'Ao = 80. AI = 810 A2 = 82. etc.
Logic Diagram
Vee
Ao
A,
A2
A3
A4
As
A6
A7
TA=B
TUF/l0194-5
Please note that this diagram Is provided only for the underslanding of logic operations and should not be used to estimate propagation delays.
4-224
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee)
DC Input Diode Current (111<>
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + O.5V
DC Output Voltago (Vo)
Supply Voltage (Vee)
'AC
'ACT
Input Voltage (VI)
Output Voltage (Vo)
-20mA
+20mA
-0.5VtoVee + 0.5V
OV to Vee
OV to Vee
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (tNI':\t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (.:\V/.:\t)
'ACT Devices
VIN from 0.8V to 2.0V
Vcc @ 4.5V, 5.5V
-20mA
+20mA
-0.5VtoVee + 0.5V
DC Output Source
or Sink Current (10)
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
PDIP
2.0Vt06.0V
4.5Vt05.5V
±50mA
±50mA
-65·Cto + 150·C
- 40·C to + 85·C
- 55"C to + 125·C
125mVlns
125 mVlns
175·C
140"C
NOle 1: Absolute maximum ratings are those values beyond which damage
10 the device may occur. The databock specKications should be met. without
excoptlon. to onsure Ihallhe system design is reliable over its power supply,
tomporaturo. and output/Input loading variables. National does not recommontl oporntlon of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
74AC
S4AC
74AC
TA = +2S·C
TA=
-S5"C to + 125"C
TA=
-40"Cto +8S·C
Parameter
Vee
(V)
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = O.W
orVec - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.W
orVce - O.lV
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
!LA
Typ
VIH
VIL
VOH
3.0
4.5
5.5
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
Units
Conditions
Guaranteed Limits
•All outputs loaded; thresholds on input associated wilh output under tesl
tMaximum lest duration 2.0 ms. one output loaded al a time.
4-225
lOUT = -50/LA
·VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50/LA
·VIN = VILorVIH
12mA
24mA
10L
24mA
VI = Vcc,GND
DC Characteristics for 'AC·Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25°C
TA =
- 55°C to + 125"C
TA =
-40°C to + 85°C
IOHD
Icc
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Conditions
Guaranteed Limits
TyP
IOLD
Units
5.5
50
75
rnA
VOLD = 1.65V Max
5.5
-50
-75
rnA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vee
orGND
5.5
8.0
·AII outputs loaded; thresholds on input assoclatod with output undor tost.
tMaximum test duration 2.0 ms, on. output loaded at a time.
Note: liN and Icc @ 3.0V are guaran1eed to b. less than or equal to the respective limit @ 5.5V Vcc.
ICC for 54AC @ 25"C is identical to 74AC @ 25"C.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +25°C
TA=
- 55°C to + 125°C
TA=
- 40°C to + 85°C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
orVcc - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
/LA
1.6
1.5
rnA
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
Units
Conditions
Guaranteed Umits
lOUT = -50/LA
'VIN = VIL or VIH
-24 rnA
-24 rnA
IOH
lOUT = 50/LA
'VIN
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.6
= VIL or VIH
24 rnA
24mA
IOL
VI
= Vcc,GND
VI = Vee - 2.1V
5.5
50
75
rnA
VOLD = 1.65VMax
5.5
-50
-75
rnA
VOHD
/LA
VIN = VCC
orGND
5.5
8.0
160.0
80.0
•All outputs loaded; thresholds on input associated with output under test
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT @ 25"C is Identical to 74ACT @ 25"C.
.,
4-226
.-
= 3.85V Min
AC Electrical Characteristics:
See Section 2 for Waveforms
74AC
S4AC
74AC
TA = +2S'C
Cl = SOpF
TA = -SS'C
to + 12S'C
Cl = SOpF
TA = -40'C
to +8S'C
Cl = SOpF
Parameter
Vcc'
(V)
Min
Typ
Max
Min
Max
Min
Max
Propagation Delay
An or Bn to OA = B
3.3
5.0
4.0
2.5
7.5
5.5
11.5
B.5
1.0
1.5
14.0
10.5
3.0
2.0
An or Bn to OA
Propagation Delay
=B
3.3
5.0
4.5
3.0
B.O
5.5
12.0
9.0
1.0
1.5
15.0
11.0
tpLH
Propagation Delay
iA = BtoOA = B
3.3
5.0
3.5
2.5
5.5
4.5
B.5
6.5
1.0
1.5
tpHL
Propagation Delay
iA = BtoOA = B
3.3
5.0
3.5
2.5
5.5
4.5
B.5
6.5
1.0
1.5
Symbol
tpLH
tpHL
Units
Fig.
No.
13.0
9.5
ns
2-3,4
3.5
2.5
13.5
10.0
ns
2-3,4
10.0
7.5
2.5
2.0
9.5
7.0
ns
2-3,4
10.5
B.O
2.5
2.0
9.5
7.0
ns
2-3,4
Units
Fig.
No.
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 Is S.OV ± O.SV
AC Electrical Characteristics:
Symbol
Parameter
Vcc'
(V)
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2S'C
Cl = SOpF
TA = -SS'C
to + 12S'C
Cl = SOpF
TA = -40'C
to +8S'C
Cl = SOpF
Min
Typ
Max
Min
Max
Min
Max
5.0
3.0
5.5
B.5
1.5
12.0
2.5
9.5
ns
2-3,4
Propagation Delay
=B
S.O
3.0
6.0
10.0
1.5
12.0
2.5
11.5
ns
2-3,4
tpLH
Propagation Delay
iA = BtcOA = B
5.0
2.0
4.0
6.0
1.5
B.5
2.0
6.5
ns
2-3,4
tpHL
Propagation Delay
iA = BtoOA = B
5.0
2.5
5.0
7.5
1.5
9.0
2.0
B.5
ns
2-3,4
tpLH
tpHL
Propagation Delay
An or Bn to OA = B
An or Bn to OA
'Voltage Range 5.0 is 5.0V ± O.SV
4·227
Capacitance
Typ
Units
Conditions
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
Vee = 5.0V
CPO
Power Dissipation Capacitance
40
pF
Vee = 5.0V
Applications
Ripple Expansion
Ao Bo
ENABLE
LOW
A7 B7
IA=B
As Bs
AtSB tS
IA=B
°A=S
At6 Bt6
A23 B23
IA=B
°A=B
°A=B
TLIF110194-6
Parallel Expansion
Ao Bo
A7 87
As B8
AtSB tS
AtSB tS
A23 B23
TLIF110194-7
4-228
r------------------------------------------------------------------------.~
....
N
~National
~ semiconductor
54AC/74AC521 • 54ACT/74ACT521
8-Bit Identity Comparator
General Description
Features
The 'AC/'ACT521 is an expandable 8-bit comparator. It
compares two words of up to eight bits each and provides a
LOW output when the two words match bit for bit. The expansion input iA = 8 also serves as an active LOW enable
input.
Compares two 8-bit words in 6.5 ns typ
II Expandable to any word length
II 20-pin package
II Outputs source/sink 24 mA
II 'ACT521 has TTL-compatible inputs
II
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and sOle
TLlF/9964-1
IEEE/IEC
CaMP
I>
TA=B
1
Vee
Ao
2
Bo
3
°A=B
B7
AI
4
BI
5
A2
6
15
A6
B2
7
14
Bs
A3
a
13
As
B3
9
12
B4
10
11
A4
GND
A7
16
B6
TL/F/9964-2
Pin Assignment
for lee
A3
liz Az
BI AI
~][IlIIl [[J ~
lP=Q
rn
[IlBo
B3
GND Ii]]
A4 1Iil
B41il1
AS Ii]
Q
[IlAo
IIITA=B
~Vee
I!ID°A=B
1i3li§[IDIi][ID
B5AsB6~~
TL/F/9964-4
Pin Names
Ao-A7
80- 8 7
TA = 8
OA= 8
Description
Word A Inputs
Word 8 inputs
Expansion or Enable Input
Identity Output
4-229
TL/F/9964-3
III
~
~
r-----------------------------------------------------------------------------------------~
Truth Table
Inputs
Outputs
iA = B
A,S
OA=B
L
L
H
H
A = B·
A¥oB
A = B·
A¥oB
L
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
'''0 = Bo. At = Bt. A2 = B2. etc.
Logic Diagram
Ao
80 - - [ > 0
A1
81- - [ > 0
A2
82 - - [ > 0
A3
83 - - [ > 0
A4
84 - - [ > 0
As
8s
--[>o
A6
86 - - [ > 0
A7
87 - - [ > 0
t>o---j
t>o---j
t>o---j
t>o---j
t>o---j
t>o---j
t>o---j
t>o---j
°A=B
TA=B
TLlF/9964-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4·230
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
Supply Voltage (Vecl
'AC
'ACT
-0.5Vto +7.0V
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
-20mA
+20mA
-20 rnA
+20mA
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50 rnA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
±50mA
Storage Temperature (T8m)
-65'C to + 150'C
Junction Temperature (TJ)
CDIP
PDIP
2.0Vt06.0V
4.5Vto 5.5V
Input Voltage (VI)
OV to Vee
Output Voltage (Va)
OV to Vee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
U1
N
-40'Cto +85'C
-55'C to + 125'C
Minimum Input Edge Rate (Il V lilt)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (Il V lilt)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
175'C
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design is reliable over its power supply,
temperature, output/input loading variables. National does not recommend
operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
=
+25'C
Typ
VIH
VIL
VOH
liN
74AC
TA =
-40'C to +85'C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
J1-A
3.0
4.5
5.5
VOL
54AC
TA =
-55'C to + 125'C
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4·231
lOUT
=
-50 J1-A
'VIN
=
VIL or VIH
-12mA
-24 rnA
-24 rnA
lOUT
=
50 J1-A
'VIN
=
VIL or VIH
12mA
24 rnA
24 rnA
IOH
IOL
VI
=
Vee,GND
III
....
N
&I)
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
S4AC
74AC
TA = +2S'C
TA=
-S5'C to + 125'C
TA=
-40'Cto +8S'C
Typ
IOLD
IOHD
Icc
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed LImits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
160.0
BO.O
p.A
VIN = Vee
orGND
5.5
B.O
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
Ice for 54AC @ 25'C is Identical to 74AC @ 25'C.
DC Characteristics for' ACT Family Devices
74ACT
54ACT
74ACT
TA = +2S'C
TA =
- 55'C to + 125'C
TA =
-40'Cto +8S'C
Parameter
Vee
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
O.B
0.8
O.B
O.B
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.B6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
±0.1
±1.0
±1.0
p.A
1.6
1.5
mA
Symbol
(V)
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
liN
Maximum Input
Leakage Current
5.5
ICCT
Maximum
leellnput
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.001
0.001
Conditions
Units
Guaranteed Limits
0.6
lOUT = - 50 p.A
'VIN = VIL or VIH
-24mA
-24mA
IOH
lOUT = 50/LA
'VIN = VIL or VIH
24mA
IOL
24mA
VI = Vee.GND
VI = Vce - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
BO.O
p.A
VIN = Vce
orGND
5.5
B.O
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT @ 25'C is Identical to 74ACT @ 25'C.
4-232
AC Electrical Characteristics:
UI
N
.....
See Section 2 for Waveforms
74AC
S4AC
74AC
TA = +2S'C
Cl = SOpF
TA = -SS'C
to + 12S'C
Cl = SOpF
TA = -40'C
to +8S'C
Cl = SOpF
Units
Fig.
No.
12.0
9.0
ns
2-3,4
3.5
2.5
12.5
9.0
ns
2-3,4
10.5
8.0
2.5
2.0
9.0
7.0
ns
2-3,4
10.5
8.0
2.5
2.0
9.0
7.0
ns
2-3,4
Units
Fig.
No.
Parameter
Vee'
(V)
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
An or Bn to DA = B
3.3
5.0
3.5
2.5
7.0
5.0
11.0
8.0
1.0
1.5
15.0
10.5
3.0
2.0
tpHL
Propagation Delay
An or Bn to DA = B
3.3
5.0
4.5
3.0
7.5
5.5
11.5
8.5
1.0
1.5
15.0
10.5
tpLH
Propagation Delay
iA = BtoDA = B
3.3
5.0
3.0
2.5
5.5
4.0
8.0
6.0
1.0
1.5
tpHL
Propagation Delay
iA = BtoDA = B
3.3
5.0
3.0
2.0
5.5
4.0
8.0
6.0
1.0
1.5
Symbol
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +25'C
Cl = SOpF
TA = -55'C
to + 12S'C
Cl = 50pF
TA = -40'C
to +85'C
CL = SOpF
Min
Typ
Max
Min
Max
Min
Max
5.0
3.0
5.5
9.0
1.5
11.0
2.5
9.5
ns
2-3,4
Propagation Delay
An or Bn to DA = B
5.0
3.0
6.0
10.0
1.5
12.0
2.5
11.0
ns
2-3,4
tpLH
Propagation Delay
iA = BtoDA = B
5.0
2.0
4.0
6.5
1.5
7.5
2.0
7.0
ns
2-3,4
tpHL
Propagation Delay
iA = BtoDA = B
5.0
2.5
5.0
7.5
1.5
8.5
2.0
8.0
ns
2-3,4
tpLH
Propagation Delay
An or Bn to DA = B
tpHL
'Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
Typ
Units
C'N
Input Capacitance
Parameter
4.5
pF
Vee
CPD
Power Dissipation Capacitance
40
pF
Vee
4-233
Conditions
=
=
5.0V
5.0V
,..
C'I
it)
,---------------------------------------------------------------------------------,
Applications
Ripple Expansion
AO BO
A7 B7
As Bs
A15 B15
ENABLE
LOW
TL/F/9964-6
Parallel Expansion
As Bs
A15 B15
TL/F/9964-7
4-234
.------------------------------------------------------------------------,
~
(0)
-'="
~National
~ Semiconductor
54ACT17 4ACT534
Octal D Flip-Flop with TRI-STATE® Outputs
General Description
Features
The 'ACT534 is a high-speed, low-power octal Ootype flipflop featuring separate Ootype inputs for each flip-flop and
TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all
flip-flops. The 'ACT534 is the same as the 'ACT374 except
that the outputs are inverted.
•
•
•
•
•
•
Edge-triggered Ootype inputs
Buffered positive edge-triggered clock
TRI-STATE outputs for bus-oriented applications
Outputs source/sink 24 rnA
'ACT534 has TIL-compatible inputs
Inverted output version of 'ACT374
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
BE
CP
OE
DO
0,
O2
TL/F/9965-1
BE
1
20
Vee
00
2
19
07
°0
DO
3
18
°1
01
0,
4
17
5
16
~
06
06
O2
6
°2
03
D3
15
05
D4
05
°4
D2
7
14
D5
°5
13
°6
D3
03
GND
8
06
07
9
12
D4
04
10
11
CP
°7
TLlF/9965-2
TL/F/9965-3
Pin Names
0 0- 0 7
CP
OE
'00 -'07
Description
Pin Assignment
forlCC
Oa1a Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
Complementary TRI-STATE Outputs
[I] [I] [I] [[][IJ
D3~020,D,
03 [IJ
GNO lim
[IJDo
[IJ 00
CP [j]
mBE
°4 1iID
BQlVee
1lID~
o.1l]]
1HI1rn1l]J1l1I1l]J
Ds0506D6~
TLlF/9965-4
4-235
•
~ r-------------------------------------------------------------------------------~
C')
an
Functional Description
The' ACT534 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE complementary
outputs. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold times requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Logic Diagram
TLlF/9965-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Function Table
Inputs
Output
CP
OE
0
0
../"
../"
L
X
L
L
L
H
H
L
L
H
X
X
00
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
.../" = LOW·to·HIGH Clock Transition
Z = High Impedance
(50 = Value stored from previous clock cycle
4-236
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Diode Current (11K)
VI = -0.5V
-20mA
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Va = -0.5V
-20mA
+20mA
Va = Vee + 0.5V
DC Output Voltage (Va)
-0.5V to to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGND)
Storage Temperature (TSTG)
- 65'C to + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
Supply Voltage (Vecl
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TpJ
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (Ll.V/Ll.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (Ll.V/Ll.t)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vt06.0V
4.5Vt05.5V
OVto Vee
OVtoVee
-40'Cto +85'C
-55'Cto +125'C
125 mV/ns
125 mV/ns
DC Characteristics for' ACT Family Devices
74ACT
Symbol
Parameter
Vee
(V)
54ACT
TA =
+ 25'C
74ACT
TA =
TA =
Units
- 55'C to + 125'C - 40'C to + 85'C
Typ
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0,1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT
= -50/LA
'VIN
= VIL or VIH
10H
-24mA
-24mA
lOUT
= 50/LA
'VIN
= VIL or VIH
10L
24mA
24mA
= Vee, GND
liN
Maximum Input Leakage Current
5.5
±0.1
±1.0
±1.0
/LA
VI
10Z
Maximum TRI-STATE®
Current
5.5
±0.5
±10.0
±5.0
/LA
VI = VIL, VIH
Va = Vee,GND
1.6
1.5
mA
Maximum
5.5
0.6
Icc/Input
'All oulputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
leeT
4-237
VI
= Vee - 2.1V
DC Characteristics for' ACT Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACT
S4ACT
74ACT
TA =
+2S'C
TA =
-SS'C to + 12S'C
TA=
-40'C to +SS'C
IOHD
Icc
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Conditions
Guaranteed Limits
Typ
IOLD
Units
5.5
SO
75
mA
VOlD = 1.6SV Max
5.5
-50
-75
mA
VOHD = 3.8SV Min
160.0
80.0
",A
VIN = Vcc
orGND
8.0
5.5
"All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT @ 25'C is identical to 74ACT @ 25'C.
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
Min
See Section 2 for waveforms
74ACT
S4ACT
74ACT
TA = +2S'C
Cl = SOpF
TA = -SS'C
to + 12S'C
Cl = SOpF
TA = -40'C
to +8S'C
Cl = SOpF
Typ
Max
Min
Max
Min
Units
Fig.
No,
Max
f max
Maximum Clock
Frequency
5.0
tpLH
Propagation Delay
CPtoQn
5.0
2.5
6.5
11.5
1.0
14.0
2.0
12.5
ns
2-3,4
tpHL
Propagation Delay
CPtoQn
5.0
2.0
6.0
10.5
1.0
13.0
2.0
12.0
ns
2-3,4
tpZH
Output Enable Time
5.0
2.5
6.5
12.0
1.0
14.0
2.0
12.5
ns
2-5
tpZL
Output Enable Time
5.0
2.0
6.0
11.0
1.0
13.0
2.0
11.5
ns
2-6
tpHZ
Output Disable Time
5.0
1.5
7.0
12.5
1.0
14.5
1.0
13.5
ns
2-5
Output Disable Time
tpLZ
'Voltage Range 5.0 is 5.0V ± 0.5V
5.0
1.5
5.5
10.5
1.0
11.5
1.0
10.5
ns
2-6
Units
Fig.
No.
100
AC Operating Requirements:
Symbol
Parameter
Vee'
(V)
85
120
MHz
See Section 2 for waveforms
74ACT
S4ACT
74ACT
TA = +2S'C
Cl = 50pF
TA = -SS'C
to + 12S'C
Cl = SO pF
TA = -40'C
to +S5'C
Cl = SOpF
Typ
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn toCP
5.0
1.0
3.5
5.0
4.0
ns
2-7
th
Hold Time, HIGH or LOW
Dn toCP
5.0
-1.0
1.0
3.0
1.5
ns
2-7
5.0
2.0
3.5
5.0
3.S
ns
2-3
CP Pulse Width
HIGH or LOW
'Voltage Range 5.0 is 5.0V ±0.5V
tw
4-238
, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , U1
Co)
.jlo.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
40.0
pF
4-239
Vee = 5.0V
C) r---------------------------------------------------------------------~----_,
-.:r
LI)
~National
~ Semiconductor
54AC/74AC540
Octal Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The 'AC540 is an octal buffer/line drivers designed to be
employed as memory and address drivers, clock drivers and
bus oriented transmitter/receivers.
These devices are similar in function to the 'AC240 while
providing flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes these devices especially useful as output ports for microprocessors,
allowing ease of layout and greater PC board density.
• TRI-STATE inverting outputs
• Inputs and outputs opposite side of package, allowing
easier interface to microprocessors
• Output source/sink 24 rnA
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
Pin Assignment
forLCC
Is's 14 13 '2
III IIlrnJ [ID[!]
OE,
10
00
10
II
12
13
14
Is
Is
17
°1
°2
°3
°4
°5
Os
GNDIl§
'3
14
Is
L
H
L
H
X
X
X
X
L
H
L
L
~VCC
lim 0E2
04°3°2°1°0
TLIFI9966-2
TLlFI9966-3
outputs
OE2
mOEI
~1iID1!ID1lZl1i]J
Truth Table
Inputs
IIlIa
°71l]
°slIID
osiij]
°7
TLIF19966-1
OEI
mil
'7 00
'I
12
L
Z
Z
H
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Immaterial
Z ~ High Impedance
4-240
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
-0.5Vto +7.0V
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (VO)
Supply Voltage (Vecl
'AC
'ACT
-20mA
+20mA
-0.5V to to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
±50mA
Storage Temperature (TSTG)
- 65'C to + 150'C
Junction Temperature (TJ)
CDIP
PDIP
Input Voltage (VI)
OVtoVee
Output Voltage (Vo)
OVtoVee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
2.OVt06.0V
4.5Vto 5.5V
- 40'C to + 85'C
-55'Cto +125'C
Minimum Input Edge Rate (.:l. V /.:l.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (.:l. V / .:l.t)
'ACT Devices
VIN from 0.8V to 2.OV
Vee @ 4.5V, 5.5V
125mV/ns
175'C
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not racom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
=
+25'C
Typ
VIH
VIL
VOH
liN
74AC
TA =
- 40'C to + 85'C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - O.lV
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.lV
or Vee - O.IV
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
I-'A
3.0
4.5
5.5
VOL
54AC
TA =
-55'C to + 125'C
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
.. All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-241
lOUT
= -
'VIN
=
VIL or VIH
-12mA
-24mA
-24mA
lOUT
=
5Ol-'A
'VIN
=
VIL or VIH
12mA
24mA
24mA
10H
10L
VI
=
5O I-'A
Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Vee
(V)
Parameter
74AC
S4AC
74AC
TA = +2S'C
TA=
-SS'C to + 12S'C
TA =
-40'C to +SS'C
Typ
Maximum TRI-STATE®
Current
loz
tMinimum Dynamic
Output Current
IOLD
IOHO
Maximum Quiescent
Supply Current
Icc
5.5
Units
Conditions
Guaranteed Limits
±0.5
±10.0
±5.0
p.A
VI (OE) = VIL, VIH
VI = Vee,GND
Vo = Vee,GND
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHO = 3.85V Min
160.0
80.0
p.A
VIN = Vee
orGND
5.5
8.0
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ S.SV Vee.
Icc for S4AC @ 2S'C is identical to 74AC @ 2S'C.
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
See Section 2 for Waveforms
74AC
S4AC
74AC
TA = +2SoC
CL = SOpF
TA = -SsoC
to + 12SoC
CL = SOpF
TA = -40'C
to +8SoC
CL = SOpF
Min
Typ
Max
Min
Max
Min
Max
Units
Fig.
No.
tpLH
Propagation Delay
Data to Output
3.3
5.0
1.5
1.5
5.5
4.0
7.5
6.0
1.0
1.0
9.0
7.0
1.0
1.0
8.0
6.5
ns
2-3,4
tpHL
Propagation Delay
Data to Output
3.3
5.0
1.5
1.5
5.0
4.0
7.0
5.5
1.0
1.0
8.0
6.5
1.0
1.0
7.5
6.0
ns
2-3,4
tPZH
Output Enable Time
3.3
5.0
3.0
2.0
8.5
6.5
11.0
8.5
1.0
1.0
13.0
10.0
2.5
2.0
12.0
9.5
ns
2-5
tpZL
Output Enable Time
3.3
5.0
2.5
2.0
7.5
6.0
10.0
7.5
1.0
1.0
12.0
9.0
2.0
1.5
11.0
8.5
ns
2-6
tpHZ
Output Disable Time
3.3
5.0
2.5
1.5
8.5
7.5
13.0
10.5
1.0
1.0
15.5
12.0
1.5
1.0
14.0
11.0
ns
2-5
tpLZ
Output Disable Time
3.3
5.0
2.5
1.5
7.0
6.0
10.0
8.0
1.0
1.0
12.0
10.0
2.0
1.5
11.0
9.0
ns
2-6
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range S.O is S.OV ± o.sv
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
Cpo
Power Dissipation
Capacitance
30.0
pF
Vee = 5.0V
4-242
,----------------------------------------------------------------------------.
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (10K)
Va = -0.5V
-20mA
+20mA
Va = Vee + 0.5V
DC Output Voltage (Va)
-0.5Vto to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGND)
Storage Temperature (T8m)
-65'Cto + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design Is reliable over its power supply,
temperature, and output/Input loading variables. National does not recom-
Supply Voltage (Vee)
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (aVlat)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (aVlat)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vt06.0V
4.5Vt05.5V
OVtoVee
OVtoVee
-40'Cto +85'C
-55'Cto + 125'C
125mV/ns
125 mV/ns
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' ACT Family Devices
Symboi
Parameter
Vee
(V)
74ACT
S4ACT
74ACT
TA = +2S'C
TA=
-sS'C to + 12S'C
TA =
- 40'C to + 8S'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = - 50 /LA
'VIN = VIL or VIH
-24mA
10H
-24mA
lOUT = 50/LA
'VIN = VIL or VIH
24mA
10L
24mA
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
/LA
10Z
Maximum TRI·STATE V,H
Vo = Vee. GND
ICCT
Maximum Icc/Input
5.5
1.6
1.5
rnA
V, = VCC - 2.1V
10LD
tMinimum Dynamic
Output Current
5.5
50
75
rnA
VOLD = 1.65V
5.5
-50
-75
rnA
VOHD = 3.S5V
160
SO
",A
Y,N = Vee
orGND
10HD
Icc
Maximum Quiescent
Supply Current
5.5
0.6
S.O
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for S4ACT @ 2S'C Is identical to 74ACT @ 25'C.
4-262
V, = Vee.GND
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74AC
S4AC
74AC
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 125'C
CL = SOpF
TA = -40'C
to +8S'C
CL = 50pF
Min
Min
Max
Max
Units
Fig.
No.
Min
Typ
fMAX
Maximum Clock
Frequency
3.3
5.0
75
95
112
153
tpLH
Propagation Delay
CPtoOn
3.3
5.0
3.5
2.0
8.5
6.0
13.5
9.5
1.0
1.0
16.5
11.5
3.5
2.0
15.0
11.0
ns
2-3,4
tpHL
Propagation Delay
CP to On
3.3
5.0
3.5
2.0
7.5
5.5
12.0
8.5
1.0
1.0
15.0
10.5
3.5
2.0
13.5
9.5
ns
2-3,4
tpZH
Output Enable Time
3.3
5.0
2.5
2.0
7.0
5.0
11.0
8.5
1.0
1.0
13.0
9.5
2.5
2.0
12.0
9.0
ns
2-5
tPZL
Output Enable Time
3.3
5.0
3.0
2.0
6.5
5.0
10.5
8.0
1.0
1.0
12.5
9.5
3.0
1.5
11.5
9.0
ns
2-6
tpHZ
Output Disable Time
3.3
5.0
3.5
2.0
7.5
6.0
12.0
9.5
1.0
1.0
14.0
11.0
2.5
1.5
13.0
10.5
ns
2-5
tpLZ
Output Disable Time
3.3
5.0
2.0
1.0
5.5
4.5
9.0
7.5
1.0
1.0
10.5
9.0
1.5
1.0
10.0
8.5
ns
2-6
55
80
Max
60
85
MHz
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 Is 5.0V ±0.5V
AC Operating Requirements:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25'C
CL = SOpF
TA = -5S'C
to + 125'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Typ
Units
Fig.
No.
Guaranteed Minimum
Is
Sel-Up Time, HIGH or LOW
Dnlo CP
3.3
5.0
0.5
0
2.5
1.5
3.0
2.0
3.0
2.0
ns
2-7
Ih
Hold Time, HIGH or LOW
Dn lOCP
3.3
5.0
-0.5
a
1.5
1.5
1.5
1.5
1.5
1.5
ns
2-7
CP Pulse Width
HIGH or LOW
3.3
5.0
3.5
2.0
6.0
4.0
7.5
5.5
7.0
5.0
ns
2-3
Iw
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
4-263
AC Electrical Characteristics:
Symbol
Parameter
Vee· ,
(VI
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2SoC
CL = SOpF
TA = -SsoC
to + 125"C
CL = SOpF
TA = -40"C
to +8SoC
CL = SOpF
Min
Min
Min
Typ
Max
Max
Units
Fig.
No.
Max
fMAX
Maximum Clock Frequency
5.0
100
110
tpLH
Propagation Delay
CPtoO n
5.0
2.5
7.0
11.0
1.0
13.5
2.0
12.0
ns
2-3,4
tpHL
Propagation Delay
CPtoOn
5.0
2.0
6.5
10.0
1.0
12.5
1.5
11.0
ns
2-3,4
tPZH
Output Enable Time
5.0
2.0
6.4
9.5
1.0
11.0
1.5
10.0
ns
2-5
tpzL
Output Enable Time
5.0
2.0
6.0
9.0
1.0
11.0
1.5
10.0
ns
2-6
tpHZ
Output Disable Time
5.0
2.0
7.0
10.5
1.0
12.0
1.5
11.5
ns
2-5
tpLZ
Output Disable Time
5.0
2.0
5.5
8.5
1.0
10.0
1.5
9.0
ns
2-6
Units
Fig.
No.
70
85
ns
'Voltage Range 5.0 is 5,OV ± 0.5V
AC Operating Requirements:
Symbol
Parameter
See Section 2 for Waveforms
Vee·
(V)
74ACT
S4ACT
74ACT
TA = +2SoC
CL = SOpF
TA = -SsoC
to + 12SoC
CL = SOpF
TA = -40"C
to +85"C
CL = SOpF
Typ
Guaranteed Minimum
ts
Set-Up Time, HIGH or LOW
On to CP
5.0
1.5
2.5
3.5
2.5
ns
2-7
th
Hold Time, HIGH or LOW
On to CP
5.0
-0.5
1.0
2.0
1.0
ns
2-7
5.0
2.5
3.0
5.0
4.0
ns
2-3
CP Pulse Width
HIGHorLOW
'Voltage Range 3,3 Is 3,3V ± 0.3V
Voltage Range 5,0 is 5,OV ± 0.5V
tw
Capacitance
Symbol
Typ
Units
CIN
Input Capacitance
Parameter
4.5
pF
Vee
CPO
Power Dissipation Capacitance
40.0
pF
Vee
4-264
Conditions
=
=
5.0V
5.0V
r--------------------------------------------------------------------------------,
~National
~ semiconductor
54AC/74AC646 • 54ACT /7 4ACT646
Octal Transceiver/Register with TRI-STATE® Outputs
General Description
Features
The 'AC/'ACT646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A
or B bus will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functions
available are illustrated in Figures 1-4.
•
•
•
•
•
•
•
Independent registers for A and B buses
Multiplexed real-time and stored data transfers
TRI-STATE outputs
300 mil slim dual-i.n-Iine package
Outputs source/sink 24 rnA
'ACT646 has TTL compatible inputs
Standard Military Drawing (SMD)
- 'AC646: 5962-89682
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
DIR
DIR
CPBA
CPAB
1
24
Vee
CPBA
SBA
CPAB
SAB
SAB
2
23
CPBA
DlR
3
22
SBA
Ao
4
21
G
A,
5
20
Bo
Ao
A2
6
19
B,
A,
7
18
B2
A.
8
17
B3
As
9
16
B.
A,
10
15
Bs
A,
II
14
B.
GND
12
13
TL/F/l0132-1
A,
A,
A,
A.
B7
TUF/l0132-3
As
Ae
Pin Assignment
for LCe and PCC
A,
As A. A, NC A2 A,
Ao
1l!I1!!!J[ID J!] izJ[!]J!]
TL/F110132-2
A.Jg]
[IJDIR
mSAB
A7 @]
GND IGJ
NC@]
B7 @]
Pin Names
CPAB,CPBA
SAB,SBA
G
DIR
Description
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
mCPAB
[DNC
Iiilvee
B.1lZI
~CPBA
B5 @]
Iiil SBA
~!JO{:JUIOIvV
IlIDI!llJalliilliilf!llliil
B4 B,B2 NCB,B D G
TLlF/l0132-4
4-265
en
0l:Io
en
CD
~
CD
Real Time Transfer
A·Bus to B·Bus
Real TIme Transfer
B·Bus to A·Bus
Storage from
Bus to Register
A-Bus
A-Bus
A-Bus
!~JIi~
M
~
•
!~a~
B-Bus
TLlF/l0132-7
B-Bus
TL/F/l0132-9
TLlF/l0132-8
FIGURE 1
FIGURE 3
FIGURE 2
.~OR8
A-Bus,
~
B-Bus
Transfer from
Register to Bus
-
....-~
~
B-Bus
TL/F/l0132-10
FIGURE 4
Function Table
Data 1/0·
Inputs
Function
G DIR CPAB CPBA SAB SBA Ao-A7 Bo-B7
H
H
H
X
X
X
H or L H or L
../
X
X
../
L
L
L
L
H
H
H
H
../
HorL
../
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
../
HorL
../
X
X
X
L
L
H
H
X
X
X
X
X
X
X
X
X
Isolation
Clock An Data into A Register
Clock Bn Data into B Register
Input
Input
Input
Output
X
An to Bn-Real Time (Transparent Mode)
Clock An Data into A Register
A Register to Bn (Stored Mode)
Clock An Data into A Register and Output to Bn
L
L
H
H
Input
Bn to An-Real Time (Transparent Mode)
Clock Bn Data into B Register
B Register to An (Stored Mode)
Clock Bn Data into B Register and Output to An
X
Output
'The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e.. data at the bus
pins will be stored on every LOW·to·HIGH transition of the appropriate clock inputs.
H ~ HIGH Voltage Level
X ~ Immaterial
L = LOW Voltage Level
..r = LOW·to·HIGH Trans~ion
Logic Diagram
OIR-~~""';~r--------------'
-.....,h
....
CPBA------+----:::---::----1~>---
s~ ....--~------r_----~=>O~I:>
CPAB -----__."~~__.
~8-....~----_r+--~
Do
c",Io---I-+-+
TO 7 OTHER CHANNn.s
TLlF/l0132-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4·266
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Diode Current (Illd
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
-0.5Vto to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
±50mA
Storage Temperature (Tsm)
2.0Vto 6.0V
4.5Vt05.5V
Input Voltage (VI)
OVtoVee
Output Voltage (Va)
OVtoVee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
Supply Voltage (Vecl
'AC
'ACT
- 65·C to + 150·C
-40·C to + 85·C
-55·C to + 125·C
Minimum Input Edge Rate (aV/At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (aV/at)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
175·C
CDIP
PDIP
140"C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception. to ensure that the system design is reliable over its power supply,
temperature, and outputlinput loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25·C
TA=
- 55·C to + 125·C
TA=
- 40·C to + 85·C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
orVee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
p.A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under test
tMaximum test duration 2.0 ms, one output loaded at a time.
4-267
lOUT = -50 p.A
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50p.A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
DC Characteristics for' AC .Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
loz
10LD
10HD
Maximum TRI-STATEIt
Current
tMlnimum Dynamic
Output Current
Icc
Maximum Quiescent
Supply Current
10ZT
Maximum I/O
Leakage Current
Conditions
±5.0
/LA
VI (OE) = VIL. VIH
VI = Vee. VGND
Vo = Vee. GND
Guaranteed Limits
±0.5
5.5
Units
±10.0
~~
5.5
50
75
mA
VOLD
5.5
-50
-75
mA
VOHD = 3.85V Min
1.65V Max
5.5
8.0
160.0
80.0
/LA
VIN = Vee
orGND
5.5
±0.6
±11.0
±6.0
/LA
VI (OE) = VIL. VIH
VI = Vee.GND
Vo = Vee.GND
•All outputs loaded; thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time,
Nole: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vcc.
Icc for 54AC @ 25'C is identical to 74AC @ 25'C.
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +25'C
TA=
- 55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
O.B
O.B
O.B
O.B
O.B
V
VOUT = 0.1V
or Vee - O.lV
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.B6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = -50/LA
·VIN = VIL or VIH
-24mA
-24mA
IOH
lOUT = 50/LA
·VIN = VIL or VIH
24mA
10L
24mA
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
/LA
loz
Maximum TRI-STATEIt
Leakage Current
5.5
±0.5
±10.0
±5.0
/LA
VI = VIL. VIH
Vo = Vee.GND
IOCT
Maximum
lee"nput
5.5
1.6
1.5
mA
VI = Vee - 2.1V
IOLD
tMinimum Dynamic
Output Current
10HD
Icc
Maximum Quiescent
Supply Current
10ZT
Maximum I/O
Leakage Current
0.6
VI = Vee.GND
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
5.5
B.O
160.0
BO.O
/LA
VIN = Vee
orGND
5.5
±0.6
±11.0
±6.0
/LA
VI (OE) = VIL. VIH
VI = Vee.GND
Vo = Vcc.GND
•All outputs loaded; thresholds on input essoclated with output under test
tMaxlmum test duration 2.0 ms. one output loaded at a time.
Nole: Icc for 54ACT @ 25'C is identical to 74ACT @ 25'C.
4-268
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee'
(V)
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay
Clock to Bus
3.3
5.0
4.0
2.5
10.5
7.5
16.5
12.0
1.0
1.0
20.0
14.0
3.0
2.0
18.5
13.0
ns
2·3,4
tpHL
Propagation Delay
Clock to Bus
3.3
5.0
3.0
2.0
9.5
6.5
14.5
10.5
1.0
1.0
17.5
12.0
2.5
1.5
16.0
11.5
ns
2·3,4
tpLH
Propagation Deley
Busto Bus
3.3
5.0
2.5
1.5
7.5
5.0
12.0
B.O
1.0
1.0
15.0
10.0
2.0
1.0
13.5
9.0
ns
2·3,4
tpHL
Propagation Delay
Bus to Bus
3.3
5.0
1.5
1.5
7.5
5.0
12.5
9.0
1.0
1.0
14.5
9.5
1.5
1.0
13.5
9.5
ns
2·3,4
tpLH
Propagation Delay
SBA or SAB to An or Bn
(wi An or Bn HIGH or LOW)
3.3
5.0
2.0
1.5
8.5
6.0
13.5
10.0
1.0
1.0
17.0
12.0
1.5
1.5
15.5
11.0
ns
2·3,4
Propagation Delay
SBA or SAB to An or Bn
(wi An or Bn HIGH or LOW)
3.3
5.0
1.5
1.5
8.5
6.0
13.5
10.0
1.0
1.0
17.0
12.0
1.5
1.5
15.0
11.0
ns
2·3,4
tpZH
Enable Time
'GtoAnorBn
3.3
5.0
2.5
1.5
7.0
5.0
11.5
8.5
1.0
1.0
13.0
9.5
2.0
1.5
12.5
9.0
ns
2·5
tpZL
Enable Time
'GtoAnorBn
3.3
5.0
2.5
1.5
7.5
5.5
12.5
9.0
1.0
1.0
15.5
11.0
2.0
1.5
14.0
10.0
ns
2·6
tpHZ
Disable Time
'GtoAnorBn
3.3
5.0
3.0
2.0
8.0
6.5
12.5
10.0
1.0
1.0
14.0
11.5
2.5
2.0
13.5
11.0
ns
2·5
tpLZ
Disable Time
'GtoAnorB n
3.3
5.0
2.0
1.5
7.5
6.0
12.0
9.5
1.0
1.0
13.5
11.0
2.0
1.5
13.5
10.5
ns
2·6
tpZH
Enable Time
DIR to An or Bn
3.3
5.0
2.0
1.5
6.5
5.0
11.0
7.5
1.0
1.0
14.5
10.5
1.5
1.0
12.0
8.5
ns
2·5
tPZL
Enable Time
DIR to An or Bn
3.3
5.0
2.5
1.5
7.0
5.0
11.5
8.0
1.0
1.0
16.0
12.5
2.0
1.0
13.0
9.0
ns
2·6
tpHZ
Disable Time
DIR to An or Bn
3.3
5.0
2.5
1.5
7.5
5.5
11.5
9.5
1.0
1.0
14.5
12.0
1.5
1.5
12.5
10.0
ns
2·5
tpLZ
Disable Time
DIR to An or Bn
3.3
5.0
1.5
1.5
7.5
5.5
12.0
9.5
1.0
1.0
16.5
12.0
1.5
1.5
13.5
10.5
ns
2·6
Units
Fig.
No.
tpHL
'Voltage Range 3.3 Is 3.3V ±O.3V
Voltage Range 5.0 is 5.0V ±O.5V
AC Operating Requirements:
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +2S'C
CL = 50pF
TA = -55'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = 50pF
Parameter
Vee'
(V)
ts
Setup Time, HIGH or LOW
Busto Clock
3.3
5.0
2.0
1.5
5.0
4.0
6.0
4.5
5.5
4.5
ns
2·7
th
Hold Time, HIGH or LOW
Busto Clock
3.3
5.0
-1.5
-0.5
0
0.5
1.5
2.0
0
1.0
ns
2·7
lw
Clock Pulse Width
HIGH or LOW
3.3
5.0
2.0
2.0
3.5
3.5
5.0
5.0
4.5
3.5
ns
2·3
Symbol
Typ
Guaranteed Minimum
'Voltage Range 3.3 is 3.3V ± O.3V
Voltage Range 5.0 is 5.0V ± 0.5V
4·269
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee·
(V)
74ACT
S4ACT
74ACT
TA = +2SoC
CL = SOpF
TA = -SsoC
to + 12SoC
CL = SOpF
TA - -40"C
to +8SOC
CL=SOpF
Min
Min
Max
Fig.
No.
Min
Typ
Max
5.0
6.0
12.0
14.5
3.0
16.0
ns
2·3,4
Propagation Delay
Clock to Bus
5.0
6.0
12.0
14.5
3.5
16.0
ns
2-3,4
tpLH
Propagation Delay
Busto Bus
5.0
4.5
8.5
10.5
2.5
11.5
ns
2·3,4
tpHL
Propagation Delay
Busto Bus
5.0
5.0
8.5
10.5
2.0
11.5
ns
2-3,4
tpLH
Propagation Delay
SBA or SAB to An to Bn
(w/An or Bn
HIGH or LOW)
5.0
5.0
9.5
11.5
2.5
12.5
ns
2-3,4
Propagation Delay
SBA or SAB to An to Bn
(w/Anor Bn
HIGH or LOW)
5.0
5.0
9.5
11.5
2.5
12.5
ns
2-3,4
tPZH
Enable Time
GtoAnorBn
5.0
6.0
9.0
11.0
1.5
12.0
ns
2-5
tPZL
Enable Time
GtoAnorBn
5.0
5.0
9.0
11.0
3.0
12.0
ns
2-6
tpHZ
Disable Time
GtoAnorBn
5.0
7.5
10.5
13.0
4.5
14.5
ns
2-5
tpLZ
Disable Time
GtoAnorBn
5.0
5.5
10.0
12.5
3.0
14.0
ns
2-6
tpZH
Enable Time
DIR to An or Bn
5.0
5.5
6.5
10.5
1.5
11.5
ns
2-5
tPZL
Enable Time
DIR to An or Bn
5.0
4.0
6.5
10.5
3.0
11.5
ns
2-6
tpHZ
Disable Time
DIR to An or Bn
5.0
5.5
8.5
12.5
4.5
13.5
ns
2·5
5.0
4.0
8.5
12.5
3.0
13.5
ns
2·6
tpLH
Propagation Delay
Clock to Bus
tpHL
tpHL
Disable Time
DIR to An or Bn
'Voltage Range 5.0 is 5.0V ± 0.5V
tpLZ
AC Operating Requirements:
Symbol
Parameter
Vee·
(V)
Max
Units
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2SoC
CL = SOpF
TA = -SSOC
to + 12SOC
CL=SOpF
TA = -40"C
to +8SOC
CL=SOpF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
BUSto Clock
5.0
2.5
7.0
8.0
ns
2-7
th
Hold Time, HIGH or LOW
Bus to Clock
5.0
0
2.5
2.5
ns
2-7
5.0
4.5
7.0
8.0
ns
2-3
Clock Pulse' Width
HIGH or LOW
'Voltage Range 5.0 is 5,OV ± 0.5V
tw
4·270
Capacitance
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
ClIO
Input/Output Capacitance
15.0
pF
Vee = 5.0V
Cpo
Power Dissipation
Capacitance
60.0
pF
Vee = 5.0V
Symbol
4-271
co
"'II'
CD
r----------------------------------------------------------------------------,
~National
~ semiconductor
54AC/74AC648
Octal Transceiver/Register with TRI-STATE® Outputs
General Description
Features
The 'AC648 consists of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B
bus will be loaded into the respective registers on the LOWto-HIGH transition of the appropriate clock pin (CPAB or
CPBA). The four fundamental data handling functions available are illustrated in Figures 1 thru 4 (See Page 2).
•
•
•
•
•
•
Independent registers for A and B buses
Multiplexed real-time and stored data transfers
TRI-STATE outputs
300 mil slim dual-in-line package
Outputs source/sink 24 mA
Inverted data to output
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
ii
DlR
CPBA
SBA
CPAO
SAO
DlR
CPBA
SBA
CPAO
I
24
Vee
SAO
2
23
CPBA
DIR
3
22
SBA
At,
4
21
AI
5
20
ii
80
8,
82
83
8,
85
8.
87
Ao
TL/F/l0133-1
A,
A2
6
19
A3
A,
7
10
17
16
A5
A,
A.
A.
10
15
A7
11
14
GNO
12
13
A,
TLlF110133-3
As
Pin Assignment
for LCC and PCC
Ae
A5 A4 A3NC
A,
A:! A,
AD
1ilIIil!l[!l[!]IIl[!][!]
TL/F110133-2
A.1rn
A71il1
[!IOIR
mSAB
rn CPAO
GND 1m
Pin Names
AO-Pq
Bo-B7
CPAB,CPBA
SAB,SBA
DIR,G
Description
Data Register A Inputs,
Data Register A TRI-STATE Outputs
Data Register B Inputs,
Data Register B TRI-STATE Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Inputs
NC 1m
[]J NC
B, Ii!!
lllI vee
8.1iZ1
85 Ii!!
[lI CPOA
IiiISOA
~(J{J{:JOOJ7I'
Ii!!R!iI[lIIilIIiilIillIiil
8,83 82 NC 8, 80 ii
TL/FI10133-4
4-272
Function Table
Data 1/0'
Inputs
G
DIR
CPAB
CPBA
SAB
SBA
Ao-A7
Bo-B7
H
H
H
X
X
X
Horl
Horl
J
X
X
X
X
X
X
X
X
Input
Input
l
l
l
l
H
H
H
H
X
X
X
X
l
l
H
H
X
X
X
X
Input
Output
J
X
J
Horl
J
Function
Isolation
Clock An Data into A Register
Clock Sn Data into S Register
An to Sn-Real Time (Transparent Mode)
Clock An Data into A Register
A Register to Sn (Stored Mode)
Clock An Data into A Register and Output to Sn
L
X
X
X
L
Sn to An-Real Time (Transparent Mode)
l
X
l
L
J
X
l
Clock Sn Data into S Register
Output
Input
X
Horl
X
S Register to An (Stored Mode)
l
l
H
X
L
l
J
X
H
Clock Sn Data into S Register and Output to An
'The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus
pins will be stored on every LOW·to·HIGH transition of the clock inputs.
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X = Irrelevant
~ ~
LOW·to·HIGH Transition
Real Time Transfer
A-Bus to B-Bus
4
Real Time Transfer
B-Bus to A-Bus
4
~
A-BUS
t:JJI[:j
t:J1I[:j
B-BUS
B-BUS
~
4
4
~
TL/F/l0133-7
FIGURE 1
FIGURE 2
Storage from
Bus to Register
Transfer from
Register to Bus
4
4
~
~! I
~
B-BUS
4
I
Lft2
~
4
REG
II
I I
OR
B-BUS
TL/F/l0133-9
FIGURE 4
FIGURE 3
4-273
!
!~
REG
I
~
~
4
TL/F/l0133-8
~
A-BUS
A-BUS
GEG
4
~
A-BUS
TlIF/l0133-10
Logic Diagram
G---~CI
DIR--.....--L~
CPBA--------+-----------1
SBA--------+---~
CPAB--~
SAB-------+-+---1
1 OF 8 CHANNELS
ColO---+-+-t
AO
+--....+-+-.....
....++......--+BO
....+-+--(l!Co
.. - ----------------
-
-
----------------
-
..
TO 7 OTHER CHANNELS
TLlF/l0133-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-274
Absolute Maximum Rating (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee)
DC Input Diode Current (111<>
VI = -0.5V
-20mA
VI = Vee + 0.5V
+20mA
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
-20mA
Vo = Vee + 0.5V
+20mA
DC Output Voltage (VO)
-0.5V to to Vee + 0.5V
DC Output Source
±50mA
or Sink Current (10)
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGND)
Storage Temperature (T8TG)
-65'Cto + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design is reliable over its power supply,
temperature, and outputlinput loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
Recommended Operating
Conditions
Supply Voltage (Vecl
'AC
'ACT
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (~V/~t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (~V I ~t)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vto 6.0V
4.5Vto 5.5V
OVtoVee
OV to Vee
-40'Cto +85'C
- 55'C to + 125'C
125 mV/ns
125 mV/ns
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'Cto + 125'C
TA=
- 40'C to + 85'C
Typ
VIH
VIL
VOH
Guaranteed Limits
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
orVee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
±1.0
±1.0
/LA
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
Maximum Input
±0.1
5.5
Leakage Current
•All outputs loaded; thresholds on input associated wHh output under test.
tMaximum test duretion 2.0 ms, one output loaded at a time.
liN
Conditions
Minimum High Level
Input Voltage
3.0
4.5
5.5
VOL
Units
4·275
lOUT = -50/LA
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50/LA
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
DC Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA =
-55'C to + l25'C
TA=
-40'Cto + 85'C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Icc
Maximum Quiescent
Supply Current
IOZT
Maximum 1/0
Leakage Current
Conditions
VOLD = 1.65V Max
Guaranteed Limits
5.5
5.5
50
75
mA
-50
-75
mA
VOHD = 3.85V Min
5.5
8.0
160.0
80.0
p,A
VIN = Vee
orGND
5.5
±0.6
±11.0
±6.0
p,A
VI (OE) = VIL, VIH
VI = Vee, GND
Vo = Vee,GND
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Not.: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit
Icc for S4AC @ 2S'C is Identical to 74AC @ 2S'C.
AC Electrical Characteristics:
Symbol
Units
Parameter
@
S.SV Vee.
See Section 2 for Waveforms
Vcc·
(V)
74AC
54AC
74AC
TA = +25'C
CL = 50 pF
TA = -55'C
to + l25'C
CL = 50pF
TA = -40'C
to +.85'C
CL = 50pF
Min
Units
Fig.
No.
Min
Typ
Max
Min
Max
tpLH
Propagation Delay
Clock to Sus
3.3
5.0
1.5
1.5
10.0
7.0
15.5
11.0
1.5
1.5
17.0
12.0
ns
2·3,4
tpHL
Propagation Delay
Clock to Sus
3.3
5.0
1.5
1.5
8.5
6.0
13.5
10.5
1.5
1.5
14.5
11.5
ns
2-3,4
tpLH
Propagation Delay
Sus to Sus
3.3
5.0
1.5
1.5
6.0
4.0
10.0
7.0
1.5
1.0
11.0
7.5
ns
2-3,4
tpHL
Propagation Delay
Sus to Sus
3.3
5.0
1.5
1.5
5.5
3.5
9.0
7.5
1.5
1.0
10.0
8.0
ns
2-3,4
tpLH
Propagation Delay
SSA or SAS to An or Sn
(with An or Sn HIGH or LOW)
3.3
5.0
1.5
1.5
7.5
5.5
12.5
9.0
1.5
1.5
14.0
10.0
ns
2-3,4
Propagation Delay
SSA or SAS to An or Sn
(with An or Sn HIGH or LOW)
3.3
5.0
1.5
1.5
7.5
5.5
12.5
9.5
1.5
1.5
14.0
10.5
ns
2-3,4
Enable Time
GtoAnorSn
3.3
5.0
1.5
1.5
6.5
5.0
11.0
B.O
1.0
1.0
11.5
9.0
ns
2-5
tPZL
Enable Time
GtoAnorSn
3.3
5.0
1.5
1.5
7.0
5.0
11.0
8.0
1.0
1.0
12.5
9.0
ns
2-6
tpHZ
Disable Time
GtoAnorS n
3.3
5.0
1.5
1.5
7.5
6.0
12.0
10.0
1.0
1.0
13.0
11.0
ns
2-5
tpLZ
Disable Time
GtoAnorS n
3.3
5.0
1.5
1.5
7.0
5.5
11.5
9.0
1.0
1.0
12.5
10.0
ns
2-6
tpZH
Enable Time
DIR to An or Sn
3.3
5.0
1.5
1.5
6.0
4.5
12.5
9.5
1.0
1.0
14.0
10.5
ns
2-5
tpZL
Enable Time
DIR 10 An or Sn
3.3
5.0
1.5
1.5
6.5
4.5
13.0
9.0
1.5
1.0
14.5
10.5
ns
2-6
IpHZ
Disable Time
DIR to An or Sn
3.3
5.0
1.5
1.5
7.0
5.5
11.5
9.0
1.0
1.0
13.5
10.0
ns
2-5
3.3
5.0
1.5
1.5
7.0
5.0
13.5
9.5
1.5
1.0
15.0
10.0
ns
2-6
tpHL
tPZH
Disable Time
DIR to An or Sn
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range S.O is S.OV ±O.SV
tpLZ
4-276
Max
AC Operating Requirements:
See Section 2 for Waveforms
74AC
S4AC
74AC
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Parameter
Vcc'
(V)
ts
Setup Time, HIGH or LOW,
Bus to Clock
3.3
S.O
2.0
1.5
3.0
2.0
th
Hold Time, HIGH or LOW,
Bus to Clock
3.3
5.0
-1.5
-0.5
tw
Clock Pulse Width
HIGH or LOW
3.3
5.0
2.0
2.0
Symbol
Units
Fig.
No.
3.5
2.0
ns
2·7
0
1.0
0
1.0
ns
2·7
3.5
3.0
4.0
3.0
ns
2·3
Typ
Guaranteed Minimum
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Typ
Units
Conditions
Input Capacitance
4.5
pF
Vee = 5.0V
CpO
Power Dissipation Capacitance
65.0
pF
Vee = 5.0V
ClIO
Input/Output Capacitance
15.0
pF
Vee = 5.0V
CIN
Parameter
•
4·277
~r-----------------------------------------------------~
~
~National
ADVANCE INFORMATION
~ Semiconductor
54ACT17 4ACT705 Arithmetic Logic Unit for
Digital Signal Processing Applications
General Description
The 'ACT705 is a high-speed arithmetic processing integrated circuit which is packaged in an B4-pin leadless chip carrier. It features separate input buses that provide data and
instruction codes to a high-speed single-cycle 16-bit ALU
and an B-bit by B-bit parallel multiplier/accumulator.
The ALU is a 16-bit parallel design which supports sixteen
arithmetic and logic functions, as well as carry-in/out and
borrow-in/out. The multiplier/accumulator, which offers a
full 16-bit product, provides for unsigned, signed. mixed
mode and imaginary number multiplication. Product accumulation with sum and difference arithmetic is available in
each multiplier operating mode.
The 16-bit results of the ALU and multiplier/accumulator are
multiplexed to a single set of TRI-STATE~ output buffers.
The two ALU and multiplier/accumulator carry-out bits, as
well as the 4-bit status field indicating ALU and multiplier/
accumulator error conditions make up the remaining six bits
of the entire 22-bit output.
• 16-bit full ALU performs sixteen Boolean and arithmetic
functions with carry-in and carry-out
• B x B parallel multiplier supports unsigned, signed, complex or mixed mode multiplications, produces 16-bit result with carry-out
• Separate data and instruction buses allow instruction
fetches in parallel with execution-single cycle operation
• Accepts B- or 16-bit data and delivers a 16-bit output
• Data register bank configured to accept a combination
of B- or 16-bit data
• Separate clocks for ALU instruction. multiplier instruction, data, ALU accumulator and multiplier accumulator
registers
• Clustered clock pins for ease of board design
• 16-bit ALU/accumulator with feedback to ALU input
• Status of accumulator inputs is monitored: conditions
monitored include twos complement overflow. underflow or equal-to-zero
Features
Applications
•
•
•
•
• Voice-band signal processing
• Discrete Fourier transform applications
- FIR filters
-IIR filters
• Fast Fourier transform applications
- Spectrum analysis
- Speech recognition
B4-pin, PCC, CPGA
Outputs source/sink B mA
'ACT705 has TTL-compatible inputs
High throughput achieved with high degree of parallelism in the architecture
• Pipelined stages
• High-speed 16-bit ALU and an 8 x B complex multiplier
Connection Diagram
Pin Assignment for PCC
~~;;;;;~~~5~~~J~~~~~~
~
3332 31 30 29 28 27 28 25 2. 23 22 21 20 19 18 17 16 15 ,. 13 ,~,
ACour
3<1
DE
35
36
RMUX
ALUC,N
ALU3
ALU Z
ALU,
ALUO
WWUX
WUXO,
10
9
37
38
39
AIRCLK
40
4 WIRCLK
41
ACLK
42
WCLK
I DClK
43
WUXDo
44
84
MUXA 1
0,
45
83
WUXAo
06 46
82
~
05 .7
81
04
46
49
80
As
As
79
A4
50
51
78
77
"'3
A2
76
A,
61 62 63 64 65 66 67 68 69 70 71 72 73 7r5
An
~
D:!
0,
Do~~~/
,
~ ~ !i6 57 58 59 60
WUXC
~~3~J~~u8~~~m~~~~~~~~
2
22
TL/F/l0135-1
4-278
.------------------------------------------------------------------, .....
~
UI
•
~National
r3:
.....
~ Semiconductor
00
00
N
S4ACT17 4ACT71S e LM 1882
Programmable Video Sync Generator
General Description
Features
The 'ACT715/LM1882 is a 20-pin TTL-input compatible device capable of generating Horizontal, Vertical and Composite Sync and Blank signals for televisions and monitors. All
pulse widths are completely definable by the user. The device is capable of generating signals for both interlaced and
noninterlaced modes of operation. Equalization and serration pulses can be introduced into the Composite Sync signal when needed.
• Maximum Input Clock Frequency> 100 MHz
• Interlaced and non-interlaced formats available
• Separate or composite horizontal and vertical Sync and
Blank signals available
• Complete control of pulse width via register programming
• All inputs are TTL compatible
• 8 mA drive on all outputs
• Default RS170INTSC values mask programmed into
registers
• Orderable as linear device LM1882CN or LM1882CM
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
The 'ACT715/LM1882 makes no assumptions concerning
the system architecture. Line rate and field/frame rate are
all a function of the values programmed into the data registers, the status register, and the input clock frequency.
Ordering Code: See Section 8
Connection Diagrams
Pin Assignment for
DIP, Flatpak and sOle
'-../
0 1-
2
O2 03 -
3
18I-L/HBYTE
4
171-LOAO
04 -
5
1
Il-]- 8
13 r-HBLHOR
CLR- 9
12 I-VCBLANK
04 03
/
111111111111111
CLR III ~
GND [QJ ~
CLOCK
VCBLANK IilI ~
HBLHOR
~ m02
II rn 01
~ II] 00
II ~ Vee
~~
16 r-OOO/EVEN
14 r-VCSYNC
Os Os
lID [mIl [§:][I!
~~
15 r-HSYNVOR
05 - 6
0&- 7
·GNO- 10
lee
Il-]
20 r-Vcc
19 I-AOOR/OATA
00 -
Pin Assignment
for
"
~
l1'li
'''''''III
Ii]] AOOR/DATA
l1'li l1'li
IBJfrn@llill@l
U 15 1% Q
...
~~~g~
Ill-CLOCK
~ ~
TLlF/l0137-1
4-279
8
,...I
o
TL/F/l0137-2
Logic Block Diagram
ADDR/DATA
LHBYTE
LOAD
!;1""
~
CLR
...---1::>
~
""
E~-I:::>
ODD/EVEN
VCSYNC
VCBLANK
HBLHDR
L---1:> HSYNVDR
CLOCK 0_--1
TLlF/l0137-3
Pin Description
VCSYNC: Outputs Vertical or Composite Sync signal based
on value of the status Register.
There are a Total of 13 inputs and 5 outputs on the
'ACT715/LM1882.
Data Inputs DO-D7: The Data Input pins connect to the
Address Register and the Data Input Register.
ADDR/DATA: The ADDR/DATA Signal is latched into the
device on the falling edge of the LOAD Signal. The signal
determines if an address (0) or data (1) is present on the
data bus.
VCBLANK: Outputs Vertical or Composite Blanking signal
based on value of the Status Register.
HBLHDR: Outputs Horizontal Blanking Signal, Horizontal
Gating signal or cursor position based on value of the
Status Register.
HSYNVDR: Outputs Horizontal Sync Signal, Vertical Gating
signal or Vertical Interrupt signal based on value of Status
Register.
UHBYTE: The LlHBYTE Signal is latched into the device
on the falling edge of the LOAD signal. The signal determines if data will be read into the 8 LSB's (0) or the 4 MSB's
(1) of the Data Registers. A 1 on this pin when an ADDR/
DATA is a 0 enables Auto-Load Mode.
Register Description
All of the data registers are 12 bits wide. Width's of all pulses are defined by specifying the start count and end count
of all pulses. Horizontal pulses are specified with-respect-to
the number of clock pulses per line and vertical pulses ,are
specified with-respect-to the number of lines per frame.
LOAD: The Load control pin loads data into the Address or
Data Registers on the riSing edge. AlIDA/DATA and
LlHBYTE data is loaded into the device on the falling edge
of the clock. The Load pin has been implemented as a
Schmitt trigger input for better noise immunity.
REGO-STATUS REGISTER
CLOCK: System Clock input from which all timing is derived.
The clock pin has been implemented as a Schmitt trigger for
better noise immunity.
The Status Register controls the mode of operation, the
signals that are output and the polarity of these outputs.
CLR: The Clear pin is an asynchronous input that initializes
the device when it is high. Initialization consists of setting all
Bits 0-2
registers to their mask programmed values, and initializing
all counters, comparators and registers. The clear pin has
been implemented as a Schmitt trigger for better noise immunity.
ODD/EVEN: Output that identifies if display is in odd (HIGH)
or even (LOW) field of interlace when device is in interlaced
mode of operation. In noninterlaced mode of operation this
input is always HIGH. Data can be serially scanned out on
this pin during test mode.
4-280
B2 B1
EIo VCBLANK VCSYNC HBLHDR HSYNVDR
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
CBLANK
VBLANK
CBLANK
VBLANK
CSYNC
CSYNC
VSYNC
VSYNC
HGATE
HBLANK
HGATE
HBLANK
VGATE
VGATE
HSYNC
HSYNC
CBLANK
VBLANK
CBLANK
VBLANK
CSYNC
CSYNC
VSYNC
VSYNC
CURSOR
HBLANK
CURSOR
HBLANK
VINT
VINT
HSYNC
HSYNC
....
•
ri:
....
m
r----------------------------------------------------------------------,~
Register Description
U1
(Continued)
Bits 3-4
B4
B3
0
0
0
1
1
1
0
1
VERTICAL INTERRUPT SPECIFICATION REGISTERS
These Registers determine the width of the Vertical Interrupt signal if used.
Mode of Operation
Interlaced Double Serration and
Equalization
Non Interlaced Double Serration
Illegal State
Non Interlaced Single Serration
and Equalization
REG13- Vertical Interrupt Activate Time
REG14- Vertical Interrupt Deactivate Time
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating signals.
REG15- Horizontal Cursor Position Start Time
REG16- Horizontal Cursor Position End Time
Bits 5-8
Bits 5 through 8 control the polarity of the outputs. A value
of zero in these bit locations indicates a pulse active LOW.
A value of 1 indicates an active HIGH pulse.
B5-- VCBLANK Polarity
REG17- Vertical Cursor Position Start Time
REG18- Vertical Cursor Position End Time
B6- VCSYNC Polarity
B7- HBLHDR Polarity
Signal Specification
B8- HSYNVDR Polarity
HORIZONTAL SYNC AND BLANK
SPECIFICATIONS .
Bits 9-11
All horizontal Signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is considered
pulse 1 not O. The horizontal counters start at 1 and count
until HMAX. The value of HMAX must be divisible by 2. This
limitation is imposed because during interlace operation this
value is internally divided by 2 in order to generate serration
and equalization pulses at 2 x the horizontal frequency.
Horizontal signals will change on the falling edge of the
CLOCK signal. Signal specifications are shown below.
Horizontal Period (HPER) = REG(4) x ckper
Horizontal Blanking Width = [REG(3) - 11 x ckper
= [REG(2) - REG(1)1 x ckper
Horizontal Sync Width
Bits 9 through 11 enable several different features of the
device.
B9- Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
B10- Disable System Clock (0)
Enable System Clock (1)
B11- Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizontal Sync and Blank pulses.
Horizontal Front Porch
REG1- Horizontal Front Porch
REG2- Horizontal Sync Pulse End Time
REG3- Horizontal Blanking Width
REG4- Horizontal Interval Width
x ckper
All vertical signals are defined in terms of number of lines
per frame. This is true in both interlaced and noninterlaced
modes of operation. Care must be taken to not specify the
Vertical Registers in terms of lines per field. The vertical
counter starts at the value of 1 and counts until the value of
VMAX. No restrictions exist on the values placed in the vertical registers. Vertical Blank will change on the leading
edge of HBLANK. Vertical Sync will change on the leading
edge of HSYNC.
Vertical Frame Period (VPER) = REG(8) X hper
# of Clocks per Line
VERTICAL INTERVAL REGISTERS
The Vertical Interval Registers determine the number of
lines per frame, and the characteristics of the Vertical Blank
and Sync Pulses.
REG5- Vertical Front Porch
REG6- Vertical Sync Pulse End Time
REG7- Vertical Blanking Width
REG8- Vertical Interval Width
= [REG(1) - 11
VERTICAL SYNC AND BLANK SPECIFICATION
Vertical Field Period (VPER/n) = REG(8) X hper/n
Vertical Blanking Width = [REG(7) - 11 X hper/n
# of Lines per Frame
EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS
These registers determine the width of equalization and serration pulses and the vertical interval over which they occur.
Vertical Syncing Width = [REG(6) - REG(5)1 X hper/n
Vertical Front Porch = [REG(5) - 11 x hper/n
where n = 1 for noninterlaced
n = 2 for interlaced
REG 9- Equalization Pulse Width End Time
REG10- Serration Pulse Width End Time
COMPOSITE SYNC AND BLANK SPECIFICATION
Composite Sync and Blank signals are created by logically
ANDing (ORing) the active LOW (HIGH) signals of the corresponding vertical and horizontal components of these signals. The CompOSite Sync signal may also include serration
and/or equalization pulses. The serration pulse interval occurs in place of the Vertical Sync interval. Equalization puis-
REG11- Equalization/Serration Pulse Vertical
Interval Start Time
REG12- Equalization/Serration Pulse Vertical
Interval End Time
4-281
m
N
C'II
co
....co
:!!
.....
....•
In
....
Signal Specification (Continued)
es occur preceding and/or following the serration pulses.
The width and location of these pulses can be programmed
through the registers shown below.
CURSOR POSITION AND VERTICAL INTERRUPT
The Cursor Position and Vertical Interrupt signal are available when Composite Sync and Blank signals are selected
and bit 2 of the Status Register is set to the value of 1. The
cursor position generates a single pulse of n clocks wide
during every line that the cursor is specified. The signals are
generated by logically DRing (ANDing) the active LOW
(HIGH) signals specified by the registers used for generating Horizontal and Vertical Gating signals. The Vertical Interrupt signal generates a pulse during the vertical interval
specified. The Vertical Interrupt Signal will change in the
same manner as that specified for the Vertical Blanking signal.
Horizontal Cursor Width = [REG(16) - REG(15)) X ckper
Horizontal Equalization PW = [REG(9) - REG(1)1 x ckper
Horizontal Serration PW
= [REG(4)/n + REG(1)
REG(10)1 X ckper
-
Where n = 1 for noninterlaced single serration/equalization
n = 2 for noninterlaced double
serration/ equalization
n = 2 for interlaced operation
HORIZONTAL AND VERTICAL GATING SIGNALS
Horizontal and Vertical Gating Signals are available for use
when Composite Sync and Blank signals are selected and
the value of bit 2 of the status register is o. The Vertical
Gating signal will change in the same manner as that specified for the Vertical Blank.
Vertical Cursor Width = [REG(1B) - REG(17)1 X hper
Vertical Interrupt Width = [REG(14) - REG(13)) X hper.
Horizontal Gating Signal Width = [REG(16) - REG(15)1 X
ckper
Vertical Gating Signal Width
= [REG(1 B) - REG(17)) X
hper
SYSCK
HMAX
REG4
REG10
HMAX/2
TL/F/10137-4
FIGURE 1. Horizontal Waveform Specification
HBLANK
WAX
REGS
TLlF/10137-5
FIGURE 2. Vertical Waveform Specification
4-2B2
.....
....
r•
3:
....
co
U1
Addressing Logic
The register addressing logic is composed of two blocks of
logic. The first is the address register and counter
(ADDRCNTR), and the second is the address decode
(ADDRDEC).
Byte is written the address counter is incremented by 1. The
counter has been implemented to loop on the initial value
loaded into the address register. For example: If a value of 0
was written into the address register then the counter would
count from 0 to 18 before resetting back to O. If a value of
15 was written into the address register then the counter
would 'count from 15 to 18 before looping back to 15. If a
value greater than or equal to 18 is placed into the address
register the counter will continuously loop on this value.
Auto addressing is initiated on the falling edge of load when
ADDRDATA is 0 and LHBYTE is 1. Incrementing and loading of data registers will not commence until the falling edge
of LOAD after ADDRDATA goes to 1. The next rising edge
of LOAD will load the first byte of data. Auto Incrementing is
disabled on the falling edge of load after ADDRDATA and
LHBYTE goes low.
ADDRCNTR LOGIC
Addresses for the data registers can be generated by one of
two methods. Manual addressing requires that each byte of
each register that needs to be loaded needs to be addressed. To load both bytes of all 19 registers would require
a total of 57 Load cycles (19 Address and 38 Data cycles).
Auto Addressing requires that only the initial register value
be specified. The Auto Load sequence would require only
39 Load cycles to completely program all registers (1 Address and 38 Data). In the auto load sequence the low order
byte of the data register will be written first followed by the
high order byte on the next load cycle. At the time the High
co
N
07-DO
LOAD
AOOR/DATA
[/HBYTE
''''---_....../
--J/
,'-_ _ _ _ _
,
TL/F/l0137-7
Manual Addressing Mode
Cycle #
Load Falling Edge
1
Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
2
3
4
5
6
Load Rising Edge
Load Address m
Load Lbyte m
Load Hbyte m
Load Address n
Load Lbyte n
Load Hbyte n
07-DO
LOAD
,
,
ADDR/DATA
[/HBYTE
/
Auto Addressing Mode
Cycle #
Load Failing Edge
Load Rising Edge
1
2
Enable Auto Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing
Load Start Address n
Load Lbyte (n)
Load Hbyte (n); Inc Counter
Load Lbyte (n + 1)
Load Hbyte (n + 1); Inc Counter
Load Address
3
4
5
6
4-283
TL/F/l0137-8
II
Addressing Logic (Continued)
ADDRDEC LOGIC
Normal device operation can be resumed by latching in a
non-scan address. As the scanning of the registers is a nondestructive scan, the device will resume correct operation
from the point at which it was halted.
The ADDRDEC logic decodes the current address and generates the enable signal for the appropriate register. The
enable values for the registers and counters change on the
falling edge of LOAD. Since the data registers are disabled
at this time any overlap of enable signals will not cause
register data to change. The following Addresses are used
by the device.
Address 0
Status Register REGO
Address 1-18
Data Registers REG1-REG18
RS170 Default Register Values
The tables below show the values programmed for the
RS170 Format and how they compare against the actual
EIA RS170 Specifications. The default signals that will be
displayed are CSYNC, CBLANK, HDRIVE and VDRIVE. The
device initially starts at the beginning of the odd field of
interlace. All signals have active low pulses and the clock is
disabled at power up. Registers 13 and 14 are not involved
in the actual signal information. If the Vertical Interrupt was
selected a pulse indicating the active lines would be displayed.
Address 19-21 Unused
Address 22/54 Restart Vector {Restarts Device}
Address 23/55 Clear Vector {Zeros All Registers}
Address 24-31 Unused
Address 32-50 Register Scan Addresses
Address 51-53 Counter Scan Addresses
Reg
Address 56-63 Unused
DValueH
Register Description
REGO
0
000
Status Register
REG1
REG2
REG3
REG4
23
91
157
910
017
05B
090
38E
HFPEndTime
HSYNC Pulse End Time
HBLANK Pulse End Time
Total Horizontal Clocks
VECTORED RESTART ADDRESS
REG5
REG6
REG7
REG8
7
13
41
525
007
000
029
200
VFPEndTime
VSYNC Pulse End Time
VBLANK Pulse End Time
Total Vertical Lines
The function of addresses 22 (16H) or 54 (36H) are similar
to that of the CLR pin except that the programming of the
registers is not affected. It is recommended but not required
that this address is read after the initial device configuration
load sequence.
REG9
REG10
REG11
REG12
57
410
1
19
038
19A
001
013
Equalization Pulse End Time
Serration Pulse Start Time
Pulse Interval Start Time
Pulse Interval End Time
SCAN MODE LOGIC
REG13
REG14
41
526
029
20E
Vertical Interrupt Activate Time
Vertical Interrupt Deactivate Time
REG15
REG16
REG17
REG18
911
92
1
21
38F
05C
001
015
Horizontal Drive Start Time (1)
Horizontal Drive End Time
Vertical Drive Start Time
Vertical Drive End Time
At any given time only one register at most is selected. It is
possible to have no registers selected.
VECTORED CLEAR ADDRESS
Addresses 23 {17H} or 55 {37H} is used to clear all registers
simultaneously. This function may be desirable to use prior
to loading new data into the Data or Status Registers. This
address is read into the device in a similar fashion as all of
the other registers.
A scan mode is available in the ACT715/LM1882 that allows the user to non-destructively verify the contents of the
registers. Scan mode is invoked through reading a scan address into the address register. The scan address of a given
register is defined by the Data register address + 32. The
internal Clocking signal is disabled when a scan address is
read. Disabling the clock freezes the device in it's present
state. Data can then be serially scanned out of the data
registers through the ODD/EVEN Pin. The value of the two
horizontal counters and 1 vertical counter can also be
scanned out by using address numbers 51-53.
Input Clock
Line Rate
Field Rate
Frame Rate
Signal
Width
p.s
HFP
HSYNCWidth
HBLANK Width
HDRIVE Width
HEQPWidth
HSERRWidth
HPER 10D
22 Clocks
68 Clocks
156 Clocks
91 Clocks
34 Clocks
68 Clocks
910 Clocks
1.536
4.749
10.895
6.356
2.375
4.749
63.556
4-284
Rate
Period
14.31818 MHz
15.73426 kHz
59.94 Hz
29.97 Hz
69.841 ns
63.556 p.s
16.683 ms
33.367ms
'YoH
7.47
17.15
10.00
3.74
7.47
100
Specification (p.s)
1.5
4.7
10.9
0.1H
2.3
4.7
±0.1
±0.1
±0.2
±0.005H
±0.1
±0.1
.....
....
en
RS170 Default Register Values (Continued)
Signal
Width
VFP
VSYNCWidth
VB LANK Width
VDRIVE Width
VEQP Intrvl
VPERIOD (field)
VPERIOD (frame)
3 Lines
3 Lines
20 Lines
11.0 Lines
9 Lines
262.5 Lines
525 Lines
•
r-
,..s
190.67
190.67
1271.12
699.12
-20mA
+20mA
-20mA
+20mA
-0.5VtoVcc +0.5V
DC Output Source
or Sink Current (10)
±15mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
±20mA
Storage Temperature (TSTG)
4.5Vt05.5V
Input Voltage (VI)
OV to Vee
Output Voltage (Va)
OV to Vee
Operating Temperature (TA)
74ACT/LM1882
54ACT/LM1882
-0.5V to Vee +0.5V
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee +0.5V
DC Output Voltage (Va)
CO
CO
N
7.62
4.20
3.63
6EQP Pulses
6 Serration Pulses
0.075V ± 0.005V
0.04V ± 0.006V
9 Lines/Field
16.683 ms/Field
33.367 ms/Frame
Supply Voltage (Ved
'ACT/LM1882
-0.5Vto +7.0V
DC Input Voltage (VI)
3:
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee +0.5V
Specification
16.683 ms
33.367ms
Absolute Maximum Ratings (Note 1)
Supply Voltage (Ved
%V
-40'Cto +85'C
-55'C to + 125'C
Minimum Input Edge Rate (t.V / t.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (t. V / t.t)
'ACT/LM1882 Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125mV/ns
-65'C to + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over Its power supply,
temperature and output/input loading variables. National does not recom·
mend operation of FACTTM Circuits outside databook specifications.
DC Characteristics For 'ACT Family Devices over Operating Temperature Range (unless otherwise specified)
Symbol
Parameter
Vee
(V)
Minimum High Level
Output Voltage
4.5
5.5
74ACT/LM1882
54ACT/LM1882
74ACT/LM1882
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to + 85'C
Typ
VOH
4.49
5.49
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
4.5
5.5
10LD
Minimum Dynamic
Output Current
0.001
0.001
Units
Conditions
Guaranteed limits
=
4.4
5.4
4.4
5.4
V
V
lOUT
3.86
4.86
3.76
4.76
V
V
'VIN = VILIVIH
10H = -8mA
0.1
0.1
0.1
0.1
V
V
lOUT
0.36
0.36
0.44
0.44
V
V
'VIN = VILIVIH
10H = +BmA
32.0
mA
5.5
•All outputs loaded; thresholds on input associated with input under test.
4-285
VOLD
=
=
-50,..A
50,..A
1.65V
....
N
CD
CD
....
•
....
....
:E
....I
DC Characteristics
For 'ACT Family Devices over Operating Temperature Range (unless otherwise specified) (Continued)
II)
Symbol
Parameter
Vee
(V)
74ACT/LM1882
54ACTILM1882
74ACT/LM1882
TA = +25"C
CL=50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
Minimum Dynamic
Output Current
5.5
liN
Maximum Input
Leakage Current
5.5
Icc
Supply Current
Quiescent
5.5
Maximum leellnput
5.5
ICCT
Note 1: Test Load 50 pF, 500n to Ground.
Parameter
-32.0
mA
±0.1
±1.0
/LA
8.0
80
/LA
VIN = Vee, GND
1.5
mA
VIN = Vee - 2.1V
0.6
AC Electrical Characteristics:
Symbol
VOHO = 3.85V
VI = Vcc,GND
See Section 2 for Waveforms
74ACT/LM1882
54ACT/LM1882
74ACT/LM1882
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Vee
(V)
Conditions
Guaranteed Limits
Typ
IOHO
Units
Typ
5.0
170
190
150
MHz
5.0
190
220
175
MHz
5.0
4.0
13.0
15.5
3.5
18.5
ns
2-3,4
Clock to ODDEVEN
(Scan Mode)
5.0
4.5
15.0
17.0
3.5
20.5
ns
2-3,4
Load to Outputs
5.0
4.0
11.5
16.0
3.0
19.5
ns
2-3,4
Interlaced fMAX
(HMAX/2 is ODD)
fMAX
Non-Interlaced fMAX
(HMAX/2 is EVEN)
tpLH1
tpHL1
Clock to Any Output
tpLH2
tpHL2
tpLH3
Min
Max
Capacitance
Symbol
Typ
Units
Conditions
CIN
Input Capacitance
Parameter
7.0
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
17.0
pF
Vcc = 5.0V
4-286
Min
Fig.
No.
Min
fMAXI
Max
Units
Max
AC Operating Requirements:
Symbol
Vee
(V)
Parameter
tse
tse
tsd
Data Setup Time
D7-DO to LOAD+
the
Control Hold Time
LOAD- toADDR/DATA
LOAD- to L/HBYTE
•
r-
74ACT/LM1882
54ACT/LM1882
74ACT/LM1882
TA = +25'C
TA = -55'C
to + 125'C
TA = -40'C
to +85'C
Typ
Control Setup Time
ADDR/DATA to LOADLlHBYTE to LOAD-
.......
.....
CI1
See Section 2 for Waveforms
Units
Fig.
No.
Guaranteed Minimums
5.0
3.0
3.0
4.0
4.0
4.5
4.5
ns
ns
2-7
2-7
5.0
2.0
4.0
4.5
ns
2-7
5.0
0
0
1.0
1.0
1.0
1.0
ns
ns
2-7
2-7
thd
Data Hold Time
LOAD+ to D7-DO
5.0
1.0
2.0
2.0
ns
2-7
tree
LOAD + to CL - (Note 1)
5.0
5.5
7.0
8.0
ns
2-3,7
twldtwld+
Pulse Width
Load Low
Load High
5.0
5.0
3.0
3.0
5.5
5.0
5.5
7.5
ns
ns
2-3
2-3
twelr
CLR Pulse Width HIGH
5.0
5.5
6.5
9.5
ns
2-3
Iwek
CLOCK Width
(High or Low)
5.0
2.5
3.0
3.5
ns
2-3
Nole 1: Removal of Vectored Reset to Clock.
~
I
5 -L
CLOCK
OUTPUTS
00-07
tsD
thO
.I
t wLD -
LOAD
~IwLD
tac
~
the
LHBYTE ADDRDATA .J
TLlF/10137-6
FIGURE 3. AC Specifications
4-287
s::
.....
CD
CD
I\)
-r----------------------------------------------------------------------------,
~National
CD
CD
~ Semiconductor
54ACT174ACT818
8-Bit Diagnostic Register
General Description
Features
The'ACT818 is a high-speed, general-purpose pipeline register with an on-board diagnostic register for performing serial diagnostics and/or writable control store loading.
The D-to-Y path provides an 8-bit parallel data path pipeline
register for normal system operation. The diagnostic register can load parallel data to or from the pipeline register and
can output data through the D input port (as in WCS loading).
• On-line and off-line system diagnostics
• Swaps the contents of diagnostic register and output
register
• Diagnostic register and diagnostic testing
• Cascadable for wide control words as used in microprogramming
• Edge-triggered D registers
• Outputs source/sink 24 mA
• 'ACT818 has TTL-compatible inputs
• 'ACT818 is functionally- and pin-compatible to AMD
Am29818 and MMI 74S818
The 8-bit diagnostic register has multiplexer inputs that select parallel inputs from the Y-port or adjacent bits in the
diagnostic register to operate as a right-shift-only register.
This register can then participate in a serial loop throughout
the system where normal data, address, status and control
registers are replaced with 'ACT818 diagnostic pipeline registers. The loop can be used to scan in a complete test
routine starting point (Data, Address, etc.). Then after a
specified number of machine cycles it scans out the results
to be inspected for the expected results. WCS loading can
be accomplished using the same technique. An instruction
word can be serially shifted into the shadow register and
written into the WCS RAM by enabling the D output.
Applications
•
•
•
•
•
•
•
•
Register for microprogram control store
Status register
Data register
Instruction register
Interrupt mask register
Pipeline register
General purpose register
Parallel-seriallserial-parallel converter
Ordering Code: See Section 8
Logic Symbol
_
DCLK
-
MODE
Connection Diagrams
I I I I LJ I J I
Do 01 ~ 03 04 Os Os 17 501
OEY- 1
'-../
DCLK- 2
-(lOEY
-
Pin Assignment
for DIP, Flatpak and sOle
PCLK Yo Y, Y2 Y3 Y4 Ys Ys Y7 SDO
I I I I I I I I I
TL/F/9BOI-3
24
Pin Assignment
for Lee and pee
06
I-Vcc
Os
04 HC 03 02 0,
[iJ1W[!]1!l1Il1!l[[J
23 rMOOE
171m
00- 3
22 i-Yo
0,- 4
21i-Y,
O2 -
5
20 i-Y2
03- 6
19 i-Y3
04- 7
18 i-Y4
0s- 8
17 i-Ys
°s:- 9
10
161-Ys
17-
151-Y7
1iID~gj]~~~1§
501- 11
141-SDO
Ys Y5 Y4 He Y3 Y2 Y1
GHO- 12
13 rPCLK
TUF/9BO'-'
4-288
[!] °0
rn OCLK
SOI~
GHO~
HC (j]J
ill OEY
III HC
PCLKIiID
~Vcc
500
Ii1I
~MOOE
~Yo
Y7 1iID
TUF/9BO'-2
Description
Pin Names
Data Inputs
Serial Data Input
Diagnostics Clock
Control Input
Pipeline Register Clock
Output Enable Input
Serial Data Output
Data Outputs
Do-D7
SDI
DCLK
MODE
PCLK
OEY
SDO
YO-Y7
Diagnostic Register
SOl -i---1~I-----+----+
MODE
DCLl(
TLlF/9801-4
Block Diagram
SD--....----.r~8:-~8IT:-l
OCLK
MODE
---+--......-..
DIAGNOSTIC
REGISTER
t--+--+- SDO
---------t'L~~~~J
•
PCLK - - - - - - - - -....
CiE-----------
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
Supply Voltage (Vee>
'AC
-65'Cto + 150'C
-40'Cto +85'C
- 55'C to + 125'C
Minimum Input Edge Rate (AV I At)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125mVlns
Minimum Input Edge Rate (AVI At)
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125mVlns
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception. to ensure that the system design is reliable over its power supply.
temperature, and outpuVlnput lceding variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
orVee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
p.A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on Input associated wfth output under test.
tMaxlmum test duration 2.0 ms. one output loaded at a time.
4-296
lOUT = - 50 IJA
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50p.A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
CD
....
N
DC Characteristics for' AC Family Devices (Continued)
Parameter
Symbol
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Maximum TRI-STATE®
Current
loz
tMinimum Dynamic
Output Current
10LD
10HD
Maximum Quiescent
Supply Current
Icc
Conditions
Guaranteed Limits
±0.5
5.5
Units
±10.0
±5.0
)LA
VI (DE) = VIL. VIH
VI = Vee.GND
Vo = Vee. GND
5.5
50
75
rnA
VOLD = 1.65V Max
5.5
-50
-75
rnA
VOHD = 3.85V Min
160.0
80.0
)LA
VIN = Vee
orGND
5.5
8.0
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: liN and Icc
@
3.0V are guaranteed to be Jess than or equal to the respective limit
ICC for 54AC @ 25'C is identical to 74AC
@
@
S.5V Vee.
25'C.
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
)LA
loz
Maximum TRI-STATE®
Current
5.5
±0.5
±10.0
±5.0
)LA
leCT
Maximum
Icc/Input
5.5
1.6
1.5
rnA
10LD
tMinimum Dynamic
Output Current
10HD
Icc
Maximum Quiescent
Supply Current
0.6
lOUT = - 50 )LA
'VIN = VIL or VIH
-24 rnA
-24mA
10H
lOUT = 50)LA
'VIN = VIL or VIH
24mA
10L
24 rnA
VI = Vee.GND
VI = VIL. VIH
Yo' = Vee. GND
VI = Vee - 2.1V
5.5
50
75
rnA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
)LA
VIN = Vee
orGND
5.5
8.0
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: Icc for 54ACT @ 25'C Is identical to 74ACT @ 25"C.
4-297
III
....N
co
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74AC
S4AC
74AC
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 125'C
CL=SOpF
TA = -40'C
to +8S'C
CL = SOpF
Min
Min
Min
Typ
Maximum Clock
Frequency
3.3
5.0
110
120
145
160
tpLH
Propagation Delay
CP to On
3.3
5.0
3.0
2.0
B.O
6.0
13.0
9.5
1.0
1.0
16.0
11.5
3.0
2.0
15.0
10.5
ns
2-3,4
tpHL
Propagation Delay
CP to On
3.3
5.0
3.0
2.0
B.O
5.5
13.0
9.5
1.0
1.0
16.0
11.5
3.0
2.0
15.0
10.5
ns
2-3,4
tPZH
Output Enable Time
OEtoOn
3.3
5.0
2.5
1.5
6.0
4.5
11.0
B.O
1.0
1.0
13.0
10.0
2.5
1.5
12.0
9.0
ns
2-5
tpZL
Output Enable Time
OEtoO n
3.3
5.0
2.5
1.5
6.5
5.0
11.0
B.O
1.0
1.0
13.5
10.0
2.5
1.5
12.0
9.0
ns
2-6
tpHZ
Output Disable Time
OEtoO n
3.3
5.0
2.5
1.5
6.5
5.0
10.5
B.O
1.0
1.0
12.0
10.0
2.5
1.5
11.0
B.5
ns
2-5
Output Disable Time
OEtoO n
'Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
3.3
5.0
2.5
1.5
6.0
4.5
10.5
B.O
1.0
1.0
12.0
10.0
2.5
1.5
11.0
B.5
ns
2-6
Units
Fig.
No.
AC Operating Requirements:
Max
. Fig.
No.
f max
tpLZ
Max
Units
Max
100
110
95
100
MHz
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 12S'C
CL=50pF
TA = -40'C
to +85'C
CL = SOpF
Parameter
Vee'
(V)
ts
Setup Time, HIGH or LOW
Dn to CP
3.3
5.0
-1.0
-1.0
1.5
1.5
2.5
2.5
1.5
1.5
ns
2-7
th
Hold Time, HIGH or LOW
Dn to CP
3.3
5.0
-1.0
-1.0
3.5
3.5
4.0
4.0
4.0
4.0
ns
2-7
3.3
5.0
3.5
2.5
5.0
4.0
6.0
5.0
5.5
4.0
ns
2-3
Symbol
Typ
CP Pulse Width
HIGH or LOW
'Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ±0.5V
tw
Guaranteed Minimum
4·29B
AC Electrical Characteristics:
Symbol
Vee'
IV)
Parameter
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25"C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Min
Fig.
No.
Min
Typ
5.0
120
150
Propagation Delay
CPtoOn
5.0
2.0
6.0
9.5
1.0
11.5
1.5
10.5
ns
2-3,4
tpHL
Propagation Delay
CPtoOn
5.0
2.5
6.0
9.5
1.0
11.5
2.0
10.5
ns
2-3,4
tpZH
Output Enable Time
DE to On
5.0
2.5
7.0
10.5
1.0
12.5
2.0
11.5
ns
2-5
tpZL
Output Enable Time
OEtoO n
5.0
2.5
7.0
10.5
1.0
13.0
2.0
12.0
ns
2-6
tpHZ
Output Disable Time
DE to On
5.0
1.5
7.5
12.0
1.0
13.5
1.0
13.0
ns
2-5
tpLZ
Output Disable Time
DE to On
5.0
1.5
7.0
10.5
1.0
12.5
1.0
11.5
ns
2-6
Units
Fig.
No.
fmax
Maximum Clock
Frequency
tpLH
Max
Max
Units
85
Max
110
MHz
'Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements:
Symbol
Parameter
Vee'
IV)
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125"C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Typ
Guaranteed Minimum
Is
Setup Time, HIGH or LOW
Dn to CP
5.0
2.5
2.0
4.0
2.5
ns
2-7
th
Hold Time, HIGH or LOW
Dn toCP
5.0
-0.5
2.0
3.0
2.5
ns
2-7
tw
CP Pulse Width
HIGH or LOW
5.0
3.0
4.5
6.0
5.5
ns
2-3
·Voltage Range 5.0 is 5.0V ± O.5V
Capacitance
Parameter
Typ
Units
Conditions
CIN
Symbol
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
35.0
pF
Vee = 5.0V
4-299
~National
~ semiconductor
54ACT17 4ACT823
9-Bit D Flip-Flop
General Description
Features
The 'ACT823 is a 9-bit buffered register. It features Clock
Enable and Clear which are ideal for parity bus interfacing in
high performance microprogramming systems. The
'ACT823 offers noninverting outputs and is fully compatible
with AMD's Am29823.
•
•
•
•
Outputs source/sink 24 mA
TRI-STATE® outputs for bus interfacing
Inputs and outputs are on opposite sides
'ACT823 has TIL-compatible inputs
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and sOle
Of
CLR
EN
CP
TL/F/9894-1
Do
00
Dl
°1
D2
°2
D3
°3
D4
°4
Of
1
Do
2
Dl
3
Vee
24
23
°0
°1
°20
3
°4
D2
D3
D4
D5
°s
06
°7
Os
Ds
Os
D6
°6
I?
0.,
CLR
EN
Ds
Os
GND
CP
Ds
TL/F/9894-2
TUF/9894-S
Pin Assignment
for Lee
I? 06 05 Ne
04 03 O2
[jJJjg [[I [§][l][§]IID
Pin Names
Do-De
QQ.-Oe
OE
CLR
CP
EN
Description
Data Inputs
Data Outputs
Output Enable
Clear
Clock Input
Clock Enable
De@
CLR 1m
GND IBl
ill DI
NCIi§]
[jJNC
CPJi]J
~Vcc
EHIi1l~
~Oo
rn Do
III DE
~Ol
°eJi]J;:'
"-,,, '" "'''' l'1li l'1li "I,
1iID~~~~~~
07 0 6 05 NC 04 03 02
TL/F/9894-4
4-300
Functional Description
the state of the flip·flops. In addition to the Clock and Output
Enable pins, there are Clear (CLR) and Clock Enable (EN)
pins. These devices are ideal for parity bus interfacing in
high performance systems.
The 'ACT823 consists of nine D·type edge·triggered flip·
flops. These have TRI·STATE outputs for bus systems or·
ganized with inputs and outputs on opposite sides. The buff·
ered clock (CP) and buffered Output Enable (OE) are com·
mon to all flip·flops. The flip·flops will store the state of their
individual D inputs that meet the setup and hold time reo
quirements on the LOW·to·HIGH CP transition. With OE
LOW, the contents of the flip·flops are available at the out·
puts. When OE is HIGH, the outputs go to the high imped·
ance state. Operation of the OE input does not affect
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip·flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW·to·HIGH clock transition. When the EN
is HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
Function Table
Inputs
Internal
Output
0
Q
0
..r
..r
L
H
X
X
X
X
X
X
X
X
..r
..r
..r
..r
L
H
L
H
L
H
L
L
NC
NC
L
H
L
H
Z
Z
Z
L
Z
NC
Z
Z
L
H
OE
CLR
EN
CP
H
H
H
L
H
L
H
H
L
L
X
X
L
L
L
L
H
H
H
H
H
H
X
X
H
H
L
L
L
L
Function
HighZ
HighZ
Clear
Clear
Hold
Hold
Load
Load
Load
Load
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
../" = LOW·lo-HIGH Transition
NC = No Change
logic Diagram
cP ....-------lLJ
Os
TUF/9694-5
Please nole Ihallhis diagram is provided only for Ihe underslanding of logic operalions and should nol be used 10 estimale propagallon delays.
4·301
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5V to 7.0V
Supply Voltage (Vecl
DC Input Diode Current (1110
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (10K)
Va = -0.5V
-20mA
+20mA
Va = Vee + 0.5V
DC Output Voltage (Va)
-0.5V to Vee + 0.5V
DC Output Source or Sink Current (10)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (lee or IGNO)
Storage Temperature (T8TG)
-65'C to + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140"C
Nole 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception. to ensure that the system design Is reliable over Its power supply,
temperature. and output/Input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
Supply Voltage (Vecl
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (tN/t:..t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (t:.. VI t:..t)
'ACT Devices
VIN from O.BV to 2.0V
Vee @ 4.5V, 5.5V
2.0Vt06.0V
4.5Vt05.5V
OVtoVee
OV to Vee
-40"Cto +B5'C
-55'C to + 125'C
125 mV/ns
125 mV/ns
DC Electrical Characteristics
74ACT
54ACT
74ACT
Parameter
Vee
TA = 25'C
VIH
Minimum High Level
Input Voltage
4.5
5.5
Typ
1.5
1.5
2.0
2.0
VIL
Maximum Low Level
Input Voltage
4.5
4.5
1.5
1.5
O.B
O.B
O.B
O.B
O.B
O.B
V
VOUT = 0.1V
or Vee -0.1V
VOH
Minimum High Level
4.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
lOUT = - 50 /LA
3.B6
4.B6
3.76
4.76
V
'VIN = VIL or VIH
-24mA
IOH
-24mA
0.1
0.1
3.70
4.70
0.1
0.1
0.1
0.1
V
lOUT = 50/LA
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
VI = Vee,GND
5.5
±0.5
±10.0
±5.0
/LA
VI = VIL, VIH
Va = Vee,GND
1.6
50
1.5
mA
mA
VI = Vee -2.1V
VOLO = 1.65V Max
mA
VOHO = 3.B5V Min
/LA
VIN = Vee
orGND
Symbol
(V)
4.5
VOL
Maximum Low Level
Output Voltage
liN
Maximum Input
Leakage Current
loz
Maximum TRI-STATE Current
leeT
10LD
Maximum leellnput
tMinimum Dynamic
Output Current
10HO
4.5
5.5
5.5
5.5
0.001
0.001
TA=
TA=
Units
Conditions
-55'C to + 125'C -40'Cto +85'C
Guaranteed Limits
2.0
2.0
VOUT = 0.1V
V
2.0
2.0
or Vee -0.1V
0.6
5.5
Maximum Quiescent
5.5
B.O
Supply Current
•All outputs loaded; thresholds on input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
Nole: Icc limit for 54ACT I!!I 25'C Is Identical to 74ACT I!!I 25'C.
Icc
4-302
-50
75
-75
160
BO
'VIN = VIL or VIH
24mA
IOL
24mA
AC Electrical Characteristics:
Symbol
Parameter
f max
Maximum Clock
Frequency
tpLH
Propagation Delay
CPtoO n
Propagation Delay
CP to On
tpHL
Vee'
(V)
Propagation Delay
ClRtoOn
Output Enable Time
OE to On
tpHL
tpZH
tPZL
Output Enable Time
OEtoO n
tpHZ
Output Disable Time
OEtoOn
Output Disable Time
OE to On
tpLZ
'Voltage Range 5.0 is S.OV
74ACT
S4ACT
74ACT
TA = +2S'C
CL = SOpF
TA - -SS'C
to + 12S'C
CL = SOpF
TA- 40'C
to +8S'C
CL = SO pF
Min
Min
Max
Fig.
No.
Min
Typ
120
158
5.0
1.5
5.5
9.5
1.0
12.0
1.5
10.5
ns
2-3,4
5.0
2.0
5.5
9.5
1.0
12.0
1.5
10.5
ns
2-3,4
5.0
2.5
8.0
13.5
1.0
18.0
2.0
15.5
ns
2-3,4
1.5
6.0
10.5
1.0
11.5
1.5
11.5
ns
2-5
5.0
2.0
6.5
11.0
1.0
12.0
1.5
12.0
ns
2-6
5.0
1.5
6.5
11.0
1.0
13.5
1.5
12.0
ns
2-5
5.0
1.5
6.0
10.5
1.0
12.0
1.5
11.5
ns
2-6
5.0
Max
Units
5.0
95
Max
109
MHz
± O.SV
AC Operating Requirements:
Symbol
See Section 2 for Waveforms
Parameter
Vee'
(V)
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Typ
Units
Fig.
No.
Guaranteed Minimum
t.
Setup Time, HIGH or lOW
DtoCP
S.O
0.5
2.5
4.0
2.5
ns
2-7
th
Hold Time, HIGH or lOW
Dn to CP
5.0
0
2.5
3.0
2.5
ns
2-7
t.
Setup Time, HIGH or lOW
ENtoCP
5.0
0
2.0
4.0
2.5
ns
2-7
th
Hold Time, HIGH or lOW
ENtoCP
5.0
0
1.0
3.0
1.0
ns
2-7
tw
CP Pulse Width
HIGH or lOW
5.0
2.5
4.5
6.0
5.5
ns
2-3
tw
ClR Pulse Width, lOW
5.0
3.0
5.5
7.0
5.5
ns
2-3
tree
CLRtoCP
Recovery Time
5.0
1.5
3.5
4.5
4.0
ns
2-3,7
'Voltage Range 5.0 is S.OV
±o.sv
Capacitance
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee - 5.0V
CPD
Power Dissipation
Capacitance
44
pF
Vee = 5.0V
Symbol
4-303
U)
N
CIO
r----------------------------------------------------------------------------,
~National
~ Semiconductor
54ACT17 4ACT825
8-Bit D Flip-Flop
General Description
Features
The 'ACT825 is an 8-bit buffered register. They have Clock
Enable and Clear features which are ideal for parity bus
interfacing in high performance microprogramming systems.
Also included are multiple enables that allow multi-use control' of the interface. The' ACT825 has noninverting outputs
and is fully compatible with AMD's Am29825.
, • Outputs source/sink 24 mA
• Inputs and outputs are on opposite sides
• 'ACT825 has TTl-compatible inputs
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
liEl
liE2
liEl
liE3
o~
2
liE3
°0
3
°0
CLR
EN
CP
Vee
°1
4
°1
°2
5
°2
00
00
°3
6
°3
°1
°1
' °4
7
°4
°2
°2
°5
8
°3
04
°3
0,
Os
9
°5
06
10
°7
°5
06
°5
06
07
CLR
GNO
12
TLlF19895-1
D7
EN
11
13
°7
CP
TLIFI989S-2
TLIFI989S-3
Pin Names
DO-D7
0 0- 0 7
OE1, OE2, OEs
EN
ClR
CP
Pin Assignment
forlCC
Description'
D6 Ds D, HC D3 D2 Dl
Data Inputs
Data Outputs
Output Enables
Clock Enable
Clear
Clock Input
IIlIlrnIlIlrnJlllrnJrnJ
~1l1I(
II [!J Do
ilrnBEz
CLRIilI
II rn eEl
GHD~
NC~
[TINC
CP~
~Vcc
ENIiZI
~0E3
°7~
~Oo
1i!I~~~~~~
0 6 Os 0, HC 03 02 01
TLIF19895-4
4-304
r---------------------------------------------------------------------------------, N00
Functional Description
U1
Operation of the OE input does not affect the state of the
flip-flops. The 'ACT825 has Clear (CLA) and Clock Enable
(EN) pins. These pins are ideal for parity bus interfacing in
high performance systems.
When CLA is LOW and OE is LOW, the outputs are LOW.
When CLA is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When EN is
HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
The 'ACT825 consists of eight D-type edge-triggered flipflops. These devices have TAI-STATE~ outputs for bus systems, organized in a broadside pinning. In addition to the
clock and output enable pins, the buffered clock (CP) and
buffered Output Enable (OE) are common to all flip-flops.
The flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the
LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW,
the contents of the flip-flops are available at the outputs.
When one of OE1, OE2 or OE3 is HIGH, the outputs go to
the high impedance state.
Function Table
Inputs
OE
CLR
EN
CP
H
H
H
L
H
L
H
H
L
L
X
X
L
L
H
H
H
H
H
H
L
L
X
X
H
H
L
L
L
L
...r
...r
X
X
X
X
...r
...r
...r
...r
Internal
Output
On
Q
0
L
H
X
X
X
X
L
H
L
H
L
H
L
L
NC
NC
L
H
L
H
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High-Z
High-Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
H=
L=
X=
Z=
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
..r = LOW-to-HIGH Transition
NC = No Change
Logic Diagram
EN------r.........
cP ...------L~
TL/F/9895-5
Please note that this diagram Is provided only for the understending of logic operations and should not be used to estimate propagation delays.
4-305
It)
N
co
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
DC Input Diode Current (1110
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
Supply Voltage (Vee)
'AC
'ACT
-0.5V to 7.0V
-20mA
+20mA
-20mA
+20mA
DC Output Voltage (Va)
+0.5V
DC Output Source or Sink Current (10)
±50mA
DC Vee or Ground Current
Per Output Pin (Icc or IGNO)
Storage Temperature (TSTG)
Input Voltage (VI)
OVtoVee
Output Voltage (Va)
OVtoVee
Operating Temperature (TA)
74AC/ACT
54AC/ACT
-0.5VtoVee +0.5V
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee +0.5V
2.0Vto 6.0V
4.5Vto 5.5V
±50mA
-65'Cto + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
-40'Cto +B5'C
-55'C to + 125'C
Minimum Input Edge Rate (Il.V/ll.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (Il.V/ll.t)
'ACT Devices
VIN from O.BV to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not racom·
mend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics
74ACT
Symbol
Parameter
Vcc
(V)
TA = 25'C
54ACT
74ACT
TA =
TA=
Units
-55'C to + 125'C - 40'C to + 85'C
Typ
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
0.8
O.B
0.8
O.B
O.B
VOH
Minimum High Level
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.B6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
,..A
VI = Vee,GND
5.5
±0.5
±10.0
±5.0
,..A
VI = VIL, VIH
Va = Vee,GND
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
V
VOUT = 0.1V
or Vee -0.1V
VOUT = 0.1V
or Vee -0.1V
lOUT = -50,..A
'VIN = VIL or VIH
-24mA
10H
-24mA
lOUT = 50,..A
·VIN = VIL or VIH
24mA
10L
24mA
liN
Maximum Input Leakage Current
102
Maximum TRI-STATE Current
leeT
Maximum leellnput
5.5
1.6
1.5
mA
VI = Vee -2.1V
10LD
tMinimum Dynamic
Output Current
5.5
50
75
mA
YOLO = 1.65V Max
5.5
-50
-75
mA
VOHO = 3.85V Min
160
80
,..A
VIN = Vee
orGND
10HO
0.6
Maximum Quiescent
8.0
5.5
Supply Current
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a lime.
Note: Icc limit for 54ACT @ 25'C is identical to 74ACT @ 25'C.
Icc
4-306
AC Electrical Characteristics:
Symbol
Vee'
(V)
Parameter
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25DC
CL = 50pF
TA = -55D C
to + 125DC
CL = 50pF
TA = -40"C
to +85DC
CL = 50pF
Min
Min
Typ
5.0
120
158
Propagation Delay
CPtoO n
5.0
1.5
5.5
9.5
1.0
11.5
1.5
10.5
ns
2-3,4
tpHL
Propagation Delay
CP to On
5.0
2.0
5.5
9.5
1.0
11.5
1.5
10.5
ns
2-3,4
tpHL
Propagation Delay
ClRtoO n
5.0
2.5
8.0
13.5
1.0
18.0
2.0
15.5
ns
2-3,4
tPZH
Output Enable Time
OE to On
5.0
1.5
6.0
10.5
1.0
11.5
1.5
11.5
ns
2-5
tPZL
Output Enable Time
OE to On
5.0
2.0
6.5
11.0
1.0
12.5
1.5
12.0
ns
2-S
tpHZ
Output Disable Time
OEtoO n
5.0
1.5
6.5
11.0
1.0
13.5
1.5
12.0
ns
2-5
tpLZ
Output Disable Time
OE to On
5.0
1.5
S.O
10.5
1.0
13.0
1.5
11.5
ns
2-S
Maximum Clock
Frequency
tpLH
Max
Fig.
No.
Min
f max
Max
Units
95
Max
MHz
109
'Voltage Range 5.0 is S.OV ± O.SV
AC Operating Requirements:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25D C
CL=50pF
TA = -55"C
to + 125D C
CL = 50pF
TA - -40"C
to +85D C
CL = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or lOW
Dnto CP
5.0
0.5
2.5
4.0
2.5
ns
2-7
th
Hold Time, HIGH or lOW
Dn toCP
5.0
0
2.5
3.0
2.5
ns
2-7
ts
Setup Time, HIGH or lOW
EN to CP
5.0
0
2.0
4.0
2.5
ns
2-7
th
Hold Time, HIGH or lOW
ENtoCP
5.0
0
1.0
3.0
1.0
ns
2-7
tw
CP Pulse Width
HIGH or lOW
5.0
2.5
4.5
6.0
5.5
ns
2-3
tw
ClR Pulse Width, lOW
5.0
3.0
5.5
7.0
5.5
ns
2-3
tree
ClRto CP
Recovery Time
5.0
1.5
3.5
4.5
4.0
ns
2-3,7
'Voltage Range S.O is S.OV ± o.sv
Capacitance
Parameter
Typ
Units
CIN
Symbol
Input Capacitance
4.5
pF
Vee
CPO
Power Dissipation
Capacitance
44
pF
Vee = 5.0V
4-307
Conditions
5.0V
.._ ~National
r---------------------------------------------------------------------~
CD
~ semiconductor
54ACT174ACT841
10-Bit Transparent Latch with TRI-STATE® Outputs
General Description
Features
The 'ACT841 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/ data paths or
buses carrying parity. The 'ACT841 is a 10-bit transparent
latch, a 10-bit version of the 'ACT373.
• 'ACT841 has TTL-compatible inputs
• Outputs source/sink 24 rnA
• Non-inverting TRI-STATE outputs
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
DE
LE
Vee
OE
LE
TL/F/l01S6-l
Do
00
DI
D2
°
°2
D2
4
D3
D.
°1
°2
°3
°4
D3
5
°3
6
DS
D6
°50 6
D4
Ds
7
°s
D6
8
0.,
06
°7
D7
9
D8
°8
10
15
D9
D8
°8
°9
D9
GND
II
14
09
12
13
LE
1
TL/F/l01S6-2
Pin Names
0 0- 0 9
0 0- 0 9
OE
LE
°0
°4
°7
TL/F/l0156-3
Description
Data Inputs
TRI-STATE Outputs
Output Enable
Latch Enable
Pin Assignment
forLCC
~ 06 05 HC 0, 03 ~
1IllII9l!Il[[]Il][[][ID
Oali1l:-
mOl
091iID:-
moo
III DE
HC IiID :LEij]J;'
[l] HC
GNO iBI ;.
~ vee
091l11:-
~Oo
0ali§];'
(mOl
QuI(Jl{Jl(JI{JI[Jif
~gglaiJ~~~~
07 06 05 HC 0, 03 02
TL/F/l0l56-4
4-308
Functional Description
The ACT841 consists of ten D-type latches with TRI-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LEI is HIGH. This allows asynchronous operation, as the output transition follows the data in transition.
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is latched. Data appears on the bus
when the Output Enable (OEI is LOW. When OE is HIGH
the bus output is in the high impedance state.
Function Table
Inputs
Internal
Output
LE
0
Q
0
X
X
X
X
H
H
H
L
L
L
H
H
L
H
H
L
L
H
L
H
NC
L
H
NC
Z
Z
Z
Z
L
H
NC
OE
X
L
H
X
Function
HighZ
HighZ
HighZ
Latched
Transparent
Transparent
Latched
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
TlIF1101S6-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate progagation delays•
•
4-309
.....
co
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
.-0.5Vto +7.0V
DC Input Diode Current (11K)
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (10K>
Vo = -0.5V
-20mA
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5V to Vee + 0.5V
DC Output Source
±50mA
or Sink Current (10)
DC Vee or Ground Current
±50mA
per Output Pin (lee or IGNO)
Storage Temperature (TSTG)
-65'Cto + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specHications should be met. without
exception, to ensure that the system design is reliable over its power supply,
temperature, and outputflnput loading variables. Natlonai does not recom·
mend operation of FACT'" circuHs outside databook speCifications.
Supply Voltage (Vee>
'AC
'ACT
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (.6.Vl.6.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (.6.V/.6.t)
'ACT Devices
VIN from O.SV to 2.0V
Vee @ 4.5V, 5.5V
2.0Vt06.0V
4.5Vt05.5V
OV to Vee
OV to Vee
-40'Cto +85'C
- 55'C to + 125'C
125mVlns
125 mV/ns
DC Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +2S'C
TA=
-S5'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
or Vee - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = O.W
or Vee - O.W
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
~
loz
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
~
ICCT
Maximum
Icel.lnput
5.5
1.6
1.5
/LA
0.6
'All outputs loaded; thresholds on Input associated wHh output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-310
lOUT = - 50 /LA
'VIN = VIL or VIH
-24mA
-24mA
IOH
lOUT = 50/LA
'VIN = VIL or VIH
24mA
IOL
24mA
VI = Vee,GND
VI = VIL, VIH
Vo = Vee,GND
VI = Vee - 2.W
DC Characteristics for' ACT Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'Cto +85'C
Typ
IOLD
IOHD
Icc
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
. Guaranteed Limits
5.5
50
75
mA
VOLO = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
!LA
VIN = Vcc
orGND
5.5
8.0
·AII outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT @ 25'C is identical to 74ACT @ 25'C.
AC Electrical Characteristics:
Symbol
Parameter
Vcc'
(V)
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
5.0
2.0
5.5
9.5
1.0
11.0
2.0
10.0
ns
2-3.4
Propagation Delay
Dn to On
5.0
2.0
5.5
9.5
1.0
11.0
2.0
10.0
ns
2-3.4
tpLH
Propagation Delay
LEtoO n
5.0
2.0
5.5
9.0
1.0
11.0
2.0
10.0
ns
2-3.4
tpHL
Propagation Delay
LE to On
5.0
2.0
5.5
9.0
1.0
11.0
2.0
10.0
ns
2-3.4
tPZH
Output Enable Time
OE to On
5.0
2.0
5.5
9.5
1.0
11.0
2.0
10.5
ns
2-5.6
tPZL
Output Enable Time
OE to On
5.0
2.0
5.5
9.5
1.0
11.0
2.0
10.5
ns
2-5.6
tpHZ
Output Disable Time
OEtoO n
5.0
2.0
6.0
10.5
1.0
12.0
2.0
11.0
ns
2-5.6
5.0
2.0
6.0
10.5
1.0
12.0
2.0
11.0
ns
2-5,6
tpLH
Propagation Delay
DntoOn
tpHL
Output Disable Time
OEtoO n
'Voltage Range 5.0 is 5.0V ±O.5V
tpLZ
4-311
....
:
AC Operating Requirements:
Symbol
Parameter
Vcc'
(V)
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25°C
Cl=50pF
TA = -55"C
to + 125"C
Cl = 50pF
TA = -400C
to +85"C
Cl = 50pF
Units
Fig.
No.
Guaranteed Minimum
Typ
ts
Setup TIme, HIGH or LOW
Onto LE
5.0
-0.5
0.5
3.0
t.O
ns
2·7
th
Hold Time, HIGH or LOW
DntoLE'
5.0
0.5
2.0
2.0
2.0
ns
2·7
tw
LE Pluse Width, HIGH
5.0
2.0
3.5
5.0
3.5
ns
2·3
'Voltage Range 5.0 is 5.0V
± 0.5V
Capacitance
Symbol
Parameter
AC/ACT
Units
Conditions
Typ
CIN
Input Capacitance
4.5
pF
Vee
=
5.0V
CpO
Power Dissipation
Capacitance
44
pF
Vee
=
5.0V
4·312
r-----------------------------------------------------------------------~ ~
oIiIo
W
~National
~ Semiconductor
54AC/74AC843 • 54ACT17 4ACT843
8-Bit Transparent Latch
General Description
Features
The 'AC/'ACT843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths.
The 'AC/'ACT843 is functionally and pin compatible with
AMD's Am29843.
• 'ACT843 has TTL-compatible inputs
• TRI-STATE<1!l outputs for bus interfacing
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and sOle
Pin Assignment
for lee
OE
IiilliIDrnlIDllllIDrnJ
07 06 05 NC 04 03 O2
TUF/9800-1
1
24
Do
2
23
00
Dl
3
22
°1
CLR~
D2
4
21
°2
GNO IHI
IIlCiE
NCjjID
III NC
LEIi!!
~Vee
~Oo
~01
Vee
08~
D3
5
20
°3
D4
6
19
°4
7
8
9
10
18
PREIiZI
Ds
°s
0&
°ali!!
17
16
DJ
15
11
14
°8
PRE
12
13
LE
D&
DJ
D8
CLR
GND
[!] 01
moo
IiIDsgWl~@]~~
07 0 6 Os NC 0. 0 3 02
TL/F/9800-4
°0
TL/F/9800-2
°1
°2
03
°4
°5
°6
~
08
II
TLlF/9800-3
Pin Names
Description
Data Inputs
Data Outputs
Output Enable
Latch Enable
Clear
Preset
4-313
Functional Description
The 'AC/'ACT843 consists of nine D-type latches with TRISTATE outputs. The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data
in transition. On the LE HIGH-to-LOW transition, the data
that meets the setup times is latched. Data appears on the
bus when the Output Enable (OE) is LOW. When OE is
HIGH, the bus output is in the high impedance state. In
addition to the LEand OE pins, the 'AC/'ACT843 has a
Clear (CLR) pin and a Preset (PRE) pin. These pins are ideal
for parity bus interfacing in high performance systems.
When CLR is LOW, the outputs are LOW if OE is LOW.
When CLR is HIGH, data can be entered into the latch.
When PRE is LOW, the outputs are HIGH if OE is LOW.
Preset overrides CLR.
'
Function Tables
Internal
Outputs
CLR
PRE
Inputs
OE
LE
D
Q
0
H
H
H
H
H
.H
H
L
L
L
H
H
H
H
H
H
H
L
H
L
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
L
H
H
L
L
H
L
H
NC
L
H
NC
H
L
H
L
H
Z
Z
Z
L
H
NC
H
L
H
Z
Z
X
X
X
L
L
X
L
H
X
X
X
X
X
X
Function
HighZ
HighZ
Latched
Transparent
Transparent
Latched
Preset
Clear
Preset
Clear/High Z
Preset/High Z
H = HIGH Voltage Level
L = LrYW Voltage Level
X = Immaterial
Z ~ High Impedance
NC = No Change
Logic Diagram
lE
0,
Os
TLlF/9800-5
4-314
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
Supply Voltage (Vee>
'AC
'ACT
-0.5Vto +7.0V
DC Input Diode Current (111<>
V, = -0.5V
V, = Vee +0.5V
-20 rnA
+20mA
DC Input Voltage (V,)
-20 rnA
+20mA
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
±50mA
Storage Temperature (TSTG)
Input Voltage (V,)
OV to Vee
Output Voltage (Va)
OV to Vee
Operating Temperature (TAl
74AC/ACT
54AC/ACT
-0.5V to Vee +0.5V
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee +0.5V
DC Output Voltage (Va)
2.0Vt06.0V
4.5Vt05.5V
-65'C to + 150'C
- 40'C to + 85'C
- 55'C to + 125'C
Minimum Input Edge Rate (IlV/llt)
'AC Devices
Y,N from 30% to 70% of Vee
Vf::C @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (IlV/llt)
'ACT Devices
Y,N from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be me~ without
exception, to ensure that the system design is reliable over its power supply,
temperature, and outputlinput loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics for' AC Family Devices
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25'C
TA=
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
V,H
V,L
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
.4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
lOUT = -50/LA
lOUT = 50/LA
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
,
• All outputs loaded; thresholds on input associated with ~utput under test.
tMaximum lest duration 2.0 ms, one output loaded al a time.'
4-315
'V,N = V,L or V,H
-12mA
-24 rnA
10H
-24 rnA
'V,N = V,L or V,H
12mA
24 rnA
10L
24 rnA
V, = Vee,GND
II
DC Electrical Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = +25"C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
loz
IOLD
IOHD
Icc
Maximum TRI·STATE
Leakage Current
tMinimum Dynamic
Output Current
Maximum Quiescent '
Supply Current
5.5
Units
Conditions
Guaranteed Limits
±0.5
±10.0
±5.0
p.A
VI (OE) = VIL. VIH
VI = Vee.GND
Vo = Vee.GND
VOLD = 1.65VMax
5.5
50
75
mA
5.5
-50
-75
mA
VOHD = 3.85V Min
p.A
VIN = Vee
orGND
5.5
8.0
80.0
160.0
•All outputs loaded; thresholds on Input associated wRh output under tesl
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: liN and lee @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
Icc for 54AC @ 25'C Is Identical to 74AC @ 25'C.
DC Electrical Characteristics for' ACT Family Devices
Symbol
Parameter
Vec
(V)
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
liN
Maximum input
Leakage Current
5.5
±0.1
±1.0
±1.0
p.A
loz
Maximum TRI·STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
p.A
ICCT
Maximum
Iccllnput
5.5
1.6
1.5
mA
IOLD
tMinlmum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
0.6
iOUT = -50 p.A
'VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50 p.A
·V,N = VIL or VIH
24mA
IOL
24mA
VI = Vcc.GND
VI = VIL. V,H
Vo = Vee.GND
VI = Vee - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
p.A
VIN = Vcc
orGND
5.5
8.0
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note: Icc for 54ACT @ 25'C Is identical to 74ACT @ 25'C.
4·316
AC Electrical Characteristics:
Symbol
Vcc'
Parameter
(V)
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tplH
Propagation Delay
Dn to On
3.3
5.0
3.5
2.0
6.5
4.5
12.0
8.5
1.0
1.0
14.0
10.0
2.5
1.5
13.0
9.0
ns
2-3,4
tpHL
Propagation Delay
Dn to On
3.3
5.0
4.0
2.5
7.0
5.0
12.0
8.5
1.0
1.0
14.0
10.0
3.0
. 1.5
13.0
9.0
ns
2-3,4
tpLH
Propagation i!)elay
lE to On
3.3
5.0
3.5
2.0
6.5
4.5
12.0
8.5
1.0
1.0
14.0
10.0
2.5
1.5
13.0
9.0
ns
2-3,4
tpHL
Propagation Delay
lEtoOn
3.3
5.0
4.0
2.5
7.0
5.0
12.0
8.5
1.0
1.0
14.0
10.0
3.0
1.5
13.0
9.0
ns
2-3,4
tplH
Propagation Delay
PRE to On
3.3
5.0
5.5
3.5
8.5
6.0
19.0
13.0
1.0
1.0
23.5
16.0
4.5
2.5
21.5
14.5
ns
2-3,4
3.3
5.0
7.5
5.0
11.0
7.5
21.5
15.0
1.0
1.0
26.5
19.0
6.0
4.0
24.0
17.0
ns
2-3,4
,
tpHL
Propagation Delay
ClR to On
tpZH
Output Enable Time
OEtoOn
3.3
5.0
3.5
2.0
6.0
4.5
11.0
B.O
1.0
1.0
13.0
10.0
3.0
1.5
12.0
9.0
ns
2-5,6
Output Enable Time
OEtoOn
3.3
5.0
4.0
2.0
6.5
5.0
11.0
8.0
1.0
1.0
13.0
10.0
2.5
1.5
12.0
9.0
ns
2-5,6
Output Disable Time
DE to On
3.3
5.0
4.0
3.0
6.5
5.0
10.5
8.0
1.0
1.0
12.0
9.0
3.5
2.5
11.0
8.5
ns
2-5,6
tpLZ
Output Disable Time
OEtoOn
3.3
5.0
3.0
2.0
6.0
4.5
10.5
8.0
1.0
1.0
12.0
9.0
2.5
1.5
11.0
8.5
ns
2-5,6
tpHL
Propagation Delay
PRE to On
3.3
5.0
4.5
3.0
7.0
5.0
12.5
9.0
1.0
1.0
15.0
10.5
3.5
2.0
13.5
9.5
ns
2-3,4
tpLH
Propagation Delay
ClRtoOn
3.3
5.0
4.5
3.0
7.0
5.0
12.5
9.0
1.0
1.0
15.0
10.5
3.5
2.0
13.5
9.5
ns
2-3,4
tPZL
tpHZ
'Voltage Range 3.3 is 3.3V ± 0.3V
'Voltage Range 5.0 Is 5.0V ± 0.5V
4-317
AC Operating Requirements:
Symbol
See Section 2 for Waveforms
74AC
54AC
74AC
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
3.5
2.0
ns
2-7
2.0
2.5
2.0
2.5
ns
2-7
3.0
3.0
3.5
3.0
3.0
3.0
ns
2-3
5.0
3.0
12.0
8.5
16.0
11.0
14.5
10.0
ns
2-3
3.3
5.0
5.5
4.0
14.0
10.0
18.5
13.0
16.5
12.0
ns
2-3
PRE Recovery Time
3.3
5.0
1.0
0
3.0
1.5
3.5
1.5
3.0
1.5
ns
2-3,7
CLR Recovery Time
3.3
5.0
0
-0.5
1.5
0.5
2.5
1.5
1.5
0.5
ns
2-3,7
Parameter
Vcc·
(V)
ts
Setup Time, HIGH or LOW
On to LE
3.3
5.0
0
-0.5
3.0
1.5
3.5
2.0
th
Hold Time, HIGH or LOW
On to LE
3.3
5.0
-0.5
2.0
2.5
tw
LE Pulse Width, HIGH
3.3
5.0
1.5
1.5
tw
PRE Pulse Width, LOW
3.3
5.0
tw
CLR Pulse Width, LOW
tree
tree
Typ
Guaranteed Minimum
'Voltage Range 3.3 is 3.3V ±0.3V
'Voltage Range 5.0 is 5.0V ±0.5V
4-318
AC Electrical Characteristics:
Symbol
Parameter
Vee·
(V)
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Min
Typ
Max
Min
Max
Min
Max
Units
Fig.
No.
tpLH
Propagation Delay
DntoOn
S.O
2.5
5.5
9.5
1.0
11.0
2.0
10.0
ns
2-3,4
tpHL
Propagation Delay
DntoOn
5.0
2.5
5.5
9.5
1.0
11.0
2.0
10.0
ns
2-3,4
tpLH
Propagation Delay
LE to On
5.0
2.5
5.5
9.0
1.0
11.0
2.0
10.0
ns
2-3,4
tpHL
Propagation Delay
LE to On
5.0
2.5
5.5
9.0
1.0
11.0
2.0
10.0
ns
2-3,4
tpLH
Propagation Delay
PRE to On
5.0
2.5
6.5
14.0
1.0
17.5
2.0
16.0
ns
2-3,4
tpHL
Propagation Delay
CLR to On
5.0
2.5
7.5
15.5
1.0
19.0
2.0
17.5
ns
2-3,4
tpZH
Output Enable Time
OEtoO n
5.0
2.5
5.5
9.5
1.0
11.0
2.0
10.5
ns
2-5,6
tPZL
Output Enable Time
OEtoOn
5.0
2.5
5.5
9.5
1.0
11.0
2.0
10.5
ns
2-5,6
tpHZ
Output Disable Time
OE to On
5.0
2.5
6.0
10.5
1.0
12.0
2.0
11.0
ns
2-5,6
tpLZ
Output Disable Time
OEtoO n
5.0
2.5
6.0
10.5
1.0
12.0
2.0
11.0
ns
2-5,6
tpHL
Propagation Delay
PRE to On
5.0
2.5
6.0
10.5
1.0
12.5
2.0
11.0
ns
2-3,4
tpLH
Propagation Delay
CLR to On
5.0
2.5
5.5
9.5
1.0
11.5
2.0
10.5
ns
2-3,4
'Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements:
Symbol
Parameter
Vee·
(V)
See Section 2 for Waveforms
74ACT
S4ACT
74ACT
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dnto LE
5.0
-0.5
0.5
1.0
1.0
ns
2-7
th
Hold Time, HIGH or LOW
Dn to LE
5.0
0.5
2.0
2.0
2.0
ns
2-7
tw
LE Pulse Width, HIGH
5.0
2.0
3.5
3.5
3.5
ns
2-3
tw
PRE Pulse Width, LOW
5.0
5.0
8.5
11.0
10.0
ns
2-3
tw
CLR Pulse Width, LOW
5.0
5.5
9.S
12.5
11.0
ns
2-3
tree
PRE Recovery Time
5.0
0.5
2.0
2.0
2.0
ns
2-3,7
tree
CLR Recovery Time
5.0
-0.5
1.0
1.0
1.0
ns
2-3,7
'Voltage Range 5.0 is 5.0V ±0.5V
4-319
II
.. r---------------------------------------------------------------------------------,
~
flO
Capacitance
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPD
Power Dissipation
Capacitance
44
pF
Vee = 5.0V
Symbol
4·320
r---------------------------------------------------------------------~
~National
m
.Do
U'I
~ Semiconductor
54ACT174ACT845
8-Bit Transparent Latch with TRI-STATE® Outputs
General Description
Features
The 'ACT845 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide easy expansion through multiple DE: controls.
- 'ACT845 has TTL-compatible inputs
The 'ACT845 is functionally and pin compatible with AMD's
Am29845.
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and sOle
0E1
0E2
0E3
0E1
24
VCC
o~
23
0E3
00
22
PRE
TLlF/9B96-3
Pin Names
0 0- 0 7
0 0- 0 7
OE1-0E3
lE
ClR
PRE
Description
Data Inputs
Data Outputs
Output Enables
Latch Enable
Clear
Preset
CLR
21
°1
LE
20
00
10
°0
03
04
19
°2
03
18
°4
01
°1
17
~
°2
16
03
°5
06
°3
10
IS
0,
D4
°4
CLR
11
14
PRE
Os
°5
GNO
12
13
LE
D6
°6
0,
TLlF/9B96-1
°7
TL/F/9B96-5
Pin Assignment
for lee
06 05 04 NC 03 O2 01 ,
[j] lim 12l1§:)[ZlIID ~
I?~
III DO
rn
CLRJi]j
GNOJi]J
NC~
0E2
[!I OE,
[I) NC
LE Ii§!
~Vcc
PRE IilI
~0E3
°71i!1
~OO
1iID1m~~~~~
06 05 04 NC 03 02 0,
TLlF/9B96-2
4-321
•
U)
oo:t
CD
r---------------------------------------------------------------------------------,
Functional Description
The 'ACT845 consists of eight 0 latches with TRI-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous operation as the output transition follows the data in transition.
On the LE HIGH-to-LOW transition, the data that meets the
setup times is latched OatS appears on the "bus when the
Output Enables (OE1, OE2, OEa) are LOW. When anyone
of OE1, 0E2 or OEa is HIGH, the bus output is in the high
impedance state.
Function Table
Inputs
Internal
Output
CLR
PRE
OEn
LE
0
Q
0
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
L
H
L
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
L
H
H
L
L
H
L
H
NC
L
H
NC
H
L
H
L
H
Z
Z
Z
L
H
NC
H
L
H
Z
Z
X
X
X
L
L
X
L
H
X
X
X
X
X
X
Function
HighZ
HighZ
Latched
Transparent
Transparent
Latched
Preset
Clear
Preset
Clear/High Z
Preset/High Z
H = HIGH Voltage level
l = lOW Voltage level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
TlIF/9896-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4-322
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee)
Supply Voltage (Vecl
'AC
'ACT
Input Voltage (VI)
Output Voltage (Va)
DC Input Diode Current (11K)
VI = -0.5V
-20mA
+20mA
VI = Vee +0.5V
DC Input Voltage (VI)
-0.5V to Vee +0.5V
DC Output Diode Current (10K)
Va = -0.5V
-20mA
+20mA
Va = Vee + 0.5V
DC Output Voltage (Va)
-0.5V to Vee +0.5V
DC Output Source or Sink Current (10)
±50mA
DC Vee or Ground Current
Per Output Pin (Icc or IGND)
Storage Temperature (T8TG)
Junction Temperature (TJ)
CDIP
PDIP
2.0Vt06.OV
4.5Vt05.5V
OV to Vee
OV to Vee
Operating Temperature (TA)
74ACT
54ACT
Minimum Input Edge Aate (6. V / 6.t)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Aate (6.V/6.t)
'ACT Devices
VIN from O.SV to 2.0V
Vee @ 4.5V, 5.5V
±50mA
-65'C to + 150'C
-40'Cto +S5'C
-55'C to + 125'C
125 mV/ns
125 mV/ns
175'C
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, IQ ensure that the system design is reliable over its power supply.
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics for' ACT Family Devices
Symbol
Parameter
74ACT
54ACT
74ACT
TA = 25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Units
(V)
Vee
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
4.5
5.5
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
1.5
1.5
O.S
O.S
O.S
O.S
O.S
O.S
V
4.5
5.5
VOUT = O.W
or Vee - O.W
VOH
Minimum High Level
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
4.5
5.5
lOUT = -50 p.A
3.S6
4.S6
3.70
4.70
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
0.001
0.001
V
4.5
5.5
'VIN = VIL or VIH
-24mA
10H
-24mA
lOUT = 50 p.A
'VIN = VIL or VIH
24mA
10L
24mA
liN
Maximum Input
Leakage Current
±0.1
±1.0
±1.0
p.A
5.5
loz
Maximum TAl-STATE
Leakage Current
±0.5
±10.0
±5.0
p.A
5.5
VI = VIL, VIH
Va = Vee,GND
leCT
Maximum Icc/Input
1.6
1.5
mA
5.5
VI = Vee - 2.1V
10LD
tMinimum Dynamic
Output Current
50
75
mA
5.5
VOLO = 1.65V Max
-50
-75
mA
5.5
VOHD = 3.S5V Min
160
SO
p.A
5.5
VIN = Vee
or Ground
10HD
ICC
0.6
Maximum Quiescent
Supply Current
S.O
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc limit for 54ACT
@
25·C is identical to 74ACT
@
25·C.
4-323
VI = Vee,GND
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25"C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -400C
to +85'C
CL = 50pF
Min
Min
Max
Units
Vcc'
(V)
Fig.
No.
Min
Typ
Max
tpLH
Propagation Delay
Dn to On
2.0
5.5
9.5
2.0
10.0
ns
5.0
2-3,4
tpHL
Propagation Delay
Dn to On
2.0
5.5
9.5
2.0
10.0
ns
5.0
2-3,4
tpLH
Propagation Delay
lE to On
2.0
5.5
9.0
2.0
10.0
ns
5.0
2-3,4
tpHL
Propagation Delay
lEto On
2.0
5.5
9.0
2.0
10.0
ns
5.0
2-3,4
tpLH
Propagation Delay
PRE to On
2.0
6.5
14.0
2.0
16.0
ns
5.0
2-3,4
tpHL
Propagation Delay
ClR to On
2.0
7.5
15.5
2.0
17.5
ns
5.0
2-3,4
tpZH
Output Enable Time
OEtoOn
2.0
5.5
9.5
2.0
10.5
ns
5.0
2-5
tpZL
Output Enable Time
OE to On
2.0
5.5
9.5
2.0
10.5
ns
5.0
2-6
tpHZ
Output Disable Time
OEtoOn
2.0
6.0
10.5
2.0
11.0
ns
5.0
2-5
2.0
6.0
10.5
2.0
11.0
ns
5.0
2-6
tpLZ
Output Disable Time
DE to On
Max
tpHL
Propagation Delay
PRE to On
2.0
6.0
10.5
2.0
11.0
ns
5.0
2-3,4
tpLH
Propagation Delay
ClR to On
2.0
5.5
9.5
2.0
10.5
ns
5.0
2-3,4
'Voltage Range 5.0 Is 5.0V ± O.5V
4·324
AC Operating Requirements:
Symbol
Parameter
See Section 2 for Waveforms
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Typ
Units
Vcc·
(V)
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dnto LE
-0.5
0.5
1.0
ns
5.0
2-7
th
Hold Time, HIGH or LOW
Dn to LE
0.5
2.0
2.0
ns
5.0
2-7
tw
LE Pulse Width, HIGH
2.0
3.5
3.5
ns
5.0
2-3
tw
PRE Pulse Width, LOW
5.0
8.5
10.0
ns
5.0
2-3
tw
CLR Pulse Width, LOW
5.5
9.5
11.0
ns
5.0
2-3
tree
PRE Recovery Time
0.5
2.0
2.0
ns
5.0
2-3,7
tree
CLR Recovery Time
0
1.0
1.0
ns
5.0
2-3,7
'Voltage Range 5.0 is S.OV ± o.sv
Capacitance
Symbol
Parameter
Typ
Units
C'N
Input Capacitance
4.5
pF
Vee
= 5.0V
CPO
Power Dissipation
Capacitance
44
pF
Vee
= 5.0V
Conditions
II
4-325
~National
~ Semiconductor
54AC/74AC899 • 54ACT174ACT899
9-Bit Latchable Transceiver
with Parity GeneratorIChecker
General Description
Features
The 'AG/'ACT899 is a 9-b!t to 9-blt parity transceiver with
transparent latches. The device can operate as a feedthrough transceiver or it can generate/ check parity from the
8-bit data busses in either direction. The' AGI' AGT899 features independent latch enables for the A-to-B direction and
the B-to-A direction, a select pin for ODD/EVEN parity, and
separate error signal output pins for checking parity.
• Latchable transceiver with output sink of 24 mA
• Option to select generate parity and check or "feedthrough" data/parity in directions A-to-B or B-to-A
• Independent latch enable for A-to-B and B-to-A directions·
• Select pin for ODD/EVEN parity
• ERRA and ERRB output pins for parity checking
• Ability to simultaneously generate and check parity
• May be used in system applications in place of the '534
and '280
• May be used in system applications in place of the '657
and '373 (no need to change T /R to check parity)
• 4 kV minimum ESD immunity
Ordering Code: See Section 8
Logic Symbol
Connection Diagram
Pin Assignment for PCC
A7 A6 As A4 A3 A2 A\
[i]1i2l[!)rrum[[J[[)
iii AD
IIJLEA
III ERRA
APAR Ii]
GBA IIID
GND[j]J
ERRBfi]J
SEL liE
LEB Ii1I
BPAR IiID
TL/F/l0637-1
4-326
[j] ODD/EVEN
~VCC
1m GAB
~Bo
1iID~1iJl~I~H~~
B7 86 85 84 B3 82 8\
TLlF/l0637-2
Pin Names
Description
Ao-A7
Bo-B7
APAR,BPAR
ODD/EVEN
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active
LOW for EVEN Parity
Output Enables for A or B Bus,
Active LOW
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
Latch Enables for A and B Latches,
HIGH for Transparent Mode
Error Signals for Checking
Generated Parity with Parity In,
LOW if Error Occurs
GBA,GAB
SEL
LEA, LEB
ERRA,ERRB
Functional Description
The 'AC/'ACT899 has three principal modes of operation
which are outlined below. These modes apply to both the Ato-B and B-to-A directions.
-
Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select.{SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be
checked and monitored by ERRB (ERRA).
-
Bus A (B) communicates to Bus
mode if SEL is HIGH. Parity
checked as ERRA and ERRB in
(can be used as an interrupt to
error to the CPU).
-
Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function Table below).
B (A) in a feed-through
is still generated and
the feed-through mode
signal a data/parity bit
Function Table
Inputs
GAB GBA SEL
Operation
LEA
LEB
H
X
X
X
Busses A and Bare TRI-STATE®.
H
L
L'
L
H
Generates parity from B[0:7] based on OlE (Note 1). Generated parity
..... APAR. Generated parity checked against BPAR and output as
ERRB.
H
L
L
H
H
Generates parity from B[0:7] based on OlE. Generated parity .....
APAR. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check
asERRA.
H
L
L
X
L
Generates parity from B latch data based on OlE. Generated parity
..... APAR. Generated parity checked against latched BPAR and
output as ERRB.
H
L
H
X
H
BPAR/B[0:7] ..... APAR/ AO:7] Feed-through mode. Generated parity
checked against BPAR and output as ERRB.
H
L
H
H
H
BPAR/B[0:7] ..... APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch for
generate/check as ERRA.
L
H
L
H
L
Generates parity for A[0:7] based on OlE. Generated parity .....
BPAR. Generated parity checked against APAR and output as ERRA.
L
H
L
H
H
Generates parity from A[0:7] based on OlE. Generated parity .....
BPAR. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check
as ERRB.
L
H
L
L
X
Generates parity from A latch data based on OlE. Generated parity
..... BPAR. Generated parity checked against latched APAR and
output as ERRA.
L
H
H
H
L
APAR/A[0:7] ..... BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and
output as ERRA.
L
H
H
H
H
APAR/A[O:71 ..... BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch for
generate/check as ERRB.
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immatanal
Note 1: OlE
= ODD/Ei7EIii
4-327
II
Functional Block Diagram
ror--;::::::::
TRA:;:A~ENT
-
LATCH
9-'bR
Output
Buffer
III
=
=
PARITY
GENERAmR
=
-
r0-
LE
---
:~
f=
f=
9-bft
-
9-bft
TRANSPARENT
Output
=
Buffer
~
LATCH
~I-----t
===-
LE
GENERAmR
I
I
ODO!£VEN
LEB
TLlF/l0637-3
AC Path
SEL
1------------------------------------------
An. APAR
(Bn. BPAR)
/
Bn. BPAR
(An. APAR)
''---
INPUT
OUTPUT
TLlF/l0637-4
An. APAR --+ Bn. BPAR
(Bn• BPAR --+ An. APAR)
FIGURE 1
4·328
Q)
AC Path
co
co
(Continued)
SEL
OlE
0
0
LEA
(LEB)
AIO:71
(BIO:71)
ODD PARIlY
INPUT
BPAR
(APAR)
OUTPUT
An -- BPAR
(Bn -- APAR)
TL/F/l0637-5
FIGURE 2
OlE
APAR
(BPAR)
0
0
LEA
(LEB)
AlO:71
(BIO:71)
ODD PARIlY
INPUT
ERRA
(ERRB)
OUTPUT
An -> ERRA
(Bn --+ ERRB)
TL/F/l0637-6
FIGURE 3
APAR
(BPAR)
AIO:71
(BIO:7I)
=><
EVEN PARIlY
INPUT
OlE
ERRA
(ERRB)
OlE -OlE --+
ERRA
ERRB
INPUT
OUTPUT
TPLH
TL/F/l0637-7
FIGURE 4
4-329
m
m
co
AC Path
(Continued)
SEL
APAR
(8PAR)
A[O:7J
(8[0:71)
0
0
=><
EVEN PARITY
INPUT
INPUT
OlE
OPAR
(APAR)
OUTPUT
TPLH
ole -+ SPAR
(Ole -+ APAR)
TLlF/l0637-8
FIGURES
OlE
A[0:71
(0[0:71)
0
=><
EVEN PARITY
INPUT
APAR
(8PAR)
INPUT
ERRA
(ERRO)
OUTPUT
APAR -+ ERRA
(SPAR -+ ERRS)
TPLH
TL/F/l0637-9
FIGURE 6
SEL
1
GAO
(G8A)
INPUT
8PAR,O[0:71
(APAR, A!0:71)
0.3V
TPHZ
OUTPUT
TPZH
ZH.HZ
TLlF/l0637-10
FIGURE 7
4-330
CD
CD
CD
AC Path (Continued)
SEL 1- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
GAB
INPUT
(GSA)
BPAR, B[0:71
(APAR, A[0:71)
OUTPUT
0.3V
TPLZ
TPZL
TL/F/10637-11
ZL, LZ
FIGURES
OlE
APAR
(BPAR)
A[0:71
(B[0:71)
0
::x
--------------------------------------------_______________EV
__
EN_P_A_RI_TY___________________
INPUT
INPUT
OUTPUT
BPAR
(APAR)
SEL
(SEC
~
TLlF/10637-12
BPAR
~ APAR)
FIGURE 9
OlE
AlO:7I, APAR
(B[0:7I, BPAR)
--~/
'~---",/
LEA
INPUT
INPUT
(LEB)
B[0:7I, BPAR
(A[0:7I, APAR)
OUTPUT
LEA ~ BPAR. B[0:7]
(LEB ~ APAR, A[O:7J)
TL/F/10637-13
FIGURE 10
4-331
AC Path
(Continued)
LEA
(LEB)
INPUT
'!'I...
~/
APAR, A[o:7J
(BPAR, B[0:7J)
-
TS(H) -
TS(H), TH(H)
INPUT
'I\..
I--
TH(H)
I-TLlF/l0637-14
LEA ..... APAR, A(0:7]
(LEB ..... BPAR, B(0:7])
FIGURE 11
LEA
(LEB)
INPUT
'!'I...
APAR, A[o:7J
(BPAR, B[o:7])
'I\..
TS(L)-
TS(L), TH(L)
-
~/
INPUT
I-- TH(L)
iTLlF/l0637-15
LEA ..... APAR, A(0:7]
(LEB ..... BPAR, B(0:7])
FIGURE 12
LEA
(LEB)
~/
'!'I...
INPUT
APAR, A[O:7J
(BPAR, B[o:7J)
INPUT
BPAR, MO:7J
(APAR, B[0:7J)
OUTPUT
I-
TW--
TL/F/l0637-16
FIGURE 13
4-332
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee)
DC Input Diode Current (111<>
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
. DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
-20mA
Vo = -0.5V
+20mA
Vo = Vee + 0.5V
DC Output Voltage (VO)
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGNO)
-65·Cto + 150·C
Storage Temperature (TSTG)
DC Latch-Up Source or
±300mA
Sink Current
Junction Temperature (TJ)
CDIP
175·C
140·C
PDIP
Note 1: Absolute maximum ratings are those values beyond which damage
Recommended Operating
Conditions
Supply Voltage (Vee)
'AC
'ACT
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TAl
74AC/ACT
54AC/ACT
Minimum Input Edge Rate AV/At
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate AVI At
'ACT Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V. 5.5V
2.0Vt06.0V
4.5Vto 5.5V
OVtoVee
OV to Vee
- 40·C to + 85·C
- 55·C to + 125·C
125 mV/ns
125 mVlns
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design Is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics for' AC Family Devices
74AC
Symbol
Parameter
Vee
(V)
TA
= +25·C
Typ
VIH
VIL
VOH
liN
74AC
TA=
-40"C to +85·C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
,..A
3.0
4.5
5.5
VOL
54AC
TA=
-55·C to + 125·C
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
'Maximum of 9 outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
4-333
lOUT = -50,..A
V
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50,..A
V
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee.GND
(Note)
III
DC Electrical Characteristics for' AC Family Devices (Continued)
Symbol
Parameter
VCC
(V)
74AC·
54AC
74AC
TA = +25'C
TA=
-55"C to + 125"C
TA=
- 40"C to + 85'C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Icc
Maximum Quiescent
Supply Current
IOZ
Maximum TRI-STATE
Leakage Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.S5V Min
5.5
S.O
160.0
SO.O
/LA
VIN = Vcc
or GND (Note)
5.5
±0.5
±10.0
±5.0
/LA
VI(OE) = VIL. VIH
VI = Vcc.GND
Vo = VCC.GND
'Maximum of 9 outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a·time.
Note: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective IImH @ 5.5V Vee. Icc for 54AC @ 25'C Is identical to 74AC @ 25"C.
DC Electrical Characteristics for' ACT Family Devices
Symbol
Parameter
Vee
(V)
74ACT
54ACT
74ACT
TA = +25'C
TA=
-55"C to + 125"C
TA=
-40"Cto +85"C
Typ
Units
Conditions
Guaranteed limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
orVcc - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.S
O.S
O.S
O.S
O.S
O.S
V
VOUT = 0.1V
orVcc -0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.S6
4.S6
3.70
4.70
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
V
lOUT = -50/LA
·VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50/LA
·VIN = VIL or VIH
24mA
IOL
24mA
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
/LA
loz
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
/LA
VI = VIL. VIH
Vo = Vcc.GND
ICCT
Maximum Icc/Input
5.5
1.6
1.5
mA
VI = Vcc - 2.W
IOLD
tMinimum Dynamic
Output Current
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.S5V Min
/LA
VIN = Vee
or GND (Note)
IOHD
Icc
Maximum Quiescent
Supply Current
0.6
5.5
S.O
160.0
'Maximum of 9 outputs loaded; thresholds on Input associaied with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note: Icc for 54ACT @ 25'C is identical to 74ACT @ 25'C.
4-334
SO.O
VI = Vcc.GND
AC Electrical Characteristics
Symbol
Parameter
Vcc·
(V)
74AC
54AC
74AC
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Min
Fig.
No.
Min
Typ
Max
Min
Max
tpLH
tpHL
Propagation Delay
An, Bn to Bn, An
3.3
5.0
2.5
1.5
12.0
7.0
15.0
10.0
2.5
1.5
15.5
10.5
ns
1
tpLH
tpHL
Propagation Delay
APAR, BPAR to BPAR, APAR
3.3
5.0
2.5
1.5
9.5
5.5
12.0
8.0
2.5
1.5
12.5
8.5
ns
1
tpLH
tpHL
Propagation Delay
An, Bn to BPAR, APAR
3.3
5.0
3.0
2.0
13.5
8.0
16.5
11.0
3.0
2.0
17.0
11.5
ns
2
tpLH
tpHL
Propagation Delay
An, Bn to ERRA, ERRB
3.3
5.0
2.5
1.5
12.5
7.5
15.5
10.5
2.5
1.5
16.5
11.0
ns
3
tpLH
tpHL
Propagation Delay
ODD/EVEN to ERRA, ERRB
3.3
5.0
2.5
1.5
12.5
7.5
15.5
10.5
2.5
1.5
16.5
11.0
ns
4
tpLH
tpHL
Propagation Delay
ODD/EVEN to APAR, BPAR
3.3
5.0
3.0
2.0
12.5
7.5
15.5
10.5
3.0
2.0
16.5
11.0
ns
5
tpLH
tpHL
Propagation Delay
APAR, BPAR to ERRA, ERRB
3.3
5.0
2.0
1.5
12.5
7.5
15.5
10.5
2.0
1.5
16.5
11.0
ns
6
tpLH
tpHL
Propagation Delay
SEL to APAR, BPAR
3.3
5.0
2.0
1.5
10.0
6.0
12.5
8.5
2.0
1.5
13.5
9.0
ns
9
tpLH
tpHL
Propagation Delay
LEB; LEA to An, Bn
3.3
5.0
4.0
2.5
12.0
7.0
15.5
10.5
4.0
2.5
16.5
11.0
ns
10,11
tpLH
tpHL
Propagation Delay
LEB, LEA to APAR, BPAR
3.3
5.0
3.0
2.0
13.5
8.0
17.0
11.5
3.0
2.0
18.0
12.0
ns
10,11
tpLH
tpHL
Propagation Delay
LEB, LEA to ERRA, ERRB
3.3
5.0
4.0
2.5
13.5
8.0
17.0
11.5
4.0
2.5
18.0
12.0
ns
12
tPZH
tPZL
Output Enable Time
GBA, GAB to An, Bn
3.3
5.0
3.0
2.0
12.5
7.5
15.5
10.5
3.0
2.0
16.5
11.0
ns
7,8
tPZH
tpZL
Output Enable Time
GBA, GAB to APAR, BPAR
3.3
5.0
2.5
1.5
10.5
6.0
13.5
9.0
2.5
1.5
14.0
9.5
ns
7,8
tpHZ
tpLZ
Output Disable Time
GBA, GAB to An, Bn
3.3
5.0
1.5
1.0
11.0
6.5
14.0
9.5
1.5
1.0
14.0
9.5
ns
7,8
tpHZ
tpHL
Output Disable Time
GBA, GAB to APAR, BPAR
3.3
5.0
1.5
1.0
11.0
6.5
14.0
9.5
1.5
1.0
14.0
9.5
ns
7,8
'Voltage Range 5.0 is 5.0V ±0.5V.
Voltage Range 3.3 is 3.3V ±0.3V.
4·335
Max
Units
AC Operating Requirements
Symbol
Parameter
74ACT
54ACT
74ACT
(V)
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL=50pF
TA = -40'C
to +85'C
CL = 50pF
Units
Fig.
No.
Vee·
Guaranteed Minimum
ts
Setup Time. HIGH or LOW
An. Bn. PAR to LEA. LEB
3.3
5.0
3.0
3.0
3.0
3.0
ns
11.12
th
Hold Time. HIGH or LOW
An. Bn. PAR to LEA. LEB
3.3
5.0
2.0
1.5
2.0
1.5
ns
11.12
tw
Pulse Width for LEA. LEB
3.3
5.0
4.0
4.0
4.0
4.0
ns
13
Units
Fig.
No.
'Voltage Range 5.0 is 5.0V ±0.5V.
Voltage Range 3.3 is 3.3V ±0.3V.
AC Electrical Characteristics
Symbol
Parameter
Vee·
(V)
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Min
Max
Min
Typ
Max
5.0
2.5
7.5
11.5
2.5
12.0
ns
1
Propagation Delay
APAR. SPAR to SPAR. APAR
5.0
1.5
6.0
8.5
1.5
9.0
ns
1
tpLH
tpHL
Propagation Delay
An. Sn to SPAR. APAR
5.0
2.5
8.5
12.0
2.5
12.5
ns
2
tpLH
tpHL
Propagation Delay
An. Sn to ERRA. ERRS
5.0
2.0
8.0
11.5
2.0
12.0
ns
3
tpLH
tpHL
Propagation Delay
ODD/EVEN to ERRA. ERRB
5.0
2.0
8.0
11.5
2.0
12.0
ns
4
tpLH
tpHL
Propagation Delay
ODD/EVEN to APAR. BPAR
5.0
2.5
8.0
11.5
2.5
12.0
ns
5
tpLH
tpHL
Propagation Delay
APAR. BPAR to ERRA. ERRB
5.0
1.5
7.5
10.5
1.5
11.5
ns
6
tpLH
tpHL
Propagation Delay
SEL to APAR. BPAR
5.0
1.5
6.5
9.0
1.5
9.5
ns
9
tpLH
tpHL
Propagation Delay
LEBtoAn. Bn
5.0
2.5
7.0
10.5
2.5
11.0
ns
10.11
tpLH
tpHL
Propagation Delay
LEA to APAR. BPAR
5.0
2.0
8.0
11.5
2.0
12.0
ns
10.11
tpLH
tpHL
Propagation Delay
LEA. LES to ERRA. ERRB
5.0
2.5
8.0
11.5
2.5
12.0
ns
12
tpZH
tPZL
Output Enable Time
GBA or GAB to An. Bn
5.0
2.5
7.0
10.5
2.5
11.0
ns
7.8
tPZH
tPZL
Output Enable Time
GBA or GAS to BPAR or APAR
5.0
1.5
6.0
9.0
1.5
9.5
ns
7.8
tpHZ
tpHL
GSA or GAB to An. Bn
5.0
1.5
6.5
9.5
1.5
9.5
ns
7.8
tpHZ
tpLZ
Output Disable Time
GBA or GAB to BPAR. APAR
5.0
1.5
6.5
9.5
1.5
9.5
ns
7.B
tpLH
tpHL
Propagation Delay
An. Bn to Bn. An
tpLH
tpHL
Output Disable Time
'Voltage Range 5.0 is 5.0V ± 0.5V.
4-336
Max
AC Operating Requirements
Symbol
Vcc'
(V)
Parameter
74ACT
54ACT
74ACT
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40"C
to +85'C
CL = 50pF
Units
Fig.
No.
Guaranteed Minimum
Is
Setup Time, HIGH or LOW
An, Bn, PAR to LEA, LEB
5.0
3.0
3.0
ns
11,12
Ih
Hold Time, HIGH or LOW
An, Bn, PAR to LEA, LEB
5.0
1.5
1.5
ns
11,12
Pulse Width for LEB, LEA
5.0
4.0
4.0
ns
13
tw
'Voltage Range 5.0
= 5.0V
±0.5V.
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
CPO
Power Dissipation
Capacitance
210
pF
4-337
Conditions
Vee
Vee
= 5.0V
= 5.0V
~National
ADVANCE INFORMATION
~ Semiconductor
54AC/74AC2525 • 54AC/74AC2526
Minimum Skew Clock Driver
The 'AC2525 is a minimum skew clock driver with one input
driving eight outputs specifically designed for signal generation and clock distribution applications. The 2525 is designed to distribute a single clock to eight separate receivers with low skew across all outputs during both the TPLH
and TPHL transitions. The AC2526 is similar to the AC2525
but contains a multiplex~d clock input to allow for systems
with dual clock speeds or systems where a separate test
clock has been implemented.
Features
•
•
•
•
•
Logic Symbols
Ideal for signal generation and clock distribution
Guaranteed pin to pin and part to part skew
Multiplexed clock input (,2526)
Guaranteed 2000V minimum ESO protection
24 mA output drive capability
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
'AC2526
'AC2525
'AC2525
CKIN
°0
°1
00
°1
°2
03
°2
03
GNDO
CKIN
GNDQ
CKO
GND
VCC
GND
GND
Vee
GND
Vee
0.
06
Vee
SEL
CK1
0.
06
°1
TL/F/l0SB4-1
TL/F/l0BB4-3
Os
TLlF/l0BB4-4
Pin Assignment
forLCC
'AC2526
CK1
GNOQ GND NC vee NC
GNDQ GND NC vee SEL
III III IIlIIJ[II
1Il1Il1Il[Il1Il
°slI2l
III 0 0
III 02
III 00
III 02
NC
IIil
°slI2l
[j] NC
NC
IIil
[j]NC
07
trn
~01
07
trn
~01
Os
1m
1i!I°3
Os
1m
1i!I°3
0.1]]
SEL
TL/F/l0BB4-2
trnliIDli]]liZlli]]
CKI GND NC Vee CKO
trnliIDli]]liZlli!l
NC GND NC VeeCKIN
TLlF/l0664-5
4-338
0.1]]
TL/F/l06B4-6
r----------------------------------------------------------------------------,
~
CD
~National
~
~ Semiconductor
54AC/7 4AC270S e 54ACT17 4ACT270S
64 X 9 First-In, First-Out Memory
General Description
The 'AC/'ACT2708 is an expandable first-in, first-out memory organized as 64 words by 9 bits. An 85 MHz shift-in and
60 MHz shift-out typical data rate makes it ideal for highspeed applications. It uses a dual port RAM architecture
with pOinter logic to achieve the high speed with negligible
fall-through time.
Separate Shift-In (51) and Shift-Out (SO) clocks control the
use of synchronous or asynchronous write or read. Other
controls include a Master Reset (MR) and Output Enable
(OE) for initializing the internal registers and allowing the
data outputs to be TRI-STATE
OR
<5
0..
HF
FULL
OE---~W'
TL/F/l0144-4
4-340
Functional Description
INPUTS
Output Ready (OR)
Data Inputs (00-08)
Data inputs for 9-bit wide data are TTL-compatible. Word
width can be reduced by trying unused inputs to ground and
leaving the corresponding outputs open.
OR HIGH indicates data can be shifted-out from the FIFO.
When SO goes HIGH. OR goes LOW, indicating output
stage is busy. OR is LOW when the FIFO is reset or empty
and goes HIGH after the falling edge of the first shift-in.
Half-Full (HF)
Reset (MR)
This status flag along with the FULL status flag indicates the
degree of fullness of the FIFO. On reset, HF is LOW; it rises
on the falling edge of the first SI. The rising edge of the SI
pulse that fills up the FIFO makes HF go LOW. Going from
the empty to the full state with SO LOW. the falling edge of
the first SI causes HF to go HIGH. the riSing edge of the
33rd SI causes FULL to go HIGH. and the rising edge of the
64th SI causes HF to go LOW.
Reset is accomplished by pulsing the MR input LOW. During
normal operation MR is HIGH. A reset is required after power up to guarantee correct operation. On reset, the data
outputs go LOW. IR goes HIGH. OR goes LOW, FH and
FULL go LOW. During reset, both internal read and write
pointers are set to the first location in the array.
Shift-In (SI)
When the FIFO is full. HF is LOW and the falling edge of the
first shift-out causes HF to go HIGH indicating a "non-full"
FIFO.
Data is written into the FIFO by pulsing SI HIGH. When
Shift-In goes HIGH, the data is loaded into an internal data
latch. Data setup and hold times need to be adhered to with
respect to the falling edge of SI. The write cycle is complete
after the falling edge of SI. The shift-in is independent of any
ongoing shift-out operation. After the first word has been
written into the FIFO. the falling edge of SI makes HF go
HIGH, indicating a non-empty FIFO. The first data word appears at the output after the falling edge of SI. After half the
memory is filled, the next rising edge of SI makes FULL go
HIGH indicating a half-full FIFO. When the FIFO is full. any
further shift-ins are disabled.
Full Flag (FULL)
This status flag along with the HF status flag indicates the
degree of fullness of the FIFO. On reset, FULL is LOW.
When half the memory Is filled. on the rising edge of the
next SI, the FULL flag goes HIGH. It remains set until the
difference between the write pointer and the read pOinter is
less than or equal to one-half of the total memory of the
device. The FULL flag then goes LOW on the rising edge of
the next SO.
When the FIFO is empty and OE is LOW, the falling edge of
the first SI will cause the first data word just shifted-in to
appear at the output. even though SO may be LOW.
Status Flags Truth Table
Shift-Out (SO)
Data is read from the FIFO by the Shift-Out signal provided
the FIFO is not empty. SO going HIGH causes OR to go
LOW indicating that output stage is busy. On the falling
edge of SO, new data reaches the output after propagation
delay to. If the last data has been shifted-out of the memory,
OR continues to remain LOW, and the last word shifted-out
remains on the output pins.
HF
FULL
L
L
H
H
L
H
L
H
Status Flag Condition
Empty
Full
<32 Locations Filled
~ 32 Locations Filled
H = HIGH Voltage Level
L = LOW Voltage Level
Reset Truth Table
Output Enable (OE)
Inputs
OE LOW enables the TRI-STATE output buffers. When OE
is HIGH, the outputs are in a TRI-STATE mode.
OUTPUTS
Data Outputs (00-08)
Data outputs are enabled when OE is LOW and in the TRISTATE condition when OE is HIGH.
Outputs
MR
SI
SO
IR
OR
HF
FULL
00-0 6
H
L
X
X
X
X
X
X
X
X
X
H
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Input Ready (IR)
IR HIGH indicates data can be shifted-in. When SI goes
HIGH, IR goes LOW, indicating input stage is busy. IR stays
LOW when the FIFO is full and goes HIGH after the falling
edge of the first shift-out.
4-341
Functional Description (Continued)
4. Shift-In is set LOW; IR goes HIGH indicating the FIFO is
ready for additional data. Data just shifted-in arrives at
output propagation delay tODs after SI falls. OR goes
HIGH propagation delay tlOR after SI goes LOW, indicating the FIFO has valid data on its outputs. HF goes HIGH
propagation delay tiE after SI 1alls, indicating the FIFO is
no longer empty.
5. The process is repeated through the 64th data word. On
the rising edge of the 33rd SI, FULL flag goes HIGH propagation delay tlHF after SI, indicating a half-full FIFO. HF
goes LOW propagation delay tlF after the rising edge of
the 64th pulse indicating that the FIFO is full. Any further
shift-ins are disabled.
MODES OF OPERATION
Mode 1: Shin In Sequence for FIFO Empty to FUll,
Sequence of Operation
1. Input Ready is initially HIGH; HF and FULL flags are
LOW. The FIFO is empty and prepared for valid data. OR
is LOW indicating that the FIFO is not yet ready to output
data.
2. Shift-In is set HIGH, and data is loaded into the FIFO.
Data has to be settled ta· before the falling edge of SI and
held th after.
3. input Ready (lR) goes LOW propagation delay tlR after SI
goes HIGH: input stage is busy.
1st PULSE
33rd PULSE
64th PULSE
SI
IR
FU~----------~------------------~I~----~
HF ________~-'I~--------------~r-------------~s~
OR--------~-"
1st
DATA WORD
OO-08-------------J'I'---------------~r_--------------~S~~----------TL/F/10144-5
Note: so and DE are LOW; MR Is HIGH.
FIGURE 1. Modes of Operation Mode 1
4-342
Functional Description
(Continued)
Mode 2: Master Reset
Sequence of Operation
4. IR rises (if not HIGH already) to indicate ready to write
state recovery time tMRIRH after the falling edge of MR.
Both HF and FULL will go LOW indicating an empty FIFO.
occurring recovery times tMRE and tMRO respectively after the falling edge of MR. OR falls recovery time tMR<;JRL
after MR falls. Data at outputs goes LOW recovery time
tMRONL after MR goes LOW.
5. Shift-In can be taken HIGH after a minimum recovery
time tMRSIH after MR goes HIGH.
1. Input and Output Ready. HF and FULL can be in any
state before the reset sequence with Master Reset (MR)
HIGH.
2. Master Reset goes LOW and clears the FIFO. setting up
all essential internal states. Master Reset must be LOW
pulse width tMRW before rising again.
3. Master Reset rises.
50----------~--------~------------------_r-------
51 _______________________________________-'
TLlF/l0144-6
FIGURE 2. Mode of Operation Mode 2
4-343
:ew
Functional Description (Continued)
3. Input Ready goes HIGH one fall-through time, tFT, after
the falling edge of SO. Also, HF goes HIGH one toF after
SO falls, indicating that the FIFO is no longer full. '
4. IR returns LOW pulse width tiP after rising and shifting
new data in. Also, HF returns LOW pulse width iaF after
rising, indicating the FIFO is once more full.
5. Shift-In is brought LOW to complete the shift-in process
and maintain normal operation
Mode 3: With FIFO Full, Shift-In Is Held HIGH
In Anticipation of an Empty location
Sequence of Operation
1. The FIFO is initially full and Shift-In goes HIGH. OR is
initially HIGH. Shift-Out is LOW. IR is LOW.
2. Shift-Out is pulsed HIGH, Shift-Out pulse propagates and
the first data word is latched on the rising edge of SO. OR
falls on this edge. On the falling edge o1SO, the second
data word appears after propagation delay 10. New data
is written into the FIFO after SO goes LOW.
/
so
\.
51
t"
IR
~~
I
I
\.
/
OR
-
HF
I.
J
!:::::1
tor--1"==.t3
I
FULL
'1
X
\.
rULL
1
NEW DATA
X
~-08 ____________~I~.~W~O~RD~__________~~________~2n~d~W~O~RD~_________
I--tD
Note: J\m and FULL are HIGH;
TL/F/l0144-7
rn: is LOW.
FIGURE 3. Modes of Operation Mode 3
4-344
Functional Description
(Continued)
Mode 4: Shift-Out Sequence, FIFO Full to Empty
4. Repeat process through the 64th SO pulse. FULL flag
goes LOW one propagation delay. toHF. after the rising
edge of 33rd SO. indicating that the FIFO is less than half
full. On the falling edge of the 64th SO. HF goes LOW
one propagation delay. toE, after SO, indicating the FIFO
is empty. The SO pulse may rise and fall again with an
attempt to unload an empty FIFO. This results in no
change in the data on the outputs as the 64th word stays
latched.
Sequence of Operation
1. FIFO is initially full and OR is HIGH. indicating valid data
is at the output. IR is LOW.
2. SO goes HIGH. resulting in OR gOing LOW one propagation delay. tOR, after SO rises. OR LOW indicates output
stage is busy.
3. SO goes LOW. new data reaches output one propagation
delay. to. after SO falls; OR goes HIGH one propagation
delay. tOR. after SO falls and HF rises one propagation
delay. tOF. after SO falls. IR rises one fall-through time,
tFT. after SO falls.
1st PULSE
33rd PULSE
64th PULSE
OR
IR _ _ _ _I-'I
HF _ _ _ __
TLIFll0144-8
Note: Sl and C5E are LOW; MR Is HIGH; Do-Os are Immaterial.
FIGURE 4. Modes of Operation Mode 4
II
4-345
Functional Description (Continued)
Mode 5: With FIFO Empty. Shift-Out Is Held HIGH
In Anticipation of Data
Sequence of Operation
1. FIFO is initially empty; Shift-Out goes HIGH.
4. Data arrives at output one propagation delay, ta05, after
the falling edge of Shift-In.
5. OR goes LOW pulse width top after rising and HF goes
LOW pulse width tX3 after rising, indicating that the FIFO
is empty once more.
2. Shift-In pulse loads data into the FIFO and IR falls. HF
rises propagation delay tX1 after the falling edge of SI.
6. Shift-Out goes LOW, necessary to complete the Shift-Out
process.
3. OR rises a fall-through time of tFTO after the falling edge
of Shift-In, indicating that new data is ready to be output.
/
51
~
IFTO _
so
OR
lI-Iop-i
\.
I
IR
~
X
NEW DATA
HF
EMPTY
NEW DATA
X
-u4-IX3-i
EMPTY
TL/F/10144-9
Note: FULL is LOW; MR is HIGH; OE Is LOW; tOOF = tFTO -
taos. Data oulputtransilion-valid data arrives at output stage IOOF after OR is HIGH.
FIGURE 5. Modes of Operation Mode 5
4-346
,---------------------------------------------------------------------------------, ....a
~
CI
FIFO Expansion
CD
Word Width Expansion
Word width can be increased by connecting the corre·
sponding input control signals of multiple devices. Flags can
be monitored to obtain a composite signal by ANDing the
corresponding flags.
FULL 1
t
FUL~
9"
DIN (0-8)
DO- 8
FIF01
64x9
SO
r--
r
DC Input Diode Current (11K)
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
-20mA
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5V to Vee + O.5V
DC Output Source or Sink Current (10)
±32mA
DC Vee or Ground Current
±32mA
per Output Pin (lee or IGNO)
Storage Temperature (TSTG)
-65'C to + 150'C
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
10 the device may occur. The datebook specifications should be met. without
excepUon. to ensure that the system design Is reliable over Its power supply.
temperature. and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
Supply Voltage (Vee>
'AC
'ACT
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TA)
74AC/ACT
54AC/ACT
Minimum Input Edge Rate (a VI at)
'AC Devices
VIN from 30% to 70% of Vee
Vee @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (aVlat)
'ACT devices
VIN from O.SV to 2.0V
Vee @ 4.5V, 5.5V
2.0Vt06.0V
4.5Vt05.5V
OVtoVee
OV to Vee
-40"Cto +S5'C
- 55'C to + 125'C
125mV/ns
125mVlns
DC Characteristics for' AC Family Device
54AC
74AC
TA = -55'C
to + 125'C
TA = -40"
to +85'C
74AC
Symbol
Parameter
Vee
(V)
TA
= 25'C
VIL
VOH
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.S5
2.1
3.15
3.S5
2.1
3.15
3.S5
V
VOUT = O.W
or Vee -O.W
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.W
or Vee -O.W
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.S6
4.S6
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
p.A
5.5
±0.5
±10.0
±5.0
3.0
4.5
5.5
VOL
Conditions
Guaranteed Umlts
Typ
VIH
Units
Maximum Low Level
Output Voltage
liN
Maximum Input
Leakage Current
loz
Maximum TRI-STATE
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on Input allSOCiated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
4·34S
lOUT
= - 50 JAA
'VIN
= VILorVIH
10H
-4mA
-SmA
-SmA
lOUT
= 50p.A
'VIN
= VIL or VIH
10L
VI
4mA
SmA
SmA
= VeeGND
VI(OE) = VIL, VIH
VI = Vee,GND
Vo = Vee,GND
DC Characteristics for' AC Family Device (Continued)
Symbol
Parameter
Vee
(V)
74AC
54AC
74AC
TA = 25°C
TA = -55°C
to + 125°C
TA = -40°
to + 85°C
Typ
IOLD
IOHD
Icc
tMinimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
5.5
32
32
mA
VOLD = 1.65V Max
5.5
-32
-32
mA
VOHD = 3.B5V Min
160
BO
p.A
VIN = VCC
orGND
150
mA
5.5
B.O
Supply Current
5.5
125
150
20 MHz Loaded
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 20 ms. one output loaded at a time.
Nole: liN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vcc.
Icc for 54AC @ 25'C is identical to 74AC @ 25·C.
Nole 2: Test load 50 pF. 500n to ground.
ICCD
f = 20 MHz
(Note 2)
DC Electrical Characteristics for 'ACT Family Devices
Symbol
Parameter
Vee
(V)
54ACT
54ACT
74ACT
TA = 25°C
TA = -55"C
to + 125°C
TA = -400
to +85°C
Typ
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
O.S
O.B
O.B
O.B
VOH
Minimum High Level
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
3.S6
4.B6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.32
0.32
0.40
0.40
0.37
0.37
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
Conditions
V
VOUT = 0.1V
orVcc -O.W
VOUT = 0.1V
orVCC -O.W
V
lOUT = -50 p.A
'VIN = VIL or VIH
-SmA
IOH
-BmA
lOUT = 50 p.A
'VIN = VIL or VIH
BmA
IOL
SmA
liN
Maximum Input
5.5
±0.1
+1.0
±1.0
p.A
VI = Vcc,GND
loz
Maximum
TRI-STATE Current
5.5
±0.5
±10.0
±5.0
p.A
VI = VIL, VIH
Va = Vcc,GND
ICCT
Maximum Icc/Input
5.5
1.0
1.6
1.5
mA
VI = Vcc -2.W
IOLD
tMaximum Dynamic
5.5
32
32
mA
VOLD = 1.65V
IOHD
Output Current
5.5
-32
-32
mA
VOHD = 3.B5V
Icc
Maximum Quiescent
Supply Current
5.5
160
BO
p.A
VIN = Vcc
orGND
150
mA
0.6
S.O
Supply Current
5.5
125
150
20 MHz Loaded
•All oulputs loaded; thresholds on input associated with output under test
tMaxlmum test duration 2.0 ms. one output loaded at a time.
Noles: Icc limit for 54ACT @ 25'C is identical to 74ACT @ 25·C.
When I!Fi is low with SO High. Icc > 1.5 mAo
Nole 2: Teslload 50 pF. 500n to ground.
ICCD
4-349
f = 20 MHz
(Note 2)
AC Characteristics:
Symbol
See Section 2 for waveforms
Parameter
'Vee
(V)
74AC
54AC
74AC
TA = +25"C
CL = 50pF
TA = -55"C
to + 125'C
CL = 50pF
TA = -40'C
to +S5"C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpLH
Propagation Delay, tlR
SltolR
3.3
5.0
2.5
1.5
8.5
5.5
16.5
11.5
1.0
1.5
20.0
15.0
2.0
1.0
18.5
12.5
ns
1
tpHL
Propagation Delay, tlR
SltolR
3.3
5.0
2.5
1.5
7.0
5.0
14.0
10.0
1.0
1.5
20.0
15.0
2.0
1,0
16.0
11.0
ns
1
Propagation Delay, tlHF
3.3
5.0
4.5
3.0
12.0
8.0
23.5
15.5
1.0
1.5
30.0
20.0
4.5
3.0
27.0
18.0
ns
1
3.3
5.0
5.0
3.5
11.5
8.0
22.0
15.0
1.0
2.0
28.0
20.0
5.0
3.5
25.0
17.0
ns
1
51 to Not Empty
3.3
5.0
4.5
3.0
11.5
8.0
23.5
15.5
1.0
1.5
29.0
20.0
4.5
3.0
26.5
17.5
ns
1
tpLH
Propagation Delay, tlOR
SltoOR
3.3
5.0
4.5
3.0
13.5
9.0
30.5
20.0
1.0
1.5
39.0
26.0
4.5
3.0
34.5
23.0
ns
1
tpLH
Propagation Delay tMRIRH
MRtolR
3.3
5.0
3.5
2.5
10.5
7.5
21.5
14.5
1.0
1.5
26.0
18.0
3.5
2.0
23.5
16.0
ns
2
tpHL
Propagation Delay, tMRORL
MRtoOR
3.3
5.0
7.5
6.0
18.5
12.0
35.5
23.0
1.0
3.0
45.0
31.0
7.5
6.0
41.0
26.5
ns
2
tpHL
Propagation Delay tMRO
MR to Full Flag
3.3
5.0
4.0
2.5
9.0
6.5
18.0
12.5
1.0
1.5
24.0
17.0
4.9
2.0
21.5
15.0
ns
2
tpHL
Propagation Delay tMRE
MRtoHFFlag
3.3
5.0
8.5
7.0
20.0
13.5
39.5
26.0
1.0
4.0
49.0
33.0
8.5
~.5
44.5
29.5
ns
2
tpHL
Propagation Delay, tMRONL
MR to On, LOW
3.3
5.0
3.5
2.0
9.5
7.0
19.5
14.0
1.0
1.5
25.0
18.0
3.5
2.0
21.5
15.5
ns
2
tw
IR Pulse Width, tiP
3.3
5.0
17.0
15.0·
37.5
22.0
69.0
40.5
87.0
53.0
17.0
14.5
79.5
48.0
ns
3
tw
HF Pulse Width tSF
3.3
5.0
18.0
16.0
40.0
23.0
71.5
42.0
92.0
56.0
18.0
15.5
84.0
50.5
ns
3
tpLH
Propagation Delay, to
SO to Data Out
3.3
5.0
7.0
5.5
20.5
13.5
41.5
26.0
1.0
3.5
55.0
37.0
7.0
5.0
47.5
31.0
ns
3,4
tpHL
Propagation Delay, to
SO to Data Out
3.3
5.0
7.0
5.5
22.5
14.5
43.5
28.0
1.0
3.5
55.0
37.0
7.0
5.5
50.5
32.5
ns
3,4
tpHL
Propagation Delay, tOHF
SO to < HF
3.3
5.0
4.0
2.5
9.0
6.5
17.5
12.0
1.0
1.5
23.0
16.0
4.0
2.0
20.5
14.0
ns
4
tpLH
Propagation Delay, tOF
SO to Not Full
3.3
5.0
5.5
4.0
14.5
10.0
29.0
19.0
1.0
2.5
36.0
24.0
5.5
4.0
33.0
22.0
ns
3,4
tpLH, tpHL
Propagation Delay, tOR
SO to OR
3.3
5.0
3.0
2.0
8.5
5.5
17.0
12.0
1.0
1.5
22.0
18.0
3.0
1.5
19.5
13.0
ns
4
tpLH
51 to > HF
tpHL
Propagation Delay, tlF
51 to Full Condition
tpLH
Propagation Delay, tiE
'Voltage Range 3.3 is 3.3V ± 0.3V
'Voltage Range 5.0 is 5.0V ± 0.5V
4-350
AC Characteristics:
Symbol
See Section 2 for waveforms (Continued)
Parameter
'Vee
(V)
74AC
S4AC
74AC
TA = +2S'C
Cl = SOpF
TA = -SS'C
to + 12S'C
Cl = SO pF
TA = -40'C
to +8S'C
Cl = SOpF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
tpHl
Propagation Delay, tOE
SO to Empty
3.3
5.0
4.0
2.5
10.S
7.0
20.S
14.0
1.0
1.5
26.0
19.0
3.S
2.0
23.5
16.0
ns
4
tpLH
Propagation Delay, tOD5
SI to New Data Out
3.3
5.0
7.5
6.0
22.5
15.5
44.5
30.0
1.0
4.5
60.0
39.0
7.0
5.5
53.5
35.0
ns
5
tpHl
Propagation Delay, tOD5
SI to New Data Out
3.3
5.0
7.5
6.0
21.5
14.5
42.0
28.5
1.0
4.5
60.0
39.0
7.0
5.5
48.5
33.0
ns
5
tpLH
Propagation Delay, tXt
SI to HF
3.3
5.0
4.0
2.5
11.5
8.0
23.0
15.5
1.0
1.5
29.0
20.0
3.5
2.0
26.0
17.5
ns
5
tplH
Fall-Through Time, tFTO
SltoOR
3.3
5.0
4.0
3.0
15.5
10.5
30.5
20.0
1.0
2.5
39.0
26.0
4.0
2.5
34.5
23.0
ns
5
tw
OR Pulse Width, top
3.3
5.0
13.0
10.0
23.5
13.5
42.0
25.5
54.0
34.0
12.0
9.0
48.5
29.5
ns
5
tw
HF Pulse Width, t x3
3.3
5.0
15.0
12.0
27.0
16.0
49.5
30.0
63.0
40.0
14.0
11.0
57.0
34.5
ns
5
tpLH
Fall-Through Time, tFT
SO to IR
3.3
5.0
6.5
5.0
19.0
12.5
37.0
24.0
1.0
4.0
47.0
31.0
6.0
4.5
42.5
27.5
ns
5
tPZL
Output Enable
DE to On
3.3
5.0
2.5
1.5
7.0
5.0
14.0
10.0
1.0
1.5
21.0
15.0
2.0
1.0
16.0
11.0
ns
2-6
tpLZ
Output Disable
DE to On
3.3
5.0
2.0
1.0
4.5
3.5
9.0
7.0
1.0
1.5
17.0
13.0
1.5
1.0
9.5
7.5
ns
2-6
tPZH
Output Enable
DE to On
3.3
5.0
2.5
1.5
7.5
5.5
16.5
11.5
1.0
1.5
21.0
15.0
2.0
1.0
18.5
13.0
ns
2-7
tpHZ
Output Disable
DE to On
3.3
5.0
2.0
1.0
6.5
5.0
13.0
10.0
1.0
1.5
17.0
13.0
1.5
1.0
13.5
11.0
ns
2-7
fSI
MaximumSI
Clock Frequency
3.3
5.0
35.0
60.0
20.0
45.0
30.0
50.0
MHz
fSO
Maximum SO
Clock Frequency
3.3
5.0
25.0
45.0
15.0
30.0
20.0
35.0
MHz
'Voltage Range 3.3 is 3.3V ± 0.3V
'Voltage Range 5.0 is 5.0V ± 0.5V
4-351
AC Characteristics:
Symbol
See Section 2 for waveforms (Continued)
Parameter
'Vee
(V)
74ACT
S4ACT
74ACT
TA = +2S·C
CL = SOpF
TA = -S5"C
to + 12S·C
CL=SOpF
TA = -40·C
to +8S·C
CL = SOpF
Min
Min
Max
Fig.
No.
Min
Typ
Max
5.0
2.0
6.5
11.0
1.5
12.5
ns
1
Propagation Delay, tlR
SltolR
5.0
2.0
6.5
11.0
1.5
12.0
ns
1
tpLH
Propagation Delay, tlHF
Slto> HF
5.0
4.0
10.5
17.0
4.0
19.5
ns
1
tpHL
Propagation Delay, tlF
SI to Full Condition
5.0
4.5
10.5
16.5
4.5
19.5
ns
1
tpLH
Propagation Delay, til:
SI to Not Empty
5.0
4.0
10.0
15.5
4.0
17.5
ns
1
tpLH
Propagation Delay, tlOR
SltoOR
5.0
4.0
13.5
16.5
4.0
19.0
ns
1
tpLH
Propagation Delay tMRIRH
MRtolR
5.0
3.0
8.5
13.5
3.0
15.5
ns
2
tpHL
Propagation Delay, tMRORL
MRtoOR
5.0
7.0
16.5
25.5
7.0
29.0
ns
2
5.0
3.5
9.0
14.0
3.5
16.0
ns
2
tpLH
Propagation Delay, tlR
SltolR
tpHL
tpHL
Propagation Delay, tMRO
MR to Full Flag
Max
Units
tpHL
Propagation Delay, tMRE
MR to HF Flag
5.0
8.0
17.5
27.5
8.0
30.5
ns
2
tpHL
Propagation Delay, tMRONL
MR to On, LOW
5.0
3.0
9.0
15.0
3.0
17.0
ns
2
tw
IR Pulse Width, tiP
5.0
16.5
28.0
43.0
16.5
51.5
ns
3
tw
HF Pulse Width, t3F
5.0
17.5
30.0
46.5
17.5
56.0
ns
3
tpLH
Propagation Delay, to
SO to Data Out
5.0
6.5
18.5
27.0
6.5
31.0
ns
3,4
tpHL
Propagation Delay, to
SO to Data Out
5.0
6.5
18.5
29.5
6.5
34.5
ns
3,4
tpHL
Propagation Delay, toHF
SO to < HF
5.0
3.5
8.5
13.5
3.5
15.5
ns
4
tpLH
Propagation Delay, toF
SO to Not Full
5.0
5.0
12.5
19.5
5.0
22.0
ns
3,4
tpLH, tpHL
Propagation Delay, toR
SO to OR
5.0
2.5
7.0
11.5
2.5
13.5
ns
4
'Voltage Range 5.0 is 5.0V ± 0.5V
4-352
AC Characteristics:
Symbol
See Section 2 for waveforms (Continued)
Parameter
'Vee
(V)
74ACT
S4ACT
74ACT
TA = +25"C
CL = SOpF
TA = -SS'C
to + 125"C
CL = SOpF
TA = -40'C
to +85"C
CL = SOpF
Min
Min
Max
Units
Fig.
No.
Min
Typ
Max
5.0
3.5
9.5
15.5
3.0
17.5
ns
4
Propagation Delay, toos
SI to New Data Out
5.0
7.0
19.0
30.5
6.0
35.5
ns
5
tpHL
Propagation Delay, toos
SI to New Data Out
5.0
7.0
19.0
29.5
6.0
34.S
ns
5
tpLH
Propagation Delay, tXt
SltoHF
5.0
3.5
10.0
16.0
2.5
18.0
ns
5
tpLH
Fall·Through Time, tFTO
SltoOR
5.0
3.5
13.5
21.0
1.5
24.0
ns
5
tw
OR Pulse Width, toP
5.0
12.5
17.0
26.0
12.5
30.5
ns
5
tw
HF Pulse Width, tX3
5.0
14.5
20.5
30.5
14.5
36.5
ns
5
tpLH
Fall·Through Times, tFT
SO to IR
5.0
6.0
15.0
23.5
2.5
28.0
ns
5
tPZL
Output Enable
OEtoOn
5.0
2.0
6.5
11.0
1.5
12.0
ns
2·6
tpLZ
Output Disable
DE to On
5.0
1.5
5.0
8.5
1.5
9.5
ns
2·6
tpZH
Oulput Enable
DE to On
5.0
2.0
7.0
12.0
1.5
13.0
ns
2·5
tpHZ
Output Disable
DE 10 On
5.0
1.5
7.0
12.0
1.5
13.0
ns
2·5
fSI
MaximumSI
Clock Frequency
5.0
55
85
45
MHz
fso
Maximum SO
Clock Frequency
5.0
42
60
35
MHz
tpHL
Propagation Delay, toE
SO to Empty
tpLH
'Voltage Range 5.0 Is S.OV ± O.SV
4·353
Max
AC Operating Requirements
S4AC
74AC
TA = -Ssoc
to + 12SOC
TA = -40°C
to +8SOC
74AC
Symbol
Parameter
'Vee
(Vl
TA = +2SOC
CL = SOpF
Typ
CL
=
SOpF
CL
=
Units
Fig.
No.
SOpF
Guaranteed Minimum
tw(Hl
SI Pulse Width, tslH
3.3
5.0
9.0
5.5
16.5
10.5
11.0
9.0
20.5
12.5
ns
1
tw(Ll
SI Pulse Width, tslL
3.3
5.0
8.5
6.5
16.0
12.0
26.0
14.0
19.5
14.5
ns
1
ts
Setup Time, HIGH or
LOW, DntoSI
3.3
5.0
-2.0
-1.5
1.0
1.0
2.0
0.0
1.0
1.0
ns
1
tH
Hold Time, HIGH or
LOW, DntoSI
3.3
1.0
1.0
5.5
4.0
7.0
7.0
6.0
4.5
ns
1
tw
MR Pulse Width, tMRW
3.3
5.0
13.0
8.5
26.0
16.0
34.0
22.0
30.5
20.0
ns
2
tree
Recovery Time, tMRSIH
MRtoSI
3.3
5.0
4.5
3.0
8.0
6.0
11.0
8.0
9.5
7.0
ns
2
tw(H)
SO Pulse Width, tsOH
3.3
5.0
4.0
2.5
7.5
5.5
24.0
15.0
8.5
6.5
ns
4
tw(Ll
SO Pulse Width, tSOL
3.3
5.0
10.0
6.0
18.0
12.0
23.0
16.0
21.0
14.0
ns
4
74ACT
S4ACT
74ACT
TA = +2SOC
CL = SOpF
TA = -Ssoc
to + 125"C
CL = SOpF
TA = -40"C
to +8SoC
Units
Fig.
No.
Typ
Guaranteed Minimum
'Voltage Range 3.3 is 3.3V ± 0.3V
'Voltage Range 5.0 Is 5.0V ± 0.5V
AC Operating Requirements
Symbol
Parameter
'Vee
(V)
CL
=
SOpF
tw(Hl
SI Pulse Width, tSIH
5.0
3.5
6.5
7.5
ns
1
tw(Ll
SI Pulse Width, tSIL
5.0
6.0
10.0
12.0
ns
1
ts
Setup Time, HIGH or
LOW, DntoSI
5.0
1.0
3.5
4.5
ns
1
tH
Hold Time, HIGH or
LOW, DntoSI
5.0
1.5
3.5
4.5
ns
1
tw
MR Pulse Width, tMRW
5.0
13.0
20.0
24.5
ns
2
tree
Recovery Time, tMRSIH
MRtoSI
5.0
4.5
7.5
8.5
ns
2
tw(Hl
SO Pulse Width, tsOH
5.0
7.5
6.5
8.0
ns
4
tw(Ll
SO Pulse Width, tSOL
5.0
9.0
14.0
17.0
ns
4
'Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
I
I
Symbol
CIN
I
I
Parameter
Input Capacitance
I
I
Typ
Units
4.5
pF
4-354
I
I
Conditions
Vee
=
5.0V
I
I
JZI National
ADVANCE INFORMATION
~ Semiconductor
54ACT174ACT2725
512 X 9 First In, First Out Memory (FIFO)
General Description
Features
The 512 x 9 FIFO is a first-in, first-out dual port memory
capable of asynchronous, simultaneous read and write. Other important features are: expansion capability in both the
word depth and bit width, half-full flag capability in the single
device mode, empty and full warning flags, ring pOinters for
fall-through time; it is suited for high-speed applications.
•
•
•
•
•
•
•
•
•
•
•
Logic Symbol
Connection Diagram
I I I I I I I I I
First-in, first-out dual port memory
512 x 9 organization
Low power consumption
Asynchronous and simultaneous read and write
Fully expandable by word depth andlor bit width
Half-full flag capability in single device mode
Empty and full warning flags
Auto retransmit capability
Outputs source/sink 8 mA
'ACT2725 has TTL-compatible inputs
Pin and functionality compatible with IDT7201 A
Pin Assignment
for DIP, Flatpak and sOle
w0803020100TLlF/10138-3
Xiff-
1
2
3
4
5
6
7
8
00- 9
Pin Names
Do-De
Oo-Oe
W
R
Xi
XO/HF
EF
FF
RS
FLIRT
Ol- IO
°2- 11
°3- 12
°a- 13
GNO- 14
Description
Data Inputs
Data Outputs
Write Enable
Read Enable
Expansion In
Expansion Out, Half-Full Flag
Empty Flag
Full Flag
Reset
First Load/Retransmit
'-.../
281-Vcc
271-°4
261-°5
251-0&
241-1?
231-FL/Rf
221-RS
211-Ef'
20l-XOjiW
191-07
181-°&
171-°5
161-0,
15 Hi
TLlF110138-1
4-355
~National
ADVANCE INFORMATION
~ Semiconductor
54ACT17 4ACT2726
512 X 9 Bidirectional First In, First Out Memory (BIFIFO)
General Description
Features
The 512 x 9 FIFO is a first-in, first-out dual port memory
capable of asynchronous, simultaneous read and write. Other important features are: expansion capability in both the
word depth and bit width, half-full flag capability in the single
device mode, empty and full warning flags, and ring pOinters
for zero fall-through time. There are two sets of bidirectional
ports, each 9 bits wide, through which data flow can be
controlled. A direction pin (DIRI controls the direction of the
data: when the DIR is HIGH, A is the input port and B is the
output port. When the DIR is LOW, the input port is Band
output port is A. It is suited for high-speed applications.
•
•
•
•
•
•
•
•
•
•
•
Logic Symbol
Connection Diagram
Pin Assignment
for DIP, Flatpak and sOle
I I I I I I I I I
-
VI = -0.5V
VI = Vee + 0.5V
o.....
Recommended Operating
Conditions
-40"Cto +85'C
- 55'C to + 125'C
Minimum Input Edge Rate a V / at
'ACO Devices
VIN from 30% to 70% of Vee
Vee @3.0V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate aVlat
'ACTO Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125mV/ns
±300mA
Junction Temperature (TJ)
CDIP
PDIP
175'C
140'C
Nota 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design Is rellabfe over lis power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FAeTTM circuits outside databook specifications.
DC Characteristics for' ACT Family Devices
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
TA=
-55'C to + 125"C
TA=
-40'Cto +85'C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
3.86
4.86
3.70
4.70
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
I£A
Symbol
Typ
4.5
5.5
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
4.5
5.5
0.001
0.001
Units
Conditions
Guaranteed Limits
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one oulputloaded at a time.
5·5
lOUT = -50 itA
V
·VIN = VIL or VIH
-24mA
10H
-24mA
lOUT = 50 itA
·VIN = VIL or VIH
24mA
10L
24mA
VI = Vee,GND
DC Characteristics for 'ACT Family Devices (Continued)
Symbol
Vee
Parameter
(V)
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
TA=
- SS'C to +,12S'C
TA=
-40'C to + 85'C
Maximum
Icc/Input
IOLD
tMinimum Dynamic
Output Current
I'HD
5.5
Conditions
Guaranteed Umits
Typ
ieCT
Units
0.6
1.5
1.6
mA
V, = Vee - 2.1V
5.5
50
75
mA
5.5
-50
-75
mA
VOHD = 3.85V Min
p.A
V,N = Vee
or GND (Note 1)
Icc
Maximum Quiescent
Supply Curent
5.5
VOLP
Maximum High Level
Output Noise
5.0
1.1
1.5
V
VOLV
Maximum Low Level
Output Noise
5.0
-0.6
-1.2
V
V,HD
Maximum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
V,LD
tMaximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
160.0
80.0
VOLD = 1.65VMax
Figures 1,2
(Note 2, 3)
Figures 1,2
(Notes2,4)
(Notes 2, 4)
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note 1: Icc for S4ACTO @ 2S'C is identical to 74ACTO @ 2S'C.
Note 2: Worst case package.
Note 3: Max number of Date Inputs defined as (n). n - 1 Data Inputs are driven OV to SV. One Data Input @ VIN = GND.
Note 4: Max number of Data Inputs (n) switching. (n - 1) Inputs switching OV to SV ('ACTO), Input-under.test switching: SV to threshold (VILO), OV to threshold
(VIHO), I = 1 MHz.
AC Electrical Characteristics:
Symbol
Vee·
Parameter
(V)
See Section 2 for Waveforms
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
CL = SOpF
TA = -S5'C
to + 12S'C
CL = SOpF
TA = -40'C
to +85'C
CL = SOpF
Min
Min
Max
Fig.
No.
Min
Typ
Max
5.0
3.0
7.0
11.5
2.0
13.5
ns
2-3,4
Propagation Delay
SntoZn
5.0
3.0
7.0
11.5
2.5
13.5
ns
2-3,4
tpLH
Propagation Delay
En to Zn
5.0
2.0
6.5
10.5
2.0
12.5
ns
2-3,4
tpHL
Propagation Delay
En to Zn
5.0
3.0
6.0
9.5
2.5
11.0
ns
2-3,4
tpLH
Propagation Delay
In to Zn
5.0
2.5
5.5
9.5
2.0
11.0
ns
2-3,4
tpHL
Propagation Delay
In to Zn
5.0
2.0
5.5
9.5
2.0
11.0
ns
2-3,4
tpLH
Propagation Delay
Sn to Zn
tpHL
Max
Units
'Voltege Range S.O is S.OV ±o,sv
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vce = 5.0V
CPD
Power Dissipation
Capacitance
65.0
pF
Vee = 5.0V
5-6
~National
~ Semiconductor
54ACQ/74ACQ240. 54ACTQ/74ACTQ240 Quiet Series
Octal Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The 'ACQ/'ACTQ240 is an inverting octal buffer and line
driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver
which provides improved PC board denSity. The 'ACQ/
'ACTQ utilizes NSC Quiet Series technology to guarantee
quiet output switching and improve dynamic threshold performance. FACT Quiet Series™ features GTOTM output
control and undershoot corrector in addition to a split
ground bus for superior performance.
• Guaranteed simultaneous switching noise level and
dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Improved latch-up immunity
• Inverting TRI-STATE outputs drive bus lines or buffer
memory address registers
• Outputs source/sink 24 mA
• Faster prop delays than the standard 'ACT240
• 4 kV minimum ESD immunity
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEEIIEC
Pin Assignment
for DIP, Flatpak and SOIC
20
DEI
19
10
18
0,
17
11
16
05
15
12
06
14
13
07
12
13
11
GND
Pin Assignment
for LCC and PCC
13 06 12 05 11
[IJ[l][§][[IfII
Vee
DE2
00
rn
07 [[J
0,
1IJ10
DEl
GND Ii])
I,
m
17 [j]
03 liZl
16 1@)
01
Is
O2
16
03
~Vcc
Ii]) DE2
1iJl1i]J1i]J1ilI1i]J
O2
Is 01 14 00
TUF/10234-3
17
TL/F/l0234-2
TUF/l0234-1
Truth Tables
PlnNllmes
OE1,OE2
10-17
00-0 7
Inputs
Description
OE1
TRI-STATE Output Enable Inputs
Inputs
Outputs
L
L
H
In
Outputs
(Pins 12, 14, 16, 18)
L
H
H
X
Z
L
Inputs
H=
L=
X=
Z=
5-7
OE2
In
Outputs
(Pins 3, 5, 7, 9)
L
L
L
H
H
L
H
X
Z
HIGH Vol1age Level
LOW Voltage Level
Immalerial
High Impedance
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee>
DC Input Diode Current (IIIG
VI = -O.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
DC Output Diode Current (10K)
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (Vo)
Supply Voltage (Vee)
'ACO
'ACTO
-20mA
+20mA
-O.5V to to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
±50mA
Storage Temperature (TSTG)
-65'C to + 150'C
DC Latch-Up Source or
Sink Current
Input Voltage (VI)
OVtoVee
Output Voltage (Vo)
OVtoVee
Operating Temperature (TA)
74ACQ/ACTO
54ACO/ACTO
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
2.0Vt06.0V
4.5Vt05.5V
-40'Cto +B5'C
- 55'C to + 125'C
Minimum Input Edge Rate AV / At
'ACO Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
125 mVlns
Minimum Input Edge Rate AV/At
'ACTO Devices
VIN from O.BV to 2.0V
Vee @ 4.5V, 5.5V
125 mVlns
±300mA
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Nole 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception. to ensure that the system design is reliable over its power supply.
temperature. and output/input loading variables. National does not recom·
mend operation of FACnM circuits outside databook specifications.
DC Characteristics for' ACQ Family Devices
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +25'C
TA=
-55'Cto + 125'C
TA =
- 40'C to + 85"C
Typ
VIH
VIL
VOH
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.B5
2.1
3.15
3.B5
2.1
3.15
3.B5
V
VOUT = 0.1V
orVce - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.B6
4.B6
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
3.0
4.5
5.5
VOL
Unlta
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
'All outputs loaded; thresholds on input associated wHh output under test
tMaximum lest duration 2.0 ms. one outpulloaded at a time.
5-B
lOUT = -50,...A
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50 p.A
V
'VIN = VILorVIH
12mA
24mA
10L
24mA
DC Characteristics for' ACQ Family Devices
Symbol
Parameter
Vee
(V)
74ACO
S4ACO
74ACO
TA = +2S·C
TA=
-SS·C to + 12S·C
TA=
-40·Cto +8S·C
Typ
liN
Maximum Input
Leakage Current
10LD
tMinimum Dynamic
Output Current
10HD
Icc
Maximum Quiescent
Supply Current
loz
Maximum TRI·STATE
Leakage Current
(Continued)
5.5
Units
Conditions
Guaranteed Limits
±0.1
±1.0
±1.0
poA
VI = Vcc,GND
(Note 1)
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
5.5
B.O
160.0
BO.O
poA
VIN =.Vcc
orGND (Note 1)
5.5
±0.5
±10.0
±5.0
poA
VI (OE) = VIL, VIH
VI = Vcc,GND
Vo = Vcc,GND
VOLP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Figures 1,2
(Notes 2, 3)
VOLV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1,2
(Notes2,3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
(Notes 2, 4)
Maximum Low Level
(Notes 2, 4)
5.0
1.9
1.5
V
Dynamic Input Voltage
'All outputs loaded; thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
Note 1: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vcc.
Icc for 54ACQ @ 25'C is identical to 74ACQ @ 25'C.
Note 2: Worst case package.
Note 3: Max number of outputs defined as (n). Data Inputs are driven OV to 5V. One output @ GND.
Note 4: Max number of data inputs (n) switching. (n -1) inputs switching OV to 5V ('ACQ). Input·under·test switching: 5V to threshold (Vile), ov to threshold (VIHO),
f = 1 MHz.
VILD
DC Characteristics for' ACTQ Family Devices
74ACTO
S4ACTO
74ACTO
TA = +2S·C
TA=
-SS·C to + 12S·C
TA =
-40·Cto +8S·C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
orVcc - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
O.B
0.8
V
VOUT = O.W
orVcc - O.W
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
10H
0.1
0.1
0.1
0.1
0.1
0.1
V
1c:i~T = 50 poA
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
10L
5.5
±0.1
±1.0
±1.0
poA
Symbol
Typ
4.5
5.5
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
4.5
5.5
0.001
0.001
Units
Conditions
Guaranteed Limits
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
5·9
lOUT = -50 poA
'VIN = VIL or VIH
-24mA
-24mA
'VIN = VIL or VIH
24mA
24mA
VI = Vcc,GND
DC Characteristics for' ACTQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACTQ
S4ACTQ
74ACTQ
TA = +25"C
TA=
-S5"C to + 12SoC
TA=
- 40"C to + 8SoC
Typ
loz
Maximum TRI·STATE
Leakage Current
5.5
ICCT
Maximum
Icc/Input
5.5
10LD
tMinimum Dynamic
Output Current
10HD
Units
Conditions
Guaranteed Limits
±0.5
0.6
VI = VIL, VIH
Vo = Vcc,GND
±10.0
±5.0
/LA
1.6
1.5
mA
VI = Vee - 2.1V
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vee
or GND (Note 1)
ICC
Maximum Quiescent
Supply Current
5.5
VOLP
Maximum High Level
Output Noise
5.0
1.1
1.5
V
Figures 1,2
(Note 2, 3)
VOLV
Maximum Low Level
Output Noise
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
(Notes 2,4)
(Notes 2, 4)
'All outputs loaded; thresholds on Input associated with output undar test
tMaximum test duration 2.0 ms, one output loaded at a time.
Note 1: Icc lor 54ACTO @ 2S'C is identical to 74ACTO @ 2S·C.
Note 2: Worst case package.
Nole 3: Max number 01 Data Inpuls defined as (n). n-1 Data Inputs are driven OV to 3V. One Data Inpul @ VIN = GND.
Nole 4: Max number 01 Data Inputs (n) switching. (n-l) Inputs switching OV to 3V ('ACTO). Input·under·test switching: 3V to threshold (VILD), OV to threshold
(VIHO), I = 1 MHz.
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74ACQ
S4ACQ
74ACQ
TA = +2SoC
CL=SOpF
TA = -S5"C
to + 12SoC
CL = SOpF
TA = -40"C
to +8SoC
CL = SOpF
Min
Max
Units
Fig.
No.
Min
Typ
Max
Min
Max
tpHL, tpLH
Propagation Delay
Data to Output
3.3
5.0
2.0
1.5
7.0
5.0
10.0
6.5
2.0
1.5
10.5
7.0
ns
2-3,4
tpZL,tpZH
Output Enable Time
3.3
5.0
2.5
1.5
8.0
5.5
12.0
8.0
2.5
1.5
12.5
8.5
ns
2-5,6
tpHZ, tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
8.5
6.0
13.5
9.0
1.0
1.0
'14.0
9.5
ns
2-5,6
tOSHL,
IoSLH
Output to Output
Skew"
Data to Output
3.3
5.0
1.0
0.5
1.5
1.0
1.5
1.0
ns
'Voltage Range 5.0 Is s,ov ±O.SV
Voltage Range 3.3 is 3.3 ±0.3V.
"Skew is defined as the absolute value 01 the difference between the actual propagation delay lor any two separate outputs 01 the same device. The specification
applies to any outputs switching in the same diraction, either HIGH to LOW (toSHU or LOW to HIGH (toSLH)' Parameter guaranteed by design.
5·10
AC Electrical Characteristics:
Vcc·
(V)
Parameter
Symbol
See Section 2 for Waveforms
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
CL = SOpF
TA = -S5'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
5.0
1.5
5.5
7.0
1.5
9.0
1.5
7.5
ns
2-3,4
Output Enable Time
5.0
1.5
6.5
8.5
1.5
11.0
1.5
9.0
ns
2-5,6
Output Disable Time
5.0
1.0
7.0
9.5
1.5
10.0
1.0
10.0
ns
2-5,6
Output to Output
Skew··
Data to Output
5.0
0.5
1.0
1.0
ns
tpHL, tpLH
Propagation Delay
Data to Output
tpZL, tPZH
tpHZ, tpLZ
tOSHL,
tOSLH
'Voltage Range 5.0 is S.OV ± O.SV
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (toSHU or LOW to HIGH (tosLH)' Parameter guaranteed by design.
Capacitance
Parameter
Typ
Units
CIN
Symbol
Input Capacitance
4.5
pF
Vee
= 5.0V
CPD
Power Dissipation
Capacitance
70
pF
Vee
= 5.0V
5-11
Conditions
'P"
'1:1'
N
o
~National
Semiconductor
54ACQ/74ACQ241 • 54ACTQ/74ACTQ241
Quiet Series Octal Buffer/Line Driver
with TRI-STATE® Outputs
General Description
Features
The 'ACOI'ACT0241 is an octal buffer and line driver designed to be employed as a memory address driver, clock
driver and bus oriented transmitter or receiver which provides improved PC board density. The ACO/ ACTO utilizes
NSC Ouiet Series technology to guarantee quiet output
switching and improved dynamic threshold performance.
FACT Ouiet Series™ features GTOTM output control and
undershoot corrector in addition to a split ground bus for
superior performance.
• Guaranteed simultaneous switching noise level and
dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Improved latch-up immunity
• TRI-STATEI!> outputs drive bus lines or buffer memory
address registers
• Outputs source/sink 24 mA
• Faster prop delays than the standard 'ACI'ACT241
• 4 kV minimum ESO immunity ('ACTO)
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEIIEC
OE,
EN
Pin Assignment
for DIP, Flatpak and SOIC
Pin Assignment
for LCC and PCC
.Y
oomoornm
,
-
OE,
10-
I>
',-
0"""4
r-°2
r03
'3 -
oEz
Io~
v rOo
~O,
~-
2
I,~
~
~~
~~
~~
9
0.,70 ~~
05-;-
12~
EN
06 8
13
'4'5-
Ia~-
I>
V~04
r-°s
rO,
r-o.,
GND-
13 06 '2 05 I,
20
fs""~
OE
~~lEoo"
2
18
00
17
16 I"
°1
15
15
14
°z
13
16
12
03
11
mlo
GNDIiQ)
~1Ill
03iUJ
'6~
mOEI
~Vcc
1iID00z
1iJI1IID1iID1iil1iID
0z 15 0, I" 00
TL/FI10642-3
17
TL/F/l0642-2
TLlFI10642-1
Truth Tables
Pin Names
OE1,C5E2
10-17
00-0 7
Description
Inputs
TRI-STATE Output Enable Inputs
Inputs
Outputs
OE1
In
L
L
H
H
X
Outputs
(Pins 12, 14, 16, 18)
L
L
H
Z
Inputs
In
L
L
H
L
H
L
H
X
Z
H = HIGH Vol1age Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
5-12
Outputs
(Pins 3, 5, 7, 9)
OE2
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
'ACO
'ACTO
-0.5Vto +7.0V
Supply Voltage (Vcc)
DC Input Diode Current (Iud
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
±50mA
Storage Temperature (TSTG)
-65'C to + 150'C
DC Latch-Up Source or
Sink Current
Input Voltage (VI)
OV to Vee
Output Voltage (Va)
OV to Vee
Operating Temperature (TA)
74ACO/ACTO
54ACO/ACTO
-0.5VtoVee + 0.5V
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
2.0Vt06.OV
4.5Vt05.5V
-40'Cto +85'C
- 55'C to + 125'C
Minimum Input Edge Rate tN/At
'ACO Devices
VIN from 30% to 70% of Vcc
Vee @ 3.0V, 4.5V, 5.5V
125 mVins
Minimum Input Edge Rate AV/At
'ACTO Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
±300 mA
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACT circuits outside databook specHications.
DC Electrical Characteristics for' ACQ Family Devices
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +25'C
TA=
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
VIH
VIL
VOH
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
liN
5.5
±0.1
±1.0
±1.0
/LA
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
VOL
Units
• Ali outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
5-13
VOUT = 0.1V
or Vee - 0.1V
Your =
0.1V
or Vee - 0.1V
lOUT = - 50 /LA
V
'ViN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50/LA
V
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
(Note 1)
DC Electrical Characteristics for' ACa Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACQ
S4ACQ
74ACQ
TA = +2So C
TA=
-55°C to + 125°C
TA=
-40"Cto +8SoC
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.85V Min
VIN = Vee
or GND (Note 1)
ICC
Maximum Quiescent
Supply Current
5.5
8.0
160.0
80.0
p.A
loz
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
p.A
VOLP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Figures 1,2
(Notes2,3)
VOLV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
(Notes 2, 4)
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.9
1.5
V
(Notes 2,4)
VI(OE) = VIL, VIH
VI = Vcc,GND
Vo = Vee,GND
'All outputs loaded; thrasholds on input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
Note 1: liN and Icc @ 3.0V ara guaranteed to be less than or equal to the respective limit @ S.SV Vcr;. ICC for 54ACQ @ 2S'C Is Identical to 74ACQ @ 2S'C.
Note 2: Worst case package.
Note 3: Max number of outputs defined as (n). Data Inputs are driven OV to SV. One output @ GND.
Note 4: Max number 01 Data Inputs (n) switching. n-1 Inputs switching OV to SV ('ACQ). Input·under·test switching: SV to threshold (VILO), OV to thrashold (VIHO), 1
~
1 MHz.
DC Electrical Characteristics for' ACTa Family Devices
Symbol
Parameter
Vee
(V)
74ACTQ
S4ACTQ
74ACTQ
TA = +2SoC
TA=
-55°C to + 125"C
TA =
-40"Cto +85"C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
O.B
0.8
0.8
0.8
0.8
V
VOUT = O.W
or Vee - O.W
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.B6
3.70
4.70
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
0.36
0.36
0.50
0.50
0.44
0.44
V
±1.0
±1.0
p.A
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
4.5
5.5
0.001
0.001
Maximum Input
5.5
±0.1
Leakage Current
'All outputs loaded; thresholds on input essociated with output under test
tMaxlmum test duration 2.0 ms, one output loaded at a time.
liN
5-14
V
V
lOUT = - 50 p.A
'VIN = VILorVIH
-24mA
IOH
-24mA
lOUT = 50 p.A
'VIN = VIL or VIH
24mA
IOL
24mA
VI = Vee,GND
DC Electrical Characteristics for' ACTQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
. 74ACTQ
54ACTQ
74ACTQ
TA = +25'C
TA =
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Conditions
Guaranteed Limits
loz
Maximum TAl-STATE
Leakage Current
5.5
ICCT
Maximum Icc/Input
5.5
IOLD
tMinimum Dynamic
Output Current
5.5
5.5
160.0
IOHD
Units
±O.5
0.6
±10.0
±5.0
/LA
VI = VIL, VIH
Vo = Vcc,GND
1.6
1.5
rnA
VI = Vee - 2.1V
50
75
rnA
VOLD = 1.65V Max
-50
-75
rnA
VOHD = 3.85V Min
80.0
/LA
VIN = Vcc
orGND(Notel)
ICC
Maximum Quiescent
Supply Current
5.5
VOLP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Figures 1,2
(Notes 2, 3)
VOLV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
(Notes 2, 4)
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
(Notes 2, 4)
8.0
•All outputs loaded; thresholds on input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
Note 1: ICC for S4ACTO @ 2S'C is identical to 74ACTO @ 2S'C.
Note 2: Worst case DIP package.
Note 3: Max number of outputs defined as (n). Data Inputs are driven OV to 3V. One output @ GND.
Note 4: Max number of Data Inputs (n) switching. n-l Inputs SWitching OVto 3V ('ACTO).lnput·under-testswitching: 3V to threshold (VILO), OV to threshold (VIHO),
f ~ 1 MHz.
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee'
(V)
74ACQ
54ACQ
74ACQ
TA = +25'C
CL=50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Max
Units
Fig.
No.
Min
Typ
Max
Min
Max
tpHL, tpLH
Propagation Delay
Data to Output
3.3
5.0
2.0
1.5
6.5
4.5
9.0
6.0
2.0
1.5
9.5
6.5
ns
2-3,4
tpZL' tpZH
Output Enable Time
3.3
5.0
2.5
1.5
8.0
5.5
13.0
8.5
2.5
1.5
13.5
9.0
ns
2-5,6
tpHz, tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
8.5
5.5
14.5
9.5
1.0
1.0
15.0
10.0
ns
2-5,6
Output to Output
3.3
1.0
1.5
1.5
toSHL,
ns
Skew • 'Data to Output
5.0
1.0
0.5
1.0
toSLH
'Voltage Range S.O is S.OV ±O.SV.
Voltage Range 3.3 is 3.3V ±0.3V.
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specnication
applies to any outputs switching in the same direction, either HIGH to LOW (toSHU or LOW to HIGH (toSLH). Parameter guaranteed by design.
5-15
,..
"1:1'
C\I
o
AC Electrical Characteristics:
Symbol
See Section 2 for Waveforms
Vcc'
(V)
Parameter
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
CL =50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to + 85'C
CL = 50pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
5.0
1.5
5.0
6.5
1.5
8.0
1.5
7.0
ns
2-3,4
Output Enable Time
5.0
1.5
6.5
9.0
1.5
10.5
1.5
9.5
ns
2-5,6
tPHZ, tpLZ
Output Disable Time
5.0
1.0
7.0
10.0
1.5
9.5
1.0
10.5
ns
2-5,6
tOSHL,
tOSLH
Output to Output
Skew "Data to Output
5.0
0.5
1.0
1.0
ns
tpHL, tpLH
Propagation Delay
Data to Output
tpZL, tPZH
'Voltage Range 5.0 is 5.0V ± 0.5V.
··Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (!oSHU or LOW to HIGH (!oSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPD
Power Dissipation
Capacitance
70
pF
5-16
Vee = 5.0V
~National
Semiconductor
54ACQ/74ACQ244 • 54ACTQ/74ACTQ244
Quiet Series Octal Buffer/Line Driver
with TRI-STATE® Outputs
General Description
Features
The 'ACQ/'ACTQ244 is an octal buffer and line driver designed to be employed as a memory address driver, clock
driver and bus oriented transmitter or receiver which provides improved PC board density. The ACQ/ ACTQ utilizes
NSC Quiet Series technology to guarantee quiet output
switching and improved dynamic threshold performance.
FACT Quiet Series™ features GTOTM output control and
undershoot corrector in addition to a split ground bus for
superior performance.
• Guaranteed simultaneous switching noise level and dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Improved latch-up immunity
• TRI-STATEIII> outputs drive bus lines or buffer memory
address registers
• Outputs source/sink 24 mA
• Faster prop delays than the standard 'AC/'ACT244
• 4 kV minimum ESD immunity
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEIIEC
0[1
EN
lo-
t>
'3 0[2
V rOo
IS'6 -
'7-
~
13 Os '2 Os '1
lID III lID lID III
"4
°S6"
12
°S8
138
°7-
7
EN
'4-
Pin Assignment
for LCC and PCC
1
0[1 2
10"3
04
115
1--°1
1--°2
1--°3
'1 '2-
Pin Assignment
for DIP, Flatpak and SOIC
t>
V --04
-°5
-°6
- 07
GNO...!2..
~
~
~
~
.r~
.r'~
.r'~
.r'-
....::.."
20
-Vee
19 _
18
17
16
15
14
13
12
11
~~[ljrn'.
OE2
00
14
GNO [QJ
mlo
'7{i]
031111
°1
Is
III 0E1
WJYcc
[QJ0E2
Is@
°2
'6
Ii] [j]]1lID Il1JIlID
02 Is 01 14 00
03
TLlF/l023S-3
17
TL/F/l023S-2
TL/F/l023S-1
Truth Tables
Pin Names
OE1,OE2
10-17
00-0 7
Inputs
Description
TRI-STATE Output Enable Inputs
Inputs
Outputs
Outputs
(Pins 12, 14, 16, 18)
OEI
In
L
L
H
L
H
L
H
X
Z
Inputs
H~
L~
X~
Z ~
5-17
Outputs
(Pins 3, 5, 7, 9)
OE2
In
L
L
H
L
H
L
H
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
•
Recommended Operating
Conditions
Absolute Maximum Rating (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
-0.5Vto +7.0V
DC Input Diode Current (11K)
-20 rnA
VI = -0.5V
VI = Vee + 0.5V
+20 rnA
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (loKl
Vo = -0.5V
-20 rnA
Vo = Vee + 0.5V
+20 rnA
DC Output Voltage (Vo)
-0.5VtoVee + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vee or Ground Current
±50mA
per Output Pin (ICC or IGND)
-65·Cto + 150·C
Storage Temperature (TSTG)
DC Latch-Up Source or
Sink Current
±300mA
Junction Temperature (TJ)
CDIP
175·C
PDIP
140"C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design Is reliable oyer Its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACT circuits outside databook specifications.
Supply Voltage (Vee)
'ACQ
'ACTQ
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TAl
74ACQ/ACTQ
54ACQ/ACTQ
Minimum Input Edge Rate AVI At
'ACQ Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate AVI At
'ACTQ Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vto6.0V
4.5Vt05.5V
OV to Vee
OVtoVee
-40"Cto +85·C
- 55·C to + 125·C
125.mV/ns
125mV/ns
DC Electrical Characteristics for' ACQ Family Devices
Symbol
VIH
VIL
VOH
Parameter
Vee
(V)
Minimum High Level
Input Voltage
3.0
4.5
5.5
Maximum Low Level
Input Voltage
3.0
4.5
5.5
Minimum High Level
Output Voltage
3.0
4.5
5.5
74ACQ
54ACQ
74ACQ
TA = +25·C
TA =
-55"Cto + 125"C
TA=
- 40·C to + 85·C
Typ
1,5
2.25
2.75
2.1
3.15
3.85
0.9
1.35
1.65
0.9
1.35
1.65
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.9
4.4
5.4
2.. 9
4.4
5.4
2.56
3.86
4.86
2.4
3:7:
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
50
-50
75
-75
rnA
rnA
160.0
80.0
/LA
1.5
2.25
2.75
2.99
4.49
5.49
Maximum Low Level
Output Voltage
liN
Maximum Input
Leakage Current
10LD
tMinimum Dynamic
Output Current
10HD
Icc
3.0
4.5
5.5
0.002
0.001
0.001
Conditions
Guaranteed Limits
2.1
3.15
3.85
3.0
4.5
5.5
VOL
Units
5.5
5.5
Maximum Quiescent
8.0
5.5
Supply Current
'All outputs loaded thresholds on input associated with output under test.
tMaximum test duration 2.0 mo, one output loaded at a time.
5-18
V
VOUT = 0.1V
or Vee - 0.1V
V
VOUT = 0.1V
or Vee - 0.1V
lOUT = - 50 JAA
V
'VIN = VIL or VIH
-12mA
-24 rnA
10H
-24 rnA
lOUT = 50JAA
'VIN = VIL or VIH
12mA
24 rnA
10L
24 rnA
VI = Vee,GND
(Note 1)
VOLD = 1.65VMax
VOHD = 3.85V Min
VIN = Vee
or GND (Note 1)
DC Electrical Characteristics for' ACQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
loz
Maximum TRI-STATE
Leakage Current
VOLP
Quiet Output
Maximum Dynamic VOL
VOLV
Quiet Output
Minimum Dynamic VOL
Minimum High Level
Dynamic Input Voltage
VIHD
Conditions
Guaranteed Limits
±0.5
5.5
Units
±10.0
±5.0
/LA
5.0
1.1
1.5
V
5.0
-0.6
-1.2
V
5.0
3.1
3.5
V
VI(OE) = VIL, VIH
VI = Vee,GND
Va = Vee, GND
Figures 1,2
(Notes2,3)
Figures 1,2
(Notes 2,3)
(Notes 2, 4)
Maximum Low Level
(Notes 2, 4)
5.0
1.9
1.5
V
Dynamic Input Voltage
• All outputs loaded thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note 1: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
ICC lor 54ACO @ 25'C Is Identical to 74ACO @ 25'C.
Note 2: Worst case package.
Note 3: Max number 01 outputs delined as (n). Data Inputs are driven OV to 5V. One output @ GND.
Note 4: Max number 01 Data Inputs (n) switching. (n - 1) Inputs switching OV to 5V ('ACO). Input·under-test switching: 5V to threshold (VILO), OV to threshold
(VIHO), I = 1 MHz.
VILD
DC Electrical Characteristics for' ACTQ Family Devices
Symbol
Parameter
Vee
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.S
O.S
O.S
O.S
O.S
O.S
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
lOUT = -50/LA
3.S6
4.S6
3.70
4.70
3.76
4.76
V
'VIN = VIL or VIH
-24mA
10H
-24mA
0.1
0.1
0.1
0.1
0.1
0.1
V
lOUT = 50/LA
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
'VIN = Vil or VIH
24mA
IOl
24mA
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
p.A
loz
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
p.A
VI = Vll, VIH
Vo = Vee,GND
leCT
Maximum Icc/Input
5.5
1.6
1.5
mA
VI = Vee - 2.1V
10LD
tMinimum Dynamic
Output Current
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.S5V Min
160.0
SO.O
p.A
VIN = Vee
or GND (Note 1)
10HD
Icc
Maximum Quiescent
Supply Current
5.5
VOLP
Quiet Output
Maximum Dynamic VOL
5.0
0.6
S.O
1.1
1.5
Quiet Output
5.0
-0.6 -1.2
Minimum Dynamic VOL
• All outputs loaded thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
VOlV
5-19
VI = Vee,GND
V
Figures 1,2
(Notes 2, 3)
V
Figures 1,2
(Notes2,3)
•
DC Electrical Characteristics for' ACTQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
TA=
-S5"C to + 125"C
TA=
-40"C to +8S'C
Typ
Units
Conditions
Guaranteed Limits
VIHD
Minimum High Level
Dynamic Inpu1 Voltage
5.0
1.9
2.2
V
(Notes2,4)
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
(Notes2,4)
•All outputs loaded; thresholds on Input associated with output undar tesl
tMaximum test duration 2.0 ms. one output loaded at a time.
Note 1: ICC lor 54ACTQ @ 25'C Is identical to 74ACTQ @ 25'C.
Note ,2: Worst case package.
Note 3: Max number 01 outputs defined as (n). Data Inputs are driven OV to 3V. One output @ GND.
Note 4: Max number 01 Data Inputs (n) switching. (n-l) Inputs switching OV to 3V ('ACTO).lnput·under·test switching: 3V to threshold (VILO), OV to threshold
(VIHO), I = 1 MHz.
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee·
(V)
74ACQ
S4ACQ
74ACQ
TA = +25"C
CL = SOpF
TA = -SS'C
to + 125"C
CL = SOpF
TA = -40"C
to +8S'C
CL = SOpF
Min
Max
Units
Fig.
No.
Min
Typ
Max
Min
Max
tpHL, tpLH
Propagation Delay
Data to Output
3.3
5.0
2.0
1.5
7.0
5.0
9.0
6.0
2.0
1.5
9.5
6.5
ns
2-3,4
tpzlo tPZH
Output Enable Time
3.3
5.0
2.5
1.5
8.0
6.5
12.0
8.0
2.5
1.5
12.5
8.5
ns
2-5,6
tpHZ, tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
9.0
7.5
13.5
9.0
1.0
1.0
14.0
9.5
ns
2-5,6
Output to Output
3.3
1.0
1.5
1.5
toSHL,
ns
Skew" Data to Output
5.0
0.5
1.0
1.0
toSLH
'Voltage Range 5.0 Is 5.0V ±0.5V.
Voltage Range 3.3 is 3.3V ±0.3V.
"Skew Is defined as the absOlute value 01 the difference between the actual propagation delay lor any two separata outputs of the 88me device. The specification
applies to any outputs swllching In the same direction, either HIGH to LOW (tosHU or LOW to HIGH (toSLH)' Parameter guaranteed by design.
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
CL = SOpF
TA = -S5"C
to + 125"C
CL = SOpF
TA = -40"C
to +85"C
CL = SOpF
Units
Fig.
No.
Min
Typ
Max
Min
Max
Min
Max
5.0
1.5
5.5
6.5
1.5
9.0
1.5
7.0
ns
2-7
Output Enable Time
5.0
1.5
7.0
8.5
1.5
10.5
1.5
9.0
ns
2-7
Ou1put Disable Time
5.0
1.0
8.0
9.5
1.5
10.5
1.0
10.0
ns
2-3
tpHL, tpLH
Propagation Delay
Data to Ou1put
tpZL, tpZH
tpHZ, tpLZ
Ou1put to Output
tOSHL,
Skew"
5.0
0.5
1.0
1.0
ns
tOSLH
Data to Output
'Voltage Range 5.0 Is 5.0V ±0.5V.
•'Skew Is defined as the absolute value 01 the difference between the actual propagation delay for any two separate outputs 01 the ssme device. The specification
applies to any outputs swllching In the 88me direction, eRher HIGH to LOW (toSHU or LOW to HIGH (toSLH)' Parameter guaranteed by design.
5-20
Capacitance
Parameter
Typ
Units
Conditions
CIN
Symbol
Input Capacitance
4.5
pF
Vee = 5.0V
CPD
Power Dissipation
Capacitance
70
pF
Vee = 5.0V
•
5-21
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
~
N
a
~National
~ semiconductor
54ACQ/74ACQ245 • 54ACTQ/74ACTQ245
Quiet Series Octal Bidirectional Transceiver
with TRI-STATE® Inputs/Outputs
General Description
Features
The 'ACQ/'ACTQ245 contains eight non-inverting bidirectional buffers with TRI-STATE outputs and is intended for
bus-oriented applications. Current sinking capability is
24 mA at both the A and B ports. The Transmit/Receive
(T /R) input determines the direction of data flow through
the bidirectional transceiver. Transmit (active-HIGH) enables data from A ports to B ports; Receive (active-LOW)
enables data from B ports to A ports. The Output Enable
input, when HIGH, disables both A and B ports by placing
them in a HIGH Z condition.
The 'ACQ/'ACTQ utilizes NSC Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
• Guaranteed simultaneous switching noise level and dynamic threshold performance
III Guaranteed pin-to-pin skew AC performance
• Improved latch-up immunity
II TRI-STATE outputs drive bus lines or buffer memory
address registers
II Outputs source/sink 24 mA
III Faster prop delays than the standard 'ACT245
c 4 kV minimum ESD immunity (,ACQ)
Ordering Code:
See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
DE
T/ii
TIR
20 Vee
19 DE
18 8
17 80
'6 8'
15 82
14 83
13 84
12 85
11 S
87
Ao
80
AI
8,
A3
Description
A2
82
A4
A3
83
As
Output Enable Input
Transmit/Receive Input
Side A TRI-STATE
Inputs orTRI-STATE
Outputs
Side B TRI-STATE
Inputs orTRI-STATE
Outputs
A4
As
84
85
As
8s
A2
TL/F/10236-1
Pin
Names
OE
T/R
Ao-A7
Bo-B7
A,
Ao
A7
B7
TL/F/l0236-3
TLlF/l0236-2
Pin Assignment
for LeC and PCC
AS As A" A3 A2
A7[[1Bm
[[IlIl[[l[[lm
Truth Table
Inputs
ONO
Outputs
OE
T/R
L
L
L
H
H
X
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
A1
mAo
IiQI
., []]
0, Ii]
lilT/R
MI
[WOE
85
~Vcc
Ii] IiIDIi]] []]Ii]]
84 93 92 Bf 90
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
TLlF110236-4
5-22
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
DC Output Diode Current (loKI
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (VO)
Supply Voltage {Vecl
'ACO
'ACTO
-0.5Vto +7.0V
Supply Voltage (Vecl
-20mA
+20mA
-0.5V to to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
±50mA
Storage Temperature (T8m)
-65'Cto +150'C
DC Latch-Up Source or
Sink Current
Input Voltage (VI)
OVtoVee
Output Voltage (VO)
OV to Vee
Operating Temperature (TA)
74ACO/ACTO
54ACO/ACTO
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
2.0Vt06.0V
4.5Vto 5.5V
-40'Cto +85'C
-55'C to + 125'C
Minimum Input Edge Rate AV/At
'ACO Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
125 mVl ns
Minimum Input Edge Rate AV/At
'ACTO Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
±300mA
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to Ule device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over ~s power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACT circuits outside databook specifications.
DC Characteristics for' ACQ Family Devices
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +2S'C
TA=
- SS·C to + 125'C
TA=
-40"Cto +85'C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Volta~e
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
,..A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
5-23
lOUT = -50,..A
'VIN = VILorVIH
-12mA
-24mA
10H
-24mA
lOUT = 50,..A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
Vj= Vee,GND
(Note 1)
•
DC Characteristics for' ACQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACQ
S4ACQ
74ACQ
TA = +25"C
TA=
-S5"C to + 125"C
TA=
- 40'C to + 85"C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
ICC
Maximum Quiescent
Supply Current
IOZT
Maximum I/O
Leakage Current
UnIts
CondlUons
Guaranteed LImIte
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.S5V MIn
5.5
S.O
160.0
SO.O
p.A
VIN = Vee
or GND (Note 1)
5.5
±0.6
±11.0
±6.0
p.A
VI(OE) = VIL, VIH
VI = Vee,GND
Vo = Vee,GND
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
VOLV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
VIHD
Maximum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.9
1.5
V
VOLP
Figures 1,2
(Notes 2, 3)
Figures 1,2
(Notes 2,3)
(Notes 2,4)
(Notes2,4)
'All outputs loaded; Ihresholds on input assoclaled with outpul under test.
tMaximum le91 durallon 2.0 ms, one outpulloBdad al a time.
Note 1: liN and Icc @ 3.0V are guaranteed 10 be lesslhen or equal 10 Ihe respeclive IImll @ 5.5V Vee. Icc for 54Aca @ 25'C is Idenllcallo 74Aca 1!1 25"C.
Nota 2: Worsl case package.
Note 3: Max number of oulputs defined as (n). Dala Inputs are driven OV 10 5V; ana outpul @ GND.
Note 4: Max number of Dala Inputs (n) swilchlng. (n -1) Inpuls switching OV 10 SV ('ACQ). Input·under·last swltching: SV to Ihreshold (VII.n>. OV to threshold (VIHO),
t = 1 MHZ.
DC Characteristics for'ACTQ Family Devices
74ACTQ
S4ACTQ
74ACTQ
TA = +2S"C
TA=
-S5"C to + 12S"C
TA=
-40'Cto +85"C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
orVcc - 0.1V
VIL
Maximum low level
Input Voltage
4.5
5.5
1.5
1.5
O.S
0.8
O.S
0.8
O.S
O.S
V
VOUT = O.W
or Vee - O.W
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.S6
4.S6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
p.A
Symbol
VOL
liN
Maximum Low level
Output Voltage
Maximum Input
Leakage Current
4.5
5.5
0.001
0.001
Conditions
Guaranteed Umlte
Typ
4.5
5.5
Unite
'All outputs loaded; Ihresholds on inpul associated wllh output under test.
tMaxlmum lesl duration 2.0 ms, one outpulloaded at a lime.
5-24
lOUT = - 50 p.A
·VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50p.A
·VIN = VIL or VIH
24mA
IOL
24mA
VI = Vee.GND
DC Characteristics for' ACTQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACTO
S4ACTO
74ACTO
TA = +2SoC
TA=
-S5"C to + 125°C
TA=
-40"Cto +8SoC
Typ
loz
Maximum TAI·STATE
Leakage Current
5.5
ICCT
Maximum
Iccllnput
5.5
IOLD
tMinimum Dynamic
Output Current
IOHD
Units
Conditions
Guaranteed Limits
to.5
0.6
t10.0
t5.0
/LA
1.6
1.5
mA
VI = VIL, VIH
Vo = Vcc,GND
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vcc
or GND (Note 1)
Icc
Maximum Quiescent
Supply Current
5.5
VOLP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Figures 1,2
(Notes 2, 3)
VOLV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
VIHD
Maximum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
(Notes 2,4)
(Notes 2. 4)
outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note t: Icc lor 54ACTQ @ 25'C is identical to 74ACTQ @ 2S'O.
Note 2: Worst case package.
Note 3: Max number 01 outputs defined as (n). n-1 Data Inputs are driven OV to 3V; one output @ GND.
Note 4: Max number 01 Data Inputs (n) swHching. (n-l) Inputs switching OV to 3V ('ACTQ). Input·under·lest switching: 3V to threshold (VILD). OV to threshold
(VIHO) I = 1 MHz.
• All
AC Electrical Characteristics:
Symbol
Parameter
Vcc'
(V)
See Section 2 for Waveforms
74ACO
54ACO
74ACO
TA = +2SoC
CL = 50pF
TA =' -55"C
to + 125"C
CL = SOpF
TA = -40"C
to +85°C
CL = SOpF
Min
Units
Fig.
No.
Min
Typ
Max
Min
Max
tpHL. tpLH
Propagation Delay
Data to Output
3.3
5.0
2.0
1.5
7.5
5.0
10.0
6.5
2.0
1.5
10.5
7.0
ns
2·3,4
tPZL. tpzH
Output Enable Time
3.3
5.0
3.0
2.0
8.5
6.0
13.0
8.5
3.0
2.0
13.5
9.0
ns
2·5.6
tpHZ. tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
8.5
7.5
14.5
9.5
1.0
1.0
15.0
10.0
ns
2·5.6
Max
Output to Output
3.3
1.0
1.5
1.5
ns
Skew··
5.0
0.5
1,0
1.0
Data to Output
'Voltage Range 5.0 1$ 5.0V ±O.SV
Voltage Range 3.3 is 3.3V ±O.3V
"Skew is defined as the absolute value 01 the difference between the actual propagation delay lor any two separale outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (toSHU or LOW to HIGH (tosLH). Parameter guaranteed by design.
tOSHL,
tOSLH
5·25
AC Electrical Characteristics:
Symbol
Parameter
Vcc'
(V)
See Section 2 for Waveforms
74ACTQ
S4ACTQ
74ACTQ
TA = +25"C
Cl = SOpF
TA = -SS'C
to + 125"C
Cl = SOpF
TA = -40'C
to +8S'C
Cl = SOpF
Min
Max
Min
Max
1.5
9.0
1.5
Units
Fig.
No.
7.5
ns
2-3,4
Min
Typ
Max
5.0
1.5
5.5
7.0
Output Enable Time
5.0
2.0
7.0
9.0
1.5
12.0
2.0
9.5
. ns
2-5,6
Output Disable Time
5.0
1.0
B.O
10.0
1.0
11.5
1.0
10.5
ns
2-5,6
tpHLo tpLH
Propagation Delay
Data to Output
tpZL, tPZH
tpHZ, tpLZ
Output to Output
Skew"
5.0
0.5
1.0
1.0
ns
Data to Output
'Vo"age Range 5.0 Is 5.0V ± 0.5V
"Skew Is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (toSHU or LOW to HIGH (tosLH)' Parameter guaranteed by design.
toSHL,
toSLH
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input CapaCitance
4.5
pF
Vee = 5.0V
CliO
Input/Output
Capacitance
15
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
80.0
pF
Vee = 5.0V
5-26
~National
~ Semiconductor
54ACQ/74ACQ273 0 54ACTQ/74ACTQ273
Quiet Series Octal D flip-fiop
General Description
The 'AC/'ACT273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
features
1:1
IJ
[J
IJ
I!l
CI
CI
Guaranteed simultaneous switching noise level and dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
Buffered common clock and asynchronous master reset
Outputs source/sink 24 mA
Faster prop delays than the standard 'AC/'ACT273
4 kV minimum ESD immunity
The 'ACQ/'ACTQ utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
The information for the ACQ273 is Advanced Information only_
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIIEC
t.lii
t.lii
1
20
Vce
00
2
19
07
00
Do
3
18
DJ
°1
°2
Dl
4
17
01
5
Cp
CP
MR
Do
Dl
D2
TL/F/l0S6S-1
D3
03
°4
°s
06
°7
D4
Ds
D6
D7
16
D6
06
02
15
05
D2
14
Ds
D,
D3
03
GND
8
13
9
12
10
11
TL/F/l0565-3
TL/F/l0S65-2
Pin Names
0,
CP
Description
Pin Assignment
forlCC
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
D31l:!~0IDl
[§] [lJ[IIIID [!]
G~~~O~~~
cpli]]
mMii
0, Jg]
D,1l1l
liE 07
~Vcc
~1iID1iID1l1I1iID
Os
5-27
05
De
D6
DJ
TLlF/l0565-4
III
a~
Mode Select-Function Table
Inputs
Operating Mode
Outputs
MR
CP
On
an
Reset (Clear)
L
X
X
L
Load '1'
H
.../
H
H
Load '0'
H
.../
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X
= Immaterial
....r =
LOW·to·HIGH Transition
Logic Diagram
cP--~~>o~~-------.4-------~-------.4-------~-------.4-------~-------,
0,
TL/F/l0585-5
Please note that this diagram Is provided only for the understanding of logic, operations and should not be used to estimate propagation delays.
5·28
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vccl
DC Input Diode Current (11K)
VI = -0.5V
-20mA
+20mA
VI = Vcc + 0.5V
DC Input Voltage (VI)
-0.5V to Vcc + 0.5V
DC Output Diode Current (10K>
-20mA
Va = -0.5V
Va = Vee + 0.5V
+20mA
DC Output Voltage (Va)
-0.5Vto Vcc + 0.5V
DC Output Source
or Sink Current (10)
±50mA
DC Vcc or Ground Current
±50mA
per Output Pin (Icc or IGNO)
-65·C to + 150·C
Storage Temperature (TSTG)
DC Latch·up Source or
Sink Current
±300mA
Junction Temperature (TJ)
CDIP
175·C
PDIP
140·C
Nate 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be me~ without
exception. to ensure that the system design Is reliable over its power supply,
temperature, and outputllnput loading variables. National does not recom·
mend operation of FACT circuits outside datsbook speCifications.
Supply Voltage (Vee>
'ACO
'ACTO
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TA)
74ACO/ACTO
54ACO/ACTO
Minimum Input Edge Rate 11V1l1t
'ACO Devices
VIN from 30% to 70% of Vcc
Vee @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate 11V1l1t
'ACTO Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vto 6.0V
4.5Vt05.5V
OVtoVee
OVtoVcc
-40·Cto +85·C
- 55·C to + 125·C
125 mV/ns
125 mV/ns
DC Characteristics for' ACTQ Family Devices
74ACTO
54ACTO
74ACTO
TA = +25·C
TA=
- 55·C to + 125"C
TA=
- 4lrC to + 85·C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.7
4.7
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
,...A
1.6
1.5
mA
Symbol
Typ
4.5
5.5
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
4.5
5.5
0.001
0.001
Units
Conditions
Guaranteed Limits
Maximum
5.5
0.6
lee/Input
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
ICCT
5·29
lOUT = -50,...A
·VIN = VIL or VIH
-24mA
10H
lOUT = 50,...A
·VIN = VIL or VIH
-24mA
10L
VI = Vee,GND
VI = Vee - 2.1V
DC Characteristics for' ACTO Family Devices (Continued)
54ACTQ
74ACTQ
TA =
-SS'C to + 12S'C
TA =
- 40'C to + 8S'C
74ACTQ
Symbol
Parameter
Vee
(V)
TA
= +25'C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Units
Conditions
Guaranteed Limits
50
75
mA
VOLD
= 1.65V Max
-50
-75
mA
VOHD
= 3.85V Min
/1- A
VIN = VCC
or GND (Note 1)
5.5
5.5
ICC
Maximum Quiescent
Supply Current
5.5
VOLP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
VIHD
Maximum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
(Notes 2, 4)
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
(Notes 2, 4)
VOLV
8.0
160.0
80.0
Figures 1, 2
(Notes 2, 3)
Figures 1,2
(Notes 2, 3)
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note 1: Icc lor 54ACTO
@
25'C is identical to 74ACTO
@
25'C.
Note 2: Worst case package.
Note 3: Max number 01 outputs delined as (n). n - 1 Data inputs are driven OV to 3V; one output @ GND.
Note 4: Max number 01 Data Inputs (n) switching. (n - 1) Inputs switching OV to 3V (,ACTO). Input·under·test switching: 3V to threshold (VILD), OV to threshold
(VIHD) I ~ 1 MHz.
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee'
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +2S'C
CL = 50 pF
TA = -55'C
to + 125'C
CL = SOpF
TA = -40'C
to + 85'C
CL = SOpF
Min
Min
Typ
5.0
125
189
Propagation Delay
Clock to Output
5.0
1.5
6.5
8.5
1.5
10.0
1.5
9.0
ns
2-3,4
Propagation Delay
MR to Output
5.0
1.5
7.0
9.0
1.5
11.0
1.5
9.5
ns
2-3,4
0.5
1.0
1.0
ns
Maximum Clock
Frequency
tpHL, tpLH
tpHL
Output to Output Skew"
tOSHL,
Data to Ouput
tOSLH
'Voltage Range 5.0 is S.OV ±0.5V.
5.0
Max
Fig.
No.
Min
f max
Max
Units
85
Max
110
MHz
*'Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (toSHU or LOW to HIGH (tOSLH)' Parameter guaranteed by design.
.,
5-30
-.,
AC Operating Requirements:
Symbol
Parameter
Vcc·
(V)
See Section 2 for Waveforms
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
DatatoCP
5.0
1.0
3.5
5.0
3.5
ns
2-7
th
Hold TIme, HIGH or LOW
DatatoCP
5.0
-0.5
1.5
2.0
1.5
ns
2-7
tw
Clock Pulse Width
HIGH or LOW
5.0
2.0
4.0
5.0
4.0
ns
2-3
tw
MR Pulse Width
HIGH or LOW
5.0
1.5
4.0
5.0
4.0
ns
2-3
5.0
0.5
3.0
3.0
ns
2-3,7
Recovery Time
MRtoCP
'Voltage Range 5.0 Is 5.0V ± 0.5V
tree
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
CPO
Power Dissipation
Capacitance
40.0
pF
5·31
Conditions
= 5.0V
Vee = 5.0V
Vee
~National
~ Semiconductor
54ACQ/74ACQ373 • 54ACTQ/74ACTQ373
Quiet Series Octal Transparent Latch
with TRI-STATE® Outputs
General Description
Features·
The 'ACQ/'ACTQ373 consists of eight latches with TRISTATE outputs for bus organized system applications. The
latches appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is low, the data satisfying the input
timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
The 'ACQ/'ACTQ373 utilizes NSC Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
• Guaranteed simultaneous switching noise level and
dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Improved latch up immunity
• Eight latches in a single package
• TRI-STATE outputs drive bus lines or buffer memory
address registers
• Outputs source/sink 24 mA
• Faster prop delays than the standard 'ACt' ACT373
• 4 kV minimum ESD immunity (' ACQ)
Ordering Code: See Section B
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIIEC
TL/F/l0237-1
OE
OE
LE
00
2
DO
3
18
I?
06
DO
00
0,
°1
O2
°2
03
03
04
05
°4
°5
06
06
I?
Vee
°7
01
4
17
°1
5
16
°6
°2
O2
03
6
15
7
14
°5
05
8
13
04
12
°4
LE
03
GNO
10
11
°7
TLIF/l0237-3
TLlF/l0237-2
Pin Names
Description
Pin Assignment
for LCC and PCC
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch Outputs
~~0201Dl
1!l1Il1!l1Al11l
~~:O~~:
mOE
LE Ii]
041111
D4 1i]1
~VCC
1iID07
iBlllElf§iliZllf§i
1ls0506Ds~
TL/F/l0237-4
5-32
Functional Description
Truth Table
The 'ACOI'ACT0373 contains eight D-type latches with
TRI-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance mode
but this does not interfere with entering new data into the
latches.
Inputs
Outputs
LE
OE
On
On
X
H
L
L
L
X
Z
L
H
L
H
X
00
H
H
L
H = HIGH Voltage Level
L = LOW Vollage Level
Z = High Impedance
X = Immaterial
00 = Previous 00 before HIGH to Low transition of Latch Enable
Logic Diagram
TLlF/l0237-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
III
5-33
Recommended Operating
Conditions
Absolute Maximum Rating (Note 1)
If Military/Aerospace specified devlcea are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee)
DC Input Diode Current (11K)
-20 rnA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (10K)
-20mA
Vo = -0.5V
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5V to to Vee + 0.5V
DC Output Source
±50mA
or Sink Current (10)
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGNO)
Storage Temperature (T8TG)
- 65°C to + 150°C
DC latchup Source
or Sink Current
±300mA
Junction Temperature (TJ)
CDIP
175°C
PDIP
1400C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception. to ensure that the system design is reliable over ns power supply.
temperature. and outputllnput loading variables. National does not recom·
mend operation of FACTTM circuits outside dalabook specifications.
Supply Voltage (Vee>
'ACO
'ACTO
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TAl
74ACO/ACTO
54ACO/ACTO
Minimum Input Edge Rate a VI at
'ACO Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate aV/at
'ACTO Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vto6.0V
4.5Vt05.5V
OV to Vee
OV to Vee
-40°C to +85°C
- 55°C to + 125°C
125 mV/ns
125 mVins
DC Characteristics for' ACQ Family Devices
Symbol
74ACQ
54ACQ
74ACQ
TA = +25°C
TA=
-55"Cto + 125"C
TA=
- 400C to + 85°C
Parameter
Vee
(V)
Minimum High level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum low level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
/LA
Typ
VIH
VIL
VOH
3.0
4.5
5.5
VOL
liN
Maximum low level
Output Voltage
Maximum Input
leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
Units
Condltlona
Guaranteed limits
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
5·34
lOUT = - 50 /LA
'VIN = VIL or VIH
-12mA
-24 rnA
10H
-24 rnA
lOUT = 50/LA
'VIN = VILorVIH
12mA
24mA
10L
24mA
VI = Vee,GND
(Note 1)
DC Characteristics for' ACQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +25°C
TA=
-55"C to + 125°C
TA=
-40"C to +85°C
Typ
10LD
10HD
tMinimum Dynamic
Output Current
Icc
Maximum Quiescent
Supply Current
10Z
Maximum TRI-STATE
Leakage Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.S5V Min
5.5
S.O
160.0
SO.O
/LA
VIN = Vee
or GND (Note 1)
5.5
±0.5
±10.0
±5.0
p.A
VI(OE) = VIL. VIH
VI = Vee.GND
Va = Vee.GND
VOlP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Figures 1,2
(Notes 2. 3)
VOLV
Quiet Output
Maximum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2. 3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.9
1.5
V
(Notes 2. 4)
(Notes 2. 4)
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note 1: liN and lee @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vee.
lee lor 54ACQ @ 25"C Is identical to 74ACQ @ 25'C.
Note 2: Worst case package.
Note 3: Max number 01 outputs delined as (n). Data inputs are driven OV to 5V. One output @ GNO.
Note 4: Max number 01 data inputs (n) switching. (n -1) inputs switching OV to 5V ('ACO). Input·under·test switching: 5V to threshold (VILe>, OV to threshold (VIHC),
1= 1 MHz.
DC Characteristics for' ACTQ Family Devices
Symbol
Parameter
Vee
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25"C
TA =
-55°C to + 125°C
TA =
- 40°C to + 85°C
Typ
Units
CondItIons
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
or Vee - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.S
O.S
O.S
O.S
O.S
O.S
V
VOUT = O.W
orVee - O.W
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.S6
4.S6
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = -50p.A
'VIN = VIL or VIH
-24mA
-24mA
10H
lOUT = 50/LA
'VIN = VIL or VIH
24mA
IOL
24mA
liN
Maximum Input Leakage
Current
5.5
±0.1
±1.0
±1.0
/LA
VI = Vee.GND
loz
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
p.A
VI = VIL. VIH
Va = Vee.GND
•All outputs loaded; thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms. one output loaded at a time.
5-35
II
DC Characteristics for' ACTQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25°C
TA=
-55°C to + 125°C
TA=
- 4lrC to + 85°C
Typ
ICCT
Maximum
leellnput
IOLD
tMinimum Dynamic
Output Current
IOHD
5.5
Units
Conditions
Guaranteed Limits
0.6
1.6
1.5
mA
VI = VCC - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
p.A
VIN = Vee
or GND (Note 1)
Icc
Maximum Quiescent
Supply Current
5.5
VOLP
Maximum High Level
Output Noise
5.0
1.1
1.5
V
Figures 1,2
(Notes 2, 3)
VOLV
Maximum Low Level
Output Noise
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
VIHD
Maximum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
(Notes 2,4)
(Notes 2,4)
•All outputs loaded; thresholds on Input associated wHh output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note 1: Icc for 54ACTO @ 25'C Is identical to 74ACTO @ 25'C.
Note 2: Worst case package.
Note 3: Max number of outputs defined as (n). Data inputs are driven OV to 3V. One output @ GND.
Note 4: Max number of data inputs (n) switching. (n-1) Inputs switching OV to 3V ('ACTO). Input·under·test switching: 3V 10 threshold (VILO), OV to threshold
(VIHO), f = 1 MHz.
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee'
(V)
74ACQ
54ACQ
74ACQ
TA = +25°C
CL = 50pF
TA = -55°C
to + 125°C
CL=50pF
TA = -41rC
to +85°C
CL = 50pF
Min
Units
Fig.
No.
Min
Typ
Max
Min
Max
tpHL, tpLH
Propagation Delay
On to On
3.3
5.0
2.5
1.5
8.0
5.5
10.5
7.0
2.5
1.5
11.0
7.5
ns
2-3,4
tpLH, tpLH
Propagation Delay
LEtoO n
3.3
5.0
2.5
2.0
8.0
6.0
12.0
8.0
2.5
2.0
12.5
8.5
ns
2-3,4
tpZL, tpZH
Output Enable Time
3.3
5.0
2.5
1.5
8.5
6.5
13.0
8.5
2.5
1.5
13.5
9.0
ns
2-5,6
tpHZ, tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
9.0
6.5
14.5
9.5
1.0
1.0
15.0
10.0
ns
2-5,6
Max
Output to Output Skew"
3.3
1.0
1.5
1.5
tOSHL,
ns
5.0
0.5
1.0
1.0
On to On
tOSLH
'Voltage Range 5.0 is 5.0V ± 0.5V.
Voltage Range 3.3 is 3.3V ± 0.3V.
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies 10 any outputs switching in the same direction, either HIGH to LOW (toSHU or LOW 10 HIGH (IosLH). Parameter guarsnteed by design.
5-36
AC Operating Requirements:
Symbol
See Section 2 for Waveforms
Vee'
Parameter
(V)
74ACQ
54ACQ
74ACQ
TA = +25"C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dnto LE
3.3
5.0
0
0
3.0
3.0
3.0
3.0
ns
2-7
th
Hold Time, HIGH or LOW
Dnto LE
3.3
5.0
0
0
1.5
1.5
1.5
1.5
ns
2-7
tw
LE Pulse Width, HIGH
3.3
5.0
2.0
2.0
4.0
4.0
4.0
4.0
ns
2-3
Units
Fig.
No.
'Voltage Range 5.0 is 5.0V ±0.5V.
Voltage Range 3.3 is 3.3V ± 0.3V.
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee'
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL=50pF
Min
Typ
Max
Min
Max
Min
Max
5.0
2.0
6.5
7.5
1.5
10.5
2.0
8.0
ns
2-3,4
Propagation Delay
LEtoOn
5.0
2.5
7.0
8.5
1.5
11.5
2.5
9.0
ns
2-3,4
tpZL, tPZH
Output Enable Time
5.0
2.0
7.0
9.0
1.5
11.0
2.0
9.5
ns
2-5,6
tPHZ, tpLZ
Output Disable Time
5.0
1.0
B.O
10.0
1.5
10.5
1.0
10.5
ns
2-5,6
tOSHL,
tOSLH
Output to Output Skew"
DntoOn
5.0
0.5
1.0
1.0
ns
tpHL, tpLH
Propagation Delay
DntoOn
tpLH, tpLH
'Voltage Range 5.0 is 5.0V ±0.5V.
Voltage Range 3.3 is 3.3V ± 0.3V.
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (!oSHU or LOW to HIGH (!oSLH). Parameter guaranteed by design.
AC Operating Requirements:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
CL = 50pF
TA = -55'C
to + 125"C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dnto LE
5.0
0
3.0
3.5
3.0
ns
2-7
th
Hold Time, HIGH or LOW
Dn to LE
5.0
0
1.5
1.5
1.5
ns
2-7
Iw
LE Pulse Width, HIGH
5.0
2.0
4.0
5.0
4.0
ns
2-3
'Voltage Range 5.0 is 5.0V ± 0.5V
'Voltage Range 3.3 is 3.3V ± 0.3V
Capacitance
Parameter
Typ
Units
Conditions
CIN
Symbol
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
44.0
pF
5-37
Vee = 5.0V
•
~National
~ Semiconductor
54ACQ/7 4ACQ37 4 • 54ACTQ/74ACTQ374
Quiet Series Octal D Flip-Flop
with TRI-STATE® Outputs
General Description
Features
The 'ACQ/'ACTQ374 is a high-speed, low-power octal 0type flip-flop featuring separate Ootype inputs for each flipflop and TRI-STATE outputs for bus-oriented applications. A
buffered Clock (CP) and Output Enable (OE) are common to
all flip-flops.
The 'ACQ/'ACTQ374 utilizes Quiet Series technology to
guarantee quiet output switching and improve dynamic'
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
• Guaranteed simultaneous switching noise level and dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Improved latch-up immunity
• Buffered positive edge-triggered clock
• TRI-STATE outputs drive bus lines or buffer memory
address registers
• Outputs source/sink 24 mA
• Faster prop delays than the standard 'AC/'ACT374
• 4 kV minimum ESO immunity
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
DE
OE
Tl/F/l023B-l
CP
DE
°0
00
01
00
00
01
°1
02
03
°2
03
0,
0,
05
°s
06
06
l7
1
20
Vee
19
°7
07
06
18
3
°1
°6
°s
05
03
0,
°7
Tl/F/l023B-2
Pin Names
00- 0 7
CP
OE
00-0 7
Tl/F/l023B-3
Pin Assignment
for LCe and pee
Description
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
TRI-STATE Outputs
03~~0101
[ID III [ID @:)[I]
11100
lIloo
03 [II
GNO [QJ
CP !TIl
mOE
o,irn
~Vee
!iID°7
0, Ml
1BlliIDliEliZlliID
Os Os
06
Os l7
Tl/F/1023B-4
5-38
Functional Description
Truth Table
The 'ACQI'ACTQ374 consists of eight edge-triggered flipflops with individual Ootype inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual 0 inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Inputs
Outputs
On
CP
OE
On
H
L
../"
../"
X
X
L
L
H
H
L
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
f
= LOW·to-HIGH Transition
Logic Diagram
TL/F/10238-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5-39
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
-0.5Vto +7.0V
DC Input Diode Current (111<>
-20mA
VI = -0.5V
VI = Vee + 0.5V
+20mA
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
-20mA
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5V to to Vee + 0.5V
DC Output Source
±50mA
or Sink Current (10)
DC Vee or Ground Current
±50mA
per Output Pin (Icc or IGND)
- 65·C to + 150·C
Storage Temperature (TSTG)
DC Latch-Up Source or Sink Current
±300mA
Junction Temperature (TJ)
175·C
CDIP
140·C
PDIP
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The dalabook specifications should be met. without
Supply Voltage (Vee)
'ACO
'ACTO
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature {TAl
74ACO/ACTO
54ACO/ACTO
Minimum Input Edge Rate tN/At
'ACO Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate AV/At
'ACTO devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.0Vt06.0V
4.5Vto5.5V
OV to Vee
OVtoVee
-40"C to + 85·C
-55·Cto + 125·C
125mVlns
125mVlns
exception, to ensure that the system design Is reliable over Its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuHs outside databook specifications.
DC Characteristics for' ACQ Family Devices
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +25"C
TA=
- 5S·C to + 12S·C
TA =
- 40·C to + 8S·C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
,...A
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under tast.
tMaximum test duration 2.0 ms, one output loaded al a time.
5-40
lOUT = -50,...A
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50,...A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
(Note 1)
DC Characteristics for' ACQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
TA = +25"C
TA=
-55"C to + 125"C
Typ
IOlD
IOHD
tMinimum Dynamic
Output Current
Icc
Maximum Quiescent
Supply Current
loz
Maximum TAl-STATE
Leakage Current
74ACQ
TA=
Units
-40"Cto +85"C
Conditions
Guaranteed Limits
5.5
50
75
mA
VOlD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
5.5
8.0
160.0
80.0
/LA
VIN = Vee
or GND (Note 1)
5.5
±0.5
±10.0
±50
/LA
VI(OE) = Vll, VIH
VI = Vee,GND
Vo = Vee, GND
VOlP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Figures 1 and 2
(Notes 2 and 3)
VOlV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1 and 2
(Notes 2 and 3)
VIHD
Maximum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
VllD
Maximum Low Level
Dynamic Input Voltage
5.0
1.9
1.5
V
(Notes 2 and 4)
(Notes 2 and 4)
• All outputs loadedj thresholds on input associated with output under test.
tMaxlmum test duration 2.0 ma, one output loaded at a time.
Note 1: liN and Icc @ 3.0V are guaranteed to be lesa than or equal to the respective limit @ S.5V Vee.
Icc lor S4ACO @ 25'C is identical to 74ACO @ 2S'C.
Note 2: Worst case package.
Note 3: Max number 01 outputs defined as (n). Data inputs are driven OV to SV. One output @ GND.
Note 4: Max number 01 data Inputs (n) switching. (n -1) Inputs switching OV to SV ('ACQ). Input·under·test switching: SV to threshold (VllO), OV to threshold (VIHO),
1= 1 MHz.
DC Characteristics for' ACTQ Family Devices
Symbol
Parameter
Vee
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25"C
TA=
-S5"C to + 125"C
TA=
- 40"C to + 8S"C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = O.W
or Vee - O.W
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
4.5
5.5
0.001
0.001
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
/LA
loz
Maximum TAl-STATE
Current
5.5
±0.5
±10.0
±5.0
/LA
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one oulput loaded at a time.
5-41
lOUT = -50/LA
'VIN = Vil or VIH
-24mA
IOH
-24mA
lOUT = 50/LA
'VIN = Vil or VIH
24mA
IOL
24mA
VI = Vee,GND
VI = Vll, VIH
Vo = Vee,GND
•
DC Characteristics for' ACTQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
TA=
- S5'C to + 125'C
TA=
-40'Cto +8S'C
Maximum
Iccllnput
IOLD
tMinimum Dynamic
Output Current
IOHO
5.5
0.6
1.6
1.5
mA
50
75
mA
YOLO = 1.65V Max
5.5
-50
-75
mA
VOHO = 3.85V Min
.160.0
80.0
p.A
VIN = Vec
or GND (Note 1)
Maximum Quiescent
Supply Current
5.5
VOLP
Quiet Output
Maximum Dynamic VOL
5.0
VOLV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
VIHO
Maximum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
VILO
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
1.1
Figures 1 and 2
V
1.5
(Notes 2 and 3)
Figures 1 and 2
(Notes 2 and 3)
(Notes 2 and 4)
(Notes 2 and 4)
•All outputs loaded; thresholds on input associated with output under test
tMaximum test duration 2.0 ms, one output loaded at a time.
Nole I: Icc lor S4ACTO @ 2S'C Is identical to 74ACTO @ 25"C.
Nole 2: Worst case package.
Nole 3: Max number 01 outputs defined as (n). Data inputs are driven OV to 3V. One output @ GND
Nole 4: Max number of data Inputs (n) switching. (n -1) inputs switching OV to 3V (,ACTO). Input·under.test switching: 3V to threshold
(VIHO), I = 1 MHz.
AC Electrical Characteristics:
Parameter
Vce'
(V)
(VILO),
OV to threshold
See Section 2 for Waveforms
74ACQ
S4ACQ
74ACQ
TA = +2SoC
CL = SOpF
TA = -SS'C
to + 125'C
CL = SOpF
TA = -40'C
to +8SoC
CL = SOpF
Min
fmax
VI = Vcc - 2.1V
5.5
Icc
Symbol
Conditions
Guaranteed Umlts
Typ
ICCT
Units
Typ
Max
Min
Max
Min
Units
Fig.
No.
Max
Maximum Clock
Frequency
3.3
5.0
75
90
tpLH. tpHL
Propagation Delay
CP to On
3.3
5.0
3.0
2.0
9.5
6.5
13.0
8.5
3.0
2.0
13.5
9.0
ns
2·3.4
tPZL. tpZH
Output Enable Time
3.3
5.0
3.0
2.0
9.5
6.5
13.0
8.5
3.0
2.0
13.5
9.0
ns
2·5.6
tpHZ. tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
9.5
8.0
14.5
9.5
1.0
1.0
15.0
10.0
ns
2·5.6
Output to Output Skew"
CP to On
3.3
5.0
1.0
0.5
1.5
1.0
1.5
1.0
ns
IosHL.
IosLH
70
85
MHz
'Voltage Range S.O is S.OV ± O.SV
Voltage Range 3.3 Is 3.3V ± 0.3V
"Skew is defined as the absolute value of the difference between the actual propagation delay lor any two separate outputs 01 the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (tosHLl or LOW to HIGH (toSLH)' Parameter guaranteed by design.
5·42
AC Operating Requirements:
See Section 2 for Waveforms
Vee'
Symbol
Parameter
ts
Setup Time, HIGH or LOW
Dn toCP
3.3
th
tw
(V)
74ACQ
S4ACQ
74ACQ
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 125"C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Typ
5.0
3.0
3.0
ns
2·7
Hold Time, HIGH or LOW
Dn toCP
3.3
5.0
0
2.0
1.5
1.5
1.5
1.5
ns
2·7
CP Pulse Width,
HIGH or LOW
3.3
5.0
2.0
2.0
4.0
4.0
4.0
4.0
ns
2·3
Units
Fig.
No.
Parameter
Vee'
(V)
See Section 2 for Waveforms
74ACTQ
54ACTQ
74ACTQ
TA = +2S'C
CL = SOpF
TA = -5S'C
to + 125"C
CL = SOpF
TA = -40'C
to +85"C
Cl = SOpF
Min
Typ
Maximum Clock
Frequency
5.0
85
Propagation Delay
CPtoO n
5.0
2.0
7.0
tpZL, tpZH
Output Enable Time
5.0
2.0
tpHZ, tpLZ
Output Disable Time
5.0
1.0
Output to Output Skew"
CP to On
5.0
tOSHL,
tOSLH
Guaranteed Minimum
3.0
3.0
Symbol
tpLH, tpHL
Fig.
No.
0
0
AC Electrical Characteristics:
f max
Units
Max
Max
Min
Min
95
Max
80
MHz
9.0
2.0
11.5
2.0
9.5
ns
2·3,4
7.5
9.0
2.0
11.5
8.0
10.0
1.5
10.5
2.0
9.5
ns
2-5,6
1.0
10.5
ns
2-5,6
0.5
1.0
1.0
ns
'Voltage Range 5.0 is 5.0V ± 0.5V
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (toSHU or LOW to HIGH (toSLH)' Parameter guaranteed by design.
AC Operating Requirements:
Vee'
See Section 2 for Waveforms
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
Cl = SOpF
TA = -SS'C
to + 12S'C
Cl = SOpF
TA = -40'C
to +8S'C
Cl = SOpF
Units
Fig.
No.
3.0
ns
2-7
2.0
1.5
ns
2-7
5.0
4.0
ns
2-3
Symbol
Parameter
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
0
3.0
3.5
th
Hold Time, HIGH or LOW
Dn toCP
5.0
0
1.5
tw
CP Pulse Width,
HIGH or LOW
5.0
2.0
4.0
(V)
Typ
Guaranteed Minimum
'Voltage Range 5.0 is 5.0V ± o.sv
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
CPD
Power Dissipation
Capacitance
42.0
pF
5-43
Conditions
Vee
Vee
=
=
5.0V
5.0V
~National
ADVANCE INFORMATION
~ Semiconductor
54ACQ/74ACQ377 • 54ACTQ/74ACTQ377
Quiet Series Octal D Flip-Flop with Clock Enable
Features
General Description
• Guaranteed simultaneous switching noise level and dyThe 'ACQ/'ACTQ377 has 8 edge-triggered D-type flip-flops
namic threshold performance
with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously,
• Guaranteed pin-to-pin skew AC performance
when the Clock Enable (eE) is low. The register is fully
• Ideal for addressable register applications
edge-triggered. The state of each D input, one set-up time
• Clock enable for address and data synchronization
before the LOW-to-HIGH clock transition, is transferred to
applications
the corresponding flip-flop's Q output. The CE input must be
• Eight edge-triggered D flip-flops
stable only one set-up time prior to the LOW-to-HIGH clock
• Buffered common clock
transition for predictable operation.
. • Outputs source/sink 24 mA
The 'ACQ/'ACTQ utilizes NSC Quiet Series technology to
• Faster prop delays than the standard 'AC/'ACT377
guarantee quiet output switching and improved dynamic
• 4 kV minimum ESD immunity
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak a!ld SOIC
IEEEIiEC
CE
CE
CP
CP
CE
TL/F/10151-1
Qo
2
19
Vee
OJ
DO
3
18
0.,
0,
4
17
Ql
5
16
08
Q8
Q2
6
15
Q5
7
14
Os
8
13
9
12
°4
10
11
DO
Qo
0,
Q,
O2
03
Q2 '
Q3
04
04
05
05
O2
03
06
06
03
0.,
07
GNO
20
04
CP
TLlF/10151-2
TLlF/10151-3
Pin Names
Do-Or
CE
QO-Q7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
Pin Assignment
forleC
~Dz020101
[!IlIl[!l[[J[!]
!IJ°o
03 [[I
GNOIiQI
lIloo
mCE
cp[i]
o,irn
~vee
0,M1
1lm°7
~Ml[§)1iZ11i§J
Ds
05 06
Os 0.,
TLlF/10151-4
5-44
~National
~ Semiconductor
54ACQ/74ACQ533 • 54ACTQ/74ACTQ533
Quiet Series Octal Transparent Latch
with TRI-STATE® Outputs
General Description
Features
The 'ACQ/'ACTQ533 consists of eight latches with TRISTATE outputs for bus organized system applications. The
flip-flops appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is low, the data satisfying the input
timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
The 'ACQ/'ACTQ533 utilizes NSC Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
• Guaranteed simultaneous switching noise level and
dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Improved latch up immunity
• Eight latches in a single package
• TRI-STATE outputs drive bus lines or buffer memory
address registers
• Outputs source/sink 24 rnA
• Inverted version of the 'ACQ/'ACTQ373
• 4 kV minimum ESD immunity
Ordering Code: See Section B
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
OE
TL/F/l0630-1
LE
°0
00
°1
Of
O2
°2
°3
D4
03
°5
Os
as
°7
07
LE
OE
00-0 7
07
as
°5
7
8
13
°s
°4
9
f2
If
°4
LE
fO
TL/F/l0630-3
Pin Assignment
forLCC
04
D:5 ~ ~ Of Of
oolIlrnrnrn
/11-_ •• •
as
03
TLlF/l0630-2
00- 0 7
Vee
°7
Os
6
°2
°2
03
03
GNO
OE
20
4
5
Of
IEEEIiEC
Pin Names
f
2
3
00
00
Of
OE
Description
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch Outputs
[II::-
GNOIiID::LEITIl::04irn::041rn ::-
moo
moo
mOE
~Vcc
Ii]] 07
1iJl1i]J1i]]1i1I1i]]
IlsOSOS06~
TL/F/l0630-4
5-45
~
~
a
r-------------------------------------------------------------------------------------,
Functional Description
Truth Table
The 'ACQ/'ACTQ533 contains eight D-type latches with
TAl-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TAl-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance mode
but this does not interfere with entering new data into the
latches.
Inputs
outputs
LE
DE
Dn
On
X
H
L
L
L
X
L
H
Z
H
.L
X
00
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
~ = Previous ~ before HIGH to Low tranaRlon of Latch Enable
Logic Diagram
TLlF/l0630-5
Please nota that this diagrem is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5-46
Absolute Maximum Rating (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage {Vecl
Supply Voltage (Vee)
'ACQ
'ACTQ
-0.5Vto +7.0V
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
-20mA
+20mA
DC Output Voltage (Vol
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (Io)
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGNO)
±50mA
-65·Cto + 150·C
Storage Temperature (T8m)
DC Latchup Source
or Sink Current
Input Voltage (VI)
OVtoVee
Output Voltage {Vol
OVtoVee
Operating Temperature (TAl
74ACQ/ACTQ
54ACQ/ACTQ
-0.5VtoVee + 0.5V
DC Output Diode Current {loKI
Vo = -0.5V
Vo = Vee + 0.5V
2.0Vt06.0V
4.5Vt05.5V
-40'Cto +85'C
-55·C to + 125·C
Minimum Input Edge Rate 11V I I1t
'ACQ Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate 11V I I1t
'ACTQ Devices
VIN from 0.8V to 2.OV
Vee @ 4.5V, 5.5V
125 mV/ns
±300 mA
Junction Temperature (TJ)
175·C
CDIP
PDIP
140·C
Nole 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside dalabook specifications.
DC Characteristics for' ACQ Family Devices
Symbol
Parameter
Vee
(V)
74ACQ
S4ACQ
74ACQ
TA = +2S·C
TA=
- SS·C to + 12S·C
TA=
-40"Cto +85"C
Typ
VIH
VIL
VOH
liN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
5.5
±0.1
±1.0
±1.0
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on Input associated wilh output under test.
tMaximum test duralion 2.0 ms, one outpulloaded at a lime.
5·47
lOUT = -50 ".A
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50 ",A
V
",A
'VIN = VIL or VIH
12mA
24mA
10L
24mA
VI = Vee,GND
(Note 1)
DC Characteristics for' ACa Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACQ
S4ACQ
74ACQ
TA = +2SoC
TA =
- SsoC to + 12SoC
TA =
-40°C to +8SoC
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
ICC
Maximum Quiescent
Supply Current
loz
Maximum TRI-STATE
Leakage Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.S5V Min
5.5
S.O
160.0
SO.O
p.A
VIN = Vee
or GND (Note 1)
5.5
±0.5
±10.0
±5.0
p.A
VI(OE) = Vll, VIH
VI = Vee,GND
Vo = Vee,GND
VOlP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Figures 1,2
(Notes 2, 3)
VOlV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.9
1.5
V
(Notes 2, 4)
(Notes 2, 4)
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note 1: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ S.SV Vee.
Icc lor S4ACQ @ 2S'C is Identical to 74ACa @ 2S'C.
Note 2: Worst case package.
Note 3: Max number 01 outputs defined as (n). Data Inputs are driven OV to SV. One output @ GNO.
Note 4: Max number of data Inputs (n) switching. (n-l) inputs switching OV to SV ('ACQ). Input·under-test switching: SV to threshold (VILO), OV to threshold (VIHO),
1= 1 MHz.
DC Characteristics for' ACTa Family Devices
74ACTQ
Symbol
Parameter
Vee
(V)
54ACTQ
TA = +2SoC
74ACTQ
TA=
TA =
Units
-5SoC to + 12SoC - 40"C to + 8SoC
Conditions
Guaranteed Limits
Typ
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.S
0.8
0.8
0.8
0.8
0.8
V
VOUT = O.W
orVee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = - 50 p.A
·VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50 p.A
·VIN = VIL or VIH
24mA
IOL
24mA
liN
Maximum Input Leakage Current
5.5
±0.1
±1.0
±1.0
p.A
VI = Vee,GND
loz
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
p.A
VI = Vll, VIH
Vo = Vee,GND
•All outputs loaded; thresholds on input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.
5-48
DC Characteristics for' ACTO Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
Typ
ICCT
Maximum
Icc/Input
IOLD
tMinimum Dynamic
Output Current
IOHD
5.5
Units
Conditions
Guaranteed Limits
0.6
1.6
1.5
mA
VI = Vcc - 2.1V
5.5
50
75
mA
VOlD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vcc
or GND (Note 1)
Icc
Maximum Quiescent
Supply Current
5.5
VOlP
Maximum High Level
Output Noise
5.0
1.1
1.5
V
Figures 1,2
(Notes2,3)
VOlV
Maximum Low Level
Output Noise
5.0
-0.6
-1.2
V
Figures 1,2
(Notes2,3)
VIHD
Maximum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
VllD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
(Notes 2, 4)
(Notes2,4)
•All outputs loaded: thresholds on Input associated with output under test.
tMaxlmum test duration 2.0 ms. one output loaded at a time.
Note 1: Icc lor 54ACTO @ 25'0 Is Identical to 74AOO @ 25'0.
Nate 2: Worst cas. package.
Nate 3: Max number 01 outputs defined as (n). Data Inputs are driven OV to 3V. One output @ GND.
Nato 4: Max number of data Inputs (n) switching. (n-l) Inputs switching OV to 3V ('ACTO). Input·under-test switching: 3V to threshold (VILO), OV to threshold
(VIHO). I = 1 MHz.
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee'
(V)
74ACQ
54ACQ
74ACQ
TA = +25'C
Cl=50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to + 85'C
CL = 50pF
Min
Units
Fig.
No.
Min
Typ
Max
Min
Max
tpHl, tplH
Propagation Delay
Onto On
3.3
5.0
2.5
1.5
8.5
5.5
11.5
7.5
2.5
1.5
12.0
8.0
ns
2-3,4
tplH, tplH
Propagation Delay
LE to On
3.3
5.0
2.5
2.0
2.5
6.0
13.0
8.5
2.5
2.0
13.5
9.0
ns
2-3,4
tpZl, tpZH
Output Enable Time
3.3
5.0
2.5
1.5
8.5
6.0
13.0
8.5
2.5
1.5
13.5
9.0
ns
2-5,6
tpHZ, tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
9.0
6.5
14.5
9.5
1.0
1.0
15.0
10.0
ns
2-5,6
tOSHl,
tOSlH
Output to Output Skew"
Onto On
3.3
5.0
1.0
0.5
1.5
1.0
1.5
1.0
ns
Max
'Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
"Skew Is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching In the same direction. either HIGH to LOW (toSHU or LOW to HIGH (toSLH)' Parameter guaranteed by design.
5-49
•
AC Operating Requirements:
See Section 2 for Waveforms
74ACQ
S4ACQ
74ACQ
TA = +25"C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +85"C
CL=SOpF
Parameter
Vee'
ts
Setup Time, HIGH or LOW
Onto LE
3.3
5.0
0
0
3.0
3.0
tH
Hold Time, HIGH or LOW
On to LE
3.3
5.0
0
0
tw
LE pulse Width, HIGH
3.3
5.0
2.0
2.0
Symbol
(V)
Units
Fig.
No.
3.0
3.0
ns
2·7
1.5
1.5
1.5
1.5
ns
2·7
4.0
4.0
4.0
4.0
ns
2·3
Units
Fig.
No.
Typ
Guaranteed Minimum
'Voltage Range 5.0 is 5.0V ±0.5V.
Voltage Range 3.3 is 3.3V ±0.3V.
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee'
(V)
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
CL = SOpF
TA = -S5"C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Min
Min
Max
Min
Typ
Max
5.0
2.0
6.0
8.0
2.0
8.5
ns
2·3,4
Propagation Delay
LE to On
5.0
2.5
7.0
9.0
2.5
9.5
ns
2·3,4
tpZL, tpZH
Output Enable Time
5.0
2.0
7.0
9.0
2.0
9.5
ns
2·5,6
tpHz, tpLZ
Output Disable Time
5.0
1.0
8.0
10.0
1.0
10.5
ns
2·5,6
IoSHL.
tOSLH
Output to Output Skew"
On to On
5.0
0.5
1.0
1.0
ns
tpHL, tpLH
Propagation Delay
On to On
tpLH, tpLH
Max
'Voltage Range 5.0 is 5.0V ±0.5V.
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specifICation
applies to any outputs switching in the same direction. either HIGH to LOW (losHU or LOW to HIGH ('osLW. Parameter guaranteed by design.
AC Operating Requirements:
Symbol
Parameter
Vee'
(V)
Se~
Section 2 for Waveforms
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
CL = 50pF
TA = -S5"C
to + 12S'C
CL=50pF
TA = -40'C
to +8S'C
CL = SOpF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
On to LE
5.0
0
3.0
3.0
ns
2·7
tH
Hold Time, HIGH or LOW
On to LE
5.0
0
1.5
1.5
ns
2·7
tw
LE Pulse Width, HIGH
5.0
2.0
4.0
4.0
ns
2·3
'Voltage Range 5.0 is 5.0V ± O.5V.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPD
Power Dissipation
Capacitance
40
pF
5·50
Vee = 5.0V
~National
~ Semiconductor
54ACQ/7 4ACQ534 e 54ACTQ/7 4ACTQ534
Quiet Series Octal 0 Flip-Flop with TRI-STATE® Outputs
General Description
Features
The 'ACQI'ACTQ534 is a high-speed, low-power octal Dtype flip-flop featuring separate D-type inputs for each flipflop and TRI-STATE outputs for bus-oriented applications. A
buffered Clock (CP) and Output Enable (OE) are common to
all flip-flops. The 'ACQ/'ACTQ534 is the same as the 'ACQ/
'ACTQ374 except that the outputs are inverted.
The 'ACQI'ACTQ534 utilizes Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
• Guaranteed simultaneous switching noise level and dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Improved latch-up immunity
• Buffered positive edge-triggered clock
• TRI-STATE outputs for bus-oriented applications
• Inverted output version of the 'ACQI'ACTQ374
• Faster prop delays than the standard 'ACT534
• 4 kV minimum ESO immunity
Ordering Code: See Section B
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
OE
CP
OE
TLlF/l0247-1
DO
00
01
01
O2
°2
03
°3
04
°4
05
°5
06
°6
07
OE
1
20
Vee
°0
2
19
DO
3
18
°7
07
01
4
17
06
°1
5
16
°6
°2
O2
15
7
14
°5
05
03
8
13
04
°3
GNO
9
12
°4
10
11
CP
°7
TLlF/l0247-3
TL/F/l0247-2
Pin Assignment
forLCC
Pin Names
Do-D7
CP
OE
'00 -'07
03 D:z 0201 01
[[]1Il[IJ[[J1J]
Description
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
ComplementaryTRI-STATE Outputs
CIJOo
[II 00
°3 [[]
GNO IlQI
CP IiJl
ITlOE
°4irn
~Vee
Ii]] 07
°4 1rn
1Hl1iID1rn1i]1rn
Ds°506 060.,
TLlF/l0247-4
5-51
•
Functional Description
The 'ACQ/'ACTQ534 consists of eight D-type flip-flops with
individual inputs and TRI-STATE complementary outputs.
The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of
their individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (CE) LOW, the contents of the eight
flip-flops are available at the outputs. When the CE is HIGH,
the outputs go to the high impedance state. Operation of
the CE input does not affect the state of the flip-flops.
Logic Diagram
CP
°7
TUF/l0247-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Function Table
Inputs
Output
CP
OE
D
0
...r
...r
L
L
L
H
H
L
L
H
X
X
'00
L
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
f
= LOW·to-HIGH Clock Transition
Z = High Impedance
~ = Value stored from previous clock cycle
5-52
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Va)
Supply Voltage (Vee)
'ACO
'ACTO
-0.5Vto +7.0V
-20mA
+20mA
-0.5V to to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (Icc or IGND)
±50mA
Storage Temperature (Tsm)
- 65'C to + 150'C
DC Latch·Up Source or
Sink Current
Input Voltage (VI)
OVtoVee
Output Voltage (Va)
OVtoVee
Operating Temperature (TA)
74ACO/ACTO
54ACO/ACTO
-0.5VtoVee + 0.5V
DC Output Source
or Sink Current (10)
2.0Vt06.0V
4.5Vt05.5V
- 40'C to + B5'C
- 55'C to + 125'C
Minimum Input Edge Rate b. V / b.t
'ACO Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate b.V/b.t
'ACTO Devices
VIN from O.BV to 2.0V
Vee @ 4.5V, 5.5V
125 mVlns
±300mA
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' ACQ Family Devices
74ACQ
Symbol
Parameter
Vee
(V)
TA
=
+25'C
Typ
VIH
VIH
VOH
liN
74ACQ
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Units
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.B5
2.1
3.15
3.B5
2.1
3.15
3.B5
V
VOUT = O.tV
or Vee - O.tV
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.tV
or Vee - O.tV
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.B6
4.B6
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
",A
3.0
4.5
5.5
VOL
54ACQ
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
•All outputs loaded; thresholds on input associated with output under tesl
tMaximum test duration 2.0 ms, one output loaded at a lime.
5·53
lOUT
=
-50 ",A
'VIN
=
VIL or VIH
-12mA
-24mA
-24mA
lOUT
=
50 ",A
'VIN
=
VILorVIH
12mA
24mA
24mA
IOH
IOL
VI = Vee,GND
(Note 1)
•
DC Characteristics for' ACQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'C to +85'C
Typ
IOLD
IOHD
tMinimum Dynamic
Output Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.B5V Min
VIN = Vcc
or GND (Note 1)
Icc
Maximum Quiescent
Supply Current
5.5
B.O
160.0
BO.O
IJ-A
loz
Maximum TRI·STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
IJ-A
VOLP
Quiet Output Maximum
Dynamic VOL
5.0
1.1
1.5
V
Figures 1,2
(Note2,3)
VOLV
Quiet Output Minimum
Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
VI(OE) = VIL, VIH
VI = Vcc,GND
Va = Vcc,GND
(Notes 2, 4)
(Notes 2, 4)
Maximum Low Level
V
1.5
5.0
1.9
Dynamic Input Voltage
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a tima.
Note 1: liN and lee @ 3.0V are guaranteed to be Ie•• than or equal to the respective limit @ 5.5V Vee. lee for 54ACQ @ 25'C Is Identical to 74ACQ @ 25'C.
Note 2: Worst case package.
Note 3: Max number of outputs defined as (n). Data Inputs are driven OV to 5V. One output @ GND.
Note 4: Max number of Data Inputs (n) Switching. (n -1) Inputs switching OV to 5V ('ACO). Input-under-test switching: 5V to threshold (VILO), OV to threshold (VIHO),
f = 1 MHz.
VILD
DC Characteristics for' ACTQ Family Devices
Symbol
Parameter
Vee
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'Cto +85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - O.lV
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
O.B
O.B
O.B
O.B
O.B
O.B
V
VOUT = 0.1V
orVcc - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.B6
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
IJ-A
loz
Maximum TRI·STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
IJ-A
ICCT
Maximum
Icc/Input
5.5
1.6
1.5
mA
0.6
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
5·54
lOUT = - 5O IJ-A
'VIN = VILorVIH
-24mA
-24mA
IOH
lOUT = 50 IJ-A
'VIN = VIL or VIH
24mA
24mA
IOL
VI = Vcc,GND
VI = VIL, VIH
Va = Vcc,GND
VI = Vcc - 2.1V
DC Characteristics for' ACTQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
TA=
-55'C to + 125'C
TA=
- 40'C to + 85'C
IOHD
tMinimum Dynamic
Output Current
Conditions
Guaranteed Limits
Typ
IOLD
Units
5.5
50
75
rnA
VOLD = 1.65V Max
5.5
-50
-75
rnA
VOHD = 3.85V Min
160.0
80.0
p.A
VIN = Vee
or GND (Note 1)
lee
Maximum Quiescent
Supply Current
5.5
VOLP
Maximum High Level
Output Noise
5.0
1.1
1.5
V
Figures 1,2
(Note 2, 3)
VOLV
Maximum Low Level
Output Noise
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
(Notes 2, 4)
(Notes 2, 4)
•All outputs loaded; thresholds on input associated with output under test
tMaximum test duration 2.0 ms, one output loaded at a time.
Note 1: Icc lor S4ACTO @ 2S'C is identical to 74ACTO @ 2S'C.
Note 2: Worst case package.
Note 3: Max number 01 Data Inputs defined as (n). n-1 Data Inputs are driven OV to 3V. One Data Input @ VIN ~ GND.
Note 4: Max number 01 Data Inputs (n) switching. (n-l) Inputs switching OV to 3V (,ACTO). Input-under-test switching: 3V to threshold (VILD), OV to threshold
(VIHD), I ~ 1 MHz.
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
Min
See Section 2 for Waveforms
74ACQ
54ACQ
74ACQ
TA = +25'C
CL = 50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Min
Min
Typ
Max
Max
Units
Fig.
No.
Max
f max
Maximum Clock
Frequency
3.3
5.0
75
90
tpHL, tpLH
Propagation Delay
CP to an
3.3
5.0
3.0
2.0
9.5
6.5
13.0
8.5
3.0
2.0
13.5
9.0
ns
2-3,4
tpZL, tPZH
Output Enable Time
3.3
5.0
3.0
2.0
9.5
6.5
13.0
8.5
3.0
2.0
13.5
9.0
ns
2-5,6
tpHZ, tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
9.5
B.O
14.5
9.5
1.0
1.0
15.0
10.0
ns
2-5,6
1.0
0.5
1.5
1.0
1.5
1.0
ns
tOSHL,
tOSLH
Output to Output
Skew" CP to an
3.3
5.0
70
85
MHz
'Voltage Range S.O Is S.OV ±O.SV, Voltage Range 3.3 is 3.3V ± 0.3V.
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs SWitching in the same direction, either HIGH to LOW (tosHU or LOW to HIGH (tosLHl. Parameter guaranteed by design.
5-55
AC Operating Requirements:
See Section 2 for Waveforms
74ACQ
54ACQ
74ACQ
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Parameter
Vee'
(V)
ts
Setup Time, HIGH or LOW
Dn toCP
3.3
5.0
1.0
1.0
3.0
3.0
th
Hold Time, HIGH or LOW
Dn toCP
3.3
5.0
0
0
tw
CP Pulse Width
HIGH or LOW
3.3
3.3
2
2
Symbol
Units
Fig.
No.
3.0
3.0
ns
2-7
1.5
1.5
1.5
1.5
ns
2-7
4.0
4.0
4.0
4.0
ns
2-3
Typ
Guaranteed Minimum
'Voltage Range 5.0 is 5.0V ±0.5V. Voltage Range 3.3 Is 3.3V ± 0.3V
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
Min
See Section 2 for Waveforms
74ACTQ
54ACTQ
74ACTQ
TA = +2S'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = SOpF
TA = -40'C
to +85'C
Cl = 50pF
Typ
fmax
Maximum Clock
Frequency
5.0
85
tpHL, tpLH
Propagation Delay
CP to an
5.0
2.0
7.0
tpZL, tpZH
Output Enable Time
5.0
2.0
tPHZ, tpLZ
Output Disable Time
5.0
1.0
tOSHL.
tOSLH
Output to Output
Skew" cp to an
5.0
Max
Max
Min
Min
Units
Fig.
No.
Max
80
MHz
9.5
ns
2-3,4
2.0
9.5
ns
2-5,6
1.0
10.5
ns
2-5,6
1.0
ns
9.0
2.0
7.0
9.0
8.0
10.0
0.5
1.0
'Voltage Range 5.0 is 5.0V ±0.5V
"Skew Is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching In the same direction. either HIGH to LOW (tosHU or LOW to HIGH (toSLH)' Parameter guaranteed by design.
AC Operating Requirements:
Symbol
Parameter
Vcc'
(V)
See Section 2 for Waveforms
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
Cl = SOpF
TA = -5S'C
to + 12S'C
Cl = SOpF
TA = -40'C
to +8S'C
Cl = SOpF
Units
Fig.
No.
Guaranteed Minimum
Typ
ts
Setup Time, HIGH or LOW
Dn toCP
5.0
1.0
3.0
3.0
ns
2-7
th
Hold Time, HIGH or LOW
Dn toCP
5.0
0
1.5
1.5
ns
2-7
tw
CP Pulse Width
HIGH or LOW
5.0
2.0
4.0
4.0
ns
2-3
'Voltage Range 5.0 Is 5.0V ±0.5V
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
Vee
= 5.0V
CPO
Power Dissipation
Capacitance
40.0
pF
Vee
= 5.0V
5-56
Conditions
~National
ADVANCE INFORMATION
~ Semiconductor
54ACQ/74ACQ543 • 54ACTQ/74ACTQ543
Quiet Series Octal Registered Transceiver with
TRI-STATE® Outputs
General Description
Features
The ACOIACT0543 is a non-inverting octal transceiver
containing two sets of Ootype registers for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either
direction of data flow.
The ACOI ACTO utilizes NSC Ouiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Ouiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
• Guaranteed simultaneous switching noise level and
dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• a-bit octal latched transceiver
• Separate controls for data flow in each direction
• Back-to-back registers for storage
• Outputs sourcelsink 24 mA
• 4 kV minimum ESO immunity
Logic Symbols
Connection Diagrams
Pin Assignment
for LCC and PCC
Pin Assignment for
DIP, SOIC and Flatpak
As As A.NC A3 -'2 AI
1
24
orBA
2
23
Ao
3
LEBA
OEAB
em
Bo
OESA
CEAB
I!iJIiiil !2:J[ID III [§J [§J
Vce
Bz
CEBA
mAo
A7 1rn
CEAB~
GND IBI
mOESA
rnrnI
NC~
!TINC
~VC{;
Ill] CESA
OEAB~
LEAB
LEBA
B.
LfABIiiI
Bs
B7
~Bo
1lID
B,
~
A7
TL/F/l0154-1
CEAS
11
14
LEAB
GND
12
13
OEAB
[ill
om
CEBA
iTBI
""
ENt
""
ENZ
B6 8s 84 NC B3 Bz B,
TL/F/l0154-3
TL/F/l0154-2
IEEEIIEC
CEAB
IlIDWI~BiIB;i1~g]ij
OE8A
•
8.
8,
B2
83
B,
85
B,
87
TLlF/l0154-4
5-57
~
~
,----------------------------------------------------------------------------,
in
a ~National
~ semiconductor
ADVANCE INFORMATION
54ACQ/74ACQ544 • 54ACTQ/74ACTQ544
Quiet Series Octal Registered Transceiver with
TRI-STATE® Outputs
General Description
Features
The ACQ/ ACTQ544 is an inverting octal transceiver containing two sets of Ootype registers for temporary storage of
data flowing in either direction. Separate Latch Enable and
Output Enable inputs are provided for each register to permit independent input and output control in either direction
of data flow. The '544 inverts data in both directions.
The ACQ/ ACTQ utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
• Guaranteed simultaneous switching noise level and
dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• B-bit inverting octal latched transceiver
• Separate controls for data flow in each direction'
• Back-to-back registers for storage
• Outputs source/sink 24 mA
• 4 kV minimum ESO immunity
• 300 mil slim POIP/SOIC
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP, sOle and Flatpak
A6 A5 A4 NC A3~ Al
OEAB
LEBA
OEBA
OEBA
AD
Al
4
21
CEAB
TL/F/l0S8S-1
IEEEIIEC
CEAB
24
Vee
2
23
CEBA
3
22
A7
CEAB
10
15
80
81
82
83
84
85
86
~
11
14
LEAB
GND
12
13
DEAB
A2
20
A3
19
A4
18
As
17
A6
16
",1
LEAB
TUF/l0S8S-2
ENI
OEAB
CEBA
",1
LEBA
EN2
OEBA
Iio+-+ V1
Al +-+
A2 +-+
A3+-+
A4+-+
A5+-+
A6+-+
A7+-+
Pin Assignment
for LCC and PCC
80
81
82
83
84
85
86
~
TUF/l0S8S-4
5-58
Ii] HID lID I!HlllIl iii
mAO
A71rn
CEAB Ii]!
rn OEBA
m LEBA
GND~
II] NC
NCIi]I
OEAB IiID
LEAB Il1I
@IVee
1m CEBA
~8o
87 1iID
~[JI1[JI(:JI{JI(J1if
1iID~~~~~~
86 8s 84 NC 83 82 81
TL/F/l0S8S-3
£)
en
en
Co)
~National
~ Semiconductor
54ACQ/74ACQ563 9 54ACTQ/74ACTQ563
Quiet Series Octal latch with TRI-STATE® Outputs
General Description
Features
The 'ACQ/'ACTQ563 is a high speed octal latch with buffered common latch Enable (lE) and buffered common Output Enable (OE) inputs. The 'ACQ/'ACTQ563 is functionally
identical to the 'ACQ/'ACTQ573, but with inverted outputs.
The ACQ/ ACTQ utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
IJ Guaranteed simultaneous switching noise level and dy-
namic threshold perforfmance
I!I Guaranteed pin-to-pin skew AC performance
I!I Improved latch-up immunity
iii Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
Outputs source/sink 24 mA
IJ Faster prop delays than standard ACT563
I:J Functionally identical to the ACQ/ ACTQ573 but with
inverted outputs
IJ 4 kV minimum ESO immunity
I:l
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
OE
LE
00
0,
Do
0,
O2
03
TLlF/10631-1
°2
03
04
04
05
Os
°5
Os
07
°7
OE
1
20
DO
2
19
Vee
00
0,
0,
3
18
O2
03
4
17
°2
5
16
03
04
05
6
15
°4
7
14
Os
8
13
°5
Os
9
12
10
11
~
GNO
°7
LE
TL/F/10631-2
TL/F/10631-3
Pin Assignment
forlCC
Pin Names
Os Os 04 ~ ~
[[]m[[]rn:Jrn
Description
Data Inputs
latch Enable Input
TRI-STATE Output Enable Input
TRI-STATE latch Outputs
IIJO,
~I]]
GNO [Q]
LE IIi)
[]] Do
mOE
~Vee
07 1il1
°6H]
1m 00
IHI~~I!ZI~
°5 °4 °3 02 01
TL/F/10631-4
5-59
Function Table
Functional Description
The 'ACQI'ACTQ563 contains eight D-type latches with
TRI-STATE complementary outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input changes.
When LE is LOW the latches store the information that was
present on the D inputs a setup time preceding the HIGH-toLOW transition of LE. The TRI-STATE buffers are controlled
by the Output Enable (OE) input. When OE is LOW, the
buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but that does not interfere with entering new data into the latches.
Inputs
Internal
Outputs
Q
0
Z
Z
Z
Z
H
L
NC
OE
LE
D
H
H
H
H
L
L
L
X
X
X
H
H
L
H
H
L
L
H
H
L
NC
H
L
NC
X
L
H
X
Function
High-Z
High-Z
High-Z
Latched
Transparent
Transparent
Latched
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
TL/F/l0631-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5-60
Absolute Maximum Rating (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee)
DC Input Diode Current (1110
VI = -0.5V
-20mA
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5VtoVee + 0.5V
DC Output Diode Current (lot<>
-20mA
Vo = -0.5V
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5VtoVee + 0.5V
DC Output Source
±50mA
or Sink Current (10)
DC Vee or Ground Current
±50mA
per Output Pin (ICC or IGNO)
-65'Cto + 150'C
Storage Temperature (TSTG)
DC Latchup Source
±300mA
or Sink Current
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Nate 1: Absolute maximum ratings are those values beyond which damage
to the davies may occur. The dalabook speciflcationa should be met, without
exception, to ensure that the system deSign is reliable over its power supply,
temperature, and outputlinput loading variables. National does not racom·
mend operation of FACTTM circuits outside databook specifications.
Supply Voltage (Ved
'ACO
'ACTO
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TA)
74ACO/ACTO
54ACO/ACTO
Minimum Input Edge Rate IN/at
'ACO Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate a V/ at
'ACTO Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
2.OVt06.0V
4.5Vt05.5V
OV to Vee
OVtoVee
- 40'C to + 85'C
- 55'C to + 125'C
125mVlns
125mVlns
DC Characteristics for' ACQ Family Devices
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +25'C
TA=
-55'C to + 125'C
TA=
-40'C to + 85'C
Typ
VIH
VIL
VOH
VOL
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
Units
•All outputs loaded; thresholds on Input associated with output under tesl
tMaximum test duration 2.0 ms, one output loaded at a time.
5-61
V
V
VOUT = 0.1V
orVee - 0.1V
VOUT = 0.1V
or Vee - 0.1V
lOUT = - 5O I-'A
V
V
·VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50I-'A
V
V
·VIN = VIL or VIH
12mA
24mA
10L
24mA
•
DC Characteristics for' ACQ Family Devices (Continued)
Symbol
,
Parameter
Vee
(V)
74ACQ
S4ACQ
74ACQ
TA = +25"C
TA=
-SS'C to + 12S'C
TA=
-40'Cto +8S'C
Typ
liN
Maximum Input
Leakage Current
IOlD
tMinimum Dynamic
Output Current
IOHD
Icc
Maximum Quiescent
Supply Current
loz
Maximum TRI-STATE
Leakage-Current
Conditions
Guaranteed Limits
±0.1
5.5
Units
±1.0
±1.0
/LA
VI = Vee,GND
(Note 2)
5.5
50
75
mA
. VOlD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
5.5
B.O
160.0
80.0
/LA
VIN = Vee
orGND (Note 1)
5.5
±0.5
±10.0
±5.0
/LA
VI(OE) = Vll, VIH
VI = Vee,GND
Vo = Vee,GND
VOlP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Agures 1,2
(Notes 2, 3)
VOlV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
VllD
Maximum Low Level
Dynamic Input Voltage
5.0
1.9
1.5
V
(Notes2,4)
(Notes 2, 4)
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note 1: liN and Icc @3.0V are guaranteed to be less than or equal to the respective limit @5.SVVcc.
IcC lor S4ACQ @2S'C is Identical to 74ACQ ilt2S'C.
Note 2: Worst case package.
Note 3: Max number of outputs defined as (n). Data Inputs are driven OV to SV. One output iIt GND.
Note 4: Maximum number 01 Data Inputs (n) switching. (n-l) Inputs switching OV to SV (,ACO). Input·under-test switching: 5V to threshold (VILD), OV to threshold
(VIHO), I = 1 MHz.
5-62
DC Characteristics for' ACTQ Family Devices
74ACTQ
Symbol
Parameter
Vee
(V)
S4ACTQ
TA = +2S'C
74ACTQ
TA =
TA=
Units
- SS'C to + 12S'C - 40'C to + 8S'C
Typ
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
Vil
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
orVcc - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
liN
Maximum Input Leakage Current 5.5
±0.1
±1.0
±1.0
/LA
VI = Vcc. GND
loz
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
/LA
VI = Vil. VIH
Vo = Vcc.GND
ICCT
Maximum Iccllnput
5.5
1.6
1.5
mA
VI = Vcc - 2.1V
IOlD
tMinimum Dynamic
Output Current
5.5
50
75
mA
VOlD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vcc
or GND (Note 1)
4.5
5.5
VOL
IOHD
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
0.6
V
lOUT = - 50 /LA
'VIN = Vil or VIH
-24mA
IOH
-24mA
lOUT = 50/LA
'VIN = Vil or VIH
24mA
IOl
24mA
Icc
Maximum Quiescent
Supply Current
5.5
VOlP
Maximum High Level
Output Noise
5.0
1.1
1.5
V
Figures 1.2
(Notes 2.3)
VOLV
Maximum Low Level
Output Noise
5.0
-0.6
-1.2
V
Figures 1.2
(Note 2. 3)
VIHD
Maximum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
(Notes 2. 4)
(Notes 2. 4)
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note 1: Icc lor S4ACTO @ 2S'C is identical to 74ACO @ 2S·C.
Note 2: Worst case package.
Note 3: Max number 01 outputs delined as (n). Data inputs are driven OV to 3V. One output @ GND.
Note 4: Max number of data Inputs (n) switching. (n-l) Inputs switching OV to 3V (. ACTO). Input-under-test switching; 3V to threshold (VILC). OV to threshold (VIHC),
1= 1 MHz_
III
5-63
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee'
(V)
74ACQ
S4ACQ
74ACQ
TA = +2S'C
CL = 50pF
TA = -S5"C
to + 12S'C
CL = SOpF
TA = -40"C
to +85"C
CL=SOpF
Min
Min
Max
Min
Typ
Max
Max
Units
Fig.
No.
tpHL, tpLH
Propagation Delay
DntoOn
3.3
5.0
2.5
1.5
8.5
5.5
11.5
7.5
2.5
1.5
12.0
8.0
ns
2·3,4
tpLH, tpHL
Propagation Delay
LE to On
3.3
5.0
2.5
2.0
8.5
6.0
13.0
8.5
2.5
2.0
13.5
9.0
ns
2·3,4
tpZL, tpZH
Output Enable Time
3.3
5.0
2.5
1.5
8.5
6.0
13.0
8.5
2.5
1.5
13.5
9.0
ns
2·5,6
tpHZ, tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
9.0
6.5
14.5
9.5
1.0
1.0
15.0
10.0
ns
2·5,6
tOSHL,
tOSLH
Output to Output Skew"
On to On
3.3
5.0
1.0
0.5
1;5
1.0
1.5
1.0
ns
'Voltage Range 5.0 is 5.0V ±0.5V
Voltage Range 3.3 is 3.3V ±0.3V
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching In the same direction. either HIGH to LOW (IosHU or LOW to HIGH (!oSLH). Parameter guaranteed by design.
AC Operating Requirements:
See Section 2 for Waveforms
74ACQ
S4ACQ
74ACQ
TA = +2S'C
CL=SOpF
TA = -SS'C
to + 12S'C
CL=SOpF
TA = -40"C
to +8S'C
CL = SOpF
Units
Fig.
No.
3.0
3.0
ns
2·7
1.5
1.5
1.5
1.5
ns
2·7
4.0
4.0
4.0
4.0
ns
2·3
Units
Fig.
No.
Parameter
Vee'
(V)
ts
Setup Time, HIGH or LOW
Dn toLE
3.3
5.0
0
0
3.0
3.0
tH
Hold Time, HIGH or LOW
Dn toLE
3.3
5.0
0
0
tw
LE Pulse Width, HIGH
3.3
5.0
2.0
2.0
Symbol
Typ
Guaranteed Minimum
'Voltage Range 5.0 Is 5.0V ±0.5V
Voltage Range 3.3V Is 3.3 ±0.3V
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee'
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25"C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +85"C
CL=SOpF
Min
Min
Max
Min
Typ
Max
5.0
2.0
6.0
8.0
2.0
8.5
ns
2·3,4
Propagation Delay
LEtoOn
5.0
2.5
7.0
9.0
2.5
9.5
ns
2·3,4
tpZL, tpZH
Output Enable Time
5.0
2.0
7.0
9.0
2.0
9.5
ns
2·5,6
tpHZ, tpHL
Output Disable Time
5.0
1.0
8.0
10.0
1.0
10.5
ns
2·5,6
toSHL,
tOSLH
Output to Output Skew"
Onto On
5.0
0.5
1.0
1.0
ns
tpHL, tpLH
Propagation Delay
Onto On
tpLH, tpHL
Max
'Voltage Range 5.0 is 5.0V ±0.5V
"Skew Is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (!oSHU or LOW to HIGH (!oSLH). Parameter guaranteed by design.
5·64
AC Operating Requirements:
Symbol
Parameter
Vcc·
(V)
See Section 2 for Waveforms
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
CL=50pF
TA = -55'C
to + 125'C
CL = 50pF
TA = -40'C
to +85'C
CL = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HiGH or LOW
Onto LE
5.0
0
3.0
3.0
ns
2·7
tH
Hold Time, HIGH or LOW
Dn toLE
5.0
0
1.5
1.5
ns
2·7
5.0
2.0
4.0
4.0
ns
2·3
LE Pulse Width, HIGH
tw
'Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation
Capacitance
42
pF
5·65
Vee = 5.0V
~National
~ Semiconductor
54ACQ/74ACQ564 • 54ACTQ/74ACTQ564
Quiet Series Octal D Flip-Flop
with TRI-STATE® Outputs
General Description
Features
The 'ACTQ564 is a high speed octal D-type flip-flop with
buffered common clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs
is stored in the flip-flops on the low-to-high clock (CP) transition. The 'ACQ/'ACTQ564 utilizes NSC Quiet Series technology to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series™ features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance.
• Guaranteed simultaneous switching noise level and dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Improved latch-up immunity
• Inputs and outputs on opposite sides of package allow
easy interface with ",P's
• Outputs source/sink 24 mA
• Faster prop delays than the standard 'ACT564
• 4 kV minimum ESD immunity
Ordering Code: See Section 8
Connection Diagrams
Logic Symbols
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
CP
OE
TL/F/l0632-1
OE
20
Vee
CP
19
°0
18
°1
Do
°0
17
0,
°2
0,
16
°2
°3
°2
15
°4
03
°3
14
Os
°4
°4
°6
Os
06
I?
06
8
13
Os
I?
~
GNO
9
10
12
°6
11
CP
°7
TL/F/l0632-3
TLiF/l0632-2
Pin Names
Do-D7
CP
DE
00-0 7
Pin Assignment
for LCC and PCC
Description
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
TRI-STATE Outputs
De Os 04 ~ ~
1!l1Il1!l[[J1II
07 [[J
GNO IlID
mOl
Cp[i]
[2Joo
mOE
071il1
Ii2IVee
06~
li]Ioo
"' ..........-.-.....r-Y
~1iID1l§I[Z)1l§I
Os 04 03 ~ 01
TLiF/l0632-4
5-66
r---------------------------------------------------------------------------------, '"
en
Functional Description
Function Table
The 'ACQI'ACTQ564 consists of eight edge-triggered flipflops with individual D-type Inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the DE input does not affect the state of the
flip-flops.
Inputs
~
Internal
outputs
OE
CP
D
0
ON
H
H
H
H
L
L
L
L
H
H
./"
./"
./"
./"
H
H
L
H
L
H
L
H
L
H
NC
NC
H
L
H
L
NC
NC
Z
Z
Z
Z
H
L
NC
NC
Function
Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
.r = LOW-to-HIGH Transition
NC = No Change
Logic Diagram
TL/F/t0632-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5-67
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Input Diode Current (Iud
VI = -0.5V
VI = Vee + 0.5V
-20mA
+20mA
DC Input Voltage (VI)
DC Output Diode Current (Ioid
Vo = -0.5V
Vo = Vee + 0.5V
DC Output Voltage (VO)
Supply Voltage (Veel
'ACO
'ACTO
-0.5Vto +7.0V
Supply Voltage (Veel
-20mA
+20mA
-0.5Vto to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (lee or IGND)
±50mA
-65·Cto +150·C
Storage Temperature (T8TG)
DC Latch-Up Source or Sink Current
Input Voltage (VI)
OVtoVee
Output Voltage (Vo),
OV to Vee
Operating Temperature (TAl
74ACO/ACTO
54ACO/ACTO
-0.5V to Vee + 0.5V
DC Output Source
or Sink Current (10)
2.0Vt06.0V
4.5Vt05.5V
-40"Cto +85·C
-55·C to + 125·C
"
Minimum Input Edge Rate AV/At
'ACO Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
125mV/ns
Minimum Input Edge Rate AV I At
'ACTO devices
VIN from 0.8V to 2.0V
Vee@4.5V,5.5V
125mVlns
±300mA
Junction Temperature (TJ)
CDIP
175·C
140·C
PDIP
Note 1: Absolute maximum ratings are thosa values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over "s power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM clreu", outside databook specifications.
;
DC Characteristics for' ACQ Family Devices
Symbol
74ACQ
54ACQ
74ACQ
TA = +25·C
TA=
-55"C to + 125·C
TA=
- 40"C to + 85·C
Parameter
Vee
(V)
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = O.IV
or Vee - O.W
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = O.W
or Vee - O.W
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3:76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
V
5.5
±0.1
±1.0
±1.0
)LA
VI = Vee,GND
(Note 1)
Typ
VIH
VIL
VOH
3.0
4.5
5.5
VOL
Maximum Low Level
Output Voltage
liN
Maximum Input
Leakage Current
10LD
tMinimum Dynamic
Output Current
10HD
3.0
4.5
5.5
0.002
0.001
0.001
Units
Conditions
Guaranteed Limits
lOUT = - 50 )LA
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50)LA
'VIN = VILorVIH
12mA
24mA
10L
24mA
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.85V Min
• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
5-68
DC Characteristics for' ACQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +25"C
TA=
-55'C to + 125"C
TA=
-40'Cto +85"C
Typ
Icc
Maximum Quiescent
Supply Current
loz
Maximum TRI-STATE
Leakage Current
Units
Conditions
Guaranteed Limits
5.5
8.0
160.0
80.0
".A
VIN = Vcc
or GND (Note 1)
5.5
±0.5
±10.0
±5.0
".A
VI(OE) = VIL, VIH
VI = Vcc,GND
Vo = Vcc,GND
VOLP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Figures 1 and 2
(Notes 2 and 3)
VOLV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1 and 2
(Notes 2 and 3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.9
1.5
V
(Notes 2 and 4)
(Notes 2 and 4)
•All outputs loaded; thresholds on input associated with output under test.
tMaximum test dUration 2.0 ms, one output loaded at a time.
Note 1: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respective limit @ S.5V Vee.
Icc lor S4ACO @ 2S'C is identical to 74ACO @ 2S'C.
Note 2: Worst case package.
Note 3: Max number 01 outputs delined as (n). Data inputs are driven OV to SV. One output @ GND
Note 4: Max number 01 data Inputs (n) switching. (n -1) inputs switching OV to SV ('ACO). Input-under-test switching: SV to threshold (V,LO), OV to threshold (V,HO),
1= 1 MHz.
DC Characteristics for' ACTQ Family Devices
Symbol
Parameter
Vee
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
TA=
-55'C to + 125"C
TA=
- 40'C to + 85'C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVcc - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
orVcc - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
".A
loz
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
".A
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
5-69
lOUT = -50".A
'VIN = VIL or VIH
-24mA
IOH
-24mA
lOUT = 50".A
'VIN = VIL or VIH
24mA
IOL
24mA
VI = Vcc,GND
VI = VIL, VIH
Vo = Vcc,GND
DC Characteristics for I ACTa Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACTQ
S4ACTQ
74ACTQ
TA = +2SDC
TA=
-S5"Cto + 125"C
TA=
-40"Cto +8SDC
Typ
ICCT
Maximum
Icclinput
IOLD
tMinimum Dynamic
Output Current
IOHD
S.5
Units
Conditions
Guaranteed Limits
1.6
0.6
1.5
mA
VI = Vcc - 2.1V
5.5
50
75
mA
VOLD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
/LA
VIN = Vcc
or GND (Note 1)
Icc
Maximum Quiescent
Supply Current
5.5
VOLP
Maximum High Level
Output Noise
5.0
1.1
1.5
V
Figures 1 and 2
(Notes 2 and 3)
VOLV
Maximum Low Level
Output Noise
5.0
-0.6
-1.2
V
Figures 1 and 2
(Notes 2 and 3)
VIHD
Maximum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
(Notes 2 and 4)
(Notes 2 and 4)
'All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Note 1: Icc lor 54ACTO @ 25'C Is Identical to 74ACTO @ 25'C.
Note 2: Worst case package.
Note 3: Max number 01 outputs defined as (n). Data Inputs are driven OV to 3V. One output @ GND.
Note 4: Max number 01 data Inputs (n) switching. (n-l) Inputs switching OV to 3V ('ACTO). Input·under·test switching: 3V to threshold (VILO). OV to threshold
(VIHO). I = 1 MHz.
AC Electrical Characteristics:
Symbol
Parameter
Vee'
(V)
See Section 2 for Waveforms
74ACQ
S4ACQ
74ACQ
TA = +2SDC
CL = SOpF
TA = -SSDC
to + 12SDC
CL = SOpF
TA = -40"C
to +8SDC
CL = SOpF
Min
Min
Min
Typ
Max
Max
Units
Fig.
No.
Max
fmax
Maximum Clock
Frequency
3.3
5.0
75
90
tpLH, tpHL
Propagation Delay
CPtoOn
3.3
5.0
3.0
2.0
9.5
6.5
13.0
8.5
3.0
2.0
13.5
9.0
ns
2-3,4
tPZH,tPZL
Output Enable Time
3.3
5.0
3.0
2.0
9.5
6.5
13.0
8.5
3.0
2.0
13.5
9.0
ns
2-5,6
tpHZ, tpHL
Output Disable Time
3.3
5.0
1.0
1.0
9.5
8.0
14.5
9.5
1.0
1.0
15.0
10.0
ns
2-5,6
tOSHL,
tOSLH
Output to Output Skew"
CP to On
3.3
5.0
1.5
0.5
1.0
1.0
1.5
1.0
ns
70
85
MHz
'Voltage Range 5.0 Is 5.0V ±0.5V.
Voltage Range 3.3 is 3.3V ±0.3V.
"Skew Is defined as the absolute value 01 the difference between the actual propagation delay lor any two separate outputs 01 the same device. The specification
applies to any outputs switching In the same direction, either HIGH to LOW (tosHU or LOW to HIGH (toSLH)' Parameter guaranteed by design.
5-70
AC Operating Requirements:
See Section 2 for Waveforms
74ACQ
54ACQ
74ACQ
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Symbol
Parameter
Vee·
(V)
ts
Setup Time. HIGH or LOW
Dn toCP
3.3
5.0
0
0
3.0
3.0
tH
Hold Time, HIGH or LOW
Dn toCP
3.3
5.0
0
0
tw
LE Pulse Width,
HIGH or LOW
3.3
5.0
2.0
2.0
Units
Fig.
No.
3.0
3.0
ns
2-7
1.5
1.5
1.5
1.5
ns
2-7
4.0
4.0
4.0
4.0
ns
Typ
Guaranteed Minimum
2-3
'Voltage Range 5.0 Is 5.0V ±0.5V.
Voltage Range 3.3 Is 3.3V ±0.3V.
AC Electrical Characteristics:
Symbol
Parameter
Vee·
(V)
See Section 2 for Waveforms
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -400C
to +85'C
Cl = 50pF
Min
Min
Min
Typ
f max
Maximum Clock
Frequency
5.0
85
tpLH, tpHL
Propagation Delay
CPtoOn
5.0
2.0
7.0
Max
Max
Units
Fig.
No.
Max
80
MHz
9.0
2.0
9.5
liS
2-3,4
tpZH. tPZL
Output Enable Time
5.0
2.0
7.0
9.0
2.0
9.5
ns
2-5,6
tpHZ, tpHL
Output Disable Time
5.0
1.0
8.0
10.0
1.0
10.5
ns
2-5,6
tOSHL.
tOSLH
Output to Output Skew·'
CP to On
5.0
0.5
1.0
1.0
ns
'Voltage Range 5.0 is 5.0V ±0.5V.
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction. either HIGH to lOW (toSHU or lOW to HIGH (tosLH). Parameter guaranteed by design.
AC Operating Requirements:
Symbol
Parameter
Vee·
(V)
See Section 2 for Waveforms
74ACTQ
54ACTQ
74ACTQ
TA = +25"C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +S5'C
CL = 50pF
Units
Fig.
No.
Guaranteed Minimum
Typ
ts
Setup Time, HIGH or LOW
Dn toCP
5.0
0
3.0
3.0
ns
2-7
tH
Hold Time, HIGH or LOW
Dn to CP
5.0
0
1.5
1.5
ns
2-7
tw
LE Pulse Width,
HIGH or LOW
5.0
2.0
4.0
4.0
ns
2-3
'Voltage Range 5.0 is 5.0V ±0.5V.
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
CpO
Power Dissipation
Capacitance
40
pF
5-71
Conditions
Vee
Vee
=
=
5.0V
5.0V
•
~National
~ semiconductor
54ACQ/74ACQ573 • 54ACTQ/74ACTQ573
Quiet Series Octal Latch with TRI-STATE® Outputs
General Description
Features
The 'ACQI'ACTQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (CiE) inputs. The' ACQ/' ACTQ573 is functionally
identical to the 'ACQI'ACTQ373 but with inputs and outputs
on opposite sides of the package. The' ACQ/'ACTQ utilizes
NSC Quiet Series technology to guarantee quiet output
switching and improved dynamic threshold performance.
FACT Quiet Series™ features GTOTM output control and
undershoot corrector in addition to a split ground bus for
superior performance.
• Guaranteed simultaneous switching raise level and
dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Improved latch-up immunity
• Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
• Outputs sourcelsink 24 mA
• Faster prop delays than standard 'ACT573
• 4 kV minimum ESD immunity
Qrdering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
OE
LE
TLlF/10633-1
DO
01
O2
DO
01
0"
°2
°3
0.
Os
Os
06
06
03
~
0.,
OE
1
20
Vee
Do
01
2
19
00
3
18
°1
"
17
D2
03
D.
6
°2
°3
0.
Ds
06
7
Os
8
06
~
GNO
9
°7
LE
5
16
10
11
TL/F/10633-2
Pin Names
TL/F/10633-3
Description
Pin Assignment
forLCC
Data inputs
Latch Enable Input
TRI-STATE Output Enable Input
TRI-STATE Latch Outputs
De%0.03~
III III lID lID III
~I!l
GNO(rnJ
[IJ°l
mDo
LE !IiI
07 H]]
0 6 H]l
mOE
~Vcc
L,r.....,___
.---~
li!Joo
IBlHEfi!lIiZI@
Os
0, ~ ~ 0,
TLlF/10633-4
5-72
Functional Description
Truth Table
The 'ACQI'ACTQ573 contains eight D-type latches with
TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this
condition the latches are transparent, I.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the
Output Enable (CE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new
data into the latches.
Inputs
Outputs
OE
LE
D
On
L
L
L
H
H
H
L
X
H
L
X
X
H
L
00
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
00 = Previous 00 before HIGH·to·LOW transition of Latch Enable
Logic Diagram
DO
D,
LE
0,
°7
TL/F/l0633-5
Pleas. note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
•
5-73
Recommended Operating
Conditions
Absolute Maximum Rating
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National . Semiconductor Sales
Office/Distributors for availability and specifications.
DC Output Diode Current (10K)
Va = -0.5V
Va = Vee + 0.5V
DC Output Voltage (Vo)
DC Output Source
or Sink Current (10)
Supply Voltage (VeC>
'ACQ
'ACTQ
-0.5Vto +7.0V
Supply Voltage (VeC>
DC Input Diode Current (11K)
VI = -0.5V
VI = Vee + 0.5V
DC Input Voltage (VI)
Input Voltage (VI)
Output Voltage (Va)
Operating Temperature (TA)
74ACQ/ACTQ
54ACQ/ACTQ
-20mA
+20mA
-0.5V to Vee + 0.5V
-20mA
+20mA
-0.5Vto to Vee + 0.5V
±50mA
DC Vee or Ground Current
per Output Pin (lee or IGND)
Storage Temperature (TSTG)
DC Latchup Source
or Sink Current
2.0Vt06.0V
4.5Vt05.5V
±50mA
-65'Cto + 150'C
OVtoVee
OVtoVee
-40'Cto + 65'C
-55'C to + 125'C
Minimum Input Edge Rate AV I At
'ACQ Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate t:..VI At
'ACTQ Devices
VIN from 0.6V to 2.0V
Vee @ 4.5V, 5.5V
125 mV/ns
±300mA
Junction Temperature (TJ)
CDIP
PDIP
175'C
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply.
temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications.
DC Characteristics for' ACQ Family Devices
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +25'C
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
Typ
VIH
VIL
VOH
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.65
2.1
3.15
3.65
2.1
3.15
3.65
V
VOUT = O.W
or Vee - O.W
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - O.W
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.66
4.66
2.4
3.7
4.7
2.46
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
3.0
4.5
5.5
0.002
0.001
0.001
3.0
4.5
5.5
*AII outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
5-74
lOUT = -50/LA
'VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50/LA
V
'VIN = VIL or VIH
12mA
24mA
IOL
24mA
DC Characteristics for' ACQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACQ
54ACQ
74ACQ
TA = +25°C
TA=
- 55"C to + 125°C
TA=
- 40°C to + 85°C
Typ
liN
Maximum Input
Leakage Current
10LD
tMinimum Dynamic
Output Current
10HD
Icc
Maximum Quiescent
Supply Current
102
Maximum TRI·STATE
Leakage Curent
Units
Conditions
Guaranteed Limits
±0.1
5.5
±1.0
±1.0
}LA
VI = Vee,GND
(Note 1)
5.5
50
75
mA
VOLD = 1.65 VMax
5.5
-50
-75
mA
VOHD = 3.85 VMin
5.5
8.0
160.0
80.0
}LA
VIN = Vee
or GND (Note 1)
5.5
±0.5
±11.0
±5.0
}LA
VI(OE) = VIL, VIH
VI = Vcc,GND
Vo = Vee,GND
VOLP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Figures 1,2
(Note 2, 3)
VOLV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
VIHD
Minimum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
VILD
Maximum Low Level
Dynamic Input Voltage
5.0
1.9
1.5
V
(Notes2,4)
(Notes 2, 4)
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Nate 1: liN and Icc @ 3.0V are guaranteed to be less than or equal to the respeclive limit @ S.SV Vcc.
Icc lor S4ACQ @ 2S'C Is Identical to 74ACQ @ 2S'C.
Nate 2: Worst case package.
Nate 3: Max number 01 outputs defined as (n). Data Inputs are driven OV to SV. One output @ GND.
Nate 4: Max number 01 Data Inpuls (n) switching. (n - 1) Inputs switching OV to sv ('ACQ). Input-under-test switching: SV to threshold (VILO), OV to threshold
(VIHO), I ~ 1 MHz.
DC Characteristics for' ACTQ Family Devices
74ACTQ
54ACTQ
74ACTQ
TA=
+ 25°C
TA=
-55°C to + 125°C
TA=
- 400C to + 85°C
Parameter
Vee
(V)
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
orVec - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.50
0.50
0.44
0.44
Symbol
Typ
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
4.5
5.5
Units
Conditions
Guaranteed Limits
•All oUlputs loaded; thresholds on inpul associaled wilh output under lest
tMaximum test duration 2.0 ms, one output loaded at a time.
5·75
V
lOUT = -50}LA
·VIN = VIL or VIH
-24mA
-24mA
10H
lOUT = 50}LA
·VIN = VILorVIH
24mA
10L
24mA
DC Characteristics for' ACTQ Family Devices (Continued)
Symbol
Parameter
Vee
(V)
74ACTQ
S4ACTQ
74ACTQ
TA = +25"C
TA=
-SS'C to + 12S'C
TA=
-40'Cto +8S'C
Typ
Units
Guaranteed Limits
liN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
±1.0
p.A
loz
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
p.A
ICCT
Maximum
Icc/Input
5.5
1.6
1.5
mA
10LD
tMinimum Dynamic
Output Current
10HD
Conditions
0.6
V, = Vee,GND
V, = V'l, V,H
Vo = Vee,GND
V, = Vee - 2.1V
5.5
50
75
mA
VOlD = 1.65V Max
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
p.A
Y,N = Vcc
orGND(Note1)
Icc
Maximum Quiescent
Supply Current
5.5
VOlP
Maximum High Level
Output Noise
5.0
1.1
1.5
V
Figures 1,2
(Notes 2, 3)
VOlV
Maximum Low Level
Output Noise
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
V,HD
Maximum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
V,lD
Maximum Low Level
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
(Notes 2, 4)
(Notes 2,4)
'All outputs loaded; thresholds on Input associated wHh output under test
tMaximum test duration 2.0 ms, one output loaded at a time.
Note 1: Icc for 54ACTO @ 25"C Is identical to 74ACTO @ 2S'C.
Note 2: Worst case package.
Note 3: Max number of outputs defined as (n). Data Inputs are driven OV to 3V. One output @ GND.
Note 4: Max number of data Inputs (n) switching. (n - 1) Inputs swHchlng OV to 3V ('ACTO). Input-under-lesl switching: 3V to threshold (VILO), OV to threshold
(VIHO), f = 1 MHz.
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
Vee'
(V)
74ACQ
S4ACQ
74ACQ
TA= +2S'C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL=SOpF
Min
Max
Units
Fig.
No.
Min
Typ
Max
Min
Max
tpHl,
tpLH
Propagation Delay
DntoOn
3.3
5.0
2.5
1.5
8.5
5.5
10.5
7.0
2.5
1.5
11.0
7.5
ns
2-3,4
tpLH,
tpHL
Propagation Delay
LEtoOn
3.3
5.0
2.5
2.0
8.5
6.0
12.0
8.0
2.5
2.0
12.5
8.5
ns
2-3,4
tpZl,
tpZH
Output Enable Time
3.3
5.0
2.5
1.5
8.5
6.0
13.0
8.5
2.5
1.5
13.5
9.0
ns
2-5,6
tpHZ,
tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
9.0
6.0
14.5
9.5
1.0
1.0
15.0
10.0
ns
2-5,6
toSHl,
tOSlH
Output to Output Skew"
DntoOn
3.3
5.0
1.0
0.5
1.5
1.0
1.5
1.0
ns
'Voltage Range S.O is S.OV ±O.SV
Voltage Range 3.3 is 3.3V ±0.3V
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching In the sarne direction, either HIGH to LOW (toSHL or LOW to HIGH (toSLH)' Parameter guaranteed by design.
5-76
AC Operating Requirements:
See Section 2 for Waveforms
74ACQ
54ACQ
74ACQ
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Units
Fig.
No.
3.0
3.0
ns
2·7
1.5
1.5
1.5
1.5
ns
2·7
4.0
4.0
4.0
4.0
ns
2·3
Units
Fig.
No.
Parameter
Vce'
(V)
ts
Setup Time, HIGH or LOW
Onto LE
3.3
5.0
0
0
3.0
3.0
tH
Hold Time, HIGH or LOW
Onto LE
3.3
5.0
0
0
tw
LE Pulse Width, HIGH
3.3
5.0
2.0
2.0
Symbol
Typ
Guaranteed Minimum
'Voltage Range 5.0 Is 5.0V ± 0.5V
voltage Range 3.3 is 3.3V ±0.3V
AC Electrical Characteristics:
Symbol
Parameter
tpHL,
tpLH
Propagation Delay
Onto On
tPLH,
tpHL
Propagation Delay
LE to On
See Section 2 for Waveforms
Vee'
(V)
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Min
Typ
Max
Min
Max
5.0
2.0
6.5
7.5
2.0
8.0
ns
2·3,4
5.0
2.5
7.0
8.5
2.5
9.0
ns
2·3,4
Min
Max
tpZL, tPZH
Output Enable Time
5.0
2.0
7.0
9.0
2.0
9.5
ns
2·5,6
tpHZ, tpLZ
Output Disable Time
5.0
1.0
8.0
10.0
1.0
10.5
ns
2·5,6
toSHL
toSLH
Output to Output Skew"
On to On
5.0
0.5
1.0
1.0
ns
'Voltage Range 5.0 is 5.0V ± O.5V
• 'Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction, either HIGH to LOW (tosHL or LOW to HIGH (tosLHI. Parameter guaranteed by design.
AC Operating Requirements:
Symbol
Parameter
Vec'
(V)
See Section 2 for Waveforms
74ACTQ
54ACTQ
74ACTQ
TA = +25'C
Cl = 50pF
TA = -55'C
to + 125'C
Cl = 50pF
TA = -40'C
to +85'C
Cl = 50pF
Typ
Units
Fig.
No.
Guaranteed Minimum
Is
Setup Time, HIGH or LOW
Dn toLE .
5.0
0
3.0
3.0
ns
2·7
tH
Hold Time, HIGH or LOW
Onto LE
5.0
0
1.5
1.5
ns
2·7
tw
LE Pulse Width, HIGH
5.0
2.0
4.0
4.0
ns
2·3
'voltage Range 5.0 is 5.0V ± 0.5V
CapaCitance
Symbol
Parameter
Typ
Units
CIN
Input CapaCitance
4.5
pF
CPO
Power Dissipation
Capacitance
pF
42.0
5·77
Conditions
Vee
Vee
=
=
5.0V
5.0V
~National
~ semiconductor
54ACQ/74ACQ574 • 54ACTQ/7 4ACTQ57 4
Quiet Series Octal DFlip-Flop
with TRI-STATE® Outputs
General Description
Features
The 'ACQI'ACTQ574 is a high-speed, low-power octal Dtype flip-flop with a buffered Common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-toHIGH ciock (OP) transition.
'ACQ/'ACTQ574 utilizes Quiet Series technology to guarantee quiet output switching and improve dynamic threshold
performance. FACT Quiet Series™ features GTOTM output
control and undershoot corrector in addition to a split
ground bus for superior performance.
The 'ACQ/'ACTQ574 is functionally identical to the
'ACTQ374 but with different pin-out.
• Guaranteed simultaneous switching noise level and dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Inputs and outputs on opposite sides of the package allowing easy interface with microprocessors
• Functionally identical to the 'ACQ/ACTQ374
• TRI-STATE outputs drive bus lines or buffer memory
address registers
• Outputs source/sink 24 mA
• Faster prop delays than the standard 'AC/'ACT574
• 4 kV minimum ESD immunity
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
OE
CP
OE
TL/F/10634-1
Do
00
01
01
O2
O2
03
03
04
°4
Os
Os
06
Os
17
°7
OE
1
20
Do
2
19
01
18
Do-D7
CP
OE
00-0 7
°1
O2
03
0,
Os
Os
Os
°7
GNO
CP
10
TL/F/10634-2
Pin Names
Vee
00
TL/F/10634-3
Pin Assignment
Description
for LCC and PCC
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
TRI-STATE Outputs
Os Os 04 Os ~
[!][[J[!][§]III
07 [I]
GNOIi]]
CPIllI
°7[i]]
°slill
~~
•••••
mOl
III Do
mOE
~
(gQJVee
[IDoo
" Os
IBlliIDliIDliZlliID
04 ~
Oz 01
TL/F/10634-4
5-78
Function Table
Functional Description
Inputs
The 'ACQ/'ACTQ574 consists of eight edge-triggered flipflops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual 0 inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When OE
is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.
Internal
Outputs
OE
CP
D
Q
ON
H
H
H
.../"
.../"
.../"
L
H
L
H
L
H
L
H
NC
NC
L
H
L
H
NC
NC
Z
Z
Z
Z
H
H
H
L
L
L
L
.../"
H
H
L
H
NC
NC
Function
Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
.../ = LOW-to·HIGH Transition
NC = No Change
Logic Diagram
TL/F/l0634-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5-79
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage {Vee>
DC Input Diode Current (11K)
-20mA
VI = -0.5V
+20mA
VI = Vee + 0.5V
DC Input Voltage (VI)
-0.5V to Vee + 0.5V
DC Output Diode Current (10K)
Vo = -0.5V
-20mA
+20mA
Vo = Vee + 0.5V
DC Output Voltage (Vo)
-0.5V to Vee + 0.5V
DC Output Source
±50mA
or Sink Current (10)
DC Vee or Ground Current
±50mA
per Output Pin (lee or IGNO)
Storage Temperature (T8TG)
- 65'C to + 150'C
DC Latch·Up Source or
±300mA
Sink Current
Junction Temperature (TJ)
CDIP
175'C
PDIP
140'C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The datebook specifications should be met, without
exception. to ensure that the system design Is reliable over Its power supply,
temperature, and output/Input loading variables. National does not recom·
mend operation of FACTTM clrcuUs outside datebook speCifications.
Supply Voltage {Vee>
'ACO
'ACTO
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TAl
·74ACOIACTO
2.0Vt06.0V
4.5Vt05.5V
OVtoVee
OVtoVee
-40'Cto +85'C
-55'Cto + 125'C
54ACO/ACTO
Minimum Input Edge Rate AV I At
'ACO Devices
VIN from 30% to 70% of Vee
Vee @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate AV I At
'ACTO Devices
VIN from 0.8V to 2.0V
Vee @ 4.5V, 5.5V
125mV/ns
125mV/ns
DC Electrical Characteristics for' ACQ Family Devices
Symbol
74ACQ
54ACQ
74ACQ
TA = +25'C
TA=
- 55'C to + 125'C
TA=
-40'Cto +85'C
Parameter
Vee
(V)
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1V
or Vee - 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1V
or Vee - 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
Typ
VIH
VIL
VOH
3.0
4.5
5.5
VOL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.002
0.001
0.001
Units
Conditions
Guaranteed Limits
•All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
5·80
lOUT = -50/loA
V
·VIN = VIL or VIH
-12mA
-24mA
10H
-24mA
lOUT = 50/loA
V
V
·VIN = VIL or VIH
12mA
24mA
10L
24mA
DC !Electrical Characteristics for' ACQ Family Devices (Continued)
54ACQ
74ACQ
TA =
-55'C to + 125'C
TA =
- 40'C to + 85'C
74ACQ
Symbol
Parameter
Vcc
(V)
TA
= +25'C
Typ
liN
Maximum Input
Leakage Current
IOLD
tMinimum Dynamic
Output Current
IOHD
lee
Maximum Quiescent
Supply Current
loz
Maximum TRI-STATE
Leakage Current
Conditions
Guaranteed Limits
±0.1
5.5
Units
±1.0
±1.0
/LA
V, = Vee,GND
(Note 1)
= 1.65V Max
5.5
50
75
mA
VOlD
5.5
-50
-75
mA
VOHD = 3.85V Min
5.5
8.0
160.0
80.0
/LA
V,N = Vee
orGND(Note1)
5.5
±0.5
±10.0
±5.0
/LA
V,(OE) = V'l, V,H
V, = Vee,GND
Vo = Vee, GND
VOlP
Quiet Output
Maximum Dynamic VOL
5.0
1.1
1.5
V
Figures 1,2
(Notes 2, 3)
VOLV
Quiet Output
Minimum Dynamic VOL
5.0
-0.6
-1.2
V
Figures 1,2
(Notes 2, 3)
V,HD
Minimum High Level
Dynamic Input Voltage
5.0
3.1
3.5
V
V,LD
Maximum Low Level
Dynamic Input Voltage
5.0
1.9
1.5
V
(Notes 2, 4)
(Notes 2, 4)
'All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.
Nole 1: liN and Icc @ 3.0V are guaranteed to be less than or equal to the rospective limit @ 5.5V Vec.
Icc lor 54ACO @ 25'C Is identical to 74ACO @ 25'C
Note 2: Worst case package.
Nole 3: Max number 01 outputs defined as (n). Data Inputs are driven OV to 5V. One output @ GND.
Nole 4: Maximum number 01 data Inputs (n) switching. (n-l) inputs switching OV to 5V (,ACO). Input·under-tesl switching: 5V to threshold (V,LO), OV to threshold
(V,HO). I = 1 MHz.
5-81
DC Electrical Characteristics for' ACTQ Family Devices
74ACTQ
Symbol
Parameter
Vee
(V)
54ACTQ
74ACTQ
TA=
TA=
Units
-55"Cto + 125"C -40"Cto +85'C
TA = +25"C
Typ
CondlUons
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT = 0.1V
or Vee - 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT = 0.1V
or Vee - 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.85
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
lOUT = -50 JloA
'VIN = VIL or VIH
-24mA
10H
-24mA
lOUT = 50p.A
'VIN = VIL or VIH
24mA
10L
24mA
liN
Maximum Input Leakage Current 5.5
±0.1
±1.0
±1.0
p.A
VI = Vee,GND
loz
Maximum TRI-STATE
Leakage Current
5.5
±0.5
±10.0
±5.0
JloA
VI = VIL, VIH
Vo = Vee,GND
leCT
Maximum
leellnput
5.5
1.6
1.5
mA
10LD
....::.=..10HD
tMaximum Dynamic
Output Current
0.6
VI = Vee - 2.1V
5.5
50
75
mA
VOLD = 1.65VMax
5.5
-50
-75
mA
VOHD = 3.85V Min
160.0
80.0
JloA
VIN = Vee
or GND (Note 1)
Icc
Maximum Quiescent
Supply Current
5.5
VOLP
Maximum !"Iigh Level
Output Noise
5.0
1.1
1.5
V
Figures 1,2
(Notes 2, 3)
VOLV
Maximum Low' Level
Output Noise ..
5.0
-0.6
-1.2
V
Rgures 1,2
(Notes 2, 3)
VIHD
Maximum High Level
Dynamic Input Voltage
5.0
1.9
2.2
V
VILD
Maximum Low Lev~!
Dynamic Input Voltage
5.0
1.2
0.8
V
8.0
(Notes 2, 4)
(Notes 2, 4)
• All outputs loaded: thresholds on input associated with output under test.
tMaximum test duration 2.0 ms. one output loaded at a time.
Note 1: Icc lor 54ACTO
@
25'C Is identical to 74ACTO
@
25"C.
Note 2: Worst case package.
Note 3: Max number 01 outputs defined as (n). Data inputs ere driven OV to 3V. One output
@
GND.
Note 4: Max number of data inputs (n) switching. (n-l) inputs switching OV to 3V (,ACTO). Input·under·test switching: 3V to thrashold (VILol. OV to threshold
(VIHol, I = 1 MHz.
5-82
AC Electrical Characteristics:
Symbol
Parameter
Vcc'
(V)
See Section 2 for Waveforms
74ACQ
S4ACQ
74ACQ
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 12S'C
CL = 50pF
TA = -40'C
to +8S'C
CL=SOpF
Min
Min
Min
Typ
Max
Max
Units
Fig.
No.
Max
f max
Maximum Clock
Frequency
3.3
5.0
75
90
tpLH
tpHL
Propagation Delay
CPtoOn
-
3.0
5.0
3.0
2.0
9.5
6.5
13.0
8.5
3.0
2.0
13.5
9.0
ns
2·3,4
tPZH
tpZL
Output Enable Time
3.3
5.0
3.0
2.0
9.5
6.5
13.0
8.5
3.0
2.0
13.5
9.0
ns
2·5,6
tpHZ
tpLZ
Output Disable Time
3.3
5.0
1.0
1.0
9.5
8.0
14.5
9.5
1.0
1.0
15.0
10.0
ns
2·5,6
tOSHL,
tOSLH
Output to Output Skew"
CPtoOn
3.3
5.0
1.0
0.5
1.5
1.0
1.5
1.0
ns
70
85
MHz
'Voltage Range 5.0 Is 5.0V ±0.5V
Voltage Range 3.3 Is 3.3V ±0.3V
"Skew Is defined as the absoluta value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification
applies to any outputs switching in the same direction. either HIGH to LOW {!oSHU or LOW to HIGH (!oSLH). Parameter guaranteed by design.
AC Operating Requirements:
See Section 2 for Waveforms
74ACQ
S4ACQ
74ACQ
TA = +2S'C
CL = SO pF
TA = -S5'C
to + 12S'C
CL = SOpF
TA = -40'C
to +8S'C
CL = SOpF
Units
Fig.
No.
3.0
3.0
ns
2·7
1.5
1.5
1.5
1.5
ns
2·7
4.0
4.0
4.0
4.0
ns
2·3
Parameter
Vcc'
(V)
ts
Setup Time, HIGH or LOW
Dn to CP
3.3
5.0
0
0
3.0
3.0
tH
Hold Time, HIGH or LOW
Dn toCP
3.3
5.0
0
0
tw
LE Pulse Width,
HIGH or LOW
3.3
5.0
2.0
2.0
Symbol
Typ
Guaranteed Minimum
'Voltage Range 5.0 is 5.0V ±0.5V
Voltage Range 3.3 Is 3.3V ± 0.3V
!
5·83
AC Electrical Characteristics:
See Section 2 for Waveforms
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
CL=SOpF
TA = -SlrC
to + 12lrC
CL = SOpF
TA = -4O'C
to +8lrC
CL = SOpF
Parameter
Vcc'
fmax
Maximum Clock Frequency
5.0
85
tpLH,
tpHL
Propagation Delay
CPtoOn
5.0
2.0
7.0
9.0
2.0
9.5
ns
2·3,4
tpZH,
tPZL
Output Enable Time
5.0
20
7.0
9.0
2.0
9.5
ns
2·5,6
tpHZ,
tpLZ
Output Disable Time
5.0
1.0
8.0
10.0
1.0
10.5
ns
2·7
Symbol
(V)
Min
Typ
Max
Min
Max
Min
Units
Fig.
No.
Max
MHz
80
Output to Output Skew"
taSHL,
5.0
0.5
1.0
1.0
ns
CPtoOn
taSLH
'Voltage Range 5.0 Is 5.0V ± 0.5V.
"Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specHication
applies 10 any outputs switching in the same direction, either HIGH to LOW (IoSHU or LOW to HIGH (IoSLH). Parameter guaranteed by design.
AC Operating Requirements:
Symbol
Parameter
See Section 2 for Waveforms
vcc'
(V)
74ACTQ
S4ACTQ
74ACTQ
TA = +2S'C
CL = SOpF
TA = -SS'C
to + 12lrC
CL=SOpF
TA = -40'C
to +8lrC
CL = SOpF
Units
Fig.
No.
Guaranteed Minimum
Typ
Is
Setup Time, HIGH or LOW
Dn to CP
5.0
0
3.0
3.0
ns
2·7
tH
Hold Time, HIGH or LOW
Dn to CP
5.0
0
1.5
1.5
ns
2·7
5.0
2.0
4.0
4.0
ns
2·3
LE Pulse Width,
HIGH or LOW
'Voltage Range 5.0 is 5.0V ± 0.5V
tw
Capacitance
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
Vee = 5.0V
CPO
Power Dissipation Capacitance
40.0
pF
Vee = 5.0V
Symbol
Parameter
5·84
~National
ADVANCE INFORMATION
~ Semiconductor
54ACQ/74ACQ646 • 54ACTQ/74ACTQ646
Quiet Series Octal TransceiverIRegister
with TRI-STATE® Outputs
General Description
Features
The 'ACQI'ACTQ646 consist of registered bus transceiver
circuits, with outputs, D-type flip-flops, and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
orCPBA).
• Guaranteed simultaneous switching noise level and dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Independent registers for A and B busses
• Multiplexed real-time and stored data transfers
• 300 mil slim dual-in-line package
• Outputs source/sink 24 mA
• Faster prop delays than the standard 'AC/'ACT646
• 4 kV minimum ESD immunity
The 'ACQI'ACTQ utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
The information on the ACQ646 is Advanced Information only.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
CPAD
DIR
AD
Ao-A7
Bo-B7
CPAB,CPBA
SAB,SBA
G
DIR
24
Vee
23
CPDA
22
SBA
4
21
Al
20
Bo
A2
19
Bl
A3
7
18
B2
A4
8
17
B3
As
9
16
B4
A.
10
15
Bs
A7
GND
11
14
B.
12
13
TL/F/l0635-1
Pin Names
1
SAD
DIR
CPBA
B7
Description
TL/F/l0635-3
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
Pin Assignment
for LCC and PCC
As A4 A3 NC A2 Al
Ao
IIll[QJIIDIIDIllOOIID
TUF/l0635-2
A. rrn
I1lDlR
A71i1l
GND IGI
NCijID
B7 1!§J
B61ill
Bsl!§J
mSAB
rn CPAB
[TINC
IilJVcc
IiiI CPBA
filISBA
\:x,I(JOI(JIOUIif
fi]]1!l!I1!ll1ill@~filI
B4 B3 B2 NCB 1 Bo
G
TLlF/l0635-4
5-85
,----------------------------------------------------------------------------,
ADVANCE INFORMATION
o ·~National
~
II)
CD
~ semiconductor
54ACQ/74ACQ657 • 54ACTQ/74ACTQ657
Quiet Series Octal Bidirectional Transceiver
with 8-Bit Parity Generator/Checker
and TRI-STATE® Outputs
General Description
Features
The 'ACQI'ACTQ657 contains eight non·inverting buffers
with TRI·STATE outputs and an B·bit parity generator/
checker. Intended for bus oriented applications, the device
combines the '245 and the '2BO functions in one package.
The 'ACQ/'ACTQ utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTOTM output control and undershoot corrector in addition
to a split ground bus for superior performance.
The Information on the ACQ657 Is Advanced Information
• Guaranteed simultaneous switching noise level and dy·
namic threshold performance
• Guaranteed pin·to·pin skew AC performance
• Combines the '245 and the '2BO functions in one
package
• 300 mil 24·pin slim dual·in·line package
• Outputs source/sink 24 rnA
• 4 kV minimum ESD immunity
only.
Logic Symbols
Connection Diagrams
IEEEIiEC
Pin Assignment
for DIP, SOIC
and Flatpak
TIR
DE
TIR
ODD/
EVEN
24
ERROR
80
8,
B2
83
84
85
8s 86 87 Ne PAR ERR ODD/EVEN
!i]1@I[!]1!l[l]l!lm
DE
23
Bo
B41i11
III A7
A,
3
22
B,
Az
4
B2
GNDIiID
GND IBI
III As
Ao
PARllY
Pin Assignment
for LCC and PLCC
rn A6
A3
5
2'
20
A4
6
19
B3
GNO
Vee
7
'8
GNO
8
17
B4
9
16
(:JIlJO-I'II{JIIXIIO{]l'II.,if
85
liID~gjj~I1l!I~11l!I
Bo Of T/ii NC
~
~
NCHID
83 Ii§!
82 1iZ1
8, Ii§!
A7
ODD/EVEN
10
15
86
11
14
ERROR
12
13
B7
PARITY
OJNC
I1l!I Vee
~A4
I1l!I A3
Ao
A, Az
TL/F/l0636-3
86
TLlF/l0636-2
B7
TLlF/l0636-1
Pin Names
Ao- A7
8 0- 8 7
TL/F/l0636-4
T/R
OE
PARITY
ODD/EVEN
ERROR
5·B6
Description
Data Inputs/TRI·STATE Outputs
Data Inputs/TRI-STATE Outputs
Transmit/Receive Input
Enable Input
Parity Input/TRI·STATE Output
ODD/EVEN Parity Input
Error Output
~National
ADVANCE INFORMATION
~ Semiconductor
54ACQ/74ACQ821
Quiet Series 10-Bit 0 Flip-Flop
with TRI-STATE® Outputs
General Description
Features
The 'ACQ821 is a 10-bit D flip-flop with non-inverting TRISTATE outputs arranged in a broadside pinout. The
ACQ821 utilizes NSC Quiet Series technology to guarantee
quiet output switching and improved dynamic threshold performance. FACT Quiet Series™ features GTOTM output
control and undershoot corrector in addition to a split
ground bus for superior performance.
• Guaranteed simultaneous switching noise level and dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Non-inverting TRI-STATE outputs for bus interfacing
• 4 kV minimum ESD immunity
• Outputs source/sink 24 rnA
• Functionally identical to the AM29821
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
DE
CP
DE
1
Do
°0
Do
2
D,
°1
D,
3
CP
TLlF/l0686-1
D2
°2
D3
°3
D4
°4
Ds
Os
D6
°6
I?
°7
D8
°8
D9
°9
TLlF/l0686-2
24
Vcc
°0
°1
D2
D3
°2
03
D4
°4
Ds
°5
D6
°6
D7
°7
Os
D8
09
D9
GND
12
13
CP
TLlF/l0686-3
Pin Names
Do-Dg
OO-Og
OE
CP
Description
Pin Assignment
forlCC
Data Inputs
Data Outputs
Output Enable Input
Clock Input
I? D6
Ds NC 04 03 02
1TIl1i~][!lIIJ[ll [§]
~~
m
.r-\..r'1.r-
r-
~ ill 0 ,
~ III Do
08~
Oglill
IKmOE
IK ill NC
GNO 1m
NC 1m
CP 1m
~ ~Vcc
~ gzj °0
OgliZl
081iID~
~ ~O,
1iID@l1lil~~~@j
07 06 Os NC 04 03 02
TLlF/l0686-4
5-87
~National
ADVANCE INFORMATION
~ Semiconductor
54ACTQ/74ACTQ827 Quiet Series
10-Bit Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The' ACTQ827 10-bit bus buffer provides high performance
bus interface buffering for wide datal address paths or buses carrying parity. The 10-bit buffers have NOR output enables for maximum control flexibility. The 'ACTQ827 utilizes
NSC Quiet Series technology to guarantee quiet output
switching and improved dynamic threshold performance.
FACT Quiet Series™ feature GTOTM output control and undershoot corrector in addition to a split groun.d bus for superior performance.
• Guaranteed simultaneous switching noise level and dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
• Improved latch-up immunity
• Outputs sourcelsink 24 mA
• Functionally and pin-compatible to AMD's AM29827
• 'ACTQ827 has TTL-compatible inputs
• 4 kV minimum ESD immunity
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIIEC
DE,
Do
0,
02
O~
TL/F/l06S7-1
D.
05
06
07
Pin Names
OE"OE2
Do-D7
00-0 7
Description
Output Enable
Data Inputs
Data Outputs
°6t------1
06
~t-----t
Or
°st------1 Os
Os
Os
GNO
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
09 1 - - - - - 1 Og
Vee
°0
°1
°2
O~
0.
°s
06
°7
Os
°9
DE2
TUF/l06B7-3
TUF/l08B7-2
Pin Assignment
forlCC
mo,
moo
0sli1l
OglHl
GNO 1m
ill OE,
NC[j]J
[j]NC
OE2 Ii]
OgllZl
Os liE
liZIOo
Iii!I vee
~IIOO~W
Iii!I 01
1iEf!iil1llI1iil1iiI~1ii!I
°706 05 NC 04 O~ 02
TLlF/l0BB7-4
5-88
~National
ADVANCE INFORMATION
~ Semiconductor
54ACTQ/74ACTQ841 Quiet Series 10-Bit Transparent
latch with TRI .. STATE® Outputs
General Description
Features
The 'ACTQ841 bus interlace latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths or
buses carrying parity. The '841 is a 1O-bit transparent latch,
a 10-bit version of the '373. The 'ACTQ841 utilizes NSC
Quiet Series technology to guarantee quiet output switching
and improved dynamic threshold performance, FACT Quiet
Series™ features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
II Guaranteed simultaneous switching noise level and
dynamic threshold performance
II Guaranteed pin-to-pin skew AC perlormance
II Inputs and outputs on opposite sides of package allow
easy interlace with microprocessors
.. Improved latch-up immunity
II Outputs source/sink 24 mA
III 'ACTQ841 has TTL-compatible inputs
II 4 kV minimum ESD immunity
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and sOle
OE
LE
°0
OE
LE
TL/F/l0S88-1
OE
1
24
VCC
00
2
23
00
°0
°1
22
01
°1
°1
21
O2
°2
°2
20
°30
°3
°3
°2
03
04
19
°4
Os
4
°4
Os
Os
°6
Os
07
08
09
°9
Os
06
18
17
06
16
°7
10
15
°8
11
14
GNO- 12
13
°9
LE
°7
°7
08
°8
D9
8
TLlF/l0688-2
TL/F/l0S88-3
Pin Names
Do-D9
00-0 9
OE
LE
Description
Pin Assignment
for Lee
Data Inputs
TRI-STATE Outputs
Output Enable
Latch Enable
07 06 Os NC 04 03 O2
1TIl[§JI]][[]mlIllIl
°sli1l
mOt
09 Ii]
GNO [1J
NC Ii]
LE Ij]]
III Do
mOE
[I]NC
Illi vce
°9 [j]
Ill] 00
°slj]]
Illi 0t
1j]]g:§]~IllJ~IEl~
07 Os Os Ne 04 03 02
TLlF/l0688-4
5-89
~National
ADVANCE INFORMATION
~ Semiconductor
54ACTQ/74ACTQ843
Quiet Series 8-Bit Transparent Latch
General Description
Features
The 'ACTQ843 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/ data paths. The
'ACTQ843 utilizes NSC,Quiet Series technology to guarantee quiet output switching and improved dynamic threshold
performance. FACT Quiet Series™ features GTOTM output
control and undershoot corrector in addition to a split
ground bus for superior performance.
• Guaranteed simultaneous switching noise level and
dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Inputs and outputs on oppostie sides of package for
easy interface with microprocessors
• Improved latch-up immunity
• Outputs source/sink 24 mA
• 'ACTQ843 has TTL-compatible inputs
• Functionally and pin-compatible to AMO's AM29843
• 4 kV minimum ESO immunity
• 'ACT843 has TTL-compatible inputs
.. TRI-STATE® outputs for bus interfacing
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
DE
Do
1
24
2
23
°1
02
03
3
22
4
21
5
20
03
04
6
19
Os
06
7
18
°4
8
17
0,
9
08
10
16
15
CLR
11
14
Os
PRE
GNO
12
13
LE
°0
TUF/l0689-1
°1
°1
~
°2
03
03
°4
0.
Os
06
Os
06
0,
~
Os
Os
TLlF/l0689-4
Vee
00
°1
°2
Os
06
°7
TL/FI106S9-2
Pin Names
Pin Assignment
forLCC
Description
07 0 6 Os NC 04 03 O2
Data Inputs
Data Outputs
Output Enable
Latch Enable
Clear
Preset
lTII[Q]rn:I III III IIIrn
[!] 0 1
Os jgI
CLRIbiI
GNO IBJ
moo
[1] DE
[TINC
NC~
LEIiID
PRE Ii1I
~Vee
°sliID
~01
gnOo
IlIDEl!I~~~~~
°7 °6 Os NC 04 03 02
TUF/l0689-3
5-90
Section 6
FCT Series Datasheets
Section 6 Contents
54FCT/74FCT138 1-to-8 Multiplexer... .. ... ........ ...... .... .. ... .. ..... ......... ...
54FCT174FCT240 Octal Buffer/Line Driver with TRI-STATE Outputs......................
54FCT174FCT241 Octal Buffer/Line Driver with TRI-STATE Outputs......................
54FCT174FCT244 Octal Buffer/Line Driver with TRI-STATE Outputs......................
54FCT /74FCT245 Octal Buffer/Line Driver with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . .
54FCT174FCT273 Octal D Flip-Flop..................................................
54FCT174FCT373 Octal Transparent Latch with TRI-STATE Outputs. ........ . .... ..... ..
54FCT /74FCT37 4 Octal D Flip-Flop with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . .
54FCT174FCT377 Octal D Flip-Flop with Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54FCT174FCT521 8-Bit Identity Comparator. .......... .... .. .... ..... ..... . ...........
54FCT174FCT533 Octal Transparent Latch with TRI-STATE Outputs.. .. ..... ........... .
54FCT174FCT534 Octal D Flip-Flop with TRI-STATE Outputs.. .... ..... ..... .......... ..
54FCT540 Inverting Octal Buffer/Line Driver with TRI-STATE Outputs ....................
54FCT541 Non-Inverting Octal Buffer/Line Driver with TRI-STATE Outputs . . . . . . . . . . . . . . . .
54FCT174FCT543 Octal Registered Transceiver with TRI-STATE Outputs. . . . . . . . . . . . . . . . .
54FCT174FCT544 Octal Registered Transceiver with TRI-STATE Outputs. . . . . . . . . . . . . . . . .
54FCT174FCT563 Octal Transparent Latch with TRI-STATE Outputs. . .. ..... ... ..... ....
54FCT174FCT564 Octal D Flip-Flop with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . .
54FCT174FCT573 Octal Transparent Latch with TRI-STATE Outputs...... ........... ....
54FCT174FCT574 Octal D Flip-Flop with TRI-STATE Outputs............................
54FCT174FCT646 Octal Transceiver/Register with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . .
6-2
6-3
6-4
6-8
6-12
6-16
6-20
6-25
6-30
6-35
6-40
6-41
6-46
6-51
6-55
6-59
6-60
6-61
6-66
6-70
6-75
6-80
r----------------------------------------------------------------------------, -"
Co)
~National
ADVANCE INFORMATION
~ semiconductor
54FCT17 4FCT138
1-of-8 DecoderIDemultiplexer
General Description
Features
The 'FCT138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just
three 'FCT138 devices or a 1-of-32 decoder using four
'FCT138 devices and one inverter.
FACTTM FCT utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCT features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
• NSC 54FCT174FCT138 is pin and functionally equivalent to lOT 54FCT174FCT138
• Demultiplexing capability
• Multiple input enable for easy expansion
• Active LOW mutually exclusive outputs
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 rnA (Com), 32 rnA (Mil)
• CMOS power levels
• ESD immunity ;;, 4 kV typ
• Military Product compliant to MIL-STD 883 and Standard Military Drawing #5962-87654
Logic Symbol
Connection Diagrams
Pin Assignment
forLCC
Pin Assignment
for DIP, Flatpak and SOIC
E3i2NC£I~
Ao
TL/F/l0657-1
IEEEIIEC
1Il1Il[[][[I[±J
Vee
AI
2
15
00
A2
£1
[2
3
4
5
14
13
12
°2
E3
6
11
°4
°7
GND
°1
°3
07 [[J
GND Il]J
NC ITII
rnA l
mAo
ITlNC
°6 1W
05 Ii]
1lID0o
~Vee
°5
°6
1Hl1i]J1i§]1i1I1mi
04 03 NC 02 01
BIN/OCT
Ao
1
AI
A2
2
°1
°2
03
4
°4
E3
£1
[2
TL/F/l0657-2
00
EN
°5
°6
°7
TL/F/l0657-4
Pin Names
Ao-A2
El-E2
Es
00-0 7
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
6-3
TUF/l0657-3
00
~National
~ Semiconductor
54FCT/7 4FCT240
Inverting Octal Buffer/Line Driver
with TRI-STATE® Outputs
General Description
Features
The 'FCT240 is an inverting octal buffer and line driver de·
signed to be employed as a memory address driver, clock
driver and bus oriented transmitter or receiver which pro·
vides improved PC board density.
• NSC 54FCT174FCT240 is pin and functionally equiva·
lent to IDT 54FCT174FCT240
• Inverting TRI·STATE outputs
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 64 rnA (commercial), 46 rnA (military)
• CMOS power levels
• ESD immunity ~ 4 kV typ
• Military product compliant to MIL·STD 663 and stan·
dard military drawing #5962·87655
FACTTM FCT utilizes NSC quiet series technology to pro·
vide improved quiet output switching and dynamic threshold
performance.
FACT FCT features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior per·
formance.
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
_
OE,
m
ilE2
I>
v
~Ij,\
G~~:.~~I
1-"--1.
0'"8"\'
~
~3-;1\
07~", '
~,
Os
I,
0,
~
°s----:c'
'
I,..! ,\
.27,\
Is
17
13 06 12 Os "
00 1lJ00 oorn
.'-/
~.~"\ orO'~"\' 1-"--1.
N
I,
I
2
Pin Assignment
forlCC
GND...!... I '\
031rn
1,1i1l
~
IlliVcc
lrnilE2
1i1I1rn1rn1iil1i!l
c-
0215 01 1,00
'-'-l.
TL/F/I0239-3
TL/F/I0239-2
07
TL/F/I0239-1
Pin Names
OE1,OE2
10-17
00-0 7
Truth Table
Description
TRI·STATE Output Enable Inputs
Inputs
Outputs
Inputs
OE1
I
Outputs
(Pins 12, 14, 16, 18)
L
L
L
H
H
L
H
X
Z
Inputs
Outputs
(Pins 3, 5, 7, 9)
OE2
L
L
H
H~
L=
X=
Z=
6·4
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
L
H
X
H
L
Z
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Terminal Voltage
with Respect to GND (VTERM)
74FCT
54FCT
Supply Voltage (Vecl
54FCT
74FCT
-0.5Vt07.0V
-0.5V to 7.0V
Input Voltage
OV to Vee
Output Voltage
OV to Vee
Temperature under Bias (TSIAS)
74FCT
54FCT
-55'C to + 125'C
-65'Cto + 135'C
Operating Temperature (TA)
54FCT
74FCT
Storage Temperature (TSTG)
74FCT
54FCT
- 55'C to + 125'C
- 65'C to + 150'C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (PT)
4.5Vto 5.5V
4.75V to 5.25V
- 55'C to + 125'C
- O'C to + 70'C
175'C
140'C
0.5W
120mA
DC Output Current (lOUT)
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. The databook specifications
should be met, without exception, to ensure that the system design is
reli~
able over its power supply, temperature, and output/input loading variables.
DC Characteristics for 'FCr Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ±10%, TA = -55'C
to + 125'C, VHe = Vee - 0.2V.
Symbol
54FCT174FCT
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
2.0
V
0.8
V
Input High Current
5.0
5.0
/LA
IlL
Input Low Current
-5.0
-5.0
/LA
loz
Maximum TRI-STATE Current
10.0
10.0
-10.0
-10.0
/LA
-1.2
V
VIK
Clamp Diode Voltage
los
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
VOL
lee
alee
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
Conditions
Units
Max
-0.7
mA
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Max
Vo
Vo
Vo
Vo
= Vee
= 2.7V (Note 2)
= 0.5V (Note 2)
= GND
Vee = Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2Vor VHe; 10H = -32/LA
V
Vee = Min
VIN = VIH or VIL
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
0.001
1.5
mA
Vee = Max
VIN ;;: VHe, VIN :s; 0.2V
II = 0
0.5
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
6·5
10H = -300/LA
IOH = -12 mA (Mil)
10H = -15 mA (Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300 /LA
V
Vee = Min
VIN = VIH or VIL
10L = 300 /LA
IOL = 48 mA (Mil)
10L = 64 mA (Com)
DC Characteristics for 'FCT Family Devices
(Continued)
Typical values are at Vee = 5.0V, 25°C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O°C to + 70°C; Mil: Vee = 5.0V ± 10%, TA = -55°C
to + 125°C, VHe = Vee - 0.2V.
Symbol
74FCT
Parameter
MIn
leeD
Ie
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
UnIts
Typ
Max
0.25
0.55
1.5
5.0
1.B
6.0
mA/MHz
Conditions
Vee = Max
Outputs Open
OEA = OEs = GND
One Input Toggling
50% Duty Cycle
Vee = Max
Outputs Open
OEA = OEs = GND
fl = 10MHz
One Bit Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
mA
3.0
B.O
5.0
14.5
(Note 5)
Vee = Max
Outputs Open
OEA = OEs = GND
fl = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven Input (VIN = 3.4V); all other inputs at Vee or GND.
Note 4: This parameter Is not directly testable, but Is derived lor use In Total Power Supply calculations.
Note 5: Values lor these conditions are examples 01 the lee lormula. These limits are guaranteed but not tested.
Note 6: Ic = 10UIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + alcc DHNT + ICCD (lcp/2 + II NI)
Icc = Quiescent Current
alcc = Power Supply Current lor a TTL High Input (VIN
DH = Duty Cycle lor TTL Inputs High
NT = Number 01 Inputs at DH
= 3.4V)
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero lor Non-Register Devices)
II = Input Frequency
NI = Number 01 Inputs at II
All currents are milliamps and all Irequencles are in megahertz.
Note 7: For 54FCT, ICCD = 0.40 mA/MHz.
Reier to applicable standard military drawing or NSC Table I lor test conditions and Ic/lcc limits.
6·6
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
Symbol
54FCT/74FCT
74FCT
54FCT
TA = +25'C
Vee = 5.0V
TA, Vee = Com
Rl = 500n
Cl = 50pF
TA, Vee = Mil
Rl = 50 on
Cl = 50pF
Parameter
tpLH
tpHL
Propagation Delay
Onto On
tpZH
tpZL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
See Section 2 for Waveforms
Symbol
+ 25'C, f
=
Parameter (Note)
Fig.
No.
Typ
Min
(Note 1)
Max
Min
Max
5.0
1.5
8.0
1.5
9.0
ns
2·8
7.0
1.5
10.0
1.5
10.5
ns
2·11
6.0
1.5
9.5
1.5
12.5
ns
2·11
Note 1: Minimum limits are guaranteed but not tested on propagation delays.
Capacitance TA =
Units
1.0 MHz
Condition
Typ
Max
Units
CIN
Input Capacitance
6
10
pF
VIN
COUT
Output Capacitance
8
12
pF
VOUT
Note: This parameter is measured at characterization but not tested.
COUT for 74FCT only.
6·7
= OV
= OV
.- r----------------------------------------------------------------------------,
~
~National
~ semiconductor
54FCT/74FCT241
Octal Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The 'FCT241 is an octal buffer and line driver designed to
be employed as a memory address driver, clock driver and
bus-oriented transmitter or receiver which provides improved PC board density.
• NSC 54FCT174FCT241 is pin and functionally equivalent to lOT 54FCT/74FCT241
• Non-inverting TAl-STATE outputs drive bus lines or
buffer memory address registers
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 64 rnA (Com), 48 rnA (Mil)
• CMOS power levels
• ESO immunity ~ 4 kV typical
• Military product compliant to MIL-STO 883
FACTTM FCT utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCT features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
Pin Assignment
forLCC
.~
I!lIlH!] rn [!J
Orl
1
2
IJ"""i
.r~ '-'-L
.r~
'-'-L
12~
.r~ '-'-L
13~
.r~70
04~
11~
056"
O:~I>04
v
Is
Os
16
06
17
O's
GIIO---
~
'-'-L
~
13 0 6 12 05 11
~v
19 cc
~rnllm'.
OE2
18 0
17 0
16 14
15 0 1
14 15
13 O2
12 16
GIIOIii!I
171!il
mlo
mOr1
03~
~Vcc
16 Ii}]
Ii!IOE2
1Bl1lID1lID1iZl1lID
O2 15 0 1 14 0 0
II 0 3
~
TL/F/I0659-3
TLlF/I0659-2
TLlF/I0659-1
Truth Tables
Pin
Names
Description
OE1,
OE2
10- 17
0 0- 0 7
TAl-STATE Output Enable Input
TAl-STATE Output Enable Input (Active HIGH)
Inputs
Outputs
Inputs
Outputs
(Pins 12, 14, 16, 18)
L
L
H
L
H
X
L
H
Z
Inputs
H
H
L
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
6-8
Outputs
(Pins 3, 5, 7, 9)
L
H
X
L
H
Z
x ~ Immaterial
Z = High Impedance
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Terminal Voltage with Respect to GND (VTERM)
-0.5Vt07.0V
74FCT
54FCT
-0.5V to 7.0V
Temperature under Bias (TBIAS)
74FCT
-55'C to + 125'C
54FCT
- 65'C to + 135'C
Storage Temperature (TSTG)
74FCT
-55'Cto + 125'C
54FCT
-65'C to + 150'C
Power Dissipation (Pr)
0.5W
120mA
DC Output Current (lOUT)
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Exposure to absolute maximum rating conditions
lor extended periods may allect reliability. The databook specifications
should be met, without exception, to ensure that the system design is reli·
Supply Voltage (Vee!
54FCT
74FCT
Input Voltage
Output Voltage
Operating Temperature (TA)
54FCT
74FCT
Junction Temperature (TJ)
CDIP
PDIP
4.5Vto 5.5V
4.75V to 5.25V
OVtoVee
OV to Vee
- 55'C to + 125'C
-O'Cto +70'C
175'C
140'C
able over its power supply, temperature, and output/Input loading Yariables.
DC Characteristics for 'FCT Family Devices
Typical values are at Vee = 5.0V. 25'C ambient and maximum loading. For test conditons shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ±10%, TA = -55'C
to + 125'C, VHe = Vee - 0.2V
Symbol
54FCT174FCT
Parameter
Min
VIH
Minimum High Level
Input Voltage
Vil
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
,.A
III
Input Low Current
-5.0
-5.0
p.A
10Z
Maximum TRI·STATE Current
10.0
10.0
-10.0
-10.0
VIK
Clamp Diode Voltage
los
Short Circuit Current
VOH
Minimum High Level
Output Voltage
VOL
Icc
Alec
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TIL Inputs HIGH
-0.7
-60
Conditions
Max
-1.2
-120
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Max
Va
Va
Va
Va
,.A
V
mA
=
=
=
=
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
Vee = Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
2.8
3.0
Vee = 3V; VIN = 0.2V or VHe; 10H = -32 p.A
VHe
2.4
2.4
Vee
4.3
4.3
Vee = Min
VIN = VIH or Vil
V
Vee = 3V; VIN = 0.2V or VHe; 10l = 300 p.A
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
0.001
1.5
mA
Vee = Max
VIN ~ VHe, VIN ,,; 0.2V
fl = 0
0.5
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
6·9
10H = -300 p.A
10H = -12 mA (Mil)
IOH = -15 mA (Com)
V
Vee = Min
VIN = VIH or Vil
IOl = 300 p.A
IOl = 48 mA (Mil)
IOl = 64 mA (Com)
.r----------------------------------------------------------------------------------------------,
-=r
N
DC Characteristics for 'FCT Family Devices (Continued)
Typical values are at Vcc = 5.0V, 25·C ambient and maximum loading. For test conditons shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ± 5%, TA = O·C to + 70"C; Mil: Vee = 5.0V ± 10%, TA = -55·C
to + 125·C, VHC = Vee - 0.2V
Symbol
74FCT
Parameter
Min
ICCD
Ic
Typ
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
mA/MHz
Vec = Max
Outputs Open
OEA = OEe = GND
One InputToggling
50% Duty Cycle
0.25
0.55
1.5
5.5
Vec = Max
Outputs Open
OEA = OEe = GND
1.8
6.0
11=10MHz
One Bit Toggling
50% Duty Cycle
mA
Input Hysteresis
on Clock Only
Conditions
Units
Max
3.0
9.0
(Note 5)
Vce = Max
Outputs Open
OEA = OEe = GND
5.0
14.5
II = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
200
mV
Note 1: Maximum lesl duralion nollo exceed one second, nol more Ihan one oulpul shorted alone time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven input (VIN
= 3.4V); all other inputs at Vcc or GND.
Note 4: This parameter is not directly testable, but Is derived lor use In Total Power Supply calculations.
Note 5: Values lor these condHions are examples 01 the Icc lormula. These limits are guaranteed but not tested.
Note 6: IC = laulESCENT + IINPUTS + IDYNAMIC
IC = ICC + alCC DHNT + ICCD (ICp/2 + II NI)
ICC =. Quiescent CUrrent
alcc = Power Supply Current lor a TTL High Input (VIN = 3.4V)
DH = Duty Cycle lor TTL Inputs High
NT = Number 01 Inputs at DH
ICCD = Dynamic Current Ceused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero lor Non-Register Devices)
II = Input Frequency
NI = Number 01 Inputs at II
All currents are in milliamps and all frequencies are in megahertz.
Note 7: For 54FCT, ICCD = 0.40 mA/MHz.
Reier 10 applicable standard milHary drawing or NSC Table I lor test condHions and Iclicc limits.
6-10
VIN = 3.4V
VIN = GND
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
Symbol
S4FCT174FCT
74FCT
S4FCT
TA = +2S'C
Vee = S.OV
TA. Vee = Com
Rl = soon
Cl = SOpF
TA. Vee = Mil
Rl = soon
Cl = SOpF
Parameter
Propagation Delay
tpLH
tpHL
DntoOn
tPZH
tpzL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
See Section 2 for Waveforms
Symbol
(TA
=
+25'C,f
=
Parameter (Note)
Min (Note 1)
Max
Min
Max
4.0
1.5
6.5
1.5
9.0
ns
2-8
5.5
1.5
8.0
1.5
12.5
ns
2-10
4.5
1.5
7.0
1.5
11.5
ns
2-10
1.0 MHz)
Typ
Max
Units
CIN
Input Capacitance
6
10
pF
VIN
COUT
Output Capacitance
8
12
pF
VOUT
Note: This parameter is measured at characterization but not tested.
COUT
Fig.
No.
Typ
Note 1: Minimum limits are guaranteed but not tested on propagation delays.
Capacitance
Units
for 74FCT only.
6-11
Conditions
= OV
= OV
~National
~ semiconductor
54FCT /7 4FCT244
Octal Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
Tl)e 'FCT244 is an octal buffer and ,line driver designed to
be employed as a memory address driver, clock driver and
bus-oriented transmitter/receiver which provides improved
PC board density.
• NSC 54FCT174FCT244 is pin and functionally equivalent to lOT 54FCT174FCT244
• Controlled output edge rates and undershoot for improved noise immunity. Internal split ground for improved noise immunity
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOl = 64 mA (commercial) and 48 mA (military)
• CMOS power levels
• ESO immunity ;;, 4 kV typ
• Military product compliant to MIL-ST0883C and standard military drawing #5962-87630
FACTTM FCT utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCT and GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance.
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEEIIEC
Pin Assignment
for DIP, Flatpak and SOIC
Pin Assignment
forLCC
~
13 06 12 05 11
IOllllornm
0E1
1
•...!3
10
o.-~
11-t
05-;
12~
Oe~
13~
07~
~:~N
V
I>
15
04
Os
16
06
'"
°7
GND"""""
~ -'-L
.r~ -'-L
.r~ -'-L
.r~ -'-L
.,..;-
~V
19 cc
18
O~
°700
17 0 0
16 I,
GNDIilil
171il1
15 °1
°31i11
161m
14 IS
13 °2
12 Ie
10-17
00-0 7
~
;::;~1iID1m1i1l-:--
-;:::.,
OJ0E 1
Ii.iiIVcc
IiIDO~
02 15 01 I, 0 0
11 03
17
TL/F/l0240-3
Truth Tables
Inputs
OEl,0E2
t1I
rn04
[Illo
TL/F/l0240-2
TL/F/l0240-1
Pin Names
~
F
Outputs
(Pins 12, 14, 16, 18)
Description
TRI-STATE Output Enable Inputs
Inputs
Outputs
L
L
H
L
H
X
L
H
Z
Outputs
(Pins 3, 5, 7, 9)
Inputs
L
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
6-12
L
H
X
L
H
Z
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee!
54FCT
74FCT
Terminal Voltage with Respect to GND (VTERM)
-0.5V to 7.0V
54FCT
-0.5Vt07.0V
74FCT
Input Voltage
OV to Vee
Output Voltage
OVtoVee
Temperature under Bias (T BIAS)
74FCT
54FCT
- 55'C to + 125'C
-65'Cto + 135'C
Storage Temperature (Tsm)
74FCT
54FCT
Operating Temperature (TA)
54FCT
74FCT
-55'Cto + 125'C
- 65'C to + 150'C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (Pr)
0.5W
4.5Vto 5.5V
4.75V to 5.25V
-55'C to + 125'C
-O'Cto +70'C
175'C
140'C
DC Output Current (lOUT)
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. The databook specifications
should be met, without exception, to ensure that the system design is reli-
able over its power supply. temperature. and outpUt/input loading variables.
DC Characteristics for 'FCT Family Devices
Typical values are at Vee = 5.0V. 25'C ambient and maximum loading. For test conditons shown as Max, use the value
specilied lor the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ±10%, TA = -55'C
to + 125'C, VHe = Vee - 0.2V
Symbol
54FCT174FCT
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Conditions
Units
Max
2.0
V
0.8
V
Input High Current
5.0
5.0
",A
IlL
Input Low Current
-5.0
-5.0
",A
102
Maximum TRI-STATE Current
10.0
10.0
-10.0
-10.0
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Max
Vo
Vo
Vo
Vo
",A
= Vee
= 2.7V (Note 2)
= 0.5V (Note 2)
= GND
Clamp Diode Voltage
lOS
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
Vee = 3V; VIN = 0.2Vor VHe; 10H = -32 ",A
Vee
4.3
4.3
Vee = Min
VIN = VIH or VIL
lee
alee
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
VHe
2.4
2.4
-1.2
VI = Vee
VI = 2.7V (Note 2)
VIK
VOL
-0.7
Vee = Max
V
mA
V
Vee = Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
0.001
1.5
rnA
Vee = Max
VIN ~ VHe, VIN ,;; 0.2V
II = 0
0.5
2.0
rnA
Vee = Max
VIN = 3AV (Note 3)
6-13
10H = -300 ",A
10H = -12 mA (Mil)
10H = -15 mA (Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300 ",A
V
Vee = Min
VIN = VIH orVIL
10L = 300 ",A
48 rnA (Mil)
10L = 64 mA (Com)
ioL =
DC Characteristics for 'FCT Family Devices (Continued)
Typical values are at Vee = 5.0V, 25°C ambient and maximum loading. For test conditons shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O°C to + 70°C; Mil: Vee = 5.0V ± 10%, TA = -55°C
to + 125°C, VHe = Vee - 0.2V
Symbol
74FCT
Parameter
Min
leeD
Ie
Typ
Units
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
Conditions
Max
0.15
0.55
1.5
5.5
1.8
6.0
mA/MHz
Vee = Max
Outputs Open
OEl = OE2 = GND
One Input Toggling
50% Duty Cycle
Vee = Max
Outputs Open
OEl = OE2 = GND
f, = 10MHz
mA
Input Hysteresis
on Clock Only
One Bit Toggling
50% Duty Cycle
3.0
9.0
(Note 5)
Vee = Max
Outputs Open
OEl = OE2 = GND
5.0
14.5
f, = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
mV
200
Note 1: Maximum tesl duration not to exceed one second, not more Ihan one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven Inpul (V,N = 3.4V); all other Inputs al Vcc or GND.
Note 4: This parameter Is not directly lestable, bulls derived lor use In Total Power Supply calculations.
Note 5: Values lor these conditions are examples 01 the ICC lormula. These limits are guaranleed but nol tested.
Note 8: IC = IQUIESCENT + I,NPUTS + IDYNAMIC
IC = ICC + alCC DHNT + loco (lcp/2 + I, N,)
IOC = Quiescent Current
alcc = Power Supply Current lor a TTL High Input (Y,N = 3.4V)
DH = Duly Cycle for TTL Inputs High
NT = Number of Inputs at DH
loco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency for Register Devices (Zero for Non·Reglster Devices)
I, = Input Frequency
N, = Number 01 Inputs al f,
All currents are In milliamps and all frequencies are In megahertz.
Note 7: For 54FCT, ICCD = 0.40 rnA/MHz.
Reier to applicable standard military drawing or NSC Table I Icr test conditions and Icllcc limits.
6·14
Y,N = 3.4V
Y,N = GND
Y,N = S.4V
Y,N = GND
AC Electrical Characteristics:
Symbol
74FCT
54FCT
TA = +25'C
Vee = 5.0V
TA. Vee = Com
Rl = 500n
Cl = 50pF
TA. Vee = Mil
Rl = 500n
Cl = 50 pF
Parameter
tpLH
tpHL
Propagation Delay
On to On
tpZH
tPZL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
See Section 2 for Waveforms
54FCT174FCT
Symbol
Min (Note 1)
Max
Min
Max
4.5
1.5
6.5
1.5
9.0
ns
2-8
6.0
1.5
8.0
1.5
10.5
ns
2-11
5.0
1.5
7.0
1.5
12.5
ns
2-11
(TA = + 25'C, f = 1.0 MHz)
Parameter (Note)
Fig.
No.
Typ
Note 1: Minimum limits are guaranteed but not tested on propagation delays.
Capacitance
Units
Typ
Max
Units
CIN
Input Capacitance
6
10
pF
VIN = OV
Cour
Output Capacitance
8
12
pF
Your = OV
Note: This parameter is measured at characterization but not tested.
eOUT for 74FCT only.
6-15
Conditions
Ln
~
r--------------------------------------------------------------------------------,
~National
~ Semiconductor
54FCT/7 4FCT245
Octal Bidirectional Transceiver
with TRI-STATE® Inputs/Outputs
General Description
Features
The 'FCT245 contains eight non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus-oriented applications. The Transmit/Receive (TfR) input determines the direction of data flow through the bidirectional
transceiver. Transmit (active-HIGH) enables data from A
ports to B ports; Receive (active-LOW) enables data from B
ports to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition.
• NSC54FCT174FCT245 is pin and functionally equivalent
to IDT54FCTf74FCT245
• Controlled output edge rates and undershoot for improved noise immunity. Internal split ground for improved noise immunity.
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 64 mA (commercial) and 48 mA (military)
• CMOS power levels
• ESD immunity ~ 4 kV typ
• Military product compliant to MIL-STD 883 and Standard Military Drawing #5962-87629
FACTTM FCT utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCT features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEEflEC
Pin Assignment
for DIP, Flatpak and SOIC
...! ~ )''C/rO::
T/R
2
L
3
Pin
Names
Description
17
5
16
6
15
7
14
8
13
Output Enable Input
Transmit/Receive Input
Side A TRI-STATE
Inputs orTRI-STATE
Outputs
Side B TRI-STATE
Inputs orTRI-STATE
Outputs
9
12
.!!!I
11
A3
A4
83
84
8s
As
86
87
GND
A6
A7
18
4
TL/F/10241-1
81
82
~
1!
82
83
84
8s
86
87
TLlF/10241-3
TUF/10241-2
Truth Table
Inputs
OE
T/R
L
L
H
L
H
X
Pin Assignment
for LCC and PCC
Outputs
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A,A5,,
54FCT
74FCT
Input Voltage
Output Voltage
Operating Temperature (TA)
54FCT
74FCT
Junction Temperature (TJ)
CDIP
PDIP
U1
4.5Vt05.5V
4.75V to 5.25V
OVtoVee
OVtoVee
- 55·C to + 125·C
O·Cto +70·C
175·C
140·C
DC Characteristics for 'FCT Family Devices
Typical values are at Vee = 5.0V, 25·C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ± 5%, TA = O·C to + 70·C; Mil: Vee = 5.0V ± 10%, TA = -55·C
to + 125·C, VHe = Vee - 0.2V.
Symbol
54FCT174FCT
Parameter
Min
Typ
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
0.8
V
IIH
Input High Current
(except 1/0 Pins)
5.0
5.0
p.A
Input High Current
15
15
p.A
IIH
2.0
V
(110 Pins Only)
IlL
Input Low Current
(except 1/0 Pins)
-5.0
-5.0
p.A
IlL
Input Low Current
(110 Pins Only)
-15
-15
p.A
loz
Maximum TRI-STATE Current
10.0
10.0
-10.0
-10.0
p.A
VIK
Clamp Diode Voltage
los
Short Circuit Current
VOH
Minimum High Level
Output Voltage
VOL
Maximum Low Level
Output Voltage
-0.7
-60
Conditions
Units
Max
-1.2
-120
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
V
mA
V
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
6-17
V
Vee
= Max
Vee
= Max
Vee
= Max
Vee
= Max
Vee
= Max
= Vee
= 2.7V (Note 2)
VI = Vee
VI = 2.7V (Note 2)
VI = 0.5V (Note 2)
VI = GND
VI = 0.5V (Note 2)
VI = GND
VI = Vee
VI = 2.7V (Note 2)
VI = 0.5V (Note 2)
VI = GND
VI
VI
= Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2V or VHe; 10H = -32 p.A
10H = - 300 p.A
Vee = Min
10H = -12 mA (Mil)
VIN = VIH or VIL
10H = -15mA(Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300 p.A
Vee = Min
10L = 300 p.A
10L = 48 mA (Mil)
VIN = VIH orVIL
10L = 64 mA (Com)
Vee
DC Characteristics for 'FCT Family Devices
(Continued)
Typical values are at Vcc = 5.0V, 25"C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O"C to +70"C; Mil: Vc;c = 5.0V ±10%, TA = -55"C
to + 125"C, VHC = Vee - 0.2V.
Symbol
74FCT
Parameter
Min
Icc
alee
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
ICCD
Ic
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
Units
Conditions
Typ
Max
0.001
1.5
mA
Vee = Max
VIN :;;: VHC, VIN ~ 0.2V
fl = 0
0.5
2.0
mA
Vcc = Max
VIN = 3.4V (Note 3)
0.25
0.40
mA/MHz
1.5
1.8
Vee = Max
Outputs Open
OEA = OEB = GND
. One InputToggling
50% Duty Cycle
VIN:;;: VHC
VIN ~ 0.2V
4.5
VCC = Max
Outputs Open
T/R = OE = GND
VIN:;;: VHC
VIN ~ 0.2V
5.0
fl = 10 MHz
One BitToggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
(Note 5)
Vee = Max
Outputs Open
T/R = OE = GND
VIN:;;: VHC
VIN ~ 0.2V
fl = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
mA
3.0
10.0
5.0
14.5
Input Hysteresis
200
mV
on Clock Only
Nole 1: Maximum test duration not to exceed one second. not more than one output shorted at one time.
Nole 2: This parameter guaranteed but not tested.
Nole 3: Per TTL driven Input (YIN = 3.4V); all other inputs at Vce or GND.
Note 4: This parameter is not directly testable, but is derived lor use in Total Power Supply calculations.
Nole 5: Values lor these conditions are examples of the Ice lormula These limits are guaranteed but not tested.
Nole 6: Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = IcC + Alce DHNT + ICCD (lcp/2 + II NI)
Icc = Quiescent Current
Alce = Power Supply Current lor a TTL High Input (YIN = 3.4V)
DH = Duty Cycle lor TTL Inputs High
NT = Number of Inputs at DH
IceD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency for Ragister Devices (Zero for Non-Register Devices)
II = Input Frequency
NI = Number of Inputs al II
All currents are milliamps and all frequencies are In megahartz.
Note 7: For 54FCT, lceo = 0.40 rnA/MHz.
Refer to applicable standard military drawing or NSC Table I lor test conditions and Icllce IimHs.
VH
6-18
AC Electrical Characteristics:
Symbol
See Section 2 for Waveforms
S4FCT174FCT
74FCT
S4FCT
TA = +2S'C
Vee = S.OV
TA.Vee = Com
RL = soon
CL = SOpF
TA. Vee = Mil
RL = soon
CL=SOpF
Parameter
Units
Fig.
No.
Typ
Min (Note)
Max
Min
Max
tpLH
tpHL
Propagation Delay
Ato B, BtoA
5.0
1.5
7.0
1.5
7.5
ns
2·8
tPZH
tpZL
Output Enable Time
OEtoAorB
6.0
1.5
9.5
1.5
10.0
ns
2·8
tpHZ
tpHL
Output Disable Time
OEtoAorB
6.0
1.5
7.5
1.5
10.0
ns
2-11
tPZH
tPZL
Output Enable Time
T/RtoAorB
6.0
1.5
9.5
1.5
10.0
ns
2-11
tpHZ
tpLZ
Output Enable Time
T/R to A or B
6.0
1.5
7.5
1.5
10.0
ns
2-11
Note: Minimum limits guaranteed but not tested on propagation delays.
Capacitance TA =
Symbol
+ 25'C, f = 1.0 MHz
Parameter (Note)
Typ
Max
Units
CIN
Input Capacitance
6
10
pF
VIN = OV
Conditions
COUT
Output Capacitance
8
12
pF
VOUT = OV
Note: This parameter is measured at characterization but not tested.
COUl for 74FCT245 only.
•
6-19
~National
~ semiconductor
54FCT17 4FCT273
Octal D Flip-Flop
General Description
Features
The 'FCT273 has eight edge-triggered Ootype flip-flops with
Individual 0 Inputs and a outputs. The common buffered
Clock (CP) and Master Reset (MR) Input load and reset
(clear) all flip-flops simultaneously.
The register Is fully edge-triggered. The state of each 0 input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's a output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
•
•
•
•
•
•
•
•
Ideal buffer for MaS microprocessor or memory
Eight edge-triggered 0 flip-flops
Buffered common clock
Buffered, asynchronous master reset
TIL input and output level compatible
TIL levels accept CMOS levels
IOL = 48 mA (Com), 32 mA (Mil)
NSC 54174FCT273 is pin and functionally equivalent to
lOT 54174FCT273
Ordering Code: See Section 8
Connection Diagrams
Logic Symbols
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIIEC
Mii
CP
CP
MR
20
Do
0,
O2
TLlF/l0146-1
Vee
00
07
0,
O2
06
~
03
04
03
06
04
05
Os
06
Os
06
Os
04
~
04
~
TL/F/l0146-2
TLlF/l0146-3
Pin Names
00-0 7
MR
CP
00-0 7
Description
Pin Assignment
forLCC
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
~~020,0,
[]]!Ll[]][§]11l
1Bi@]1i]]1iII1i]]
DsOsOsDe~
TL/F/l0146-4
6-20
Mode Select-Function Table
Inputs
Operating Mode
MR
CP
Reset (Clear)
L
X
Load '1'
H
Load '0'
H
...r
...r
Outputs
On
X
an
H
H
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
../" = LOW-to-HIGH Transition
Logic Diagram
CP
ilii
0,
°2
0,
0,
TUF/'O'46-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
6-21
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Terminal Voltage with Respect to GND
(VTERM)
54FCT
74FCT
Supply Voltage (Vecl
54FCT
74FCT
-0.5to +7.0V
-0.5 to +7.0V
Input Voltage
OV to Vee
Output Voltage
OV to Vee
Temperature Under Bias (TBIAS)
74FCT
54FCT
- 55'C to + 125'C
-65'C to + 135'C
Operating Temperature (T;J
54FCT
74FCT
Storage Temperature (Tsm)
74FCT
54FCT
-55'Cto +125'C
-65'C to + 150'C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (PT)
4.5Vt05.5V
4.75 to 5.25V
- 55'C to + 125'C
O'Cto +70'C
175'C
140'C
0.5W
DC Output Current (lOUT)
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTTM FeT circuits outside databook specifications.
DC Characteristics for 'FCr Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ± 10%, TA = -55'C
to + 125'C, VHe = Vee - 0.2V
Symbol
54FCT174FCT
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
Conditions
Max
2.0
V
0.8
V
Input High Current
5.0
5.0
p.A
IlL
Input Low Current
-5.0
-5.0
p.A
VIK
Clamp Diode Voltage
los
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
-0.7
-1.2
V
mA
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2V or VHe;
10L = 300 p.A
V
6-22
Vee = Min
VIN = VIH or VIL
10H = -300 p.A
10H = -12mA(Mil)
10H = -15 mA (Com)
DC Characteristics for 'FCT Family Devices (Continued)
Typical values are at Vee = 5.0V, 25·C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vee = 5.0V ±5%, TA = O·C to +70·C; Mil: Vee = 5.0V ±10%, TA = -55·C
to + 125·C, VHe = Vee - 0.2V
Symbol
Parameter
54FCT174FCT
Min
VOL
lee
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
.:llee
Quiescent Supply Current;
TTL Inputs HIGH
leeD
Dynamic Power
Supply Current (Note 4)
Input Hysteresis
on Clock Only
Ie
Total Power
Supply Current (Note 6)
GND
0.2
GND
0.3
0.3
0.2
0.5
0.5
V
0.001
1.5
mA
Vee = Max
VIN ~ VHe, VIN ,;; 0.2V
II = 0
0.5
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
mA/MHz
Vee Max
Outputs Open
MR = Vee
One Input Toggling
50% Duty Cycle
0.40
Vee = 3V; VIN = 0.2V or VHe;
IOL = 300 ",A
Input Hysteresis on Clock Only
Vee = Min
VIN =VIHorVIL
IOL = 300 ",A
IOL = 48 mA (Mil)
IOL = 64 mA (Com)
VIN ~ VHe
VIN';; 0.2V
VIN';; 0.2V
mV
200
1.5
4.0
Vee = Max
Outputs Open
MR = Vee
VIN ~ Vee
VIN';; 0.2V
1.8
6.0
II = 10MHz
One Bit Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
3.0
7.8
(Note 5)
Vce = Max
Outputs Open
MR = Vee
VIN ~ VHe
VIN';; 0.2V
5.0
16.8
II = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
mA
VH
Conditions
Max
0.25
VH
Units
Typ
200
mV
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TIL driven input (VIN = 3.4V); all other inputs al Vee or GND.
Note 4: This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Note 5: Values lor these conditions are examples 01 the Icc lormula. These limits are guaranteed but not lested.
Note 6: Ic = 10UIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + dlCC DHNT + ICCD (lcp/2 + II NI)
Icc = Quiescent Current
dlCC = Power Supply Curent lor a TIL High Input (VIN = 3.4V)
DH = Duly Cycle lor TIL Inputs High
NT = Number 01 Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero lor Non-Register Devieas)
fl = Input Frequency
NI = Number 01 Inputs at II
All currents are In milliamps and all Irequencies are in megahertz.
6-23
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
S4FCT174FCT
74FCT
S4FCT
TA = +2S·C
Vee = S.OV
TA. Vee = Com
RL = soon
CL = SOpF
TAo Vee = Mil
RL = soon
CL = SOpF
Min
Units
Fig.
No.
Typ
Min
Max
tpHL
tpLH
Propagation Delay
Clock to Output
7.0
2.0
13.0
ns
2-8
tpLH
tpHL
Propagation Delay
MR to Output
8.0
2.0
13.0
ns
2·8
tsu
Setup TIme HIGH
or LOW Data to CP
3.0
3.0
ns
2·10
th
Hold Time HIGH
or LOW Data to CP
1.0
2.0
ns
2·10
tw
Clock Pulse Width
!"iIGHorLOW
4.0
7.0
ns
2·9
Iw
MR Pulse Width
H!GHorLOW
4.0
7.0
ns
2·9
tree
Recovery Time
MRtoCP
3.0
4.0
ns
2·10
Note 1: Minlm~m limits !"" guaranteed but not tested on Propagation Delays.
CapaC!~anCe TA = 25·C. f
Symbol
Parameter
CrN
Input Capacitance
CoUT
Output Capacitance
= 1.0 MHz
Conditions
Typ
Max
Unit
= OV
VOUT = OV
6
10
pF
8
12
pF
VIN
Note: This paramete~ ,is guaranteed by characterization data and not tested.
6·24
Max
r----------------------------------------------------------------------------, ....
(0)
(0)
~National
~ Semiconductor
54FCT17 4FCT373
Octal Transparent Latch with TRI-STATE® Outputs
General Description
Features
The 'FCT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH, the bus output is in the
high impedance state.
• NSC 54FCT174FCT373 is pin and functionally equivalent to IDT 54FCT174FCT373
• Controlled output edge rates and undershoot for improved noise immunity. Internal split ground for improved noise immunity
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 mA (commercial) and 32 mA (military)
• CMOS power levels
• ESD immunity ~ 4 kV typ
• Military product compliant to MIL-STD 883 and
standard military drawing #5962-87644
FACT FCT utilizes NSC quiet series technology to provide
improved quiet output switching and dynamic threshold performance.
FACT FCT features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
TLIFll0242-1
Of
Of
Vee
LE
00
DO
°7
07
01
06
DO
°0
01
°1
O2
°2
°1
06
°2
O2
°5
05
03
°3
04
°4
03
05
06
°5
03
°6
GNO
07
°7
04
9
12
°4
10
11
LE
TLlFll0242-3
TLlFll0242-2
Pin Names
Description
Pin Assignment
forLCC
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch Outputs
~~0201Dl
[ID[l][ID[§][!]
G~~~O~~~
LE [jJ
04 jgJ
[i]
DE
gQ) Vee
lim 07
D4 1rn
1iJ]1i]Ifi]J1ill1im
Ds°506D6~
TLlFll0242-4
6-25
~
l:;
r-------------------------------------------------------------------------------------,
Functional Description
Truth Table
The 'FCT373 contains eight D-type latches with TRI-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance mode
but this does not interfere with entering new data into the
latches.
Inputs
Outputs
LE
OE
On
On
X
H
L
L
L
X
Z
L
H
On
H
H
L
L
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
On = PrevIous On before HIGH to Low lransition of Latch Enable
Logic Diagram
TUF/l0242-5
Please notelhatlhis diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
6-26
Absolute Maximum Rating
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
54FCT
74FCT
Terminal Voltage with Respect to GND (VTERM)
54FCT
-0.5V to + 7.0V
74FCT
-0.5Vto +7.0V
4.5Vt05.5V
4.75V to 5.25V
Input Voltage
Output Voltage
OVtoVcc
OVtoVee
Temperature under Bias (TBIAS)
74FCT
54FCT
-55·Cto + 125·C
-65·Cto + 135·C
Storage Temperature (TSTG)
74FCT
54FCT
Operating Temperature (TA)
54FCT
74FCT
-55·Cto + 125·C
-65·C to + 150·C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (Pr)
0.5W
DC Output Current (lOUT)
- 55·C to + 125·C
- O·C to + 70·C
175·C
140·C
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. The databook specifications
should be met, without exception, to ensure that the system design is reliable over its power supply. temperature, and output/input loading variables.
DC Characteristics for 'FCT Family Devices
Typical values are at Vee = 5.0V, 25·C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O·C to +70·C; Mil: Vee = 5.0V ±10%, TA = -55·C
to +125·C, VHe = Vee - 0.2V
Symbol
54FCT174FCT
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
".A
IlL
Input Low Current
-5.0
-5.0
".A
loz
Maximum TRI-STATE Current
10.0
10.0
-10.0
-10.0
VIK
Clamp Diode Voltage
los
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VOL
lee
Alee
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
-0.7
VHe
2.4
2.4
Conditions
Max
-1.2
Vee
4.3
4.3
Vee
=
Max
VI
VI
Vee
=
Max
VI
VI
Vee
=
Max
Vo
Vo
Vo
Vo
V
Vee
= Min; IN = -18 mA
mA
Vee
".A
V
=
Vee =
Max (Note 1); Vo
3V; VIN
=
= 3V; VIN =
Vee = Min
VIN = VIH or VIL
GND
0.2
0.2
0.50
0.50
0.001
1.5
rnA
Vee = Max
VIN ;;, VHe, VIN
fl = 0
0.5
2.0
rnA
Vee = Max
VIN = 3.4V (Note 3)
6-27
S;
0.5V (Note 2)
GND
=
=
Vee
2.7V (Note 2)
= 0.5V (Note 2)
= GND
GND
10H
10H
10H
GND
0.3
0.3
V
Vee
2.7V (Note 2)
0.2Vor VHe; 10H
Vee = Min
VIN = VIH or VIL
Vee
=
=
=
=
=
=
=
=
0.2V or VHe; 10L
10L
10L
10L
0.2V
=
=
=
=
-32".A
-300".A
-12mA(MiI)
-15 mA (Com)
=
300 p.A
300 p.A
32 mA (Mil)
48 mA (Com)
DC Characteristics for 'FCT Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vee = 5.0V ± 5%, T A = O'C to + 70'C; Mil: Vee = 5.0V ± 10%, T A = - 55'C
.
to + 125'C, VHe = Vee - 0.2V (Continued)
Symbol
74FCT
Parameter
Min
IceD
Ie
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
Units
Typ
Max
0.15
0.45
1.5
4.5
1.8
5.0
mA/MHz
Conditions
Vee = Max
Outputs Open
One Input Toggling
50% Duty Cycle
Vee = Max
Outputs Open
OE = GND
LE = Vee
mA
II = 10MHz
One Bit Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
(Note 5)
Input Hysteresis
on Clock Only
3.0
8.0
5.0
14.5
Vee = Max
Of; = GND
LE = Vce
II = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
200
mV
Not. 1: Maximum test duratloln not to exceed one second, not more than one output shorted at one time.
Not. 2: This parameter guaranteed but not tested.
Not. 3: Per TIL driven Input (YIN = 3.4V); all other Inputs at Vce or GND.
Not. 4: This parameter Is not directly testable, but Is derived lor use In Total Power Supply calculations.
Not. 6: Values lor these conditions are examples 01 the Icc lormula. These limits are guaranteed but not tested.
Note 6: Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (ICp/2 + II NI)
Ice = Quiescent Current
AlcC = Power Supply Current lor a TIL High Input (VIN
DH = Duly Cycle lor TIL Inputs High
= 3.4V)
NT = Number 01 Inputs at DH
IceD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero lor Non·Register Devices)
II = Input Frequency
NI = Number 01 Inputs at II
All currents are in milliamps and all Irequencies are in megahertz.
Note 7: For 54FCT, IceD = 0.40 mA/MHz.
Reier to applicable standard military drawing or NSC Table I for test conditions and Icllce limits.
6-28
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
54FCT174FCT
74FCT
54FCT
TA = +25°C
Vee = 5.0V
TA. Vee = Com
Rl = 500n
Cl = 50pF
TA. Vee = Mil
Rl = 500n
Cl = 50pF
Units
Fig.
No.
Typ
Min (Note 1)
Max
Min
Max
5.0
1.5
8.0
1.5
8.5
ns
2-8
7.0
1.5
12.0
1.5
13.5
ns
2-11
6.0
1.5
7.5
1.5
10.0
ns
2-11
Propagation Delay
LEtoOn
9.0
2.0
13.0
2.0
15.0
ns
2-8
Isu
Set Up Time High or Low
Onto LE
1.0
2.0
2.0
ns
2-10
tH
Hold Time High or Low
On to LE
1.0
1.5
3.0
ns
2-10
tw
LE Pulse Width
High or Low
5.0
6.0
6.0
ns
2-9
tpLH
tpHL
Propagation Delay
On to On
tpZH
tPZL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
tpLH
tpHL
Note 1: Minimum limits are guaranteed but not tested on propagation delays.
Capacitance TA =
+ 25°C, f
=
Typ
Max
Units
C'N
Input Capacitance
6
10
pF
V,N
COUT
Output Capacitance
8
12
pF
VOUT
Symbol
Parameter (Note)
10 MHz
Note: This parameter is measured at characterization but not tested.
COUT for 74FCT only.
6-29
Condition
=
OV
=
OV
~ ~--------------------------------------------------------------------------~
~
~National
~ Semiconductor
54FCT17 4FCT37 4
Octal D Flip-Flop with iRI-STATE® Outputs
General Description
Features
The 'FCT374 is a high-speed, low-power octal O.type flipflop featuring separate Ootype inputs for each flip-flop and
TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all
flip-flops.
FACTTM FCT utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCT features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
• NSC 54FCT174FCT374 is pin and functionally equivalent to lOT 54FCT174FCT374
• Controlled output edge rates and undershoot for improved noise immunity. Internal split ground for improved noise immunity
• Input clamp diodes to limit bus reflections
• TrL/CMOS input and output level compatible
• IOL = 48 mA (commercial) and 32 mA (military)
• CMOS power levels
• ESO immunity ~ 4kV typ
• Military product compliant to MIL-STO 883 and standard military drawing '" 5962-87628
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIIEC
OE
CP
CP
OE
TL/F/l0243-1
Do
00
01
°1
O2
°2
°3
OJ
04
05
20
Vee
2
19
07
~
06
01
°5
06
~
1
Do
°4
06
liE
00
01
06
05
O2
03
05
o.
°7
TLlF/l0243-3
TL/F/l0243-2
Pin Names
Oo-~
CP
OE
00-0 7
Description
Pin Assignment
forlCC
Oata Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
TRI-STATE Outputs
D3~0201Dl
---- --
IIll2llIlrnm
03
II!
GNDIi2I
!II Do
lIloo
CP(j]
IIlOE
0.1i1I
D.1iAI
IiiiIvee
1!ID°7
'-.-.
. . ..-..-,
. ............
...-v,
irnliIDli§llilIli§I
DsOsOsOs~
TLlF/l0243-4
6-30
Truth Table
Functional Description
The 'FCT374 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With
the Output Enable (OE) LOW, the contents of the eight flipflops are available at the outputs. When the OE' is HIGH, the
outputs go to the high impedance state. Operation of the
OE input does not affect the state of the flip-flops.
Inputs
H=
L=
X=
Z=
.../'
outputs
Dn
CP
OE
On
H
L
.../
.../
X
X
L
L
H
H
L
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
= LOW-to·HIGH Transition
Logic Diagram
TL/F/l0243-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagaUon delays.
6-31
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Terminal Voltage
with Respect to GND (VTERM)
54FCT
74FCT
Supply Voltage (Vee>
54FCT
74FCT
-0.5V to 7.0V
.,..0.5V to 7.0V
4.5Vt05.5V
4.75V to 5.25V
Input Voltage
OVtoVee
Output Voltage
OVtoVee
Temperature under Bias (TBIAS)
74FCT
54FCT
- 55°C to + 125°C
-65°C to + 135°C
Operating Temperature (TAl
54FCT
74FCT
Storage Temperature (TSTG)
74FCT
54FCT
- 55°C to + 125°C
-65°C to + 150°C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (Pr)
- 55°C to + 125°C
O"Cto +70°C
175°C
140"C
0.5W
DC Output Current (lOUT)
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the davies may occur. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. The databook specifications
should be met, without exception, to ensure that the system design is
reli~
able over Its power supply, temperature, and output/input loading variables.
DC Characteristics for 'FCT Family Devices
Typical values are at Vee = 5.0V, 25°C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O"Cto +70"C; Mil: Vee = 5.0V ±10%, TA = -55"C
to + 125°C, VHe = Vee - 0.2V.
Symbol
54FCT174FCT
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
/LA
IlL
Input Low Current
-5.0
-5.0
/LA
loz
Maximum TRI-STATE Current
VIK
Clamp Diode Voltage
los
Short Circuit Current
VOH
Minimum High Level
Output Voltage
VOL
lee
Alec
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
10.0
10.0
-10.0
-10.0
-0.7
-60
Conditions
Max
-1.2
-120
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
Vee
=
Max
VI
VI
Vee
=
Max
VI
VI
Vee
=
Max
Vo
Vo
Vo
Vo
/LA
V
mA
V
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
=
=
=
=
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
= Min; IN = -18 mA
VCe = Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2Vor VHe; 10H = -32/LA
Vee = Min
10H = - 300 /LA
10H = -12 mA (Mil)
VIN = VIH or VIL
10H = -15 mA (Com)
Vee
=
GND
0.2
Vee
GND
0.3
0.3
0.2
0.50
0.50
V
Vee = Min
VIN = VIH or VIL
0.001
1.5
mA
Vee = Max
VIN ~ VHe, VIN
fl = 0
0.5
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
6-32
=
=
=
=
3V; VIN. = 0.2V or VHe; 10L
:s: 0.2V
10L
10L
10L
=
=
=
=
300 p.A
300/LA
32 mA (Mil)
48 mA (Com)
DC Characteristics for 'FCT Family Devices
(Continued)
Typical values are at Vcc = 5.0V, 25·C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vcc = 5.0V ±5%, TA = O·C to +70·C; Mil: Vcc = 5.0V ± 10%, TA = -55·C
to + 125·C, VHC = Vcc - 0.2V.
Symbol
74FCT
Parameter
Min
Dynamic Power
Supply Current (Note 4)
ICCD
Total Power Supply
Current (Note 6)
Ic
Typ
Conditions
Units
Max
0.25
0.15
1.5
4.0
1.8
6.0
mA/MHz
Vcc = Max
Outputs Open
One Input Toggling
50% Duty Cycle
Vcc = Max
Outputs Open
fcp = 10 MHz
OE = GND
f, = 5 MHz
One Bit Toggling
50% Duty Cycle
V,N;;' VHC
V,N"; 0.2V
Y,N = 3.4V
Y,N = GND
mA
3.0
7.8
5.0
16.8
(Note 5)
Vcc = Max
Outputs Open
fcp = 10MHz
OE = GND
f, = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
Note 1: Maximum test duration not to exceed one second, not more than ons output shorted at ons time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven input (VIN
~
3.4V); all other inputs at Vce or GND.
NOle 4: This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Note 5: Values lor these conditions are examples 01 the Icc lormula. These limits are guaranteed but not tested.
Note 6: Ic ~ 'OUIESCENT + liN PUTS + IDYNAMIC
Ic ~ Icc + ~Icc DHNT + ICCD (lcpf2 + II NI)
Ice ~ Quiescent CUrrent
~Ice ~
DH
~
NT
~
~
ICp
II
NI
~
~
~
3.4V)
Number 01 Inputs at DH
~
IceD
Power Supply CUrrent lor a TTL High Input (VIN
Duly Cycle lor TTL Inputs High
Dynamic CUrrent Caused by an Input Transition Pair (HLH or LHL)
Clock Frequency lor Register Devices (Zero lor Non-Register Devices)
Input Frequency
Number 01 Inputs at II
All currents ars in milliamps and all frequencies are in megahertz.
Note 7: For 54FCT, ICCD
~
0.40 mA/MHz.
Reier to applicable standard military drawing or NSC Table I lor test conditions and IcliCC limits.
6-33
Y,N = 3.4V
Y,N = GND
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 lor Wavelorms
54FCT174FCT
74FCT
54FCT
TA = +25"C
Vee = 5.0V
TA. Vee = Com
Rl = 5000
Cl = 50pF
TA. Vee = Mil
Rl = 5000
Cl = 50pF
Units
Fig.
No.
Typ
Min (Note 1)
Max
Min
Max
6.6
2.0
10.0
2.0
11.0
ns
2-8
9.0
1.5
12.5
1.5
14.0
ns
2-11
6.0
1.5
8.0
1.5
8.0
ns
2-11
Set Up Time High or Low
DntoCp
1.0
2.0
2.5
ns
2-10
Hold Time High or Low
Dn to Cp
0.5
2.0
2.5
ns
2-10
7.0
7.0
ns
2-9
tpLH
tpHL
Propagation Delay
CptoO n
tPZH
tpZL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
tsu
tH
Cp Pulse Width
4.0
High or Low
Note 1: Minimum IimHs are guaranteed but not tested on propagation delays.
tw
Capacitance TA =
+ 25'C. I = 1.0 MHz
Symbol
Parameter (Note 1)
CIN
Input Capacitance
Typ
Max
Unit
6
10
pF
VIN = OV
12
pF
VOUT = OV
Output Capacitance
8
COUT
Note 1: This parameter is measured at characterization but not tested.
eOUl for 74FCT only.
6-34
Condition
~National
~ Semiconductor
54FCT377/74FCT377
Octal D Flip-Flop with Clock Enable
General Description
Features
The FCT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and
outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
• NSC 54FCT174FCT377 is pin and functionally equivalent to IDT 54FCT/74FCT377
• Ideal for addressable register applications
• Clock enables for address and data synchronization applications
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 mA (com), 32 rnA (mil)
• CMOS power levels
• ESD immunity ~ 4 kV typ
• Military product compliant to MIL-STD 883 and Standard Military Drawing # 5962-87627
a
The register is fully edge-triggered. The state of each Dinput, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable operation.
FACTTM FCT utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCT features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
CP
CE
CE
20
Vee
CP
00
DO
01
2
19
°7
3
18
~
4
17
01
5
16
08
08
°2
O2
03
6
15
7
14
CE
TUF/l0661-1
00
DO
01
O2
°1
°2
03
03
04
05
0.
°5
06
06
~
~
03
GNO
8
13
9
12
10
11
TL/F/l0661-2
°5
05
04
°4
CP
TL/F/l0661-3
Pin Assignment
forLCC
~DzOz°l0l
1EI1I11E1[ID[!)
Pin Names
Do-D7
CE
00-0 7
CP
Description
III DO
!II 00
03 [[J
GNO IlID
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
CP
liD
IIlCE
~Vcc
1i]J°7
°41iZl
°4~
~1iID[§J1ilJ[§J
DsOs06Ds~
TUF/l0661-4
6-35
•
Mode Select-Function Table
Outputs
Inputs
Operating Mode
CP
CE
On
On
Load '1'
.../
L
H
H
Load '0'
.../
L
L
L
Hold (Do Nothing)
.../
X
H
H
X
X
NoChang9
NoChang9
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Immaterial
..r ~ LOW·to·HIGH Clock Transition
Logic Diagram
CP
0,
0,
0,
0,
0,
TL/F/l0661-5
Please note thallhis diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
6-36
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Terminal Voltage with Respect to GND
(VTERM)
54FCT
74FCT
Supply Voltage {Veel
54FCT
74FCT
-0.5Vto +7.0V
-0.5Vto +7.0V
Input Voltage
OV to Vee
Output Voltage
OV to Vee
Temperature Under Bias (TBIAS)
74FCT
54FCT
- 55·C to + 125·C
-65·C to + 135·C
Operating Temperature (TAl
54FCT
74FCT
Storage Temperature (TSTG)
74FCT
54FCT
- 55·C to + 125·C
-65·C to + 150·C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (PT)
4.5Vt05.5V
4.75V to 5.25V
-55·Cto + 125·C
-OOC to + 700C
175·C
140·C
0.5W
120mA
DC Output Current (lOUT)
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Exposure to absolute maximum raUng conditions
for extended periods may affect rellalbilily. The databook specifications
should be met. without exception, to ensure that the system design Is reli·
alble over Its power supply, temperature, and oulpuVlnput loading variables.
DC Characteristics for 'FCT Family Devices
Typical values are at Vee = 5.0V, 25·C ambient and maximum loading. For test conditions shown as Max, use the value
speCified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O·C to +70·C; Mil: Vee = 5.0V ±10%, TA = -55·C
to + 125·C, VHe = Vee - 0.2V.
Symbol
54FCT174FCT
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
Conditions
Max
2.0
V
0.8
V
Input High Current
5.0
5.0
/LA
IlL
Input Low Current
-5.0
-5.0
/LA
VIK
Clamp Diode Voltage
-1.2
V
los
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
Vee = 3V; V,N = 0.2Vor VHe; 10H = -32/LA
VHe
Vee
2.4
4.3
Vee = Min
VIN = V,H or V,L
2.4
4.3
VOL
Maximum Low Level
Output Voltage
-0.7
mA
V
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
10H = -300 /LA
10H= -12mA(Mil)
10H = -15 mA (Com)
GND
0.2
GND
0.2
0.3
0.5
0.3
0.5
6·37
Vee = 3V; V,N = 0.2V or VHe; 10L = 300 /LA
V
Vee = Min
VIN = V,H or V,L
10L = 300/LA
10L = 32 mA (Mil)
10L = 48 mA (Com)
DC Characteristics for 'FCT Family Devices (Continued)
Typical values are at Vcc = S.OV, 2S·C ambient and maximum loading, For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vcc = S.OV ±S%, TA = O·C to +70·C; Mil: Vcc = S.OV ±10%, TA = -SS·C
to + 12S·C, VHC = Vcc - 0.2V.
Symbol
74FCT
Parameter
Min
icc
Maximum Quiescent
Supply Current
AICC
Quiescent Supply Current;
TIL Inputs HIGH
lecD
Dynamic Power
Supply Current (Note 4)
Ie
Total Power
Supply Current (Note 6)
Units
Conditions
Typ
Max
0.001
1.S
mA
Vcc = Max
VIN ~ VHC, VIN ,;; 0.2V
fl = 0
O.S
2.0
mA
Vcc = Max
VIN = 3.4V (Note 3)
VIN ~ VHC
VIN';; 0.2V
mA/MHz
Vcc = Max
Outputs Open
CE = GND
One Input Toggling
SO% Duty Cycle
0.2S
0.30
1.S
4.0
VCC = Max
Outputs Open
ICp = 10MHz
SO% Duty Cycle.
VIN ~ VHC
VIN';; 0.2V
6.0
CE = GND
II = SMHz
One Bit Toggling
SO% Duty Cycle
VIN
.YIN
(NoteS)
Vcc = Max
Outputs Open
Icp = 10 MHz
SO% Duty Cycle
VIN ~ VHC
VIN';; 0.2V
CE = GND
II = 2.SMHz
Eight Bits Toggling
VIN'= 3.4V
VIN = GND
1.8
mA
3.0
S.O
9.0
16.8
Input Hysteresis on Clock Only
200
mV
VH
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven Input (VIN = 3.4VI; all other inputs at Vee or GND.
Note 4: This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Note 5: Values for these conditions are examples of the Icc lormula. These limits are guaranteed but not tested.
Note 6: Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (lcp/2 + fl Nil
lee = Quiescent Current
Alee = Power Supply Current lor a TTL HIGH Input (VIN = 3.4V)
DH = Duly Cycle for TTL inputs HIGH
NT = Number of Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
Note 7: For 54FCT. ICCD = 0.4 mAlMHz.
Refer to applicable standard military drawing or NSC Table I for test conditions and Icllcc limits.
6-38
= 3.4V
= GND
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
S4FCT174FCT
74FCT
S4FCT
TA = 2S'C
Vee = S.OV
TA. Vee = Com
Rl =
Cl = SOpF
TA. Vee = Mil
Rl =
Cl = SOpF
soon
soon
Units
Fig.
No.
ns
2-8
Typ
Min (Note) Max
Min
Max
tpLH
tpHL
Propagation Delay
CptoDn
7.0
2.0
2.0
13.0
tsu
Set UpTime
HIGH or LOW
DntoCp
1.0
2.5
4.0
ns
2-10
Hold Time·
HIGH or LOW
Dn to Cp
1.0
2.0
2.0
ns
2-10
Set Up Time
HIGH or LOW
CE to Cp
1.5
4.0
4.5
ns
2-10
Hold Time
HIGH or LOW
CEtoCp
3.0
1.5
2.0
ns
2-10
Clock Pulse Width, LOW
4.0
7.0
7.0
ns
2-9
tH
tsu
tH
tw
13.0
Note: Minimum limits are guaranteed but not tested on propagation delays.
Capacitance TA =
Symbol
+25'C, f
=
Parameter
1.0 MHz
Typ
Max
Units
CIN
Input Capacitance
6
10
pF
VIN
COUT
Output Capacitance
8
12
pF
VOUT
Note: This parameter is measured at characterization but not tested.
COUT for 74FCT only.
6-39
Conditions
=
OV
=
OV
.r----------------------------------------------------------------------------,
N
an
~National·
ADVANCE INFORMATION
~ Semiconductor
54FCT17 4FCT521
8-Bit Identity Comparator
General Description
Features
The 'FCT521 is an expandable 8-bit comparator. It compares two words of up to eight bits each and provides a
LOW output when the two words match bit for bit. The expansion input TA = 8 also serves as an active LOW enable
input.
• NSC 54FCT174FCT521 is pin and functionally equivalent to lOT 54FCT/74FCT521
• Expandable to any word length
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 mA (Com), 32 mA (Mil)
• CMOS power levels
• 4 kV minimum ESO immunity
• Military Product compliant to MIL-STO 883
FACTTM FCT utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCT features GTOTM output control and undershoot
corrector In addition to a split ground bus for superior performance.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
I..,=B
°A=II
TUF/l0682-1
IEEE/IEC
COMP
TA=B
I>
Gl
Ao
Vee
TA=II
1
20
Ao
2
19
OA=B
80
3
18
Al
81
4
17
87
A7
5
16
Is
Az
6
15
~
A3
83
GIlD
7
14
As
Is
8
13
9
12
As
84
10
11
A4
Al
TUF/l0662-2
Az
A3
Pin Assignment
forLCC
A4
As
As
Ar
Bo
,mOm,
A3~Az81Al
lP=Q
i!l1IJi!l1ID1!I
°A=B
81
82
B3
84
Q
lis
I!iiJVee
Ii!! OA=B
1i3J1i§l1i§l1iZl1i!!
BsAsBeArBr
Dr
Ao-A7
8 0- 87
TA = B
OA=B
rnTA=B
Asfi]
86
Pin Names
mAo
GNDIi2\
A4 1ii1
B4 1iil
TUF/l0682-4
Description
Word A Inputs
Word 8 Inputs
Expansion or Enable Input
Identity Output
6-40
TUF/l0662-3
r----------------------------------------------------------------------------,~
Co)
Co)
~National
~ Semiconductor
54FCT17 4FCT533
Octal Transparent Latch with TRI-STATE® Outputs
General Description
Features
The 'FCT533 consists of eight latches with TRI-STATE outputs for bus organized system applications_ The flip-flops
appear transparent to the data when latch Enable (lE) is
HIGH. When lE is lOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is lOW. When OE is HIGH the bus output is in
the high impedance state. FACTTM FCT utilizes NSC quiet
series technology to provide improved quiet output switching and dynamic threshold performance. FACT FCT features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance. The
'FCT533 is the same as the 'FCT373, except that the outputs are inverted.
• NSC 54FCT174FCT533 is pin and functionally equivalent to lOT 54FCT174FCT533
• TRI-STATE outputs for bus interfacing
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 mA (Com), 32 mA (Mil)
• CMOS power levels
• ESD immunity 4 kV typ
• Military product compliant to Mil-STD 883 and Standard Military Drawing #5962-88651
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
IEEE/IEC
OE
OE
LE
Do
°0
01
°1
°0
Do
01
02
03
04
°2
05
06
07
20
Vee
2
19
07
3
18
Os
°1
°3
°2
6
°4
O2
7
03
8
13
°5
05
04
10
12
11
lE
°5
°7
°3
GND
Os
04
TlIF/l0664-1
TL/F/l0664-2
lE
DE
TlIF/l0664-4
6-41
D3~~01Dl
IIlrn([J[ID[!J
~
4
5
Os
Pin Assignment
forlCC
°3 12l
GND [9J
LE Ii]
moo
III 00
mOE
04 1m
@Vee
D4 1l]
IrnI 07
1BI1iIDirnliUlIrID
DsOS0611;~
TL/F/l0664-3
~ r-----------------------------~------------------------------------------------__,
~
Function Table
Description
Pin Names
Inputs
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary TRI-STATE Outputs
Do-D7
LE
OE
0 0-0 7
Output
LE
OE
D
'0
H
H
L
L
L
L
H
H
L
L
H
On
X
X
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Logic(O) or 10gic(l) must be valid Input Level
On = Previous On before high to low transition of latch enable.
Functional Description
The 'FCT533 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent and the latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH 7to-LOW transition of
LE. The TRI-STATE buffers are controlled by the Output
Enable (OE) input. When DE is LOW the latch contents are
presented inverted at the outupts 07-00' When OE is
HIGH the buffers are in the high impedance mode but this
does not interfere with entering new data into the latches.
Logic Diagram
DO
Dl
LE
°1
°7
TL/F/l0664-S
Please note that this diagram is provided only for the understanding of logiC operations and should not be used to estimate propagation delays.
6-42
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
54FCT
74FCT
Input Voltage
Temperature Voltage with respect to GND (VTERM)
-0.5Vto +7.0V
54FCT
74FCT
-0.5Vto +7.0V
- 55'C to + 125'C
- 65'C to + 135'C
Storage Temperature (TSTG)
74FCT
54FCT
Operating Temperature (TA)
54FCT
74FCT
- 55'C to + 125'C
- 65'C to + 135'C
Junction Temperature (TJ)
CDIP
PDIP
O.5W
DC Output Current (lOUT)
OVtoVee
Output Voltage
Temperature under Bias (TBIAS)
74FCT
54FCT
Power Dissipation (PT)
4.5Vt05.5V
4.75V to 5.25V
OV to Vee
-55'C to + 125'C
O'Cto +70'C
175'C
140'C
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. The databook specifications
should be met. without exception. to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables.
DC Characteristics for FCT Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ±10% TA = -55'C
to +125'C.
Symbol
54FCT174FCT
Parameter
Min
VIH
Minimum HIGH Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
,..A
IlL
Input Low Current
-5.0
-5.0
,..A
loz
Maximum TRI·STATE
Current
10.0
10.0
-10.0
-10.0
,..A
-1.2
V
VIK
Clamp Diode Voltage
los
Short Circuit Current
VOH
Minimum High Level
Output Voltage
-0.7
-60
Maximum Low Level
Output Voltage
-120
2.8
3.0
VHe
Vee
2.4
4.3
2.4
VOL
Conditions
Max
mA
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Max
Va
Va
Va
Va
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
Vee = Min; liN = -18 mA
Vee = Max (Note 1); Va = GND
Vee = 3V; VIN = 0.2V or VHe; 10H = -32,..A
V
Vee = Min
10H = -300,..A
VIN = VIH or VIL
10H = -12mA(Mil)
10H = -15 mA (Com)
4.3
GND
=
=
=
=
Vee = 3V; VIN = 0.2V or VHe; 10L = 300,..A
0.2
GND
0.2
0.3
0.50
0.3
0.50
V
Vee = Min
10L = 300,..A
VIN = VIH or VIL
10L = 32 mA (Mil)
10L = 48 mA (Com)
6·43
DC Characteristics for FCT Family Devices
Typical values are at Vcc = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vcc = 5.0V ± 5 %, TA = O'C to + 70'C; Mil: Vcc = 5.0V ± 10% TA = - 55'C
to + 125'C. (Continued)
Symbol
74FCT
Parameter
Min
Icc
Maximum Quiescent
Supply Current
54FCT
74FCT
Input Voltage
Output Voltage
Operating Temperature (TA)
54FCT
74FCT
Junction Temperature (TJ)
CDIP
PDIP
4.5Vt05.5V
4.75V to 5.25V
OVtoVee
OVtoVee
- 55°C to + 125°C
- COC to + 70°C
175°C
140°C
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25°C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O°C to +7COC; Mil: Vee = 5.0V ±10%, TA = -55°C
to + 125°C, VHe = Vee - 0.2V.
Symbol
Parameter
54FCTA174FCTA
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
p.A
IlL
Input Low Current
-5.0
-5.0
p.A
loz
Maximum TRI-STATE Current
10.0
10.0
-10.0
-10.0
VIK
Clamp Diode Voltage
los
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
VOL
Maximum Low Level
Output Voltage
Conditions
Max
-0.7
-1.2
0.2
GND
0.3
0.3
0.2
0.5
0.5
6-48
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee
p.A
Vee
Vee
V
= Max
Vo = Vee
Vo = 2.7V (Note 2)
Vo = 0.5V (Note 2)
Vo = GND
= Min; IN = -18 mA
= Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2V or VHe; 10H = -32 p.A
10H = -300 p.A
Vee = Min
10H = -12 mA (Mil)
VIN = VIH or VIL
10H = -15mA(Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300 p.A
Vee = Min
10L = 300 p.A
10L = 32 mA (Mil)
VIN = VIHorVIL
10L = 48 mA (Com)
V
mA
V
GND
Vee = Max
DC Characteristics for 'FCT Family Devices (Continued)
Typical values are at Vcc = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vcc = 5.0V ±5%, TA = O'C to +70'C; Mil: Vcc = 5.0V ± 10%, TA = -55'C
to + 125'C, VHC = Vcc - 0.2V.
Symbol
74FCT
Parameter
Min
Maximum Quiescent
Supply Current
Icc
alcc
Quiescent Supply Current;
TIL Inputs HIGH
ICCD
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
IC
Units
Conditions
Typ
Max
0.001
1.5
mA
Vcc = Max
VIN :<: VHC, VIN ,;; 0.2V
II = 0
0.5
2.0
mA
Vcc = Max
VIN = 3.4V (Note 3)
0.15
0.25
1.5
4.0
1.8
6.0
mA/MHz
Vcc = Max
Outputs Open
OE = GND
One Input Toggling
50% Duty Cycle
Vcc = Max
Outputs Open
fcp = 10 MHz
OE = GND
II = 5 MHz
One Bit Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
mA
3.0
7.8
5.0
16.8
(Note 5)
Vcc = Max
Outputs Open
OE = GND
Icp = 10MHz
II = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven Input (Y,N
~
3.4V); all other inputs at Vee or GND.
Note 4: This parameter is not directly testable, but is derived lor use in Total Power Supply calculations.
Note 5: Values lor these conditions are examples 01 the IcC lormula. These limits are guaranteed but not tested.
Note 6: IC ~ ICUIESCENT + I,NPUTS + IDYNAMIC
IC ~ Icc + alCC DHNT + ICCD (lcp/2 + I, N,)
Icc = Quiescent Current
alcc ~ Power Supply Current lor a TTL High Input (V,N
DH
~
Duty Cycle lor TTL inputs High
NT
~
Number 01 Inputs at DH
ICCD
~
Icp
I,
N,
~
~
~
~
3.4V)
Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Clock Frequency lor Register Devices (Zero lor Non·Register Devices)
Input Frequency
Numbers 01 Inputs at I,
All currents are in milliamps and all frequencies are in megahertz.
Note 7: For 54FCT, ICCD ~ 0.40 mA/MHz.
Reier to applicable standard military drawing or NSC Table I lor test conditions and Icllcc limits.
6-49
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
S4FCT174FCT
74FCT
S4FCT
TA = +2S"C
Vee = S.OV
TAJ Vee =
Mil
CL = SOpF
TA Vee =
Com
CL = SOpF
Typ
Min
(Note 1)
Max
Min
Unlls
Fig.
No.
Max
tpLH
tpHL
Propagation Delay
CptoOn
6.5
1.5
10.0
ns
2-9
tPZH
tPZL
Output Enable
Time
9.0
1.5
12.5
ns
2-11
tpHZ
tpHL
Output Disable
Time
6.0
1.5
8.0
ns
2-11
Is
Set Up Time High or Low
DntoCP
1.0
2.0
ns
2-10
th
Hold Time High or Low
DntoCP
0.5
1.5
ns
2-10
7.0
ns
2-9
CP Pulse Width
4.0
High or Low
Nole 1: Minimum limns guaranteed but not tested on propagalion delays.
tw
Capacitance TA =
Symbol
+ 25"C, fl = 1.0 MHz
Typ
Max
Units
CIN
Input Capacitance
Parameter
6
10
pF
VIN = OV
COUT
Output Capacitance
8
12
pF
VOUT = OV
Nole: This parameter Is measured al characterization but not tested.
COUT for 74FCT only.
6-50
Conditions
,----------------------------------------------------------------------------, en
....
o
~National
~ Semiconductor
54FCT540
Inverting Octal Buffer/Line Driver
with TRI-STATE® Outputs
General Description
Features
The 'FCT540 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock
driver and bus oriented transmitter or receiver which provides improved PC board denSity.
• NSC 54FCT540 is pin and functionally equivalent to lOT
54FCT540
• Controlled output edge rates and undershoot for improved noise immunity. Internal split ground for improved noise immunity
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
The FACT540 is functionally equivalent to the FCT240 while
providing broadside pinout.
The FACTTM FCT utilizes NSC quiet series technology to
provide improved quiet output switching and dynamic
threshold performance.
FACT FCT features undershoot corrector and a split ground
bus for superior performance.
IOL = 48 mA
CMOS power levels
2 kV minimum ESD immunity
Military product compliant to MIL-STD 883 and Standard Military Drawing #5962-89767
•
•
•
•
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
OE,
19 0E 2
18 -
4
17 -
"
'2
°0
°1
13
°2
03
14
°4
Is
Os
Is
06
'7
rn
!lJ "
15 -
[II '0
07 (j] ~4*~~~a;JIII..!II OE,
oslrn
@]Vee
14 -
0slrn
16 -
°2
03
Is
6 Is 14 13 '2
GNo!lID
°1
'3
'4
16
'7
°0
'2
10
'
[I)[1] !II [[III!
20 Vee
2
'0
"
Pin Assignment
forLCC
!lID 0E2
°4
8
13 -
9
12 °6
11 °7
1Hl1iID1lID1lZl1lID
Os
17
GNo 10
04 03 02 01 00
TLlF/l0695-3
TL/F/l0695-2
°7
TL/F/l0695-1
Truth Table
Pin Names
OE1,OE2
10- 17
0 0- 0 7
Inputs
Description
TRI-STATE Output Enable Inputs
Inputs
Outputs
OEI
OE2
L
L
X
H
X
L
H
L
X
Z
6-51
~
~
~
~
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
H
L
Outputs
H
X
X
L
L
Z
Z
H
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specHled devices are required,
please contac1 the National Semiconductor Sales
Office/Distributors for availability and specifications.
Terminal Voltage
with Respect to GND (VTERM)
54FCT
-0.5V to 7.0V
Temperature under Bias (TSIAS)
54FCT
- 65'C to + 135'C
Storage Temperature (TSTG)
54FCT
- 65'C to + 150'C
Power Dissipation (PT)
0.5W
DC Output Current (lOUT)
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the ,device may occur. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. The dalabook specifications
should be met. without exception. to ensure that the system design is reli·
able over Its power supply, temperature, and output/input loading variables.
Supply Voltage (Veel
54FCT
Input Voltage
Output Voltage
Operating Temperature (TAl
54FCT
Junction Temperature (TJ)
CDIP
PDIP
4.5Vt05.5V
OV to Vee
OVtoVee
- 55'C to + 125'C
175'C
'140'C
DC Characteristics for 'FCT Family Devices
Typical values are at Vee = 5.0V. 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ± 10%, TA = -55'C
to + 125'C, VHe = Vee - 0.2V.
Symbol
54FCT
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
jJ.A
IlL
Input Low Current
-5.0
-5.0
jJ.A
loz
Maximum TRI·STATE Current
10.0
10.0
-10.0
-10.0
jJ.A
-1.2
V
VIK
Clamp'Diode Voltage
lOS
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
VOL
Icc
~Iee
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
Conditions
Max
-0.7
mA
V
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
0.001
1.5
mA
0.5
2.0
mA
6·52
V
Vee
= Max
Vee
= Max
Vee
= Max
= Vee
= 2.7V (Note 2)
VI = 0.5V (Note 2)
VI = GND
Vo = Vee
Vo = 2.7V(Note2)
Vo = 0.5V (Note 2)
Vo = GND
VI
VI
= Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2V or VHe; 10H = -32 jJ.A
IOH = -300jJ.A
Vee = Min
10H = -12 mA (Mil)
VIN = VIH or VIL
10H = -15 mA (Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300 jJ.A
Vee = Min
10L = 300 ",A
10L = 48 mA (Mil)
VIN = VIH or VIL
10L = 64 mA (Com)
Vee = Max
Vee
VIN :;;: VHe, VIN
II = 0
~
0.2V
Vee = Max
VIN = 3.4V (Note 3)
DC Characteristics for 'FCT Family Devices (Continued)
Typical values are at Vcc = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vcc = 5.0V ± 5%, TA = O'C to + 70'C; Mil: Vcc = 5.0V ± 10%, TA = -55'C
to + 125'C, VHC = Vcc - 0.2V.
Symbol
54FCT
Parameter
Min
ICCD
Ic
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
Conditions
Units
Typ
Max
0.35
0.4
rnA/MHz
5.5
rnA
6.0
Vcc = Max
Outputs Open
OEA = OEB = GND
One Input Toggling
50% Duty Cycle
Vcc = Max
Outputs Open
OEA = OEB = GND
fl = 10 MHz
One Bit Toggling
50% Duty Cycle
Nole 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Nole 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
Nole 4: This parameter is not directly testable, but Is derived lor use In Total Power Supply calculations.
Nole 5: Values lor these conditions are examples 01 the Icc lonnula. These limits are guaranteed but not tested.
Note 6: Ic - IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .1lcc DHNT + Iceo (lcp/2 + II NI)
Icc = Quiescent Current
.1ICC = Power Supply Current lor a TTL High Input (VIN = 3.4V)
DH = Duly Cycle lor TTL Inputs High
NT = Number 01 Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
ICp = Clock Frequency lor Register Devices (Zero lor Non-Register Devices)
II = Input Frequency
NI = Number 01 Inputs at II
All currents are milliamps and all frequencies are in megahertz.
6-53
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
54FCT174FCT
74FCT
54FCT
TA = +25'C
Vee = 5.0V
TA. Vee = Com
RL = 500.0
CL = 50pF
TA. Vee = Mil
RL = 500.0
CL = 50pF
Propagation Delay
On to On
tPZH
tpZL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
Capacitance TA =
I
I
Symbol
CIN
I
I
Max
5.0
1.5
9.5
ns
2·6
7.0
1.5
12.5
ns
2·11
6.0
1.5
9.5
ns
2·11
Min
Max
+ 25'C, f = 1.0 MHz
Parameter (Note)
Input Capacitance
I
I
Fig.
No.
Min
Typ
tpLH
tpHL
Units
Typ
6
I
I
Max
8
Note: This parameter is measured at characterization but not tested.
6·54
I
I
Units
pF
Conditions
VIN = OV
I
I
~-------------------------------------------------------------------------------,
~National
~ Semiconductor
54FCT541
Non-Inverting Octal Buffer/Line Driver
with TRI-STATE® Outputs
General Description
Features
The 'FCT541 is a non·inverting octal buffer and line driver
designed to be employed as a memory address driver, clock
driver and bus oriented transmitter or receiver which pro·
vides improved PC board density.
The FCT541 is functionally equivalent to the FCT 241 with
the exception of packaging, inputs and outputs are on the
opposite side of the package.
FACTTM FCT utilizes NSC quiet series technology to pro·
vide improved quiet output switching and dynamic threshold
performance.
• NSC 54FCT541 is pin and functionally equivalent to lOT
54FCT541
• Input clamp diodes to limit bus reflections
• TIL/CMOS input and output level compatible
iii IOL = 4B mA
• CMOS power levels
• 2 kV minimum ESD immunity
• Military product compliant to MIL·STD BB3 and stan·
dard military drawing # 5962·B9766
FACT FCT features undershoot corrector and split ground
bus for superior performance.
Ordering Code: See Section B
Logic Symbol
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
Pin Assignment
forLCC
Is 15 14 13 12
[[111] [!] I]][!J
m11
m10
1,[[1
GNDIiQ]
10
O,!Iil ,..mn1~~~~Ja;~ m0E1
°0
~Vcc
0slffi
0sll]]
°1
lrn 0E2
12
°2
13
°3
lEI Irnlrn IlZIlrn
14
°4
04 03 02 01 00
15
°5
IS
Os
I,
TL/F/l0696-3
0,
TL/F/l0696-2
TL/F/l0696-1
Truth Table
Pin Names
OE1,OE2
10-17
00-0 7
Description
Inputs
TRI·STATE Output Enable Inputs
Inputs
Outputs
OE2
L
H
L
H
H
X
X
X
Z
Z
L
L
X
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
6·55
Outputs
OE1
H
L
In
tn
...."'"
...
'III'
II)
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Terminal Voltage
with Respect to GND (VTERM)
54FCT
Temperature under Bias (TBIAS)
54FCT
Storage Temperature (TSTG)
54FCT
Supply Voltage (Ved
54FCT
-0.5V to 7.0V
- 65'C to
- 65'C to
Power Dissipation (PT)
4.5Vt05.5V
Input Voltage
OVtoVee
Output Voltage
OVtoVee
Operating Temperature (TA)
54FCT
+ 135'C
- 55'C to
Junction Temperature (TJ)
CDIP
PDIP
+ 150'C
0.5W
+ 125'C
175'C
140'C
120mA
DC Output Current (loUT)
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. The datebook specifications
should be met. without exception, to ensure that the system design Is reliable over Hs power supply, tempeniture, and output/Input loading variables.
DC Characteristics for 'FCT Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, Mil: Vee = 5.0V ±10%, TA = -55'C to + 125'C, VHe =
Vee - 0.2V.
Symbol
54FCT
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Leve!
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
/LA
IlL
Input Low Current
-5.0
-5.0
/LA
loz
Maximum TRI·STATE Current
10.0
1q:p
-10:0
-10.0
VIK
Clamp Diode Voltage
los
Short Circuit Current
VOH
Minimum High Level
Output Voltage
VOL
lee
Alee
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
-0.7
-60
Conditions
Max
-1.2
-120
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Max
Vo =
Vo =
Vo =
Vo=
/LA
V
mA
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
Vee = Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
2.8
3.0
Vee = 3V; VIN = 0.2Vor VHe; 10H = -32/LA
VHe
2.4
2.4
Vee
4.3
4.3
V
Vee = Min
VIN = VIH or VIL
V
10H = -300/LA
10H = -12mA(MiI)
10H = -15 mA (Com)
GND
0.2
Vee = 3V; VIN = 0.2V or VHe; 10L = 300/LA
GND
0.3
0.3
0.2
0.55
0.55
Vee = Min
VIN = VIH or VIL
0.001
1.5
mA
Vee = Max
VIN ~ VHe, VIN ~ 0.2V
fl = 0
0.5
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
6-56
10L = 300/LA
10L = 48 mA (Mil)
10L = 64 mA (Com)
~----------------------------------------------------------------------------------------~
DC Characteristics for 'FCT Family Devices (Continued)
Typical values are at Vee = S.OV, 2S'C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vee = S.OV ± S%, TA = O'C to + 70'C; Mil: Vee = S.OV ± 10%, TA = -SS'C
to + 12S'C, VHe = Vee - 0.2V.
Symbol
54FCT
Parameter
Min
Dynamic Power
Supply Current (Note 4)
IceD
Typ
0.3S
Units
0.40
Total Power Supply
Current (Note 6)
Ie
Conditions
Max
mA/MHz
Vee = Max
Outputs Open
OEA = OEB = GND
One Input Toggling
SO% Duty Cycle
Vee = Max
Outputs Open
OEA = OEB = GND
I, = 10MHz
One Bit Toggling
SO% Duty Cycle
S.S
6.0
V,N = 3.4V
V,N = GND
mA
(NoteS)
Vee = Max
OEA = OEB = GND
I, = 2.S MHz
Eight Bits Toggling
50% Duty Cycle
Note 1: Maximum test duratlen net te exceed ene secend, net mere than ene eutput sherted at ene time.
Note 2: This parameter guaranteed but net tested.
Note 3: Per TIL driven Input (VIN = 3.4V); all ether Inputs at Vcc er GND.
Note 4: This parameter is net directly testable, but is derived fer use in Tetal Pewer Supply calculatiens.
Note 5: Values fer these cenditiens are examples ef the Icc fermula. These limits are guaranteed but net tested.
Note 6: Ie = IQUIESCENT + 'INPUTS + 'DYNAMIC
Ie = Icc + ~4
~
~
~
v
[DOE,
031rn
~Vcc
161m
1i!l0E2
02 0, 00
1HI1rn1i§l1ill1i!l
'5
14
TLlF/l0268-3
~
~
~
TL/F/l0268-2
TLlF/l0268-1
Pin Names
OE1,OE2
10-17
00-0 7
Truth Tables
Description
TRI·STATE Output Enable Inputs
Inputs
Outputs
Inputs
OE1
D
Outputs
(Pins 12, 14, 16, 18)
L
L
H
L
H
H
L
X
Z
Inputs
OE2
D
Outputs
(Pins 3, 5, 7, 9)
L
L
H
L
H
H
L
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
7-4
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
54FCTA
74FCTA
Terminal Voltage
with Respect to GND (VTERM)
54FCTA
74FCTA
-0.5V to 7.0V
-0.5V to 7.0V
Temperature under Bias (TSIAS)
74FCTA
54FCTA
- 55'C to + 125'C
-65'C to + 135'C
Operating Temperature (TA)
54FCTA
74FCTA
Storage Temperature (TSTG)
74FCTA
54FCTA
- 55'C to + 125'C
- 65'C to + 150'C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (PT)
4.5Vto 5.5V
4.75V to 5.25V
Input Voltage
OV to Vee
OV to Vee
Output Voltage
- 55'C to + 125'C
- O'C to + 70'C
175'C
140'C
0.5W
DC Output Current (lOUT)
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT FeT circuits outside databook specifications.
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ± 10%, TA = -55'C
to + 125'C, VHe = Vee - 0.2V.
Symbol
Parameter
54FCTA174FCTA
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
iJ- A
IlL
Input Low Current
-5.0
-5.0
iJ-A
loz
Maximum TRI-STATE Current
10.0
10.0
-10.0
-10.0
iJ-A
-1.2
VIK
Clamp Diode Voltage
Conditions
Max
-0.7
Vee
= Max
VI = Vee
VI = 2.7V (Note 2)
Vee
= Max
VI
VI
Vee
= Max
Va
Va
Va
Va
V
Vee
= Min; IN = -18 mA
mA
= 0.5V (Note 2)
= GND
=
=
=
=
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
lOS
Short Circuit Current
-60
Vee
= Max (Note 1); Va = GND
VOH
Minimum High Level
Output Voltage
2.8
3.0
Vee
VHe
2.4
2.4
Vee
4.3
4.3
Vee = Min
VIN = VIH or VIL
= 3V; VIN = 0.2VorVHe; 10H = -32 iJ-A
10H = -300 iJ-A
10H = -12 mA (Mil)
10H = -15 mA (Com)
VOL
Maximum Low Level
Output Voltage
lee
Maximum Quiescent
Supply Current
dlee
Quiescent Supply Current;
TTL Inputs HIGH
-120
V
= 3V; VIN = 0.2V or VHe; 10L = 300 iJ-A
GND
0.2
Vee
GND
0.3
0.3
0.2
0.55
0.55
Vee = Min
VIN = VIH or VIL
0.001
1.5
0.5
2.0
7-5
V
mA
Vee = Max
VIN ;0, VHe, VIN ,;: 0.2V, fl
mA
Vee = Max
VIN = 3.4V (Note 3)
10L
10L
10L
=0
= 300 iJ-A
= 48 mA (Mil)
= 64 mA (Com)
,.
~
~
DC Characteristics for 'FCTA Family Devices (Continued)
Typical values are at Vcc = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vcc = 5.0V ± 10%, TA = -55'C
to + 125'C, VHC = Vcc - 0.2V.
Symbol
Parameter
54FCTA174FCTA
Min
ICCD
Ic
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
Typ
Max
0.25
0.40
1.5
4.5
1.8
5.0
Units
rnA/MHz
Conditions
Vcc = Max
Outputs Open
OEA = OEB = GND
One Input Toggling
50% Duty Cycle
VIN;;;' VHC
VIN';;: 0.2V
Vcc = Max
Outputs Open
OEA = OEB = GND
fl = 10MHz
One Bit Toggling
50% Duty Cycle
VIN;;;' VHC
VIN';;: 0.2V
VIN
VIN
=
=
3.4V
GND
rnA
(Note 5)
3.0
8.0
5.0
14.5
VCC = Max
Outputs Open
OEA = OEB = GND
II = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but noi tested.
Note 3: Per TIL drlven Input (VIN ~ 3.4V); all other Inputs at Vee or GND.
Note 4: This parameter Is not directly testable, but Is derived for use In Total Power Supply calculations.
Note 5: Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
Nota 6: Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = ICC + b.lcc DHNT + ICCD (fcp/2 + fl NI)
Icc = Quiescent Current
b.lcc = Power Supply Currerit for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number 01 Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number 01 inputs at II
All currents are milliamps and all frequencies are In megahertz.
7-6
VIN;;;' VHC
VIN';;: 0.2V
VIN
VIN
=
=
3.4V
GND
AC Electrical Characteristics:
Symbol
Parameter
tpLH
tpHL
Propagation Delay
On to On
tPZH
tPZL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
See Section 2 for Waveforms
54FCTA174FCTA
74FCTA
54FCTA
TA = +25'C
Vee = 5.0V
TA. Vee = Com
RL = soon
CL = 50pF
TA. Vee = Mil
RL = soon
CL = 50pF
Min (Note 1)
Symbol
Min (Note 1)
Max
3.5
1.5
4.8
ns
2-8
4.8
1.5
6.2
ns
2-11
4.3
1.5
5.6
ns
2-11
+ 25'C, f = 1.0 MHz
Parameter (Note)
Fig.
No.
Typ
Not. 1: Minimum limits are guaranteed but not tested on propagation delays.
Capacitance TA =
Units
Typ
Max
Units
CIN
Input Capacitance
6
10
pF
VIN = OV
COUT
Output Capacitance
8
12
pF
VOUT = OV
Not.: This parameter Is measured at characterization but not tested.
7-7
Condition
Max
~National
~ Semiconductor
54FCT/7 4FCT241A
Octal Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The 'FCT241 A is an octal buffer and line driver designed to
be employed as a memory address driver, clock driver and
bus-oriented" transmitter or receiver which provides improved PC board denSity.
• NSC 54174FCT241A is pin and functionally equivalent
to lOT 54174FCT241A
• Non-inverting TRI-STATE outputs drive bus lines or
buffer memory address registers
•
•
•
•
•
•
'FCT241A has TIL-compatible inputs
Military product compliant to MIL-STO-883C
Inherently radiation tolerant
IOL = 64 mA (Comm) and 48 mA (Mil)
TIL input and output level compatible
High current latch up
Ordering Code: See Section 8
Logic Sym~ol
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
Pin Assignment
forLCC
13 0 6 12 Os I,
II][lJ[!lrnm
G~:IO~~4
O:~N
V04
05
16
06
17
[!JOE,
ImVcc
ilIDOE2
IrnliIDilIDliililID
I>
Is
~1!iI
03~
16 Ii})
02 Is 0, 14 00
TL/FI10269-3
0.,
TL/FI10269-2
TLlF/l0269-1
Pin
Names
OE1,
OE2
10-17
00-0 7
Truth Tables
Description
Inputs
TRI-STATE Output Enable Input
TRI-STATE Output Enable Input (Active HIGH)
Inputs
Outputs
OEl
0
L
L
H
L
H
Outputs
(Pins 12, 14, 16, 18)
L
H
Z
X
Inputs
H
H
L
H
L
H
L
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
7-8
Outputs
(Pins 3, 5, 7, 9)
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
54FCTA
74FCTA
Terminal Voltage with Respect to GND (VTERM)
-0.5V to 7.0V
74FCTA
-0.5V to 7.0V
54FCTA
4.5Vt05.5V
4.75V to 5.25V
Input Voltage
OV to Vee
Output Voltage
OVtoVee
Temperature under Bias (TBIAS)
74FCTA
54FCTA
-55'Cto +125'C
-65'C to + 135'C
Storage Temperature (TSTG)
74FCTA
54FCTA
Operating Temperature (Till
54FCTA
74FCTA
-55'Cto + 125'C
-65'C to + 150'C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (PT)
0.5W
- 55'C to + 125'C
-O'Cto +70'C
175'C
140'C
DC Output Current (lOUT)
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception. to ensure that the system design is reliable over its power supply,
temperature, and outputlinput loading variables. National does not recom·
mend operation of FACTlM FCT circuits outside databook specifications.
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditons shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ± 10%, TA = -55'C
to + 125'C, VHe = Vee - 0.2V
Symbol
Parameter
54FCTA174FCTA
Min
VIH
Minimum High Level
Input Voltage
Vil
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
p.A
III
Input Low Current
-5.0
-5.0
p.A
loz
Maximum TRI-STATE Current
10.0
10.0
-10.0
-10.0
Vee
=
Max
p.A
Vo
Vo
3.0
Vee
=
3V; VIN
Vee
4.3
4.3
Vee = Min
VIN = VIH or Vil
VOH
Minimum High Level
Output Voltage
2.8
Quiescent Supply Current;
TIL Inputs HIGH
Max
Min; IN
-120
Il.lee
=
=
=
-60
Maximum Quiescent
Supply Current
Vee
= Vee
= 2.7V (Note 2)
VI = 0.5V (Note 2)
VI = GND
Vo = Vee
Vo = 2.7V (Note 2)
VI
VI
Vee
Short Circuit Current
Icc
Max
Vee
lOS
Maximum Low Level
Output Voltage
=
V
Clamp Diode Voltage
VOL
Vee
rnA
-0.7
VIK
VHe
2.4
2.4
Conditions
Max
-1.2
V
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
0.001
0.5
Vee
=
= 3V; VIN =
=
GND
0.2V or VHe; 10H
10H
10H
10H
=
=
=
Vee = Min
VIN = VIH or Vil
1.5
rnA
Vee = Max
VIN ~ VHe, VIN
fl = 0
2.0
rnA
Vee = Max
VIN = 3.4V (Note 3)
:s: 0.2V
10l
10l
10l
=
-32 p.A
-300 p.A
-12 rnA (Mil)
-15 mA (Com)
0.2V or VHe; 10l
V
7-9
0.5V (Note 2)
GND
-18 rnA
Max (Note 1); Vo
=
=
=
=
300 p.A
= 300 p.A
=
=
48 rnA (Mil)
64 mA (Com)
•
DC Characteristics for 'FCTA Family Devices (Continued)
Typical values are at Vee = 5.0V, 25·C ambient and maximum loading. For test conditons shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O"C to +70·C; Mil: Vcc = 5.0V ±10%, TA = -55·C
to + 125·C, VHC = Vee - 0.2V
Symbol
Parameter
54FCTA174FCTA
Min
ICCD
Ic
Typ
DynamiC Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
rnA/MHz
Vcc = Max
Outputs Open
OEA = DEe = GND
One Input Toggling
50% Duty Cycle
0.25
0.40
1.5
4.5
Vee = Max
Outputs Open
OEA = DEe = GND
1.8
5.0
fl = 10 MHz
One BitToggling
50% Duty Cycle
rnA
Input Hysteresis
on Clock Only
Conditions
Units
Max
3.0
8.0
(Note 5)
Vee = Max
Outputs Open
OEA = OEe = GND
5.0
14.5
fl = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
mV
200
Nota 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Nota 2: This parameter guaranteed but not tested.
Nota 3: Per TTL driven Input (VIN
= 3.4V): all other Inputs at Vcc or GND.
Nota 4: This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Note 5: Values for these conditions are examples of the Icc fonnula. These limits are guaranteed but not tested.
Note 6: Ie = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + AICC DHNT + ICCD (fCp/2 + fl NI)
Icc = Quiescent Current
Alcc = Power Supply Current for a TTL High Input (YIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of Inputs at DH
ICCD = Dynamic Current Caused by an Input TransHion Pair (HLH or LHL)
fCp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
7-10
VIN = 3.4V
VIN = GND
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
Symbol
S4FCTA174FCTA
74FCTA
S4FCTA
TA = +2S'C
Vee = S.OV
TA. Vee = Com
RL =
CL = SOpF
TA. Vee = Mil
RL =
CL = SOpF
Parameter
tpLH
tpHL
Propagation Delay
Onto On
tpZH
tpZL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
See Section 2 for Waveforms
soon
soon
Min (Note 1)
Units
Fig.
No.
Typ
Min (Note 1)
Max
3.0
1.5
4.8
ns
2-8
4.0
1.5
6.2
ns
2-10
3.0
1.5
5.6
ns
2-10
Typ
Max
Units
Max
Nate 1: Minimum limits are guaranteed but not tested on propagation delays.
Capacitance (TA =
Symbol
+ 25'C, f
=
Parameter (Note)
1.0 MHz)
Conditions
=
CIN
Input Capacitance
6
10
pF
VIN
COUT
Output Capacitance
8
12
pF
VOUT
OV
=
OV
Note: This parameter is measured at characterization but not tested.
•
7-11
~National
~ Semiconductor
54FCT/7 4FCT244A
Octal Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The 'FCT244A is an octal buffer and line driver designed to
be employed as a memory address driver, clock driver and
bus-oriented transmitter/receiver which provides improved
PC board density.
II NSC 54/74FCT244A is pin and functionally equivalent
to IDT 54/74FCT244A
II TRI-STATE outputs drive lines or buffer memory address registers
II TTL input and output level compatible
II TTL inputs accept CMOS levels
II High current latch up immunity
II IOL = 64 mA (commercial) and 48 mA (military)
II Electrostatic discharge protection ~ 2 kV
II Military product compliant to MIL-STD 883C
II Inherently radiation tolerant
Ordering Code: See Section 8
Logic Symbol
Connection Diagrams
IEEE/IEC
OEl~N
10
I>
1,
V
Pin Assignment
forlCC
13 06 12 0s 1,
IIDITlIIDIIDIIl
G~~BfJ~~~
00
01
12
02
13
03
~:~N
VO~
0s
Is
Os
J.r
[]JOE,
Ili!IVcc
161m
1m 0E2
Irnlmimlillim
02 15 01 I~ 00
I>
15
17fi]
031rn
TL/F/l0270-3
TLlF/l0270-2
07
TL/F/l0270-1
Truth Tables
Pin Names
OE1,OE2
10-17
00-0 7
Description
Inputs
TRI-STATE Output Enable Inputs
Inputs
Outputs
Outputs
(Pins 12, 14, 16, 18)
OE1
D
L
L
H
L
H
L
H
X
Z
Inputs
OE2
D
L
L
H
L
H
H ~ HIGH Vollage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
7-12
X
Outputs
(Pins 3, 5, 7, 9)
L
H
Z
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
54FCTA
74FCTA
Terminal Voltage with Respect to GND (VrERM)
-0.5Vt07.0V
54FCTA
74FCTA
-0.5V to 7.0V
4.5Vto 5.5V
4.75V to 5.25V
Input Voltage
OVtoVee
Output Voltage
OVtoVee
Temperature under Bias (TSIAS)
74FCTA
54FCTA
-55'Cto + 125'C
-65'Cto +135'C
Storage Temperature (TSTG)
74FCTA
54FCTA
Operating Temperature (TA)
54FCTA
74FCTA
-55'C to + 125'C
-65'C to + 150'C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (Pr)
0.5W
-55'Cto + 125'C
- O'C to + 70'C
175'C
140'C
DC Output Current (lour)
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The datebook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom~
mend operation of FACT FeT circuits outside databook specifications.
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditons shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ± 5%, TA = O'C to + 70'C; Mil: Vee = 5.0V ± 10%, TA = -55'C
to + 125'C, VHe = Vee - 0.2V
Symbol
Parameter
54FCTA174FCTA
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
2.0
V
0.8
V
Input High Current
5.0
5.0
/LA
IlL
Input Low Current
-5.0
-5.0
/LA
loz
Maximum TRI·STATE Current
VIK
Clamp Diode Voltage
los
Short Circuit Current
VOH
Minimum High Level
Output Voltage
VOL
lee
Alee
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
-0.7
-60
Conditions
Units
Max
10.0
10.0
-10.0
-10.0
/LA
-1.2
V
-120
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
mA
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Max
VI
VI
VI
VI
= Vee
= 2.7V (Note 2)
= 0.5V (Note 2)
= GND
Vee = Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2V or VHe; 10H = -32/LA
V
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
0.001
0.5
Vee = Min
VIN' = VIH or VIL
10H = - 300 /LA
10H = -12 mA (Mil)
10H = -15 mA (Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300/LA
V
Vee = Min
VIN = VIH or VIL
1.5
mA
Vee = Max
VIN ;;, VHe, VIN
fl = 0
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
7·13
s:
10L = 300/LA
10L = 48 mA (Mil)
10L = 64 mA (Com)
0.2V
~
==
DC Characteristics for 'FCTA Family Devices (Continued)
Typical values are at Vcc = 5.0V, 25'C ambient and maximum loading. For test conditons shown as Max, use the value
specified for the appropriate device type: Com: Vcc = 5.0V ±5%, TA = O'C to +70'C; Mil: Vcc = 5.0V ±10%, TA = -55'C
to + 125'C, VHC = Vcc - 0.2V
Symbol
Parameter
54FCTA174FCTA
Min
ICCD
IC
Typ
Units
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
mA/MHz
Input Hysteresis
on Clock Only
Vcc = Max
Outputs Open
OEA = OEB = GND
One Input Toggling
50% Duty Cycle
0.25
0.40
1.5
4.5
Vcc = Max
Outputs Open
OEA = OEB = GND
1.8
5.0
fl = 10MHz
One Bit Toggling
50% Duty Cycle
mA
VH
Conditions
Max
3.0
8.0
(Note 5)
Vcc = Max
Outputs Open
OEA = OEe = GND
5.0
14.5
fl = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
mV
200
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven Input (VIN = 3.4V); all other Inputs at Vcc or GND.
Note 4: This parameter Is not directly testable, but Is derived lor use In Total Power Supply calculations.
Nole 5: Values lor these conditions are examples 01 the Ice lormula. These limits are guaranteed but not tested.
Note 6: Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + alce DHNT + IceD (lcp/2 + II NI)
Ice = Quiescent Current
alcc = Power Supply CUrrent for a TTL High Input (VIN = 3.4V)
DH = Duly Cycle lor TTL Inputs High
NT = Number of Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero lor Non·Register Devices)
'I = Input Frequency
NI = Number of Inputs at fl
All currents are In milliamps and all frequencies are in megahertz.
7·14
VIN = 3.4V
VIN = GND
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
74FCTA
54FCTA
TA = +25'C
Vee = 5.0V
TA, Vee = Com
RL = soon
CL = 50pF
TA, Vee = Mil
RL = soon
CL = 50pF
Parameter
Symbol
tpLH
tpHL
Propagation Delay
On to On
tPZH
tpZL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
See Section 2 for Waveforms
54FCTA174FCTA
Min (Note 1)
Symbol
+ 25'C, f
=
Parameter (Note)
Fig.
No.
Typ
Min (Note 1)
Max
3.1
1.5
4.8
ns
2-8
3.8
1.5
6.2
ns
2-11
3.3
1.5
5.6
ns
2-11
Note 1: Minimum limits are guaranteed but not tested on propagation delays.
Capacitance (TA =
Units
1.0 MHz)
Typ
Max
Units
CIN
Input Capacitance
6
10
pF
VIN
COUT
Output Capacitance
8
12
pF
VOUT
Note: This parameter is measured at characterization but not tested.
7-15
Conditions
= OV
= OV
Max
~National
~ Semiconductor
54FCT /7 4FCT245A
Octal Bidirectional Transceiver
with TRI-STATE® Inputs/Outputs
General Description
Features
The 'FCT245A contains eight non-inverting bidirectional
buffers with TRI-STATE outputs and is intended for bus-oriented applications. The Transmit/Receive (T/R) input determines the direction of data flow through '''Ie bidirectional
transceiver. Transmit (active-HIGH) enable~ data from A
ports to B ports; Receive (active-LOW) enableb data from B
ports to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition.
• NSC 54174FCT245A is pin and functionally equivalent
to lOT 54174FCT245A
• Non-inverting buffers
• Bidirectional data path
• TTL input and output level compatible
• TTL inputs accept CMOS levels
• High current latch up immunity
• IOl = 64 mA (commercial) and 48 mA (military)
• Electrostatic discharge protection ~ 2 kV
• Military product compliant to MIL-STD 883C
• Inherently radiation tolerant
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
OE
T/R
.J ~'\::7~ ~ Vee
2
B,
TL/F/l0271-1
B2
Pin
Names
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or TRISTATE Outputs
Side B Inputs or TRISTATE Outputs
A3
A.
B3
A5
B.
As
B5
A7
B6
GND
Inputs
T/R
L
L
H
L
H
X
DE
t!!
18
4
17
5
16
L
6
7
8
9
.,lllil
Bo
Bl
B2
51: 15
B3
~
14
B4
13
B5
12
B6
11
B7
B7
TL/F/l0271-3
TUF/l0271-2
Pin Assignment
forlCC
AS As A. A3 A2
Truth Table
OE
3
III mlii 1Il0
Outputs
A71Il1IJ III
AI
III Ao
GND!lID
BrrITI
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
H = HIGH Voltage level
L = LOW Voltage Level
X = Immaterial
my/Ii
Bslm
~Vcc
Bs~
li!liiE
1HI~1rn1lll1rn
B. B3 B2 B, Bo
TL/F110271-4
7-16
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
54FCTA
74FCTA
Input Voltage
Output Voltage
Operating Temperature (TA)
54FCTA
74FCTA
Junction Temperature (TJ)
CDIP
PDIP
Terminal Voltage with Respect to GND (VTERM)
54FCTA
- 0.5V to 7.0V
74FCTA
- 0.5V to 7.0V
Temperature under Bias (TBIAS)
74FCTA
- 55'C to + 125'C
54FCTA
- 65'C to + 135'C
Storage Temperature (TSTG)
-55'Cto +125'C
74FCTA
54FCTA
- 65'C to + 150'C
Power Dissipation (PT)
0.5W
120mA
DC Output Current (lOUT)
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over Its power supply,
temperature, and output/Input loading variables. National does not
4.5Vto 5.5V
4.75V to 5.25V
OVtoVee
OVtoVee
- 55'C to + 125'C
O'Cto +70'C
175'C
140'C
recom~
mend operation of FAeTTM FCT circuits outside dalabook specifications.
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ± 5%, TA = O'C to + 70'C; Mil: Vee = 5.0V ± 10%, TA = -55'C
to + 125'C, VHe = Vee - 0.2V.
Symbol
Parameter
54FCTA174FCTA
Min
Typ
Units
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
0.8
V
IIH
Input High Current
(except I/O Pins)
5.0
5.0
/LA
IIH
Input High Current
(110 Pins Only)
15
15
/LA
IlL
Input Low Current
(except 110 Pins)
-5.0
-5.0
/LA
IlL
Input Low Current
(110 Pins Only)
-15
-15
/LA
VIK
Clamp Diode Voltage
lOS
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
VOL
Maximum Low Level
Output Voltage
Conditions
Max
2.0
V
-0.7
-1.2
V
mA
Vee = Max
Vee = Max
Vee = Max
Vee = Max
= Vee
= 2.7V (Note 2)
VI = Vee
VI = 2.7V (Note 2)
VI = 0.5V (Note 2)
VI = GND
VI
VI
VI = 0.5V (Note 2)
VI = GND
Vee = Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
Vee = 3V;VIN = 0.2VorVHe;loH = -32/LA
V
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
7-17
Vee = Min
VIN = VIH or VIL
10H = -300/LA
10H = -12 mA (Mil)
10H = -15 mA (Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300/LA
V
Vee = Min
VIN = VIH or VIL
10L = 300 /LA
10L = 48 mA (Mil)
10L = 64 mA (Com)
,.
DC Characteristics for 'FCTA Family Devices (Continued)
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vcc = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ±10%, TA = -55'C
to + 125'C, VHC = Vcc - 0.2V.
Symbol
Parameter
54FCT174FCT
Min
Icc
Maximum Quiescent
Supply Current
alcc
Quiescent Supply Current;
TTL Inputs HIGH
ICCD
Dynamic Power
Supply Current (Note 4)
Ic
Total Power Supply
Current (Note 6)
Max
0.001
1.5
mA
Vee = Max
VIN ~ VHC, VIN
fl = 0
0.5
2.0
mA
Vcc = Max
VIN = 3.4V (Note 3)
mAIMHz
Input Hysteresis
on Clock Only
s: 0.2V
Vcc = Max
Outputs Open
T/R = GNDorVcc
OE = GND
One Input Toggling
50% Duty Cycle
VIN ~ VHC
VIN s: 0.2V
0.25
0.40
1.5
4.5
Vee = Max
Outputs Open
T/R = OE = GND
VIN ~ VHC
VIN s: 0.2V
1.8
5.0
fl = 10MHz
One Bit Toggling
50% Duty Cycle
VIN
VIN
(Note 5)
Vcc = Max
Outputs Open
TiA = OE = GND
VIN ~ VHC
VIN s: 0.2V
fl = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
VIN
VIN
mA
VH
Conditions
Units
Typ
3.0
8.0
5.0
14.5
200
mV
Note 1: Maximum test duration not to exceed one second. not more than one output shorted at one time.
Nole 2: This parameter guaranteed but not tested.
Nole 3: Per TTL driven input (YIN = 3.4V); all other inputs at Vcc or GND.
Nole 4: This parameter Is not directly testable, but is derived lor use in Total Power Supply calculations.
Nole 5: Values lor these conditions are examples 01 the Icc lormula. These limits are guaranteed but not tested.
Nole 6: Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (lcp/2 + II NI)
ICC = Quiescent Current
Alcc = Power Supply Currant lor a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number 01 Inputs at DH
lceo = Dynamic Currant Caused by an Input Transition Pair (HLH or LHL)
lep = Clock Frequency for Register Devices (Zero for Non·Register Devices)
II = Input Frequency
NI = Number of Inputs at II
All currents are in milliamps and all frequencies are in megahertz.
7·18
= 3.4V
= GND
= 3.4V
= GND
AC Electrical Characteristics:
Symbol
See Section 2 for Waveforms
54FCTA174FCTA
74FCTA
54FCTA
TA = +25"C
Vee = 5.0V
TA. Vee = Com
Rl = 500n
Cl = 50pF
TA. Vee = Mil
Rl = 500n
Cl = 50pF
Parameter
Fig.
No.
Typ
Min (Note 2)
Max
tpLH
tpHL
Propagation Delay
AtoB.BtoA
3.3
1.5
4.6
ns
2·8
tPZH
tPZL
Output Enable Time
OEtoAorB
4.8
1.5
6.2
ns
2·8
tpHZ
tpHL
Output Disable Time
OEtoAorB
4.5
1.5
5.0
ns
2·11
tpZH
tpZL
Output Enable Time
T/R toA or B (Note 1)
4.8
1.5
6.2
ns
2·11
1.5
5.0
ns
2·11
Output Enable Time
tpHZ
4.5
T/RtoAor B (Note 1)
tpLZ
Note 1: This parameter is guaranteed but not tested.
Note 2: Minimum limits guaranteed but not tested on propagation delays.
Capacitance TA =
Symbol
CIN
Min (Note 2)
Units
+ 25D C, f = 1.0 MHz
Parameter (Note)
Input Capacitance
Typ
Max
Units
6
10
pF
VIN = OV
12
pF
VOUT = OV
Output Capacitance
8
COUT
Note: This parameter is measured at characterization but not tested.
7·19
Conditions
Max
~National
ADVANCE INFORMATION
~ Semiconductor
54FCT17 4FCT273A
Octal D Flip-Flop
General Description
Features
The 'FCT273A has eight edge-triggered Ootype flip-flops
with Individual O. inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.
• NSC 54FCT174FCT273A is pin and functionally equivalent to lOT 54FCT174FCT273A
• Ideal buffer for MOS microprocessor or memory
• Buffered common clock
• Buffered, asynchronous master reset
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 mA (Com), 32 mA (Mil)
• CMOS power levels
• 4 kV minimum ESO immunity
• Military Product compliant to MIL-STO 883
The register is fully edge-triggered. The state of each 0 input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
All outputs will be. forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
FACTTM FCTA utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCTA features NSC correction and split ground bus
for superior performance.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
N'R
N'R
CP
CP
Do
00
MR
0,
0,
02
03
°2
03
04
05
°4
TL/F110660-1
06
°5
06
17
°7
00
Do
D,
0,
02
D2
D3
03
GND
1
2
3
4
5
Vee
07
17
6
7
10
13
12
11
TL/FI10660-3
TLlF110660-2
Pin Names
D6
06
05
D5
D4
04
CP
Pin Assignment
forLCC
Description
D:!DzOzO, D,
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
[!I [iJ[!l rn:J III
G~~:O~~:
[IlN'R
CP[jJ
041rn
D41rn
~vee
1iID~
1HI~~IiZI~
DsOsOsDeI7
TLlFI10660-4
7-20
,------------------------------------------------------------------------, w
~
~National
~ Semiconductor
54FCT17 4FCT373A
Octal Transparent Latch with TRI-STATE® Outputs
General Description
Features
The 'FCT373A consists of eight latches with TRI-STATE
outputs for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH, the bus output is in the
high impedance state.
• NSC 54/74FCT373A pin and functionally equivalent to
lOT 54174FCT373A
• Eight latches in a single package
• TRI-STATE outputs for bus interfacing
• TTL input and output level compatible
• High current latch up immunity
• IOL = 48 mA (commercial) and 32 mA (military)
• Military product compliant to MIL-STD 883
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIlEC
DE
DE
1
20
Vee
LE
00
2
19
°7
°0
3
18
Iry
°1
4
17
°6
°0
°0
0,
°1
Tl1Fll0618-1
O2
°2
03
°3
°4
°4
°5
06
°5
Iry
°7
°6
0,
5
16
°6
°2
6
15
°5
°2
7
14
°5
°3
8
13
°3
GNO
9
12
10
11
°4
04
LE
Tl1Fll0818-3
TUFll0618-2
Pin Names
Description
Pin Assignment
forLCC
D:I D:z O2 0, D,
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch Outputs
rn:Jmrn:Jrn:J[I]
G~~~D~~:
lE [j]
041il1
@iVcc
D4~
~07
[!JOE
1HI~~1i1I1iE
DsDs06Ds~
TUF/l0618-4
fI
7-21
Truth Table
Functional Description
The 'FCT373A contains eight D-type latches with TRISTATE outputs. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the Dinputs a setup time preceding the HIGH-to-LOW transition of
LE. The TRI-STATE outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard outputs
are in the 2-state mode. When OE is HIGH, the standard
outputs are in the high impedance mode but this does not
interfere with entering new data into the latches.
Inputs
outputs
LE
OE
On
On
X
H
L
L
L
X
L
H
Z
L
H
X
00
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
00 = Previous 00 before HIGH to Low transition of Latch Enable
Logic Diagram
TLIFI1061B-S
Please note that this diagram Is provided only for the understanding of logic operatlon~ and should not be used to estimate propagation delays.
7-22
Absolute Maximum Rating (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Terminal Voltage with Respect to GND (VTERM)
54FCTA
-0.5Vto +7.0V
74FCTA
-0.5Vto +7.0V
Temperature under Bias (TSIAS)
74FCTA
-55·Cto + 125·C
-65·Cto + 135·C
54FCTA
Storage Temperature (TSTG)
74FCTA
-55·Cto + 125·C
54FCTA
-65·C to + 150·C
Power Dissipation (PT)
0.5W
DC Output Current (lOUT)
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and oulputllnput loading variables. National does not recom·
mend operation of FACT FCTA circuits outside databook specifications.
Supply Voltage (Vecl
54FCTA
74FCTA
Input Voltage
Output Voltage
Operating Temperature (TAl
54FCTA
74FCTA
Junction Temperature (TJ)
CDIP
PDIP
4.5Vto 5.5V
4.75V to 5.25V
OVtoVee
OVtoVee
-55·C to + 125·C
-O·Cto +70·C
175·C
140·C
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25·C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O·C to +70·C; Mil: Vee = 5.0V ±10%, TA = -55·C
to + 125·C, VHe = Vee - 0.2V
Symbol
Parameter
54FCTA174FCTA
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
,.,.A
IlL
Input Low Current
-5.0
-5.0
IJ.A
10Z
Maximum TRI·STATE Current
10.0
10.0
-10.0
-10.0
,.,.A
-0.7
VIK
Clamp Diode Voltage
lOS
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
VOL
Icc
dice
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
Conditions
Max
-1.2
V
mA
V
GND
0.2
GND
0.3
0.3
0.2
0.50
0.50
0.001
1.5
mA
0.5
2.0
mA
7·23
V
Vee
= Max
Vee
= Max
Vee
= Max
= Vee
= 2.7V (Note 2)
VI = 0.5V (Note 2)
VI = GND
VI = Vee
VI = 2.7V (Note 2)
VI = 0.5V (Note 2)
VI = GND
VI
VI
= Min; IN = -18 mA
= Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2Vor VHe; 10H = -32,.,.A
10H = -300,.,.A
Vee = Min
10H = -12 mA (Mil)
VIN = VIH orVIL
10H = -15 mA (Com)
Vce = 3V; VIN = 0.2V or VHe; 10L = 300,.,.A
Vee = Min
10L = 300,.,.A
10L = 32 mA (Mil)
VIN = VIH or VIL
10L = 48 mA (Com)
Vee = Max
Vee
Vee
VIN ~ VHe, VIN
fl = 0
:s: 0.2V
Vee = Max
VIN = 3.4V (Note 3)
•
DC Characteristics for 'FCTA Family Devices
(Continued)
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vcc = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ±10%, TA = -55'C
to + 125'C, VHe = Vcc - 0.2V
Symbol
Parameter
54FCTA174FCTA
Min
ICCD
Ie
Typ
Units
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
Conditions
Mex
Vee = Max
Outputs Open
0.25
0.45
1.5
4.5
mA/MHz
~=GND
LE = Vcc
One Input Toggling
50% Duty Cycle
Vee = Max
Outputs Open
~=GND
LE = Vee
1.8
5.0
mA
Input Hysteresis
on Clock Only
3.0
8.0
5.0
14.5
fl = 10MHz
One Bit Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
(Note 5)
Vcc = Max
OE= GND
LE = Vcc
fl = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
200
mV
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TIL driven input (YIN = 3.4V); all other inputs at Vcc or GND.
Note 4: This parameter Is not directly testable. but is derived lor use In Totsl Power Supply calculations.
Note 5: Values lor these conditions are examples of the Icc lormula. These limits are guaranteed but not tested.
Note 6: Ic = IQUIESCENT + liN PUTS + IDYNAMIC
Ic = Icc + alcc DHNT + lceo (lcp/2 + II NI)
Icc = Quiescent Current
alcc = Power Supply Current lor a TIL High Input (YIN = 3.4V)
DH = Duly Cycle lor TIL Inputs High
NT = Number 01 Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero lor Non·Reglster Devices)
II = Input Frequency
NI = Number 01 Inputs at II
All currents are in milliamps and all Irequencies are in megahertz.
7·24
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
Symbol
See Section 2 for Waveforms
S4FCTA174FCTA
74FCTA
S4FCTA
TA = +2SoC
Vee = 5.0V
TA. Vee = Com
RL = soon
CL=50pF
TA. Vee = Mil
RL = soon
CL = 50pF
Parameter
Min (Note 1)
Units
Fig.
No.
Typ
Min (Note 1)
Max
4.0
1.5
5.2
ns
2·8
5.5
1.5
6.5
ns
2·11
4.0
1.5
5.5
ns
2·11
Propagation Delay
LEtoOn
7.0
2.0
8.5
ns
2·8
tsu
Set Up Time High or Low
Dn toLE
1.0
2.0
ns
2·10
tH
Hold Time High or Low
Onto LE
1.0
1.5
ns
2·10
5.0
ns
2·9
tpLH
tpHL
Propagation Delay
Onto On
tpZH
tPZL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
tpLH
tpHL
LE Pulse Width
4.0
High or Low
Note 1: Minimum limits are guaranteed but not tested on propagation delays.
tw
Capacitance TA = + 25°C, f = 1.0 MHz
Symbol
Parameter (Note 1)
CIN
Input Capacitance
Typ
Max
Units
6
10
pF
VIN
12
pF
VOUT
Output Capacitance
8
COUT
Nole: This parameter is measured at characlerizaUon but not tested.
7·25
Conditions
= OV
= OV
Max
~National
~ Semiconductor
54FCT17 4FCT37 4A
Octal D Flip-Flop with TRI-STATE® Outputs
General Description
Features
The 'FCT374A is a high-speed,low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and
TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all
flip-flops.
• NSC 54174FCT374A is pin and functionally equivalent
to IDT 54174FCT374A
• Buffered positive edge triggered clock
• TRI-STATE outputs for bus-oriented applications
• TTL input and output level compatible
• TTL inputs accept CMOS levels
• High current latch up immunity
• IOL = 48 mA (commercial) and 32 mA (military)
• Electrostatic discharge protection :2: 2 kV
• Inherently radiation tolerant
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
DE
CP
DE
1
20
Vee
2
19
Do
01
°0
Do
01
3
18
54FCTA
74FCTA
Input Voltage
Output Voltage
Operating Temperature (TA)
54FCTA
74FCTA
Junction Temperature (TJ)
CDIP
PDIP
4.5Vto 5.5V
4.75V to 5.25V
OVtoVee
OVtoVeG
- 55'C to + 125'C
O'Cto +70'C
175'C
140'C
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximllm loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ±10%, TA = -55'C
to + 125'C, VHe = Vee - 0.2V.
Symbol
Parameter
54FCTA174FCTA
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
",A
IlL
Input Low Current
-5.0
-5.0
",A
loz
Maximum TRI·STATE Current
10.0
10.0
-10.0
-10.0
VIK
Clamp Diode Voltage
los
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
VOL
Icc
alec
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
Conditions
Max
-0.7
-1.2
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Max
Vo
Vo
Vo
Vo
",A
V
mA
=
=
=
=
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
Vee = Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2Vor VHe; 10H = -32 ",A
V
GND
0.2
GND
0.3
0.3
0.2
0.50
0.50
0.001
0.5
Vee = Min
VIN = VIH or VIL
10H = -300",A
10H = -12mA(MiI)
10H = -15mA(Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300 ",A
V
Vee = Min
VIN = VIH or VIL
1.5
mA
Vee = Max
VIN ;;, VHe, VIN
fl = 0
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
7·28
~
10L = 300 ",A
10L = 32 mA (Mil)
10L = 48 mA (Com)
0.2V
Co)
DC Characteristics for 'FCTA Family Devices (Continued)
Typical values are at Vcc = S.OV, 2S·C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vcc = S.OV ±S%, TA = O·C to +70·C; Mil: Vcc = 5.0V ±10%, TA = -55·C
to + 125·C, VHC = Vcc - 0.2V.
Symbol
Parameter
54FCTA174FCTA
Min
ICCD
Ic
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
Typ
Conditions
Units
Max
0.15
0.25
1.5
4.0
2.0
6.0
mA/MHz
Vcc = Max
Outputs Open
OE = GND
One Input Toggling
50% Duty Cycle
Vcc = Max
Outputs Open
Icp = 10 MHz
OE = GND
II = 5.0 MHz
One Bit Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
mA
Input Hysteresis
on Clock Only
3.75
7.8
6.0
16.8
(Note 5)
Vcc = Max
Outputs Open
Icp = 10 MHz
OE = GND
II = 2.5 MHz
Eight Bits Toggling
SO% Duty Cycle
mV
200
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven input (V,N ~ 3.4V); all other inputs at Vce or GND.
Note 4: This parameter is not directly testable, but is derived lor use in Total Power Supply calculations.
Note 5: Values lor the.. conditions Bre examples 01 the ICC lormula. These limits are guaranteed but not tested.
Note 6: Ic ~ 10UIESCENT + I,NPUTS + IDYNAMIC
Ic = Icc + boice DHNT + IceD (lcp/2 + I, N,)
Icc = Quiescent Current
boice ~ Power Supply Current lor a TTL High Input (V,N = 3.4V)
DH = Duly Cycle lor TTL Inputs High
NT = Number 01 Inputs at DH
IceD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
ICp = Clock Frequency lor Register Devices (Zero lor Non·Register Devices)
I, = Input Frequency
N, = Number 01 Inputs at I,
All currents are in milliamps and all frequencies are in megahertz.
7-29
VIN = 3.4V
VIN = GND
:=.....
AC Electrical Characteristics:
Symbol
See Section 2 for Waveforms
S4FCTA174FCTA
74FCTA
S4FCTA
TA = +2S'C
Vee = S.OV
TA, Vee = Com
Rl = soon
Cl = SOpF
TA, Vee = Mil
Rl = soon
Cl = SOpF
Parameter
Fig.
No.
Typ
Min (Note 1)
Max
4.5
2.0
6.5
ns
2·8
5.5
1.5
6.5
ns
2·11
4.0
1.5
5.5
ns
2·11
Set Up Time High or Low
Dn to Cp
1.0
2.0
ns
2-10
Hold Time High or Low
Dn to Cp
0.5
1.5
ns
2-10
5.0
ns
2-9
tpLH
tpHl
Propagation Delay
CptoO n
tpZH
tPZl
Output Enable Time
tpHZ
tpLZ
Output Disable Time
tsu
tH
Cp Pulse Width
4.0
High or Low
Note 1: Minimum limits are guaranteed but not tested on propagation delays.
tw
Capacitance TA =
Symbol
CIN
Min (Note 1)
Units
+ 25'C, f
= 1.0 MHz
Parameter (Note)
Input Capacitance
Typ
Max
Unit
6
10
pF
VIN
12
pF
VOUT
Output Capacitance
8
COUT
Nole: This parameter Is measured at characterizaUon but not tested.
7-30
Condition
= OV
= OV
Max
....
Co)
~National
ADVANCE INFORMATION
~
~ Semiconductor
54FCT377A/74FCT377A
Octal D Flip-Flop with Clock Enable
General Description
Features
The FCT377A has eight edge-triggered, D-type flip-flops
with individual D inputs and a outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
• NSC 54FCTI74FCT377A is pin and functionally equivalent to IDT 54FCT/74FCT377A
• Ideal for addressable register applications
• Clock enables for address and data synchronization applications
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 4B mA (com), 32 mA (mil)
• CMOS power levels
• ESD immunity ~ 4 kV.
• Military product compliant to MIL-STD BB3
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's a output. The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable operation.
FACTTM FCTA utilizes NSC quiet series technology to provide improved quiet output switching and dynamiC threshold
performance.
FACT FCTA features undershoot corrector in addition to a
split ground bus for superior performance.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and sOle
CE
CP
CE
Qo
CP
CE
Do
D,
TL/F/'0697-1
O2
00
DO
Q,
0,
°2
Q3
D3
04
°4
05
06
°5
Q6
07
Q7
20
Vee
19
Q7
07
17
0,
Os
Os
15
Q2
O2
Qs
05
03
13
04
Q3
12
Q4
11
CP
GNO
10
TL/F/10697-2
TL/F/l0697-3
Pin Assignment
for lee
03 O2 Q2 Q, 0,
[[] [L][I] [[I [!]
Pin Names
DO-D7
CE
aO-a7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
Q3 [[J
GNO (jQ]
CP [ill
moo
ill Qo
OJCE
Q4 1ill
04
@)Q 7
~Vcc
rrn
IrnIimIrnIiZlIrn
05 Qs Q6 06 07
TL/F/10697-4
7-31
fI
~National
ADVANCE INFORMATION
~ semiconductor
54FCT174FCT521A
8-Bit Identity Comparator
General Description
Features
The 'FCT521A is an expandable 8-bit comparator. It compares two words of up to eight bits each and provides a
LOW output when the two words match bit for bit. The expansion input IA = B also serves as an active LOW enable
input.
• NSC 54FCT174FCT521A is pin and functionally equivalent to lOT 54FCT174FCT521A
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 mA (Com), 32 mA (Mil)
• CMOS power levels
• 4 kV minimum ESO immunity
• Military Product compliant to MIL-STO 883
FAC"fTM FCTA utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCTA features undershoot correction and split
ground bus for superior performance.
Logic Symbols
Connection Diagrams
I I I I I I I I I I I I I I I I
BJ A7 86 As 8s As 8. A. 83 A3 82 Az 81 AI 80 Ao
Pin Assignment
for DIP, Flatpak and SOIC
'\..../
~IA=B
20 -Vee
19 -OA=B
TL/F/l0663-1
IEEE/IEC
COMP
TA=8 .....
Ao-
I>
GI
0
AI -
-BJ
81- 5
Az- 6
82- 7
18
17
16
IS
14
A3 -
13
-As
A1-
4
8
-A7
-86
-A6
-8s
83- 9
12 -8.
GNO- 10
" -A.
A2-
TLlF/l0663-2
A3 -
A.-
Pin Assignment
forLCC
As-
AsA7-
7
80-
0
A3
82 -
8.--
81 AI
~~:O~~
81 83 -
liz Az
IIDIllOOmrn
A.1llI
8. 1m
As U1J
Q
8s
86 87 -1,;.7.;...._ _- - '
mTA=B
~Vee
HID 0A=B
IBIU1JU1JIilIIiID
TL/F110663-3
BsAsBs~BJ
TLlFI10663-4
Pin Names
Ao- A7
80-87
TA = B
OA= B
Description
Word A Inputs
Word 8 Inputs
Expansion or Enable Input
Identity Output
7-32
r----------------------------------------------------------------------------,
~National
en
w
w
»
~ Semiconductor
54FCT 17 4FCT533A
Octal Transparent latch with TRI-STATE® Outputs
General Description
Features
The 'FCT533A consists of eight latches with TRI-STATE
outputs for bus organized system applications. The flip-flops
appear transparent to the data when latch Enable (lE) is
HIGH. When lE is lOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is lOW. When OE is HIGH the bus output is in
the high impedance state. The 'FCT533A is the same as the
'FCT373A, except that the outputs are inverted.
iii NSC 54FCT/74FCT533A is pin and functionally equiva-
FACT FCTA utilizes NSC quiet series technology to provide
improved quiet output switching and dynamic threshold performance.
lent to IDT 54FCT174FCT533A
TRI-STATE outputs for bus interfacing
Input clamp diodes to limit bus reflections
TTL/CMOS input and output level compatible
IOL = 48 mA (Com), 32 mA (Mil)
II CMOS power levels
1!1 4 kV minimum ESD immunity
II Military product compliant to Mil-STD 883
III Inherently radiation tolerant
•
•
II
..
FACT FCTA features undershoot correction and split
ground bus for superior performance.
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
IEEE/IEC
OE
LE
LE
OE
TL/F/1063B-4
OE
1
20
Vee
00
2
19
3
18
°7
07
Os
DO
01
°0
Do
°1
01
4
17
O2
03
°2
03
°1
5
16
Os
6
15
04
°4
7
14
05
°5
Os
°2
O2
03
°5
05
04
03
°7
GNO
Os
07
8
13
12
TLlF/1063B-l
°4
LE
TL/F/1063B-2
Pin Assignment
forlCC
~~020101
II][ID !II
[ID
m
rn
03
GNO [Q]
LE [j]
moo
III 00
iIlOE
°41rn
°4 1rn
lim 07
@JVcc
1BI1rn1i]J1iZl1i]J
Os as as Os I?
TL/F/1063B-3
7-33
•
00-0 7
LE
OE
00-0 7
Function Table
Description
Pin Names
Inputs
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary TRI-STATE Outputs
Output
LE
OE
D
0
H
H
L
L
L
L
H
H
L
L
H
X
X
00
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Logie(O) or logie(l) must be valid Input Level
Functional Description
The 'FCT533A contains eight D-type latches with TRISTATE output buffers. When the Latch Enable (LE) input is
HIGH, data on the On inputs enters the latches. In this condition the latches are transparent and the latch output will
change state each time its 0 input changes. When LE is
LOW, the latches store the information that was present on
the 0 inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW the latch contents are presented inverted at the outupts 07-00. When
DE is HIGH the buffers are in the high impedance mode but
this does not interfere with entering new data into the
latches.
Logic Diagram
TL/F/10638-5
Please note that this diagram is provided only lor the understanding 01 logic operations and should not be used to estimate propagation delays.
7-34
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
54FCTA
74FCTA
Temperature Voltage with respect to GND (VrERM)
54FCTA
-0.5Vto +7.0V
74FCTA
-0.5Vto +7.0V
Input Voltage
Output Voltage
Temperature under Bias (T BIAS)
74FCTA
54FCTA
- 55'C to + 125'C
- 65'C to + 135'C
Storage Temperature (Tsm)
74FCTA
54FCTA
Operating Temperature (TA)
54FCTA
74FCTA
- 55'C to + 125'C
-65'Cto +135'C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (Pr)
0.5W
DC Output Current (lour)
4.5Vt05.5V
4.75V to 5.25V
OVtoVee
OVtoVee
-55'Cto +125'C
O'Cto +70'C
175'C
140'C
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT FCT circuits outside databook specifications.
DC Characteristics for FCTA Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ± 10% TA = -55'C
to + 125'C.
Symbol
Parameter
54FCTA174FCTA
Min
VIH
Minimum HIGH Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
r- A
IlL
Input Low Current
-5.0
-5.0
r- A
loz
Maximum TRI-STATE
Current
10.0
10.0
-10.0
-10.0
r- A
-1.2
V
VIK
Clamp Diode Voltage
los
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VHe
Vee
2.4
4.3
2.4
4.3
VOL
Maximum Low Level
Output Voltage
Conditions
Max
-0.7
GND
mA
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Max
Va
Va
Va
Va
=
=
=
=
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
Vee = Min; liN = -18 mA
Vee = Max(Note1);Vo = GND
Vee = 3V; VIN = 0.2Vor VHe; 10H = -32 r-A
V
Vee = Min
10H = -300 r-A
VIN = VIH or VIL
10H = -12mA(MiI)
10H = -15 mA (Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300 r-A
0.2
GND
0.2
0.3
0.50
0.3
0.50
V
Vee = Min
10L = 300 r-A
VIN = VIH or VIL
10L = 32 mA (Mil)
10L = 48 mA (Com)
7-35
DC Characteristics for FCTA Family Devices
Typical values are at Vee = 5.0V, 25°C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vee = 5.0V ±5%, TA = O"C to +70"C; Mil: Vee = 5.0V ±10% TA = -55°C
to + 125°C. (Continued)
Symbol
Parameter
54FCTAl74FCTA
Min
Icc
Maximum Quiescent
Supply Current
Alec
Quiescent Supply Current;
TTL Inputs HIGH
ICCD
Dynamic Power
Supply Current (Note 4)
Total Power
Supply Current (Note 6)
Conditions
Max
0.001
1.5
mA
Vee = Max
VIN ~ VHe, VIN
II = 0
0.5
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
VIN ~ VHe
VIN S; 0.2V
mA/MHz
Vce = Max
Outputs Open
OE = GND
LE = Vee
One Input Toggling
50% Duty Cycle
Vee = Max
Outputs Open
OE = GND'
LE = Vee
fl=10MHz
VIN ~ VHe
VIN S; 0.2V
0.25
Ic
Units
Typ
0.45
1.5
4.5
1.8
5.0
mA
3.0
8.0
5.0
14.5
0.2V
VIN = 3.4V
VIN = GND
One Bit Toggling
50% Duty Cycle
(Note 5)
Vee = Max
Outputs Open
OE= GND
LE = Vee
II = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
Input Hysteresis on Clock Only
200
mV
VH
Nole I: Maximum test duration not to exceed one second, not more than one output shorted at one lime.
Nole 2: This parameter guaranteed but not tested.
Note 3: Per TTL drtven input (YIN = 3.4V); all other Inputs at Vee or GND.
Note 4: This parameter Is not directly testable. but is dertved lor use In Total Power Supply calculations.
Nole 5: Values lor these conditions are examples 01 the lee lormula. These limits are guaranteed but not testad.
Note 6: Ic = laUIEScENT + IINPUTS + IDYNAMIC
Ic = lee + Alee DHNT + leeD (lcp/2 + II NI)
lee = Quiescent Current
Alee = Power Supply Current lor a TTL High Input (YIN = 3.4V)
DH = Duty Cycle lor TTL Inputs High
NT = Number 01 Inputs at DH
leeD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero lor Non-Register Devices)
II = Input Frequency
NI = Number 01 Inputs at II
All currents are In milliamps and alilrequencies are In megahertz.
7·36
S;
VIN;;: VHe
VIN S; 0.2V
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
54FCTAl74FCTA
74FCTA
54FCTA
TA = +25"C
Vee = +5.0V
TA. Vee = Com
RL = 500n
CL = 50pF
TA. Vee = Mil
RL = 500n
CL = 50pF
Min
Parameter
Symbol
See Section 2 for Waveforms
Units
Fig.
No.
Typ
Min
Max
tpLH
tpHL
Propagation Delay
On to On
4.0
1.5
5.2
ns
2-8
tpLH
tpHL
Propagation Delay
LEtoOn
7.0
2.0
8.5
ns
2-8
tpZH
tpZL
Output Enable
Time
5.5
1.5
6.5
ns
2-11
tpHZ
tpLZ
Output Disable
Time
4.0
1.5
5.5
ns
2-11
ts
Set UpTime
High or Low
Onto LE
1.0
2.0
ns
2-10
HOLD Time
High or Low
Dn toLE
1.0
1.5
ns
2-10
5.0
ns
2-9
tH
tw
LE Pulse Width
4.0
High or Low
Minimum limits are guaranteed but not tested on Propagation Delays
Capacitance rrA =
Symbol
+ 25C, f = 1.0 MHz)
Parameter
Typ
Max
Units
Conditions
Cin
Input Capacitance
6
10
pF
VIN = OV
Cout
Output Capacitance
8
12
pF
Vout = OV
Note: This
parameter is measured at characterization but not tested
7·37
Max
~National
~ Semiconductor
54FCT /7 4FCT534A
Octal 0 Flip-Flop with TRI-STATE® Outputs
General Description
Features
The 'FCT534A is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and
TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all
flip-flops. The 'FCT534A is the same as the 'FCT374A except that the outputs are inverted.
• NSC 54/74FCT534A is pin and functionally equivalent
to IDT 54174FCT534A
• Edge-triggered D-type inputs
• Buffered positive edge-triggered clock
• TTL input and output level compatible
• TTL inputs accept CMOS levels
• High current latch up
• IOL = 48 mA (Com), 32 mA (Mil)
• Military product compliant to MIL-STD-883
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
tor DIP, Flatpak and SOIC
IEEE/IEC
DE
CP
DE
TL/F/l0819-1
Do
°0
01
°1
OE
1
00
2
00
01
3
4
°7
07
06
5
°6
6
°s
05
04
20
O2
°2
°1
03
04
°3
05
06
07
°5
°2
O2
03
8
13
03
9
12
GNO
10
11
°4
°6
°7
7
TL/F/l0619-2
Pin Names
Do-D7
CP
OE
00-0 7
Vee
°4
CP
TL/F/l0619-3
Description
Pin Assignment
torlCC
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
Complementary TRI-STATE Outputs
1]][IJ1]][[]1±l
~D:z°20101
03 []]
GNOIiQ)
CP Ii]
moo
III 00
mOE
°
@Ivee
4 011
[i]] 07
°4@
1i3]1i])1i§J1iZl1i§J
DsOs0606~
TL/F/l0619-4
7-38
Functional Description
The 'FCT534A consists of eight edge-triggered flip-flops
with individual D-type inputs and TRI-STATE complementary outputs. The buffered clock and buffered Output Enable
are common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold times requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Logic Diagram
TL/F/l0619-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Function Table
Inputs
Output
CP
OE
D
0
.../
L
L
L
H
H
L
L
H
X
X
00
.../
L
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW·to·HIGH Clock Transition
Z = High Impedance
'0'0 = Value stored from previous clock cycle
..r
,.
7-39
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 1)
It Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors tor availability and specifications.
Terminal Voltage with Respect
to GND (VTERM)
54FCTA
-0.5Vto +7.0V
74FCTA
-0.5Vto +7.0V
Temperature Under Bias (TSIAS)
74FCTA
- 55'C to + 125'C
54FCTA
- 65'C to + 135'C
Storage Temperature (TSTG)
74FCTA
-55'Cto + 125'C
54FCTA
-65'C to + 150'C
Power Dissipation (PT)
0.5W
DC Output Current (lOUT)
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specHicatlons should be met. without
exception. to ensure that the system design is reliable over Hs power supply.
temperature. and output/Input loading variables. National does not recommend operation 01 FACTTM FCT circuits outside databook specifications.
Supply Voltage (Vee>
54FCTA
74FCTA
Input Voltage
Output Voltage
Operating Temperature (TAl
54FCTA
74FCTA
Junction Temperature (TJ)
CDIP
PDIP
4.5Vt05.5V
4.75V to 5.25V
OV to Vee
OVtoVee
- 55'C to + 125'C
-O'C to + 70'C
175'C
140'C
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max. use the value
specified for the appropriate device type: Com: Vee = 5.0V ±50/0. TA = O'C to +70'C; Mil: Vee = 5.0V ±100/0, TA = -55'C
to + 125'C. VHe = Vee - 0.2V.
Symbol
Parameter
54FCTA174FCTA
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
Conditions
Max
2.0
V
0.8
V
Input High Current
5.0
5.0
",A
IlL
Input Low Current
-5.0
-5.0
",A
loz
Maximum TRI-STATE Current
10.0
10.0
-10.0
-10.0
-1.2
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Max
Vo
Vo
Vo
Vo
",A
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
Vee = Min; IN = -18 mA
Clamp Diode Voltage
los
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
Vee = 3V; VIN = 0.2V or VHe; 10H = -32 ",A
Vee
4.3
4.3
Vee = Min
VIN = VIH or VIL
VH
Maximum Low Level
Output Voltage
Input Hysteresis on
Clock Only
VHe
2.4
2.4
V
=
=
=
=
VIK
VOL
-0.7
Vee = Max
mA
V
GND
0.2
GND
0.3
0.3
0.2
0.5
0.5
200
10H = - 300 p,A
10H = -12 mA (Mil)
IOH = -15 mA (Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300 ",A
V
mV
7-40
Vee = Max (Note 1); Vo = GND
Vee = Min
VIN = VIH or VIL
10L = 300 ",A
10L = 32 mA (Mil)
10L = 48 mA (Com)
~----------------------------------------------------------------------------------------~
DC Characteristics for 'FCTA Family Devices (Continued)
Typical values are at Vcc = 5.0V, 25·C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vcc = 5.0V ± 5%, T A = O·C to + 70·C; Mil: Vcc = 5.0V ± 10%, T A = - 55·C
to + 125·C, VHC = Vcc - 0.2V.
Symbol
Parameter
54FCTA174FCTA
Min
Maximum Quiescent
Supply Current
Icc
alcc
Quiescent Supply Current;
TTL Inputs HIGH
ICCD
Dynamic Power
Supply Current (Note 4)
Total Power Supply
Current (Note 6)
Ic
Max
0.001
1.5
mA
Vcc = Max
VIN :;;, VHC, VIN ,,; 0.2V
fl = 0
0.5
2.0
mA
Vcc = Max
VIN = 3.4V (Note 3)
0.40
1.5
4.0
1.8
6.0
mA/MHz
Co)
:=
Conditions
Units
Typ
0.15
tn
Vcc = Max
Outputs Open
OE = GND
One Input Toggling
500/0 Duty Cycle
VIN:;;' VHC
VIN"; 0.2V
Vcc = Max
Outputs Open
fcp = 10 MHz
OE = GND
VIN:;;' VHC
VIN"; 0.2V
fl = 5 MHz
One Bit Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
(Note 5)
VIN:;;' VHC
VIN"; 0.2V
mA
3.0
7.8
5.0
16.8
Vcc = Max
Outputs Open
OE = GND
fcp = 10MHz
fl = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven input (VIN
= 3.4V); all other Inputs at Vcc or GND.
Note 4: This parameter is not directly testable, but Is derived for use In Total Power Supply calculations.
Note 5: Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Note 6: Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .!.Icc DHNT + ICCD (fcp/2 + fl NI)
Icc = Quiescent Current
.!.Icc = Power Supply Current for a TTL High Input (VIN
= 3.4V)
DH = Duty Cycle for TTL inputs High
NT
= Number of Inputs at DH
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
ICCD
fep = Clock Frequency for Register Devices (Zero for Non·Reglster Devices)
fl
= Input Frequency
NI = Numbers 01 Inputs at II
All currents are in milliamps and all frequencies are in megahertz.
•
7·41
AC Electrical Characteristics:
54FCTAl74FCTA
74FCTA
54FCTA
TA = +25"C
Vee = 5.0V
TAo Vee =
Mil
CL = 50pF
TAVee =
Com
CL = 50pF
Parameter
Symbol
See Section 2 for Waveforms
Typ
Min
(Note 1)
Max
Min
(Note 1)
Units
Fig.
No.
Max
IpLH
IpHL
Propagalion Delay
CploOn
4.5
1.5
6.5
ns
2-9
IpZH
IpZL
Oulput Enable
Time
5.5
1.5
6.5
ns
2-11
IpHZ
tpHL
Output Disable
Time
4.0
1.5
5.5
ns
2-11
Is
Set Up TIme High or Low
DntoCP
1.0
2.0
ns
2-10
Ih
Hold Time High or Low
Dn to CP
1.0
1.5
ns
2-10
5.0
ns
2-9
CP Pulse Width
4.0
High or Low
Note 1: Minimum limits guaranteed but not tested on propagation delays.
Iw
Capacitance TA =
Symbol
+ 25"C, fl
= 1.0 MHz
Parameter
Typ
Max
Units
Conditions
= OV
= OV
CIN
Input Capacitance
6
10
pF
VIN
Cour
Outpul Capacitance
8
12
pF
Your
Note: This parameter is measured at characterization
but not tested.
7-42
r----------------------------------------------------------------------------, en
.j:Io
~
~National
~ Semiconductor
54FCT17 4FCT543A
Octal Registered Transceiver
General Description
Features
The FCT543A octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are
provided for each register to permit independent control of
inputting and outputting in either direction of data flow.
• NSC 54FCT174FCT543A is pin and functionally equivalent to IDT 54FCT174FCT543A
• Speed controls for data flow in each direction
• Back to back latched transceiver
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 64 mA (com), 48 mA (mil)
• CMOS power levels
• 4 kV minimum ESD immunity
iIiI Military product complaint to MIL-STD 883
FACTTM FCTA utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCTA features undershoot correction and split
ground bus for superior performance.
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and SOIC
AO········ .A7
LEBA
aEAB
aEBA
aEBA
CEAB
CEBA
24
2
Vee
23
CEBA
AO
22
Bo
A1
21
B1
A2
LEAB
B2
A3
LEBA
B3
B4
B5
B6
B7
TUF/10667-1
LEAB
GND
12
aEAB
TLlF/10667-3
Pin Names
OEAB
OEBA
CEAS
CEBA
LEAS
LEBA
Ao-A7
Pin Assignment
forLCC
Description
A-to-S Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-S Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-S Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A TRI-STATE® Outputs
B-to-A Data Inputs or
A-to-B TRI-STATE Outputs
A6 As A4 HC A3 A2 A1
Il]) Ijg III rn:J [l][!l rn:J
A71il1
mAo
rn OEBA
CEAB ~
GND Ii]
NC Ii]!
I1J LEBA
[i] NC
~Vcc
OEAB Ii§]
LEAB Iill
~ CEBA
~Bo
B71iID
'OO~(JI(JII::Jt7'
1iID~~~~~~
B6 Bs B4 NC B3 B2 B1
TUF/10667-4
7-43
•
Functional Description
Data I/O Control Table
The FCT543A contains two sets of eight D-type latches,
with separate input and output controls for each set. For
data flow from A to B, for example, the A-to-B Enable
(CEAB) input must be LOW in order to enter data from AoA7 or take data from Bo-B7, as indicated in the Data I/O
Control Table. With CEAB LOW, a LOW signal on the A-to-B
Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB
signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and
OEAB both LOW, the TRI-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the
CEBA, LEBA and OEBA inputs.
Input
CEAB
LEAB
OEAB
H
X
X
H
L
X
X
X
X
X
H
L
L
X
L
Latch Status
Output Buffers
Latched
Latched
Transparent
HighZ
-
HighZ
Driving
-
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-tOoB data flow shown; B·to·A flow control
is the same, except using CEBA, LEB and OEBA
Logic Diagram
Ao--!-.......+----KK
..
AI
A2
A3
A4
DETAIL Ax7
A5
A6
A7
OEBA
r-,..----- OEAB
'------HX
CEBA
LEBA
L-----LEAB
TLlF/l0667-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
7-44
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
54FCTA
74FCTA
Terminal Voltage with Respect to GND (VTERM)
-0.5V to + 7.0V
54FCTA
74FCTA
-0.5V to + 7.0V
4.5Vt05.5V
4.75V to 5.25V
Input Voltage
OVtoVee
Output Voltage
OVtoVee
Temperature under Bias (TSIAS)
74FCTA
54FCTA
-55·C to + 125·C
-65·Cto + 135·C
Storage Temperature (TSIG)
74FCTA
54FCTA
Operating Temperature (TA)
54FCTA
74FCTA
-55·C to + 125·C
-65·Cto +150·C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (PT)
0.5W
DC Output Current (lOUT)
-55·Cto + 125·C
O·Cto +70·C
175·C
140·C
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. The databook specifications
should be met. without exception. to ensure that the system design is reli·
able over its power supply. temperature, and output/input loading variables.
DC Characteristics for 'FCTA Family Device
Typical values are at Vee = 5.0V. 25·C ambient and maximum loading. For test conditions shown as Max. use the value
specified for the appropriate device type: Com: Vee = 5.0V ± 5%. TA = O·C to + 70·C; Mil: Vee = 5.0V ± 10%. TA = -55·C
to + 125·C. VHe = Vee - 0.2V
Symbol
Parameter
54FCTA174FCTA
Min
Typ
Conditions
Units
Max
V,H
Minimum High Level
Input Voltage
V,L
Maximum Low Level
Input Voltage
0.8
V
I'H
Input Current
(Except liD Pins)
5.0
5.0
p.A
Vee
=
Max
V,
V,
I,L
Input Low Current
(Except 1/0 Pins)
-5.0
-5.0
p.A
Vee
=
Max
V,
V,
I'H
Input High Currents
(1/0 Pins)
15
15
p.A
Vee
=
Max
V,
V,
I,L
Input Low Currents
(1/0 Pins)
-15
-15
p.A
Vee
=
Max
V,
V,
V
Vee
mA
Vee
=
=
Max (Note 1); Vo
Vee
=
3V; Y,N
2.0
V
-0.7
V,K
Clamp Diode Voltage
los
Short Circuit Current
-60
-120
Minimum High Level
Output Voltage
2.8
3.0
VOH
VOL
lee
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
VHe
2.4
2.4
-1.2
Vee
4.3
4.3
V
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
V
0.001
1.5
mA
=
=
=
3V; Y,N
=
=
=
=
=
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
Vee
2.7V
0.5V
GND
-18 mA
=
GND
= -32 p.A
= -300 p.A
= -12 mA(MiI)
= -15 mA (Com)
0.2V or VHe; 10H
10H
10H
10H
Vee = Min
Y,N = V,H or V,L
Vee
7·45
Min; IN
=
=
=
=
0.2V or VHe; 10L
Vee = Min
Y,N = V,L or V,L
Vee = Max
Y,N ;;, VHe. Y,N :5: 0.2V
I, = 0
10L
10L
10L
=
=
=
=
300 p.A
300 p.A
48 mA (Mil)
64 mA (Com)
•
~
~
DC Characteristics for 'FCTA Family Device
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vec = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ±10%, TA = -55'C
to + 125'C, VHe = Vcc -0.2V (Continued)
Symbol
54FCTA174FCTA
Parameter
Min
alee
Quiescent Supply Current;
TTL Inputs HIGH
ICCD
Dynamic Power
Supply Current (Note 4)
Typ
Max
0.5
0.2
0.25
Ic
0.55
Units
rnA
rnA/MHz
Total Power
Supply Current (Note 6)
1.5
4.0
1.8
6.0
16.5
5.0
21.75
Vce = Max
VIN = 3.4V (Note 3)
Vcc = Max Outputs Open
CEAB & OEAB = GND
CEBA = Vcc
One Input Toggling
50% Duty Cycle
Vcc = Max
Outputs Open
tcp = 10 MHz
50% Duty Cycle
CEAB & OEAB = GND
CEBA = Vee
fcp = LEAB = 10 MHz
One BitToggling
atfl = 5MHz
50% Duty Cycle
rnA
3.0
Conditions
(Note 5)
Vcc = Max
Outputs Open
tcp = 10 MHz
50% Duty Cycle
CEAB & OEAB = GND
CEBA = Vcc
fcp = LEAB = 10 MHz
fl = 2.5 MHz
Eight Bits Toggling
atfl = 5 MHz
50% Duty Cycle
Note 1: Maximum test duration nollo exceed one second, nol more than one output shorted at one lime.
Note 2: This parameter guaranteed bul not lested.
Note 3: Per TTL driven input (VIN = 3.4V); all other Inpuls at Vcc or GND
Note 4: This para meier Is not directly teslable. but Is derived for use In Total Power Supply calculations.
Note 5: Values for these conditions are examples of the Icc formula. These IimHs are guaranteed but not tested.
Note 6: Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + alcc DHNT + ICCD (fcp/2 + fl NI)
Icc = Quiescent Current
alcc = Power Supply Current for a TTL High Inpul (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero lor Non-Register Devices)
II = Input Frequency
NI = Number 01 Inpuls at II
All currents are in millamps and all frequencies are in megahertz.
7-46
VIN = 3.4V
VIN = GND
VIN;;'; VHC
VIN :S;;'O.2V
VIN = 3.4
VIN = GND
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
54FCTA174FCTA
74FCTA
54FCTA
TA = +25'C
Vee = 5.0V
TA. Vee = Com
RL = 500n
CL = 50pF
TA. Vee = Mil
RL = 50 on
CL = 50pF
Typ
Min
(Note)
Max
Min
Units
Fig.
No.
Max
tpLH
tpHL
Propagation Delay
Transparent Mode
An to Bn or Bn to An
1.5
6.5
ns
2-8
tpLH
tpLH
Propagation Delay
LEABtoAn•
LEABtoB n
1.5
8
ns
2-8
tPZH
tPZL
Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
2
9
ns
2-11
tpHZ
tpLZ
Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
2
7.5
ns
2-11
tsu
Set UpTime
High or Low
An or Bn to LEBA or LEAB
2
ns
2-10
2
ns
2-10
Hold Time
tH
Note: Minimum propagation delays are guaranteed but not listed.
Capacitance TA =
Symbol
+ 25'C. f = 1.0 MHz
Typ
Max
Units
CIN
Input Capacitance
Parameter (Note)
6
10
pF
VIN = OV
Conditions
COUT
Output Capacitance
8
12
pF
VOUT = OV
Note: This parameter is measured at characterization but not tested.
•
7-47
~National
~ semiconductor
54FCT17 4FCT544A
Octal Registered Transceiver
General Description
Features
The 'FCT544A octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are
provided for each register to permit independent control of
inputting and outputting in either direction of data flow. The
'FCT544A inverts data in both directions.
• NSC 54FCT174FCT544A is pin and functionally equivalent to IDT 54FCT174FCT544A
• Sack to back registers for storage separate controls for
data flow in each direction
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 64 mA (Com), 48 mA (Mil)
• CMOS power levels
• 4 kV minimum ESD immunity
• Military Product compliant to MIL-STD 883
FACTTM FCTA utilizes NSC quiet series technology to provide improved quiet output switching and dynamiC threshold
performance.
FACT FCTA features undershoot correction and split
ground bus for superior performance.
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment for
DIPandSOIC
CEAB
LEAB
OEAB
CEBA
OEAB
LEBA
OEBA
OEBA
CEAB
CEBA
Au
LEAB
AI
LEBA
A2
A3
A4
As
TLfFfl0669-1
As
A7
LEBA
1
24
OEBA
2
23
Ao
3
22
80
AI
4
21
81
A2
5
20
82
A3
6
19
83
A4
7
18
AS
8
17
8"
8s
AS
9
16
86
A7
10
15
87
CEAB
11
14
LEAB
GND
12
13
OEAB
Vee
CEBA
TLfFfl0669-3
Pin Names
OEAS
OESA
CEAS
CESA
LEAS
LESA
Ao-Poq
80-8 7
Description
Pin Assignment
forLCC
A-to-S Output Enable Input (Active LOW)
S-to-A Output Enable Input (Active LOW)
A-to-S Enable Input (Active LOW)
S-to-A Enable Input (Active LOW)
A-to-S Latch Enable Input (Active LOW)
S-to-A Latch Enable Input (Active LOW)
A-to-S Data Inputs or S-to-A
TRI-STATE® Outputs
S-to-A Data Inputs or A-to-S
TRI-STATE Outputs
A6 As A4 NC A3 A2 AI
1i]1iQI1ID1!I1ZI1!li]]
111111111111_111111111
A71l]
CEAB MI
GND IBI
NC Il]I
DEAB IiID
LEAB IiZI
mAO
OEBA
LEBA
[IJ NC
rn
m
~Vee
~ Ill] CEBA
~ ~Bo
~1iID
'-_111___
111 ......
111111
......,111111---III,¥
1iID~~~I~H~~
Bs Bs B4 NC B3 B2 Bl
TLfFfl0669-4
7-48
,---------------------------------------------------------------------------------, en
.".
~
Functional Description
The 'FCT544A contains two sets of eight D-type latches,
with separate input and output controls for each set. For
data flow from A to B, for example, the A-to-B Enable
(CEAB) input must be LOW in order to enter data from AoA7 or take data from 80-87, as indicated in the Data I/O
Control Table. With CEAB LOW, a LOW signal on the A-to-B
Latch Enable (LEAB) input makes the A-to-S latches transparent; a subsequent LOW-to-HIGH transition of the LEAB
signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and
OEAB both LOW, the TRI-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the
CESA, LEBA and OEBA outputs.
Data I/O Control Table
Input
LEAB
OEAB
H
X
X
X
H
L
X
X
X
X
H
L
CEAB
L
X
L
Latch
Status
Output
Buffers
Latched
Latched
Transparent
High-Z
High-Z
Driving
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A·to·B data flow shown; B·to-A flow control is the same, except using CEBA,
LEBA and OEBA.
Logic Diagram
Ao---o-+----KK
_.
A,
B,
A2
B2
A3
B3
A4
DETAIL Ax7
B4
As
Bs
As
B6
A7~
B7
aEBA
r-,..----- aEAB
'-------HX
CEBA
LEBA
L...----LEAB
TL/F/l0669-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays•
•
7-49
Absolute Maximum Ratings (Note)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
54FCTA
74FCTA
Terminal Voltage with Respect to GND (VTERM)
-0.5Vto +7.0V
54FCTA
74FCTA
-0.5Vto +7.0V
Input Voltage
OVtoVee
Output Voltage
OVtoVee
Temperature under Bias (TBIAS)
54FCTA
74FCTA
-65·C to + 135·C
-55·C to + 125·C
Operating Temperature (TAl
54FCTA
74FCTA
Storage Temperature (TSTG)
54FCTA
74FCTA
-65·C to + 150"C
-55·Cto + 125·C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (PT)
4.5Vto 5.5V
4.75V to 5.25V
- 55·C to + 125·C
O·Cto +70·C
175·C
140·C
0.5W
DC Output Current (lOUT)
120mA
Note: Absolute maximum ratings are those values beyond which damage to
the device may occur. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. The databook specHications should
be met, without exception, to ensure that the system design is reliable over
its power supply, temperature, and output/input loading variables.
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, + 25·C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ± 5%, TA = O·C to + 70·C; Mil: Vee = 5.0V ± 10%, TA = -55·C
to + 125·C.
Symbol
Parameter
54FCTA174FCTA
Min
Typ
Units
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
0.8
V
IIH
Input High Current
(Except 110 Pins)
5.0
5.0
/J- A
IlL
Input Low Current
(Except 110 Pins)
-5.0
-5.0
/J- A
15
15
/J- A
-15
-15
/J- A
IIH
2.0
V
Input High Currents
(110 Pins)
IlL
Input Low Currents
(110 Pins)
VIK
Clamp Diode Voltage
los
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
VOL
Icc
alec
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
Quiescent Supply Current;
TTL Inputs HIGH
Conditions
Max
-0.7
-1.2
V
mA
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = Max
VI = 0.5V (Note 2)
VI = GND
Vee = Max
VI = Vee
VI = 2.7V (Note 2)
Vee = MAx
VI = 0.5V (Note 2)
VI = GND
Vee = Min; IN = -18 mA
Vee = Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2V or VHe; 10H = -32/J-A
V
Vee = Min
VIN = VIH or VIL
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
V
0.001
1.5
mA
Vee = Max
VIN .~ VHe, VIN ,,;: 0.2V
fl = 0
0.5
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
7-50
10H = -300/J-A
10H = -12 mA (Mil)
10H = -15 mA (Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300/J-A
Vee = Min
VIN = VIH or VIL
10L = 300/J-A
IL = 48 mA (Mil)
10L = 64 mA (Com)
r---------------------------------------------------------------------------------, .&:10
~
DC Characteristics for 'FCTA Family Devices (Continued)
~
Typical values are at Vee = S.OV, +2S·C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vee = S.OV ±S%, TA = O·C to +70·C; Mil: Vec = S.OV ±10%, TA = -SS·C
to +12S·C.
Conditions
Units
mA/MHz
1.8
Vcc = Max
Outputs Open
CEAB + OEAB = GND
CEBA = Vcc
One Input Toggling
SO% Duty Cycle
Vee = Max
Outputs Open
fcp = 10 MHz
SO% Duty Cycle
CEAB + OEAB = GND
CEBA = Vee.
Icp = LEAB = 10 MHz
One Bit Toggling
alll = S MHz
50% Duty Cycle
6.0
VIN = 3.4V
VIN = GND
mA
3.0
16.S
5.0
21.75
(Note S)
Vcc = Max
Outputs Open
Icp = 10MHz
SO% Duty Cycle
CEAB + OEAB = GND
CEBA = Vee.
Icp = LEAB = 10 MHz
Eight Bits Toggling
at II = S MHz
SO% Duty Cycle
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TIL driven input (VIN
= 3.4); all other inputs at Vcc or GND.
Note 4: This parameter is not directly testable, but is derived lor use In Total Power Supply calculations.
Note 5: Values lor these conditions are examples 01 the Icc lormula These limits are guaranteed but not tested.
Note 6: Ic = laUIEscENT + IINPUTS + IDYNAMIC
Ic = Icc + Alce DHNT + IceD (Icp/2 + IINI)
Ice = Quiescent Current
Alcc = Power Supply Current lor a TIL High Input (VIN = 3.4V)
DH = Duty Cycle lor TIL Inputs High
NT = Number 01 Inputs at DH
IceD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero lor Non·Register Devices)
II = Input Frequency
NI = Number 01 Inputs at II
All currents are in milliamps and all Irequencies are in megahertz.
7·S1
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
Symbol
See Section 2 for Waveforms
54FCTA174FCTA
74FCTA
54FCTA
TA = +25°C
Vee = 5.0V
TA. Vee = Com
RL = soon
CL = 50pF
TA. Vee = Mil
RL = soon
CL = 50pF
Typ
Min (Note 1) Max
Min
Parameter
Units
Fig.
No.
Max
tpLH
tpHL
Propagation Delay
Transparent Mode
An to Bn or Bn to An
1.5
7.0
ns
2-8
tpLH
tpHL
Propagation Delay
LEABtoA n,
LEABtoB n
1.5
8.0
ns
2-8
tPZH
tpZL
Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
1.5
9
ns
2-11
tpHZ
tpLZ
Output Disable Time
CEBA or OEAB to An or Bn
CEBA or OEAB to An or Bn
1.5
7.5
ns
2-11
tsu
Setup Time
High or Low
An or Bn to LEBA or LEAB
2
ns
2-10
Hold Time
High or Low
An or Bn to LEBA or LEAB
2
ns
2-10
tH
Note 1: Minimum propagation delays are guaranteed but not tested.
Capacitance TA =
Symbol
+ 25°C, f = 1.0 MHz
Parameter
(Note)
Typ
Max
Units
Conditions
CIN
Input Capacitance
6
10
pF
VIN = OV
COUT
Output Capacitance
B
12
pF
VOUT = OV
Note: This parameter Is measured at characterization but not tested.
7-52
-
r----------------------------------------------------------------------------,
U1
Q)
~
~National
~ Semiconductor
54FCT17 4FCT563A
Octal Latch with TRI-STATE® Outputs
General Description
Features
The 'FCT563A is a high-speed octal latch with buffered
common Latch Enable (LE) and buffered common Output
Enable (OE) inputs.
• Inputs and outputs on opposite side of package allow
easy interface with microprocessors
• Useful as input or output port for microprocessors
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 mA (Com), 32 mA (Mil)
• CMOS power levels
• 4 kV minimum ESD immunity
• Military product compliant to MIL-STD-883
• Inherently radiation tolerant
The 'FCT563A device is functionally identical to the
'FCT573A, but with inverted outputs.
FACTTM FCTA utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCTA features undershoot correction and split
ground bus for superior performance.
Ordering Code: See Section 8
logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
TlIF/l0639-1
DE
DE
20
Vee
LE
DO
2
19
°0
00
Dl
3
18
°1
D2
4
17
D3
5
16
°2
03
D4
6
15
°4
Ds
7
14
°s
D6
8
13
°6
12
°7
°0
°1
°1
°2
°2
°3
D4
°3
Ds
°5
°4
D6
°6
~
°7
~
GND
lE
TUF/l0639-2
Pin Names
Do-D7
LE
OE
0 0-0 7
TL/F/l0639-3
Description
Pin Assignment
forlCC
Data Inputs
Latch Enable Input
TRI-STATE Output Enable Input
TRI-STATE Latch Outputs
~%04~Dz
I?[[]Dm
1!][1][!Jmm
OI
moo
GNO fig
mOE
LEI]]
071111
~VCC
0all]
lim 00
~~1lID1l1I1lID
0s
°° 02 0,
4 3
TL/FI10639-4
7-53
•
Function Table
Functional Description
The 'FCT563A contains eight D-type latches with TRISTATE complementary outputs. When the Latch Enable
(LE) input is HIGH, data on the Dn inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes.
When LE is LOW the latches store the information that was
present on the D inputs a setup time preceding the HIGH-toLOW transition of LE. The TRI-STATE buffers are controlled
by the Output Enable (OE) input. When DE is LOW, the
buffers are in the TRI-STATE mode. When OE is HIGH the
buffers are in the high impedance mode but that does not
interfere with entering new data into the latches.
Inputs
Outputs
OE
LE
D
0
H
L
L
L
X
X
H
H
L
L
H
Z
H
L
NC
X
Function
High-Z
Transparent
Transparent
Latched
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
TL/F/10839-6
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
7-54
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Terminal Voltage with Respect to GND (VTERM)
54FCTA
-0.5Vto +7.0V
74FCTA
-0.5Vto +7.0V
Temperature under Bias (TSIAS)
74FCTA
-55'C to + 125'C
54FCTA
- 65'C to + 135'C
Storage Temperature (TSTG)
74FCTA
- 55'C to + 125'C
54FCTA
-65'C to + 150'C
Power Dissipation (PT)
0.5W
DC Output Current (lOUT)
120mA
Nole 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The dalabook specifications should be met. without
exception. to ensure thai the system design is reliable over ils power supply.
temperalure. and outputllnpulloading vartables. National does not recom·
mend operation 01 FACTTM circuits outside databook specifications.
Supply Voltage (Vee)
54FCTA
74FCTA
Input Voltage
Output Voltage
Operating Temperature (TA)
54FCTA
74FCTA
Junction Temperature (TJ)
CDIP
PDIP
4.5Vt05.5V
4.75V to 5.25V
OVtoVee
OVtoVee
-55'C to + 125'C
O'Cto +70'C
175'C
140'C
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ±10% TA = -55'C
to + 125'C, VHe = Vee - 0.2V
Symbol
54FCTA174FCTA
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
/LA
IlL
Input Low Current
-5.0
-5.0
/LA
loz
Maximum TRI·STATE
Current
10.0
10.0
-10.0
-10.0
-0.7
VIK
Clamp Diode Voltage
los
Short Circuit Current
-60
-120
VOH
Minimum High Level
Output Voltage
2.8
3.0
VHe
Vee
2.4
4.3
2.4
4.3
VOL
Maximum Low Level
Output Voltage
Conditions
Max
GND
-1.2
V
V
0.2
0.2
0.3
0.50
0.3
0.50
7·55
= Max
Vee
= Max
Vee
= Max
/LA
mA
GND
Vee
V
= Vee
= 2.7V (Note 2)
VI = 0.5V (Note 2)
VI = GND
Vo = Vee
Vo = 2.7V (Note 2)
Vo = 0.5V (Note 2)
Vo = GND
VI
VI
= Min; IN = -18 mA
= Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2Vor VHe; 10H = -32/1oA
10H = -300/LA
Vee = Min
VIN = VIH or VIL
10H = -12 mA (Mil)
10H = -15 mA (Com)
Vee = 3V; VIN = 0.2V or VHe; 10L = 300/LA
Vee = Min
IOL = 300/loA
VIN = VIH or VIL
10L = 32 mA (Mil)
10L = 48 mA (Com)
Vee
Vee
,.
DC Characteristics for FCTA Family Devices
(Contin'ued)
Typical values are at Vcc = 5.0V, 25°C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vcc = 5.0V ±5%, TA = O°C to +700C; Mil: Vcc = 5.0V ± 10% TA = -55°C
to + 125°C, VHC = Vee - 0.2V
Symbol
Parameter
54FCTA174FCTA
Min
Icc
Maximum Quiescent
Supply Current
alee
Quiescent Supply Current;
TTL Inputs HIGH
ICCD
Dynamic Power
Supply Current (Note 4)
Ic
Total Power
Supply Current (Note 6)
Units
Conditions
Typ
Max
0.001
1.5
mA
Vcc = Max
VIN ~ VHC ,;; 0.2V
II = 0
0.5
2.0
rnA
Vcc= Max
VIN = 3.4V (Note 3)
0.25
0.45
1.5
4.5
1.8
5.0
Vcc = Max
Outputs Open
OE = GND
mA/MHz.
LE = Vee
One InputToggling
50% Duty Cycle
mA
3.0
8.0
5.0
14.5
Vcc = Max
Outputs Open
OE = GND
VIN ~ VHC
VIN';; 0.2V
LE = Vcc
11=10MHz
One Bit Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
(Note 5)
Vcc = Max
Outputs Open
OE= GND
VIN ~ VHC
VIN';; 0.2V
LE = Vcc
II = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
Input Hysteresis on Clock Only
200
mV
VH
Note 1: Maximum test duration not to exceed one second. not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven Input (YIN ~ 3.4V); all other inputs at Vce or GND.
Note 4: This parameter is not directly testable, but Is derived for use In Total Power Supply calculations.
Nole 5: Values for these conditions are examples of the Ice formula. These IImHs are guaranteed but not tested.
Nole 6: Ic ~ IQUIESCENT + IINPUTS + IDYNAMIC
Ic ~ Ice +
54FCTA
74FCTA
Input Voltage
Terminal Voltage with respect to GND (VTERM)
-0.5V to 7.0V
54FCTA
-0.5 to 7.0V
74FCTA
-55'Cto +125'C
-65'Cto +135'C
Storage Temperature (TSTG)
74FCTA
54FCTA
Operating Temperature (TAl
54FCTA
74FCTA
- 55'C to + 125'C
- 65'C to + 150'C
Junction Temperature (TJ)
CDIP
PDIP
0.5w
DC Output Current (lOUT)
OVtoVee
Output Voltage
Temperature Under Bias (TSIAS)
74FCTA
54FCTA
Power Dissipation (PT)
4.5Vto 5.5V
4.75V to 5.25V
OV to Vee
-55'C to + 125'C
O'Cto +70'C
175'C
140'C
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met. without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTTM FCT circuits outside databook specifications.
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value specified
for the appropriate device type: Com: Vee 5.0V + 5%, T A = O'C to + 70'; Mil: Vee = 5.0V ± 10% T A = 55'C + 125'C VHe =
Vee -0.2V
Symbol
54FCTA174FCTA
Parameter
Min
V,H
Minimum High Level
Input Voltage
V,L
Maximum Low Level
Input Voltage
I'H
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
",A
I,L
Input Low Current
-5.0
-5.0
p.A
loz
Maximum TRI-STATE
Current
10.0
10.0
-10.0
-10.0
",A
-1.2
V
V,K
-0.7
Clamp Diode Voltage
Conditions
Max
V, = Vee
V, = 2.7V (Note 2)
Vee = Max
V, = 0.5V (Note 2)
V, = GND
Vee = Max
Va =
Va =
Va =
Vo=
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
Vee = Min; IN = -18 mA
los
Short Circuit Current
-60
VOH
Minimum High Level
Output Voltage
2.8
3.0
Vee = 3V; Y,N = 0.2V or VHe; IOH = -32 ",A
VHe
2.4
2.4
Vee
4.3
4.3
Vee = Min
Y,N = V,H orV,L
VOL
Maximum Low Level
Output Voltage
-120
Vee = Max
mA
V
GND
0.2
GND
0.3
0.3
0.2
0.50
0.50
Vee = Max (Note 1); Va = GND
IOH = -300 ",A
IOH = -12 mA (Mil)
IOH = -15mA(Com)
Vee = 3V; Y,N = 0.2V or VHe; IOL = 300 p.A
V
Vee = Min
VIN = V,H or VIL
IOH = 300 ",A
IOL = 32 mA (Mil)
IOL = 48 mA (Com)
•
7-59
DC Characteristics for 'FCTA Family Devices
(Continued)
Typical values are at Vcc = 5.0V, 25·C ambient and maximum loading. For test conditions shown as Max, use the value
specilied lor the appropriate device type: Com: Vcc = 5.0V +5%, TA = O·C to +70·C; Mil: Vcc = 5.0V ± 10% TA = -55·C
+ 125·C; VHC = Vcc - 0.2V
Symbol
Parameter
54FCTA174FCTA
Min
Icc
Maximum Quiescent
Supply Current
Alcc
Quiescent Supply Current;
TTL Inputs HIGH
ICCD
Dynamic Power
Supply Current (Note 4)
Ic
Total Power
Supply Current (Note 6)
Conditions
Units
Typ
Max
0.001
1.5
mA
Vcc = Max
VIN :;;, VHC, VIN
II = 0
0.5
2.0
mA
Vcc = Max
VIN = 3.4V (Note 3)
VIN:;;' VHC
VIN s;; 0.2V
mA/MHz
Vcc = Max
Outputs Open
OE = GND
One Input Toggling
50% Duty Cycle
Vcc = Max
Outputs Open
OE = GND
ICp = 10MHZ
II = 5MHz
50% Duty Cycle
One Bit Toggling
50% Duty Cycle
VIN:;;' VHC
VIN s;; 0.2V
(Note 5)
VCC = Max
Outputs Open
OE = GND
Icp = 10 MHz
50% Duty Cycle
II = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
VIN:;;' VHC
VIN:S: 0.2V
0.25
0.40
1.5
4.0
1.8
6.0
:s: 0.2V
VIN = 3.4V
VIN ='GND
mA
3.0
7.8
5.0
16.8
Input Hysteresis on Clock Only
200
mV
VH
Note 1: Maximum test duration not to exceed one second. not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested,
Note 3: Per TIL driven input lVIN = 3.4V); all other Inputs at Vee or GND.
Note 4: This parameter Is not directly testable, but Is derived lor use in Total Power Supply calculations.
Note 5: Values lor these conditions are examples 01 the ICC lormula. These limits are guaranteed but not tested.
Note 6: Ic = laUIEscENT + IINPUTS + IDYNAMIC
Ic = Icc + dlCC DHNT + lecD (lcp/2 + II NI)
Icc = Quiescent Current
dlCC = Power Supply Current lor a TIL High Input (VIN = 3.4V)
DH = Duty Cycle lor TIL inputs High
NT = Number 01 Inputs at DH
loco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Icp = Clock Frequency lor Register Devices (Zero lor Non-Register Devices)
II = Input Frequency
NI = Number of Inputs at II
All currents are in milliamps and all Iraquencies are in megahertz.
7-60
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
Symbol
See Section 2 lor Wavelorms
54FCTA174FCTA
74FCTA
54FCTA
TA = +25'C
Vee = 5.0V
TA. Vee = Com
Rl = 500n
Cl = 50pF
TA. Vee = Mil
Rl = 500n
Cl = 50pF
Typ
Min (Note) Max
Parameter
Min
Units
Fig.
No.
Max
tpLH
tpHL
Propagation Delay
CPtoOn
4.5
2.0
6.5
ns
2-8
tpZH
tPZL
Output Enable
Time
5.5
1.5
6.5
ns
2-11
tpHZ
tpLZ
Output Disable
Timed
4.0
1.5
5.5
ns
2-11
Is
Set-UpTime
High or Low
Dn to CP
1.0
2.0
ns
2-10
HOLD Time
High or Low
Dn toCP
1.0
1.5
ns
2-10
CP Pulse Width
High or Low
4.0
5.0
ns
2-9
tH
tw
Note: Minimum limits are guaranteed but not tested on propagation delays.
Capacitance (TA =
Symbol
+ 25'C, 1= 1.0 MHz)
Typ
Max
Units
CIN
Input Capacitance
Parameter
6
10
pF
Conditions
VIN = OV
COUT
Output Capacitance
8
12
pF
VOUT = OV
Note: This parameter is measured at characterization but not tested.
•
7-61
~Nat1onal
~ Semiconductor
54FCT17 4FCT573A
Octal Latch with TRI-STATE® Outputs
General Description
Features
The 'FCT573A is a high-speed octal latch with buffered
common Latch Enable (LE) and buffered common Output
Enable (OE) inputs.
• NSC 54174FCT573A is pin and functionally equivalent
to lOT 54174FCT573A
• Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
• Useful as input or output port for microprocessors
• IOL = 48 mA (Com), 32 mA (Mil)
• TRI-STATE outputs for bus interfacing
• Military product compliant to MIL-STD-883
• TTL input and output level compatible
• TTL inputs accept CMOS levels
The 'FCT573A is functionally identical to the 'FCT373A but
has inputs and outputs on opposite sides.
Ordering Code: See Section 8
Connection Diagrams
Logic Symbols
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
OE
LE
TLfFf10641-1
Vee
Do
0,
00
0,
02
03
°2
03
04
05
0.
06
°5
06
D-r
°7
00
0,
°2
03
6
15
°4
Os
7
'4
06
8
13
°5
06
D-r
9
12
10
11
GNO
°7
LE
TLfFf10641-2
TLfFf10641-3
Pin Names
Pin Assignment
forLCC
Description
060s°403~
1]][1]1]]1]]111
Data Inputs
Latch Enable Input
TRI-STATE Output Enable Input
TRI-STATE Latch Outputs
mo,
°71]]
GNO Il9l
LE Ii]
°7
°6
irn
1Hl
!II 00
mOE
~Vee
..............----------'/
H]i°o
1iJ]li]]li]]1i1l1iE
Os 0. 03 02 0,
TLfFf10641-4
7-62
Functional Description
Truth Table
The FCT573A contains eight D-type latches with TRISTATE output buffers. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, and the latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the latch contents are presented inverted at the outputs 07-00. When
OE is HIGH the buffers are in the high impedance mode but
this does not interfere with entering new data into the latches.
Outputs
Inputs
OE
LE
D
On
L
L
L
H
H
H
L
H
L
H
L
X
X
00
Z
X
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
00 = Previous 00 before HIGH·to·LOW transition of Latch Enable
Logic Diagram
LE
07
TL/F/l0641-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
7-63
Recommended Operating
Conditions
Absolute Maximum Rating (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vecl
54FCTA
74FCTA
Input Voltage
Outpu1 Voltage
Operating Temperature
54FCTA
74FCTA
Terminal Voltage with Respect to GND (VTERM)
54FCTA
-0.5Vto +7.0V
74FCTA
-0.5Vto +7.0V
Temperature under Bias (TaIAS)
54FCTA
74FCTA
- 65'C to + 135'C
-55'Cto + 125'C
Storage Temperature (TSTG)
54FCTA
74FCTA
Power Dissipation (PT)
-65'Cto +150'C
-55'Cto + 125'C
0.5W
DC Ouput Current (lOUT)
4.5Vt05.5V
4.75V to 5.25V
OVtoVee
OVtoVee
(TAl
- 55'C to + 125'C
O'Cto +70'C
Junction Temperature (TJ)
CDIP
PDIP
175'C
140'C
120mA
Nole 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom·
mend operation of FACTlM FCT circuits outside databook specifications.
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ±5%, TA = O'C to +70'C; Mil: 5.0V ±10%, TA = -55'C to
+ 125'C, VHe = Vee - 0.2V
Symbol
Parameter
54FCTA174FCTA
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
2.0
V
0.8
V
Input High Current
5.0
5.0
p.A
IlL
Input Low Current
-5.0
-5.0
p.A
loz
Maximum TRI·STATE
Current
10.0
10.0
-10.0
-10.0
p.A
VIK
Clamp Doide Voltage
los
Short Circuit Current
VOH
Minimum High Level
Output Voltage
-0.7
-60
Icc
Maximum Low Level
Output Voltage
Maximum Quiescent
Supply Current
~Iee
Quiescent Supply Current;
TTL Inputs HIGH
IceD
Dynamic Power
Supply Current (Note 4)
-1.2
-120
2.8
3.0
VHC
2.4
Vee
4.3
2.4
VOL
Conditions
Max
V
mA
V
Vee
=
Max
Vee
=
Max
Vee
=
Max
= Vee
= 2.7V (Note 2)
VI = 0.5V (Note 2)
VI = GND
Vo = Vee
Vo = 2.7V (Note 2)
Vo = 0.5V (Note 2)
Vo = GND
VI
VI
= Min; IN = -18 mA
= Max (Note 1); Vo = GND
Vee = 3V; VIN = 0.2V or VHe; 10H = -32 p.A
10H = -300 p.A
Vee = Min
VIN = VIH or VIL
10H = -12 mA (Mil)
Vee
Vee
4.3
10H
= 3V; VIN =
Vee = Min
VIN = VIH or VIL
GND
0.2
GND
0.3
0.3
0.2
0.50
0.50
0.001
1.5
mA
Vee = Max
VIN ~ VHe, VIN ,;: 0.2V
fl = 0
0.5
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
0.25
0.45
Vee
V
Vee = Max
Outputs Open
One Input Toggling
mA/MHz
50% Duty Cycle
OE = GND
LE = Vee
7·64
=
-15 mA (Com)
0.2V or VHe; 10L
10L
10L
10L
=
=
=
=
300 p.A
300 p.A
32 mA (Mil)
48 mA (Com)
VIN ~ VHe
VIN';: 0.2V
DC Characteristics for 'FCTA Family Devices (Continued)
Typical values are at Vcc = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vcc = 5.0V ±5%, TA = O'C to +70'C; Mil: 5.0V ±10%, TA = -55'C to
+ 125'C, VHC = Vcc - 0.2V
Symbol
54FCTA174FCTA
Parameter
Min
Ic
Total Power
Supply Current (Note 6)
Typ
Max
1.5
4.5
1.B
5.0
Conditions
Units
Vcc = Max
Outputs Open
OE = GND, LE = Vcc
fcp = 10 MHz
One Bit Toggling
50% Duty Cycle
VIN;;;' VHC
VIN';: 0.2V
(Note 5)
Vcc = Max Outputs Open
OE = GND, LE = Vcc
fcp = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
VIN;;;' VHC
VIN';: 0.2V
VIN
VIN
= 3.4V
= GND
rnA
3.0
B.O
5.0
14.5
VIN
VIN
= 3.4V
= GND
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
Nole 3: Per TTL driven input (VIN
~
3.4V); all other inputs at Vee or GND.
Note 4: This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Nole 5: Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Nole 6: IC ~ IQUIESCENT + IINPUTS + IDYNAMIC
IC ~ ICC + alee DHNT + ICCD (fcp/2 + fiN I)
Icc ~ Quiescent Current
alCC ~ Power Supply Current for a TTL High Input (VIN ~ 3.4V)
DH ~ Duty Cycle for TTL inputs High
NT ~ Number of Inputs at DH
ICCD ~ Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCp ~ Clock Frequency for Register Devices (Zero for Non·Reglster Devices)
fl ~ Input Frequency
N, ~ Number of Inputs at fl
All currents are In milliamps and all frequencies are In megahertz.
AC Electrical Characteristics:
Symbol
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
Parameter
Propagation Delay
Onto On
Propagation Delay
LEtoO n
Output Enable Time
See Section 2 for Waveforms
54174FCTA
74FCTA
54FCTA
TA = +25'C
Vee = 5.0V
TA. Vee = Com
RL = 5000.
CL = 50pF
TA. Vee = Mil
RL = 5000.
CL = 50pF
Min
Units
Fig.
No.
Typ
Min
Max
4.0
1.5
5.2
Max
ns
2·B
7.0
2.0
B.5
ns
2·B
5.5
1.5
6.5
ns
2-11
4.0
1.5
5.5
ns
2-11
tpHZ
tpLZ
Output Disable Time
ts
Setup Time High or
Low, On to LE
1.0
2.0
ns
2-10
tH
Hold Time High or
Low, Onto LE
1.0
1.5
ns
2-10
ns
2·9
LE Pulse Width
4.0
5.0
High or Low
Nole 1: Minimum limits are guaranteed but not tested on propagation delays.
tw
7-65
•
~
c;
Capacitance (TA = + 25°C, f =
1.0 MHz)
Conditions
Typ
Max
Units
CIN
Input Capacitance
6
10
pF
VIN = OV
COUT
Output Capacitance
8
10
pF
VOUT = OV
Symbol
Parameter
Note: This parameter is measured at characterization but not tested.
7-66
r-----------------------------------------------------------------------~~
.....
:=
~National
~ semiconductor
54FCT174FCT574A
Octal D Flip-Flop with TRI-STATE® Outputs
General Description
Features
The 'FCT574A is a high-speed, low power octal flip-flop with
a buffered common Clock (CP) and a buffered common
Output Enable (OE). The information presented to the D
inputs is stored in the flip-flops on the LOW-to-HIGH Clock
(CP) transition.
• NSC 54174FCT574A is pin and functionally equivalent
to IDT54/74FCT574A
• Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
• Useful as input or output port for microprocessors
• Functionally identical to 'FCT374A
• TRI-STATE outputs for bus-oriented applications
• 'FCT574A has TTL-compatible inputs
• IOL = 48 mA (Comm) and 32 mA (Mil)
• TTL inputs accept CMOS levels
The 'FCT574A is functionally identical to the 'FCT374A except for the pinouts.
Ordering Code: See Section 8
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
OE
OE
TUF/l0150-1
IEEE/IEC
OE
1
20
Vee
°0
0,
Pin Assignment
forlCC
06 Os D4 D:! D.2
!ID1II!ID[[)1Il
Do
2
19
0,
3
18
°2
D3
4
5
17
°2
16
°3
°4
Os
6
15
7
14
°4
Os
°6
8
13
06
1HI1lID1IID1lZI1IID
I?
9
12
°7
Os 4 3 02 0,
10
11
CP
GND
mo,
°7 [[]
GNO [QJ
CP
moo
IIll
mOE
gQIVee
°71i]J
JgJ
°6
Ii]] 00
°°
TL/F/l0150-3
CP
TL/F/l0150-2
Do
0,
°0
0,
°2
°2
D:!
°3
D4
°4
Os
Ds
06
06
I?
°7
TUF/l0150-4
Pin Names
Description
•
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
TRI-STATE Outputs
7-67
~
Functional Description
Function Table
The 'FCT574A consists of eight edge-triggered flip-flops
with individual D-type inputs and TRI-STATE true outputs.
The buffered clock and buffered Output Enable are common to aI/ flip-flops. The eight flip-flops will store the state of
their individual 0 inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CPl transition.
With the Output Enable (OEl LOW, the contents of the eight
flip-flops are available at the outputs. When OE is HIGH, the
outputs go to the high impedance state. Operation of the
OE input does not affect the state of the flip-flops.
Inputs
Internal
Outputs
OE
CP
D
Q
ON
H
H
H
H
L
L
L
L
H
H
L
H
L
H
L
H
L
H
NC
NC
L
H
L
H
NC
NC
Z
Z
Z
Z
L
H
NC
NC
...r
...r
...r
...r
H
H
Function
Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedanoa
..r = LOW-to·HIGH Transition
NC = No Change
Logic Diagram
TL/F/l0150-5
Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
7-68
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee!
54FCTA
74FCTA
Terminal Voltage with Aespect to GND (VTERM)
54FCTA
-0.5Vto +7.0V
74FCTA
-0.5Vto +7.0V
4.5Vto 5.5V
4.75V to 5.25V
Input Voltage
OV to Vee
Output Voltage
OVtoVee
Temperature under Bias (TSIAS)
74FCTA
54FCTA
-55'Cto +125'C
- 65'C to + 135'C
Storage Temperature (TSTG)
74FCTA
54FCTA
Operating Temperature (TAl
54FCTA
74FCTA
- 55'C to + 125'C
-65'C to + 150'C
Junction Temperature (TJ)
Power Dissipation (PT)
-55'Cto +125'C
O'Cto +70'C
CDIP
PDIP
0.5W
175'C
140'C
DC Output Current (lOUT)
120mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The dalabook specifications should be me~ without
exception, to ensure that the system design is reliable over its power supply.
temperature, and output/input loading variables. National does not recommend operation of FACT FCT circuits outside databook specifications.
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ± 5%, T A = O'C to + 70'C; Mil: Vee = 5.0V ± 10%, T A = - 55'C
to + 125'C, VHe = Vee -0.2V
Symbol
54FCTA174FCTA
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Input High Current
Typ
Conditions
Units
Max
2.0
V
0.8
V
5.0
5.0
",A
Vee
=
Max
VI
VI
= Vee
= 2.7V (Note 2)
= 0.5V (Note 2)
= GND
IlL
Input Low Current
-5.0
-5.0
",A
Vee
=
Max
VI
VI
loz
Maximum TAI·STATE
Current
10.0
10.0
-10.0
-10.0
",A
Vee
=
Max
Vo
Vo
Vo
Vo
V
Vee
=
Min; IN
mA
Vee
=
Max (Note 1); Vo
Vee
= 3V; VIN = 0.2V or VHe; IOH =
VIK
Clamp Diode Voltage
los
Short Circuit Current
VOH
Minimum High Level
Output Voltage
VOL
Maximum Low Level
Output Voltage
-0.7
-60
-1.2
-120
2.8
3.0
VHe
2.4
2.4
Vee
4.3
4.3
GND
GND
0.3
0.3
0.2
0.2
0.5
0.5
7·69
V
Vee = Min
VIN = VIH or VIL
Vee
V
=
=
3V; VIN
=
Vee
= 2.7V (Note 2)
=
=
0.5V (Note 2)
GND
-18 mA
= GND
IOH
10H
10H
-32 ",A
= - 300 ,uA
= -12mA(MiI)
= -15 mA (Com)
= 0.2V or VHe; IOL = 300 ,u.A
10L = 300,u.A
Vee = Min
VIN = VIH or VIL
10L
10L
=
32 mA (Mil)
= 48 mA (Com)
•
~
DC Characteristics for 'FCTA Family Devices
Typical values are at Vcc = 5.0V, 25·C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vcc = 5.0V ±5%, TA = O"C,to +70·C; Mil: Vcc = 5.0V ±10%, TA = -55·C
to + 125·C, VHe = Vcc -0.2V (Continued)
Symbol
Parameter
54FCTA/74FCTA
Min
Icc
Maximum Quiescent
Supply Current
.1lcc
Quiescent Supply Current;
TTL Inputs HIGH
ICCD
Dynamic Power
Supply Current (Note 4)
Ie
Total Power
Supply Current (Note 6)
Units
Conditions
Typ
Max
0.001
1.5
mA
0.5
2.0
mA
Vee = Max
VIN = 3.4V (Note 3)
mA/MHz
Vee = Max
Outputs Open
OE = GND
One Input Toggling.
50% Duty Cycle
0.15
0.25
1.5
4.0
1.8
6.0
Vee = Max
VIN ~ VHe, VIN ,,; 0.2V
fl = 0
Vee = Max
Outputs Open
OE = GND
fl = 5.0 MHz
One Bit Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
mA
3.0
7.8
5.0
16.8
Note 1: Maximum test duration not to exceed one second. not more than one oulput shorted at one time.
Note 2: This parameter guaranteed but not tested.
Note 3: Per TTL driven Input (YIN = 3.4V); all other Inputs at Vce or GND.
Note 4: This parameter Is not directly te.table, but Is derived lor use In Total Power Suppty calculations.
Note 5: Values lor these condHlons are examples 01 the Ice lo""ula. These limHs are guaranteed but not tested.
Note 6: IC = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Ice + boice DHNT + IceD (fCp/2 + II NI)
Ice = Quiescent Current
boice = Power Supply Current lor a TTL High Input (YIN = 3.4V)
DH = Duty Cycle lor TTL Inputs High
NT = Number 01 Inputs at DH
lceo = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
ICp = Clock Frequency for Registar Devices (Zero lor Non-Register Devices)
II = Input Frequency
NI = Number 01 Inputs at II
All currents are in milliamps and alilrequencies are In megahertz.
7-70
(Note 5)
Vee = Max
Outputs Open
OE = GND
feD = 10MHz
fl = 2.5 MHz'
Eight Bits Toggling
50% Duty Cycle
VIN = 3.4V
VIN = GND
AC Electrical Characteristics:
Symbol
Parameter
See Section 2 for Waveforms
54FCTA174FCTA
74FCTA
54FCTA
TA = +25'C
Vee = 5.0V
TA. Vee = Com
Rl = 500n
Cl = 50pF
TA. Vee = Mil
Rl = 500n
Cl = 50pF
Units
Fig.
No.
Typ
Min
Max
4.5
2.0
6.5
ns
2-8
5.5
1.5
6.5
ns
2-11
4.0
1.5
5.5
ns
2·11
Min
Max
tPLH
tpHL
Propagation Delay
CPtoO n
tPZH
tPZL
Output Enable Time
tpHZ
tpLZ
Output Disable Time
tsu
Set-UpTime
High or Low
Dn to CP
1.0
2.0
ns
2-10
Hold Time
High or Low
Dn toCP
0.5
1.5
ns
2-10
CP Pulse Width
High or Low
4.0
5.0
ns
2-9
tH
tw
Note 1: Minimum limits are guaranteed but not tested on propagation delays.
Capacitance (TA =
+ 25°C. f = 1.0 MHz)
Symbol
Parameter (Note 1)
Typ
Max
Units
CIN
Input Capacitance
6
10
pF
VIN = OV
COUT
Output Capacitance
8
12
pF
VOUT = OV
7·71
Conditions
~National
ADVANCE INFORMATION
~ Semiconductor
54FCT/7 4FCT646A
Octal Transceiver/Register with TRI-STATE® Outputs
General Description
Features
The FCT646A consist of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B
bus will be loaded into the respective registers on the LOWto-HIGH transition of the appropriate clock pin (CPAB or
CPBA).
• NSC 54FCT174FCT646A is pin and functionally equivalent to lOT 54FCT174FCT646A
• Independent registers for A and B buses
• Multiplexed real-time and stored data transfers
• Input clamp diodes to limit bus reflections
• TIL/CMOS input and output level compatible
• IOL = 64 mA (Com), 48 mA (Mil)
• CMOS power levels
• 4 kV minimum ESD immunity
• Military Product compliant to MIL-STD 883
FACFM FCTA utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCTA features undershoot correction and split
ground bus for superior performance.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
G--'---...c:-----,
CPAD
SAD
OIR
CPUA---I>
SUA
Cf'AB---I>
OIR
Ao
A,
SAB-----,."
-'2
D.
1
2
3
4
5
6
CPUA
SUA
22
21
20
G
Do
1,
17
16
15
,4
D,
D2
D.
B4
Bs
B6
12
13
a.,
A4
As
A6
'0
AJ
GNO
8,
Vee
23
'9
,a
A.
TL/F/l0675-1
24
9
TL/F/l0675-3
Pin Assignment
for LCC and PCC
Pin Names
CPAB,
CPBA
SAB,SBA
G
DIR
Description
A5 A4 A3 HC Az A,
Ao
[iJli]IlIDlIDlIllIlrn
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
TUF/l0675-2
As Ii1I
[!] DlR
A7~
GHD~
rnSAB
~CPAB
HC~;'
[I]NC
{mVcc
IW CPBA
~Ii]]::-
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
~
~ Ia§ SBA
B6 IllI ;.
Bsli]] ;.
'=:Ju1OO1[JlUll00"
1iID~~~~~~
B4 B3 B2 HC B, Bo ii
TLlF/l0675-4
7-72
CD
~National
ADVANCE INFORMATION
~ semiconductor
N
....
»
•
CD
N
....
m
54FCT17 4FCT821A • 54FCT17 4FCT821 B
10-Bit 0 Flip-Flop with TRI-STATE® Outputs
General Description
Features
The 'FCT821A1B is a 10-bit D flip-flop with TRI-STATE oututs arranged in a broadside pinout.
FACTTM FCTA/B utilizes NSC quiet series technology to
provide improved quiet output switching and dynamic
threshold performance.
FACT FCTA features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
FACT FCTB features an undershoot corrector in addition to
a split ground bus for superior performance.
• NSC 54FCTI74FCT821A1B is pin and functionally
equivalent to IDT 54FCTI74FCT821A1B
• High-speed parallel registers with positive edge-triggered D-type flip-flops for ringing suppression
• Buffered common clock enable (EN) and asynchronous
clear input (CLR)
• Input clamp diodes for ringing suppression
• TIL/CMOS input and output level compatible
• IOL = 48 mA (COM), 32 mA (MIL)
• CMOS power levels
• 4 kV minimum ESD immunity
• Military Product compliant to MIL-STD 883
• TRI-STATE outputs for bus interfacing
• Noninverting outputs
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and sOle
IEEEIIEC
DE
CP
Do
CP
10
I>
01
Pin Names
Do-Dg
OO-Og
OE
CP
°0
°1
O2
TL/FI10677-'
V
°2
OE
2.
Vee
Do
23
00
22
°1
O2
0,
3
D2
4
21
03
5
20
03
I.
0.
18
Os
D.
03
03
D.
05
°4
D6
°5
Ds
8
17
•
06
16
°7
06
°6
10
15
Os
~
1?
Os
0.,
Dg
11
14
D.
08
08
GNO
12
13
CP
D.
0.
Description
TL/FI10677-3
TLlF/l0677-2
Data Inputs
Data Outputs
Output Enable Input
Clock Input
Pin Assignment
for LCC
D7 D6 Os NC
o. D3 D2
iJ]1i9J1ID!!J1Zl!!J1ID
III D,
!!J Do
mOE
Dslill
0.1rn
GNDIrn
NCM!
[j]NC
CPIrn
I11iIVcc
IilI 00
0.1i1I
0slrn
OOI(Jl(JOI(JIro'
I11iI 0,
1lID11l!0001!l1~fllIl11iI
°°
7 6 Os NCO. 03 02
TL/FI10677 -4
7-73
,.
m
.-----------------------------------------------------------------~
C')
N
• ~National
~ Semiconductor
ADVANCE INFORMATION
co
i
54FCT /7 4FCT823A • 54FCT /7 4FCT823B
9-Bit D Flip-Flop
General Description
Features
The 'FCT823A1B is a 9-bit buffered register. It features
Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems.
FACnM FCTAIB utilizes NSC quiet series technology to
provide improved quiet output switching and dynamic
threshold performance.
• NSC 54FCTI74FCT823A1B is pin and functionally
equivalent to lOT 54FCT/74ACT823A1B
• High speed parallel registers with positive edge-triggered D-type flip'flop
• Buffered common clock enable (EN) and asynchronous
clear input (ClR)
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 mA (Com), 32 mA (Mil)
• CMOS power levels
• 4 kV minimum ESD immunity
• Military product compliant to Mil-STD 883
FACT FCTA features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
FACT FCTB features an undershoot corrector in addition to
a split ground bus for superior performance.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIlEC
OE
CLR
EN
CP
TL/F/l067B-l
Pin Names
Do-De
Oo-Oe
OE
ClR
CP
EN
Description
Data Inputs
Data Outputs
Output Enable
Clear
Clock Input
Clock Enable
Do
00
Dl
°1
D2
D3
°2
03
D4
°4
Ds
°5
06
D6
Dr
D3
D4
D5
06
Dr
5
6
7
8
CUi
9
10
11
GNO
12
Os
24
23
22
21
20
19
°1
°2
03
°4
°5
06
IS
17
16
15
Or
Os
EN
14
13
°7
Os
Ds
Vee
00
CP
TL/F/l067S-3
TUF/l067B-2
Pin Assignment
forlCC
07 06 05 NC 04 03 O2
1liIfi]J[!][!]m[§][ID
II mOl
Oa[!J~
rn DO
CUi Ii}]
GNO~
III OE
[IJ NC
NCIi§]
CPIi§]
EN I!]
°ali§]
~Vcc
Iiil 00
~JOOlI(JIOoif
~Ol
IiIDB!ilWJ~liU~~
07 06 05 NC 04 0 3 02
TLlF/l0678-4
7-74
~-------------------------------------------------------------------------------,
co
I\)
~NaHorna~
ADVANCE INFORMATION
~ Semiconductor
~
•
co
I\)
UI
OJ
54FCT 17 4fCT825A
8-Bit D Flip-flop
tAl
54fCT 17 4fCT825fB
General Description
features
The 'FCT825A1B is an 8-bit buffered register. They have
Clock Enable and Clear features which are ideal for parity
bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multiuse control of the interface.
£i/ NSC
FACTTM FCTAIB utilizes NSC quiet series technology to
provide improved quiet output switching and dynamic
threshold performance.
FACT FCTA features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
FACT FCTB features an undershoot corrector in addition to
a split ground bus for superior performance.
I:l
[;J
IJ
II
I:l
fI
III
III
54FCT174FCT825A1B is pin and functionally
equivalent to IDT 54FCT174FCT825A1B
High-speed parallel registers with positive edge-triggered D-type flip flops
Buffered common clock enable (EN) and asynchronous
Clear input (ClR)
Input clamp diodes to limit bus reflections
TIL/CMOS input and output level compatible
IOL = 48 mA (Com), 32 mA (Mil)
CMOS power levels
4 kV minimum ESD immunity
Military Product compliant to Mil-STD 883
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEEIIEC
OE I
OE I
0E2
1
2
0E3
00
01
3
00
4
21
°1
Dz
5
20
°2
03
EN
CP
TlIF/IOS79-1
03
6
19
00
00
04
7
18
01
01
8
17
O2
03
°2
03
Os
06
9
16
°4
Os
06
07
10
15
07
04
°4
Os
06
CLR
11
14
EN
GNO
12
13
CP
Os
Os
°7
TL/F/l0S79-3
07
TL/Fll0679-2
Pin Names
DO-D7
00-0 7
OE1, OE2, OEs
EN
ClR
CP
Vee
Pin Assignment
forlCC
Description
Os Os 04 NC 03 O2 01
1l1I1i]]12l12l[l]mlIl
Data Inputs
Data Outputs
Output Enables
Clock Enable
Clear
Clock Input
~
07 Iill (
CLR 1m
moo
0 0E2
rn OEI
OJ NC
GNO rgr
NC Ii]]
CP Ii]]
~
vee
EN Ii1I
~
0E3
07 Ii]]
~Oo
\~~~rn:~~~~rn~J!(~:RIV
1i]][@)~~I~H~~
OS Os 0 4 NC 03 02 01
TlIF/l0679-4
7-75
fII
m .------------------------------------------------------------------,
~ ~National
ADVANCE INFORMATION
~ ~ Semiconductor
CN
CD
54FCT /7 4FCT827 A • 54FCT /7 4FCT827B
10-Bit Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The 'FCT827A1B 10-bit bus buffer provides high performance bus interface buffering for wide datal address paths or
buses carrying parity. The 10-bit buffers have NOR output
enables for maximum control flexibility.
FACTTM FCTAIB utilizes NSC quiet series technology to
provide improved quiet output switching and dynamic
threshold performance.
FACT FCTA features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
FACT FCTB features an undershoot corrector in addition to
a split ground bus for superior performance.
• NSC 54FCT/74FCT827A1B is pin and functionally
equivalent to lOT 54FCTI74FCT827A1B
• High Speed parallel registers with positive edge-triggered Ootype flip-flops
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 mA (Com), 32 mA (Mil)
• CMOS power levels
• 4 kV minimum ESO immunity
• Military Product compliant to Mil-STO 883
Connection Diagrams
Logic Symbols
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
Vee
00
°1
°z
03
20
19
TUF/106BO-1
Pin Names
OE1,OE2
0 0- 0 7
0 0- 0 7
Description
GHD
Output Enable
Data Inputs
Data Outputs
18
°4
05
17
as
16
~
15
°e
14
°9
o~
13
TL/F/10BBO-3
TL/F/1OBBO-2
Pin Assignment
forlCC
Del!il
Ogli]
GND 1m
mD,
mOo
ill OE,
NC Ii]
[j] NC
OEzli])
1m vee
Ogliil
!Woo
~o,
°eli])
-Qooo(JIOOIif
Ii]Ii!iIDI~~~~
07 Os 0s Ne 04 03 02
TUF/10B80-4
7-76
.----------------------------------------------------------------------------,co
~National
ADVANCE INFORMATION
~ semiconductor
01:00
.....
J:-
co•
01:00
.....
OJ
S4FCT/74FCT841A-S4FCT/74FCT841B
10-Bit Transparent Latch with TRI-STATE ® Outputs
General Description
Features
The bus interface latch is designed to eliminate the extra
packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The 'FCT841 AlB is a 10-bit transparent latch, a
10-bit version of the FCT373A.
FACTTM FCTAIB utilizes NSC quiet series technology to
provide improved quiet output switching and dynamic
threshold performance.
FACT FCTA features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior performance.
• NSC 54FCTI74FCT841A1B is pin and functionally
equivalent to lOT 54FCTI74FCT841A1B
• High Speed parallel latches
• Buffered common latch enable, clear and preset input
• Input clamp diodes to limit bus reflections
• TIL/CMOS input and output level compatible
• IOL = 48 mA (com), 32 mA (mil)
• CMOS power levels
• 4 kV minimum ESO immunity
• Military Product compliant to MIL-STO 883
FACT FCTB features an undershoot corrector in addition to
a split ground bus for superior performance.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
OE
LE
DE
Do
LE
°0
0,
24
Vee
Do
01
23
00
0,
3
21
5
20
°2
03
O2
03
04
°2
°3
04
04
05
6
19
°4
7
18
05
Os
05
Os
Os
07
8
17
°5
Os
9
16
I?
0.,
Os
10
15
Os
Dg
Os
Og
Os
11
14
°7
08
Og
GNo
12
13
LE
TUF/10681-2
Pin Names
00- 0 9
00-0 9
OE
LE
22
4
O2
03
0,
Tl/F/10681-1
OE
TlIF/106S1-3
Pin Assignment
forLCC
Description
I? 0 6 05 Ne
Oatalnputs
TRI-STATE Outputs
Output Enable
Latch Enable
04 03 O2
li]Ji]immmmm
mo,
oslilJ
ogli1l
GNo Jj]J
Ne IlID
moo
mOE
[I] Ne
LEIiID
~vcc
~~oo
OgliZl
°a lim
~O,
.
~.
~~~~I~H~~
07 Os Os Ne 04 03 02
TL/F/10681-4
7-77
•
~National
ADVANCE INFORMATION
~ semiconductor
54FCT17 4FCT843A • 54FCT174FCT843B
9·Bit Transparent Latch
General Description
Features
The 'FCT843A1B bus interface latch is designed to elimi·
nate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths.
FACTTM FCTAIB utilizes NSC quiet series technology to
provide improved quiet output switching and dynamic
threshold performance.
• NSC 54FCTI74FCT843A1B is pin and functionally
equivalent to lOT 54FCTI74FCT843A1B
• High Speed parallel latches
• Buffered common latch enable, clear and preset inputs
• Input clamp diodes to limit bus reflections
• TTL/CMOS input and output level compatible
• IOL = 48 mA (Com), 32 mA (Mil)
• CMOS power levels
• 4 kV minimum ESD immunity
• Military Product compliant to Mll·STD 883
FACT FCTA features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior per·
formance.
FACT FCTB features an undershoot corrector in addition to
a split ground bus for superior performance.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
OE
OE
Do
PRE
Description
Data Inputs
Data Outputs
Output Enable
latch Enable
Clear
Preset
00
01
Dl
3
LE
D2
4
21
D3
5
20
02
03
°0
0,
D,
Pin Names
Vee
23
CLR
DO
TL/F/l0682-1
24
D2
D3
°2
03
D4
°4
Ds
D6
°s
06
D7
°7
Ds
22
D4
6
19
°4
Ds
7
18
D6
8
17
°s
06
DJ
9
16
D8
CLR
1O
15
II
14
°7
Os
PRE
GHD
12
13
LE
TLlF/l0682-2
°8
TL/F/l0682-4
Pin Assignment
forleC
DJ D6 Ds HC D4 D3 D2
Ji][QJ [[JIIDIII lID 00
D8~
ill D,
CLR Ii]
mDo
GHD~
[IJOE
HC I!ID
LE I!ID
PRE Ii]
[DHC
~Vee
QiI 00
I!!IO,
°sl!!l
IiIDJi2iWl~I~H3I~
07 Os Os He 04 03 O2
TL/F/l0682-3
7·78
....
•
....
, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , CD
ADVANCE INFORMATION ~
~National
~ semiconductor
CD
CI1
CD
54FCT17 4FCT845A • 54FCT17 4FCT845B
8-Bit Transparent Latch with TRI-STATE® Outputs
General Description
Features
The 'FCT845A1B bus interface latch is designed to elimi·
nate the extra packages required to buffer existing latches
and provide easy expansion through multiple OE controls.
• NSC 54FCT174FCT845A1S is pin and functionally
equivalent to lOT 54FCT174FCT845A1B
• High speed parallel latches
• Buffered common latch enable, clear and preset input
• Input clamp diodes to limit bus reflections
• TIL/CMOS input and output level compatible
• IOL = 48 mA (Com), 32 mA (Mil)
• CMOS power levels
!I 4 kV minimum ESD Immunity
• Military product compliant to Mll·STD 883
FACTTM FCTAIB utilizes NSC quiet series technology to
provide improved quiet output switching and dynamic
threshold performance.
FACT FCTA features GTOTM output control and undershoot
corrector in addition to a split ground bus for superior per·
formance.
FACT FCTS features an undershoot corrector in addition to
a split ground bus for superior performance.
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and sOle
0E1
0E2
0E3
0E1
0E2
PRE
Do
00
CLR
°1
°2
°1
°2
LE
24
Vee
0E3
°30.
03
TL/F/10SB3-1
Pin Names
Do-~
0 0- 0 7
OE1- 0E3
lE
ClR
PRE
00
0.
O2
°1
°2
°5
°5
06
0&
Description
D3
03
°7
Data Inputs
Data Outputs
Output Enables
latch Enable
Clear
Preset
0.
0.
CLR
°5
°5
GNO
Do
01
06
0&
°7
°7
°7
12
14
PRE
13
LE
TLlF/10SB3-3
TLlF/10SB3-2
Pin Assignment
for Lee
06 05 0, NC 03 O2 01
Ii] lim
IIJ[Z) J]]
rn
........,..~I"'\.t"""l..
__
m
• .r"'I.'-
~@
[!JOo
!II 0E2
ill 0E1
CLR IiAI
GNO IBI
NC [§I
LE IlID
mNC
Ii§! vee
PRE I!iI
B2I 0[3
071lID
~[J{J{:JIU{JI17'
~Oo
[ID~I!lJIUI~~~
06 05
Ne 03 02 01
o.
TL/F/10BB3-4
7·79
•
~National
~ Semiconductor
54FCT17 4FCT899A
9-Bit Latchable Transceiver
with Parity GeneratorIChecker
General Description
Features
The 'FCT899A is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction. It has a guaranteed current
sinking capability of 24 mA at the A-bus and 64 mA at the
8-bus.
• Latchable transceiver with output sink of 24 mA at the
A-bus and 64 mA at the 8-bus
• Option to select generate parity and check or "feedthrough" data/parity in directions A-to-8 or 8-to-A
• Independent latch enables for A-to-8 and 8-to-A directions
• Select pin for ODD/EVEN parity
• ERRA and ERR8 output pins for parity checking
• Ability to simultaneously generate and check parity
• CMOS power levels
• Guaranteed 4000V min ESD protection
The 'FCT899A features independent latch enables for the
A-to-8 direction and the 8-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
FACTTM FCTA utilizes NSC quiet series technology to provide improved quiet output switching and dynamic threshold
performance.
FACT FCTA features undershoot correction and split
ground bus for superior performance.
Ordering Code: See Section 8
Logic Symbol
Connection Diagram
Pin Assignment for PCC
A7 A6 A5 A4 A3 A2 Al
Il]IIQI 00 1ID1Il1]]1]]
APAR !ill
GBA Ii]]
GND Ii]]
[!] AO
[IJLEA
[II ERRA
mODO/EVEN
~Vcc
~ GAB
ERRB 1m
SEL Ii]J
LEB Il1J
BPAR liE
LEA.
LEB
~Bo
Jj])~gj)~I~H~~
TL/F/l0693-1
87 B6 B5 B4 B3 B2 B,
7-80
TL/F/l0693-2
r-------------------------------------------------------------------------------~
Functional Description
Pin Names
Description
Ao-A7
Bo-B7
APAR, BPAR
ODD/EVEN
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active
LOW for EVEN Parity
Output Enables for A or B Bus,
Active LOW
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
Latch Enables for A and B Latches,
HIGH for Transparent Mode
Error Signals for Checking
Generated Parity with Parity In,
LOW if Error Occurs
GBA,GAB
SEL
LEA,LEB
ERRA, ERRB
co
CD
;
The 'FCT899A has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
-
Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[O:?] (A[O:?]) can be
checked and monitored by ERRB (ERRA).
-
Bus A (B) communicates to Bus
mode if SEL is HIGH. Parity
checked as ERRA and ERRB in
(can be used as an interrupt to
error to the CPU).
-
Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function Table below).
B (A) in a feed-through
is still generated and
the feed-through mode
signal a data/parity bit
Function Table
Inputs
Operation
GAB GBA SEL LEA LEB
H
L
X
H
H
X
X
X
Busses A and Bare TRI-STATE®.
H
L
L
L
H
Generates parity from B[O:?] based on OlE (Note 1). Generated parity
~ APAR. Generated parity checked against SPAR and output as
ERRS.
H
L
L
H
H
Generates parity from S [O:?] based on OlE. Generated parity ~
APAR. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check
asERRA.
H
L
L
X
L
Generates parity from S latch data based on OlE. Generated parity
~ APAR. Generated parity checked against latched BPAR and
output as ERRB.
H
L
H
X
H
BPAR/B[O:?] ~ APAR/ AO:?] Feed-through mode. Generated parity
checked against BPAR and output as ERRB.
H
L
H
H
H
BPAR/B[O:?] ~ APAR/A[O:?]
Feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch for
generate/check as ERRA.
L
H
L
H
L
Generates parity for A[O:?] based on OlE. Generated parity ~
BPAR. Generated parity checked against APAR and output as ERRA.
L
H
L
H
H
Generates parity from A[O:?] based on OlE. Generated parity ~
BPAR. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check
asERRB.
L
H
L
L
X
Generates parity from A latch data based on OlE. Generated parity
~ BPAR. Generated parity checked against latched APAR and
output as ERRA.
L
H
H
H
L
APAR/A[O:?] ~ BPAR/B[O:?]
Feed-through mode. Generated parity checked against APAR and
output as ERRA.
L
H
H
H
H
APAR/A[O:?] ~ BPAR/B[O:?]
Feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch for
generate/check as ERRB.
~
~
~
HIGH Voltage Level
LOW Voltage Level
Immaterial
Note 1: OlE ~ ODD/EVEN
?-81
ill
~
i
Functional Block Diagram
arIB-blt
Output
,....--
!!-blt
---:-'"" TRANSPARENT
-'-LATCH
r0-
Buffer
III
LE
=
PARITY
GDlERATOR
--
r=
I-
-
:~~
~
~
r-
-
=
B-bR
Output
9-bR
mANSPARENT
LATCH
Suffer
~
~I-
===--
LE
GENERATOR
I
I
ODD/MN
LEB
TL/F/10693-3
AC Path
SEI
1--------------------------------------------
An. APAR
(Bn. BPAR)
/
Bn. BPAR
(An. APAR)
'----
INPUT
' - - - ,OUTPUT
TL/F/10693-4
An. APAR --> Bn. BPAR
(Bn• BPAR --> An. APAR)
FIGURE 1
7·82
(XI
AC Path
CD
CD
):0
(Continued)
SEL
OlE
0
0
LEA
(LES)
A!O:7]
(S[0:7])
000 PARITY
INPUT
SPAR
(APAR)
OUTPUT
TPHL
An -> BPAR
(Bn -> APAR)
TL/F/l0693-5
FIGURE 2
OlE
APAR
(SPAR)
0
0
LEA
(LEB)
A[O:71
(S[0:7])
ODD PARITY
INPUT
ERRA
(ERRS)
OUTPUT
An -> ERRA
(Bn -> ERRB)
TL/F/l0693-6
FIGURE 3
APAR
(SPAR)
A[O:71
(S[0:7])
=><
EVEN PARITY
OlE
INPUT
ERRA
(ERRS)
OlE -> ERRA
OlE -> ERRB
INPUT
OUTPUT
TPLH
TLlF/l0693-7
FIGURE 4
7-83
~r-------------------------------------------------------~
m
AC Path
(Continued)
SEL
APAR
(BPAR)
A[O:7I
(B[O:7I)
0
0
=><
EVEN PARITY
INPUT
INPUT
OlE
BPAR
(APAR)
OUTPUT
TPLH
OlE -. BPAR
(OlE -. APAR)
TUF/10693-8
FIGURE 5
OlE
A[O:7J
(BIO:7])
0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
:x
INPUT
_ _ _ _ _ _ _ _EV_E_N_PA_R_ITY_ _ _ _ _ _ _ _ __
APAR
(BPAR)
INPUT
OUTPUT
APAR -. §iRA
(BPAR -. ERRB)
TPLH
TL/F/10693-9
FIGURE 6
SEL 1- - - - - - - - - - - - - - - - - - - - - -
INPUT
BPAR, B[0:7]
(APAR, AIO:7])
0.3V
TPHZ
OUTPUT
TPZH
TLlF/10693-10
ZH.HZ
FIGURE 7
7-84
co
AC Path
CD
CD
(Continued)
:I>
SEL 1-------------------------------------------
GAB
(GBA)
INPUT
BPAR. B[0:7]
(APAR. A[0:7])
OUTPUT
0.3V
TPLZ
ZL, LZ
TLlF/10693-11
FIGURE 8
OlE
APAR
(BPAR)
1
0
A[0:7]
(B[O:71)
---------------------~
---./'\_______________EV_EN_P_A_RIlY
_ _ _ _ _ _ _ _ __
INPUT
INPUT
OUTPUT
BPAR
(APAR)
TPLH
TL/F/10693-12
SE[ --- BPAR
(SEL --- APAR)
FIGURE 9
SEL
OlE
A[0:7]. APAR
(B[O:7l. BPAR)
1--------------------------------------------------------------1-----------------------------
__----J/
, ____---J/
LEA
INPUT
INPUT
(LED)
B[O:71. BPAR
(AlO:7]. APAR)
OUTPUT
TLlF/10693-13
LEA --- BPAR, B[0:71
(LEB --- APAR, A[0:7])
FIGURE 10
•
7-85
AC Path (Continued)
LEA
(LEB)
'''"
,~
~/
APAR; A[O:7l
(BPAR, a[o:7l)
-
TS(H) -
TS(H), TH(H)
INPUT
INPUT
I- TH(H)
lTL/F/10693-14
LEA .... APAR, A[O:7J
(LEB ..... SPAR, B[O:71)
FI~URE 11
LEA
(LEB)
'''"
APAR, A[O:7J
(SPAR,8[0:71)
'"
TS(L)-
TS(L), TH(L)
INPUT
~/
-
INPUT
I- TH(L)
iTLlF/10693-15
LEA -+ APAR, A[O:7J
(LEB .... BPAR, B[O:71)
FIGURE 12
,
LEA
(LEB)
"'-
INPUT
APAR, A[O:7)
(BPAR, B[0:71)
INPUT
SPAR, A[0:71
(APAR, B[O:7I)
OUTPUT
I-
TW--
TLlF/10693-16
FIGURE 13
7·86
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
54FCTA
74FCTA
Terminal Voltage with Respect to GND (VTERM)
-0.5Vto +7.0V
54FCTA
74FCTA
-0.5Vto +7.0V
4.5Vto 5.5V
4.75V to 5.25V
Input Voltage
OVtoVee
Output Voltage
OVtoVee
Temperature under Bias (TBIAS)
74FCTA
54FCTA
-55°C to + 125°C
-65°C to + 135°C
Storage Temperature (TSTG)
74FCTA
54FCTA
Operating Temperature (TA)
54FCTA
74FCTA
-55°C to + 125°C
- 65°C to + 150°C
Junction Temperature (TJ)
CDIP
PDIP
Power Dissipation (PT)
0.5W
- 55°C to + 125°C
-O°Cto + 70°C
175°C
140°C
120 rnA
DC Output Current (lOUT)
Note 1: Absolute maximum ratings are those values beyond which damage
to'the device may occur. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. The databook specifications
should be me~ without exception, to ensure that the system deSign Is reliable over its power supply, temperature, and output/input loading variables.
DC Characteristics for 'FCTA Family Devices
Typical values are at Vee = 5.0V, 25°C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vee = 5.0V ± 5%, T A = O°C to + 70°C; Mil: Vee 5.0V ± 10% T A = - 55°C to
+ 125°C, VHe = Vee -0.2V
Symbol
54FCTA174FCTA
Parameter
Min
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
IIH
Typ
Units
Conditions
Max
2.0
V
0.8
V
Input High Current
5.0
5.0
",A
Vee
=
Max
VI
VI
=
=
Vee
2.7V (Note 2)
IlL
Input Low Current
-5.0
-5.0
",A
Vee
=
Max
VI
VI
=
=
0.5V (Noie 2)
GND
loz
Maximum TRI-STATE
Current
10.0
10.0
-10.0
-10.0
VI
VI
VI
VI
=
=
=
=
Vee
2.7V (Note 2)
0.5V (Note 2)
GND
-0.7
VIK
Clamp Diode Voltage
los
Short Circuit Current
-60
2.8
3.0
VOH
Minimum High Level
Output Voltage
VHe
2.4
2.4
Vee
4.3
4.3
VOL
Maximum Low Level
Output Voltage
lee
Maximum Quiescent
Supply Current
.:\Iee
Quiescent Supply Current;
TIL Inputs HIGH
-1.2
-120
",A
Vee
=
Max
V
Vee
Vee
=
=
Min; IN
rnA
Vee
=
3V; VIN
V
=
-18 mA
Max (Note 1); Vo
=
=
10H
10H
10H
=
GND
0.2
GND
0.3
0.3
0.2
0.55
0.55
V
0.001
1.5
rnA
Vee = Max
VIN ;;;: VHe, VIN ~ 0.2V
fl = 0
0.5
2.0
rnA
Vee = Max
VIN = 3.4V (Note 3)
7-87
3V; VIN
GND
0.2V or VHe; 10H
Vee = Min
VIN = VIH or VIL
Vee
=
=
=
=
0.2V or VHe; 10L
Vee = Min
VIN = VIH or VIL
IOL
10L
IOL
=
=
=
=
-32 ",A
-300,.,.A
-12mA(Mil)
-15 rnA (Com)
=
300 ,.,.A
300,.,.A
48 rnA (Mil)
64 rnA (Com)
•
DC Characteristics for 'FCTA Family Devices
(Continued)
Typical values are at Vee = 5.0V, 25'C ambient and maximum loading. For test conditions shown as Max, use the value
specified for the appropriate device type: Com: Vcc = 5.0V ±5%, TA = O'C to +70'C; Mil: Vee = 5.0V ±10% TA = -55'C
to + 125'C, VHC = Vcc -0.2V (Continued)
Symbol
Parameter
54FCTA174FCTA
Min
leeD
Ic
Dynamic Power
Supply Current (Note 4)
Typ
Max
0.25
0.40
1.5
4.0
1.8
5.0
Total Power
Supply Current (Note 6)
Units
mA/MHz
6.5
5.0
14.5
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This psrameter guaranteed but not tested.
Note 3: Per TTL driven input (YIN = 3.4y); all other inputs at Vcc or GND.
Note 4: This psrameter Is not directly testable, but Is derived for use In Total Power Supply calculations.
Note 5: Values lor these conditions are examples of the Icc lormula. These limits are guaranteed but not tested.
Note 6: Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ie = Icc + bolCC DHNT + ICCD (ICp/2 + II N~
Icc = Quiescent Current
bolcc = Power Supply Current for a TTL High Input (YIN = 3.4y)
DH = Duty Cycle lor TTL Inputs High
NT = Number of Inputs at DH
ICCD = Dynamic Current Caused by an Input TransHion Pair (HLH or LHL)
fcp = Clock Frequency lor Register Devices (Zero lor Non·Register Devices)
fl = Input Frequency
NI = Number of Inputs at II
All Currents are In milliamps and all frequencies are In megahertz.
7·88
VCC = Max
Outputs Open
One Input Toggling
50% Duty Cycle
Vee = Max
Outputs Open
fl=10MHz
One Bit Toggling
50% Duty Cycle
mA
3.0
Conditions
(Note 5)
VCC = Max
Outputs Open
fl = 2.5 MHz
Eight Bits Toggling
50% Duty Cycle
VIN ~ VHC
VIN~ 0.2V
VIN ~ VHC
VIN ~ 0.2V
VIN = 3.4V
VIN = GND
VIN ~ VHC
VIN ~ 0.2V
VIN
VIN
= 3.4V
= GND
AC Electrical Characteristics
Symbol
Parameter
S4FCTA174FCTA
74FCTA
S4FCTA
TA = +2S'C
Vee = S.OV
TA. Vee = Com
RL = soon
CL = SOpF
TA. Vee = Mil
RL = soon
CL = SOpF
Fig.
No.
Typ
Min
Max
tpHL
tpLH
Propagation Delay
An to Bn or Bn to An
10.0
2.5
11.0
ns
1
tpHL
tpLH
Propagation Delay
APAR to BPAR or
BPARtoAPAR
11.0
1.5
8.0
ns
1
tpHL
tpLH
Propagation Delay
A to BPAR orB
to APAR SEL = 0
13.0
2.5
11.5
ns
2
tpHL
tpLH
Propagation Delay
A to ERRA or B to ERRB
13.0
2.0
11.0
ns
3
tpHL
tpLH
Propagation Delay
ODD/EVEN to ERRA, ERRB
or APAR, BPAR
13.0
2.0
11.0
ns
4,5
tpHL
tpLH
Propagation Delay
SEL to APAR or BPAR
10.5
1.5
8.5
ns
9
tpHL
tpLH
Propagation Delay
LEA/LEB to B/ A
or BPAR/ APAR
11.0
2.0
11.0
ns
10,11
tpZL
tPZH
Output Enable Delay
9.5
1.5
10.0
ns
7,8
tpHZ
tpLZ
Output Disable Enable
11.0
1.5
8.5
ns
7,8
tSET
Setup Time
A to LEA or B to LEB
3.0
3.0
ns
11,12
tHOLD
Hold Time
A to LEA, B to LEB
1.5
1.5
ns
11,12
tw
Pulse Width
LEA or LEB
5.0
4.0
ns
13
7-89
Min
Units
Max
Section 8
Ordering Information and
Physical Dimensions
Section 8 Contents
Ordering Information and Physical Dimensions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
8-2
8-3
o
a.
~National
CD
::::!.
::11
Semiconductor
CQ
S-
a'
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74AC/ACT
I
~~
P
C
QR
L
Temperature Range Family
74AC = Commercial FACTTM
54AC = Military FACT
74ACT = Commercial TIL-Compatible FACT
54ACT = Military TIL-Compatible FACT
74ACQ = Commercial Quiet Series
54ACQ = Military Quiet Series
74ACTQ = Commercial Quiet Series TIL-Compatible
54ACTQ = Military Quiet Series TIL-Compatible
74FCT = Commercial FCT TIL-Compatible
54FCT = Military FCTTIL-Compatible
74FCTXXXA = Commercial FCT A-Speed
TIL-Compatible
54FCTXXXA = Military FCT A-Speed TIL-Compatible
74FCTXXXB = Commercial FCT B-Speed
TIL-Compatible
54FCTXXXB = Military FCT B-Speed TIL-Compatible
Special Variations
X = Devices shipped in 13" reels
QR = Commercial grade device with
burn-in
QB = Military grade device with
environmental and burn-in
processing shipped in tubes
Temperature Range
C = Commercial JEDEC
AC/ ACQ/ ACT / ACTQ
(- 40·C to + 85·C)
FCT,FCTXXXA
(O·C to + 70·C)
J = Commercial EIAJ
AC/ ACQ/ ACT / ACTQ
(- 40·C to + 85·C)
M = Military ( - 55·C to + 125·C)
Device Type
Package Code
P = Plastic DIP
SP = Slim Plastic DIP
D = Ceramic DIP
SD = Slim Ceramic DIP
F = Flatpak
L = Leadless Ceramic Chip Carrier (LCC)
Q = Plastic Leaded Chip Carrier (PCC)
S = Small Outline (SOIC)
For most current packaging InformatIon, contact Product MarketIng.
JEDEC-EIAJ Small Outline Package Comparison
14 Pin
Dim
20 PIn
16 Pin
24 PIn
MIn
Max
MIn
Max
Min
Max
MIn
Max
A
0.228
(5.80)
0.245
(6.20)
0.228
(5.80)
0.245
(6.20)
0.393
(10.0)
0.420
(10.65)
0.393
(10.0)
0.420
(10.65)
B
0.149
(3.80)
0.158
(4.00)
0.149
(3.80)
0.158
(4.00)
0.291
(7.40)
0.300
(7.60)
0.291
(7.40)
0.300
(7.60)
A
0.300
(7.62)
0.350
(8.89)
0.300
(7.62)
0.350
(8.89)
0.300
(7.62)
0.350
(8.89)
0.300
(7.62)
0.350
(8.89)
B
0.198
(5.02)
0.245
(6.22)
0.198
(5.02)
0.245
(6.22)
0.198
(5.02)
0.245
(6.22)
0.198
(5.02)
0.245
(6.22)
JEDEC
EIAJ
Units: Inch (mm)
WOI
8-3
f
A
1
TLlF/l0162-2
3
ao·
::11
!o
"i!
Q)
E
~National
~ Semiconductor
All dimensions are in inches (millimeters)
i5
ii
u
~
a.
64 Lead Side Brazed Ceramic Dual-In-Line Package (D)
NS Package Number D64A
MAX------------------,,·~I
1.>------------------(:z~:1
u u
« u u
n
~
~
H
9
M
~
~
9
~
H
H
M "
U
q
U
q
~
q
N
~
D
H
~
~
l
~~~"~'r'·~,'~IO-E~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;::r.
2
3
I
I
~
11
12
13
M 15
1&
17
U
19
m "
n
D
U
Hun
n
n
_
~
H
D.150-0m!
,r--(~:::IMAXSQUARE__113.•,0rlllllll
I:::::::~J TVP
I-----(~'~~I IEF---_I
LEADS,VERTICAL
'MIl" MAX
OUTWARDTY'
Note: FACDM Product Shipped WITHOUT Protective Silicon "Bumpers",
20 Terminal Ceramic Leadless Chip Carrier, (L)
NS Package Number E20A
t ·, ,· ·,·,
I
o
iWomOii'-'
ropYiew
~
0.015
To:3iif
MINTYP
~-->O;:'l<-o"""""",,-.!.
10.178-0,2791
RTVP
t
SId. View
45')(~
(U16±D.211i41
'PLCS
BotlomVlew
.!:!!!..
o.OOa
(G07Bh
~ . .(0.381)
MINlYP ~ MAXTyP
""'T
(0.559,---..
MAX TYP
.!!!.
(0.152)
MINYYP
Dal.lllA
8-4
45")(~
(D.311±lUS4,
o.a07-0.011
0.045-0.055
11.143-1.3971
,yp
,-----------------------------------------------------------------------------, ::r
~
28 Terminal Ceramic leadless Chip Carrier (l)
NS Package Number E28A
~
~
c
§.
0,065-0,076
111.651-1.930)
o·
::s
D
en
TOP
VIEW
SIDE
BonOM
VIEW
VIEW
E2BA (REV C}
84 Terminal Ceramic leadless Chip Carrier (l)
NS Package Number E84B
-fr;,.l!!!i!!!!.I' ""''''1_
IZI.4D±D.ZICI -"'Tflftrl
I
...
".,
L
f
"'I
--
CD
::s
en
II,DlIOtO.1Ift
.-
o.oU:U.D03
~i1.i'fi±i.iiii ----1r(O.114±O.~11
I
TYP
__
1
('''UI
I
0
""'
BOnDMVIEW
TDPVlEW
8·5
SlDEVlfW
14 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J 14A
0.185
1
·----(l9.939)---~·~1
MAX
0.026
(0.635)
t
0.220-0.310
(5.688-7.874)
RAD
L.....,-:-r-r::'T"T";"T"'T":'Ir"'r.'n~r-.J
0.125-0.200
(3.175-5.080)
0.150
(3.81)
MIN
J14A (REV G)
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
0.025
(0.635)
RAo
0.005-0.020
(0.127 0.50S)
RAD TYP
-.=\.
0.290-0.320
I
~f.!\J(7'366-S'12S)
0.IS0
(~~~2)
95·+5·
0.310 - 0.410
(7.S74 -10.41)
0.005--1
0.200
r
(5,;.':)
~ ~~~~~~~~~~~~.:~1~--+--J0.00S-0.012
~(0'203-0'3:~~80
J
(2.~~
BOTH
ENDS
J16AIREVK)
8·6
"U
~
20 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
~
o
0.985
~-----(25.019)
3'
CD
-----.
MAX
::I
(II
0'
::I
(II
0.180
(4.572)
0.290 - 0.320
(7.3SS-8.128)~
MAX
GLASS SEALANT
0.008-0.012
'J
0.200
(5.080)
MAX
0.125-0.200
(3.175-5.080)
86' 9
(0.203-0.305)
I....(7.874-10.41)
0.310-0.410
(1.524)
MAX
BOTH ENDS
t
IL
II
0.018±0.003 __
(0.457±0.07S)
O.OSO
0.100±0.010
(2.540±0.254)
J20A(REVMI
24 Lead Slim (0.300" Wide) Ceramic Dual-In-Line Package (SO)
NS Package Number J24F
O.UZS
11.83&) HAD
1.290
1 - - - - - - -132.77) M A X - - - - - - - - t
r
~~0.1~8or.---·H;~~~~~~~~~~~~~~~~"··r·~: !fFi
0.030-0.065
10.782-1.397)
I~::: ::~:;) TVP
0.020-0.070 HAD TiVP
I::~::~:~!:)
MAX
J, •
H---:.+:~-:)- I
MIN
95':1$'
0.31D-OA10
1--17.874-10A1I
~
I ~;pU3-0.305)
-I
JZ4flIlEVGI
8·7
28 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J28A
1--1·-------13'::)MAX
-------·--11
0.600
115.240)
.......u.:::&....I:"'-'.::L."""..J:.!Ju.:::J..I.!:U::J...L!!I....I!:I...J..:!L....\ _ _+-MAXGLASS
r~.=
0.025
10.&35)
RAD
0.514-0.526
0.030-0.055
10.762-1.397)
RAD TVP
0.180
Note: FACDM Product Shipped WITHOUT Protective Silicon "Bumpers".
14 Lead Small Outline Integrated Circuit (S)
NS Package Number M14A
,-
0.335-0.344
18.509-8.738)
- 1114
13
12
11
10
_I
9
0.228-0.244
15.7H91i6.198)
30'
0
~TYP
~;::;:r=rr::r:i::;:;:::j;l
LfAD NO. 1
IDENT
8
__
I
1~
2
..!!:!!!!.MAX
10.254)
0.010-0.020 45'
(0.264-0.508) x
,
0.053 -0.069
11.346 -1.753)
8' MAX TVP
l-f'
SEATING
PLANE
f ot.*
(0.356)
0.018 -0.050
(0.406-1.270)
TYP ALL LfADS
0.004-0.010
~a
~J
(1.270)
TVP
I-JL
-
-
-
..§.~
j e J - 010.356-0.508)
. 0 2 0 TYP
~TVP .
10.203)
8-8
(0.102-0.254)
M14A(REVftl
14 Lead Small Outline Package - EIAJ (SJ)
NS Package Number M 140
~JJ€
t--J L. .
-uo
(0.408 - 0.787)
DETAILF
0.071
0.067 -0.083
'r:
:
f ~*
~ f ;""...--J
1.--(1.270)
0.014-0.020
SEEDETAILF
JL~
(0.000 - 0.254)
(o.a56 - 0.508)
M14DIREVA)
16 Lead Small Outline Integrated Circuit (S)
NS Package Number M16A
1r
0.150-0.157
i'3.iii='3.iiii
~X45'
(0.254 - 0.5081
L
~y::t~~J
0.D08C
[;----i
-r--j
I 0.004
(0.1021
0.1153-0.1169
(1.34&-1.7531
8° MAX TYP
ALLlfADS
L-±.
0.01M-O.010
~
+
0.050
iWOi
(0.408-1.2701
TYP
TVP ALL lfADS
.
j
O.DOI TVP
(0.203)
ALL LEAD TIPS
8·9
-.-J
SEAlING
PLlNE
0.014-0.020 TVP
(U58 -8.508)
~ r-------------------------------------------------------------------------------------~
C
.~
;
16 Lead Small Outline Package - EIAJ (SJ)'
NS Package Number M16D
E
is
B
10
9
.~
.c
a.
t-JJe
L0.01H031
(0.406 - 0.787)
DETAILF
0.071 REF
0.D87 - 0.D83
(1.803)
(1.702-2.101)
L 6"---""-'. .,. - ,-~.-----Ltt
f ~J
I.--Lt--'""
0.014-0.020
SEE DETAIL F
(0.000-0.254),
(0.358 - 0.501)
,
M16DtREVA)
20 Lead Small Outline Integrated Circuit (S)
NS Package Number M20B
..
0.496-0.112
(.2.6118-13.005)
0.Dl3-0.104
(2.362 -2.642)
I'MAXTYP
~~"===s~-=+S
I
0.009-0.0'3
{i.iii':ii.iiOi
TVP ALL LEADS
(:::./
AU l.EAD TIPS
001. 0050
...... 10:40&=':2701
•L
~ 0.DIM-0.012
t f J '1
(:.~:)
.
TYP ALL LEADS
8-10
LJL
(0.102-0.305)
~--.-lSEATlNa
(l.m)
TYP
t
PlAN£
~lYP
_.!!I!!.
_
..!!.!!!!!.TYP
(0.203)
(0.356-0.508)
M_tAEYF)
20 Lead Small Outline Package - EIAJ (SJ)
NS Package Number M20D
0.492 - 0.500
~--------(I~~-12JO)--------~
20
19
18
17
16
15
14
13
12
11
~k
JL
0.016-0.031
(0.406 - 0.787)
DETAILF
0.071 REF
(1.803)
0.067 - 0.083
(1.702 _ ~108)
~__________~~t
~r=1HHHAH H
--J ~(1.270)
J
H H
~ i
tt
r=~
0.014 - 0.020
SEEDETAILF
SEATING PLANE
Lo.ooo_o.ol0
(0.000- D.254)
(0.356 - 0.508)
M200(REVAl
24 Lead Small Outline Integrated Circuit (S)
NS Package Number M24B
r .........., , .. .
0.596-0.&12
~1'5'''-'5'541-------1~
~
~f:. ~°fF::~~~~~~~~~~~~flI
L---f.
2
3
--IL~
4
5
6
7
8
9
'0
11
.2
,0.6861
~-----
17.39'-7.5941
0.017
4321
'0.
xe5"
~
10.229-0.3301
TYP ALL WDS
-+
-,
0.037-0.044
1
,0.940-'.1181
t
r:::!)"!"':===;r=~~
f
0.004
iD.iD2i
0.093-0.104
~
hUtiDtiriiitiil
t] L~
JL
+
0° _8° np All LEADS
+
[:I.oso
0.DD'-0.0.2
,0··02io.3051
f
o.oLo.o.g
~
,'.2701
TVP ALL laDS
ALL laD TIPS
8·11
10.35&-U831
TVP
o ,---------------------------------------------------------------------------------,
C
o
'ecn
CP
28 Lead Small Outline Integrated Circuit (S)
NS Package Number M28B
E
C
'5
'!
.c
INDEX
AREA
a.
10.65 (0.420)
10.00 (0.393)
1
I'
18.10 (0.713)
17.70 (0.696)
I
0.75 (0.030) .45.
0.25 (0.009)
I
(o.ol~3)
0.32
0.23 (0.009)
L
'Jl~:
1.27 (0.050)
0.49 (0.020)
0.35 (0.013)
Bse
-1~~1
_
~"::;:~==:::::;1==~
!
2.65 (0.105l
2.35 (0.092
0.30 (o.012l
-C0.10 (0.003
1.27 (0.050)
0.40 (0.015)
t.128B
14 Lead Plastic Dual-In-Line Package (P)
NS Package Number N 14A
OPTION 1
IJI'TION D2
0.131i±0.1I05
(3.429±O.127)
0.3110-0.320
4'TYP
OPTIONAL
0.020
(0.508)
MIN 0.12&-0.150
(3.175-3.810)
-I
I
1
0.014-0.023 TYP- _
(0.356-0.584)
~
....
f
9Do±4° TYP
-
_
I
I
_~TYP
4-~
(1.905±0.381)
0.100 to.OIO TYP
(Z.640±0.Z54)
_-_I
~
0.085
(1-;51)
/fC=;:.~f
95'±S'
~TYP
(0.203-0.4011)
0.Z80
(7.112) ____
MIN
0.325~~::
(1.270 -0.254)
18255 +1.016)
~ .
-G.381
8-12
N14AIR£VFI
r--------------------------------------------------------------------------,
16 Lead Plastic Dual-In-Line Package (P)
NS Package Number N 16E
. ,.'':,
PIN NO. lJ~'T'll'~i'i"T'i'i"m"i'ii''i''j';i'i''i'iiP
IDENT
OPTION 01
0.145-0.200
(3.683 - 5.080)
o.o!o
MIN]
(0.508)
r= L
0'125-0"5~
(3.175-3.810)
0.014- 0.023
(0.356 - 0.584)
,
1
3'
CD
~
In
o·
~
In
r
0.065
(1.651)
5;,~'t -!~"
I-
0.280.:..:j
I. ~ .1
I- 0.030:1:0.015
(0.762:1:0.381)
1 0.100:1:0.010
f4"" (2.540:1: 0.254)
(0.325
TYP
TYP
0.300-0.320
N
(D.203- Q..4(6)
!8:8tg
N16E (REY F)
(B.255~k~1~)
20 Lead Plastic Dual-In-Line Package (P)
NS Package Number N20B
0.092 x0.030
12.337 x0.762)
MAXOP
~!::!:::!:::!:!:=============='2 I,
~
(~:~~:)-
~~D'9
(0.813'0.127)
RAD
====I"
0.240-0.260
16.096-6.6041
PIN NO.1 IDENT
PIN NO.lIDENT~
~~mffi9.mffiT.~~~~
,
MIN
OPTION 2
0.290-0.325
C'
I -"" I
I
(~r-----~-------++-------~
9_"
.
.
"rJ
1-·----1 ~NOM
~197'5' ±7~
~NOM
(8.890)
-gOo.0.004°L
10.203-0.381)
(1.016)
I
I
~
!- 0.014-0.023 _
I
0.020
O. I 25-0.150 (0.508)
(3.175-3.8101
MIN
(0.355-0.5851
N2CIBIREVA)
8·13
~
~
c
I~~g:c:
PIN NO.1'
.. .
IDENT
1 2
OPTION 02
~
!o
'US
c
CP
E
24 Lead Plastic Slim (0.300" Wide) Dual-In-Line Package (SP)
NS Package Number N24C
is
0.092
(2.337)
'8
(2 PLS)
'!
f
.c
a.
0.260±0.005
(6.604±0.127)
I
OPTION 2
r:'-I
0.300-0.320
0.009-0.015
(0.229-0.381)
0.325 ~~:~~~
0.062
(1.575)
HAD
-r-J I
0.065
(1.651)
-+~"':=---I
0.075±0.015
(1.905±0.3Sl)
(8255 +1.016)
(.
-0.381
I-N24C(REVF)
28 Lead Plastic Dual-In-Line Package (P)
NS Package Number N28B
PIN NO. 1 IDENT
I
FrtC
o.oa;.~ MAX
(O.762
0.600-0.620
--1
~-Li
0.145-0.210
'.-'N
'~~_5'334)
(0.229-0.381)
0.050tO.015
(U70tO.381)
I ~
(4-
0.125-0.145
(3.1711-3.683)
HHBIREYE)
8·14
"U
-!C:i"
64 Lead Plastic Dual-In-Line Package (P)
NS Package Number N64A
!!!.
C
Err
CD
::::II
rn
o·
::::II
rn
1:':1 1
20 Lead Plastic Chip Carrier (Q)
NS Package Number V20A
4SMCES AT
0.050
(1.270)
iiT43i
0.045if
)(45
0
I
0.080
18
iZ]3ii
~~"'''''''-+-.....L.P~:E~~:L
tu~
4SPACESAT
0.050
iWoi
:P15'
VIEW A·A
0.226
(5.T4O)
NOM
SOUARE
0.310-0.330
(7.BT4-8.382)
(CONTACT DIMENSION)
0.026-0.032
(0.660-0.B13)
0.020
TYP
0.l1li8-0.011
(0.127-0.381)
j~:~~;'1~~~~~~t~
iD.5Oii
0.032-0.040
(0.813-1.016)
MIN
PIN NO.1
10ENT
V2QA(AEYJ)
8·15
o
c:
.~
5i
.-----------------------------~--------~--------------------~----~--------.
28 Lead Plastic Chip Carrier (Q)
NS Package Number V28A
E
is
B
.~
.s::.
a.
l
0.020
0.032, -0.040
(0.813-1.0161
+
iD.iOai
t==t
MIN
Ul0-0.430
(iiF-iD.iij
,
SQUARE
(CONTACT DlMENSIONI
~
I
0.013-0.011
(0.830-0.4571
7YP
0.165-0.180
(4.191-4.5721
.
* t
IS'
0.026-0.032
(0.660-0.8131
7YP
V28A (REV G)
68 Lead Plastic Chip Carrier (Q)
NS Package Number V68A
0.020
(O:5iiii
MIN
0.104-0.118
(2.542-2.9971
~
,---
0.910-0.930 \
(23.11-23.62)
SQUARE
CONTACT
OIMENSION
43
0.013-0.018
(0.330-8.4571
TIP
0.950
(24.13)
REFSQ
0.185-0.915
(25.02-25.27)
SQUAIE
27
0.826 ______.....~I
~.I--____ (20.98)
NOM
V88A (REV 0,
8·16
"'tI
::r
84 Lead Plastic Chip Carrier (Q)
NS Package Number V84A
':ine!-
~-Ir
o
3"
(1.524)
.IN
TYP
0.020
tOM~al
"
Ir
CD
::::I
..!!!!.=ll!!.
til
12.642-2.1197)
ci"
::::I
II
til
l 1{j
°'085
12,1601
NOM
~
(21.21)
REFSQ
UAIIND. 1 IDEKT
D.DfiD
(UiZ4)
'IA
L
0.1&5-0.180
(4.181-4.5721
OD30-D.D45
(0.762-1.143)
HAO
TYP
.....
0.005-0.015
~
14 Lead Ceramic Flatpak (F)
NS Package Number W14B
0.055-0.080
(1.397-2.032)
0.026-0.035
0.005
(0.127) MIN TIP
0.050tO.005
( 1.271lJ~.127)
(0.66~~.889)
f
1413121110 9
0.280
(7.112)
MAX LASS
2 3 4 5 6
l~"
(0.203-0.305)
DETAIL A
0.250-0.370
(6.350-9.398)
0.004-0.006
(0.10t~·152)
JL
0.015-0.019
(0.381-0.483)
TYP
JL
8-17
J
(~:~~) MAX TIP
WT48 (REV H)
o
C
o
"iii
c
III
E
is
B
~
a.
r---------------------------------------------------------------------------~
16 Lead Ceramic Flatpak (F)
NS Package Number W16A
0.050-0.080
(1.270-2.032)
1 Ir--
0.004-0.006 TYP-I
(0.102-0.152)
rot-
0.371-0.390
(9.423 -9.906)
1t
0.007-0.018
10.178 -0.457)
TYP
0.050±0.005
(1.270±0.127) TYP
71-0.000 MIN TYP
.i.
0.250-0.370
(6.350-9.398)
I
rr!!16!o-:!1~51M-4~13H-12~1~1~10~9~--f
0.300
(7.620)
~
MAX GLASS
.-
0.245-0.275
(6.223-6.985)
__ ,2 3 4 5 6 7 8
OETAILA _ _ :
L
~
t
j
10ENT
l
-
0.250 -0.370
(6.350 - 9.398)
PlNNO.l.J
0.026-0.040 TYP .....
(0.660-1.016)
1r
_I
~l
0.008-0.012
(0.203-0.305)
DETAIL A
~
0.015-0.019
(0.381-0.482)
TYP
W16A(REVHI
20 Lead Ceramic Flatpak (F)
NS Package Number W20A
-+
..
0.060-0.090
(1.524-2.286)
0.030-0.040
(0.762-1.016)TYP
~. (~ij~lMAX0.05'0:1:0.005
--
1(1.270J~.127) --
0.005
MIN TYP
I-w.rm
0.2520.320
(6.350-8.128)
120191817161514131211--1
0.285
(7239)
MAX' GLASS
r
r-
2 3 4 5 6 7 8 9 10 - - 1
rV
SEE).
DETAIL
0.008-0.012
(0.203-0.305)
DETAIL A
(6.350-8.128)
1
IDENT
(0.102-0.152)
L
0.250-0.320
PIN , ; / -
__ 1--, 0.004-0.006 TYP __
]
0.260-0.227C0
(6.604-6.858)
)
L (0.381-0.483)
0.015-0.019 TYP
8·18
_
I-- 0045
(1:143) MAX TYP
W20A (REV DJ
24 Lead Ceramic Flatpak (F)
NS Package Number W24C
- r-
:,,0,,,.0:::30,---~0·704,:,0,_~
(0.762-1.o16)
r---
0.080-0.090
(2.032-2.286)
Irt-I
0.050±0.005
(1.270±0.127)
L'I'
-I
0.590-0.625;_
(14.99-15.88)
1-·
~~MINTYP
(0.127)
r
0.250 0.320
~.J.J....LJ...!.u.L..I.L..JJ...J.J..1J..IJ...1.1..J..J.1~8.128}
~
0.400
(10.16)
(~:~~~7~:~i~
..
r
~
0.004-0009
_11_
•
IJ> 2
3 4 5 6 7 8 9 10 11 12
/ )(
~
O~:;II~~.:'~J
0.011-0.025
0.250-0.320
(6.350.
PIN #1
IDENT
(REFER
"mFr
~-8.128)
-i(9.271_9.652)
OPTIONAL/ /
(0102-0229)
0.365-0.380
ss
t
t
24 23 22 21 20 19 18 17 16 15 14 13
_ _ 0.015-0.019 TYP
I
_
(0.381-0.483)
0.008-0.015
(0.203 -0.381)
8-19
J
_I
0.008-0.015
~ (0.203-0.381)
OETAIL ··A"" PIN # 11DENT OPTION 2
f.-;0.045 MAX
(1.143)
W.'4C(REV Dl
NOTES
NOTES
~National
D
Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 16-300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara. CA 95052-8090
AlS/ AS lOGIC DATABOOK-1990
Introduction to Advanced Bipolar Logic. Advanced Low Power Schottky. Advanced Schottky
ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CEllS-1987
SSI/MSI Functions. Peripheral Functions. LSIIVLSI Functions. Design Guidelines. Packaging
CMOS lOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount
DATA ACQUISITION liNEAR DEVICES-1989
Active Filters • Analog Switches/Multiplexers. Analog-to-Digital Converters. Digital-to-Analog Converters
Sample and Hold. Temperature Sensors. Voltage Regulators • Surface Mount
DATA COMMUNICATION/lAN/UART DATABOOK-1990
LAN IEEE 802.3 • High Speed Serial/IBM Data Communications. ISDN Components. UARTs
Modems. Transmission Line Drivers/Receivers
DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides. Diodes. Bipolar NPN Transistors
Bipolar PNP Transistors. JFET Transistors • Surface Mount Products • Pro-Electron Series
Consumer Series. Power Components. Transistor Datasheets • Process Characteristics
DRAM MANAGEMENT HANDBOOK-1989
Dynamic Memory Control. Error Detection and Correction • Microprocessor Applications for the
DP8408A109A117 /18/19/28/29. Microprocessor Applications for the DP8420Al21A122A
Microprocessor Applications for the NS32CG821
EMBEDDED SYSTEM PROCESSOR DATABOOK-1989
Embedded System Processor Overview. Central Processing Units. Slave Processors. Peripherals
Development Systems and Software Tools
F100K ECl lOGIC DATABOOK & DESIGN GUIDE-1990
Family Overview. 300 Series (Low-Power) Datasheets. 100 Series Datasheets • 11 C Datasheets
ECL BiCMOS SRAM. ECL PAL. and ECL ASIC Datasheets • Design Guide. Circuit Basics. Logic Design
Transmission Line Concepts. System Considerations. Power Distribution and Thermal Considerations
Testing Techniques. Quality Assurance and Reliability. Application Notes
FACTTM ADVANCED CMOS LOGIC DATABOOK-1990
Description and Family Characteristics. Ratings, Specifications and Waveforms
Design Considerations • 54AC174ACXXX • 54ACT 174ACTXXX • Quiet Series: 54ACQ/74ACQXXX
Quiet Series: 54ACTQI74ACTQXXX. 54FCTI74FCTXXX. FCTA: 54FCTXXXA174FCTXXXA
FAST® ADVANCED SCHOTTKY TTL LOGIC DATABOOK-1990
Circuit Characteristics. Ratings, Specifications and Waveforms. Design Considerations. 54F17 4FXXX
FAST® APPLICATIONS HANDBOOK-1990
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders
Operators. FIFOs • Counters. TTL Small Scale Integration. Line Driving and System Design
FAST Characteristics and Testing. Packaging Characteristics
GENERAL PURPOSE LINEAR DEVICES DATABOOK-1989
Continuous Voltage Regulators • Switching Voltage Regulators. Operational Amplifiers. Buffers • Voltage Comparators
Instrumentation Amplifiers. Surface Mount
GRAPHICS HANDBOOK-1989
Advanced Graphics Chipset. DP8500 Development Tools. Application Notes
INTERFACE DATABOOK-1990
Transmission Line Drivers/Receivers • Bus Transceivers. Peripheral Power Drivers. Display Drivers
Memory Support. Microprocessor Support. Level Translators and Buffers. Frequency Synthesis. Hi-Rei Interface
LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.
LS/S/TTL DATABOOK-1989
Contains former Fairchild Products
Introduction to Bipolar Logic. Low Power Schottky. Schottky. TTL. TTL-Low Power
MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors • Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller. SCSI Bus Interface Circuits • Floppy Disk Controllers. Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits. Rigid Disk Microcontroller Circuits. Disk Interface Design Guide
MEMORY DATABOOK-1990
PROMs, EPROMs, EEPROMs. TTL I/O SRAMs • ECL I/O SRAMs
MICROCONTROLLER DATABOOK-1989
COP400 Family. COP800 Family. COPS Applications • HPC Family. HPC Applications
MICROWIRE and MICROWIRE/PLUS Peripherals. Microcontroller Development Tools
MICROPROCESSOR DATABOOK-1989
Series 32000 Overview • Central Processing Units • Slave Processors • Peripherals
Development Systems and Software Tools. Application Notes. NSC800 Family
PROGRAMMABLE LOGIC DATABOOK & DESIGN MANUAL-1990
Product Line Overview. Datasheets • Designing with PLDs • PLD Design Methodology. PLD Design Development Tools
Fabrication of Programmable Logic • Application Examples
REAL TIME CLOCK HANDBOOK-1989
Real Time Clocks and Timer Clock Peripherals • Application Notes
RELIABILITY HANDBOOK-1986
Reliability and the Die. Internal Construction. Finished Package. MIL·STD·883 • MIL·M·3851 0
The Specification Development Process. Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge. Discrete Device. Standardization
Quality Assurance and Reliability Engineering. Reliability and Documentation. Commercial Grade Device
European Reliability Programs • Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Military/Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL·M·38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication • Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms • Key Government Agencies. AN/ Numbers and Acronyms
Bibliography. MIL·M·3851 0 and DESC Drawing Cross Listing
SPECIAL PURPOSE LINEAR DEVICES DATABOOK-1989
Audio Circuits • Radio Circuits • Video Circuits • Motion Control Circuits • Special Function Circuits
Surface Mount
TELECOMMUNICATIONS-1990
Line Card Components • Integrated Services Digital Network Components. Analog Telephone Components
Application Notes
~ National
~ Semiconductor
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