1990_OKI_Memory_Data_Book 1990 OKI Memory Data Book

User Manual: 1990_OKI_Memory_Data_Book

Open the PDF directly: View PDF .
Page Count: 800

Download
Open PDF In Browser	View PDF

DATA BOOK

OKI

MEMORY

OKI
Semiconductor
FIFTH EDITION
ISSUE DATE: FEB ., 1990

MEMORY
DATABOOK

1990/1991

IC MEMORY LINE-UP AND
TYPICAL CHARACTERISTICS
PACKAGING

RELIABILITY INFORMATION

MaS DYNAMIC RAMS

MaS STATIC RAMS

MOS MASK ROMS

(I

fill
0
~

HI
01

MOS EP ROMS/OTPS

01

MaS E2PROMS

HI

ASMP

n

CROSS REFERENCE LIST

[[!J

APPLICATIONS

III

II
TOPICS

TO THE READER:

11

11

This FIFTH Edition contains the data of following new devices in addition to the
descriptions in FOURTY Edition.

1. DRAM

3. SRAM

MSM511000A

MSM51257AL

MSM511001A

MSM51257ALL

MSM511002A
MSM514256A

4.

MSM514258A

6
11
D

In

MSM534001A

MSM514102

MSM534002A

MSM514400
MSM514402

2. SIMM/SIMD
MSC2312A-XXYS9/KS9
MSC2313A-XXYS8/KS8
MSC2320A-XXYS9

MSC2328A-XXYS2/KS2
MSC2331 A-XXYS3/KS3
MSC2340-XXYS9/KS9

II]]

MSM534000A

MSM514100

MSC2321 A-XXYS 18

~

MROM

5.

E2PROM
MSM28C256

6. ASMP
MSM514212
MSM51C262

CONTENTS
D

D

IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS ............. 3
•

MOS MEMORY HAN DUNG PRECAUTIONS
1. STATIC ELECTRICITY COUNTERMEASURES .......................... 12
2. POWER SUPPLY AND INPUT SIGNAL NOISE ........................... 12
3. CMOS MEMORY OPERATING PRECAUTIONS .......................... 12

•

MASK ROM CUSTOMER PROGRAM SPECIFICATIONS
1. USABLE MEDIA ................................................... 15
2. MAGNETIC TAPE SPECIFICATIONS .................................. 15
3. EPROM SPECIFICATIONS .......................................... 16

•

MASK ROM DEVELOPMENT FLOW CHART .............................. 19

•

TERMINOLOGY AND SYMBOLS
1. PI N TERMINOLOGY ............................................... 23
2. ABSOLUTE MAXIMUM RATINGS ..................................... 24
3. RECOMMENDED OPERATION CONDITIONS ........................... 25
4. DC CHARACTERISTICS ............................................ 26
5. AC CHARACTERISTICS ............................................ 27

PACKAGING ......................................... , ............... 31
• 8 PIN PLASTIC DIP (DIP8-P-300) ........................................ 34
• 16 PIN PLASTIC DIP (DIP16-P-300, DIP16-P-300-W1) ....................... 34
• 18 PIN PLASTIC DIP (DIP18-P-300, DIP18-P-300-W1, DIP18-P-4(0) ............ 35
• 20 PIN PLASTIC DIP (DIP20-P-300-W1, DIP20-P-4(0) ....................... 36
• 22 PIN PLASTIC SKINNY DIP (DIP22-P-300-S1 ) ............................ 36
• 24 PIN PLASTIC DIP (DIP24-P-600) ...................................... 37
• 28 PIN PLASTIC DIP (DIP28-P-600) ...................................... 37
• 32 PIN PLASTIC DIP (DIP32-P-600) ...................................... 37
• 40 PIN PLASTIC DIP (DIP40-P-600) ...................................... 38
• 8 PIN PLASTIC SOP (SOP8-P-250-K) ..................................... 39
• 28 PIN PLASTIC SOP (SOP28-P-43O-K) ................................... 39
• 60 PIN-V PLASTIC OFP (OFP60-P-1519-VK) ............................... 39
• 26 PIN PLASTIC SOJ (SOJ26-P-300, SOJ26-P-350) ......................... 40
• 18 PIN PLASTIC OFJ (PLCC) (OFJ 18-P-R290) ............................. 41
• 20 PIN PLASTIC ZIP (ZIP20-P-400, ZIP20-P-400-W1) ........................ 42
• 28 PIN PLASTIC ZIP (ZIP28-P-400) ...................................... 42
• 28 PIN CERDIP (WDIP28-G-600) ........................................ 43
• 32 PIN CERDIP (WDIP32-G-600) ........................................ 43
• 40 PIN CERDIP (WDIP40-G-600) ........................................ 43
• 30 PIN SIMM (FOR MSC2304/2307YS9) .................................. 44
• 30 PIN SIMP (FOR MSC2304/2307KS9) ................................... 44

D

•

30 PIN SIMM (FOR MSC2304YSS) ....................................... 45

•

30 PIN SIMP (FOR MSC2304KSS) ....................................... 45

•

30 PIN SIMM (FOR MSC2305YS18A) ..................................... 46

•

30 PIN SIMM (FOR MSC2312AYS9) ...................................... 47

•

30 PIN SIMP (FOR MSC2312AKS9) ...................................... 47

•

30 PIN SIMM (FOR MSC2313AYSS) ...................................... 48

•

30 PIN SIMP (FOR MSC2331AKSS) ...................................... 48

•

30 PIN SIMM (FOR MSC2331 AYS3 OR MSC2329AYS3) ..................... 49

•

30 PIN SIMM (FOR MSC2328AXXYS2) ................................... 49

•

72 PIN SIMM (FOR MSC2320AYS9) ...................................... 50

•

72 PIN SIMM (FOR MSC2321AYS18) ................................... 50-A

•

30 PIN SIMM (FOR MSC2340YS9) ..................................... 50-B

•

30 PIN SIMP (FOR MSC2340KS9) ..................................... 50-B

RELIABILITY INFORMATION
1. INTRODUCTION .................................................. 53
2. QUALITY ASSURANCE SYSTEM AND UNDERLYING CONCEPTS .......... 53
3. EXAMPLE OF RELIABILITY TEST RESULTS ............................ 56
4. SEMICONDUCTOR MEMORY FAILURES .............................. 64

D

MaS DYNAMIC RAMS
MSM3764A
MSM41256A
MSM41257A
MSM41464
MSM51C256
MSM511000A
MSM511001A
MSM511002A
MSM514256A
MSM514258A
MSM514100
MSM514102
MSM514400
MSM514402
MSC2304YS8-KSB
MSC2304 YS9-KSQ
MSC2331 A-XXYS3/KS3
MSC2312A-XXYS9JKSQ
MSC2313A-XXYS8IKSS
MSC232OA-XXYSQ
MSC2321 A-XXYS18
MSC2328A-XXYS2IKS2
MSC2340-XXYS911 .............69
262,144-Word x i-Bit RAM (NMOS)  ............85
262,144-Word x i-Bit RAM (NMOS)  ........... 100
65,536-Word x 4-Bits RAM (NMOS)  ........... 116
262,144-Wordx1-BitRAM(CMOS) ................... 131
1,048,576-Word x i-Bit RAM (CMOS)  ........... 147
1,048,576-Word x 1-Bit RAM (CMOS)  . . . . . . . . . . 162
1,048,576-Word x i-Bit RAM (CMOS)  ......... 1
262,144-Word x4-Bits RAM (CMOS)  ........... 191
262,144-Word x 4-Bits RAM (CMOS)  ......... 205
4, 194,304-Word x i-Bit RAM (CMOS)  ... . . . . . . . . 220
4,194,304-Wordx i-Bit RAM (CMOS)  ......... 234
1,048,576-Word x 4-Bits RAM (CMOS)  .......... 248
1,048,576-Word x 4-Bits RAM (CMOS)  ........ 262
262,144-Word x 8-Bits RAM (NMOS)  (MODULE) .... 2n
262,144-Word x 9-Bits RAM (NMOS)  (MODULE) .... 292
262, 144-Word x 9-Bits RAM (CMOS) (MODULE) ............ 307
1,048,576-Word x 9-Bits RAM (CMOS) (MODULE) ........... 321
1,048,576-Word x 8-Bits RAM (CMOS) (MODULE) ........... 331
262,144-Word x 36-Bits RAM (MODULE) ................ 341
524,288-Word x 36-Bits RAM (MODULE) ................ 351
262,144-Word x 8-Bits RAM (MODULE) ................. 360
4, 159,300-Word x 9-Bits RAM (CMOS)(MODULE) ........... 370

n

D

MOS STATIC RAMS
MSM5165AL

D

16,384-Word x 4-Bits RAM (CMOS) ................... 394

MSM51257AL

32,768-Word x 8-Bits RAM (CMOS) ................... 399

MSM51257ALL

32,768-Word x 8·Bit CMOS STATIC RAM ............

MSM51256

32,768-Word x 8-Bits RAM (CMOS) ................... 413

406

MOS MASK ROMS
MSM3864

D

8, 192-Word x 8-Bits RAM (CMOS) .................... 387

MSM5188

8, 192-Word x 8-Bits Mask ROM (NMOS) .............. 425

MSM38128A

16,384-Word x 8-Bits Mask ROM (NMOS) ............. 429

MSM38256

32,768-Word x 8-Bits Mask ROM (NMOS) ............. 433

MSM38256A

32,768-Word x 8-Bits Mask ROM (NMOS) ............. 437

MSM53256

32,768-Word x 8-Bits Mask ROM (CMOS) ............. 441

MSM531000

131 ,072-Word x 8-Bits Mask ROM (CMOS) ............ 445

MSM531001

131 ,072-Word x 8-Bits Mask ROM (CMOS) ............ 449

MSM534000

262, 144-Word x 16-Bits Mask ROM (CMOS) ........... 453

MSM534000A

262, 144-Word x 16-Bits MASK ROM (CMOS) .......... 458

MSM534001A

524,288-Word x 8-Bits MASK ROM (CMOS) ........... 463

MSM534002A

262, 144-Word x 16-Bits or
524,288-Word x 8-Bits MASK ROM (CMOS) ........... 468

MOS EPROMS/OTPS
MSM2764A

8,192-Word x 8-Bits EPROM (NMOS) ................. 475

MSM27128A

16,384-Word x 8-Bits EPROM (NMOS) ................ 483

MSM27256

32.768-Word x 8-Bits EPROM (NMOS) ................ 491

MSM27512

65,536-Word x 8-Bits EPROM (NMOS) ................ 499

MSM271 000

131 ,072-Word x 8-Bits EPROM (NMOS) ............... 506

MSM271024

65,536-Word x 16-Bits EPROM (NMOS) ............... 513

MSM27C256

32,768-Word x 8-Bits EPROM (CMOS) ................ 520

MSM27C256H

32,768-Word x 8-Bits EPROM (CMOS) ................ 528

MSM27C1024

65,536-Word x 16-Bits EPROM (CMOS) ............... 536

MSM27C2000

262, 144-Word x 8-Bits EPROM (CMOS) ............... 543

MSM27C2048

131,072-Word x 16-Bits EPROM (CMOS) .............. 550

MSM2764AZB

8, 192-Word x 8-Bits OTP ROM (NMOS) ............... 557

MSM27128AZB

16,384-Word x 8-Bits OTP ROM (NMOS) .............. 564

MSM27256ZB

32.768-Word x 8-Bits OTP ROM (NMOS) .............. 571

MSM27512ZB

65,536-Word x 8-Bits OTP ROM (NMOS) .............. 578

MSM271000ZB

131 ,072-Word x 8-Bits OTP ROM (NMOS) ............. 585

MSM271024ZB

65,536-Word x 16-Bits OTP ROM (CMOS) ............. 591

MSM27C256ZB

32,768-Word x 8-Bits OTP ROM (CMOS) .............. 598

MSM27C256HZB

32,768-Word x 8-Bits OTP ROM (CMOS) .............. 605

III MOS E2 PROMS
MSM16811

1,024-Word xl-Bit E2 PROM ........................ 615

MSM16811P

1,024-Word xl-Bit E2 PROM

MSM16911

1,024-Word xl-Bit E2 PROM ........................ 629

........................ 622

MSM16911P

1,024-Word xl-Bit E2 PROM ........................ 638

MSM16812

2,048-Word xl-Bit E2 PROM ........................ 647

MSM16912

2,048-Word xl-Bit

MSM28C16A

2,048-Word x 8-Bits E2 PROM

MSM28C64A
MSM28C256

8, 192-Word x 8-Bits E2 PROM ....................... 670

e PROM

........................ 654
....................... 663

32k x 8-Bits CMOS E2 PROM ........................ 678

I I ASMP

IIi]

MSM514212

5k x 8 Line Memory ................................. 681

MSM514221

262,263-Word x 4-Bits Field Memory ................. 692

MSM514252

262, 144-Word x 4-Bits Multi-port DRAM .............. 700

MSM51C262
MSM514201

65,536-Word x 4-Bits Multi-port DRAM ............... 727
1,048,576-Word x 1-Bits Serial Register ............... 757

CROSS REFERENCE LIST
1. DYNAMIC RAM ........................................................ 765
2. STATIC RAM .......................................................... 770
3. MASK ROM ........................................................... 771
4. EPROM ............................................................... 772
5. E2 PROM (serial) ....................................................... 774
6. E2 PROM .............................................................. 774
7. OTP ........................................................... _...... 775

m

APPLICATIONS
CMOS RAM BATIERY BACK-UP, ••••••••••••••••••••••••••••••••••• 779
1. SYSTEM POWER AND BATIERY SWITCHING CIRCUIT

•••••••••••.•••.• 779

2. SWITCHING CIRCUIT MODIFICATIONS .•••••••••••••• , ••••••••••••• 779
3. DATA RETENTION MODE ••.•.•.••••••••••••.••••••••••.••.••••• 781
4. INTERFACiNG ••••••.•.•.•.••••••••.•••••.••••••••••.••••.••• 782
5. MiSCELLANEOUS •.•••.•••••••••••••••••••••••••••••••••••••• 782
APPLICATION NOTE OF KANJI GENERATION MASKROM •••.•••••.••••••.• 783
1. KANJI GENERATION MEMORIES .••..••••••••.•••••••••••••••.••• 783
2. MSM38256 SERIES •.••.•.••.•••.••.•••••.••••••••••.•••••••• 784
3. MSM531000 SERIES •••••.•..••.•••••••.••••••••••••.•••••••• 788

IC MEMORY
LINE-UP AND TYPICAL
CHARACTERISTICS

[I

11
D

IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS ............. 3
•

MOS MEMORY HANDLING PRECAUTIONS
1. STATIC ELECTRICITY COUNTERMEASURES •.••••••.•••••..•••••.•.•• 13
2. POWER SUPPLY AND INPUT SIGNAL NOISE •.••.•.••••.••.••••••.•.•• 13
3. CMOS MEMORY OPERATING PRECAUTIONS •.•••••••••.••.•.•..•.••• 13

•

MASK ROM CUSTOMER PROGRAM SPECIFICATIONS
1. USABLE MEDIA .••••..•••••.•••••••.•.••••.••••..••••.•••.••• 17
2. MAGNETIC TAPE SPECIFICATIONS ••••.••.•.••••.••••••..•.•.•••••• 17
3. EPROM SPECIFICATIONS •.•.••••.••.••..•.•••..•...••...•••.••• 18

•

MASK ROM DEVELOPMENT FLOW CHART ••.••.•••.••••••••.•••.••• 21

•

TERMINOLOGY AND SYMBOLS
1. PIN TERMINOLOGY ••••••.••••••.••.••.•..•.•..•...••.•.•.• '.' •. 25
2. ABSOLUTE MAXIMUM RATINGS ••••••.•••••.••••.••..••••..••.••• 26
3. RECOMMENDED OPERATION CONDITIONS •.••••••••.••••.•••••.•.•• 27
4. DC CHARACTERISTICS ••.•••.•.•..••.•.••.•.•.••.•.•.•••••••.•• 28
5. AC CHARACTERISTICS •••.••..•••••••••.••.••••••..•••.•••••••• 29

IC MEMORY LINE-UP AND TYPICAL
CHARACTERISTICS

(I

3

II

.IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS

.1---------

IMSM38128A

I

L.,.;..:.;.;..;;..;;....I~ MSM38256 HMSM38256A

I

.....:..:~..;;.....j~ MSM53256I

--i::=:=::::::
x
256K

~MSM5310ooH

MSM531001

I

16 HMSM534000HMSM534000AH MSM534002A

--1 8K x 8

HMSM2764AZB

--116K x 8 HMSM27128AZBI
--132K x 8 HMSM27256ZB

~64K x 8 HMSM27512ZB
--1128K x 8

H MSM271000ZB H

L.,..;;.;;~..:.....I

4

MSM271024ZB

-1 MSM27C256ZB HMSM27C256HZB I

I

- - - - - - - - - . I C MEMORY LINE-UP AND TYPICAL CHARACTERISTICS.
• DYNAMIC RAMS

Model Name

MSM3764A-12

Memory
Capacity

Circuit
Function

Memory
Configuration

64k

Dynamic

65.536xl

Numberof Access
Pins
Time
per
MAX
Pack(ns)
age
16

MSM3764A-15
MSM41256A-l0

Cycle
Time
MIN
(ns)

Power
ConsumpPower
tion
Supply
MAX
Voltage
(mw)
(V)
Operating/
Standby

120

230

330128

150

260

303128

100

200

303128

120

220

275128

MSM41256A-15

150

260

248128

MSM41257A-l0

100

200

330128

120

220

303128

150

260

275128

MSM41256A-12

MSM41257A-12
f--

--

256k

256k

Dynamic

Dynamic

262.144xl

262.144xl

16

16

MSM41257A-15

100

200

385128

120

230

358128

MSM41464-15

150

260

330128

MSM51C256-80

80

145

330120

100

175

275120

120

205

248120

70

140

468/5.5

80

160

413/5.5

100

190

358/5.5
413/5.5

MSM41464-10
MSM41464-12

MSM51C256-1O

256k

256k

Dynamic

Dynamic

65.536x4

262.144xl

18

16

MSM51 C256-12
MSM511000A-70

18

MSM511000A-80
MSM511 OOOA-10

1M

Dynamic

1.048.576xl

26

MSM511000A-8A
20

MSM511 OOOA-1A
MSM511001A-70

18

MSM511001A-80
MSM511001A-l0

1M

Dynamic

1.048.576xl

26

MSM511001A-8A
20

MSM511001A-1A
MSM511 002A- 70

18

MSM511002A-80
MSM511 002A- 10

1M

Dynamic

1.048.576x1

26

MSM511002A-8A
20

MSM511002A-1A
MSM514256A-70
MSM514256A-80
MSM514256A- 10
MSM514256A-8A
MSM514256A-1 A

20
1M

Dynamic

262,144x4
26

80

160

100

190

358/5.5

70

140

468/5.5

80

160

413/5.5

100

190

358/5.5

80

160

413/5.5

100

190

358/5.5

70

140

468/5.5

80

160

413/5.5

100

190

358/5.5

80

160

413/5.5

100

190

358/5.5

70

140

468/5.5
413/5.5

80

160

100

190

358/5.5

80

160

413/5.5

100

190

358/5.5

Equivalent
Device

+5

+5

+5

+5

+5

+5

+5

+5

+5

5

(I

II

.IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS . 1 - - - - - - - - -

Model Name

Memory
Capacity

Circuit
Function

Memory
Configuration

MSM514258A-70

Number of Access
Pins
Time
MAX
per
Pack(ns)
age

MSM514258A-l0

1M

Dynamic

262, 144x4

MSM514100-80
MSM514100-8A

4M

Dynamic

4.194.304xl

MSM5141 00-10

160

413/5.5

190

358/5.5

80

160

413/5.5

100

190

358/5.5

18

80

160

495/5.5

26

80

160

·495/5.5

20

100

190

440/5.5

18

80

160

495/5.5

26

80

160

495/5.5

MSM514102-1O

20

100

190

440/5.5

MSM514400-80

20

80

160

495/5.5

26

80

160

495/5.5

20

100

190

440/5.5

MSM514102-80
MSM514102-8A

MSM514400-8A

4M

4M

Dynamic

Dynamic

4.194.304xl

1.048.576x4

MSM514400-10
MSM514402-80
MSM514402-8A
MSM514402-1O

6

80
100

26
20

MSM514258A-1A

468/5.5

70

MSM514258A-8A

Power
Con sumpPower
tion
Supply
MAX
Voltage
(mw)
(V)
Operating 1
Standby

140

20

MSM514258A-80

Cycle
Time
MIN
(ns)

4M

Dynamic

1.048.576x4

20

80

160

495/5.5

26

80

160

495/5.5

20

100

190

440/5.5

+5

+5

+5

+5

+5

Equivalent
Device

- - - - - - - - - . I C MEMORY LINE-UP AND TYPICAL CHARACTERISTICS.

• SIP/SIMM MODULE

Model Name

Memory
Capacity

Circuit
Function

2M

Socket
Insertable
Module

Memory
Configuration

Number of Access
Time
Pins
per
MAX
(ns)
Package

MSC2304-10
YS8/KS8
MSC2304-12
YS8/KS8

262,144x8

30

MSC2304-15
YS8/KS8
MSC2304-10
YS9/KS9
MSC2304-12
YS9/KS9

2M

MSC2304-15
YS9/KS9

Socket
Insertable
Module

262,144x8

30

MSC2307-10
YS9/KS9
MSC2307-12
YS9/KS9

2M

MSC2307-15
YS9/KS9

Socket
Insertable
Module

262,144x8

30

Cycle
Time
MIN
(ns)

Power
ConsumpPower
tion
Supply
MAX
Voltage
(mw)
(V)
Operating 1
Standby

100

200

26401220

120

220

24201220

150

260

22001220

100

200

29701248

120

220

27231248

150

260

24751248

100

200

29701248

120

220

27231248

150

260

24751248

80

160

3713/49.5

100

190

3218/49.5

80

160

3713/49.5

100

190

3218/49.5

80

160

3300/44.0

100

190

2860/44

80

160

3300/44

MSC2313A-l A

100

190

2860/44

MSC2320A-80

80

160

4410/99

MSC2312A-80
MSC2312A-l0
MSC2312A-8A

9M

Socket
Insertable
Module

1,048,576x9

30

MSC2312A-1A

Equivalent
DeviG.e

+5

+5

+5

+5

~-

MSC2313A-80
MSC2313A-l0
MSC2313A-8A

8M

Socket
Insertable
Module

Socket
Insertable
Module

1,048,576x8

30

100

190

3780/99

80

160

4410/99

MSC2320A-l A

100

190

3780/99

MSC2321A-80

80

160

4568/198

MSC2320A-l0
MSC2320A-8A

MSC2321 A- 10
MSC2321A-8A

8M

16M

Socket
Insertable
Module

262,144x36

524,288x36

72

72

100

190

3938/198

80

160

4568/198
3938/198

MSC2321 A-l A

100

190

MSC2328A-80

80

160

825/198

100

190

715/198

80

160

825/198

100

190

715/198

80

160

4455/49.5

80

160

4455/49.5

100

190

3960/49.5

MSC2328A-l0
MSC2328A-8A

2M

Socket
Insertable
Module

262,144x8

30

MSC2328A-l A
MSC2340-80
YS9/KS9
MSC2340-8A
YS9/KS9
MSC2340-10
YS9/KS9

4M

Socket
Insertable
Module

4,194,304x9

30

+5

+5

+5

+5

+5

7

II

.IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS ...- - - - - - - -

• CMOS STATIC RAMS

Model Name

Memory
Capacity

Circuit
Function

Memory
Configuration

64k

Fully Static
Common
I/O

8,192x8

Fully Static
Common
I/O

16,384x4

MSM5165AL-10
MSM5165AL-12
MSM5165AL-15
MSM5188-45
MSM5188-55

64k

MSM5188-70
MSM51257L-85
MSM51257L-100
MSM51257L-120
MSM51257AL-85
MSM51257AL-100
MSM51257AL-120
MSM51257ALL-85
MSM51257ALL-100
MSM51257ALL-120
MSM51256-10
MSM51256-120

Fully Static
256k Common
I/O

32,768x8

Fully Static
256k Common
I/O

32,768x8

Fully Static
256k Common
I/O

32,768x8

Fully Static
256k Common
I/O

32,768x8

Numberof Access
Pins
Time
MAX
per
PackIns)
age

28

22

28

28

28

28

Cycle
Time
MIN
Ins)

Power
Consump- Power
tion
Supply
MAX
Voltage
(mw)
(V)
Operating/
Standby

100

100

230/0.55

120

120

303/0.55

150

150

375/0.55

45

45

605/11

55

55

605/11

70

70

605/11

85

85

440/0.55

100

100

385/0.55

120

120

385/0.55

85

85

440/0.55

100

100

385/0.55

120

120

385/0.55

85

85

440/0.11

100

100

385/0.11

120

120

385/0.11

100

100

385/0.0055

120

120

385/0.0055

Equivalent
Device

+5

+5

+5

+5

+5

+5

• MASK ROMS

Model Name

MSM3864

Memory
Capacity

Circuit
Function

Memory
Configuration

Number of Access
Pins
Time
per
MAX
Ins)
Package

Cycle
Time
MIN
Ins)

Power
Con sump- Power
tion
Supply
MAX
Voltage
(mw)
(V)
Operating/
Standby

64k

Fully Static

8,192x8

28

250

250

550/165

+5

MSM38128A

128k

Fully Static

16,384x8

28

250

250

550/165

+5

MSM38256

256k

Fully Static

32,768x8

28

250

250

660/165

+5

MSM38256A

256k

Fully Static

32,768x8

28

150

150

330/33

+5

MSM53256

256k

Fully Static

32,768x8

28

150

150

83/0.55

+5

1M

Fully Static

131,072x8

28

250

250

83/0.55

+5

MSM531001

1M

Fully Static

131,072x8

32

120

120

110/0.28

+5

MSM534000

4M

Fully Static

262,144x16

40

200

200

275/0.55

+5

MSM534000A

4M

Fully Static

262,144x16

40

150

150

274/0.28

+5

MSM534001A

4M

Fully Static

524,288x8

32

150

150

275/0.28

+5

MSM534002A

4M

Fully Static

262,144x16

40

150

150

275/0.28

+5

MSM531000

8

Equivalent
Device

- - - - - - - -.... IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS.
• EPROMS

Model Name

Memory
Capacity

Circuit
Function

Memory
Configuration

Number of Access
Pins
Time
MAX
per
(ns)
Package

Cycle
TIme
MIN
(ns)

Power
Consump- Power
tion
Supply Equivalent
MAX
Voltage
Device
(mw)
(V)
Operatingl
Standby

64k

EPROM

8,192x8

28

120

120

525/184

+5

276A

128k

EPROM

16,384x8

28

120

120

525/184

+5

27128A

MSM27256

256k

EPROM

32,768x8

28

150

150

525/184

+5

27256

MSM27512

512k

EPROM

65,536x8

28

150

150

525/184

+5

27512

1M

EPROM

131,072x8

32

120

120

525/184

+5

27010

MSM271024

1M

EPROM

65,536x16

40

120

120

630/184

+5

27210

MSM27C256

256k

EPROM

32,768x8

28

100

100

165/0.55

+5

27C256

MSM27C256H

256K

EPROM

32,768x8

28

55

55

525/184

+5

27HC256

MSM27Cl024

1M

EPROM

65,536x16

40

100

100

175/0.55

+5

27C210

100

100

385/28

2M

EPROMS

262,144x8

32

120

120

385/28

+5

27C020

MSM27C2000-15

150

150

385/28

MSM27C2048-10

100

100

550/28

120

120

550/28

+5

27C220

150

150

550/28

MSM2764A
MSM27128A

MSM271000

MSM27C2000-10
MSM27C2000-12

MSM27C2048-12

2M

EPROMS

131,072x6

40

MSM27C2048-15
MSM2764AZB

64k

EPROMS

8,192x8

28

150

150

525/184

+5

P2764A

MSM27128AZB

128k

EPROMS

16,984x8

28

150

150

525/184

+5

P27128A

MSM27256

256k

EPROMS

32,768x8

28

170

170

525/184

+5

P27256A

MSM27512ZB

512k

EPROMS

65,536x8

28

200

200

525/184

P27512

150

525/184

+5

150
MSM271000~B

1M

EPROMS

131,072x8

32

150

150

525/184

+5

P27010

MSM271024ZB

1M

EPROMS

65,536x16

40

170

170

63Ox184

+5

P2721 0

256k

EPROMS

32,768x8

28

70

70

525x184

+5

MSM27C256HZB

9

II

D

.IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS . - - - - - - - - -

Number of Access
Pins
Time
per
MAX
(ns)
Package

Circuit
Function

Memory
Configuration

MSM16811

lk

E2PROM

64x16 or
128x8

8

*250

**1.0

16.5/0.55

+5

CAT93C46

MSM16811P

lk

E2PROM

64x16 or
128x8

8

*250

**1.0

16.5/0.55

+5

CAT93C46I

MSM16911

lk

E2PROM

64x16 or
128x8

8

*250

**1.0

16.5/0.55

+5

CAT59Cll

MSM16911P

lk

E'PROM

64x16 or
128x8

8

*250

**1.0

16.5/0.55

+5

CAT59Clli

MSM16812

2k

E2PROM

128x160r
256x8

8

*1000

**0.25

16.5/0.55

+5

CAT35Cl02

MSM16912

2k

E2PROM

128x16 or
256x8

8

*1000

**0.25

16.5/0.55

+5

CAT35C202

150

150

165/0.55

16k

E2PROM

2,048x8

24

200

200

165/0.55

+5

X2816A

64k

E2PROM

8,192x8

28

+5

X28C64A

256k

E'PROM

32x8

28

Model Name

MSM28C16A-15
MSM28C16A-20
MSM28C64A- 15
MSM28C64A-20
MSM28C256

Cycle
Time
MIN
(ns)

Power
Consump- Power
tion
Supply
MAX
Voltage
(mw)
(V)
Operating/
Standby

Memory
Capacity

150

150

165/0.55

200

200

165/0.55

200

200

165/0.55

Equivalent
Device

+5

*: Clock Frequency MAX (kH)
**: Clock Pulse MIN (!ls)

• ASMP
I)

Model Name

Memory
Capacity

Circuit
Function

Memory
Configuration

40k

ASMP

5,048x8

Number of Access
Time
Pins
per
MAX
Pack(ns)
age

MSM514212-28
MSM514212-34

28

MSM514212-50
MSM514221-3
MSM514221-6

1M

ASMP

262,263x4

16

1M

ASMP

262,144x4

28

MSM514252-10
MSM514252-12
MSM51C262-80
MSM51C262-10

256k

ASMP

65,536x4

24

MSM51 C262-12
MSM514201

10

1M

ASMP

1,048,576xl

18

Cycle
Time
MIN
(ns)

Power
Consump- Power
tion
Supply
MAX
Voltage
(mw)
(V)
Operating/
Standby

28

28

600128

34

34

600128

50

50

600128

25

30

275128

30

60

275128

100

190

660128

120

220

550128

80

145

660/44

100

175

550/44

120

205

468/44

3000

4000

28/0.5

+5

+5

+5

+5

+4.5

Equivalent
Device

MOS MEMORY
HANDLING
PRECAUTIONS

(I

II

MOS MEMORY HANDLING PRECAUTIONS
1. STATIC ELECTRICITY COUNTER·
MEASURES
Since voltage is generally controlled by means of the
transistor gate oxide film in MOS memories, the input
impedance is high and the insulation tends to be destroyed more readily by static electricity.
Although Oki MOS memories incorporate built-in
protector circuits to protect all input terminals from
such destruction, it is not considered possible to give

complete protection against heat destruction due to
overcurrents and insulation film destruction due to
irregular high voltages. It is, therefore, necessary to
observe the following precautionary measures.
1) Under no circumstances must voltages or currents
in excess of the specified ratings be applied to any
input terminal.
2) Always use an electrically conductive mat or shipping tubes for storage and transporting purposes.
3) Avoid wearing apparel made of synthetic fiber
during operations. The wearing of cottons which do
not readily generate static electricity is desirable.
Also avoid handling devices with bare hands. If
handling with bare hands cannot be avoided, make
sure that the body is grounded, and that a 1Mn
resistor is always connected between the body and
ground in order to prevent the generation of static
electricity.
4) Maintaining the relative humidity in the operation
room at 50% helps to prevent static electricity.
This should be remembered especially during dry

(1) Avoid

excessive undershooting when using an
address common bus for memory board RAMs and
ROMs.
(2) Since noise can be generated very easily when using
direct drive for applying memory board RAM
addresses from other driver boards, it is highly
recommended that these addresses be first received
by buffer.
(3) Methods available for eliminating undershooting
generated in the address line include
a) Clamping of the undershooting by including a
diode.
b) Connect 10-20n in series with driver outputs.
c) Smooth the rising edge and falling edge waveforms.

3. CMOS MEMORY OPERATING
PRECAUTIONS
3.1

Latch-Up

If the CMOS memory input signal level exceeds the
Vcc power line voltage by +0.3 V, or drops below the
ground potential by -0.3 V, the latch-up mechanism
may be activated. And once th is latch-Up mode has
been activated, the memory power has to be switched
off before normal operating mode can be restored.
Destruction of the memory element is also possible if
the power is not switched off.
Although Oki CMOS memories have been designed
to counter these tendencies, it is still recommended that
input signal overshooting and undershooting by avoided.

seasons.
5) When using a soldering iron, the iron should be
grounded from the tip. And as far as possible, use
low power soldering irons 112 V Or 24 V irons!.

2. POWER SUPPLY AND INPUT SIGNAL
NOISE
2.1

Power supply noise absorption

In dynamic memories, the flow of power supply
current differs greatly between accessing and standby
modes.
Although very little power is consumed by CMOS
memories during standby mode, considerable current
is drawn for charging and discharging linstantaneous
current requirements) during access mode. I n order to
absorb the "spike noise" generated by these current
requirements, the use of relatively large capacitance
capacitors (about one 1O"F capacitor for every 8 to
10 RAMs) is recommended along with good high frequency response capacitors of about 0.1"F for each
memory element. Power line wiring with as little line
impedance as possible is also desirable.
2.2

Input signal noise absorption

Overshooting and undershooting of the input signal
should be kept to a bare minimum. Undershooting in
particular can result in loss of cell data stability within
the memory. For this reason,

3.2

Battery Back-Up

Take special note of the following 4 points when
design ing battery back-up systems.
11) Do not permit the input signal H level to exceed
Vcc +0.3 V when the memory Vcc power is dropped.
To achieve this, it is recommended that a CMOS
driver using a Vcc power common with the CMOS
memory, or an open collector buffer Or open drain
buffer pulled-up by a Vcc power common with the'
CMOS memory be used for driving purposes.
(2) Set the chip select input signal CE to the same H
level as the CMOS memory Vcc power line. And in
order to minimize memory power consumption, set
the write enable input WE level, the aJdress input
and the data input to either ground level or to the
same H level as the CMOS memory Vee power line.
(3) Make sure that the CMOS memory Vee power line is
increased without "ringing" or temporary breaks
when restoring the battery back-up mode.
(4) When using synchronous type CMOS memories
(MSM5115, MSM5104), make sure that accessing
occurs after elapse of the chip enable off time (t cc )
prescribed in the catalog after the Vcc power line
has reached the guaranteed operating voltage range.
For further details, refer to "CMOS Memory Battery
Back-up" at the end of this manual.

MASKROM II
CUSTOMER PROGRAM
SPECIFICATIONS

13

II

MASK ROM CUSTOMER PROGRAM
SPECIFICATIONS
The mask ROM custom program code
programming method is outlined below.
1. USABLE MEDIA
(1) Magnetic tape
(2) EPROM
Magnetic tape and EPROM are used as standard.

2. MAGNETIC TAPE SPECIFICATIONS
2.1 Use the following types of magnetic tape in magnetic tape units compatible with IBM magnetic tape
units.
(1 ) Length:
2400 feet, 1200 feet or 600 feet
(2) No label
(3) Width:
1/2 feet
(4) Channels: 9 channels
(5) Bit density:800BPI standard, although 1600BPI
can also be employed.
(6) Block size: Integer multiples of 256 bytes
possible with 256 bytes as standard.
1 block, 1 record is standard.

2.2

Magnetic tape format
The data for a single chip should not extend into
several tapes. Data for several chips are allowed to be
included in a single magnetic tape, multiple file format
being permitted. In this case, include the data of a
single chip in one file.
(2) Use tape marks for file partitions when employing
multiple file formats.
(3) Denote the completion of a magnetic tape file by
(1)

two successive tape marks.
2.3

Magnetic tape data format
The data contained in a single file on magnetic tape
must be inserted from the head address (OOOO)hex of
the device up to the final address in succession for a
single chip.
(2) In this case, the LSB of the data should correspond
to Do, and the MSB to 0,.
(3) "1" bits in the data denote high device output,
while "0" denotes low output.
(1)

2.4 Magnetic tape examples

Multi-file format (m chips)

B

0

*

1-chip data file 1

T

,;",

I

*:

((- - H

- - - -

/

I

Block 1

I
R
G

Block 2

I
R
G

Block 3

I
R
G

(~

I
R
G

tape mark

File m

H-I I~ I

--- - --Block n-1

I
R
G

Block n

II

• MASK ROM CUSTOMER PROGRAM SPECIFICATIONS . - - - - - - - - -

3. EPROM SPECIFICATIONS
(1)

(2)

MSM2764A. MSM27128A. MSM27256 or Intel
2764A. 27128A. 27256 equivalent device may be
used.
Prepare 2 EPROMs containing identical data.

MASKROM
DEVELOPMENT
FLOWCHART

(I

17

11

MASK ROM DEVELOPMENT FLOWCHART

Mask ROM

User's
ROM data

automatic
designing program

ROM data
check list

I"~,,,,;o,~>y_e_s

_ _ _ _--,-_ _ _ _ _ _ _ _ _ _

- ,~

I

I

Mask ROM
manufacture

I
I

I
I
I
I

Engineering
Test
sampling

I
I

sample
:
shipment TAT' I

r - - - - - - - - - - - - - - - - - - - - - - - - - - -_._- - - -

,,
,

I' .. m;,,,;o,

--N-0Y~

---- ----------,-_-_-_-_-_-_- "'- __- ,
Mass
production

I

Shipment

Production
I
shipment
I
TAT'
I

I

¢==J c)
User

'TURN-AROUND-TiME

Oki Electric

[I

II

TERMINOLOGY III

AND SYMBOLS

21

II

TERMINOLOGY AND SYMBOLS
1. PIN TERMINOLOGY
Term

Power Supply Voltage Pin

Address Input Pin

EPROM

Mask ROM

Vee, Vpp

VCC

Ao~A16

Ao - A17

EEPROM

OO~O15

Ao~A12

Do - DIS
I/OO~

Data Input/Output Pin

vce

Vee

Data Input Pin

Data Output Pin

Static RAM

1/07

Chip Enable Pin

CE

CE

eE

Output Enable Pin

OE

OE

OE

Ao .....

A14

Dynamic RAM

vDD, VCC

Ao -A lO

01

DIN,D9

DO

DOUT,09

I/O, - 1/0,

DOl~D08

CEI, CE 2

-

OE

-

OE

Address Enable Pin

-

CS

Chip Select Pin

CS

WE

Write Enable Pin

WE

WE

Row Address Strobe Pin

RAS

Column Address Strobe Pin

CAS

Program Enable Pin

PGM, Vpp

Data Valid Pin

Clock Input Pin

Ground Pin

VSS

VSS

VSS

Vacant Terminal

NC

NC

NC

VSS

VSS

II

• TERMINOLOGY AND SYMBOLS

.1----------------_

2. ABSOLUTE MAXIMUM RATINGS
Term

EPROM

Mask ROM

EEPROM

Static RAM

Dynamic RAM

Vee, Vpp

Vee

Vee

Vee

VDD, Vee

VSS

VSS

VSS

VSS

VSS

VT

VT

Power supply voltage

Terminal voltage

VT

Input voltage

VI

VI

VI

VI

VI

Output voltage

Vo

Vo

Va

Vo

Vo

Input current

Output current

10

Output short circuit current

lOS

Load capacitance

Power dissipation

Po

Po

PD

Po

Po

Operating temperature

Topr

Topr

Topr

Topr

Topr

Storage temperature

Tstg

Tstg

Tstg

Tstg

Tstg

- - - - - - - - - - - - - - - - - . TERMINOLOGY AND SYMBOLS.
3. RECOMMENDED OPERATION CONDITIONS
Term

EPROM

Vee,

vpp

Mask ROM

EEPROM

Static RAM

Vee

vcc

vcc

Vss

VSS

Vss

Power Supply Voltage

Dynamic RAM

VDD,VCC
VBB

VSS

"H" Clock Input Voltage

Vss

VIHC

"H" Input Voltage

VIH

VIH

VIH

VIH

VIH

"L" Input Voltage

VIL

VIL

VIL

VIL

VIL

Data Retention Voltage

Lead Capacitance

VCCH

CL

Fan-out

Operating Temperature

Topr

CL

CL

CL

N

N

N

Topr

Topr

Topr

Topr

25

II

• TERMINOLOGY AND SYMBOLS ••- - - - - - - - - - - - - - - - 4. DC CHARACTERISTICS
Term

EPROM

Mask ROM

EEPROM

Static RAM

Dynamic RAM

"H" output voltage

VOH

VOH

VOH

VOH

VOH

"L" output voltage

VOL

VOL

VOL

VOL

VOL

"H" output current

10H

IOH

IOH

10H

IOH

"L" output current

IOL

IOL

IOL

IOL

IOL

Input leakage current

III

III

III

III

III

Output leakage current

ILO

ILO

ILO

ILO

ILO

1/0 leak current

Program terminal current

ILO
IpP1. lpP2

Peak power on current

Power supply current

IpO

ICC·ICC1.

ICCA.ICCS

ICC2

ICCS1

ICCA.ICCS.

ICCS.ICCS1

IDD1. ICC1. IBB1

ICCS1

ICCA

IDD2. ICC2. IBB2
IDD3. ICC3. IBB3
IDD4. ICC4. IBB4

26

-----------------------------------.TERMINOLOGYANDSyMBOLS.
5. AC CHARACTERISTICS
(1) Read cycle
Term

EPROM

Read cycle ti me
Address access time

tACC

Chip select access time

Mask ROM

EEPROM

Static RAM

tc

tRC

tRC

tRC

tAA

tM

tAC

tAA

tco

tcs

Chip enable access time

tCE

tACE

tCE

tCD

Output enable access time

tOE

tco

tOE

tOE

Output setting time

tLZ

tLZ, tOLZ

Output valid time

tOH

tOH

tHZ

tHZ, tOHZ

Output disable time

tDF

Dynamic RAM

Address set-up time
Address hold time

tOEA

tcx, tox
tOHA
tOTD,tCTD

tOFF, tOEZ

tAS

tASR, tASC
tRAH,tCAH

Chip enable off time
Chip enable pulse width
Power-up time

tpu

Power-down time

tpD

Address enable pulse width
Data val id access ti me
Data valid delay time
Clock delay ti me
Clock pule width

tRAS' tCAS' twp

Clock delay time

tRCD' tRAD

Output delay time
Output access time
Output hold time
Address enable set-up time

27

III

II

• TERMINOLOGY AND SYMBOLS ••- - - - - - - - - - - - - - - - (2) Write Cycle
Term

EPROM

Write cycle time

EEPROM

Static RAM

twc

twc

tRC

Address set-up time

tAS

lAS

tAS

tASR,tASC

Write pulse width

tpwtOPW

twp,ICW

tw

twp

Write recovery time

tWR

Data set-up time

tos

tDS

tos

tos

Data hold time

tDH

tDH

tOH

tOH

Output oft-time

tDFP

tOTW

tOFF

Address hold time

tAH

tRAH' tCAH

tAH

Chip enable off time
Chip enable pulse width

tcw

Write enable set-up time

tcs

Write enable read time
Write enable hold time

tCH

Address/write enable setting time
Write enable output activation

28

Dynamic RAM

CE set-up time

tCES

tcs

OE set-up time

tOES

tOES

Data valid from OE

tOE

Vpp power set up time

tvs

Output enable hold time

tOEH

Data latch time

tDL

Data load time

tPL

PACKAGING II

D
o

PACKAGING ............................................................... 33
• 8 PIN PLASTIC DIP (DIP8-P-300) ............•..................•.............. 36
•

16 PIN PLASTIC DIP (DIP16-P-300, DIP16-P-300-W1) ........................... 36

•

18 PIN PLASTIC DIP (DIP18-P-300, DIP18-P-300-W1, DIP18-P-400) ............... 37

• 20 PIN PLASTIC DIP (DIP20-P-300-W1, DIP20-P-400) ........................... 38
•

22 PIN PLASTIC SKINNY DIP (DIP22-P-300-S1) ................................. 38

•

24 PIN PLASTIC DIP (DIP24-P-600) ............................................ 39

•

28 PIN PLASTIC DIP (DIP28-P-600) ............................................ 39

• 32 PIN PLASTIC DIP (DIP32-P-600) ............................................ 39
• 40 PIN PLASTIC DIP (DIP40-P-600) ............................................ 40
• 8PIN PLASTIC SOP (SOP8-P-250-K) .......................................... 41
•

28 PIN PLASTIC SOP (SOP28-P-430-K) ........................................ 41

• 60 PIN-V PLASTIC QFP (QFP60-P-1519-VK) .................................... 41
•

26 PIN PLASTIC SOJ (SOJ26-P-300, SOJ26-P-350) ........................•.... 42

•

18 PIN PLASTIC QFJ (PLCC) (QFJ 18-P-R290) ................................... 43

•

20 PIN PLASTIC ZIP (ZIP20-P-400, ZIP20-P-400-W1) ............................ 44

•

28 PIN PLASTIC ZIP (ZIP28-P-400) ................................•........... 44

•

28 PIN CERDIP (WDIP28-G-600) .............................................. 45

• 32 PIN CERDIP (WDIP32-G-600) .............................................. 45
• 40 PIN CERDIP (WDIP40-G-600) .............................................. 45
• 30 PIN SIMM (FOR MSC230412307YS9) ...................................... 46
• 30 PIN SIMP (FOR MSC230412307KS9) ..................................... ,. 46
• 30 PIN SIMM (FOR MSC2304YS8) ............................................ 47
• 30 PIN SIMP (FOR MSC2304KS8) ............................................. 47
• 30 PIN SIMM (FOR MSC2305YS18A) .......................................... 48
• 30 PIN SIMM (FOR MSC2312AYS9) ....................................... " .. 49
• 30 PIN SIMP (FOR MSC2312AKS9) ........................................... 49
• 30 PIN SIMM (FOR MSC2313AYS8) ........................................... 50
• 30 PIN SIMP (FOR MSC2313AKS8) ........................................... 50

----------------------------------------------------------.PACKAGING.

PACKAGING
PACKAGES
RS
Name

PLASTIC
DIP/PLASTIC
SKINNY DIP

GS
PLASTIC SOP/
PLASTIC QFP

JS
QF) (PLCC)/
PLASTIC SO)

ZS

AS

KS/YS

PLASTIC DIP

CERDIP

MODULE

MSM3764A

DIP16-P-300

-

QFJ18-PR290

-

-

-

MSM41256A

DIP 16-P-300

-

QFJ18-PR290

-

-

-

MSM41257A

DIP16-P-300

QFJ18-PR290

MSM41464

DIP18-P-300
DIP16-P-300

-

-

MSM51C256
MSM511000A

DIP18-P300-W1

-

-

MSM511001A

SOJ26-P300

ZIP20-P-400

-

.

.

-

MSM511002A
DIP20-P300-W1

-

SOJ26-P300

ZIP20-P-400

-

-

DIP18-P-400

-

SOJ26-P350

ZIP20-P400-W1

-

-

DIP20-P-400

-

SOJ26-P350

ZIP20-P400-W1

-

-

-

-

-

-

-

30 PIN
SIMM/SIMP

-

-

-

-

-

30 PIN
SIMM/SIMP

-

-

-

-

-

72 PIN
SIMM

MSC2328A(2)

-

-

-

-

-

30PIN
SIMM/SIMP

MSC2340(9)

-

-

-

-

-

30PIN
SIMM/SIMP

MSM5165AL

DIP28-P-600

-

-

-

-

MSM5188

DIP22-P300-S1

-

-

-

-

MSM514256A
MSM514258A
MSM514100
MSM514102
MSM514400
MSM514402
MSC2304(8)
MSC2304(9)
MSC2307(9)
MSC2312A(9)
MSC2313A(8)
MSC2320A(9)
MSC2321 A( 18)

SOP28-P430-K

-

30 PIN
SIMM/SIMP

fill

.PACKAGING.I-------------------------------------------------------PACKAGES
RS
Name

MSM51257L

PLASTIC
DIP/PLASTIC
SKINNY DIP

DIP28-P-600

MSM51257AL

GS
PLASTIC SOP/
PLASTIC QFP

SOP28-P430-K

ZS

AS

KS/YS

PLASTIC DIP

CERDIP

MODULE

-

-

-

-

JS
QFJ (PLCC)/
PLASTIC SOJ

MSM51257ALL
MSM51256
DIP28-P-600

-

-

-

-

-

MSM53256

DIP28-P-600

-

MSM531000

DIP28-P-600

MSM531001

DIP32-P-600

MSM534000

DIP40-P-600

-

-

-

-

-

-

-

-

-

WDIP28-G600

-

MSM271000

-

-

-

-

WDIP32-G600

-

MSM271024

-

-

-

DIP28-P-600

-

WDIP40-G600

MSM27C256

-

WDIP28-G600

-

MSM27Cl024

-

-

-

-

WDIP40-G600

-

MSM27C2000

-

-

-

-

WDIP32-G600

-

MSM27C2048

DIP28-P-600

-

-

WDIP40-G600

MSM2764AZB

-

-

MSM3864
MSM38128A
MSM38256
MSM38256A

QFP60-P1519-VK

MSM534000A
MSM534001A

DIP32-P-600

MSM534002A

DIP40-P-600

MSM2764A
MSM27128A
MSM27256
MSM27512

MSM27C256H

MSM27128AZB
MSM27256ZB
MSM27512ZB

-

----------------------------------------------------------.PACKAGING.
PACKAGES
RS

Name

PLASTIC
DIPiPLASTIC
SKINNY DIP

GS
PLASTIC SOPI
PLASTIC QFP

JS
QFJ (PLCC)I
PLASTIC SOJ

ZS

AS

KS/YS

PLASTIC DIP

CERDIP

MODULE

-

-

-

-

-

DIP8-P-300

SOP8-P-250K

-

-

-

-

DIP8-P-300

8PIN
PLASTIC
SOP*

-

-

-

-

-

-

24PIN
*
PLASTIC ZIP

-

-

-

-

-

MSM271000ZB

DIP32-P-600

MSM271024ZB

DIP40-P-600

MSM27C256ZB

DIP28-P-600

fI

MSM27C256
HZB
MSM16811
MSM16811P
MSM16911
MSM16911P
MSM16812
MsM16912
MSM28C16A

DIP24-P-600

MSM28C64A

DIP28-P-600

MM28C256

DIP28-P-600

SOP28-P430-K

SOJ26-P300

MsM51C262

-

-

MsM514201

-

-

QFJ 18-PR290

MSM514212
MSM514221
MSM514252

DIP16-P300-W1

-

ZIP28-P-400
ZIP20-P-400
ZIP28-P-400

33

.PACKAGING.I--------------------------------------------------------

PLASTIC DIP
8 PIN PLASTIC DIP
DIP18-P-300

~~

®

~]

JWr=;llo

/Q~~0
/.ndOX Mark
6.70±O.30
1.012±O,10

1 524.±O.10

i.l

J J '"

1-1 u::
\,

Seating Plana /

~

i'

O.50±O.'O~

16 PIN PLASTIC DIP
DIP16-P-300

@

®

pf)

0

]

/cDLJ=~ ~
/.ndax-Mark
19.10±{).30

16 PIN PLASTIC DIP
@

DIP16-P-300-W1

®

Po
LCD

]

0
®

Indax Mark

19.10:tO.30
O.992±O,10

E1

1.27±O,10

1:'·

DtDDDtD ; ~I
V vT~ 1 i' ~

o~L ~5 ~50".':
\

34

I5

®

Seating Plana

62U

~ff

ol

0-15.

• PACKAGING.

PLASTIC DIP
18 PIN PLASTIC DIP
@

DIP18-P-300

fI

@

I

0
®
Index Mark
22. BO±(). 30

,.

1:,62U I

~r:l

1. 14TY?

18 PIN PLASTIC DIP
@

DIP18-P-300-W1

@

0
(i)

®

J

Index Mark
22. 60±Q. 30

1,',62U I

i(l

~~

1,14TYP

18 PIN PLASTIC DIP

@

@

DIP18-P-400

0
®

(i)

J

Index Mark
22. 60:tG, 30

i(l

ill

1.14TYP

,.
~

.;

..;

"'

'(

r:1

~n
35

• PACKAGING

.1----------------------_

PLASTIC DIP
20 PIN PLASTIC DIP
@

DIP20-P-300-W1

/0
/lndaxMark
24.40tO.30
O.BB5±010

El

~

1.27±O.10

1:762~'30 I

J[ J JDDDDD,lii

~ VV~ ~.~~i'

'"

0.762'YP _I

1 1,.54±0.25

~+-- ~

4+1 0~'50=~.!.'Cj1O1M" ~ ®~

i02S ?fJ.,S
~S

Seating PIa..

20 PIN PLASTIC DIP

@

DIP20-P-400

°1

f?p

/J50=cr=o=n=r=;=;~~@
/l'ndax Mark
24.. 4OtO. 30

·111.27~.1O

O.a8S±O.10

J[ ]

t~~

JDDDDD

~ ~

o~_~n~~l~~

Seating PIa ..

22 PIN PLASTIC SKINNY DIP

@

DIP22-P-300-S 1

@

i:::::::~JI
26. 9O±O. 30
1.119±O.10

1.27±O,lQ

::J

t

::J

0 Dt

~ ~~~® ;1

O.50±O.10

•. 25

M

Seating Plano

36

0-15'

---------.PACKAGING.

PLASTIC DIP
24 PIN PLASTIC DIP
DIP24-P-600

28 PIN PLASTIC DIP

I-----DIP28-P-600----l

®

@

CD

@

~~ ~~ ~ ~ ~ ~ ~ ~ ~~]

I

32 PIN PLASTIC DIP
DIP32-P-600

@

@

~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ]1
41.7QjO.30

~~~~I ~.
~~
...... 10

,,.
t.

"~

Seati

".2~.~ I
~
I

!~.~-P.1$

~

Jl0-15"

Plane

37

_PACKAGING _ _- - - - - - -

PLASTIC DIP

IJ

40 PIN PLASTIC DIP
DIP40-P-600

e~ ~ ~~~ ~ ~ ~ ~ ~~ ~ ~:~~ ~ ~ ~jJ
52.~.3D

Seating Plane

38

--------------------------------------------------------.PACKAGING.

PLASTIC SOP/QFP
8 PIN PLASTIC SOP

EI

.00±O.30

SOP8-P-250-K

,
O.35:t{l.10~~~

28 PIN PLASTIC SOP
lB.50±O.30

SOP28-P-430-K

Index Mark
0.UJ'0.10

iGl

0.25

®

il

~ :fi 1??
"'21
~3

SelltingPla...

CI"IiIiIi"Ii~Ii)~~ ~~~O-IO'
c

0.30

~'!:I

??I

~:

O. 8S±O. 20_

60 PIN-V PLASTIC QFP
QFP60-P-1519-VK

Vent Hole

39

.PACKAGING.~-------------------------------------------------------

PLASTIC SOJ
26 PIN PLASTIC SOJ
SOJ26-P-300

17. 15±0.20

@

@

@

Index Mark

Seating Plane

26 PIN PLASTIC SOJ
SOJ26-P-350

Index Mark

Seating Plane

40

1$10.18 ®I

• PACKAGING.

PLASTIC QF
18 PIN PLCC

J (P LC C)

QF J 18-P-R290

fI

Seating Plo...

41

.PACKAGING.,--------------------------------________________________

PLASTIC ZIP
20 PIN PLASTIC ZIP
ZIP20-P-400

25.50<0.30

o
o
+0.15
0.25+0.05

~
g

:
g

..;

2.~ 30

20 PIN PLASTIC ZIP
ZIP20-P-400-Wl

2.80<0 25

25.50<0.30

"I

~

0
0
@)

~

0

g
..;

2. 4±0 30

Plane

28 PIN PLASTIC ZIP
ZIP28-P-400

I'

36.00<0.30

"I

o
~

g

+0.15
0.25+0.05

Plane

42

2.~

~

0'

g
..;

30

------------.PACKAGING.

CERDIP
28 PIN CERDIP
WDIP28-G-600

fI

32 PIN CERDIP
WDIP32-G-600

40 PIN CERDIP
WDIP40-G-600

53.5OI1AX

I

15.24:*0.30

43

.PACKAGING.--------------------------------------------------------

MODULE SIMM/SIMP
30 PIN SIMM (FOR MSC2304/2307YS(9)
88.9
82.14

3.38

z

i

00 ....

N"'!
N""
fl-t{).15

1.271-000

Chip capacitor

(UNIT: mm)

30 PIN SIMM (FOR MSC2304/2307KS(9)
88.9
3.38

82.14

000JJ030
Glass epoxy board'

=-=--l·II-· 22!.WSeating Plane

tr

.AX

~~
II

-II- 0.27

+0.1 3

-0.0 7

18·lead PlCC

Chip capacitor

(UNIT: mm)

44

-----------------------------------------------------------PACKAGING_

MODULE SIMM/SIMP
30 PIN SIMM (FOR MSC2304YS(8)

88.9
3.38

82.14

5.08 MAX

OOOJJ
1.27±O.13

GtasswEpoxy Board

18 pin PLCC

Chip capacitor

(UNIT: mm)

30 PIN SIMP (FOR MSC2304KS(8)
88.9
3.3..::8---j.-t-_ _ _ _ _ _..:8:.:,2.:..:.l.,;.4_ _ _ _ _ _--i

5.08~IAX

CD

.-

o~L4~~~~~~~~~~~~~~~
Glass-Epoxy Board
l8pin PLCC
Chip Capacitor

(UNIT: mm)

45

.PACKAGING.I---------------------------------------------------

MODULE SIMM/SIMP
30 PIN SIMM (FOR MSC2305YS18A

cor-: =3=.=38:; : : : : : _~=a_2'-'-·._9.:. . 1_4~-_-_-_-_-_-_-_--__-,,",\~3.,,~i~~MAX ~r
"'::n
.......

-'"

~

;h

....

N

.

-\OQ~

.

........ \0

73.66

1.78

Jl

+015
1.27 -0:08-

.59

Glass-Epoxy Board
18 pin PLCC
Chip Capacitor

(UNIT:mm)

46

----------------------------------------------------------.PACKAGING.

MODULE SIMM/SIMP
30 PIN SIMM (FOR MSC2312AYS9)

fI

(UNIT: mml

889
82.14

3.38

o
N

~1~f11 O~O
2.03
5.59

0

I I II

~ ~OOOOOO~OO
0

2.54

II

1.78
73.66

5.28 MAX.

p
o
o

o

0

I

'"
N

~

.11 1.27~g:6~

N

Glass-Epoxy substrate

26 pin
Chip Capacitor

30 PIN SIMP (FOR MSC2312AKS9)

(UNIT: mml

88.9
82.14

3.38

5.28 MAX

~

~

73.65

Glass-Epoxy substrate

26 pin SOJ
Chip Capacitor

0.27~:6~
SEATING
PLANE

47

_PACKAGING ______________________________________________________

MODULE SIMM/SIMP

I

30 PIN SIMM (FOR MSC2313AYS8)
88.9

(UNIT: mm)

3.38 ~----------~8=2.~14~----------~
1.45 MIN

n

5.28 MAX

r-

~'l ~u~~raoru@~M1lDi5.ffilC~~"C~
iJ1iGO~~~~Wn~~
-=

cf±:::::2X
14>3.18

~

1.78

7.62

JL

~
~

2.54
2.54 x 29 = 73.66 (BOTH SlOES)

00
~

Jt27~:~~

N

R

~

___ Glass·Epoxy substrate

___ 26 pin SOJ
-

_ _ Chip Capacitor

I

30 PIN SIMP (FOR MSC2313AKS8)

c--

IUN",

I

I

V
r

~JL

O.27~:~~
Glass·Epoxy substrate

.,--26 pin
VChiP Capacitor

48

n

5.28 MAX

78.74

~I

--------------------------------------------------------_PACKAGING_

MODULE SIMM/SIMP
30 PIN SIMM (FOR MSC2331 AYS3 OR MSC2329AYS3)
88.90±0.15

3.38.0. ,5

A1.SO/

II
11--'

82.14±0.13
_~---I'

IT

~~

I
g_ I--

2.54:t0.10 - lI I~

7.62:tO.15

I

5.25 MAX

J

I

fII

o
II

.0.10

-II-- 1.27 +0.08

2.54 X 29 .. 73.14±0.13 (Both Sides)

2.03±0.15

~

1.78.0.10

H

~

a

~
C'J

LDDDn
t
Note:
1) Substrate: Glass-Epoxy (FR-4)
2) Chip Capacitor: Under Component (0.22 x3pcs)

3) Contact Finish: 2.S4um Min PS/Sn Over 1.9um Min Ni
4) Contacts are on both sides of PC Board
5) Thickness includes plating

I

30 PIN SIMM (FOR MSC2328AXXYS2)

3.38.0.15

~I

':!

..~~

11"""'1 11"""'1 ~ ~ ~ ~

':!

~I t:;,~
cD
%"

A1.SO/

I

88.90±0.15

82.14±0.13
I--_~---I'

~

~

~

l1..--L
~_ ~ L'

mm

G~

lnnnnnnnnilnnnnnrln30

0nnnr

2.54'0.'0~ ~

7.62±O.,5

05.25 MAX
/,,3.18±O.13

I

J
II

.0.10

- I I - 1.27 +0.08

2.54X29.73.14.0.13 (Bo1hSides)

2.03±0.15

i
U)

1.78±O.10

~

HaN

LDDDn
t
Note:

1) Substrate: Glass-Epoxy (FA-4)
2) Chip Capacitor: Under Component (0.22 x2pcs)
3) Contact Finish: 2.54urn Min PBlSn Over I.gum Min Ni
4) Contacts are on both sides of PC Board

5) Thickness includes plating

49

-PACKAGING __- - - - - - - - - - - - - - - - - - -

MODULE SIMM/SIMP

I

72 PIN SIMM (FOR MSC2320AYS9)

107.95

I'

,

101.19

110

~Io

~~T 1 110

110

~

l(l

2.03~

y,

~I

~I=

~I

50

1.5MIN_

~0

.1=_0

A157iJ
6.35

95.25

+ ~i]

.1

I-- 0.2 MIN

.....

110

V

2-1213.18

,.t

c=J 0

~.-~

127--11_

-----------------.PACKAGING.

MODULE SIMM/SIMP
72 PIN SIMM (FOR MSC232 1AYS18)

I

UI

50-A

.PACKAGING ••--------------------------------------------------------

MODULE SIMM/SIMP
30 PIN SIMM (FOR MSC2340YS9)

MSC2340YS9

NOTE

1)

SUBSTRATE

GLASS EPOXY (FR-4)

2)

CONTACT PADS.

Pb/Sn or Au PLATING

3)

4M x 1 DRAM x9 pes

30 PIN SIMP (FOR MSC2340KS9)
MSC2340KS9

1 - 0 - - - - - - - - - 96.S2

--------..;

rS.28 MAX.

88.90
82.14

II
+01
2.S4 MIN ....,1---0.27 - 0.05

7.62

SEATING PLANE

1-0---------- 73.66 - - - . . ;
NOTE

50-8

1)

SUBSTRATE

GLASS EPOXY (FR-4)

2)

CONTACT LEAD .

Pb I Sn SOLDER

3)

SEATING PLANE (PAl 0.83, PITCH 2.S4)

4)

4M x 1 DRAM x 9 pes

RELIABILITY
INFORMATION

HI

11

D

RELIABILITY INFORMATION
1. INTRODUCTION ••••••••••••••.••••.•••••.•••••••••••••••••••• 53
2. QUALITY ASSURANCE SYSTEM AND UNDERLYING CONCEPTS •••••••••••• 53
3. EXAMPLE OF RELIABILITY TEST RESULTS ..••••••••••••••••••••••.•• 56
4. SEMICONDUCTOR MEMORY FAILURES •••••.•.••••••••••••••••••••• 64

RELIABILITY INFORMATION
1. INTRODUCTION
Semiconductor devices playa leading role in the
explosive progress of semiconductor technology.
They use some of the most advanced design and
manufacturing technology developed to date.
With greater integration, diversity and reliability,
their applications have expanded enormously.
Their use in large scale computers, control
equipment, calculators, electronic games and in
many other fields has increased at a fast rate.
A failure in electronic banking or telephone
switching equipment, for example, could have far
reaching effects and can cause incalculable
losses. So, the demand, for stable high quality
memory devices is strong.
We, at Oki are fully aware of this demand. So we
have adopted a comprehensive quality assurance system based on the concept of consistency in development, manufacturing and sales.
With the increasing demand for improvement in
function, capability and reliability, we will expand
our efforts in the future. Our quality assurance
system and the underlying concepts are outlined
briefy below.

2. QUALITY ASSURANCE SYSTEM
AND UNDERLYING CONCEPTS
The quality assurance system employed by Oki can
be divided into four major stages: device planning,
developmental prototype, production prototype, and
mass production. This system is outlined in the following block diagram (Fig. 1).
1) Device planning stage
To manufacture devices that meet market demands
and satisfy customer needs, we carefully consider
functional and failure rate requirements, utilization
form, environment and other conditions. Once we
determine the proper type, material and structure,
we check the design and manufacturing techniques,
and the line processing capacity. Then we prepare
the development planning and time schedule.
2) Developmental prototype stage
We determine circuits, pattern design, process
settings, assembly techniques and structural requirements during this stage. At the same time,
we carry out actual prototype reliability testing.
Since device quality is largely determined during
the designing stage, Oki pays careful attention
to quality confirmation during this stage.
This is how we do it:
(1) After completion of circuit deSign (or pattern
design), personnel from the design, process
technology, production technology, installation technology and reliability departments
get together for a thorough review to ensure

(2)

(3)

design quality and to anticipate problems
that may occur during mass production.
Past experience and know-how guide these
discussions.
Since many semiconductor memories involve new concepts and employ high level
manufacturing technology, the TEG evaluation test is often used during this stage.
Note: TEG (Test Element Group) refers to
the device group designed for stability evaluation of MOS transistors,
diodes, resistors, capaCitors and
other circuit component element
used in LSI memories.
Prototypes are subjected to repeated reliability and other special evaluation tests. In
addition, the stability and capacity of the
manufacturing process are checked.

3) Production prototype stage
During this stage, various tests check the reliability and other special features of the production
prototype at the mass production factory level.
After confirming the quality of a device, we prepare the various standards required for mass
production, and then start production. Although
reliability and other special tests performed on
the production prototype are much the same as
those performed on the developmental prototype,
the personnel, facilities and production site
differ for the two prototypes, neceSSitating
repeated confirmation tests.
4) Mass production
During the mass production stage, careful
management of purchased materials, parts and
facilities used during the manufacturing process,
measuring equipment, manufacturing conditions
and environment is necessary to ensure device
quality first stipulated during the designing
stages. The manufacturing process (including inspection of the completed device) is followed by
a lot guarantee inspection to check that the
specified quality is maintained under conditions
identical to those under which a customer would
actually use the device. This lot guarantee inspection is performed in three· different forms as
shown below.
(1)

Group A tests: appearance, labels, dimensions and electrical characteristics inspection
(2) Group 8 tests: check of durability under
thermal and mechanical environ m ental stresses, and
operating life characteristics
(3) Group C tests: performed periodically to
check operational life, etc.,
on a long term basis.
Note: Like the reliability tests, the group 8 tests
conform to the following standards.
MIL-STD-8838, JIS C 7022, EIAJ-IC-121

53

HI

!!
~

~ar1-

Process

Sales

ment

I

Acceptance
of order

Design

Purchasing
(Vendors)

Production
Control

Production Engineer

Inspectio~

Production

I

IH

r-

~

r-

Design Reviewand Tnal Product Review

1

Ilayou,

r~

I

"T1

.or

I

!;
CD

~

I

:rogram~

~I Production ~
Planning

OperatIOn
Standard

• I

Produc'ion

Process
Setup

I

t

~
~n~

1 Process

Z
"'II

. IProduc'ion
Process
Control

Control

o::zJ

r

3:
)00

I

-I

t:H

Inspection

p

2!.

J.~

I

Inspection

c

y

Product
Inspection

'... H

~

Quality
Testing

1

:::l

Shipment
Delivery
I

3

,.

~ ~ackaging

I

Transportation
Control

n

II

I

~

Service

...
----------

.

Storage
Control

iil

en
~CD

•

I

In-Proc~ss

c

~

o
Z

~ Acceptance

Purchasing
GUidelines

Inspection

iI

1

--'--

f-

Quality Assurance
& Quality Control
Statt Activities

.Quall'y and Rellabill',
Reliability
Engineering

•

::zJ

m

:;

Production

;+

Customer

....

& Quality
Standards

»

Maintenance
Service

Transportation

1 g~r~~rives

~I Technical

<

Storage

Marketing & Product Planning

l
Development

Design
Engineer

I

Quality Management and Education

,

~

Quality Control Program + Reliability Program
V

Information AnalysIs
-Quality Evaluation
-Failure AnalysIs

I

Quality Assurance
---

Failure

Report

AnalysIs

Service

I

r

t--

r r-

• RELIABILITY INFORMATION.

•

Acceptance Inspection
•
•

Production
Process
Wafer Process
&
Assembly

Electrical Test
Regular Check of Measuring
Equipment

•

Production Process Quality Control
Lot Control
Equipment Conditions
In-Process Inspection
4 Thermal Screening
5 Seal Test

I
CD

•

•
•
' -_ _ _,--_ _- - ' .

Group A Test
Group B Test
Group C Test

Early Removal of Defective Devices

Figure 2 Manufacturing Process

Devices which pass these lot guarantee inspections are stored in a warehouse awaiting shipment to customers. Standards are also set up for
handling, storage and transportation during this
period, thereby ensuring quality prior to delivery.
Figure 2 shows the manufacturing flow of the
completed device.

5) At Oki, all devices are subjected to thorough
quality checks. If, by chance, a failure does
occur after delivery to the customer, defective
devices are processed and the problem rectified
immediately to minimize the inconvenience to
the customer in accordance with the following
flowchart.

Request for
technical
Improvement

i-Re-;;;t-;;;--:
Failure report
delivery
Quality

Failure
report

Engineering
Department

results of
investigation
& improvement

Assurance
Department

Customer

I

Report on
results of
investigation

I
L _ ~ ~~r~v-=~e~t

Manufacturing
' - - - - - - - - - \ Department

Request for
manufacturing
improvement
Figure 3

Failure report process

55

• RELIABILITY INFORMATION . - - - - - - - - - - - - - - - - - -

Service
•

Failure Analysis
Customer I "formation Analysis

!t

use Quality

Target Quality

Quality Assurance

&
Quality Control

--

Quality and Reliability I "formation
Quality Evaluation

•

Defective Analysis

•

Reliability Engineering

•

Quality Management and Education

•

Operation Standard

•

Techn iear Standard

•

Quality Standard

•

Design Review

•

Prototype Review

3. EXAMPLE OF RELIABILITY TEST
RESULTS
We have outlined the quality assurance system
and the underlying concepts employed by Oki.
NoW, we will give a few examples of the reliability
tests performed during the developmental and
production prototype stages. All reliability tests
performed by Oki conform to the following standards.
MIL-STD-883B, JIS C 7022, EIAJ-IC-121
Since these reliability tests must determine performance under actual working conditions in a
short period of time, they are performed under
severe test conditions. For example, the 125°C
high temperature continuous operation test performed for 1000 hours is equivalent to testing
device life from 2 to 300 years of use at Ta =
40°C.
By repeating these accelerated reliability tests,
device quality is checked and defects analyzed.
The resulting information is extremely useful in
improving the manufacturing processes. Some
of the more common defects in LSl elements and
their analysis are described on next page.

56

Design Quality

- - - - - - - - - - - - - - - - - - - . RELIABILITY INFORMATION.
OKI MEMORY LSI LI FE TEST RESULTS

~

Device name
Function

MSM511000ARS
lMx 1 bit
DYNAMIC RAM

----

------

Structure
Test item

Operating
life test

Test condition

Pressure
cooker test

size

Test
hours

Failures

256K x 4 bit
DYNAMIC RAM

lMx 1 bit
DYNAMIC RAM

Si gate C-MOS
26PSOJ

Si gate C-MOS
20P ZIP

Sample
Site

Test

Sample

Failures

hours

size

Test
Failures
hours

100

2000

0

-

-

200

2000

0

200

2000

l'

Ta = 150°.V
Vcc = 7.0V

100

2000

0

100

2000

0

-

0

100

.._--- 1--

100

Vcc = 5.5V

120

0

100

120

120

0
I

"---

85°C 85%
Vcc = 5.5V

400

121°C 100%
No bias

50

2000

0

I

500

2000

- - \---- -

500

0

200

2000

1-----

0

50

500

0

50

500

-1l5°C - 25°C 150°C
(70min/cycle)

Device name

60

2000

0

22

2000

0

-

400

1000
cycles

0

300

1000
cycles

0

200

MSM41256ARS
--

Function

0
--

0

i
I--

I

1000
cycles

0

MSC2304KS

---

256K x 1 bit
DYNAMIC RAM
----

Structure

-

MSM2312YS9

I

1

e------ -

Low tempera· Ta = -10°C
ture life test
Vcc = 7.0V
Temperature
cycling test

Sample

MSM511000AZS

Ta=125°C
Vcc = 7.0V

130°C 85%
Temperature
humidity test

Si gate C-MOS
18P P-DIP

MSM514256AJS

1M x 9 bit
DYNAMIC RAM

256K x 9 bit
DYNAMIC RAM

Si gate C-MOS

Si gate N-MOS

------------\-

Si gate N-MOS
16P P-DIP

30P SIMM

30P SIP

--------

Test item

Operating
life test

Test condition

Pressure
cooker test

500

2000

Test
Failures
hours

ample

Test
hours Failures

,~r~
size

0

40

1000

0

0

--

Ta = 150°C
Vcc = 7.0V

45

4000

0

-

-

Vcc = 5.5V

100

120

0

-

-

85°C 85%
Vcc = 5.5V

300

2000

0

40

121°C 100%
No bias

100

500

0

60

2000

200

1000
cycles

Low tempera- Ta=-10°C
ture I ife test
Vcc = 7.0V
Temperature
cycling test

size

Test
Sample
Failures
hours
size

I

Ta = 125°C
Vcc = 7.0V

130°C 85%
Temperature
humidity test

Sample

-65°C - 25°C
150°C
(70min/cycle)

•. SINGLE BIT FAIL

**.

!

-

-

-

-

1000

0

40

-

-

-

-

-

-

0

-

-

-

-

-

-

0

40

2000
cycles

*.

0

40

1000

2000
cycles

0

0

**

O°C ~ 125°C
20 min/c

57

HI

• RELIABILITY INFORMATION . - - - - - - - - - - - - - - - - - OKI MEMORY LSI LIFE TEST RESULTS
MSM51257ALRS

MSM271000AS

MSM534000RS

Function

32K x 8 bit
STATIC RAM

128K x 8 bit
UV erasable EP ROM

512Kx8bit
Mask ROM

Structure

Si gate C-MOS
28P P-DIP

Si ~ate N-MOS
8P cerdip

Si gate C-MOS
28PP-DIP

Device name

Test item

Test condition

size

Test Failures Sample
size
hours

Test Failures Sample Test Failures
hours
hours
size

2000

Sample

Operating
Life test

Ta = 125°C
Vcc=7.0V

200

High temperature storage life

Ta = 200°C

-

130°C 85%
Vcc = 5.5V
Temperature
humidity test 85°C 85%
Vcc = 5.5V
Pressure
cooker test

121°C 100%
No bias

-65°C-25°C
150°C
(70min!cycle)

Device Name

Test item

Ta = 125°C
Vcc= 5.5V

High temperature storage life

Ta = 155°C

Temperature
humidity test

2000

0

88

-

-

100

2000

1 **

50

120

0

-

200

2000

0

50

500

0

22

2000

0

200

1000
cycles

0

0

-

-

-

-

22

120

0

1000

0

80

2000

0

-

-

50

200

0

22

2000

0

22

2000

0

100

500
cycles

0

100

500
cycles

0

*

50
-

MSM271000zBRS

MSM28C64ARS

Function

32K x 8 bit
STATIC RAM

128K x 8 bit
OTP

8Kx8bit
EEPROM

Structure

Si gate C-MOS
28P SOP

Si gate N-MOS
28P P-DIP

Si gate C-MOS
28P P-DIP

Sample Test
Sample Test
Sample Test
Failures
Failures
Failures
size
hours
size
hours
size
hours

-

-

-

88

*2000

0

100

2000

0

-

-

-

100

2000

0

200

2000

***
1

130°C 85%
Vcc= 5.5V

50

120

a

50

*120

0

50

120

0

85°C 85%
Vcc= 5.5V

200

2000

0

100

*2000

0

100

2000

0

300

0

22

300

0

22

300

0

-

-

22

2000

0

22

2000

0

0

100

500

0

100

500

0

Pressure
cooker test

121°C 100%
No bias

50

Low temperature life test

Ta=-10oC
Vcc=7.0V

-

Temperature
cycling test

-65°C - 25°C 150°C (70 min/cycle)

200

500

* : Vcc = 5.25V **: Charge loss fail
***: Charge loss fail (high temperature storage test after 10k W/E cycles test atTa = 25°C)

58

-

2000

MSM51257AGSK

Test Condition

Operating
Life test

88

.-

Low tempera- Ta =-lOoC
Vcc = 7.0V
ture life test
Temperature
cycling test

*

0

- - - - - - - - - - - - - - - - - - . RELIABILITY INFORMATION •
OKI MEMORY LSI ENVIRONMENTAL TEST RESULTS

~
Soldering
heat
Thermal
environmental
test

Mechanical
environmental
test

Electrical
Environmental
test

Thermal
shock

i

MSM511000ARS MSM514256AJS MSM511 OOOAZS
Sample
size

O°C-lOO°C
5 min
5min
10 cycles

Variable
frequency
vibration

100Hz-2000Hz
4 min per cycle
4 times in X, Y, Z

Shock

1500G, 0.5 ms,
5 times in each
X, Y,Z

Constant
acceleration

20oo0G
1 min in each X, Y, Z

ESD

100pF, 1.5kfl, 5 times
±l000V

Device name
Test condition

Soldering
heat

260°C
10 sec

Thermal
shock

0°C-100°C
5 min
5 min
10 cycles

22

0

22

0

Sample
size

Failures

22

0

22

0

22

0

22

0

10

0

10

0

Temperature
cycling

-65°C - RT - 150°C
30min
30 min
20 cycles

Variable
frequency
vibration

100Hz-2000Hz
4 min per cycle
4 times in X, Y, Z

Shock

1500G, 0.5 ms,
5 times in each
X,Y,Z

Constant
acceleration

10oo0G or 20000G
1 min in each X, Y, Z
100pF, 1.5kfl, 5 times
±l000V

HI

I

10

0

MSM41256ARS
Sample
size

I MSC2312YS9
-_.

0

22

*

MSC2304KS9

Sample
Failures
size

Sample
Failures
size

22

ESD

Failures

Sample
Failures
size

260°C
10 sec

-65"C - RT - i 50°C
30mi,;
30min
20 cycles

Thermal
environmental
test

Electrical
environmental
test

Test condition

Temperature
cycling

~

Mechanical
environmental
test

Device name

I
0

22

*

Failures

0

I
I

22

0

-

-

-

-

10

0

-

-

-

-

*. TEMPERATURE CYCLING: -40°C - 2SoC - 12SoC (20 cycles)
(30 min)

(30 min)

59

• RELIABILITY INFORMATION . - - - - - - - - - - - - - - - - - OKI MEMORY LSI ENVIRONMENTAL TEST RESULTS

~
Soldering
heat

11

Thermal
shock
Thermal

Device name
Test condition

MSM534000RS

MSM51257ALRS

MSM271000AS

Sample
size

Failures

Sample
size

Failures

Sample
size

Failures

22

0

22

0

22

a

22

0

22

a

22

0

10

0

10

0

-

-

260°C
10 sec
0°C-l00°C
5 min
5 min
10 cycles

environmental

test
Temperature
cycling

Variable
frequency
vibration

Mechanical
environmental
test

Shock
Constant
acceleration

Electrical
environmental

ESD

test

~
Thermal
environmental
test

Mechanical
environmental
test

Electrical
environmental
test

60

-65°C - RT - 150°C
30min
30 min
20 cycles

100Hz-2000Hz
4 min per cycle
4 times in X, Y, Z
1500G,0.5ms,
5 times in each
X, Y,Z
10000G or 20000G
1 min in each X, Y. Z
l00pF, 1.5kO, 5 times
±loooV

Device name

MSM51257AGSK MSM27000ZBRS

Test condition

Sample
Sample
Failures
size
size

Soldering
heat

260°C
10 sec

Thermal
shock

-100°C
5 min
5 min
10 cycles

Temperature
cycling

-65°C - RT - 150°C
30min
30 min
20 cycles

Variable
frequency
vibration

100Hz - 2000Hz
4 min per cycle
4 times in X, y, Z

Shock

1500G, 0.5 ms,
5 times in each
X,Y,Z

Constant
acceleration

l0000G or 20000G
1 min in each X, Y, Z

ESD

l00pF, 1.5kO, 5 times
±loooV

MSM28C64ARS

Sample
Failures
size

Failures

aoc

22

0

22

0

22

a

22

a

22

0

22

0

-

-

-

-

10

a

- - - - - - - - - - - - - - - - - - • RELIABILITY INFORMATION.
HIGH TEMPERATURE OPERATING LIFE TEST
MSM511000ARS

Ta

=25°C

Sample size 200

MAX.
MIN.
rnA

ICC1

MEAN
S.D.
DEL.

rnA

ICC2

ns

50.40

50.20

50.40

50.40

50.60

52.86
.85
0.00

52.89

52.87

.84
0.00

.87
0.00

52.66
.92

52.76
.88

0.00

0.00

1.0200

1.0200

1.0400

1.0400

MIN.

.4780

.4800

.4800

.4820

.4860

.4800

.5586
.0756
0.0000

.5603
.0741

.5626
.0732

.5615
.0750
0.0000

.5562
.0765
0.0000

.5627
.0747
0.0000

MAX.

68.0

0.0000 0.0000
68.0
68.0
68.0

68.0

MIN.

61.0

60.0

60.0

61.0

60.0

61.0

MEAN

64.8

64.6
1.7

64.6
1.7

64.7
1.7

64.5
1.7

64.7
1.7

0.0
21.0
19.0 .

0.0
21.0

0.0
21.0

0.0
21.0

0.0
21.0

19.0

19.0

20.3
.6
0.0

20.3
.6
0.0

19.0
20.3

1.6

MAX.

0.0
21.0

MIN.
MEAN

19.0
20.4

20.3

.6
0.0

.6
0.0

TRAC

68

34

f---- 1----1----1----1----1

56

168 500
Time(H)

1000 2000

1'----I--- -:I----~----I----,!

0

48

ICC1
mA

mA

56

1.6

52

1---1----1----1-- -1---I

.8

44

.4

48

168

500

Time (H)

1000 2000

168 500
Time (H)

1000 2000

ICC2

1.2

48

0

19.0
20.3
.6
0.0

26
18

48

.6
0.0

68.0

TCAC

ns
42

0

2000
54.40

52.85
.87
0.00

74

62

1000
54.40

1.0200

S.D.
DEL.

ns

500
54.60

1.0200

S.D.
DEL.

TCAC

168
54.40

MAX.
MEAN
S.D.
DEL.

ns

TRAC

48
54.60

0
54.60
50.60

I----I----I----r----I---~I
0

48

168 500
Time (H)

1000 2000

61

HI

• RELIABILITY INFORMATION . - - - - - - - - - - - - - - - - - HIGH TEMPERATURE OPERATING LIFE TEST
MSM511000ARS

Ta = 25°C

Sample size 200

ns

TRP

MAX.

0
25.0

48
25.0

168
25.0

500
25.0

1000
25.0

2000
25.0

MIN.

22.0

22.0

22.0

22.0

22.0

22.0

MEAN

24.0

24.0

23.9

23.9

.8
0.0
4096.0

.8
0.0
4096.0

.9
0.0
4096.0

.8
0.0
4096.0

23.9
.9
0.0
4096.0

23.9
.8
0.0
4096.0

S.D.
DEL.
MAX.

11

MIN.
ms

TREF

V

VeeM11'+-

787.0

774.0

983.3

803.0

876.0

844.0

MEAN

2933.3

2915.1

3015.6

2951.7

3013.6

2988.6

S.D.
DEL.

1313.0
0.0

1451.9
0.0

1246.6

1287.2
0.0

1273.4
0.0

1290.9

0.0

MAX.

3.320

3.290
3.050

3.300

3.300

3.290
3.050
3.155

MIN.

3.070

3.050

3.050

MEAN

3.167
.056
0.000

3.162
.057
0.000

3.156
.056
0.000

3.159
.055
0.000

3.154
.055
0.000

.055
0.000

S.D.
DEL.

V

Vee MAX

MAX.

7.000

7.000

7.000

7.000

7.000

7.000

MIN.

7.000

7.000

7.000

7.000

7.000

7.000

MEAN

7.000

7.000

7.000

7.000

7.000

7.000

S.D.
DEL.

0.000
0.000

0.000
0.000

0.000
0.000

0.000
0.000

0.000
0.000

0.000
0.000

VccM1N

V

3

Vcc MAX

V

4

9
:i----~----I---

- I---- i: --- - i:

2

8

7

*-- - -x---- *-- --J( -

- - - i C - - - - iC

6
0

48

168

500

1000 2000

0

48

Time (H)

168

500

1000 2000

Time (H)

TRP

ns

TREF

ms

50

4000

40

3000

30

2000

----

----j----- ----[---1

1--- -1---- 1--- - I -- --I---- I
1000

20
0

48

168

500

Time (H)

62

0.0

3.310
3.060

1000 2000

0

48

168

500

Time (H)

1000 2000

- - - - - - - - - - - - - - - - - - . RELIABILITY INFORMATION.
HIGH TEMPERATURE OPERATING LIFE TEST
MSM511000ARS

Ta

=25°C

Sample size 200

MAX.
MIN.
MEAN

V

VILA

S.D.
DEL.

V

VIHA

V

VILC

V

VIHC

0
1.100
.940

48
1.100
.940

168
1.100
.930

.940

1.047
.028

1.047

1.047

1.042

.028

.029

0.000

0.000

0.000
1.710

1.710

1.710

1.710

1.570

1.560

1.560

1.560

MEAN
S.D.
DEL.

1.656
.027
0.000

1.656
.027
0.000

1.656
.027
0.000

1.656
.027
0.000

1.658
.028
0.000

1.656
.027
0.000

MAX.

1.330

1.330

1.330

1.330

1.330

1.330

MIN.

1.040

1.040

1.040

1.040

1.040

1.040

MEAN
S.D.
DEL.

1.166
.061

1.165
.062
0.000

1.168
.062
0.000

1.166

1.160

.060
0.000

.057
0.000

1.163
.060
0.000

1.940
1.770

1.940

1.877
.032
0.000

1.876
.031
0.000

MAX.

0.000
1.940

1.940

1.940

1.940

MIN.

1.770

1.780

1.780

1.780

MEAN
S.D.
DEL.

1.876
.032

1.876
.032
0.000

1.878
.031

1.877
.032

0.000

0.000

0.000

500

1.92

1----1----1----1----1----1
0

1000 2000

48

VILA
V

V

1.2

1.8

fttl-Y--f
0

48

168

500

Time (H)

168

500

1000 2000

Time (H)

Time (H)

.9

1.770

VIHC

V

I----1--- -1---}---1----I

u

.029

1.560

1.76

1.1

0.000

1.710

2.08

168

0.000

1.700

1.32

48

0.000

.950

1.560

2.24

0

1.046

.028

1.045
.028

MAX.

1.48

1.16

2000
1.200

MIN.

VILC

V

1000
1.100
.940

500
1.100

1000 2000

1.7
1.6

VIHA

1----1----1 ----i----i----I

1.5
0

48

168

500

1000 2000

Time (H)

63

• RELIABILITY INFORMATION . - - - - - - - - - - - - - - - - - - -

4. SEMICONDUCTOR MEMORY
FAILURES
The life-span characteristics of semiconductor
elements in general (not only semiconductor Ie
devices) is described by the curve shown in the
diagram below. Although semiconductor
memory failures are similar to those of ordinary
integrated circuits, the degree of integration
(miniaturization), manufacturing complexity and
other circuit element factors influence their incidence.

11

al conditions) in the development stage to
reduce this type of failure. In addition to checking
endurance against surge currents, special protective circuits are incorporated in the input and
output sections.

......
AI
~'

Alu~num
.
wore

Input section

.wl1'4:.$G7R~
t

, __ ,
t

Poly Si

Destruction
position

Semiconductor Element Failure Rate Curve
1

S

a:'"

e
.=

'iii
LL

Initial SHIPPING
failure
~

Wear-out
Random _ _ _......:f""ailure
failure

\

m>l

\

I

\
\

,
\

,..

m ........ 69

MSM41256A

262, 144-Word x 1-Bit RAM (NMOS)  ....... 85

MSM41257A

262, 144-Word x 1-Bit RAM (NMOS)  ..... 100

MSM41464

65,536-Word x 4-Bits RAM (NMOS)  ...... 116

MSM51C256

262, 144-Word x 1-Bit RAM (CMOS) .................. 131

MSM511000A

1,048,576-Word x 1-Bit RAM (CMOS)  ..... 147

MSM511001A

1,048,576-Word x 1-Bit RAM (CMOS)  ... 162

MSM511002A

1,048,576-Word x 1-Bit RAM (CMOS)  ., 177

MSM514256A

262, 144-Word x 4-Bits RAM (CMOS)  ...... 191

MSM514258A

262, 144-Word x 4-Bits RAM (CMOS)  .. , 205

MSM514100

4, 194,304-Word x 1-Bit RAM (CMOS)  ..•.•• 220

MSM514102

4, 194,304-Word x 1-Bit RAM (CMOS)  •.• 234

MSM514400

1,048,576-Word x 4-Bits RAM (CMOS)  ..•..

MSM514402

1,048,576-Word x 4-Bits RAM (CMOS)  .. 262

MSC2304YS8-KS8

262,1 44·Word X 8·Bits RAM (NMOS)  (MODULE) .••••.. 277

MSC2304YS9-KS9

262,1 44-Word x 9-Bits RAM (NMOS)  (MODULE) •...... 292

MSC2307YS9-KS9

262, 144,word x 9-8its RAM (NMOS)  (MODULE) .. 307

248

MSC2312A-XXYS9/KS9

1,048,576-Word x 9-Bits RAM (CMOS) (MODULE) ..... 321

MSC2313A-XXYS8/KS8

1,048,576-Word x 8-Bits RAM (CMOS) (MODULE) ..... 331

MSC2320A-XXYS9

262, 144-Word x 36-Bits RAM (MODULE) . . . . . . . . . . . .. 341

MSC2321 A-XXYS 18

524,288-Word x 36-Bits RAM (MODULE) ............. 351

MSC2328A-XXYS2/KS2

262,144-Word x 8-Bits RAM (MODULE) .............. 360

MSC2340-XXYS9/KS9

4, 159,300-Word x 9-Bits RAM (CMOS) (MODULE) ..... 370

OKI

semiconductor

MSM3764 A
65,536-BIT DYNAMIC RANDOM ACCESS MEMORY (E3-S-004-32l

GENERAL DESCRIPTION
The Oki MSM3764A is a fully decoded, dynamic NMOS random access memory organized as 65536 one-bit words.
The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory,
peripheral storage and environments where low power dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MSM3764A to be housed in a standard 16 pin
DIP or 18 pin PLCC. Pin-outs conform to the JEDEC approved pin out.
The MSM3764A is fabricated using silicon gate NMOS and Oki's advanced Double-Layer Polysilicon process. This
process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimum chip
size. Dynamic circuitry is employed in the design, including the sense amplifiers.
Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTL
compatible.

FEATURES
.65,536 x 1 RAM, 16 or 18 pin package
• Silicon-gate, Double Poly NMOS, single transistor cell
• Row access time,
120 ns max (MSM3764A-12)
150 ns max (MSM3764A-15)
• Cycle time,
220 ns min (MSM3764A-12)
260 ns min (MSM3764A-15)
• Low power: 330 mWactive,
28 mW max standby
.Single +5V Supply, ±10% tolerance
• All inputs TTL compatible, low capacitive load

• Three-state TTL compatible output
• "Gated" CAS
• 128 refresh cycles/2 ms
• Common I/O capability using "Early Write"
operation
• Output unlatched at cycle end allows extended page
boundary and two-dimensional chip select
• Read-Modify-Write, RAS-only refresh, and PageMode capabil ity
• On-chip latches for Addresses and Data·in
• On-chip substrate bias generator for high
performance

PIN CONFIGURATION

Om t-IC

2

Vss CAS

1 1817
Pin ..... m ..

Dout

A;
NC

A·J

....

8 9 10"

,...

~A,

Pi" Names

~"nc1l0"

Ado, . . lnDua

I\4S

en

Aoww Add,.... StrObe
Column Add'.... Strobe

Wl"

Wrl,. Enable

Din

OGO"

0.,. Input
0.,.0u-q,ut

Vee

Power 1+5VI

VSS

Ground IOV)

NC

No ConnectIon

Ao-A,

','

"
.,'
.,'

Function
Address Inpun

CAS

=

Column Addr... Strobe

WE'

Writ. Enabl.

Row Addr." Strobe

Din

Catl Input

Oout

O.t. Output

VCC

Po~'

VSS

around IOV)

Supply (+5V)

• A.fresh Add, ...
• Ratr..h Addr...

69

• DYNAMIC RAMS· MSM3764A . 1 - - - - - - - - - - - - - - - - - - - FUNCTIONAL BLOCK DIAGRAM

I----WE

Buffers

Dout

Row
Address
Buffers
Row
De·

Word
Driv·
ers

Memory

I-----Din

eells

vee---~y~-I___________~
VSS-

On chip VBB

ABSOLUTE MAXiMUM RATINGS

ISee Note)

Symbol

Value

Unit

VIN, VOUT

-1 to +7

V

Voltage on Vee supply relative to VSS

Vee

-1 to +7

V

Operating temperature

Topr

o to 70

°e

Storage temperature

T stg

-55 to +150

°e

Po

1.0

W

50

mA

Rating
Voltage on any pin relative to Vss

Power dissipation
Short circuit output current

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional opera-

tion should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS
IReferenced to VSS)

Parameter

Supply Voltage

70

Symbol
Vee
VSS

Min.

Typ.

Max.

Unit

4.5
0

5.0
0

5.5
0

V
V

6.5

V

0.8

V

Input High Voltage, all inputs

VIH

2.4

Input Low Voltage, all inputs

VIL

-1.0

-1.0

Operating
Temperature

O°C to +70°C

- - - - - - - - - - - - - - - - - - - - . DYNAMIC RAMS· MSM3764A.

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

Symbol

Parameter

Min.

Max.

Unit

60

mA

Notes

Operating Current"
Average power supply current
(RAS, CAS cycling; tRC = min.!
Standby Current
Power supply current
(RAS = CAS = VIH!

ICC1

5.0

ICC2

Refresh Current"
Average power supply current
(RAS cycling, CAS = VIH; tRC

= min.!

Page Mode Current"
Average power supply current
(RAS = VI L, CAS cycling; tpc

= min.!

mA

ICC3

40

mA

ICC4

60

mA

Input Leakage Current
Input leakage current, any input
(OV :0; VIN :0; 5.5V, all other pins not
under test = OV!

III

-10

10

IJ.A

Output Leakage Current
(Oata out is disabled,
OV :0; VOUT:O; 5.5V!

lLO

-10

10

IJ.A

Output Levels
Output high voltage (IOH = -5 mAl
Output low voltage (lOL = 4.2 mAl
Note":

2.4

VOH
VOL

0.4

V
V

ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.

CAPACITANCE
(T a =25°C,f=1MHz!
Unit

Parameter

Symbol

Typ.

Max.

Input Capacitance (Ao - A" DIN!

CIN1

-

5

pF

Input Capacitance (RAS, CAS, WE!

CIN2

-

8

pF

7

pF

Output Capacitance (DOUT!

COUT

Capacitance measured with Boonton Meter.

71

• DYNAMIC RAMS· MSM3764A . - - - - - - - - - - - - - - - - - - - -

AC CHARACTERISTICS
Note 1,2,3

(Recommended operating conditions unless otherwise noted.)

Parameter

Symbol

Units

MSM3764A-12

Refresh period

MSM3764A-15
Note

Min.

Max.

Min.

tREF

ms

Random read or write cycle time

tRC

ns

220

260

Read-write cycle time

tRWC

ns

245

280

120

145

Page mode cycle time

2

Max.

2

tpc

ns

Access time from R AS

tRAC

ns

120

150

4,6

Access time from CAS

tCAC

ns

60

75

5,6

Output buffer turn-off delay

tOFF

ns

Transition time

tT

RAS precharge time

tRP

0

35

ns

3

35

ns

90

RAS pulse width

tRAS

ns

120

RAS hold time

tRSH

ns

60

CAS precharge time (Page cycle)

tcP

ns

50
60

tCAS

ns

CAS hold time

tCSH

ns

120

RAS to CAS delay time

CAS pulse width

0

40

3

35

100
10,000

150

60
10,000

75

10,000

150

tRCD

ns

25

CAS to RAS precharge time

tCRP

ns

0

Row Address set-up time

tASR

ns

0

0

Row Address hold time

tRAH

ns

15

15

Column Address set-up time

tASC

ns

0

0

Column Address hold time

tCAH

ns

20

20

Column Address hold time
referenced to R AS

tAR

ns

80

95

Read command set-up time

tRCS

ns

0

0

Read command hold time

tRCH

ns

0

0

-10

-10

Write command set-up time

10,000

75

60

25

75

7

0

twcs

ns

Write command hold time

tWCH

ns

40

45

Write command hold time
referenced to RAS

tWCR

ns

100

120

8

Write command pulse width

twp

ns

40

45

Write command to RAS lead time

tRWL

ns

40

45

Write command to CAS lead time

tCWL

ns

40

45

Data-in set-up time

tDS

ns

0

0

Data-in hold time

tDH

ns

40

45

Data-in hold time referenced
to RAS

tDHR

ns

100

120

CAS to WE delay

tCWD

ns

40

45

8

RAS to WE delay

tRWD

ns

100

120

8

Read command hold time
referenced to RAS

tRRH

ns

0

0

CAS precharge time

tCPN

ns

30

35

72

- - - - - - - - - - - - - - - - - - - - . DYNAMIC RAMS, MSM3764A.
NOTES: 1) An initial pause of 100"s is required after power-up followed by any 8 RAS cycles IExamples; RAS
only) before proper device operation is achieved.
2) AC measurements assume tT = 5 ns.
3) VIH IMin.) and VI L IMax.) are reference levels for measuring timing of input signals. Also, transition
times are measured between VI H and VI L.
4) Assumes that tRCD < tRCD Imax.).
If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by
the amount that tRCD exceeds the value shown.
5) Assumes that tACO < tRCD Imax.)
6) Measured with a load circuit equivalent to 2 TTL loads and 100pF.
7) Operation within the tRCD Imax.) limit insures that tRAC Imax.) can be met. tRCD Imax.} is specified as a reference point only; if tRCD is greater than the specified tRCD Imax.) limit, then access
time is controlled exclusively by tCAC.
8) twcs, tCWD and tRWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only; if twcs ;::: twcs Imin.), the cycle is an early write cycle and the oata
out pin will remain open circuit Ihigh impedance) throughout the entire cycle; if tewD ~ tCWD
Imin.) and tRWD > tRWD Imin.) the cycle is read-write cycle and the data out will contain data read
from the selected cell; if neither of the above sets of conditions is satisfied the condition of the data
out lat access time) is indeterminate.

READ CYCLE TIMING

~--------------------tRC------------------~~
~------------tRAS------------~~

RAS

"I

VIH - - - - , I I - - - - - - - - t A R
VIL -

Lr------.!
'-----

~---+--tRSH------~

CAS

VIH VIL -

--------~-,. t-----+--tCAS------~

r-'---+------.J

tCSH -----~.,

Addresses

WE

VIHVIL -

VIHVIL -

I

I

t------ tCAC
~----------tRAC---------~

DOUT

VOHVOL-

---J

tOFF

J-----.J..
OPEN

Valid Data
~ "H", "L" = Don't Care

73

• DYNAMIC RAMS· MSM3764A . , - - - - - - - - - - - - - - - - - - - -

WRITE CYCLE TIMING
(EARLY WRITE)

RAS

VIHVIL -

tRC
tRAS

tAR

tRSH
tCAS

D

CAS

VIH -VIL -

WE

VIHVIL -

DIN

DOUT

VOHVOL -

READ-WRITE/READ-MODI FY-WRITE CYCLE

~---------------------TRWC----------------------}­

VIHVIL -

lE

---------------tRAS----------------~~~
tAR

""I

~tRP

tRSH
tRCD--o!---'----tCAS

tCRP

I

VIH-------------~~~

VIL -

Addresses VV I H IL -

L

VIH-~~~nr,~~~----------------------,I

VIL -

'-'.I..LL.U...'4"L.U...:.LLL.u,

tCAC
DOUT VOH VOL-

OPEN
_

ulN

VIH VIL -

tRAC

r-----\V~a;t;lidd[D;;;a;,ta;_------,l_-----

~

Ijlll,

'1111,

~tDS~tDH

.,

V%'W

Valid
Data

'II~

~ "H", "L"

74

=

Don't Care

- - - - - - - - - - - - - - - - - - - - . DYNAMIC RAMS· MSM3764A.
RAS ONLY REFRESH TIMING
ICAS: VIH,~ & DIN: Don't care)

Addresses

rr;R,"~'R"
~~ASR~

~:~ =""'~"",7T7':",""~,.,,rrrr~R-O-W-A-d-d-r-es-s

L'R,J-

VOH DOUT

OPEN

VOL

~"H", "L" = Don't Care

PAGE MODE READ CYCLE

tRAS--------------------~

CAS

VIHAdresses VI L -

DOUT VOH- ______

~~*-----rrn~--~sj~--~~-tR~-H,~~~
~"H","L"=Don't CarE

75

• DYNAMIC RAMS· MSM3764A . - - - - - - - - - - - - - - - - - - - -

PAGE MODE WRITE CYCLE

~------------------tRAS------------------~

Addresses vV I H - 'lhJ'Rn.IIJ~IIArC,
IL-

~"H",

"L" ~ Don't Care

PAGE MODE, READ-MODIFY-WRITE CYCLE

RAS

VIH

tAR---j

VIL
tcp

CAS

Addresses

WE

VIH
VIL

VIH
VIL

VIH
VIL

DIN

VIH
VIL

DOUT VOH
VOL

~ "H" , "L" ~ Don't Care

76

--------------------------------------I_OYNAMICRAMS·MSM37MA_

HIDDEN REFRESH

Addresses

~ ttRA~CtCAC
VOH ---OPEN
DOUT
VOL

_

~'o;f$l/I/!$

~-----V-a-lid-D-a-ta-----

.-

~ "H", "L"

DESCRIPTION
Address Inputs:
A total of sixteen binary input address bits are required
to decode any 1 of 65536 storage cell locations within
the MSM3764A. Eight row-address bits are established
on the input pins (Ao -A,) and latched with the Row
Address Strobe (RAS). The eight column-address
bits are established on the input pins and latched with
the Column Address Strobe (CAS). All input addresses
must be stable on or before the falling edge of RAS.
CAS is internally inhibited (or "gated") by RAS to
permit triggering of CAS as soon as the Row Address
Hold Time (tRAH) specification has been satisfied and
the address inputs have been changed from row-addresses
to column-addresses.

Write Enable:
The read mode or write mode is selected with the WE
input. A logic high (1) on WE dictates read mode;
logic low (0) dictates write mode. Data input is disabled when read mode is selected.

Data Input:
Data is written into the MSM3764A during a write or
read-write cycle. The last falling edge of WE or CAS is
a strobe for the Data In (DIN) register. In a write
cycle, if WE is brought low (write mode) before CAS,
DIN is strobed by CAS, and the set-up and hold times
are referenced to CAS. In a read-write cycle, WE will
be delayed until CAS has made its negative transistion.
Thus 0 I N is strobed by WE, and set-up and hold times
are referenced to WE.

Data Output:
The output buffer is three-state TTL compatible with
a fan-out of two standard TTL loads. Data-out is the

= Don't Care

same polarity as data-in. The output is in a high impedance state until CAS is brought low. In a read cycle,
or read-write cycle. the output is valid after tRAC from
transition of RAS when tRCD (max.) is satisfied, or
after tCAC from transition of CAS when the transition
occurs after tRCD (max.). Data remain valid until CAS
is returned to a high level. In a write cycle the identical
sequence occurs, but data is not val id.

Page Mode:
Page-mode operation permits strobing the row-address
into the MSM3764A while maintaining RAS at a logic
low (0) throughout all successive memory operations in
which the row-address doesn't change. Thus the power
dissipated by the negative gOing edge of RAS is saved.
Further, access and cycle times are decreased because
the time normally required to strobe a new row-address
is eliminated.

Refresh:
Refresh of the dynamic memory cells is accomplished
by performing a memory cycle at each of the 128 rowaddresses (Ao-A.) at least every two milliseconds.
During refresh, either VIL or VIH is permitted for A,.
RAS only refresh avoids any output during refresh
because the output buffer is in the high impedance
state unless CAS is brought low. Strobing each of 128
row-addresses with RAS will cause all bits in each rwo
to be refreshed. Further RAS-only refresh results in a
substantial reduction in power dissipation.

Hidden Refresh:
RAS ONLY REFRESH CYCLE may take place while
maintaining valid output data. This feature is referred
to as Hidden Refresh_
Hidden Refresh is performed by holding CAS as VIL
from a previous memory read cycle.

77

-OVNAMICRAMS·MSM37MA_I-------------------------------------TYPICAL CHARACTERISTICS

:>
o
Lri

1.4

II

~ 1.2

Access time from RAS
(Relative value) v.s. VCC

50

Ta = 25°C
tRCO: min

~

u

"'-

~ 1.0

-t::

U

~ 0.8

'"

ICCl (tRAS: Constant)
V.s. VCC

:?

S

40

"2
0

..

';:J

............

~

~

30

Q.

Q

-

u 20
u

u

tRC = 1000 ns


o
II

~
>

1.2 t-----'IIId-"II..---+----\-----i

50

:?

S

40

"2

o

u

~ 1.0 r----+'~""""r"'-l:__---l

Ta=50°C
Ta= 25°C
Ta = O°C

-t::

U

~ 0.8

3

4

5

Cycle Rate (l/tRC) [MHz]

u

ICCl (tRAS: Constant)
v.s. Ta
VCC = 5.5V ;1
tRAS = 120 ns
tR C = 220 flS
I
tR C = 260 ns

..

'f

';:J

~

~

30

tR C = 330 ns

I

o

u 20

tR C = 500 ns

I

u

tR c=1000ns

:

..c

-0 3.0
c:

..,co

~

f5

20

VIH:1max

..§.. 4.0

2.0

_ Ta =

-

-:Ta -

-

Ta =
Ta =

!:}

4.0

50

4.5

5.0
5.5
VCC [V]

6.0

ICC1 (tRP: Constant)
v.s. Cycle rate
Ta = 25°C

';?

4.0

4.5

VCC = 5.5V
I

VCC = 5.0V
I
VCC = 4.5V

c:

0
.;::;

';?

E 4.0

>:
..c

-0 3.0
c:

~

..,co

Q)

Q.

2
U

6.0

ICC2 v.s. Ta
VCC = 5.5V
VIH: max

5.0

..§..

5.0
5.5
VCC [V]

-

~

f5' 2.0

....... .............

r-----..

u

u

o

4
2
3
5
Cycle Rate (1/tRC) [MHz]

75

50 ICC, (tRP: Constant) v.s. Ta

';?
E

40

c:

0
.;::;
co

Q;

30

Q.

2
u
u

20

-

-

---r--

I

-I"'t RC

I

I--.

= 500 ns

t RC = 1000 ns

VCC = 5,5V
tRP = 90 ns

o

I

t RC = 220 ns
I
I"'t RC = 260 ns
I
I'"t RC = 330 ns

75

I

79

_DYNAMIC RAMS· MSM37MA---------------------------------------

..sa;~

40

ICC3 (tRAS: Constant) v.s. VCC

~

a; 30
'U

.

U

>-

..,....

20

.<=

-

~

Q)

r:t!"

II
~

Q)

M

U

!d

0
4.0

40

E

a; 30

4.5

5.0
5.5
VCC[V]

6.0

ICC3 (tRAS: Constant)
v.s. Cycle rate
Ta = 25°C
tRAS = 120 ns

VCC = 5.5V
VCC = 5.0V
I
VCC = 4.5V

'U

>.r:. 20

u

.

-

10

Ta = 25°C
tRP = 90 ns

30

VCC = 5.5V
Vec = 5.0V
VCC = 4.5V

10

M

u
u

0
1

40

J
I

20

tR C = 330 ns

10

t~ C = 500 ns
C = 1000 ns
tl

I

M

U

o

0

4
2
3
5
Cycle Rate (l/tRC) [MHz]

.~.,

t.)

40

.~.,

~

a:

ICC3 (tRP: Constant)
v.s. Cycle rate

>-

a:

ICC3 (tRAS: Constant) v.s. Ta
VCC = 5.5V
tRAS = 120 ns
C = 220 ns
a; 30
I
'U
c=260ns
tR
>-

-

6.0

'U

-

M

U
~

5.0
5.5
VCC[V]

.

U

~
E

..sa;

4.5

.<=

~

!d

~

0
4.0

U

Q)

a:

20

a: 10

10

0

!:?

tRC = 220 ns
tfiC. = 260 ns
tRG. = ~ ns
tRG = 500 ns
tR = 1000 ns

E

~

30

'U

Ci
.<=
..,

80

ICC3 (tRP: Constant) v.s. VCC
40

o

25
50
Ta eC]

75

1

4
2
3
5
Cycle Rate (1ItRC) [MHz]

ICC3 (tRP: Constant) v.s. Ta
VCC - 5.5V
tRP = 90 ns
tj C = 220 ns
a; 30
tR"C = 260 ns
~
tR"C = 330 ns
u
C = 500 ns
.<= 20
~
tR c=1000ns

~

40

..s

.....

- tR

......

.

-

Q)

a:

10

M

U
U

o

o

25
50
Ta roC]

75

- - - - - - - - - - - - - - - - - - - - . DYNAMIC RAMS· MSM3764A.

ICC4 (tCAS: Constant)
v.s. VCC

ICC4 (tcp: Constant) v.s. VCC

50r--~~~--.--'

~
E

Ta = 25°C
tCAS = 60 ns

40

tpc = 120 ns
tpc = 145 ns

'"

u

G

50

I

30 >-~"';"~~~--I---=tPc = 230 ns

'"
g

tp 1 = 400 ns
~ 20~~~~~----+---~

~
E 40~-~~~~~-~

u'"

G 30~--~~~~--+---~
'"
'""

u

'"

Ta = 25°C
tcp = 50 ns

40
30

Cl

'"

~
"

'"
'"

30>-~---+---->--=~~

Cl

:

u

20L-r::::t~~~::t

u

o

25
50
Ta rOC)

75

o

25
50
Ta rOC)

75

81

• DYNAMIC RAMS· MSM3764A . - - - - - - - - - - - - - - - - - - - -

Address Input v.s. Ta

Address Input v.s. Vee

>

vJe= 5.bv
2.0

>

~IH mi~
VIL max

1.0 f--+--+---t------j

11

4~

4~

5~

5.5

o

6~

75

Vee [V]

Data Input v.s. Ta

Data Input v.s. Vee

~

>

2.0 1---+---'-'--;:=-=--'=-+---"""...-1

:>

~
~ 1.5 1---"..t!5"""'---4--+---1

~

0.

0.

....::J
c

1.0 f----i------1---t---j

4.0

4~

5~

5~

~

....::J
C

vJe= 5.L
2.0

VIH min
VIL max

1.5

1.0

o

6~

75

Vee [V]

Clock Input v.s. Vee

Clock Input v.s. Ta

Ta = 25°C

:> 2.0

:>

Qj

>

~

....::J

>

~

...

1.5

I

::J

c

4.5

5.0
5.5
Vee [V]

6.0

I

I

VIL max

0.

1.0

4.0

82

~IH mi~

Qj

1.5

0.
C

vbe = 5.6v
2.0

1.0

o

75

- - - - - - - - - - - - - - - - - - - . DYNAMIC RAMS· MSM3764A.

VCC = 5.5V
Ta = 25°C
50 ns/div

.

RAS/CAS CYCLE LONG RAS/CAS CYCLE RASONL Y CYCLE PAGE MODE CYCLE

RAS l- iCAS l-I-

\ol-V
~ 1-1- V

1'-1-

V

~V~ ~.i-' '"""

I'-~

140
ICC
[rnA]

120
100
80

..

60

11

20
0

~WI

\I

40

lA

\i

I_~ ~

V

~

~

~

~

V

83

• DYNAMIC RAMS· MSM3764A . - - - - - - - - - - - - - - - - - - - -

MSM3764A Bit MAP (Physical-Decimal)

[A7 column - "H"J
63 62
255 255

1 0
255 255

191 190
255 255

129 128
255 255

r<>--

....,...

{A7 column - "L"]

OPIN 16

64 65
255 255

126 127
255 255

63 62
127 127

1 0
127 127 r<'I

192 193
255 255

254 255
255 255

191 190
127 127

129 128
127 127
1
0
126 126

~
f-..- 64
126 126

r<>-

64

~
192 r;-ro

>-<>-

64 65
254 254

126 127
254 254

W<

192 193
254 254

191 190
126126

129 128
126 126

il<>'

192 193
126 126

~

64 65
253 253

254 255
254 254
126 127
253 253

63 62
125125

1 0
125 125

~

64 65
125 125

129 128
253 253

--&-

192 193
253 253

254 255
253 253

191 190
125 125

129 128
125 125

f-..-

192 193

63 62
252 252

1
0
252 252

--&-

64 65
252 252

126 127
252 252

63 62
124124

0
1
124 124

-<>-

191 190
252 252

129 128
252 252

~

192 193
252 252

254 255
252 252

191 190
124124

129 128
124 124

)e<

63 62
251 251

1
0
251 251

~

64 65
251 251

126 127
251 251

63 62
123 123

1 0
123 123

)<><

1 0
254 254

191 190
254 254

fe3
62
253

129 128
254 254

253

1 0
253 253

191 190
253 253

254 255
127 127

127

63 62
126 126

63 62
254 254

\

126 127
127 127

65
127

126 127
126 126
254 255
126 126
126 127
125 125
254 255
125 125

~~
65

126 127
124 124

..!.!! ~
192 193
124 124

254 255
124 124

64 65
123 123

126 127
123 123

I

191 190
132 132
63 62
131 131
191 190
131 131
63 62
130 130
191 190
130 130

129 128
132 132
1

192 193
132

254 255
132 132

191 190
4 4

65
131 131

126 127
131 131

f-<>-

192 193
131 131

254 255
131 131

63 62
3
3
i9i 190

f-<>-

64 65
130 130

126 127
130 130

~

0

~
~
131 131

I-- r-1
0
130 130
129 128
130 130

192 193
130 130

~

254 255
130 130

64 65
129 129

126 127
129 129

192193
129129

254255
129129

~

1~~ 1~~

~~~

OJ ill ~

192 193

254 255

63 62
129 129

1 0
129 129

191 190
129129

~~

1~~ 1~~
f;gj ~

12~ 12~
I;fs I;Ta

~
h>-

129128

~

Refresh Address?

(63 - OJ

I

6,

Om
(Po""ve!
\

0,

A

B

~

0

==
==

l~Refresh Address,-I 1\ (64 ~ 1271 --.-J
0,

b;

Row Address (Decimail

=

-..2 -..2

Number of Bus LIne!

129 128
4
4
1
0
3
3

~

129 128
3
3
1
2

63 62
2
2

i9i 190
2

2

63 62
1
1
i9i' 190
1

1

~0 t;go0

0
2

129 128
2
2
1
1

~

192 193
4
4
64 65
3
3

254 255
4
4
126 127
3
3

tv

192 193
3
3

254 255
2
3

f-<>-

64 65
2
2

126 127
2
2

~

192 193
2
2

254 255
2
2

0
1

~

129 128
1
1

~

63 "62

1
0

0
0

~

129 128
0
0

~

0

64
1

65
1

126 127
1
1

192 193
1
1

254 255
1
1

64

126 127
0
0

65

rw% ~
0

254 255
0
0

0

Ell ill ~ CD ill

oI-n
(Nega"ve!

Column Address (Decimal)

Sub Amp (e

m

m[128

Pin 8

:
Cell

84

~

~

~

(Column)

.Refresh AddreS!!

7Eh1~efreSh Address

(63 - O!
DIn
(Positive)

(64 ~ 127!

ill

I

04

D3

_
0,

"04

~
DIn
(Negative)

(Rowl

Word Driver

-e---

Sense Amp

OKI

semiconductor

MSM41256A
262,144-BIT DYNAMIC RANDOM ACCESS MEMORY 
GENERAL DESCRIPTION
The Oki MSM41256A is a fully decoded, dynamic NMOS random access memory organized as
262144 one-bit words. The design is optimized for high-speed, high performance applications such
as mainframe memory, buffer memory, peripheral storage and environments where low power .dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MSM41256A to be housed in a standard
16 pin DIP or 18 pin PLCC. Pin-outs conform to the JEDEC approved pin out. Additionally, the MSM
41256A offers new functional enhancements that make it more versatile than previous dynamic RAMs.
"CAS-before-RAS" refresh provides an on-chip refresh capability.
The MSM41256A is fabricated using silicon gate NMOS and Oki's advanced VLSI Polysilicon
process. This process, coupled with single-transistor memory storage cells, permits maximum circuit
density and minimum chip size. Dynamic circuitry is employed in the design, including the sense
amplifiers.
Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and
output are TTL compatible.

FEATURES
•
•
•

•

•

•

262,144 x 1 RAM, 16 or 18 pin package
Silicon-gate, Double Poly NMOS, single
transistor cell
Row access time:
100 ns max (MSM41256A-1 0)
120 ns max (MSM41 256A-1 2)
150 ns max (MSM41256A-15)
Cycle time:
200 ns min (MSM41256A-1 0)
220 ns min (MSM41 256A-1 2)
260 ns min (MSM41256A-15')
Low power:
330 mW active (MSM41 256A-1 0)
303 mW active (MSM41 256A-1 2)
275 mW active (MSM41256A-15)
28 mW max standby
Single +5V Supply, ±1 0% tolerance

• All inputs TTL compatible, low capacitive load
• Three-state TTL compatible output
• "Gated" CAS
• 256 refresh cycles/4 ms
• Common I/O capability using "Early Write"
operation
• Output unlatched at cycle end allows
extended page boundary and
two-dimensional chip select
• Read-Modify-Write, RAS-only refresh,
capability
• On-chip latches for Addresses and Data-in
• On-chip substrate bias generator for high
performance
• CAS-before-RAS refresh capability
• "Page Mode" capability

PIN CONFIGURATION (TOP VIEW)

Pin Names

Din A. Vss

Function

Ao-A&

Addrese Inputs

RAS

Row Address Strobe

CAS

Column Address Strobe

WE

WrileEnllble

D'N

Data Input

DOUT

OalaOulpul

VCC

Power Supply 1+5V)

VSS

Ground (OV)

• Refresh Address

,

CAr
,"fnN _ _

1 18 17

' ..nw:tlort

A.-A.

NC

NC

A;
A;
8 9 1011

A;

A!A:

Vce

If.i!
CAl
IV<"

A"'_I~ ..

"_A. . . . . StrotMo
Cotumfl Addr_ StroM
Wrtt.lEn....
OOto'."...1

D~.

Dot.Olltp",

Vee

'"_C+5V'

....SS

G,ound tOVI
No Con...c1ion

• A.f • ...., Add, ...

85

"..

~

• DYNAMIC RAMS· MSM41256A . : - - - - - - - - - - - - - - - - - - - FUNCTIONAL BLOCK DIAGRAM

~~~-------.r>-----