1990_PMI_SSM_Audio_Products_Volume_1 1990 PMI SSM Audio Products Volume 1
User Manual: 1990_PMI_SSM_Audio_Products_Volume_1
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SUMER
13555 BISHOP'S COURT
BROOKFIELD, WI. 53005
414/784-6641
~""--"--
®
IPMI)
SSM AUDIO PRODUCTS
AUDIO
HANDBOOK
VOLUMEl
TABLE OF CONTENTS
Precision Monolithics Inc.
Introduction ......................................................................................................................................................................................... 4
Definitions ........................................................................................................................................................................................... 5
Product Data Sheets
Voltage-Controlled Amplifiers
SSM-2013
Voltage-Controlled Amplifier .............................................................................................................................. 7
SSM-2014
Voltage-Controlled Amplifier/OVCE .............................................................................................................. 12
SSM-2018
Voltage-Controlled Amplifier/OVCE* .............................................. New ................................................... 23
SSM-2024
Quad Current-Controlled Amplifier ................................................................................................................ 24
SSM-2120
Dynamic Range Processor .................................................................................................................................. 30
SSM-2122
Dual VCA ............................................................................................................................................................... 30
Surround Sound Decoder
SSM-2125
Dolby Surround Pro-Logic Matrix Decoder* .................................... New ................................................... 42
Audio Preamplifiers
SSM-2015
Low-Noise Microphone Preamplifier ............................................................................................................... 44
SSM-2016
Ultra-Low Noise Differential Audio Preamplifier .......................................................................................... 49
SSM-2017
Self-Contained Audio Preamplifier* ................................................... New ................................................... 57
Audio Switches
SSM-2402
Dual Audio Analog Switch .................................................................. New ................................................... 58
SSM-2412
Fast Dual Audio Analog Switch .......................................................... New ................................................... 58
Line DriverlReceiver
SSM-2141
High Common-Mode Rejection Differential Line Receiver ............ New ................................................... 68
SSM-2142
Balanced Line Driver* ........................................................................... New ................................................... 75
Audio Operational Amplifiers
SSM-2131
Low Distortion, High-Speed Operational Amplifier ....................... New ................................................... 76
SSM-2132
Dual Audio Operatiomi.l Amplifier* .............. ,.................................... New ................................................... 88
SSM-2134
Low-Noise Audio Operational Amplifier ........................................................................................................ 89
SSM-2139
Dual Low-Noise Operational Amplifier ............................................ New ................................................... 95
Matched Transistors
SSM-2210
Dual Matched NPN Transistors .......................................................... New ................................................. 104
SSM-2220
Dual Matched PNP Transistors ........................................................... New ................................................. 115
Level Detection System
SSM-2110
RMS-to-DC Converter ......................................................................................................................................... 123
Voltage-Controlled Filters
SSM-2044
Voltage-Controlled Filter/Oscillator .............................................................................................................. 134
SSM-2045
Voltage-Controlled Signal Processor .............................................................................................................. 140
SSM-2047
Voltage-Controlled Filter with Triple VCAs ................................................................................................. 147
Log Conversion Amplifier
SSM-2100
Log/ Antilog Amplifer ...................................................................................................................................... 151
Multiplexed Sample~and-Hold
SSM-2300
8-Channel Multiplexed Sample-and-Hold .................................................................................................... 160
• Advance Information
2
TABLE OF CONTENTS
Application Notes - New 1989 and 1990 Publication
AN-Ill
AN-112
AN-l13
AN-114
AN-lIS
AN-116
AN-121
AN-122
AN-123
AN-124
AN-125
AN-127
AN-128
AN-129
AN-130
AN-131
AN-133
AN-l34
AN -135
PMI.Products
A Balanced Summing Amplifier ........................................................................... SSM-2015, OP-41 ..................... 167
A Balanced Input High-Level Amplifier .............................................................. SSM-2015 .................................. 169
An Unbalanced, Virtual Ground Summing Amplifier ...................................... SSM-2134 .................................. 171
A High-Performance Transformer-Coupled Microphone Preamplifier ......... SSM-2015, 2016 ........................ 172
Balanced Low-Noise Microphone Preamplifier Design .................................... SSM-2015 .................................. 174
AGC Amplifier Design with Adjustable Attack and Release Control ............ SSM-2013 .................................. 176
High-Performance Stereo Routing Switcher ....................................................... SSM-2402, 2015, 2134 .............. 178
A Balanced Mute Circuit for Audio Mixing Consoles ....................................... SSM-2402, 2122,2134 .............. 181
A Constant Power "PAN" Control Circuit for Microphone Audio Mixing .... SSM-2134 .................................. 183
Three High-Accuracy RIAA/IEC MC and MM Phono Preamplifiers ............ SSM-2015, 2134 ........................ 185
A Two-Channel Dynamic Filter Noise Reduction System ................................ SSM-2120, 2134 ........................ 190
An Unbalanced Mute Circuit for Audio MixingChannels ............................... SSM-2402,2134 ........................ 192
A Two-Channel Noise Gate ................................................................................... SSM-2120, 2134 ........................ 194
A Precision Sum and Difference (Audio Matrix) Circuit .................................. SSM-2015, 2134, OP-215 ......... 196
A Two-Band Audio .compressor/Limiter ........................................................... SSM-2120, 2134 ........................ 197
A Two-Channel VCA Level (Volume) Control Circuit ...................................... SSM-2122, 2134, OP-215 ......... 200
A High-Performance Compandor for Wireless Audio Systems ...................... SSM-2120, 2134 ........................ 202
An Automatic Microphone Mixer ......................................................................... SSM-2015, 2120,2134 .............. 206
The Morgan Compressor/Limiter ........................................................................ SSM-2014, 2110, MAT-04,
SSM-221O ............................... ~ .. 209
Packaging and Ordering Information ......................................................................................................................................... 216
Other PM! Products for Audio Applications .............................................................................................................................
Digital-to-Analog Converters .....................................................................................................................................
Digital-to-Analog Converter Selection Guide ..........................................................................................................
Operational Amplifiers ..................................................................................... :..........................................................
217
217
219
221
Highlights from PMI's 1990 Data Book ....................................................................................................................................... 223
3
INTRODUCTION
Precision I\1onolithics Inc.
We are proud to present Volume One of PMI's Audio
Handbook. It represents a significant advance over previous
SSM literature and is the result of extensive effort from
numerous PMI employees. Inside you will find 26 data
sheets and 19 application notes. The data sheets for the
original 14 products have been completely rewritten and
reformatted to be more concise and useful. Full data on
seven new products released since the last SSM Product
Guide is included, as is advance information on five new
products which will be introduced soon.
The application notes were written to provide pragmatic
solutions to real-world audio design problems. All were
written by experienced systems designers, not IC
designers. One note, the Morgan Compressor/Limiter
(AN-135), was prepared by industry-renowned designer
Michael Morgan who has spent many years developing
state-of-the-art dynamic range processors.
Precision Monolithics, Inc., through its SSM Audio
Products group, is committed to the ongoing development
of high-performance ICs for applications in all ranges of
audio equipment, including professional, consumer,
autq,~otive, medical, military, and industrial. Our goal is to
proY$~~~ integrated solutions resulting in higher
per- ;"
ce, lower cost, improved quality, and hence
gre (,,,,;,~".",,."~1~ value.
H."
::::;~;.:: '~~~.'~~~"f.r.-.~(~~vo.
;;:. ....-~·:~:~v .•... ~.. ~. .
.
,',;.. ~:~~~~
flt,:::~~a5;*~'<.;j;.;;.,.,.","".~,,"
~:~:~if
.~. ~
...
..
~ "~'.' '
~
........... .
.. ...
.:~
~·'N.~·
..
"';'
~jI'~.
•
''''""''W'~'~~~~~~.,:I :!., .
~.'''''''' "",,1
4
DEFINITIONS
Precision Monolithics Inc.
DEFINITIONS
Class A VCA - The standing (quiescent) current
in the gain core transistors is the maximum output
current the VCA can deliver without resulting in
clipping or a large increase in distortion.
CLIPPING
AVERAGE
SIGNAL LEVEL
Class AB VCA - The gain core standing current is
significantly less than the full output current.
NOISE FLOOR
i
!
DYNAMIC
RANGE
Dynamic Range Processor.- A system whereby
effective dynamic range is increased (such as
noise reduction), or decreased (as with a
compressor/limiter).
A ratio of an output signal to
Decibels (db) - The decibel is a ratio of two
quantities, and therefore is a relative rather than
an absolute measurement. The mathematical
formulas used to calculate dB are as follows:
Equivalent Input Noise (EIN) - A measurement,
in dBm, of noise at the output of a device with
amplifier gain subtracted. The measurement is
performed with a resistor connected across the
input (usually 1500), the value of which must be
specified. The theoretical minimum noise of a
1500 resistor with 20Hz to 20kHz bandwidth at
15°C (59°F) is -131.9dBm.
dB watls = 10 log (p /P 0)
dB yOItS = 20 log (V/Vo)
dB watls provides a ratio for two power levels, P1
and Po. dByolts is the calculation for two voltage
levels, V1 and Vo.
In some instances, however, dBs are expressed
relative to a given reference level. Audio circuits
may refer to one or more of the following relative
dB types:
dBm:
dBu:
dBV:
dBW:
dB SPL:
i
SIGNAL·TO·NOISE
RATIO
Control Feedthrough, or Control
Breakthrough - The amount of a control signal
reaching the output of a VCA with no signal
applied. Control feedthrough can be measured in
terms of current, voltage, or dB.
Control Rejection control voltage.
+
HEADROOM
Frequency Response - Indicates input-to-output
frequency versus amplitude performance. A
typical frequency response specification might be
20Hz to 40kHz, ±3dB. This means that amplitude
will not vary more than 3dB at any frequency
between 20Hz and 40kHz.
OdB is referenced to 1mW
OdBu is referenced to O. 775V RMS
OdBV is referenced to 1VRMS
OdBW is referenced to 1W
for sound pressure level
OdB SPL = 0.0002 dynes/cm 2
(threshold of hearing)
Headroom - The difference, measured in dB,
between clip level and the average signal level.
Input Noise Voltage Density (en) - The RMS
noise voltage in a 1Hz band centered on a
specified frequency.
Dynamic Range - The magnitude, measured in
dB, between clipping and the electronic noise floor
of a device.
5
DEFINITIONS
Intermodulation Distortion (SMPTE) - A peak
voltage measurement of non-harmonic output
frequencies caused by an electronic circuit. using
60Hz and 7kHz tones with a 4:1 ratio.
Pink Noise - Filtered thermal noise to provide flat
frequency response of OdB over a 20Hz to 20kHz
range. Equal noise power per octave.
Resonance - A sympathetic electrical vibration
caused by reactive (capacitive or inductive)
elements which causes peaking in the frequency
. response of a system.
Noise Corner - The frequency below which the
noise floor of an amplifier increases with input(s)
shorted to ground.
Noise Figure - Related to EIN. the noise figure
expresses in dB the incremental noise of a circuit
over the theoretical minimum. For example. a
circuit using a 150Q source impedance with EIN of
-129.5dB has a noise figure of 2.4dB.
Signal-to-Noise Ratio (SNR) - The difference.
measured in dB. between the average signal level
and the electronic noise floor. A statement of
headroom should normally accompany the SNR.
Total Harmonic Distortion - A measurement.
expressed as a percentage. of the RMS harmonic
distortion components added to an audio signal by
an electronic circuit.
Nominal, or Average, Signal Level- The
average electronic line level of program material
passing through an electronic device. measured in
dB with respect to a given reference level.
White Noise - Unaltered thermal noise. Equal
noise power per hertz over the frequency band.
6
SSM-2013
VOLTAGE~O~OLLED
AMPLIFIER
Precision Monolithics Inc.
and outputs, the SSM-2013 is ideal when logarithmic control of
gain is needed. The output current gain or attenuation is controlled by applying a control voltage to the EXPO pin 9. The
amplifier offers wide bandwidth, easy signal summing and .minimum external component count.
FEATURES
• 0.01 % THO Typ
• 0.03% IMD Typ
• 800kHz Unity-Gain Bandwidth
• 12dB Headroom (at Rating)
• 40dB Gain Capability
• 106dB Dynamic Range (17.5 Bits)
• Full ~Iass A Performance
• Mute and Exponential Controls
The SSM-2013 can operate with more than 12dB of headroom
at the rated specifications or be configured for gains as high as
40dB. Inherently low control feedthrough and 2nd harmonic
distortion make trimming unnecessary for most applications. An
extremely wide control range of 11 OdB regulated by a flexible
antilogarithmic control port make this VCA a versatile analog
building block. With 800kHz bandwidth and 94dB SIN ratio at
0.01 % THD, the SSM-2013 provides a useful solution for a variety of signal conditioning needs in applications ranging from
professional audio to analog instrumentation, process controls
and more.
APPLICATIONS
• Compressor/Limiters
• Noise Gates
• Automatic Gain Control
• Noise Reduction Systems
• Telephone Line Interfaces
ORDERING INFORMATION
PIN CONNECTIONS
PACKAGE
PLASTIC
14-PIN
OPERATING
TEMPERATURE
RANGE
SSM2013P
-10'C to +55'C
14-PIN
PLASTlCDIP
(P-Sufflx)
GENERAL DESCRIPTION
The SSM-2013 is a high-performance monolithic Class AVoltage Controlled Amplifier. Operating with current mode inputs
SIMPLIFIED SCHEMATIC
v+
. . . - - - - - - _......- - - -......-_---'2'O+REF
SIGIN 0-"'3'--+-_ _ _ _ _...._-1
t--;-::-oOUT
~~~--I-~~B~
MUTE CAP
12
GND O"'~----,
SUB
+-----_4..-.....--"O-REF
v-
7
7/89, Rev. A
SSM·2013 VOLTAGE·CONTROLLED AMPUFIER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ..................................................... 36Vor :l:18V
Junction Temperature .................................................. +1S0'C
Operating Temperature Range ....................... -1 O'C to +SS'C
Storage Temperature Range ........................ -6S'C to +1S0'C
Maximum Current into any Pin ....................................... 10mA
Lead Temperature Range (Soldering 60 sec) ............... 300'C
PACKAGE TYPE
UNITS
alA (NOTE 1)
14·PIn"Plaslic DIP (P)
47
90
'crw
NOTE:
1. alA Is specified for worsl esse mounling condilions, i.e., alA Is specified for
device In sockel for P·DIP package.
ELECTRICAL CHARACTERISTICS at Vs =:l:1SV and TA =2S'C, unless otherwise noted.
SSM·2013
MIN
TYP
MAX
+12
-7.6
+15
+18
~.2
~.7
Posltiva Supply Currenl
Negativa Supply Currenl
5.4
6.0
8.7
8.7
10.4
11.0
mA
Negallve Supply Bias Resls10r
(Pin 710 Pin 8)
675
900
1170
a
1.0
S.2
PARAMETER
CONDITIONS
Posl1iva Supply Vol1age
Negallve Supply Vol1age (Nole 1)
Expo Inpul Bias
V. = GND (Nole 2)
Expo Control Sensltivl1y
at Pin 9
0.0
Mule On (logIc High)
S.O
Mule Attenuation
1.0
5
15
pA
V
V
dB
-90
(@lkHz,VPIN10=+5V)
V
mV/dB
-10
Mule Off (logic Low)
UNrrs
CurreniGaln
V.=GND
0.90
1.0
1.1
Currenl Output Offset
V.=GND
-7.5
0
+7.5
pA
Oulput Leakage
V.=+600mV
-60
0
+50
nA
..1.2
Max Available Oulpul Currenl
V.=GND,15k(plnSto-V)
Currenl Bandwidth (SdB)
V.=GND
BOO
kHz
Signal Feedthrough
V.=+I.2V
-90
dB
Signal to Noise (20Hz· 20kHz)
(NotesS,4)
V. = GND, No Signal
~
92.5
dB
THD (Untrimmed) .
(Note 4)
V. = GND, liN = 6001lAp.p
0.01
0.06
%
THD (Trimmed)
V. = GND, liN = BOOIIAp.p
0.004
IMD (Untrimmed) SMPTE
(Note 4)
V. = GND, liN = 6001lAp.p
0.03
IMD (Trimmed) SMPTE
V. = GND, liN = 6OO1IAp'e
0.012
NOTES:
1. -Measured at pin 8, pin 7 = -15V.
mA
%
0.12
%
.%
Specifications subject to change; consult latest data sheet.
2. V.Is voltage on pin 9 (VEXPO)'
S. Referred to a 4OO1IAp.p Inpullevel.
4. Parsmeter Is sample lesJed to max IImi1 (0.4% AQL).
8
. 7/89, Rev. A
SSM-2013 VOLTAGE-CONTROLLED AMPLIFIER
+SUPPLY
MUTE
VIIUTE :I: +1V (VCA ·ON-)
V YUTE > +3.0V (YCA ·OFF-)
MIITE MIITECAP
14 10
caUl
12
e,•
SIGNAl. IN
0-11->l1/li'.......--......==="1-"'-1
50PF
r
"':'"
-SUPPLY
FIGURE 1: Typical Connection
THEORY OF OPERATION
The SSM-2013 is a current input/current output device. It is
essentially a current mode amplifier where the output current/
input current transfer function is controlled by a control voltage
applied at the EXPO pin (9). Current mode operation allows
easy adaptation to various voltage ranges at the input, output
and control port. As configured, it offers large attenuation plus
moderate gain capability.
0.3DO
rT----,-----;---,.---,
0.100
H..--.......: - - - - + - - - j - - - - j
0.030 I---~:---~~~-I----I
CHOOSING RIN
.Most applications use the typical connection of Figure 1. In this
configuration, The SSM-2013 will accomodate input currents up
to 1.2mA without significant distortion or clipping. To set the
maximum operating current to 1.2mA, select RIN to equal
Vpeak/1.2mA.
0.010 I----l--~......:==--I----I
0.003 ' - - _ - - - '_ _......._ _- ' -_ _-1
+40
+20
0
-2D
-40
CURRENT GAIN/ATTENUATION @ 12dB HEADROOM Id8}
1kHz (BANDWIDTH ZOkHz)
(600tLA "CONSTANT OUTPUT LEVEL) OdS TO +4Od8
As an example: For a 7Vp-p nominal signal level (:l:3.5V), select
RIN = 12kQ. Here, liN operating is: 3.5V/12k = 300JAA, which
yields 12dB headroom from 1.2mA. In some applications such
as broadcast equipment, 16 - 24dB headroom may be required.
(5ODilAw CONSTANT INPUT LEVEL) DdS TO -4DdB
FIGURE 2
Selecting :l:300JAA nominal operating current yields 12dB headroom. Figure 2 shows the IMD/THD (Intermodulation and Total
Harmonic Distortion) characteristics of the SSM-2013 at this
300JAA or 600JAA peak-to-peak operating level.
trol pin as described in the next section. Figure 2 shows how
IMD/THD performance degrades with current gain and attenuation. Note also that distortion in the SSM-2013 is nearly all 2nd
harmonic. From a sonic standpoint, this is much less objectionable than other types of distortion.
Operation at higher input currents will increase distortion effects
whereas operation at lower. currents will improve distortion but
decrease the SIN ratio. For exam ie, operation with 20dB headroom versus 12dB will improve the relative effects of IMD/THD
shown in Figure 2 by 2.5 times. For 20dB headroom, use
:I: 120JAA nominal operating input current. At this level, the signal-to-noise ratio will be B6dB.
For best performance, choose CIN and RIN for a cutoff frequency
below the audio band. CIN will block DC offsets from previous
stages.
OUTPUT SECTION
When establishing circuit gain or attenuation, it is important to
consider the tradeoffs between gain/attenuation for the SSM2013 versus the gain of the Ol!tput amplifier/current to voltage
The SSM-2013 is capable of 40dB gain and as much as -95dB
attenuation. Gain or attenuation levels are set by the EXPO con-
9
7/89, Rev. A
SSM·2013 VOLTAGEoCONTROLLED AMPUFIER
converter. Operating the SSM·2013 with current gain above 20
or 30dB increases distortion as shown in Figure 2. Gain in the
output amplifier amplifies the VCA noise. This will directly in·
crease the equivalent VCA noise floor by the amplifier gain. A
compromise within these constraints will determine the best
tradeoff between SSM·2013 current gain and the amplifier gain.
Figure 3 shows how output noise increases as current gain in·
creases.
i
~
~
!;
....
200
300
«10
~
-30
'-
'-
\
1\
10kQ
2.2kO
.Olen
•.7kO
V.
'1\
Vz
"1'0.. ..... "'"
-110
....
..
-2.
FIGURE 4: Circuit Gain/Attenuation vs. VEXPO
~ _.00
-.20
-400 -300 -200 -100
.....
..
-so
••
~
..,. \.
.;s
30
Ii"
CONTROL PIN EXPO
The control port EXPO (pin 9) is a high impedance input with an
exponential control sensitivity of-l dB/1 OmVor-l OmV/dB. The
overall control range is+40dBto -95dB. This pin is easily adapt·
able to any control voltage range by selecting the RI and R2
-
..
..
'" '"
+20
-20
-40
-10
CURRENT QAlMlAnENUAT1QN (dB)
HaBE BANDWIDTH (20Hz ~-Hz)
(REFERREDT0604LAp-pINPUTSlQNAL
v.
'Olen
r*-oIV'I""--'_-o TO PIN 0
-80
.kO
+1OdBN
(INPUT CONTROL SENSITIVITY)
12dBOFHEADROOM)
FIGURE 3
FIGURE 5: Control Summer with Improved Linearity over
Wider Control Range
divider appropriately. Note the negative control relationship
where positive voltages at pin 9 result in signal attenuation
whereas negative voltages yield gain. The control pin is accu·
rate to within ±1.5dB over a ±36dB range.
A selectable MUTE CAP connected between pin 12 and ground
determines the controlled turn onlturn off rate. The recom·
mended IIlF mute cap and internal 10kQ impedance gives a
1Oms time constant. This transition timing is considered quick
without being too abrupt or ·poppy."
Thetransfer characteristics forthe control pin is shown in Figure
4. Note the dotted line showing an optional improvement in gain
accuracy. To achieve this improved transfer characteristic, reo
fertothe circuitof Figure 5. As the recommended circuitforcon·
trol summing applications, this technique offers a significant im·
provement in linearity over a wider control voltage range:
To disable the muting function, simply ground pin 10.
APPLICATIONS INFORMATION
The control port sensitivity has a -3300ppm1"C temperature
coefficient. To compensate for this drift, use a +3300ppm1"C
tempsistor* in place of RI shown in Figure 1.
OUTPUT AMPLIFIER
Note the importance of including COUT in parallel with ROUT to
ensure stability under all signal and output loading conditions. A
corner frequency of 300kHz for the ROUT' COUT combination is
sufficient, but a lower frequency may also be chosen to limit
noise output the audio band. This, however will result in a slower
transient response.
MUTING FUNCTION
The mute circuit turns the device on or off independent of the
control pin EXPO. Muting is activated when the MUTE (pin 10) is
raised above 3.0V and is compatible up to 15V. Muting is off
when MUTE is below 1.0V.
* RCD Components, Inc. Part Number LP1/4, 3301 Bedford Street, Manchester, NH U.S.A., (603) 669-0054, Telex 943512
10
7/89, Rev. A
SSM-2013 VOLTAGE-CONTROLLED AMPLIFIER
COMPENSATION
To compensate, connect a 50pF capacitor from pin 11 (COMP)
to GNO as shown in the typical connection.
CONTROL FEEDTHROUGH TRIMMING
Control feedthrough is defined as the portion of the control signal fed to the output in the absence of an input signal. A single
shunt resistor across pins 2 and 6 will reduce both control
feedthrough and noise (see Figure 6). Values from 3.3k!l to
5.4k!l offer an improvement in control feedthrough from 20dB to
10dB, respectively.
ON-BOARD REFERENCE
An on-chip zener diode helps establish the -8V available at the
SUB output (pin 8). This is a general purpose reference that can
be used to introduce OC offsets.
f
3.31<0
TO
S.4kO
6
FIGURE 6
FIGURE7
This trim will tradeoff an increase in THO by roughly 3 to 5 times.
THO increases slightly more using a lower resistor value. With
3.3k!l, the worst case is about 0.4% over gain and attenuation.
By comparison, THO ranges from 0.05% to 0.1 % with no shunt
resistor.
BREADBOARDING THE SSM-2013
A typical connection identical to Figure 1 and redrawn for breadboarding purposes is shown in Figure 8.
MEASURING NOISE
When measuring audio noise in the SSM-2013, bandwidth
should be limited to 20kHz to 30kHz. This is due to the presence
of broadband noise which is caused by a zero at 600kHz. The
zero results from the 5000pF-47!l network at the input. Beyond
30kHz, the noise floor increases at approximately 6dB per octave from 45kHz to 600kHz where it rolls off ..
TRIMMING DISTORTION
The SSM-2013 has very good distortion, offset and control
feedthrough at unity current gain. For applications requiring
over 1OdB to 20dB gain, trimming allows the best overall distortion versus gain.
Distortion Trim Procedure for High Gain Applications:
1. Apply voltage at pin 9 corresponding to maximum current
gain.
2. Set input level so output is just below clipping.
3. Adjust trimming per Figure 7 until distortion is at a minimum.
500CpF
RIH
CIH
~-NI/'--lf-o SIG IN
470
'4
'3
)-"2=--_...,+
5SM'-2013
11
~'''''
VUUTE ~+1Y(VCA "ON")
YWUTE > +3.OV (VCA "OFF1
f!'''-O- I - - - - - - - - - < l f.lUTE
OUT
v-
SOpF
R,.s: lkn
FIGURE 8: Typical Connection for Breadboarding
11
7/89, Rev_ A
SSM-2014
VOLTAGE-CON1ROLLED
AMPLIFIER/OVCE
Precision Monolithics Inc.
FEATURES
DESCRIPTION
• Wide Dynamic Range •.•...•.. ,..........•...... 116dB (Class AB)
.............................. 104dB (Class A)
• 12MHz Effective Gain-Bandwidth Product
• 100dB Open-Loop Gain
• 0.01% THD Class A (Any Gain/Signal) @ = 10dBVIN/OUT
• Minimum External Component Count
• No Trimming in Many Applications
• Low Cost
The SSM-2014 is an extremely flexible VCA building block that
rivals the best monolithic VCAs while approaching the performance of modular devices. This versatile device acts as a VCA or
OVCE (Operational Voltage-Controlled Element) and has inputs and outputs that can operate either in the current or voltage
domain. To optimize performance at different signal levels, the
SSM-2014 features programmable Class A or Class AS operation. This feature, along with the many configurations possible
for operation make the SSM-2014 a unique and powerful signal
processing tool. The device can be configured as a VCA or VCP
(Voltage-Controlled Panner) and can replace a standard veA
and two or more operational amplifiers. Operation as a standard
VCA provides up to SOdS gain and excellent specifications at
any signal level. As a result, the SSM-2014 is an ideal choice for
any system requiring remote or automatic control of gain or volume.
UNIQUE FEATURES
•
•
•
•
•
•
•
•
•
Voltage Selectable Class A or AB Operation
Low Distortion vs. Frequency
No Active Components Needed
Operates at ±15V
Low Modulation Noise
Complementary Current Outputs
Combines Op Amp and VCA Features
Fully Buffered Control Port
High and Low (Balanced) Impedance Inputs
BLOCK DIAGRAM
APPLICATIONS
•
•
•
•
•
•
•
•
Voltage-Controlled Amplifiers
Voltage-Controlled Preamplifiers
Voltage-Controlled Panners
Voltage-Controlled Equalizers
Voltage-Controlled Oscillators
Console Automation Systems
Dynamics Processors
Fader Automation
ORDERING INFORMATION
PACKAGE
PLASTIC
16-PIN
OPERATING
TEMPERATURE
RANGE
SSM2014P
PIN CONNECTIONS
16-PIN
PLASTIC DIP
(P-Suffix)
Manufactured under the following U.S. Patents: 4,471,320 and 4, 560, 947. Other Patents pending. Mask work protected under the Semiconductor Chip Protection Act of 1983.
12
2/90, Rev. A 1
SSM-2014 VOLTAGE-CONTROLLED AMPLIFIER/OVCE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ..................................................... 36V or :l:18V
Junction Temperature .................................................. + 150·C
Operating Temperature Range ....................... -1 D·C to +55·C
Storage Temperature Range ......................... -65·C to +150·C
Maximum Current Into Any Pin ....................................... 10mA
Lead Temperature Range (Soldering, 60 sec) ............ +300·C
PACKAGE TYPE
e lA (Note 1)
16-Pin Plastic DIP (P)
90
e lc
UNITS
47
·C/W
NOTE:
1. alA Is specified for worst case mounting conditions, i.e., alA is specified for
device in socket for P-DIP package.
ELECTRICAL CHARACTERISTICS at V S = :l:15V and TA = :l:25·C, unless otherwise specified.
SSM-2014
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
100
300
nA
15
30
nA
0.5
2
INPUT AMPLIFIER
Bias Current
Input Offset Current
Input Offset Voltage
Input Impedance
Equivalent Input Noise
@lkHz
18
Common-Mode Range
Open-Loop Gain
75
Effective Gain BW Product
VCA Configuration
VCP Configuration
Slew Rate
VCA Configuration
mV
Me
0.5
nV/-/Hz
+13,-13
V
100
V/mV
12
.5
MHz
6
V/J1.S
Supply Current - Positive
7.5
9
mA
Supply Current - Negative
10
12
mA
10
20
mV
OUTPUT AMPLIFIERS
Offset Voltage
Minimum Load Resistor
For Full Output Swing
10
Output Voltage Swing
Noise Residual
20kHz Bandwidth
ke
9
~13.5
V
8
J1.V
CONTROL PORT
Bias Current
150
300
Input Impedance
Gain Constant
nA
Me
Ratio of Outputs
Gain Constant
Temperature Coefficient
Gain Linearity
Control Feedthrough (Trimmed)
Class A
Class AB
Intermediate
100Hz Sine Wave Applied
to Control Port Causing
-{30dB to +20dB of Gain
Control Feedthrough (Untrimmed)
Class A
Class AB (Note 1)
Intermediate (Note 1)
100Hz Sine Wave Applied
to Control Port Causing
-{30dB to +20dB of Gain
Off Isolation
@,lkHz
mY/dB
-{3300
ppm/·C
0.5
%
2
0.5
mV
25
5
15
100
13
-{30
105
75
15
45
mV
dB
2190, Rev_A1
SSM-2014 VOLTAGE-CONTROLLED AMPLIFIER/OVCE
ELECTRICAL CHARACTERISTICS at Vs = ±15V and TA = ±25°C, unless otherwise specified. Continued
SSM-2014
PARAMETER
CONDITIONS
Channel Specifications
Noise· Class A (Note 2)
Noise· Class AB (Note 2)
Noise· Intermediate (Note 2)
RplN 12 = 33kn. 20kHz BW
RplN 12 = 330kn. 20kHz BW
RplN 12 = 43kn. 20kHz BW
THO· A @ Av - OdB (Note 3)
THO· A @Av = ±20dB (Note 3)
THO· AB @ Av = OdB (Note 3)
THO· AB @ Av = ±2OdB (Note 3)
THO· Intermediate @ Av = OdB (Note 3)
THO· Intermediate @ Av - ±2OdB (Note 3)
RplN
RplN
RplN
RplN
RplN
12
12
MIN
= 33kn
= 33kn
12 = 330kn
12
= 330kn
12 = 43kn
RplN 12 - 43kn
TYP
MAX
UNITS
-85
-95
-88
0.005
0.02
0.02
0.06
0.01
0.03
-81
-92
-85
0.02
0.04
0.05
0.12
0.03
0.06
dBV
dBV
dBV
%
%
%
%
%
%
NOTES:
1. Symmetry trim only.
2. Parameler sample lollesled 10 maximum limils.
3. VIN andlor VOUT = +1 OdBV. Specifications may be subject to change without
THEORY OF OPERATION
SELECTING CLASS OF OPERATION
The class of operation is set by the cu rrent into pin 12. A resistor
connected between pin 12 and V+ can be used to establish this
current. Table 1 indicates the recommended resistor values and
typical performance tradeoffs for various classes of operation.
notice.
The simplified schematic shows that the SSM-2014 is fundamentally a controllable gain block that operates in the current or
voltage mode. The outputs are the product of an input signal and
a control signal. These outputs along with differential inputs, a
control port, and selectable bias for Class Aor AB operation give
the SSM-2014 unparalleled flexibility. It is important to note,
however, that actual implementation of any given function can
only be realized by applying feedback as shown in the applications sections.
Class A operation is preferred for its distortion performance,
particularly at high signal levels and over gain and attenuation.
Distortion in Class A is nearly pure second harmonic, which from
a sonic standpoint, is much less objectionable than other types.
Class AB operation provides significantly better control
feedthrough performance and lower noise which is important at
low signal levels.
INPUT SECTION
For most applications, input signals should be coupled by a DC
blocking capacitor to prevent errors from previous stages from
affecting control feedthrough. The input section consists of an
opamp with differential inputs and a gain-variable compensation scheme controlled by the gain control port. The variable
compensation makes it possible to maintain a bandwidth in
excess of 120kHz over the gain range of ±40dB.
DYNAMICALLY SETTING CLASS OF OPERATION
In order to realize the virtues of both classes of operation, it is
possible to use a level detector to sense the input signal and
dynamically change the VCA from Class AB at lower signal levels to Class A for signals above this (sometimes referred to as
"sliding bias"). Low signal levels are usually considered to be
less than +4dBV. A time constant in the range of 10 to 25 milliseconds should be included in the level detectorto both smooth
the signal and to subjectively eliminate the resulting noise floor
modulation and output offset shift. Both of these effects are
small compared to the signal level at which the class of operation changes.
The output of the op amp faces a current splitter with a variable
bias point controlled by pin 12. This bias point establishes the
quiescent current in the gain core which sets the class of operation (Class A. AB or INT). The class of operation selected affects
the noise, distortion, and control feedthrough performance.
IMPORTANT NOTE
A current between 40 to 500J.LA must be sourced into pin 12 for
proper operation of the device. Without such a current, the output signal will appear half-wave rectified.
TABLE 1
CLASS
RSET
Noise
THD@Av=OdB
THO @ Av = ±20dB
THO Type
. Trimmed Control Feedthrough
A
33kn
-84dBV
0.005
0.02
Pure 2nd
2mV
AB
330kn
-95dBV
0.02
0.06
Mostly3rd
500~LV
INTERMEDIATE
CONDITION
43kn
-88dBV
0.010'
0.030'
2nd'
1mV
Vs = ±15V
20kHz Bandwidth
+10dBVINIOUT@ 1kHz
+ 1OdBVINIOUT @ 1kHz
-30dB ::; Gain::; +20dB
• For intermediate operation near unity-gain, distortion will increase and become mostly third harmonic for levels above + 14dBV1NIOUT.
14
SSM-2014 VOLTAGE-CONTROLLED AMPLIFIER/OVCE
v+
270kQ (R SET)
30kg
v+
12VZENER
30kQ
~-.f\N'---------
I
I
I
SIGNALer .... _
OUTPUT
(OPTIONAL)
3Ok"
180ke IR SET)
15ke
27kD
>-......./11'>1'--<_-0 PIN 12
FOR RREF= 27kDANDVs =:t15Y
VIN < +5dBV CLASS AD OPERATION
VIN > +sdBV CLASS A OPERATION
"'3."'k",....>-_ _ _ _ _....I
FIGURE 1: SSM-2014 Operating Class Control Circuit (Sliding Bias)
Figure 1 shows a typical level detector circuit which senses the
input and/or output signal level and changes the SSM-2014 from
Class AB to A when the signal exceeds +4dBV (RREF =270kQ).
Sensing the output signal is important in high-gain applications
such as the voltage-controlled preamp. This circuit is a full-wave
rectifier followed by an integrator which provides a fast, smooth
transition. The 12V zener clamp diode in the feedback loop
improves ripple rejection by maintaining the op amp output in its
linear operating range. The output resistor network provides the
program current into pin 12 for Class A or AB operation when the
integrator output is high (+ 12V) or low (-O.6V) respectively. The
program current is 500/lA when the device operates in Class A
(high) and 40l!A when operating in Class AB (low).
OUTPUT SECTION
The SSM-2014 has three current outputs and two voltage outputs. The current outputs can deliver at least 675/lA signal current when operating on :t15V supplies. Feedback resistors for
the internal or external current-to-voltage converter op amps
should not be lower than 20kQ with :t15V supplies. In normal
operation, the current outputs are virtual grounds. The SSM2014 block diagram shows that amplifiers Al and A2 act as current mirrors that maintain the +CUR 1 • Gto ground potentiai. Amplifiers A3 and A4 are used as current-to-voltage converters and
maintain -CURG and -CUR 1 • Gat ground. If external op amps
are used forthis purpose, the on-board op amps can be disabled
by connecting their outputs to the negative supply as shown in
Figure 6. When used, the on-board op amps have current outputs and can sink in excess of 1OmA and source a minimum of
1.5mA.
CONTROL SECTION
The control sensitivity of the control port is-30mV/dB at pin 11.
A simple resistor divider is ordinarily used to scale the control
voltage source range to the desired voltage applied at the control port. This pin can draw as much as 300nA of bias current so
the impedance ofthe divider to ground should be kept low. 10kQ
or less is recommended to keep gain error resulting from the
voltage drop to a minimum. The graph of Figure 2 shows the
control voltage transfer characteristic by plotting VCONTROL (at
pin 11) vs. gain/attenuation over different temperatures.
APPLICATIONS
The SSM-2014 can be used in a variety of ways. The most
straightforward and perhaps the most often used configuration
is that of a simple yeA. Here, the minimum VCA uses its own
When using the control pins, care must be taken to eliminate
coupling to signal paths, particularly when using higher impedances.
The control port has a -3300ppm/oC temperature coefficient as
do all dBN VCAs. To compensate for this drift in automation
systems, use a single tempsistor* with a +3300ppmrC drift to
replace the reference current set resistor in the system DAC.
Temperature compensation can also be accomplished by using
a tempsistor connected to the control pin to ground as part ofthe
control input attenuator. This will improve tempco performance
by five to ten times.
GAIN/ATTENUATION (dB)
FIGURE 2: VCONTROL at Pin 11 vs.Gain/Attenuation
• RCD Components Inc., Manchester, N.H., TEL: (603) 869~OO54 TLX: 943512
15
2190,Rev_A1
SSM-2014 VOLTAGE-CONTROLLED AMPUFIER/OVCE
.CUR,-G 1
SAL 15 100kO
'00""
-CUA,.O 4
V,.G '6
V-
-CUR G 3
v+
V.
SpF
,.
VOUT
100D
300PF
J
J,'300 PF
12 MODE
6 +IN
7 -I
*
47pF
~ o.1"F
'--"-1==-----'
--=---------'
O-MI'-f-"'-I'!-'v...........- - - - - -a-.D
*IN.MAOERMAHruU DIODES.
OPTIONAL DIODES WLL PREVENT
THE INPUTS FAOM BEING OVERDRIVEN
BY TRANSIENTS WMEN VERY FAST
LAROE SIGNALS ARE APPUED.
'3
FIGURE 3a: Simple VCA
on-board op amps and using the configuration of Figures 3a and
3b, performs the basic VCA function of logarithmic voltage-controlled gain. In this application, the VCA is fixed in Class A or AB
operation, whichever optimizes the tradeoff between noise and
distortion.
2.211D
....
V~Lo-~~----~~
n.
"":;'----.,....--0 v...
Otherfunctions are easily implemented using the SSM-2014 as
an operational VOltage-controlled element or "core" for other
VCA configurations, including voltage-controlled panners and
voltage-controlled preamplifiers. These applications will be described in the sections to follow.
.pF
'J.
SIMPLIFIED VeA OPERATION
The SSM-2014, when configured as a simple VCA, is a selfcontained minimum component VCA with single-ended or differential inputs and a voltage output. The basic VCA configuration is shown in Figures 3a and 3b. Gain of up to 50dB is set by
a voltage applied to the control pin. Current feedback from
+CUR,_G to the -INPUT and -CUR,_Gto the +INPUT creates
differential virtual ground inputs. Input signals may be applied
through blocking capacitors and 22kQ resistors to pins 6 or 7
'000
300pF
*OPTIONAL DIODES WILL PREVENT THE INPUTS
FROM BEING OVERDRIVEN BVTRANSIENTS
WHEN VERY FAST LAROE SIONAlS ARE "PPWED.
FIGURE 3b: Block Diagram of Simple VCA
16
2190, Rev_A1
SSM-2014 VOLTAGE-CONTROLLED AMPLIFIER/OVCE
(+IN and -IN). For single-ended inverting or non inverting operation, connect the unused input through 22kQ to ground for best
performance. Also, when large common-mode signals are present in differential operation, choose Class A operation.
THO + N(%)
vs FREQUENCY (Hz)
Figure 4A shows typical distortion measurements using this circuit over gain and attenuation at 1kHz. (Figures 4b, 4c and 4d
show THO vs. frequency for Class A and AB operation using
+10dBV input.) These curves show THO at gain settings of
+10dB, OdB, and -10dB, respectively. Figure 4b is the worst
case showing the amplifier near clipping.
.
i!:
z
~
The noise performance ofthe device with shorted inputs measured over a 20kHz bandwidth is seen in Figure 5. Three cases
are shown: full Class A, Class AB, and Intermediate bias between the two extremes.
1••
'"
••
".
20
-30
-20
-10
0
+10
.30
10k
SDk
THO+ N(%)
vs FREQUENCY (Hz)
..!
Od.~,".
+ZD
Ik
FIGURE 4c: THO at OdB Gain
.
"
i!z
"
0.0'
-40
100
FREQUENCY (Hz)
. ,
r- l"'-*. · ;' V ......
··.
~ .. V
"cr."
0.03
O.OODS
.---,.--
0.'
0.0'
Q.DOI~~I~!
t:
The tests for Figures 4a, 4c and 4d were made with a singleended 1kHz source driving the input and/or output to a signal
level of + 1OdBV regardless of gain or attenuation. This is 10dB
below clipping.
O~
0.'
l1li
0.' . .
j!:O.O'mR
+40
GAIN IdBI
*INTERMEDIATE SAME AS CLASS A AT THIS LEVEL.
o.OO'~HI~~~
..
0.0005 t;
FIGURE 4a: VCA THO Performance Curves
.
Ik
10k
SDk
FREQUENCY (Hz)
FIGURE 4d:' THO at-10dB Attenuation
THO + N(%)
vs FREQUENCY (Hz)
~
100
0.,_
"
.j!: 0.0'
0.001
..
'00
.
,
10k
sOk
FREQUENCY (Hz)
FIGURE 4b: THOat+tOdB Gain (+10dBV,N)
FIGURE 5: VCA Noisl{I vs. Gain (20kHz) Bandwidth
17
2190, Rev. A1
SSM-2014 VOLTAGE-CONTROLLED AMPUFIER/OVCE
IOpF
v.
FIGURE 6: Outboard OVCE
COMPENSATION
To ensure stability when driving some distortion analyzers, it
was found necessary to add a 300pF capacitor between pin 12
and GND in Figure 3a as shown. This is because high-gain
preamp and AGC circuits in such measuring systems can cause
ground loop problems which can lead to instability and false
distortion readings. The output can drive capacitive loads of up
to 1OOpF with little or no degradation in performance.
OVCE OPERATION
The complete SSM-2014 is a combination of a VCA structure
and an operational amplifier. To simplify analysis, assume the
op amp portion has infinite gain. (The finite gain limitations of the
OVCE cause substantially the same problems as are found with
conventional op amps and can be handled and appreciated in
the same way.) This means we can apply the same rules used
for the ideal op amp.
BASIC OVCE CONNECTIONS
Figure 6 shows the SSM-2014 as an operational voltage-controlled element with outboard current-to-voltage converter amplifiers. This diagram shows the SSM-2014 with uncommitted
inputs and outputs and forms only the core of the application circuits to follow. Feedback Is required to actually implement any
given function. Note that Figure 6 uses an external 5532 op amp
and has somewhat better output drive, distortion and noise performance. Pins 14 and 16 are tied to V- which disables the onboard op amps. The outputs used for feedback connections are
now at the outputs of the external op amps and are now called
VG and V,-G' Use of a 5532 is recommended since use of a
TL072 would requirethatthe SSM-2014 be somewhat overcompensated resulting in reduced bandwidth.
Since this device is intended for use only with negative feedback, the Infinite gain assumption yields the usual contraint that
in any closed-loop configuration, the voltage between the + and
- inputs is zero. This is the same assumption that is typical of op
amps where both inputs are forced to be at the same potential.
In addition to this, we have the VCA constraint, that the ratio of
the VG and V,.G outputs are always e-av e , where "a" is about 4
at room temperature, regardless of the configuration.
These two assumptions make calculation of the transfer characteristics simple for any configuration. Note that the VCAlVCP
connections of Figures 7, 8, 9 and 12 resemble non-voltagecontrolled functions implemented with op amps.
18
2190, Rev. A1
SSM-2014 VOLTAGE-CONTROLLED AMPUFIER/OVCE
2.21<0
2.21<0
VCOHTRO<.
,1<0
/ " " - - - 0 va=YIH .....vo
Vo
v.. 0----1
V"
V,-a
22kO
221<0
FIGURE 7: Noninverting VCA
FIGURE 9: SSM-2014 or OVCE as a Noninverting VoltageControlled "Panning" Circuit
VCAIVCP FEEDBACK CONNECTIONS
For the following examples, the core configuration of Figure 6
will be used. First, examine the feedback connection forthe noninverting VCA of Figure 7. Here, the op amp assumption guarantees that the V'.G output exactly follows the input, while the
VG output tracks the input with a gain of e·ave. This means that
this circuit simultaneously implements a voltage follower and a
true exponential VCA.
says that the average of the two outputs is always equal to the
input. Because the ratio of the two outputs can be made to cover
many orders of magnitude, it is possible to "pan" the input signal
from the V'.G output to the VG output through the use of the
control voltage. Setting Veto zero is the "center" position, since
the ratio is unity there. Positive control voltages will increase V'.G
and attenuate the VG output. Conversely, setting Vc to negative
voltages will increase VG and attenuate V'.G.
Grounding the non inverting input and applying feedback as
shown in Figure 8 yields the inverting VCA amplifier. Outputs are
now -VIN and -VIN (e· aVe ).
Noise and distortion performance are completely complementary where noise is lower and THD is higher in Class AB and the
reverse for Class A. Figures 10 and 11 show the distortion and
noise at the VGor VOUT (right) output only, where V'.G and VOUT
(left) are symmetrical. Figure 11 shows noise vs. gain in Class
AB bias only.
COMPENSATION
To ensure stability for VCA operation as described above, a capacitor greater than or equal to 220pF should be placed between pin 5 (COMP 1) and pin 8 (COMP 2). Pin 9 (COMP 3)
should be left open.
22kO
........
0.03
2.21<0
VCOHTRO<.
o--../W'-_-.J
0.01
,kO
.........
FIGURE 8: Inverting VCA
...--.
AD
"or INT
'.'.
'.
""
"'\
..
~\\
..
:'
'"
-'0
r\
o
+.
ONE CHANNEL (Va ORY1oQ)VCPQAlNdB
PANNING CIRCUIT
Figure 9 shows the SSM-2014 used as a voltage-controlled
panning circuit. This is accomplished by feeding back signals
from both the V'.G and VGoutputs simultaneously. In this circuit,
the signal at the inverting input is the average of the two outputs
dueto the balanced feedback (identical resistors). The assumption that the inputs are held to the same potential, therefore,
FIGURE 10: VCP Typical THO Performance Curves (1kHz
+10dB Vc/Vf-a) Noninverting
19
2/90, Rev. A 1
SSM-2014 VOLTAGE-CONTROLLED AMPLIFIER/OVCE
.....
-0.
-
-100
-110
-24
_18
-12
-6
GAIN (d8)
.,....,V
'------..w---+--o
..
V,oC
FIGURE 12: VCA as an Inverting Voltage-Controlled
"Panning" Circuit
FIGURE 11: Noise Performance of Circuit of Figure 10
(20kHz Bandwidth) Noninverting
2.2kn
In Class AB operation at a maximumgain of unity, the variable
compensation is not required and gain-bandwidth product is not
of concern. Slew rate is 6V/Ilsforthe inverting configuration and
approximately 3V/!ls forthe non inverting connection (Figure 9).
Control feedthrough for the voltage-controlled panner is
50011 Vp·p with a 100Hz sine wave varying the gain from maximum to -40dB.
..._---0
~:rP't~
Vour
0---;
V,oC
This panning circuit may be configured for inverting or noninverting operation in the same way that any operational amplifier
circuit might be used. Grounding the +input and feeding the
signal inputthrough a resistor to the- input creates the inverting
analogy to this example (Figure 12). The SSM-2014 is noteworthy for truly exceptional noise and distortion performance for the
VCP, one of its unique uses.
LOWZ
INPUT
COMPENSATION
For best stability when used in panning circuits, connect a capacitor greater than or equal to 330pF across pin 5 (CaMP 1)
and pin 8 (CaMP 2) while grounding pin 3 (CaMP 3).
.o--+---~~--~
AsIAS =43kn
COMP 3 (Pin Q) OPEN
1
FORVc=OVANDf'2:. - 211:R 1 C
VeA PREAMPLIFIER
A simple variation of the above VCA example is given in Figure
13 which shows the SSM-2014 configured as a full VCA preamp
accepting both high and low impedance inputs simultaneously.
Here, the feedback from the V'_G output to the - input causes
the V'_G output to follow the input with a fixed gain, which is
about 10 (20dB) inband. (Inband isthe portion of the input signal
at frequencies above the R" C, cutoff.) This behaves in exactly
the same manner as the output of a noninverting operational
amplifier. At the same time, however, the VG output is voltagecontrolled with a gain of e-ave times the V,.G output or 10e·ave
times the input inband signal.
FIGURE 13: Voltage-Controlled Preamplifier Accepts Both
High and Balanced Low Impedance Inputs
20
2190, Rev_ A1
SSM-2014 VOLTAGE-CONTROLLED AMPLIFIER/OVCE
Performance curves for the VCA preamp are shown in Figures
14 and 15. Measurements for this data were taken with a signal
applied to the high impedance input using the INT (Intermediate) bias setting. Performance in Class A or AS will vary from the
INT setting in practically the same ''lay as for the VCA. Distortion
measurements were made by configuring the VCA to drive one
or both outputs to +1OdSV with a 1kHz sine wave applied. Auxiliary specifications are quite good for the device operating in
this configuration. The effective gain-bandwidth product was
measured to be 12MHz with an accompanying slew rate of
about 1OV/'tAs. The control feedthrough was measured at 3mV
peak-to-peak, with a 100Hz sine wave varying gain from +40dB
to OdB. Tests were also conducted with a balanced 600r.! input
using more than 70dB of gain which showed essentially the
same noise and distortion.
AUTOMATIC GAIN CONTROL
An automatic gain control circuit can easily be implemented
using the SSM-2014 and DAC-08 8-bit DAC. In this type of
application, a DAC-08 could be digitally controlled to set the
control voltage for the desired gain or attenuation with the SSM2014 configured as a VCA or voltage-controlled preamplifier.
TRIMMING THE SSM-2014
Two TRIMPOTs" are shown in each circuit. Figure 16 shows
the basic scheme for trimming symmetry and offset. Both trims
affect offset and control feedthrough while the symmetry trim
also affects distortion. The waveform symmetry trim is mandatory for Class AB operation, but may not be required for less critical Class A-only operation. Offset trimming is needed when it is
necessary to improve the untri[Tlmed control feedthrough performance in either Class A or AB operation.
TRIM PROCEDURE
1. Symmetry trim - perform first if used. Apply a 1kHz sine wave
at + 1OdBV with the amplifier set at unity gain.
0.1
2. Adjust symmetry trim to minimize distortion.
~
0.05
~
-
V
V
3. Ground input signal and apply a 100Hz sine wave to the control port. The sine wave should have its high and low peaks
correspond to the highest gain and 30dB attenuation, respectively.
---
4. Adjust the offset trim to null control feedthrough.
5. Further reduction of control feedthrough can be achieved by
a slight readjustment of the symmetry trim when in Class A
operation. (This is not useful for Class AB.)
0.01
-40
-10
10
20
30
40
50
6. When a level detector switching scheme is used to select
Class A and Class AB operation, choose the Class AB symmetry null point. This is the best choice since control
feedthrough null points for Class A and Class AB operation
do not exactly coincide.
60
GAIN (dB)
FIGURE 14: Preamp THO Performance vs. Gain
As noted in the input section, the DC blocking capacitor in series
with the input will prevent offsets of previous stages from affecting the control feedthrough performance.
-50
II
-60
~
-70
~
z
w
-80
/
-90
_/
V
V
V
V.
2
4.7MD
100kn
100ke
15
/
-10
100kc
10
v-
-100
-20
cr-.tV'v'--+
10
20
30
40
50
60
GAIN (dB)
OFFSET
TRIM
FIGURE 15: Preamp Noise Performance VS. Gain (20kHz
Bandwidth)
FIGURE 16: Symmetry and Offset Trimming Scheme
21
2190, Rev. A1
SSM·2014 VOLTAGE·CONTROLLED AMPLIFIER/OVCE
For many applications such as panning and equalizer circuits,
control feedthrough trimming should not be required. Control
settings for these circuits are usually established at setup and
varied infrequently. In these types of circuits, audible control
feedthrough can also be suppressed by inserting a 10 to 20ms
time constant in the control signal path.
FADER AUTOMATION SYSTEMS
The SSM·2014 lends itself well to fader automation applica·
tions. The circuit of Figures 3a and 3b is the most common
where simple gain control would be used to amplify or attenuate
signals in multi·channel systems. As an example, an SSM·2300
a·channel multiplexed sample·and·hold could be used along
with a PM· 7541 12·bit DAC to control the gain or attenuation of
systems with a multiple of eight channels. Here, the DAC is used
to set any given VCA control voltage port for gain or attenuation
while the SSM·2300 captures and distributes the appropriate
control voltage to the appropriate VCA in a time multiplexed
system. With each channel updated by the time distributed
SSM·2300 output, a real time fader automation system can be
implemented.
SELF·CONTAINED OVCE
Figure 17 shows a self·contained OVCE building block. It is
used as the core element for VCAs and panning circuits in a
similar fashion to the out· board OVCE element of Figure 6.
Unlike Figure 6, however, this configuration utilizes the on·
board op amps and needs only the SSM·2014 for the active
electronics. This circuit tends to be more sensitive to oscillation
than other configurations when prototyped on typical proto
boards or even copper·clad vector boards. Forthis reason, use
of the SSM·2014 evaluation board is recommended.
DYNAMIC RANGE PROCESSORS
Similar to applications described for the SSM.2120, the SSM·
2014 can be used in conjunction with the SSM·211 0 level detec·
tor to implement virtually any dynamic range processing func·
tion. These may include noise reduction systems, compressor/
limiters, noise gates, psychoacoustic enhancers and automatic
microphone mixers.
···:f.~.r~'V::Ii'OT"-~-~~-NJ:""'-~~---"'v"
.
SSM·2014 EVALUATION BOARD
An evaluation PCB for the SSM·2014 is available free of charge
to qualified OEMs. It permits easy evaluation of the sliding bias
control circuit (Figure 1), simple VCA (Figures 3a, 3b), outboard
OVCE (Figure 6), and the self·contained OVCE (Figure 17). In
orderto avoid confusion, please use the PCB marked "Rev 3,1/
90" for proper reference to the appropriate circuits. Contact your
local PM I sales office for details.
-1SV
SYMMETRY
TRIM
'-~~~~~-J'~'~~-~~~~-o V,
;. 3.3k0
~68PF
15
SSM·2014
"
• 30kg (A)
f.!J"t......,;~33-.;;O¥kO~(A=BI'" .,SV
43kn (INTERMEDIATE)
v,
INPUTS
cr-+---'-I
_15V
* veA vep -
C. 220pF. COMP 3 OPEN
c. 33OpF, CeMP 3 TO GRO~D
FIGURE 17: Self·Contained OVCE
22
2190, Rev. A1
SSM-20tS
VOLTAGE-CONTROLLED
AMPLIFIER/OVCE
Precision l\1onolithics Inc.
ADVANCE PRODUCT INFORMATION
FEATURES
Combined with a PM-7524 DAC and SSM-2300 8-channel
mUltiplexed sample-and-hold, the SSM-2018 enables the design of high performance fader automation systems with few
components. The SSM-2018 and SSM-211 0 can be used as the
nucleus of a state-of-the-art dynamic range processor.
• Wide Dynamic Range ••••.••••••••...•..• 11SdB (Class AB Typ)
....................... 10SdB (Class A Typ)
• Improved THD and IMD over Gain, Attenuation, and
Frequency
• Low Control Feedthrough ............. SOOIlV (Class AB Typ)
•..••••••••...•••• 2mV (Class A Typ)
• Buffered Control Port
• Accepts Low or High Impedance Inputs
• Extended Industrial Temperature Range -40·C to +SS·C
• Few External Components
• Low Cost
PIN CONNECTIONS
16-PIN PLASTlC DIP
(P-Sufflx)
APPLICATIONS
•
•
•
•
•
•
•
•
•
Mix Console Fader Automation Systems
Compressor/Limiters
Noise Gates
Noise Reduction Systems
Telephone Line Interfaces
Surround Sound Systems
Automatic or Remote Volume Controllers
Voltage-Controlled Equalizers
Voltage-Controlled Panners
BLOCK DIAGRAM
.....- : : - - - - - _ - " , O B A L
ORDERING INFORMATION
PACKAGE
PLASTIC
16·PIN
SSM2018P
OPERATING
TEMPERATURE
RANGE
XI NO'
• XINO = -40'C 10 +85'C
GENERAL DESCRIPTION
The SSM-2018 is a pin compatible upgrade to the SSM-2014,
offering improved specifications while maintaining applications
flexibility. Improvements include lower noise and lower distortion, particularly over gain and attenuation, with increased
bandwidth. PMl's thin-film resistor capability results in fewer
required external components than the SSM-2014.
Differential inputs and outputs are provided that permit voltage
or current operation. An additional feature is the SSM-2018's
programmable gain core, which allows Class A, AB, intermediate, or 'sliding bias' operation. As a result, the SSM-2018 is an
excellent choice for all common VCA applications, as well as
Operational Voltage-Controlled Element (OVCE) functions
such as voltage-controlled panners and equalizers.
MODE
+IN
-IN
COMPI
COMP2
COMP30=----'
v=~~--------------------------~
This advance product Information dasc,lbas a product In davatopmant attha tlma ofthts printing. Final spaclflcatlons may vary. Plaasacontact local salas 0lllc8
or distributor for final data shaat.
23
9/89, Rev. A
SSM-2024
QUAD CURRENTCONTROLLED AMPLIFIER
Precision MonoHthics Inc.
FEATURES
GENERAL DESCRIPTION
• Four VCAs in One Package
• Ground Referenced Current Control Inputs
• 82dB SIN at 0.3 % THD
• Full Class A Operation
• -40dB Control Feedthrough (Untrimmed)
• Easy Signal Summing
• 6% Gain Matching
The SSM-2024 is a quad Class A noninverting current-controlled transconductance amplifier. Each of the four VCAs is
completely independent and includes a ground referenced linear current gain control. These voltage-in/current-out amplifiers
offer over 82dB SIN at 0.3% THO. Other features include low
control voltage feedthrough and minimal external components
for most applications. With four matched VCAs in a single IC. the
SSM-2024 provides a convenient solution for applications requiring multiple amplifiers. The pinout groups the four outputs for
easy signal summing for circuits such as four-channel mixers.
APPLICATIONS
• Electronic Musical Instruments
• Noise Gating
• Compressor/Limiters
• Signal Mixing
• Automatic Gain Control
• Voltage·ContrOlied Oscillators
PIN CONNECTIONS
16·PIN PLASTIC DIP
(P·Suffix)
ORDERING INFORMATION
PACKAGE
PLASTIC
16·PIN
OPERATING
TEMPERATURE
RANGE
SSM2024P
-10'C to +SO'C
BLOCK DIAGRAM
v.
16
IN,
CONTROL,
<>-"+----'
CONTROL.,
13
OUT,o-''+----------'
12
OUT,o--''+---------,
CONTROL,
OUT4
OUT3
CONTROL3
IN,
IN,
v-
GNO
Tho SSM·2024 I. mask work protected under the Semiconductor Chip Protection Act of 1983.
24
11/89, Rev. A
SSM·2024 QUAD CURRENT·CONTROLLED AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
PACKAGE TYPE
Supply Voltage ..................................................... 36V or ±18V
Junction Temperature .................................................. +150·C
Operating Temperature Range ........................... -10 to +50·C
Storage Temperature Range ............................ -65 to +150·C
Maximum Current into Any Pin ....................................... 10mA
Lead Temperature Range (Soldering, 60 sec) .............. 300·C
UNITS
14·Pin Plaslic DIP (P)
90
47
'C/W
NOTES:
1. e lA Is specified for worst case mounting condilions, I.e., e lA Is specifled for
device In socket for P·DIP package.
ELECTRICAL CHARACTERISTICS at VS =±15V, T A =+25·C, unless otherwise noted.
SSM·2024
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Posilive Supply Currenl
+Isy
ICON (1·4) = 0 Vs = =15V
ICON (I.4)=0 Vs ==16.5V
0.95
1.05
1.40
1.55
1.85
2.05
mA
Negalive Supply Current
-ISY
ICON (1·4) =0 Vs==15V
ICON (1·4)=0 Vs ==16.5V
1.05
1.20
1.55
1.65
2.05
2.25
mA
3842
4085
4330
Ilmhos
=6
%
Gain
G
ICON (1·4) = ±500j!A
Gain Malching
AG
ICON (1·4) = =500j!A
Inpul Offsel Voltage
Vos
V'N = OV ICON (1·4) ==500j!A
ICON (1·4) = +250j!A
=.4
=1.3
mV
Change in Offset Voltage
AVos
+2.5j!A s ICON (1-4) s +250j!A
+250nA s ICON (1-4) s +250j!A
=100
=250
=840
=840
IlV
Output Leakage
10l.
ICON (1.4) = 0
0.1
=5
nA
CVR
ICON (1·4) = 500j!A
V'N (1·4) = 40mV.,.
Signal,to·Noise
SIN
Distortion
THO
Control Rejeclion (Untrimmed)
Threshold Input Control Voltage
VTC '
41.5
dB
V'N (1·4) = 40mV.,.
82
dB
V'N (1·4) = 40mV.,.
0,3
30
+160
lOUT (1·4) = 0
%
+220
mV
NOTE: Specifications subject to change; consult latest data sheet.
SIMPLIFIED SCHEMATIC (1 OF 4 AMPLIFIERS)
v+
+ICONTROL
v-
25
11/89, Rev. A
SSM-2024 QUAD CURRENT-CONTROLLED AMPLIFIER
THEORY OF OPERATION
100
The SSM-2024 is a quad transconductance amplifier. Its voltage-in/current-out transfer functions are controlled by ground
referenced linear current inputs. As shown in the simplified
schematic, the control current is mirrored in the input stage
current source. This sets the operating level for the input differential pair. The operating level established by ICONTROL will
determine the slope of the 10UTNIN transfer characteristic. Each
independent device is configured as a noninverting transconductance amplifier and rated for :!:15V operation.
r----;r----,--...,--7150
.O~--~-~--~~-~
l
~
~
~
SIGNAL INPUTS
The signal inputs offer the best offset and control rejection when
shunted with 2000 to ground. This resistor along with RIN form
the voltage divider to scale the input signal. Select RI Nto set the
maximum operating level for the largest input signal.
80 ~-___ir----I""c.--+~'---I40 ~
Z
~
~
70
.0
50
f----;I----7"-t---j----j
30
'0
f---IIr---1---j----j
20
30~~~'---~--~--~
3
10
30
100
INPUT SIGNAL LEVEL (mVp-p)
300
FIGURE 1
This selection will determine the VCAs operating levels which
have tradeoffs as shown in Figures 1 and 2. As the input signal
level is increased, the effective signal-to-noise and control rejection will increase (improve). However, a larger input signal
also means more THO.
10
The signal at the input of the device will be:
VIN' = VIN (R
I
,I
0.3
2~~00)
IN
i!
j!:
/V
0.1
/
0.03
I
gm = 8.17 ICONTROL = ~
0.01
IN
Therefore, the output current expressed as a function of the
control current and the applied input signal is:
200 )
lOUT = 8.17 ICONTROL =( RIN + 200 VIN
/
/
a
(where V IN is the applied input). The circuit transconductance
10UTNIN'is:
/
L
/
10
30
100
INPUT SIGNAL LEVEL (mVp-p)
300
FIGURE 2
A graph of some typical operating levels is shown in Figure 3.
Note this plot is for a general application where
TAa+2,·C
Ys·,.,15V
RIN = RCONTROL = 10kO
niH. tOke
For output voltage vs. V IN see the right axes of the graph using
800
600
.00
ROUT= 10kO.
CONTROL INPUTS
Each control input is a low impedance, ground referenced linear
current control input. When operated in its active region, input
impedance is approximately 2500. When operating with an
applied control voltage, connect a series resistor. Select RCON
so VCONTROL maX/R CON is no more than 500J.lA.
A) 'CONTROL. SOOa.aA
.....,
B) 'CONTROL. 200~
C) 'CONTROL. 100~
. .00
lOUT. (~A)
.
..
FIGURE 3: SSM-2024 gm = lourN/N
26
11/89, Rev_ A
SSM·2024 QUAD CURRENT·CONTROLLED AMPLIFIER
systems. A waveform mixer following tone sources is shown in
Figure 4. This type of mixer can be configured in several ways to
allow the various waveforms and tone sources to be mixed
under program control. Choice of mixer configurations depends
on system philosophy and the number ottone and noise sources
to be considered.
The VCA will turn completely off as the control voltage drops
below approximately 200mV. The control pin can go as low as
V- with no adverse effects. Control voltages usually do not ex·
ceed 10V. It is possible to operate at higher voltages with cur·
rent limiting. If the control pin is shorted directly to V+, however,
the power dissipation rating of the package will be exceeded
within 10 to 20 seconds.
The SSM·2024 can also be used as the final VCA/volume and
filter controls. This would make keyboard tracking and envelope
sweep programmable.
OUTPUTS
The SSM·2024 is a current output device. Operating in the cur·
rent mode as virtual grounds, the outputs have a voltage compli·
ance of only about500mV. For large output voltages an op amp
is used as a current·to·voltage converter as shown in Figure 4.
Selecting ROUT will determine the output voltage range as
V OUT
=lOUT (ROUT)'
The outputs can be used directly in many applications where
voltage ranges are small, such as the exponential input of a
voltage·controlled filter or other logarithmic·control voltage de·
vices.
Outputs are conveniently located together at the center of the
package for easy connections in signal summing applications.
R'N
1.,,0-."""'_-'-1
DISTORTION
As shown in Figure 2, operation at higher signal levels will in·
crease THD (Total Harmonic Distortion). For many applications
such as control paths where a single input signal is being proc·
essed, distortion effects are minimal. This is because distortion
only slightly alters the harmonic structure of a saw, pulse or trio
angle shaped waveform already rich in harmonics.
VOUT
10kO
CONTROL,~11
In the final VCA, however, where two or more signals are pres·
ent, the effects of IMD (Intermodulation Distortion) become
more significant. Intermodulation distortion is unwanted side·
band signals produced by the circuit at frequencies that are the
sums and differences of the harmonics present at the inputs.
lDIlO
CQNTRO"'~14
A,.
In a Class A VCA, IMD will increase with increasing input signal
level at the same rate as THO. For such applications, we recom·
mend use of the SSM·2024 at signal levels corresponding to
THO of no more than 0.3% (see Figure 2).
v·
FIGURE 4: Four·Channel Mixer (4-1)
APPLICATIONS
The following examples were developed for musical instrument
applications but also illustrate general methods of use. Applica·
tions for the SSM·2024 are numerous in programmable music
27
11/89, Rev. A
SSM·2024 QUAD CURRENT·CONTROLLED AMPLIFIER
56kO
O.1~F
VCOFM
56kO
PULSE
WIDTH
MODULATION
VCFFM
27kQ
27kn
VCF FM CONTROL
PULSE WIDTH
MODULATION
CONTROL
FIGURE 5: Modulation Oscillator
A VCA with programmable amplitude modulation control is
shown in Figure 6. This circuit also exhibits direct interface to
the SSM·2044 VCF without adding an op amp or offset adjust·
ments.
A practical modulation oscillator is shown in Figure 5. Here. the
device is used in the circuit to control the oscillator frequency
and the amountof modulation signal onto the modulation buses.
ADSR
IN
10ka
20kC )( Vee
V pEAK
MODULATION
OSCIL&~g~ o-....2"'O.'V"'--<>-_ _ _- l
(0 TO :VPEAtd*
100pF
20kQ
O--------l. . -l'
1.F
(SSM.:~~~I~C~
AUDIO
OUT
2000
.".3.3."
*MODULATlQN INCREASES FROM ZERO WITH NO INPUT TO 100% AT PEAK LEVEL.
FIGURE 6: VCA with Amplitude Modulation
28
11/89, Rev. A
SSM-2024 QUAD CURRENT-CONTROLLED AMPLIFIER
Two of the SSM-2024 channels can be used with the SSM-2220
dual PNP transistor in an exponential cross-fade circuit. Figure
7 shows how the PNP splits a common linear control current according to the bias of the PNP pair. Here, the voltage called
"exponential cross-fade control" will determine the relative
amount of the two signals at the inputs of the VCAs in the mix.
gain point. As the control voltage is swept positive or negative,
the control current in each VCA is varied logarithmically. As the
control voltage is increased, VCA B receives increased current
as VCA A's current attenuates at a more rapid logarithmic rate.
This applies inversely for decreasing control voltages. At the
maximum positive or negative control voltages, VeA B orVCA A
receives virtually all500flA and is 6dB above the balance point.
The transfer characteristic of this circuit is shown in Figure 8.
This plot is normalized to the balance point where each VCA
has equal current (250flA). This is plotted as the OdB or unity-
To operate a single VCA with exponential control sensitivity,
simply ground the collector of the unused PNP.
Vee ADSR OUT or
MASTER VOLUME
EXPO
CROSS·FADE
CONTROL
A IN
O-o/II'y'--T-+i?=~~~=~
0--"""""1'---0---;
AUDIO
OUT
200kO
BIN o----,/\N-------Q---I
200ko:
FIGURE 7: Exponential Cross-Fade Controller
.10
.6
i
.......... .,/
L'\
-10
~
~
o
~
[\
/
c
-20
veAS/
-30
-5.
1\
/
S
_0 -40
-6.
\VCAA
V
-200
-150 -100
\
-50
50
100
150
200
VCONTROL (mY)
FIGURE 8: Normalized Transfer Characteristic of a Exponential Cross-Fade Controller
29
11/89, Rev. A
SSM-2120/SSM-2122
DYNAMIC RANGE
PROCESSOR/DUAL VCA
Precision i\lollolithics
Illl
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The SSM·2120 is a monolithic integrated circuitdesignedforthe
purpose of processing dynamic signals in various analog sys·
tems including audio. This "dynamic range processor" consists
of two VCAs and two level detectors (the SSM·2122 consists of
two VCAs only). These circuit blocks allow the user to 10garHh·
mically control the gain or attenuation of the signals presented
to the level detectors depending on their magnitudes. This allows the compression, expansion or limiting of ACsignals, some
of the primary applications for the SSM-2120.
0.01% THO at +10dBV In/Out
100dB VCA Dynamic Range
Low VCA Control Feedthrough
100dB Level Detection Range
Log/Antilog Control Paths .
Low External Component Count
APPLICATIONS
•
•
•
•
•
•
•
Compressors
Expanders
LImiters
AGC Circuits
Voltage·Controlled Filters
Noise Reduction Systems
Stereo Noise Gates
PIN CONNECTIONS
THRESH 1
aND
ORDERING INFORMATION
PACKAGE
PLASTIC
16-PIN
PLASTIC
22·PIN
SSM2122P
SSM2120P
-VC1
OPERATING
TEMPERATURE
RANGE
7
SIOo.. •
REc",.
SIG N2
-10'C to +50'C
g aND
SSM-2120
22·PIN PLASTIC DIP
(P·Sufflx)
SIMPLIFIED SCHEMATIC (VCA Section Only)
y+
SSM·2122
16-PIN PLASTIC DIP
(P·Sufllx)
y-
Protected under U.S. Patenls #4,471 ,320 and #4,560,947. OIherPatent Pending. The SSM-2120ISSM-2122Is mask work protected under the Semiconductor Chip
Protection Act 011983.
30
2190, Rev. B
SSM·2120/SSM·2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................................. ±18V
Operating Temperature Range ......................... -10° to +55°C
Junction Temperature .................................................. +150°C
Storage Temperature ...................................... -65° to + 150°C
Maximum Current into Any Pin ....................................... 10mA
Lead Temperature Range (Soldering, 60 sec) .............. 300°C
8 le
UNITS
16·Pln Plastic DIP (P)
8 lA (Note 1)
86
10
22-Pin Plastic DIP (P)
70
7
'CIW
'CIW
PACKAGE TYPE
NOTE:
1. 8jA is specified for worst case mounting conditions, i.e., 8jA is specified for
device in socket for P-DIP.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +25°C,
IREF
= 200JlA, Av = 1, unless otherwise noted.
SSM·2120/SSM·2122
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Supply Voltage Range
±18
V
Positive Supply Current
±5
8
10
rnA
Negative Supply Current
6
8
rnA
±4oo
±413
flA
±1
±2
flA
VCAs
±387
Max ISIGNAL (In/Out)
Output Offset
Control Feedthrough (Trimmed)
RIN = ROUT = 36kO, AvSOdB S-30dB
Gain Control Range
Unity-Gain
750
-100
Control Sensitivity
Gain Scale Factor Drift
fLY
+40
dB
6
mY/dB
-3300
ppm/'C
Frequency Response
Unity-Gain or Less
250
kHz
Off Isolation
At 1kHz
100
Current Gain
+Vc =-Vc =OV
THD (Unity·Gain)
+10dBV I NlOUT
Noise (20kHz Bandwidth)
RE:OdBV
-0.25
dB
0
+0.25
0.005
0.02
-80
dB
%
dB
LEVEL DETECTORS (SSM·2120 ONLY)
Dynamic Range
100
Input Current Range
110
0.03
Rectifier Input Bias Current
4
Output Sensitivity (At LOG AV Pin)
3
Output Offset Voltage
dB
3000
±0.5
16
flAp.p
nA
mY/dB
±2
mV
Frequency Response
1000
50
7.5
liN = 1mAp•p
liN = 1OflAp-p
liN = 1flAp-p
kHz
CONTROL AMPLIFIERS (SSM-2120 ONLY)
Input Bias Current
85
Output Drive (Max Sink Current)
5.0
Input Offset Voltage
175
7.5
±0.5
nA
mA
±2
mV
NOTE:
1. Specifications are subject to change; consult latest data sheet.
31
2190, Rev. 8
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
The current consumption of the VCAs will be directly proportional to IREF which is nominally 2001lA. The device will operate
at lower current levels which will reduce the effective dynamic
range of the VCAs. With a 200llA reference current, the input
and output clip points will be ±400IlA. In general:
VOL TAGE·CONTROLLED AMPLIFIERS
The two voltage-controlled amplifiers are full Class A current in/
current out devices with complementary dBN gain control ports.
The control sensitivities are +SmV/dB and -SmV/dB. A resistor
divider (attenuator) is used to adapt the sensitivity of an external
control voltage to the range of the control port. It is best to use
200Q or less for the attenuator resistor to ground.
ICLIP = ±2IREF
VCAOUTPUTS
The VCA outputs are designed to interface directly with the virtual ground inputs of external operational amplifiers configured
as current-to-voltage converters. The outputs must operate at
virtual ground because of the output stage's finite output impedance. The power supplies and selected compliance range determines the values of input and output resistors needed. As an
example, with ±15V supplies and ±400JlA maximum input and
output current, choose RIN = ROUT = 3SkQ for an output compliance range of ±14.4 V. Note that the signal path through the
VCA including the output current-to-voltage converter is non inverting.
VCAINPUTS
The signal inputs bJhave as virtual grounds. The input current
compliance range is determined by the current into the reference current pin.
REFERENCE PIN
The reference current determines the input and output current
compliance range of the VCAs. The current into the reference
pinis set by connecting a resistor to V+. The voltage althe reference pin is about two volts above V- and the current will be
IREF =
- (~V+'-!.)_--'.('-..:(V_-)'-.+:..::2c:...V.!...=..)]
,-->l
BLOCK DIAGRAM (SSM-2120)
--------------,
I~~n
I
I
I
I
I
I
I
I
I
I
+VCl
INPUT 1
OUTPUT 1
-Ve,
I
i
~
~.m'
_2
'"'""ir?'."
I
I
eFT 1
~~
I
I
I
I
I
I
I
I
I
i
I
I
L ____________ _
32
2190, Rev. B
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
a)
VCA PERFORMANCE
Figures 1a and 1b show the typical THO and noise performance
of the VCAs over :!:20dB gain/attenuation. Full Class A operation provides very low THO.
VCA THO PERFORMANCE
vsGAIN
(+10dBV IN/OUT@1kHz)
.0, ,..--'----r--....,--..,....-'---,
TRIMMING THE VCAs
The control feedthrough (CFT) pins are optional control
feedthrough null points. CFT nulling is usually required in applications such as noise gating and downward expansion. If trimming is not used, leave the CFT pins open.
.01 ~:---+--+---t---"7I
Trim Procedure
1) Apply a 100Hz sine wave to the control point attenuator. The
signal peaks should correspond to the control voltages which
induce the VCAs maximum intended gain and at least 30dB of
attenuation.
.OD31----t---\---+--1
2) Adjustthe SOke potentiometerforthe minimum feedthrough.
-20
-1D
1D
(Trimmed control feedthrough is typically well under 1mVRMS
when the maximum gain is unity using 36ke input and output resistors.)
2D
GAIN (dB)
b)
VCA NOISE vs GAIN
(20kHz BANDWIDTH)
-7D
Applications such as compressor/limiters typically do not require control feedthrough trimming because the VCA operates
at unity-gain unless the signal is large enough to initiate gain
reduction. In this case the signal masks control feedthrough.
,..--,;.".;,.--....,--..,.....:......""7"1
This trim is ineffective for voltage-controlled filter applications.
~D~--t--~--~-~
LEVEL DETECTION CIRCUITS
The SSM-2120 contains two independent level detection circuits. Each circuit contains a wide dynamic range full-wave rectifier, logging circuit and a unipolar drive amplifier. These circuits
will accurately detect the input signal level over a 100dB range
from 30nA to 3mA peak-to-peak.
-2D
-10
0
1D
LEVEL DETECTOR THEORY OF OPERATION
Referring to the level detector block diagram of Figure 2, the
REC 'N input is an AC virtual ground. The next block implements
the full-wave rectification of the input current. This current is
then fed into a logging transistor (0,) whose pair transistor (02)
has a fixed collector current of IREF • The LOG AVoutput is then:
2D
GAIN (dB)
FIGURE 1
,SIeD
lIeD
r-------------------------
I
I
RIN
THRESH----------:
I
AeON
REe'N I
INPUT~I-=~~>-I
I
I
I
I
I
I
:
I
I
I
I
I
+
1-=-2V
I
'1
I
I
II -
~----------------------
!:.O~~"-
___________':_:
v-
FIGURE 2: Level Detector
33
2190, Rev_ B
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL IiCA
VLOGAV= kT 1n(l!m)
q
. IREF
With the use of the LOG AV capacitor the output is then the log
of the average of the absolute value of liN.
(The unfiltered LOG AV output has broad flat plateaus with
sharp negative spikes at the zero crossing. This reduces the
"work" that the averaging capacitor must do, particularly at low
frequencies.)
Note: It is natural to assume that with the addition ofthe averaging capacitor, the LOG AV output would become the average of
the log ofthe absolute value Ofi IN . However, since. the capacitor forces an AC ground at the emitter of the output transistor,
the capacitor charging currents are proportional to the antilog
of the voltage at the base ofthe output transistor. Since the base
voltage of the output transistor is the log of the absolute value of
liN' the log and antilog terms cancel, so the capacitor becomes a
linear integrator with a charging current directly proportional to
the absolute value of the input current. This effectively inverts
the order of the averaging and logging functions. The signal at
the output therefore is the log of the average of the absolute
value of liN.
FIGURE 3: Detector Output
USING DETECTOR PINS REC IN • LOG AV ' THRESH
AND CON oUT
FIGURE 4: Overlayed Detector Output
When applying signals to REC IN (rectifier input) an input series
resistor should be followed by a low leakage blocking capacitor
sinceREC IN has a DC voltage of approximately 2.IV above
ground. Choose RIN for a ±1.SmA peak signal. For ±1SVoperation this corresponds to a value of 10kQ.
scope. The attack rate is determined by the step size and the
value of CAV • The attack time to final value is a function of the
step size increase. The chart of Figure S shows the values of
total settling times to within S, 3, 2 and 1dB of final value with
CAV 10~F. When step sizes exceed 40dB, the increase in settling time for larger steps is negligible. To calculate the attack
time to final value for any value of CAV' simply multiply the value
in the chart by CAV 11 O~F.
=
A 1.SMQvalue of RREF from log averageto-1SVwill establish a
10~A reference current in the logging transistor (0 1). This will
bias the transistor in the middle of the detector's dynamic current range in dB to optimize dynamic range and accuracy. The
LOG AVoutputs are buffered and amplified by unipolar drive op
amps. The 39kQ, 1kQ resistor network at the THRESH pin provides a gain of 40.
The decay rates are linear ramps that are dependent on the
current out of the LOG AV pin (set by RREF) and the value ofCAV .
The integration or decay time of the circuit is derived from the
formula:
An attenuatorfrom the CON oUT (control output) to the appropriate VCA control port establishes the control sensitivity. Use
200Q for the attenuator resistor to ground and choose RCON for
the desired sensitivity. Care should be taken to minimize capacitive loads on the control outputs CON our If long lines or capacitive loads are present, it is best to connect the series resistor
RCON as closely to the CON oUT pin as possible.
.
.
Decrementallon Rate (In dB/s)
I REF x 333
=--CAY
DYNAMIC LEVEL DETECTOR CHARACTERISTICS
Figures 3 and 4 show the dynamic performance of the level
detector to a change in signal level. The inputto the detector (not
shown) is series of SOOms tone bursts at 1kHz in successive
I OdBV steps. The tone bursts start at a level of -BOdBV (with
RIN =10k) and return to -BOdBV after each successive 10dB
step. Tone bursts range from -BOdBV to +1 OdBV. Figure 3
shows the logarithmic level detector output. The output of the
detector is 3mV/dB at LOG AV and the amplifier gain is 40 which
yields 120mV/dB. Thus, the output at CON oUT is seen to increase by 1.2V for each 1OdBV increase in input level.
SdB
3dB
2dB
IdB
10dB Step
11.28"s
21.46
30.19
46.09
20dBStep
16.65
26.83
35.56
51.46
30dB Step
18.15
28.33
37.06
52.96
40dB Step
18.61
27.79
37.52
53.42
50dB Step
(+144"s)
SOdB Step
(+46"s)
FIGURES: Settling Time (tsJ forCAV = 10~F, ts'= ts (CAV /
DYNAMIC ATTACK AND DECAY RATES
Figure 4 shows the output levels overlayed using a storage
1O~F)
34
2190, Rev. B
SSM·2120/SSM·2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
b)
a) CONTROL CIRCUIT
TYPICAL DOWNWARD EXPANDER
CONTROL CURVE
THRESHOLD
I
I
I
I
I
I
I
~--IVV---o--/lN'-...oTO +VC
2000
VeON
=
=
MONO-RIM 10kn
STEREO - RIH 20kQ
V
Y'N(dB)
*LOWER LIMrr CAN BE FIXED BV CONNECTING
A RESISTOR ALL FROM REe lN TO GROUND
FIGURE 6: Noise Gate/Downward Expander Control Circuit and Typical Response
a) CONTROL CIRCUIT
b)
TYPICAL COMPRESSOR/LIMITER
CONTROL CURVE
v+
M,.
Lo--vvII'--1
MONO_ ~~N. 1
I
ORR~+
RECIN
VeON
I-----~I_-......:l---l
MONO - RIH • 10ka
STEREO - RIH .. 20kA
v_
V,Nldal
·UPPER UMIT CAN BE FIXED BY VALUE OF PULL UP
RESISTOR (Rpy) CONNECTED TO POSITiVe SUPPLY
FIGURE 7: Compressor/Limiter Control Circuit and Typical Response
APPLICATIONS
lar control output. This is typically used in noise gate, downward
expander, and dynamic filter applications. This potentiometer is
used in all applications to control the signal level versus control
voltage characteristics.
The following applications for the SSM·2120 use both the VCAs
and level detectors in conjunction to assimilate a variety offunc·
tions.
In the noise gate, downward expander and compressor/limiter
applications, this potentiometer will establish the onset of the
control action. The sensitivity of the control action depends on
the value of RT'
For a positive unipolar control output add two diodes as shown
in Figure 7a. This is useful in compressor/limiter applications.
Figure 7b shows a typical response.
The first section describes the arrangement of the threshold
control in each control circuit configuration. These control circuits form the foundation for the applications to follow which
include the downward expander, compressor/limiter and com·
pandor.
THRESHOLD CONTROL
Figure 6a shows the control circuit for a typical downward expander while Figure 6b shows a typical control curve. Here, the
threshold potentiometer adjusts Vr to provide a negative unipo·
Bipolar control outputs can be realized by adding a resistor from
the op amp output to V+. This is useful in compandor circuits as
35
2190,Rev.B
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
TYPICAL COMPANDOR
CONTROL CURVES
b)
a) CONTROL CIRCUIT
v.
R,.
L~
....--I\II/'---(>--Mht-~rw'--_-f--<> -vc
FIGURE 9: Control Circuit for Stereo Compressor/Limiter with Noise Gating and Input/Output Curve
/
shown in Figure Ba, with its response in Figure ab. The value of
the resistor Rpv will determine the maximum output from the
control amplifier.
compressor/limiter which also acts as a downward expander for
noise gating. The output noise in the absence of a signal will be
dependent on the noise of the current-to-voltage converter
amplifier if the expansion ratio is high enough.
STEREO COMPRESSOR/LIMITER
The two control circuits of Figures 6 and 7 can be used in conjunction to produce composite control voltages. Figures 9a and
9b show this type of circuit and transfer function for a stereo
As discussed in the Threshold Control section, the use of the
control circuit of Figure 5, including the Rpv to V+ and two diodes, yields positive unipolar control outputs.
36
2190, Rev_ B
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
y-
y-
FIGURE 10: Companding Noise Reduction System
COMPANDING NOISE REDUCTION SYSTEM
A complete companding noise reduction system is shown in
Figure 10. Normally. to obtain an overall gain of unity. the value
of Rc is equal to RE. The values of RCIE will determine the compression/expansion ratio.
,.
IREP:: 3p.A
RREF_4.7Ma
lit
~
§ ...
Table 1 shows compression/expansion ratios ranging from
1.5:1 to full limiting with the corresponding values of RCtE '
:;!
z
~
An example of a 2:1 compression/expansion ratio is plotted in
Figure 11. Note that signal compression increases gain for low
level signals and reduces gain for high levels while expansion
does the reverse. The net result for the system is the same as
the original input signal except that it has been compressed
before being sent to a given medium and expanded after recovery. The compression/expansion ratio needed depends on the
medium being used. As an extreme example. a household tape
player would require a higher compression/expansion ratio than
a professional stereo system.
!;
~
....
-60
-GO
-40
-20
0
20
INPUT SIGNAL LEVEL (dB)
FIGURE 11: Companding Noise Reduction with 2:1 Compression/Expansion Ratio
tABLE 1
INPUT SIGNAL
INCREASE (dB)
GAIN
(REDUCTION
OR INCREASE)
(dB)
COMPRESSOR
ONLY
OUTPUT SIGNAL
INCREASE (dB)
EXPANDER
ONLY
OUTPUT SIGNAL
INCREASE (dB)
20
6.67
13.33
22.67
1.5:1
11.800
2.0
20
10.00
10.00
30.00
2:1
7,800
3.0
20
13.33
6.67
33.33
3:1
5,800
4.0
20
15.00
5.00
35.00
4:1
5,133
4.5
20
16.00
4.00
36.00
5:1
4,800
4.8
5.2
COMPRESSIONI
EXPANSION RATIO
RCiE
n
~VCONTROC
(mV/dB)
20
17.33
2.67
37.33
7.5:1
4,415
20
18.00
2.00
38.00
10:1
4,244
5.4
20
20.00
0
40.00
AGC'/Limiter
3,800
6.0
•AGC for Compression Only
37
2190, Rev. B
SSM-2120/sSM-2122 DYNAMIC RANGE PROCESSOR/DUALVCA
v+
THRESHOLD
CONTROL
+---./11'1'---0 v-
v-
v+
THRESH
12
39kO
CONQIIT 5.6kO
,.
101e0 330~ REc",
1.
Fe= 5kHz
(HIGH FREOUENCy)
v-
v35k0
3SkO
SIG IN
70
AUDIO
OUTPUT
~2200PF 7
FIGURE 12: Dynamic Noise Filter Circuit
DYNAMIC FILTER
Figure 12 shows a control circuit for a dynamic filter capable of
single ended (non·encode/decode) noise reduction. Such circuits usually suffer from a loss of high-frequency content at low
signal levels because their control circuits detect the absolute
amount of highs present in the signal. This circuit, however,
measures wideband level as well as high-frequency band level
to produce a composite control signal combined in a 1:2 ratio
respectively. The upper detector senses wideband signals with
a cutoff of 20Hz while the lower detector has a 5kHz cutoff to
sense only high-frequency band signals. This approach allows
very good noise masking with a minimum loss of "highs" when
the signal level goes below the threshold.
38
2190, Rev. B
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
a)
at
VTHRESH
..
ID
....
........
§ ••
~
..
. ....
~ ...
=
"
Ii
." -
17.8
•
-3
::>
:
....
.. .. ..
541 50.1 SO.l
~
!!
Figures 13a-c show the filter's 3dB frequency response with the
threshold potentiometer at V.+., centered, and V-. Data was
taken by applying a 300Hz signal to the wideband detector and
a 20kHz signal 10 the high-frequency band detector simultaneously. These figures correspond to filter characteristics for
50dB, 70dB and 90dB dynamic range program source material,
respectively. The system could thus treat signals from anything
ranging from 1/4" magnetic tape to high-performance compact
disc players.
V+
Note that in Figure 13a the control circuit is designed so that the
minimum cutoff frequency is about 1kHz. This results from the
control circuit detecting the noise floor of the source material.
... "9 ... ... ..
... ... ... ... ... ...
... ... ... ... .. .. ...
3.. .
1.7
• .0
.
8.3 11.7 11.7 11.7
.... ....
..
Dynamic filtering limits the signal bandwidth to less than 1kHz
unless enough highs are detected in the signal to coverthe noise
floor in the mid- and high-frequency range. In this case the filter
opens to pass more of the audio band as more highs are detected. The filter's bandwidlh can extend to 50kHz with a nominal signal level at the input. At other signal levels with varying
high-frequency content, the filter will close to the required bandwidth. Here, noise outside the band is removed while the perceived noise is masked by other signals within the band. Even in
this system, however, a certain amount of mid- and high-frequency components will be lost, especially during transients at
very low signal levels. This circuit does not address low frequency noise such as "hum" and "rumble."
..
• ••
-3G -aD -10
W1DEBAND SIGNAL LEVEL IdB)
b) VTHRESH Centered
ID
.
....
§ ••
~
50.1 50.1
..
"
~
z
Ii
r;
z
~
IE
... . ..
•• ••
50.& 50.. 50.1 50.1
-3
4&2 48.2 4Sl.2 48.2
....
.5.1
....
i= ....
50..
50.1 50.1
-
4.9
1.5
7.'
... ...
.... ... ....
•• •• •• •• ••
4.2
4.2
-2D
-1.
4.2
.
4••
4.2
• , ••
W1DEaAND SlONAL LEVEL IdB)
c)
VTHRESH
!
§
~
"
Ii
at
V-
.,.
....
........
50.& SO'& 50.8
-1.
50.8 SO.&
i ....
8
...
"=
5eUl 50.8 50.1 50.1 50.1 SO'&
IE
:
....
SO.. 50..
SO.l 50.1 SO'& SO.. 50.8
-3
4D
41
41
41
41
41
4•
.
12.3 17.3 17.8 17.1 17.8 17.8 1'.1 17.1
....
-olD -aD -20 -10
• , ••
W1DEaAND SlONAL LEVEL Ida)
FIGURE 13: 3dB Filter Response
39
2/90, Rev_ B
SSM-2120/sSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
v.
,2kD
V.
SlCNAL
OUTPUT
470
J
2200pF
'::"
DOWNWARD EXPANDER
2000
•. l1li1
LOGAV
r:!t--<>-----I
"='"
CAV2
1.SMQ
V-
V3IIcO
470
~
UDOpF
":'
NOISE FILTER
FIGURE 14: Dynamic Filter with Downward Expander
DYNAMIC FILTER WITH DOWNWARD EXPANDER
A composite single-ended noise reduction system can be realized by a combination of dynamic filtering and a downward expander. As shown in Figure 14, the output from the wideband
detector can also be connected to the +Vc control port of the
second VCA which is connected in series with the sliding filter.
This will act as a downward expander with a threshold that
tracks that of the filter. Although both of these techniques are
used for noise reduction, each alone will pass appreciable
amounts of noise under some conditions. When used together,
both contribute distinct advantages while compensating for
each other's deficiencies.
The dynamic filter and downward expander techniques used together can be employed more subtly to achieve a given level of
noise reduction than would be required if used individually. Up
to 30dB of noise reduction can be realized while preserving the
crisp highs with a minimum of transient side effects.
.20I
Downward expansion uses a VCA controlled by the level detector. This section maintains dynamic range integrity for all levels
above the user adjustable threshold level. As the input level
decreases below the threshold, gain reduction occurs at an increasing rate (see Figure 15). This technique reduces audible
noise in fade outs or low level signal passages by keeping the
standing noise floor well below the program material.
!
i
~
This technique by itself is less effective for signals with predominantly low frequency content such as a bass solo where wideband frequency noise would be heard at full level. Also, since
the level detector has a time constant for signal averaging. percussive material can modulate the noise floor causing a "pump.ing" or "breathing" effect.
1'20
-30
-3G
-40
....5
ii
:!!.
-iO
!;
10
0
~
FIGURE 15: Typical Downward Expander 110 Characteristics
at -30dS Threshold Level (1 :1.5 Ratio)
40
2190, Rev. B
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
10pF
,.
SIG OUT1
,.
20---+---.....---------QVOUT
NULL2~~--rr----_+------------+_----~~--------~
Co
SOpF
4N~~~~----_+------_.--~
470pP
.IN o-~.....T+----_+------------_+_----+_--------'
AlOUT
L:S!':O~!,_L._-_-_--_-_-_-_-_-_-_-_--_-_-_-_-_-_-_--_-_-_-_-___-_-_--_-_-_-_.._~_-_-_--_-_-_~I----....,.....:..2-oV-
R2
5kO
~ D.1~F
-470pFCAPACITOR SHOULD BE MOUNTED CLOSE TO THE PACKAGE
FIGURE 1: Typical Preamplifier Amplification
APPLICATIONS INFORMATION
is supplied by a nulling (servo) amplifier through the external
resistors R3 and R4 (Figure 1). This system produces both optimum noise and common-mode rejection while retaining a very
high input impedance. The internal "servo" amplifier is used to
control the input stage current independently of common-mode
voltage and its output is accessible via pin 12.
PRINCIPLE OF OPERATION
The SSM-2016 operates as a true differential amplifier with
feedback returned directly to the emitters of the input stage transistors by Rl (See Figure 1). The differential pair is fed by a
current source at the collectors and the required emitter current
51
2/90, Rev_A 1
SSM·2016 ULTRA LOW NOISE DIFFERENTIAL AUDIO PREAMPLIFIER
GAIN SETTING
The nominal gain of the SSM-2016 is given by:
R, + R2
Rg
TOTAL HARMONIC DISTORTION
Figures 2 - 5 show the distortion behavior of SSM-2016. All
measurements were taken at a 1OV RMS output to ensure a true
"worst case" condition. No crossover distortion is observed at
lower ouput levels. At 20dB of gain (Figure 2) total harmonic
distortion (plus noise) is well below 0.01 % at all audio frequencies. At 40dB of gain (Figure 3) some loading effects are evident,
especially at higher frequencies, but the overall THD is still very
low. The measurements at 60dB of gain (Figure 4) are a little
misleading because the noise floor is at an equivalent level of
0.0085% at this gain. In fact, the real distortion components are
not greatly increased from the 40dB case.
R, + R2
R3 + R4
G= - - - + - - - +1
or
G=
10kQ
R
+ 3.5
For R, = R2 = 5kQ, R3 = R4 = 2kQ
9
R, and R2 should be equal to 5kQ for best results. It is vital that
good quality resistors be used in the gain setting network, since
low quality types (notably carbon composition) can generate
significant amounts of distortion and, under some conditions,
low frequency noise.
Figure 5 shows the intermodulation distortion performance of
the SSM-2016. A basic SMPTE type test was performed with the
main generator swept from 2.5kHz to 20kHz. The 60dB reading
is once more mostly noise.
The SSM-2016 is capable of operating at gains down to 3.5 at
full performance. Gain range can be extended further by increasing R3 and R4 in Figure 1, but at the penalty of reduced
common-mode input range. Gains below 2.5 are not practical
unless the negative supply voltage is increased.
OVERALL DISTORTION
AT +20dB GAIN
Note that tolerance of R, - R4 directly affects the gain error and
that good matching between R, - R4 is essential to prevent
degradation of the common-mode rejection performance.
0.1
The SSM-2016 provides internal 1 kQ resistors to replace R3
and R4 in applications where distortion is not too critical.
~
FREQUENCY COMPENSATION
The SSM-2016's internal "servo" amplifier is compensated by
C3 , while C, and C2 (see Figure 1) compensate the overall
amplifier. The values shown maintain a very wide bandwidth
with a good symmetrical slew rate. If desired, the bandwidth can
be reduced by increasing the value of C,.
~
o
~
IRILIJ tooo
0.010
RL
RL
=2ka
= 10kO
II-III
0.001
20
100
1k
10k
20k
FREQUENCY (Hz)
NOISE PERFORMANCE
The SSM-2016's input referred noise is O.11j.lV RMS (20kHz
bandwidth) at60dB of gain, 0.2IlVRMS at40dB, and 0.8j.lV RMS at
20dB. The apparent increase at low gains is due to noise incurred in the feedback resistors and second stage becoming
dominant. This noise is actually present at all times but becomes
masked by input stage noise as the gain is increased.
FIGURE2
OVERALL DISTORTION
AT +40dB GAIN
The SSM-2016 is optimized for source impedances of 1kQ or
less and under these conditions, the noise performance is equal
to the best discrete component designs. Considering that a
"standard" microphone with impedance of 150Q generates
1.6nV! vHZ of thermal noise, the SSM-2016's 800pV! vHZ of
voltage noise or the corresponding noise figure of typically 1dB
make the device virtually transparent to the user.
~
i
0
is
11_
RL:!:!
z
0 010
.
RL "2kO
R L =10kO
.....
In applications where higher source impedances than 1 kQ are
desired, the SSM-2015 preamplifier is recommended.
0.001
20
100
lk
10k
20k
FREQUENCY (Hz)
Another source of noise degradation is the chip's total power
dissipation, since any increase in temperature will increase the
noise. This effect is more pronounced at higher gains. As are·
suit, the SSM-2016 uses a copper lead-frame package which
greatly helps the power dissipation and the noise performance.
The best noise performance of the SSM-2016 can be achieved
at low supply voltages while driving light loads.
FIGURE 3
52
2190, Rev. A1
SSM-2016 ULTRA LOW NOISE DIFFERENTIAL AUDIO PREAMPLIFIER
OVERALL DISTORTION
AT +60dB GAIN
0.1
RL
=600n
0.1
~
z
g
TYPICALIMD
PERFORMANCE
0.010
a:
60dS GAIN
e!
R L = 10kel
~
0.010
C
40dB GAIN
~
i5
20dB GAIN
0.001
.0005
2k
0.001
20
100
1k
10k
10k
20k
FREQUENCY (Hz)
20k
FREQUENCY (HZ)
FIGURE 4
FIGURE 5
DRIVE CAPABILITY
Fabricated on a high voltage process, the SSM-2016 is capable
of operating from ±9V to ±36V supplies. In addition, the powerful
output stage is designed to drive a jack·field directly. The SSM·
2016 is capable of driving a 1OV RMS sine wave into 600Q load
using ±18V supplies. However, ±20V or greater supplies are
recommended to give a more comfortable headroom. A copper
lead·frame DIP package is used to permit 1.5W of dissipation
when driving heavy loads or operating from elevated supplies.
16
IS
I.
I
13
-:#
470pF 5
SSM-201S 12
TRANSDUCER
I
I
11
10
(NON INVERTING)
0:!:-
INPUTS
The SSM-2016 offers protection diodes across the base·emitter
junctions of the input transistors. These prevent accidental
avalanche breakdown which could seriously degrade noise
performance. Additional clamp diodes are also provided to pre·
vent the inputs from being forced too far beyond the supplies.
s) SINGLE ENDED
16
IS
I.
Although the SSM-2016's inputs are fully floating, care must be
exercised to ensure that both inputs have a DC bias connection
capable of maintaining them within the input common·mode
range. The usual method of achieving this is to ground one side
ofthe transducer as in Figure 6a, but an alternative way is to float
the transducer and use two resistors to set the bias point as in
figure 6b. The value of these resistors can be up to 10kQ, but
they should be kept as small as possible to limit common·mode
pickup. Noise contribution by resistors themselves is negligible
since it is attenuated by the transducer's impedance. Balanced
transducers give the best noise immunity, and interface directly
as in Figure 6c.
13
TRANSDUCER
470pF
S
SSM·2016 12
11
10
b) PSEUDO DIFFERENTIAL
16
IS
"13
TRANSDUCER
470pF
S
SsM-20tS 12
11
10
c) TRUE DIFFERENTIAL
FIGURE 6: Three Ways of Interfacing Transducers for High·
Noise Immunity
53
2190, Rev. A1
SSM-2016 ULTRA LOW NOISE DIFFERENTIAL AUDIO PREAMPLIFIER
16
,.
+48V
Rs
100D
c,
14
~INPUT
R,
6.aka 1%
13
SSM·2016
200pF 5
I
R,
S.8kQ'%
+
11
47pF-INPUT 0-----'-1
":"
12
10
C1 - C 2 4711F 60Y TANTALUM
FIGURE 7: SSM-2016 with Phantom Power
...----I\N---.NV'----.....- VOUT
4.7kt1
1100
16
R.
1.
2.4MD
v+ o---./VV'-Ov-
YR,
14
100kD
13
SSM·201S
12
4.7kD
11
10
Rz
lDDktl
8
FIGURE 8: Trimming Circuit
PHANTOM POWERING
A typical phantom microphone powering circuit is shown in Figure 7. Z, through Z4 provide transient overvoltage protection for
the SSM-2016 whenever microphones are plugged in and out.
offset, and VR3 the low-gain offset. Common-mode rejection is
best adjusted by applying an 8Vp·p 60Hz (50Hz in Europe) sine
wave to both inputs and adjusting VR, for minimum output. Interaction is minimized by trimming the high-gain offset first, followed by the CMR and finally the low-gain offset. A two-pass trim
is recommended for best results. Note that the overall gain has
been reduced slightly to allow convenient values of resistors.
TRIMMING
The SSM-2016 accommodates four types of trimming: gain,
high-gain offset, low-gain offset, and common-mode rejection.
All four can be accomplished with the circuits shown in Figure 8.
If the low-gain offset trim is not used, then gain control
feedthrough can still be reduced by adjusting the high-gain offset to equal the low-gain offset by means of VR 2 •
Gain trim on the SSM-2016 is readily accomplished by adjusting
RG • VR, adjusts the common-mode rejection, VR 2 the high~gain
54
2190, Rev_ A1
SSM-2016 ULTRA LOW NOISE DIFFERENTIAL AUDIO PREAMPLIFIER
BUS SUMMING AMPLIFIER
In addition to its use as a microphone preamplifier, the SSM2016 can be used as a very low noise summing amplifier. Such
a circuit is particularly useful when many medium impedance
outputs are summed together to produce a high effective noise
gain.
To remove the 0.65V offset, the circuit of Figure 9 is recommended.
A2 forms a "servo" amplifier feeding the SSM-2016's inputs.
This places pins 4 and 5 at a true DC virtual ground. Rs in conjunction with Ce remove the voltage noise of A2 and in fact just
about any operational amplifier will work well here since it is
removed from the signal path. If the DC offset at pins 4 and 5 is
not too critical, then the servo loop can be replaced by the diode
biasing scheme of Figure 9a. If AC coupling is used throughout,
then pins 3 and 6 may be directly grounded.
The principle of the summing amplifier is to ground the SSM2016 inputs. Under these conditions, pins 4 and 5 are AC virtual
grounds sitting about 0.65V below ground. Any current injected
into these pOints must flow through the feedback resistor (R l )
and hence are amplified to appear in the the output. Moreover,
both positive (pin 5) and negative (pin 6) transfer characteristics
are available simultaneously in contrast to the usual "inverting
only" configuration.
a)
INPUT BIAS CIRCUIT TO
REPLACE SERVO AMP IN NONCRITICAL APPLICATIONS
.kD
1%
V+
.k1l
1%
R,
IOUT
10k1l
5kD
1%
~O.1"F
V-
*'
16
o--_----='-j
15
1"
-IIM o---!------_-----+~
+IIN
5
o-......*------------+~
INPUT VIRTUAL
GROUND SERVO AMP
13
SSMa2Q16
1.
11
10
33k1l
1N4148
39pF
SOpF
V+
~o.l.F
R,
5.11ca
-NOTE: TOTAL INPUT CURRENT MUST BE LESS THAN CAN
BE SUPPLIED BY 5kD FEEDBACK RESISTOR
FIGURE 9: Bus Summing Amplifier
55
2190, Rev. A1
SSM·2016 ULTRA LOW NOISE DIFFERENTIAL AUDIO PREAMPLIFIER
R,
5kQ
D
16
O•1i!F
IS
V-
,.
+IN
c"
3Gp~
Vour
Flo
2kQ
47OpF'
SSM·201.
R.
2kQ
-IN
V+
0
VOLTAGE GAIN
50pF
='~Q + 3.5
'47OpF CAP MOUNTED CLOSE TO PACKAGE
FIGURE 10: Typical Connection for Breadboarding Purposes
56
2190, Rev, A1
SSM-2017
SELF-CONTAINED
AUDIO PREAMPLIFIER
Precision 1\1onolithics Inc.
ADVANCE PRODUcr INFORMATION
FEATURES
GENERAL DESCRIPTION
• Excellent Noise Performance ........................ 750pvYHl,
or 1dB Noise Figure
• Ultra-Low THO .................................... < 0.01 % @ G =1000
Over the Full Audio Band
• Wide Bandwidth·.................................... 250kHz@ G =100
• High Slew Rate ••••••••••••••••••••••••••••••••••••••••••••••~.; •••••••• 10V/ILS
• True Differential Inputs
• 8-Pln Mini-DIP with Only One External
Component Required
• Very Low Cost
• Extended Industrial Temperature
Range .......................................................... -40'C to +85'C
• Gain Range of OdB to Over 60dB
• Sub-Audio 11f Noise Corner
The SSM-2017 is PMl's latest generation audio preamplifier
combining SSM preamplifier design expertise with advanced
processing. The result is excellent audio performance from a
self:contained 8-pin mini-DIP device, requiring only one external gain-set resistor or potentiometer. The SSM-2017 is further
enhanced by its unity-gain stability.
Key specifications include ultra-low noise (1 dB noise figure) and
THD «0.01% at G = 1000), complemented by wide bandwidth
and high slew rate. The SSM-2017 can be operated by supply
voltages from ±9V to ± 25V.
Applications forthis low cost device include microphone preamplifiers and bus summing amplifiers in professional and consumer audio equipment, sonar, and other applications requiring
a low-noise instrumentation amplifier with high gain capability.
APPLICATIONS
•
•
•
•
•
TYPICAL APPLICATION
Audio Mix Consoles
Intercom/Paging Systems
Two-Way Radio
Sonar
Digital Audio Systems
v.
.IN
OUT
-IN
ORDERING INFORMATION
PACKAGE
PLASTIC
a·PIN
OPERATING
TEMPERATURE
RANGE
SSM2017P
XINO'
~
1 I N.C.
IOII.11Ia
Vour
(IOkn)
i+iiii=FiN) = To • 1
100 11000
1000 1100
·XINO. -40'C tD.+85'C
PIN CONNECTIONS
8-PIN
PLASTIC DIP
(P-Sufflx)
This advance product Information describes a product In development at the tlmeolthls printing. Final specillcatlons may vary. Please contact local sales office
or distributor forllnal data sheet.
57
9/89, Rev. A
SSM-2402/SSM-2412
DUAL AUDIO
ANALOG SWITCHES
Precision l\1onolithics Inc.
FEATURES
new circuit topology that optimizes audio performance, the
SSM-240212412 make use of a proprietary bipolar-JFET process with thin-film resistor network capability. Nitride capacitors,
which are very area efficient, are used for the proprietary ramp
generator that controls the switch resistance transition. Very
wide bandwidth amplifiers control the gate-to-source voltage
over the full audio operating range for each switch. The ONresistance is very constant with changes in signal amplitude and
frequency, thus distortion is very low, less than 0.01 °/~ Max.
•
•
•
•
•
•
•
"Cllckless" Bilateral Audio Switching
Gua.ranteed "Break-Belore-Make" Switching
low Distortion •••••••••••••••••• ,.............................. 0.003% Typ
low Noise ............................................................. 1nVtv"FiZ
Superb OFF-Isolation ....................................... 120dB Typ
low ON-Resistance .............................................. 60n Typ
Wide Signal Range:
Vs =±18V ....,....................................................... 10V RMS
• Wide Power Supply Range ................................ ±20V Max
• Available In Dice Form
The SSM-2402 is the first analog switch truly optimized for highperformance audio applications. For broadcasting and other
switching applications which require a faster switching time, we
recommend the SSM-2412- a dual analog switch with one-third
of the switching time of the SSM-2402.
ORDERING INFORMATION
PACKAGE
PLASTIC
l4·PIN
SOL
l6·PIN
OPERATING
TEMPERATURE
RANGE
SSM2402P
SSM2412P
SSM2402S
SSM2412S
XINo'
XI NO'
PIN CONNECTIONS
'XINo = --40'C to +85'C
14-PIN
PLASTIC DIP
(P-Sufflx)
GENERAL DESCRIPTION
The SSM-2402/2412 are dual analog switches designed spe·
cifically for high-performance audio applications. Distortion and
noise are negligible over the full audio operating range of 20Hz
to 20kHz at signal levels of up to 1OVRMS' The SSM-2402/2412
offer a monolithic integrated alternative to expensive and noisy
relays or complex discrete JFET circuits. Unlike conventional
general-purpose CMOS switches, the SSM-2402/2412 provide
superb fidelity without audio "clicks" during switching.
GROUND 1
sw, CONTROL
2
15 SWa CONTROL
N.C.- 3
sw,
Conventional TTL or CMOS logic can be used to control the
switch state. No external pull-up resistors are needed. A "T"
configuration provides superb OFF-isolation and true bilateral
operation. The analog inputs and outputs are protected against
overload and overvoltage.
l6-PINSOl
(S·Sufflx)
IN "
N.C.'
An important feature is the guaranteed "break-before-make"for
all units, even IC-to-IC. In large systems with multiple switching
channels, all separate switching units must open before any
switch goes into the ON-state. With the SSM-2402/2412, you
can be certain that multiple circuits will all break-before-make.
• GUARD PINS FOR INPUTJOUTPUT ISOLAnON
(GROUND FOR BEST PERFORMANCE)
CONTROL LOGIC
The SSM-2402/2412 represent a significant step forward in
audio switching technology. Distortion and switching noise are
significantly reduced in the new SSM-2402/2412 bipolar-JFET
switches relative to CMOS switching technology. Based on a
Logic In
Switch State
o
OFF
ON
58
Logic '0- S 0.8V
Logie -1- ~ 2.0V
2/90, Rev, A1
SSM·2402/SSM·2412 DUAL AUDIO ANALOG SWITCHES
FUNCTIONAL DIAGRAM
v+
TIMING DIAGRAM
()-+
GNO~
0:
o
... ~
,,0:
ZW
o:Z
WW
1-"
., ..
'"
::
MAIN SWITCH OPEN'
SHUNT SWITCH CLOSED
I
I
I.. tON -+1
...,
I
t+- tOFF
HIGHJ
CONTROL
INPUT
IN 0-+....- - - - - - '
L.----~_1:-o OUT
LOW
TIME
SWITCH TIMING
v-o-~---_t---~---_1---~
CO~!~~~
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range ....................... -40°C to +B5°C
Operating Supply Voltage Range .................................... ±20V
Analog Input Voltage Range
Continuous .................................. V- +3.5V " VA" V+ -3.5V
Maximum Current Through Switch ................................. 20mA
Logic Input Voltage Range ........................... V+ Supply to -2V
V+ Supply to Ground ....................................................... +36V
V- Supply to Ground ........................................................ -20V
VA to V- Supply ............................................................... +36V
C>-+
~--------------~
PACKAGE TVPE
=
=
LOGIC HIGH ON
LOGIC LOW OFF
5 1 ,5 2 MAIN SWITCHES
53 = SHUNT SWITCH
=
alc
UNITS
14-Pin Plastic OIP (P)
76
33
'C/W
16·Pin SOL (5)
92
27
'C/W
alA (NOTE 1)
NOTE:
1. alA is specified for worst case mounting conditions, i.e .• alA is specified for
device in socket for P-DIP package; alA is specified for device soldered to
printed circuit board for SOL package.
ELECTRICAL CHARACTERISTICS at Vs =±1BV, RL =OPEN, and -40°C" TA " +B5°C, unless otherwise noted.
All specifications, tables, graphs, and application data apply to both the SSM·2402 and SSM·2412, unless otherwise noted.
SSM·2402/2412
PARAMETER
SYMBOL
CONDITIONS
TVP
MAX
UNITS
Positive Supply
Current
+Isy
V ,L = o.av, 2.0V
(Note 1)
6.0
7.5
mA
. Negative Supply
Current
-ISY
V'L = o.av. 2.0V
(Note 1)
4.B
6.0
mA
'GNO
V ,L = o.av, 2.0V
(Note 1)
0.6
1.5
mA
Digital Input High
V 1NH
T A = Full Temperature Range
Digital Input Low
V ,NL
T A = Full Temperature Range
Logic Input
Current
'LOGIC
V ,N =Oto15V
(Note 2)
Analog Voltage
Range (Note 3)
VANALOG
Ground Current
MIN
V
2.0
1.0
-14.2
59
0.8
V
5.0
!1A
+14.2
V
2190, Rev. A1
SSM-2402/SSM-2412 DUAL AUDIO ANALOG SWITCHES
ELECTRICAL CHARACTERISTICS at Vs = ±18V,
RL
= OPEN, and -40°C sTA s +85°C, unless otherwise noted. Continued
SSM-2402/2412
PARAMETER
SYMBOL
Analog Current
Range (Note 3)
'ANALOG
CONOITIONS
VIN
RON
~
VA
~
RONMATCH
Switch ON
Leakage Current
IS (ON)
Turn·On Time
(Note 4)
~
IS(OFF)
+10
mA
mA
60
V A ~ +14.2V
IA = .10mA, V'L = 2.0V
V'L = 2.0V
-14.2V ~ VA
~
V'L = 0.8V
-14.2V ~ VA
~
85
liS
0.2
+14.2V
0.05
0.05
VA =OV
Switch OFF
Leakage Current
-14.2
UNITS
+t4.2V
IA = .10mA, V'L = 2.0V
TA = +25'C
TA = Full Temperature Range
Tempco (ll.RON/ll.T)
RON Match
MAX
.40
=±VSUPPLY
-t4.2
Switch ON
Resistance
TYP
-10
Overvoltage Input
Current
MIN
+14.2V
0.05
0.05
VA =OV
Q
Q
Q/'C
5
%
1.0
!LA
10.0
nA
1.0
10.0
!LA
nA
tON
VA =+IOV,R L =2kQ
TA = +25'C, See Test Circuit
SSM-2402
SSM·2412
10.0
3.S
ms
VA=+IOV,R L =2kQ
T A = +25'C, See Test Circuit
SSM-2402
tOFF
SSM-2412
4.0
1.5
ms
tOFF-tON
TA = +25'C
Q
TA = +25'C
CS(ON)
VA = IVRMS
I = 5kHz, T A = +25'C
12
pF
OFF-State
Input Capacitance
CS(OFF)
VA = IVRMS
I = 5kHz, TA = +25'C
4
pF
OFF Isolation
ISO(OFF)
VA = 10VRMS ' 20Hz to 20kHz
T A = +25'C, See Test Circuit
120
dB
Channel·to-Channel
Crosstalk
Cr
VA = 10VRMS ' 20Hz to 20kHz
TA =+25'C
96
dB
Total Harmonic
Distortion (Note 7)
THO
Spectral Noise
Density
en
Wide band Noise
Density
en p.p
Turn-Off Time
(Note 5)
Break·Belore-Make
Time Delay (Note 6)
Charge Injection
ON-State
Input Capacitance
SSM-2402
SSM·2412
oto 10VRMS ' 20Hz to 20kHz
TA = +25'C, RL = 5kQ
6.0
ms
2.0
SSM-2402
SO
SSM·2412
ISO
0.003
20fiz to 20kHz
pC
0.01
%
nV/v'HZ
T A = +25'C
20Hz to 20kHz
0.2
TA =+25'C
NOTES:
I .• v,L" is the Logic Control Input.
2. Current tested at V, N = OV. This is the worst case condition.
3. Guaranteed by RON test condition.
4. Turn-ON Time is measured Irom the time the logic input reaches the 50% pOint
to the time the oulput reaches 50% 01 the linal value.
5. Turn-OFF time is measured Irom the lime the logic input reaches the 50% point
to the time the output reaches 50% 01 the Initial value.
6. Swilch is guaranleed by design 10 provide break-belore·make operation.
7. THO guaranleed by design and dynamic RON lesling.
60
2190, Rev.A1
SSM·2402/SSM·2412 DUAL AUDIO ANALOG SWITCHES
DICE CHARACTERISTICS
SSM·2402/SSM·2412
1.
2.
4.
6.
7.
9.
11.
13.
14.
GROUND
SWITCH 1 CONTROL
SWITCH 1 IN
SWITCH 1 OUT
V-SUPPLY
SWITCH 2 IN
SWITCH 2 OUT
SWITCH 2 CONTROL
V+SUPPLY
For additional DICE information, refer
to PMl's Data Book, Section 2.
DIE SIZE 0.105 x 0.097 inch, 10,185 sq. mils
(2.667 x 2.464 mm, 6.57 sq. mm)
WAFER TEST LIMITS atVs = ±18V, RL = OPEN, and TA = +25°C.
SSM·2402/2412
PARAMETER
SYMBOL
CONDITIONS (Note 1)
LIMIT
UNITS
Positive Supply Current
+ISY
V ,L ; O.BV
7.5
mAMAX
Negative Supply Current
-ISY
V ,L ; 0.8V
6.0
mAMAX
Ground Current
IGND
V ,L ; O.BV
1.5
mAMAX
5.0
j'AMAX
85
QMAX
5
% MAX
V ,N ;OV
Logic Input Current
ILOGIC
Switch ON Resistance
RON
IA ; ~10mA, V'L ; 2.0V
RON Match
Between Switches
RONMATCH
-14.2V .VA • +14.2V
tA ; ~10mA, V ,L ; 2.0V
Switch ON
Leakage Current
Is (aNI
-14.2V.VA. +14.2V
V ,L ; 2.0V
1.0
j'AMAX
Switch OFF
Leakage Current
IS(OFFI
-14.2V. VA. +14.2V
V ,L ; 0.8V
1.0
j'AMAX
(Note 2)
-14.2. VA. +14.2V
NOTES:
1. V, L ; Logic Conlrollnput
VA; Applied Ana(og Inpul Voltage
'A ; Applied Analog Input Current
2. Worst Case Condition
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss. yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
61
2190, Rev. A1
SSM-2402/SSM-2412 DUAL AUDIO ANALOG SWITCHES
TYPICAL PERFORMANCE CHARACTERISTICS
TOTAL HARMONIC
DISTORTION vs FREQUENCY
"OFF" ISOLATION
vs FREQUENCY
220
"ON" RESISTANCE
vs ANALOG VOLTAGE
"'"
TAz+2S-C
Vs =:t.18V
70
Vs ":l:18V
200
IA
=lOrnA
VIN .10V RMS
TA =+8S·C
iz
9:
'.0
~
~
?
II
u
0
g
60
w
160
T A ,"+2S·C-
z
t'-.
~
., 50
T~~-4o.l-
~
t'-.
140
~
40
........
120
30
0.0001 L....1..1.J.U.llL-I..l.J.Ll.WL....u.w.
10 20
100
1k
10k
,.
Vs
14
Iw
"""
SSM-2402
SWITCHING TIME
vs TEMPERATURE
SSM-2412
SWITCHING TIME
vs TEMPERATURE
........
~ r- r-
r-
,.iii
-
-20
0
40
60
80
o
100
-40
-20
tOFF
20
40
TMEPERATURE
+15'"
.. r-
..s.
VS. :l:18V
V.LaOV -
•3
iii
VA .OV
~
"uw
laN~
"~
~
It
60
...."
~
I
.1
~A" +2S-C
20
40
TEMPERATURE
60
re)
80
..
40
tOO
100
10
1k
lOOk
10k
LEAKAGE CURRENT vs
ANALOG VOLTAGE
60
I
I
!
V'L" a.sv#-
Vs ·:t18V
r-1BV Z VA Z +18V
40
70
1..
i
30
..
60
r- T. ~ .25-6
Vs
= 3:18V
f- VILa D.8V
40
U
w
20
10
V1L = 2.0V
-10
-30_
0
I'
eo
FREQUENCY (Hz)
-20
-20
:--.
100
re)
"u
-3
80
I
120
OVERVOLTAGE
CHARACTERISTICS
70
-40
140
w
Z
Z
u
0
rei
.m
."
ION
--
tOFF
20
~
--r-
15
10
~~~ '25~cl
Z
SUPPLY CURRENT
vs TEMPERATURE
..
5
Vs B:l:18V
VIN = 1GVRUS
RL .. SkC
0
«
iil
0
CHANNEL SEPARATION
vs FREQUENCY
ION
TEMPERATURE
'"
"'"u~
-5
_ v,I••1OV I
o
iii
-10
SWITCH INPUT VOLTAGE-VA (VOLTS)
160
I'-..
r--
-15
tOOk
160
;!;
..
10k
FREQUENCY (Hz)
10
-40
1k
FREQUENCY (Hz)
"
i.
100
10
~ :l:18V
~
12
100
tOOk
_
_
~
0
5
10
I
I
U
"~
30
~
20
"
!
10
-10
~
-20_
J
(
I
~
_
~
0
•
10
~
20
100
ANALOG INPUT VOLTAGE (VOLTS)
62
ANALOG INPUT VOLTAGE (VOLTS)
2190, Rev_A1
SSM-2402/SSM-2412 DUAL AUDIO ANALOG SWITCHES
TYPICAL PERFORMANCE CHARACTERISTICS Continued
SSM-2402 To tITOFF SWITCHING RESPONSE
10
---+-:I :i
OUTPUT(VO)
I
.,
I
i
. . . . ..
.•.iLfh-Tq~
~
......
!:i
g
I' '.;':
!., __ ", I,!
•
I
TONfTOFF SWITCHING RESPONSE TEST CIRCUIT
,
,
CONTROL LOGIC
i·i~ INPUT (IN,)
5'"
S,
TIME (ms)
500
V. =-o.1V'o---JW--+-...,
t----oVo
Vo =-100Vs WITH
SWITCH OPEN
SSM·2412 T ONfTOFF SWITCHING RESPONSE
SWITCH ON/OFF TRANSITION TEST CIRCUIT
OUTPUT(Vo)
10
CONTROL LOGIC
INPUTONtl
TIME(...)
5'"
8,
SWITCHING ON/OFF TRANSITION
SSM-2402
V•• -o.1VQ---./I/V'--....--!
i! ,.
i! ,.
~
~
Vo
5
'::0.1
5
~o.1
....----oVo
SSM-2412
R.
=- iiiO
(-0.1V), WHERE
RF=
Asx5tQ
Rs + 5ka
R. III swrrCH RESISTANCE
VIL • LOW TO HIGH
·OFF" ISOLATION TEST CIRCUIT
.
i! ,.
~
.j0.1
VIL. HIGH TO LOW
.
~ 10
~
:: D.'
VIL • HIGH TO LOW
'OFF' ISOLATION
63
I I
=20 LOG ~
2190, Rev. A1
SSM-2402/SSM-2412 DUAL AUDIO ANALOG SWITCHES
SWITCHING TIME TEST CIRCUIT
+1BV
RL
S'f..~~~ s,
~=+IOV
~,\
V+
VO= Vs R L • RON
LOGIC
SWrrCH
OUTPUT
VA
',dDOms
D,
0-+---'-'---0',
RL
.kg
-IBY
REPEAT TEST FOR INI
":"
INPUT
',<100mB
r
S'fN~~~
1AV
V
Vs
'Va
SWITCH
OUTPUT 0
.tOFF
tON
SIMPLIFIED SCHEMATIC
IOkD
IOkD
'.:
..
L--+-----~-_+--~~~~-~-oV-
lr : -
I
I
I'
I
I
I
I
I
I
~~V:JH I·
CONTROL I
I
I
I
I
I
IM~
I
I
I
I
MAIN
"'"
I c8:'W6~
I
~
I
I
I
":"
I
______________________ I
L~
64
2190, Rev_ A1
SSM-2402/SSM-2412 DUAL AUDIO ANALOG SWITCHES
APPLICATIONS INFORMATION
v+o-----~------~----~----~~----,
FUNCTIONAL SECTIONS
Each half of the SSM-2402/2412 are made up of three major
functional blocks:
1_
"T" Switch
Consists of JFET switches SI and S2 in series as the main
switches and switch S3 as a shunt.
2_
Ramp Generator
Generates a ramp voltage on command olthe Control Input
(see Figure 1). A LOW-to-HIGH TTL input at Control Input
initiates a ramp that goes from approximately -7V to +7V in
12ms. Conversely, a HIGH-to-LOW TTL transition at Control Input will cause a downward ramp from approximately
+7V to -7V in 12ms for the SSM-2402, and 4ms for the
SSM-2412. The Ramp Generator also supplies the +3V
and -3V reference levels for Switch Control.
3.
Switch Control
The ramp from the Ramp Generator section is applied to
two differential amplifiers (DA, and DA2) in the Switch Control block. (See Simplified Schematic). One amplifier is referenced to -3V and the other is referenced to +3V. Switch
Control Outputs are:
-
v-o-----~------~------~~--------~
.. 60pF (SSM.2402)
20pF (SSM·2412)
FIGURE 1: Ramp Generator
Main Switch Control - Drives two 0.2SmA current
sources that control the inverting inputs of each op amp.
When ON, the current sources cause a gate-to-source
voltage of approximately 2.SV which is sufficient to turn
off 5, and S2' When the current sources from Main
Switch Control are OFF, each op amp acts as a unitygain follower (VGS = 0) and both switches (S, and S2)
will beON.
HIGH
CONTROL
INPUT
~
LOW
+7V
-I
1
+3v- L - 1
RAMP
Shunt Switch Control - Controls the Shunt Switch of
the "T" configuration.
1
1
SWITCH OPERATION
Unlike conventional analog switches, the SSM-2402/2412 are
designed to ramp on and off gradually over several milliseconds. The soft transition prevents popping or clicking in audio
systems. Transients are minimized in active filters when the
SSM-2402/2412 are used to switch component values.
1
-7V
1
tON FOR
S,.S2
1- I
ON - : -
OFF
To see h.ow the SSM-2402/2412 switches work, first consider
an OFF-to-ON transition. The Control Input is initially LOW and
the Ramp Output is at approximately -7V. The Main Switch
Control is HIGH which drives current sources 03 and 04 to
O.25mA each. These currents generate 2.SV gate-to-source
back bias for each JFET switch (S, and S2) which holds them
OFF.
ON
S,
OFF
1
1
-
i -I
+1
1
I
1
1
I
1
tOFF FOR
S"S2
"1'-
:i
1
1
:
1
'--_..1._ _
1
Ir--
1
1
-1- ·f------;-I----'j
-
'OFF 1-
FOR 53
tON
FOR 53
FIGURE 2: Switch Control
The Shunt Switch Control is negative which holds the shunt
JFET S3 ON. Undesired feedthrough signals in the series JFET
switches S, and S2 are shunted to the negative supply rail
through S3'
65
2190, Rev. A 1
SSM.2402/SSM.2412 DUAL AUDIO ANALOG SWITCHES
When the Control Input goes from LOW to HIGH, the Ramp
Generator slews in the positive direction as shown in Figure 2.
When the ramp goes more positive than -3V, the Shunt Switch
Control is pulled positive by differential amplifier DA2 which
thereby puts shunt switch S3 into the OFF state. Note that 8 1
and S2 are still OFF, so at this time all three switches in the 'T'
are OFF.
The SSM·2402/2412 are much more than simple single solid·
state switches. The "T" configuration provides superb OFF·iso·
lation through shunting of feedthrough via shunt switch S3'
Break·before·make is inherent in the design. The ramp provides
a controlled gating action that softens the ON/OFF transitions.
Distortion is minimized by holding zero gate·to·source voltage
for the two main FET switches, SI and S2' using the two op amp
followers. Figure 3 shows a distortion comparison between the
SSM·2402 and a typical CMOS switch. In summary, the SSM·
2402/2412 are designed specifically for high·performance au·
dio system usage.
When the Ramp Output reaches +3V, and the drive for the Main
Switch Control output is gated OFF by differential amplifier DAI '
current sources 0 3 and 0 4 go to the OFF state and the V s of
each main switch goes to zero. The high·speed op amp fOYlow.
ers provide essentially zero gate·to·source voltage over the full
audio signal range; this in turn assures a constant low imped·
ance in the ON state over the full audio signal range. Total time
to turn on the SSM·2402 switch is approximately 10.0ms and
3.5ms for the SSM·2412.
OVERVOLTAGE PROTECTION
The SSM·2402/2412 are designed to guarantee correct opera·
tion with inputs of up to :t14.2V with:t1 BV supplies. The switch
input should never beforced to go beyond the supply rails. In the
OFF condition, if the inputs exceeds +14.2V, there is a risk of
turning the respective input pass FET 'ON. n When the input
voltage rises to within 3.BV of the positive supply, the op amp
follower saturates and will not be able to maintain the fu1l2.5V of
back bias on the gate·to·source junction. Under this condition,
current will flow from the input through the shunt FET to the
negative supply. This current is substantial, but is limited by the
FET loss. Although this current will not damage the device,
there is a danger of also turning on the output pass FET, espe·
cially if the output is close to the negative rail.
In systems using a large number of separate switches, there are
advantages to having faster switching into OFF state than into
the ON state. Break·before·make can be maintained at the
system level. To see how the SSM·2402/2412 guarantee
break·before·make, consider the ON·to·OFF transition.
A Control Input LOW initiates the ON·to·OFF transition. The
Ramp Generator integrates down from approximately +7V to·
wards -7V. As the ramp goes through +3V, the comparator
controlling the Main Switches (SI and S2) goes HIGH and turns
on current sources 0 3 and 0 4 which thereby puts SI and S2 into
the OFF state. At this time, all switches in the "T" are OFF. When
the ramp integrates down to -3V, the Shunt Switch Control
changes state and pulls shunt switch S3 into the ON state. This
completes the ON·to·OFF transistion; SI and S2 are OFF, and
S3 is ON to shunt away any undesired feedthrough. Note though
that the ON·to·OFF time for main switches SI and S2 is only the
time interval required for the ramp to go from +7V to +3V, about
4ms for the SSM·2402, and 1.5ms for the SSM·2412. The time
to turn on is about 2.5 times as long as the time to turn off.
This risk of signal "breakthrough' for inputs above +14.2V can
be eliminated by using a source resistor of 100·5000 in series
with the analog input to provide additional current limiting.
Near the negative supply, transistors 0 3 and 0 4 saturate and
can no longer keep the switch OFF. Signal breakthrough can·
not happen, but the danger here is latch·up via a path to Vthrough the shunt FET. Additional circuitry (not shown) has
been incorporated to turn OFF the shunt FET under these con·
ditions, and the potential for latch·up is thereby eliminated.
TYPICAL CONFIGURATION
~~~~l
LOW. OFF
o---'::"'-=;-
• OPTIONAL INPUT RESISTORS
SEE SECTION ON OVERVOLTAGE PROTECTION
... opnONAL LOAD RESISTORS
LOWER VAWES WILL MINIMIZE 'CUCKS' BUT WITH A IOV ••• INPUT
IT IS RECOMMENDED THAT THEY BE GREATER THAN 2110
66
2190, Rev. A1
SSM-24D2ISSM-2412 DUAL AUDIO ANALOG SWITCHES
SSM·240212412
OR CMOS SWITCH
IN o----<~--...,.....
j
_
..,....s, ~ OUT
+-R_'_ _
10kO
20(»(0
2kO
FIGURE4
= 20Vp-p
f= 10Hz
' " VIN
IN
SSM·2402
o----/VI/'------F......-o your
FIGURE 2: Precision Unity-Gain Inverting Amplifier
-1""
APPLICATIONS INFORMATION
The SSM-2141 represents a versatile analog building block. In
order to capitalize on fast settling time, high slew rate, and high
CMR, proper decoupling and grounding techniques must be
employed. For decoupling, place O.1IlF capacitor located within
close proximity from each supply pin to ground.
MAINTAINING COMMON-MODE REJECTION
In order to achieve the full common-mode rejection capability of
the SSM-2141, the source impedance must be carefully controlled. Slight imbalances of the source resistance will result in
a degradalion of DC CMR - even a 50 imbalance will degrade
CMR by 20dB. Also, the matching of the reactive source impedance must be matched in order to preserve theCMRR over frequency.
FIGURE 3: Precision Summing Amplifier
APPLICATION CIRCUITS
SSM·2141
R,
-IN E, o-.:.t--N"'--4~~NI/'---f:'"
25kQ
FIGURE 4: Precision Summing Amplifier with Gain
25kQ
FIGURE 1: Precision Difference Amplifier. Rejects Common-
Mode Signal = [E, + E21 by 1DDdB
2
73
2190, Rev. A2
SSM-2141 HIGH COMMON-MODE REJECTION DIFFERENTIAL LINE RECEIVER
E,
-IN
>---I"-.....O~'1..TPUT
E,
,IN
FIGURE 5: Suitable instrumentation amplifier requirements
can be addressed by using an input stage consisting of A l'
A 2 , RI and R2 ,
74
2190, Rev. A2
SSM-2142
BALANCED
LINE DRIVER
Precision Monolithics Inc.
ADVANCE PRODUcr INFORMATION
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
The SSM-2142 is a fully integrated processing block used to
derive precision balanced outputs from a single-ended input in
high performance audio systems. The output, which drives a
600n load from a 1oV RMS signal, functions very similar to transformer-based circuits. Low gain error and high slew rate further
enhance the SSM-2142, making it the ideal output device in
systems requiring balanced or differential outputs with high
drive capability.
Transformer-Like Output
Drives 1OV RMS Into a 600n Load
Low Gain Error (Differential or Single-Ended) .•••• < 0.1%
Low Supply Current (Quiescent) ...•.....•.....•....... SmA Max
High Slew Rate .•.......••..•..•.......•••....••••....•.......•••....•.• 15V/~s
Short-Circuit Protected Outputs
Space Saving S-Pln Mini-DIP
No External Components Required
TYPICAL APPLICATION
APPLICATIONS
•
•
•
•
•
•
Audio Mix Consoles
Graphic and Parametric Equalizers
Dynamic Range Processors
Digital Effects Processors
High Performance HI-FI
Instrumentation Equipment
+OUTA
-OUTe
S-PIN PLASTIC DIP
(P-Sufflx)
ORDERING INFORMATION
PACKAGE
PLASTIC
a-PIN
OPERATING
TEMPERATURE
RANGE
SSM2142P
XINO'
• XI NO = -40'C to +85'C
BLOCK DIAGRAM
100
>-....~N---o
.OUTFORCE
+OUTSENSE
-OUT SENSE
>-....hlVlJo--o -OUT FORCE
eND
This advance product Information describes a product In development allhatima olthls printing. Final specifications may vary. Please contact local sales ollice
or distributor for final data shaat.
75
10/89, Rev. A
SSM-2131
ULTRA-LOW DISTORTION,
ffiGH-SPEED AUDIO OPERATIONAL AMPLIFIER
Precision Monolithics Inc.
FEATURES
•
•
•
•
•
The SSM-2131 's common-mode rejection of aOdS minimum
over a±11 range is exceptional for a high-speed amplifier. High
CMR, combined with a minimum 500V/mV gain into a 1Okn load
ensures excellent linearity in both noninverting and inverting
gain configurations. This means that distortion will be very low
over a wide range of circuit configurations. The low offset provided by the JFET input stage often eliminates the need for AC
coupling or for external offset trimming.
Low Distortion - DC to 40kHz, Av =+10 ...••..... 0.01 % Typ
High Slew Rate .................................................. 40V/IlS Min
Gain-Bandwidth Product ................................. 10MHz Typ
High Gain ......................................................... 200,000 Typ
Common-Mode Rejection .................................. SOdB Min
APPLICATIONS
•
•
•
•
•
•
•
TheSSM-2131 conformstothestandard 741 pinout with nulling
to V-. The SSM-2131 upgrades the performance of circuits
using the AD544, AD611 , AD711 , and LF400 by direct replace·
ment.
Power Amplifier Driver
Active Filter Circuits
Parametric Equalizers
Graphic Equalizers
Mixing Consoles
Voltage Summers
Active Crossover Networks
PIN CONNECTIONS
PLASTIC MINI-DIP
(P-Suffix)
GENERAL DESCRIPTION
The SSM-2131 is a fast JFET input operational amplifier intended for use in audio applications. The SSM-2131 offers a
symmetric 50V/IlS slew rate for low distortion and is internally
compensated for unity gain operation. Power supply current is
less than 6.5mA. Unity-gain stability, a wide full-power bandwidth of 800kHz, and excellent ability to handle transient overloads make the SSM-2131 an ideal amplifier for use in high performance audio amplifier circuits.
S-PINSO
(S-Suffix)
SIMPLIFIED SCHEMATIC
.---~--------------~----~~----~~---ov
• IN
0---------------+------1-----------,
-IN
0-_-£:=
.
~---r--+-----~----~--------~~----~------~--~vNULL
NULL
76
2190, Rev. A2
SSM-2131 ULTRA-LOW DISTORTION, HIGH-SPEED AUDIO OPERATIONAL AMPLIFIER
Output Short-Circuit Duration .................................... Indefinite
Storage Temperature Range ........................ -65°C to +175°C
Operating Temperature Range ........................ -40°C to +85°C
Junction Temperature ................................... -65°C to + 175°C
Lead Temperature Range (Soldering, 60 sec) ............ +300°C
ORDERING INFORMATION
PACKAGE
PLASTIC
S-PIN
SO
S-PIN
OPERATING
TEMPERATURE
RANGE
SSM2131P
SSM2131S
XIND·
PACKAGE TYPE
·XIND ~ -40'C to +S5'C
8JA (Note 2)
8 1e
UNITS
S·Pin Plastic DIP (P)
103
43
'CrN
8·PinSO(S)
158
43
'erN
NOTES:
1. For supply voltages less than ±20V. the absolute maximum input voltage is
equal to the supply voltage.
2.' 8jA is specilied lor worst case mounting conditions. i.e .• 9jA is specified lor
device in socket lor P·DIP packages; 8jA is specified lor device soldered to
printed circuit board lor SO package.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................................. ±20V
Input Voltage (Note 1) ...................................................... ±20V
Differential Input Voltage (Note 1) ..................................... 40V
ELECTRICAL CHARACTERISTICS at Vs =±15V, TA = 25°C, unless otherwise noted.
SSM-2131
CONDITIONS
PARAMETER
SYMBOL
Slew Rate
SR
Gain·Bandwidth
Product
GBW
10= 10kHz
Full·Power
Bandwidth
BWp
(Note 2)
Total Harmonic
Distortion
THO
DC to 40kHz,
Voltage Noise Density
en
10= 10Hz
10= 1kHz
Current Noise Density
in
10= 1kHz
MIN
TYP
40
50
V/)lf'
10
MHz
800
kHz
0.01
0/0
38
13
nVlv'Ri
600
f\ = 10k!!, A., = +10
MAX
UNITS
0.007
pAlv'Ri
500
200
100
900
260
170
V/mV
±11.5
+12.5
-11.9
V
large·Signal
Voltage Gain
Avo
RL: 10k!! Vo =±10V
RL - 2k!! T. = 25'C
RL=Ik!! J
Output Voltage
Swing
Vo
RL=Ik!!
Offset Voltage
Vos
1.5
6.0
mV
Input Bias Current
Ie
VCM=OV Tj =25'C
130
250
pA
Input Ollset Current
los
VCM=OV Tj =25'C
6
50
pA
±11.0
+12.5
-12.0
V
80
92
dB
Input Voltage Range
IVR
(Note 1)
Common·Mode
Rejection
CMR
VCM .dl1V
Power·Supply
Rejection Ratio
PSRR
Vs =±10Vto±20V
12
50
I1VN
Supply Current
ISY
No load
Vo=OV
5.1
6.5
rnA
Short·Circuit
Current Limit
Ise
Output Shorted to Ground
+33
-28
±SO
rnA
SeltlingTime
t.
10V Step 0.01 % (Note 3)
0.9
1.2
I1s
Overload Recovery
Time
±20
700
tOR
77
ns
2190, Rev. A2
SSM·2131 ULTRA·LOW DISTORTION, HIGH·SPEED AUDIO OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS at Vs
=:t15V, TA =25·C, unless otherwise noted. Continued
SSM·2131
PARAMETER
SYMBOL
CONDITIONS
Phase Margin
"0
OdB Gain
Gain Margin
A IBO
180· Open· Loop
Phase Shift
Capacitive Load
Drive Capabilily
CL
Unily-Gain Stable
(Note 4)
Supply Voltage Range
Vs
MIN
TYP
MAX
UNITS
47
degrees
9
dB
100
300
pF
,,8
,,15
,,20
V
MAX
UNITS
NOTES:
1. Guaranteed by CMR test.
2. Guaranteed by slew·rate test and formula BW p = SR/(2nl0VpEAK)'
3. Settling time Is guaranteed but not tested.
4. Guaranteed but not tested.
ELECTRICAL CHARACTERISTICS at VS =:t15V, -40·C :!: T A:!: a5·C, unless otherwise noted.
SSM·2131
PARAMETER
SYMBOL
CONDITIONS
Slew Rate
SR
RL =2kC
Large-Signal
Voltage Gain
Avo
RL = 10kC (Note 1)
RL =2kC Vo =,,10V
Output Voltage
Swing
Vo
RL =2kC
Offset V?ltage
Vos
Offset Voltage
Temperature Coefficient
TCVos
Input Bias Current
18
(Note 1)
0.6
2.0
nA
Input Offset Current
los
(Note 1)
0.06
0.4
nA
,,11.0
+12.5
-12.0
V
80
94
dB
MIN
TYP
40
50
V/flS
200
100
500
160
V/mV
,,11.0
+12.3
-11.8
V
2.0
7.0
8
Input Voltage Range
IVR
(Note 2)
Common-Mode
Rejection
CMR
VCM ="l1V
Power-Supply
Rejection Ratio
PSRR
Vs =,,10Vto,,20V
Supply Current
ISY
Short-Circuit
Current Limit
Isc
No Load
Vo=OV
Oulput Shorted to Ground
,,8
mV
flVrC
6
50
flVN
5.1
6.5
mA
,,60
mA
NOTES:
1. T j = 85·C.
2. Guaranteed by CMR test.
78
2190, Rev. A2
SSM·2131 ULTRA·LOW DISTORTION, HIGH·SPEED AUDIO OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM OUTPUT SWING
vs FREQUENCY
DISTORTION
vs FREQUENCY
VOLTAGE NOISE DENSITY
vs FREQUENCY
200
30.-rrnn~~~m-~MTmr~~mm
~~Em'
~~'~~M k~,~~
251;$*t;!.1;;*~1,-I-U
~
125
2
illa
100
~
~
0.1
Z
Ii:
"
TA _u'e
Vs =-.tSV
~ 150
5
g
'mg-
17.
~
0.01
75
:'l
~
so
g
r\
25
o
100
1k
10k
10k
100k
Vs =:l:15V
50
~
id :
A VCL • +10
AvCL = +5
"
e:
\
I
\.\\
\\..
I
I
-20
-30
10
100
1k
40
y'
AvCL· +10
1
/
\
I
10k
100k
1M
FREQUENCY (H.2)
10U
100
l
~
~
n-r
100k
I
~
5.
54
r--..
TA _+25"C
Vs _",15V
50
I
:i
......... r--... NEClAnVE
. . . r--, l-
52
J- RL
T-
p~
V
40
~
.~
30
20
,. /v
o~
48
-.25
25
50
TEMPERATURE (",C)
75
100
.2110:
~
50
-so
135
40
180
"e.
20
225
:l'"
0
270
i
125
o
V
./
10M
10
/
V
100
111.
10k
tOOk
111
FREQUENCY (Hzl
Vs • *15V
I-RL .2kO
4
IIf"
-2
i!
-4
~
"
0.&
0.1
79
10011
I-!A _+2S·C
'"
:!
!I
DIFFERENTIAL INPUT VOLTAGE (VOLTS)
1011
SLEWRATEvs
CAPACITIVE LOAD
,.
l
V
0.4
if
-20
NEGAnYE
~
1.0
r-
p~ ~
f'.:
-0
-8
-1.
0.2
m
a:
-so L....-l.._-'-....L....-..l.._-'-....L........I
111
so
........
.~
SLEW RATEvs
DIFFERENTIAL INPUT VOLTAGE
Ri.. _2110-
58
40
-75
10k
1k
Vs _"t5V
f'..
50
60
FREQUENCY (Hz)
64
.0
~rl---+--I---l--+--+---l
iD .0
0
Y.L. ?/~/
o
100M
~
"J I I
/J J
AvCL-+100
20
SLEWRATEvs
TEMPERATURE
.2
tOOk
l!.
AvcL. +5
!
~
=+1
so
'"uz
.\veL- +1
-10
t
20k
OPEN·LOOP GAIN,
PHASE vs FREQUENCY
120
AvcL
-I
0
10k
1k
100 ~~~-l---l---I--+--+---1
I
30
100
10
FREQUENCY (Hz)
TA • 25'C
Vs _,.,15V
.0
AvCL = +100
iD
!!. 40
1
140 . - - - - , - - . , . - - , - -•.,..-.,....-..----.
I
I
TA = +25·C
60
IOU
1M
CLOSED·LOOP OUTPUT
IMPEDANCE vs FREQUENCY
CLOSED·LOOP GAIN
vs FREQUENCY
70
100k
FREQUENCV (Hz)
FREQUENCY (Hz)
o
100
2011
30D
CAPACmvE LOAD (PFJ
r"::
...
2190, Rev. A2
SSM-2131 ULTRA-LOW DISTORTION, HIGH-SPEED AUDIO OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS Continued
SMALL-SIGNAL OVERSHOOT
vs LOAD CAPACITANCE
Vs .,,15V
RL .. 2kD
I.
7.
YIN .100mVp-p
I
AVCL"' +1
-NEGATIVEED~/
/
..,.
//
•
•
hV
.......:
'"
--
....-
AVCl- .,
POSITIVE EDaE
-
AYCL&·S
AVCL-·,D
ii
l?
z
"~
200
300
400
."
OJ
~
"....""
z
"u
..
I .•
[;
"
AYCL • • 1
_.
.
.PSR
'\
............
1\
" "'- ,
\
-PSR
••
T.&.25·C
VS·:tlSV
,
'00
1t
10k
FREQUENCY (H:r:)
'OOk
,..
•,.
lk
'00
10k
'OOk
'"
FREQUENCY (H.J:)
SUPPLY CURRENT vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs TEMPERATURE
r--r-,---r-"'T'"-'-""'-"'---'
&..
...
NO LOAD
5.•
i
.!i:
~
~
"
u
,.
SA
T._-55·C TA=+2rc-
Q
5.'
~ 5..
V
,.
'.1 I--+-+--l-+-+--+--!--I
100
'.k
It
SETTLING-TIME
vs STEP SIZE
~
·b
I
.
4
~
~
~
BIAS CURRENT vs
JUNCTION TEMPERATURE
,0'
Vs • *15V
VCM .ov
/0.0'%
I
\
0.1"
I"
1\
\
-R
200
40D
SETTUNG-TiME
i
Iii
./
~
~
.."
...
*"
BIAS CURRENT vs
COMMON-MODE VOLTAGE
I
./
,0'
u
5
\
800
" ,.'
,.'
0.01"
1\
(n,'
*'2
SUPPLY VOLTAGE (VOLTS)
,0'
.....
-I
*8
::Vs ••15V
=TJ ••25"C
I
,
1-_
.
4A
~
TEIIPERATURE reI
,.'
II
/0.,%
iiiIi; -2•
.•
~
TAc +125·C-
_.8
...
u'--'--..I---1_-'-_.l--I._..l---l
_
50
n
I
"vel -.,
~
•.• t--+-+--l-+-+--+--!--I
~
TO •••
Vs .s:15Y
-,
50
it
"~
."
-+--1f-+-+--+--l
5 .• 1--+-+---1-+-r-+-+--l
LOAD RESISTANCE (D)
..iii~
!;
VS&:l:15V
. '0 • 1kHz
,% DISTORTION
,.
~
I.
I
\
5.8
1:
••
i!.
"!Oz ,.
.5
~
.....
;
50
OUTPUT SWING
••
......
z
7•
LOAD CAPACITANCE IPFI
Vs ·t:15V
..
,
l?
...... 1'\..
.
500
IIIll
T A &+25-C
ii
9.
vs LOAD RESISTANCE
3.
Vs • &15V
,
POWER-SUPPLY REJECTION
vs FREQUENCY
12.
TA _.25·C
11.
50
100
COMMON-MODE
REJECTION vs FREQUENCY
12.
9.
...
..
,
-75
-so
-25
25
50
75
JUNCTION TEMPERATURE reCi
80
too
125
.. .
, -,
-10
-5
,.
15
COMMON-MODE VOLTAGE (VOLTS)
2190, Rev. A2
SSM-2131 ULTRA-LOW DISTORTION, HIGH-SPEED AUDIO OPERATIONAL AMPLIFIER
APPLICATIONS INFORMATION
OFFSET VOLTAGE ADJUSTMENT
Offset voltage is adjusted with a 1OkQ to 100kQ potentiometer
as shown in Figure 3. The potentiometer should be connected
between pins 1 and 5 with its wiper connected to the V- supply.
The SSM-2131 combines speed with a high level of input precision usually found only with slower devices. Well-behaved AC
performance in the form of clean transient response, symmetrical slew rates and a high degree offorgiveness to supply decoupiing are the hallmarks of this amplifier. AC gain and phase
response are quite independent of temperature or supply voltage. Figure 1 shows the SSM-2131's small-signal response.
Even with 75pF loads, there is minimal ringing in the output
waveform. Large-signal response is shown in Figure 2. This
figure clearly shows the SSM-2131's exceptionally close matching between positive and negative slew rates. Slew rate symmetry decreases the DC offset a system encounters when processing high-frequency signals, and thus reduces the DC current
necessary for load driving.
Alternately, Vos may be nulled by attaching the potentiometer
wiper through a 1MQ resistor to the positive supply rail.
v+
vALTERNATE METHOD
vSTANDARD METHOD
NOTE:
Vos CAN BE TRIMMED WITH
POTENTIOMETER RANGING
FROM 10ke TO 100kC
*
USE SMALLER VALUE FOR
WIDER TRIM RANGE
FIGURE 3: Input Offset Voltage Nulling
VOLTAGE SUMMING
Because of its extremely low input bias current and large unitygain bandwidth, the SSM-2131 is ideal for use as a voltage
summer or adder.
FIGURE 1: Small-Signal Transient Response, ZL = 2kQII75pF
The following figures show both an inverting and noninverting
voltage adder.
R,
\'IN1
11~
\'IN2
12R;+
"'.Nl
',-
FIGURE 2: Large-Signal Transient Response, ZL = 2kQII75pF
As with most JFET-input amplifiers, the output ofthe SSM-2131
may undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion will not damage the
amplifier, nor will it cause an internal latch-up.
FIGURE 4: Inverting Adder
Supply decoupling should be used to overcome inductance and
resistance associated with supply lines to the amplifier.
For most applications, a 0.1 ~F to 0.01 ~F capacitor should be
placed between each supply pin and ground.
81
2190, Rev_ A2
SSM-2131 ULTRA-LOW DISTORTION, HIGH-SPEED AUDIO OPERATIONAL AMPLIFIER
the overall amplifier is more than adequate at 300V//ls and is responsible for ,the very low dynamic intermodulation distortion
(OIM-1 00) that was measured at just 0.0017% at 50 watts output into ohms. The total amplifier idling current for all tests was
approximately 300mA; the V+IV++ and V-/V- power supplies
were both ±40V; and the gain was set to 24.0.
YIN, cr.-~#-.,
a
YIH'o-~#-"
In a current feedback amplifier, a unity or low gain input buffer
drives a low impedance network. Any differential current that
flows in the collectors of the buffer (SSM-2131) output transistors is fed, via the two complementary Wilson current mirrors A
and B, to a high impedance gain node where the high output
voltage is generated.
FIGURE 5: Noninverting Adder
This voltage is then buffered by a double emitter follower driver
stage and fed to the complementary power MOSFET output
stage. No RC compensation network to ground or output inductor is required at the output of this amplifier to make it stable. As
the 100kHz square wave response shows, there's no evidence
of any instability in the circuit. Capacitive load compensation
can be provided by the components marked TBO on the amplifier schematic. These were not used in the test, however.
CURRENT FEEDBACK AUDIO POWER AMPLIFIER
The SSM-2131 can be used as the input buffer in a current feedback audio power amplifier as shown in Figure 6. This design is
capable of very good performance as shown in Figures 7, and
9. At 1kHz and 50 watts output into an
load, the amplifiergenerates just 0.002% THO, and is flat to 1MHz. The slew rate for
an
a
Y+o--~-------------=-~_-_-_-=_~_~_-_-=_--------~~---~-.
I
20kQ
2).1F
POLY.OOY
v+
WILSON CURRENT
MIRROR A
ALL RESISTORS.% NF,14 W
UNLESS OTHERWISE NOTED
.N965B
MPSU10
(ON HEATSINK)
.000
+.~~~-~~~~~~
INPUT
+
1
+--....~..........,.....- ......_l. 2N540.
'----f---~-I:)I-..........
MPSU60
(ON HEATSINK)
• MOUNTED ON
OUTPUT HEATSINK
I WILSON CURRENT
I MIRRORB
I
.000 I
I
__ I
~o--~------------~~~~~~~~---------+_---~
I
2>-....-r:.
OUTPUT
SUBSTRATE
89
10/89, Rev. A
SSM·2134 LOW NOISE AUDIO OPERATIONAL AMPLIFIER
Power Dissipation ........................................................ 300mW
Derate Above +24·C ............................................. 2.SmW'·C
Short·Circuit Duration (Note 3) ................................. Indefinite
Operating Temperature Range ....................... -40·C to +8S·C
Storage Temperature .................................... -SO·Cto +1S0·C
ORDERING INFORMATION
PACKAGE·
PLASTIC
a·PIN
OPERATING
TEMPERATURE
RANGE
SSM2134P
XIND'
NOTES:
I. The SSM-2134's Inputs are protected by diodes. Current limiting resistors are
not used in order to achieve low noise. If differential input voltage exceeds
±C.SV, the input current should be limited to 10mA.
2. For supply voltages less than ±22V, the absolute maximum input voltage is
equal to the supply voltage.
3. Output maybe shorted to ground atVs =±15V, TA =+25'C. Temperatureandl
or supply voltages must be limited to ensure dissipation rating is notexceeded.
'XIND = -40'C to +85'C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................................. ±22V
Differential Input Voltage (Note 1) .................................. ±O.SV
Input Voltage (Note 2) ...................................................... ±22V
ELECTRICAL CHARACTERISTICS at Vs = ±1SV and TA = +2S·C, unless otherwise noted.
SSM·2134P
PARAMETER
Input Offset Voltage
Input Offset Current
SYMBOL
Vos
) los
Input Bias Current
Ie
large-Signal Voltage Gain
Avo
Supply Current
CONDITIONS
TYP
MAX
UNITS
-40'C s T AS +85'C
0.3
0.4
2
3
mV
-40'C S T AS +85'C
15
25
300
400
nA
-40'C sTAS +85'C
350
500
1500
2000
nA
Rl "600n. Vo =±IOV
25
200
Rl"SOOn. Vo =±IOV
-40'C S T AS +85'C
15
150
±12
±15
±13
±IS
V
60
mA
30
100
kn
±12
±13
V
70
114
dB
ISY
No load
Output Voltage Swing
Vo
V s a±15V.Rl ,,600n
VS =±18V, Rl ,,600n
Output Short·Circuit Current
Isc
(Note I)
Input ResistanceDifferential-Mode
RIN
(Note 2)
Input Voltage Range
IVR
Common· Mode Rejection
CMR
MIN
VlmV
4.5
VCM =±12V
6.5
mA
Power Supply Rejection Ratio
PSRR
Rise Time
t,
Rl "soon. C c = 22pF
20
ns
Overshoot
OS
Cl = loopl'
20
%
6
2.2
V/mV
Cc = O. fo = 10kHz
Cc = 22pF. fo = 10kHz
ACGain
Unity-Gain Bandwidth
6
100
(J.VIV
GBW
Cc =22pF,C l =100 pF
10
MHz
Slew Rate
SR
Cc=O
Cc = 22pF
13
6
V/(J.S
Full Power Bandwidth
BWp
Cc=O
95
200
kHz
Input Noise Voltage Density
en
fo = 30Hz
fo = 1kHz
5.5
3.5
Input Noise Current Density
in
fo = 30Hz
fo= 1kHz
2.5
O.S
pAifiz
0,7
dB
0.025
%
Vo _±IOV. C c - 22pF
Broadband Noise Figure
FN
Rs = 5kn. f = 10Hz to 20kHz
Total Harmonic Distortion
THO
VIN = 3VRMS ' Av = +1000. Rl = 2kn
NOTES:
1. Output may be shorted to ground at Vs =±15V. T A = +25'C. Temperature andl
or supply voltages must be limited to ensuredissipation rating is not exceeded.
2. Guaranteed by design.
7.0
4.5
nVi-/Hz
Specifications subject to change. Consult latest data sheet.
90
10/89, Rev. A
SSM-2134 LOW NOISE AUDIO OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE DENSITY
vs FREQUENCY
CURRENT NOISE DENSITY
vs FREQUENCY
,···.mIiI
BROADBAND INPUT
NOISE VOLTAGE
'.' .------.....----.----,
~a·~=EI!tH~~~Eff~~~~?E
~
TA= .25·C
Vs",*'SV
TA" +25·C
Vs"':t15V
'-
'.. ~~
..
,.
..
,
,~,L---J----L--~--~
,0'
,02
,
•. , 1-....I.....u..I.J..I.1lL..--'....L..LJ..1.1JJL_-'-'.J...J.J..LW
1k
FAEQUENCY (H:r:)
TOTAL INPUT NOISE DENSITY
'.'
TA" +25·C
,.'
~
. /v,:;Y
V
~
~ '.',.
/: ~
"
w
~
z
--
!;
~
!
~
I!
g
10-1
10-2:
,.
,.
,
= :::::::::: r-...
i
""" "'\
~ 4.
a.
CC" 22pF
w
'.'
.
,
'.'
104
AsIO)
....
~ 1\/1" Ceai"
,.
X"T Cc a 'I'"
!;
S
~l(\
,.
'00
1(10
Ik
10k
tOOk
lOOk
-
Cc • 47pF -
1M
FREQUENCY (Hz)
IOU
1M
10M
100M
".1=
..
,
••
••
~!I. +25'C
VS"':l:ISV
II
r...
104
•
'00
J-_~
f05
__
1011
~_~
107
108
PSR vs FREQUENCY
TA
i\
..
~
+PSR
T
-pJA
'\
.
!'
J.~~·c
VS·:I:'5Y
'"
7.
i'
•
4.
•
100M
103
FREQUENCY (Hz)
a.
~~
10k
9
u
CMR vs FREQUENCY
\.\ \
,.
"":'; ,.
~
FREQUENCY (Hz)
• r-
I _
4•
z
~
14
30
ii"
!1.
_,.L__-L__
10
OUTPUT VOLTAGE SWING
vs FREQUENCY
vsar'5V -
0
CL·lOpF
1'0
TA'" +25·C
~
"!
RL:a 600D
>
,oJ
.. .----,----,--"T""----.----,
"'-'r-...
0
'.'
TA= +25'C
Vs," ..15V
~c=OPF
"~
VrHERMAL NOISE OF
SOURCE RESISTANCE
'.'
RsIC)
CLOSED-LOOP GAIN
vs FREQUENCY
OPEN-LOOP GAIN
vs FREQUENCY
".
'.H~
VS=:l:15V
'.'
FREQUENCY (Hz)
1'-
4C
,.
10k
tOOk
FREQUENCY (Hz)
91
'M
,.M
30
'00
Ik
10k
tOOk
'M
FREQUENCY (Hz)
10/89, Rev. A
SSM-2134 LOW NOISE AUDIO OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS Continued
SLEW RATEvs
COMPENSATION CAPACITOR
16
12
l~
I" ........
...........
t--
2.
40
60
CC(pF)
--..
••
,
TOTAL HARMONIC DISTORTION vs FREQUENCY
TOTAL HARMONIC DISTORTION vs FREQUENCY
TOTAL HARMONIC DISTORTION vs FREQUENCY
TOTAL HARMONIC DISTORTION vs FREQUENCY
92
10/89, Rev. A
SSM-2134 LOW NOISE AUDIO OPERATIONAL AMPLIFIER
TYPICAL PERFORMANCE CHARACTERISTICS Continued
INPUT COMMON-MODE
VOLTAGE vs SUPPLY VOLTAGE
OUTPUT VOLTAGE SWING
vs LOAD RESISTANCE
30
16
I
I.
NEGAnVE
TA" +2S'C
VS=:t15V
POSITIVE
;;;
~
0
a
"~
12
10
~
~
e
;;;
~
fi
II
.
0
20
a
~"
.
~
~
~
10
~
~
~
TA ...2S·C
Vr'I':'~
2
100
lk
10k
o
A~·jV
tOOk
~
o
:1:10
INPUT OFFSET VOLTAGE
vs TEMPERATURE
0.3
0
>
i
D••
C
'"
0.2
~
0.1
-55
-25
.
.~
.S
~
ill
~
~
110
.l!
0
0
0 ••
~
u
"
$2
:14
"'- r- y
25
50
75
TEMPERATURE 1°C)
100
.......... 1-..
0.4
..........
~
0.2
125
26
:1:8
... 10 :1:12 .2:14 :t16 :1:'8 :1:20
CMR vs TEMPERATURE
130
Vs.l,5V
120
"
o
SUPPLY VOLTAGE (VOLTS)
INPUT BIAS CURRENT
vs TEMPERATURE
VS=I:t'5V
"~
o
... 20
1.0
•
--
I- I--
V
SUPPLY VOLTAGE (VOLTS)
0.5
D••
i.,...- l-
'/
LOAD RESISTANCE (n)
..S r--...
TA. +2S'C
POSITIVE-
g
0
;;-
SUPPLY CURRENT
vs SUPPLY VOLTAGE
Ii
100
"u
90
.
-
VS=:tISV
~
--
aD
70
o
&D
-25
-55
0
25
SO
TEMPERATURE
75
100
125
-5'
re,
50
75
100
125
TEMPERATURE (OC)
SHORT-CIRCUIT CURRENT
vs TEMPERATURE
SUPPLY CURRENT
vs TEMPERATURE
PSR vs TEMPERATURE
25
"5
aD
VS",.,'5V
VS. :I!'SV
V
V
......
,V
V
VS·:tI5V
-
l....-
j.....-
-~
1
.
~
B 40
......
r-.....
1"'- f..-.
S
~
20
o
-55
-25
0
25
50
75
TEMPERATURE ("C)
100
125
-55
-25
25
50
75
TEMPERATURE ("C)
93
IDO
125
-55
-25
25
50
75
100
125
150
TEMPERATURE ("CI
10/89, Rev. A
SSM·2134 LOW NOISE AUDIO OPERATIONAL AMPLIFIER
APPLICATIONS INFORMATION
PREAMPLIFIER-RIAA/NAB COMPENSATION
INPUT~2PF
>-_-0 OUTPUT
lAsL
fI
NAB
1.1MQ
16kQ
O.OO3F
·SELECT TO PROVIDE SPECIFIED TRANSDUCER LOADING
OUTPUT NOISE O.8mV RMS (WITH INPUT SHORTED)
70
60
70
PL~T
1-'-,
BODE
60
50
Iii'
50
"
40
~
Ii
\
~
30
20
I
I~CTUAL "ESPONSE BODE PLOT
40
"
'~
~
~
ACTUAL
RESPONSE _
~r-
3D
20
10
10'
. . -~~
,
10
102
103
104
105
10'
103
104
FREQUENCV (Hz)
FREQUENCY (HZ)
BODE PLOT OF RIAA EQUALIZATION AND THE
RESPONSE REALIZED IN AN ACTUAL CIRCUIT
USING THE SSM·2134
"
'\
102
105
BODE PLOT OF NAB EQUALIZATION AND THE
RESPONSE REALIZED IN THE ACTUAL CIRCUIT
USING THE SSM.2134
TEST CIRCUIT
FREQUENCY COMPENSATION
AND OFFSET VOLTAGE
ADJUSTMENT CIRCUIT
CLOSED-LOOP FREQUENCY RESPONSE
v+
22kD
RS
.sa
vR,
I'OOPF
6000
v-
94
10/89, Rev. A
SSM-2139
DUAL, LOW NOISE, illGH-SPEED
AUDIOOPERATIONALAMPUFIER(AyCL~3)
'ptg'MiI;,irlMfflimMi,'
GENERAL DESCRIPTION
FEATURES
• Ultra-Low Voltage Noise .................................. 3.2nV/-IHz
• High Slew Rate •.•..•.•••.•.....•.....•.•.....••.....•........•.•....... 11V/IlS
• Excellent Gain Bandwidth Product ....................... 30MHz
• Low Supply Current (Both Amplifiers) ...................... 4mA
• Low Offset Voltage ................................................... 500llV
• High Gain ........................................................... 1,700V/mV
• Compensated for Minimum Gain of 3
• LowCost
• Industry Standard a-Pin Plastic Dual Pinout
The SSM-2139 is a low noise, high-speed dual audio operational amplifier which has been internally compensated for
gains equal to, or greater than three.
This monolithic bipolar op amp offers exceptional voltage noise
performance of 3.2nV/..,(Hz (typical) with a guaranteed specifi·
cation of only 5nV/..,(Hz MAX @ 1kHz.
The high slew rate of 11 V/IlS and the gain-bandwidth product of
30MHz is achieved without compromising the power consumption of the device. The SSM·2139 draws only 4mA of supply current for both amplifiers.
Continued
APPLICATIONS
• Microphone Preamplifiers
• Audio Line Drivers
• Active Filters
• Phono and Tape Head Preamplifiers
• Equalizers
PIN CONNECTIONS
ORDERING INFORMATION
PACKAGE
PLASTIC
B-PIN
16-PIN
SOL
OPERATING
TEMPERATURE
RANGE
SSM2139P
SSM2139S
XIND"
a-PIN
PLASTIC MINI-DIP
(P-Sufflx)
16-PIN SOL
(S-Sufflx)
" XIND = -40'C to +8S'C
For availability on SOL package. contact your local sales office.
SIMPLIFIED SCHEMATIC (One of two amplifiers is shown.)
r-.-------~----~----~--~----------------------~~~~--~~~
OUT
~--------------~~~--------~~--------~--~--~~--~-o~
95
10/89, Rev. A1
SSM·2139 DUAL LOW NOISE, HIGH·SPEED AUDIO OPERATIONAL AMPLIFIER
These characteristics make the SSM·2139 an ideal choice for
use in high quality professional audio equipment, instrumenta·
tion, and control circuit applications.
Input Voltage .................................................... Supply Voltage
Output Short-Circuit Duration ................................ Continuous
Storage Temperature Range ......................... -65°C to + 150C
Lead Temperature Range (Soldering, 60 sec) .............. 300°C
Junction Temperature (T.J ...................•........ -65°C to +150°C
Operating Temperature Range
SSM-2139 (P, S) ........................................... -40°C to +85°C
The low offset voltage Vos of 500!J.V MAX (20!J.V typical) and
offset voltage drift of only 2.5!J.VrC MAX assures system accu·
racy and eliminates the need for external V 0 s adjustments.
The SSM·2139's outstanding open·loop gain of 1,700,000 and
its exceptional gain linearity eliminate incorrectable system
nonlinearities and provides superior performance in high
closed-loop gain applications, such as preamplifiers.
PACKAGE TYPE
alA (Note 1)
B-Pin Plastic DIP (P)
16-Pin SOL (S)
NOTES:
The SSM-2139 is offered in an 8-pin plastic DIP and Small Outline (SO) package and its performance and characteristics are
guaranteed over the extended industrial temperature range of
-40°C to +85°C.
96
92
ale
UNITS
37
27
·C/W
·C/w
1. alA is specified for worst case mounting conditions, i.e., a jA is specified for
device in socket for P-DIP package; alA is specified for device soldered to
printed circuit board for SOL package.
2. The SSM-2139 inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise performance. If differential
voltage exceeds ±1.0V, the input current should be limited to :t25mA.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .................................................................. ± 18V
Differential Input Voltage (Note 2) .................................. ±1.0V
Differential Input Current (Note 2) ................................ ±25mA
ELECTRICAL CHARACTERISTICS atVs =±15V, TA
PARAMETER
SYMBOL
CONDtTtONS
Input Noise Voltage
8 np _p
O.lHzto 10Hz
(Note 1)
Input Noise
Voltage Density
en
'Input Noise
Current Density
in
=25°C, unless otherwise noted.
MtN
SSM·2139
TYP
MAX
UNtTS
80
200
nVp •p
10 = 10Hz
fo = 100Hz
fo = 1kHz
(Note 2)
3.6
3.2
3.2
6.5
5.5
5.0
10 = 10Hz
fO = 100Hz
fa = 1kHz
1.1
0.7
0.6
pN/Hz
Slew Rate
SR
Gain Bandwidth Product
GBW
fo = 100kHz
Full Power Bandwidth
BWp
Vo = 27Vp • p
RL = 2kO (Note 3)
Supply Current
(All A'l'plifiers)
ISY
No Load
Total Harmonic Distortion
THO
RL = 2kO
Vo =3VRMS ' fo = 1kHz
Input Offset Voltage
Vos
Input Offset Current
los
VCM=OV
Input Bias Current
18
VCM=OV
Large-Signal
Voltage Gain
Avo
Vo = ",10V
RL = 10kO
RL = 2kO
RL = 6000
Output Voltage Swing
Vo
Vo+
Vo-
Common-Mode Rejection
CMR
7
nV//Hz
11
VI""
30
MHz
130
kHz
4
6.5
0.002
20
5
rnA
%
500
",V
50
nA
80
nA
1000
500
1700
900
900
V/mV
RL ~2kO
RL ~6000
RL ",6000
",12
",13.5
+13
-10
V
VCM = ",12V
94
115
dB
96
10189, Rev. A1
SSM-2139 DUAL LOW NOISE, HIGH-SPEED AUDIO OPERATIONAL AMPLIFIER
ELECTRICAL CHARACTERISTICS atVs = ±15V, TA = 25·e, unless otherwise noted. Continued
SSM-2139
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Power Supply
Rejection Ratio
PSRR
V S =±4.5Vto.18V
105
120
dB
Input Voltage Range
IVR
(Note 4)
±12.0
±12.5
V
Isc
Sink
Source
20
40
rnA
20
Gn
0.4
Mn
3
pF
175
dB
Output Short· Circuit
Current
Input Resistance
Common-Mode
R'NCM
Input Resistance
Differential·Mode
R'N
Input Capacitance
C 'N
Channel Separation
CS
VA =20Vp. p
fa = 10Hz (Note 1)
125
MAX
UNITS
NOTES:
1. Guaranteed but not 100% tested.
2. Sample tested.
3. BWp = SR/2" V pEAK '
4. Guaranteed by CMR test.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, --
"w
3DOD
C
"
2DDD
lDOD
o
tOOk
1\
V
o
L
:1:5
V
:1:10
0
V
L
:1:15
5!Ii
.
. .0
10M 100M
10k
.2.
;;;
W
12
...
11
~
"
o
~
'"~
10
.,.,..
10k
-so
'SWING
10
took
1M
100
lOll
10k
1k
LOAD RESISTANCE (0)
TOTAL HARMONIC DISTORTION
vs FREQUENCY
TOTAL HARMONIC DISTORTION
vs OUTPUT VOLTAGE
D.'
AV. +1'00
-
l
i!i
"
-SR
. /~
-25
IY
/r~EGATIVE
FREQUENCY (Hz)
i'"
0
25
50
D.oS
75
rC)
100
125
150
D.DDI ............'-I.JCUiJ..................'"""_.................--J
10
100
1k
FREQUENCY (Hz)
99
~~'=
-+-
-
v..
TA • +25·C
-
+
Vo
VS ·*15Y
0
0.01
TEMPERATURE
0.1
~
+SR
""'"
.'"
0.01
~
0.005
11
7
-75
SWING
S
1k
0.1
",..
lDOII
I
V~ •• ,~
11
10M
POS:';:VE
+2S'C
Vs a:t15V
13
!:j
~
12
SLEW RATE
vs TEMPERATURE
12
'A-
"
13
~
1M
MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE
I.
TA_+2S·C
Vs. :t15Y
THD .. t%
,.
SUPPLY VOLTAGE (VOLTS)
,.
tOOk
FREQUENCY (Hz)
"::l
6
~
::l...
220
I'
-"1M
20
0
!;
~
i!;
"'
"
20
28
4DOD
z
10k
~
9u
MAXIMUM OUTPUT SWING
vs FREQUENCY
24
~
40
..."
FREQUENCV (Hz)
OPEN·LOOP GAIN
vs SUPPLY VOLTAGE
_0
=:l:15V
"-
~
w
!:l
0
>
Vs
60
20
o
TA~+~~·~
T A _+2S·C
Ys :I:t15V
2kC"-
--.!L=~%
':'
-
_i+3
AY
I
0.001
1
_
•
7
OUTPUT VOLTAGE
cY...s)
10/89, Rev. A1
SSM-2139 DUAL LOW NOISE, HIGH-SPEED AUDIO OPERATIONAL AMPLIFIER
R.
-OUT
500
R,
R,
R"
2kO
1k0
10kO
R,
2kO
r
R"
10kO
R"
Ike
R,
R"
2ke
.OUT
500
HlkQ
FIGURE 1: High-Speed Differential Line Driver
APPLICATIONS INFORMATION
HIGH-SPEED DIFFERENTIAL LINE DRIVER
The circuit of Figure 1 is a unique approach to a line driver circuit
widely used in professional audio applications. With ±18V supplies, the line driver can deliver a differential signal of 30Vp-p
into a 1.5kQ load. The output of the differential line driver looks
exactly like a transformer. Either output can be shorted to
ground without changing the circuit gain of 5, so the amplifier
can easily be set for inverting, noninverting, or differential operation. The line driver can drive unbalanced loads, like a true
transformer.
R,
2000
R,
2000
LOW NOISE AMPLIFIER
Asimple method of reducing amplifier noise is by paralleling amplifiers as shown in Figure 2. Amplifier noise, depicted in Figure
3, is around 2nV/-I"HZ@ 1kHz (R.T.I.). Gain for each paralleled
amplifier and the entire circuit is 1000. The 200Q resistors limit
circulating currents and provide an effective output resistance
of50Q.
VOUT =
1000V1N
",
2000
R"
200e
SOkO
FIGURE 2: Low Noise Amplifier
FIGURE 3: Noise Density of Low Noise Amplifier, G = 1000
100
10/89, Rev. A1
SSM·2139 DUAL LOW NOISE, HIGH·SPEED AUDIO OPERATIONAL AMPLIFIER
VOLTAGE AND CURRENT NOISE
The SSM·2139 is a low noise, high-speed dual op amp, exhibiting a typical voltage noise of only 3.2nVl../Hz @ 1kHz. The exceptionally low noise characteristics of the SSM-2139 is in part
achieved by operating the input transistors at high col/ector currents since the voltage noise is inversely proportional to the
square root of the col/ector current. Current noise, however, is
directly proportional to the square root of the col/ector current.
As a result, the outstanding voltage noise performance of the
SSM-2139 is gained at the expense of current noise performance, which is normal for low noise amplifiers.
100
~
~
J-SSM'r aO
......
To obtain the best noise performance in a circuit, it is vital to
understand the relationship between voltage noise (en)' current
noise (in)' and resistor noise (et).
/
..
RESISTOR
NOISE ft~LY
,
TOTAL NOISE AND SOURCE RESISTANCE
The total noise of an op amp can be calculated by:
En
.XI
1k
10k
'OOk
Hs - sounCE RESISTANCE (D)
FIGURE 4: Total Noise vs. Source Resistance (Including
Resistor Noise) at 1kHz
=V(en)2 + (in RS)2 =(el
where:
En
=total input referred noise
en = op amp voltage noise
'00
in = op amp current noise
=source resistance thermal noise
Rs =source resistance
et
1/
V
The total noise is referred to the input and at the output would be
amplified by the circuit gain.
J- SSM:l!.Vr
Figure 4 shows the relationship between total noise at 1kHz and
source resistance. For Rs < 1kg, the total noise is dominated by
the voltage noise of the SSM-2139. As Rs rises above 1kg, total
noise increases and is dominated by resistor noise rather than
by voltage or current noise of the SSM-2139. When Rs exceeds
20kg, current noise of the SSM-2139 becomes the major contributor to total noise.
V
'00
...Ii
RESISTOR
NOISE ft~LY
1k
10k
,OOk
Rs - SOURCE RESISTANCE (0)
Figure 5 also shows the relationship between total noise and
source resistance, but at 10Hz. Total noise increases more
quickly than shown in Figure 4 because current noise is inversely proportional to the square root offrequency. In Figure 5,
current noise of the SSM-2139 dominates the total noise when
Rs >5kg.
FIGURE 5: Total Noise vs. Source Resistance (Including
Resistor Noise) at 10Hz
From Figures 4 and 5, it can be seen that to reduce total noise,
source resistance must be kept to a minimum.
101
10/89, Rev. A1
SSM·2139 DUAL LOW NOISE, HIGH·SPEED AUDIO OPERATIONAL AMPLIFIER
Figu're 6 shows peak-Io·peak noise versus source resistance
over Ihe 0.1 Hz 1010Hz range. Once again, at low values of Rs '
the voltage noise of the SSM-2139 is the major contributor to
peak-to-peak noise with current noise the major contributor as
Rs increases.
TABLE l'
Strain Gauge
<5000
Typically used In low-frequency
applications.
For reference, typical source resistances of some signal
sources are listed in Table 1.
Magnetic
Tapehead,
Microphone
<15000
Low Ie very Important to reduce
seH-magnetizatlon problems when
direct coupling Is used. SSM-213910
can be neglected.
Magnetic
Phonograph
Cartridge
<1500Q
Similar need for low Ie In direct
coupled applications. SSM-2139 will not
Introduce any seH-magnetization
problem.
Unear Variable
Differential
Transformer
<15000
Used in rugged servo-feedback
applications. Bandwidth of interest Is
400Hz to 5kHz.
DEVICE
For further information regarding noise calculations, see "Mini·
mization of Noise in Op Amp ,Applications," Application Note
AN-15.
'
'0"
V
V
1. The device has to be warmed-up for at least five minutes. As
shown in the warm·up drift curve, the offset voltage typically
changes 211V due to increasing chip temperature after
power·up. In the 10-second measurement interval, these
temperature-induced effects can exceed tens-of-nanovolts.
RESISTOR
,.
,.
N!lIS~ ~~LY
'00,
'.k
COMMENTS
NOISE MEASUREMENTS PEAK·TO·PEAK VOLTAGE NOISE
The circuit of Figure 7 is a test setup for measuring peak-to-peak
voltage noise. To measure Ihe 200nV peak·to·peak noise specification ofthe SSM·2139 in the 0.1 Hz to 10Hz range, the follow·
ing precautions must be observed:
,/
SSM·2139
SOURCE
IMPEDANCE
1OOk·
AS - SOURCE RESISTANCE {OJ
2. For similar reasons, the device has to be well·shielded from
air currents. Shielding also minimizes thermocouple effects.
FIGURE 6: Peak·to-Peak Noise (0. 1Hz to 10Hz) vs. Source
Resistance (Includes Resistor Noise)
c.
so
9090
> .........,IW'-1>---O·.UT
GAIN .......
Vs. ,.,15V
FIGURE 7: Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10Hz)
102
10/89, Rev. A1
SSM-2139 DUAL LOW NOISE, HIGH-SPEED AUDIO OPERATIONAL AMPLIFIER
3. Sudden motion in the vicinity of the device can also "feedthrough" to increase the observed noise.
100
4. The test time,6 measure 0.1 Hz to 10Hz noise should not exceed 10 seconds. As shown in the noise-tester frequencyresponse curve of Figure 8, the 0.1 Hz corner is defined by
only one pole. The test time of 10 seconds acts as a additional pole to eliminate noise contribution from the frequency
band below 0.1 Hz.
aD
iD
!!.
.
z
a
"
5. A nOise-voltage-density test is recommended when measuring noise on a large number of units. A 10Hz noise-voltagedensity measurement will correlate well with a 0.1 Hz-to10Hz peak-to-peak noise reading, since both results are
determined by the white noise and the location of the 1/f corner frequency.
4D
2D
D
0.01
D.l
10
10D
FREQUENCY (Hz)
6. Power should be supplied to the test circuit by well bypassed
low-noise supplies, e.g. batteries. These will minimze output
noise introduced via the amplifier supply pins.
FIGURE 8: O.1Hz to 10Hz Peak-to-Peak Voltage Noise Test
Circuit Frequency Response
CHANNEL SEPARATION TEST CIRCUIT
5kg
5kg
50O!>
>"""--0 v,
CHANNEL SEPARATION = 20 I09(
V2~:WO)
103
10/89, Rev_ A1
SSM-2210
AUDIO DUAL MATCHED
NPNlRANSISTOR
Precision Monolithics Inc.
The SSM-221 0 is also an ideal choice for accurate and reliable
current biasing and mirroring circuits. Furthermore, since a current mirror's accuracy degrades exponentially with mismatches
of VBE'S between transistor pairs, the low Vos of the SSM-221 0
will preclude offset trimming in most circuit applications.
FEATURES
• Very Low Voltage Noise ............. @100Hz, 1nV/#iZ MAX
• Excellent Current Gain Match ........................... 0.5% TYP
• Tight VeE Match (Vos) ...................................... 200~V MAX
• Outstanding Offset Voltage Drift .............. 0.03~V/oC TYP
• High Gain-Bandwidth Product ..................... 200MHz TYP
• Low Cost
• Direct Replacement For LM394BN/CN
The SSM-221 0 is offered in an 8-pin epoxy DIP and S-pin SO, its
performance and characteristics are guaranteed over the extended industrial temperature range of -40°C to +85°C.
ORDERING INFORMATION
PACKAGE
PLASTIC
8·PIN
SSM2210P
SO
8·PIN
SSM2210St
PIN CONNECTIONS
OPERATING
TEMPERATURE
RANGE
S-PIN
PLASTIC DIP
(P·Sufflx)
XIND'
• XIND =-40'C to +85'C
t For availability on SO package, contact your local sales office.
8-PINSO
(S.Sufflx)
GENERAL DESCRIPTION
The SSM-221 0 is a dual NPN matched transistor pair specificially designed to meet the requirements of ultra·low noise audio systems.
ABSOLUTE MAXIMUM RATINGS
Collector Current (Ie) ....................................................... 20mA
Emitter Current (IE) ......................................................... 20m A
Collector-Collector Voltage (BVee) .................................... 40V
Collector-Base Voltage (BVCBO) ....................................... 40V
Collector-Emitter Voltage (BVCEO) .................................... 40V
Emitter-Emitter Voltage (BVEE ) ......................................... 40V
Operating Temperature Range ....................... -40°C to +85°C
Storage Temperature .................................... -65°C to + 125°C
Junction Temperature ................................... -65°C to + 150°C
Lead Temperature (Soldering, 60 sec) ........................ +300°C
With its extremely low input base spreading resistance (rbb' is
typically 28Q), and high current gain (hFE typically exceeds 600
@ Ic = 1mAl, systems implementing the SSM-221 0 can achieve
outstanding signal-to-noise ratios. This will result in superior
performance compared to systems incorporating commercially
available monolithic amplifiers.
The equivalent input voltage noise of the SSM-221 0 is typically
only 0.8nV/..JRZ over the entire audio bandwidth of 20Hz to
20KHz.
Excellent matching of the current gain (t.h FE ) to about 0.5% and
low Vos of less than 50~V (typical) make it ideal for symmetrically balanced designs which reduce high order amplifier harmonic distortion.
PACKAGE TYPE
Stability of the matching parameters is guaranteed by protection diodes across the base-emitter junction. These diodes prevent degradation of Beta and matching characteristics due to
reverse biasing of the base-emitter junction.
a JA (NOTE 1)
UNITS
8·Pin Plastic DIP (P)
110
50
'CIW
B·Pin SO (S)
160
44
'CIW
NOTE:
1. a·A is specified for worst case mounting conditions, i.e., a·A is specified for
d~vice in socket for P·DIP packages; ajA is specified for d~vice soldered to
printed circuit board for SO packages.
104
7/89, Rev. 81
SSM-2210 AUDIO DUAL MATCHED NPN TRANSISTOR
ELECTRICAL CHARACTERISTICS atVcB = 15V, Ic = lOI-lA, TA = 25°C, unless otherwise noted.
SSM·2210
PARAMETER
SYMBOL
CurrenlGain
hFE
CONDITIONS
MIN
TVP
Ic = 1mA (Nole 1)
300
200
S05
550
Ic = 10"A
MAX
UNITS
%
AhFE
10"AslcslmA (Note2)
0.5
5
en
1.S
0.9
0.85
0.85
2
Noise Voltage Density
Ic = 1rnA, VCB =0 (Note3)
10=10Hz
'0= 100Hz
10= 1kHz
10= 10kHz
Offset Voltage
Vas
VCB=O
Ic=lmA
10
200
~V
Offset Voltage
Change vs VCB
AVoS/AVCB
OsVCBsVMAX (Note4)
1"Aslcs1mA (NoteS)
10
50
~V
Offset Voltage Change
vs Collector Current
AVos/Alc
VCB=OV
1"Aslcs1mA (NoteS)
5
70
~V
Current Gain Match
nVJVFrz
V
Breakdown Voltage
BVCEO
Gain·Bandwidth Product
'-r
Ic =10mA,VCE =10V
Collector-Base
Leakage Current
ICBO
VCB=VMAX
25
500
pA
Coliector·Coliector
Leakage Current
Icc
VCC=VMAX (NotesS,7)
35
500
pA
Collector-Emitter
Leakage Current
ICES
VCE=VMAX (NotesS,7)
VBe=O
35
500
pA
Input Bias Current
IB
Ic = 10"A
50
nA
Input Offset Current
los
Ic=10"A
S.2
nA
Collector Saturation
Voltage
VCe(SAT)
Ic=lmA
IB = loo"A
0.2
V
40
0.05
Output Capacitance
COB
VCB =15V,I E =0
23
Bulk Resistance
rBe
1O"A s Ic slOmA (Note S)
0.3
Collector-Collector
Capacitance
CCC
VCc=O
35
NOTES:
1. Current gain is guarantBed with Coliector·Base VoltagB (V CB) swept from 0 to
VMAX at the indicated collector currents.
2. Current Gain Match (Ah Fe) is defined as:
AhFE=
MHz
200
pF
1.S
pF
5. Measured at Ic = 1O~A and guaranteed by design over the specified range ofl c '
S. Guaranteed by design.
7. Icc and Ices are verified by measurement of ICBO'
100(AI e) (h FEmil)
Ie
3 ••·Noise Voltage Density is guaranteed, but riot 100% tested.
4. This is the maximum change in Vas as VCBls sweptfrom OV to 40V.
105
7/89, Rev. 81
SSM·2210 AUDIO DUAL MATCHED NPN TRANSISTOR
ELECTRICAL CHARACTERISTICS at VCB =15V, -40·C:s TA :s +85·C, unless otherwise noted.
SSM·2210
PARAMETER
SYMBOL
Current Gain
hFE
CONDITIONS
MtN
Ie = lmA (Note 1)
300
Ie = 10j1A
200
TYP
MAX
UNITS
220
"V
0.3
"vrc
Vos
Vce=O
le=lmA
TCVos
10j1A"lc " lmA. O"Vee"VMAX (Note 2)
Vos Trimmed to Zero (Note 3)
Input Bias Current
Ie
Ie = 10j1A
50
nA
Input Offset Current
los
Ie = 10j1A
13
nA
TClos
Ie = 10j1A (Note 4)
ISO
pArC
tceo
Vce=VMAX
3
nA
ICES
VeE = VMAX ' VeE = 0
4
nA
Icc
Vee=VMAx
4
nA
Offset Voltage
Average Offset
Voltage Drift
Input Offset
Current Drift
0.08
0.03
40
Coliector·Base
Leakage Current
Coliector·EmiHer
Leakage Current
Coliector·Coliector
Leakage Current
NOTES:
1. Current gain is guaranteed with Coliector·Base Voltage
V MAX at the indicated collector curr~t.
2. Guaranteed by Vos test (TCVos·
rvce) swept from 0 to
~s .VeE),T= 298K for TA =2S'C.
3. The initial zero offset voltage is established by adjusting the ratio of Ic 1 to IC2 at
T A = 2S'c' This ratio must be held to 0.003% over the entire temperature range.
Measurements are taken at the temperature extremes and 25°C.
4. Guaranteed by design.
TYPICAL PERFORMANCE CHARACTERISTICS
LOW FREQUENCY NOISE
(0.1 Hz TO 10 Hz)
NOISE FIGURE vs
COLLECTOR CURRENT
•• 4
15
"
13
,
\
11
.
ii 10
Vea:ll: ov
TA _25'"<:
Fa .. 1kHz
~RS=1kQ
12
T =+25·C
!
1
•.3
I
~
i
No
1 _AS. 10k
•
i
i
I
I
i
"-
0.001
-0.01
I
......
-0.1
0.1
COLLECTOR CURRENT (mA)
106
I .•
10-8
1
I
II
t.1,tDIV
i
!
I
i
7
ill •
~ 5
!
A
I
;- 9
~
EMITTER·BASE
LOG CONFORMITY
I
,
I
I
10- 7
10- 8
!
/
./
i
I
10- 5
10-·
COLLECTOR CURRENT (A)
7/89, Rev. 81
SSM-2210 AUDIO DUAL MATCHED NPN TRANSISTOR
TYPICAL PERFORMANCE CHARACTERISTICS
NOISE VOLTAGE DENSITY
NOISE VOLTAGE
DENSITY vs FREQUENCY
NOISE CURRENT
DENSITY vs FREQUENCY
vs COLLECTOR CURRENT
1000
1.5
100
. +:;.C:
~~:
~
!
100
~
ille
~
I
\.
~
IC·'pA=
r-..
10
IC·'~
w
"~
g
~
~
w
>
w
Ie" 1mA
I
10
100
1k
10k
0.5
tOOk
~
~
60
"isz
...
1111
'00
"'
40
20
700
~
/
I
!
II
III
~
""
III
I II
:!
:;!
VCB=OV
.00
=11
111
II~S" fOOkQ
t'-.
0:
"
I
III
o
0.001
600
Ie" tOpA=--
"w
rlz
~
0.1
12
'C".~~
0.1
10
~
II
C!
~
~
400
§
I
u
·55-C
IIIII
III
0.01
500
/
400
..J
Voc"'j.lA
(EXCLUDES 'CBO)
,/
300
200
100
a
-7'
0.1
COLLECTOR CURRENT (mAl
GAIN BANDWIDTH
vs COLLECTOR CURRENT
BASE-EMITTER-ONVOLTAGE vs COLLECTOR
CURRENT
0.7
V
L L
L
.00
I
V
J
tOOk
IC=1mA~
LV'
.00
700
300
10k
CURRENT GAIN
+25-C
+125·C
1k
vs TEMPERATURE
/
COLLECTOR CURRENT (mAl
1000
100
FREQUENCY (Hz)
900
!I
100
0.001
0.1
Ie .. 1mA
U
500
200
Rs·1kD
0.01
"'-
~
~0:
III
~
U
RS·tOkD
"'i-
'C· 1OmA -
~
CURRENT GAIN vs
COLLECTOR CURRENT
'"''
to 10H,
w
10
COLLECTOR CURRENT (mAl
~-
80
~
i
./
V'
3
TOTAL NOISE vs
COLLECTOR CURRENT
''''
k
/'"
V
0.01
o
FREQUENCY (Hz)
100
/v
L
rlz
0.1
0.1
..... r--
1.0
"e~
r--...
w
rlz
TA" +25·C
VeE= 5V
-25
25
7.
12'
175
TEMPERATURE rC)
SMALL-SIGNAL INPUT
RESISTANCE vs COLLECTOR
CURRENT
;.,~!~
TA
VCE=5Y
/
a.•
"
1
o. 1
0.001
::lz
~
~
5
"
Ii
!.
\.-'"
ill0:
.
\.-'"
!;
II
~
a. 4
/
0.01
0.1
1
10
COLLECTOR CURRENT (mAl
a.3
100
0.001
;;
0.01
0.1
COLLECTOR CURRENT (mA)
107
10
0.01
0.01
to
0.1
100
COLLECTOR CURRENT (mAl
7/89, Rev. B1
SSM-2210 AUDIO DUAL MATCHED NPN TRANSISTOR
TYPICAL PERFORMANCE CHARACTERISTICS
SMALL-SIGNAL OUTPUT
CONDUCTANCE vs
COLLECTOR CURRENT
Continued
COLLECTOR-TO-BASE
LEAKAGEvsTEMPERATURE
SATURATION VOLTAGE
vs COLLECTOR CURRENT
10
1000
100
~
E
100
in
!:;
""
"~
"
W
:;-
0
""
Z
10
!:;
0
Z
0
>
0-
"
Q
~
~
Z
~
~
~
0
L
I
~
~
Q
0.1
0.1
2
0.01
0.1
1
10
..
/'
~
"I
,
Iii
.Y
~
0.1
0.01 L-",-,-J..WJJL....J....I..J..U.IlL...J..u.J.""---L...L.l.JJ..lJIJ
0.001
0.01
0.1
1
10
100
10
s
1.0
w
0.01
50
25
COLLECTOR-BASE
CAPACITANCE vs
REVERSE BIAS VOLTAGE
COLLECTOR-TO·COLLECTOR
CAPACITANCE vs COLLECTORTO-SUBSTRATE VOLTAGE
40
c
100
100
TAl" .2S-C
-+2S·C
./
40
~
30
Z
!!------I--_
OUTPUT
r- -
,'N 0-....,.-1--1[,
"l-........L..-O_'N
~ 100nF
I SSM".,.
'71eD
I SSM·221.
Q,
2N2905
____ I SSM·••,.
"..
1800
"ED
LED
55
L . . - -.....- - -......-o_15V
FIGURE 7: Complete Amplifier Schematic
112
7/89, Rev. 81
SSM·2210 AUDIO DUAL MATCHED NPN TRANSISTOR
AMPLIFIER PERFORMANCE
The measured performance of the op amp is summarized in
Table 2. Figure 8 shows the broadband noise spectrum which is
flat at about 500pv/VRZ. Figure 9 shows the low-frequency
spectrum which iIIustra,es the low 1/f noise corner at 1.5Hz. The
low-frequency characteristic in the time domain from 0.1 Hz to
10Hz is shown in Figure 10; peak-to-peak amplitude is less than
40nV.
TABLE 2: Measured Performance of the Op Amp
Input Noise
Voltage Density at 1kHz
40nV~.~
Input Noise Current at 1kHz
Gain-Bandwidth
1.5pNv'RZ
=10
=100
G =1000
3MHz
600kHz
G
G
150kHz
Slew Rate
2V/lJ.s
Open-Loop Gain
3 x 107
Common-Mode Rejection
130dB
Input Bias Current
-
3iJ.A
Supply Current
10mA
FIGURE 10: Oscilloscope Display
0.11J.V/oC Max
Nulled TCVos
T.H.D. at 1 kHz
FIGURE 9: Spectrum Analyzer Display - Low Frequency
500pV/v'FlZ
Input Noise
Voltage from 0.1 Hz to 10Hz
G
=1000
0.002%
CONCLUSION
Using SSM-2210 matched transistor pairs operating at a high
current level, it is possible to construct a high-performance, lownoise operational amplifier. The circuit uses a minimum of components and achieves performance levels exceeding monolithic
amplifiers.
FIGURE 8: Spectrum Analyzer Display - Broadband
113
7/89, Rev. 81
SSM-2210 AUDIO DUAL MATCHED NPN TRANSISTOR
+15V
l00kll
(0 10
".
1~~ o--"'.IV."Ir--_--'i
~-_-OVo
"3
7.SkO
",
V~:~ o----'II.VI.",.---i>--9
",
50Da
=
R 2 TEL LABS QB1E (+O.35%rC)
-15V
FIGU R E'11: Fast Logarithmic Amplifier
FAST LOGARITHMIC AMPLIFIER
The circuit of Figure 11 is a modification of a standard logarithmic amplifier configuration. Running the SSM-2210 at 2.5mA
per side (full-scale) allows a fast response with wide dynamic
range. The circuit has a 7 decade current range, a 5 decade voltage range, and is capable of 2.51-1s settling time to 1% with a 1to
10V step.
The output follows the equation:
Vo
=&..±..& kT
R2
q
In VREF
VIN
To compensate for the temperature dependence of the kT/q
term, a resistor with a positive O.35%/oC temperature coefficient
is chosen for R2 •
The output is inverted with respect to the input, and is nominally
- 1V/decade using the component values indicated.
114
7/89, Rev. 81
SSM-2220
AUDIO DUAL MATCHED
PNP TRANSISTOR
Precision Monolithics Inc.
The SSM-2220 also offers excellent matching of the current
gain (C,h FE ) to about 0.5% which will help to reduce the high
order amplifier harmonic distortion. In addition, to insure the
long-term stability of the matching parameters, internal protection diodes across the base-emitter junction were used to clamp
any reverse base-emitter junction potential. This prevents a
base-emitter breakdown condition which can result in degradation of gain and matching performance due to excessive breakdown current.
FEATURES
Very Low Voltage Noise ............. @ 10aHz, 1nV/v'HZ Max
High Gain Bandwidth ..................................... 190MHz Typ
Excellent Gain ................................... @ Ic = 1mA, 165 Typ
Tight Gain Matching .............................................. 3% Max
Outstanding Logarithmic Conformance .• rBE = 0.3[2 Typ
Low Offset Voltage ........................................... 200~V Max
Low Cost
Anotherfeature of the SSM-2220 is its very low bulk resistance
of 0.3[2 typically which assures accurate logarithmic conformance.
APPLICATIONS
• Microphone Preamplifiers
• Tape-Head Preamplifiers
• Current Sources and Mirrors
• Low Noise Precision Instrumentation
• Voltage Controlled Amplifiers/Multipliers
The SSM-2220 is offered in 8-pin plastic, dual-in-line, and SO
and its performance and characteristics are guaranteed over
the extended industrial temperature range of -40°C to +85°C.
ORDERING INFORMATION
PACKAGE
PIN CONNECTIONS
PLASTIC
a-PIN
SO
a_PINt
OPERATING
TEMPERATURE
RANGE
SSM2220P
SSM2220S
XIND'
8-PIN
PLASllCDIP
(P-Suffix)
, XIND ~ -40'C to +85'C
t For availability of SO package, contact your local sales office.
8-PIN
SO
(S-Suffix)
GENERAL DESCRIPTION
The SSM-2220 is a dual low noise matched PNP transistor
which has been optimized for use in audio applications.
The ultra-low input voltage noise of the SSM-2220 is typically
only 0.7nVA,IHZ over the entire audio bandwidth of 20Hz to
20kHz. The low noise, high bandwidth (190MHz), and Offset
Voltage of (200~ V Max) make the SSM-2220 an ideal choice for
demanding low noise preamplifier applications.
115
2/90, Rev. A1
SSM-2220 AUDIO DUAL MATCHED PNP TRANSISTOR
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ..•.••.•••......••••.••••.••..••••.• -65°Cto +150°C
Collector-Base Voltage (BVCBO ) ........................................ 36V
Collector-Emitter Voltage (BVCEO ) •.•....•.••.•.••••.••..•••..•.•••.... 36V
Junction Temperature ...•••••••......•.•••••••••...••••. -65°C to + 150°C
Lead Temperature (Soldering, 60 sec) ...••••..•••••.••••••••• +300°C
Collector-Collector Voltage (BVcc ) •...•••...•.••.....•••••..........• 36V
Emitter-Emitter Voltage (BV EE) •••••••.•.••.....•••.•.....••.•..•••...••• 36V
PACKAGE TYPE
BIC
UNITS
Collector Current (lc) •••.•.•.•.•••...••.•......•••.•...•••••••.••.••..•.••. 20mA
8·Pin Plastic DIP (P)
103
43
·CIW
Emitter Current (IE) .••••.•.....•.•....••••......•••••.••••.•.••...•••.•..... 20mA
8·PinSO(S)
158
43
·CIW
BIA (Note 11
NOTE:
1. B'A Is specilied for worst case mounting conditions, i.e., B'A Is specified for
dbvice in socket for P·DIP package; BiA is specified for d!.vice soldered to
printed circuit board for SO packages.
Operating Temperature Range
SSM-2220P .•••••••.•...••••••..••..•..•••••••.....•••....••• -40°C to +85°C
SSM-2220S .•••••••......•••.•....•••...•.••••.....•.•....••• -40°C to +85°C
Operating Junction Temperature ....•..•••....•.•• -55°C to +150°C
ELECTRICAL CHARACTERISTICS at TA = +25°C, unless otherwise noted.
SSM-2220
PARAMETER
SYMBOL
CONDITIONS
Current Gain
(Note 1)
hFE
Vce =OV,--36V
Ic=1mA
le= 100jJA
Ie = 10jJA
Current Gain Matching
(Note 2)
6hFE
Ie = 100jJA, Vee =OV
Noise Voltage Density
(Note 3)
MIN
TYP
80
70
80
165
lSO
120
MAX
UNITS
0.5
6
%
0.8
0.7
0.7
0.7
2
eN
Ic=1mA, Vee=OV
fo= 10Hz
fo= 100Hz
fa = 1kHz
fa = 10kHz
Offset Voltage
(Note 4)
Vas
Vee = OV,le = l00jJA
40
200
j1V
Offset Voltage Change
vs. Collector Voltage
6Vos/6Vee
Ie = 100jJA
VCe1 =OV
VCB2 =--36V
11
200
j1V
Offset Voltage Change
vs. Collector Current
6Vo r/61 e
Vee=OV
lel = 1OjJA, le2 = 1mA
12
75
j1V
Offset Current
los
Ie = 100jJA, Vee = OV
6
45
nA
Collector-Base
Leakage Current
leBO
Vee =--36V = VMAX
SO
400
pA
Bulk Resistance
reE
Vee=OV'
10jJA"le ,,1mA
0.3
0.75
n
Collector Saturation
Voltage
VeE(SAT)
le= lmA,le= 100jJA
0.026
0.1
V
NOTES:
1. Current gain is measured at collector-base voltages (Vee) swept from 0 to
VMAX at indicated collector current. Typicals are measured at VeB = OV.
2. Current gain matching (6h FE) is defined as:
6hFE
nV/v'Hz
4 .. Offset voltage is defined as:
Vas = VeE' - VBE2'
where Vas is the differential voltage for
IC2 =IC2:VOS =VSEl - VSE2 =!SI In (~
q
IC2
100(6IS) hFE (MIN)
IC
3. Sample tested. Noise tested and specified as equivalent input voltage for
each transistor.
116
2190, Rev. A1
SSM-2220 AUDIO DUAL MATCHED PNP TRANSISTOR
ELECTRICAL CHARACTERISTICS at -40·C :s TA :s +85·C, unless otherwise noted.
SSM-2220
PARAMETER
SYMBOL
CONDITIONS
MIN
TVP
60
50
40
120
105
90
VCB =OV.-{!6V
Ic=lmA
Ic= 100fJA
Ic = 10fJA
Current Gain
hFE
Offset Voltage
Vos
Ic = 100fJA. VCB =OV
30
Offset Voltage Drift
(Note 1)
0.3
TCVos
Ie = 100fJA. VCB =OV
Offset Currant
los
Ie = 100fJA. VCB =OV
Breakdown Voltage
BVCEO
10
MAX
UNITS
265
"V
200
nA
36
V
NOTE:
1. Guaranteed byVos test (TCVos = VosfTforVos« VB E)
where T = 29S"K for TA = 25"C.
TYPICAL PERFORMANCE CHARACTERISTICS
NOISE FIGURE vs
COLLECTOR CURRENT
LOW FREQUENCY NOISE
14
EMITTER-BASE
LOG CONFORMITY
O.S
v~~"", 5V
12
0.3
+4DnV
10
ov
-40nV
~
j'
Rs .1kg
i".
Vc.=SV
Ic=1mA
0.001
TOTAL NOISE vs
COLLECTOR CURRENT
250
T. I.
i.Jc
~
ycs- OV
200
~
;!
;0
.5.
ll!0
...z
~
""1kHz
100
f!
so
o
,,~ _1'~O~g
~
1
5i5
.~
I
r
10
"w
lm
AS
100
COLLECTOR CURRENT elLA)
1000
•
.
...
0
1
o
-0.1
-0.2
-0.3
-oA
0.01
-0.5 ,0 -1
0.1
10-7
10-6
10-5
10~
COLLECTOR CURRENT (mA)
COLLECTOR CURRENT (A)
NOISE VOLTAGE DENSITY
vs COLLECTOR CURRENT
NOISE VOLTAGE DENSITY
vs FREQUENCY
1000
TA _2S·C
Vca- OY
L
FTA.ZS-C
Vca
117
I
I
1
I
.5.
10
I"\" "\..
1
~
Ie .10pA
Ii
Ie .100pA
1"""-
w
;
12
COLLECTOR CURRENT (mAl
I
100
~
-~ V100~
o
~.,
i
/
c::::::::
10-3
aOV
10HL
iz
I
",.
r-...A s ·1'I~kQ
3
2
0.1
1
4
g
II:
I
TA = +25·C
o
0.2
i5
r\
VERTICAL =40nVJDIV
HORIZONTAL =1S1OIV
!
Ii
, . A. _l00kg
1 150
fA. +2S-C
Vee" OY
0.4
h1kHz
Ie .1mA
I
r--1
1
0.1
0.1
10
100
111
10k
100k
FREQUENCY (Hz)
2190, Rev _A1
SSM-2220 AUDIO DUAL MATCHED PNP TRANSISTOR
TYPICAL PERFORMANCE CHARACTERISTICS Continued
CURRENT GAIN
vs TEMPERATURE
CURRENT GAIN vs
COLLECTOR CURRENT
7DO
300
Ic'.. m~
Vca=OV
---
+125"C
j;
.......
Z
;;
+25°,..
,....
I.
I
"c.-~
500
400
V
,."..
~
~
ili
3DD
u
2DD
~
~
~
-55·C
50
lDD
o
0'0
100
V
"."
~
~
iii
a"
--
~
VCB=OV
rol- I -I -
L
10
~
/
~
"oJ:
z
I
-15
5254565
8S
105
,
0.1
0.001
125
10
0.70
TA
lDD
COLLECTOR-BASE
CAPACITANCE vs Vee
.
= 25~~1
0."
40
0.50
rL"
:
30
!!
V·'1'2~
10
COLLECTOR CURRENT (mA)
BASE-EMITTER VOLTAGE
vs COLLECTOR CURRENT
SATURATION VOLTAGE
vs COLLECTOR CURRENT
0.1
0.01
TEMPERATURE (C)
COLLECTOR CURRENT (J&A)
+25'C -.
/'
100
0
~
V
t::VCB-ov
i!t;
~
-55 -35
lDOD
t::!A-2S·C
i
600
250
GAIN BANDWIDTH vs
COLLECTOR CURRENT
10DD
TA .25'C
1\
1\
I '~ t-
ilu
~
I.;'
20
u
0.45
...·c
OAO
0.01
0.01
IIII
0.1
0.35
1
10
I;'
1
10
10
100
1000
SMALL-SIGNAL INPUT
RESISTANCE (hi.,) vs
COLLECTOR CURRENT
fa
?
a
"
w
100
-5
-10
-15
-20
-25
-30
-35
COLLECTOR·BASE VOLTAGE (VOLTS)
10
~
~
.
!;
i!;
il
8
" 1\
;l
!.
o
l00~_
TA" 25·C
u
~
o
SMALL-SIGNAL OUTPUT
CONDUCTANCE (hoe) vs
COLLECTOR CURRENT
lDOD
~
w
z
lDODD
COLLECTOR CURRENT (J&A)
COLLECTOR CURRENT {mAl
10
~ 'III!II~!II
:I
,
}
1
1
1
10
100
lDDO
0.1
~
10
100
COLLECTOR CURRENT fllAl
COLLECTOR CURRENT (Jr,A)
118
2190, Rev. A1
SSM-2220 AUDIO DUAL MATCHED PNP TRANSISTOR
PULSE RESPONSE
-15V
+15V
JO.OO'.F
1.SkQ
1.5kD
0.01%
0.01%
~----~~------~
~=10
C,=30pF
LOW FREQUENCY NOISE
SSM·2220 PAIRS:
0,-02
0 3 -°4
os-o,
+15V
/\y= 1000
VEAT =1nV/D1V
FIGURE 1a: Super Low Noise Amplifier
APPLICATIONS INFORMATION
D.'
SUPER LOW NOISE AMPLIFIER
The circuit in Figure 1a is a super low noise amplifier with equivalent input voltage noise of 0.32nV/-iHZ. By paralleling SSM2220 matched pairs, a further reduction of amplifier noise is
attained by a reduction of the base spreading resistance by a
factor of 3, and consequently the noise byV3. Additionally, the
shot noise contribution is reduced by maintaining a high collector current (2mNdevice) which reduces the dynamic emitter
resistance and decreases voltage noise. The voltage noise is
inversely proportional to the square root of the stage current,
and current noise increases proportionally to the square root of
the stage current. Accordingly, this amplifier capitalizes on voltage noise reduction techniques at the expense of increasing the
current noise. However, high current noise is not usually important when dealing with low impedance sources.
g
I
y
liIl"D1°;.(
0.01
!i
!.
NO LOAD
~
i!
I!
D.",'D
100
1k
10k
lOOk
FREQUENCY (Hz)
FIGURE 1b: Super Low Noise Amplifier - Total Harmonic
Distortion
This amplifier exhibits excellent full power AC performance,
0.08% THO into a 6000 load, making it suitable for exacting
audio applications (see Figure 1b).
119
2190, Rev. A1
SSM-222D AUDIO DUAL MATCHED PNP TRANSISTOR
FIGURE 2: Super Low Noise Amplifier
LOW NOISE MICROPHONE PREAMPLIFIER
Figure 2 shows a microphone preamplifier that consists of a
SSM-2220 and a low noise op amp. The input stage operates at
a relatively high quiescent current of 2mA per side, which reduces the SSM-2220 transistor's voltage noise. The 1/t corner
is less than 1Hz. Total harmonic distortion is under 0.005% for
a 1OVp-p signal from 20Hz to 20kHz. The preamp gain is 100, but
can ~e modified by varying Rs or Rs ryOU-rNIN =Rs/Rs + 1).
A total input stage emitter current of 4mA is provided by 02. The
constant current in 02 is set by using the forward voltage of a
GaAsP LED as a reference. The difference between this voltage
and the VBE of a silicon transistor is predictable and constant (to
a few percent) over a wide temperature range. The voltage difference, approximately 1V, is dropped across the 2500 resistor
which produces a temperature stabilized emitter current.
120
2190, Rev_ A1
SSM·2220 AUDIO DUAL MATCHED PNP TRANSISTOR
.15V
+15V
ADJ~~~:~! I
(2V ACROSS 't
1kC RES)
en
O"fi
-15V
-15V
~
:I
SPOT NOISE FOR
EACH TRANSISTOR
en
II
to,ooox.fi
FIGURE 3: SSM-2220 Voltage Noise Measurement Circuit
SSM·2220 NOISE MEASUREMENT
All resistive components (Johnson noise, en 2 = 4kTBR, or en =
0.13 ,fA' nV/.vHZ, where R is in kQ) and semiconductor junctions (Shot noise, caused by current flowing through a junction,
produces voltage noise in series impedances such as transistor-collector load resistors, In = 0.556V1pN....iHZwhere I is in!lA)
contribute to the system input noise.
Figure 3 illustrates a technique for measuring the equivalent input noise voltage ofthe SSM-2220. 1mA of stage current is used
to bias each side ofthe differential pair. The 5kQ collector resistors noise contribution is insignificant compared to the voltage
noise ofthe SSM-2220. Since noise in the signal path is referred
back to the input, this voltage noise is attenuated by the gain of
the circuit. Consequently, the noise contribution of the collector
load resistors is only 0.048nV/ v"Hz. This is considerably less
than the typical 0.8nV/VHZinput noise voltage ofthe SSM-2220
transistor.
R
I
+V-2VSE
t I=-R-
FIGURE 4: Casco de Current Source
CURRENT SOURCES
A fundamental requirement for accurate current mirrors and
active load stages is matched transistor components. Due to the
excellent V BE matching (the voltage difference between VBE'S
required to equalize collector current) and gain matching, the
SSM-2220 can be used to implement a variety of standard cur·
rent mirrors that can source current into a load such as an amplifier stage. The advantages of current loads in amplifiers versus
resistors is an increase of voltage gain due to higher impedances, larger signal range, and in many applications, a wider
signal bandwidth.
The noise contribution of the OP-27 gain stages is also negligible due to the gain in the signal path. The op amp stages am·
plify the input referred noise of the transistors to increase the
signal strength to allow the noise spectral density (e in x 10000)
to be measured with a spectrum analyzer. And, since we assume equal noise contributions from each transistor in the SSM·
2220, the output is divided byv'2to determine a single transistor's input noise.
Air currents cause small temperature changes that can appear
as low frequency noise. To eliminate this noise source, the
measurement circuit must be thermally isolated. Effects of extraneous noise sources must also be eliminated by totally
shielding the circuit.
Figure 4 illustrates a cascode current mirror consisting of two
SSM-2220 transistor pairs.
121
2190, Rev. A1
SSM-2220 AUDIO DUAL MATCHED PNP TRANSISTOR
The cascode current source has a common base transistor in
series with the output which causes an increase in output impedance of the current source since VCE stays relatively constant. High frequency characteristics are improved due to a reduction of Miller capacitance. The small-signal output impedance can be determined by consulting "hoe vs. Collector Current" typical graph. Typical output impedance levels approach
the performance of a perfect current source.
(
----,
I
A CLOSELY MATCHED
) TRANSISTOR PAIR
Considering a typical collector current of 1OO~A, we have:
rOQ3=
1
1.0~MHOS
=IM!L
Q 2 and Q 3 are in series and operate at the same current level, so
the total output impedance is:
Ro = hFE rOQ3 " (160)(1 Mn) = 160Mn.
FIGURE Sa: Current Matching Circuit
CURRENT MATCHING
The objective of current source or mirror design is generation of
currents that are either matched or must maintain a constant ratio. However, mismatch of base-emitter voltages cause output
current errors. Considerthe example of Figure 5. If the resistors
and transistors are equal and the collector voltages are the
same, the collector currents will match precisely. Investigating
the current-matching errors resulting from a non-zero Vos' we
define Ll.lc as the current error between the two transistors.
1.2
'c. 1"", 'c. 10
1 .•
•.8
p::~~~~~8!
~
01 0
• 1-
Graph 5 describes the relationship of current matching errors
versus offset voltage for a specified average current Ie' Note
that since the relative error between the currents is exponentially proportional to the offset voltage, tight matching is required
to design high accuracy current sources. For example, if the
offset voltage is 5mV at 1OO~A collector current, the current
matching error would be 20%. Addnionally, temperature effects
such as offset drat (3~ VI·C per mV of Vos) will degrade performance if Q, and Q 2 are not well matched.
•.•
..•
I
/
II
....
~c·1mA
R.3kO
h FE _200
•.2
•
0.001
let +Ia
••01
0.1
1·'-241 .1 C1 -lcz
1•
I\,slmV)
FIGURE 5b: Current Matching Accuracy % vs. Offset Voltage
122
2190, Rev_ A1
SSM-2110
TRUE RMS-TO-DC
CONVERTER,
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
• Multiple Output Options (Absolute Value, RMS, Log RMS,
Log Absolute Value, Average Absolute Value)
• Wide Dynamic Range ............................................... 100dB
• Prebias Option for Fast Response at Low Signal Levels
• On-Chip Log Output Amplifier
• Optional Internal Log Output Temperature
Compensation
• Low Drift Internal Voltage Reference
• LowCost
The SSM-2ll 0 is a true RMS-to-DC converter designed to provide multiple linear and logarithmic output options. The linear
outputs, true RMS and absolute value, can be obtained simultaneously with the absolute value output configurable to give a
peak function. The logarithmic outputs can provide log RMS, log
absolute value or log average absolute value. Full on-chip temperature compensation is available for each output option.
Continued
PIN CONNECTIONS
APPLICATIONS
•
•
•
•
•
•
•
Audio Dynamic Range Processors
Audio Metering Systems
Digital Multimeters
Noise Testers
Panel Meters
Power Meters
Process Control Systems
la-PIN PLASTIC DIP
(P-Suffix)
FUNCTIONAL DIAGRAM
ABSOLUTE
LOGOUT
VALUE
RMS
V+
13
16
LOG
RECOVERY
AMPLIFIER
+LOG IN
0-"'0'+-_-1
-LOG IN
0-""'+---1
LOG SCALE
LOG
RECOVERY
TRANSISTOR
0-::'2+--_ _--'
.:J---t''-O
'----+=-0
INPUT
BASE
0"
O-::+---l
0.
EMmER
....---+"-0 GNO
RMS
COMPUnNG
LOOP
VAEF
<>-''+---------t-'t------+----- 10flARMS
l1knx CINT
Frequency Response (Sine Wave)
For 0.1 dB Additional Error
For 0.5dB Additional Error
BW
-3dB Bandwidth
Log Amp Output Offset Current
(Pin 9)
loos -LOG
Max Log Amp Output (Pin 9)
lOUT -LOG
liN> lmA RMS
liN> 10flARMS
liN> 1flA RMS
400
10
2
liN> lmA RMS
liN> 10flARMS
liN> 1flA RMs
1000
50
7.5
liN> lmA RMS
liN> 10flARMS
liN> 1flA RMS
1500
300
50
±250
Log Scale Factor
(Pin 2 or Pin 6)
kHz
±3.3
±13
flA
±265
±288
flA
+6
Log Mode Zero Crossing
(Mean or RMS, Pin 9)
RMS In To Get Zero Out (See Figure 7)
10
Log Amp Linearity (Pin 9)
-240mV < VplN 10 - VplN 11 < +24DmV
0.1
Log OutputTempco
O'C
Vp
2 'Vp
v'2
It
Vp
Vp
~
~
CREST
FACTOR
Vp
= RMS
v'2 =1.414
SINE WAVE
Vp
--
1
SQUARE WAVE
Vp
v'2
Va
..f3 =1.732
TRIANGLE WAVE
2v·1 A \;;JL
.Ifi
RMS
xRMS
Typically varies from 1 to 6 de·
pending on the characteristic of
the noise. Theoretically, the
crest factor is unlimited.
GAUSSIAN NOISE
FIGURE11: RMS, Average of Absolute Value and Crest Factors for Different Waveforms
132
2190, Rev. A1
SSM·2110 TRUE RMS·TO·DC CONVERTER
100pF
-15V
GAIN
4.64kn 22
REDUCTION
RATIO
10ke
015T
NULL
10ke 10
SSM·2134
+15Y
O.1~
lSkn
15kn 7
-=-
NONINVERTING o--IIN'-.......--''-j
30pF
INPUT
INVErJ~~~ o--IIN'-.....---''-l
_:-j:
14
';OO>'kC'-....
GND C>-1>-.t1N'-..J
1 10
l~~
35V
+15V
3.321dl
GAINI:·:.:c:_ _--iDr==__-+2kQ
.15V
LIMIT
AnACK
~'rF_~'~OVkQ~~_ _ _ _ _0~.012r~_F,
FASro-J
SSM·2UQ
I
31.SkQ + - - - - v W ' - - - - - +
100ka
10%
TANTALUM
-15V
OUTPUT LEVEL ~ ..'.:c0k;:;g_ _ _ _ _- ,
22Mn
AGcl'0kg
RELEASE
t
t
FAST
U1
1.5kO
S5M·2013
R",
U 2 • U 3 SSM·2134
U4
SSM·211D
Us
1/2 OP·215GP
U.
1/2 Op·215GP
15kn
NOTE: U 2'U 3'U 5 _& U6
POWER SUPPLY CONNECTIONS
-15Y
AND BYPASSING ARE NOT SHOWN
-15V
TYPICAL APPLICATIONS
AUTOMATIC GAIN CONTROL (AGC) AMPLIFIER
The automatic gain control amplifier shown below features se·
lectable gain reduction compression ratios and time domain
adjustable AGC attack and release. The design employs the
SSM·2013 VCA, SSM·2110 true RMS·to·DC converter, two
SSM·2134 low noise op amps and an OP·215 FET inputop amp.
For additional information about this circuit, please see PMI
application note AN·116.
133
2190, Rev. A1
SSM-2044
4-POLE VOLTAGE-CONTROLLED
FILTER/OSCILLATOR
Precision l\1onolithics Inc.
FEATURES
• Outstanding Frequency Control Range ••• 10,000 to 1 Min
• Stable Resonance OVer Frequency Sweep
• Mlnlmun External Parts Count
• High Control Rejection ... For 1000 to 1 SWeep 36dB Typ
• On-Chip Resonance Control
• Excellent Dynamic Range ................................. 90dB Typ
• Gain Bandwidth ••••••••••••••••••••••••••••••.••••••••••••••••••• 1MHz Typ
• Wide Supply Voltage Range.,......................... ±5V to ±18V
• Low Cost
with a 10,000 to 1 variable cutoff frequency. The cutoff frequency
is determined by a control voltage, making the device ideal for
real-time analog filtering under microprocessor control.
APPLICATIONS
• Voltage Controlled Oscillators
• Anti-Aliasing and Reconstruction Filtering
• Medical Imaging and Ultra-Sound Systems
• Instrumentation and Sonar Systems
• Lower Noise Alternative to Switched-Capacitor Filters
PIN CONNECTIONS
A unique feature of the SSM-2044 is its on-chip resonance
control, which can produce a low distortion sine wave for use in
Voltage-Controlled Oscillator (VeO) applications.
A novel filtering technique provides extended control range, low
noise, and high control rejection of 36dB (Typ) for 'pop'-free
performance.
16-PIN
PLASTIC DIP
(P·Sufflx)
GENERAL DESCRIPTION
The SSM-2044 is a low cost 4-pole Voltage-Controlled Filterl
Oscillator which has been designed as a -24/dB low-pass filter
BLOCK DIAGRAM
B
L,...-r--j--I---I-~A 14
Manufactured under the following U. S. patent: 4,404,529
134
2190, Rev. A1
SSM-2044 4-POLE VOLTAGE·CONTROLLED FILTER/OCILLATOR
ABSOLUTE MAXIMUM RATINGS
The SSM-2044's dynamic range of 90dB (Typ) and gain band·
width of 1 MHz (Typ) make this device agood low noise alternative
to switched-capacitor filters in a wide variety of applications, such
as anti-aliasing and reconstruction filtering, medical/ultra-sound,
instrumentation, and sonar systems.
Positive Supply Voltage ................................................... + lav
Negative Supply Voltage ................................................. -laV
Storage Temperature, P-Package ................ -55°C to + 125°C
Lead Temperature (Soldering, 60 sec) ........................ +300'C
Junction Temperature ................................................... + l50C
Operating Temperature, P-Package ................... O°C to +70°C
The SSM-2044's performance and characteristics are guaran·
teed over the O°C to +70°C temperature range and it is available
in 16-pin epoxy DIP package,
PACKAGE TYPE
16·Pin Plastic DIP (P)
ORDERING INFORMATION
PACKAGE
SSM2044P
82
39
'C/W
NOTE:
1. a'A is specified for worst case mounting conditions, i.e., a'A is specilied for
dbvice in socket for P.DIP package.
I
OPERATING
TEMPERATURE
RANGE
PLASTIC
16-PIN
UNITS
alA (Note 1)
O'Cta +70'C
ELECTRICAL CHARACTERISTICS
at Vs = ±15V, TA = +25°C, unless otherwise noted.
SSM-2044
TYP
PARAMETER
SYMBOL
MAX
UNITS
Positive Supply Range
v+
+5
+15
+18
V
Negative Supply Range
V-
-5
-15
-18
V
3.0
5.4
8.5
mA
4.5
8.0
11.5
mA
10,000:1
50,000:1
dB
CONDITIONS
MIN
Positive Supply Current
Isy+
V'c = OV(Pin 13 ta GND)
Negative Supply Current
I.y-
V'c = OV (Pin 13 to GND)
Frequency Control Range
±VIN = OV, -90mV s V'c S +90mV
Frequency Control Feedthrough
-36
-26
0.035
0.12
675
900
1200
Q
450
500
550
/LA
-30
-20
Output Olfset
IdloMAX
± VIN = V'c = OV
Normalized Frequency
IIfNOMINAL
Untrimmed
0.6
a Control Input Impedance
RINOC
Voc ,,0.7V
Q Current at Oscillation
loos
-90mV S V'c S +90mV
Q Control Feedthrough
400
500
1.25
1.7
Q Control Threshold Voltage
Voc THRESHOLD
Maximum Available
Control Current
lOMAX
Frequency Control
Input Range
V'c
-120
Maximum Output
Signal Current
IOMA/<
±300
Signal·to·Noise
SIN
VPINI3=-120mV
Reference to 30mV p.p (Pin 1 or 15)
1.5
±400
70
dB
mV
2.2
mA
+180
mV
±520
/LA
dB
MHz
Gain Bandwidth
Specifications subject to change; consult latest data sheet.
135
2/90, Rev. A1
SSM·2044 4·POLE VOLTAGE·CONTROLLED FILTER/OCILLATOR
of the filter at minimum a with a gradual rolloff approaching
-24dB/octave at higher frequencies. As a increases, the low
frequency components are suppressed and the components
near the cutoff frequency are emphasized. For all a settings
below oscillation, the final rolloff at high frequencies is -24dBI
octave. At high a settings, the filter will oscillate with a pure
sinewave althe cutoff frequency. Oscillation will occur when the
current into the a control reaches approximately 500IlA.
(Figures 2, through 5 show the Square Wave resonance
response vs. the a-curren!.)
APPLICATIONS INFORMATION
PRINCIPLE OF OPERATION
The SSM·2044 provides two major control functions controlled
by two separate control input pins (pins 2 and 13). The voltage
(V ) on the frequency control pin (pin 13) determines the cutoff
fr~~uency of the filter; the current (10) sourced into the a control
(pin 2) determines the amount of the peaking in the filter
frequency response by controlling the gain of the feedback
amplifier.
Figure 1 shows the normalized amplitude vs. frequency for the
SSM·2044 operating at a constant cutoff frequency for different
a or resonance settings. The overdamped curve is the response
INCREASING
o
CUTOFF
Jr
OdS OVERDAMPED
/ 1\
- ..... /
\
'>:
w
o
~
''""
-12d8
\
---:.HIGHLY UNOEROAMPBl
1 \
1 \
\1 \
\
\
FIGURE4
-24dB/OCTAVE
FREQUENCY/FREQUENCY NOMINAL
FIGURE 1: Normalized Amplitude vs. Frequency Response
la
=500ilA (OSCILLATION)
FIGURE 5
FIGURE 2
FIGURE3
136
2190, Rev. A1
SSM-2044 4-POLE VOLTAGE-CONTROLLED FILTER/OSCILLATOR
When Q =OV, the feedback loop will be eliminated and the SSM2044 will have a fourth-order transfer function with only one pole
position. This will result in having all four poles on top of each
other (see Figure 6).
applications where more precise control of the Q is desired, a
"reverse-audio" taper pot can be connected to the Q control pin
(pin 2) of the SSM-2044 (see Figure 9).
Combining the SSM-2044 with a "reverse-audio" taper pot will
change the shape of the curve in Figure 8 to the one shown in
Figure 10. By comparing the two graphs, it can be observed
that when using the SSM-2044 by itself, the last 10 percent of
the pot travel in the Q panel control will result in a 50 percent
change in resonance. Using a "reverse-audio" taper pot in
conjuction with the SSM-2044 will result in about 20 percent
change in resonance for the same last 10 percent of pot travel.
As Q increases in the positive direction, the four poles of the
SSM-2044 will be separated from each other and will travel in
the direction shown in Figure 7. This will continue until the poles
reach the imaginary axis. As previously stated, the oscillation
will occur when the current into the Q control pin (pin 2) reaches
approximately 500",A. This corresponds to +7.5V with the input
resistors shown in Figure 11.
This oscillating waveform can be used as a tone source. The
V/octave trim and the temperature compensation resistor (see
Figure 11) are required in applications where the filter has to
produce accurate musical intervals when in oscillation. If this is
not necessary, the control op amp feedback network and the
temperature compensation resistor can be replaced by 300kQ
and 1kQ resistors respectively.
100
OSCILLATION
60
~
Figure 8 shows Q or resonance of a four-pole low-pass filter as
a function of feedback or Q control current. The function
changes very slowly with control current at the low end of the
range but increases very rapidly as oscillation is approached. In
60
~
RESONANCE.
o
~ 40
20
o
OSCILLATION
-
V
o
100
I'"
200
V
~
'·f
I
I
V
/
400
300
500
Ie (I'A)
FIGURE 8: Q-Control Transfer Curve
FOURTH ORDER
r-v--
3.3kQ
v+ = 15V
5kO
15kn
REVERSE
AUDIO
2
SSM·2044
1.8kQ
':'
FIGURE 9: "Reverse-Audio" Pot
FIGURE 6: Fourth-Order Transfer Function Q = OV
100
r---r--..,...--r--"'--~
OSCILLATION
je
80~-4---+--~-~~~
g 60 1---+---I---J.,£.-4--1--1
"~
~
~ 40
o~~~==~--L--~-~
o
20
40
60
aD
100
POT ROTATION (%)
FIGURE 10: SSM-2044 and "Reverse-Audio" Pot
Transfer Curves
FIGURE 7: Transfer Function as Q -Increasing
137
V90,Rev.A1
SSM-2044 4-POLE VOLTAGE-CONTROLLED FILTER/OCILLATOR
In other words, the "reverse-audio" pot will help to reduce the Q
panel control sensitivity before reaching oscillation.
resistor and the series resistor from pin 13 to a control voltage
source form an attenuatorthat determines the frequency control
scale factor which is about -18mV/octave at the pin. This
attenuator will have a temperature drift of -3300PPMrC. To
offset this, a thermistor (in lieu of the 1kn resistor) with opposite
drift characteristics should be connected from pin 13 to ground
(for a possible thermistor source see Note 1). For best dynamic
range, the control summer and the input attenuator should be
designed so that the maximum swing at the SSM-2044's control
pin corresponds 10 the extremes of the intended sweep range
when the control summer is driven to the supplies. With the
values shown in Figure 11, the voltage at the input pin will be
±90mV which corresponds to a 1000-to-l sweep range for±15V
supplies.
TYPICAL CONNECTION
Figure 11 shows the typical connection of the SSM-2044 as a
four-pole filter. The differential inputs will accept any signal(s)
up to ±18Vp.p'
The control summer adds the voltages of various control
sources such as fe panel controls, transient generators, LFOs,
etc. Any number of signals can be summed by applying them
through resistors to the summing node of the op amp. The
frequency offset adjust is required in polyphonic and
programmable systems to make the filter(s) sound the same for
identical input control voltages.
The frequency control pin (pin 13) should be terminated to
ground through a resistor of 1knor less. The combination ofthis
I~---------------,
SSM·2044
I
I
47kn
~1-P~Ll-~l1
O.01J1F
~J-b:i--rrI~A1.
10
~----+----4--------+--O~
SIO IN -
0-"""1'-_----0+----,
SIQ IN +
o-M"--_----oJ---_,...--r.:
820pF
a CONTROL C>--Nlf>-------<:>-!----------II--.lW--,
100kn
"Reo Components, MWlchester, N.H., TEL: (603) 669·0054 TLX: 943512
FIGURE11: Typical Connection
138
2190, Rev. A1
SSM-2044 4-POLE VOLTAGE-CONTROLLED FILTER/OSCILLATOR
shown in the Figure 12, an offset adjustment is not required to
guarantee a worst case 30dB VeA control rejection.
VOLTAGE CONTROLLED AMPLIFIER INTERFACE
Figure 12 shows the SSM-2044 is capable of driving a yeA's
input without an intervening op amp. The 11-lF capacitor
provides a De block so that the SSM-2044 offset will not affect
the De balance of the SSM-2024 yeA. With the connection
The SSM-2024 Quad veA is an excellent companion to the
SSM-2044. The SSM-2024's channel specifications offer
excellent performance in control mixers as well as a voicing
yeA.
10kn
20kll
SSM-2044
FIGURE 12: VCA Interface
-5IGIN
2000
68kO
+
SIG IN o-----N>I-----......I----.!..j
lSkO
QCO~ROLo------~VY--~4
47kn
1501(0
OUT
470kn
v-
v.
SOkn
y-
FREQUENCY OFFSET ADJUST
-RCD Components, Manchester, N.H., TEL: (603) 669·0054 TLX: 943512
ALL COMPONENTS 5% UNLESS NOTED
FIGURE 13: Typical Connection for Breadboarding Purposes
139
2/90, Rev. A1
SSM-2045
VOLTAGE-CONTROLLED
SIGNAL PROCESSOR
Precision Monolithics Inc.
monolithic device includes a voltage-controlled filter with 2-pole
and 4-pole low pass outputs and an uncommitted mixerlVCA
combination.
FEATURES
•
•
•
•
•
•
•
2-Pole and 4-Pole Low Pass Filter Outputs
On-Chip Q Control, MlxerIVCA
Low Offset
Low Noise (SOdB Below Nominal Signal Level)
Low Control Feedthrough
±15 Volt Operation
Separate Linear and Exponential Cross Fade
Mixer Controls
The filter section has exceptionally low noise, offset and control
feedthrough delivering quality performance even in systems
where the filter is not followed by a VCA. A voltage-controlled
feedback amplifier gives built-in electronic Q control with a minimum amount of in-band loss at the oscillation point.
The mixerlVCA section can be connected to the filter input for
waveform mixing or the outputs for mixing between the 2-pole
and 4-pole responses. The two linear and exponential cross
fade controls allow this circuit to be used both as a mixer and a
VCA. This section has excellent offset, signal-to-noise and control feedthrough specifications. AC coupling between the filter
and mixerlVCA is not required.
APPLICATIONS
•
•
•
•
Music Voicing Systems
Audio Filtering
Antiallaslng Systems
Voltage-Controlled Oscillators
Continued
PIN CONNECTIONS
ORDERING INFORMATION
PACKAGE
PLASTIC
la-PIN
OPERATING
TEMPERATURE
RANGE
SSM2045P
O'C to +70'C
1S-PIN PLASTIC DIP
(P-Sufflx)
GENERAL DESCRIPTION
The SSM-2045 is a flexible, high performance building block
which offers maximum options for active filter design. This
BLOCK DIAGRAM
c,
c,
C,
Q
C,
v.
2-POLEOUT
v-
LOW PASS FILTER
SECTION
4·POLE OUT
SIGNAL IN
r ' ~--------------t-o~
GND
-=
,---------------------------:
t
t
:
MIXER/YCA SECTION
I
MIX11N
MIX21N
EXPO MIX
LlNMIX1
MIX OUT
LIN MIX 2
The SSM-2045 has been granted mask work protection under the Semiconductor Chip Protection Act of 1983.
140
2/90 Rev. A1
SSM-2045 VOLTAGEoCONTROLLED SIGNAL PROCESSOR
Storage Temp Range ...................................... -6S· to + 1S0·C
Lead Temp Range (Soldering, 60 sec) ........................ +300·C
Junction Temperature .................................................. +1S0·C
Operating Temp Range ...................................... O·C to +70·C
GENERAL DESCRIPTION Continued
Use in audio applications provides a "fat" open-loop type sound.
Additional features such as a series voltage-controlled high
pass filter can be designed using the VCF and onboard VCAs or
by using the VCF with the SSM-2024.
PACKAGE TYPE
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage ................................................... + 18V
Negative Supply Voltage ................................................. -18V
UNITS
alA (Note 1)
H!·Pin Plastic DIP (P)
70
30
'CIW
NOTE:
1. a jA Is specified lor worst case mounting conditions, I.e., a jA is specilied for
device in socket for P·DIP package.
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +2S·C, unless otherwise noted.
SSM-2045
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
3.0
5.0
9.0
mA
5.0
6.5
7.1
mA
-62.5
+62.5
mV
-62.5
+62.5
mV
+31.25
·mV
FILTER SECTION
Positive Supply Current
Negative Supply Current
VpIN5 =GND, IpINI5_17 =0 (Note 1)
Output Offset (Pin 1)
VpINs=GND
Output Offset (Pin 8)
Change in OutputOffset(Pin 1)
-90mV < VplN 5 < +90mV
-31.25
Change in Output Offset (Pin 8)
-90mV < VPIN 5 < +90mV
-31.25
+31.25
mV
150
300
mV...."
3
mV...."
5
10
15
mV
600
750
900
J1A
1000:1
5000:1
Signal Input Level (Pin 2)
Signal Output (Pin 1,8)
Output Source Current (Pin 1,8)
Output Sink Current (Pin 1, 8)
Frequency Control Range
Fc Input Bias Current (Pin 5)
1.0
Fc Scale Factor Drift
2.5
J1A
-3300
ppm/'C
Fc Control Sensitivity (Pin 5)
-20
-19.3
-18.7
Q Current Required for Oscillation (Pin 17)
120
150
185
mY/OCTAVE
J1A
Dynamic Range
VPIN 5 = -90mV (Filter Wide Open)
92
In Band Distortion (THD) (4FIN sFc)
At 150V...." IN
0.1
%
Max Distortion (THD) (FIN = Fc)
At 150V...."IN
1.0
%
dB
MIXERIVCA SECTION
Output Offset Current
VplN 11 = VplN 12 = VplN 14 = GND
IplN 15 = 500)1A, IplN 16 = 0
or
-12.5
+12.5
J1A
-1
+1
nA
4330
J1mhos
-0.5
+0.5
dB
-50
-5
J1A
30
dB
IplN 16 = 500)1A, IplN 15 = 0
Output Leakage
IplN 1S
VCAGain
IplN 15 = IplN 16 = 500)1A
IplN 14 = GND
=
IplN 16
=0
3842
VCA Gain Matching
Mix Expo Input Bias Current (Pin 14)
IplN 15 = 500)1A, IplN 14· GND
Control Rejection (Untrimmed)
RE 40mV...." (Pin lIar 12)
4085
41.5
Signal·to·Noise Ratio
RE 40mV....,,(Pin lIar 12)
82
dB
Distortion
40mV...." (Pin lIar 12)
0.3
%
Specifications subject to change: consult latest data sheet.
NOTE:
1. Resistor in series with pin 10 required for negative voltage supply voltage
S-6.BV.
141
2/90 Rev. A1
SSM·2045 VOLTAGE·CONTROLLED SIGNAL PROCESSOR
Q CONTROL CHARACTERISTICS
00
Iii
'pJ-..I......~.......
1
.tb
--'---
..... -
I
•
10
!
__
H + . -..
I ___ )'._.
: ___
•
I
fl!_l
I'
=150llA (Oscillation)
FUNCTIONAL DIAGRAM
6.8V
GND~V-
B.1kQ
SIGNAL IN
o'-2_~-l
r ......=-o '·POLE OUT
~·"ri
.'
.
,
'500
.---.lI/V'---'-O LIN MIX 2
14
EXPO MIX
MIX OUT
MIXIlN~--'-.----------<
13
142
MIX21N
2190, Rev. A1
SSM·2045 VOLTAGE·CONTROLLED SIGNAL PROCESSOR
15kn
O~~'--------~
SIGNAL
INPUTIS)
1SkQI..._________ .
o----I>N
20kQ
15kg
~--------~~~Q
56kQ
I
I
I
I
=I
OUT
O.47"F
1kD
I
I
11
I
I
3.9kD
10kO
+-------~NV'--------{)MIX EXPO
200D
FIGURE 1: SSM·2045 Typical Connection
The output can source more than the 10mA and sink approxi·
mately 750f1A. Resistors can be connected from the outputs to
the negative supply to increase sink current capability. The 2·
pole output is inverted with respect to the 4·pole output.
TYPICAL CONNECTION
Figure 1 shows a typical connection of the SSM·2045. The in·
puts of the MixerNCA are connected to the 2· and 4·pole out·
puts of the filter section. This allows the relative amount of the
two low pass responses to be placed under program control via
the expo mix control. The envelope is applied to the two linear
mix controls. This determines the overall volume at the final
output.
The signal·to·noise ratio of the filter section is 84dB for 150m
Vp.p at the signal input pin which allows for more than 6dB of
headroom. The worst case control feedthrough referred to this
signal level is -32dB, 12dB better than conventional designs.
MIXERNCA SECTION
FILTER SECTION
This section is completely independent of the filter circuit allow·
ing it to meet a variety of system requirements. First, it can be
used as both a VCA and as a cross fade control between the 2·
pole and 4·pole filter outputs. It can also be used in a similar
manner as a volume contour VCA and to mix tone sources to the
filter input. With most filters, placing the volume VCA before the
filter would be unacceptable as the VCA as a follower is used to
mask the filter background noise and control feedthrough.
However, the filter specifications of the SSM·2045 will allow this
configuration. For designs with more than two sources, a third
oscillator or noise generator for example, the additional signals
can be mixed or switched to the filter input using simple resistor
summing, CMOS transmission gates or the SSM·2024.
The signal input has an input impedance of 900r.! and accepts a
nominal input signal of 150mVp.p. Higher signal levels can be
used if the increased distortion is compatible with the desired
sound. Signals can be summed at the input using a resistor
network, the on·chip mixerNCA or a multiple VCA IC such as
. the SSM·2024.
The frequency control input (pin 5) can vary the cutoff frequency
over a 5000:1 range. Usually the sweep is restricted to 1000:1
which corresponds to ±90mV at the pin. With the input attenu·
ator shown in Figure 1, the F G control sensitivity is about -1
octave per volt. For best control rejection, a time constant of ap·
proximately 500flS should be established to limit rapid voltage
changes either at the input pin or in the preceding control sum·
mer.
The impedance from the signal inputs of the VCAs to ground
should be approximately 91 Or.! for the best offset and control
rejection performance. The overall performance of the VCAs
with respect to signal·to·noise ratio, control rejection and distor·
tion vs. input signal level is identical to the SSM·2024.
The frequency control pin (pin 5) should be terminated to ground
through a resistor of ,,1 kr.!. A series resistor from pin 5 to a
control voltage source and the ground connected'resistor form
an input attenuator that determines the frequency control scale
factor which is approximately -18mVloctave atthe pin. This has
a temperature drift of 3300ppm/"C. A tempsistorwith similar drift
to the ground connected ground resistor can minimize drift ef·
fect (see note).
Nate: RCO Components. Manchester, N.H. USA, Telephone: (603) 669·0054 TLX: 943512
143
2/90, Rev. A1
SSM-2045 VOLTAGE·CONTROLLED SIGNAL PROCESSOR
MIXERNCA PERFORMANCE
lOa
/.
"
Ii
./
"-
~
70
~
60
a
/"
I-'
VL (MAX)'RL:5 250"A
/
SIGNAL TO N : y
V
let + IC2 :II SOOj.LA
/
/
"
"
/cONTROL REJECTION (MIN)
TOVCA1
/
3D
3
10
'00
3D
3D0
FIGURE 3
INPUT SIGNAL lEVEL (mVp.p)
10.00
/
'.00
/
0.30
/V
Q
j:
A series voltage· controlled high pass filter can also be made
with this section (Figure 2a). Figure 2b shows a similar circuit
using one section of the SSM-2024. The input signal level of
these two circuits must be no more than 500mVp-p unless pad·
ded as shown. The output level c;an be set by scaling R3 - Rs'
v
3.00
!
TO VCA 2
0.10
The controls of the MixerNCA section offer maximum flexibility
as several control configurations and response characteristics
are possible. Figure 3 shows both the VCA inputs connected for
linear control. A VCA will be completely off when corresponding
input control voltage is within 500mV of ground. The series reo
sistor to linear control input should be chosen to give < 250!-,A at
the maximum control voltage.
/
0.03
0.01
/
/
0.003
3
10
3D
100
3D0
INPUT SIGNAL LEVEL ImVp.p)
b)
a)
R,
------.T----,i
i ':'
H.P.IN<>-----v'IIV"'·
Rc 16 4500
H.P. CONTROL.O-,JVI,"-C'I--IW-..,
R,
H.P. IN C>----NII""- - - -......-----,
RC
H.P. CONTROLQ--o/VI,I'--.,
I
R••• kIJ
....L
CHP
+
H.P.OUTl
11
H.P.OUT
910g
910D
NOTE:
VCA21S OFF, PINS 12, 14 AND 15 ARE GND
FIGURE2
144
2/90, Rev. A1
SSM·2045 VOLTAGE-CONTROLLED SIGNAL PROCESSOR
a)
a)
R3 VAT (MAX)
2 (R2 ... A3)
450{)
=Voe
R 2 +R 3 =10R,
VAT (MAX)
~=500~A
TO PIN(S) 15 AND/OR 16
TO veA 1
TO VCA2
b)
b)
IC(MAX)
r - - - - -....- - - - - - "
-........
-6
0.75
/
-12
f------j-----,f--j
/
II
-18
-24
O.SO
f------j---f----j
-36
-42
0.251------1-1'-----1
-48
1/2 VAT (MAX)
/
.. 0
-250
VAT (MAX)
"- \.
\
1\VCA'
veA1
-30
-54
/'
I
I
I
I
\
-125
\
\
\
+125
\
+250
Ve (PIN 14, mY)
CONTROL VOLTAGE
FIGURE4
FIGURE5
Figure 4a shows a circuit that can be added in series with a linear control input to give an audio taper control response. The
network around the transistor is desired so the the impedance
seen by the control voltage decreases by a factor of ten when
the control voltage exceeds half its maximum value. At this
point, the transistor turns on and almost all additional control
passes through the transistor. Figure 4b shows the approximate
control characteristic of the circuit.
directly to pin 10. For a negative supply voltage below -6.8V, a
series resistor is used with a value determined by the following
equation:
The control for the combined linear and exponential cross-fade
control is given in Figure 5a. This circuit splits a common linear
control current between two VCAs according to the transfer
characteristics of a differential input pair. An envelope generator can be applied to the common generator linear input to control overall volume contour while the relative amount of the two
Signals, of the VCAs in the mix is determined by the voltage on
pin 14. The characteristic of this control is shown in Figure 5b.
Example: Butterworth Rolloff Characteristic
RLlMIT = (Vee-6.8)/7.1mA for Vee <-6.8V
CALCULATING THE SSM-2045 FILTER RESPONSE
CHARACTERISTIC
Each 2-pole section in the SSM-2045 obeys the generalized 2pole low pass transfer function:
VOUT = H(s)
VIN
where (J)0 21t = fCUTCfF and a
If cross-fade control is desired, a resistor can be connected to
the common linear control from the positive supply to give a
current of 500flA or less.
_.1.
Q
Deriving for the SSM-2045 gives the following:
POWER SUPPLIES
The SSM-2045 is designed to give best overall performance
when operated from ± 15 volt supplies. Supply voltages down to
±5V can be accommodated with increasing degradation of
some specifications, notably VCA offset and control
feedthrough. The negative supply can be any value below -5V
with no change in performance. A -5V supply can be connected
VOUT
-gm2 /(Cl10C2)
VIN
S2 + s gm/Cl + gm2 /(Cl 10 C2)
Comparing the generalized equation with the equation for the
SSM-2045 we have:
H0 = -1, (J)0 =
145
gm
and a " J...
YC 110C2
Q
~
C1
2/90, Rev. A 1
SSM-2045 VOLTAGE-CONTROLLED SIGNAL PROCESSOR
These last two equations allow calculation of the capacitor values for a desired transfer characteristic. Note that C 2 behaves
as if it were 10 times its actual value. This is due to the gain of 10
in the second and fourth filter stages.
trolled. Also, the oscillation amplitude with a given feedback is
nearly constant over the audio band as the frequency is swept.
TYPICAL APPLICATION
Figure 6 shows an application using two SSM-2045 Mixer/VCA
sections which in addition to providing the basic dual VCA function, also positions the two sound sources in the left-right stereo
image field under voltage control. Signal 1 and Signal 2 amplitude are the overall linear VCA gain control ports while the Signal1 and Signal 2 Pan inputs control the relative amount of signals appearing in the two output channels. Note that each sound
source can be both separately enveloped and positioned. Each
half section works as described for the linear-exponential crossfade circuit shown in Figures 5a and 5b.
DESIGN EXAMPLE
The principle application ofthe SSM-2045 is a low pass filter with
2- and 4-pole outputs. If a Butterworth (maximally flat) rolloff
characteristic with no feedback (10 ~ 0) is desired as the final 4pole output, filter design tables would show:
W~1 ~ w~2'
u1 ~ 1.85 and u 2 ~ 0.765
So the first 2-pole section would be overdampened and the
second would be underdampened. Choosing C, ~ 0.011lF we
find:
C,
~
0.01IlF, C2
'"
The Signal 1 and Signal 2 inputs can be connected to the outputs of the SSM-2045 filter sections in the two ICs. This scheme
can easily be extended to any polyphonic music system having
any multiple of two voices. In such a system, all the left and all
the right current outputs can be connected together to the virtual
ground inputs of the two op amp current-to-voltage converters.
Note that since the left and right VCA inputs are inverted for each
signal, one of the final outputs, either left or right, should be
inverted to avoid phase cancellation.
3300pF, C3 .. 0.024IlF, C4 .. 1500pF
This does produce a system with the correct response, however, performance under feedback is poor because of the high
feedback gain required for oscillation. If W~l is increased by
approximately an octave and we recalculate:
C, ~ 0.01IlF, C2 '" 3300pF, C3
'"
0.01IlF, C4 '" 680pF
This yields a system with excellent sonic quality. The onset of
oscillation with increasing feedback is smooth and well con-
4500
SIGNAL 1 AMPLITUDE
SIGNAL 1 PAN
4500
o-oM"--Q---_t_--[.
~-+
SIGNAL 1 INPUT O":'oM"--~~_t__o_--l
SIGNAL 2 INPUT
...--oI'VV'--o--NV'--''':'::''''--IVV'--o SIGNAL 2 PAN
>-+_____...-'-'3::::8'0
RIGHT
470Q
4700
FIGURE 6: Dual VCAlStereo Panning Circuit
146
2190, Rev_A 1
SSM-2047
VOLTAGE-CONTROLLED FILTER
WITH TRIPLE VCAs
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
• 4 Pole Low-Pass Filter and On-Board Parallel Output
VCAs
• 92dB VCF Dynamic Range
• Low Distortion VCF and VCAs
• Low Control Feedthrough
• Full Class A Signal Path
• dBlVolt Master Gain and Pan Controls
The SSM-2047 is a dedicated signal processing array designed
to conform to the demands of state-of-the-art systems. Provided
on-chip is a four pole low-pass voltage-controlled filter and three
output VCAs which feature individual channel as well as mixable
left and right independent outputs.
The filter section has been designed for low distortion, wide
dynamic range and low offset. A voltage-controlled feedback
amplifier gives built-in electronic Q (resonance) control with a
minimum of in-band loss at the oscillation point.
APPLICATIONS
•
•
•
•
The output VCAs are low control feedthrough, full Class A devices connected in parallel rather than in series for less noise
and distortion build up.
Digital Audio Systems
Antiallaslng and Reconstruction Filters
Flight Simulators
Sound Effects
The master gain and stereo pan pins have exponential (dBlvolt)
control characteristics. Unit-to-unit frequency and amplitude
variability is reduced by external reference resistors.
ORDERING INFORMATION
PACKAGE
PLASTIC
18-PIN
OPERATING
TEMPERATURE
RANGE
SSM2047P
ooe to +70 e
BLOCK DIAGRAM
0
PIN CONNECTIONS
SIGNAL
IN
PANo-~----.r---'
18-PIN
PLASTIC DIP
(P-Sufflx)
MASTER
GAIN
GREF
v.
v-
Cep
GND
ROUT Lour CHANNEL
OUT
147
2190, Rev. A1
SSM-2047 VOLTAGE-CONTROLLED FILTER WITH TRIPLE VCAs
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage ................................................... + 18V
Negative Supply Voltage ................................................. -18V
Storage Temperature Range ........................ -65°C 10 + 150°C
Lead Temperature Range (Soldering, 60 sec) ............ +300°C
Junction Temperature .................................................. + 150°C
Operating Temperature Range ........................... O°C to +70°C
ELECTRICAL CHARACTERISTICS al Vs
aJA (Note 1)
PACKAGE TYPE
70
18·Pin Plastic DIP (P)
UNITS
30
NOTE:
1. a'A is specified for worst case mounting conditions, i.e., a'A is specified for
d/.vice in socket for P.DIP package.
J
= ±15V, TA = +25°C, unless otherwise noted.
SSM-2047
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
10.2
11.5
mA
8.15
9.8
mA
1.35
2.7
7.2
9.84
kn
+5
+15
mV
-36
-28
dB
12
14
Octaves
1.00
1.08
F/F nom
1.25
2.5
-19.3
-18.7
Positive Supply
Current
V pIN9 = V plN 12= GND
8.5
Negative Supply
Current
V PIN9 = V plN 12= GND
6,5
Filter Section @ IFREF = IOIlA
Signal Input Level (Pin 8)
6.56
Input Impedance (Pin 8)
Output Offset (Pin 15)
Frequency Control
Feedthrough (Pin 15)
-90mV ,; VPIN 9 ,; = 90mV
(Note 2)
Frequency Control Range
(Pin 9)
Center Frequency
Variability
VpIN9 =GND
Fe Input Bias
Current (Pin 9)
VpIN9 =GND
0.92
Frequency Control
Sensitivity (Pin 9)
-20
-3300
Fe Scale Factor Drift
Q Current Required
40
for Oscillation (Pin 2)
Q Control Feedthrough
(Pin 15)
Dynamic Range
(Clipping to Noise Floor)
OSIoS601lA
(Note 2)
mY/Octave
ppm/"C
75
100
-26
-16
dB
92
dB
In·Band Distortion 4FIN < Fe
0.1
%
Max Distortion FIN = Fe
1.0
%
VPIN 9 = -90mV
Output VCAs @ IG REF = 300llA
Max VCA Gain (Pins 13, 14 and 16)
VplN 12= OV
V PIN 1 = +300mV or -300mV
Output Leakage
(Pins 13, 14 and 16)
V PIN 12 = +400mV
Left·Right Gain Matching
(Pins 14, 16)
VplN 1 = V plN 12= GND
Gain Control Input
Bias Current(Pin 12)
VplN 12= OV
1.0
Pan Control Input
Bias Current (Pin 1)
V pIN1 =OV
0.5
Control Feedthrough
(Note 2)
-41.5
Signal-ta-Noise
(Note 2)
82
dB
Distortion
(Note 2)
0.3
%
NOTES:
1. Resistor in series with pin 10 required for V - < -6.8V. Due to internal zener
diode between pin 10 and ground, negative supply voitages between -43V and
-9V should be avoided.
2250
2450
2650
-1
+1
nA
-0.5
+0.5
dB
-30
dB
2. These specifications are referred to a 1.8VP-P signal into pin 8.
Specifications subject to change; consult latest data sheet.
148
2190, Rev. A1
SSM·2D47 VOLTAGEoCONTROLLED FILTER WITH TRIPLE yeAs
OUTPUTVCAs
FUNCTIONAL DIAGRAM
4000
Q
Fe
Three output VCAs are provided: channel and left·right stereo.
These are connected in parallel ratherthan series for less noise
and distortion build up. The inputs of the VCAs are internally
connected to the filter output. Pin 15 has been provided for a
capacitor which effectively acts as a DC block between the filter
and the VCAs. This prevents any filter offset voltage from degrading the control rejection performance of the VCAs. The gain
control (pin 12) controls the gain of all three VCAs. The control
sensitivity is about -1 OdB/30mV at pin 12. A control attenuator
is usually connected between pin 12 and the gain control
source.
FRE•
11
The pan control (pin 1) determines the relative amount of signal
that will appear in the left-right stereo outputs. The sum of the
signals in the two outputs is constant. The control sensitivity
rapidly approaches-l OdB/30mV away from center in the output
being attenuated. Again, an external control attenuator is usually provided from the pan control voltage source to the pan pin.
It may be desirable to remove the signal from the stereo mix
when the channel output is in use. This can be accomplished
with a switch on the channel jack con necting the positive supply
to a resistor which goes to the control attenuator at the pan pin.
The resistor's value should be chosen to give about + 1.5V at pin
1 when it is connected to the supply.
2000
PAN
0-'----1
The VCAs all have current outputs. This allows signal summing
by simply connecting the apprDpriate outputs of multiple SSM2047s to a single op amp current-to-voltage converter. The voltage compliance of the outputs is ±330mV. However, the
output(s) can also be connected to a small resistor to ground.
GENERAL INFORMATION
The SSM-2047 will operate with positive supply voltage in the
range from +9 to +18 volts. Due to the internal zener diode
connected between ground and pin 10, a resistor in series with
pin 10 to the negative supply must be included for negative
supplies below -6.8 volts. The resistor's value is determined by
the equation:
FILTER SECTION
The filter section of the SSM·2047 is similar in design and per·
formance to that of the SSM·2045. The primary dHference is a
reduced output voltage swing since it is not brought out directly.
This dictates different C2 and C4 than those used with the SSM2045 (see Typical Connection Diagram).
The SSM-2047 has a 7.2kn input attenuator resistor internal to
the device. The input (pin "8) referred clip point is approximately
2.7V p. The maximum input signal should be kept a few dB
belO\~i this value. The frequency control (pin 9) should be terminated to ground through a resistorof 1kOor less. Aseries resistor from pin 9 to a control voltage source and the ground connected resistor form an input attenuator that. determines the
overall frequency control scale factor. The scale factor is ap·
proximately -19.3mV/octave at pin 9. This will have a temperature driftof-3300ppml"C unless a tempsistorwith opposite drift
is used as the ground connected resistor (see note below).
The Q control has been designed to give only a 6dB in-band
signal loss at the oscillation point. This slight loss will keep
headroom nearly constant as Q is increased. The Q control input
(pin 2) is the emitter of a grounded base PNP transistor through
a 4000 short-circuit protection resistor. The onset of sine wave
oscillation will occur with about 75!1A sourced into pin 2. An
external series resistor is usually connected from pin 2 to the Q
control voltage source.
NOTE: RCD Component. LP1/4. Manche.ter. Nfl USA TEL: (603)
Rs = I 6.8 + VEE 1/9.8mA for VEE < -6.8V
A -5 volt supply can be connected directly in pin 10. Negative
supply voltages less than -6 volts or greater than -9 volts are
recommended.
The SSM-2047 requires two external resistors to establish the
filter center frequency and the maximum gain of the output
. VCAs. The voltage at pin II, the filter reference current pin, is
2.5 volts above ground. The resistor between this pin and the
negative supply or pin 10 should establish a 10!1A current
source. Pin 17's voltage is a few hundred millivolts below
ground. The resistor between this pin and the negative supply or
pin 10 will produce a current that determines the maximum gain
of the ouput VCAs. This current should be no more than 300!1A
for optimum performance. If the negative supply is lower than
the voltage on pin 10, connecting the resistors to V- will establish currents with greater accuracy. However, the supply should
be well regulated and free of noise. If this is not the case, the
resistors and the bypass capacitor should be connected to pin
10.
66~054
149
2190, Rev. A1
SSM-2047 VOLTAGE-CONTROLLED FILTER WITH TRIPLE VCAs
BLOCK DIAGRAM: a-Channel System Using a-Bit CMOS DAC, a-Channel Demultiplexers, VCFsNCAs.
TYPICAL CONNECTION OF THE SSM-2047
and filter center frequency respectively. Note that the negative
supply should be well regulated and free of noise orthe resistor
values should be scaled and the connections moved to pin 10
w"h the bypass capacitor.
The figure below shows a typical connection of the SSM-2047
powered from ±15V supplies. The 43kn and 1.5Mn resistors
establish the 300ILA and 1OILA current references for VCA gain
SSM-2407 TYPICAL CONNECTION
v.
"kll
PANo-.......W -......~
II
.000n
17
Q
(+15Y)
la-·""
47pF
43kll
201cn
1300pF
3
IS
4
SSM·2047
6800pF
,:>~
47)-~---o~~
O.01p.F
.t7pF
"
SIGNALIN
••kll
-o~~T
1.SMn
"::"
lkll
10 8200
Fe
"::"
lkll
O.'~F~
CHANNEL
OUT
V- (-I5V)
56kll
"::"
GAlN
150
2/90, Rev. A 1
SSM-2100
MONOLITHIC
LOG I ANTILOG AMPLIFIER
]lrecision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
The SSM-21 00 is a monolithic low-cost DC logarithmic amplifier
capable of implementing log/antilog as well as log ratio transfer
functions. This device offers a dynamic range of 6 decades of
current and 3 decades of voltage. The circuit contains two precision operational amplifiers, a high conformance transistor pair
and a precision bandgap voltage reference. An on-board substrate temperature regulator stabilizes both the scale factor and
reference drift. A negative voltage reference is also available to
facilitate external trimming.
Performs Log, Antilog, and Log Ratio Functions
50pA Input Bias Current (Trimmed)
4mV Input Offset Voltage
On·Board Reference
Temperature Stabilized
25ppm/oC Reference Drift
30ppmrC Scale Factor Drift
0.25% Conformance
3·Decade Dynamic Range (Voltage Mode)
6·Decade Dynamic Range (Current Mode)
Low Cost
BLOCK DIAGRAM
APPLICATIONS
•
•
•
•
•
•
•
v+
Photodiode Preamplifier
Absorption Measurement
Low Sweep Generators
High Resolution Data Acquisition
Analog Computation Circuits
Analog Compression/Expansion
Linear·to·dB Conversion
ORDERING INFORMATION
PACKAGE
PLASTIC
16-PIN
.-_--+".::..3-0 COUP 3
>-_-1-",,-4-0 OUTPUT
s:~~e~ 0--"2'+--+-_._--;
.---p.o...o COMP 2
>-_+,,--0 COMP'
OPERATING
TEMPERATURE
RANGE
-10°C to +SsoC
SSM2l00P
.:1-----+-+"...6 -0 FEEOBACK
GND2
REF OUT
(+"V)
REFCOMP
,.
PIN CONNECTIONS
TEMPADJ
GNDl
GNDl
1
TEMPADJ
2
GND3
16·PIN PLASTIC DIP
(P·Suffix)
REF IN
1
11
v-
GND3
10 REF OUT
N.C.
REFCOMP
The SSM·21 00 la mask work protected under the Semiconductor Chip Protection Act of 1983.
151
2190, Rev _A1
SSM-2100 MONOLITHIC LOG/ANTILOG AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
PACKAGE TYPE
UNITS
Supply Voltage ..................................................... 36V or ±18V
16-Pln Plastic DIP (P)
Junction Temperature .................................................. + 150·C
82
'C/W
39
NOTE:
I. e lA is specified for worst case mounting conditions. I.e .• e lA Is specifled for
device In socket for P-DIP package.
Operating Temperature Range .....•.••.•.•.•.••••... -10·C to +55·C
Storage Temperature Range ..••••.•.•••. , .•.•.••••• -65·C to + 150·C
Maximum Current into Any Pin •..••.••.....•.••.•.•.•.•••.•.•.•.•••.• 10mA
Lead Temperature Range (Soldering, 60 sec) ..••.•••••.• +300·C
ELECTRICAL CHARACTERISTICS at V S = ±15V, RLIMIT
PARAMETER
= 1.6kQ,
+5·C
SYMBOL
CONDITIONS
Conformity Error
(Note I)
VERROR
I, N =1OOnA to 100jIA
liN =10nAto ImA
(Input Offset Trimmed)
Scale Faclor
VSCALE
Measured at Pin 16
Scale Factor
Temperature Drift
TCVSCALE
Inpul Offset Voltage
(Note 2)
V,OS
Input Bias Current
(Notes I. 2)
18
Output Offset Voltage
Voos
liN =IREF =ImA
Scale Factor Set at IV/Decade
Power Supply
Aejection Aatio
(Note 3)
PSAA
+12V s V+ s +17V
-12V,.V-,.-17V
Scale Factor Set at IV/Decade
Output Voltage Swing
VOUT
AL ,.IOke
AL ,.2ke
Aeference Output Voltage
+VREF
No Load
Aeference Output Voltage
Temperature Coefficient
TCVREF
Aeference Output Current
10UTREF
Aeference Load Aegulation
Aeference Supply Aejection
Voltage at Pin 7
s: TA s: +50·C,
IAEF
MIN
65
+ISY
Negative Supply Current
SSM-2100
TYP
MAX
UNITS
70
%
75
mV/Decade
ppm/'C
30
4
8
mV
500
2000
pA
30
70
mV
500
250
-I
-0.2
4.7
5.0
"VN
+10
+10
V
5.2
V
25
ppmrC
0.015
%/mA
mA
5
%N
0.04
+12V s V+ s +17V
6
+VREF
Positive Supply Current
unless otherwise noted.
0.25
0.4
AL,.lke
PSAR REF
= 1 rnA,
TA =+25'C
TA =+50'C
TA =+5'C
Heater Disabled
7
8
35
20
50
5
V
mA
-ISY
5
6.25
mA
Heater Start-up Current
IHTR
80
120
mA
Aegulated Chip
Temperature
TREG
60
75
'C
53
Specifications subject to change; consult latest data sheet.
NOTES:
I. Guaranteed by design but not directly measured.
2. Applies to both signal and reference inputs.
3. Aeferred to output in log mode. or to input In antilog mode.
4. Specifications apply after a 50 second warmup period.
152
2190, Rev.A1
SSM-2100 MONOUTHIC LOG/ANTILOG AMPUFIER
GENERAL PRINCIPLE OF OPERATION
The SSM-2100 utilizes the predictable logarithmic relationship
between the collector currents and differential input voltage of
an NPN transistor pair, given by:
NOTE: The output amplifier can only swing to approximately
1.5Vbelowground and sinks about300jlA. Forthis reason, they
are used only with positive output voltages. For bipolar amplifier
output, see Figure 7 in the Log Ratio section.
delta VIN =kTlq In b"c,
where: k = Boltzmann's constant (1.38 x 10-23) J/OK)
q = charge of an electron (1.6 x 10-23 C)
V'6 = kT/q In (IREP'IIN)
converting to base 10:
Equation (1) can be rewritten:
(1)
(3)
V'6 = 2.303 kT/q LOG,o (IREP'IIN)
Figure 1 shows the feedback which produces the output scale
factor:
T =absolute temperature (OK)
Deviation in the absolute temperature term is eliminated with the
SSM-2100 design since the chip temperature is regulated at
+60°C (333°K).
»
PRINCIPLE OF LOG OPERATION
The logging function is realized by placing the antilog element
(transistor pair) in the feedback loop of the output converter
amplifier (A,) as shown in the block diagram. As shown in Figure
1, the loop is closed and the conversion is scaled with feedback
resistors R, and R2from pin 16to pin 14. The high-gain opamps
(A, and A2) have negligible input bias current. These force the
collector currents of the high conformance transistor pair to be
equal to the input current (pin 12) and the reference current
(pin 6).
lIN. Ie,
(5)
(6)
VOUT = K LOG,o (IREF"IIN)
For voltage-mode operation:
(7)
VOUT = K LOG,o (VREF"VIN x RIJRREF)
(8)
Since both op amp inputs rest at virtual ground, the reference
and input currents can easily be generated by applied voltages
through external resistors without generating excessive errors.
For the best results, the input and reference currents should be
kept below 1mAo
A 5V reference has been included on chip for applications requiring a true log function (rather than a log ratio function).
COIIP3
"Ol/TPl/T
"l
VOUT = 2.303 kT/q (R, + R2)/R, LOG,o (IREP'IIN)
Letting K = 2.303 kT/q (R, + R2)/R2
INPUTS
As with all log amplifiers, the SSM-21 00 has a limited dynamic
range of 3 decades for voltage inputs. This is partially due to
input offset voltage (trimmable) and various second order effects.
13
INPl/T
(4)
For current-mode operation:
v.
12
VOUT =V'6 (Ri(R, + R2
Substituting into equation 3 yields:
or K = 0.066 (R, + R2)/R 2 (usually set to 1V/decade with R2 =
470n)
Referring to equation (1), the input current becomes Ic, and the
reference current IC2' while delta VIN is VBASE 02 or V'6' since
the base of 0, is ground. Here, the output amplifier A, forces the
base of 02 to be at the appropriate voltage governed by equation (1) and the collector currents of 0, and 02' With the reference current set at 1mA, the input current operates at less than
orequalto 1mA.lnthecaseofthe inverting log amp, asthe input
current decreases, the VBE of 0, decreases which increases
V'6 or VOUT since the VBE of 02 is fixed.
SIGNAL
(2)
For the widest dynamic range, current-mode operation is recommended. The device can handle 5 decades of current input
untrimmed and at least 6 decades when trimmed. Similarly,
when operating in the log ratio mode, the device can handle 10
decades and 12 decades, respectively.
VOUT
15
COIIP2
In order to ensure unconditional stability when operating with
true current inputs, it is important to shunt the signal input to
ground with a 1Okn resistor and a 1OnF capacitor in series.
COMP1
OND 2?,4-;;~~:';'1----f-¥.~=·ED"'B"'N;""K"""
,,,
,
R,
*
FIGURE 1: Basic Principle of Operation
153
2190, Rev. A1
SSM·2100 MONOUTHIC LOG/ANTILOG AMPUFIER
NEGATIVE POWER SUPPLY CONSIDERATIONS
Because the negative power suppply is regulated at -7V, it is
necessary to add a current limiting resistor (R UM1T ) in series with
pin 7. When using -15V for V-, a value of 1.6kn is recommended lor RUMIT" This will keep the voltage at pin 7 very stable
and useful for external trimming. Note thai the negative power
supply is internally regulated and needs no decoupling.
POSITIVE POWER SUPPLY CONSIDERATIONS
Because of the high gain of the temperature regulator circuit,
generous positive supply decoupling should be used. The 0.21J.F
decoupling capacitor shown on the application circuits should
be of ceramic type and mounted as close to pins 1 and 4 as
possible. It should also be noted than pin 1 carries all the heater
current and care should be taken when laying out ground lines
to prevent this from causing errors.
TEMPERATURE CONTROL
The internal chip temperature is regulated at about 60 0 e if the
temperature adjustment (pin 12) is not used. This on-board
substrate temperature regulator stabilizes the scale factor and
reduces drift of the reference.
FIGURE 2a: Inverting Log Amp with Current Input
The regulated chip temperature can be increased or decreased
by the use of pin 2. To decrease the temperature by nee, connect a resistor of the value 3.5n Mn between pin 2 and 10. To
increase the temperature by nee, connect a resistorofthe value
6/n Mn between pins 2 and 7.
In some applications such as those requiring low power, the
temperature regulator can be disabled entirely. This is accomplished by connecting a 100kn resistor between pins 2 and 4
(V+). In this case, the reference drift is about 70ppm/oe. The
scale factor drift can be compensated by using a temperature
compensating resistor' for R2 .
APPLICATIONS
The SSM-21 00 can be connected for voltage or current logging
functions. Figures 2a and 2b show the transfer characteristics of
the inverting log amplifier for current and voltage mode operation .
FIGURE 2b: Inverting Log Amp with Voltage Input
• RCD Compononts, Inc. Part Numbor LP1/4, 3301 Bodford Stroot, Manchostor, NH U.S.A., (603) 669-0054, Telox 943512
154
2190, Rev. A1
SSM·2100 MONOLITHIC LOG/ANTILOG AMPLIFIER
INVERTING LOG AMPLIFIER
Figure 3 shows the SSM·2100 configured in the inverting log
mode. Setting liN IREF with V IN 10V, the output will be zero
and increase by 1V/decade as liN is decreased. Whereas VIN
can be varied proportionally by varying RIN , a 10V input opti·
mizes the dynamic range with :t15V supplies.
=
To vary the scale factor, it is best to change R, . To alter the
output offset at a given input voltage, adjust RREF' Phase com·
pensation for the circuit is provided by C C2 and C3 . This
"
scheme yields 30kHz small·signal bandwidth at 1mA input cur·
rent, 8kHz at 1!!A and approximately 1.6kHz at 100nA.
=
+1SV
0.... '
~+
:1I_
RIN
V,. o-_---...'IVO""V'--_ _
COMP3 13
~__~~'I~-==F----~
'J.£2+r""J~""iiNw...;~L_
.J:. . '"">-_.>--_ _ _!!!I0.jl!!RE;E.'.QJOUoI!1T_--/-:::::-i
AEFCOMP (+sV)1
TEMP DJ
:
1nFli
f o. !,
1 GND'
RE:l~i~CE
REGULATOR
I TEMPERATURE
AND BIAS CIRCUIT
1PF
~
I
R,
'700
GND3
v7
RUUIT
1.6kD
-15V
FIGURE 3: Inverting Logarithmic Amplifier
155
2190, Rev. A1
SSM-2100 MONOLITHIC LOG/ANTILOG AMPLIFIER
NONINVERTING LOG AMPLIFIER
Interchanging the signal and reference inputs yields a noninverting log amplifier as shown in Figure 4. In this configuration,
the output crosses zero when the input is five decades below the
full-scale value. This can be adjusted by varying R3 .
R, and R2 can cause a slight inaccuracy because they add to
the base resistance of 0, and 02. This can be minimized by
keeping R, and R2 as small as possible. It is recommended that
R2 = 470Q.
The small-signal bandwidth of this circuit is 5kHz with inputs
currents from 1!lA to 1mA. Over the full 5-decade input current
range, the bandwidth is better than 2kHz.
+15V
0.2.F
r
caMP 3 13
>---",U",Tp""U""Tt",,,"4--~---t-O~f~IDECADE
SIGNAL
r---+------
C,
lnF
R,
COMP1
6.6SkO
C,
J500PF
R,
10Ma
R,
470a
R,
"0
v7
Ruurr
1.6kO
-15V
FIGURE 4: Noninverting Logarithmic Amplifier
156
2190, Rev_A1
SSM·2100 MONOLITHIC LOG/ANTILOG AMPLIFIER
ANTILOG AMPLIFIER
Converting to basel 0 and letting K = 2.303 kT/q (R, + R2)/R 2 or
0.066(R, + R2)/R 2 (assuming T = +60°C or 333°K)
Figure 5 shows the configuration for the antilog amplifier. The
input range for this circuit is zero to 1OV which can be adjusted
by R,. The output scale factor is 1V/decade which can varied by
adjusting ROUT'
the final antilog transfer function becomes:
V OUT = IREF RouJl OIVIN R2/.066 (A'
The transfer function is also derived from equation (1). In the
antilog configuration, the current Ic, becomes lOUT and V BASE
02 or V'6 is V'N(R/(R, + R2)). Equation (2) now becomes:
V 1N (R 2/(R, + R2)) = kT/q In(IREF/loUT)
+
R211
or
V OUT = IREF RouJl0IVIN/KI
To set K = lV/decade, R/(R, + R2) = 0.066
(9)
If R2 = 470Q, R, = 6.65kQ
or
The bandwidth of the antilog amplifier circuit is approximately
500kHz.
IREF/loUT = exp[R/(R, + R2) q/kT VIN)
or
IREF ROUT = V OUT exp[R 2/(R, + R2) q/kT VIN)
+15V
ROUT
10ke
0.2,F
±
4
v.
*f~
-------------
OUTPUT 14
~~~~:L
12
COMP 3 13
- - -- - -
COMP2
+
REFERENCE
INPUT
6
RREF
"0
5 I GND
10
Q,
Q~
1 DECADENOLT
~~~nF
TEMPADJ
+"'1TO. l11:
GNDl
11lF
GND3
C,
J'00
pF
CaMP 1 3
R,
6.65kO
FEEDBACK 16
V,N
1
REF OUT
9 REF COMP (+5V)
r
~
r
J.
A,
-=-
Your
R,
4700
I RE~J~i~CE
I TEMPERATURE
REGULATOR I
AND BIAS CIRCUIT
(~
J'l
V-
7
I~'
-=-
RUglT
1.6kC
-15V
FIGURE 5: Antilogarithmic Amplifier
157
2190, Rev. A1
SSM-2100 MONOLITHIC LOG/ANTILOG AMPLIFIER
+15V
0.2.F
RIN1
ceMP 3 13
>-__
T 1-",,-4----~--+-o ~f~JDECADE
-,O",UC!.!TP",U.c.
SIGNAL
______~12LpIN~P~T~__r-~~____~
tOke
v'~VV
I
C,
,--+------
I'O
C,
2.7nF
RIN2
10ka
v,~VV-.
COMP 1 3
REFERENCE
JI F
.,
____~'~'N~P~UT~__r--1__~--~
6.6SkO
FE DBA K 16
.,
470Q
v7
RUMIT
1.6ka
-15V
FIGURE 6: Log Ratio Amplifier, V OUT = K LOG (V2N,), K.= lV/Decade with Values Shown
LOG RATIO AMPLIFIER
The output of the log ratio amplifier is proportional to the ratio of
its two input signals. The SSM-2l 00 is very well suited to this
application because both the signal and reference inputs operate at true virtual ground. This eliminates the need for an external true current source as required by other types of log amplifiers.
+15V
2501l
,
'6
2
15
,.
3
•
The log ratio amplifier shown in Figure 6 has a dynamic range of
105 to 10- 1 if the output buffer of Figure 7 is not used. This is
because the oulput amplifier (A, ) can swing to a minimum of
about 1.5V below ground and can only sink about 300ilA maximum. Thus, the input current should not be more than one decade below the reference current.
5
SSM-2100
3.3ka·
5~
'1)1
. 1/2N3904
'3
11
7
'0
VOUT (:t5V MAX)
3.3kO
1skO
9
-15V
For full four-quadrant operation, however, refer to the output
buffer of Figure 7. The addition of this circuit will provide a ±5V
output for reference/signal ratios from 105 to 10- 5 for a full 10decade range.
J
12
6
•
1
-=
* ADJUST FOR DIFFERENT SCALE fACTOR
FIGURE 7: Modification of Figure 6 for Four-Quadrant Operation
158
2190, Rev_A1
SSM-2100 MONOLITHIC LOG/ANTILOG AMPLIFIER
TRIMMING THE SSM-2100
Figure 8 shows the general trimming technique for the log and
log ratio applications shown in Figures 3, 4 and 6. The trim
schemes for scale factor (R , ), input offset (Rx' R ), and output
offset (RREF) factor are shown. For log ratio ap~lications, the
input offset trim can be duplicated for the reference input.
LOG AMPLIFIER TRIM PROCEDURE
Log amp trim for K =1:
1. Apply full-scale input voltage or current and adjust output
offset for the proper output.
2. Apply an input signal one decade down from full-scale and
adjust the scale factor for the desired output.
The scale factor trim scheme is identical in all applications.
Simply replace R, with a 6.2kQ resistor and 1kQ potentiometer.
3. Finally, with the minimum input signal applied, adjust the
Input offset trimming removes errors from input bias current as
well as amplifier offset. For optimum trim integrity, the use of the
positive and negative reference voltages yields high rejection to
variations in power supply voltages.
ANTILOG AMPLIFIER TRIM PROCEDURE
Antilog trimming for K =1:
input offset trim for the correct minimum scale output voltage
or current.
1. Set full-scale by grounding VI N and adjusting the output offset trim until V OUT is 10V.
Output offset errors are essentially due to the mismatch between the base-emitter voltages of 0, and 02' The output offset
adjustment (RREF) scheme shown applies to the inverting log
amp and the antilog amplifier. Output offset is adjusted in the
noninverting log amplifier by changing Rs in Figure 4. To adjust
out the equivalent error in the log ratio amplifier, replace either
of the 1OkQ input resistors with a 9kQ resistor and 2kQ potentiometer.
2. Apply 1V to VIN and adjust the scale factor for lV output.
3. Setthe VIN to the maximum value to be used and adjust input
offset trim for the minimum desired output. Using K = 1 , adjust for V OUT of 0.1 V with VIN at 2V.
Unlike an operational amplifier, a log amp can not be trimmed
with VI N = 0 since the log of zero would theoretically produce an
infinite output voltage.
I.
v,.
"IN
12
+-&
I
SIGNAL
INPUT
COMP 3 13
OUTPUT 14
A,
lka
",
+
R'f
6
3.9kO
INPUT
OUTPUT
OFFSET
TRIM
V,ka'
I.
100kQ
~
a
COMP 1 3
A,
=
REFERENCE
INPUT
5 rm02
OFFSET
TRIM
~ TRIM
~X~~5R
ceMP 2 15
L
6.2kO
a
FEEDBACK 16
~
REF OUT
REF COMP (+5V)
2
TEMP ADJ
1
GNO 1
11
GND 3
4700
I RE~~~iJCE
TEMPERATURE REGULATOR
AND BIAS CIRCUIT
I
r;,
)'1
v7
RLIMIT
=
R,.
R,
lkQ
470kQ
Ry
,.kQ
4.7MQ
00
,.0kQ
10MQ
6.8kQ
00'
20MQ
680Q
*Current Input
-15V
FIGURE 8: Trimming the SSM-2100
159
2190, Rev. A1
SSM-2300
8-CHANNEL MULTIPLEXED
SAMPLE-AND-HOLD
Precision Monolithics Inc.
FEATURES
PIN CONNECTIONS
• On-Chip 1:8 Demultiplexer, 8 Sample-and-Hold Capacitors
and 8 Output Buffers
• Saves Space, Reduces System Cost
• Output Buffers Stable for CL ,,; 500pF
• Output Swing Includes Negative Supply
• TTL and CMOS Compatible Logic Inputs
• 5 to 18 Volts Total Supply Operation
• Low Cost
15 CHAN 2 OUT
16-PIN
PLASTIC DIP
(P-Suffix)
11 ACONTAOL
10 BCONTROL
DeCONTROL
APP LlCATIONS
• Automatic Test Equipment
• Process Control and Monitoring Systems
• Audio and Video Systems
FUNCTIONAL DIAGRAM
ORDERING INFORMATION
PACKAGE
IN
PLASTIC
16-PIN
OPERATING
TEMPERATURE
RANGE
SSM2300P
-25'C to +75'C
c
A
INH
I-----':"'OONO
1------''''-0 v.
GENERAL DESCRIPTION
The SSM-2300 is an eight-channel CMOS multiplexed sampleand-hold device designed for voltage level distribution in JlP
controlled systems. On-chip functions include an a-channel
demultiplexer, 8 sample-and-hold capacitors and a output buffers. This function saves valuable board space and reduces
system cost where multiple voltage levels are required.
TG
Ta
The SSM-2300 can operate from single or dual supplies with
both TTL and CMOS logic compatibility. Useful for adjusting
amplifier offsets or VCA gains, one or more SSM-2300s can be
used with a single DAC to provide multiple set points within a
system. Applications are in ATE, audio and video, process control and monitoring systems.
Ta
Ta
For improved performance and system upgrade, request the
PMI SMP-oa data sheet.
Ta
TG
Protected under U.S. Patent #4,739,281. The SSM-2300 has been granted mask work protection under the Semiconductor Chip Protection Act of 1983.
160
2/90, Rev_B
SSM·2300 a·CHANNEL MULTIPLEXED SAMPLE~AND·HOLD
ABSOLUTE MAXIMUM RATINGS
Total Supply Range ........................................................... 18V
Positive Supply (V+ - VGND) •••••••••••••••••••••••••••••••••••••••••••••• 18V
Negative Supply (V-- VGND ) •••••••••••••••••••••••••••••••••••••••••• -10V
Storage Temperature Range
P Package ..................................................... -65°C to + 150°C
Lead Temperature Range (Soldering, 60 sec) .............. 300°C
Junction Temperature .................................................... 150°C
Operating Temperature Range ....................... -25°C to +75°C
ELECTRICAL CHARACTERISTICS at V+
alA (Note 1)
PACKAGE TYPE
16-PinPlasticDIP(P)
82
alc
UNITS
39
'CfW
NOTE:
t. a'A is specified for worst case mounting conditions, i.e.,
d~vice in socket for P-DIP.
= +15V, V- = GND,
ajA is specified for
TA = +25°C, unless otherwise noted.
SSM·2300
MIN
TYP
MAX
UNITS
2
4
a
mA
5
18
V
(V-- VGNO)
-10
0
V
V INH
See Table 1
6
V INL
See Table 1
PARAMETER
SYMBOL
CONDITIONS
Supply Current
Is
Positive Supply Voltage
V+
(V+ - V GNO )
Negative Supply Voltage
V-
LOllic High (A; B. C, IN H)
Logic Low (A, B, C, INH)
V
0.8
Channel Select Time
tON
300
Channel Deselect Time
V
ns
tOFF
300
ns
Inhibit Recovery Time
tlNH
150
ns
Buffer Offset
Vos
0< VIN < +13V
8
50
mV
4
8
mV
Hold Step
V HS
0< VIN < +13V
Acquisition Time
tA
o --0 GND
11
·s
10
~---__1---
SW, GAINADJ
6
II
§
rE
FIGURE 1
172
~
::;
rE
~
rE
" ~,; ~
~
'"
~
'"
~ ~
•
10
Q
:e
rl' '" "'~ "'~ "'~
~
~
'"
~
12
11
[:;
~
","
~
~
'"
39.65dB
APPLICATION NOTE 114
The circuit design incorporates a gain switch with twelve (12)
calculated gain settings. The Jensen transformer, model JE11 OK-HPC used in this application has a voltage gain of 17.9dB.
For an output voltage of -10dBu, the microphone amplifier
circuit has an input sensitivity range of -6SdBu to -17.SdBu,
wilh a typical output headroom of 33dB. The preamplifier circuit
shown is gain adjustable from 9.6dB to 39.6dB in 2.SdB steps.
For applications where additional headroom is required, the
SSM-2016 should be used. The SSM-2016 can be powered
with up to ±36VDC rails and drive 600n loads. If ±24VDC rails are
used, headroom increases to 35.7dB (typically), while the EIN
remains at -127dB. As a consequence of the increased power
supply voltage, the SSM-2016 package power dissipation will
typically be 600mW with ±24VDC rails (no signal), and will rise
to 72SmW with worst case signal conditions into 600n load.
PMl's SSM-201S/2016 input circuit utilizes two identical low
noise bipolar transistors, with access to the emitters, that provide the gain adjustment. The output circuit topology is complementary bipolar producing 6V/I1s (201S) and 10V/1lS (2016)
slew rate into a 2kn unbalanced load.
For ±36VDC power rails, although the headroom increases to
39.3dB, the SSM-2016 will dissipate 1.2 watts with no signal
applied, and 1.S watts worst case signal conditions into 600n
load. Therefore IC package cooling should be taken into consideration. Please see the SSM-2016 data sheet for IC pin-out
connections and recommended compensation capacitor values. All other circuit component values shown here apply.
RG (R17 through R2B ) sets the amplifier gain using the equation:
VG
= 3.S + (20~03)
The transformer-coupled microphone preamplifier circuit described above demonstrates robust, real-world usage refinements, along with most operational features required byequipment designers todeliverthe highest performance. It will handle
the most hostile microphone environments without distress to
either the circuit or the user.
for R14' and R15 = 10.0kn.
SW
GdB
*eIN(dB)
1
2
3
4
S
6
7
8
9
10
11
12
9.6
12.1
14.6
17.1
19.6
22.1
24.6
27.1
29.6
32.1
34.6
39.6
-37.S
-40.0
-42.S
-45.0
-47.S
-SO.O
-S2.S
-SS.O
-S7.S
-60.0
-62.S
-6S.0
RG
R17
R 18
R 19
R 20
R21
R22
R23
R24
R 25
R 26
R27
R2B
"Input attenuator set to the OdB position.
VALUE(n)
100k
37.4k
10.7k
S.49k
3.32k
2.1Sk
1.47k
1.05k
7S0
S49
402
21S
TABLE 1: Circuit Performance Specifications
Frequency Response
(20Hz to 20kHz, -60dBu, SOdB gain)
THO + Noise (20Hz to 20kHz, -60dBu, SOdb gain)
IMO (+23dBu, SMPTE 60Hz and 4kHz, 4:1)
= 20109[3.S +(20~03)]
0.045%
0.05%
-127dB
Input Impedance (20Hz to SkHz)
1S00n
Source Impedance
1S0n
CMR at 1kHz (common-mode rejection at 1kHz)
CMVR (common-mode voltage range)
Unspecified overall circuit gain can be calculated from the
equation:
Goa
±0.1SdB
±1S0VDC
Slew Rate (overall circuit)
6V/I1s
Gain Range (overall circuil)
+17.9
Output Voltage
SSM-2015 (±18VDC ' 2kQ load)
SSM-2016 (±24VDC ' 2kn load)
TYPICAL PERFORMANCE
Frequency response versus amplitude is ±0.2dB from 20 to
20,OOOHz, and THO + noise is better than 0.03% over gain and
frequency range described, with a typical EIN (Equivalent Input
Noise) of -127dBu. See Table 1 for detailed performance specifications.
17.SdB to 36dB
+23dBu or 11VRMS
+2S.7dBu or 1SVRMS
Output Headroom
(SSM-201S, 2kn load, -1 OdBu nominal)
173
120dB
33dB
AN-llS
BALANCED LOW NOISE MICROPHONE
PREAMPLIFIER DESIGN
Precision Monolithics Inc.
APPLICATION NOTE 115
The circuit design incorporates a gain switch with twelve (12)
calculated gain settings. For an output voltage of -1 OdBu, the
microphone amplifier circuit has an input sensitivity range of
-65dBu to -27.5dBu, and an output headroom of 33dB. The
overall circuit gain is adjustable from 27.5dB to 55dB in 2.5dB
steps.
The SSM-2015 differential amplifier is utilized in a transformerless, active-balanced input amplifier. The circuit shown in
Figure 1 provides a microphone preamplifier design with excellent performance and low noise. The design features a transformerless preamplifier circuit with true-balanced input, 15000
input loading, phantom microphone powering, and high common-mode rejection. The design shown also includes a twelve
position gain selector, or for fixed gain usage, component value
calculations.
SW
The design includes microphone input loading of 15000, but
the load resistor can be changed to accommodate other applications. Input loading is capacitive reactive at higher frequencies to attenuate unwanted RF and ultrasonic voltages at the
input terminals.
2
3
4
The phantom microphone powering circuit provides power for
condenser microphones that require 24 to 48 volts DC. The
zener diodes CR" CR 2, CR 3, and CR 4 protect the input transistors of the SSM-2015 when connecting the microphone to the
preamplifier circuit.
5
6
7
The common-mode voltage range is :1:5.5 volts. Its commonmode rejection is optimized for most applications by the truebalanced and differential input topology of the SSM-2015. A
balanced single pole low-pass filter at the input terminals
provides protection for the circuit from radio frequency interference and prevents slewing of the SSM-2015 amplifier. The
output circuit topology is complementary bipolar producing 6V/
~s slew rate, and able to drive a 2kO unbalanced load.
10
8
9
G dB
eIN(dB)
RG
27.5
30
32.5
35
37.5
40
42.5
45
47.5
-37.5
-40
-42.5
-45
-47.5
-50
-52.5
-55
-57.5
-60
-62.5
-65
R'5
R'6
R'7
R'B
50
52.5
55
11
12
R22
R23
~R'
-'N ,···p~iZ
1000pF TC2
1.87kQ
1\
LO
1\
r;;
-.to
=.11kC
5.6V
GND
R,
6.81ka
12
R,
C,
3311F sov
10ke
~
13
+
~ ~'
'2 ~
7
le,
114
1000
Vee 5
V,,/.
18V
-18V
R"
100n
RtO
M
~~.
~~
.
Rtf
3
SSM·2015
R
R.
1Qkn
G NO
J
~FP
1
9
~
-10dBu
C4
r,~I30PF
,-l!!
~3
CR,
86.6
63.4
47.5
35.7
R24
R25
R26
e OUT
C3
C,
HI
1.00k
715
511
374
280
205
154
115
R'9
R20
R2,
R,
10ka
3311~(50V
VALUE (0)
150kO
+
~~~~ ::~
100llF
25Voc
GND
v+ 48V
R"
100n
;::;: ~~~6
1
~
2
3
g ~ ~
'::'
r£
FIGURE 1
174
r£
r£
•
~ ~.
r£ r£
)
SW, GAIN ADJ
5
6
7
8
,.
9
~
~ ~ E
",g
'"
'"
'"
",N
~
is
:Ii
~
~
11
iil
1i
"'~
~l
55dB
APPLICATION NOTE 115
TABLE 1: Circuit Performance Specifications
SSM-2015 input circuitry utilizes two identical low noise bipolar
transistors, with access to the emitters that provide the gain
adjustment. RG (R 15 through R26 ) sets the amplifiers gain using
the equation:
Gain = 3.5 + (20
~03)
for Ag, & R13 = 10.0kn
Unspecified gain can be calculated from the equation:
GaindB = 20 log [3.5 +
(20~03)]
Frequency Response (20Hz to 20kHz)
±0.1dB
THO + Noise (@ +23dBu, 20Hz to 20kHz)
0.03%
IMO (@ +23dBu, SMPTE 60Hz & 4kHz, 4:1)
0.05%
EIN (Equivalent Input Noise, 150n source)
-124dB
CMR (Common-Mode Rejection at 1kHz)
105dB
Slew Rate
6V/j.1s
Output Voltage (2kn load)
+23dBu or 11 VRMS
Output Headroom (2kn load, -1 OdBu nominal)
The frequency response amplitude is ±0.1dB from 20 to
20,OOOHz, and THO + noise of better than 0.03% over the gain
range described with a typical EIN (Equivalent Input Noise) of
-124dBu.
The transformerless microphone preamplifier circuit described
above demonstrates real-world usage refinements and includes most operational features required by equipment designers.
175
33dB
AN-116
AGC AMPLIFIER DESIGN WITH ADJUSTABLE
ATTACK AND RELEASE CONTROL
Precision Monolithics Inc.
APPLICATION NOTE 116
The automatic gain control (AGC) amplifier described below
and shown in Figure' 1, features selectable gain reduction
compression ratios and time domain adjustable AGC attack
and release. This design employs the SSM-2013 VCA , SSM2110 precision level detector, two SSM-2134 low noise op
amps, and an OP-215 FET input dual op amp.
The six-position gain reduction selector that follows the input
amplifier provides adjustable compression that smoothes the
AGC action. Six GAIN REDUCTION slope ratios of2 to 22 can
be selected, thus reducing the irritating "hole producing and
pumping" character of most AGC circuits. The SSM-2013 VCA
is chosen for its predictable behavior and its high performance.
The dynamic range exceeds 94dB over the frequency range
20Hz to 20kHz. Over this frequency range, the amplifier
achieves typically less than 0.01 % THO + noise, and 0.03%
IMD.
The design features an inverting or noninverting input buffer
amplifier, a voltage controlled amplifier with adjustable attack
and recovery characteristics, driven by a true RMS level detector. Additionally, it provides selectable gain reduction compression, adjustable AGC output level, and maximum gain limit
controls. Signal-to-noise ratio is better than 100dB and the
RMS level detector allows the AGC amplifier to operate transparently throughout the audio spectrum. The gain recovery is
linear and time adjustable, and has maximum gain limiting
(gating) to preclude input source noise floor rise.
The SSM-2110's precision rectifier circuit produces the true
RMS output that comprises a level detector. It results in a
consistent and precise AGC action that retains good signal
dynamics while leveling the input signal. It responds to the audio
signal power density in a manner similar to human hearing.
Following the precision RMS rectifier is the VCA control voltage
conditioning circuits. Constructed around Us (OP-215), the
FET-input amplifier forms an integrator while the other amplifier
provides the VCA control port buffer. The AGC output level is set
by the rectified signal voltage compared to the reference voltage from the OUTPUT LEVEL control.
The input circuit includes a line level (-10dBu to OdBu) buffer
amplifier, that accepts inverting or noninverting inputs with
greater than 1OkQ loading impedance. The buffer also isolates
the input source from the compressor gain reduction ratio
selector, and limits step function slewing voltage.
100pF
-15V
GAIN
4.64kQ 22
REDUCTION
RATtO
10ka
DIST
NULL
10ke 10
O.1IlF
SSM·2134
NONINVERTING o--IIoIV--_~
15kQ
+15V
O.1~
":" 30pF
10"F ":'" 200 F
INPUT
+
35V
INVE~Nr:.~~ o--IIoIV--.--"-t
GND
..c-1
15kD 7
C>-.--N>fo-'
+15V
';O >-'kl '- --i
INPUT (LEFT) I
(+20dBU)
I
~....,.-_vHI
LO o-",'N'---4o----1l:!:-'
OUTPUT (LEFT)
I
(+20dBu)
HI~SM.20t5
NPUT (RIGHT)
LO
:
,>--1_-0 LO
-
+
I
.. ____
...!N~U!'&"pf!9~P.£)I~T
I
_____ I
------------------
: NO.2
HI o-",'N'--i
I
INPUT (LEFT)
>--'-<1 HI
LOo-:,-.tW'---4>-i
I
HI~SM'2015
NPUT (RIGHT)
:
,>--1--oLO
-
+
LO
I
.. ____
IN!!.U!'&''pF!9~P..QI~T
_____ t
------------------ I
•
I NO.3
I
INPUT (LEFT) I
LO
r-------------------,
STEREO AUDIO CROSSPOINT SELECTOR
I
I
1
HI~SSM.2015
INPUT (RIGHT)
:
+
I
.. ___ _ ....!N!U! &_C~O!!.SP.9I!!T _ _ _ _ _
LO
n
+5Vo--/
2
V
n
3
16
roooi
V
V
~
1
I
• CAN BE EXTENDED TO 16 INPUT & CROSSPOINT CKTS
.... - - - - - - - - - - - - - - - - -
Hlo-,-,J'N--4o-J
I
I NO. 16
I
INPUT (LEFT) I
LO 0-;-'VIII/'-.....,
I
HI
SM.2015
~
INPUT (RIGHT)
_
:
+
LO
I
Co
___
_
JNfU! &_C'!.0!iSPJ)I~T _ _ _ _ _
I
FIGURE 2: Switcher Functional Block Diagram
+1OdBu with a +20dBu input level and +14dBu peak, well within
ideal operating range. Good signal-to-noise is maintained, with
generous head-room available by electing to use ±18VDC
power supply voltages.
The routing switcher bus carries high level unbalanced audio,
but is driven with low impedance sources. With the output impedance of the SSM-2015 at virtually OQ and the SSM-2402
switch ON, resistance is typically 60Q. Bus-to-bus crosstalk is
exceptionally low. For example, assuming 14pF coupling between buses and 20kHz signal, the crosstalk (isolation) exceeds 80dB. The 14pF would be representative for the 16 X 1
stereo design shown. Shielding of the buses with a printed
circuit board ground plane and physically isolating the input and
output circuits will reduce the crosstalk even further. The "T"
configuration of the SSM-2402 switch virtually eliminates
crosstalk between the various input signal sources.
The output amplifier incorporates a buffer amplifier that provides 4dB of gain (nominally), with adjustable output level trim
control. The buffer also isolates the switching bus from the
balanced output amplifier circuit. The balanced output is designed to drive 600Q loads and utilizes two SSM-2134 IC
amplifiers. The differential design increases drive capability, yet
increases the heat dissipation surface area, and keeps IC
package temperature well within safe operating limits, even
when driving 600Q loads. The SSM-2134 is recommended due
to its low noise, wide frequency response, and output drive
current capabilities.
Overall performance ofthe 16 X 1 stereo switcher is noteworthy.
Input-to-output frequency response is flat to within 1dB over a
10Hz to 50kHz band. Total harmonic distortion plus noise is less
than 0.03%, from 20Hz to 20kHz. SMPTE intermodulation distortion is less than 0.02%. The use of ±18VDC power supplies
produces a +30dBm clip level, even when driving 600Q loads.
179
APPLICATION NOTE 121
TABLE 1: Circuit Performance Specifications
Max Input Level
+30dBu
Input Impedance, Unbalanced
100kIJ
Input Impedance, Balanced
200kIJ
Common·Mode Rejection (20Hz to 20kHz)
Common· Mode Voltage Limit
Max Output Level
>70dB
:l:98V Peak
+30dBu/dBm
Output Impedance
sm
Gain Control Range
:l:2dB
Output Voltage Slew Rate
SV/IAS
Frequency Response (:l:0.05dB)
20Hz to 20kHz
Frequency Response (:l:0.5dB)
10Hz to 50kHz
THO + Noise (20Hz to 20kHz, +8dBu)
0.005%
THO + Noise (20Hz to 20kHz, +24dBu)
0.03%
IMO (SMPTE SOHz & 4kHz, 4:1, +24dBu)
0.02%
Crosstalk (20Hz to 20kHz)
>80dB
SIN Ratio @ OdB Gain
135dB
180
AN-122
A BALANCED MUTE CIRCUIT
FOR AUDIO MIXING CONSOLES
Precision Monolithics Inc.
APPLICATION NOTE 122
The SSM-2402 Dual Audio Switch enhances the performance
and simplifies the design of balanced high level switching
(Mute) circuits used in audio mixing consoles. The use of the
SSM-2402 and SSM-2134 creates a design that has negligible
transient noise (as a result of signal switching), and exceptionally low signal distortion over a wide dynamic range. The balanced high level voltage switch then drives a virtual ground
summing bus through 10k!) resistors. Also included is a design
for a virtual ground summing amplifier.
The SSM-2402 is a monolithic dual audio switch that improves
electrical performance and eases printed circuit board layout
• design. The design reduces manufacturing cost when compared with discrete JFET designs of similar performance.
Electrical performance is measurably superior to CMOS switch
designs, and will be less prone to failure from electrical static
discharge.
",
37.4kO
lakO
(-6dBm NOM.)
"s
HI
10kO
1ka
V.
,.
HI
INPUT
(LEFT)
5pF
37.4kO 6
La
OUTPUT
(LEFT)
12
IN,
GND
",
37.4kO
BALANCED SIGNAL
lakO
SOURCE (LEFT)
10pF
SIDE2
see SSM
SpF
LO
PRODUCT GUIDE FOR CONNECTIONS
"s
1kO
10kQ
LEFT AUDIO BUS
(VIRTUAL GROUNDS)
ON
~
MUTE
is-ION)
CMOS OR TIL GATES
RIGHT AUDIO BUS
OV - MUTE (OFF)
MUTE (ONiOFF)
~
",
CONTROL
37.4kO
lakO
"s
SpF
HI
10kg
1kO
V.
37.4kQ 14
HI
U"
INPUT
(RIGHT)
SSM·24Q2
37.4kO 6
La
12
IN,
GND
BALANCED SIGNAL
SOURCE (RIGHT)
OUTPUT
(RIGHT)
,.
37.4kO
",
101(0
SIDE 2
see SSM PRODUCT GUIDe FOR CONNECTIONS
NOTES:
u1. U2 -SSM.2122
u3• 4, 5' 6. 1. 8, g. 10;" SSM·2134
u11 , 12 - SSM·2402
10pF
5pF
LO
"s
10kO
FIGURE 1: Audio Mixer Channel Mute (On/Off) Circuit, a Balanced Design with High Level Bus Switching
181
,.0
APPLICATION NOTE 122
The "T" switch configuration of the SSM-2402 provides excellent ON-OFF isolation. The design shown further improves the
ON-OFF isolation and left/right channel crosstalk figures by
maintaining the common-mode rejection ratio of a fully balanced design. The switch features a 7ms ramped turn-on and
4ms ramped turn-off, and guaranteed break-before-make
switching sequence for transient-free audio switching. The
system performance is improved for large audio consoles that
have multiple switches in the audio signal path.
TABLE 1: Circuit Performance Specifications
The switch control ports are easily interfaced to conventional
5V DC TTL or CMOS digital control circuits, further simplifying
the control circuit design. Furthermore, product reliability and
serviceability are improved by the simplified design. The application shown uses an elementary control circuit to functionally
illustrate control voltage requirements. Customized logic gate
cDntrol schemes or computer-controlled designs can easily be
implemented.
Frequency Response (±0.05dBu)
20Hz to 20kHz
Frequency Response (±0.5dBu)
10Hz to 50kHz
The application circuit design employs dual audio switches
driven by U3 , U4 , Us and Us inverting amplifiers. Their gain is
controlled by two dual voltage controlled amplifier (VCA) elements U 1 and U2 . A simplified signal path is shown for application clarity. For additional design information of the SSM-2122
dual VCA, consult the data sheet.
The design shown in Figure 1 is signal phase noninverting, and
incorporates a minimum number of components to minimize
noise. The input signal source should be balanced to maximize
separation and crosstalk isolation. PCB layout should also
utilize equal inductance in each side of the signal path wiring,
and include equal stray capacitance to ground and other signal
paths to obtain maximum performance. The SSM-2122 VCA
provides good gain tracking of the two audio channels, while
maintaining accuracy in the balanced signal path.
U" and U 12 are utilized as high level switches so that other
post-switching functions can be employed. A nominal drive
level of OdBu balanced (-6dBu unbalanced) is applied to the
switch. This level is arbitrary, but will satisfy most signal-tonoise and headroom compromises. The output of amplifiers U3 '
U4 ' Us' and Us are AC coupled prior to the switches to further
minimize the switching transients caused by active component
offset voltages. The balanced virtual ground mixing buses are
current driven by Rs of 10kQ. This value can affect overall
system performance, and should be modified to suit the size of
the mixing bus system. A greater number of input mixing
channels will warrant lower bus drive current. Although the
individual values of Rs and RF can be altered, their values must
be the same for a summing amplifier voltage gain of one (1).
Max Input Level
Input Impedence, Balanced
Common-Mode Rejection (20Hz to 20kHz)
Common-Mode Voltage Limit
Max Output Level
Output Voltage Slew Rate
+30dBu
75kQ
>70dB
±12V Peak
+30dBu
12V/fAs
THO + Noise (20Hz to 20kHz, +8dBu)
0.005%
THO + Noise (20Hz to 20kHz, +24dBu)
0.03%
IMO (SMPTE 60Hz & 4kHz, 4:1, +24dBu)
0.02%
ON/MUTE Isolation (20Hz to 20kHz)
>85dB
SIN Ratio @ OdB Gain
135dB
The active switches' ON resistances are typically 60Q and are
well matched. One should use 1% or better tolerance series
resistor Rs (1 OkQ) to minimize imbalance in the signal path. In
the OFF state, the "T" configuration of the switch virtually
eliminates leakage of the input source signal into the mixing
bus(es). Greater than 100dB mute isolation at 1kHz can be
obtained with prudent printed circuit board design since the
SSM-2402 control inputs and switch terminals are separated by
ground guards.
The use of ±18VDC power supplies allows a +30dBu (balanced)
clipping level. All integrated circuit components mentioned will
operate reliably at ±18VDC' and noise contribution will be
indiscernible, even in large mixing systems. The balanced input
to balanced output frequency response is typically greater than
10Hz to 50kHz, within 1dB. Total harmonic distortion plus noise
will measure less than 0.01%, from 20Hz to 20kHz at +30dBu,
while SMPTE intermodulation distortion less than 0.02% under
the same measurement conditions.
182
AN-123
A CONSTANT POWER "PAN" CONTROL
CIRCUIT FOR MICROPHONE AUDIO MIXING
Precision Monolithics Inc.
APPLICA nON NOTE 123
The SSM-2134 permits the design of a constant power, transient-free "PAN" control circuit suitable for installation in the
highest performance audio mixing consoles. The design incorporates unique and vital features. The PAN IN/OUT switch does
not introduce transient type noise or interruptions in the audio
when activated or deactivited, and when panning, an accurate
constant power output is maintained between the sum ofthe two
channels. The design allows "punching-in" and "punching-out"
of the PAN circuit while mixing down or on-the-air, without
transient clicks or holes in the mix.
in the center) forms an attenuator that has a 14dB loss. Rotating
the PAN control in either direction decreases the attenuation to
-11 dB for one channel and maximum attenuation for the other.
The design utilizes conventional parts, e.g., a single SPST
switch and a linear 10kQ potentiometer. U, (SSM-2134) is used
as a unity gain, inverting buffer with an input impedance of
37.4kQ. The input source could be a VCA element or audio
direct from the fader control. The values shown will allow a VCA,
for example, the SSM-2013, to be used with only minor additions. The overall application circuit is noninverting from input to
output.
Amplifier (U 2 & U3 ) gain is:
The 15kQ series input resistors Rs ' plus the inverting input
15kQ R, in parallel with 5kQ (1/2 of 1OkQ, with the PAN control
..L_.1-+_1_
RL - RI
5kQ'
RL
= 3.75kQ
Attenuation is calculated as:
dBLOSS
dBGAIN
= 2010g_R_L-
= 20 log
3.75kQ
RL + Rs3.75kQ + 15kQ
= 20 log RF = 20 log 75kQ = + 14dB
RI
15kQ
The frequency response is typically 10Hz to 50kHz, within
0.5dB. Total harmonic distortion plus noise will measure less
than 0.007% from 20Hz to 20kHz, and SMPTE intermodulation
distortion less than 0.01%. The amplifier clipping level is
+24dBu with :!:18Voc power supply rails. Headroom is nominally
30dB, and 27dB at full PAN for the operating channel.
l.:
10"F
6V
(RIQUT
HidBuNOM.}
(-80 dBu TO -3dBu)
100kg
lkll
FIGURE 1: Constant Power Type Control Circuit with Transient Free IN/OUT Switching
183
-14dB
APPLICATION NOTE 123
TABLE 1: Circuit Performance Specifications
PAN Range, L +-C .... R (L Out)
+3dB +-OdB .... -BOdB
PAN Range, R +-C .... L (R Out)
+3dB +-OdB .... -BOdB
Max Input Level
+24dBu
Input Impedance, Balanced
37.4kO
Max Output Level (> 6000 %lBVoc PS)
+24dBu
Headroom
Output Voltage Slew Rate
30dB
<6V/fl S
Frequency Response (%0.05dB)
20 Hz to 20kHz
Frequency Response (%0.5dB)
10Hz to 50kHz
THO + Noise (20Hz to 20kHz, +BdBu)
0.005%
THO + Noise (20Hz to 20kHz, +24dBu)
0.03%
IMO (SMPTE 60Hz & 4kHz, 4:1, +24dBu)
0.02%
SIN Ratio
130dB
184
AN-124
THREE HIGH ACCURACY RIANIEC
MC AND MM PHONO PREAMPLIFIERS
Precision Monolithics Inc.
I
APPLICATION NOTE 124
Although the digital compact disk is rapidly supplanting the vinyl
disk as the popular media method for professional and consumer audio entertainment, the electro-mechanical recording
and reproduction of audio signals has many more years of life.
The group of phono preamplifier application designs below will
make the future years with vinyl more productive and pleasant.
The applications employ solid engineering concepts, and dismiss "golden ear" discussions.
One design includes an input scheme for both moving coil (MC)
and moving magnet (MM) - or variable reluctance - transducers. All designs employ extremely low noise circuit topologies,
high accuracy active and passive RIAA (Recording Industries
Association of America) equalization with selectable old RIAA
or RIANIEC (International Electro-Technical Commission)
curves. The applications incorporate both consumer and balanced output circuit configurations.
BALANCED OUTPUT
GAIN TRIM
+44dB GAIN
10kQ
+4dB
r-----N>/'---..,...-/'---..,...-50dB
±10V Peak
Common-Mode Voltage Limit
+8dBu/dBm
+30dBu/dBm
70Q
O.OdBu to 10dBu/dBm
12.5
+14.1
Nominal Output Level, Unbalanced
-10dBu
16.0
+15.4
Max Output Level, Unbalanced
+24dBu
20.0
+16.3
+19.3
Output Impedance, Unbalanced
1,000Q
25.0
+16.8
+19.0
Output Voltage Slew Rate
>6V/ Ils
31.5
+17.0
+18.5
RIM Reproduction Characteristics
(20Hz to 20kHz)
40.0
+16.8
+17.8
50.0
+16.3
+16.9
63.0
+15.4
+15.8
80.0
+14.2
+14.5
100
+12.9
+13.1
125
+11.5
+11.6
160
+9.7
+9.8
200
+B.2
+B.2
250
+6.7
+6.7
315
+5.2
+5.2
400
+3.B
+3.B
500
+2.6
+2.6
630
+O.B
+O.B
1,000
0.0
0.0
1,250
-O.B
-0.7
1,600
-1.6
-1.6
2,000
-2.6
-2.6
2,500
-3.7
-3.7
3,150
-5.0
-5.0
4,000
-6.6
-6.6
5,000
-B.2
-B.2
6,300
-10.0
-10.0
-11.9
B,OOO
-11.9
10,000
-13.7
-13.7
12,500
-15.6
-15.6
16,000
-17.7
-17.7
20,000
-19.6
-19.6
RIANIEC Reproduction Characteristic
(2Hz to 20kHz)
Wideband Frequency Response (±1.0dB)
:!:0.25dB
±1.0dB
O.OHz to 70kHz
Signal-to-Noise Ratio (20Hz to 20kHz)
>90dB
THO + Noise
(20Hz to 20kHz +BdBu, Any Output)
0.01%
IMO (SMPTE 60Hz & 4kHz, 4:1)
0.02%
A PASSIVE MULTI-FILTER DESIGN
The Passive Split Multi-Filter RIANIEC Preamplifier design,
shown in Figure 2, is intended for moving magnet (MM) input
phono transducers. The design has an extremely low noise
circuit topology, high accuracy passive RIM/IEC equalization
filters, and both unbalanced consumer and balanced output
circuits. The input configuration utilizes the SSM-2015. It provides the lowest possible noise, adjustable resistive and capacitive input loading, and high accuracy passive RIM filtering
totally devoid of transient and frequency dependent gain errors.
Referring to Figure 2, the following two stages contain the RIMRIM/IEC passive equalization filters. All high pass and low
pass filters are passive. The signal is amplified by U2 and U3
SSM-2134 op amps. The overall gain of the circuit at 1,000Hz
is 38dB. RIAA equalization requires a gain of 19.3dB at 20Hz,
and attenuation of 19.6dB at 20,000Hz. Open-loop gain of U2
and U3 is greater than 1OOdB at 20Hz, and 60dB at 20,000Hz.
Closed-loop gain of U1 is 22.5dB, and U2 , U3 is 16.6dB,
ensuring an extensive gain margin for phase accuracy. Referto
Table 3 for complete circuit specifications.
188
APPLICATION NOTE 124
TABLE 3: Passive Multi-Filter Circuit Performance
Specifications
TABLE 4: Uncomplicated Passive Circuit Performance
Specifications
MM Nominal Input Level
MM Nominal Input Level
-48dBu (3.0mV)
MM Input Impedance, Resistive
69kQ or 47kQ
MM Input Impedance, Resistive
MM Input Impedance, Capacitive
50pF to 350pF
MM Input Impedance, Capacitive
Common-Mode Rejection (20Hz to 20kHz)
Common-Mode Voltage Limit
> 50 dB
:!:10V Peak
Max Output Level, Balanced
+30dBu/dBm
Nominal Output Level, Balanced
+8dBu/dBm
Output Impedance, Balanced
Gain Control Range, Balanced
-48dBu (3.0mV)
69kQ or 47kQ
50pF to 350pF
Common-Mode Rejection (20Hz to 20kHz)
Com mom-Mode Voltage Limit
Max Output Level, Balanced
+30dBu/dBm
Nominal Output Level, Balanced
+8dBu/dBm
Output Impedance, Balanced
O.OdBu to 10dBu/dBm',
Gain Control Range, Balanced
> 50dB
:!:10V Peak
70Q
O.OdBu to 10dBu/dBm
Nominal Output Level, Unbalanced
-1 OdB~
Nominal Output Level, Unbalanced
-10dBu
Max Output Level, Unbalanced
+2~dBm
Max Output Level, Unbalanced
+24dBu
Output Impedance, Unbalanced
1,000Q
Output Impedance, Unbalanced
1,000Q
Output Voltage Slew Rate
>6V/fts
Output Voltage Slew Rate
>6V/fts
RIAA Reproduction Characteristic
(20Hz to 20kHz)
:!:0.5dB
RIAA Reproduction Characteristic
(20Hz to 20kHz)
RIAAlIEC Reproduction Characteristic
(2Hz to 20kHz)
Wideband Frequency Response (:!:1.0dB)
:!:0.25dB
:!:0.5dB
O.OHz to 70kHz
RIAAlIEC Reproduction Characteristic
(2Hz to 20kHz)
Wideband Frequency Response (:!:1.0dB)
:!:1.0dB
O.OHz to 70kHz
>90dB
Signal-to-Noise Ratio (20Hz to 20kHz)
>90dB
THO + Noise
(20Hz to 20kHz +8dBu, Any Output)
0.01 %
THO + Noise
(20Hz to 20kHz, +8dBu, Any Output)
0.01%
IMO (SMPTE 60Hz & 4kHz, 4:1)
0.02%
IMO (SMPTE 60Hz & 4kHz, 4:1)
0.02%
Signal-to-Noise Ratio (20Hz to 20kHz)
AN ECONOMICAL APPROACH
An Uncomplicated Passive RIAAlIEC Preamplifier is shown in
Figure 3. It is a low cost, practical design for a passively
equalized RIAAlIEC phono preamplifier. The design shown is
for moving magnet (MM) input. It also is an extremely low noise
input circuit design, and includes both unbalanced consumer
and balanced output circuit configurations. The input circuit also
utilizes the SSM-2015, and provides adjustable resistive and
capacitive input loading. Wide bandwidth stages minimize inband phase shift, and provide exceptional phase and frequency
response accuracy. Table 4 details circuit performance data.
SUMMARY
For a phono transducer cartridge to deliver the performance as
intended, it should be loaded with proper resistance and capacitance. The MM input circuits have adjustable transducer loading. Most transducers currently available will be accommodated
with resistive loading of 69kQ or 47kQ, and capacitive loading
of a few pF (input wiring dependent) to 350pF, in 50pF steps.
If greater input common-mode noise rejection is required, it can
be obtained in all input designs by increasing the value of the
1OOQ resistor and 0.1 ftF capacitor connected between the input
RCA jack shield connection and the main circuit ground point.
The values shown satisfy most requirements for 1 meter cables
supplied with the newer tone arms.
189
All circuits described are signal noninverting, and constructed
with bipolar IC amplifiers for lowest noise. They are compensated for widest bandwidth and circuit stability.
To achieve optimum trouble-free performance, a few construction and manufacturing tips should be observed. For grounding
to be truly effective, all grounded components must return to a
single point. This technique is effective in minimizing ground
current loops that can cause excessive noise, signal cross-talk,
AC power line noise, and circuit instability, and permit external
noise spikes to enter. The ground center should be as close to
the input amplifier (U 1 ) as possible. All grounded components
of U 2 , U3 , U4 , Us' the output jack grounds, and the power supply
ground lead should be tied to the same U 1 ground point.
As long as the power supply leads are kept short, and adequately filtered and bypassed with polyester film capacitor at
the regulators, there is no need for individual decoupling capacitors at U2 , U3 , U4 , and Us' The power supply voltages should be
regulated for :!:18Voc '
All signal filter components should be of the highest quality, i.e.,
metalized polypropylene or polystyrene film, 1% tolerance capacitors (except for Cs ' 5% tolerance is OK) and metal film
resistors, 1% or better tolerance.
AN-125
A TWO-CHANNEL DYNAMIC FILTER
NOISE REDUCTION SYSTEM
Precision Monolithics Inc.
APPLICA nON NOTE 125
In this application, the SSM-2120 Dynamic Range Processor
and SSM-2134 op amp are utilized in a dual-channel dynamic
noise reduction circuit, where the input signal level and threshold control determine the corner frequency of a low-pass filter.
47pF
10llF
r-/'
10ka
N~; ; , y::: ~.
U
The SSM-2120 contains two class A VCAs (Voltage Controlled
Amplifiers) that are used as the filter's control element, and two
wide dynamic range full-wave rectifiers with control amplifiers.
The VCA section or variable resistor is a current device con-
10kO
35V
10"F
37.4kO
35V
~L:
37.4kO
GND
r-------~~----------------------_+~~r----,
~'.F vf
I_~I
FE';~~~RU
,oke FIL~:~i::uOLD 'OkO
F '~~F
at'OPF
2:P
' . +-+-1(---,
2 _
3
HlrP-F-+_+--.1
411'70>1'-+_ _-;
U3
+
46.4kO
1p.F
10ka VEE Vee
~-~~--~-----+-l-~Jt-100
o
220
kD
a
1
2.74kO
22
21
20
19
18
17
16
100ke
1
+-----::='"-iH----o GND
.----!---oNIl'--....,>---.fW---;
10ka
46.4kD
V
EE
100
~ OUTPUT
4
~
1.SMD
3SV
7
I
~~F
+I,-4-+-,3----1°·I'~
15
1kO
t(lka
22pF
12
2
3
-
5
u,
+
••
7
4
'Oka
4
5
6
7
8
9
10
11
VEEVc(:
.".
':;:
It
tOka
100
D
220
kc
150
100
0
V?
kO
I
10ka
SOkO
':'"
FEEDTHRU
10ka
II
INV
10kO
10kO
N?NPUT'r
10ka
2
1-
31
5
U:r
+
35V
8
6
'~rF
10ka
47
35V
37.4kO
FIGURE 1: Two-Channel Dynamic Filter Noise Reduction System
190
7
10kO VEE Vee
GND
u, THRU U.ARE S5"-2134
3+
3SV
1-0
4
>"-.....-------ir--.I\fII'---+----'
VEE Vee
§1
50P
: _::PF:>,. . . ...,..-j'0t-.F,
VEE
INPUT
NINY
VEEYCC
OUTPUT
1OOkO
+-------...l>-f----O
GND
APPLICATION NOTE 125
trolled by the +V c voltage control ports. The VCAs are employed
as variable resistor elements in a single pole low-pass filter
operating in a virtual ground configuration. The level detecting
rectifier is a full-wave averaging type with more than 100dB
dynamic range, followed by a LOG amp converter. The part also
contains two operational amplifiers with PNP output transistors
used to drive the +Vc ports.
U 1 and U2 (SSM-2134) are input amplifiers and source-load
isolating buffers. They provide a choice of noninverting, inverting, or balanced inputs. Unbalanced loading is 10kQ and
balanced loading is 20kQ. U 1 and U2 gain is set at OdB, with a
-10dBu nominal input signal recommended using ±18Voc
power supply rails. This configuration will provide an overall
circuit headroom of more than 30dB. In less critical applications,
the feedthrough trim controls and 220kQ resistors can be
eliminated.
DETAIL CIRCUIT DESCRIPTION FOR U7 (SSM-2120),
ANDU 3 &U 4
The rectifier circuit is configured to provide a negative control
voltage referenced to ground. The LOG amplifier's bias is set by
the 1.5MQ resistor. The 1.5MQ resistor also provides the
discharge path for the 1 f.lF rectifier averaging capacitor. The
discharge time constant controls the low-pass filter's action
toward a lower corner frequency. The LOG amplifier provides a
constant current charging for the ll-1F averaging capacitor. It
results in an attack (return to flat response) time constant T co of
approximately 6ms, and a low-pass filter activation T c 1 of
350ms.
The internal op amp of U7 has the gain VG set at 47. The
potentiometer at the inverting input provides the adjustable
threshold to activate the filter. The threshold adjustment ranges
from -40dBu to OdBu of input signal level. The output from the
op amp drive transistor supplies only a negative control voltage
to the VCA (+Vc ) control portIs). For example, with the filter
threshold control adjusted to OdB and a-I OdBu signal applied
to the input, fCl is ... 4kHz; or with -20dBu applied, fC2 is
... 1.2kHz, both rolling off at 6dB/Octave. With the input signal
level exceeding the filter threshold setting (OV VCA control
voltage present), the overall circuit frequency response is 20Hz
to 16kHz, at ±1 dB.
virtual ground of an amplifier loop. The feedback capacitor
around the amplifier loop sets up a single-pole low-pass filter.
The SSM-2120 (U 7 ) inverts the signal current, therefore Us and
U6 are required to invert the output signal that is summed at the
input(s) of U7 .
The design is an effective single-ended noise reduction circuit
with low distortion and noise. When utilized on a noisy signal
source, it will attenuate high frequency noise with inconspicuous operation.
TABLE 1: Circuit Performance Specifications
Nominal Input Voltage (-10dBu Out)
-10dBu
Headroom (-10dBu Out)
Input Voltage Range
+30dBu
-20dBu to +10dBu
Input Type/Impedance, Balanced
20kQ
10kQ
Input Type/Impedance, Unbalanced
Dynamic Noise Reduction Class
Dynamic Low-Pass
350ms
Filter Activate Time Constant (6dB)
Threshold Range (Level)
-40dBu to OdBu
Filter Deactivate Time Constant
Signal Rectifier Type
6ms
Full Wave Averaging
-100dB
Modulation Feedthrough, Trimmed
Frequency Response (20Hz to 16kHz)
Filter Type, Low-Pass
±ldB
Single Pole, 6dB/Oct
=3,800Hz
Input 10dB Below Threshold Setting
fCl
Input 20dB Below Threshold Setting
fc 2 = 1,400Hz
Dynamic Range
@ OdB Gain (Ref. +22dBu)
106dB
THO + Noise (20Hz to 20kHz)
0.02%
IMD (SMPTE 60Hz & 4kHz, 4:1)
Output Voltage (2kQ Load)
Output Type
Power Supply
The VCA audio input current is limited by the 37.4kQ resistor.
The VCAs operate as current devices whose outputs feed the
191
0.05%
+22dBu
Unbalanced
±18Voc Regulated
AN-127
AN UNBALANCED MUTE CIRCUIT
FOR AUDIO MIXING CHANNELS
Precision Monolithics Inc.
APPLICA TION NOTE 127
This application note describes a dual channel unbalanced
analog audio mute switch, for use in audio console mute
circuits. The SSM-2402 dual audio switch, when used in the
virtual ground configuration, truly enhances any audio mute
design. The application, as shown in Figure 1, incorporates
unbalanced stereo input buffers, dual stereo electronic virtual
ground switches (with simplified control circuit), and virtual
ground summing amplifiers.
THE AUDIO SWITCH AS IMPLEMENTED
The design utilizes the SSM-2402 (U, and U2 ) dual audio switch
in a virtual ground switching configuration. This method of
operation improves linearity over a wide dynamic range. The
SSM-2402 utilizes JFET switching, with internal wide bandwidth integrated amplifiers applied in a unique configuration.
The result is low transient intermodulation distortion, low THD,
and low IMD, while essentially eliminating all audio switching
R.
tOka
5pF
100ke
CHANNEL A
IL) OUT
1kQ
AUDIO FROM
VCAOR OTHER
SIGNAL SOURCE
(-6dBu NOM)
'0
12
37.4kO
CHANNEL A (R) IN
37.4kO
R.
10llF
O---"¥----.-.JW~--H+ H>-~M"-+-+---1
10kQ
tOka
100ka
5pF
CHANNEL A
AUDIO BUS A (Ll ---...( .-
1kO
(R)OUT
AUDIO BUS A (R)
AUDIO BUS B (L)
A·BUS
ASSIGN
~
MUTE
AUDIO BUS B (R)
tOOka
ON
CMOS OR TIL GATES
+5- (ON)
OV - MUTE (OFF)
MUTE ION OFF)
~
a·BUS
ASSIGN
CONTROL
tOOka
10FF)
37.4kO
37.4kO
R.
10j.1F
~':~~~~:,~l~ o---NV----''-.....-------------If-,~MJ'------------'
+
47
VEE Vee
FIGURE 1:
'70
2
tDka
GND
;~~
37.4kO
10ko
IN~~~:~
5
10"F
Two-Channel Noise Gate
22r~
.
3'V
~
2
5
-
.
U,
10JlF
3
35V
+
.
•
7
Vee Vee
U,. u2• u3• U, - SSM·2134
194
l00kO
OUTPUT
37.4kO
22pF
GND
APPLICATION NOTE 128
tifiers are full-wave averaging type with 1OOdB dynamic range,
followed by LOG converters. The part also contains two operational amplifiers with PNP output transistors connected in a
common collector configuration.
Two SSM-2134s are used as input amplifiers, U, and U2 , to
provide noninverting, inverting, or balanced inputs. Unbalanced
loading is 10kQ and balanced loading 20kQ. U, and U2 gain is
set at OdB, and with a-10dBu nominal input signal and ±18Voc
power, will provide overall circuit headroom of 30dB. The
VCA(s) could be DC coupled, although in this application they
are AC coupled to reduce the dependence on trimming the side
chain voltage modulation feedthrough. In critical applications
the feedthrough trim controls and 220kQ resistors should be
added.
The SSM-2120's internal rectifier produces a negative DC
voltage referenced to ground. The LOG amplifier bias is set by
the 1.5MQ resistor. The 1.5MQ resistor also provides the
discharge current path for the 1 j.lF capacitor, that controls the
gate's downward expansion time constant. The LOG amplifier
provides a constant current capacitor charging value. It results
in an attack (return OdB gain) time constant T c of approximately
6ms, and a downward expansion T c of 350ms.
The internal op amp gain Av is set at 47, with the inverting input
also providing the reference voltage. The reference voltage
range from the gate threshold control allows the gating to
activate at any source signal level from -40dBu to OdBu. The
output from the op amp drive transistor supplies a negative
control voltage to the VCA (+Vc) control port(s). The VCA(s)
control ports have a sensitivity of 6mV/dB. As shown, the
voltage divider provides a 2:1 downward expansion slope.
Below the threshold level, the gain slope is 2dB G /dB 1N •
The VCAs are current output amplifiers that are designed to
operate with virtual ground configurations such as U3 and U4 •
The VCA input current is supplied by the 37.4kQ resistor and
input voltage signal. The virtual ground amplifier feedback
resistors are 37.4kQ. With no VCA control voltage, the overall
circuit voltage gain is 1 (OdB). Other. non-gating gains can be
attained by changing the output amplifiers feedback resistor
value. The VCA input resistor should remain as shown for
maximizing the performance of the VCA(s).
TABLE 1: Circuit Performance Specifications
Nominal Input Voltage (-10dBu Out)
Headroom (-10dBu Out)
Input Type/Impedance, Balanced
Unbalanced
Downward Expander Class
Threshold Sense Time Constant (6dB)
Threshold Range (Level)
Gate Deactivate Time Constant
Signal Rectifier Type
Modulation Feedthrough, Trimmed
Gain Reduction Ratio,
Downward Expansion
Frequency Response (20Hz to 20kHz)
-10dBu
+30dB
20kQ
10kQ
Feedthrough
350ms
-40dBu to OdBu
6ms
Full-Wave Averaging
< -60dBV
1 to 2 (-2dB/dB)
±0.25dB
Dynamic Range·
100dB
THD + Noise (20Hz to 20kHz)
0.02%
IMD (SMPTE 60Hz & 4kHz, 4:1)
0.05%
Output Voltage Slew .Rate
6V/j.ls
Output Voltage (2kQ Load)
Output Type
Power Supply
195
+22dBu
Unbalanced
± 18Voc Regulated
AN-129
A PRECISION SUM AND DIFFERENCE
(AUDIO MATRIX) CIRCUIT
Precision Monohthics Inc.
APPLICATION NOTE 129
When constructing an accurate sum and difference signal from
stereo left and right sources, amplitude and phase (delay)
errors can contribute substantial amounts of crosstalk in the reconstructed left and right audio channels. A minor 1dB difference, or 6° phase error, will result in only 25dB stereo channel
separation. The design presented has essentially no phase or
group delay in the sum or difference outputs as measured over
the audio spectrum, 20Hz to 20kHz. This circuit utilizes matched
(laser trimmed) resistor networks combined with high open-loop
gain differential amplifiers to guarantee virtually no phase and
amplitude error in the sum and difference channels.
Amplifiers U3 and U4 (SSM-2134) are utilized as input signal
buffers that provide a low source impedance (OQ) to the 10kQ
summing resistors that feed the virtual ground current summing
100D
1kg
10ke
5pF
INPUT SIGNAL SOURCES
NOMINAL LEVEL (-.OdSu)
10kO·
10ke*
10kO*
SIJ-~~o---IW'-""'---~M--",,--J\M---1P-----""---j"""
SUM
>"'-.....--~ g.U~~UT
~~r~
'Oka"
....._-+-1
SIG~~~ o-.....-IW'--"I
+
OUTPUT
GND
35V
'Ok'!-.....- - - o ( L - R )
:/IJ:v----.. . .---:j.::::
~~r~
- - -........
r
35V
.....--1--1
VEE
+
35V
PSG~
* MATCHED RESISTOR NETWORK - see TEXT
U I• U2 • - SSM·2015
U3• U,. - SSM·2134
Us. - OP·215GP
'Oka"
.oon
.oon
Vee
FIGURE 1: Precision Sum and Difference (Audio Matrix) Circuit
196
"':"
OUTPUT
OUTPUT
GND
APPLICATION NOTE 129
nodes of U, and U2 • The overall gain of the buffer circuit is OdB.
The buffer amplifiers, U3 and U4 ' are compensated for a
frequency response that extends to 100kHz at +24dBu. The
buffers are configured as inverting amplifiers for lowest phase
and group delay effects.
U, and U2 (SSM-2015) are true differential input, high performance bipolar amplifiers. The current summing inputs have been
employed for sum and difference operations. All bipolar and
JFET op amps exhibit considerable propagation time differences between inverting and noninverting inputs, which result
in phase and group delay errors. The SSM-2015 was selected
because this device has practically equal propagation time
between inverting and noninverting inputs (typically less than
IOns differential). This important characteristic produces high
accuracy L + Rand L - R signals. Because U, and U2 are ultrafow noise audio preamplifiers, they contribute little noise and
distortion to output signals.
Us (OP-215GP) is a dual JFET amplifier, and is utilized as a long
time constant integrator, or DC servo amplifier. The noninverting input is referenced to ground (OV oc ) and will hold the
output terminals of U, and U2 at OV oc. Capacitor (AC) coupling
is not recommended as it would allow formation of envelope and
low frequency group delay distortion.
CONSTRUCTION REQUIREMENTS
All 10kQ resistors need to be matched within 0.05% of each
other, but can be 5% in value tolerance. The 0.1 J.lF capacitor in
the integrator circuit should be a metalized polyester film capacitor with 10% tolerance. The power supply rails are regulated at :t18Voc .
TABLE 1: Circuit Performance Specifications
20Hz to 20kHz
Frequency Response (:t 0.02dB)
104dB
Dynamic Range (20kHz Bandwidth)
THD + Noise (20Hz to 20kHz, +24dBu)
0.007%
IMD (SMPTE 60Hz & 4kHz, 4:1, +24dBu)
0.015%
Slew Rate
Nominal Signal Level
Maximum Output Voltage
(2kQ Load)
Amplitude Accuracy
Differential Error
197
10V/J.ls
-10dBu
+23.3dBu or 11.3VRMS
0.05%
-
48.4
k"
1\
100
100
"
"
-::'
22pF
1.sMa
1\
2
-::'
-:: ~ 1N9148
••
5 22PF
FIGURE 1: Two-Band Audio Compressor
2.43."
"GR
r
+15V
20ka
-15V
""
3
-::'
1k"
SOk"
-::'
2 ......... 25
LOW·PASS
GAIN REDUCTION RATIO
198
OUTPUT
1OQkO
37.4kO
15VTANT
-15V
\~
GND
1'~
2.F
.
10ka
30.1ka
10""F
8
5 22PF
10ke
!~jF
2.74
k"
.
~
.
+U
4
-::".a
25V
3
+
3
SSM·212Q
37.4ka
1k"
2
PGJ§
20
5
-::'
lako
2~~F
U,
~
10kO
O.047"F
5 22PF
1~~
----.!!
11
-3QdBu
10kO
15
121
---.!.
1~~
8
>22
+15dBu
"T
-::'
1\
INPUT
6
5
+
3
-::'
THRESHOLD
~~
Z. 1N9148
22PF
c OMPRE5510N
22pF
2.43kQ
8
2.43kO
37.4kn
20kn
;>~
U,
+
"GR
U 1 - SSM·2120
U:!. U3• U... Us. U6 • U7 - SSM·2134
+
5
6
U,
8
22pF
APPLICATION NOTE 130
Two continuously variable gain reduction controls (R GR ) in the
VCA control circuit provide independent adjustment of compression gain slopes. The GAIN REDUCTION ratios are each
adjustable from 2 to 25 for high-pass and low-pass bands. This
range of adjustment provides mild compression to severe
limiter/clipper action independently on each band. Thus the
irritating "hole producing and pumping" character of single,
wide-band compressor circuits can be reduced. The SSM-2120
provides a dynamic range of greater than 100dB over the
frequency range of 20Hz to 20kHz with typically less than 0.02%
THD + noise, and 0,.05% IMD.
The small signal averaging time for the 2J.lF integration capacitor shown is 12ms. The attack time to 3dB of final value is about
6ms and is almost independent of signal level increase for level
changes in excess of + 1OdB. The compression release rate is
controlled by the 1.5MQ discharge resistor in the integrator
circuit. The recovery time constant is nearly linear since the
discharge resistor returns to the -15V oc rail, and the rectifier
produces a positive control voltage.
The COMPRESSION THRESHOLD control (R T) allows the
compressor to take effect from - 30dBu to +20dBu input levels.
The SSM-2120's log-average precision rectifier is configured as
a feedback-type level detctor. The design produces consistent
and precise compression profile of the input signal with no
threshold level or compression drift over time and temperature.
Input Voltage Range
(Nominal for OdBu Out)
The SSM-2120's full-wave log-averaging rectifier and control
amplifier form an integrator and buffer circuit that isolates the
low impedance VCA control port from the integrator timing
circuit. This circuit senses the VCA output level and modifies its
compression profile by feeding the averaged VCA signal plus
the compression threshold control signal back into the VCA
control ports. The control Rs is used to balance the threshold
amplitude between the two bands to pre-establish the compressor dynamics.
TABLE 1: Circuit Performance Specifications
-10dBu to OdBu
245mV to 755mV
Rectifier Type
Averaging
Compressor Amplifier Class
Feedback
Attack Time (+10dB or Greater Level Change)
Recovery Rate
6ms
1.67dB/ms
Feedthrough, Trimmed
-100dB
Gain Reduction Range
2 to 25
Frequency Response (20Hz to 20kHz)
0.2dB
Dynamic Range @ OdB Gain
100dB
THD + Noise ( 20Hz to 20kHz)
0.02%
IMD (SMPTE 60Hz & 4kHz, 4:1)
0.05%
Output Voltage Slew Rate
Output Voltage (2kQ Load)
199
6V/J.ls
+22dBu or 10VRMS
AN-131
A TWO-CHANNEL VCA
LEVEL (VOLUME) CONTROL CIRCUIT
Precision Monolithics Inc.
APPLICATION NOTE 131
The dual-channel voltage-controlled amplifier (VCAl level
control circuit describes a useful application of the SSM-2122
dual VCA, SSM-2134 low noise op amp, and PMl's OP-215BP
JFET/bipolar op amp. This circuit is very handy when extremely
close gain matching of a stereo audio source is desired, such as
in ON-AIR and production audio consoles.
The design features a balanced input buffer amplifier and VCA
driven by a level shifting amplifier which is controlled by a single
10kQ linear potentiometer. Additionally, there are fully adjustable and independent gain limit and maximum attenuation trim
controls. The VCA circuit has a nominal attenuation range
greater than 95dB and has input overdrive protection. The
signal-to-noise ratio exceeds 100dB with a gain of 10dB, and
headroom of 32dB. The amplitude varies less than :1:0.1 dB over
the frequency range 20Hz to 20kHz. Typical THO and IMO are
less than 0.005% and 0.02%, respectively.
As shown, the circuit includes two line-level inputs designed for
a -10dBu input signal level. The SSM-2134 (U 2 and U4l input
buffer amplifiers can be connected for balanced or unbalanced
inputs with inverting or non inverting inputs. The input loading
impedance is 1OkQ unbalanced and 20kQ balanced. The input
buffer amplifier also limits step function slewing voltages from
entering following stages. Other input levels can be accommodated by adjusting the feedback resistor RF2 . For example: for
a nominal input level ofOdBu, RF2 should be changed to 3.16kQ,
or for a nominal input level of +1OdBu, RF2 changed to 1kQ to
provide the optimal current drive to the VCA. C F should also be
changed to 68pF and 2.20pF respectively for both U2 and U3 .
For other input levels, RF2 can be calculated:
RF2 = 10 x 103 x EXP·(~)
-20
e,
"Ft
""
22pF
.,5V
22pF
37.4kD
FEEDTHROUGH
NULL
+------.--_--t>.IV'---<>-I5V
N?NN~~~ o----/IIII'--+-<.J
(BAL) HOdBu)
IN~~¥ o----/IIII'-+itj
GND
·~~F
220pF
"Ft
'.0
kg
,.
22pF
".
".
.Oka
N?NN~~~ o---.fIJ'V'-......>.j
,.
lDO
Q
11
24'
kg
12
OUTPUT
(-1OdBu)
lDOkD
'DO
Q
GND
"
14
U,
SSM·2122
37.4kO
(BAL) (-10dBu)
e,
veA
37.4kn
IN~~~ o----/IIII'--+-"1
GND
E
0-_--/1111'--'
0-_--/1111'--'
24'
kD
I DOD
'ODD
·~~~F
..
",_
0.1"F
-1SV
sake
FEEDTHROUGH
NULL
.1SV
E
OUTPUT
(-1DefBu)
100kQ
GND
"-1mV
OdBu to -40dBu
OdB to -90dB
20Hz to 20kHz
110dB
0.005%
IMO (SMPTE 60Hz and 4kHz, 4:1)
0.02%
Output Voltage Slew Rate
12V/lls
Rated Output Level (6000 Load)
Output Impedance
Output Type
Power Supply Requirements
+24dBu
680
Balanced
:l:15Vpc Regulated
208
AN-13S
THE MORGAN COMPRESSOR!
LIMITER
Precision Monolithics Inc.
APPLICATION NOTE 135
The following application was written by Michael Morgan, a
consultant to PMI with extensive experience in the design of
professional audio equipment, including high-performance
dynamic range processors. While currently a freelance consultant, Mr. Morgan spent nine years at Valley International as a
principal designer of their products.
SHAPING THE RESPONSE
Figures 1aand 1b illustrate the transferfunction of an ideal compressor as the ratio is varied with a fixed threshold, and as the
threshold is varied with a fixed ratio, respectively. Note that in
both cases, the rotation point is easily identified at OdB. Note
also that the compressor operates as a limiter when the threshold is equal to, or higher than, the rotation point. Forthis reason,
the device described in this application note may be considered
as a "compressorllimiter," but because it possesses a rotation
point, we shall refer to the device as a compressor.
This application note describes the configuration of a low cost,
high quality compressor with variable attack time and ratio
control using the SSM-211 0 Level Detector and SSM-2014
VCA. The discussion begins with an overview of compressor/
limiter fundamentals, and is followed by a description of the
unique attributes of the integrated circuits and their implications
for the design engineer.
30
COMPRESSOR/LIMITER FUNDAMENTALS
The function of the audio compressor is, of course, to compress
the dynamic range of the processed audio signal by altering the
gain of its signal path in response to the relative level of the
signal as compared to an arbitrary setpoint called the threshold,
thus adding gain to low-level signals and reducing gain in the
presence of high-level signals.
.
~
~
I
10
0
r- RAno. 20:1
RAno.
-10
~
_20
/
-40
V,
V, ,'~
,
_.0
_
I
"'Xi. . . . . ~'
~
' - ROTAnON
POIIiT
_
/~,'
5
An audio compressor consists primarily of two functional sections, one of which derives a control signal by measuring and
otherwise manipulating the audio signal to produce a voltage
suitable for the second functional section, which is the gain
control element. The gain control element is a device which can
alter its attenuation, gain, or resistance in response to an external signal, such as a voltage or current.
uJITY
Gr,' ~
I
'0
l.-
THRESHOLD .-20dO
I
~
4
~
_
0
~
~
30
INPUT LEVEl. (dB)
The audio compressor differs from a similar device, called a
limiter, in that a compressor exhibits a rotation point which is
independent of its threshold setting. The rotation point is the
locus on a graph of the compressor's transfer function at which
the gain control element exhibits unity gain, and through which
all lines derived from data describing the device's output level
as a function of input level will pass. A limiter, in the purest
sense, adds no gain and has no rotation point.
FIGURE 1a: Output vs. Input Transfer Function of an Ideal
Compressor
.
The compressor's ratio is defined as the increase in input level,
in decibels, above the threshold which will result in an increase
of output level equal to 1dB, and is a function of control circuitry
gain. For example, each increase of 1dB in signal level above
the threshold may cause a corresponding decrease in gain
equal to 1dB, thus keeping the output level constant for a ratio
of infinity:1, or it may cause a 1/2 dB decrease in gain, thus
allowing the output level to rise at a ratio of 2:1. A compressor
may have a very high ratio, and conversely, a limiter may have
a very low ratio.
~
0
I--::±::=!.,,--+--l--:::.E'-'-+--I--I
~ 1--t--;---:iW"'~'---+_10
5
~~ol-~~,-~.-l---+--+--I--I
4jC-T1I~+-t-+--t--f--;
-40jC-~~-;-~-T--t--f--;
-40
~
-20
-10
a
10
20
30
INPUT lEVEL (dB)
FIGURE 1 b: Output vs. Input Transfer Function of an Ideal
Compressor Having a Fixed Ratio Showing the Effect of
Threshold
209
APPUCATION NOTE 135
Audio compressors use two types of circuit topologies. In a
feedback, or closed-loop configuration, the control signal is
derived by measuring the output level of the gain ·control element. In a feedforward, or open-loop configuration, the control
signal is derived by measuring the level of audio present at the
input of the gain control device. Each topology has its typical
advantages and disadvantages. The most common type of
audio compressor uses the feedback topology. Among its
advantages are: low parts cost; ease of configuration; ability to
use simple, "linear" control circuitry and gain control elements.
The disadvantages of the feedback topology are numerous:
inability to realize continuously variable parameters accurately;
heavy dependence upon circuit trimming to assure consistency
in performance from unit to unit; tendency toward overshoot in
either control signal or processed signal; virtual inability to configure circuitry for performing arbitrary dynamic functions, such
as program control of release times, equalized sidechain functions, and interactive processing having more than one control
function per gain control element.
VARIABLE TIME INTEGRATOR
In this application, the SSM-211 Ois used in the design of a
feedforward compressor. The log of the absolute value of the
input signal is extracted, then integrated by a Ell x C circuit
which corresponds roughly to an RC network in the linear
domain (see Figure 2).
Vee
SSM-211D
10,
1
PIN2
LOGAyOUT
c
The feedforward topology has long been considered by equipment designers to be the more versatile method of configuring
audio dynamics processors. Among its advantages are: precise
control of dynamics; ability to accurately and continuously vary
processor parameters, such as ratio and attack-and-release
time constants; easy circuit trimming for unit-to-unit consistency; possibility to realize arbitrary types of dynamics alteration; ease in configuration of interactive. processing schemes
using multiple control signals to operate a single gain control
element; and relative freedom from control and signal overshoot. The disadvantages of feedforward topology have traditionally been: dependence upon relatively expensive and little
understood logarithmic circuitry in configuration; difficulty in
sourcing high-quality, low cost logllinear multipliers (dB/volt
VCAs); dependence upon expensive 10g/RMS detection
schemes to achieve the required accuracy for wide range of
control.
FIGURE 2: Simplified Schematic of a Variable Time Con.stant Log of Average Integrator Using the SSM-211 0
The product of this operation is not, as one would expect, the average of the log of the absolute input value. During the integration process achieved by charging the integrator capacitor, C,
the charging current is proportional to the antilog of the voltage
appearing at the base of 0,. Since the voltage at the base of 0,
represents the log of the absolute value of the input, the log and
anti-log terms cancel, thus leaving C to charge as a linear integrator with a current proportional to the absolute value of the
input until the voltage across Capproaches the voltage at the
emitter of 0, ..In this manner, the order of the logging and
averaging operations are reversed. This is a very important
phenomenon which directly influences the audibility of the com:
pression process, and will be discussed at length later.
By using integrated building blocks, feedforward control technology can be realized by equipment designers by virtue oftheir
ease of application and low cost. These readily available integrated circuits deliver performance equal to or surpassing
complicated discrete circuits, and are more cost effective for
general use by equipment manufacturers.
The integration time of the circuit in Figure 2 is varied by changing the current through the collector of 03. This is accomplished
by means of the multiplier circuit consisting of the operational
amplifier, transistors 02 and 3 , and their associated resistors.
°
THE SSM-2110 MONOLITHIC LEVEL DETECTOR
The SSM-211 0 level detector IC represents a significant advancement in low cost, high quality converter circuitry. The
device greatly simplifies the design of feedforward dynamic
processors since it produces an accurate output that is proportionalto the log of the absolute value of its input, and the log of
the rms value of its input, in addition to the corresponding linear
values. Such versatility is unique among detector/converter
configurations.
Current IREF is forced to flow through the collector of 02. The
Vbe of 02 is thus made to be proportional to the log of IREF by
virtue of the silicon transistor'S intrinsic logarithmic property,
idealized in the equation:
Vbe = kT/q x In(l/I.) where
k = Boltzman's constant (1.38 x 10- 23J/K)
T = Temperature in Kelvins
q = Charge on an electron (1.60 x 10-' 9C)
Ie = Collector current
I. = Reverse saturation current (extrapolated as V be _ 0)
210
APPLICATION NOTE 135
°
of 03). The illustration is a composite of several sampled waveforms, thus, scalar references in the X-axis are valid only for
each pulse.
When transistors 02 and 03 are closely matched, Vb. of 2,
which appears also at 03'S emitter, causes a current equal to Ie
of 02 to flow through the collector of 03. This transistor collector
current, IREF' may be used to charge or discharge a capacitor,
to cause a voltage drop across a resistor, or may be converted
to a voltage at the output of an operational amplifier. The collector current of 0 3 may be varied by applying a voltage at the
bases of 02 or 3, or both bases simultaneously. As a rule of
thumb, at 25°C, each 60mV change in Vb will cause a corresponding ten-fold change in 03's Ie. By using the "shorthand" log
relationship for gain in which a ten-fold change in voltage (or
current) equals 20dB, we can say that the collector current of 03
can be made to vary antilogarithmically at a rate of 1 dB/3mV
(20dB/60mV). In effect, the circuit generates a voltage at the
emitter of 02 which corresponds to the log of the input current,
IREF' adds the control voltage, then generates a current at the
collector of 03 which is proportional to the antilog of the sum.
Thus the portion of the circuit formed by the operational amplifier, 2 , 3, and their associated passive components form a
two-quadrant multiplier whose output is a high compliance
current sink.
As can be seen in Figure 3, in the log average detection mode,
the response of the device to large level changes is relatively
fast, while the last 50 to 1OOmV of change occurs at the characteristic integration time determined by the status of the charge
on the capacitor, C, as it is discharged by the collector current
of 03. As the voltage across C approaches the voltage at the
emitter of 1 , the transistor behaves less as an antilog element,
and more as a linear resistance proportional to VbiIREF"
°
°
These attributes determine the detector circuit's response to
complex waveforms, and directly affect the audibility of the compression process. Considerthe following explanation: Humans
respond to changes in audio signal level by perceiving volume
as being proportional to the log of the acoustic power emitted by
a source, thus the human listener perceives a source emitting
10 watts of "sound," (if the reader will permit such simplifications) to be roughly twice as loud as the same source emitting
only 1 watt. This implies that one should be able to control audio
levels logarithmically for a natural "sound" in the processed
output. That is generally the case, but the principle does not
extend, in a strict sense, to the control of a compressor.
°°
A positive voltage applied to the base of 02 will cause a corresponding decrease in 03'S collector current, while a positive
voltage applied to the base of 03 has the opposite effect, causing an increase in Ie of 03. Both bases may be controlled by
bipolar voltages, but IREF must flow in the direction indicated by
conventional current flow through the transistors (must be
sourced froma voltage more positive than the non inverting input
of the operational amplifier for NPN transistors).
If one accepts the premise that the most common uses of the
audio compressor are to enhance the "loudness" of the processed material, or to "level" the apparent volume of the processed material, one should be aware of the effect of waveform
complexity upon perceived loudness. A simple example is found
in the case of a musician playing an instrument: when called
upon to perform a solo, in order to "stand out" from the background music, the instrumentalist produces more complex
sounds, in addition to producing sounds at a higher relative
level. The increase in complexity provides a psychoacoustic
"cue" which translates to the human listener as increased perceived loudness.
In operation, varying the current which discharges C also
causes a varying offset voltage at the collector of 03 which
equals the change in Vb' and must be compensated for in order
to derive a useful control voltage. Figure 3 shows the response
to a +10 volt pulse input having a repetition frequency of approximately 4 pps and a duty cycle of 50%. Note that the X-axis
corresponds also to increasing integration time (decreasing Ie
20~V -------------f~--------------~~----------------------~~----------~~~~---
10~V ------------~----~----------~------~~----------~~-------------------------
ov ------------~--------~------~------------~~----~~-------------------------MAXIMUM ATTACK TIME
FIGURE 3: Output Voltage Response of the Variable Time Constant Log of Average Integrator to a LF Square Wave Input
211
APPUCATtON NOTE 135
During the compression process, if the detector circuitry produces a signal which calls for more gain reduction in response
to the added harmonics in a sound which cause an increase in
complexity, the gain control element will comply, thus making a
solo instrumental exit the compressor at a lower level, foiling the
intent of the performer. This is precisely what happens when
using AMS detection -the detector circuit (correctly) assesses
the increased complexity as an increase in sound energy, and
calls for gain reduction.
offset corresponding to the change in voltage at pin 2 which
results from varying the integration time is applied via A'2.
Variable resistorVA2 allows the adjustment of the compressor's
rotation point, or that input level at which the output of A4 will
be OV.
A pair of matching two-quadrant multipliers, which are configured using amplifiers As and As along with a four-transistor
array 02 (MAT-04), allow adjustment of the compressor's ratio
and adds sufficient gain as a function of both the threshold
setting from VR4 and A g , and the ratio, as determined by VR3
and As' to maintain the compressor's rotation point. Amplifier A7
converts the current output of the ratio multiplier from 02b into
a voltage which charges the holding capacitor Cs via 03a to a
voltage corresponding to the amount of gain reduction required
of the VCA. Amplifier A'2 converts the current output of the
maintenance gain multiplier from O~c into a voltage corresponding to the quiescent gain required lor the VCA to maintain the
compressor rotation point, and adds or reduces gain at the VCA
in response to the output gain control VA 7.
The log averaging detector is relatively insensitive to increases
in waveform complexity, and "ignores" the loudness cue thus
provided. As a result, a complex waveform exits the compressor
at a slightly higher level than it would if under the control of an
rms detector. This rather unique "quirk" found in the log averaging process allows a solo instrumental or vocal to stand out in
the processed signal, thus preserving the intent of the performer.
As a log averaging detector, the SSM-211 0 exhibits remarkably
little departure from an idealized log curve representing its input
level throughout the entire range of the adjustable integration
time, and offers superior performance to the equipment designer in this type of application. In addition, at higher input
levels, the device does not compress the waveform at its output,
thus under-reading the input value. In fact, the detector exhibits
a gentle and quite predictable deviation from log conformity at
high input current levels which results in the addition of a linear
error term. This causes a slight over-reading of the input, and is
quite useful for aficionados of "soft knee" limiting. It is unlikely
that any real compressor design would require so wide a range
of operation that this deviation might pose a problem (> 60 dB),
but since the error term is so predictable and consistent, it can
easily be corrected elsewhere in the control circuitry if necessary.
The release current sink is formed by amplifier A, 0' and two
sections of monolithic transistor array 03. Compensation for
Vbe of 38 , and for the quiescent change of voltage across Cs
caused by varying the release current through 03C are applied
via R3, to Ar
°
Amplifier Ag and diode 0 3 form a precision half-wave rectifier
whose output is a positive voltage equal to the gain reduction
signal. This point may also source a gain reduction indicator
with intrinsic scaling of + 1 V = -20dB. Since metering is a matter
of preference for the design engineer, no attempt has been
made to include a gain reduction indicator as part of this circuit
discussion.
As
to be negaSince it is possible for the inputs of both As and
tive voltages, it is wise to include germanium diodes 0, and O2
to preventforward conduction olthe internal base to emitter protective diodes in the MAT-04, thus eliminating the possibility of
reverse leakage coupling between the multipliers. The existence of these diodes also prevents application of the MAT-04
as the charging transdiode 38, since a voltage more negative
than that across Cs will frequently be present at the emitter of
THE COMPRESSOR CONTROL CIRCUIT
Figure 4 illustrates a compressor control circuit incorporating
the SSM-2110 as the detector element. Because the temperature compensation characteristics of the log recovery amplifier
are not required in this application (control of a VCA having a
complementary control sensitivity temperature coefficient) and
to eliminate trimming of scale factor on a unit by unit basis, the
log recovery amplifier Is disabled by connecting its inputs to the
IC's VREF output. This step is necessary for proper operation of
the IC when the log recovery amplifier is not used. The log
recovery transistor is not used since offset is not a reiil concern
in this circuit configuration.
°
°3a·
Amplifier A'3 outputs the algebraic sum of the various gain control signals for application to the compressor VCA section which
will be described next.
Selection of the internal scale factor at 1Vldecade, and inclusion of the -7.SV "mSith rail" are arbitrary choices made by the
author in order to accommodate the use of the variable integrator, and to skew the control markings on the front panel controls,
ind icated by the enclosed names associated with those variable
resistor potentiometers. Placing the rotation point, as determined by A~, at the nominal operating line level, e.g., +4dB, etc.,
minimizes the effects of errors caused by the uncompensated
temperature coefficient of the ratio multiplier, and any minor
deviations in log conformity inherent in the detector circuitry or
VCA sections of the compressor.
The amplifier in the audio signal path, A" should be of a high
quality, low noise type such as the SSM-2134. The remaining
amplifiers may be general purpose types, preferably having
FET input stages to minimize the effects of input bias currents
on the accuracy of the multiplier circuits.
i
Amplifier A 2, and the SSM-2210 matched transistor pair 0,
0, b form the voltage-controlled current sink for the variable log
averaging integrator. Amplifier A4 boosts the output of the integratorto a usable level by increasing the nominal6mVldB scale
factor of the signal at pin 2 to 1V120dB, or 1 V per decade. An
212
!!
il
G')
c:
:II
m
~
f
ii:
'"
g
~
[
(')
~.
NOTES:
ALL VARIABLE RESISTORS ARE TRIMS. EXCEPT PANEL
CONTROLS WHICH ARE INDICATED BY A FUNCTION BOX
lSI
MATH RAIL (-7.5V)
..!r AUDIO GROUND
..1 CONTROL GROUND
C,o
+15V
'"
R,.
C,
c:
~
f
5-
N
.....
TOPOINT"B"
ON FIGURE 5
37~
~
lh I ~ 'l~
RS
W
R,.
101lkn
2~
bOPOINT"A"
NFIGURE5
~
J, I I
SSM-~10
!
II'NI
3 ... II'NI
~~4k!l
47pF
D1
R34
+15V
c.,
47pF
49.9kQ
I ...
R33
49.91<0
1%
TO
4 VREF
~---.....--~) ~~UCTION
GND
03
METER
lN914 +lV.-2OdB
: IlL
llag l'N 2
Co>
8
_ C3
JO.01~F
RII
151<0
R..
1821<0
1'"
°
30• D3E - N.C.
5s12OdB
VAs
501<0
/lo.ossl2OdB
IREle.:E I
CONTROL
:J>
"II
"II
§
o
z
~m
~
Co>
O""'III-"
TRIM
R..
10kll
GND
AUDIO
OUTPUT
Ra
1D-.....+""·0 V",""
Features
• Fits AD7226 Sockets
• ±1/2 LSB Maximum INL and DNL
• Space Saving 20-Pin 0.3" Wide DIP Package
Functional Diagram
VREFH, VREFL, VAEFHz VREFLz
2
L6
1
151
20
DAC-8800
13
Octal a-Bit CMOS TrimDACTM
VourO
VourC
VourD
Vour"
VOUTF
VourD
VcxrrH
V••
217
Features
• Excellent for General Purpose Voltage
Adjustment/Level Setting Applications
• ±1/2 LSB Relative Accuracy
• TTL Compatible, Serial Input
4J,ls Settling Time
OTHER PMI PRODUCTS FOR AUDIO APPUCATIONS
DIGITAL-TO-ANALOG CONVERTERS
Advance Information
DAC-8840
Functional Diagram
.-------t---oVINA
DAC-8840
r- +-NV--",---N-V--- \
\
".
Voo
:>-<'-t--l--< Your A
!...:::.. ____ I
I
OAe REGISTER
DGND
Vas
8-BIT Octal
4-Quadrant, CMOS
Multiplying TrimDACTM
Features
• Replaces 8 Potentiometers
• 0.5% Total Harmonic Distortion
• 1MHz 4-Quadrant Multiplying Bandwidth
• No Signal Inversion
• Eight Individual Gain-Controlled Channels
• 3-Wire Serial Input
• Low Cost
• ±3Volt Minimum Output Swing
• Mid-Scale Preset, VOUT = OV
• 24-Pin 0.3" DIP and SOL-24 Packages
seo
Functional Diagram
DAC-8043
12-Bit Serial Input
Multiplying CMOS D/A Converter
in an 8-Pin Mini-DIP
La
Features
12-Bit Accuracy in an 8-Pin Mini-DIP
Fast Serial Data Input
Low ±1/2 LSB Max INL and DNL
Max Gain Error: ±1 lSB
Low 5ppm/oC Max Tempco
ESD Resistant
low Cost
-40°C to +85°C for the Extended
Industrial Temperature Range
o-''t----<:j
elK D - ' ' f - - - - . j
SRlo-'l--~::'::::J
.---F-()GND
Functional Diagram
DAC-8143
12-Bit Serial Daisy-Chain
CMOS D/A Converter
V DD
14
,.
R,.
Features
• Fast, Flexible, Microprocessor Interfacing in
Serially-Controlled Systems
• Buffered Digital Output-Pin for Daisy-Chaining
Multiple DACs
Minimizes Address-Decoding in Multiple DAC
Systems - Three Wire Interface for Any Number
of DACs
One Data Line
One ClK Line
One load Line
10011
lour.!
AGND
elR
~
CO;
ST8 1
~
STB 3
ST8 2
•
SRI
SRO
12
DGND
218
OTHER PMI PRODUCTS FOR AUDIO APPLICATIONS
DIGITAL-TO-ANALOG CONVERTER SELECTION GUIDE
DIGITAL-TO-ANALOG CONVERTER
SELECTION GUIDE
ranges, and some which have become industry
standards. The D/A converters have been
arranged in the selector guide by resolution. 6-bit
through 16-bit devices are sorted by number of
D/A converters per package.
PMI offers a complete line of digital-to-analog
converters (DACs), all of which are guaranteed to
be monotonic over their operating temperature
D/A CONVERTERS
Power
Dissipation
(mW)
Digital Interface
Resolution
(Bits)
Settling
Time
DACs/
Package
DAC
Output
*DAC-01
6
3J.ls
1
V
250
6-Bit
PM-7224
PM-7524
DAC-08
DAC-108
DAC-888
*DAC-1408A
*DAC-1508A
DAC-20
8
8
8
8
8
8
8
8
5J.ls
200ns
135ns
20ns
400ns
250ns
250ns
150ns
V
60
5
136
136
190
265
265
194
Latched 8-Bit
Latched 2-Digit BCD
8-Bit
8-Bit
Latched 8-Bit
8-Bit
8-Bit
2-Digit BCD
DAC-8228
DAC-8229
PM-7528
PM-7628
8
8
8
8
5J.ls
5J.ls
350ns
200ns
2
2
2
2
165
165
5
5
Latched
Latched
Latched
Latched
DAC-8408
PM-7226
DAC-8426
8
8
8
250ns
5J.ls
5J.ls
4
4
4
V
V
5
250
'250
8-Bit w/ Readback
Latched 8-Bit
Latched 8-Bit
PM-7228 .
PAC-8800
DAC-8840
8
8
8
5J.ls
2J.ls
4J.ls
8
8
8
V
V
V
430
25
150
Latched 8-Bit
Latched Serial
Latched Serial
Product
I
I
I
I
I
I
I
'Not recommended for new designs.
219
V
V
I
I
I
8-Bit
8-Bit
8-Bit
8-Bit
OTHER PMI PRODUCTS FOR AUDIO APPUCATIONS
DIGITAL-TO-ANALOG CONVERTER SELECTION GUIDE
01 A CONVERTERS
Product
PM-7533
*DAC-02
*DAC-03
*DAC-05
DAC-06
DAC-10
DAC-86
DAC-88
DAC-89
DAC-100
DAC-210
DAC-401
Resolution
(Bits)
Settling
Time
DACsl
Package
10
10 + Sign
10 + Sign
10 + Sign
10 + Sign
10
10
10
10
10
10 + Sign
10
600ns
2J.Ls
2J.Ls
2J.Ls
1.5J.Ls
150ns
500ns
500ns
500ns
300ns
1.5J.Ls
2ns,400MHz
1
1
1
1
1
1
1
1
1
1
1
1
DAC
Output
I
V
V
V
V
I
I
I
I
I
V
V
Power
Dissipation
(mW)
Digital Interface
10-Bit
30
350
10-Bit
350
10-Bit
10-Bit
350
10-Bit
300
285
10-Bit
207
Chord + Step
262
Chord + Step, J.L Law
263
Chord + Step, A Law
250
10-Bit
315
1O-Bit + Sign
450
Latched 10-Bit
DAC-8012
DAC-8043
DAC-8143
PM-7541
PM-7541A
PM-7542
PM-7543
PM-7545
PM-7548
PM-7645
DAC-312
PM-562
12
12
12
12
12
12
12
12
12
12
12
12
1J.LS
1J.Ls
1J.LS
1J.Ls
1J.LS
1J.Ls
1J.LS
1J.Ls
1J.LS
1J.LS
500ns
1.5J.Ls
1
1
1
1
1
1
1
1
1
1
1
1
10
10
10
10
10
10
10
10
10
10
305
465
DAC-8212
DAC-8221
DAC-8222
DAC-8248
12
12
12
12
1J.LS
1J.Ls
1J.LS
1J.Ls
2
2
2
2
10
10
10
10
DAC-8412
12
20J.Ls
4
DAC-16 t
16
650ns
• Not recommended for new designs.
t Advance information - check factory for availability.
220
12-Bit wI Readback
Latched Serial Daisy
Latched Serial Daisy
12-Bit
12-Bit
Latched 4-Bit
Latched Serial
Latched 12-Bit
Latched 8-Bit
Latched 12-Bit
12-Bit
12-Bit
Latched 12-Bit
Latched 12-Bit
12-Bit Double-Buffered
8-Bit Double-Buffered
V
180
12-Bit wI Readback
V
200
16-Bit
OTHER PMI PRODUCTS FOR AUDIO APPLICATIONS
OPERATIONAL AMPLIFIERS
Precision, Low Noise
OP-27, OP-270, OP-470
OP-27
Single
Extremely Low Noise (@ 1kHz)
Very Low Offset Voltage
Slew Rate
Gain-Bandwidth
3.SnV/YHz
25ILV
2.8V/ILS
8MHz
OP-270
Dual
OP-470
Quad
5nV/YHz
5nV/v'HZ
400ILV
2V/ILS
6MHz
75ILV
2.4V/lLs
5MHz
Max
Max
Typ
Typ
The OP-27, OP-270 (dual), and OP-470 (quad) feature low noise with
excellent DC performance. Each device is unity-gain stable. Supply current for
the OP-270 and OP-470 is unusually low for low noise amplifiers, running at
2.2SmA typically per amplifier. The excellent AC matching between amplifiers
makes them ideal for matched gain stages, audio amplifiers, and active filters.
The low offset, high CMR and PSR are especially useful in low noise
instrumentation amplifiers.
Precision, Low Noise, Fast
OP-37, OP-271, OP-471
OP-37
Single
High Gain-Bandwidth
63MHz
OP-471
Quad
OP-271
Dual
5MHz
6MHz
Typ
7V/ILS
SnV/YHz
SV/ILS
7nV/v'RZ
200ILV
SOOILV
Typ
Typ
Max
(AVCL~5)
Excellent Slew Rate
Low Noise (@ 1kHz)
Low Offset Voltage
17V/ILS
3nV/v'HZ
25ILV
The OP-37 has very good gain-bandwidth performance and is stable for gains
of five and above. The OP-271 (dual) and OP-471 (quad) are unity-gain stable.
Wide Bandwidth, Low Noise, Precision
OP-S1
High GBW (AVCL ~ 10) ............................................ 200MHz
Low Vo~age Noise ................................ 3.4nV/YHz @ 1kHz
Low Offset Voltage ..................................................... 5OOILV
High Slew Rate ......................................................... .45V/lLs
Fast Settling ................................................. 300ns to 0.01%
High Gain ............................................................... 475V/mV
Typ
Typ
Max
Typ
Typ
Typ
The OP-61 offers an outstanding combination of high speed and low noise with
DC precision to meet the demands of today's high performance equipment.
A very high gain-bandwidth product of 200MHz (AVCL ;::: 10) and a fast 4SVIllS
slew rate are achieved with only 7.SmA supply current.
The OP-61 is available in 8-pin plastic DIP and 8-pin small outline (SO)
packages, with guaranteed operation over the -40°C to +8S o C temperature
range.
Also available in MIL temp and LCC packages.
221
OTHER PMI PRODUCTS FOR AUDIO APPLICATIONS
OPERATIONAL AMPLIFIERS
Dual High-Speed JFET Input
OP-249
Fast Slew Rate ............................................................ 22V/IlS
Fast Settling .................................................. 900ns to 0.01 %
Low Offset Voltage ...................................................... 30011 V
High Open-Loop Gain ........................................... 1 ,000V/mV
Low THO .................................................................... 0.002%
Typ
Typ
Max
Min
Typ
This high-precision dual features high slew rate, excellent DC performance and
very low cost Specifications include a maximum long term limit for input offset
voltage, a first for JFET input amplifiers.
The OP-249 is available in an 8-pin plastic DIP with guaranteed operation over
the -40°C to +85°C temperature range. Also available in military versions.
Matched Monolithic Quad NPN Transistor
MAT"04
Low Noise Voltage @ 100Hz, 1mA ................... 2.5nV/;!Hz
High-Current Gain .......................................................... .400
Gain-Bandwidth Product ......................................... 300MHz
Excellent Log Conformance ............................... rSE = 0.6Q
Very Low Offset Voltage ............................................ 200IlV
Max
Min
Typ
Max
Max
Matching Guaranteed for All Transistors
The MAT-04 is a quad monolithic NPN transistor that offers excellent
parametric matching for non-linear circuit applications. Performance
characteristics of the MAT-04 include hl~h gain of 400 (Min) over a wide range
= 1mA); and
of collector current; low noise (2.5nV/v'Hz Max at 100Hz,
excellent logarithmic conformance. The MAT-04 also features a low offset
voltage of 200llV and tight current gain matching to within 2%.
The MAT-04 is an ideal choice in applications where low noise and high gain
are required.
'cz
Other Products from PMI:
•
•
•
•
•
•
•
•
•
•
•
High-Speed Operational Amplifiers
Low Power/Micropower Operational Amplifiers
High Accuracy Instrumentation Amplifiers
High-Speed Buffers
Data Conversion Products
Voltage Comparators
Precision VOltage References
Analog Switches and MUltiplexers
Sample-and-Hold Amplifiers
Precision Matched Transistors
Communication Products
222
HIGHLIGHTS FROM
PMI'S 1990 DATA BOOK
Precision Monolithks Inc.
Over 1,800 Pages Of Products For The Analog Designer!
Covers instrumentations, data
acquisition, process control, telecom,
and audio applications.
----------=--=-
A comprehensive directory of
direct and functional ______________
equivalent products.
_
-=:::::::::::::
1a
Applications Subject Index
1b
Ordering Information
2
Product Assurance Program
3
-=::::::::::::
~
Industry Cross Reference
4
Operational Amplifiers/Buffers
5
Instrumentation Amplifiers
6
SSM Audio Products
7
Voltage Comparators
8
Matched Transistors
9
~
Contains definitions, selection
principles, AC & DC considerations,
and Selection Guide based on
12 parameters.
Table of Contents
~
Voltage References
10
Digital-to-Analog Converters
11
Analog-to-Digital Converters
12
Analog Switches/Multiplexers
13
Sample-and-Hold Amplifiers/Special Functions
14
Communications Products
15
Package Information
16
Sales Offices, Representatives and Distributors
17
--------=-
-=======
Contains definitions and
DC error calculations for standard
inverting and noninverting
configurations.
For your copy, contact your local PMl sales office, representative, or distributor.
Also, ask about PMl's Precision Decisions catalog-on-a-disk.
223
Copyright© 1990
Precision Monolithics Inc.
Precision Monolithics Inc.
Life Support and Nuclear Facility Applications Policy
PMI reserves the right to make changes to the product in this data
book to improve performance, reliability, or manufacturability. Consequently, contact PMI for the latest available specifications and performance data.
As a general policy, Precision Monolithics Inc. (PMI) does not recommend the use of any of its products in (a) life support (i.e., critical
medical) applications where failure or malfunction of the PMI product
can be reasonably expected to cause failure of the life support device
or to significantly affect its safety or effectiveness, or (b) any nuclear
facility applications. PMI will not knowingly sell its products for use in
such applications unless it receives in writing assurances satisfactory
to PMI that (a) the risks of injury or damage have been minimized (b)
the customer assumes all such risks, and (c) the liability of PMI is
adequately protected under the circumstances.
Although every effort has been made to ensure accuracy of the
information contained in this data book, PMI assumes no responsibility for inadvertent errors.
PMI assumes no responsibility for the use of any circuits described
herein and makes no representation that they are free of patent
infringement.
Following is the most current list of PMl's trade marks, registered
trade marks, and service marks.
The products in this catalog may be manufactured under one or more
of the following patents: 4,055,773; 4,056,740; 4,068,254; 4,088,905;
4,092,639; 4,109,215; 4,118,699; 4,131,884; 4,138,671; 4,142,117;
4,168,528; 4,210,830; 4,228,367; 4,260,911; 4,272,656; 4,285,051;
4,333,047; 4,340,851 ;4,374,335; 4,404,529; 4,444,309; 4,449,067;
4,454,413; 4,471,320; 4,471,321; 4,503,381; 4,538,115; 4,542,349;
4,560,947; 4,572,975; 4,583,051; 4,633,165; 4,675,561; 4,677,369;
4,683,423; 4,687,984; 4,737,281; 4,757,274; other patents pending.
~IPMD
Audio Silicon Specialists™
COMDAC~
TRICEpsM
TrimDACTM
Publication Team
Project Coordinator:
Graphic Production/Coordination:
Cover Design:
Technical Editor:
_ Project Production Team:
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Scot Realth
Elizabeth Brown
Deitrich Baltzer
Jeff Fasbinder
David Okada
Jan Schwartz
Technical Coordinator:
Technical Contribution:
224
Dan Parks
Gary Adrig
Derek Bowers
Tom Cate
Irene Chitwood
Ron Dow
Jim Hauer
Walt Heinzer
Art Kapoor
Dan Musso
Arman Naghavi
AI Neves
Dan Parks
Donn Soderquist
James Wong
Jerry Zis
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