1990_Philips_IC01a_Radio 1990 Philips IC01a Radio
User Manual: 1990_Philips_IC01a_Radio
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INTEGRATED
CIRCUITS
m
m
C)
u
Radio, audio and
associated systems
Bipolar, MOS
. CA3089 to lOA 151 OA
-
~
0
0
CD
Philips Components
PHILIPS
__._._"--_
-------------------_.
.......
~
~'
I
I
RADIO, AUDIO AND ASSOCIATED SYSTEMS
BIPOLAR, MOS
Part a
page
Selection guide
Functional index ........................................ .
Numerical index ................................................... .
Maintenance type list ............................................... .
5
17
31
General
Product status definition for type numbers
with prefixes CA, MC, NE, SA, SE and JlA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering information for type numbers with
prefixes CA, MC, NE, SA, SE and JlA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Type designation for type numbers with prefixes
HEF, MAB, MAF, OM, PCA, PCB, PCF, PNA,
SAA, SAD, SAF, TDA, TDB, TOO, TEA and TSA . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rating systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Handling MaS devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
36
39
41
43
Device data
CA3089 to TDA 1510A
Part b
Selection guide
Functional index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Numerical index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance type list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
page
953
965
979
Device data
TDA 1512 to JlA 758N
Package information
Package outlines for prefixes CA, MC, NE, SA, SE and JlA . . . . . . . . . . . . . . . . . . .
Package outlines for prefixes HEF, MAB, MAF, OM, PCA,
PCB, PCF, PNA, SAA, SAD, SAF, TDA, TDB, TOO, TEA and TSA . . . . . . . . . . . . . .
1839
1847
Soldering information
For type numbers with prefixes HEF, MAB, MAF, OM, PCA,
PCB, PCF, PNA, SAA, SAD, SAF, TDA, TDB, TOO, TEA and TSA . . . . . . . . . . . . . .
1887
SELECTION GUIDE
Functional index
Numerical index
Maintenance type list
FUNCTIONAL
INDEX
FUNCTIONAL INDEX
type no.
page
description
AMPLIFIERS
NE542
NE5532
NE5532A
NE5533
NE5533A
NE5534
NE5534A
SA5534
SA5534A
SE5532
SE5532A
SE5534
SE5534A
TDA1010A
TDA10ll
TDA1013B
TDA1015
TDA1015T
TDA1016
TDA1020
TDA1510
TDA1510A
TDA1512
TDA1512Q
TDA1514A
TDA1515B
TDA1516Q
TDA1517
TDA1518Q
TDA1519
TDA1519A
TDA1519B
TDA1520B
TDA1520BQ
TDA1521
TDA1521A
TDA1521Q
dual low-noise preamplifier
internally-compensated dual low noise operational amplifier
internally-compensated dual low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
internally-compensated dual low noise operational amplifier
internally-compensated dual low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
6 W audio power amplifier for in-car applications/l0 W
audio power amplifier for mains-fed applications
2 to 6 W audio power amplifier with preamplifier
4 W audio power amplifier with DC volume control
1 to 4 W audio power amplifier with preamplifier
0.5 W audio power amplifier with preamplifier
2 W recording/playback audio power amplifier with
preamplifier, automatic level control, short-circuit
and thermal protection
12 W audio power amplifier with preamplifier for car radios
24 W BTL or 2 x 12 W stereo car radio power amplifier
24 W BTL or 2 x 12 W stereo car radio power amplifier
12 to 20 W hi-fi audio power amplifier
12 to 20 W hi-fi audio power amplifier
50 W hi-fi power amplifier for digital audio (e.g. Compact Disc)
24 W BTL or 2 x 12 W stereo car radio power amplifier
22 W BTL or 2 x 11 W stereo car radio power amplifier;
closed loop voltage gain 26 dB
2 x 6 W stereo car radio audio power amplifier (20 dB gain)
22 W BTL or 2 x 11 W stereo car radio power amplifier;
closed loop voltage gain 46 dB
2 x 6 W stereo car radio audio power amplifier (40 dB gain)
22 W BTL or 2 x 11 W stereo car radio power amplifier
12 W BTL or 2 x 6 W stereo car radio power amplifier
20 W hi-fi audio power amplifier; complete SOAR protection
20 W hi-fi audio power amplifier; complete SOAR protection
2 x 12 W hi-fi stereo audio power amplifier
2 x 6 W hi-fi stereo audio power amplifier
2 x 12 W hi-fi stereo audio power amplifier
91
129
129
135
135
135
135
135
135
129
129
135
135
811
829
841
849
859
865
871
941
941
983
983
989
997
1003
1011
1019
1027
1035
1045
1055
1055
1061
1071
1061
' ] (AUgUst 1989
5
FUNCTIONAL
INDEX
l
_
'-----------------------------------------------------------------type no.
description
page
TDA1522
TDA1535
TDA1579
TDA1579T
TDA1589
TDA2611A
TDA2613
TDA7050
stereo playback amplifier/equalizer with mute switch
high-speed sample-and-hold amplifier
traffic warning decoder circuit (AM carriers); ARI system
traffic warning decoder circuit (AM carriers); AR I system
traffic control message and warning tone circuit; AR I system
5 W audio power amplifier
6 W hi-fi audio power amplifier
150 mW BTL or 2 x 75 mW stereo audio power amplifier;
low voltage
150 mW BTL or 2 x 75 mW stereo audio power amplifier;
low voltage
1 W BTL mono audio amplifier for portable applications
2 x 1 W BTL stereo audio power amplifier for portable applications
1081
1125
1231
1231
1241
1305
1315
hi-fi stereo audio processor; 12 C-bus
hi-fi stereo audio processor; 12 C-bus
hi-fi stereo audio processor; 12 C-bus
car radio preamplifier and source selector with sound
and fader controls; 12 C-bus
car radio preamplifier and source selector with sound
and fader controls; 12 C-bus
sound fader control circuit; 12 C-bus
1445
1467
1489
signal-source switch (4 x two channels)
dual tandem electronic potentiometer circuit
stereo tone/volume control circuit
stereo tone/volume control circuit
multi-function oscillator switch for audio cassette recorders
spatial, stereo and pseudo-stereo sound circuit
equalizer for audio cassette recorders
877
931
1091
1103
1293
1335
1589
TDA7050T
TDA7052
TDA7053
1423
1427
1431
1437
AUDIO ICs
Bus-controlled
TDA8420
TDA8421
TDA8425
TEA6300
TEA6300T
TEA6310T
1787
1787
1803
DC-controlled
TDA1029
TDA1074A
TDA1524A
TDA1525
TDA1600
TDA3810
TDD1601
CLOCK/CALENDAR
clock calendar; 12 C-bus
clock calendar with 256 x 8-bit static RAM;
PCF8573
PCF8583
2
1
C-bus
329
491
COMPANDOR
NE570
NE571
NE572
NE575
SA571
SA572
6
August
compandor
compandor
programmable analogue compandor
low voltage compandor
compandor
programmable analogue compandor
19891 (
95
95
103
111
95
103
~___J
type no.
FUNCTIONAL
INDEX
description
page
10-bit high-speed mUltiplying DAC
10-bit high-speed multiplying DAC
10-bit high-speed multiplying DAC
1O-bit high-speed multiplying DAC
8-bit ADC/DAC; 12 C-bus
7-bit ADC; 22 MHz; 3-state output
8-bit multiplying DAC; 30 MHz
stereo DAC for Compact Disc
10-bit high-speed mUltiplying DAC
14-bit ADC
dual 16-bit DAC
dual 16-bit economy DAC (PS bus format)
octuple 6-bit DAC; 12 C-bus
83
83
83
119
509
527
539
757
119
1117
1129
1145
1511
DATA CONVERSION
ADCs, DACs
MC3410
MC3410C
MC3510
NE5410
PCF8591
PNA7509
PNA7518
SAA7320
SE5410
TDA1534
TDA1541A
TDA1543
TDA8444
DIGITAL AUDIO
Compact Disc
SAA7210
SAA7220
SAA7310
SAA7320
SAD7630
TDA1514A
TDA1541A
TDA1542
TDA1543
TDA5708
TDA5709
TDA8808T
TDA8808AT
TDA8808T / A T
TDA8809T
TDA8809T
671
693
727
757
decoder for Compact Disc (second generation)
digital filter and interpolator for Compact Disc (second generation)
decoder for Compact Disc (third generation)
stereo DAC for Compact Disc
CCD delay line for error correction in video and sound
carrier timebases (Iaservision players)
50 W hi-fi power amplifier for digital audio (e.g. Compact Disc)
dual 16-bit DAC
active element for post filtering (dual channel)
dual 16-bit economy DAC (1 2 S bus format)
photo diode signal processor for Compact Disc
single-spot read-out systems
radial error signal processor for Compact Disc
photo diode signal processor for Compact Disc
photo diode signal processor for Compact Disc
transfer functions
radial error signal processor for Compact Disc
transfer functions
777
989
1129
1137
1145
1347
1367
1519
1519
1539
1559
1571
Input circuits
SAA7274
TDA1542
audio digital input circuit (ADIC)
active element for post filtering (dual channel)
715
1137
1(AUgust
1989
7
FUNCTIONAL
INDEX
l
'----------------------------------------------------------------
type no.
description
page
DISPLAY DRIVERS
PCF1303T
PCF2100
PCF2110
PCF2111
PCF2112
PCF2201
PCF8566
PCF8576
PCF8577
PCF8577A
PCF8578
PCF8579
SAA1064
18-element bar graph LCD driver (with analogue input)
LCD duplex driver; 40 segments
LCD duplex driver; 60 segments and 2 LEDs
LCD duplex driver; 64 segments
LCD driver; 32 segments
LCD flat panel row/column driver
universal LCD driver for low multiplex rates
(1:1 to 1 :4); max. 96 elements; 12 C-bus
universal LCD driver for low multiplex rates
(1:1 to 1 :4); max. 160 segments; 12 C-bus
LCD direct driver (32 segments) or duplex driver
(64 segments); 12 C-bus
LCD direct driver (32 segments) or duplex driver
(64 segments); 12 C-bus; different slave address
LCD row/column driver for dot matrix graphic displays;
40 outputs, of which 24 are programmable; 12 C-bus
LCD column driver for dot matrix graphic displays;
40 column outputs; 12 C-bus
4-digit LED driver; 12 C-bus
223
229
229
229
229
245
289
359
393
393
409
447
555
DOLBY CIRCUITS
NE645
NE646
NE649
NE650
NE5240
TEA0651
TEA0652
TEA0653T
TEA0654
TEA0657
TEA0665
TEA0665T
TEA0666
TEA0666T
TEA0670T
Dolby Band C type noise reduction circuit
Dolby Band C type noise reduction circuit
low voltage Dolby B type noise reduction circuit
Dolby B type noise reduction circuit
Dolby digital audio decoder
Dolby B & C noise reduction circuit
Dolby B & C noise reduction circuit
stereo or 2-channel Dolby B noise reduction circuit
preamplifier and electronic switch for Dolby B & C
noise reduction circuits
dual Dolby B noise reduction circuit
Dolby B & C processor with preamplifier and electronic switch
Dolby B & C processor with preamplifier and electronic switch
Dolby B & C processor with preamplifier and electronic switch;
changed frequency response in relation to TEA0665
Dolby B & C processor with preamplifier and electronic switch;
changed frequency response in relation to TEA0665
Dolby B & C processor with preamplifier and electronic switch;
low voltage
179
179
185
191
115
1627
1627
1645
1627
1651
1659
1659
1669
1669
1679
FREQUENCY SYNTHESIZERS
HEF4750V
SAA1057
TDD1742T
TSA6057
TSA6057T
8
frequency synthesizer
radio tuning PLL frequency synthesizer (SYMO II)
low power frequency synthesizer (LOPSY)
radio tuning PLL frequency synthesizer; 12 C-bus
radio tuning PLL frequency synthesizer; 12 C-bus
August 19891 (
53
545
1605
1821
1821
FUNCTIONAL
INDEX
type no.
page
description
INTERFERENCE SUPPRESSORS
TDA 1001 B
TDA1001BT
interference and noise suppression circuit for FM receivers
interference and noise suppression circuit for FM receivers
801
801
MEMORIES
PCF8570
PCF8570C
PCF8571
PCF8582A
256
256
128
256
x
x
x
x
319
319
319
481
8-bit static RAM; 12 C-bus
8-bit static RAM; 12 C-bus; different slave address
8-bit static RAM; 12 C-bus
8-bit EEPROM; 12 C-bus; -40 to +85 0C
MICROCONTROLLERS (8-bit)
8051/80C51 family CMOS
PCA80C31 BH-3
PCA80C51 B H-3
PCA80C552
PCA80C562
PCA80C652
PCA83C552
PCA83C562
PCA83C652
PCA83C654
PCB80C31 BH-3
PCB80C31 BH-3
PCB80C51 BH-3
PCB80C51 BH-3
microcontroller; 128 x 8 RAM; 1.2 to 12 MHz;
-40 to + 125 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
1.2 to 12 MHz; -40 to + 125 °C
microcontroller; 256 x 8 RAM; 80C31 CPU plus 16-bit
capture/compare timer/counter; watch-dog timer;
2 pUlse-width modulated signals; 10-bit ADC with
8 multiplexed input lines; 12 C-bus; 1.2 to 12 MHz;
-40 to + 125 °C
microcontroller; 256 x 8 RAM; 80C31 CPU plus 16-bit
capture/compare timer/counter; watch-dog timer;
2-pulse-width modulated signals; 8-bit ADC with 8 multiplexed
input lines; 1.2 to 12 MHz; -40 to + 125 °C
microcontroller; 256 x 8 RAM; serial I/O; UART;
12 C-bus; 1.2 to 12 MHz; -40 to + 125 °C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU
plus 16-bit capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 10-bit ADC with 8 multiplexed
input lines; 12 C-bus; 1.2 to 12 MHz; -40 to + 125 oC
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU
plus 16-bit capture/compare timer/counter; watch-dog timer;
2-pulse-width modulated signals; 8 multiplexed input lines;
1.2 to 12 MHz; -40 to + 125 0C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; -40 to + 125 °C
microcontroller; 256 x 8 RAM; 16K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; -40 to + 125 °C
microcontroller; 128 x 8 RAM; 0.5 to 12 MHz; 0 to +70 °C
microcontroller; 128 x 8 RAM; 1.2 to 16 MHz; 0 to +70 0C
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
0.5 to 12 MHz; 0 to + 70 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
1.2 to 16 MHz; 0 to + 70 0C
1
(AUgust 1989
209
209
213
215
217
213
215
217
219
209
209
209
209
9
FUNCTIONAL
INDEX
type no.
description
page
8051/80C51 family CMOS (continued)
PCB80C552
microcontroller; 256 x 8 RAM; 80C31 CPU plus
l6-bit capture/compare timer/counter; watch-dog timer;
two pulse-width modulated signals; 10-bit ADC with
8 multiplexed input lines; 12 C-bus; 1.2 to 12 MHz;
o to + 70 °C
microcontroller; 256 x 8 RAM; 80C31 CPU plus 16-bit
capture/compare timer/counter; watch-dog timer;
2 pUlse-width modulated signals; 8-bit ADC with
8 multiplexed input lines; 1.2 to 12 MHz; 0 to + 70 °C
microcontroller; 256 x 8 RAM; serial I/O; UART; 12 C-bus;
1.2 to 12 MHz; 0 to +70 0C
microcontroller; 128 x 8 RAM; 256 x 8 EEPROM;
1.2to12MHz;Oto+70 o C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU
plus 16-bit capture/compare timer/counter; watch-dog timer;
two pUlse-width modulated signals; 10-bit ADC with
8 multiplexed input lines; 12 C-bus; 1.2 to 12 MHz; 0 to +70 °C
micrbcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU
plus 16-bit capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 8 multiplexed input lines;
1.2to12MHz;Oto+70 o C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz;Oto+70 o C
microcontroller; 256 x 8 RAM; 16K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; 0 to + 70 0C
microcontroller; 128 x 8 RAM; 4K x 8 ROM; 256 x 8 EEPROM;
1.2 to 12 MHz; 0 to +70 °C
microcontroller; 128x8 RAM; 1.2to 12 MHz;
-40 to + 85 0C
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
1.2 to 12 MHz; -40 to +85 0C
microcontroller; 256 x 8 RAM; 80C31 CPU plus 16-bit
capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 10-bit ADC with 8 multiplexed
input lines; 12 C-bus; 1.2 to 12 MHz; -40 to +85 °C
microcontroller; 256 x 8 RAM; 80C31 CPU plus 16-bit
capture/compare timer/counter; watch-dog timer; 2 pulse-width
modulated signals; 8-bit ADC with 8 multiplexed input lines;
1.2 to 12 MHz; -40 to +85 °c
microcontroller; 256 x 8 RAM; serial I/O; UART; 12 C-bus;
1.2 to 12 MHz; -40 to +85 0C
microcontroller; 128 x 8 RAM; 256 x 8 EEPROM;
1.2 to 12 MHz; -40 to +85 °c
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU plus
16-bit capture/compare timer/counter; watch-dog timer;
2 pUlse-width modulated signals; 10-bit ADC with 8 multiplexed
input lines; 12 C-bus; 1.2 to 12 MHz; -40 to + 85 °C
PCB80C562
PCB80C652
PCB80C851
PCB83C552
PCB83C562
PCB83C652
PCB83C654
PCB83C851
PCF80C31BH-3
PCF80C51 BH-3
PCF80C552
PCF80C562
PCF80C652
PCF80C851
PCF83C552
10
1(
August 1989
213
215
217
221
213
215
217
219
221
209
209
213
215
217
221
213
FUNCTIONAL
INDEX
page
type no.
description
PCF83C562
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU
plus 16-bit capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 8 multiplexed input lines;
1.2 to 12 MHz; -40 to +85 °C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; serial I/O; UART;
12 C-bus; 1.2 to 12 MHz; -40 to + 85 0C
microcontroller; 256 x 8 RAM; 16K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; -40 to +85 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM; 256 x 8 EEPROM;
1.2 to 12 MHz; -40 to +85 °C
PCF83C652
PCF83C654
PCF83C851
215
217
219
221
84CXX family CMOS
PCF84COO
PCF84C12
PCF84C21
PCF84C22
PCF84C41
PCF84C42
PCF84C81
PCF84C85
microcontroller; 256 x 8 RAM; bond-out version
PCF84CXX family; 12 C-bus
low cost microcontroller; 64 x 8 RAM; 1K x 8 ROM
microcontroller; 64 x 8 RAM; 2K x 8 ROM; plus 8-bit
LED driver; 12 C-bus; -40 to + 85 0C
low cost microcontroller; 64 x 8 RAM; 1K x 8 ROM
microcontroller; 128 x 8 RAM; 4K x 8 ROM; plus 8-bit
LED driver; 12 C-bus; -40 to +85 0C
low cost microcontroller; 64 x 8 RAM; 4K x 8 ROM
microcontroller; 256 x 8 RAM; 8K x 8 ROM; plus 8-bit
LED driver; 12C-bus; -40 to +85 °c
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 32 I/O;
plus 8-bit LED driver; 12 C-bus; -40 to + 85 0C
283
285
283
285
283
285
283
287
84XX family NMOS
MAB8401
MAB8411
MAB8421
MAB8422
MAB8441
MAB8442
MAB8461
microcontroller; 128 x 8 RAM; piggy-back version for
MAB84XX family plus 8-bit LED driver; 12 C-bus;
1.0 to 6 MHz; 0 to + 70 0C
microcontroller; 64 x 8 RAM; 1K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 6 MHz; 0 to + 70 0C
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 6 MHz; 0 to + 70 °C
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12 C-bus;
1.0 to 6 MHz; 0 to +70 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.6 to 6 MHz; 0 to + 70 0c
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12 C-bus;
1.6 to 6 MHz; 0 to +70 0C
microcontroller; 128 x 8 RAM; 6K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus
1.0 to 6 MHz; 0 to + 70 °C
1(
79
79
79
81
79
81
79
Augus' 1989
11
FUNCTIONAL
INDEX
type no.
description
84XX family NMOS (continued)
microcontroller; 64 x 8 RAM; 1K x 8 ROM;
MAF84All
plus 8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 5 MHz; -40 to + 110 °c
MAF84A21
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 5 MHz; -40 to + 110 °C
MAF84A22
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12C-bus;
1.0 to 5 MHz; -40 to + 110 0C
MAF84A41
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 5 MHz; -40 to + 110 °C
MAF84A42
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12 C-bus;
1.0 to 5 MHz; -40 to + 110 0C
MAF84A61
microcontroller; 128 x 8 RAM; 6K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 5 MHz; -40 to + 110 °C
MAF8411
microcontroller; 64 x 8 RAM; 1K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 6 MHz; -40 to +85 °c
MAF8421
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 6 MHz; -40 to +85 0C
MAF8422
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12 C-bus
1.0 to 6 MHz; -40 to +85 0C
MAF8441
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 6 MHz; -40 to +85 0C
MAF8442
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12 C-bus;
1.0 to 6 MHz; -40 to +85 °C
MAF8461
microcontroller; 128 x 8 RAM; 6K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 6 MHz; -40 to +85 °C
page
79
79
81
79
81
79
79
79
81
79
81
79
8048 family CMOS
PCA80C39
PCA80C49
PCB80C39
PCB80C49
PCF80C39
PCF80C49
12
August
microcontroller; 128 x 8 RAM; 1.0 to 15 MHz;
-40 to + 110 0C
microcontroller; 128 x 8 RAM; 2K x 8 ROM;
1.0 to 15 MHz; -40 to + 110 0C
microcontroller; 128 x 8 RAM; 1.0 to 15 MHz;
o to +70 °c
microcontroller; 128 x 8 RAM; 2K x 8 ROM;
1.0 to 15 MHz; 0 to + 70 0C
microcontroller; 128 x 8 RAM; 1.0 to 15 MHz;
-40 to +85 0C
microcontroller; 128 x 8 RAM; 2K x 8 ROM;
1.0 to 15 MHz; -40 to +85 °C
19891 (
211
211
211
211
211
211
FUNCTIONAL
INDEX
type no.
page
description
MOTOR CONTROLLERS
TDA1059B
TDA5040T
motor speed regulator with thermal shut-down;
multiplication coefficient = 9; drop-out voltage = 1.8 V
DC motor drive circuit with magnetic-field detector
891
1339
PERSONAL RADIO/AUDIO
TDA7000
TDA7010T
TDA7021 T
TDA7030T
TDA7040T
TDA7050
TDA7050T
TDA7052
TDA7053
TEA0670T
TEA5551T
FM radio circuit; mono (in plastic DIL-18)
FM radio circuit; mono (in SO-16 plastic mini-pack)
FM radio circuit; stereo/mono; for low voltage
micro tuning system (MTS)
low voltage micro tuning system (MTS)
PLL stereo decoder; low voltage
150 mW BTL or 2 x 75 mW stereo audio power amplifier;
low voltage
150 mW BTL or 2 x 75 mW stereo audio power amplifier;
low voltage
1 W BTL mono audio amplifier for portable applications
2 x 1 W BTL stereo audio power amplifier for portable applications
Dolby B & C processor preamplifier and electronic switch;
low voltage
single-chip AM radio circuit, plus dual AF amplifier,
for pocket receivers with headphones
1381
1389
AM receiver circuit for hi-fi and car radio
AM receiver circuit for hi-fi and car radio
AM receiver circuit for stereo hi-fi and car radio
AM receiver circuit for stereo hi-fi and car radio
I F limiting amplifier, FM detector and audio amplifier
I F limiting amplifier, FM detector and audio amplifier
AM upconversion radio receiver; 10.7 MHz IF
897
913
1153
1171
1583
1583
1775
AM/FM radio receiver circuit
AM/FM radio receiver circuit
1697
1733
FM IF system
high performance low-power FM I F system
low-power FM I F system
low-power FM I F system
high performance low-power FM I F system
low-power F M I F system
low-power F M I F system
integrated FM tuner for radio receivers
integrated FM tuner for radio receivers
FM/I F amplifier and detector
47
149
159
169
149
159
169
1187
1195
1205
1397
1407
1415
1423
1427
1431
1437
1679
1685
RADIO RECEIVERS
AM
TDA1072A
TDA1072AT
TDA1572
TDA1572T
TDB1080
TDB1080T
TEA6200
AM/FM
TEA5570
TEA5591
FM
CA3089
NE604A
NE605
NE614A
SA604A
SA605
SA614A
TDA1574
TDA1574T
TDA1576
1(
August 1989
13
FUNCTIONAL
INDEX
type no.
description
page
FM/ I F amplifier and detector
FM/I F amplifier and detector
FM radio circuit; mono (in plastic OIL-18)
FM radio circuit; mono (in SO-16 plastic mini-pack)
FM radio circuit; stereo/mono; for low voltage
micro tuning system (MTS)
FM/I F system and microcomputer-based tuning
interface; 12 C-bus
1249
1267
1381
1389
FM (continued)
TOA1596
TOA1596T
TOA7000
TOA7010T
TOA7021T
TEA6100
1397
1751
REMOTE CONTROLLERS
SAA3004
SAA3006
SAA3007
SAA3008
SAA3009
SAA3010
SAA3028
SAA3049
SAF1032
SAF1039
TOA3047
TOA3048
high performance transmitter (455 kHz) for infrared
remote control; up to 448 commands
high performance transmitter (RC-5) for infrared
remote control; up to 2048 commands
high performance transmitter (455 kHz) for infrared
remote control; up to 1280 commands; low voltage
high performance transmitter (38 kHz) for infrared
remote control; low voltage
infrared remote control decoder; decodes 64 commands
(RECS80/RC-5); up to 32 subaddresses; high current
output capability for direct LED drive
high-performance transmitter (RC-5) for infrared remote
control; low voltage
high performance transcoder (RC-5) for infrared remote
control; 12 C-bus
infrared remote control decoder, low current version
of SAA3009
receiver/decoder for infrared remote control
transmitter for infrared remote control
high performance receiver for infrared remote control;
positive output voltage
high performance receiver for infrared remote control;
negative output voltage
585
595
609
623
637
647
663
637
787
787
1323
1329
REMOTE I/O EXPANDERS
PCF8574
PCF8574A
remote 8-bit I/O expander; 12 C-bus
remote 8-bit I/O expander; 12 C-bus; different slave address
347
347
SOUND GENERATOR
SAA1099
stereo sound generator for sound effects and music synthesis
(J.LC-CO ntro lied)
565
SPEECH SYNTHESIZERS
OM8200
OM8201
OM8209
OM8210
PCF8200
14
August
speech demonstration board (PCF8200)
speech demonstration box (PCF8200)
update package for OM8010
speech analysis/editing system (PCF8200)
voice synthesizer (CMOS); 12 C-bus
19891 (
197
201
203
205
267
FUNCTIONAL
INDEX
type no.
description
page
time multiplex PLL stereo decoder for hi-fi and car radios
time multiplex PLL stereo decoder for hi-fi and car radios
PLL stereo decoder; low voltage
PLL stereo decoder for medium-fi and car radios
PLL stereo decoder with source selector switch for
medium-fi and car radios
PLL stereo decoder with source selector switch for
medium-fi and car radios
radio tuning PLL frequency synthesizer; 12 C-bus
radio tuning PLL frequency synthesizer; 12 C-bus
FM stereo multiplex decoder; PLL
1217
1285
1415
1711
frequency synthesizer
universal divider
double-balanced mixer and oscillator
double balanced mixer and oscillator
double-balanced mixer and oscillator
radio tuning PLL frequency synthesizer (SYMO II)
tuner switching circuit; 12 C-bus
integrated FM tuner for radio receivers
integrated FM tuner for radio receivers
low voltage micro tuning system (MTS)
low power frequency synthesizer (LOPSY)
53
69
143
163
143
545
581
1187
1195
1407
1605
STEREO DECODERS
TDA1578A
TDA1598
TDA7040T
TEA5580
TEA5581
TEA5581T
TSA6057
TSA6057T
J,LA758
1721
1721
1821
1821
1831
TUNING CIRCUITS
HEF4750V
HEF4751V
NE602
NE612
SA602
SAA1057
SAA1300
TDA1574
TDA1574T
TDA7030T
TDD1742T
1(AUgust
1989
15
NUMERICAL
INDEX
NUMERICAL INDEX
page
type no.
description
CA3089N
HEF4750VD
HEF4750VU
HEF4751VD
HEF4751VP
HEF4751VT
HEF4751VU
MAB8401B
FM IF system
frequency synthesizer
frequency synthesizer
universal divider
universal divider
universal divider
universal divider
microcontroller; 128 x 8 RAM; piggy-back version
for MAB84XX family plus 8-bit LED driver; 12 C-bus;
1.0 to 6 MHz; 0 to + 70 oC
microcontroller; 128 x 8 RAM; piggy-back version
for MAB84XX family plus 8-bit LED driver; 12 C-bus;
1.0 to 6 MHz; 0 to + 70 0C
microcontroller; 64 x 8 RAM; 1K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 6 MHz; 0 to + 70 0C
microcontroller; 64 x 8 RAM; 1K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 6 MHz; 0 to + 70 °C
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LE D driver; 20 I/O lines; 12 C-bus;
1.0 to 6 MHz; 0 to + 70 Oc
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 6 MHz; 0 to + 70 oC
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12C-bus;
1.0 to 6 MHz; 0 to + 70 oC
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 6 MHz; 0 to + 70 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 6 MHz; 0 to + 70 oC
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12C-bus;
1.0 to 6 MHz; 0 to + 70 oC
microcontroller; 128 x 8 RAM; 6K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 6 MHz; 0 to + 70 °C
microcontroller; 128 x 8 RAM; 6K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 6 MHz; 0 to + 70 °C
MAB8401WP
MAB8411P
MAB8411T
MAB8421P
MAB8421T
MAB8422P
MAB8441P
MAB8441T
MAB8442P
MAB8461P
MAB8461T
'1
47
53
53
69
69
69
69
79
79
79
79
79
79
81
79
79
81
79
79
(AUgust 1989
17
NUMERICAL
INDEX
type no.
description
MAF84AllP
microcontroller; 64 x 8 RAM; 1 K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 5 MHz; -40 to + 110 °C
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 5 MHz; -40 to + 110 0C
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12C-bus;
1.0 to 5 MHz; -40 to + 110 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 5 MHz; -40 to + 110 0C
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12C-bus;
1.0 to 5 MHz; -40 to + 110 °C
microcontroller; 128 x 8 RAM; 6K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 5 MHz; -40 to + 110 °C
microcontroller; 64 x 8 RAM; 1 K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12C-bus;
1.0 to 6 MHz; -40 to +85 °C
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 6 MHz; -40 to + 85 °C
microcontroller; 64 x 8 RAM; 2K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12C-bus;
1.0 to 6 MHz; -40 to + 85 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 6 MHz; -40 to +85 0C
microcontroller; 128 x 8 RAM; 4K x 8 ROM plus
8-bit LED driver; 15 I/O lines; 12C-bus;
1.0 to 6 MHz; -40 to + 85 0C
microcontroller; 128 x 8 RAM; 6K x 8 ROM plus
8-bit LED driver; 20 I/O lines; 12 C-bus;
1.0 to 6 MHz; -40 to + 85 0C
10-bit high-speed multiplying DAC
10-bit high-speed multiplying DAC
10-bit high-speed mUltiplying DAC
dual low-noise preamplifier
compandor
compandor
compandor
compandor
compandor
programmable analogue compandor
programmable analogue compandor
low voltage compandor
low voltage compandor
Dolby digital audio decoder
MAF84A21P
MAF84A22P
MAF84A41P
MAF84A42P
MAF84A61P
MAF8411P
MAF8421P
MAF8422P
MAF8441P
MAF8442P
MAF8461P
MC3410F
MC3410CF
MC3510F
NE542N
NE570F
NE570N
NE571D
NE571F
NE571N
NE572D
NE572N
NE575D
NE575N
NE5240D
18
August
19891 (
page
79
79
81
79
81
79
79
79
81
79
81
79
83
83
83
91
95
95
95
95
95
103
103
111
111
115
NUMERICAL
INDEX
type
description
NE5240N
NE5410F
NE5532D
NE5532N
NE5532FE
NE5532AN
NE5532AFE
NE5533D
NE5533N
NE5533AD
NE5533AN
NE5534D
NE5534N
NE5534FE
NE5534AD
NE5534AN
NE5534AFE
NE602D
NE602N
NE602FE
NE604AD
NE604AN
NE605D
NE605F
NE605N
NE612D
NE612N
NE614AD
NE614AN
NE645N
NE646N
NE649N
NE650N
OM8200
OM8201
OM8209
OM8210
PCA80C31 BH-3P
Dolby digital audio decoder
10-bit high-speed multiplying DAC
internally-compensated dual low noise operational
internally-compensated dual low noise operational
internally-compensated dual low noise operational
internally-compensated dual low noise operational
internally-compensated dual low noise operational
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
double-balanced mixer and oscillator
double-balanced mixer and oscillator
double-balanced mixer and oscillatoe
high performance low-power FM I F system
high performance low-power F M I F system
low-power F M I F system
low-power F M I F system
low-power F M I F system
double-balanced mixer and oscillator
double-balanced mixer and oscillator
low-power F M I F system
low-power F M I F system
Dolby Band C type noise reduction circuit
Dolby Band C type noise reduction circuit
low voltage Dolby B type noise reduction circuit
Dolby B type noise reduction circuit
speech demonstration board (PCF8200)
speech demonstration box (PCF8200)
update package for OM801 0
speech analysis/editing system (PCF8200)
microcontroller; 128 x 8 RAM; 1.2 to 12 MHz;
-40 to + 125 °C
microcontroller; 128 x 8 RAM; 1.2 to 12 MHz;
-40 to + 125 °C
microcontroller; 128 x 8 RAM; 1.0 to 15 MHz;
-40 to + 110 °c
microcontroller; 128 x 8 RAM; 1.0 to 15 MHz;
-40 to + 110 °C
microcontroller; 128 x 8 RAM; 2K x 8 ROM;
1.0 to 15 MHz; -40 to + 110 °C
microcontroller; 128 x 8 RAM; 2K x 8 ROM;
1.0 to 15 MHz; -40 to + 110 °C
PCA80C31 BH-3WP
PCA80C39P
PCA80C39WP
PCA80C49P
PCA80C49WP
page
115
119
129
129
129
129
129
135
135
135
135
135
135
135
135
135
135
143
143
143
149
149
159
159
159
163
163
169
169
179
179
185
191
197
201
203
205
amplifier
amplifier
amplifier
amplifier
amplifier
209
209
211
211
211
211
1(AUgust
1989
19
NUMERICAL
INDEX
l
'-------------------------------------------------------------
type
description
PCA80C51 BH-3P
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
1.2 to 12 MHz; -40 to + 125 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
1.2 to 12 MHz; -40 to + 125 0c
microcontroller; 256 x 8 RAM; 80C31 CPU plus
16-bit capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 10-bit ADC with
8 multiplexed input lines; 12 C-bus; 1.2 to 12 MHz;
-40 to + 125 0C
microcontroller; 256 x 8 RAM; 80C31 CPU plus
16-bit capture/compare timer/counter; watch-dog timer;
2 pUlse-width modulated signals; 8-bit ADC with
8 multiplexed input lines; 1.2 to 12 MHz;
-40 to + 125 0C
microcontroller; 256 x 8 RAM; serial I/O; UART;
2
1 C-bus; 1.2 to 12 MHz; -40 to + 125 0C
microcontroller; 256 x 8 RAM; serial I/O; UART;
12 C-bus; 1.2 to 12 MHz; -40 to + 125 0C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU
plus 16-bit capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 10-bit ADC with 8 multiplexed
input lines; 12 C-bus; 1.2 to 12 MHz; -40 to + 125 °C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU
plus 16-bit capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 8 multiplexed input lines;
1.2 to 12 MHz; -40 to + 125 0C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; -40 to + 125 0C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; -40 to + 125 °C
microcontroller; 256 x 8 RAM; 16K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; -40 to + 125 °C
microcontroller; 256 x 8 RAM; 16K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; -40 to + 125 0C
microcontroller; 128 x 8 RAM; 0.5 to 12 MHz;
o to + 70 0c
microcontroller; 128 x 8 RAM; 0.5 to 12 MHz;
o to + 70 0c
microcontroller; 128 x 8 RAM; 1.2 to 16 MHz;
o to + 70 0C
microcontroller; 128 x 8 RAM; 1.2 to 16 MHz;
o to + 70 0c
microcontroller; 128 x 8 RAM; 1.0 to 15 MHz;
Oto+70 o C
microcontroller; 128 x 8 RAM; 1.0 to 15 MHz;
o to + 70 0c
microcontroller; 128 x 8 RAM; 2K x 8 ROM;
1.0to15MHz;Oto+70 o C
microcontroller; 128 x 8 RAM; 2K x 8 ROM;
1.0to15MHz;Oto+70 o C
PCA80C51 BH-3WP
PCA80C552WP
PCA80C562WP
PCA80C652P
PCA80C652WP
PCA83C552WP
PCA83C562WP
PCA83C652P
PCA83C652WP
PCA83C654P
PCA83C654WP
PCB80C31 BH-3P
PCB80C31 BH-3WP
PCB80C31 BH-3P
PCB80C31 BH-3WP
PCB80C39P
PCB80C39WP
PCB80C49P
PCB80C49WP
20
August
19891 (
page
209
209
213
215
217
217
213
215
217
217
219
219
209
209
209
209
211
211
211
211
NUMERICAL
INDEX
page
type
description
PCB80C51 BH-3P
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
0.5 to 12 MHz; 0 to + 70 °c
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
0.5 to 12 MHz; 0 to + 70 °c
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
1.2to 16MHz;Oto+70 o C
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
1 .2 to 16 MHz; 0 to + 70 °c
microcontroller; 256 x 8 RAM; 80C31 CPU plus
16-bit capture/compare timer/counter; watch-dog timer;
two pUlse-width modulated signals; 10-bit ADC with
8 multiplexed input lines; 12 C-bus; 1.2 to 12 MHz;
o to + 70 °c
microcontroller; 256 x 8 RAM; 80C31 CPU plus
16-bit capture/compare timer/counter; watch-dog timer;
2 pUlse-width modulated signals; 8-bit ADC with
8 multiplexed input lines; 1.2 to 12 MHz; 0 to + 70 °c
microcontroller; 128 x 8 RAM; 256 x 8 EEPROM;
1.2 to 12 MHz; 0 to + 70 °C
microcontroller; 128 x 8 RAM; 256 x 8 EEPROM;
1 .2 to 12 MHz; 0 to + 70 °c
microcontroller; 256 x 8 RAM; serial I/O; UART;
12 C-bus; 1.2 to 12 MHz; 0 to + 70 °c
microcontroller; 256 x 8 RAM; serial I/O; UART;
12 C-bus; 1.2 to 12 MHz; 0 to + 70 °c
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU
plus 16-bit capture/compare timer/counter;
watch-dog timer; two pulse-width modulated signals;
10-bit ADC with 8 multiplexed input lines;
2
1 C-bus; 1.2 to 12 MHz; 0 to + 70 °c
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU
plus 16-bit capture/compare timer/counter; watch-dog timer;
2 pUlse-width modulated signals; 8 multiplexed input lines;
1.2 to 12 MHz; 0 to + 70 °c
microcontroller; 256 x 8 RAM; 8K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; 0 to + 70 °c
microcontroller; 256 x 8 RAM; 8K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; 0 to + 70 °C
microcontroller; 256 x 8 RAM; 16K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; 0 to + 70 °C
microcontroller; 256 x 8 RAM; 16K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; 0 to + 70 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM; 256 x 8 EEPROM;
1 .2 to 12 MHz; 0 to + 70 °c
microcontroller; 128 x 8 RAM; 4K x 8 ROM; 256 x 8 EEPROM;
1.2 to 12 MHz; 0 to + 70 0c
18-element bar graph LCD driver (with analogue input)
LCD duplex driver; 40 segments
LCD duplex driver; 40 segments
PCB80C51 BH-3WP
PCB80C51 BH-3P
PCB80C51 BH-3WP
PCB80C552WP
PCB80C562WP
PCB80C851P
PCB80C851WP
PCB80C652P
PCB80C652WP
PCB83C552WP
PCB83C562WP
PCB83C652P
PCB83C652WP
PCB83C654P
PCB83C654WP
PCB83C851P
PCB83C851 WP
PCF1303T
PCF2100P
PCF2100T
1
(AUgust
209
209
209
209
213
215
221
221
217
217
213
215
217
217
219
219
221
221
223
229
229
1989
21
NUMERICAL
INDEX
l
'--------------------------------------------------------
type
description
PCF2110P
PCF2110T
PCF2111P
PCF2111T
PCF2112P
PCF2112T
PCF2201V
PCF80C31 BH-3P
LCD duplex driver; 60 segments and 2 LEDs
LCD duplex driver; 60 segments and 2 LEDs
LCD duplex driver; 64 segments
LCD duplex driver; 64 segments
LCD driver; 32 segments
LCD driver; 32 segments
LCD flat panel row/column driver
microcontroller; 128 x 8 RAM; 1.2 to 12 MHz;
-40 to + 85 °C
microcontroller; 128 x 8 RAM; 1.2 to 12 MHz;
-40 to + 85 °C
microcontroller; 128 x 8 RAM; 1.0 to 15 MHz;
-40 to + 85 °C
microcontroller; 128 x 8 RAM; 1.0 to 15 MHz;
-40 to + 85 °c
microcontroller; 128 x 8 RAM; 2K x 8 ROM;
1.0 to 15 MHz; -40 to + 85 0c
microcontroller; 128 x 8 RAM; 2K x 8 ROM;
1.0 to 15 MHz; -40 to + 85 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
1.2 to 12 MHz; -40 to + 85 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM;
1.2 to 12 MHz; -40 to + 85 °C
microcontroller; 256 x 8 RAM; 80C31 CPU plus 16-bit
capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 10-bit ADC with
8 multiplexed input lines; 12 C-bus; 1.2 to 12 MHz;
-40 to + 85 °C
microcontroller; 256 x 8 RAM; 80C31 CPU plus 16-bit
capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 8-bit ADC with
8 multiplexed input lines; 1.2 to 12 MHz;
-40 to + 85 °C
microcontroller; 256 x 8 RAM; serial I/O; UART;
2
1 C-bus; 1.2 to 12 MHz; -40 to + 85 0C
microcontroller; 256 x 8 RAM; serial I/O; UART;
12 C-bus; 1.2 to 12 MHz; -40 to + 85 0C
microcontroller; 128 x 8 RAM; 256 x 8 EEPROM;
1.2 to 12 MHz; -40 to + 85 0C
microcontroller; 128 x 8 RAM; 256 x 8 EEPROM;
1.2 to 12 MHz; -40 to + 85 °C
voice synthesizer (CMOS); 12 C-bus
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU plus
16-bit capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 10-bit ADC with 8 multiplexed
input lines; 12 C-bus; 1.2 to 12 MHz; -40 to + 85 0C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 80C51 CPU
plus 16-bit capture/compare timer/counter; watch-dog timer;
2 pulse-width modulated signals; 8 multiplexed input lines;
1.2 to 12 MHz; -40 to + 85 °C
PCF80C31 BH-3WP
PCF80C39P
PCF80C39WP
PCF80C49P
PCF80C49WP
PCF80C51 BH-3P
PCF80C51 BH-3WP
PCF80C552WP
PCF80C562WP
PCF80C652P
PC F80C652WP
PCF80C851P
PCF80C851WP
PCF8200
PCF83C552WP
PCF83C562WP
22
August
19891 (
page
229
229
229
229
229
229
245
209
209
211
211
211
211
209
209
213
215
217
217
221
221
267
213
215
NUMERICAL
INDEX
type
description
PCF83C652P
microcontroller; 256 x 8 RAM; 8K x 8 ROM; serial I/O;
UART; 12C-bus; 1.2 to 12 MHz; -40 to + 85 °C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; serial I/O;
UART; 12C-bus; 1.2 to 12 MHz; -40 to + 85 °C
microcontroller; 256 x 8 RAM; 16K x 8 ROM; serial I/O;
UART; 12C-bus; 1.2 to 12 MHz; -40 to + 85 °C
microcontroller; 256 x 8 RAM; 16K x 8 ROM; serial I/O;
UART; 12 C-bus; 1.2 to 12 MHz; -40 to + 85 °c
microcontroller; 128 x 8 RAM; 4K x 8 ROM; 256 x 8 EEPROM;
1.2 to 12 MHz; -40 to + 85 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM; 256 x 8 EEPROM;
1.2 to 12 MHz; -40 to + 85 °C
single-chip 8-bit microcontroller family
microcontroller; 256 x 8 RAM; bond-out version
PCF84CXX family; 12 C-bus
microcontroller; 256 x 8 RAM; bond-out version
PCF84CXX family; 12C-bus
low cost microcontroller; 64 x 8 RAM; 1K x 8 ROM
low cost microcontroller; 64 x 8 RAM; 1K x 8 ROM
microcontroller; 64 x 8 RAM; 2K x 8 ROM; plus
8-bit LED driver; 12C-bus; -40 to + 85 °C
microcontroller; 64 x 8 RAM; 2K x 8 ROM; plus
8-bit LED driver; 12 C-bus; -40 to + 85 °c
low cost microcontroller; 64 x 8 RAM; 1K x 8 ROM
low cost microcontroller; 64 x 8 RAM; 1K x 8 ROM
microcontroller; 128 x 8 RAM; 4K x 8 ROM; plus
8-bit LED driver; 12 C-bus; -40 to + 85 °C
microcontroller; 128 x 8 RAM; 4K x 8 ROM; plus
8-bit LED driver; 12 C-bus; -40 to + 85 °c
low cost microcontroller; 64 x 8 RAM; 4K x 8 ROM
low cost microcontroller; 64 x 8 RAM; 4K x 8 ROM
microcontroller; 256 x 8 RAM; 8K x 8 ROM; plus
8-bit LED driver; 12 C-bus; -40 to + 85 °c
microcontroller; 256 x 8 RAM; 8K x 8 ROM; plus
8-bit LED driver; 12 C-bus; -40 to + 85 °C
microcontroller; 256 x 8 RAM; 8K x 8 ROM; 32 I/O;
plus 8-bit LED driver; 12C-bus; -40 to + 85 0C
microcontroller; 256 x 8 RAM; 9K x 8 ROM; 32 I/O;
plus 8-bit LED driver; 12C-bus; -40 to + 85 °C
universal LCD driver for low multiplex rates
(1: 1 to 1 :4); max. 96 elements; 12 C-bus
universal LCD driver for low multiplex rates
(1:1 to 1:4); max. 96 elements; 12C-bus
256 x 8-bit static RAM; 12 C-bus
256 x 8-bit static RAM; 12 C-bus
256 x 8-bit static RAM; 12C-bus; different slave address
256 x 8-bit static RAM; 12 C-bus; different slave address
128 x 8-bit static RAM; 12C-bus
128 x 8-b it static RAM; 12 C-bus
PC F83C652WP
PCF83C654P
PC F83C654WP
PCF83C851P
PC F83C851 WP
PCF84CXXX
PCF84COOB
PCF84COOT
PCF84C12P
PCF84C12T
PCF84C21P
PCF84C21T
PCF84C22P
PCF84C22T
PCF84C41P
PCF84C41T
PCF84C42P
PCF84C42T
PCF84C81P
PCF84C81T
PCF84C85P
PCF84C85T
PCF8566P
PCF8566T
PCF8570P
PCF8570T
PCF8570CP
PCF8570CT
PCF8571 P
PCF8571T
page
' ) (AUgUst 1989
217
217
219
219
221
221
281
283
283
285
285
283
283
285
285
283
283
285
285
283
283
287
287
289
289
319
319
319
319
319
319
23
NUMERICAL
INDEX
type
description
PCF8573P
PCF8573T
PCF8574AP
clock calendar, 12 C-bus
clock calendar; 12C-bus
remote 8-bit I/O expander; 12 C-bus
different slave address
remote 8-bit I/O expander; 12 C-bus;
different slave address
remote 8-bit I/O expander; 12 C-bus
remote 8-bit I/O expander; 12 C-bus
universal LCD driver for low multiplex rates
(1: 1 to 1:4); max. 160 segments; 12 C-bus
universal LCD driver for low multiplex rates
(1:1 to 1 :4); max. 160 segments; 12C-bus
universal LCD driver for low multiplex rates
(1:1 to 1:4); max. 160 segments; 12 C-bus
LCD direct driver (32 segments) or duplex driver
.(64 segments); 12C-bus; different slave address
LCD direct driver (32 segments) or duplex driver
(64 segments) 12C-bus; different slave address
LCD direct driver (32 segments) or duplex driver
(64 segments) 12 C-bus; different slave address
LCD direct driver (32 segments) or duplex driver
(64 segments); 12 C-bus
LCD direct driver (32 segments) or duplex driver
(64 segments); 12C-bus
LCD direct driver (32 segments) or duplex driver
(64 segments); 12C-bus
LCD row/column driver for dot matirx graphic displays;
40 outputs; of which 24 are programmable; 12 C-bus
LCD row/column driver for dot matrix graphic displays;
40 outputs, of which 24 are programmable; 12C-bus
LCD row/column driver for dot matrix graphic displays;
40 outputs, of which 24 are programmable; 12 C-bus
LCD column driver for dot matrix graphic displays;
40 column outputs; 12 C-bus
LCD column driver for dot matrix graphic displays;
40 column outputs; 12 C-bus
LCD column driver for dot matrix graphic displays;
40 column outputs; 12 C-bus
256 x 8-bit EEPROM; 12 C-bus; -40 to + 85 oC
256 x 8-bit EEPROM; 12 C-bus; -40 to + 85 °C
clock calendar with 256 x 8-bit static RAM; 12 C-bus
clock calendar with 256 x 8-bit static RAM; 12C-bus
8-bit ADC/DAC; 12C-bus
8-bit ADC/DAC; 12 C-bus
7 -bit ADC; 22 MHz; 3-state output
8-bit multiplying DAC; 30 MHz
PCF8574AT
PCF8574P
PCF8574T
PCF8576T
PCF8576U
PCF8576U/10
PCF8577 AP
PCF8577AT
PCF8577AU
PCF8577P
PCF8577T
PCF8577U
PCF8578T
PCF8578U
PCF8578V
PCF8579T
PCF8579U
PCF8579V
PCF8582AP
PCF8582AT
PCF8583P
PCF8583T
PCF8591P
PCF8591T
PNA7509P
PNA7518P
24
August 1989) (
page
329
329
347
347
347
347
359
359
359
393
393
393
393
393
393
409
409
409
447
447
447
481
481
491
491
509
509
527
539
NUMERICAL
INDEX
type
description
SA571F
SA571N
SA572D
SA572F
SA572N
SA5534N
SA5534AD
SA5534AN
SA602D
SA602N
SA602FE
SA604AD
SA604AN
SA605D
SA605F
SA605N
SA614AD
SA614 AN
SAA1057
SAA1064P
SAA1099
compandor
compandor
programmable analogue compandor
programmable analogue compandor
programmable analogue compandor
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
double balanced mixer and oscillator
double balanced mixer and oscillator
double balanced mixer and oscillator
high performance low-power FM I F system
high performance low-power FM IF system
low-power F M I F system
low-power F M I F system
low-power F M I F system
low-power F M I F system
low-power F M I F system
radio tuning PLL frequency synthesizer (SYMO II)
4-digit LED driver: 12 C-bus
stereo sound generator for sound effects and
music synthesis (,uC-controlled)
tuner switching circuit; 12 C-bus
high performance transmitter (455 kHz) for
infrared remote control; up to 448 commands
high performance transmitter (455 kHz) for
infrared remote control; up to 448 commands
high performance transmitter (RC-5) for infrared
remote control; up to 2048 commands
high performance transmitter (455 kHz) for infrared
remote control; up to 1280 commands; low voltage
high performance transmitter (455 kHz) for infrared
remote control; up to 1280 commands; low voltage
high performance transmitter (38 kHz) for infrared
remote control; low voltage
high performance transmitter (38kHz) for infrared
remote control; low voltage
infrared remote control decoder; decodes 64 commands
(RECS80/RC-5); up to 32 subaddresses; high current
output capability for direct LED drive
high performance transmitter (RC-5) for infrared
remote control; low voltage
high performance transmitter (RC-5) for infrared
remote control; low voltage
high performance transcoder (RC-5) for infrared
remote control; 12 C-bus
infrared remote control decoder, low current
version of SAA3009
SAA1300
SAA3004P
SAA3004T
SAA3006P
SAA3007P
SAA3007T
SAA3008P
SAA3008T
SAA3009P
SAA3010P
SAA3010T
SAA3028
SAA3049P
page
1(AUgust
95
95
103
103
103
135
135
135
143
143
143
149
149
159
159
159
169
169
545
555
565
581
585
585
595
609
609
623
623
637
647
647
663
637
1989
25
NUMERICAL
INDEX
l
'-------------------------------------------------------~
type
description
SAA3049T
infrared remote control decoder, low current
version of SAA3009
decoder for Compact Disc (second generation)
digital filter and interpolator for Compact Disc
(second generation)
audio digital input circuit (ADIC)
audio digital input circuit (ADIC)
decoder for Compact Disc (third generation)
decoder for Compact Disc (third generation)
stereo DAC for Compact Disc
CCD delay line for error correction in video and sound
carrier timebases (Iaservision players)
receiver/decoder for infrared remote control
transmitter for infrared remote control
10-bit high-speed multiplying DAC
internally-compensated dual low noise operational amplifier
internally-compensated dual low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
dual and single low noise operational amplifier
interference and noise suppression circuit for FM receivers
interference and noise suppression circuit for FM receivers
6 W audio power amplifier for in-car applications/10 W
audio power amplifier for mains-fed applications
2 to 6 W audio power amplifier with preamplifier
4 W audio power amplifier with DC volume control
1 to 4 W audio power amplifier with preamplifier
0.5 W audio power amplifier with preamplifier
2 W recording/playback audio power amplifier with
preamplifier, automatic level control, short circuit
and thermal protection
12 W audio power amplifier with preamplifier for car radios
signal-sources switch (4 x two channels)
motor speed regulator with thermal shut-down;
multiplication coefficient = 9; drop-out voltage = 1.8 V
AM receiver circuit for hi-fi and car radios
AM receiver circuit for hi-fi and car radios
dual tandem electronic potentiometer circuit
24 W BTL or 2 x 12 W stereo car radio power amplifier
24 W BTL or 2 x 12 W stereo car radio power amplifier
12 to 20 W hi-fi audio power amplifier
12 to 20 W hi-fi audio power amplifier
50 W hi-fi power amplifier for digital audio
(e.g. Compact Disc)
24 W or 2 x 12 W stereo car radio power amplifier
22 W BTL or 2 x 11 W stereo car radio power amplifier;
closed loop voltage gain 26 dB
2 x 6 W stereo car radio audio power amplifier (20 dB gain)
SAA7210
SAA722P
SAA7274P
SAA7274T
SAA7310P
SAA7310GP
SAA7320GP
SAD7630P
SAF1032P
SAF1039P
SE5410F
SE5532FE
SE5532AFE
SE5534N
SE5534AN
SE5534FE
SE5534AFE
TDA 1001 B
TDA1001 BT
TDA1010A
TDA1011
TDA1013B
TDA1015
TDA1015T
TDA1016
TDA1020
TDA1029
TDA1059B
TDA1072A
TDA1072AT
TDA1074A
TDA1510
TDA1510A
TDA1512
TDA15120
TDA1514A
TDA1515B
TDA15160
TDA1517
26
August
19891 (
page
637
671
693
715
715
727
727
757
777
787
787
119
129
129
135
135
135
135
801
801
811
829
841
849
859
865
871
877
891
897
913
931
941
941
983
983
989
997
1003
1011
NUMERICAL
INDEX
page
type
description
TDA15180
22 W BTL or 2 x 11 W stereo car radio power amplifier;
closed loop voltage gain 46 dB
2 x 6 W stereo car radio audio power amplifier (40 dB gain)
22 W BTL or 2 x 11 W stereo car radio power amplifier
12 W BTL or 2 x 6 W stereo car radio power amplifier
20 W hi-fi audio power amplifier; complete SOAR protection
20 W hi-fi audio power amplifier; complete SOAR protection
2 x 12 W hi-fi stereo audio power amplifier
2 x 6 W hi-fi stereo audio power amplifier
2 x 12 W hi-fi stereo audio power amplifier
stereo playback amplifier/equalizer with mute switch
stereo tone/volume control circuit
stereo tone/volume control circuit
14-bit ADC
high-speed sample-and-hold amplifier
dual 16-bit DAC
active element for post filtering (dual channel)
dual 16-bit economy DAC (1 2 S-busformat)
AM receiver circuit for stereo hi-fi and car radios
AM receiver circuit for stereo hi-fi and car radios
integrated FM tuner for radio receivers
integrated FM tuner for radio receivers
FM/I F amplifier and detector
time multiplex PLL stereo decoder for hi-fi and car radios
traffic warning decoder circuit (AM carriers); AR I system
traffic warning decoder circuit (AM carriers); ARI system
traffic control message and warning tone circuit; AR I system
FM/I F amplifier and detector
FM/I F amplifier and detector
time multiplex PLL stereo decoder for hi-fi and car radios
multi-function oscillator switch for audio cassette recorders
5 W audio power amplifier
6 W hi-fi audio power amplifier
high performance receiver for infrared remote control;
positive output voltage
high performance receiver for infrared remote control;
positive output voltage
high performance receiver for infrared remote control;
negative output voltage
high performance receiver for infrared remote control;
negative output voltage
spatial, stereo and pseudo-stereo sound circuit
DC motor drive circuit with magnetic-field detector
photo diode signal processor for Compact Disc
single-spot read-out systems
radial error signal processor for Compact Disc
FM radio circuit; mono (in plastic DIL18)
FM radio circuit; mono (in S016 plastic mini-pack)
FM radio circuit; stereo/mono; for low voltage
micro tuning system (MTS)
TDA1519
TDA1519A
TDA1519B
TDA1520B
TDA1520BO
TDA1521
TDA1521A
TDA15210
TDA1522
TDA1524A
TDA1525
TDA1534
TDA1535
TDA1541A
TDA1542
TDA1543
TDA1572
TDA1572T
TDA 1574
TDA1574T
TDA1576
TDA1578A
TDA1579
TDA1579T
TDA1589
TDA1596
TDA1596T
TDA1598
TDA1600
TDA2611A
TDA2613
TDA3047P
TDA3047T
TDA3048P
TDA3048T
TDA3810
TDA5040T
TDA5708
TDA5709
TDA7000
TDA7010T
TDA7021T
1(AUgust
1019
1027
1035
1045
1055
1055
1061
1071
1061
1081
1091
1103
1117
1125
1129
1137
1145
1153
1171
1187
1195
1205
1217
1231
1231
1241
1249
1267
1285
1293
1305
1315
1323
1323
1329
1329
1335
1339
1347
1367
1381
1389
1397
1989
27
NUMERICAL
INDEX
type
description
page
TDA7030T
TDA7040T
TDA7050
low voltage micro tuning system (MTS)
PLL stereo decoder; low voltage
150 mW BTL or 2 x 75 mW stereo audio power amplifier;
low voltage
150 mW BTL or 2 x 75 mW stereo audio power amplifier;
low voltage
1 W BTL mono audio amplifier for portable applications
2 x 1 W BTL stereo audio power amplifier for
portable applications
hi-fi stereo audio processor; 12 C-bus
hi-fi stereo audio processor; 12 C-bus
hi-fi stereo audio processor; 12 C-bus
octuple 6-bit DAC; 12 C-bus
photo diode signal processor for Compact Disc
photo diode signal processor for Compact Disc
transfer functions
radial error signal processor for Compact Disc
transfer functions
I F limiting amplifier, FM detector and audio amplifier
I F limiting amplifier, FM detector and audio amplifier
equalizer for audio cassette recorders
low power frequency synthesizer (LOPSY)
Dolby B & C noise reduction circuit
Dolby B & C noise reduction circuit
stereo or 2-channel Dolby B noise reduction circuit
preamplifier and electronic switch for Dolby B & C
noise reduction circuits
dual Dolby B noise reduction circuit
Dolby B & C processor with preamplifier and
electronic switch
Dolby B & C processor with preamplifier and
electronic switch
Dolby B & C processor with preamplifier and
electronic switch; changed frequency response
in relation to TEA0665
Dolby B & C processor with preamplifier and
electronic switch; changed frequency response
in relation to TEA0665
Dolby B & C processor with preamplifier and
electronic switch; low voltage
single-chip AM radio circuit, plus dual AF amplifier,
for pocket receivers with headphones
AM/FM radio receiver circuit
PLL stereo decoder for medium-fi and car radios
PLL stereo decoder with source selector switch
for medium-fi and car radios
PLL stereo decoder with source selector switch
for medium-fi and car radios
AM/FM radio receiver circuit
1407
1415
TDA7050T
TDA7052
TDA7053
TDA8420
TDA8421
TDA8425
TDA8444
TDA8808AT
TDA8808T
TDA8808
TDA8809T
TDA8809
TDB1080
TDB1080T
TDD1601
TDD1742T
TEA0651
TEA0652
TEA0653T
TEA0654
TEA0657
TEA0665
TEA0665T
TEA0666
TEA0666T
TEA0670T
TEA5551T
TEA5570
TEA5580
TEA5581
TEA5581T
TEA5591
28
l
August
19891 (
1423
1427
1431
1437
1445
1467
1489
1511
1519
1519
1539
1559
1571
1583
1583
1589
1605
1627
1627
1645
1627
1651
1659
1659
1669
1669
1679
1685
1697
1711
1721
1721
1733
NUMERICAL
INDEX
type
description
TEA6100
FM/I F system and microcomputer-based tuning
interface; 12 C-bus
AM upconversion radio receiver; 10.7 M Hz IF
car radio preamplifier and source selector with
sound and fader controls; 12 C-bus
car radio preamplifier and source selector with
sound and fader controls; 12 C-bus
sound fader control circuit; 12 C-bus
radio tuning PLL frequency synthesizer; 12 C-bus
radio tuning PLL frequency synthesizer; 12 C-bus
FM stereo multiplex decoder; PLL
TEA6200
TEA6300
TEA6300T
TEA6310T
TSA6057
TSA6057T
MA758N
page
1751
1775
1787
1787
1803
1821
1821
1831
1(AUgust
1989
29
MAINTENANCE
TYPE LIST
MAINTENANCE TYPE LIST
The types listed below are not included in this handbook. Detailed information will be supplied on
request.
SAA 1056P
SAA3027
PLL frequency synthesizer
infrared remote control transmitter (RC-5)
TCA730A
TCA740A
DC volume and balance stereo control circuit
DC treble and bass stereo control circuit
TDA 1011A
TDA1506
2 to 6 W audio power amplifier
motor regulator and function controller
for car cassette systems
auto-reverse car radio cassette deck
steering circuit
PLL motor speed control circuit for
hi-fi applications
low voltage FM stereo radio circuit
TDA1508
TDA1533
TDA7020T
successor type: SAA 1057
successor type: SAA3006
successor type: TDA 1011
successor type: TDA7021T
1(
May 1989
31
GENERAL
Product status defenition for type numbers
with prefixes CA, MC, NE, SA, SE and ~A
Ordering information for type numbers
with prefixes CA, MC, NE, SA, SE and ~A
Type designation for type numbers with prefixes
HEF, MAB, MAF, OM, PCA, PCB, PCF, PNA,
SAA, SAO, SAF, TOA, TOB, TOO, TEA and TSA
Rating systems
Handling MOS devices
PRODUCT STATUS
DEFINITION
For type numbers with prefixes CA, MC, NE, SA, SE and p.A
DEFINITIONS
Data Sheet
Identification
Product Status
Definition
Objectille Specification
Formative or In Design
This data sheet contains the design target or goal
specifications for product development. Specifications may
change in any manner without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data and supplementary
data will be published at a later date. Signetics reserves the
right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product Specification
Full Production
This data sheet contains Final Specifications. Signetics
reserves the right to make changes at any time without
notice in order to improve design and supply the best
possible product.
'] (
December 1988
35
ORDERING
INFORMATION
Signetics' Linear integrated circuit products may be ordered by contacting either
the local Signetics sales office, Signetics
representatives and/or Signetics authorized distributors. A complete listing is
located in the back of this manual.
For type numbers with prefixes CA, MC, NE, SA, SE and J.lA
Table 1. Part Number Description
PART NUMBER
N E 5 5 3,!...
CROSS REF
PART NO.
J:!
PRODUCT
FAMILY
.;;;;.LF_3_9_8_~_ _ _
Ll_N
PRODUCT
DESCRIPTION
LH.~~
Minimum Factory Order:
Description of
Product Function
Commercial Product:
$1000 per order
$250 per line item per order
Military Product:
$250 per line item per order
~
Linear Product Family
Table 1 provides part number information concerning Signetics originated
products.
Table 2 is a cross reference of both the
old and new package suffixes for all
presently existing types, while Tables 3
and 4 provide appropriate explanations
on the various prefixes employed in the
part number descriptions.
As noted in Table 3, Signetics defines
device operating temperature range by
the appropriate prefix. It should be noted, however, that an SE prefix (-55°C to
+ 125°C) indicates only the operating
temperature range of a device and not
its military qualification status. The military qualification status of any Linear
product can be determined by either
looking in the Military Data Manual and/
or contacting your local sales office.
36
December
19881 (
~ Package Descriptions '------1_
L-------t_
See Table 2
Device Number
Device Family and Temperature Range Prefix Tables 3 & 4
See
ORDERING
INFORMATION
For type numbers with prefixes CA, MC, NE, SA, SE and J.LA
Table 2. Package Descriptions
OLD
NEW
A, M
A
N
N-14
B, BA
N
D
F
F
I,IK
I
K
L
H
H
NA, NX
N
R
Q
Q,
T, TA
U
V
XA
XC
XC
XL, XF
H
U
N
N
N
N
N
A
EC
FE
PACKAGE
DESCRIPTION
14-lead plastic DIP
14-lead plastic DIP
(selected analog
products only)
16-lead plastic DIP
Microminiature
package (SO)
14-, 16-, 18-, 22-,
and 24-lead
ceramic DIP
(Cerdip)
14-, 16-, 18-, 22-,
28-, and 4-lead
ceramic DIP
10-lead TO-100
10-lead high-profile
TO-100 can
24-lead plastic DIP
10-, 14-, 16-, and
24-lead ceramic
flat
8-lead TO-99
SIP plastic power
8-lead plastic DIP
18-lead plastic DIP
20-lead plastic DIP
22-lead plastic DIP
28-lead plastic DIP
PLCC
T0-46 header
8-lead ceramic DIP
Table 3. Signetlcs Prefix and
Device Temperature
PREFIX
DEVICE TEMPERATURE
RANGE
NE
SE
SA
o to +70°C
-55°C to +125°C
-40°C to +85°C
Table 4. Industry Standard Prefix
PREFIX
ADC
AM
CA
DAC
ICM
LF
LM
MC
NE
SA
SE
SG
pA
UC
DEVICE FAMILY
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
1(
December 1988
37
TYPE
DESIGNA TION
For type numbers with prefixes HEF, MAB, MAF, OM, PCA,
PCB, PCF, PNA, SAA,SAO, SAF, TOA, TOB, TOO, TEA and TSA
PRO ELECTRON TYPE DESIGNATION CODE
FOR INTEGRATED CIRCUITS
This type nomenclature applies to semiconductor monolithic, semiconductor multi-chip, thin-film,
thick-film and hybrid integrated circuits.
A basic number consists of:
THREE LETTERS FOLLOWED BY A SERIAL NUMBER
FIRST AND SECOND LETTER
1. DIGITAL FAMILY CIRCUITS
The FIRST TWO LETTERS identify the FAMILY (see note 1).
2. SOLITARY CIRCUITS
The FIRST LETTER divides the solitary circuits into:
S : Solitary digital circuits
T : Analogue circuits
U: Mixed analogue/digital circuits
The SECOND LETTER is a serial letter without any further significance except 'H' which stands
for hybrid circuits.
3. MICROPROCESSORS
The FIRST TWO LETTERS identify microprocessors and correlated circuits as follows:
MA
.
MB
MD
ME
{Microcomputer
Central processing Unit
Slice processor (see note 2)
Correlated memories
Other correlated circuits (interface, clock, peripheral controller, etc.)
4. CHARGE-TRANSFER DEVICES AND SWITCHED CAPACITORS
The FIRST TWO LETTERS identify the following:
NH
NL
NM
NS
NT
NX
NY
:
:
:
:
:
:
:
Hybrid circuits
Logic circuits
Memories
Analogue signal processing, using switched capacitors
Analogue signal processing, using CTDs
I maging devices
Other correlated circuits
Notes
1. A logic family is an assembly of digital circuits designed to be interconnected and defined by its
basic electrical characteristics (such as: supply voltage, power consumption, propagation delay,
noise immunity).
2. By 'slice processor' is meant: a functional slice of microprocessor.
'] (
October 1987
39
TYPE
DESIGNATION
l
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
THIRD LETTER
It indicates the operating ambient temperature range.
The letters A to G give information about the temperature~
A: temperature range not specified
B : 0 to + 70 °C
C : -55 to + 125 °C
D: -25 to + 70 oC
E : -25 to + 85 0C
F : -40 to + 85 0C
G: -55 to + 85 oC
If a circuit is published for another temperature range, the letter indicating a narrower temperature
range may be used or the letter' A' .
Example: the range 0 to + 75 0C can be indicated by 'B' or 'A'.
SERIAL NUMBER
This may be either a 4-digit number assigned by Pro Electron, or the serial number (which may be a
combination of figures and letters) of an existing company type designation of the manufacturer.
To the basic type number may be added:
A VERSION LETTER
Indicates a minor variant of the basic type or the package. Except for 'Z', which means customized
wiring, the letter has no fixed meaning. The following letters are recommended for package variants:
C : for cylindrical
o : for ceramic 01 L
F for flat pack
L : for chip on tape
P : for plastic 0 I L
Q : for QIL
T : for miniature plastic (mini-pack)
U : for uncased chip
Alternatively a TWO LETTER SUFFIX may be used instead of a single package version letter, if the
,manufacturer (sponsor) wishes to give more information.
FIRST LETTER: General shape
SECOND LETTER: Material
C : Cylindrical
o : Oual-in-line (OIL)
E.: Power 01 L (with external heatsink)
F : Flat (leads on 2 sides)
G : Flat (leads on 4 sides)
K: Diamond (TO-3 family)
M: Multiple-in-line (except Oual-, Triple-, Quadruple-in-line)
Q : Quadruple-in-line (QI L)
R : Power QI L (with external heatsink)
S : Single-in-line
T : Triple-in-line
C :
G :
M:
P :
Metal-ceramic
Glass-ceramic (cerdip)
Metal
Plastic
A hyphen precedes the suffix to avoid confusion with a version letter.
40
October 1987\ (
RATING
SYSTEMS
For type numbers with prefixes HEF, MAB, MAF, OM, PCA,
PCB, PCF, PNA, SAA, SAD, SAF, TDA, TDB, TOO, TEA and TSA
RATING SYSTEMS
The rating systems described are those recommended by the International Electrotechnical Commission
(IEC) in its Publication 134.
DEFINITIONS OF TERMS USED
Electronic device. An electronic tube or valve, transistor or other semiconductor device.
Note
This definition excludes inductors, capacitors, resistors and similar components.
Characteristic. A characteristic is an inherent and measurable property of a device. Such a property
may be electrical, mechanical, thermal, hydraulic, electro-magnetic, or nuclear, and can be expressed
as a value for stated or recognized conditions. A characteristic may also be a set of related values,
usually shown in graphical form.
Bogey electronic device. An electronic device whose characteristics have the published nominal values
for the type. A bogey electronic device for any particular application can be obtained by considering
only those characteristics which are directly related to the application.
Rating. A value which establishes either a limiting capability or a limiting condition for an electronic
device. It is determined for specified values of environment and operation, and may be stated in any
suitable terms.
Note
Limiting conditions may be either maxima or minima.
Rating system. The set of principles upon which ratings are established and which determine their
interpretation.
Note
The rating system indicates the division of responsibility between the device manufacturer and the
circuit designer, with the object of ensuring that the working conditions do not exceed the ratings.
ABSOLUTE MAXIMUM RATING SYSTEM
Absolute maximum ratings are limiting values of operating and environmental conditions applicable to
any electronic device of a specified type as defined by its published data, which should not be exceeded under the worst probable conditions.
These values are chosen by the device manufacturer to provide acceptable serviceability of the device,
taking no responsibility for equipment variations, environmental variations, and the effects of changes
in operating conditions due to variations in the characteristics of the device under consideration and
of all other electronic devices in the equipment.
The equipment manufacturer should design so that, initially and throughout life, no absolute maximum
value for the intended service is exceeded with any device under the worst probable operating conditions with respect to supply voltage variation, equipment component variation, equipment control
adjustment, load variations, signal variation, environmental conditions, and variations in characteristics
of the device under consideration and of all other electronic devices in the equipment.
1
(octOber 1987
41
RATING
SYSTEMS
DESIGN MAXIMUM RATING SYSTEM
Design maximum ratings are limiting values of operating and environmental conditions applicable to a
bogey electronic device of a specified type as defined by its published data, and should not be exceeded under the worst probable conditions.
These values are chosen by the device manufacturer to provide acceptable serviceability of the device,
taking responsibility for the effects of changes in operating conditions due to variations in the characteristics of the electronic device under consideration.
The equipment manufacturer should design so that, initially and throughout life, no design maximum
value for the intended service is exceeded with a bogey device under the worst probable operating
conditions with respect to supply voltage variation, equipment component variation, variation in
characteristics of all other devices in the equipment, equipment control adjustment, load variation,
signal variation and environmental conditions.
DESIGN CENTRE RATING SYSTEM
Design centre ratings are limiting values of operating and environmental conditions applicable to a
bogey electronic device of a specified type as defined by its published data, and should not be exceeded under normal conditions.
These values are chosen by the device manufacturer to provide acceptable serviceability of the device
in average applications, taking responsibility for normal changes in operating conditions due to rated
supply voltage variation, equipment component variation, equipment control adjustment, load variation,
signal variation, environmental conditions, and variations in the characteristics of all electronic devices.
The equipment manufacturer should design so that, initially, no design centre value for the intended
service is exceeded with a bogey electronic device in equipment operating at the stated normal supply
voltage.
42
Mavl9831 (
HANDLING
MOS DEVICES
HANDLINGMOS DEVICES
Though all our MaS integrated circuits incorporate protection against electrostatic discharges, they
can nevertheless be damaged by accidental over-voltages. In storing and handling them, the following
precautions are recommended.
Caution
Testing or handling and mounting call for special attention to personal safety. Personnel handling MaS
devices should normally be connected to ground via a resistor.
Storage and transport
Store and transport the circuits in their original packing. Alternatively, use may be made of a conductive
material or special IC carrier that either short-circuits all leads or insulates them from external contact.
Testing or handling
Work on a conductive surface (e.g. metal table top) when testing the circuits or transferring them from
one carrier to another. Electrically connect the person doing the testing or handling to the conductive
surface, for example by a metal bracelet and a conductive cord or chain. Connect all testing and handling equipment to the same surface.
Signals should not be applied to the inputs while the device power supply is off. All unused input leads
should be connected to either the supply v~ltage or ground.
Mounting
Mount MaS integrated circuits on printed circuit boards after all other components have been mounted.
Take care that the circuits themselves, metal parts of the board, mounting tools, and the person doing
the mounting are kept at the same electric (ground) potential. If it is impossible to ground the printedcircuit board the person mounting the circuits should touch the board before bringing MaS circuits
into contact with it.
Soldering
Soldering iron tips, including those of low-voltage irons, or soldering baths should also be kept at the
same potential as the MaS circuits and the board.
Static charges
Dress personnel in clothing of non-electrostatic material (no wool, silk or synthetic fibres). After the
MaS circuits have been mounted on the board proper handling precautions should still be observed.
Until the sub-assemblies are inserted into a complete system in which the proper voltages are supplied,
the board is no more than an extension of the leads of the devices mounted on the board. To prevent
static charges from being transmitted through the board wiring to the device it is recommended that
conductive clips or conductive tape be put on the circuit board terminals.
Transient voltages
To prevent permanent damage due to transient voltages, do not insert or remove MaS devices, or
printed-circuit boards with MaS devices, from test sockets or systems with power on.
Voltage surges
Beware of voltage surges due to switching electrical equipment on or off, relays and d.c. lines.
1
(May 1983
43
DEVICE DATA
CA3089
FM IF System
Product Specification
DESCRIPTION
CA3089 is a monolithic integrated circuit
that provides all the functions of a comprehensive FM IF system. The block
diagram shows the CA3089 features,
which include a three-stage FM IF amplifier/limiter configuration with level detectors for each stage, a doubly-balanced quadrature FM detector and an
audio amplifier that features the optional
use of a mutjng (squelch)· circuit.
The circuit design of the IF system
includes desirable features such as delayed AGC for the RF tuner, an AFC
drive circuit, and an output signal to drive
a tuning meter and/or provide stereo
switching logic. In addition, internal power supply regulators maintain a nearly
constant current drain over the voltage
supply range of + 8V to + 18V.
The CA3089 is ideal for high-fidelity
operation. Distortion in a CA3089 FM IF
system is primarily a function of the
phase linearity characteristic of the outboard detector coil.
The CA3089 utilizes a 16-lead dual-inline plastic package and can operate
over the ambient temperature range of
-40°C to + 85°C.
PIN CONFIGURATION
N Package
FEATURES
BYPASSING
• Exceptional limiting sensitivity:
10llV typo at -3dB point
• Low distortion: 0.1 % typo (with
double-tuned coil)
• Single-coil tuning capability
• High recovered audio: 400mV
typo
• Provides specific signal for
control of interchannel muting
(squelch)
• Provides specific signal for direct
drive of a tuning meter
• Provides delayed AGC voltage
for RF amplifier
• Provides a specific circuit for
flexible AFC
• Internal supply/voltage regulators
IF INPUT
BYPASSING
QUADRATURE
INPUT
TOP VIEW
APPLICATIONS
• High-fidelity FM receivers
• Automotive FM receivers
• Communications FM receivers
BLOCK DIAGRAM
DELAYEO
AGe FOR o - . . - - - - - t - H
RF AMPl
) - ' . N o , . - - . i ' - - - - - - - - - - 0 TO STEREO
TUNING METER OUTPUT
THRESHOLD
LOGIC CIRCUITS
NOTES:
1. All resistor values are typical and in ohms. 00"" 75 (G.L EX27825 or equivalent)
2. L tunes with 100pF (C) at 10. 7MHz
November 14, 1986
47
853-0044 86551
Product Specification
FM IF System
CA3089
EQUIVALENT SCHEMATIC
NOTES:
1. All resistance values are typical and in ohms.
2. All capacitance values are in picofarads.
November 14, 1986
48
Product Specification
CA3089
FM IF System
ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic DIP
TEMPERATURE RANGE
ORDER CODE
-40·C to + 85·C
CA3089N
ABSOLUTE MAXIMUM RATINGS
SYMBOL
Vee
PD
PARAMETER
RATING
UNIT
DC supply voltage:
between terminals 11 and 4
between terminals 11 and 14
18
18
V
V
DC current (out of Terminal 15)
2
mA
600
derate linearly
6.7
mW
Device dissipation:
up to TA = 60·C
above TA = 60·C
mW;oC
TA
Operating ambient temperature range
-40 to +85
·C
TSTG
Storage temperature range
-65 to +150
·C
TSOLD
Lead soldering temperature
(10sec max)
+300
·C
November 14. 1986
49
Product Specification
CA3089
FM IF System
DC ELECTRICAL CHARACTERISTICS T A = 25°C, V+ = 12V, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Typ
Min
Max
Static (DC) Characteristics
111
I Quiescent
circuit current
I
No signal input, non-muted
I
16
I
23
I
30
I
mA
DC Voltages4
V1
Terminal 1 (1F input)
No signal input, non-muted
1.2
1.9
2.4
V
V2
V3
Terminal 2 (AC return to input)
Terminal 3 (DC bias to input)
No signal input, non-muted
No signal input, non-muted
1.2
1.2
1.9
1.9
2.4
2.4
V
V
Vs
V7
V 10
Terminal 6 (audio output)
Terminal 7 (AFC)
Terminal 10 (DC reference)
No signal input, non-muted
No signal input, non-muted
No signal input, non-muted
5.0
5.0
5.0
5.6
5.6
5.6
6.0
6.0
6.0
V
V
V
10
25
IlV
Dynamic Characteristics
VI(LlM)
Input limiting voltage (-3dB pOint)3
AMR AM rejection (Terminal 6)4
Vo
Recovered audio voltage (Terminal 6)3
THO
THO
Total harmonic distortion: 1
Single tuned (Terminal 6)3
Double tuned (Terminal 6)4
S + N/N
MUIN
Signal plus noise-to-noise ratio (Terminal 6)3
Mute input (Terminal 5)
MUOUT
Mute output (Terminal 12)
VIN = O.W, fo = 10.7MHz,
fMOD = 400Hz, AM Mod = 30%
55
400
500
600
mV
0.5
0.1
1.0
%
%
fMOD = 400Hz, VIN = 0.1
Deviation = ± 75kHz, VIN = 0.1 V
V5 = 2.5V
60
50
VIN = 50llV
VIN = OV
4.0
MTR
Meter output (Terminal 13)
VIN = 0.1V
VIN = 500llV
VIN = OV
AGe
Delay AGC (Terminal 15)
VIN = O.OW
VIN = 10llV
THO
45
Double tuned (Terminal 6)4
fMOD = 400Hz
VIN=0.1
dB
70
70
dB
dB
0.5
2.5
1.0
3.5
1.5
0.7
0.5
4.0
V
V
V
V
V
5.0
V
V
0.1
%
NOTES
1. THD characteristics and audio level are essentially a function of the phase and Q characteristics of the network connected between Terminals 8, 9,
and 10.
2. Test circuit Figure 1.
3. Test circuit Figure 2.
4. Test circuit Figures 1 and 2.
November 14, 1986
50
Product Specification
CA3089
FM IF System
TEST CIRCUITS
;f!j~iI
I
I
I
1GOpF
I
C1
I
I--IT'
I
I
I
AFC OUTPUT
SIGNAL
INPUT (OlH~t----'-I
VOLTAGE
NOTES:
1. L tunes with 100pF (C) at 10. 7MHz.
2. All resistor values are typical and in ohms.
3. 00 (unloaded) "" 75 (G.I. automatic mfg. div. EX27B25 or equivalent).
Figure 1. Test Circuit Using a Single-Tuned Detector Coil
NOTES:
All resistor values are typical and in ohms.
T: Pri - 00 (unloaded) "" 75 (tunes with I OOpF (CI) 20 t of 34e on 7/32' dia.
form) Sec. (unloaded) "" 75 (tunes with I OOpF (C2) 20 t of 34e on 7/32'
dia. form)
kO (percent of critical coupling) > 70%
(Adjusted for coil voltage Vc = 150mV)
Above values permit proper operation of mute (squelch) circuit 'E' type slugs,
spacing 4mm
a
Figure 2. Test Circuit Using a Double-Tuned Detector Coli
November 14, 1986
51
Product Specification
CA3089
FM IF System
TEST CIRCUITS
y. _12V
30011
INPUT
NOTES:
All resistor values are typical and in ohms.
1. Waller 4SN3FIC or equivalent.
2. Murate SFG 10.7mA or equivalent.
3. Rs will affect stability depending on circuit layout. To increase stability Rs is decreased.
Range 01 As is 330 to 50n, Rl + Rs .;; 3300.
4. L tunes with 100pF (C) at 10.7MHz 00 unloaded "" 75 (G.I. EX27825 or equivalent).
Performance data at 10 - 98MHz, IMoo - 400Hz, deviation - ± 74kHz.
±74kHz.
2jJV (antenna level)
- 3d8 limiting sensitivity
20d8 quieting sensitivity
1jJV (antenna level)
3Od8 quieting sensitivity
1.5jJV (antenna level)
Figure 3. Typical FM Tuner With a Single-Tuned Detector Coli
SYSTEM DESIGN
CONSIDERATIONS
The CA3089 is a very high gain device and
therefore careful consideration must be given
to the layout of external components to
minimize feedback. The input bypass capacitors should be located close to the input
terminals and the values should not be large
nor should the capacitors be of the type
which might introduce inductive reactance to
the circuit. An example of good bypass capaCitors would be ceramic disc with values in
the range of 0.01 to 0.05J.1F.
The input impedance of the CA3089 is approximately 10,OOOn. It is not recommended
to match this impedance. The value of the
input termination resistor should be as low as
possible without degrading system operation.
The lower the value of this resistor the
greater the system stability. An input terminating resistor between Son and 100n is recommended.
TYPICAL PERFORMANCE CHARACTERISTICS
Muting Action, Tuner AGC
(Tuning meter output as a
function of input signal voltage.)
AFC Characteristics
(Current at Terminal 7 as a
function of change in frequency.)
125
100
=
DC POWER SUPPLY (V+) 12V _~
AMBIENT TEMPERATURE (TA) 25'C_
SEE TEST CIRCUIT FIGURE 3
=
.L
'"
~,
1
~
V- r--
75
~
-t--.....::llk--+--i
z
i
o
/
0
~
Q
-25
/
I-
ffiIX:
-50
/
IX:
~
0
-75
-100
-125
10
100
lK
10K
lOOK
INPUT SIGNAL - jJV
)f'
If'
-100
-50
50
CHANGE IN FREQUENCY (lIl)- kHz
OP09370S
November 14, 1986
/
52
100
HEF4750V
LSI
FREQUENCY SYNTHESIZER
The HEF4750V frequency synthesizer is one of a pair of LOCMOS devices, primarily intended for use
in high-performance frequency synthesizers, e.g. in all communication, instrumentation, television and
broadcast applications. A combination of analogue and digital techniques results in an integrated
circuit that enables high performance. The complementary device is the universal divider type
HEF4751V.
Together with a standard prescaler, the two LOCMOS integrated circuits offer low-cost single loop
synthesizers with full professional performance. Salient features offered (in combination with
HEF4751V) are:
•
•
•
•
•
•
•
•
•
•
•
Wide choice of reference frequency using a single crystal.
High-performance phase comparator - low phase noise - low spurii.
System operation to> 1 GHz.
Typical 15 MHz input at 10 V.
Flexible programming:
frequency offsets
ROM compatible
fractional channel capability.
Programme range 6% decades, including up to 3 decades of prescaler control.
Division range extension by cascading.
Built-in phase modulator.
Fast lock feature.
Out-of-Iock indication.
Low power dissipation and high noise immunity.
APPLICATION INFORMATION
Some examples of applications for the HEF4750V in combination with the HEF4751V are:
•
•
•
•
•
•
•
VHF/UHF mobile radios.
H F s.s.b. transceivers.
Airborne and marine communications and navaids.
Broadcast transm itters.
High quality radio and television receivers.
High performance citizens band equipment.
Signal generators.
SUPPLY VOLTAGE
rating
recommended
operating
-0,5 to + 15
9,5 to 10,5 V
') (
October 1980
53
HEF4750V
LSI
PINNING
V
VOO
STB
MOO
TCB
OUT
OL
R
TCA
NS 1
TRA
NS O
TCC
OSC
PC1
XTAL
PC 2
Ag
AO
A8
A1
A7
A2
A6
A3
A5
VSS
A4
R
V
STB
TCA
TCB
TCC
TRA
PC1
PC2
MOO
OL
OSC
XTAL
AO to Ag
NSO, NS1
OUT
7Z84472
Fig. 1 Pinning diagram.
HEF4750VO: 28-lead 01 L; ceramic (cerdip) (SOT135A).
54
May 1983
'1 (
phase comparator input, reference
phase comparator input
strobe input
timing capacitor CA pin
timing capacitor CB pin
timing capacitor Cc pin
biasing pin (resistor RA)
analogue phase comparator output
digital phase comparator output
phase modulation input
out-of-Iock indication
reference oscillator/buffer input
reference oscillator/buffer output
programming inputs/programmable
divider
programming inputs, prescaler
reference divider output
~
CD
-
.0
V DD
VSS
OL
4
~
I
REFERENCE
OSCILLATOR :---+
& BUFFER
+1,2,10
or 100
-
-;.-1 to 1024
f---+
P-MOS
PHASE
---+ SWITCH
----COMPARATOR
---+ N-MOS
PC2
SWITCH
i i t i
PROGRAMMING
LOGIC
~
PHASE
A
~
en
-<
:s
'*
~
CD
en
N·
.,CD
~
1
PROGRAMMING
LOGIC
PC 2 9
c:
CD
:s
PHASE COMPARATOR
(SAMPLE & HOLD TYPE)
PCl
PC 1 8
MODULATOR
~
OSC
22
XTAL
21
NSO
NSl
23
24
AO
A9
12
10
11
o
I
o
13
y
programming inputs
reference divider
17
16
19
18
20
V
TCB MOD STB
26
1
3
u
25
27
2
TRA
TCA
TCC
6
5
7
eBt eoJi eAt eef
,
crystal standard
C')
15
OUT R
DO
y
external circuitry
7Z84473
Fig. 2 Block diagram comprising five basic functions: phase comparator 1 (PC1), phase comparator 2 (PC2), phase modulator, reference oscillator
and reference divider. These functions are described separately.
~
o
...,
0CD
co
00
o
N.B. PC1 = analogue output; PC2
= 3-state output.
I
,"m
(I).j::::...
"-I
01
o
U1
U1
<
HEF4750V
LSI
FUNCTIONAL DESCRIPTION
Phase comparator 1
Phase comparator 1 (PC1) is built around a SAMPLE and HOLD circuit. A negative-going transition at
the V-input causes the hold capacitor (CA) to be discharged and after a specified delay, caused by the
Phase Modulator by means of an internal V' pulse, it produces a positive-going ramp. A negative-going
transition at the R-input terminates the ramp. Capacitor CA holds the voltage that the ramp has
attained. Via an internal sampling switch this voltage is transferred to Cc and in turn buffered and
made available at output PC,.
If the ramp terminates before an R-input is present, an internal end of ramp (EaR) signal is produced.
These actions are illustrated in Fig. 3.
V
I
----,
R
I
I
I
V'
1
~
determined by the
phase modulator
-
-
TCA
(analogue)
- - - - - - " " " " ; ; ; - - - - - - - - - - - - - VDD
-
~
-
II
reset
,,""
____________I
~l
,~
______________________
voltage
transferred to T C C
----------------~
_h-O-I-d----t------------
.1~1
..
r-------------------
EaR
I
I
analogue
sampling
switch'S'
~.
ON
OFF
OFF
• • ON
I
ON
-------------------------------------
TCC
(analogue)
---------------------~
7Z84474
Fig.3 Waveforms associated with PC1.
56
October 1980
1(
HEF4750V
Frequency synthesizer
LSI
The resultant phase characteristic is shown in Fig. 4.
PC 1 )
output
voltage
L4~ V4~ V4~ r
1--
1
2rr __
7Z84476
Fig. 4 Phase characteristic of PC1.
PC1 is designed to have a high gain, typically 3200 V/cycle (at 12,5 kHz). This enables a low noise
performance.
Phase comparator 2
Phase comparator 2 (PC2) has a wide range, which enables faster lock times to be achieved than
otherwise would be possible. It has a linear ± 360 0 phase range, which corresponds to a gain of
typically 5 V/cycle. This digital phase comparator has three stable states:
- reset state,
- V' leads R state,
- R leads V' state.
Conversion from one state to another takes place according to the state diagram of Fig. 5.
active R- edge
(negative going)
active R - edge
(negative going)
0B=e=rB
active V - edge
(negative going)
active V - edge
(negative going)
7Z84477
Fig. 5 State diagram of PC2.
Output PC2 produces positive or negative-going pulses with variable width; they depend on the phase
relationship of R and V'. The average output voltage is a linear function of the phase difference.
Output PC2 remains in the high impedance OFF-state in the region in which PC1 operates. The
resultant phase characteristic is shown in Fig. 6.
1(
October 1980
57
l___~_
HEF4750V
LSI
FUNCTIONAL DESCRIPTION (continued)
2
PC
average
output
voltage
j
./
1-2n-1
7Z84478
Fig.6 Phase characteristic of PC2.
Strobe function
The strobe function is intended for applications requiring extremely fast lock times. In normal
operation the additional strobe input (STB) can be connected to the V-input and the circuit will
function as described in the previous sections.
In si ngle, phase-locked-loop type frequency synthesizers, the comparison frequency generally used is
either the nominal channel spacing or a sub-multiple. PC2 runs at the higher frequency (a higher
reference frequency must also be used), whilst strobing takes place on the lower frequency, thereby
obtaining a decrease in lock time. I n a system using the Universal Divider HE F4 751 V, the output a FS
cycles on the lower frequency, the output OF F cycles on the higher frequency.
Out-of-Iock function
There are a number of situations in which the system goes from the locked to the out-of-Iock state
(OL goes HIGH):
1. When V' .Ieads R, however out of the range of PC 1.
2. When R leads V'.
3. When an R-pulse is missing.
4. When a V-pulse is missing.
5. When two successive STB-commands occur, the first without corresponding V-signal.
Phase modulator
The phase modulator only uses one external capacitor, CB at pin TCB. A negative-going transition at
the V-input causes CB to produce a positive-going linear ramp. When the ramp has reached a value
almost equal to the modulation input voltage (at MOD), the ramp terminates, CB discharges and a
start signal to the CA-ramp at TCA is produced. A linear phase modulation is reached in this way.
If no modulation is required, the MOD-input must be connected to a fixed voltage of a certain
positive value up to VDD' Care must be taken that the V' pulse is never smaller than the minimum
value to ensure that the external capacitor of PC1 (CA) can be discharged during that time. Since the
V' pulse width is directly related to the TCB ramp duration, there is a requirement for the minimum
value of this ramp duration.
58
1(
October 1980
-'"l.
HEF4750V
____________F_r_e_q_u_en_c_y__
sy_n_t_h_e_si_ze_r______________________________________
LSI
Reference oscillator
The reference oscillator normally operates with an external crystal as shown in Fig. 2. The internal
circuitry can be used as a buffer amplifier in case an external reference should be required.
Reference divider
The reference divider consists of a binary divider with a programmable division ratio of 1 to 1024 and
a prescaler with selectable division ratios of 1, 2, 10 and 100, according to the following tables:
• Binary divider
N (AO to Ag)
0
O~
N
~
1023
• Prescaler
division ratio
programming word
(NSO, NS1)
division ratio
0
1
2
3
1
2
10
100
1024
N
In this way suitable comparison frequencies can be obtained from a range of crystal frequencies. The
divider can also be used as a 'stand alone' programmable divider by connecting input TRA to VOO,
which causes all internal analogue currents to be switched off.
~
Biasing circuitry
The biasing circuitry uses an external current source or resistor, which has to be connected between
the TRA and VSS pins. This circuitry supplies all analogue parts of the circuit. Consequently the
analogue properties of the device, such as gain, charge currents, speed, power dissipation, impedance
levels etc., are mainly determined by the value of the input current at TRA. The TRA input must be
decoupled to VOO, as shown in Fig. 7. The value of Co has to be chosen such that the TRA input is
'clean', e.g. 10 nF at RA = 68 kft
HEF4750V
7Z84479
Fig. 7 Oecoupling of input TRA.
1(
October 1980
59
l""----~_
HEF4750V
LSI
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage
VDD
-0,5 to + 15 V
Voltage on any input
-0,5 to VDD + 0,5 V
D.C. current into any input or output
max.
10 rnA
Power dissipation per package
for T amb = 0 to + 85 °C
max.
500 mW
max.
100 mW
Power dissipation per output
for T amb = 0 to 85 °C
P
Storage temperature
T stg
-65 to + 150 °C
Operating ambient temperature
Tamb
-40 to + 85 °C
D.C. CHARACTERISTICS at VDD = 10 V ± 5%; voltages are referenced to VSS
otherwi.se specified; for definitions see note 1.
= 0 V, unless
Tamb (OC
parameter
symbol
-40
+ 25
+85
unit
min. typo max. min. typo max. min. typo max.
notes
Quiescent device
current
IDD
-
-
100
-
-
100
-
-
750 JlA
2
Input current; logic
inputs, MOD
± liN
-
-
300
-
-
300
-
-
1000 nA
3
Output leakage current
at % VDD
3,4
TCA, hold-state
±IZ
-
-
20
-
0,05
20
-
-
60 nA
TCC, analogue
switch OFF
±IZ
-
-
20
-
0,05
20
-
-
60 nA
PC2, high impedance
OFF-state
± IZ
-
-
50
-
50
-
-
500 nA
Logic input voltage
LOW
HIGH
Logic output voltage
LOW; at
1<1 JlA
Po
HIGH
-
VIL
max. 0,3 VDD
V
VIH
min. 0,7 VDD
V
VOL
-
-
50
I-
-
50
I-
-
50 mV
3
mV
3
min. VDD-50 mV
VOH
Logic output current
LOW; at VOL = 0,5 V
outputs
OUT
output XTAL
60
3
a L, PC2,
10L
5,5
-
10L
2,8
-
1(
October 1980
-
4,6
-
-
3,6
2,4
-
-
1,9
-
-
rnA
rnA
HEF4750V
Frequency synthesizer
LSI
Tamb (OC)
symbol
unit notes
-40
+25
+ 85
min. typo max. min. typo max. min. typo max.
outputs 0 L,PC2,OUT
-IOH
1,5
-
output XTAL
-IOH
1,4
Output TCC sink
current
10
Output TCC source
current
-10
parameter
Logic output current
HIGH;
at VOH =VOO-0,5 V
3
rnA
-
-
-
-
-
rnA
3,4,5
-
-
-
-
rnA
3,4,6
0,7
-
-
-
-
kn
3,4
-
0
-
-
0
-
V
3,4,7
-
-
1,1
-
-
-
-
rnA
3,4,8
-
-
-
1,0
-
-
-
-
rnA
3,4,9
-
-
-
-
1,4
-
-
-
-
kn
3,4
!:lV
-
0
-
-
0
-
-
0
-
V
3,4,10
VEOR
-
0,9 -
-
0,7
-
-
0,6
-
V
3,4,11
10
10
-
-
-
-
2,5 -
-
-
-
mA
-
-
rnA
1,3
-
-
1,0
-
-
-
1,2
-
-
0,9
-
-
-
-
2,1
-
-
-
-
-
1,9
I nternal resistance
ofTCC
loutput swing 1~200 mV
specified output range:
0,3 VOO to 0,7 VOO Ri
-
-
-
-
Output TCC voltage
with respect to
TCA input voltage
!:lV
-
0
-
Output PCl sink
current
10
-
-
Output PCl source
current
-10
-
I nternal resistance
of PCl
loutput swing I~ 200 mV
specified output range:
0,3 VOO to 0,7 VOO Ri
Output PCl voltage
with respect to
TCC input voltage
EOR generation
VEOR = VOO-VTCA
rnA
Source current; H IG H
at VOUT = % VOO;
output in ramp mode
TCA
TCB
3,4
-
13
1(
October 1980
61
HEF4750V
LSI
A.C. CHARACTERISTICS
General note
The dynamic specifications are given for the circuit built-up with external components as given in
Fig. 8, under the following conditions; for definitions see note 1; for definitions of times see Fig. 19;
VOD = 10 V ± 5%; Tamb = 25 °C; input transition times'::;:;; 20 ns; RA = 68 k.n ± 30% (see also note 4);
CA = 270 pF; CB = 150 pF; Cc = 1 nF; CD = 10 nF; unless otherwise specified.
62
symbol
min.
typo
max.
unit
conditions
notes
Slew rate
TCA
TCA
TCB
TCB
STCA
STCA
STCB
STCB
-
-
-
52
28
20
10
-
V/JlS
V/JlS
V/JlS
V/JlS
RA = minimum
RA = maximum
RA = minimum
RA = maximum
12
12
12
12
Ramp linearity
TCA
TCB
ITCA
ITCB
-
2
2
-
%
%
Start of TCA-ramp delay
tCBCA
-
200
-
ns
Delay of TCA-hold
tRCA
-
40
ns
Delay of TCA-discharge
tVCA
-
60
Start of TCB-ramp delay
tVCB
-
60
TCB-ramp duration
.trCB
trCB
trCB
-
-
250
350
450
-
Required TCB min.
ramp duration
trCB
-
Pulse width
V: LOW
V: HIGH
tpWVL
tpWVH
-
R:LOW
R: HIGH
tpWRL
tpWRH
STB: LOW
STB: HIGH
tpWSL
tpWSH
Fall time
TCA
TCB
tfCA
tfCB
Prescaler input frequency
fPR
-
-
-
-
ns
ns
-
ns
ns
ns
150
-
ns
20
20
-
ns
ns
ns
ns
20
20
20
20
-
=4 V
=6 V
=8 V
14
ns
ns
-
50
50
-
30
MHz
all division ratios
MHz
all division ratios
-
Binary divider frequency
fDIV
-
30
Crystal oscillator frequency
fOSC
-
10
-
MHz
Average power supply current
with speed-up 1 : 10
without speed-up
Ip
Ip
-
3,6
3,2
-
rnA
rnA
1(
VMOD
VMOD
VMOD
ns
ns
-
October 1980
13
13
locked state
-
15
16
HEF4750V
Frequency synthesizer
LSI
to VSS or VOO
A.
'\
NS O NS 1 AO------------Ag
OUT
VOO
MOD
PC 1
R
HEF4750V
V
PC 2
STB
OL
VSS
TRA
TCA
TCB
OSC XTAL
.......--+-~~--+-VSS
7Z84480
Fig. 8 Test circuit for measuring a.c. characteristics.
NOTES
1. Definitions:
RA = external biasing resistor between pins TRA and VSS; 68 kn ± 30%.
CA = external timing capacitor for time/voltage converter, between pins TCA and VSS.
CB = external timing capacitor for phase modulator, between pins TCB and VSS.
Cc = external hold capacitor between pins TCC and VSS.
CD = decoupling capacitor between pins TRA and VOO'
2.
3.
4.
5.
logic inputs: V, R, STB, AO to Ag, NSO, NS1, OSC.
logic outputs: Ol, PC2, XTAl, OUT.
Analogue signals: TCA, TCB, TCC, TRA, PC1, MOD.
TRA at VOO; TCA, TCB, TCC and MOD at VSS; logic inputs at VSS or VOO'
All logic inputs at VSS or VDO'
RA connected; its value chosen such that ITRA = 100 11A.
The analogue switch is in the ON position (see Fig. g).
--10
analogue
switch
7Z84481
Fig. 9 Equivalent circuit for note 5.
1(
October 1980
63
HEF4750V
LSI
NOTES (continued)
6. The analogue switch is in the ON position (see Fig. 10).
Fig. 10 Equivalent circuit for note 6.
7. This guarantees the d.c. voltage gain, combined with d.c.-offset.
Input condition: 0,3 VOO ~ VTCA ~ 0,7 VOO'
f:l.V = VTCC-VTCA'
TCA
Fig. 11 Circuit for note 7.
8.
Fig. 12 Equivalent circuit for PCl
sink current.
7Z84484
9.
Fig. 13 Equivalent circuit for PCl
sou rce cu rrent.
7Z84485
10. This guarantees the d.c. voltage gain, combined with d.c.-offset.
Input condition: 0,3 VOO ~ VTCC ~ 0,7 VOO'
f:l.V = VpCl-VTCC'
TCC
Fig. 14 Circuit for note 10.
7Z84486
64
October 1980
1(
Vss
J
Frequency synthesizer
HEF4750V
LSI
~~-
11. Switching level at TCA, generating an EOR-signal, during increasing input voltage.
12.
Fig. 15 Waveform at the output.
13. Definition of the ramp linearity at full swing.
"' ramp waveform
7Z84488
Fig. 16 flV is the maximum deviation of the ramp waveform to the straight line, which joins the
30% VDD and 70% VDD points.
Linearity
=~ x
100%.
%VDD
14. The external components and modulation input voltage must be chosen such that this requirement
will be fulfilled, to ensure that CA is sufficiently discharged during that time.
'I
(october 1980
65
l_~__
HEF4750V
LSI
NOTES (continued)
15. Circuit connections for power supply current specification, with speed-up 1 : 10. V and R are in the
range of PC1, such that the output voltage at PCl is equal to 5 V.
fOSC = 5 MHz (external clock)
fSTB = 12,5 kHz
fV = 125 kHz
~--------'-------+---+10V
NS O NS 1
\,
Y
division ratio = 40
V DD
+5V
OUT
MOD
PC 1
R
HEF4750V
V
SL
JL.
PC 2
STB
OL
VSS
'/
TRA
TCA
TCB
TeC
..---~----+-----e-
OSC XTAL
VSS
7Z84489
Fig. 17 Circuit for note 15.
66
October 1980
'I (
J
Frequency synthesizer
HEF4750V
LSI
~~-
16. Circuit connections for power supply current specification, without speed-up. Vand R are in the
range of PC1, such that the output voltage at PC 1 is equal to 5 V.
fOSC = 5 MHz (external clock)
fSTB = 12,5 kHz
fV = 12,5 kHz
~----'---'-----------+10V
NS O NS 1 AO-------------Ag
I
y
VDD
OUT
division ratio = 400
MOD
PC 1
R
HEF4750V
V
PC 2
STB
\
+5V
JL
SL
~
OL
VSS
TRA
TCA
TCB
t---------~-
XTAL
_____-
VSS
7Z84490
Fig. 18 Circuit for note 16.
"I (
October 1980
67
l_______~~
HEF4750V
LSI
v
50%
- - tpWVH
R
- - - 1 .....
-----
50%
1---- tpWR H
tpWVL
----...-I
----·1-.----
tpWR L -----I~I
STB
-
tpWSH-I--+-------1f--- tpWSL ------I.,~I
forbidden
zone --------------------~~
50ns ---
------------Voo
TCA
(analogue)
tfCA -+----1
tVCA~
tVCB--tCBCA
---------------VOO
TCB
(analogue)
0,5V
trCB-
10%
.,......--..;.---------- VSS
--
---I
7Z84475
(1) Forbidden zone in the locked state for the positive edge of V and R and both edges of STB.
Fig. 19 Waveforms showing times in the locked state.
68
I(
October 1980
_~_J
HEF4751V
LSI
UNIVERSAL DIVIDER
The HEF4751 V is a universal divider (U.O.) intended for use in high performance phase lock loop
frequency synthesizer systems. It consists of a chain of counters operating in a programmable feedback
mode. Programmable feedback signals are generated for up to three external (fast) -:-10/11 prescaler.
The system comprising one HEF4751 V U.O. together with prescalers is a fully programmable divider
with a maximum configuration of: 5 decimal stages, a programmable mode M stage (1 ~ M ~ 16, nondecimal fraction channel selection), and a mode H stage (H = 1 or 2, stage for half channel offset).
Programming is performed in BCD code in a bit-parallel, digit-serial format.
To accommodate fixed or variable frequency offset, two numbers are applied in parallel, one being
subtracted from the other to produce the internal programme.
The decade selection address is generated by an internal programme counter which may run continuously or on demand. Two or more universal dividers can be cascaded, each extraU.O. (in slave mode) adds
two decades to the system. The combination retains the full programmability and features of a single U.O.
The U.O. provides a fast output signal FF at output OFF, which can have a phase jitter of ± 1 system
input period, to allow fast frequency locking. The slow output signal FS at output OFS, which is
jitter-free, is used for fine phase control at a lower speed.
OFS OFB 2 _
OSY
OFB 3
OFB
1
IN
SI
HEF4751V
00 1 00 0 PE
7Z84464
Fig. 1 Pinning diagram.
SUPPLY VOLTAGE
rating
recommended
operating
-0,5 to +18
4,5 to 12,5 V
FAMILY DATA
HEF4751 VP : 28-lead 01 L; plastic (SOT117).
HEF4751VO: 28-lead 01 L; ceramic (cerdip) (SOT135A).
HEF4751VT: 28-lead mini-pack; plastic
(S028; SOT136A).
}
see Family Specifications
IDD LIMITS category LSI
' ] (May 1983
69
HEF4751V
LSI
3
4
1
2
4
SUBTRACTOR
18 B2
C
0
0
19 B3
:\:~
r-- I
r------
8
~
---
7
6
5
---
----
00 6
PROGRAMME
I+r---
-----?-
_J
1
3
4
21 OSY
B3,B 2
LATCH
n ms
f--++
COb
+1,2,5,10/11
o ) __
I
I~
+nmslnms+1
--j---- )
RS
switches
+10
11
RS4
24 OFB 3
RS3
i
d3
! LATCH
n3
d2
LATCH
LATCH
! LATCH
:
+M
fBo
H
1-----C4
I-r+-
OFS
f-+- ~
+H
OFF 27
I
I
4
+
n2
11
22 OFB 1
I
~
4
+
11
RS2
+
LATCH
: n4
:
23 OFB 2
j
d4
d6
I
~
C3
C2
f-+-
11
-
I
4
!++--
RS1
RSO
-----
-----
LATCH
n1
LATCH
4
nO
d6-+
+ci 1
d;+
Ai
--+- ~
RSH
8 1 -----LATCH
nh
VSS
7Z84471
114
Fig. 2 Block diagram.
70
load
I- pulses
M
C1
PRESCALER
128
6
------
1--------
1--------
V DD
5
d6
LATCH
20 IN
COUNTER
?~
+ + + • • d• d+ __
dO d d2 d d
d6
I
~
12
PE
13
PC
PROGRAMME DECODER
2 I
4
9
---- --.-
----
d sub
CARRY FF
10
00 0 - ----
SI
16 BO
17 B1
11
15
AO A1 A2 A3
'I (
October 1980
-0 OFF
C-2
~
C-l
I--+--
input
(fil
liN
I
COa
COb
I--+-
Cl
I
+ 10/11
f--+--
+10/11
I-+-
losy
+ 10/11,
5/6,2/3
+1,2,5,
10/11
I
r-+-
+n5/
n5+ 1
C2
I--+-+10
t L-y-----J
C4
C3
+M
+H
RSO
RSH
:::::s
~.
~
~ OFS
f--+--
f- ........
C
ce:.
a:
~
111~
+ 10/11
RS4
I
I
I
n4
I
1
1~OFB3
~
I
---
ll- l
RS3
....
Y
n3
I
I
~
I
I
~
:-
n2
1
1
-r11
I
lOFB 1
C')
r-+
o
~
RSl
I
c-
~
RS2
lOFB 2
o
II
r-+-
~
I
EXTERNAL PRESCALER
I
UNIVERSAL DIVIDER
n,
r--+nO
I
7Z84469
~
co
(X)
o
f--+-o RI
nh
I
m
Fig. 3 The HEF4751 V U.D. used in a system with 3 (fast) prescalers.
1 ~ M ~ 16; 1 ~ H ~ 2; n5 > 0; fj/fOFS
= {(n5 . 10 + n4 . 10 + n3 . 10 + n2 . 10 + n1)
4
3
2
M + nO} H + nh.
r
"
~~
-...J
....
01
.....
-'
<
HEF4751V
LSI
JLrLrLrLrLrLrLrLrLrLrLrLrLrLrLIL
PC
I
PE
000
L...--I
00 1
~I
~
'--I
~I
L...--I
~I
~I
rl
I
I
:Jt.~~GCL.L._-I?0;IICLL4..--!~~--!~~---l~~---l~'"'-~~CLL.!-~~CLL.!---;----!of321~--f'fmCLL!-~~~~'f"L'~~
data valid
(shaded)
I 10 1
61
fetch period
11
I
12 \
\3\
141
15 \
61
1
\
10
1
11 1
\6\ 6
1
6 I 6
7Z84467
Fig. 4 Timing diagram showing programme data inputs.
Allocation of data input
fetch
period
inputs
A3
A2
A1
a
1
2
3
4
5
nOA
n1A
n2A
n3A
n4A
n5A
6
M
AO
B3
B2
B1
BO
nOB
n1B
n2B
n3B
n4B
n5B
cab
% channel
control control
I
51
bin
X
X
X
X
X
X
Allocation of data input B3 to BO during fetch period 6
B3
B2
cab division ratio
B1
L
L
L
H
L
L
H
H
H
1
2
5
10/11
L
H
H
H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
72
1(
October 1980
BO
% channel configuration
L
H=1
H = 2; nh = a
H = 2; nh = 1
test state
H
H
L
HEF4751V
Universal divider
LSI
PROGRAMME DATA INPUT (see also Figs 3 and 4)
The programming process is timed and controlled by input PC and PE. When the programme enable
(PE) input is HIGH, the positive edges of the programme clock (PC) signal step through the internal
programme counter in a sequence of 8 states. Seven states define fetch periods, each indicated by a
LOW signal at one of the corresponding data address outputs (000 to 006)' These data address
signals may be used to address the external programme source. The data fetched from the programme
source is applied to inputs AO to A3 and 80 to 83' When PC is LOW in a fetch period an internal load
pulse is generated, the data is valid during this time and has to be stable. When PE is LOW, the
programming cyclus is interrupted on the first positive edge of PC. On the next negative edge at input
PC fetch period 6 is entered. Data may enter asynchronously in fetch period 6.
Ten blocks in the U.D. need programme input signals (see Fig. 2). Four of these (COb, C3, C4 and RSH)
are concerned with the configuration of the U.D. and are programmed in fetch period 6. The remaining
blocks (RSO to RS4 and Cl) are programmed with number P, consisting of six internal digits nO to n5.
P = (n5' 104 + n4 .10 3 + n3 .10 2 + n2 ·10 + nl) . M + nO
These digits are formed by a substractor from two external numbers A and B and a borrow-in (bin).
P = A - B - bin or if this result is negative; P = A - B - bin + M . lOs.
The numbers A and B, each consisting of six four bit digits nOA to n5A and nOB to n5B, are applied in
fetch period 0 to 5 to the inputs AO to A3 (data A) and 80 to 83 (data B) in binary coded negative
logic.
A
= (n5A
. 104 + n4A . 10 3 + n3A . 10 2 + n2A . 10 + n1A) . M + nOA·
4
B = (n5B' 10 + n4B' 103 + n3B' 10 2 + n2B' 10+ nlB)' M + nOB·
Borrow-in (bin) is applied via input SI in fetch period 0 (SI = HIGH: borrow, SI ;;; LOW: no borrow).
Counter C1 is automatically programmed with the most significant non-zero digit (n ms ) from the
internal digits n5 to n2 of number P. The counter chain C - 2 to Cl (see Fig. 3) is fully programmable
by the use of pulse rate feedback.
Rate feedback is generated by the rate selectors RS4 to RSO and RSH, which are programmed with
digits n4 to nO and nh respectively. In fetch period 6 the fractional counter C3, half channel counter
C4 and COb are programmed and configured via data B inputs. Counter C3 is programmed in fetch
period 6 via data A inputs in negative logic (except all HIGH is understood as: M;;; 16). The counter
CO is a side steppable 10/11 counter composed of an internal part COb and an external part COa. COb
is configured via 83 and 82 to a division ratio of 1 or 2 or 5 or 10/11; COa must have the complementary
ratio 10/11 or 5/6 or 2/3 or 1 respectively. I n the latter case COb comprises the whole CO counter
with internal feedback, COa is then not required.
The half channel counter C4 is enabled with 80 = HIGH and disabled with 80;;; LOW. With C4
enabled, a half channel offset can be programmed with input 81 ;;; HIGH, and no offset with 81 ;;; LOW.
1
(October 1980
73
HEF4751V
LSI
FEEDBACK TO PRESCALERS (see also Figs 5 and 6)
The counters Cl, CO, C-l and C-2 are side-steppable counters, i.e. its division ratio may be increased by
one, by applying a pulse to a control terminal for the duration of one division cycle. Counter C2 has
10 states, which are accessible as timing signals for the rate selectors RSl to RS4. A rate selector,
programmed with n (nl to n4 in the U.D.) generates n of 10 basic timing periods an active signal. Since
n ~ 9, 1 of 10 periods is always non-active. In this period RSl transfers the output of rate selector RSO,
which is timed by counter C3 and programmed with nO. Similarly, RSO transfers RSH output during
one period of C3. Rate selector RSH is timed by C4 and programmed with nh. In one of the two states
of C4, if enabled, or always, if C4 is disabled, RSH transfers the LOW active signal at input AT to RSO.
If AT is not used it must be connected to HIGH. The feedback output signals of RS1, RS2 and RS3 are
externally available as active LOW signals at outputs OFB1, OFB2 and OFB3.
Output OFBl is intended for the prescaler at the highest frequency (if present), OFB2 for the next
(if present) and OFB3 for the lowest frequency prescaler (if present). A prescaler needs a feedback
signal, which is timed on one of its own division cycles in a basic timing period. The timing signal at
OSY is LOW during the last U.D. input period of a basic timing period and is suitable for timing of the
feedback for the last external prescaler. The synchronization signal for a preceding prescaler is the ORfunction of the sync. input and sync. output of the following prescaler (all sync. signals active LOW).
C-1
710/11
0 - - IN"
CO a
OUT"
f-+-
75/6
IN'
IN
a UT' I---+--I--~
f--
s'
PE'
O_S_yL---.......-......
1
Sy'
II I I
RS2
II I I
RS1
UNIVERSAL DIVIDER
7Z84466
Fig. 5 Block diagram showing feedback to prescalers.
74
October 1980
1(
HEF4751V
Universal divider
LSI
b.t.p. (n-1)
b.t.p. (n+1)
basic timing period (n)
-I"
IN'
eo
(1)
{ eO
a
IN, OUT'
PE'
OSY
S'
SY'
PE"
C-1
(1)
- - - - - - - - - - - - - +10 - - - - - - - - - - - - + - + - - - +10
+11
7Z84468
(1) scaling factor
Fig. 6 Timing diagram showing signals occurring in Fig. 5.
1(
October 1980
75
HEF4751V
LSI
CASCADING OF U.D.s (see also Fig. 8)
A U.D. is programmed into the 'slave' mode by the programme input data: n2A = 11, n2B = 10,
n3A = n4A = n3B = n4B = n5B = O. A U.D. operating in the slave mode performs the function of two
extra programmable stages C2' and C3' to a 'master' (not slave) mode operating U.D. More slave U.D.s
may be used, every slave adding two lower significant digits to the system.
Output OFB3 is converted to the borrow output of the programme data subtractor, which is valid after
fetch period 5. Input 51 is the borrow input (both in master and in slave mode), which has to be valid
in fetch period O. Input 51 has to be connected to output OFB3 of a following slave, if not present, to
LOW. For proper transfer of the borrow from a lower to a higher significant U.D. subtractor, the U.D.s
have to be programmed sequentially in order of significance or synchronously if the programme is
repeated at least the number of U.D.s in the system.
Rate input RT and output OF5 must be connected to rate output OFB1 and the input IN of the next
slave U.D. The combination thus formed retains the full programmability and features of one U.D.
OUTPUT (see also Fig. 7)
The normal output of the U.D. is the slow output OF5, which consists of evenly spaced LOW pulses.
This output is intended for accurate phase comparison. If a better frequency acquisition time is
required, the fast output OFF can be used. The output frequency on OFF is a factor M • H higher than
the frequency on OF5. However, phase jitter of maximum ±1 system input period occurs at OFF,
since the division ratio of the counters preceding OFF are varied by slow feedback pulse trains from
rate selectors following OFF.
OF5
LJ
LJ
Fig.7 Timing diagram showing output pulses.
76
1(
October 1980
AotoA3
PC
PE
BOtoB3
~~
--T--
PC'
PE'
AO' to A 3 '
C
BO' to B3 '
~~
::l
<.
CD
---,
~
Co
<.
c.:
..,CD
I
I
PROGRAMME
COUNTER
DECODER
I
I
PROGRAMME
COUNTER
DECODER
DATA
SUBTRACTOR
DATA
SUBTRACTOR
IN
C4
OSY
+H
51'
OFSIIN'
OFS'
OFFI
'-----------~n
OFF'
I I
OFB 2 0
+
o
(')
r-+
o
c~
co
00
o
RS1' ~ RSO'
OFB 1
!
L
MASTER UNIVERSAL DIVIDER
(n2A';;;;9;n2B';;;;9)
- _________________________
RSH'
I-----<:> RI'
SLAVE UNIVERSAL DIVIDER
I
I_ _ _ _ _ _(n2A=11;n2B=10)
______________ J
!
I
m
I
~
1284470
Fig. 8 Block diagram showing cascading of U.Ds.
.....
.....
1---1
r-
-n
~
~ -...J
.....
<
(]1
HEF4751V
LSI
D.C. CHARACTERISTICS VSS = 0 V
VOO
V
Output (sink)
current LOW
VOH
V
4,75
5
10
Output (source)
current HIGH
5
5
10
Tamb (OC)
+25
min.
max.
+85
min.
max.
IOL
1,6
1,7
2,9
1,4
1,5
2,7
1,1
1,2
2,2
mA
mA
mA
-IOH
1,0
3,0
3,0
0,85
2,5
2,5
0,55
1,7
1,7
mA
mA
mA
-40
VOL symbol
max.
min.
V
0,4
0,4
0,5
4,6
2,5
9,5
A.C. CHARACTERISTICS
VSS
= 0 V; T amb = 25 oC; input transition times ~ 20 ns
VOO
V
parameter
min.
typo
max.
unit
5
10
tpHL
135
45
270
90
ns
ns
CL
= 10 pF
5
10
tTHL
30
12
60
25
ns
ns
CL
= 50 pF
5
10
tTLH
45
20
90
40
ns
ns
CL
= 50 pF
Maximum input
frequency; IN
5
10
f max
4
12
8
24
MHz
MHz
{ 5 = 50%
COb ratio> 1
Maximum input
frequency; IN
.5
10
f max
2
6
4
12
MHz
MHz
{ 5 = 50%
COb ratio
Maximum input
frequency; PC
5
10
f max
0,15
0,5
Voo
V
typical formula for P (pW)
Propagation delay
IN - . OSY
HIGH to LOW
Output transition
times
HIGH to LOW
LOW to HIGH
Oynamic power
dissipation per
package (P)
78
symbol
May 1983
5
10
1(
0,3
1,0
1 200 fi + ~(foCL) x VOO 2
5400 fi + ~(foCL) x VOO 2
=1
MHz
MHz
where
fi = input freq. (M Hz)
fo = output freq. (MHz)
CL = load capacitance (pF)
~(foCL) = sum of outputs
VOO = supply voltage (V)
MAB84X1
MAF84X1
MAF84AX1
FAMILY
FOR DETAILED INFORMATION SEE RELEVANT DATABOOK OR DATASHEET.
SINGLE-CHIP 8-BIT MICROCONTROLLER
DESCRIPTION
The MAB84X1 family of microcontrollers is fabricated in NMOS. The family consists of 5 devices:
• MAB8401
•
•
•
•
MAB/MAF8411
MAB/MAF8421
MAB/MAF8441
MAB/MAF8461
- 128 bytes RAM, external program memory, with 8-bit LE D-driver (1 OmA),
emulation of MAB/F8422/42* possible
- 1 K byte ROM/64 bytes RAM plus 8-bit LE D-driver
- 2K bytes ROM/64 bytes RAM plus 8-bit LED-driver
- 4K bytes ROM/128 bytes RAM plus 8-bit LED-driver
- 6K bytes ROM/128 bytes RAM plus 8-bit LED-driver
Each version has 20 quasi-bidirectional I/O port lines, one serial I/O line, one single-level vectored
interrupt, an 8-bit timer/event counter and on-board clock oscillator and clock circuits. Two 20-pin
versions, MAB/F8422 and MAB/F8442* are also available.
This microcontroller family is designed to be an efficient controller as well as an arithmetic processor.
The instruction set is based on that of the MAB8048. The microcontrollers have extensive bit handling
abilities and facilities for both binary and BCD arithmetic.
For detailed information see the "8-bit Single-chip Microcontrollers user manual".
* See data sheet on MAB/F8422/42.
Features
•
•
•
•
•
•
•
•
•
•
•
•
8-bit: CPU, ROM, RAM and I/O in a single 28-lead 01 L package
1 K, 2K, 4K or 6K ROM bytes plus a ROM-less version
64 or 128 RAM bytes
20 quasi-bidirectional I/O port lines
Two testable inputs: one of which can be used to detect zero cross-over, the other is also the
external interrupt input
Single level vectored interrupts: external, timer/event counter, serial I/O
Serial I/O that can be used in single or multi-master systems (serial I/O data via an existing port line
and clock via a dedicated line)
8-bit programmable timer/event counter
Internal oscillator, generated with inductor, crystal, ceramic resonator or external source
Over 80 instructions (based on MAB8048) all of 1 or 2 cycles
Single 5 V power supply (± 10%)
MAB84X1 family
Operating temperature ranges:
0 to + 70 0 C
-40 to + 85 0 C
MAF84X1 family only
-40 to + 11 0 0C
MAF84AX1 family only
PACKAGE OUTLINES
MAB8401 B: 28-lead 'Piggy-back' package (with up to 28-pin EPROM on top).
MAB8401WP: 68-lead plastic leaded chip-carrier (PLCC) (SOT188).
MAB/MAF8411/21/41/61 P: 28-lead 01 L; plastic (SOT117).
MAF84A11/21/41/61P: 28-lead OIL; plastic (SOT117).
MAB8411/21/41/61T: 28-lead mini-pack; plastic (S028; SOT163A).
1
(December 1987
79
l_ __
MAB84X1
MAF84X1
MAF84AX1
FAMILY
SERIAL DATAl P2.3
P1.7- Pl.0
PO.7 -PO.O
SCLK
(pin 3)
CLOCK
REGISTER 0
REGISTER 1
a-I
1:
REGISTE R 2
REGISTER 3
REGISTER 4
REGISTER 5
EXSI
_TEST 0
~
POWER {
SUPPLY
_TEST 1
external
interrupt
VSS
-GND
CONDITIONAL _
TIMER
BRANCH
FLAG
LOGIC
_CARRY
D
E
C
REGISTER 6
0
8 LEVEL STACK
(VARIABLE LENGTH)
D
E
REGISTER 7
OPTIONAL SECOND
REGISTER BANK
DATA STORE
_ACC
ACC BIT
TEST
RESIDENT RAM ARRAY
INTERRUPT INITIALIZE
OSCILLATOR
XTAL
(1) EXSI and EMU20 for 8401 WP only
lZ83139.5
8401: 128 BYTES
8411: 64 BYTES
8421: 64 BYTES
8441 : 128 BYTES
8461 : 128 BYTES
Fig.4a Block diagram of the MAB84Xl family.
,------I
r--------------,
AO-A12
AO-A12
I
DO-D7
I
I
: PSEN
I
I
CLK
C1
I
I
I
PSEN
I
: HALT
I
I INTA
L___
13
I
I
_ _ _ _ _ _ _ -J
I
I
IL
I
I
___
13
_ _ _ _ _ _ _ .JI
lZ91968
Fig. 4b Replacement for dotted part in Fig. 4a
for the MAB8401WP bond-out version.
80
December
19871 (
Fig.4c Replacement of dotted part in Fig. 4a
for the MAB8401 B 'Piggy-back' version.
MAB8422/42
MAF8422/42
MAF84A22/A42
FOR DETAILED INFORMATION SEE RELEVANT DATA BOOK OR DATA SHEET
SINGLE-CHIP 8-BIT MICROCONTROLLER
DESCRIPTION
The MAB8422/8442 is a high-performance microcontroller incorporating dedicated hardware, memory
capacity and I/O lines. This dedication means a microcontroller can be economically installed in
high-volume products where its main function is control.
The MAB8422/8442 is a 20 pin, single-chip 8-bit microcontroller that has been developed from the
28 pin MAB8421/8441 microcontrollers. The versions are:
• MAB8422 - 2K x 8 ROM/64 bytes RAM
• MAB8442 - 4K x 8 ROM/128 bytes RAM
Each version has 15 I/O port lines comprising one 8-bit parallel port (PO), one 2-bit parallel port (Pl.0
and Pl.l that are shared with the serial I/O lines SOA and SCL), one 3-bit parallel port (P2.0 - P2.2) and
two input lines (INT/TO and Tl).
The serial I/O interface is 12 C compatible and therefore the MAB8422/8442 can operate as a slave or
a master in single and multi-master systems. Conversion from parallel to serial data when transmitting,
and vice versa when receiving, is done mainly in software. There is a minimum of hardware for the
serial I/O implemented. This hardware is controlled by the status of the SOA and SCL lines and can
be read or written under software control. Standard software for 12 C-bus control is avai lable upon
request. For detailed information see the user manual 'Single-chip 8-bit microcontrollers'.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit: CPU, ROM, RAM and I/O
20 pin package
MAB8422: 2K x 8 ROM/64 bytes RAM
MAB8442: 4K x 8 ROM/128 bytes RAM
13 quasi-bidirectional I/O port lines
Two testable inputs Tl and INT/TO
High current output on PO (IOL = 10 mA at VOL = 1 V)
One interrupt line combined with the testable input line I NT/TO
Single-level interrupts: external, timer/event counter, serial I/O
2
1 C-compatible serial I/O that can be used in single or multi-master systems (serial I/O data and clock
via PLO and Pl.l port lines, respectively)
8-bit programmable timer/event counter
Internal oscillator, generated with inductor, crystal, ceramic resonator or external source
Over 80 instructions (based on MAB8048)
All instructions 1 or 2 cycles, cycle time dependent on oscillator frequency
Single power supply
Operating temperature ranges:
0 to +70 oC (MAB84X2)
-40 to +85 oC (MAF84X2)
-40 to +110 oC (MAF84AX2)
PACKAGE OUTLINES
MAB/MAF84X2, MAF84AX2: 20-lead 01 L; plastic (SOT146).
1
(November 1987
81
MAB8422/42
MAF8422/42
MAF84A22/A42
l
_______________________________________
r----------,
PLO/SDA
Pl.l/SCL
:
I
I
I
I
I
I
i
RESIDENT ROM
PO.7 - PO.O
I
~I____- ,
8422 : 2 K BYTES
8442 : 4 K BYTES
L_
L..-_-_-_""'A:------'
SIO
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
REGISTER 6
REGISTER 7
8 LEVEL STACK
(VARIABLE LENGTH)
TEST 0
VCC
POWER{SUPPLY
~GND
TEST 1
external
interrupt
OPTIONAL SECOND
REGISTER BANK
TIMER
FLAG
ACC
DATA STORE
ACC BIT
TEST
RESIDENT RAM ARRAY
INTERRUPT
INITIALIZE
OSCILLATOR
XTAL
7Z80477.2
Fig. 1 Block diagram of the MAB8422/8442.
82
November 19871 (
8422: 64 BYTES
8442 : 128 BYTES
MC3410, MC3510,
MC3410C
10-Bit High-Speed Multiplying
D/ A Converter
Product Specification
DESCRIPTION
The MC341 a series are 1a-bit Multiplying Digital-to-Analog Converters. They
are capable of high-speed performance,
and are used as general-purpose building blocks in cost-effective OJ A systems.
The Signetics' design provides complete
1a-bit accuracy without laser trimming,
and guaranteed monotonicity over temperature. Segmented current sources, in
conjunction with an R-2R DAC provides
the binary weighted currents. The output
buffer amplifier and voltage reference
have been omitted to allow greater
speed, lower cost, and maximum user
flexibility.
FEATURES
• 10-bit resolution and accuracy
(±0.05%)
• Guaranteed monotonicity over
temperature
• Fast settling time - 250ns typical
• Digital inputs are TTL and CMOS
compatible
• Wide output voltage compliance
range
• High-speed multiplying input slew
rate - 20mA/IlS
• Reference amplifier internallycompensated
F Package
• Standard supply voltages + 5V
and -15V
APPLICATIONS
• Successive approximation AID
converters
• High-speed, automatic test
equipment
• High-speed modems
• Waveform generators
•
•
•
•
CRT displays
Strip CHART and X-V plotters
Programmable power supplies
Programmable gain and
attenuation
BLOCK DIAGRAM
MSB
LSB
vee
November 14, 1986
PIN CONFIGURATION
83
GND
TOP VIEW
Product Specification
10-Bit High-Speed Multiplying
D/ A Converter
MC3410, MC3510, MC3410C
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
o to
o to
16-Pin Cerdip
16-Pin Cerdip
16-Pin Cerdip
ORDER CODE
+70°C
MC3410F
+70°C
MC3410CF
-55°C to +125°C
MC3510F
ABSOLUTE MAXIMUM RATINGS TA = + 25°C unless otherwise noted
SYMBOL
Vee
VEE
PARAMETER
Power supply
VI
Digital input voltage
Vo
Applied output voltage
IREF(16)
Reference current
VREF
Reference amplifier inputs
RATING
UNIT
+7.0
-18
Voe
Voc
+15
Voc
0.5, -5.0
Voe
2.5
mA
Vee, VEE
Voe
VREF(O)
Reference amplifier differential inputs
0.7
Voc
TA
Operating ambient temperature range
MC3510
MC3410, 3410C
-55 to +125
o to +70
°C
°C
Junction temperature, ceramic
package
+150
°C
Maximum power dissipation,
TA = 25°C (still-air) 1
F package
1190
mW
TJ
Po
NOTE:
1. Derate above 25°C, at the following rates:
F package at 9.5mWfOe
November 14, 1986
84
Product Specification
10-Bit High-Speed Multiplying
DjA Converter
MC3410, MC3510, MC3410C
DC AND AC ELECTRICAL CHARACTERISTICS
vcc = + 5.0Voc. VEE = - 150c. VREF = 2.0mA. all digital inputs at high
logic level.
R16
MC3510: TA =-55°C to + 125°C. MC3410 Series: TA=O°C to + 70°C.
unless otherwise noted.
MC3410, MC3510
SYMBOL
PARAMETER
UNIT
Min
Er
MC3410C
TEST CONDITIONS
Relative accuracy
(error relative to full-scale 10)
Typ
TA = 25°C
Max
Min
Typ
Max
±0.05
±0.1
%
1;4
h
LSB
TCE r
Relative accuracy drift
(relative to full-scale 10)
t8
Settling time to within ± Y2 LSB
(all bits LOW-to-HIGH)
TA = 25°C
250
250
ns
tpLH
tpHL
Propagation delay time
TA = 25°C
35
20
35
20
ns
TClo
Output full scale current drift
VIH
Digital input logic levels (all bits)
HIGH-level. Logic "1"
LOW-level. Logic "0"
Monotonicity
2.5
Over temperature
2.5
10
ppmfOC
10
Bits
60
2.0
0.8
70
ppm/oC
Voc
2.0
0.8
Digital input current (all bits)
HIGH-level. VIH = 5.5V
LOW-level. VIL = 0.8V
-0.05
+.04
-0.4
-0.05
+.04
-0.4
IREF(15)
Reference input bias current (Pin 15)
-1.0
-5.0
-1.0
-5.0
p.A
lOR
Output current range
4.0
5.0
4.0
5.0
mA
IOH
Output current (all bits high)
VREF = 2.000V.
R16 = 1000.(2
3.996
4.2
3.996
4.2
mA
IOL
Output current (all bits low)
TA = 25°C
4.0
J1A
-2.5
+0.2
Voc
IIH
IlL
Va
Output voltage compliance
SR IREF
Reference amplifier slew rate
ST IREF
Reference amplifier settling time
PSRR(-)
Output current power supply sensitivity
Co
Output capacitance
CI
Digital input capacitance
(all bits high)
Icc
lEE
Power supply current
(all bits low)
Vcc
VEE
Power supply voltage range
0
o to
4.0mA. ±0.1%
20
20
2.0
0.003
J1s
0.02
%/%
25
pF
4.0
4.0
pF
+18
-20
-11.4
+18
-20
+4.75 +5.0 +5.25 +4.75 +5.0 +5.25
-14.25 -15 -15.75 -14.25 -15 -15.75
220
200
85
0.01
mAlJ1s
25
-11.4
TA = 25°C
0
2.0
0.003
Vo =0
2.0
3.8
-2.5
+0.2
TA = 25°C
Power consumption
(all bits low)
(all bits high)
November 14. 1986
3.8
mA
380
220
200
380
mA
Voc
mW
Product Specification
10-Bit High-Speed Multiplying
D/ A Converter
4.0
!.
15
II:
3.0
II
II
2.0
II:
1.0
g~
(
-3
-1 0
1
"1
2.0
I I
1.0
+Vec. +5V -VEE- -15V
IREF=2mA -
w
~ -1.0
A-
I
I
I
II
-1.0
-5
4.0
3.0
o
z
!
;:)
A-
I-
;:)
0
CJ
VEE= -15.0V_
T.... 25·C
IREF~2 ~A -
;:)
0
w
Jee~ +~.oJ
I-
I-
~
~
I
I
!f
c-
MC3410, MC3510, MC3410C
~ -2.0
o
I-
3
~
5
5
-3.0
-4.0
-75-SO-25 0
Figure 1. Output Current
V8
i
13
~
12 f-- t-- I--I!E
w
II:
II:
;:)
11
o
~
10
t
iil
I
I I
Vee. +5V-VEE: -15V
IREF=2 mA-
I
I
II:
5~ =!:~
W
~
+Iee
A-
-6.0
-8.0
-10
-12
~
]
0
-75-SO-25
0
25
so
November 14, 1986
V8
'0=200
~~~~~~;; XtP+ 1.0V
~~~~~~~~~~w
0.1
75 100 125
T... ("C)
Figure 3. Power Supply Current
75 100 125
18.0 r--,--rTTTTTn----.--.-.........,.,..,...,
16.0
R15=R16=1.0k
14.0 B CURVE
VREF(-)-OV
m '2.0 SMALL·SIGNAL BW
~ 10.0
8.0
6.0
4.0 I---+-t-+++t+tt-~y.-\-i-++~
2.0 1---+-t-++tH......~-+-ti-++~
~
0 t--+...,."""~tt--4-+-+\l-++~
I
I
so
Figure 2. Maximum Output Compliance
Voltage V8 Temperature
Output Compliance Voltage
I
!
25
T... (·C)
COMPLIANCE VOLTAGE (VOLTS)
Temperature
0.20.3 0.5 1.0 2.03.0 5.0
f, FREQUENCY (MHz)
10
Figure 4. Reference Amplifier Frequency Response
86
Product Specification
10-Bit High-Speed Multiplying
DI A Converter
CIRCUIT DESCRIPTION
The MC3410 consists of four segment current sources which generate the two most
significant bits (MSBs), and an R-2R DAC
implemented with ion-implanted resistors for
scaling the remaining eight least significant
bits (LSBs) (See Figure 5). This approach
provides complete 10-bit accuracy without
trimming.
The individual bit currents are switched ON or
OFF by fully differential current switches. The
switches use current steering for speed.
An on-chip high-slew reference current amplifier drives the R-2R ladder and segment
decoder. The currents are scaled in such a
way that, with all bits on, the maximum output
current is two times 1023/10?4 of the reference amplifier current, or nominally 3.996mA
for a 2.000mA reference input current. The
reference amplifier allows the user to provide
a voltage input. Out-board resistor R16 (see
Figure 6) converts this voltage to a usable
current. A current mirror doubles this reference current and feeds it to the segment
MC3410, MC3510, MC3410C
decoder and resistor ladder. Thus, for a
reference voltage of 2.0V and a 1kn resistor
tied to Pin 16, the full-scale current is approximately 4.0mA. This relationship will remain
regardless of the reference voltage polarity.
Connections for a positive reference voltage
are shown in Figure 6a. For negative reference voltage inputs, or for bipolar reference
voltage inputs in the multiplying mode, R15
can be tied to a negative voltage corresponding to the minimum input level. For a negative
reference input, R16 should be grounded
(Figure 6b). In addition, the negative voltage
reference must be at least 3V above the VEE
supply voltage for best operation. Bipolar
input signals may be handled by connecting
R16 to a positive voltage equal to the peak
positive input level at Pin 15.
When a DC reference voltage is used, capacitive bypass to ground is recommended. The
5V logic supply is not recommended as a
reference voltage. If a well regulated 5.0V
supply, which drives logic, is to be used as
the reference, R16 should be decoupled by
connecting it to the + 5.0V logic supply
through another resistor and bypassing the
junction of the two resistors with a 0.1 iJ.F
capacitor to ground.
The reference amplifier is internally-compensated with a 10pF feed-forward capacitor,
which gives it its high slew rate and fast
settling time. Proper phase margin is maintained with all possible values of R16 and
reference voltages which supply 2.0mA reference current into Pin 16. The reference
current can also be supplied by a high impedance current source of 2.0mA. As R16 increases, the bandwidth of the amplifier decreases slightly and settling time increases.
For a current source with a dynamic output
impedance of 1.0Mn, the bandwidth of the
reference amplifier is approximately half what
it is in the case of R16 = 1.0kn, and settling
time is ~ 10iJ.s. The reference amplifier phase
margin decreases as the current source value
decreases in the case of a current source
reference, so that the minimum reference
current supplied from a current source is
0.5mA for stability.
(4)
(13)
MSB
(7)
(8)
(9)
(10)
(11)
(12)
LSB
D1
Dc
D5
Ds
D7
De
D,
D10
GND
(2)
V81AS
(INTERNAL)
2R
2R
2R
2R
2R
R
(18)
CODE SELECTED 0111110011
(15)
VEE (1)
Figure 5. MC3410 Equivalent Circuit
November 14, 1986
87
Product Specification
10-Bit High-Speed Multiplying
0/A Converter
MC3410, MC3510, MC3410C
The MC3510 and the MC3410 are accurate
to within ± 0.05% at 25°C with a reference
current of 2.0mA on Pin 16.
MONOTONICITY
0, THROUGH
0,o
I
=
Vee
R,S + RT R,s = RReF
RT < < R,s
10 F.S. = 2 IR z VReF/RReF
The MC3410, MC3510 and MC3410C are
guaranteed monotonic over temperature.
This means that for every increase in the
input digital code, the output current either
remains the same or increases but never
decreases. In the multiplying mode, where
reference input current will vary, monotonicity
can be assured if the reference input current
remains above 0.5mA.
a. Positive Reference Voltage
SETTLING TIME
0, THROUGH
0,0
The worst-case switching condition occurs
when all bits are switched "on," which corresponds to a low-to-high transition for all bits.
This time is typically 250ns for the output to
settle to within ± V2 LSB for 10-bit accuracy,
and 200ns for 8-bit accuracy. The turn-off
time is typically 120ns. These times apply
when the output swing is limited to a small
( < 0.7V) swing and the external output capacitance is under 25pF.
I
R,S+ RT= R'6
RT <: < R,s
VREF '< Vee + 3V
Vee
If a load resistor of 625n is connected to
ground, allowing the output to swing to -2.5V,
the settling time increases to 1.5p.s.
b. Negative Reference Voltage
Figure 6. Basic Connections
OUTPUT VOLTAGE
COMPLIANCE
The output voltage compliance ranges from
-2.5 to +0.2V. As shown in Figure 2, this
compliance range is nearly constant over
temperature. At the temperature extremes,
however, the compliance voltage may be
reduced if VEE> -15V.
ACCURACY
Absolute accuracy is a measure of each
output current level with respect to its intend-
November 14, 1986
The major carry (MSB off-to-on, all others onto-Off) settles in approximately the same time
as when all bits are switched off-to-on.
ed value. It is dependent upon relative accuracy and full-scale current drift. Relative accu-'
racy, or linearity, is the measure of each
output current with respect to its intended
fraction of the full-scale current. The relative
accuracy of the MC341 0 is fairly constant
over temperature due to the excellent temperature tracking, of the implanted resistors.
The full-scale current from the reference
amplifier may drift with temperature causing a
change in the absolute accuracy. However,
the MC3410 has a low full-scale current drift
with temperature.
88
Extra care must be taken in board layout as
this is usually the dominant factor in satisfactory test results when measuring settling time.
Short leads, 100p.F supply bypassing, and
minimum scope lead length are all necessary.
A typical test setup for measuring settling
time is shown in Figure 7. The same setup for
the most part can be used to measure the
slew rate of the reference amplifier (Figure 9)
by tying all data bits high, pulsing the voltage
reference input between 0 and 2V, and using
a 500n load resistor RL.
Product Specification
10-Bit High-Speed Multiplying
D/ A Converter
MC3410, MC3510, MC3410C
Vee
O.l.F
1:
14
16
+2Vdc
RISE AND FALL TIMES" 10ns
2.4V
lk
J
lk
vti
0.4V
O1
. "F
":"500
RL
°~t. -
CO" 25pF
FOR SETTLING TIME
MEASUREMENT.
(ALL BIT SWITCHED
LOW TO HIGH)
O.l.F
~
Vee
250ns TYPICAL
TO :;: 1/2 LSB
USE RL TO GND FOR TURN·OFF MEASUREMENT
":"
50
__________
,o ..
Vo
.J
C:~+
Figure 7. Settling Time
Vee
0'1~
RISE AND FALL TIMES" 10ns
2.4V
14
lk
+ 2Vdc
0.4Vc:=-f-_ _ _ _ _ _---1~-lk
IO.l"F
OV
Vo
-80mVL--~~----------__f
FOR PROPAGATION
DELAY TIME
Vee
Figure 8. Propagation Delay Time
November 14, 1986
89
Product Specification
10-Bit High-Speed Multiplying
D/ A Converter
MC3410, MC3510, MC3410C
Vee
0.1~F
~
14
VREF<+)
1k
18
J1::2V
0
2.0VI
1k
15
VREF<+)
lo.'~F
oL.._...L._ _ _ _ _ _ _ __
":"
MC3510/
MC3410
O.
RL
500
10
Vo
Vo
5V
h
I \
SLEW RATE
o~
J:525 PF
t.=2~. TYPICAL
TO :to.l%
":"
USE RL" 200 TO GND FOR
SLEW RATE MEASUREMENT
":"
VEE
Figure 9. Reference Amplifier Settling Time and Slew Rate
TYPICAL APPLICATIONS
~P
,os
[
~
5-------------1
4-------------~
l::::::::::~:~:;:::::::::::::::::::::~~
..............
CONTROL {E2
F=~:~~
-
10-81T
DAC
(MC3410)
E
E, ______
~~~----__-----------
DATA
THE VALID DATA WILL BE LATCHED TO THE DAC UNTIL UPDATED WITH E2 PULSE.
TIMING WILL DEPEND ON THE PROCESSOR USED.
Figure 10. Interfacing 10-Bit DAC With 8-Bit Microprocessor
November 14, 1986
90
OUTPUT
NE542
Dual Low-Noise Preamplifier
Product Specification
DESCRIPTION
FEATURES
The NE542 is a dual preamplifier for the
amplification of low level signals in applications requiring optimum noise performance. Each of the two amplifiers is
completely independent, with individual
internal power supply decoupler-regulator, providing 110dS supply rejection
and 70dS channel separation. Other
outstanding features include high gain
(104dS), large output voltage swing
(Vcc-2Vp.p), and internal compensation
to 10dS. The NE542 operates from a
single supply across a range of 9 to 24V.
• Low noise - O.7J.LV total input
noise
• High gain -104dB open-loop
• Single supply operation
• Wide supply range 9 to 24V
• Power supply rejection 110dB
• Large output voltage swing
(Vcc- 2V p_p)
• Wide bandwidth 15MHz unity
gain
• Power bandwidth 100kHz (15Vp_p)
• Internally-compensated (stable at
10dB)
• Short-circuit protected
• High slew rate 5VI J.LS
The NE542 is ideal for use in stereo
phono, tape, or microphone preamps
and other applications requiring low
noise amplification of small signals.
PIN CONFIGURATION
N Package
+IN(1)O+IN(2)
-IN (1)
7 -IN (2)
. QND
Vce
3
OUTPUT (1) 4
5 OUTPUT (2)
TOP VIEW
APPLICATIONS
• Tape preamplifier
• Phono preamplifier
• Microphone preamplifier
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
8·Pin Plastic DIP
NE542N
EQUIVALENT CIRCUIT
,-----
Vee
------,
I
I
R3
I
I
I
I
I
I
I
f4.5)
I
I
I
_____ L ____~
November 14, 1986
91
Product Specification
Dual Low-Noise Preamplifier
NE542
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
UNIT
RATING
Vee
Supply voltage
+24
V
PD
Power dissipation
500
mW
o to
TA
Operating ambient temperature range
TSTG
Storage temperature range
-65 to +150
+70
°C
°C
TSOLD
Lead soldering temperature
(10sec max)
+300
= dc
DC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee = 14V, unless otherwise specified.
LIMITS
PARAMETER
SYMBOL
UNIT
TEST CONDITIONS
Min
Vee
Supply voltage
Ice
Supply current
RIN
Input resistance
Positive input
Negative input
ROUT
Output resistance
Typ
9
Vee = 9 to 18V, RL =
9
00
Open-loop
Max
24
V
15
mA
100
200
kn
kn
150
n
AC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee = 14V, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
UNIT
TEST CONDITIONS
Min
Av
Voltage gain
liN
Negative Input current
lOUT
Output current
VOUT
Output voltage swing
SR
Small Signal bandwidth
Slew rate
PBW
Power bandwidth
VIN
Maximum input voltage
PSRR
Power supply rejection ratio
THD
Total harmonic distortion
Channel separation
Total equivalent input noise
NOise figure
November 14, 1986
Open-loop
Typ
Max
160,000
VIV
0.5
Source
Sink (linear operation)
8
2
14
3
Vee -2.5
Vee -2
V
15
5
MHz
V/p.s
100
15Vp.p
Linear operation,
< 2.5%
mA
mA
f = 60, 120Hz
f= 1kHz
f= 1kHz
kHz
300
distortion
100
110
40
mVRMS
dB
dB
70
dB
40dB gain, f = 1kHz
0.1
0.3
%
Rs = 600n, 100-10,OOOHz
0.7
1.2
P.VRMS
Rs = 50kn, 10 - 10,OOOHz
Rs = 20kn, 10 - 10,OOOHz
Rs = 10kn, 10- 10,OOOHz
Rs = 5kn, 10- 10,OOOHz
1.2
1.2
1.5
2.4
92
dB
dB
dB
dB
Product Specification
Dual Low-Noise Preamplifier
NE542
TYPICAL PERFORMANCE CHARACTERISTICS
Large-Signal Frequency Response
> 22
I
CI
Z
!
\
20
Gain vs Temperature
~C~%2~I~T~RT::_
!ll
~
14
z
10
S
8
8
4
:
°lk
~
C
:
\
\
...
3
115
t----+---_+_----t
\
\
I,Ok
\
-"'--
100
10M
~
____________
25
100M
20
~~
15
...
~
o
10
/v
...
0.7
z
0
0.8
I
0.5
I
20
SUPPLY VOLTAGE -
40
.... c::::::r::::: V
c:z:
30
"'-V
25
100
lk
"
90
'\
80
70
~
I 60
z
50
Cl
40
C
"'"'-
20
10
November 14, 1986
10
100
15
110
30
100
45
90
75
90
\
.'\. \
\
'\l
1k
10k
FREQUENCY -
93
0.1M
Hz
1M
105
120
135
~
I
80
Z
z C
70
~:z: ~c
60
Cl
Q
-
Cl
w
Go
!:;
0
>
100
lk
10k
lOOk
1M
-
50
40
150
30
165
20
180
10M
10
t-
o
'-~
Voltage Gain vs Supply Voltage
60
"
\
FREQUENCY - Hz
PHASE '--
1
24
Ay.l000
10
Hz
"'-GAIN
30
Hz
22
V
./
50
120
100
20
20
lOOk
Gain and Phase Response
110
1.
Vcc-12V
10k
FREQUENCY -
120
FREQUENCY -
u
40cIB
V
PSRR vs Frequency
Z
Z
SOcIB.....-::
10
eo
i.......
0.3
0.1
15
i
/
L
70
/
NAB EQUIVALENT
0.4
o
18
~
eo
0.8
0
14
Channel Separation
I
~
12
SUPPLY VOLTAGE -
Z
~
/
10
10
VCC· 12V
0.2
o
8
AI
('
o
8
75
·C
0.9
/
....
:>
~
80
1.1
1.0
/
z
____
50
% Distortion
25
CI
~
~
TEMPERATURE -
Peak-to-Peak Output Voltage
Swing vs Vee
I
I
r-- I-- r--
1~ ~---4-----_+_--_1
FREQUENCY - Hz
>
~
-
10
1l
>
1M
lOOk
1
t----+---_+_----t
110
~o
-
11
I
~ 12
~
r-----~-------r-----,
12
...
18
18
CI
Vee vs lee
13
120
10
15
25
20
SUPPLY VOLTAGE -
V
Product Specification
Dual Low-Noise Preamplifier
NE542
TYPICAl. PERfORMANCE CHARACTERISTICS (Continued)
Noise Voltage vs Frequency
Noise Current vs Frequency
Pulse Response
16
NOTE: Rs=50k
NOTE: Rs=O
Av=10
14
12
~
~
~
>
10
>
0.8
~
I"'b-
8
'>
"I'.,
100
1
z
--
0.4
'"
10k
I~
:::I
~
~t'-.
o
1\
LII
L\
...
:::I
~-t-
100
Hz
:::I
~
0.2
lk
FREQUENCY -
0.6
...I
lk
10k
\
\
-1
-2O-1~
0
10 20
FREQUENCY - Hz
TVP!CAL APPLICATIONS
0.5VRMS
240K
Typical Tape Playback Amplifier
Audio Mixer
VCC,= +18V
Two-Pole Fast Turn-On NAB Tape Preamp
RIAA Magnetic Phono Preamp
NOTE:
All resistor values are typical and in ohms,
November 14, 1986
94
30
40 50 60
TIME-I'a
70
80
NE570j571jSA571
Compandor
Product Specification
DESCRIPTION
FEATURES
The NE570/571 is a versatile low cost
dual gain control circuit in which either
channel may be used as a dynamic
range compressor or expandor. Each
channel has a full-wave rectifier to detect the average value of the signal, a
linerarized temperature-compensated
variable gain cell, and an operational
amplifier.
• Complete compressor and
expandor in one IC
The NE570/571 is well suited for use in
cellular radio and radio communications
systems, modems, telephone, and satellite broadcast/receive audio systems.
CIRCUIT DESCRIPTION
The NE570/571 compandor building
blocks, as shown in the block diagram,
are a full-wave rectifier, a variable gain
cell, an operational amplifier and a bias
system. The arrangement of these
blocks in the IC result in a circuit which
can perform well with few external components, yet can be adapted to many
diverse applications.
The full-wave rectifier rectifies the input
current which flows from the rectifier
input, to an internal summing node
which is biased at VREF. The rectified
current is averaged on an external filter
capacitor tied to the CRECT terminal, and
the average value of the input current
controls the gain of the variable gain
ceil. The gain will thus be proportional to
the average value of the input signal for
capacitively-coupled voltage inputs as
shown in the following equation. Note
that for capacitively-coupled inputs there
is no offset voltage capable of producing
a gain error. The only error will come
from the bias current of the rectifier
(supplied internally) which is less than
O.1J..LA.
PIN CONFIGURATION
D, F, N Packages 1
• Temperature compensated
• Greater than 110dB dynamic
range
• Operates down to 6Voc
• System levels adjustable with
external components
• Distortion may be trimmed out
APPLICATIONS
• Ce"ular radio
• Telephone trunk compandor570
• Telephone subscriber
compandor - 571
•
•
•
•
TOP VIEW
NOTE:
1. SOL· Released in Large SO Package Only.
High level limiter
Low level expandor - nOise gate
Dynamic noise reduction systems
Voltage-contro"ed amplifier
• Dynamic filters
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
o to
o to
o to
o to
o to
16-Pin Cerdip
16-Pin Plastic DIP
16-Pin Plastic SOL
16-Pin Cerdip
16-Pin Plastic Cerdip
ORDER CODE
+70°C
NE570F
+70°C
NE570N
+70°C
NE571D
+70°C
NE571F
+70°C
NE571N
16-Pin Cerdip
-40°C to + 85°C
SA571F
16-Pin Plastic DIP
-40°C to + 85°C
SA571N
BLOCK DIAGRAM
R3
INVERTER IN
R3
R2 20K
lIG IN
20K
( ) - - - W........--f
output
I VIN -
VREF
I avg
Gex----A1
Rl
10K
RECT IN ()---"""IIv---I
or
G ex IVIN I avg
Al
November 14, 1986
95
R4
30K
V REF
18V
Product Specification
NE570/571/SA571
Compandor
ABSOLUTE MAXIMUM RATINGS
SYMBOL
Vee
TA
PD
PARAMETER
RATING
UNIT
24
18
VDe
o to +70
-40 to +85
°e
°e
400
mW
Positive supply
570
571
Operating ambient temperature range
NE
SA
Power dissipation
DC ELECTRICAL CHARACTERISTICS TA = 25°e, Vee = 15V. Except where indicated, the 571 specifications are identical to
those of the 570.
NE/SA571 5
NE570
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Vce
Supply voltage
Icc
Supply current
lOUT
Output current capability
SR
Output slew rate
Min
24
6
3.2
4.8
±20
Untrimmed
Trimmed
Resistor tolerance
1.7
Output De shift3
Untrimmed
No signal, 15Hz - 20kHz 1
Unity gain level
-1
-40 oe < T < 70 0 e
ooe < T < 70 0 e
-40 oe < T < 70 0 e
Gain change 2, 4
Reference drift4
Resistor drift4
ooe
< T < 70
0
= +6dBm,
V2
= -30dBm,
0.3
0.05
1.0
±5
±15
1.8
1.9
±20
±50
20
45
0
+1
±0.1
±0.1
±0.2
V
4.8
mA
mA
1.65
-1.5
V/p.s
0.5
0.1
2.0
%
±5
±15
%
1.8
1.95
V
±30
± 100
mV
20
60
p.V
0
+1.5
dBm
±0.1
±0.1
±0.4
dB
+2, -25 +20, -50
±5
±20
mV
%
dB
±0.2
V 1 = OdB
+0.2
ehannel separation
-0.5, +1
60
NOTES:
1. Input to V1 and V2 grounded.
2. Measured at OdBm, 1kHz.
3. Expandor Ae input change from no signal to OdBm.
4. Relative to value at TA = 25°e.
5. Electrical characteristics for the SA571 only are specified over -40 to +85°C temperature range.
November 14, 1986
18
3.2
+8, -0
+1.-0
e
Rectifier input,
V1 = OdB
V2
Max
± .5
+2, -25 +10, -40
±5
±10
ooe < T < 70 0 e
-40 oe < T < 70 0 e
Typ
±20
± .5
Internal reference voltage
Tracking error (measured
relative to value at
unity gain) equals
[Yo - Vo (unity gain)]
dB - V2dBm
Max
6
No signal
Gain cell distortion 2
Expandor output noise
Typ
96
+0.2
60
-1, +1.5
dB
Product Specification
NE570/571/SA571
Compandor
The speed with which gain changes to follow
changes in input signal levels is determined
by the rectifier filter capacitor. A small capacitor will yield rapid response but will not fully
filter low frequency signals. Any ripple on the
gain control signal will modulate the signal
passing through the variable gain cell. In an
expandor or compressor application, this
would lead to third harmonic distortion, so
there is a trade-off to be made between fast
attack and decay times and distortion. For
step changes in amplitude, the change in gain
with time is shown by this equation.
G(t) = (Ginitial- Gfinal) a-tiT
+ Gfinal; T
=
10k X CRECT
The variable gain cell is a current-in, currentout device with the ratio IOUTII'N controlled by
the rectifier. liN is the current which flows
from the AG input to an internal summing
node biased at VREF. The following equation
applies for capacitively-coupled inputs. The
output current, lOUT, is fed to the summing
node of the op amp.
A compensation scheme built into the AG cell
compensates for temperature and 'cancels
out odd harmonic distortion. The only distortion which remains is even harmonics, and
they exist only because of internal offset
voltages. The THO trim terminal provides a
means for nulling the internal offsets for low
distortion operation.
TYPICAL PERFORMANCE
CHARACTERISTICS
~ 020~----------------,
w
~
The operational amplifier (which is internally
compensated) has the non-inverting input
tied to VREF, and the inverting input connected to the AG cell output as well as brought
out externally. A resistor, R3, is brought out
from the summing node and allows compressor or expandor gain to be determined only by
internal components.
010
...
:::>
:::l
0
a:
0
0
z
~
Q.
~ -30
a:
0
The output stage is capable of ± 20mA output
current. This allows a + 13dBm (3.5VRMS)
output into a 300n load which, with a series
resistor and proper transformer, can result in
+ 13dBm with a 600n output impedance.
-40
w
~
...
-50
[
!; -60
a:
o
A bandgap reference provides the reference
voltage for all summing nodes, a regulated
supply voltage for the rectifier and AG cell,
and a bias current for the AG cell. The low
tempco of this type of reference provides very
stable biasing over a wide temperature range.
~ -70
a:
~ -80L-~---L--~--~~
-40 -30 -20
-10
0 ·10
o
COMPRESSOR OUTPUT LEVel
OR
EXPANDOR INPUT LEVEL IdBm)
U
The typical performance characteristics illustration shows the basic input-output transfer
curve for basic compressor or expandor circuits.
Basic Input-Output Transfer Curve
TYPICAL TEST CIRCUIT
VCC=lSV
D.l
13
I
I
'O F
/I
6.11
8.2K
November 14, 1986
97
I2°O
P
F
Product Specification
NE570/571/SA571
Compandor
INTRODUCTION
Much interest has been expressed in high
performance electronic gain control circuits.
For non-critical applications, an integrated
circuit operational transconductance amplifier
can be used, but when high-performance is
required, one has to resort to complex discrete circuitry with many expensive, wellmatched components. This paper describes
an inexpensive integrated circuit, the NE570
Compandor, which offers a pair of high performance gain control circuits featuring low
distortion ( < 0.1 %), high signal-to-noise ratio
(90dS), and wide dynamic range (110dS).
provides a gain control current, IG, for the
variable gain (~G) cell. The output of the ~G
cell is a current which is fed to the summing
node of the operational amplifier. Resistors
are provided to establish circuit gain and set
the output DC bias.
Figure 3 shows how the circuit is hooked up
to realize an expandor. The input signal, VIN,
is applied to the inputs of both the rectifier
and the ~G cell. When the input signal drops
by 6dS, the gain control current will drop by a
factor of 2, and so the gain will drop 6dS. The
output level at VOUT will thus drop 12dS,
giving us the desired 2-to-1 expansion.
CIRCUIT BACKGROUND
The NE570 Compandor was originally designed to satisfy the requirements of the
telephone system. When several telephone
channels are multiplexed onto a common
line, the resulting signal-to-noise ratio is poor
and companding is used to allow a wider
dynamic range to be passed through the
channel. Figure 1 graphically shows what a
compandor can do for the signal-to-noise
ratio of a restricted dynamic range channel.
The input level range of + 20 to -BOdS is
shown undergoing a 2-to-1 compression
where a 2dS input level change is compressed into a 1dS output level change by the
compressor. The original 100dS of dynamic
range is thus compressed to a 50dS range for
transmission through a restricted dynamic
range channel. A complementary expansion
on the receiving end restores the original
signal levels and reduces the channel noise
by as much as 45dS.
The significant circuits in a compressor or
expandor are the rectifier and the gain control
element. The phone system requires a simple
full-wave averaging rectifier with good accuracy, since the rectifier accuracy determines the
(input) output level tracking accuracy. The
gain cell determines the distortion and noise
characteristics, and the phone system specifications here are very loose. These specs
could have been met with a simple operational transconductance multiplier, or OTA, but
the gain of an OTA is proportional to temperature and this is very undesirable. Therefore, a
linearized transconductance multiplier was
designed which is insensitive to temperature
and offers low noise and low distortion performance. These features make the circuit useful in audio and data systems as well as in
telecommunications systems.
The circuit is intended for use in single power
supply systems, so the internal summing
nodes must be biased at some voltage above
ground. An internal band gap voltage reference provides a very stable, low noise 1.BV
reference denoted VREF. The non-inverting.
input of the op amp is tied to VREF, and the
summing nodes of the rectifier and ~G cell
(located at the right of R1 and R2) have the
same potential. The THD trim pin is also at
the VREF potential.
Figure 1_ Restricted Dynamic Range
Channel
THO TRIM
R.
INY. IN
Figure 4 shows the hook-up for a compressor. This is essentially an expandor placed in
the feedback loop of the op amp. The ~G cell
is setup to provide AC feedback only, so a
separate DC feedback loop is provided by the
two Roc and Coc. The values of Roc will
determine the DC bias at the output of the op
amp. The output will bias to:
VOUT DC = 1 + ROC1 + RDC2
R4
VREF = ( 1 + Roc TOT
30k
R,
·CIN1
'{.~2~""--J.
CRecT
NOTES:
BASIC CIRCUIT HOOK-UP AND
OPERATION
Figure 2 shows the block diagram of one half
of the chip, (there are two identical channels
on the IC). The full-wave averaging rectifier
November 14, 19B6
1.BV
Figure 2. Chip Block Diagram
(1 of 2 Channels)
GAIN
2 R3 VIN (avg.)
R, R2 IB
IB = 1401JA
·External components
Figure 3. Basic Expandor
98
VOUT
Product Specification
NE570/571/SA571
Compandor
The output of the expand or will bias up to:
VREF
20k )
1 + - - 1.8V = 3.0V
30k
=(
The output will bias to 3.0V when the internal
resistors are used. External resistors may be
placed in series with R3 , (which will affect the
gain), or in parallel with R4 to raise the DC
bias to any desired value.
R,
10K
R.
10K
'--T---E... Q ,
vCF
NOTE:
CIN°
V,N avg
IG=2-- R1
Rl
<>--i .........M.r+---I
Figure 6. Simplified Rectifier Schematic
V OU1
Y,N
then mirrored with a gain of 2 to become IG,
the gain control current.
NOTES:
GAIN =
(
R, R218
-2-R-"":V-'--=N:""'(=-av-g-)
3
)
~2
18 = 1401lA
"external components
Figure 4. Basic Compressor
Figure 5. Rectifier Concept
CIRCUIT DETAILS - RECTIFIER
Figure 5 shows the concept behind the fullwave averaging rectifier. The input current to
the summing node of the op amp, VINR 1, is
supplied by the output of the op amp. If we
can mirror the op amp output current into a
unipolar current, we will have an ideal rectifier. The output current is averaged by Rs, CR,
which set the averaging time constant, and
November 14, 1986
Figure 6 shows the rectifier circuit in more
detail. The op amp is a one-stage op amp,
biased so that only one output device is on at
a time. The non-inverting input, (the base of
0 1), which is shown grounded, is actually tied
to the internal 1.8V VREF. The inverting input
is tied to the op amp output, (the emitters of
05 and 06), and the input summing resistor
R1. The single diode between the bases of 05
and 0 6 assures that only one device is on at
a time. To detect the output current of the op
amp, we simply use the collector currents of
the output devices 05 and Os. Os will conduct
when the input swings positive and 05 conducts when the input swings negative. The
collector currents will be in error by the a of
Os or Os on negative or positive signal
swings, respectively. ICs such as this have
typical NPN (3s of 200 and PNP (3s of 40. The
a's of 0.995 and 0.975 will produce errors of
0.5% on negative swings and 2.5% on positive swings. The 1.5% average of these
errors yields a mere 0.13dB gain error.
At very low input signal levels the bias current
of O2 , (typically 50nA), will become significant
as it must be supplied by 05. Another low
level error can be caused by DC coupling into
the rectifier. If an offset voltage exists between the VIN input pin and the base of 02,
an error current of Vos/R1 will be generated.
A mere 1mV of offset will cause an input
current of 100nA which will produce twice the
error of the input bias current. For highest
accuracy, the rectifier should be coupled into
capacitively. At high input levels the (3 of the
PNP Os will begin to suffer, and there will be
'an increasing error until the circuit saturates.
99
Saturation can be avoided by limiting the
current into the rectifier input to 250/iA. If
necessary, an external resistor may be
placed in series with R1 to limit the current to
this value. Figure 7 shows the rectifier accuracy vs input level at a frequency of 1kHz.
,
z
C
CI
0:
~
0
l5
-20
RECTIFIER INPUT dBm
Figure 7. Rectifier Accuracy
At very high frequencies, the response of the
rectifier will fall off. The roll-off will be more
pronounced at lower input levels due to the
increasing amount of gain required to switch
between 05 or Os conducting. The rectifier
frequency response for input levels of OdBm,
-20dBm, and -40dBm is shown in Figure 8.
The response at all three levels is flat to well
above the audio range.
Product Specification
NE570/571/SA571
Compandor
INPUT = Od8m
10K
FREQUENCY (Hz)
Figure 8. Rectifier Frequency
Response vs Input Level
VARIABLE GAIN CELL
Figure 9 is a diagram of the variable gain cell.
This is a linerarized two-quadrant transconductance multiplier. 01, O 2 and the op amp
provide a predistorted drive signal for the gain
control pair, 03 and 04. The gain is controlled
by IG and a current mirror provides the output
current.
The op amp maintains the base and collector
of 01 at ground potential (VREF) by controlling
the base of O 2 . The input current liN
( = VIN/R2) is thus forced to flow through 01
along with the current 11, so IC1 = 11 + liN·
Since 12 has been set at twice the value of 11,
the current through 02 is:
Figure 9. Simplified AG Cell Schematic
This equation is linear and temperature-insensitive, but it assumes ideal transistors.
12 - (1 1 + liN) = 11 -liN = IC2·
The op amp has thus forced a linear current
swing between 01 and 02 by providing the
proper drive to the base of 02. This drive
signal will be linear for small signals, but very
non-linear for large Signals, since it is compensating for the non-linearity of the differential pair, 01 and 02, under large signal conditions.
The key to the Circuit is that this same
predistorted drive signal is applied to the gain
control pair, 03 and 04. When two differential
pairs of transistors have the same signal
applied, their collector current ratios will be
identical regardless of the magnitude of the
currents. This gives us:
~=~= 11 + liN
IC2
IC3
11 - liN
plus the relationships IG = IC3 + IC4 and
lOUT = IC4 - IC3 will yield the multiplier transfer
function,
November 14, 1986
operating level of OdBm, a 1mV offset will
yield 0.34 % of second harmonic distortion.
Most circuits are somewhat better than this,
which means our overall offsets are typically
about 1,12mV. The distortion is not affected by
the magnitude of the gain control current, and
it does not increase as the gain is changed.
This second harmonic distortion could be
eliminated by maki.,g perfect transistors, but
since that would be difficult, we have had to
resort to other methods. A trim pin has been
provided to allow trimming of the internal
offsets to zero, which effectively eliminated
second harmonic distortion. Figure 11 shows
the simple trim network required.
Vcc
INPUT LEVEL (dBm)
Figure 10. AG Cell Distortion
vs Offset Voltage
3.6V
If the transistors are not perfectly matched, a
parabolic, non-linearity is generated, which
results in second harmonic distortion. Figure
10 gives an indication of the magnitude of the
distortion caused by a given input level and
offset voltage. The distortion is linearly proportional to the magnitude of the offset and
the input level. Saturation of the gain cell
occurs at a + 8dBm level. At a nominal
100
8.2K
o~-""·.",v",,,-
__
,~ 20K
To THO Trim
,
T,
.200pF
~
Figure 11. THD Trim Network
Product Specificotion
NE570j571jSA571
Compandor
Figure 12 shows the noise performance of
the LlG cell. The maximum output level before clipping occurs in the gain cell is plotted
along with the output noise in a 20kHz
bandwidth. Note that the noise drops as the
gain is reduced for the first 20dS of gain
reduction. At high gains, the signal to noise
ratio is 90dS, and the total dynamic range
from maximum signal to minimum noise is
110dB.
Control signal feedthrough is generated in the
gain cell by imperfect device matching and
mismatches in the current sources, 11 and 12 ,
When no input signal is present, changing IG
will cause a small output signal. The distortion
trim is effective in nulling out any control
signal feedthrough, but in general, the null for
minimum feedthrough will be different than
the null in distortion. The control signal feedthrough can be trimmed independently of
distortion by tying a current source to the LlG
input pin. This effectively trims 11 . Figure 13
shows such a trim network.
A - SELECT FOA
J
3.&\1
470K
'001(
~TOPIN30A,.
come very significant. Figure 15 shows the
effects of temperature on the diffused resistors which are normally used in integrated
circuits, and the ion-implanted resistors which
are used in this circuit. Over the critical O°C to
+ 70°C temperature range, there is a 10-to-1
improvement in drift from a 5% change for
the diffused resistors, to a 0.5% change for
the implemented resistors. The implanted
resistors have another advantage in that they
can be made Yl the size of the diffused
resistors due to the higher resistivity. This
saves a significant amount of chip area.
Figure 13_ Control Signal Feedthrough
Trim
OPERATIONAL AMPLIFIER
The main op amp shown in the chip block
diagram is equivalent to a 741 with a 1MHz
bandwidth. Figure 14 shows the basic circuit.
Split collectors are used in the input pair to
reduce gM, so that a small compensation
capacitor of just 10pF may be used. The
output stage, although capable of output
currents in excess of 20mA, is biased for a
low quiescent current to conserve power.
When driving heavy loads, this leads to a
small amount of crossover distortion.
Figure 14. Operational Amplifier
RESISTORS
_100'---'----........-40
_20
........-~----'
veA GAIN (dB)
Figure 12_ Dynamic Range of NE570
November 14, 1986
Inspection of the gain equations in Figures 3
and 4 will show that the basic compressor
and expandor circuit gains may be set entirely
by resistor ratios and the internal voltage
reference. Thus, any form of resistors that
match well would suffice for these simple
hook-ups, and absolute accuracy and temperature coefficient would be of no importance. However, as one starts to modify the
gain equation with external resistors, the
internal resistor accuracy and tempco be-
101
1K[} JD
LOWTC
.MPUNTED
RESISTOR
TEMPERATURE
Figure 15. Resistance vs Temperature
NEjSA572
Programmable Analog
Compandor
Product Specification
DESCRIPTION
FEATURES
The NE572 is a dual-channel, high-performance gain control circuit in which
either channel may be used for dynamic
range compression or expansion. Each
channel has a full-wave rectifier to detect the average value of input signal, a
linearized, temperature-compensated
variable gain cell (LlG) and a dynamic
time constant buffer. The buffer permits
independent control of dynamic attack
and recovery time with minimum external components and improved low frequency gain control ripple distortion over
previous compandors.
• Independent control of attack
and recovery time
• Improved low frequency gain
control ripple
• Complementary gain compression
and expansion with external op
amp
• Wide dynamic range - greater
than 110dB
• Temperature-compensated gain
control
• Low distortion gain cell
• Low noise - 6J.LV typical
• Wide supply voltage range6V-22V
• System level adjustable with
external components
The NE572 is intended for noise reduction in high-performance audio systems.
It can also be used in a wide range of
communication systems and video recording applications.
PIN CONFIGURATION
ORDERING INFORMATION
DESCRIPTION
i6-Pin Plastic SO
i6-Pin Plastic DIP
TEMPERATURE RANGE
o to
o to
ORDER CODE
NE572D
+70°C
NE572N
+70°C
-40°C to + 85°C
SA572D
i6-Pin Cerdip
-40°C to + 85°C
SA572F
i6-Pin Plastic DIP
-40°C to + 85°C
SA572N
i6-Pin Plastic SO
D, N, F Packages 1
TRACK TRIM A
1
RECOV. CAP. A
2
15
TRACK TRIM B
RECT. IN A
3
14
RECOV. CAP. B
ATTACK CAP A
4
12
ATTACK CAP B
THO TRIM A
6
~G
IN A
7
GROUNO
8
TOP VIEW
NOTE:
1. D package released in large SO (SOL) package
only.
APPLICATIONS
•
•
•
•
•
•
•
Dynamic noise reduction system
Voltage control amplifier
Stereo expandor
Automatic level control
High-level limiter
Low-level noise gate
State variable filter
BLOCK DIAGRAM
(7.9)-+--JyR",,',--_...,
,-----------------------------;-(S.")
(6.'0)
(1.15)
r----t---+---+(3. '3)-+--+----+--1
('6)
(8)
October 7, 1987
(4. '2)
(2.'4)
103
853-0813 90829
Product Specification
Programmable Analog Compandor
NE/SA572
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Vce
Supply voltage
TA
Operating temperature range
NE572
SA572
RATING
UNIT
22
Voe
o to +70
-40 to +85
°C
500
mW
Power dissipation
Po
DC ELECTRICAL CHARACTERISTICS Standard test conditions (unless otherwise noted) Vee = 15V, TA = 25°C; Expandor
mode (see Test Circuit). Input signals at unity gain level (OdB) = 100mVRMS at 1kHz;
V1 = V2; R2 = 3.3kn; R3 = 17.3kn.
NE572
PARAMETER
SYMBOL
UNIT
Min
Vee
Supply voltage
Icc
Supply current
VR
Internal voltage
reference
THO
THO
THO
Total harmonic distortion
(untrimmed)
Total harmonic distortion
(trimmed)
Total harmonic distortion
(trimmed)
No signal output noise
DC level shift
(untrimmed)
6
PSRR
Power supply rejection
ratio
October 7, 1987
Max
Min
22
6
Typ
2.3
2.5
2.7
1.0
2.3
Max
22
Voe
6.3
mA
2.5
2.7
Voe
0.2
1.0
%
6
1kHz CA
= 1.0J.LF
0.2
1kHz CR
= 10J.LF
0.05
0.05
%
100Hz
0.25
0.25
%
Input to V1 and V2 grounded
(20-20kHz)
6
25
6
25
J.LV
Input change from no signal to
100mVRMS
±20
±50
±20
±50
mV
0
+1
0
+1.5
dB
0.7
3.0
0.7
3
%
-2.5
+1.6
dB
-1
Vl
= V2 = 400mV
Tracking error (measured
relative to value at unity Rectifier input
gain) =
V2 = +6dB V1 = OdB
[Yo - Vo (unity gain)]dB
V2 = -30dB V1 = OdB
-V2dB
Channel crosstalk
Typ
No signal
Unity gain level
Large-signal distortion
SA572
TEST CONDITIONS
200mVRMS into channel A,
measured output on channel B
±0.2
±0.5
104
±0.2
±0.5
-1.5
+0.8
60
60
70
120Hz
-1.5
dB
70
dB
Product Specification
NEjSA572
Programmable Analog Compandor
TEST CIRCUIT
-15V
2.2~F
VI
(7.9)
o---i
S.8K
(5.11)
Rl
50
CR
= IOI'F
CA
= I~F
J
J
(2.14)
(6.10)
BUFFER
(4.12)
(8)
(1.15)
2.2,.,F
3.3K(3,13)
V2o---i~~~----~--4
AUDIO SIGNAL PROCESSING IC
COMBINES VCA AND FAST
AITACK/SLOW RECOVERY
LEVEL SENSOR
In high-performance audio gain control applications, it is desirable to independently control the attack and recovery time of the gain
control signal. This is true, for example, in
compandor applications for noise reduction.
In high end systems the input signal is usually
split into two or more frequency bands to
optimize the dynamic behavior for each band.
This reduces low frequency distortion due to
control signal ripple, phase distortion, high
frequency channel overload and noise modulation. Because of the expense in hardware,
multiple band Signal processing up to now
was limited to professional audio applications.
With the introduction of the Signetics NES72
this high-performance noise reduction concept becomes feasible for consumer hi fi
applications. The NES72 is a dual channel
gain control IC. Each channel has a linearized, temperature-compensated gain cell and
an improved level sensor. In conjunction with
an external low noise op amp for current-tovoltage conversion, the VCA features low
distortion, low noise and wide dynamic range.
October 7, 1987
100~!
~------------------------~--~~~~TI5V
(16)
The novel level sensor which provides gain
control current for the VCA gives lower gain
control ripple and independent control of fast
attack, slow recovery dynamic response. An
attack capacitor CA with an internal 10k
resistor RA defines the attack time tAo The
recovery time tR of a tone burst is defined by
a recovery capacitor CR and an internal 10k
resistor RR. Typical attack time of 4ms for .the
high-frequency spectrum and 40ms for the
low frequency band can be obtained with
0.1 J.lF and 1.0J.lF attack capacitors, respectively. Recovery time of 200ms can be obtained with a 4.7J.1F external capacitor. With
the recovery capacitor added in the level
sensor, the gain control ripple for low frequency signals is much lower than that of a
simple RC ripple filter. As a result, the residual third harmonic distortion of low frequency
Signal in a two quad transconductance amplifier is greatly improved. With the 1.0J.lF attack
capacitor and 4.7 J.lF recovery capacitor for a
100Hz Signal, the third harmonic distortion is
improved by more than 10dB over the simple
RC ripple filter with a single 1.0J.lF attack and
recovery capacitor, while the attack time
remains the same.
The NES72 is assembled in a standard 1S-pin
dual in-line plastic package and in oversized
105
SOL package. It operates over a wide supply
range from SV to 22V. Supply current is less
than SmA. The NES72 is designed for consumer application over a temperature range
0- 70·C. The SAS72 is intended for applications from -40·C to + 8S·C.
NE572 BASIC APPLICATIONS
Description
The NES72 consists of two linearized, temperature-compensated gain cells (dG), each
with a full-wave rectifier and a buffer amplifier
as shown in the block diagram. The two
channels share a 2.SV common bias reference derived from the power supply but
otherwise operate independently. Because of
inherent low distortion, low noise and the
capability to linearize large Signals, a wide
dynamic range can be obtained. The buffer
amplifiers are provided to permit control of
attack time and recovery time independent of
each other. Partitioned as shown in the block
diagram, the IC allows flexibility in the design
of system levels that optimize DC shift, ripple
distortion, tracking accuracy and noise floor
for a wide range of application requirements.
Product Specification
NEjSA572
Programmable Analog Compandor
Gain Cell
Figure 1 shows the circuit configuration of the
gain cell. Bases of the differential pairs
0 1 - 02 and 03 - 0 4 are both tied to the
output and inputs of OPA A1. The negative
feedback through 0 1 holds the VSE of
01 - 02 and the VSE of 03 - 0 4 equal. The
following relationship can be derived from the
transistor model equation in the forward active region.
= VT In
('l
where liN
;slIN ) - VT In ('2
v+
-II~ -liN )(2)
VIN
=-
R1
R1 = 6.8kn
11 = 140llA
12 = 280llA
10 is the differential output current of the gain
cell and IG is the gain control current of the
gain cell.
If all transistors 01 through 04 are of the
same size, equation (2) can be simplified to:
The first term of Equation 3 shows the
multiplier relationship of a linearized two
quadrant transconductance amplifier. The
second term is the gain control feedthrough
due to the mismatch of devices. In the design,
this has been minimized by large matched
devices and careful layout. Offset voltage is
caused by the device mismatch and it leads
to even harmonic distortion. The offset voltage can be trimmed out by feeding a current
source within ± 251lA into the THO trim pin.
October 7, 1987
Vin
Figure 1. Basic Gain Cell Schematic
The residual distortion is third harmonic distortion and is caused by gain control ripple. In
a compandor system, available control of fast
attack and slow recovery improve ripple distortion significantly. At the unity gain level of
100mV, the gain cell gives THO (total har·
monic distortion) of 0.17% typo Output noise
with no input signals is only 61lV in the audio
spectrum (10Hz - 20kHz). The output current
10 must feed the virtual ground input of an
operational amplifier with a resistor from output to inverting input. The non-inverting input
of the operational amplifier has to be biased
at VREF if the output current 10 is OC coupled.
Rectifier
The rectifier is a full-wave design as shown in
Figure 2. The input voltage is converted to
current through the input resistor R2 and
turns on either 05 or 06 depending on the
106
signal polarity. Oeadband of the voltage to
current converter is reduced by the loop gain
of the gain block A2. If AC coupling is used,
the rectifier error comes only from input bias
current of gain block A2. The input bias
current is typically about 70nA. Frequency
response of the gain block A2 also causes
second-order error at high frequency. The
collector current of 06 is mirrored and
summed at the collector of 0 5 to form the full
wave rectified output current IR. The rectifier
transfer function is
VIN-VREF
IR=---R2
(4)
If VIN is AC-coupled, then the equation will be
reduced to:
VIN(AVG)
IRAC=--R2
Product Specification
NEjSA572
Programmable Analog Compandor
The internal bias scheme limits the maximum
output current IR to be around 300J,LA. Within
a ± 1dB error band the input range of the
rectifier is about 52dB.
Buffer Amplifier
VREF
In audio systems, it is desirable to have fast
attack time and slow recovery time for a tone
burst input. The fast attack time reduces
transient channel overload but also causes
low-frequency ripple distortion. The low-frequency ripple distortion can be improved with
the slow recovery time. If different attack
times are implemented in corresponding frequency spectrums in a split band audio system, high quality performance can be
achieved. The buffer amplifier is designed to
make this feature available with minimum
external components. Referring to Figure 3,
the rectifier output current is mirrored into the
input and output of the unipolar buffer amplifier Aa through OB, 0 9 and 010' Diodes Dl1
and D12 improve tracking accuracy and provide common-mode bias for A3. For a positive-going input signal, the buffer amplifier
acts like a voltage-follower. Therefore, the
output impedance of Aa makes the contribution of capacitor CR to attack time insignificant. Neglecting diode impedance, the gain
Ga(t) for ~G can be expressed as follows:
0-----4
,--------- -----j
I
I
I
I
:
I
R2
V~
I
I
I
I
I
:
Q6
L______________ J
Figure 2. Simplified Rectifier Schematic
-t
v+
Ga(t) = (GaINT - GaFNd eTA + GaFNL
010
GalNT = Initial Gain
GaFNL = Final Gain
TA = RA • CA = 10k' CA
where TA is the attack time constant and RA
is a 10k internal resistor. Diode D15 opens the
feedback loop of Aa for a negative-going
signal if the value of capacitor CR is larger
than capacitor CA. The recovery time depends only on CR • RR' If the diode impedance is assumed negligible, the dynamic gain
GR (t) for ~G is expressed as follows.
IR2
10K
-t
10K
X2
018
GR(t) = (GR INT - GR FNU e TR + GR FNL
TR = RR • CR = 10k • CR
CA
CR
I
TRACKING
TRIM
where TR is the recovery time constant and
RR is a 10k internal resistor. The gain control
current is mirrored to the gain cell through
0 14 , The low level gain errors due to input
bias current of A2 and A3 can be trimmed
through the tracking trim pin into Aa with a
current source of ± 3J,LA.
r
Figure 3. Buffer Amplifier Schematic
October 7, 1987
107
Product Specification
NE/SA572
Programmable Analog Compandor
R4
R3
17.3K
CIN1
YIN
:>----<>-----0 your
o----II-----i----I
2.2~F
RS
+Ycc
Figure 4. Basic Expandor Schematic
Basic Expandor
Figure 4 shows an application of the circuit as
a simple expandor. The gain expression of
the system is given by
VOUT = ~ • R3 • V1N(AVG)
VIN
(11
11
(5)
R2 • R1
= 1401lA)
80th the resistors R1 and R2 are tied to
internal summing nodes. R1 is a 6.8k internal
resistor. The maximum input current into the
gain cell can be as large as 140J..LA. This
corresponds to a voltage level of 140iJA •
6.8k = 952mV peak. The input peak current
October 7, 1987
into the rectifier is limited to 300J..LA by the
internal bias system. Note that the value of
R1 can be increased to accommodate higher
input level. R2 and R3 are external resistors. It
is easy to adjust the ratio of R3/R2 for
desirable system voltage and current levels.
A small R2 results in higher gain control
current and smaller static and dynamic tracking error. However, an impedance buffer A1
may be necessary if the input is voltage drive
with large source impedance.
The gain cell output current feeds the summing node of the external OPA A2. R3 and A2
convert the gain cell output current to the
output voltage. In high-performance applications, A2 has to be low-noise, high-speed and
108
wide band so that the high-performance output of the gain cell will not be degraded. The
non-inverting input of A2 can be biased at the
low noise internal reference Pin 6 or 10.
Resistor R4 is used to bias up the output DC
level of A2 for maximum swing. The output
DC level of A2 is given by
VaDe = VREF
(
1
+ -R3 ) - VB -R3
R4
(6)
R4
VB can be tied to a regulated power supply for
a dual supply system and be grounded for a
single supply system. CA sets the attack time
constant and CR sets the recovery time
constant.
Product Specification
NEjSA572
Programmable Analog Compandor
Basic Compressor
Figure 5 shows the hook-up of the circuit as a
compressor. The IC is put in the feedback
loop of the OPA A1. The system gain expression is as follows:
(7)
R4
ROCl
ROC2
CINl
VIN <>---l1--JV\IIr--+---~
2.2~F
,:';K
~-----~~--------OVOUT
ROC1, ROC2, and CDC form a DC feedback for
A1. The output DC level of A1 is given by
Va DC
= VREF
(
1 + RDc1 R+4ROC2 )
-VB' (
ROC1 + ROC2 )
""~rl
"1
(8)
R4
co,
2.2~F
The zener diodes D1 and D2 are used for
channel overload protection.
Basic Compandor System
3.3K
R2
The above basic compressor and expandor
can be applied to systems such as tape1disc
noise reduction, digital audio, bucket brigade
delay lines. Additional system design techniques such as band limiting, band splitting,
pre-emphasis, de-emphasis and equalization
are easy to incorporate. The IC is a versatile
functional block to achieve a high performance audio system. Figure 6 shows the
system level diagram for reference.
October 7, 1987
(3.13)
Figure 5. Basic Compressor Schematic
109
Product Specification
NE/SA572
Programmable Analog Compandor
REL LEVEl.
VRMS
,--_ _ _ COMP~~SSION
3.0V
547.6MV
400MV
100MV
10MV
1MV
100~V
~
INPUT TO lIG
AND RECT
-----
/
-----~
/
~
~
10~V
Figure 6. NE572 System Level
October 7. 1987
dB
EXPANDOR
OUT
110
ABS LEVEL
dBM
... 29.54
+11.76
"1"14.77
"1"12.0
-3.00
-5.78
0.0
-17.78
-20
-37.78
-40
-57.78
-60
-17.78
-80
-97.78
NE575
Low Voltage Compandor
Preliminary Specification
DESCRIPTION
FEATURES
The NE575 is a dual gain-control circuit
designed for low voltage applications.
The NE575's channel 1 is an expandor,
while channel 2 can be configured either
for expand or, compressor, or automatic
level controller (ALC) application.
• Operating voltage range from 3
to 7V
• Reference voltage of
100mVRMS = OdB
• One dedicated summing op amp
per channel and two extra
uncommitted op amps
• SOOn drive capability
• Single or split supply operation
• Wide input/output swing
capability.
PIN CONFIGURATION
APPLICATIONS
•
•
•
•
•
•
Portable communications
Cellular radio
Cordless telephone
Consumer audio
Portable broadcast mixers
Wireless microphones
• Modems
• Electric organs
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
o to
o to
20-Pin Plastic DIP
20-Pin Plastic SO
ORDER CODE
+70°C
NE575N
+70°C
NE575D
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
8
V
Operating temperature range
-40 to +85
°C
Storage temperature range
-65 to +150
°C
Vce
Supply voltage
TA
TSTG
December 1988
111
NE575 0, N Packages
Preliminary Specification
NE575
Low Voltage Compandor
DC ELECTRICAL CHARACTERISTICS
TA = 25°C, OdB = 100mV, expander mode, Vee = 5V, Figure 1, unless otherwise
specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
I
I
UNIT
Min
Typ
3
5
7
V
3
4
5.5
mA
1kHz, OdB, BW = 3.5kHz
0.13
1.0
%
BW = 20kHz, Rs = on
6
20
p.V
Max
For compandor, Including summing amplifier
Vee
Supply voltage 1
lec
Supply current
RL
Summing amp output load
THO
Total harmonic distortion
eno
Output voltage noise
OdB
Unity gain level
Vos
Output voltage offset
Output DC shift
Tracking error
Crosstalk
No signal
10
kn
1kHz
-1.0
1.0
dB
no signal
-100
100
mV
no signal to OdB
-50
1kHz, + 6dB to -30dB
-0.5
10
-80
1kHz, OdB, CREF = 220p.F
50
mV
+0.5
dB
-65
dB
For operational amplifier
Vo
Output swing
RL
Output load
Vp.p, RL = 10kn
1kHz
Input common-mode range
0
CMRR
Common-mode rejection ratio
60
18
Input bias current
Vos
Input offset voltage
AVOL
Open-loop gain
RL = 10kn
SR
Slew rate
unity gain
n
600
CMR
VIN = 0.5V - 4.5V
V
Vee - O.4 Vee- 0.2
Vee
80
-0.3
V
dB
0.3
p.A
10
mV
-10
3
80
90
dB
1
V/p.s
MHz
GBW
Bandwidth
unity gain
3
eni
Input voltage noise
BW= 20kHz
2.5
p.V
PSRR
Power supply rejection ratio
1kHz, 250mV
60
dB
NOTE:
1. The Ie remains functional down to 2V.
December 1988
112
Preliminary Specification
NE575
Low Voltage Compandor
C15
O.1~F
20
~
NE575
C14
':" GND
lO~F
+
I----oVIN
R4
200
C3
10~F
VREF
~~
R5
100k
RlO
200
RECTIFIER
4.3k
':" GND
17
RECTIFIER
4.3k
C1l
164.7~F
C10
lO~F
R9
lOOk
+
-=
+
C6
10~F
VIN
14
o---i ~+~-.......
~
13
R8
30k
12
R7
30k
+ C8
I1~F
.......M.-I~1..;.1....I
GAIN CELL
NOTE:
Left channel in expander mode; right channel in compressor mode.
For additional Information, call the factory.
Figure 1. Typical Application
December 1988
113
-=
GND
GND
NE5240
Dolby Digital Audio Decoder
Preliminary Specification
DESCRIPTION
FEATURES
The NE5240 is a two channel decoder
for the Dolby Digital Audio System. *The
IC includes input latches to separate two
channels of audio and control data, a
precision internal voltage reference, and
digital/analog signal processing circuitry
for each channel. The IC design is implemented in a bipolar process to achieve
low noise, low distortion, and wide dynamic range.
• Wide dynamic range - 85dB
• Low distortion 0"05% @ 1kHz,
-10dB
• TTL and CMOS compatible logic
inputs
• Audio bandwidth - 30Hz to
15kHz
NOTE:
'Available only to licensees of Dolby Laboratories
Licensing Corporation, San Francisco, from whom
licensing and applications information must be ob·
tained. Dolby is a registered trademark of Dolby
Laboratories Licensing Corporation, San Francisco,
California.
PIN CONFIGURATION
APPLICATIONS
• High quality digital transmission
of audio data
• Satellite reception
• Cable TV
• Microwave distribution systems
ORDERING INFORMATION
DESCRIPTION
28-Pin SO
28-Pin Plastic DIP
December 1988
TEMPERATURE RANGE
o to
o to
ORDER CODE
+70°C
NE5240D
+70°C
NE5240N
115
N, 0 Packages
MULTOUT"
1
ANALOG
SUPPLY VOLT
VARIABLE
IMPEDANCE'
SUM NODE"
5
INTERNAL
AMPLIFIER'
SLIDING BAND
BUFFER IN"
SLIDING BAND
BUFFER OUT'
STEP SIZE
BUFFER IN'
STEP SIZE
BUFFER OUT'
LOGIC
SUPPLY
STEP SIZE
DATA IN
AUDIO
DATA IN
SLIDING BAND
DATA IN
23
22
21
20
19
~J~~~~~
g~~~~~ ::'~D
g~~~~~ ~~p.
ru~~~~N"'
ru~~~6UT*"
DIGITALGND
1
EXT RES
REF VOLT
lOP VIEW
Preliminary Specification
NE5240
Dolby Digital Audio Decoder
BLOCK DIAGRAM
Rl
UK
R2
43K
R3
360K
R15
5.1K
V DD
11
VOUT
CH.A
VDD
eX
SSO
12
NE5240
AD
13
REFERENCE
GENERATOR
REX
VH
INPUT
LOGIC
SBO
CK
Vee
17
R17
104K
VR
14
Vl
VREF
AGNO
15
16
....:!: C17
27
220!,F
26
DGNO
VOUT
CH.B
18
19
21
NOTE:
One channel of the application shown with external components.
December 1988
116
Preliminary Specification
Dolby Digital Audio Decoder
NE5240
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Vs
Analog supply voltage
+15
V
Voo
Logic supply voltage
+7
V
TA
Operating ambient temperature range
TSTG
Storage temperature range
TsoLO
Lead temperature (soldering, 60sec)
o to
+70
°C
-65 to + 150
°C
+300
°C
DC ELECTRICAL CHARACTERISTICS All specifications are at TA = 25°C, Vee = 12V, Voo = 5V.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Typ
Max
Vee
Analog voltage supply range
10
12
14
Voo
Logic voltage supply range
4.5
5
5.5
V
Icc
Supply current
10
24
35
mA
5
12
18
mA
= 12V
Voo = 5V
Vee
V
100
Supply current
VIH
Input voltage high
2
5
V
VIL
Input voltage low
0
0.8
V
IlL
Input current low
IIH
Input current high
Voo
= 4.5V
ts
Setup time
150
tH
Hold time
150
Is
Input buffers, Pins 7, 9, 20, 22
RL
Summing amp output load
Vas
Output offset voltage
Vas
Output offset change
VREF
Reference voltage
December 1988
VIN
10
100
I1A
1
100
I1A
ns
ns
= 2.0V
100
kQ
5
10%-SBO-70%
5.5
117
nA
0.1
0.6
V
±5
±20
mV
0. 5V ce
6.5
V
Preliminary Specification
NE5240
Dolby Digital Audio Decoder
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
Va
TEST CONDITIONS2
PARAMETER
Full-Scale output, OdB
Absolute output level
Channel balance
f
Step-Size linearity
f
Step-Size linearity
fR
Frequency response
fA
Frequency response
fA
Frequency response
fA
Frequency response
fR
Frequency response
fR
Frequency response
(all WRT 100Hz)
SIN
Dynamic range
THO
Harmonic distortion
THO
Harmonic distortion
Channel separation
PSRR
f
Power supply rejection ratio 1
f = 100Hz
= 1kHz, SSO = 40%
= 1kHz,
= 1kHz,
Typ
93
118
1.8
VRMS
150
mVRMS
-1.5
1.5
dB
20%-SSO-70%
-1.5
1.5
dB
-2.5
1.0
dB
-1.0
1.0
dB
-1.0
1.0
dB
-1.0
1.0
dB
-1.0
1.0
dB
-1.0
1.0
dB
-1.0
-1.5
1.0
1.5
dB
dB
= 100Hz, SSO = 90%
f = 2kHz, SBO = 10%
f = 5kHz, SBO = 20%
f = 7kHz, SBO = 30%
f = 8kHz, SBO = 40%
f = 10kHz, SBO = 50%
f = 12kHz, SBO = 60%
f = 14kHz, SBO = 70%
f
SSO = 70%, CCIR/ARM
= 1kHz, -3dB
f = 1kHz, -10dB
f = 1kHz, OdB
f = 1kHz
80
f
118
Max
20%-SSO-70%
NOTES:
1. PSRR depends on value of capacitor on Pin 16.
2. The duty cycle of SSD and SBD control data is 10%, unless otherwise noted.
December 1988
UNIT
Min
60
85
dB
0.1
0.5
%
0.05
75
0.2
%
dB
60
dB
NEjSE5410
10-Bit High-Speed Multiplying
D/ A Converter
Product Specification
DESCRIPTION
FEATURES
The NE541 OfSE541 a are 10-bit Multiplying Oigital-to-Analog Converters pinand function-compatible with the industry-standard MC3410, but with improved
performance. These are capable of highspeed performance, and are used as
general-purpose building blocks in cost
effective Of A systems.
• Pin- and function-compatible with
MC3410
• 10-bit resolution and accuracy
(±0.05%)
• Guaranteed differential nonlinearity over temperature
• Wide compliance voltage range-2.5 to + 2.5V
• Fast settling time - 250ns typical
• Digital inputs are TTL- and
CMOS-compatible
• High-speed multiplying input slew
rate - 20mA/Ils
• Reference amplifier internallycompensated
• Standard supply voltages + 5V
and -15V
The NEfSE5410 provides complete 10bit accuracy and differential non-linearity
over temperature, and a wide compliance voltage range. Segmented current
sources, in conjunction with an Rf2R
OAC, provide the binary weighted currents. The output buffer amplifier and
voltage reference have been omitted to
allow greater speed, lower cost, and
maximum user flexibility.
PIN CONFIGURATION
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
o to
16-Pin Cerdip
16-Pin Cerdip
ORDER CODE
+70°C
NE5410F
-55 to +125°C
SE5410F
BLOCK DIAGRAM
MSB
LSB
16 r-----~
F Package
TOP VIEW
APPLICATIONS
• Successive approximation AID
converters
• High-speed, automatic test
equipment
•
•
•
•
•
•
High-speed modems
Waveform generators
CRT displays
Strip CHART and X-Y plotters
Programmable power supplies
Programmable gain and
attenuation
,----..,
Vr:.c
VEE
November 14, 1986
GND
119
853-0945 86554
Product Specification
10-Bit High-Speed Multiplying DjA Converter
NEjSE5410
ABSOLUTE MAXIMUM RATINGS TA = + 25°C, unless otherwise specified.
SYMBOL
Vee
PARAMETER
RATING
Power supply
VEE
VI
Digital input voltage
Vo
Applied output voltage
IREF(16)
Reference current
VAEF
Reference amplifier inputs
VAEF(O)
Reference amplifier differential inputs
TA
Operating temperature range
SE5410
NE5410
UNIT
+7.0
Voe
-18
Voe
+15
Voe
+4, -5.0
Voe
2.5
mA
Vee, VEE
Voe
0.7
Voe
-55 to.+ 125
o to +70
°c
°c
TJ
Junction temperature
Ceramic package
+150
°c
TSTG
Storage temperature
-65 to + 150
°c
Po
Maximum power dissipation
TA = 25°C (still-air)l
1190
mW
NOTE:
1. Derate above 25"C at the following rate:
F package at 9.5mWI"C.
DC ELECTRICAL CHARACTERISTICS Vee = +5.0Voe, VEE = -15Voe, IREF = 2.0mA, all digital inputs at high logic level.
SE5410: T A = -55°C to + 125°C, NE5410 Series: TA = O°C to + 70°C, unless
otherwise noted.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
fA
Relative accuracy
(Error relative to full scale 10)
Over temperature
Differential non-linearity
Over temperature
Typ
Max
±0.025
±0.05
0/0
d'4
± 1;2
LSB
±0.025
±0.05
0/0
± 1;4
± 1;2
LSB
ts
Settling time to within ± Y2 LSB
(all bits low to high)
TA
= 25°C
250
ns
tpLH
tpHL
Propagation delay time
TA
= 25°C
35
20
ns
TClo
Output full-scale current drift
VIH
Digital input logic levels (all bits)
High level, Logic "1"
Low level, Logic "0"
IIH
IlL
Digital input current (all bits)
High level, VIH = 5.5V
Low level, VIL = 0.8V
IAEF(15)
Reference input bias current (Pin 15)
10H
Output current (all bits high)
IOL
Output current (all bits low)
Vo
Output voltage compliance
SR IREF
Reference amplifier slew rate
November 14, 1986
20
40
2.0
ppmrC
Voe
0.8
VREF = 2.000V,
R16=1000n
TA
= 25°C
3.937
20
-20
IlA
-1.0
-5.0
p.A
3.996
4.054
mA
0
0.4
p.A
-2.5
+2.5
Voe
TA = 25°C
fR < 0.050%
relative to full-scale
20
120
mAillS
Product Specification
10-Bit High-Speed Multiplying
0/A
Converter
DC ELECTRICAL CHARACTERISTICS (Continued)
NE/SE5410
vcc = + 5.0Voc. VEE = -15Voc. IREF = 2.0mA, all digital inputs at high
logic level. SE5410: TA = -55°C to + 125°C. NE5410 Series: TA = O°C
to + 70°C. unless otherwise noted.
LIMITS
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT
Min
ST IREF
Reference amplifier settling time
PSRR(-)
Output current power supply
sensitivity
o to
Typ
4.0mA. ± 0.1 %
Max
2.0
0.003
p.s
0.01
%/%
Co
Output capacitance
CI
Digital input capacitance
(all bits high)
4.0
Icc
lEE
Power supply current
(all bits low)
+2
-12
+4
-18
Vcc
VEE
Power supply voltage range
+5.0
-15
+5.25
-15.75
Voc
190
300
mW
Vo=O
25
+4.75
-14.25
TA = 25°C
Vo=O
Power consumption
4.0
1....
3.0
~
2.0
,
(
Jee~ +~.oJ
pF
mA
~
4.0 r---r--,.-.---,.--,.-.---r--,
~
3.0
1-+--+--1I-+--+--l-+--l
2.0
1-+--+--1I--+--+--l--+--l
w
I
pF
CI
~
g
1.0
I
:~;~=~:~v-
~
I-+--+-+-I-IREF = 2 mA
.... 1.0
~ -1.0
I-+--+--ll--+--+--l--+--l
:::I
~ - 2.0 t--+---+-t----+---+---1f--+---i
z
VEE'"' -15.0V _
TA=25°C
IREF=2 mA -
II:
:::I
(,)
z
....~
o
IL
0
(,)
I
-1.0 ~
-5
.... - 3.0 t--+---+-t---+---+---1f--+---i
:::I
~ - 4.0
-3
-1 0
o
1
L-...I---'-_'---L---'----JL.---L----l
-75
COMPLIANCE VOL TAGE (VOLT)
c.§.
13
~
12
II:
II:
:::I
11
r-- r-- ~I!E
iii
'""""
~
~
I I I
(,)
Vee = +5V-VEE= -15V
IREF=2mA-
IL
~
o
~
~
~
+Ice
II:
o
-75-50-25
0
25 50
TA(·C)
18.0
16.0
14.0
12.0
10.0
8.0
6.0
4.0
2.0
0
-2.0
-4.0
-6.0
-8.0
-10
- 12
0
25 so
TA(OC)
75 100 125
r---r-r-rrTTTrr---"--r"~""""""
t--+-+-+++++I+R15=R16=1.0k
B CURVE
VREF( -) = OV
SMALL· SIGNAL BW
ro = loon
VREF(+)=50mVp- p
CENTERED AT +2oomV
1--+-+-+++++I+--7II~-+1-++1+f
I--+-+++++I:~~--+-I-l-++I+f
t--+-;-~CH1ft--+-+-t\t+H+t
L..-..........-'--'-'-J..L1.U----'--l-...L..I...c..J..u
0.1
75 100 125
Figure 3. Power Supply Currents vs Temperature
November 14. 1986
-so -25
Figure 2. Maximum Output Compliance Voltage vs
Temperature
Figure 1. Output Current vs Output Compliance Voltage
w
-
0.2 0.3 0.5 1.0 2.0 3.0 5.0
I. FREQUENCY (MHz)
10
Figure 4. Reference Amplifier Frequency Response
121
Product Specification
10-Bit High-Speed Multiplying 0/A Converter
CIRCUIT DESCRIPTION
The NE5410 consists of four segment current
sources which generate the 2 Most Significant Bits (MSBs), and an R/2R DAC implemented with ion-implanted resistors for scaling the remaining 8 Least Significant Bits
(LSBs) (see Figure 5). This approach provides complete 1O-bit accuracy without trimming.
The individual bit currents are switched ON or
OFF by fully-differential current switches. The
switches use current steering for speed.
An on-chip high slew reference current amplifier drives the R/2R ladder and segment
decoder. The currents are scaled in such a
way that, with all bits on, the maximum output
current is two times 1023/1024 of the reference amplifier current, or nominally 3.996mA
for a 2.000mA reference input current. The
reference amplifier allows the user to provide
a voltage input: out-board resistor R16 (see
Figure 6) converts this voltage to a usable
current. A current mirror doubles this reference current and feeds it to the segment
NE/SE5410
decoder and resistor ladder. Thus, for a
reference voltage of 2.0V and a 1kS1 resistor
tied to Pin 16, the full-scale current is approximately 4.0mA. This relationship will remain
regardless of the reference voltage polarity.
Connections for a positive reference voltage
are shown in Figure 6a. For negative reference voltage inputs, or for bipolar reference
voltage inputs in the multiplying mode, R15
can be tied to a negative voltage corresponding to the minimum input level. For a negative
reference input, R16 should be grounded
(Figure 6b). In addition, the negative voltage
reference must be at least 3V above the VEE
supply voltage for best operation. Bipolar
input signals may be handled by connecting
R16 to a positive voltage equal to the peak
positive input level at Pin 15.
When a DC reference voltage is used, capacitive bypass to ground is recommended. The
5V logic supply is not recommended as a
reference voltage. If a well regulated 5.0V
supply, which drives logic, is to be used as
the reference, R16 should be decoupled by
connecting it to the + 5.0V logic supply
through another resistor and bypassing the
junction of the two resistors with a 0.11lF
capacitor to ground.
The reference amplifier is internally-compensated with a 10pF feed-forward capacitor,
which gives it its high slew rate and fast
settling time. Proper phase margin is maintained with all possible values of R16 and
reference voltages which supply 2.0mA reference current into Pin 16. The reference
current can also be supplied by a high impedance current source of 2.0mA. As R16 increases, the bandwidth of the amplifier decreases slightly and settling time increases.
For a current source with a dynamic output
impedance of 1.0MS1, the bandwidth of the
reference amplifier is approximately half what
it is in the case of R16 = 1.0kS1, and settling
time is ~1 OilS. The reference amplifier phase
margin decreases as the current souce value
decreases in the case of a current source
reference, so that the minimum reference
current supplied from a current source is
0.5mA for stability.
(4)
(13)
MSB
(6)
(8)
(9)
(10)
(11)
(12)
0,
03
05
06
07
08
09
LSB
0,0
GND
(2)
VBIAS
(INTERNAL)
2R
2R
2R
2R
2R
R
R
R
(16)
+<>-----1>----------,
CODE SELECTED 0111110011
(15)
V"e(1)
Figure 5. NE5410 Equivalent Circuit
November 14, 1986
122
Product Specification
10-Bit High-Speed Multiplying D/ A Converter
NE/SE5410
OUTPUT VOLTAGE
COMPLIANCE
0, THROUGH
0'0
The output voltage compliance ranges from
-2.5 to + 2.5V. As shown in Figure 2, this
compliance range is nearly constant over
temperature. At the temperature extremes,
however, the compliance voltage may be
reduced if VEE> -15V.
I
ACCURACY
Absolute accuracy is a measure of each
output current level with respect to its intended value; It is dependent upon relative accuracy and full-scale current drift. Relative accuracy, or linearity, is the measure of each
output current with respect to its intended
fraction of the full-scale current. The relative
accuracy of the NE541 0 is fairly constant
over temperature due to the excellent temperature tracking, of the implanted resistors.
The full-scale current from the reference
amplifier may drift with temperature causing a
change in the absolute accuracy. However,
the NE5410 has a low full-scale current drift
with temperature.
NOTES:
R,s+ RT = R'5 = RREF
RT < < R,s
10 F.S. = 2 IR = VREF/RREF
a. Positive Reference Voltabe
RT
0, THROUGH
0'0
The SE5410 and the NE5410 are accurate to
within ± 1;2 LSB at 25°C with a reference
current of 2.0mA on Pin 16.
I
MONOTONICITY
The NE5410 and SE5410 are guaranteed
monotonic over temperature. This means that
for every increase in the input digital code,
the output current either remains the same or
increases but never decreases. In the mUltiplying mode, where reference input current
will vary, monotonicity can be assured if the
reference input current remains above
O.5mA.
NOTES:
R'5+ RT = R,s
RT < < R'5
IVAEF;;' RVEE+ 3V
b. Negative Reference Voltage
Figure 6. Basic Connections
November 14, 1986
123
Product Specification
NEjSE5410
10-Bit High-Speed Multiplying DjA Converter
The major carry (MSB off-to-on, all others onto-off) settles in approximately the same time
as when all bits are switched off-to-on.
SETTLING TIME
The worst-case switching condition occurs
when all bits are switched "on," which corresponds to a LOW-to-HIGH transition for all
bits. This time is typically 250ns for the output
to settle to within ± Y2 LSB for 10-bit accuracy, and 200ns for 8-bit accuracy. The turn-off
time is typically 120ns. These times apply
when the output swing is limited to a small
( < 0.7V) swing and the external output capacitance is under 25pF.
If a load resistor of 625n is connected to
ground, allowing the output to swing to -2.5V,
the settling time increases to 1.5I-1s.
Extra care must be taken in board layout as
this is usually the dominant factor in satisfactory test results when measuring settling time.
Short leads, 100l-lF supply bypassing, and
minimum scope lead length are all necessary.
A typical test setup for measuring settling
time is shown in Figure 7. The same setup for
the most part can be used to measure the
slew rate of the reference amplifier (Figure 9)
by tying all data bits high, pulsing the voltage
reference input between 0 and 2V, and using
a 500n load resistor RL.
vee
0.1"F
~
14
16
+2Vdc
1k
I
1k
-=-500
RISE AND FALL TIMES
s
10ns
O1
. "F
RL-=-
Vo
J.
Vo
CO" 25pF
t. -
50
250n5 TYPICAL
TO %1/2 LSB
O.1"F
~
Vee
Figure 7. Settling Time
vee
0.1"F
14
~
RISE AND FALL TIMES" 10n5
1k
+2Vdc
1k
VI
10.1"F
Vo
Vo
RL
20
50
tpLH
0.1"F
vee
~
Figure 8_ Propagation Delay Time
November 14, 1986
tpHL
FOR PROPAGATION
DELAY TIME
124
Product Specification
10-Bit High-Speed Multiplying Dj A Converter
NEjSE5410
Vee
O.l"F
14
~
16
VREF( +)
.JL::2V
°
1k
2.ov
l
VREF( +)
lk
To.
RL
SOO
o
1"F
~
o.5v
Vo
~-i
_________________
h
USLEW RATE
Vo
°
J
V
,.;25pF
Is = 2.5 TYPICAL
TO
~O.l%
NOTE:
Use RL = 20[2 10 GND for slew rale measurement.
O.l."F
1
VEE
Figure 9. Reference Amplifier Settling Time and Slew Rate
--------------------------------------------~
F.S. ADJ
2.Sk
nRT
Vour
-15V
a. Bipolar Output (-10 to + 10V)
b. Unipolar Positive Output (0 - 10V)
Figure 10. Voltage Output Circuits
November 14, 1986
125
Product Specification
10-Bit High-Speed Multiplying D/ A Converter
ANALOG
INPUT
(O-10V)
NE/SE5410
+SVdc
20k
-V~+V
14
SOOk
3 V1+
~+-----~----~INA
NES410
V2+
NE529
2.Sk
°OUT
2504 SAR
CLOCK
+SVdc
NOTES:
10·bit conversion time = 3.3"s with 3M Hz clock.
This converter uses a 2504 12-bit successive approximation register in the short cycle operating mode where the end of conversion signal is taken from the first unused bit of the
SAR (010)'
Figure 11. Successive Approximation AID Converter
16
15
12
~P
LS373
8US
NES410
CONTROL {E2
SIGNALS
FROM ~P E1
Do
Qo
1/2 LS375
01 Eo,l Q1
TIMING SEQUENCE
E1~
E2---1'L-
OATA~
080,1
082-9
NOTE:
With this double latch technique, valid data will be latched to the DAC until updated with the E2 pulse. Timing will depend on the processor used.
Figure 12. B-Bit J.lP Bus Interface
November 14, 1986
126
Product Specification
10-Bit High-Speed Multiplying DjA Converter
VIN
NEjSE5410
+5V
3k
DOUT
NOTE:
( 1023 )
VIN FULL SCALE = 4mA (R, + RT)
1024
Figure 13. Staircase AID
November 14, 1986
127
NE/SE5532/5532A
Internally-Compensated Dual
low Noise Operational
Amplifier
Product Specification
DESCAIPTION
FEATURES
The 5532 is a dual high-performance low
noise operational amplifier. Compared to
most of the standard operational amplifiers, such as the 1458, it shows better
noise performance, improved output
drive capability and considerably higher
small-signal and power bandwidths.
• Small-signal bandwidth: 10MHz
• Output drive capability: 600n,
10VRMS
• Input noise voltage:
SnV 1v'Hz (typical)
• DC voltage gain: SOOOO
• AC voltage gain: 2200 at 10kHz
• Power bandwidth: 140kHz
This makes the device especially suitable for application in high-quality and
professional audio equipment, instrumentation and control circuits, and telephone channel amplifiers. The op amp is
internally compensated for gains equal
to one. If very low noise is of prime
importance, it is recommended that the
5532A version be used because it has
guaranteed noise voltage specifications.
PIN CONFIGURATIONS
• Slew rate: 9V IllS
• Large supply voltage range: ± 3
to ± 20V
• Compensated for unity gain
OUTPUT A
INVERTING
INPUT A
NON·INVERTING
INPUT A
INVERTING
INPUT B
NON·INVERTING
INPUT B
TOP VIEW
D Package 1
NC
NC
Ne
OUTA
+Vcc
NC
TOP VIEW
NOTE:
1. SOL and non·standard pinout.
EQUIVALENT SCHEMATIC (EACH AMPLIFIER)
I
0
+
January 15, 1988
129
853-0949 91980
Product Specification
Internally-Compensated Dual Low Noise
Operational Amplifier
NEjSE5532j5532A
ORDERING INFORMATION
TEMPERATURE RANGE
DESCRIPTION
o to
o to
o to
o to
8-Pin Plastic DIP
8-Pin Ceramic DIP
8-Pin Plastic DIP
8-Pin Ceramic DIP
ORDER CODE
70°C
NE5532N
70°C
NE5532FE
70°C
NE5532AN
70°C
NE5532AFE
8-Pin Ceramic DIP
-55°C to +125°C
SE5532FE
8-Pin Ceramic DIP
-55°C to + 125°C
SE5532AFE
o to
16-Pin Plastic SOL
70°C
NE5532D
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Vs
Supply voltage
VIN
Input voltage
VOIFF
Differential input voltage 1
RATING
UNIT
±22
V
± VSUPPLY
V
±0.5
V
Operating temperature range
NE5532/A
SE5532/A
o to 70
-55 to + 125
°C
°C
TSTG
Storage temperature
-65 to +150
°C
TJ
Junction temperature
150
°C
Po
Maximum power dissipation,
TA = 25°C, (still-air)2
N package
F package
D package
1200
1000
1200
mW
mW
mW
Lead soldering temperature (10sec max)
300
°C
TA
TSOLO
NOTES:
1. Diodes protect the inputs against over-voltage. Therefore, unless current-limiting resistors are used, large
currents will flow if the differential input voltage exceeds O.6V. Maximum current should be limited to
±10mA.
.
2. Thermal resistances of the above packages are as follows:
N package at 100°C/W.
F package at 135°C/W.
D package at 105°C/W.
January 15, 1988
130
Product Specification
Internally-Compensated Dual low Noise
Operational Amplifier
NE/SE5532/5532A
DC ELECTRICAL CHARACTERISTICS TA = 25°C, Vs = ± 15V, unless otherwise specified. 1,
SE5532/5532A
SYMBOL
PARAMETER
UNIT
Offset voltage
Typ
Max
0.5
Over temperature
~Vos/~T
los
~los/~T
Supply current
VCM
Common-mode input range
CMRR
Common-mode rejection ratio
PSRR
Power supply rejection ratio
Large-signal voltage gain
r
VOUT
Max
2
3
0.5
4
5
mV
mV
/lVrC
100
200
10
150
200
nA
nA
400
700
200
10.5
13
8
5
Output swing
8
Over temperature
pA/oC
200
5
~ls/~T
I AVOL
Typ
200
200
Input current
Over temperature
Icc
Min
5
Offset current
Over temperature
Is
NE5532/5532A
TEST CONDITIONS
Min
Vas
2, 3
800
1000
nA
nA
nArC
16
mA
mA
5
±12
±13
±12
±13
V
80
100
70
100
dB
RL ?>2kn, Vo= ± 10V
Over temperature
RL?> 600n, Vo = ± 10V
Over temperature
50
25
40
20
100
25
15
15
10
100
RL ?>600n
Over temperature
RL?> 600n, Vs = ± 18V
Over temperature
RL?>2kn
Over temperature
±12
±10
±15
±12
±13
±12
±13
±12
±16
±14
± 13.5
± 12.5
±12
±10
±15
±12
±13
±10
±13
±12
±16
±14
± 13.5
± 12.5
30
300
10
38
10
50
RIN
Input resistance
30
300
Isc
Output short circuit current
10
38
10
50
60
100
/lVN
V/mV
V/mV
V/mV
V/mV
50
V
V
V
V
V
V
kn
60
mA
NOTES:
1. Diodes protect the inputs against overvoltage. Therefore, unless current-limiting resistors are used, large currents will flow if the differential input
voltage exceeds O,6V. Maximum current should be limited to ± 10mA.
2. For operation at elevated temperature, derate packages based on the package thermal resistance.
3. Output may be shorted to ground at Vs = ± 15V, TA = 25°C. Temperature and/or supply voltages must be limited to ensure dissipation rating is not
exceeded.
January 15, 1988
131
Product Specification
Internally-Compensated Dual Low Noise
Operational Amplifier
NE/SE5532/5532A
AC ELECTRICAL CHARACTERISTICS T A = 25°C, Vs = ± 15V, unless otherwise specified.
NE/SE5532/5532A
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT
Min
ROUT
Typ
Max
Output resistance
Av = 30dB Closed-loop
f = 10kHz, RL = 60051
0.3
51
Overshoot
Voltage-follower
VIN = 100mVp.p
CL = 100pF, RL = 60051
10
%
f = 10kHz
2.2
V/mV
CL = 100pF, RL = 60051
10
MHz
9
V/J.Ls
140
100
kHz
kHz
Av
Gain
GBW
Gain bandwidth product
SR
Slew rate
Power bandwidth
VOUT = ± 10V
VOUT = ± 14V, RL = 60051,
Vcc=±18V
ELECTRICAL CHARACTERISTICS TA = 25°C, Vs = ± 15V, unless otherwise specified.
NE/SE5532
PARAMETER
SYMBOL
NE/SE5532A
TEST CONDITIONS
UNIT
Min
Typ
Max
Min
Typ
Max
12
6
VNOISE
Input noise voltage
fo = 30Hz
fo = 1kHz
8
5
8
5
INOISE
Input noise current
fo = 30Hz
fo= 1kHz
2.7
0.7
2.7
0.7
pA/YHz
pAlYHz
Channel separation
f = 1kHz, Rs = 5kn
110
110
dB
January 15, 1988
132
nV/YHz
nV/YHz
Product Specification
Internally-Compensated Dual Low Noise
Operational Amplifier
NE/SE5532/5532A
TYPICAL PERFORMANCE CHARACTERISTICS
Open-Loop Frequency
Response
Closed-Loop Frequency
Response
120
eo
,
'\
i
10
1,\
0
10'
10' 10'
10'
111'
10'
10'
l
30
(V)
Vo(p-P) 20
L=1k",Loo
0
~
10'
10'
10'
f(Hz)
I(Hz)
VS = ttS
TYPICAL VALUES
TYPICAL VALUES
RtLJ."
-20
10'
10
.
RF= lIMen: AE = 100n
20
\
-10
10
_1.1
..
'\
~
!
10
TYPICAL VALUES
Large-Signal Frequency
Response
~
10
\
0, 0'
HI'
10'
10'
111'
'to10'
10'
I (Hz)
OPT......
OPT.....
OP048705
Output Short-Circuit Current
Input Common-Mode
Voltage Range
Input Bias Current
eo
30
1.'
VS= :I:,5V
= !lSV
Vs
TYPICAL VALUES
1.2
10
20
.........
(!~)
10
'"
r- to!!! I -+--
"
(~A)
0 .•
o.•
20
o
-25
-5$
25
0
.
TA("C)
.
,
~ .........
0
100 1"125
55 -25
-
"'"
25
0
50
"
/
0
100
12.
OP04"OS
Input Noise Voltage Density
'0= 0
Ip
f
'N
(mA)
TVP
~ I--
-
..........
10
(nV/v'Hi)
TYP
1
10·'
0
'0. 2
0
10
Vp; -VN (V)
20
10
10'
10'
10'
I (Hz)
....
.,..
OP0413OS
January 15, 1988
133
0
10
20
VP;-VN (V)
10'
.
.
/
-r0-
OPCMOOOS
Supply Current
/
10
TA(OC)
12
/
V,N (V)
OP04I20S
Product Specification
Internally-Compensated Dual Low Noise
Operational Amplifier
NE/SE5532/5532A
TEST CIRCUITS
RS
25n
1K
v-
lOOn
Closed-Loop Frequency Response
January 15, 1988
Voltage-Follower
134
NE5533/5533A
NE/SA/SE5534/5534A
Dual and Single Low Noise
Op Amp
Product Specification
DESCRIPTION
FEATURES
The 5533/5534 are dual and single highperformance low noise operational amplifiers. Compared to other operational
amplifiers, such as TL083, they show
better noise performance, improved output drive capability and considerably
higher small-signal and power bandwidths.
• Small-signal bandwidth: 10MHz
• Output drive capability: 600n,
10VRMS at Vs = ± 18V
• Input noise voltage: 4nV IvlHZ
• DC voltage gain: 100000
• AC voltage gain: 6000 at 10kHz
• Power bandwith: 200kHz
• Slew rate: 13VI p.s
• Large supply voltage range: ± 3
to ±20V
• 5534 MIL-STD processing
available
This makes the devices especially suitable for application in high quality and
professional audio equipment, in instrumentation and control circuits and telephone channel amplifiers. The op amps
are internally compensated for gain
equal to, or higher than, three. The
frequency response can be optimized
with an external compensation capacitor
for various applications (unity gain amplifier, capacitive load, slew rate, low overshoot, etc.) If very low noise is of prime
importance, it is recommended that the
5533A15534A version be used which
has guaranteed noise specifications.
PIN CONFIGURATIONS
NE/SA/SE5534/5534A
D, FE, N Packages
BALANCE/
COMPENSATION
INVERTING
INPUT
NONINVERTING
INPUT
NE5533/5533A
N Package
APPLICATIONS
• Audio equipment
• Instrumentation and control
circuits
• Telephone channel amplifiers
• Medical equipment
TOP VIEW
ORDERING INFORMATION
DESCRIPTION
14-Pin Plastic DIP
16-Pin Plastic SO package
14-Pin Plastic DIP
16-Pin Plastic SO package
8-Pin Plastic SO package
8-Pin Hermetic Cerdip
8-Pin Plastic DIP
8-Pin Plastic SO package
8-Pin Hermetic Cerdip
8-Pin Plastic DIP
NE5533/5533A
TEMPERATURE RANGE
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
ORDER CODE
+70°C
NE5533N
+70°C
NE5533AD
+70°C
NE5533AN
+70°C
NE5533D
1)2
+70°C
NE5534D
+70°C
NE5534FE
+70°C
NE5534N
+70°C
NE5534AD
+70°C
NE5534AFE
+70°C
NE5534AN
8-Pin Plastic DIP
-40·C to + 85°C
SA5534N
8-Pin Plastic SO package
-40°C to + 85°C
SA5534AD
8-Pin Plastic DIP
-40°C to + 85°C
SA5534AN
8-Pin Hermetic Cerdip
-55°C to + 125°C
SE5534AFE
8-Pin Plastic DIP
-55°C to +125°C
SE5534N
8-Pin Hermetic Cerdip
-55°C to + 125°C
SE5534FE
8-Pin Plastic DIP
-55°C to + 125°C
SE5534AN
November 3, 1987
D Package
135
INVINPUTA 1
NON·INV
INPUTA
BALANCE A
3
BALANCEB
5
NON·INVB
6
BALANCE I
COMPB
TOP VIEW
NOTE:
This device may not be symboled in standard
format.
853-0222 91250
Product Specification
NE5533/5533A
NE/SA/SE5534/5534A
Dual and Single Low
Noise Op Amp
EQUIVALENT SCHEMATIC
November 3, 1987
136
Product Specification
NE5533/5533A
NE/SA/SE5534/5534A
Dual and Single Low
Noise Op Amp
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Vs
Supply voltage
VIN
Input voltage
VOIFF
Differential input voltage 1
TA
RATING
UNIT
±22
V
±V supply
V
±0.5
V
Operating temperature range
SE
SA
NE
-55 to +125
-40 to +85
o to +70
°C
°C
°C
TSTG
Storage temperature range
-65 to +150
°C
TJ
Junction temperature
150
°C
Po
Power dissipation at 25°C 2
55330
5533N
55340
5534FE
5534N
1350
1500
750
800
1150
mW
mW
mW
mW
mW
Output short-circuit duration3
Indefinite
TsoLO
Lead soldering temperature (10sec
max)
300
°C
NOTES:
1. Diodes protect the inputs against over voltage. Therefore, unless current-limiting resistors are used, large
currents will flow if the differential input voltage exceeds O.6V. Maximum current should be limited to
±10mA.
2. For operation at elevated temperature, derate packages based on the following junction-to-ambient
thermal resistance:
8-pin ceramic DIP 150°C/W
8-pin plastic DIP 105°C/W
8-pin plastic SO 160°C/W
14-pin plastic DIP 80°C/W
16-pin plastic SO 90°C/W
3. Output may be shorted to ground at Vs = ± 15V, TA = 25°C. Temperature and/or supply voltages must be
limited to ensure dissipation rating is not exceeded.
November 3, 1987
137
Product Specification
NE5533/5533A
NE/SA/SE5534/5534A
Dual and Single Low
Noise Op Amp
DC ELECTRICAL CHARACTERISTICS TA = 25°C, Vs = ± 15V, unless otherwise specified. 1.
SE5534/5534A
PARAMETER
SYMBOL
TEST CONDITIONS
Min
Vas
Offset voltage
Typ
Max
0.5
Over temperature
I1Vas/ !1T
5
los
10
Offset current
Over temperature
I11os/l1T
200
Is
400
Input current
Over temperature
NE5533/5533A
NE/SA5534/5534A
Min
Icc
Supply current
per op amp
VCM
CMRR
PSRR
Common mode input range
Common mode rejection ratio
Power supply rejection ratio
AVOL
Large-signal voltage gain
Output swing
RIN
Input resistance
Isc
Output short circuit current
4
Over temperature
±12
80
±13
100
10
RL #600n, Va = ± 10V
Over temperature
50
25
RL#600n
Over temperature
RL # 600n, Vs = ± 18V
RL#2kn
Over temperature
Max
2
3
0.5
4
5
mV
mV
p.V/oC
200
500
20
300
400
nA
nA
pArc
1500
2000
nA
nA
nAloC
8
10
mA
mA
100
V
dB
p.V/v
5
200
800
1500
500
6.5
9
4
November 3, 1987
138
5
±12
70
±13
100
10
100
25
15
100
V/mV
V/mV
±12
±10
±15
±13
±12
±13
±12
±16
± 13.5
± 12.5
±12
±10
±15
±13
±12
±13
±12
±16
± 13.5
± 12.5
V
V
V
V
V
50
100
30
100
kn
38
mA
38
NOTES:
1. For NE5533/5533A/5534/5534A, TMIN = ooe, TMAX = 70°C.
2. For SE5534/5534A, TMIN = -55°C, T MAX = + 125°C.
3. For SA5534/5534A, TMIN = -40°C, T MAX = + 125°C.
UNIT
Typ
5
I1ls/I1T
VOUT
2. 3
50
Product Specification
NE5533/5533A
NE/SA/SE5534/5534A
Dual and Single Low
Noise Op Amp
AC ELECTRICAL CHARACTERISTICS TA = 25°C, Vs = ± 15V, unless otherwise specified.
NE5533/5533A
NESA5534/5534A
SE5534/5534A
SYMBOL
PARAMETER
TEST CONDITIONS
Min
ROUT
tR
Output resistance
Av = 30dB closed-loop
f = 10kHz, RL = 600n,
Ce = 22pF
Transient response
Voltage-follower,
VIN = 50mV
RL = 600n, Ce = 22pF,
CL = 100pF
Min
Typ
UNIT
Max
0.3
n
Rise time
20
20
ns
Overshoot
20
20
%
Rise time
50
50
ns
Overshoot
35
35
%
6
2.2
6
2.2
V/mV
V/mV
Av
Gain
GBW
Gain bandwidth product
SR
Max
0.3
Transient response
tR
Typ
VIN = 50mV, RL = 600n
Ce = 47pF, CL = 500pF
f = 10kHz, Ce = 0
f = 10kHz, Ce = 22pF
Slew rate
Power bandwidth
Ce = 22pF, CL = 100pF
10
10
MHz
Ce=O
Ce = 22pF
13
6
13
6
V/lJ.s
V/lJ.s
VOUT=±10V, Ce=O
VOUT = ± 10V, Ce = 22pF
VOUT = ± 14V, RL = 600n
Ce = 22pF, Vee = ± 18V
200
95
70
200
95
70
kHz
kHz
kHz
ELECTRICAL CHARACTERISTICS TA = 25°C, Vs = 15V, unless otherwise specified.
5533A/5534A
5533/5534
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Typ
Max
Min
Typ
Max
7
4.5
nV/y'Hz
nV/y'Hz
VNOISE
Input noise voltage
fa = 30Hz
fa = 1kHz
7
4
5.5
3.5
INOISE
Input noise current
fa = 30Hz
fa = 1kHz
2.5
0.6
1.5
0.4
pA/y'Hz
pA/y'Hz
0.9
dB
110
dB
Broadband noise figure
Channel separation
November 3, 1987
f = 10Hz - 20kHz,
Rs= 5kn
f = 1kHz, Rs = 5kn
139
110
Product Specification
NE5533/5533A
NE/SA/SE5534/5534A
Dual and Single Low
Noise Op Amp
TYPICAL PERFORMANCE CHARACTERISTICS
Slew Rate as a Function of
Compensation Capacitance
Open-Loop Frequency
Response
•
120
TYPICAL VALUES
v£= i15V
it
"I~
80
",,~C~O
1
CC~ 22pF",,~
S
IV/".)
~~
Closed-Loop Frequency
Response
.i
~
~
"~P
~
-40
10
102
10J
10'
10'
1Q1
10 '
o
o
80
CclpF)
11Hz)
Large-Signal Frequency
Response
Output Short-Circuit Current
Input Bias Current
I,'
VS.: t15V
TYPICAL VALUES
Vs = t15V
Va
1,2
CC~
OpF
.........
~~~2PF
47pF
IV)
VO(P-P) 20
o
l1
l\\
\\\
102
~~
10)
10"
lOS
1()1
~
r- ~
--
~
~)o,.
"'-
0,'
TVP
""r--
-
o
o
-55
-55
10 1
t(Hz}
Input Common-Mode
Voltage Range
Supply Current
per Op Amp
TYPICAL VALUES
10
--- -
~
0
r----.
TYP
20
~
VINIV)
~
r
~OS
pV
o
Input Noise
Voltage Density
o
2
(nVlv'Hi:)
TVP
1
V
20
Vp; -VN IV)
November 3, 1987
o
o
10
20
Vp; -VN IV)
140
I (Hz)
= :t:1SV
Product Specification
NE5533/5533A
NE/SA/SE5534/5534A
Dual and Single Low
Noise Op Amp
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Total Input
Noise Density
Input NOise
Current Density
Broadband Input
Noise Voltage
TYPICAL VALUES
"'-
/
~
Vn(rma) 10'
(nVI.rHi)
-
f--
v-:
/ V
10Hz
1kHz
~~
t;:::::"1~ ~~~~~:~~~II::A~E
V
'0''0
10
102
f(Hz)
101
10~
105
'1--+--+--+----1f--+-4
10'
RS(II)
RS (ll)
TEST LOAD CIRCUITS
V+
6
600ll
vFrequency Compensation and Offset Voltage
Adjustment Circuit
November 3, 1987
Closed-Loop Frequency Response
141
Product Specification
NE5533/5533A
NE/SA/SE5534/5534A
Dual and Single Low
Noise Op Amp
NOISE TEST BLOCK DIAGRAM
1\
nV/v'Hz
BANDPASS
AT 1 kHz
J\
BANDPASS
AT 30 Hz
-=-
November 3, 1987
GND
142
nV/.JHz
NEjSA602
Double-Balanced Mixer and
Oscillator
Product Specification
DESCRIPTION
FEATURES
The SA/NE602 is a low-power VHF
monolithic double-balanced mixer with
input amplifier, on-board oscillator, and
voltage regulator. It is intended for high
performance, low power communication
systems. The guaranteed parameters of
the SA602 make this device particularly
well suited for cellular radio applications.
The mixer is a "Gilbert cell" multiplier
configuration which typically provides
18dB of gain at 45MHz. The oscillator
will operate to 200M Hz. It can be configured as a crystal oscillator, a tuned tank
oscillator, or a buffer for an external L.O.
The noise figure at 45MHz is typically
less than 5dB. The gain, intercept performance, low-power and noise characteristics make the SAlNE602 a superior
choice for high-performance battery operated equipment. It is available in an 8lead dual in-line plastic package and an
8-lead SO (surface-mount miniature
package).
• Low current consumption: 2.4mA
typical
• Excellent noise figure: < 5.0dB
typical at 45MHz
• High operating frequency
• Excellent gain, intercept· and
sensitivity
• Low external parts count;
suitable for crystal/ceramic filters
• SA602 meets cellular radio
specifications
PIN CONFIGURATION
INPUT A u 8 Vee
INPUT B
2
7
OSCILLATOR
GROUND
3
6
OSCILLA TOR
OUTPUT A 4
5
OUTPUT B
APPLICATIONS
•
•
•
•
•
•
Cellular radio mixer/oscillator
Portable radio
VHF transceivers
RF data links
HF/VHF frequency conversion
Instrumentation frequency
conversion
• Broadband LANs
BLOCK DIAGRAM
November 9, 1987
143
853-0390 91374
Product Specification
Mixer and Oscillator
Double~Balanced
NE/SA602
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
o to
o to
o to
8-Pin Plastic DIP
8-Pin Plastic SO
8-Pin Cerdip
ORDER CODE
+70°C
NE602N
+70°C
NE602D
+70°C
NE602FE
8-Pin Plastic DIP
-40°C to + 85°C
8-Pin Plastic SO
-40°C to + 85°C
SA602D
8-Pin Cerdip
-40°C to + 85°C
SA602FE
-
SA602N
ABSOLUTE MAXIMUM RATINGS
r-----.
SYMBOL
PARAMETER
Vee
Maximum operating vOltage
TSTG
TA
RATING
UNIT
9
V
Storage temperature
-65 to +150
°C
Operating ambient temperature range
NE602
SA602
o to +70
-40 to +85
°C
°C
AC/DC ELECTRICAL CHARACTERISTICS
T A = 25°C, Vce = 6V, Figure 1
-LIMITS
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT
Min
Vee
Power supply voltage range
DC current drain
f---!IN
fose
Typ
4.5
2.4
Max
8.0
V
2.8
mA
Input signal frequency
500
MHz
Oscillator frequency
200
MHz
Noise figured at 45MHz
Third-order intercept point
RFIN
= -45dBm:
f1 = 45.0
f2 = 45.06
Conversion gain at 45MHz
14
RIN
RF input resistance
1.5
CIN
RF input capacitance
5.0
6.0
dB
-15
-17
dBm
kSl
3
Mixer output resistance
(Pin 4 or 5)
dB
18
1.5
3.5
pF
kSl
DESCRIPTION OF OPERATION
0.5 to
1.3~H
122PF
I
~
44.545MHz THIRD OVERTONE CRYSTAL
Vee
150pF
602
1.5 to
44.2p
~
120pF
Figure 1. Test Configuration
November 9, 1987
144
The NE/SA602 is a Gilbert cell, an oscillatorl
buffer, and a temperature compensated bias
network as shown in the equivalent circuit.
The Gilbert cell is a differential amplifier (Pins
1 and 2) which drives a balanced switching
cell. The differential input stage provides gain
and determines the noise figure and signal
handling performance of the system.
The NE/SA602 is designed for optimum low
power performance. When used with the
SA604 as a 45MHz cellular radio 2nd IF and
demodulator, the SA602 is capable of receiving -119dBm signals with a 12dB SIN ratio.
Third-order intercept is typically -15dBm
(that's approximately +5dBm output intercept
because of the RF gain). The system designer must be cognizant of this large signal
limitation. When designing LANs or other
closed systems where transmission levels are
high, and small-signal or signal-to-noise
issues not critical, the input to the NE602
should be appropriately scaled.
Product Specification
Double-Balanced Mixer and Oscillator
Besides excellent low power performance
well into VHF, the NE/SA602 is designed to
be flexible. The input, output, and oscillator
ports can support a variety of configurations
provided the designer understands certain
constraints, which will be explained here.
The RF inputs (Pins 1 and 2) are biased
internally. They are symmetrical. The equivalent AC input impedence is approximately
1.5k II 3pF through 50MHz. Pins 1 and 2 can
be used interchangeably, but they should not
be DC biased externally. Figure 3 shows
three typical input configurations.
The mixer outputs (Pins 4 and 5) are also
internally biased. Each output is connected to
the internal positive supply by a 1.5kn resistor. This permits direct output termination yet
allows for balanced output as well. Figure 4
shows three single ended output configurations and a balanced output.
The oscillator is capable of sustaining oscillation beyond 200M Hz in crystal or tuned tank
configurations. The upper limit of operation is
determined by tank "0" and required drive
levels. The higher the "0" of the tank or the
smaller the required drive, the higher the
NE/SA602
permissible oscillation frequency. If the required L.O. is beyond oscillation limits, or the
system calls for an external L.O., the external
signal can be injected at Pin 6 through a DC
blocking capacitor. External L.O. should be at
least 200rnVp_p.
Figure 5 shows several proven oscillator
circuits. Figure 5a is appropriate for cellular
radio. As shown, an overtone mode of operation is utilized. CapaCitor C3 and inductor L1
suppress oscillation at the crystal fundamental frequency. In the fundamental mode, the
suppression network is omitted.
Figure 6 shows a Colpitts varacter tuned tank
oscillator suitable for synthesizer-controlled
applications. It is important to buffer the
output of this circuit to assure that switching
spikes from the first counter or presca1er do
not end up in the oscillator spectrum. The
dual-gate MOSFET provides optimum isolation with low current. The FET offers good
isolation, simplicity, and low current, while the
bipolar transistors provide the simple solution
for non-critical applications. The resistive divider in the emitter-foliower circuit should be
chosen to provide the minimum input Signal
which will assure correct system operation.
When operated above 100MHz, the oscillator
may not start if the 0 of the tanK is too low. A
22kn resistor from Pin 7· to ground will
increase the DC bias current of the oscillator
transistor. This improves the AC operating
characteristic of the transistor and should
help the oscillator to start. 22kn will not upset
the other DC biasing internal to the device,
but smaller resistance values should be
avoided.
ill
GND
Figure 2. Equivalent Circuit
L
+
TC020415
a. Single-Ended Tuned Input
November 9, 1987
b. Balanced Input (For Attenuation
of Second-Order Products)
Figure 3. Input Configuration
145
c. Single-Ended Untuned Input
Product Specification
Double-Balanced Mixer and Oscillator
NE/SA602
CFU455
OR EQUIVALENT
602
102
a. Single-Ended Ceramic Filter
FILTER K&L38780 OR EQUIVALENT
·Cr MATCHES 3.SKll TO NEXT STAGE.
b. Single-Ended Crystal Filter
c. Single-Ended 1FT
d. Balanced Output
Figure 4. Output Configuration
R
1
602
602
b. Colpitts LIC Tank Oscillator
c. Hartley LIC Tank Oscillator
602
a. Colpitts Crystal Oscillator
(Overtone Mode)
Figure 5. Oscillator Circuits
November 9, 1987
146
Product Specification
Double-Balanced Mixer and Oscillator
NE/SA602
5.5I'H
L.....,_-_-o+tiV
t--...----<_--.. ~~FFER
5
"-------..
l000PFf~
1 ..
l000pF
O.06I'H
-=-
t
t
DC CONTROL VOLTAGE
FROM SYNTHESIZER
MV2105
OR EQUIVALENT
JO.01PF
lOOK
2K
3SKI26
O.OlpF
~--fl----It----o
TO SYNTHESIZER
lO.DlpF
Figure 6. Colpitts Oscillator Suitable for Synthesizer Applications and Typical Buffers
0.5 to 1.3j\' K2000·YSI' c..lmlc
C12 6 BuF: 20°" 25\' Tlnl.lum
FI 455kHz c..lm.c Fill .. Murata SFG4SSA3
F2 455kHZ IF FII1&'
I'll sIn'I'" 1'41'01 Meal Film
R2 I Soon ,I'" 1'41'01 Melal Film
1'13 I SOOn, 5°.. I 181'01 ~rt>on CompoS-lion
1'14100.,,1,1.,. 1/41'01 Metal Film
FI ure 1. NE614A Test Circuit
171
Preliminary Specification
Low Power FM IF System
NE/SA614A
Figure 2. Equivalent Circuit
Circuit Description
The NElSA614A Is a very high gain,
high frequency device. Correct
operation Is not possible If good RF
layout and gain stage practices are
not used. The NElSA614A can not
be evaluated Independent of circuit,
components, and board layout. A
physical layout which correlates to
the electrical limits Is shown In Figure 1. This configuration can be
used as the basis for production
layout.
The NE/SA614A is an IF signal processing system suitable for IF frequencies as high as 21.4MHz. The device
consists of two limiting amplifiers,
quadrature detector, direct audio out·
put, muted audio output, and signal
strength indicator (with log output char-
acteristic).
The sub-systems are
shown in Figure 2. A typical application
with 45MHz input and 455kHz IF is
shown in Figure 3.
IF Amplifiers
The IF amplifier section consists oftwo
log-limiting stages. Thefirst consists of
two differential amplifiers with 39dB of
gain and a small signal bandwidlh of
41 MHz (when driven from a 50n
source). the output of the first limiter is
a low impedance emitter follower with
1kn of equivalent series resistance.
The second limiting stage consists of
three differential amplifiers with a gain
of 62dB and a small signal AC bandwidth of 28MHz. The outputs of the
final differential stage are buffered to
the internal quadrature detector. One
of the outputs is available at Pin 9 to
172
drive an external quadrature capacitor
and UC quadrature tank.
Both ofthe limiting amplifier stages are
DC biased using feedback. The buffered output of the final differential
amplifier is fed back to the input
through 42kn resistors. As shown in
Figure 2 the input impedance is established for each stage by tapping one of
the feedback resistors 1.6kn from the
input. This requires one additional
decoupling capacitor from the tap point
to ground.
Because of the very high gain, bandwidth and input impedance of the limiters, there is a very real potential for
instability at IF frequencies above
455kHz. The basic phenomenon is
shown in Figure 6. Distributed feed-
Preliminary Specification
Low Power FM IF System
NE/SA614A
NEtUA F HPLIT (jIV) (11OCOJ
tV
,v
2V
,v
_ 2 . . INPUT (iIIIm) (III! I)
Figure 3. TyplCIII Application Cellular Radio (45MHz to 455kHz)
back (capacitance, inductance and
radiated fields) forms a divider from the
output of the lim iters back to the inputs
(including the RF input). If this feedback divider does not cause attenuation greater than the gain of the forward path, then oscillation or low level
regeneration is likely. If regeneration
occurs, two symptoms may be present:
(1 )The RSSI output will be high with no
signal input (should nominally be
250mV or lower), and (2) the demodulated output will demonstrate a threshold. Above a certain input level, the
limited signal will begin to dominate the
regeneration, and the demodulator will
begin to operate in a Rnormal" manner.
42K
15~--~~~~~------------~
11~---r--~~~~----------~
There are three primary ways to deal
with regeneration: (1) Minimize the
FI ure 4. First Umlter Bias
173
Preliminary Specification
Low Power FM IF System
NE/SA614A
421(
12
8
10K
Figure S. Second Umlter and Quadrature Detector
r--------;..._z,-"'r----------l
~--i ..
I
I
t---r--="-="-="-:l-I .. t----
--.-
H
I
_--..1
z,
I-i ---- rl
I
I
z,
I
I
J
H
1
1
I
r
Figure 6. Feedback Paths
feedback by gain stage isolation, (2)
lower the stage input impedances, thus
increasing the feedback attenuation
factor, and (3) reduce the gain. Gain
reduction can effectively be accomplished by adding attenuation between
stages. This can also lower the input
impedance if well planned. Examples
of impedance/gain adjustment are
shown in Figure 7. Reduced gain will
result in reduced limiting sensitivity.
A feature of the NE614A IF amplifiers,
which is not specified, is low phase
shift. The NE614A is fabricated with a
1OGHz process with very small collec-
tor capacitance. It is advantageous in
some applications that the phase shift
changes only a few degrees over a
wide range of signal input amplitudes.
Additional information will be provided
in the upcoming product specification
(this is a preliminary specification)
when characterization is complete.
Stability Considerations
The high gain and bandwidth of the
NE614A in combination with its very
low currents permit circuit implementation with superior performance. However, stability must be maintained and,
to do that, every possible feedback
174
mechanism must be addressed.
These mechanisms are: 1) Supply
lines and ground, 2) stray layout inductances and capacitances, 3) radiated
fields, and 4) phase shift. As the system IF increases, so mustthe attention
to fields and strays. However, ground
and supply loops cannot be overlooked, especially at lower frequencies. Even at 455kHz, using the test
layout in Figure 1, instability will occur
if the supply line is not decoupled with
two high quality RF capacitors, a 0.1 p,F
monoflthic right at the Vcc pin, and a
6.8p,F tantalum on the supply line. An
electrolytic is not an adequate substitute. At 10. 7MHz, a 1p,F tantalum has
proven acceptible with this layout.
Every layout must be evaluated on its
own merit, but don't underestimate the
importance of good supply bypass.
At 455kHz, if the layout of Figure 1 or
one substantially similar is used, it is
possible to directly connect ceramic
filters to the input and between limiter
stages with no special consideration.
At frequencies above 2M Hz, some
input impedance reduction is usually
necessary. Figure 7 demonstrates a
practical means.
As illustrated in Figure 8,
4300
external resistors are applied in parallel to the internal 1.6kQ load resistors,
thus presenting approximately 3300 to
Preliminary Specification
Low Power FM IF System
NE/SA614A
Q9-o-1BPF
Low Impedance
7a. Terminating High Impedance Filters with Transformation to Low Impedance
I
I
Resistive Loss into BPF
T -----~
TL-------------
-
7b. Low Impedance Termination and Gain Reduction
Figure 7. Practical Termination
the filters. The input filter is a crystal
type for narrow-band selectivity. The
filter is terminated with a tank which
transforms to 3300. The interstage
filter is a ceramic type which doesn't
contribute to system selectivity, but
does suppress wideband noise and
stray signal pickup.
In wideband
10.7MHz IFs the input filter can also be
ceramic, directly connected to Pin 16.
In some products it may be impractical
to utilize shielding, but this mechanism
may be appropriate to 10. 7MHz and
21.4MHz IF. One of the benefits of low
current is lower radiated field strength,
but lower does not mean non-existent.
A spectrum analyzer with an active
probe will clearly show IF energy with
the probe held in the proximity of the
second limiter output or quadrature
coil. No specific recommendations are
provided, but mechanical shielding
should be considered if layout, bypass,
and input impedance reduction do not
solve a stubborn instability.
phase shift. The phase shift of the
limiters is very low, but there is phase
shift contribution from the quadrature
tank and the filters. Most filters demonstrate a large phase shift across their
passband (especially at the edges). If
the quadrature detector is tuned to the
edge of the filter passband, the combined filter and quadrature phase shift
can aggravate stability. This is not
usually a problem, but should be kept in
mind.
The final stability consideration is
430
430
614A
ut Filter with Ceramic Intersta e Filter
175
Preliminary Specification
Low Power FM IF System
NE/SA614A
Quadrature Detector
Figure 5 shows an equivalent circuit of
the NE614A quadrature detector. It is
a multiplier cell similar to a mixer stage.
Instead of mixing tw.o different frequencies, it mixes two signals of common
frequency but different phase. Internal
to the device, a constant amplitude
(limited) signal is differentially applied
to the lower port of the multiplier. The
same signal is applied single ended to
an external capacitor at Pin 9. There is
a 90 0 phase shift across the plates of
this capacitor, with the phase shifted
signal applied to the upper port of the
multiplier at Pin 8. A quadrature tank
(parallel lIC network) permits frequency selective phase shifting at the
IF frequency. This quadrature tank
must be returned to ground through a
DC blocking capacitor.
a
The loaded
of the quadrature tank
impacts three fundamental aspects of
the detector: Distortion, maximum
modulated peak daviation, and audio
output amplitude. Typical quadrature
curves are illustrated in Figure 10. The
phase angle translates to a shift in the
multiplier output voltage.
Thus a small deviation gives a large
output with a high tank. However, as
the deviation from resonance increases, the nonlinearity of the curve
increases (distortion), and, with too
much deviation, the signal will be outside the quadrature region (limiting the
peak deviation which can be demodulated). If the same peak deviation is
applied to a lower a tank, the deviation
will remain in a region of the curve
which is more linear (less distortion),
but creates a smaller phase angle
(smaller output amplitude). Thus the a
of the quadrature tank must be tailored
to the design. Basic equations and an
example for determining are shown
below. This explanation includes first
order effects only.
Multiplying the two signals in the mixer,
and low pass filtering yields:
(4)
FI ure 9.
after low pass filtering
~
(1b)
V
aIr
=.!.- A2
(5)
2
(1c)
From the above equation, the phase
shift between nodes 1 and 2, or the
phase across Cs will be:
(2)
a
a
Figure 10. Is the plot of. VS.
(1a)
1t
shift is
2"
and the response is close
to a straight line with a slope of
~
= 20 1
flO)
::::"f~v~(:,):1::h::pect
0)1
Which is the discriminated FM output.
(Note that &0> is the deviation frequency from the carrier 0>,.)
Ref. Krauss, Raab, Bastian; Solid
State Radio Eng.; Wiley,1980, p.311.
Example: At 455kHz IF, with ±5kHz
FM deviation. The maxImin normalized frequency will be
455 ±5kHz
455
- 1.0100rO.990
Go to the, vs. normalized frequency
curves (Figure 10) and draw a vertical
to the V,N •
straight line at
(3)
~ Vo=A
Vo= - - - .
C p + Cs
+
(:.1
It is notable that at 0> ... 0>1' the phase
Frequency discriminator design
equations for NE614A
Cs
For
176
1.01. The
curves with a .. 100, a - 40 are not
linear, but a .. 20 and less shows better
linearity for this application. Too small
decreases the amplitude of the discriminated FM signal. (Eq.6)
~ Choose a a - 20.
a
Q~~ + (~(VN
(:.1 -
Preliminary Specification
Low Power FM IF System
The internal Rofthe614A is40k. From
Eq. 1c, and then 1b, it results that
Cp + Cs = 174pF and L = 0.7mH.
A more exact analysis including the
source resistance of the previous
stage shows that there is a series and
a parallel resonance in the phase detector tank. To make the parallel and
series resonances close, and to get
maximum attenuation of higher harmonics at 455kHz IF, we have found
that a Cs = 1OpF and Cp =164pF (commercial values of 150pF or 180pF may
be practical), will give the best results.
A variable inductor which can be adjusted around 0.7mH should be chosen and optimized for minimum distortion. (For 10. 7MHz, a value of Cs = 1pF
is recommended.)
AudiO Outputs
Two audio outputs are provided. Both
are PNP current-to-voltage converters
with 55kn nominal internal loads. The
unmuted output is always active to
permit the use of signaling tones in
systems such as cellular radio. The
other output can be muted with 70dB
typical attenuation. The two outputs
have an internal 180" phase difference.
The nominal frequency response of the
audio outputs is 300kHz. This response can be increased with the
addition of external resistors from the
output pins to ground in parallel with
the internal55k resistors, thus lowering
the output time constant. Since the
output structure is a current-to-voltage
converter (current is driven into the
resistance, creating a voltage drop),
adding external parallel resistance
also has the effect of lowering the output audio amplitude and DC level.
This technique of audio bandwidth
expansion can be effective in many
applications such as SCA receivers
and data transceivers. Because the
two outputs have a 1800 phase relationship, FSK demodulation can be
accomplished by applying the two outputs differentially across the inputs of
an op amp or comparator. Once the
threshold of the reference frequency
(or "no-signal" condition) has been
established, the two outputs will shift in
NE/SA614A
opposite directions (higher or lower
output voltage) as the input frequency
shifts. The output of the comparator
will be the logic output. The choice of
op amp or comparator will depend on
the data rate. With high IF frequency
(1 OMHz and above), and wide IF bandwidth (LIC filters) data rates in excess
of 4Mbaud are possible.
RSSI
The "received signal strength indicator", or RSSI, of the NE614A demonstrates monotonic logarithmic output
over a range of 9OdB. The signal
strength output is derived from the
summed stage currents in the limiting
amplifiers. It is essentially independent of the IF frequency. Thus, unfiltered signals at the limiter inputs, spurious products, or regenerated signals
will manifest themselves as RSSI outputs. An RSSI output of greater than
250mV with no signal (or a very small
signal) applied, is an indication of possible regeneration or oscillation.
In order to achieve optimum RSSllinearity, there must be a 12dB insertion
loss between the first and second limiting amplifiers. With a typical 455kHz
ceramic filter, there is a nominal 4dB
insertion loss in the filter. An additional
6dB is lost in the interface between the
filter and the input of the second limiter.
A small amount of additional loss must
be introduced with a typical ceramic
filter. In the test circuit used for cellular
radio applications (Figure 3) the optimum linearity was achieved with a
5.1 kn resistor from the output of the
first limiter (Pin 14) to the input of the
interstage filter. With this resistor from
Pin 14 to the filter, sensitivity of 0.25Jl V
for 12dB SINAD was achieved. With
the 3.6kn resistor, sensitivity was optimized at 0.22JlV for 12dB SINAD with
minor change in the RSSllinearity.
Any application which requires optimized RSSI linearity, such as spectrum analyzers, cellular radio, and
certain types of telemetry, will require
cereful attention to limiter interstage
cumponent selection. This will be
especially true with high IF frequencies
which require insertion loss or impedance reduction for stability.
177
At low frequencies the RSSI mak&s an
excellent logarithmic AC voltmeter.
For data applications the RSSI is effective as an amplitude shift keyed (ASK)
data slicer. If a comparator is applied to
the RSSI and the threshold set slightly
above the no signal level, when an inband signal is received the comparator
will be sliced. Unlike FSK demodulation, the maximum data rate is somewhat limited. An internal capacitor
limits the RSSI frequency response to
about 100kHz. At high data rates the
rise and fall times will not be symmetrical.
The RSSI output is a current-to-voltage
converter similar to the audio outputs.
However, an external resistor is required. With a 91 kn resistor, the output characteristic is 0.5V for a 10dB
change in the input amplitude.
Additional Circuitry
Internal to the NE614A are voltage and
current regulators which have been
temperature compensated to maintain
the performance of the device over a
wide temperature range. These regulators are not accessible to the user.
Preliminary Speclflcatton
Low Power FM IF System
NE/SA614A
"~----------------r-----------------~----------------~----------------'
WO~~~--__=--------r~~--~~~~--~------------------+------------------i
UI~--------~~~~--~--~~~--~~~~~-------------------+------------------~
o~--
...
______________~________________~~________________~________________~
o.m
1.0
Flgur. 10. Ph.s. vs. Normalized IF Frequency
178
1JI25
0>
Ao>
0>1
(a) 1
--= 1 + -
1.CI5
NE645/646
Dolby Noise Reduction Circuit
Product Specification
DESCRIPTION
FEATURES
The NE645/646 is a monolithic audio
noise reduction circuit designed as a
direct replacement device for the
NE645B/NE646B in Dolby* B-Type
noise reduction systems. The NE6451
646 is used to reduce the level of
background noise introduced during recording and playback of audio signals on
magnetic tape, and to improve the noise
level in FM broadcast reception. This
circuit is available only to licensees of
Dolby Laboratories Licensing Corporation, San Francisco, California.
• Accurate record mode frequency
response
• Excellent frequency response
tracking with temperature and
Vee ± 0.4 dB typical
• Excellent back-to-back dynamic
response - DC shift less than
20mV typical
• Improved stability of all op amps
• High reliability packaging
NOTE:
·T.M. Dolby Laboratories Licensing Corporation.
PIN CONFIGURATION
N Package
APPLICATIONS
• Tape decks
• Dolby surround sound system
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
TEMPERATURE RANGE
o to
o to
16-Pin Plastic DIP
16-Pin Plastic DIP
+70°C
NE645N
+70°C
NE646N
BLOCK DIAGRAM
16
INTERNAL
BIAS
SUPPLY
INPUT AMP
November 14, 1986
179
853-0952 86554
Product Specification
NE645/646
Dolby Noise Reduction Circuit
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Vcc
Supply voltage
TA
TSTG
Temperature range
Operating ambient
Storage
TSOLD
Lead soldering temperature
(10sec max)
DC ELECTRICAL CHARACTERISTICS
RATING
UNIT
24
V
o to +70
-65 to +150
°C
°C
+300
°C
Vce = 12V, f = 20Hz to 20kHz. All levels referenced to 580mVRMS (OdB) at
Pin 3, T A = + 25°C, unless otherwise specified.
NE645
SYMBOL
PARAMETER
UNIT
Min
Vee
Supply Voltage Range
Ice
Supply Current
Av
Voltage gain (Pins 5 - 3)
Av
Voltage gain (Pins 3 - 7)
Distortion
THO, 2nd and 3rd
harmonic
Signal handling 1
(Vee = 12V)
SIN
Signal-to-noise ratio 2
Record mode
Frequency response
(at Pin 7) referenced
to encode monitor point
(Pin 3)
Typ
Max
Min
20
8
16
24
24.5
26
27.5
-0.5
0
+0.5
0.05
0.15
0.1
0.3
8
Vee
f
= 12V
= 1kHz (Pins 6 and 2 connected)
f = 1kHz, 0 dB at Pin 3, noise
reduction out
f
f = 20Hz -10 kHz, OdB
= 20Hz - 10kHz, + 10dB
Typ
Max
20
V
16
24
mA
24.5
26
27.5
dB
-0.5
0
+0.5
dB
0.05
0.2
0.2
0.5
%
%
1 % dist at 1kHz
+12
+15
+12
+15
dB
Record mode
Playback mode
67
77
72
82
64
74
72
82
dB
dB
-1
-16.6
-23.5
0
-15.6
-22.5
+1
-14.6
-21.5
-1.5
-17.1
-24.0
0
-15.6
-22.5
+1.5
-14.1
-21.0
dB
dB
dB
-0.7
-17.8
-22.8
-30.2
+0.3
-16.8
-21.8
-29.7
+1.3
-15.8
-20.8
-28.7
-1.2
-18.3
-23.3
-30.2
+0.3
-16.8
-21.8
-29.7
+1.8
-15.3
-20.3
-28.2
dB
dB
dB
dB
-0.3
-18.3
-24.5
+0.7
-17.3
-23.5
+1.7
-16.3
-22.5
-0.8
-18.8
-25.0
+0.7
-17.3
-23.5
+2.2
-15.8
-22.0
dB
dB
dB
Using typical record mode .5
frequency response test points
-1
0
+1
-1.5
0
+1.5
dB
f
= 1.4kHz
OdB
-20dB
-30dB
f
= 5kHz
OdB
-20dB
-30dB
-40dB
f
= 20kHz
OdB
-20dB
-30dB
Back-to-back frequency
response
NE646
TEST CONDITIONS
RIN
Input resistance
Pin 5
Pin 2
35
3.1
50
4.2
65
5.3
35
3.1
50
4.2
65
5.3
kn
kn
ROUT
Output resistance
Pin 6
Pin 3
Pin 7
1.9
2.4
80
80
3.1
120
120
1.9
2.4
80
80
3.1
120
120
kn
n
n
Back-to-back frequency
response shift
vs temperature
vs supply voltage
O°C to +70°C
8-20V
±0.4
±0.4
NOTES:
1. See maximum signal handling versus supply voltage characteristics.
2. All noise levels are measured CCIR/ARM weighted using a 10k source with respect to Dolby level. See Dolby Laboratories Bulletin 19.
November 14, 1986
180
±0.4
±0.4
dB
dB
Product Specification
NE645/646
Dolby Noise Reduction Circuit
TYPICAL PERFORMANCE CHARACTERISTICS
!z
THO vs Frequency Record Mode
THO vs Frequency Record Mode
1.0
1.0
!z
OdBtm:
Vee=12V
0
0
~
0
is
u
I/)
~
IE:
0
~
I/)
U
Z
0
c
.....
~
is
U
0.1
Z
IE:
IE:
l:
.....
C
b
c
~
E 0.01
0.01
100
lK
10K
~
0.01
100
THO vs Frequency
Noise Reduction (NR) Off
1=1 kHz
Vec· 12V
20
l
z
0
0
IE:
II!
Vee = 12V
~
0.1
Z
5
~
II
I/)
Q
is
U
Z
+10 B
~
0
=e
II!
~
,/
II!
~
~
OdB-
c
'\../
C
l:
16
C
~
E 0.01
0.01
-20
-10
+10
/v
7
10
100
+20
V
/v
14
12
.....
c
V
/"
I
0
l:
.....
1 kHz
CD
~
0.1
I
I-- RECORD MODE
~
0
0
1% fHD
18
~
~
10K
Maximum Signal Handling
vs Supply Voltage
1.0
1.0
I/)
lK
FREQUENCY (Hz)
FREQUENCY (Hz)
THO vs Output Record Mode
0
:Ii
100
10K
lK
FREQUENCY (Hz)
!z
.....
C
l:
.....
E
0.1
0
:Ii
C
l:
~
I/)
j.,.
0
:Ii
=e
IE:
is
u
~
r-- r-..r-.
is
0.1
OdB~
Vee -12V
0
~
IE:
IE:
Z
~
z
+10 dBt
Vee- 12V
0
~
THO vs Frequency Play Mode
1.0
lK
10K
FREQUENCY (Hz)
OUTPUT (dB)
8
10
Vee -
12
14
16
18
SUPPLY VOLTAGE (VOLTS)
Supply Current vs
Supply Voltage
20
C
§.
~
ffi
II!
II!
:>
15
u
~
:>
V !--"
~
v
V
I/)
I
~
10
8
10
Vee -
APPLICATION INFORMATION
The NE645/646 is a direct replacement for
the NE645B/646B. The NE645/646 incorpo-
November 14, 1986
12
14
18
18
SUPPLY VOLTAGE (VOLTS)
rates improved design techniques to insure
excellent performance required in Dolby B
and C Type Audio Noise Reduction Systems.
Critical component values are unchanged
181
except for C309 on Pin 1 which is now an
optional component in specific applications
defined by Dolby Laboratories. All circuit
parameters are guaranteed at 12V Vee.
Product Specification
NE645/646
Dolby Noise Reduction. Circuit
DOLBY ENCODER Output for constant level input (single tone frequency response)
Input Level (dB)
Frequency
(kHz)
0
-15
-20
-25
(Dolby
Level)
-5
0.1
0
0.1
0
0.1
0
0
0
0
0
0.14
0
0.2
0.2
0.2
0.2
0.2
0.1
0.2
0.1
0.5
-10
-30
-35
-40
0.2
0
0.3
0.4
0.5
0.5
0.6
0.6
0.5
0.3
0
0.3
0.6
1.1
1.3
1.3
1.3
1.3
1.3
2.0
2.1
2.2
2.3
2.1
2.9
2.9
3.0
2.9
3.6
3.7
3.8
3.7
0.4
0.5
0
0.3
0.8
1.8
2.6
0.6
0.7
0
0.4
0.9
2.1
3.5
0.8
4.3
4.4
4.5
4.4
4.8
5.0
5.3
5.1
5.6
5.8
5.6
6.1
6.3
6.2
0.9
1.0
0
0.4
1.0
2.3
4.2
5.7
0
0.3
0.9
2.3
4.4
6.6
2.0
0.1
0.4
0.9
2.2
4.3
3.0
0.2
0.6
0.9
1.9
3.9
5.0
0.3
0.6
1.0
1.7
3.2
5.4
1.2
1.4
6.9
7.1
7.1
7.5
7.7
7.7
7.0
8.5
8.9
8.9
6.6
8.8
9.7
9.7
8.2
10.0
10.3
7.0
0.3
0.6
1.0
1.7
2.8
4.7
7.3
9.7
10.4
10.0
0.4
0.7
1.1
1.7
2.6
4.2
6.5
9.1
10.4
14.0
0.5
0.8
1.1
1.8
2.7
4.4
6.5
8.7
10.3
20.0
0.7
0.7
1.2
1.9
2.7
4.4
6.5
8.7
10.3
NOTE:
The figures given in this table are the average response of many of Dolby Laboratories' professional encoders, and are not intended to be taken as required
consumer equipment performance characteristics. Thus, no inference should be drawn on the tolerances which licensees must retain in consumer equipment. The
figures can, however, be used to plot typical characteristics.
November 14, 1986
182
Product Specification
NE645/646
Dolby Noise Reduction Circuit
TEST CIRCUIT
C206
10.F
15VDC
~----~----~:~~
R309
1K
10
I
C208
470pF
R306
190
C304
rO.047• F
5%
C301
C302
~F 0.02~~I
R301
3.3K
1%
NOTE:
All resistors standard and are measured in fl. 'Optional capacitor in specific applications defined by Dolby Laboratories.
November 14, 1986
183
14 R304
270K
C306
J.0.1.F
R305
180K
15
-I
C307
0 33 F
. •
NE649
Signetics
Low Voltage Dolby Noise
Reduction Circuit
Product Specification
Linear Products
DESCRIPTION
The NE649 is an audio noise reduction
circuit designed for use in low voltage
entertainment systems. The circuit is
used to reduce the level of background
noise introduced during the recording
and playback of audio signals on magnetic tape and improve the noise
Dolby is a trademark of Dolby Laboratories Licensing Corporation
level in FM broadcast reception. The
circuit is intended for use in automotive
and portable cassette DolbyTM B-Type
noise reduction systems. This circuit is
available only to licensees of Dolby Laboratories Licensing Corp., San Francisco.
PIN CONFIGURATION
N Package
FEATURE
• Low voltage operation
APPLICATION
• Tape decks
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
16-Pin Plastic DIP
NE649N
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
16
V
Operating temperature range
-40 to +85
°C
TSTG
Storage temperature range
-65 to + 150
°C
TSOLD
Lead soldering temperature 10sec max
+300
°C
Vcc
Supply voltage
TA
BLOCK DIAGRAM
16
INPUT AMP
October 7, 1987
185
853-1193 90826
Product Specification
Low Voltage Dolby· Noise Reduction Circuit
NE649
DC ELECTRICAL CHARACTERISTICS Vee = 9V, f = 20Hz to 20kHz. All levels referenced to 580mVRMS (OdB) at Pin 3,
TA = + 25°C, unless otherwise specified.
NE649
SYMBOL
Vcc
PARAMETER
TEST CONDITIONS
Supply voltage range 3
Minimum voltage supply for
8dB headroom
10dB headroom
Icc
Supply Current
Icc
Supply Current 1
f = 1.4kHz
THO < 1%
Typ
Max
6
9
14
Av
Voltage gain (Pins 5 - 3)
Av
Voltage gain (Pins 3 - 7)
f = 1kHz, OdB at Pin 3,
noise reduction out
V
V
V
6.5
7.5
11
f = 1kHz
(Pins 6 and 2 connected)
Distortion
UNIT
Min
18
mA
20
mA
24.5
26
27.5
dB
-0.5
0
+0.5
dB
0.05
0.2
0.2
0.5
%
%
f = 20kHz to 10kHz, OdB
f = 20Hz to 10kHz, + 10dB
Signal Handling
(See Performance Characteristics)
SIN
Signal-to-noise rati0 2
Record
(Pins 6 and 2 connected)
Playback
(Pins 6 and 2 connected)
Record mode frequency
response (at Pin 7) referenced to
encode
monitor pOint (Pin 3)
Back-to-back frequency response
64
72
dB
74
82
dB
!f = 1.4kHz
OdB
-20dB
-30dB
-1.5
-17.1
-24.0
0
-15.6
-22.5
+1.5
-14.1
-21.0
dB
dB
dB
f = 5kHz
OdB
-20dB
-30dB
-40dB
-1.2
-18.3
-23.3
-30.2
+0.3
-16.8
-21.8
-29.7
+1.8
-15.3
-20.3
-28.2
dB
dB
dB
dB
f = 20kHz
OdB
-20dB
-30dB
-0.8
-18.8
-25.0
+0.7
-17.3
-23.5
+2.2
-15.8
-22.0
dB
dB
dB
± 1.5
Using typical record mode response
RIN
Input resistance
Pin 5
Pin 2
ROUT
Output resistance
Pin 6
Pin 3
Pin 7
db
35
3.1
50
4.2
65
5.3
kn
kn
1.9
2.4
80
80
3.1
120
120
kn
n
n
Record mode frequency response shift
o to 70°C
-40 to 85°C
6 to 14V
vs temperature
vs vcc
NOTES:
1. With electronic switching.
2. All noise levels are measured CCIR/ARM weighted using a 10k source with respect to Dolby level. See Dolby Laboratories Bulletin 19.
3. The circuit will function as low as Vcc = 4.5V (i.e., output signal present). See graphs of Icc and signal handling vs Vcc.
October 7, 1987
186
dB
dB
dBN
Product Specification
low Voltage Dolby Noise Reduction Circuit
NE649
TYPICAL PERFORMANCE CHARACTERISTICS
(+ 10dB) THO vs Frequency
(OdB) THO vs Frequency
1.0
1.0
~
~
9V
00. 1
00.1
~
~
14V
- ~
......-: :v
6V
9V
0.0 1
100
lK
lK
FREQUENCY (Hz)
Current vs Supply Voltage
Maximum Signal Handling
vs Supply Voltage for
1%THO (Record)
!
17
JJ
J I
15
I
:>
I
ffi
! J...... ~I
~
1
~
jI
"'J
~
.... "'!: P"
~-:160·lc
I I
1
1
I
!
!
;g
~
, !
i
~
....
::;)
I
10 12
Vee (V)
~
1
0-1 I
i
I!
I
14
/'
/
9
iii
E. 7
w
I
I I
I I
13
~ 11
+25·C
10K
:.-
.,
15
E
',-40·C .1
13
October 7, 1987
14V
0.01
100
10K
FREQUENCY (Hz)
16
-3
18
6
8
10
12
SUPPLY VOLTAGE (V)
187
14
16
Product Specification
Low Voltage Dolby Noise Reduction Circuit
NE649
DOLBY ENCODER Output for constant level input (single tone frequency response)
INPUT LEVEL (dB)
0
(DOLBY
LEVEL)
-5
0.1
0
0.1
0
0.1
0
0
0
0
0
0.14
0
0.2
0.2
0.2
0.2
0.2
0.1
0.2
0.1
0.5
FREQUENCY
(kHz)
-10
-15
-20
-25
-30
-35
-40
0.2
0
0.3
0.4
0.5
0.5
0.6
0.6
0.5
0.3
0
0.3
0.6
1.1
1.3
1.3
1.3
1.3
1.3
2.0
2.1
2.2
2.3
2.1
0.4
0.5
0
0.3
0.8
1.8
2.6
0.6
0.7
0
0.4
0.9
2.1
3.5
0.8
2.9
2.9
3.0
2.9
3.6
3.7
3.8
3.7
4.3
4.4
4.5
4.4
4.8
5.0
5.3
5.1
5.6
5.8
5.6
6.3
6.2
0.9
1.0
0
0.4
1.0
2.3
4.2
5.7
6.1
6.9
7.1
7.1
0
0.3
0.9
2.3
4.4
6.6
7.5
7.7
7.7
8.9
1.2
1.4
2.0
0.1
0.4
0.9
2.2
4.3
7.0
8.5
8.9
3.0
0.2
0.6
0.9
1.9
3.9
6.6
8.8
9.7
9.7
5.0
0.3
0.6
1.0
1.7
3.2
5.4
8.2
10.0
10.3
7.0
0.3
0.6
1.0
1.7
2.8
4.7
7.3
9.7
10.4
10.0
0.4
0.7
1.1
1.7
2.6
4.2
6.5
9.1
10.4
14.0
0.5
0.8
1.1
1.8
2.7
4.4
6.5
8.7
10.3
20.0
0.7
0.7
1.2
1.9
2.7
4.4
6.5
8.7
10.3
NOTE:
The figures given in this table are the average response of many of Dolby Laboratories' professional encoders, and are not intended to be taken as required
consumer equipment performance characteristics. Thus, no inference should be drawn on the tolerance which licensees must retain in consumer equipment. The
figures can, however, be used to plot typical characteristics.
987
188
Product Specification
Low Voltage Dolby Noise Reduction Circuit
NE649
TEST CIRCUIT
C206
10.F
15VDC
~----~----~:~~
"R309
lK
C202
+
l~~~~I
INPUT AMP
I
C208
470pF
10
R305
180K
R308
C304
0047
5% ."
180
1°
C301
C302
~F 0002~~~I
October 7, 1987
13
189
R301
303K
1%
14 R304
270K
C306
001 F
•
1
15
C307
1°033.F
NE650
Dolby B-Type Noise Reduction
Circuit
Product Specification
DESCRIPTION
The NE650 is a monolithic audio noise
reduction circuit designed for use in
Dolby™B-Type noise reduction systems. The NE650 is used to reduce the
level of background noise introduced
during recording and playback of audio
signals on magnetic tape.
The NE650 features excellent dynamic
characteristics over a wide range of
operating conditions and is pin-compatible with NE645/646. This circuit is available only to licensees of Dolby Laboratories Licensing Corp., San Francisco.
PIN CONFIGURATION
I
N Package
Dolby is a trademark of Dolby Laboratories Licensing Corporation.
ORDERING INFORMATION
I
i-DESCRIPTION
~Plastic
ORDER CODE
TEMPERATURE RANGE
o to
DiP
NE650N
+70°C
ABSOLUTE MAXIMUM RATINGS
'---.
SYMBOL
PARAMETER
Vce
Supply voltage
TA
TSTG
Temperature range
Operating ambient
Storage
TSOLD
Lead soldering temperature (10 sec. max)
I
RA;:NG~. r":'T
o to + 70
-65 to + 150
°C
°C
+300
°C
I
--
BLOCK DIAGRAM
16
November 14, 1986
191
853-0953 86554
Product Specification
NE650
Dolby B-Type Noise Reduction Circuit
DC ELECTRICAL CHARACTERISTICS Vee = 12V, f = 20Hz to 20kHz. All levels referenced to 580mV RMS (Odb) at Pin 3,
TA = + 25°e, unless otherwise noted.
NE650
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Vee
Supply voltage range
lee
Supply current
Typ
8
Electronic switching on
16
Max
20
V
24
mA
Av
Voltage gain (Pins 5 - 3)
f = 1kHz (Pins 6 and 2 connected)
25.5
26
26.5
dB
Av
Voltage gain (Pins 3 - 7)
f = kHz, OdB at Pin 3, noise reduction out
-0.5
0
+0.5
dB
Av
Voltage gain (Pins 2 - 3)
f = 1kHz
13
f=20Hz to 10kHz, OdB
f=20Hz to 10kHz, + 10dB
0.05
0.15
Distortion
THO: 2nd and 3rd harmonic
Signal handling
SIN
Signal-to-noise ratio'
Back-to-back frequency response
Record mode frequency response
(at Pin 7) referenced to encode
monitor point (Pin 3)
dB
0.1
0.3
%
%
1% distortion at 1kHz
+12
+15
dB
Record mode
Playback mode
68
78
72
82
dB
dB
±0.5
dB
Using typical record mode response
f = 1.4kHz
OdB
-20dB
-30dB
-0.5
-16.1
-23.5
0
-15.6
-22.5
+0.5
-15.1
-21.5
dB
dB
dB
f = 5kHz
OdB
-20dB
-30dB
-40dB
-0.7
-17.3
-22.3
-30.2
+0.3
-16.8
-21.8
-29.7
+1.3
-16.3
-21.3
-29.2
dB
dB
dB
dB
f = 20kHz
OdB
-20dB
-30dB
-0.3
-18.3
-24.5
+0.7
-17.3
-23.5
+1.7
-16.3
-22.5
dB
dB
dB
I
RIN
Input resistance
Pin 5
Pin 2
35
3.1
50
4.2
65
5.3
kn
kn
2.4
80
80
3.1
120
120
kn
Output resistance
Pin 6
Pin 3
Pin 7
1.9
ROUT
Back-to-back frequency response
shift
vs TA
vs Vee
ooe to -70 oe
8 to 20V
±0.4
±0.4
NOTE:
• All noise levels are measured CCIRt ARM weighted using a 10k source with respect to Dolby level. See Dolby Laboratories Bulletin 19.
November 14, 1986
192
n
n
dB
dB
Product Specification
Dolby B-Type Noise Reduction Circuit
NE650
PERFORMANCE CHARACTERISTICS
THO vs Frequency Record Mode
!z
THO vs Frequency Record Mode
!z
OdBt:±tt
Vee=12V
0
j::
a:
I-
III
2i
U
-
0
t;
2i
0.1
U
i
0
:I
0.1
~
0
I-
!!!
r--. ....
c
io'"
0
::E
a:
c
:z:
a:
C
:z:
.....
.....
.....
c
c
~ 0.01
e
!5
I-
100
0.01
(\.01
100
10K
lK
0.1
U
i
0
:I
a:
c
:z:
o dBt::f!:t
Vee = 12V
0
j::
0
1.0
!z
+10dBJ;
Vee- 12V
0
a:
i
THO vs Frequency Play Mode
1.0
1.0
10K
lK
100
1.0
Maximum Signal Handling vs
Supply Voltage
20
1.0
t.l kHz
Vee· 12V
!z
Vee=12
0
0
j:::
j:::
>:
a:
a:
e
2i
u 0.1
i
0
!!!
c
u
i
c
+10 B
a:
c
:z:
g
16
I-
~
14
;=)
0
12
j!
0
I-
t- 0.01
-20
-10
+10
0.01
+20
/V
l-
OdEl-
/
/V
:s
0.1
a:
C
:z:
.....
...... ~
.....
V
/'
III
0
:I
0
:I
1% +HD
\
RECORD MODE
18 -1kHz
~
0
I-
/
III
10K
FREQUENCY (Hz)
THD vs Frequency
Noise Reduction (NR) Off
THD vs Output Record Mode
!z
lK
FREQUENCY (Hz)
FREQUENCY (Hz)
/
10
100
10K
lK
OUTPUT (dB)
FREQUENCY (HZ)
8
10
12
14
16
18
Vee - SUPPLY VOLTAGE (VOLTS)
OP10120S
Supply Current vs
Supply Voltage
20
i
I-
Z
1&.1
~
;=)
15
u
~
~
IlL
IlL
V
-
v
V
51
~
10
10
12
14
18
vee - SUPPLY VOLTAGE (VOLTS)
November 14, 1986
193
18
Product Specification
Dolby B-Type Noise Reduction Circuit
NE650
DOLBY ENCODER Output for constant level input (single tone frequency response)
Input Level (dB)
Frequency
(kHz)
0
(Dolby
Level)
-5
-10
-15
-20
-25
-30
-35
-40
0.1
0
0.1
0
0.1
0
0
0
0
0
0.14
0
0.2
0.2
0.2
0.2
0.2
0.1
0.2
0.1
0.2
0
0.3
0.4
0.5
0.5
0.6
0.6
0.5
0.5
0.3
0
0.3
0.6
1.1
1.3
1.3
1.3
1.3
1.3
2.0
2.1
2.2
2.3
2.1
0.4
0.5
0
0.3
0.8
1.8
2.6
0.6
0.7
0
0.4
0.9
2.1
3.5
0.8
2.9
2.9
3.0
2.9
3.6
3.7
3.8
3.7
4.3
4.4
4.5
4.4
4.8
5.0
5.3
5.1
5.6
5.8
5.6
6.1
6.3
6.2
6.9
7.1
7.1
0.9
1.0
0
0.4
1.0
2.3
4.2
5.7
1.2
1.4
0
0.3
0.9
2.3
4.4
6.6
7.5
7.7
7.7
2.0
0.1
0.4
0.9
2.2
4.3
7.0
8.5
8.9
8.9
3.0
0.2
0.6
0.9
1.9
3.9
6.6
8.8
9.7
9.7
5.0
0.3
0.6
1.0
1.7
3.2
5.4
8.2
10.0
10.3
7.0
0.3
0.6
1.0
1.7
2.8
4.7
7.3
9.7
10.4
10.0
0.4
0.7
1.1
1.7
2.6
4.2
6.5
9.1
10.4
14.0
0.5
0.8
1.1
1.8
2.7
4.4
6.5
8.7
10.3
20.0
0.7
0.7
1.2
1.9
2.7
4.4
6.5
8.7
10.3
NOTE:
The figures given in this table are the average response of many of Dolby Laboratories' professional encoders, and are not intended to be taken as required
consumer equipment performance characteristics. Thus, no inference should be drawn on the tolerance which licensees must retain in consumer equipment. The
figures can, however, be used to plot typical characteristics.
November 14, 1986
194
Product Specification
Dolby B-Type Noise Reduction Circuit
NE650
TEST CIRCUIT
C206
10.F
ISVDC
~----~----~: ~
INTEFlNAl
BIAS
SUPPLY
RlO9
lK
INPUT AMP
C201
...
Isv~T
B
C208
1470PF
RlO6
180
I---+~
ClOl
ClO2
~:F
O.02;{I
NOTES:
Ail resisters standard and are measured in i1.
·Optional capacitor in specific applications defined by Dolby Laboratories.
November 14, 1986
195
RlOl
3.3K
1%
RlO5
180K
DEVELOPMENT DATA
This data sheet contains advance information and
specifications ara subject to change without notice.
l___
O_M_8_2_00_ __
LOW COST SPEECH DEMONSTRATION BOARD
GENERAL DESCRIPTION
The low cost speech demonstration board is designed to add voice output to existing card based
electronic equipment with the minimum of additional effort and components. The majority of
components used are of the CMOS type with low power consumption making the board suitable
for battery operation.
Applications include speech evaluation and speech demonstration.
FEATURES
• PCF8200 speech synthesizer
- Male and female speech of very high quality
- CMOS technology
- Extended operating temperature range
- Programmable speaking speed
• Low current consumption
- All major components use CMOS technology
(PCF8200, 80C39 and 27C64)
• Very large vocabulary up to 12 minutes
- 4 EP ROM sockets
- EPROM selection for 27C16 to 27C256
- Low data rates for synthesizer (average 1500 bits per second)
• Easy interfacing
- 8-bit parallel data bus/key switch input
- Volume control, speaker connection
- Control signals (e.g. RESET, BUSY etc etc)
• Simple operating modes
- ROM selection
- Word sequence within a ROM
- Repeat last utterence
- Control software is readily customizeable
- To implement parameter download from external source
• Single Eurocard size PC board
• Single + 5 V supply
• Low cost
APPLICA TIONS
• OEM design-in
• May be simply used with many card systems for speech evaluation
• Speech demonstration
- Particularly simple when used with the OM8201 (Speech Demonstration Box)
1(MarCh
1985
197
...A
co
co
VCC
o
r;;o~--'
Vss
s:
Ci
~
co
OJ
CJ1
ADDRESS
vcc
./
EA
[
RESET
--c::J-
It
f
j
II
II
VCC
+5PJ
ADDRESS
,+
I
':Z cb
T
MULTIPLEXER
~
I
PSEN
/
OCTAL
LATCH
r-r-
t
/
/
L
D-
,~
TO
BUSY
T1
~ J
.L
EPROM
3
/
CE
CE
{
{
/
/
"
V
-t
V
DUAL
DECODER
~
,
OCTAL
D-FF
-
L
SPEECH
SYNTHESIZER
PCF8200
r
/
It'
r--
AUDIO ~---+ SPEE CH
FILTER
OUT
I
6MHz
POWER
AMPLIFIER
LS
AUDIO
' - CONNECTOR
WR
7Z80626
WAIT
DS
Fig" 1 Block diagram.
DB7-DBO
I\)
o
/
CE
1
+SV
INT
/
~
ex>
o
L
EPROM
2
/
~
MICROPROCESSOR
80C39
/
EPROM
1
CE
DATA
AD
/
/
0
ALE
SS
L
EPROM
XTAL 1
XTAL2
1
1
L- _ _ _ - I
Q)
c
Low cost speech demonstration board
l__
O_M_8_2_0_0_ __
OPERATION
HARDWARE DESCRIPTION
The main controlling microprocessor is an 80C39 running at 6 MHz. This device supplies all of the
main controlling signals for the board operation and the interfacing to any external system.
Four sockets are provided for EPROMS which contain speech coding. These may be 27C16 types,
through to 27C256 types; the sockets will be a low insertion force type to allow for easy customizing.
The board will be supplied with one socket occupied by a 27C64 which will contain the control
program and some speech examples. All four EPROM sockets must contain the same EPROM type.
The speech synthesizer PCF8200 converts the coding into a speech output. This synthesizer has been
designed to simulate the human vocal tract using five formants for male and four formants for female
speech. Periodic updating of the parameters for these formants can produce very high quality speech.
The output of the synthesizer can be fed into an audio amplifier, TOA7050, via a resistor-capacitor filter
network which provides a frequency cut-off above 5 kHz of about 25 dB. The configuration of the
audio amplifier used on this board gives an output of 140 mW peak power into a 25
speaker from
a 5 V supply.
.n
e::(
le::(
C
I2
w
:iE
Connections are made to the board via a standard 01 Nil EC connector. This allows access to the
8-bit parallel data bus so that speech coding from an external source may be used, if implemented,
and allows the selection of speech phrases by an external system, such as a microcomputer or even a
bank of switches. The same connector also permits the addition of a volume control, loudspeaker, a
high impedance audio output, and power supply. The control signals RESET, BUSY, WAIT and OS
are also taken to the outside of the board. There is also a loudspeaker plug on the board.
All components are contained on a standard single Eurocard, and therefore suitable for rack mounted
equipment.
Q..
SOFTWARE DESCRIPTION
W
All the software required to operate the board is contained in the only EPROM supplied. The software
is written in modular from so that it is possible for a customer to alter or add to any particular function
which suits his applications. An industrial standard microprocessor was chosen so that readily available
development systems could be used to facilitate this modification.
o...J
>
W
C
There are four main modes of operation:
-
ROM Selection
Word Sequence
Repeat Word
Speaking Speed Selection
These modes are all controlled by software.
ROM Selection mode permits access to an individual EPROM and pronounces the first utterence
from that EPROM.
Word Sequence gives the next word (activated by repeated access to the same EPROM) and if continually
exercised will keep looping on the words in that EPROM.
The Repeat Word command allows indefinate repetition of the last utterance pronounced.
The Speaking Speed Selection allows the utterence to be pronounced at a different speed.
The soft~are also controls the address sequencing within the utterance and ensures that the required
data is supplied to the synthesizer.
1
(MarCh 1985
199
Jl___~_
_OM_8200
There are also some examples of words/utterences encoded in the remainder of the supplied EPROM.
These words are intended for demonstration purposes and will show the features 'of the synthesizer
when selected. The main features being illustrated are:
- Male speech in several languages
- Female speech in several languages
- Programmable speaking speed
ORDERING INFORMATION
Product name:
Low Cost Speech Demonstration Board
Type number:
OM8200
Ordering code:
9337 541 30000
Orders should be placed with your local Philips/Signetics agency.
200
March
19851 (
t__
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
O_M_B_2_0_1- - -
SPEECH DEMONSTRATION BOX
GENERAL DESCRIPTION
Speech demonstration box OM8201 is designed to be used in conjunction with the low cost speech
demonstration board OM8200. The box contains all the necessary components to drive the board.
The combination of these two components make an extremely attractive demonstration unit.
FEATURES
• Low cost
• Can use unmodified OM8200 board which allows access to all features of the OM8200
• Single + 9 V supply
- Low power consumption therefore permits battery operation
- External power supplies may also be used
- Voltage is regulated and dropped to a standard + 5 V for the OM8200 board
• Simple mechanical construction
- Allows easy access to the OM8200 for changing EPROMS
• Contains all peripherals needed to drive the OM8200
HARDWARE DESCRIPTION
The box contains a set of eight keypad switches which are connected to the data bus. Four switches
can select which EPROM your speech data is derived from. Repeated pressing of an EPROM switch
increments the expression number which will be uttered. To repeat the last expression, a separate
switch must be activated.
It is possible in the PCF8200 to change the rate of speaking to 73%, 123% or 145% of the normal
speed. A switch has been included on the box which will sequence through the speed options making
the same utterance every time.
One of the two remaining switches is the master reset for the program and the other is for future
enhancements of the box.
Included in the box are, the volume control for the amplifier, the loudspeaker, and a high impedance
audio output.
The final piece of electronics is the power supply. This can be supplied from a + 9 V internal battery
or from a + 9 V external supply. The + 9 V is regulated to a + 5 V supply which is then fed to other
parts of the box and to the OM8200.
The box is of simple construction and allows easy access to the OM8200 for changing of EPROMS.
SOFTWARE DESCRIPTION
There is no software in the OM8201. The software of the OM8200 may be used in an unmodified
form without any problems. However, if changes have been made to the control program of the
OM8200 then different functions for the switches of the box can be achieved.
'1
(March 1985
201
Jl_~~
_OM_8201
+
1-+_5,....V---t_-+-_ +5 V
out
9V
+
BATIERY
+vext==-r
0,1/-tF
" - " - - - - - -..........---~--+-~
~
+5V
~VOLUME
~""'----------CONTROL
~
+5V
100kO
EPROM 0
EPROM 1
DO
~LS+
01
~LS-
02
EPROM 2
03
EPROM 3
04
REPEAT
05
CHANGE
SPEED
06
07
RESET
PROGRAM
audio-out
OS
7Z80627
Fig. 1 Schematic diagram.
ORDERING INFORMATION
Product name:
Speech Demonstration Box
Type number:
OM8201
Ordering code:
9337 541 40000
N.B. OM8200 must be ordered as well if this box is to be used in demonstration mode.
The order number for the OM8200 is 9337 541 30000.
Orders should be placed with your local Philips/Signetics agent.
202
March
19851 (
DEVELOPMENT DATA
Hlis data sheet contains advance inforrnation and
specifications are subject to change withouT notice.
l____
O_M_8_2_0_9______
UPDATE PACKAGE FOR EXISTING OM8010
SPEECH EDITING SYSTEM
GENERAL DESCRIPTION
This package, OM8209, is an updating package which allows the users of our already existing editing
system for the MEA8000 also to generate the parameters and codes necessary for our new CMOS voice
synthesizer, PCF8200.
FEATURES
• Hardware updates for the synthesizer board to permit output via the PCF8200 and the M EA8000
• Software update to generate parameters and codes for the PCF8200
• Gives all the features of the OM8210 to those who have the OM8010 (used for generating first
generation synthesizer codes)
Hardware
The only hardware changes are to the synthesizer card. This card is completely replaced by a new
synthesizer card. This card cor.tains the new PCF8200 voice synthesizer, the MEA8000 voice synthesizer
and the necessary components required to interface the synthesizers to their environment.
Software
The software package is exactly the same as in the OM8210, for fuller information consult the data
for that device.
ORDERING INFORMATION
Product name:
Update package for existing OM8010 Speech Editing System using the HP9816S
Type number:
OM8209
Ordering number:
9337 564 50000
Orders should be placed with your local Philips/Signetics agent.
1
(MarCh 1985
203
l___
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
O_M_8_2_10_ _ __
SPEECH ANAL YSIS/EDITING SYSTEM
GENERAL DESCRIPTION
The OM821 0 is a speech analysing/editing system, and comprises of a speech adapter box and associated
software. The system uses either the HP9816S or IBM-PC personal computer.
The OM821 0 and the computer function together to produce speech coding for the PCF8200.
The system has many commands available, mostly single key operations, which gives it flexability.
FEATURES
•
•
•
•
•
•
•
•
Input sampling of analogue speech signals
Speech analysis
Graphic parameter representation
Parameter editing screen
Conversion of parameters to PCF8200 synthesizer
EPROM programming
Parameter storage on floppy disc
Speech output via PCF8200 voice synthesizer
ANALOGUE CARD
QD
~-4----4~ ~------_ (+
.....
ADC
t
level
ANALOGUE
MUX
'
+-
~AC
8
+-
CONTROL
CARD
t
IEC625/
IEEE488
SYNTHESIZER
CARD
28-pin
socket
D
8
PERSONAL
COMPUTER
1+--_~2J_--+.1 PRO~=~~MER 1...~_ _ _ _ _8('--_ _ _ _+1
7
CARD
7
+-SPEECH ADAPTER BOX
OM8210
7Z87995
Fig. 1 Block diagram.
1(MarCh
1986
205
Jl__~_
_OM_8210
HARDWARE DESCRIPTION
The hardware for the OM8210 is contained in an attractive box with access to all the interconnections
(IEC 625, interface loudspeaker, headphones, tape input, and EPROM socket), from the front panel.
There are four single Eurocards and a power supply forming the speech adapter box.
These cards are:
-
Analogue Card
Synthesizer Card
EPROM Card
Control Card
Analogue Card
On this card, the level of the recorded audio input signal is adjusted by an electronic potentiometer.
Before the audio is sampled, frequencies higher than half the sampling frequency are removed by a
switched capacitor filter of the type normally used for codecs. A 12-bit analogue-to-digital converter
(ADC) produces the digital samples that are sent to the control card. An 8-bit digital-to-analogue
converter (DAC) on the analogue card allows the sampled speech to be output. The audio input signal,
the sampled speech and the synthesized speech are selected by an analogue multiplexer, filtered,
and adjusted for volume before reproduction by a loudspeaker.
The use of integrated electronic potentiometers and codec filters substantially reduces the number
of components required while maintaining high performance.
Synthesizer Card
This card accommodates the PCF8200 voice synthesizer and a small amount of peripheral components
and a socket for the M EA8000 voice synthesizer.
EPROM Programmer Card
This card allows four different types of EPROM (2716,2732, 2732A and 2764) to be programmed
under software control. All the hardware to generate the programming voltages and the programming
waveforms are on this card.
Control Card
This card performs three functions:
- IEC625/IEEE 488 interface
- Control sequencer
- Clock generator
The IEC/IEEE interface is a simple talker/listener implementation with a HEF4738 circuit.
An FPLA control sequencer provides the handshake signals for IEC/I EEE interface and the chip
enable signals for the rest of the system (the ADC, the DAC, the synthesizer and control circuits).
The filter sampling frequency is generated with a software programmable PLL frequency synthesizer.
The speech sampling frequency is derived from the filter sampling frequency by frequency division.
Hence, the filter frequency cut-off and the sample rate of the ADC and the DAC are automatically
linked.
The hardware includes all the necessary cables, adapter plug, loudspeaker, headphone and power supply.
206
March
19851 (
l____
Speech analysis/editing system
O_M_8_2_10______-
SOFTWARE DESCRIPTION
The software for this speech coding system has been developed and arranged for optimum user
convenience. There are eight modes available.
Each mode and each command in the mode is selected by single key entries. Commands that can
destroy data have to be confirmed before they are executed. More than 100 commands are available.
The modes are:
Sample Mode
Samples and digitizes the recorded speech, the amplitude can be checked and
speech segments selected. The sampled speech is stored in a memory and can
be displayed or made audible.
Analysis Mode
Generates speech parameters from samples. The analysis selects the voiced/
unvoiced sections, extracts the formants (5 for male and 4 for female),
amplitude, and the pitch, and quantisizes the speech parameters.
Parameter
Edit Mode
Speech parameters are displayed graphically on the VDU and can be edited to
correct errors in the analysis, improve speech quality by altering contours,
or amplitudes, concatenate sounds and optimize data rate by editing the frame
duration.
Code Mode
Generates PCF8200 code and permits the arrangement of utterences in the
optimum order of application. This mode also generates the address map at the
head of the EPROM.
EPROM Mode
Used to program/read EPROMS with data for the code memory also possible is
a new check, bit check and verification commands.
File Mode
Stores speech parameters or codes on disc, can also assemble code speech segment
from an already existing library.
Media Mode
For diskette initialization and making back-up copies.
Option Mode
Allows the system configuration to be read or changed.
The software is supplied on two diskettes, one labelled 'BOOT' which wakes up the system and also
contains the system library routines. The other diskette labelled 'SPEECH' contains the speech program, the disc initialization and the file handler programs. The 'BOOT' disc is not required during
operation, giving a free disc drive with the system for a diskette to store speech parameter files.
Computer System
The following equipment is required to make a complete Hewlett Packard based editing system:
- HP9816S-630 (optimum computer type) or HP9817
- HP9121 D (dual floppy disc)
- Additional memory card for the HP9816S (512 K bytes total required)
The following equipment is required to make a complete IBM based editing system:
- I BM-PC or PC-XT or Philips P31 00
- Additional memory (512 K recommended)
- Display graphics card (Hercules monochrome)
- I EEE488 card (Tecmar Rev. D.)
ORDERING INFORMATION
Product name:
Speech Analysis/Editing System
Type number:
OM8210
Ordering code:
9337 561 50112
The computer system should be purchased from your local agents.
The OM821 0 should be ordered through your local Philips/Signetics agent.
'I
(MarCh 1986
207
DEVELOPMENT DATA
PC880C518H-3
PC880C31BH-3
This data sheet contains advance information and
specifications are subject to change without notice.
FOR DETAILED INFORMATION SEE RELEVANT DATA BOOK OR DATA SHEET
SINGLE-CHIP 8-BIT MICROCONTROLLER
DESCRIPTION
The PCB80C51 family of single-chip 8-bit microcontrollers is manufactured in an advanced CMOS
process. The family consists of the following members:
• PCB80C51 BH-3; 4 K bytes mask-programmable ROM, 128 bytes RAM
• PCB80C31 BH-3: ROM-less version of the PCB80C51 BH-3
I n the following text, the generic term "PCB80C51 BH-3" is used to refer to both family members.
The device provides hardware features, architectural enhancements and new instructions to function
as a controller for applications requiring up to 64 K bytes of program memory and/or up to 64 K
bytes of data memory.
The PCB80C51 BH-3 contains a non-volatile 4 K x 8 read-only program memory; a volatile
128 x 8 read/write data memory; 32 I/O lines; two 16-bit timer/event counters; a five-source,
two-priority level, nested interrupt structure; a serial I/O port for either multi-processor communications,
I/O expansion, or full duplex UART; and on-chip oscillator and timing circuits. For systems that
require extra capability, the PCB80C51 BH-3 can be expanded using standard TTL compatible memories
and logic.
The PCB80C51 BH-3 has two software selectable modes of reduced activity for further power reduction Idle and Power-down.
The Idle mode freezes the CPU while allowing the RAM, timers, serial port and interrupt system to
continue functioning.
The Power-down mode saves the RAM contents but freezes the oscillator causing all other chip
functions to be inoperative.
The device also functions as an arithmetic processor having facilities for both binary and BCD
arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions:
49 one-byte, 46 two-byte and 16 three-byte. With a 12 M Hz crystal, 58% of the instructions are
executed in 1 /ls and 40% in 2/ls. Multiply and divide instructions require 4/ls. Multiply, divide,
subtract and compare are among the many instructions .included in the instruction set.
Features
•
•
•
•
•
•
•
•
•
•
4 K x 8 ROM (80C51 BH-3 only), 128 x 8 RAM
Four 8-bit ports, 32 I/O lines
Two 16-bit timer/event counters
Full-duplex serial port
External memory expandable to 128 K, external
ROM up to 64 K and/or external RAM up to 64 K
Boolean processing
218 bit-addressable locations
On-chip oscillator
Five-source interrupt structure with two priority
levels
With a 12 MHz clock, 58% of the instructions
execute in 1 /ls; multiply and divide instructions
execute in 4 /lS; all other instructions execute in
2/ls
• Enhanced architecture with:
non-page-oriented-instructions
direct addressing
four 8-byte + 1-byte register blanks
stack depth up to 128-bytes
multiply, divide, subtract and compare
instructions
• PCB80C51/C31 BH-3
XTAL frequency range: 1,2 to 16 MHz
temperature range: 0 °C to + 70 °C
PCF80C51/C31BH-3
XTAL frequency range: 1,2 to 12 MHz
temperature range: -40 0C to + 85 0C
PCA80C51/C31 B H-3
XTAL frequency range: 1,2 to 12 MHz
temperature range: -400C to +125 0C
PACKAGE OUTLINES
PCB/PCF80C51/C31BH-3P, PCA80C51/C31BH-3P: 40 lead DIL; plastic (SOT129).
PCB/PCF80C51/C31BH-3WP, PCA80C51/C31BH-3WP: 44-lead PLCC; plastic leaded chip-carrier
(SOT187 pedestal or SOT187AA pocket version depending on source, versions are interchangeable.
I (June
1988
209
l
PCBBOC51BH-3
PCBBOC31BH-3
'---------------------------------------------------------------~
frequency
reference
cou nters
~
~
XTAL2
TO
XTAL 1
OSCILLATOR
AND
TIMING
PROGRAM
MEMORY
(4K x 8 ROM)
L.
TWO l6-BIT
riMER/EVENT
COUNTERS
DATA
MEMORY
(128x8RAM)
(1)
L ;:-.
;:.
Tl
L.
;:-.
PCBBOC31BH-3
PCBBOC51 BH-3
J--
A
CPU
'l
III
64 K-BYTE BUS
EXPANSION
CONTROL
internal
interrupts
..: 7'
-- -INTO
INTl
control
~
external interrupts
===>
'" 7'
PROGRAMMABLE I/O
'" 7
PROGRAMMABLE
SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
M{H}
parallel ports,
address/data bus
and I/O pins
serial in
serial out
7Z22355
POWER
VCC
_
-
SUPPLY { VSS
+5VMAINSUPPLY
GROUND
(1) PCB80C51 BH-3 only.
Fig. 1 Block diagram.
210
June
19881 (
DEVELOPMENT DATA
PCB80C39
PCBBOC49
Tnis data sheet cuntains advance information and
specifications are subject to change Without notice.
FOR DETAILED INFORMATION SEE REVELANT DATA BOOK OR DATA SHEET
SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
DESCRIPTION
The PC80CXX famiiy of single-chip 8-bit CMOS microcontrollers consists of:
• The PCB80C49 with resident mask programmed 2 K x 8 ROM, 128 x 8 RAM.
• The PCB80C39 without resident program memory for use with external EPROM/ROM, 128 x 8 RAM.
All versions are pin and function compatible to their NMOS counter parts but with additional features
and high performance.
The PC80CXX family are designed to be efficient control processors as well as arithmetic processors.
Their instruction set allows the user to directly set and reset individual I/O, and to test individual
individual bits within the accumulator. A large variety of branch and table look-u'p instructions enable
efficient implementation of standard logic functions. Code efficiency is high; over 70% of the
instructions are single byte; all others are two byte.
An on-chip 8-bit counter is provided, which can count either machine cycles (-=- 32) or external events.
The counter can be programmed to cause an interrupt to the processor.
Program and data memories can be expanded using standard devices. Input/output capabilities can be
expanded using standard devices.
The family has low power consumption and in addition a power down mode is provided.
For further detailed information see users manual 'single-chip 8-bit microcontrollers'.
Features
8-bit CPU, ROM, RAM, liD in a single 40-pin package
PCB80C49: 2K x 8 ROM, 128 x 8 RAM
Internal counter/timer
Internal oscillator, clock driver
Single-level interrupts: external and counter/timer
17 internal registers: accumulator, 16 addressable registers
Over 90 instructions: 70% single byte
All instructions: 1 or 2 cycles
Easily expandable memory and I/O
TTL compatible inputs and outputs
Single 5 V supply
Wide frequency operating range
Low current consumption
Available with extended temperature ranges: (PCB version)
0 to + 70 °C
(PCF version) -40 to + 85 0C
(PCA version) -40 to + 110 °C
• Frequency range: 1 to 15 MHz for all temperature ranges
•
•
•
•
•
•
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
•
•
•
Peripheral interfaces and controllers
Test and measurement instruments
Sequencers
Audio/video systems
Environmental control systems
Modems and data enciphering
PACKAGE OUTLINES
PCB/F/A80C39/C49P: 40-lead 01 L; plastic (SOT129).
PCB/F/A80C39/C49WP: 44-lead PLCC; plastic leaded chip carrier, 'pocket' version (SOT187AA);
'pedestal' version (SOT187). These versions are interchangeable.
---------------------------
' ] (APril 1989
211
N
...a
N
""0""0
()()
DB7-DBO
roro
(X) (X)
00
»
g
()(')
RESIDENT ROM
1K x 8
2K x 8
c.o
c.o
~W
PCB80C48
PCB80C49
<.0<.0
DECODE
00
P17-P10
cfu
t
REGISTER 2
INSTRUCTION
REGISTER
&
DECODER
REGISTER 3
REGISTER 4
REGISTER 5
+-- TEST 0
D
'+-- TEST 1
E
C
REGISTER 7
D
E
8 LEVEL STACK
(VARIABLE LENGTH)
o
VCC
I+-- FLAG 0
V;;
POWER
SUPPLY
{
+-- FLAG 1
VSS
I+--
REGISTER 6
OPTIONAL SECOND
REGISTER BANK
;~~~R
+-- CARRY
DATA STORE
ACC 81T
TEST
RESIDENT RAM ARRAY
128 x 8
TIMING
OUTPUT
INTERRUPT
EXPANDER
STROBE
OSCILLATOR ADDRESS
XTAL
LATCH
SINGLE
STEP
READ WRITE
STROBES
ENABLE
Fig. 1 Block diagram.
PCB80C49
7Z89661.2
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
~
PCB83C552
PCB80C552
~
FOR DETAILED INFORMATION SEE REVELANT DATA BOOK OR DATA SHEET
SINGLE-CHIP 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The PCB83C552 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is
a derivative of the PCB80C51 microcontroller family. The PCB83C552 has the same instruction set as
the PCB80C51. Two versions of the derivative exist although the generic term "PCB83C552" is used
to refer to both family members:
• PCB83C552: 8 K bytes mask-programmable ROM, 256 bytes RAM
• PCB80C552: ROM-less version of the PCB83C552
This I/O intensive device provides architectural enhancements to function as a controller in the field of
automotive electronics, specifically engine management and gear box control.
The PCB83C552 contains a non-volatile 8 K x 8 read-only program memory, a volatile 256 x 8 read/write
data memory, six 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51),
an additional 16-bit timer coupled to capture and compare latches, a fifteen-source, two-priority-level,
nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and 12C-bus), a 'watchdog' timer and on-chip oscillator and timing circuits. For
systems that require extra capability, the PCB83C552 can be expanded using standard TTL compatible
memories and logic.
The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic
plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte,
45 two-byte and 17 three-byte. With a 12 MHz crystal, 58% of the instructions are executed in 1 /J.S
and 40% in 2 /J.S. Multiply and divide instructions require 4/J.s.
Features
•
•
•
•
•
•
•
•
•
•
•
80C51 central processing unit
8 K x 8 ROM, expandable externally to 64 K bytes
256 x 8 RAM, expandable externally to 64 K bytes
Two standard 16-bit timer/counters
An additional 16-bit timer/counter coupled to four
capture registers and three compare registers
A 10-bit ADC with 8 multiplexed analogue inputs
Two 8-bit resolution, Pulse Width Modulated outputs
Five 8-bit I/O ports plus one 8-bit input port shared
with analogue inputs
12 C-bus serial I/O port with byte orientated master
and slave functions
Full-duplex UART compatible with the standard
PCB80C51
On-chip watchdog timer
• PCB80C552/83C552
XTALfrequency range: 1.2to 12 MHz
temperature range: 0 oC to + 70 oC
PCF80C552/83C552
XTAL frequency range: 1.2 to 12 MHz
temperature range: -40 oC to +85 OC
PCA80C552/83C552
XTAL frequency range: 1.2 to 12 MHz
temperature range: -40 oC to + 125 oC
PACKAGE OUTLINES
PCA/PCB/PC F/83C552/80C552WP
68-lead plastic leaded chip carrier (PLCC) 'pocket' version (SOT188AA)
1
(March 1989
213
PC883C552
PC880C552
AVSS
TO
T1
CD
XT
XT
~ I-
CD
I
AVDD
PROGRAM
MEMORY
DATA
MEMORY
8Kx8
ROM
256xS
RAM
~
... I,~
~
~
.
C0 C0
SERIAL
12 C PORT
ADC
..I.
, 7
SDA SCL
®
,
~
..I. ...
PCB8C1C552
PCB83C552
. . >-
DC
t
DUAL
PWM
;..
STi
f
t
®
>-
,
7
lJ..
""®
AS -15
... 7
... 7
8-bit
internal bus
1
J.
16
L,.
:.
~ ~
r
l -.. - -
PARALLEL
I/O PORTS
SERIAL
UART
PORT
&
8-BIT
I/O
PORTS
;..
;..,
L....r--r-
PO P1
7' 7
CD CD
P2 P3
TXD RXD
alternative function of port 0
CD
alternative functions of port 1
CD
®
®
alternative function of port 2
POWER
SUPPLY
~+ 5 V MAIN SUPPLY
!
VSS GROUND
---.
March
19891 (
T2
16-BIT
TIMER/
EVENT
COUNTER
~
THREE
16-BIT
~ COMPARACOMPARAf-+
TORS
~ SELECTION
WITH
REGISTERS
I-- I - - - -
• ?
P5
P4
C0 C0
CTOI-CT31
INT2-INT5
C0
T2
RT2
alternative function of port 3
alternative function of port 4
alternative function of port 5
not present in PCB80C552
Fig. 1 Block diagram.
T3
OJ~:UT
;..
....
"'---- l- I- l, L,.'\.L,.,
FOUR
16-BIT
CAPTURE
LATCHES
, L,.
...
,.-- ""-
EXT. BUS
0
214
VSS
I
ADCO-7
-
<
C0
CD
VDD
I
-
AD 0,,-7
®
CD
CPU
80C51
core
excluding
ROM/
7 RAM
~-
,~
CD
AVref
-+
-PWMO PWM1
I
I
--
PCB~
~
~-
CD
INT1
'---
~ I--
,~
CD
TO, T1
TWO 16-BIT
TIMER/
EVENT
COUNTERS
~ I-
A
INTO
CD
"L,.'
WATCHDOG
TIMER
-
CMSRO-CMSR5
CMTO, CMT1
RST
-EW
7Z97647.5
DEVELOPMENT DATA
PCB83C562
PCB80C562
This data sheet contains advance information and
specifications are subject to change without notice.
FOR DETAILED INFORMATION SEE RELEVANT DATABOOK OR DATASHEET.
SINGLE-CHIP 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The PCB83C562 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is
a derivative of the PCB80C51 microcontroller family. PCB83C562 has the same instruction set as the
PCB80C51. Two versions of the derivative exist although the generic term "PCB83C562V'f is used to
refer to both family members:
• PCB83C562: 8 K bytes mask-programmable ROM, 256 bytes RAM
• PCB80C562: ROM-less version of the PCB83C562
The PCB83C562 contains a non-volatile 8 K x 8 read-only program memory (not ROM-less version),
a volatile 256 x 8 read/write data memory, six 8-bit I/O ports, two 16-bit timer/event counters (identical
to the timers of the PCB80C51), an additional 16-bit timer coupled to capture and compare latches: a
fourteen source, two-priority-Ievel, nested interrupt structure, an 8-input ADC, a dual DAC with pulse
width modulated outputs, a UART serial interface, a 'watchdog' timer and on-chip oscillator and timing
circuits. For systems that require extra capability, the PCB83C562 can be expanded using standard TTL
compatible memories and logic.
The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic
plus bit-handling capabilities. The instruction set consists of over 100 instructions; 44% one-byte, 41 %
two-byte and 15% three-byte. With a 12 MHz crystal, 58% of the instructions are executed in 1 /.l.S and
40% in 2 /.l.S. Multiply and divide instructions require 4/.l.s.
Features
•
•
•
•
•
•
•
•
•
•
•
PCB80C51 central processing unit
8 K x 8 ROM, expandable externally to 64 K x 8 bytes
256 x 8 RAM, expandable externally to 64 K x 8 bytes
Two standard 16-bit timer/counters
An additional 16-bit timer/counter coupled to four capture registers and three compare registers
An ADC with 8 multiplexed analogue inputs and 8-bit resolution
Two 8-bit resolution, Pulse Width Modulated analogue outputs
Five 8-bit I/O ports plus one 8-bit input port shared with analogue inputs
Full-duplex UART compatible with the standard PCB80C51
On-chip watchdog timer
Operating ambient temperature
range and XTAL frequency range:
PCB83C562:
0 to + 70 oC; 1.2 MHz - 16 MHz
PCF83C562: -40 to + 85 °C; 1.2 MHz - 12 MHz
PCA83C562: -40 to + 125 oC; 1.2 MHz - 12 MHz
PACKAGE OUTLINE
PCB/PCF/PCA83C562: 68-lead PLCC; plastic 'pocket' version (SOT188AA).
1(
May 1989
215
l
PCB83C562
PCB80C562
~------------------------------------------------------~
AVSS
TO
®
XT
XT
~I-
.~ ~
'!i.- -
I
I
CPU
I
DATA
MEMORY
BKxB
ROM
256x8
RAM
®
,
,,~
SERIAL
UART
PORT
&
I
I
t
t
STjDC
t
;..
~
~
S-bit
internal bus
"
~
16
7
FOUR
16-BIT
CAPTURE
LATCHES
8-81T
I/O
PORTS
~r---r-
T2
16-BIT
TlMER/
EVENT
COUNTER
~
".
"~
• 7
.
;..
THREE
... COMPARA16-BIT
COMPARA...
TORS
f-+ SELECTION
WITH
REGISTERS
~I-
"
PO P1
;:..
7
P5
I-7
P4
CD CD
CTOI-CT31
INT2-INT5
®
alternative function of port 0
®
alternative function of port 3
alternative functions of port 1
@
alternative function of port 4
alternative function of port 2
®
alternative function of port 5
®
not present in PCBSOC552
POWER
SUPPLY
~+ 5 V MAIN SUPPLY
I
VSSGROUND
-.
216
® ®
P2 P3 TXD RXD
~
CD
o
May
WATCHDOG
TIMER
4-
I-
7-
T3
OJ~pRUT
- - -
~
®
ADC
!,.
"
EXT. BUS
;.. ;-
ADCO-7
PCBBOC562
PCB83C562
~t....
PARALLEL
I/O PORTS
AVDD
DUAL
PWM
" >-
" ;..
AD 0-7
r
L.
PROGRAM
MEMORY
AVref
-+
--
PWMO PWM1
®
"
®
.~ I-
-'-0
VSS
PCB'-- ,.-SOC51 "
core
excluding
ROM/
RAM ~
~-
~®
AS -)5
®
VDD
L...--
~f-
-A
INT1
®
®
TO, T1
TWO 16-BIT
TIMER/
EVENT
COUNTERS
A~f-
A
INTO
T1
19891 (
CD
T2
RT2
Fig. 1 Block diagram.
!,.@
CMSRO-CMSR5
CMTO, CMT1
RST
-
EW
7Z22645
DEVELOPMENT DATA
PC883C652
PC880C652
This data sheet contains advance information and
specifications are subject to change without notice.
FOR DETAILED INFORMATION SEE REVELANT DATA BOOK OR DATA SHEET
SINGLE-CHIP 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The PC883C652 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and
is a derivative of the PCB80C51 microcontroller family. The PCB83C652 has the same instruction set as
the PCB80C51. Two versions of the derivative exist although the generic term "PCB83C652" is used
to refer to both family members:
• PCB83C652:
8 K bytes mask-programmable ROM, 256 bytes RAM
• PCB80C652:
ROM-less version of the PCB83C652
This device provides architectural enhancements that make it applicable in a variety of applications
in general control systems.
The PCB83C652 contains a non-volatile 8 K x 8 read-only program memory, a volatile 256 x 8 read/write
data memory, four 8-bit I/O ports, two 16-bittimer/event counters (identical to the timers of the 80C51 ),
a multi-source, two-priority-Ievel, nested interrupt structure, an 12 C interface, UART and on-chip
oscillator and timing circuits. For systems that require extra capability, the PCB83C652 can be
expanded using standard TTL compatible memories and logic.
The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic
plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte,
45 two-byte and 17 three-byte. With a 12 MHz crystal, 58% of the instructions are executed in 1J.Ls
and 40% in 2 J.Ls. Multiply and divide instructions require 4 J.Ls.
Features
•
•
•
e
•
SOC51 central processing unit
8 K x 8 ROM, expandable externally to 64 K bytes
256 x 8 RAM, expandable externally to 64 K bytes
Two standard l6-bit timer/counters
Four 8-bit I/O ports
• 12 C-bus serial I/O port with byte orientated master a~d slave functions
• Full-duplex UART facilities
Three temperature ranges available
to + 70 0C; PCB83C652 versions
-40 to + 85 °C; PCF83C652 versions
-40 to + 125 DC; PCA83C652 versions
• Extended frequency range: 1.2 MHz to 12 MHz
o
PACKAGE OUTLINES
PCA/PCB/PCF83C652P; PCA/PCB/PCF80C652P: 40-lead 01 L; plastic (SOT129).
PCA/PCB/PCF83C652WP; PCA/PCB/PCF80C652WP: 44-lead plastic leaded-chip-carrier
(PLCC) (SOT187 pedestal or SOT187AA pocket versions, these are interchangeable).
PCA/PCB/PCF83C652H; PCA/PCB/PCF80C652H: 44-lead quad flat-pack (QFP). This is in preparation.
1
(september 1988
217
...
N
00
"'0"'0
00
OJ OJ
CX>CX>
OW
00
en
CD
"0
.-+
CD
frequency
reference
counters
~
,---------A----
3
CT
~
co
XTAL2
(J1(J1
1\)1\)
Tl
TO
XTAL 1
(J)(J)
ex>
ex>
1
PROGRAM
MEMORY
(8 K x 8 ROM)
OSCI LLATOR
AND
TIMING
L.
1
TWO 16-BIT
TIMER/EVENT
COUNTERS
DATA
MEMORY
(256x8RAM)
~
L.
;,.
L.
r----
F>
VL
N
CPU
~
PCB80C652
PCB83C652
12 C
1-
SERIAL
I/O
1-
"--'<;
1111
7
64 K-BYTE BUS
EXPANSION
CONTROL
internal
interrupts
V
INTO
INTl
control
"--r----'
external interrupts
~
PROGRAMMABLE I/O
ffi~
parallel ports,
address/ data bus
and I/O pins
-
-VSS
PROGRAMMABLE
SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
serial in
serial out
shared with
port 3
lZ96652.1
POWER {VDD +5V MAIN SUPPLY
SUPPLY
'" 7
'" 7
GROUND
Fig. 1 Block diagram.
SDA} shared with
port 1
SCL
DEVELOPMENT DATA
Th is data sheet contains advance information and
specifications are subject to change without notice.
l__
P_C_B_8_3_C_6_54_ _ _,
FOR DETAILED INFORMATION SEE REVELANT DATA BOOK OR DATA SHEET
SINGLE-CHIP 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The PCB83C654 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and
is a derivative of the PCB80C51 microcontroller family. The PCB83C654 has the same instruction set as
the PCB80C51. The ROM-less PCB80C652 should be used for development purposes.
This device,provides architectural enhancements that make it applicable in a variety of applications
in general control systems.
The PCB83C654 contains a non-volatile 16 K x 8 read-only program memory, a volatile 256 x 8 read/write
data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51),
a multi-source, two-priority-Ievel, nested interrupt structure, an 12 C interface, UART and on-chip
oscillator and timing circuits. For systems that require extra capability, the PCB83C654 can be
expanded using standard TTL. compatible memories and logic.
The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic
plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte,
45 two-byte and 17 three-byte. With a 12 MHz crystal, 58% of the instructions are executed in 1ps
and 40% in 2 ps. Multiply and divide instructions require 4 ps.
Features
•
•
•
•
•
•
•
80C51 central processing unit
16 K x 8 ROM, expandable externally to 64 K bytes
256 x 8 RAM, expandable externally to 64 K bytes
Two standard 16-bit timer/counters
Four 8-bit I/O ports
12 C-bus serial I/O port with byte orientated master and slave functions
Full-duplex UART facilities
A version for extended temperature range is in preparation
PACKAGE OUTLINES
PCB83C654P : 40-lead DI L; plastic (SOT129).
PCB83C654WP: 44-lead plastic leaded chip-carrier (PLCC); (SOT187 pedestal or SOT187AA pocket
version depending on source, versions are interchangeable).
PCB83C654H : 44-iead quad flat-pack; plastic (SOT205A) in preparation.
1(AUgust
1988
219
N
N
-u
o
()
OJ
»c::
to
5i
.-+
CO
frequency
reference
counters
~
~
XTAL2
W
()
0>
T1
TO
XTAL 1
(J1
~
c.o
CO
CO
1
OSCILLATOR
AND
TIMING
"" ~
1
""
~
"" ~
~
"'"
'"
I1II
internal
interrupts
,.
64 K-BYTE BUS
EXPANSION
CONTROL
~
--
INT1
'---v---'
external interrupts
7
control
""
~
PROGRAMMABLE I/O
»U
parallel ports,
address/ data bus
and I/O pins
-
-VSS
12 C
1-
SERIAL
I/O
I-
'--
,.
'"
7
PROGRAMMABLE
SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
serial in
serial out
shared with
port 3
7Z96652.1P
POWER {VDD +5V MAIN SUPPLY
SUPPLY
~
PCB83C654
/l
CPU
INTO
TWO 16-BIT
TIMER/EVENT
COUNTERS
DATA
MEMORY
(256x 8 RAM)
PROGRAM
MEMORY
(16Kx8 ROM)
GROUND
Fig. 1 Block diagram.
SDA} shared with
port 1
SCL
~~_J
PCB83C851
PCB80C851
FOR DETAILED INFORMATION SEE RELEVANT DATABOOK OR DATASHEET.
SINGLE-CHIP 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
Features
The PCB83C851 single chip microcontroller is
manufactured in an advanced CMOS process and is a
derivative of the PCB80C51 microcontroller family. The
PCB83C851 has the same instruction set as the PCB80C51.
Two versions of the derivative exist although the generic
term 'PCB83C851 ' is used to refer to both family members:
•
•
•
•
•
•
•
•
•
• PCB83C851: 4 K bytes mask-programmable ROM, 128
bytes RAM, 256 bytes EEPROM
• PCB80C851: ROM-less version of the PCB83C851
This device provides architectural enhancements that make
it suitable for a variety of applications, specifically control
systems.
The PCB83C851 contains a non-volatile 4 K x 8 read-only
program memory; a volatile 128 x 8 read/write data
memory; a 256 byte electrically erasable programmable
read only memory (EEPROM); 32 110 lines; two 16-bit
timer/event counters (identical to the timers of the
PCB80C51); a seven source, five-vector, two-priority-level,
nested interrupt structure; a serial 110 port for either multiprocessor communications, 110 expansion or full duplex
UART; and on-chip oscillator and timing circuits. For
systems that require extra capability, the PCB83C851 can
be expanded using standard TTL compatible memories and
logic.
The PCB83C851 has two software selectable modes of
reduced activity for further power reduction: Idle and
Power-down. The Idle mode freezes the CPU while
allowing the RAM, timers, serial port and interrupt system
to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator causing all other
chip functions to be inoperative.
•
•
•
•
•
PCB80C51 central processing unit
4 K x 8 ROM, expandable externally to 64 K bytes
128 x 8 RAM, expandable externally to 64 K bytes
Four 8-bit 110 ports, 32 110 lines
Two 16-bit timer/event counters
Full-duplex serial port
Boolean processing
On-chip oscillator
Seven-source, five-vector interrupt structure with two
priority levels
58% of the instructions are executed in 1 [1s; multiply
and divide in 4 [1s; all others are executed in 2 [1s (with a
12 MHz oscillator)
Enhanced architecture with non-page-orientedinstructions, direct addressing, four 8-byte register
banks, stack depth up to 128-bytes, multiply, divide,
subtract and compare instructions
ROM code protection (mask-programmable)
Security mode, user dependent protection of the
EEPROM contents
Additional interrupt source (EEPROM) 'ORed' with
serial interrupt
EEPROM:
• Non-volatile 256 x 8 bit EEPROM (electrically erasable
. programmable read only memory)
• On-chip voltage multiplier for erase/write
• 10000 erase/write cycles per byte
• 10 years non volatile data retention
• Infinite number of read cycles
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bithandling capabilities. The instruction set consists of over
100 instructions: 49 one-byte, 46 two-byte and 16 threebyte. With a 12 MHz crystal, 58% of the instructions are
executed in 1 [1s and 40% in 2 [1S. Multiply and divide
instructions require 4 [1s.
PACKAGE OUTLINES
PCB /PCF83C85 1I80C85 1P: 40-lead DIL; plastic (SOT 129)
PCB/PCF83C851 /80C851 WP: 44-lead PLCC; plastic, leaded-chip-carrier (SOT 187 AA)
I(
December 1988
221
l______
PCB83C851
PCB80C851
frequency
reference
.-"----,
XTAL2
counters
TO
XTAL 1
T1
•
OSCILLATOR
AND
TIMING
PROGRAM
MEMORY (I)
(4Kx8ROM)
DATA
MEMORY
(128 x 8 RAM)
/~
/).
TWO 16-BIT
TIMER/EVENT
COUNTERS
EEPROM
(256x8)
f~
~
A
CPU
K
"
PCB83C851
PCB80C851
V
internal
interrupts
INTO
64 K-BYTE BUS
EXPANSION
CONTROL
controi
INT 1
'-----v---'
external interrupts
POWER
SUPPLY {
V
~
PROGRAMMABLE I/O
~
parallel ports,
address/ data bus
and I/O pins
VDD + 5 V MAiN SUPPLY
VSS GROUND
-
Note (1): PCB/PCF83C851 only
Fig. 1 Block diagram.
222
~
December
19881 (
V
PROG RAMMAB LE
SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
7Z24296
serial in
"
serial out
shared with
port 3
PCF1303T
18-ELEMENT BAR GRAPH LCD DRIVER
GENERAL DESCRIPTION
The PCF l303T is an l8-element bar graph LCD driver with linear relation to control voltage (V c)
when in pointer or thermometer mode.
27
PCF1303T
Vref max
01
6
02
7
03
8
04
9
0 S 10
26
Vref min
LATCH
AND
DIVIDER
CIRCUITRY
06
11
07
12
08
13
09
14
°10 15
°11 16
°12 17
°13 18
V
-+_....;14--=.OS:..::C_--t OSCILLATOR 1 - - - - - - - - - 1 CP
°14 19
°15 20
°16 21
°17 22
VSS
4
11
MODE
SELECTOR
°18 23
OR
24
7Z81228
Fig. 1 Block diagram.
PACKAGE OUTLINE
PCF1303T: 28-lead mini-pack; plastic (S028; SOT136A).
~ ~November1986
223
Jl___________________________________
______
PC_F_13_0_3_T___
PIN DESCRIPTION
voo
pin no.
symbol
name and function
Vref max
1
Vosc
oscillator pin
4
11
mode select input
OR
5
VSS
ground (O V)
°18
6 to 23
01 to 018
segment outputs
24
OR
back-plane output
25
Vc
control voltage
26
27
Vref min
Vref max
reference voltage inputs
28
VDD
positive supply voltage
Vref min
Vc
°17
°16
°15
°5
°14
°7
°12
08
°11
09
°10
°13
(1) Pins 2 and 3 should be connected to VSS'
Fig.2 Pin configuration.
FUNCTION TABLE
H
11
mode
L
pointer
H
thermometer
= HIGH voltage
level
L = LOW voltage level
224
November
19861 (
l___
18-element bar graph LCD driver
P_C_F_1_3_03_T______
FUNCTIONAL DESCRIPTION
The PCF1303T is an 18-element bar graph LCD driver with linear relation to the control voltage when
in pointer or thermometer mode.
The first segment will energize when the control voltage is less than the trigger voltage (VT(bar)2 see
equation [3]).
The circuit has analogue and digital sections.
The analogue section consists of a comparator with the inverting input coupled to the input control
voltage. The non-inverting input of the comparator is connected via 17 analogue switches to the nodes
of an 18-element resistor divider. The extremities of the resistor divider are coupled via high-input
impedance amplifiers to the maximum reference voltage input and the minimum reference voltage input.
The control input functions with Schmitt trigger action.
The digital section has one reference output (OR) to drive the back-plane and 18 outputs (01 to 018)
to drive the segments.
The segment outputs incorporate two latches and some gates.
The circuit is driven by an on-chip oscillator with external resistors and capacitors. The outputs are driven
at typical 100 Hz.
LINEARITY
V step = V step' ± ~ V step
[1 ]
V step ' is the voltage drop (internal) across the resistor-ladder network.
~ V step is the differential on V step.
V step '
~ V2
=
(Vrefmax ± ~V2') - (Vrefmin ± ~V2)
18
[2]
2nd ~ V2' are the maximum offset voltage spread of the on-chip voltage followers.
ABSOLUTE VOLTAGE TRIGGER LEVEL
The absolute voltage trigger level at the V c pin is VT(bar)n;
VT(bar)n = (Vrefmin ± ~V2*)
+ {(n - 1)V step ' ± ~VR} ± ~V1 ± VH
[3]
n = number of segments; 2 ~ n ~ 18.
~VR
is the voltage deviation at step n of the resistor-ladder network (for n = 2 or 18, ~VR = ~Vstep).
~V 1
is the offset voltage for the on-chip comparator.
VH is the hysteresis voltage: 30% V step ;;;. VH;;;' 10% V step .
* For ~ V2 the same sign (+ or -) should be used as in equation [2] .
1
(November 1986
225
~
Jl___________________________________
____P_C_F_13_0_3_T__
RATINGS
Limiting values as in accordance with the Absolute Maximum System (IEC 134)
-0,5 to + 15 V
Supply voltage
VOO
Voltage on any input
VI
-0,5 to VOO + 0,5 V
O.C. current into any input or output
± II
max.
Storage temperature range
T stg
Operating ambient temperature range
Tamb
10 mA
-25 to + 125 °C
-40 to + 85 °C
D.C. CHARACTERISTICS
VSS = 0 V
Tamb (OC)
parameter
VOO
symbol
V
min. max.
min. typo
+ 85
unit
notes
max. min. max.
Quiescent device
current
10,0
100
1200
1200
1200 IJ.A
1
Operating supply
current
8,2
100
2,0
2,0
2,0
mA
2
I nput leakage
current
6,0
8,2
10,0
± II
± II
± II
300
300
300
300
300
300
1000 nA
1000 nA
1000 nA
3
HIGH level
input voltage
select input 11
6,0
8,2
10,0
VIH
VIH
VIH
LOW level input
voltage
select input 11
6,0
8,2
10,0
VIL
VIL
VIL
HIGH level
output voltage
6,0
8,2
10,0
VOH
VOH
VOH
LOW level
output voltage
6,0
8,2
10,0
VOL
VOL
VOL
Output current
HIGH
6,0
8,2
10,0
-IOH
-IOH
-IOH
0,6
0,85
1,0
0,5
0,7
0,85
0,35
0,45
0,6
mA
mA
mA
5
Output current
LOW
6,0
8,2
10,0
IOL
IOL
IOL
0,65
1,0
1,3
0,5
0,8
1,0
0,4
0,6
0,8
mA
mA
mA
6
For notes see page 6.
226
+ 25
-40
November
19861 (
4,2
5,8
7,0
4,2
5,8
7,0
1,8
2,4
3,0
2,4
1,8
2,4
3,0
5,95
8,15
9,95
5,95
8,15
9,95
1,8
3,0
5,95
8,15
9,95
0,05
0,05
0,05
0,05
0,05
0,05
V
V
V
4,2
5,8
7,0
V
V
V
V
V
V
4
0,05 V
0,05 V
0,05 V
4
l___
18-element bar graph LCD driver
P_C_F_13_0_3_T______
Tamb (OC)
parameter
VDD
-40
symbol
V
+ 25
min. max.
min.
typo
+ 85
max. min.
max.
unit
Input voltage
control input V c
6,0
8,2
10,0
V'C
V'C
V'C
0,0
0,0
0,0
6,0
8,2
10,0
0,0
0,0
0,0
6,0 0,0
8,2 0,0
10,0 0,0
6,0 V
8,2 V
10,0 V
Input voltage
6,0
8,2
10,0
V,R max
V,R max
V,R max
3,6
3,6
3,6
5,5
7,7
9,5
3,6
3,6
3,6
5,5
7,7
9,5
3,6
3,6
3,6
5,5
7,7
9,5
V
V
V
V ref m in input
6,0
8,2
10,0
V,R min
V,R min
V,R min
0,5
0,5
0,5
1,0
4,5
6,0
0,5
0,5
0,5
1,0
4,5
6,0
0,5
0,5
0,5
1,0
4,5
6,0
V
V
V
Vref max Vrefmin
6,0
8,2
10,0
~V,
~V,
3,0
3,0
3,0
DC component
bar output to
back-plane output
8,2
± VBP
Back-plane
frequency
8,2
fBP
I nput offset
voltage
8,2
± V,O
120
Step voltage
variation
8,2
± ~Vstep
Input voltage
slew rate
Vc input
6,0
8,2
10,0
SR
SR
SR
V ref max input
Input voltage
For notes see next page.
~V,
90
3,0
3,0
3,0
3,0
3,0
3,0
25
10
110
100
25
notes
V
V
V
25
mV
7
110
Hz
8
120
120
mV
9
50
50
50
mV
10
50
50
50
50
50
50
50
50
50
Vis
Vis
Vis
11
90
'I
(November 1986
227
Jl___________________________________
______P_C_F1_30_3_T___
Notes to D.C. characteristics
1. Vrefmin = 0,5 V, Vrefmax = 9,5 V, Vc= Vosc= 0 V, 11 at VSSor VOO·
2. See Fig. 2.
3. Pin under test at VSS or VOO. All other inputs simultaneously at VSS or VOO.
4.
10 = 0, all inputs at VSS or VOO.
5.
VOH = VOO - 0,5 V, all inputs at VSS or VOO.
6. VOL = 0,4 V, all inputs at VSS or VOO'
7. fBP = 100 Hz, load segment outputs to back-plane output.
Cl - C18 ~ 0,01 JJ.F, CBP = Cl + C2 + ... C18 ~ 0,05 JJ.F, Rl - R18 ~ 2 Mil.
8.
9.
Rosc = 0,1 Mil, Cosc = 390 pF.
Number of segments 2 or 18.
For n = 2:
Via = Vc - Vrefmin -
(Vrefmax) - (Vrefmin)
18
± VH
For n = 18:
Via = Vc - Vrefmax +
(Vref max) - (V ref min)
18
± VH
10. See equation [1] .
11. Condition applies with clock oscillator such that fBP = 100 Hz.
50kO
c::=:::::J
r-C==I-
c=::=:J
gOO
kO
L--
50
kO
Voo
input
I
VOO Vref Vref
Ve
max min
0,1
MO
II
I I
C
OR 018 017 016 015 014 013 012 011 010
PCF1303T
Vose
L-J
=r: 390pF
11
VSS
I
°1
02
03
04
05
06
°7
I
VOO or
VSS
08
l
l!I~
Og
II
~
r-
7 Z81230
Fig.3 Typical application.
228
November
19861 (
c::::::::J
c=::=:J
----
c::::::::J
--
DEVELOPMENT DATA
This data sheet contains advance information and
PCF21XX
FAMILY
specifications are subject to change without notice.
LCD DRIVER
GENERAL DESCRIPTION
The members of the PCF21 XX family are single chip, silicon gate CMOS circuits. A three-line bus
(CBUS) structure enables serial data transfer with microcontrollers. All inputs are CMOS/NMOS
compatible.
Features
•
•
•
•
•
•
•
Supply voltage 2,25 to 6,5 V
Low current consumption
Serial data input
CBUS control
One-point built-in oscillator
Expansion possibility
Power-on reset clear
•
•
•
•
LCD segments
LE 0 segments
Multiplex rate
Word length
PCF2100
PCF2110
PCF2111
PCF2112
40
60
2
1 :2
34 bit
64
32
1 :2
34 bit
1: 1
34 bit
1 :2
22 bit
PACKAGE OUTLINES
PCF2100P: 28-lead 01 L; plastic (SOT117).
PCF2110P:
PCF2111 P: 40-lead 0 I L; plastic (SOT129).
PCF2112P:
PCF2100T: 28-lead mini-pack; plastic (S028; SOT136A).
PCF2110T:
PCF2111T: 40-lead mini-pack; plastic (VS040; SOT158A).
PCF2112T:
'I
(DeCember 1987
229
l_~__
PCF21XX
FAMILY
BP1
26
BACKPLANE
&
2 V DD
OLEN
28
&
CLB
DATA
27
6BO
pF
OSCILLATOR
BUS
CONTROL
DIVIDER
1 MD
PCF 2100
4
VSS
7Z83453.3
Fig, 1 Block diagram; PCF2100
OLEN
DATA
PINNING
Supply
BP1
BP2
S1
S2
CLB
Inputs
asc
clock burst (CBUS)
oscillator input
S4
27
28
DATA
OLEN
data line
} CBUS
data line enable
S20 to S1
BP2
BP1
LCD driver outputs
backplane drivers
(commons of LCD)
S6
S13
SB
S12
S9
S11
S10
Fig, 2 Pinning diagram; PCF2100
December
positive supply
negative supply
3
S7
230
VDD
VSS
S3
S5
S15
2
4
19871 (
1
Outputs
5 to 24
25
26
}
J
LCD driver
PCF21XX
FAMILY
V LED
BP1
BACKPLANE
&
11 V DD
680
9
DLEN
10
CLB
8
DATA
pF
OSCILLATOR
BUS
12
&
CONTROL
DIVIDER
1 M.I1.
PCF2110
13
VSS
7Z83449.3
«~
«C
Fig.3 Block diagram; PCF2110 (50T-129).
56
~
:2
57
:2!!
58
0
59
W
0..
PINNING (50T-129)
Supply
..J
W
>
w
510
C
11
13
VDD
V55
positive supply
negative supply
DATA
DLEN
CLB
05C
data line
)
data line enable CBU5
clock burst
oscillator input
LCD driver outputs
backp lane drivers
(commons of LCD)
14
15
55 to 51
BP2
BP1
532
531
16 to 40
530 to 56
511
512
Inputs
8
513
514
CLB
PCF2110
(50T -129)
515
9
10
12
516
Outputs
05C
517
1 to 5
6
V55
518
532
519
531
520
530
521
529
522
528
523
527
524
526
7
}
}
LED driver outputs
LCD driver outputs
525
7Z83445.4
Fig. 4 Pinning diagram; PCF2110
1
(December 1987
231
PCF21XX
FAMILY
l
PINNING (50T-158A)
DLEN
Supply
DATA
2
4
VDD
V55
positive supply
negative supply
CLB
05C
DATA
DLEN
clock burst (CBU5)
oscillator input
BP1
BP2
Inputs
1
S1
S2
S30
7
S3
S29
8
S4
S28
9
32
S5
10
31
S6
S27
PCF2110
(SOT -158A)
S7
S25
S8
S24
S9
S23
S10
S22
26
S11
S21
25
S12
S20
24
S13
S19
23
S14
S18
S15
S17
S16
lZ97133.1
Fig. 5 Pinning diagram; PCF2110
232
December 1987] (
3
39
40
data line
} CBU5
data line enable
Outputs
5
6
7 to 36
37
38
532
531
530 to 51
BP2
BP1
}
}
LE D driver outputs
LCD driver outputs
backplane drivers
(commons of LCD)
j
LCD driver
PCF21XX
FAMILY
- - BP1
38
37
BACKPLANE
OLEN
&
680
pF
40
05CILLATOR
BU5
3
&
CLB
39
DATA
CONTROL
DIVIDER
1 MrI.
PCF2111
4
V55
lZ84581.3
Fig.6 Block diagram; PCF2111
OLEN
e:(
le:(
0
I:2
V DD
2
DATA
PINNING
BP1
Supply
w
:2:
BP2
0
51
...J
W
>
W
0
2
4
Q..
530
7
529
8
35
52
34
53
54
9
55
527 10
56
526
PCF2111
(50T -129)
(50T -158A)
525
30
57
29
58
524
59
523
510
522 15
511
16
512
521
520 17
24
513
519 18
23
514
518 19
515
517
516
20
positive supply
negative supply
CLB
asc
clock burst (CBUS)
oscillator input
DATA
OLEN
data line
} CBUS
data line enable
S32 to S1
BP1
BP2
LCD driver outputs
backplane drivers
(commons of LCD)
Inputs
1
3
39
40
528
VDD
VSS
Outputs
5 to 36
38
37
}
lZ97731
Fig. 7 Pinning diagram; PCF2111
'I (
December 1987
233
PCF21XX
FAMILY
BP
38
BACKPLANE
&
2 V DD
40
DLEN
05CI LLATOR
BU5
CLB
1,5 nF
&
39
DATA
DIVIDER
PCF2112
lZ86381.3
Fig. 8 Block diagram; PCF2112
DLEN
DATA
PINNING
Supply
38 BP
37
n.e.
51
52
34 53
33 54
2
4
VDD
VSS
positive supply
negative supply
CLB
OSC
DATA
OLEN
clock burst (CBUS)
oscillator input
Inputs
1
3
39
40
data line
\ CBUS
data line enable f
32 S5
Outputs
527 10
526
PCF2112
(50T -129)
(50T -158A)
31
56
57
525
58
524
59
523
510
26
S22
521
S11
512
16
520
513
519
514
S18
515
21
517
516
lZ91732
Fig. 9 Pinning diagram; PCF2112
234
December
19871 (
5 to 36
38
S32 to S1
BP
37
n.c.
LCD driver outputs
backplane driver (common
of LCD)
not connected
J
LCD driver
PCF21XX
FAMILY
-~-
FUNCTIONAL DESCR IPTION
An LCD segment or LED output is activated when the corresponding DATA-bit is HIGH.
PCF2100
When DATA-bit 21 is HIGH, the A-latches (BP1) are loaded. With DATA-bit 21 LOW, the B-Iatches
(BP2) are loaded. CLB-pulse 23 transfers data from the shift register to the selected latches.
PCF2110
When DATA-bit 33 is HIGH, the A-latches (BP1) are loaded. Bits 31 and 32 contain the LED output
information. With DATA-bit 33 LOW, the B-Iatches (BP2) are loaded and bits 31 and 32 are ignored.
CLB-pulse 35 transfers data from the shift register to the selected latches.
PCF2111
When DATA-bit 33 is HIGH, the A-latches (BP1) are loaded. With DATA-bit 33 LOW, the B-Iatches
(BP2) are loaded. CLB-pulse 35 transfers data from the shift register to the selected latches.
PCF2112
When DATA-bit 33 is HIGH, the latches are loaded. CLB-pulse 35 transfers data from the shift
register to the selected latches.
e::(
le::(
o
I:2
-~
OLEN ~
w
:a;:
c..
o...J
CLB
W
>
W
o
__ 111_2
l~
32
20
4
test leading zero
DATA
bit no. 0
output
1
1
51
51
leading zero
52
52
3
53
4
54
5
55
56
57
53
4
54
55
56
57
33
21
34
22
t
35 . . - 2110,2111,2112
23 . . - 2100
load pulse
=~
31
32
33 }
2110,2111,2112
531 532
19 20
519 520
1" }
_2100
load bit
7Z97738.3
Fig. 10 CBUS data format.
7283447.2
Fig. 11 LED driver circuitry.
I
(December 1987
235
l_~__
PCF21XX
FAMILY
The following tests are carried out by the bus control logic:
a. Test on leading zero.
b. Test on number of DATA-bits.
c. Test of disturbed OLEN and DATA signals during transmission.
If one of the test conditions is not fulfilled, no action follows the load condition (load pulse with
DLEN LOW) and the driver is ready to receive new data.
Voo
(V oo + VSS )/2
vss
Voo
(V oo + V )/2
SS
Vss
voo
Vss
-
ON/OFF
OFF/ON
ON/ON
A A
-iJT1- dl- dl- dl_TI LJ JL LJ
-~
dl-
- V ss )
- V SS)/2
o
(V oo - Vss )/2
- (V oo - VSS )
(V oo - V )
SS
(V oo -V SS )/2
o -~
(V oo - V )/2
SS
- (V oo - V SS )
(V oo
(V oo
-
_n A
OFF/OFF
J\
A
11
II 11
1
J
_I l/f LCD 1__
Fig. 12 Timing diagram (except PCF2112).
OFF
ON
_TIl JlJ
_TIl U1
o
ru
-.1_1
f LCD
BP
Segment X
(SX)
BP -SX
I~
7Z97730.2
Fig. 13 Timing diagram for PCF2112.
236
December
19871 (
BP1
BP2
Sx
BP1-Sx
BP2-Sx
Z97739.1
J
LCD driver
PCF21XX
FAMILY
- - - - BUS DRIVER
PCF21 XX
____~---+~VDD2
VDD_1+-~____~___
7Z83448.3
Fig. 14 Input circuitry.
Note to Fig. 14
VSS line is common. In systems where it is expected that V002>V001 +0,5 V,a resistor should be
inserted to reduce the current flowing through the input protection. Maximum input current ~40J.LA.
LCD
11IfCA
«
«
o
I-
I-
Z
w
r
~
Q.
o
...J
W
~
>
W
o
-
t
I
BP1 BP2
S1 to S32
V DD
OLEN
C LB
PCF2111
asc
r- DATA
MASTER
DATA
CLB
OLEN1
OLEN2
DLEN3
--
VSS
A
~
!
BP1 BP2
j
l
, . . - - OLEN
r--- CLB
1
BP1 BP2
S1 to S32
Sl to S32
, . . - - OLEN
PCF2111
OSC -
.---
CLB
PCF2111
asc r--
r- DATA
r- DATA
SLAVE 1
SLAVE 2
VSS r-
VSS
r--
7Z97735.1
(1) I n the slave mode, the serial resistors between dP1 and BP2 of the PCF2111 and the backplane
of the LCD must be> 2,7 kn. In most applications the resistance of the interconnection to
the LCD already has a higher value.
Fig. 15 Diagram showing expansion possibility (using PCF2111).
Note to Fig. 15
By connecting OSC to VSS the BP-pins become inputs and generate signals synchronized to the single
oscillator frequency, thus allowing expansion of several members of the PCF21 XX family up to the BP
drive capability of the master. The PCF2112 can only function as a master for other PCF2112s.
I
(December 1987
237
l______- -
PCF21XX
FAMILY
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
symbol
min.
max.
unit
Supply voltage range
VOO
-0,5
9,0
V
Input voltage range
OLEN, CLB, OATA and OSC
VI
VSS-O,5
VOO+O,5
V
Output voltage range
BP1, BP2 and S1 to S32
Vo
VSS-O,5
VOO+ 0,5
V
conditions
parameter
Supply current
±IOO, ±ISS
-
50
mA
OC input current
±II
-
20
mA
OC output current
±IO
-
25
mA
Ptot
-
500
mW
Po
-
100
mW
-65
+150
°c
Total power dissipation
per package
note 1
Power dissipation per output
Storage temperature range
T stg
Note to the ratings
1. Derate by 7,7 mW/oC when Tamb > 60 °C.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is advised to take handling precautions appropriate to handling MaS devices (see
'Handling MaS devices').
238
December
19871 (
J
LCD driver
PCF21XX
FAMILY
- - DC CHARACTERISTICS
VSS = 0 V; VOO = 2,25 to 6,5 V; Tamb = -40 to + 85 oC; RO = 1 Mil; Co = 680 pF; unless otherwise
specified
parameter
conditions
Supply voltage
unit
symbol
min.
typo
max.
VOO
2,25
-
6,5
V
-
20
50
pA
Supply current
note 1
1001
Supply current
note 1; T amb =
-25 to + 85 oc
1002
-
20
30
pA
Power-on reset level
note 2
VPOR
-
1,0
1,4
V
VIL
VIH
-
-
0,8
2,0
-
-
V
V
Inputs CLB, DATA
OLEN
I nput voltage
LOW
HIGH
«
~
o
I-
Z
w
:;
Leakage current
VI = VSS or VOO
± II
-
pA
note 3
CI
-
-
1
Input capacitance
10
pF
VI = VSS
IOSC
0,5
1,2
5,0
pA
± VBP
-
20
-
mV
RBP
-
0,5
5
kil
RS
-
1
7
kil
8
14
-
mA
±IO
-
-
1
pA
ILEO
-
-
20
mA
Input
asc
Oscillator start-up
current
0..
o
..J
LCD outputs
W
>
W
o
OC component of
backplane drivers
Backplane driver
output impedance
Segment driver
output impedance
note 4; VOO
=5 V
note 4; V DO = 5 V
LED outputs
(S31 and S32 in
PCF2110)
Output current LOW
Output leakage
current
Load current
VOL =0,4 V;VOO=5 V IOL
Va = VOD
'I
(December 1987
239
PCF21XX
FAMILY
AC CHARACTERISTICS (note 5)
VSS = 0 V; VDD = 2,25 to 6,5 V; Tamb = -40 to + 85 oC; RO = 1 Mn; Co = 680 pF; unless otherwise
specified
parameter
conditions
symbol
min.
typo
max.
unit
tSUDA
3
-
-
/J-S
/J-S
-
/J-S
-
/J-S
Inputs CLB, DATA
DLEN
Data set-up time
Data hold time
tHDDA
3
-
Leading zero set-up time
tSULZ
3
-
Enable set-up time
tSUEN
1
Disable set-up time
tSUDI
2
Load pulse set-up time
tSULD
2,5
-
/J-S
Busy time
tBUSY
3
tWH
-
/J-S
1
-
CLB LOW time
tWL
5
-
-
/J-S
CLB period
tCLB
10
-
-
/J-S
Rise and fall times
t r , tf
-
-
10
/J-S
flCD
60
75
100
Hz
flCD
30
35
50
Hz
CLB HIGH time
/J-S
/J-S
LCD timing
LCD frame frequency
240
LCD frame
frequency for
PCF2112
Co
Transfer time with
test loads
VDD
=5 V
tBS
-
20
100
/J-S
Driver delay with
test loads
VDD
=5 V
tpLCD
-
20
100
/J-S
December 1987"1 ("
= 1,5 nF
j
LCD driver
- - -
Ii
PCF21XX
FAMILY
Notes to the characteristics
1. Outputs open; CBUS inactive.
2. Resets all logic, when VDD
< VPOR.
3. Periodically sampled (not 100% tested).
4. Outputs measured one at a time.
5. All timing values are referred to VI H and VI L levels with an input voltage swing of VSS to VDD.
-
BP (PCF2112), BP1,BP2 - - ( ] ) - I LOAD = 25 J.l.A
-
51 to 532 - - ( ] ) - ILOAD=15J.l.A
1,5 U]'
«
«
---c==J-- V DD
531, 532
(PCF2110only)
(2%)
I-
lZ97731.1
o
I2
LLJ
Fig. 16 Test loads.
:E
Q.
o..J
W
>
LLJ
o
I
(December 1987
241
~
N
.,,"'0
oCD
(")
»0
DISABLE
ENABLE
CD
-
-
W
f lCD
C
(Hz)
r---..
100
VI
"-
""'-,-
~~
'-"
typ
jV
16
'-,
typ
//
/,/ /
'\.
/
~
.~'
/~
~~
Co (nF)
/
/ /'/
12
'\..
10
0,1
// If /
Ji
~.
8
10
Fig. 20 Display frequency as a function
of RO and CO; Tamb = + 25 oC; VDD = 5 V.
RO = 1 Mn;
- - - - RO=100kn.
V
o
4
6
8
VDO (V)
Fig. 21 Supply current as a function
of supply voltage.
- - - T amb = -40 oC;
- - - - T amb = + 25 oC;
- . - . - T amb = + 85 °C.
1
(DeCember 1987
243
l__~~
PCF21XX
FAMILY
7Z866951
,\
(mA)
\ \ '.
1,5
\
\
typ
"
" -.
\\~ ~ r--- r----_ ~ ~. t-..
r-... • ...;,
-r--..: r-
o
14
typ
~, 1' ... '-.
typ
o
- -I
=
-
-
RS-
I
10
Rsp
6
8
Fig. 22 Output resistance of backplane
and segments.
- - - ' Tamb = -40 oC;
- - - - T amb = + 25 oC;
- . - . - T amb = + 85 °C.
December
12
8
4
19871 (
i
II
/
l
VDD(V)
244
,/
16
r--- ......
0,5
7Z866981
18
'DL
/
o
1/
V
V ,.
....
.;'"
/
/
/'
If'
1/
/
./
/
/
4
6
8
VDD (V)
Fig. 23 Output current as a function
of supply voltage (only PCF2112).
- - - T amb = -40oC;
- - - - T amb = + 25 oC;
- . - . - T amb = + 85 DC.
DEVELOPMENT DATA
PCF2201
This data sheet contains advance information and
specifications are subject to change without notice.
LCD FLAT-PANEL ROW/COLUMN DRIVER
GENERAL DESCRIPTION
The PCF2201 is a row or column LCD driver, designed to drive LCD flat-panels at multiplex rates
of up to 1 : 256. The PCF2201 converts serial or parallel 4-bit display data into parallel LCD drive waveforms, capable of driving up to 81 rows or 80 columns of an LCD matrix. The PCF2201 is cascadable,
enabling it to drive any LCD flat-panel matrix. The PCF2201 is controlled by an alphanumeric/graphic
controller.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Row or column drive capability
80 data latches
81 stage bidirectional shift register
81 LCD drive outputs
Proprietary margin control drive output
Low drive impedance
LCD drive voltage of up to 25 V
5 V logic compatibility
High speed operation (4 MHz)
Multiplex rates of up to 1 : 256
Externally adjusted bias voltages
Maximum LCD voltage and VDD may be separated
64/65 pin programmable output operation mode
Low power consumption
Overall flat-panel power consumption minimized
Pin programmable right/left orientation for convenience of flat-panel construction
Optimized pinning for single plane wiring
Space-saving 120-lead Tape-Automated Bonding package
Manufactured in silicon gate CMOS process
PACKAGE OUTLINE
PCF2201V: 120-lead Tape-Automated Bonding (TAB) module (SOT235)
1(
August 1987
245
_P_CF2_201_Jl________
F/Y81
Y1 to Y80
i
80
I I
V1
V2/V3
V4/V5
VEE
1---+
1---+
4-LEVEL DRIVER (x 80)
~
~
4-LEVEL
DRIVER
f----.
ira°
f---
LEVEL SHIFTER (x 80)
f---
M
ITso
VSS
LEVEL
SHIFTER
1
I
RR/ER
CL1
81 STAGE BIDIRECTIONAL
SHIFT REGISTER
RLIEL
t
ir
PCF2201
O
FON
COLUMN MODE DATA PRESENTATION
LATCH (x 80)
ilJ[
DO
D1
D2
D3
>-
DATA
SCRAMBLER
4
cp2
cp1
CL2
~
4
~O~~~E~ J'.T
cp 20
SELECTOR
lis
UP/DOWN COUNTER. CARRY LOGIC
AND CONTROL
•1 i i i
I
I
I
I
SHL
COLI
ROW
PIS
LNG
Fig. 1 Block diagram.
246
August
19871 (
7Z81313.1
l____
LCD flat-panel row/column driver
PC_F_2_2_0_1____
bus level lines
r~--------------JA~------------~
m
I~ "'Z~ O.~ .~:: .l~om~~ww~MN~om~~ww
I.....
~~~~~~~~m~~d~;~~~~~~~~~~~~~~~~~~~~~~
o
m
La
o
Y64
Y63
Y62
Y61
Y60
Y59
Y58
Y57
Y56
Y55
Y54
Y53
Y52
Y51
Y50
Y49
Y48
Y47
Y46
Y45
Y44
Y43
Y42
Y41
Y40
Y39
Y38
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
Y19
Y18
Y17
La
ex)
80
75
70
~
«
c
65
I-
2:
w
:E
(1)
Il.
:.. :
o
..J
PCF2201
~.:
60
W
>
W
C
55
50
45
40
lZB1314.2
m
~~'--------------~yr------------~
bus level lines
(1)
mark orientation
Fig. 2 Pinning diagram.
1(
August 1987
247
~1
_Jl________
__
PC_F22_01
PINNING FUNCTIONS
mnemonic
I/O function
VDD
P
VSS
P
Logic ground (0 V)
V1
P
Most positive LCD supply voltage (~VDD), 'selection level
V2/ V 3
P
Upper non-selection level for row (V2) or column (V3) driver
V4/ V 5
P
Lower non-selection level for row (V5) or column (V4) driver
VEE
P
Most negative LCD supply voltage (-20 V), selection level
Y1 to Y80
a
Liquid crystal driver outputs
CL1
I
Clock for 81 stage bidirectional shift register
Positive supply voltage (5 V)
-Loads parallel data from the data presentation latch and frame control in
column driver mode
Shifts data in row driver mode
Negative edge triggered
CL2
I
Data transfer clock in column driver modes
Data must be valid on the negative edge of CL2
Unused in row driver mode (may be left open)
COL/ROW
I
Column/row driver mode select
pis
I
Parallel/serial mode select for column drivers
Tie to VSS in row driver mode
SHL
I
Shift direction select
DO to D3
I
Data inputs in column driver modes
----
-------
Unused in row driver mode (may be left open)
Filling order:
COL/ROW
pis
SHL
H
L
H
L
D1
D2
D3
L
Y1, Y2, Y3,. unused
unused
unused
H
Y80, Y79, ... (may be left (may be left
open)
open)
DO
(may be left
open)
H
H
L
Y1, Y5, Y9,. Y2, Y6, Y10,. Y3, Y7, Y11,. Y4, Y8, Y12, ..
H
H
H
Y80, Y76, ...
Y79, Y75, .... Y78, Y74, ....
Y77, Y73, .....
Also in the serial column driver mode, a multiple of 4 data bits must always be
transferred. Add dummy bits if necessary
248
'
August
19871 (
PCF2201
LCD flat-panel row/column driver
mnemonic
I/O function
RL/EL
RR/ER
I/O Left/right serial input/outputs in row driver mode, left/right enable input/outputs
in column driver modes
COL/ROW PIS
«
«
Cl
SHL
RL/IT
RR/ER comments
L
L
L
I
a
shift direction:
RL/EL -> RR/ER (Y1 -> F/Y81)
L
L
H
a
I
shift direction:
RR/ER -> RL/EL (F/Y81->Y1)
H
L
L
I
a
RR/ER goes LOW 80 CL2 pulses
after R L/E L
H
L
H
a
I
RL/EL goes LOW 80 CL2 pulses
after R R/E R
H
H
L
I
a
RR/ER goes LOW 20 CL2 pulses
after RL/EL
H
H
H
a
I
R L/E L goes LOW 20 C L2 pu Ises
after RR/ER
I-
In the serial column mode, the device accepts one bit of display data at each CL2
pulse after RL/EL (or RR/ER respectively) goes LOW
When 80 bits of display data have been accepted, the device accepts no further
display data and takes its output RR/ER (or RL/EL respectively) LOW, thereby
enabling the next PCF2201 to accept display data
The sequence is reset when CL 1 is HIGH and CL2 is LOW
I2
w
~
0..
a....I
W
>
W
o
In the parallel column mode, the device accepts one nibble of display data at each
CL2 pulse after RL/EL (or RR/ER respectively) goes LOW
When 20 nibbles of display data have been accepted, the device accepts no further
display data and takes its output RR/ER (or RL/EL respectively) LOW, thereby
enabling the next PCF2201 to accept display data.
The sequence is reset when C L 1 is HI G Hand C L2 is LOW
LNG
I
Length control
COL/ROW
LNG SHL description
valid Yi
undefined Yi
L
L
L
L
L
H
65-bit row mode Y1 ... Y65
operation
Y17 ... Y80, F/Y81
Y66 ... Y80, F /Y81
Y1 ... Y16
L
L
H
H
L
H
81-bit row mode Y1 ... Y80, F/Y81
operation
Y1 ... Y80, F/Y81
-
H
H
L
L
L
H
64-bit column
mode operation
Y1 ... Y64
Y17 ... Y80
Y65 ... Y80
Y1 ... Y16
H
H
H
H
L
H
80-bit column
mode operation
Y1 ... Y80
Y1 ... Y80
-
-
-
In 80/81-bit operation, the device behaves as previously described
In 64/65-bit operation, the device behaves as if all resources have been reduced to
64/65 instances; i.e. 16 outputs (determined by SHL) can no longer be accessed
and should be left open circuit.
1(AUgust
1987
249
_P_CF2_201_Jl_ _ _ _ __
PINNING FUNCTIONS (continued)
mnemonic
I/O function
F/Y81*
a
Frame output in column driver mode
It continuously delivers the select or non-select column driver LCD voltages
depending on the state of the frame control
The frame output is used to blank the flat-panel display margin outside the
actual LCD matrix
Liquid crystal driver output, number 81 in row driver mode
FaN
I
Frame control
Defines the contents of the shift register cell corresponding to F/Y81 in column
driver mode
Tie to VDD or VSS in row driver mode
M
I
Signal to convert LCD drive waveform into a.c.:
M
output level (Yi or F/Y81)
L
L
V2/ V 3
L
L
H
V4/ V 5
L
L
VEE
L
H
H
H
V1
H
L
L
V2/ V 3
H
L
H
V4/ V 5
H
H
H
L
V1
H
H
VEE
COL/ROW
L
n.c.
-
not connected
* Patent application pending.
250
August 1987] (
SR data
note
row driver
column driver
LCD flat-panel row/column driver
l____
P_C_F_22_0_1____
FUNCTIONAL DESCRIPTION
4-level driver
One of the liqu id crystal driver levels (V 1, V 2/V 3, V 4/V 5 and VEE) is output onto lines Y 1 to Y80
and F /Y81 depending on the state of the relevant level shifter.
Level shifter
The level shifter converts logic level driver information into LCD level selection signals. The LCD level
selection signals are dependent on the contents of the 81 stage bidirectional shift register and the state
of signals M and COL/ROW.
81 stage bidirectional shift register
In row driver mode the bidirectional shift register is used for the row line scan. In column driver mode
the bidirectional shift register is used to hold column data until the next line is assembled in the data
presentation latch.
Column mode data presentation latch
The column mode data presentation latch provides temporary storage during transfer of column data
required for the next row.
e:(
le:(
Cl
I-
2
w
Data scrambler
I n serial column data transfer, the data scrambler converts 1-bit data to para"el 4-bit nibbles. Data is
rearranged by the data scrambler according to the orientation (left or right) of the chip, as defined
by pin SHL.
::2:
0..
o--l
Selector
W
The selector generates latch clocks ¢1 to ¢20 for the presentation latch. Selection is determined by the
state of the up/down counter and the carry logic.
>
W
Cl
Up/down counter, carry logic and control
Incoming column data storage locations are determined by the up/down counter making use of enable
lines (RL/EL, RR/ER) and the length control select (LNG). The carry logic inhibits the data transfer
clock (CL2) in inactive column drivers, thereby reducing power dissipation. When data transfer to one
column driver is completed, the subsequent column driver is enabled by the carry logic. The control
part co-ordinates the up/down counter and carry logic, depending upon the condition of the device
(SHL, COL/ROW, pIS, LNG, RL/EL and RR/ER).
1(
August 1987
251
~
___PC_F22_01_Jl_________________
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage
VDD
VSS -0,3 to VSS + 7
V
LCD supply voltage range
VEE
VDD -30 to VDD
V
V1, V2/V3 voltage range (note 1)
Vu
VDD + VEE
-1 toVDD V
2
VEE to V D D + VEE - 1 V
V 4/V5 voltage range (note 1)
2
Input voltage range
(CL 1, CL2, COL/ROW, PIS,
SH L, DO, D1, D2, D3,
RL/EL, RR/ER, LNG, FaN, M)
VI
VSS -0,3 to VDD + 0,3 V
Output voltage range
(RL/EL, RR/ER)
Va
VSS -0,3 to VDD + 0,3 V
Driver output voltage range
(F/Y81, Y1 to Y80)
Vy
VEE -0,3 to VDD + 0,3 V
DC input current
± II
max.
20 mA
DC output current
± 'a
max.
25 mA
VDD, VSS, V1, V2/ V 3,
V 4/V5 or VEE current
± ISUp
max.
20 mA
Power dissipation per package
Ptot
max.
400 mW
Power dissipation per output
Po
max.
100 mW
Storage temperature range
T stg
-65 to + 150 0C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally
safe, it is desirable to take normal precautions appropriate to handling MaS devices (see 'Handling MaS
Devices').
252
August
19871 (
l___
LCD flat-panel row/column driver
PC_F_2_2_0_1_ __
DC CHARACTERISTICS
VSS = 0 V; VOO = 4,5 to 5,5 V;
VEE = 0 to -20 V; VOO ~ V1 ~V2/V3~
VOO + VEE
2
-1 V ~ V4/V5 ~ VEE; fM = 100 Hz
Tamb = -40 to + 85 oC; unless otherwise specified.
symbol
min.
typo
max.
unit
Positive supply
voltage
VOO
4,5
-
5,5
V
Negative LCO supply
voltage
VEE
VOO-25
-
VOO-5
V
fCl1 = fCl2
= 0 Hz; CO L/ROW
=H;M=l;
note 2
1001
-
15
40
JiA
Operating supply
current
COL/ROW = H;
fCl1 = 25 kHz;
fCl2 = 4 MHz;
note 2
1002
-
0,4
1
mA
Operating supply
current
COL/ROW = H;
RL/El = H
(SHl = l) or
RR/ER = H
(SHl = H);
fCl1 = 25 kHz;
note 2
1003
-
50
150
JiA
Operating supply
current
COL/ROW = l;
fCL1 = 100 kHz;
note 2
1004
-
75
200
JiA
Vil
VIH
0
0,7 VOO
-
0,3 VOO
VDO
V
parameter
Static supply current
«
I«
C
IZ
w
:1E
~
o
...I
W
>
W
C
conditions
Logic
Input voltage
lOW
HIGH
Output voltage lOW
to RL/El and
RR/ER
10 = 0 mA
Val
-
-
0,05
V
Output voltage HI G H
to RL/El and
RR/ER
10 = 0 mA
VOH
VOO-0,05
-
-
V
Output current lOW
to Rl/EI and
RR/ER
VOl=1V
10L
1
-
-
mA
'] (AUgust 1987
253
___PC_F22_01_jl_______________~
DC CHARACTERISTICS (continued)
parameter
conditions
symbol
min.
typo
max.
unit
Output current HIGH
RL/Eland
RR/ER
VOH = VDD-l V
10H
-
-
1
mA
± 1L1
-
1
p.A
CI
-
-
7
pF
± Il2
-
-
2
p.A
RON
-
-
2
kn
Leakage current at
Cll, Cl2, COL/ROW,
PIs' SHl, DO to D3,
RL/El, RR/ER,
lNG, FaN and M
Input capacitance
note 3
LCD outputs
leakage current at
V 1, V2/V3, V4/V5
Resistance ON between
V 1, V2/V3, V4/V5,
VEE and Yl to Y80,
F/Y81
10 = 100 p.A;
VEE = VDD-25 V
note 4
AC CHARACTERISTICS (note 5)
VSS=OV;VDD=4,5to5,5V;
VEE = 0 to -20 V; V D D ;;:. V 1 ;;:. V2/V 3 ;;:.
V
DD +
2
V
EE
- 1 V;;:' V4/V 5 ;;:. VEE;
fM = 100 Hz; see Figs 4 and 5; Tamb = -40 to + 85 oC; unless otherwise specified.
parameter
conditions
Column driver
data transfer rate
Cl2 HIGH time
254
symbol
min.
typo
max.
unit
fCl2
-
-
4
MHz
-
-
ns
tCl2H
100
CL2 LOW time
tCL2L
100
-
-
ns
Cl2 rise time
tCL2r
25
ns
tCL2f
-
-
Cl2 fall time
-
25
ns
Row driver clock rate
fCL1
-
-
100
kHz
Cll HIGH time
tCL1H
275
-
-
ns
Cll LOW time
tCll L
5
-
-
p.s
CL1 rise time
tCll r
-
-
50
ns
Cll fall time
tCllf
-
-
50
ns
August
19871 (
PCF2201
LCD flat-panel row/column driver
AC CHARACTERISTICS (continued)
parameter
symbol
conditions
min.
typo
max.
unit
--------
Column data set-up time
~
W
C
COL/ROW = H
--
Column data hold time
COL/ROW
Row data set-up time
COL/ROW
Row data hold time
tsuc
50
-
-
ns
=
H
tHDC
30
-
-
ns
=
L
tSUR
200
-
ns
COL/ROW
=
L
tHDR
0
-
-
Enable HIGH
to CL2 set-up time
COL/ROW
=
H
tECH
90
-
-
ns
Enable LOW
to CL2 set-up time
COL/ROW
=
H
tECL
85
-
-
ns
Propagation delay
to enable HIGH
COL/ROW = H
tpEH
-
-
185
ns
Propagation delay
to enable LOW
COL/ROW = H
tPEL
-
-
140
ns
CL2 to CL 1 time
COL/ROW
=
H
tCL21
50
-
-
ns
CL 1 to CL2 time
COL/ROW
=
H
tCL 12
50
-
-
ns
Overlap time of
CL2 = LOW and
CL1 == HIGH
COL/ROW
=
H
tov
275
-
-
ns
Propagation delay HIGH
to RL/EL, RR/ER
COL/ROW
=
L
tpLH
20
-
200
ns
Propagation delay LOW
to RL/EL, RR/ER
COL/ROW = L
tPHL
20
-
200
ns
Propagation delay
to Y1 ... Y80, F/Y81
VEE = VDD
-20V
tpy
-
-
3
/lS
--
--
ns
Notes to characteristics
2. Outputs open, inputs at VSS or VDD.
3. Periodically sampled, not 100% tested.
4. Outputs measured one at a time.
5. All timing values referred to VIH and VIL levels with an input voltage swing of VSS to VDD'
-
3,6 kO
----c:::J-
I LOAD=100 }lA
-([)-
0,5 VDD
(2%)
Y1 ..... Y80,F/Y81
RL!EL (SHL=H)
7Z81315
RR/ER (SHL=L)
Fig.3 Test loads.
'1 (
Augus' 1987
255
N
0'1
0')
~
-u
i
()
"T1
I
lJ
I\)
I\)
1
fCl2
tCl2f
o.......
.1
Cl2
0, 7V oo
0, 3V OO
00,01,02,03
0,7V OO
0, 3V OO
RLla. (SHl=l)
or RR/ER (SHl=H)
(input)
0,7V OO
0,3V OO
0,7V OO
0,3V OO
ell
RR/ER (SHl=l)
or RLla. (SHl =H)
(output)
0,7V OO
0,3V OO
M
1l.
0,7V OO
0,3V OO
t=t~~/
*
tpy
YlroY80.~Y81 ~~~~~~~~~~~~~~~~~~~~~~~~~-~
~00-%E=20~
~~
t
Fig. 4 Column driver timing waveforms.
~:~
7281316.1
DEVELOPMENT DATA
r-
o
o
.....
i:ii'
r+
'l!J
II)
::I
~
a
~
no
1
10(
fCU
-I
C
3
tCL 1f
tCL 1L
tCL1r
::I
o, 7V OO
CL1
O, 3V OO
RUEL (SHL==L)
orRR/ER (SHL=H)
(input)
~.
o, 7VOO
7f"-'r'-_ _ _ _ _....J
"'1<
~
O, 3V OO
tpLH,tpHL
..
RR/ER (SHL=L)
or RUEL (SHL=H)
-I
.,. ~
O,7V O O
.,. ~"-_ _ __
O, 3V OO
(output)
O,7V O O
O,3V O O
M
I.0(
10(
tpy
tpy
~
Yl to Y80, F!Y81 - - - - - - - - - - - - - - - - - - - - - - . .
*
(VOO-VEE =20V)
l T
t
»c
to
~::~
7ZB1317.1
Fig. 5 Row driver timing waveforms.
C
~
co
ex>
~
"1J
()
"'Tl
I\)
I\)
o......
N
(J1
"
~__PCF_220_1_Jl_________________
APPLICATION INFORMATION
Generation of LCD bias levels
Optimum contrast for LCD flat-panels is achieved when the bias levels are selected using the formulae
in Table 1. The multiplex rate is denoted by the variable n (n ~ 9). Vth is defined as the LCD threshold
voltage, typically where the LCD exhibits approximately 10% contrast. The ratio of the 'ON' voltage to
the 'OFF' voltage is discrimination (D) and is a measure of the flat-panel contrast at a given multiplex rate.
Table 1 LCD flat-panel bias levels for optimum contrast (V op
V2
-
=
Vop
yn
V3
---
-
yn+1
Voff(rms)
Vop
=
Vop
0=
Von(rms)
=
Voff(rms)
258
August
19871 (
=
yn-1
yn+ 1
V4
-
Vop
= V1
- VEE)
2
=
V5
---
-
yn+1
2 (yn -1)
Von(rms)
yn(yn+ 1)2
Vop
vIn=1
Vop
yn-1
Vth
1
=
yn+ 1
Vop
=
=
j~
+
yn-1
n (yn+ 1)
yn+1
..j2
(1
-llyn
PCF2201
LCD flat-panel row/column driver
The intermediate bias levels are generated by a resistive divider (see Fig. 6). Capacitors (C) are used to
smooth out switching transients. Considerable power consumption may result by using this arrangement
when driving a large LCD flat-panel, because of the low impedance of the resistive divider.
V1
t
vss
c
]R
C
}
to other column
driver PCF2201s
V2
'-H
lOC')
H~l
V3
-~
COL/ROW
h/n-3)R
~
~~
>
UJ ::::::::
'UJ »
>
R
I
V4
II
VSS
PCF2201
7Z81318.2
[ R
~
e:(
VS
II
l-
e:(
o
R[
IZ
II
w
::2E
I
R
VEE
VDD
r:
VEE
D-
O
..J
V2/V3
V4/VS PCF2201
W
>
W
o
VEE
'----v--"
t 0 ot her r0 w
driver PCF2201 s
COL/ROW
~
Vss
Fig.6 Unbuffered LCD biasing level generation.
I
(August 1987
259
___P_CF2_20_1_Jl_________________
A better solution for LCD flat-panel biasing is presented in Fig. 7. The operational amplifiers provide
low impedance biasing with a low power consumption. The fairly high impedance which can be
implemented at the resistive divider, helps maintain low power consumption. One diode voltage drop
seperates V1 from VDD to compensate for the limited common mode voltage range (V+ -1,5 V) when
the operational amplifiers are powered between VDD and VEE.
voo
c
+"
vss
R!
R
-3)R!
~
~
~
R~
R
to other column
driver PCF2201 s
:;: c
J
}
V1
l()C")
»
UJ ............
UJ' > »
0
0
>
L...-
COL/ROW
1V3
PCF2201
vsslZ81319.1
1V4
1V5
VEE
1
Voo
VEE
V1
V2/V3
V4/V5
PCF2201
VEE
'---y----/
to other row
driver PCF2201s
~COL/ROW
VSS
Fig. 7 Buffered LCD bias level generation.
Typical LCD flat-panel application
Alphanumeric/graphic computer terminals with LCD flat-panel screens using 200 x 640 dots are very
popular. The format of 200 x 640 is compatible with the standard 25 lines by 80 characters at
8 x 8 dot character fonts. Fig. 8 gives a possible circuit using 19 PCF2201's, with upper and lower half
screens used for good contrast. The use of half screens reduces the multiplex rate to 1 :100 (Fig. 9 gives
the timing information).
260
August
19871 (
DEVELOPMENT DATA
f~:
ALPHANUMERIC I
GRAPHIC
CONTROLLER
L-______
OLO,OL1,
,OL2,OL3
·"
4
I II
I I ;
I
~
1
°i \L
M CL1 CL2
RL/EL
RR/ER!r'
VOO'- LNG
PCF2201
PIS
,VOO
_~
-~
r
I
SHL
(#1)
VOO' - COL/ROW
I
FON
J
VOO-
~
PCF2201
(#2)
IIf
~Voo
. . Vi
Voo-
~
PCF2201
(#7)
VOO-
VOO-
80].,.
I
~~
8~Yi
8~Yi
r.,Vo o
~
III
V00i=
PCF2201
(#8)
r-
(")
o
.....
~voo
VOO-
-g
:::I
~
8~Yi
a
:e
~
t
Dr
~
8E"
Yi
3
~,.1
:::I
>0
~
~.
UPPER HALF 100 x 640
f
~
Yi
t= ~~-°
>0
Voo
f1C
LOWER HALF 100 x 640
V1
Iffi
~>-~
RI
tj
4}-
~
z
2
dl-"~CI...J:J~
~
d.
/Y;
I
~~,.1
of'
~
c
(Q
c
COL/ROW
VOO
PCF2201
SHL
VOO
~
(#1)
LNG
VOO
VOOP/S_
RLia 1---------1
RR/ER
Vi
Dj CL2 CL1 M
~FON
"
LLl
~
.....
VEE
co
(Xl
"-J
VOO
Vito
VEE
Vito
PCF2201
(#2)
Yi
80
~
voo
VOO
VOO
t I I
~VOO
VOO~
VOO
VOO
t
-,
~r~(4------~--------~---see Fig. 9 for waveforms
L-. _ _
}
'-~
Fig. 8 LCD flat-panel with 1: 100 multiplex rate in upper and lower half screens.
N
CD
....
-u
7Z81321.2
()
II
I\)
I\)
o
~
N
0')
N
-0
()
.."
I\)
I\)
»c:::
to
C
~
co
ex)
-....J
I
CL1~
_________
:1
CL2lJLSU1...JL ___
20
121
I
---1 : (# 1)
RR/ER ---1 i (#2)
I
RRIER ---1 : (#7)
I
R
141
140
1141
160
:
=>K=>C>Oc --- - ~ --- - =>e>oofc>c ------- ---- ~ ---- =:xx:::>et=
I
RR/ER
y.
I
JLSLI1.Jl.SLr1J ___ JlS1..Sl..S1SL. ____________ .I1.SLfULJLSl.. ___ ~
I
RR/ER
40
....L
:
I
~
I
DUO, DU3
o
I
M~
II:I (# 8)
I
-n
I
I
r-+--
I
I
I
I
I
----------~
i
r-r-
---------
I
i
t
:
:
:
:
I
I
I
!
I
:
I
i
________
(horizontal scan)
Ii
----+:- - - - :
I
:
I
-Ll
I
_______ -1
I
I
I
I
I
M~---
timing. lor lirst row
(
k
I
I
l
I
:
I
I
rr-
-~__________:
:
:
I
I
I
f
:
----1'
I
I
I
-----i./
I
!
:
11
2
3
4
5
99
100:
CL1 ~ ___ ~ ___ ~ ___ ~ ___ ~ ___ ~ ______________ ~ ___ ~
I
-1U1J1JL ___ .-n.ruuuuL
___ Jll1JlflflJL ___ JlJ1JUUlIL ___ JlJUUlJ1.fL _ - _ JlJ1JUUlIL ______________ J1Jl..flJ1JlJL - - -
CL2:
Y,
R
I
~
=k= ---==k= ---==x= ---==x= ---:::=x= ---==x=--------------==x:= ---==k=
--IL=== i -------==
--============
--- ----IL
I
:
I
timing lor 1 Irame
(vertical scan)
I
---~
I
I
,--
I
I
I_
,,~--il
I
1 Ira me
_~~~~~~~~~~
.1
i
Yi~-------------
R
-J:1
________
__
n_____
I
I
I
I
I
I
I~
I
______________ ~
n
L
_____________
I
I
TZB 1322. 2
I
Fig. 9 Timing for the upper half screen of the LCD flat-panel (Fig. 8).
For the lower half screen, replace RR/ER, DUO, DU1, DU2 and DU3
with RL/EL, DLD, DL 1, DL2, DL3.
r
!tlmtn910r2lrames
(DClree)
l____
LCD flat-panel row/column driver
PC_F_2_2_0_1____
Margin control
The used area of the flat-panel matrix is normally smaller than the LCD glass surface. Connection lines
outside of the used area of the matrix carry row or column LCD signals (see Fig. 10A). This 'null' state
differs slightly in colour from the 'OFF' state pixel for twisted nematic LCD. The structural change
in the margin zone is noticeable.
When a high contrast Philips LCD flat-panel of the supertwisted birefringence effect (SBE) type is
employed, the situation becomes critital. The colour of the 'OF F' state appears blue and-the colour
of the 'ON' state appears grey or white. Therefore inverted information is sent to the display, generating
dark (blue) characters on a light (grey) background. The margin zone is treated as an extension of the
used matrix area (see Fig. 10B), to avoid the margin zone appearing as a dark blue frame. This is
extended out to a region where the LCD glass can be covered up. The additional row requires an
increase in the mu Itiplex rate from n to n + 1, the additional column is realized by the frame output
of the furthest left and right column drivers of the flat-panel. This removes the requirement for
additional column drivers packages to provide margin control.
o
u
N
-'
o
u
o
U
o
~ 8
-~ >- >- >- >- >- >- >- >- >- >-~ >- >- >- >- >- >- >- >- >- I
C"')
7Z96970
N
C"')
C"')
C"')
<:t
C"')
L{)
C"')
(0
C"')
r--
C"')
00
C"')
OJ
C"')
0
<:t
<:t
N
<:t
C"')
<:t
<:t
L{)
<:t
(0
<:t
- - - - - - - - 3,84 mm
Chip area: 25,65 mrn 2
Bonding pad dimensions: 104,urn x 104,urn
Fig. 11 Bonding pad locations.
264
August
19871 (
r-- <:t
00
<:t
OJ L{)
0
<:t
..
l____
LCD flat-panel row/column driver
PC_F_2_2_0_1______
Table 2 Bonding pad centre locations (dimensions in Jim)
All x/v co-ordinates are referenced to the bottom left corner, see Fig. 11.
pad
X
Y
pad
X
Y
D3
D2
D1
DO
RL/EL
1556
1372
1188
1004
820
636
452
268
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
252
428
604
780
956
1132
1308
1484
1660
1836
2012
2188
6526
6526
6526
6526
6526
6526
6526
6526
5982
5806
5630
5454
5278
5102
4926
4750
4574
4398
4222
4046
3870
3694
3518
3342
3166
2990
2814
2638
2462
2286
2110
1934
1758
1582
1406
1230
1054
878
702
154
154
154
154
154
154
154
154
154
154
154
154
Y43
Y44
Y45
Y46
Y47
Y48
Y49
Y50
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Y75
Y76
Y77
Y78
Y79
Y80
F/Y81
VEE
V4/V5
V2/V3
V1
2364
2540
2716
2892
3068
3244
3420
3596
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3684
3580
3396
3212
3028
2844
2660
2476
2292
2108
1924
1740
154
154
154
154
154
154
154
154
702
878
1054
1230
1406
1582
1758
1934
2110
2286
2462
2638
2814
2990
3166
3342
3518
3694
3870
4046
4222
4398
4574
4750
4926
5102
5278
5454
5630
5806
5982
6526
6526
6526
6526
6526
6526
6526
6526
6526
6526
6526
PIS
«
I-
<{
o
I2:
w
:2:
Q.
o
..J
W
>
W
o
LNG
COL/ROW
CL2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
M
CL 1
VDD
SHL
FaN
VSS
RR/ER
1
(AUgUst 1987
265
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
l____
~
~
PC_F_8_2_0_0____
VOICE SYNTHESIZER
GENERAL DESCRIPTION
The PCF8200 is a CMOS integrated circuit for generating good quality speech from digital code with
a programmable bit rate. The circuit is primarily intended for applications in microprocessor controlled
systems, where the speech code is stored separately.
Applications include automotive, telephony, personal computers, annunciators, aids for the handicapped,
and general industrial devices.
Features
•
•
•
•
•
•
•
•
•
Male and female speech with good quality
Speech-band from 0 to 5 kHz
Bit-rate between 455 bits/second and 4545 bits/second
Programmable frame duration
Programmable speaking speed
CMOS technology
Operating temperature range -40 to + 85 0C
Single 5 V supply with low power consumption and power-down stand-by mode
Interfaces easily with most popular microcomputers and microprocessors through 8 bit parallel
bus or 12 C bus
• Software readable status word (parallel bus or 12 C bus)
• BUSY-signal and REO-signal hardware readable
It I nternal low-pass filter and 11-bit D/ A converter
OUICK REFERENCE DATA
parameter
symbol
Supply voltage
Supply current
Supply current (stand-by)
VDD
IDD
IDD(SB)
min.
typo
max.
unit
5
12
1
#
V
rnA
J.lA
Inputs
Input voltage
Input voltage
Input capacitance
0,8
V
V
pF
3,5
o
VDD
0,4
80
V
V
pF
-40
+ 85
°C
2,0
VDD
o
7
Outputs (D5 to D7)
Output voltage high
Output voltage low
Load capacitance
Operating ambient
temperature range
Tamb
# Value not yet available.
PACKAGE OUTLINE
24-lead D I L; plastic (SOT1 01 A).
'1 (JUlY
1986
267
~1
N
i
""0
05 to DO
0
(...
c::
-<
C
co
0)
R/W
0)
Iii
SER/PA
~
13
~
14
~
15
~
9
()
"Tl
())
18 23
-
112
l
~
12 C
17
De/SCL
INTERFACE
r----+
r--
SHIFT
CONTROL
I+-
~ f-
!
REQUEST
CONTROL
~$
OSCI
OSCO
...
END-OFSPEECH
CONTROL
~
'----
POWER
UP/DOWN
CONTROL
,
5-BYTE
INPUT
BUFFER
~
EXCITATION
CHAIN 2
j.-
DECODER
.... 8
...
~
FILTER
DATA CHAIN
3
MULTIPLIERS
L..o..
..
I
,.-
COEFFICIENT
ROM
1+
PHASE
COUNTER
~
PITCH VALUE
AND
PITCH
INCREMENT
VALUE
~
i
~
~
L
1--
PARALLEL/
SERIAL
REGISTER
COEFFICIENT
CHAIN
7
TIMING CHAIN
PLUS
DECODER
CRYSTAL
OSCILLATOR
f-~
SOURCE
GENERATOR
L
1+ -
I+-
f
11
2 MHz
CLOCK
GENERATOR
EXCITATION
CHAIN 1
r---
lo
I-
10
BUSY
r-+
t
1
REQ
STATUS/
COMMAND
REGISTER
STATIC
LATCH
...
..
16
D7/SDA
I\)
o
o
PCF8200
PARALLEL
MODE
INTERFACE
ft
124
Ie
n.c.
Fig. 1 Block diagram.
t-1 r+
DAC
l
15
TEST
I+- ~
..-1-
~
3
~
...
VDD - A
Vref
VSS_A
OUT
Jl
Voice synthesizer
PINNING
PCF8200
voo-o
00
01
02
03
04
05
SCL/06
SOA/07
REO
W
VSS-O
CE
Fig. 2 Pinning diagram.
R/W
7Z97577
e:(
l-
2
c
3
e:(
I-
z
w
:!:
e..
0
.J
w
>
w
c
4
VOO-A
positive supply voltage for OAC output stage
VREF
OUT
speech output
OAC reference voltage input
negative supply voltage for OAC stage
5
VSS-A
n.c.
6
TEST
for normal operation this pin must be grounded (VSS)
7
ascI
oscillator input
8
OSCO
oscillator output
9
SER/PAR
for parallel data bus operation this pin is hard-wired to VOO, or to VSS to
enable the 12 C bus
not connected
10
REQ
status bit indicating request for data
11
BUSY
status indicating synthesizer busy
12
VSS-O
CE
negative supply voltage for digital circuits
chip-enable input
15
R/W
W
write input
16
SOA/07
12 C bus serial data input/output (serial mode)
or parallel data input/output 07 (parallel mode)
17
SCL/06
2
1 C bus serial clock input/output (serial mode)
or parallel data input/output 06 (parallel mode)
18
19
20
21
22
23
05
04
03
02
01
24
VOO-O
13
14
read/write control input
parallel data input/outputs
DO
positive supply voltage for digital circuits
1(JUlY
1986
269
___
PC_F82_00_Jl________________
FUNCTIONAL DESCRIPTION
The synthesizer has been designed for a vocal tract modelling technique of voice synthesis. An excitation
signal is fed to a series of resonators. Each resonator simulates one of the formants 'in the original speech.
It is controlled by two parameters, one for the resonant frequency and one for the bandwidth. Five
formants are needed for male speech and four for female speech. The output of this system is defined by
the excitation signal, the amplitude values and the resonator settings. By periodic updating of all parameters very high quality speech can be produced.
OPERATION
Speech characteristics change quite slowly, therefore the control parameters for the speech synthesizer
can be adequately updated every few tens of milliseconds with interpolation during the interval to ensure
a smooth changeover from one parameter value to the next. In the PCF8200 the standard-frame duration
can be set to 8,8, 10,4, 12,8 or 17,6 milliseconds with the speed-option, speaking speed, in the commandregister.
The duration of each individual speech frame is programmable to be 1,2,3 or 5 times the standard-frame
duration.
00
01
10
11
FD1, FDO
10
8,8
17,6
26,4
44,0
01
10,4
20,8
31,2
52,0
00
12,8
25,6
38,4
64,0
11
17,6
35,2
52,8
88,0
FSO, FS1
ms
ms
ms
ms
Table 1. Frame duration as a function of speed-option (FS1, FSO) and frame-duration (FD1, FDO).
The excitation signal is a random noise source for unvoiced sounds and a programmable pulse generator
for voiced sounds. Both sources have an amplitude modulator which is updated 8 times in one speechframe by linear interpolation. The pitch is updated every 1/8 of a standard frame.
The excitation signal is filtered with a five formant filter for male speech and a four formant filter for
female speech. The formant filter is a cascade of all second-order sections. The control parameters, formantfrequency and formant-bandwidth, are updated eight times per speech frame by linear interpolation.
A block diagram of the formant synthesizer is shown in Fig. 3.
The filter output is upsampled to 80 kHz and filtered with a digital low-pass filter. Before the signal is
digital to analogue converted (DAC), with an 11-bit switched capacitor DAC, the signal is multiplied
with a DAC-amplitude factor. The use of a digital filter means that no external audio filtering is required
for low-medium applications and minimal filtering is required for those applications requiring very high
quality speech.
NOISE
5 FORMANT
FILTER
UPSAMPLED
DIGITAL
FILTER
DAC
7280616
PULSE
GENERATOR
Fig. 3 Block diagram of formant synthesizer.
270
July 1986\ (
SPEECH
OUT
Jl____
y
______
V_oic_es_n_th_es_ize_r_______________________
p_C_F_B_20_0______
DATA FORMAT
Three types of format are used for data transfer to the synthesizer.
DAC-amplitude factor
The DAC-amplitude factor is one byte, which is used to optimize the digital speech signal to the 11-bit
DAC. It is the first byte after a STOP or a BADSTOP or VDD on. Table 2 indicates the amplitude factor.
e:(
le:(
C
I:2
w
byte
01110000
10110000
00110000
11010000
01010000
10010000
00010000
11100000
01100000
10100000
00100000
11000000
01000000
10000000
00000000
11110000
:liE
0..
Table 2 DAC amplitude factor.
o
...J
W
factor
dB
10,88
3,5
10,24
3,25
3,0
9,54
8,97
2,75
7,96
2,5
7,04
2,25
6,02
2,0
1,75
4,86
1,5
3,52
1,25
1,94
1,0
0,00
0,75
-2,50
-6,02
0,5
0,25
-12,04
0,0
HEX code FO is not allowed as a DAC amplitude
>
Start pitch
C
The second byte after a STOP or BADSTOP, or VDD on is the start pitch. It is a one byte start value
for the on-chip pitch-period generator.
W
Frame Data
The frame data is a five byte block which contains the filter and source information:
pitch increment/decrement value
amplitude
frame duration
frequency of 1st formant
frequency of 2nd formant
frequency of 3rd formant
frequency of 4th formant
frequency of 5th formant
bandwidth of 1st formant
bandwidth of 2nd formant
bandwidth of 3rd formant
bandwidth of 4th formant
bandwidth of 5th formant
5 bits
4 bits
2 bits
5 bits
5 bits
3 bits
3 bits
1 bit
3 bits
3 bits
2 bits
2 bit~
2 bits
40 bits
= 5 bytes
The frame-data bits are organized as shown in Fig. 4.
'I (JUlY
1986
271
Jl
PCF8200
07
DO
byte 0
S1
byte 1
F5
S:5
byte 2
FD1
:
byte 3
FDO
byte 4
I
F1
I
I
PI
I
A~
F3 :
I ~3
I
:
S:4
I
I
F2
F4
S2
7Z80617 .2
It is not allowed to set byte
I
a to the hexadecimal value 00.
Fig. 4 Format of frame-date.
CONTROL FORMAT
Command Write
A command write consists of two bytes, and it may occur before a data block. The four bits which can
be written are shown in Fig. 5.
07
DO
byte 0
I
0
0
:
:
0
byte 1
I
1
0
: STOP: M/F :
0
0
0
:
:
0
:
:
0
: FS1
0
0
: FSO
1"00"
I
7Z80618.1
Fig. 5 Control write: first byte fixed, second byte control.
FSO, FS1 speed option
FS1
FSO
a
a
0
1
1
1
speech
speed
standard-frame
duration
100%
145%
123%
73%
12,8
8,8
10,4
17,6
a
1
ms
ms
ms
ms
M/F, male/female option
M/F
= a male quantization table
= 1 female quantLzation table
STOP
STOP
last complete frame with amplitude =
(no excitation signal)
= a if the frame data is not sent within the duration 'of a half
frame, there will be a BADSTOP:
1. REQ = 1 STOP = a
2. Repeat last frame with amplitude
3. BUSY = a
272
a
= 1 stop; repeat
July
19861 (
=a
Jl____
p_C_F_B_20_0______
_______
vo_iC_eS_V"_th_es_ize_r_______________________
Status Read
Three status bits can be read out at any time without a preceding byte (00).
This is shown in Fig. 6.
07
DO
I REo : BUSY :STOP:
x :
x :
x :
x : x
I
7Z80619.2
Fig. 6 Status read.
1
No data required
Synthesizer requesting for new data
1 Busy (an utterance is pronounced)
Oldie, REO will set to 1; the synthesizer is in STOP or BADSTOP mode
The STOP bit is the same as the stop bit written to the
synthesizer during a command write.
STOP = 1, BUSY = 0 stopped by the user.
STOP = 0, BUSY = 0 BADSTOP because the data was not sent in time.
o
BUSY
STOP
~
~
C
IZ
w
~
c..
o
...I
W
After initial power-up the status/command register is set to the following status:
FSO, FS1
M/F
STOP
BUSY
REO
=0
0
0
0
1
Standard-frame duration of 12,8 ms
Male quantization table
Idle
No data required
>
INTERFACE PROTOCOL
C
Data can be written to the synthesizer when REO = 0 or, when REO = 1 and BUSY
shows the interface protocol of the synthesizer.
W
=
O. Figure 7
In parallel mode the synthesizer is activated by sending the DAC-amplitude factor. In serial mode the
DAC-amplitude factor can be sent as soon as the synthesizer is powered-up.
The 12C transmitter/receiver will then acknowledge. When the request for the pitch-byte occurs the
byte must be provided within the duration of a half standard frame. If the byte is not provided in time
a BADSTOP will be generated.
During each data write operation, the status bit REO will be set to '1'.
Within a frame data block, it disappears within a few microseconds, asking for the next byte of that
block. If the bytes of frame data are not provided within the time-duration of a half frame, a BADSTOP
wi II be generated.
12C ADDRESS
On chip there is a 12C slave receiver/transmitter with the address:
7 6 543 2 1 0
1 0 0 0 0 R/W
o0
1(JUlY
1986
273
__PC_F82_00_Jl_ _ _ _ _ _ _ __
POWER UP
The synthesizer will be set to power-up on a parallel-write sequence.
PAR-mode:
SER-mode:
The input-latches are active so they can receive the first byte
The 12 C transmitter/receiver will not acknowledge until the synthesizer has poweredup. To power up the synthesizer a parallel write sequence (F ig. 9) must be made to
the synthesizer by using external logic for the control lines; at least one line must be
toggled, GE, while W= 0 and R/W = 1.
The synthesizer can be set to permanent power-up by hard-wired control pins
(C E = 0, R/W = 1, W = 0).
POWER DOWN MODE
When BUSY = 0 the synthesizer will be set to power-down. In the power-down mode the status/command
register will be retained.
In power-down mode the clock-oscillator is switched off. After initial VOO the synthesizer is in powerdown mode.
HANDLING
All inputs and outputs are protected against electrostatic charge under normal handling conditions.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
274
parameter
conditions
symbol
min.
max.
unit
Supply voltage
any pin with
respect to V SS
VOO
-0,3
7,5
V
Input voltage
any pin with
respect to V SS
VI
-0,3
7,5
V
Output voltage
any pin with
respect to V SS
Vo
-0,3
7,5
V
20
20
mA
mA
D.C. input diode current
VI VOO
-11K
11K
-
D.C. output diode current
Vo < VSS
VO>VOO
-10K
10K
-
-
20
20
mA
mA
Operating ambient
temperature range
Tamb
-40
85
oC
Storage temperature range
T stg
-55
125
oC
July
19861 (
-
PCF8200
Voice synthesizer
CHARACTE R ISTICS
Tamb = -45 to + 85 °C; supply voltage (VOO to VSS)
otherwise specified
parameter
= 4,5 to 5,5 V with
respect to VSS, unless
symbol
min.
typo
max.
unit
VOO
100
IOO(SB)
4,5
-
5,5
-
-
5,0
10
200
-
V
rnA
p.A
VIH
VIL
2,0
0
-
VOO
0,8
V
V
IIR
trf
CI
-
-
10
50
7
p.A
ns
pF
VIH
VIL
2,2
-
0
-
VOO
0,8
V
V
-10
10
50
7
p.A
ns
pF
VOO
0,8
V
V
Supply
Supply voltage
Supply cu rrent
Standby current
Inputs
CE,
R/W,W
Input voltage HIGH
I nput voltage LOW
Input leakage current
Vin = 0 to 5,5 V
Rise and fall times (note 2)
I nput capacitance
w
OSCI
Input voltage HIGH
Input voltage LOW
I nput leakage current
Vin = 0 to 5,5 V
Rise and fall times (note 2)
I nput capacitance
Q.
PARALLEL MODE
W
I nput Characteristics
(DO to 07)
<
I<
C
I:2
~
o
..J
>
W
C
Input voltage HIGH
I nput voltage LOW
Input leakage current
(Vin = 0 to 5,5 V,
output off)
I nput capacitance
-10
-
IIR
trf
CI
-
-
VIH
VIL
2,0
0
-
IIR
CI
-10
-
-
10
7
p.A
pF
VOH
3,5
-
VOO
V
VOL
CL
trf
0
-
-
0,4
80
50
V
pF
ns
VIH
VIL
3,0
0
-
VOO
1,5
V
V
IIR
CI
-
-
10
10
p.A
pF
-
Output Characteristics
(05 to 07 only)
Output voltage HIGH
(IOH = -100 p.A)
Output voltage LOW
(IOL = 3,2 mAl
Load capacitance
Rise and fall times (note 3)
-
SERIAL MODE
Input characteristics
(SOA and SOL)
Input voltage HIGH
I nput voltage LOW
I nput leakage cu rrent
(Vin = 0 to 5,5 V,
output off)
I nput capacitance
-10
-
1(JUlY
1986
275
PCF8200
symbol
min.
typo
max.
unit
VOL
0
-
0,4
V
Crystal frequency
fXTAL
-
6
6,1
MHz
VREF
Reference voltage
VREF
1,9
-
I nput leakage current (active)
IIR
-
5
-
/J.A
VOH
3,5
-
VDD
V
VOL
CL
trf
0
-
-
-
0,4
80
50
V
pF
ns
VOUT
0,66 x VREF
600
1,34 x VREF
-
n
tWR
tDS
tDH
tRD
tDD
200
150
30
200
-
-
tDF
tcs
tCH
0
0
-
tRN
tRV
tRH
0
#(~3)
parameter
Output Characteristics
(SOA only, open drain)
Output voltage LOW
(lOL = 3 mA)
OSCILLATOR
VDD-1,5
1,25
V
Outputs
REQ, BUSY
Output voltage HI G H
(lOH = 100 /J.A)
Output voltage LOW
(IOL = 3,2 mA)
Load capacitance
Rise and fall times (note 3)
-
OUT
Output voltage
Minimum external load
V
Tim ing characteristics
(note 1) (Figs 8 and 9)
Write enable
Data set-up for write
Data hold for write
Read enable
Data delay for read (note 2)
Data floating for read
(note 2)
Control set-up
Control hold
REO new (new byte of the
same speech frame)
REO Valid
REO Hold
-
250
-
-
150
150
-
ns
ns
ns
ns
ns
ns
ns
ns
fJ.S
#
ns
ns
NOTES TO THE CHARACTERISTICS
1. Timing reference level is 1,5 V; supply 5 V ± 10%; temperature range of -40 0C to 85 °C.
2. Levels greater than 2 V for a '1' or less than 0,8 V for a '0' are reached with a load of one TTL
input and 50 pF.
3. Rise and fall times between 0,6 V and 2,2 V levels.
# Values not yet available.
276
1(
July 1988
PCF8200
Voice synthesizer
no
~
«
c
I2:
w
:E
0..
o-I
W
>
W
C
no
7Z80620.2
Fig.7 Interface protocol.
1(JUlY
1986
277
_J
l"""---_ _ _ _ _ _ __
__
PC_F82_00
Timing diagrams
W
The control signals CE, 'R/W and
have been specified to enable easy interface to most microprocessors
and microcomputers. For instance with connection to an MAB8048 microcomputer the R/W and W
inputs can be used as the RD and WR strobe inputs.
CE ='0'
w~
R!W~
NW------------~,,~
___________
7Z80541
Typical connection of control signals.
CE
CE used
as strobe
W='O'
II
P,/W
fi./W used as
re~
strobe
CE='O'
R/W
W
D7
7Z80542
Fig.8 Read timing,
CE
~s~r~~~
W='O'
!
R/W
data
write
REO
7Z80621
Fig. 9 Write timing.
278
July
19861 (
PCF8200
Voice synthesizer
1
ADDRESS
"I
VOICE
ROM
~
DATA
A
DATA
CE, R/W, Iii
MICROPROCESSOR
REQ
BUSY
~
OUT
r-----
PCF8200
SYNTHESIZER
lZ80623.1
Fig. 10 Typical application configuration with parallel interface.
I
ADDRESS
.1
"I
e:(
VOICE
ROM
l-
~
e:(
o
DATA
I2:
...
w
~
0..
"
MICROPROCESSOR
o
..J
12 C
W
>
W
o
OUT
SDA
SCL
r-----
PCF8200
SYNTHESIZER
7Z80622
Fig. 11 Typical application configuration with series interface.
---+---...-.--
Vrefl---.....
47 nF
OUTI----L_r-~-L__r_~~Ir__,
PCF8200
SYNTHESIZER
RL = 25!1
PO=(~~a~W
Fig. 12 An example of an output configuration.
1(
July 1986
279
_ _PC_FB2_00_Jl_ _ _ _ _ _ _ __
PCF8200
PCF8200
OSC
IN
OSC
OUT
n.c.
TTL
clock
Fig. 13 Oscillator clock configurations.
280
July
19861 (
7Z80625
DEVELOPMENT DATA
PCF84CXXX
FAMILY
This data sheet contains advance information and
specifications are subject to change without notice.
FOR DETAILED INFORMATION SEE REVELANT DATA BOOK OR DATA SHEET
SINGLE-CHIP 8-BIT MICROCONTROLLER FAMILY
DESCR IPTION
An advanced CMOS process is used to manufacture the PCF84CXXX microcontroller family. The family
consists of the following devices:
•
•
•
•
PCF84COO
PCF84C21
PCF84C41
PCF84C81
•
•
•
•
PCF84C12
PCF84C22
PCF84C42
PCF84C85
•
•
•
•
PCF84C121
PCF84C230
PCF84C270
PCF84C271
• PCF84C430
• PCF84C470
• PCF84C640
This data sheet describes features of the PCF84CXXX microcontroller family which are common to
several family members. For details on a particular device, consult the relevant data sheet.
All family members have quasi-bidirectional I/O port lines, a single-level vectored interrupt structure,
an 8-bit timer/event counter and on-chip clock oscillator and clock circuits.
These efficient controllers also perform wetl as arithmetic processors. They have facilities for both
binary and BCD arithmetic plus bit-handling capabilities. The instruction set is similar to that of the
MAB8048 and the PCF84CXXX family is very similar to the MAB8400 family.
Features common to all family members are listed below.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit CPU, ROM, RAM, I/O in a single DI L or SO package
1 K,2 K, 4 K or 8 K x 8 ROM; there is also a ROM-less device
64,128 or 256 x 8 RAM
Quasi-bidirectional I/O port lines
Two test inputs: one of which is also an external interrupt input
Single-level vectored interrupt structure
8-bit programmable timer/event counter
Clock frequency range: 100 kHz to 10 MHz
Over 80 instructions (similar to those of the MAB8048) all of 1 or 2 cycles
Single supply voltage (2,5 V to 5,5 V)
STOP and IDLE modes
Power-on-reset circuit
Operating temperature range: -40 to + 85 oC
PACKAGE OUTLINES
Consult individual data sheets.
1(MarCh
1989
281
l____---
PCF84CXXX
FAMILY
RESIDENT ROM
~
r
INTERNAL
CLOCK
FREQ.
~---::r:--~
TEST'
.;. 30
REGISTER'
REGISTER 2
REGISTER 3
Vref
REGISTER 4
',5V
&
REGISTER 5
DECODER
REGISTER 6
REGISTER 7
RESET
B LEVEL STACK
(VARIABLE LENGTH)
_INT/TO
~
POWER {
SUPPLY
VSS
-GND
_TEST,
external
CONDITIONAL _
BRANCH
LOGIC
interrupt
TIMER
FLAG
CARRY
OPTIONAL SECOND
REGISTER BANK
DATA STORE
ACC BIT
TEST
RESIDENT RAM ARRAY
INTERRUPT INITIALIZE
OSCILLATOR
XTAL
Fig. 1 PCF84CXXX block diagram.
282
August 1988](
lZ22399
____m_L~_j
PCF84COO
PCF84C211C
PCF84C41/C
PCF84C811C
FOR DETAILED INFORMATION SEE RELEVANT DATA BOOK OR DATA SHEET
SINGLE-CHIP 8-BIT MICROCONTROLLERS
WITH 12 C-BUS INTERFACE
DESCRIPTION
An advanced CMOS process is used to manufacture the PCF84COO, PCF84C21/C, PCF84C41/C and
PCF84C81/C microcontrollers. The PCF84C21 C, PCF84C41 C and PCF84C81C operate at a higher
clock frequency. Each device has 20 quasi-bidirectional I/O port lines, a serial I/O interface, a singlelevel vectored interrupt structure, an 8-bit timer/event counter and on-chip clock oscillator and
clock circuits. On-chip RAM and ROM content is as follows:
• PCF84C41 - 128 x 8 RAM, 4 K x 8 ROM
• PCF84COO - 256 x 8 RAM, external program
memory
• PCF84C81 - 256 x 8 RAM, 8 K x 8 ROM
• PCF84C21 - 64 x 8 RAM, 2 K x 8 ROM
These efficient controllers also perform well as arithmetic processors. They have facilities for both binary
and BCD arithmetic plus bit-handling capabilities. The instruction set is similar to that of the MAB8048.
These microcontrollers are members of the PCF84CXXX family. For detailed information, consult the
PCF84CXXX data sheet.
Features
• 8-bit CPU, ROM, RAM, I/O in a single 28-lead
D I l or SO package
• 2K,4 K or 8 K x ROM; also a ROM-less version
• 64,128 or 256 x 8 RAM
• 20 quasi-bidirectional I/O port lines
• Two test inputs, one of which is also the
external interrupt input
• Single-level vectored interrupts: external,
timer/event counter and serial I/O
• 12 C hardware interface for serial data transfer
on two lines (serial I/O data via an existing
port line and clock via a dedicated line)
• 8-bit programmable timer/event counter
• Clock frequency range: 100 kHz to 10 MHz;
C versions: 1 M Hz to 12 MHz
• Over 80 instructions (similar to those of the
MAB8048) all of 1 or 2 cycles
• Single supply voltage (2,5 to 5,5 V)
• STOP and IDLE modes
• Power-on reset circuit
• Operating temperature range: -40 to +85 °c
• High current on Port 1: 10l = 10 mA at
VOL = 1,2 V (all versions except the
PCF84COO).
For following sections see PCF84CXXX family data sheet
Program memory
Data memory
Program counter stack
IDLE and STOP modes
I/O facilities
Serial I/O
Interrupts
Oscillator
Timer/event counter
Program status word
Program counter
Central processing unit
Conditional branch logic
Test input T1
Power-on reset
I nstruction set
PACKAGE OUTLINES
PCF84C21/41/81 P:
PCF84C21/41/81T:
PCF84COOB
:
PCF84COOT
:
28-lead
28-lead
28-lead
56-lead
DI l; plastic (SOT117).
mini-pack; plastic (S028; SOT136A).
'piggy-back' package (supports up to 28-pin EPROM).
mini-pack; plastic (VS056; SOT190).
1(
March 1989
283
l___~
PCF84COO
PCF84C211C
PCF84C41/C
PCF84C81/C
SERIAL DATA/P2.3
----------,
SCLK
RESIDENT ROM
I
I
2 K BYTES
I
I
Pl.7· P1.0
PO.7·
po.o
4 K BYTES
CLOCK
8 K BYTES
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
REGISTER 6
REGISTER 7
.
8 LEVEL STACK
(VARIABLE LENGTH)
.':'PE
POWER {
SUPPLY
+-iNT/TO
+-TESTl
VSS
-GND
CONDITIONAL + - TIMER
BRANCH
FLAG
LOGIC
+-- CARRY
OPTIONAL SECOND
REGISTER BANK
DATA STORE
+-ACC
ACC BIT
TEST
RESIDENT RAM ARRAY
INTERRUPT INITIALIZE
OSCILLATOR
XTAL
7Z97336.2
Fig. 1 Block diagram.
r---AO-A12 - - - - -
--l
00-07
1
1I PSEN
IDXALE
I OXRO
I
r-------------,
AO-A12
00-07
I
I
I
1
1
I
1
PSEN
1
OXWR
1
I
I
I
I
IL
EXOI~
1
I
1
__ _
I
_ _ _ _ _ _ _ .JI
7Z20149.1
Fig. la Replacement of dotted section
in Fig. 1, for the PCF84COOT
ROM-less version.
284
September
19881 (
Fig.lb Replacement of dotted section
in Fig. 1, for the PCF84COOB
'piggy-back'version.
PCF84C12
PCF84C22
PCF84C42
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
FOR DETAILED INFORMATION SEE REVELANT DATA BOOK OR DATA SHEET
SINGLE-CHIP 8-BIT MICROCONTROLLERS
DESCRIPTION
An advanced CMOS process is used to manufacture the PCF84C12, PCF84C22 and PCF84C42
microcontrollers. Each device has 13 quasi-bidirectional I/O port lines, a single-level vectored interrupt
structure, an 8-bit timer and on-chip clock oscillator and clock circuits. On-chip RAM and ROM content
is as follows:
• PCF84C12 - 64 x 8 RAM, 1 K x 8 ROM
• PCF84C22 - 64 x 8 RAM, 2 K x 8 ROM
• PCF84C42 - 64 x 8 RAM, 4 K x 8 ROM
These efficient microcontrollers also perform well as arithmetic processors. The instruction set is
similar to that of the MAB8048. They have bit handling abilities and facilities for both binary and
BCO arithmetic.
These microcontrollers are members of the PCF84CXXX family. For detailed information, consult the
PCF84CXXX data sheet.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
a-bit CPU, ROM, RAM, I/O in a single 20-lead 01 L or SO package
1 K,2 K or 4 K x 8 ROM
64 x 8 RAM
2 timers (8-bit programmable)
13 quasi-bidirectional I/O port lines
Two test inputs: one of which is also the external interrupt input
Single-level, vectored interrupts: external and timer/event counter
8-bit programmable timer/event counter
Clock frequency range: 100 kHz to 10 MHz
Over 80 instructions (similar to those of the MAB8048) all of 1 or 2 cycles
Single supply voltage (2.5 V to 5.5 V)
STOP and IDLE modes
Power-on-reset circuit
Operating temperature range: -40 to + 85 oC
Program memory
Data memory
Program cou nter stack
IDLE and STOP modes
I/O facilities
Interrupts
Oscillator
Timer/event counters
Program status word
Program counter
Central processing unit
Conditional branch logic
Test input T1
Power-on-reset
PACKAGE OUTLINES
PCF84C12/22/42P: 20-lead 01 L; plastic (SOT146).
PCF84C12/22/42T: 20-lead mini-pack; plastic (S020, SOT163A).
'I (
September 1988
285
l___~_
PCF84C12
PCF84C22
PCF84C42
,---------,
I
f
RESIDENT ROM
I
32
INTERNAL
CLOCK
FREQ.
I
I
I
BYTES
I
DECODE
TIMER/
EVENT
COUNTER
(BI
P1.4-P1.0
PO.7 - PO.O
I
1 1 K , 2 K or 4 K
:
r=§:
r
I
I
HIGHER
PROGRAM
COUNTER
(21
~--,-J
t-=-I_ _ _---,
LOWER
PROGRAM
COUNTER
(BI
PROGRAM
STATUS
WORD
TEST 1
.;. 30
REGISTER 1
REGISTER 2
REGISTER 3
INSTRUCTION
REGISTER
Vref
1,5V
REGISTER 4
&
REGISTER 5
DECODER
REGISTER 6
REGISTER 7
RESET
8 LEVEL STACK
(VARIABLE LENGTHI
-iNT/TO
~
POWER {
SUPPL Y
_TEST 1
external
interrupt
VSS
-GND
CONDITIONAL _
BRANCH
LOGIC
-
OPTIONAL SECOND
REGISTER BANK
TIMER
FLAG
CARRY
DATA STORE
_ACC
ACC BIT
TEST
RESIDENT RAM ARRAY
INTERRUPT INITIALIZE
OSCILLATOR
XTAL
Fig. 1 Block diagram.
286
September 1988
1(
lZ96218.4
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
I~
PCF84C85
~
FOR DETAILED INFORMATION SEE REVELANT DATA BOOK OR DATA SHEET
SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 32 I/O LINES
DESCRIPTION
The PCF84C85 microcontroller is manufactured in CMOS, and is designed to be an efficient controller
as well as an arithmetic processor. The instruction set is based on that of the MAB8048 and is software
compatible with the PCF84CXX family. The PCF84C85 has two additional derivative ports and the
microcontroller has bit handling abilities and facilities for both binary and BCD arithmetic.
For detailed information on the PCF84CXX see the "Single-chip 8-bit Microcontrollers" user manual.
Features
• 8-bit CPU, ROM, RAM, I/O in a single 40-lead DI L or mini-pack package
•
•
•
•
•
•
•
•
•
•
•
•
•
8 K ROM
256 RAM bytes
32 quasi-bidirectional I/O port lines
Two test inputs: one of which is also the external interrupt input
Single-level vectored interrupts: external, timer/event counter, serial I/O
12 C hardware interface for two-line serial data transfer
(serial I/O data via an existing port line and clock via a dedicated line)
8-bit programmable timer/event counter
Clock frequency 100 kHz to 10 MHz
Over 80 instructions (based on MAB8048) all of 1 or 2 cycles
Single supply voltage from 2,5 V to 5,5 V
STOP and IDLE mode
Power-on-reset circuit
Operating temperature range: -40 to +85 oc
PACKAGE OUTLINES
PCF84C85P: 40-lead DI L; plastic (SOT129).
PCF84C85T: 40-lead; mini-pack (VS040; SOT·158).
1
(APril 1987
287
N
co
co
r---------,
I
I
SCLK
(pin 38)
po. 0- PO. 7
Pl.0-P1. 7
DPO. 0 - DPO. 7
RESIDENT ROM
I
»
~
()
I
I
I
-g.
00
DECODE
01
L:O"'L.-_-_-_....,X~----'
co
00
-...J
SERIAL
INPUTI
OUTPUT
INTERNAL
CLOCK
FREQ.
SIO
inter.
+30
TEST 1
REGISTER 1
REGISTER 2
REGISTER 3
I+-
REGISTER 4
Vref
1,5V
REGISTER 5
REGISTER 6
REGISTER 7
8 LEVEL STACK
(VARIABLE LENGTH)
RESET
POWER
SUPPLY
{
+-INT/TO
~
VSS
_
GND
+ - TEST 1
external
interrupt
CONDITIONAL I+- TIMER
BRANCH
FLAG
+ - CARRY
LOGIC
OPTIONAL SECOND
REGISTER BANK
DATA STORE
:+-ACC
I.
ACC BIT
TEST
lZ96650
RESIDENT RAM ARRAY
INTERRUPT
INITIALIZE
-0
()
"'TI
00
1 8 K BYTES
CLOCK
DP1. 0- DP1. 6
OSCILLATOR
XTAL
Fig. 1 Block diagram.
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
~
~
l____
P_C_F_85_6_6______
UNIVERSAL LCD DRIVER FOR LOW MULTIPLEX RATES
GENERAL DESCRIPTION
The PCF8566 is a peripheral device which interfaces to almost any liquid crystal display (LCD) having
low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to
four backplanes and up to 24 segments and can easily be cascaded for larger LCD applications. The
PCF8566 is compatible with most microprocessors/microcontrollers and communicates via a two-line
bidirectional bus W~ C). Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex
drive modes).
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single-chip LCD controller/driver
Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing
Selectable display bias configuration: static, 1/2 or 1/3
Internal LCD bias generation with voltage-follower buffers
24 segment drives: up to twelve 8-segment numeric characters; up to six 15-segment alphanumeric
characters; or any graphics of up to 96 elements
24 x 4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
LCD and logic supplies may be separated
2,5 V to 6 V power supply range
Low power consumption
Power-saving mode for extremely low power consumption in battery-operated and telephone
applications
12 C bus interface
TTL/CMOS compatible
Compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers
May be cascaded for large LCD applications (up to 1536 segments possible)
Cascadable with the 40 segment LCD driver PCF8576
Optimized pinning for single plane wiring in both single and multiple PCF8566 applications
Space-saving 40-lead plastic mini-pack (VSO-40; SOT-158A)
No external components required (even in multiple device applications)
Manufactured in silicon gate CMOS process
PACKAGE OUTLINES
PCF8566P: 40-lead DI L; plastic (SOT129),
PCF8566T: 40-lead mini-pack (VS040; SOT158A),
1
(December 1987
289
~
o
""tJ
()
BPO BP2 BP1 BP3
o
CD
SO
"'T1
S23
ex>
(')
01
CD
3
0-
~
+13 +14 +15 + 16
VDD
I
5
R~
co
CX)
-.....J
RF
+17
I~
] GENERATOR
m
m
40+
DISPLAY SEGMENT OUTPUTS
it
I
LCD
VOLTAGE
SELECTOR
~~
R
VLCD 12
W
f-
r-
BACKPLANE
OUTPUTS
--------
I
DISPLAY LATCH
I
SHIFT REGISTER
I
lr
~
PCF8566
-CLK ~
- .;..
t
OSC
-
VSS
-
SCL
SDA
~
f+-
TIMING
SYNC
t
t
OSCILLATOR
DISPLAY
CONTROLLER
INPUT
BANK
SELECTOR
POWERON
:+RESET
COMMAND
DECODER
t>
DISPLAY
RAM
24 x 4 BITS
1(.
DATA
POINTER
¢=
Si
r-"-
2
INPUT
FILTERS
~
12 C BUS
--.
CONTROLLER
OUTPUT
BANK
ISELECTOR
~
~
1
~
1
k
BLINKER
:~
"
SUBADDRESS
COUNTER
7
10
I
AO
SAO
8
A1
9
A2
7Z97485
Fig. 1 Block diagram.
l____
Universal LCD driver for low multiplex rates
P_C_F8_5_6_6______
PINNING
523
SDA
12C bus data input/output
2
SCl
12C bus clock input/output
3
SYNC
cascade synchronization input/output
ClK
external clock input/output
VDD
positive supply voltage
6
OSC
oscillator input
517
7
8
12C bus subaddress inputs
516
9
AO
A1
A2
10
SAO
12C bus slave address bit 0 input
11
VSS
logic ground
12
VLCD
LCD supply voltage
13
14
15
LCD backplane outputs
LCD segment outputs
521
520
4
519
5
518
515
5AO
1
522
514
PCF8566
513
VLCD
512
BPO
511
16
BPO
BP2
BP1
BP3
l-
BP2
510
0
IZ
BP1
59
17
to
40
SO
to
S23
BP3
58
CL
50
57
51
56
52
55
53 20
54
e:(
e:(
W
~
0
..J
W
>
W
0
7Z97492
Fig.2 Pinning diagram.
I
(December 1987
291
___
PCF_856_6_jl_________________
FUNCTIONAL DESCRIPTION
The PCF8566 is a versatile peripheral device designed to interface any microprocessor to a wide variety
of LCOs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up
to 24 segments. The display configurations possible with the PCF8566 depend on the number of active
backplane outputs required; a selection of display configurations is given in Table 1.
Table 1 Selection of display configurations
active backplane outputs
no. of
segments
7-segment
numeric
14-segment
alphanumeric
dot matrix
4
96
12 digits +
12 indicator
symbols
6 characters +
12 indicator
symbols
96 dots
(4 x 24)
3
72
9 digits +
9 indicator
symbols
4 characters +
16 indicator
symbols
72 dots
(3 x 24)
2
48
6 digits +
6 indicator
symbols
3 characters +
6 indicator
symbols
48 dots
(2 x 24)
24
3 digits +
3 indicator
symbols
1 characters +
10 indicator
symbols
24 dots
1
All of the display configurations given in Table 1 can be implemented in the typical system shown in
Fig. 3. The host microprocessor/microcontroller maintains the two-line 12 C bus communication channel
with the PCF8566. The internal oscillator is selected by tying OSC (pin 6) to VSS. The appropriate
biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VOO, VSS and VLCO) and to the
LCD panel chosen for the application.
12
SDA 1
HOST
MICROPROCESSOR/
MICROCONTROLLER
LCD PANEL
SCL 2
17-40
24 segment drives
13-16
4 backplanes
PCF8566
OSC 6
96
elements)
(up to
7
7Z97493
Fig. 3 Typical system configuration.
292
1(
December 1987
PCF8566
Universal LCD driver for low multiplex rates
Power-on reset
At power-on the PCF8566 resets to a defined starting condition as follows:
1. All backplane outputs are set to V DO,
2. All segment outputs are set to VDD.
3. The drive mode'1 : 4 multiplex with 1/3 bias' is selected.
4. Blinking is switched off.
5. I nput and output bank selectors are reset (as defined in Table 5).
6. The 12C bus interface is initialized.
7. The data pointer and the subaddress counter are cleared.
Data transfers on the 12C bus should be avoided for 1 ms following power-on to allow completion of the
reset action.
LCD bias generator
The full-scale LCD voltage (V op ) is obtained from VDD - VLCD' The LCD voltage may be temperature
compensated externally through the V LCD supply to pin 12. Fractional LCD biasing voltages are obtained
from an internal voltage divider of three series resistors connected between V D D and V LCD. The centre
resistor can be switched out of circuit to provide a % bias voltage level for the 1 : 2 multiplex configuration.
«
I-
«
o
I2
w
~
a...
o
..J
LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD according to the selected LCD drive
configuration. The operation of the voltage selector is controlled by MODE SET commands from the
command decoder. The biasing configurations that apply to the preferred modes of operation, together
with the biasing characteristics as functions of Vop = VDD - V LCD and the resulting discrimination
ratios (0), are given in Table 2 .
W
>
W
Table 2 Preferred LCD drive modes: summary of characteristics
Cl
LCD drive mode
LCD bias
configuration
Voff(rms)
Von (rms)
Vop
Vop
static (1 BP)
static (2 levels)
0
D = Von(rms)
Voff(rms)
1
00
1 : 2 MUX (2 BP)
1/2 (3 levels)
0/4
00/4
y'5 = 2,236
1 : 2 MUX (2 BP)
1/3 (4 levels)
1/3
y'5i3
J5 = 2,236
1 : 3 MUX (3 BP)
1/3 (4 levels)
1 : 4 MUX (4 BP)
1/3 (4 levels)
= 0,354
= 0,333
1/3 = 0,333
1/3 = 0,333
= 0,791
= 0,745
y'33/9 = 0,638
yfJ3/3 = 1,915
y'3/3 = 0,577
J3 = 1,732
'I
(December 1987
293
__--PCF-856-6-Jl----------------LCD voltage selector (continued)
A practical value for Vop is determined by equating Voff(rms) with a defined LCD threshold voltage
(Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a
suitable choice is Vop :;;; 3 Vth. _
Multiplex drive ratios of 1 : 3 and 1 : 4 with 1/2 bias are possible but the discrimination and hence the
contrast ratios are smaller (y'3::; 1,732 for 1 : 3 multiplex orV2"1/3::; 1,528 for 1 : 4 multiplex).
The advantage of these modes is a reduction of the LCD full scale voltage Vop as follows:
1 : 3 multiplex (1/2 bias) : Vop ::;y'6V o ff(rms) ::; 2,449 Voff(rms)
1 : 4 multiplex (1/2 bias) : Vop::; ifJ/3 Voff(rms)::; 2,309 Voff(rms)
These compare with Vop ::; 3 Voff(rms) when 1/3 bias is used.
LCD drive mode waveforms
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and
segment drive waveforms for this mode are shown in Fig. 4.
1--
spa
VDD
-ill----...!
Tframe---I
VLCD-VDD -
ru
LCD segments
I'
state 1
(on)
state 2
(off)
VLCDDD
sn+1
V
-
ill
ru
VLCD----(a) WAVEFORMS AT DRIVER
voaP
state 1
At any instant (t):
Vstate 1 (t) = VSn (t) - VBPO(t)
Von(rms) = Vop
-Vop
Vop
Vstate 2(t) =VS n +1 (t) - VBPO(t)
state 2
Voff(rms) = 0 V
a
-Vop
(b)
RESULTANT WAVEFORMS
AT LCD SEGMENT
7Z91465
Fig.4 Static drive mode waveforms: Vop::; VDD - VLCD·
294
December
19871 (
l____
Universal LCD driver for low multiplex rates
PC
__
F8_5_6_6______
When two backplanes are provided in the LCD the 1 : 2 multiplex drive mode applies. The PCF8566
allows use of 1/2 or 1/3 bias in this mode as shown in Figs 5 and 6.
BPO
BPl
<2:
<2:
Sn+l
ICl
IZ
V op - - - -
~
Vop/2---
(a) WAVEFORMS AT DRIVER
w
At any instant (t):
Vstate 1(t) = VSn(t) - VSPO(t)
Il.
o
..J
state 1
W
0----
>
W
-Vop/2 - - -
Cl
-Vop - - - -
Von(rms)
Vstate 2(t) = VSn(t) - VSP1 (t)
Vop - - - -
op
V
state 2
/2
Vop r.-;:.
= TV 10 = OJ91V op
~
0-----
_.J
~
Vop
Voff(rms)
= 4ft = O,354V op
-Vop/2--7Z91477
-Vop - - - (b)
RESULTANT WAVEFORMS
AT LCD SEGMENT
Fig. 5 Waveforms for 1 : 2 multiplex drive mode with 1/2 bias: Vop
= VDD -
1
VLCD.
(DeCember 1987
295
___P_CF_856_6_jl_________________
LCD drive mode waveforms (continued)
LCD segments
VOO----
spa
SP1
VOO-Vop/3 VOO- 2Vop/3 VLCO--VOO
Voo-Vo~/3 VOO-2 Vop /3 -
,/
state 1
~state2
~
VLCO---
~~~-VOP/3-~
VOO- 2Vop/3 VLCO---
~~~-VOp/3
-JLfUl
VOO-2Vop / 3 VLCO
_ _ _--J
(a)
WAVEFORMS AT DRIVER
V op - - - -
At any instant (t):
2Vop/3---
Vstate 1(t) = VSn (t) - VSPO{t)
Vop/3--state 1
a----
Vop k
Von{rms) = -3-V5 = 0,745V op
-Vop/3--- 2Vo p / 3 - - -Vop---V op - - - 2Vop/3--3
Vaop / - - -
state 2
Vstate 2{t) = VSn{t) - VSP1 (t)
II
~
-Vop/3--- 2Vo p / 3 - - -Vop----
II 11
L.J L
L-.J
Vop
Voff{rms) = -3-= O, 333V op
7Z91466
(b) RESULTANT WAVEFORMS
AT LCD SEGMENT
Fig.6 Waveforms for 1 : 2 multiplex drive mode with 1/3 bias: Vop = VDD - VLCD.
The backplane and segment drive wavefront for the 1 : 3 multiplex drive mode (three LCD backplanes)
and for the 1 : 4 multiplex drive mode (four LCD backplanes) are shown in Figs 7 and 8 respectively.
296
Decembe,
19871 (
l__
Universal LCD driver for low multiplex rates
P_C_F_8_56_6_ _
VDD---
BPa
BP1
VDD- Vop/3 VDD-2Vop /3 VLCD--VDD--VDD- Vop/3 VDD-2Vop /3 VLCD--VDD---
BP2
VOD- Vop/3 VOD-2 Vop/3VLCD - - VOD--VDD- Vop/3 VOD-2 Vop/3VLCO - - VDO
Sn+1
VOO-Vop/3 VOD-2Vop /3 VLCD--VOO---
«
~
o
Sn+2
VLCO---
IZ
(a) WAVEFORMS AT ORIVER
V op - - - -
w
:E
At any instant (t):
2Vop/3--
c-
Vstate 1 (t) :::; VSn(t) - VBPO{t)
Vop/3---
O
-oJ
W
VDD- Vop/3 VOO- 2Vop/3 -
state 1
>
o
a
Vop
-Vop/3---
W
Von(rms) :::;
-2Vop / 3 - -Vop----
r.:;;:;
V 33:::; O, 638V op
Vstate 2(t) = VSn(t) - VBP1 (t)
Vop - - - -
Vop
2Vop/3---
Voff(rms)=
Vop / 3 - - -
state 2
9
3:::; O,333V op
a
-Vop/3--- 2Vo p / 3 - -Vop
7Z91478
(b)
RESULTANT WAVEFORMS
AT LCD SEGMENT
Fig.7 Waveforms for 1 : 3 mUltiplex drive mode: Vop:::; VOO - VLCD.
'I
(December 1987
297
~II!
__-P-CF-856-6_JL_________________
LCD drive mode waveforms (continued)
Voo---BPa
VOO-Vop/3 VOO-2 Vop /3 VLCO--VOO----
BP1
VOO-Vop/3VOO-2Vop / 3 VLCO--VOO----
BP2
VOO-Vop/3VOO-2 Vop/3VLCO--VOO----
BP3
VOO-Vop/3VOO- 2Vop/3VLCO--VOO---VOO-Vop/3 VOO-2 Vop/3VLCO--VOO---VOO-Vop/3 -
5 n +1
VOO-2 Vop/3VLCO---
5 n +2
VOO---VOO-Vop/3 VOO-2 Vop /3 VLCO--VDD----
5 n +3
VDO-Vop / 3 VDD-2 Vop/3VLCO--(a) WAVEFORMS AT DRIVER
At any instant (t):
Vop - - - 2Vop / 3 - - -
V state 1(t)
Vop/3---
state 1
-Vop/3---
Von(rms)
-2Vop / 3 - - -Vop----
Vop
3
Vop - - - 2Vop / 3 - - -
a ----
r,:;
V 3 = O,577V op
7Z91479
(b)
RESULTANT WAVEFORMS
AT LCO SEGMENT
Voff(rms)
Vop
=
3= O,333Vop
Fig.8 Waveforms for 1 : 4 multiplex drive mode: Vop = VDD - VLCD.
December 19871 (
=
VSn(t) - VBPl (t)
-Vop/3---2Vop / 3 - - -Vop - - - -
298
=
V state 2(t)
Vop/3---
state 2
=
VSn(t) - VBPO(t)
a----
Universal LCD driver for low multiplex rates
PCF8566
Oscillator
The internal logic and the LCD drive signals of the PCF8566 or PCF8576 are timed either by the
built-in oscillator or from an external clock.
The clock frequency (fCLK) determines the LCD frame frequency and the maximum rate for data
reception from the 12 C bus. To allow 12 C bus transmissions at their maximum data rate of 100 kHz,
fCLK should be chosen to be above 125 kHz.
A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC
state.
Internal clock
When the internal oscillator is used, OSC (pin 6) should be tied to VSS. In this case, the output from
CLK (pin 4) provides the clock signal for cascaded PCF8566s and PCF8576s in the system.
External clock
The condition for external clock is made by tying OSC (pin 6) to VDD; CLK (pin 4) then becomes the
external clock input.
Timing
W
o
The timing of the PCF8566 organizes the internal data flow of the device. This includes the transfer of
display data from the display RAM to the display segment outputs. In cascaded applications, the
synchronization signal SYNC maintains the correct timing relationship between the PCF8566s in the
system. The timing also generates the LCD frame frequency which it derives as an integer multiple of
the clock frequency (Table 3). The frame frequency is set by MODE SET commands when internal
clock is used, or by the frequency applied to pin 4 when external clock is used.
Table 3 LCD frame frequencies
PCF8566 mode
fframe
normal mode
fCLK/2880
64
power-saving mode
fCLK/480
64
nominal fframe (Hz)
The ratio between the clock frequency and the LCD frame frequency depends on the mode in which
the device is operating. In the power-saving mode the reduction ratio is six times smaller; this allows
the clock frequency to be reduced by a factor of six. The reduced clock frequency results in a significant reduction in power dissipation. The lower clock frequency has the disadvantage of increasing the
response time when large amounts of display data are transmitted on the 12 C bus. When a device is
unable to 'digest' a display data byte before the next one arrives, it holds the SCL line low until the
first display data byte is stored. This slows down the transmission rate of the 12 C bus but no data loss
occurs.
December 1987
299
___P_CF_856_6_Jl________________
Display latch
The display latch holds the display data while the corresponding multiplex signals are generated. There
is a one-to-one relationship between the data in the display latch, the LCD segment outputs and one
column of the display RAM.
Sh itt register
The shift register serves to transfer display information from the display RAM to the display latch while
previous data are displayed.
Segment outputs
The LCD drive section includes 24 segment outputs SO to S23 (pins 17 to 40) which should be connected
directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with the data resident in the display latch. When less than 24 segment outputs are
required the unused segment outputs should be left open-circuit.
Backplane outputs
The LCD drive section includes four backplane outputs BPO to BP3 which should be connected directly
to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode.
If less than four backplane outputs are required the unused outputs can be left open. In the 1 : 3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied
together to give enhanced drive capabilities. In the 1 : 2 mUltiplex drive mode BPO and BP2, BP1 and
BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. I n the
static drive mode the same signal is carried by all four backplane outputs and they can be connected in
parallel for very high drive requirements.
Display RAM
The display RAM is a static 24 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map
indicates the 'on' state of the corresponding LCD segment; similarly, a logic a indicates the 'off' state.
There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between
the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the
24 segments operated with respect to backplane BPO (Fig. 9). In multiplexed LCD applications the
segment data of the second, third and fourth column of the display RAM are time-multiplexed with
BP1, BP2 and BP3 respectively.
display RAM addresses (rows) / segment outputs (5)
display RAM bits
(columns) /
backplane outputs
(BP)
0EO
1 23
4
1
2
3
___
---------
;;19
20 212223
lZ97488
Fig. 9 Display RAM bit-map showing direct relationship between display RAM addresses and segment
outputs, and between bits in a RAM word and backplane outputs.
300
December
19871 (
l____
Universal LCD driver for low multiplex rates
P_C_F_8_56_6______
When display data are transmitted to the PCF8566 the display bytes received are stored in the display
RAM according to the selected LCD drive mode. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Fig. 10; the RAM filling organization depicted
applies equally to other LCD types.
°
With reference to Fig. 10, in the static drive mode the eight transmitted data bits are placed in bit of
eight successive display RAM addresses. In the 1 : 2 mUltiplex drive mode the eight transmitted data
bits are placed in bits and 1 of four successive display RAM addresses. I n the 1 : 3 multiplex drive
mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address
left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overriding adjacent data because full bytes are always transmitted. I n the
1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses.
°
Data pointer
e:(
le:(
C
IZ
w
:E
Q..
o
..J
W
>
W
o
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading
of an individual display data byte, or a series of display data bytes, into any location of the display
RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA PO I NTE R
command. Following this, an arriving data byte is stored starting at the display RAM address indicated
by the data pointer thereby observing the filling order shown in Fig. 10. The data pointer is automatically incremented according to the LCD configuration chosen. That is, after each byte is stored, the
contents of the data pointer are incremented by eight (static drive mode), by four (1 : 2 multiplex
drive mode), by three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex drive mode).
Subaddress counter
The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed
to take place only when the contents of the subaddress counter agree with the hardware subaddress
applied to AD, A 1 and A2 (pins 7,8, and 9). AD, A 1 and A2 should be tied to VSS or VDD. The
subaddress counter value is defined by the DEVICE SELECT command. If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also incremented
when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded applications.
When a series of display bytes are being sent to the display RAM, automatic wrap-over to the next
PCF8566 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is
successful even if the change to the next device in the cascade occurs within a transmitted character.
'I
(December 1987
301
~
N
,-------
S"+2£DB
o B/S"
BP~fFV
-- - -
g
S~+7
C
0'1
Sn+6-~ OOP
bit/ 0
BP 1
2
3
- ---
1:2
multiplex
SoU
S"+,~b
S"+29
BPOR
s:::'fEB,s"
BP0[J]
-
BP1
Sn+3-~L...C)op
1:3
~
'TI')
9
multiplex
~~
t1
9
e
multiplex
BP~
OP
Sn+1---
- --
)
BPlBJ
'-
c"<:)oP
---
n+1 n+2 n+3 n+4 n+5 n+6 n+7
-c
x
x
x
b
x
x
x
n
f
a
b
x
x
BP3
~
-
9
n
x
x
x
d
x
x
x
9
x
DP
X
x
msb
Isb
I c Ib Ia! fig Ie Id IDP
X
- --
-- - - - - - - - - - -
d
DP
msb
Isb
I alblflglelcldlDp
X
x
----------
------ - - - - - f
e
x
x
a
d
- ---
msb
Isb
I b IDP Ic Ia Idig Ifie
----------------
n+1
n
- - -
----- - - - - - - - - - - - - - - -
--- -
9
e
x
x
x
n+1 n+2
bit/ 0 a
BP 1 c
2 b
3 DP
---- -
f
x
x
x
e
c
x
x
x
x
bit/ 0 b
BP 1 DP
2 c
3 x
-
a
x
x
x
n + 1 n+2 n+3
- ---
b BP'Ift::!)}P2
~
bit/ 0
BP 1
2
3
----
S"~1
1:4
- - - -
n
-
f
e
Isb
I aJclblDPlflelgld
9
d
msb
--------------
-------
-----------------
Fig. 10 Relationships between LCD layout, drive mode, display RAM filling order
and display data transmitted over the FC bus (x = data bit unchanged).
---
--------
-
-
7Z91469
0)
0)
l____
Universal LCD driver for low multiplex rates
P_C_F_8_56_6______
Output bank selector
This selects one of the four bits per display RAM address for transfer to the display latch. The actual
bit chosen depends on the particular LCD drive mode in operation and on the instant in the multiplex
sequence. In 1 : 4 multiplex, all RAM addresses of bit 0 are the first to be selected, these are followed
by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected
sequentially. In 1 : 2 multiplex, bits 0 then 1 are selected and, in the static mode, bit 0 is selected.
The PCF8566 includes a RAM bank switching feature in the static and 1 : 2 multiplex drive modes. In
the static drive mode, the BAN K SE LECT command may request the contents of bit 2 to be selected
for display instead of bit 0 contents. I n the 1 : 2 drive mode, the contents of bits 2 and 3 may be
selected instead of bits 0 and 1. This gives the provision for preparing display information in an
alternative bank and to be able to switch to it once it is assembled.
Input bank selector
The input bank selector loads display data into the display RAM according to the selected LCD drive
configuration. Display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 drive
mode by using the BAN K SE LECT command. The input bank selector functions independently of the
output bank selector.
Blinker
W
o
The display blinking capabilities of the PCF8566 are very versatile. The whole display can be blinked
at frequencies selected by the B LI N K command. The blinking frequencies are integer multiples of the
clock frequency; the ratios between the clock and blinking frequencies depend on the mode in which
the device is operating, as shown in Table 4.
An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the
static and 1 : 2 LCD drive modes and can be implemented without any communication overheads. By
means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks
at the blinking frequency. This mode can also be specified by the BLINK command.
In the 1 : 3 and 1 : 4 multiplex modes, where no alternate RAM bank is available, groups of LCD
segments can be blinked by selectively changing the display RAM data at fixed time intervals.
If the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can
be effectively performed by resetting and setting the display enable bit E at the required rate using the
MODE SET command.
Table 4 Blinking frequencies
blinking mode
normal operating
mode ratio
power-saving
mode ratio
nominal blinking frequency
off
-
-
blinking off
2 Hz
fCLK/92160
fCLK/15360
2
1 Hz
fCLK/184320
fCLK/30720
1
0,5 Hz
fCLK/368640
fCLK/61440
0,5
fblink (Hz)
'I
(December 1987
303
___P_CF_856_6_jl_________________
CHARACTERISTICS OF THE FC BUS
The FC bus is for 2-way, 2-line communication between different ICs or modules. The two lines are
a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated
only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted
as control signals.
SDA --J._-t-_ _ _ _ _
4--~X'_---I-_____ ~
---~
SCL
data line
stable:
data valid
change
of data
allowed
7Z87019
Fig. 11 Bit transfer.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the
data line while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of
the data line while the clock is HIGH is defined as the stop condition (P).
SOA
SCL
---t\. .
C___ ==~---->-------t_r-'-rt_--
-...,!____....
I
I
I
I
I
I
I
\
:5:
L. _ _ _
.J
start condition
;--\
'
/
I
I
'--__- - ' :
I
stop condition
1(
December 1987
I
:
SCL
L. _ _ _ J
Fig. 12 Definition of start and stop conditions.
304
SOA
I
7Z87005
PCF8566
Universal LCD driver for low multiplex rates
System configuration
A device generating a message is a "transmitter", a device receiving a message is a "receiver". The
device that controls the message is the "master" and the devices which are controlled by the master
are the "slaves".
SDA----------~------------~--------------~------------~------------~--
SCL--~------~----~------_+----~r_------~----~------~----~------_+--
7Z87004
Fig. 13 System configuration.
Acknowledge
<:(
le:(
o
IZ
w
:E
0-
o..J
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is not limited. Each byte is followed by one acknowledge bit. The acknowledge bit is a HIGH
level put on the bus by the transmitter whereas the master generates an extra acknowledge related
clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during
the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver
must signal an end of data to the transmitter by not generating an acknowledge on the last byte that
has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable
the master to generate a stop condition .
W
>
W
o
clock pulse for
acknowledgement
start
condition
I
~
I
SCL FROM
MASTER
I
I
I
I
--~
I
DATA OUTPUT
BY TRANSMITTER
1,---.L.--/~X,"-----JK~~J<
s
DATA OUTPUT
BY RECEIVER
/
-~
7 Z87D07
Fig. 14 Acknowledgement on the 12C bus.
I
(December 1987
305
___PC_F85_66_jl________________~
PC F8566 12 C bus controller
The PCF8566 acts as an 12 C slave receiver. It does not initiate 12 C bus transfers or transmit data to an
12 C master receiver. The only data output from the PCF8566 are the acknowledge signals of the selected devices. Device selection depends on the 12 C bus slave address, on the transferred command data
and on the hardware subaddress.
In single device applications, the hardware subaddress inputs AD, Aland A2 are normally left opencircuit or tied to VSS which defines the hardware subaddress O. In mUltiple device applications AD, A 1
and A2 are left open-circuit or tied to VSS or VDD according to a binary coding scheme such that no
two devices with a common 12 C slave address have the same hardware subaddress.
In the power-saving mode it is possible that the PCF8566 is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. If this situation occurs, the PCF8566
forces the SCL line LOW until its internal operations are completed. This is known as the 'clock
synchronization feature' of the 12C bus and serves to slow down fast transmitters. Data loss does not
occur.
Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on
the SDA and SCL lines.
12C bus protocol
Two 12C bus slave addresses (0111110 and 0111111) are reserved for PCF8566. The least-significant
bit of the slave address that a PCF8566 will respond to is defined by the level tied at its input SAO
(pin 10). Therefore, two types of PCF8566 can be distinguished on the same 12C bus which allows:
(a) up to 16 PCF8566s on the same FC bus for very large LCD applications;
(b) the use of two types of LCD multiplex on the same 12C bus.
The 12C bus protocol is shown in Fig. 15. The sequence is initiated with a start condition (S) from the
12C bus master which is followed by one of the two PCF8566 slave addresses available. All PCF8566s
with the corresponding SAO level acknowledge in parallel the slave address but all PCF8566s with the
alternative SAO level ignore the whole 12C bus transfer. After acknowledgement, one or more command
bytes (m) follow which define the status of the addressed PCF8566s. The last command byte is tagged
with a cleared most-significant bit, the continuation bit C. The command bytes are also acknowledged
by all addressed PCF8566s on the bus.
After the last command byte, a series of display data bytes (n) may follow. These display data bytes
are stored in the display RAM at the address specified by the data pointer and the subaddress counter.
Both data pointer and subaddress counter are automatically updated and the data are directed to the
intended PCF8566 device. The acknowledgement after each byte is made only by the (AD, A 1, A2)
addressed PCF8566. After the last display byte, the 12C bus master issues a stop condition (P).
306
December
19871 (
PCF8566
Universal LCD driver for low multiplex rates
acknowledge by
(AO, A1, A2l-selected
PCF8566 only
R/W
sl ave address
r - - - - ' -_ _,
1
acknowledge by all
raddressed PCF8566st
+
v
1 byte
m;;;' 1 bytes
n;;;' 0 bytes
update data pointer
and, if necessary,
subaddress counter
7Z97489.1
Fig. 15 12 C bus protocol.
Command decoder
<
<
C
I-
The command decoder identifies command bytes that arrive on the 12C bus. All available commands
carry a continuation bit C in their most-significant bit position (Fig. 16). When this bit is set, it indicates
that the next byte of the transfer to arrive will also represent a command. If the bit is reset, it indicates
the last command byte of the transfer. Further bytes will be regarded as display data.
IZ
w
:E
11.
o
...J
W
>
W
C
o= last command
1 = commands continue
I I ~ES~ O:F ipC~D~ I
c
msb
Isb
7Z91471
Fig. 16 General format of command byte.
The five commands available to the PCF8566 are defined in Table 5.
' ] (December 1987
307
_Jl_________
__
PC_F85_66
Command decoder (continued)
Table 5 Definition of PCF8566 commands
description
options
command/opcode
Defines LCD drive mode
LCD drive mode
MODE SET
IcI10lLpiEIBIM11Moi
bits M1
static (1 BP)
1 : 2 MUX (2 BP)
1 : 3 MUX (3 BP)
1 : 4 MUX (4 BP)
0
1
1
0
MO
1
0
1
0
Defines LCD bias configuration
LCD bias
bit
0
1
1/3 bias
1/2 bias
display status
B
disabled (blank)
enabled
mode
Defines display status
The possibility to disable the
display allows implementation
of blinking under external
control
E
bit
0
1
normal mode
power-saving mode
Defines power dissipation mode
LP
bit
0
1
Five bits of immediate data .
bits P4 to PO, are transferred
to the data pointer to define
one of twenty-four display RAM
addresses
LOAD DATA POINTER
I CI 01
bits
P4 P3 P2 P1
PO
0 I P4 P3 P2 P1 pol
5-bit binary value of 0 to 23
DEVICE SELECT
bits
I CI1
308
AO
1 o 0lA2 A1 Aol
December
3-bit binary value of 0 to 7
19871 (
A1
A2
Three bits of immediate data,
bits AO to A2, are transferred
to the subaddress counter to
define one of eight hardware
sub add resses
l____
Universal LCD driver for low multiplex rates
P_C_F_8_56_6______
options
command/opcode
description
Defines input bank selection
bit I (storage of arriving display data)
BANK SELECT
ICI1
static
1 : 2 MUX
RAM bit 0
RAM bit 2
RAM bits 0, 1
RAM bits 2, 3
static
1 : 2 MUX
RAM bit 0
RAM bit 2
RAM bits 0, 1
RAM bits 2, 3
1 1 1 Om
0
1
bit
a
Defines output bank selection
(retrieval of LCD display data)
0
1
The BAN K SE LECT command has
no effect in 1 : 3 and 1 : 4 multiplex drive modes
Defines the blinking frequency
BLINK
blink frequency
bits BF 1
BFa
I Cll 1 1 alAIBF1 BFal
off
2 Hz
1 Hz
0,5 Hz
e:(
le:(
o
I2:
w
blink mode
:;:
a..
o
..J
normal blinking
alternation blinking
W
>
W
o
a
0
1
1
0
1
0
1
bit A Selects the blinking mode;
normal operation with frequency
set by bits BF 1, BFO, or
0
blinking by alternation of
1
display RAM banks. Alternation
blinking does not apply in 1 : 3
and 1 : 4 multiplex drive modes
Display controller
The display controller executes the commands identified by the command decoder. It contains the
status registers of the PCF8566 and coordinates their effects. The controller is also responsible for loading
display data into the display RAM as required by the filling order.
1
(December 1987
309
___PC_F85_66_jl________________
Cascaded operation
I n large display configurations, up to 16 PCF8566s can be distinguished on the same 12 C bus by using
the 3-bit hardware subaddress (AD, A 1, A2) and the programmable 12C slave address (SAO). It is also
possible to cascade up to 16 PCF8566s. When cascaded, several PCF8566s are synchronized so that they
can share the backplane signals from one of the devices in the cascade. Such an arrangement is costeffective in large LCD applications since the backplane outputs of only one device need to be throughplated to the backplane electrodes of the display. The other PCF8566s of the cascade contribute
additional segment outputs but their backplane outputs are left open-circuit (Fig. 17).
The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8566s.
This synchronization is guaranteed after the power-on reset. The only time that ·~rYNC is likely to be
needed is if synchronization is accidently lost (e.g. by noise in adverse electrical environments; or by
the definition of a multiplex mode when PCF8566s with differing SAO levels are cascaded). SYNC is
organized as an input/output pin; the output section being realized as an open-drain driver with an
internal pull-up resistor. A PCF8566 asserts the SYNC line at the onset of its last active backplane
signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it
will be restored by the first PCF8566 to assert SYNC. The timing relationships between the backplane
waveforms and the SYNC signal for the various drive modes of the PCF8576 are shown in Fig. 18.
The waveforms are identical with the parent device PCF8576. Casadability between PCF8566s and
PCF8576s is possible, giving cost effective LCD applications.
I I I I I "
I I I I I I I
I I I I I "
LCD PANEL
IVDD
5
~1
~~2
(upto1536
elements)
VlCD
12
I\.
17-40
SYNC 3
24 segment drives
)
V
PCF 8566
ClK 4
r ::t.13-16
OSC 6
7
8
t1
lAO
10
9
11
AO
A2
BP3
(open-circuit)
IVss
VlCD
V DD
1
R<
";~ ~
IVDD
2Cbus
HOST
MICROPROCESSOR!
MICROCONTROllER
1
SCl 2
17-40
SYNC 3
VSS
I\.
24 segment drives-)
PCF8566
ClK 4
~6
13-16
rt' rr"
7
j
VlCD
12
5
SDA 1
8
10
9
11
4 backplanes
BPO to BP3
A2
Fig. 17 Cascaded PCF8566 configuration.
310
December
19871 (
~
/
7Z97486.1
PCF8566
Universal LCD driver for low multiplex rates
For single plane wiring of PCF8566s, see section "APPLICATION INFORMATION",
1
(December 1987
311
l
PCF8566
--------------------------------------------------------------RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage range; see note
VOO
LCO supply voltage range
V lCO
-0,5 to + 7 V
VOO -7 to VOO V
Input voltage range (SCl; SOA;
AO to A2; OSC; ClK; SYNC; SAO)
VSS -·0,5 to VOO + 0,5 V
Output voltage range (SO to S23;
BPO to BP3)
Va
VLCO--0,5 to VOO + 0,5 V
DC input current
± II
max.
20 mA
max.
25 mA
'a
DC output current
±
VDO, VSS or VlCO current
± 100, ± ISS, ± 'LCD
max.
50 mA
Power dissipation per package
Ptot
max.
400 mW
Power dissipation per output
Po
max.
Storage temperature range
100 mW
-65 to + 150 °C
T stg
Note
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be
totally safe, it is advised to take handling precautions appropriate to handling MaS devices (see
'Handling MaS devices').
DC CHARACTERISTICS
VSS
= 0 V; VOO = 2,5 to 6 V; VLCO = VOO
-2,5 to VOO -6 V;
T amb = -40 to +85 oC; unless otherwise specified
i
I
312
parameter
symbol
min.
typo
max.
unit
Operating supply voltage
VOO
2,5
-
6
V
LCO supply voltage
VLCO
VDO -6
-
VOD -2,5
V
Operating supply current
(normal mode) at fClK
= 200 kHz (note 1)
100
-
30
90
/lA
Power-saving mode supply current
at VOO = 3,5 V; VLCO = 0 V;
fCLK = 35 kHz; AO, A 1 and A2
tied to VSS (note 1)
ILP
-
15
40
J.lA
December
19871 (
l___
Universal LCD driver for low multiplex rates
P_C_F_8_5_6_6______
parameter
symbol
min.
typo
max.
unit
I nput voltage LOW
VIL
VSS
-
0,3 VDD
V
Input voltage HiGH
VIH
0,7 VDD
-
VDD
V
Val
-
-
0,05
V
Logic
= a mA
Output voltage HIGH at 10 = a mA
Output voltage lOW at 10
«
I0::(
C
I-
VOH
VDD -0,05
-
-
V
Output current lOW (ClK, SYNC)
at V a l = 1,0 V; V D D = 5 V
10L1
1
-
-
rnA
Output current HIGH (ClK)
at VOH = 4,0 V; VDD = 5 V
10H
-
-
-1
rnA
Output current lOW (SDA; SCl)
at V a l = D,4 V; V D D = 5 V
IOl2
3
-
-
rnA
Leakage current (SAO, ClK, OSC, AO,
A 1, A2, SCl, SDA) at VI = VSS
or VDD
±Il
-
-
1
J1.A
Pull-down current (AD; A 1; A2; ascI
at VI = 1 V and VDD = 5 V
Ipd
15
50
150
J1.A
Pull-up resistor (SYNC)
RSYNC
15
25
60
krl
VREF
-
1,3
2,0
V
Power-on reset level (note 2)
:.-2:
w
Tolerable spike width on bus
tsw
-
-
100
ns
::2:
I nput capacitance (note 3)
CI
-
-
7
pF
Q.
o.-I
W
LCD outputs
W
D.C. voltage component (BPO to BP3)
at CBP = 35 nF
±VBP
-
20
-
mV
D.C. voltage component (SO to S23)
at Cs = 5 nF
±VS
-
20
-
mV
Output impedance (BPO to BP3)
at VlCD = VDD -5 V (note 4)
RBP
-
1
5
krl
Output impedance (SO to S23)
at V LCD = VDD -5 V (note 4)
RS
-
3
7,0
krl
>
C
1
(December 1987
313
_Jl_________
__
PC_F85_66
AC CHARACTERISTICS (note 5)
= 0 V; VOO = 2,5 to 6 V; VLCO = VOO -2,5 to
T amb = -40 to +85 OC; unless otherwise specified
VSS
VOO -6 V;
parameter
symbol
min.
typo
max.
unit
Oscillator frequency (normal mode)
at VOO = 5 V (note 6)
fCLK
125
200
315
kHz
Oscillator frequency (power-saving
mode) at VOO = 3,5 V
fCLKLP
21
31
48
kHz
CLK HIGH time
tCLKH
1
-
-
flS
CLK LOW time
tCLKL
1
-
-
flS
SYNC propagation delay
tpSYNC
-
400
ns
SYNC LOW time
tSYNCL
1
-
-
flS
Driver delays with test loads
at VLCO = VOO -5 V
tPLCD
-
-
30
flS
12 C bus
Bus free time
tBUF
4,7
-
-
flS
Start condition hold time
tHO; STA
4
-
flS
SCL LOW time
-
-
flS
-
flS
-
flS
ns
tLOW
4,7
SCL HIGH time
tHIGH
4
Start condition set-up time
(repeated start code only)
tsu; STA
4,7
Data hold time
tHO; OAT
0
-
Data set-up time
tsu; OAT
250
-
-
Rise time
flS
tr
-
flS
tf
-
-
1
Fall time
300
ns
Stop condition set-up time
tsu; STO
4,7
-
-
flS
Notes to characteristics
1. Outputs open; inputs at VSS or VOO; external clock with 50% duty factor; 12 C bus inactive.
2.
Resets all logic when VOO
< VREF.
3. Periodically sampled, not 100% tested.
4. Outputs measured one at a time.
5. All timing values referred to VIH and VI L levels with an input voltage swing of VSS to VOO.
6. At fCLK
314
< 125 kHz,
December
12 C bus maximum transmission speed is derated.
19871 (
Universal LCD driver for low multiplex rates
ClK
(pin 4)
(pins1,2)
(2%)
(pin 3)
-
I
load
(2%)
6,8 kn
~VDD
(2%)
SOtOS23~
BPOtoBP3 ~
(pins13to16)
SDA SCl
1,5 kn
,
~VDD
3,3 kn
~0,5VDD
SYNC
'i
PCF8566
~25!LA
(pins 17 to 40)
_
Iload"" 15 !LA
7Z97490
Fig. 19 Test loads.
«
«
Cl
IIZ
w
:iE
Q.
o..J
ClK
W
>
W
CI
- 1 - - - - - - - - , - 0,5 V
t
BPO to BP3
SO to S23
(VDD
= 5V)
~_ _ _ _---:-..;;.:0,5V
t
7Z97491
Fig. 20 Driver timing waveforms.
1
(December 1987
315
_Jl_________
__
PCF_856_6
SDA
SCL
-+- tHD;STA - -
SDA
7Z87013.2
tSU;STA
Fig. 21 12 C bus timing waveforms.
Purchase of Philips' 12 C components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system
provided the system conforms to the 12 C specifications defined
by Philips.
316
December
19871 (
tSU;STO
II
7Z24051
40
II
PCF8566
Universal LCD driver for low mUltiplex rates
7Z24052
24
'DO
(j.LA)
I
-40 0 C/
30
0
20
Y
Z
16
V
..,,/ . /~
/85 0 C
~
~v
~
10
o
,/'
8
o
o
4
Voo (V)
8
a
(a) Normal mode; VLCD = V;
external clock = 200 kHz.
/
o
4
Voo (V)
(b) Low power mode; VLCD
external clock = 35 kHz.
8
= a V;
Fig. 22 Typical supply current characteristics.
~
W
8
4
C
~\;:400C
\
\
o
o
25°C
85°C,
4
~ ~ f:::::::-..
- -
'-...
I--
o
4
Voo (V)
8
(a) Backplane output impedance BPO to BP3 (RBP);
VDD = 5 V; Tamb = -40 to + 85°C.
~
o
4
Voo (V)
8
(b) Segment output impedance SO to S23 (RS);
VDD = 5 V.
Fig. 23 Typical characteristics of LCD outputs.
1
(December 1987
317
...cow
0
(')
CD
3
0"
~
.....
I
~~[JI1T~ :::I1IIII
<.0
(Xl
J
SDA
SCl
I
I
I
(")
I ~~~r
CD
-....I
""0
~~~
APPLICATION INFORM ATION
VlCD
I
--S47
S46-
S21ClK
S20S19-
~
Al
AO
A2
SAO
VSS
S12 -
r
,=52'
o
SllS10-
open-circuit
S9 -
BP2
BPl
BP3
-S25
Sl
-S26
S2
-S27
S3
SO - - - - - - - - - - - - - - - - - - - - - - S23
S24 - - - - - - - - - - - - - - - - - - - - - - - -
S47
y----------------------------------------------------~
BACKPLANES
SEGMENTS
Fig. 24 Single plane wiring of packaged PCF8566s.
7Z97487.1
"m
())
01
m
PCF8570
PCF8570C
PCF8571
128 X 8-BIT 1256 X 8-BIT
STATIC RAMS WITH 12 C-BUS INTERFACE
GENERAL DESCRIPTION
The PCF8570, PCF8570C and PCF8571 are low-power static CMOS RAMs. The PCF8570 and
PCF8570C are organized as 256 words by 8-bits and the PCF8571 is organized as 128 words by 8-bits.
Addresses and data are transferred serially via a two-line bidirectional bus (12 C). The built-in word
address register is incremented automatically after each written or read data byte. Three address pins
AO, A 1 and A2 are used for hardware address, allowing the use of up to eight devices connected to the
bus without additional hardware. For system expansion over 8 devices the PCF8570/71 can be used in
conjunction with the PCF8750C which has an alternative slave address for memory extension up to
16 devices.
Features
•
•
•
•
Operating supply voltage
Low data retention voltage
low standby cu rrent
Power saving mode
2.5 V to 6 V
min.1.0V
max. 15 /lA
typo 50 nA
•
•
•
•
Serial input/output bus W C)
Address by 3 hardware address pins
Automatic word address incrementing
8-lead 0 I l package
Applications
• Telephony
• Radio and television
• Video cassette recorder
• General pu rpose
RAM expansion for stored numbers in repertory dialling
(e.g. PC03343 applications)
channel presets
channel presets
RAM expansion for the microcontroller families MAB8400,
PCF84CXX and most other microcontrollers
PCF8570
PCF8570C
PCF8571
WORD
ADDRESS
REGISTER
MEMORY
CELL
ARRAY
AO-+~-------------.
Al-++-----------~
A2-++-----------~
SCL
SDA
CONTROL
~-------+--------~
VDD
VSS
8
4
TEST
PACKAGE OUTLINES
lZ90775.3
Fig.1 Block diagram.
PCF8570/PCF8570C/ PCF8571/P: 8-lead 01 l; plastic (SOT97).
PCF8570/PCF8570C/PCF8571IT: 8-lead mini-pack (S08l; SOT176C)'
1
(March 1989
319
PCF8570
PCF8570C
PCF8571
l
'----------------------------------------------------------------
PINNING
4
5
6
7
1 to 3
AO to A2
VSS
SDA
SCL
TEST
8
VDD
address inputs
negative supply
serial data line \ 12 C-b
serial clock line J
us
test input for test speed-up; must be connected to VSS when not in use
(power saving mode, see Figs 12 and 13)
positive supply
7Z87034.3
Fig.2 Pinning diagram.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
parameter
symbol
min.
max.
unit
Supply voltage range
VDD
-0.8
+8.0
V
Input voltage range
VI
-0.8
VDD+0.8
V
DC input current
± II
-
10
rnA
DC output current
± 10
± IDD; ± ISS
-
10
mA
VDD or VSS current
-
50
mA
Total power dissipation
Ptot
-
300
mW
Power dissipation per output
Po
-
50
mW
Operating ambient temperature range
Tamb
-40
+85
oC
Storage temperature range
Tstg
-65
+ 150
oC
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is good practice to take normal precautions appropriate to handling MaS devices (see
'Handling MaS Devices').
Purchase of Philips' 12C components conveys a license under the
Philips' 12C patent to use the components in the 12C-system
provided the system conforms to the 12 C specifications defined
by Philips.
320
March
19891 (
PCF8570
PCF8570C
PCF8571
128 x 8-bit/256 x 8-bit static RAMs with 12 C-bus interface
CHARACTER ISTICS
VOO
= 2.5 to 6 V;
VSS
= 0 V; Tamb = -40 to +85 oC unless otherwise specified
--
parameter
conditions
symbol min.
typo
max.
unit!
-
6.0
V
Supply
Supply voltage
VOO
2.5
VI = VOO or VSS
fSCL = 100 kHz
100
-
-
200
}lA
fSCL = 0 Hz
Tamb = -25 to + 70 oC
1000
1000
-
-
15
5
}lA
pA
note 1
VPOR
1.5
1.9
2.3
V
Input voltage LOW
note 2
VIL
-0.8
-
0. 3V OO
V
Input voltage HIGH
note 2
VIH
0. 7V OO
-
VOO+0.8
V
Output current LOW
VOL
10L
3
-
-
mA
Leakage current
VI
= VOO or VSS
IILI
-
-
1
JlA
VI
= VOO
± III
-
-
250
CI
-
-
7
Supply current
operating
standby
Power-on reset level
Inputs, input/output SOA
= 0.4 V
I nputs AD to A2; TEST
Input leakage current
or VSS
I nA
Inputs SCL; SOA
I nput capacitance
VI = VSS
pF
LOW VOO data retention
Supply voltage for
data retention
VOOR
1
-
6
V
Supply current
VOOR=1V
100R
-
-
5
}lA
Supply current
VOOR = 1 V;
T amb = -25 to + 70 °C
100R
-
-
2
}lA
100R
100R
-
50
50
400
200
nA
nA
tH02
-
50
-
JlS
Power saving mode
see Figs 12 and 13
Supply current
TEST = VOO;
Tamb = 25 oC
PCF8570/PCF8570C
PCF8571
Recovery time
,
Notes to the characteristics
1. The power-on reset circuit resets the 12 C-bus logic when VOO < VPOR. The status of the device
after a power-on reset condition can be tested by sending the slave address and testing the
acknowledge bit.
2. If the input voltages are a diode voltage above or below the supply voltage VOO or VSS an input
current will flow: this current must not exceed ± 0.5 mAo
I
(MarCh 1989
321
l
PCF8570
PCF8570C
PCF8571
'-------------------------------------------------------~
CHARACTERISTICS OF THE 12C-BUS
The 12C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are
a serial data line (SDA) and a serial clock line (SCl). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated
only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted
as control signals.
SDA ---''---+-_ _ _ _ _
-+-.....JX~--I-__
~
---~
SCL
data line
stable:
data valid
change
of data
allowed
7Z870 19
Fig.3 B it transfer.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-lOW transition of the
data line, while the clock is HIGH is defined as the start condition (S). A lOW-to-HIGH transition of
the data line while the clock is HIGH is defined as the stop condition (P).
SOA
---F\-1
I
SCL
I
I
I
1
:s:
I
L ___
I
..1
start condition
[-;+----
C--~
~
......1 - - - - - ' - - - - -
------'-------+I-J·
I
\
.
;---\
1
'--__. . . J :
/
I
March
19891 (
I
I
I
:
SCL
L _ _ _ .J
stop condition
Fig.4 Definition of start and stop conditions.
322
SOA
I
7Z87005
PCF8570
PCF8570C
PCF8571
128 .x 8-bit/256 x 8-bit static RAMs with 12C-bus interface
System configuration
A device generating a message is a "transmitter", a device receiving a message is the "receiver". The
device that,controls the message is the "master" and the devices which are controlled by the master
are the "slaves".
SDA----------~------------~--------------~------------~------------_4~
SCL--~------_r----~------~------~------+_----~------~----~------~--
7287004
Fig.5 System configuration.
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge
bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge
related clock pUlse. A slave receiver which is addressed must generate an acknowledge after the reception
of each byte. Also a master must generate an acknowledge after the reception of each byte that has
been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse, set-up and hold times must be taken into account. A master
receiver must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH
to enable the master to generate a stop condition.
clock pulse for
acknowledgement
start
condition
I
t
I
SCL FROM
MASTER
I
I
I
I
--~
I
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
~'---.L...-/----JX'--_K~~Y
7
-~
7Z87007
'Fig.6 Acknowledgement on the 12C-bus.
I
(MarCh 1989
323
l
PCF8570
PCF8570C
PCF8571
'--------------------------------------------------------
Timing specifications
All the timing values are valid within the operating supply voltage and ambient temperature range and
refer to VI L and VI H with an input voltage swing of VSS to VDD.
parameter
symbol
min.
typo
max.
unit
SCL clock frequency
fSCL
-
-
100
kHz
Tolerable spike width on bus
tsw
-
-
100
ns
Bus free time
tBUF
4.7
-
/..lS
Start condition set-up time
tsu; STA
4.7
-
/..lS
Start condition hold time
tHD;STA
4.0
-
/..lS
SCL LOW time
tLOW
4.7
-
-
/..lS
-
/..lS
SCL HIGH time
tHIGH
4.0
SC Land SDA rise time
tr
-
SCL and SDA fall time
tf
-
Data set-up time
tsu; DAT
250
1.0
/..lS
0.3
/..lS
-
ns
Data hold time
tHD; DAT
0
-
-
ns
SCL LOW to data out valid
tVD; DAT
-
-
3.4
/..lS
Stop condition set-up time
tsu; STO
4.0
-
-
/..lS
PROTOCOL
SCL
SDA
lZ81193.2
tHD;STA
tSU;DAT
Fig.7
324
March
19891 (
2
1
tHO; OAT
tVD; OAT
C-bus timing diagram.
tSU;STO
PCF8570
PCF8570C
PCF8571
128 x 8-bit/256 x8-bit static RAMs with 12C-bus interface
Bus protocol
Before any data is transmitted on the 12 C-bus, the device which should respond is addressed first. The
addressing is always done with the first byte transmitted after the start procedure. The 12 C-bus
configuration for different PCF8570/PCF8570C/PCF8571 READ and WR ITE cycles is shown in Fig.8.
acknowledge
from slave
acknowledge
from slave
SLAVE ADDRESS
~
~
~
s
acknowledge
from slave
0 A
WORD ADDRESS
DATA
A
A
P
L--nbytes~
R/W
auto increment
memory word address
lZ81031.2
Fig.8(a) Master transmits to slave receiver (WRITE mode).
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from master
~
~
~
..I
~S~~S_L~A~V_E~A~D_D~R_ES~S__~O~_A~~_W~O~R_D~A_D~D~R~ES_S~~A~S~~S~L_A~V_E~A~D~D_R~E_S~S~~_A~~~~_D_A~TA~~~~_A~ --~
atthis~omentmasterl~Jw
t
R /W
transmitter becomes
master receiver and
PCF85701
lZ90118.2
_
n bytes
- jl'rI
auto increment
word address
PCF8570C I PCF8571
slave receiver becomes
slave transmitter
n~r~~::~~~ge
~
L ___ I
::
:D~TA:
lastbyte
:
:
4
111 P
auto increment
word address
Fig.8(b) Master reads after setting word address
(WRITE word address; READ data).
acknowledge
from slave
acknowledge
from master
no acknowledge
from master
t
•
t
S
7Z90777
auto increment
word address
auto increment
word address
Fig.8(c) Master reads slave immediately after first byte (R EAD mode).
I (MarCh
1989
325
PCF8570
PCF8570C
PCF8571
l
'-------------------------------------------------------------~
APPLICATION INFORMATION
The PCF8570/PCF8571 slave address has a fixed combination 1010 as group 1, while group 2 is fully
programmable (see Fig.9). The PCF8570C has slave address 1011 as group 1, while group 2 is fully
programmable (see Fig.1 0).
1 1 1 D 1 1 1 D 1A2 1A1 1AD 1R/W 1
1_
group 1
_1_
group 2
_I
7Z87030.1
Fig.9 PCF8570 and PCF8571 address.
I 1 I D 11
11
1_
_1_
group 1
I A2
1Al I ATI
group 2
_I
7Z95973
Fig.10 PCF8570C address.
Note
AO, A 1, and A2 inputs must be connected to VOO or VSS but not left open-circu it.
326
March
19891 (
PCF8570
PCF8570C
PCF8571
128 x 8-bit/256 x 8-bit static RAMs with \2C-bus interface
Voo
o
AO
Voo
PCF8570/
A1
PCF8571
AO
voo
SCL~--+-~
Voo
voo
0
0
A1
A2
upto8 PCF8570/PCF8571
SCL
PCF8570/
PCF8571
SOA
'1010'
VSS
to Voo
~
Voo
Voo
AO
Voo
Voo
A1
PCF8570/
PCF8571
SCL
R
R
R : pull- up resistor
R=~
VOO
CBUS
VOO
0
AO
A1
VOO
SCL
PCFB570C
Voo
AO
Voo
o
o
SCL 1----+--+
A1
up to 8 additional
devices
using PCF8570C
(16 max_)
Voo
VOO
AO
VOO
A1
VOO
PCF8570C
SCL
VOO
SOA SCL
(1 2 C bus)
7Z90774_3
It is recommended that a 4.7 J.LF/l0 V soiid aluminium capacitor (SAL) be connected between VDD and
VSS·
Fig.l1 Application diagram.
'I (MarCh
1989
327
PCF8570
PCF8570C
PCF8571
l
'-------------------------------------------------------------------
POWER SAVING MODE
With the condition TEST = Voo or VOOR the PCF8570/PCF8570C/PCF8571 goes into the power
saving mode and 12 C-bus logic is reset.
___
power saving
power saving
mode (1)· _ _ operating mode _ _ mode (2) __
TEST =VDDR
TEST = VD D
- , + - - - - - - VDD
TEST
--~k-------------------A-----------~---------- VDDR
~---- OV
VDD
SCL
VDDR
OV
VDD
SDA
VDDR
OV
~----.l------+-----+---
VDD
VDDR
OV
IDD
IDD
IDDS
7Z96997
(1) Power saving mode without 5 V supply voltage.
(2) Power saving mode with 5 V supply voltage.
(3) tsu and tH01 ~ 4 f.1S and tH02 ~ 50 f.1S.
Fig.12 Timing for power saving mode.
+5V----~--~--~~I~~---r--~----~r-----4r----~
8
3
A2
SC L
A1
l-_ r f__-+----4__- - -t 6 PCF8570
PCF8570C 2
PCF8571
TEST (1)
1---r;-~-----,7
4
+
I
1,2V
(NiCd)
"
7Z90776.3
(1) In the operating mode TEST = 0; In the power saving mode TEST = VOOR.
It is recommended that a 4.7 f.1F/10 V solid aluminium capacitor (SAL) be connected between VOO and
VSS·
Fig.13 Application example for power saving mode.
328
March
19891 (
rJ_.·.~_J
PCF8573
____
CLOCK/CALENDAR WITH SERIAL I/O
GENERAL DESCRIPTION
The PCF8573 is a low threshold, CMOS circuit that functions as a real time clock/calendar with an
12 C-bus interface.
The IC incorporates an addressable time counter and an addressable alarm register for minutes, hours,
days and months. Three special control/status flags, COMP, POWF and NODA, are also available.
Information is transferred via a serial two-line bidirectional bus (l 2 C). Back-up for the clock during
supply interruptions is provided by a 1.2 V nickel cadium battery~ The time base is generated from
a 32.768 kHz crystal-controlled oscillator.
Features
•
•
•
•
•
Serial input/output 12 C-bus interface for minutes, hours, days and months
Additional pulse outputs for seconds and minutes
Alarm register for presetting a time for alarm or remote switching functions
Battery back-up for clock function during supply interruption
Crystal oscillator control (32.768 kHz)
QUICK REFERENCE DATA
parameter
symbol
min.
typo
max.
unit
Supply voltage range
clock (pin 16 to pin 15)
12 C interface (pin 16 to pin 8)
VDD-VSS1
VDD-VSS2
1.1
2.5
-
6.0
6.0
V
V
Crystal oscillator frequency
fosc
-
32.768
-
kHz
PACKAGE OUTLINES
PCF8573P: 16-lead DI L; plastic (SOT38).
PCF8573T: 16-lead mini-pack; plastic (S016L; SOT162A).
"I (
March 1989
329
___PC_F85_73_Jl_________________
FSET
MIN
SEC
V DO
10
9
+-___----,
16
32,768 kz
OSCO 14
PRESCALER
13
OSCILLATOR
1: 2 15
SECONDS
COUNTER
RESET
1: 60
CT
V DD
6
4
TIME COUNTER
SDA
EXTPF
SCL
'------1--- PF I N
CaMP
TEST
ALARM REGISTER
B
LEVEL SHIFTER
PCF8573
1.286691.1
AD
A1
Fig.1 Block diagram.
PINNING
1
v DD
V SS1
osco
OSCI
7
TEST
8
9
FSET
SEC
7Z86685.1
Fig.2 Pinning diagram.
330
March 1989\ (
2
3
4
5
6
10
11
12
13
14
15
16
AO
A1
CaMP
SDA
SCL
EXTPF
PFIN
VSS2
MIN
SEC
FSET
TEST
ascI
asca
VSS1
VDD
address input
address input
comparator output
serial data line
I 12C-bus
serial clock line J
enable power fail flag input
power fail flag input
negative supply 2 (12C interface)
one pulse per minute output
one pulse per second output
oscillator tuning output
test input; must be connected
to VSS2 when not in use
oscillator input
oscillator input/output
negative supply 1 (clock)
common positive supply
l____
Clock/calendar with serial I/O
P_C_F_85_7_3____
FUNCTIONAL DESCRIPTION
Oscillator
The PCF8573 has an integrated crystal-controlled oscillator which provides the timebase for the
prescaler. The frequency is determined by a single 32.768 kHz crystal connected between ascI and
OSCO. A trimmer is connected between ascI and VDD.
Prescaler and time counter
The prescaler provides a 128 Hz signal at the FSET output for fine adjustment of the crystal oscillator
without loading it. The prescaler also generates a pulse once a second to advance the seconds counter.
The carry of the prescaler and the seconds counter are available at the outputs SEC, MIN respectively,
and are also readable via the 12 C-bus. The mark-to-space ratio of both signals is 1 : 1. The time counter
is advanced one count by the falling edge of output signal MIN. A transition from HIGH-to-LOW of
output signal SEC triggers MIN to change state. The time counter counts minutes, hours, days and
months, and provides a full calendar function which needs to be corrected once every four years. Cycle
lengths are shown in Table 1.
Table 1 Cycle length of the time counter
unit
minutes
hours
days
months
number
of bits
counting
cycle
carry for
following
unit
7
6
6
00 to 59
00 to 23
01 to 28
5
01 to 30
01 to 31
01 to 12
59--.00
23--.00
28--.01
or29 -.01
30-.01
31-.01
12 -.01
content of
month
counter
I
2 (note 1)
2 (note 1)
4,6,9, 11
1,3,5,7,8,10,12
Note to Table 1
1. Day counter may be set to 29 by a write transmission with EXECUTE ADDRESS.
Alarm register
The alarm register is a 24-bit memory. It stores the time-point for the next setting of the status flag
CaMP. Details of writing and reading of the alarm register are included in the description of the
characteristics of the 12 C-bus.
Comparator
The comparator compares the contents of the alarm register and the time counter, each with a length
of 24 bits. When these contents are equal the flag CaMP will be set 4 ms after the falling edge of MIN.
This set condition occurs once at the beginning of each minute. This information is latched, but can be
cleared by an instruction via the 12C-bus. A clear instruction may be transmitted immediately after the
flag is set and will be executed. Flag CaMP information is also available at the output CaMP. The
comparison may be based upon hours and minutes only if the internal flag NODA (no date) is set.
Flag NODA can be set and cleared by separate instructions via the 12 C-bus, but it is undefined until
the first set or clear instruction has been received. Both CaMP and NODA flags are readable via the
2
1 C-bus.
'1 (
March 1989
331
~1
_Jl_________ _ _
__
PC_F85_73
FUNCTIONAL DESCRIPTION (contin!Jed)
Power on/power fail detection
If the voltage VOO-VSSl falls below a certain value the operation of the clock becomes undefined.
Thus a warning signal is required to indicate that faultless operation of the clock is not guaranteed.
This information is latched in a flag called POWF (Power Fail) and remains latched after restoration
of the correct supply voltage until a write procedure with EXECUTE AOORESS has been received.
The flag POWF can be set by an internally generated power fail level-discriminator signal for application
with (VOO-VSS1) greater than VTH1, or by an externally generated power fail signal for application
with (VOO-VSS1) less than VTH1. The external signal must be applied to the input PFIN. The input
stage operates with signals of any slow rise and fall times. Internally or externally controlled POWF
can be selected by input EXTPF as shown in Table 2.
Table 2 Power fail selection
EXTPF
PFIN
0
0
1
0
1
1
1
0
function
power fail is sensed internally
test mode
power fail is sensed externally
no power fail sensed
0: connected to VSSl (LOW)
1 : connected to VOO (HIGH)
The external power fail control operates by absence of the VOO-VSS2 supply. Therefore the input
levels applied to PFIN and EXTPF must be within the range of VOO-VSS1. A LOW level at PFIN
indicates a power fail. POWF is readable via the 12C-bus. A power on reset for the 12C-bus control is
generated on-chip when the supply voltage VOO-VSS2 is less than VTH2.
I nterface level shifters
The level shifters adjust the 5 V operating voltage (VOO-VSS2) of the microcontroller to the internal
supply voltage (VOO-VSS1) of the clock/calendar. The oscillator and counter are not influenced by
the VOO-VSS2 supply voltage. If the voltage VOO-VSS2 is absent (VOO = VSS2) the output signal
of the level shifter is HIGH because VOO is the common node of the VOO-VSS2 and the VOO-VSSl
supplies. Because the level shifters invert the input signal, the internal circuit behaves asif a LOW signal
is present on the inputs. FSET, SEC, MIN and COMP are CMOS push-pull output stages. The driving
capability of these outputs is lost when the supply voltage VOO-VSS2 = O.
332
March 1989\ (
l____
Clock/calendar with serial I/O
PC_F_8_5_7_3____
CHARACTERISTICS OF THE 12C-BUS
The 12 C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are
a serial data line (SDA) and a serial clock line (SCl). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated
only when the bus is not busy.
Bit transfer (see Fig.3)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted
as control signals.
SDA
----4.--JX'-......j-.___ ~ ~
---,,-
---'-_4--_ _ _
SCL
data line
stable:
data valid
change
of data
allowed
7Z87019
Fig.3 Bit transfer.
Start and stop conditions (see Fig. 4)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-lOW transition of the
data line, while the clock is HIGH is defined as the start condition (S). A lOW-to-HIGH transition of
the data line while the clock is HIGH is defined as the stop condition (P).
SOA
-----R'---II-----LC---== ~---~----__+r..J-rt_-I
SCL
I
:: s::
L ___
I
\
.J
'
/r---\\.,. __- ' / ::
SOA
I
I
p
SCL
:
L _ _ _ .J
start condition
stop condition
7Z87005
Fig.4 Definition of start and stop conditions.
System configuration (see Fig.5)
A device generating a message is a "transmitter", a device receiving a message is the "receiver", The
device that controls the message is the "master" and the devices which are controlled by the master
are the "slaves".
SDA---------~----------~------------~------------~----------~-SCL--~------+_----~------+-----~------;_---~------~--~----_r--
f:=ig.5 System configuration.
'I (
March 1989
333
~
~_PC_F85_73_Jl________________
CHARACTERISTICS OF THE 12C-bus (continued)
Acknowledge (see Fig.6)
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge
bit is a HI G H level put on the bus by the transmitter whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception
of each byte. Also a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during
the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver
must signal an end of data to the transmitter by not generating an acknowledge on the last byte that
has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable
the master to generate a stop condition. (See Fig.10 and Fig.11).
start
condition
clock pulse for
acknowledgement
I
t
I
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
I
I
I
I
I
--~
1~/-----'X~_K~~-:x
7
S
DATA OUTPUT
BY RECEIVER
7Z87007
Fig.6 Acknowledgement on the 12 C-bus.
334
March
19891 (
l____
Clock/calendar with serial I/O
P_C_F_85_7_3____
Timing specifications
All the timing values are valid within the operating supply voltage and ambient temperature range and
refer to VIL and VIH with an input voltage swing of VSS to VDD.
parameter
symbol
min.
typo
max.
unit
SCL clock frequency
fSCL
100
kHz
tsw
-
-
Tolerable spike width on bus
-
100
ns
Bus free time
tBUF
4.7
-
IlS
Start condition set-up time
tsu; STA
4.7
-
Start condition hold time
tHD; STA
4.0
IlS
IlS
SCL LOW time
tLOW
4.7
-
SCL HIGH time
tHIGH
4.0
SCL and SDA rise time
tr
SCL and SDA fall time
tf
-
Data set-up time
tsu; DAT
250
Data hold time
tHD; DAT
0
SCL LOW to data out valid
tVD; DAT
-
Stop condition set-up time
tsu; STO
4.0
-
IlS
-
1.0
IlS
IlS
0.3
IlS
-
ns
3.4
IlS
IlS
-
ns
PROTOCOL
SCL
SDA
lZB1193.2
tHD;STA
tSU;DAT
tHO; OAT
tVo;oAT
tSU;STO
Fig.7 12 C-bus timing diagram.
') (
March 1989
335
~
___PC_F85_73_Jl~________________
ADDRESSING
Before any data is transmitted on the 12C-bus, the device which should respond is addressed first. The
addressing is always done with the first byte transmitted after the start procedure.
Slave address
The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCl is only
an input signal, but the data signal SDA is a bidirectional line. The clock calendar slave address is shown
in Fig.B.
MSB
I I
1
LSB
1
0
I I
1
0
A1
I I I
AO
R/W
7Z86686
Fig.B Slave address.
The subaddress bits AD and A 1 correspond to the two hardware address pins AD and A 1 which allows
the device to have 1 of 4 different addresses.
Clock/calendar READ/WRITE cycles
The 12C-bus configuration for different clock/calendar READ and WRITE cycles is shown in Figs 9,
1D and 11.
acknowledge
from slave
acknowledge
from slave
+ MSB
R/vd
S
CLOCK/CALENDAR
ADDRESS
0 A
acknowledge
from slave
MODE POINTER
LSB
DATA
A
L
nbytes _
(n=0.1.2 •... )
+
A
I
P
t
auto increment
of B1. BO
7Z86687
Fig.9 Master transmitter transmits to clock/calendar slave receiver.
The write cycle is used to set the time counter, the alarm register and the flags. The transmission of the
clock/calendar address is followed by the MODE-POINTER-WORD which contains a CONTROL-nibble
(Table 3) and an ADD RESS-nibble (Table 4). The ADDRESS-nible is valid only if the preceding
CONTROL-nibble is set to EXECUTE ADDRESS. The third transmitted word contains the data to be
written into the time counter or alarm register.
336
March
19891 (
PCF8573
Clock/calendar with serial I/O
Table 3 CONTROL-nibble
0
0
0
0
0
0
0
C2
C1
CO
function
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
execute address
read control/status flags
reset prescaler, including seconds counter; without carry for minute counter
time adjust, with carry for minute counter (see note)
reset NODA flag
set NODA flag
reset CaMP flag
Note
If the seconds counter is below 30 there is no carry. This causes a time adjustment of max. -30 s.
From the count 30 there is a carry which adjusts the time by max. + 30 s.
Table 4 ADDRESS-nibble
0
0
0
0
0
0
0
0
B2
B1
BO
addressed to:
0
0
0
0
0
0
1
1
0
0
0
time counter hours
time counter minutes
time counter days
time counter months
alarm register hours
alarm register minutes
alarm register days
alarm register months
1
1
1
1
1
1
1
0
1
0
1
0
1
At the end of each data word the address bits B1, BO will be incremented automatically provided the
preceding CONTROL-nibble is set to EXECUTE ADDRESS. There is no carry to B2.
Table 5 shows the placement of the BCD upper and lower digits in the DATA byte for writing into the
addressed part of the time counter and alarm register respectively.
Table 5 Placement of BCD digits in the DATA byte
MSB
DATA
upper digit
LSB
lower digit
UD UC UB UA LD
LC
LB
LA addressed to:
X
X
X
X
D
D
D
D
D
D
D
D
D
D
D
X
D
X
X
D
D
D
D
D
X
D
D
D
D
D
D
D
hours
minutes
days
months
Where:
"X" is the don't care bit
"D" is the data bit
Acknowledgement response of the clock calendar as slave receiver is shown in Table 6.
1(
March 1989
337
___P_CF8_57_3_Jl______________~
ADDRESSING (continued)
Table 6 Slave receiver acknowledgement
acknowledge on byte
mode pointer
C2
C1
B2
CO
x x
x X
X
x
x x
a a a a
a a a 1
a a 1 x
a 1 a x
a 1 1 X
1
a a x
1
a 1 x
1
1
a x
a
a
a
a
a
a
a
a
a
1
X
1
1
X
1
X
B1
X
X
X
X
X
X
x x
x
X
x x
X
X
address
mode pointer
data
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
no
yes
yes
yes
yes
yes
yes
no
no
yes
no
no
no
no
no
no
no
no
no
BO
X
X
X
X
X
X
X
X
X
X
Where:
"X" is the don't care bit.
Table 7 Organization of the BCD digits in the DATA byte
MSB
DATA
LSB
upper digit
lower digit
UD UC UB
UA LD
LC
LB
LA
addressed to
a a D
a D D
a a D
a a a
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
hours
minutes
days
months
a a a
*
**
NODA
COMP
POWF
control/status flags
Where:
"D" is the data bit
* = minutes
* * = seconds.
338
March 1989
'I (
C')
acknowledge
from slave
R/W
s
CLOCK/CALENDAR 10
ADDRESS
acknowledge
from slave
+
IA I
acknowledge
from master
acknowledge
from slave
R/W
CLOCK/CALENDAR
ADDRESS
MODE POINTER
atthis~omentmaster
~ MSB
LSB
11A
DATA
no acknowledge
~ MSB
A
LSB
(11
+
0n
~
g
CD
;:,
C.
..
DATA
III
:E
;:t..
~
} J t ( n _ 1 1 b y t e s _ i t nth byte
transmitter becomes
master receiver and
en
9l
~
CLOCK/CALENDAR
becomes slave transmitter
auto increment
of B1, BO
auto increment
of B1, BO
7Z86690.1
~
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave.
Fig.10 Master transmitter reads clock/calendar after setting mode pointer.
To read the addressed part of the time counter and alarm register, plus information from specified control/status flags, the BCD digits in the
DATA byte are organized as shown in Table 7.
acknowledge
from slave
R
~~--'---r-----'-----'--T--
S
--1
CLOC:~g~~~~DAR
acknowledge
from master (1)
/vd MSB
A
!+-
LSB
DATA
s:
n
::r
co
A
P
n bytes _ I
auto increment
of B1, BO
III
+
7Z86689
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave.
Fig.11 Master reads clock/calendar immediately after first byte.
00
\)'
(")
CO
The status of the MODE-paiNTER-WORD concerning the CONTROL-'nibble remains unchanged until a write to MODE POINTER condition
occurs.
"
(X)
01
-...I
(.V.
~
CO
___
PC_F85_73_Jl________________
RATINGS
Limiting values in accordance with the Absolute Maximum System (lEe 134)
parameter
condition
Supply voltage range
pin 16 to pin 15
pin 16 to pin 8
Voltage input
pins 4 and 5
pins 6, 7,13 and 14
any other pin
note 1
symbol
min.
max.
unit
VDD~\§SSl
VDD-M'SS2
-0.3
-0.3
8.0
8.0
V
V
VI
VI
VI
VSS2- 0 .8
VSS1- 0 .6
VSS2-0 .6
VDD+0.8
VDD+0.6
VDD+0.6
V
V
V
Input current
II
-
10
mA
Output current
10
-
10
mA
Po
Ptot
-
100
mW
Total power dissipation
-
200
mW
Operating ambient
temperature range
Tamb
-40
+85
oe
Storage temperature range
T stg
-55
+125
oe
Power dissipation
per output
Note to the Ratings
1. With input impedance of minimum 500 n.
HANDLING
Inputs and outputs are protected against electrostatic charge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see
'Handling' MOS devices').
340
March
19891 (
PCF8573
Clock/calendar with serial I/O
CHARACTERISTICS
VSS2 = 0 V; T amb = -40 to + 85 OC unless otherwise specified. Typical values at T amb =+ 25 oC
parameter
conditions
typo
max.
unit
VOO-VSS2 2.5
5.0
6.0
V
1.1
1.5
VOO-VSS2
V
-
3
12
10
50
p.A
p.A
-
-
50
p.A
symbol
min.
Supply
Supply voltage
12 C interface
clock
Supply current
VSS1 (pin 15)
VSS2 (pin 8)
tHO; OAT;;::'
300 ns
VOO-VSS1
VOO-VSS1 = 1.5 V -ISS1
VOO-VSS1 = 5 V -ISS1
VOO-VSS2=5 V;
10 = 0 all outputs
-ISS2
Input Sel;
input/output SOA
I nput voltage LOW
VIL
-
-
0. 3V OO
V
Input voltage HIGH
VIH
0. 7V OO
-
V
!Ill
-
-
1
p.A
CI
-
-
7
pF
Input voltage LOW
VIL
-
0. 2V OO
V
Input voltage HIGH
VIH
0.7 V OO
-
-
V
-
-
250
nA
Leakage current
Input capacitance
VI =VSS2 or VOO
Inputs AD, A 1,
TEST
Input leakage current VI = VSS2 or VOO ± ILl
Inputs EXTPF,
PFIN
Input voltage LOW
Input voltage HIGH
VIL
0
-
0.2 VOO-VSS1
V
VIH
0.7 VOO-VSS1
-
V
-
-
1.0
p.A
-
-
0.1
p.A
Input leakage current VI =VSS1 to VOO ± III
Tamb = 25 oC;
VI =VSS1 to VOO ± III
1(
March 1989
341
J
PCF8573
CHARACTERISTICS (continued)
parameter
conditions
symbol min.
10 =3 rnA;
VOO-VSS2 = 2.5 to
to 6 V
VOL
VOO-VSS2 = 6 V;
VO=6V
VOO-VSS2 = 2.5 V;
10 =0.3 rnA
typo
max.
unit
-
-
0.4
V
IILI
-
-
1
IJ.A
OutputSDA
(n channel open drain)
Output "ON"
Leakage current
Outputs
Outputs SEC, MIN, CaMP, FSET
(normal buffer outputs)
Output voltage LOW
Output voltage HIGH
VOL
-
-
0.4
V
VOO-VSS2 = 4 to 6 V;
10 = 1.6 rnA
VOL
-
-
0.4
V
VOO-VSS2 = 2.5 V;
-10 = 0.1 rnA
VOH
VOo-O.4
-
-
V
VOO-VSS2 = 4 to 6 V;
-10 =0.5mA
VOH
VOD-O.4
-
-
V
Internal threshold voltage
Power failure detection
VTH1
1
1.2
1.4
V
Power "ON" reset
VTH2
1.5
2.0
2.5
V
t r , tf
t r , tf
-
-
1
IJ.S
-
-
00
IJ.S
Rise and fall times of
input signals
Input EXTPF
Input PFIN
I nput signals except EXTP F
and PFIN between VIL and
VIH levels
342
rise time
tr
-
-
1
IJ.S
fall time
tf
-
-
0.3
IJ.S
1(
March 1989
. PCF8573
Clock/calendar with serial I/O
parameter
conditions
symbol
min.
typo
max.
unit
COUT
-
40
-
pF
Rf
-
3
-
Mn
f/fos c
-
2 x 10. 7
-
-
RS
-
-
40
kn
10
-
5
-
25
Oscillator
Integrated oscillator
capacitance
Oscillator feedback
resistance
Oscillator stability
~(VDD-VSSl )
= 100 mV; at
VDD-VSSl = 1.55 V;
Tamb = 25 °C
Quartz crystal parameters
Series resistance
Parallel capacitance
Trimmer capacitance
f = 32.768 kHz
CL
CT
'1 (
.p£ .
pF
March 1989
343
_ _PC_FB_573_Jl_ _ _ _ _ _ __
APPLICATION INFORMATION
r-~~-----r~~----~------+5V
R: pull-up resistor
t--t----i
VDD
PCF8570
SDA
MASTER DEVICE
SCL
MICRO CONTROLLER
128 x 8 BIT STATIC CMOS RAM
VSS
PCF8577
OSCI
SDA I---f--+
64 LCD
SEGMENT DRIVER
SCL I--~I--+--+
VSS1
1,2V
(NiCa)
~
+
Rch : resistor for
permanent charging
detection circuit
with very high
impedance
7Z86688.3
Fig.12 Application example of the PCF8573 clock/calendar.
+5V--~--~~----~~+-----~----~--------~~------_,
R
R
~_+----------------~--+-----------------~_+----.SDA
t-_+--+_--------~--~--+-_4--------------~_+--+_--_+
SCL
SCL SDA VDD
MASTER
MICRO -
PCF8571
CONTROLLER
VSS
VSS
7Z87945.1
Fig.13 Application example of the PCF8573 with common VSS1 and VSS2 supply.
344
March
19691 (
l___
Clock/calendar with serial I/O
P_C_F_8_5_7_3______
7Z24490
12
/
/
B
/
4
V
o
o
2
V
~
V
4
6
VDD-VSS1 (V)
Fig.14 Typical supply current (-1551) as a function of clock supply voltage (VOD-VSS1) at
T amb = -40 to + 85 °C.
Purchase of Philips' 12C components conveys a license under the
Philips' 12C patent to use the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
1(
March 1989
345
~i
J
PCF8574
PCF8574A
~~-
REMOTE 8-BIT liD EXPANDER FOR 12C-BUS
GENERAL DESCRIPTION
The PCF8574 is a single-chip silicon gate CMOS circuit. It provides remote I/O expansion for the
MAB8400 and PCF84CXX microcontroller families via the two-line serial bidirectional bus (1 2 C).
It can also interface microcomputers without a serial interface to the 12 C-bus (as a slave function only).
The device consists of an 8-bit quasi-bidirectional port and an 12 C interface.
The PCF8574 has low current consumption and includes latched outputs with high current drive
capability for directly driving LEOs. It also possesses an interrupt line (INT) which is connected to the
interrupt logic of the microcomputer on the 12 C-bus. By sending an interrupt signal on this line, the
remote I/O can inform the microcomputer if there is incoming data on its ports without having to
communicate via the 12 C-bus. This means that the PCF8574 can remain a simple slave device.
The PCF8574 and the PCF8574A versions differ only in their slave address as shown in Fig.9.
Features
•
•
•
•
•
•
•
•
Operating supply voltage
2.5 V to 6 V
Low stand-by current consumption
max. 10 JlA
Bidirectional expander
Open drain interrupt output
8-bit remote I/O port for the 12 C-bus
Peripheral for the MAB8400 and PCF84CXX microcontroller families
Latched outputs with high current drive capability for directly driving LEOs
Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A)
INT _+-'-.:.3-------1
PCF8574
PCF8574A
AO--~---------~
A'--~--------~
4
A2-~------------~
PO
P'
SCL--+--+-I
~
SDA +-+--....-.1
~
P2
SHIFT
REGISTER
P3
I/O
PORTS
P4
P5
P6
P7
write pulse
VDD--~---i
read pulse
VSS
lZ85821.2
Fig.1 Block diagram.
PACKAGE OUTLINES
PCF8574P, PCF8574AP: 16-lead OIL; plastic (SOT38).
PCF8574T, PCF8574AT: 16-lead mini-pack; plastic (S016L; SOT162A).
1(
May 1989
347
l
PCF8574
PCF8574A
________________________________________
PINNING
Fig.2 Pinning diagram.
7ZB7597.1
1 to 3
AO to A2
4 to 7
PO to P3
1
address inputs
9 to 12
P4 to P7
I
8
VSS
INT
negative supply
13
14
SCL
serial clock line
15
SOA
serial data line
16
VOO
positive supply
8-bit quasi-bidirectional I/O port
interrupt output
~---~-----~-----VDD
write pulse
--.>__--_._-------\
PO to P7
power- on --t>--_--+-----'
reset
' - - + - - - - - - - vss
read pulse - - . > - - - ; - - - - 1
}-_ _ _ _--+
data to
shift register
7ZB759B.1
Fig.3 Simplified schematic diagram of each port.
348
May
19891 (
to interrupt
logic
J
Remote 8-bit I/O expander for FC-bus
PCF8574
PCF8574A
-'--------CHARACTERISTICS OF THE 12C-BUS
The 12 C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are
a serial data line (SDA) and a serial clock line (SCl). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated
only when the bus is not busy.
Bit tra nsfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted
as control signals.
SDA ........:.-..-I-_ _ _ _ _-I---'X'--4-_ _
SCL
data line
stable:
data valid
change
of data
allowed
7Z87019
F ig.4 Bit transfer.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the
data line, while the clock is HIGH is defined as the start condition (5). A lOW-to-HIGH transition of
the data line while the clock is H IG H is defined as the stop condition (P).
r----,
SDA - -
!\\...-li----'-c--- ==~------>------_+-'Ii-I
SCL
r---l
II
I
II
I
I
I
I
L ___
SDA
I
\
;---\
/
,- - - - '
'------'
II
I
-
SCL
I
.J
stop condition
start condition
7Z87005
F ig.5 Definition of start and stop conditions.
System configuration
A device generating a message is a "transmitter", a device receiving a message is the "receiver". The
device that controls the message is the "master" and the devices which are controlled by the master
are the "slaves".
SDA----------~------------~-------------~------------~------------~-
SCL--~------1_----~------_+----~r_------~----~------_l_----~------_+--
7Z87004
F ig.6 System configuration.
'] (
May 1989
349
PCF8574
PCF8574A
l
--------------------------------------------------------~
CHARACTERISTICS OF THE 12 C-BUS (continued)
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge
bit is a HI G H level put on the bus by the transmitter whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception
of each byte. Also a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during
the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver
must signal an end of data to the transmitter by not generating an acknowledge on the last byte that
has been clocked out of the slave. I n this event the transmitter must leave the data line H IG H to enable
the master to generate a stop condition.
clock pu Ise for
acknowledgement
start
condition
I
I
SCL FROM
MASTER
I
I
I
I
+
--~
I
DATA OUTPUT
BY TRANSM ITTE R
~'---L--/----JX'---_>C~~X
DATA OUTPUT
BY RECEIVER
7
--~
7Z87007
Fig.7 Acknowledgement on the 12 C-bus.
350
May
19891 (
PCF8574
PCF8574A
Remote a-bit I/O expander for 12 C-bus
Timing specifications
All the timing values are valid within the operating supply voltage and ambient temperature range and
refer to VI L and VI H with an input voltage swing of VSS to VDD·
parameter
symbol
min.
typo
SCL clock frequency
fSCL
-
Tolerable spike width on bus
tsw
I
Bus free time
Start condition set-up time
Start condition hold time
SCL LOW time
SCL HIGH time
max.
unit
-
100
kHz
-
-
100
ns
tBUF
4.7
-
-
J.l.S
tsu; STA
4.7
-
-
J.l.S
tHO; STA
4.0
.-
-
J.l.S
tLOW
4.7
-
-
J.l.S
tHIGH
4.0
-
-
J.l.S
SCL and SDA rise time
tr
-
-
1.0
J.l.S
SCL and SDA fall time
tf
-
-
0.3
J.l.S
tsu; OAT
250
-
-
ns
-
ns
Data set-up time
Data hold time
tHO; OAT
0
-
SC L LOW to data out val id
tVD; OAT
-
-
3.4
J.l.S
Stop condition set-up time
tsu; STO
4.0
-
-
J.l.S
PROTOCOL
SCL
SDA
7ZB1193.2
tHD;STA
tsu; DAT
tHD; DAT
tVD;DAT
tSU;STO
Fig.8 12 C-bus timing diagram.
'1 (
May 1989
351
w
c.n
N
'1J'1J
00
FUNCTIONAL DESCRIPTION
Illl
0000
Addressing (see Figs 9, 10 and 11)
(Jl(Jl
slave add ress
s::
slave address
Q)
-<
c.o
00
c.o
S
D
,;1
D : A2 : A' : AD:
D
I
A
SiD :
'
1
(a) PCF8574.
I,
:uA
................
<<
A
~~
A<
D
»
I I
A
7Z96587
(b) PCF8574A.
Fig.9 PCF8574 and PCF8574A slave addresses.
Each bit of the PCF8574 I/O port can be independently used as an input or an output. Input data is transferred from the port to the
microcomputer by the READ mode. Output data is transmitted to the port by the WRITE mode.
~
SCL
slave address (PCF857 4)
data to port
A
A
data to port
J..,
I
I
I
I
1
SDA
S
t
D
start condition
WRITE
TO
PORT
D
0
A2
DATA'
iA
DATA 2
t i t
I acknowledge from slave
acknowledge from slave
IA
It
acknowledge from slave
---------------------T------------------~Vl
1
~
I
1
1
:
DATA OUT
FROM PORT
-----------------~---------------~!~~
I
tpv
_I
I
D_'0~
i~A'O~
I
1..-
I
tpv
_I
1
1..7Z87593.1
Fig.l0 WRITE mode (output port).
slave address (PCF8574)
I I
SDA
5
I
0
I
I
1
I
0
0
Al
AO
I
IA
I
-----.------.--.
DATA 1
~
DATA 1
I
I
I
I
I
~
I
-J
1__ tiv
0;:;..
-
stop
condition
o
CD
)(
"0
Q)
:1
Q.
~
~--~I--------------------------~
DATA 3
1__ tph
I
I
in
I I
---I
00
DATA 4
~----------------~
I
I
EJ.
I
A
from master
I
_I
I
I
I
!I
CD
3
S
CD
J.
I acknowledge
~----------------------__-----+I--
::I:J
data from port
~
t
R /W I acknowledge
I from slave
----------------------~VI
I
READ FROM
PORT
INT
A2
L d
t
start condition
DATA INTO
PORT
data from port
..A-_ _ _ _ _ _
~
A
1-- tir
X:
Q
DATA 4
n
c-
IL-~I--------------------------+_---__ I
1__ tps
I
5
I
:
---I
1
I
1-- tir
7787596.1
F ig.11 READ mode (input port).
Note
A LOW-to-HIGH transition of SDA, while SCL is HIGH is defined as the stop condition (P). Transfer of data can be stopped at any moment by a
stop condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost.
~
$;
Q)
-<
<0
00
co
"'U"'U
00
"TI"TI
0000
(J"1(J"1
-....J-....J
~~
W
fJ'1
W
:x>
l
PCF8574
PCF8574A
------------------------------------------------------------------Interrupt (see Figs 12 and 13)
The PCF8574/PCF8574A provides an open drain output (INT) which can be fed to a corresponding
input of the microcomputer. This gives these chips a type of master function which can initiate an
action elsewhere in the system.
PCF8574
PCF8574
PCF8574A
(11
(2)
(16)
M I C ROCOMPUTE R
INT 1--_+_-4-----........- - - - - - - 7ZB7599.1
F ig.12 Appl ication of multiple PCF8574s with interrupt.
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time
tiv the signal INT is valid.
Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the
original setting or data is read from or written to the port which has generated the interrupt.
Resetting occurs as follows:
• In the READ mode at the acknowledge bit after the rising edge of the SCL signal.
• In the WRITE mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL signal.
Each change of the ports after the resettings will be detected and after the next rising clock edge, will
be transmitted as I NT.
Reading from or writing to another device does not affect the interrupt circuit.
slave address (PCF8574)
data from port
A
J..
SDA
t
start condition
+_I1 t
R /W 1acknowledge
1 from slave
t
P5
stop
condition
1
1
1
SCL
1
1
1
DATA INTO
INT
p0
1
1
1
1
1
1
1
1
1
I
--t-J
:
1
-------------------------rl
~I
__ I
I
~I
1-- tiv
--I
1-- tir
Fig.13 Interrupt generated by a change of input to port P5.
354
7ZB7594.1
PCF8574
PCF8574A
Remote a-bit I/O expander for 12 C-bus
FUNCTIONAL DESCRIPTION (continued)
Quasi-bidirectional I/O ports (see F ig.14)
A quasi-bidirectional port can be used as an input or output without the use of a control signal for
data direction. At power-on the ports are HIGH. In this mode only a current source to VOO is active.
An additional strong pull-up to VOO allows fast rising edges into heavily loaded outputs. These devices
turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The ports
should be HIGH before being used as inputs.
slave address (PCF8574A)
SDA
I I 0:
S
t
<< >< ><
A1
start condition
data to port
data to port
II
0
t
>:t
I I
R/W
II
A
t
acknowledge
:a:t
I:I I
A
I
P3
P3
I
from slave
I
I
I
SCl
I
I
I
I
I
P3
OUTPUT
VOLTAGE
I
------~----------------------------------~!
.
~
,
:
--rL----------1L-
P3
PUll-UP
OUTPUT
CURRENT
I
I
t
I
I
I
I OHt :
t
: IOH
7Z87595.1
Fig.14 Transient pull-up current IOHt while P3 changes from LOW-to-HIGH and back to LOW.
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
parameter
symbol
min.
max.
unit
Supply voltage range
VOO
-0.5
+ 7.0
V
I nput voltage range
VI
VSS -0.5
VOD + 0.5
V
DC input current
-
20
mA
-
25
rnA
VOO or VSS current
± II
± 10
± 100; ± ISS
-
100
mA
Total power dissipation
Ptot
-
400
mW
Power dissipation per output
Po
-
100
mW
Operating ambient temperature range
Tamb
T stg
-40
+ 85
°C
-65
+ 150
°C
DC output current
Storage temperature range
HANDLING
I nputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see
'Handling MOS Devices').
355
l
PCF8574
PCF8574A
------------------------------------------------------------~
CHARACTERISTICS
VOO = 2.5 to 6 V; VSS = 0 V; T amb = -40 to + 85 °C unless otherwise specified
parameter
conditions
symbol
min.
typo
max.
unit
VOO
2.5
-
6.0
V
40
2.5
13
1 .
100
10
2.4
JlA
JlA
V
V
Supply
Supply voltage
Supply current
I
operating
standby
Power-on reset level
VOO = 6 V;
no load;
VI =VOO or
VSS
fSCL = 100 kHz
note 1
100
1000
V pOR
1-
-
Input SCL; input/output SOA
I nput voltage LOW
Input voltage HIGH
VIL
-0.5
-
0. 3V OO
-
VOO + 0.5 V
VIH
0. 7V OO
Output current LOW
VOL = 0.4 V
10L
3
-
-
rnA
Leakage current
VI = VOO or
VSS
IILI
-
1
JlA
VI = VSS
CI
-
-
7
pF
VIL
-0.5
-
0. 3V OO
V
VIH
0. 7V OO
-
VOO + 0.5 V
VI ~VOO or
~VSS
± IIHL
-
-
400
JlA
VOL = 1 V;
VOO = 5 V
10L
10
25
-
rnA
Output current HIGH
VOH = VSS
10H
30
-
300
JlA
Transient pull-up current
HIGH during acknowledge
(see Fig.14)
VOH = VSS;
VOO = 2.5 V
-IOHt
-
1
-
rnA
CliO
-
-
10
pF
tpv
-
-
4
Jls
I nput data set-up
tps
0
JlS
tph
4
-
-
I nput data hold
-
JlS
Input capacitance (SCL, SOA)
I/O ports
Input voltage LOW
Input voltage HIGH
Maximum allowed input
current through
protection diode
Output current LOW
I nput/Output capacitance
Port timing
(see Figs 10 and 11)
Output data valid
356
May
19891 (
CL = ~ 100 pF
PCF8574
PCF8574A
Remote 8-bit I/O expander for FC-bus
conditions
symbol
min.
typo
max.
unit
Output current LOW
VOL = 0.4 V
IOL
1.6
-
-
mA
Leakage cu rrent
VI = VOO or
VSS
IILI
-
-
1
I~A
parameter
Interrupt INT
tNT timing
(see Figs 11 and 13)
CL = ~ 100 pF
I nput data valid
tiv
-
-
4
fJ.s
Reset delay
tir
-
-
4
fJ.s
VIL
-0.5
-
0. 3V OO
V
VIH
0. 7V OO
-
VOO + 0.5 V
IILI
-
-
250
Select inputs AO, A 1, A2
I nput voltage LOW
Input voltage HIGH
I nput leakage current
pin at VOO or
VSS
nA
Note to the characteristics
1. The power-on reset circuit resets the 12 C-bus logic with VOO
(with current source to VOO).
< VPOR
and sets all ports to logic 1
Purchase of Philips' 12C components conveys a license under the
Philips' 12C patent to use the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
I(
May 1989
357
_____i!_~U~_Jl__
PCF_8576_
UN1VERSAL LCD DRIVER FOR LOW MULTIPLEX RATES
GENERAL DESCRIPTION
The PCF8576 is a peripheral device which interfaces to almost any liquid crystal display (LCD) having
low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to
four backplanes and up to 40 segments and can easily be cascaded for larger LCD applications. The
PCF8576 is compatible with most microprocessors/microcontrollers and communicates via a two-line
bidirectional bus WC). Communication overheads are minimized by a display RAM with autoincremented addressing, by hardware subaddressing and by display memory switching (static and
duplex drive modes).
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single-chip LCD controller/driver
Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing
Selectable display bias configuration: static, 1/2 or 1/3
Internal LCD bias generation with voltage-follower buffers
40 segment drives: up to twenty 8-segment numeric characters; up to ten 15-segment alphanumeric
characters; or any graphics of up to 160 elements
40 x 4-bit RAM for display data storage'
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
LCD and logic supplies may be separated
Wide power supply range: from 2 V for low-threshold LCDs and up to 9 V for guest-host LCDs and
high-threshold (automobile) twisted nematic LCDs
Low power consumption
Power-saving mode for extremely low power consumption in battery-operated and telephone
applications
2
1 C-bus interface
TTL/CMOS compatible
Compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers
May be cascaded for large LCD applications (up to 2560 segments possible)
Cascadable with the 24-segment LCD driver PCF8566
Optimized pinning for single plane wiring in both single and multiple PCF8576 applications
Space-saving 56-lead plastic mini-pack (VS056)
Very low external component count (at most one resistor, even in multiple device applications)
Compatible with chip-on-glass technology
Manufactured in silicon gate CMOS process
Purchase of Philips' FC components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system
provided the system conforms to the 12 C specifications defined
by Philips.
PACKAGE OUTLINES
PCF8576T: 56-lead mini-pack; plastic (VS056; SOT190).
PCF8576U: uncased chip in tray
PCF8576U/10: chip-on-film frame carrier (FFC)
1
(March 1987
359
w
en
o
-u
()
so
BPO BP2 RPl BP3
s:
~
n
VDD
+13 +14 +15 +16
I
5
~
:~
c.o
00
--..J
BACKPLANE
OUTPUTS
W
I-
DISPLAY
RAM
40x 4 BITS
1'r
DATA
POINTER
~
11
OUTPUT
W
BANK
~ SELECTOR
~
to.
2
1
<=>
~
INPUT
FILTERS
~
1 C BUS
--.
CONTROLLER
2
:~
~ 10
"
SUBADDRESS
COUNTER
7
I
AD
SAO
8
Al
9
A2
7Z91475.1
Fig. 1 Block diagram.
_ _ _ _ _ _u_n_iv_e_rs_a_1_LC_D_d_r_iV_er_f_O_r_IO_W_m_u_lt_iP_I_ex_ra_te_s_ _ _ _ _ _
,~ l:r_8_5_7_6_____
PINNING
S39
1
2
SCl
12 C-bus clock input/output
S37
3
SYNC
cascade synchronization input/output
S36
4
ClK
external clock input/output
5
6
VOO
OSC
osci llator input
7
8
9
AO
A1
A2
12 C-bus subaddress inputs
10
SAO
2
1
11
VSS
logic ground
12
13
14
15
16
lCO supply voltage
VlCO
BPO
BP2
( lCO backplane outputs
BP1
BP3
J
17
to
56
SO
to
S39
535
S34
533
532
531
S30
S29
VLCD
528
BPO
527
BP2
C-bus data input/output
SOA
S38
5AO
2
1
526
PCF8576T
BP1
525
BP3
S24
50
S23
51
522
S2
S21
S3
520
54
519
55
518
56
517
S7
S16
58
515
59
514
510
S13
S11
512
positive supply voltage
C-bus slave address bit 0 input
1
l
lCO segment outputs
J
7Z91476.2
Fig.2 Pinning diagram.
1
(MarCh 1987
361
___
PC_F857_6_jl________________
FUNCTIONAL DESCRIPTION
The PCF8576 is a versatile peripheral device designed to interface any microprocessor/microcontroller to
a wide variety of LCOs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. The display configurations possible with the PCF8576 depend on the
number of active backplane outputs required; a selection of display configurations is given in Table 1.
Table 1 Selection of display configurations
active backplane outputs
no. of
segments
7-segment
numeric
14-segment
alphanumeric
dot matrix
4
160
20 digits +
20 indicator
symbols
10 characters +
20 indicator
symbols
160 dots
(4 x 40)
3
120
15 digits +
15 indicator
symbols
8 characters +
8 indicator
symbols
120 dots
(3 x 40)
2
80
10 digits +
10 indicator
symbols
5 characters +
10 indicator
symbols
80 dots
(2 x 40)
40
5 digits +
5 indicator
symbols
2 characters +
12 indicator
symbols
40 dots
1
All of the display configurations given in Table 1 can be implemented in the typical system shown in
Fig.3. The host microprocessor/microcontroller maintains the 2-line 12 C-bus communication channel
with the PCF8576. A resistor connected between
(pin 6) and VSS (pin 11) controls the device
clock frequency. The appropriate biasing voltages for the multiplexed LCD waveforms are generated
internally. The only other connections required to complete the system are to the power supplies
(VOO, VSS and VLCO) and to the LCD panel chosen for the application.
asc
SOA 1
HOST
MICROPROCESSOR/
MICROCONTROLLER
5
12
LCD PANEL
SCL 2
17-56
(up to 160
PCF8576
elements)
13-16 t-_4_ ba
_ ck-,-pl_an_e_s--"1/
VSS
lZ91464.2
Fig.3 Typical system configuration.
362
March
40 segment drives
19871 (
l__
Universal LCD driver for low multiplex rates
P_C_F_8_57_6_ __
Power-on reset
At power-on the PCF8576 resets to a defined starting condition as follows:
1. All backplane outputs are set to VDD.
2. All segment outputs are set to VDD.
3. The drive mode '1 : 4 multiplex with 1/3 bias' is selected.
4. Blinking is switched off.
5. Input and output bank selectors are reset (as defined in Table 5).
6. The 12 C-bus interface is initialized.
7. The data pointer and the subaddress counter are cleared.
Data transfers on the 12 C-bus should be avoided for 1 ms following power-on to allow completion of the
reset action.
LCD bias generator
The full-scale LCD voltage (V op ) is obtained from VDD - VLCD. The LCD voltage may be temperature
compensated externally through the V LCD supply to pin 12. Fractional LCD biasing voltages are obtained
from an internal voltage divider of three series resistors connected between VDD and VLCD. The centre
resistor can be switched out of circuit to provide a % bias voltage level for the 1 : 2 multiplex configuration.
LCD voltage selector
The LCD voltage selector coordinates the mu Itiplexing of the LCD according to the selected LCD drive
configuration. The operation of the voltage selector is controlled by MODE SET commands from the
command decoder. The biasing configurations that apply to the preferred modes of operation, together
with the biasing characteristics as functions of Vop = VDD - VLCD and the resulting discrimination
ratios (D), are given in Table 2.
Table 2 Preferred LCD drive modes: summary of characteristics
LCD drive mode
LCD bias
configuration
Voff (rms)
Von (rms)
Vop
Vop
static (1 BP)
static (2 levels)
0
1 : 2 MUX (2 BP)
1/2 (3 levels)
0/4
1 : 2 MUX (2 BP)
1/3 (4 levels)
1/3 = 0.333
1 : 3 MUX (3 BP)
1/3 (4 levels)
1 : 4 MUX (4 BP)
1/3 (4 levels)
= 0.333
1/3 = 0.333
1/3
D = Von (rms)
Voff (rms)
1
= 0.354
00
= 0.791
0/3 = 0.745
V33/9 = 0.638
.J3i3 = 0.577
yTO/4
I
v'5 = 2.236
.J5 = 2.236
yI33/3
= 1.915
J3 = 1.732
(MarCh 1987
363
_Jl_________
__
PC_F857_6
LCD voltage selector (continued)
A practical value for Vop is determined by equating Voff (rms) with a defined LCD threshold voltage
(Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a
suitable choice is Vop ~ 3 Vth.
Multiplex drive ratios of 1 : 3 and 1 : 4 with 1/2 bias are possible but the discrimination and hence the
contrast ratios are smaller
= 1.732 for 1: 3 multiplex orV21/3 = 1.528 for 1 : 4 multiplex).
The advantage of these modes is a reduction of the LCD full scale voltage Vop as follows:
(.J3
1 : 3 multiplex (1/2 bias) : Vop
=y6 Voff (rms) = 2.449 Voff(rms)
1 : 4 multiplex (1/2 bias) : Vop
= 4j3i3 Voff (rms) = 2.309 Voff (rms)
These compare with Vop
= 3 Voff (rms) when
1/3 bias is used.
LCD drive mode waveforms
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and
segment drive waveforms for this mode are shown in Fig.4.
1--Tframej
BPO
VDD - i l l - - - t - . - {
VLCD--
Sn
LCD segments
VDD-ru
I'
state 1
state 2
(on)
(off)
VLCDSn+1
VDD-ill
ru
VLCD----(al WAVEFORMS AT DRIVER
VOOP
state 1
At any instant (t):
V state 1(t)
0
(b) RESULTANT WAVEFORMS
AT LCD SEGMENT
7Z91465
Fig.4 Static drive mode waveforms: Vop
364
March
- VBPO(t)
Von (rms)
VOP
state 2
= Vs n (t)
= Vop
Vstate 2(t) = VSn+1 (t)
Voff (rms) = 0 V
-Vop
19871 (
= VDD
- VLCD.
- VBPO(t)
l___
Universal LCD driver for low multiplex rates
P_CF_8_5_76_ __
When two backplanes are provided in the LCD the 1 : 2 multiplex drive mode applies. The PCF8576
allows use of 1/2 or 1/3 bias in this mode as shown in Figs 5 and 6.
BPa
BP1
Sn+1
(a) WAVEFORMS AT DRIVER
Vap - - - Vap/2--state 1
At any instant (t):
a ----
Vstate 1(t)
-Vap/2 - - -
- VsPq(t)
_ Vop 11nVon (rms) - 4 V 10 - 0.791 Vop
-vap - - - vap - - - -
Vap/2---~
state 2
= VSn(t)
a-----
u-
V state 2(t)
---'
= VSn (t)
_ Vop
Voff (rms) -
- VSP 1(t)
fi)-
4" 2 -
0.354 Vop
-Vap/2---Yap - - - -
1Z91477
(b)
RESULTANT WAVEFORMS
AT LCD SEGMENT
Fig.5 Waveforms for 1 : 2 multiplex drive mode with 1/2 bias: Vop
= VOO -
1(
VLCO.
March 1987
365
_Jl_________
__
PC_F857_6
LCD drive mode waveforms (continued)
LCO segments
VOO---BPO
VOO-Vop/3VOO- 2Vop/3 VLCO
VOO
VOO-Vop/3 -VOO- 2Vop/3 -
BP1
VLCD---
~~~-Vop/3-.
VOO- 2Vop/3 VLCO---
VOO---Sn+1
VOO-Vop/3 VOO- 2Vop/3VLCO - - -
V
op
_ _ __
~
state 1
~state2
~
Lr-r-L
mm
2Vop/3---
At any instant (t):
Vop/3---
state 1
Vstate 1(t)
0----Vop/3---
= VSn(t)
- VSPO(t)
_ VOp
_
Von (rms) - 3V5 - 0.745 Vop
- 2Vo p / 3 - - -Vop----
Vstate 2(t)
Vop - - - 2Vop / 3 - - Vop/3---
state 2
- - -......
(a) WAVEFORMS AT ORIVER
= VSn(t)
- VSP1 (t)
_ Vop_
Voff (rms) - 3- 0.333 Vop
0
-Vop/3--- 2Vo p / 3 - - -Vop----
7Z91466
(b) RESULTANT WAVEFORMS
AT LCO SEGMENT
Fig.6 Waveforms for 1 : 2 multiplex drive mode with 1/3 bias: Vop
= VDD
- VLCD'
The backplane and segment drive waveform for the 1 : 3 mUltiplex drive mode (three LCD backplanes)
and for the 1 : 4 multiplex drive mode (four LCD backplanes) are shown in Figs 7 and 8 respectively.
366
March
19871 (
l___
Universal LCD driver for low multiplex rates
PC_F_8_57_6_ _
Tframe
BPa
BP1
BP2
Sn
VOO
VOO-Vop/3 Voo- 2Vop/3 VLCO--VOO
Voo-Vop/3 Voo- 2Vop/3 VLCO--VOO
Voo-Vop/3 Voo- 2Vop/3VLCO--VOO
VOO-Vop/3 VOO- 2Vop/3 VLCO - - -
Sn+1
VOO
VOO-Vop/3 VOO-2 Vop/3VLCO--VOO
Sn+2
VOO-Vop/3 VOO- 2Vop/3 VLCO--(a) WAVEFORMS AT ORIVER
Vop
2Vop/3-Vop/3---
state 1
At any instant (t) :
= VSn(t)
Vstate 1(t)
a
-Vop/3---2Vop / 3 - -
_ Vop
Von (rms) -
-Vop
Vop
2Vop / 3 - - -
Vstate 2 (t)
- VBPO(t)
_
gV'33 - 0.638 Vop
= VSn(t)
- VBP1 (t)
_ Vop_
Voff (rms) 0.333 Vop
3 -
Vop/3--state 2
a
-Vop/3---2Vop / 3 - -Vop
7Z91478
(b)
RESULTANT WAVEFORMS
AT LCO SEGMENT
Fig.7 Waveforms for 1 : 3 mUltiplex drive mode: Vop
= VOO
- VLCO.
'I (MarCh
1987
367
~j
___PC_F85_76_jl________________
LCD drive mode waveforms (continued)
Voo---BPO
VOO-Vop/3 VOO-2 Vop /3 VLCO--VOO----
BPl
BP2
BP3
VOO-Vop/3 VOO- 2Vop/3VLCO--VOO---VOO-Vop/3VOO-2 Vop/3VLCO--VOO---VOO-Vop/3VOO- 2Vop/3VLCO--VOO---VOO-Vop/3 VOO-2 Vop/3VLCO--VOO---VOO-Vop/3-
Sn+1
Sn+2
VOO-2 Vop/3VLCO--VOO---VOO-Vop/3 VOO-2 Vop /3 VLCO--VOO----
Sn+3
VOO-Vop/3VDO-2Vop / 3 VLCO--(a)
WAVEFORMS AT DRIVER
Vop - - - 2Vop/3--Vop/3--state 1
0 ----Vop/3---
At any instant (t):
=
V state 1(t)
VSn(t) - VBPO(t)
-2Vop / 3 - - -Vop---Vop - - - 2Vop/3---
Von (rms)
=
Vop Pi
Ty3 = 0.577 Vop
Vop/3--state 2
0 ----
=
Vstate 2(t)
-Vop/3 - - - 2Vo p / 3 - - -Vop - - - -
VSn(t) - VBP1(t)
(b)
Voff (rms)
RESULTANT WAVEFORMS
AT LCD SEGMENT
=
Vop
T= 0.333 Vop
7Z91479
Fig.8 Waveforms for 1 : 4 mUltiplex drive mode: Vop
368
March
19871 (
= VDD
- V LCD.
L:._8_5_76___
Universal LCD driver for low mUltiplex rates
Oscillator
Internal clock
The internal logic and the LCD drive signals of the PCF8576 are timed either by the built-in oscillator
or from an external clock. When the internal oscillator is used, frequency control is performed by a
single resistor connected between OSC (pin 6) and VSS (pin 11) as shown in Fig.9. In this application,
the output from CLK (pin 4) provides the clock signal for cascaded PCF8576s in the system.
7Z91467 1
1000
fCLK
(kHz) 500
200
100
","
"
"
50
' "'r"max
I
l'
min
~"
"'
20
10
100
I'"
"-'
200
500
1000
2000
5000
Rose (kn)
Fig.9 Oscillator frequency
as a function of Rose:
fCLK ~ (3.4 x 107 /Rosel kHz·n.
External clock
The condition for external clock is made by tying OSC (pin 6) to VDD; CLK (pin 4) then becomes the
external clock input.
The clock frequency (fCLK) determines the LCD frame frequency and the maximum rate for data
reception from the 12 C-bus. To allow 12 C-bus transmissions at their maximum data rate of 100 kHz,
fCLK should be chosen to be above 125 kHz.
A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a
DC state.
Timing
The timing of the PCF8576 organizes the internal data flow of the device. This includes the transfer
of display data from the display RAM to the display segment outputs. In cascaded applications, the
synchronization signal SYNC maintains the correct timing relationship between the PCF8576s in the
system. The timing also generates the LCD frame frequency which it derives as an integer multiple of
the clock frequency (Table 3). The frame frequency is set by the choice of value for Rosc when internal
clock is used, or by the frequency applied to pin 4 when external clock is used.
Table 3 LCD frame frequencies
PCF8576 mode
normal mode
power-saving mode
recommended Rosc (kn)
180
1200
fframe
nominal fframe (Hz)
fCLK/2880
64
fCLK/480
64
1(MarCh
1987
369
_Jl________
__
PC_F85_76
Timing (continued)
The ratio between the clock frequency and the LCD frame frequency depends on the mode in which
the device is operating. In the normal mode, Rosc = 180 kil will result in the nominal frame frequency.
In the power-saving mode the reduction ratio is six times smaller; this allows the clock frequency to be
reduced by a factor of six and for the same frame frequency Rosc will be 1.2 Mil. The reduced clock
frequency and the increased value of Rosc together contribute to a significant reduction in power
dissipation. The lower clock frequency has the disadvantage of increasing the response time when large
amounts of display data are transmitted on the 12 C-bus. When a device is unable to 'digest' a display
data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored.
This slows down the transmission rate of the 12 C-bus but no data loss occurs.
Display latch
The display latch holds the display data while the corresponding multiplex signals are generated. There
is a one-to-one relationship between the data in the display latch, the LCD segment outputs and one
column of the display RAM.
Shift register
The shift register serves to transfer display information from the display RAM to the display latch while
previous data is displayed.
Segment outputs
The LCD drive section includes 40 segment outputs SO to S39 (pins 17 to 56) which should be connected
directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with the data resident in the display latch. When less than 40 segment outputs are
required the unused segment outputs should be left open.
Backplane outputs
The LCD drive section includes four backplane outputs BPO to BP3 which should be connected directly
to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode.
If less than four backplane outputs are required the unused outputs can be left open. In the 1 : 3 multiplex drive mode BP3 carries the same signal as BP 1, therefore these two adjacent outputs can be tied
together to give enhanced drive capabilities. In the 1 : 2 multiplex drive mode BPO and BP2, BP1 and
BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the
static drive mode the same signal is carried by all four backplane outputs and they can be connected in
parallel for very high drive requirements.
Display RAM
The display RAM is a static 40 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map
indicates the 'on' state of the corresponding LCD segment; similarly, a logic 0 indicates the 'off' state.
There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between
the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the
40 segments operated with respect to backplane BPO (Fig.10). In multiplexed LCD applications the
segment data of the second, third and fourth column of the display RAM are time-multiplexed with
BP 1, BP2 and BP3 respectively.
370
March
19871 (
l___
Universal LCD driver for low multiplex rates
PC_F_8_5_76_ __
display RAM addresses (rows) / segment outputs (S)
display RAM bits
(columns) /
backplane outputs
(BP)
7Z91468
Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses and segment
outputs, and between bits in a RAM word ana backplane outputs.
When display data are transmitted to the PCF8576 the display bytes received are stored in the display
RAM according to the selected LCD drive mode. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Fig.11; the RAM filling organization depicted
applies equally to other LCD types.
With reference to Fig.11, in the static drive mode the eight transmitted data bits are placed in bit 0 of
eight successive display RAM addresses. In the 1 : 2 multiplex drive mode the eight transmitted data
bits are placed in bits 0 and 1 of four successive display RAM addresses. In the 1 : 3 multiplex drive
mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address
left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overriding adjacent data because full bytes are always transmitted. In the
1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1,2 and 3 of two successive display RAM addresses.
Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading
of an individual display data byte, or a series of display data bytes, into any location of the display
RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER
command. Following this, an arriving data byte is stored starting at the display RAM address indicated
by the data pointer thereby observing the filling order shown in Fig.11. The data pointer is automatically incremented according to the LCD configuration chosen. That is, after each byte is stored, the
contents of the data pointer are incremented by eight (static drive model, by four (1 : 2 multiplex
drive mode), by three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex drive mode).
Subaddress counter
The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed
to take place only when the contents of the subaddress counter agree with the hardware subaddress applied
to AO, A 1 and A2 (pins 7,8, and 9). The subaddress counter value is defined by the DEVICE SE LECT
command. If the contents of the subaddress counter and the hardware subaddress do not agree then data
storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress
counter is also incremented when the data pointer overflows.
1
(MarCh 1987
371
w
.....
N
-u
drive mode
..,
Q)
(')
::T
5 n +3
<0
00
n
msb
bit/ 0
BP 1
2
3
G ~S"
5 n +5- e
5~+7
c
5n+6-~
1:2
multiplex
OOP
S"::~ : B
bit/ 0
BP 1
2
3
~oP
d
8P0[1]
8Pa
5 n +1
1:3
multiplex
OP
1:4
rib
9
multiplex
e
c
5 n +1-~-----
c
x
x
x
n
S"·'9
5 n+3-C=
o."
8PQ..q;J),8"
8"SJ
"
OP
01
.........
0>
n+1 n+2 n+3 n+4 n+5 n+6 n+7
b '5 n +1
5 n +4 -c=I::)
static
transmitted display byte
(X)
S"·,£DB
-tl
s::
.....
display RAM filling order
LCD backplanes
LCD segments
BP3
~
a
b
x
x
n
bit/ 0 b
BP 1 DP
2 c
3 x
n
b
x
x
x
a
x
x
x
f
x
x
x
n+1 n+2 n+3
f
9
x
x
e
c
x
x
n+1 n+2
a
d
f
e
9
X
x
x
9
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
-------------
msb
Isb
I alblflglelcldlDP
X
----------
----- ---- -
-
- ---
msb
Isb
I blDPlclaldlglfle
----------------
n+1
----- --------------bit/ 0 a
BP 1 c
2 b
3 DP
I clblalflgleldlDp I
X
d
DP
x
Isb
f
e
Isb
I alclblDPlflelgld
9
d
msb
---- -------- -------
-----
Fig. 11 Relationships between LCD layout, drive mode, display RAM filling order
and display data transmitted over the PC bus (x = data bit unchanged).
7Z91469
PCF8576
Universal LCD driver for low mUltiplex rates
Subaddress counter (continued)
The storage arrangements described lead to extremely efficient data loading in cascaded applications.
When a series of display bytes are being sent to the display RAM, automatic wrap-over to the next
PCF8576 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is
successful even if the change to the next device in the cascade occurs within a transmitted character
(such as during the 14th display data byte transmitted in 1 : 3 multiplex mode).
Output bank selector
This selects one of the four bits per display RAM address for transfer to the display latch. The actual
bit chosen depends on the particular LCD drive mode in operation and on the instant in the multiplex
sequence. In 1 : 4 multiplex, all RAM addresses of bit 0 are the first to be selected, these are followed
by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected
sequentially. In 1 : 2 multiplex, bits 0 then 1 are selected and, in the static mode, bit 0 is selected.
The PCF8576 includes a RAM bank switching feature in the static and 1 : 2 multiplex drive modes. In
the static drive mode, the BAN K SE LECT command may request the contents of bit 2 to be selected
for display instead of bit 0 contents. In the 1 : 2 drive mode, the contents of bits 2 and 3 may be
selected instead of bits 0 and 1. This gives the provision for preparing display information in an
alternative bank and to be able to switch to it once it is assembled.
Input bank selector
The input bank selector loads display data into the display RAM according to the selected LCD drive
configuration. Display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 drive
mode by using the BANK SE LECT command. The input bank selector functions independently of the
output bank selector.
Blinker
The display blinking capabilities of the PCF8576 are very versatile. The whole display can be blinked
at frequencies selected by the BLINK command. The blinking frequencies are integer multiples of the
clock frequency; the ratios between the clock and blinking frequencies depend on the mode in which
the device is operating, as shown in Table 4.
An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the
static and 1 : 2 LCD drive modes and can be implemented without any communication overheads. By
means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks
at the blinking frequency. This mode can also be specified by the BLINK command.
In the 1 : 3 and 1 : 4 multiplex modes, where no alternate RAM bank is available, groups of LCD
segments can be blinked by selectively changing the display RAM data at fixed time intervals.
If the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can
be effectively performed by resetting and setting the display enable bit E at the required rate using the
MODE SET command.
1
(March 1987
373
_Jl____________
__
PCF_857_6
Blinker (continued)
Table 4 Blinking frequencies
blinking mode
. . normal operating
mode ratio
power-saving
mode ratio
nominal blinking frequency
fblink (Hz)
-
blinking off
2
off
-
2 Hz
fCLK/92160
fCLK/15360
1 Hz
fCLK/184320
fCLK/30720
1
0.5 Hz
fC LK/368640
fCLK/61440
0.5
CHARACTERISTICS OF THE FC-BUS
The 12 C-bus is for 2-way,2-line. communication between different ICs or modules. The two lines are
a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated
only "'vhen the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted
as control signals.
SDA --t.._01--.--_______
~X~-4-----~~
---~
SCL
data line
stable:
data valid
change
of data
allowed
7Z87019
Fig.12 Bit transfer.
Start and stop conditions
Both data and clock linesremain HIGH when the bus is not busy. A HIGH-to-LOW transition of the
data line while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of
the data line while the clock is HIGH is defined as the stop condition (P).
SOA
--+\-1
I
SCL
I
:
:
: s:
L _ _ _ .l
start condition
\
iit---
;-n~
.
/r---,\. . __--II
....- + I - - - - - L - - - -
I
____
--.lo-_ _ _ _ _+I...J·
1(
March 1987
I
of
I
!!
SCL
L ___ J
stop condition
Fig.13 Definition of start and stop conditions.
374
SOA
I
I
7Z87005
l___
Universal LCD driver for low multiplex rates
P_CF_8_5_76_ _ _--'
System configuration
A device generating a message is a "transmitter", a device receiving a message is a "receiver". The
device that controls the message is the "master" and the devices which are controlled by the master
are the "slaves".
SDA------~------_.----------~------------~------------~--
SCl--~------~----~------_+----~~------~----~------~----~------_t--
F ig.14 System configu ration.
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is not limited. Each byte is followed by one acknowledge bit. The acknowledge bit is a HIGH
level put on the bus by the transmitter whereas the master generates an extra acknowledge related
clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during
the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver
must signal an end of data to the transmitter by not generating an acknowledge on the last byte that
has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable
the master to generate a stop condition.
start
condition
I
clock pulse for
acknowledgement
~
I
SCl FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
I
I
I
I
I
--~
~'---.L....-/_X'----_K~~)(
I
7
S
DATA OUTPUT
BY RECEIVER
-~
7Z87007
F ig.15 Acknowledgement on the 12C bus.
Note
The general characteristics and detailed specification of the 12 C bus are described in a separate data
sheet (serial data buses) in handbook: ICs for digital systems in radio, audio and video equipment.
'1 (
March 1987
375
_Jl________
__
PC_F85_76
PCF8576 12 C-bus controller
The PCF8576 acts as an 12 C slave receiver. It does not initiate 12 C-bus transfers or transmit data to an
12 C master receiver. The only data output from the PCF8576 are the acknowledge signals of the selected
devices. Device selection depends on the 12 C-bus slave address, on the transferred command data and on
the hardware subaddress.
In single device applications, the hardware subaddress inputs AD, Aland A2 are normally tied to VSS
which defines the hardware subaddress O. In multiple device applications AD, Aland A2 are tied to VSS
or VDD according to a binary coding scheme such that no two devices with a common 12 C slave address
have the same hardware subaddress.
in the power-saving mode it is possible that the PCF8576 is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. If this situation occurs, the PCF8576
forces the SCL line LOW until its internal operations are completed. This is known as the 'clock
synchronization feature' of the 12 C-bus and serves to slow down fast transmitters. Data loss does not
occur.
Input filters
To enhance noise immunity in electrically adverse environments, HC low-pass filters are provided on
the SDA and SCL lines.
F C-bus protocol
Two 12 C-bus slave addresses (0111000 and 0111001) are reserved for PCF8576. The least-significant
bit of the slave address that a PCF8576 will respond to is defined by the level tied at its input SAO
(pin 10). Therefore, two types of PCF8576 can be distinguished on the same 12 C-bus which allows:
(a) up to 16 PCF8576s on the same 12 C-bus for very large LCD applications;
(b) the use of two types of LCD multiplex on the same 12 C-bus.
The 12 C-bus protocol is shown in Fig.16. The sequence is initiated with a start condition (S) from the
12 C-bus master which is followed by one of the two PCF8576 slave addresses available. All PCF8576s
with the corresponding SAO level acknowledge in parallel the siave address but all PCF8576s with the
alternative SAO level ignore the whole 12 C-bus transfer. After acknowledgement, one or more command
bytes (m) follow which define the status of the addressed PCF8576s. The last command byte is tagged
with a cleared mist significant bit, the continuation bit C. The command bytes are also acknowledged
by all addressed PCF8576s on the bus.
After the last command byte, a series of display data bytes (n) may follow. These display data bytes
are stored in the display RAM at the address specified by the data pointer and the subaddress counter.
Both data pointer and subaddress counter are automatica!ly updated and the data are directed to the
intended PCF8576 device. The acknowledgement after each byte is made only by the (AD, A 1, A2)
addressed PCF8576. After the last display byte, the 12 C-bus master issues a stop condition (P).
376
March 19871 (
L:_8_57_6___
Universal LCD driver for low multiplex rates
acknowledge by
(AO, Al, A2l-selected
PCF8576 only
R/W
~
slave address
l
acknowledge by all
.addressed PCF8576st
+
'-----,y--------'
I
1 byte
m;;;' 1 bytes
n;;;' 0 bytE'S
t
update data pointer
and, if necessary,
subaddress counter
lZ91410.2
Fig.16 12 C-bus protocol.
Command decoder
The command decoder identifies command bytes that arrive on the 12 C-bus. All available commands
carry a continuation bit C in their most-significant bit position (Fig.17). When this bit is set, it indicates
that the next byte of the transfer to arrive will also represent a command. If the bit is reset, it indicates
the last command byte of the transfer. Further bytes will be regarded as display data.
o= last command
1 = commands continue
7Z9147i
F ig.17 General format of command byte.
The five commands available to the PCF8576 are defined in Table 5.
1
(MarCh 1987
377
_Jl_________
__
PC_F85_76
Command decoder (continued)
Table 5 Definition of PCF8576 commands
command/opcode
options
description
Defines LCD drive mode
LCD drive mode
bits M1
MO
MODE SET
Ic 11 0 ILPIE IBIM11 MO
I
static (1 BP)
1 : 2 MUX (2 BP)
1 : 3 MUX (3 BP)
1 : 4 MUX (4 BP)
0
1
1
0
1
0
1
0
Defines LCD bias configuration
LCD bias
B
bit
1/3 bias
1/2 bias
0
1
display status
Defines display status
The possibility to disable the
display allows implementation
of blinking under external
control
E
bit
disabled (blank)
enabled
0
1
Defines power dissipation mode
mode
LP
bit
normal mode
power-saving mode
0
1
LOAD DATA POINTER
bits
P5
P4
P3
P2
P1
PO
Iclolp5 P4 P3 P2 P1 pol
6-bit binary value of 0 to 39
DEVICE SELECT
bits
Ic 11 1 o OlA2 A1 AOI
378
March 19871 (
AO A1
3-bit binary value of 0 to 7
A2
Six bits of immediate data,
bits P5 to PO, are transferred
to the data pointer to define
one of forty display RAM
addresses
Three bits of immediate data,
bits AO to A2, are transferred
to the subaddress counter to
define one of eight hardware
su baddresses
l___
Universal LCD driver for low mUltiplex rates
PC_F_8_57_6_ __
command/opcode
options
description
BANK SELECT
Ic 11
1 1 1 0
1'10 I
static
1 : 2 MUX
RAM bit 0
RAM bit 2
RAM bits 0, 1 0
RAM bits 2, 3 1
static
1 : 2 MUX
RAM bit 0
RAM bit 2
RAM bits 0, 1 0
RAM bits 2, 3 1
bit I
bit
a
Defines input bank selection
(storage of arriving display data)
Defines output bank selection
(retrieval of LCD display data)
The BANK SELECT command has
no effect in 1 : 3 and 1 : 4 multiplex d rive modes
BLINK
Defines the blinking frequency
blink frequency
bitsBFl
BFO
IC 11 1 1 0lAIBF1 BFOI
off
2 Hz
1 Hz
0.5 Hz
0
0
1
1
0
1
0
1
blink mode
bit A
normal blinking
alternation blinking
0
1
Selects the blinking mode;
normal operation with frequency
set by bits BF1, BFO, or
blinking by alternation of
display RAM banks. Alternation
,blinking does not apply in 1 : 3
and 1: 4 multiplex drive modes
Display controller
The display controller executes the commands identified by the command decoder. It contains the
status registers of the PCF8576 and coordinates their effects. The contr.o'ller is also responsible for
loading display data into the display RAM as required by the filling order.,
1(
March 1987
379
_Jl_________
__
PC_F857_6
Cascaded operation
In large display configurations, up to 16 PCF8576s can be distinguished on the same 12 C-bus by using
the 3-bit hardware subaddress (AD, A 1, A2) and the programmable 12 C slave address (SAO). It is also
possible to cascade up to 16 PCF8576s. When cascaded, several PCF8576s are synchronized so that they
can share the backplane signals from one of the devices in the cascade. Such an arrangement is costeffective in large LCD applications since the backplane outputs of only one device need to be throughplated to the backplane electrodes of the display. The other PCF8576s of the cascade contribute
additional segment outputs but their backplane outputs are left open (Fig.18). '
The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8576s.
This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be
needed is if synchronization is accidently lost (e.g. by noise in adverse electrical environments; or by
the definition of a multiplex mode when PCF8576s with differing SAO levels are cascaded). SYNC is
organized as an input/output pin; the output section being realized as an open-drain driver with an
internal pull-up resistor. A PCF8576 asserts the SYNC line at the onset of its last active backplane
signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it
will be restored by the first PCF8576 to assert SYNC. The timing relationships between the backplane
waveforms and the SYNC signal for the various drive modes of the PCF8576 are shown in Fig.19.
I I I I I I I
I I I I I I I
I I I I I I I
LCD PANEL
5
~ SDA 1
(up to 2560
elements)
V LCD
V DD
12
SCL 2
40 segment drives
17-56
SYNC 3
PCF8576
CLK 4
OSC 6
7
r
8
lAO
13-16
~
rTss
10
9
A2
>
"V
11
BPO- BP3 (open)
VLCD
VDD
R< t'i~ ~
VDD
2Cbus
SDA 1
HOST
MICROPROCESSOR/
MICROCONTROLLER
VLCD
12
5
SCL 2
SYNC 3
17-56
PCF8576
CLK 4
R~r 6lAO jA'
13-16
9
10
11
40 segment drives-)
V
4 backplanes
BPO to BP3
A2 rO!Vss
VSS
Fig.18 Cascaded PCF8576 configuration.
380
March
19871 (
~
~
lZ91480,3
l__
Universal LCD driver for low multiplex rates
P_C_F_8_57_6_ __
1
,BPO
SYNC
Tframe
= fframe
l
lJ
(a)
STATIC DRIVE MODE
u
r
r
BP1
(112
bias)
BP1
(1/3 bias)
SYNC
I
--,
lJ
(b)
1: 2 MULTIPLEX DRIVE MODE
U
lJ
(e)
1: 3 MULTIPLEX DRIVE MODE
U
lJ
(d)
1: 4 MULTIPLEX DRIVE MODE
U
BP2
SYNC
BP3
SYNC
7Z91481
Note
Excessive capacitive coupling between SCL or ClK and SYNC may cause erroneous synchronization.
If this proves to be a problem, the capacitance of the SYNC line should be increased (e.g. by an external
capacitor between SYNC and VDD). Degradation of the positive edge of the SYNC pulse may be
countered by an external pull-up resistor.
Fig.19 Synchronization of the cascade for the various PCF8576 drive modes.
For single plane wiring of packaged PCF8576s and chip-on-glass cascading, see 'APPLICATION
INFORMATION'.
'I (
March 1987
381
_J l""----_ _ _ _ _ _ __
__
PCF_857_6
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage range
VDD
LCD supply voltage range
VLCD
Input voltage range (SCL; SDA;
AO to A2; OSC; CLK; SYNC; SAO)
VI
-0,5 to + 11 V
VDD-11 to VOD V
VSS-0,5 to VDD + 0,5 V
Output voltage range (SO to S39;
BPO to BP3)
Va
VLCD-0,5 to VDD + 0,5 V
D.C. input current
± II
max.
20 mA
D.C. output current
± 10
max.
25 mA
VOD, VSS or V LCO current
± IDD, ± ISS, ± I LCD
Ptot
max.
50 mA
Power dissipation per package
max.
400 mW
Power dissipation per output
Po
max.
Storage temperature range
T stg
100 mW
-65 to + 150 oC
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MaS devices (see
'Handling MaS Devices').
D.C. CHARACTERISTICS
VSS = 0 V; VOD = 2 to 9 V; VLCD = VOO-2 to VOO-9 V;
T amb = -40 to + 85 oC; unless otherwise specified
parameter
symbol
min.
typo
max.
unit
Operating supply voltage
VDD
2
9
V
VOO-2
V
LCD supply voltage (note 1)
VLCO
VOD-9
-
Operating supply current (normal mode)
at fCLK = 200 kHz (note 2)
IDD
-
-
180
J.l.A
Power-saving mode supply current
at VDD = 3,5 V; VLCD = 0 V;
fCLK = 35 kHz (note 2)
ILP
-
-
60
J.l.A
VIL
VSS
-
0,3 VDD
V
Logic
I nput voltage LOW
Input voltage HIGH
382
VIH
0,7 VDD
-
Output voltage LOW at 10
VOL
-
-
VDD
0,05
V
Output voltage HIGH at
= 0 mA
10 = 0 mA
V
VOH
VDD-0,05
-
-
V
Output current LOW (CLK, SYNC) at
VOL = 1,0 V; VDD = 5 V
10L1
1
-
-
mA
Output current HIGH (CLK) at
Va H = 4,0 V; V D D = 5 V
10H
-
-
-1
mA
Output current LOW (SDA; SCL) at
Va L = 0,4 V; V D D = 5 V
IOL2
3
-
-
mA
leakage current (SAO; AO to A2; ClK;
SCl; SDA) at VI = VSS or VDD
± 'L1
-
-
1
J.l.A
March
19871 (
PCF8576
Universal LCD driver for low multiplex rates
parameter
symbol
leakage current (OSC)
at VI = VOO
± IL2
Pull-up resistor (SYNC)
min.
typo
max.
unit
-
-
1
J.lA
50
150
kn
RSYNC
20
Power-on reset level (note 3)
VREF
-
1,0
1,6
V
Tolerable spike width on bus
tsw
-
100
ns
Input capacitance (note 4)
CI
-
-
7
pF
O.C. voltage component (BPO to BP3)
at CBP = 35 nF
± VBP
-
20
-
mV
O.C. voltage component (SO to S39)
at Cs = 5 nF
± Vs
-
20
-
mV
Output impedance (BPO to BP3)
at VLCO = VOO-5 V (note 5)
RBP
-
-
5
kn
Output impedance (SO to S39)
at VLCO = VOO-5 V (note 5)
RS
-
-
7,0
kQ
LCD outputs
A.C. CHARACTERISTICS (note 6)
VSS
= a V; VOO = 2 to 9 V; VLCO = VOO-2 to VOO-9 V;
Tamb = -40 to + 85 oC; unless otherwise specified
parameter
symbol
min.
typo
max.
unit
Oscillator frequency (normal mode)
at VOO = 5 V; Rosc = 180 kn
(note 7)
fCLK
125
185
288
kHz
Oscillator frequency (power-saving
mode) at VOO = 3,5 V; Rosc = 1,2 Mn
fCLKLP
21
31
48
kHz
ClK HIGH time
tCLKH
1
-
-
J.lS
ClK lOW time
tCLKL
1
-
-
J.lS
SYNC propagation delay
tpSYNC
-
-
400
ns
SYNC LOW time
tSYNCL
1
-
-
J.lS
Oriver delays with test loads at
VLCO = VOO-5 V
tPLCO
-
-
30
J.lS
1
(March 1987
383
___
PC_F857_B_Jl________________
A.C. CHARACTERISTICS (continued)
parameter
symbol
min.
typo
max.
unit
Bus free time
tBUF
4,7
-
tHO; STA
4
-
-
fJ.S
Start condition hold time
SCL LOW time
tLOW
4,7
-
-
fJ.S
SCL HIGH time
tHIGH
4
-
-
fJ.S
Start condition set-up time
(repeated start code only)
tsu; STA
4,7
-
-
fJ.S
-
fJ.S
12 C bus
fJ.S
Oata hold time
tHO; OAT
0
-
Oata set-up time
tsu; OAT
250
-
-
ns
Rise time
tR
-
-
1
fJ.S
Fall time
tF
-
.-
300
ns
Stop condition set-up time
tsu; STO
4,7
-
-
fJ.S
2
1 C
bus inactive.
Notes to characteristics
1. VLCO';;;;; VOO-3 V for 1/3 bias.
2. Outputs open; inputs at VSS or VOO; external clock with 50% duty factor;
3. Resets all logic when VOO
< VREF.
4. Periodically sampled, not 100% tested.
5. Outputs measured one at a time.
6. All timing values referred to VI H and VI L levels with an input voltage swing of VSS to VOO.
7. At fCLK
384
< 125 kHz, 12 C bus maximum transmission speed is derated.
March
19871 (
l___
Universal LCD driver for low mUltiplex rates
P_C_F8_5_76_ __
1.5 kn
SDA,SCl~v
(pins 1 2)
DD
,
(2%)
ClK
3.3 kn
( in4)~O.5VDD
p
(2%)
--
6.Sn
SYNC~V
(pin 3)
(2%)
DD
1 nF
BPO
to BP3
(pins 13 to 16)
----I ~ V
.--
1 nF
SO
to S39
(pins 17 to 56)
DD
----II-- V DD
7Z91472.3
Fig. 20 Test loads.
1
fClK
-tCLKH-I-tCLKL-I
elK
~_ _ _ _ _ _
0.5V
t
BPO to BP3
SO to 539
(VDD = 5V)
'--_ _ _ _ _~0.5 V
7Z91473.2
Fig.21 Driver timing waveforms.
1(
March 1987
385
_J
__
PC_F857_6
l""---_ _ _ _ _ _ __
SDA
SCL
-
tHD;STA -
SDA
tSU;STA
7Z87013.2
Fig. 22 12 C bus timing waveforms.
386
March
19891 (
----
t SU;STO
l___
Universal LCD driver for low multiplex rates
PC_F_8_5_76_ __
7Z80829
50
-Iss
,/
I
(~)
40
(~)
40
/
30
30
/
/
20
/
it,.VI-'
o
V
/
V
10
./
20
Vpower-saving
.
V
V
V
~-
mode
10
I
o
100
o
200
fframe(Hz)
(a) VOO = 5 V; VLCO = 0 V; Tamb = 25°C.
V
normal mode
fCLK=200kHz
40
,/
30
1/
1/
V
10
200
fframe(Hz)
7Z80832
50
II
(~)
01
85 C/
40
/
/
/V
/
30
VV
V
/'"
V
fC~K=135kliT
V
1/
25°C ,/
/1-"
20
. / ~wer-Saving mode
I~V
100
-ILCO
II
V
20
o
V
o
(b) VOO = 5 V; VLCO = 0 V; Tamb = 25°C.
7Z80831
50
-ISS
(~)
7Z80830
50
-ILCO
/
normal
madlY
I
/
lL
10
J~
V
~
lL
./
V
./
~
..IV
V
/
../V
V ~ooc
~
0
o
5
10
VOO (V)
0
5
VOO (V)
10
(e) VLCO = 0 V; external clock;
(d) VLCO = 0 V; external clock;
Tamb = -40 to + 85 °C.
fCLK = nominal frequency.
Fig. 23 Typical supply current characteristics.
7Z80833
10
7Z80834
C 2,5
C
~
~
\.
OJ
"-
(.)
c:
a5
1:l
Ql
OJ
(.)
lij 2,0
i'..
1:l
1\ i'-.. ......... --..
~
"~ r-......
0.
.§
E
:l
E
'xa5
E
Ql
--
0.
.§
RS
§
-
-
r-
.-.. AS
~
V"'"
1,5
E
'xa5
RSp-
E
1,0
RSp
L---
I---,...-
0,5
0,1
o
2
4
6
8
10
o
-40
o
40
VOo(V)
(a) VLCO = 0 V; Tamb = 25°C.
80
120
Tamb(°C)
(b) VOO = 5 V; VLCO = 0 V.
Fig. 24 Typical characteristics of LCD outputs.
'] (
March 1987
387
~
00
"'U
()
APPLICATION INFORMATION
5DA
5CL
s:
"01
(X)
.......
0')
~
n
::J'"
(0
ex>
"'-J
0 5C
D
AO
Rose
A1
A2
5AO
Vss
.------------------BP1
r----------------BP3
.------------
50
51
52
53
-57
-58
- 59
J
BACKPLANE5
50
m
J [~~~
539
538537536535534533532531530529528527526525524523522521-
open
{"PO
BP2
BP1
BP3
!;540
-541
-542
-543
517516515514 -
-547
-548
-549
:~J 1513 539
540
m
m
JI.~~~
579
578577576575574573572571570569568567566565564563562561557556555554-
:::,J ISS3 S79
m
~l____________________________________________________~___________________________________________________
5EGMENT5
Fig. 25 Single plane wiring of packaged PCF8576s.
7Z91482.2
Universal LCD driver for low multiplex rates
l___
P_C_F8_5_7_6_ __
Chip-on-glass cascadability in single plane
In chip-on-glass technology, where driver devices are bonded directly onto the glass of the lCD, it is
important that the devices may be cascaded without the crossing of conductors, but the paths of
conductors can be continued on the glass under the chip. All of this is facilitated by the PCF8576
bonding pad layout (Fig. 26). Pads needing bus interconnection between all PCF8576s of the cascade
are VDD, VSS, VlCD, ClK, SCl, SDA and SYNC. These lines may be led to the corresponding pads of
the next PCF8576 through the wide opening between VlCD pad and the backplane output pads.
The only bussed line that does not require a second opening to lead through to the next PCF8576 is
V lCD, being the cascade centre. The placing of V LCD adjacent to VSS allows the two supplies to be
tied together.
Fig.27 shows the connection diagram for a cascaded PCF8576 application with single plane wiring.
Note the use of the open space between the VlCD pad and the backplane output pads to route VDD,
VSS, ClK, SCl, SDA and SYNC. The external connections may be made to either end of the cascade,
wherever most convenient for the connector.
When an external clocking source is to be used, asc of all devices should be tied to VDD. The pads
asc, AO, A 1, A2 and SAO have been placed between VSS and VDD to facilitate wiring of oscillator,
hardware subaddress and slave address.
1
(MarCh 1987
389
_Jl_________
__
PC_F857_6
APPLICATION INFORMATION (continued)
r-.
<.0
l!)
'OJ"
C')
Vi
Vi
Vi
Vi
Vi Vi
N
0
Vi
Vi
Ol
CXl
r-.
(f)
(f)
(f)
(0
(f)
'OJ"
l!)
(f)
(f)
DDDDDDDDDDDD 0 0
518
519
520
521
522
523
524
525
0
0
D
D
0
0
0
D
D
0
0
D
D
4,12
mm
51
50
BP3
0
BP1
0
0
BP2
BPO
D
I \vLCD
PCF8576
526
527
528
529
530
S31
532
_
53
52
D
0
0
0
0
0
0
cascade
centre
~~D21
--'-_ _
S3.,.-3_k-D
________________
vD DODD DOD 0 DOD 0
o /, 'OJ"
l!)
(0
r-.
CXl
Ol
<{
-l
1<->
~
0
<->
a lh lh lh lh lh lh g ii5 I~ d ~ ~
1 - - - - - - - 3,07 mm
0
<{
---.7Z91474.3
Fig.26 PCF8576 bonding pad locations.
390
March
19871 (
:::
l___
Universal LCD driver for low multiplex rates
P_C_F8_5_76_ __
Bonding pad locations
All x/V coordinates are referenced to left-hand bottom corner (0/0, Fig. 26).
Dimensions in ~m
pad
x
y
160
bottom
VDD
OSC
AO
A1
160
380
580
780
980
1180
1380
1580
1780
1980
2180
2400
2640
2910
160
bottom
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
160
380
580
780
980
1180
1380
1580
1780
1980
2180
2400
2640
2910
3960
top
S34
S35
S36
S37
S38
S39
SDA
SCl
SYNC
ClK
pad
x
y
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
160
400
640
860
1060
1260
1460
1660
1860
2260
2460
2660
2860
3060
3260
3480
3720
160
left
left
~
3960
top
A2
SAO
2910
VSS
VlCD
BPO
BP2
BP1
BP3
SO
S1
S2
S3
2910
2880
2910
360
560
760
960
2360
2560
2760
2960
3160
3360
3560
3760
:
2910
'I
right
right
(March 1987
391
w
c.o
N
-u
o11
APPLICATION INFORMATION (continued)
(X)
01
s:
~
n
:J
c.o
co
-....J
-...J
VlCD
VSS
VSS
VDD
~---------------------ClK
r-----------------SYNC
ClK
~---------------------SCl
()
SYNC
SCl
~-----------------
(',
SDA
(>
~
~~"-
(open)
<> ~. .
O~~"
~~~ 0
PCF8576
o
oo
PCF8576
0<>
o
0°
o
0°
00
o
00
00
00
o 0°
00°
0
00
S79
S40 I
0 00
00
00
00
0o
00
0°
o 0°
000
I S39
SO
' L---~
~-----------------------------------------------------v
segments
backplanes
7Z91483.1
Fig. 27 Chip-an-glass application; cascaded PCF8576s with single-plane wiring (viewed from back of chip)'
m
DEVELOPMENT DATA
PCF8577
PCF8577A
This data sheet contains advance information and
specifications are subject to change without notice.
LCD DIRECT IDUPLEX DRIVER WITH 12 C-BUS INTERFACE
GENERAL DESCRIPTION
The PCF8577 is a single chip, silicon gate CMOS circuit. It is designed to drive liquid crystal displays
with up to 32 segments directly, or 64 segments in a duplex manner.
The two-line 12 Cbus interface substantially reduces wiring overheads in remote display applications.
Bus traffic is minimized in multiple IC applications by automatic address incrementing, hardware subaddressing and display memory switching (direct drive mode).
The PCF8577 and PCF8577 A differ only in their slave addresses.
Features
•
•
•
•
•
•
•
•
•
•
•
Direct/duplex drive modes with up to 32/64 LCD-segment drive capabilitv per device
Operating supply voltage: 2.5 to 9 V
Low power consumption
12 C-bus interface
Optimized pinning for single plane wiring
Single-pin built-in oscillator
Auto-incremented loading across device subaddress boundaries
Display memory switching in direct drive mode
May be used as 12 C-bus output expander
System expansion up to 256 segments (512 segments with PCF8577 A)
Power-on-reset blanks display
1
SCL
39
r--
SDA
12 C-BUS
INPUT
FI LTERS
12 C BUS
40
t,
II
CONTROLLER
1+-+
T
38
~
I
II~~
PCF8577
PCF8577A
32
DRIVERS
-
t
COMPARATOR
34
36
III
CONTROL REGISTER
AND
37
t
-
S32
BACKPLANE
AND
SEGMENT
33
35
I POWER-I
ONRESET
f-+-
SEGMENT BYTE
REGISTERS
AND
MULTIPLEX
LOGIC
S1
BP1
A2/BP2
A1
AO/OSC
OSCILLATOR
AND
DIVIDER
1
6
7Z87556.3
Fig.1 Block diagram.
PACKAGE OUTLINES
PCF8577P, PCF8577 AP: 40-lead 01 L; plastic (SOT129).
PCF8577T, PCF8577 AT: 40-lead mini-pack; plastic (VS040; SOT158A).
PCF8577T, PCF8577 AT: in blister tape.
PCF8577U/5, PCF8577 AU/5:
wafer unsawn.
PCF8577U/10, PCF8577AU/10: chip-on-film frame carrier (FFC).
1
(MarCh 1989
393
l
PCF8577
PCF8577A
SDA
PINNING
Supply
SCL
vss
AO/OSC
A1
35
38
4D
39
6
vDD
S26
'7
A2/BP2
Inputs
BP1
36
37
S23
PCF8577
PCF8577A
SOA
SCL
12 C-bus data line
12 C-bus cI ock Ii ne
A1
AD/OSC
hardware address line
hardware address line/oscillator pin
S2
Outputs
S3
1 - 32 S32 - S1
S21
S4
Input - Output
S20
S5
34
A2/BP2
S19
S6
33
BP1
S18
15
segment outputs
harware address line/cascade sync
input/backplane output
cascade sync input/backplane output
S7
S17
25
S8
S16
S9
S15
S10
S14
S11
S13
positive supply
negative supply
12 C-bus
S27
S1
VOO
VSS
20
S12
7Z87557.1
Fig.2 Pinning diagram.
FUNCTIONAL DESCRIPTION
Hardware subaddress AO, A 1, A2
The hardware subaddress lines AD, A 1, A2 are used to program the device subaddress for each PCF8577
on the bus. Lines AD and A2 are shared with OSC and BP2 respectively to reduce pin-out requirements.
AD/OSC
Line AD is defined as LOW (logic D) when this pin is used for the local oscillator or when
connected to VSS. Line AD is defined as HIGH (logic 1) when connected to VOO.
A1
Line A1 must be defined as LOW (logic D) or as HIGH (logic 1) by connection to VSS or VOO
respectivel y.
A2/BP2
In the direct drive mode the second backplane signal BP2 is not used and the A2/BP2 pin is
exclusively the A2 input. Line A2 is defined as LOW (logic D) when connected to VSS or,
if this is not possible, by leaving it unconnected (internal pull-down). Line A2 is defined as
HIGH (logic 1) when connected to VOO.
In the duplex drive mode the second backplane signal BP2 is required and the A2 signal is
undefined. In this mode device selection is made exclusively from lines AD and A 1.
3M
March 1989] (
LCD direct/duplex driver with 12 C-bus interface
PCF8577
PCF8577A
Oscillator AO/OSC
The PCF8577 has a single-pin built-in oscillator which provides the modulation for the LCD segment
driver outputs. One external resistor and one external capacitor are connected to the AO/OSC pin to
form the oscillator. In an expanded system containing more than one PCF8577 the backplane signals
are usually common to all devices and only one oscillator is needed. The devices which are not used for
the oscillator are put into the cascade mode by connecting the AD/OSC pin to either VDD or VSS
depending on the required state for AD. In the cascade mode each PCF8577 is synchronized from the
backplane signal (s).
User-accessible registers
There are nine user-accesible 1-byte registers. The first is a control register which is used to control the
loading of data into the segment byte registers and to select display options. The other eight are segment
byte registers, split into two banks of storage, which store the segment data. The set of even numbered
segment byte registers is called BANK A. Odd numbered segment byte registers are called BANK B.
There are two slave addresses, one for PCF8577, and one for PCF8577 A (see Fig.6). All addressed
devices load the second byte into the control register and each device maintains an identical copy of
the control byte in the control register at all times (see 12 C-bus protocol Fig.7), i.e. all addressed
devices respond to control commands sent on the bus.
«~
«o
~
:2:
w
::?E
c..
o..J
The control register is shown in more detail in Fig.3. The least-significant bits select which device and
which segment byte register is loaded next. This part of the register is therefore called the Segment
Byte Vector (SBV).
The upper three bits of the SBV (V5 to V3) are compared with the hardware subaddress input signals
A2, A 1 and AD. If they are the same then the device is enabled for loading, if not the device ignores
incoming data but remains active.
The three least-significant bits of the SBV (V2 to VD) address one of the segment byte registers within
the enabled chip for loading segment data .
W
>
W
o
r-CONTROL REGISTER---"l
DISPLAY
I
CONTROL SEGMENT BYTE VECTOR (SBV)
r-~,
A
\
msb
Isb
I I
V5
I
(1)
iI
><
V31 V2
11
VO
SEGMENT BYTE REGISTERSj
llsb
Isb
I
segmentaddress
byte
register
"----y---l
(1)
tt'><"l
I A2
>,;
I
AD
I
BANK 'A'
L
device subaddress
: I
:
]
BANK 'B'
: I
~-~f---+---------" }
DISPLAY
MODE
(1) Bits ignored in duplex mode.
Fig.3 PCF8577 register organization.
7Z87558.2
1
(March 1989
395
l
PCF8577
PCF8577A
________________________________________
FUNCTIONAL DESCRIPTION (continued)
The control register also has two display control bits. These bits are named MODE and BAN K. The
MODE bit selects whether the display outputs are configured for direct or duplex drive displays.
The BANK bit allows the user to display BANK A or BANK B.
Auto-incremented loading
After each segment byte is loaded the SBV is incremented automatically. Thus auto-incremented
loading occurs if more than one segment byte is received in a data transfer.
Since the SBV addresses both device and segment registers in all addressed chips, auto-incremented
loading may proceed across device boundaries provided that the hardware subaddresses are arranged
contiguously.
Direct drive mode
The PCF8577 is set to the direct drive mode by loading the MODE control bit with logic O. In this
mode only four bytes are needed to store the data for the 32 segment drivers. Setting the BANK bit to
logic 0 selects even bytes (BAN K A); setting the BAN K bit to logic 1 selects odd bytes (BAN K B).
In the direct drive lTlode the SBV is auto-incremented by two after the loading of each segment byte
register. This means that auto-incremented loading of BANK A or BANK B is possible. Either bank may
be completely or partially loaded irrespective of which bank is being displayed .. Direct drive output
waveforms are shown in Fig.4.
OFF
ON
_nJ J1J
_nJ U1
o
-(V DD - V SS )
ru
...1 _ 1
f LCD
BP1
Segment x
(Sx)
BP1 - Sx
Von(rms)
I....
Voff(rms)
VDD - VSS
o
7Z87559.3
Fig.4 Direct drive mode display output waveforms.
Duplex mode
The PCF8577 is set to the duplex mode by loading the MODE bit with logic 1. In this mode a second
backplane signal (BP2) is needed and pin A2/BP2 is used for this; therefore A2 and its equivalent SBV
bit V5 are undefined. The SBV auto-increments by one between loaded bytes.
All of the segment bytes are needed to store data for the 32 segment drivers and the BAN K bit is
ignored.
Duplex mode output waveforms are shown in Fig.5.
396
March
19891 (
PCF8577
PCF8577A
LCD direct/duplex driver with 12C-bus interface
OFF/OFF
VOO - 0.5 (V OO + V
SS)
VSS
--J=fL--L
VOO--
V OO - -
VSS
o
SS)--~
-0.5 (V OO + VSS)
-(V OO -VSS)
VOO - VSS
0.5 (V OO + V
o
OFF/ON
ON/ON
~ ~ ~
BPl
~ ~
BP2
lflJL LJ JL LJ
0.5 (V OO + VS S ) - - J ? l VSS
VOO - VSS
0.5 (V OO + V
ON /OFF
SS)--~
-0.5 (V OO + VS S ) - - -(V OO - VSS)
«
J\ )l
~ il j1
~
I-
~
«
C
1
Segment x
(Sx)
BPl - Sx
BP2 - Sx
__
7Z87560.3
I:2
w
:E
Q..
o
..J
W
>
W
C
Von(rms)
Voff(rms)
Von(rms)
0.791 (VDD - VSS)
0.354 (VDD - VSS)
2.236
Voff(rms)
Fig.5 Duplex mode display output waveforms.
Power-on reset
At power-on reset the PCF8577 resets to a defined starting condition as follows:
1. Both backplane outputs are set to VSS in master mode; to 3-state in cascade mode.
2. All segment outputs are set to V ss.
3. The segment byte registers and control register are cleared.
4. The 12 C-bus interface is initialized.
'1
(March 1989
397
l
PCF8577
PCF8577A
_____________________________________~
Slave address
The slave address for PCF8577 and PCF8577 A are shown in Fig.6.
ISlo»»»>IAI
L SLAVE ADDRESS -.J
ISlo»»»>IAI
L SLAVE ADDRESS ~
7Z87561.2
(a) PCF8577
(b) PCF8577 A
Fig.6 PCF8577 and PCF8577 A slave addresses.
Before any data is transmitted on the 12 C-bus, the device which should respond is addressed first.
The addressing is always done with the first byte transmitted after the start procedure.
12 C-bus protocol
The PCF8577 12 C-bus protocol is shown in Fig.7.
acknowledge by
all PCF8577
acknowledge by
all PCF8577
~
~
acknowledge by
selected PCF8577 only
Isb
msb
~
SEGMENT DATA
SLAVE ADDRESS
L - control byte ---.-J
auto increment
segment byte vector
7 Z87553.2
Fig.7 12 (;-bus protocol.
The PCF8577 is a slave receiver and has a fixed slave address (Fig.6). All PCF8577s with the same
slave address acknowledge the slave address in parallel. The second byte is always the control byte and
is loaded into the control register of each PCF8577 on the bus. All addressed devices acknowledge the
control byte. Subsequent data bytes are loaded into the segment registers of the selected device. Any
number of data bytes may be loaded in one transfer and in an expanded system rollover of the SBV
from 111 111 to 000 000 is allowed. If a stop (P) condition is given after the control byte acknowledge
the segment data remains unchanged. This allows the BANK bit to be toggled without changing the
segment register contents. During loading of segment data only the selected PCF8577 gives an
acknowledge. Loading is terminated by generating a stop (P) condition.
398
March
19891 (
PCF8577
PCF8577A
LCD direct/duplex driver with 12 C-bus interface
Display memory mapping
The mapping between the eight segment registers and the segment outputs Sl to S32 is shown in
Tables 1 and 2.
Since only one register bit per segment is needed in the direct drive mode, the BANK bit allows
swapping of display information. If BANK is set to logic 0 even bytes (BANK A) are displayed; if
BANK is set to logic 1 odd bytes (BANK B) are displayed. BP1 is always used for the backplane output
in the direct drive mode.
Table 1 Segment byte-segment driver mapping in the direct drive mode
segment
MODE BANi< V2
<{
~
W
C
In duplex mode even bytes (BANK A) correspond to backplane 1 (BP1) and odd bytes (BANK B)
correspond to backplane 2 (BP2).
Table 2 Segment byte; segment driver mapping in the duplex mode
MODE BANK V2
V1
VO
segment
I bit
register
~
MSB
7
6
5
4
2
3
1
LSB
0
backplane
1
x
0
0
0
0
S8
S7
S6
S5
S4
S3
S2
Sl
1
x
0
0
1
1
S8
S7
S6
S5
S4
S3
S2
Sl
BP2
1
x
0
1
0
2
S16
S15
S14
S13
S12
S11
S10
S9
BP1
1
x
0
1
1
3
S16
S15
S14
S13
S12
Sll
S10
S9
BP2
1
x
1
0
0
4
S24
S23
S22
S21
S20
S19
S18
S17
BP1
1
x
1
0
1
5
S24
S23
S22
S21
S20
S19
S18
S17
IBP2
1
x
1
1
0
6
S32
S31
S30
S29
S28
S27
S26
S25
BP1
1
x
1
1
1
7
S32
S31
S30
S29
S28
S27
S26
S25
BP2
BP1
x = don't care.
Mapping example: bit 7 of register 5 controls the LCD segment S24/BP2.
1
(March 1989
399
l
PCF8577
PCF8577A
________________________________________
CHARACTERISTICS OF THE 12C-BUS
The 12 C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are
a serial data line (SDA) and a serial clock line (Sel). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated
only when the bus is not busy.
Bit tra nsfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the H IG H period of the clock pulse as changes in the data line at this time will be interpreted
as control signals.
SDA --L_+--_ _ _ _
i----JX~.-+-_---~
---~
SCL
data line
stable:
data valid
change
of data
allowed
7Z87019
Fig.8 Bit transfer.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-lOW transition of the
data line, while the clock is HIGH is defined as the start condition (S). A lOW-to-HIGH transition of
the data line while the clock is HIGH is defined as the stop condition (P)'
SOA
---F\-1
I
SCL
~·~I
I
I
:
:
: s:
L ___
[)1---
IU~
______-L_____________
\
.
------------~-----------+I~·
~--\
/
\~.______. . ./
I
I
I
I
!!
...J
SOA
I
SCL
L ___ J
stop condition
start condition
7Z87005
Fig.9 Definition of start and stop conditions.
System configuration
A device generating a message is a "transmitter", a device receiving a message is the "receiver". The
device that controls the message is the "master" and the devices which are controlled by the master
are the "slaves".
SDA----------~------------~--------------~------------~------------~--
SCL--~------_r----~------~------~------+_----4r------_r----~------~--
7Z87004
Fig.10 System configuration.
400
March
19891 (
PCF8577
PCF8577A
LCD direct/duplex driver with 12 C-bus interface
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is not limited. Each byte is followed by one acknowledge bit. The acknowledge
bit is a HI G H level put on the bus by the transmitter whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception
of each byte. Also a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during
the acknowledge clock pulse, so that the SDA line is stable LOW during the H IG H period of the
acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver
must signal an end of data to the transmitter by not generating an acknowledge on the last byte that
has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable
the master to generate a stop condition.
SCl FROM
MASTER
start
condition
I
clock pu Ise for
acknowledgement
I
+
--~
I
I
I
I
I
DATA OUTPUT
BY TRANSMITTER
C~~)(
/
le:(
o
-~
DATA OUTPUT
BY RECEIVER
IZ
7Z87007
w
:E
Fig.11 Acknowledgement on the
Il.
o
2
1 C-bus.
...J
W
>
W
o
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
I
parameter
symbol
min.
Supply voltage range
VDD
Voltage on pin
V,
max.
unit
-0.5
+ 11.0
V
-0.5
VDD +0.5
V
+ 50
rnA
VDD or VSS current
100; ISS
-50
DC input current
II
-20
+ 20
mA
DC output current
10
-25
+ 25
rnA
Power dissipation per package
Ptot
-
500*
mW
Power dissipation per output
Po
-
100
mW
Storage temperature range
Tstg
-65
+ 150
oC
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is good practice to take normal precautions appropriate to handling MaS devices (see
'Handling MaS Devices').
* Derate 7.7 mW/K when Tamb
> 60 oC.
1(MarCh
1989
401
PCF8577
PCF8577A
l
~______________________________________~
OC CHARACTERISTICS
VOO
= 2.5 to 9.0 V; VSS = 0 V; Tamb = -40 to +85 oc unless otherwise specified
parameter
conditions
symbol
min.
typ.*
max.
unit
VOO
2.5
-
9.0
V
Supply
Supply voltage
Supply current
non specified inputs
at VOO or VSS
at fSCL
= 100 kHz
no load; ROSC = 1 M.n;
COSC = 680 pF
1001
-
80
250
JJ.A
at fSCL
=0
no load; ROSC = 1 M.n;
Casc = 680 pF
1002
-
25
150
JJ.A
at fSCL
=0
-
25
40
JJ.A
at fSCL
=0
no load; ROSC = 1 M.n;
COSC = 680 pF;
V 0 0 = 5 V; T amb = 25 oc 1003
no load;
AO/OSC = VOO or VSS
1004
note 1
VPOR
-
10
20
JJ.A
1.1
2.0
V
-
0.05
V
VOO
V
Power-on reset level
Input AO
Input voltage LOW
VIL1
0
Input voltage HIGH
VIH1
VOO-0.05 -
Input A1
Input voltage LOW
VIL2
0
-
0. 3V OO V
VIH2
0.7 VOO
-
VOO
V
Input voltage LOW
VIL3
0
-
0.10
V
Input voltage HIGH
VIH3
VOO-0.10
-
VOO
V
VIL4
0
-
0.08
V
Input voltage HIGH
Input A2
Inputs SCL; SOA
Input voltage LOW
Input voltage HIGH
Input capacitance
note 2
VIH4
2.0
-
9.0
V
CI
-
-
7
pF
3.0
-
-
mA
JJ.A
Output SOA
Output current LOW
VOL
= 0.4 V; VOO =
5 V IOL
A1;SCL; SOA
Leakage current
VI
= VOO or VSS
+ 1L1
-
-
1
VI
= VSS
= VOO
IL2
-
-
1
JJ.A
-IL2
-
1.5
5
Il A
A2;BP2
Leakage current
Pull-down current
* Typical conditions: VOO
~
VI
= 5 V; Tamb = 25 oc.
_ffi~('---------------------------
PCF8577
PCF8577A
LCD direct/duplex driver with 12 C-bus interface
parameter
conditions
symbol
min.
typ.*
max.
unit
AO/OSC
leakage current
VI
= VOO
-ll3
-
-
1
JJ.A
VI
= VSS
IOSC
-
1.2
5
JJ.A
± VBP
-
20
-
mV
IOl
0.3
-
-
rnA
-IOH
0.3
-
-
mA
RBP
-
0.4
5
kn
Oscillator
Start-up current
LCD outputs
DC component of lCO driver
Segment output current
Backplane output resistance
(BP1; BP2)
VOL
VOO
= 0.4 V;
=5V
VOH
VOO
= VOO -0.4 V;
=5V
Vo = VSS, VDO,
(VSS+ VOO)/2; note 3
AC CHARACTERISTICS (note 2)
e::(
VOO = 2.5 to 9.0 V; VSS
=0
V; T amb
= -40 to + 85 °C unless otherwise specified
l-
e::(
C
IZ
w
:r::
a...
o
......I
W
>
W
C
parameter
conditions
symbol
min.
typ.*
max.
unit
flCO
65
90
120
Hz
tBS
-
20
100
JJ.s
Sel clock frequency
fSCl
-
-
100
kHz
Tolerable spike width on bus
tsw
-
-
100
ns
JJ.s
JJ.s
Display frequency
COSC
= 680 pF;
! ROSC= 1 Mn
Driver delays with test loads
VOO
=5
V
2
1 C-bus
Bus free time
tBUF
4.7
-
Start condition set-up time
tsu; STA
4.7
-
Start condition hold time
tHO; STA
4.0
-
-
JJ.s
SCl lOW time
tlOW
4.7
-
-
JJ.s
SCl HIGH time
tHIGH
4.0
-
-
JJ.s
SCl and SOA rise time
tr
-
-
1.0
JJ.s
SCl and SOA fall time
tf
-
-
1.3
JJ.s
Data set-up time
tsu; OAT
250
-
ns
Data hold time
tHO; OAT
0
-
tsu; STO
4.7
-
-
Stop condition set-up time
I
* Typical conditions: VOO = 5 V; Tamb = 25 °C.
'1
(MarCh 1989
ns
JJ.s
403
l
PCF8577
PCF8577A
_______________________________________
Notes to the characteristics
1. Resets all logic when VDD
< VpOR'
2. Periodically sampled, not 100% tested.
3. Outputs measured one at a time; VDD
= 5 V;
Iload
= 100 JJ.A.
4. All the timing values are valid within the operating supply voltage and ambient temperature range
and refer to VIL and VIH with an input voltage swing of VSS to VDD'
SCL, SOA
(pins39,40)
1.S kn
----c::::r--
v
00
S1 to S32
6.8 kn
(pins 1 to 32) ~ (V OO + VSS )/2
7Z21918
F ig.12 Test loads.
-------""'\ 1:=:=:=:=:=;: O,S v
Sx
+ O,SV
-tBSVOO
+
-1=:=::=::=::=::=::=::=::=::=::=:~ D,S v
BP1,BP2 _ _ _2_ _(1
(V OO = SV)
7Z21916
Fig.13 Driver timing waveforms.
SOA
seL
-
tHO;STA -
SDA
tSU;STA
7Z87013.2
Fig.14
404
March
2
1 C-bus
19891 (
--
timing diagram; rise and fall times refer to VI L and VI H.
t su;STO
DEVELOPMENT DATA
r
APPLICATION INFORMATION
(')
C
c..
~.
g
Q::
s::::
"t:J
~
DIRECT DRIVE LCD DISPLAY
32
33
~
backplane
64
~'
256
~
;:;'
:r
...,
(')
6s::::
en
:;'
r+
~
or
g
V DD
C OSC
VSS
SCL
SDA
device subaddress
device subaddress
device subaddress
A2.Al.AO= 000
A2.A1.AO= 001
A2.Al.AO= 111
~
7Z87554.3
~
::r
n
c.o
OJ
c.o
"1J"1J
Fig.15 Direct drive display; expansion to 256 segments using eight PCF8577.
00
."."
(X) (X)
~
o
c.TI
CJICJI
-...J-...J
-...J-...J
»
~
c0')
-U-u
APPLICATION INFORMATION (continued)
()()
."."
(»(»
s:
(JJ(JJ
C')
-...J-...J
-...J-...J
~
::r
»
(0
00
(0
BP2
DUPLEX LCD DISPLAY
32
33
64
BP1
128
V DD
C OSC
ROSC
VSS
SCL
SDA
device subaddress
A1.AO=OO
dev ice su badd ress
A1.AO=01
dev ice su badd ress
A1.AO= 11
7Z87555.3
Fig.16 Duplex display; expansion to 2 x 128 segments using four PCF8577.
PCF8577
PCF8577A
LCD direct/duplex driver with 12 C-bus interface
32 output lines
V DD - - - - - - I
VSS
-----I
SCL
-----I
SDA
-----I
device subaddress
A2, At AO = 000
«
~
«c
7ZB7562.1
'--_ _ _ _ _ _ _ _ _... }
expansion
~
z
w
~
Notes
o
...I
1. MODE bit must always be set to logic D (direct drive).
2. BANK switching is permitted.
3. BP1 must always be connected to VSS and AD/OSC must be connected to
either VDD or VSS (no LCD modulation).
Q.
W
>
W
C
Fig.17 Use of PCF8577 as 32-bit output expander in 12 C-bus application.
Purchase of Philips' 12 C components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system provided
the system conforms to the 12 C specifications defined by Philips.
1(MarCh
1989
407
PCF8577
PCF8577A
CHIP DIMENSIONS AND BONDING PAD LOCATIONS
u
(/)
OJ
N
m
N
0
M
(/)
(/)
(/)
M
(/)
N
M
(/)
0
(3
LU
C
C36
R19/C19
C35
R20/C20
C34
R2l/C2l
C33
R22/C22
C32
R23/C23
R3l/C3l
R24/C24
R30/C30
R25/C25
R29/C29
R26/C26
R28/C28
R27/C27
7Z21371.2
Fig.2 (a) Pinning diagram: VS056; SOT190.
'] (
January 1989
411
_Jl________
__
PC_F85_78
PINNING (continued)
VlCO
n.c.
64
n.c.
V5
V4
(1)
V3
V2
Ir-:::
n.c.
rJ L,
n.c.
L.lr.l
LJ
60
n.c.
VOO
OSC
n.c.
SAO
n.c.
n.C.
n.c.
TEST
VSS
55
10
PCF8578
SYNC
C38
SCl
C37
SOA
C36
RO
C35
R1
C34
R2
C33
R3
C32
R4
R31/C31
R5
R30/C30
R6
R29/C29
"-
II:
co
(.')
ii)
II:
0
'" U
S2.
'"
II:
0~
co
g §.'"
'-t
co "u §. §. ii)u '"c;;-u '"
§. §. ;;;
'-t
~
~
'"~
C')
It)
0
N
S2.
~ N
(.')
C')
~
~
co
~
"-
~
~
~
II:
II:
C')
'-t
It)
co
(.')
(.')
(.')
(.')
co "'"
'"'"~ '" '"~ '";;; '"S2.co '"S2. ii)
"'"II: ~II: '"II: '"II: '"II: '"II: '"II:
(1 ) Orientation mark.
Fig.2 (b) Pinning diagram; S0121.
412
n.c.
C39
ClK
January
7Z21552.7
l___
LCD row/column driver for dot matrix graphic displays
PC_F_8_5_78_ __
pin no.
mnemonic
description
SOT190
~
«c
S0121
SDA
1
51
12 C-bus serial data line
SCl
2
52
12 C-bus serial clock line
SYNC
3
53
cascade synchronization output
ClK
4
54
external clock input/output
VSS
TEST
5
55
ground (logic)
6
56
test pin (connect to VSS)
SAO
7
57
12 C-bus slave address input (bit 0)
OSC
8
58
oscillator input
VDD
9
59
positive supply voltage
V2 to V5
10 - 13
60-63
LCD bias voltage inputs
VlCD
n.c.
14
64
LCD supply voltage
15 - 16
1 - 10
not connected
C39 to C32
17 - 24
11 - 18
LCD column driver outputs
R31/C31 to R8/C8
25- 48
19 - 42
LCD row/column driver outputs
R7 to RO
49 - 56
43 - 50
LCD row driver outputs
I-
Z
w
:E
Q.
o
..J
W
>
W
C
1( Janua~
1989
413
_Jl________
__
PC_F85_78
FUNCTIONAL DESCRIPTION
The PCF8578 row/column driver is designed for use in one of three ways:
• Stand-alone row/column driver for small displays (mixed mode)
• Row/column driver with cascaded PCF8579s (mixed mode)
• Row driver with cascaded PCF8579s (row mode)
Mixed mode
In mixed mode, the device functions as both a row and column driver. It can be used in small stand-alone
applications, or for larger displays with up to 15 PCF8579s (31 PCF8579s when two slave addresses
are used). See table 1 for common display configurations.
Row mode
I n row mode, the device functions as a row driver with up to 32 row outputs and provides the clock and
synchronization signals for the PCF8579. Up to 16 PCF8579s can I"ormally be cascaded (32 when two
slave addresses are used).
Table 1 Possible display configurations
multiplex
rate
application
stand-alone
with PCF8579
row mode
mixed mode
rows
columns
32
1:8
1: 16
1:24
1 :32
8
16
24
32
1:8
1: 16
1:24
1:32
8
632
624
16
24
616
32
608
using 15
PCF8579s
24
16
8
rows
-
-
typical applications
I
-
8x4
16 x 2
24
32
columns
small digital or
alphanumeric displays
640
640
640
640
using 16
PCF8579s
I
alphanumeric displays
and dot matrix
graphic displays
Timing signals are derived from the on-chip oscillator, whose frequency is determined by the value of
the resistor connected between
and VSS.
asc
Commands sent on the 12 C-bus from the host microprocessor set the mode (row or mixed}
configuration (multiplex rate and number of rows and columns) and control the operation of the
device. The device may have one of two slave addresses. The only difference between these slave
addresses is the least significant bit, which is set by the logic level applied to SAO. The PCF8578
and PCF8579 also have subaddresses. The subaddress of the PCF8578 is only defined in mixed mode
and is fixed at O. The RAM may only be accessed in mixed mode and data is loaded as described for
the PCF8579.
I
Bias levels may be generated by an external potential divider with appropriate decoupling capacitors.
For large displays, bias sources with high drive capability should be used. A typical mixed mode
system operating with up to 15 PCF8579s is shown in Fig.3 (a stand-alone system would be identical
but without the PCF8579s).
414
January
19891 (
PCF8578
LCD row/column driver for dot matrix graphic displays
Multiplexed LCD bias generation
The bias levels required to produce maximum contrast depend on the multiplex rate and the LCD
threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the LCD exhibits 10%
contrast. Table 2 shows the optimum voltage bias levels for the PCF8578 as functions of Vop
(V op = VDD - VLCD), together with the discrimination ratios (D) for the different multiplex rates.
A practical value for Vop is obtained by equating Voff(rms) with Vth.
Table 2 Optimum LCD bias voltages
multiplex rate
parameter
1:8
1:24
1: 16
1:32
i
V2
-
0.739
0.800
0.830
Vop
I
i
0.850
i
e:(
f0-
I
I
V3
Vop
0.522
II
0.600
0.661
I
V4
Vop
fo2
w
0.478
0.400
0.339
I
I
0.261
0.200
0.170
I
~
W
>
W
o
0.300
t
V5
-
Vop
0.150
I
c..
o..J
0.700
I
e:(
o
II
I
Voff(rms)
0.297
0.245
Vop
J
Von(rms)
0.430
0.316
1.447
1.291
3.37
4.08
Vop
D=
Von(rms)
I
1
I
!
0.263
0.193
0.230
I
Voff(rms)
Vop
0.214
I
1.230
4.68
I
1.196
5.19
Vth
") ("January 1989
415
,&::.
...a
0')
"TI
mUltiplex rate (n)
C-
Ol
::J
C
Ol
-<
co
(Xl
R
R
R3
C
Z
n=8
n=16.24.32
R
R
(yn (3
2) R
-y'ii)
R
/">.
~
R
~.(
R
:j
o
z
LCD DISPLAY
_ _--'J.,....
(y'rl- 3)
(')
--
r
o
40- n
I
(0
__ _
:t>
m
columns
en
--~~------~~~
(')
JJ
V DD
V
40
-·---;~-....~-----.---------,-:n--,-R-1---------j v~D
"'tI
oo'"m",
.....
(5
Z
no
::J
.-+
R2
3'
C
C
i~
HOST
MICROPROCESSOR
~
Q..
R3
VDD V
_
LCD
VSS _
C
V4
II
~r
SCl
CD
V3
PCF8578
AO rA1 f -
VDD
V
lCD
PCF8579
VSS
subaddress 1
A2 f }
R2
---+---1 SDA
C
VSSIVDD _
,. ~
C
__
~
V5
II
SAO
~
SDA SCl ClK SYNC V4
VSSIVDD
A3 f V3
UR1
~~
V~D
~------------~------~~~------~VSS
~
V
VSS
LCD
ROSC
OSC
SDA SCl ClK
,
SAO f-- VssIVDD
SYNC
~
~
,
n = multiplex rate
7Z21375.2
F ig.3 Typical mixed mode configuration,
'"tJ
()
"
(X)
(Jl
-..J
(X)
Il__
LCD row/column driver for dot matrix graphic displays
p_CF_8_57_8_ __
1.0 1 - - \!bias
----r--
.-~
3-
I---
7Z21533.1
~
0.8
0.6
0.4
0.2
~
I
)-- ~
V
"',
~
~ r-V-5
I
1.8
1:.6
.:24
1:32
multiplex
rate
FigA LCD bias voltages as a function of the multiplex rate.
W
o
1.
2.
3.
4.
5.
6.
7.
Display blank
1 :32 multiplex rate, row mode
Start bank 0 selected
Data pointer is set to X, Y address 0, 0
Character mode
Subaddress counter is set to 0
12 C-bus interface is initialized.
Data transfers on the l:l C-bus shou id be avoided for 1
the reset action.
'TIS
following power-on, to ailow completion of
1(
January 1989
417
_Jl_________
__
PC_F85_78
FUNCTIONAL DESCRIPTION (continued)
I-------------Tframe - - - - - - - - - - - - 1
_ON
=OFF
ROW
a
~~O-I
V3 - V4 - V -5
VLCO -
OO --
COLUMN
a
COLUMN
1
u---a I 1 I 2 I 3 I 4 I 5 I s I 7 I s I 9 110 111 I 12 1 13 114 115
I
ROW
~1:8
1
V
V -2
V3 - V -4
V -5
VLCO - SYNC-U
~~O-I
V -3
V4 - V5 - V LCO V
-OO
V2 - V -3
V4 - V5 - -
1
VLCO SYNC
1
a
I
ROWO
COLUMN
ROWO
u----
-U
11 12 I 31 4 151s 171 s 19110 111 11211311411511sl1711s119120 121122123
Uuuuuuuuu
W
~F
V4 - V5 - VLCO -
~I
U
r
I
COLUMN
a
I
I
32
UUl
I
1
I
column
display
lZ21542
Fig.5 LCD row/column waveforms.
January
1:
11 121314151 s 171819 lwi11112113 H1511sl1711s119120H2212312412512s127128129130H
SYNC-Ur---------------------------------------~
418
24
u----
VLCO -
OO --
1:
I
SYNC -
V
V2 - V -3
V -4
V5 - VLCO -
IUl
19891 (
l___
LCD row/column driver for dot matrix graphic displays
PC_F_8_5_7_8_ __
. . . .- - - -
V
V
ROW 1
R1 (t)
OO
Tframe - - - - - 1
state 1 (ON)
state 2 (OFF)
--
-2
-3
V -4
V -5
1
V
VLCO -
ROW2
R2 (t)
fo--.--o--o-o-o-
V
-OO
V2 - V -3
dot matrix
1 : 8 multiplex rate
V - - '4
V -5
V LCO -
COLUMN 1
C1 (t)
V OO - V2 - V -3
V4 - V -5
V LCO -
COLUMN 2
C2 (t)
V OO - V2 - V3 - V4 - V5 - V LCO -
W
Vop - -
0
= C1(t)
Vstate 1(t)
W
Von(rms) ) 1
-- =
V op
Vstate 1 (t)
8
- R1(t):
+
va-1
8
+ 1)
(VB
= 0.430
g·e61 Vop-0.261 Vop-
-Vop--
V state 2(t)
= C2(t) -
Voff(rms)
=
(yIB - 1)
= 0.297
(y'8 + 1)2
~/8
Vop
Vop - -
2
R2(t):
0.478 VopVstate 2 (t)
g·e61 Vop-
general relationship (n
-0.261 Vop -0.478 Vop
1 Vn-1
-!
-vop _ _ 1
= multiplex rate)
-+
n
7Z21S44.1
n(vn+1)
Voff(rms)_
2(y'n-1)
Vop
Vn (01 + 1)2
Fig.6 LCD drive mode waveforms for 1:8 multiplex rate.
1(
January 1989
419
_J l________- - '
__
PC_F85_78
FUNCTIONAL DESCRIPTION (continued)
,
-I
Voo
V2
ROW 1
R1(t)
.
Tframe
ta te
state 2 (OFF)
O -<:1)-(ON)
-1 ___ O-o-J;r:rIo-(sr
V3
V -4
V5 - V
LCO
r~
-
VOO - -
V -2
V3 - V -4
ROW 2
R2(t)
V -5
V LCO -
COL 1
C1(t)
VOO V2 - V3 - V -4
V -5
V LCO -
COL2
C2(t)
VOO V2 - V3 - V4 - V -5
V
LCO
dot matrix
1 : 16 multiplex rate
0.2 Vop _
OV
Vstate 1 (t)
-0.2 Vop -
Vop - 0.6 Vop -
~'evop
Vstate 2 (t)
-I
=
-0.2 Vop
-0.6 Vop -Vop
7Z21543.1
V state 1 (t)
Von(rms)
= C 1(t) -
=
Vop
Vstate 2(t)
R 1(t):
1
~/f6-1
16
16
- +
= C2(t)
general relationship (n
(v'16 + 1)
= 0.316
- R2(t):
Voff(rms)
_2_(V16_1_6_-_1_)_
Vop
Vl6 (y"i6 + 1)2
= 0.245
Von(rms)
Vop
=
1
= multiplex rate)
yIn-1
-+ - - - n
n (yin + 1)
vn -1)
Voff(rms)
2
Vop
yin (yin + 1)2
Fig.7 LCD drive mode waveforms for 1: 16 multiplex rate.
420
January
l____
LCD row/column driver for dot matrix graphic displays
pC
__
F8_5_7_8______
Internal clock
The clock signal for the system may be generated by the internal oscillator and prescaler. The
frequency is determined by the value of the resistor ROSC, see Fig.8. For normal use a value of
330 kn is recommended. The clock signal, for cascaded PCF8579s, is output at ClK and has a
frequency one-sixth (multiplex rate 1:8, 1: 16 and 1:32) or one-eighth (multiplex rate 1:24) of the
oscillator frequency.
7Z215321
lose
(kHz)
i'
......
., , 'r-.
'-..'
!,
10
.......
«
~
«
c
10
~
zw
~
a..
F ig.8 Oscillator frequency as a function of ROSC.
o
...J
W
>
Note
C
To avoid capacitive coupling, which could adversely affect oscillator stability, Rose should be placed
as closely as possible to the OSC pin. If this proves to be a problem, a filtering capacitor may be
connected in parallel to ROSC.
W
External clock
If an external clock is used, OSC must be connected to VDD and the external clock signal to ClK.
Table 3 summarizes the nominal ClK and SYNC frequencies.
Table 3 Signal frequencies required for nominal 64 Hz frame frequency
frame frequency
oscillator frequency
(Rose = 330 kn)
fOSC (Hz)
fSYNC (Hz)
12288
64
12288
64
clock frequency
multiplex rate
division
ratio
fClK (Hz)
1: 8; 1: 16; 1: 32
6
2048
1:24
8
1536
n
A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
'] (
January 1989
421
___
PC_F85_78_jl______________~
FUNCTIONAL DESCRIPTION (continued)
Timing generator
The timing generator of the PCF8578 organizes the internal data flow of the device and generates the
LCD frame synchronization pulse SYNC, whose period is an integer multiple of the clock period. In
cascaded applications, this signal maintains the correct timing relationship between the PCF8578 and
PCF8579s in the system.
Row/column drivers
Outputs RO to R7 and C32 to C39 are fixed as row and column drivers respectively. The remaining
24 outputs R8/C8 to R31/C31 are programmable and may be configured (in blocks of 8) to be either
row or column drivers. The row select signal is produced sequentially at each output from RO up to
the number defined by the multiplex rate (see Table 1). In mixed mode the remaining outputs are
configured as columns. In row mode all programmable outputs (R8/C8 to R31/C31) are defined as
row drivers and the outputs C32 to C39 should be left open-circuit. Using a 1: 16 multiplex rate,
two sets of row outputs are driven, thus facilitating split-screen configurations; i.e. a row select
pulse appears simultaneously at RO and R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex
rate of 1:8, four sets of row outputs are driven simultaneously. Driver outputs must be connected
directly to the LCD. Unused outputs should be left open-circuit.
Display mode controller
The configuration of the outputs (row or column) and the selection of the appropriate driver waveforms
are controlled by the display mode controller.
Display RAM
The PCF8578 contains a 32 x 40 bit static RAM which stores the display data. The RAM is divided
into 4 banks of 40 bytes (4 x 8 x 40 bits). During RAM access, data is transferred to/from the RAM
via the 12 C-bus. The first eight columns of data (0 to 7) cannot be displayed but are available for
general data storage and provide compatibility with the PCF8579.
Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows an
individual data byte or a series of data bytes to be written into, or read from, the display RAM,
controlled by commands sent on the 12 C-bus.
Subaddress counter
The storage and retrieval of display data is dependent on the content of the subaddress counter.
Storage takes place only when the contents of the subaddress counter agree with the hardware
subaddress. The hardware subaddress of the PCF8578, valid in mixed mode only, is fixed at 0000.
12 C-bus controller
The 12 C-bus controller detects the 12 C-bus protocol, slave address, commands and display data bytes.
It performs the conversion of the data input (serial-to-parallel) and the data output (parallel-to-serial).
The PCF8578 acts as an 12 C-bus slave transmitter/receiver in mixed mode, and as a slave receiver
in row mode. A slave device cannot control bus communication.
Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on
the SDA and SCl lines.
422
January 1989] (
l__
LCD row/column driver for dot matrix graphic displays
P_C_F_8_5_78_ _ _....-I !
I
RAM access
RAM operations are only possible when the PCF8578 is in mixed mode. I n this event its hardware
subaddress is internally fixed at 0000 and the hardware subaddresses of any PCF8579 used in
conjunction with the PCF8578 must start at 0001.
There are three RAM ACCESS modes:
• Character
• Half-graphic
• Full-graphic
These modes are specified by bits G 1 and GO of the RAM ACCESS command. The RAM ACCESS
command controls the order in which data is written to or read from the RAM (see Fig.9).
To store RAM data, the user specifies the location into which the first byte will be loaded (see F ig.1 0):
• Device subaddress (specified by the DEVICE SELECT command)
• RAM X-address (specified by the LOAD X-ADD R ESS command)
• RAM bank (specified by bits Y1 and YO of the RAM ACCESS command)
Subsequent data bytes will be written or read according to the chosen RAM access mode. Device
subaddresses are automatically incremented between devices until the last device is reached. If the last
device has subaddress 15, further display data transfers will lead to a wrap-around of the subaddress
to O.
W
o
Display control
The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the
column outputs. The number of rows scanned depends on the multiplex rate set by bits M1 and MO
of the SET MODE command.
The display status (all dots on/off and normal/inverse video) is set by bits E1 and EO of the SET MODE
command. For bank switching, the RAM bank corresponding to the top of the display is set by
bits B1 and BO of the SET START BANK command. This is shown in Fig.11. This feature is useful
when scrolling in alphanumeric applications.
I(
January 1989
423
~
~
PCF8578jPCF8579
PCF8579
"T1
c
driver 1
driver 2
t::J
I::
-<
CO
CO
(")
-i
0)
co
2
driver k
--
O)
_bankO
(5
_bank1
»
r-
z
RAM
4 bytes
0
m
_bank2
(I)
(")
JJ
_4__-
bank 3
"tJ
-i
PCF8578/PCF8579 system RAM
1,.. k ~ 16
40-bits
L
1 byte
{l I;
0
_ _ _ _ _ _ -,
12131
~
1516171819110
1111
I
::J
.-+
3"
-
..............
I
I
4
6
8 10 12 14 16 18 20 22
1
3
5
7
9 11 13 15 1719 21 23
2by,", {
half-graphic mode
0
4
8 12 16 20 2428 3236 4044
1
5
9 -13 17 21 25 29 3337 41 45
2
6 10 14 18 2226 3034 38 42 46
3
7 11 15 19 2327 31 35 39 43 47
-
-1 bytes
7Z21539.1
RAM data bytes are
written or read as
indicated above
2
no
CIl
..................
.............
2
0
I::
character mode
0
LSB
------------I~ ~~ ~~ ~
I
I
~~~
full-grapilic mode
Fig.9 RAM access mode.
3:
MSB
"'0
()
"'T1
ex>
01
~
CO
DEVE LOPMENT DATA
r-
n
c
o
:e
( ")
o
2"
3
~
DEVICE SELECT:
subaddress 12
~
-------'-
:C'
RAM ACCESS:
~
_bankO
/I
character mode
bank 1
Q
_bankl
0..
RAM
_bank2
g
_bank3
3
~
X'
R/W
I
LOAD X-ADDRESS: X-address = 8
READ I
il
R/W
I
I
__
slave address
I I I I I I lSI
5011110 A 0
I I I I I
0
I
DEVICE SELECT
111
All
I
I
1
I
I
I I I I I
01100 A
I I I I I
I
l I
LOAD X-ADDRESS
RAM ACCESS
I
~I
I I I I II ~. I r I T i l
10001000 A 01110001
(see 12C-bus protocol)
I
,
I
I
l
I
slave address
-1
In
II I I I I
5
0 1 1 1 lOA
I I I I I
0
~
Q)
~
Ij
1 A
'C
::r
I-I
I
I
!-'-I--'I}l
DATA
A
I I I I I
n'
0..
iii'
'C
i
Col>
A
I
last c.ommand
II
WRITE
I
IDA~AI
I
I
I
I
I
IAI'
I
IDA~AI
I-I
I
I
I
I
I
r!
7Z21549.1
F ig,1 0 Example of commands specifying initial data byte RAM locations,
c...
Q)
~
c:
Q)
-<
CO
00
CO
""tJ
()
"T1
00
01
........
00
~
N
(J'1
_Jl_________
_ _P_CF_857_8
FUNCTIONAL DESCR IPTION (continued)
RAM
top of LCD
00000000000000
000000000000
000000000
00000000
0000000
000000
00000
000
000
0000
LCD
7Z21550
Fig.11 Relationship between display and SET START BANK;
1:32 multiplex rate and start bank = 2.
426
January
1989\ (
LCD row/column driver for dot matrix graphic displays
l____
PC_F_8_5_7_8______
12 C-BUS PROTOCOL
Two 7-bit slave addresses (0111100 and 0111101) are reserved for both the PCF8578 and PCF8579.
The least-significant bit of the slave address is set by connecting input SAO to either 0 (VSS) or
1 (VDD). Therefore, two types of PCF8578 or PCF8579 can be distinguished on the same 12 C-bus
which allows:
(a) one PCF8578 to operate with up to 32 PCF8579s on the same 12 C-bus for very large applications
(b) the use of two types of LCD mu Itiplex schemes on the same 12 C-bus.
In most applications the PCF8578 will have the same slave address as the PCF8579.
The 12 C-bus protocol is shown in Fig. 12. All communications are initiated with a start condition (S)
from the 12 C-bus master, which is followed by the desired slave address and read/write bit. All devices
with this slave address acknowledge in parallel. All other devices ignore the bus transfer.
In WRITE mode (indicated by setting the read/write bit LOW) one or more commands follow the
slave address acknowledgement. The commands are also acknowledged by all addressed devices on
the bus. The last command must clear the continuation bit C. After the last command a series of data
bytes may follow. The acknowledgement after each byte is made only by the (AD, A 1, A2 and A3)
addressed PCF8579 or PCF8578 with its implicit subaddress O. After the last data byte has been
acknowledged, the 12 C-bus master issues a stop condition (P).
«
!d:
c
IZ
w
~
CL.
o
...J
W
>
W
C
In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read from the
RAM following the slave address acknowledgement. After this acknowledgement the master transmitter
becomes a master receiver and the PCF8578 becomes a slave transmitter. The master receiver must
acknowledge the reception of each byte in turn. The master receiver must signal an end of data to
the slave transmitter, by not generating an acknowledge on the last byte clocked out of the slave. The
slave transmitter then leaves the data line HIGH, enabling the master to generate a stop condition (P).
Display bytes are written into, or read from, the RAM at the address specified by the data pointer and
subaddress counter. Both the data pointer and subaddress counter are automatically incremented,
enabling a stream of data to be transferred either to, or from, the intended devices.
In multiple device applications, the hardware subaddress pins of the PCF8579s (AD to A3) are connected
to VSS or VDD to represent the desired hardware subaddress code. If two or more devices share the
same slave address, then each device must be allocated a unique hardware subaddress.
1
(January 1989
427
_Jl_________
__
PC_F85_78
12 C-BUS PROTOCOL (continued)
acknowledge
by AO, A1, A2 and A3
selected PCF8578s/
PCF8579s only
~
update data pOinters
and if necessary
subaddress counter
7Z21547
F ig.12(a) Master transmits to slave receiver (WR ITE mode).
no acknowledge
from master
tL
iW
R/W
at this moment master
transmitter becomes a }
master receiver and
PCF8578/PCF8579 slave
receiver becomes a
slave transmitter
~
"+
n bytes
7Z21548
Fig.12(b) Master reads after sending command string (WRITE commands; READ data).
I
acknowledge
by all addressed
PCF8578s/PCF8579s
acknowledge
from master
no acknowledge
from master
~
~
~
slave address
1 s 10;
I
<<<<°1~ 11 H: : :O+A:
L~
R/W
n bytes
H: :
::
:0+< : : 11 1 P 1
~ L~
~J
last byte
update data pointers
and if necessary
subaddress counter
7Z21546
Fig.12(c) Master reads slave immediately after sending slave address (READ mode).
428
January
1989~
("
l___
LCD row/column driver for dot matrix graphic displays
P_C_F8_5_7_8_ __
Command decoder
The command decoder identifies command bytes that arrive on the 12 C-bus. The most-significant bit
of a command is the continuation bit C (see Fig.13). When this bit is set, it indicates that the next
byte to be transferred will also be a command. If the bit is reset, it indicates the conclusion ofthe command
transfer. Further bytes will be regarded as display data. Commands are transferred in WR ITE mode
only.
MSB
LSB
Ic I ~ES; O:F ~P+D~ I
7Z21545
C == 0; last command
C == 1; commands continue
F ig.13 General format of command byte.
«
The five commands available to the PCF8578 are defined in Tables 4 and 5.
<1:
Table 4 Summary of commands
I-
C
IZ
w
code
command
description
~
o
CODDDDDD
LOAD X-ADD R ESS
o to 39
W
C10DDDDD
SET MODE
mUltiplex rate, display status, system type
W
C110DDDD
DEVICE SELECT
defines device subaddress
C111DDDD
RAM ACCESS
graphic mode, bank select
(D DOD ~ 12 is not allowed; see
SET START BANK opcode)
C11111DO
SET START BANK
defines bank at top of LCD
Q.
...J
>
C
Where!
C == command continuation bit
D == may be a logic 1 or O.
1(
January 1989
429
_Jl_________
__
PC_F85_78
12 C-BUS PROTOCOL (continued)
Table 5 Definition of PCF8578/PCF8579 commands
options
command / opcode
SET MODE
LCD drive mode
lell 0lTlE1 EolM1 Mol
1:8
1: 16
1:24
1:32
MUX
MUX
MUX
MUX
description
bits M1
(8 rows)
(16 rows)
(24 rows)
(32 rows)
display status
1
1
defines LCD drive mode
1
a
1
a a
bits El
EO
defines display status
a a
a 1
1
a
blank
normal
all segments on
inverse video
system type
a
MO
1
1
bit T
defines system type
a
PCF8578 row only
PCF8578 mixed mode 1
SET START BANK
start bank pointer bits B1
a
Ie 11 1 1 1 1 I B 1 BO
I
DEVICE SE LECT
Ic [1 1 0lA3 A2 A1
430
January 1989] (
a a
a 1
1
a
bank
bank 1
bank 2
bank 3
bits
1
a to 15
defines pointer to RAM bank
corresponding to the top of
the LCD. Useful for scrolling,
pseudo-motion and background
preparation of new display
1
A3 A2 A1 AO
4-bit binary value of
Aol
BO
four bits of immediate data,
bits AO to A3, are transferred
to the subaddress counter to
define one of sixteen hardware
su badd resses
l____
LCD row/column driver for dot matrix graphic displays
P_C_F8_5_7_8______
RAM ACCESS
Ic 11 1 11G1 GO IV1 YO
description
options
command / opcode
I
defines the auto-increment
behaviour of the address for
RAM access
RAM access mode bits G1
GO
character
half graphic
full graphic
not allowed *
0
0
1
1
0
1
0
1
bits
Y1
YO
two bits of immediate data,
bits YO to Y1, are transferred
to the Y -address pointer to
define one of four banks for
RAM access
X5 X4 X3 X2 X 1 XO
six bits of immediate data,
bits XO to X5, are transferred
to the X-address pointer to
define one of forty display
RAM columns
2-bit binary value of 0 to 3
LOAD X-ADDRESS
bits
ICIolX5 X4 X3 X2 X1 XOI
6-bit binary value of 0 to 39
W
C
* See opcode for SET START BANK.
1(
January 1989
431
_Jl_________
__
PC_F85_78
CHARACTERISTICS OF THE IZC-BUS
The 12 C-bus is for bidirectional, two-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL) which must be connected to a positive
supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HI G H period of the clock pu Ise as changes in the data line at this moment will be
interpreted as control signals.
!
SDA
X:\-4._
i
---~
SCL
data line
stable:
data valid
change
of data
allowed
7Z87019
F ig.14 Bit transfer.
Start and stop cond itions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the
data line, while the clock is HIGH, is defined as the start condition (S). A LOW-to-HIGH transition
of the data line while the clock is HIGH, is defined as the stop condition (P).
SOA
--f\-1
I
SCL
iit----
cn~
~'~I------~-------------
I
I
:
i \
I
: s:
L _ _ _ ..J
start condition
.
r- - - \
/
January
19891 (
p
SCL
:
L ___ J
stop condition
Fig.15 Definition of start and stop condition.
432
I
::
\~.__~!:
SOA
I
------------~----------41~·
7Z87005
l____
LCD row/column driver for dot matrix graphic displays
PC_F_8_5_7_8______
System configuration
A device transmitting a message is a "transmitter", a device receiving a message is the "receiver".
The device that controls the message flow is the "master" and the devices which are controlled by
the master are the "slaves".
SDA----------~-------------~------------~~------------~------------~--
SCL--~------~----~-------+----~r_------~----~------4_----~------_+--
7Z87004
Fig.16 System configuration.
Acknowledge
o
W
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is unlimited. Each data byte of eight bits is followed by one acknowledge bit. The acknowledge
bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra
acknowledge related clock pu Ise. A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an acknowledge after the reception of
each byte that has been clocked out of the slave transmitter. The device that acknowledges must
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW
during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken
into consideration). A master receiver must signal the end of a data transmission to the transmitter
by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
start
condition
I
clock pulse for
acknowledgement
I
+
--~
I
I
I
I
I
~I.....--.l--/-----JX
I
;(~ ~)(
~----~
~
7
____- J
S
DATA OUTPUT
BY RECEIVER
7Z87007
Fig.17 Acknowledgement on the 12 C-bus.
Note
The general characteristics and detailed specification of the 12 C-bus are available on request.
1(
January 1989
433
_Jl_________
__
PC_F85_78
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
parameter
symbol
min.
max.
unit
Supply voltage range
VOO
-0.5
+8.0
V
LCO supply voltage range
VlCO
VOO -11
VOO
V
Input voltage range at
SOA, SCl, elK, TEST,
SAO and OSC
Vll
VOO+0.5
V
VI2
VlCO -0.5
VDO+0.5
V
SYNC and ClK
Val
VSS -0.5
VOO+0.5
V
RO to R7, R8/C8 to R31/C31,
and C32 to C39
V02
V2 to V5
I VSS -0.5
i Output voltage range at
I
i
;
VlCO -0.5
VOO+0.5
V
DC input current
I!
-10
10
rnA
DC output current
10
-10
10
rnA
-50
50
rnA
-
400
mW
-
100
mW
+ 150
oC
VOD, VSS or VlCD current
Power dissipation per package
Power dissipation per output
I
Storage temperature range
L-.
I
II DO. ISS. I LCD
Ptot
I Po
Tstg
~-65
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MaS devices (see
'Handling MaS Oevices').
434
January
1989"1 ("
I
l____
LCD row/column driver for dot matrix graphic displays
P_C_F8_5_7_8______
DC CHARACTERISTICS
VDD = 2.5 V to 6.0 V; VSS
unless otherwise specified
= 0 V;
VLCD
= VDD
-3.5 V to VDD -9 V; Tamb
= -40 oC to +B5 oC;
symbol
min.
typo
max.
unit
Supply voltage
VDD
2.5
-
6.0
V
LCD supply voltage
VLCD
VDD-9
-
VDD -3.5
V
parameter
conditions
Supply
Supply current
external clock
internal clock
note 1;
fCLK = 2 kHz
ROSC = 330 kn
IDDl
IDD2
-
-
6
20
15
50
JlA
JlA
Power-on reset level
note 2
VPOR
O.B
1.3
1.B
V
I nput voltage LOW
VIL
VSS
0.3 VDD
V
Input voltage HIGH
VIH
0.7 VDD
-
VDD
V
lOll
1
-
-
rnA
IOHl
-
-
-1
rnA
IOl2
3.0
-
-
rnA
III
-1
-
1
JlA
Il2
-1
-
1
JlA
CI
-
-.
5
pF
Logic
e:(
Output current LOW
at SYNC and CLK
le:(
o
I-
Z
w
:::!:
a..
Output current HIGH
at SYNC and ClK
VOL = 1.0 V
VDD = 5 V
= 4.0 V
=5 V
Val = 0.4 V;
VDD = 5 V
VOH
VDD
o
SDA output current lOW
>
W
o
leakage cu rrent
at SDA, SCl, SYNC,
ClK, TEST and SAO
VI
= VDD
leakage cu rrent
at OSC
VI
= VDD
I nput capacitance
at SCl and SDA
note 3
..I
W
or VSS
LCD outputs
leakage current at
V2 to V5
= VDD
Il3
-2
-
2
JlA
DC component of LCD
drivers RO to R7,
RB/CB to R31/C31,
and C32 to C39
±VDC
-
20
-
mV
note 4
Output resistance at
RD to R7 and RB/CB to
row mode
R31/C31
RROW
-
1.5
3.0
kn
RCOl
-
3
6
kn
RB/CB to R31/C31
and C32 to C39
VI
or VlCD
column mode
1(
January 1989
435
___PC_F857_8_Jl~_______________
AC CHARACTERISTICS (note 5)
VOO = 2.5 to 6 V; VSS = 0 V; VLCO
unless otherwise specified
= VOO -3.5 V to VOO -9 V; Tamb = - 40 to +85 OC;
parameter
conditions
Clock frequency at
multiplex rates of
1:8, 1:16and 1:32
1:24
ROSC = 330 kn;
VOO = 6 V
SYNC propagation delay
Driver delays
VDO -. VLCD = 9 V;
with test loads
symbol
min.
typo
max.
unit
fCLK1
fCLK2
1.2
0.9
2.1
1.6
3.3
2.5
kHz
kHz
tpSYNC
-
-
500
ns
tPLCD
-
-
100
JlS
fSCL
-
-
100
kHz
12 C-bus
SCL clock frequency
Tolerable spike width
on bus
tsw
-
ns
tBUF
4.7
-
100
Bus free time
-
JlS
Start condition
set-up time
436
repeated start
codes only
tsu; STA
4.7
-
-.
JlS
Start condition
hold time
tHO; STA
4.0
JlS
tLOW
4.7
-
-
SCL LOW time
-
JlS
SCL HIGH time
tHIGH
4.0
-
-
JlS
SC Land SDA rise time
tr
-
1.0
JlS
SCL and SDA fall time
tf
-
-
0.3
Data set-up time
tsu; OAT
250
-
-
JlS
ns
Data hold time
tHO; OAT
0
-
-
ns
Stop condition
set-up time
tsu; STO
4.0
--
-
JlS
January
1989\ (
l____
LCD row/column driver for dot matrix graphic displays
PC_F_8_5_7_8______
Notes to the characteristics
1. Outputs are open; inputs at VDD or VSS; 12 C-bus inactive; external clock with 50% duty factor,
(IDD1 only).
2.
Resets all logic when VDD
< VPOR.
3. Periodically sampled; not 100% tested.
4.
Resistance measured between output terminal (RO to R7, R8/C8 to R31/C31 and C32 to C39)
and bias input (V2 to V5, VDD and VLCD) when the specified current flows through one output
under the following conditions (see Table 2):
VOP = VDD - VLCD = 9 V;
row mode, RO to R7 and R8/C8 to R31/C31 (row mode);
V2 - VLCD;;;': 6.65 V; V5 - VLCD ~ 2.35 V; I LOAD = 150 ~A
column mode, R8/C8 to R31/C31 (column mode) and C32 to C39:
V3 - VLCD;;;': 4.70 V; V4 -VLCD ~ 4.30 V; ILOAD = 100 ~A.
5. All timing values are referred to V,H and V, L levels with an input voltage swing of VSS to VDD.
«
«
o
1.5 kn
3.3 kn
~
SYNC, ClK
-----c=J----
0.5 V DD
SDA
-----c=J----
V DD
~
2
w
:!:
~
o
-I
C39 to C32,
A31/C31 to A8/C8
and A7 to RO
-----1"1 nF
7Z21535.1
W
>
W
o
Fig.18 Test loads.
1(
January 1989
437
___
PC_F85_78_Jl_______________
1
r---------,.
fClK
0.7 VDO
ClK
0.3 VDD
- J - - - - - - - 0 .7
Voo
SYNC
+ - - - - - - 0.3 Voo
- - - tpSYNC
-
_ _ _ 0.5V
t
___t 0.5V
C39 to C32,
R31/C31 to RS/CS
and R7 to RO
1------
tPLCD
t
---------.,~I
lZ21531.1
F ig.19 Driver timing waveforms.
SOA
sel
- - - tHD;STA - -
JDDAT
SOA
-
~uj
[
tSU;STA - tSU;STO
lZ21536
F ig.20 12 C-bus timing waveforms.
438
January
19891 (
~
DEVELOPMENT DATA
»
"'tJ
"'tJ
r-
n
»
-t
0
2
2
"T1
LCD DISPLAY
0
C
0
:E
ti'"
0
C
3
;:,
c.
:!.
<
s:
....0~
-t
c.
:D
»
r-r-
r-
n
0
2
""'I
0
"'
3
Q)
~
)C.
CQ
""'I
Q)
RO
Rl
R2
R3
R4
R5
R6
R7
RB/
CB
'tl
::T
R9/ Rl0/ Rll/ R12/ R13/ R14/ R15/ R16/ R17/ R1B/ R19/ R20/ R2l/ R22/ R23/ R24/ R25/ R26/ R27/
C9 Cl0 Cll C12 C13 C14 C15 C16 C17 C1B C19 C20 C2l C22 C23 C24 C2S C26 C27
c:;.
c.
iii·
'tl
cr
"S
PCFBS7B
VSS TEST SAO
SDA SCl SYNC CLK
IT!
R3l/ R30/ R29/ R2B/
OSC VDD
V2
V3
V4
Vs VLCD n.c.
I
~
-c:::J---'
ROSC
-
n.c. C39 C38 C37 C36 C35 C34 C33 C32 C3l C30 C29 C2B
I
L
I
'---'----
J
CQ)
::J
C
Q)
-<
'-
l
co
00
co
7Z21541
""tJ
()
""T1
ex>
Fig.21 Stand-alone application using 8 rows and 32 columns.
(Jl
.......
ex>
,J::a
w
co
t
o
'1J
()
APPLICATION INFORMATION (continued)
"'T1
(X)
(...
Q)
(J'1
~
::J
c:
Q)
-<
to
00
(X)
VDD
CO
VDD
~OWs
V2
V
PCF8578
4 (ROW MODE)
%40 columns
V5
VlCD
v
1 : 32 multiplex rate
32 x 40 x k dots (1 .;; k.;; 16)
20480 (max)
LCD DISPLAY
'"
SAO f--Vss
0" ~
-SS SDA SClClKSYNC
ROSC
VSS
a
'00
V
40 columns
lCD
#1
PCF8579
v.,
~~~
'00
r l V3
VSS
:::n II~: Illl
140 columns
SYNC ClK
SCl SDA SAO
III~"
I\I!" I
subaddress k-1
subeddress 1
subaddress 0
1\1:"
#2
PCF8579
}J ',,-
-iIj
I
#k
PCF8579
IIm ~._]]
Fig.22 Typical LCD driver system with 1:32 multiplex rate.
]}J
,
Vss
7Z21551.1
DEVELOPMENT DATA
~/
-~
~r
I I I
r
Voo
i{~
~;t
C
II
-llC
V3
R
,
I V4
c
PCF8578
IROW MODE}
"R
-u11--+---++--1
VOO
I~"..
SAO
R
c....
Q)
::J
c:
Q)
.,
"<
CO
00
·"n
SYNC
AOSC
I I
I
columns
--l VOO
V4
Vss
I I
#1
PCF8579
V3
v!s
I
VOO
3
III
::J
~
~.
g
..--.l
c..
o
.-+
Voo
3
subl:jddress 0
40
~
40
x'
columns
(Q
~
"C
::r
16 x40. k dots Ik '" 16}
110240 dots max.}
40
f
>
rl
I r+I
VSS
~
III
C:;.
Co
r-+/VlCO
SOA SCl CLK
o
V4
V LCO
-~
iii'
VSS/V OO
OSC
1
iL:
#1
PCF8579
o
C
"C
1: 16 multiplt[!x rate
16 x 40 x k dots Ik';; 16}
110240 dots max.}
VOO
VSS
vIs
.-
n
n
I, I
1: 16 multiplex rate
~
unused columns
I---
I
~ ~ ~
columns
LCD DISPLAY
V5
n
r
Vss
sabaddress 1
16
-r-
-l I---+-.........J.-..+ V LCO
V LCO
#2
PCF8b79
PCF8579
rows
n
I
';:
"0
~
e
,S
co
r-..
L!)
co
u.
(.)
e:cu
+-'
~
«
l-
X
cu
a.
e:(
E
::J
E
o
I2
w
:iE
Q.
N
M
o
...J
~
+-'
'~
W
>
C
cu
W
e
C
~
cu
Oi
c
'iii
Oi
,§
'~
cu
c
co
a.
cu
Oi
c
'iii
"I-
o
cu
a.
E
co
x
w
L!)
N
,~
U.
1
(January 1989
443
PCF8578
CHIP DIMENSIONS AND BONDING PAD LOCATIONS
o
«
Cf)
0
0 0000 0000 0
0
R6
0
0
0
0
0
0
R10/C10
0
0
0
0
0
0
0
0
0
0
0
0
R11/C11
0
osc
Voo
V2
V3
V4
V5
4.B1
mm
VLCO
0
0
0
0
0
0
PCF8578
0
0
0
0
0
C39
C3B
C37
C36
C35
0
0
0"
~
c..>
0
(')
(')
c..>
R5
R7
RB/C8
R9/C9
R12/C12
R13/C13
R14/C14
R15/C15
R16/C16
R17/C17
R18/C18
R19/C19
R20/C20
R21/C21
R22/C22
0 0000 00000
N
(')
c..>
C;;
~
C;;
II:
.
0
(')
~
'"c..>
N
0
(')
en
N
II:
II:
N
....
N
CD
N
N
....
N
iO
N
CIO
c..>
;:0
II:
~
II:
c..>
II:
It)
...,.
(')
N
N
N
~
It)
N
II:
c..>
~
c..>
(;)
II:
II:
N
N
2.94 mm
7Z21538
Chip area: 14.14 mm 2
Bonding pad dimensions: 120 Mm x 120 Mm.
F ig.26 Bonding pad locations.
444
January
19891 (
l___
LCD row/column driver for dot matrix graphic displays
PC_F_8_5_78_ __
Table 6 Bonding pad locations (dimensions in JLm)
All x/V co-ordinates are referenced to the bottom left corner, see Fig.26.
pad
~
«
c
I-
2
w
:lE
0...
o
..J
W
>
W
C
SOA
SCl
SYNC
ClK
VSS
TEST
SAO
OSC
VOO
V2
V3
V4
V5
VlCO
n.c.
n.c.
C39
C38
C37
C36
C35
C34
C33
C32
R31/C31
R30/C30
R29/C29
R28/C28
X
Y
1642
1438
1234
1000
742
454
160
160
160
160
160
160
160
160
-
4642
4642
4642
4642
4642
4642
4642
4318
3514
3274
3064
2860
2656
2452
_..
160
160
160
160
160
160
454
742
1000
1234
1438
1642
pad
-1252
1048
844
628
406
160
160
160
160
160
160
160
I
R27/C27
R26/C26
R25/C25
R24/C24
R23/C23
R22/C22
R21/C21
R20/C20
R19/C19
R18/C18
R17/C17
R 16/C16
R15/C15
R 14/C14
R13/C13
R 12/C12
R11/C11
R 1O/C10
R9/C9
R8/C8
R7
R6
R5
R4
R3
R2
R1
RO
X
Y
1936
2140
2344
2548
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2776
2548
2344
2140
1936
160
160
160
160
160
424
670
886
1096
1300
1504
1708
1912
2116
2320
2524
2752
3004
3502
3706
3916
4132
4378
4642
4642
4642
4642
4642
Purchase of Philips' 12C components conveys a license under the
Philips' 12C patent to use the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
") ('"January
1989
445
___
PC_F85_78_Jl________________
CHIP-ON GLASS INFORMATION
Voo
-------------~------------------___,_-----
Voo
V3 - - - - - - - _ . .
V.--------...
VlCo - - - - - - - - - - - - .
VSS
ClK
SYNc
r - - - - V3
r - - - - V•
V LCD
Vss
ClK
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
[
co
[ [---------------------------------------C1
C2
Fig.27 Typical chip-on glass application (viewed from underside of chip).
Note to Fig.27
If inputs SAO and AO to A3 are left unconnected they are internally pulled-up to VDD.
446
January
19891 (
--
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change withOllt notice.
~
~
PCF8579
LCD COLUMN DRIVER FOR DOT MATRIX GRAPHIC DISPLAYS
GENERAL DESCRIPTION
The PCF8579 is a low power CMOS LCD column driver, designed to drive dot matrix graphic displays
at multiplex rates of 1:8, 1: 16, 1:24 or 1:32. The device has 40 outputs and can drive 32 x 40 dots in
a 32 row multiplexed LCD. Up to 16 PCF8579s can be cascaded and up to 32 devices may be used on
the same 12 C-bus (using the two slave addresses). The device is optimized for use with the PCF8578
LCD row/column driver. Together these two devices form a general LCD dot matrix driver chip set,
capable of driving displays of up to 40,960 dots. The PCF8579 is compatible with most microcontrollers
and communicates via a two-line bidirectional bus (l2C-bus). Communication overheads are minimized
by a display RAM with auto-incremented addressing and display bank switching.
Features
• LCD column driver
• Used in conjunction with the PCF8578, this device forms part of a chip set capable of driving up to
40,960 dots
• 40 column outputs
• Selectable multiplex rates; 1:8, 1: 16, 1:24 or 1:32
• Externally selectable bias configuration, 5 or 6 levels
• Easily cascadable for large applications (up to 32 devices)
• 1280-bit RAM for display data storage
• Display memory bank switching
• Auto-incremented data loading across hardware subaddress boundaries
• Power-on reset blanks display
• Logic voltage supply range 2.5 V to 6.0 V
• Mc;lximum LCD supply voltage 9 V
• Low power consumption
• 12 C-bus interface
• TTL/CMOS compatible
• Compatible with most microcontrollers
• Optimized pinning for single plane wiringm multiple device applications
• Space saving 56-lead plastic mini-pack
• Compatible with chip-on-glass technology
APPLICATIONS
•
•
•
•
•
Automotive information systems
Telecommunication systems
Point-of-sale terminals
Computer terminals
Instrumentation
PACKAGE OUTLINES
PCF8579T:
PCF8579V:
PCF8579U:
56-lead mini-pack; plastic (VS056; SOT190).
64-lead tape-automated-bonding module (SOT267A).
chip with bumps on-tape.
' ] (January 1989
447
PCF8579
C39 - CO
17 - 56
VD D
V3
V4
V LCD
12
14
15
16
COLUMN (1)
PCF8579
DRIVERS
TEST
VSS
A3--~------~-------1
I+--.....::.j\----- SYNC
A2--~------~-------
Al __~10~____~_______
I+--~--CLK
AO __~l~l______~______ 1
SCL--~---------'I
SDA -~-----'--+I
13
7Z21374.2
SAO
(1) LCD voltage levels. all other blocks operate at logic levels
Fig.1 Block diagram.
448
January
l____
LCD column driver for dot matrix graphic displays
PC_F_8_5_7_9______
PINNING
CO
Cl
C2
C3
C4
C5
C6
C7
C8
~
I-
Al
C9
AO
Cl0
VDD
Cll
n.c.
C12
C
IZ
V3
C13
:i!
V4
C14
o-I
VLCD
C15
C39
C16
~
w
Q.
W
>
W
C
C38
C17
C37
C18
C36
C19
C35
C20
C34
C2l
C33
C22
C32
C23
C3l
C24
C30
C25
C29
C26
C28
C27
7Z21373.1
Fig.2 (a) Pinning diagram: VS056; SOT190.
1
(January 1989
449
_Jl_________
__
PC_F85_79
PINNING (continued)
VlCD
n.c.
V4
n.c.
V3
(1)
AO
n.c.
~r-::
n.C.
r JL .,
VDD
",r.J
60
LJ
n.c.
A1
n.c.
A2
n.c.
A3
n.c.
n.c.
SAO
TEST
10
55
C39
C38
VSS
PCF8579
ClK
C37
SYNC
C36
SCl
C35
SDA
15
50
C34
CO
C33
C1
C32
C2
C31
C3
C30
C4
20
45
C29
C28
C5
7Z21553.1
(1) Orientation mark.
Fig.2 (b) Pinning diagram: S0122.
450
January 1989"1 ('"
l____
LCD column driver for dot matrix graphic displays
PC_F_8_5_7_9______
pin no.
description
mnemonic
«
«
c
SOT190
S0122
SDA
1
50
12 C-bus serial data line
SCl
2
51
12 C-bus serial clock line
cascade synchronization input
SYNC
3
52
ClK
4
53
external clock input
VSS
5
54
ground (logic)
TEST
6
55
test pin (connect to VSS)
SAO
7
56
12 C-bus slave address input (bit 0)
A3 to AO
8 - 11
57 - 60
12 C-bus subaddress inputs
VDD
n.c.
12
61
positive supply voltage
13 *
1-9
not connected
V3 to V4
14 - 15
62 - 63
LCD bias voltage inputs
VLCD
C39 to CO
16
64
LCD supply voltage
17 - 56
10 - 49
LCD column driver outputs
~
~
z
w
::liE
Q.
o
..J
W
>
W
C
* Do not connect, this pin is reserved.
"I ("January
1989
451
_Jl_________
__
PC_F85_79
FUNCTIONAL DESCRIPTION
The PCF8579 column driver is designed for use with the PCF8578. Together they form a general
purpose LCD dot matrix chip set.
Typically up to 16 PCF8579s may be used with one PCF8578. Each of the PCF8579s is identified by
a unique 4-bit hardware subaddress, set by pins AO to A3. The PCF8578 can operate with up to
32 PCF8579s when using two 12 C-bus slave addresses. The two slave addresses are set by the logic level
on input SAO.
Multiplexed LCD bias generation
The bias levels required to produce maximum contrast depend on the multiplex rate and the LCD
threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the LCD exhibits 10%
contrast. Table 1 shows the optimum voltage bias levels for the PCF8578/PCF8579 chip set as
functions of Vop (V op = VDD - VLCD), together with the discrimination ratios (D) for the different
multiplex rates. A practical value for Vop is obtained by equating Voff(rms) with Vth.
Table 1 Optimum LCD bias voltages
multiplex rate
parameter
V2
--
1:8
1: 16
1:24
1 :32
0.739
0.800
0.830
0.850
0.522
0.600
0.661
0.700
0.400
0.339
0.300
0.261
0.200
0.170
0.150
0.297
0.245
0.214
0.193
0.430
0.316
0.263
0.230
1.447
1.291
1.230
1.196
3.37
4.08
4.68
5.19
Vop
V3
-Vop
V4
--
0.478
I
Vop
I
I
V5
-Vop
Voff(rms)
Vop
Von(rms)
Vop
0=
Von(rms)
Voff(rms)
Vop
Vth
452
January
19891 (
l____
LCD column driver for dot matrix graphic displays
PC_F_8_5_7_9______
7Z215331
1.0
Vbias
v;-
0.8
0.6
0.4
0.2
v---
:3-I - - ~~
V
" -~
-..............
-
V-5
1:8
1:16
1:24
1:32
multiplex
rate
F ig.3 LCD bias voltage as a function of the multiplex rate.
e:(
l-
Power-on reset
o
At power-on the PCF8579 resets to a defined starting condition as follows;
e:(
I-
Z
w
:E
Q.
o
...J
W
>
W
o
1.
2.
3.
4.
5.
6.
7.
Display blank (in conjunction with PCF8578)
1:32 mUltiplex rate
start bank 0 selected
Data pointer is set to X, Y address 0,0
Character mode
Subaddress counter is set to 0
12 C-bus is initialized.
Data transfers on the 12 C-bus shou Id be avoided for 1 ms following power-on, to allow completion of
the reset action.
' ] (January 1989
453
_Jl_________
__
PC_F85_79
FUNCTIONAL DESCRIPTION (continued)
- - - - - Tframe
--------------1
_ON
OFF
=
ROW 0
~1:8
COLUMN
I
~----------------------------------------u____
I
1 I 2 13 I
4
15 1
6
I
7
I
8
I
9
1 10 111 112 1 13 114 1 15
ROW 0
I'"
COLUMN
ROWO
1:
24
1:
32
COLUMN
ROW 0
COLUMN
7Z21542
F igA LCD row/column waveforms.
464
January 1989] (
l____
LCD column driver for dot matrix graphic displays
PC_F_8_5_7_9______
VOO - - V --2
ROW 1
R1 (t)
V
V
1. --------
Tframe - - - - - - - -..1
--3
-4
rj
r
V --S
:::D~I
V2 - - ROW 2
R2 (t)
COLUMN 1
C1 (t)
V -3
V4 - V --S
V LCO -
~~O--=lrIlJ1J1lJUU1rl
V -3
V4 - - - -
W
Vstate l(t)
C
Vstate 1 (t)
= C1(t)
- R1(t):
1 y'B-l
- +
°0·2v61 Vop -
8 (y'B'+ 1)
8
-0.261 Vop-
= 0.430
Vstate 2(t) = C2(t) - R2(t):
Voff(rms)_
Vop - - 0.478 V
Vstate 2 (t)
op-
g·e
61 Vop-
Vop
(yB - 1)
general relationship (n
-0.261 Vop -
-0.478
2
--:=---
v'B(y'8+ 1)2
= 0.297
= multiplex rate)
1 y'n'-1
-+
n
n (yin + 1)
V,p-I
-Vop---
Voff(rms)=
2 (yin - 1)
Vop
y'n (yn + 1)2
Fig.5 LCD drive mode waveforms for 1:8 mUltiplex rate.
I
(January 1989
455
_Jl_________
__
PC_F85_79
FUNCTIONAL DESCRIPTION (continued)
voo - ' "
-I
Tframe
sa
t t e 1 (ON)
[ [ state2( OFF)
ROW 1
R1 (t)
'J
'j
[f
v~co-
I
r IUl,J\rUU1IlillUUUU1J1J1J
ROW2
R2 (t)
vLCD
~I
COL1
C1 (t)
Voo - V
2
--
--I
COL2
V--
C2(t)
V!
V -S
V
LCO
0.2 Vop _
Vstate 1 (t)
OV
-0.2 Vop -
-Vop'--
Vop - 0.6 Vop 0.2 Vop _
Vstate 2 (t)
OV
-0.2 Vop
-0.6 Vop
=
-Vop
V state 1(t)
-
I
-I
7Z21543,1
= Cl(t)
1
-+
16
- R 1(t):
general relationship (n = mUltiplex rate)
y'16 - 1
= 0.316
16 (y'16 + 1)
Vstate 2(t) = C2(t) - R2(t):
Voff(rms)
Vop
2 (y16 - 1)
y'l6 (y'16 + 1) 2
==
Von(rms) _
/1
Voff(rms)=
2
Vn -
(vn - 1)
0.245
Fig.6 LCD drive mode waveforms for 1: 16 multiplex rate.
456
1(
January 1989
1
~ ~j~+~1)
dot matrix
1 : 16 multiplex rate
LCD column driver for dot matrix graphic displays
l____
P_C_F8_5_7_9______
Timing generator
The timing generator of the PCF8579 organizes the internal data flow from the RAM to the display
drivers. An external synchronization pulse SYNC is received from the PCF8578. This signal maintains
the correct timing relationship between cascaded devices.
Column drivers
Outputs CO to C39 are column drivers which must be connected to the LCD. Unused outputs should
be left open-circuit.
Display RAM
The PCF8579 contains a 32 x 40 bit static RAM which stores the display data. The RAM is divided
into 4 banks of 40 bytes (4 x 8 x 40 bits). During RAM access, data is transferred to/from the RAM
via the I). C-bus.
Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows an
individual data byte or a series of data bytes to be written into or read from the display RAM, as
specified by commands sent on the i 2 C-bus.
~
Subaddress counter
2
The storage and retrieval of display data is dependent on the content of the subaddress counter. Storage
and retrival take place, only when the contents of the subaddress counter agree with the hardware
subaddress at pins AO, A 1, A2 and A3.
a..
12 C-bus controller
cd:
C
I-
w
:2!:
o..J
W
>
W
C
The 12 C-bus controller detects the 12 C-bus protocol, slave address, commands and display data bytes.
It performs the conversion of the data input (serial-to-parallel) and the data output (parallel-to-serial).
The PCF8579 acts as an 11. C-bus slave transmitter/receiver. Device selection depends on the 12 C-bus
slave address, the hardware subaddress and the commands transmitted.
Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on
the SDA and SCl lines.
") ("January 1989
457
_Jl________
__
PC_F85_79
FUNCTIONAL DESCRIPTION (continued)
RAM access
There are three RAM ACCESS modes:
• Character
• Half-graphic
• Fu II-graphic
These modes are specified by bits G 1 and GO of the RAM ACCESS command. The RAM ACCESS
command controls the order in which data is written to or read from the RAM (see Fig.7).
To store RAM data, the user specifies the location into which the first byte will be loaded (see Fig.B):
• Device subaddress (specified by the DEVICE SELECT command)
• RAM X-address (specified by the LOAD X-ADDRESS command)
• RAM bank (specified by bits Y1 and YO of the RAM ACCESS command)
Subsequent data bytes will be written or read according to the chosen RAM access mode. Device
subaddresses are automatically incremented between devices until the last device is reached. If the
last device has subaddress 15, further display data transfers will lead to a wrap-around of the subaddress
to O.
Display control
The display is generated by continuously shifting rows of RAM data to the dot matrix LCD, via the
column outputs. The number of rows scanned depends on the multiplex rate set by bits M1 and MO
of the SET MODE command.
The display status (all dots on/off and normal/inverse video) is set by bits E 1 and EO of the SET MODE
command. For bank switching, the RAM bank corresponding to the top of the display is set by bits B 1
and 80 of the SET START BANK command. This is shown in Fig.9. This feature is useful when
scrolling in alphanumeric applications.
458
1(
January 1989
DEVELOPMENT DATA
PCF8579
PCF8579
PCF8579
driver 1
driver 2
driver k
r-
n
o
(")
o
~
_bankO
3
:l
~
:C.
_bank1
RAM
4 bytes
~
_bank2
Q
c..
_bank3
40-bits
L _ _ _ _ _ _ ..,
I
1 byte
{8]~13F15J6-1718191101111
I
PCF8579 system RAM
1 ~ k ~ 16
-------------,I~ ~ ~ ~ ~
.- .-'-
.-
3
LSB
........
........
~
Q)
c..
;n'
......................
"t:I
................
I
2
4
6
1
3
5
7
~
s;:.
"t:I
::T
........
I
0
Q)
C:; •
character mode
I
2
S
MSB
iii"
CO
00
CO
RAM data bytes are
written or read as
indicated above
full-graphic mode
~
C11
"'TI
ex>
01
Fig.7 RAM ACCESS mode.
(g
""U
(')
-.....I
CD
~
al
o
"
"1J
(')
11
c:...
(")
(X)
::J
o
z
C
Z
:::!
Q)
c::
Q)
-<
»
r
-'
c.o
c.o
o
m
(I)
00
(")
DEVICE SELECT:
subaddress 12
::0
"tJ
RAM ACCESS:
character mode
bank 1
:::!
-bankO
II
o
:2
no
_bank 1
RAM
_bank2
::J
~.
_bank3
::J
c::
Cl>
a.
LOAD X-ADDRESS: X-address = 8
(see 12C-bus protocol)
last command
II
WRITE
I
IDAITAI
I
I
I
I
I
IAI'
I
IDA~AI
I
I
I
I
IAI
I
7Z21S49.1
Fig.8 Example of commands specifying initial data byte RAM locations.
01
.....
(0
l____
LCD column driver for dot matrix graphic displays
PC_F_8_5_7_9______
RAM
bank 0
top of LCD
000000000000000
1000000000000
bank 1
/000000000
00000000
0000000
000000
00000
~
ggg
0000
/0000
// 000
LCD
«
....
«
c
I2
w
:2:
0..
o
..J
W
>
W
C
lZ21550
Fig.9 Relationship between display and SET START BANK;
1:32 multiplex rate and start bank = 2.
"1
(January 1989
461
_Jl________
__
PC_F85_79
12 C-BUS PROTOCOL
Two 7-bit slave addresses (0111100 and 0111101) are reserved for both the PCF8578 and PCF8579.
The least-significant bit of the slave address is set by connecting input SAO to either 0 (VSS) or 1
(VDD). Therefore, two types of PCF8578 or PCF8579 can be distinguished on the same 12C-bus
which allows:
(a) one PCF8578 to operate with up to 32 PCF8579s on the same 12C-bus for very large applications.
(b) the use of two types of LCD multiplex schemes on the same 12C-bus.
In most applications the PCF8578 will have the same slave address as the PCF8579.
The 12C-bus protocol is shown in Fig. 10. All communications are initiated with a start condition (5)
from the 12 C-bus master, which is followed by the desired slave address and read/write bit. All devices
with this slave address acknowledge in parallel. All other devices ignore the bus transfer.
In WRITE mode (indicated by setting the read/write bit LOW) one or more commands follow the
slave address acknowledgement. The commands are also acknowledged by all addressed devices on
the bus. The last command must clear the continuation bit C. After the last command a series of data
bytes may follow. The acknowledgement after each byte is made only by the (AO, A 1, A2 and A3)
addressed PCF8579 or PCF8578 with its implicit subaddress O. After the last data byte has been
acknowledged, the 12C-bus master issues a stop condition (P).
In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read from the RAM
following the slave address acknowledgement. After this acknowledgement the master transmitter
becomes a master receiver and the PCF8579 becomes a slave transmitter. The master receiver must
acknowledge the reception of each byte in turn. The master receiver must signal an end of data to the
slave transmitter, by not generating an acknowledge on the last byte clocked out of the slave. The
slave transmitter then leaves the data line HIGH, enabling the master to generate a stop condition (P).
Display bytes are written into, or read from, the RAM at the address specified by the data pointer and
subaddress counter. Both the data pointer and subaddress counter are automatically incremented,
enabling a stream of data to be transferred either to, or from, the intended devices.
In multiple device applications, the hardware subaddress pins of the PCF8579s (AO, A 1, A2 and A3)
are connected to VSS or VDD to represent the desired hardware subaddress code. If two or more
devices share the same slave address, then each device must be allocated with an unique hardware
subaddress.
462
January
19891 (
l__
LCD column driver for dot matrix graphic displays
P_C_F8_5_7_9_ __
acknowledge
by AO, A1, A2 and A3
selected PCF8578s/
PCF8579s only
~
~1byte~ Ln;;'1bytes~
uodale data pOinters
and if necessary
subaddress counter
7Z21547
Fig.10(a) Master transmits to slave receiver (WRITE mode).
«
~
«
c
acknowledge
from master
I:2
w
:?!
c..
LL
o...J
W
>
W
/W
R/W
~ecomes
at this moment master
trans, mitter
a
master receiver and
C
)
PCF8578/PCF8579 slave
recerve: becomes a
~
+
n bytes
slave transmitter
7Z21548
Fig.10(b) Master reads after sending command string (WRITE commands; READ data)'
I
acknowledge
by all addressed
PCF8578s/PCF8579s
acknowledge
from master
no acknowledge
from master
~
~
~
slave address
I
°>>>>;0 1~ 11
1s 1
H: : :DA~A: H: : :DA~A:
L~
R/W
: :
n bytes
-l~_last
byte
--J
: :
11 1 P 1
update data pOinters
and if necessary
subaddress counter
7Z21546
Fig.10(c) Master reads-slave immediately after sending slave address (READ mode).
I
(January 1989
463
___
PCF_857_9_jl________________
12 C-BUS PROTOCOL (continued)
Command decoder
The command decoder indentifies command bytes that arrive on the 12 C-bus_ The most-significant
bit of a command is the continuation bit C (see Fig.11). When this bit is set, it indicates that the
next byte to be transferred will be a command. If the bit is reset, it indicates the conclusion of the
command transfer. Further bytes will be regarded as display data. Commands are transferred in WRITE
mode only.
MSB
LSB
Ic I ~ES; ~F ~p+Df I
lZ21545
C = 0; last command
C = 1; commands continue
Fig.11 General format of command byte.
The five commands available to the PCF8579 are defined in Table 2.
Table 2 Summary of commands
command
description
CODDDDDD
LOAD X-ADDRESS
Oto 39
C10DDDDD
SET MODE
multiplex rate, display status, system type
C110DDDD
DEVICE SELECT
defines device subaddress
C111DDDD
RAM ACCESS
graphic modes, bank select
(D D D D ~ 12 is not allowed; see SET
START BANK opcode)
C11111DD
SET START BANK
defines bank at top of LCD
code
Where:
C = command continuation bit
D = may be a logic 1 or O.
464
January 1989] (
l__
LCD column driver for dot matrix graphic displays
I
P_C_F_8_57_9_ _ _
Table 3 Definition of PCF8578/PCF8579 commands
description
options
command / opcode
SET MODE
LCD drive mode
Icll1 0 lTIE1 EOiM1 MOl
1:8
1: 16
1:24
1:32
MUX
MUX
MUX
MUX
(8 rows)
(16 rows)
(24 rows)
(32 rows)
display status
blank
normal
all segments on
inverse video
system type
e:(
bits M1
0
1
1
0
bits E1
0
0
1
1
MO
defines LCD drive mode
1
0
1
0
EO
defines display status
0
1
0
1
defines system type
bit T
le:(
C
IZ
PCF8578 row only
0
PCF8578 mixed mode 1
w
:E
0..
o...J
SET START BAN K
start bank pointer bits B 1
BO
bank
bank
bank
bank
0
1
0
1
W
>
W
C
Ic 11 1 1 1 11 B1 BO
I
DEVICE SE LECT
I
Ic 11 1 0 A3 A2 A 1 AO
bits
I
0
1
2
3
0
0
1
1
A3 A2 Al AO
4-bit binary value of 0 to 15
defines pointer to RAM bank
corresponding to the top of
the LCD. Useful for scrolling,
pseudo-motion and backgrou nd
preparation of new display
four bits of immediate data,
bits AO to A3, are transferred
to the subaddress counter to
define one of sixteen hardware
subaddresses
'1 (January
1989
465
• •'
___PC_F85_79_Jl_________________
12 e BUS PROTOCOL (continued)
Table 3 (continued)
RAM ACCESS
Ie 11
I
I
1 1 G 1 GO Y 1 YO
description
options
command / opcode
I
RAM access mode bits Gl
GO
character
half graphic
full graphic
not allowed*
0
0
0
1
1
0
bits
Yl
YO
two bits of immediate data,
bits YO to Y 1, are transferred
to the Y-address pointer to
define one of four banks for
RAM access
X5 X4 X3 X2 Xl XO
six bits of immediate data,
bits XO to X5, are transferred
to the X-address pointer to
define one of forty display
RAM columns
1
1
2-bit binary value of 0 to 3
LOAD X-ADDRESS
[CIOIX5 X4 X3 X2 Xl XO I
bits
6-bit binary value of 0 to 39
* See opcode for SET START BAN K.
466
January 1989\ (
defines the auto-increment
behaviour of the address for
RAM access
PCF8579
LCD column driver for dot matrix graphic displays
CHARACTERISTICS OF THE 12 C-BUS
The 12 C-bus is for bidirectional, two-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCl). Both lines must be connected to a
positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during
the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a
control signal.
SDA
X\...--l-_~=~~
i
/
---~
SCL
data line
stable:
data valid
<
<
C
I-
change
of data
allowed
7Z87019
Fig.12 Bit transfer.
IZ
Start and stop conditions
o
..J
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-lOW transition of the
data line, while the clock is HIGH, is defined as the start condition (S). A lOW-to-HIGH transition of
the data line while the clock is HIGH, is defined as the stop condition (P).
w
::iE
a..
W
>
W
C
SOA
----t\.--Il----c'----- ==~---...>......-----+-r-J-rt_-I
SCL
I
: s:
:
:
L _ _ _ .J
start condition
I
\
.
/r - - - \
-.JI
\1....._ _
I
i
SOA
I
I
1
SCL
L _ _ _ .J
stop condition
7Z87005
F ig.13 Definition of start and stop condition.
") ("January 1989
467
PCF8579
CHARACTERISTICS OF THE 12 C-BUS (continued)
System configuration
A device transmitting a message is a "transmitter", a device receiving a message is the "receiver". The
device that controls the message flow is the "master" and the devices which are controlled by the
master are the "slaves".
SDA----------~------------~--------------~------------~------------~--
SCL--~------4_----~------_+----~~------r_----~------~----~------_T--
F ig.14 System configuration.
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is unlimited. Each data byte of eight bits is followed by one acknowledge bit. The acknowledge
bit is a HI G H level put on the bus by the transm itter, whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception
of each byte. Also a master must generate an acknowledge after the reception of each byte that has
been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line
during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal the end of a data transmission to the transmitter by not generating an acknowledge
on the last byte that has been clocked out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.
clock pu Ise for
acknowledgement
start
condition
I
~
I
SCL FROM
MASTER
I
I
I
I
--~
I
DATA OUTPUT
BY TRANSMITTER
~'--L..-/-----'X'---_)(~~)(--..J7
I
S
--~
DATA OUTPUT
BY RECEIVER
7Z87007
Fig.15 Acknowledgement on the 12 C-bus.
Note
The general characteristics and detailed specification of the 12 C-bus is available on request.
468
January
1989
~
('"
PCF8579
LCD column driver for dot matrix graphic displays
RATINGS
Limiting values in accordance with the Absolute Maximum System (lEC 134)
parameter
symbol
min.
max.
unit
Supply voltage range
VOO
-0.5
+8.0
V
lCO supply voltage range
VlCO
VDO -11
VOO
V
Input voltage range at
SOA, SCl, SYNC, ClK, TEST,
SAO, AO, A 1, A2 and A3
VI1
VSS -0.5
VOO+0.5
V
VI2
VlCO -0.5
VOO+0.5
V
V01
VSS -0.5
VOO+0.5
V
V
V3 to V4
Output voltage range at
SOA
CO to C39
V02
VlCO -0.5
VOO+0.5
OC input current
II
-10
10
rnA
OC output current
10
-10
10
rnA
VOO, VSS or VlCO current
Power dissipation per package
100, ISS, I LCO
-50
50
rnA
Ptot
mW
Power dissipation per output
Po
-
400
l-
100
C
Storage temperature range
Tstg
-65
+150
mW
oC
«
e:(
I-
Z
~
HANDLING
w
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see
'Handling MOS Oevices').
c..
9
~
C
1
(January 1989
469
_Jl________
__
PCF_857_9
DC CHARACTERISTICS
VOD = 2.5 V to 6.0 V; VSS
unless otherwise specified
= 0 V;
VLCO
= VOO -3.5
conditions
parameter
V to VOO -9 V; Tamb
= -40 oC to +85 oC;
symbol
min.
typo
max.
unit
VOO
2.5
-
6.0
V
VLCO
VOO-9 -
VOO -3.5
V
Supply
Supply voltage
LCO supply voltage
Supply current
note 1;
fCLK = 2 kHz
Power-on reset level
note 2
1001
-
9
20
JlA
VPOR
-
1.3
1.8
V
Logic
I nput voltage LOW
VIL
VSS
-
0.3 VOO
V
Input voltage HIGH
VIH
0.7 VOO
-
VOO
V
1L1
-1
-
1
JlA
leakage cu rrent
at SOA, SCL, SYNC,
ClK, TEST, SAO,
AO, A1, A2 and A3
VI
= VOO or VSS
SDA output current LOW
Val = 0.4 V;
VOO = 5 V
IOL
3
-
-
mA
I nput capacitance
note 3
CI
-
-
5
pF
IL2
-2
-
2
JlA
±VOC
-
20
-
mV
RCOL
-
3
6
kn
LCD outputs
leakage cu rrent at
V3 to V4
VI
= VOO or VLCD
DC component of LCO
drivers CO to C39
Output resistance at
CO to C39
470
January
19891 (
note 4
PCF8579
LCD column driver for dot matrix graphic displays
AC CHARACTERISTICS (note 5)
VDD = 2.5 to 6 V; VSS
otherwise specified
= 0 V; VLCD = VDD -3.5 V to VDD -9 V; Tamb = -40 to +85 oC; unless
parameter
conditions
symbol
min.
typo
max.
unit
Clock frequency
50% duty factor
fCLK
-
*
10
kHz
D river delays
VDD - VLCD
with test loads
tPLCD
-
-
100
J,ts
SCL clock frequency
fSCL
-
-
100
kHz
Tolerable spike width
on bus
tsw
-
-
100
ns
tBUF
4.7
-
-
J,ts
tsu; STA
4.7
-
-
J,ts
Start condition
hold time
tHD; STA
4.0
-
-
J,ts
SCL LOW time
tLOW
4.7
-
-
J,ts
SCL HIGH time
tHIGH
4.0
-
-
J,ts
SCL and SDA rise time
tr
-
-
1.0
J,ts
SCL and SDA fall time
tf
-
-
0.3
J,ts
Data set-up time
tsu; DAT
250
-
-
ns
Data hold time
tHD; DAT
0
-
-
ns
Stop condition
set-up time
tsu; STO
4.0
-
-
J,ts
= 9 V;
12 C-bus
Bus free time
Start condition
set-up time
«
le:(
C
I2
w
:i!:
DO
..J
W
>
W
o
repeated start
codes only
* Typically 0.9 to 3.3 kHz.
'1
(January 1989
471
PCF8579
Notes to the characteristics
1. Outputs are open; inputs at VDD or VSS; 12 C-bus inactive; clock with 50% duty cycle.
2. Resets all logic when VDD
< VPOR.
3. Periodically sampled; not 100% tested.
4. Resistance measured between output terminal (CO to C39) and bias input (V3 to V 4, VDD and
VLCD) when the specified current flows through one output under the following conditions
(see Table 1):
VOP= VDD - VLCD = 9 V;
V3 - VLCD ~ 4.70 V; V 4 - V LCD ~ 4.30 V; I LOAD = 100 /lA.
5. All timing values are referred to VIH and VIL levels with an input voltage swing of VSS to VDD.
1.5 kO
SDA~VDD
(2%)
CO to C39
---I~
1 nF
7Z21S34.1
Fig.16 Test loads.
472
January
19891 (
l____
LCD column driver for dot matrix graphic displays
P_C_F8_5_7_9______
ClK
•t
•t
r-=========~ 0.5 v
CO to
(V DD - V lCD
C39
= 9 V)
~==========~
0.5 V
lZ21530.1
Fig.17 Driver timing waveforms.
«
I-
«
C
SDA
2'"'"
w
~
0-
o
-I
SCL
W
>
W
C
--.. tHD;STA
1-
--..
tSU;DAT
I
SDA
I
-I
tSU;STA
tSU;STO
7Z21536
Fig.18
2
1
C-bus timing waveforms.
1
(January 1989
473
.j:Io
.....
.j:Io
"1J
()
APPLICATION INFORMATION
"TI
t....
CJ
::J
CO
c:
(]1
-<
(0
-..J
CJ
co
00
CO
VOO
VOO
OR
32 rows
1 : 32 multiplex rate
32 x 40 x k dots (1 .. k ... 16)
20480 (max)
lCO DISPLAY
V2
II
JR
V3
II
] (4"2-3) R
V
PCF8578
4 (ROW MODE)
)R
8/
~I
V5
It 40 columns
/40 columns
40 columns
unu:ed columns
JR
V lCO
1\
SAO -VSS
V lCO
I'"
Vss
osc
SOA SCl ClK SYNC
1
V OO -
ROSC _
VSS
Voo
V lCO
, - V4
r- V3
#1
PCF8579
'"~}J
~}J
V OO -
r-
r----
A21-
r-
A31-,
r-
A1
, baddress k-1
subaddress 1
subaddress 0
#2
PCF8579
V OO -
-
}J
#k
PCF8579
,r-
VSS SYNC ClK SCl SOA SAO
'DO
-r-----
I
I
I
VSS
VSS
VSS
I
I
VSS
VSS
/
[1 1
I
Vss
/
/ f--
/ L
iCl
iDA
/
/ /
Fig.19 Typical LCD driver system with 1:32 multiplex rate.
/
7, '21551.1
DEVELOPMENT DATA
r-
(")
o
n
J L
V DD
VSS
I
I
~=/J
l
o
~
3
V
:::J
DD
VSS
I
I
V DD
VSS
I
I
~
;C:'
SAO SDA SCl ClK SYNC VSS
1+
j[
+
I+-
#k
PCF8579
1r-VDD
subaddress k-1
j[
#2
PCF8579
-VOD
rows
l
R
C
r
C
rJ R
C
R
PCF8578
(RDW MDDE)
~
t
40
columns
unused columns
SAO -
[) R
V lCD
-
V DD -
.1 SDA
'" SCl elK SYNC
=~ R OSC
VSS
VSS
V OD
V lCD
r-+
V3
r+
V4
DD-rr--
n'
9:
Qj
r
columns
40
subaddress 0
#1
PCF8579
Mr}J
,.--.
A2 '--
r-+
A3 -
J
-
columns
40
subaddress k-l
~}J
V DD -
V DD -
r-
Al
f
subaddress 1
]J
#2
PCF8579
r+
#k
PCF8579
r-+
~
Vss
1
Vss
1
Vss
1
Vss
/
1
1
vss
VSS
J
J J
( IJ
OA
::r
-0
Q)
CO
"C
I
I
VSS SYNC ClK SCL SDA SAO
1
c...
00
1'"
columns
VSSIvDD
VlCD
~l
~
Q)
16x40xkdots(k<;16)
(10 240 dots max.)
rows
V5
co
Q)
q-
1 :16 multiplex rate
16
V4
-<
3
V DD r - V DD
-<
en
V3
:::J
C
c..
o
.-+
V2
C
Q)
Q
V4
1: 16muftiplex rate
16 x 40 x k dots (k <; 16)
(10 240 dots max.)
LCD DISPLAY
"
#1
PCF8579
AO
columns
16
R
C
-
subaddress 0
1'"
columns
VDD
jl= :
!+
!+V lCD
I+V3
)('
subaddress 1
f'"
VDD
+-
~
"'tJ
(')
J
L
"ex>
01
F ig,20 Split screen application with 1: 16 multiplex rate for improved contrast,
~
.....,
0'1
--.J
CO
~
en
»
~
L
I
I
CO)
~~
:J
c:
0)
-<
voo
vss
j
I
~
co
""V
r-
n
Vss
vl°
Voo
vis
j
J
~
0
z
SAO SOA SCl ClK SYNC VSS
~
~
#k
PCF8579
~
rt
_VOO
suboddross k-l
r{~
#2
PCF8579
r-VOO
!"
suboddressl
1'"
Voo
#1
PCF8579
lCO OISPLAY
Z
VlCO
0
-
:J:J
3:
»
-I
VOO _VOO
. - AO
0
Z
no
!'"
suboddross 0
columns
:J
.-+
:i"
c:
CD
+--
V2
II
."
V3 +
V _
4
1:32multiptexrate
32 x 40 x k (k" 16)
(20480 dots max.)
JR
C
r{=::
columns
columns
Voo
14I+I+-
E;
32
!
R ?v'2-3)R
C
r
C
11
II
"
r
C
C
..
V3
V4
rows
PCF8578
(ROW MOOE)
~
R
"
1 :32 multiplex rate
32 x 40 x k (k" 16)
(20480 dots max.)
32
t
40
columns
unused columns
V5
[
VOO -
VlCO
I)
columns
40
t
columns
40
subaddress 1
VSS
OSC
vi
55 SOA SCl ClK SYNC
r-+
ROSC
VO O -
VOO
r-
VSS
v lO-"-~
t
subaddress 0
subaddress k-l
SAO -VSStvOO
R
VlCO
-
VlCO
V3
~ V4
#1
PCF8579
"r}J
V OO -
AIr-
r-
A2 ' -
r-+
A3
~
;}J
#2
PCF8579
r-+
;}J
#k
PCF8579
r-+
+
~
VSS SYNC ClK SCl SOA SAO
V~s
v!s
V~s
I
VSS
I
J
J
v!s
v!s
I
L
:l
lA
---.--- .
Fig.21 Split screen application using double screen with 1 :32 multiplex rate.
'"tJ
()
"T1
(X)
01
-....I
<0
LCD column driver for dot matrix graphic displays
l____
P_C_F8_5_7_9______
~
II II IIIII ~
II II II I II §
Q)
~
0
E
....Q)
>
~
s:
e
.=
00
.....
L!)
00
u.
u
e:.
Q)
.....
~
«
I«0
x
Q)
a.
E
::J
E
l-
z
N
W
~
M
0
..c
.....
Il.
...J
.~
W
>
w
c::
Q)
~
C
t.)
II)
Q)
0,
c::
.iii
c;
.§
.~
"-'"
()
~
»c>~g~
Q)
c::
CtI
a.
Q)
0,
c::
.iii
0
~
a.
E
CtI
~0!-
X
W
N
N
.!?
u.
1
(January 1989
477
_Jl_________
__
PC_F85_79
CHIP DIMENSIONS AND BONDING PAD LOCATIONS
M
«
0 000000000000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCF8579
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A2
A1
AO
V DD
n.c.
V3
.61
mm
V4
V LCD
C39
C38
C37
C36
0
0"
0
1
"
~
()
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
0 OOODOOOOOOO
..,.
M
()
M
M
()
N
M
()
M
()
0>
CD
N
()
()
0
M
N
2.95
mm
()
I'N
()
'"
N
()
It)
..,.
N
()
()
N
M
N
()
7Z21537
Chip area: 13.6 mm 2
Bonding pad dimensions: 120 ILm x 120 ILm
Fig.23 Bonding pad locations.
478
January
19891 (
PCF8579
LCD column driver for dot matrix graphic displays
Table 4 Bonding pad locations (dimensions in Mm)
All x/V co-ordinates are referenced to the bottom left corner, see Fig.23.
pad
e:(
l-
e:(
Cl
IZ
w
~
c..
o-I
W
>
W
Cl
SDA
SCl
SYNC
ClK
VSS
TEST
SAO
A3
A2
A1
AO
VDD
n.c.
V2
V3
VlCD
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
X
Y
pad
X
Y
1726
1522
1318
1114
910
688
442
160
160
160
160
160
160
160
160
160
160
160
160
160
160
442
688
910
1114
1318
1522
1726
4444
4444
4444
4444
4444
4444
4444
4444
4222
4018
3814
3010
2806
2602
2398
2194
994
790
586
382
160
160
160
160
160
160
160
160
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
CO
1972
2176
2380
2584
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2788
2584
2380
2176
1972
160
160
160
160
160
472
736
976
1180
1384
1588
1792
1996
2200
2404
2608
2812
3016
3220
3424
3628
3868
4132
4444
4444
4444
4444
4444
Purchase of Philips' 12 C components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system
provided the system conforms to the 12 C specifications defined
by Philips.
1
(January 1989
479
_Jl________
__
PC_F85_79
CHIP-ON GLASS INFORMATION
Voo
--------------,------------------~----
Voo
V3------~
V.------~
V
- - - - - -_____
leo
VSS
elK
sel
SOA
,,---V3
____- - v .
VLCD
VSS
elK
I
I
I I
I I
I
I
I
I
I
I
I
I
I
I
-,.".• -I
~
111-------------------------------------==
F ig.24 Typical chip-on glass application (viewed from underside of chip).
Note to Fig.24
If inputs SAO and AO to A3 are left unconnected they are internally pulled-up to VOO.
480
January 1989\ (
l___
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
256
X
P_C_F_8_58_2_A______
8-bit STATIC CMOS EEPROM
2
WITH 1 C-BUS INTERFACE
GENERAL DESCRIPTION
The PCF8582A is a 2 Kbits 5 Volt electrically erasable programmable read only memory (EEPROM)
organized as 256 by 8-bits. It is designed in a floating gate CMOS technology.
As data bytes are received and transmitted via the serial 12 C·bus, an eight pin DI L package is sufficient.
Up to eight PCF8582A devices may be connected to the 12 C·bus.
Chip select is accomplished by three address inputs.
Timing of the Erase/Write cycle can be done in two different ways; either by connecting an external
clock to the "Programming Timing Control", pin (7 or 13), or by using an internal oscillator.
If the latter is used an RC time constant must be connected to pin 7 or 13.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Non-volatile storage of 2 Kbits organized as 256 x 8
Only one power supply required (5 V)
On chip voltage multiplier for erase/write
Serial input/output bus (1 2 C)
Automatic word address incrementing
Low power consumption
One point erase/write timer
Power on reset
10,000 erase/write cycles per byte
10 years non-volati Ie data retention
I nfinite number of read cycles
Pin and address compatible to PCF8570, PCF8571, PCF8582 and PCD8572
External clock signal possible.
A version with automotive temperature range -40 to + 125 oC
(PCF8582B) and a version with extended temperature range
-40 to + 85 °C (PCF8582C) are in preparation.
PACKAGE OUTLINE
PCF8582AP; 8-lead dual in line; plastic (SOT97).
PCF8582AT; 16-lead mini-pack; plastic (S016L; SOT162A).
I
(May 1989
481
-I=a
00
N
'"tJ
(')
"'TI
(X)
s:
Ql
-<
01
PCF8582AP
PCF8582AT
Voo
co
CO
CO
ss~~ I,
:,---'-----'
I
:: I j I
j
I--+---+-- PTe
II
Vss
7Z96673.1
Fig. 1 Block diagram.
(X)
I\)
»
l___
256 x 8-bit Static CMOS EEPROM with 12 C-bus interface
P_C_F_8_5_8_2A______
AD
v DD
A1
PTC
A2
SCL
vss
SDA
7Z96671.2
1
2
3
4
5
6
7
8
AO
A1
A2
} address inputs/test
mode select
ground
VSS
SDA} 2
.
SCL
I C·bus lines
PTC
VDD
programming time control
positive supply
Fig.2 (a) Pinning diagram.
n.c.
n.c.
VDD
«
I«
0
PTe
SCL
IZ
w
:E
c..
0
n.c.
..J
w
>
w
7Z95939.1
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
n.c.
n.c.
AO
A1
A2
VSS
n.c.
n.c.
n.c.
n.c.
}
address inputs/test
mode select
ground
SDA} 12 C-bus lines
SCL
programming time control
PTC
VDD positive supply
n.c.
n.c.
Fig.2 (b) Pinning diagram.
VOD
14
RE/W
PCF8582AT
13
81--__-
V OD
PCF8582AP
PTC
CE/W
6
Vss
7Z23047.1
7Z23046.1
Figs.3 (a) and (b) RC circuit connections to PCF8582AP and PCF8582AT
when using the internal oscillator
1
(May 1989
483
Jl___________________________________
_____P_C_F_8_5_82_A___
FUNCTIONAL DESCRIPTION
Characteristics of the 12 C-bus
The 12 C-bus is intended for communication between different ICs. The serial bus consists of two
bi-directionallines, one for data signals (SDA), and one for clock signals (SCl). Both the SDA and
the SCl lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the
data line while the clock line is H IG H will be interpreted as control signals.
The following bus conditions have been defined:
Bus not busy; both data and clock lines remain HIGH.
Start data transfer; a change in the state of the data line, from HIGH to lOW,
while the clock is HIGH defines the start condition. Stop data transfer; a change in the state of the data
line, from lOW to HIGH, while the clock is HIGH, defines the stop condition.
Data valid; the state of the data line represents valid data when, after a start condition, the data line
is stable for the duration of the HI G H period of the clock signal. There is one clock pu Ise per
bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition; the number
of the data bytes, transferred between the start and stop conditions is limited to two bytes in the
ERASE/WRITE mode and unlimited in the READ mode. The information is transmitted in bytes and
each receiver acknowledges with a ninth bit.
Within the 12 C-bus specifications a low speed mode (2 kHz clock rate) and a high speed mode (100 kHz
clock rate) are defined. The PCF8582A operates in both modes.
By definition a device that sends a signal is called a "transmitter", and the device which receives the
signal is called a "receiver". The device which controls the signal is called the "master". The devices
that are controlled by the master are called liS laves".
Each word of eight bits is followed by one acknowledge bit. Th is acknowledge bit is a HI G H level put
on the bus by the transmitter. The master generates an extra acknowledge related clock pulse.
The slave receiver which is addressed is obliged to generate an acknowledge after the reception of
each byte.
The master receiver must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable lOW during the HIGH period of the acknowledge clock pulse in
clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an end of data to the
slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this condition the transmitter must leave the data line HIGH to enable the master generation
of the stop condition.
Note
Detailed specifications of the 12 C-bus are available on request.
484
May
19891 (
l___
256 x 8-bit Static CMOS EEPROM with 12 C-bus interface
P_C_F_8_5_8_2A______
12 C-Bus Protocol
The 12 C-bus configurations for different READ and WRITE cycles of the PCF8582A are shown in
Fig. 4, (a), (b) and (c).
acknowledge
from slave
acknowledge
from slave
~
~
S
SLAVE ADDRESS
acknowledge
from slave
WORD ADDRESS
~
DATA
A
~
DATA
A
II
R/W
7Z94117.1
acknowledge
from slave
auto increment
word address (2)
(1) After this stop condition the erase/write cycle starts and the bus is free for another transmission.
The duration of the erase/write cycle is approximately 30 ms if only one byte is written and 60 ms
if two bytes are written. During the erase/write cycle the slave receiver does not send an
acknowledge bit if addressed via the 12 C-bus.
(2) The second data byte is voluntary. It is not allowed to erase/write more than two types.
Fig. 4(a) Master transmitter transmits to PCF8582A slave receiver (E RASE/WR ITE mode).
acknowledge
from slave
«
~
C
acknowledge
from slave
+
acknowledge
from master
+
~
+
L-S-L~S_L~A_V~E_A~D~D_R~E_S~S_L~0L-A~~~W~O~R-D~A-D~D-R~E-S~S~_A~S
__L-~SL_A~V_E~A~D_D~R_ES~S~~'-LA_+~~~-DA~T-A~~~_±~A --~
t-
t
Z
w
at this moment master }
transmitter .becomes
master receiver and
PCF8582A slave receiver
becomes slave transmitter
R/W
::2E
Q"
o
..J
acknowledge
from slave
7Z96672.1
jwJR/W
-----
b t
n yes
~
auto increment
word address
W
>
W
C
no acknowledge
from master
,I
Fig. 4(b) Master reads PCF8582A slave after setting
word address (write word address; READ data).
L ___ I : : :D~TA: : : 1,1 p
l...--
lastbyte
-4
aui:O increment
word address
acknowledge
from slave
S
~L~VE>~D~ES~
acknowledge
from master
t
I, I AI
.;w
7Z87033.4
: :
no acknowledge
from master
t
:DA:TA:
L--"
: : I AI:
b,,~ -----it
t
: : :
: :
L - - I,. by"
auto increment
word address
: I, I p
--iI
1
auto increment
word address
Fig.4(c) Master reads PCF8582A slave immediately after first byte (READ mode).*
Note: the slave address is defined in
accordance with the 12 C-bus
specification as:
o
o
I A2 I A 1 I AO IR/W I
* The device can be used as read only without the programming clock.
' ] (May 1989
485
Jl~__________________________________
_____P_C_F_8_58_2_A___
J2 C-bus
timing
SDA
sel
-
-
tHo;STA . -
t SU;DAT
SDA
--I tSU;STA
7Z87013.2
1tSU;STO
Fig.5 12 C-bus timing.
---~
PTe!l)
SOA
sel
--"--I
7Z23045.1
STOP
(a)
tr
tf
tOEL
---~
PTe(l)
SOA
sel
STOP
(b)
7Z23044.1
(1) I f external clock for PTC is chosen, this information is latched internally by leaving pin 7 lOW
after transmission of the eight bit of the word address (negative edge of SCll. The state of PTC then,
may be previously undefined.
Fig.6 (a) One-byte ERASE/WRITE cycle; (b) two-byte ERASE/WRITE cycle.
486
May
19891 (
l___
256 x 8-bit Static CMOS EEPROM with 12 C-bus interface
P_C_F_8_5_8_2A______
Ratings
Limiting values in accordance with the Absolute Maximum System (IEC 134)
I
parameter
symbol
Supply voltage
min.
max.
unit
VOO
-0.3
+7
V
Voltage on any input pin input impedance 500 n
VI
VSS - 0.8
VOO + 0.8
V
Operating temperature range
Tamb
T stg
-40
+85
Storage temperature range
-65
+150
°c
°c
Current into any input pin
IIII
1
mA
Output current
1101
-
10
mA
«
I«
Q
I-
2:
w
~
0.
o..J
W
>
LU
o
Purchase of Philips' 12 C components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system
provided the system conforms to the 12 C specifications defined
by Philips.
487
l_ _ __
PCF8582A
CHARACTERISTICS
VOO = 5 V; VSS =
a V; T amb = -40 to +85 °C; unless otherwise specified.
symbol
min.
typo
max.
unit
VOO
4.5
5.0
5.5
V
VOO max.
fSCL = 100 kHz
100
-
-
0.4
mA
VOD max.
100W
-
-
2.0
mA
VOO max.
1000
-
-
10
conditions
arameter
perating supply
voltage
a perating supply
current R EAO
a perating supply
current
WR ITE/ERASE
S tandby supply
current
I JiA
I
nput PTC
nput voltage H IG H
VOO - 0.3 -
nput voltage LOW
-
-
-
V
VSS + 0.3
V
nput SCL and
input/output SDA
I nput voltage LOW
VIL
-0.3
-
1.5
V
I nput voltage HIGH
VIH
3.0
-
VOO + 0.8
V
10L = 3 mA
VOO = 4.5 V
VOL
-
-
0.4
V
current HIGH
VOH = VOO
ILO
-
-
1
JiA
nput leakage
current (SC L)
VI = \!OO or VSS
a utput voltage LOW
a utput leakage
Clock frequency
nput capacitance
(SCL;SOA)
488
III
-
-
1
JiA
fSCL
a
-
100
kHz
CI
-
-
7
pF
T ime the bus must be
free before new
transm ission can start
tBUF
4.7
-
-
JiS
Start condition hold
time after which first
clock pulse is
generated
THO;STA
4
-
-
JiS
May
19891 (
PCF8582A
256 x 8-bit Static CMOS EEPROM with 12 C-bus interface
symbol
min.
typo
max.
uni1
The lOW period
of the clock
tlOW
4.7
-
-
f..lS
The HI G H period
of the clock
tHIGH
4.0
-
-
f..lS
tSU;STA
4.7
-
-
f..lS
tHD;DAT
5.0
-
-
IlS
parameter
conditions
Set-up time for
start condition
repeated start only
2
1 C-
Data hold time for
bus compatible masters
Data hold time for
2
1 C devices
note 1
tHD; DAT
0
-
-
ns
Date set up time
tsu; DAT
250
-
-
ns
Rise time for SDA
and SCl lines
tr
-
-
1
f..lS
Fall time for SDA
and SCl lines
tf
-
-
300
ns
W
Cl
Resistor used for E/W
cycle of 30 ms
II
Programming
frequency using
external clock
Frequency
Period lOW
Period HIGH
Rise-time
Fall-time
Delay-time
Data retention time
Tamb
Note to the characteristics
1. The hold time required to bridge the undefined region of the falling edge of SCl
must be internally provided by a transmitter. It is not greater than 300 ns.
1
(May 1989
489
Jl__________________________________
_____P_C_F8_5_82_A___
CHARACTERISTICS (continued)
E/W programming time control
A. Using external resistor RE/W and capacitor CE/W (see Table 1)
Table 1 Recommended R, C combinations
RE/W
(kn)
note 1
CE/W
(nF)
note 2
tE/W (typ.)
(ms)
note 3
56
3.3
34
56
2.2
21
22
3.3
13
22
2.2
7.5 (note 4)
Notes to Table 1
1. Maximum tolerance is 10%.
2. Maximum tolerance is 5%.
3. Actual E/W lines are mainly influenced by the tolerances in values of Rand C.
4. Minimum allowed tE/W is 5 ms (see CHARACTERISTICS).
B. Using an external clock (see Table 2 and Fig.6)
Table 2 E/W programming time control using an external clock
490
parameters
symbol
min.
max.
unit
frequency
kHz
fp
10.0
50.0
period LOW
tLOW
10.0
-
period HIGH
tHIGH
10.0
-
rise time
tr
-
300
ns
fall time
tf
-
300
ns
delay time
td
0
-
ns
May
19891 (
s
s
l___
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
P_C_F_8_5_8_3______
CLOCK CALENDAR WITH 256 X 8-BIT 8T A TIC RAM
GENERAL DESCRIPTION
The PCF8583 is a low power 2048-bit static CMOS RAM organized as 256 words by 8-bits. Addresses
and data are transferred serially via a two-line bidirectional bus (1 2C). The built-in word address
register is incremented automatically after each written or read data byte. One address pin AO is used for
programming the hardware address, allowing the connection of two devices to the bus without
additional hardware. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM are
used for the clock/calendar and counter functions. The next 8 bytes may be programmed as alarm
registers or used as free RAM space.
Features
•
•
•
•
•
•
•
•
•
•
2
1 C-bus interface operating supply voltage: 2.5 V to 6 V
Clock operating supply voltage (0 to 70 oC): 1.0 V to 6 V
Data retention voltage: 1.0 V to 6 V
Operating current (fSCl = 0 Hz): max. 50 p,A
Clock function with four year calendar
24 or 12 hour format
32.768 kHz or 50 Hz time base
Serial input/output bus WC)
Automatic word address incrementing
Programmable alarm, timer and interrupt function
PCF8583
- ~
OSCO 4
ascI
-
SDA
POWER ON
RESET
CONTROL
LOGIC
8
'---
- -4
SCL
DNiDER
1 :256
100:128
7
INT
AO
100 Hz
OSCILLATOR
32.768 kHz
-
~
------------------------
i
~
12 C-BUS
INTERFACE
ADDRESS
REGISTER
- 4
II
.Ii
"'
'I
~I
Control/ Status
Hundredths of a second
Seconds
Minutes
Hours
Year/Date
Weekdays/Months
Timer
Alarm control
Alarm registers
or RAM
/I..
00
01
07
08
OF
RAM
(256x8)
vFF
I
I
7ZB1191.2
Fig.1 Block diagram.
PACKAGE OUTLINES
PCF8583P: 8-lead 01 L; plastic (SOT97).
PCF8583T: 8-lead mini-pack; plastic (S08l; SOT176A).
1
(FebrUary 1989
491
_Jl_________
__
PC_F85_83
PINNING
OSCI
oscillator input, 50 Hz or event-pulse input
2
OSCO
oscillator output
3
4
5
6
AO
address input
VSS
SDA
serial data line
SCL
serial clock line
7
INT
open drain interrupt output (active low)
8
VDD
positive supply
negative supply
1
12C-bus
lZ81192
Fig.2 Pinning diagram.
RATINGS
Limiting values in accordance with the Absolute Maximum System (lEC 134)
parameter
symbol
min.
max.
unit
Supply voltage range (pin 8)
VDD
-0.8
+ 7.0
V
'DD; ISS
-
50
rnA
V
Supply current (pin 4 or pin 8)
Input voltage range
VI
-0.8 to VDD
+0.8
DC input current
II
-
10
rnA
DC output current
10
-
10
rnA
Power dissipation per package
Ptot
-
300
mW
Power dissipation per output
Po
-
50
Operating ambient temperature range
Tamb
T stg
-40
+85
mW
oC
-65
+ 150
°C
Storage temperature range
HANDLING
I nputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is good practice to take normal precautions appropriate to handling MOS devices
(see 'Handling MOS Devices')'
492
February
19891 (
Clock calendar with 256 x a-bit static RAM
l____
PC
__
F8_5_8_3______
FUNCTIONAL DESCRIPTION
The PCF8583 contains a 256 by 8-bit RAM with an 8-bit auto-increment address register, an on-chip
32.768 kHz oscillator circuit, a frequency divider, a serial two-line bidirectional 12 C-bus interface and a
power-on reset circuit.
The first 8 bytes of the RAM (memory addresses 00 to 07) are designed as addressable 8-bit parallel
registers. The first register (memory address 00) is used as a control/status register. The memory addresses 01 to 07 are used as counters for the clock function. The memory addresses 08 to OF are free
RAM locations or may be programmed as alarm registers.
Counter function modes
When the control/status register is set a 32.768 kHz clock mode, a 50 Hz clock mode or an eventcounter mode can be selected.
In the clock modes the hundredths of a second, seconds, minutes, hours, date, month (four year
calendar) and weekdays are stored in a BCD format. The timer register stores up to 99 days. The eventcounter mode is used to count pulses applied to the oscillator input (OSCO left open). The event
counter stores up to 6 digits of data.
When one of the counters is read (memory locations 01 to 07), the contents of all counters are strobed
into capture latches at the beginning of a read cycle. Therefore faulty reading of the count during a
carry condition is prevented.
<
<
o
IIZ
w
:?!
c..
o..J
W
>
W
o
When a counter is written, other counters are not affected.
Alarm function modes
By setting the alarm enable bit of the control/status register the alarm control register (address 08) is
activated.
By setting the alarm control register a dated alarm, a daily alarm, a weekday alarm or a timer alarm
may be programmed. In the clock modes, the timer register (address 07) may be programmed to count
hundredths of a second, seconds, minutes, hours or days. Days are counted when an alarm is not
programmed.
Whenever an alarm event occurs the alarm flag of the control/status register is set. A timer alarm event
will set the alarm flag and an overflow condition of the timer will set the timer flag. The open drain
interrupt output is switched on (active LOW) when the alarm or timer flag is set (enabled). The flags
remain set until directly reset by a write operation.
When a timer function without any alarm function is programmed the remaining alarm registers
(addresses 09 to OF) may be used as free RAM space.
1(
February 1989
493
___PC_F85_83_Jl________________
Control/status register
The control/status register is defined as the memory location 00 with free access for reading and
writing via the 12C-bus. All functions and options are controlled by the contents of the control/status
register (see F ig.3).
MSB
7
LSB
6
5
I
4
3
2
I
0
I
J
Memory location 00
reset state: 0000 0000
Timer flag (50% duty factor
seconds flag if alarm
enable bit is 0)
Alarm flag (50% duty factor
minutes flag if alarm
enable bit is 0)
Alarm enable bit:
o
alarm disabled/set: flags toggle
(memory locations 08 to OF
are free RAM space)
enable alarm control register
(memory location 08 is the
alarm control register)
Mask flag:
o
read locations 05 to 06
unmasked
read date and month count
directly
Function mode:
00
01
10
11
clock mode 32.768 kHz
clock mode 50 Hz
event-counter mode
test modes
Hold last count flag:
o
1
count
store and hold last count in
capture latches
Stop counting flag:
o
1
F ig.3 Control/status register.
494
February
19891 (
count pulses
stop counting, reset divider
l____
Clock calendar with 256 x 8-bit static RAM
PC
__
F8_5_8_3______
Counter registers
In the different modes the counter registers are programmed and arranged as shown in Fig.4. Counter
cycles are listed in Tab.le 1.
In the clock modes 24 h or 12 h format can be selected by setting the most significant bit of the
hours counter register. The format of the hours counter is shown in Fig.5.
The year and date are packed into memory location 05 (see F ig.6). The weekdays and months are
packed into memory location 06 (see Fig.7). When reading these memory locations the year and
weekdays are masked OUt when the mask flag of the control/status register is set. This allows the user
to read the date and month count directly.
In the event-counter mode events are stored in BCD format. D5 is the most significant and DO the
least significant digit. The divider is by-passed.
Control 1Status
ControllStatus
00
Hundredths of a second
1/10s
I 1/100s
01
DO
10s secrds 1 s
03
02
05
04
01
02
Minlutes
«
10m
e::(
10h
IZ
10d
l-
o
w
~
W
>
W
o
HOrS
03
free
1h
04
vear)oate
free
1d
05
weekdar 1Month
10m
1m
Q.
o...J
1m
free
06
Timer
TiTer
1d
10d
Alarm control
Hundredthslof a second
1/10s
1/100 s
Alarm jeCOndS
I
T1
TO
07
Alarm control
08
Alarm
01
Alarm
DO
03
02
05
04
09
OA
Alarm Tinutes
Alarm hours
OB
l
free
Alari date
free
Alarm month
free
Alarm timer
Alarm timer
free RAM
free RAM
CLOCK MODES
EVENT COUNTER
OC
00
OE
OF
7Z81195
F ig.4 Register arrangement.
1
(FebrUary 1989
495
___PC_F85_83_Jl________________
Counter registers (continued)
MSB
LSB
I
7
6
5
I
4
3
2
a
~
Memory location 04 (hours counter)
reset state: 0000 0000
Unit hours BCD
Ten hours (0 to 2 binary)
AM/PM flag:
a
1
AM
PM
Format:
a
24 h format, AM/PM flag
remains unchanged
12 h format, AM/PM flag
will be updated
Fig.5 Format of the hours counter.
MSB
LSB
3
2
a
_
_
l~_ _
u~.
Memory location 05 (year/date)
reset state: 0000 000 1
Unit days BCD
Ten days (0 to 3 binary)
Year (0 to 3 binary, read as
the mask flag is set)
a if
Fig.6 Format of the year/date counter.
MSB
7
LSB
6
5
4
LI I I
Memory location 06 (weekdays/
months)
reset state: 0000 000 1
Unit months BCD
Ten months
Weekdays (0 to 6 binary, read as
if the mask flag is set)
Fig.7 Format of the weekdays/months counter.
496
February
19891 (
a
PCF8583
Clock calendar with 256 x a-bit static RAM
Table 1 Cycle length of the time counters, clock modes
unit
W
o
1(
February 1989
497
PCF8583
l__~__
Alarm control register
When the alarm enable bit of the control/status register is set the alarm control register (address 08) is
activated. All alarm, timer and interrupt output functions are controlled by the contents of the alarm
control register (see Figs 8a and 8b).
MSB
LSB
Memory location 08
reset state: 0000 0000
Timer function:
000 no timer
001 hundredths of a second
010 seconds
all minutes
100 hours
101 days
110 not used
111 test mode, all counters
in parallel
Timer interrupt enable:
a timer flag, no interrupt
1 timer flag, interrupt
Clock alarm function:
L_
00
01
10
11
no clock alarm
daily alarm
weekday alarm
dated alarm
Timer alarm enable:
a
no timer alarm
1 timer alarm
Alarm interrupt enable:
(Valid only when "alarm enable" in
control/status register is set)
a alarm flag, no interrupt
1 alarm flag, interrupt
F ig.8a Alarm control register, clock modes.
498
February 19891 (
l__
Clock calendar with 256 x 8-bit static RAM
P_C_F_8_5_83
_ __
MSB
7
LSB
6
4
5
3
2
I
a
LL'--1---
Memory location 08
reset state: 0000 0000
Timer function:
000
001
010
011
100
101
110
111
no timer
units
100
10 000
1 000 000
not allowed
not allowed
test mode, all counters in
parallel
Timer interrupt enable:
a timer flag, no interrupt
1 timer flag, interrupt
Event alarm function:
«I«
C
IZ
w
~
a..
o
...J
W
>
W
C
00
01
10
11
I
L=
no event alarm
event alarm
not en lowed
not allowed
Timer alarm enable:
a
no timer alarm
1 timer alarm
----------------------------
Alarm interrupt enable:
a alarm flag, no interrupt
1 alarm flag, interrupt
F ig.8b Alarm control register, event-counter mode.
'1
(FebrUary 1989
499
___
PCF_858_3_Jl_______________
Alarm registers
All alarm registers are allocated with a constant address offset of hex 08 to the corresponding counter
registers.
An alarm goes off when the contents of the alarm registers matches bit-by-bit the contents of the
involved counter registers. The year and weekday bits are ignored in a dated alarm. A daily alarm
ignores the month and date bits. When a weekday alarm is selected, the contents of the alarm
weekday/month register will select the weekdays on which an alarm is activated (see Fig.9).
Note: I n the 12 h mode bits 6 and 7 of the alarm hours register must be the same as the hours counter.
MSB
7
LSB
6
5
4
3
2
I
0
Memory location OE
(alarm weekday/month)
Weekday 0 enabled when set
Weekday 1 enabled when set
Weekday 2 enabled when set
Weekday 3 enabled when set
Weekday 4 enabled when set
Weekday 5 enabled when set
Weekday 6 enabled when set
not used
F ig.9 Selection of alarm weekdays.
I nterrupt output
The open-drain n-channel interrupt output is programmed by setting the alarm control register. It is
switched on (active LaW) when the alarm flag or the timer flag is set. I n the clock mode without
alarm the output sequence is controlled by the timer flag. The aFF voltage of the interrupt output
may exceed the supply voltage.
Oscillator and divider
A 32.768 kHz quartz crystal has to be connected to ascI (pin 1) and asca (pin 2). A trimmer
capacitor between ascI and VDD is used for tuning the oscillator (see quartz frequency adjustment).
A 100 Hz clock signal is derived from the quartz oscillator for the clock counters.
I n the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is
switched to a high impedance state. This allows the user to feed the 50 Hz reference frequency or an
external high speed event signal into the input ascI.
500
February
19891 (
~
PCF8583
Clock calendar with 256 x 8-bit static RAM
Initial izat ion
When power-up occurs the 12 C-bus interface, the control/status register and all clock counters are reset.
The device starts time keeping in the 32.768 kHz clock mode with the 24 h format on the first of
January at 0.00.00: 00. 1 Hz is output at the interrupt (starts HIGH). This can be disabled by setting
the alarm enable bit in the control/status register.
A second level-sensitive reset signal to the 12 C-bus interface is generated as soon as the supply voltage
drops below the interface reset level. This reset signal does not affect the control/status or clock
counter registers.
It is recommended to set the stop counting flag of the control/status register before loading the actual
time into the counters. loading of illegal states wi" lead to a clock malfunction but wi" not latch-up
the device.
CHARACTERISTICS OF THE 12C-BUS
The 12C-bus is for bidirectional, two-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (Sel). Both lines must be connected to a
positive supply via a 'pu"-up resistor. Data transfer may be initiated only when the bus is not busy.
Bit transfer
W
data line
stable:
data valid
C
change
of data
allowed
7ZB7019
F ig.1 0 Bit transfer.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-lOW transition of the
data line, while the clock is HIGH, is defined as the start condition (S). A lOW-to-HIGH transition of
the data line while the clock is HIGH, is defined as the stop condition (P).
gDA
---F\-1
I
I
SCL
L ___
____
........_ _ _ _ _+1-'·
I
:~--\
: s: \I-__..JI
:
r-ji---
~--~
'-.~I------'-----
.J
start condition
I
/
\1-._ _-...J
gDA
I
I
r:
SCL
:
L _ _ _ .J
stop condition
7ZB7005
Fig.11 Definition of start and stop condition.
1(
February 1989
501
___
PC_F85_83_Jl_______________
System configuration
A device generating a message is a "transmitter", a device receiving a message is the "receiver". The
device that controls the message is the "master" and the devices which are controlled by the master
are the "slaves".
SDA----------~------------_.---------------~------------4r------------~-SCl--~------~----_.------_+----~~------r_----~------_r----_.------~--
7Z87004
F ig.12 System configuration.
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is not limited. Each data byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HI G H level put on the bus by the transm itter whereas the master also generates an extra
acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an acknowledge after the reception of
each byte that has been clocked out of the slave transmitter. The device that acknowledge has to pull
down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HI G H period of the acknowledge related clock pu Ise. A master receiver must signal an end of data
to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a
stop condition.
start
condition
:
SCl FROM
MASTER
clock pu Ise for
acknowledgement
~
~~--~
~ /
X
)(~~)<
7
I
I
DATA OUTPUT
BY TRANSMITTER
I
S
DATA OUTPUT
BY RECEIVER
7Z87007
Fig.13 Acknowledgement on the 12 C-bus.
502
February
19891 (
~
PCF8583
Clock calendar with 256 x 8-bit static RAM
Timing specifications
All the timing values are valid within the operating supply voltage and ambient temperature range and
refer to VI Land VIH with an input voltage swing of VSS to VOO.
parameter
symbol
SC L clock frequency
min.
typo
max.
unit
fSCL
-
kHz
tsw
-
-
100
Tolerable spike width on bus
100
ns
Bus free time
tBUF
4.7
-
JlS
tsu; STA
4.7
-
tHO; STA
4.0
-
SCL LOW time
tLOW
4.7
-
SCL HIGH time
tHIGH
4.0
-
-
SCL and SOA rise time
tr
-
-
1.0
JlS
SCL and SOA fall time
tf
-
-
0.3
JlS
Oata set-up time
tsu; OAT
250
-
ns
-
-
Start condition set-up time
Start condition hold time
Oata hold time
JlS
JlS
JlS
JlS
ns
tHO; OAT
0
«
SCL LOW to data out valid
tvo; OAT
-
-
3.4
JlS
W
o
I nput leakage current
= 0.4 V
+ 0.8
SCL;SDA
'nput capacitance
Output INT
Output current LOW
VOL
10L
3
-
-
mA
Leakage cu rrent
V,
IILI
-
-
1
Il A
VOOR
1
-
6
V
100R
-
-
5
Il A
100R
-
-
2
f.1A
LOW VDD data
retention
Supply voltage for
data retention
Supply current
--
note 3
VOOR = 1 V
Tamb = -25 to
+ 70 oC;
VODR = 1 V
'1
(FebrUary 1989
505
~
___PC_FB_5B_3_Jl_________________
parameter
conditions
symbol
min.
typo
max.
unit
COSC
-
40
-
pF
Tamb = 25 oC;
VDO = 1.5 V
f/fOSC
-
2 x 10- 7
-
note 4
f·I
-
-
1
MHz
Series resistance
RS
-
-
40
kQ
Parallel capacitance
CL
-
10
-
pF
CT
5
-
25
pF
Oscillator
Integrated oscillator
capacitance
Oscillator stability
for llVOO = 100 mV
I nput frequency
Quartz crystal
parameters
Frequency = 32.768 kHz
Trimmer capacitance
Notes to the characteristics
1. The power-on reset circuit resets the 12 C-bus logic'when VOO
< VPOR.
2. When the voltages are a diode voltage above or below the supply voltage VOO or VSS an input
current will flow; this current must not exceed ± 0.5 mAo
3. Event or 50 Hz mode only (no Quartz).
4. Event mode only.
APPLICATION INFORMATION
Quartz frequency adjustment
Method 1: Fixed
ascI capacitor
By evaluating the average capacitance necessary for the' application layout a fixed capacitor can be
used. The frequency is best measured via the 1 Hz signa,l available after power-on at the interrupt
output (pin 7). The frequency tolerance depends on the quartz crystal tolerance, the capacitor
tolerance and the device-to-device tolerance (on average';± 5 x 10- 6 ). Average deviations of
± 5 minutes per year can be achieved.
Method 2:
ascI Trimmer
Using the alarm function (via the 12 C-bus) a signal faster than 1 Hz can be generated at the interrupt
output for fast setting of a trimmer.
Procedure:
Power-on
Initialization (alarm function)
Routine:
Set clock to time T and set alarm to time T + dT.
At time T + dT (interrupt) repeat routine.
If time dT is approximately 10 ms a frequency of approximately 40 Hz is obtained.
506
February 1989] (
___________C_IO_c_k_c_a_le_nd_a_r_w_it_h_2_5_6_X_8_-_b_it_s_t_a_ti_c_R_A_M____________________
-'~ ~
P
__C_F__8_5_8__3_________
_____
APPLICATION INFORMATION (continued)
The PCF8583 slave address has a fixed combination 1010 as group 1.
I I I I I I I I IVY I
1
0
1__
1
0
group 1
0
_1_
0
AO
group 2
_I
R
7Z96106
F ig.16 PCF8583 address.
Voo
o
AO
Voo
CLOCK CALENDAR SCL
PCF8583
ascI
'1010'
SOA
asca
w
SCL
SOA
asca
vSS
CI
to voo
voo
~
voo
voo
Voo
VOO
AO
Al
A2
256 BYTE RAM
PCF8570
'1010'
SCL
R
R:pull-up resistor
R
SOA
R
= trise
CBUS
SOA SCL
(1 2 C- bus)
lZ81194.2
Recommendation:
Connect a 4.7 fJ.F 10 V solid aluminium (SAL) capacitor between VDD and VSS.
Fig.17 PCF8583 application diagram.
') (
February 1989
507
___
PCF_858_3_Jl________________
7Z22749
12
/
J
8
v
V
-/
v
4
./
o
o
4
V
DD
(V)
6
Fig.18 Typical supply current as a function of supply voltage (clock);
= -40 to + 85 °C.
T amb
Purchase of Philips' 12 C components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system
provided the system conforms to the 12 C specifications defined
by Philips.
508
February
19891 (
l____
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
P_C_F_8_59_1______
8-BIT AID AND DIA CONVERTER
GENERAL DESCRIPTION
The PCF8591 is a single chip, single supply low power 8-bit CMOS data acquisition device with four
analogue inputs, one analogue output and a serial 12 C bus interface. Three address pins AD, A 1 and. A2
are used for programming the hardware address, allowing the use of up to eight devices connected to
the 12 C bus without additional hardware. Address, control and data to and from the device are
transferred serially via the two-line bidirectional bus (l 2 C).
The functions of the device include analogue input multiplexing, on-chip track and hold function,
8-bit analogue-to-digital conversion and an 8-bit digital-to-analogue conversion. The maximum conversion
rate is given by the maximum speed of the 12 C bus.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Single power supply
Operating supply voltage 2,5 V to 6 V
Low standby current
Serial inputloutput via 12 C bus
Address by 3 hardware address pins
Sampl ing rate given by 12 C bus speed
4 analogue inputs programmable as single-ended or differential inputs
Auto-incremented channel selection
Analogue voltage range from VSS to VDO
On-chip track and hold circuit
8-bit successive approximation AID conversion
Multiplying OAC with one analogue output
APPLICATIONS
Closed loop control systems; low power converter for remote data acquisition; battery operated
equipment; acquisition of analogue values in automotive, audio and TV applications.
PACKAGE OUTLINES
PCF8591 P: 16-lead 01 L; plastic (SOT38).
PCF8591T:16-lead mini-pack; plastic (S016L; SOT162A).
1
(AUgUst 1986
509
....U1
o
"1J
(')
."
»
c:
SCl
c:
C/)
SDA ---+
AO
A1
A2
---+
---+
---+
00
J\
01
2-....
co
.......
"
2
1 C BUS
INTERFACE
STATUS
REGISTER
DAC DATA
REGISTER
.
~
ADC DATA
REGISTER
",/
).
EXT
---t
VD D
--.
POWER ON
RESET
CONTROL
lOGIC
VSS
-----
OSCilLATOR
....V'7
--.
OSC
A!NO
AIN1
---.
-+
AIN3 -+
AIN2
AOUT
....~?
--.
ANALOGUE
MUlTIPlEXER
<,.
S/H
~~
COMPARATOR
SUCCESSIVE APPROXIMATION
REGISTER/lOGIC
,-+-
11111111
~ VREF
S/H
I~
DAC
~ AGND
7Z80971
Fig. 1 Block diagram.
J
8-bit A/D and 0/ A converter
PCF8591
~--
PINNING
1.
2.
3.
4.
5.
6.
7.
8.
9.
~:~~
AIN2
AIN3
AO
Al
A2
I
VSS
SDA
10. SCL
lL OSC
12. EXT
13. AGND
14. VREF
15. AOUT
16 VDD
lZ80959.1
Fig. 2 Pinning diagram.
I
f
analogue inputs
(A/D converter)
hardware address
negative supply voltage
12 C bus data input/output
12 C bus clock input/output
oscillator input/output
external/internal switch for oscillator input
analogue ground
voltage reference input
analogue output (D/ A converter)
positive supply voltage
FUNCTIONAL DESCRIPTION
«
«
o
I-
I2
w
~
a..
o
..J
Adressing
Each PCF8591 device in an 12 C bus system is activated by sending a valid address to the device. The
address consists of a fixed part and a programmable part. The programmable part must be set according
to the address pins AO, A 1 and A2. The address always has to be sent as the first byte after the start
condition in the 12 C bus protocol. The last bit of the address byte is the read/write-bit which sets the
direction of the following data transfer (see Figs 3 and 10).
W
>
W
o
MSB
I1
LSB
I
0
I0
fixed part
11
I A21 A1 I AD IR/wl
programmable part
7Z80960
Fig. 3 Address byte.
Control byte
The second byte sent to a PCF8591 device will be stored in its control register and is required to
control the device function.
The upper nibble of the control register is used for enabling the analogue output, and for programming
the analogue inputs as single-ended or differential inputs. The lower nibble selects one of the analogue
input channels defined by the upper nibble (see Fig. 4). If the auto-increment flag is set the channel
number is incremented automatically after each A/D conversion.
The selection of a non-existing input channel results in the highest available channel number being
allocated. Therefore, if the auto-increment flag is set, the next selected channel will be always channel O.
The most significant bits of both nibbles are reserved for future functions and have to be set to O.
After a power-on reset condition all bits of the control register are reset to O. The Of A converter and
the oscillator are disabled for power saving. The analogue output is switched to a high impedal'"!ce state.
I (AUgUst
1986
511
__PC_F85_91_Jl_ _ _ _ _ _ _ __
LSB
MSB
x
x
o
x
x
CONTROL BYTE
I'
I '
AID CHANNEL NUMBER
00
channel 0
01
channel 1
10
channel 2
11
channel 3
AUTOINCREMENT FLAG:
(switched on if 1)
ANALOGUE INPUT PROGRAMMING:
00
01
Four single ended inputs
AI NO - - - - - - AIN1
AIN2
AIN3
0
1
2
3
Three differential inputs
AINO
AIN1
AIN2
AIN3
10
channel
channel
channel
channel
~+
channel 0
~
channel 1
+
channel 2
-
Single ended and differential mixed
AINO
AIN1
channel 0
channel 1
AIN2=
+ 1 > - channel 2
AIN3 -
11
Two differential inputs
AIN0=
+ 1 > - channel 0
AIN1
AIN2=
~ 1 > - channel 1
AIN3
L..--_ _ _
ANALOGUE OUTPUT ENABLE FLAG:
(analogue output active if 1)
Fig. 4 Control byte.
512
August
19861 (
7Z80961
l
!
I
l
I
I
~~
________
8-b_it_A_/o_a_nd_O_/A_c_on_ve_rt_er_____________________
P_C_F_8_5_9_1______
_ ___
01 A conversion
The third byte sent to a PCF8591 device is stored in the DAC data register and is converted to the
corresponding analogue voltage using the on-chip 01 A converter. This 01 A converter consists of a
resistor divider chain connected to the external reference voltage with 256 taps and selection switches.
The tap-decoder switches one of these taps to the DAC output line (see Fig. 5).
The analogue output voltage is buffered by an auto-zeroed unity gain amplifier. This buffer amplifier
may be switched on or off by setting the analogue output enable flag of the control register. In the
active state the output voltage is held until a further data byte is sent.
The on-chip 01 A converter is also used for successive approximation AID conversion. In order to
release the DAC for an AID conversion cycle the unity gain amplifier is equipped with a track and
hold circuit. This circuit holds the output voltage while executing the AID conversion.
The output voltage supplied to the analogue output AOUT is given by the formula shown in Fig. 6.
The waveforms of a 01 A conversion sequence are shown in Fig. 7.
DAC OUT
VREF
«
«C
I-
FF
I2
w
~
Q.,
0
+--07
..J
W
06
>
w
TAP
DECODER
C
02
DO
01
AGND
00
7280962
Fig.5 DAC resistor divider chain.
"I (AUgUst
1986
513
__PC_F85_91_jl_ _ _ _ _ _ _ __
MSB
I
07
1
06
1
05
LSB
DAC data
03 02
04
1
1
1
1 01 I DO I register
VAOUT
= VAGND +
7Z80963
VREF - VAGND 7 ,
i
256
Dr x 2
r=O
,I
--------------------------------."
..,/ .........
.,/
..
.,/
........-
"
..,/
........-
VAGND
- .........
.........
.........
.,/
I
VSS+--0+0--O~1-402~0+3--0+4----------------F+E--F~F--H-EX~CODE
Fig. 6 DAC data and d.c. conversion characteristics.
CONTROL BYTE
A
DATA BYTE 1
J\J.\Jl
PREVIOUS VALUE
HELD IN DAC
REGISTER
Fig. 7 D/A conversion sequence.
August
VALUE OF
DATA BYTE 1
time
7Z80964
514
A
I
nnn
U1U2L -.JaUeU1L
SCL,nn
HIGH IMPEDANCE STATE OR
PREVIOUS VALUE HELD IN DAC REGISTER
DATA BYTE 2
A
1986\ (
,J~____
P_C_F_8_5_9_1______
________
8-_bi_tA_I_D_an_d_D/_A_co_nv_er_te_r_____________________
AID conversion
The AID converter makes use of the successive approximation conversion technique. The on-chip DI A
converter and a high gain comparator are used temporarily during an AID conversion cycle.
An AID conversion cycle is always started after sending a valid read mode address to a PCF8591 device.
The AID conversion cycle is triggered at the trailing edge of the acknowledge clock pulse and is
executed while transmitting the result of the previous conversion (see Fig. 8).
Once a conversion cycle is triggered an input voltage sample of the selected channel is stored on the
chip and is converted to the corresponding 8-bit binary code. Samples picked up from differential
inputs are converted to an 8-bit two's complement code (see Fig. 9). The conversion resu It is stored
in the ADC data register and awaits transmission. If the auto-increment flag is set the next channel is
selected.
The first byte transmitted in a read cycle contains the conversion result code of the previous read cycle.
A fter a power-on reset cond ition the first byte read is a hexadeci mal 80. The protocol of an 12 C bus
read cycle is shown in Fig. 10.
The maximum AID conversion rate is given by the actual speed of the 12 C bus.
DATA BYTE 0
«
le:(
o
I:2
w
DATA BYTE 1
A
DATA BYTE 2
SCL,nn
nnn
U1U2L ..JSU9U1L
~
0..
o
.....I
A
SDA
A
JVl
1
W
>
7Z80965
W
C
LSAMPLING
LSAMPLING
BYTE 1
BYTE 2
CONVERSION
OF BYTE 1
CONVERSION
OF BYTE 2
CONVERSION
OF BYTE 3
TRANSMISSION
OF PREVIOUSLY
CONVERTED BYTE
TRANSMISSION
OF BYTE 1
TRANSMISSION
OF BYTE 2
Fig. 8 AID conversion sequence.
1(AUgust
1986
515
__PC_F85_91_jl_ _ _ _ _ _ _ __
HEX
7Z80966
CODE
FF
FE
254
255
VAIN - VAGND
VLSB
Fig. 9a AID conversion characteristics of single-ended inputs.
HEX
CODE
7Z80967
7F
7E
02
-128 -127 --- -2
-1
2
--- 126
127
FE
,
~-"----------.+::
VLSB
=
VREF - VAGND
256
Fig. 9b AID conversion characteristics of differential inputs.
516
August
19861 (
~~
________8_-b_it_A_fD
__
an_d_D_fA_c_on_v_er_te_r_______________________
_____P_C_F_8_5_9_1______
Reference voltage
For the Df A and A/D conversion either a stable external voltage reference or the supply voltage has to
be applied to the resistor divider chain (pins VREF and AGND). The AGND pin has to be connected
to the system analogue ground and may have a d.c. off-set with reference to VSS.
A low frequency may be applied to the VREF and AGND pins. This allows the use of the D/A converter as a one-quadrant multiplier; see Application Information and Fig. 6.
The A/D converter may also be used as a one or two quadrant analogue divider. The analogue input
voltage is divided by the reference voltage. The result is converted to a binary code. In this appiication
the user has to keep the reference voltage stable during the conversion cycle.
Oscillator
An on-chip oscillator generates the clock signal required for the A/D conversion cycle and for refreshing
the auto-zeroed buffer amplifier. When using this oscillator the EXT pin has to be connected to VSS.
At the OSC pin the oscillator frequency is available.
If the EXT pin is connected to VDD the oscillator output OSC is switched to a high impedance state
allowing the user to feed an external clock signal to OSC.
Bus protocol
W
C
I (AUgUst
1986
517
~
_ _PC_F85_91_Jl_ _ _ _ _ _ _ _-'
Acknowledge
from PCF8591
Acknowledge
from PCF8591
i
t
ADDRESS
S
A
0
Acknowledge
from PCF8591
A
CONTROL BYTE
t
DATA BYTE
A
N=O to M
DATA BYTES
P,S
7Z80968
Fig. lOa Bus protocol for write mode, DIA conversion.
Acknowledge
from PCF8591
I
S
I
ADDRESS
1
I
Acknowledge
from master
t
A
DATA BYTE
I
No acknowledge
~
A
LAST DATA BYTE
I
1
7Z80969
N=O to M
DATA BYTES
Fig. lOb Bus protocol for read mode, AID conversion.
518
August 19861 (
,J~_____
P_C_F_8_5_9_1_______
_________
S-_bi_tA_I_D_an_d_D_/A_c_o_nv_er_te_r_______________________
CHARACTERICS OF THE 12 C BUS
The 12 C bus is for bidirectional, two-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a
positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transfered during each clock pulse. The data on the SDA line must remain stable during
the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a
control signal.
SDA
--I---IX. . .__-- -~
------+-_ _ _ _ _
---~
SCL
data line
stable:
data valid
<2:
<2:
Z
w
:E
Q.
o
-I
w
>
w
7Z87019
Fig. 11 Bit transfer.
IC
I-
change
of data
allowed
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the
data line, while the clock is HIGH, is defined as the start condition (S). A LOW-to-HIGH transition of
the data line while the clock is HIGH, is defined as the stop condition (P).
C
SOA
----t\'-~-fI----L.C
___ -=~
iit-----"""-------+-1-' :
I
SCL
: s:
:
L ___
SOA
I
:
\
-l
start condition
.
!
r---\
\\-.__~/
I
I
::
L___ J
stop condition
SCL
7Z87005
Fig. 12 Definition of start and stop condition.
I
(AUgUst 1986
519
__PC_F85_91_jl_ _ _ _ _ _ __
System configuration
A device generating a message is a "transmitter", a device receiving a message is the "receiver'·. The
device that controls the message is the "master" and the devices which are controlled by the master
are the "slaves".
SCL--~------~-----+------_+----~~------~----~------4_----~------_+--
Fig. 13 System configuration.
Acknowledge.
The number of data bytes transfered between the start and stop conditions from transmitter to
receiver is not limited. Each data byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HI G H level put on the bus by the transmitter whereas the master also generates an extra
acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an acknowledge after the reception of
each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull
down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the
HIGH period of the acknowledge related clock pulse. A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a
stop condition.
start
condition
I
clock pulse for
acknowledgement
I
+
SCL FROM
MASTER
I
I
I
I
I
DATA OUTPUT
BY TRANSMITTER
--~
~'---"'-[-----Jx~_K ~ ~~"'-----oJ7
I
S
DATA OUTPUT
BY RECEIVER
--~
7Z87007
Fig. 14 Acknowledgement on the
520
August
19861 (
1
2
C bus.
____
~l
________
8-_bi_tA_/D_a_nd_D_/A_c_on_ve_rt_er____________________
P_C_F_8_5_9_1____
Timing specifications
All the timing values are valid within the operating supply voltage and ambient temperature range and
refer to VI Land VIH with an input voltage swing of VSS to VOO.
parameter
symbol
SCL clock frequency
min.
typo
max.
unit
-
100
kHz
fSCL
-
Tolerable spike width on bus
tsw
-
Bus free time
tBUF
4,0
Start condition set-up time
ns
fJ.S
tsu; STA
4,0
-
fJ..s
Start condition hold time
tHO; STA
4,7
fJ.S
SCL LOW time
tLOW
4,7
SCL HIGH time
tHIGH
4,0
SC Land SOA rise time
tR
SCL and SOA fall time
tF
-
-
Data set-up time
tsu; OAT
250
-
ns
tHO; OAT
0
ns
-
«
SCL LOW to data out valid
tVD; OAT
-
-
Q
Stop condition set-up time
tsu; STO
4,0
-
Data hold time
~
100
fJ.S
fJ.S
I
1,0
fJ.S
a,3
fJ.S
3,4
--
I2
w
~
a...
o
..J
W
>
w
PROTOCOL
Q
SCL
SOA
lZB1193.1
tHO;STA
tSU;OAT
Fig.15
2
1
tHO; OAT
tVO;OAT
tSU;STO
C bus timing diagram.
"I (AUgUst
1986
521
~
___PC_F85_91_Jl_________________
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage range
-0,5 to +8,0 V
Voltage on any pin
VOO
V,
Input current d .c.
II
max.
Output current d.c.
'0
100,ISS
max.
20 rnA
max.
50 rnA
Ptot
P
max.
300 mW
Power dissipation per output
max.
100 mW
Storage temperature range
Tstg
Operating ambient
temperature range
Tamb
VOO or VSS current
Power dissipation per package
-0,5 to VOO +0,5 V
10 rnA
-65 to +150 oC
-40 to +85 oC
Note:
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be
totally safe, it is advised to take handling precautions appropriate to handling MOS devices (see
'Handling MOS devices').
CHARACTERISTICS
=0
VOO = 2,5 V to 6 V; VSS
parameter
V; Tamb
= -40 oC to +85 oC
unless otherwise specified
conditions
symbol
Supply voltage
operating
VOO
2,5
Supply current
standby
V, = VSS or VOO;
no load
1000
-
Supply current
operating; AOUT off;
fSCl = 100 kHz
1001
Supply current
AOUT active;
fSCl = 100 kHz
Power-on reset level
note 1
Digital inputs/output
SCl, SOA, AO, A 1, A2
Input voltage
lOW
Input voltage
HIGH
Input current
leakage;
V, = VSS to VOO
typo
min.
unit
max.
Supply
Input capacitance
522
-
6,0
V
1
15
J.l.A
-
125
250
J.l.A
1002
-
0,45
1,0
mA
VPOR
0,8
-
2,0
V
V,l
0
-
0,3 x VOO
V
V,H
0,7 x VOO
-
VOO
V
II
-
nA
-
-
250
C,
5
pF
SOA output current
leakage;
HIGH at VOH =VOO
10H
-
-
250
nA
SOA output current
lOW at VOL
= 0,4 V
10l
3,0
-
-
rnA
August
19861 (
~
~~
_____
P_C_F_8_5_9_1_______
_______
8-_bi_tA_/_D_an_d_D_/A_c_o_nv_er_te_r_______________________
parameter
conditions
symbol
Reference voltage inputs
VREF, AGND
Voltage range
reference
VREF
Voltage range
analogue ground
VAGND
I nput current
leakage
I nput resistance
VREF to AGND
Oscillator
OSC,EXT
I nput current
leakage
Oscillator frequency
min.
typo
max.
unit
VAGND
-
VDD
V
VSS
-
II
-
-
VREF
250
nA
RREF
-
100
II
fOSC
-
V
kil
-
-
250
nA
0,75
-
1,25
MHz
D/A CHARACTERISTICS
VOO = 5,0 V; VSS = 0 V; VREF = 5,0 V; VAGNO = 0 V; Rload
T amb = -40 oC to +85 oC unless otherwise specified
parameter
«
<
C
IZ
w
::2!:
conditions
symbol
min.
typo
Output voltage range
no resistive load
VOA
VSS
Output voltage range
Rload
VOA
Output current
leakage;
AOUT disabled
Q..
W
max.
unit
-
VOO
V
VSS
-
O, 9xV OD
V
ILO
-
-
250
nA
OSe
-
-
50
mV
Le
-
-
±',5
Analogue output
o-J
>
Accuracy
C
Offset error
W
= 10 kil; Cload = 100 pF;
Tamb
= 10 kil
= 25 oC
Linearity error
,
Gain error
no resistive load
Ge
-
-
Settling time
to % LSB full
scale step
tOAC
-
-
90
fOAC
-
-
11,1
SNRR
-
40
Conversion rate
Supply noise rejection
at f = 100 Hz;
VOO = 0,1 Vpp
-
'I (AUgust
LSB
%
J,lS
kHz
dB
1986
523
___
PC_F85_91_jl_________________
AID CHARACTERISTICS
VDD = 5,0 V; VSS = 0 V; VREF = 5,0 V; VAGND = 0 V; Rsource = 10 kS1; Tamb = -40 oC to +85 OC
unless otherwise specified
conditions
parameter
symbol
min.
typo
max.
unit
VIA
VSS
-
VDD
V
IIA
-
-
100
nA
CIA
-
10
-
pF
CID
-
-
pF
Analogue inputs
I nput voltage range
leakage
I nput current
I nput capacitance
I nput capacitance
differential
Single-ended voltage
measuring range
VIS
Differential voltage
measuring range;
VFS = VREF
-VAGND
VID
Tamb = 25 OC
OSe
VAGND
-VFS
10
-
-
2
VREF
+VFS
2
V
V
Accuracy
Offset error
Linearity error
-
-
20
mV
Le
-
-
±1,5
LSB
Ge
-
-
1
%
small-signal;
.1VIN = 16 LSB
GS e
-
5
%
Rejection ratio
common-mode
CMRR
-
60
-
dB
Supply noise rejection
at f = 100 Hz;
VDDN = 0,1 xVpp
SNRR
-
40
-
dB
tADC
-
-
90
J1S
fADC
-
-
11,1
Gain error
Gain error
Conversion ti me
Sampling/conversion rate
Note
1. The power on reset circuit resets the 12C bus logic when VDD is less than VPOR.
Purchase of Philips' 12 C components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system
provided the system conforms to the 12 C specifications defined
by Philips.
524
August
19861 (
kHz
~~
_____P_C_F_8_5_9_1_______
_________B_-b_it_A_/D_a_"d_D_I_A_CO_"_ve_rt_er_______________________
7Z94726
200
7Z94727
160
100
(pA)
100
(pA)
150
100
.-"
V
V
V
V
v
V
~
120
~
-40~
80
40
50
~
V
V
~~
~V
~850C
+ 27 0 C
o
o
2
5
4
3
6
2
3
5
4
Voo (V)
(a) internal oscillator; T amb
6
Voo (V)
= + 27 oC.
(b) external oscillator.
Fig. 16 Operating supply current against supply voltage (analogue output disabled).
e:(
le:(
C
I-
Z
W
:!:
Q"
0
..J
a
i
W
.S
>
C
7Z94729
500
§
2lc:
w
7Z94728
500
400
c.
g
~
\
:::l
~ 300
0
«
"0
\
i
c.
.S
...
~
V
o
«
"0
\
100
02
/
200
I
"-
""""'" t--.. "'-
o
00
I
:::l
~ 300
\
200
400
04
06
100
t-- r-08
OA
o
~
BO
-I---
CO
-
I-- V
DO
FO
EO
FF
hex input code
hex input code
(a) output impedance near negative power rail;
Tamb = + 27 oc.
V
(b) output impedance near positive power rail;
Tamb = + 27 oc.
Fig. 17 Output impedance of analogue output buffer (near power rails).
The x-axis represents the hex input-code equivalent of the output voltage.
'] (
August 1986
525
_Jl_________
__
PC_F85_91
APPLICATION INFORMATION
Inputs must be connected to Vss or VDD when not in use. Analogue inputs may also be connected to
AGND or VREF.
I n order to prevent excessive ground and supply noise and to minimize cross-talk of the digital to
analogue signal paths the user has to design the printed-circuit board layout very carefully. Supply
lines common to a PCF8591 device and noisy digital circuits and ground loops should be avoided.
Decoupling capacitors (> 10 J,tF) are recommended for power supply and reference voltage inputs.
VDD
VDO
+H
AIND
VD D
AOUT
AIN1
VREF
AIN2
AGND
EXT
AIN3
AD
PCF8591
OSC
A1
SCL
A2
SDA
VSS
VDD
AIND
VD D
AOUT
AIN1
VREF
AIN2
AGND
AIN3
AD
VOUT
EXT
PCF8591
OSC
A1
SCL
A2
SDA
VSS
VDD
,,1 ANALOGUE GROUND
.1 DIGITAL GROUND
MASTER
TRANSMITTER
lZ80970.1
Fig. 18 Application diagram.
526
August 1986] (
l___
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
P_N_A_75_0_9_ __
7-81T ANALOGUE-TO-DIGITAL CONVERTER (ADC 7)
GENERAL DESCRIPTION
The PNA7509 is a monolithic NMOS 7-bit analogue-to-digital converter (AOC) designed for video
applications. The device converts the analogue input signal into 7 -bit binary coded digital words at a
sampling rate of 22 MHz.
The circuit comprises 129 comparators, a reference resistor chain, combining logic, transcoder stages,
and TTL output buffers which are positive edge triggered and can be switched into 3-state mode. The
digital output is selectable in two's complement or binary coding.
The use of separate outputs for overflow and underflow detection facilitates full-scale driving.
Features
Applications
•
•
•
•
•
•
•
•
•
•
•
•
7 -bit resol ution
No external sample and hold required
High input impedance
Binary or two's complement 3-state TTL outputs
Overflow and underflow 3-state TTL outputs
All outputs positive-edge triggered
Standard 24-pin package
High-speed AID conversion
Video signal digitizing
Radar pulse analysis
Transient signal analysis
High energy physics research
QUICK REFERENCE DATA
Measured over full voltage and temperature range unless otherwise specified
parameter
conditions
Supply voltage (pins 3,12,23)
Supply voltage (pin 24)
min.
typo
max.
unitl
V005
4,5
-
5,5
V
10,5
V
65
mA
symbol
V0010
9,5
Supply current (pins 3, 12,23)
note 1
1005
Supply current (pin 24)
note 1
10010
-
-
13
mA
Reference current (pins 4,20)
I ref
150
-
450
IlA
Reference voltage LOW (pin 20)
VrefL
2,4
2,5
2,6
V
Reference voltage HIGH (pin 4)
VrefH
5,0
5,1
5,2
V
INL
ONL
-
11
±lk
±lk
-
LSB
LSB
B
-
MHz
22
MHz
500
mW
Non-linearity
integral
differential
fi
= 1,1
-3 dB Bandwidth
Clock. frequency (pin 14)
Total power dissipation
note 1
kHz
fCLK
1
Ptot
-
Note to quick reference data
1. Measured under nominal conditions: V005
= 5 V; V0010 = 10 V; Tamb = 22 DC.
PACKAGE OUTLINES
24-lead 01 L; plastic (SOT101A).
'I (une
1987
527
___PN_A75_09_Jl________________
reference
voltage
HIGH
(VrefH)
clock input
(f
CLK )
select
two's complement
(STC)
CEl
CE2
4
overflow
7
MSB
bit 6
bit 5
9
ROM
OUTPUT
127 x 7
LATCHES
bit 4
10
bit 3
11
bit 2
15
bit 1
16 LSB
17
20
reference
voltage
LOW
(V
refL )
13
analogue
voltage
input
bit 0
underflow
7Z93495.1
ground
(VI)
Note
All three pins 3, 12 and 23 must be connected to positive supply voltage + 5 V.
Fig. 1 Block diagram.
528
June
1989"1 ~
digital voltage
outputs (Va)
l____
7-bit analogue-to-digital converter (ADe 7)
P_N_A_75_0_9______
PINNING
VI
analogue voltage input
vOOlO
2
AGND
analogue ground
VOO5
3
VDD5
positive supply voltage (+ 5 V)
4
VrefH
STC
select two's complement
6
OVFL
overflow
7
bit 6
most-significant bit (MSB)
8
bit 5
n.e.
CE2
v refL
VBB
CEl
UNFL
bit 0
bit 3
5
9
bit 4
10
bit 3
11
bit 2
12
VDD5
DGND
bit 1
13
vOO5
fCLK
14
DGND
15
fCLK
bit 1
w
0
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
+7 V
Supply voltage range (pins 3, 12, 23)
VDD5
-0,5 to
Supply voltage range (pin 24)
VDD10
-0,5 to + 12 V
I nput voltage range
VI
-0,5 to + 7 V
Output current
10
Total power dissipation
Storage temperature range
Ptot
T stg
Operating ambient temperature range
Tamb
5 mA
1W
-65 to + 150 0C
o to
+ 70 0C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MaS devices (see
"Handling MaS Devices").
"] (June
1987
529
___
PN_A75_09_Jl________________
CHARACTERISTICS
VDD5 = V3 12 23-13 = 4,5 to 5,5 V; VDD10 = V24-2 = 9,5 to 10,5 V; CBB = 100 nF;
T amb = 0
+ io °C
to
parameter
symbol
min.
typo
max.
unit
VDD5
4,5
-
5,5
V
VDD10
9,5
-
10,5
V
Supply
Supply voltage (pins 3, 12, 23)
Supply voltage (pin 24)
Supply current (pins 3, 12,23)
IOD5
-
-
85
mA
Supply current (pin 24)
IDD10
-
-
18
mA
Reference voltage LOW (pin 20)
VrefL
2,4
2,5
2,6
V
Reference voltage HIGH (pin 4)
VrefH
5,0
5,1
5,2
V
Reference current
Iref
150
-
450
p.A
Reference voltages
Inputs
Clock input (pin 14)
I nput voltage LOW
VIL
-0,3
-
0,8
V
Input voltage HIGH (note 1)
VIH
3,0
-
V005
V
I nput voltage LOW
VIL
0
-
0,8
V
Input voltage HIGH
VIH
2,0
-
VDD5
V
I nput current
at V 5 = 0 V; V 13
-15
15
p.A
15
-
70
118
70
p.A
-121
15
-
120
p.A
III
-
-
10
p.A
Input voltage amplitude
(peak-to-peak value)
VI(p_p)
-
2,6
-
V
I nput capacitance (note 3)
C1-2
-
-
30
pF
Digital input levels(pins5,18,21; note 2)
= GN D
= 5 V; V 13 = G N D
at V 21 = 0 V; V 13 = GN D
at V 18
I nput leakage current
(except pins 5,18 and 21)
Analogue input levels (pin 1)
at VrefL = 2,5 V; VrefH = 5,1 V
Notes to characteristics
1. Maximum input voltage must not exceed 5,0 V.
2. I f pin 5 is LOW binary coding is selected.
If pin 5 is HIGH two's complement is selected.
If pin 5,18 and 21 are open-circuit, pin 5,21 are HIGH and pin 18 is LOW.
For output coding see Table 1 and mode selection see Table 2.
3. Tested on sample base.
530
June
19871 (
l____
7-bit analogue-to-digital converter (ADC 7)
P_N_A_7_50_9______
parameter
symbol
min.
max.
unit
VOL
0
+0,4
V
VOL
2,4
VOO5
V
Outputs
Digital voltage outputs
(pins 6 to 11 and 15 to 17)
Output voltage LOW
at 10 = 2 mA
Output voltage HIGH
at -10 = 0,5 mA
I
Table 1 Output coding (VrefL
step
= 2,50 V; VrefH = 5,08 V)
OVFL
<2,51
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
2,51
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
(1)
underflow
two's complement
bit 6 - bit 0
binary
bit 6 - bit 0
UNFL
Vl-2
0
1
2,53
0
0
0
0
0
0
0
0
1
1
0
0
overflow
W
C
Note to Table 1
1. Approximate values.
Table 2 Mode selection
CE 1
CE 2
bit 0 to bit 6
UNFL,OVFL
X
0
HIGH impedance
HIGH impedance
0
1
active
active
1
1
HIGH impedance
active
'I (June
1987
531
_Jl________
__
PNA_750_9
CHARACTERISTICS (continued)
VDD5 = V3 12 23-13 = 4,5 V to 5,5 V; VDD10 = V24-2 = 9,5 V to 10,5 V; VrefL = 2,5 V;
VrefH = 5,1'V; fCLK = 22 MHz; CBB = 100 nF; Tamb = 0 to + 70 oC
parameter
symbol
min.
max.
unit
Switching characteristics (see also Fig. 3)
Clock input (pin 14)
Clock frequency
fCLK
1
22
MHz.
Clock cycle time LOW
tLOW
20
ns
Clock cycle time HIGH
tHIGH
20
-
Input rise and fall times (pin 1)
rise time
tr
-
3
ns
tf
-
3
ns
fall time
ns
Analogue input (note 1)
Bandwidth (-3 dB)
B
11
-
MHz
Differential gain (note 2)
dG
-
±5
%
Differential phase (note 2)
dp
-
± 2,5
deg
Non-harmonic noise
-
-36
dB
Peak error (non-harmonic noise)(note 3)
-
3
LSB
-
0
dB
f2,3
-28
dB
f4-7
-
-35
dB
Harmonics (full scale)
fundamental (note 3)
r.m.S. (2nd + 3rd harmonic)
r.m.S. (4th + 5th + 6th + 7th harmonic)
532
1(
June 1989
fO
l____
7-bit analogue-to-digital converter (ADC 7)
P_N_A_7_50_9______
parameter
symbol
min.
max.
unit
Digital outputs (notes 1 and 4)
Output hold time
tHOLD
6
-
ns
= 15 pF
td
-
38
ns
Output delay time at CL = 50 pF
td
-
48
ns
3-state delay time
tdt
--
25
ns
Capacitive output load
COL
0
15
pF
INL
-
±%
LSB
±%
LSB
Output delay time at C L
Transfer function
Non-linearity at fi
integral
= 1,1
kHz
differential
DNL
Notes to timing characteristics
1. Clock input rise and fall times are at the maximum clock frequency (10% and 90% levels).
«
«C
IIZ
w
::i!:
c..
o
2.
Low frequency sinewave (peak-to-peak value of the analogue input voltage at VI (p_p) = 1,8 V)
combined with a sinewave voltage (Vl(p_p) = 0,7 V) at fi = 5 MHz.
3. Analogue frequency fi(A) = 5 MHz
Amplitude Vi(A) = 2.42 V (peak-to-peak value).
4. The timing values of the digital outputs at pins 6 to 11 and 15 to 17 are measured with the clock
input reference level at 1,5 V.
...J
W
>
W
C
1(June
1989
533
___
PNA_75_09_Jl_______________~
clock input
CLOCK INPUT
(pin 14)
- - I - - - - l - - - - - reference level
(1,5V)
ANALOGUE INPUT
(pin 1)
\4-----
3tCL~';"')----.1
tHOLD'"
..-
- - 2,aV
DIGITAL OUTPUTS
(pins 6 to 11 and 15 to 17)
- - a,BV
7Z80491.1
(1) There is a delay of 3 clock cycles between sampling of an analogue input signal and the corresponding
digital output.
Fig.3 Timing diagram.
534
June
19871 (
PNA7509
7-bit analogue-to-digital converter (ADC 7)
APPLICATION NOTE
The minimum and maximum values provided in the data sheet are guaranteed over the whole voltage
and temperature range. This note gives additional information to the data sheet where the typical
values indicate the behaviour under nominal conditions; V005 = 5 V, VOOlO = 10 V, Tamb = 22 °C.
parameter
symbol
typo
unit
Supply
Supply current (pins 3, 12, 23)
1005
51
mA
Supply current (pin 24)
10010
11
mA
Maximum clock frequency
fCLK
25
MHz
Bandwidth (-3 dB)
B
20
MHz
Ptot
365
mW
1,5
LSB
31
39
dB
dB
± 1/4
± 1/3
LSB
LSB
Total power dissipation
Peak error (non-harmonic noise)
e:(
le:(
o
I-
Suppression of harmonics
sum of:
f2nd + f3rd
f4th + f5th + f6th + f7th
Non-linearity
integral
differential
INL
ONL
Z
w
Differential gain
dG
±3
%
Q.
Differential phase
dP
±1
%
Large signal phase error
Pe
10
deg
40
dB
~
o
...J
W
>
W
Non-harmonic noise
C
Typical values are measured on sample base.
Application recommendation
Spikes at the 10 V supply input must be avoided (e. g. overshoots during switching).
Even a spike duration of less than 1 j1S can destroy the device.
1(June
1987
535
_Jl________
__
PN_A75_09
APPLICATION NOTE (continued)
Test philosophy
Fig.4 is a block diagram showing analogue-to-digital testing with a phase locked signal source. The
signal generator provides a 5 MHz sinewave for the device under test (except for the linearity test).
The 22 MHz clock input is provided by the clock generator. The phase relationship between signal and
clock generator is shifted by 100 pico sec. each signal period to provide an effective clock rate of 10 GHz
for analysis.
Most calculations are carried out in the spectral domain using Fast Fourier Transformation (FFT) and
the inverse F FT to return to time domain.
The successive processing completes the specific measurement (Fig. 5, 6, 7 and 8).
The non-linearities of the converter, integral (IN L) and differential (ON L), are measured using a low
frequency ramp signal. Within a general uncertain range of conversion between two steps the output
signal of the converter randomly switches.
After low-pass filtering the different step width is used for calculating the line of least squares to obtain
integral non-linearity.
To calculate differential non-linearity a counter is used to count the frequency of each step. A histogram
is calculated from the counter result to provide the basis for further computation (Fig. 7).
r-t-
CLOCK
GENERATOR
~
PULSE
FORMER
clock
input
(22 MHz)
I
phase
lock
~
SIGNAL
GENERATOR
DEVICE
UNDER
TEST
-----+
LOGIC
ANALYZER
analogue
input
7Z97665
Fig.4 Analogue-to-digital converter testing with locked signal source.
536
June
19871 (
l___
7-bit analogue-to-digital converter (ADC 7)
P_N_A_7_5_0_9______
stimulus; HF sinewave
HARMONICS
e::(
7Z97664
le::(
Q
I2
w
:E
Where:
FFT = Fast Fourier Transformation.
IF FT = I nverse Fast Fou rier Transformation.
Fig.5 Sinewave test; non-harmonic noise and peak error.
c..
o...J
stimulus;
LF sinewave
with HF added
W
>
w
Q
HF and SIDEBANDS
ROTATED and NORMALIZED
to
vectorscope
7Z97663
Fig. 6 Differential gain and phase.
1(
June 1987
537
___P_NA_750_9_Jl_________________
APPLICATION NOTE (continued)
stimulus; LF ramp
lZ91666
Where:
INL = Integral Non-Linearity.
DN L = Differential Non-Linearity.
Fig.7 Low frequency ramp test; linearity.
stimulus;
amplitude modulated
HF sinewave
HF and SIDEBANDS
ROTATED and NORMALIZED
to
vector scope
lZ96716
Fig. 8 Large signal phase error.
538
June
19871 (
l____
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
P_N_A_7_51_8______
8-BIT MULTIPLYING DAC
GENERAL DESCRIPTION
The PNA7518 is a NMOS 8-bit mUltiplying digital-to-analogue converter (OAC) designed for video
applications. The device converts a digital input signal into a voltage-equivalent analogue output at a
sampling rate of 30 MHz.
The input signal is latched, then fed to a decoder which switches a transfer gate array (1 out of 256) to
select the appropriate analogue signal from a resistor chain. Two external reference voltages supply the
resistor chain. The multiplying capability is obtained by using the independent reference voltages.
The input latches are positive-edge triggered. The output impedance is approximately 0,5 H2 depending
on the applied digital code. An additional operational amplifier is required forthe 75 output impedance.
Two's complement is selected when STC (pin 11) is HIGH or is not connected. STC inverts the most
significant bit (MSB).
n
Features
•
•
•
•
•
•
•
•
TTL input levels
Positive-edge triggered
Analogue voltage output at 30 MHz sampling rate
Binary or two's complement input
Output voltage accuracy to within ± ~ of the input LSB
Multiplying capability
12 M Hz bandwidth
8-bit resolution
QUICK REFERENCE DATA
parameter
conditions
symbol
min.
typo
max.
unit
VOO
4,5
-
5,5
V
Supply current
100
-
-
80
rnA
Reference voltage LOW
VrefL
0
Reference voltage HIGH
VrefH
0
Supply voltage range
Static non-linearity
note 1
Bandwidth at -3 dB
note 2
Clock frequency
T amb == 25 °C;
VOO == 5 V
Total power consumption
B
12
-
fCLK
P
10
-
30
MHz
-
-
470
mW
-
2,0
V
2,0
V
± 0,5
LSB
-
MHz
For explanation of notes see "Notes to the characteristics".
Applications
• Video data conversion
• CRT displays
• Waveform/test signal generation
• Colour/black-and-white graphics
PACKAGE OUTLINE
16-lead OIL; plastic (SOT380)
1(
May 1989
539
__
PNA7_518_Jl_ _ _ _ _ _------.
select
two's
complement
(STC)
digital voltage input (VI)
1\
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
11
clock input
(f CLK )
10
(+5V)
V DD
16
INPUT BUFFER/LATCH x 8
DECODER
256
PNA7518
VrefH _-t-=9:...-{_- J~---+--+-"'" 0 - - - - - - - - - ,
reference
voltage
inputs
+-_ _----'~_
VrefL --t-=--r--J.-+------r
7Z80546.1
Fig. 1 Block diagram.
540
May
19891 (
analogue
voltage
output
(VAO)
l
8-bit multiplying DAC
PINNING
1
2
3
4
5
6
7
8
9
7Z80547.1
Fig. 2 Pinning diagram.
10
11
12
13
14
15
16
VAO
VrefL
bit 3
bit 2
bit 1
bit 0
VBB
GND
VrefH
fCLK
STC
bit 7
bit 6
bit 5
bit 4
VDD
PNA7518
analogue output voltage
reference voltage LOW
)
digital voltage inputs (VI)
least-significant bit (LSB)
back bias
ground
reference vo Itage HI GH
clock input
select two's complement
most-significant bit (MSB)
digital voltage inputs (VI)
J
positive supply voltage
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
~
«
o
parameter
symbol
IZ
w
Supply voltage range
min.
max.
unit
VDD
-0,5
7,0
V
Input voltage BO to B7 and STC
VI
-0,5
7,0
V
Output voltage
-0,5
7,0
V
>
Total power dissipation
VAO
Ptot
-
800
mW
C
Storage temperature range
T stg
-65
+ 150
Operating ambient temperature range
Tamb
0
+ 70
°C
oC
Temperature range with back bias
TBB
-10
+80
°C
10
-
kHz
:?!
Q,.
o
..J
W
W
Clock frequency
fCLK
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see
"Handling MOS Devices").
1
(May 1989
541
_P_NA7_518_jl________
CHARACTERISTICS
VOD
= 4,5 to 5,5 V; CBB = 100 nF; T amb = 0 to + 70 °C; unless otherwise specified
condit~ons
parameter
I syrbol
(
min.
I
typo
,
max.
unit'
Supply
Supply voltage
Supply current
VOO
4,5
-
5,5
V
IOD
-
-
80
rnA
Inputs BO to B7, ClK, and STC
I nput voltage lOW
VIL
0
-
0,8
V
Input voltage HIGH
VIH
2
-
VOD
V
I nput leakage current
(except STC)
III
-
10
p.A
II
-
100
p.A
Reference voltage LOW
VrefL
0
2
V
Reference voltage HI G H
VrefH
0
-
2
V
Reference ladder between
V ref L and V refH
Rref
150
-
300
!2
-
-
± 0,5
LSB
STC input current
Reference voltages
Linearity
Static non-linearity
note 1
Clock input
Clock frequency
Tamb = 25 oC;
VOD = 5 V
fCLK
10
-
30
MHz
note 2
B
12
-
-
MHz
Bandwidth
Bandwidth at -3 dB
Notes to the characteristics
1. Measured at RAO = 200 k!2; VrefL = 0 V; VrefH = 2 V and fCLK = 28 MHz.
2. Measured at VOO = 5 V; Tamb = 25 °C; Vrefl = 0 V; VrefH = 2 V; fClK = 30 MHz; duty cycle = 0,5;
rise and fall time = 3 ns and a 6 pF load at the analogue output. The analogue output signal is scanned
by an external sample and hold circuit.
542
May
19891 (
~~
_____
P_N_A_7_5_1_8_______
_________
8-_bi_tm_u_lt_iP_ly_in_g_DA_C___________________________
APPLICATION INFORMATION
This section provides additional information to the characteristics. The values are measured on a
sampling basis.
Table 1 Application characteristics
parameter
symbol
typo
unit
Supply current
50
mA
Power consumption
100
P
270
mW
Minimum clock frequency
fCLK
10
kHz
fCLK
45
MHz
Maximum clock frequency
Static non-linearity
± 0,25
LSB
Rref
B
210
n
15
MHz
Set-up time
tsu
3
ns
Input hold time
tHO
4
ns
Propagation delay
tpo
1 x tCLK + 30
ns
l
Reference ladder
Bandwidth
<
~
<
o
~
2
Where:
VOD = 5 V; Tamb = 25 °C; VrefL = 0 V; VrefH = 2,0 V.
w
:E
c..
o...I
W
>
o
CLOCK
W
~,.........,,.........,-r--r--r-r-...,
2,0 V
DATA
ANALOGUE OUTPUT
lZ94958.1
Fig. 3 Switching characteristics.
1
(Mav 1989
543
_________________jl~_S_AA1_057___
RADIO TUNING PLL FREQUENCY SYNTHESIZER
The SAA1057 is a single chip frequency synthesizer IC in 12L technology, which performs all the
tuning functions of a PLL radio tuning system. The IC is applicable to all types of radio receivers,
e.g. car radios, hi-fi radios and portable radios.
Features
• On-chip prescaler with up to 120 MHz input frequency.
• On-chip AM and FM input amplifiers with high sensitivity (30 mV and 10 mV respectively).
• Low current drain (typically 16 mA for AM and 20 mA for FM) over a wide supply voltage range
(3,6 V to 12 V).
• On-chip amplifier for loop filter for both AM and FM (up to 30 V tuning voltage).
• On-chip programmable current amplifier (charge pump) to adjust the loop gain.
• Only one reference frequency for both AM and FM.
• High signal purity due to a sample and hold phase detector for the in-lock condition.
• High tuning speed due to a powerful digital memory phase detector during the out-lock condition.
• Tuning steps for AM are: 1 kHz or 1,25 kHz for a VCO frequency range of 512 kHz to 32 MHz.
• Tuning steps for FM are: 10kHz or 12,5 kHz for a VCO frequency range of 70 MHz to 120 MHz.
• Serial 3-line bus interface to a microcomputer.
• Test/features.
QUICK REFERENCE DATA
Supply voltage ranges
VCC1
VCC2
VCC3
3,6 to 12 V
3,6 to 12 V
VCC2 to 31 V
Supply currents
ICC1 + ICC2
ICC3
typo
typo
18 mA
0,8 mA
Input frequency ranges
at pin FAM
at pin FFM
fFAM
fFFM
Maximum crystal input frequency
fXTAL
>
Tamb
-25 to + 80 °C
Operating ambient temperature range
512 kHz to 32 MHz
70 to 120 MHz
4 MHz
PACKAGE OUTLINE
18-lead OIL; plastic (SOT102H).
'I
(November 1983
545
Jl_________________
___
S_AA1_0S7_ _
FFM
DCA
OUT
FAM
V CC1
V CC 2
16
XTAL
CURRENT
DCS
STABI LlZER
VEE
DLEN
CLB
DATA
15
13
14
12
BUS/LOAD
&
CONTROL
LOGIC
7Z83975.2
Fig. 1 Block diagram.
GENERAL DESCRIPTION
The SAA1057 performs the entire PLL synthesizer function (from frequency inputs to tuning voltage
output) for all types of radios with the AM and FM frequency ranges.
The circuit comprises the following:
• Separate input amplifiers for the AM and FM VeO-signals.
• A divider-by-1 0 for the FM channel.
• A multiplexer which selects the AM or FM input.
• A 15-bit programmable divider for selecting the required frequency.
• A sample and hold phase detector for the in-lock condition, to achieve the high spectral purity of
the veo signal.
• A digital memory frequency/phase detector, which operates at a 32 times higher frequency than
the sample and hold phase detector, so fast tuning can be achieved.
• An in-lock counter detects when the system is in-lock. The digital phase detector is switched-off
automatically when an in-lock condition is detected.
• A reference frequency oscillator followed by a reference divider. The frequency is generated by a
4 MHz quartz crystal. The reference frequency can be chosen either 32 kHz or 40 kHz for the
digital phase detector (that means 1 kHz and 1,25 kHz for the sample and hold phase detector),
which results in tuning steps of 1 kHz and 1,25 kHz for AM, and 10 kHz and 12,5 kHz for FM.
• A programmable current amplifier (charge pump), which controls the output current of both the
digital and the sample/hold phase detector in a range of 40 dB. It also allows the loop gain of the
tuning system to be adjusted by the microcomputer.
• A tuning voltage amplifier, which can deliver a tuning voltage of up to 30 V.
• BUS; this circuitry consists of a format control part, a 16-bit shift register and two 15-bit latches.
Latch A contains the to be tuned frequency information in a binary code. This binary-coded number, multiplied by the tuning spacing, is equal to the synthesized frequency. The programmable divider
(without the fixed divide-by-10 prescaler for FM) can be programmed in a range between 512 and
32767 (see Fig. 3). Latch B contains the control information.
546
November
19831 (
l____
Radio tuning PLL frequency synthesizer
S_A_A_10_5_7______
OPERATION DESCRIPTION
Control information
The following functions can be controlled with the data word bits in latch B. For data word format
and bit position see Fig. 3.
FM
REF H
FM/AM selection; '1' = FM, '0' = AM
reference frequency selection; '1' = 1,25 kHz, '0'
g:;
control bits for th~ programmable current amplifier
(see section Characteristics)
CP1
CPO
I
= 1 kHz (sample and
SB2
enables last 8 bits (SLA to TO) of data word B;
'1' = enables, '0' = disables; when programmed '0', the last 8 bits
of data word B will be set to '0' automatically
SLA
load mode of latch A; '1'
POM1 )
POMOJ
phase detector mode
hold phase detector)
= synchronous, '0' = asynchronous
POM1
POMO
digital phase
detector
0
X
automatic
on/off
1
0
on
1
1
off
BRM
bus receiver mode bit; in this mode the supply current of the BUS
receiver will be switched-off automatically after a data transmission
(current-draw is reduced); '1' = current switched; '0' = current always on
T3
test bit; must be programmed always '0'
T2
test bit; selects the reference frequency (32 or 40 kHz) to the TEST pin
T1
test bit; must be programmed always '0'
TO
test bit; selects the output of the programmable counter to the TEST pin
T3
T2
T1
TO
0
0
0
0
1
0
1
0
0
reference frequency
0
0
0
1
output programmable counter
0
1
0
1
output in-lock counter
'0' = out-lock
'1' = in-lock
TEST (pin 18)
"1
(November 1983
547
_Jl_________
__
SAA_105_7
D LEN::z::1
I
I
--I -..1--
tClBleadCLB
,-
__
W/'k\\§\\\'j
tDLENhoid __
tClB lag2
II.....
---t-------
S
tDIST ,--
,--
~ __
-- tCLBL
I.....
tCLBH --
-"'ftDATAhOld
tDATAlead
===x.....----..X
DATA
Xll/d//U __ _
7Z83974.1
__ test leading zero
bit no.
--I
L...-_ _ _ _
t LZ su (1)
tCLBlag1
o
15
16
Fig. 2 BUS format.
(1) During the zero set-up time (tLZsu) CLB can be LOW or HIGH, but no transient of the signal is
permitted. This can be of use when an 12 C bus is used for other devices on the same data and clock
lines.
DATA WORD A
bits stored in latch A
512';; dividing number';; 32767
DATA WORD B
bits stored' in latch B
Fig.3 Bit organization of data words A and B.
548
November
19831 (
7Z83973
l
Radio tuning PLL frequency synthesizer
SAA1057
PINNING
1
2
3
TR
TCA
TCB
} resistor/capacitors
decoupling of supply
for sample and
hold circuit
4
DCS
5
IN
input of output amplifier
6
OUT
output of output amplifier
7
VCC3
positive supply voltage of
output amplifier
8
FFM
FM signal input
9
VCC1
positive supply voltage of
high frequency logic part
10
DCA
decoupling of input
amplifiers
7Z83971
Fig.4 Pinning diagram.
11
FAM
AM signal input
12
13
14
DATA
OLEN
CLB
} BUS
15
VEE
ground
16
VCC2
positive supply voltage of
low frequency logic part and
analogue part
17
XTAL
reference oscillator input
18
TEST
test output
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage; logic and analogue part
VCC1; VCC2
Supply voltage; output amplifier
VCC3
Ptot
max.
Tamb
T stg
-65 to + 150 0C
Total power dissipation
Operating ambient temperature range
Storage temperature range
-0,3 to 13,2 V
VCC2 to + 32 V
800 mW
-30 to + 85 0C
'I
(November 1983
549
Jl_________________
_ _ _S_AA1_0S7_ _
CHARACTE R ISTICS
VEE
= 0 V; VCC1 = VCC2 = 5 V;
Supply voltages
Supply currents*
AM mode
FM mode
Operating ambient
temperature
VCC3
= 30 V; Tamb = 25 oC;
symbol
min.
typo
VCC1
VCC2
VCC3
3,6
3,6
VCC2
5
5
-
Itot
-
ICC3
0,3
0,8
Tamb
-25
-
Itot
16
20
unless otherwise specified
max.
12
12
31
conditions
V
V
V
-
mA
-
mA
1,2
mA
+80
Itot
= ICC1
+ ICC2
in-lock: BRM = '1';
} PDM
= '0'
lOUT
=0
°C
RF inputs (FAM, FFM)
AM input frequency
FM input frequency
fFAM
512 kHz
fFFM
70
Input voltage at FAM
Vi (rms)
30
Input voltage at F FM
Vi (rms)
10
Input resistance at FAM
Ri
-
Input resistance at FFM
Ri
-
32
MHz
120
MHz
500
mV
500
mV
2
-
kn
-
135
n
Input capacitance at FAM
C'I
-
3,5
-
Input capacitance at FFM
C'I
-
3
-
pF
Voltage ratio allowed
between selected and
non-selected input
Vs/Vns
-
-30
-
dB
pF
Crystal oscillator (XTA L)
see note 1
Maximum input frequency
fXTAL
Crystal series resistance
Rs
4
-
-
-
-
150
0,8
V
VCC1
V
MHz
n
BUS inputs (OLEN, CLB,
DATA)
Input voltage LOW
VIL
0
-
Input voltage HIGH
VIH
2,4
-
Input current LOW
-IlL
-
-
10
/lA
VIL
Input current HIGH
IIH
-
-
10
/lA
VIH
= 0,8 V
= 2,4 V
* When the bus is in the active mode (see BRM in Control Information), 4,5 mA should be added to the
figures given.
550
November
19831 (
l___
Radio tuning PLL frequency synthesizer
S_A_A_1_05_7_ __
CHARACTERISTICS (continued)
VEE
= 0 V; VCC1 = VCC2 = 5 V;
VCC3
= 30 V; Tamb = 25 oC; unless otherwise specified
symbol
min.
typo
max.
conditions
BUS inputs timing
(DLEN, CLB, DATA)
see also Fig. 2 and
note 2
Lead time for CLB to DLEN
tCLBlead
Lead time for DATA to
the fi rst C LB pu Ise
tTlead
1
-
-
p.s
·0,5
-
-
J.Ls
J.LS
Set-up time for DLEN
to CLB
tCLBlag1
5
-
-
CLB pulse width HIGH
tCLBH
5
-
-
J.LS
CLB pulse width LOW
tCLBL
5
-
-
J.LS
Set-up time for DATA
to CLB
tDATAlead
2
-
-
J.LS
-
-
J.LS
-
J.LS
Hold time for DATA to CLB
tDATAhoid
0
Hold time for DLEN to CLB
tDLENhoid
2
-
Set-up time for D LE N to
CLB load pulse
tCLBlag2
2
-
-
J.LS
Busy time from load pulse
to next start of transmission
tDIST
5
-
-
J.LS
Busy time
asynchronous mode
tDIST
0,3
-
-
ms
tDIST
1,3
-
-
ms
synchronous mode
Sample and hold circuit
(TR, TCA, TCB)
next transmission
{ after word 'B'
to other device
or
} next transmission
to SAA1057
after word 'A'
(see also note 5)
see also notes 3; 4
Minimum output voltage
VTCA,
VTCB
-
1,3
Maximum output voltage
VTCA,
VTCB
-
-
Capacitance at TCA
(external)
CTCA
CTCA
Discharge time at TCA
tdis
tdis
-
-
-
-
-
-
-
Resistance at TR
RTR
100
-
Voltage at TR during
discharge
V
-
VCC2- 0,7 V
2,2 nF
2,7 nF
REFH
REFH
= '1'
= '0'
= '1'
= '0'
J.LS
REFH
REFH
-
n
external
-
V
5
6,25
J.LS
VTR
-
0,7
Capacitance at TCB
CTCB
-
10 nF
external
Bias current into TCA, TCB
Ibias
-
-
10 nA
in-lock
1
(November 1983
551
___
SAA_105_7_Jl_________________
CHARACTERISTICS (continued)
VEE = 0 V; VCC1 = VCC2 = 5 V; VCC3
= 30 V; Tamb = 25 oC; unless otherwise specified
symbol
min.
typo
max.
conditions
± Idig
-
0,4
-
Gp1
Gp2
Gp3
Gp4
Gp5
-
0,023
0,07
0,23
0,7
2,3
-
-
-
1,0
-
p.A/V
-
-
1
V
in-lock
-
1,3
-
V
{ in-lock; equal to
internal reference voltage
Programmable current
amplifier (PCA)
Output current of the
dig. phase detector
mA
Current gain of PCA
CP3 CP2 CP1 CPO
P1
P2
P3
P4
P5
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
0
Ratio between the output
current of S/H into PCA
and the voltage on
CTCB
STCB
Offset voltage on TCB
LlVTCB
VCC2 ~ 5 V (only for P1)
-
-
-
Output amplifier (IN,OUT)
I nput voltage
VIN
Output voltages
minimum
maximum
maximum
VOUT
VOUT
VOUT
Maximum output current
± lOUT
VCC3- 2
VCC3- 1
5
-
-
0,5 V
- V
- V
-
mA
-lOUT = 1 mA
lOUT = 1 mA
lOUT =0,1 mA
VOUT =% VCC3
Test output (TEST) *
Output voltage LOW
0,5 V
VTL
-
-
Output voltage HI G H
VTH
-
-
12
V
Output current 0 F F
I Toft
-
-
10
p.A
VTH
ITon
150
-
-
p.A
VTL
LlVCC1/LlV OUT
LlVCC2/LlV OUT
-
77
-
dB
-
70
-
dB
Ll V CC3/Ll VOUT
-
60
-
dB
Output current ON
Ripple rejection**
at fripple
= 100 Hz
* Open collector output.
** Measured in Fig. 6.
552
November
19831 (
VOUT ~ VCC3-3 V
l___
Radio tuning PLL frequency synthesizer
S_A_A_10_5_7_ __
NOTES
1. Pin 17 (XTA L) can also be used as input for an external clock.
The circuit for that is given in Fig. 5. The values given in Fig. 5 are a typical application example.
+ 5V
J1J ~nF
22kSl
OV
17
XTAL
I
4 MHz
CXTAL*~F
I
W
7Z83970
Fig.5 Circuit configuration showing external 4 MHz clock.
2. See BUS information in section 'operation description'.
3. The output voltage at TCB and TCA is typically % V CC2+0,3 V when the tuning system is in-lock
via the sample and hold phase detector. The control voltage at TCB is defined as the difference
between the actual voltage at TCB and the value calculated from the formula % VCC2+0,3 V.
4. Crystal oscillator frequency fXTAL
= 4 MHz.
5. The busy-time after word "A" to another device which has more clock pulses than the SAA 1057
(> 17) must be the same as the busy-time for a next transmission to the SAA 1057.
When the other device has a separate D LE N or has less clock pu Ises than the SAA 1057 it is not
necessary to keep to this busy-time, 5 p.s will be sufficient.
APPLICATION INFORMATION
Initialize procedure
Either a train of at least 10 clock pulses should be applied to the clock input (CLB) or word B should
be transmitted, to achieve proper initialization of the device.
For the complete initialization (defining all control bits) a transmission of word B should follow. This
means that the I C is ready to accept word A.
Synchronous/asynchronous operation
Synchronous loading of the frequency word into the programmable counter can be achieved when bit
'SLA' of word B is set to '1'. This mode should be used for small frequency steps where low tuning noise
is important (e.g. search and manual tuning). This mode should not be used for frequency changes of
more than 31 tuning steps. In this case asynchronous loading is necessary. This is achieved by setting
bit 'SLA' to '0'. The in-lock condition will then be reached more quickly, because the frequency information is loaded immediately into the divider.
Restrictions to the use of the programmable current amplifier
The lowest current gain (0,023) must not be used in the in-lock condition when the supply voltage
V CC2 is below 5 V (CP3, CP2, CP1 and CPO are all set to '0'). This is to avoid possible instability of the
loop due to a too small range of the sample and hold phase detector in this condition (see also section
'Characteristics') .
Transient times of the bus signals
When the SAA 1057 is operating in a system with continuous activity on the bus lines, the transient
times at the bus inputs should not be less than 100 ns. Otherwise the signal-to-noise ratio of the tuning
voltage is reduced.
1
(November 1983
553
_S_AA10_57
_Jl_______
TUNER
47 J.lF 4
~ +
VCCl
TR
TCA
DCS
TCB
V CC3
10 kn ( 1)
OUT i-=---_L~_+____,- tuning
voltage
I
*
I
10 nF
~ 10 DCA
100 nF (1)
oSCillato~
(Zi=75n)r~
FM
SAA1057
1 nF 8
330 nF
FFM
TEST 18
FAM
XTAL 17
•
I
~
(1)
4 MHz
22 nF
AM oscillator
(Zi = 2 kn)
I
I
IN
180n
11
VEE
DLEN CLB DATA
~------'---~--r------~--~
OH~
~
27pF
7Z83972.1
BUS
(1) Values depend on the tuner diode characteristics.
Fig.6 Application example of the SAA 1057PLL frequency synthesizer module.
554
November
19831 (
_ _ _ _ _l:_[~~
_Jl_S_AA10_64_
2
4-DIGIT LED-DRIVER WITH 1 C BUS INTERFACE
GENERAL DESCRIPTION
The LED-driver is a bipolar integrated circuit made in an 12 L compatible 18 volts process. The circuit
is especially designed to drive four 7-segment LED displays with decimal point by means of multiplexing
between two pairs of digits. It features an 12 C bus slave transceiver interface with the possibility to
program four different SLAVE ADDRESSES, a POWER RESET flag, 16 current sink OUTPUTS,
controllable by software up to 21 mA, two multiplex drive outputs for common anode segments, an
on-chip multiplex oscillator, control bits to select static, dynamic and blank mode, and one bit for
segment test.
QUICK REFERENCE DATA
parameter
conditions
Supply voltage
=5 V
symbol
min.
VCC
4,5
5
15
V
9,5
-
mA
typo
max.
unit
ICC
-
Total power dissipation
24-lead DI L (SOT-101 B)
Ptot
-
-
1000
mW
Operating ambient
temperatu re range
Tamb
-20
-
+ 70
oC
Supply current all outputs OFF
VCC
PACKAGE OUTLINE
SAA1064P: 24-lead OIL; plastic (with internal heat spreader) (SOT101B).
1
(November 1987
555
CJ'I
CJ'I
0)
Z
0
en
»
»
.....
SAA1064
<
CD
o
m
3
C'"
~
~
EMITTER
FOLLOWER
c.o
OJ
141 MX2
1/0
'-I
PR
CURRENT
DAC
131 VCC
LEN
2
1 C BUS
LCO
RESET
AON
ADR 11
IA1N
INSTRUCTION
DECODER
I PR
LEVEL
DETECTOR
&
CURRENT
REFERENCE
CLOCK
DIVIDER
121 VEE
EMITTER
FOLLOWER
111 MX1
EN
CEXT 12
CLOCK
OSCILLATOR
lZ81282.2
Fig. 1 Block diagram.
l___
4-digit LED-driver with 12 C bus interface
S_A_A_10_6_4_ __
PINNING
P14
P13
SAA1064
P12
P11
P10
P1
P9
MX2
VEE
Vee
7Z81283
Fig.2 Pinning diagram.
FUNCTIONAL DESCRIPTION
Is 10
1 1 0 A 1 AO
status byte
slave address
Fig.3a
2
1 C
bus format; READ mode.
S 0 1 1 1 0 A 1 AO 0 A 0 0 0 0 0 SC S8 SA A X C6 C5 C4 C3 C2 C 1 CO A
slave address
control byte
instruction byte
~]D 17 ___m ___m_m __ D 10 IA ID27 -m--m---------D 20 IA ID37 ------------------D30 IA ID47 _____
data digit 1
data digit 2
Fig.3b
S = start condition
P = stop condition
A = acknowledge
X = don't care
2
1 C
m_mmm
III
D40 A P
data digit 4
data digit 3
bus format; WRITE mode.
A 1, AO
SC S8 SA
C6 to CO
PR
= programmable address bits
= subaddress bits
= control bits
= POWER RESET flag
Address pin ADR
Four different slave addresses can be chosen by connecting ADR either to VEE, 3/8 VCC, 5/8 VCC
or VCC. This results in the corresponding valid addresses HEX 70, 72, 74 and 76 for writing and 71,
73, 75 and 77 for reading. All other addresses cannot be acknowledged by the circuit.
1(
November 1987
567
_S_AA1_064_Jl________
Status byte
Only one bit is present in the status byte, the POWER RESET flag. A logic 1 indicates the occurence of a
power failure since the last time it was read out. After completion of the READ action this flag will be
set to logic O.
Subaddressing
The bits SC, SB and SA form a pointer and determine to which register the data byte following the
instruction byte will be written. All other bytes will then be stored in the registers with consecutive
subaddresses. This feature is called Auto-I ncrement (AI) of the subaddress and enables a quick
initialization by the master.
The subaddress pointer will wrap around from 7 to O.
The subaddresses are given as follows:
subaddress
SC
SB
SA
0
0
0
00
control register
0
0
1
01
digit 1
function
0
1
0
02
digit 2
0
1
1
03
digit 3
1
0
0
04
digit 4
1
0
1
05
1
1
0
06
1
1
1
07
} reserved,
not used
Control bits (see Fig. 4)
The control bits CO to C6 have the following meaning:
CO;: 0
static mode, i.e. continuous display of digits 1 and 2
CO;: 1
dynamic mode, i.e. alternating display of digit 1 + 3 and 2 + 4
C1 ;: 0/1
digits 1 + 3 are blanked/not blanked
C2;: 0/1
digits 2 + 4 are blanked/not blanked
C3;: 1
all segment outputs are switched-on for segment test*
=1
=1
adds 3 mA to segment output current
C5
C6
=1
adds 12 mA to segment output current
C4
adds 6 mA to segment output current
Data
A segment is switched ON if the corresponding data bit is logic 1. Data bits D17 to 010 correspond with
digit 1, 027 to D20 with digit 2, 037 to 030 with digit 3 and 047 to 040 with digit 4.
The MSBs correspond with outputs P8 and P16, the LSBs with P1 and P9. Digit numbers 1 to 4 are
equal to their subaddresses (hex) 1 to 4.
* At a current determined by C4, C5 and C6.
558
November
19871 (
4-digit LED-driver with 12 C bus interface
l___
I
S_A_A_10_6_4_ _
SDA, SCL
The SDA and SCL I/O meet the 12 C bus specification. For protection against positive voltage pulses
on these inputs voltage regulator diodes are connected to VEE. This means that normal line voltage
should not exceed 5,5 volt. Data will be latched on the positive-going edge of the acknowledge related
clock pulse.
Power-on reset
The power-on reset signal is generated internally and sets all bits to zero, resulting in a completely
blanked display. Only the POWE R RESET flag is set.
External Control (CEXT)
With a capacitor connected to pin 2 the multiplex frequency can be set (see Fig. 5). When static this pin
can be connected to VEE or VCC or left floating since the oscillator will be switched off.
Segment outputs
The segment outputs P1 to P16 are controllable current-sink sources. They are switched on by the
corresponding data bits and their current is adjusted by control bits C4, C5 and C6.
Multiplex outputs
The multiplex outputs MX1 and MX2 are switched alternately in dynamic mode with a frequency
derived from the clock -osci Ilator. I n static mode M X 1 is switched on. The outputs consist of an
emitter-follower, which can be used to drive the common anodes of two displays directly provided
that the total power dissipation of the circuit is not exceeded. If this occurs external transistors should
be connected to pins 11 and 14 as shown in Fig. 5.
I (November198~
559
----i
•
~
___
SAA_106_4_Jl_________________
RATINGS
Limiting values in accordance with the Absolute Maximum System (lEe 134)
parameter
conditions
symbol
min.
max.
unit
Supply voltage (pin 13)
Vee
-0,5
18
V
Supply current (pin 13)
lee
-50
200
mA
Total power dissipation
SOT-101
24-lead 01 L
Ptot
1000
mW
V23,24-12
-0,5
5,9
V
V1-11, V14-22
±I
-0,5
Vee + 0,5
V
-
10
mA
Operating ambient
temperatu re range
Tamb
-20
+ 70
oe
Storage temperature range
Tstg
-65
+ 125
oe
SOA, SeL voltages
Voltages AO-MX1 and MX2-P16
Input/output current all pins
outputs OFF
THERMAL RESISTANCE
From crystal to ambient
24-lead OIL
560
November
19871 (
Rth cr-a
35 K/W
l____
4-digit lED-driver with 12 C bus interface
S_AA_1_0_6_4______
CHARACTERISTICS
VCC = 5 V; T amb = 25 oe; voltages are referenced to ground (VEE = 0 V); unless otherwise specified
parameter
conditions
typo
max.
unit
4,5
5,0
15
V
7,0
9,5
14,0
mA
-
50
-
mW
5,5
V
symbol min.
Supply
Supply voltage (pin 13)
Supply current
Power dissipation
Vee
all outputs OFF
Vee = 5 V
ICC
all outputs OFF Pd
SDA; SCl bus (pins 23 and 24)
I nput voltages
V23,24 0
-
Logic input voltage LOW
VIL(L) -
-
1,5
V
Logic input voltage HIGH
VIH(L) 3,0
-
-
V
-
-10
JJ.A
10
JJ.A
Input cu rrent LOW
V23,24 = VEE
IlL
-
Input current HIGH
V23,24 = Vee
IIH
-
10 = 3 mA
VOL(L) -
SDA
Logic output voltage LOW
Output sink current
V
3
-
0,4
10
-
mA
Vl
VEE
-
3/ 16Vee
V
Address input (!=lin 1)
I nput voltage
programmable address bits:
AO = 0; Al = 0
AO = 1; Al = 0
Vl
5/ 16V ee
3/8 V ee 7/16Vce
V
AO = 0; Al = 1
Vl
9/ 16Vce
5/8V ce
11/ 16Vee
V
AO = 1; A 1 = 1
Vl
13/ 16Vee
-
Vee
V
JJ.A
Input cu rrent LOW
Vl = VEE
11
-
-
~10
I nput current H IG H
Vl = Vee
11
-
-
10
Vil
-
Vee-2,5
-
V
-180
180
JJ.A
JJ.A
External control (eEXT) pin 2
Switching level input
I nput voltage LOW
Input voltage HIGH
nput cu rrent
V2= 2 V
V2= 4 V
VIH
Vee- 1,5
-
12
12
-140
140
-160
160
1
V
(November 1987
561
_Jl________
__
SA_A106_4
CHARACTERISTICS (continued)
conditions
symbol
min.
typo
max. unit
Output voltages
10 = 15 mA
Va
-
0,5
Output current HIGH
Va = VCC = 15 V
10
-
-
Output current LOW
control bits HIGH
C4, C5 and C6
VO= 5 V
parameter
Segment outputs
(P8 to Pl; pins 3 to 10)
(P9 to P16; pins 15 to 22)
V
± 10 IlA
10
17,85
21
25
mA
Contribution of:
control bit C4
10
2,55
3,0
4,0
mA
control bit C5
10
5,1
6,0
7,0
mA
10
10,2
12,0 14,0 mA
13 to 110 and '15 to 122 = 3 mA
~IO
-
%
13 to 110 and '15 to 122 = 21 mA
~IO
-
5
-
7
%
-
V
control bit C6
Relative segment 1 output accuracy
with respect to highest value when:
Multiplex 1 and 2 (pins 11 and 14)
Output voltage
(when ON)
10 = 50 mA
Va
VCC 1,5
-
Output current HI G H
(when ON)
VO=2 V
111; '14
50
-
mA
70
100
mA
-
10
ms
Va =2 V
-111; -'14 50
Output period
C2-12 = 2,7 nF
TMPX
5
TMPX
-
1,25 -
TMPX
-
666
-
IlS
48,4
-
-
%
C2-12 = 820 pF
C2-12 = 390 pF
Output duty factor
* Value to be fixed.
562
*
Output current LOW
(when OFF)
November
19871 (
ms
l____
4-digit LED-driver with 12 C bus interface
S_A_A_10_6_4______
CO
C1
C2
><
><
MUX
MX1
MX2
-,
I I~----------------~II~------
----------------------------~II~----~~
I-
DETAIL
CLOCK
"I
clock frequency /64
~---~
MUX
MX1
MX2
7Z81284
Fig.4 Timing diagram.
3
4
CA
SDA
P16
P15
P14
5V
1/
1/
/ /
SCL
CA
L /
P13
P12
P11
P10
P9
MX2
P3
P2
P1
MX1
SAA1064
5V
P8
P7
P6
1/
L /
CA
P4
1/
/ /
2
CA
7Z81285
Fig.5 Dynamic mode application diagram.
' ) (November 1987
563
__
SAA1_064_Jl_ _ _ _ _ _ __
5V
2
CA
1/
L/
13
SCL
SDA
P16
P15
P14
P13
P12
P11
P10
P9
P3
P2
P1
MX2
Vce
SAA1064
ADA
P8
P7
P6
P5
P4
1/
L /
CA
5V
Fig.6 Static mode application diagram.
Purchase of Philips' 12C components conveys a license under the
Philips' 12C patent to use:the components in the 12C-system
provided the system conforms to the 12C specifications defined
by Philips.
564
November
19871 (
l____
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
S_A_A_10_9_9______
MICROPROCESSOR CONTROLLED STEREO SOUND GENERATOR
FOR SOUND EFFECTS AND MUSIC SYNTHESIS
GENERAL DESCRIPTION
The SAA1099 is a monolithic integrated circuit designed for generation of stereo sound effects and
music synthesis.
Features
• Six frequency generators
eight octaves per generator
256 tones per octave
• Two noise generators
• Six noise/frequency mixers
• Twelve amplitude controllers
• Two envelope controllers
• Two 6-channel mixers/current sink analogue output stages
• TTL input compatible
• Readily interfaces to 8-bit microcontroller
• Minimal peripheral components
• Simple output filtering
Applications
•
•
•
•
Consumer games systems
Home computers
Electronic organs
Arcade games
• Toys
• Chimes/alarm clocks
QUICK REFERENCE DATA
Voo
typo
5 V
Supply current (pin 18)
100
typo
70 rnA
Reference current (pin 6)
typo
250 JlA
Total power dissipation
I ref
Ptot
Operating ambient temperature range
Tamb
Supply voltage (pin 18)
500 mW
o to + 70
oC
PACKAGE OUTLINE
18-lead 01 L; plastic (SOT102).
I
(November 1986
565
U'I
en
en
WR
CS
VSS
AD
en
»
Iref
»
--10.
o
<0
<0
s:
III
-<
~
DTACK
GENERATOR
U'I
address bus
data bus
rL--1from amplitude
control
MIXER
AND
~ left
OUTPUT ~ output
STAGE
I I 51
LINE
DRIVERS
07
to frequency and
noise registers
CLK
I~
.1
MIXER
AND
OUTPUT
'----+-•• 1 STAGE
internal
clocks
(4 MHz)
7Z80466
Fig. 1 Block diagram.
right
output
SAA1099
Microprocessor controlled stereo sound generator
for sound effects and music synthesis
PINNING
Voo
07
06
05
SAA1099
04
03
02
7Z90786
Fig. 2 Pinning diagram.
o:!
o:!
PIN DESIGNATION
I-
WR
Write Enable: active lOW input which operates in conjunction with CS and
AO to allow writing to the internal registers.
2
CS
0
...I
w
Chip Select: active lOW input to identify valid WR inputs to the chip. This
input also operates in conjunction with WR and AO to allow writing to the
internal registers.
3
AD
Control/Address select: input used in conjunction with WR and CS to load
data to the control register (AD = 0) or the address buffer (AO = 1).
Q
4
OUTR
Right channel output: a 7-level current sink analogue output for the 'right'
component. This pin requires an external load resistor.
5
OUTl
left channel output: a 7-level current sink analogue output for the 'ieft'
component. This pin requires an external load resistor.
6
7
Iref
OTACK
8
ClK
Clock: input for an externally generated clock at a nominal frequency of
8 MHz.
9
VSS
Ground: 0 V.
10-17
00-07
Data: Oata bus input.
18
VOO
Power supply:
0
I-
zw
~
0..
>
w
Reference current supply: used to bias the current sink outputs.
Data Transfer Acknowledge: open drain output, active lOW to acknowledge
successful data transfer. On completion of the cycle OTACK is set to inactive.
+ 5 V typical.
1
(May 1985
567
SAA1099
FUNCTIONAL DESCRIPTION
The following sections provide a detailed functional description of the SAA 1099 as shown in the block
diagram, Fig. 1.
Frequency generators
Six frequency generators can each select one of 8 octaves and one of 256 tones within an octave.
A total frequency range of 31 Hz to 7,81 kHz is available. The outputs may also control noise or
envelope generators. All frequency generators have an enable bit which switches them on and off,
making it possible to preselect a tone and to make it inaudible when required. The frequency
generators may be synchronized using the frequency reset bit.
The frequency ranges per octave are:
Octave
Frequency range
a
31 Hz to 61 Hz
61 Hz to 122 Hz
122 Hz to 244 Hz
245 Hz to 488 Hz
489 Hz to 977 Hz
978 Hz to 1,95 kHz
1,96 kHz to 3,91 kHz
3,91 kHz to 7,81 kHz
1
2
3
4
5
6
7
Noise generators
The two noise generators both have a programmable output. This may be a software controlled noise
via one of the frequency controlled generators or one of three pre-defined noises. There is no tone
produced by the frequency generator when it is controlling the noise generator. The noise produced is
based on double the frequency generator output, i.e. a range of 61 Hz to 15,6 kHz.
I n the event of a pre-defined noise being chosen, the output of noise generator can be mixed with
frequency generator 0, 1 and 2; and the output of noise generator 1 can be mixed with frequency
generator 3,4 and 5. In order to produce an equal level of noise and tone outputs (when both are
mixed) the ampl itude of the tone is increased. The three pre-defined noises are based on a clock
frequency of 7,8 kHz, 15,6 kHz or 31,25 kHz.
a
Noise/frequency mixers
Six noise/frequency mixers each with four selections
•
•
•
•
Channel off
Frequency only
Noise only
Noise and frequency
Each mixer channel has one of the frequency generator outputs fed to it, three channels use noise
generator and the other three use noise generator 1.
a
Amplitude controllers
Each of the six channel outputs from the mixer is split up into a right and left component giving
effectively twelve amplitude controllers. An amplitude of 16 possible levels is assigned to each of the
twelve signals. With this configuration a stereo effect can be achieved by varying only the ampl itude
component. The moving of a sound from one channel to the other requires, per tone, only one update
of the amplitude register contents.
When an envelope generator is used, the ampl itude levels are restricted. The number of levels available
is then reduced to eight. This is achieved by disabling the least significant bit (LSB) of the amplitude
control.
568
May
19851 (
Microprocessor controlled stereo sound generator
for sound effects and music synthesis
l____
S_A_A_10_9_9____
Envelope controllers
Two of the six tone generators are under envelope control. This applies to both the left and right
outputs from the tone generator.
The envelope has the following eight possible modes:
•
•
•
•
•
•
•
•
Amplitude is zero
Single attack
Single decay
Single attack-decay (triangular)
Maximum amplitude
Continuous attack
Continuous decay
Continuous attack-decay
The timing of the envelope controllers is programmable using one of the frequency generators (see
Fig. 1). When the envelope mode is selected for a channel its control resolution is halved for that
channel from 16 levels to 8 levels by rounding down to the nearest even level.
There is also the capability of controlling the 'right' component of the channel with inverse of the
'left' component, which remains as programmed.
W
Command/control select
I n order to simplify the microprocessor interface the command and control information is multiplexed.
To select a register in order to control frequencies, amplitudes, etc. the command-register has to be loaded.
The contents of this register determines to which register the data is written in the next control-cycle.
If a continuous update of the control-register is necessary, only the control-information has to be
written (the command-information does not change).
If the command/control select (AO) is logic 0, the byte transfer is control; if AO is logic 1, the byte
transfer is command.
I nterface to microprocessor
The SAA 1099 is a data bus based I/O peripheral. Depending on the value ofthe command/control
signal (AO) the CS and WR signals control the data transfer from the microprocessor to the SAA 1099.
The data-transfer-acknowledge (DTACK) indicates that the data transfer is completed. When, during
the write cycle, the microprocessor recognizes the DTACK, the bus cycle will be completed by the
processor.
569
~
___S_AA_109_9_jl~________________
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage (pin 18)
VDD
-0,3 to + 7,5 V
Maximum input voltage
VI
-0,3 to + 7,5 V
VI
-0,5 to + 7,5 V
at VDD
= 4,5 to 5,5 V
Maximum output current
10
Total power dissipation
Storage temperature range
Ptot
T stg
Operating ambient temperature range
T amb
Electrostatic handling*
Ves
* Equivalent to discharging a 250 J.l.F capacitor through a 1 kS1 series resistoL
570
May
19851 (
max.
10 mA
500 mW
-55 to + 125 °C
0 to
+ 70 °C
-1000 to + 1000 V
l____
Microprocessor controlled stereo sound generator
S_A_A_10_9_9______
for sound effects and music synthesis
D.C. CHARACTERISTICS
V DD = 5 V ± 10%; T amb = 0 to 70 oC; unless otherwise specified
parameter
symbol
min.
typo
max.
unit
Supply
Supply voltage
VDD
4,5
5,0
5,5
V
Supply current
IDD
-
70
100
mA
Reference current (note 1)
I ref
100
250
400
J.l.A
VIH
2,0
-
6,0
V
INPUTS
Input voltage HIGH
I nput voltage LOW
VIL
-0,5
-
0,8
V
I nput leakage current
± III
-
-
10
J.l.A
I nput capacitance
CI
-
-
10
pF
VOL
0
0,4
V
OUTPUTS
DTACK (open drain; note 2)
«
«
Q
I-
I2
w
:?!
c..
o..J
Output voltage LOW
at IOL = 3,2 mA
Voltage on pin 7 (OFF state)
V7-9
-0,3
Output capacitance (OFF state)
Co
-
-
Load capacitance
CL
-
-ILO
-
101 II ref
W
Output leakage current (OFF state)
Cl
Audio outputs (pins 4 and 5)
>
W
6,0
V
10
pF
-
150
pF
-
10
J.l.A
90
-
120
%
85
-
110
%
With fixed Iref (note 3)
One channel on
Six channels on
With Iref = 250 pA; RL
106 /6xl ref
= 1,5 kn
(± 5%)
One channel on
101/1ref
90
%
106 /6xl ref
85
-
110
Six channels on
105
%
Output current one channel on
101
225
-
275
J.l.A
Output current six channels on
106
1,3
-
1,6
mA
101
150
-
350
J.l.A
With resistor supplying I ref (note 4)
Output current one channel on
Output current six channels on
106
0,9
-
1,9
mA
Load resistance
RL
600
-
-
n
D.C. leakage current all channels off
-ILO
-
-
10
J.l.A
Maximum current difference between
left and right current sinks (note 5)
± lOmax
-
-
15
%
Signal-to-noise ratio (note 6)
SIN
-
tbf
-
dB
1
(May 1985
571
SAA1099
A.C. CHARACTERISTICS
VOO = 5 V ± 10%; Tamb = 0 to 70 oC; timing measurements taken at 2,0 V for a logic 1 and 0,8 V
for a logic 0 unless otherwise specified (see waveforms Figs 3 and 4)
symbol
min.
typo
max.
unit
AO set-up time to CS fall
tASC
0
-
ns
CS LOW to WR fall
AO set-up time to WR fall
tcsw
30
-
ns
tASW
50
-
ns
WR LOW time
tWL
100
-
ns
Oata bus va I id to W R rise
tBSW
100
-
-
ns
OTACK fall delay from WR fall (note 7)
tOFW
0
-
85
ns
-
-
ns
100
ns
parameter
Bus interface timing (see Fig. 3)
AO hold time from WR HIGH
tAHW
0
CS hold time from WR HIGH
tCHW
0
-
Oata bus hold time from WR HIGH
tOHW
0
OTACK rise delay from WR HIGH
tORW
0
-
-
-
Bus cycle time (note 8)
tCY
4tCLK
-
Bus cycle time (note 9)
tCY
16tCLK
-
ns
ns
Clock input timing (see Fig. 4)
Clock period
tCLK
120
125
255
ns
Clock LOW time
tLOW
55
-
-
ns
Clock HIGH time
tHIGH
55
-
-
ns
Notes to the characteristics
1. Using an external constant current generator to provide a nominal Iref or external resistor
connected to VOO.
2. This output is short-circuit protected to VOO and VSS.
3. Measured with I ref a constant value between 100 and 400 IlA; load resistance (RL) allowed to match
E12 (5%) in all applications via:
R L = 0,6 [I ref]
-1
-16 [I ref]
-0,5
± 12%
4. Measured with Rref = 10 kn (± 5%) connected between I ref and VOO; RL = 1,5 kn (± 5%); OUTR
and OUTL short-circuit protected to VSS.
5. Left and right outputs must be driven with identical configuration.
6. Sample tested value only.
7. This timing parameter only applies when no wait states are required; otherwise parameter is invalid.
S. The minimum bus cycle time of four clock periods is for loading all registers except the amplitude
registers.
9. The minimum bus cycle time of 16 clock periods is for loading the amplitude registers. In a
system using OTACK it is possible to achieve minimum times of 500 ns. Without OTACK the
parameter given must be used.
572
May
19851 (
l____
Microprocessor controlled stereo sound generator
S_A_A1_0_9_9______
for sound effects and music synthesis
AD
K
)<
...-tAsc--1
... tcsw--
-tAHW-
~
CS
-tASW-
-twl-I
~
---
-
DTACK
J
tCHW
/
-tBSW-
..
.
tDHW
K
)<
DD-D7
0:{
..
..
tDFW _
..
--(~--Y=
tDRW
I0:{
Fig.3 Bus interface waveforms.
C
IZ
w
~
Il..
o
..J
W
>
W
C
ClK
r'
1
H1GH
l}~'LOw-L
.1
'--7-Z8-7-8-'2
Fig. 4 Clock input waveform.
I
(May 1985
573
SAA1099
APPLICATION INFORMATION
Device operation
The SAA 1099 uses pulse width modulation to achieve amplitude and envelope levels. The twelve
signals are mixed in an analogue format (6 'left' and 6 'right') before leaving the chip. The amplitude
and envelope signals chop the output at a minimum rate of 62,5 kHz, compared with the highest tone
output of 7,81 kHz. Simple external low-pass filtering is used to remove the high frequency components.
Rates quoted are based on the input of a 8 MHz clock.
A data bus based write only structure is used to load the on-board registers. The data bus is used to
load the address for a register, and subsequently the data to that register. Once the address is loaded
multiple data loads to that register can be performed.
The selection of address or data is made by the single address bit AO, as shown in register maps Table 1
and Table 2.
The bus control signals WR and CS are designed to be compatible with a wide range of microprocessors,
a OTACK output is included to optimise the interface with an 568000 series microprocessor. In most
bus cycles OTACK will be returned immediately, this applies to all register address load cycles and all
except amplitude data load cycles. With respect to amplitude data, a number of wait cycles may need
to be performed, depending on the time since the previous amplitude load. OTACK will indicate the
number of required waits.
Register description (see Tables 2 and 3)
The amplitudes are assigned with 'left' and 'right' components in the same byte, on a channel by
channel basis. The spare locations that are left between blocks of registers is to allow for future
expansion, and should be written as zero's. The tone within an octave is defined by eight bits and the
octave by three bits. Note that octaves are paired (0/1,2/3 etc.). The frequency and noise enables are
grouped together for ease of programming. The controls for noise 'colour' (clock rate) are grouped
in one byte.
The envelope registers are positioned in adjacent locations. There are two types of envelope controls,
direct acting controls and buffered controls. The direct acting controls always take immediate effect,
and are:
• Envelope enable (reset)
• Envelops resolution (16/8 level)
The buffered controls are acted upon only at the times shown in Fig. 5 and control selection of:
• Envelope clock source
• Waveform type
• Inverted/non-inverted 'right' component
Table 1 External memory map
select
AO
06
05
a
07
06
05
1
X
X
X
Where X
514
07
= don't care state.
May
19851 (
data bus inputs
04
03
04
A4
03
A3
02
01
00
02
A2
01
A1
00
AO
operations
data for internal registers
internal register address
l____
Microprocessor controlled stereo sound generator
S_A_A_10_9_9______
for sound effects and music synthesis
Table 2 I nternal register map
register
address
e:{
le:{
o
IZ
w
::?!
0..
o
...J
W
>
W
o
07
06
05
data bus inputs
04
03
02
01
00
AR03 AR02 AROl
AROO AL03 AL02 ALOl
01
02
03
04
05
06
07
08
09
OA
08
OC
00
OE
OF
10
11
12
13
14
15
16
1
2
3
4
5
X
X
F07
1
2
3
4
F57
X
X
X
X
X
X
X
X
X
1
2
3
4
5
X
X
F06
1
2
3
4
F56
X
X
012
032
052
X
X
X
X
1
2
3
4
5
X
X
F05
1
2
3
4
F55
X
X
011
031
051
X
FE5
NE5
Nll
1
2
3
4
5
X
X
F04
1
2
3
4
F54
X
X
010
030
050
X
FE4
NE4
Nl0
1
2
3
4
5
X
X
F03
1
2
3
4
F53
X
X
X
X
X
X
FE3
NE3
X
1
2
3
4
5
X
X
F02
1
2
3
4
F52
X
X
002
022
042
X
FE2
NE2
X
1
2
3
4
5
X
X
FOl
1
2
3
4
F51
X
X
001
021
041
X
FEl
NEl
NOl
17
18
19
lA
18
lC
10
lE
IF
X
E07
E17
X
X
X
X
X
X
X
X
E05
E15
X
X
E04
E14
X
X
E03
E13
X
X
E02
E12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EOl
Ell
X
X
RST
X
X
X
X
X
X
X
X
X
DO
operations
ALOO amplitude 0 right channel;
left channel
ampl itude 1 right/left
1
amp I itude 2 right/left
2
amplitude 3 right/left
3
amp I itude 4 right/left
4
amplitude 5 right/left
5
X
X
FOO
frequency of tone 0
frequency of tone 1
1
frequency of tone 2
2
frequency of tone 3
3
frequency of tone 4
4
frequency of tone 5
F50
X
X
000
octave 1 ; octave 0
020
octave 3; octave 2
040
octave 5; octave 4
X
FEO
frequency enable
NEO
noise enable
noise generator 1;
NOO
noise generator 0
X
EOO
envelope generator 0
envelope generator 1
El0
X
X
SE
X
{ frequency reset (all channels)
sound enable (all channels)
X
X
Where:
All don't cares (X) should be written as zero's.
00 to 1F block of registers repeats eight times in the block between addresses 00 to FF (full internal
memory map).
'I (
May 1985
575
_Jl_________
__
SA_A
109_9
APPLICATION INFORMATION (continued)
Table 3 Register description
bit
description
ARn3; ARn2;
ARn1; ARnO
(n = 0,5)
4 bits for amplitude control
of right channel
o 0 0 0 minimum amplitude (off)
1 1 1 1 maximum amplitude
ALn3; ALn2;
ALn1; ALnO
(n 0,5)
4 bits for amplitude control
of left channel
o 0 0 a minimum amplitude (off)
1 1 1 1 maximum ampl itude
Fn7 to FnO
= 0,5)
8 bits for frequency control
of the six frequency generators
a a a a 0 0 0 0 lowest frequency
1 1 1 1 1 1 1 1 highest frequency
On2; On1; Dna
(n = 0,5)
3 bits for octave control
a a a lowest octave (31 Hz to 61 Hz)
001
(61 Hz to 122 Hz)
a 1 0
(122 Hz to 244 Hz)
a 1 1
(245 Hz to 488 Hz)
1 a 0
(489 Hz to 977 Hz)
1 0 1
(978 Hz to 1,95 kHz)
1 10
(1,96 kHzto 3,91 kHz)
1 1 1 highest octave (3,91 kHz to 7,81 kHz)
FEn
frequency enable bit (one tone per generator)
FEn = 0 indicates that frequency 'n' is off
0=
(n
(n
= 0,5)
NEn
(n
= 0,5)
Nn1; NnO
(n = 0,1)
noise enable bit (one tone per generator)
NEn = 0 indicates that noise 'n' is off
2 bits for noise generator control.
These bits select the noise generator rate (noise 'colour')
Nn1 NnO clock frequency
0
31,3 kHz
1
15,6 kHz
1
a
7,6 kHz
1
1
61 Hz to 15,6 kHz (frequency generator 0/3)
o
o
576
l____
Microprocessor controlled stereo sound generator
SA_A_1_0_9_9______
for sound effects and music synthesis
bit
En7;
En5 to EnO
(n = 0,1)
SE
W
o
RST
description
7 bits for envelope control
EnO
left and right component have the same envelope
0
right component has inverse of envelope that is applied to left
1
component
En3 En2 En1
zero ampl itude
0
0
0
0
1
maximum ampl itude
0
0
single decay
1
0
0
1
1
repetitive decay
1
single triangular
0
0
1
repetitive triangular
0
1
1
1
0
single attack
1
1
1
repetitive attack
En4
4 bits for envelope control (maximum frequency = 977 Hz)
0
3 bits for envelope control (maximum frequency = 1,95 kHz)
1
En5
0
internal envelope clock (frequency generator 1 or 4)
1
external envelope clock (address write pulse)
En7
0
reset (no envelope control)
1
envelope control enabled
SE sound enable for all channels
(reset on power-up to 0)
all channels disabled
0
1
all channels enabled
Reset signal to all frequency generators
all generators enabled
all generators reset and synchronized
0
1
Note
All rates given are based on the input of a 8 MHz clock.
I
(May 1985
577
___S_AA_109_9_jl_________________
APPLICATION INFORMATION (continued)
envelope generator inactive
(En7 = 0)
envelope generator active
(En7 = 1)
~f
En3 En2 En1 EnO
~
0000
~
1
a
~~~------~--------------------
1-- (1) --I
-I
(3)
'(2)
o
0
1
0
~
b
~
(4)
(4)
(4)
o
~=========~!
1
0
(2)
c
0
1-- (1)-.1
+--------__1
(3)
o
o
~!(21
1--(1)--1
t
(4)
t
(4)
d
t
(4)
===~===========*, (2)
000
~~
0
,
+-------1
1--0)-1
o
e
I
(3)
~1121
t
1-- 0) --l
(4)
==========~, (2)
1
0
0
~
1-- (1) -I
9
I
+'-----------1
(3)
'(2)
1
0
~I
(4)
(4)
(4)
~===r=====;::===:r===~, (2)
~I
(4)
(4)
Fig. 5 Envelope waveforms.
578
(4)
7Z87813
h
l____
Microprocessor controlled stereo sound generator
S_A_A_10_9_9______
for sound effects and music synthesis
Notes to Fig. 5
(1) The level at this time is under amplitude control only (En7
(2) When the generator is active (En7
= 1) the maximum
= 0; no envelope).
level possible is 7/8ths of the amplitude level.
(3) After position (3) the buffered controls will be acted upon when loaded.
(4) At positions (4) the buffered controls will be acted upon if already loaded.
(5) Waveforms 'a' to 'h' show the left channel (EnO = 0; left and right components have the same
envelope).
Waveform 'i' shows the right channel (EnO = 1; right component inverse of envelope applied to
left).
~------~~__--VOO
OUTPUT
FILTERS
18
LOS
6
OUTPUT
AMPLIFIER
5~O_U_T_L~__~_C=-~__~~~
WR
left channel
output
OTACK
W
address
I I
7Z90787
C
Fig. 6 Typical application circuit diagram.
'I
(May 1985
579
~j
l__
SAA_1300_
TUNER SWITCHING CIRCUIT
The SAA1300 is for switching on and off the supply lines of various circuit parts via an 12 C bussignal.
Furthermore, it can be used to supply current for switching diodes in radio and television tuners. It
contains 5 output stages, which are capable of supplying up to 85 mA in the ON state or sinking up'
to -100 J.l.A in the OFF state.
Current limiting and short-circuit protection are included. The output stages are driven by a shift
register/latch combination which is loaded via data from the 12 C bus. A power-on reset of the latches
ensures the OFF state of the output stages (OUT 2 to OUT 5) without data reception from the 12 C bus.
A subaddressing system allows the connection of up to three circuits on the same 12 C bus lines; one of
the outputs (OUT 1, pin 7) can also be used as an input to select the device via a simple internal A/D
converter.
OUT l O U T 2
OUT 3
OUT 4
OUT 5
Vp
GND
7Z85576.1
Fig. 1 Block diagram.
PACKAGE OUTLINE
9-lead SI L; plastic (SOT142).
I(
June 1987
581
_Jl'---________
__
SA_A130_0
PINNING
pin no.
symbol
function
1
2
3
4
5
6
GND
Vp
OUT5
OUT4
OUT3
OUT2
OUT1
SDA
SCl
ground
positive supply
7
8
9
1
outputs
output and subaddressing input
serial data line } 12C b
serial clock line
us
12C BUS INFORMATION
Address, first byte
a 1 aaa A B a
where,
A
B
function
condition
a
a
0
1
1
1
1
general address
OUT 1 == input
OUT 1 == input
OUT 1 == input
OUT 1 = output
address accepted if VOUT 1 == Va UT l (lOW)
address accepted if VOUT 1 == VOUT H (HIGH)
address accepted if VOUT 1 == VOUT M (MEDIUM)
a
Data, second byte
OUT 5, OUT 4, OUT 3, OUT 2, OUT 1, X, X, X
The 1/0 output stage (OUT 1) is switched as an input stage after a power-on reset. It depends on the
contents of the first data transmission whether the output stage is switched as an output or remains
as an input.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage
Vp
Input voltage range at SDA, SCl
VI
-0,5 to + 6,0 V
Input voltage range at OUT 1
VI
-0,5 to + 12,5 V
Output voltage range at OUT 1 to OUT 5
Va
-0,5 to + 12,5 V
Input current at SDA, Sel
II
max.
13,2 V
20 rnA
Input current at OUT 1
II
max.
20 rnA
Total power dissipation
Ptot
T stg
max.
825 mW
Storage temperature range
Operating ambient temperature range
582
max.
June
19871 (
Tamb
-40 to
+ 125 oC
-20 to + 80 oC
Jl____
S_A_A_13_0_0______
_______T_un_er_sw_itc_hi_ng_ci_rCu_it_____________________
CHARACTERISTICS
Vp = 8 V; Tamb = 25 °C; unless otherwise specified
parameter
symbol
min.
typo
max.
unit
Supply voltage range
Vp
4
8
12
V
Supply current
5 outputs LOW
5 outputs HIGH
IpL
IpH
5
30
10
50
15
70
mA
mA
VPR
Pmax
-
3,5
3,8
V
650
-
mW
VIH
3,0
-
5,5
V
Input voltage LOW
VIL
0
-
1,5
V
Input current HIGH
-IIH
-
-
10
Il A
I nput current LOW
IlA
Supply (pin 2)
Power-on reset level
output stage in "OFF' condition
Maximum power dissipation*
Inputs SDA, SCL (pins 8 and 9)
Input voltage HIGH
IIH
-
-
0,4
Acknowledge sink current
lACK
2,5
-
-
mA
Maximum input frequency
fi max
100
-
-
kHz
Outputs OUT 1 to OUT 5 (pins 3 to 7)
Maximum output current; source: "ON"
10sa
+ 85
-
+ 150
mA
Maximum output current; source: "ON"
Tamb = 80 °C
10so
60
-
-
mA
Output voltage HIGH
at 10so = 85 mA
VOH
Vp-2
-
-
V
Output current; sink "OFF"
10si
-100
-300
-
IlA
Output voltage LOW
at 10si = -100 IlA
VOL
-
-
100
mV
Output voltage MEDIUM
at 10 = 10 mA
VOM
Vp-0,5
-
-
V
OUT 1 used as subaddressing input
Input voltage HIGH (code 1 0)
VOUT1H
0,72 Vp
-
Vp
V
Input voltage MEDIUM (code 1 1)
VOUT1M
0,39 Vp
-
0,61 Vp
V
Input voltage LOW (code 0 1)
VOUT1L
0
-
0,28 Vp
V
Purchase of Philips' 12 C components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system
provided the system conforms to the 12 C specifications defined
by Philips.
* Outputs must not be driven simultaneously at maximum source current.
1(June
1987
583
l___
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
S_A_A_3_0_04
_ __
REMOTE CONTROL TRANSMITTER
GENERAL DESCRIPTION
The SAA3004 transmitter IC is designed for infrared remote control systems. It has a total of 448
commands which are divided into 7 sub-system groups with 64 commands each. The sUb-system code
may be selected by a press button, a slider switch or hard wired.
The SAA3004 generates the pattern for driving the output stage. These patterns are pulse distance
coded. The pulses are infrared flashes or modulated. The transmission mode is defined in conjunction
with the sUb-system address. Modulated pulses allow receivers with narrow-band preamplifiers for
improved noise rejection to be used. Flashed pulses require a wide-band preamplifier within the
receiver.
The SAA3004 has the following features:
• Flashed or modulated transmission
• 7 su b-system addresses
• Up to 64 commands per sub-system address
• High-current remote output at VOO
=6
V (-IOH
= 40 mA)
• Low number of additional components
• Key release detection by toggle bits
• Very low stand-by current «
• Operational current
2 J.LA)
< 2 rnA at 6 V supply
• Wide supply voltage range (4 to 11 V)
• Ceramic resonator controlled frequency (typ. 450 kHz)
• Encapsulation: 20-lead plastic 01 Lor 20-lead plastic mini-pack (SO-20)
PACKAGE OUTLINES
SAA3004P: 20-lead 01 L; plastic (SOT146).
SAA3004T: 20-lead mini-pack; plastic (S020; SOT163A).
'I (
June 1982
585
_Jl________
__
SAA_30_04
z
0
>
cr:
z
:;
cr:
0
SENON
0
13
zN zcry
>
>
cr: cr:
0
z' cr:
cr: >
0
0
14 15
16
0
17
z
CO
>
cr:
0
18 19
20
VDD
SAA3004
10
9
11
I
+
6/9V
VSS
12
ascI
asca
T
W
ceramic
resonator
455 kHz
7ZB567B
Fig. 1 Transmitter with SAA3004.
INPUTS AND OUTPUTS
Key matrix inputs and outputs (DRVON to DRV6N and SENON to SEN6N)
The transmitter keyboard is arranged as a scanned matrix. The matrix consists of 7 driver outputs and
7 sense inputs as shown in Fig. 1. The driver outputs DRVON to DRV6N are open drain N-channel
transistors and they are conductive in the stand-by mode. The 7 sense inputs (SENON to SEN6N) enable
the generation of 56 command codes. With 2 external diodes all 64 commands are addressable.The sense
inputs have P-channel pull-up transistors, so that they are HIGH until they are pulled LOW by connecting them to an output via a key depression to initiate a code transmission.
Address mode input (ADRM)
The sub-system address and the transmission mode are defined by connecting the ADRM input to one
or more driver outputs (DRVON to DRV6N) of the key matrix. If more than one driver is connected
to ADRM, they must be decoupled by a diode. This allows the definition of seven sub-system addresses as shown in Table 3. If driver DRV6N is connected to ADRM the data output format of REMO is
modulated or if not connected, flashed.
The ADRM input has switched pull-up and pull-down loads. In the stand-by mode only the pull-down
device is active. Whether ADRM is open (sub-system address 0, flashed mode) or connected to the
driver outputs, this input is LOW and will not cause unwanted dissipation. When the transmitter
becomes active by presssing a key, the pull-down device is switched off and the pull-up device is
switched on, so that the applied driver signals are sensed for the decoding of the sub-system address
and the mode of transmission.
586
June
1982] (
Remote control transmitter
l__
SA_A_3_0_0_4_ __
The arrangement of the sub-system address coding is such that only the driver DRVnN with the highest
number (n) defines the sub-system address, e.g. if driver DRV2N and DRV4N are connected to ADRM,
only DRV4N wi II define the sub-system address. This option can be used in transmitters for more than
one sUb-system address. The transmitter may be hard-wired for sub-system address 2 by connecting
DRV1 N to ADRM. If now DRV3N is added to ADRM by a key or a switch, the transmitted sub-system
address changes to 4.
A change of the sub-system address will not start a transmission.
Remote control signal output (REMO)
The REMO signal output stage is a push-pull type. In the HIGH state a bipolar emitter-follower allows
a high output current. The timing of the data output format is listed in Tables 1 and 2.
The information is defined by the distance tb between the leading edges of the flashed pulses or the
first edge of the modulated pulses (see Fig. 3).
The format of the output data is given in Figs 2 and 3. In the flashed transmission mode the data word
starts with two toggle bits T1 and TO, followed by three bits for defining the sub-system address S2, S1
and SO, and six bits F, E, D, C, S and A, which are defined by the selected key.
In the modulated transmission mode the first toggle bit T1 is replaced by a constant reference time bit
(REF). This can be used as a reference time for the decoding sequence.
~
The toggle bits function as an indication for the decoder that the next instruction has to be considered
as a new command.
~
The codes for the sUb-system address and the selected key are given in Tables 3 and 4.
~
~
~
Oscillator input/output (OSCI and OSCO)
g
The external components must be connected to these pins when using an oscillator with a ceramic
resonator. The oscillator frequency may vary between 400 kHz and 500 kHz as defined by the resonator.
>
~
FUNCTIONAL DESCRIPTION
Il..
w
Keyboard operation
In the stand-by mode all drivers (DRVON to DRV6N) are on. Whenever a key is pressed, one or more
of the sense inputs (SENnN) are tied to ground. This will start the power-up sequence. First the oscillator is activated and after the debounce time tDS (see Fig. 4) the output drivers (DRVON to DRV6N)
become active successively.
Within the first scan cycle the transmission mode, the applied sUb-system address and the selected
command code are sensed and loaded into an internal data latch. In contradiction to the command
code the sub-system address is sensed only within the first scan cyCle. If the applied sUb-system
address is changed while the command key is pressed, the transmitted sub-system address is not altered.
I n a mu Itiple key-stroke sequence (see Fig. 5) the command code is always altered in accordance with
the sensed key.
Multiple key-stroke protection
The keyboard is protected against multiple key-strokes. If more than one key is pressed at the same time,
the circuit will not generate a new output at REMO (see Fig. 5). In case of a mUltiple key-stroke the
scan repetition rate is increased to detect the release of a key as soon as possible.
There are two restrictions caused by the special structure of the keyboard matrix:
"I (June
1982
587
___
SAA_300_4_Jl_________________
FUNCTIONAL DESCRIPTION (continued)
- The keys switching to ground (code numbers 7, 15,23,31,39,47,55 and 63) and the keys
connected to 5EN5N and 5EN6N are not covered completely by the multiple key protection. If one
sense input is switched to ground, further keys on the same sense line are ignored.
- 5EN5N and 5EN6N are not protected against multiple key-stroke on the same driver line, because
this condition has been used for the definition of additional codes (code numbers 56 to 63).
Output sequence (data format)
The output operation will start when the selected code is found. A burst of pulses, including the latched
address and command codes, is generated at the output REMO as long as a key is pressed. The format
of the output pulse train is given in Figs 2 and 3. The operation is terminated by releasing the key or if
more than one key is pressed at the same time. Once a sequence is started, the transmitted words will
always be completed after the key is released.
The toggle bits TO and T1 are incremented if the key is released for a minimum time tREL (see Fig. 4).
The toggle bits remain unchanged within a multiple key-stroke sequence.
-,
H
REMO
L
T1
0
bit data -
TO
1
52
0
51
50
0
0
0
E
0
B
0
C
A
0
T1
0
(a)
H
REMO
-
L
bit
I-
I
tw
REF
TO
-I
I I I I I I I II I
52
0
data -
51
50
0
E
0
0
0
C
B
0
I I
A
0
REF
7Z85675
(b)
Fig. 2 Data format of REMO output; REF = reference time; TO and T1 = toggle bits; 50, 51 and 52 =
system address; A, B, C, D, E and F = command bits.
(a) flashed mode: transmission with 2 toggle bits and 3 address bits, followed by 6 command bits
(pulses are flashed).
(b) modulated mode: transmission with reference time, 1 toggle bit and 3 address bits, followed by 6
command bits (pulses are modulated).
REMO
(1)
:Jl
-1 .
---~
1
---~
REMO
(2)
L
-I
tb
-"
H
~~-t'MH
-tML
-
-tM
7Z85676
tpw
-
(1) Flashed pulse.
(2) Modulated pulse (tpw
= (5 x tM) + tMH'
Fig.3 REMO output waveform.
588
June
19821 (
DEVELOPMENT DATA
closed
KEY
released
key bouncing
I
JlllJ
I
l
\
off
I-IREL-I
[1111
i
:JJ
new key
[- - - - - - -,.-----(- - -
scan
CD
3
o
a:-
.
S
::J
DRVnN
r+
--I
lOB
£
1_
~
new word
Q)
H
REMO
::J
1_ 1ST __lL.....1L.....1L.....1L.....1I-1L.......1L.....1L-1L.-.1L......1L.-.11
OSCO
H
JUlVlIIIIIIIIIIIIIIIIIIIIIIII
'L.....IL......JL.....IL......JL.....IL..... L ...... ,~~..... L - - ' L -.... L _ _ _ _ _ _... L
OSCILLATOR ACTIVE
3
;:j:
..... L--'L.....J,L-.. ' -..... L ...... ,~'--
~
IIIIIIIIIIIIIIIIIIIIIIIIIIII
7Z85674
Fig. 4 Single key-stroke sequence.
Oebounce time: tOB = 4 to 9 x To.
Start time: tST = 5 to 10 x To.
Minimum release time: tREL = To.
Word distance: tWo
closed
key A decoded as LOW
/
KEY A
released
closed
KEYB
released
',,,,
/scan
off
DRVnN
H
REMO
C-
C
::J
CD
CO
(Xl
I\.)
"
word key A
OSCO
H
word key A
J11lVIIIIIIIIIIIIIIIIIIIIIIIIIIII
word key B
OSCILLATOR ACTIVE
OOI//I7IZ/II//IIIOIIIIOOIIJ
7Z85673
Fig. 5 Multiple key-stroke sequence.
Scan rate mUltiple key-stroke: tSM = 6 to 10 x To.
For tOB, tST and tw see Fig. 4.
CJ)
»
»c.u
o
o
~
(J1
CO
CD
___
SAA_30_04_Jl~________________
Table 1 Pulse train timing
mode
To
ms
tp
tM
tML
tMH
jlS
jlS
jlS
jlS
flashed
2,53
-
2,53
8,8
-
-
modulated
26,4
17,6
8,8
fosc
455 kHz
tp
4 x tosc
121
121
tosc = 2,2 jlS
flashed pulse width
tM
12 x tosc
modu lation period
tML
8 x tosc
modu lation period LOW
tMH
To
4 x tosc
1152 x tosc
basic unit of pulse distance
tw
55296 x tosc
word distance
modulation period HIGH
Table 2 Pulse train separation (tb)
590
tw
ms
code
tb
logic "0"
2 x To
logic "1"
3 x To
reference time
3x To
toggle bit time
2 x To or 3 x To
June
19821 (
l____
Remote control transmitter
SA_A_3_0_0_4______
Table 3 Transmission mode and sUb-system address selection
The sub-system address and the transmission mode are defined by connecting the ADRM input to one
or more driver outputs (DRVON to DRV6N) of the key matrix. If more than one driver is connected to
ADRM, they must be decoupled by a diode.
F
L
A
S
H
E
D
M
0
D
U
e:(
le:(
C
IZ
L
A
T
E
D
driver D RVnN
for n =
sub-system
address
mode
# S2
S1
SO
a
1
1
1
2
3
4
5
6
a
1
2
3
4
5
6
1
a
a
a
a
a
a
1
1
a
a
1
1
1
1
a
a
a
a
a
a
1
1
a
a
1
1
a
a
1
a
1
a
1
3
2
4
5
6
0
x 0
x x 0
X X X 0
x x x x 0
x X x x x
1
0
1
0
a
1
a
0
0
x 0
x x 0
X X X 0
x x x x 0
x X x x x
1
a
1
0
0
0
0
0
0
o
blank
= connected to ADRM
= not connected
X
=
to ADRM
don't care
w
~
o
..J
W
>
W
C
Table 4 Key codes
matrix
drive
matrix
sense
DRVON
DRV1N
DRV2N
DRV3N
DRV4N
DRV5N
DRV6N
VSS
*
*
*
*
*
*
SENON
SENON
SENON
SENON
SENON
SENON
SENON
SENON
*
SEN1N
SEN2N
SEN3N
SEN4N
SEN5N
SEN6N
SEN5N
and
SEN6N
F
E
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
code
D
C
B A
matrix
position
a
a
a
a
a
a
a
a
a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a
1
1
1
1
a
1
a a
a 1
1 a
**
**
**
**
**
**
8 to
16 to
24 to
32 to
40 to
48 to
1
1
1
**
56 to 63
1
1
1
1
a
1
2
3
4
5
6
7
1
15
23
31
39
47
55
* The complete matrix drive as shown above for SENON is also applicable for the matrix sense inputs
SEN 1N to SEN6N and the combined SEN5N/SEN6N.
** The C, B and A codes are identical to SENON as given above.
I(
August 1982
591
SAA3004
Jl
PINNING
REMO
key matrix sense inputs
DRV3N
SEN6N
SEN5N
SEN4N
SEN3N
SEN2N
SEN1N
SENON
DRV2N
9
ADRM
address mode control input
DRV6N
DRV5N
DRV4N
10 VSS
11 OSCI
ground
DRVQN
12 OSCO
oscillator output
asca
13
14
15
16
17
18
19
key matrix drive outputs
DRV1N
vss
11
remote data output
1
2
3
4
5
6
7
8
V DD
ascI
7Z85677
Fig.6 Pinning diagram.
DRVON
DRV1 N
DRV2N
DRV3N
DRV4N
DRV5N
DRV6N
20 VDD
oscillator input
positive supply
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage range
VDD'
-0,5 to +15
V
Input voltage range
VI
-0,5 to VDD +0,5
V
Output voltage range
Vo
D.C. current into any input or output
±I
-0,5 to VDD +0,5
max.
Peak R EMO output current
du ri ng 10 /lS; duty factor = 1%
-I(REMO)M
Ptot
T stg
Tamb
Power dissipation per package
for T amb = -20 to + 70 0 C
Storage temperature range
Operating ambient temperature range
592
June
19821 (
V
10
mA
max.
300
mA
max.
200
-55 to +150
mW
oC
-20 to +70
°C
SAA3004
Remote control transmitter
CHARACTERISTICS
VSS
=0
V; T amb
= 25 °C; unless otherwise specified
VOO
(V)
symbol
min.
typo
max.
unit
Supply voltage
Tamb = 0 to +70 °C
-
VOD
4
-
11
V
Supply current; active
fosc = 455 kHz;
REMO output unloaded
6
100
100
-
1
3
-
9
-
mA
mA
100
100
-
-
9
-
-
2
2
J.lA
J.lA
4 to 11
fosc
400
-
500
kHz
I nput voltage LOW
4 to 11
VIL
-
-
4 to 11
0,8 x VOO -
0,2 x VOO
-
V
I nput voltage H IG H
J.lA
J.lA
parameter
Supply current; inactive
(stand-by mode)
Tamb = 25 °C
asci Ilator frequency
(ceramic resonator)
6
Keyboard matrix
Inputs SENON to SEN6N
~
«
c
IZ
w
2
Q.
o
...J
W
>
W
C
Input current
VI = 0 V
4
11
VIH
-II
-II
Input leakage current
VI = VOO
Outputs ORVON to ORV6N
11
Output voltage liON"
10:: 0,1 mA
10 = 1,0 mA
Output cu rrent "0 F F"
Va = 11 V
-
V
10
30
-
100
300
I,
-
-
1
J.lA
4
11
VOL
VOL
-
-
0,3
0,5
V
V
11
10
-
-
10
J.lA
-
VIL
-
-
VIH
0,2 x VOO
0,8 x VOO
-
V
-
Pu II-up active
stand-by voltage: 0 V
4
11
IlL
IlL
10
30
-
100
300
J.lA
J.lA
Pu II-down active
stand-by voltage: VOO
4
11
IIH
IIH
10
30
-
100
300
J.lA
J.lA
Control input ADRM
I nput voltage LOW
I nput voltage HI G H
V
I nput current (switched Pand N-channel pull-up/
pull-down)
1(June
1982
593
SAA3004
CHARACTERISTICS (continued)
VSS
= a V; Tamb = 25 oC; unless otherwise specified
VOO
(V)
symbol
min.
typo
max.
unit
6
9
VOH
VOH
3
6
-
-
V
V
6
9
VOL
VOL
-
-
-
-
0,2
0,1
V
V
I nput current
ascI at VOO
6
II
0,8
-
2,7
Il A
Output voltage HIGH
-IOL = 0,1 mA
6
VOH
-
-
VOO-0,6
V
Output voltage LOW
IOH = 0,1 mA
6
VOL
-
-
0,6
V
parameter
Data output R EMO
Output voltage HIGH
-IOH = 40 mA
Output voltage LOW
IOL = 0,3 mA
Oscillator
594
June
19821 (
DEVELOPMENT DATA
SAA3006
This data sheet contains advance information and
specifications are subject to change without notice.
LOW VOLTAGE INFRARED REMOTE CONTROL
TRANSMITTER (RC-5)
GENERAL DESCRIPTION
The SAA3006 is intended as a general purpose (RC-5) infrared remote control system for use where
only low supply voltages are available. The device can generate 2048 different commands and utilizes a
keyboard with a single-pole switch per key. The commands are arranged so that 32 systems can be
addressed, each system containing 64 different commands.
The circuit response to legal (one key pressed at a time) and illegal (more than one key pressed at a
time) keyboard operation is specified later in this publication (see KEY ACTIVITIES).
Features
• Low supply voltage requirements
• Very low current consumption
• For infrared transmission link
• Transmitter for 32 x 64 commands
• One transmitter controls 32 systems
• Transmission biphase technique
• Short transmission times; speed-up of system reaction time
• Single-pin oscillator input
• I nput protection
• Test mode facility
QUICK REFERENCE DATA
Supply voltage range
VDO
2 to 7
V
I nput voltage range
VI
0,5 to (VOO + 0,5)
V*
Input current
± II
max. 10
rnA
Output voltage range
V*
Va
-0,5 to (VOO + 0,5)
Output current
±IO
max. 10
Operating ambient temperature range
Tamb -25 to +85
rnA
oC
* VOO + 0,5 V not to exceed 9 V.
PACKAGE OUTLINE
28-lead OIL; plastic (SOT117).
1(JUlY
1983
595
SAA3006
SAA3006
OSC
18
3x2 1
OSC.
TPl
20
TP2
19
SSM
2
TEST
MODE
}
I
Z3
li
~
MODE
SELECTION
DECODER f---
I
CONTROL
UNIT
6
Z2
5
Zl
4
ZO
3
RESET
MASTER
GENERATOR
f--
1-1--
X7
1
X6
27
X5
26
X4
25
X3
24
X2
23
Xl
22
XO
21
KEYBOARD
ENCODER
~I--
COMMAND
AND
SYSTEM
ADDRESS
LATCH
I
PARALLEL
TO SERIAL
CONVERTER
OUTPUT
8
DATA
7
MDATA
KEYBOARD
DRIVER
DECODER
~
14
28
I
I
VSS
Fig. 1 Block diagram.
596
July
2 13
DIVIDER
19831 (
V DD
17
ORO
16
DRl
15
DR2
13
DR3
12
DR4
11
DR5
10
DR6
9
DR7
7Z90143
SAA3006
Low voltage infrared remote control transmitter (RC-5)
PINNING
14
28
1
xo
3
4
5
6
ZO
Z1
Z2
Z3
TP1
2
SSM
TP2
20
19
TP1
TP2
test input
test input/output
18
OSC
oscillator input
17
16
15
13
12
11
10
9
DRO
DR1
DR2
DR3
DR4
DR5
DR6
DR7
scan driver output with open
drain N-channel transistors
VDD
X6
X5
X4
X3
X2
X1
SAA3006
DR6
asc
«
«C
II-
zw
:!:
Q.
0
DR4
DRO
DR3
DR1
vss
DR2
7Z90139
..J
w
>
w
C
negative supply (ground)
positive supply
VSS
VDD
XO
X1
X2
X3
X4
X5
X6
X7
Fig.2 Pinning diagram.
21
22
23
24
25
26
27
7
8
MDATA
DATA
keyboard command inputs with
P-channel pull-up transistors
I
keyboard system inputs with
P-channel pull-up transistors
system mode selection input
}
remote signal outputs
(3-state outputs)
1(JUlY
1983
597
SAA3006
t17 t16
0
a:
0
~7
~5
(3)
~6
"-
1\5
~4 ~3
I" I'\.
~14 ~3 ~12
~2
I'\.
~1
I'\.
~O
23
r\31 1\30 f\29 1\.28 ~27 ~26 ",25 ~24
24
~39 1\38 ~37 1',,36 ~35 1',,34 ~33 ~32
25
~47 ~46 ~45 ",44 ~43 [\42 [\41 ,,40
26
f\
49 ~48
1',,63 [\62 ,,61 [\60 ,,59 [\58 [\57 ,,56
~3 ~2 ~1 ,,0
~7 1\6 1\5 1'4
I, I\,
I,
1\15 ~14 1\13
1'\
~2 1\ 11 ~10
I"
1\23 ~22 1'\.21 1'\.20 ,,19 ~18
31
"-
30
\.
29
'\.
28
'\
27
"-
26
'\
~7
[\16
5
25
24
'\,
0
'
W
o
The X-lines are active HIGH in the quiescent state; the pull-up transistors of the Z-lines are switched off
and the inputs are disabled. Only legal key operation in the X-D R matrix starts the debounce cycle.
When the contact is made for two bit times without interruption, the oscillator-enable signal is latched
and the key may be released. Interruption within the two bit times resets the internal action. At the
end of the debounce time, the pull-up transistors in the X-lines are switched off, those in the Z-lines
are switched on during the first scan cycle. The wired connection in the Z-matrix is then translated
into a system address number and stored in the system address latch. At the end of the first scan
cycle the pull-up transistors in the Z-lines are switched off and the inputs are disabled again, while the
transistors in the X-lines are switched on. The second scan cycle produces the command number
which, after latching, is transmitted together with the system address number.
Inputs
The command inputs XO to X7 carry a logical '1' in the quiescent state by means of an internal pull-up
transistor. When SSM is LOW, the system inputs ZO to Z3 also carry a logical '1' in the quiescent state
by means of an internal pull-up transistor.
When SSM is HIGH, the transistors are switched off and no current flows via the wired connection in
the Z-DR matrix.
Oscillator
The oscillator is formed by a ceramic resonator (catalogue number 2422 540 98021 or equivalent)
feeding the single-pin input OSC. Direct connection is made for supply voltages in the range 2 to
5,25 V but it is necessary to fit a 10 kQ resistor in series with the resonator when using supply voltages
in the range 2,6 to 7 V.
Key-release detection
An extra control bit is added which will be complemented after key-release. In this way the decoder
gets an indication that shows if the next code is to be considered as a new command. This is very
important for multi-digit entry (e.g. by channel numbers or Teletext/Viewdata pages). The control bit
will only be complemented after finishing at least one code transmission. The scan cycles are repeated
before every code transmission, so that, even by 'take-over' of key operation during code transmission,
the correct system and command numbers are generated.
1(JUlY
1983
599
SAA3006
FUNCTIONAL DESCRIPTION (continued)
Outputs
The output DATA carries the generated information according to the format given in Fig. 4 and Tables
2 and 3. The code is transmitted in biphase; definitions of logical '1' and '0' are given in Fig. 5.
The code consists of four parts:
• Start part formed by 2 bits (two times a logical '1');
• Control part formed by 1 bit;
• System part formed by 5 bits;
• Command part formed by 6 bits.
The output MDATA carries the same information as output DATA but is modulated on a carrier frequency of 1/12 of the oscillator frequency, so that each bit is presented as a burst of 32 pulses. To
reduce power consumption, the carrier frequency has a 25% duty cycle.
In the quiescent state, both outputs are non-conducting (3-state outputs). The scan drivers DRO to
DR7 are of the open drain N-channel type and are conducting in the quiescent state of the circuit. After
a legal key operation all the driver outputs go into the high ohmic state; a scanning procedure is then
started so that the outputs are switched into the conducting state one after the other.
Reset action
The circuit will be reset immediately when a key release occurs during:
• debounce time;
• between two codes.
When a key release occurs during scanning of the matrix, a reset
~ction
will be accomplished if:
• the key is released while one of the driver outputs is in the low-ohmic '0' state;
• the key is released before detection of that key;
• there is no wired connection in the Z-DR matrix while SSM is HIGH.
Test pin
The test pins TP1 and TP2 are used for testing in conjunction with inputs Z2 and Z3 as shown in Table 1.
Table 1 Test functions
TPl
600
TP2
Z2
LOW
LOW
matrix input
matrix input
LOW
HIGH
matrix input
matrix input
HIGH
output fOSC 6
HIGH
6
July
output fOSC
19831 (
Z3
function
normal
scan + output frequency
six times faster than normal
LOW
LOW
reset
HIGH
HIGH
output frequency 3 x 27
faster than normal
l____
Low voltage infrared remote control transmitter (RC-5)
S_A_A_30_0_6______
KEY ACTIVITIES
Every connection of one X-input and one DR-output is recognized as a legal keyboard operation and
causes the device to generate the corresponding code.
Activating more than one X-input at a time is an illegal keyboard operation and no circuit action is
taken (oscillator does not start).
When SSM is LOW, every connection of one Z-input and one DR-output is recognized as a legal keyboard operation and causes the device to generate the corresponding code.
Activating two or more Z-inputs, or Z-inputs and X-inputs, at one time is an illegal keyboard operation
and no circuit action is taken.
When SSM is HIGH, a wired connection must be made between a Z-input and a DR-output. If no
connection is made, the code is not generated.
When one X or Z-input is connected to more than one 0 R-output, the last scan signal is considered
legal.
The maximum allowable value of the contact series resistance of the keyboard switches is 7 kn.
~
«
c
1 CODE
debounce
MSB
IZ
::iE
Q.
o
..I
LSB
LSB MSB
w
--1- command_
system
address bits
1-- control bit
_
start
bits
W
>
W
C
2 bit
times
1_---
data word time = 14 bit times
2 CODES SUCCESSIVELY
I~
stan
1••- - - - -
repetition time = 64 bit times - - - - ..
I
-;~:e
7Z90142
Fig.4 DATA output format (RC-5).
digital '1'
-lbittime-
t=t~
digital '0'
7 Z82856
Fig. 5 Biphase transmission code; 1 bit time:::: 3 X 2 8 X T asc
(typically 1,778 ms) where T asc is the oscillator period time.
'] (JUlY
1983
601
_Jl"'---________
__
SA_A30_06
Table 2 Command matrix X-DR
x ..
0
0
1
2
3
4
5
6
7
2
3
4
•
•
10
6
7
0
•
•
9
5
•
•
•
•
•
•
•
•
•
8
1
•
•
•
•
•
•
•
11
12
13
14
15
•
•
•
16
17
•
•
18
19
•
2
•
•
•
•
20
3
•
•
•
•
21
4
•
•
•
•
•
22
23
•
24
•
•
•
25
26
27
•
28
•
29
•
•
30
31
602
1
July
19831 (
command bits
DR-lines
DR ..
X-lines
code
no.
•
•
•
•
•
c..
5
•
•
•
•
6
•
•
•
•
7
•
•
•
•
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
1
0
1
1
0
0
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
0
0
1
1
1
1
1
SAA3006
Low voltage infrared remote control transmitter (RC-5)
code
no.
a 1 2 3 4
32
33
34
35
36
37
38
39
«
I«
o
I-
2
w
:E
40
41
42
43
44
45
46
47
Q.
o..J
W
>
W
C
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
DR-lines
DR ..
X-lines
X ..
5
6
7
•
•
•
•
•
•
•
•
3
2
•
a
1 a
1 a
1 a
1 a
1 a
1 a
1 a
a
a
a
a
a
a
a
a
a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a
1
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
1
1
•
•
•
a
1
1
1
1
a
1
1
1
1
a
1 0
1
1
1
1
•
•
•
•
•
1
1
1
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a
1
1
1
1
1
•
a
a
1 a
1 a
1
1
1
•
1
1 1 a a
0
1
1
•
0
1 0
1 0
1
•
1
1 1 a a a a
1 1 a a a 1
1 1 a a 1 a
1 1 a a 1 1
1 1 a 1 a a
•
•
•
1
1 a 1 a a a
1 a 1 a a 1
1 a 1 a 1 a
•
•
•
•
•
•
•
•
•
•
a
5 4
•
•
•
•
•
•
•
•
c..
a 1 2 3 4 5 6 7
•
•
•
•
•
•
command bits
1
1
1
1
1
1(JUlY
1983
1
1
603
_Jl'--________
__
SAA_300_6
Table 3 System matrix Z-DR
0
1
2
1
2
3
4
5
6
7
9
0
•
•
•
8
•
•
•
•
•
10
11
12
13
1
•
•
2
•
•
3
•
•
4
•
•
•
•
14
15
•
•
•
•
•
•
•
•
16
17
18
19
20
21
22
23
•
•
•
•
24
25
26
•
27
•
•
28
29
•
30
•
31
604
3
•
•
•
•
•
•
•
•
0
July
19831 (
system bits
S..
DR-lines
DR ..
Z-lines
Z..
system
no.
•
•
•
•
•
•
•
•
•
5
•
•
•
•
6
•
•
•
•
7
•
•
•
•
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
0
1
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
l____
Low voltage infrared remote control transmitter (RC-5)
S_A_A_30_0_6______
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage range with respect to VSS
8,5 V
VDD
-0,5 to
-0,5 to (VDD +0,5) V*
I nput voltage range
VI
Input current
+11
max.
Output voltage range
Vo
-0,5 to (VDD +0,5) V*
Output cu rrent
+10
max.
Power dissipation output OSC
Po
Po
max.
50 mW
Power dissipation per output (all other outputs)
max.
100 mW
Total power dissipation per package
Ptot
max.
Tamb
T stg
-25
to
-55
to
Operating ambient temperature range
Storage temperature range
10 mA
10 mA
200 mW
+85
0
C
+ 150 oC
HANDLING
«
«
C
Inputs and outputs are protected against electrostatic charge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to hand I ing MOS devices (see "Handling MOS Devices").
IIZ
w
:E
c..
o
...J
W
>
W
C
* VDD + 0,5 V not to exceed 9 V.
1(JUlY
1983
605
_Jl'---________
__
SAA_300_6
CHARACTERISTICS
VSS = 0 V; Tamb = -25 to 85 °C unless otherwise specified
min.
typo
max.
unit
parameter
VDO (V)
symbol
Supply voltage
-
VOO
2
-
7
V
Supply current
at 10 = rnA for all outputs;
XO to X7 and Z3 at VOO;
all other inputs at VOO or VSS;
excluding leakage current from
open drain N-channeloutputs;
Tamb = 25 °C
7
100
-
-
10
/lA
Input current (each input) at
V I = V; TP = SSM = LOW
2 to 7
-II
10
-
600
/lA
I nput voltage HI G H
2 to 7
VIH
0,7 x VOO -
VOO
V
Input voltage LOW
2 to 7
VIL
a
-
0,3 x VOO
V
1
/lA
1
/lA
a
Inputs
Keyboard inputs X and Z with
P-channel pull-up transistors
a
Input leakage current
at Tamb = 25 oC; TP = HIGH;
VI = 7 V
-IIR
-
-
IIR
VI =OV
~
SSM, TP1 and TP2
Input voltage HIGH
2 to 7
VIH
0,7 x VOO
-
VOO
V
I nput voltage LOW
2 to 7
VIL
a
-
0,3 x VOO
V
IIR
-
/lA
-IIR
-
1
-
1
/lA
-II
-
-
2
/lA
Input leakage current
at Tamb = 25 oC;
VI =7V
VI =OV
OSC
Input leakage current
at Tamb = 25 oC; VI = V;
TP1 = HIGH; Z2 = Z3 = LOW
a
606
July
19831 (
2 to 7
l____
Low voltage infrared remote control transmitter (RC-5)
S_A_A_3_00_6______
VDD (V)
symbol
Output voltage HIGH
at -IOH = 0,4 mA
2 to 7
VOH
Output voltage LOW
at IOL = 0,6 mA
2 to 7
VOL
parameter
min.
typo
max.
unit
-
-
V
-
0,3
V
Outputs
DATA and MDATA
Output leakage current at:
VO= 7V
VO=OV
Tamb = 25 oC;
VO= 7V
VO=OV
VDD -0,3
-
lOR
-
-
10
p.A
-lOR
-
-
20
p.A
lOR
-
-
1
p.A
-lOR
-
-
2
p.A
ORO to DR7, TP2
~
<{
C
I-
2
w
:E
~
o
Output voltage LOW
at IOL = 0,3 mA
2 to 7
VOL
-
-
0,3
V
Output leakage current
at Vo = 7 V
7
lOR
-
-
10
p.A
lOR
-
-
1
p.A
7
IOSC
4,5
-
30
p.A
Maximum oscillator frequency
at CL = 40 pF (Figs 6 and 7)
2
fOSC
-
-
450
kHz
Free-running oscillator frequency
at Tamb = 25 °C
2
fOSC
10
-
120
kHz
at Vo = 7 V
Tamb = 25 °C
OSC
..J
W
Oscillator current at OSC = VDD
W
Oscillator
>
C
7 Z82857
1\,
normalized
frequency
V DD
SSM
\
JUUl
typ
I"f'
2
OSC
XO
....... i'...
..........
ZO
t- to-
DRO
o
o
50
C
L
(pF)
100
Fig.6 Typical normalized input
frequency as a function of the
load (keyboard) capacitance.
7Z90140
18
21
8
DATA
SAA3006
3
17
Fig. 7 Test circuit
for measurement of
maximum oscillator
frequency.
'] (JUlY
1983
607
l____
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
S_A_A_30_0_7______
INFRARED REMOTE CONTROL TRANSMITTER (LOW VOLTAGE)
GENERAL DESCRIPTION
The SAA3007 transmitter I C for infrared remote control systems has a capacity for 1280 commands
arranged in 20 subsystem address groups of 64 commands each. The subsystem address may be
selected by press-button or slider switches, or be hard-wired.
Commands are transmitted in patterns of pulses coded by the pulse spacing. The pulses can be
infrared flashed (single pulse) or modulated. Flashed infrared transmissions require a wideband
preamplifier at the receiver, but modulated transmissions allow a narrow band receiver to be used
for improved noise rejection. The modulation frequency of the SAA3007 is 455 kHz which allows
disturbance-free infrared operation in the presence of 10- 100 kHz fluorescent lamps.
Features
• Flashed or modulated transmission modes
• Immune from fluorescent lamp disturbance in modulated mode
• Supply voltage range 2 V to 6,5 V
• 40 mA output current capability
• Very low standby current « 4 J.l.A at VOO = 6 V)
• Up to 20 subsystem address groups
• Up to 64 commands per subsystem address
}
up to 1280 commands
• Requires few additional components
PACKAGE OUTLINES
SAA3007P: 20-lead 01 L; plastic (SOT146).
SAA3007T: 20-lead mini-pack; plastic (S020; SOT163A).
1
(october 1987
609
_-SA-A30-07-Jl--_______
z0 z Nz (')
z z z z
;; > > >o::t >LO >CO
>
0:
0:
0:
0:
0:
0:
0:
0
SENON
~
~ ~
/
7/
/
/23 /
/31 /
/39 /'
/47 /
[{55 /
/'
?
/'
~ ~ / ~ /'
~ ~ / ~ f
/15
~ ~
~ ~
?O
SEN1N
/8
SEN2N
/16
SEN3N
/24
~ ~ ~32
~ ~ ~40
/
If f
~
~~3 ?)
~ ~ ~48
?
~) ~) ?) ~) ~)
~{6
(
(
1 1 1 1
([
lI!~
~
~
?
-
]>
SEN4N
SEN5N
SEN6N
I
0
0
0
0
0
0
13 14 15 16 17 18 19
COY89A(D1' 1;
MI
7
6
1
5
SAA3007
BC368
3 to 6V-c.:!:
4
3
10
2
VSS
"
~
I
11
9
12
OSCI 270kn OSCO
ADRM
subsystem
address/
mode selection
VDD
20
8
-c::}
100 pF
l
HD~
ceramic
resonator
455 kHz
~120 pF
7Z974BI.1
Fig. 1 SAA3007 application example.
PINNING
1.
REMO
DRV3N
2.
3.
4.
5.
6.
7.
8.
SEN6N
SEN5N
SEN4N
SEN3N
SEN2N
SEN1N
SENON
DRV2N
9. ADRM
VDD
DRV6N
DRV5N
DRV4N
SEN2N
SAA3007
6
DRV1N
DRVON
osco
Vss
7Z974B2
Fig.2 Pinning diagram.
610
October
19871 (
remote data output
1
I
sense inputs from key matrix
address/mode control input
10. VSS
ground (0 V)
11. ascI
oscillator input
12. OSCO
osci Ilator output
13.
14.
15.
16.
17.
18.
19.
DRVON
DRV1N
DRV2N
DRV3N
DRV4N
DRV5N
DRV6N
20.
VDD
1
drive outputs to key matrix
positive supply voltage
Infrared remote control transmitter (low voltage)
l
SAA3007
'---------------------------
FUNCTIONAL DESCRIPTION
Key matrix (ORVON - ORV6N and SENON - SEN6N)
The transmitter keyboard is arranged as a scanned matrix with seven driver lines (0 RVON to 0 RV6N)
and seven sensing lines (SENON to SEN6N) as shown in Fig. 1. The matrix allows generation of 56
command codes per subsystem address, with triple contacts all 64 commands are addressable, giving
a maximum possibility of 1280 commands.
Lines ORVON to ORV6N are driven by open drain N-channel transistors (conductive in standby mode).
The sense lines go to P-channel pull-up transistors, so that they are HIGH until they are pulled LOW
by key contact with a driver line. This key operation initiates a code transmission.
The maximum allowable value of contact series resistance for keyboard switches in the ON-state is
7 kn.
Address/mode input (AORM)
Subsystem addresses are defined by connecting one or two of the key matrix driver lines (ORVON to
ORV6N) to the AORM input. This allows up to 20 subsystem addresses to be generated for the REMO
output (bits S3, S2, S1 and SO) as shown in Table 1 and Fig. 3.
«
«
C
IIZ
w
:E
D..
o...J
W
>
w
Q
The transmission mode is defined by the ORV6N to AORM connection as follows:
ORV6N not connected to AORM
Flashed mode
Modulated mode ORV6N connected to AORM
When more than one connection is made to AORM then all connections should be decoupled using
diodes.
The AORM input has switched pull-up and pull-down loads. In the standby mode only 'pull-down'
is active and AORM is held LOW (this condition is independent of AORM circuit configuration and
minimizes power loss in the standby mode).
When a key is pressed the transmitter becomes active, 'pull-down' is switched off, 'pull-up' is switched
on and the driver line signals are sensed for the subsystem address coding.
The subsystem address is sensed only within the first scan cycle, whereas the command code is
sensed in every scan. The transmitted subsystem address remains unchanged if the subsystem address
selection is changed while the command key is pressed. A change of the subsystem address does not
start a transmission.
Remote control signal output (REMO)
The REMO output driver stage incorporates a bipolar emitter-follower which allows a high output
current in the output active (HIGH) state. The format of the output pulse trains are shown in Fig. 3
and one cycle of the output waveform for flashed or modulated mode is shown in Fig. 4.
A data word starts with two toggle bits TO, T1 (Fig. 3) which indicate by changing state that the
next instruction is a new command. The subsystem address is defined by the bits S3, S2, S1 and SO
(bit S3 is transmitted only for subsystem addresses 8 to 20). The selected command key is defined
by bits F, E, 0, C, B and A as shown in Table 2.
' ] (october 1987
611
___SA_A30_07_Jl_________________
FUNCTIONAL DESCRIPTION (continued)
H
REMO
L
,-
tw
I I
I I I I I I I I I I I I
T1
bit data -
TO
S2
SO
S1
0
0
E
D
0
0
B
0
C
A
0
(a)
H
REMO
L
bit data -
,-
tw
I I I I I I
T1
1
TO
S3
S2
S1
0
0
0
~I
I I I I I I
SO
E
D
0
0
C
B
0
I I
A
0
7Z97483
(b)
toggle bits
subsystem address
command bits
word length
determined by pulse spacing
T1, TO
S3,S2,Sl,SO
A to F
tw
binary values
Fig.3 Data format of remote control signal (REMO); (a) subsystem addresses 1 to 7, (b) subsystem
addresses 8 to 20.
REMO
(1)
REMO
(2)
(1) F lashed mode
(2) Modulated mode
Fig.4 Waveform for one pulse period at REMO output; for timing values see Table 3.
All pulse timings are multiples of the oscillator period (toscl as given in Table 3. Information carried
on the REMO output is defined as logic 1 or logic 0 by the time (tb) between leading edges of the
initial pulses of adjacent pulse periods.
Oscillator (OSCI, OSCO)
The external components for the oscillator circuit are connected to OSCI and OSCO. The oscillator
operates with a ceramic resonator in the frequency range 350 kHz to 500 kHz, as defined by the
resonator. With a supply voltage of less then 3 V a 270 Kn resistor should be connected in parallel with
the resonator (see Fig. 1).
612
October 19871 (
l____
Infrared remote control transmitter (low voltage)
S_A_A_3_0_0_7_____
Table 1 Definition of subsystem addresses
address
number
1
2
3
4
5
e:(
le:(
C
I-
Z
w
driver line(s)
connected to ADRM
no connection
DRVON
DRV1N
DRV2N
DRV3N
subsystem address
S1
S3
S2
-
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
-
-
-
SO
6
7
8
9
10
DRV4N
DRV5N
DRVON and DRV2N
DRVON and DRV3N
DRVON and DRV4N
0
1
0
1
1
0
0
1
11
12
13
14
15
D RVON and
DRV1 Nand
DRV1N and
DRV1N and
DRV1N and
D RV5N
DRV2N
DRV3N
DRV4N
DRV5N
1
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
16
17
18
19
20
DRV2N
DRV2N
DRV2N
DRV3N
DRV3N
DRV3N
DRV4N
DRV5N
DRV4N
DRV5N
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
and
and
and
and
and
-
~
a..
o..J
~
Table 2 Definition of command codes
w
C
key
pressed
command code generated
D
B
C
drive-to-sense
connection made
F
E
0
1
2
3
4
5
6
7
DRVON to
DRV1 N to
DRV2N to
DRV3N to
DRV4N to
DRV5N to
DRV6N to
DRV7N to
SENON
SENON
SENON
SENON
SENON
SENON
SENON
SENON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
DRVON to
DRV1 N to
DRV2N to
DRV3N to
DRV4N to
DRV5N to
DRV6N to
DRV7N to
SEN1 N
SEN1 N
SEN 1N
SEN1 N
SENtN
SEN1 N
SEN1N
SEN1N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
9
10
11
12
13
14
15
1
(october 1987
A
613
___
SA_A30_07_Jl________________
Table 2 Definition of command codes (continued)
key
pressed
614
drive-to-sense
connection made
F
E
16
17
18
19
20
21
22
23
DRVON
DRV1 N
DRV2N
DRV3N
DRV4N
DRV5N
DRV6N
DRV7N
to
to
to
to
to
to
to
to
SEN2N
SEN2N
SEN2N
SEN2N
SEN2N
SEN2N
SEN2N
SEN2N
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24
25
26
27
28
29
30
31
DRVON
DRV1N
DRV2N
DRV3N
DRV4N
DRV5N
DRV6N
DRV7N
to
to
to
to
to
to
to
to
SEN3N
SEN3N
SEN3N
SEN3N
SEN3N
SEN3N
SEN3N
SEN3N
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32
33
34
35
36
37
38
39
DRVON
DRV1 N
DRV2N
DRV3N
DRV4N
DRV5N
DRV6N
DRV7N
to
to
to
to
to
to
to
to
SEN4N
SEN4N
SEN4N
SEN4N
SEN4N
SEN4N
SEN4N
SEN4N
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
40
41
42
43
44
45
46
47
DRVON
DRV1 N
DRV2N
DRV3N
DRV4N
DRV5N
DRV6N
DRV7N
to
to
to
to
to
to
to
to
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
48
49
50
51
52
53
54
55
DRVON to
DRV1 N to
DRV2N to
DRV3N to
DRV4N to
DRV5N to
DRV6N to
DRV7N to
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
56
57
58
59
60
61
62
63
DRVON
DRV1N
DRV2N
DRV3N
DRV4N
DRV5N
DRV6N
DRV7N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
October
to
to
to
to
to
to
to
to
19871 (
and
and
and
and
and
and
and
and
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
com mand code generated
D
C
B
A
l____
Infrared remote control transmitter (low voltage)
S_A_A_3_00_7______
Table 3 Pulse timing
«
«
o
parameter
symbol
duration
duration at fosc
tosc = 2,2 /lS
= 455 kHz;
Flashed pulse width
tp
4 x tosc
8,8/ls
Modulation period
tM
1 x tosc
2,2/ls
Modulation LOW time
tML
0,5 x tosc
1,1 /lS
Modulation HIGH time
tMH
0,5 x tosc
1,1 /lS
Modulation pulse width
tpw
Basic unit of pulse spacing
to
Word length for subsystem addresses
1 to 7
8 to 20
tw
tw
Pulse spacing for
logic 0
logic 1
tb
tb
7tM + tMH
16,5 /lS
1152 x tosc
2,53 ms
55296 x tosc
59904 x tosc
121 ms
132 ms
5,06 ms
7,59 ms
2 x to
3 x to
~
OPERATION
~
zw
:2:
Q.
o
...J
W
>
W
o
Keyboard
In the standby mode all drivers ORVON - ORV6N are 'on' but are non-conducting due to their open
drain configuration. When a key is pressed, a completed drain connection pulls down one or more of
the sense lines to ground. Referring to Fig. 5, the power-up sequence for the Ie commences as a key
is pressed. The oscillator becomes active and then, following the debounce time (tOB), the output
drivers become active successively.
Within the first scan cycle the mode selection, subsystem address and the selected command are sensed
and loaded into an internal data latch.
Multiple keystroke protection
I n a mu Itiple keystroke sequence the command selected is always that of the first key to be sensed
and the scan rate increases to speed detection of a key-release (Fig. 6).
If more than one key is pressed at the same time, the output sequence is not changed.
There are two restrictions caused by the special structure of the keyboard matrix:
The keys switching directly to ground (codes 7, 15, 23, 31,39,47,55,63) are not completely
covered by multiple keystroke protection. If one sense input is switched to ground, other keys on
that sense line are ignored.
The sense lines SEN5N and SEN6N are not protected against multiple keystrokes on the same
driver line because this has been used to define codes 56 to 63.
I
(october 1987
615
_Jl_________
__
SA_A
3 0_0
7
Output sequence
The output operation starts when the selected code has been detected. A burst of pulses, including the
latched address and command codes, is generated at the output REMO for as long as the key is pressed.
The format of the output pulse train is as shown in Figs 3 and 4. The operation is terminated by
releasing the key, or by pressing more than one key at the same time. Once a sequence has been
started, the transmitted words will always be completed after the key has been released.
The toggle bits TO, T1 are incremented if the key is released for a minimum time tRE L (Fig. 5). They
remain unchanged in a multiple keystroke sequence.
616
October
19871 (
DEVELOPMENT DATA
5'
....
~
~
y
I/ke bouncing
closed
KEY
released
off
Jlill
~
r
l1--tREL-1
[1111
_______
[
...--_new~key_ __
I(
__
DRVnN
ca
3
~
8::1
....
2-....
~
::1
3
H
~.
REMO
""'I
0:E
o<
H
OSCO
OSCILLATOR ACTIVE
7Z85674
;:::t
III
c.c
~
Fig.5 Single keystroke sequence: tDB = debounce time = 4 To to 9 To;
tST = start time = 5 To to 10 To; tREL = minimum release time = To;
tw = word length.
0(")
.-+
0
0"
~
<0
W
C
parameter
conditions
symbol
min.
typo
max.
unit
Supply voltage
pin 20
VOO
2,0
-
6,5
V
fosc = 455 kHz;
VOO = 3,0 V
VOO = 4,5 V
VOO = 6,0 V
100
100
IOD
-
0,25
0,5
1,0
-
-
-
mA
rnA
rnA
Tamb = 25 OC;
VOO = 6,0 V
100
-
-
4
JJ,A
fosc
350
-
500
kHz
Supply current
active
Supply current
standby mode
Oscillator frequency
(ceramic resonator)
VOO
= 2 to
6,5 V
'I
(october 1987
619
___
SA_A30_07_Jl_________________
CHARACTERISTICS (continued)
parameter
conditions
symbol
min.
typo
max.
unit
Inputs SENON to SEN6N
Input voltage LOW
V D D = 2 to 6,5 V
I nput voltage HI GH
V D D = 2 to 6,5 V
VIL=OV;VDD=2V
VI L = 0 V; VDD = 6,5 V
I nput current
(P-channel pull-up)
-
-
0,3 x VDD V
VIH
0,7 x VDD
-
-
V
-II
-II
10
100
-
100
600
JlA
JlA
VIL
Outputs DRVON to
DRV6N (open drain)
Output voltage "ON"
10 = 0,25 mA; VDD=2 V VOL
10 = 2,5 mA; VDD = 6,5 V VOL
-
-
0,3
0,6
V
V
Output current "OF F"
VDD = 6,5 V
-
-
10
JlA
10
Input ADRM
Input voltage LOW
VIL
-
-
0,4 x VDD V
Input voltage HIGH
VIH
0,85 x VDD
-
-
V
VI=OV;VDD=2V
VI = 0 V; VDD = 6,5 V
-IlL
-IlL
10
100
-
100
600
JlA
JlA
VI = VDD; VDD = 2 V
VI = 0 V; VOO = 6,5 V
IIH
IIH
10
100
-
100
600
JlA
JlA
VOH
VOH
0,8
5,0
-
-
-
V
V
VOH
VOH
1,5
4,5
-
-
-
V
V
VOH
0,8 x VDD
-
-
V
VOL
-
-
0,4
V
VOL
-
-
0,4
V
Input current
(switched P- and Nchannel pull-up and
pull-down)
pull-up active
pull-down active
Output REMO
Output voltage HIGH
Output voltage LOW
620
October
19871 (
-IOH = 40 mA;
Tarnb = 25 oC;
VOO = 2 V
VDD = 6,5 V
-IOH = 100 mA;
Tamb = 25 oC;
VDD = 4 V
VDD = 6,5 V
-IOH = 0,5 mA;
VDD = 2 V
10L = 0,5 mA;
VDD = 2 V
10L = 2,0 rnA;
VOD = 6,5 V
l____
Infrared remote control transmitter (low voltage)
S_A_A_30_0_7______
parameter
conditions
symbol
min.
typo
max.
unit
Input OSCI
I nput current HI G H
VOO = 2 V
VOO = 6,5 V
IIH
IIH
5,0
-
5,0
70
J.lA
J.lA
-IOH = 100 J.lA;
VOO = 6,5 V
VOH
VOO -0,8
-
-
V
IOL = 100 J.lA;
VOO = 6,5 V
VOL
-
-
0,7
V
-
Output OSCO
Output voltage HI G H
Output voltage LOW
«
~
o
I-
Z
w
~
c..
o-I
W
>
o
W
I
(october 1987
621
l___
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
S_A_A_3_0_0_8______
INFRARED REMOTE CONTROL TRANSMITTER
(RECS 80 LOW VOLTAGE)
GENERAL DESCRIPTION
The SAA3008 transmitter IC is designed for infrared remote control systems. It has a capacity for
1280 commands arranged in 20 sUb-system address groups of 64 commands each. The subsystem
address may be selected by press-button, slider switches or be hard-wired.
Commands are transmitted in patterns which are pulse distance coded. Modulated pulse transmissions
allow a narrow-band receiver to be used for improved noise rejection. The modulation frequency of
the SAA3008 is 38 kHz which is 1/12 of the oscillator frequency of 455 kHz (typical).
Features
• Modulated transmission
• Ceramic resonator controlled frequency
• Data-word-start with reference time of unique start pattern
• Supply voltage range 2 V to 6.5 V
• 40 mA output current capability
• Very low standby current « 4 J.lA at VDD
• Up to 20 subsystem address groups
• Up to 64 commands per subsystem address
= 6 V)
up to 1280 commands
• Requires few additional components
PACKAGE OUTLINES
SAA3008P: 20-lead D I L; plastic (SOT146).
SAA3008T: 20-lead mini-pack; plastic (S020; SOT163A).
1
(DeCember 1988
623
___
SA_A30_0B_Jl_________________
z It)
z z Nz Mz " > > > >
> :;
a: a: a: a: a: a:
a:
0
0
0
SENON
0
0
0
13 14 15
17
16
0
18 19
20
8
SEN1N
SEN2N
SAA3008
+
10
11
9
ADRM
270 kn only
for operation
Below 3V
12
OSCI
resonator
subsystem
_address/
mode selection
100 pF
;J;
455 kHz
Fig.1 SAA3008 application example.
PINNING
VDD
DRV6N
DRV5N
DRV4N
DRV3N
DRV2N
DRV1N
DRVON
osco
VSS
OSCI
lZ24375
Fig.2 Pinning diagram.
624
December
19881 (
1
REMO
remote data output
2
3
4
5
6
7
8
SEN6N
SEN5N
SEN4N
SEN3N
SEN2N
SEN1N
SENON
sense inputs from key matrix
9
ADRM
address/mode control input
VSS
ground (0 V)
10
11
ascI
oscillator input
12
OSCO
oscillator output
13
14
15
16
17
18
19
DRVON
DRV1N
DRV2N
20
VDD
DRV3N J'
DRV4N
DRV5N
DRV6N
drive outputs to key matrix
positive supply voltage
lZ24314
Infrared remote control transmitter (RECS 80 low voltage)
l____
SA_A_3_0_0_8______
FUNCTIONAL DESCRIPTION
Key matrix (DRVON - DRV6N and SENON - SEN6N)
The transmitter keyboard is arranged as a scanned matrix with seven driver outputs (DRVON to DRV6N)
and seven sensing inputs (SENON to SEN6N) as shown in Fig.1. The driver outputs are open-drain
n-channel transistors which are conductive in the stand-by mode. The sensing inputs enable the
generation of 56 command codes. With two external diodes connected (or triple contact), as in Fig.1,
all 64 commands are addressable. The sense lines have p-channel pull-up transistors, so that they are
HIGH until pulled LOW by connecting them to an output via a key depression to initiate a code
transmission.
The maximum allowable value of contact series resistance for keyboard switches in the ON-state is 7 kQ.
Address/mode input (ADRM)
Subsystem addresses are defined by connecting one or two of the key matrix driver lines (DRVON to
DRV6N) to the ADRM input. This allows up to 20 subsystem addresses to be generated for the REMO
output (bits S3, S2, S1 and SO) as shown in Table 1 and Fig.3.
The transmission mode is defined by the DRV6N to ADRM connection as follows:
• Mode 1
• Mode 2
<2:
<2:
I-
C
IZ
w
:!:
0..
o
...J
W
>
W
C
DRV6N not connected to ADRM
D RV6N connected to AD RM
In Mode 1 the reference time REF equals 3To, this may be used as a reference time for the decoding
sequence. In Mode 2 an additional modulated pulse has been inserted into the middle of the reference
time, therefore, these pulses are now separated by 1.5To. This unique start pattern START uses the
detection of a beginning word (see Fig.3).
When more than one connection is made to ADRM then all connections should be decoupled using
diodes.
The ADRM input has switched pull-up and pull-down loads. In the standby mode only pull-down load
is active and ADRM input is held LOW (this condition is independent of the ADRM circuit configuration
and minimizes power loss in the standby mode). When a key is pressed the transmitter becomes active
(pull-down is switched OF F, pull-up is switched ON) and the driver line signals are sensed for the
subsystem address coding.
The subsystem address is sensed only within the first scan cycle, whereas the command code is sensed
in every scan. The transmitted subsystem address remains unchanged if the subsystem address selection
is changed while the command key is pressed. A change of the subsystem address does not start a
transmission.
In a multiple keystroke sequence (Fig.6) the second word B might be transmitted with subsystem
address 18 or 19 instead of the preselected subsystem address (Table 1). This is only relevant for
systems decoding subsystem address 18 or 19.
Remote control signal output (REMO)
The REMO output driver stage incorporates a bipolar emitter-follower which allows a high output
current in the output active (H IGH) state (Fig.7).
The information is defined by the distance 'tb' between the leading edges of the modulated pulses
(Fig.4). The distance tb is a multiple of the basic unit To (Table 3) which equals 1152 periods of the
oscillator frequency fosc (Table 3). The pulses are modulated with 6 periods of 1/12 of the oscillator
frequency (38 kHz).
The format of the output data is illustrated in Figs 3 and 4.
A data word starts with the reference time and toggle bit TO and is followed by the definition bits for
the subsystem address S3, S2, S1 and SO (bit S3 is transmitted only for subsystem addresses 8 to 20).
The selected command key is defined by bits F, E, D, C, B and A as shown in Table 2.
' ] (December 1988
625
_Jl_____________
__
SA_A
3 0_08
FUNCTIONAL DESCRIPTION (continued)
The toggle bit TO acts as an indication for the decoder whether the next instruction should be
considered as a new command or not. The codes for the subsystem address and the selected key are
given in Table 3.
1.....- - - - - - - - - - - - - -
H
REMO
bit
I I
I I
TO
REF
-
S2
I I
S1
o
data -
tw - - - - - - - - - - - - - - - " ,
I I I
SO
E
D
0
o
0
I I
I I I
c
A
o
0
(a) Transmission with reference time and subsystem addresses 1 to 7.
1. . .- - - - - - - - - - - - - -
tw
---------------"1
H
REMO
bit
-
11111I1
START
TO
S3
o
data -
S2
0
III
S1
0
SO
E
D
o
0
c
III
B
A
o
0
I
7Z24376
(b) Transmission with start-pattern and subsystem addresses 8 to 20.
Where:
Reference time
start pattern TO
S3, S2, S1, SO
A to F
tw
binary values
toggle bit
subsystem address
command bits
word length
determined by pulse spacing
Fig.3 Data format of remote control signal (REMO).
I ..------------tb-------------"I
H
REMO
L
--tl-c~~~
l:=tM
..
~---~
7Z24377
tpw - - - -
Fig.4 Waveform for one pulse period at REMO output; for timing values see Table 3.
Oscillator (OSCI,OSCO)
The external components for the oscillator circuit are connected to OSCI and OSCO. The oscillator
operates with a ceramic resonator in the frequency range 350 kHz to 500 kHz, as defined by the
resonator. When operating at a supply voltage of below 3 V a 270 kHz resistor should be connected
in parallel with the resonator.
626
December 1988 ' ] (
l___
Infrared remote control transmitter (RECS 80 low voltage)
SA_A_3_0_0_8_ __
Table 1 Definition of subsystem addresses
«
I«
C
IZ
address
number
driver line(s)
connected to ADRM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
no connection
DRVON
DRV1N
DRV2N
DRV3N
DRV4N
DRV5N
DRVON and DRV2N
DRVON and DRV3N
DRVON and DRV4N
D RVON and D RV5N
DRV1 Nand DRV2N
DRV1 Nand DRV3N
DRV1 Nand DRV4N
DRV1 Nand DRV5N
D RV2N and D RV3N
DRV2N and DRV4N
D RV2N and D RV5N
D RV3N and D RV4N
DRV3N and DRV5N
subsystem address
S1
S2
S3
-
1
1
a
a
a
a
-
-
a
a
1
1
a
a
1
a
1
0
1
1
1
1
1
a
a
1
1
1
1
1
1
1
1
1
1
a
a
1
1
1
a
a
1
a
a
a
a
a
a
a
a
a
a
a
a
1
1
a
SO
1
1
a
1
a
0
a
a
1
1
1
1
a
a
a
1
1
w
:1!
~
Table 2 Definition of command codes
...J
w
>
w
C
key
pressed
a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
drive-to-sense
connection made
F
D RVON to
DRV1 N to
DRV2N to
DRV3N to
DRV4N to
DRV5N to
DRV6N to
DRV7N to
DRVON to
DRV1 N to
DRV2N to
DRV3N to
D RV4N to
DRV5N to
DRV6N to
DRV7N to
D RVON to
DRV1 N to
D RV2N to
DRV3N to
D RV4N to
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
SENON
SENON
SENON
SENON
SENON
SENON
SENON
SENON
SEN1 N
SEN1 N
SEN1 N
SEN1 N
SEN1 N
SEN1 N
SEN1 N
SEN1 N
SEN2N
SEN2N
SEN2N
SEN2N
SEN2N
command code generated
EE
B
D
C
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
1
1
1
1
1
a
a
a
a
a
a
a
a
1
1
1
1
1
1
1
1
a
a
a
a
a
a
a
a
a
1
1
1
1
a
a
" a
a
.1
1
1
1
a
a
a
a
1
1
a
a
1
1
a
a
A
a
1
a
1
a
1
1
1
a
1
1
a
1
1
a
a
a
a
a
a
a
1
1
a
1
a
1
1
a
1
1
a
1
a
1
a
(December 1988
627
__S_AA_300_8_jl_________________
Table 2 Definition of command codes (continued)
628
key
pressed
drive-to-sense
connection made
F
command code generated
E
D
C
B
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
DRV5N to
DRV6N to
DRV7N to
D RVON to
DRV1 N to
D RV2N to
DRV3N to
DRV4N to
D RV5N to
D RV6N to
DRV7N to
D RVON to
DRV1N to
DRV2N to
DRV3N to
DRV4N to
DRV5N to
DRV6N to
DRV7N to
D RVON to
DRV1 N to
DRV2N to
DRV3N to
D RV4N to
DRV5N to
DRV6N to
DRV7N to
DRVON to
DRV1 N to
D RV2N to
o RV3N to
DRV4N to
DRV5N to
DRV6N to
DRV7N to
D RVON to
DRV1 N to
DRV2N to
D RV3N to
DRV4N to
DRV5N to
DRV6N to
DRV7N to
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
December 1988] (
SEN2N
SEN2N
SEN2N
SEN3N
SEN3N
SEN3N
SEN3N
SEN3N
SEN3N
SEN3N
SEN3N
SEN4N
SEN4N
SEN4N
SEN4N
SEN4N
SEN4N
SEN4N
SEN4N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
SEN5N
and
and
and
and
and
and
and
and
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
SEN6N
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
l__
Infrared remote control transmitter (RECS 80 low voltage)
S_A_A_3_0_0_8_ __
Table 3 Pulse timing
parameter
symbol
duration
duration at fasc
tosc = 2.2 J.ls
= 455 kHz;
Modulation period
tM
12tosc
26.4 J.lS
Modulation LOW time
tML
8tosc
17.6 J.ls
Modulation HIGH time
tMH
4tosc
8.8 J.lS
Modulation pulse width
tpw
5tM + tMH
Basic unit of pulse spacing
to
1152tosc
o to 7
tw
55296tos c
121.44 ms
8 to 20
tw
59904tos c
132.56 ms
140.8 J.lS
2.53 ms
Word length for subsystem
addresses
Pulse separation for
logic 0
~
<{
tb
2to
5.06 ms
logic 1
tb
3to
7.59 ms
reference time
tb
3to
7.59 ms
toggle bit
tb
C
I-
Z
w
Start pattern
tb
2to
5.06 ms
3to
7.59 ms
2 x 1.5to
2 x 3.79 ms
:E
Q.
o
OPERATION
>
Keyboard
.oJ
W
W
C
In the standby mode all drivers DRVON-DRV6N are ON but are non-conducting due to their open
drain configuration. When a key is pressed, a completed drain connection pulls down one or more of
the sense lines to ground. Referring to Fig.5, the power-up sequence for the Ie commences as a key
is pressed. The oscillator becomes active and then, following the debounce time (tDS), the output
drivers become active successively.
Within the first scan cycle the transmission mode, subsystem address and the selected command code
are sensed and loaded into an internal data latch. In a multiple keystroke sequence (Fig.6) the command
code is always altered according to the sensed key.
Multiple keystroke protection
The keyborad is protected against multiple keystrokes. If more than one key is pressed the circuit will
not generate a new REMO sequence (Fig.6).
In a multiple keystroke sequence the scan repetition rate is increased to detect the release of the key
as soon as possible.
There are two restrictions caused by the special structure of the keyboard matrix:
• The keys switching directly to ground (codes 7, 15,23,31,39,47, 55,63) are not completely
covered by multiple keystroke protection. If one sense input is switched to ground, other keys on
that sense line are ignored .
• The sense lines SEN5N and SEN6N are not protected against multiple keystrokes on the same driver
line because this has been used to define codes 56 to 63.
'I
(December 1988
629
_Jl_________
__
SAA_30_08
OPERATION (continued)
Output sequence
The output operation starts when the code of the selected key has been loaded into the internal
command register. A burst of pulses, including the latched address and command codes, is generated
at the output REMO for as long as the key is pressed. The format of the output pulse train is as
shown in Figs 3 and 4. The operation is terminated by releasing the key, or by pressing more than
one key at the same time. Once a sequence has been started, the transmitted words will always be
completed after the key has been released.
The toggle bit TO is incremented if the key is released for a minimum time tREL (Fig.5). In a multiple
keystroke sequence the toggle bit remains unchanged.
630
. December 1988
1(
DEVELOPMENT DATA
::::l
::t
~
CD
c..
Ci1
3
SCD
g
l/eVbounCin
closed
KEY
released
JllO
~
off
DRVnN
--I
r
l-tREL-1
/1111
_
[-
______
.---n_eWke_
v - -
I(
(')
o
::::l
r+
£
__
~
III
::::l
3
~.
tDB
H
:D
REMO
m
C')
en
OSCD
H
JUlVIIIIIIIIIIIIIIIIIIIIIIIII
OSCILLATOR ACTIVE
IIIIIIIIIIIIIIIIIIIIIIIIIIII
7Z85674
00
o
0'
:e
<
o
Sf
Fig.5 Single keystroke sequence; tDB = debounce time = 4T 0 to 9T 0; tST = start time = 5T 0 to 1OT 0;
tREL = minimum release time = To; tw = word length.
~
0
CD
(')
CD
3
0-
....
CD
(0
CO
CO
en
»
»W
0
0
ex>
(j)
....
W
fJ
N
(J)
»
»
c.u
o
£3
o
o
CT
.,
en
C'D
....
~
closed
00
KEY A
released
closed
KEY B
released
)I
I I I
/scan
off
DRVnN
REMO
word (key A)
OSCO
H
word (key A)
J1IlVZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
word (key B)
OSCILLATOR ACTIVE
IZVZI/Z7IZZZZIIOZOZZZZZZIIZ//1
7Z85673.1
Fig.S Scan rate multiple keystroke sequence: tSM
tOB, tST, and tw are as per Fig.5.
= scan
rate (multiple keystroke)
= ST 0
to lOT 0;
l____
Infrared remote control transmitter (RECS 80 low voltage)
S_A_A_30_0_8______
RATINGS
Limiting values in accordance with the Absolute Maximum Rating System (I EC 134)
symbol
min.
max.
unit
Supply voltage range
VOO
-0.3
+7
V
I nput voltage range
VI
-0.3
VOO+0.3
V
Output voltage range
Vo
-0.3
VDO+0.3
V
Ptot
Ptot
-
300
mW
-
200
mW
conditions
parameter
Total power dissipation
01 L package (SOT146)
mini-pack (S020; SOT163A)
Power dissipation
matrix outputs ORVON to ORV6N
Po
-
50
mW
Po
-
200
mW
Operating ambient temperature range
Tamb
-20
+70
oC
Storage temperature range
T stg
-20
+125
oC
remote data output REMO
HANDLING
W
C
parameter
conditions
"
Supply voltage
Supply current active
Standby mode
Oscillator frequency
(ceramic resonator)
symbol
min.
typo
max.
unit
VOO
2.0
-
6.5
V
fosc = 455 kHz;
VOO = 3 V
100
--
0.25
-
rnA
VOD = 4.5 V
100
0.5
-
1
-
-
4
IlA
-
500
kHz
-
-
0.3 VDO
V
-
V
-100
-600
IlA
IlA
Von = 6 V
JDO
-
T amb ,; 25 oC;
VOO =6 V
100
-
VOO
= 2 to 6.5 V
-
rnA
rnA
-
fosc
--'-----
350
~
Inputs SENON to SEN6N
= 2 to 6.5 V
I nput voltage LOW
VOO
Input voltage HIGH
VOO = 2 to 6.5 V
VIH
0.7 VOO
-
VIL = 0 V
VOO = 2 V
VOO = 6.5 V
II
II
-10
-100
-
I nput current
(p-channel pull-up)
VIL
1
(December 1988
633
_Jl_________
__
SAA_30_08
CHARACTERISTICS (continued)
parameter
conditions
symbol
min.
typo
max.
unit
10 = 0.25 rnA;
VOO = 2 V
VOL
-
-
0.3
V
10 = 2.5 rnA;
VOO = 6.5 V
VOL
-
-
0.6
V
VOO = 6.5 V
10
-
-
10
JJ.A
VIL
-
-
0.4 VOO
V
VIH
0. 85V OO
-
-
V
VI =OV
VOO = 2 V
VOO = 6.5 V
IlL
IlL
-10
-100
-
-100
-600
JJ.A
JJ.A
VI = VOO
VOO = 2 V
VOO = 6.5 V
IIH
IIH
10
100
-
-
100
600
JJ.A
JJ.A
10H = -40 rnA;
Tamb = 25 OC
VOO = 2 V
VOO = 6.5 V
VOH
VOH
0.8
5.0
-
-
-
-.
V
V
10H = 0.5 rnA;
VOO = 2 V
VOH
0.8 VOO
-
-
V
10L = 0.5 rnA;
VOO = 2 V
VOL
-
-
0.4
V
IOL = 2.0 rnA;
VOO = 6.5 V
VOL
-
-
0.4
V
VOO = 6.5 V
IIH
3.0
-
7.0
JJ.A
10H = 100 JJ.A;
VOO = 6.5 V
VOH
VOO-0.8
-
-
V
10L = 100 JJ.A;
VOO = 6.5 V
VOL
-
-
0.7
V
Outputs DRVON to
DRV6N (open drain 1)
Output voltage ON
Output cu rrent OFF
Input ADRM
Input voltage LOW
I nput voltage HI G H
Input current
(switched p and n
channel pull-up and
pull-down)
pull-up active
pull-down active
-
Output REMO
Output voltage HI G H
Output voltage LOW
Input OSCI
Input current HIGH
Output OSCO
Output voltage HIGH
Output voltage LOW
634
December
19881 (
l__
Infrared remote control transmitter (RECS 80 low voltage)
S_A_A_3_0_0_8_ __
'-------4----+-
vD D
Vss
7Z24378
Fig.7 R EMO output stage.
«
~
«
c
I-
2
w
:!E
c...
o..J
W
>
W
C
1
(DeCember 1988
635
DEVELOPMENT DATA
SAA3009
SAA3049
This data sheet contains advance information and
specifications are subject to change without notice.
INFRARED REMOTE CONTROL DECODERS
GENERAL DESCRIPTION
The main function of the SAA3009 and SAA3049 ICs is to check and convert the received coded data
(R ECS80/RC5) into latched binary outputs. The device address can be hard-wired for a particular address
allowing several devices in one location. Alternatively, received data with any address can be accepted,
the received data and address are then outputs ..
Features
• Decodes 64 remote control commands with a maximum of 32 subaddresses
• Accepts RECS80 codes with pulse position modulation (SAA3004, SAA3007, SAA3008)
or RC5 codes with biphase transmission (SAA3006, SAA3010)
• Available at SAA3009 with 8 high current (10 mAl open-drain outputs and internal pull-ups for
direct LED drive via resistors or as SAA3049 for low supply current applications
• Adding circuitry for binary decoding allows a maximum of 2048 commands to be used, for example
1-of-16 decoder (HEF4515)
QUICK REFERENCE DATA
parameter
conditions
symbol
min.
typo
max.
unit
Supply voltage
SAA3009
SAA3049
note 1
note 2
Vee
Vec
4.5
2.5
5.0
-
5.5
5.5
V
V
Supply current
SAA3009
SAA3049
note 1
note 2
Ice
Ice
-
1.0
70
2.0
mA
mA
fosc
-
4
-
MHz
IOL
IOL
1.6
3.0
10
-
mA
mA
Osci Ilator frequency
Output sink current LOW
(pins 1 to 8)
SAA3009
SAA3049
note 3
note 4
Notes to the QUICK REFERENCE DATA
1.
2.
3.
4.
T amb = 0 to + 70 oC.
Tamb = -40 to + 85 °C.
Open-drain with 20 to 50 kn internal pull-up resistor.
Open-drain without internal pull-up resistor at VCC = 5 V ± 10%; Vo
= 0.4 V.
PACKAGE OUTLINES
SAA3009P; SAA3049P: 20 lead 01 L; plastic (SOT146).
SAA3049T: 20 lead mini-pack; plastic (S020; SOT163A).
' ] (March 1989
637
SAA3009
SAA3049
~:mand
+5 V
~CA
REMOTE
CONTROL
TRANSMITTER
SAA3004
SAA3007
SAA3008
or
SAA3006
SAA3010
REMOTE
CONTROL
DECODER
acknowledge
bits
A
B
C
o
CQW89A
CQY89A
BPW50
IR
-+
-+
IR
PREAMPLIFIER
IN
TDA3048
SAA3009
or
SAA3049
data
E
F
TO
toggle
AO (SO)
A1 (S1)
A2 (S2)
address
A3 (S3)
A4
Fig.1 System diagram.
4 MHz
TRANSMITTERS (see individual data sheets for full specifications)
638
SAA3004
VBatt = 4 to 11 V (max.); 7 x 64 = 448 commands (RECS80 code)
SAA3007
VBatt
SAA3008
VBatt = 2 to 6.5 V (max.); 20 x 64 = 1280 commands (RECS80 code)
= 2 to 6.5 V (max.); 20 x 64 = 1280 commands (RECS80 code)
SAA3006
VBatt = 2 to 7.0 V (max.); 32 x 64
SAA3010
VBatt
= 2 to 7.0 V
March 19891 (
(max.); 32 x 64
= 2048 commands (RC5 code)
= 2048 commands (RC5 code)
7Z21786
SAA3009
SAA3049
Infrared remote control decoders
RATINGS
Limiting values in accordance with the Absolute Maximum System (I Ee 134)
W
C
'I
(MarCh 1989
639
SAA3009
SAA3049
l
'----------------------------------------------------------
CHARACTERISTICS
All voltages measured with respect to ground (VEE
= 0 V).
SAA3009: Vee = 4.5 to 5.5 V; Tamb = 0 to + 70 oe unless otherwise specified
SAA3049: Vee = 2.5 to 5.5 V; T amb = -40 to + 85 unless otherwise specified
symbol
min.
typo
max.
unit
Supply voltage
SAA3009
SAA3049
Vee
Vee
4.5
2.5
5.0
-
5.5
5.5
V
V
Supply current
SAA3009
SAA3049
lee
lee
-
-
-
0.8
70
2.0
mA
mA
VIH
VIH
2.0
0.7 Vee
-
Vee + 0.5
Vee
V
V
VIL
VIL
0.5
0
-
0.8
0.3 Vee
V
V
VIH
VIH
2.0
0.7 Vee
-
Vee + 0.5
Vee
v
VIL
VIL
-0.5
0
-
0.8
0.3 Vee
V
V
Input voltage HIGH
SAA3009
SAA3049
VIH
VIH
3.0
0.7 Vee
-
Vee + 0.5
Vee
V
V
Input voltage LOW
SAA3009
SAA3049
VIL
VIL
-0.5
0
-
1.5
0.3 Vee
V
V
fosc
-
4
-
MHz
parameter
conditions
Input signals (pin 9)
Input voltage HIGH
SAA3009
SAA3049
Input voltage LOW
SAA3009
SAA3049
active
-
Mode selection (pin 11)
Input voltage HIGH
SAA3009
SAA3049
note 1
I nput voltage LOW
SAA3009
SAA3049
note 2
Command received indicator
and mode control (pin 19)
-
V
note 3
Crystal oscillator
Oscillator frequency
640
March 1989\ (
note 4
SAA3009
SAA3049
Infrared remote control decoders
parameter
conditions
symbol
min.
typo
max.
unit
Output voltage HI G H
IOH = -50J.LA
VOH
2.4
-
IOl = 10 mA
Val
-
-
VCC
1.0
V
Output voltage lOW
-
10
mA
SAA3009 OUTPUTS
10 mA open-drain with
internal pull-up resistor
(pins 1 to 8)
Output sink current lOW
IOl
V
5 mA open-drain without
internal pull-up resistor
(pins 18 and 19)
Output voltage HIGH
Output voltage lOW
IOl = 5 rnA
Output sink current lOW
W
C
SAA3049 OUTPUTS
Open-drain without
internal pull-up resistor
Output sink current lOW
note 5
V CC = 5 V ± 10%;
VOl=O.4V
Notes to the characteristics
1. R ECS80 decoder for transmitters SAA3004, SAA3007 or SAA3008; SAA3009 has an internal
pull-up resistor.
2. RC5 decoder for transmitters SAA3006 ot SAA3010.
3. With pin 19 = HIGH, then pins 7, 8,15,16 and 17 are address inputs.
With pin 19 = lOW, then pins 7, 8,15,16 and 17 are 4 or 5 address received outputs.
In Figs 4,5 and 6 this HIGH/lOW switching is dependent on whether the transistor on pin 19 is fed
via a series resistor or not. In both applications pin 19, which toggles several times (see Fig.3) while
a valid command is acknowledged, can be used to activate (flash) an lED indicator.
4. A quartz crystal with a frequency of 4 MHz is recommended for the standard transmitter application.
4. Application as output requires connection of an external pull-up resistor.
'I (MarCh
1989
641
SAA3009
SAA3049
CHARACTERISTICS (continued)
Reset (pin 14)
The simple circuit is shown in Figs 4,5 and 6. The alternative reset circuit shown in Fig.2 protects
against short term power supply transients by generating a reset.
VCC----~----~----------~~--~20
+
SAA3009
or
SAA3049
1j!F
zener diode
3.6 V
~
Y
68kO
(SAA3049 only)
,1
7Z21787
Fig.2 Proposed improved reset circuit.
Infrared signal input (pin 9)
This pin is sensitive to a negative-going edge.
Command received indicator (pin 19)
signal at pin 19
-, 1'-==
_"'15msms_I
120
7Z21785
Fig.3 Output diagram of command acknowledge.
642
March
19891 (
DEVELOPMENT DATA
APPLICATION INFORMATION
~
c..
(3)
I-----~-*
I
~b
?
111F
UI
~
3
f:::\
1
+nl
o
S
~
'-.:./
1N4148
CaW24
n
o
52-bit
address
S3-bit
5.6 kO
(1) }
~
~48
~
33 kO [)
5.6 kO )
outputs
I
I
IL - _ _
n
~
n
27 pF
27 pF
----
::J
r+
2-
c..
(2)
,...-----------,
~
CD
8
c..
I
I
I
~
en
--~
4 MHz
BC548
~
~
Q)
mmand acknowledge
f"f\
::J
TO-bit
Vcc
(+5 V)
~DI-
,
subaddress
range (4)
.-
I
---
1'(2)
I
I
1 MO
I~
If
20
19
L
18
17
16
___
~
15
14
13
12
11
6
7
8
9
10
SAA3009
SAA3049
1
2
3
4
5
1f11N
input
\
A
B
C
data outputs
s:
Q)
c:l
:T
co
00
co
(1)
(2)
(3)
(4)
0
E
F
1
51-bit
address
SO-bit
}
outputs
7Z21788
only for subaddress 8 to 20.
only for SAA3009.
only for SAA3049.
subaddress range:
when LOW (subaddress 8 to 20) pin 15 is connected to ground
when HIGH (subaddress 1 to 7) pin 15 is open (SAA3009)
when HIGH (subaddress 1 to 7) pin 15 is connected via pull-up resistor to VCC (SAA3049)
F ig.4 Remote control decoder with latched 11 (10) -bit parallel outputs (10 (9) -bits inverted)
for use with transmitter types SAA3004, SAA3007 or SAA3008; pin 11 is HIGH for RECS80 code.
~
Co\)
(J)(J)
»
»
u>u>
00
~o
(0(0
t
CJ)CJ)
»»
»»
(,.)(,.)
APPLICATION INFORMATION (continued)
TO-bit
s:
III
~
Vcc
V)
~
CO
00
CO
0
r---C::J
~O
(0(0
r-----~-~
I
t::\
111F
1
220nb
-"'
00
(2)
(+5
mmand acknowledge
+m
UI
'C/
01
CaW24
,-
1N4148
A2-bit
A3-bit
~
5.6kn
.-----.
~48
~
33kn
)
5.6 kn
A4-bit
I]
r -
-
-
-
-
-
-
address
outputs
-'(1)
:n n:
I
~
~
27 pF
27 pF
I
_ _ ...l
----
'----
4MHz
BC548
~
-
}
HOt-
,-
- - - -r(1)
r
U
20
19
1 Mn
~
I
I
L...
18
17
16
---
I
I
~
L
15
14
13
12
11
6
7
8
9
10
SAA3009
SAA3049
1
2
3
4
5
1F1..
input
A
~
~
~
B
C
0
1A1-bit
E
F
AO-bit
I
\
data outputs
(1) only forSAA3009.
(2) only for SAA3049.
Fig.5 Remote control decoder with latched 12-bit parallel outputs (11 bits inverted)
for use with transmitter types SAA3006 or SAA3010; pin 11 is LOW for RC5 code.
7Z21789
address
} outputs
DEVELOPMENT DATA
VCC
(+5 V)
command acknowledge
(2)
c::::::J-
,
11
~
'-Y
UI
1N4148
set: ubaddresses
H or L (3)
-u
S2 (A2)
'"' S3 (A3)
5.6kD
~
~
~~
~
33 kD [)
5.6kD
~
'"'
,--------,I
~
(M) (4)
(1)
BC548
I
I
0
L __
68 kD
"""L-.J--
n
27 pF
~
S1 (A1)
rD
SO (AO)
fo r address see
dl ta sheets of
tn nsmitter ICs
I
- - - - 2~~J
f-----.JDJ-
~
r
::::I
~
III
!.
a3
o
a-
S
::::I
'*
2-
c..
CD
S
c..
4 MHz
BC548
~
~
\::./
01
CaW24
~
mode
H selects RECS o code
L selects RC5 c, de
---~
~
en
- - - l(1)
I
1MD
I~ I
L
If
20
19
18
17
16
___
W
15
14
13
12
11
6
7
8
9
10
SAA3009
SAA3049
1
2
3
4
5
vliN
input
TO
\ A
B
C
v
data outputs
s:
III
n
=r
co
00
CO
~
(J1
0
E
F
1
I
7Z21790
(1) only for SAA3009.
(2) only for SAA3049.
(3) address inputs:
when LOW address input pin is connected to ground
when HIGH address input pin is open (SAA3009)
when HIGH address input pin is connected via pull-up resistor to VCC (SAA3049)
(4) subaddress range RECS80 code:
when LOW (subaddress 8 to 20) pin 15 is connected to ground
when HIGH (subaddress 1 to 7) pin 15 is open (SAA3009)
when HIGH (subaddress 1 to 7) pin 15 is connected via pull-up resistor to VCC (SAA3049)
Fig.6 Remote control decoder for up to 20 subaddresses with 6 + 1-bit parallel outputs (RECS80 code).
Decoder is set for required subaddress by holding address pins HIGH or LOW. Pin 11 is HIGH for use with
transmitter types SAA3004, SAA3007 or SAA3008 (RECS80 code). Pin 11 is LOW for use with transmitter
types SAA3006 or SAA301 0 (RC5 code). Remote control decoder for up to 32 subaddresses with 6 + 1-bit
parallel outputs (RC5 code).
en en
»»
»»
ww
00
~O
COCO
_________Jl__
SA_A30_10_
INFRARED REMOTE CONTROL TRANSMITTER RC-5
GENERAL DESCRIPTION
The SAA3010 is intended as a general purpose (RC-5) infrared remote control system for use where
a low voltage supply and a large debounce time are expected. The device can generate 2048 different
commands and utilizes a keyboard with a single pole switch for each key. The commands are arranged
so that 32 systems can be addressed, each system containing 64 different commands. The keyboard
interconnection is illustrated by Fig.3.
The circuit response to legal (one key pressed at a time) and illegal (more than one key pressed at a
time) keyboard operation is specified in the section "KEYBOARD OPERATION".
Features
•
•
•
•
Low voltage requirement
Biphase transmission technique
Single pin oscillator
Test mode facility
QUICK REFERENCE DATA
parameter
symbol
min.
typo
max.
unit
Supply voltage range
I nput voltage range*
VOO
2
-
7
V
VI
-0.5
-
VOO+0.5
V
Input cu rrent
II
-
-
±10
mA
Output voltage range*
Vo
-0.5
-
VOO+0.5
V
Output current
10
-
-
±10
mA
Tamb
-25
-
85
°C
Operating ambient temperature range
* VOO+0.5 V must not exceed 9 V.
The use of this device must conform with the Philips Standard number URT-0421.
PACKAGE OUTLINES
28-lead 01 L plastic; (SOT117).
28-lead mini-pack; plastic (S028; SOT136A),
"I (June
1989
647
___
SAA_301_0_Jl_________________
SAA3010
OSC
TP1
TP2
18
OSC
3 x 21
~~
20
TEST
MODE
19
I
I
SSM
Z3
Z2
Z1
ZO
X7
X6
X5
X4
X3
X2
X1
XO
2
~
MODE
SELECTION
I
6
5
MASTER
RESET
GENERATOR
r---
o
W
~'----y----I\
L
L
T
J
stop time
Lcontrol
-l _
master address
start
1 - 4 - - - - - - - - - - - - - - data word time = 30 bit times - - - - - - - - - - - - - - 1...1
7Z87355
Fig. 4 RC-5(extended) code format: the first start bit is used only for detection and input gain-setting;
stop time = 1,5 bit-times (nominal).
digital '1'
-1bittime-
t=+L------I
digital '0'
7Z82856
Fig. 5 Biphase code definition: RC-5 bit-time = 27 X TOSC = 1,778 ms (typical); RC-5(ext) bit-time
x TOSC = 0,89 ms (typical), where TOSC = the oscillator period time.
= 26
"] (JUlY
1983
665
___
SAA_30_28_Jl_________________
FUNCTIONAL DESCRIPTION (continued)
More information is added to the input data held in the buffer in order to make it suitable for
transmission via the 12 C interface. The information now held in the buffer is as follows:
RC-5(ext) buffer contents
RC-5 buffer contents
•
•
•
•
•
•
data valid indicator
format indicator
input indicator
control
address data
command data
1 bit
1 bit
1 bit
1 bit
5 bits
6 bits
•
•
•
•
•
•
•
data valid indicator
format indicator
input indicator
master address
control
slave address
data
1 bit
1 bit
1 bit
3 bits
8 bits
8 bits
8 bits
The information assembled in the buffer is subjected to the following controls before being made available at the 12 C interface:
ENB = HIGH
Enables the set standby input SSB.
SSB = LOW
Causes power-off output PO to go HIGH.
PO
= HIGH
This occurs when the set standby input SSB = LOW and allows the existing values
in the buffer to be overwritten by the new binary equivalent values. After
ENB = LOW, SSB is don't care.
PO
= LOW
This occurs according to the type of code being processed, as follows:
RC-5. When the binary equivalent value is transferred to the buffer.
RC-5(ext). When the reset standby bit is active and the master address bits are
equal in value to the MAO, MA 1, MA2 inputs.
At power-on, PO is reset to LOW.
DAV
666
= HIGH
July
This occurs when'the buffer contents are valid. If the buffer is not empty, or an
output transfer is taking place, then the new binary values are discarded.
19831 (
l___
Infrared remote control transcoder (RC-6)
S_A_A_3_0_2_8______
Output function
The data is assembled in the buffer in the format shown in Fig. 6 for RC-5 binary equivalent values, or
in the format shown in Fig. 7 for RC-5(ext) binary equivalent values. The data is output serially, starting
from the left of the formats shown in Figs 6 and 7.
Fig. 6 RC-5 binary equivalent value format.
«
«
Cl
IIZ
w
~
c..
o
-'
w
Fig. 7 RC-5(ext) binary equivalent value format.
>
w
Cl
The output signal DAV, derived in the buffer from the data valid bit, is provided to facilitate use of the
transcoder on an interrupt basis. This output is reset to LOW during power-on.
The 12 C interface allows transmission on a bidirectional, two-wire 12 C bus. The interface is a slave
transmitter with a built-in slave address, having a fixed 7-bit binary value of 0100110: Serial output of
the slave address onto the 12 C bus starts from the left-hand bit.
Oscillator
The oscillator can comprise a ceramic resonator circuit as shown in Fig. 8. The typical frequency of
oscillation is 455 kHz.
H
15 nF
1---___1--.-----0
osc I
(1)
r-----~---+----~osco
7Z87358
(1) Catalogue number of ceramic resonator: 2422 540 98008.
Fig. 8 Oscillator circuit.
'I (JUlY
1983
667
___
SAA_30_28_Jl_________________
FUNCTIONAL DESCRIPTION (continued)
12 C bus transmission
Formats for 12 C transmission in low and high speed modes are shown respectively in Figs 9 and 10.
Fig. 9 Format for transmission in 12C low speed mode.
acknowledge
from slave
Fig. 10 Format for transmission in 12 C high speed mode.
Note to Figures 9 and 10
When R/W bit = 0; the slave generates a NACK (negative acknowledge), leaves the data line HIGH and
waits for a stop (P) condition.
When the receiver generates a NACK; the slave leaves the data line HIGH and waits for P (the slave
acting as if all data has been transmitted).
When all data has been transmitted, the data line remains HIGH and the slave waits for P.
668
July
19831 (
l___
Infrared remote control transcoder (RC-5)
S_A_A_3_0_2_8______
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage range with respect to VSS
VOO
-0,5 to
Input voltage range
VI
-0,5 to (VOO+0,5) V*
+ 15 V
Input current
± II
max.
Output voltage range
Vo
-0,5 to (VOO+ 0,5) V*
Output current
± 10
max.
10 rnA
10 rnA
Power dissipation output oseo
Po
max.
50 mW
Power dissipation per output (all other outputs)
Po
max.
100 mW
Total power dissipation per package
Ptot
max.
Operating ambient temperature range
Tamb
T stg
-25 to
200 mW
+85 0 e
Storage temperature range
-55 to
+ 150 0e
HANDLING
...««
c
...z
Inputs and outputs are protected against electrostatic charge in normal handling. However, to be totally
safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS
Oevices") .
w
:E
c..
o..J
W
>
W
C
Purchase of Philips' 12 e components conveys a license under the
Philips' 12 C patent to use the components in the 12 C-system
provided the system conforms to the Fe specifications defined
by Philips.
* VOO + 0,5 V not to exceed 15 V.
669
_Jl_________
__
SAA_30_28
CHARACTERISTICS
VSS
= 0 V; Tamb = -25 to 85 °Cunless otherwise specified
parameter
VDD (V)
min.
symbol
typo
max.
unit
Supply voltage
-
VDD
4,5
-
5,5
V
Supply current; quiescent
at Tamb = 25 °c
5,5
IDD
-
-
200
IlA
Input voltage HIGH
4,5 to 5,5
VIH
0,7 x VDD -
VDD
V
I nput voltage LOW
4,5 to 5,5
VIL
0
-
0,3 x VDD V
5,5
II
-
-
1
IlA
5,5
-II
-
-
1
IlA
Output voltage LOW
at 10 L = 1,6 m A
4,5 to 5,5
VOL
-
-
0,4
V
Output leakage current
at Va = 5,5 V;
Tamb = 25 °c
5,5
lOR
-
-
1
IlA
Output voltage HIGH
at -IOH = 0,2 mA
4,5 to 5,5
VOH
VDD- 0,5 -
-
V
Output voltage' LOW
at IOL = 0,3 rnA
4,5 to 5,5
VOL
-
-
0,4
V
Output leakage current
at Tamb = 25 oC;
VO=5,5V
5,5
lOR
-
-
1
IlA
5,5
lOR
-
-
1
IlA
Output voltage LOW
at IOL = 2 rnA
4,5 to 5,5
VOL
-
-
0,4
V
Output leakage current
at Va = 5,5 V;
Tamb = 25 °c
5,5
lOR
-
-
1
IlA
4,75
fOSCI
500
-
-
kHz
Inputs
MAO, MA1, MA2, DATA 1, DATA 2,
RC5,SC~ENB,SSB,OSCI
I nput leakage current
at VI = 5,5 V;
Tamb = 25 °c
Input leakage current
at VI = OV;
Tamb = 25 oC;
Outputs
DAV, PO
OSCO
VO=OV
SOO
Oscillator
Max. oscillator frequency (Fig. 8)
670
July 1983\ (
l____
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
S_A_A_7_2_10______
DECODER FOR COMPACT DISC DIGITAL AUDIO SYSTEM
GENERAL DESCRIPTION
The SAA7210 incorporates the functions of demodulator, subcoding processor, error corrector and
concealment in one chip. The device accepts data from the disc and outputs serial data directly to a
dual 16-bit digital-to-analogue converter TOA1541 (OAC) via the Inter IC signal bus (1 2 S). The 12 S
output can also be fed via the stereo interpolating digital filter SAA7220 which provides additional
concealment plus over-sampling digital filtering. For descriptive purposes, the SAA721 0 is referred to
as the A-chip and the SAA7220 as the B-chip.
Features
•
•
•
•
•
•
•
•
•
Adaptive slicer with high-frequency level detector for input data
Built-in drop-out detector to prevent error propagation in adaptive slicer
Fully protected timing synchronization to incoming data
Eight-to-Fourteen Modulation (EFM) decoding
Cross-Interleaved Reed-Solomon Code (CI RC) used for error correction system
Subcoding microprocessor handshaking protoco!
Motor speed control logic which stabilizes the input data rate
Error flag processing to identify unreliable data
Concealment to replace uncorrectable data
• 12 S bus for data exchange between A-chip, B-chip and OAC
• Bidirectional data bus to external RAM (16 K x 4 bits)
QUICK REFERENCE DATA
Supply voltage (pin 40)
VOO
typo
5 V
typo
200 rnA
Supply current (pin 40)
100
Oata slicer input voltage range
VI(p_p)
Oscillator operating frequency
XTAL
VCO
fXTAL
fVCO
typo
typo
Maximum output current (each output)
10
max.
Operating ambient temperature range
Tamb
0,25 to 2,5 V
11,2896 MHz
8,6436 MHz
10 rnA
-20 to +70 oC
PACKAGE OUTLINE
40-lead 01 L; plastic (SOT129).
I
(september 1985
671
0')
~
(J)
en
CD
"'0
Cit
3
HF
inp~t--tc:::J-t-lH
FB
0-
o
XTAL21
18
~
QCL
QDATA I QRA
»
»
-....I
DEEM
I\)
~
IXTAL1
o
119
~
01
AO
to
A7
D1
r\.r------r-:t/ ~4
r;L~
I
;;OZeSSOR-
FL--
i
I~
I,<\\l~
I
I
13
I
J;
I
I
I
CI RC DECODER
L_L_-':' __ J
SAA7210
MICROCODED
SYNDROME FORMER 1CORRECTION PROCESSOR
EEP/PES
GENERATOR
10
28
27
7Z87976
CRI
CEFM
V DD
VSS
Vaa
(decoupling only)
Fig. 1 Block diagram.
l____
Decoder for compact disc digital audio system
S_A_A_7_21_0______
PINNING
A7
VOO
A3
WSAB
A2
38
ClAB
A1
OAAB
AO
EFAB
A4
SCAB
AS
34
SOAB
A6
33
SWAB/SSM
RAS
32
OEEM
R/W
OCl
SAA721 0
MUTE
«
I«
c
I:2
ORA
02
OOATA
01
CRI
03
CEFM
w
CAS
o-I
c..
04
W
>
MSC
C
XTAl2
HFO
~
HFI
FB
W
18
I ref
PO/DC
XTAl1
VBB
VSS
7Z80604
Fig.2 Pinning diagram; for pin functions see next page.
1
(september 1985
673
___S_AA_721_0_Jl_________________
Pin functions
mnemonic
description
1-8
AO-A7
Address: address outputs to external RAM.
9
RAS
Row Address Select: output to external RAM (4416) which uses mUltiplexed
address inputs.
pin no.
674
10
R/W
Read/Write: output signal to external RAM.
11
MUTE
Mute: input from the microprocessor. When mute is LOW the data output
OAAB (pin 37) is attenuated to zero in 15 successive divide-by-2 steps. On
the rising edge of mute the data output is incremented to the first "good"
value in 2 steps. This input has an internal pull-up of 50 kQ (typ.).
12-14
01-03
Data: data inputs/outputs to external RAM.
15
CAS
Column Address Select: output signal to external RAM.
16
04
Data: data input/output to external RAM.
17
MSC
Motor Speed Control: open drain output which provides a pulse width
modulated signal with a pulse rate of 88 kHz to control the rate of data
entry. The duty factor varies from 1,6% to 98,4% in 62 steps.
When a motor-start signal is detected via pin 33 (SWAB/SSM) the duty
factor is forced to 98,4% for 0,2 seconds followed by a normal calculated
signal. After a motor-stop signal is detected the duty factor is forced to
1,6% for 0,2 seconds, followed by a continous 50% duty factor.
18
XTAL2
Crystal oscillator output: drive output to clock crystal (11,2896 MHz typ.).
19
XTAL1
Crystal oscillator input: input from crystal oscillator or slave clock.
20
VSS
Ground: ci rcu it earth potential.
21
VBB
Back Bias supply voltage: back bias output voltage (-2,5 V ±20%). The
internal back bias generator can be decoupled at this pin.
22
PO/OC
Phase Detector output/Oscillator Control input: outputs of the frequency
detector and phase detector are summed internally, then filtered at this
pin to provide the frequency control signal for the VCO.
23
Iref
Current reference: external reference input to the phase detector. This
input is required to minimize the spread in the charge pump output of
the phase detector. An internal clamp prevents the voltage on this pin
rising above 3,5 V.
24
FB
Feedback: output from the input data slicer. This output is a current
source of 100 J1.A (typ.) which changes polarity when the level detector
input at pin 25 (HFI) rises above the threshold voltage of 2 V (typ.).
When a data run length violation is detected (e.g. during drop-out), or when
HFO (pin 26) is LOW, this output goes to high impedance state.
25
HFI
High-Frequency Input: level detector input to the data slicer. A differential
signal of between 0,25 and 2,5 V (peak-to-peak value) is required to drive
the data slicer correctly. When a T max violation is detected or when HFO
is LOW, this input is biased directly to its threshold voltage.
26
HFO
High-Frequency Detector: when HIGH this input signal enables the frequency and phase detector inputs, also the feedback output (FB) from the data
slicer.
An internal voltage clamp of 3 V (typ.) requires the HFO input to be fed
via a high impedance. This input has an internal pull-up of 50 kQ (typ.).
September 1985
(
Decoder for compact disc digital audio system
l____
S_A_A_7_21_0______
pin no.
mnemonic
description
27
CEFM
Clock Eight-to-Fourteen Modulation: demodulator clock output 4,3218 MHz
(typ.).
28
CRI
Counter Reset Inhibit: when LOW this input signal allows the divide-by-588
master counter in the DEMOD timing to run-free. This input has an internal
pull-up of 50 kr2 (typ.).
29
QDATA
Q-channel Data: this subcoding output is parity checked and changes in
response to the Q-channel clock input (see subcoding microprocessor
handshaking protocol).
30
QRA
Q-channel Request input/Acknowledge output: the output has an internal
pull-up of nominally 10 kr2. (see subcoding microprocessor handshaking
protocol).
31
QCL
Q-channel Clock: clock input generated by the micro-processor when it
detects a QRA LOW signal.
32
DEEM
De-emphasis:signal derived from one bit of the parity-checked Q-channel
and fed out via the debounce circuit.
33
SWAB/SSM
Subcoding Word clock output & Start/Stop Motor input: open drain output
which is sensed during each HIGH period and if externally forced LOW a
motor-stop condition will be decoded and fed to the motor control logic
circuit.
34
SDAB
Subcoding Data: a 1O-bit burst of data, including flags and sync bits, is
output serially to the B-chip once per frame clocked by burst clock output
SCAB (see Fig. 4).
35
SCAB
Subcoding Clock: a 1O-bit burst clock 2,8224 MHz (typ.) output which is
used to synchronize the subcoding data.
36
EFAB
Error Flag: output from interpolation and mute circuit to B-chip indicating
unreliable data.
37
DAAB
Data: this output which is fed to the B-chip or DAC, together with its
clock (CLAB) and word select (WSAB) outputs, conforms to the 12 S bus
format (see Fig. 5).
e::(
l-
e::(
0
I-
zw
2:
a..
0
..J
w
>
LU
0
38
CLAB
Clock: output to B-chip or DAC.
39
WSAB
Word Select: output to B-chip or DAC.
40
VOD
Power Supply: positive supply voltage(+ 5 V).
Note to the pin functions
The pin sequence of the address outputs (AO-A7l and the data outputs (D1-D4) has been selected to
be compatible with various dynamic 16 K x 4-bit RAMs including the 4416.
September 1985
675
Jl___________________________________
_______
S_AA_7_2_10___
FUNCTIONAL DESCRIPTION
Demodulation
Data read from the disc is amplified and filtered externally and then converted into a clean digital
signal by the data slicer. The data slicer is an adaptive level detector which relies on the nature of the
eight-to-fourteen modulation system (EFM) to determine the optimum slicing level. When a signal
drop-out is detected (via the H FD input, or internally when a data run length violation is detected) the
feedback (FB) to the data slicer is disabled to stop drift of the slicing level.
Two frequency detectors, a phase detector and a voltage-controlled oscillator (VCO) form an internal
phase-lock loop (PLL) system. The voltage-controlled oscillator (VCO) runs at twice the input data
rate (typically at 8,6436 MHz), its frequency being dependent on the voltage at pin 22 (PD/OC). One
of the frequency detectors compares the VCO frequency with that of the crystal clock to provide
coarse frequency-control signals which pull the VCO to within the capture range of fine frequency
control. Signals for fine frequency control are provided by the second frequency detector which uses
data run length violations to pull the VCO within the capture range of the PLL. When the system is
phase-locked the frequency detector output stage is disabled via a lock indication signal. The VCO
output is divided by two to provide the main demodulator clock signal which is compared with the
incoming data in the phase detector. The output of the phase detector, which is combined internally
with the frequency detector outputs at pin 22 (PD/OC), is a positive and negative current pulse with
a net charge that is dependent on the phase error. The current amplitude is determined by the current
source connected to pin 23 (Iref).
The demodulator uses a double timing system to protect the EFM decoder from erroneous sync
patterns in the data. The protected divide-by-588 master counter is reset only if a sync pattern occurs
exactly one frame after a previous sync pattern (sync coincidence) or if the new sync pattern occurs
within a safe window determined by the divide-by-588 master counter. If track jumping occurs the
divide-by-588 master counter is allowed to free-run to minimize interference to the motor speed
controller; this is achieved by taking the CR I input (pin 28) LOW to inhibit the reset signal.
The sync coincidence pulse is also used to reset the lock indication counter and disable the output
from the fine frequency detector. If the system goes out of lock, the sync pulses cease and the lock
indication counter counts frame periods. After 63 frame periods with no sync coincidence pulse, the
lock indication counter enables the frequency detector output.
The EFM decoder converts each symbol (14 bits of disc data + 3 merging bits) into one of 256 8-bit
digital words which are then passed across the clock interface to the subcoding section. An additional
output from the decoder senses one of two extra symbol patterns which indicate a subcoding frame
sync. This signal together with a data strobe and two error flags are also passed across the clock
interface. The error flags are derived from the HFD input and from detected run length violations.
f4-1~---------- 1 Frame = 588 channel bits - - - - - - - - - - - + \
32 \
SYNC
\
SUB \ SYMBOL \
CODING
1
2
\
28
3
29
11 channel
11 channel bits
I + I . - - - - - - - m a y be inverted
bits
----------<~
\1 \2\3\4\ 5\6\71si 9\10 \11 \12\13\141 1 1 I
I.
(1) = merging and low frequency suppression bits.
Fig. 3 Data input signal.
676
September 1985
(
32
format of subcoding or data
symbol - 17 channel bits
format of sync pattern - 27 channel bits
J
30 \ 31
14 bit
EFM Word
.1.
(1)-J
7Z80408
l____
Decoder for compact disc digital audio system
S_A_A_7_2_10______
FUNCTIONAL DESCRIPTION (continued)
Subcoding
The subcoding section has four main functions
•
•
•
•
Q-channel processor
De-emphasis output
Pause (P-bit) output
Serial subcoding output to B-chip
The Q-channel processor accumulates a subcoding word of 96 bits from the Q-bit of successive subcoding symbols, performs a cyclic redundancy check (eRe) using 16 bits and then outputs the
remaining 80 bits to a microprocessor on an external clock. The de-emphasis signal (DEEM) is derived
from one bit of the eRe-checked Q-channel. The DEEM output (pin 32) is additionally protected by a
debounce circuit.
The P-bit from the subcoding symbol, also protected by a debounce circuit, is output via the serial
subcoding signal (SDAB) at pin 34. The protected timing used for the EFM decoder makes this output
unreliable during track jumping.
«
«o
The serial output to the B-chip consists of a burst of 10 bits of data clocked by a burst clock (SCAB).
The 10 bits are made up from subcoding signal bits Q to W, the Q-channel parity check flag, a demodulator error flag and the subcoding sync signal. At the end of the clock burst this output delivers the
debounced P-bit signal which can be read externally on the rising edge of SWAB at pin 33 (see Fig. 4).
II-
Q-CHANNEL PARITY CHECK FLAG
w
2:
(0 = FAIL)
P-BIT
2
0..
SDAB
o...J
W
>
W
o
SUBCODING ERROR FLAG
SYNC (active LOW)
\~r-hr-\r---\r---\r-\r-"\f-"\r---\rhl
P-BIT
I
I
I
I
:I
iI
I
I
\!
I
1\=50% DUTY FACTOR 7,35 kHz
SWAB:
I
I
I
1'1...·- - - - - - - I
I
SCAB
2,8224 MHz BURST CLOCK
7Z80605
Fig. 4 Typical subcoding waveform outputs.
Pre-FIFO
The 10 bits (8 bits of symbol data + 2 error flag bits) which are passed from the demodulator across
the clock interface to the subcoding section are also fed to the pre- F I Fa with the addition of two
timing signals. These two timing signals indicate:
(1) That a new data symbol is valid
(2) Whether the new data symbol is the first symbol of a frame
The pre-F I Fa stores up to 4 symbols (including flags) and acts as a time buffer between data input
and data output. Data passes into the pre-F I Fa at the rate of 32 symbols per demodulator frame and
the symbols are called from the pre-F I Fa into RAM storage at the rate of 32 symbols per errorcorrection frame. The timing, organized by the master controller, allows up to 40 attempts to write
32 symbols into the RAM per error-correction frame. The 8 extra attempts allow for transient changes
in clock frequency (e.g. pitch control).
September 1985
677
____
SAA_72_10_Jl__________________
Data control
This section controls the flow of data between the external RAM and the error corrector. Each symbol
of data passes through the error corrector two times (correction processes Cl and C2) before entering
the concealment section.
The RAM interface uses the full crystal frequency of 11,2 MHz to determine the RAM access waveforms (the main clock for the system is 5,6 MHz). One RAM access (READ or WRITE) uses 12 crystal
clock cycles which is approximately 1 f.ls. The timing (see Fig. 6) is based upon the specification for
the dynamic 16 K x 4-bit RAM (4416). This RAM requires multiplexed address signals and therefore,
in each access cycle, a row address (RAS pin 9) is set up first and then three 4-bit nibbles are accessed
using sequential column addresses (CAS pin 15). As only 10 bits are used for each symbol (including
flags), the fourth nibble is not accessible.
There are 4 different modes of RAM access:
• WRITE 1
• READ 1
• WRITE 2
• READ 2
During WR ITE 1, data is taken from pre-F I Fa at regular intervals and written into one half of the
RAM. This half of the RAM acts as the main FI Fa and has a capacity of up to 64 frames. During
READ 1, the 32 symbols of the next frame due out are read from the FI Fa. The numerical difference
between the WRITE 1 and READ 1 addresses is used to control the speed of the disc drive motor.
When a frame of data has been read from the F I Fa it is stored in a buffer RAM until it can be accepted
by the CI RC error correction system. At this time the error correcting strategy of the CI RC decoder
for the frame is determined by the flag processor. The frame for correction is then loaded into the
decoder one symbol at a time and the 32 symbols from the previous correction are returned to the
buffer RAM.
After the first correction (C1), only 28 of the symbols are required per frame. The symbols are stored
in the buffer RAM together with new flags generated after the correction cycle by the flag updating
logic. This partially-corrected frame is then passed to the external RAM by a WR ITE 2 instruction.
The de-interleaving process is carried out during this second passage through the external RAM. The
WRITE 2 and READ 2 addresses for each symbol provide the correct delay of 108 frames for the
first symbol and zero delay for the last symbol.
After execution of the READ 2 instruction, the frame of 28 symbols is again stored in the buffer RAM
pending readiness of the CI RC decoder and calculation of decoding strategy. Following the second
correction (C2), 24 symbols including unreliable data flags (URD) are stored in the buffer RAM and
then output to the concealment section at regular intervals.
Flag processing
Flag processing is carried out in two parts as follows:
• Flag strategy logic
• Flag updating logic.
While a frame of data from the external memory is being written into the buffer RAM, the error flags
associated with that frame are counted. Two bits are used for the flags, thus 'good ' data (flags == 00)
and three levels of error can be indicated.
The optimum strategy to be used by the CI RC error corrector is determined by the 2-bit flag information used by the flag strategy logic ROM in conjunction with its associated arithmetic unit (ALU). The
flags for the C1 correction are generated in the demodulator and are based on detected signal drop-outs
and data run length violations. Updating of the flags after C1 is dependent on the CI RC decoder correction of that frame. The updated flags are used to determine the C2 strategy. After C2 correction a single
flag (URD) is generated to accompany the data into the concealment section.
678
September 1985
(
DEVELOPMENT DATA
o
LEFT SAMPLE
CI)
C")
RIGHT SAMPLE
o
c..
-
DAAB
~
1
1
~
1
I
I
C")
o
3
1
EFAB
~
~~
LEFT ERROR FLAG
[
RIGHT ERROR FLAG
"C
III
I
I
I
I
1
I
1
1
I
1
1
1
I
I
C")
r+
c..
Ir-~'---------------------------------_~
:
WSAB\
I
1
:
I
I
I
I
I
I
1
I
I
iii·
C")
c..
cC·
[
III
C
c..
o·
CLAB
en
I-
W
Cl
Output current (each output)
10
Storage temperature range
T stg
Operating ambient temperature range
Tamb
Electrostatic handling *
Ves
-0,5 to +7,0 V
-0,5 to V DD +0,5 V
max.
5 rnA
-0,5 to +7,0 V
10 rnA
max.
-55 to +125 oc
-20 to +70 oc
-1000 to +1000 V
* Equivalent to discharging a 100 pF capacitor through a 1,5 kn series resistor with a rise time of
15 ns.
I(
September 1985
681
_ _SA_A72_10_Jl_ _ _ _ _ _ _ __
CHARACTERISTICS
VOO
= 4,5 to 5,5 V; VSS = 0 V; Tamb = -2- to +70 oC unless otherwise specified
parameter
symbol
min.
Supply voltage (pin 40)
VOO
Supply current (pin 40)
100
Input voltage lOW
I nput voltage HI G H
Input leakage current
±I LI
I nput capacitance
CI
typo
max.
4,5
5,0
5,5
V
-
200
tbf
mA
Vil
-0,3
-
+0,8
V
VIH
2,0
-
VOO + 0,5
V
-
-
10
J.1A
-
-
7
pF
unit
Supply
Inputs
01-04,OCl
--MUTE, CRI
Input voltage lOW
Vil
-0,3
-
+0,8
V
Input voltage HI G H
VIH
2,0
-
VOO +0,5
V'
Internal pull-up impedance
at VI = 0 V
IZII
tbf
50
tbf
kn
CI
-
-
7
pF
I nput capacitance
ORA, SWAB
I nput voltage lOW
Vil
-0,3
-
+0,8
Input voltage HIGH
VIH
2,0
-
VOO + 0,5
I nput capacitance
CI
-
-
7
Internal pull-up impedance
at VI = 0 V
IZII
5
10
-
V
V
pF
kn
HFO
I nput voltage lOW
682
Vil
-0,3
-
+0,8
V
Input voltage HIGH
VIH
2,0
-
clamped
V
I nput clamping voltage
at II = 100 J.1A
VCl
-
Input source current
±IS
100
J.1A
CI
-
-
I nput capacitance
-
7
pF
Internal pull-up impedance
at VI = 0 V
IZII
-
50
September
19851 (
3
-
-
V
kn
l____
Decoder for compact disc digital audio system
S_A_A_7_2_10______
parameter
symbol
min.
typo
max.
unit
Outputs
A1-AS, R/W, 01-04, CAS, RAS, CEFM,
OOATA, OEEM, SOAB, SCAB, EFAB,
OAAB, CLAB, WSAB
Output voltage LOW
at -IOL = 1,6 mA
VOL
0
-
0,4
V
Output voltage HIGH
at 10H = 0,2 mA
VOH
2,4
V
CL
-
-
VOO
Load capacitance
-
0,2
V
-
50
pF
0
-
0,4
V
50
pF
5
-
-
kQ
0,25
-
2,5
V
-
50
pF
MSC (open drain)
Output voltage LOW
at -IOL = 1 mA
Load capacitance
0
VOL
CL
-
SWAB, ORA (open drain)
I-
Output voltage LOW
at-IOL=1,6mA
VOL
o
Load capacitance
CL
Internal load resistance
RL
W
o
-
ANALOGUE CIRCUITS
Data slicer
Input HFI
A.C. input voltage range
(peak-to-peak value)
VI(p_p)
Input impedance
normal (HFO HIGH)
disabled (HFO LOW)
IZII
IZII
tbf
tbf
-
tbf
tbf
kQ
kQ
Input capacitance
CI
-
-
7
pF
10
tbf
100
tbf
Il A
kQ
Output FB
Output current
at VFB = 2 V
Phase detector
Output PO/OC
Output impedance
Control range (note 1 )
Gain factor
-
tbf
-
~
±2,1
-
-
rad
G
-
tbf
-
mA/rad
Iref
-
500
tbf
Il A
IZOI
Input Iref
I nput reference current
I
(september 1985
683
___SA_A72_10_Jl_________________
CHARACTE R ISTICS
parameter
typo
symbol
min.
max. unit
IZol
-
2
-
kn
IZol
-
1
-
kn
Kosc
-
tbf
-
MHz/V
Gm
1,5
-
-
mS
Fine frequency detector
Output PO/OC
Output impedance
Coarse frequency detector
Output PO/OC (note 2)
Output impedance
Voltage controlled oscillator
Input PO/OC
Oscillator constant
Crystal oscillator
Input XTAL 1
Output XTAL2
Mutual conductance at 100 kHz
Small signal voltage gain
(G v = Gm x RO)
Gv
3,5
-
-
V/V
I nput capacitance
CI
-
10
pF
-
5
pF
-
10
pF
10
Il A
VOO + 0,5
V
V
Feedback capacitance
CFB
Output capacitance
Co
Input leakage current
±I LI
-
VI(p_p)
1,6
-
Slave clock mode
Input voltage (peak-to-peak value)
684
Input voltage LOW
VIL
-0,3
-
0,8
Input voltage HIGH
VIH
2,4
-
VOO + 0,5
V
Input rise time (note 3)
tr
-
-
20
ns
Input fall time (note 3)
tf
-
-
20
ns
Input HIGH time at 1,2 V
(relative to clock period)
tHIGH
-
65
%
September 1985
(
35
l____
Decoder for compact disc digital audio system
S_A_A_7_2_10______
CHARACTERISTICS (continued)
symbol
min.
typo
Operating frequency (XTAL)
fXTAL
10,16
11,2896
12,42
MHz
Operating frequency (VCO)
coarse frequency detector inactive
no input pin 25 (HFI)
fVC01
fVC02
fXTAL/2
4
8,6436
fXTAL
15
MHz
MHz
parameter
max. unit
TIMING
-
Outputs (see Figs. 8 and 9)
CEFM (note 4)
tHIGH
50
-
Output rise time
tr
-
l-
Output fall time
tf
o
DAAB, WSAB, EFAB to CLAB
IZ
Data set-up time
:E
0-
CLAB to DAAB, WSAB, EFAB
...J
Data hold time
20
ns
20
ns
-
ns
-
20
ns
-
-
20
ns
tsu; OAT
100
-
-
ns
tHO; OAT
100
-
-
ns
-
-
20
ns
-
20
ns
tsu; SDAT
100
-
-
ns
tHD;SDAT
100
-
-
ns
-
-
1
-
100
ns
-
50
-
%
Output rise time
tr
-
Output fall time
tf
-
Output HIGH time
DAAB, CLAB, WSAB, EFAB (note 4)
(data to B-chip; 1 2 S format)
e:(
e:(
w
o
W
>
W
o
SDAB, SCAB, DEEM (note 4)
(subcoding outputs)
Output rise time
tr
Output fall time
tf
SDAB to SCAB
Subcoding data set-up time
SCAB to SDAB
Subcoding data hold time
SWAB (note 4)
Output rise time
tr
Output fall time
tf
Output duty factor
1
fJ.S
(september 1985
685
~1
___S_AA_721_0~jl_________________
CHARACTERISTICS (continued)
symbol
parameter
min.
typo
max. unit
Q-channel I/O (see Figs. 12 and 13)
ORA, OCl, OOATA
Access time (note 5)
normal mode
tACC; F
13,3
-
13,3 +
n x 13,3
n x 13,3
tOACK
-
-
500
ns
tHO; R
500
-
-
ns
OCl clock input lOW time
tCK; lOW
500
-
-
ns
OCl clock input HIGH time
tCK; HIGH
500
-
-
ns
OCl to OOATA delay time
too
-
-
500
ns
Data hold time before
new frame is accessed
tHO; ACC
2,3
-
-
ms
tACK
-
-
10,8
ms
refresh mode
OCl to ORA acknowledge delay
OCl to ORA request hold time
Acknowledge time
tACC; N
0
-
ms
ms
Notes to the characteristics
1800
1.1 rad == - - .
(3,14)
2. Coarse frequency detector output PO/OC active for VCO frequencies> fXTAl and
3. Reference levels == 1 V and 2,4 V.
4. Output rise and fall times measured with load capacitance (CLl == 50 pF.
5. O-channel access times dependent on cyclic redundancy check (CRC).
686
September 1985
(
<
fXTAl.
2
l____
Decoder for compact disc digital audio system
S_A_A_7_2_10______
CLAB
DAAB
WSAB
EFAB
Fig.8 Typical data output waveforms to B-chip or DAC: reference levels = 0,8 V and 2,0 V.
«
l-
SCAB
e:(
o
I-
Z
w
:2:
c..
o-I
SDAB
W
>
W
o
Itt It,
SWAB
Fig.9 Typical subcoding data output waveforms: reference levels for SCAB and SDAB
reference levels for SWAB = 0,8 V and 4,0 V.
I
= 0,8 V
and 2,0 V;
(september 1985
687
___S_AA_721_0_Jl_________________
APPLICATION INFORMATION
E FM Encoding system
The Eight-to-Fourteen Modulation (EFM) code used in the Compact Disc Digital Audio system is
designed to restrict the bandwidth of the data on the disc and to present a d .c. free signal to the demodulator. In this modulation system the data run length between transitions is ~ 3 clock periods and
~ 11 clock periods. The number of bits per symbol is 17, including three merging and low frequency
suppression bits which also assist in the removal of the d.c. content.
The conversion from 8-bit, non-return-to-zero (NRZ) symbols to equivalent 14-bit code words is
shown in Table 2. C1 is the first bit of a 14-bit code word read from the disc and D1 is the Most
Significant Bit (MSB) of the data sent to the error corrector. The 14-bit code words are given in N RZ-I
representation in which a logic 1 means a transition at the beginning of that bit from HI G H-to-LOW
or LOW-to-HIGH (see Fig. 10).
o
CODED NRZ-I
DECODED EQUIVALENT
1 001 000 1 000 001 0 0 0 0
r'I ___. .
OR
7Z80609
Fig. 10 Non Return to Zero (NRZ) representation.
The codes shown in Table 2 cover the normal 256 possibilities for an 8-bit data symbol. There are other
combinations of 14-bit codes which, although they obey the EFM rules for maximum and minimum
run length (T max, T min), produce unspecified data output symbols. Two of these extra codes are used
in the subcoding data to define a subcoding frame sync and are as shown in Table 1.
Table 1 Codes used to define subcoding frame sync
r----------------------------------------------------- ------------,-----------------------------------------------------------------------------------------------------------------------1
I
8-bit N RZ data symbol
I
14-bit equivalent code word
I
~-----------T------T------i------T------T----T------T-------r------j-------I--------r----r------j"----r----r------T------T--------r-------j--------r--------j---------------1
II 011021031041051061071
OalCl IC21C3 IC41C5 IC61 C71 cal C91Cl0 IClll C121 C131C14
II
I
I
I
I
I
I
I
I
I
I
I
I
I
I I
I
I
I
I
I
I
r-----------t------1-------I------1--------1-----+------t------t------1------1-------1------1------+-----1-----1-------t------+--------+-------I--------1---------1---------------1
I x: 0 I 0 I 1 1 1 : 1 : 1 : 1 I 0 10 : 1 10 10 10 101 0 I 0 I 0 I 0 I 0 I 0 I 1 I
I x 11: 111: 1 : 1 I 0 11 : 0 10 : 0 10 : 0 10 10: 0 10 I 1 10 I 0 I 1 I 0 I
~-----------+-----+----+----+------l----+-----+------t- _____ L ___L ____ L ___ L ___ L ___ L __ L ____ L ____ L _____ L _____ L ______1... ______ L_____________ .1
I
plOIRISITIUIVIWI
L__________ L_____L______ ~ ______ ~ ________ ~ ______ ~ _______,______ !
Where: X = don't care state.
When a subcoding frame sync is detected the P-bit (Pause-bit) of the data is ignored by the debounce
circuitry. The remaining bits (0 to W) are not specified in the system but always appear at the serial
output as shown in Table 1.
688
September 1985
(
DEVELOPMENT DATA
cCD
Table 2 E F M code conversion
n
o
No.
I ONZ data symbol
01
08
equivalent code word
C1
No.
C14
01
c..
equivalent code word
ONZ data symbol
08
CD
....
~
C14
C1
~
n
o
0 0
o0
2
0 0
300
4
0 0
500
0 0
6
7
o0
o0
8
0 0 0 000
000 001
0 0 0 0 1 0
0 0 001 1
0 0 0 1 0 0
000 1 0 1
000 1 1 0
0 0 0 1 1 1
0 0 1 0 0 0
o0
o0
0 0 1 0 0 1
0 0 1 0 1 0
9
10
11
en
CD
.-+
CD
3
C'"
~
co
(Xl
(J'1
001
1 0 000
100 1 0
1 000 1
o 1 000
o 0 000
000 1 0
I
I
000 1
1 000
0 0 0 1
000 1
1 0 0 0
1 000
0 001
0 0 0 0 0
0 0 000
0 0 000
000 0 0
0 000 0
1 0 0 0 0
0 0 000
0 0 1 0 0 1 0 0 0 0 0 0 0 0
0 1 0 0 1 0 0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0 0 0 0
1 0 0 1 0 0 0 1 0 0 0 0 0 0
o 1 001
o0 0 0
134
1 0 0 0 0 0 0 0
1 000 000 1
1 0 0 0 001 0
10000011
1 0 0 0 0 1 0 0
1 000 0 1 0 1
1 0 0 0 0 1 1 0
135
136
137
138
0 0 0 0 1 1 1
0 0 0 1 0 0 0
10001001
100 0 001 0
0 0 1 0 0 1 0 0 1 0 0
0 1 0 0 1 0 0 1 0 0 0
000000100 0
001 000 1 000
128
129
130
131
132
133
I
1
to
119
247
248
125
126
127
000 1
1 001
100 1 000 0 1
1 000 1 000 1
o 1 000 1 001
o 0 0 0 0 0 001
000 1 000 0 1
000 0 1
0 0 0 0 1
0 0 001
0 0 001
0 0 001
0 0 0 0 1
0 0 0 0 1
0
0
0
0
0
0
0
0
1
1
1
1
001
001
001
001
001
001
001
001
0
0
0
0
0
0
0
0
o
3
't:I
II)
n
r+
c..
in'
n
c..
ca'
~
II)
c
o·c..
-<
III
Cit
3
139
to
120
121
122
123
124
"0
o1
o1
0 0 0
o1
o
0 0 1
o0
1
o1
010
o 1 1 1 101 1
o1
0 0
o1
0 1
o
o
1
1
1 1 1 1 0
1 1 1 1 1
001
0 0 1
100 1 0
1 000 1
0 1 000
0 0 0 0 1
0 0 0 0 000 1 0
001 001 000
0 0 0 0 000 1 0
0 0 000 001 0
0 0 0 0 000 1 0
000 0 0 001 0
000 1 0 0 0 0 0 000 1 0
001 0 0 0 0 0 0 0 0 0 1 0
249
250
251
252
253
254
255
000
001
010
o1
1
100
o1
1 0
1 1
o
1 001 000 0 1
1 0 0 0 0 0 0 0 0 1
100 1 0 0 0 0 0 1
1 000 1 0 0 001
o10 0 0 0 0 0 0 1
o 0 0 0 1 0 000 1
000 1 0 0 000 1
001 000 0 0 0 1
(J)
»
»
"'"
I\)
~
0)
co
co
o
_Jl________
__
SA_A72_10
APPLICATION INFORMATION (continued)
Subcoding microprocessor handshaking protocol (see Figs. 11, 12 and 13)
The ORA line is normally held lOW by the microprocessor.
When the microprocessor needs data (Request) it releases the ORA line and allows it to be pulled HIGH
by the pull-up resistor in the SAA721 O.
The SAA7210 is continuously collecting O-channel data and when it detects that ORA is HIGH it holds
the first frame of O-channel data for which the Cyclic Redundancy Check (CRC) is 'good '. Then the
SAA7210 pulls ORA lOW to tell the microprocessor that the data is ready (Acknowledge) and enables
the OOA T A output.
When the microprocessor detects a ORA lOW signal it generates a clock signal (OCL) to shift the data
out from the SAA7210 to the microprocessor via the OOATA output. The first negative edge of OCl
also resets the acknowledge signal and thus releases the ORA line.
As soon as the microprocessor has received sufficient data (not necessarily 80 bits) it pulls the ORA
line LOW again. The SAA7210 now disables the OOATA output and resumes collecting new O-channel
data.
If the microprocessor does not generate a OCl signal within 10,8 ms from the start of the acknowledge
(ORA lOW), the SAA7210 resets the acknowledge signal and allows the ORA line to go HIGH again.
The microprocessor still has 2,3 ms to accept the data, which allows for a long propagation delay in
the microprocessor. After a further 13,33 ms the SAA721 0 will have received a new frame of O-channel data and, provided the CRC is 'good', will give a fresh acknowledge signal. This refreshing process
is repeated until the microprocessor accepts the data or stops the request.
When the microprocessor has a requirement to hold the data for a long period before acceptance, it
prevents the refreshing process by setting OCl lOW after any acknowledge signal.
+
MICROPROCESSOR
ORA
30
o DATA
29
DATA
ENABLE
OCL
31
> - -....... CLOCK
7Z80610
Fig. 11 Microprocessor handshaking protocol.
690
September 1985
(
l___
Decoder for compact disc digital audio system
S_A_A_7_2_10_ __
DATA REQUEST
(microprocessor
internal signal)
I
ACKNOWLEDGE
(SAA7210
internal signal)
-- 1-
I
-- (
tHD;R
\..-tDACK
(
ORA
I
I
tCK; LOW
tCK; HIGH
-\\- -\\-
LIU1JUUUlJ
OCL
-litDD
r-------------~
QDATA _____h_i~gh__
im~p_e_da_n_c_e~
high impedance
Q1
7Z80611
Fig. 12 Q-channel timing waveforms (normal mode).
«
«
o
I-
I2:
w
:!:
c..
o
..J
DATA REQUEST
(microprocessor
internal signal)
~--------------~I
~--~~~---------
W
>
W
o
ACKNOWLEDGE
(SAA721 0
internal signal)
ACCESS FRAME
~
rr-tACC;N
QRA
1.....- - - -
tACK - - - - -
QCL
QDA
-------------i(
I.
H
Q1
Q1
~
this will repeat
__
until QCL goes LOW
.
7Z80612
Fig. 13 Q-channel timing waveforms (refresh mode).
'I
(september 1985
691
SAA7220
DIGITAL FILTER FOR COMPACT DISC DIGITAL AUDIO SYSTEM
GENERAL DESCRIPTION
The SAA7220 is a stereo interpolating digital filter designed for the Compact Disc Digital Audio system.
For descriptive purposes, the SAA7220 is referred to as the B-chip and the SAA7210 as the A-chip.
Features
•
•
•
•
•
16-bit serial data input (two's complement)
Interpolated data replaces erroneous data samples
-12 dB attenuation via the active LOW attenuation input control (ATSB)
Smoothed transitions before and after muting
Two identical finite impulse response transversal filters each with a sampling rate of four times that
of the normal digital audio data
• Digital audio output of 32-bit words transmitted in biphase-mark code
• 12 S data transfer between SAA7210, SAA7220 and 16-bit dual DAC (TOA 1541)
QUICK REFERENCE DATA
parameter
conditions
Supply voltage (pin 24)
Supply current (pin 24)
symbol
min.
typo
max.
unit
VOO
4,5
5,0
5,5
V
100
100
180
285
rnA
VIL
-0,3
-
+ 0,8
V
VIH
2,0
-
VOO+0,5
V
I nput voltage ranges
WSAB,OAAB,EFAB,SOAB
note 2
CLAB, SCAB, ATSB, MUSB
note 3
Input voltage LOW
note 1
Input voltage HIGH
note 1
Output voltage ranges
OABO, CLBO, WSBO
Output voltage LOW
IOL = 0,8 rnA
VOL
0
-
0,4
V
Output voltage HIGH
IOH= 0,2 rnA
VOH
2,4
-
VOO
V
VL(p-p)
0,4
-
0,6
V
fXTAL
10,16
11,2896 12,42
-20
-
OOBM
Voltage across a 75 n
load via attenuator
(peak-to-peak value)
Operating frequency
XTAL
Operating ambient
temperature range
see Fig. 10
Tamb
For explanation of notes see "Notes to the characterIStiCS".
+ 70
MHz
°C
PACKAGE OUTLINE
SAA7220P/A: 24-lead 01 L; plastic (with internal heat spreader) (SOT101A).
1(
April 1987
693
0)
co
~
(J)
V~+5V)
MUSB ATSB
XSYS
XOUT
»»
""'-J
XIN
23
:x:-
-g.
co
WSAB
CLAB
DAAB
EFAB
L
I\)
I\)
o
00
-....J
18 1
~
WSBD
15 1
•
DABD
DIGITAL AUDIO OUTPUT
14
13
7Z80749
TEST
SCAB
SDAB
DOBM
Where:
IPSR
IISR
Input Shift Register
IOSR = Intermediate Output Shift Register
Intermediate Input Shift Register
FDSR = Filter Data Shift Register
Fig. 1 Digital filter block diagram.
o
[
cE'
from timing
and control
~
ii
...
from left
Q
n
o
3
'C
I»
SCAB
nr+
0...
iii'
n
0...
cC'
[
SDAB
I»
C
0...
0'
(II
<
~
3
DATA
SELECT 1
DOBM
LEFT AOSR
,mm"'1
IOSR
RIGHT AOSR
I
•
»
-g,
7Z80750
Where:
co
ex>
-...J
SISR
SOSR
=
=
Subcode Input Shift Register
Subcode Output Shift Register
IOSR
AOSR
*
= Intermediate Output Shift
Register
= Audio Output Shift Register
= Subcode word error flag
Fig, 2 Digital audio output block diagram.
0)
co
U'I
(j)
»
»
~
I\)
I\)
o
___SA_A72_20_Jl_________________
PINNING
VDD
MUSB
ATSB
n.c.
n.c.
n.c.
WSBD
n.c.
CLBD
DABD
XOUT
DOBM
TEST
VSS
7Z80740
Fig. 3 Pinning diagram.
Pin functions
pin no.
696
mnemonic
description
WSAB
Word Select: input from A-chip.
2
CLAB
Clock: input from A-chip; has an internal pull-up.
3
DAAB
Data: input from A-chip.
4
EFAB
Error Flag: active HIGH input from A-chip indicating unreliable
data. This input has an internal pull-down.
5
n.c.
not connected.
6
SCAB
Subcode Clock: a 10-bit burst clock 2,8224 MHz (typ.) input
which synchronizes the subcode data. This input has an internal
pull-up.
7
SDAB
Subcode Data: a 10-bit burst of data, including flags and sync
bits serially input from the A-chip once per frame clocked by
burst clock input SCAB (see Fig. 8). This input has an internal
pull-down.
8
n.c.
not connected.
9
XSYS
System clock output: 11,2896 MHz (typ.) output to DAC and to
A-chip as slave clock input.
10
XOUT
Crystal oscillator output: drive output to clock crystal
(11,2896 MHz typ.).
11
XIN
Crystal oscillator input: input from crystal oscillator or slave
clock.
April
19871 (
Digital filter for compact disc digital audio system
l____
S_AA_7_2_2_0______
pin no.
mnemonic
description
Ground: circuit earth potentional.
13
VSS
TEST
14
DOBM
Digital audio output: this output contains digital audio samples
which have received interpolation, attenuation and muting plus
subcode data. Transmission is by biphase-mark code.
15
DABD
Data: this output which is fed to the DAC, together with its clock
(CLBD) and word select (WSBD) outputs, conforms to the 12S
format (see Fig. 7).
12
1
Test input: this input has an internal pull-down. In normal operation pin 13 should be open-circuit or connected to VSS.
16
CLBD
Clock: output to DAC.
17
n.c.
not connected.
18
WSBD
Word Select: output to DAC.
19
n.c.
not connected.
20
n.c.
not connected.
21
n.c.
not connected.
22
ATSB
Attenuation: when active LOW this control input provides -12 dB
attenuation. This input has an internal pull-up.
23
MUSB
Mute: active LOW control input with internal pull-up.
24
VDD
Power Supply: positive supply voltage (+ 5 V).
FUNCTIONAL DESCRIPTION
General
The SAA7220 incorporates the following functions:
•
•
•
•
•
Interpolation of data in error
Attenuation
Muting
Finite impulse response transversal filtering with a four times increased sampling rate
A digital audio output
Serial data formatted in two's complement (DAAB; pin 3) is clocked in by its bit clock (CLAB; pin 2)
together with word select (WSAB; pin 1) and error flag (EFAB; pin 4) as shown in Fig. 1. After
resynchronization with the internal clocks the data is separated into left and right channels and fed to
two identical Input Shift Registers (lPSR). Internal timing and control loads the data into the interpolation RAM via the Intermediate Input Shift Register (lISR).
After interpolation, attenuation and muting the data is fed serially from the Intermediate Output
Shift Register (IOSR) to the Audio Output Shift Register (AOSR) and to the IISR. From the IISR it
is loaded into the filter RAM.
After filtering the data is passed to the Filter Data Shift Register (FDSR). From the FDSR it is
transmitted serially to the data output (DABD; pin 15) together with the appropriate word select
(WSBD; pin 18) and bit clock (CLBD; pin 16), in accordance with the 12S bus specification. Data is
again formatted in two's complement. Outputs DABD, WSBD and CLBD are strobed to maintain the
correct timing relationship with the system clock output (XSYS) at pin 9 (see Fig. 13).
1(
April 1987
697
FUNCTIONAL DESCRIPTION (continued)
The subcode data (SDAB; pin 7) and 1a-bit burst clock (SCAB; pin 6) are resynchronized to the internal clocks within the digital audio output block. SCAB clocks the data into the Subcode Input Shift
Register (SISR; Fig. 2). Data is transferred to the Subcode Output Shift Register (SOSR) on receipt
of all of the 1a-bit burst clocks. The subcode data is then mixed with the data from the AOSR and
the error flag to provide the output DOBM at pin 14. SISR is reset when no clocks are detected on the
SCAB input.
Interpolation
When, for either left or right channel, unreliable samples are flagged between two correct samples,
linear interpolation is used to replace the erroneous samples (up to a maximum of 8 consecutive
errors) .
When the error flag is set, the sample is replaced by a value calculated by the following formula:
x
1
S(n) == . S(n-1) + . S(n+x)
x+1
x+1
Where: S(n)
x
S(n-1)
S(n+x)
new sample value
number of successive erroneous samples following S (n-1)
the preceding sample
the first following correct sample
The value of x is detected (1 to 8) to determine the coefficients for the multiplications. Eight coefficient pairs are stored in the ROM. If x == a or ~ 9 then S(n) will remain unchanged.
I I I I I I I I
error flag
7Z80741
?
= sample interpolated or held in A-chip
I
Fig. 4 Example of an eight sample linear interpolation.
698
April
19871 (
Digital filter for compact disc digital audio system
l__
S_A_A_7_2_20_ __
Attenuation
Attenuation is controlled by the ATSB input at pin 22. When the input is active LOW the sample is
multiplied by a coefficient that provides -12 dB attenuation. If the input is HI G H the multiplication
factor is 1.
Mute
Mute is controlled by the MUSB input at pin 23. When the input is active LOW the value of the
samples is decreased smoothly to zero following a cosine curve. 32 coefficients are used to step down
the value of the data, each one being used 31 times before stepping onto the next. When MUSB is
released (pin 23 HIGH) the samples are returned to the full level again following a cosine curve with
the same coefficients being used in the reverse order.
Filtering
The SAA7220 incorporates two identical finite impulse response transversal filters with the equivalent
of 120 taps, one filter for each stereo channel. The corresponding 120 coefficients are structured as
4 sections of 30 coefficients.
(Each ROM contains only 60 filter coefficients, the same 60 being used a second time, but in the
reverse order, to make a total of 120.) Plotsofthefilter characteristics are shown in Fig. 16.
Data is stored in a 480-bit RAM (30 words x 16 bits). The 30 words are sequentially addressed 4 times
to generate the 4 output samples.
When a new word is moved from the interpolation RAM to the filter RAM, the oldest word is discarded
and all other words moved one position with respect to the ROM coefficients. The data storage
effectively forms a 30 sample wide moving window on the input data. The samples move within this
window at 5,6448 MHz and the window moves one sample every 22,6 MS.
An output word is formed by mUltiplying 30 samples from the filter RAM with 30 coefficients from
the ROM using a 16 x 12 array multiplier. The result is added in an accumulator. At the end of the
30 multiplications the 16 MSB's are passed from the accumulator via the IOSR to the FDSR, and the
accumulator is reset. Overflow protection is incorporated so that the output always limits cleanly in
the event of accumulator overflow. Also, to simplify the design of the digital-to-analogue converter a
d.c. offset of + 5% is added to the accumulator.
The filtered data is output in the
2
1
S format at a 5,6448 MHz bit rate and a sample rate of 176,4 kHz.
Digital audio output
Audio 16-bit samples and subcode data are formatted according to the Philips/Sony proposal; "Digital
audio interface for domestic use" (Reference Philips 'Red Book' CD-DA standard specification).
The digital audio output (DOBM; pin 14) consists of 32-bit words transmitted in biphase-mark code.
That is, two transitions for a logic 1 and one transition for a logic O. The 32-bit words are transmitted
in blocks of 384 words. Table 1 shows the information contained in each word.
The sync word is formed by violation of the biphase rule and therefore does not contain any data. Its
length is equivalent to 4 data bits. The three different sync patterns (B, M and W) indicate the following situations:
• Sync B; start of a block of 384 words, contains left sample (11101000)
• Sync M; word contains left sample, but is not a block start (11100010)
• Sync W; word contains right sample (11100100)
I n the SAA7220 sync words are always preceded by O. A typical biphase-mark code output is shown in Fig. 11.
Left and right samples are transmitted alternately.
Audio samples are available for digital audio output after interpolation, attenuation and muting, but
before filtering.
Data held in the Subcode Output Shift Register (SOSR) is transmitted via the user data bit and is
asynchronous with the block rate.
1(
April 1987
699
___S_AA7_22_0_Jl_________________
Digital audio output (continued)
Table 1 Composition of the 32-bit digital audio output word
bit number
description
1 to 4
5to 8
9to 28
sync
auxiliary
audio sample
29
30
31
32
audio valid
user data
channel status
parity bit
information
not used (always zero)
bits 9 to 12 not used (always zero).
bits 13 (LSB) to 28 (MSB) two's complement
copy of the error flag
used for subcode data
indication of control bits and category code
even parity for all word bits excluding sync pattern
Channel status
The channel status bit is the same for both left and right words. Therefore a block of 384 words
contains 192 channel status bits as shown in Table 2.
When there is no subcode the channel status will switch over to the general format. ' No subcode' is
identified by the subcode detector when SCAB is a continuous HIGH or LOW.
Table 2 Channel status bit assignment
bit number
description
subcode provided
no subcode provided
1 to 4
control
copy of Q channel
5 to 8
9 to 16
reserved
category code
always zero
CD category
bit 9 logic 1
always zero
bits 1 and 2 zero
bit 3 image of SCAB
bit 4 image of SDAB
always zero
general category
all bits zero
always zero
17 to 192
If a subcode clock is provided but there is no subcode data (SDAB is a continuous HIGH or LOW) the
control bits will be zero and the category code will be CD.
The SYNC bit and the cyclic redundancy check bit (CRC) in the subcode data from the A-chip to the
B-chip have the format shown by Fig. 5. Typical subcode data input waveforms are shown by Fig. 8.
700
April 1987! (
l____
Digital filter for compact disc digital audio system
S_A_A_72_2_0____
SYNC
SO
S1
SO
S1
CRC error bit
~----------75Hz----------~
7Z80742
Fig. 5 Subcode data format for SYNC and CRC bits.
SYNC is active LOW and indicates the start of a subcode block, which contains 98 words including
2 sync words, SO and S1.
CRC is always LOW except during SYNC S1 when:
• CRC
• CRC
= logic 1; previous Q
= logic 0; previous Q
block was true
block was false
Two 32-bit words are transmitted at the sample frequency of 44,1 kHz (2 x 32 x 44,1 kHz = 2,8224
Mbits/s data rate). An internal 5,6448 MHz clock (XSYS/2) is used in the biphase modulator.
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
symbol
min.
typo
max.
unit
Supply voltage range (pin 24)
VOO
-0,5
V
VI
-0,5
-
+ 7,0
Maximum input voltage range
VOO+O,5
V
Storage temperature range
T stg
-55
-
+ 125
°C
Operating temperature range
Tamb
-20
-
+ 70
°C
Ves
-1000
-
+ 1000
V
parameter
Electrostatic handling*
Ensure no electrical connections are made to the underside or ends of the package as there is the
possibility of making accidental connection to the lead frame and/or internal heat spreader of the device.
* Equivalent to discharging a 100 pF capacitor through a 1,5 kQ series resistor with a rise time of
15 ns.
'I (
April 1987
701
~
___S_AA_722_0_Jl_________________
CHARACTERISTICS
VOO = 4,5 to 5,5 V; VSS = 0 V; T amb = -20 to + 70 °C unless otherwise specified
parameter
unit
symbol
min.
typo
max.
VOO
4,5
5,0
5,5
V
100
100
180
285
rnA
VIL
-0,3
-
+ 0,8
V
-
VOO+0,5
V
-
Supply
Supply voltage (pin 24)
Supply current (pin 24)
Inputs
WSAB,OAAB
Input voltage LOW (note 1)
Input voltage HIGH (note 1)
VIH
2,0
Input leakage current
at VI = 0 V
at VI = VOO
III
III
-10
-
-
+10
p.A
p.A
I nput capacitance
CI
-
-
7
pF
Input voltage LOW (note 1)
VIL
-0,3
-
+ 0,8
V
Input voltage HIGH (note 1)
VIH
2,0
-
VOO+0,5
V
I nput leakage cu rrent
at VI = 0 V
at VI = VOO
III
III
-10
-
-
-
+ 50
p.A
p.A
I nput capacitance
CI
-
-
7
pF
VIL
-0,3
-
+ 0,8
V
VOO+0,5
V
EFAB, SOAB (note 2)
CLAB, SCAB, ATSB, MUSB (note3)
Input voltage LOW (note 1)
I nput voltage HI G H (note 1)
VIH
2,0
-
Input leakage current
at VI = 0 V
at VI = VOO
III
III
-30
-
-
+ 10
p.A
p.A
I nput capacitance
CI
-
-
7
pF
Mutual conductance at 100 kHz
Gm
1,5
-
-
mA/V
Small signal voltage gain
(Av= Gm x RO)
Crystal oscillator (see Fig. 9)
Input XIN
Output XOUT (note 4)
702
Av
3,5
-
-
V/V
I nput capacitance
CI
-
-
10
pF
Feedback capacitance
CFB
-
-
5
pF
Output capacitance
Co
-
-
10
pF
Input leakage current
at VI = 0 V
at VI = VOO
III
III
-10
-
-
-
+10
p.A
p.A
April
19871 (
l___
Digital filter for compact disc digital audio system
S_A_A_7_2_2_0______
unit
symbol
min.
typo
max.
Input voltage (note 5)
(peak-to-peak value)
VI(p_p)
1,6
-
VOD + 0,5
I nput voltage LOW (note 6)
VIL
a
-
1
V
I nput voltage HI G H (note 6)
VIH
2,4
-
VOD + 0,5
V
Input rise time (note 7)
tr
-
-
20
ns
Input fall time (note 7)
tf
-
-
20
ns
Input HIGH time at 2 V
(relative to clock period)
tHIGH
35
-
65
%
parameter
Slave clock mode
V
Outputs (note 4)
DABD,CLBD,WSBD
Output voltage LOW
at IOL = 0,8 mA
VOL
a
-
0,4
V
Output voltage HI G H
at -IOH = 0,2 mA
VOH
2,4
-
VDO
V
-
50
pF
-
0,4
V
VDD
V
-
50
pF
0,4
-
0,6
V
-
+ 0,05
V
Load capacitance
CL
-
XSYS (note 8)
Output voltage LOW
VOL
a
Output voltage HIGH
VOH
2,4
Load capacitance
CL
-
DOBM
Voltage across a 75 Q load
via attenuator; see Fig. 10
(peak-to-peak value)
VL(p-p)
D.C. offset voltage
VLDC
-0,05
fXTAL
10,16
TIMING
Operating frequency (XTAL)
12,42
11,2896
MHz
Inputs (see Fig. 12)
SCAB, CLAB (note 9)
SCAB clock frequency
(burst clock)
fSCAB
-
2,8224
-
MHz
C LAB clock frequency
or (note 10)
fCLAB
fCLAB
-
2,8224
1,4112
-
MHz
MHz
Clock LOW time
tCKL
110
-
ns
Clock HIGH time
tCKH
110
-
ns
Input rise time
tr
20
ns
20
ns
Input fall time
tf
-
-
-
1(
April 1987
703
_Jl_________
__
SA_A72_20
CHARACTERISTICS (continued)
parameter
symbol
min.
typo
max.
-
-
ns
-
ns
unit
DAAB, WSAB, EFAB (note 11)
Data set-up time
tsu; DAT
40
Data hold time
tHD; DAT
0
Input rise time
tr
-
Input fall time
tf
-
Subcode data set-up time
tsu; SDAT
40
Subcode data hold time
tHD;SDAT
0
I nput rise ti me
tr
-
Input fall time
tf
tsu;WS
20
ns
20
ns
-
-
ns
-
-
ns
-
20
ns
-
-
20
ns
40
-
-
ns
-
-
ns
SDAB (note 12)
Outputs (see Figs 13 and 14)
WSBD (notes 9 and 13)
Word select set-up time
Word select hold time
0
tHD;WS
WSBD (note 9)
Output rise time
Output fall time
tr
-
-
20
ns
tf
-
-
20
ns
tsu; DATD
40
-
-
ns
tHD; DATD
0
-
-
ns
DABD (notes 9 and 13)
Data set-up time
Data hold time
DABD (note 9)
Output rise time
tr
-
-
20
ns
Output fall time
tf
-
-
20
ns
161
177
197
ns
-
-
ns
-
ns
-
ns
CLBD (notes 9 and 13)
Clock period
tCK
Clock LOW time
tCKL
65
Clock HIGH time
tCKH
65
Clock set-up time
tsu; CLD
40
-
Clock hold time
tHD; CLD
0
-
ns
CLBD (note 9)
Output rise time
tr
20
ns
tf
-
-
Output fall time
-
20
ns
Data set-up time
tsu; DATBD
40
-
-
ns
Data hold time
tHO; DATBD
60
-
-
ns
DABD (notes 9 and 14)
704
April
19871 (
l____
Digital filter for compact disc digital audio system
S_A_A_72_2_0______
symbol
parameter
min.
typo
max.
unit
Outputs (continued)
WSBD (notes 9 and 14)
Word select set-up time
tsu; DATWSD
40
-
-
ns
Word select hold time
tHO; DATWSD
60
-
-
ns
Output rise time
tr
-
-
20
ns
Output fall time
tf
-
-
20
ns
Data bit 0 (note 16)
pulse width HIGH
pulse width LOW
tHIGH(O)
tLOW(O)
336
336
354
354
372
372
ns
ns
Data bit 1 (note 17)
pulse width HIGH
pulse width LOW
tHIGH(l )
tLOW(l)
172
172
177
177
182
182
ns
ns
DOBM (note 15)
XSYS
Output rise time (note 9)
tr
-
-
20
ns
Output fall time (note 9)
tf
-
-
20
ns
Output HIGH time at 2 V
(relative to clock period)
tHIGH
35
-
65
%
INTER'le
I~B
SOUND
Purchase of Philips' 12 S components conveys a license under the
Philips' 12S patent to use the components in the 12 S-system
provided the system conforms to the 12S specification defined
by Philips.
A Philips publication "1 2S bus specification" is available on request.
I(
April 1987
705
Jl__________________________________
_____S_A_A_7_22_0___
Notes to the characteristics
1. Minimum V I L and maximum V I H are peak values to allow for transients.
2.
Inputs EFAB and SDAB both have internal pUIl-downs.
3.
Inputs CLAB, SCAB, ATSB and MUSB have internal pUll-ups.
4. All outputs are short-circuit protected except crystal oscillator output.
5.
If used in a.c. coupled mode.
6. VIH - VIL ~ 1,6 V.
7.
Reference levels = 10% and 90%.
8. The output current conditions are dependent on the drive conditions.
When a crystal oscillator is being used the output current capability is IOL = + 0,8 rnA;
IOH = -0,2 rnA. But if a slave input is being used the output currents are reduced to IOL = + 0,2 rnA;
IOH = -0,2 rnA.
9.
Reference levels = 0,8 V and 2,0 V.
10. The signal CLAB can run at either 2,8 MHz (1/4 system clock) or 1,4 MHz (1/8 system clock) under
typical conditions. It does not have a minimum or maximum frequency, but is limited to being 1/4
or 1/8 of the system clock frequency.
11. Input set-up and hold times measured with respect to clock input from A-chip (CLAB). Reference
levels = 0,8 V and 2,0 V.
12. Input set-up and hold times measured with respect to subcode burst clock input from A-chip (SCAB).
Reference levels = 0,8 V and 2,0 V.
13. Output set-up and hold times measured with respect to system clock output (XSYS).
14. Output set-up and hold times measured with respect to clock output (CLBD).
15. Output rise and fall times measured between the 10% and 90% levels; the data bit pulse width
measured at the 50% level.
16. Data bit a pulse width times are typically system clock period (1/fXTAL) x 4. Maximum and minimum values are ± 5% of this time. Values shown are for fXTAL = 11,2896 MHz, but these will
change accordingly if fXTAL changes.
17. Data bit 1 pulse width times are typically system clock period (1/fXTAL) x 2. Maximum and minimum values are ± 2,5% of this time. Values shown are for fXTAL = 11,2896 MHz, but these will
change accordingly if fXTAL changes.
706
April
19871 (
o
LEFT SAMPLE
ce'
[
RIGHT SAMPLE
DAAB
:n
---~I
I
I
I
I
EFAB
~
i
LEFT ERROR FLAG
~
I
I
~ ~--+-i----------R-IG-H-T-E-R-R-O-R-F-L-A-G---
~
n
o
3
"C
:
I
I
I
I
:
I
I
I
:
WSABI
:
I
I»
I
I
I
I
c..
I
I
....n
~I_~I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
n
c..
_~
i
iii'
ce'
[
I
I
I»
I
I
I
c:
c..
o·
-
w
o
1 _ - - - - - fIBIFA> fIOSCl/4-_ _ _ _
-I.~I ---~..
flBIFA .. f i OSCl /4
flBIFA
W
o
• User data/pre-emphasis output signal (OSDU). After receiving a category code of mode 0 from a
non-compact disc source this signal outputs the pre-emphasis bit of the channel status bits in
the biphase input signal. If the category code of mode 0 is from a compact disc source then the
user data bits from the subcode channel including the CRC check on the 96 preceding Q bits
are output.
• User clock/copy bit output signal (OSCU). After receiving a category code of mode 0 from a
non-compact disc source then the copy bit of the channel status bits in the biphase input signal
is output. If the category code of mode 0 is from a compact disc source then 10 clock pulses for
the 'user data' are output.
• Pre-emphasis level output signal (OPRE), which indicates the value of the pre-emphasis bit of the
channel status bits after receiving the two-channel audio fromat in the biphase input signal
(lBIFA).
• Control data bits output signal (OCDB), which contains the 4 control bits of each word of the
biphase input signal.
• Input ITEST is used for device tests at the factory on Iy, for normal operation it has to be
connected to VSS.
Clock oscillator
The clock oscillator of the circuit can be formed by connecting either lC components or a crystal
or a ceramic resonator between the oscillator input and output pins.
The circuit can also be driven by an external signal source applied to the oscillator input. The
oscillator output is buffered and available at pin OSCL. The internal circuitry is driven via an
inverter, which is connected to the buffered output. This allows all the output signals (especially
ODCl, OWSY and OBSY) to change their state after a pulse from OSCl, independent of the
capacitive load of the OSCl pin. All output signals of the circuit are triggered on the positive
transition of the buffered OSCl signal.
I
(December 1988
721
____
SAA_72_74_Jl~________________
RATINGS
Limiting values in accordance with the Absolute Maximum System (lEe 134)
conditions
parameter
Supply voltage range
note 1
Input voltage
symbol
min.
max.
unit
VOO
-0.5
7.0
V
V
VI
-0.5
Maximum input current
11M
-
VOO+0.5
±10
mA
Maximum output current
10M
-
±10
mA
Maximum supply current in VSS
ISS
-
-40
mA
-
+40
mA
mW
Maximum supply current in VOO
100
P
-
50
-
280
mW
Storage temperature range
Ptot
T stg
-55
+150
oC
Operating ambient temperature range
Tamb
-40
+70
oC
Maximum power dissipation per output
Total power dissipation
Note
1. Input voltage should not exceed 7 V unless otherwise specified.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MaS devices (see
"Handling MaS Devices").
INTER'le
I~S
SOUNO
722
December
Purchase of Philips' 12 S components conveys a license under the
Philips' 12 S patent to use the components in the 12 S-system
provided the system conforms to the 12 S specification defined
by Philips.
19881 (
l___
Audio Digital Input Circuit (ADIC)
S_A_A_7_2_7_4______
DC CHARACTERISTICS
VOO = 4.5 to 5.5 V; T amb = -40 to + 70 oC, unless otherwise specified
conditions
symbol
min.
typo
max.
unit
note 1
note 2
100
100
-
-
*
100
-
J.J.A
rnA
Input voltage
(peak-to-peak value)
note 3
VI(p_p)
30
-
300
mV
Input voltage
(non-active)
INCAP = VOO
VI
-
-
5
mV
Input voltage HIGH
VIH
0.7 VOO
-
-
V
I nput voltage LOW
VIL
-
-
0.3 VOO
V
-II
II
-
-
1
1
J.J.A
J.J.A
CI
-
-
7.5
pF
parameter
Supply
Supply current
Inputs
IBIFA
All other inputs
«
Input current
I-
«
C
IZ
w
:?!
VI =OV
VI = 5.5 V
Input capacitance
Outputs
a..
OSCL
-'
w
Output voltage HIGH
-IOL=8mA
VOH
VOO-0.5
-
-
V
Output voltage LOW
IOL = 10 rnA
VOL
-
-
0.4
V
Output voltage HIGH
-IOL=2mA
VOH
VOO-0.5
-
-
V
Output voltage LOW
10L = 2 rnA
VOL
-
-
0.4
V
3-state
ILO
-
-
10
J.J.A
CL
20
-
50
pF
CL
-
-
80
pF
CL
-
-
50
pF
o
>
w
C
All other outputs
OSOA,OOCL,OWSY,OBSY
Output leakage current
OWSY, OOCL and OBSY
Load capacitance
OSCL
Load capacitance
All other outputs
Load capacitance
Notes to the DC characteristics
1. Vo = VOO, 10 = 0 rnA on all outputs and VI = VSS on all inputs, except INCAP which must be at
VSS·
2. fOSCL = 11.3 MHz.
3. INCAP = VOO, fmin = 1 MHz, tr and tf = 10%.
... Value to be fixed.
I (June
1989
723
_Jl_________
__
SA_A72_74
AC CHARACTER ISTICS
VDD
= 4.5 to 5.5 V; T amb = -40 to + 70 oC, unless otherwise specified
symbol
min. typo
max.
unit
IOSCl
flOSCl
-
-
12.5
MHz
Timing pulse lOW
tPl
37
-
-
ns
Rise and fall time
t r , tf
-
-
10
ns
Data set-up time
tsu
1
-
-
*
Data hold ti me
tHD
-
-
1
*
tp
-
10
ns
-
50
ns
parameter
conditions
Clock frequency
Set-up and hold times
IWSEl to IDACl
see Fig.5
Proagation delays
IDACl to OSDA
tp
-
OSCl to OWSY and ODCl
HIGH-to-lOW
lOW-to-H IGH
tPHl
tPlH
10
10
-
50
50
ns
ns
-
-
5
ns
-
15
ns
-
-
10
ns
40
ns
IOSCl to OSCl
Rise and fall times
OSCl
TTL levels = 0.4 to 2 V
Rise and fall time
t r, tf
CMOS levels = 10 to 90% VDD tr, tf
Rise and fall time
OWSY and ODCl
Rise and fall time
TTL levels = 0.4 to 2 V
Rise and fall time
CMOS levels = 10 to 90% VDD tr, tf
IOACL
1.
IWSEL
tr, tf
\
tHO
i
/
tsu
Fig.5 Set-up and hold time diagram.
* Clock periods of OSCL.
724
December
19881 (
.1
lZ81430.1
DEVELOPMENT DATA
c»
c.
clock
o·
biphase
input
I
~
c
cO'
L
~
::::I
't:I
phase output
C
rot
~
n
reference
c
;:+'
data clock
output
~~r---
};
C
§
word sync
output
block sync
output
L
data clock
output
~
control
bits
X
p
v
X
u
word sync
output
__________________~!I~------------------
block sync
output
o
CD
user clock
*
n
CD
3
0"
~
co
00
00
user data
(C)
o
Iw 1 v 1 u 1 T i s 1 R 1
N
U'I
en
1
lZ87437.7
* user clock pattern is not necessarily synchronous with the block sync signal.
»
»
.......
I\,)
Fig.6 Timing diagram.
.....
all
.......
~
DEVELOPMENT DATA
INTER'le
This data sheet contains advance information and
I~
specifications are subject to change without notice.
SOUND
SAA7310
CMOS DECODER FOR COMPACT DISC SYSTEMS
GENERAL DESCRIPTION
The SAA7310 (C03A) incorporates the functions of demodulator, subcoding processor, motor speed
control, error corrector and concealment in one CMOS chip. The device accepts data from the disc and
outputs serial data via the Inter IC signal bus (1 2S) directly to a digital-to-analogue converter (such as
the stereo CMOS dual OAC; SAA7320). The 12 S output can also be fed via the stereo interpolating
digital filter SAA7220 which provides additional concealment plus over-sampling digital filtering.
The SAA7310 is available in both 40-pin 01 Land 44-pin OFP packages.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Adaptive slicer with high-frequency level detector for input data
Built-in drop-out detector to prevent error propagation in adaptive slicer
Fully protected timing synchronization to incoming data
Eight-to-Fourteen Modulation (EFM) decoding
Adaptive CI RC error correction enabling 4 erroneous symbols per frame (32 symbols) to be corrected
Subcoding microprocessor handshaking protocol
Motor speed control logic which stabilizes the input data rate
Error flag processing to identify unreliable data
Concealment to replace uncorrectable data
12 S bus for data exchange
Bidirectional data bus to external RAM (16 K x 4 bits) with 64-frame FIFO capacity
Demodulator PLL requiring virtually no peripheral components
Replacement for the CD2A
Low power consumption (typ. 175 mW)
Track loss correction by additional muting
Non-digital audio interface application (such as CO-ROM or CD-I)
2-package option
-40 to +85 oC operating temperature range
QUICK REFERENCE DATA
parameter
symbol
min.
typo
max.
unit
Supply voltage
VOD
4,5
5,0
5,5
V
Supply current
IDD
-
35
50
mA
Data slicer input voltage
(peak-to-peak value)
VI(p_p)
0,5
-
2,5
V
Oscillator operating frequency
XTAL
fXTAL
10,16
11,2896
12,42
MHz
fVC01
2,54
4,3218
6,21
MHz
Output current (each output)
10
-10
-
+10
mA
Operating ambient temperature
Tamb
-40
-
+ 85
oC
VCO (PLL locked on to data)
PACKAGE OUTLINES
SAA7310P : 40-lead OIL; plastic (SOT129).
SAA7310GP : 44-lead OFP; plastic (SOT205A).
1(AUgust
1987
727
....
~
(J)
llI1r- '1ur- '"1~
~
HF input----l,
»
c:
co
c:
....~
~
....
HFI
FB
25 (32)
24 (31)
23 (30)
~
DATA
SLICER
Il
t
PHASE
DETECTOR
~
I
_r-
SERIAL TO
PARALLEL
CONVERTER
&
SYNC, Tmin,
Tmax
DETECTOR
+
2
I
+
FREQUENCY
DETECTOR
& LOCK IND.
COUNTER
PDIOC
22 (29)
LQ
I
[ I
ST1ST2ST3-
t
VCO
4,3 MHz
I
DELAY
I
5,6 MHz
I
I OOA~'
LOCKING
DEMOD.
TIMING
II
GI
I
I
I
(17)
r-
+
P-BIT
DEBOUNCE
I
I
I
I
i21 (28)
I
CRI
VDD
"-.1
l
"I
I
1~
I
I
I
i
K'
II
I
A-I
@
I"".,,,,g;:
FLAG
K2
LOGIC
1-8
(7-14)
AOto A7
M
12-14,16
(19-21,23)
4
10
'9
LATCH
LATCH
9
"J'",
INTER-
POL~TlNG
I
10
LATCH
2)1
V "
COS
CIRC DECODER
10
MUTE
37 (2)
CLAB
39 (4)
36 (1)
WSAB
EFAB
40 (5)
DINT2
RES
GEE;:~~~~R
J
7Z95866
Pins in parenthesis relate to 44-pin QFP package.
DAAB
38(3)
20 (27)
I
...
4) 01 toD4
,~~
f-+-
MICROCODED
CORRECTION PROCESSOR
Vss
R/W
11 (18)
I
MOO'"
I
RAS
10 (16)
A
LATCH
'AM
-"
9 (15)
RAM
INTERFACE
10
10
BUFFER
Fig. 1 Block diagram.
MSC
CAS
10
I":~~~OY
"'" "
~5
17 (24)
15 (22)
11,2MHZ
13
MOTOR
SPEED
CONTROL
LOGIC
8
9)1 PRE-FIFO 19
r;;:-A-;p;;C~~ - ,
I
II
I
P-BIT
10
28 (36)
DEBOUNCE
CIRCUIT
Q-BIT
SYNDROME FORMER
SAA7310
~~
~
D
I
CONTROL
ROM
I
c.v
-..
o
32 (41)
31
30 27 (35)
(40) (38)
QCHANNEL
PROCESSOR
5
I
L _ ~ _ _ _ _ -I
~
DEEM/DINT1
-....J
29
(37)
I M~," I
I
I
AM
t
~
~
(39)
ST4- I--
SYSTEM
CLOCK
GENERATOR
I
t
PARALLEL
TO
SERIAL
CONVERTER
I
11
I
I
~
34
35
33
(43) (44) (42)
9
I I
I~
t
19 (26)
I
9
DEMOD.
FLAG
PROCESSOR
I
HFD
18 (25)
SYNC
TO
CRYSTAL
CLOCK
n
I ref
26 (34)
~
EFM
DECODER
ORA
XTALl
XTAL2
l
»
}>
QCL
SWAB/ OOATA
SSM
SDAB
-c:::J-
CLOCK INTERFACE
-1
SCAB
l____
CMOS decoder for compact disc systems
S_A_A_7_31_0______
12S output
(176,4kHz)
from
r.f.
pre-amp.
mute from
servo
SAA7310
(44-pin QFP or 40-pin OIL)
CMOS DECODER
drop·out
signal L...--r------::-""2----,--....J
Q - channel
subcoding
data
XSYS
12S bus
3
(44,1 kHz)
SAA7320
L
(44-pin QFP)
R
audio
CMOS STEREO DAC
DEEM
t
disc motor
mute
from
control
controller
r
r
attenua~ion
mute
from
controller
from
controller
y
y
demodulation, error correction & basic concealment
digital filtering & analogue post - filtering
lZ95868
«
~
C
I-
Fig.2 (a) Block diagram of SAA7310 as used with SAA7320.
Z
w
:i!:
Q..
o..J
W
>
W
C
1(AUgust
1987
729
......
w
0
en
»»
~
tv
.......
l>
c:::
CO
c:::
(II
0
r-+
CO
ex>
......
DEEM
11,3MHz
o
from
r.f.
pr~-amp.
mute from
servo
XSYS
SAA7310
(40-pin DIL/44-pin QFP)
12S bus
CMOS DECODER
-,L--
SAA7220
(24-pin DIL)
12 S bus
DIGITAL FILTER
(176,4kHz)
TDA1542
ANALOG
OUTPUT
IC
(28-pin DIL)
(28-pin DIL)
3
3
(44,1 kHz)
drop-out
signal
TDA1541
DUAL DAC
IR
audio
~ headR .... phone
output
subcode
Q - channel
mute
disc motor
subcoding
from
control
data
controller
demodulation, error correction & basic concealment
r
digital
audio
attenuation
mute
from
from
controller controller
y
enhanced interpolation & digital filtering
y
D I A conversion & low - pass filtering
Fig.2 (b) Block diagram of SAA7310 as used with SAA7220.
7Z95867
SAA7310
CMOS decoder for compact disc systems
PINNING
DINT2
A3
2
WSAB
A2
3
ClAB
A1
4
DAAB
EFAB
35 SCAB
34 SDAB
33 SWAB/SSM
32 DEEM/DINT1
31
R/W
oel
SAA7310
ORA
MUTE
e:(
le:(
C
I0;:::
W
~
0..
0
..J
W
>
W
D2
ODATA
D1
CRI
D3
AM
CAS 15
HFD
D4 16
HFI
MSC 17
24 FB
C
XTAl2
Iref
XTAL1
PD/OC
VSS 20
21 V DD
7Z95875
Fig.3 Pinning diagram; for 40-lead DI L package.
'1
(AUgUst 1987
731
___SA_A73_10_Jl_________________
PINNING (continued)
~
C/l
~
e{
CD
e{
C/l
C/l
CD
u
0
CD
e{
~
C/l
I~i
w
w
0
e{
'
w
c
description
QFP
20
27
VSS
Ground: circuit earth potential.
21
28
VOO
Power Supply: positive supply voltage (+ 5 V).
22
29
PO/OC
Phase Detector output/ Oscillator Control input: outputs of the
frequency detector and phase detector are summed internally,
then filtered at this pin to provide the frequency control signal
for the VCO.
23
30
I ref
Current reference: external reference input to the phase detector
and data slicer. This input is required to minimize the spread in
the charge pump output of the phase detector and data slicer.
24
31
FB
Feedback: output from the input data slicer.
This output is a current source of 100 JlA (typ.) which changes
polarity when the level detector input H F I at pin 25 (32) rises
above the threshold voltage of 2 V (typ.). When a data run
length violation is detected (e.g. during drop-out), or when H FO
at pin 26 (34) is LOW, this output goes to a high impedance state.
'1 (AUgust
1987
733
l_ __
SAA7310
Pin functions (continued)
pin no.
734
mneumonic
description
DIL
OFP
25
32
HFI
High-Frequency Input: level detector input to the data slicer.
A differential signal of between 0,5 and 2,5 V (peak-to-peak value)
is required to drive the data slicer correctly. When a T max
violation is detected or when H F D is LOW, this input is biassed
directly to its threshold voltage
26
34
HFD
High-Frequency Detector: when HIGH this input signal enables
the frequency and phase detector inputs, also the feedback
output (FB) from the data slicer.
An internal voltage clamp of 3 V (typ.) requires the HFD input
to be fed via a high impedance. This input has an internal pull-up
of 50 kf2 (typ.).
27
35
AM
Additional Mute: This pin is normally held HIGH.
Should track loss occur the pin should be taken LOW and then the
data is forced LOW at the pre-F I Fa stage. The muted data will then
be corrected after de-interleaving.
Note With DINT2, DEEM/DINT1, FB set to logic 0 and SDAB,
SCAB set to logic 1, this pin becomes the demodulator clock
output (CEFM) of the SAA7210 (CD2A).
28
36
CRI
Counter Reset Inhibit: when LOW this input signal allows the
divide-by-588 master counter in the DEMOD timing to run-free.
This input has an internal pull-up of 50 kf2 (typ.).
29
37
ODATA
O-channel Data: this subcoding output is parity checked and
changes in response to the O-channel clock input (see subcoding
microprocessor handshaking protocol).
30
38
ORA
Q-channel Request input/Acknowledge output: the output has
an internal pull-up of nominally 10 kf2. (see subcoding
microprocessor handshaking protocol).
31
40
OCL
O-channel Clock: clock input generated by the microprocessor
when it detects a ORA LOW signal.
32
41
DEEM/DINT1 De-emphasis output and data interpolated input: signal derived
from one bit of the parity-checked O-channel and fed out via
the debounce circuit in DEEM mode. When using the CD3A in
a non-digital audio application this pin should be set HIGH
(with DINT2 set LOW) to prevent data being interpolated.
Note This pin should only be used in its input mode when
DINT2 is LOW.
33
42
SWAB/SSM
August
19871 (
Subcoding Word clock output and Start/Stop Motor input: open
drain output which is sensed during each HIGH period and if
externally forced LOW a motor-stop condition will be decoded
and fed to the motor control logic circuit. When allowed to
return HIGH, the motor will start. This open-drain output has
an internal pull-up of 10 kf2 (typ.).
l____
CMOS decoder for compact disc systems
S_A_A_73_1_0______
Pin functions
pin no.
mneumonic
description
43
SDAB
Subcoding Data: a 10-bit burst of data, including flags and sync
bits, is output serially once per frame clocked by burst clock
output SCAB (see Fig. 6).
44
SCAB
Subcoding Clock: a 1O-bit burst clock 2,8224 MHz (typ.) output
which is used to synchronize the subcoding data.
EFAB
Error Flag: output from interpolation and mute circuit indicating
unreliable data.
DIL
QFP
34
35
36
«
«
c
37
2
DAAB
Data: this output together with its clock (CLAB) and word
select (WSAB) outputs, conforms to the 12 S bus format
(see Fig. 7).
38
CLAB
Clock:
39
3
4
WSAB
Word Select: 12 S output.
40
5
DINT2
Data interpolated input: this pin should normally be set HIGH.
When using the CD3A in a non-digital audio application this pin
should be set LOW (with DEEM/DINTl set HIGH) to prevent
data being interpolated.
~
~
2
1 S
output.
The following pins apply to the 44-pin QFP package only:
z
6
TEST1
Test output 1
:E
a..
17
TEST2
Test output 2
o
...J
33
TEST3
Test output 3
W
39
TEST4
Test output 4
w
>
W
C
Note to the pin functions
The pin sequence of the address outputs (AO - A7) and the data outputs (01 - 04) has been selected
to be compatible with various dynamic 16 K x 4-bit RAMs including the 4416.
1(AUgust
1987
735
___S_AA_731_0_Jl_________________
FUNCTIONAL DESCRIPTION
All references to pin numbers show the 40-lead DI L pin first followed by the 40-lead QFP pin in
parenthesis.
Demodulation
Data read from the disc is amplified and filtered externally and then converted into a clean digital
signal by the data slicer. The data slicer is an adaptive level detector which relies on the nature of the
eight-to-fourteen modulation system (EFM) to determine the optimum slicing level. When a signal
drop-out is detected (via the H F 0 input, or internally when a data run length violation is detected)
the feedback (FB) to the data slicer is disabled to stop drift of the slicing level.
Two frequency detectors, a phase detector and a voltage-controlled oscillator (VeO) form an
internal phase-lock loop (PLL) system. The voltage-controlled oscillator (VeO) runs at the input
data rate (typically at 4,3218 MHz), its frequency being dependent on the voltage at pin 22 (29)
(P%e). One of the frequency detectors compares the veo frequency with that of the crystal
clock to provide coarse frequency-control signals which pull the veo to within the capture range
of fine frequency control. Signals for fine frequency control are provided by the second frequency
detector which uses data run length violations to pull the veo within the capture range of the PLL.
When the system is phase-locked the frequency detector output stage is disabled via a lock indication
signal. The veo output provides the main demodulator clock signal which is compared with the
incoming data in the phase detector. The output of the phase detector, which is combined internally
with the frequency detector outputs at pin 22 (29), is a positive and negative current pulse with
a net charge that is dependent on the phase error. The current amplitude is determined by the
current source Iref connected to pin 23 (30).
The demodulator uses a double timing system to protect the E FM decoder from erroneous sync
patterns in the data. The protected divide-by-588 master counter is reset only if a sync pattern occurs
exactly one frame after a previous sync pattern (sync coincidence) or if the new sync pattern occurs
within a safe window determined by the divide-by-588 master counter. If track jumping occurs
the divide-by-588 master counter is allowed to free-run to minimize interference to the motor speed
controller; this is achieved by taking the eR I input at pin 28 (36) LOW to inhibit the reset signal.
The sync coincidence pulse is also used to reset the lock indication counter and disable the output
from the fine frequency detector. If the system goes out of lock, the sync pulses cease and the lock
indication counter counts frame periods. After 63 frame periods with no sync coincidence pulse,
the lock indication counter enables the frequency detector output.
The EFM decoder converts each symbol (14 bits of disc data + 3 merging bits) into one of 256 8-bit
digital words which are then passed across the clock interface to the subcoding section. An additional
output from the decoder senses one of two extra symbol patterns which indicate a subcoding frame
sync. This signal together with a data strobe and two error flags are also passed across the clock
interface. The error flags are derived from the H F D input and from detected run length violations.
736
August 1987
J(
DEVELOPMENT DATA
(")
s:
0
en
c..
CD
n
0
c..
~
Q
n
0
3
'tl
II)
I-
1 Frame
= 588
n
channel bits
....
.,
c..
in'
n
en
c:
c:
en
.....
co
to
00
000,J
Fig. 5 Data input signal.
(J)
»
»
.....,j
w
.....
o
(j
"
___S_AA_731_0_jl_________________
FUNCTIONAL DESCRIPTION (continued)
Subcoding
The subcoding section has four main functions
•
•
•
•
Q-channel processor
De-emphasis output
Pause (P-bit) output
Serial subcoding output
The Q-channel processor accumulates a subcoding word of 96 bits from the Q-bit of successive subcoding
symbols, performs a cyclic redundancy check (CRC) using 16 bits and then outputs the remaining
80 bits to a microprocessor on an external clock. The de-emphasis signal (DEEM) is derived from one
bit of the CRC-checked Q-channel. The DEEM output pin 32 (41) is additionally protected by a
debounce circuit.
The P-bit from the subcoding symbol, also protected by a debounce circuit, is output via the serial
subcoding signal (SDAB) at pin 34 (43). The protected timing used for the EFM decoder makes this
output unreliable during track jumping.
The serial output consists of a burst of 10 bits of data clocked by a burst clock (SCAB). The 10 bits
are made up from subcoding signal bits Q to W, the Q-channel parity check flag, a demodulator error
flag and the subcoding sync signal. At the end of the clock burst this output delivers the debounced
P-bit signal which can be read externally in the rising edge of SWAB at pin 33 (42); see Fig. 6.
Q-CHANNEL PARITY CHECK FLAG
(0 = FAIL)
SDAB
SUBCODING ERROR FLAG
SYNC (active LOW)
\,In ~ r - \ ,.---,.,.---,. r-\,.---,.,.---,. ,.---,.rhl
P-BIT
P-BIT
I
I
I
I
I
I
I
I
I
I
I
I
\J
I
:
SWAB
!\""50% DUTY FACTOR 7,35 kHz
I
I
I
II....·- - - - - - - I
I
SCAB
2,8224 MHz BURST CLOCK
7Z80605
Fig.6 Typical subcoding waveform outputs.
Pre-FIFO
The 10 bits (8 bits of symbol data + 2 error flag bits) which are passed from the demodulator across
the clock interface to the subcoding section are also fed to the pre-F I FO with the addition of two
timing signals. These two timing signals indicate:
(1) That a new data symbol is valid
(2) Whether the new data symbol is the first symbol of a frame
The pre-F I FO stores up to 4-symbols (including flags) and acts as a time buffer between data input
and data output. Data passes into the pre-FIFO at the rate of 32 symbols per demodulator frame and
the symbols are called from the pre-F I FO into RAM storage at the rate of 32 symbols per errorcorrection frame. The timing, organized by the master controller, allows up to 40 attempts to write
32 symbols into the RAM per error-correction frame. The 8 extra attempts allow for transient changes
in clock frequency.
738
August
19871 (
CMOS decoder for compact disc systems
l____
SA_A_7_3_1_0______
Data control
This section controls the flow of data between the external RAM and the error corrector. Each symbol
of data passes through the error corrector two times (correction processes Cl and C2) before entering
the concealment section.
The RAM interface uses the full crystal frequency of 11,2 MHz to determine the RAM access waveforms (the main clock for the system is 5,6 MHz). One RAM access (READ or WRITE) uses 12 crystal
clock cycles which is approximately 1 JlS. The timing (see Fig. 8) is based upon the specification for
the dynamic 16 K x 4-bit RAM (4416). This RAM requires multiplexed address signals and therefore, in
each access cycle, a row address RAS pin 9 (15) is set up first and then three 4-bit nibbles are accessed
using sequential column addresses CAS pin 15 (22). As only 10 bits are used for each symbol (including
flags), the fourth nibble is not accessible.
There are 4 different modes of RAM access:
e::(
le::(
C
I2:
w
~
Q.
o-I
W
>
W
C
• WRITE 1
• READ 1
• WRITE 2
• READ 2
During WRITE 1, data is taken from pre-FIFO at regular intervals and written into one half of the
RAM. This half of the RAM acts as the main F I Fa and has a capacity of up to 64 frames. During
READ 1, the 32 symbols of the next frame due out are read from the FI Fa. The numerical difference
between the WRITE 1 and READ 1 addresses is used to control the speed of the disc drive motor.
When a frame of data has been read from the F I Fa it is stored in a buffer RAM until it can be accepted
by the CI RC error correction system. At this time the error correcting strategy of the CI RC decoder
for the frame is determined by the flag processor. The frame for correction is then loaded into the
decoder one symbol at a time and the 32 symbols from the previous correction are returned to the
buffer RAM.
After the first correction (Cl), only 28 of the symbols are required per frame. The symbols are stored
in the buffer RAM together with new flags generated after the correction cycle by the flag updating
logic. This partially-corrected frame is then passed to the external RAM by a WR ITE 2 instruction.
The de-interleaving process is carried out during this second passage through the external RAM. The
WRITE 2 and READ 2 addresses for each symbol provide the correct delay of 108 frames for the
first symbol and zero delay for the last symbol.
After execution of the READ 2 instruction, the frame' of 28 symbols is again stored in the buffer RAM
pending readiness of the CI RC decoder and calculation of decoding strategy. Following the second
correction (C2), 24 symbols including unreliable data flags (URD) are stored in the buffer RAM and
then output to the concealment section at regular intervals.
Flag processing
Flag processing is carried out in two parts as follows:
• Flag strategy logic
• Flag updating logic.
While a frame of data from the external memory is being written into the buffer RAM, the error flags
associated with that frame are counted. Two bits are used for the flags, thus 'good' data (flags = 00)
and three levels of error can be indicated.
The optimum strategy to be used by the CI RC error corrector is determined by the 2-bit flag information used by the flag strategy logic ROM in conjunction with its associated arithmetic unit (ALU). The
flags for the Cl correction are generated in the demodulator and are based on detected signal drop-outs
and data run length violations. Updating of the flags after Cl is dependent on the CI RC decoder correction of that frame. The updated flags are used to determine the C2 strategy. After C2 correction a single
flag (URD) is generated to accompany the data into the concealment section.
I (AUgust
1987
739
"'-I
~
o
LEFT SAMPLE
RIGHT SAMPLE
en
»
»
-...J
DAAB
I.........J I.........J I.........J '---.L..--- _
I
I
»
c:
I
I
I
I
CO
c:
~
EFAB
~
~~ i
LEFT ERROR FLAG
I
I
co
00
"'-I
I
I
I
I
I
I
I
----i
_--1:
I
WSAB
I
I
:
CLAB
RIGHT ERROR FLAG
I
I
I
I
I
I
I
I
I
I
I.
-- - - - -
~1,3:S
-
-
-
-
-
-
-
./
2,8224 MHz
7Z80613.1
Fig.7 Typical
2
1
S waveform outputs to SAA7220 or SAA7320.
CRYSTAL
CLOCK
:
ADDRESS
RAS
~
J
I
I
ROW
X
COLUMN 1
\
....-----------------------.. .,1
X
X
COLUMN 2
,r---------------~
COLUMN 3
C
ROW
I
I
l~----~\
I
CAS
*
I
I
~---------
I
;;'120 ns
~....---------------------_
-1,.----"
Riw
DATA
(write)
!
DATA
(read)
J
I.
~
';;SOns
t;
~
~
RAM access cycle (6 system clock cycles = 1,0631'5 nominal)
Fig.8 RAM timing waveforms: timings based on RAM TMS4416;
i
~~-------
.1
G input to RAM held
7Z80614
LOW.
c.v
........
o
l____
CMOS decoder for compact disc systems
SA_A_7_3_1_0______
CIRC Decoding
Data on the compact disc is encoded according to a cross-interleaved Reed-Solomon code (CI RC) and
this decoder exploits fully the error-correction capabilities of the code.
Decoding is performed in two cycles and in each cycle the CI RC decoder corrects data in accordance
with the following formula:
2t
+ e =4
Where:
e = the number of erasures (erroneous symbols whose position is known).
t = allowed number of additional failures which the decoder program has to find.
The flag processor points to the erasure symbols and tells the CI RC decoder how many additional
failures are allowed. If the error corrector is presented with more than the maximum it will stop and
flag all symbols as unreliable.
The CI RC decoder is comprised of two sections:
Syndrome formation
«
«
C
Four correction syndromes are calculated while the frame of data is being written into a symbol
memory. From these syndromes errors can be detected and corrected.
II-
Z
w
:!:
c..
o
...J
W
>
W
C
Microcoded correction processing
The processor uses an Arithmetic Logic Unit (ALU) which includes a multiplier based on logarithms.
The correction algorithm follows the microcode program stored in a ROM.
Concealment
This section combines 8-bit data symbols into left and right stereo channels. Each channel has a 16-bit
capacity and holds two symbols (a stereo sample). The channels operate independently. A concealment
operation is performed when a U RD flag accompanies either symbol in a stereo sample. If a single
erroneous sample is flagged between two 'good' samples then linear interpolation is used to replace
the erroneous value. If two or more successive samples are flagged, a sample and hold is applied and
the last of the erroneous samples is interpolated to a value between that of the hold and that of the
following 'good' sample.
When using the CD3A in a non-digital audio application, pins DINT2 and DEEM/DINT1 should be set
to logic 0 and logic 1 respectively. The URD flag will then be disabled to prevent data being interpolated.
If MUTE is requested, the data in each channel is attenuated to zero in 15 successive divide-by-two
steps. At the end of a mute period the output is incremented to the first 'good' value in two steps
using the interpolator.
All erroneous data supplied to the concealment section continues to be flagged when it is output to
the SAA7220 where it receives additional and more efficient concealment (see Fig. 9).
I (AUgust
1987
741
___S_AA_731_0_Jl_________________
FUNCTIONAL DESCRIPTION (continued)
7Z91661.1 F
a·sample
interpolation
SAA7220
basic
\7I'
1 i'
1
1
I
:
EFAB (error flag)
I'
1
I
~
I'
::
~\
II " 1111
Fig. 9 The SAA7220 can make an 8-sample linear interpolation, the SAA7310 a hold and single-sample
interpolation. When interpolating more than 8 samples, a hold function operates in the SAA7220 before
the interpolation.
Non-digital audio applications
The CD3A contains a special mode for non-digital applications such as CD-ROM and CD-/. In this mode
the concealment section is not allowed to operate. The flagged output words of the error correction
circuit are passed to the output DAAB without being affected by the interpolation circuit. The EFAB
output signal indicates unreliable output words on a sample basis when one or both bytes in a sample
are unreliable. This is necessary as the CD-RaM/CD-I player performs its own error correction strategy
on the data. The level of data integrity has to be much higher to ensure no errors occur in text or
numerical information.
Specifications of CD-ROM and CD-I modes are available on request.
Motor speed control (see Fig. 10)
The motor speed control (MSC) output from pin 17 (24) is a pulse-width modulated signal. The duty
factor of the pulse-width modulation is calculated from the difference in numerical value between the
WRITE 1 and READ 1 addresses, the difference being nominally half of the FIFO space. The calculation
is performed at a rate of 88,2 kHz.
The duty factor of MSC varies in 62 steps from 1,6% (FIFO full) to 98,4% (FIFO empty). When a
motor-start signal is detected (via SWAB/SSM) the duty factor is forced to 98,4% for 0,2 seconds
followed by a normal, calculated signal. After a motor-stop signal is detected the duty factor is forced
to 1,6% for 0,2 seconds followed by a continuous 50% duty factor. A change in motor start/stop status
occurring within the 0,2 second periods overrides the previous condition and resets the data control
timer.
Track loss correction
The CD3A also incorporates a function to provide extra correction during track loss. Should track loss
occur, the additional mute pin (AM) should be taken LOW, which forces the data LOW atthe pre-FI Fa stage.
This muted data is then corrected after de-interleaving. This function is particularly useful for
applications where mechanical shock is likely to occur.
742
August 19871 (
l____
CMOS decoder for compact disc systems
S_A_A_73_1_0______
mean
PWM
output
signal
o
I
I
2
I
I
FIFO full
W inhibit
16
I
I
20
24
32
I
I
40
36
I
I
48
I
I
I
52
nominal
working
point
56
: 63
61
-
frames of
I
RAM space
FIFO ~mpty unoccupied
R inhibit
7Z80606
Fig. 10 Motor speed control.
«
!;;(
CD2A replacement
C
The C03A can become a direct replacement for the C02A by externally connecting pin 21 to VOO
and modifying the PLL peripheral components (see Fig. 12).
~
w
:E
D-
O
.J
W
>
W
C
I (AUgust
1987
743
___SA_A73_10_jl_________________
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
parameter
symbol
min.
max.
unit
Supply voltage, pin 21 (28)
VDD
-0,5
+ 6,5
V
Maximum input voltage
VI
-0,5
VDD + 0,5
V
Input current, pin 23 (30)
II
-
5
rnA
Maximum output voltage
MSC, QRA, SWAB/SSM
Vo
-0,5
+6,5
V
Output current (each output)
10
-
±10
rnA
DC VSS or VDD current
IDD or ISS
-
± 100
rnA
DC input diode current
11K
-
± 20
rnA
DC output diode current
10K
-
± 20
rnA
Storage temperature range
Tstg
-55
+ 150
oC
Operating ambient temperature range
Tamb
-40
+ 85
OC
Electrostatic handling*
Ves
-1000
+ 1000
V
INTER·le
I~S
SOUND
Purchase of Philips' 12 S components conveys a license under the
Philips' 12 S patent to use the components in the 12 S-system
provided the system conforms to the 12 S specification defined
by Philips.
Detailed information on the 12 S bus specification is available on request.
Supply of this Compact Disc IC does not convey an implied licence under any patent right to use this
IC in any Compact Disc application.
*
744
Equivalent to discharging a 100 pF capacitor through a 1,5 kn series resistor with a rise time of
15 ns.
August
19871 (
l___
CMOS decoder for compact disc systems
S_A_A_7_3_10_ __
CHARACTERISTICS
VOO = 4,5 to 5,5 V; VSS = 0 V; Tamb = -40 to + 85 0C unless otherwise specified
symbol
min.
typo
max.
unit
Supply voltage, pin 21 (28)
VOO
4,5
5,0
5,5
V
Supply current, pin 21 (28)
100
-
35
50
rnA
parameter
conditions
Supply
Inputs
01 - 04, OCl, AM,
OEEM/0INT1,OINT2
Input voltage lOW
note 1
Vil
-0,3
-
+0,8
V
Input voltage HIGH
note 1
VIH
2,0
-
VOO + 0,5
V
Input leakage current
note 2
III
-10
-
+10
JlA
CI
-
-
10
pF
-
+0,8
V
VOO + 0,5
V
Input capacitance
MUTE, CRI
«
«
C
Input voltage lOW
note 1
Vil
-0,3
Input voltage HIGH
note 1
VIH
2,0
I-
Internal pull-up impedance
VI =OV
w
:E
Input capacitance
o
ORA, SWAB/SSM
W
Input voltage lOW
W
Input voitage HIGH
I-
Z
Q.
...J
>
C
Ilil
18
50
110
kn
CI
-
-
10
pF
note 1
Vil
-0,3
-
+0,8
V
note 1
VIH
2,0
-
VOO + 0,5
V
CI
-
-
10
pF
Ilil
3,9
10
18
kn
Vil
-0,3
-
+0,8
V
VIH
2,0
-
clamped
V
Input capacitance
Internal pull-up impedance
VI =OV
HFO
Input voltage lOW
Input voltage HIGH
VCl
2,0
3,0
4,5
V
Input source current
IS
-100
100
JlA
Input capacitance
CI
-
-
10
pF
Ilil
18
50
110
kn
Input clamping voltage
Internall pull-up impedance
II = 100 JlA
VI =OV
I (AUgust
1987
745
___
SAA_73_10_jl_________________
parameter
conditions
symbol
min.
typo
max.
unit
Output voltage LOW
-IOL = 1,6 rnA
VOL
0
-
0,4
V
Output voltage HIGH
10H = 0,2 rnA
V
Outputs
AO-A7, R/W, 01-04, CAS, RAS,
QDATA, DEEM/DINT1, SDAB, SCAB,
EFAB, DAAB, CLAB, WSAB,
TEST1,TEST2,TEST3,TEST4
Load capacitance
Leakage current
note 2
VOH
3,0
-
VDD
CL
-
-
50
pF
ILO
-10
-
+10
J.lA
MSC (open drain)
Output voltage LOW
-IOL = 1 rnA
Load capacitance
Leakage cu rrent
note 2
VOL
0
-
0,35
V
CL
-
-
50
pF
ILO
-10
-
+10
J.lA
SWAB/SSM, QRA (open drain)
Output voltage LOW
-IOL = 1,6 rnA
VOL
0
-
0,4
V
Load capacitance
CL
-
-
50
pF
Internal load resistance
RL
3,9
10
18
kn
AC input voltage range
(peak-to-peak value)
VI(p_p)
0,5
-
2,5
V
Input impedance
normal (HFD HIGH)
1211
500
-
-
kn
disabled (HFD LOW)
1211
50
100
200
kn
CI
-
-
10
pF
10
I re f/ 5
5
-20% I re f/
I re f/5
+20%
J.lA
ANALOGUE CIRCUITS
Data slicer (see Fig. 11)
Input HFI
Input capacitance
Output FB
Output current
746
August
19871 (
VFB = 2 V
l____
CMOS decoder for compact disc systems
S_A_A_73_1_0____
parameter
conditions
symbol min.
typo
max.
unit
Phase detector
Output PO/OC
see Fig. 12
Output cu rrent
PO/OC
Control range
note 3
Input Iref
see Fig. 13
= 1 to 3 V
Input reference current
10
±l re f-2O% ±Iref
±l re f+2O%
IlA
ex
±2,1
-
-
rad
Iref
-
500
*
IlA
IZOI
2
4,1
5,6
kn
r.
v
-
0,4
V
VOL
4
-
VOO
V
IZOI
1
2,3
3,2
kn
VOL
0
-
0,4
V
VOL
4
-
VOO
V
Kosc
-
3,5
-
MHz/V
Gm
Gv
1,5
-
-
ms
3,5
-
-
V/V
CI
-
-
10
pF
-
5
pF
Fine frequency detector
Output PO/OC
Output impedance
Output voltage LOW
10L = 1 IlA
Output voltage HIGH
-IOH
VOL
= 1 IlA
Coarse frequency detector
Output PO/OC
«
~
C
IZ
Output voltage LOW
10L = 1 IlA
Output voltage HIGH
-IOH
W
~
Voltage controlled oscillator
o..J
Input PO/OC
c..
W
>
W
note 4
Output impedance
= 1 IlA
Osci Ilator constant
C
Crystal oscillator
see Fig. 14
Input XTAL 1
Output XT A L2
Mutual conductance
100 kHz
Small signal voltage gain
Gv
= Gm x
Input capacitance
Ro
Feedback capacitance
CFB
-
Output capacitance
Co
-
III
-10
Input leakage current
* Value to be fixed.
note 2
10
pF
+10
IlA
"I (AUgust
1987
747
~
___S_AA_731_0_jl_________________
parameter
conditions
Slave clock mode
see Fig. 15
Input voltage
(peak-to-peak value)
symbol
min.
typo
max.
unit
VI(p_p)
3,0
-
VDD+0,5 V
Input voltage LOW
note 1
VIL
-0,3
-
0,8
Input voltage HIGH
note 1
VIH
2,4
-
VDD+0,5 V
V
Input rise time
note 5
tr
-
-
20
ns
Input fall time
note 5
tf
-
-
20
ns
Input HIGH time
(relative to clock period)
at 1,5 V
tHIGH
45
-
55
%
TIMING
Operating frequency (XTAL)
fXTAL
10,16
11,2896 12,42
MHz
Operating frequency (VCO)
PLL locked
on to data
fVC01
2,54
4,3218
6,21
MHz
Operating frequency (VCO)
VCO absolute limits;
PLL not locked
on to data
fVC02
2
-
7,5
MHz
Output rise time
tr
20
ns
tf
-
-
Output fall time
20
ns
Output HIGH time
tHIGH
50
-
-
ns
Output rise ti me
tr
-
-
20
ns
Output fall time
tf
-
-
20
ns
tsu; DAT
100
-
-
ns
tHD; OAT
100
-
-
ns
tr
-
-
20
ns
tf
-
-
20
ns
-
-
ns
Outputs
Figs. 16 and 17
CEFM
note 6
DAAB,CLAB,WSAB,EFAB
( 12 S format)
note 6
DAAB, WSAB,
EFAB to CLAB
Data set-up time
CLAB to DAAB, WSAB,
EFAB
Data hold time
SDAB, SCAB, DEEM
(subcoding outputs)
Output rise time
Output fall time
note 6
SDAB to SCAB
Subcoding data set-up time
748
August 19871 (
tsu; SDAT 100
l____
CMOS decoder for compact disc systems
parameter
S_A_A7_3_1_0______
conditions
symbol
min.
typo
max.
unit
tHO; SOAT
100
-
-
ns
SCAB to SOAB
Subcoding data hold time
note 6
SWAB/SSM
Output rise ti me
tr
-
-
1
ns
Output fall time
tf
-
-
100
ns
-
50
-
%
tACC;N
0
-
13,3 + n x 13,3
ms
tACC; F
13,3
-
n x 13,3
ms
ns
Output duty factor
a-channel I/O
Figs 18 and 19
ORA, OCL, OOATA
Access time
normal mode
note 7
refresh mode
<2:
~
c
~
zw
~
Q..
o
..J
W
OCL to ORA
acknowledge delay
tOACK
-
-
500
request hold time
tHO; R
750
-
-
ns
OCL clock input LOW time
tCK; LOW
750
-
-
ns
OCL clock input HIGH time
tCK; HIGH
750
-
-
ns
OCL to OOATA delay time
too
-
-
750
ns
Oata hold time before
new frame is accessed
tHO;ACC
2,3
-
-
ms
Acknowledge time
tACK
-
-
10,8
ms
>
~
Notes to the characteristics
1. Minimum VIL, maximum VIH are peak values to allow for transients.
2.
3.
ILI(min) and ILO(min) measured at VI
1 rad
= 0 V; ILI(max) and
ILO(max) measured at VI = VOO.
1800
=- - .
(3,14)
4. Coarse frequency detector output PO/OC active for VCO frequencies
> fXTAL
2
5.
and
< fXTAL
4
Reference levels = 0,5 V and 2,5 V.
6. Output rise and fall times measured with load capacitance (CL)
=50 pF.
7. O-channel access times dependent on cyclic redundancy check (CRC);
n = number of cycles until CRC is 'good'.
'I (AUgust
1987
749
___S_AA_731_0_jl_________________
2,2 nF
18kn
HFinput ~
l/lF
+
~
PD/OC
HFI
FB
25 (32)
24 (31)
22 (29)
SAA7310
SAA7310
lZ95871
lZ95869
Fig. 11 Data slicer H F I input.
Fig. 12 PLL circuit.
11.2896MHz
+5V
18 (25)
.-----.--f---1..--+--+--
1--+-2_3_(_30_)-+ I ref
XT A L 2
SAA7310
1MO
SAA7310
19 (26)
+-_
... XTAL1
L....-_......._~_ _
lZ95810
Fig. 13 Iref circuit.
750
August 19871 (
lZ95814
Fig. 14 Crystal oscillator circuit;
using crystal type: 4322 14305031.
CMOS decoder for compact disc systems
l___
S_A_A_7_3_10______
clock input
(V,)
lZ95872
Fig. 15 Input clock timing diagram; reference levels 0,5 V, 1,5 V and 2,5 V.
CLAB
e:(
le:(
C
IZ
DAAB
WSAB
EFAB
w
:t
a..
o
...J
W
>
Fig. 16 Typical 12 S data output waveforms; reference levels = 0,8 V and 2,0 V.
W
C
SCAB
SDAB
SWAB
Fig. 17 Typical subcoding data output waveforms; reference levels for SCAB and SDAB = 0,8 V
and 2,0 V; reference levels for SWAB = 0,8 V and 4,0 V.
'I (AUgUst
1987
751
~
___S_AA_731_0_jl_________________
DATA REQUEST
( microprocessor
internal signal)
ACKNOWLEDGE
(SAA7310
internal signal)
-
'-tDACK
QRA
QCL
1.1
I
QDA T A _ _h_i,;;.,9h_i_m""-p_ed_a_n_ce_ _---i
high impedance
Ql
-,',tCK' LOW
QCL
--------~------~--~
10,8ms-i
when QCL
delayed
high impedance
QDATA - - - - - - - - - - - ' \
1-
<2,3ms
Ql
7Z95877
Fig. 18 O-channel timing waveforms (normal model.
DATA REOUEST
(microprocessor
internal signal)
ACKNOWLEDGE
(SAA7310
internal signal)
~--------------~I
~--~~~--------
ACCESS FRAME
~
~tACC;N
ORA
I. . . ~----
tACK - - - - -
OCL
......JH
ODA - - - - - - - { (...._ _ _ _ _ _ _
0_1_ _ _ _ _ _
/.
this will repeat
until OCL goes LOW
01
.1
Fig. 19 Q-channel timing waveforms (refresh model.
752
August
19871 (
7Z80612F
l____
CMOS decoder for compact disc systems
S_A_A_73_1_0______
APPLICATION INFORMATION
EFM Encoding system
The Eight-to-Fourteen Modulation (EFM) code used in the Compact Disc Oigital Audio system is
designed to restrict the bandwidth of the data on the disc and to present a OC free signal to the demodulator. In this modulation system the data run length between transitions is ~ 3 clock periods and
~ 11 clock periods. The number of bits per symbol is 17, including three merging and low frequency
suppression bits which also assist in the removal of the OC content.
The conversion from 8-bit, non-return-to-zero (N RZ) symbols to equivalent 14-bit code words is
shown in Table 2. C1 is the first bit of a 14-bit code word read from the disc and 01 is the Most
Significant Bit (MSB) of the data sent to the error corrector. The 14-bit code words are given in NRZ-\
representation in which a logic 1 means a transition at the beginning of that bit from H IGH-to-LOW
or LOW-to-HIGH (see Fig. 20).
o
CODED NRZ-I
DECODED EQUIVALENT
1 001 000 1 0 0 0 001 0 000
~L....-_ _-.J
....
W
o
The codes shown in Table 2 cover the normal 256 possibilities for an 8-bit data symbol. There are other
combinations of 14-bit codes which, although they obey the EFM rules for maximum and minimum
run length (T max, T min), produce unspecified data output symbols. Two of these extra codes are used
in the subcoding data to define a subcoding frame sync and are as shown in Table 1.
Table 1 Codes used to define subcoding frame sync
r~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~!~~~~~~~~~~~~~~~~~~~:~~~~~~~:~~~~~~~~~~]
I
'
,
,
,
,
,
,
I '
,
,
,
,
,
,
,
,
,
,
"
I
I 01102103104105106107108IC1Ic21c3Ic4Ic5Ic6Ic7!C8Ic9!C10IC111c121c13!C14
I
~--------t------~-----~------~------~------~-----t-----+----~-----+-----~-----~-----+-----t-----~-----+-----~-------+------~--------~-------~------------i
I
:
:
:
:
:
:
:
I :
:
:
:
:
:
:
:
:
:
:
::
I
0
II x 1
!, 1 1
1
1
1
10
i, 0 10
i, 0 1" 0 1 1 II
' 010
,
, 1 11
,
, 1!, 1 1
I 10
'
, 11, 010
,
, 0 i, 0 10
,
,
,
I
I x! 1 11 1 11 1 11 1 01 1 10 10 1 01 010 1 0 10 10 10 1 1 10 10 1 1 ! 0
~--------t-----+-----i------i-----+----+-----t-----+--_J J______ L ___ L ____L ___ L____ L ____L_____ L ____ J ______ L ______ L______ L__________ J
I p: Q: R : S: T : U : V: W I
_____
I
:
!
!
!
!
!
!
_________ l ______ l._____ J ______ J ______ .1 _____ -'- _____ L _____ _
Where: X
I
= don't care state.
When a subcoding frame sync is detected the P-bit (Pause-bit) of the data is ignored by the debounce
circuitry. The remaining bits (Q to W) are not specified in the system but always appear at the serial
output as shown in Table 1.
I (AUgust
1987
753
.....
U'1
~
en
»
-..J
APPLICATION INFORMATION (continued)
»c
Table 2 EFM code conversion
co
c
~
No.
......
o
2
3
I
DNZ data symbol
D1
<0
CXl
.....
»
D8
0000000
000 000 0
0 0 0 0 0 0 1
0 0 0 0 0 0 1
No.
equivalent code word
C14 I
C1
0 101 001
1
100 0 0
0
1 0 0 1 0
1
1 0 0 0 1
000 1
1 000
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
I DNZ data symbol
D1
I
D8
c.v
.....a.
o
equivalent code word
C14
C1
I0
0
0
0
0
128
129
0 0 0 0 0 0 0
0 0 0 0 0 0 1
130
131
0 0 0 0 0 1 0 I1 0 0 1 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 1 1 I 1 0 0 0 1 0 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 1 0 0 0 0 1
1 0 0 0 0 1 0 0 1 0 0 0 0 1
4
0 0 0 0 0 1 0 0
0 1 0 0 0 1 0 0 0 0 0 0 0 0
132
0 0 0 0 1 0 0
5
0 0 0 0 0 1 0 1
0 0 0 0 0 1 0 0 0 1 0 0 0 0
133
0 0 0 0 1 0 1
6
7
0
0
0
0
0 0 0 0 1 1 0
0 0 0 0 1 1 1
0 0 0 1 0 0 0 0 1 0 0 0 0 0
0 0 1 0 0 1 0 0 0 0 0 0 0 0
134
135
0 0 0 0 1 1 0
0 0 0 0 1 1 1
0 0 0 1 0 0 0
0 1 0 0 1 0 0 1 0 0 0 0 0 0
136
0 0 0 1 0 0 0
0 0 0 1 0 0 1
0 0 0 0 0 0 1 0 0 0 0 0 0
137
0 0 0 1 0 0 1
0 0 0 0 0 0 1 0 0 0 0 0 1
0 0 0 0 1 0 1 0
1 0 0 1 0 0 0 1 0 0 0 0 0 0
138
0 0 0 0 0 1 0
1 0 0 1 0 0 0 1 0 0 0 0 0 1
8
9
10
to
119
247
0 0 1 0 0 0 0 1 0 0 0 0 1
0 1 0 0 1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 1 0 0 0 0 0 1
000
o1
0 0 1 001 001 000
249
100 1 0 0 0 0 0 0 0 0 1 0
1 000 1 000 0 0 0 0 1 0
250
001
010
100 1 0 0 0 001 001 0
1
1
0 1 .0
121
o
o
01111011
1
0 0
o1
0 1
o
248
o1
o0
o1
o
001 0 0 0 0 000 1 0
000
0 0·1
120
125
126
127
1 0 0 0 1 0 0 1 0 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0 0 T
139
11
to
122
123
124
0
0
0
0
0
1
0
o1
1 1
o1
o0
0 0 0 0 0 000 0 0 1 0
0 0 1 0 0 0 0 0 0 0 1 0
000 1 0 0 0 0 0 0 001 0
00100 0 0 0 0 000 1 0
o
001 0 0 0 0 1 001 0
1 0 0 0 0 0 000 1 001 0
1 1
1 000 1 0 0 001 001 0
o0
o 1 0 0 0 0 0 0 0 1 001 0
253
o1
00001 0 000 1 001 0
254
255
o
000 1 000 001 001 0
001 000 000 1 001 0
251
252
1 1
l____
CMOS decoder for compact disc systems
S_A_A_7_31_0______
Subcoding microprocessor handshaking protocol (see Figs. 18, 19 and 21 )
The ORA line is normally held lOW by the microprocessor.
When the microprocessor needs data (Request) it releases the ORA line and allows it to be pulled HIGH
by the pull-up resistor in the SAA731 O.
The SAA7310 is continuously collecting O-channel data and when it detects that ORA is HIGH it holds
the first frame of Q-channel data for which the Cyclic Redundancy Check (CRC) is 'good'. Then the
SAA7310 pulls ORA lOW to tell the microprocessor that the data is ready (Acknowledge) and enables
the ODATA output.
.
When the microprocessor detects a ORA lOW signal it generates a clock signal (OCl) to shift the data
out from the SAA7310 to the microprocessor via the ODATA output. The first negative edge of OCl
also resets the acknowlegde signal and thus releases the ORA line.
As soon as the microprocessor has received sufficient data (not necessarily 80 bits) it pulls the ORA
line lOW again. The SAA7310 now disabled the ODATA output and resumes collecting new O-channel
data.
«
~
C
IZ
If the microprocessor does not generate a OCl signal within 10,8 ms from the start of the acknowledge
(ORA lOW), the SAA7310 resets the acknowledge signal and allows the ORA line to go HIGH again.
The microprocessor still has 2,3 ms to accept the data, which allows for a long propagation delay in
the microprocessor. After a further 13,33 ms the SAA7310 will have received a new frame of O-channel
data and, provided the CRC is 'good', will give a fresh acknowledge signal. This refreshing process
is repeated until the microprocessor accepts the data or stops the request.
When the microprocessor has a requirement to hold the data for a long period before acceptance, it
prevents the refreshing process by setting OCl lOW after any acknowledge signal.
w
~
0..
o
...J
W
>
W
+
MICROPROCESSOR
SAA 7310
C
QRA
30 (38)
QDATA
29 (37)
QCL
31 (40)
DATA
ENABLE
>--...... CLOCK
7Z95873
Fig. 21 Microprocessor handshaking protocol.
1
(August 1987
755
l____
DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
S_AA_7_3_2_0______
STEREO CMOS DAC FOR COMPACT DISC
DIGITAL AUDIO SYSTEMS
GENERAL DESCRIPTION
The SAA7320 (DAC3) is a complete monolithic stereo CMOS 16-bit input digital-to-analogue converter
designed for application in low/mid-cost portable compact disc systems.
Features
•
•
•
•
•
•
•
•
•
2
1 S data
input
3-stage digital filter incorporating F.I.R. filter, linear interpolator and sample and hold
2nd order noise shaper to provide a signal-to-noise ratio of> 90 dB
16-bit resolution from a 1-bit converter, using switched capacitor integrator
3rd order low-pass filter to reduce out-of-band noise
-12 dB attenuation, de-emphasis and mute control
Low power consumption (typ. 300 mW)
Single supply operation (+ 5 V)
-40 to + 85 0C operating temperature range
QUICK REFERENCE DATA
parameter
conditions
Supply voltage (analogue)
symbol
min.
typo
max.
unit
VDDA
4,5
5,0
5,5
V
Supply current (analogue)
IDDA
-
20
*
mA
Supply voltage (digital)
VDD
4,5
5,0
5,5
V
Supply current (digital)
IDD
-
40
*
rnA
o dB input
SIN
-
90
-
dB
I nput voltage LOW
note 6
VIL
0
-
+0,8
V
Input voltage HIGH
note 6
VIH
2,0
-
VDD+0,5
V
Output voltage LOW
note 6
VOL
0
-
+0,4
V
Output voltage HIGH
note 6
Signal-to-noise ratio at
the analogue outputs
I nput voltage ranges
WSI, CLI, DAI, DEC,
ATT
Output voltage ranges
WSO, CLO, DAO, XSYS,
VOH
2,4
-
VDD+0,5
V
Operating frequency XTAL
fXTAL
8,0
11,2896
12,3
MHz
Operating ambient
temperature range
Tamb
-40
-
+85
°C
* Value to be fixed.
For explanation of notes see "Notes to the characteristics",
PACKAGE OUTLINE
SAA7320GP: 44-lead QFP; plastic (SOT205A).
"I ~JanuarY
1988
757
jl_________________
___
SA_A7_320_ _
i~-r--r-<'''''''---1
~ .~
.~
u..
.~
l,s-+'"-----,
i
B-
t>
•
~!.!~
~+---------~~ii~
758
January
19881 (
~
b
-
SAA7320
Stereo CMOS DAC for compact disc digital audio systems
PINNING
0::
IZ
~
o
o
>
..!.
0::
w
o
I-
n.c.
DER
DAI
vrefR
CLI
WSI
V SSA
TEST 1
V SSAL
VSS
SAA7320
Vss
DEL
XSYS
I-
CDL
XTALl
IZ
INTL
«
«
0
W
:?!
n-
XTAL2
V DDAL
V DD2
O
...I
W
>
w
0
..!.
0::
::::i
0::
u
0::
>
""
I-
en
w
0
7Z95892
Fig.2 Pinning diagram.
") ('"January
1988
759
Jl
SAA7320
Pin functions
mnemonic
description
CDR
Capacitor Damping Right: damping capacitor for the right channel switchedcapacitor integrator.
2
DER
De-emphasis Right: connection to the de-emphasis switch in the feedback
of the right channel integrator.
3
VrefR
Reference voltage Right: reference voltage input for the analogue right
channel ground (+ 2,5 V typ.) ..
4
VSSAR
Ground: ground connection for the analogue right channel.
5
pin no.
VSSA
Ground: ground connection for logic in the analogue section.
6
VSSAL
Ground: ground connection for the analogue left channel.
7
VrefL
Reference voltage Left: reference voltage input for the analogue left channel
ground (+ 2,5 V typ.).
8
DEL
De-emphasis Left: connection to the de-emphasis switch in the feedback of
the left channel integrator.
9
CDL
Capacitor Damping Left: damping capacitor for the left channel switchedcapacitor integrator.
10
INTL
Integrator Left: output from the left channel switched-capacitor integrator.
12
VDDAL
OALI-
Power Supply: + 5 V supply voltage for the analogue left channel.
13
OALI+
Operational Amplifier Left Input +: non-inverting input to the left channel
low-pass filter operational amplifier.
14
OALO
Operational Amplifier Left Output: output from the left channel
operational amplifier.
15
VDDref
VRO
Power Supply: +5 V supply voltage for the reference voltage generator.
16
17
VRC
Reference Voltage Capacitor: internal reference voltage high impedance
node requiring an external smoothing capacitor.
18
TEST4
Test output 4: pin should be left open-circuit.
19
DAO
12 S Serial Data Output: is a 16-bit linear two's-complement PCM signal at
a data rate of 176,4 kHz (typ.) formatted in accordance with 12 S. After
4 x upsampling by the digital filter this signal is output so that an external
DAC could be used; combined with CLO and WSO it can be considered as
a master transm itter.
20
CLO
12 S Serial bit Clock Output: fCLO
21
WSO
12S Word Select Output: 176,4 kHz typo
22
VDDl
Power supply: + 5 V supply voltage for the digital section.
23
24
VDD2
XTAL2
Crystal oscillator output: drive output to clock crystal.
25
XTAL1
Crystal oscillator input: input from crystal oscillator or external clock
input (11,2896 MHz typ.).
26
XSYS
System clock output: buffered output from crystal oscillator
27, 28
VSS
Ground: ground connection for the digital section.
11
760
January
19881 (
Operational Amplifier Left Input -: inverting input to the left channel
low-pass filter operational amplifier.
Reference Voltage Output: internal reference voltage output (+ 2,5 V typ.).
= 5,6448 MHz typo
Power Supply: + 5 V supply voltage for the crystal oscillator.
l___
Stereo CMOS DAC for compact disc digital audio systems
S_A_A_7_3_2_0______
pin no.
mnemonic
description
29
TEST1
Test input 1: pin should be connected to ground.
30
WSI
12 S Word Select Input: 44,1 kHz typo WSI together with CLI, is used to
clock the 12 S serial data input (OAI) and synchronize the main timing
chain.
31
CLI
12 S Serial bit Clock Input: fCLI
32
DAI
12 S Serial Data Input: is a 16-bit linear two's-complement PCM signal
formatted in accordance with 12 S. If more than 16 bits are supplied then
the least significant bits (LSBs) will be truncated.
33
n.c.
not connected.
34
DEC
De-emphasis Control: this input switches an extra external capacitor
network into both the analogue left and right channel integrator feedback.
35
MUTE
Mute: when active LOW this Schmitt trigger control input will force the
interpolator data input to zero. It will also force the 12 S data output
(DAO) to zero.
36
ATT
Attenuation: when active LOW this control input provides -12 dB
attenuation to the analogue output amplitude.
37
TEST2
Test output 2: pin should be left open-circuit.
38
TEST 3
Test output 3: pin should be left open-circuit.
39
40
VODA
OARO
c..
0
41
OARI+
w
>
w
Operational Amplifier Right Input +: non-inverting input to the right
channel low-pass filter operational amplifier.
42
OARI-
Operational Amplifier Right Input -: inverting input to the right channel
low-pass filter operational amplifier.
43
VDDAR
INTR
Power Supply: + 5 V supply voltage for the analogue right channel.
«
«
C
I-
I-
z
w
~
..J
C
44
= 2,8224 MHz typo
Power Supply: + 5 V supply voltage for logic in the analogue section.
Operational Amplifier Right Output: output from the right channel
operational amplifier.
Integrator Right: output from the right channel switched-capacitor
integrator.
"l
('"January 1988
761
_Jl________
__
SA_A73_20
FUNCTIONAL DESCRIPTION
General
TheSAA7320 CMOS DAC heavily oversamples to several MHz (256 x the sampling frequency, fs), so that the
band-limiting filters required for waveform smoothing and out-of-band noise reduction are mainly digital.
In addition to the digital filters the circuit contains active components for analogue post filtering. In most
applications very few external components are required. An output after the 4 x upsampling filter allows
the circuit to be used as an interface between the decoder and external DAC in high-performance compact
disc systems. The SAA7320 requires only one + 5 V supply; the required reference voltage is generated
internally.
Separate supply pins for each of the 1-bit DACs achieves high performance signal-to-noise ratio and
channel separation.
There is no phase delay between the two analogue outputs despite the fact that the upsampling filter
structure is multiplexed between the two data channels.
Oversampling digital filter
This is a 3-stage digital filter.
• The first stage provides 4 x oversampling to 176,4 kHz using a 128-tap F.I.R. low pass filter. Data is
stored in a cyclic RAM, the filter coefficients in a ROM and the convolutions are performed using an
array multiplier.
• The second stage is a 32 x oversampling linear interpolator.
• The third stage provides 2 x upsampling using a sample and hold, giving a total of 256 x upsampling
(11,2896 MHz).
The first stage oversamples to 176,4 kHz with a band-pass ripple of ± 0,035 dB and a stop-band
attenuation of -60 dB above 24,2 kHz. It also contains frequency response compensation for the
interpolator/analogue post-filtering roll-off and coefficient scaling to prevent overflow in the noise
shapero
The characteristics of the F .I.R. filter are shown in Fig. 8.
Switched-capacitor DAC
The digital-to-analogue conversion is achieved with a 1-bit DAC oversampled to 256 fs with second-order
noise shaping performed digitally to give a 1-bit Pulse Density Modulated (PDM) code with a signal-tonoise ratio of> 90 dB. Integral with the actual 1-bit converter is a first-order low-pass filtering action
which reduces the total HF noise power.
A switched capacitor technique is used for the 1-bit DAC which converts the PDM stream to an analogue
signal with a signal-to-noise ratio of> 90 dB. A fixed charge is either added or substracted from the
virtual earth node of a first-order filter. As this output is a continuous time output a highly symmetrical
operational amplifier is used to give a low distortion figure. The output slew rate of this filter is chosen
so that the operational amplifier always remains within its high gain linear region.
An internally generated out-of-band dither signal is used to suppress audible idling patterns in the noise
shaper at low signal levels. This signal is injected digitally into the x 32 upsampling interpolator at a
frequency 352 kHz and a level of -20 dB.
762
January 1988
(
SAA7320
Stereo CMOS DAC for compact disc digital audio systems
FUNCTIONAL DESCRIPTION (continued)
Attenuation
Attenuation is controlled by the ATT input at pin 36. This input will allow an attenuation of the
analogue output amplitude by -12 dB during track search.
De-emphasis and low-pass filter
Extra on-chip analogue circuitry provides post filtering:
• Input DEC (pin 34) switches an extra external capacitor network into both the left and right channel
analogue integrator feedback to control roll-off.
Output from the right channel switched-capacitor integrator (I NTR) is available at pin 44. Output
from the left channel switched-capacitor integrator (INTL) is available at pin 10.
• A low-pass filter, for further attenuation of out-of-band noise, can be constructed using the internal
CMOS operational amplifiers. The digital filter contains compensation for a third-order Butterworth
filter with a -3 dB cut-off at 60 kHz.
12 S serial interface
The SAA7230 has two
«
I
W
C
1
2
S ports incorporated; DAI (pin 32) and DAO (pin 19).
2
1 S
• DAI receives data from the Compact Disc decoder IC (or any 16-bit 44,1 kHz
• DAO transmits the 4 x oversampled data to an external DAC.
source).
The 'slave' receiver requires a serial bit clock input (CLI; pin 31) and a word select input (WSI; pin 30).
To ensure that the filter is 'in-phase' with the input, the main timing chain is automatically synchronized
to the incoming word select signal. The frequency of the data must also be synchronized to the filter by:
• the source supplying the 11,2896 MHz system clock via crystal oscillator input (XTAL 1; pin 25).
or
• SAA7320 supplying the system clock to the source via XSYS (pin 26) .
The SAA7320 will use only the 16 most significant bits of input data even though the
a variable word length (see Fig. 4).
2
1
S format allows
The 'master' transmitter supplies bit clock, word select and data signals at twice the frequency of the
receiver to allow for the 4 x upsampling. Therefore all 16 bit positions are used.
Conversion path
The SAA7320 data conversion path is shown in Fig. 3. As both paths are identical only one path is
shown. The data flow is in a serial format up to the linear interpolator stage and then separated into
two channels.
CD3A application
A system application diagram of the CD3A with the DAC3 is shown in Fig. 9.
INTER"le
I~S
SOUND
Purchase of Philips 12 S components conveys a license under the
Philips' 12 S patent to use the components in the 12 S-system
provided the system conforms to the 12 S specification defined
by Philips.
Detailed information on the
2
1
C bus specification is available on request.
1
(January 1988
763
___S_AA7_32_0_Jl_________________
16-bit
176,4kHz
attenuation - - -.....--~
mute - - -......- -.....
~-----. . 12S serial output
32x aVE RSAMPLI NG
(linear interpolator)
DITHER SIGNAL ADDED
2 x OVERSAMPLING
(sample and hold)
(2nd order noise shaper)
1- bit
11,2 MHz
1-BITDAC
(switched - capacitor network)
de-emphasis - - -......- - - 4
ANALOGUE OUTPUT
( left or right channel)
7Z95887
Fig.3 Flow diagram of SAA7320 data conversion path (one channel).
764
January 1988
(
l__
Stereo CMOS DAC for compact disc digital audio systems
S_A_A_7_3_20_ __
RATINGS
Limiting values in accordance with the Absolute Maximum System (lEC 134)
parameter
symbol
min.
max.
Supply voltage*
VDDA
-0,5
+ 6,5
V
DC input voltage
VI
-0,5
VDD+0,5
V
DC input diode current
± 20
mA
unit
11K
-
DC output voltage
Vo
-0,5
VDD+0,5
V
DC output source or sink current
10
± 25
mA
DC VDD or VSS current (total)
IDD or ISS
-
± 0,5
A
Storage temperature range
T stg
-65
+ 150
°C
Operating ambient temperature range
Tamb
-40
+85
°C
Electrostatic handling**
Ves
-1000
+ 1000
V
~
«
c
~
2
w
:E
c.
o
..J
W
>
W
C
* All VDD and VSS pins must be connected externally to the same power supply unit.
** Equivalent to discharging a 100 pF capacitor through a 1,5 kSl series resistor with a rise time of
15 ns.
")
~January 1988
765
_S_AA_732_0
_Jl_________
CHARACTERISTICS
VOD
= 4,5 to 5,5 V; VSS = 0 V; Tamb = -40 to + 85 °C unless otherwise specified
parameter
conditions
symbol
min.
typo
max.
unit
Supply
Supply voltage (analogue)
VOOA
4,5
5,0
5,5
V
Supply current (analogue)
IOOA
-
20
*
mA
Supply voltage (digital)
VOO
4,5
5,0
5,5
V
100
-
40
*
mA
High impedance reference
voltage level
VrefC
0, 45V OO 0, 5V OO
0, 55V OO
V
Output reference voltage
relative to VRC
LlVrefO
-10
0
+ 10
mV
Reference voltage output
impedance
IZrefOI
-
2
4
n
Vref
0,4 5V OD
0, 5V OO
0, 55V OO
V
V AO(rms
-
-
1,0
V
ZAO
-
100
200
n
Supply current (digital)
ANALOGUE PART
Reference voltage source
VRO; VRC
Reference voltage inputs
V refL; V refR
Reference input voltage
note 1
Outputs
INTL; INTR
Output level
(RMS value)
note 2;
fs = 44,1 kHz
Output dynamic impedance
Output load resistance
to Vref
RL
10
kn
to Vref
CL
-
-
-
Output load capacitance
+ 20
pF
Output OC level
to Vref
VAOOC
-20
-
+ 20
mV
* Value to be fixed.
766
January 1988
(
l____
Stereo CMOS DAC for compact disc digital audio systems
S_A_A_73_2_0______
symbol
min.
typo
max.
unit
Signal spectrum
(0 dB = F .S.D. input)
< 20 kHz
>24,1 kHz
SS
SS
-0,035
-60
-
+ 0,035
-
-
dB
dB
Signal-to-noise ratio
dB input
-10 dB input
SIN
SIN
90
83
-
-
-
-
dB
dB
THD
-
-
-90
dB
*
-96
-
dB
0-
*
80
-
dB
PSRR
*
60
-
dB
Open loop gain
Gol
*
85
*
dB
Output impedance
IZol
-
100
150
n
Vlos
-10
-
+10
mV
SIN
+ 95
-
-
dB
parameter
conditions
Filter characteristics
note 3
o
Total harmonic distortion
at 0 dB/1 kHz
Digital silence
Mute LOW
Channel separation
at 1 kHz
Power supply rejection
ratio to VDD
Operational amplifiers
«
~
I nput offset voltage
Z
Signal-to-noise ratio
(20 Hz to 20 kHz)
note 4
Total harmonic distortion
(20 Hz to 20 kHz)
note 5
C
I-
w
:E
Q..
o..J
THD
-
-
--94
dB
>
W
Unity gain bandwidth
GBW
5
10
-
MHz
C
Output load to V ref
capacitive
resistive
CL
RL
-
-
200
3
-
-
pF
kn
VIL
-0,5
-
+ 0,8
V
VIH
2,0
-
VDD+0,5
V
III
-10
0
+10
iJ.A
CI
-
-
10
pF
W
DIGITAL PART
Inputs
WSI, CLI, DAI, DEC,
ATT
Input voltage LOW
note 6
I nput voltage HI G H
note 6
Input leakage current
note 7
I nput capacitance
* Value to be fixed.
") ("January 1988
767
___S_AA7_32_0_jl_________________
CHARACTERISTICS (continued)
parameter
conditions
symbol min.
typo
max.
unit
MUTE (Schmitt trigger)
Switching voltage threshold
rising
falling
Input leakage current
note 7
I nput capacitance
Vthr
Vthf
0,54VDD
0,36VDD
0,6VDD 0,66VDD
O,4VDD 0,44VDD
V
V
III
-10
0
+ 10
f.J.A
CI
-
-
10
pF
V
Crystal oscillator input
External clock only
XTAL1
Input voltage LOW
note 6
VIL
-0,5
-
1,5
Input voltage HIGH
note 6
VIH
3,5
-
VDD t05 V V
I nput leakage cu rrent
note 7
III
-10
0
+10
f.J.A
CI
-
-
10
pF
I nput capacitance
Outputs
DAO,CLO,WSO,XSYS
Output voltage LOW
note 6;
-IOL =400f.J.A
VOL
-0,5
-
+0,4
V
Output voltage HIGH
note 6;
IOH = 20f.J.A
VOH
2,4
VDD+0,5
V
CL
-
-
35
pF
Load capacitance
Crystal osci lIator
see Fig. 7
Input XTAL 1
Output XT A L2
Operating frequency XTAL
Mutual conductance
100 kHz
Small signal voltage gain
11,2896 12,3
MHz
-
-
mA/V
-
Gv
3,5
-
V/V
Input capacitance
CI
-
-
10
pF
Feedback capacitance
CFB
-
-
5
pF
Co
-
-
10
pF
III
-10
-
+10
f.J.A
Gv=GmxRO
Output capacitance
Input leakage current
768
fXTAL 8,0
Gm
1,5
January 1988
note 7
(
l____
Stereo CMOS DAC for compact disc digital audio systems
S_A_A_73_2_0______
parameter
conditions
symbol
min.
fc
8,0
11,2896
12,3
MHz
Input rise time
note 8
tr
-
20
ns
I nput fall time
note 8
tf
-
-
20
ns
Input HIGH time
(relative to clock period)
at 1,5 V
tHIGH
45
-
55
%
typo
max.
unit
TIMING
External clock input
XTALl
Input frequency (fs x 256)
System clock output
XSYS
«
note 9
Output rise time
note 8
tr
-
-
20
ns
Output fall time
note 8
tf
-
-
20
ns
Output HIGH time
(relative to clock period)
at 1,5 V
note 10
tHIGH
45
-
55
%
~
12 S TIMING
Z
w
Clock input CLI
o
I nput clock period
tCK
320
354
1000
ns
Input HIGH time
tCKH
112
-
I nput LOW time
tCKL
112
-
-
ns
C
I-
:IE
a..
...I
W
>
""C
Receiver
see Fig. 5
ns
Data inputs WSI, DAI
Data set-up time
tsu; DAT
40
-
-
ns
Data hold time
tHD; DAT
0
-
-
ns
"I ~January
1988
769
jl__________________
___
SA_A7_320_ _
CHARACTERISTICS (continued)
parameter
conditions
Transmitter
see Fig. 6
symbol
min.
typo
max.
unit
Clock output CLO
Output clock period
tCK
-
2/fC
-
ns
Output HIGH time
tCKH
60
-
-
ns
tCKL
60
-
-
ns
tsu; DATWS
40
-
-
ns
-
-
ns
20
ns
20
ns
ns
Output LOW time
Data WSO
Data set-up time
Data hold time
tHO; DATWS
40
Output rise time
tr
-
Output fall time
tf
-
-
Data set-up time
tsu; DATD
40
-
Data output DAO
Data hold time
tHO; DATD
-
Output rise time
tr
40
_.
-
-
20
ns
Output fall time
tf
-
-
20
ns
ns
Notes to the characteristics
1. Any noise at these inputs is transferred directly to the analogue outputs.
2. Output levels depend on integrator components. Value shown is for maximum digital code.
3.
The filter characteristics apply to the complete system at a sampling rate (fs) of 44,1 kHz.
4.
Value relative to 1 V (rms), with unity gain.
5.
Unity gain output
6.
Minimum V, L, VOL and maximum V,H, VOH are peak values to allow for transients.
7.
ILI(min) and 'LO(min) measured at VI
8.
Reference levels = 0,8 V and 2,0 V.
= 1 V (rms).
= 0 V;
'U(max) and 'LO(max) measured at V,
9. Output times are measured with a capacitive load of 35 pF.
10. tHIGH valid only when used with XTAL.
770
January 1988
(
= VDD'
DEVELOPMENT DATA
w
~
o
n
CLI
:s:
o
(I)
2,8224 MHz
C
l>
n
LEFT CHANNEL
WSI
RIGHT CHANNEL
44,1 kHz
Q
C')
o
3
I.
"C
0)
.1
11,34115
~
c.
u;.
C')
c.
DAI
cC'
lZ95891
[
0)
(a)
c
c.
o·
Fig.4(a) Typical 12 S data input waveforms at 2,8 MHz.
-
W
C
Fig.7 Crystal oscillator circuit using crystal type: 4322 14305031.
1(January
1988
773
......
......
~
(J)
»
»""'-I
APPLICATION INFORMATION
7Z95882
0.,
t-
W
Il)
~
c:
II)
-<
magnitude
(dB)
CO
-10
I\.)
o
-20
magnitude
(dB)
-30
(Xl
(Xl
-1,0
7Z95883
-1,2
-40
-1,4
-50
~'in~,0~
-60J
70
-
1
-BO
-1,6
-l,B
-2,0
-90
-2,2
-100
0
2'0
10
30
50
40
60
70
S·O
0
90
10
12
-50
-10
magnitude
(dB)
-70
-30
-SO
-40
-90
-50
-100
-60
-110
-70
-120
-SO
-130
-90
-140
-100
lZ95884
-60
-20
-150 I i i
19
20
21
22
20
frequency (kHz)
O~
magnitude
(dB)
lS
16
14
frequency (kHz)
23
24
25
26
27
2S
30
29
frequency (kHz)
43,0
43,2
43,4
I i i
43,6
43,S
44,0
Fig.8 Digital filter characteristics; magnitude as a function of frequency.
i i i
44,2
44,4
j
44,6
44,S
45,0
frequency (kHz)
DEVELOPMENT DATA
~
CD
V DD
I
~
16k x 4
DYNAMIC RAM
VDD
HFD
1
from photo diode signal processo
Dl1T21
I
Vi
I
disc motor control
12-14,16
(19-21,23)
12"5
9,10,15
(15,16,22)
DEEM/
DINT1
(41) 32
(28)
XTAL1
HFinputfrom~
preamplifier
17 (24)
20
1-8
(27) (7-14)
25 (32)
..L
(26) 19
DEC
Error Correction
Linear Interpolator
I
C
»
(')
left audio
output
XTAL2
OALI +
24
DAC left channel
34
IOALI12
(3) 38
XSYS
I+--
n
r+
VDDA
V SSA
31
a.
eQ'
VRO
16
-----,-t---;
1-1
C
a.
o·
en
VRC
2
1
INPUT
1
9,V 01
OUTPUT 1
~
1
~I
FZ116
-........,1-------'
signal voltage outputs
SAD7630
signal voltage input
reference voltage input
V I2
V ref2
~I
16 1 V 02
INPUT
I
OUTPUT 1
•
J
.1
FZ213
current setting input ----11--------'
8' n.c.
12
7Z24445
elK
analogue ground
external clock input
Fig.1 Block diagram.
not connected
digital ground
l___
Time base correction delay line (TBC)
S_A_D_7_63_0_ __
PINNING
7Z24441
w
Input
elK
external clock input
Inputs (analogue)
V re f1
V re f2
reference voltage inputs
VI1
VI2
signal voltage inputs
FZ1
FZ2
input stage current setting inputs
Outputs (analogue)
V01
V02
signal voltage outputs
1(June
1989
779
Jl_________________________________
______
SA_D_7_63_0___
FUNCTIONAL DESCRIPTION
Principle of variable delay
The input signal is sampled by clock pulses. At each pulse the samples are shifted one step in a
526 stage register. Two parallel multiplexed registers form one delay line. Each register is clocked
by two clock pulses 1,01 and 1,02 which have a phase difference of 1800 .
Effectively the two parallel multiplexed registers operate as a 1052 stage single line at the double
clock frequency. This provides sufficient video bandwidth and delay range for CDV applications.
The delay time is inversely proportional to the clock frequency. Thus for a frequency range of 13 to
24 MHz the following values apply:
6
= 80.92 J.,LS
= 43.83 J.,LS
43.83 = 37.09 J.,LS
• Maximum delay time
1052 -;-13.10
• Minimum delay time
1052 -;- 24.10
• Delay range
80.92 -
6
Video input circuit
FZ
7Z24442
Fig.3 Video input circuit.
Each line has two inputs V, and Vref. The input signal amplitude is defined as V, - Vref.
Within the specified limits V ref can be used to set the required DC input range for V I. The FZ input
can be used to set the current in the input stage.
In the nominal situation FZ is connected to VSB (-3 V typ.) via a 47 kQ resistor.
780
June
19891 (
l__
Time base correction delay line nBC)
S_A_D_7_6_30_ _- - - I
Video input signal
PAL
123%----------
100%1------0.85 V (p-p)
3OJ--0-----
7Z24444
-30%-----
e::(
le::(
o
I2
Fig.4 Video input signal for PAL.
w
::?!
Q.
o
..J
W
>
W
The PAL line waveform of 100% saturated colour bars with special burst.
Tip sync to top-white = 100% ~ 0.85 V (p-p).
Thus the maximum signal amplitude can become 150% x 0.85 V (p-p) = 1.3 V (p-p).
o
NTSC
123%
----------f:ITIFIJ
100%1------1 V (p-p)
3O%L-0----7Z24443
Fig.5 Video input signal for NTSC.
The NTSC line waveform of 100% saturated colour bars.
Tip sync to top-white = 100% ~ 1.0 V (p-p).
Thus the maximum signal amplitude can become 123% x 1.0 V (p-p)
= 1.23 V
(p-p).
10une
1989
781
_Jl_________
__
SA_D76_30
FUNCTIONAL DESCRIPTION (continued)
Supplies
Separate supply voltages {VDDA and VDDD are provided to prevent interference between analogue and
digital circuits. However, it is still necessary to connect decoupling capacitors as near as possible to the
respective ground pins. At decreasing VDDD the transfer loss for high input frequencies at maximum
fCLK is increasing, therefore care must be taken not to exceed the specification limits of VDDD
(4.75 V to 5.5 V).
Clock circuit
The externally applied clock signal is internally converted to a squarewave. Flipflops generate two
antiphase signals (<,O1 and <,02) at half the clock frequency which operate the registers.
Output circuit
The output signals of the two multiplexed registers are demultiplexed and stored in a hold capacitor.
A buffer stage following the hold capacitor is non-inverting and has a low output impedance (100 n
typ.).
782
June
19891 (
l__
Time base correction delay line (TBC)
S_A_D_7_6_30_ __
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
parameter
conditions
Supply voltage range
analogue
digital
symbol
min.
max.
unit
VDDA
-0.5
+7.0
V
VDDD
-0.5
+7.0
V
-0.5
VDD+0.5
V
Input voltage
note 1
VI
Output voltage
note 1
Va
-0.5
VDD+0.5
V
Maximum input current
11M
-
±10
mA
Maximum output current
±10
rnA
10M
-
Maximum supply current in VSSA; VSSD
ISS
-
-30
rnA
Maximum supply current in VDDA; VDDD
IDD
-
+30
rnA
Total power dissipation
Ptot
-
500
mW
Storage temperature range
Tstg
-55
+ 150
oC
Operating ambient temperature range
Tamb
-25
+ 70
oC
e:(
le:(
C
IZ
w
Note to the Ratings
1. Input voltage should not exceed 7 V unless otherwise specified.
:!!
HANDLING
o..J
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MaS devices (see
'Handling MaS Devices').
CL
W
>
W
C
"\ (June
1989
783
Jl_________________________________
_____S_A_D_7_63_0___
DC CHARACTERISTICS
Tamb = -25 to + 70
Fig.6.
OCt
unless otherwise specified; all parameters measured with the test circuit of
parameter
conditions
symbol
min.
typo
max.
unit
VOOA
VOOO
-VS8
4.75
4.75
3.5
5.0
5.0
3.0
5.5
5.5
2.5
V
V
V
IOOA
1000
IIS81
1
8
2
12
-
-
4
16
100
rnA
rnA
/lA
DC input voltage
Vref
0
-
1.5
V
Input current level
Iref
-
-
10
/lA
VI
0
1
1.6
V
RI
CI
1
-
-
10
Mn
pF
Input voltage amplitude
(peak-to-peak value)
VAC(p-p)
0.30
0.60
0.90
V
DC output voltage
VOC
1.5
V
IDC
-
150
/lA
Input frequency
fClK
13
-
3.5
Input current
24
MHz
-VOC
1.5
-
0.5
V
Vo
Vo
0.25
2.0
0.5
.2.5
0.75
3.0
V
V
-
1
rnA
250
n
10
10
kn
pF
Supply
Supply voltage range
analogue
digital
substrate bias
Supply current range
II =OmA;
fClK = 16.6 MHz
analogue
digital
substrate bias
Inputs
V re fl; V re f2
Vll;V12
Signal amplitude
VI = Vref
Input impedance
ClK
FZ1; FZ2
OC input voltage
w.r.t. Vref
Outputs
VOl; V02
RFZ to VS8 = 47 kn
OC output voltage
V I to V ref = 0 V
VI to Vref = 1.6 V
1101
-
Output impedance
RO
Maximum load impedance
Rl
CL
-
DC output current
784
June
19891 (
l__
Time base correction delay line (TBC)
sA_D_7_6-,.-30_ __
AC CHARACTER ISTICS
VDDD =4.75 to 5.5 V; T amb
the test circuit of Fig.6.
= -25 to + 70 oc , unless otherwise specified; all parameters measured with
parameter
conditions
symbol
min.
typo
max.
unit
Gv
2
3
4
dB
Hd
1.0
2.5
4.5
dB
-
6
%
-
5
%
Q{j
-
-
5
deg.
Va
-
30
70
mV
VLCLK
VLCLK
VLCLK
-
-
8
-
-
20
20
mV
mV
mV
Voltage gain
note 1
Transfer loss at 5 MHz
(w.r.t. 1 kHz)
fCLK
= 13 and 24 MHz
Linearity error
note 2
Le
Differential gain
note 2
Gd
Differential phase
note 2
DC output voltage
Clock leakage voltage
(RMS value)
6.5 MHz
13 MHz
19.5 MHz
fCLK
= 13 to 24 MHz
I-
Noise output voltage
(RMS value)
B = 5 MHz (unweighted)
Von(rms)
-
-
*
mV
C
I-
Crosstalk attenuation
between lines
note 3
ax
:?!
d
-
dB
note 4
-
*
Distortion
10
%
~
~
Z
w
0-
o
u::
Notes to the AC characteristics
~
1. VI to Vref
>
2. VI to Vref
3. VI to Vref
4. VI to Vref
=
=
=
=
1 V(p-p); fi
= 1 kHz; fCLK = 16.6 MHz.
1 V(p-p); fCLK = 16.6 MHz.
1 V(p-p); fi
= 2 MHz; fCLK = 16.6 MHz.
1.6 V(p-p); fi
* Value to be fixed.
= 1 kHz,;fCLK = 16.6 MHz.
1(June
1989
785
~
co
0')
en
c.....
r:::
:::s
+5.0V
CD
22 nF
co
I
2.2
»
o
external
clock input
(0.60 V)
+5.0V
50
'"
0)
n
W
o
+5.0V
n
OJ
CO
22 nF
V 0001
10
elK
15
13
12
SAD7630
signal
voltage input
47 !J.F
viii
----I1t-.-....---+----..:....:...!
4
11
14
V Oi
100
kn
47 !J.F
signal
• II--- voltage input
16
FZ1
47
I VI?
n
V 02
+12 V
1
kn
100
(2)
122 nF
.
-3 V
(1) DC measurements.
(2) AC measurements.
Fig.6 Measuring circuit.
se55a
n
+12 V
~,
kn -3V
lL'21
se55a
7Z24446
_~_J
SAF1032P
SAF1039P
REMOTE CONTROL SYSTEM FOR INFRARED OPERATION
The SAF 1032P (receiver/decoder) and the SAF 1039P (transmitter) form the basic parts of a sophisticated remote control system (pcm: pulse code modulation) for infrared operation. The ICs can be
used, for example, in TV, audio, industrial equipment, etc.
Features:
SAF1032P receiver/decoder:
• 16 programme selection codes
• automatic preset to stand-by at power 'ON', including automatic analogue base settings to 50% and
automatic preset of programme selection '1' code
• 3 analogue function controls, each with 63 steps
• single supply voltage
• protection against corrupt codes.
SAF1039P transmitter:
• 32 different control commands
• static keyboard matrix
• current drains from battery only during key closure time
• two transmission modes selectable.
The devices are implemented in LOCMOS (Local Oxidation Complementary MOS) technology to
achieve an extremely low power consumption.
Inputs and outputs are protected against electrostatic effects in a wide variety of device-handling
situations. However, to be totally safe, it is desirable to take handling precautions into account.
SELC
{IlSCI
SELD
TRY2
DATA
I
I
TRSL
I
HI3LD
TR{Ill
TR¢2
I
14
SAF1032P
2
L3{1lT
I
L211lT
4
L1IZ1T
I
BIND
6
BINC
I
2
BINA
TRXO
I
TRXl
BINB
4
TRX2
I
TRX3
6
TROT
I
TR{/lS
TINH
7Z74349.1
7Z74348
Fig. 1 Pin designations.
PACKAGE OUTLINES
SAF1032P: 18-lead 01 L; plastic (SOT102),
SAF1039P: 16-lead OIL; plastic (SOT38Z).
I (June
1981
787
SAF1032P
SAF1039P
PINNING
To facilitate easy function recognition, each integrated circuit pin has been allocated a code as shown
below.
SAF1032P
1
2
3
4
5
6
7
8
9
L3CZ>T
L2CZ>T
L1CZ>T
BIND
BINC
BINB
BINA
TVCZ>T
linear output
linear output
linear output
binary 8 output
binary 4 output
binary 2 output
binary 1 output
on/off input/output
VSS
10
11
12
13
14
15
16
17
18
HCZ>LD
DATA
MAIN
CZ>SCI
SELD
SELC
SELB
SELA
9
10
11
12
13
14
15
16
TRCZ>1
TRCZ>2
TRSL
TRY3
TRY2
TRY1
TRYO
control input
data input
reset input
clock input
binary 8 output
binary 4 output
binary 2 output
binary 1 output
VDD
SAF1039P
1
2
3
4
5
6
7
8
788
TRXO
TRX1
TRX2
TRX3
TRDT
TINH
TRCZ>S
VSS
June
keyboard input
keyboard input
keyboard input
keyboard input
data output
inhibit output/mode select input
oscillator output
19811 (
VDD
oscillator control input
oscillator control input
keyboard select line
keyboard input
keyboard input
keyboard input
keyboard input
SAF1032P
SAF1039P
Remote control system for infrared operation
BASIC OPERATING PRINCIPLES
The data to be transmitted are arranged as serial information with a fixed pattern (see Fig. 2), in
which the data bit-locations BO to B4 represent the generated key-command code. To cope with I R
(infrared) interferences of other sources a selective data transmission is present. Each transmitted bit
has a burst of 26 oscillator periods.
Before any operation will be executed in the receiver/decoder chip, the transmitted data must be
accepted twice in sequence. This means the start code must be recognized each time a data word is
applied and comparison must be true between the data bits of two successively received data words. If
both requirements are met, one group of binary output buffers will be loaded with a code defined by
the stored data bits, and an internal operation can also take place. See operating code table.
The contents of the 3 analogue function registers are available on the three outputs in a pulse code
versus time modulation format after D (digital) to A (analogue) conversion. The proper analogue levels
can be obtained by using simple integrated networks. For local control a second transmitter chip
(SAF 1039P) is used (see Fig. 7).
DATA
MODE1
DATA
MODE2
~
_ _~~_ _ _ _ _ _~~_ _ _ _ _ _ _ _~_ _~~~_ _~~~~_ _ _ _~~~L-_ _ _ _ _ _ _ _ _ _~
,rkey down
TINH
,...~t----------- start code
------------1~.....t-----------
,...~t--------------------------(1) TO
= 1 clock period = 128 oscillator periods.
one data word
data bits ------------••,
---------------------------~
32 x To =32 x :f!... ms (2 )
ft
7Z743S1.2
(2) f t in kHz.
Fig. 2 Pattern for data to be transmitted.
TIMING CONSIDERATIONS
The transmitter and receiver operate at different oscillator frequencies. Due to the design neither
frequency is very critical, but correlation between them must exist. Calculation of these timing
requirements shows the following.
With a tolerance of ±10% on the oscillator frequency (f t ) of the transmitter, the receiver oscillator
frequency (f r = 3 x f t ) must be kept constant with a tolerance of ±20%.
On the other hand, the data pulse generated by the pulse stretcher circuit (at the receiver side) may
vary ±25% in duration.
I (June
1981
789
SAF1032P
SAF1039P
GENERAL DESCRIPTION OF THE SAF1039P TRANSMITTER
SAF1039P
1 TRXO
TROT 5
2 TRX1
ENCODING
r=:>
3 TRX2
TINH
4 TRX3
15 TRYO
OUTPUT
GATING
1
INPUT
CONTROL
U
14 TRY1
13 TRY2
12 TRY3
6
~
OSCILLATOR
SCALER
27
11 TRSL
vOO
16
1
N
(/)
S
S
I--
I--
I--
9
10
7
&
a::
a::
a::
vSS
8
7Z74350.1
1
Fig. 3 Block diagram of SAF 1039P transmitter.
Any keyboard activity on the inputs TRXO to TRX3, TRYO to TRY3 and TRSL will be detected. For
a legal key depression, one key down at a time (one TRX and TRY input activated), the oscillator
starts running and a data word, as shown on the previous page, is generated and supplied to the output
TR DT. If none, or more than 2 inputs are activated at the same time, the input detection logic of the
chip will generate an overall reset and the oscillator stops running (no legal key operation).
This means that for each key-bounce the logic will be reset, and by releasing a key the transmitted data
are stopped at once.
The minimum key contact time required is the duration of two data words. The on-chip oscillator is
frequency controlled with the external components R 1 and C1 (see circuit Fig. 6); the addition of
resistor R2 means that the oscillator frequency is practically independent of supply voltage variations.
A complete data word is arranged as shown in Fig. 2, and has a length of 32 x TO ms, where TO = 2 71ft .
Operation mode
790
DATA
FUNCTION OF TINH
1
unmodulated: LOCAL operation
output, external pull-up resistor to VDD
2
modulated: REMOTE control
input, connected to VSS
June 1981
1(
SAF1032P
SAF1039P
Remote control system for infrared operation
GENERAL DESCRIPTION OF THE SAF1032P RECEIVER/DECODER
7
«
10 H0LD
6
m
z
iii
z
iii
4
5
u
z
iii
16
17
«
0
Z
...J
w
en
iii
IIBINARY OUTPUT'
m
15
u
...J
...J
w
en
w
en
14
0
...J
w
en
'BINARY SELECT'
FLAGS (SELF)
FLAGS (BINF)
LINEAR 1
REGISTER
~
DIGITAL TO
ANALOGUE
CONVERSION
(D/A)
r+-
DIGITAL TO
ANALOGUE
CONVERSION
(D/A)
t-+-
DIGITAL TO
ANALOGUE
CONVERSION
(D/A)
(LIN')
LINEAR 2
REGISTER
(LlN2)
II
I
BUFFER
REGISTER
(BFR)
I
,
I
ANALOGUE
DECODER
(ANDEC)
~
~
I
DATA SHIFT
REGISTER
(SRDT)
I
I
COMPARATOR
(K0M)
I
,'0 / '"
+
START CODE
DETECTION
(CST0)
Voo
11 8
+
I
I
TIMER COUNTER
(CTlM)
I
L30T 1
{
COMPARATOR
COUNTER
(C0MP)
BIT COUNTER
(BITC)
OETECTOR
L20T 2
m
I
+
I
11 DATA
LINEAR 3
REGISTER
(LlN3)
L10T 3
TIL
II 1
I t
I
MAIN
FLAG
(MAINF)
MAIN 12
[TV ON/OFF
TV0T 8
FLAG
(TV0NF)
PRESET
FLAG
(PREST)
SAF1032P
OSCI 13
Vss
9
7Z74352
1
Fig. 4 Block diagram of SAF 1032P receiver/decoder.
The logic circuitry· of the receiver/decoder chip is divided into four main parts as shown in the block
diagram above.
Part I
This part decodes the applied DATA information into logic '1' and '0'.
It also recognizes the start code and compares the stored data-bits with the new data-bits accepted.
'I (June
1981
791
SAF1032P
SAF1039P
l______
Part II
This part stores the programme selection code in the output group (BIN F) and memorizes it for
condition HLD = LOW.
It puts the functional code to output group (SE LF) during data accept time, and decodes the internally
used analogue commands (ANDEC).
Part III
This part controls the analogue function registers (each 6-bits long), and connects the contents of the
three registers to the analogue outputs by means of D/A conversion. During sound mute, output L 1T
will be forced to HIGH level.
Part IV
This part keeps track for correct power 'ON' operation, and puts chip in 'stand-by' condition at supply
voltage interruptions.
The logic design is dynamic and synchronous with the clock frequency (SCI), while the required
control timing signals are derived from the bit counter (BITC).
Operation
Serial information applied to the DATA input will be translated into logic '1' and
time ratio detector.
'a' by means of a
After recognizing the start code (CSTM) takes
place between the contents of SRDT and the buffer register (BF R). If SRDT equals BFR, the required
operation will be executed under control of the comparator counter (CMP).
As shown in the operating code table on the next page, the4-bit wide binary output buffer (BINF) will be
loaded for BFRO = 'a', while for BFRO = '1' the binary output buffer (SELF), also 4-bit wide will be
activated during the data accept time.
At the same time operations involving the internal commands are executed. The contents of the
analogue function registers (each 6-bits long) are controlled over 63 steps, with minimum and maximum
detection, while the D/ A conversion results in a pulsed output signal with a conversion period of
384 clock periods (see Fig. 5).
First power 'ON' will always put the chip in the 'stand-by' position. This results in an internal
clearing of all logic circuitry and a 50% presetting of the contents of the analogue registers (analogue
base value). The programme selection '1' code will also be prepared and all the outputs will be nonactive (see operating output code table).
From 'stand-by' the chip can be made operational via a programme selection command, generated
LOCAL or via REMOTE, or directly by forcing the TV ON/OFF output (TVT) to zero for at least
2 clock periods of the oscillator frequency.
For POWER ON RESET a negative-going pulse should be applied to input MAIN, when VDD is
stabilized; pulse width LOW ~ 100 f.J.s.
..., ,.-6 clock periods
ANALOGUE
OUTPUT
(SQ%contents)
n n n n n n n n
.J U U U U U U U L __
I.
JUUlJl
384 clock periods
~,
7Z76078
Fig. 5 Analogue output pulses.
792
June
19811 (
SAF1032P
SAF1039P
Remote control system for infrared operation
OPERATING CODE TABLE
buffer
BFR
key-matrix
position
TRX. TRY. TRSL 0
0
0
0
0
1
1
1
1
0
1
2
3
0
1
2
3
2
2
2
2
3
3
3
3
0
0
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
1
2
3
0
1
2
3
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
SELF
(SEL.)
BINF
(BIN.)
B
0
A
B
C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
programme
select + ON
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
programme
select + ON
1
1
1
1
1
1
1
1
2
3
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A
1
0
1
0
1
0
1
1
0
1
0
1
0
function
C
4
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
analogue base
reg. (LlN3) + 1
reg. (LlN2) + 1
reg. (LI N 1) + 1
OFF
reg. (LlN3) - 1
reg. (LlN2) - 1
reg. (LI N 1) - 1
mute (set/reset)
spare functions
Note
Reset mute also on programme select codes, (LI N 1) ± 1, and analogue base.
"I (June
1981
793
l
SAF1032P
SAF1039P
-------------------------------------------------------------OPERATING OUTPUT CODE
(L.(])T)
(SEL.)
(BIN.)
TV(])T
A
B
C
A
B
C
D
1
2
3
'stand-by' OFF
via remote
a
a
a a a
0
a
a
1
0
a
1
ON - 'not hold' condition
non-operati ng
1
1
1
1
1
1
1
1
X
X
X
0
ON - 'hold' condition
non-operating
X
X
X
X
1
1
1
1
X
X
X
0
D
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage
VDD-VSS
I nput voltage
VI
max.
Current into any terminal
±II
max.
10 mA
Power dissipation (per output)
Po
Ptot
max.
50 mW
max.
200 mW
Power dissipation (per package)
Operating ambient temperature
Storage temperature
794
-0,5 to 11 V
June
19811 (
Tamb
T stg
11 V
-40 to +85 oC
-65 to +150 °C
SAF1032P
SAF1039P
Remote control system for infrared operation
CHARACTERISTICS
Tamb = 0 to +85 0C (unless otherwise specified)
SAF1039P only
Recommended supply voltage
symbol
min.
VOO
7
VOO
V
Tamb
typo
max.
-
10
V
1
10
50
JlA
JlA
10
7
25
65
0,8
1,7
-
mA
mA
10
10
all
25
V
VOO
O, 2V OO V
1
JlA
7 to 10
7 to 10
10
all
all
25
°C
Supply current
100
operating; TR01 at VSS;
outputs unloaded;
one keyboard switch
closed
100
-
Inputs (note 1)
TR02; TINH (note 2)
input voltage HIGH
input voltage LOW
input current
VIH
VIL
II
O, 8V OO 0
10- 5
-
Outputs
TROT; TR0S; TR01
output cu rrent HI G H
at VOH = VOO -0,5 V
-IOH
0,4
-
-
mA
7
all
output current LOW
atVOL=O,4V
IOL
0,4
-
-
mA
7
all
TROT output leakage
current when disabled
Vo = VSS to VOO
IOL
-
-
1
JlA
10
25
IOL
0,4
-
-
mA
7
all
kHz
7 to 10
all
10
25
TINH
output current LOW
VOL=O,4V
I
I
-
quiescent
Oscillator
maximum oscillator
frequency
-
-
fosc
120
-
-
frequency variation with
supply voltage, temperature
and spread of IC properties
at f nom = 36 kHz (note 3)
~f
-
-
O,15f nom
oscillator current drain
at f nom = 36 kHz
losc
-
1,3
2,5
L
Notes follow characteristics.
mA
'I (June
1981
795
SAF1032P
SAF1039P
Remote control system for infrared operation
Notes to characteristics
1. The keyboard inputs (TRX.; TRY.; TRSL) are not voltage driven (see application information
diagram Fig. 6).
If one key is depressed, the circuit generates the corresponding code. The number of keys
depressed at a time, and this being recognized by the circuit as an illegal operation, depends on the
supply voltage (VOO) and the leakage current (between device and printed-circuit board) externally
applied to the keyboard inputs.
If no leakage is assumed, the circuit recognizes an operation as illegal for any number of keys> 1
depressed at the same ti me with V 0 0 = 7 V . At a leakage due to a 1 Mn resistor connected to each
keyboard input and returned to either VOO or VSS, the circuit recognizes at least 2 keys depressed
at a time with VOO = 7 V.
The highest permissible values of the contact series resistance of the keyboard switches is 500
n.
2. Inhibit output transistor disabled.
3. Llf is the width of the distribution curve at 2 a points (a
= standard deviation).
4. Terminal TVQ)T is input for manual 'ON'. When applying a LOW level TVQ)T becomes an output
carrying a LOW level.
'I (June
1981
797
l
SAF1032P
SAF1039P
_
----------------------------------------------------------APPLICATION INFORMATION
+
+
9V
C1
150 pF
SAF1039P
(2%)
R2100kn
_____A....._ _,
s: saturation
B: brightness
V:volume
7Z74353.2
Fig.6 Interconnection diagram of transmitter circuit SAF1039P in a remote
control system, for a television receiver with 12 programmes.
798
June
19811 (
1 nF
:JJ
(1)
+12V~~
I------~--- V DD 1+9 VI
3
o
S'
n
PULSE
STRETCHER
12x 1/4HEF4011BI
1B
o
:J
r+
2~
en
nF
BPW34
S'
....3
OSCILLATOR
12 x 1/4 HEF4011 BI
3,3
nF
1/4 HEF4011 B
j 1/4HEF4011B
I I I
VSS
Q
:;.
::t
~
(1)
c.
o
+12V
"t:I
~
POWER ON
RESET
Ql
r+
o·
:J
27 k>2
BZX79
-C7V5
~RII ~RII k1R
BAW62
+12V
10
VSS
12
13
SAF1039P
t...
c:
:J
(1)
CO
CO
--"
~~
~
=150 P
12%1
FI
5J~ [5:iJ ~
I~~ ~ ~
[3J ~
6J
~
".{
} selection
." ",o,""m.
SAF
1032P
switch ICs
EJ G EJ
IT] IT] IT] I
for interface
see Fig. 8
en en
»»
"'Tl"'Tl
..........
00
Fig. 7 Interconnection diagram showing the SAF1032P and SAF1039P used in a TV control system.
~
co
WW
CON
-U-u
l
SAF1032P
SAF1039P
_
--------------------------------------------------------Voo
+12V
volume
(pin 5; TBA750)
Voo
+12V
brightness
(pin 11; TDA2560)
2
Voo
+12V
saturation
(pin 16; TDA2560)
3
33 k!l.
to pin 9 of TDA2581
~-_~....
to pin 4 of TDA2581
7Z743S4.1
Fig. 8 Additional circuits from outputs L 10T (1), L20T (2), L30T (3) and
TV0T (4) of the SAF1032P in circuit of Fig. 7.
------8-00--------JU-n-e-1-98-1-'1.~
~~_J
TDA10018
TDA10018T
INTERFERENCE AND NOISE SUPPRESSION CIRCUIT
FOR FM RECEIVERS
GENERAL DESCRIPTION
The TOA 1001 B is a monolithic integrated circuit for suppressing interference and noise in FM mono
and stereo receivers.
Features
• Active low-pass and high-pass filters
• Interference pulse detector with adjustable and controllable response sensitivity
• Noise detector designed for FM Lt. amplifiers with ratio detectors or quadrature detectors
• Schmitt trigger for generating an interference suppression pulse
• Active pilot tone generation (19 kHz)
• Internal voltage stabilization
QUICK REFERENCE DATA
Supply voltage (pin 9)
Vp
typo
12 V
Supply current (pin 9)
Ip
typo
14 mA
A.F. input signal handling (pin 1)
(peak-to-peak value)
Vi(p-p)
typo
1 V
Input resistance (pin 1)
Ri
min.
35 kn
Voltage gain (V1-16/V6-16)
Gv
typo
0,5 dB
Total harmonic distortion
THO
typo
Bandwidth
0,25 %
B
typo
Suppression pulse threshold voltage
(peak value); R13 = 0
Vi(tr)OM
typo
19 mV
Suppression pulse duration
ts
typo
27 fJ.S
Supply voltage range (pin 9)
Vp
Operating ambient temperature range
70 kHz
7,5 to 16 V
-30 to +80 oC
Tamb
PACKAGE OUTLINE
TOA1001B:
16-lead OIL; plastic (SOT38).
TOA1001BT: 16-lead mini-pack; plastic (SO 16; SOT109A).
I
(December 1982
801
l
TDA10018
TDA10018T
....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
r--+-
HIGH -PASS
FILTER
~R13
-+-
'r
R11]
HIGH -PASS
AMPLIFIER
14
-4-
TDA1001 B
to Vp
~'£
,
1
INPUT STAGE
(EMITTERFOLLOWER)
r-2
13
,-
12
A.G.C.
AMPLIFIER
r-- r+-
NOISE
DETECTOR
r+-
LOW-PASS
AMPLIFIER
1-- .......
3
LOW-PASS
FILTER
II
INTERFERENCE
PULSE
DETECTOR
-4-
-f-
4
-+-
5
19821 (
R10
----c=:J----<
10
9
SUPPRESSION
PULSE
GENERATOR
SUPPLY
VOLTAGE
STABILIZER
I--
19 kHz
PILOT-TONE
GENERATOR
INTERFERENCE
SUPPRESSION ' - PULSE STAGE
Fig. 1 Block diagram.
December
R12
11
6
-t t--c:::J- I-a.f. output
802
II
..
-c:=::J----<
'--
.;;-
15
Vp
;;;~C11
17
18
I
I
1,6
~
19 kHz
FILTER
7Z87l7l
TDA10018
TDA10018T
Interference and noise suppression circuit for FM receivers
RATINGS
Limiting values in accordance with the Absolute Maximum System (lEe 134)
V
Supply voltage (pin 9)
Vp
max.
18
Input voltage (pin 1)
V 1-16
max.
Vp V
Output current (pin 6)
max.
max.
1 rnA
15 rnA
Total power dissipation
see derating curves Fig. 2
Storage temperatu re range
T stg
-65 to +150 oe
Operating ambient temperature range
Tamb
-30 to +80 oe
7Z87172
1,5
Ptot
(W)
1---
'----
~
,
,,
~
\
',\
" ~,,~
0,5
't\.
~
o
o
'\
50
Fig. 2 Power derating curves.
in plastic 01 L (SOT-38) package (TOA 1001 B)
in plastic mini-pack (SO-16; SOT-109A) package (TOA1001BT); mounted on a ceramic
substrate of 50 x 15 x 0,7 mm.
'I
(December 1982
803
TDA10018
TDA10018T
Interference and noise suppression circuit for FM receivers
symbol
min.
typo
max.
unit
Internal resistance (pins 13 and 14)
R 13-14
1,5
2,0
2,5
kf2
Operational threshold voltage
(uncontrolled); peak value (pin 14)
of the interference pulse detector
±V14intm
-
15
-
mV
parameter
A.G.C. amplifier; interference and
noise detectors
±V14n m
-
6,5
-
mV
Output voltage (peak value; pin 11)
V11-16M
5,2
5,8
6,4
V
Output control current (pin 12)
(peak value)
of the noise detector
112M
150
200
250
IlA
Output bias current (pin 12)
1012
-
2,5
6
IlA
Input threshold voltage for onset
of control (pin 12)
(Vi(tr)O + 3 dB)
V12-9
or:
360
-
500
-
mV
mV
V11-16
-
3,2
-
V
V11-16
-
2,0
-
V
425
0,66VBE
Suppression pulse generation
(Schmitt trigger)
Switching threshold (pin 11)
1: gate disabled
2: gate enabled
~V11-16
-
1,2
-
V
Input offset current (pin 11)
lioll
-
-
100
nA
Output current (pin 10)
gate disabled; peak value
Switching hysteresis
lo10M
0,6
1
1,4
mA
Reverse output current (pin 10)
IR10
-
2
IlA
Sensitivity (pin 10)
VlO-16
2,5
-
-
V
'I (
December 1982
805
l
TDA10018
TDA10018T
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
APPLICATION INFORMATION
Vp
= 12 V; Tamb = 25 °C; f = 1 kHz;
measured in Fig. 4; unless otherwise specified
parameter
symbol
min.
typo
max.
unit
Supply voltage range (pin 9)
Vp
7,5
12
16
V
Quiescent supply current (pin 9)
Ip
10
14
18
rnA
Vl-16
IZ i11
-
4,5
-
V
35
-
-
kQ
V6-16
2,4
2,8
-
V
Signal path
D.C. input voltage (pin 1)
I nput impedance (pin 1); f
=40 kHz
D.C. output voltage (pin 6)
Output resistance (pin 6)
R06
Voltage gain (V6/V 1)
GV 6/1
0
0,5
1
dB
low-ohmic
-3 dB point of low-pass filter
f(-3dB)
-
70
-
kHz
Sensitivity for TH D < 0,5%
(peak-to-peak value)
Vi(p-p)
1,2
1,8
-
V
Residual interference pulse after suppression
(see Fig. 3); pin 7 to ground;
Vi(tr)M = 100mV; (peak-to-peak value)
V6-16(p-p)
-
-
3
mV
Interference suppression at R13 = 0;
notes 5 and 6; Vi(rms) = 30 mV; f = 19 kHz
(sinewave); Vi(tr)M = 60 mV; fr = 400 Hz
~int
20
30
-
dB
Vi(tr)rms
8
11
14
mV
I nterference processing
Input signal at pin 1; output signal at pin 10
Suppression pulse threshold voltage; control
function OFF (pin 9 connected to pin 12);
r.m.s. value; note 1
measured with sinewave input signal
f = 120 kHz; -V10-9> 1 V
at R13 = 0 Q
at R13
= 2,7 kQ
Vi(tr)rms
18
28,5
40
mV
voltage difference for safe triggering/
non-triggering (r.m.s. value)
LlVi(rms)
-
1
-
mV
measured with interference pulses
f = 400 Hz (see Fig. 3); peak value
at R13 = 0 Q
Vi(tr)M
-
19
-
mV
Vi(tr)M
-
45
-
mV
ts
24
27
30
f.1,S
at R13
= 2,7 kQ
Suppression pulse duration (note 2)
806
December
19821 (
TDA10018
TDA10018T
Interference and noise suppression circuit for FM receivers
symbol
parameters
min.
typo
max.
unit
Vni(rms)
2,3
Vni(rms)
-
3,3
4,3
mV
8,2
-
mV
Vni(rms)
Vni(rms)
-
7,3
16,5
-
mV
-
Vni(rms)
33
45
57
mV
Vni(rms)
-
107
-
mV
V o6(rms)
49
-
56
mV
Vo6(rms)
45
-
65
mV
Noise threshold feedback control
(notes 1 and 3)
Noise input voltage (r.m.s. value)
f = 120 kHz sinewave
for V12-9 = 300 mV
at R13 = 0 n
= 2,7 kn
for V12-9 = 425 mV (Vi(tr)O + 3 dB)
at R13 = 0 n
at R13 = 2,7 kn
for V 12-9 = 560 mV (Vi(tr)O + 20 dB)
at R13 = 0 n
at R13 = 2,7 kn
at R13
Amplification control voltage by interference
intensity (note 4)
Vi(rms) = 50 mV; f = 19 kHz;
Vi(tr)M = 300 mV; r.m.s. value
at repetition frequency f r = 1 kHz
at repetition frequency fr
= 16 kHz
'I
mV
(December 1982
807
TDA10018
TDA1001BT
l
---------------------------------------------------------------------
Notes to application information
1. The interference suppression and noise feedback control thresholds can be determined by R 13 or a
capacitive voltage divider at the input of the high-pass filter and they are defined by the following
formulae:
Vi(tr) :::: (1 + R13/RS) x Vi(tr)O in which RS:::: 2 kQ;
Vni :::: (1 + R13/RS) x VniO in which RS:::: 2 kQ.
2. The suppression pulse duration is determined by Cll :::: 2,2 nF and Rll :::: 6,8 kQ.
3. The characteristic of the noise feedback control is determined by R 12 (and R 10).
4.
The feedback control of the interference suppression threshold at higher repetition frequencies is
determined by Rl0 (and R12).
5.
The 19 kHz generator can be adjusted with R7-16 (and R7-8). Adjustment is not required if components with small tolerances are used e.g. LlR < 1% and LlC < 2%.
6.
Measuring conditions:
The peak output noise voltage (V no m, CCITT filter) shall be measured at the output with a deemphazing time T:::: 50 I1S (R :::: 5 kQ, C:::: 10 nF); the reference value of 0 dB is Vo int with the
19 kHz generator short-circuited (pin 7 grounded).
± vi(tr)M
7Z87173
(mV)
1
0,9
0,5
0,1
SQUARE-WAVE
INPUT VOLTAGE
o
-----
:I
-ttr-I
I-td
SUPPRESSION
PULSE (TRIGGER)
OUTPUT
VlO-9 0
I
-ts=27ILs
(V)
II
I
-1,5
I
I
I
_J
IV
over - shoot of the
low- pass filter
OUTPUT
VOLTAGE
V 6 16
1
(mV)
0
~1
-[ \J
'--
-1
offset voltage
and drift
-2
o
10
20
30
I
voltage
40
*
time (ILS)
50
Fig. 3 Measuring signal for interference suppression; at the input (pin 1) a square-wave is applied
with a duration of ttr :::: 10 I1S and with rise and fall times tr :::: tf:::: 10 ns.
808
December
19821 (
TDA10018
TDA10018T
Interference and noise suppression circuit for FM receivers
HIGH - PASS FI L TER
Vs
(10 to 16V)
R13~
R11
6,8 kn
15
14
Ye11
2,2 nF
10 nF
16
~68n
13
to Vp
12
11
220nF
10
TDA1001B
4
6
3,9
6,8 nF
LOW-PASS FILTER
nF
19kHz FILTER
Fig.4 Application circuit diagram.
I
(December 1982
809
__________________Jl__
TD_A1_010A
_ _ _1
6 W AUDIO POWER AMPLIFIER IN CAR APPLICATIONS
10 W AUDIO POWER AMPLIFIER IN MAINS-FED APPLICATIONS
The TDA 1010A is a monolithic integrated class-B audio amplifier circuit in a 9-lead single in-line (SI L)
plastic package. The device is primarily developed as a 6 W car radio amplifier for use with 4 nand
2 n load impedances. The wide supply voltage range and the flexibility of the IC make it an attractive
proposition for record players and tape recorders with output powers up to 10 W.
Special features are:
• single in-line (SI L) construction for easy mounting
• separated preamplifier and power amplifier
• high output power
• low-cost external components
• good ripple rejection
• thermal protection
qUICK REFERENCE DATA
Supply voltage range
Output power at pin 2; d tot
Vp = 14,4 V; RL = 2 n
Vp = 14,4 V; R L = 4 n
Vp = 14,4 V; R L = 8 n
Total harmonic distortion at Po
= 1 W;
Input impedance
preamplifier (pin 8)
power amplifier (pin 6)
Total quiescent current at Vp
= 5,8 W;
IORM
max.
Po
Po
Po
typo
typo
typo
3 A
= 10%
Vp = 14,4 V; R L = 2 n; with additional
bootstrap resistor of 220 n between pins 3 and 4
Sensitivity for Po
6 to 24 V
Vp
Repetitive peak output current
RL
= 14,4 V
=4 n
Operating ambient temperature
Storage temperature
RL = 4 n
6,4 W
6,2 W
3,4 W
Po
typo
9W
dtot
typo
0,2 %
I Zi I
I Zi I
typo
typo
30 kn
20 kn
Itot
V·I
typo
31 mA
typo
10 mV
Tamb
T stg
-25 to + 150 °C
-55 to + 150 °C
PACKAGE OUTLINE
9-lead SI L; plastic (SOT110B).
1(
November 1982
811
co
....
N
-I
0
».....
Z
<
CD
0
~
,.
•
3
CJ'"
....CO~
50
TR9
CO
'
N
RlO
R1
9
,
TR8
R11
o. .'
Fig. 1 Circuit dia(:lram.
~D~Q
03
04
0.....
0
»
l____
6 W audio power amplifier in car applications
10 W audio power amplifier in mains-fed applications
TD_A_1_0_10_A______
RATINGS
Limiting values in accordance with the Absolute Maximum System (lEC 134)
Supply voltage
Vp
max.
24 V
Peak output current
max.
5 A
Repetitive peak output current
max.
3 A
Total power dissipation
see derating curve Fig. 2
Storage temperature
T stg
-55 to + 150 °C
Operating ambient temperature
Tamb
-25 to + 150 °C
A.C. short-circuit duration of load
during sine-wave drive;
without heatsink at Vp = 14,4 V
max.
100 hours
7Z764193
10
Ptot
\
(W)
\
6
\
~
~
4
1\
\
o
-25
0
50
100
\
150
Fig. 2 Power derating curve.
HEATSINK DESIGN
Assume Vp = 14,4 V; RL = 2 n; Tamb = 60 oC maximum; thermal shut-down starts at Tj = 150 0C.
The maximum sine-wave dissipation in a 2 n load is about 5,2 W. The maximum dissipation for music
drive will be about 75% of the worst-case sine-wave dissipation, so this will be 3,9 W. Consequently, the
total resistance from junction to ambient
Rth j-a
= Rth j-tab + Rth tab-h + Rth h-a =
Since Rth j-tab
Rth h-a
= 10
KIW and Rth tab-h
150 - 60
3,9 = 23 KIW.
= 1 KIW,
= 23 - (10 + 1) = 12 KIW.
1
(November 1982
813
___TD_A10_10A~jl~_________________
D.C. CHARACTERISTICS
Supply voltage range
6 to 24 V
Vp
Repetitive peak output current
IORM
<
Total quiescent current at Vp = 14,4 V
Itot
typo
3 A
31 mA
A.C. CHARACTERISTICS
Tamb = 25 oC; Vp = 14,4 V; RL = 4 n; f = 1 kHz unless otherwise specified; see also Fig. 3.
A.F. output power (see Fig. 4) at dtot = 10%;
measured at pin 2; with bootstrap
Vp = 14,4 V; RL = 2 n (note 1)
Po
typo
6,4 W
Vp = 14,4 V; RL =4 n (note 1 and 2)
Po
{~P.
5,9 W
6,2 W
Vp = 14,4 V; RL = 8 n (note 1)
Po
typo
3,4 W
Vp = 14,4 V; R L = 4 n; without bootstrap
Po
typo
5,7 W
Vp = 14,4 V; R L = 2 n; with additional bootstrap
resistor of 220 n between pins 3 and 4
Po
typo
9 W
Gv 1
typo
24 dB
21 to 27 dB
power amplifier
Gv2
typo
30 dB
27 to 33 dB
total amplifier
Gvtot
typo
54 dB
51 to 57 dB
Total harmonic distortion at Po = 1 W
dtot
typo
0,2 %
Efficiency at Po = 6 W
fl
typo
75 %
Frequency response (-3 dB)
B
80 Hz to 15 kHz
IZi I
typo
30 kn
20 to 40 kn
I Zi I
typo
20 kn
14 to 26 kn
IZol
typo
20 kn
14 to 26 kn
Voltage gain
preamplifier (note 3)
Input impedance
preamplifier (note 4)
power amplifier (note 5)
Output impedance of preamplifier; pin 7 (note 5)
Output voltage preamplifier (r.m.s. value)
dtot < 1% (pin 7) (note 3)
Vo(rms)
>
0,7 V
Noise output voltage (r.m.s. value; note 6)
RS=On
Vn(rms)
typo
0,3 mV
typo
0,7 mV
1,4 mV
RS = 8,2 kn
814
Vn(rms)
Ripple rejection at f = 1 kHz to 10 kHz (note 7)
at f = 100 Hz; C2 = 1 J..LF
RR
RR
<
>
>
Sensitivity for Po = 5,8 W
Vi
typo
10 mV
Bootstrap current at onset of clipping; pin 4 (r.m.s. value)
14(rms)
typo
30 mA
November
19821 (
42 dB
37 dB
TDA1010A
6 W audio power amplifier in car applications
10 W audio power amplifier in mains-fed applications
Notes
1. Measured with an ideal coupling capacitor to the speaker load.
2. Up to Po ~ 3 W : dtot ~ 1%.
3. Measured with a load impedance of 20 kf2.
4. Independent of load impedance of preamplifier.
5. Output impedance of preamplifier
Zd ) of the power amplifier.
(I
(I Zol) is correlated (within 10%) with the input impedance
6. Unweighted r.m.S. noise voltage measured at a bandwidth of 60 Hz to 15 kHz (12 dB/octave).
7. Ripple rejection measured with a source impedance between 0 and 2 kf2 (maximum ripple amplitude:
2 V).
8. The tab must be electrically floating or connected to the substrate (pin 9).
ripple
voltage
meter
C5
100nF
t----o+
3
2
+
1000 J.lF
C8
C6
Vp
100 nF
V·I
j
9
7
RL
6
R2
4,7 n
4n
C4
1 nF
7Z76418.2
Fig. 3 Test circuit.
'I (
November 1982
815
___T_DA_1010_A_Jl~_________________
7Z77909.A
15
Po
(W)
R =2n(1)
L
." "-
1\ ;.;
10
"\
i/~
I
1/
/
/
V
V
5
;'""
/
/
IIA " ; '
~
....'"
v
~I""
LI/'
~i"""
t.;:::f"'"
~i"""
~;:::::r--'
5
I
I
I~~
- ; F-"'r"
~~
o
" RL =sn
~'"
;,...'
::A
~~ I~:""-
~
.............
I
",,~
V'
.....
-R L =2n
~-
"',~~
~t/
rr~
' J / ~"'V
/~ ....:: ~
~
~.., ~.
1//
"" /. r
I
/
I/V
vI"" / "V
/
~V
~V
I
o
V RL =4n
1//
....
10
I
I
I
I
15
Vp(V)
20
14,4
Fig.4 Output power of the circuit of Fig. 3 as a function of the supply voltage with the load impedance
as a parameter; typical values. Solid lines indicate the power across the load, dashed lines that available
at pin 2 of the TDA 1010. R L = 2 n (1) has been measured with an additioncli 220 n bootstrap resistor
between pins 3 and 4. Measurements were made at f = 1 kHz, d tot = 10%, T amb = 25 °C.
Fig. 5 See next page.
Total harmonic distortion in the circuit of Fig. 3 as a function of the output power with the load
impedance as a parameter; typical values. Solid lines indicate the power across the load, dashed lines
that available at pin 2 of the TDA1010. RL = 2 n (1) has been measured with an additional 220 n
bootstrap resistor between pins 3 and 4. Measurements were made at f = 1 kHz, Vp = 14,4 V.
816
November
19821 (
l____
6 W audio power amplifier in car applications
10 W audio power amplifier in mains-fed applications
T_D_A_10_10_A______
7Z77910
10
!
, ,!
I
!
,
,
,
,
I
I
d tot
(%)
7,5
fT
['
,
I
RL =8n
5
I j'
I
I, J I
"
I
I
J I'
I
r-r' ~'2n(1)
r::: J I
I' 2~i
I' 4 n.. f\
,
2,5
:
:'
,I
,
,
Iii
Jf
~/
I
~/
1//
R.
~ V/
~
o
10- 1
10
Po (W)
Fig. 5 For caption see preceding page.
7Z77912
Po
(dB)
o
~
R L=
~~
2n r-..I
4n r-..
an r--
-2,5
ffl
rt-I
1/
II
I
I
~
-
i"-",
"" .....
~
r\
\
1
--5
10
f (Hz)
Fig.6 Frequency characteristics of the circuit of Fig. 3 for three values of load impedance; typical
values. Po relative to 0 dB = 1 W; Vp = 14,4 V.
' ] (November 1982
817
___TD_A1_010_A_jl~_________________
7Z77914
6
17
...
Ptot
~~Ioo"
(W)
(%)
RL =2n
"'"'1-- 100
I--"
i-""
i,..-'
V
4
1; ....
..
~
L.....I ...
1.01 ...
,
~~""'"
~
;
2
r
I,~
I....
1-1 .... 4n
~Iii'"
~
.
80
8n
I..-
:<"
--
....
.. ~
'-
~J
.-.............
100 ......
..........
•. -'- - ..
2n_
~
60
40
4n
I......
..~
..... ~
1... :--
8n
20
o
o
2
4
6
Po (W)
8
o
Fig. 7 Total power dissipation (solid lines) and the efficiency (dashed lines) of the circuit of Fig. 3 as
a function of the output power with the load impedance as a parameter (for R L = 2 n an external
bootstrap resistor of 220 n has been used); typical values. Vp = 14,4 V; f = 1 kHz.
818
November
19821 (
TDA1010A
6 W audio power amplifier in car applications
10 W audio power amplifier in mains-fed applications
7Z77915
30
R th h-a
(oC/W)
20
I"-
"
.....
......'"
...... r-..,
" ...." r-r--r-. ....
t"--too..
10
--"""""",
r-i"'-
r-"""I-o.
Ptot =
r-r--t-
r-I-
~
2W
I-
t-f-
5W f-I-
o
o
25
50
75
100
heatsink area (em 2)
Fig. 8 Thermal resistance from heatsink to ambient of a 1,5 mm thick bri~ht aluminium heatsink as a
function of the single-sided area of the heatsink with the total power dissipation as a parameter.
1
(November 1982
819
00
I\,)
o
z
--I
CJ
APPLICATION INFORMATION
»......
o
o......
<
CD
o
3
»
C'"
~
c5II
c2I
co
00
I\,)
+l
100n F
100 nF
3
C10
27 nF
0+
C7
100pF
~J2
-:l
V·I
9
C11
180 nF
7
I,
16
C4
1 nF
~1000pF
T
100 nF
R2
4,7 n
n n
IRL
7Z77941.1
~
Fig. 9 Complete mono audio amplifier of a car radio.
I
Vp
~
6 W audio power amplifier in car applications
10 W audio power amplifier in mains-fed applications
____T_D_A_10_10_A______
TDA1010A
7Z77931
Fig. 10 Track side of printed-circuit board used for the
circuit of Fig. 9; p.c. board dimensions 92 mm x 52 mm.
output
Cl0
:::;::.
:::~:::
. .,
:R"4~J
7Z77932.1
Fig. 11 Component side of printed-circuit board
showing component layout used for the circuit of Fig. 9.
1(
November 1982
821
l
I
00
N
N
-I
~
z0
C2!
220nF
to a
5
<
CD
3
0-
0
(0
r
~
ex>
N
J
I
lCg
-r-27nF
WQ,.8
50k.s1n
,h,nn,'
"ftInput
I
100
k.s1
__ li::>n
I
I
I
I
I
I
I
R6
1
I
I
l
i
k.s1
R1 150k.s1
--10.
+
HI
I ",... ... r n ...............
..............
I
+.
I?
+
6
I,
16
luuu J,lr
T
I .A'"
__ n n
I'
I
Vp
IRL
I
I
I
I
Ivolume
I
I
I
I
1
a~5
C105
220 nF
I
0+
h
"t
TDA1010A
C107
100jJF
2
nR~~
C106
100nF
7
16
R102~
n
IRL
4,H1
C104
1 nF
~
Fig. 12 Complete stereo car radio amplifier.
0--10.
0
»
C7
100J,lF
TDA1010A
C10
180nF
I 11
balance I tone
I
1
right channel
input
0
»
c5I
220nF
7Z77942.1
....&0)
right channel
output
left channel
output
c~
:EO)
0)
C
c 2:
2:0
7Z77934.1
R :~!::
~
':;:::
0-c
"C 0
~CD ...~
...
0)
0)
3
3-c
"C::
::::n
::n~
_.
~
_. :::J
g
3 ...
:::J
0)
0)
_. "C
i;!"C
.:..::
~g
0)
"C
"'2..
g.
:::J
!.It
[
o·
:::J
!.It
7 Z77933
zo
<
en
3
--I
0-
~
......
co
co
I'V
co
I'V
Co\)
Fig. 13 Track side of printed-circuit board
used for the circuit of Fig. 12; p.c. board
dimensions 83 mm x 65 mm.
Fig. 14 Component side of printed-circuit board
showing component layout used for the circuit of Fig. 12.
Balance control is not on the p.c. board.
o
»
-.io.
o
o
-.io.
»
___T_DA1_010_A_Jl__________________
7Z7 7922
100
channel
separation
(dB)
75
-....
50
typ
25
a
10
f (Hz)
Fig. 15 Channel separation of the circuit of Fig. 12 as a function of the frequency.
01 BY226
..-+---..------..------+ A
.--.....,~
unloaded: + 21 V
loaded: + 17 V
R13
02
BY226
'" (220 V)
+C18
68J..LF
7Z77937
'/
Fig. 16 Power supply of circuit of Fig. 17.
824
November
19821 (
-'0)
o~
:lEO)
0) s::::
s:::: c.
c.
_.
_. 0
0"C
"C 0
°:Een
right channel
input
...
0)
:Een
...
0)
3
3"C
"C:::
§i~
...en ..._.
2
_. :::l
RL
:::l
S
2!.
0)
3 ...
:::l"C
III"C
~=
I
Itreble
I
I
~s
!:!".
"C 0
0)
balance
_
"C
III
:::l
~.
I
I
I
r+
o·
:::l
III
left channel
input
RL
z
o
<
en
3
--I
0"
~
co
ex>
!IV
Fig. 17 Complete mains-fed ceramic stereo pick-up ampl ifier; for power supply see Fig. 16.
o
»
-..10.
o
o
-..10.
00
!IV
C11
»
Jl____________________________________
______T_D_A1_0_10_A___
TDA1010A
m
OJ
r
m
Fig. 18 Track side of printed-circuit board used for the circuit
of Fig. 17 (Fig. 16 partly); p.c. board dimensions 169 mm x 118 mm.
826
November
19821 (
7Z77935
l____
6 W audio power amplifier in car applications
T_D_A1_0_10_A______
10 W audio power amplifier in mains-fed applications
left channel
output
right channel
input
left channel
input
right channel
output
7Z77936
Fig. 19 Component side of printed-circuit board showing
component layout used for the circuit of Fig. 17 (Fig. 16 partly).
1
(November 1982
827
Jl_____________________________________
______T_D_A_1_01_0_A___
7Z77926
100
channel
separation
(dB)
75
7
50
~
I.,.oo'~
7
I----typ
~
............
..... r-..~
.. ~ i"---.....
/
25
o
10
f (Hz)
Fig. 20 Channel separation of the circuit of Fig. 17 as a function of frequency.
828
November
19821 (
TDA1011
2 TO 6 W AUDIO POWER AMPLIFIER
The TDA 1011 is a monolithic integrated audio amplifier circuit in a 9-lead single in-line (SI L) plastic
package. The device is especially designed for portable radio and recorder applications and delivers up
to 4 W in a 4 n load impedance. The device can deliver up to 6 W into 4 n at 16 V loaded supply in
mains-fed applications. The maximum permissible supply voltage of 24 V makes this circuit very suitable
for d.c. and a.c. apparatus, while the very low applicable supply voltage of 3,6 V permits 6 V applications.
Special features are:
• single in-line (SI L) construction for easy mounting
• separated preamplifier and power amplifier
• high output power
• thermal protection
• high input impedance
• low current drain
• limited noise behaviour at radio frequencies
QUICK REFERENCE DATA
Supply voltage range
Vp
Peak output cu rrent
10M
max.
Output power at dtot = 10%
Vp=16V;RL=4n
Vp= 12 V; RL =4n
Vp= 9V;RL=4n
Vp = 6 V; RL = 4 n
Po
Po
Po
Po
typo
typo
typo
typo
6,5
4,2
2,3
1,0
Total harmonic distortion at Po = 1 W; R L = 4 n
dtot
typo
0,2 %
>
typo
100 kn
20 kn
14 rnA
Input impedance
preamplifier (pin 8)
power amplifier (pin 6)
I Zi!
I Zil
3,6 to 20 V
3 A
W
W
W
W
Total quiescent current
Itot
typo
Operating ambient temperature
Tamb
T stg
-25 to + 150 °C
-55 to + 150 oC
Storage temperature
PACKAGE OUTLINE
9-lead SI L; plastic (SOT110B).
I(
November 1982
829
00
w
0
-of
0
CD)
::J
c:
D)
so---Jf.l
-<
co
-...J
co
f
1
1
Rl
90
I
8
Fig. 1 Circuit diagram.
I
111
~RDI 0:
~
......I.
0......I.
......I.
l_____
2 to 6 W audio power amplifier
TD_A_1_0_11______
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Vp
Supply voltage
Peak output current
max.
24 V
max.
3 A
Total power dissipation
see derating curve Fig. 2
Storage temperature
T stg
-55 to + 150 oC
Operating ambient temperature
Tamb
-25 to + 150 oC
A.C. short-circuit duration of load
during sine-wave drive; Vp :;: 12 V
max.
100 hours
7Z786282
7,5
Ptot
,
(W)
1\
5
~
infinite
heatsink
,
~
~
1-0 .....
I""""- ~
2,5
.......
r-....
....... ~heatsink
I""""- ......
o
-25
,
~
without
,
~
.............
....... """ r" ~
~
o
+50
+100
Fig. 2 Power derating curve.
HEATSINK DESIGN
Assume Vp:;: 12 V; RL :;: 4 [2; Tamb
= 60 oC maximum; Po = 3,8 W.
The maximum sine-wave dissipation is 1,8 W.
The derating of 10 K!W of the package requires the following external heatsink (for sine-wave drive):
Rth j-a
150 -60
= Rth j-tab + Rth tab-h + Rth h-a = 1T
Since Rth j-tab
= 10 K/Wand
Rth tab-h
= 1 K/W,
:;: 50 K!W.
Rth h-a
= 50- (10 + 1) = 39 K!W.
1
(November 1982
831
jl~_________________
_ _ _T_DA_1011_ _
D.C. CHARACTERISTICS
Supply voltage range
Vp
Repetitive peak output current
IORM
3,6 to 20 V
<
typo
Total quiescent current at Vp = 12 V
<
2 A
14 mA
22 mA
A.C. CHARACTERISTICS
Tamb = 25 oC; Vp = 12 V; RL = 4 n; f = 1 kHz unless otherwise specified; see also Fig. 3.
A. F. output power at d tot =10% (note 1)
wi th bootstrap:
Vp = 16 V; RL = 4 n
Vp=12V;RL=4n
typo
6,5 W
Po
>
typo
3,6 W
4,2 W
Vp= 9V;RL=4n
Po
typo
2,3 W
Vp = 6V;RL=4n
Po
typo
1,0 W
without bootstrap:
Vp=12V;RL=4n
Po
typo
3,0 W
Gv 1
typo
23 dB
21 to 25 dB
power amplifier
Gv2
typo
29 dB
27 to 31 dB
total amplifier
Gvtot
typo
52 dB
50 to 54 dB
Total harmonic distortion at Po = 1,5 W
dtot
<
Frequency response; -3 dB (note 3)
B
60 Hz to 15 kHz
Voltage gain:
preamplifier (note 2)
Input impedance:
preamplifier (note 4)
power amplifier
Output impedance preamplifier
typo
>
0,3 %
1 %
typo
100 kn
200 kn
I Zi21
typo
20 kn
I Zo11
typo
1 kn
I Zi11
Output voltage preamplifier (r.m.s. value)
dtot < 1% (note 2)
Vo(rms)
Noise output voltage (r.m.s. value; note 5)
RS = on
Vn(rms)
RS=10kn
832
Po
>
0,7 V
typo
0,2 mV
typo
0,6 mV
1,4 mV
Vn(rms)
<
Noise output voltage at f = 500 kHz (r.m.s. value)
B = 5 kHz; RS = 0 n
Vn(rms)
typo
8 J.1V
Ripple rejection (note 6)
f= 1 to 10kHz
f = 100 Hz; C2 = 1 J.1F
RR
RR
typo
>
42 dB
35 dB
Bootstrap current at onset of clipping; pin 4 (r.m.s. value)
14(rms)
typo
35 mA
November
19821 (
~~
_________
2_to_6_w
__
au_d_io_p_ow_e_r_am_p_lif_ie_r_______________________
T_D_A
__10_1_1________
_____
Notes
1. Measured with an ideal coupling capacitor to the speaker load.
2. Measured with a load resistor of 20 k,Q.
3. Measured at Po = 1 W; the frequency response is mainly determined by C1 and C3 for the low
frequencies and by C4 for the high frequencies.
4. Independent of load impedance of preamplifier.
5. Unweighted r.m.s. noise voltage measured at a bandwidth of 60 Hz to 15 kHz (12 dB/octave).
6. Ripple rejection measured with a source impedance between 0 and 2 k,Q (maximum ripple
amplitude: 2 V).
7. The tab must be electrically floating or connected to the substrate (pin 9).
c6I
C2!
100nF
I----......()
+
3
~ J-1---=8=-1----1
r
Vi
2
100 nF
+
C8
100 nF
9
7
Vp
RL
6
4,Q
R2
4,7 ,Q
j
7Z74905.2
I
I
Fig. 3 Test circuit.
1
(November 1982
833
jl~________________
_ _ _T_DA_1011_ _
APPLICATION INFORMATION
~----~----------~--------~-------o+
3
2
Vp
C8
100 nF
V-I
I
RL
C3
100pF
7
9
C4
100
nF
5,6kn
6
R3
4,7n
4n
1,8 nF
C5
7274906.2
Fig. 4 Circuit diagram of a 4 W amplifier.
7278629 1
40
I tot
(rnA)
20
typ
~~
i",...oo" ~
-
,.,,-.-.- ,.,,--
~~
--
i",...oo" ~
..
..",. ~
~
o
o
10
20
Vp(V)
Fig. 5 Total quiescent current as a function of supply voltage.
834
November
19791 (
30
~~
_________2_to_6_w
__
au_d_io_p_ow_e_r_am_p_li_fie_r_______________________
_____T_D
__A_1__
011________
TDA1011
~~~t~::::::~:f~~~
1
o
c:
7Z79431
Fig. 6 Track side of printed-circuit board used for the circuit of Fig. 4;
p.c. board dimensions 62 mm x 48 mm.
output
7Z79432.1
Fig. 7 Component side of printed-circuit board showing component layout used for the circuit of Fig. 4.
'I (
November 1979
835
jl~_________________
_ _ _T_DA_1011_ _
10
9V
Vp= 6V
7Z78631.1
II
~
12V 14V 16V
1\/\/1
I
~
!
d tot
I ,
I I
"
(%)
I
,
7,5
I
I
I
I
5
.'
-
10- 1
--,
--
~17
I
I
I
:
I
1
II
I
I
I
,
:
11
1
I
,
I
I
~
a10- 2
I
I
I
i
I
, !I
, II
, II
,
I
I
I
I
/
IT
j
j
2,5
I'
I
I II
Ij
I
/JI//
I
J
~~v
7/ .....
~
~:~---
1,..'
10
Fig.8 Total harmonic distortion as a function of output power across R L; with bootstrap;
- - - without bootstrap; f = 1 kHz; typical values. The available output power is 5% higher when
measured at pin 2 (due to series resistance of C10).
7Z78630 1
I I I I I
I I I I
RL
Y
j
Van
I7
= 4 nil
Ii
5
17
I)
V
I)
1/
D
f7
1.1
I ....
....
1.1
V
v
2,5
D
V
1.1
1/
V
V
1;1'
1;1'
L....
~
~
~
"
~
L.,..
L,..;~
10""
"""io""
5
L,..;
L.,..o
L.,..ol"
"'"
10
15
Vp (V)
20
Fig. 9 Output power across RL as a function of supply voltage with bootstrap; d tot = 10%; typical
values. The available output power is 5% higher when measured at pin 2 (due to series resistance of C10).
836
January
19791 (
j
2 to 6 W audio power amplifier
TDA1011
- - - 7278637 1
10
Po
(dB)
typ
o
" . I-
- ....
./'
.....
""L\.
\
1/
1/
-10
,
1\
1\
/
~
I(
\
-20
10
f (Hz)
Fig. 10 Voltage gain as a function of frequency; Po relative to 0 dB
= 1 W; Vp = 12 V; RL = 4 n.
7278636 1
10
d tot
(%)
7,5
5
2,5
\
1\
/
1',
o
~
typ
/
_I-'"
10
f (Hz)
Fig. 11 Total harmonic distortion as a function of frequency; Po = 1 W; Vp
= 12 V; RL = 4 n.
'I~-J-an-u-a-ry-1-9-79-------83-7-----
__-T-DA-1011--Jl-_________________
7Z78635 1
60
RR
'-
(dB)
--
I--f 1 kHz
40
I--
1--100 Hz
-
~~
i.- ~I"'"
....
.--- ....-
-----
20
o
1
R2 (kn)
10
Fig. 12 Ripple rejection as a function of R2 (see Fig. 4); RS
= 0; typical values.
7Z78633 1
600
to--
---
............... RS = 8,2 kn
.............
r-.........
[""....
"'400
'"
""" ~.........
..........
~
~
i""..
..........
...... ~
200
o
-
---
.............
RS = 0
1
to--
r - r-
---
10
""""""
........
"'"
......
R2 (kn)
Fig. 13 Noise output voltage as a function of R2 (see Fig. 4); measured according to A-curve; capacitor
C5 is adapted for obtaining a constant bandwidth.
838
January 1979
J(
~~-
_________
2_to_6_w__
au_d_io_po_w_e_ra_m_p_lif_ie_r_______________________
____T_D
__A_10__11________
7Z786321
" "",a
~ """'" '"
Vn(rms)
....
(j.1V)
"
"'~
"'~
'"
10
~
~
"'
""'"
""
i""I
"
"-
'\
1
10- 2
'"
1\
10- 1
f (MHz)
10
Fig. 14 Noise output voltage as a function of frequency; curve a: total amplifier; curve b: power
amplifier; B = 5 kHz; RS = 0; typical values.
7Z786341
60
Gv
(dB)
--- --- --
--
typ
40
to-..
f""""""-.t...
r- .....
r-
20
o
1
10
R2 (kn)
Fig. 15 Voltage gain as a function of R2 (see Fig. 4).
'I (January
1979
839
__________________jl__
TD_A10_13B_ __
4 W AUDIO POWER AMPLIFIER WITH DC VOLUME CONTROL
GENERAL DESCRIPTION
The TDA 1013B is an integrated audio amplifier circuit with DC volume control, encapsulated in a
9-lead single in-line (SI L) plastic package. The wide supply voltage range makes this circuit ideal for
applications in mains and battery-fed apparatus such as television receivers and record players.
The DC volume control stage has a logarithmic control characteristic with a range of more than 80 dB;
control is by means of a DC voltage variable between 2 and 6.5 V.
The audio amplifier has a well defined open loop gain and a fixed integrated closed loop. This device
requires only a few external components and offers stability and performance.
Features
•
•
•
•
Few external components
Wide supply voltage range
Wide control range
Pin compatible with TDA 1013A
• Fixed gain
• High signal-to-noise ratio
• Thermal protection
QUICK REFERENCE DATA
parameter
min.
typo
max.
unit
10
18
40
V
IORM
-
-
1.5
A
V·I
44
55
69
mV
Po
THD
4.0
4.2
-
W
-
0.15
0.1
%
Vi
100
125
160
mV
Ib.Gvl
80
-
-
dB
THD < 1%;
DC control = 0 dB
V·I
1.2
1.7
-
V
Vo = 125 mV;
max. voltage gain
Vi
39
45
55
mV
IZil
23
29
35
kn
conditions
Supply voltage
Vp
1
I
Repetitive peak output
current
Total sensitivity
symbol
Po =2.5W;
DC control at max. gain
Audio amplifier
Output power
Total harmonic distortion
Sensitivity
THD = 10%; RL = 8 n
Po =2.5W;RL=8n
Po = 2.5W
DC volume control unit
Gain control range
Signal handling
Sensitivity (pin 6)
I nput impedance (pin 8)
:
PACKAGE OUTLINE
9-lead SI L; plastic (SOT110B).
"I (June
1989
841
jl____________________________________
______
TD_A_1_01_3_B___
7
6
4
3
TDA1013B
-(
2
-(
input reference
voltage B
7Z21638.1
Fig.1 Block diagram.
PINNING
842
1
signal ground
2
ampl ifier output
3
supply voltage
4
5
electronic filter
6
control unit output
7
control voltage
8
9
control unit input
amplifier input
power grou nd
June
19891 (
l___
4 W audio power amplifier with DC volume control
T_D_A_1_01_3_B______
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
max.
parameter
symbol
min.
unit
Supply voltage
Vp
-
40
V
Non-repetitive peak output current
IOSM
-
3
A
Repetitive peak output current
IORM
-
1.5
A
Storage temperature range
T stg
-65
+ 150
°C
Crystal temperature
Tc
-
+ 150
°C
Total power dissipation
Ptot
see Fig. 2
I
7Z21647
20
Ptot
(W)
15
'\
i'-..
'\r\.
"',
10
r--
-
o
-25
'"
-- -- -- --'\ ~
50
100
150
Tamb (0C)
- - - - infinite heatsink
without heatsink
Fig.2 Power derating curve.
HEATSINK DESIGN EXAMPLE
Assume Vp = 18 V; RL = 8 [2; T amb = 60 oC; Tc = 150 °C (max.); for a 4 W application, the maximum
dissipation is approximately 2.5 W. The thermal resistance from junction to ambient can be expressed
as:
Rth j-a
= Rth j-tab + Rth tab-h + Rth
h-a
=
T~J,-·m--.:c..ax-=--_T-ca:.:-m-cb.c-m-'..a_x = 150 - 60 = 36 K/W
Pmax
Since Rth j-tab
2.5
= 9 K/W and
Rth tab-h
= 1 K/W,
Rth h-a
= 36 -
(9 + 1)
= 26
K/W.
1(June
1989
843
Jl____________________________________
______T_D_A1_0_13_B___
CHARACTE R ISTICS
Vp
= 18 V;
R L = 8 U; f
= 1 kHz; T amb = 25 oC; see Fig.l0; unless otherwise specified
parameter
conditions
symbol
typo
min.
max.
unit
Supply voltage range
Vp
10
18
40
V
Total quiescent current
I tot
-
25
60
mA
Vn
0.5
-
mV
0.6
1.4
mV
0.25
-
mV
55
69
mV
Noise output voltage
note 1
at maximum gain
RS = OU
at maximum gain
RS
at minimum gain
RS=OU
Vn
-
Po = 2.5 W;
OC control at max. gain
Vi
44
Total sensitivity
= 5 kU
Vn
I
Audio amplifier
Repetitive peak output
current
= 10%; R L = 8 U
Output power
THO
Total harmonic distortion
Po =2.5W;RL=8U
Po = 2.5 W
Sensitivity
I nput impedance (pin 5)
Power bandwidth
IORM
-
-
1.5
A
Po
4.0
4.2
-
W
THO
-
0.15
1.0
%
Vi
100
125
160
mV
IZil
Bp
100
200
500
kU
-
30 to
40000
-
Hz
DC volume control unit
IllGvl
80
90
-
dB
THO < 1%;
OC control = 0 dB
V·I
1.2
1.7
-
V
Vo = 125 mV;
max. voltage gain
Gain control range
Signal handling
Sensitivity (pin 6)
V·I
39
44
55
mV
I nput impedance (pin 8)
IZil
23
29
35
kU
Output impedance (pin 6)
IZol
45
60
75
U
Note to the characteristics
1. Measured in a bandwidth in accordance with IEC 179, curve 'A'.
844
June
1989\ (
~
4 W audio power amplifier with DC volume control
____
TD_A_1_0_13_B______
APPLICATION INFORMATION
7Z21640 1
)
12
16'0.7
an)
/
1/
11
7250.1
II
/
I
r7 7
I J /
RL = 4 0.1
II 1/ V
II J / '7
V/' ~
I
4
o
I
V
II
~
o
10
20
30
40
F ig.3 Output power as a function of supply voltage; f
THD = 10% and control voltage (V7) = 6.5 V.
= 1 kHz;
7Z21641
3
/
.. v
V
-I--
r-....
II~
o
o
3
4
FigA Power dissipation as a function of output power; Vp
f = 1 kHz; RL = 8 n and control voltage (V7) = 6.5 V.
= 18 V;
1(June
1989
845
jl____________________________________
______
TD_A_1_01_3_B___
APPLICATION INFORMATION (continued)
7Z21642
5
v
\
II
3
~
\
II
II
l\
J
V
o
10
f (Hz)
Fig.5 Power bandwidth; Vp = 18 V; RL = 8 Q;
THD = 10% and control voltage (V7) = 6.5 V.
7Z21643
~
\\
THO
(%)
I
f
\
\
/
1/
1\
II
o
10
'"
...........
-
~
~I"""
f(Hz)
Fig.6 Total harmonic distortion as a function of frequency;
Vp = 18 V; RL = 8 Q; Po = 2.5 Wand control voltage = 6.5 V.
846
June
19891 (
l____
4 W audio power amplifier with DC volume control
TD_A_1_0_13_B______
lZ27644
10~--~~~~~--~~~~~
THO
(%)
Po(W)
- - - - - - 10 kHz
1 kHz
F ig.7 Total harmonic distortion as a function of output power;
Vp = 18 V; R L = 8 n and control voltage = 6.5 V.
lZ27645
6
\
4
./
""
/y
"'~
i'-...
V""
..............
,,/
~ ......
..............
2
o
10
0
-20
-40
-60
i'-...
-80
/
./
-0.6
./
-0.4
-0.2
gain control (dB)
o
0.2
'7 (mA)
Fig.8 Typical control curve.
I (June
1989
847
~l___________________________________
______T_DA_1_0_13_B___
APPLICATION INFORMATION (continued)
7Z21646
0.6
{\
II \
'\
0.4
/
0.2
-
-"
\
V
o
o
Fig.9 Noise output voltage as a function of the control voltage; Vp
R L = 8 n (in accordance with I EC 179, curve 'A').
= 18 V;
0.1 IlF
~----~----~,~+-----vp
$
, .
~
470 IlF
(1)
0.221lF
VI -11--f-----I
TDA1013B
7Z21639.1
(1) Belongs to power supply circuitry.
Fig.10 Application diagram.
848
June
19891 (
_______jl__
TDA_1015---1
1 TO 4 W AUDIO POWER AMPLIFIER
The TDA 1015 is a monolithic integrated audio amplifier circuit in a 9-lead single in-line (SI L) plastic
package. The device is especially designed for portable radio and recorder applications and delivers up
to 4 W in a 4 Q load impedance. The very low applicable supply voltage of 3,6 V permits 6 V applications.
Special features are:
• single in-line (SI L) construction for easy mounting
• separated preamplifier and power amplifier
• high output power
• thermal protection
• high input impedance
• low current drain
• limited noise behaviour at radio frequencies
QUICK REFERENCE DATA
Supply voltage range
Vp
Peak output cu rrent
10M
max.
2,5 A
Output
Vp=
Vp=
Vp=
Po
Po
Po
typo
typo
typo
4,2 W
2,3 W
1,0 W
dtot
typo
0,3 %
>
typo
100 kQ
20 kQ
14 mA
power at d tot = 10%
12 V; RL =4Q
9V;RL=4Q
6V;RL=4Q
Total harmonic distortion at Po = 1 W; RL = 4 Q
Input impedance
preamplifier (pin 8)
power amplifier (pin 6)
3,6 to 18 V
Izd
IZii
Total quiescent current
Itot
typo
Operating ambient temperature
Tamb
T stg
-55 to + 150 °C
Storage temperature
-25 to + 150 °C
PACKAGE OUTLINE
9-lead SI L; plastic (SOT 110B).
1
(November 1982
849
co
en
0
--I
0
»
z
0
~
<
CD
3
C'"
r
r-"1
~
CO
ex>
rv
Rl
90
,
8
6
Fig. 1 Circuit diagram.
I
~R33
04
0
~
01
l____
1 to 4 W audio power amplifier
T_D_A_10_1_5______
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage
Vp
Peak output current
max.
18 V
max.
2,5 A
Total power dissipation
10M
see derating curve Fig. 2
Storage temperature
T stg
-55 to + 150 0C
Operating ambient temperature
Tamb
-25 to + 150 °C
A.C. short-circuit duration of load
during sine-wave drive; Vp = 12 V
max.
7,5
Ptot
,
(W)
~
5
~
,
""'""",-
~
..... ~
,
o
,
~
without
f': 100... heatsink
""
-25
infinite
heatsink
~
"-
2,5
o
100 hours
7Z78628 2
~
+50
!"'"iii
~
~ .....
+100
~
~
~
" j...l
Fig. 2 Power derating curve.
HEATSINK DESIGN
Assume Vp = 12 V; RL = 4 !1;Tam b = 45 0C maximum.
The maximum sine-wave dissipation is 1,8 W.
Rth j-a
150 -45
= Rth j-tab + Rth tab-h + Rth h-a = ~ = 58
KIW.
Where Rth j-a of the package is 45 KIW, so no external heatsink is required.
I
(November 1982
851
___T_DA_101_5_jl~________________
D.C. CHARACTER ISTICS
Supply voltage range
Vp
Repetitive peak output current
IORM
3,6 to 18 V
<
typo
Total quiescent current at Vp = 12 V
<
2 A
14 mA
25 mA
A.C. CHARACTERISTICS
Tamb = 25 oC; Vp = 12 V; R L = 4 n; f = 1 kHz unless otherwise specified; see also Fig. 3.
A.F. output power at d tot = 10% (note 1)
with bootstrap:
Vp = 12 V; RL = 4 n
Po
typo
4,2 W
Vp = 9V;RL=4n
Po
typo
2,3 W
Vp= 6V;RL=4n
Po
typo
1,0 W
without bootstrap:
Vp=12V;RL=4n
Po
typo
3,0 W
Voltage gain:
preamplifier (note 2)
Gv 1
typo
23 dB
power amplifier
Gv2
typo
29 dB
total amplifier
Gvtot
typo
52 dB
49 to 55 dB
Total harmonic distortion at Po = 1,5 W
dtot
Frequency response; -3 dB (note 3)
B
Input impedance:
preamplifier (note 4)
power amplifier
Output impedance preamplifier
1Z011
Output voltage preamplifier (r.m.s. value)
dtot < 1% (note 2)
Vo(rms}
Noise output voltage (r.m.s. value; note 5)
RS =OQ
RS = 10 kn
852
I Zi1/
I Z i21
typo
<
60 Hzto 15 kHz
>
typo
100 kn
200 kn
typo
20 kn
typo
1 kn
typo
0,8 V
Vn(rms)
typo
0,2 mV
Vn(rms)
typo
0,5 mV
Noise output voltage at f = 500 kHz (r.m.s. value)
B = 5 kHz; RS = 0 n
Vn(rms) typo
Ripple rejection (note 6)
f = 100 Hz
RR
November
19821 (
0,3 %
1,0 %
typo
8 p.V
38 dB
TDA1015
1 to 4 W audio power amplifier
Notes
1. Measured with an ideal coupling capacitor to the speaker load.
2. Measured with a load resistor of 20 kn.
= 1 W; the frequency response is mainly determined by C1 and C3 for the low
frequencies and by C4 for the high frequencies.
3. Measured at Po
4. Independent of load impedance of preamplifier.
5. Unweighted r.m.s. noise voltage measured at a bandwidth of 60 Hz to 15 kHz (12 dB/octave).
6. Ripple rejection measured with a source impedance between 0 and 2 kn (maximum ripple
amplitude: 2 V).
7. The tab must be electrically floating or connected to the substrate (pin 9).
~
C6
100nF
-L
~--o{)
+
3
2
Vp
V'I
9
7
6
R2
4,7 n
j
7Z89094.1
Fig. 3 Test circuit.
1
(November 1982
853
_T_DA1_015
_Jl________
APPLICATION INFORMATION
~-----.----------~~----~~~-----o+
3
2
Vp
V·I
7
9
C3
6
R3
100 pF
4,7D.
C5
1
1,8
nF
7Z89095
Fig. 4 Circuit diagram of a 1 to 4 W amplifier.
7Z89097
40
I tot
(mA)
20
~~
.",.
",.
"
o
o
~~
-
....... ~
,.."...
"""'"
10
20
Vp (V)
Fig. 5 Total quiescent current as a function of supply voltage.
854
November 1982] (
30
TDA1015
1 to 4 W audio power amplifier
/
9V
12V
/...........
...............
~
II
,
,,
Vp = 6V
10
d tot
/\
~
II
II
(%)
!
7,5
7Z89093
I
,,
I
I
II
5
I
I
,
I
II
I
I
I
I
II
L'
I
I
I
/
I'
,,
,
I
I
2,5
1
I
I
~
J
II
V
,"
L....-
1/
"
J
J 1
I II
I ~
1 II
J) /
// V
j
Iooo""~
10
Po (W)
Fig. 6 Total harmonic distortion as a function of output power across R L; - - with bootstrap;
- - - without bootstrap; f = 1 kHz; typical values. The available output power is 5% higher when
measured at pin 2 (due to series resistance of C1 0).
7Z89096
5
If
Po
/
(W)
1,/
/
I
RL=4D;,
V
.L
If
/
V
2,5
V
V
10'
10'
.,. ~
1.--' .....
i.-'"
".
t..,..
o
o
lL
V
/
/8D
IL
i...o'
~
I.--'
""'"
~
.... 1"'"
I-""
5
10
15
Vp (V)
20
Fig. 7 Output power across R L as a function of supply voltage with bootstrap; d tot = 10%; typical
values. The available output power is 5% higher when measured at pin 2 (due to series resistance of C10).
1
(November 1982
855
Jl__-----
__
TDA1_015__
7Z78637.1
10
Po
(dB)
o
~
....-
typ
r-~
/"
......
"'"
~
II
"' ~\
II
-10
\.
\.
I
,
1\
-20
10
f (Hz)
Fig.8 Voltage gain as a function of frequency; Po relative to 0 dB
= 1 W; Vp = 12 V;
RL
= 4 n.
7Z786361
10
d tot
(%)
7,5
5
,
2,5
/
V
1\
~i'oo
~
o
typ
....
f (Hz)
10
Fig.9 Total harmonic distortion as a function of frequency; Po
856
November
""
19821 (
= 1 W; Vp = 12 V;
RL
= 4 n.
l____
1 to 4 W audio power amplifier
T_D_A_10_15_______
7Z78635 1
60
RR
~-
(dB)
-f
-
1 kHz
40
-
f----100 Hz
10-
~
.....
-
---
.-- ".,-
.......
~
20
o
1
R2 (kSG)
10
Fig. 10 Ripple rejection as a function of R2 (see Fig. 4); RS = 0; typical values.
7Z78633 1
600
t--
---
-.........RS = 8,2 kSG
"'-...
............
...........
"' ""
400
--
~
"""'- ...........
~
~
RS - 0
-
200
~
r-...
"'
...........
...........
----
r-- t- fo-.
-..........
........ 100..
.......
I"'"
o
1
10
R2 (kSG)
Fig. 11 Noise output voltage as a function of R2 (see Fig. 4); measured according to A-curve; capacitor
C5 is adapted for obtaining a constant bandwidth.
'I
(November 1982
857
__
TD_A10_15
_J l_____________
7Z786321
"-
"~
"-
~ to- ..... f'.~
'"
~~
~
10
~
~
"
.....
1"\
.....
roo.
""\ "\
1
10- 2
10-1
~
f (MHz)
10
Fig. 12 Noise output voltage as a function of frequency; curve a: total amplifier; curve b: power
amplifier; B = 5 kHz; RS = 0; typical values.
7Z78634 1
60
--- ---
Gv
(dB)
typ
40
....... +-.
20
o
1
10
R2 (kn)
Fig. 13 Voltage gain as a function of R2 (see Fig. 4).
858
November
19821 (
............
~~
......
__________________Jl__
TD_A1_015_T_ _
0,5 W AUDIO POWER AMPLIFIER
GENERAL DESCRIPTION
The TDA 1015T is a low-cost audio amplifier which can deliver up to 0,5 W output power into a 16 n
load impedance at a supply voltage of 9 V. The amplifier is specially designed for portable applications
such as radios and recorders. The Ie has a very low supply voltage requirement (3,6 V min.).
Features
•
•
•
•
•
High input impedance
Separated preamplifier and power amplifier
Limited noise behaviour at radio frequencies
Short-circuit protected
Miniature encapsulation
QUICK REFERENCE DATA
3,6 to 12 V
Supply voltage range
Vp
Peak output current
10M
max.
Output power
Po
typo
0,5 W
Voltage gain power amplifier
Gv1
typo
29 dB
Voltage gain preamplifier
Gv2
typo
23 dB
Total quiescent current
Itot
max.
22 mA
1 A
Operating ambient temperature range
Tamb
-25 to +150 oe
Storage temperature range
Tstg
-55 to +150 oe
PACKAGE OUTLINE
8-lead mini-pack; plastic (S08; SOT96A).
'I r:~h 1986
859
Jl____________________________________
______
T_D_A1_0_15_T___
6
4
7Z87971.1
Fig. 1 Block diagram.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage
Vp
max.
12 V
Peak output current
10M
max.
A
Total power dissipation
see derating curve Fig. 2
-55 to +150 oC
Storage temperature range
A.C. short-circuit duration of load
during sine-wave drive at Vp = 9 V
tsc
7Z87973
0,6
Ptot
(W)
0,4
'"
~
~
0,2
o
o
50
~
~
100
""
0
T amb ( C)
Fig. 2 Power derating curve.
860
March
19861 (
150
max.
hour
~~
____T_D_A
__
10_1_5_T_______
________o_,s_w_a_ud_io_p_o_we_r_am_p_li_fie_r________________________
CHARACTERISTICS
Tamb = 25 oC; Vp = 9 V; RL = 16 n; f = 1 kHz; see Fig. 3; unless otherwise specified
parameter
symbol
min.
Supply voltage
typo
max.
Vp
3,6
Repetitive peak output current
IORM
Total quiescent current
Itot
-
A.F. output power at dtot = 10%
(note 1)
Vp=9V;RL=16n
Vp = 6 V; RL = 8n
Po
Po
Voltage gain power amplifier
Gv 1
-
Voltage gain preamplifier (note 2)
Gv2
-
Total voltage gain
Gtot
49
Frequency response at -3 dB (note 3)
B
-
60 to
15000
Input impedance power amplifier
-
20
100
200
Output impedance preamplifier
IZ i11
IZ i21
IZ 021
0,5
1
Output voltage preamplifier (r.m.s. value)
dto t < 1% (note 2)
V 0 2(rms)
-
Noise output voltage (r.m.s. value)
(note 5)
RS = on
RS = 10 kn
Vn(rms)
Vn(rms)
Noise output voltage (r.m.s. value)
f = 500 kHz; B = 5 kHz; RS = 0 n
Ripple rejection at f = 100 Hz;
C2 = 1 IlF (note 6)
Input impedance preamplifier (note 4)
9
unit
12
V
1
A
-
22
mA
0,5
0,3
-
W
W
29
-
dB
23
-
dB
52
55
dB
-
Hz
-
kn
kn
1,5
kn
0,7
-
V
-
0,2
0,5
-
mV
mV
Vn(rms)
-
8
-
IlV
RR
-
38
-
dB
-
12
-
Notes to the characteristics
1. Output power is measured with an ideal coupling capacitor to the speaker load.
2. Measured with a load resistance of 20 kn.
3. The frequency response is mainly determined by the capacitors, C1, C3 (low frequency) and C4
(high frequency).
4. I ndependent of load impedance of preamplifier.
5. Effective unweighted r.m.s. noise voltage measured in a bandwidth from 60 Hz to 15 kHz (slopes
12 dB/octave).
6. Ripple rejection measured with a source impedance between 0 and 2 kn (maximum ripple amplitude
of 2 V).
I (MarCh
1986
861
jl_____________________________________
______T_D_A1_0_15_T___
APPLICATION INFORMATION
100nF
300kn
~r-~----~-j-----~----------~--Vp
R1
C2
6
+
I
TDA1015T
100nF
<;>---1t--f-'--l
r
CI
2
input
J
7Z95550
Fig. 3 Test circuit.
7Z87972 1
20
0,6
/V
Po
0,5
'tot
(rnA)
... V
10
...
V
./
/'
0,4
0,3
/
0,2
~Ij/
4
8
Vp (V)
12
Fig.4 Total quiescent current as a function
of supply voltage.
862
March
19861 (
I
/11
7Z97115
~I
32n
/V /
~V"
o
o
!I
.' I
1// ~ ~
~~~~ ' /
0,1
o
16n
i
/
/,
/f
fI /
/1
il 1/ ~'I
ij
'1 l'l /V
1.'/
i' , V //
'/
// //
~
il 1/ II ~jI
(W)
V
an
2
4
3,6
6
a
10
Vp(V)
12
Fig. 5 Output power as a function of supply
voltage; dtot = 10%; f = 1 kHz.
- - measured in Fig. 3
- - - - measured with a 1,5 Mn resistor
connected between pins 7 and 2.
,J~____
T_D_A_1_0_1_5T
_______
________
O,_5_w_au_d_io_po_w_er_a_m_Pli_fie_r_______________________
7Z97114
12
d tot
II
/1
(%)
10
8
I
,
;
6
4
IT
J
I:
Fig. 6 Total distortion as a function of output
power;Vp=9V; RL= 16Q;f= 1 kHz.
- - - measured in Fig. 3
- - - - - measured with a 1,5 MQ resistor
connected between pins 7 and 2.
V,
°0,01
~
0,1
TDA1015T
8
100nFT
input
7Z97116.1
Fig. 7 Application circuit for power stage only and battery
power supply; Gv 1 = 29 dB; IZi11 = 20 kQ.
r-------------1--------~~+----vp
6
TDA1015T
Fig.8 Application circuit for preamplifier and power amplifier
stages and battery power supply; Gv tot = 52 dB; IZi21 = 200 kn.
'I (
March 1986
863
_________________jl__
T_DA_1016_ __
RECORDING/PLA YBACK AND 2 W AUDIO POWER AMPLIFIER
GENERAL DESCRIPTION
The TDA1016 is a monolithic integrated audio power amplifier, preamplifier and A.L.C. circuit designed
for applications in radio-recorders and recorders. The wide supply voltage range makes this circuit very
suitable for d.c. and a.c. apparatus. The circuit incorporates the following features:
Features
•
•
•
•
•
Power amplifier/monitor amplifier
Preamplifier/record and playback amplifier
Automatic Level Control (A.L.C.) circuit
Voltage stabilizer
Short-circuit (up to 12 V a.c.) and thermal protection.
QUICK REFERENCE DATA
Supply voltage range
3,6 to 15 V
Vp
Supply current; total quiescent at Vp = 6 V
Itot
Operating ambient temperature range
Tamb
typo
10 mA
--25 to 150 0C
Power ampl ifier
Output power at d tot = 10%
Vp = 6 V; RL = 4 n
Vp = 9 V; RL = 4
n
Closed loop gain
Po
typo
1W
Po
typo
2W
Gc
typo
36 dB
Go
min.
70 dB
Gc min
min.
35 dB
Vo
min.
1 V
LlG v
typo
2 dB
V5-16
typo
Preamplifier
Open loop gain
Minimum closed loop voltage gain
Output voltage at dtot
= 1%
Automatic Level Control (A.L.C.)
Gain variation for Ll Vi
= 40 dB
Stabilized supply voltage
Output voltage
2,6 V
PACKAGE OUTLINE
16-lead DI L; plastic, with internal heat spreader (SOT38).
'I
(November 1983
865
jl~________________
_ _ _T_DA_1016_ _
560 pF
220pF
10kQ
+
100,oF
7Z80254.2
Fig. 1 Block diagram with external components; also used as test circuit.
866
November
19831 (
l__
Recording/playback and 2 W audio power amplifier
T_D_A_10_1_6_ _
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage (pin 3)
Vp
max.
18 V
Repetitive peak output current
IORM
max.
1 A
Non-repetitive peak output current (pin 1)
Total power dissipation
max.
2 A
IOSM
see derating curve Fig. 2
A.C. short-circuit duration of load during
sinewave drive; Vp = 12 V
tsc
max.
100 hours
Crystal temperature
Tc
max.
150 °C
Storage temperature range
T stg
-55 to + 150 oC
Operating ambient temperature range
Tamb
-25 to + 150 0C
THERMAL RESISTANCE
The power derating curve (Fig. 2) is based on the following data
From junction to ambient
Rth j-a
55 K/W
7280256
Ptot
(W)
~
\~
~
o
-50
50
1\
150
100
Tomb (·C)
Fig. 2 Power derating curve.
1(
October 1983
867
~
jl_________________
_ _ _T_DA_1016_ _
CHARACTERISTICS
Vp == 6 V; R L == 4 Q; f == 1 kHz; T amb == 25 °C; measured in test circuit Fig. 1; unless otherwise specified
symbol
min.
typo
Supply voltage
Vp
3,6
6
Supply current; total quiescent
at Vp == 6 V
I tot
-
parameter
max.
unit
15
V
10
-
mA
1
-
W
Supply (pin 3)
Power amplifier
Output power at d tot == 10%*
Vp == 6 V
Po
-
RR
0,5
40
Noise output voltage (r.m.s. value)
RS = 0 Q; B = 60 Hz to 15 kHz
Vn(rms)
Noise output voltage at 500 kHz
RS = 0 Q; B = 5 kHz
Vp == 9 V
Po
Closed loop voltage gain
Total harmonic distortion at Po == 0,5 W
Gc
d tot
Input impedance
IZil
2
36
-
W
dB
1
%
-
-
MQ
50
-
dB
-
90
200
p,V
Vn
-
8
-
p,V
Go
70
Gc
-
-
dB
Closed loop voltage gain
78
52
Minimum closed loop voltage gain
(when changing Rf)
Gc min
Ripple rejection at f == 100 Hz (RS
= 0 Q)
Preamplifier
Open loop voltage gain at f
= 10 k~z
35
-
-
dB
Vo
1
-
-
V
Output voltage with A. L.C.
Vi = 2 mV
Vo
0,45
0,5
0,55
V
Total harmonic distortion with A.L.C.
Vi = 2 mV
dtot
-
-
1
dtot
-
-
3
%
%
60
-
dB
-
-
kQ
Output voltage at dtot
Vi
= 1%
= 360 mV
Signal-to-noise ratio related to Vi = 1,2 m V;
RS = 1 kQ; B = 60 Hz to 15 kHz
SIN
-
Input impedance
IZi!
100
RR
50
54
-
dB
1Zol
-
-
50
Q
Ripple rejection
at f = 100 Hz; RS
=0 Q
Output impedance **
*
Measured with an ideal coupling capacitor connected to the speaker load.
** Ip (effective value) must not exceed 1 mA.
868
dB
October 1983
j(
l____
Recording/playback and 2 W audio power amplifier
parameter
T_D_A_10_1_6______
symbol
typo
min.
max.
unit
Automatic Level Control (A.L.C.) (see Fig. 3) **
= 45 dB
~Gv
-
Limiting time*
tl
-
Level setting time*
ts
-
tr
-
100
Output voltage
V11-15
-
Load current
111
RR
-
40
Gain variation for
~ Vi
Recovery time* ...
2
3
dB
-
50
ms
-
50
ms
-
s
2,6
-
V
-
1,5
rnA
-
-
dB
Voltage stabilizer
Ripple rejection at f
= 100 Hz
Vo
(V)
L-+-=:::::::::::::========~6~VO~3dB max.
t
I
I
I
I
10
10 2
360
10 3
Vi (mV)
Vi
(mV)
6Vi =40dB
1.2
time
Vo
(V)
0.5
~~=======::::1dB
time
7Z80255.1
Fig.3 Typical A.L.C. curve with RS
= 10 kn.
* At ~Vi = 40 dB with respect to Vi = 1,2 mV.
** The A. L.C. tracking in stereo has a typical spread of 1 dB if pins 6 of both ICs are connected to
the same RC network.
... Without a shunt resistor across A.L.C.
With 1 Mn or 2,2 Mn across A. L.C. recovery time becomes 22 or 50 seconds.
1(AUgust
1987
869
_________Jl__
TD_A10_20_
12 W CAR RADIO POWER AMPLIFIER
The TDA 1020 is a monolithic integrated 12 W audio amplifier in a 9-lead single in-line (SI L) plastic
package. The device is primarily developed as a car radio amplifier. At a supply voltage of Vp = 14,4 V,
an output power of 7 W can be delivered into a 4 n load and 12 W into 2 n.
To avoid interferences and car ignition signals coming from the supply lines into the IC, frequency
limiting is used beyond the audio spectrum in the preamplifier and the power amplifier.
The maximum supply voltage of 18 V makes the IC also suitable for mains-fed radio receivers, tape
recorders or record players. However, if the supply voltage is increased above 18 V « 45 V), the
device will not be damaged (load dump protected). Also a short-circuiting of the output to ground
(a.c.) will not destroy the device. Thermal protection is built-in. As a special feature, the circuit has a
19w stand-by current possibility.
The TDA 1020 is pin-to-pin compatible with the TDA 1010.
QUICK REFERENCE DATA
Supply voltage range
Vp
Repetitive peak output current
IORM
Output power at dtot = 10% (with bootstrap)
Vp = 14,4 V; R L = 2 n
Po
Vp=14,4V;RL=4n
Vp= 14,4 V; RL =8n
Output power at dtot = 10% (without bootstrap)
Vp= 14,4 V; RL =4n
Input impedance
preamplifier (pin 8)
power amplifier (pin 6)
Total quiescent current at Vp = 14,4 V
6 to 18 V
<
4 A
>
Po
Po
typo
typo
typo
10 W
12 W
7W
3,5 W
Po
>
4,5 W
typo
typo
40 kn
40 kn
typo
30 rnA
\Zi!
\Zil
Itot
<
Storage temperature range
Isb
T stg
Crystal temperature
Tc
max.
Stand-by cu rrent
1 rnA
-55 to + 150 °C
150 °C
PACKAGE OUTLINE
9-lead SI L; plastic (SOT110B).
1(
November 1982
871
co
....,
IV
--I
CJ
»
......
z
o
Cl5
:3
0-
~
~------------------------------~04
co
00
N
5 o--------------~
6
ELECTRONIC FILTER/ I
STAND-BY SWITCH ~----+-----t.-----
....-----o 3
+
r
I
LOAD
DUMP
PROT.
I
SOAR
PROT.
7
V
~
8
001=_
~
J.
II I
02
7Z84547.1
9
o.
..
Fig. 1 Internal block diagram; the heavy lines indicate the signal paths.
PINNING
1. Negative supply (substrate)
2. Output power stage
3. Positive supply (Vp)
4. Bootstrap
5. Ripple rejection filter
6. I nput power stage
7. Output preamplifier
8. Input preamplifier
9. Negative supply
o
tv
o
l____
10 W car radio power amplifier
T_D_A_10_2_0______
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage; operating (pin 3)
Vp
max.
18 V
Supply voltage; non-operating
Vp
max.
28 V
Supply voltage; load dump
Vp
max.
45 V
Non-repetitive peak output current
max.
6 A
IOSM
see derating cu rves Fig. 2
Total power dissipation
Storage temperature range
-55 to + 150 °C
T stg
Tc
Crystal temperature
Short-circuit duration of load behind output electrolytic capacitor
at 1 kHz sine-wave overdrive (10 dB); Vp = 14,4 V
max.
150 °C
max.
100 hours
7Z84548 1
10
"
~
I"
Ptot
"
~
......
(W)
t--..
I"""'~
"
5
I\.
.....
"""'~
r-..
Rth h-a Ir-... 9 K/W
......
,
-~
--
~infinite
1--
I\.heatsink --
I'"
"-
I'
......
,
.... '" .....
1'\
I\.
......
o
~
o
50
100
T
amb
(oC) 150
Fig. 2 Power derating curves.
HEATSINK DESIGN EXAMPLE
The derating of 8 K/W of the encapsulation requires the following external heatsink (for sine-wave
drive):
10 Win 2 nat Vp = 14,4 V
maximum sine-wave dissipation: 5,2 W
T amb = 60 °C maximum
Rth j-a
= Rth j-tab + Rth tab-h + Rth h-a = 150 - 60 = 17,3 K/W
5,2
Since Rth j-tab + Rth tab-h = 8 K/W, Rth h-a = 17,3 - 8 ~ 9 K/W.
' ] (November 1982
873
__
TD_A102_0
_Jl_____________
D.C. CHARACTERISTICS
Supply voltage range (pin 3)
6 to 18 V
Vp
Repetitive peak output current
IORM
<
Total quiescent current
atVp=14,4V
at Vp = 18 V
Itot
Itot
typo
typo
4 A
30 mA
40 mA
A.C. CHARACTERISTICS
T amb
= 25 oC; Vp = 14,4 V;
RL
= 4 U; f = 1 kHz; unless otherwise specified; see also
Output power at d tot = 10%; with bootstrap (note 1)
Vp = 14,4 V; R L = 2 U
Vp
= 14,4 V;
RL
=4 U
Po
Vp
= 14,4 V;
RL
=8 U
Po
Output power at d tot = 1%; with bootstrap (note 1)
Vp = 14,4 V; RL = 2 U
>
typo
>
10 W
12 W
typo
6W
7 W
typo
3,5 W
Po
typo
9,5 W
Vp= 14,4 V; RL =4U
Po
typo
6W
=8 U
Po
typo
3W
Vo(rms) typo
5 V
Vp = 14,4 V; RL
Output voltage (r.m.s. value)
RL = 1 kU; d tot = 0,5%
Po
>
Gv l
typo
17,7 dB
16,7 to 18,7 dB
power amplifier
Gv2
typo
29,5 dB
28,5 to 30,5 dB
total amplifier
Gvtot
typo
47 dB
46,2 to 48,2 dB
Output power at d tot = 10%; without bootstrap
Voltage gain
preamplifier (note 2)
Input impedance
preamp Iifier
IZi I
Output impedance
preamplifier
IZol
power amplifier
typo
40 kU
28 to 52 kU
typo
40 kU
28 to 52 kU
typo
2,0 kU
1,4 to 2,6 kU
IZol
= 1%
typo
50 mU
>
1 V
1,5 V
Vo(rms) typo
Frequency response
B
Noise output voltage (r.m.s. value; note 3)
RS=OU
Vn(rms)
<
Vn(rms)
<
RS
= 8,2 kU
November
19821 (
4,5 W
IZd
power amplifier
Output voltage (r.m.s. value) at dtot
preamplifier (note 2)
874
Po
Fig. 3
50 Hz to 25 kHz
typo
typo
0,3 mV
0,5 mV
0,5 mV
1,0 mV
l____
10 \IV car radio power amplifier
T_D_A_10_2_0______
Ripple rejection (note 4)
at f = 100 Hz; C2 = 1 JlF
at f
= 1 kHz to
RR
10kHz
RR
typo
44 dB
>
typo
48 dB
54 dB
40 mA
Bootstrap current at onset of clipping (pin 4)
RL = 4 nand 2 n
14
typo
Stand-by current (note 5)
Isb
<
>
Crystal temperature for -3 dB gain
Tc
1 mA
150 °C
Notes
1.
2.
3.
4.
5.
6.
Measured with an ideal coupling capacitor to the speaker load.
Measured with a load resistor of 40 kn.
Measured according to I EC curve-A.
Maximum ripple amplitude is 2 V; input is short-circuited.
Total current when disconnecting pin 5 or short-circuited to ground (pin 9).
The tab must be electrically floating or connected to the substrate (pin 9).
c5I
C2!
100 nF
100 nF
ripple voltage
meter
+
3
100JlF
2
+
Vp
C6
100 nF
V·I
9
7
6
RL
R2
4,7 n
j
7Z84546
(1) With R L = 2
n, preferred value of C8 = 2200 JlF.
Fig. 3 Test circu it.
'I (
November 1982
875
_________________jl__
T_DA1_029
_ __
SIGNAL-SOURCES SWITCH
The TDA 1029 is a dual operational amplifier (connected as an impedance converter) each amplifier
having 4 mutually switchable inputs which are protected by clamping diodes. The input currents are
independent of switch position and the outputs are short-circuit protected.
The device is intended as an electronic two-channel signal-source switch in a.f. amplifiers.
QUICK REFERENCE DATA
Supply voltage range (pin 14)
Vp
Operating ambient temperature
Tamb
-30 to + 80 °C
Supply voltage (pin 14)
Vp
typo
Current consumption
114
typo
Maximum input signal handling (r.m.s. value)
Voltage gain
Vi(rms) typo
typo
Gv
Total harmonic distortion
dtot
typo
Crosstalk
ex
typo
70 dB
Signal-to-noise ratio
SIN
typo
120 dB
6 to 23 V
20 V
3,5 rnA
6 V
0,01 %
PACKAGE OUTLINE
16-lead D I L; plastic (SOT38).
'I (
January 1980
877
__
TD_A10_29
_Jl____________
+
I
100
JlF
~(15V)
RS = 47 kn (8x)
Rbias =470kn (8x)
signal inputs
SWITCH I
SWITCH II
BIAS
VOLTAGE
signal
output
II
RL =4,7kil
10
9
11
12
4
£T IC
CIRCUIT
SUPPLY
VOLTAGE
SWITCH
CONTROL
3
13
2
1
0--
14
signal
output
I
15
16
L -IOOpF
7Z76181.1
Fig. 1 Block diagram.
878
I(
January 1980
,J·~____
T_D_A_1_0_29______
________
Sig_na_l-s_ou_rc_es_sw_it_ch_________________________
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage (pin 14)
Vp
max.
23 V
Input voltage (pins 1 to 8)
VI
-VI
max.
max.
Vp
0,5 V
Switch control voltage (pins 11,12 and 13)
Vs
Oto 23 V
Input current
± II
max.
20 rnA
Switch control current
-IS
max.
50 mA
Total power dissipation
Ptot
T stg
max.
800 mW
Storage temperature
Operating ambient temperature
Tamb
-55 to + 150 °C
-30 to +80 o C
114
typo
CHARACTERISTICS
Vp
= 20 V; Tamb = 25 oC; unless otherwise specified
Current consumption
without load; 19 = 115
=0
Supply voltage range (pin 14)
3,5 mA
2to 5 mA
6 to 23 V
Vp
Signal inputs
I nput offset voltage
of switched-on inputs
RS~ 1 kn
Vio
<
I nput offset current
of switched-on inputs
lio
<
I nput offset current
of a switched-on input with respect to a
non-switched-on input of a channel
lio
Input bias current
independent of switch position
Ii
<
Capacitance between adjacent inputs
C
typo
D.C. input voltage range
VI
Supply voltage rejection ratio; RS ~ 10 kn
SVRR
typo
100 p.V/V
Equivalent input noise voltage
RS = 0; f = 20 Hz to 20 kHz (r.m.s. value)
Vn(rms)
typo
3,5 p.V
Equivalent input noise current
f = 20 Hz to 20 kHz (r.m.s. value)
In(rms)
typo
0,05 nA
typo
100 dB
Crosstalk between a switched-on input
and a non-switched-on input;
measured at the output at RS = 1 kn; f = 1 kHz
typo
typo
typo
<
typo
2 mV
10 mV
20 nA
200 nA
20 nA
200 nA
250 nA
950 nA
0,5 pF
3 to 19 V
'I (
Januaoy 1980
879
~
___T_DA_102_9_Jl~________________
CHARACTERISTICS (continued)
Signal amplifier
Voltage gain of a switched-on input
at 19 = 115 = 0; R L = 00
typo
Gv
G·I
typo
10 5
Ro
typo
400 n
±19;±115
typo
5 mA
typo
1,3 MHz
S
typo
2 V/MS
D.C. output voltage
VlO-16
typo
11 V *
10,2 to 11,8 V
Output resistance
RlO-16
typo
Current gain of a switched-on amplifier
Signal outputs
Output resistance (pins 9 and 15)
Output current capability at Vp
= 6 to 23 V
Frequency limit of the output voltage
Vi(p-p) = 1 V; RS = 1 kn; RL = 10 Mn; CL = 10 pF
Slew rate (unity gain); .1V9-16/.1t; .1V15-16/.1t
RL::: 10Mn;cL = 10pF
Bias voltage
8,2 kn
Switch control
I
sw~tched-on
Inputs
interconnected
pins
control voltages
V11-16
V12-16
V13-16
11-1
11-2
11-3
11-4
1-15, 5-9
2-15,6-9
3-15,7-9
4-15,8-9
H
H
H
L
H
H
L
H
H
L
H
H
1-4,11-4
1-4,11-4
1-4, 11-4
1-3,11-3
4-15,8-9
4-15,8-9
4-15,8-9
3-15,7-9
L
L
L
H
L
H
L
L
H
L
L
L
1-1,
1-2,
1-3,
1-4,
In the case of offset control, an internal blocking circuit of the switch control ensures that not more
than one input will be switched on at a time. In that case safe switching-through is obtained at
VSL ~ 1,5 V.
Control inputs (pins 11, 12 and 13)
Required voltage
HIGH
LOW
VSH
VSL
>
<
3,3 V **
2,1 V
I nput current
HIGH (leakage current)
LOW (control current)
ISH
-ISL
<
<
1 MA
250 MA
V1O-16 is typically 0,5'V14-16 + 1,5'VBE'
* * Or control inputs open (R 11,12,13-16> 33 Mn).
880
January 1980
'I (
j
Signal-sources switch
TDA1029
-----APPLICATION INFORMATION
Vp
CL
= 20 V; Tamb = 25 °C; measured
in Fig. 1; RS
= 47 kn; Ci = 0,1 /IF; Rbias = 470 kn; RL = 4,7 kn;
= 100 pF (unless otherwise specified)
Voltage gain
typo
Gv
Output voltage variation when switching
the inputs
~V9-16;
~V15-16
)
typo
<
-1,5 dB
10 mV
100 mV
Total harmonic distortion
over most of signal range (see Fig. 4)
Vi = 5 V; f = 1 kHz
Vi = 5 V; f = 20 Hz to 20 kHz
dtot
dtot
dtot
Output signal handling
dtot = 0,1 %; f = 1 kHz (r.m.s. value)
Vo(rms)
Noise output voltage (unweighted)
f = 20 Hz to 20 kHz (r.m.s. value)
Vn(rms)
typo
5 JlV
Noise output voltage (weighted)
f = 20 Hz to 20 kHz (in accordance with DIN 45405)
Vn
typo
12 JlV
~V9-16;
~V15-16
<
0,1 dB *
Crosstalk between a switched-on input
and a non-switched-on input;
measured at the output at f = 1 kHz
a
typo
75 dB **
Crosstalk between switched-on inputs
and the outputs of the other channels
a
typo
90 dB **
Amplitude response
Vi = 5 V; f = 20 Hz to 20 kHz; Ci
= 0,22 /IF
typo
typo
typo
>
typo
0,01 %
0,02 %
0,03 %
5,0 V
5,3 V
The lower cut-off frequency depends on values of Rbias and Ci.
** Depends on external circuitry and RS' The value will be fixed mostly by capacitive crosstalk of the
external components.
I(
January 1980
881
___T_DA_102_9~Jl~________________
7Z75947 1
..........
,
~Ioo""
r--.
--
...........
.....
-r--
-
10- 1
10
f (Hz)
Fig. 2 Equivalent input noise current.
7Z75945.1
-
-:- r--~
10
10
882
January 1980
f (Hz)
'I (
Fig. 3 Equivalent input noise volta~e.
~l~
_______S_ig_nal_-so_ur_ce_ss_wi_tch
_______________________
___
T_D_A_10_2_9______
7Z75944
0,8
d tot
(%)
0,6
ZL =1 Mn II 100pF,,,,'-':N
I I
I I
ZL =4,7 kn II
0,4
I
100pF"
~
10
'"
I
I
I
I
I
II
0,2
II
~
o
-1-
o
--2-- .- -----
..... -
i-I-
I_I-
-I-~
I-~
~I-
-~ -r-
4
-~
Vo (rms) (V)
6
Fig. 4 Total harmonic distortion as a function of r.m.s. output voltage.
- f = 1 kHz;---- f=20kHz.
1(
January 1980
883
___
TD_A10_29_Jl_________________
7Z72937
30
f = 1 kHz
d tot = 1%
V9 ;15-16
RL = 00
(V)
max
20
,
V
10
V
,
,,
,
,
f-
~
~
V
V
~
V
V
V
r.,],si L,..oon
1/
o
....
I
",
1/
~
~
...
min -
L,..oo ....
5
1
15
Vp(V)
25
Fig. 5 Output voltage as a function of supply voltage.
7Z75946
Vn (rms)
(IlV)
10
.....
",.
---
~
[/
~
V ..
...
/
..,, "
V
V
/
.., ~
",
".
i.o'
... i-"'"
[/
//
",
".'"
1
1
~.
...
I......
~
10
Fig. 6 Noise output voltage as a function of input resistance; Gv
Vn (output); - - - Vn (RS)'
884
January 1980
'I (
Ri (kn)
20 kHz.
= 1; f = 20 Hz to
~
,Jl____
_____
S_ign_al__
so_ur_ces_sw_it_ch_______________________
T_D_A_10_2_9______
APPLICATION NOTES
Input protection circuit and indication
_---Vp
TDA1029
.-----Vp
SWITCH
CONTROL
11
12
13
+~-~
(~23V)
7Z75943.1
Fig.7 Circuit diagram showing input protection and indication.
Unused signal inputs
Any unused inputs must be connected to a d.c. (bias) voltage, which is within the d.c. input voltage
range; e.g. unused inputs can be connected directly to pin 10.
Circuits with standby operation
The control inputs (pins 11,12 and 13) are high-ohmic at VSH';;;; 20 V (ISH';;;; 1 MA), as well as, when
the supply voltage (pin 14) is switched off.
'I (
January 1980
885
jl~________________
_ _ _T_DA_1029_ _
+ 20V d.c. - - - - - - - - - - - - - - . . . . - - - - - - - - - - - - - - ,
0,22pF
I
14
(8x)
470kn
10
RADIO
input L
t
input R
~----------u-_----+-~
11
12
13
}
pin connected to 0 V
or LOW level:
none = radio
13 = pick-up
12 = tape 1
11 = tape 2
15
TDA1029
OUTPUT
j..:9~-.:R~_+-
0,1
pF
PREAMPLIFIER
(with RIAA equalization)
Fig. 8 TDA 1029 connected as a four input stereo source selector.
886
January 1980
'I (
___ R
0,1
pF
Jl
Signal-sources switch
TDA1029
+20Vd.c.------------------------~~--------------------~------------------------,
0,22I'F
RADIO
inputL
input R
1
14
(8x)
470kSl
10
t
pin connected to OV
or LOW level:
11
12
~-------------------H--........----.,..........:,
} "'"'
-"';0
13 = pick-up
12 = tape 1
11 = tape 2
13
3
15
820
kSl
L
TDA1029
4
820
kSl
9
R
8
6
PREAMPLIFIER
(with RIAA equalization)
~------------~----------------~
OV or LOW
= AUX. on
2,2kSl
~T~PE
~
>-~~~....,Ir--r-~~2=,2=k=Slr
LINE
OUT
R
L
OUTPUT
~~12~--__- - - - - -______--+ R
7Z84042.1A
Fig. 9 TDA 1029 and TDA 1028 connected as a
five input stereo source selector with monitoring facilities.
OV or LOW = monitor on
1(
January 1980
887
jl_________________
_ _ _T_DA1_029_ _
120 kn (8x)
left
15
left
output
9
right
output
Vp
~~"-(+20V)
11
mute
12
13
rumble
filter
subsonic
filter
7Z84185
Fig. 10 TDA 1029 connected as a third-order active high-pass filter with Butterworth response and
component values chosen according to the method proposed by Fjallbrant. It is a four-function
circuit which can select mute, rumble filter, subsonic filter and linear response.
Switch control
function
Vll-16
V12-16
V13-16
H
H
H
L
H
H
L
H
L
linear
subsonic filter 'on'
rumble filter 'on'
mute 'on'
888
January 1980
'I (
X
X
X
____
~l
_______
S_ign_al-_so_ur_ces_sw_it_ch_______________________
T_D_A_1_0_29______
7Z84183
Gv
(dB)
o
-- ~I-
..... ~
i,I"
."
",
~"Iinear
/
-10
/
/
/
/
/
1/
J
/
J
/
/
/
I
/
IJ
-20
/
subsonic t/'(
filter I
,; rumble
)
filter
/
-30
/
I
I
/
II
/
:/
-40
I
/
J
I
L
I
/
I
1
-50
1
10
f (Hz)
Fig. 11 Frequency response curves for the circuit of Fig. 10.
I(
January 1980
889
~
TDA10598
MOTOR SPEED REGULATOR WITH THERMAL SHUT-DOWN
The TDA 10598 is a monolithic integrated circuit with a current limiter and with good thermal
characteristics in a TO-126 plastic package for easy mounting. It is intended to regulate the speed
of d.c. motors in record players, cassette recorders and car cassette recorders.
QUICK REFERENCE DATA
Supply voltage
Vp
= V2-1
typo
9 V
3,3 to 16 V
1,3 V
Internal reference voltage
Vref
typo
Drop-out voltage
V3-1
typo
1,8 V
Limited output current
131im
typo
0,6 A
Multiplication coefficient
k
typo
9
PACKAGE OUTLINE
Dimensions in mm
Fig. 1 TO-126 (SOT-32).
Pin 1 connected to metal part of mounting surface.
\"-7,8 max-.\
3",2_
-+--_~
~
3£-
t
3,75
_
max
I
+
I
11,1
1
'--rr--rr----y-...... - - .
2,54 (1)
max
--t
1
15!3
min
2
,
-.1
,
14,581
1..-
-.11..0,5
l'
,
-.1
0,88__ 11~
max
1
31j1' ~_ _-'-
7ZS9324.2A
1_ _
12,291
(1) Within this region the cross-section of the leads is uncontrolled.
'I (
November 1982
891
___TD_A1_059_B_jl~_________________
Vp
2
CRYSTAL
TEMPERATURE
LIMITER
REFERENCE
VOLTAGE
k
,..-_ _-"A____........
CURRENT
LIMITER
7Z74790.1
Fig. 2 Functional diagram.
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage
Vp
= V2-1
max.
16 V
Storage temperature
-55 to + 150 0C
Operating ambient temperature (see Fig. 3 and note)
-25 to + 130 0C
THERMAL RESISTANCE
From junction to case
From junction to ambient
Rthj-c
10 K/W
Rthj-a
100 K/W
7Z74789.1
1500
Ptot
(mW)
1000
....... t-..
I"""'-~
............
....... t-..
500
...........
...... t-..
....... t-..
.....
o
-25
o
-"t.....
t-..
25
50
75
100
125
Tamb (oC)
150
Fig. 3 Power derating curve.
Note
At ambient temperatures above 130 oC, the crystal temperature limiter decreases the internal power
consumption.
892
November
19821 (
~
jl____
TD_A_1_0_5_98______
_____M_ot_or_sp_eoo
__
reg_UI_ato_r______________________
CHARACTERISTICS
Vp = 9 V; Tamb = 25 oC; R20 = 0; heatsink with Rth = 100 K/W and after thermal stabilization;
unless otherwise specified; see test circuit Fig. 4.
min.
Supply voltage
Vp = V2-1
Internal reference voltage
Vp = 3,3 V; 13 = 80 mA
Vref
Drop-out voltage
13 = 80 mA; ~Vref = 5%
V3-1
typo
max.
3,3
9
16 V
1,24
1,3
1,36 V
1,8
2,06 V
2,3
2,8 mA
1 A
Quiescent current; 13 = 0
Iq
1,8
Limited output current*
13lim
0,3
0,6
Multiplication coefficient
13 = 50 mA ± 10 mA
k=-
8,5
9
9,5
-0,115
0
+ 0,115 %/V
0,86
%/V
Line regulation
Vp = 3,3 to 16 Vat 13 = 50 mA
reference voltage variation
~13
~12
~V
f
~ /~Vp
Vref
multiplication coefficient variation
13 = 50 ± 10 mA
input current variation; 13 = 50 mA
~k /~Vp
k
~12
~Vp
-15
0
+ 20 JlA/V
0
19
38,5 %/A
-0,075
0
+ 0,075 %/mA
-0,03
0
+ 0,03 %/K
0,008
%/K
Load regulation
reference voltage variation
13 = 20 to 80 mA
~Vref
/~13
Vref
multiplication coefficient variation
13=30± 10t070± 10mA
~k / ~13
k
Temperature coefficient
13 = 50 mA; Tamb = -15 to + 65 0C
reference voltage variation
multiplication coefficient variation
= ± 10 mA
~13
input current variation
~Vref
- - /~Tamb
Vref
~k
-
k
/~Tamb
~12
~Tamb
-2
0
+2 JlA/K
* If the motor is stopped by a mechanical brake, the current limitation is effective in the supply voltage
range. If the motor is short-circuited, the TDA 1059B will be damaged if the supply voltage is higher
than 10 V due to parasitic oscillations.
'1
(November 1982
893
___TD_A10_59_B_Jl~________________
r---------........-
Note
VP
For start operation: V ref must start with final
Vp = 6,7 V and a time constant of 3 T = 100 ms
in which T = R.C; R = source impedance,
C = by-pass capacitor.
Fig. 4 Test circuit.
Vp
APPLICATION INFORMATION
k
3
7Z74792.1
(1) Inclusion of D(BA220) is arbitrary; it permits
compensation of variation of the motor resistance
as function of temperature.
(2) Motor example (without diode D):
Catalogue no. 9904 12001806; n = 2000 rev/min; R20 = 180 n (± 2%); R32 = 100 n + 100 n (variable).
Fig. 5 Example of using the TDA 1059B in a d.c. motor speed regulation circuit.
894
November 19821 (
jl____
M_oto_r_spe_~_re_gU_la_tor
_______
T_DA_1_0_59_8______
______________________
Motor equations
Em
=
Vm
a1 n
a2 r
1m
=
Em+Rmlm
where: a1, a2 = motor constant
n = number of revolutions
r = motor torque
Em = back electromotive force
Rm = motor resistance
The back electromotive force (Em) in Fig. 5 can be expressed (excluding diode 0) as:
and including diode 0, as:
Em
= ( R:O
- Rm ) 1m +( Vref + Vo )
{1 + ~~~ (1 + ~ ) }+ R20.l o
Speed regulation is constant when Em is independent of 1m variations; this will be obtained when
R20 = kR m .
Em, and therefore the motor speed, is regulated by R32. A practical condition for stability is
R20 < kR m .
1
(November 1982
895
__________________jl__
TD_A1O_72_A_ _
AM RECEIVER CIRCUIT
GENERAL DESCRIPTION
The TDA 1072A integrated AM receiver circuit performs the active and part of the filtering functions
of an AM radio receiver. It is intended for use in mains-fed home receivers and car radios. The circuit
can be used for oscillator frequencies up to 50 MHz and can handle r.f. signals up to 500 mY. R.F.
radiation and sensitivity to interference are minimized by an almost symmetrical design. The voltagecontrolled osci Ilator provides signals with extremely low distortion and high spectral pu rity over the whole
frequency range even when tuning with variable capacitance diodes. If required, band switching diodes
can easily be applied. Selectivity is obtained using a block filter before the Lt. amplifier.
Features
•
•
•
•
•
•
•
•
•
•
Inputs protected against damage by static discharge
Gain-controlled r.f. stage
Double balanced mixer
Separately buffered, voltage-controlled and temperature-compensated oscillator, designed for
simple coils
Gain-controlled Lt. stage with wide a.g.c. range
Full-wave, balanced envelope detector
Internal generation of a.g.c. voltage with possibility of second-order filtering
Buffered field strength indicator driver with short-circuit protection
A F. preampl ifier with possibil ities for simple a. f. filtering
Electronic standby switch
QUICK REFERENCE DATA
Supply voltage range
Vp
Supply current range
Ip
R.F. input voltage for S + N/N
= 6 dB at m = 30%
7,5 to 18 V
15 to 30 rnA
V'I
typo
1,5 J.l.V
Vi
typo
500 mV
Vo(af)
typo
310 mV
typo
86 dB
typo
2,8 V
R. F. input voltage for 3% total harmonic
= 80%
AF. output voltage with Vi = 2 mY;
fi = 1 MHz; m = 30% and fm = 400
distortion (THD) at m
Hz
AG.C. range: change of Vi for 1 dB change of Vo(af)
Field strength indicator voltage at
Vi = 500 mY; RL(9) = 2,7 kn
VIND
PACKAGE OUTLINE
16-lead DI L; plastic (SOT38).
"\ (May 1984
897
Jl~
______T_D_A_10_7_2_A___
___________________________________
~
Cosc
12to440pF
~ lr"r
C4
470pF
($)
1
~~
$
pF
33 pF C8
+ VB
RL (9)
2,7 kU
C9J..
_ .. 10nFi
O
100nF
15
GAIN-
13
12
INTERNAL
SUPPLY
VOLTAGES
220U
CONTROLLED
OSCILLATOR ~----1""'---J
BALANCED
FULL-WAVE
DETECTOR
STANDBY
SWITCH
MIXER
ftC
o ~
R2
22U
c1I
optional
band switching
diodes
A.F.
PRE -
9
INDICATOR
DRIVER
A.G.C.
AMPLIFIER
V R (a.g.c.)
TDA1072A
..........---- 10 mV
I.F. output impedance
R 14-16, R 15-16
kQ
Conversion transconductance
before start of a.g.c.
Maximum Lf. output voltage, inductive
coupling to pin 1
11/V i
-
6,5
-
mA/V
V1-13(p-p)
-
5
-
V
D.C. value of output current (pin 1)
at Vi = 0 V
11
-
1,2
30
-
dB
-
500
-
mV
A.G.C. range of input stage
R.F. signal handling capability:
input voltage for THD = 3% at m
900
pF
May
19841 (
= 80%
Vi(rms)
mA
____
~l
______A_M_re_re_ive_rc_irc_ui_t_______________________
symbol
parameter
T_D_A_10_7_2A
______
min.
typo
max.
unit
Oscillator
fosc
0,6
-
60
MHz
Oscillator amplitude (pins 11 to 12)
V11-12
-
130
150
mV
External load impedance
R12-11(ext)
0,5
-
200
kU
External load impedance for no oscillation
R12-11(ext)
-
-
60
U
Ripple rejection at VP(rms) = 100 mY;
fp = 100 Hz
(RR = 20 log [V13-16/Vll-16])
RR
55
-
dB
4,2
Frequency range
Source voltage for switching diodes (6 x VB E)
Vll-16
-
D.C. output current (for switching diodes)
--111
0
-
20
mA
Change of output voltage at
.:l111 = 20 mA (switch to maximum load)
.:lVll-16
-
0,5
-
V
V1O-16
0,7
-
V
320
V
Buffered oscillator output
Output impedance
R10
Output current
-110(peak)
-
D.C. input voltage
V3-16, V4-16
I.F. input impedance
R3-4
C3-4
-
D.C. output voltage
Output signal amplitude
V 10-16(p-p)
mV
170
-
U
-
3
mA
-
2,0
-
V
2,4
3
7
3,9
-
kU
pF
-
dB
I.F., a.g.c. and a.f. stages
I.F. input voltage for
T HD = 3% at m = 80%
V3-4
Voltage gain before start of a.g.c.
V3-4/V6-16
A.G.C. range of Lf. stages: change of
V3-4 for 1 dB change of Vo(af);
V3-4(ref) = 75 mV
-
90
68
dB
3,5
-
.:lV3-4
-
55
= 50 p.V
AF. output voltage at V3-4(if) = 1 mV
Vo(af)
-
130
Vo(af)
310
A.F. output impedance (pin 6)
1Zol
-
A.F. output voltage at V3-4(if)
mV
mV
mV
kU
Indicator driver
Output voltage at Vi
RL(9) = 2,7 kU
= 0 mY;
V9-16
-
20
150
mV
Output voltage at Vi = 500 mY;
RL(9) = 2,7 kU
V9-16
2,5
2,8
3,1
V
Load resistance
RL(9)
1,5
-
-
kU
I
(May 1984
901
~~
______T_D_A_10_7_2_A___
_____________________________________
DEVICE CHARACTERISTICS (continued)
parameter
symbol
min.
typo
max.
unit
V2-16
0
2,0
V
20
V
Standby switch
Switching threshold at Vp = 7,5 to 18 V;
T amb = -40 to + 80 °C
off-voltage
V2-16
3,5
-
=0 V
off-current at V2-16 = 20 V
-12
-
-
200
J1A
1121
-
-
10
/lA
on-voltage
on-current at V2-16
OPERATING CHARACTERISTICS
Vp = 8,5 V; fi = 1 MHz; m = 30%; f m
specified
= 400
parameter
Hz; T amb
= 25 °C; measured
in Fig. 1; unless otherwise
symbol
min.
typo
max.
unit
R.F. input required for S + N/N
V·I
-
1,5
-
/lV
R.F. input required for S + N/N
V·I
-
15
-
J1V
R.F. input required
V·I
-
150
-
J1V
V·I
-
30
-
/lV
R.F. input at THO
V·I
-
500
-
mV
R.F.
V·I
-
700
-
mV
V·I
-
900
-
mV
Change of Vi for 1 dB change
of Vo(af); Vi(ref) = 500 mV
AVj
-
86
-
dB
Change of Vi for 6 dB change
of Vo(af); Vi(ref) = 500 mV
AVi
-
91
-
dB
Vo(af)
-
130
-
mV
Vo(af)
d tot
240
310
390
mV
-
0,5
-
%
R.F. sensitivity
= 6 dB
= 26 dB
for S + N/N = 46 dB
R.F. input at start of a.g.c.
R.F. large signal handling
R.F.
= 3%; m = 80%
input at THO = 3%; m = 30%
input at THO = 10%; m = 30%
A.G.C. range
Output signal
A. F. output voltage at
Vi = 4 /lV; m =80%
A.F. output voltage at Vi = 1 mV
THD at Vi = 1 mV; m
= 500 mV; m = 30%
dtot
-
1
-
%
Signal-to-noise ratio at Vi = 100 mV
(5 + N)/N
-
58
-
dB
Ripple rejection at Vi = 2 mV;
VP(rms) = 100 mV; fp = 100 Hz
(RR = 20 log [Vp/Vo(af)])
RR
-
38
-
dB
THD at Vi
902
= 80%
May
19841 (
___
~l
_______
A_M_rec_ei_ve_rc_irc_uit________________________
T_D_A_1_O_72_A____
symbol
min.
typo
max.
unit
at fi ~ 2 x fif
(X2 if
-
37
-
dB
at fi ~ 3 x fif
parameter
Unwanted signals
Suppression of i.f. whistles at
Vi = 15 }J.V; m = 0% related to
a.f. signal of m = 30%
(X3 if
-
44
-
dB
I.F. suppression at r.f. input
for symmetrical input
(Xif
-
40
-
dB
for asymmetrical input
(Xif
-
40
-
dB
l1(osc)
-
1
-
}J.A
11 (20sc)
-
1,1
-
}J.A
Residual oscillator signal at mixer output
at fosc
at 2 x fosc
APPLICATION INFORMATION
100nF
22
n
16
11
TDA1072A
7Z87701
(1) Capacitor values depend on crystal type.
(2) Coil data: 9 windings of 0,1 mm dia laminated Cu wire on TaKa coil set 7K 199CN; 0 0
Fig. 2 Oscillator circu it using quartz crystal; centre frequency
= 27
I
= 80.
MHz.
(May 1984
903
~
j~~_____________________________________
______T_D_A_10_7_2_A___
APPLICATION INFORMATION (continued)
7Z87703
7Z87702
S+N
THO
N
slN
Vo(af)
(dBV)
V
V
-20
-40
40
l(
\
f..- f-- ...........
""-
-60
~ N
20
40
60
----
80
100
J'\
V
o
'"""120
/
I
/
~
J
6
r-
"""
4
~I
20
....... 1"---
o
I\J
60
~
(%)
S+N
(dB)
'-...
o
20
-
./
THO
40
60
80
100
Vi (dBJlV)
Fig. 4 Total harmonic distortion and (S + N)/N
as functions of r.f. input in the circuit of
Fig. 1; m = 30% for (S + N)/N curve and
m = 80% for THD curve.
Fig.3 A.F. output as a function of d. input
in the circuit of Fig. 1; fi = 1 MHz; fm = 400 Hz;
m = 30%.
7Z87704
10
""'""-
:-....
"-
"\.
THO
(%)
C7-16
"'- ........
'r-..,
~
r--~
"
= 2,2 JlF",
~~=OJlF
r-...
..........
"'\.
....... v
'-
----
""","""
V
"~ -....
.............
0,1
10
20
100
200
1000
2000
Fig. 5 Total harmonic distortion as a function of modulation frequency at Vi
measured in the circuit of Fig. 1 with C7-16(ext) = 0 J.1.F and 2,2 J.1.F.
904
May
19841 (
o
120
Vi (dBJlV)
= 5 mV; m = 80%;
____
~l
_______
A_M_rec_ei_ver_c_irc_uit________________________
T_D_A_1O_7_2_A_____
7Z87705
7Z87706
Vo (af)
./'
(dB)
//
V 1ND
(V)
/
o
l/
.... :...~
,
-10
,\
/
f\
,
-30
\
-40
/
o lL
o
r..
\\
-20
,,/
/
"
'-\
/
/
L
~
'\
-50
40
20
60
80
100
120
0,1
10
fm (kHz)
Vi (dBI.tV)
Fig. 7 Typical frequency response curves from
Fig. 1 showing the effect of filtering as follows:
with Lt. filter;
- ' - ' - '-' -' with a.f. filter;
Fig.6 Indicator driver voltage as a function
of r.f. input in the circuit of Fig. 1.
with i.f. and a.f. filters.
- - - - - -
r--------l
Rgen
vrf
I
56 n
15pF
I
Vae
10nF
50n TT"60P~I ~~
~
"
I"
"
50n
I
I'
390pF
100pF
L!~RIAL _~~B_)__ ~
I
60pF
12
11
7 Z87707
Fig. 8 Car radio application with inductive tuning.
7Z87708
o
sIN 1m J30
Vo(af)
(dBV)
V
20
./
40
%)
V
/"
t:;::Vr-
.........
. . . .1'.
.......
i'-. 1"'--_
r-...
60
..........
o
!
1
20
40
60
-
~
80
100
Vrf (dBIlV)
120
Fig. 9 A.F. output as a function of, r.f. input using the circuit of Fig. 8 with that of Fig. 1.
I
(May 1984
905
______________________________________
~l
______T_D_A_10_7_2_A___
APPLICATION INFORMATION (continued)
o
20
40
V'aew (dB/lV)
:;
V rfu
(dB/lV)
120
V
-----
V
v
7Z87709
V'aeu
(dB/lV)
V
106
./V
/"
100
86
./V
./
80
66
o
20
10
30
40
50
60
70
Vrfw (dB/lV)
Fig. 10 Suppression of cross-modulation as a function of input signal, measured in the circuit of Fig. 8
with the input circuit as shown in Fig. 11. Curve is for Wanted Vo(af)/Unwanted Vo(af) == 20 dB;
Vrfw, Vrfu are signals at the aerial input, V'aew, V'aeu are signals at the unloaded output of the aerial.
Wanted signal (V' aew, V rfw): fi == 1 MHz; f m == 400 Hz; m == 30%.
Unwanted signal (V'aeu, Vrfu): fi
= 900 kHz; fm == 400
Hz; m == 30%.
Effective selectivity of input tuned circuit == 21 dB.
r----'
I
1--+-----+1
I
I
v rfw
v rfu
Vwanted
I
I
v'aew
I v'aeu •
AERIAL
(Fig. 8 ) :
to radio
input circuit
iL- ___ !
Fig. 11 Input circuit to show
cross-modulation suppression
(see Fig. 10).
--..J
Vunwanted
7Z87710
7Z87711
120
V12 (rms)
1/
(mV)
100
II
I
80
1
I
60
I
40
Fig. 12 Oscillator amplitude as a
function of pin 11, 12 impedance
in the circuit of Fig. 8.
20
o
10
0,1
100 200
I Z o12-11I(k,Q)
906
May
19841 (
Jl____
n c
______A_M_re_re_iVi_9_i_rcu_it_______________________
T_DA_1_O_72_A______
7Z87712
S+N
-N-
THD
(%)
(dB)
60
S+N
-N-
\
\
40
VV
1\
o
I -I--"
V
/"
o
~
I'"
4
./
vV
\
20
V
-
___ r-
~
~v
I'-.t--
THD
40
20
60
~~
80
100
V
iJ
Vrf (dBILV)
o
120
Fig. 13 Total harmonic distortion and (5 + N)/N as functions of r.f. input using the circuit of Fig. 8
with that of Fig. 1.
7Z87713
o
~l-/'
~~
II'
~
Ii
I Zf(:~f) I
I'
l
l\
-40
I\,'
1,2,3/
~\
,\\ \
,II
I
\\
/
4[\ ?
1/1/4
-80
-100
1..3·tl3
1,2
\
I
-10
-1
±0,1
10 ""fif (kHz) 100
Fig. 14 Forward transfer impedance as a function of intermediate frequency for filters 1 to 4 shown
in Fig. 15; centre frequency = 455 kHz.
1
(May 1984
907
___T_DA1_072_A_jl~_________________
APPLICATION INFORMATION (continued)
56pF
3kn
56pF
3 kn
56 pF
3 kn
100pF
100pF
3 kn
Fig. 15 I.F. filter variants applied to the circuit of Fig. 1. For filter data, refer to Table 1.
908
May
19841 (
Table 1 Data for I.F. filters shown in Fig. 15. Criterium for adjustment is ZF
fO = 455 kHz). See also Fig. 14.
= "maximum
(optimum selectivity curve at centre frequency
~
unit
4
filter no.
1
2
Coil data
L1
L1
L1
L2
L1
Value of C
3900
430
3900
4700
3900
N1:N2
12: 32
13 : (33 + 66)
15 : 31
29: 29
13: 31
Diameter of Cu
laminated wire
0,09
0,08
0,09
0,08
0,09
O·0
65 (typ.)
50
75
60
75
!~ (:31
;~ ' : 29
•(N1) •(N2)
7V (:31
7XNS-A7518DY
7XNS-A7521AIH
7XNS-A7519DY
Schematic*
of
windings
I
Toko order no.
!~
!V
(:32
•
7 XNS-A7523D Y
3
(<'- 66
.~
.~
L7PES-A0060BTG
»
aQ
i·
~
pF
n
~.
n
c
~.
mm
•
Resonators
Murata type
SFZ455A
SFZ455A
SFZ455A
SFT455B
D (typical value)
4
4
4
6
dB
RG,RL
Bandwidth (-3 dB)
3
3
3
3
kn
4,2
4,2
4,2
4,5
kHz
S9kHz
24
24
24
38
dB
ZI
4,8
3,8
4,2
4,8
kn
°B
ZF
Bandwidth (-3 dB)
57
40
0,70
0,67
0,68
0,68
kn
3,6
3,8
3,6
4,0
kHz
S9kHz
35
31
36
42
dB
S18kHz
52
49
54
64
dB
S27kHz
63
58
66
74
dB
Filter data
~
Q)
-<
co
00
~
-
-
---
---
-
-- _
- - ---
18 (L2)
52 (L1)
-------~L-
----
--
-
----
55
-
* The beginning of an arrow indicates the beginning of a winding; N 1 is always the inner winding, N2 the outer winding.
CD
~
-
---
--
-I
o
»......
o
-..J
I\)
»
____________________________________
~l
______
TD_A_1_0_72_A___
APPLICATION INFORMATION (continued)
standby
switch
Fig. 16 Printed-circuit board component side, showing component layout. For circuit diagram see Fig. 1.
Fig. 17 Printed-circuit board showing track side.
910
May
19841 (
-
VB = +8,5V
:t>
22n
Vp
100kn
3:
470 pF
Ci1
s
VTUN •
i·
~
22n
n
:::;.
2
;:+.
390 pF
IloonF
BC548
2,2kn
10nF
~fosc
Vp
V 1ND
13
12
11
10
TDA1072A
s:
Ql
c.o
00
.j::o
12kn
vp
-<
standby switch
(1) Values of capacitors depend on the selected group of capacitive diodes 88112.
(2) For i. f. filter and coil data refer to Fig. 1.
.L
7Z87716
Fig. 18 Car radio application with capacitive diode tuning and electronic MW/LW switching. The circuit includes pre-stage a.g.c. optimised for
good large-signal handling.
c.o
...a
Vo (af)
lonFI 3,3nFJ; ~
--I
o
»
....
o
~
I\)
»
DEVELOPMENT DATA
TDA1072AT
This data sheet contains advance information and
specifications are subject to change without notice.
AM RECEIVER CIRCUIT
GENERAL DESCRIPTION
The TDA 1072AT integrated AM receiver circuit performs the active and part of the filtering functions of
an AM radio receiver. It is intended for use in mains-fed home receivers and car radios. The circuit can
be used for oscillator frequencies up to 50 MHz and can handle R F signals up to 500 mV. R F radiation
and sensitivity to interference are minimized by an almost symmetrical design. The voltage-controlled
oscillator provides signals with extremely low distortion and high spectral purity over the whole frequency
range even when tuning with variable capacitance diodes. If required, band switching diodes can easily be
applied. Selectivity is obtained using a block filter before the IF amplifier.
Features
•
•
•
•
•
•
•
•
•
•
I nputs protected against damage by static discharge
Gain-controlled R F stage
Double balanced mixer
Separately buffered, voltage-controlled and temperature-compensated oscillator, designed for
simple coils
Gain-controlled I F stage with wide AGe range
Full-wave, balanced envelope detector
Internal generation of AGe voltage with possibility of second-order filtering
Buffered field strength indicator driver with short-circuit protection
AF preamplifier with possibilities for simple AF filtering
Electronic standby switch
QUICK REFERENCE DATA
parameter
conditions
symbol
min.
typo
max.
unit
10
V
Supply voltage range
Vp
7.5
~
Supply current range
Ip
15
-
26
mA
RF input voltage for
S+N/N = 6 dB at m = 30%
VI
-
1.5
-
j.J.V
R F input voltage for 3%
total harmonic distortion
(THO) at m = 80%
VI
-
500
-
mV
AF output voltage with
VI = 2 mV;fl= 1 MHz;
m = 30% and fm = 400 Hz
VO(AF)
-
310
-
mV
-
86
-
dB
-
2.8
-
V
AGe range: change of VI
for 1 dB change of VO(AF)
Field strength indicator
voltage at VI = 500 mV;
R L(9) = 2.7 kn
VIND
PACKAGE OUTLINE
16-lead mini-pack; plastic (S016; SOT109A).
'] (MarCh
1989
913
_____________________________________
J~
______T_D_A_10_7_2_A_T__
Vf
Cosc
l2to440pF
~ if'I
C4
470 pF
~j
1
$ffi
~0.1 ILFI C6
2 to 22 pF
C7
pF
R2
22,Q
O
13
GAIN-
MIXER
Cg..l
10nFT
_oJ
100nF
15
fosc
'+1:
o 0
33 pF C8
clI
optional
band switching
diodes
12
INTERNAL
SUPPLY
VOLTAGES
CONTROLLED
OSCILLATOR t - - - - . t - - - '
A.F.
BALANCED
FULL- WAVE
DETECTOR
STANDBY
SWITCH
INDICATOR
DRIVER
PRE -
AGC
VR (AGC)
-=r-......-----....
TDA1072AT
V2
2
C12
1220nF
3.3 nF
H
standby
switch
C14
C15
Tl00nF
~--c::J----~ Vo(AF)
RL = 1 Mn
+ Vp (pin 13)
7Z87714.1
IF FILTER
(1) Coil data: TOKO sample no. 7XNS-A7523DY; L 1: N1/N2
Filter data: ZF = 700 f2. at R3-4 = 3 kf2.; Z1 = 4.8 kf2..
= 12/32; 00 = 65; Os = 57.
Fig.1 Siock diagram and test circuit (connections shown in broken lines are not part of the test circuit).
914
March
19891 (
Jl___
______A_M_re_ce_ive_rc_ir_cu_it_______________________
TD_A_1_0_72_A_T____
FUNCTIONAL DESCRIPTION
Gain-controlled R F stage and mixer
The differential amplifier in the RF stage employs an AGe negative feedback network to provide a wide
dynamic range. Very good cross-modulation behaviour is achieved by AGe delays at the various signal
stages. Large signals are handled with low distortion and the SIN ratio of small signals is also improved.
Low noise working is achieved in the differential amplifier by using transistors with a low base resistance.
A double balanced mixer provides the I F output to pin 1.
Oscillator
The differential amplifier oscillator is temperature compensated and is suitable for simple coil connection.
The oscillator is voltage-controlled and has little distortion or spurious radiation. It is specially suitable for
electronic tuning using variable capacitance diodes. Band switching diodes can easily be applied using the
stabilized voltage V 11-16. An extra buffered oscillator output is available for driving a synthesizer. If this
is not needed, resistor R L( 10) can be omitted.
Gain-controlled I F amplifier
This amplifier comprises two cascaded, variable-gain differential amplifier stages coupled by a band-pass
filter. Both stages are gain-controlled by the AGe negative feedback network.
~
Detector
c5
The full-wave, balanced envelope detector has very low distortion over a wide dynamic range. The residual
I F carrier is blocked from the signal path by an internal low-pass filter.
I-
z
w
~
g
~
w
o
AF preamplifier
This stage preamplifies the audio frequency output. The amplifier output stage uses an emitter follower
with a series resistor which, together with an external capacitor, provides the required low-pass filtering
for AF signals.
AGC amplifier
The AGe amplifier provides a control voltage which is proportional to the carrier amplitude. Second-order
filtering of the AGe voltage achieves signals with very little distortion, even at low audio frequencies. This
method of filtering also gives a fast AGe settling time which is advantageous for electronic search tuning.
The AGe settling time can be further reduced by using capacitors of smaller value in the external filter.
The AGe voltage is fed to the R F and I F stages via suitable AGe delays. The capacitor at pin 7 can be
omitted for low-cost applications.
Field strength indicator output
A buffered voltage source provides a high-level field strength output signal which has good linearity for
logarithmic input signals over the whole dynamic range. If field strength information is not needed,
RL(9) can be omitted.
'] (
March 1989
915
~,
~l_____________________________________
______T_D_A_10_7_2A_T___
FUNCTIONAL DESCRIPTION (continued)
Standby switch
This switch is primarily intended for AM/FM band switching. During standby mode the oscillator,
mixer and demodulator are switched off.
Short-circuit protection
All pins have short-circuit protection to ground.
RATINGS
Limiting values in accordance with the Absolute Maximum Rating System (lEe 134)
parameter
conditions
Supply voltage
Vp
symbol
min.
max.
unit
V13
-
12
V
V14-15
V14-16
V15-16
V14-16
V15-16
-
10
Vp
Vp
-0.6
-0.6
V
V
V
V
V
I nput current
(pins 14 and 15)
'14-15
-
200
rnA
Total power dissipation*
Ptot
-
300
mW
Operating ambient temperature range
Tamb
T stg
-40
+80
-55
+ 150
°e
oe
T-J
-
+ 125
oe
Input voltage
pins 14-15
pins 14-16
pins 15-16
pins 14-16
pins 15-16
Storage temperature range
Junction temperature
= V13-16
-
-
THERMAL RESISTANCE
From junction to ambient
* Mounted on epoxiprint
916
1(
March 1989
Rthj-a
300 K/W
160 K/W*
~
j~___
T_D_A1_0_7_2A_T_____
_____
AM
__
rec_eiv_er_ci_rcu_it________________________
CHARACTE R ISTICS
Vp = V13-16 = 8.5 V; Tamb = 25 oC; fi = 1 MHz; fm = 400 Hz; m = 30%; flF = 460 kHz; measured in
test circuit of Fig.1; all measurements are with respect to ground (pin 16); unless otherwise specified
min.
typo
Supply voltage (pin 13)
V13
7.5
8.5
10
V
Supply current (pin 13)
113
15
23
27
mA
V14-15
-
Vp/2
-
V
-
5.5
25
-
kn
pF
8
22
-
kn
pF
conditions
max.
unit
symbol
parameter
Supplies
R F stage and mixer
Input voltage (DC value)
R F input impedance at
VI <300j.LV
R F input impedance at
VI> 10 mV
e:(
:E
c..
o
...J
W
>
W
C
-
0
6
0
-
-
kn
pF
Conversion transconductance
before start of AGC
11/ V I
-
6.5
-
mA/V
Maximum I F output voltage,
inductive coupling to pin 1,
(peak-to-peak value)
V1(p-p)
-
5
-
V
DC value of output current
(pin 1) at VI = 0 V
11
-
1.2
-
mA
30
-
dB
VI(rms)
-
500
-
mV
Frequency range
.6.f
0.6
-
60
MHz
Oscillator amplitude
(pins 11 to 12)
(peak-to-peak value)
V11-12(p-p)
-
130
150
mV
External load impedance
R 11-12(ext)
0.5
-
200
kn
External load impedance for
no oscillation
R11-12(ext)
-
-
60
n
e:(
IZ
w
R14-15
C14-15
-
R1
C1
I F output impedance
l-
C
R 14-15
C14-15
AGC range of input stage
RF signal handling capability:
input voltage for THO = 3%
at m = 80% (RMS value)
500
Oscillator
' ] (MarCh 1989
917
Jl______________________________________
_____T_D_A_10_7_2_A_T__
CHARACTERISTICS (continued)
parameter
conditions
symbol
min.
typo
max.
unit
V 11
-
4.2
-
V
111
0
-
5
mA
AVll
-
0.5
-
V
-
V
Ripple rejection at Vp
= 100 mV (RMS value);
fp = 100 Hz
(RR = 20 log [V13/V11])
Source voltage for switching
diodes (6 x VBE)
DC output current (for
switching diodes)
Change of output voltage at
.1111 = 20 mA (switch to
maximum load)
Vp = V13
';;;;9 V
Buffered oscillator output
DC output voltage
V10
-
0.7
Output signal amplitude
(peak-to-peak value)
V1O(p-p)
-
320
-
mV
Output impedance
R10
-
170
-
n
Output current
110(peak)
-
-
-3
mA
DC input voltage
V3-4
-
2
-
V
I F input impedance
R3-4
C3-4
2.4
-
3.0
7
3.9
-
kn
pF
I F input voltage for
TH D = 3% at m = 80%
V3-4
-
90
-
mV
Voltage gain before start
of AGC
V3-4/V6
-
68
-
dB
AGe range of I F stages:
change of V3-4 for 1 dB
change of VO(AF);
V3-4(ref) = 75 mV
AV3-4
-
55
-
dB
AF output voltage at
V3-4(IF) = 50 J.LV
VO(AF)
-
130
-
mV
AF output voltage at
V3-4(IF) = 1 mV
VO(AF)
310
-
mV
AF output impedance (pin 6)
IZol
-
3.5
-
kn
IF, AGC and AF stages
913
March 1989\ (
,Jl___
T_D_A_10_7_2A_T______
______A_M_re_ce_iv_er_cir_cu_it_______________________
CHARACTERISTICS
parameter
conditions
symbol
min.
typo
max.
unit
Output voltage at
VI = 0 mV
RL(9) = 2.7 kll
V9
-
20
150
mV
Output voltage at
VI = 500 mV
R L(9) = 2.7 kll
V9
2.5
2.8
3.1
V
RL(9)
2.7
-
-
kll
V2
V2
12
12
0
3.5
-
-
2
20
-200
10
V
V
JiA
JiA
Indicator driver
Load resistance
Stand by switch
Switching threshold at
Vp=7.5to18V;
Tamb = -40 to + 80 °C
ON-voltage
OFF -vo Itage
ON-current
OFF -cu rrent
V2= OV
V2 = 20 V
~
OPERATING CHARACTERISTICS
IZ
Vp = 8.5 V; fl = 1 MHz; m = 30%; fm
specified
«c
w
~
Il..
o
parameter
>
R F sensitivity
C
..J
W
-
= 400 Hz; Tamb = 25 °C; measured in Fig.1; unless otherwise
conditions
symbol
min.
typo
max.
unit
RF input required for
S+N/N = 6 dB
S+N/N = 26 dB
S+N/N = 46 dB
VI
VI
VI
-
1.5
15
150
-
-
-
JiV
JiV
JiV
RF input at start of AGC
VI
-
30
-
JiV
VI
VI
VI
-
500
700
900
-
mV
mV
mV
W
R F large signal handling
R F input at
THD = 3%; m = 80%
TH D = 3%; m = 30%
THD = 10%; m = 30%
-
1(
-
March 1989
919
~~
______T_D_A_10_7_2_AT___
_____________________________________
CHARACTE R ISTICS (continued)
parameter
conditions
symbol
min.
typo
max.
unit
Vl(ref) = 500 mV
Vl(ref) = 500 mV
AV,
AV,
-
86
91
-
dB
dB
m =80%
VO(AF)
VO(AF)
-
130
310
390
mV
mV
AGC range
Change of V, for
1 dB change of VO(AF)
6 dB change of VO(AF)
-
Output signal
AF output voltage at
V, = 4 JlV
V, = 1 mV
240
-
Total harmonic distortion at
V, = 1 mV
V, = 500 mV
m= 80%
m=30%
d tot
dtot
-
0.5
1
-
%
%
Signa'-to-noise ratio
V, = 100 mV
S+N/N
-
58
-
dB
RR
-
38
-
dB
Suppression of 'F whistles
at V I = 15 Jl V; m = 0%
related to AF signal of
m =30%
at f, ~ 2 x f'F
at f, ~ 3 x f'F
<:X21F
<:X31F
-
37
44
-
-
-
dB
dB
I F suppression at R F input
for symmetrical input
for asymmetrical input
<:XIF
<:XIF
-
40
40
-
Residual oscillator signal
at mixer output
at fosc
at 2 x fosc
I(osc)
I (20sc)
-
1
1.1
-
Ripple rejection at
V, = 2 mV
Vp= 100mV(RMSva'ue)
fp = 100 Hz
(RR = 20 'og [Vp/VO(AF)J)
Unwanted signals
920
March 1989) (
-
-
dB
dB
JlA
JlA
J
AM receiver circuit
TDA1072AT
~~-
APPLICATION INFORMATION
100nF
22
n
16
11
TDA1072AT
7Z87701.1
(1) Capacitor values depend on crystal type.
(2) Coil data: 9 windings of 0.1 mm dia laminated Cu wire on TaKa coil set 7K 199CN; 00 = 80.
Fig.2 Oscillator circuit using quartz crystal; centre frequency
e::(
le::(
= 27
MHz.
C
I2:
S+N
0
0
..J
w
>
w
C
7Z87703 1
7Z877021
w
:;:
c..
vo(AF)
S+N
(dBV)
-40
[7
[7
~
-60
o
\
20
"
40
N
60
/
r- r-- t--
80
100
120
o
4
V
~V
20
................
j
o
2
11\
r--....I-20
vi
THD
40
60
80
100
o
120
Vi (RF) (dBILV)
Vi (RF) (dBILV)
Fig.3 AF output as a function of RF
input in the circuit of Fig.l;
fl = 1 MHz; fm = 400 Hz; m = 30%.
6
VT
1V
40
- r---..~
(%)
S+N
~
60
/
-20
THD
N
(dB)
I
Fig.4 Total harmonic distortion and
S+N/N as functions of R F input in the
circuit of Fig.l; m = 30% for (S+N)/N
curve and m = 80% for THO curve.
1(
March 1989
921
Jl_____________________________________
______T_D_A_10_7_2A_T___
APPLICATION INFORMATION (continued)
7Z877041
10
"
"' I'\.
THD
(%)
.........
"
'\
r-..
r-..",
"
""
C7-16 = 2.2 M:;'\"
~
,
"''\..
~16=OMF
........
r--..
......f----"
......
............
::--....
'"
...............
~
.....-
0.1
100
20
10
200
1000
2000
Fig.5 Total harmonic distortion as a function of modulation frequency at VI = 5 mV; m = 80%; measured
in the circuit of Fig.1 with C7 -16{ext) = 0 f..lF and 2.2 f..lF.
7Z877051
V
V1ND
(V)
I
./
7Z877062
Vo(AF)
(dB)
o
V
... ,
-....~
-10
/
J
/
V
'j'-.
"
\\
-20
,\
\
-30
/
oj
o
~
'\
\\
/
"
-40
I
-50
20
40
60
80
100
120
0.1
f m (kHz)
Vi (RF) (dBMV)
Fig.6 Indicator driver voltage as
a function of R F input in the circuit
of Fig.1.
with I F filter
with AF filter
with I F and AF filter
Fig.7 Typical frequency response
curves from Fig.1 showing the effects
of filtering.
922
March 19891 (
10
,Jl---T-D-A-10_7_2_A_T_____
_______
AM_r_ec_eiv_er_ci_rcu_it_______________________
r--------l
Rgen
V RF
I
560. 15pF
t~ i
,Vae
rj
60pT
II'
10nF
~~
390pF
100pF
~~RIAL"_(-14~B_)__
"
60pF
12
11
lZ81101.1
Fig.8 Car radio application with inductive tuning.
«
«
0
I-
lZ811081
I2
w
2
0..
0
w
...J
0
I ITT
S+N (m=30%)
vo(AF)
(dBV)
20
>
w
/'
0
40
./'
.,/
V
V
~ +-
V
r-
...... ~
" 1'-. r--....
"'"
60
o
20
40
60
r--..... r- ~
80
100
Vi (RF) (dB~V)
120
Fig.9 AF output as a function of RF input using the circuit of Fig.8 with that of Fig.1.
'I (MarCh
1989
923
j~______________________________________
______
TD_A_1_0_72_A_T__
APPLICATION INFORMATION (continued)
o
20
V'aew (dBMV)
40
7 Z8 77 09
V
Vrfu
(dBMV)
120
~
V
V'aeu
(dBMV)
V
106
/"
V
//
100
/
,/
V
86
./
80
o
66
10
20
30
60
50
40
70
Vrfw (dBMV)
Fig.10 Suppression of cross-modulation as a function of input signal, measured in the circuit of Fig.8
with the input circuit as shown in Fig.11. Curve is for wanted VO(AF)!unwanted VO(AF) = 20 dB; Vrfw,
Vrfu are signals at the aerial input, V'aew, V'aeu are signals at the unloaded output of the aerial.
Wanted signal (V'aew, Vrfw): fi = 1 MHz; fm = 400 Hz; m = 30%.
Unwanted signal (V'aeu, Vrfu): fi
= 900 kHz; fm = 400
Hz; m
= 30%.
Effective selectivity of input tuned circuit = 21 dB.
r----'
POWER
SPLITTER
Vwanted
I
I
I
vrfw
v rfu
-r-t---.:...:...=------+I
I
v'aew
v'
aeu ~ to radio
input circuit
(Fig. 8 ) :
I
AERIAL
I
ii - ___ -.JI
Vunwanted
7Z87710
Fig.11 Input circuit to show cross-modulation suppression (see Fig.10).
924
March
19891 (
j
AM receiver circuit
TDA1072AT
~~-
7Z87711 1
120
V12 (rms)
(mV)
II
100
II
I
80
1
II
60
I
40
20
o
0.1
10
100 200
IZo12-11I(kn)
Fig.12 Oscillator amplitude as a function of the impedance at pins 11 and 12 in the circuit of Fig.S.
<
I<
C
IZ
W
~
7Z877121
S+N
r;r-
THO
(%)
(dB)
60
6
\
Q..
0
\
i\
..J
W
>
W
40
C
-
V
a
./
".,.
".-
-
/" ~
~~
4
./
\
20
o
V ....
S+N
-N-
V
V
K~
I"'- ~
THO
-~
I
20
40
60
80
V
/
a
100
120
Vi (RF) (dBj.lV)
Fig.13 Total harmonic distortion and (S+N)/N as functions of RF input using the circuit of Fig.S with
that of Fig.1.
I(MarCh
1989
925
!I
II
APPLICATION INFORMATION (continued)
7Z877131
o
~~
~~
f\
II'
Z21
Z21 (ref)
I
II
I
~
\:,
-40
1,2,3/
,1J
I
\\1\
\\
/
1/1/4
1'3.~3 J
-80
-100
\
-10
1\1,2
41\ ,3
-1
±0.1
1\
10
100
dflF (kHz)
Fig.14 Forward transfer impedance as a function of intermediate frequency for filters 1 to 4 shown in
Fig.14; centre frequency = 455 kHz.
926
March 1989
'I (
J
AM receiver circuit
TDA1072AT
- - 56 pF
3kU
56 pF
3kU
vp
e:{
J;
le:{
56pF
C
IZ
w
:E
0.
0
..J
W
>
w
c
I
vp
v 3 -4
~
100pF
3kU
100pF
3kU
F ig.15 IF fi Iter variants appl ied to the circuit of F ig.1 ; for fi Iter data refer to Table 1.
I
(MarCh 1989
927
:1
,I
CD
N
00
-t
»
"C
(f)fJ)-I
CD
CD
~
s:
~
C')
~
co
CO
CO
fJ)
o
"TI
~ Q)
CD C'"
g.
CD
<
_. ....
-<
to· C')
. !:;
0
~
Q)
+:>'<-h
CD 0
Q)
.,
.-+
filter no.
2
1
4
3
L2
L1
L1
L1
Value of C
3900
430
3900
4700
3900
N1:N2
12: 32
13 : (33 + 66)
15 : 31
29: 29
13 : 31
2
0
0.08
0.09
0.08
0.09
50
75
60
75
Schematic*
of
windings
•12
•
+:>.U:;
CJ1.
Toko order no.
7XNS-A7523DY
CJ1()
Resonators
CD
.0
~
0
c: :E
~ :::J
C')
-.
-< :::J
o-h"TI
_.
II
cP
'" :::::!.
I.-+
N
~.
c:
3
-h
pF
."
•
•
.32
•13
•
•
•
.33=
L7PES-A0060BTG
•15
•
•
•
.31
7XNS-A7518DY
•29
•(N1 )
•
•(N2)
.29
7XNS-A7521 AI H
•13
•
mm
S
»
•
•
0
.31
2
()
0
;.
:::J
7XNS-A7519DY
c:
CD
8:
SFT455B
Murata type
SFZ455A
SFZ455A
SFZ455A
D (typical value)
4
4
4
6
dB
3
kQ
Q
RG,RL
3
3
Q)
.9:
Bandwidth (-3 dB)
4.2
4.2
4.2
4.5
kHz
3
S9kHz
Filter data
24
24
24
38
dB
CD
:::J
en·
ZI
4.8
3.8
4.2
4.8
kQ
°B
ZF
Bandwidth (-3 dB)
57
40
0.70
0.67
0.68
0.68
3.8
3.6
4.0
kHz
dB
.-+
N
"TI
II
3Q)
x
3·
c:
3
0-
"0
.-+
o·
:::J
Q)
:xl
-I
3
c:
fJ)
0
2
65 (typ.)
::.:
CD
.,
.-+
-hfJ)
., fJ)
»
-I
Coil data
0.09
"TI
-h
n
L1
00
CD
:::J
.-+
.,
CD
"tI
r
Diameter of Cu
laminated wire
C')
unit
3.6
18 (L2)
52 (L 1)
55
kQ
S9kHz
35
31
36
42
S18kHz
52
49
54
64
dB
S27kHz
63
58
66
74
dB
* The beginning of an arrow indicates the beginning of a winding; N 1 is always the inner winding. N2 the outer winding.
j
0
»......
0
""
»-t
I\)
DEVELOPMENT DATA
VB~
~
22n
:is:
Vp
100 kn
470 pF
~
n
CD
~.
22n
~.
n
c
;:;:
390 pF
BC548
r
I
100 nF
2.2
kn
10nF
J--.. fosc
Vp
V 1ND
13
12
11
10
TDA1072AT
Vp
s:
standby switch
~
:;r
co
co
(1) Values of capacitors depend on the selected group of capacitive diodes BB 112.
(2) For I F filter and coil data refer to Fig.1.
Fig.18 Car radio application with capacitive diode tuning and electronic MW/LW
switching. The circuit includes pre-stage AGe optimised for good large-signal handling.
e.g
~
3.3nFJ;
r
Vo(AF)
7ZB7715.1
(")
OJ
10nFJ;
--I
o
»
~
o
""""
»--I
I\)
_____________________________________Jl___
T_D_A_1_07_4_A_____
DUAL TANDEM ELECTRONIC POTENTIOMETER CIRCUIT
GENERAL DESCRIPTION
The TOA 1074A is a monolithic integrated circuit designed for use as volume and tone control circuit
in stereo amplifiers. This dual tandem potentiometer IC consists of two ganged pairs of electronic
potentiometers with the eight inputs connected via impedance converters, and the four outputs driving
individual operational amplifiers. The setting of each electronic potentiometer pair is controlled by an
individual d.c. control voltage. The potentiometers operate by current division between the arms of
cross-coupled long-tailed pairs. The current division factor is determined by the level and polarity of
the d.c. control voltage with respect to an externally available reference level of half the supply voltage.
Since the electronic potentiometers are adjusted by a d.c. control voltage, each pair can be controlled
by single linear potentiometers which can be located in any position dictated by the equipment styling.
Since the input and feedback impedances around the operational amplifier gain blocks are external, the
TOA 1074A can performs bass/treble and volume/loudness control. It also can be used as a low-level
fader to control the sound distribution between the front and rear loudspeakers in car radio installations.
Features
•
•
•
•
High impedance inputs to both 'ends' of each electronic potentiometer
Ganged potentiometers track within 0,5 dB
Electronic rejection of supply ripple
Internally generated reference level available externally so that the control voltage can be made to
swing positively and negatively around a well-defined 0 V level
• The operational amplifiers have push-pull outputs for wide voltage swing and low current consumption
• The operational amplifier outputs are current limited to provide output short-circuit protection
• Although designed to operate from a 20 V supply (giving a maximum input and output signal level
of 6 V), the TOA 107 4A can work from a supply as low as 7,5 V with reduced input and output
signal levels
QUICK REFERENCE DATA
Vp
typo
20 V
Supply current (pin 11)
Ip
typo
22 rnA
Input signal voltage (r.m.s. value)
Vi(rms)
max.
6 V
Total harmonic distortion
Vo(rms)
THO
max.
typo
Output noise voltage (r.m.s. value)
Vno(rms)
typo
50 JlV
Control range
~a
typo
110 dB
Cross-talk attenuation (L/R)
typo
80 dB
Ripple rejection (100 Hz)
act
a 100
typo
46 dB
Tracking of ganged potentiometers
~Gv
typo
0,5 dB
Supply voltage range
Vp
Supply voltage (pin 11)
Output signal voltage (r.m.s. value)
Operating ambient temperature range
6 V
0,05 %
7,5 to 23 V
-30 to + 80 °C
Tamb
PACKAGE OUTLINE
18-lead 01 L; plastic (SOT102).
"I
(December 1982
931
_____________________________________
~l
______
TD_A_1_07_4_A___
100 nF
I
Vp = 20V
18
f
11
100!1F
(25V)
1
+
+
V ref
Cj
VjlA~
+
Vp/2
Zl
= Vref
Zl
Cj
+
I--+- Vj 2A
(R G)
(RG)
Co
Vo lA+--j +
(R L)
Cj
VjlB~
+
Cj
Zl
+ ~Vj2B
(RG)
(R G)
Co
Vj lB
+-1
+
(R L)
TDA1074A
7Z87196
Fig. 1 Block diagram and basic external components; Ic1 (at pin 9) and Ic2 (at pin 10) are control input currents;V c 1 (at pin 9) and Vc2 (at pin 10) are control input voltages with respect to Vref = Vp/2
at pin 8; Z1 = Z2 = Z3 = Z4 = 22 kn; the input generator resistance RG = 60 n; the output load
resistance R L = 4,7 kn; the coupling capacitors at the inputs and outputs are Ci = 2,2 fJ.F and Co = 10 fJ.F
respectively.
932
December 1982
(
l___
Dual tandem electronic potentiometer circuit
T_D_A_1_07_4_A____
RATINGS
Limiting values in accordance with the Absolute Maximum System (I EC 134)
Supply voltage (pin 11)
Vp
max.
23 V
Control voltages (pins 9 and 10)
± Vc 1; ± Vc2
max.
1 V
Input voltage ranges (with respect to pin 18)
at pins 3, 4, 5, 6, 13, 14, 15, 16
o to
Vi
Total power dissipation
Storage temperature range
Ptot
T stg
Operating ambient temperature range
Tamb
max.
Vp V
800 mW
-55 to + 150 0C
-30 to + 80 0C
THERMAL RESISTANCE
From crystal to ambient
80 K/W
Rth cr-a
REMARK
The difference between the TDA 1074 and its successor the TDA 1074A is shown in Fig. 2 as the
different component configuration at pin 8.
TDA1074
8
TDA1074A
8
15kU
Fig. 2 Component configuration at pin 8 showing the
difference between the TDA1074 and the TDA1074A.
'I
(December 1982
933
~1
Jl_____________________________________
______T_D_A_10_7_4_A___
APPLICATION INFORMATION
Treble and bass control circuit
Vp = 20 V; Tamb = 25 oC; measured in Fig. 3; RG = 60 U; RL > 4,7 kU; CL
a linear frequency response (V c1 = V c2 = 0 V); unless otherwise specified
parameter
symbol
min.
typo
max.
unit
Supply current (without load)
Ip
14
22
30
mA
Frequency response (-1 dB)
Vc1 = Vc2 = 0 V
f
10
-
20000
Hz
Voltage gain at linear frequency
response (V c1 = V c2 = 0 V)
Gv *
-
0
-
dB
Gain variation at f = 1 kHz
at maximum bass/treble boost or
cut at ± Vc1 = ± Vc2 = 120 mV
AG v *
-
±1
-
dB
Bass boost at 40 Hz (ref. 1 kHz)
Vc2 = 120 mV
-
17,5
-
dB
Bass cut at 40 Hz (ref. 1 kHz)
-Vc2 = 120 mV
-
17,5
-
dB
Treble boost at 16 kHz (ref. 1 kHz)
Vc1 = 120 mV
-
16
-
dB
Treble cut at 16 kHz (ref. 1 kHz)
-Vc1 = 120 mV
-
16
-
dB
0,002
-
%
0,005
-
%
Total harmonic distortion
at Vo(rms) = 300 mV
f = 1 kHz (measured selectively).
f = 20 Hz to 20 kHz
THO
-
at Vo(rms) = 5 V
f = 1 kHz
THO
-
0,015
0,1
%
f = 20 Hz to 20 kHz
THO
-
0,05
0,1
%
Signal level at THO = 0,7%
(input and output)
Vi; o(rms)
5,5
6,2
-
V
Power bandwidth at reference
level Vo(rms) = 5 V (-3 dB);
THO = 0,1%
B
-
40
-
kHz
Output noise voltages
signal plus noise (r.m.s. value);
f = 20 Hz to 20 kHz
Vno(rms)
-
75
-
JlV
Vno(m)
-
160
230
JlV
noise (peak value); weighted to
DIN 45405; CCITT filter
* Gv=Vo/Vi·
934
< 30 pF; f = 1 kHz; with
December 1982
(
THO
l____
Dual tandem electronic potentiometer circuit
TD_A_1_0_7_4A______
Treble and bass control circuit
parameter
symbol
min.
typo
act
act
-
-
Control voltage cross-talk to
the outputs at f = 1 kHz;
V c 1(rms) = V c2(rms) = 1 mV
-act
Ripple rejection at f = 100 Hz;
VP(rms) < 200 mV
a1QO
Cross-talk attenuation (stereo)
f = 1 kHz
f
= 20
Hz to 20 kHz
max.
unit
86
-
dB
80
-
dB
-
20
-
dB
-
46
-
dB
Vp (+20V)
470 kn
470 kn
lin.
lin.
14V)
10
1A treble (left)
1 B treble (right)
2A bass (left)
2B bass (right)
Vi 1A
(R G )
~Ir-~~~r-~~~~~------------, r------------r_+---~__i
inputs
outputs to
power
amplifier
(4V)
7Z87195
Fig. 3 Application diagram for treble and bass control.
I
(December 1982
936
jl~___________________________________
_____T_D_A_10_7_4_A___
APPLICATION INFORMATION (continued)
7Z87185
20 r-..
Gv
I""-
-
(dB)
10
--r-. r-
~~
-.......;::::
" , ~~
~"""
~~~
~V
L..-f-
J
I-- f·..•.. -
VV
V
-20
I---
V--
t;ebl'e
""bass
r-
I---
-10
--
........ 1'-
~
-~;:: I::--
to--
_I-f-
........ ~ I:-- t-t~~~
b---
~
--
I-'
1
20
f (Hz)
Fig.4 Frequency response curves; voltage gain (treble and bass) as a function of frequency.
7Z87186
20
Gv
V
(dB)
10
V
I.-
J
II
II
I
V
I
o
1/
~l
f-- f--
-l.-V
-50
o
50
L~U
100
V e2 (mV)
Fig.5 Control curve; voltage
gain (bass) as a function of
the control voltage (V c2);
f = 40 Hz.
936
December
10
J......- l--
V
/
L
-10
/
-20
-150 -100
vV'
/
/
-10
7Z87187
20
19821 (
150
--
-20
-150 -100
V
-50
o
50
100
Ve1 (mV)
Fig. 6 Control curve; voltage
gain (treble) as a function of
the control voltage (V c1);
f=16kHz.
150
l____
Dual tandem electronic potentiometer circuit
T_D_A_10_7_4_A_____
7Z84087
+20
k:1..o!~
.Y:Y:: V~
20 log Gv
7.YX WI!
(dB)
1
r/v VI'!
+10
curve no.
value of R
1
3
10 kn
100 kS1
220 kn
4
470 kn
2 3 4/5
V
/7 VL,j 17
r) /.
rz '~ V 1/
Iho ... 17
2
II
~v
v~
~W
1...V
V
V
-10
5
1 Mn
/'1'1
~'V
~I/i/
'I
1 VJ 77
l,f
1
~L. ~...-
-20 ~~f-
o
0,5
Fig.7 Voltage gain (G v = Vo/Vi) control curves as a function of the angle of rotation (ex) of a linear
potentiometer (R); for curve numbers see table above; f = 40 Hz to 16 kHz.
Fig. 8 Circuit diagram for
measuring curves in Fig. 7.
7Z84088,1
7Z87188
8
Vo(rms)
(V)
/
l
./
6
V
/
/
4
/
V
o
I
I
o
/
10
20
Vp (V)
30
Fig.9 Output signal level as a function of Vp;
THD = 0,7%; f = 1 kHz; Vc1 = Vc2 = 0 V.
1
(December 1982
937
jl~___________________________________
______
TD_A_1_07_4_A___
APPLICATION INFORMATION (continued)
7Z87189
0,2
THO
(%)
0,1
1<2..\<.~~~
o --~
o
........
-~
--
....
1/
~
j)
~ I--""
468
Vo(rms) (V)
Fig. 10 Total harmonic distortion as a function of the output level; Vp = 20 V; RL
Vcl = Vc2 = 0 V (linear, Gvtot = 1 ). - - - f = 1 kHz; - - - - f = 20 kHz.
= 4,7 kQ;
7Z87190
8
Vo(rms)
(V)
6
f-- --
\
I-
!\
4
-3dB
2
o
0,1
10
f (kHz)
100
Fig. 11 Power bandwidth at THD = 0,1%; reference level is 5 V (r.m.s.).
7Z8719 1
100
Cl'ct
(dB)
90
'-
~
f-'"
80
---
70
60
50
10
Fig. 12 Cross-talk as a function of frequency; linear treble/bass setting (V c1
RG =60 Q; RL =4,7 kQ.
938
December 19821 (
f (Hz)
= V c2 = 0 V); Vi = 5 V;
l____
Dual tandem electronic potentiometer circuit
T_DA_1_0_7_4A
______
Application recommendations
1. If one or more electronic potentiometers in an IC are not used, the following is recommended:
a. Unused signal inputs of an electronic potentiometer should be connected to the associated output,
e.g. pins 3 and 4 to pin 2.
b. Unused control voltage inputs should be connected directly to pin 8 (V ref).
2. Where more than one TDA 1074A IC are used in an application, pins 1 can be connected together;
however, pins 8(V ref) may not be connected together directly.
3.
Additional circuitry for limiting the frequency response in the ultrasonic range.
from pin
7 (12)
1
12
kn
4 (15) 1 - - - - - - - - _ - - - - 4
33
TDA1074A
nF
2 (17)
t---.--_--+---+~
output
3 (16) t-----------<>------+.--.l
7Z87193
(1) f -3 dB = 110kHz at linear setting
Fig. 13 Circuit diagram for frequency response limiting.
4. Alternative circuitry for limiting the gain of the treble control circuit in the ultrasonic range.
to pin
4 (15)
Vo
1,8nF RS1
Vi -+-111--+___-~ t--l_J-1>-----.--t---I 5 (14)
TDA1074A
J--.----...----<~_I
1,8nF
7 (12)
RS2
'-------------16(13)
7Z87194
For RS1 = RS2 = 3,3 kQ; f -3 dB == 1 MHz at linear setting
For RS1 = RS2 = 0 Q; f-3 dB == 100 kHz at linear setting
Fig. 14 Circuit diagram for limiting gain of treble control circuit.
1(
December 1982
939
TDA1510
TDA1510A
24 W BTL OR 2 x 12 W STEREO CAR RADIO POWER AMPLIFIER
GENERAL DESCRIPTION
The TDA 151 O/TDA 151 OA is a class-B integrated output amplifier encapsulated in a 13-lead single
in-line (SI Ll plastic power package. Developed primarily for car radio application, the device can also
be used to drive low impedance loads (down to 1,6 nl. With a supply voltage (Vpl of 14,4 V, an output
power of 24 W can be delivered into a 4 n Bridge Tied Load (BTL), or when used as a stereo amplifier,
2 x 12 W into 2 n or 2 x 7 W into 4 n.
Features
• Flexibility - stereo as well as mono BTL
• Low offset voltage at the output
(important for BTU
• Load dump protection
• A.C. short-circuit-safe to ground
• Low number, small sized external components
• Internal limiting of bandwidth for high frequencies
•
•
•
•
•
•
High output power
Large useable gain variation
Good ripple rejection
Thermal protection
Low stand-by current possibility
High reliability
QUICK REFERENCE DATA
parameter
conditions
symbol
min.
Vp
Vp
typo
max.
unit
6,0
14,4
-
-
18,0
28,0
V
V
Vp
-
-
45,0
V
IORM
Itot
-
-
4,0
A
Total quiescent current
-
75
120
mA
Stand -by cu rrent
Isb
-
-
2
mA
Iso
0,15
0,35
0,80
mA
IZII
1
-
-
Mn
Supply voltage range:
operating
non-operating
non-operating, load
dump protection
Repetitive peak output
current
Switch-on current
Input impedance
pins 1,2,
12 and 13
Storage temperature range
T stg
-65
Crystal temperature
Tc
-
+ 150
°C
150
°C
PACKAGE OUTLINES
TDA 1510: 13-lead SI L-bent-to-DI L; plastic power (SOT141 Bl.
TDA 151 OA: 13-lead SI L-bent-to-DI L; plastic power (SOT141 Cl.
1(June
1987
941
TDA1510
TDA1510A
6
8
r-----~------+-----~------~----------------~----+_------~--~10
11
3
12
~-+--+---o
7Z86843
Fig. 1 Functional diagram; heavy lines indicate signal paths.
942
June
19871 (
13
TDA1510
TDA1510A
24 W BTL or 2 x 12 W stereo car
radio power amplifier
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
parameter
Supply voltage:
operating
non-operating
non-operating,
load dump protection
Peak output current
Total power dissipation
Storage temperature range
Crystal temperature
conditions
symbol
min.
max.
unit
pin 10
Vp
Vp
-
18
28
V
V
during 50 ms
Vp
10M
Ptot
T stg
Tc
-
-
45
6
V
A
-65
-
+ 150
+ 150
°C
°C
see Fig. 2
7Z86577 1
20
Ptot
(W)
16
.....
12
t--....
. . . . J'..
\
"I'-..
r--....
8
..........
I'Z.~/Wr-
f"
1"'-1"-0.
f'
infinite
Rth h - a
I
1'--"
f2.,.K/W
r- ~eatsink_ r-r-
"~
\
f',
1'""-
4
,
f\
I'-- ~ "- f"...J\
.....1"-'
o
-20
o
20
~
40
60
80
100
120
140
160
Tamb (oC)
(a)
lZ968151
20
Ptot
(W)
16
12
I'-...
. . . . 1'--
" ."",r--...
.........
. . . . 1'--
8
r--....
,
.....
0>
~~
~,
infinite
heatsink
~,
~20 k -
Hz
Input impedance
note 4
IZil
1
-
-
Mn
Rs= on
RS = 10 kn
RS=10kn;
according to
IEC 179 curve A
Vn (rms)
Vn (rms)
-
0,2
0,35
0,8
mV
mV
Vn (rms)
-
0,25
-
mV
f = 100 Hz; note 5
SVRR
42
50
-
dB
I~V5-91
-
2
50
mV
B
-
30 to>40k
-
Hz
Noise output voltage
(r.m.s. value)
Supply voltage ripple
rejection
f = 20 Hz to
20 kHz
D.C. output offset
voltage between
channels
Power bandwidth
-1 dB;
d tot = 0,5%
I (June
1987
945
l
TDA1510
TDA1510A
_________________________________________
A.C. CHARACTERISTICS (continued)
parameter
conditions
symbol
min.
typo
max.
unit
Vp = 13,2 V
d tot = 0,5%
d tot = 10%
Po
Po
-
4,5
6,0
-
W
W
Vp = 14,4 V
d tot = 0,5%
d tot = 10%
Po
Po
4,5
6,0
5,5
7,0
-
W
W
Vp=13,2V
d tot = 0,5%
d tot = 10%
Po
Po.
-
7,5
10,0
Vp=14,4V
d tot = 0,5%
d tot = 10%
Po
Po
7,75
10,0
9,0
12,0
-
W
W
notes 6, 8 and 9
RL =4n
Vp=14,4V
d tot = 10%
Po
-
6
-
W
notes 3 and 6
-3dB
fr
-
40 to
-
Hz
note 5
f = 1 kHz
SVRR
-
50
-
dB
Channel separation
RS = 10 kn;
f = 1 kHz
a
40
50
-
dB
Closed loop voltage gain
note 7
Gc
39,5
40,0
40,5
dB
f = 20 Hz to
20 kHz;
RS =on
RS = 10 kn
RS = 10 kn;
according to
I EC179 curve A
Vn(rms)
Vn(rms)
-
0,15
0,25
-
-
mV
mV
Vn(rms)
-
0,2
-
mV
Stereo application
Output power; with
bootstrap
note 6;
RL =4n
RL = 2n
Output power; without
bootstrap
Frequency response
Supply voltage ripple
rejection
Noise output voltage
(r.m.s. value)
946
June 1987
I(
-
-
> 20 k
W
W
TDA1510
TDA1510A
24 W BTL or 2 x 12 W stereo car
radio power amplifier
Notes to the characteristics
1. If Vl1
> V10 then 111 must be < 10 mAo
2. Closed loop voltage gain can be chosen between 32 and 56 dB (BTL), and is determined by external
components.
3. Frequency response externally fixed.
4. The input impedance in the test circuit (Fig. 3) is typo 100 kil.
5. Supply voltage ripple rejection measured with a source impedance of 0
amplitude 2 V).
on (maximum ripple
6. Output power is measured directly at the output pins of the IC.
7. Closed loop voltage gain can be chosen between 26 and 50 dB (stereo), and is determined by external
components.
8. A resistor of 56 kil between pins 3 and 7 is required for symmetrical clipping.
9. Without bootstrap the 100 JlF capacitor between pins 5 and 6 and the 100 JlF capacitor between
pins 8 and 9 can be omitted. Pins 6 and 8 connected to pin 10.
1(June
1987
947
l_ __
TDA1510
TDA1510A
APPLICATION INFORMATION
100kU
100kU
47
/tF
+
stand-by switch
J;
,+
$(1)
3
J;;
TDA1510
TDA1510A
lZ89091.5
(1) belongs to power supply
Fig.3 Test and application circuit; Bridge Tied Load (BTL).
100kU
100 kD.
$
WP
0-11--+-1----1
TDA1510
TDA1510A
8
+
100kU
100/tF
100/tF
+
RL
RL
100kU
0,1
/tF
4,7 U
lZ89092.4
(1) belongs to power supply
Fig.4 Test and application circuit; stereo mode.
948
June 1987
J(
Vs
+
I
(1)
,I
I
,
I
ill'
Philips Components - a worldwide company
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Philippines: PHILIPS INDUSTRIAL DEV. INC., 2246 Pasong
Tamo, PO. Box 911, Makati Comm. Centre,
MAKATf-RIZAL3116, Tel. (02) 868951 to 59.
Portugal: PHILIPS PORTUGUESA SAR.L., Av. Eng. Duarte
Pacheco 6, 1009 LlSBOA Codex, Tel. (019) 6831 2"
Singapore: PHILIPS SINGAPORE, PTE LTD., Components Div.,
Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. 3502000.
South Africa: SA PHILIPS PTY LTD. Components Division,
JOHANNESBURG 2000, P.O. Box 7430.
Spain: PHILIPS COMPONENTS, Balmes 22, 08007
BARCELONA, Tel. (03) 3016312.
Sweden: PHILIPS COMPONENTS, A.B., Tegeluddsvagen 1,
S-11584 STOCKHOLM, Tel. (0)8-7821 000.
Switzerland: PHILIPS A.G., Components Dept.,
Allmendstrasse 140-142, CH-8027 ZURICH,
Tel. (01)488221"
Taiwan: PHILIPS TAIWAN LTD., 150 Tun Hua North Road,
P.O. Box 22978, TAIPEI, Taiwan, Tel. (02) 71 20500.
Thailand: PHILIPS ELECTRICAL CO. OFTHAILAND LTD.,
283 Silom Road, P.O. Box 961, BANGKOK,
Tel. (02) 233-6330-9.
Turkey: TURK PHILIPS TICARET A.S., Philips
Components,Talatpasa Cad. No.5, 80640
LEVENTIISTANBUL, Tel. (01) 1792770.
United Kingdom: PHILIPS COMPONENTS LTD., Mullard
House, Torrington Place, LONDON WC1 E 7HD,
Tel. (01) 5806633.
United States: (Colour picture tubes - Monochrome & Colour
Display Tubes) PHILIPS DISPLAY COMPONENTS
COMPANY, 1600 Huron' Parkway, P.O. box 963, ANN
ARBOR, Michigan 48106, Tel. 313/996-9400.
(lC Products) SIGNETICS CORPORATION, 811 EastArques
Avenue, SUNNYVALE, CA 94088-3409, Tel. (408) 991-2000.
(passive Components, Discrete Semiconductors, Materials
and Professional Components) PHILIPS COMPONENTS,
Discrete Products Division, 2001 West Blue Heron Blvd.,
P.O. Box 10330, RIVIERA BEACH, Florida 33404,
Tel. (407) 881-3200.
Uruguay: PHILIPS COMPONENTS, Coronel Mora 433,
MONTEVIDEO, Tel. (02) 70-4044.
Venezuela: MAGNETICA SA, Calle 6, Ed. Las Tres Jotas,
CARACAS 1074A. App. Post. 78117, Tel. (02) 2417509.
Zimbabwe: PHILIPS ELECTRICAL (PVT) LTD., 62 Mutare Road,
HARARE, P.O. Box 994, Tel. 47211.
For all other countries apply to: Philips Components Division,
International Business Relations, P.o,. Box 218,5600
MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl
AS74
© Philips Export B.V.
1989
All rights are. reserved. Reproduction in whole or in part is
prohibited without the prior written consent of the copyright
owner.
The information presented in this document does not form part
of any quotation or contract, is believed to be accurate and
reliable and may be changed without notice. No liability will be
accepted by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license under
patent- or 9ther industrial or intellectual property riqhts.
Printed in The Netherlands
9398 16450011
PllilillS CDmpDnents
PHILIPS
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:07:27 13:49:07-08:00 Modify Date : 2017:07:27 17:16:24-07:00 Metadata Date : 2017:07:27 17:16:24-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:810bcd81-e920-e646-b955-569dba8423f5 Instance ID : uuid:88b61695-6b67-a244-a817-029f74d884eb Page Layout : SinglePage Page Mode : UseNone Page Count : 954EXIF Metadata provided by EXIF.tools