1990_SEEQ_Data_Book 1990 SEEQ Data Book
User Manual: 1990_SEEQ_Data_Book
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seeQ
EEPROMs
FLASH
EPROMs
DATACOM
EEPLD
MILITARY
.
RELIABILITY
APPLICATIONS
GENERAL INFORMATION
seeQ
Technology,lncorporated - - - - - - -
ii
Table of Contents
EEPROMS
EEPROMS (Electrically Erasable Programmable Read Only Memories)
EEPROM Cross Reference ............................................................................................................... 1-1
EEPROM Replacement Chart. .......................................................................................................... 1-2
52B13/52B13H
52B33/52B33H
2804A
2816A12816AH
5516A15516AH
2817A12817AH
5517A
2864/2864H
28C64
28C65
28C256
28C64A
28C256K
36C16/32
38C16/32
Modules Q/E28C010
16K Latched .......................................................................... 1-3
64K Latched, 10K cycles/byte ............................................. 1-11
4K Latched & Timed, 10K cycles/byte ................................. 1-19
16K Latched & Timed, 10K cycles/byte ............................... 1-25
16K Latched & Timed, 1M cycles/byte ................................ 1-25
16K Latched & Timed, rdy/busy, 10K cycles/byte ............... 1-31
16K Latched & Ti med, rdy/busy, 1M cycles/byte ................. 1-31
64K Latched & Timed, rdy/busy ........................................... 1-37
64K CMOS Page Mode ....................................................... 1-43
64K CMOS Page Mode (W/Rdy/Busy) ................................ 1-51
256K CMOS Page Mode ..................................................... 1-59
High Speed CMOS 64K EEPROM ...................................... 1-67
256K CMOS Page Mode, 1K cycles ................................... 1-69
High Speed CMOS Bipolar PROM Replacement ................ 1-77
High Speed CMOS EEPROM .............................................. 1-83
Timer E2 ............................................................................... 1-89
FLASH
Flash EEPROM Alternate Source
47F512
48F512
47F010
48F010
KT48
............................................................................................... 2-1
512K CMOS FLASH EPROM ................................................ 2-3
512K CMOS FLASH EEPROM ........................................... 2-13
1024K CMOS FLASH EPROM ............................................ 2-25
1024K CMOS FLASH EEPROM ......................................... 2-35
Flash EEPROM PROGRAMMER ....................................... 2-47
EPROMS
EPROMS (Erasable Programmable Read Only Memories)
EPROM Alternate Source
2764
27128
27C256
............................................................................................... 3-1
64K ........................................................................................ 3-3
128K ...................................................................................... 3-3
256K CMOS ......................................................................... 3-11
DATA COM
DATA COMMUNICATIONS
8003
8020
8023A
8005
83C92
EasyLAN
seeG
Ethernet Data Link Controller ............................................... .4-1
Manchester Code Converter ............................................... 4-13
Manchester Code Converter ................................................ 4-27
Advanced Ethernet Data Link Controller ............................ 4-43
Ethernet Transceiver ........................................................... 4-83
LAN Development Kit .......................................................... 4-85
Technology, Incorporated
iii
EEPLD
EEPLD Cross Reference
20RA10Z
26V12H
..........................................................................................................5-1
Registered Asynchronous CMOS EEPLD ............................ 5-3
Versatile High Speed CMOS EEPLD .................................. 5-21
MILITARY
Military Standard - 883 Class B Compliant Product Processing ...................................................... 6-1
EEPROMs
M52B13/M52B13H
E52B 13/E52B13H
M52B33/M52B33H
E52B33/E5233H
M2816A1E2816A
M2817A1E2817A
M2864/2864H-E2864/2864H
M28C64/E28C64
M28C65/E28C65
M28C256/E28C256
M28C256A
M28HC256
M36C16/M36C32
E36C16/E36C32
M38C16/M38C32
E38C 16/E38C32
Module M28C01 0
M28C010
16K Latched .......................................................................... 6-7
16K Latched, (-40° to 85°C) .................................................. 6-7
64K Latched ........................................................................ 6-15
64K Latched, (-40° to 85°C) ................................................ 6-15
16K Latched & Timed .......................................................... 6-21
16K Latched & Timed, rdy/busy pin ..................................... 6-27
64K Latched and Timed, rdy/busy pin ................................. 6-33
64K CMOS Latched & Timed .............................................. 6-39
64K CMOS Page Mode, Latched & Timed rdy,busy pin ...... 6-47
256K CMOS Page Mode, Latched & Timed ........................ 6-55
256K CMOS Page Mode SWP Latched and Timed ............ 6-63
256K CMOS High Speed, SWP, Latched and Timed .......... 6-73
High Speed CMOS Bipolar PROM Replacement ................ 6-83
High Speed CMOS Bipolar PROM Replacement ................ 6-83
High Speed CMOS .............................................................. 6-89
High Speed CMOS .............................................................. 6-89
1024K Electrically Erasable PROM ..................................... 6-95
1024K High Speed EEPROM ............................................ 6-1 03
EPROMs
M2764
E2764
M27128
E27128
M27C256
E27C256
82005
82025
86063
64K .................................................................................... 6-113
64K (-40° to 85°C) ............................................................ 6-113
128K .................................................................................. 6-113
128K (-40° to 85°C) .......................................................... 6-113
256K CMOS ...................................................................... 6-121
256K CMOS (-40° to 85°C) ............................................... 6-121
DESC SMD-Compliant 64K UV EPROM ........................... 6-129
DESC SMD-Compliant 122K UV EPROM ......................... 6-133
DESC SMD-Compliant 256K CMOS UV EPROM ............. 6-137
FLASH
E/M47F512
E/M48F512
E/M47F010
E/M48F010
512K CMOS FLASH EPROM ............................................ 6-141
512KCMOSFLASH EEPROM ........................................... 6-151
1024K CMOS FLASH EPROM .......................................... 6-163
1024K CMOS FLASH EEPROM ....................................... 6-173
EEPLD
M20RA10Z
eeeQ
Registered Asynchronous CMOS EEPLD ......................... 6-185
Technology, Incorporated
iv
RELIABILITY
SEEO EEPROM Reliability Report .............................................................................................. 7-1
Radiation and MOS Non-Volatile Memories .................................................................................... 7-7
Memory Products Reliability Note 1 ............................................................................................. 7 -11
APPLICA TIONS
Microprocessor Interfacing With
SEEO's Latched EEPROM ................................................. 8-1
Interfacing The 8003 EDLC@To A 16-Bit Bus ..................... 8-11
DMA Interconnection To The 8003 EDLO~ ......................... 8-19
8005 Advanced EDLC@ Users Guide .................................. 8-27
EEPROM Interfacing ........................................................... 8-49
Software Downline Load Using
SEEO's CMOS EEPROMs ............................................... 8-65
Power-Up/Down With SEEO's EEPROM ............................ 8-73
Power Fail Protection With SEEO's CMOS EEPROMs ....... 8-79
EEPROM As A Substitute For Bubble Memory ................... 8-85
Using High Speed CMOS EEPROMS With
High Performance Microprocessors ................................. 8-91
EEPLDs Interface IBM PC BUS With The EDLC@ 8003 .... 8-105
Providing Switched Vpp to the 48F512, 48F010 ................ 8-137
Note 2
Note 5
Note 6
Note 7
Note 8
Note 9
Note 10
Note 11
Note 24
Note 27
Note 28
Note 29
GENERAL INFORMATION
Thermal Resistance ........................................................................................................................ 9-1
Packaging Information .................................................................................................................... 9-1
Package Diagrams ..........................................................................................................................9-2
SEEO Die Sales ............................................................................................................................ 9-32
Bonding Diagrams ........................................................................................................................ 9-34
Domestic Sales/Rep. Office Listing ............................................................................................... 9-47
Distributor Listing .......................................................................................................................... 9-47
International Sales/Rep. Office Listing .......................................................................................... 9-48
seeQ
Technology, Incorporated
v
vi
seeQ
DATA BOOK
Welcome to SEEQ's 1990 Data Book.
Featured in this Data Book are the latest specifications on our renowned full featured
EEPROMs and Flash EEPROMS. As you will see, SEEQ continues to lead the industry in
reprogrammable non-volatile memory density, speed, and low cost. We have also included
information on a new development board for SEEQ's powerful Ethernet data communications components.
SEEQ products are available in standard plastic or ceramic DIP and PGA packages. In
surface mount packages, SEEQ offers LCC, PLCC, flatpack, sOle. SEEQ also offers unencapsulated die.
For pricing and delivery information call your nearest SEEQ sales office, representative, or
distributor --listed in the back ofthis book. A postage paid business reply card is also included
for your convenience.
Thank you for your interest in SEEQ,
J. Daniel McCranie
Chairman and President
seeQ
Technology, Incorporated - - - - - - - - - - - - - - - - - - -
vii
viii
Product Previews contain information on products under development. These specifications may be changed at any time, without notice.
,Advanced Data Sheets contain target product specifications which are subject to change
upon device characterization over the full specified temperature range. These specifications
may be changed at any time, without notice.
Preliminary Data Sheets contain minimum and maximum limits specified over the full
temperature range based upon initial production device characterization. These specifications may be changed at any time, without notice.
Additional copies of this manual or other SEEQ literature may be obtained from:
SEEQ Technology Incorporated
Literature Department
1849 Fortune Drive
San Jose, CA 95131
The following are trademarks of SEEQ Technology and may only be used to identify SEEQ
products:
SEEQ®
Silicon Signature®
EDLC®
DiTrace®
MCCTM
Q CeWM
SEEQ-LANTM
Assembly location: Military products are assembled atSEEO's offshore (Korea, Hong Kong) and stateside assembly plants. The assembly plants are identified
by backside marking. The markings used are: Korea, Hong Kong, U.S.A.
Applications for any integrated circuits contained in this publication are for illustration purposes only and SEEO makes no representation or warranty that such
applications will be suitable for the use specified.
Circuit diagrams are included as a means of illustrating typical applications, and complete information for construction purposes is not necessarily given. The
information presented here has been carefully checked, and is believed to be entirely reliable, but no responsibility is assumed for inaccuracies. Furthermore,
no responsibility is assumed by SEEO Technology, Inc., for use; not for any infringements of patents or other rights of third parties, which may result from its
use. No license is granted by implication, or otherwise, under any patent or patent rights of SEEO Technology, Inc.
ProductsofSEEO may notbe used as critical components in Life Support Systems without the express written authorization ofthe Presidentand Vice-President
of Ouality/Reliability of SEEO Technology. Inc.
A critical component is any component whose failure to perform its intended function, could possibly lead to loss of life, or bodily harm.
Life Support Systems that may Include but are not necessarily limited to:
1) Surgical implants In a human body,
2) Equipment used to sustain human life, or
3) Equipment used to monitor and/or measure human body conditions.
Product warrantles,lot acceptance guarantees, warranty periods and limitation of obligation underthosewarranties and guarantees for all products
manufactured by SEEQ Technology, Incorporated are defined In SEEQ specification OG100020 "Warranty Procedure".
SEEO Technology makes no waranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does
it make a commitment to update the information contained herein.
SEEO retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
A "For Reference Only" specification on a purchase order denotes the designated specifications is for reference by the customer and is not invoked on the
manufacturer.
seeQ
Technology,lncorporated
ix
x
SEEQ Technology
Product Selection Guide
4K EEPROMs
PART
NUMBER
ORGANIZATION
ACCESS
TIME(ns)
ICC MAX. (rnA*)
ACTIVE STANDBY
TEMP
RANGE
2S04A
512 x S
250
SO
40
C,E,M
2S04A
512 x S
300
SO
40
C,E,M
2S04A
512 x S
350
SO
40
C,E,M
PART
NUMBER
ORGANIZATION
ACCESS
TIME(ns)
52813
2KxS
200
SO
30
C
52813
2KxS
250
SO
30
C,E,M
52813
2KxS
300
SO
30
M
52813
2KxS
350
SO
30
C,E
2S16A
2KxS
200
110
40
C
2S16A
2KxS
250
110
40
C,E,M
2S16A
2KxS
300
110
40
C,E,M
2S16A
2KxS
350
110
40
C
PACKAGE
P D N L F C T
••
••
••
DATA SHEET
PAGE#
1·19
1·19
1·19
16K EEPROMs
ICC MAX. (rnA*)
ACTIVE STANDBY
TEMP
RANGE
5516A
2KxS
200
110
40
C
5516A
2KxS
250
110
40
C
5516A
2KxS
300
110
40
C
2S17A
2KxS
200
110
40
C
2S17A
2KxS
250
110
40
C,E,M
2S17A
2KxS
300
110
40
C,E,M
2S17A
2KxS
350
110
40
C
5517A
2KxS
250
110
40
C
5517A
2KxS
300
110
40
C
PACKAGE
P D N L F C T
••
••
••
1·3
1·3,6·7
6·7
••
•••
•••
•••
•••
1·25,6·21
•
1·25
•
•
•••
•••
•••
•••
•
•
TEMPERATURE RANGE
PACKAGE
C = Commercial O°C to +70°C
E = Extended -40°C to +S5°C
M =Military ·55°C to +125°C
o = Ceramic Dip (Cerdip)
T8D
DATA SHEET
PAGE#
1·3,6·7
1·25
1·25,6·21
1·25
1·25
1·25
1·31
1·31,6·27
1·31,6·27
1·31
1·31
1·31
P = Plastic Dip (PDip)
N = Plastic Leaded Chip Carrier (PLCC)
L = Ceramic Leadless Chip Carrier (LCC)
F = Flat Pack
M = Module
C = Sidebraze
T = Pin Grid Array
=To 8e Determined
·Commercial Temperature Range
xi
64KEEPROMs
PART
NUMBER
ORGANIZATION
ACCESS
TIME(ns)
ICC MAX. (mA*)
ACTIVE STANDBY
TEMP
RANGE
52B33
8Kx8
200
110
40
52B33
8Kx8
250
110
40
C,E,M
52B33
8Kx8
300
110
40
C,E,M
52B33
8Kx8
350
110
40
C
2864
8Kx8
250
110
40
C,E,M
2864
8Kx8
300
110
40
C,E,M
2864
8Kx8
350
110
40
C,E,M
28C64
8Kx8
200
50
.150
C,E,M
28C64
8Kx8
250
50
.150
C,E,M
28C64
8Kx8
300
50
.150
C,E,M
28C64
8Kx8
350
50
.150
C,E,M
28C65
8Kx 8
200
50
.150
C,E,M
28C65
8Kx8
250
50
.150
C,E,M
28C65
8Kx 8
300
50
.150
C,E,M
28C65
8Kx 8
350
50
.150
C,E,M
• •••
PART
NUMBER
ORGANIZATION
ACCESS
TIME(ns)
TEMP
RANGE
PACKAGE
P D N L FCT
DATA SHEET
PAGE#
28C256
32Kx8
200
60
.200
C,E,M
1-59,6-55
28C256
32Kx8
250
60
.200
C,E,M
28C256
32Kx8
300
60
.200
C,E,M
2SC256
32KxS
350
60
.200
C,E,M
•• • ••••
• • • ••••
• • • • •••
• • • ••••
C
PACKAGE
PDNLFCT
••
•• •
•• •
••
• • • ••
• • • ••
• • • ••
• • ••
••••
••••
••••
••••
••••
••••
DATA SHEET
PAGE#
1-11
1-11,6-15
1-11,6-15
1-11
1-37,6-33
1-37,6-33
1-37,6-33
1-43,6-39
1-43,6-39
1-43,6-39
1-43,6-39
1-51,6-47
1-51,6-47
1-51,6-47
1-51,6-47
256K EEPROMs
ICC MAX. (mA*)
ACTIVE STANDBY
1-59,6-55
1-59,6-55
1-59,6-55
1024K EEPROMs
PART
NUMBER
ORGANIZATION
ACCESS
TIME(ns)
M28C010
12SK x S
250
M28C010
128K x S
M28C010
12SK x 8
ICC MAX. (mA*)
ACTIVE STANDBY
TEMP
RANGE
70
2
C,E,M
300
70
2
C,E,M
350
70
2
C,E,M
PACKAGE
DATA SHEET
PAGE#
M P D N L F CT
•
•
•
1-S9,6-95
1-S9,6-95
1-89,6-95
TEMPERATURE RANGE
PACKAGE
C = Commercial O°C to +70°C
E = Extended -40°C to +S5°C
M =Military -55°C to +125°C
P = Plastic Dip (PDip)
D = Ceramic Dip (Cerdip)
N = Plastic Leaded Chip Carrier (PLCC)
L = Ceramic Leadless Chip Carrier (LCC)
F = Flat Pack
M = Module
C =Sidebraze
T = Pin Grid Array
TBD = To Be Determined
·Commercial Temperature Range
xii
FLASH EPROMs
PART
NUMBER
ORGANIZATION
ACCESS
TIME(ns)
ICC MAX. (rnA*)
ACTIVE STANDBY
TEMP
RANGE
47F512
64Kx 8
200
40
.400
C
47F512
64Kx 8
250
40
.400
C,E,M
47F512
64Kx 8
300
40
.400
C,E,M
47F010
128K x 8
200
40
.400
C
47F010
128K x 8
250
40
.400
C,E,M
47F010
128K x 8
300
40
.400
C,E,M
PACKAGE
P D N L F C T
•••
••••
•• ••
•••
•• ••
•• ••
DATA SHEET
PAGE#
2-3
2-3,6-141
2-3,6-141
2-25
2-25,6-163
2-25,6-163
FLASH EEPROMs
PART
NUMBER
ORGANIZATION
ACCESS
TIME(ns)
ICC MAX. (rnA*)
ACTIVE STANDBY
TEMP
RANGE
48F512
64Kx 8
200
60
.100
C
48F512
64Kx 8
250
60
.100
C,E,M
48F512
64Kx 8
300
60
.100
C,E,M
48F010
128K x 8
200
60
.100
C
48F010
128K x 8
250
60
.100
C,E,M
48F010
128K x 8
300
60
.100
C,E,M
KT48
FLASH
PROGRAMMING
KIT
PACKAGE
P D N L F C T
• ••
•• •••
•••••
•••
•••••
•• •••
DATA SHEET
PAGE#
2-13
2-13,6-151
2-13,6-151
2-35
2-35,6-173
2-35,6-173
2-47
HIGH SPEED 16K EEPROMs
PART
NUMBER
ORGANIZATION
36C16
2Kx8
35
80
36C16
2Kx 8
40
80
-
C
ACCESS
TIME(ns)
ICC MAX. (rnA*)
ACTIVE STANDBY
TEMP
RANGE
C
36C16
2Kx 8
45
80
-
C,E,M
36C16
2Kx 8
55
80
2KxS
70
SO
-
C,E,M
36C16
3SC16
2Kx S
35
SO
40
C
3SC16
2Kx 8
40
SO
40
C
E,M
3SC16
2KxS
45
SO
40
C,E,M
3SC16
2KxS
55
80
40
C,E,M
3SC16
2KxS
70
SO
40
E,M
PACKAGE
PDNLFCT
••
••
•• •
•• •
•• •
•••
•••
••••
••••
• •
DATA SHEET
PAGE#
1-77
1-77
1-77,6-83
1-77,6-S3
6-S3
1-83
1-83
1-S3,6-89
1-S3,6-S9
6-89
TEMPERATURE RANGE
PACKAGE
C = Commercial O°C to +70°C
E = Extended -40°C to +S5°C
M = Military -55°C to +125°C
P = Plastic Dip (PDip)
D = Ceramic Dip (Cerdip)
N = Plastic Leaded Chip Carrier (PLCC)
L = Ceramic Leadless Chip Carrier (LCC)
F = Flat Pack
M = Module
C = Side braze
T = Pin Grid Array
TBD
=To Be Determined
·Commercial Temperature Range
xiii
HIGH SPEED 32K EEPROMs
PART
ORGANIZATION
NUMBER
ACCESS
TlME(ns)
ICC MAX. (mA*)
ACTIVE STANDBY
TEMP
RANGE
36C32
4Kx8
35
80
-
C
36C32
4Kx8
40
80
C
36C32
4Kx8
45
80
-
C,E,M
36C32
4Kx8
55
80
-
C,E,M
36C32
4Kx8
70
80
-
E,M
38C32
4Kx8
35
SO
40
C
38C32
4Kx8
40
SO
40
C
38C32
4KxS
45
SO
40
C,E,M
38C32
4Kx S
55
80
40
C,E,M
38C32
4Kx8
70
SO
40
E,M
PACKAGE
P D N L FCT
••
••
•• •
•• •
•• •
• ••
•••
••••
••••
••••
DATA SHEET
PAGE#
1-77
1-77
1-77, 6-83
1-77, 6-83
6-S3
1-S3
1-S3
1-S3, 6-89
1-S3, 6-89
6-S9
HIGH SPEED 256K EEPROMs
PART
NUMBER
ORGANIZATION
ACCESS
TIME(ns)
ICC MAX. (mA*)
ACTIVE STANDBY
TEMP
RANGE
PACKAGE
P D N L F C T
28HC256
32Kx8
70
SO
28HC256
32KxS
90
SO
.300
C,E,M
.300
C,E,M
SO
.300
C,E,M
150
60
.300
C,E,M
200
60
.300
C,E,M
60
.300
C,E,M
• • • • • ••
• • • • • ••
• • • • • ••
•••••••
•••••••
•••••••
28HC256
32Kx8
120
28C256A
32Kx8
28C256A
32Kx8
28C256A
32Kx8
250
DATA SHEET
PAGE#
6-73
6-73
6-73
6-63
6-63
6-63
HIGH SPEED 1024K EEPROMs
PART
NUMBER
ORGANIZATION
ACCESS
TIME(ns)
ICC MAX. (mA*)
ACTIVE STANDBY
TEMP
RANGE
28C010
12SK x 8
120
120
.350
C,E,M
28C010
128K x 8
150
120
.350
C,E,M
2SC010
12SK x 8
200
120
.350
C,E,M
2SC010
12SK x 8
250
120
.350
C,E,M
PACKAGE
P D N L F C T
•••
•••
•••
•••
DATA SHEET
PAGE#
6-103
6-103
6-103
6-103
TEMPERATURE RANGE
PACKAGE
C =Commercial ODC to +70DC
E = Extended _40DC to +S5°C
M =Military -55 DC to +125DC
P = Plastic Dip (PDip)
= Ceramic Dip (Cerdip)
N = Plastic Leaded Chip Carrier (PLCC)
L = Ceramic Leadless Chip Carrier (LCC)
F = Flat Pack
M = Module
C = Sidebraze
T = Pin Grid Array
o
TBD = To Be Determined
·Commercial Temperature Range
XIV
64K1128K1256K UVEPROMs
ACCESS
TIME(ns)
ICC MAX. (mA*)
ACTIVE STANDBY
PART
NUMBER
ORGANIZATION
TEMP
RANGE
2764
8Kx8
160
100
30
C
2764
8Kx8
200
100
30
C,E,M
2764
8Kx 8
250
100
30
C,E,M
C
2764
8Kx8
300
100
30
2764
8Kx8
350
100
30
E,M
2764
8Kx8
450
100
30
C,E,M
27128
16K x 8
200
100
30
C,E,M
27128
16K x 8
250
100
30
C,E,M
27128
16K x 8
300
100
30
C
27128
16K x 8
350
100
30
E,M
27128
16K x 8
450
100
30
C,E,M
27C256
32Kx8
200
50
.150
C,E,M
27C256
32Kx 8
250
50
.150
C,E,M
27C256
32Kx8
300
50
.150
C,E,M
27C256
32Kx 8
450
50
.150
C
PACKAGE
P D N L F C T
DATA SHEET
PAGE#
•
•
•
•
•
•
• •
• •
•
• •
• •
• •
• •
• •
•
3-3
3-3,6-113
3-3,6-113
3-3
6-113
3-3,6-113
3-3,6-113
3-3,6-113
3-3
6-113
3-3,6-113
3-11,6-121
3-11,6-121
3-11,6-121
3-11
DESC - COMPLIANT UVEPROMs
PART
ORGANIZATION
NUMBER
ACCESS
TIME(ns)
ICC MAX. (mA*)
ACTIVE STANDBY
TEMP
RANGE
82005
8Kx 8
200
100
30
M
82005
8Kx 8
250
100
30
M
82005
8Kx 8
450
100
30
M
82025
16Kx 8
200
100
30
M
82025
16K x 8
250
100
30
M
82025
16K x 8
300
100
30
M
82025
16Kx 8
450
100
30
M
86063
32Kx8
200
50
.150
M
86063
32Kx8
250
50
.150
M
86063
32Kx 8
300
50
.150
M
PACKAGE
P D N L F C T
•
•
•
• •
• •
• •
• •
• •
• •
• •
DATA SHEET
PAGE#
6-129
6-129
6-129
6-133
6-133
6-133
6-133
6-137
6-137
6-137
TEMPERATURE RANGE
PACKAGE
C = Commercial O°C to +70°C
E = Extended -40°C to +85°C
M = Military -55°C to +125°C
P = Plastic Dip
D = Ceramic Dip
N = Plastic Leaded Chip Carrier
L =Ceramic Leadless Chip Carrier
F = Flat Pack
M = Module
C = Side braze
T = Pin Grid Array
TBD = To Be Determined
·Commercial Temperature Range
**f =1 MHz; 5mA/Additional MHz
···Commercial O°C to 75°C
xv
CMOS EEPLDs
PART
NUMBER
DESCRIPTION PINS
SPEED
tpD(ns)
ICC MAX. (mA*)
ACTIVE STANDBY
TEMP
RANGE
20RA10Z-35
Asynchronous
24
35
25**
.150
C***
20RA10Z-40
Asynchronous
24
40
25**
.150
C,***E,M
20RA10Z-45
.150
C,***E,M
Asynchronous
24
45
25**
26V12H-20
Versatile
28
20
105
-
C
26V12H-25
Veratile
28
25
105
-
C
PACKAGE
DATA SHEET
PDNLFCT
PAGE#
••••
• •••
• • ••
•••
•••
5-3
5-3
5-3
5-21
5-21
COMMUNICATION PRODUCTS
PART
NUMBER
ICC MAX. (mA*)
ACTIVE
TEMP
RANGE
8003
200
C
8020
75
C
8023A
75
C
8005
350
C
PACKAGE
PDNLFCT
••
•••
•••
•
FUNCTION
PAGE#
DATA SHEET
Ethernet Data Link
Controller
4-1
10 MHz Manchester
Encoder/Decoder
4-13
1OMHz Manchester
Encoder/Decoder
4-27
Advanced Ethernet
Data Link Controller
4-43
TEMPERATURE RANGE
PACKAGE
C = Commercial O°C to +70°C
E = Extended -40°C to +85°C
M Military -55°C to + 125°C
P = Plastic Dip
D = Ceramic Dip
N = Plastic Leaded Chip Carrier
L = Ceramic Leadless Chip Carrier
F = Flat Pack
M = Module
C = Sidebraze
T = Pin Grid Array
=
TBD = To Be Determined
*Commercial Temperature Range
**f = 1 MHz; 5mA/Additional MHz
·*·Commercial O°C to 75°C
xvi
·
EEPROMs
(Electrically Erasable Programmable Read Only Memories)
SEEQ TECHNOLOGY
EEPROM CROSS REFERENCE
Alternate
Manufacturer
AMD
AMD
AMD
Atmel
Atmel
Atmel
Atmel
Atmel
Atmel
Atmel
Atmel
Atmel
Atmel
Atmel
Atmel
Atmel
Atmel
Cypress
Cypress
Cypress
Exel
Exel
Exel
Exel
Intel
Intel
Intel
Intel
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
TI
TI
Xicor
Xlcor
Xicor
Xicor
Xlcor
Xicor
Xlcor
Xicor
Xlcor
Xlcor
Part #
EEPROM
Configuration
SEEa Part #
2817A
2864
28648
AT28HC16
AT28C64
AT28C64E
AT28C64X
AT28HC64
AT28PC64
AT28C64F
AT28C256
AT28C256F
AT28HC256
AT28HC256F
AT28MC010
AT28HC191
AT28HC291
CV7292
CV7291
CV8C291
2804A
2816A
2864
2865
2816
2816A
2817A
2864
28HC16
28C291
28C191
28C64
28CP64
28C256
TMS27C291
TMS27C191
X2804A
X2816A
X2864A
X2864AT
X2864A8
X2864H
X28256
X28C256
XM28C010
X28C010
2KX8
8KX8
8KX8
2KX8
8KX8
8KX8
8KX8
8KX8
8KX8
8KX8
32KX8
32KX8
32KX8
32KX8
128K X 8
2KX8
2KX8
2KX8
2KX8
2KX8
512 X8
2KX8
8KX8
8KX8
2KX8
2KX8
2KX8
8KX8
2KX8
2KX8
2KX8
8KX8
8KX8
32KX8
2KX8
2KX8
512 X8
2KX8
8KX8
8KX8
8KX8
8KX8
32KX8
32KX8
128K X8
128K X 8
2817A
2864
28C64
38C16
28C65
55C65
28C64
28C64A
28C64
28C64A
28C256
28C256A
28HC256
28HC256H
M28C010
36C16
36C16*
36C16
36C16*
36C16*
2804A
2816A
2864
28C65
52813
52813
2817A
52833
38C16
36C16*
36C16
28C65
28C64A
28C256
36C16*
36C16
2804A
2816A
28C64
28C64
28C64
28C64A
28C256
28C256
M28C010
28C010
* Indicates 300 mil wide package (Skinny DIP)
SeeQ
Technology, Incorporated
1-1
SEEQ TECHNOLOGY
PROM REPLACEMENT CHART
Alternate
Manufacturer
Part #
Description
SEEQ Part #
AMD
AM27PS291 DC
2KX 8 PROM
36C16-45
AMD
AM27PS291OM
2KX8 PROM
36C16-55
AMD
AM27PS291 ADM
2K X8 PROM
36C16-55
AMD
AM27S291ADC
2KX8 PROM
36C16-35
CYPRESS
CY7C291-35
2KXS PROM
36C16-35
CYPRESS
CY7C291-50
2KX8 PROM
36C16-45
FUJITSU
MB7138Y-SKZ
2K X8 PROM
36C16-35
FUJITSU
MB713SH-SKZ
2K XS PROM
36C16-45
FUJITSU
MB713SE-WZ
2K XS PROM
36C16-45
HARRIS
6-76161
2KXS PROM
36C16-45
MMI
63S1681NS
2K X8 PROM
36C16-45
MMI
63S16S1ANS
2K XS PROM
36C16-35
NATIONAL
DM77S291
2K X8 PROM
36C16-55
NATIONAL
DM87S291
2KX8 PROM
36C16-55
RAYTHEON
296S1ASM
2K XS PROM
36C16-55
RAYTHEON
296S1ASC
2KXS PROM
36C16-55
RAYTHEON
296S1SC
2K XS PROM
36C16-55
RAYTHEON
29683ASC
2KXSPROM
36C16-45
RAYTHEON
296S3ASM
2K XS PROM
36C16-55
SIGNETICS
S2S291
2KXS PROM
36C16-45
TI
27C291-35
2KXS PROM
36C16-45
TI
27C291-50
2KXS PROM
36C16-45
36C16-45
TI
TBP2SS166N
2K X8 PROM
WAFRSCAL
57C291-40
2KXSPROM
36C16-35
WAFRSCAL
57C291-55
2K X8 PROM
36C16-55
NATIONAL
DM87S421
4KXS PROM
36C32-55
NATIONAL
DM87S421A
4KXS PROM
36C32-45
NATIONAL
DM77S421
4KXS PROM
36C32-55
NATIONAL
DM77S421A
4KXSPROM
36C32-55
RAYTHEON
29671ASC
4KXS PROM
36C32-45
RAYTHEON
29671ASM
4KXS PROM
36C32-55
RAYTHEON
29673SC
4KX8PROM
36C32-55
RAYTHEON
29673SM
4KXS PROM
36C32-55
seeG
Technology, Incorporated
1-2
seeQ
52813152813H
16K Electrically Erasable PROM
October 1988
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Description
Input Latches
SEEO's 52813 and 52813H are 2048 x 8 bit, 5 volt electrically erasable programmable read only memories
(EEPROM) with input latches on all address, data and
control (chip and output enable) lines. Data is latched and
electrically written by either a TTL or a 21 V pulse on the
Write Enable pin. Once written, which requires under 10
ms, there is no limit to the number of times data may be
read. 80th byte and chip erase modes are available. The
erasure time in either mode is under 10 ms, and each byte
may be erased and written a minimum of 10,000 times.
They are direct pin-for-pin replacement for SEEO's 5213,
and Intel 2816/2816A.
TTL Byte Erase/Byte Write
1 ms (S2B13H) or 9 ms Byte Erase/Byte Write
Power Up/Down Protection
10,000 EraseIWrlte Cycles per Byte Minimum
SV± 10% Operation
Fast Read Access Time - 200 ns
Infinite Number of Read Cycles
Chip Erase and Byte Erase
DiTrace®
The 52813 and 52813H are ideal for applications that
require a non-volatile memory with in-system write and
erase capability. Dynamic reconfiguration (the alteration
JEDEC Approved Byte WldeMemory Pinout
Military And Extended Temperature Range
Available
Direct Replacement for Intel 2816/2816A
Block Diagram
Pin Configuration
52B13/52B13H
A O-3
E2
MEMORY
ARRAY
As
A5
Ag
A4
WE
BE
A2
A
Al
CE
Ao
1/°7
VO o
VOs
V0 5
VOl
V0 2
LATCH ENABLE
l0
V04
1/0 3
GND
CE
DE
Pin Names
Aa-Al0
110 0- 7
DiTrace is a registered trademark of SEEQ Technology Inc.
MD400006/C
Vcc
As
A3
WRITE/ERASE
ENABLE
seeQ
A7
Technology, Incorporated
1-3
ADDRESSES
CE
CHIP ENABLE
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00 _7
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
52813152813H
applied to WE to execute an erase or write operation. The
52813 specifies no restriction on the rising edge ofW£.
of operating software in real-time) is made possible by this
device. Applications for the 52813 and 52813H will be
found in military avionics systems, programmable character generators, self-calibrating instruments/machines,
programmable industrial controllers, and an assortment of
other systems. Designing the 52813 and 52813H into
eight and sixteen bit microprocessor systems is also simplified by utilizing the fast access time with zero wait states.
The addition of the latches on all data, address and control
inputs reduces the overhead on the system controller by
eliminating the need for the controller to maintain these
signals. This reduces IC count on the board and improves
the system performance. Extended temperature and military grade versions are available.
For certain applications, the user may wish to erase the
entire memory. A chip erase is performed in the same
manner as a byte erase except that Output Enable is
between 14Vand 22V. AI12K bytes are erased in under
1Oms.
A characteristic of all EEPROMs is that the total number of
write and erase cycle is not unlimited. The 52813 and
528 13H have been designed for applications requiring up
to 10,000 write and erase cycles per byte. The write and
erase cycling characteristic is completely byte independent. Adjacent bytes are not affected during writelerase
cycling.
Device Operation
SEEO's 52813 and 52813H have six modes of operation
(see Table 1) and except for the chip erase mode they
require only TTL inputs to operate these modes.
After the device is written, data is read by applying a TTL
high to WE, enabling the chip, and enabling the outputs.
Data is available teE time after Chip Enable is applied or
tAA time from the addresses. System power may be reduced by placing the 52813 or 52813H into a standby
mode. Raising Chip Enable to a TTL high will reduce the
power consumption by over 60%.
To write into a particular location of the 52813 or 52813H,
that byte must first be erased. A memory location is erased
by presenting the 52813 or 52813H with Chip Enable at a
TTL low while Output Enable is at TTL high, and TTL highs
(logical 1s) are being presented to all the 110 lines. These
levels are latched and the data written when write enable
is brought to a TTL low level. The erase operation requires
under 10 ms. A write operation is the same as an erase
except true data is presented to the 110 lines. The 52813H
performs the same as the 52813 except that the device
byte eraselbyte write time has been enhanced to 1 ms.
DiTrace
SEEO's family of EEPROMs incorporate a DiTrace field.
The DiTrace feature is a method for storing production flow
information to wafer level in an extra column of EEPROM
cells. As each major manufacturing operation is performed the DiTrace field is automatically updated to reflect
the results of that step. These features establish manufacturing operation traceability of the packaged device back
to the wafer level. Contact SEEO for additional information
on these features.
The 52813 is compatible to prior generation EEPROMs
which required a high voltage signal for writing and erasing. In the 52813 there is an internal dual level detection
circuit which allows either a TTL low or 21 V signal to be
Table 1. Mode Selection (Vee =5V ± 10%)
~
CE
OE
WE
1/0
Mode
Read[1]
(18)
(20)
(21)
(9-11,13-17)
VIL
VIH
VIL
Don't Care
VIH
Standby[1]
Dour
HighZ
Byte Erase[2]
VIL
VIH
VIL
Byte Write[2]
VIL
VIH
VIL
VIL
Don't Care
Chip Erase[2]
VIL
VOE
Write/Erase Inhibit
VIH
Don't Care
VIH
DIN
=VIH
DIN
=VIH
HighZ
DIN
NOTES:
1. WE may be from V to 6V in the read and standby mode.
2. WE may be atV1L (TIL WE Mode) or from 15 to 21V (High Voltage WE mode) in the byte erase, byte write, or chip erase mode of
the 52B13/52B13H.
seeQ
MD4000061C
Technology, Incorporated
1-4
52813152813H
Power Up/Down Considerations
Typical EEPROM Write/Erase Routine
SEEQ's "528" P family has internal circuitry to minimize
false erase or write during system Vee power up or down.
This circuitry prevents writing or erasing under anyone of
the following conditions:
1. Vee is less than 3 V. {I}
WAIT SUBROUTINE
.
2. A negative Write Enable transition has not occurred
when Vee is between 3 V and 5 V.
Writing will also be prevented if CE or OE are in a logical
state other than that specified for a byte write in the mode
selection table.
EXECUTE
WAIT
SUBROUTINE
FOR 'WP
ISSUE
MEMORY READ
COMMAND TO
CLEAR EXTERNAL
WE LATCH
(Note: Data is
invalid in this
operation.)
Microprocessor Interface Circuit Example for Byte Write/Erase
ADDRESS , -__________________________________.,
ADDRESSES
BUS
r-------------------------------~ OE
SYSTEM RESET
l,>--+----~
MEMORY READ
l,
EEPROM SELECT
~
MEMORY WRITE
p-..--+-a
l,r--"'---'
WE
74LSOO
74LS32
CHIP SELEC-
~>----------------~ CE
1/0 0 -7
DATA BUS
NOTE:
1. Characterized. Not tested.
seeQ
MD4000061C
Technology, Incorporated
1-5
52813152813H
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Stress Ratings*
Temperature
Storage ............................................ -65°C to +150°C
Under Bias ........................................ -1O°C to +80° C
D. C. Voltage applied to all Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot/Overshoot pulse of less then 10 ns
(measured at 50% point) applied to all inputs or
outputs with respect to ground .... (undershoot) -1.0 V
(overshoot) + 7.0 V
WE During Writing/Erasing
with Respect to Ground ..................... +22.5V to -0.3V
Recommended Operating Conditions
52B13-200/-250/-350
52B13H-200/-250/-350
I Vee Supply Voltage
I Temperature Range (Ambient)
Endurance and Data Retention
5V± 10%
O°C to 70°C
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
Condition
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
D.C. Operating Characteristics During Read or Write/Erase
(Over the operating Vee and temperature range)
NomPI
Symbol
Parameter
Max.
Unit
liN
Input Leakage Current
10
Il A
VIN = Vee Max.
10
Output Leakage Current
10
IlA
VOUT = Vee Max.
IWE
Write Enable Leakage
Read Mode
10
IlA
TTL W/E Mode
10
IlA
High Voltage W/E Mode
1.5
mA
High Voltage W/E Inhibit Mode
1.5
mA
WE = V IH
WE = V IL
WE = 22V, CE = V1L
WE = 22V, CE = V1H
Chip Erase -
TTL Mode
10
IlA
WE = V 1L
Chip Erase Mode
High Voltage
Min.
Test Conditions
1.5
mA
WE = 22V
lee1
Vee Standby Current
15
30
mA
CE = V1H
lee2
Vee Active Current
50
80
mA
CE = OE = V 1L
V IL
Input Low Voltage
-0.1
0.8
V
V1H
V WE
Input High Voltage
2
Vee + 1
V
WE Read Voltage
2
Vee + 1
V
-0.1
0.8
V
14
22
V
0.45
V
10L = 2.1 mA
V
10H = -400 IlA
V
10E = 10 IlA
WE Write/Erase Voltage
TTL Mode
High Voltage Mode
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
VOE
OE Chip Erase Voltage
14
NOTES:
1. Nominal values are for T A
SeeQ
MD4000061C
= 25°C and Vee = 5.0 V.
Technology, Incorporated
1-6
22
52813152813H
A.C. Operating Characteristics During Read
(Over the operating Vcc and temperature range)
Device
Number
Extension
52813
52813H
Symbol
Parameter
Max.
Units
tAA
Address Access Time
-200
-250
-350
200
250
350
ns
ns
ns
CE = OE =VIL
tCE
Chip Enable to Data Valid
-200
-250
-350
200
250
350
ns
ns
ns
OE = VIL
(1)
Output Enable to Data Valid
-200
-250
-350
80
90
100
ns
ns
ns
CE = VIL
(2)
Output Enable to High Impedance
-200
-250
-350
0
0
0
60
70
80
ns
ns
ns
CE = VIL
All
0
ns
CE = OE = VIL
tOE
t
OF
Output Hold
tOH
Min.
Capacitance l3I TA =25°C, f = 1 MHz
Test Conditions
A.C. Test Conditions
Symbol
Parameter
Max.
Unit
Conditions
CIN
Input Capacitance
10
pF
VIN = OV
COUT
Output Capacitance
10
pF
VOUT=OV
CVcc
Vcc Capacitance
500
pF
CV WE
V WE Capacitance
10
pF
OE = CE = V IH
OE = CE = V IH
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times:::; 20ns
Input Pulse Levels: 0.45V to 2.4 V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
Read Timing
ADDRESSES
VALID
ADDRESSES
OE
OUTPUT
------+-------f-+-+-+--10
Years
MIL-STD 883 Test
Method 1008
D.C. Operating Characteristics During Read or Erase/Write
(Over the operating Vee and temperature range)
Symbol
Parameter
Max.
Unit
Test Conditions
liN
Input Leakage Current
10
J.LA
10
Output Leakage Current
10
J.LA
IWE
Write Enable Leakage
leel
Vee Standby Current
lee2
V ll
VIH
Vee Active Current
= Vee Max.
= Vee Max.
WE = V ll
CE = VIH
CE = OE = V ll
VOL
Output Low Voltage
V OH
Output High Voltage
Min.
J.LA
40
rnA
60
110
rnA
VOUT
-0.1
0.8
V
Input High Voltage
2
Vee + 1
V
0.45
V
'Ol = 2.1 mA
V
IOH
2.4
1. Nominal values are for TA = 25°C and Vee = 5.0 V.
seeQ
10
18
VIN
Input Low Voltage
NOTE:
MD4000081B
Nom.
Technology, Incorporated
1-13
= -400 J.LA
52833152833H
A.C. Operating Characteristics During Read
Device
Number
Extension
(Over the operating Vee and temperature range)
52B33
52B33H
Min.
Max.
Units
Test Conditions
Symbol
Parameter
tAA
Address Access Time
-200
-250
-350
200
250
350
ns
ns
ns
CE =OE =VIL
teE
Chip Enable to Data Valid
-200
-250
-350
200
250
350
ns
ns
ns
OE = VIL
(1)
Output Enable to Data Valid
-200
-250
-350
80
90
100
ns
ns
ns
CE = VIL
(2)
Output Enable to High Impedance
-200
-250
-350
0
0
0
60
70
80
ns
ns
ns
CE = VIL
0
ns
CE =OE = V IL
10
pF
VIN =0 V for
C IN • VOUT =0 V
for COUTo
TA III: 25°C
t
OE
tOF
tOH
Output Hold
All
CI,/
Input and Output
Capacitance
All
C
(3)
OUT
Read Cycle Timing
ADDRESSES
VALID
ADDRESSES
CE
OUTPUT
-------+-------+-t--+++_<
HIGHZ
1 - 4 - - - - 1M ------I1tooI
NOTES:
1. OE may be delayed to tAA - tOE after the falling edge of CE without impact on tAA .
2. tDF is specified from OE or CE. whichever occurs first.
3. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
4. After tHo hold time. from WE, the inputs CE, OE,
Address and Data are latched and are "Don't Cares" until twR' Write
Recovery Time, after the trailing edge of WE.
5. The Write Recovery Time, tWR ' is the time after the trailing edge of WE that the latches are open and able to accept the next
mode set-up conditions. Reference Table 1 (page 2) for mode control conditions.
ce,
seeQ
MD40000BIB
Technology, Incorporated
1-14
52833152833H
A.C. Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ~ 20ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs O.B V and 2 V
A.C. Operating Characteristics During Write/Erase
(Over the operating Vee and temperature range)
Max.
Units
Symbol
Parameter
Min.
ts
GE, OE or Address Setup to WE
50
ns
tos
t [4}
Data Setup to WE
15
ns
WE to GE, OE, Address or Data Change
50
ns
Write Enable (WE) Pulse Width
Byte Modes - 52B33
9
H
twp
Byte Modes tWR
[5}
52B33H
WE to Mode Change
WE to Start of Next Byte Write Cycle
WE to Start of Read Cycle
1
ms
50
ns
1
Il s
Byte Erase or Byte Write Cycle Timing
ADDRESSES
DON'T CARE
CE
DON'T CARE
OE
DON'T CARE
~---IWp---~~
WE
-------+-------,I
1/0 _ _ _ _H_IG_H_Z--+-{ I
(WRITE MODE)
DON'T CARE
1/0 - - - - - - + - - J '
(ERASE MODE)
DON'T CARE
1-----
BYTE ERASElWRITE PERIOD
(Noles 4 and 5 are on previous page)
seeQ
MD40000BIB
Technology, Incorporated
1-15
~-- START OF NEXT MODE
52833152833H
A.C. Operating Characteristics During Chip Erase.
(Over the operating Vee and temperature range)
Max.
Symbol
Parameter
Min.
ts
t (4)
CC, CE, OE Setup to WE
50
ns
WE to CE, OE, CC change
50
ns
Write Enable (WE) Pulse Width
Chip Erase - 52B33
Chip Erase - 52B33H
10
ms
WE to Mode change
WE to Start of Next Byte Write Cycle
50
ns
H
twp
tWR
(5)
WE to Start of Read Cycle
1
TTL Chip Erase Timing
L
I
CC
~~
I
~~
I
II
DON'T CARE
II
DON'T CARE
I
I
1
1
1
OE
--
y~
IH
1\
........
I
I
WE
1
1
IS
1
1
I
.--
\
"'"
-'t-.
r ..
"
~
~~
~
1
IWR
1
CHIP ERASE PERIOD
NOTE: Address, Data are don't eare during Chip Erase.
MD40000BIB
I
.... -
1.....
1-----
seeQ
1
IWp
1
T
DON'T CARE
Technology, Incorporated
1-16
~I
- - - - - I...
Units
Jls
52833152833H
Microprocessor Interface Circuit Example for Byte Write/Erase
ADDRESS r-------------------------------~~
BUS
ADDRESSES
r-----------------------------Q OE
SYSTEM RESET ~.>--+------'~-......
MEMORY READ
P--+-.,..Q WE
~"------A-.II''''---''
EEPROM SELECT ~
MEMORY WRITE ~,--"",--,
CHIP SELECT ~
CE
110 0 _7
DATA BUS
NOTE:
ALL SIGNALS MUST SATISFY THE RELATIONSHIPS INDICATED BY THE TIMING DIAGRAMS
SHOWN ON PAGES 4 AND 5. EEPROM SELECT IS DERIVED FROM THE CHIP SELECT SIGNALS
OF ALL DEVICES FOR WHICH THIS CIRCUIT GATES WE. THIS MAY ENTAIL A SIMPLE OR
FUNCTION. IN CASE OF A SINGLE EEPROM, THE TWO SIGNALS WOULD BE COMMON.
Typical EEPROM Write/Erase Routine
WAIT SUBROUTINE
ISSUE
MEMORY READ
COMMAND TO
CLW; ~~~RNAL
Ordering Information
o
Q
(Note: Data is
invalid in this
operation.)
52833
H-250
~IT~T~
PACKAGE
TYPE
OPERATING
TEMPERATURE
RANGE
PART TYPE
0- CERAMIC DIP
P - PLASTIC DIP
UX - UNENCAPSULATED DIE
Q - O"C TO + 7O"C
8K
seeQ
MD40000BIB
x 8 EEPROM
(COMMERCIAL)
Technology, Incorporated
1-17
EEPROM BYTE WRITE TIME
ACCESS TIME
(BLANK) - STANDARD WRITE TIME
H - FAST WRITE TIME
200 - 200 ns
250 - 250 ns
350- 350 ns
1-18
seeQ
2804A
Timer E2
4K Electrically Erasable PROM
October 1989
Description
Features
•
•
•
•
•
•
•
•
•
•
SEEQ's 2804A is a 5 Vonly, 512 x 8 electrically erasable
programmable read only memory (EEPROM). EEPROMs
are ideal for applications which require non-volatility and
in-system data modification. The endurance, the number
of times that a byte may be written, is 10 thousand cycles
for the 2804A.
High Endurance
• 10,000 Cycles/Byte Minimum
On-Chip Timer
• Automatic Erase and Write Time Out
AI/Inputs Latched by Write or Chip Enable
Direct Replacement to 512 x 8 EEPROMs
This device has an internal timer that automatically times
out the write time. A separate erase cycle is not required
and the minimum write enable (WE) pulse width needs to
be only 150 ns. The on-chip timer, along with the inputs
being latched by a write or chip enable signal edge, frees
the microcomputer system for other tasks during the write
time. The write time is 10 ms. Once a byte is written, it can
be read in 250 ns. The inputs are TTL for both the byte
write and read mode.
5 V t 10% Power Supply
Power Up/Down Protection Circuitry
250 ns max. Access Time
Low Power Operation
• 80 mA max. Active Current
• 40 mA max. Standby Current
10 Year Data Retention
JEDEC Standard Byte- Wide Pinout
Pin Configuration
Block Diagram
A7
VCC
As
As
AS
NC
A4
WE
A3
OE
A2
NC
A1
CE
AO
1/°7
1/°0
I/Os
1/°1
1/°5
1/°2
1/°4
GND
1/0 3
Pin Names
1/°0-7
seeQ
MD400019/C
Technology, Incorporated
1-19
Ao-A4
COLUMN ADDRESSES
As-As
CE
CHIP ENABLE
ROW ADDRESSES
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/°0_7
DATA INPUT (WRITE)
DATA OUTPUT (READ)
2804A
Mode Selection
Device Operation
There are four operational modes (see Table 1) and only
TTL inputs are required. To write into a particular location,
a TTL low is applied to the write enable (WE) pin of a
selected (CE low) device. This, combined with output
enable (OE) being high, initiates a write cycle. During a
byte write cycle, addresses are latched on the last falling
edge of CE orWE' and data is latched on the first rising
edge of CE or WE. An internal timer times out the required
byte write time. An automatic byte erase is performed
internally in the byte write mode. The 2804A ignores
attempts to read or write while the internal write cycle is in
progress.
(Table 1)
Mode
CE
OE
WE
1/0
Read
VIL
VIH
Standby
VIL
VIH
X
X
DOUT
HIZ
Byte Write
VIL
VIH
VIL
DIN
Write
Inhibit
X
X
VIL
X
HI ZlDouT
HI ZlDouT
X
VIH
X: any TIL Level
prevents writing under anyone 0 f the following conditions.
1. Vce is less than 3V.l'J
2. A negative Write Enable (WE) transition has not
occurred when Vcc is between 3 V and 5 V.
Absolute Maximum Stress Ratings'"
Writing will also be prevented if CE or OE are in a logical
state other than that specified for a byte write in the Mode
Selection table.
Temperature
Storage ............................................ -65°C to + 150°C
Under Bias ........................................ -10°C to +80° C
D.C. Voltage applied to all Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot/Overshoot pulse of less then 10 ns
(measured at 50% point) applied to all inputs or
outputs with respect to ground .... (undershoot) -1.0 V
(overshoot) + 7.0 V
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings· may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Power Up/Down Considerations
Recommended Operating Conditions
The 2804A has internal circuitry to minimize a false write
during system Vcc power up or down. This circuitry
I Temperature Range
I Vee Supply Voltage
Endurance and Data Retention
2804A
(Ambient) O°C to 70°C
5V ± 10%
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
DC Operating Characteristics
Condition
TA = 0° to 70°C; Vee = 5 V ± 10%, unless otherwise noted.
Limits
Symbol
Parameter
Max.
Units
Icc
Active Vee Current
80
mA
CE = OE =V1L; All 1/0 Open;
Other Inputs = 5.5 V
IS8
Standby Vee Current
40
mA
CE = VIH' OE = VIL; All 110's
Open; Other Inputs = 5.5 V
IlL
Input Leakage Current
10
IOL
VIL
VIH
Output Leakage Current
10
IlA
IlA
VIN = 5.5 V
VOUT = 5.5 V
VOL
VOH
Output Low Voltage
Min.
Input Low Voltage
-0.1
0.8
V
Input High Voltage
2.0
6
V
0.4
V
101. = 2.1 mA
V
IOH = -400 ~A
Output High Voltage
2.4
NOTE:
1 Characterized. Not tested.
SeeQ
MD4000191C
Test Condition
Technology, Incorporated
1-20
2804A
AC Characteristics
Read Operation TA=O° t070° C; Vcc=5V ± 10%, unless otherwise noted.
Limits
2804A-2S0
2804A-300
Symbol
Parameter
Min.
t RC
Read Cycle Time
250
tCE
Chip Enable Access Time
250
300
ns
tAA
Address Access Time
250
300
ns
tOE
Output Enable Access Time
90
100
ns
tLZ
CE to Output in Low Z
tHZ
CE to Output in HI Z
tOLZ
OE to Output in Low Z
tOHZ
OE to Output in HI Z
Max.
tpu
CE to Power-up Time
tpD
[I)
CE to Power Down Time
ns
ns
100
100
[I)
ns
100
50
50
Units
ns
10
100
Output Hold from Address Change
Capacitance {2}
Min.
300
10
[I)
tOH
Max.
ns
20
20
ns
0
0
ns
50
50
ns
TA = 25°C, f = 1 MHz
Symbol
Parameter
Max
Conditions
A. C. Test Conditions
C IN
Input Capacitance
6 pF
VIN = 0 V
C OUT
Data (1/0) Capacitance
10 pF
VI/O = 0 V
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 20ns
Input Pulse Levels: 0.45V to 2.4V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
E.S.D. Characteristics
Symbol
VZAP
Parameter
Value
Test Conditions
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
[I)
Read Cycle Timing
14-----tRe---~
ADDRESSES
DATA OUT ---'-'-=.;...;;;;..+-----{I
'be
SUPPLY
CURRENT _ _
=-_--J
NOTES:
1. Characterized. Not tested.
2. This parameter measured oniy for the Initial qualification and after process or design changes which may
affect capacitance.
seeQ
MD4000191C
Technology, Incorporated
1-21
2804A
AC Characteristics
TTL Write Cycle TA=O° to 70°C; Vcc=5 V
± 10%, unless otherwise noted.
2804A-2S0
Symbol
Parameter
Min.
2804A-300
Max.
Min.
10
Max.
Units
10
ms
twc
Write Cycle Time
t AS
Address Set Up Time
10
10
ns
tAH
Address Hold Time
50
70
ns
tcs
Write Set Up Time
0
0
ns
tCH
Write Hold Time
0
0
ns
tcw
CE to End of Write Input
150
150
ns
tOES
OE Set Up Time
10
10
ns
tOEH
OE Hold Time
10
10
ns
WE Write Pulse Width
150
150
ns
Data Latch Time
50
50
ns
twp
(1)
tOl
tov
[2]
Data Valid Time
tos
Data Set Up Time
tOH
Data Hold Time
1
1
50
ns
0
0
ns
Notes:
1. WE is noise protected. Less than a 20 ns write pulse will not activate a write cycle.
2. Data must be valid within 1 ~s maximum after the initiation of a write cycle. Characterized, not tested.
TTL Byte Write Cycle
WE CONTROLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
ADDRESS
ADDRESS
CE
CE
OE
OE
WE
WE
DATA IN
DATA IN
seeQ
MD4000191C
Technology, Incorporated
I.l. s
50
1-22
2804A
Ordering Information
o
L
PACKAGE
TYPE
D - CERAMIC DIP
P - PLASTIC DIP
seeQ
MD4000191C
Q
2804A - 250
~TL2
~
_IL-
TEMPERATURE
RANGE
PART TYPE
-O°C TO + 70°C
(COMMERCIAL)
512
Q
Technology, Incorporated
x 8 EEPROM
ACCESS TIME
250 - 250
ns
300 -300 ns
1-23
1-24
seeQ
2816A15516A
Timer E2
16K Electrically Erasable PROMs
October 1988
Features
Description
•
High Endurance Write Cycles
• 5516A : 1,000,000 Cycles/Byte Minimum
• 2816A: 10,000 Cycles/Byte Minimum
•
On-Chip Timer
• Automatic Erase and Write Time Out
• 2 ms Byte Write Time (2816AH)
SEEQ's 5516A and 2816A are 5Vonly, 2Kx8 electrically
erasable programmable read only memories
(EEPROMs). EEPROMs are ideal for applications which
require non-volatility and in-system data modification. The
endurance, the minimum number of times that a byte may
be written, is 1 million for the 5516A and 10 thousand for
the 2816A. The 5516A's extraordinary high endurance
was accomplished using SEEQ's proprietary oxyntride
EEPROM process and its innovative Q Cell T", design. The
5516A is ideal for systems that require frequent updates.
•
AI/Inputs Latched by Write or Chip Enable
•
5 V± 10% PowerSupply
•
Power Up/Down Protection Circuitry
•
•
200 ns max. Access Time
Low Power Operation
• 110 mA max. Active Current
• 40 mA max. Standby Current
•
•
JEDEC Approved Byte-Wide Pinout
Military and Extended Temperature Range
Available
Both EEPROMs have an internal timer that automatically
times out the write time. A separate erase cycle is not
required and the minimum write enable (WE) pulse width
needs to be only 150 ns. The on-chip timer, along with the
inputs being latched by a write or chip enable signal edge,
frees the microcomputer system for other tasks during the
write time. The standard 2816A and5516A's write time is
10 ms, while the 2816AH's write time is a fast 2 ms. Once
Block Diagram
Pin Configuration
A7
Vee
As
As
As
Ag
A4
WE
A3
6E
A2
AlO
Al
CE
Ao
11°7
1/°0
IIOs
11°1
1I0 s
1/°2
1/°4
GND
110 3
Pin Names
A~-A~
CE
OE
WE
1/00 .7
11°0-7
o Cell is a trademark of SEEO Technology. Inc.
seeQ
MD4000161C
Technology, Incorporated
1-25
ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
WRITE ENABLE
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
2816AI5516A
Mode Selection
a byte is written, it can be read in 200 ns. The inputs are
TTL for both the byte write and read mode.
(Table 1)
Mode
CE
OE
WE
1/0
Device Operation
Read
V1L
V1L
V1H
There are five operational modes (see Table 1) and,
except for the chip erase mode {2J, only TTL inputs are
required. To write into a particular location, a TTL low is
applied to the write enable (WE) pin of a selected (CE low)
device. This, combined with output enable (OE) being
high, initiates a write cycle. During a byte write cycle,
addresses are latched on the last falling edge of CE or WE
and data is latched on the first rising edge of CE or WE. An
internal timer times out the required byte write time. An
automatic byte erase is performed internally in the byte
write mode.
Standby
V1H
X
X
DOUT
High Z
Byte Write
V1L
V1H
V1L
Write
Inhibit
X
X
V1L
X
X
V1H
DIN
High ZlDoUT
High ZlDoUT
X: any TTL level
Power Up/Down Considerations
The 2816A15516A has internal circuitry to minimize a false
write during system Vee power up or down. This circuitry
prevents writing under anyone of the following conditions.
1. Vee is less than 3VPJ
2. A negative Write Enable (WE) transition has not
occured when Vce is between 3 V and 5 V.
Absolute Maximum Stress Ratings""
Writing will also be prevented if CE or OE are in a logical
state other than that specified for a byte write in the Mode
Selection table.
Temperature
Storage ............................................ -65°C to +150°C
Under Bias ......................................... -10° C to +80° C
D. C. Voltage applied to all Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot/Overshoot pulse of less then 10 ns
(measured at 50% point) applied to all inputs or
outputs with respect to ground .... (undershoot) -1.0 V
(overshoot) + 7.0 V
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings· may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Recommended Operating Conditions
I Temperature Range (Ambient)
I Vee Supply Voltage
5516A15516AH
2816A12816AH
O°C to 70°C
5V± 10%
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
1,000,000[1)
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
NOTES:
1. 5516A-1 million cycles/byte.
2. Chip Erase is an optional mode.
3. Characterized. Not tested.
seeQ
MD4000161C
Technology, Incorporated
1-26
Condition
2816AI5516A
DC Operating Characteristics TA =0 0 to 70 0 e, vee =5 V ± 10% unless otherwise noted
Limits
Symbol
Parameter
Max.
Units
Icc
Active V cc Current
110
mA
CE = DE =VIL ; All I/O Open;
Other Inputs = 5.5 V
ISB
Standby V cc Current
40
mA
CE = V IH ' DE = V IL ; All I/O's
Open; Other Inputs = 5.5 V
Min.
Test Condition
III
Input Leakage Current
10
~A
V IN = 5.5 V
ILO
V IL
Output Leakage Current
10
~A
V OUT = 5.5 V
0.8
V
6
V
Input Low Voltage
-0.1
V IH
Input High Voltage
2.0
VOL
V OH
Output Low Voltage
0.4
Output High Voltage
2.4
V
IOL = 2.1 mA
V
IOH = -400 ~A
AC Characteristics
Read Operation TA =0° to 70° C, V cc=5 V ± 10% unless otherwise noted
Limits
Symbol
5516A15516AH·200
5516A15516AH·250 5516A15516AH·300
2816A12816AH·200
2816A12816AH·250 2816A12816AH-300
Min.
t RC
Read Cycle Time
200
tCE
Chip Enable Access Time
200
250
300
350
ns
tM
Address Access Time
200
250
300
350
ns
tOE
Output Enable Access Time
90
90
100
100
ns
tLZ
CE to Output in Low Z
tHZ
CE to Output in High Z
tOLZ
DE to Output in Low Z
tOHZ
DE to Output in High Z
tOH
[1]
[1]
CE to Power-up Time
tpD
[1]
CE to Power Down Time
Capacitance [2]
Min.
Max.
50
100
50
100
20
350
ns
100
50
100
20
ns
ns
0
50
ns
ns
100
20
0
50
ns
10
100
100
0
50
Min. Max. Units
50
20
0
Max.
10
10
100
Min.
300
250
10
Output Hold from Addr Change
tpu
Max.
2816A·350
Parameter
ns
50
ns
A.C. Test Conditions
TA = 25°C, f = 1 MHz
Symbol
Parameter
Max Conditions
C IN
Input Capacitance
COUT
Data (I/O) Capacitance
6 pF VIN = 0 V
10 pF VI/a = 0 V
E.S.D. Characteristics
Symbol
Parameter
Value
Test Conditions
V ZAP [1]
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V
NOTES:
1. Characterized. Not tested.
2. This parameter measured only for the initial qualification and after process or design changes which may affect capacitance.
seeQ
MD4000161C
Technology, Incorporated
1-27
2816A15516A
Read Cycle Timing
IRC
-'D(f-
. , k-
ADDRESS ' ) :
IM
r---IM--'
'-
\
Ce
ICE-'
J
f4--10~
DATA OUT
/
~
lOll
-
HIGHZ
~ILl~
VCC
SUPPLY
CURRENT
.., ....
\k-
OE
~IOH ...
D:
<4-IHZ~
K
DATA VALID
~IOHZ-.
~
DATA VALID
-
I
I
.IPU/
Icc
ISB
~Ipo----
AC Characteristics
Write Operation TA=0° to 70°C, V cc=5 V
± 10% unless otherwise noted
Limits
5516A·200
5516A·250
5516A·300
2816A12816AH·200 2816A12816AH·250 2816A12816AH·300
Symbol
Parameter
twc
Write Cycle Time
Min.
Max.
Min.
Max.
Max.
5516AH/2816AH
2
2
2
5516A12816A
10
10
10
2816A·350
Min. Max. Units
-
-
ms
10
t AS
Address Set Up Time
10
10
10
10
tAH
Address Hold Time
50
50
70
70
ns
tcs
Write Set Up Time
0
0
0
0
ns
ns
tCH
Write Hold Time
0
0
0
0
ns
tcw
CE to End of Write Input
150
150
150
150
ns
tOES
OE Set Up Time
10
10
10
10
ns
tOEH
t (1)
wp
OE Hold Time
10
10
10
10
ns
WE Write Pulse Width
150
150
150
150
ns
tOL
t (2)
ov
Data Latch Time
50
50
50
50
tos
Data Set Up Time
tOH
Data Hold Time
Data Valid Time
1
seeQ
MD4000161C
1
1
ns
1
J.ls
50
50
50
50
ns
0
0
0
0
ns
NOTES:
1. WE is noise protected. Less than a 20 ns write pulse will not activate a write cycle.
2. Data must be valid within 1 ~ maximum after the initiation of a write cycle.
'--
Min.
Technology. Incorporated
1-28
2816AJ5516A
TTL Byte Write Cycle
CE CONTROLLED WRITE CYCLE
WE CONTROLLED WRITE CYCLE
ADDRESS
ADDRESS
CE
CE
OE
OE
WE
WE
DATA IN
DATA IN
Ordering Information
o
Q
1
5516A
~~-~
- 200
tT,----o- - - - - - - ,
PACKAGE
TYPE
TEMPERATURE
RANGE
PART TYPE
EEPROM BYTE WRITE TIME
ACCESS TIME
D - CERAMIC DIP
P - PLASTIC DIP
UX - UNENCAPSULATED DIE
Q-O·C TO + 70·e
(COMMERCIAL)
2K x 8 EEPROM
(BLANK) - STANDARD WRITE TIME
H - FAST WRITE TIME
200 250 300 350 -
seeQ
MD4000161C
Technology, Incorporated
1-29
200
250
300
350
ns
ns
ns
ns
1-30
seeQ
2817A15517A
Timer E2
16K Electrically Erasable PROMs
October 1989
Features
Description
•
Ready/Busy Line for End-of-Write
•
High Endurance Write Cycles
• 5517A: 1,000,000 Cycles/Byte Minimum
• 2817A: 10,000 Cycles/Byte Minimum
•
On-Chip Timer
• Automatic Byte Erase Before Byte Write
·2 ms Byte Write Time (2817AH)
•
AI/Inputs Latched by Write or Chip Enable
•
5 V± 10% PowerSupply
SEEQ's 5517A and 2817A are 5V only, 2Kx8 electrically
erasable programmable read only memories
(EEPROMs). They are packaged in a 28 pin package and
have a readylbusy pin. These EEPROMs are ideal for
applications which require non-volatility and in-system
data modification. The endurance, the minimum number
of times which a byte may be written, is 1 million for the
5517A and 10 thousand for the 2817A. The 5517A's
extraordinary high endurance was acccomplished using
SEEQ's proprietary oxynitride EEPROM process and its
innovative Q CelfT M design. The 5517A is ideal for systems that require frequent updates and/or high reliability.
System reliability is enhanced greatly over lower specified
endurance EEPROMs while still maintaining 10 year data
retention.
•
Power Up/Down Supply
•
200 ns max. Access Time
•
10 Year Data Retention for Each Write
•
JEDEC Approved Byte-Wide Pinout
•
Military and Extended Temperature Range
Available
Both EEPROMs have an internal timer that automatically
times out the write time. The on-chip timer, along with the
input latches, frees the microcomputer system for other
tasks during the write time. The standard 5517A12817A 's
Block Diagram
Pin Configuration
RDY/BUSY
NC
Vcc
We
NC
A6
AS
AS
A4
A3
OE
A2
A10
Al
CE
AO
V07
VOl
1/°5
V0
V0
V0
2
GND
6
4
110 3
Pin Names
1/° 0-7
o Cell is a trademark of
seeQ
MD400014/C
SEEO Technology Inc.
Technology, Incorporated
1-31
Ao-Al0
ADDRESSES
CE
CHIP ENABLE
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/°0.7
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
RDY/BUSY
DEVICE READY/BUSY
NC
NO CONNECT
2817A15517A
Power Up/Down Considerations
The 2817Ai5517A has internal circuitry to minimize a false
write during system Vee power up or down. This circuitry
prevents writing under anyone of the following conditions.
1. Vee is less than 3VPJ
2. A negative Write Enable (WE) transition has not
occured with Vee is between 3 V and 5 V.
write time is 10 ms, while the 2817AH's write time is a fast
2 ms. An automatic byte erase is performed before a byte
operation is started. Once a byte has been written, the
readylbusy pin signals the microprocessor that it is available for either a write or read mode. The inputs are TTL for
both the byte write and read mode. Data retention is
specified for 10 years.
Writing will also be prevented if CE or OE are in TTL logical
states other than that specified for a byte write in the Mode
Selection table.
Device Operation
There are five operational modes (see Table1) and,
except for the chip erase mode f2l, only TTL inputs are
required. To write into a particular location, a TTL low is
applied to the write enable (WE) pin of a selected (CE low)
device. This, combined with output enable (OE) being
high, initiates a write cycle. During a byte write cycle,
addresses are latched on either the falling edge of CE or
WE, whichever one occurred last. Data is latched on the
rising edge of CE or WE, whichever one occurred first. The
byte is automatically erased before data is written. While
the write operation is in progress, the RO Y/BUSY output
is at a TTL/ow. An internal timer times out the required byte
write time and at the end of this time, the device signals the
ROY/BUSY pin to a TTL high. The ROY/BUSY pin is an
open drain output and a typical3K n. pull-up resistor to Vee
is required. The pull-up resistor value is dependent on the
number of OR-tied 2817A ROY/BUSYpins.
Absolute Maximum Stress Ratings'"
Temperature
Storage ............................................ -65°C to +150°C
Under Bias ........................................ -1 DoC to +80° C
D.C. Voltage applied to all Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot/Overshoot pulse of less then 10 ns
(measured at 50% point) applied to all inputs or
outputs with respect to ground .... (undershoot) -1.0 V
(overshoot) + 7.0 V
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings n may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Mode Selection (Table 1)
Mode/Pin CE
OE
WE
Read
VIL
VIH
VIL
VIH
X
X
Byte Write VIL
Write
X
Inhibit
X
VIH
VIL
Standby
X
I/O
ROY/BUSY
DOUT
HighZ
High Z
VIL
DIN
X
High ZlDoUT
High ZlDoUT
VOL
High Z
High Z
VIH
Recommended Operating Conditions
High Z
5517A
2817A12817AH
IVee Supply Voltage
ITemperature Range (Ambient)
5V± 10%
O°C to 70°C
X: any TTL level
Endurance and Data Retention
Condition
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
1,000,000[1[
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
NOTES:
1. 5517 A - 1 million cycleslbyte
2. Chip Erase is an optional mode.
3. Characterized. Not tested.
seeQ
MD400014/C
Technology, Incorporated
1-32
2817A15517A
D.C. Operating Characteristics
(Over the operating Vcc and temperature range)
Limits
Test Condition
Symbol
Parameter
Max.
Units
Icc
Active Vcc Current
(Includes Write Operation)
110
rnA
CE = OE =VIL; All 1/0 Open;
Other Inputs =5.5 V
ISB
Standby Vcc Current
40
rnA
CE = VIH ' OE = VIL; All 1/0
Open; Other Inputs = 5.5 V
III
ILO
Input Leakage Current
Output Leakage Current
10
10
0.8
IlA
Il A
VIN =5.5 V
Your =5.5 V
Vcc +1
V
V
IOL = 2.1 rnA
V
IOH
VIL
VIH
Input Low Voltage
VOL
VOH
Output Low Voltage
Min.
-0.1
2.0
Input High Voltage
V
0.4
2.4
Output High Voltage
=-400 IlA
A. C. Characteristics
Read Operation (Over the operating Vcc and temperature range)
Limits
2817AH·200
2817A·200
Symbol Parameter
t RC
Read Cycle Time
tCE
Chip Enable Access Time
tAA
Address Access Ti me
tOE
Output Enable Access Time
tDF
Output Enable High
to Output Not being Driven
Output Hold from Address
Change, Chip Enable, or
Output Enable whichever
occurs first
tOH
2817AH·250
5517A·250
2817A·250
2817AH·300
5517A·300
2817A·300
2817A·350
Min. Max. Min. Max.
Min. Max.
Min. Max. Units Test Conditions
200
300
350
250
200
200
90
60
0
300
300
100
60
250
250
90
60
0
0
350
350
100
80
0
Read Cycle Timing
~------
ADDRESSES
I RC:--------..;
ADDRESSES VALID
CE
OE
loti
O~PUT-------+---------~~~
seeQ
MD4000141C
Technology, Incorporated
1·33
VALID OUTPUT
ns
=OE = VIL
=VIL
CE = OE = VIL
ns
CE = VIL
ns
CE = VIL
ns
CE orOE =VIL
ns
CE
ns
OE
2817A15517A
Capacitance (1l
TA
= 25°C, f = 1 MHz
Symbol
Parameter
Max
Conditions
A.C. Test Conditions
C IN
Input Capacitance
6 pF
COUT
Data (I/O) Capacitance
10 pF
=0 V
VI/O = 0 V
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V
VIN
E.S.D. Characteristics
Symbol
Parameter
Value
Test Conditions
VZAP (2)
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
AC Characteristics
Write Operation (Over the operating Vcc and temperature range)
Limits
2817AH-200
2817A-200
2817AH-250
5517A-250
2817A-250
2817AH-300
5517A-300
2817A-300
2817A-350
Min. Max.
Min.
Min. Max.
Symbol
Parameter
Min.
t AS
Address to Write
Set Up Time
10
Max.
10
Max.
10
Units
10
ns
CE to Write Set Up Time
10
10
10
10
ns
WE Write Pulse Width
120
150
150
150
ns
tAH
Address Hold Time
50
50
50
70
ns
tos
Data Set Up Time
50
50
50
50
ns
tcs
twp
(3)
tOH
Data Hold Time
0
0
0
0
ns
tCH
CE Hold Time
0
0
0
0
ns
tOEs
OE Set Up Time
10
10
10
10
ns
tOEH
OE Hold Time
10
10
10
10
ns
tOL
Data Latch Time
50
50
50
50
(4)
Data Valid Time
ns
1
1
1
1
tOB
Time to Device Busy
120
120
120
120
Il s
ns
tWR
Write Recovery Time
Before Read Cycle
10
10
10
10
Il s
twc
2817A15517A
Byte Write Cycle Time
2817AH
10
10
10
10
ms
2
2
2
tov
ms
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not tested.
3. WE is noise protected. Less than a 20 ns write pulse will not activate a write cycle. Max. recommended twp is 150 iJ.S.
4. Data must be valid within 1 iJ.S maximum after the initiation of a write cycle.
seeQ
MD4000141C
Technology, Incorporated
1-34
2817AI5517A
Write Cycle Timing
tOES
OE
CE
WE
1/00-7
RDY/BUSY
I
I"'"..
- - - - - - - WRITE CYCLE
-------------l~~i"'---
READ CYCLE
~
Ordering Information
D
D
D
Q
Q
Q
5517A
2817A
2817A
- 250
- 250
H -250
~IT'----1T
PACKAGE
TEMPERATURE
RANGE
PART TYPE
EEPROM BYTE WRITE TIME
ACCESS TIME
D - CERAMIC DIP
P - PLASTIC DIP
UX - UNENCAPSULATED DIE
Q - O·C to + 70·C
2K x 8 EEPROM
(BLANK) - STANDARD WRITE TIME
H - FAST WRITE TIME
200 250 300 350 -
seeQ
MD4000141C
Technology, Incorporated
1-35
200
250
300
350
ns
ns
ns
ns
1-36
seeQ
286412864H
Timer E2
64K Electrically Erasable PROMs
November 1989
Features
the number of times which a byte may be written, is a
minimum of 10 thousand cycles.
• Ready/&Jsy Pin
• High Endurance Write Cycles
• 10,000 Cycles/Byte Minimum
The EEPROM has an internal timer that automatically
times out the write time. The on-chip timer, along with the
input latches, frees the microcomputer system for tasks
during the write time. The standard byte write cycle time
is 10 ms. For systems requiring faster byte write, a 2864H
is specified at 2 ms. An automatic byte erase is performed
before a byte operation is started. Once a byte has been
written, the readylbusy pin signals the microprocessor that
it is available for another write or a read cycle. All inputs
are TTL for both the byte write and read mode. Data retention is specified for ten years.
• On-Chip Timer
• Automatic Byte Erase Before Byte Write
• 2 ms Byte Write (2864H)
• 5 V± 10% Power Supply
• Power Up/Down Protection Circuitry
• 250 ns max. Access Time
• Military and Extended Temperature Range
Available
These two timer EEPROMs are ideal for systems with
limited board area. For systems where cost is important,
SEEQ has a latch only "52B" family at 16K and 64K bit
densities. AII"52B" family inputs, except for write enable,
are latched by the falling edge of the write enable signal.
Description
SEEQ's 2864 is a 5 V only, 8K x 8 NMOS electrically
erasable programmable read only memory (EEPROM). It
is packaged in a 28 pin package and has a readylbusy pin.
This EEPROM is ideal for applications which require nonvolatility and in-system data modification. The endurance,
Pin Configuration
DUAL-IN-L1NE
TOP VIEW
PLASTIC LEADED CHIP CARRIER
TOP VIEW
Block Diagram
Pin Names
110 _
07
seeQ
MD400002/B
Technology, Incorporated
1-37
Ao-A4
ADDRESSES - COLUMN (LOWER
ORDER BITS)
As-A12
CE
ADDRESSES - ROW
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00 •7
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
RDY/BUSY
DEVICE READY/BUSY
N/C
NO CONNECT
CHIP ENABLE
286412864H
Device Operation
Chip Erase
There are five operational modes (see Table 1) and, except
for the chip erase mode, only TTL inputs are required. To
write into a particular location, a 150 ns TTL pulse is applied
to the write enable (WE) pin of a selected (CE low) device.
This, combined with output enable (OE) being high, initiates a 10 ms write cycle. During a byte write cycle,
addresses are latched on either the falling edge of CE or
WE, whichever one occurred last. Data is latched on the
rising edge of CE or WE, whichever one occurred first. The
byte is automatically erased before data is written. While
the write operation is in progress, the ROY/BUSY output is
at a TTL low. An internal timer times out the required byte
write time and at the end of this time, the device signals the
ROY/BUSY pin to a TTL high. The ROY/BUSY pin is an
open drain output and a typical3Kn. pull-up resistor to Vee
is required. The pull-up resistor value is dependent on the
number of OR-tied ROY/BUSY pins. If ROY/BUSY is not
used it can be left unconnected.
Certain applications may require all bytes to be erased
simultaneously. This feature is optional and the timing
specifications are available from SEEQ.
Mode Selection
Power Up/Down Considerations
The 2864 has internal circuitry to minimize a false write
during system Vcc power up or down. This circuitry
prevents writing under anyone of the following conditions.
1. Vee is/essthan3V.f1 1
2. A negative Write Enable (WE) transition has not
occured when Vee is between 3 V and 5 V.
Writing will also be prevented if CE or OE are in TTL logical
states other than specified for a byte write in the Mode
Selection table.
Absolute Maximum Stress Ratings*
Temperature
Storage ............................................ - 65° C to + 150° C
Under Bias ........................................ -10°C to +80° C
(Table 1)
ROYI
1/0
WE
(27) (11.13,15·19)
ModelPin
CE
(20)
OE
(22)
Read
V IL
V IH
V IL
V IH
Standby
X
X
Byte Write
VIL
V IH
V IL
DIN
Write
Inhibit
X
X
V IL
X
High ZlDoUT
High ZlDoUT
X
V IH
DOUT
High Z
BUSY
(1)*
D.C. Voltage applied to all Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot/Overshoot pulse of less then 10 ns
(measured at 50% point) applied to all inputs or
outputs with respect to ground .... (undershoot) -1.0 V
(overshoot) + 7.0 V
High Z
HighZ
VOL
High Z
High Z
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
*Pin 1 has an open drain output and requires an external
3K resistor to Vcc. The value of the resistor is dependent
on the number of OR-tied RDY/BUSY pins.
Recommended Operating Conditions
2864H·250/H·300
2864·350
2864·2501·300
I Vcc Supply Voltage
I Temperature Range (Ambient)
5 V± 10%
5 V ± 10%
O°C to 70°C
O°C to 70°C
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
NOTES:
1. Characterized. Not tested.
seeQ
MD400002/B
Technology, Incorporated
1-38
Condition
286412864H
DC Operating Characteristics
(Over the operating Vee and temperature range)
Limits
Min.
Test Condition
Symbol
Parameter
Max.
Units
Icc
Active Vcc Current
(Includes Write Operation)
110
mA
CE = OE =VIL ; All 1/0 Open;
Other Inputs = Vee Max.
IS8
Standby Vec Current
40
mA
CE = V IH ' OE = V ll; All 1/0 Open;
Other Inputs = Vce Max.
III
ILO
Input Leakage Current
10
JlA
VIN = Vee Max.
Output Leakage Current
10
JlA
Your = Vec Max.
V IL
Input Low Voltage
-0.1
0.8
V
V IH
Input High Voltage
2.0
V
VOL
VOH
Output Low Voltage
Vce +1
0.4
Output High Voltage
2.4
V
IOl=2.1 mA
V
IOH = -400 JlA
AC Characteristics
Read Operation (Over the operating Vec and temperature range)
Limits
2864H-250
2864-250
2864H-300
2864-300
Min.
2864-350
Symbol
Parameter
Min.
t RC
Read Cycle Time
250
teE
Chip Enable Access Time
250
300
350
tAA
Address Access Time
250
300
350
ns
90
100
100
ns
CE = OE =VIL
CE = VIL
80
ns
CE = VIL
ns
CE orOE = VIL
tOE
Output Enable Access Time
tOF
Output Enable High to Output
Not being Driven
0
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable whichever occurs first
0
Read Cycle Timing
Max.
Max.
300
60
0
0
Min.
Max.
350
60
0
ns
0
1'4------tRC-----~
ADDRESSES
OUTPUT
ADDRESSES VALID
-----+------+-+-+-<
NOTES:
1. OE may be delayed to tM - tOE after the falling edge of
2. t OF is specified from OE or CE, whichever occurs first.
seeQ
MD4000021B
Technology, Incorporated
1-39
Units Test Conditions
CE without impact on tM'
ns
CE = OE = V il
OE = VIL
286412864H
Capacitance
A.C. Test Conditions
TAll) = 25°C, f = MHz
Symbol
Parameter
Max
Conditions
C IN
Input Capacitance
6 pF
V IN
COUT
Data (I/O) Capacitance
10 pF
V I/0
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V
=0 V
=0 V
E.S.D. Characteristics[4]
Symbol
Parameter
Value
Test Conditions
V ZAP
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
AC Characteristics
Write Operation (Over operating temperature and Vcc range)
Limits
2864H-250
2864-250
Min.
Max.
2864H-300
2864-300
Symbol
Parameter
twc
Write Cycle Time /Byte
Standard Family Only
Min.
tAS
Address to WE Set Up Time
10
10
tcs
CE to Write Set Up Time
0
twp12)
WE Write Pulse Width
tAH
10
Min.
10
2
2
"H" Family Only
Max.
2864-350
Max.
Units
10
ms
-
ms
10
ns
0
0
ns
150
150
150
ns
Address Hold Time
50
50
70
ns
tos
Data Set Up Time
50
50
50
ns
tOH
Data Hold Time
20
20
20
ns
tCH
CE Hold Time
0
0
0
ns
tOES
OE Set Up Time
10
10
10
ns
tOEH
OE Hold Time
10
10
10
ns
tOL
t 13)
OV
Data Latch Time
50
tOB
tWR
Data Valid Time
50
50
ns
1
1
1
Time to Device Busy
200
200
200
ns
Write Recovery Time
Before Read Cycle
10
10
10
Jls
Jls
NOTES:
1. This parameter measured only for the initial qualification and after process or design changes which may affect capacitance.
2. WE is noise protected. Less than a 20 ns write pulse will not activate a write cycle.
3. Data must be valid within 1 ~ maximum after the initiation of a write cycle.
4. Characterized. Not tested.
seeQ
MD4000021B
Technology, Incorporated
1-40
286412864H
Write Cycle Timing
tOES
OE
CE
WE
1/00-7
ROY/BUSY
Ordering Information
D
D
Q
Q
2864
2864
-250
H - 250
~IT<------,T
PACKAGE
TYPE
TEMPERATURE
RANGE
0- CERAMIC DIP
P - PLASTIC DIP
N - PLASTIC LEADED
CHIP CARRIER
UX - UNENCAPSULATED DIE
Q - DOC to + 7DOC
seeQ
MD4000021B
DEVICE TYPE
BK x B EEPROM
(COMMERCIAL)
Technology, Incorporated
1-41
EEPROM WRITE TIME
ACCESS TIME
(BLANK) - STANDARD WRITE TIME
H - FAST WRITE TIME
250 = 250 ns
300 - 300 ns
350 - 350 ns
1-42
seeQ
28C64
Timer E2
64K Electrically Erasable PROM
October 1989
Features
Description
•
CMOS Technology
•
LowPower
• 50 mA Active
• 150 /JA Standby
•
Page Write Mode
• 64 Byte Page
• 160 us Average Byte Write Time
•
Byte Write Mode
•
Write Cycle Completion Indication
• DA TA Polling
•
On-Chip Timer
• Automatic Erase Before Write
SEEO's 28C64 is a CMOS 5V only, 8K x 8 Electrically
Erasable Programmable Read Only Memory (EEPROM). It
is manufactured using SEEO's advanced 1.25 micron
CMOS Process and is available in both a 28 pin Cerdip
package as well as a Plastic Leaded Chip Carrier (PLCC).
The 28C64 is ideal for applications which require low power
consumption, non-volatility and in system reprogrammability. The endurance, the number of times a byte can be
written, is specified at 10, 000 cycles per byte and is typically
1, 000, 000 cycles per byte. The extraordinary high endurance was accomplished using SEEO's proprietary oxynitride EEPROM process and its innovative 0 CelfM design.
System reliability, in all applications, is higher because of
the low failure rate of the 0 Cell.
•
High Endurance
·10,000 Cycles/Byte
• 10 Year Data Retention
•
Power Up/Down Protection Circuitry
•
200 ns Maximum Access Time
•
JEDEC Approved Byte Wide Pinout
•
Military and Extended Temperature
Range Available
Pin Configuation
DUAL-IN-LiNE
TOP VIEW
PLASTIC LEADED CHIP CARRIER
TOP VIEW
Vcc
WE
NC
As
Ag
A11
De
Block Diagram
A,O
CE
A2
1107
VOs
VO s
VO.
V03
Pin Names
Ao-As
ADDRESSES-COLUMN
As-AI2
ADDRESSES-ROW
CE
CHIP ENABLE
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00 _7
DATA INPUT (WRITE)/DATA
OUTPUT (READ)
NC
NO CONNECTION
11°0_7
o Cell is a trademark of SEEO Technology, Inc_
seeQ
MD4000041D
Technology, Incorporated
1-43
28C64
The 28C64 has an internal timer which automatically times
out the write time. The on-chip timer, along with input
latches free the microprocessor for other tasks while the
part is busy writing. The 28C64's write cycle time is 10 ms.
An automatic erase is performed before a write. The DATA
polling feature of the 28C64 can be used to determine the
end of a write cycle. Once the write has been completed, data can be read in a maximum of 200 ns. Data retention
is specified for 10 years.
Device Operation
Operational Modes
There are five operational modes (see Table 1) and, except
for the chip erase mode, only TTL inputs are required. A
Write can only be initiated under the conditions shown.
Any other conditions for CE, OE, and WE will inhibit writing
and the 110 lines will either be in a high impedance state or
have data, depending on the state of aforementioned three
latched on the rising edge of WE or CJ; whichever occurred first. An automatic erase is performed before data
is written.
Write Cycle Control Pins
For system design simplification, the 28C64 is designed
such that either the CE or WE pin can be used to initiate a
write cycle. The device uses the latest high-to-Iow transition of either CE orWE signal to latch addresses and the
earliest low-to-high transition to latch the data. Address
and OE setup and hold are with respect to the later of CE
or WE; data setup and hold is with respect to the earlier of
WEorCE.
To simplify the following discussion, the WE pin is used as
the write cycle control pin throughout the rest of this data
sheet. Timing diagrams of both write cycles are included
in the AC Characteristics.
input lines.
Write Mode
Mode Selection
One to 64 bytes of data can be randomly loaded into the
page. The part latches row addresses, A6-A 12, during the
first byte write. These addresses are latched on the falling
edge of the WE signal and are ignored after that until the
end of the write cycle. This will eliminate any false write
into another page if different row addresses are applied
and the page boundary is crossed.
Mode
CE
OE
WE
1/0
Read
VIL
VIL
VIH
DOUT
Standby
Write
VIH
VIL
X
VIH
X
VIL
Write
Inhibit
X
X
VIL
X
X
VIH
Chip Erase
VIL
VH
VIL
HighZ
DIN
High
High
ZlDouT
The column addresses, AO-A5, which are used to select
different locations of the page, are latched every time a
new write initiated. These addresses and the OE state
(high) are latched on the falling edge of WE signal. For
proper write initiation and latching, the WE pin has to stay
low for a minimum of twp ns. Data is latched on the rising
edge of WE, allowing easy microprocessor interface.
ZlDouT
X
X: Any TTL level
VH: High Voltage
Reads
A read is accomplished by presenting the address of the
desired byte to the address inputs. Once the address is
stable, CE is brought to a TTL low in order to enable the
chip. The WE pin must be at a TTL high during the entire
read cycle. The output drivers are made active by bringing
Output Enable (OE) to a TTL low. During read, the
address, CE ,OE, and 110 latches are transparent.
Writes
To write into a particular location, the address must be
valid and a TTL low applied to the Write Enable (WE) pin
of a selected (CE low) device. This combined with Output
Enable (OE) being high, initiates a write cycle. During write
cycle, all inputs except data are latched on the falling edge
of WE or CE, whichever occurred last. Write enable needs
to be at a TTL low only for the specified twp time. Data is
seeQ
MD4000041D
Technology, Incorporated
1-44
Upon a low to high WE transition, the 28C64 latches data
and starts the internal page load timer. The timer is reset
on the falling edge of the WE signal if another write is
initiated before the timer has timed out. The timer stays
reset while the WE pin is kept low. If no additional write
cycles have been initiated within tBLC after the last WE low
to high transition, the part terminates the page load cycle
and starts the internal write. During this time which takes
a maximum of 10 ms, the device ignores any additional
write attempts. The part can be read to determine the end
of write cycle (DATA polling).
Extended Page Load
In order to take advantage of the page mode's faster
average byte write time, data must be loaded at the page
load cycle time (tBLC). Since some applications may not
28C64
Power Up/Down Considerations
There is internal circuitry to minimize a false write during
power up or power down. This circuitry prevents writing
under anyone of the following conditions:
be able to sustain transfers at this minimum rate, the 28C64
permits an extended page load cycle. To do this, the write
cycle must be "stretched" by maintaining WE low, assuming a write enable-controlled cycle, and leaving all other
control inputs (CE, OE) in the proper page load cycle state.
Since the page load timer is reset on the falling edge of WE,
keeping this signal low will not start the page load timer.
When WE returns high, the input data is latched and the
page load cycle timer begins. In CE controlled write the
same is true, with CE holding the timer reset instead oWE.
wy.
1. Vee is less than V
2. A high to low Write Enable (WE) transition has not
occurred when the VCS<.!.upply is between VWI V and
Vee with CE low and OE high.
Writing will also be inhibited when WE, CE, or OE are in
TTL/ogical states other than that specified for a write in the
Mode Selection table.
DATA Polling
The 28C64 has a maximum write cycle time of 10 ms.
Typically though, a write will be completed in less than the
specified maximum cycle time. DATA polling is a method
of minimizing write times by determining the actual endpoint of a write cycle. If a read is performed to any address
while the 28C64 is still writing, the device will present the
ones-complement of the last byte written. When the 28C64
has completed its write cycle, a read from the last address
written will result in valid data. Thus, software can simply
read from the part until the last data byte written is read
correctly.
Absolute Maximum Stress Range*
Temperature
Storage ............................................ -65°C to + 150°C
Under Bias ......................................... -10°C to +80°C
A DATA polling read can occur immediately after a byte is
loaded into a page, prior to the initation of the internal write
cycle. DATA polling attempted during the middle of a page
load cycle will present a ones-complement of the most
recent data byte loaded into the page. Timing for a DATA
polling read is the same as a normal read.
Chip Erase
Certain applications may require all bytes to be erased simultaneously. This feature, which requires high voltage, is
optional and timing specifications are available from SEEQ.
seeQ
MD4000041D
Technology, Incorporated
1-45
D. C. Voltage applied to all Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot pulse of less then 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground ...................................... -1.0 V
Overshoot pulse of less than 10 ns (measured at
50% point )applied to all inputs or outputs
with respect to ground ..................................... + 7.0 V
·COMMENT: Stresses beyond those listed under '~bso
lute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
28C64
Recommended Operating Conditions
28C64
I
I Vee Power Supply
Temperature Range (Ambient)
O°C to 70°C
5 V ± 10%
Endurance and Data Retention
Condition
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL·STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL·STD 883 Test
Method 1008
DC Characteristics
(Over operating temperature and Vcc range, unless otherwise specified)
Limits
Max.
Units
50
mA
CE = OE =VIL ; All I/O Open;
Other Inputs = Vee Max.;
Max read or write cycle time
Standby Vcc Current
(TTL Inputs)
2
mA
CE = VIH , OE = V IL; All I/O Open;
Other Inputs = ANY TTL LEVEL
Standby Vcc Current
(CMOS Inputs)
200
flA
CE = Vcc -0.3
Other Inputs = V IL to VIH
All I/O Open
Symbol
Parameter
lec
Active Vce Current
1561
1562
Min.
I [2]
IL
Input Leakage Current
IOL
Output Leakage Current
V IL
Input Low Voltage
-0.3
VIH
Input High Voltage
2.0
VOL
VOH
Output Low Voltage
VWI
[1]
1
flA
VIN = Vcc Max.
10
flA
VOUT = Vec Max.
0.8
V
6
V
0.45
V
IOL = 2.1 mA
IOH = -400 IJA
Output High Voltage
2.4
V
Write Inhibit Voltage
3.8
V
NOTES:
1. Characterized. Not tested.
2. Inputs only. Does not include 1/0.
seeQ
MD4000041D
Test Condition
Technology, Incorporated
1-46
28C64
Capacitance [1} TA = 25°C, f = 1 MHz
A.C. Test Conditions
Symbol
Parameter
Max
Conditions
C IN
Input Capacitance
6 pF
V IN =
0V
C OUT
Data (1/0) Capacitance
12 pF
VI/o =
0V
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V
E.5. D~ Characteristics
Symbol
V ZAP
12]
Parameter
Value
Test Conditions
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
AC Characteristics
Read Operation (Over operating temperature and Vcc Range, unless otherwise specified)
Limits
28C64-200
Symbol
28C64-250
28C64-300
28C64-350
Test
Conditions
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Units
t RC
Read Cycle Time
200
ns
CE = OE =V IL
tCE
Chip Enable Access Time
200
250
300
350
ns
tAA
Address Access Time
200
250
300
350
ns
OE = V IL
CE = OE = V IL
tOE
Output Enable Access Time
90
ns
CE = V IL
tOF
Output or Chip Enable High to
output not being driven
0
80
ns
CE
= V IL
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
ns
CE
= OE = V IL
250
80
60
300
90
0
0
60
350
90
0
0
80
0
0
Read/Data Polling Cycle Time
} 4 - - - - - lAC ---~~
ADDRESSES
ADDRESSES AN
DATA_~H~IG~H~Z~_ _ _ _ _ _ _ _~~
t 4 - - - - - 1M
--~~
NOTES:
1. This parameter is measured only for the in~ial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not tested.
seeQ
MD4000041D
Technology, Incorporated
1-47
28C64
AC Characteristics
Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
28C64-200
Max.
28C64-300
Min.
Min.
Max.
Max.
28C64-350
Min.
Max.
Units
10
ms
Symbol
Parameter
twc
Write .Cycle Time
tAS
Address Set-up Time
10
10
10
10
tAH
Address Hold Time (see note 1)
150
150
150
150
ns
tes
Write Set-up Time
0
0
0
0
ns
tCH
Write Hold Time
tew
CE Pulse Width (note 2)
Min.
28C64-250
10
10
10
ns
0
0
0
0
ns
150
150
150
150
ns
tOES
OE High Set-up Time
10
10
10
10
ns
tOEH
OE High Hold Time
10
10
10
10
ns
twp
WE Pulse Width (note 2)
150
150
150
150
ns
tos
Data Set-up Time
50
50
50
50
ns
tOH
Data Hold Time
0
0
0
0
ns
t SlC
Byte Load Timer Cycle
(Page Mode Only) (see note 3)
t lP
Last Byte Loaded
to DATA Polling
0.2
300
0.2
300
200
200
0.2
300
200
0.2
300
us
200
ns
Write Timing
WE CONTROLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
NOTES:
1 Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3.
min. is the minimum time before the next byte can be loaded.
max. is the minimum time the byte load timer
waits before initiating internal write cycle.
tac
seeQ
MD4000041D
tac
Technology, Incorporated
1-48
28C64
Page Write Timing
~------------------------PAGELOAD------------------~I
_____
.
WE
DATA
HIGHZ
#
r--.
,
------<
Ordering Information
2TT
D
seeQ
MD4000041D
Q
28C64 - 250
PACKAGE
TEMPERATURE
RANGE
PART TYPE
ACCESS TIME
D - CERAMIC DIP
P - PLASTIC DIP
N - PLASTIC LEADED
CHIP CARRIER
UX - UNENCAPSULATED DIE
a - O°C to + 70°C
8Kx 8 EEPROM
200 250 ~
300 350 -
(COMMERCIAL)
Technology, Incorporated
1-49
200 ns
250 ns
300 ns
350 ns
1-50
seeQ
28C65
Timer E2
64K Electrically Erasable PROM
October 1989
Features
•
•
•
•
•
•
•
•
•
•
•
Description
SEEO's 28C65 is a CMOS 5V only, BK x 8 Electrically
Erasable Programmable Read Only Memory (EEPROM).
It is manufactured using SEEO's advanced 1.25 micron
CMOS Process and is available in both a 28 pin Cerdip
package as well as a Plastic Leaded Chip Carrier (PLCC).
The 28C65 is ideal for applications which require low
power consumption, non-volatility and in system reprogrammability. The endurance, the number of times a byte
can be written, is specified at 10,000 cycles per byte and
is typically 1,000,000 cycles per byte. The extraordinary
high endurance was accomplished using SEEO's proprietary oxynitride EEPROM process and it's innovative
Cell TAI design. System reliability, in all applications, is
higher because of the low failure rate of the 0 Cell.
CMOS Technology
Low Power
• 50 mA Active
• 150 IlA Standby
Page Write Mode
• 64 Byte Page
• 160 us Average Byte Write Time
Byte Write Mode
Write Cycle Completion Indication
• DATA POlling
• RDY/BUSY Pin
On-Chip Timer
• Automatic Erase Before Write
High Endurance
• 10,000 Cycles/Byte
• 10 Year Data Retention
Power Up/Down Protection Circuitry
200 ns Maximum Access Time
o
Pin Configuration
DUAL-IN-LiNE
TOP VIEW
JEDEC Approved Byte Wide Pinout
Military and Extended Temperature Range
Available
PLASTIC LEADED CHIP CARRIER
TOP VIEW
Vcc
WE
NC
A8
Block Diagram
A9
A'1
6E
A
'0
CE
V07
vOs
RDYIflUSY
---------1-----,
VO ,
V0 5
V0 2
V0
GND
VOl
'---"
4
Pin Names
CE
Ao-A5
ADDRESSES - COLUMN
WE
A6- A 12
ADDRESSES - ROW
CE
CHIP ENABLE
110 0-7
Q Cell is a trademark of SEEQ Technology, Inc.
seeQ
MD4000251C
Technology, Incorporated
1-51
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00 _7
DATA INPUT (WRITE)
DATA OUTPUT (READ)
RDY/SUSY
DEVICE READY/BUSY
NC
NO CONNECTION
28C65
ofWE' orCE, whichever occurred last. Write enable needs
to be at a TTL low only for the specified tw.e.!!..me. Data is
latched on the rising edge of WE' or CE, whichever
occurred first. An automatic erase is performed before
data is written.
The 28C65 has an internal timer which automatically times
out the write time. The on-chip timer, along with input
latches free the microprocessor for other tasks while the
part is busy writing. The 28C65's write cycle time is 10 ms.
An automatic erase is performed before a write. The DATA
polling feature of the 28C65 can be used to determine the
end of a write cycle. Once the write has been completed,
data can be read in a maximum of 200 ns. Data retention
is specified for 10 years.
Write Cycle Control Pins
For system design simplification, the 28C65 is designed
such that either the CE or WE pin can be used to initiate a
write cycle. The device uses the latest high-to-Iow transition of either CE or WE signal to latch addresses and the
earliest low-to-high transition to latch the data. Address
and OE setup and hold are with respect to the later of CE
or WE; data setup and hold is with respect to the earlier of
WE or CE
Device Operation
Operational Modes
There are five operational modes (see Table 1) and, except
for the chip erase mode, only TTL inputs are required. A
write can only be initiated under the conditions shown. Any
other conditions for CE, OE, and WE' will inhibit writing and
the 110 lines will either be in a high impedance state or have
data, depending on the state of aforementioned three input
lines.
To simplify the following discussion, the WE pin is used as
the write cycle control pin throughout the rest of this data
sheet. Timing diagrams of both write cycles are included
in the AC Characteristics.
Mode Selection (Table 1)
Mode
ce oe we
I/O
Read
V IL
V IL
V IH
DOUT
HIGHZ
Standby
V IH
X
X
HighZ
HIGHZ
Write
V IL
V IH
V IL
DIN
Write
Inhibit
X
X
V IL
X
X
V IH
V IL
VH
V IL
Chip Erase
High
High
One to 64 bytes of data can be randomly loaded into the
page. The part latches row addresses, A6-A 12, during the
first byte write. These addresses are latched on the falling
edge of the WE signal and are ignored after that until the
end of the write cycle. This will eliminate any false write
into another page if different row addresses are applied
and the page boundary is crossed.
VOL
ZlDoUT
HIGHZ
HIGHZ
X
HIGHZ
ZlDoUT
Write Mode
ROY/BUS?(1)
The column addresses, AO-A5, which are used to select
different locations of the page, are latched every time a
new write initiated. These addresses and the OE state
(high) are latched on the falling edge of WE' signal. For
proper write initiation and latching, the WE pin has to stay
low for a minimum of twp ns. Data is latched on the rising
edge of WE, allowing easy microprocessor interface.
X: Any TTL level
VH : High Voltage
Reads
A read is accomplished by presenting the address of the
desired byte to the address inputs. Once the address is
stable, CE is brought to a TTL low in order to enable the
chip. The WE pin must be at a TTL high during the entire
read cycle. The output drivers are made active by bringing
Output Enable (OE) to a TTL low. During read, the
address, CE, OE, and 110 latches are transparent.
Upon a low to high WE transition, the 28C65 latches data
and starts the internal page load timer. The timer is reset
on the falling edge of the WE signal if another write is
initiated before the timer has timed out. The timer stays
reset while the WE pin is kept low. If no additional write
cycles have been initiated within tSLC after the last WE low
to high transition, the part terminates the page load cycle
and starts the internal write. During this time which takes
a maximum of 10 ms, the device ignores any additional
write attempts. The part can be read to determine the end
of write cycle (DATA polling).
Writes
To write into a particular location, the address must be
valid and a TTL low applied to the Write Enable (WE) pin
of a selected (CE low) device. This combined with Output
Enable (OE) being high, initiates a write cycle. During write
cycle, all inputs except data are latched on the falling edge
NOTES:
1. ROY/BUSY Pin 1(Pin 2 on PLCC) has an open drain output and requires an external3K resistor to V cc' The value of the resistor
is dependent on the number of OR-tied ROY/BUSY pins.
seeQ
A4D4000251C
Technology, Incorporated
1-52
28C65
Extended Page Load
In order to take advantage of the page mode's faster
average byte write time, data must be loaded at the page
load cycle time (tsLd. Since some applications may not be
able to sustain transfers at this minimum rate, the 28C65
permits an extended page load cycle. To do this, the write
cycle must be "stretched" by maintaining WE low, assuming a write enable-controlled cycle, and leaving all other
control inputs (CE, OE) in the proper page load cycle state.
Since the page load timer is reset on the falling edge of WE,
keeping this signal low will not start the page load timer.
When WE returns high, the input data is latched and the
page load cycle timer begins. In CE controlled write the
same is true, with CE holding the timer reset instead of WE
3 K pull-up resistor to Vee is required. The pull-up value
is dependent on the number of OR-tied ROY/BUSY pins.
If ROY/BUSY is not used it can be left unconnected.
Chip Erase
Certain applications may require all bytes to be erased
simultaneously. This feature, which requires high voltage, is optional and timing specifications are available
from SEEQ.
Power Up/Down Considerations
There is internal circuitry to minimize a false write during
power up or power down. This circuitry prevents writing
under anyone of the following conditions:
1. Vee is less than VWIV,
2. A high to low Write Enable (WE) transition has not
occurred when the Vee supply is between VWI V and
Vee with CE low and OE high.
DATA Polling
The 28C65 has a maximum write cycle time of 10 ms.
Typically though, a write will be completed in less than the
specified maximum cycle time. DATA polling is a method
of minimizing write times by determining the actual endpoint of a write cycle. If a read is performed to any address
while the 28C65 is still writing, the device will present the
ones-complement of the last byte written. When the 28C65
has completed its write cycle, a read from the last address
written will result in valid data. Thus, software can simply
read from the part until the last data byte written is read
correctly.
Writing will also be inhibited when WE, CE, or OE are in
TTL logical states other than that specified for a write in the
Mode Selection table.
Absolute Maximum Stress Range*
Temperature
Storage ........................................... - 6f1' C to + 15(JJ C
Under Bias ........................................ -1(JJC to +8(JJC
A DATA polling read can occur immediately after a byte is
loaded into a page, prior to the initiation of the internal write
cycle. DATA polling attempted during the middle of a page
load cycle will present a ones-complement of the most
recent data byte loaded into the page. Timing for a DATA
polling read is the same as a normal read.
O. C. Voltage applied to all Inputs or Outputs
with respect to ground ...................... +6.0 V to -0.5 V
Undershoot pulse of less then 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground ..................................... -1.0 V
Overshoot pulse of less than 10 ns (measured at
50% point )applied to all inputs or outputs
with respect to ground .................................... + 7.0 V
READY/BUSY Pin
28C65 provides write cycle status on this pin. ROY/BUSY
output goes to a TTL low immediately after the falling edge
of WE ROY/BUSY will remain low during the byte load or
page load cycle and continues to remain at a TTL low while
the write cycle is in progress. An internal timer times out the
required write cycle time and at the end of this time, the
device signals ROY/BUSYpin to a TTL high. This pin can
be polled for write cycle status or used to initiate a rising
edge triggered interrupt indicating write cycle completion.
The ROY/BUSY pin is an open drain output and a typical
seeQ
M0400025/C
·COMMENT: Stresses beyond those listed under '~bso
lute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Technology, Incorporated
1-53
28C65
Recommended Operating Conditions
I Temperature Range (Ambient)
I Vee Power Supply
28C65
O°C to 70°C
5V± 10%
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
DC Characteristics
Condition
(Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol
Parameter
Min.
Max.
Units
Icc
Active Vee Current
50
mA
CE = OE =V IL : All 1/0 Open;
Other Inputs = Vee Max;
Max read or write cycle time
IS81
Standby Vee Current
(TTL Inputs)
2
mA
CE = VIH, OE = V IL; All 110 Open;
Other Inputs = ANY TTL LEVEL
IS82
Standby Vee Current
(CMOS Inputs)
200
IlA
CE = Vee -0.3
Other Inputs = VIL to VIH
All 110 Open
I [2J
IL
IOL
VIL
Input Leakage Current
1
10
IlA
IlA
VIN
Output Leakage Current
V
Input Low Voltage
-0.3
0.8
2.0
6
V
0.45
V
IOL = 2.1 mA
2.4
V
IOH = -400 IlA
3.8
V
Output Low Voltage
Output High Voltage
VWI [lJ
Write Inhibit Voltage
NOTES:
1 . Characterized. Not tested.
2. Inputs only. Does not include 110.
~D400025/C
= Vee Max.
VOUT = Vee Max.
Input High Voltage
VIH
VOL
VOH
seeQ
Test Condition
Technology, Incorporated
1-54
28C65
Capacitance tt]
TA
= 25°C, f = 1 MHz
Symbol
Parameter
Max
Conditions
C IN
Input Capacitance
6 pF
VIN = 0 V
C OUT
Data (I/O) Capacitance
12 pF
Vila = 0 V
A.C. Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V
E.S.D. Characteristics
Symbol
Parameter
Value
Test Conditions
VZAP [21
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
AC Characteristics
Read Operation (Over operating temperature and Vcc Range, unless otherwise specified)
Limits
28C65-250
Parameter
Min. Max.
Min. Max.
Min.
t RC
Read Cycle Time
200
250
300
ns
CE = OE =VIL
tCE
Chip Enable Access Time
200
250
300
350
ns
tAA
Address Access Time
200
250
300
350
ns
tOE
Output Enable Access Time
150
ns
OE = V IL
CE = OE = V IL
CE = V IL
tOF
Output or Chip Enable High to
output not being driven
0
80
ns
CE = V IL
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, which ever occurs first
0
ns
CE = OE = V IL
Symbol
90
80
60
28C65-300
Test
28C65-200
0
0
60
Max.
28C65-350
Min.
350
150
0
0
Max. Units Conditions
80
0
0
Read/Data Polling Cycle Time
~----tRC----~
ADDRESSES
AD DRESSES AN
CE
OE
DATA_---'-H""'IG:::,.H'-'Z"--+-_ _ _ _ _ _+_<
~---tAA.-----.-j
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes may affect capacitance.
2. Characterized. Not tested.
seeQ
MD4000251C
Technology, Incorporated
1-55
28C65
A C Characteristics
Read Operation (Over the operating temperature and Vcc Range, unless otherwise specified)
Limits
28C65-250
28C65-200
Symbol
Parameter
twc
Write Cycle Time
t AS
Address Set-up Time
tAH
Address Hold Time (see note 1)
tcs
Write Set-up Time
tCH
Write Hold Ti me
tcw
CE Pulse Width (note 2)
tOES
OE High Set-up Time
tOEH
OE High Hold Time
twp
WE Pulse Width (note 2)
tos
Data Set-up Time
Min.
Max.
Min.
10
28C65-300
Min.
10
10
150
0
0
150
10
10
150
50
10
150
0
0
150
10
10
150
50
0
0.2
Max.
0
0.2
tOH
Data Hold Ti me
Byte Load Timer Cycle
(Page Mode Only) (note 3)
t LP
Last Byte Loaded
to DATA Polling
200
200
tOB
Time to Device Busy
100
100
300
28C65-350
,Min.
10
10
150
0
0
150
10
10
150
50
tSlC
300
Max.
0
0.2
Max.
Units
10
ms
10
150
0
0
150
ns
ns
ns
ns
ns
10
10
150
50
300
0
0.2
ns
ns
ns
ns
ns
300
us
200
200
ns
100
100
ns
Write Timing
WE CONTOLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
oe
Of
CE
WE
WE
Ce
DATA
DATA
RDYIBUSY
RDY/BUSY
NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. talC min. is the minimum time before the next byte can be loaded. talC max. is the minimum time the byte load timer waits before initiating
the internal write cycle.
seeQ
MD4000251C
Technology, Incorporated
1-56
28C65
Page Write Timing
f 4 - - - - - - - - - - PAGE LOAD - - - - - - - - - ; - - -
~::::::
OE
WE
,--,
,::;il------<
DATA
Ordering Information
D
Q
28C65 - 250
~TT
PACKAGE
TEMPERATURE
RANGE
PART TYPE
D = CERAMIC DIP
P = PLASTIC DIP
N = PLASTIC LEADED
CHIP CARRIER
UX = UNENCAPSULATED DIE
Q
= O°C to + 70°C
(COMMERCIAL)
8K x 8 EEPROM
seeQ
MD4000251C
Technology, Incorporated
1-57
ACCESS TIME
200 = 200
250 = 250
300 = 300
350 = 350
ns
ns
ns
ns
1-58
seeQ
28C256
Timer E2
256K Electrically Erasable PROM
October 1989
Features
Description
••
•
SEEQ's 28C256 is a C~OS 5V only, 32K x 8 Electrically
Erasable Programmable Read Only ~emory (EEPRO~).
It is manufactured using SEEQ's advanced 1.25 micron
C~OS Process and is available in a 28 pin Cerdip package
a Plastic Leadless Chip Carrier (PLCC) as well as a
Leadless Chip Carrier (LCC). The 28C256 is ideal for
applications which require low power consumption, non·
volatility and in system reprogrammability. The enduro
ance, the number of times a byte can be written, is
specifiedat 10,000 cycles per byte andis typically 1,000,000
cycles per byte. The extraordinary high endurance was
accomplished using SEEQ's proprietary
oxynitride
EEPRO~ process and its innovative Q CeffTM design.
System reliability, in all applications, is higher because of
the low failure rate of the Q Cell.
•
•
•
•
•
•
•
CMOS Technology
Low Power
• 60 mA Active
• 150 pA Standby
Page Write Mode
• 64 Byte Page
• 160 us Average Byte Write Time
Byte Write Mode
Write Cycle Completion Indication
• DATA Polling
On-Chip Timer
• Automatic Erase Before Write
High Endurance
·10,000 Cycles/Byte
• 10 Year Data Retention
Pin Configuration
Power Up/Down Protection Circuitry
DUAL·IN·LlNE
TOP VIEW
200 ns Maximum Access Time
Military and Extended Temperature Range
Available
PLASTIC LEADED CHIP CARIER
TOP VIEW
Vee
WE
A'3
Block Diagram
A8
Ag
All
OE
A,O
Ce
V07
V0
6
VOl
VO s
V0 2
VO.
GNO
'--'"
V03
Pin Names
1/°0_7
Q Cell is a trademark of SEEQ Technology, Inc.
seeQ
~D400020/E
Technology, Incorporated
1-59
Ao'As
ADDRESSES - COLUMN
As'Au
CE
ADDRESSES - ROW
CHIP ENABLE
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00_7
DATA INPUT (WRITE)/
DATA OUTPUT (READ)
28C256
falling edge of WE or GE, whichever occurred last. Write
enable needs to be at a TTL low only for the specified
twp time. Data is latched on the rising edge of WE or OE,
whichever occurred first. An automatic erase is performed
before data is written.
The 28C256 has an internal timer which automatically
times out the write time. The on-chip timer, along with input
latches free the microprocessor for other tasks while the
part is busy writing. The 28C256's write cycle time is 10 ms
maximum. An automatic erase is performed before a
write. The DATA polling feature of the 28C256 can be
used to determine the end of a write cycle. Once the write
cycle has been completed, data can be read in a maximum
of 200 ns. Data retention is greater than 10 years.
The 28C256 can write both bytes and blocks of up to 64
bytes. The write mode is discussed below.
Write Cycle Control Pins
For system design simplification, the 28C256 is designed
such that either the OE or WE pin can be used to initiate a
write cycle. The device uses the latest high-to-Iow transition of either OE orWE signal to latch addresses and the
earliest low-to-high transition to latch the data. Address
and OE set up and hold are with respect to the later ofOE
or WE; data set up and hold is with respect to the earlier of
WE orO£.
Device Operation
Operational Modes
There are five operational modes (see Table 1) and,
except for the chip erase mode, only TTL inputs are
required. A write can be initiated under the conditions
shown. Any other conditions for OE, OE, and WE will
inhibit writing and the 110 lines will either be in a high
impedance state or have data, depending on the state of
thea forementioned three input lines.
Mode Selection
Mode
CE
OE
WE
1/0
Read
Vil
VIH
Vil
X
X
Vil
Vil
VIH
DOUT
X
X
HighZ
VIH
Vil
VIH
X
Vil
Standby
Write
Write
Inhibit
Chip Erase
To simplify the following discussion, the WE pin is used as
the write cycle control pin throughout the rest of this data
sheet. Timing diagrams of both write cycles are included
in the AC Characteristics.
(Table 1)
X
Vil
VH
Write Mode
One to 64 bytes of data can be randomly loaded into the
device. The part latches row addresses, A6-A 14, during
the first byte write. These addresses are latched on the
falling edge of the WE signal and are ignored after that until
the end of twc. This will eliminate any false write into
another page if different row addresses are applied and
the page boundary is crossed.
DIN
High ZlDouT
High ZlDouT
X
X: Any TTL level
VH: High Voltage
The column addresses, AO-A5, which are used to select
different locations of the page, are latched every time a
new write is initiated. These addresses and the OE state
(high) are latched on the falling edge of WE signal. For
proper write initiation and latching, the WE pin has to stay
low for a minimum of twp ns. Data is latched on the rising
edge of WE, allowing easy microprocessor interface.
Reads
A read is typically accomplished by presenting the addresses of the desired byte to the address inputs. Once
the address is stable, GE is brought to a TTL low in order
to enable the chip. The WE pin must be at a TTL high
during the entire read cycle. The output drivers are made
active by bringing Output Enable (OE) to a TTL low.
During read, the addresses, GE , OE, and input data
latches are transparent.
Upon a low to high WE transition, the 28C256 latches data
and starts the internal page load timer. The timer is reset
on the falling edge of the WE signal if another write is
initiated before the timer has timed out. The timer stays
reset while the WE pin is kept low. If no additional write
cycles have been initiated in (tSLC) after the last WE low to
high transition, the part terminates the page load cycle and
starts the internal write. During this time which takes a
maximum of 10 ms, the device ignores any additional write
attempts. The part can now be read to determine the end
of write cycle (DATA polling).
Writes
To write into a particular location, the address must be
valid and a TTL low applied to the Write Enable (WE) pin
of a selected (OE low) device. This combined with Output
Enable (OE) being high, initiates a write cycle. During a
byte write cycle, all inputs except data are latched on the
seeQ
MD400020lE
Technology, Incorporated
1-60
28C256
Extended Page Load
read correctly. A DATA polling read should not be done
until a minimum of tLP microseconds after the last byte is
written. Timing for a DATA polling read is the same as a
normal read once the tLP specification has been met.
In order to take advantage of the page mode's faster
average byte write time, data must be loaded at the page
load cycle time, (tsLd. Since some applications may not
be able to sustain transfers at this minimum rate, the
28C256 permits an extended page load cycle. To do this,
the write cycle must be "stretched" by maintaining WE low,
assuming a write enable-controlled cycle, and leaving all
other control inputs (CE, OE) in the proper page load cycle
state. Since the page load timer is reset on the falling edge
of WE, keeping this signal low will inhibit the page load
timer. When WE returns high, the input data is latched and
the page load cycle timer begins. In CE controlled write the
same is true, with CE holding the timerresetinsteadofWE.
Chip Erase
Certain applications may require all bytes to be erased
simultaneously. This feature, which requires high voltage,
is optional and timing specifications are available from
SEEQ.
Power Up/Down Considerations
There is internal circuitry to minimize a false write during
power up or power down. This circuitry prevents writing
under anyone of the following conditions.
DATA Polling
The 28C256 has a maximum write cycle time of 10 ms.
Typically though, a write will be completed in less than the
specified maximum cycle time. DATA polling is a method
of minimizing write times by determining the actual endpoint of a write cycle. If a read is performed to any address
while the 28C256 is still writing, the device will present
the ones-complement of the last byte written. When the
28C256 has completed its write cycle, a read from the last
address written will result in valid data. Thus, software can
simply read from the part until the last data byte written is
seeQ
~D4000201E
1. Vee is less than VWI V.
2. A high to low Write Enable (WE) transition has not
occurred when th!!.Jee supply is between VW1 V and Vee
with CE low andOE high.
Writing will also be inhibited when WE, CE, or OE are in
TTL logical states other than that specified for a byte write
in the ~ode Selection table.
Technology, Incorporated
1-61
28C256
Overshoot pulse of less than 10 ns (measured at
SO% point )applied to all inputs or outputs
with respect to ground ......................................... + 7.0 V
Absolute Maximum Stress Range"
Temperature
Storage .............................................. -6SoC to +1S0°C
Under Bias .....•..................................... -10°C to +80°C
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. Voltage applied to aI/Inputs or Outputs
with respect to ground ....................... +6.0 V to -O.S V
Undershoot pulse of less then 10 ns (measured at
SO% point) applied to all inputs or outputs
with respect to ground ...................................... -1.0 V
Recommended Operating Conditions
28C256
I Temperature Range
I Vcc Supply Voltage
(Ambient) O°C to 70°C
± 10%
5V
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
DC Characteristics
Condition
Read Operation (Over operating temperature and Vcc range, unless otherwise specified)
Limits
Symbol
Parameter
Max.
Units
Icc
Active Vcc Current
60
mA
CE = OE = V ,L ; All 110 open;
Other Inputs = Vcc Max.
Min. read or write cycle time
IS81
Standby Vee Current
(TTL Inputs)
2
mA
CE = V ,H , OE = V IL; All I/O Open;
Other Inputs - V ,L to V ,H
IS82
Standby Vec Current
(CMOS Inputs)
200
JlA
CE = Vce -0.3
Other Inputs = V ,L to V ,H
All I/O Open
Input Leakage Current
1
JlA
Y'N
Output Leakage Current
10
JlA
VOUT
I
IL
I
(2)
OL
(3)
V,L
V,H
Min.
Input Low Voltage
-0.3
0.8
V
Input High Voltage
2.0
6
V
Test Condition
VOL
Output Low Voltage
V
IOL
V OH
Output High Voltage
2.4
V
IOH
V WI (I)
Write Inhibit Voltage
3.8
V
0.45
NOTES:
1. Characterized. Not tested.
2. Inputs only. Does not include 110.
3. For 110 only.
seeQ
MD400020lE
Technology, Incorporated
1-62
= Vce Max.
= Vce Max.
= 2.1 rnA
= -400 IJA
28C256
Capacitance t1l
TA
= 25°C, f = 1 MHz
Symbol
Parameter
Max.
Conditions
C IN
Input Capacitance
6 pF
VIN = OV
C OUT
Data (1/0) Capacitance 12 pF
A.C. Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V
VI/o = OV
E.S.D. Characteristics
Symbol
VZAP
[21
Test Conditions
Parameter
Value
E.S.D. Tolerance
>2000 V. MIL-STD 883
Test Method 3015
AC Characteristics
Read Operation (Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol Parameter
28C256-200
28C256-250
28C256-300
28C256-350
Min. Max.
Min. Max.
Min. Max.
Min.
200
250
300
350
t Re
Read Cycle Time
teE
Chip Enable Access Time
tAA
Address Access Time
tOE
Output Enable Access Time
tOF
Output or Chip Enable High to
output in Hi-Z
0
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
200
200
80
60
0
0
Test
Max. Units Conditions
ns
250
300
350
ns
250
90
300
90
350
ns
90
80
ns
CE = OE =V 1L
OE = V IL
CE = OE = V IL
CE = V IL
ns
CE = V IL
ns
CE = OE = V IL
60
0
0
80
0
0
Read IDATA Polling Cycle
~----tRC-----.J~
ADDRESSES
ADDRESS AN
CE
HIGHZ
DATA---------+------------~~
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not tested.
seeQ
MD400020lE
Technology, Incorporated
1-63
28C256
AC Characteristics
Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
28C256-200
28C256-250
Min.
Min.
Max.
28C256-350
Min.
Min.
Parameter
twc
t AS
Write Cycle Time
Address Set-up Time
20
20
20
20
ns
150
150
150
150
ns
10
Max.
28C256-300
Symbol
10
Max.
10
Max.
Units
10
ms
tAH
Address Hold Time (see note 1)
tcs
Write Set-up Time
0
0
0
0
ns
tCH
Write Hold Time
0
0
0
0
ns
tcw
CE Pulse Width (note 2)
150
150
150
150
ns
tOES
OE High Set-up Time
20
20
20
20
ns
tOEH
OE High Hold Time
20
20
20
20
ns
twp
WE Pulse Width (note 2)
150
150
150
150
ns
tos
Data Set-up Time
50
50
50
50
ns
tOH
t BlC
Data Hold Time
0
0
0
0
t lP
Last Byte Loaded
to DATA Polling Output
Byte Load Timer Cycle
(Page Mode Only) (note 3)
0.2
300
600
0.2
300
600
0.2
300
0.2
600
ns
300
~s
600
~s
Write Timing
WE CONTROLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3.1a..c min. is the minimum lime before the next byte can be loaded. ~LC max. is the minimum time the byte load timer waits before initiating
internal write cycle.
seeQ
MD400020lE
Technology, Incorporated
1-64
28C256
Page Write Timing
~-----------------------PAGELOAD----------------~~~--
DATA
,,--.
HIGHZ
~
,,, ..•, .....- - - <
Ordering Information
o
PACKAGE
TYPE
P = PLASTIC DIP
D = CERAMIC DIP
N = PLASTIC LEADED
CHIP CARRIER
UX = UNENCAPSULATED DIE
seeQ
~D400020/E
Q
~
28C256 - 250
-I
T~_ _
I'
TEMPERATURE
RANGE
PART TYPE
ACCESS TIME
a = O°C to + 70°C
32K x 8 EEPROM
200 = 200 ns
250 = 250 ns
300 = 300 ns
350 = 350 ns
(COMMERCIAL)
Technology, Incorporated
1-65
1-66
seeQ
28C64A
High Speed CMOS
64K Electrically Erasable PROM
PRODUCT PREVIEW
October 1989
Features
•
Block Diagram
High Speed: 90, 120, 150 ns Access Times
•
Commercial and Military Temperature Ranges
•
CMOS Technology
•
LowPower
• 300 mW (Typical)
• Less than 1mW Standby
•
Page Write Mode: 64 Byte Page
•
Fast Write: 5 ms Byte/Page Write Time
•
Write Cycle Completion Indication
• DATA Polling of Data Bit 7
•
On Chip Timer
• Automatic Erase Before Write
•
High Endurance
• 10,000 Cycles/Byte Minimum
• 10 Year Data Retention
•
Power Up/Down Protection Circuitry
•
JEDEC Approved Byte-Wide Pinout
DUAL-IN-LiNE
TOP VIEW
Description
SEEQ's 28C64A is a high speed CMOS 5V only, 8K x 8
Electrically Erasable Programmable Read Only Memory
(EEPROM). It is manufactured using SEEQ's advanced
1.25 micron CMOS process and is available in 28 pin
Cerdip, Plastic DIP packages and 32 pad LCC, PLCC. The
28C64A is ideal for high speed applications which require
low power consumption, non-volatility and in-system reprogrammability. The endurance, the number of times
which a byte may be written, is specified at 10,000 cycles
per byte minimum.
The 90 ns, 120 ns, 150 ns access times meet the requirements of many of today's high performance microprocessors. The 28C64A has an internal timer which automatically times out the write time. The on-chip timer, along with
the input latches, frees the microprocessor for other tasks
during the write time. The 28C64A's write cycle time is 5
msec typical. An automatic erase is performed before a
write. The Data Polling feature of the 28C64A can be used
to determine the end of a write cycle. All inputs are CMOS/
TTL for both write and read modes. Data retention is
specified to be greater than 10 years.
seeQ
110 _
07
Pin Configuration
LEADLESS CHIP CARRIER
BonOMVIEW
vee
We
A12
A7
~ I~
u
>u
!i !i
<
...
<
NC
Au
A5
A9
A4
All
A3
OE
A2
A10
AI
CE
Ao
1107
1108
110 5
110 2
110
4
GND
1103
~
g
~
U
z
C
z
"
g~
Pin Names
Technology, Incorporated
1-67
Ao-A5
ADDRESSES-COLUMN
A 6 -A'2
ADDRESSES-ROW
CE
CHIP ENABLE
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00 _7
DATA INPUT (WRITE)/DATA
OUTPUT (READ)
NC
NO CONNECT
1-68
seeQ
28C256K
Timer E2
256K Electrically Erasable PROM
October 1989
Features
Description
••
SEEQ's 28C256K is a C~OS 5Vonly, 32K x 8 Electrically
Erasable Programmable Read Only ~emory (EEPRO~).
It is manufactured using SEEQ's advanced 1.25 micron
C~OS Process and is available in both a 28-pin Cerdip
package as well as a Plastic Leadless Chip Carrier (PLCC).
The 28C256K is ideal for applications that require low
power consumption, non-volatility and in-system reprogrammability. The endurance, the number of times a byte
can be written, is specified at 1,000 cycles per byte.
•
•
•
•
•
•
•
•
CMOS Technology
Low Power
• 60 mA Active
• 150 pA Standby
Page Write Mode
• 64 Byte Page
• 160 ps Average Byte Write Time
Byte Write Mode
Write Cycle Completion Indication
The 28C256K has an internal timer that automatically
times out the write time. The on-chip timer, along with input
latches, frees the microprocessor for other tasks while the
part is busy writing. The 28C256K's write cycle time is 10
• DATAPolJ/ng
On-Chip Timer
• Automatic Erase Before Write
Endurance
• 1,000 Cycles/Byte
·10 Year Data Retention
Pin Configuration
Power Up/Down Protection Circuitry
DUAL-IN-L1NE
TOP VIEW
150 ns Maximum Access Time
PLASTIC LEADED CHIP CARIER
TOP VIEW
Military and Extended Temperature Range
Available
Block Diagram
Pin Names
seeG
~D400074/A
Technology, Incorporated
1-69
Ao-As
A6- A14
ADDRESSES-COLUMN
CE
CHIP ENABLE
ADDRESSES - ROW
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00_7
DATA INPUT (WRITE)/
DATA OUTPUT (READ)
28C256K
ms maximum. An automatic erase is performed before a
write. The DATA polling feature of the 28C256K can be
used to determine the end of a write cycle. Once the write
cycle has been completed, data can be read in a maximum
of 150 ns. Data retention is greater than 10 years.
time. Data is latched on the rising edge of WE or CE
whichever occurred first. An automatic erase is performed
before data is written.
The 28C256K can write both bytes and blocks of up to 64
bytes. The write mode is discussed below.
Device Operation
Operational Modes
Write Cycle Control Pins
There are five operational modes (see Table 1) and,
except for the chip erase mode, only TTL inputs are
required. A write can be initiated under the conditions
shown. Any other conditions for CE, OE, and WE will
inhibit writing and the 110 lines will either be in a high
impedance state or have data, depending on the state of
the aforementioned three input lines.
For system design simplification, the 28C256K is designed
such that either the CE or WE pin can be used to initiate a
write cycle. The device uses the latest high-to-Iow transition of either CE orWE signal to latch addresses and the
earliest low-to-high transition to latch the data. Address
and OE set up and hold are with respect to the later ofCE
or WE; data set up and hold is with respect to the earlier of
WEorCE.
Mode Selection
(Table 1)
Mode
CE
OE
WE
1/0
Read
VIL
VIH
DOUT
X
X
High Z
Write
VIL
VIH
VIL
VIH
Write
Inhibit
X
X
V IL
VIL
VIH
Chip Erase
VIL
VH
Standby
X
X
VIL
DIN
High
High
ZlDouT
ZlDoUT
X
X: Any TTL level
VH : High Voltage
Reads
A read is typically accomplished by presenting the address
of the desired byte to the address inputs. Once the
address is stable, CE is brought to a TTL low in order to
enable the chip. The WE pin must be at a TTL high during
the entire read cycle. The output drivers are made active
by bringing Output Enable (OE) to a TTL low. During read,
the addresses, CE , OE, and input data latches are
transparent.
Writes
To write into a particular location, the address must be
valid and a TTL low applied to the Write Enable (WE) pin
of a selected (CE low) device. This combined with Output
Enable (OE) being high, initiates a write cycle. During a
byte write cycle, all inputs except data are latched on the
falling edge of WE or CE, whichever occurred last. Write
Enable needs to be at a TTL low only for the specified twp
seeQ
MD4000741A
To simplify the following discussion, the WE pin is used as
the write cycle control pin throughout the rest of this data
sheet. Timing diagrams of both write cycles are included
in the AC Characteristics.
Write Mode
One to 64 bytes of data can be randomly loaded into the
device. The part latches row addresses, A6-A 14, during
the first byte write. These addresses are latched on the
falling edge of the WE signal and are ignored after that until
the end of twe . This will eliminate any false write into
another page if different row addresses are applied and
the page boundary is crossed.
The column addresses, AO-A5, which are used to select
different locations of the page, are latched every time a
new write is initiated. These addresses and the OE state
(high) are latched on the falling edge of WE signal. For
proper write initiation and latching, the WE pin has to stay
low for a minimum of twp ns. Data is latched on the rising
edge of WE, aI/owing easy microprocessor interface.
Upon a low to high WE transition, the 28C256K latches
data and starts the internal page load timer. The timer is
reset on the falling edge of the WE signal if another write
is initiated before the timer has timed out. The timer stays
reset while the WE pin is kept low. If no additional write
cycles have been initiated in (tBLe) after the last WE low to
high transition, the part terminates the page load cycle and
starts the internal write. During this time, a maximum of 10
ms, the device ignores any additional write attempts. The
part can be read to determine the end of write cycle (DA TA
polling).
Technology, Incorporated
1-70
28C256K
Extended Page Load
is read correctly. A DATA polling read should not be done
until a minimum of tLP microseconds after the last byte is
written. Timing for a DATA polling read is the same as a
normal read once the tLP specification has been met.
In order to take advantage of the page mode's faster
average byte write time, data must be loaded at the page
load cycle time, (tsLe)' Since some applications may not
be able to sustain transfers at this minimum rate, the
28C256Kpermits an extended page load cycle. To do this,
the write cycle must be "stretched" by maintaining WE low,
assuming a write enable-controlled cycle, and leaving all
other control inputs (GE, OE) in the proper page load cycle
state. Since the page load timer is reset on the falling edge
of WE, keeping this signal low will inhibit the page load
timer. When WE returns high, the input data is latched and
the page load cycle timer begins. In GE controlled write the
same is true, with GE holding the timerreset insteadofWE.
Chip Erase
Certain applications may require all bytes to be erased
simultaneously. This feature, which requires high voltage,
is optional and timing specifications are available from
SEEQ.
Power Up/Down Considerations
There is internal circuitry to minimize a false write during
power up or power down. This circuitry prevents writing
under anyone of the following conditions.
DA TA Polling
The 28C256K has a maximum write cycle time of 10 ms.
Typically though, a write will be completed in less than the
specified maximum cycle time. DATA polling is a method
of minimizing write times by determining the actual endpoint of a write cycle. If a read is performed to any address
while the 28C256K is still writing, the device will present
the ones-complement of the last byte written. When the
28C256K has completed its write cycle, a read from the
last address written will result in valid data. Thus, software
can simply read from the part until the last data byte written
seeQ
MD4000741A
1. Vee is less than VWI V.
2. A high to low Write Enable (WE) transition has not
occurred when th-=-Yee supply is between VWI V and Vee
with GE low andOE high.
Writing will also be inhibited when WE, GE, or OE are in
TTL logical states other than that specified for a write in the
Mode Selection table.
Technology, Incorporated
1-71
28C256K
"COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Stress Range*
Temperature
Storage .............................................. -65°C to + 150°C
Under Bias ........................................... -10°C to +80°C
D.C. Voltage applied to all Inputs or Outputs
with respect to ground ..................... +6.0 V to -0.5 V
Undershoot pulseof less than 10 ns (measured at 50 %
point) applied to all Inputs or Outputs with respect to
ground ............................................................. -1.0 V
Overshoot pulse of less than 10 ns (measured at 50%
point) applied to all Inputs or Outputs with respect to
ground ............................................................. +7.0 V
Recommended Operating Conditions
28C256K
(Ambient) ODC to 70 DC
I Temperature Range
I Vee Supply Voltage
5V ± 10%
Endurance and Data Retention
Symbol
Parameter
Value
Units
K
Minimum Endurance
1,000
Cycles/Byte
TOR
Data Retention
>10
Years
Condition
MIL-STD 883 Test
Method 1033
MIL-STD 883 Test
Method 1008
DC Characteristics Read Operation (Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol
Parameter
Max.
Units
Icc
Active Vee Current
60
mA
CE = OE =VIL: All 1/0 open;
Other Inputs = Vcc Max.
Min. read or write cycle time
1SS1
Standby Vee Current
(TTL Inputs)
2
mA
CE = VIH ' OE = V IL; All 110 Open;
Other Inputs = VIL to VIH
1582
Standby Vee Current
(CMOS Inputs)
200
JlA
CE = Vee -0.3
Other Inputs = VIL to VIH
All 1/0 Open
112)
IL
I 13)
OL
V IL
V IH
VOL
V OH
VWI
(1)
Min.
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
-0.3
2.0
Output Low Voltage
1
JlA
VIN = Vee Max.
10
0.8
6
JlA
V
V
Vour = Vee Max.
0.45
101.. = 2.1 mA
Output High Voltage
2.4
V
V
Write Inhibit Voltage
3.8
V
NOTES:
1. Characterized. Not tested.
2. Inputs only. Does not include 1/0.
3. For 1/0 only.
seeQ
MD4000741A
Test Condition
Technology, Incorporated
1-72
IOH = -400 IJA
28C256K
Capacitance [1J
TA = 25°C, f = 1 MHz
Parameter
Max.
Conditions
A.C. Test Conditions
CIN
Input Capacitance
6 pF
VIN = OV
C OUT
Data (1/0) Capacitance 12 pF
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V
Symbol
V IIO = OV
E.S.D. Characteristics
Symbol
VZAP
(2)
Parameter
Value
Test Conditions
E.S.D. Tolerance
>2000 V.
MIL-STD 883
Test Method 3015
AC Characteristics
Read Operation (Over operating temperature and Vcc range, unless otherwise specified)
Limits
28C256K-150 28C256K-200 28C256K-250
Symbol
Parameter
Min.
150
Max.
Min.
Max.
200
Min.
Test
Max.
Units
t RC
Read Cycle Time
ns
CE = OE =VIL
tCE
Chip Enable Access Time
150
200
250
ns
OE = V IL
tAA
Address Access Time
150
200
250
ns
CE = OE = VIL
tOE
Output Enable Access Time
70
80
90
ns
tOF
Output or Chip Enable High to
output in Hi-Z
0
60
ns
CE = V IL
CE = V IL
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
ns
CE = OE = V IL
50
0
250
Conditions
60
0
0
0
Read IDATA Polling Cycle
\04-----ADDRESSES
tRC'-----~
ADDRESSES AN
CE
OE
DATA_---..:H.:.:.IG~H~Z--+_ _ _ _ _ _ _~
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes may affect capacitance.
2. Characterized. Not tested.
seeQ
MD4000741A
Technology, Incorporated
1-73
28C256K
AC Characteristics
Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
28C256K-150
Symbol
Parameter
twc
t AS
Write Cycle Time
tAH
Address Hold Time (see note
tcs
Write Set-up Time
tCH
Write Hold Time
tcw
CE Pulse Width (note
tOES
OE High Set-up Time
tOEH
OE High Hold Time
twp
WE Pulse Width (note
tos
Data Set-up Time
tOH
t BLC
Data Hold Time
t LP
Last Byte Loaded
to DATA Polling Output
Min.
Max.
28C256K-200
Min.
10
Address Set-up Time
2)
2)
Byte Load Timer Cycle
(Page Mode Only) (note 3)
1)
20
150
0
0
150
20
20
150
50
0
0.2
200
600
Max.
28C256K-250
Min.
10
20
150
0
0
150
20
20
150
50
0
0.2
200
20
150
0
0
150
20
20
150
50
0
0.2
600
Max.
Units
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
Il s
600
Il s
Write Timing
WE CONTROLLED WRITE CYCLE
CE
CE CONTROLLED WRITE CYCLE
WE
WE
CE
OATA
DATA
NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. ~LC min. is the minimum time before the next byte can be loaded. fat.c max. is the minimum time the byte load timer waits before initiating
internal write cycle.
seeQ
MD4000741A
Technology, Incorporated
1-74
28C256K
Page Write Timing
~-------------------------PAGELOAD------------------~~-----
CE
WE
DATA
HIGHZ
Ordering Information
D
Q
28C256K - 150
~TT
~
PACKAGE
TEMPERATURE
RANGE
PART TYPE
ACCESS TIME
P = PLASTIC DIP
D = CERAMIC DIP
N = PLASTIC LEADED
CHIP CARRIER
Q = DoC
to + 70°C
(COMMERCIAL)
32K x 8 EEPROM
150 = 150 ns
200 = 200 ns
250 = 250 ns
seeQ
MD4 000 741A
Technology, Incorporated
1-75
1-76
seeQ
36C16
36C32
High Speed CMOS Electrically Erasable PROM
October 1989
Features
Description
•
SEEQ's 36C16132 are high speed 2K x 814Kx 8 Electrically
Erasable Programmable Read Only Memories, manufactured using SEEQ's advanced 1.25 micron CMOS process.
•
•
•
•
•
•
•
•
•
•
•
•
High Speed:
• 35 ns Maximum Access Time
CMOS Technology
LowPower:
• 350mW
10 Year Data Retention
High Output Drive
• Sink 16 mA At 0.45 V
• Source 4 mA At 2.4 V
The 36C16132 are intended as bipolar PROM replacements in high speed applications. The 35 ns maximum
read access time meets the requirements of many of
today's high performance processors. The endurance,
the number of times the part can be erased/written, is
specified to be greater than 100 cycles. The 36C16132 are
built using SEEQ's proprietary oxynitride EEPROM process and its innovative Q Cell™ design.
5V :t10% Power Supply
Power UplDown Protection Circuitry
Fast Byte Write
.5mslByte
Automatic Byte Clear Before Write
JEDEC Approved PROM Pinout
Direct Replacement for Bipolar PROMs
Slim 300 mil Packaging Available
Military and Extended Temperature Range
Available.
Data retention is specified to be greater than 10 years.
Block Diagram
3J~
ROW
DECODERS
,
Pin Configuration
DUAL-IN-L1NE
TOP VIEW
3q
--
36C16/36C32
(24 pins)
19
-
...
COLUMN
DECODER
E2
MEMORY
ARRAY
COLUMN
ADDRESS
GATING
i--ERASE
CONTROL
LOOIC
r---- WAITE
r---- READ
110
BUFFERS
..0: ~
CSI
V
CS3/A11(1)
I/OO•T
CS 2
V07
Pin Names
GND
NOTES:
1. Pin 19 is Al1 on the 36C32.
2. CS3 is on the 36C16 only.
3. A4 - A 10 on 36C16.
MD4000271C
ADDRESSES - COLUMN
ADDRESSES - ROW
CS 1
CS 2
CS 3
CHIP SELECT INPUTS
1/0
o Cell is a trademark of SEEO Technology, Inc.
seeQ
AO-A3
A.-A)3J
Technology, Incorporated
1-77
DATA INPUT (WRITE)
DATA OUTPUT (READ)
36C16136C32
Device Operation
Operational Modes
MODE PIN
Read
Standby
CS1
eS2
esp'
1/0
Vil
VIH
VIH
VIH
DOUT
X
X
X
Vil
X
X
High Z
X
Vil
Vil
X
V
Write
(I)
H
DIN
X: Any TIL level
The 36C16132 are available in 24 pin Slim 300 mil
CERAMIC DIP and PLASTIC DIP. 24128 pin full featured
EEPROM versions are also available (38C16132). All
parts are available in commercial as well as military
temperature ranges.
Read
A read is started by presenting the addresses of the
desired byte to the address inputs. Once the address is
stable, the chip select inputs should be brought to the
proper levels in order to enable the outputs. (see Table
above.)
Write
To write into a particular location, addresses and data
must be valid, CS2 must be TTL low and a V pulse has
to be applied to cq for 5ms. An automatic internal byte
clear is done prior to the byte write. The byte clear feature
is transparent to the user.
/1
NOTES:
1. VH - High Voltage.
2. CS3 applies only to the 36C16. This pin becomes All in the 36C32.
seeQ
MD4000271C
Technology, Incorporated
1-78
36C16136C32
Absolute Maximum·Stress Range
Temperature
Storage ............................................. -65°C to + 150°C
Under Bias .......................................... -10°C to +80°C
AI/Inputs and Outputs
with Respect to Ground .................... -3V to +7 V D.C.
CS1 with Respect to Ground ...... -0.5 V to +14 V D.C.
"'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
36C16
36C32
I Vee Supply Voltage
I Temperature Range (Read Operation)
O°C to 70°C (Ambient)
DC Operating Characteristics
(Over operating temperature and Vee range, unless otherwise specified)
5V ± 10%
Limits
Symbol
Parameter
lee
Vee Active Current
liN
Input Leakage Current
lOUT
VIL
VIH
Output Leakage Current
VH
Input High Voltage During
Write
VOL
VOH
Output Low Voltage
Input Low Voltage
Input High Voltage
Min.
Max.
Units
80
mA
CS 2 = CS 3 =VIH ; CS1 = VIL ;
Address Inputs = 20 MHz
I/O = OmA
1
)lA
0.1 V> = VIN < = Vee Max.
VOOT = Vee Max.
10
)lA
-0.5
0.8
V
2
Vee + 1.5
13.2
V
For CS 1 Input Only
0.45
V
= 16 mA, Vee = Vee Min.
= -4 mA, Vee = Vee Min.
Vee = Vee Max,
10.8
V
Output High Voltage
2.4
V
los
[l)[2J
Output Short Circuit Current
-20
mA
V
[2J
Input Undershoot Voltage
-3
V
el
NOTES:
1. Only one pin at a time for less than one second.
2. Characterized. Not tested.
seeQ
MD4000271C
Test Condition
Technology, Incorporated
1-79
10l
IOH
VOOT = 0
VIN Undershoot Pulse Width 10 ns
36C16136C32
Capacitance [1}
A.C. Test Conditions
TA = 25°C, f = 1 MHz
Parameter
Max
Conditions
C IN
Input Capacitance
6 pF
V IN = 0 V
C OUT
Data (1/0) Capacitance 12 pF
Symbol
Output Load: 10 TTL gates and total CL
Input Rise and Fall Times: < 5 ns
Input Pulse Levels: a V to 3 V
Timing Measurement Reference Level:
Inputs 1.5 V
Outputs 1.5 V
VItO = 0 V
E.S.D. Characteristics
Symbol
V ZAP
[2)
3.0V
Parameter
Value
Test Conditions
E.S.D. Tolerance
>2000 V.
MIL-STD 883
Test Method 3015
...., '- 90%
--'.--90%
10%-.{
GND
:S5ns-
= 30 pF
\-10%
---
-4---
~:S5ns
INPUT PULSES
AC Characteristics
Read Operation (Over operating temperature and V cc Range, unless otherwise specified)
Limits
36C16-35
36C32-35
36C16-40
36C32-40
Symbol
Parameter
Min.
Read Cycle Time
35
tCE
Chip Select Access Time
25
25
30
35
tAA
Address Access Time
35
40
45
55
ns
tOF
Output Enable to Output
not being Driven
25
25
25
30
ns
Output Hold from Address
Change or Chip Select
whichever occurs first
Min.
Max.
Max.
45
40
0
Min.
36C16-55
36C32-55
t RC
tOH
Max.
36C16-45
36C32-45
0
Min.
Max.
55
0
0
Units
ns
ns
ns
Read Cycle Timing
~
ADDRESSES
~
IRC
~t
J\
ADDRESSES VALID
)~
-
)~
~I{
J
CS 2
}~
)~
~
CS 1
cS 3
f 4 - I CE- "
IIJI
\\,\
1100 . 7
VAliD OUTPUT
---
..
f4- I OF"
IOH
"'~
Ilh
NOTE 3
NOTE 3
- 4 - - lAA---"
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not tested.
3. Transition is measured at steady state level -0.5 V or steady low level +0.5 V on the output from the 1.5 V level on the input.
"---
seeQ
MD4000271C
Technology, Incorporated
1-80
36C16136C32
AC Characteristics Write Operation (All Speeds)
(Over Vcc Range, TA = 25°
± 5°C unless otherwise specified)
36C16
36C32
Symbol
Parameter
Min.
Max.
Units
twp
t AS
Write Pulse Width
5
50
ms
Address Set-up Time
0
j.ls
tAH
Address Hold Time
0.5
j.ls
tcs
CS 2 Set-up Time
0
j.ls
tCH
CS2 Hold Time
0
j.ls
tos
Data Set-up Time
0
j.ls
tOH
Data Hold Time
0
tWR
Write Recovery
j.ls
10
j.ls
Write Cycle Timing
ADDRESSES
ADDRESSES VALID
V H MIN_
6.SV_
VIH------""IfI
VIL
-----..1
~------twR----~~~
__________
tcs
"°0-7
tD~ D_MA_:~_f ~~
___
__
__
11'....
1111------------
WRITE CYCLE
NOTE:
1. CS3 is All on 36C32.
seeQ
A4D4000271C
Technology, Incorporated
1-81
__
-------I~~~
DATA OUT
READ CYCLE
36C16136C32
Ordering Information
D
D
PACKAGE
TYPE
D=SUM
CERAMIC DIP
P = SLIM
PLASTIC DIP
Q
Q
36C16 -35
36C32 -35
~~
TEMPERATURE
RANGE
PART TYPE
l
a = O°C to 70°C
36C16 - 2K x 8 EEPROM
36C32 - 4K x 8 EEPROM
35 = 35 ns
45 = 45 ns
(COMMERCIAL)
SPEED
55=55ns
The "Preliminary Data Sheet" designation on a SEEO data sheet indicates that the product is not fully characterized. The specifications
are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. SEEO Technology or an
authorized sales representative should be consulted for current information before using this product. No responsibility is assumed by
SEEQ for its use, nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. S EEO reserves
the right to make changes in specifications at any time and without notice.
seeQ
MD4000271C
Technology, Incorporated
1-82
seeQ
38C16
38C32
High Speed CMOS Electrically Erasable PROM
October 1989
Features
•
High Speed:
• 35 ns Maximum Access Time
•
•
•
Power Up/Down Protection Circuitry
DATA Polling of All Data Bits 7
JEDEC Approved Byte Wide Pinout
• 38C16: 2816A Pin Compatible
• 38C32: 28C64 Pin Compatible
Military and Extended Temperature Range
Available.
•
CMOS Technology
•
Low Power:
• 350mW
High Endurance:
• 10,000 Cycles/Byte Minimum
• 10 Year Data Retention
•
On-Chip Timer and Latches
• Automatic Byte Erase Before Write
• Fast Byte Write: 5 mS/Byte
Description
•
•
•
High Speed Address/Data Latching
•
•
50 ms Chip Erase
5V ±10% Power Supply
SEEO's 38C16/32 are high speed 2K x 8/4K x 8 Electrically
Erasable Programmable Read Only Memories
(EEPROM), manufactured using SEEO's advanced 1.25
micron CMOS process.
Pin Configuration
38C16
(24 pins)
DUAL-IN-LiNE
TOP VIEW
Pin Names
38C32
(28 pins)
Ao-Aa
A4- Al l
ADDRESSES - COLUMN
CE
CHIP ENABLE
ROW ADDRESSES
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00 . 7
DATA INPUT (WRITE)
DATA OUTPUT (READ)
Block Diagram
PLASTIC LEADED CHIP CARRIER
TOP VIEW
38C16
WE
CE
OE
NOTES:
1. A. - ~o on 38C16.
2. NC -
seeQ
MD400029/C
Technology, Incorporated
1-83
No connect.
1100-7
38C16138C32
The 38C16/32 are ideal for high speed applications which
require non-volatility and in-system reprogrammability.
The endurance, the number of times a byte may be written,
is specified at 10,000 cycles per byte minimum. The high
endurance is accomplished using SEEQ's propietary
oxyntride EEPROM process and its innovative Q CelJTM
design. System reliability in applications where writes are
frequent is increased because of the low endurancefailure rate of the Q Cell. The 35 ns maximum access time
meets the requirements of many of today's high performance processors. The 38C16/32 have an internal timer
which automatically times out the write time. The on-chip
timer, along with the input latches, frees the microprocessor for other tasks during the write time. DATA Polling can
be used to determine the end of a write cycle. All inputs are
TTL compatible for both write and read modes.
read cycle. The output drivers are made active by bringing
output enable (OE) to a TTL low. During read, the address,
CE, OE, and I/O latches are transparent.
Data retention is specified to be greater than 10 years.
The EEPROM has a specified twc write cycle time of 5ms.
The typical device has a write cycle time faster than the
twe . DATA polling is a method to indicate the completion of
a timed write cycle. During the internal write cycle, the
complement of the data bit 7 is presented at output 7 when
a read is performed. Once the write cycle is finished, the
true data is presented at the outputs. A software routine
can be used to "poll': i. e. read the outputs, for true or
complemented data bit 7. The polling cycle specifications
are the same as for a read cycle. During data polling, the
addresses are don't care.
Device Operation
Operational Modes
MODE PIN
CE
OE
WE
Read
VIL
VIH
VIL
X
VIH
X
VIL
VIL
X
VIH
X
X
VIL
VIL
VIH
X
VIL
VIH
X
VIH
VIL
VIH
V [2)
VIH
Standby
Write
Write
Inhibit
Chip Erase[l)
H
1/0
DOUT
High Z
DIN
Write
To write into a particular location, addresses must be valid
.... ,..,.1 ... TTl I_ .. ~ i,. ", __ li,.,."/ f", .,"'_ lurif_ "'_"" ..... ,,, 1I"AiE", _i __ I ....
Q"V
IV .....
"',..",.,,"';;"'" IV '''f;; .rll',,", r;;IICAu,r;; '."'-1"""' V I ' "
selected (CE low) device. This initiates a write cycle.
During a write cycle, all inputs except for data are latched
on the falling edge of WE (or CE, whichever one occurred
last). Write enable needs to be at a TTL low only for the
specified twp time. Data is latched on the rising edge of WE
(or CE, which ever one occurred first). An automatic byte
erase is performed before data is written.
Q
,
,'-
,~
DATA Polling
High ZlDoUT
HighZ
High ZlDoUT
No Operation
(HighZ)
Chip Erase
Certain applications may require all bytes to be erased
simultaneously. This feature, which requires high voltage,
is optional and timing specifications are available from
SEEQ.
High Z
X: Any TIL level
Power Up/Down Considerations
The 38C16 and 38C32 are both available in CERAMIC
DIP, PLASTIC DIP and PLCC packages 24 pin versions of
both 38C16 and 38C32 intented for bipolar PROM replacement are also available (36C16/36C32). All parts are
available in commercial as well as military temperature
ranges.
Protection against false write during Vee power up/down
is provided through on chip circuitry. Writing is prevented
under anyone of the following conditions:
1. Vee is less than VWI V.
2. A high to low Write Enable (WE) transition has not
occurred when the Vee supply is between VWI V and
Vee with CE low and OE high.
Read
Writing wi/l also be inhibited when WE, CE, or OE are in
TTL logical states other than those specified for a byte
write in the Mode Selection table.
A read is started by presenting the addresses of the
desired byte to the address inputs. Once the address is
stable, CE is brought to a TTL low in order to enable the
chip. The WE pin must be at a TTL high during the entire
NOTES:
1. Chip erase is an optional mode.
2. VH - High Voltage.
o Cell is a trademark of SEEO Technology, Inc.
seeQ
MD400029/C
Technology, Incorporated
1-84
38C16138C32
COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Range
Temperature
Storage ................................................ -6SOC to +15U'C
Under Bias ..............•.............................. -1U'C to +8U'C
All Inputs and Outputs
with Respect to Ground ...................... -3 V to +7 V D.C.
Recommended Operating Conditions
38C16
38C32
I Temperature Range (Ambient)
I Vee Supply Voltage
O°C to 70°C
5V± 10%
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
DC Characteristics
Condition
(Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol
Parameter
Icc
Vee Active Current
Min.
Stand by Vee Current
ISB
Max.
Units
Test Condition
80
mA
CE = OE =V IL ;
Address Inputs
I/O = 0 mA
= 20 MHz
40
mA
CE = VIH ;
All I/O Open;
All Other Inputs TTL don't care;
liN
Input Leakage Current
1
!lA
0.1 V~ V IN ~ Vee Max.
lOUT
Output Leakage Current
10
!lA
VOUT = Vee Max.
V 1L
Input Low Voltage
-0.5
0.8
V
V1H
Input High Voltage
2
Vee + 1.5
V
VOL
Output Low Voltage
V
IOL = 2.1 mA, Vce = Vee Min.
VOH
Output High Voltage
2.4
V
IOH = -400 !lA, Vee Min.
V WI [1}
Write Inhibit Voltage
3.8
V
V
Input Undershoot Voltage
-3
V
[1}
eL
0.45
NOTES:
1. Characterized. Not tested.
seeQ
MD4000291C
Technology, Incorporated
1-85
V IN Undershoot Pulse Width < 10 ns
38C16138C32
Capacitance [1]
A.C. Test Conditions
TA = 25°C, f = 1 MHz
Symbol
Parameter
Max
Conditions
C IN
Input Capacitance
6 pF
VIN = 0 V
COUT
Data (1/0) Capacitance 12 pF
Output Load: 1 TTL gate and total C L = 30 pF
Input Rise and Fall Times: < 5 ns
to 3 V
Input Pulse Levels:
Timing Measurement Reference Level:
Inputs 1.5 V
av
V IIO = 0 V
1"""\ •• .&_
• • .&_
04
co
VUI/.IUI::> I.v
lJ
v
E.S.D. Characteristics
3.0 V
Symbol
VZAP
12)
Parameter
Value
Test Conditions
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
={~OO%
GND
--".90%
10%
~5ns
~
-
INPUT PULSES
~
-~5ns
AC Characteristics
Read Operation (Over operating temperature and V cc Range, unless otherwise specified)
Limits
38C16-35
38C16-35
Min. Max.
Symbol Parameter
t AC
Read Cycle Time
tCE
Chip Enable Access Time
25
38C16-40
38C32-40
Min. Max.
35
40
38C16-45
38C32-45
Min. Max.
45
25
38C16-55
Test
38C32-55
Min. Max. Units Conditions
55
30
ns
35
ns
CE =OE =VIL
OE = VIL
tAA
Address Access Time
35
40
45
55
ns
CE =OE = VIL
tOE
Output Enable Access Time
20
20
25
30
ns
CE = VIL
tOF
Output or Chip Enable
to Output Float not being Driven
15
15
25
30
ns
CE = V ,L
ns
CE crOE = V IL
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
0
Read Cycle Timing
ADDRESSES
CE
0
tAC
~~
ADDRESSES VALID
I~
/~
7--
~
~r--
-
~~
1/
~[-
OE
1/
Jf-
\
~
tOE
f4- t OF.....
tOHH
tCE
1/0 0-7
0
///'1
\\\i\
r--tAA~
VALID OUTPUT
\[\\' :- NOTE 3
IllJ '- NOTE 3
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which affect capacitance.
2. Characterized. Not tested.
3. Transition is measured at steady state level-- 0.5 V or steady state low level + 5.0 V on the output from the 1.5 V level on the input.
'-------
seeQ
MD4000291C
Technology, Incorporated
1-86
38C16138C32
AC Characteristics Write Operation
(Over the operating temperature and Vcc Range, unless otherwise specified)
38C16-35
38C32-35
Symbol
Parameter
twc
Write Cycle Time
Min.
tAS
Address Set-up Time
tAH
38C16-40
38C32-40
Max.
Min.
38C16-45
38C32-45
Max.
5
Min.
38C16-55
38C32-55
Max.
5
Min.
Max.
Units
5
ms
5
0
0
0
0
ns
Address Hold Time
25
25
25
30
ns
tcs
Write Set-up Time
0
0
0
0
ns
tCH
Write Hold Time
0
0
0
0
ns
tcw
CE Pulse Width
20
20
25
30
ns
tOES
OE High Set-up Time
5
5
5
5
ns
tOEH
OE High Hold Time
0
0
0
0
ns
twp
WE Pulse Width
20
20
25
30
ns
tos
Data Set·up Time
20
20
25
30
ns
tOH
Data Hold Time
0
0
0
0
top
Time to DATA Polling
from Byte Latch
35
40
ns
45
55
ns
Write Cycle Timing
WE CONTROLLED WRITE CYCLE
CE CONTROILLED WRITE CYCLE
DATA
rr:==~B~YT~E~W~RIT~S=;:":::::::;=:::;:.~1'-POLLlNG~
~L...J
OE
ADDRESSES
ADDRESSES
t~WP lOS
DATA
HIGHZ
_ _~c;.::..._ _ _-(
DONTCARE
CE
tDH---/
DATAIN
-~
IDH-J
~I-----I;JJF----
HIGHZ
NOTES
1. Address hold time is with respect to falling edge of the control signal WE or CE.
seeQ
MD4000291C
Ir-....:...--~'--------
DATA-------{
Technology, Incorporated
1-87
DATA IN
~
38C16138C32
Ordering Information
o
o
PACKAGE
TYPE
D = CERAMIC DIP
P = PLASTIC DIP
N=PLCC
~Q
Q
38C16
38C32
- 35
-35
=2~
TEMPERATURE
RANGE
Q = O°C to 70°C
(COMMERCIAL)
PART TYPE
ACCESS TIME
38C16 2K x 8 EEPROM
38C32 4K x 8 EEPROM
35=35n5
40=40n5
45=45n5
55= 55 n5
The "Preliminary Data Sheet" designation on a SEEO data sheet indicates that the product is not fully characterized. The specifications
are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. SEEO Technology or an
authorized sales representative should be consulted for current information before using this product. No responsibility is assumed by
SEEO for its use, nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. SEEO reserves
the right to make changes in specifications at any time and without notice.
seeQ
MD4000291C
Technology, Incorporated
1-88
seeQ
MODULES Q/E28C010
Timer E2
1024K Electrically Erasable PROM
October 1989
Features
Description
•
•
•
•
•
•
•
•
•
SEEQ's MOIME28C010 is a CMOS 5Vonly, 128K x 8
Electrically Erasable Programmable Read Only Memory
(EEPROM). THe MOIME28C010 consists of 4 28C256
(32K x 8) CMOS EEPROMs and a 2 to 4 line decoder in
LCC packages, mounted on and interconnected on a
ceramic substrate. The MOIME28C010 is available in a
32 pin module package and is ideal for applications which
require low power consumption, non-volatility and insystem reprogrammability.
CMOS Technology
Military Temperature Range
Low Power Operation
• 70 mA Active Current
• 2 mA Standby Current
On-Chip Timer
• Automatic Erase Before Write
64 Byte Page Mode. . . Fast Effective
Write Time
·80 psec Average Byte Write Time
Write Cycle Completion Indication
• DATA Polling
5V:f 10% Power Supply
Pin Names
Ao-A'6
CE
ADDRESSES
CHIP ENABLE
Power Up/Power Down Protection Circuitry
OE
OUTPUT ENABLE
JEDEC Approved Byte Wide Pinout
WE
WRITE ENABLE
1/°0_7
DATA INPUT (WRITE)/DATA
OUTPUT (READ)
Block Diagram
Pin Configuration
AO-A16
ADDRESS
AO-A16
NC
A
A
WE
1S
15
A12
OE----"
CE
A15
SEL1
A16
SEL2
CE
seeQ
MD400066/A
Technology, Incorporated
1-89
NC
A14
A7
A
AS
AS
13
A5
Ag
A4
All
A3
DE
EN
DATA
11°0-7
Vcc
WE
A2
AlO
Al
CE
AO
V07
VO o
VO
VOl
V0 5
V0 2
V04
Vss
V03
s
MQ/ME28C010
The MOIME28C01 0 has an internal timer which automatically times out the write time. The on-chip timer, along with
the input latches, frees the microprocessor for other tasks
during the write time. The MOIME28C010's write cycle
time is 10 ms maximum. An automatic erase is performed
before a write. The DATA Polling feature of the MOl
1v1E28C01 0 C~r: be used to deterrnine the end of a !Alrite
cycle. Data retention is greater than 10 years.
Write enable needs to be at a TTL low only for the
specified twp time. Data is latched on the rising edge of WE
(or CE, whichever occurred first). An automatic erase is
performed before data is written.
Device Operation
For system design simplification, the MOIME28C010 is
designed such that either the CE orWE pin can be used
to initiate a write cycle. The device uses the latest high-tolow transition of either CE orWE signal to latch the data.
Address and OE set up and hold are with respect to the
later of CE or WE; data set up and hold is with respect to
the earlier of WE or CE
The MOIME28CO 10 can write both bytes and blocks of up
to 64 bytes. The write mode is discussed below.
Write Cycle Control Pins
Operational Modes
There are four operational modes (see Table 1); only TTL
inputs are required. Write can only be initiated under the
conditions shown. Any other conditions for CE, OE, and
WE will inhibit writing and the 110 lines will either be in a
high impedance state or have data, depending on the state
of the forementioned three input lines.
Mode Selection
(Table 1)
Mode
CE
OE
WE
Read
VIL
VIH
VIL
X
VIH
X
VIL
X
VIH
X
X
VIL
VIH
X
VIL
VIH
X
X
Standby
Write
Write
Inhibit
To simplify the following discussion, the WE pin is used as
the control pin throughout the rest of this document.
Timing diagrams ofboth write cycles are included in the AC
characteristics.
1/0
Write Mode
DOUT
High Z
One to 64 bytes of data can be loaded randomly into the
MQIME28C010. Address lines A 15 and A 16 must be held
valid during the entire page load cycle. The part latches
row addresses, A6-A 14 during the first byte write. These
addresses are latched on the falling edge of WE signal
(assuming WE control write cycle) and are ignored after
that until the end of the write cycle. This will eliminate any
false write into another page if different row addresses are
applied and the page boundary is crossed.
DIN
High Z or Dour
High Z
High Z or Dour
X: any CMOSnTL level
Reads
A read is typically accomplished by presenting the ad-
The column addresses, AO-A5, which are used to write into
different locations of the page, are latched every time a
new write is initiated. These addresses along with OE
state (high) are latched on the falling edge of WE signal.
For proper write initiation and latching, the WE pin has to
stay low for a minimum of twp ns. Data is latched on the
rising edge of WE, allowing easy microprocessor interface.
dresses of the desired byte to the address inputs. Once
the address is stable, CE is brought to a TTL low in order
to enable the chip. The WE pin must be at a TTL high
during the entire read cycle. The output drivers are made
active by bringing Output Enable (OE) to a TTL low. During
read, the addresses, CE , OE, and input data latches are
transparent.
Upon a low to high WE transition, the MQIME28C010
latches data and starts the internal page load timer. The
timer is reset on the falling edge of WE signal if a write is
initiated before the timer has timed out. The timer stays
reset while the WE pin is kept low. If no more write cycles
have been initiated in (tsu) after the last WE low to high
transition, the part terminates page load cycle and starts
the internal write. During this time, which takes a maxi-
Writes
To write into a particular location, addresses must be valid
and a TTL low applied to the Write Enable (WE) pin of a
selected (CE low) device. This combined with Output
Enable (OE) being high, initiates a write cycle. During a
byte write cycle, all inputs except data are latched on the
falling edge of WE (or CEo whichever one occurred last.)
seeQ
MD4000661A
Technology, Incorporated
1-90
MQ/ME28C010
end point of a write cycle. If a read is performed to any
address while the MQIME28GO 10 is still writing, the device
will present the Ones-complement of the last data byte
written. When the MOIME28GO 10 has completed its write
cycle, a read from the last address written will result in valid
data. Thus, software can simply read from the part until the
last data byte written is read correctly. A DATA polling read
should not be done until a minimum of tiP microseconds
after the last byte is written. Timing for a DATA polling read
is the same as a normal read once the tiP specifications
have been met.
mum of 10 ms, the device ignores any additional load
attempts. The part can be now read to determine the end
of write cycle (DATA Polling). A 160 JJS maximum effective
byte write time can be achieved if the page is fully utilized.
Extended Page Load
In order to take advantage of the page mode's faster
average byte write time, data must be loaded at the page
load cycle time, (tBLe ). Since some applications may not
be able to sustain transfers at this minimum rate, the MOl
ME28G010 permits an extended page load cycle. To do
this, the write cycle must be 'stretched' by maintaining WE
low, assuming a write enable controlled cycle, and leaving
all other control inputs (GE, OE) in the proper page load
cycle state. Since the page load timer is reset on the falling
edge of WE, keeping this signal low will inhibit the page
load timer. When WE returns high, the input data is latched
and the page load cycle timer begins. In GE controlled
write the same is true, with GE holding the timer reset
instead of WE.
Power Up/Down Considerations
There is internal circuitry to minimize a false write during
Vee power up or down. This circuitry prevents writing
under anyone of the following conditions:
1. Vee is less than VWI V.
2. A high to low Write Enable (WE) transition has not
occurred when the Vee supply is between VWI V and Vee
with GE low andOE high.
Data Polling
The MQIME28GO 10 has a maximum write cycle time of 10
ms. Typically though, a write will be completed in less than
the specified maximum cycle time. DATA polling is a
method of minimizing write times by determining the actual
seeQ
MD4000661A
Writing will also be inhibited when WE, GE, or OE are in
TTL logical states other than that specified for a byte write
in the Mode Selection table.
Technology, Incorporated
1-91
MQ/ME28C010
"COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Stress Range*
Temperature
Storage .............................................. -65°C to +150°C
Under Bias ......................................... -65°C to + 135°C
AI! Input ar Output Valtages
witth Respect to Vss ............................ + 6 V to - O.5V
Recommended Operating Conditions
I Temperature Range (Ambient)
ME28C010
MQ28C010
-55 DC to 85 DC
ODC to 70 DC
I Vee Power Supply
5V
± 10%
5V
± 10%
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance[4)
10,000
1,000
Cycles/Byte
MIL-STD 833 Test
Method 1033
Data Retention
>10
Years
MIL-STD 833 Test
Method 1008
K
TOR
DC Characteristics
Condition
(Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol
Parameter
Max.
Units
Icc
Active Vee Current
70
mA
CE = OE = V ,L; All 110 = 0 rna;
Addr = 5 MHz
IS81
Standby Vee Current
(TTL Inputs)
10
mA
CE = V ,H , OE = V ,L; All 1/0 = 0 rna;
IS82
Standby Vee Current
(CMOS Inputs)
2
rnA
CE = Vee -0.2;
A15, A16 = Vee -0.2
Other Inputs = V ,H
All 110=0 ma
I
[2)
IL
[3)
Min.
Input Leakage Current
Test Condition
5
J.1A
Y'N = Vee Max.
25
J.1A
VOUT = Vee Max.
-0.3
0.8
V
2.0
6
V
IOL
V ,L
Output Leakage Current
Input Low Voltage
V ,H
Input High Voltage
VOL
V OH
Output Low Voltage
V
IOL
Output High Voltage
2.4
V
IOH = -400 J,JA
VWl [1)
Write Inhibit Voltage
3.8
V
0.45
= 2.1
rnA
NOTES:
1. Characterized. Not tested.
2. Inputs only. Does not include 1/0.
3. For 1/0 only.
4. Endurance can be specified as an option to be 1000 or 10000 cyeleslbyte minimum for ME28C010 and is 1000 cycleslbyte
minimum for MQ28C010.
seeQ
MD4000661A
Technology, Incorporated
1-92
MQ/ME28C010
Capacitance [1J
TA
= 25°C, t = 1 MHz
Symbol
Parameter
Max.
Conditions
AC Test Conditions
C IN
Input Capacitance
30 pF
V IN = OV
C OUT
Data (I/O) Capacitance 40 pF
VItO = OV
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V
E.S.D. Characteristics
Symbol
VZAP
(2J
Parameter
Value
Test Conditions
E.S.D. Tolerance
>1000 V.
MIL-STD 883
Test Method 3015
AC Characteristics
Read Operation (Over operating temperature and Vcc range, unless otherwise specified)
Limits
MQ28C010-250 MQ28C010-300
ME28C010-250 ME28C010-300
Symbol
Parameter
Min.
Max.
t RC
Read Cycle Time
250
tCE
Chip Enable Access Time
250
tAA
Address Access Time
tOE
Output Enable Access Time
tOF
Output or Chip Enable High to
Output in Hi-Z
0
Units
300
350
ns
250
300
350
ns
150
150
150
ns
CE = OE = V IL
CE = V IL
80
ns
CE = V IL
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
ns
CE = OE = V IL
350
300
60
0
0
Min.
Test
Conditions
Max.
Min.
Max.
MQ28C010-350
ME28C010-35O
80
0
0
ns
CE = OE =VIL
OE = V IL
Read IDATA Polling Cycle
14-----tRC----...;
ADDRESSES
ADDRESSAN
CE
OE
HIGHZ
DATA---------r-------------<
1 4 - - - - tAA---..-j
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacttance.
2. Characterized. Not tested.
seeQ
MD4000661A
Technology, Incorporated
1-93
MQ/ME28C010
AC Characteristics
Write Operation (Over the operating temperature and Vec range, unless otherwise specified)
Limits
MQ28C010-250
ME28C010-250
MQ28C010-300
ME28C010-300
M!n,
MQ28C010-35O
ME28C010-350
M!n_
SymbQ!
Parameter
twc
t AS
Write Cycle Time
Address Set-up Time
20
20
20
ns
tAH
Address Hold Time (see note 1)
150
150
150
ns
tes
Write Set-up Time
0
0
0
ns
tCH
Write Hold Ti me
0
0
0
ns
tew
CE Pulse Width (note 2)
150
150
150
ns
tOES
OE High Set-up Time
20
20
20
ns
tOEH
OE High Hold Time
20
20
20
ns
twp
WE Pulse Width (note 2)
150
150
150
ns
tos
Data Set-up Time
50
50
50
ns
tOH
Data Hold Time
0
0
0
taLc
Byte Load Timer Cycle
(Page Mode Only) (note 3)
t LP
Last Byte Loaded
to DATA Polling
M!!"L
Ma~_
10
0.2
200
1
Ma~_
10
0.2
200
0.2
1
Ma~_
IJn!ts
10
ms
ns
200
Il s
1
ms
Write Timing
WE CONTROLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. tac min. is the minimum time before the next byte can be loaded. ~c max. is the minimum time the byte load timer waits before initiating
internal write cycle.
seeQ
MD4000661A
Technology, Incorporated
1-94
MQ/ME28C010
Page Write Timing
~-----------------------PAGELOAD----------------~~~----
WE
DATA
HIGHZ
Ordering Information
PACKAGE
TYPE
TEMPERATURE
RANGE
PART TYPE
ENDURANCE
ACCESS TIME
M= MODULE
Q = DoC to + 70°C
(COMMERCIAL)
E -55°C to 85°C
(EXTENDED)
128 Kx 8
EEPROM
K = 1000 CYCLES
N = 10000 CYCLES
250 = 250 ns
300 = 300 ns
350 = 350 ns
seeG
~D400066/A
Technology, Incorporated
1-95
1-96
FLASH
SEEa TECHNOLOGY
FLASH EEPROM ALTERNATE SOURCE DIRECTORY
Alternate
Manufacturer
INTEL
INTEL
NATIONAL
NATIONAL
Configuration
Part #
D28F512
D28F010
MC48F512
MC48F010
64KX8
128K X8
64KX8
128K X 8
Functionally
Equivalent
48F512
48F010
48F512
48F010
1024K Flash EEPROM
seeQ
Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-------1
2-1
2-2
seeQ
47F512
512K Bit Flash EPROM
October 1989
PRELIMINARY DATA SHEET
Block Diagram
Features
•
64K Byte Rash Erasable Non- Volatile Memory
•
Input Latches for Writing and Erasing
•
Low Power CMOS Process
•
Rash EPROM Cell Technology
•
Fast Byte Write: 225 ps max
•
Ideal for LOW-Cost Program Storage Applications
• In-Circuit Alterable
• 100 Program/Erase Cycles
• Minimum 10 Year Data Retention
•
Pinouts Upward Compatible Thru 2 Megabit
Densities
•
JEDEC Standard Byte Wide Pinout
• 32PlnPLCC
• 32 Pin Dip
•
Silicon Signatureqj
ARRAY
64KxS
1J00_7
Pin Names
Pin Configuration
Ao-As
A9 -A 15
COLUMN ADDRESS INPUT
CE
CHIP ENABLE
DUAL-IN-LiNE
TOP VIEW
ROW ADDRESS INPUT
OE
OUTPUT ENABLE
WE
WRITE ENABLE
TOP VIEW
PLASTIC LEADED CHIP CARRIER
NC
AI4
AI3
1/00-7
DATA INPUT (WRITE)/OUTPUT (READ)
N.C.
NO INTERNAL CONNECTION
A9
Vpp
D.U.
WRITE/ERASE INPUT VOLTAGE
OE
DON'T USE
CE
As
A11
AIO
~
1/°6
"°5
1/°4
......._ _...... 1103
Silicon Signature is a registered trademark of SEEQ Technology.
seeQ Technology,
MD400076/-
Incorporated
2-3
47F512
PRELIMINARY DATA SHEET
Description
The 47F512 is a 512K bit CMOS Flash EPROM organized
as 64K x 8 bits. The 47F512 brings together the high
density and cost effectiveness of UVEPROMs with the incircuit reprogrammability and package options of full featured EEPROMs. SEEQ's patented split gate Flash
from a 0 to a 1, the 47F512 must first be erased via chip
erase and then reprogrammed with the desired data. Any
byte write operation requires that the Vpp pin be at high
voltage (Vp ).
EPR01rf eel! dasigii ieduces both ilie Urne find (;vsi
The 47F5i 2 uses a software controlled looping algorithm
(figure 1) to perform writes and verify successful byte programming. During a byte write operation, all non /lFF'"
bytes are incrementally written using a 7511S minimum twc.
Each byte write is automatically latched and timed on-chip,
so that the microprocessor can perform other tasks once
the write cycle has been initiated. Write cycle time duration can be controlled by the microprocessor, or the onchip timer will automatically terminate twe after 150 I1s.
One write loop has been completed when all non /IFF" data
for all desired bytes have been written. After 3 programming loops, a read-verification cycle is performed. For any
bytes which do not verify, a fill-in programming loop is
performed.
re-
quired to alter code in program and data storage applications.
The 47F512's fast electrical erase and 0.2 ms/byte programming is 20 times faster than reprogramming of
UVEPROMs. Electrical erase and reprogramming make
the 47F512 ideal for applications with high density requirements, but where ultraviolet erasure is either impractical
or impossible.
On chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to perform other
tasks once write/erase cycles have been initiated. Endurance, the number of times each byte can be written and
erased, is specified at 100 cycles. Electrical erase allows
the 47F512 to be packaged in a wide range of windowless
plastic, ceramic and surface mount packages.
Chip Erase
Chip Erase will change all bits in the memory to a logical
1. The 47F512 uses a two-step, software controlled looping algorithm to perform the chip erase operation. Each
loop requires that a chip erase select be performed prior to
the start of each chip erase cycle.
Read
Reading is accomplished by presenting a valid address on
Ao - A ,s with chip enable (CE) and output enable (OE) at
V'L and write enable (WE) at VIH • The Vpp pin can be at
any TTL level or Vp during read operations. See page 5
for additional information on A.C. parameters and read
timing waveforms.
The chip erase select is activated by initiating a write cycle
with the Vpp pin at V,H or lower. During the chip erase
select, address and data lines can be at any TTL level.
Following a chip erase select, the 47F512 will start chip
erase if all data inputs are /IFF", Vpp = Vp and a write cycle
initiated. After 20 loops, a device erase verify is performed
to insure all bytes = /IFF". After erase, the Vpp pin can be
brought to any TTL level or left at high voltage.
Erase and Write
Erasing and writing of the 47F512 can only be accomplished when Vpp = Vp. Latches on address, data and control inputs permit erasing and writing using normal microprocessor bus timing. Address inputs are latched on the
falling edge of write enable or chip enable, whichever is
later. While data inputs are latched on the rising edge of
write enable or chip enable, whichever is earlier. The write
enable input is noise protected; a pulse of less than 20 ns
will not initiate a write or erase. In addition, chip enable,
output enable and write enable pins must be in the proper
state to initiate a write or erase. Timing diagrams depict
write enable controlled writes; the timing also applies to
chip enable controlled writes.
Refer to page 8 for chip erase timing diagram and figure 2
for the erase algorithm.
Power Up/Down Protection
This device contains a sense circuit which disables internal erase and write operations when Vee is below 3.5 volts.
In addition, erases and writes are prevented when any
control input (eE, OE, WE) is in the wrong state for writing
/erasing (see mode table).
High Voltage Input Protection
Byte Write
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification for the Vpp
pin which must not be exceeded, even briefly, or permanent device damage may result. To minimize switching
A byte write is used to change any 1 in a byte to a o.
Individual bytes, multiple bytes or the entire memory can
be written atone time. If a bit in a byte needs to be changed
10nly non OFF" bytes can be written.
seeQ
MD400076~
Technology, Incorporated
2-4
47F512
PRELIMINARY DATA SHEET
transients on this pin, we recommend using a minimum o. 1
pf decoupling capacitor with good high frequency response connected from Vpp to ground at each device. In
addition, sufficient bulk capacitance should be provided to
minimize Vpp voltage sag when a device goes from
standby to a write or erase cycle.
contains data which identifies SEEQ as the manufacturer
and gives the product code. This allows device programmers to match the programming specification against the
product which is to be programmed.
Silicon Signature is read by raising address Ag to 12:t 0.5
volts and bringing all other address inputs, plus chip
enable, and output enable to V,L with Vee at 5 V. The two
Silicon Signature bytes are selected by address input AD"
Silicon Signature
A row of fixed ROM is present in the 47F512 which
contains the device's Silicon Signature. Silicon Signature
Silicon Signature Bytes
Ao
V IL
V IH
SEEQ Code
Product Code 47F512
Data (Hex)
94
1A
Mode Selection Table
Mode
CE
OE
WE
Vpp
A O • 15
Read
VIL
VIL
VIH
X
Address
DOUT
Standby
VIH
VIL
VIL
VIL
X
VIH
VIH
VIH
X
VIL
VIL
VIL
Byte Write
Chip Erase Select
Chip Erase
Absolute Maximum Stress Range*
X
X
HighZ
Address
DIN
TIL
X
X
Vp
X
'FF'
E.S.D. Characteristics*
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
MD400076~
Value
Symbol
Parameter
V ZAP
E.S.D. Tolerance >2000 V
* Characterization data - not tested.
Vpp and Ag with respect to Vss .......................... 14 V
seeQ
.7
Vp
Temperature
Storage ..................................... - 65°C to + 125°C
Under Bias .................................. -10°C to +85°C
All Inputs except Vpp and
outputs with respect to Vss ........ +7 V to -0.5 V
Do
Technology, Incorporated
2-5
Test Condition
MIL-STD 883
Method 3015
47F512
PRELIMINARY DATA SHEET
Operating Conditions
47F512
5V± 10%
ODC to 70DC
25DC ± SoC
Vcc Supply Voltage
Temperature Range (Read)
Temperature Range (Write/Erase)
Capacitance *
Symbol
CIN
COUT
TA =25D C, f =1 MHz
Parameter
Input Capacitance
Output capacitance
Value
6 pF
12 pF
Test Condition
VIN =0 V
VI/O = 0 V
* This parameter is measured only for initial qualifications and
after process or design changes which may affect capacitance.
DC Operating Characteristics
Over specified Vcc and temperature range
Limits
Symbol
Parameter
Max.
Unit
Test Condition
III
ILO
Input Leakage
1
Output Leakage
10
IlA
IlA
VIN = 0.1V to Vce
VIN = 0.1 V to Vcc
Min.
Vp
Program/Erase Voltage
VpR
Ipp
Vpp Voltage During Read
12.50
13.00
V
0
Vp
V
200
200
30
60
IlA
IlA
rnA
rnA
CE =VIH ' Vpp = VpR
CE = V1L• Vpp = VpR
Vpp = Vp
Vpp = Vp
Vp Current
Standby Mode
Read Mode
Byte Write
Chip Erase
Iccl
Standby Vcc Current
400
Standby Vcc Current
5
IlA
rnA
CE
Icc2
CE
= Vcc -O.3V
= V,Hmin.
Icc3
VIL
VIH
Active Vcc Current
CE
= V1L
VOL
VOH1
Output Low Voltage
VOH2
Output Level (CMOS)
seeQ
MD400076/-
Input Low Voltage
-0.3
Input High Voltage
2.0
Output Level (TTL)
40
rnA
0.8
V
7.0
V
0.45
V
IOL = 2.1 ma
2.4
V
IOH = -400 IJA
Vcc -1.0
V
IOH = -100 IJA
Technology, Incorporated
2-6
47F512
PRELIMINARY DATA SHEET
READ
AC Characteristics
(Over specified Vee and Temperature Range)
47F512
-250
47F512
-200
Symbol
Parameter
Min.
t RC
Read Cycle Time
200
tAA
Address to Data
tCE
CE to Data
tOE
OE to Data
tOF
OE/CE to Data Float
tOH
Output Hold Time
Max.
Min.
47F512
-300
Max.
0
250
250
100
60
0
Max.
Unit
300
250
200
200
75
50
Min.
ns
300
300
150
100
ns
ns
ns
ns
0
ns
Read Timing
VOO-7
...---+---tOF-----+-I
WE
XX'IJXf
XXXXX
A. C. Test Conditions
Output Load: 1 TTL gate and C(load) = 100 pF
Input Rise and Fa/I Times: < 20 ns
Input Pulse Levels: 0.45V to 2.4 V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
seeQ
MD400076/-
Technology, Incorporated
2-7
47F512
PRELIMINARY DATA SHEET
Byte Write
AC Characteristics
(Over specified Vee and temperature range)
_._.... _.._.
I '-1···--·
~umh.nl I PSUAm~t~r
.
47F512
MIn
_... _--
I
_._----
UnIt
---_.
MAY
t vps
Vpp Setup Time
2
Ils
t VPH
VPP Hold Time
tcs
CE Setup Time
Ils
ns
tCH
CE Hold Time
tOES
OE Setup Time
tOEH
t AS
OE Hold Time
tAH
Address Hold Time
tos
Data Setup Time
tOH
Data Hold Time
twp
WE Pulse Width
twc
Write Cycle Time
150
0
0
10
10
20
100
50
0
100
75
tWR
Write Recovery Time
Address Setup Time
ns
ns
ns
ns
ns
ns
ns
ns
Ils
1.5
ms
NOTE: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the
user must provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device,
e.g. access time, erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.
Byte Write Timing
, =-jgggg
ARRAY
12Sx512xS
Pin Names
U°0-7
Silicon Signature is a registered trademarks of SEEQ Technology.
seeQ
MD4000621A
Technology, Incorporated
2-13
Ao-Ae
A9 -A15
COLUMN ADDRESS INPUT
CE
CHIP ENABLE
ROW ADDRESS INPUT
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00-7
DATA INPUT (WRITE)/OUTPUT (READ)
N.C.
NO INTERNAL CONNECTION
Vpp
D.U.
WRITE/ERASE INPUT VOLTAGE
DON'T USE
48F512
PRELIMINARY DATA SHEET
The 48F512's fast electrical erase and 0.5 mslbyte programming is 20 times faster than reprogramming of
UVEPROMs. Electrical erase and reprogramming make
the 48F512 ideal for applications with high density requirements, but where ultraviolet erasure is either impractical or
impossible.
SEEQ's FLASH memories provide users with the flexibility
to alter code in all or small sections of the memory array.
The memory array is divided into 128 sectors, with each
sector containing 512 bytes. Each sector can be individually erased, or the chip can be bulk erased before reprogramming.
On-chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to perform other
tasks once write/erase/read cycles have been initiated.
Endurance, the number of times each byte can be written,
is specified at 100 cycles with an optional screen for 1000
cycles available. Electrical write/erase capability allows
the 48F512 to accommodate a wide range of plastic,
ceramic and surface mount packages.
Read
a write of 'FF', the part will wait for time t"BORT to allow
aborting the erase by writing again. This permits recovering from an unintentional sector erase if, for example, in
loading a block of data a byte of 'FF' was written. After the
tABORT delay, the sector erase will begin. The erase is accomplished by following the erase algorithm in figure 2.
V.... can be brought to any TTL level or left at hi..qh voltage
after the erase. --
Chip Erase
Chip erase will change all bits in the memory to a logical 1.
The 48F512 uses a two-step, software controlled looping
algorithm to perform the chip erase operation. Each loop
requires that a chip erase select be performed prior to the
start of each chip erase cycle.
Byte Write
A byte write is used to change any 1 in a byte to a O.
Individual bytes, multiple bytes or the entire memory can
be written atone time. Ifa bitin a byte needs to be changed
from a 0 to a 1, the byte must first be erase via sector or chip
erase and then reprogrammed with the desired data. Any
byte write operation requires that the Vpp pin be at high
voltage (Vp)'
Reading is accomplished by presenting a valid address on
Ao - A,s with chip enable (eE) and output enable (OE) at V1L
and write enable (WE) at V1W The Vpp pin can be at any
TTL level or Vp during read operations. See page 5 for
additional information on A.C. parameters and read timing
waveforms.
Data is organized in the 48F512 in a group of bytes called
a sector. The memory array is divided into 128 sectors of
512 bytes each. Individual bytes are written as part of a
sector write operation. Sectors need not be written separately; the entire device or any combination of sectors can
be written using the write algorithm.
Erase and Write
The 48F512 uses a software controlled looping algorithm
(figure 1) to perform writes and verify successful byte programming. During a byte write operation, all non uFF'"
bytes are incrementally written using a 75 fJs minimum twe'
Each byte write is automatically latched and timed on-chip,
so that the microprocessor can perform other tasks once
the write cycle has been initiated. Write cycle time duration can be controlled by the microprocessor, or the onchip timer will automatically terminate twe after 150 IJs.
One write loop has been completed when all non uFF" data
for all desired bytes have been written. After 7 programming loops, a read-verification cycle is performed. For any
bytes which do not verify, a fill-in programming loop is
performed.
Erasing and writing of the 48F512 can only be accomplished when Vpp - Vp. Latches on address, data and
control inputs permit erasing and writing using normal
microprocessor bus timing. Address inputs are latched on
the falling edge of write enable or chip enable, whichever
is later, while data inputs are latched on the rising edge of
write enable orchip enable, whicheveris earlier. All control
pins are noise protected; a pulse of less than 20 ns will not
initiate a write or erase. In addition, chip enable, output
enable and write enable must be in the proper state to
initiate a write or erase. Timing diagrams depict write
enable controlled writes; the timing also applies to chip
enable controlled writes.
Sector Erase
Sector erase changes all bits in a sector of the array to a
logical one. It requires that the Vpppin be brought to a high
voltage and a write cycle performed. The sector to be
erased is defined by address inputs A" through A,,. The
data inputs must be all ones to begin the erase. Following
1
Because bytes can only be written as part ofa sector write,
if data is to be added to a partially written sector or one or
more bytes in a sector must be changed, the contents of
the sectors must first be read into system RAM; the bytes
can then be added to the block of data in RAM and the
sector written using the sector write algorithm.
Only non -FP bytes can be written.
seeQ
MD4000621A
Technology, Incorpof'llled
2-14
48F512
PRELIMINARY DATA SHEET
This device contains a Vee sense circuit which disables
internal erase and write operations when Vcc is below 3.5
volts. In addition, erases and writes are prevented when
any control input (CE, OE, WE) is in the wrong state for
writing or erasing (see mode table).
may result. To minimize switching transients on this pin we
recommend using a minimum 0.1 ufdecoupling capacitor
with good high frequency response connected from Vpp to
ground at each device. In addition, sufficient bulk capacitance should be provided to minimize Vpp voltage sag
when a device goes from standby to a write or erase cycle.
High Voltage Input Protection
A row of fixed ROM is present in the 48F512 which
Power Up/Down Protection
Silicon Signature
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification which must
notbe exceeded, evenbrieffy, orpermanentdevicedamage
contains the device's Silicon Signature. Silicon Signature
contains data which identifies SEEQ as the manufacturer
and gives the product code. This allows device programmers to match the programming specification against the
product which is to be programmed.
Silicon Signature Bytes
SEEQCode
Product Code 48F512
Ao
Data (Hex)
VIL
VIH
94
1A
Silicon Signature is read by raising address A9 to 12:t 0.5
V and bringing all other address inputs, plus chip enable,
and output enable to V,L with Vcc at 5 V. The two Silicon
Signature bytes are selected by address input Ao'
Mode Selection Table
Mode
Read
Standby
Byte Write
Chip Erase Select
Chip Erase
Block Erase
CE
OE
VIL
VIH
VIL
X
X
X
X
X
VIL
VIL
VIH
VIH
VIL
VIL
Vp
Address
Address
TIL
X
X
DIN
X
VIL
VIL
VIH
VIH
VIL
Vp
X
X
'FF'
VIL
Vp
Address
X
'FF'
WE
VIH
Absolute Maximum Stress Range*
Temperature
Storage ..................................... - 65°C to + 125°C
Under Bias .................................. -1 DoC to +85°C
All Inputs except Vpp and
outputs with Respect to Vss ........ +7 V to -0.5 V
Vpp
X
Symbol
V ZAP
Do .7
DOUT
High Z
Value
Parameter
Test Condition
E.S.D. Tolerance >2000 V MIL-STD 883
Method 3015
Note: Characterization data - not tested.
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
MD4000621A
Ao_s
Address
E.S.D. Charateristics/1]
Vpp pin with respect to Vss .......................... 14 V
seeQ
A~.15
Address
Technology, Incorporated
2-15
48F512
PRELIMINARY DATA SHEET
Recommended Operating Conditions
48F512
ODC to 70DC
I Temperature Range (Ambient)
I Vee Supply Voltage
Capacitance f21
Symbol
CIN
COUT
5V± 10%
TA = 25 D C, f =1 MHz
Value
6 pF
12 pF
Parameter
Input Capacitance
Output capacitance
Test Condition
VIN = 0 V
VIJO= OV
Note 2: This parameter is only sampled and not 100% tested.
DC Operating Characteristics
Over the Vee and temperature range
Limits
Symbol
Parameter
Max.
Unit
Test Condition
III
ILo
Input Leakage
1
~A
Output Leakage
10
~A
VIN = 0.1V toVee
VIN ... 0.1V toVcc
Min.
Vp
Program/Erase Voltage
VpR
Vpp Voltage During Read
Ipp
Vp Current
11.4
13
V
0
Vp
V
200
200
30
~A
mA
60
10
mA
mA
Standby Mode
Read Mode
Byte Write
Chip Erase
Sector Erase
~A
Iccl
Standby Vee Current
100
~A
Icc2
Standby Vee Current
5
mA
Icc3
VIL
VIH
Active Vee Current
Input Low Voltage
-0.3
40
0.8
mA
V
Input High Voltage
2.0
7.0
V
VOL
VOHl
Output Low Voltage
0.45
VOH2
Output Level (CMOS)
seeQ
MD4000621A
Output Level (TTL)
CE = VIH ' Vpp = VpR
CE = VIL• Vpp = VpR
Vpp = Vp
= Vp
= Vp
CE = Vee -O.3V
CE = V,Hmin.
CE = VIL
Vpp
Vpp
V
IOL = 2.1 ma
2.4
V
IOH
Vcc-1.0
V
IOH
Technology, Incorporated
2-16
= -400 IJA
= -100 IJA
48F512
PRELIMINARY DATA SHEET
READ
AC Characteristics
(Over the Vee and temperature range)
48F512
-200
Symbol
Parameter
Min.
t RC
Read Cycle Time
200
tAA
Address to Data
tCE
CE to Data
tOE
OE to Data
tOF
OE/CE to Data Float
tOH
Output Hold Ti me
48F512
-300
48F512
-250
Max.
Min.
Max.
250
0
Max.
Unit
300
ns
300
300
150
100
250
250
100
60
200
200
75
50
0
Min.
ns
ns
ns
ns
0
ns
Read Timing
AOO~S~~~:~~~~~t-AA~~~_.-,~_t_~~~~=====~~XXX~
VOO-7
t---I---tDF--~
~xxx
A. C. Test Conditions
Output Load: 1 TTL gate and C(load) = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45V to 2.4V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
seeQ
MD400062YA
Technology, Incorporated
2-17
48F512
PRELIMINARY DATA SHEET
Byte Write
AC Characteristics
(Over the Vcc and temperature range)
48F512
Symbol
Parameter
Min.
t vps
Vpp Setup Time
tv PH
Vpp Hold Time
tcs
CE Setup Time
tCH
CE Hold Time
tOES
OE Setup Time
tOEH
t AS
OE Hold Time
tAH
Address Hold Time
tos
Data Setup Time
tOH
Data Hold Time
twp
WE Pulse Width
twc
Write Cycle Time
2
150
0
0
10
10
20
100
50
0
100
75
tWR
Write Recovery Time
Address SetupTime
Max.
Unit
~s
~s
ns
ns
ns
ns
ns
ns
ns
ns
ns
~s
1.5
ms
NOTE: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the
user must provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device,
e.g. access time, erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.
Byte Write Timing
seeQ
MD4000621A
Technology, Incorporated
2-18
48F512
PRELIMINARY DATA SHEET
Figure 1
48F512 Write Algorithm
SETVpp -Vp
WAITtvps jIS
LOOP _ COUNT = 0
SET ADDRESS
1ST LOCATION
RE-WRITE
BYTE (4X)
FOR twci.lS
SET ADDRESS
RE·WRITE BYTE
FOR
twci.lS
WAIT tWRms
1ST LOCATION
WRITE BYTE
FOR twci.lS
INC. ADDRESS
INCREMENT
ADDRESS
INCREMENT
LOOP _COUNT
YES
END
NO
INCREMENT
LOOP_COUNT
WAITtwRms
LOOP_COUNT = 0
seeQ
MD4000621A
NO
YES
Technology, Incorpol'8ted
2-19
DEVICE
FAILED
48F512
PRELIMINARY DATA SHEET
Sector Erase
AC Characteristics
(Over the Vee and temperature range)
48F512
Symbol
Parameter
Min.
t vps
Vpp Setup Time
tv PH
Vpp Hold Time
tcs
CE Setup Time
tOES
t AS
tAH
OE Setup Time
tos
Data Setup Time
tOH
Data Hold Time
twp
WE Pulse Width
2
500
0
0
20
100
50
0
100
tCH
CE Hold Time
tOEH
OE Hold Time
tERASE
Sector Erase Time
tABORT
Sector Erase Delay
tER
Erase Recovery Time
Address Setup Time
Address Hold Time
Max.
Unit
J.1s
ms
ns
ns
ns
ns
ns
ns
ns
0
0
ns
500
ms
ns
250
250
J.1s
ms
Sector Erase Timing
Vpp
~~~~~~~-1~voot~~~~~~~~~==1hJO~~~~~~~~~~~~~
~R~~~~~~~~~~~~~~~~O£~~~~~~~~~~O£~~~~O£~~~~~~
NEXTLOOP
seeQ
MD4000621A
Technology, Incorporated
2-20
48F512
PRELIMINARY DATA SHEET
Figure 2
48F512 Sector Erase Algorithm
WAlTtER ms
THEN VERIFY
ALL BYTES - FF
SETVpp-Vp
WAlTtvps j.IS
WRITEFF
TO SECTOR
ADDRESS
NO
L=24
seeQ
MD4000621A
Technology, Incorporated
2-21
48F512
PRELIMINARY DATA SHEET
Chip Erase
AC Characteristics
(Over the Vcc and temperature range)
48F512
Parameter
Min.
Max.
Unit
Symbol
t vps
Vpp Setup Time
2
J,ls
tv PH
Vpp Hold Time
500
ms
tcs
CE Setup Time
0
ns
tOEs
OE Setup Time
0
ns
tos
Data Setup Time
50
ns
tOH
Data Hold Time
0
ns
twp
WE Pulse Width
100
ns
tCH
CE Hold Time
0
ns
tOEH
OE Hold Time
0
ns
tERASE
Chip Erase Time
500
ms
tER
Erase Recovery Time
250
Chip Erase Timing
VP
seeQ
MD4000621A
Technology, Incorporated
2-22
ms
48F512
PRELIMINARY DATA SHEET
Figure 3
48F512 Chip Erase Algorithm
WAITIER ms
THEN VERIFY
SET
LOOP_COUNT. 0
ALL BYTES. FF
WRITEFF
TO ANY
ADDRESS
SETVpp.Vp
WAITlVPS Jl.s
WRITEFF
TO ANY
ADDRESS
NO
L=24
seeQ
MD4000621A
Technology. Incorporated
2-23
48F512
PRELIMINARY DATA SHEET
Ordering Information
Q
0
T
T
48F512 K
~T
Package
Type
Temperature
Range
Device
D = Ceramic Dip
a = 0 to 70° C
64K x 8 FLASH
EEPROM
P = Plastic Dip
N = Plastic Leaded
Chip Carrier
seeQ
MD4000621A
Technology, Incorporated
-200
T
Endurance
BLANK = 100
K = 1000
Access
Time
200 =200 ns
250 = 250 ns
300 - 300 ns
-----------------------~
2-24
seeQ
47F010
1024K Bit Flash EPROM
October 1989
PRELIMINARY DATA SHEET
Block Diagram
Features
•
128K Byte Flash Erasable Non-Volatile Memory
•
Input Latches for Writing and Erasing
•
Low Power CMOS Process
•
Flash EPROM Cell Technology
•
Fast Byte Write: 225 lis max
•
Ideal for Low-Cost Program Storage Applications
• In-Circuit Alterable
• 100 Program/Erase Cycles
• Minimum 10 Year Data Retention
•
Pinouts Upward Compatible Thru 2 Megabit
Densities
•
JEDEC Standard Byte Wide Pinout
• 32 PinPLCC
• 32 Pin Dip
•
Silicon Signature@
ARRAY
128K x 8
1/00-7
Pin Configuration
Pin Names
Ao·Ag
A1o·A 16
COLUMN ADDRESS INPUT
CE
CHIP ENABLE
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/°0-7
DATA INPUT (WRITE)/OUTPUT (READ)
DUAL-IN-LiNE
TOP VIEW
ROW ADDRESS INPUT
N.C.
NO INTERNAL CONNECTION
Vpp
D.U.
WRITE/ERASE INPUT VOLTAGE
TOP VIEW
PLASTIC LEADED CHIP CARRIER
Vee
NC
A14
A13
As
A9
All
BE
~o
DON'T USE
CE
110]
1106
1105
1104
. ._ _ _.-110
3
19
Silicon Signature is a registered trademark of SEEQ Technology.
seeQ
A1D400077~
Technology, Incorporated
2-25
1100
47F010
PRELIMINARY DATA SHEET
Description
The 47F010 is a 1024K bit CMOS Flash EPROM organizedas 12BKxBbits. The 47F010 brings together the high
density and cost effectiveness of UVEPROMs with the incircuit reprogrammability and package options of full featured EEPROMs. SEEQ's patented split gate Flash
be written atone time. If a bit in a byte needs to be changed
from a 0 to a 1, the 47F01 0 must first be erased via chip
erase and then reprogrammed with the desired data. Any
byte write operation requires that the Vpp pin be at high
voltage (Vp).
,.",,11
n""d,.,n
hrlth
th"
tim"
("n",t..,.,,
_I=Pr:lrlAA
... _... -_
.. --_.:#
...,.""n",.""",
------ -_
......
- .....
- _!:Inn
..- --_
-_
quired to alter code in program and data storage applications.
The 47F010's fast electrical erase and 0.2 ms/byte programming is 20 times faster than reprogramming of
UVEPROMs. Electrical erase and reprogramming make
the 47F01 0 ideal for applications with high density requirements, but where ultraviolet erasure is either impractical
or impossible.
On chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to perform other
tasks once write/erase cycles have been initiated. Endurance, the number of times each byte can be written and
erased, is specified at 100 cycles. Electrical erase allows
the 47F01 0 to be packaged in a wide range of windowless
plastic, ceramic and surface mount packages.
The 47F01 0 uses a software controlled looping algorithm
(figure 1) to perform writes and verify successful byte programming. During a byte write operation, all non "FF'"
bytes are incrementally written using a 75/1s minimum twc.
Each byte write is automatically latched and timed on-chip,
so that the microprocessor can perform other tasks once
the write cycle has been initiated: Write cycle time duration can be controlled by the microprocessor, or the onchip timer will automatically terminate twc after 150 /1s.
One write loop has been completed when all non "FF" data
for all desired bytes have been written. After 3 programming loops, a read-verification cycle is performed. For any
bytes which do not verify, a fill-in programming loop is
performed.
Chip Erase
Chip Erase will change all bits in the memory to a logical
1. The 47F01 0 uses a two-step, software controlled looping algorithm to perform the chip erase operation. Each
loop requires that a chip erase select be performed prior to
the start of each chip erase cycle.
Read
Reading is accomplished by presenting a valid address on
Ao - A'6 with chip enable (CE) and output enable (OE) at
V1L and write enable (WE) at V,H. The Vpp pin can be at
any TTL level or Vp during read operations. See page 5
for additional information on A.C. parameters and read
timing waveforms.
The chip erase select is activated by initiating a write cycle
with the Vpp pin at V,H or lower. During the chip erase
select, address and data lines can be at any TTL level.
Following a chip erase select, the 47F010 will start chip
erase if all data inputs are "FF", Vpp = Vp and a write cycle
initiated. After 20 loops, a device erase verify is performed
to insure all bytes = "FF". After erase, the Vpppin can be
brought to any TTL level or left at high voltage.
Erase and Write
Erasing and writing of the 47F010 can only be accomplishedwhen Vpp= Vp. Latches on address, data and control inputs, permit erasing and writing using normal microprocessor bus timing. Address inputs are latched on the
falling edge of write enable or chip enable, whichever is
later. While data inputs are latched on the rising edge of
write enable orchip enable, whichever is earlier. The write
enable input is noise protected; a pulse of less than 20 ns
will not initiate a write or erase. In addition, chip enable,
output enable and write enable pins must be in the proper
state to initiate a write or erase. Timing diagrams depict
write enable controlled writes; the timing also applies to
chip enable controlled writes.
This device contains a sense circuit which disables internal erase and write operations when Vee is below 3.5 volts.
In addition, erases and writes are prevented when any
control input (CE, OE, WE) is in the wrong state for writing
/erasing (see mode table).
Byte Write
High Voltage Input Protection
A byte write is used to change any 1 in a byte to a
Refer to page B for chip erase timing diagram and figure 2
for the erase algorithm.
Power Up/Down Protection
o.
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification for the Vpp
Individual bytes, multiple bytes or the entire memory can
, Only non "FF" bytes can be written.
seeQ
MD400077/-
Technology, Incorporated
2-26
47F010
PRELIMINARY DATA SHEET
Silicon Signature
A row of fixed ROM is present in the 47F010 which
pin which must not be exceeded, even briefly, or permanent device damage may result. To minimize switching
transients on this pin, we recommend using a minimum O. 1
IJf decoupling capacitor with good high frequency response connected from Vpp to ground at each device. In
addition, sufficient bulk capacitance should be provided to
minimize Vpp voltage sag when a device goes from
standby to a write or erase cycle.
contains the device's Silicon Signature. Silicon Signature
contains data which identifies SEEQ as the manufacturer
and gives the product code. This allows device programmers to match the programming specification against the
product which is to be programmed.
Silicon Signature is read by raising address A9 to 12:t 0.5
volts and bringing all other address inputs, plus chip
enable, and output enable to V,L with Vee at 5 V. The two
Silicon Signature bytes are selected by address input Ao'
Silicon Signature Bytes
Data (Hex)
Ao
SEEQCode
V IL
94
Product Code 47F010
V IH
1C
Mode Selection Table
Mode
CE
Read
VIL
OE
WE
Vpp
A O• 16
VIL
VIH
X
Address
Do
.7
Standby
VIH
X
X
X
X
DOUT
HighZ
Byte Write
VIL
VIH
VIL
Vp
Address
DIN
Chip Erase Select
VIL
VIH
VIL
TTL
X
X
Chip Erase
V1L
VIH
VIL
Vp
X
'FF'
Absolute Maximum Stress Range*
Temperature
Storage ...•................................. - 65°C to + 125°C
Under Bias .................................. -10°C to +85°C
All Inputs except Vpp and
outputs with respect to Vss ........ +7 V to -0.5 V
E.S.D. Characteristics*
Symbol
Parameter
V ZAP
E.S.D. Tolerance >2000 V
* Characterization data - not tested.
Vpp and A9 with respect to Vss •......................... 14 V
"COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
seeQ
MD400077/-
Value
Technology, Incorporated
2-27
Test Condition
MIL-STD 883
Method 3015
47F010
PRELIMINARY DATA SHEET
Operating Conditions
47F010
5V ± 10%
Vcc Supply Voltage
Temperature Range (Read)
Temperature Range (Write/Erase)
Capacitance'"
Symbol
CIN
COUT
O°C to 70°C
25°C ± 5°C
TA = 25°C, f =1 MHz
Parameter
Input Capacitance
Output capacitance
Value
6 pF
12 pF
Test Condition
VIN = 0 V
VI/o = 0 V
* This parameter is measured only for initial qualifications and
after process or design changes which may affect capacitance.
DC Operating Characteristics
Over specified Vce and temperature range
Limits
Symbol
Parameter
Max.
Unit
Test Condition
III
ILO
Input Leakage
1
Output Leakage
10
IlA
IlA
VIN = 0.1V to Vcc
VIN = 0.1 V to Vce
Min.
Vp
Program/Erase Voltage
VpR
Vpp Voltage During Read
Ipp
Vp Current
12.50
13.00
V
0
Vp
V
200
200
30
60
IlA
mA
mA
Standby Mode
Read Mode
Byte Write
Chip Erase
!lA
Icc,
Standby Vcc Current
400
Icc2
Standby Vcc Current
5
IlA
mA
Icc3
Vil
Active Vcc Current
40
mA
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
7.0
V
VOL
VOH1
Output Low Voltage
0.45
VOH2
Output Level (CMOS)
seeQ
MD4 000 77/-
Output Level (TIL)
CE = VIH ' Vpp = V pR
CE = VIL' Vpp = VpR
Vpp = Vp
Vpp = Vp
= Vcc -O.3V
= VIH min.
CE = VIL
CE
CE
V
IOL = 2.1 ma
2.4
V
IOH = -400 IJA
Vcc - 1.0
V
IOH
Technology, Incorporated
2-28
= -100 IJA
47F010
PRELIMINARY DATA SHEET
READ
AC Characteristics
(Over specified Vee and Temperature Range)
47F010
-250
47F010
-200
Symbol
Parameter
Min.
t Re
Read Cycle Time
200
tAA
Address to Data
teE
CE to Data
tOE
OE to Data
tOF
OE/CE to Data Float
tOH
Output Hold Time
Max.
Min.
Max.
250
200
200
75
50
Min.
Max.
Unit
300
250
250
100
60
0
0
47F010
-300
ns
300
300
150
100
ns
ns
ns
ns
0
ns
Read Timing
ADDRESS
-tRC------.j~
~~
XXXX
1/0 0-7
I'-------~_~
14-----
IAA--~.'
14-+---tDF--~
WE
,2000 V
Technology, Incorporated
2-37
MIL-STD 883
Method 3015
48F010
PRELIMINARY DATA SHEET
Recommended Operating Conditions
48F010
O°C to 70°C
SV±10%
I Temperature Range (Ambient)
I Vcc Supply Voltage
Capacitance f2]
Symbol
CIN
COUT
TA = 2SoC, f =1 MHz
Parameter
Input Capacitance
Output Capacitance
Value
6 pF
12 pF
Test Condition
VIN = 0 V
VI/O = 0 V
Note 2: This parameter is only sampled and not 100% tested.
DC Operating Characteristics
I
I
Over the Vcc and temperature range
_... _-
I
IlmltQ
Symbol
Parameter
Max.
Unit
ILl
ILO
Input Leakage
1
~A
VIN = 0.1Vto Vcc
Output Leakage
10
~A
VIN = 0.1V to Vcc
Vp
Program/Erase Voltage
11.4
13
V
VpR
Vpp Voltage During Read
0
Vp
V
Ipp
Vp Current
Standby Mode
Read Mode
Byte Write
200
200
30
~A
~A
rnA
CE = VIH , Vpp = VpR
CE = VIL• Vpp = VpR
Vpp = Vp
Chip Erase
Sector Erase
60
10
rnA
rnA
Vpp = Vp
Vpp = Vp
Min.
Test Condition
Standby Vcc Current
100
~A
CE = Vcc -O.3V
Icc2
Standby Vcc Current
5
rnA
Icc3
VIL
Active Vcc Current
Input Low Voltage
rnA
CE = VIH min.
CE = VIL
-0.3
40
0.8
VIH
Input High Voltage
2.0
7.0
V
VOL
VOHl
Output Low Voltage
0.45
VOH2
Output Level (CMOS)
ICCl
seeQ
MD4000631A
Output Level (TTL)
V
V
IOL = 2.1 rna
2.4
V
IOH =-400 ~A
Vcc -1.0
V
IOH = -100 ~A
Technology, Incorporated
2-38
48F010
PRELIMINARY DATA SHEET
READ
AC Characteristics
(Over the V cc and temperature range)
48F010
-200
Min.
Max.
200
48F010
-250
Max.
Min.
Min.
250
300
Symbol
Parameter
t RC
Read Cycle Time
tAA
Address to Data
200
250
tCE
CE to Data
tOE
OE to Data
tOF
OE/CE to Data Float
200
75
50
250
100
60
tOH
Output Hold Time
0
0
48F010
-300
Max.
Unit
ns
300
300
150
100
ns
ns
ns
ns
0
ns
Read Timing
ADDRESS
XXXX~:I4-~=-=-~-t-AA=-~_~_.-!~_t_RC========:ixxxxxzzZ
11°0-7
t--+---tDF - - - - - - I
,«xxx
A.C. Test Conditions
Output Load: 1 TTL gate and C(load) = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45V to 2.4V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
seeQ
MD4000631A
Technology, Incorporated
2-39
48F010
PRELIMINARY DATA SHEET
Byte Write
AC Characteristics
(Over the Vcc and temperature range)
-, ... __ .
~umhnl
I .Dsaramatar
--_... _.. _-
48F010
Min
.--.---
Max
----.
Unit
1yps
Vpp Setup Time
2
fls
1yPH
VPP Hold Time
150
fls
tcs
CE Setup Time
0
ns
tCH
CE Hold Time
0
ns
tOES
OE Setup Time
10
ns
tOEH
tAS
tAH
OE Hold Time
10
ns
Address Setup Time
20
ns
Address Hold Time
100
ns
tos
Data Setup Time
50
ns
tOH
Data Hold Time
0
ns
twp
.
WE Pulse Width
100
ns
lWC
Write Cycle Time
75
Jls
tWR
Write Recovery Time
1.5
ms
NOTE: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the
user must provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device,
e.g. access time, erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.
Advance Data Sheets contain target product specifications which are subject to change upon device characterization over the full
specified temperature range. These specifications may be changed at any time, without notice.
Byte Write Timing
Vpp
ADDRESS
r----1WR----i
seeQ
MD4000631A
Technology, Incorporated
2-40
48F010
PRELIMINARY DATA SHEET
Figure 1
48F010 Write Algorithm
SET Vpp = Vp
WAlTtvpS j.LS
SET ADDRESS
LOOP _ COUNT = 0
1ST LOCATION
RE-WRITE
BYTE (4X)
FOR twcj.LS
SET ADDRESS
1ST LOCATION
RE-WRITE BYTE
FOR
twcj.LS
WAIT tWRms
WRITE BYTE
FORtWCj.LS
INC. ADDRESS
INCREMENT
ADDRESS
48F010
PRELIMINARY DATA SHEET
Sector Erase
AC Characteristics
(Over the Vcc and temperature range)
I
.:»ymboi
~
I"'arameier
Mm.
fyps
Vpp Setup Time
fyPH
VPP Hold Time
Ils
ms
tcs
CE Setup Time
2
500
0
tOES
tAS
tAH
OE Setup Time
0
ns
Address Hold Time
tos
Data Setup Time
tOH
Data Hold Time
twp
WE Pulse Width
tCH
CE Hold Time
OE Hold Time
48F010
tOEH
Address Setup Time
Max.
ns
ns
20
100
50
0
100
ns
ns
ns
ns
ns
ns
0
0
tERASE
~ector
tABORT
Sector Erase Delay
tER
Erase Recovery Time
crase lime
Unit
ms
500
250
250
Ils
ms
Sector Erase Timing
Vpp
MW~~:~+f~~~ro~~~~~~~~r------h~~~~~~crn~~~~~~
AOORESSES ..l.::.L.~' -'}--++------'.f\£~Ul.iIlf)L~~.D.L~.tiL~
'--_ _ _¥
I\EXTLoa>
1. Loa>
seeQ
MD4000631A
\L:lQcu.illD.L:.~:lQD.L~~.DL.~~D.L~
Technology, Incorporated
2-42
48F010
PRELIMINARY DATA SHEET
Figure 2
48F010 Sector Erase Algorithm
WAITt ER ms
THEN VERIFY
ALL BYTES - FF
SETVpp _ Vp
WAITtvps jLS
WRITEFF
TO SECTOR
ADDRESS
NO
L = 24
seeQ
MD4000631A
Technology. Incorporated
2-43
48F010
PRELIMINARY DATA SHEET
Chip Erase
AC Characteristics
(Over the Vcc and temperature range)
~ymuUl
r-iiiiiffic,ci
\.ps
Vpp Setup Time
\.PH
VPP Hold Time
tcs
CE Setup Time
tOES
OE Setup Time
tos
Data Setup Time
tOH
Data Hold Time
1wp
WE Pulse Width
tCH
CE Hold Time
tOEH
OE Hold Time
tEAASE
Chip Erase Time
tEA
Erase Recovery Time
•,1
,WIIII.
MD4000631A
..
• •• UAo.
'W' • • • •
II
'.
2
500
J.1s
ms
0
0
ns
50
0
100
0
ns
ns
ns
ns
ns
0
500
ns
ms
250
Chip Erase Timing
seeQ
48F010
Technology, Incorporated
2-44
ms
48F010
PRELIMINARY DATA SHEET
Figure 3
48F010 Chip Erase Algorithm
WRITEFF
TO ANY
ADDRESS
NO
seeQ
MD4000631A
Technology, Incorporated
2-45
48F010
PRELIMINARY DATA SHEET
Ordering Information
0
Q
Package
Type
Temperature
Range
Device
D =Ceramic Dip
Q =0 to 70° C
128K x 8 FLASH
EEPROM
T
P = Plastic Dip
T
N = Plastic Leaded
Chip Carrier
seeQ
MD4000631A
-200
48F010 K
~T
T
Endurance
BLANK =100
K =1000
Access
Time
200
250
300
=200 ns
=250 ns
=300 ns
Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - l
2-46
seeQ
KT48
FLASH EEPROM Programmer
May 1988
Features
Description
•
Programs SEEQ FLASH EEPROMs
•
Half-card size programmer board fits Into single
expansion slot on IBM PC/XT/A T, with cable
connector to a 40-pln ZIF DIP socket
•
User-friendly menu driven software:
Software resides on single floppy diskette
•
Csn load and save buffer:
Reads/generates binary, Intel hex or
Motorola S-record files
•
Easy buffer editor with different entry modes
Including string and hex
KT48 is a FLASH EEPROM programmer from SEEO
Technology. The complete unit consists of a half-card size
hardware board, a ribbon cable connected to a 40-pin ZIF
DIP socket and MS/DOS compatible software. The programmer card fits into a single expansion slot on an IBM
PC/XT/A T or IBM PC compatibles. The software is user
friendly and menu driven. The programmer currently
supports erasing/programming of SEEO 128K-bit and
512K-bit density FLASH EEPROMs. Software updates
will provide support for future members of SEEO's FLASH
product family.
•
Split EEPROM feature allows splitting of 16-or
32-blt files
•
Buffer allows stacking of code/data
KT48 enables an IBM PC to be turned into a local
development station for program generation and product
pro to typing. By eliminating the need for separate downloading, the KT48 reduces the time needed for protypingl
development work. The programmer erases/programs/
verifies FLASH EEPROMs with one single socket insertion! Gone is the need for a UV-light eraser and 20 long
minutes of waiting to erase a UV-EPROM. These programmer features make program development easy,
convenient and cost effective.
Programmer Features:
All programmer commands are menu driven with userselectable options. There is an online HELP system for
programmer operation.
Erase Comand: This command erases the FLASH
EEPROM and verifies erasure of the device. Errors, if any,
are reported.
Program Command: This command programs the target
device with data in the buffer memory and performs an
automatic verification of programmed data. An automatic
'blank check' is also performed on the target device before
programming. Errors, if any, are reported.
Verify Erase Command: This command is similar to a
'Blank Check'. Checks target device to see if it is erased.
Errors if any are reported.
Verify Data Command: This command compares target
device data to buffer data. Errors, if any, are reported.
"IBM, XT, AT are trademarks of International Business
Machines.
seeQ
MD400058~
Technology, Incorporated
2-47
Read Command: This command reads target device data
into the buffer. Buffer size is automatically determined by
the selection of the target device type.
Read File Command: This command reads a specified
file from a disk into the buffer. Buffer size is determined by
target device type selection. Binary, Intel HEX and Motorola S-record formats are supported. File Off-set option
allows files to be off-set into the buffer as desired by the
user.
Configure System Command: This command allows the
user to specify port address selection for the programmer
card, specify Vee voltage levels during programming!
erase and verify operations, select Vpp voltage during programming!erase and Enable or Disable 'Beeper' sound
prompts.
Save File Command: This command allows buffer data to
be saved to a disk under a specifiedfile name. Binary, Intel
HEX and Motorola S-record formats are supported. Buffer
size i.e., length of the file is determined by the device type
selected. Read and Save file commands allow 'Chip
Master' copies to be maintained.
Select Buffer Pointer Command: This command is used
to change the Buffer Pointer, normally O. Using this command the user can divide or shuffle data/code for simplified
partitioning into multiple FLASH EEPROM devices. For
example a 64K-byte large code can be split into four 16Kbyte blocks-each small enough to be accommodated on
a single 48128 device. Data can also be stacked into the
buffer. For example, two 2764's (8K-bytes each) can be
read into the buffer and re-programmed into a single
48128.
Copy Buffer Command: This command allows a userdefined block of buffer data to be copied into another block
with a specified starting address.
Print Buffer Command: This command writes buffer data
into a print file on the disk. The print file can be printed for
a hard copy using MSIDOS print command or a word
processing program.
Split Flash EEPROM Command: Using this command,
16- or 32-oit wide data can be spiit and programmed inro
standard 8-bit wide devices.
Fiii Buffer Command: This command fiiis the buffer with
user specified data. User specifies starting address and
ending address for the buffer fill command.
Display/Modify Buffer Command: This command displays buffer data. Using the buffer editor, data can be
edited. The editor supports various entry modes including
string and HEX.
Ordering Information
KT48-FLASH EEPROM Programmer
SEEO Technology reserves the right to make changes without further notice to products and their specifications herein to improve
reliability, function or design. SEEQ does not assume any liability arising out of the application or use of any product described herein;
neither does it convey any license under its patent rights nor the rights of others. The software described herein will be provided on an
'as is' basis and without warranty. SEEO accepts no liabil ity for incidental or consequential damages arising from the use of the software.
SEEO Technology distributes the product described herein for the sole purpose of facilitating programming support of SEEO products
and does not extend any warranty independent of that extended by the original equipment manufacturer.
seeQ
MD400058/-
Technology, Incorporated
2-48
EPROMs
(Erasable Programmable Read Only Memories)
SEEa TECHNOLOGY
EPROM ALTERNATE SOURCE
Alternate
Manufacturer
AMD
AMD
AMD
AMD
AMD
AMD
ATMEL
FUJITSU
FUJITSU
FUJITSU
GE/RCA
HITACHI
HITACHI
HYUNDAI
INTEL
INTEL
INTEL
INTEL
INTEL
INTEL
INTEL
INTEL
NATIONAL
NATIONAL
NEC
NEC
NEC
NEC
OKI
OKI
PANATECH
SGS
SGS
SIGNETICS
THOMPSON
TI
TI
TI
TOSHIBA
TOSHIBA
VLSI
VLSI
VLSI
WAFERSCALE
Part #
AM27128
AM27128A
AM2764
AM2764A
82005
82025
AT27C256
MBM27128
MBM2764
MBM27C256
CMD27C256
HN27128A
HN27C256
HY2764
MD27128
MD27128A
MD2764
MD2764A
MD27C256
5962-86063
82005
82025
NM27C256
5962-86063
uPD27128
uPD2764
uPD27C256
uPD27C256A
MSM27128A
MSM27C256
RD27C256
M2764A
M2764
5962-86063
TS27C256
TMS2764
TMS27C256
5962-86063
TMM27128
TMM2764
VM27C256
VM27C256A
5962-86063
WS27C256F
Configuration
Functionally
Equivalent
16KX8
16KX8
8KX8
8KX8
8KX8
16KX8
32KX8
16KX8
8KX8
32KX8
32KX8
16KX8
32KX8
8KX8
16KX8
16KX8
8KX8
8KX8
32KX8
32KX8
8KX8
16KX8
32KX8
32KX8
16KX8
8KX8
32KX8
32KX8
16KX8
32KX8
32KX8
8KX8
8KX8
32KX8
32KX8
8KX8
32KX8
32KX8
16KX8
8KX8
32KX8
32KX8
32KX8
32KX8
27128
27128
2764
2764
82005
82025
27C256
27128
2764
27C256
27C256
27128
27C256
2764
27128
27128
2764
2764
27C256
5962-86063
82005
82025
27C256
5962-86063
27128
2764
27C256
27C256
27128
27C256
27C256
2764
2764
5962-86063
27C256
2764
27C256
5962-86063
27128
2764
27C256
27C256
5962-86063
27C256
ALTERNATE SOURCE REPLACEMENTS MAY HAVE SOME FUNCTIONAL DIFFERENCES.
CONTACT THE SEEa FACTORY FOR ADDITIONAL INFORMATION.
seeQ
Technology, Incorporated
3-1
3-2
seeQ
2764
64KEPROM
27128
128KEPROM
November 1989
Features
•
•
Pin Configuration
Fast Access Times at 0° to 70°C
• 2764 - 160 ns
·27128 - 200 ns
Programmed Using Intelligent Algorithm
2764/27128
Vpp
A12
A7
A6
AS
A4
A3
A2
Al
Ao
• 21 VVpp
• 2 Minutes for 27128
• 1 Minute for 2764
•
JEDEC Approved Bytewlde Pin Configuration
• 2764 8K x 8 Organization
• 27128 16K x 8 Organization
•
Low Power Dissipation
• 100 mA Active Current
• 30 mA Standby Current
Military And Extended Temperature Range
Available
•
•
Description
~
Read
VIL
Output Disable
X
Standby
VIH
VIL
Program
Program Verify
Program Inhibit
VIL
V1H
Silicon Signature* V1l
VIL
VIH
(1)
Outputs
(28) (11-13,15-19)
vee
VIH
Vee Vee
Vee
Vee Vee
DOUT
HighZ
X
X
Vee Vee
High Z
VIH
V1L
VIL
V1H
Vpp Vee
DIN
Vpp Vee
DOUT
High Z
X
X
Vpp Vee
V1L
V1H
Vee Vee
Encoded
Data
X ean be either V1L or V1H
*For Silicon Signature: Ao is toggled, Ag = 12V, and all other
addresses are at a TTL low.
Silicon Signature is a registered trademark of
SEEa Technology, Inc.
seeQ
MD400010!A
06
Os
O2
GND
04
OJ
Block Diagram
Mode Selection
Vpp
01
NOTE 1: PIN 26 IS ANO CONNECT
ONTHE 2764.
SEEQ's 2764 and 27128 are ultraviolet light erasable
EPROMs which are organized 8K x 8 and 16K x 8
respectively. They are pin for pin compatible to JEDEC
approved 64K and 128K EPROMs in all operational!
programming modes. The devices have access times as
fast as 160 ns over the 0° to 70DC temperature and Vee
tolerance range. The access time is achieved without
CE OE PGM
(20) (22) (27)
As
A9
All
BE
A10
CE
07
00
Silicon Slgnature®
MODE
VCC
PGM
A13[1]
Technology, Incorporated
3-3
q
ROW
DECODERS
q
COLUMN
DECODER
OE ~
CE
PGM ~
----
"-
"
CONTROL
LOGIC
MEMORY
ARRAY
COLUMN
ADDRESS
GATING
110
BUFFERS
~
~
"'v7
Pin Names
Ae
ADDRESSES - COLUMN (LSB)
AR
ADDRESSES - ROW
CE
CHIP ENABLE
OE
OUTPUT ENABLE
00 - 07
OUTPUTS
PGM
PROGRAM
2764
27128
ming time is typically 5 mslbyte or 2 minutes for all 16K
bytes of the 27128. The 2764 requires only half this time,
about a minute for 8K bytes. This faster time improves
manufacturing throughput time by hours over cnventional
50 ms algorithms. Commercial programmers (e.g. Data II
0, Pro-log, Digelec, Kontron, and Stag) have implemented
this fast algorithm for SEEQ's EPROMs. If desired, both
EPROMs may be programmed using the conventional 50
ms programming specification of older generation
EPROMs.
sacrificing power since the maximum active and standby
currents are 100 mA and 30 mA respectively. The fast
access times allow higher system efficiency by eliminating
the need for wait states in today's 8 - or 16-bit microprocessors.
Initially, and after erasure, all bits are in the "1" state. Data
is programmed by applying 21 Vto Vppanda TTL "O"topin
27(program pin).
The 2764 and 27128 may be
programmed with an intelligent algorithm that is now
available on commercial programmers. The program-
Absolute Maximum Ratings
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature
Storage ........................................... - 65° C to + 150° C
Under Bias ......................................... -10°C to +80°C
All Inputs and Outputs
with Respect to Ground ....................... + 7 V to -0.6 V
Vpp During Programming
with Respect to Ground ..................... +22 V to -0.6 V
Voltage on Ag
with Respect to Ground .................. + 15.5 V to -0.6 V
Recommended Operating Conditions
2764
27128
5V±10%
Vcc Supply Voltage[2[
Temperature Range (Read Mode) (Ambient) O°C to 70°C
Vpp During Programming
21 ± 0.5 V
DC Operating Characteristics During Read or Programming
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
liN
Input Leakage Current
10
JlA
10
Ipp(1)
Output Leakage Current
10
JlA
VIN = Vce Max.
VOUT = Vee Max.
Read Mode
5
rnA
Vpp = Vee Max.
Prog. Mode
30
rnA
Vpp = 21.5 V
CE = VIH
CE =OE = VIL
Vpp Current
I [11
CCl
I [1[
eC2
VIL
Vee Standby Current
30
rnA
Vee Active Current
100
rnA
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2
V
VOL
Output Low Voltage
Vee + 1
0.45
VOH
Output High Voltage
2.4
V
10L = 2.1 rnA
V
10H = -400
NOTES:
1. Vee must be appied simultaneously or before Vpp and removed simultaneously or after Vpp'
seeQ
MD400010lA
Technology, Incorporated
3-4
JlA
2764
27128
AC Operating Characteristics During Read
Limits
2764·16
Symbol
27XX·20
27XX·25
Min. Max. Min. Max. Min.
Parameter
tAA
Address Access Time
tCE
Chip Enable to Data Valid
tOE
Output Enable to Data Valid
tOF
Output Enable to
Output Float
0
tOH
Output Hold from Chip
Enable, Addresses, or
Output Enable whichever
occurred first
0
160
160
75
60
200
200
75
60
0
0
0
0
Capacitance It]
Max.
250
250
100
60
27XX·30
27XX·45
Min.
Max.
Min.
Max.
0
300
300
120
105
0
450
450
150
130
0
0
Test
Conditions
CE=OE=VIL
OE=VIL
CE=V IL
CE=VIL
CE=OE=VIL
A.C. Test Conditions
Symbol
Parameter
C IN
Input Capacitance
4
COUT
Output Capacitance
8
Unit
Conditions
6
pF
V IN = 0 V
12
pF
VOUT = 0 V
Typ. Max.
Output Load: 1 TTL gate and CL = 100pF
Input Rise and Fall Times:!!: 20 ns
Input Pulse Levels: 0.45V to 2.4V
Timing Measurement Reference Level:
Inputs 1 V and 2V
Outputs O.BV and 2V
A.C. Waveforms
ADDRESSES
CE
ADDRESSES VALID
-----+--"""
OE
OUTPUT -----+-.....;.;~~--_+-+++_f_(
~----
tM ----II~
NOTES:
1.
2.
3.
4.
This parameter is sampled and is not 100% tested.
OE may be delayed to tAA
after the falling edge of CE without impact on tAA.
~F is specified from Of or CE. whichever occurs first.
These are equivalent test conditions and actual test conditions are dependent on the tester.
seeQ
MD400010lA
:1E
Technology, Incorporated
3-5
HIGHZ
2764
27128
Incorporated on SEEQ's EPROMs is Silicon Signature.
Silicon Signature contains encoded data which identifies
SEEQ as the EPROM manufacturer, the product's fab
location, and programming information. This data is
encoded in ROM to prevent erasure by ultraviolet light.
Silicon Signature is activated by raising address Ag to 12V
± 0.5V, bringing chip enable and output enable to a TTL
low, having Vee at 5V, and having all addresses except Ao
at a TTL low. The Silicon Signature data is then accessed
by toggling (using TTL) the column address Ao. There are
2 bytes of data available (see Table 2). The data appears
onoutDUts O. to 0._ with O_usedasanoddn$lritvhit Thi.<:
mode'is functiona/~t 25±
ambient-t~-,;,p~~;t~~~. .. "-
Erasure Characteristics
Soc
The 16K and 128K EPROMs are erased using ultraviolet
light which has a wavelength of 2537 Angstroms. The
integrated dose, i. e. intensity x exposure time, for erasure
is a minimum of 15 watt-secondlcm2 • The EPROM should
be placed within 1 inch of the lamp tube during erasure.
Table 1 shows the typical EPROM erasure time for various
light intensities.
Table 2. Silicon Signature Bytes
Table 1. Typical EPROM Erasure Time
Light Intensity
(Mlcro-Watts/cm2)
Erasure Time
(Minutes)
15,000
20
10,000
30
5,000
55
AO
Hex Data
SEEQ Code (Byte 0)
V1L
94
Product Code (Byte 1)
2764
27128
V1H
V1H
C1
40
Programming
Both EPROMs may be programmed using an intelligent
algorithm or with a conventional 50 msec programming
pulse.
The intelligent algorithm improves the total
programming time by approximately 10 times over the
conventional 50 msec algorithm. It typically requires only
1 and 2 minute programming time for all64K and 128K bits
respectively.
---
Silicon Signature
The intelligent algorithm requires Vee - 6V and Vpp =21 V
during byte programming. The initial program pulse width
is one millisecond, followed by a sequence of one millisecond pulses. A byte is verified after each pulse. A single
program pulse, with a time duration equal to 4 times the
number of one millisecond pulses applied, is additionally
given to the address after it is verified as being correctly
programmed. A maximum of 15 one millisecond pulses
per byte should be applied to each address. When the
intelligent algorithm cycle has been completed, all bytes
must be read at Vee = Vpp = 5V.
Incorporated in SEEQ's EPROMs is a row of mask
programmed read only memory (ROM) cells which is
outside of the normal memory cell array. The ROM
contains the EPROM's Silicon Signature.
Silicon
Signature contains data which identifies SEEQ as the
manufacturer and gives the product code.
This data
allows programmers to match the programming
specification against the product which is to be
programmed. If there is verification, then the programmer
can proceed programming.
seeQ
MD4000 1OIA
Technology, Incorporated
3-6
2764
27128
Intelligent Algorithm Flowchart
seeQ
A1D4000101A
Technology, Incorporated
3-7
2764
27128
Intelligent Algorithm
1 ' 4 - - - - - - PROGRAM------....·'""II------VERIFY----II~
V 1H
ADDRESSES
V IL
V 1H
DATA
V 1L
Vpp
Vpp
Vee
Vee
Vee
V 1H
eE
V 1L
V 1H
PGM
V 1L
tOE
(0.15)
MAX.
V 1H
OE
V 1L
NOTES:
1. All times shown in ( ) are minimum and in J.lSec unless otherwise specified.
2. The input timing reference level is .BV for a V1l and 2V for a V1H•
3. tOE and \'FP are characteristics of the device but must be accommodated by the programmer.
seeQ
MD400010lA
Technology, Incorporated
3-8
2764
27128
Intelligent Algorithm
AC Programming Characteristicsl4} TA =25° ± 5°C, Vee [1] = 6.0 V ± 0.25 V, Vpp = v ± 0.5 v
Limits
Typ.
Symbol
Parameter
tAS
Address Setup Time
2
~s
tOES
OE Setup Time
2
~s
tos
Data Setup Time
2
~s
tAH
Address Hold Time
0
~s
tOH
t OFP
Data Hold Time
2
~s
Output Enable to Output Float Delay
0
1vps
VPP Setup Time
2
1ves
t [2]
PW
[3]
t
OPW
Vee Setup Time
teEs
CE Setup Time
tOE
Data Valid from OE
Min.
Max.
130
0.95
PGM Overprogram Pulse Width
3.8
~s
1.0
1.05
ms
63
ms
2
~s
150
NOTES:
1. Vee must be applied simultaneously or before Vpp and
removed simultaneousy or after Vpp'
2. Initial Program Pulse width tolerance is 1 msec ± 5 %.
3. The length of the overprogram pulse will vary from 3.8 msec
to 63 msec as a function of the iteration counter value X.
4. For 50 rns programming, Vee" 5V± 5%, Tpw = 50 ms ± 10 %,
and T OPW is not applicable.
PACKAGE
TYPE
D=CERD[P
AC Test Conditions
Q 27128
Q 2764
- XX
- XX
=2~
TEMPERATURE
RANGE
PART TYPE
a =O°C to + 70°C
2764 - 8K x 8 EPROM
27128 - 16K x 8 EPROM
(COMMERCIAL)
ACCESS TIME
16 ·160 ns
20 -200 ns
25 -250ns
30 -300 ns
45 -450 ns
seeQ
AfD400010lA
ns
Input Rise and Fall Times (10% to 90%) ............... 20 ns
Input Pulse Levels .................................. 0.45 V to 2.4 V
Input Timing Reference Level ................ O.B V and 2.0 V
Output Timing Reference Level ............. O.B V and 2.0 V
Ordering Information
o
o
ns
~s
2
PGM Initial Program Pulse Width
Unit
Technology, Incorporated
3·9
3-10
seeQ
27C256
256K CMOS EPROM
November 1989
Pin Configuration
Features
•
256K (32K x 8) CMOS EPROM
•
Ultra Low Power
• 100 IlA Max. Vee Standby Current
• 40 mA Max. Active Current
27C256
•
Programmed Using Intelligent Algorithm
• 12.5 V Vpp
•
200 ns Access Times
• 5V± 10% Vee
• 0° to 70° C Temperature Range
•
Minimum 10 Year Data Retention
•
JEDEC Approved Bytewide Pin Configuration
•
Silicon Signature®
•
Military and Extended Temperature Range
Available.
Description
SEEQ's 27C256 is the industry's first 256K CMOS
EPROM. It has a 32K x 8 organization and has very low
power dissipation. Its 40 mA active current is less than one
half the active power of n-channel EPROMs. In addition
the 100 IlA Vee standby current is orders of magnitude
lower than those same EPROMs. Consequently, system
memory sizes can be substantially increased at a very
small increase in power. Low active and standby power is
~
Read
Output Disable
Standby
Program
Program Verify
Program Inhibit
Ao-A
Outputs
CE
OE
Vpp
vee
(22)
(1)
(28)
(11-13,15-19)
VIL
X
VIL
VIH
Vee
Vee
Vee
Vee
DOUT
High Z
VIH
VIL
X
Vee
Vee
High Z
VIH
V1L
Vpp
Vee
DIN
Vpp
Vee
VIH
VIL
Vpp
Vee
Dour
High Z
Silicon Signature* VIL
X ean be either V1l or V1H
·For Silicon Signature: Ao is toggled,
addresses are at a TTL low.
Vee
Ag
Vee
MD4000121A
07
AS
05
04
GND
03
4q
ROW
DECODERS
MEMORY
ARRAY
sq
COLUMN
DECODER
COLUMN
ADDRESS
GATING
OE
CE
CONTROL
LOGIC
BUFFERS
--
1/0
,I.
;.
"v
Pin Names
Encoded
Data
= 12V, and all other
Silicon Signature is a registered trademark of
SEEO Technology_
seeQ
A14
A13
AS
Ag
A11
DE
A10
CE
AS .A1
(20)
V1H
VIH
Vcc
A12
A7
AS
A5
A4
A3
A2
Al
AO
00
01
O2
Block Diagram
Mode Selection
MODE
Vpp
Technology, Incorporated
3-11
Ao -As
ADDRESSES - COLUMN (LSB)
A6 - A14
ADDRESSES - ROW
CE
CHIP ENABLE
OE
OUTPUT ENABLE
00- 07
OUTPUTS
27C256
important in applications which require portability, low
cooling cost, high memory bit density, and long term
reliability.
at 200 ns, making the 27C256 compatible with most of
today's microprocessors. Its inputs and outputs are
completely TTL compatible.
The 27C256 is specified over the 00 to 70° C temperature
rangeandat5 V± 10% Vee- Theaccesstimeisspecified
Initially, and after erasure, all bits are in the"1" state. An
intelligent algorithm is used to program the 27C256 typi-
Absolute Maximum Ratings
"COMMENT: Stresses above those listed under uAbsolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature
Storage ........................................... -65°C to +150°C
Under Bias ........................................ -10°C to +80°C
All Inputs and Outputs
with Respect to Ground ....................... + 7 V to -0.6 V
Vpp with Respect to Ground ............... + 14. 0 V to -0.6 V
Voltage on Ag
with Respect to Ground .................. + 14.0 V to -0.6 V
Recommended Operating Conditions
27C256-20, 27C256-25
27C256-30, 27C256-45
vee Supply Voltage(1)
Temperature Range (Read Mode)
Vpp During Read(2)
5V± 10%
(Ambient) OuC to 70"C
Vpp During Programming(3)
Vee
12.5 ± 0.3V
DC Operating Characteristics During Read or Programming
Limits
Symbol
(4)
liN
I (5)
0
Ipp
lec1
Parameter
Max.
Min.
Units
Test Condition
Input Leakage
1
J.lA
VIN = Vee Max.
Output Leakage
10
J.lA
VOUT = Vee Max.
Vpp Current:
Standby Mode
Read Mode
Programming Mode
150
1
30
J.lA
rnA
rnA
CE = Vee -1 v. min.
F = 5 MHz, CE = Vil
Vpp = 12.5 v.
Vee Standby Current
100
J.lA
CE~Vee-1v.
CE = VIH
CE = OE =Vll' 0 0 _ 7 = 0,
F = 5 MHz.
lec2
Vee Standby Current
1.5
rnA
lec3
Vee Active Current
40
rnA
VIL
VIH
Input Low Voltage
-0.1
0.8
V
Input High Voltage
2.0
VOL
VOH
Output Low Voltage
Vee + 1
0.45
V
IOl = 2.1 rna
V
IOH = -400 J.lA.
Output High Voltage
2.4
V
NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp'
2. Vpp cannot be left floating and should be connected to Vee during read.
3.0.1 J1.F ceramic capacitor on Vpp is required during programming only, to suppress voltage transients.
4. Inputs only. Does not include 110.
5. For 110 only.
seeQ
MD4000121A
Technology, Incorporated
3-12
27C256
AC Characteristics Read Operation (Over operating temperature and Vcc range,
unless otherwise specified)
Limits
27C256-20
Symbol
t""
tCE
Parameter
Min.
Chip Enable Access Time
Output Enable Access Time
tOF
Output or Chip Enable off
to Output Float!3)
tOH
Output Hold from Address
Change, Chip Enable, or
Output Enable, whichever
occurs first
27C256-30
27C256-45
Min.
Min.
Min.
200
200
75
60
Address Access Time
tOE
27C256-25
Max.
Max.
300
300
120
105
250
250
100
60
0
0
Max.
0
0
Capacitance [1/
Max.
Units
450
450
150
130
ns
Test
Conditions
CE=OE=V1l
ns
OE=V1L
ns
CE=V1L
ns
CE=V1L
ns
CE=OE=V1L
A.C. Test Conditions
Symbol
Parameter
Typ.
Max
Unit
Conditions
C1N
Input Capacitance
4
6
pF
V1N = 0 V
COUT
Output Capacitance
8
12
pF
V OUT = 0 V
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ~ 20 ns
Input Pulse Levels: 0.45V to 2.4 V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
A.C. Waveforms
ADDRESSES
ADDRESSES VALID
CE----------~--~
OE
110 0.7
----------+-------------4I-f-+-t-o+-o(
VALID OUTPUT
1 - 4 - - - - tAA - - - - . - . . t
NOTES:
1. This parameter is sampled and is not 100% tested.
2. OE may be delayed to tAA ~E after the falling edge of CE without impact on tAA .
3.
foF is specified from OE or CE, whichever occurs first.
seeQ
MD4000121A
Technology, Incorporated
3-13
HIGHZ
27C256
cally in four minutes. Data is programmed using a 12.5V
Vpp and an initial chip enable pulse of 1.0 ms.
the programming specification against the product which
is to be programmed. If there is verification, then the
programmer proceeds to program.
Incorporated on the 27C256 is Silicon Signature. Silicon
Signature contains encoded data which identifies SEEQ
as the EPROM manufacturer and gives the product code.
This data is encoded in ROM to prevent erasure by
uitravioiet iighr.
Silicon Signature is activated by raising address Ag to 12V
± 0.5V, bringing chip enable and output enable to a TTL
low, having Veeat 5V, and having all addresses except A.,
at a TTL low. The Silicon Signature data is then accessed
by toggling Ao. The data appears on outputs 0 0 to 0 6 , with
0 7 used as an odd parity bit (see Table 2).
Erasure Characteristics
The 27C256 is erased using ultraviolet light which has a
wavelength of 2537 Angstroms. The integrated dose, i.e.
intensity x exposure time, for erasure is a minimum of 15
watt-secondslcrrl. The EPROM should be placed within
one inch of the lamp tube during erasure. Table 1 shows
the typical EPROM erasure time for various light intensities.
Table 2. Silicon Signature Bytes
SEEQ Code (Byte 0)
Product Code (Byte 1)
AO
Hex Data
V1L
V1H
C2
94
Table 1. Typical EPROM Erasure Time
Light Intensity
(Micro-Watts/cm2)
Erasure Time
(Minutes)
15,000
20
10,000
30
5,000
55
Programming
The 27C256 is programmed using the industry standard
intelligent algorithm.
The intelligent algorithm requires Vee =6 Vand Vpp = 12.5
V during byte programming. The initial program pulse
width is 1.0 millisecond, followed by a sequence of 1.0
millisecond pulses. A byte is verified after each pulse. A
single program pulse, with a time duration equal to 3 times
the number of 1.0 millisecond pulses applied, is additionally given to the address after it is verified as being
correctly programmed. A minimum of one to a maximum
of 25 1-ms pulses, plus one 3X overpulse, may be applied
to each byte. When the intelligent algorithm cycle has
been completed, all bytes must be read at Vee= Vpp= 5 V.
Silicon Signature
Incorporated in SEEQ's EPROMs is a row of mask pro·
grammed read only memory (ROM) cells which is outside
of the normal memory cell array. The ROM contains the
EPROM's Silicon Signature. Silicon Signature contains
data which identifies SEEQ as the manufacturer and gives
the product code. This data allows programmers to match
seeG
MD4000121A
Technology, Incorporated
3-14
27C256
Intelligent Algorithm Flowchart
seeQ
A4D4000121A
Technology, Incorporated
3-15
27C256
Intelligent Algorithm
V IH
ADDRESSES
\I
• IL
PROGRAM--------1·~I""~-----VERIFY'-JJ--------·--IUr---
---i
ADDRESS STABLE
ii
..,
-'It-
DATllN STABLE
DATA
-'
V IL
(4)
vee
eE
V IL
t
OE
V IL
ii
...
Jf~tv~f-'-
,
tpw
~
~
topw ~
(3ms)
,
-,
MD4000121A
..
~'o"-1 ~-'~-I
(2)
(0.15)
~
MAX.
1L
NOTES:
1. All times shown in ( ) are minimum and in fLSec unless otherwise specified.
2. The input timing reference level is O.8V for a V 1L and 2V for a V1H•
3. tOE and foFP are characteristics of the device but must be accommodated by the programmer.
4. 0.1 ~F ceramic capacitor on Vpp is required during programming only. to suppress voltage transients.
seeQ
Technology, Incorporated
3-16
..,
~
1';
-'
~AH
(0)-1
~T VALID
"
(1.0ms)
V IH
DATA
~ tV~f---
vee +
V IH
l\\\\\~1t-
Jf-
Vpp
vee
'11111h
f4t~. .
(2)
Vpp
HIGHZ
... f-
~tDS~
vee
-
---Ft~~1
V IH
~
,.,.
tDFP
(0.13)
Max.
27C256
Intelligent Algorithm
AC Programming Characteristics
TA =25° ±5°C, VCC [l]= 6.0 V± 0.25 V, Vpp = 12.5 V
Limits
Min.
Max.
Typ.
Unit
Symbol
Parameter
t AS
Address Setup Time
2
tOES
OE Setup Time
2
~s
tos
Data Setup Time
2
~s
tAH
Address Hold Time
0
~s
tOH
Data Hold Time
2
t OFP
Output Enable to Output Float Delay
0
typs
V PP Setup Time
2
tvcs
Vee Setup Time
2
tpw
t
[2]
opw
CE Initial Program Pulse Width
0.95
CE Overprogram Pulse Width
2.85
tOE
Data Valid from OE
~s
~s
130
~s
~s
1.0
1.05
ms
78.75
ms
150
ns
AC Test Conditions
NOTES:
1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp'
2. The length of the overprogram pulse will vary from 2.85 msec
to 78.75 msec as a function of the iteration counter value x.
Input Rise and Fall Times (10% to 90%) ............... 20 ns
Input Pulse Levels .................................. 0.45 V to 2.4 V
Input Timing Reference Level ................ 0.8 V and 2.0 V
Output Timing Reference Level ............. 0.8 V and 2.0 V
Ordering Information
D
PACKAGE
TYPE
D-CERDIP
UX - UNENCAPSULATED DIE
Q
27C256 - 25
2~
TEMPERATURE
RANGE
PART TYPE
a - O"C to + 7O"C
32Kx 8 EPROM
COMMERCIAL
ACCESS TIME
20· 200 ns
25-250 ns
30 - 300 ns
45 -450 ns
seeQ
MD4000121A
ns
Technology, Incorporated
3-17
3-18
DATACOM
(Data Communications)
seeQ
8003
EDLC@ Ethernet
Data Link Controller
November 1989
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Description
Optimized for Burst Mode DMA Applications
The SEEQ Ethernet Data Unk Controller (EDLC) is designed to support Data Unk Layer (layer 2) of the Ethernet
specification for Local Area Networks (LAN). The system
interface is optimized for ease of connection to commonly
available DMA Controllers and specifically for BURST
MODE OPERA TION. The 8003 interfaces directly to the
8023A and 8020 Manchester Code Converters to complete the station resident Ethernet functions. The protocol
used is Carrier Sense, Multiple Access with Collision
Detection (CSMAlCD). The 8003 EDLC chip is a single 40
pin VLSI device which replaces approximately 60 MSI and
S51 devices. It is designed to greatly simplify the development of Ethernet communication in computer based systems. The 8003 provides an economic solution for the construction of an Ethernet node, providing high speed data
communication at 10 Megabits/second and sees applications in terminals, workstations, personal computers,
small business systems, and large computer systems, in
both the office and industrial environment. The 8003
EDLC chip has a universal system interface compatible
with almost any microprocessor, microcomputer, or system bus, allowing the system designer to make the price!
performance tradeoffs for each application. The transmit
and receive sections of the EDLC chip are independent
100% EthernetllEEE 802.3 (10BASE5) and
IEEE 802.31CHEAPERNET (10BASE2)
10 MHz Serial/Parallel Conversion
Preamble Generation and Removal
Automatic 32-Blt FCS (CRC) Generation and
Checking
Collision Handling, Transmission Deferral and
Retransmission with Automatic Jam and
Backoff Functions
Error Interrupt and Status Generation
40 Pin Package
Single 5 V.:t 10% Power Supply
Standard CPU and Peripheral Interface
Control Signals
Loopback Capability for Diagnostics
Single Phase Clock
Inputs and Outputs TTL Compatible
Functional Block Diagram
TID
ENCODER
INTERFACE
COMMANDI
STATUS
INTERFACE
DATA
INTERFACE
CSN ) - DECODER
INTERFACE
r-_______.....:..:..Rx::..;:D
EDLC is a registered trademark of SEEQ Technology Inc.
SeeQ
MD400024!B
Technology, Incorporated
4-1
8003
Data Field: The Data Field consists of 46 to 1500 bytes of
information which are fully transparent in the sense that
any arbitrary sequence of bytes may occur.
and can operate simultaneously to allow reception of a
transmitted frame for use in loopback diagnostics modes.
Functional Description
Frame Check Sequence: The Frame Check Sequence
(FCS) field is a 32-bit cyclic redundancy check (CRC)
value computed as a function of the Destination Address
Field, Source Address Field, Type Field and Data Field.
The FCS is appended to each transmitted frame, and used
at reception to determine if the received frame is valid.
Frame Format
On an Ethernet communication network, information is
transmitted and received in PfJcklJt$ Qr frfJmlJ$, An Ethernet frame consists of a preamble, two address fields, a
byte-count field, a data field and a frame check sequence
(FCS). Each field has a specific format which is described
in detail below. An Ethernet frame has a minimum length
of 64 bytes and a maximum length of 1518 bytes exclusive
of the preamble. The Ethernet frame format is shown
below.
II
I
I
SOURCE
PREAMBLE
(8)
ADDRESS
D~D~-:N
(6)
(6)
I
Transmitting
The transmit data stream consists of the Preamble, four
information fields, and the FCS which is computed in real
time by the EDLC chip and automatically appended to the
frame at the end of the serial data. The Preamble is also
generated by the EDLC chip and transmitted immediately
prior to the Destination Address. Destination Address,
Source Address, Type Field and Data Field are prepared
in the buffer memory prior to initiating transmission. The
EDLC chip encapsulates these fields into an Ethernet
frame by inserting a preamble prior to these information
fields and appending a CRC after the information fields.
I
DATA
FCS
(48-1500)
(4)
c~~
(2)
NOTE:
Field length in bytes in parentheses.
Preamble: The preamble is a 64-bit field consisting of 62
alternating U1"s and "O''s followed by a "11" End-of-Preamble indicator.
Transmission Initiation/Deferral
The Ethernet node initiates a transmission by storing the
entire information content of the frame to be transmitted in
an external buffer memory, and then transferring initial
frame bytes to the EDLC Transmit FIFO. "Transmit-buffer
to FIFO" transfers are coordinated via the TxWR and
TxRDY handshake interface, i.e., bytes are written to the
FIFO via TxWR only when TxRDY is HIGH. Actual transmission of the data onto the network will only occur if the
network has not been busy for the minimum defer time (9.6
ps) and any Backoff time requirements have been satisfied. When transmission begins, the EDLC chip activates
the transmit enable (TxEN) line concurrently with the
transmission of the first bit of the Preamble and keeps it
active for the duration of the transmission.
Destination Address: The Destination Address is a 6-byte
field containing either a specific Station Address, a Broadcast Address, or a A4ulticast Address to which this frame is
directed.
Source Address: The Source Address is a 6-byte field
containing the specific Station Address from which this
frame originated.
Byte-Count Reid: The Byte-Count Field consists of two
bytes providing the number of valid data bytes in the Data
Field, 46 to 1500. This field is uninterpreted at the Data
Link Layer, and is passed through the EDLC chip to be
handled at the Client Layer.
BIT
NAME
, - - - - - RxTx
Rx Tx
RxTx
RxTx
RxTx
RxTx
RxTx
RxTx
I
I
FIRST BYTE
PREAMBlE
lAO .. , A7
'\.
1
...
•
DO
01
D2
D3
D4
os
D6
07
PIN
NO.
6
7
8
9
10
11
12
13
SIXTH BYTE
A8 ... A15
I ... ~ .. I
MO .. , M7
I
SOURCE ADDRESS
/
I
DESTINATION ADDRESS
BITS WITHIN A BYTE TRANSMITTEOt'RECEIVED BIT NO. "0" FIRST THROUGH BIT NO. '7" LAST.
Figure 1.
-
SeeQ
A4D4000241B
Bit Serialization/Deserialization
Technology, Incorporated
4·2
8003
AIS ...... AI
AI6
ARST BYTE
A7
. . . . •.
NI
}
Transmit FIFO is signaled to the EDLC chip by activation
of the RxTxEOF signal concurrently with the last byte of
data loaded into the Transmit FIFO. This line acts as a
ninth bit in the Transmit FIFO. When this last byte is
serialized, the CRC is appended and transmitted concluding frame transmission. The Transmission Successful bit
of the Transmit Status Register will be set by a normal
termination.
DESTINATION
A23 ......
ADDRESS
All ...... A24
(6 BYTES)
Al9 ..•... A32
M7 ...... MO
~ .••••• ~ }~~~~
Collision: Transmission attempted by two or more Ethernet nodes. The Jam sequence is transmitted, the Collision status bit is set, the TxRET signal is generated, and
the Backoff interval begun.
839 ...... 832
847 .•...• B40
T7 . . . . .. TO
TIS ...... T8
) - BYTE COUNT
(2 BYTES)
Underflow: Transmit data is not ready when needed for
transmission. Once transmission has begun, the EDLC
chip on average requires one transmit byte every 800 ns
in order to avoid Transmit FIFO underflow (starvation). If
this condition occurs, the EDLC chip terminates the transmission, issues a TxRET signal, and sets the TransmitUnderflow status bit.
~}?!~AI500
BYTES)
LAST BYTE
Figure 2. Typical Frame Buffer Format for
Byte-Organized Memory
16 Transmission Attempts: If a Collision occurs for the
sixteenth consecutive time, the 16- Transmission-Attempts status bit is set, the Collision status bit is set, the
TxRET signal is generated, and the Backoff interval begun. The counter that keeps track of the number of
collisions is modulo 16 and therefore rolls over on the 17th
collision.
Collision
When concurrent transmissions from two or more Ethernet
nodes occur (collision), the EDLC chip halts the transmission of the data bytes in the Transmit FIFO and transmits
a Jam pattern consisting of 55555555 hex. At the end of
the Jam transmission, the EDLC chip issues a TxRET
signal to the CPU and begins the Backoff wait period.
At the completion of every transmission or retransmission,
new status information is loaded into the Transmit Status
Register. Dependent upon the bits enabled in the Transmit Command Register, an interrupt will be generated for
the just completed transmission. In both collision and
underflow the TxRET signal is activated.
To reinitiate transmission, the initial bytes of the frame
information fields must be reloaded into the EDLC Transmit FIFO. The TxRET is used to indicate to the buffer
manager the need for frame reinitialization. The reloading
of the Transmit FIFO may be done prior to the Backoff
interval elapsing, so that no additional delay need be
incurred to retransmission.
Receiving
The EDLC chip is continuously monitoring the network.
When activity is recognized via the Carrier Sense (CSN)
line going active, the EDLC chip synchronizes itself to the
incoming data stream during the Preamble, and then
examines the destination address field of the frame.
Depending on the Address Match Mode specified, the
EDLC chip will either recognize the frame as being addressed to itself in a general or specific fashion or abort the
frame reception.
Scheduling of retransmission is determined by a controlled randomization process called Truncated Binary
Exponential Backoff. The EDLC chip waits a random
interval between 0 and 2K slot times (51.2 ps per slot time)
before attempting retransmission, where "K"is the current
transmission attempt number (not to exceed 10).
When 16 consecutive attempts have been made at transmission and all have been terminated due to collision, the
EDLC Transmit Control sets an error status bit and issues
an interrupt to the CPU if enabled.
Preamble Processing
The EDLC chip recognizes activity on the Ethernet via the
Carrier Sense line. The Preamble is normally 64 bits (8
bytes) long. The Preamble consists of a sequence of 62
alternating "1's and "O's followed by "11': with the frame
information fields immediately following. In order for the
decoder phase-lock to occur, the EDLC chip waits 16 bit
times before looking for the "11" end ofpreamble indicator.
Terminating Transmission
Transmission Terminates under the following conditions:
Normal: The frame has been transmitted successfully
without contention. Loading of the last data byte into the
seeG
MD4000241B
Technology. Incorporated
4-3
8003
If the EDLC chip receives a "Oon before receiving the "11 n
in the Preamble, an error condition has occurred. The
frame is not received, and the EDLC chip begins monitoring the network for a carrier again.
Carrier Sense Inactive: Indicates that traffic is no longer
present on the Ethernet cable.
Etn!!m!!t ac!dr!!sses consist of two 6-byte fields, ThlJ fir$t
Overflow: The host node for some reason is not able to
empty the Receive FIFO as rapidly as it is filled, and an
error occurs as frame data is lost. On average the Receive
FIFO must be serviced every 800 ns to avoid this condition.
bit of the address signifies whether it is a Station Address
or a Multicast/Broadcast Address.
Frame Reception Conditions
Address Matching
RrstBlt
Upon terminating reception, the EDLC chip will determine
the status of the received frame and conditionally load it
into the Receive Status Register. An interrupt will be
issued if the appropriate conditions as specified in the
Receive Command Register are present. The EDLC chip
may report the following conditions at the end of frame
reception:
Address
0
Station Address (Physical)
1
Multicast/Broadcast Address
(logical)
Address matching occurs as follows:
Overflow: The EDLC internal Receive FIFO overflows.
Station Address: All destination address bytes must
match the corresponding bytes found in the Station Address Register.
Dribble Error: Carrier Sense did not go inactive on a
receive data byte boundary.
Multicast Address: if the first bit of the incoming address
is a 1 and the EDLC chip is programmed to accept
Multicast Addresses, the frame is received.
do!!s not match that calculated upon reception.
CRC Error: The 32-bit CRC transmitted with the frame
Short Frame: A frame containing less than 64 bytes of
information was received (including FCS).
Broadcast Address: The six incoming destination address bytes must all be FF hex. If the EDLC chip is
programmed to accept broadcast or Multicast Addresses
the frame will be received.
Good Frame: A frame is received that does not have a
CRC error, Shortframe or Overflow Condition.
System Interface
The EDLC chip system interface consists of two independent busses and respective control signals. Data is read
and written over the ReceivelTransmit Data Bus RxTxD
(0-7). These transfers are controlled by the TxRDYand
TxWR signals for transmitted data and RxRDY and RxRD
for received data. All Commands and Station Addresses
are written, and all status read over a separate Command!
Status Bus CdSt (0-7). These transfers are controlled by
the CS, RD, WR and AO-A2 signals. The EDLC chip's
command and status registers may be accessed at any
time. However, it is recommended that writing to the
command register be done only during interframe gaps.
If the incoming frame is addressed to the EDLC chip
specifically (Destination Address matches the contents of
the Station Address Register), or is of general or group
interest (Broadcast or Multicast Address), the EDLC chip
will pass the frame exclusive of Preamble and FCS to the
CPU buffer and indicate any error conditions at the end of
the frame. If, however, the address does not match, as
soon as the mismatch is recognized the EDLC chip will terminate reception and issue an RxDC.
The EDLC chip may be programmed via the Match Mode
bits of the Receive Command Register to ignore all frames
(Disable Receiver), accept all frames (Promiscuous
mode), accept frames with the proper Station Address or
the Broadcast Address (Station/Broadcast), or accept all
frames with the proper Station Address, the Broadcast
Address, or all Multicast Addresses (Station/Broadcast/
Multicast).
With the exception of the two Match Mode bits in the
Receive Command Register, all bits in both command
registers are interrupt enable bits. Changing the interrupt
enable bits during frame transmission does not affect the
frame integrity. Asynchronous error events, however,
e.g., overflow, underflow, etc., may cause chip operation
to vary, if their corresponding enable bits are being altered
at the same time.
Terminating Reception
Reception is terminated when either of the following conditions occur:
seeQ
MD4000241B
Reading the status registers may also occur at any time
during transmission or reception.
Technology, Incorporated
4-4
8003
8023
MANCHESTER
CODE
CONVERTER
COLLISION
'~------'I------~/
TO
ETHERNET
TRANSCEIVER
Figure 3. Typical Ethernet Node Configuration
Internal Register Addressing
Register
Address
0
1
2
3
4
5
6
7
A2
A1
AO
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
condition will cause an interrupt to be generated. The four
specific conditions for which interrupts may be generated
are:
• Underflow
• Collision
• 16 Collisions
• Transmission Successful
The interrupt signallNTwill be set when one or more of the
specified transmission termination conditions occurs and
the associated command bit has been set. The interrupt
signal INT will be cleared when the Transmit Status
Register is read.
Register Description
Read
-
-
Rx Status
Tx Status
Write
Station Addr 0
Station Addr 1
Station Addr 2
Station Addr 3
Station Addr 4
Station Addr 5
Rx Command
Tx Command
All bits of the Transmit Command Register are cleared
upon chip reset.
Status Registers are read only registers. Command and
Station Address registers are write only registers. Access
to these registers is via the CPU interface: Control signals
CS, RD, WR, and the Command/Status Data Bus
CdSt (0·7).
Transmit Command Register Format
7 6
~
Station Address Register
The Station Address Register is 6 bytes in length. The
contents may be written in any order, with bit "0" of byte "0"
corresponding to the first bit received in the data stream,
and indicating whether the address is physical or logical.
Bit 7 of station address byte 5 is compared to the last bit of
the received destination address. The Station Address
should be programmed prior to enabling the receiver.
Interrupt on
Interrupt on
Interrupt on
Attempts
Interrupt on
Successful
Transmit Underflow
Transmit Collision
16 Transmission
Transmission
Transmit Status Register
The Transmit Status Register is loaded at the conclusion
of each frame transmission or retransmission attempt. It
provides for the reporting of both the normal and error
termination conditions of each transmission.
The Transmit Command Register is an interrupt mask
register, which provides for control of the conditions allowed to generate transmit interrupts. Each of the four
least significant bits of the register may be individually set
or cleared. When set, the occurrence of the associated
MD400024/B
BIT
Transmission Successful is set only on the successful
transmission or retransmission of a frame.
Transmit Command Register
seeQ
5 4 3 2 1 0
ooo
The OLD/NEW status bit is set each time the Transmit
Status Register is read, and reset each time new status is
Technology, Incorporated
4-5
8003
rence of the corresponding frame reception condition.
They also specify the corresponding types of frames to be
Frames-of-Interest for use by the Receive Status Register
to control status loading.
loaded into the Transmit Status Register. The OLD/NEW
status bit is SET, and all other bits CLEARED upon chip
reset.
Receive Status Register
'1"1 ,I ,I EIIIII
~ T....m.U"'._
~
The Receive Status Register is normally loaded with the
status of each received frame when the frame has been
received or frame reception has been terminated due to an
error condition. In addition, this register contains the Old!
New Status bit which is set when the Receive Status
Register is read or the chip is reset, and cleared only when
status is loaded for a Frame-of-Interest (as defined by bits
0-5 of the Receive Command Register). All other bits are
cleared upon chip reset.
Transmit Collision
16 Transmission Attempts
Transmission Successful
OldlNew Status
Receive Command Register
The Receive Command Register has two primary functions, it specifies the Address Match Mode, and it specifies
Frames-of Interest. i.e. frames whose arrival must be
communicated to the CPU via interrupts and status register updates. Frames-of-Interest are frames whose status
must be saved for inspection, even atthe expense of/osing
subsequent frames.
Receive Status Register Format
7 6 5 4 3 2 1 0
~
Receive Command Register Format
7 6 5 4 3 2 1 0
I I I I I I
I
BIT
I
I
E
L
Interrupt on Overflow Error
Interrupt on CRC Error
Interrupt on Dribble Error
' - - - - Interrupt on Short Frame
' - - - - - Interrupt on End of Frame
Interrupt on Good Frames
Match Mode 0
Match Mode 1
L...=
0
1
1
Receive All Frames
2
1
0
Receive Station or Broadcast
Frames
3
1
1
Receive Station,
BroadcasVMulticast Frames
Function
Receiver Disable
With this one exception caused by a write-protect condition, the status of each frame is always loaded into the
Receive Status Register on completion of reception.
Any frame received will cause an interrupt to be generated
if the corresponding Interrupt Enable bit is set. This
interrupt is reset upon reading the Receive Status Register.
Changing the receive Match Mode bits during frame reception may change chip operation and give unpredictable
results.
Interrupt Enable and Frames-of-Interest
These conditions ensure that a maximum number of good
frames are received and retained.
Bits 0-5 when set specify interrupt generation on occur-
-
SeeQ
MD400024/B
~::~:~ ~~~rt~;;~;~e
Received Good Frame
OldlNew Status
Thus the status of any frame received following the reception of a Frame-of-Interest will not be loaded into the
Receive Status Register unless the previous status has
been read. If any following frame is received before the
status of the previous Frame-of-Interest has been read,
the new status will not be loaded, the Receive Discard
(RxDC) signal will be issued and the Receive FIFO will be
cleared.
Match Mode Definition
Match
Mode
0
0
I
Received Frame with Overflow Error
Received Frame with CRC Error
Received Frame with Dribble Error
The OId!New Status bit write-protects the Receive Status
Register while it contains unread status for a Frame-ofInterest. When this bit is zero, the register is writeprotected. The OId!New Status bit is cleared whenever the
status of a new Frame-of-Interest is loaded into the Receive Status Register and is set after that status is read.
When zero, it indicates "new status for a Frame-ofInterest".
Bits 0-5 specify Interrupt and Frame-of-Interest when set.
Bit 4, End of Frame, specifies any type of frame except
overflow.
Match
Mode
1
0
0
.
BIT
Technology, Incorporated
4-6
8003
bit ofthe Preamble received, and inactive one bit time after
the last bit of the frame is received. Active HIGH.
Vee
A2
CS
AD
COLL Collision (Input): Indicates transmission contention of the Ethernet cable. the Collision input is latched
internally. Sampled during transmission, Collision is set by
an active high pulse on the COLL input and automatically
reset at the end of transmission of the JAM sequence.
WR
CdStO
CdSt1
CdSt2
R xT x D3
CdSt3
RxTxD4
CdSt4
Data Buffer Interface
RxTxD (0-7) RecelvelTransmlt Data Bus (I/O): Carries
ReceivelTransmit data byte from/to the EDLC chip ReceivelTransmit FIFOs.
CdStS
RxTxD6
R xT xD7
TxC
TxWR
TxRDY
RxTxEOF
RxRD
RxRDY
VSS
CdSt6
CdSt7
RxC
RxDC
RxTxEOF ReceivelTransmit End of Frame (I/O): Indicates last byte of data on the ReceivelTransmit Data Bus.
Effectively a ninth bit in the FIFOs with identical timing to
RxTxD (0-7). Active HIGH.
INT
COll
RESET
CSN
RxD
RxRDY Receive Ready (Output): Indicates that at least
one byte of received data is available in the Receive FIFO.
This signal will remain active high as long as one byte of
data remains in the Receive FIFO. When this condition no
longer exists, RxRDY will be deasserted with respect to the
leading edge of the RxRD strobe that removes the last byte
of data from the Receive FIFO. RxRD should not be
activated if RxRDY is low. Active HIGH and cleared by
Reset.
Agure 4. Pin Configuration
Pin Description
The EDLC chip has four groups of interface signals:
• Power Supply
• Data Buffer
• Encoder/Decoder
• Command/Status
Power Supply
Vee .......................................................................... +5V
Vss ..................................................................... Ground
RxRD Receive Read Strobe (Input): Enables transfer of
received data from the EDLC Receive FIFO to the RxTxD
Bus. Data is valid from the EDLC Receive FIFO at the
RxTxD pins on the rising edge of this signal. This signal
should not be activated unless RxRdy is high. Active LOW.
Encoder/Decoder Interface
TxC Transmit Clock (Input): 10 MHz, 50% duty cycle
transmit clock used to synchronize the transmit data from
the EDLC chip to the encoder. This clock runs continuously, and is asynchronous to RxC.
RxDCReceive Discard(OUtput):Assertedwhen one ofthe
following conditions occurs, and the associated Interrupt
Enable bit in the Receive Command Register is reset. (1)
Receive FIFO overflow. (2) CRC Error. (3) Short Frame
Error. (4) Receive frame address nonmatch or (5) current
frame status lost because previous status was not read.
RxDC does not activate on errors when the associated
Interrupt Enable bit is set. In this case, EOF will be
generated instead when the Receive FIFO is read out.
This allows reception of frames with errors. RxDC acts
internally to clear the Receive FIFO.
TxD Transmit Data (Output): Serial Data output to the
encoder. Active HIGH.
TxEN Transmit Enable (Output): This signal is used to
activate the encoder. It becomes active when the first bit
of the Preamble is transmitted and inactive when the last
bit of the frame is transmitted. Active HIGH and cleared by
Reset.
RxC Receive Data (Input): 10 MHz, 50% duty cycle nominal. The receive clock is used to synchronize incoming
data to the EDLC chip from the decoder. This clock runs
continuously, and is asynchronous to TxC.
TxRDY Transmit Ready (Output): Indicates that the
Transmit FIFO has space available for at least one data
byte. This signal will remain active high as long as one byte
of space exists for transmitted data to be written into.
When this condition no longer exists, TxRDY will be
deasserted with respect to the leading edge of the TxWR
strobe that fills the Transmit FIFO. TxRDY is forced
inactive during Reset, and when TxRET is active. Active
HIGH. Goes high after Reset.
RxD Receive Data (Input): Serial input data to the EDLC
chip from the decoder. Active HIGH.
CSN Carrier Sense (Input): Indicates traffic on the coaxial cable to the EDLC chip. Becomes active with the first
seeQ
MD400024/B
Technology, Incorporated
4-7
8003
TxWR Transmit Write (Input): Synchronizes data transfer from the RxTxD Bus to the Transmit FIFO. Data is
written to the FIFO on the rising edge of this signal. This
signal should not be active unless TxRDY is high. Active
LOW
TxR.t TrlJf1!Jml, R.'rlJm",'"
(O~'p~');
(0-7) data lines must be set up relative to the rising edge
of the signal. Active LOW.
INT Interrupt (Output):Enabled as outlined above by a
variety of transmit and receive conditions. Remains active
until the status register containing the reason for the
AS$l!lrtl!ld wnl!ln-
intQ""nt
••••
_ •• -T" .if>
- •rQ".'/
--_.
ever either transmit underflow or transmit collision conditions occur. It is nominally BOO ns in width. Active HIGH.
Asserted by Reset.
TxRET clears the internal Transmit FIFO.
1-11(::1-1
•JJl"tillQ
._ ••• - •••
_ •••
RESET(lnput): Initializes control logic, clears command
registers, clears the Transmit Status Register, clears bits
0-5 of the Receive Status Register, sets the Old/New
Status bit (bit 7 of the Receive Status Register), asserts
RxDC and TxRET and clears the Receive and Transmit
FIFOs. In addition, TxRDY is forced low during a reset.
TxRDY goes high when RESET goes high, indicating the
EDLC chip is ready to transmit. RESET is active LOW.
Command/Status Interface
CdSt(0-7) Command/Status Data Bus (110): These lines
carry commands and status as well as station address
initialization information between the EDLC chip and CPU.
These lines are nominally high impedance until activated
by OS and RD being simultaneously active.
Absolute Maximum Ratings
Ambient Temperature
Under Bias ............................................ -1 DoC to + BOoe
Storage Temperature .......................... -65°e to +150 0 e
AI/Input or Output Voltages
with Respect to Ground ............................ +6V to -O.3V
Package Maximum Power Dissipation ............ 1.5 Watts
AO-A2 Address (0-2) (Input): Address lines to select the
proper EDLC internal registers for reading or writing.
os
Chip Select (Input): Chip Select input, must be active
in conjunction with RD orWR to successfully access the
EDLC internal registers. Active LOW.
Operating Conditions
RD Read (Input): Enables reading of the EDLC internal
registers in conjunction with OS. Data from the internal
registers is enabled via the falling edge of RD and is valid
on the rising edge of the signal. Active LOW.
Ambient Temperature Range ...................... ooe to 70°C
Vee Power Supply ................................. 4.50 V to 5.50 V
WR Write (Input): Enables writing of the EDLC internal
registers in conjunction with OS. Write data on the Cdst
DC Characteristics
TA = 0° C to 70°C, Vee = 5 V to 5%
Llmits(1(
Symbol
Parameter
Min.
Max.
Units
liN
Input Leakage Current
10
~A
VIN = 0.45 V to 5.25 V
10
Output Leakage Current
10
VOUT = 0.45 V to 5.25 V
200
IlA
rnA
6
V
Clock Input Low Voltage
0.8
V
Input Low Voltage
0.8
V
Typ.
150
Condition
Icc
VCH
VCl
Vil
Vcc Current
VIH ,
VIH •
Input High Voltage
2.0
6
V
Except TxWR and RxRD
Input High Voltage
3.0
6
V
TxWR and RxRD
0.4
V
101. = 2.1 rnA
V
IOH = -400
VOL
VOH
Clock Input High Voltage
Output Low Voltage
Output High Voltage
NOTE:
1. Typical values are for Til
seeG
MD4000241B
3.5
2.4
=25°C and nominal supply voltages.
Technology, Incorporated
4-8
~A
8003
AC Test Conditions
Capacitance[6]
Output Load: 1 Schottky TTL Gate + CL = 100 pF
(All pins except TxEN, TxD)
TxEN, TxD Load: 1 Schottky TTL Gate + CL =35 pF
Input Pulse Level:O.4 V to 2.4 V
Timing Reference Level:1.5 V
AC Characteristics
TA
= 0° C to 70°C,
Vee
TA = 25°C, Fe = 1 MHz
Symbol Parameter
CIN
CliO
Maximum
Condition
Input Capacitance
15 pF
I/O Capacitance
15 pF
VIN = 0 V
VI/o = 0 V
= 5 V ± 5%
Limits
Symbol(S)
Parameter
Min.
Typ.
Units
Max.
(ns)
150
ns
150
ns
100
ns
Condition
DATA AND COMMAND/STATUS INTERFACE TIMING
TDBD
RxTxlCdSt Bus Data Delay
TDBR
RxTxlCdSt Bus Release Delay
10
TDBS
RxTxlCdSt Bus Siezure Delay
10
TDRY
RxRDYlTxRDY Clear Delay
THAR
THDA
THRW
TSAR
TSCS
TSRT
TWCH
TWCL
AO-/CS Hold
RxTx/CdSt Bus Hold
ns
10
ns
0
ns
RxRDlTxWR Hold
0
ns
Ao.!CS Setup
0
ns
CdSt Bus Setup
90
ns
RxTx Bus Setup
90
ns
RxRDlTxWRlRDtWR High Width
100
RxRDITWR/RDtWR low Width
200
ns
10,000
ns
150
ns
3400
ns
SERIAL TRANSMIT AND RECEIVE INTEFACE TIMING
TDDC
RxDC Set Delay
TDIC
INT Clear Delay
800
ns
TDRE
TxRET Set Delay
2400
TDRI
Receive INT Delay
1000
TDTD
TxDlTxEN Delay
TDTI
Transmit INT Delay
THRD
TPCK
TSRD
RxD Hold
20
RxClTxC Clock Period
95
RxD Setup
30
ns
TWDC
RxDC High Width
600
ns
TWRC
RxC High/low Width
45
ns
TWRE
TxRET High Width
600
ns
TWRS
RESET low Width
10,000
ns
TWTC
TxC High/low Width
45
ns
TWCO
COll Width
50
ns
20
60
1200
NOTE 1
NOTE 3
ns
NOTE 2
ns
CI
ns
NOTE 4
=35 pF
ns
1000
ns
NOTES:
1. For frame reception with Shortframe or CRC Error. If frame reception is terminated due to Overflow, RxDC will be issued within 1.2 ~s of Overflow. If frame
reception is terminated due to non-match of address, RxDC wil be issued within 2.4 ~s of the receipt of the last address bit.
2. Normal frame reception without Overflow. If frame reception is terminated due to Overflow, INT will be issued within 1.2jJ of Overflow.
3. ForTxRET caused by Collision or 16 Collision condition. If transmission is terminated due to UnderflowTxRETwili be issued within 1.2 ~s of the Underflow.
4. For INT caused by Collision or 16 Collision condition. If caused by Underflow, INT will be issued within 1.2 ~s. If caused by normal termination, INT will
be issued within 200 ns of TxEN going LOW.
5. Italics indicate input requirement, non-italics indicate output timing.
6 Characterized. Not tested.
seeQ
MD4000241B
Technology, Incorporated
4-9
8003
RECEIVE DATA INTERFACE TIMING
Ax
ADY------------------T-D-A-vl--t-f""'~(oon~l ~
=IT-
--~~
AxAD
RxTxDO-7
AxTxEOF
NOTE 1
NOTE 1
TRANSMIT DATA INTERFACE TIMING
T x FIFO (TOP) FULL
TxRDY
THRW
RxTxDO-7
RxTxEOF
THDA
COMMAND/STATUS INTERFACE TIMING
AO-A2, CS
RD
CdSl0-7
NOTE 1: Bus is driven at this time. However, no valid information present.
seeQ
AALJ4000241B
Technology, Incorporated
4-10
8003
SERIAL TRANSMIT INTERFACE TIMING
SERIAL RECEIVE INTERFACE TIMING
TxC
TxD
Tx EN
COll
Tx RET
INT
RD
Ordering Information
D Q
8003
L-~~
seeQ
AfD4000241B
PACKAGE
TYPE
TEMPERATURE
RANGE
PART TYPE
D - CERAMIC DIP
P - PLASTIC DIP
N - PLCC
Q - O°C to +70°C
EDLC
Technology, Incorporated
4-11
4-12
seeQ
8020
MCCTM Manchester
Code Converter
November 1989
Features
• Low Power CMOS Technology with Single SV
Supply
• Compatible with IEEE 802.3 IEthernet (10BASES),
IEEE802.31Cheapernet (10BASE2) and Ethernet
Rev. 1 Specifications
• 20 pin DIP & PLCC Packages
• Compatible with 8003 ELD~J 8005 Advanced
EDLC
Description
• Manchester Data Encoding/Decoding and
Receiver Clock Recovery with Phase Locked
Loop (PLL)
The SEEO 8020 AAanchester Code Converter chip provides the AAanchester data encoding and decoding functions of the Ethernet Local Area Network physical layer. It
interfaces to the SEE08003 and 8005 Controllers and any
standard Ethernet transceiver as defined by IEEE 802.3
and Ethernet Revision 1.
• Receiver and Collision Squelch Circuit and Noise
Rejection Filter
• Differential TRANSMIT Cable Driver
• Loopback Capability for Diagnostics and
Isolation
The SEEO 8020 AACC is a functionally complete Encoder/
Decoder including ECL level balanced driver and receivers, on board oscillator, analog phase locked loop for clock
• Fall-Safe Watchdog Timer Circuit to Prevent
Continuous Transmission
Pin Configuration
• 20 MHz Crystal Oscillator
• Transceiver Interface High Voltage (16 V)
Short Circuit Protection
DUAL-I N LINE
TOP VIEW
Vee
MODE 1
GND
Functional Block Diagram
T~N-------+--------~--------~
LPBKlWDTD
Tx-
Ax.
TxD
TxC
Rx-
CSN
TxC
Tx.
Txo
Tx-
Xl
AxC
X2
COLl.
RxD
COll-
"bc
VSS
CSN
MODEl
Xl
PLASTIC LEADED CHIP CARRIER
TOP VIEW
~
X2
AxC
Rx.
Axo
Ax-
COll.
COll-
COll
Figure 1. 8020 MCC Manchester Code Converter
Block Diagram.
MCC is a trademark of SEEQ Technology Inc.
EDLC is a registered trademark of SEEQ Technology Inc.
AAD4000231C
COll
TRANSMIT
lPBKI
WOTo
seeQ
TxEN
Technology, Incorporated
4-13
II
§
§
>8
~
8020
recovery and collision detection circuitry. In addition, the
8020 includes a watchdog timer, a 4.5 microsecond windowgenerator, and a loopback mode for diagnostic operation.
Together with the 8003 or 8005 and a transceiver, the 8020
Manchester Code Converter provides a high performance
minimum cost interface for any system to Ethernet.
FuncUonalDescripUon
The 8020 Manchester Code Converter chip has two portions, transmitter and receiver. The transmitter uses
Manchester encoding to combine the clock and data into
a serial stream. It also differentially drives up to 50 meters
of twisted pair transmission line. The receiver detects the
presence of data and collisions. The 8020 MCC recovers
the Manchester encoded data stream and decodes it into
clock and data outputs. Manchester Encoding is the
process of combining the clock and data stream so that
they may be transmitted on a single twisted pair of wires,
and the clock and data may be recovered accurately upon
reception. Manchester encoding has the unique property
of a transition at the center of each bit cell, a positive going
transition for a "1': and a negative going transition for a "0"
(See Figure 2). The encoding is accomplished by exclusive-ORing the clock and data prior to transmission, and
the decoding by deriving the clock from the data with a
phase locked loop.
Clock Generator
The internal oscillator is controlled by a 20 MHz parallel
resonant crystal or by an external clock on X1. The 20 MHz
clock is then divided by 2 to generate a 10 MHz±0.01%
transmitter clock. Both 10 MHz and 20 MHz clocks are
used in Manchester data encoding.
Manchester Encoder and Differential Output Driver
The encoder combines clock and data information for the
transceiver. In Manchester encoding, the first halfof the bit
cell contains the complement of the data and the second
half contains the true data. Thus a transition is always
guaranteed in the middle of a bit cell.
Data encoding and transmission begin with TxEN going
active; the first transition is always positive for Tx(-) and
negative for Tx(+). In IEEE mode, at the termination of a
transmission, TxEN goes inactive and transmit pair approach to zero differential. In Ethernet mode, at the end of
the transmission, TxEN goes inactive and the transmitpair
stay differentially high. The transmit termination can occur
at bit cell center if the last bit is a one or at a bit boundary
if the last bit is a zero. To eliminate DC current in the
transformer during idle, Tx± is brought to 100 mV differential in 600 ns after the last transition (IEEE mode). The
back swing voltage is guaranteed to be less than. 1 V.
Watchdog Timer
A watchdog timer is built on chip. It can be enabled or
disabled by the LPBKIWDTD signal. The timer starts
counting at the beginning of the transmission. If TxEN
goes inactive before the timer expires, the timer is reset
and ready for the next transmission. If the timer expires
before the transmission ends, transmission is aborted by
disabling the differential transmitter. This is done by idling
the differential output drivers (differential output voltage
becomes zero) and deasserting CSN.
Differential Input Circuit (Rx+ and Rx-, COLL+ and
COLL-).
As shown in Figure 3, the differential input for Rx+ and Rxand COLL+ and COLL- are externally terminated by a pair
of 39.2 n ± 1% resistors in series for proper impedance
matching.
The center tap has a 0.01J.lF capacitor, tied to ground, to
provide the AC common mode impedance termination for
the transceiver cable.
COLLISION OR
RECEIVE
INPUT
39.2 ± 1%
TRANSCEIVER
CABLE
TRANSMTTED
DATA
(MANCHESTER
ENCODED)
39.2n±1%
Figure 2. Manchester Coding
seeQ
MD4000231C
Figure 3. Differential Input Terminator
Technology, Incorporated
4-14
8020
Both collision and receiver input circuits provide a static
noise margin of -140 m V to -300m V (peak value). Noise
rejection filters are provided at both input pairs to prevent
spurious signals. For the receiver pair, the rangeis 15 ns
to 30 ns. For the collision pair, the range is 10 ns to 18 ns.
The D.C. threshold and noise rejection filter assure that
differential receiver data signals less than -140 mV in
amplitude or narrower than 15 ns (10 ns for collision pair)
are always rejected, signals greater than -300 mV and
wider than 30 ns (18 ns for collision pair) are always
accepted.
Manchester Decoder and Clock Recovery Circuit
The filtered data is processed by the data and clock
recovery circuit using a phase-locked loop technique. The
PLL is designed to lock onto the preamble of the incoming
signal with a transition width asymmetry not greater than
+8.25 ns to -8.25 ns within 12 bit cell times worst case and
can sample the incoming data with a transition width
asymmetry of up to +8.25 ns to -8.25 ns. The RxC high or
low time will always be greater than 40 ns. RxC follows
TxC for the first 1.21ls and then switches to the recovered
clock. In addition, the Encoder/Decoder asserts the CSN
signal while it is receiving data from the cable to indicate
the receiver data and clock are valid and available. At the
end o~ the frame, after the node has finished transmitting,
CSN IS deasserted and will not be asserted again for a
period of 4.51ls regardless of the state of the state of the
receiver pair or collision pair. This is called inhibit period.
There is no inhibit period after packet reception. During
clock switching, RxC may stay high for 200ns maximum.
Collision Circuit
A collision on the Ethernet cable is sensed by the transceiver. It generates a 10 MHz ± 15% differential square
wave to indicate the presence of the collision. During the
collision period, CSN is asserted asynchronously with
RxC. However, if a collision arrives during inhibit period
4.51ls from the time CSN was deasserted, CSN will not be
reasserted.
Loopback
In loopback mode, encoded data is switched to the PLL
instead of Tx+lTx- signals. The recovered data and clock
are returned to the Ethernet Controller. All the transmit and
receive circuits, including noise rejection filter, are tested
except the differential output driver and the differential
input receiver circuits which are disabled during loopback.
At the end of frame transmission, the 8020 also generates
a 650 ns long COLL signal 550 ns after CSN was deassertedto simulate the IEEE 802.3 SQE test. The watchdog
timer remains enabled in this mode.
seeQ
MD400023/C
Pin Description
The MCC chip signals are grouped into four categories:
•
•
•
•
Power Supply and Clock
Controller Interface
Transceiver Interface
Miscellaneous
Power Supply
Vee .......................................................................... +5V
Vss ..................................................................... Ground
X1 and X2 clock (Inputs): Clock Crystal: 20 MHz crystal
oscillator input. Alternately, pin X1 may be used at a TTL
level input for external timing by floating pint X2,
Controller Interface
RxC Receive Clock (Output): This signal is the recovered clock from the phase decoder circuit. It is switched to
TxC when no incoming data is present from which a true
receive clock is derived. 10 MHz nominal and TTL compatible.
RxD Receive Data (Output): The RxD signal is the
recovered data from the phase decoder. During idle
periods, the RxD pin is LOW under normal conditions. TTL
and MOS level compatible. Active HIGH.
l?S~ Carrier Sense (Output): The Carrier Sense Signal
mdlcates to the controller that there is activity on the
coaxial cable. It is asserted when receive data is present
or when a collision signal is present. It is deasserted at the
end of frame or at the end of collision, whichever occurs
later. It is asserted or deasserted synchronously with RxC.
TTL compatible.
TxC Transmit Clock (Output): A 10 MHz signal derived
from the internal oscillator. This clock is always active.
TTL and MOS level compatible.
TxD Transmit Data (Input): TxD is the NRZ serial input
data to be transmitted. The data is clocked into the MCC
by TxC. Active HIGH, TTL compatible.
TxEN Transmit Enable (Input): Transmit Enable, when
asserted, enables data to be sent to the cable. It is
asserted synchronously with TxC. TxEN goes active with
the first bit of transmission. TTL compatible.
Technology, Incorporated
4-15
8020
COLL Collision (Output): When asserted, indicates to
the controller the simultaneous transmission of two or
more stations on network cable. TTL Compatible.
loading. These resistors must be rated at 1 watt to
withstand the fault conditions specified by IEEE 802.3. If
MODE 1=1, after 200 ns following the last transition, the
differential voltage is slowly reduced to zero volts in 8 J.ls
to limit the back swing of the coupling transformer to less
than 0.1 V.
Transceiver Interface
Rx+ and Rx- Differential Receiver Input Pair (Input):
niHaronf;!:J1 '13,..13;II13r in".",f "#!Iir IAI",i,.." hri ... ,..~ ''''n
_ " , .... , ..... ,"'_' ...... ""'.." ..... ,
" ' , . , .... ,., ...."
.. r'IIv"
"""'::I~
,,,,,,,,,,.1,..,./
lillIOil' "",""",,,,, ... ,,,,
Miscellaneous
receive data to the 8020. The last transition is always
positive-going to indicate the end of the frame.
MODE 1 (Input): This pin is used to select between AC or
DC coupling. When it is tied high or left floating, the output
drivers provide differential zero signal during idle (IEEE
802.3 specification). When pin 1 is tied low, then the
output is differentially high when idle (Ethernet Rev.1
specification).
COLL+ and COLL- Differential Collision Input Pair
(Input): This is a 10 MHz± 15% differential signal from the
transceiver indicating collision. The duty cycle should not
be worse than 600/0/40% - 400/0/60%. The last transition
is positive-going. This signal will respond to signals in the
range of 5 MHz to 11.5 MHz. Collision signal may be
asserted if 'MAU not available' signal is present.
LPBKlWDTD Loopback /Watchdog Timer
Disable (Input):
Normal Operation: For normal operation this pin should
be HIGH or tied to Vee In normal operation the watchdog
timer is enabled.
Tx+ and Tx- Differential Transmit Output Pair (Output):
Differential transmit pair which sends the encoded data to
the transceiver. The cable driver buffers are source
follower and require external 243 .Q resistors to ground as
MODE 1
0.01v.F
LPBKt
WOTO
LPBKlWOTD
14
X1
Rx+
13
~
5
1-4"--.-_---1'--.:0..
Ol-A
X2
20pF
5
Rx- 1-'--+_..--+-_1=.2 Ol-B
~
RxC
RxO
CSN
8003
Tx+
COLL
OR
8005
16
TxC
17
TxO
15
19
t-=-...-----=-
OO-A
SEEQ
8020
18
Tx- 1-'--+-_t-_...;.10-,- OO-B
TxEN
12
COLL+ ~--..---=- CI-A
11
COLL- ~--+-..-.....:::.... CI-B
39.20
~0.01jLF
+5
Figure 4. 8020 Interface
seeQ
MD4000231C
Technology, Incorporated
4-16
AUI
CABLE
8020
Loopback: When this pin is brought low, the Manchester
encoded transmit data from TxD and TxC is routed through
the receiver circuit and sent back onto the RxD and RxC
Pins. During loopback, Collision and Receive data inputs
are ignored. The transmit pair is idled. At the end of
transmission, the signal quality error test (SOET) will be
simulated by asserting collision during the inhibit window.
During loopback, the watchdog timer is enabled.
Watchdog Timer Disable: When this pin is between 10 V
(Min.) and 16 V (Max.), the on chip 25 ms Watchdog Timer
will be disabled. The watchdog timer is used to monitor the
transmit enable pin. If TxEN is asserted for too long, then
the watchdog timer (if enabled) will automatically deassert
CSN and inhibit any further transmissions on the Tx+ and
Tx-lines. The watchdog timer is automatically reset each
time TxEN is deasserted.
Interconnection to a Data Link
Controller
Receiver connections are:
Receive Data, RxD
Receive Clock, RxC
Carrier Sense, CSN
D.C. and A.C. Characteristics and
Timing
Crystal Specification
Resonant Frequency (CL
=20 pF) ...................... 20 MHz
± 0.005% 0-70° C
and± 0.003% at 25° C
Type ................................................. Fundamental Mode
Circuit ............................................... Parallel Resonance
Load Capacitance (CL) ............................................ 20pF
Shunt Capacitance (Co) ................................... 7pF Max.
Equivalent Series Resistance (R1) ................. 250. Max.
Motional Capacitance (Ct) ......................... 0.02 pF Max.
Drive Level .............................................................. 2mW
Figure 5 shows the interconnections between the 8020
MCC and SEEO's 8003 or 8005. There are three connections for each of the two transmission channels, transmit
and receive, plus the Collision Signal line (COLL).
Transmitter connections are:
Transmit Data, TxD
Transmit Clock, TxC
Transmit Enable, TxEN
Collision, COLL
EQUIVALENT CIRCUIT OF CRYSTAL
Figure 6.
TxD
TxC
TxEN
lOOPBACK(1)
TxD
-
TxC
TxEN
lOOPBACK
8003
8020
OR
MeC
8005
COll
RxD
RxC
CSN
COll
RxD
RxC
CSN
Figure 5. Interconnection of 8020 and 8003/8005
NOTE
1. Loopback output on 8005 only.
seeQ
MD4000231C
Technology, Incorporated
4-17
8020
·COMMENT: Stresses above those listed under tifl.bsolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabili~v.
Absolute Maximum Rating*
Storage Temperature .......................... -6SOC to +15C1'C
AI/Input or Output Voltage .................. -0.3 to Vee +0.3
Vee .... ............................................................. -0.3 to 7V
(Rx±, Tx±, COLL±) High Voltage
Short Circuit Immunity ............................... -0.3 to 16V
DC Characteristics
TA = O°C to 70C C; vee = 5 V ±5%
Symbol
Parameter
IlL
Input Leakage Current (except
MODE 1, Receive and Collision Pairs)
Min.
MODE 1 Input Leakage Current
Receive and Collision Pairs (RX±,
COLLi) Input Leakage Current
Max.
Unit
Conditions
10
JlA
O~ VIN ~ Vee
200
JlA
O~ V IN ~ Vee
2
rnA
V IN
All Inputs, Outputs Open
75
rnA
-0.3
0.8
V
TTL Input High Voltage (except X1)
2.0
Vee + 0.3
V
X1 Input High Voltage
3.5
Vee + 0.3
V
0.4
0.4
V
V
IOL =2.1 rnA
IOL =4.2 rnA
V
V
tOH = -400 JlA
tOH = -400 JlA
lee
Vee Current
V IL
TTL Input Low Voltage
V IH
VOL
TTL Output Low Voltage except TxC
TxC Output Low Voltage
VOH
TTL Output High Voltage (except
RxC, TxC, RxD)
RxC, TxC, RxD Output High Voltage
VODF
Differential Output Swing
VOeM
Common Mode Output Voltage
V BKSV
Tx± 8ackswing Voltage During Idle
V IDF
Input Differential Voltage
(measured differentially)
2.4
3.9
to.55
±1.2
V
78.0 Termination Resistor and
243.0 Load Resistors
Vee -2.5
Vee-1
V
78.0 Termination Resistor and
243,Q Load Resistors
0.1
V
Shunt Inductive Load:::; 27 JlH
±O.3
t1.2
V
0
VleM
Input Common Mode Voltage
Vee
V
C
Input Capacitance
15
pF
Output Capacitance
15
pF
C
IN
[1)
[1)
OUT
=0
NOTE:
1. Characterized. Not tested
seeQ
MD4000231C
Technology, Incorporated
4-18
8020
AC Test Conditions
Output Loading TTL Output:
Differential Output:
50% point of swing
20% to BO% points
Differential Signal Delay Time Reference Level:
Differential Output Rise and Fall Time:
RxC, TxC, X1 High and Low Time:
High time measured at 3.0V
Low time measured at 0.6V
Measured between 0.6V and 3.0V points
RxD, RxC, TxC, X1 Rise and Fall Time:
TTL Input Voltage (except X1):
X1 Input Voltage: .
Differential Input Voltage:
O.BV to 2.0V with 10 ns rise and fall time
O.BV to 3.5V with 5 ns rise and fall time
At least± 300 mV with rise and fall time of 10 ns measured
between -0.2V and +0.2V
1 TTL gate and 20 pF capacitor.
2430. resistor and 10 pF capacitor from each pin to Vss
and a termination 7Bo. resistor load resistor in parallel with
a 271lH inductor between the two differential output pins
20 MHz TTL Clock Input Timing TA = O°C to 70°C; Vee = 5 V ± 5%
Symbol
Parameter
Min.
Max.
Unit
t1
X1 Cycle Time
49.995
50.005
ns
t2
t3
t4
ts
tSA
X1 High Time
15
Low Time
15
X1
5
ns
X1 Fall Time
5
ns
45
ns
X1
to TxC Delay Time
10
TxC ---...,...---I-~
tSA
Figure 12. 20 MHz TIL Clock Timing
MD4000231C
ns
X1 Rise Time
X1
seeQ
ns
Technology. Incorporated
4-19
8020
Transmit Timing
TA = O°C to 70 0 C; Vee = 5 V ± 5%
Symbol
t (1)
Min.
Max.
Unit
6
TxC Cycle Time
99.99
100.01
ns
t7
TxC High Time
40
t8
t (1)
TxC Low Time
40
TxC Rise Time
5
ns
t (1)
10
TxC Fall Time
5
ns
tll
TxEN Setup Time
40
t12
t (1)
13
t (1)
14
t (1)
15
t (1)
16
TxD Setup Time
40
9
t
ns
ns
100.5
ns
Bit Center to Bit Boundary Time
49.5
50.5
ns
Tx+ and Tx - Rise Time
5
ns
Tx+ and Tx - Fall Time
5
ns
(1)
From Last Positive Transition of the
Transmit Pair to Differential Output
Approaches within 100 mV of 0 V
400
(1)
From Last Positive Transition of the
Transmit Pair to Differential Output
Approaches within 40 mV of 0 V
178
ns
99.5
200
17A
ns
Bit Center to Bit Center Time
Transmit Active Time From The Last
Positive Transition
t17
t
Parameter
ns
600
ns
7000
ns
70
ns
t 18
Tx+ and Tx- Output Delay Time
t 19
TxD Hold Time
15
ns
~o
TxEN Hold Time
15
ns
NOTE:
1. Characterized. Not tested.
seeQ
MD4000231C
Technology, Incorporated
4-20
8020
MODE 1=1
TxC
TxEN
3f.t
T~ 11.J ~"
s
"1"
"1"
\LASTBIT/
"011"
)....,...,.....1_--__.1""""'
Tx± _LA::.;,:S:..:.T.,;:B;;,.:IT,..;O:...--(
Tx± _ _
LA_S_T_B_IT_1_[[X
.p
1~f4
Figure 7. Transmit Timing
MODE 1=0
TxC
TxEN
Til 3f.t
11.~" ;"
Tx (+)
"1"
"1"
I
\LAST BIT
. "0/1" _
=f]
ili
-----rn x: :=diTI
15
1
14
_(_-)"" I r - - -.. 1_-'
LAST BIT = 0
Tx(-)----...1
(-)
(+)
1
I
o
1
'--":'""(-':""")- - - -
16
Tx (+)
LAST BIT = 1
Tx(-) - - - - - .
:::
I
1
·---....,j0
1
I
Figure 8. Transmit Timing
seeQ
~D400023/C
Technology, Incorporated
4-21
1
I
1'----(--)-----
8020
Min.
Symbol
Parameter
t21
CSN Assert Delay Time
t22
CSN Deasserts Delay Time (measured
from Last Bit Boundary)
t23A
CSN Hold Time
t23B
CSN Set up Time
t24
RxD Hold Time
t 25
RxD Set up Time
till
26
t27III
RxC Rise and Fall Time
During Clock Switch RxC Keeps High Time
t 28
RxC High and Low Time
till
RxC Clock Cycle Time (during
data period)
t30
CSN Inhibit Time (on Transmission
Node only)
t31
t32III
Rx+/Rx- Rise and Fall Time
29
t33III
t 34III
40
40
95
4.3
Rx+/Rx- Begin Return to Zero from Last
Positive-Going Transition
ns
ns
ns
ns
5
200
ns
105
ns
4.6
Ils
10
ns
RxD Fall Time
CSN
RxC
RxD
Figure 9. Receive TIming-Start of Packet
Technology, Incorporated
4-22
ns
ns
ns
10
10
RxD Rise Time
ns
ns
160
Rx(+)
MD4000231C
Unit
240
240
30
30
30
30
Rx(-)
seeQ
Max.
ns
ns
8020
RxC
I
CSN
~----------------~,~----~~
-~-------t30-----""'~~1
RxD _ _ _ _
---'1
"1"
\'-"_O"_ _ _ _ _ _ _ _ _ _ _ _
Figure 1o. Receive Timing-End of Packet
seeQ
AfD4000231C
Technology, Incorporated
4-23
~H§-------
8020
Collision Timing
T" = ODC to 70 DC; Ycc = 5 V ±5%
Symbol
Parameter
tSl
COLL+ ICOLL - Cycle Time
tS2
COLL+/COLL - Rise and Fall Time
tS3
COLL+/COLL - High and Low Time
35
tS4
COLL+/COLL - Width (measured at -0.3 V)
26
tss
COLL Asserts Delay Time
300
ns
tS6
COLL Deasserts Delay Time
500
ns
tS7
CSN Asserts Delay Time
tS8
CSN Deasserts Delay Time
400
600
ns
Min.
Max.
Unit
86
118
ns
10
ns
70
ns
ns
ns
NOTES:
1. COll + and COll - asserts and deasserts COll, asynchronously, and asserts and deasserts CSN synchronously with RxC.
2. If COll + and COll - arrives within 4.5J.LS from the time CSN was deasserted; CSN will not be reasserted (on transmission node only).
3. When COll + and COll - terminates, CSN will not be deasserted if Rx+ and Rx- are still active.
4. When the node finishes transmitting and CSN deasserted, it cannot be asserted again for 4.5 J.LS.
COll(+)
COll(-)
COll
1'4---t57--~~~{
T~---------~j~~--------------
CSN
------------------~
Figure 11. Collision Timing
seeQ
MD4000231C
Technology. Incorporated
4-24
8020
Loopback Timing
= O°C to 70°C; Vee = 5 V ± 5%
TA
Symbol
Parameter
Min.
t61
LPBK Setup Time
t62
LPBK Hold Time
t63
In Collision Simulation, COLL Signal
Delay Time
500
5
475
625
ns
t64
COLL Duration Time
600
750
ns
Max.
ns
Ils
NOTES:
1. PLL needs 12-bit cell times to acquire lock, RxD is invalid during this period.
LPBKIWDTD
TxC
TxEN
I
'1'
I
'0'
I
I
'1'
'0'
I
'0'
1r--'l_·--:...I~~..:..I_'l_'---:....I__f--_ _ _ __
TXD,~_ _..J
(lAST BIT)
COll
(NOTE 1)
RxC
~
CSN
RxD _ _ _ _ _ _ _ _ _ _ _ _ _
~~
Figure 13. Loopback Timing
seeG
A4D4000231C
Technology, Incorporated
4-25
Unit
8020
Ordering Information
r----T---r
D Q
seeQ
MD4000231C
8020
PACKAGE
TYPE
TEMPERATURE
RANGE
PRODUCT
P - PLASTIC DIP
N - PLASTIC LEADED
CHIP CARRIER
O°C to +70°C
MCC MANCHESTER
CODE CONVERTER
Technology, Incorporated
4-26
seeQ
B023A
MCCTM Manchester
Code Converter
November 1989
Features
Description
• Compatible with IEEE 802.3 /Ethernet (10BASE5),
IEEE802.3ICHEAPERNET (10BASE2) and Eth
ernett Rev. 1 Specifications
The SEEO 8023A Manchester Code Converter chip provides the Manchester data encoding and decoding functions of the Ethernet Local Area Network physical layer. It
interfaces to the SEEO 8003 and 8005 Ethernet Data Link
Controllers or to the Intel 82586 LAN Controller and any
standard Ethernet transceiver as defined by IEEE 802.3
and Ethernet Revision 1.
• Compatible with 8003 ELDC~, 8005 Advanced
EDLC and Intel 82586 LAN Controller
• Manchester Data Encoding/Decoding and
Receiver Clock Recovery with Phase Locked
Loop (PLL)
• Receiver and Collision Squelch Circuit and Noise
Rejection Filter
The SEEO 8023A MCC is a functionally complete Encoder/Decoder including ECL level balanced driver and
receivers, on board oscillator, analog phase locked loop
for clock recovery and collision detection circuitry. In
addition, the 8023A includes a 25 millisecond watchdog
timer, a 4.5 microsecond window generator, and a
loopback mode for diagnostic operation.
• Differential TRANSMIT Cable Driver
• Loopback Capability for Diagnostics and
Isolation
• Fal/-Safe Watchdog Timer Circuit to Prevent
Continuous Transmission
Together with the 8003 or 8005 and a transceiver, the
8023A Manchester Code Converter provides a high performance minimum cost interface for any system to Ethernet.
• 20 MHz Crystal Oscillator
Transceiver Interface High Voltage (16 V) Short
Circuit Protection
•
• Low Power CMOS Technology with Single 5V
Supply
DUAL-IN-LiNE
TOP VIEW
Pin Configuration
• 20 pin DIP & PLCC Packages
MODE 1
VCC
Functional Block Diagram
TxEN
----.-------<1>-----------1
LPBKlWDTD
Tx-
Ru
TxO
Rx-
TxC
(CSN)CSN
TxC
Tx+
Tx-
TxO
TRANSMIT
LPBKI
WOTD
TxEN (TxEN)
(COlL)COLL
Xl
(RxC)RxC
X2
RxO
COlL+
VSS
COlL-
VCC
VSS
CSN
MODEl
Xl
MODE 2
X2
PLASTIC LEADED CHIP CARRIER
o TOPVIEW
II i § ~ ~
RECEIVE
RxC
<}=RX+
Rx-
RxD
--t--1;.::.2 01-6
1=
RxC
RxO
CSN
COll
8005
OR
82586
16
17
15
19
Tx+ I--'-'-__
---~
DO-A
SEEQ
8023A
TxC
TxO
TxEN
18
Tx- t-.:..=...-+-~>--_1:..:..0 DO-B
COll+
12
I---~>---=--
CI-A
11
COll- ~---I---1J-"::'" CI-6
MOOE2
~O.Q1"F
Figure 4. 8023A Interface
seeQ
MD4000221B
Technology, Incorporated
4-30
AUI
CABLE
B023A
MODE signal active HIGH, or by aI/owing it to float HIGH
with its internal pul/up. In this configuration, RxC, TxEN,
CSN and COLL become active LOW. In addition, RxD is
HIGH during idle, and RxC has 1.21ls discontinuity during
signal acquisition.
Transmitter connections are:
LPBK/WDTD LoopbacklWatchdog Timer Disable
(Input):
Normal Operation: For normal operation this pin should
be HIGH or tied to VCe" In normal operation the watchdog
timer is enabled.
Receiver connections are:
Transmit Data, TxD
Transmit Clock, TxC
Transmit Enable, TxEN
Collision, COLL
Receive Data, RxD
Receive Clock, RxC
Carrier Sense, CSN
Compatibility with Other LAN Controllers
SEEO's 8023A is compatible with other LAN Controllers,
such as the 82586, when Pin 2 (MODE2) of the 8023A is
floating or tied to Vcc. In this mode (1( operation, timing and
polarity on the controller interface lines are compatible,
with the 82586 specifications dated March 1984.
Loopback: When this pin is brought low, the Manchester
encoded transmit data from TxD and TxC is routed through
the receiver circuit and sent back onto the RxD and RxC
Pins. During loopback, Collision and Receive data inputs
are ignored. The transmit pair is idled. At the end of
transmission, the signal quality error test (SOET) will be
simulated by asserting collision during the inhibit window.
During loopback, the watchdog timer is enabled.
Use of Time Domain Reflectometry in the 82586 is not
recommended since the TDR transmission does not have
a valid preamble.
Watchdog Timer Disable: When this pin is between 10 V
(Min.) and 16 V (Max.), the on chip 25 ms Watchdog Timer
will be disabled. The watchdog timer is used to monitor the
transmit enable pin. If TxEN is asserted for longer than
25 ms, then the watchdog timer (if enabled) will automatically deassert CSN and inhibit any further transmissions
on the Tx+ and Tx-lines. The watchdog timer is automatically reset each time TxEN is deasserted.
D.C. and A.C. Characteristics and
Timing
Crystal Specification
Resonant Frequency (CL = 20 pF) ...................... 20 MHz
± 0.005% 0-70° C
and ± 0.003% at 25° C
Type ................................................. Fundamental Mode
Circuit ............................................... Parallel Resonance
Load Capacitance (CL ) ........................................... 20pF
Shunt Capacitance (Co) .................................. 7pF Max.
Equivalent Series Resistance (R1) ................. 25n Max.
Motional Capacitance (C 1) ......................... 0.02 pF Max.
Drive Level .............................................................. 2mW
Interconnection to a Data Link Controller
Figure 5 shows the interconnections between the 8023A
MCC and SEEO's 8003 or 8005. There are three connections for each of the two transmission channels, transmit
and receive, plus the Collision Signal line (COLL).
TxD
TxC
TxEN
LOOPBACK[l]
TxD
-
TxC
TxEN
LOOPBACK
8003
OR
8005
8023A
MCC
COLL
RxD
COll
RxD
RxC
RxC
CSN
CSN
MODE 2
EQUIVALENT CIRCUIT OF CRYSTAL
J..
Figure 6.
Figure 5. Interconnection of 0023A and 0003/0005
NOTE
1. Loopback output on 8005 only.
seeQ
MD4000221B
Technology, Incorporated
4-31
B023A
"COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods ma~y affect device reliability.
Absolute Maximum Range'"
Storage Temperature ......................... -65°C to +150°C
AI/Input or Output Voltage .................. - 0.3 to Vee +0.3
Vee .... ............................................................. -0.3 to 7V
(RXi, TXi, COLL±) High Voltage
Short Circuit Immunity ............................... -0.3 to 16V
DC Characteristics
TA =O°C to 70°C; vee =5 Vi 10%
Symbol
Parameter
Max.
Unit
Conditions
IlL
Input Leakage Current (except
MODE1, MODE2 Receive and
Collision Pairs)
Min.
10
IlA
o ~ VIN ~ Vee
MODE11nput Leakage Current
200
2
IlA
rnA
VIN
75
rnA
All Inputs, Outputs Open
Receive and Collision Pairs(Rxt,
COLLi) Input Leakage Current
o ~ VIN ~ Vee
=0
Icc
Vee Current
V IL
TTL Input Low Voltage
-0.3
O.S
V
V IH
TTL Input High Voltage (except X1)
2.0
Vee + 0.3
V
X1 Input High Voltage
3.5
Vee + 0.3
V
0.4
0.4
V
V
IOL = 2.1 rnA
IOL =4.2 rnA
V
V
tOH
tOH
VOL
TTL Output Low Voltage except TxC
TxC Output Low Voltage
VOH
TTL Output High Voltage (except
RxC,TxC,RxD)
RxC, TxC, RxD Output High Voltage
VODF
Differential Output Swing
VOeM
Common Mode Output Voltage
V BKSV
Txt Backswing Voltage During Idle
V IDF
Input Differential Voltage
(measured differentially)
VleM
C [1[
IN
C [1]
OUT
2.4
3.9
=-400 ~
=-400 IlA
to.55
i1.2
V
7Sn Termination Resistor and
243n Load Resistors
Vee -2.5
Vee-1
V
7Sn Termination Resistor and
243n Load Resistors
0.1
V
Shunt Inductive Load :s; 27 IlH
to.3
i1.2
V
0
Vee
15
V
Input Capacitance
pF
Output Capacitance
15
pF
Input Common Mode Voltage
NOTE:
1. Characterized. Not tested
seeQ
MD400022JB
Technology, Incorporated
4-32
B023A
A.C. Test Conditions
Output Loading TTL Output:
1 TTL gate and 20 pF capacitor.
Differential Output:
2430. resistor and 10 pF capacitor from each pin to Vss
and a termination 7Bo. resistor load resistor in parallel with
a 27~H inductor between the two differential output pins
Differential Signal Delay Time Reference Level:
50% point of swing
Differential Output Rise and Fall Time:
20% to BO% points
RxC, TxC, X1 High and Low Time:
High time measured at 3.0V
Low time measured at 0.6V
RxD, RxC, TxC, X1 Rise and Fall Time:
Measured between O. 6V and 3.0 V points
TTL Input Voltage (except X1):
O.B V to 2.0 V with 10 ns rise and fall time
X1 Input Voltage:
O.BV to 3.5V with 5 ns rise and fall time
Differential Input Voltage:
At least± 300 mV with rise and fall time of 10 ns measured
between -0.2V and +0.2V
20 MHz TTL Clock Input Timing TA = O°C to 70°C; Vee =5 V ± 10%
Symbol
Parameter
Min.
Max.
Unit
t1
X1 Cycle Time
49.995
50.005
ns
t2
t3
t4
X1 High Time
15
ns
X1
Low Time
15
ns
X1 Rise Time
5
ns
ts
X1 Fall Time
5
ns
tSA
X1
45
ns
to TxC Delay Time
10
X1
TxC - - - - - - - + - ; 7 1
Figure 12. 20 MHz TTL Clock Timing
seeQ
MD4000221B
Technology, Incorporated
4-33
B023A
Transmit Timing
TA =0°Ct070°C;Vcc =5V±10%
Symbol
Parameter
Min.
Max.
t(1)
6
TxC Cycle Time
99.99
100.01
40
TxC LowTime
40
Unit
ns
ns
t7
TxC High Time
t8
t(1)
TxC Rise Time
t (1)
10
TxC Fall Time
tl1
TxEN Setup Time if Mode 2=0
TxEN Setup Time if Mode 2=1
40
55
ns
ns
t12
TxD Setup Time if Mode 2=0
TxD Setup Time if Mode 2=1
40
55
ns
ns
t (1)
13
t (1)
14
t (1)
15
t )1)
16
Bit Center to Bit Center Time
99.5
100.5
ns
Bit Center to Bit Boundary Time
49.5
50.5
ns
Tx+ and Tx - Rise Time
5
ns
Tx+ and Tx - Fall Time
5
9
ns
5
5
ns
ns
ns
t17
Transmit Active Time From The Last
Positive Transition
200
t
(1)
17A
From Last Positive Transition of the
Transmit Pair to Differential Output
Approaches within 100 mV of 0 V
400
t
(1)
178
From Last Positive Transition of the
Transmit Pair to Differential Output
Approaches within 40 mV of 0 V
t 18
Tx+ and Tx- Output Delay Time
t 19
TxD Hold Time if Mode 2=0
TxD Hold Time if Mode 2=1
15
0
ns
ns
t20
TxEN Hold Time if Mode 2=0
TxEN Hold Time if Mode 2=1
15
0
ns
ns
NOTE:
1. Characterized. Not tested.
seeG
MD4000221B
Technology, Incorporated
4-34
ns
600
ns
7000
ns
70
ns
B023A
MODE1 = 1
MODE2=0
TxC
s
"1"
"1"
\LAST BIT/
.
"011"
_
TX± _LA_ST_B_IT_O_-C
TX±
LAST BIT 1
rnv
------\.J!:l.A
K:
1--..jO
Figure 7. Transmit Timing
MODE1 =0
MODE2=0
TxC
J
"1"
\LASTBIT/
"0/1"
m
(+)
1
TX(+)-----VT-iV
LASTBIT=1~
I
K:
0
1 ' - - - -.....
I
1
NOTE:
1. If MODE 2=1, TxEN becomes active low signal TxEN.
MD4000221B
o
1
-(:-:-)~---
:Ifill,----I
Figure 8. Transmit Timing
seeG
TI
t 15
(-)
LAST BIT =0
Tx(-)----..I
Tx (-)
"1"
Technology, Incorporated
4-35
1
I
1
(-)
B023A
Receive Timing TA = O°C to 70°C; Vee = 5 V± 10%
Symbol
Parameter
t21
CSN Assert Delay Time
t22
CSN Deasserts Delay Time (measured
from Last Bit Boundary)
t23A
t23B
CSN Hold Time
t24
CSN Deassertion Delay Time
~5A
t25B
t (1)
26
t [1)
27
RxD Hold Time
t28
t (1)
29
t30
t31
t [1)
32
Min.
30
30
10
30
30
CSN Set up Time
RxD Set up Time
RxC, AxC Rise and Fall Time
[1)
35
[1)
36
35
ns
ns
ns
5
ns
ns
105
ns
4.3
4.6
J..1s
1.15
10
1.35
J..1s
240
ns
CSN Inhibit Time (on Transmission
Node only)
Rx+/Rx- Rise and Fall Time
RxC Held Low Duration from First Valid
Negative-Going Transition
RxD Rise Time
ns
160
Technology, Incorporated
4-36
ns
ns
10
10
RxD Fall Time
1. Characterized. Not tested.
MD4000221B
ns
40
95
RxC, AxC Clock Cycle Time (during)
Data Period
NOTE:
seeQ
ns
RxC, AxC High and Low Time
Rx+/Rx- Begin Return to Zero from Last
Positive-Going Transition
t
ns
200
t
t
ns
40
RxC Stops Delay Time from First Valid
Negative-Going Transition
[1)
Unit
240
240
During Clock Switch RxC Keeps High,
AxC Keeps Low Time
t33
34
Max.
ns
ns
B023A
Rx(+)
Rx(-)
MODE2=O
CSN
RxC
RxD
MODE2=1
CSN
~
t
/ 4 - - - - - - 32
RxC
~:r----
-----------fS.r---~5A
'25B
136
RxD
Figure 9. Receive Timing-Start of Packet
MODE2=O
AxC
AxH -S
(LAST BIT - 0)
I---------fd
CSN
-~I------t30------j---I~
AxD _ _ _ _
~~~"O_'_ _ _ _ _ _ _ _ _ ___fSrS------
MODE2=1
AxC
(LAST BIT - 1)
CSN - - - - - - - - - - -
.J/
'I"
"I"
14-----,~==r-SS
AxD _ _ _
Figure 10. Receive Timing - End of Packet
seeQ
MD4000221B
Technology, Incorporated
4-37
B023A
Symbol
Parameter
t51
COll+ ICOll -
Cycle Time
t52
COll+/COll -
Rise and Fall Time
ts~
COll+/COll -
High and low Time
t54
COll+/COll - Width (measured a1 -0.3 V)
155
COll Asserts Delay Time
156
COll Deasserts Delay Time
157
CSN Asserts Dealy Time
158
CSN Deasserts Delay Time
Min.
Max.
Unit
86
118
10
70
ns
35
26
ns
ns
ns
300
500
400
600
ns
ns
ns
ns
NOTES:
1. COll + and COll - asserts and deasserts COll, asynchronously, and asserts and deasserts CSN synchronously with RxC.
2. If COll + and COll - arrives within 4.5~ from the time CSN was deasserted; CSN will not be reasserted (on transmission node only).
3. When COll + and COll - terminates, CSN will not be deasserted if Rx+ and Rx- are still active.
4. When the node finishes transmitting and CSN is deasserted, it cannot be asserted again for 4.5 fJS.
5. If MODE 2=1, then COll and CSN are inverted.
MODE 2=0
COll(+)
COll(-)
COll
~---t57---I"~{
T~---------~$$~---------------
CSN
--------------------~
Figure 11. Collision Timing
seeQ
MD4000221B
Technology, Incorporated
4-38
B023A
Loopback Timing
TA
= O°C to 70°C; vee =5 V ± 10%
Max.
Unit
Symbol
Parameter
Min.
tS1
lPBK Setup Time
500
ns
tS2
lPBK Hold Time
5
f..Ls
tS3
In Collision Simulation, COll Signal
Delay Time
475
625
ns
tS4
COll Duration Time
600
750
ns
NOTES:
1. PLL needs 12-bit cell times to aquire lock, RxD is invalid during this period. Rxe is low for 1.35 IlS (max) if MODE2 = 1.
RxD = 0 if MODE2 = O. RxD = 1 if MODE2 = 1.
MODE 2=0
lPB!
2804A
v
v;!.
CJl
:J
m
::i:
SEE
NOTE_-\
~
I\
)
CJl
>CJl
II>
.A
~
;!.
8
"
.......
V't-- -
~
K... 0 -015 "-/
'---_/
L-
8
"15
~
'I
G
0
00 -07
IT
NOT NEEDED
IN 8·BIT MODE
0 - 0
APEN'
20~
a
:;;!; =r=
~
lPBK'
"
2O~Z
COLl
TxEN
Ao
A3
READYIDTACK'
ADo
AD1
INT/INT"
AD2
lACK'
AD3
AD.
TERMCT!TERMeT"
ADs
CS'
AD7
AD5
BUSSIZE
RAS'
BUSMOOE
CAS'
Vee
W'
Vss
G'
"
'-
./
A4D4000311C
o
ffi~
0.01 UF
~
{)
~
«
U
243 OHMS 1% 1 W.
=
5V~
I ADo
Ao
AD1
A1
AD2
A2
A3
AD3
0
~
A.
A5
AD.
i.,
A6
AD5
ADs
f/)
::IE
A7
IRAS'
AD7
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CAS'
DO:!
Do.!
W'
001 I - - -
G'
000
Ao
A1
0000
0000
A2
A3
0
~
A.
..;
As
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As
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A7
::IE
I-
CnCn
~~~~
III
\
INTERCONNECT DIAGRAM
/
MOTOROLA MODE
seeQ
z:5
".'OHM'"
~~
)
.........
\~/
~
0-2
:J
TxD
DREOIDREQ'
DACK'
CE'
{)
8005
RESET"
('~)
/
w
if
a:
TxC'
~
--
0.01 UF
<
RxC
lOR'
A2
,..-
8020
-
Tx.
Tx-
".,OHM'"
~~
-
>
X2
RxD
A1
NOTE:
Call.
COll-
Vss
X1
~20a
ClK
::r:
IOW'IA.w.
R.W. (MOTOROlA MODE)
~
CSN
EN"
lOR' (INTEL MODE)
l?
l?
Do-~
~
A......---r;-"
Rx •
Rx-
Vee
=
Technology, Incorporated
4-47
-'--
1----5
i.;1.
PRELIMINARY
8005
Bit 7: XmltlReceive. This bit is always set to 0 by the
controller to indicate a receive packet header.
the allowed 1514 bytes, excluding preamble and CRC.
If babble occurs with bit O-Xmit Babble Int. Enable set
to a 1 on byte 3, the Transmit Command byte, the
transmitter will abort transmission and turn itself off.
The fourth byte of the header, called the Packet Status
byte, contains status information resulting from processing the packet associated with this block.
Bit 1: Xmit Collision. If set to a one, a collision
occurred during the transmission attempt.
Bit 0: Oversize Packet. If this bit is a one, the packet
• ... __ 1 _____ £L _ _ <4
wa.:>
la/~f;1
Illall
co 2000 V
Mil-STD 883
Meth.3015
NOTES: 1. This parameter is measured only for the initial qualification and after process or design changes which may affect
capacitance.
2. Characterized. Not tested.
seeQ
MD4000311C
Technology, Incorporated
4-57
8005
PRELIMINARY
A.C. Characteristics (Assuming 20 MHz Input Master Clock)
(Over operating temperature and Vcc range, unless otherwise specified)
Table A. Bus Write Cycle - BUSMODE
=a
Ref. #
Symbol
Description
1
2
TAVCSL
Address Setup TIme
30
ns
TRWLCSL
FuW· Setup Time
30
ns
3
TCSLCSH
CS* Pulse Width
100
ns
4
TDVCSH
Data Setup TIme
70
ns
5
6
7
8
9
TCSHDX
Data Hold TIme
20
TCSLDTL
DTACK* Assertion Delay"
60
ns
TCSHDTH
DTACK* Deassertion Delay
60
ns
10
TCSHRWX
11
TCSHCSL
12
TCSHDTL
Write Recovery Time:
a. FIFO Data Write 1
b. Configuration Regs 1.2
c. Pointer Regs. 3
Min.
TDTHDTZ
DTACK* Hi-Z Delay
TCSHAX
Address Hold Time
Max.
Units
ns
50
ns
20
ns
RIW* Hold TIme
20
ns
CS* High TIme
200
ns
800
800
1800
ns
ns
ns
ns
13
TCSLENL
EN* Assert Delay
50
ns
14
TCSHENH
EN* Deassert Delay
50
ns
15
TCSLDTV
CS* Assert to DTACK* Valid
50
ns
NOTES:
1. Write Recovery Time is for 16 bit writes. If BUSSIZE = 0 (8 bit writes), subtract 200 ns.
2. Configuration Registers are: Command/Status Register, Configuration Register #1 & 2, Interrupt Vector Register, and Station Address
Registers.
3. Pointer Registers are: Receive End Area Pointer, Receive Pointer Register, Transmit Pointer Register, Transmit End Area Register,
and DMA register. If BUSSIZE = 0, subtract 600 ns.
4. The trailing edge of CS* initiates an internal write sequence. Should another CS· occur during this time, the assertion of DTACK* will
be delayed until the internal write sequence has finished (Ref. # 12, TCSHDTL).
5. After changing the Buffer Code (Config. Reg. #1 bits 0-3), Ref. #11 must be increased to 800 ns before a Buffer Window access is done
in order to allow time for the new Buffer Code to propagate internally.
seeQ
MD4000311C
Technology, Incorporated
4-58
8005
PRELIMINARY
AO-A3
~--------QD--------~~
CS
~-----0---~
DO -D15
DTACK
-------+---<
-------+-....1
@
EN
Figure A. Bus Write Cycle Timing Diagram - BUSMODE
seeQ
MD4000311C
Technology, Incorporated
4-59
=0
8005
PRELIMINARY
A.C. Characteristics (Assuming 20 MHz Input Master Clock)
(Over operating temperature and Vee range, unless otherwise specified)
Table B. Bus Read Cycle - BUSMODE
=0
Ref. #
Symbol
Description
1
TAVCSL
Address Setup Time
30
ns
2
TRWHCSL
RIW* Setup Time
30
ns
3
TCSLDTL
DTACK* Assert Delay
a. FIFO Data 1
b. Configuration Regs. 2
c. Other Pointer Regs. 3
Min.
Max.
60
800
1800
4
TDTLDV
Time from DTACK* Asserted to Data Valid
5
TCSLCSH
CS* Pulse Width
50
100
Units
ns
ns
ns
ns
ns
ns
6
TCSHDTH
DTACK* Deassertion Delay
60
ns
7
TDTHDTZ
DTACK* Hi-Z Delay
50
ns
8
TCSHDZ
Data Hi-Z Delay
100
9
TCSHDX
Data Hold Time
20
ns
10
TCSHRWX
RIW* Hold Time
20
ns
11
TCSHAX
Address Hold Time
20
ns
12
TCSHCSL
CS* High Time
13
TCSLAPL
APEN* Assert Delay
400
ns
14
TCSHAPH
APEN* Deassert Delay
50
ns
15
TCSLENL
EN* Assert Delay
50
ns
16
TCSHENH
EN* Deassert Delay
50
ns
17
TCSLDTV
CS* Assert to DTACK* Valid
50
ns
200
ns
ns
NOTES:
1. The BIU pre fetches one word (byte) of FIFO data. Thus, data is generally available immediately and DTACK* will assert within
50 ns. Following the read, the BI U will fetch the next word (byte) of data. Should another data read occur before the BIU has completed
the prefetch, DTACK* will be delayed until the prefetch is completed. The assert delay in this case is 650 ns max (450 ns in 8 bit mode).
2. Configuration Registers are: Command/Status Register, Configuration Register # 1 & 2, Interrupt Vector Register, DMA Pointer
Register, and Station Address Registers. If BUSSIZE = 0 (8 bit reads), subtract 200 ns.
3. Pointer Registers are: Receive End Area Pointer, Receive Pointer Register, Transmit Pointer Register, and Transmit End Area
Register. If BUSSIZE =0, subtract 600 ns.
seeQ
MD4000311C
Technology, Incorporated
4-60
8005
PRELIMINARY
@ f4-
~
-K
~:
AO-A3
--""'f}f-
Rm
~
®
-4-@)~
~
~
®
-k-
~
-~
~®~
r
® __
®
~r"..
/~
00-015
HI-Z
o~~
~
{
--""v
~®...
- ~,
\
J
0----
-
®
\k-
APEN
---- (j) ~
~
@
- t
@
\~
EN
Agure B. Bus Read Cycle Timing Diagram -
seeQ
AfD4000311C
Technology, Incorporated
4-61
BUSMODE
=0
HI-Z
PRELIMINARY
8005
A.C~
Characteristics (Assuming 20 MHz Input Master Clock)
(Over operating temperature and Vee range, unless otherwise specified)
Table C. Inte"upt Cycle - BUSMODE
Ref. #
I
2
3
4
5
6
7
8
9
10
11
Symbol
Description
IUILUV
I ime nom U I "'\.If\. ",$Sen 10 Uclla valla
TIALDTV
TIAHDX
TIAHDZ
TIAHDTH
TDTHDTZ
TRWHIAL
TIAHRWX
TIALENL
TIAHENH
TIALDTV
seeQ
MD4000311C
=0
Min.
DTACK* Assert Delay
Data Hold from IACK* Deassert
Data Hi-Z from IACK* Deassert
DTACK* Deassert Delay
DTACK* Hi-Z Delay
R/W* Setup Time
R/W* Hold Time from IACK*
EN* Assert Delay
EN* Deassert Delay
IACK* Assert to DTACK* Valid
Technology, Incorporated
4-62
Max.
Units
ou
ns
600
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
100
60
50
30
20
50
50
50
8005
PRELIMINARY
INT~S
5
lACK
S
00-07
OTACK
HI-Z
S
®
®
EN
Figure C. Interrupt Cycle Timing Diagram - BUS MODE
seeQ
MD4000311C
Technology, Incorporated
4-63
=0
8005
PRELIMINARY
A.C~ Characteristics (Assuming 20 MHz Input Master Clock)
(Over operating temperature and Vee range, unless otherwise specified)
Table D. DMA Read Cycle - BUSMODE
Ref.'
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Symbol
TRWHDAL
TDALDAH
TDTLDV
TDAHDX
TDAHDZ
TDAHDAL
TDAHRWX
TDALTCL
TTCLDRH
TDALDRH
TDALDTL1
TDAHDTH
TDTHDTZ
TDALENL
TDAHENH
TDALDTV
TDALDTL2
Description
R/W* Setup Time
DACK* Pulse Width 1
Time from DTACK* Asserted to Data Valid
Data Hold Time
Data Hi-Z Delay
DACK* High Time
R/W* Hold Time
TERMCT* Asserted While DACK* Asserted
DREQ* DelayS
DREQ Delay After End of DMA Burst6
DTACK* Assertion Delay2
DTACK* Deassertion Delay
DTACK* Hi-Z Delay
EN* Assert Delay
EN* Deassert Delay
DACK* Assert to DTACK* Valid
Read Recovery Time3•4
=0
Min.
30
100
Max.
50
20
100
200
20
125
175
100
60
60
50
50
50
50
800
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
1. DACK* must be asserted until DTACK* is asserted and for a minimum of 100 ns.
2. This delay applies only if the 8005 is "ready" when DACK* is asserted i.e. the first read of a burst, or a read that occurs after the
Ref. 117 TDALDTL2 period has elapsed.
3. The BIU pre-fetches FIFO data. Thus, data is available immediately for the first read of any burst. Once the BIU detects a read operation,
it begins fetching the next byte or word of data. This occurs during the Ref.•17 TDALDTL2 period. If a subsequent DACK" occurs
within the Ref.•17 TDALDTL2 period, DTACK" will stay de-asserted until the FIFO data has been fetched. If the subsequent DACK"
does not occur until after the Ref.•17 TDALDTL2 period has elapsed, then the 8005 is "ready" and Ref. .11 TDALDTL1 applies.
4. Subtract 200 ns if BUSSIZE - 0 (8 bit mode).
5. DACK* and TERMCT" must both be active at the same time and for a minimum of 125 ns. The de-assertion of DREO" is timed from
the last one to assert.
6. Ref. '10 TDALDRH applies for normal DMA burst terminations - not those due to TERM CT.
All the timing in this lable also apply when reading data with programmed 110; CS* replaces DACK" and the DREO" and TERMCr signals
do not apply. AO-A3 setup times are the same as RIW".
seeQ
MD4000311C
Technology, Incorporated
4-64
8005
PRELIMINARY
DREQ
DO-D1S------H----<.
HI-Z
~ACK--~H~I-Z~--+JI
EN
Figure D. DMA Read Cycle Timing Diagram -
seeQ
MD4000311C
Technology, Incorporated
4-65
BUSMODE
=0
8005
PRELIMINARY
A.C. Characteristics (Assuming 20 MHz Input Master Clock)
(Over operating temperature and Vee range, unless otherwise specified)
Table E. DMA Write Cycle - BUSMODE
Ref ••
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
TRWLDAL
TDALDAH
TDVDAH
TDAHDX
TDAHDAL
TDALTCL
TDAHRWX
TTCLDRH
TDALDRH
TDALDTL
TDAHDTH
TDTHDTZ
TDALENL
TDAHENH
TDALDTV
TDAHDTL
Description
RJW* Setup Time
DACK* Pulse Width 1
Data Setup Time
Data Hold Time
DACK* High Time
TERMCT* Asserted While DACK* Asserted
RJW* Hold Time
DREQ* DelaYS
DREQ Delay After End of DMA Burst6
DTACK* Assertion Delay2
DTACK* Deassertion Delay
DTACK* Hi-Z Delay
EN* Assert Delay
EN* Deassert Delay
DACK* Assert to DTACK* Valid
Write Recovery Time3.4
=0
Min.
Max.
30
100
70
20
200
125
20
175
100
60
60
50
50
50
50
800
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. DACK* must be asserted until DTACK* is asserted and for a minimum of 100 ns.
2. This delay applies only if the 8005 is ·ready· when DACK* is asserted i.e. the first write of a burst, or a write that occurs after
Ref. 1# 16 TDAHDTL period has elapsed.
3. The trailing edge of DACK* initiates an intemal write sequence that lasts a maximum of 800 ns in 16 bit mode. Should another DACK*
occur during this period, DTACK* will remain de-asserted until Ref. #16 TDAHDTL period has elapsed. If the subsequent DACK* does
not occur until after the intemal write sequence has ended, then the 8005 is ·ready· and Ref. # 10 TDALDTL applies.
4. Subtract 200 ns when BUSSIZE = 0 (8 bit mode).
5. DACK* and TERMCr must both be active at the same time and for a minimum of 125 ns. The de-assertion of DREO* is timed from
the last one to assert.
6. Ref. 1#9 TDALDRH applies for normal DMA burst terminations - not those due to TERM CT.
All the timing in this table also apply when writing data with programmed 110; CS* replaces DACK* and the DREO*, TERMCT* signals
do not apply. Ao-A3 times are the same as R/W".
seeQ
MD4000311C
Technology, Incorporated
4-66
8005
PRELIMINARY
OREQ
DO - 015
------1-+---<..
HI-Z
OTACK-------+-JI
HI-Z
EN
Figure E. DMA Write Cycle Timing Diagram - BUSMODE
eeeG
MD4000311C
Technology, Incorporated
4-67
=0
PRELIMINARY
8005
A.C. Characteristics (Assuming 20 MHz Input Master Clock)
(Over operating temperature and Vee range, unless otherwise specified)
Table F. Bus Write Cycle - BUSMODE = 1
Ref.'
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Symbol
TAVWL
TCSLWL
TWLWH
TDVWH
TWHDX
TWLRYL
TCSLRYV
TCSHRYZ
TWHAX
TWHCSH
TWHWL
TWHRYH
TCSLENL
TCSHENH
Description
Address Setup Time
CS* Setup Time
IOW* Pulse Width
Data Setup Time
Data Hold Time
READY Deassert Delay
CS* Asserted to READY Valid4
READY Delay to Hi-Z
Address Hold Time
CS* Hold Time
IOW* High times
Write Recovery Time:
a. FIFO Data Write1
b. Configuration Regs. 1.2
c. Pointer Registers. 3
EN* Assert Delay
EN* Deassert Delay
Min.
30
30
100
70
20
Max.
35
50
50
20
20
200
800
800
1800
50
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Recovery time is for 16 bit writes. If BUSSIZE - 0 (8 bit writes), subtract 200 ns.
2. Configuration Registers are: CommandlStatus Register, Configuration Register '1, & 2, Interrupt Vector Register, and Station Address
Registers.
3. Pointer Registers are: Receive End Area Pointer, Receive Pointer Register, Transmit Pointer Register, Transmit End Area Register,
and DMA Register. If BUSSIZE - 0, subtract 600 ns.
4. The trailing edge of IOW* initiates an internal write sequence. Should another IOW* occur during this sequence, READY de-asserts
(Ref. 1# 6 TWLRYL) and then asserts after the internal write sequence has finished (Ref. '12 TWHRYH). If the subsequent IOW* does
not occur until after the internal write sequence has ended, then Ref. 1# 6 TWLRYL has no meaning since READY does not de-assert
under this condition.
5. After changing the Buffer Code (Config. Reg.'1 bits 0-3), Ref. '11 must be increased to 800 ns before a Buffer Window access is done
in order to allow time for the new Buffer ZCode to propagate intemally.
seeQ
MD4000311C
Technology. Incorporated
4-68
8005
PRELIMINARY
®
@
AO-A3
cs
00-015
-------+-<1
READY _~H.;.;..I-.;;;;.Z_ _ _ _+--,'
Figure F. Bus Write Cycle Timing Diagram - BUSMODE = 1
seeQ
MD4000311C
Technology, Incorporated
4-69
8005
PRELIMINARY
A.C. Characteristics (Assuming 20 MHz Input Master Clock)
(Over operating temperature and Vcc range, unless otherwise specified)
Table G. Bus Read Cycle - BUSMODE
=1
Ref. #
Symbol
Description
1
TAVRL
Address Setup Time
30
ns
----_.-
Min.
Max.
Units
1a
TCSLRL
CS* Setup Time
30
ns
2
3
TRHRL
IOR* High Time
200
ns
TRLRYH
READY Assert Delay
a. FIFO Data 1
b. Configuration Regs. 2
c. Pointer Registers. 3
35
800
1800
ns
ns
ns
ns
4
TRLRYL
READY Deassertion Delay
35
ns
5
TRYHDV
READY Assert to Data Valid
50
ns
6
TCSHRYZ
READY Delay to Hi-Z
50
ns
7
8
9
TRHDX
Data Hold Time
TRHDZ
Data Delay to Hi-Z
TRHAX
Address Hold Time
20
ns
10
TRHCSH
CS* Hold Time
20
ns
100
20
ns
100
ns
11
TRLRH
IOR* Pulse Width
12
TRLAPL
APEN* Assert Delay
ns
13
TRHAPH
APEN* Deassert Delay
50
ns
14
TCSLENL
EN* Assert Delay
50
ns
15
TCSHENH
EN* Deassert Delay
50
ns
16
TCSLRYV
CS* Assert to READY Valid
50
ns
400
ns
NOTES:
1. The BIU prefetches one word (byte) of FIFO data. Thus, data is generally available immediately and READY will not de-assert during
a data read. Following the read, the BIU will fetch the next word (byte) of data. Should another data read occur before the BIU has
completed the prefetch, READY will first de-assert and then assert after the prefetch is completed. The assert delay in this case is
800 ns max (600 ns in 8 bit mode).
2. Configuration Registers are: Command/Status Register, Configuration Register # 1, & 2, Interrupt Vector Register, DMA Pointer
Register, and Station Address Registers. If BUSSIZE = 0 (8 bit reads), subtract 200 ns.
3. Pointer Registers are: Receive End Area Pointer, Receive Pointer Register, Transmit Pointer Register, and Transmit End Area
Register. If BUSSIZE = 0, subtract 600 ns.
seeQ
MD4000311C
Technology, Incorporated
4-70
8005
PRELIMINARY
@
Ao-A3
cs
lOR
DO-D15------------~--~--------~
HI-Z
READY _.....;H..;.;,I-..;;;Z_______+-..tl
APEN
EN
Figure G. Bus Read Cycle Timing Diagram -
seeQ
MD4000311C
Technology, Incorporated
4-71
BUSMODE
=1
8005
PRELIMINARY
A.C. Characteristics (Assuming 20 MHz Input Master Clock)
(Over operating temperature and Vee range, unless otherwise specified)
Table H. Interrupt Cycle - BUSMODE
Ref.'
2
3
4
5
6
7
8
9
10
11
seeQ
MD4000311C
Symbol
...... _..
I
I
Description
TIJV~nV
I
TRLRYL
TRLRYH
TRHDZ
TIAHRYZ
TRHDX
TIALRL
TIALENL
TIAHENH
TIALRYV
TRHIAH
READY Deassertion Delay
READY Assert Delay
Data Delay to Hi-Z
READY Delay to Hi-Z
Data Hold from lOR·
lACK· Setup Time
EN· Assert Delay
EN· Deassert Delay
lACK· Assert to READY Valid
lACK· Hold Time from lOR·
. _• • _
• • • _ _ _ • • •_ _ _ . _
Technology, Incorporated
4-72
=1
Min.
.. _ I I .....
Max.
Units
I;;n
..,...,
.....
35
600
100
50
20
30
50
50
50
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8005
PRELIMINARY
INT
- - - fr4
S
\'--~!
DO-D7------In------i------?Dtt ~2 ,
0
I
PI.
~
7
10 2 (3)
~
8
1
~
~
ARP
11 3 (4)
16
r=>?Dtt ~
I
23
124(5)
24
I
r=>?Dtt
31
13 5 (6)
32
~
~.
PI.
~
~
r=>?Dtt ~
I
39
ARP
14 S (7)
40
~
r=>?Dtt ~
I
47
1
56
1
63
64
~
r=>?Dtt ~
1
71
ARP
1810 (12)
72
...
79
~
.....AI
21 (25) 1107
.....AI
20 (24) IlOs
I
19 (23) 110 5
.... ,
.... ,
....A
~,
......A1
-0<1
PIN NUMBERS REFER TO DIP (PLCC PINOUT)
Technology, Incorporated
5-7
18 (21) 1104
~I
....
..A
r
17 (20) 1103
""""T
,-
r=>?~ 2
39
MD4000651B
,.
,.
,.
~
ARP
--j~
seeQ
n
ARP
~
22 (2S) 1108
~I
~Dtt ~
55
1911 (13)
......AI
n
r=>?Dtt o-wn
48
17 9 (11)
2
ARP
15 7 (9)
23 (27) 1109
....
~Dtt o-w
15
IS 8 (10)
...A l
....A
1
16 (19) 1102
~I
.....A
r
15 (18) 1101
~I
....A
I
14 (17) 110 0
~,
..A
""""
13(1S)OE
EEPLD
20RA10Z
Stresses above those listed under ABSOLUTE MAXIMUM RA TING may cause permanent device failure.
Functionality at or above these limits is not implied.
Exposure to absolute maximum ratings for extended periods may affect device reliability.
Absolute Maximum Ratings
Supply voltage, Vee" ................................ -0.5 V to 7 V
DC input voltage, V .. ................... -0.5 V to VCC + 0.5V
DC output voltage Va' ................ -0.5 V to VCC + 0.5 V
DC output source/sink ................................................... .
""""~~~,,~.~
±35 mA
current per output pin;
DC Vee or ground current, lee or IGND *100 mA
Input diode current, I,K
VI < 0 ............................................................. -20mA
VI > Vee·· ...................................................... +20mA
Output diode current, 10K
VO < 0 ............................................................ -20mA
Vo > Vee' ...................................................... +20 mA
Storage temperature ............................. -6SOC to 150"C
Static discharge voltage ................................... > 2001 V
Latchup current ............................................... > 100 mA
Ambient Temperature under bias ........ -5SOC to +12SOC
'0·
DC Characteristics
..................
Operating Ranges
Commercial (0) Devices
Temperature (TA)
Operating Free Air ............................... O°C to +7SOC
Supply voltage, Vee- ....................... .4.75 V to 5.25 V
Industrial (E) Devices
Temperature (T)
Case ................................................ -40°C to +8SOC
Supply voltage, Vee- ............................ 4.5 V to 5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
(over operating conditions unless otherwise specified)
Min.
Max.
Unit
V IL
Low-level Input Voltage
Guaranteed Input Logical Low
Voltage for all Inputsl 1J
0
0.8
V
V IH
High-level Input Voltage
Guaranteed Input Logical High
Voltage for all Inputsl1J
2
Vee
V
IlL
Low-level Input Current
Vee = Max.
IIH
High-level Input Current
Vee = Max.
VOL
LOW-level Output Voltage
Symbol
Test Conditions
Parameter
VI =GND
VI =Vee
1
IlA
V
Vee = Min.
10L = 8 rnA
0.5
0.05
Vee = 5V
10L = 1 ~
VOH
High-level Output Voltage
Vee = Min.
10H =-4.0 rnA
3.80
Vee = 5V
10l = -1 IlA
4.95
lozl
Off-state Output Current
VCC =Max.
Vo = GN[)I4J
[4J
Vo = Vee
-10
10ZH
lee
IlA
-1
IlA
IlA
10
Standby Supply Current[2J
10 = 0 rnA, VI = GND or Vee
150
IlA
Operating Supply Current[3]
f = 1 MHz, 10= 0 rnA, VI = GND or Vee
25
rnA
Notes: 1. These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or
tester noise. Do not attempt to test these values without suitable equipment.
2. Disabled output pins = Vcc or GND.
3. Frequency of any input. See gragh page 12 for Icc versus frequency
4. I/O pin leakage is worst case of III and lozl (or IIH and 10HZ).
CapaCitance
Parameter
Symbol
CIN
COUT
Parameter Description
Test conditions
Input capacitance[1]
V IN = 2.0 V at f = 1.0 MHz
Vec =5VTA =25°C
7
VOUT = 2.0 V at f = 1.0 MHz
Vee =5VTA =25°C
8
Output capacitance[1]
Note: 1. Sampled but not 100% tested.
SeeQ
MD400065/B
Technology, Incorporated
5-8
Typ.
Unit
pF
EEPLD
20RA10Z
Switching Characteristics
(over commercial operating range(11)
-35(5)
Symbol
Parameter(2)
Min.
Max.
-45(6)
-40
Min.
Max.
Min.
40
35
Max.
Unit
ns
45
tpD
Input or Feedback to Output
ts
Setup Time for Input or Feednack to Clock
15
tH
Hold Time
10
teo
Clock to Output or Feedback(3 )
twp
Preload Pulse Width
25
30
30
ns
tsup
Preload Setup Time
20
25
25
ns
t HP
Preload Hold Time
20
20
20
15
15
40
30
ns
ns
45
ns
25
25
ns
tAP
Asynchronous Preset to Registered Output(3 )
t APW
Asynchronous Preset Pulse Width
25
25
30
ns
tAPR
Asynchronous Preset Recovery Time
10
15
15
ns
tWL
Width of Clock
15
20
20
ns
LOW
HIGH
tWH
=teo)
45
35
ns
45
15
20
20
ns
22.2
16.6
15.3
MHz
f MAX
Maximum
Extenal Feedback 1Its
Frequency
No Feedback 1/(twL =lwH)
tpzx
Common Enable to Output Buffer Enabled
20
25
30
ns
tpxz
Common Enable to Output Buffer Disabled
20
25
30
ns
tEA
Input to Output Buffer Enabled(4)
30
40
45
ns
tER
Input to Output Buffer Disabled(4)
30
40
45
ns
33.3
25
25
MHz
Note:
1. The 20RA10Z is designed for the full military operating range. Contact your nearest SEEQ representative for availability
information and for specifications of industrial and military devices.
2. Test conditions are specified in table on page 12.
3. Minimum values of these parameters are guaranteed to be larger than the hold time tH"
4. Equivalent functions to tpz/~xz but using product term control.
5. Preliminary specification.
6. The 20RA1 OZ-45 is available and specified for commercial and industrial operating conditions.
Remarks: All specified input-to-output delays include the time it takes the input edge detection circuitry to activate the device (from
standby mode into operating mode).
Data Retention and Endurance
Symbol
Parameter
Value
Unit
Conditions
tOR
Pattern data retention time
>10
years
Max. storage temperature
Mil-STD 883 Test Method 1008
N
Min. reprogramming cycles
100
cycles
Operating conditions
seeQ
MD4000651B
Technology, Incorporated
5-9
EEPLD
20RA10Z
Switching Waveforms
~
VT
INPUT OR
FEEDBACK
COMBINATORIAL
OUTPUT
~.
tPD~-VT-----
- - - - - - - - - - - -__
COMBINATORIAL OUTPUT (BYPASS MODE)
~~
~f
INPUT OR
FEEDBACK
I~VT
J~
ts
tH
"t-If VT
CLOCK
teo
REGISTERED
OUTPUT
\
I
I I I ... 1
AIII I I I I I I I I I lfH-V
AIAAAIIAIAIA.'\ T
REGISTERED OUTPUT (REGISTERED MODE)
OE
OUTPUT
COMMON ENABLE (OE) TO OUTPUT DISABLE/ENABLE
IINPUT
OUTPUT
INPUT TO OUTPUT DISABLE/ENABLE
eeeQ
MD4000651B
Technology, Incorporated
5-10
EEPLD
20RA10Z
Switching Waveforms (continued)
tWH
IVT
CLOCK
1f
tWL
CLOCK WIDTH
t APW
ASYNCHRONOUS
PRESET
REGISTERED
OUTPUT
CLOCK
ASYNCHRONOUS PRESET
tARW
ASYNCHRONOUS
RESET
REGISTERED
OUTPUT
CLOCK
ASYNCHRONOUS RESET
L
OE
I/O
I~W~I
PL
--------~----~
tsup
~----~--------
t HP
PRELOAD TIMING
seeQ
MD4000651B
Technology, Incorporated
5-11
EEPLD
2DRA1DZ
Switching Test Laod
iR1
Specification
OUTPUT ,..0_-4--_._--_-+(,.:\) TEST POINT
~R2
~'
R~
Ct.
R~
Measured
Output Value
tlL,teo
SO pF 4400. 190n
1.SV
tpzx' ~A
SO pF 4400. 190n
Z-H: 2.0V
Z-L: O.BV
tpxz' ~R
SpF
440n 190n
H - Z: VOH -O.S V
L - Z: VOL + O.SV
Icc Versus Frequency
TYPICAL: Vee = SV, TA = 2SoC
100
~::- ~
25/. . .
o
5
10
15
20
INPUT FREQUENCY (MHz)
Key to Timing Diagrams
WAVEFORM
INPUTS
OUTPUTS
DON'T CARE:
CHANGE PERMITIED
CHANGING:
STATE UNKNOWN
NOT APPLICABLE
CENTER LINE IS
HIGH IMPEDANCE STATE
MUST BE STEADY
WILL BE STEADY
'\\~\\\\
MAY CHANGE FROM
HTOL
WILL BE CHANGING
FROM HTOL
//!/!////
MAY CHANGE FROM
L TO H
WILL BE CHANGING
FROM L TO H
'-- SeeQ
MD4000651B
Notes:
Technology, Incorporated
5-12
1. Vr = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times 2 - 5 ns typical
EEPLD
20RA10Z
fMAX Parameters
The second type of design is a simple data path application. In this case. input data is presented to the flip-flop and
clocked through; no feedback is employed. Under these
conditions. the period is limited by the sum of the data
setup time and the data hold time (ts + tH). However. a
lower limit for the period of each fMAX type is the minimum
clock period (tWH + twJ Usually. this minimum clock period
determines the period for the second fMAX' designated
The parameters fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because flexibility
inherent in programmable logic devices offers a choice of
clocked flip-flop designs. fMAX is specified in this case for
two types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs. or to a second device in a multichip state machine. The slowest path defining the period
is the sum of the clock-to-output time and input setup time
for the external signals (ts + ted' The reciprocal. fMAXI is the
maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAXI External Feedback. ..
Itf
..
MAX. No feedback
ClK
r-----I
lOGIC
REGISTER
- - - -
1-
...
- - -
--I ...
ts
J-o---...........~ (SECOND CHIP)
-.J
teo
f MAX, External Feedback; 1/(ts + teo)
- - - - -
r
lOGIC
ClK
REGISTER
I
L
I ...
- - -
ts
.+~-tH-....j
f MAX, No Feedback; 1/(ts + t H) or 1/(tWH + t wL )
seeQ
MD4000651B
Technology, Incorporated
5-13
..I . .
ts~
EEPLD
20RA10Z
PLD Development
PLD Programmer Vendors
Development software assists the user in implementing a
design in one or several PLDs. The software converts the
user's input into a device dependent fuse map in JEDEC
format. The software packages listed below support the
20RA 1OZ EEPLD. For more information about PLD de·
velopment software contact SEEQ Technology or the soft·
ware vendor directly:
Adams MacDonald
DATA liD Corp.
10525 Willows Road, NE, P.O. Box 97046,
Redmont, WA 98073·9746
(800) 247·5700
Software offered: ABEL, PLD Test
800 Airport Road, Monterey, CA 93940
(408) 373·3607
DATA liD Corp.
10525 Willows Road NE, P.O. Box 97046
Redmont, WA 98073·9746
(800) 247·5700
PLD Programming equipment:
System 29A or 29B
Logic Pak™ 303A·V04
Adaptor 303·011A for 24 pin DIP
303·011B for 28 pin PLCC
Family Pinout Code for 20RA 1OZ: 9EI45
Mlnc. Incorporated
1575 York Road, Colorado Springs, CO 80918
(719) 590·1155
Software offered: PLDesigner
Log/cal Devices, Inc.
Digl/ec Inc.
22736 Vanowen, Canoga Park, CA 91307
(800) 367·8750; CA: (818) 887·3755
Logical Devices Inc.
1021 N. W. 65th Place, Fort Lauderdale, FL 33309
(305) 974·0967
Software offered: CUPL
1201 N. W. 65th Place, Fort Lauderdale, FL 33309
(305) 974·0967
PROMOC
PLD Programming
The 20RA 10Z can be programmed on standard logic
programmers. Previously programmed devices can be
reprogrammed easily, using exactly the same procedure
as required for blank EEPLDs. If the user wants to erase
a 20RA 10Z, but not program it to a new pattern, an empty
JEDEC file should be loaded into the device programmer.
see Adams MacDonald
Stag Microsystems Inc.
1600 Wyatt Dr., Santa Clara CA 95054
(408) 988·1118
For more information about PLD programmers contact
SEEQ Technology or the programmer vendor directly.
Logic Pak is a trademark of DATA I/O Corporation.
seeQ
MD4000651B
Technology, Incorporated
5-14
This page has been left blank intentionally.
5-15
This page has been left blank intentionally.
5-16
This page has been left blank intentionally.
5-17
This page has been left blank intentionally.
5-18
EEPLD
20RA10Z
Ordering Information
P
Q
20
RA
10
Z - 35
~
L
PACKAGE TYPE
P = PLASTIC DIP
D = CERAMIC DIP
N = PLCC
L= LCC
-
t PO
' - - - - - - NUMBER OF OUTPUTS
OUTPUT TYPE
R = REGISTERED
A =ASYCHRONOUS
Technology, Incorporated
t PO
t PO
' - - - - ZERO STANDBY POWER
NUMBERS OF ARRAY INPUTS
MD4000651B
=35 ns
=40 ns
45 =45 ns
- 40
- 35
OPERATING RANGE
Q = COMMERCIAL
E = INDUSTRIAL
M = MILITARY
seeQ
SPEED
5-19
5-20
seeQ
EEPLD
26V12H-20125
June 1989
PRELIMINARY DATA SHEET
Features
•
28-pin versatile CMOS EEPLD with halfpower (only
105 mAl at high speed - 20 ns propagation delay
•
Quickly and easily reprogram mabie in all
package types
•
14 dedicated inputs and 12 input/output macro
cells for architectural flexibility
•
Space saving 0.3" wide 28-pin Ceramic/Plastic DIP
and LCC/PLCC surface mount packages
•
Macro cells are a superset of the 22V10 architecture with additional feedback paths In the output
logic to offer 8 different configurations
•
Center VCC and GND pins to improve signal
characteristics and minimize noise sensitivity
•
100 reprogramming cycles, minimum
•
Silicon security bit for design secrecy
•
Reprogrammable macro cells can be conffguredto
be registered or combinatorial and active HIGH or
active LOW
•
Varied product term distribution allows up to 16
product terms per output
•
Two independent clocks
•
Extra terms provide global asynchronous reset
and synchronous preset for initialization
•
Built-in register reset on power-up and register
preload to facilitate testing
•
10 year data retention guaranteed
•
Supported by ABEU'" version 3.1 software and
other design tools
•
Programmed on Sprint and other standard logic
programmers
•
Fully tested for 100% field programming/functional
yield and high reliability
Block Diagram
CLKlI
PROGRAMMABLE
AND ARRAY
(52.150)
ABEL is a trademark of DATA VO Corporation
seeQ
MD400075
Technology, Incorporated
5-21
ASYNC.
RESET
EEPLD
26V12H
26V12H Super Macrocell
OE~~-----------------------------------,
Pn----o-~
n _ 8,8,10,12,14,16
So - Active HIGH I LOW Output
81 - Combinational I Registered Output
82-Clk1orClk2
83 - Changes Feedback Path
8P
* When &J - 1 (unprogrammed) the feedback is selected by 81.
When 83 - 0 (programmed), the feedback is opposfte of
that selected by 81.
General Description
the programmed state is a '0'. In the unprogrammed state,
all AND product terms float HIGH. If both true and complement of any input are connected the term will be permanently LOW.
The EEPLD 26V12H is a 2S-pin version of the popular
PAL22V10 architecture. It is manufactured using SEEQ's
low power, high speed, 1 micron single poly double metal
Electrically Erasable CMOS technology. The 26V12H
offers many unique advantages over the 22V1 0 because
of its superior macrocell architecture. The 26V12H macrocell offers S distinct 110 configurations, twice that possible
with the 22V1 O. In addition to increased functional density,
the 26V12H offers low power operation at high speed
when compared to 22V10 bipolar equivalents; it consumes only 105 mA (half power) with 20 ns propagation
delay.
The product terms are connected to the fixed OR array with
a varied distribution. There are 6 pairs of product terms
beginning at Sproduct terms per output and incrementing
by 2 to 16 product terms per output. The OR sum of the
products feeds the output macro cell. Each macrocell can
be programmed to be registered or combinatorial, active
HIGH or active LOW, with registered feedback possible.
The flip-flops can be clocked by one of two clock inputs to
implement independent registered functions. The output
configuration is determined by four electrically erasable
bits controlling three multiplexers in each macro cell.
Bipolar devices cannot be reprogrammed while UVerasable PLDs can be reprogrammed only in windowed, ceramic packages. Electrically erasable devices offer reprogrammability without constraints in all package types,
Functional Description
Reprogrammability reduces development costs and eliminates the risks involved in preprogramming production
quantities, Systems can be updated quickly by reconfiguring the EEPLDs. Reprogrammability allows SEEQ to
perform extensive AC and DC tests on the EEPLDs and
thus offer 100% field programming yield and high reliability.
The EEPLD 26V12H has fourteen dedicated input lines,
two of which can be used as clock inputs. Unused inputs
should be tied directly to ground or Vee' Buffers for device
inputs and feedbacks feature both active high and active
low outputs to offer user-selectable signal polarity. The
inputs drive a programmable AND logic array which feeds
a fixed OR logic array.
The 26V12H with its 12 input/output macrocells utilizes the
familiar sum-of-products (ANDIOR) architecture that allows the designers to implement complex logic functions
easily and efficiently. The user defined functions are
programmed into the device through Electrically Erasable
floating gate cells in the AND logic array and the macro
cells. The unprogrammed state of an EE cell is a '1' while
seeQ
MD400075
Technology, Incorporated
The fixed OR gates feed twelve 110 super macrocells. The
26V12H super macrocell is shown above. The super
macrocell allows Sunique output configurations, twice that
possible with the 22V10 macrocell. In addition there are
two clock inputs (pin1 and pin4) allowing the user to
implement independent register functions.
5-22
EEPLD
26V12H
a 2:1 feedback multiplexer. The multiplexer controls intitially float to Vee (1) through a reprogrammable EE cel/,
selecting the "1" path through the multiplexer. Programming the EE cell connects the control line to GND (0),
selecting the "0" path. The state of an unprogrammed or
erased EE cell is a "1" while the programmed state of the
cell is a "0". See Configuration Table 1 on page 5. For
details on state of EE bits So - 53 and corresponding output
configuration selected. The unprogrammed state is a
combinatorial active HIGH I/O pin feedback configuration.
The reprogrammable functions on the EEPLD 26V12H are
automatically configured from the User's design specifications. The design specifications are processed by development software. Third party software packages like
ABEL from Data I/O allow users to enter PLD designs on
personal computers or engineering workstations. Common input formats are: Boolean Algebra, Truth tables,
State diagrams or Schematics. The software processes
the design specifications, verifies the design and automatically creates a programming file containing the EE cell
pattern. These programming files, once downloaded to
PLD programmers, configure PLDs according to the user's
specifications.
Registered or Combinatorial Outputs
Each super macro cell of the EEPLD 26V12H includes a 0type flip-flop fordata storage and synchronization. The flipflop is loaded on the LOW to HIGH edge of the selected
clockinput(Clk1-pin1 orClk2-pin4). Anysupermacrocell
can be configured as combinatorial by selecting a multiplexer path that bypasses the flip-flop. Bypass is controlled
by bit S, (Table1 page 5).
Configuration Options
The super macrocell in the 26V12H allows 8 different
output configurations as shown on page 4. The outputs
can be either registered or combinatorial, and active high
or active low with register or I/O pin feedback. The configuration choice is made according to the design needs of the
user. Various configurations are selected by programming 4 configuration EE cell bits So - S3' EE bits S2 and S3
are unique to the 26V12H. The reprogrammable bits in
each super macrocell control a 4:1 output multiplexer and
Programmable Clock
The clock input for any flip-flop can be selected from one
of two inputs either pin 1 or pin 4. The two individual clock
Pin Configurations
(Top View)
PLCC PINOUT
LCCPINOUT
SLIM DIP PINOUT
a
<::
~
~
a
d~~g
27
14 5
26
25 !JOg
LI
!JOg
15
6
24 !JOa
IlOa
Vee
7
23 110 7
!J07
16
a
22 1106
17
g
21
18 10
20 !JO s
11
19 1104
Ig
12
a
13
-
14
N
15
16 17
1106
GND
GND
!JO s
la
!J04
1a
~ ~ g, ~
N
a
~
N
-r .:-
~ ~ g,N
Pin Designations: I = Input
110 = Input/Output
ClK = Clock Input
Vee = Supply Voltage
GND = Ground
seeQ
MD400075
Technology, Incorporated
5-23
g
EEPLD
26V12H
26V12H Macrocell Configuration Options
REGISTERED ACTIVE-HIGH OUTPUT,
REGISTER FEEDBACK
REGISTERED ACTIVE-LOW OUTPUT,
REGISTER FEEDBACK
*REGISTERED ACTIVE-LOW 1/0,
VO PIN FEEDBACK
*REGISTERED ACTIVE-HIGH 110,
1/0 PIN FEEDBACK
Registered Outputs
===~
__
S3- 1
S1-1
====~
-1 SO- 0
COMBINATORIAL ACTIVE-LOW 1/0,
VO PIN FEEDBACK
__
*COMBINATORIAL ACTIVE-HIGH OUTPUTS,
REGISTER FEEDBACK
Combinatorial Outputs
* THESE CONFIGURATIONS ARE UNIQUE TO THE 26V12H AND ARE NOT
AVAILABLE ON THE 22V10.
NOTES: BIT ~ IS UNIQUE TO THE 26V12H
1 - UNPROGRAMMED EEBIT
o - PROGRAMMED
MD400075
Technology. Incorporated
-1 SO-1
COMBINATORIAL ACTIVE-HIGH 110,
VO PIN FEEDBACK
*COMBINATORIAL ACTIVE-LOW OUTPUTS,
REGISTER FEEDBACK
seeQ
S3- 1
S1-1
5-24
EEPLD
26V12H
Configuration Table 1
Configuration Table 2
EE Bit
EE Bit
5(1)
3
51
50
1
0
0
1
0
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
Output Configuartion
5(1)
2
Registered Output and Feedback,
Active lOW
Registered Output and Feedback,
Active HIGH
CombinatorialI/O, Active lOW
Combinatorial 1/0, Active High
Registered 1/0, Active lOW
Registered 1/0, Active HIGH
Combinatorial Output, Registered
Feedback, Active lOW
Combinatorial Output, Registered
Feedback, Active HIGH
1
0
Clock Input
ClK/lo
ClK/1 3
Notes:
1. EE Bits $2,S3 are unique to the 26V12H and are not available
in 22V10.
1 = Unprogrammed EE Bit.
0= Programmed EE Bit.
bination of device inputs or feedback. The super macrocell
provides a bidirectional 110 pin if the 110 feedback is
selected, and may be configured as a dedicated input if the
buffer is always disabled. This is accomplished by connecting at least one input and its complement to the
enable term, forcing the AND of the complemented inputs
to be always LOW. To permanently enable the outputs, all
inputs are left disconnected from the term (unprogrammed
state "1 'J.
options provide the user flexibility to implement independent registered functions. A 2:1 multiplexer controlled by bit
S2 determines the clock input. This is an unique feature on
the 26V12H (Table 2).
Programmable Feedback
The super macrocell in the 26V12H offers additional
flexibility over the 22V1 0 when selecting feedback paths.
A 2:1 multiplexer allows the user to select the feedback
path from the flip-flop or the 110 pin, independent of
whether the output is registered or combinatorial. Thus,
registered outputs may have internal buried register feedback for higher speed (tCF spec applies), or 110 feedback
for use of the pin as a direct input (tco spec applies).
Combinatorial outputs can be selected to have 110 pin
feedback either for use of the signal in other equations or
for use as another direct input or use registered feedback.
Programmable Output Polarity
The outputs of each super macrocell can be programmed
either active HIGH or active LOW to match output signal
needs or to reduce product terms. The programmable
output polarity feature gives the user a higher degree of
flexibJ1ity when writing equations. Boolean expressions
can be written in their most compact form (true or inverted)
and the output can still have the desired polarity. It can also
save "DeMorganizing efforts". Polarity selection is controlled by reprogrammable EE bit So and affects both
registered and combinatorial outputs. Polarity selection is
automatic, based on the design specifications and pin
definitions. If pin definition and equation for a particular
output have the same polarity, the output is programmed
to be active HIGH.
The feedback multiplexer is controlled by the same EE bit
(SI) that controls selection of registered or combinatorial
outputs as on the 22V10. On the 26V12H there is an
additional unique EE control bit S3 that allows the selection
of alternative feedback paths. When EE bit S3 = 1 (unprogrammed or erased), EE bit SI selects register feedback
for registered outputs (SI = 0) and 110 pin feedback for
combinatorial outputs (SI = 1). When S3 = 0, the opposite
feedback paths are selected; 110 pin feedback for registered outputs and registered feedback for combinatorial
outputs.
Note: Preset and reset control the flip-flop, not the output
pin. The output level is determined by the output polarity
selected.
Programmable Enable and 110
Varied Product Term Distribution
All super macrocells on the 26V12H have three-state
output buffers controlled by individual product terms.
Output enable and disable can be a function of any com-
The 26V12H features a "Variable Product Term" mixture.
The product terms are distributed among the twelve super
macro cells in a varied manner, ranging from eight to
seeQ
MD400075
Technology, Incorporated
5-25
EEPLD
26V12H
Security Bit
sixteen terms per output. The varied distribution allows
optimum use of the device resources. The outputs have
8,8,10,12 or 16 product terms available for the OR gate
within each macro cell.
Designs on the 26V12H can be secured by programming
the security bit. Once programmed, this bit disables the
read verify datapath of the internal programmed pattern,
making it impossible to copy the EEPLD design pattern.
Since EEPLDs store patterns as electrical charges on
floating polysilicon gates (and not in blown fuses like other
PLD technologies) it is not possible to determine the
pattern by simply examining the die. A copy protected
EEPLD can be reused after a block erase, which clears
both the security bit and the previously programmed
pattern at the same time. If the user wants to erase a
secured 26V12H on a PLD programmer, but not program
a new pattern, an empty JEDEC file should be loaded into
the device programmer.
Programmable Preset and Reset
The 26V12 also includes a synchronous preset and an
asynchronous reset product term. These product terms
are common to all 12 super macrocells and facilitate system initialization. The Q outputs of the registers will go to
the logic High state following a Low to High transition of the
clock when the synchronous preset (SP) product term is
asserted. The two programmable clocks allow for implementation of independent initialization functions. The registers will be forced to the logic Low state independent of the
two clocks when the asynchronous reset (AR) product
term is asserted. Product term control allows preset and
reset to be functions of any combination of device inputs
and output feedback. The outputs will be High or Low depending on the polarity option chosen.
High Performance Packages
The 26V12H is offered in a 28-pin 0.3" wide slim DIP
package with center power and ground. The center-pin
package minimizes simultaneous switching noise effects
and eases decoupling layout. This pin configuration helps
to reduce the effective package inductance which contributes to the voltage noise spike caused especially during
simultaneous switching of multiple EEPLD outputs. Traditional PLD pinouts place Vee and GND pins at the opposite
ends of the package, resulting in the maximum possible
inductance through the leadframe. Placing the Vee and
GND pins at the center of the package results in the
shortest lead length from the die to the package pin and
thus offers the lowest inductance. This results in a significant reduction in the magnitude of voltage noise generated
by the high speed CMOS EEPLD 26V12H during simultaneous switching of multiple outputs and enhances system
noise performance.
Power-Up Reset
All flip-flops on the 26V12H reset automatically to logic
Low on power-up for predictable system initialization.
Depending on the polarity option chosen, outputs will be
active High or active Low. The Vee rise must be monotonic
and the reset delay time is 1 us maximum. The required
setup and clock widths are listed in the specifications on
page 15.
Register Preload
The Register Preload feature on the 26V12H allows any
arbitrary state to be loaded into the device output registers.
This facilitates functional testing even of complex state
machine designs. This feature allows direct loading of
arbitrary states that are impossible or impractical to reach
otherwise. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery. See page 14 for sequence diagram. The procedureis:
The 26V12H is also offered in 28-pin Ceramic LCC and
PLCC surface mount packages. The surface mount package options offer 100% pin utilization (unlike the 22V1 0).
Quality and Reliability
The 26V12H offers a very high level of built-in quality and
reliability due to its EE CMOS technology. Its reprogrammabIe EE cells allow SEEQ to perform complete Cell, AC,
DC and Functionality testing during manufacture. It is
important to note that the elements tested are the same
elements normally programmed by the user to implement
a logic function. There are no special test rows, columns or
'Phantom' arrays. EE CMOS technology allows actual
device signal paths to be tested prior to shipment from the
factory without the need for simulation or correlation. The
user gets the benefit of 100% field programming and functionality of SEEQ EEPLDs.
1. Raise Vee to 5V +/- 0.5 V.
2. Disable output registers by setting pin 5 to
VHH - 10.5 +/- 0.25 V.
3. Apply V'L (logic LOW)/V'H (logic High) as desired to all
register output pins. Leave combinatorial outputs floating.
4. Clock output registers with Clock 1/Clock 2. (pins 1,4)
5. Remove high Voltage from pin 5.
7. Enable output registers per programmed pattern.
8. Verify for YaL(logic LoW)/~H (logic High) at all registered output pins, according to programmed polarity.
See page 14 for further details.
seeQ
MD400075
Technology, Incorporated
5-26
EEPLD
26V12H
26V12H Logic Diagram
.
~
,J.;'
4
8
12
16
20
24
28
32
36
40
44
48
ASYNCH
RESET
1
/1()°
ClK1
1
~1
I
~
IIDARa~ 00
11
-
'fC
e-~ J'tt"
rtrJ ~1
,
9
10
-"
o
5P
27
1/0 11
50
=52
2~
11
1
53
-=
10
~1 _
I
10
-"
11
AR'"
a-oo
110
e-~"~"
o
I9
l:>-I
18
5P
=52
3
12
J rtrJ
1
-=
19
53
~LL
I
~
10
~DD
~
....
-;
29
11
5P
_52
4
ClK 211 3
0
1
30
53
I
-~DD
; ~
~
::::Y'
=
.::::;
53
I
~DD
~
=
-;
~
-
0
1
110
16
20
24
28
32
36
40
44
48
When 53 = 1 (unprogrammed) the feedback is selected by S1.
When 53 = 0 (programmed), the feedback is the opposite of that selected by 51.
MD400075
SP
52
50
1
1
12
Technology, Incorporated
5-27
11
a-oo
o
'fC
-~
"-:::c"
rhl__~1
.........l
.=;
>-I
8
~1
10
J'o.
AR'"
=*""
-
,,=50
51
53
I
~
seeQ
-
-
58
~
11
52 SP
6
15
4
~LL
10
J'o.
0
I/O a
-
=
43
AR
ClKl
24
-
,,-50
-51
0
1
5
14
8
16
11
5P
_52
74
~1
10
J'o.
---,
57
-
50
51
-=
42
50
'ls1
-=
-
53
_ 22
1/06
EEPLD
26V12H
26V12H Logic Diagram (cont'd)
0
4
8
AR
12
16
20
24
28
32
36
40
44
48
78
ClK,
SP C K2
>--l
>--
-u.
I
10
L&.11
•
lJ~L-oo
AR
'~
IT'p:
~o
"
1~
SP
91
_
52
VO S
SO
53
r
10
~l
IN L&.11
..
~1
~
~a~oo
1
CiaOl
5P
104
-S21
10
20
=$1
=
92
~
Is
]-t:
50
~ ~1
'1.53
107
-~ ~
~~"
I
10
Y>o-ll
J ~-oo
SP
110
SO
=S2
11
0
1
19
=
120
1isl
53
1Lt:- ~~
11
I~oo r10
1
.~
~
130
SP
=52Tltt
1
12
I
r~ 0IT"
]"t:
'0
=
131
10
Y>o-ll
1~f--OO
~~ °IT"'p:
139
5P
=S2]
13
I
=
140
~-"
,
148
ro"
I '2
SYNCH
149
12
16
20
24
28
32
36
40
44
48
PRESET
When 53 = 1 (unprogrammed) the feedback is selected by 51.
When 53 = 0 (programmed), the feedback is the opposite of that selected by 51 .
Technology, Incorporated
5-28
~~
VOl
50
-lL
l,...,. 10
.. 11
l~l--oo
AR
r=
°IT"
spll
_s2T-rtrJ
1
....
14
53
I
o
16
~ ~1
"
seeQ
MD400075
53
-kL ~
I
~
so
_51
-
=
S3
so
';t,~1
r- 15
1/0 5
EEPLD
26V12H
fMAX Parameters
the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAX ' External Feedback."
The parameter fMAX is the maximum clock. rate at which the
device is guaranteed to operate. Because flexibility inherent in programmable logic devices offers a choice of
clocked flip-flop designs, fMAX is specified in this case for
two types of synchronous designs.
The second type of design is a single-chip state machine
with internal feedback only. In this case, flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under
these conditions, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and
logic to the flip-flop inputs (ts + tCF). This f",AX is designated
"fMAX internal. "
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a multichip state machine. The slowest path defining the period
is the sum of the clock-to-output time and input setup time
for the external signals (ts + tcoJ. The reciprocal, fMAX' is
ClK
r-----1
lOGIC
1- - - -
I..
REGISTER
-
-1--
tco
f MAX, External Feedback; 1/(ts + t CO )
r
ClK
- - - - - -
-I
1
lOGIC
L
-----Is
,.
. . I. .
REGISTER
-1--
tCF~
f MAX Internal Feedback; 1/(ts + t CF)
seeQ
MD400075
Technology, Incorporated
.....~ (SECOND CHIP)
- - - -
--1--
ts
" -......-
5-29
ts~
EEPLD
26V12H
Absolute Maximum Ratings
Stresses above those listed underABSOLUTE MAXIMUM
RA TlNG may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to
absolute maximum ratings for extended periods may affect device reliability.
Supply voltage, Vcc ................................... -0.5 Vto 7 V
DC input voltage, V, ..................... -0.5 V to Vcc + 0.5 V
DC output voltage Vo ................... -0.5 V to Vcc + 0.5 V
DC output source/sink
current per output pin, ' 0 , •••••••••••••••••••••••••••••••••• ±35 mA
DC Vec or ground current, Icc or 'aND' •••..••••.••• ±100 mA
Input diode current, ~K
V, <0 ............................................................. -20mA
V, > Vcc ........................................................ +20mA
Output diode current, 10K
VO < 0 ............................................................ -20mA
Vo > Vcc ........................................................ +20 mA
Storage temperature ............................. -6SOC to 15f1'C
Static discharge voltage ................................... > 2001 V
Latchup current ............................................... > 100 mA
Ambient temperature under bias ......... -5SOC to +12SOC
DC Characteristics
Parameter
Symbol
Operating Ranges
Commercial (Q) Devices
Temperature (T)
Operating Free Air ............................... 0° C to + 7SO C
Supply voltage, Vcc ......................... 4.75 V to 5.25 V
Industrial (E) Devices
Temperature (T)
Operating Free Air ........................... -400C to +8SOC
Supply voltage, Vcc ........................... ..4.5 V to 5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
(over operating conditions unless otherwise specified)
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
Vee = Min.,
VIN = VIH or VIL
10H =-3.2 rnA
VOL
Output LOW Voltage
Vee = Min.,
VIN = VIH or VIL
10L = 16 rnA
VIH
(Note 1)
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs
VIL
(Note 1)
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs
Min.
Max.
Unit
2.4
V
0.4
V
2.0
V
0.8
V
J.lA
liZ
Input Leakage Current
10
Output Leakage Current
VIN = 0 to 5.5 V, Vee = Max.
VOUT = 0 to 5.5 V, Vee = Max.
-10
loz
-10
10
J.lA
Ise
Output Short-Circuit Current
Vee = Max., VOUT = 0.5 V (Note 2)
-30
-130
rnA
lee
Operating Supply Current
VIN = 0 V, Outputs Open (10 = 0 rnA)
105
rnA
Notes:
1. These are absolute values with respect to the device ground and all overshoots due to system and tester noise are included.
2. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
Capacitance
Parameter
Symbol
CIN
COUT
(Note 1)
Parameter
Description
Input capacitance
Output capacitance
Test conditions
Vee = 5.0 V, T = +25°C
VIN = 2.0 V at f = 1.0 MHz
Typ.
Unit
5
pF
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
seeQ
MD400075
Technology, Incorporated
5-30
EEPLD
26V12H
Switching Characteristics
Parameter
Symbol
(over commercial operating range (Note 1)
-20
Min.
Parameter Description
Active LOW
Active HIGH
-25
Max.
Min.
Max.
Unit
25
ns
lpo
Input or Feedback to
Combinatorial Output
ts
Setup Time for Input, Feedback,
or SP to Clock
tH
Hold Time
tco
Clock to Output
12
15
tCF
Clock to Feedback
10
13
ns
tAR
Asynchronous RESET to Registered Output
25
30
ns
tARw
Asynchronous RESET Width
20
25
ns
tARR
t SPR
Asynchronous RESET Recovery Time
20
25
ns
Synchronous PRESET Recovery Time
13
15
ns
lwL
Width of Clock
LOW
10
13
ns
HIGH
10
13
lwH
f MAX
Maximum Frequency
20
Extenal Feedback 1/(ts + tco)
Internal Feedback 1/(ts + tCF)
13
15
ns
0
0
ns
ns
ns
40
33.3
43
35
MHz
tEA
Input to Output Enable
20
25
ns
tER
Input to Output Disable
20
25
ns
Notes:
1. Commercial Test Conditions: see Switching Test Load.
2. These parameters are not 100% tested, but are calculated at initial charaterization and at any time the design is
modified where frequency may be affected.
Data Retention and Endurance
Symbol
Parameter
Value
Unit
Conditions
tOR
Pattern data retention time
>10
years
Max. storage temperature
Mil-STD 883 Test Method 1008
N
Min. reprogramming cycles
100
cycles
Operating conditions
seeQ
MD400075
Technology, Incorporated
5-31
EEPLD
26V12H
Switching Waveforms
COMBINATORIAL OUTPUT
INPUT OR
FEEDBACK
t=
--------
VT
;~~--I
~'_V_T_ __
COMBINATORIAL
OUTPUT
REGISTERED OUTPUT
~~V
JI'- T
INPUT OR
FEEDBACK
~~
J\
IH
Is
-clV
CLOCK
J
T
I
REGISTERED
OUTPUT
----------iiil~V-T--
0X
CLOCK TO FEEDBACK TO COMBINATORIAL OUTPUT
~
CLOCK
,,~~r
tCF~tp~
___
COMBINATORIAL
OUTPUT
T_ _
~
(see palh below)
ClK
lOGIC
'----
_____ 1
CLOCK WIDTH
CLOCK
seeQ
MD400075
Technology, Incorporated
V
5-32
EEPLD
26V12H
Switching Waveforms (continued)
ASYNCHRONOUS RESET
ASYNCHRONOUS
RESET
_ _ _.J
REGISTERED
OUTPUTS _ _ _~~~'lI'
'-_~I--_ _ _ _ _ _ __
CLOCK
SYNCHRONOUS PRESET
SYNCHRONOUS
PRESET
ts
tSPR
CLOCK
REGISTERED
OUTPUTS
VV\/VVVV,,,_
V
T
----------~~~
INPUT TO OUTPUT DISABLE/ENABLE
INPUT
OUTPUT
Notes:
1. V T = 1.5 V.
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 - 5 ns typical.
eeeG
MD400075
Technology, Incorporated
5-33
EEPLD
26V12H
Output Register Preload
The PALCE26V12H registered outputs are provided with
circuitry to allow loading each register synchronously with
either a HIGH or LOW. This feature will simplify testing
since any state can be loaded into the registers to control
test sequencing.
to
The pin levels and timing necessary to preform the PRELOAD function are detailed below.
to
to
to
0
~
PIN 5
VILP
1/
I
VIHP
1/
PINS 1,4
I
--
"
VHH
~
,
VILP
VILP
~
VOH
VIHP
VOH
VOL
VILP
VOL
REGISTERE 0
OUTPUT
PRELOAD
ENABLED
OUTPUTS
DISABLED
Par.
Min.
Max.
VHH 10.25 10.75
V1tp
0
0.5
V1HP 2.4
5.S
10
to
seeQ
MD400075
Unit
V
V
V
JlS
OUTPUT
FORCED
TO VIHP
ORV ILP
Level forced on
registered output
pin during
PRELOAD cycle
V1HP
V1LP
Technology, Incorporated
PRELOAD
DATA
CLOCKED
IN
Registered a output
state after cycle
High
low
5-34
OUTPUT
FORCING
VOLTAGE
REMOVED
PRELOAD
DISABLED
EEPLD
26V12H
Power-Up Reset
SEEQ 26V12H has been designed with the capability to
reset during system power-up. Following power-up, all
registers will be resetto LOW. The output state will depend
on the polarity of the output buffer. This feature provides
extra flexibility to the designer and is especially valuable in
simplifying state machine initialization. A timing diagram
and parameter table are shown below. Due to the asynchronous operation of the power-up reset, and the wide
range of ways Vee can rise to its steady state, two condi-
POWER
tions are required to ensure a valid power-up reset. These
conditions are:
1. The Vee rise must be monotonic.
2. Following reset, the clock input must not be driven from
LOW to HIGH until applicable input and feedback setup
times are met.
, 1----------------------------------- VCC
--------------4~v'l~4~-------tPR--------~.~1
CLOCK
REGISTERED ACTIVE
LOW OUTPUT
Parameter
Symbol
Parameter
Description
tpR
Power-Up
Reset Time
t8
Input or Feedback
Setup Time
tw
Clock Width
eeeG
MD400075
Technology, Incorporsted
Min.
Typ.
Max.
Unit
600
1000
ns
See Switching
Characteristics Table
5-35
EEPLD
26V12H
Switching Test Laod
Vcc
}o,
~R1
OUTPUT ::
i~
TEST POINT
;:]~CL
r
I
~
Specification
t pD,
Switch S1
CL
Rl
R2
Measured
Output Value
Closed
50 pF
300.Q
390.Q
1.5V
tEA
z-> H:open
Z -> L: closed
50 pF
300.Q
390.Q
1.5V
tEA
H ->Z: open
L -> Z: closed
5 pF
300.Q
390.Q
H -> Z: V OH -0.5 V
L -> Z: VOL + 0.5V
tco'
tCF
Key to Timing Diagrams
WAVEFORM
seeQ
MD400075
Technology, Incorporated
INPUTS
OUTPUTS
DON'T CARE:
CHANGE PERMITIED
CHANGING:
STATE UNKNOWN
NOT APPLICABLE
CENTER LINE IS
HIGH IMPEDANCE STATE
MUST BE STEADY
WILL BE STEADY
5-36
EEPLD
26V12H
PLD Development
26V12H super macroceJ/ Configuration:
Development software assists the user in implementing a
design in one or several PLDs. The software converts the
user's input into a device dependent fuse map in JEDEC
format. The software package listed below support & the
EEPLD 26V12H. For more information about PLD development software contact SEEO Technology or the software vendor directly:
Example 2 shows the listing of 26V12H from ABEL's
design example list. Notice the use of various configuration options.
Clk1, Clk2 pins: The two clock pins 1, 4 on the
26V12H allow the designer flexibility in selecting
either one or both of the clock inputs for registered
configurations. The ABEL software defaults to Clk1
from pin 1 if no clock function is defined for a registered
output.
DATA I/O Corp.
10525 Willows Road, NE, P.O. Box 97046,
Redmont, WA 9B073-9746
(BOO) 247-5700
Software offered: ABEL, PLD Test
Output super macroceJ/ control: ABEL's 'ISTYPE'
statement can be used to explicitly define the super
macrocell configuration. Or the ISTYPE statement
can be used to define the feedback point only, leaving
the polarity and register/combinatorial selection to be
determined by ABEL from the equations.
PLD Development
Data I/O ABEL version 3.1 release supports the SEEO
EEPLD26V12H. This section describes ABEL 3. 1 release
features as applied to the 26V12H. For detailed software
documentation refer to ABEL manual from Data I/O.
The following four output configurations are unique to
the 26V12H and cannot be implemented on the
22V10.
SEEO EEPLD 26V12H architecture is a superset of the
22V10. Each super macrocell on the 26V12H allows
eight output configurations. See macrocell configuration
options (Page 4). Configuration Tables 1 and 2 list the
EEbit settings for the various options. The designer can
program the 26V12H to operate like a 22V10 by using
the following configuration:
• Combinatorial output, registered feedback
with active-low or active-high outputs.
• Registered output, I/O registered feedback
with active-low or active-high.
• Combinatorial output, I/O combinatorial feedback.
• Registered output, registered feedback.
For example, to configure an output macrocell as
combinatorial with registered feedback, the following
'IS TYPE' statement can be used:
When output pin equations alone are used in design
specifications, ABEL automatically selects I/O feedback
for combinatorial output equations and registered feedback for registered equations (i. e, EEbit S3 defaults to 1).
The designer has the flexibility to configure all or some of
the 26V12H super macrocells to operate like 22V10 design.
Q15 istype 'com, feed_reg' ;
Output polarity can be controlled by entering "pos" or
"neg" in the ISTYPE statement. In which case the
statement would be:
Q15 istype 'pos,com,feed_reg';
Example 1 shows the listing of a 22V10 example from
Data /lO's ABEL design examples list converted into a
26V12H design. Notice the new pin assignments and
reset node definition.
Example 2 uses ABEL's Dot extension notation for
accessing internal nodes. ABEL will automatically
choose whether to bypass or select a register based
on the form of equation written for the output. The
ISTYPE statement is used to explicitly declare an
output configuration. Also, notice the use of registered feedback as input for output 01B.
Device nodes:
The internal nodes on the 26V12H have been assigned
specific numbers. SeeABEL user documentation for node
assignment list. The relevant nodes can also be referred
by using the Dot extension notation. See Example 2.
ABEL user documentation provides detailed description.
seeQ
MD400075
Technology, Incorporated
For a more complete description on ABEL features refer to
the ABEL user documentation.
5-37
EEPLD
26V12H
EXAMPLE 1
module _MuxAdd flag '-r3'
title '5-bit ripple adder with input multiplex
Michael Holley
FutureNet Division, Data I/O Corp.
Redmond WA
14 July 1987'
MuxAdd device 'P26VI2';
AddClk,Clr,Addl0,Subl0,is_Ace pin 1,
V4,V3,V2,V1,VO
pin 6, 5, 4,
S4,S3,S2,SI,SO
C4,C3,C2,C1
9, 8, 10,20;
3, 2;
pin 15,16,17,18,19;
pin 26,27,22,23;
Reset
node 29;
0,
X,C,L,H
.X., .C.,
Card
Score
CarryIn
CarryOut
ten
minus ten
[ V4, V3, V2, VI,
[ S4, S3, S2, Sl,
[ C4, C3, C2, C1,
[ X, C4, C3, C2,
[ 0, 1, 0, 1,
[ 1, 0, 1, 1,
" Input Multiplexer
Data
Score
];
];
1;
1;
];
];
Add 10
&
Sub10
Subl0
& ! Subl0
&
&
&
$ Score
$ CarryIn;
:= Data
CarryOut
Data
Reset
!Clr;
is_Ace
VO
SO
0
C1
0
0
# !Add10
* Addl0
equations
1;
= Card
&
Score
Card
ten
minus_ten;
* (Data # Score)
&
CarryIn;
"Async reset node for registers
==
1;
test vectors
([AddClk,Clr,Addl0,Sub10,Card] -> [Score, is_Ace] )
L
H
H
X -> [ 0
L
L ]; "Clear
-> [ 7
7
L ];
H
C , H, H
-> [ 17
L 1;
C , H, H
H , 10
H
X -> [ 0
L ] ; "Clear
L , L , H
-> [ 1
H
H
H ];
C
H
1
H
L
-> [ 11
H 1; "Add 10
C
H
-> [ 15
C , H, H
H
L ];
-> [ 23
L ];
C , H, H
H
8
H
H
-> [ 13
L 1; "Subtract 10
C
L
8
-> [ 18
H
H
C
L ];
H
5
end MuxAdd
seeQ
MD400075
Technology, Incorporated
5-38
EEPLD
26V12H
EXAMPLE 2
module P26V12
title 'Bob Hamilton
Data I/O
p26v12
Dec. 1988'
device 'P26V12';
Clk1,Clk2
12,I3,I5
Q15,Q16,Q17,Q18
pin 1,4;
pin 2,3,5;
pin 15,16,17,18;
LIBRARY 'constant';
Q15
Q16
Q17
Q18
istype
istype
istype
istype
'com, feed_reg' ;
'reg,feed-pin';
'reg, feed_reg' ;
'com, feed_pin' ;
~
~
~
~
Combinatorial with registered feedback
Registered with pin feedback
Registered with registered feedback
Combinatorial with pin feedback
equations
[Q15.0E,Q16.0E,Q17.0E,Q18.0E) = "bl1l1; " All outputs enabled
Q15.C = Clk2;
Q16.C = Clk1;
Q17.C = Clk2;
Q16 .- 12;
Q17 .- I3;
Q15
15;
Q18 = Q15.Q;
"
"
"
"
"
"
"
Clock pin 15 register with pin 4
Clock pin 16 register with pin 1
Clock pin 17 register with pin 4
Registered output, input is pin 2
Registered output, input is pin 3
Combinatorial output, input is pin 5
Combinatorial output, input is pin 15 reg. feedback
test vectors
([Clk1,Clk2,I2,I3,I5) ->
[ C,
0, 1, 1, 1 ) -> [
[ 0,
C, 0, 1, 1
->
[ C,
0, 0, 0,
->
[ 0,
->
C, 0, 0,
°
°
[Q15,Q16,Q17,Q18))
H H , L, L ) ;
H H , H, H ) ;
L , L , H, H 1;
L , L , L, L );
end P26V12
seeQ
MD400075
Technology, Incorporated
5-39
EEPLD
26V12H
PLD Programming
PROMAC
The 26V12H can be programmed on standard logic programmers. Previously programmed devices can be reprogrammed easily, using exactly the same procedure as required for blank EEPLDs. If the user wants to erase a
26V12H, but not program it to a new partain, an empty
JEDEC file should be loaded into the device programmer.
see Adams MacDonald
Stag Microsystems Inc.
1600 ~'vyati Dr., Santa Ciara CA 95054
(408) 988-1118
PLD Programmer Vendors
For more information about PLD programmers contact
SEEQ Technology or the programmer vendor directly.
Adams MacDonald
800 Airport Road, Monterey, CA 93940
(408) 373-3607
Sprint
see Adams MacDonald
DA TA 110 Corp.
10525 Willows Road NE, P.O. Box 97046
Redmont, WA 98073-9746
(800) 247-5700
PLD Programming Equipment:
Unisite V 2.5
Ordering Information
-=r]
p
a
26
v
12 H - 20
SPEED
PACKAGE TYPE
P = PLASTIC DIP
D = CERAMIC DIP
N= PLCC
L=LCC
20= 20 ns tpo
25 = 25 ns tpo
[
HALF POWER
OPERATING RANGE
Q = COMMERCIAL
E = INDUSTRIAL
M = MILITARY
105mA
L - ._ _ _ _
NUMBERS OF ARRAY INPUTS
OUTPUT TYPE
VERSATILE
S99Q
MD400075
Technology, Incorporated
5-40
NUMBER OF OUTPUTS
This page has been left blank intentionally.
5-41
This page has been left blank intentionally.
5-42
This page has been left blank intentionally.
5-43
This page has been left blank intentionally.
5-44
MILITARY
(Military and Industrial Temperature Range)
seeQ
MIL-STD-883 Class B
Compliant Product Processing
SEEQ's Management emphasis is on Quality in products and performance, converting the results of the Technology
evolution and innovations to the greatest benefit of our customers with an ever increased degree of system reliability, quality,
and functionality
SEEQ's comprehensive and interactive Quality program is designed to exceed military and customer expectations and
requirements.
SEEQ's Quality program complies with MIL·STD·883 para 1 .2.1 and military standards including MIL·Q·9859, MIL·I·45208,
MIL·M·38510 Appendix A, MIL·STD·45662 and FED·STD·209. Fundamental building blocks of the Quality program are
described below.
SEEQ's Military product flow (Chart 1) incorporates manufacturing processing, screening and controls. Controls as
specified in Military procedures or customers specifications are an integral part of the processing flows in wafer fabrication,
assembly product screening and test. (Table1)
Quality Conformance Inspection
Quality conformance testing is performed per
MIL·STD·883 para 1.2.1 and method 5005
Group A Tests
Group A -lot acceptance tests (see Table 2) are pre·
formed on each SEEQ inspection lot after completion of all
screening per MIL·STD·883 method 5004 (see Table 1).
Electrical test is per applicable SEEQ specification.
Group B - Tests (see Table 3)
Group B testing is performed by package type, lead finish
and seal date code. The Group B covers all product
manufactured using the same package type and lead
finish assembled with the same week of seal per MIL·STD·
883 method 5005 alternate Group B test.
Group C Stresses - (see Table 4)
The product stressed, as part of Group C, is identical to
that shipped or fro m the same process and product family.
The seal date code of the product covered will be the same
asor within the 51 * consecutive weeks following the Group
C seal date code. Electrical test is per applicable SEEQ
specification.
Group D Stresses - (see Table 5)
Each package type and lead finish stressed, as part of
Group D, is identical to that shipped. The seal date code
of package lead finish covered will be the same as or within
the 51 * weeks following the Group D inspection lot code.
seeQ
MD 5000021-
Technology, Incorporated
6·1
MIL-STD-883 CLass B
Compliant Product Processing
Product Processing Flow
(Chart1)
ASSEMBLY 100%
ENVIRONMENTAL
SCREENS: SEAL FINE
AND GROSS CONSTANT
ACCELERATION
TEMPERATURE CYCLE
QA,OCI
DOCUMENTATION
REVIEW - GROUP B,C
AND DAND DATA
PREPARATION
seeQ
MD 5000021-.
Technology, Incorporated
6-2
QASHIPPING
DOCUMENTATION
REVIEW AND
ACCEPTANCE
MIL-STD-883 CLass B
Compliant Product Processing
SEEQ Screens & Tests (Table 1)
Military Screen
MIL-STD Method
Internal Visual
2010, Test
Condition B
100%
Temperature Cycling
1010, Test
Condition C
100%
Constant Acceleration
2001, Y1
Orientation Only
100%
Seal
(A) Fine
(B) Gross
1014
Condition A
Condition C
100%
Visual Inspection
100%
Initial (Pre-Burn-In-Test)
Electrical
Parameters
Per Application
SEEQ Specification
100%
Burn-I n-Stress
1015, Dynamic at
125°C MIN
100%
(Post-Burn-ln~Test)
Per Applicable
SEEQ Specification
100%
Percent Defective
Allowable (PDA)
Calculation
5%
100%
Final
Electricals
Per Applicable
SEEQ Specification
100%
Electrical Parameters
Tested within 96 Hrs.
Qualification or Quality
Conformance Inspection
Test Sample Selection
External Visual
seeG
MD 500002/-
Reqmt.
100%
2009
Technology, Incorporated
6-3
100%
MIL-STD-883 CLass B
Compliant Product Processing
Group A Electrical Test per applicable SEEQ Specification (Table 2)
Subgroup
Sample
Description
1
Static Test at 25°C
116/0
2
Static test at Max Rated Operating Temperature
116/0
3
Static Test at Min Rated Operating Temperature
116/0
7
Functional Test at 25°C
116/0
8A
Functional Test at Max Rated Operating Temperature
116/0
8B
Functional Test at Min Rated Operating Temperature
116/0
9
Switching Test at 25°C
116/0
10
Switching Test at Max Rated Operating Temperature
116/0
11
Switching Test at Min Rated Operating Temperature
4
Dynamic Test
Capacitance Testing
116/0
Performed on initial qualification and design
changes that may affect capacitance
Group B Tests (Table 3)
Test
Test
Method
Subgroup 2
Resistance to Siovents
2015
Subgroup 3
Solderability
2003
Subgroup 5
Bond Strenth
Ultrasonic or Wedge
2011
Test Conditions
Quality Levell
Accept Number
4 Devices (no failures)
Soldering Temperature of
+245°C Plus or Minus 5°C
LTPD 10
=1
Test Condition C or 0
LTPD 15
=1
Subgroups 1, 4, 6, 7 and 8 have been deleted, the remaining Subgroups have not been renumbered, per MIL-STD-883,
Method 5005.
Group C Stresses (Table 4)
Test
Test
Method
Subgroup 1
Steady-State Life Test
1005
End-Point Electrical
seeQ
MD 5000021-
Test Conditions
Condition 0, Equivalent to
1000 hours at 125°C
Per SEEQ Specification
Technology, Incorporated
6-4
Quality Levell
Accept Number
LTPD 5 = 1
MIL-STD-883 CLass B
Compliant Product Processing
Group 0 Stresses (Table 5)
MIL-STD
Test
Method
Test
Test Conditions
Minimum
Quality Levell
Accept Number
Subgroup 1
Physical Dimensions
2016
Subgroup 2
Lead Integrity
Hermeticity, Fine and Gross
2004
1014
Subgroup 3
Thermal Shock
Temperature Cycling
Moisture Resistance
Hermeticity, Fine and Gross
Visual Examination
End-Point Electrical Parameters
1011
1010
1004
1014
1004
1010
-65°C Condition B, 15 Cycles Minimum
-65°C Condition C, 100 Cycles Minimum
90% Minimum Relative Humidty
2002
2007
2001
Condition B
Condition A
Y1 Orientation
1014
1014
2009
Condition A
Condition C
Per SEEQ Specification
Per SEEQ Specification
1009
Condition A
1014
1014
1009
Condition A
Condition C
Per SEEQ Specification
Subgroup 6
Internal Water Vapor
1018
5,000 ppm Maximum Wafer Content at
T = +100°C
3 Devices, 0 Failures or
5 Devices, 1 Failure
Subgroup 7
Adhesion of Lead Finish
2025
Bend 90°, Inspect at 1Ox to 20x
Magnification
LTPD 15
Subgroup 8
Lid Torque
2024
As Application to Glass-Frit Packages
5 Devices, 0 Failures
Subgroup 4
Mechanical Shock
Vibration, Variable Frequency
Constant Acceleration
Hermeticity
Fine
Gross
Visual Examination
End-Point Electrical Parameters
Subgroup 5
Salt Atmosphere
Hermeticity
Fine
Gross
Visual Examination
seeQ
MD 500002/-
Per SEEQ Outline Drawing
LTPD 15
=1
LTPD 15
=1
LTPD 15
=1
LTPD 15
=1
LTPD 15
=1
Per SEEQ Specification
Per SEEQ Specification
Technology, Incorporated
6-5
=1
6-6
seeQ
M52B131M52813H
(Military Temperature Range)
E52B131E52813H
(Extended Temperature Range)
16K Electrically Erasable PROM
October 1989
Features
Description
•
Miitary and Extended Temperature Range
-M52B13IM52B13H: -55<' to 110° C WRITE
-55° to 125<' READ
- E52B131E52B13H: -40° to 85° C
•
Input Latches
•
5V± 10%2Kx8EEPROM
SEEO's M52813 and M52813H are 2048 x 8 bit, 5 volt
electrically erasable programmable read only memories
(EEPROMs) which are specified over the military and
extended temperature range respectively. They have
input latches on all addresses, data, and control (chip and
output) enable lines. In addition, for applications requiring
fast byte write time (1 msec), an M52813H and E52813H
are also available. Data is latched and electrically written
by a TTL (or a 21 V pulse) on the Write Enable pin. Once
written, which requires under 10 ms, there is no limit to the
number of times data may be read. 80th byte and chip
erase modes are available. The erasure time in either
mode is under 10 ms, and each byte may be erased and
written a minimum of 10,000 times.
•
1 ms (52B13H) or 9 ms TTL Byte Erase!Write
•
10,000 EraselWrite Cycles per Byte Minimum
•
Chip Erase and Byte Erase
•
DiTrace®
•
Fast Read Access Time - 250 ns
•
Infinite Number of Read Cycles
•
JEDEC Approved Byte Wide Memory Pinout
•
Intel M281612816A E2 Compatible
The M52813 is compatible to the Intel M281612816A and
SEEO's M5213. For system upgrades of these older
generation EEPROMs, the M52813 is specified over the
miitary temperature range and has an access time of 250
ns. The M52813 is available in a 24 pin cerdip package.
Block Diagram
Pin Configuration
M52B131E52813
E2
MEMORY
ARRAY
WRITE/ERASE
ENABLE
LATCH ENABLE
A7
Vcc
AS
As
As
Ag
A4
WE
A3
OE
A2
A10
Al
CE
AO
1/°7
11°0
I/Os
1/°1
1/°5
1/°2
1/°4
GND
11°3
Pin Names
AO-Al0
1/0 0- 7
DiTrace is a registered trademark of SEEQ Technology, Inc.
seeQ
MD4000071C
Technology, Incorporated
6-7
ADDRESSES
CE
CHIP ENABLE
OE
WE
OUTPUT ENABLE
1/00 _7
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
WRITE ENABLE
M528131M52813H
E528131E52813H
These EEPROMs are ideal for applications that require a
non-volatile memory with in-system write and erase capability. Dynamic reconfiguration (the alteration of operating
software in real-time) is made possible by this device.
Applications will be found in military avionics systems, programmable character generators, self-calibrating instruments/machines, programmable industrial controllers,
and an assortment of other systems. Designing the
EEPROMs into eight and sixteen bit microprocessor systems is also simplified by utilizing the fast access time with
zero wait states. The addition of the latches on all data, address and control inputs reduces the overhead on the system controller by eliminating the need for the controller to
maintain these signals. This reduces IC count on the board
and improves the system performance.
circuit which allows either a TTL low or 21 V signal to be
applied to WE to execute an erase or write operation. The
52813 specifies no restriction on the rising edge of WE.
For certain applications, the user may wish to erase the
entire memory. A chip erase is performed in the same
manner as a byte erase except that Output Enable is
between 14V and 22V. AII2K bytes are erased in under
1Oms.
A characteristic of all EEPROMs is that the total number of
write and erase cycle is not unlimited. The 52813 and
52813H have been designed for applications requiring up
to 10,000 write and erase cycles per byte. The write and
erase cycling characteristic is completely byte independent. Adjacent bytes are not affected during write/erase
cycling.
Device Operation
After the device is written, data is read by applying a TTL
high to WE, enabling the chip, and enabling the outputs.
Data is available teE time after Chip Enable is applied or
tAA time from the addresses. System power may be reduced by placing the 52813 or 52813H into a standby
mode. Raising Chip Enable to a TTL high will reduce the
power consumption by over 60%.
SEEQ's52813 and 52813H have six modes of operation
(see Table 1) and except for the chip erase mode they
require only TTL inputs to operate these modes.
To write into a particular loaction of the 52813 or 528 13H,
that byte must first be erased. A memory location is erased
by presenting the 52813 or 528 13H with Chip Enable at a
TTL low while Output Enable is a TTL high, and TTL highs
(logical 1's) are being presented to all the I/O lines. These
levels are latched and the data written when write enable
is brought to a TTL low level. The erase operation requires
under 10 ms. A write operation is the same as an erase
except true data is presented to the I/O lines. The 52813H
performs the same as the 52813 except that the device
byte erase/byte write time has been enhanced to 1 ms.
DiTrace
SEEQ's family of EEPROMs incorporate a DiTrace field.
The DiTrace feature is a method for storing production flow
information to wafer level in an extra column of EEPROM
cells. As each major manufacturing operation is performed the DiTrace field is automatically updated to reflect
the results of that step. These features establish manufacturing operation traceability of the packaged device back
to the wafer level. Contact SEEQ for additional information
on these features.
The 52813 is compatible to prior generation EEPROMs
which required a high voltage signal for writing and erasing. In the 52813 there is an internal dual level detection
Table 1. Mode Selection (Vee = 5V ± 10%)
~
CE
OE
(20)
WE
(21)
1/0
(9-11, 13-17)
VIL
VIH
VIL
VIL
VIL
Don't Care
VIH
DOUT
HighZ
VIH
VIL
VIH
VIL
Chip Erase[2]
VIL
Write/Erase Inhibit
VIH
VOE
Don't Care
VIL
Don't Care
Mode
(18)
Read[1]
Standby[1]
Byte Erase[2]
Byte Write[2]
NOTES:
1. WE may be from V1H to 6V in the read and standby mode.
2. WE may be atV1L (TTL WE Mode) or from 15 to 21V (High Voltage WE mode) in the
the 52B13/52B13H.
seeQ
MD400007/C
Technology, Incorporated
6-8
VIH
DIN
=VIH
DIN
=VIH
HighZ
DIN
byte erase, byte write, or chip erase mode of
M528131M52813H
E52B131E52813H
Power Up/Down Considerations
SEEQ's "52B" E2 family has internal circuitry to minimize
false erase or write during system Vee power up or down.
This circuitry prevents writing or erasing under anyone of
the fol/owing conditions:
1. Vee is less than 3 V. (I}
2. A negative Write Enable transition has not occurred
when Vee is between 3 V and 5 V.
Under the above conditions, the outputs are in a high
impedance state.
Absolute Maximum Stress Ratings"
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature
Storage ............................................ -6SoC to +1S0°C
Under Bias ...................................... -6SO C to + 13SO C
D.C. Voltage applied to aI/Inputs or Outputs
with respect to ground ....................... +6.0 V to -O.S V
Undershoot/Overshoot pulse of less then 10 ns
(measured at SO% point) applied to aI/ inputs or
outputs with respect to ground .... (undershoot) -1.0 V
(overshoot) + 7.0 V
WE During Writing/Erasing
with Respect to Ground ..................... +22.SV to -0.3V
Recommended Operating Conditions
Vee Supply Voltage
Temperature Range:
MS2813/MS2813H (Case)
ES2813/ES2813H (Ambient)
SV±10%
WRITE -55° to +11 O°C
READ -55° to 125°C
-40° to 85°C
NOTE:
1. Characterized. Not tested.
seeQ
MD400007/C
Technology, Incorporated
6-9
M528131M52813H
E528131E52813H
Endurance and Data Retention
N
Parameter
Minimum Endurance
10,000
Units
Cycles/Byte
Condition
MIL-STD 883 Test
Method 1033
TDR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
Symbol
Value
D.C. Operating Characteristics During Read or Write/Erase
(Over the operating Vee and temperature range)
Symbol
Nom.l11
Max.
10
Unit
~A
VIN = Vee Max.
Output Leakage Current
10
~A
VOUT = Vee Max.
Write Enable Leakage
Read Mode
10
~
TTL W/E Mode
10
~A
WE = VIH
WE = VIL
High Voltage W/E Mode
1.5
rnA
High Voltage W/E Inhibit Mode
1.5
rnA
WE = 22V, CE = VIL
WE = 22V, CE = VIH
Chip Erase - TTL Mode
10
~A
WE = VIL
liN
Parameter
Input Leakage Current
10
IWE
Min.
Chip Erase - High Voltage
Mode
Test Conditions
1.5
rnA
WE =22V
lee1
Vee Standby Current
15
35
rnA
lee2
VIL
Vee Active Current
50
90
rnA
CE = VIH
CE =OE =VIL
Input Low Voltage
-0.1
0.8
V
VIH
VWE
Input High Voltage
2
Vee + 1
V
WE Read Voltage
2
Vee + 1
V
-0.1
0.8
V
14
22
V
0.45
V
10L = 2.1 rnA
V
10H = -400 ~A
V
10E = 10 ~A
WE Write/Erase Voltage
TTL Mode
High Voltage Mode
VOL
VOH
Output Low Voltage
Output High Voltage
2.4
VOE
OE Chip Erase Voltage
14
NOTES:
1. Nominal values are for T" = 25°C and Vee = 5.0 V.
seeQ
MD4000071C
Technology, Incorporated
6-10
22
M528131M52813H
E52B131E52813H
A.C. Operating Characteristics During Read
Symbol
Parameter
tM
Address Access Ti me
Chip Enable to Data Valid
teE
tOE
t
Device
Number
Extension
[11
[21
OF
Output Enable to Data Valid
Output Enable to High Impedance
Output Hold
tOH
Cli COUT[3 1 Input Capacitance
Output Capacitance
(Over the operating Vcc and temperature range)
M52B13/
M52B13H
Min. Max.
E52B13/
E52B13H
Min.
Max. Units
-250
-300
-350
250
300
250
-
350
-250
-300
-350
250
300
250
-250
-300
-350
90
90
-
-
350
90
-
CE =OE =VIL
ns
ns
ns
OE = VIL
ns
ns
ns
CE = VIL
CE = VIL
ns
CE = OE = V IL
-
-
0
0
70
0
70
70
-
-
-
-
0
80
ns
ns
ns
-250
-300
-350
All
0
110
0
Test Conditions
ns
ns
ns
All
10
10
pF
VIN = 0 V for
All
10
10
pF
C IN • V OUT = OV
for COUTo
TA = 25°C
Equivalent A. C. Test Conditions[6]
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ~ 20ns
Input Pulse Levels: 0.45V to 2.4 V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
Read Timing
HIGHZ
NOTES:
1 OE may be delayed to tj\A - tOE after the falling edge of CE without impact on tl\l\.
2. ~F is specified from OE or CEo whichever occurs first.
3. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
4. After~. hold time. from WE, the inputs CE, OE, Address and Data are latched and are "Don't Cares· until twR ' Write Recovery Time,
after the trailing edge of WE.
5. The Write RecoveryTirne, lwR' is the time after the trailing edge of WE that the latches are open and able to accept the next mode
set-up conditions. Reference Table 1 (page 2) for mode control conditions.
6. These are equivalent test conditions and actual test conditions are dependent on the tester.
eeeQ
MD4000071C
Technology, Incorporated
6-11
M528131M52813H
E528 131E528 13H
A.C. Operating Characteristics During Write/Erase
(Overthe operating Vee and temperature range)
Symbol
Parameter
ts
CE, OE or Address Setup to WE
50
ns
tos
t [4[
H
twp
Data Setup to WE
15
ns
WE to CE, OE, Address or Data Change
50
ns
Write Enable (WE) Pulse Width
Byte Modes - M52B13/E52B13
9
ms
Byte Modes - M52B13H/E52B13H
1
WE to Mode Change
WE to Start of Next Byte Write Cycle
50
tWR
(5)
Min.
Max.
Units
ns
WE to Start of Read Cycle
2
~s
52B13/52B13H High Voltage Write Specifications
Except for the functional differences noted here, the 52B13 and 52B13H operate to the same specifications,
including the TTL W/E mode.
M52B13
M52B13H
E52B13
E52B13H
Symbol
Function/Parameter
Min.
Max.
Min.
Units
Max.
twp
Write Enable Pulse Width
Byte Write/Erase
9
20
1
20
ms
9
20
9
20
ms
14
22
14
22
V
Chip Erase
VWE
WE Write/Erase Voltage
High Voltage Mode
Byte Erase or Byte Write Timing
}l
ADDRESSES
,...--
VAUD
CE
}
Oe
....
tH \
+ts
I
(WRITE)
I/O
(ERASE)
I
DON'T CARE
I
DON'T CARE
I
I
I
HIGH Z
I
.IJ- -
I
seeQ
MD4000071C
...
~
\:
V
K DON'TeARE
!'------'
\
DON'T CARE
I
I
I
~
I
I
I.--- BYTE ERASEIWRITE PERIOO -.!.- START
Notes: See AC notes
~
I
twp-
1'4V -
tH
tos;~ I-~
~
HIGH Z I VALID
I
DON'T CARE
16V I
I i\
We
110
X
II
~
Technology, Incorporated
6-12
OF
NEXT MOOE
M528131M52813H
E528131E52813H
Chip Erase Specifications
Min.
Max.
Units
Symbol
Parameter
ts
CE, OE Setup to WE
1
tOEH
OE Hold Time
1
J.1s
twp
WE Pulse Width
10
ms
tER
Erase Recovery Time
J.1s
10
J.1s
Chip Erase Timing
CE
::: _ _
V
WE
--~~---------------i~~-"";;~;;;;;';;;;;;;"--~ts-"
[1 1 _ _ _ _ _ _ _ _ _
_
14V
WE
VCC ± 1V
VIH _ _ _ _ _ _ _ _ _-'1
VOE[11- -
-
-
-
-
-
-
-r--O+----------+-_
14V
VCC
VIH _ _ _ _ _ _-'
± 1V
NOTES:
1. V WE and VOE
can be from
15V
to 21 V in the high voltage mode for chip erase on
52813.
Ordering Information
o
o
E
M
52B13
52B13
-250
H-250 /B
I1
~r-----?
T,----1-
PACKAGE
TYPE
TEMPERATURE
RANGE
PART TYPE
EEPROM BYTE WRITE TIME
ACCESS TIME
SCREENING OPTION
D - CERAMIC DIP
M - MILITARY
E - EXTENDED
2K x 8 EEPROM
(Blank) -Standard Write Time
H - Fast Write Time
250-25Ons
300 -300 ns
350-35Ons
IB - MIL 883 CLASS B
SCREENED
seeQ
MD4000071C
Technology, Incorporated
6-13
6-14
seeQ
M52B331M52B33H
E52B331E52B33H
64K Electrically Erasable PROM
October 1989
Features
•
•
•
extended temperature range respectively. They have
input latches on all addresses, data, and control (chip and
output) lines. In addition, for applications requiring fast
byte write time (1 ms), an E52B33H and M52833H are
available. Data is latched and electrically written by a TTL
pulse on the Write Enable pin. Once written, there is no
limit to the number of times data may be read. The erasure
time is under 10 ms, and each byte may be erased and
written a minimum of 10,000 times.
Full Military and Extended Temperature Range
• M52B33/M52B33H: -550 to 125° C
• E52B33/E52B33H: - 40° to 85° C
10,000 Write Cycles/Byte Over Temperature
•
•
Input Latches
5 V± 10% Vcc
1 ms (52B33H) or 9 ms (52B33)
TTL Byte Erase/Byte Write
•
Power Up/Down Protection
•
•
•
•
DiTrace®
Fast Read Access Time-250 ns
Infinite Number of Read Cycles
JEDEC Approved Byte-Wide Memory Pinout
The EIM52833 is available in a 28 pin cerdip or 32 pad
leadless chip carrier. The pin configuration is to the
JEDEC approved byte wide memory pinout for these two
types of packages. These EEPROMs are ideal for applications that require a non-volatile memory with in-system
write and erase capability. Dynamic configuration (the al-
Pin Configuration
Description
DUAL-I N-LI NE
TOP VIEW
SEEQ's M52833 and E52833 are 8192 x 8 bit, 5Velectrically erasable programmable read only memories
(EEPROMs) which are specified over the military and
LEAD LESS CHIP CARRIER
BOTTOM VIEW
Block Diagram
Pin Names
Ao-A4
ADDRESSES-COLUMN
(LOWER ORDER BITS)
As -A12
CE
ADDRESSES - ROW
OUTPUT ENABLE
WE
WRITE ENABLE
1/00 •7
DATA INPUT (WRITE OR ERASE),
DATA OUTPUT (READ)
CC
NIC
CHIP CLEAR
NO CONNECT
VOO-7
DiTrace is a registered trademark of SEEQ Technology Inc.
seeQ
MD4000091C
Technology, Incorporated
6-15
CHIP ENABLE
OE
M528331M52833H
E528331E52833H
Data is available, tCE time after Chip Enable is applied or
tAA time from the addresses. System power may be
reduced by placing the device into a standby mode.
Raising Chip Enable to a TTL high will reduce the power
consumption by over 60%.
teration of opening software in real-time) is made possible
by this device. Applications will be found in military
avionics systems, programmable character generators,
self-calibrating instrument/machines, programmable industrial controllers, and an assortment of other systems.
Designing the EEPROMs into eight and sixteen bit microprocessor system is also simplified by utilizing the fast
access time zero wait states. The addition of the latches
on all data, address and control inputs reduces the overhead on the system controller by eliminating the need for
the controller to maintain these signals. This reduces IC
count on the board and improves the system performance.
DITrace
SEEQ's famiiy 0; EEPROMs incorporate a DiTrace field.
The DiTrace feature is a method for storing production flow
information in an extra row of EEPROM cells. As each
major manufacturing operation is performed the DiTrace
field is automatically updated to reflect the results of that
step. These features establish manufacturing operation
traceability of the packaged device back to the wafer level.
Contact SEEQ for additional information on these features.
Device Operation
SEEQ E/M52B33 and E/M52B33H have six modes of
operation (see Table 1) and require only TTL inputs to
operate these modes.
Chip Clear
Certain applications may require all bytes to be erased
simultaneously. See A.C. Operating Characteristics for
TTL chip erase timing specifications.
To write into a particular location, that byte must first be
erased. A memory location is erased by having valid addresses, Chip Enable at a TTL low, Output Enable at TTL
high, and TTL highs (logical 1's) presented to all the VO
lines. Write Enable is then brought to a TTL low level to
latch all the inputs. The erase operation requires under 10
ms. A write operation is the same as an erase except true
data is presented to the I/O lines. The 52B33H performs
the same as the ElM52B33 except that thebyte erase/byte
write time has been enhanced to 1 ms.
Power Up/Down Considerations
SEEQ's "52B" P family has internal circuitry to minimize false erase or write during system Vccpower up or
down. This circuitry prevents writing or erasing under
anyone of the following conditions:
1. Vcc is less than 3 VPJ
A characteristic of all EEPROMs is that the total number of
2. A negative Write Enable transition has not occurred
when Vcc is between 3 V and 5 V.
write and erase cycles is not unlimited. The ElM52B33 is
designed for applications requiring up to 10,000 write and
erase cycles per byte over the temperature range. The
write and erase cycling characteristics are completely byte
independent. Adjacent bytes are not affected during write/
erase cycling.
Writing will also be prevented if CE or OE are in a
logical state other than that specified for a byte write in
the Mode Selection table.
After the device is written, data is read by applying a TTL
high to WE, enabling the chip, and enabling the outputs.
Mode Selection
(Table 1)
CE
CO
OE
WE
1/0
(20)
(1)
(22)
(27)
{11-13,15-19}
VIH
Don't Care
VIL
Don't Care
VIH
Don't Care
DOUT
HighZ
Chip Clear
VIL
VIH
VIL
VIL
VIL
VIH
VIH
VIL
VIH
VIH
VIH
VIL
VIL
VIL
= VIH
DIN
VIL or VIH
Write/Erase Inhibit
VIH
Don't Care
Don't Care
Don't Care
HighZ
~tion
J.Pin)
Mode
Read
Standby
Byte Erase
Byte Write
NOTE:
1. Characterized. Not tested.
seeQ
MD400009/C
Technology, Incorporated
6-16
DIN
M528331M52833H
E528331E52833H
Absolute Maximum Stress Ratings"
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature
Storage ............................................ -6SoC to +1S0°C
Under Bias ........................................ -6SOC to +13SOC
D.C. Voltage applied to aI/Inputs or Outputs
with respect to ground ....................... +6.0 V to -O.S V
Undershoot/Overshoot pulse of less then 10 ns
(measured at SO% point) applied to aI/ inputs or
outputs with respect to ground .... (undershoot) -1.0 V
(overshoot) + 7.0 V
Recommended Operating Conditions
5 V± 10%
Vee Supply Voltage
Temperature Range:
M52B33/M52B33H (Case)
-55°C to + 125°C
E52B33/E52B33H (Ambient)
-40 0 C to +85 0 C
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
Condition
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
D.C. Operating Characteristics During Read or Erase/Write
(Over the operating Vee and temperature range)
Symbol
Parameter
Max.
Unit
liN
Input Leakage Current
10
V IN
10
Output Leakage Current
10
IlA
IlA
IWE
Write Enable Leakage
Read Mode
W/E Mode
10
10
IlA
IlA
WE
WE
Min.
Nom.
leel
Vee Standby Current
15
50
rnA
lec2
V 1L
V IH
Vee Active Current
50
120
rnA
VOL
V OH
Output Low Voltage
seeQ
= Vee Max.
= Vee Max.
VOUT
= VIH
= V1L
CE = V IH
CE =OE = VIL
Input Low Voltage
-0.1
0.8
V
Input High Voltage
2
Vee + 1
0.45
V
10L = 2.1 rnA
V
IOH
Output High Voltage
2.4
NOTE: See next page for notes.
MD4000091C
Test Conditions
Technology, Incorporated
6-17
V
=-400 IlA
M52B331M52B33H
E52B331E52B33H
A.C. Operating Characteristics During Read
(Over the operating Vcc and temperature range)
Device
M52B33
Number
M52B33H
Extension Min. Max.
E52B33
E52B33H
Min. Max. Units
Symbol
Parameter
tAA
Address Access Time
-250
-300
250
300
250
300
ns
..- ns
tCE
Chip Enable to Data Valid
-250
-300
250
300
250
300
ns
ns
OE = VIL
OE
(2)
Output Enable to Data Valid
-250
-300
90
90
90
90
ns
ns
CE = VIL
t
(3)
Output Enable to High Impedance
-250
-300
0
0
70
70
ns
ns
CE = VIL
0
ns
CE = OE = VIL
10
pF
VIN =0 V for
CIN • VOUT = 0 V
for COUT'
TA = 25°C
t
OF
tOH
Output Hold
All
Cit!
C
(4)
OUT
Input/Output Capacitance
All
70
70
0
0
0
10
Test Conditions
CE =OE =VIL
Read Cycle Timing
ADDRESSES
VALID
ADDRESSES
CE
OE
OUTPUT
-------+-------HH-++_<
HIGHZ
~---- tACC'----~
NOTES:
1. Nominal values are for TA = 25° C and Vce = 5.0V.
2. OE may be delayed to tAA - tOE after the falling edge of CE without impact on tAA'
3. tDFis specified from 6E or CE, whichever occurs first.
4. This parameter is measured only for the initia.!.9u~ication and after process or design changes which may affect capacitance.
5. After tH, hold time, from WE, the inputs CE, OE, CC, Address and Data are latched and are "Don't Cares· until tWR ' Write
Recovery Time, after the trailing edge of WE.
6. The Write Recovery TIme, tWR ' is the time after the trailing edge of WE that the latches are open and able to accept the next
mode set-up conditions. Reference Table 1 (page 2) for mode control conditions.
7. These are equivalent test conditions and actual test conditions are dependent on the tester.
seeQ
A1D4000091C
Technology, Incorporated
6-18
M528331M52833H
E528331E52833H
Equivalent A.C. Test Conditions[7]
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times::5; 20ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V
A.C. Operating Characteristics During Write/Erase
(Over the operating Vee and temperature range)
Symbol
Parameter
Min.
ts
CE, OE or Address Setup to WE
50
ns
tos
t [5)
Data Setup to WE
15
ns
WE to CE, OE, Address or Data Change
50
ns
Write Enable, (WE) Pulse Width
Byte Modes - M52B33/E52B33
9
ms
1
ms
50
ns
1
Jls
H
twp
Byte Modes tWA
[6)
M52B33H
WE to Mode Change
WE to Next Byte Write/Erase Cycle
WE to Start of a Read Cycle
Max.
Units
Byte Erase or Byte Write Cycle Timing
I
I
~:
I
ADDRESSES
VALID
~\
CE
K
DON'T CARE
V
DON'TeARE
I
I
I
I
1
+Y
ts
r"
DON'T CARE
1
1
twp
1
1
I
WE
I
\
,.,
1
va
HIGHZ
I
r-
(WRITE MODE)
"
--~tH
tDS""
l-
VALID
K
Y
f-
tWR
1
~
1
DON'TeARE
1
1
va
HIGHZ
(ERASE MODE)
I
I
""l
DON'TeARE
1
1......1 - - - - BYTE ERASElWRITE PERIOD - - - ' - - START OF NEXT MODE
NOTES
See previous page for notes.
seeQ
MD4000091C
Technology, Incorporated
6-19
M52B331M52833H
E528331E52833H
A.C. Operating Characteristics During Chip Erase.
(Over the operating Vee and temperature range)
Symbol
Parameter
Min.
ts
t (4J
CC, CE, OE Setup to WE
50
WE to CE, OE, CC change
50
ns
twp
Write Enable (WE) Pulse Width
Chip Erase -M52B33/M52B33H
Chip Erase - E52B33H/E52B33H
iO
ms
(5
fwR )
WE to Mode change
WE to Start of Next Byte Write Cycle
50
ns
H
Max.
Units
ns
1
WE to Start of Read Cycle
Jls
TTL Chip Erase Timing
I
I
~
VALID
k'
I
OON'TCARE
I
I
I
I
k'
~
CE
I~
I
I
I
I
OE
I
OON'TCARE
tH
~
1\
OON'TCARE
twp
I
+
J
I
ts ~
I
WE
~---- CHIP ERASE PERIOD
~I
----I
..
NOTE: Address, Data are don't care during Chip Clear.
Ordering Information
o
M
I1
52B33
H - 250
~.-----?
/B
T
TL.o..--- - - - - - ,
PACKAGE
TYPE
OPERATING
TEMPERATURE
RANGE
PART TYPE
EEPROM BYTE WRITE TIME
ACCESS TIME
D - CERAMIC DIP
L-LEADLESS CHIP
CARRIER
E - -40" C to +85"C
M • -55· C to +125· C
8K x 8 EEPROM
(BLANK) • STANDARD WRITE TIME
H • FAST WRITE TIME
250 • 250 ns
300 • 300 ns
seeQ
MD4000091C
Technology, Incorporated
6-20
l
SCREENING
OPTION
IB-MIL883
CLASS B
SCREENED
seeQ
EIM2816A
Timer E2
16K Electrically Erasable PROMs
October 1989
Features
Description
•
High Endurance Write Cycles
• 2816A: 10,000 Cycles/Byte Minimum
•
On-Chip Timer
• Automatic Erase and Write Time Out
•
AI/Inputs Latched by Write or Chip Enable
•
•
5 V± 10% Power Supply
Power Up/Down Protection Circuitry
•
250 ns max. Active Time
SEEQ's EIM2816A are 5V only, 2K x 8 electrically erasable programmable read only memories (EEPROMs).
EEPROMs are ideal for applications which require nonvolatility and in-system data modification. The endurance,
the minimum number of times that a byte may be written,
is 10 thousand for the EIM2816A. The EIM2816A's high
endurance was accomplished using SEEQ's proprietary
oxyntride EEPROM process and its innovative Q Cell™
design. The EIM2816A is ideal for systems that require
frequent updates.
•
Low Power Operation
• 110 mA max. Active Current
• 40 mA max. Standby Current
•
JEDEC Approved Byte-Wide Pinout
•
Military and Extended Temperature Range
• - 55° C to + 125° C: M2816A (Military)
• - 40° C to +85° C: E2816A (Extended)
There is an internal timer that automatically times out the
write time. A separate erase cycle is not required and the
minimum write enable (WE) pulse width needs to be only
150 ns. The on-chip timer, along with the inputs being
latched by a write or chip enable signal edge, frees the
microcomputer system for other tasks during the write
Pin Configuration
Block Diagram
COLUMN
ADDRESS
LATCHES
ROW
ADDRESS
LATCHES
COLUMN
ADDRESS
DECODE
ROW
ADDRESS
DECODE
E2
MEMORY
ARRAY
A7
Vee
A6
AS
A5
Ag
A4
WE
A3
OE
A2
A10
Al
CE
AO
1/° 7
1/0 0
I/OS
1/°5
1/°1
1/0
2
1/°4
GND
1/0 3
Pin Names
VO O-7
o Cell is a trademark of SEEO Technology, Inc.
seeQ
MD4000171C
Technology, Incorporated
6-21
Ao-Al0
CE
OE
WE
1/°0 _7
ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
WRITE ENABLE
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
EIM2816A
Mode Selection
time. The EIM2816's write time is 10 ms. Once a byte is
written, it can be read in 250 ns. The inputs are TTL for
both the byte write and read mode.
(Table 1)
Mode
CE
OE
WE
1/0
Read
V IL
VIL
V IH
Device Operation
Standby
V IH
X
X
DOUT
High Z
There are five operational modes (see Table 1) and,
except for the chip erase mode [IJ, only TTL inputs are
required. To write into a particular location, a TTL low is
applied to write enable (WE) pin of a selected (CE low)
device. This, combined with output enable (OE) being
high, initiates a write cycle. During a byte write cycle,
addresses are latched on the last falling edge of CE or WE
and data is latched on the first rising edge of CE or WE. An
internal timer times out the required byte write time. An
automatic byte erase is performed internally in the byte
write mode.
Byte Write
V IL
V IH
V IL
,Wnte
I
~nhibit
DIN
,,",
High ZluOUT
X
X
High ZlDoUT
X: any TIL level
Power Up/Down Considerations
The EIM2816A has internal circuitry to minimize a false
write during system Vee power up or down. This circuitry
prevents writing under anyone of the following conditions.
1. Vee is less than 3VJ2J
2. A negative Write Enable (WE) transition has not
occured when Vee is between 3 V and 5 V.
Absolute Maximum Stress Ratings'"
Temperature
Storage ............................................ -65°C to +150°C
Under Bias ....................................... -65° C to + 135° C
D. C. Voltage applied to all Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot/Overshoot pulse of less then 10 ns
(measured at 50% point) applied to all inputs or
outputs with respect to ground .... (undershoot) -1.0 V
(overshoot) + 7.0 V
Writing will also be prevented if CE or OE are in a logical
state other than that specified for a byte write in the Mode
Selection table.
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings· may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Recommended Operating Conditions
I Temperature Range
I Vee Supply Voltage
M2816A
E2816A
(Case) -55°C to 125°C
(Ambient) -40°C to 85°C
5V± 10%
5V± 10%
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
NOTES:
1. Chip Erase is an optional mode.
2. Characterized. Not tested.
seeQ
MD4000171C
Technology, Incorporated
6-22
Condition
EIM2816A
DC Operating Characteristics
(Over the operating Vcc and temperature range)
Limits
Symbol
Parameter
Max.
Units
Icc
Active Vcc Current
125
mA
CE = OE =VIL ; All 1/0 Open;
Other Inputs = 5.5 V
IS8
Standby Vcc Current
40
mA
CE = V IH , OE = V IL ; All 1/0's
Open; Other Inputs = 5.5 V
III
ILo
V IL
Input Leakage Current
10
Output Leakage Current
10
IlA
IlA
Input Low Voltage
-0.1
0.8
V
V IH
Input High Voltage
2.0
6
V
VOL
VOH
Output Low Voltage
0.4
V
IOL = 2.1 rnA
V
IOH = -400 IlA
Min.
2.4
Output High Voltage
Test Condition
VIN = 5.5 V
VOUT = 5.5 V
AC Characteristics
Read Operation (Over the operating Vcc and temperature range)
Limits
E/M2816A-250
Symbol
E/M2816A-350
Parameter
Min.
t RC
Read Cycle Time
250
tCE
Chip Enable Access Time
250
350
tAA
Address Access Time
250
350
ns
tOE
Output Enable Access Time
90
100
ns
tLZ
CE to Output in Low Z
tHZ
CE to Output in High Z
tOLZ
OE to Output in Low Z
tOHZ
OE to Output in High Z
50
tpu
CE to Power-up Time
tpD
[1]
CE to Power Down Time
TA
Units
ns
ns
ns
100
50
100
[1]
Max.
10
100
Output Hold from Addr Change
Capacitance [2J
Min.
350
10
[1]
tOH
Max.
ns
ns
100
ns
20
20
ns
0
0
ns
50
=25°C, f = 1 MHz
50
ns
Equivalent A.C. Test Conditions
Symbol
Parameter
C IN
COUT
Input Capacitance
6 pF
VIN = 0 V
Data (1/0) Capacitance
10 pF
V I/O = 0 V
Max
Conditions
E.S.D. Characteristics
Symbol
Parameter
Value
Test Conditions
V ZAP [1]
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V
NOTES:
1. Characterized. Not tested.
2. This parameter measured only for the initial qualification and after process or design changes which may affect capacitance.
seeQ
MD4000171C
Technology, Incorporated
6-23
EIM2816A
Read Cycle Timing
~~ooJ{
IRC
-I
1M
\
CE
~
X
I
~IM_
If-
~ICE-
.-~IOE--
-
\r
OE
I
~
lou
DATA OUT
HIGHZ
~ILZ
.tOH .......
..
Dr
DATA VALID
______
1
_IOHZ_
---tHZ--
K x:
DATA VALID
'-
I
Vcc
SUPPLY
CURRENT
I-Ipu
Iss
I
Icc
_IPO ___
AC Characteristics
Write Operation (Over the operating Vee and temperature range)
Limits
E/M2816A-250
Min.
Max.
E/M2816A-2350
Min.
Symbol
Parameter
twc
Write Cycle Time
t AS
Address Set Up Time
10
10
tAH
Address Hold Time
tcs
Write Set Up Time
50
0
0
150
70
0
0
150
10
10
tCH
Write Hold Time
tcw
CE to End of Write Input
tOES
OE Set Up Time
tOEH
OE Hold Time
twp
[1J
tOL
tov
[2J
10
WE Write Pulse Width
10
10
150
Data Latch Time
50
Data Set Up Time
tOH
Data Hold Time
Units
10
ms
ns
ns
ns
ns
ns
ns
ns
150
Il s
1
Ils
50
1
Data Valid Time
tos
150
Max.
ns
50
50
ns
0
0
ns
NOTES:
1. WE is noise protected. Less than a 20 ns write pulse will not activate a write cycle. Max. recommended twp is 150 ~.
2. Data must be valid within 1 ~ maximum after the initiation of a write cycle.
'---
seeG
MD4000171C
Technology, Incorporated
6-24
EIM2816A
TTL Byte Write Cycle
CE CONTROLLED WRITE CYCLE
WE CONTROLLED WRITE CYCLE
ADDRESS
ADDRESS
CE
CE
OE
OE
WE
WE
DATA IN
DATA IN
Ordering Information
PACKAGE
TYPE
TEMPERATURE
RANGE
D-CERAMIC DIP
M - -550 C to +1250 C
PART TYPE
ACCESS TIME
SCREENING OPTION
2Kx8EEPROM
250 = 250 ns
350 = 350 ns
IB - MIL 883 CLASS B
SCREENED
(Military)
E - - 40 C to +85 C
0
0
(Extended)
seeQ
MD4000171C
Technology, Incorporated
6-25
6-26
seeQ
ElM2817A
Timer E2
16K Electrically Erasable PROMs
October 1989
Features
Description
•
Military and Temperature Range
• -sse C to +125' C: M2817A (Military)
• -400 C to +SSO C: E2817A (Extended)
•
•
Read/Busy Pin
High Endurance, 10,000 Byte Write Cycles
Minimum
SEEQ's M2817A is a 5 V only, 2Kx 8 electrically erasable
programmable read only memory (EEPROM). It is packaged in a 28 pin package and has a readylbusy pin. This
EEPROM is ideal for applications which require non-volatility and in-system data modification. The endurance, the
minimum number of times which a byte may be written, is
10 thousand cycles.
•
On-Chip Timer
• Automatic Byte Erase Before Byte Write
•
•
5 V ± 10% Power Supply
Power Up/Down Protection Circuitry
•
250 ns max. Access Time
•
Low Power Operation
• 110 mA Active Current
• 40 mA Standby Current
•
JEDEC Approved Byte-Wide Pinout
The M2817A has an internal timer that automatically times
out the write time. The on-chip timer, along with the input
latches, frees the microcomputer system for other tasks
during the write time. The 2817A's write cycle time is 10
ms over the military temperature range. An automatic byte
erase is performed before a byte operation is started.
Once a byte has been written, the readylbusy pin signals
the microprocessor that it is available for another write or
Pin Configuration
Block Diagram
DUAL-IN-LiNE
TOP VIEW
LEADLESS CHIP CARRIER
BOTTOM VIEW
r~
!i I~ '"8 !i! ~ !i .;-
E2
MEMORY
ARRAY
AS •10
Pin Names
Ao-A.
ADDRESSES - COLUMN
(LOWER ORDER BITS)
As-Alo
CE
ADDRESSES - ROW
CHIP ENABLE
OE
VO O-7
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/°0 _7
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
ROY/BUSY DEVICE READY/BUSY
NC
seeQ
MD400015/B
Technology, Incorporated
6-27
NO CONNECT
EIM2817A
Power Up/Down Considerations
a read cycle. All inputs are TTL for both the byte write and
read mode. Data retention is specified for 10 years.
The M2817A has internal circuitry to minimize a false write
during system Vee power up or down. This circuitry
prevents writing under anyone of the following conditions.
1. Vee is less than 3 V,f2!
_
2. A negative Write Enable (WE) transition has not
occured with Vee is between 3 V and 5 V.
Device Operation
There are five operational modes (see Table 1) and,
except for the chip erase mode lf/, only TTL inputs are
required. To write into a particular location, a TTL low is
applied to the write enable (WE) pin of a selected (CE low)
device. This, combined with output enable (OE) being
high, initiates a write cycle. During a byte write cycle,
addresses are latched on either the falling edge of CE or
WE, whichever one occurred last. Data is latched on the
risingedgeofCEorWE, whichever one occurred first. The
byte is automatically erased before data is written. While
the write operation is in progress, the ROY/BUSY output
is at a TTL/ow. An internal timer times out the required byte
write time and at the end of this time, the device signals the
ROY/BUSY pin to a TTL high. The ROY/BUSY pin is an
open drain output and a typical3K n pull-up resistor to Vee
is required. The pull-up resistor value is dependent on the
number of OR-tied 2817A RDY/BUSYpins.
Mode Selection
CE
OE
WE
110
ROY/BUSY
Read
V IL
V IL
V IH
Standby
V IH
X
X
DOUT
High Z
HighZ
Byte Write V IL
V IH
V IL
DIN
X
X
V IL
X
High ZlDoUT
High ZlDoUT
X
Absolute Maximum Stress Ratings*
Temperature
Storage ............................................ -65° C to + 150° C
Under Bias ...................................... -65° C to + 135° C
D.C. Voltage applied to all Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot/Overshoot pulse of less then 10 ns
(measured at 50% point) applied to all inputs or
outputs with respect to ground .... (undershoot) -1.0 V
(overshoot) + 7.0 V
(Table 1)
Mode/Pin
Write
Inhibit
Writing will also be prevented ifCE orOE are in TTL logical
states other than specified for a byte write in the Mode
Selection table.
VIH
High Z
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
VOL
High Z
High Z
X: any TTL level
Recommended Operating Conditions
E2817A-300
E2817A-250
M2817A-300
M2817A-250
IVee Power Supply
ITemperature Range
5V± 10%
5V± 10%
(Case) -55°C to + 125 °C
(Ambient) -40°C to +85°C
Endurance and Data Retention
Condition
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
NOTES:
1. Chip Erase is an optional mode.
2. Characterized. Not tested.
seeQ
MD400015/B
Technology, Incorporated
6-28
EIM2817A
D.C. Operating Characteristics
(Over the operating Vee and temperature range)
Limits
Parameter
Max.
Units
Icc
Active Vee Current
(Includes Write Operation)
110
rnA
CE = OE =V1L; All 1/0 Open;
Other Inputs = 5.5 V
Isa
Standby Vee Current
40
rnA
CE = V IH, OE = V IL ; All 1/0
Open; Other Inputs = 5.5 V
'l
Input Leakage Current
10
10
IlA
IlA
VIN = 5.5 V
Output Leakage Current
ILo
VIL
Min.
Test Condition
Symbol
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.0
Output Low Voltage
Vee +1
0.4
V
VOL
VOH
Output High Voltage
2.4
V OUT = 5.5 V
rnA
V
IOL = 2.1
V
IOH = -400 Il A
A.C. Characteristics
Read Operation (Over the operating Vec and temperature range)
limits
E/M2817A-2S0
ElM2817A-300
Symbol
Parameter
Min.
t Ae
Read Cycle Time
250
tCE
Chip Enable Access Time
250
300
ns
tAA
Address Access Time
250
300
ns
tOE
Output Enable Access Time
90
100
ns
CE =OE =VIL
OE = V IL
CE = OE = V IL
CE = V IL
tOF
Output Enable High
to Output Not being Driven
0
60
ns
CE = V IL
tOH
Output Hold from Address
Change, Chip Enable, or
Output Enable whichever
occurs first
0
ns
CE orOE =VIL
Read Cycle Timing
Max.
Min.
Max.
300
60
0
ns
0
~------tRC------~
ADDRESSES
ADDRESSES VAUD
tOH
OU~UT--------~------~~~
seeQ
MD40001SIB
Technology, Incorporated
6-29
Units
VAUDOUTPUT
Test Conditions
EIM2817A
Capacitance {1l
Symbol
CIN
A.C. Test Conditions
TA = 25°C, f = 1 MHz
Parameter
Max
Input Capacitance
6 pF
Data (1/0) Capacitance
4"
,
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fa/I Times: < 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Levei:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V
Conditions
VIN
=0 V
-"
I
'V1/0-VV
E.S.D. Characteristics
Symbol
Parameter
Value
Test Conditions
V ZAP [21
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
AC Characteristics
Write Operation (Over the operating Vce and temperature range)
Limits
E/M2817 A-250
E/M2817A-300
Symbol
Parameter
t AS
Address to Write Set Up Time
10
10
ns
tcs
t wp[31
CE to Write Set Up Time
10
10
ns
WE Write Pulse Width
150
150
ns
tAH
Address Hold Time
50
50
ns
tos
Data Set Up Time
50
50
ns
tOH
Data Hold Time
0
0
ns
Min.
Max.
Min.
Max.
Units
tCH
CE Hold Time
0
0
ns
tOEs
OE Set Up Time
10
10
ns
tOEH
OE Hold Time
10
10
ns
tOL
Data Latch Time
50
50
[41
Data Valid Time
ns
1
1
Ils
tos
Time to Device Busy
200
200
ns
lwR
Write Recovery Time
Before Read Cycle
10
10
Il S
twc
Byte Write Cycle Time
10
10
ms
tov
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not tested.
3. WE is noise protected. Less than a 20 ns write pulse will not activate a write cycle. Max. recommended t lP is 150 ~.
4. Data must be valid within 1 ~ maximum after the initiation of a write cycle.
seeQ
MD4000151B
Technology, Incorporated
6-30
EIM2817A
Write Cycle Timing
IOES
OE
AO-AI2
CE
WE
V°0--7
ROY/BUSY
1""'1.-------
lWA
WRITE CYCLE
- - - - - - - - - - - . <...r4---READ CYCLE ~
Ordering Information
o
M
~
I
2817A
-250
/8
T'-----,T
PACKAGE
TYPE
TEMPERATURE
RANGE
PART TYPE
ACCESS TIME
SCREENING OPTION
D - CERAMIC DIP
L-LCC
M - --£5 0 C 10 + 125 0 C
(Military)
E - -40 0 C 10 +85 0 C
(Extended)
2Kx 8 EEPROM
250-250 ns
300-300 ns
IB - MIL 883 CLASS B
seeQ
MD4000151B
Technology, Incorporated
6-31
Screened
6-32
seeQ
M28641M2864H
E28641E2864H
Timer E2
64K Electrically Erasable ROMs
October 1989
Features
•
64KEEPROM
• Military Temperature M2864
• Extended Temperature E2864
•
Read/Busy Pin
•
High Endurance Write Cycles
• 10,000 Cycles/Byte Minimum
•
On-Chip Timer
• Automatic Byte Erase Before Byte Write
• 2 ms Byte Write (M2864H)
•
5 V:t 10% Power Supply
•
Power Up/Down Protection Circuitry
•
250 ns max. Access Time
volatility and in-system data modification. The endurance,
the number of times which a byte may be written, is a
minimum of 10 thousand cycles.
The EEPROM has an internal timer that automatically
times out the write time. The on-chip timer, along with the
input latches, frees the microcomputer system for other
tasks during the write time. The standard byte write cycle
time is 10 ms. For sytems requiring faster byte write, an
M2864H is specified at 2 ms. An automatic byte erase is
performed before a byte operation is started. Once a byte
has been written, the readylbusy pin signals the microprocessor that it is available for another write or a read cycle.
All inputs are TTL for both the byte write and read mode_
Data retention is specified for ten years.
Pin Configuration
Description
DUAL-IN-LiNE
TOP VIEW
SEEQ's M2864 is a 5 Vonly, 8K x 8 NMOS electrically
erasable programmable read only memory (EEPROM). It
is packaged in a 28 pin package and has a readylbusy pin.
This EEPROM is ideal for applications which require non-
LEADLESS CHIP CARRIER
BOTTOM VIEW
Vee
WE
NC
!t I~
o
>0
!t
II lJ:
~
NC
Ae
Block Diagram
A8
AS
A9
A4
A"
A3
OE
A2
A,O
A,
CE
AO
V07
VO e
VO s
V0
2
VO.
GND
V03
~
'5....
~f? ~
~ g f
Pin Names
Ao-A4
ADDRESSES - COLUMN
(LOWER ORDER BITS)
As-A'2
CE
ADDRESSES - ROW
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00-7
DATA INPUT (WRITE OR ERASE)
DATA OUTPUT (READ)
ROY/BUSY DEVICE READY/BUSY
VO O-7
NC
seeQ
MD4000031B
CHIP ENABLE
Technology, Incorporated
6-33
NO CONNECT
M28641M2864H
E28641E2864H
up resistor to Vee is required. The pull-up resistor value is
dependent on the number of OR-tied RDY/BUSYpins. If
RDY/BUSY is not used it can be left unconnected.
These two timer EEPROMs are ideal for systems with
limited board area. For systems where cost is important,
SEEQ has a latch only "52BH family at 16K and 64K bit
densities. All H52BH family inputs, except for write enable,
are latched by the falling edge of the write enable signal.
Chip Erase
Certain applications may require all bytes to be erased
simultaneously. This feature is optional and the timing
specifications are available from SEEQ.
Device Operation
There are five operational modes (see Table 1) and,
except for the chip erase mode, only TTL inputs are
required. To write into a particular location, a 150 ns TTL
pulse is applied to the write enable (WE) pin of a selected
(CE low) device. This, combined with output enable (OE)
being high, initiates a 10 ms write cycle. During a byte write
cycle, addresses are latched on either the falling edge of
CE or WE, whichever one occurred last. Data is latched on
the rising edge of CE or WE, whichever one occurred first.
The byte is automatically erased before data is written.
While the write operation is in progress, the RDY/BUSY
output is at a TTL low. An internal timer times out the
required byte write time and at the end of this time, the
device signals the RDY/BUSYpin to a TTL high. The RDY/
BUSY pin is an open drain output and a typical3K n pull-
Mode Selection
CE" at
1. Vee is less than 3 V.t'J
2. A negative Write Enable (WE) transition has not
occured when Vee is between 3 V and 5 V.
Writing will also be prevented if CE or OE are in TTL logical
states other than that specified for a byte write in the Mode
Selection table.
Absolute Maximum Stress Ratings"
Temperature
Storage ............................................ -65°C to + 150°C
Under Bias ....................................... -6SO C to + 13SO C
(22)
I/O
ROY/BUSY
WE
(27) (11-13.15-19)
(1)"
Read
V IL
VIL
V IH
DOUT
HighZ
Standby
V IH
X
X
High Z
High Z
Byte Write V IL
Write
X
Inhibit
X
VIH
V IL
DIN
VOL
V 1L
X
High ZlDoUT
High ZlDoUT
HighZ
HighZ
X
The M2864 has internal circuitry to minimize a false write
during system Vee power up or down. This circuitry
prevents writing under anyone of the following conditions.
(Table 1)
(20)
Mode/Pin
Power Up/Down Considerations
V IH
D.C. Voltage applied to aI/Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot/Overshoot pulse of less then 10 ns
(measured at 50% point) applied to aI/ inputs or
outputs with respect to ground .... (undershoot) -1.0 V
(overshoot) + 7.0 V
'COMMENT: Stresses above those listed under "Absolute
n
Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
*Pln 1 has an open drain output and requires an external 3K n
resistor to Vcc. The resistor value is depent the number of ORtied RDY /BUSY pins.
Recommended Operating Conditions
E2864
E2864H
M2864
M2864H
IVee Supply Voltage
ITemperature Range
5V±10%
5V± 10%
(Case) -55°C to +125°C
(Ambient) -40°C to +85°C
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
NOTE: 1. Characterized. Not tested.
seeG
MD400003/B
Technology. Incorporated
6-34
Condition
M28641M2864H
E28641E2864H
D.C. Operating Characteristics
(Over the operating Vcc and temperature range)
Limits
Test Condition
Symbol
Parameter
Max.
Units
Icc
Active Vcc Current
(Includes Write Operation)
120
mA
CE = OE =VIL : All I/O Open;
Other Inputs = Vcc Max.
ISB
Standby Vee Current
50
mA
CE = V IH , OE = VIL ; All I/O Open;
Other Inputs = Vee Max.
III
ILO
Input Leakage Current
10
JlA
VIN = Vee Max.
Output Leakage Current
10
JlA
Voor = Vec Max.
V IL
Input Low Voltage
-0.1
0.8
V
V IH
VOL
V OH
Input High Voltage
2.0
Output Low Voltage
Vcc +1
0.4
V
IOL = 2.1 mA
V
IOH = -400 ~A
Min.
Output High Voltage
V
2.4
A.C. Characteristics
Read Operation (Over the operating Vcc and temperature range)
Limits
E/M2864H-250
E/M2864-250
Symbol
Parameter
Min.
250
E/M2864H-300
E/M2864-300
Max.
Min.
Max.
M2864-350
Min.
Max.
Units
Test Conditions
t RC
Read Cycle Time
ns
CE = OE = V IL
tCE
Chip Enable Access Time
250
300
350
ns
OE = V IL
tAA
Address Access Ti me
250
300
350
ns
CE = OE = V IL
tOE
Output Enable Access Time
90
100
100
ns
tOF
Output Enable High
to Output Not being Driven
0
80
ns
CE = V IL
CE = V IL
tOH
Output Hold from Address
Change, Chip Enable, or
Output Enable whichever
occurs first
0
ns
CE or OE =VIL
Read Cycle Timing
300
60
0
350
60
0
0
0
....- - - - - - t R c - - - - - - . . - t
ADDRESSES
ADDRESSES VALID
tOH
OUTPUT -----+-----+-t~_(
VAUDOUTPUT
NOTES:
1. OE may be delayed to tM - tOE after the falling edge of CE without impact on tM .
2.lo F is specified from OE or CE, whichever occurs first.
seeQ
MD4000031B
Technology, Incorporated
6-35
M28641M2864H
E28641E2864H
Capacitance
TA(1)
=25°C, f = 1 MHz
A.C. Test Conditions
Parameter
Max
Conditions
C IN
Input Capacitance
6 pF
VIN = 0 V
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
C ~U,
.•
Data li/O Capacitance
10 of
V. =OV
Timing Measurement Reference Level:
Symbol
Inputs 1 V and 2 V
Outputs O.B V and 2 V
E.S.D. Characteristics[41
Symbol
Parameter
Value
Test Conditions
V ZAP
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
AC Characteristics
Write Operation (Over the operating Vcc and temperature range)
Limits
ElM2864H-250
ElM2864-250
ElM2864H-300
ElM2864-300
Min.
Min.
Max.
Max.
E/M2864H-350
E/M2864-350
Min.
Max.
Units
10
ms
-
ms
Symbol
Parameter
twc
Write Cycle TimelByte
Standard Family Only
t AS
Address to WE Set Up Time
10
10
10
ns
tcs
CE to Write Set Up Time
0
0
0
ns
twp[2]
WE Write Pulse Width
150
150
150
ns
tAH
Address Hold Time
50
50
70
ns
tos
Data Set Up Time
50
50
50
ns
tOH
Data Hold Time
20
20
20
ns
tCH
CE Hold Time
0
0
0
ns
tOES
OE Set Up Time
10
10
10
ns
tOEH
OE Hold Time
10
10
10
ns
tOL
t [3]
OV
Data Latch Time
50
50
50
10
10
"H" Family Only
2
2
ns
1
1
1
tOB
Time to Device Busy
200
200
200
Ils
ns
tWR
Write Recovery Time
Before Read Cycle
10
10
10
IlS
Data Valid Time
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. WE is noise protected. Less than a 20 ns write pulse will not activate a write cycle.
3. Data must be valid within 1 IJS maximum after the initiation of a write cycle.
4. Characterized. Not tested.
seeQ
MD4000031B
Technology, Incorporated
6-36
M28641M2864H
E28641E2864H
Write Cycle Timing
tOES
OE
CE
WE
VO O- 7
ROY/BUSY
Ordering Information
D
E
2864
H· 250
IB
? I 1T ~------,
D
PACKAGE
O-CERAMIC DIP
L-LCC
seeQ
MD4000031B
M
2864
H· 250
IB
TEMPERATURE
RANGE
PART TYPE
EEPROM BYTE
WRITE TIME
ACCESS TIME
SCREENING OPTION
M --550 Cto + 1250 C
(MILITARY)
E - -400 C to +850 C
(EXTENDED)
8Kx 8 EEPROM
(BLANK) - STANDARD WRITE TIME
H - FAST WRITE TIME
250- 250 ns
/B - MIL 883 CLASS B
SCREENED
Technology, Incorporated
6-37
300- 300 ns
350-350 ns
6-38
seeQ
EIM28C64
Timer E2
64K Electrically Erasable PROM
October 1989
Description
Features
•
•
•
•
•
•
•
•
•
•
•
SEEO's ElM28C64 is a CMOS 5Vonly, 8K x 8 Electrically
Erasable Programmable Read Only Memory (EEPROM). It
is manufactured using SEEO's advanced 1.25 micron
CMOS Process and is available in both a 28 pin Cerdip
package as well as a Leadless Chip Carrier (LCC). The E/
M28C64 is ideal for applications which require low power
consumption, non-volatility and in system reprogrammability. The endurance, the number of times a byte can be
written, is specified at 10,000 cycles per byte and, is
typically 1,000,000 cycles per byte. The extraordinary high
endurance was accomplished using SEEO's proprietary
oxynitride EEPROM process and it's innovative 0 CelfTM
design. System reliability, in all applications, is higher
because of the low failure rate of the 0 Cell.
Military and Extended Temperature Range
• -55 D C to +125 D C Operation (Military)
• -40 D C to +85 D C Operation (Extended)
CMOS Technology
Low Power
• 60 mA Active
·250 IIA Standby
Page Write Mode
• 64 Byte Page
• 160 us Average Byte Write Time
Byte Write Mode
Write Cycle Completion Indication
• DATA Polling
On-Chip Timer
• Automatic Erase Before Write
Pin Configuation
High Endurance
• 10,000 Cycles/Byte Minimum
• 10 Year Data Retention
DUAL·IN·L1NE
TOP VIEW
Power Up/Down Protection Circuitry
Vee
WE
NC
200 ns Maximum Access Time
A'2
A7
JEDEC Approved Byte Wide Pinout
NC
A6
Block Diagram
LEAD LESS CHIP CARRIER
BonOMVIEW
A8
As
A9
A4
All
A3
OE
"2
A,o
A,
CE
"'0
1107
vo o
1106
110,
110 5
1/°2
V04
GNO
1103
Pin Names
a Cell is a trademark of SEEa Technology, Inc.
seeQ
MD400001/D
1/° _
07
Technology, Incorporated
6-39
Ao-As
ADDRESSES-COLUMN
As-A'2
CE
ADDRESSES-ROW
CHIP ENABLE
OE
OUTPUT ENABLE
WE
1/00_7
WRITE ENABLE
NC
NO CONNECTION
DATA INPUT (WRITE)/DATA
OUTPUT (READ)
EIM28C64
latched on the rising edge of WE or CE whichever occurred
first. An automatic erase is performed before data is
written.
The EIM28C64 has an internal timer which automatically
times out the write time. The on-chip timer, along with input
latches free the microprocessor for other tasks while the
part is busy writing. The EIM28C64's write cycle time is 10
ms. An automatic erase is performed before a write. The
DATA polling feature of the ElM28C64 can be used to determine the end of a write cycle. Once the write cycle has
been completed, data can be read in a maximum of200 ns.
Data retention is specified for 10 years.
Write Cycle Control Pins
For system design simplification, the ElM28C64 is designed such that either the CE or WE pin can be used to
initiate a write cycle. The device uses the latest high-to-Iow
transition of either CE or WE signal to latch addresses and
the earliest low-to-high transition to latch the data. Address and OE setup and hold are with respect to the later
of CE or WE; data setup and hold is with respect to the
earlier of WE or CEo
Device Operation
Operational Modes
There are five operational modes (see Table 1) and, except
for the chip erase mode, only TTL inputs are required. A
Write can only be initiated under the conditions shown.
Any other conditions for CE, OE, and WE will inhibit writing
and the 110 lines will either be in a high impedance state or
have data, depending on the state of aforementioned three
To simplify the following discussion, the WE pin is used as
the write cycle control pin throughout the rest of this data
sheet. Timing diagrams of both write cycles are included
in the AC Characteristics.
input lines.
Write Mode
One to 64 bytes of data can be randomly loaded into the
page. The part latches row addresses, A6-A 12, during the
first byte write. These addresses are latched on the falling
edge of the WE signal and are ignored after that until the
end of the write cycle. This will eliminate any false write
into another page if different row addresses are applied
and the page boundary is crossed.
Mode Selection
1/0
Mode
CE
OE
WE
Read
VIL
VIL
VIH
Dour
Standby
VIH
X
X
High Z
Write
VIL
VIH
VIL
DIN
Write
Inhibit
X
X
VIL
X
X
VIH
High ZlDour
High ZlDour
VIL
VH
VIL
X
Chip Erase
The column addresses, AO-A5, which are used to select
different locations of the page, are latched every time a
new write initiated. These addresses and the OE state
(high) are latched on the falling edge of WE signal. For
proper write initiation and latching, the WE pin has to stay
low for a minimum of twp ns. Data is latched on the rising
edge of WE, allowing easy microprocessor interface.
X: Any TIL level
VH : High Voltage
Reads
A read is accomplished by presenting the address of the
Upon a low to high WE transition, the EIM28C64 latches
data and starts the internal page load timer, The timer is
reset on the falling edge of the WE signal if another write
is initiated before the timer has timed out. The timer stays
reset while the WE pin is kept low. If no additional write
cycles have been initiated within tSLC after the last WE low
to high transition, the part terminates the page load cycle
and starts the internal write. During this time which takes
a maximum of 10 ms, the device ignores any additional
write attempts. The part can be read to determine the end
of write cycle (DATA polling).
desired byte to the address inputs. Once the address is
stable, CE is brought to a TTL low in order to enable the
chip. The WE pin must be at a TTL high during the entire
read cycle. The output drivers are made active by bringing
Output Enable (OE) to a TTL low. During read, the
address, CE ,OE, and 110 latches are transparent.
Writes
To write into a particular location, the address must be
valid and a TTL low applied to the Write Enable (WE) pin
of a selected (CE low) device. This combined with Output
Enable (OE) being high, initiates a write cycle. During write
cycle, all inputs except data are latched on the falling edge
of WE" or CE, whichever occurred last. Write enable needs
to be at a TTL low only for the specified twp time. Data is
seeQ
MD4000011D
Extended Page Load
In order to take advantage of the page mode's faster
average byte write time, data must be loaded at the page
load cycle time (tSLC). Since some applications may not
be able to sustain transfers at this minimum rate, the
Technology, Incorporated
6-40
EIM28C64
EIM28C64 permits an extended page load cycle. To do
this, the write cycle must be "stretched" by maintaining WE
low, assuming a write enable-controlled cycle, and leaving
all other control inputs (CE, OE) in the proper page load
cycle state. Since the page load timer is reset on the falling
edge of WE, keeping this signal low will not start the page
load timer. When WE returns high, the input data is latched
and the page load cycle timer begins. In CE controlled write
the same is true, with CE holding the timer reset instead of
WE.
DATA Polling
The ElM28C64 has a maximum write cycle time of 10 ms.
Typically though, a write will be completed in less than the
specified maximum cycle time. DATA polling is a method
of minimizing write times by determining the actual endpoint of a write cycle. If a read is performed to any address
while the 28C64 is still writing, the device will present the
ones-complement of the last byte written. When the
ElM28C64 has completed its write cycle, a read from the
last address written will result in valid data. Thus, software
can simply read from the part until the last data byte written
is read correctly.
A DATA polling read can occur immediately after a byte is
loaded into a page, prior to the initation of the internal write
seeQ
MD4000011D
Technology, Incorporated
6-41
cycle. DATA polling attempted during the middle of a page
load cycle will present a ones complement of the most
recent data byte loaded into the page. Timing for a DATA
polling read is the same as a normal read.
Chip Erase
Certain applications may require all bytes to be erased simultaneously. This feature, which requires high voltage,
is optional and timing specifications are available from
SEEQ.
Power Up/Down Considerations
There is internal circuitry to minimize a false write during
power up or power down. This circuitry prevents writing
under anyone of the following conditions.
1. Vee is less than VWlV.
2. A high to low Write Enable (WE) transition has not
occurred when the Vee supply;s between VWI V and
Vee with CE low and OE high.
Writing will also be inhibited when WE, CE, or OE are in
TTLlogical states other than that specified for a write in the
Mode Selection table.
EIM28C64
Absolute Maximum Stress Ratings"
Overshoot pulse of less than 10 ns (measured at
50% point )applied to all inputs or outputs
with respect to ground ..................................... + 7.0 V
Temperature
Storage ............................................ -65°C to +150°C
Under Bias ...................................... -65°C to + 135 ° C
"COMMENT: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functiona! operation of the device at these or any other conditions
beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
D.C. Voltage applied to all Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground ...................................... -1.0 V
Recommended Operating Conditions
I Temperature Range
I Vcc Power Supply
M28C64
E28C64
(Case) -55°C to +125°C
(Ambient) -40°C to +85°C
± 10%
5V
5V
± 10%
Endurance and Data Retention
Condition
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
DC Characteristics
(Over operating temperature and Vee range, unless otherwise specified)
Limits
Min.
Test Condition
Symbol
Parameter
Max.
Units
Ice
Active Vcc Current
60
mA
CE = OE =V,L ; All 1/0 Open;
Other Inputs = Vee Max.;
Max read or write cycle time
1581
Standby Vcc Current
(TIL Inputs)
2
mA
CE = V 'H ' OE = V ,L ; All 1/0 Open;
Other Inputs = ANY TIL LEVEL
1582
Standby Vee Current
(CMOS Inputs)
250
JlA
CE = Vee -0.3
Other Inputs = V ,L to V ,H
All 1/0 Open
1(2)
Input Leakage Current
IOL
Output Leakage Current
V ,L
Input Low Voltage
-0.3
V ,H
Input High Voltage
2.0
VOL
Output Low Voltage
V OH
Output High Voltage
2.4
VWI (1)
Write Inhibit Voltage
3.8
V
IL
1
JlA
Y'N = Vee Max.
10
JlA
Vour = Vee Max.
0.8
V
6
V
0.45
V
10l.=2.1 mA
V
100 = -400 IJA
NOTES:
1. Characterized. Not tested.
2. Inputs only. Does not include I/O.
SeeQ
MD4000011D
Technology, Incorporated
6-42
EIM28C64
AC Characteristics
Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
Symbol Parameter
E1M2BC64-200
E1M2BC64-250
E1M2BC64-300
E1M2BC64-350
Min.
Min.
Min.
Min.
Max.
10
Max.
10
Max.
10
Max.
Units
10
ms
twc
Write Cycle Time
t AS
Address Set-up Time
10
10
10
10
ns
tAH
Address Hold Time (see note 1)
150
150
150
150
ns
tcs
Write Set·up Time
0
0
0
0
ns
tCH
Write Hold Time
0
ns
tcw
tOES
10
10
150
10
ns
OE High Set-up Time
150
10
0
150
0
CE Pulse Width (note 2)
0
150
tOEH
OE High Hold Time
WE Pulse Width (note 2)
tos
Data Set-up Time
10
150
50
10
150
50
10
150
50
ns
twp
10
150
50
tOH
Data Hold Time
0
0
0
0
t BlC
Byte Load Timer Cycle
(Page Mode Only) (see note 3)
t lP
Last Byte Loaded
to DATA Polling
0.2
200
0.2
200
200
200
0.2
200
200
0.2
ns
ns
ns
ns
200
us
200
ns
Write Timing
WE CONTROLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
NOTES:
1 Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. talC min. is the minimum time before the next byte can be loaded. talC max. is the minimum time the byte load timer
waits before initiating internal write cycle.
seeG
MD4000011D
Technology, Incorporated
6-43
EIM28C64
Capacitance [1} TA = 25°C, f = 1 MHz
A.C. Test Conditions
Symbol
Parameter
Max
Conditions
CIN
COUT
Input Capacitance
6 pF
VIN = OV
Data (I/O) Capacitance
12 pF
VIIO = OV
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V
E.S.D. Characteristics
Symbol
VZAP
(2)
Parameter
Value
Test Conditions
E.S.D. Tolerance
>2000 V
MIL-STDSS3
Test Method 3015
A C Characteristics
Read Operation (Over operating temperature and vee Range, unless otherwise specified)
Limits
E1M28C64-200 E1M28C64-250 EIM28C64-300 E1M28C64-350
Parameter
Test
Min. Max. Min. Max. Min. Max. Min. Max. Units Conditions
t RC
Read Cycle Time
200
ns
CE = OE =VIL
teE
Chip Enable Access Time
200
250
300
350
ns
tAA
Address Access Time
200
250
300
350
ns
tOE
Output Enable Access Time
90
ns
OE = VIL
CE = OE = VIL
CE = VIL
tOF
Output or Chip Enable High to
output not being driven
0
SO
ns
CE = VIL
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
ns
CE = OE = VIL
Symbol
300
250
SO
60
90
90
0
60
0
350
0
SO
0
0
0
Read/Data Polling Cycle Time
lAC
ADDRESSES
X
X
ADDRESSES AN
NEXT ADDRESS
f+-----
1M -
V
CE
~ICEBE
-K
~
DATA
1M
"'"
IOF
~
IOH
/ / / DATA VALID
HIGHZ
/
)<~
DATA VALID
"""
~'t'/~
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacnance.
2. Characterized. Not tested.
-
seeQ
MD4000011D
Technology, Incorporated
6-44
EIM28C64
Page Write Timing
~----------------------PAGELOAD----------------~~--
WE
DATA
HIGHZ
>-11-1----«
Ordering Information
D
L
PACKAGE
TYPE
D = CERAMIC DIP
L=LCC
seeQ
MD4000011D
TEMPERATURE
RANGE
M
28C64 -250
IB
DEVICE
ACCESS TIME
III ~ l
M = _55° - + 125°C
(MILITARY)
E = -400 - +85°C
(EXTENDED)
8Kx8 EEPROM
Technology, Incorporated
6-45
200= 200
250= 250
300= 300
350= 350
ns
ns
ns
ns
MIL 883
CLASSB
SCREENED
6-46
seeQ
EIM28C65
Timer E2
64K Electrically Erasable PROM
October 1989
Features
Description
•
SEEQ's E/M28C65 is a CMOS 5Vonly, 8K x 8 Electrically
Erasable Programmable Read Only Memory (EEPROM).
It is manufactured using SEEQ's advanced 1.25 micron
CMOS Process and is available in a 28 pin Cerdip package
a Plastic Leadless Chip Carrier (PLCC) as well as a
Leadless Chip Carrier (LCC). The EIM28C65 is ideal for
applications which require low power consumption, nonvolatility and in system reprogrammability. The endurance, the number of times a byte can be written, is
specified at 10,000 cycles per byte and is typically
1,000,000 cycles per byte. The extraordinary high endurance was accomplished using SEEQ's proprietary
oxyntride EEPROM process and it's innovative Q CeWM
design. System reliability, in all applications, is higher
Military and Extended Temperature Range
• _55 0 C to + 1250 C Operation (Military)
• -40 0 C to + 850 C Operation (Extended)
•
CMOS Technology
•
LowPower
• 60 mA Active
• 250 IlA Standby
•
Page Write Mode
• 64 Byte Page
• 160 us Average Byte Write Time
•
•
Byte Write Mode
Write Cycle Completion Indication
• DATA Polling
• ROY/BUSY Pin
•
On-Chip Timer
• Automatic Erase Before Write
•
•
•
•
Pin Configuration
DUAL-IN-LiNE
TOP VIEW
High Endurance
• 10,000 Cycles/Byte Minimum
• 10 Year Data Retention
Power Up/Down Protection Circuitry
250 ns Maximum Access Time
JEDEC Approved Byte Wide Pinout
LEADLESS CHIP CARRIER
BOTTOM VIEW
Vee
I ~~
>8 ~ ~ c~
WE
A12
NC
A8
Block Diagram
AS
A9
A"
All
"a
Oe
A 10
CE
E2
MEMORY
ARRAY
"0
V07
VOl
VO s
VO s
V0
VO"
2
VOa
RDYIBUSY
~-------t----,
Pin Names
Ao-As
A6-A12
seeQ
MD4000261C
Technology, Incorporated
6-47
ADDRESSES ROW
CE
CHIP ENABLE
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00 _7
DATA INPUT (WRITE)
DATA OUTPUT (READ)
ROY/BUSY
DEVICE READY/BUSY
NC
NO CONNECTION
VO O_7
Q Cell is a trademark of SEEQ Technology, Inc.
ADDRESSES - COLUMN
EIM28C65
because of the low failure rate of the Q Cell.
cycle, all inputs except data are latched on the falling edge
of WE or OE, whichever occu"ed last. Write enable needs
to be at a TTL low only for the specified twe time. Data is
latched on the rising edge of WE or OE whichever
occu"ed first. An automatic erase is performed before
data is written.
The ElM28C65 has an internal timer which automatically
times out the write time. The on-chip timer, along with input
latches free the microprocessor for other tasks while the
part is busy writing. The ElM28C65's write cycle time is 10
ms. An automatic erase is performed before a write. The
DATA polling feature of the EIM28C65 can be used to
determine the end of a write cycle. Once the write has
been completed, data can be read in a maximum of200 ns.
Data retention is specified for 10 years.
Write Cycle Control Pins
For system design simplification, the ElM28C65 is designed such that either the OE or WE pin can be used to
initiate a write cycle. The device uses the latest high-to-Iow
transition of either OE or WE signal to latch addresses and
the earliest low-to-high transition to latch the data. Address and OE setup and hold are with respect to the later
of CE or WE; data setup and hold is respect to the earlier
ofWEorOE.
Device Operation
Operational Modes
There are five operational modes (see Table 1) and, except
for the chip erase mode, only TTL inputs are required. A
write can only be initiated under the conditions shown. Any
other conditions for OE, OE, and WE will inhibit writing and
the 110 lines will either be in a high impedance state or have
data, depending on the state ofaforementioned three input
Mode Selection
Mode
CE OE
Vil
Standby
VIH
Write
Vil
Write
X
Inhibit
X
Chip Erase Vil
Read
To simplify the following discussion, the WE pin is used as
the write cycle control pin throughout the rest of this data
sheet. Timing diagrams of both write cycles are included
in the AC Characteristics.
(Table 1)
WE
Vil VIH
X X
VIH Vil
Vil X
X VIH
VH Vil
I/O
RDY/BUS'(l1)
Dour
HIGHZ
HighZ
HIGHZ
DIN
VOL
High ZlDoUT
High ZlDoUT
HIGHZ
HIGHZ
X
HIGHZ
Write Mode
One to 64 bytes of data can be randomly loaded into the
page. The part latches row addresses, A6-A 12, during the
first byte write. These addresses are latched on the falling
edge of the WE signal and are ignored after that until the
end of the write cycle. This will eliminate any false write
into another page if different row addresses are applied
and the page boundary is crossed.
X: Any TTL level
~Sligh
The column addresses, AO-A5, which are used to select
different locations of the page, are latched every time a
new write initiated. These addresses and the OE state
(high) are latched on the falling edge of WE signal. For
proper write initiation and latching, the WE pin has to stay
low for a minimum of twp ns. Data is latched on the rising
edge of WE, allowing easy microprocessor interface.
Voltage
Reads
A read is accomplished by presenting the address of the
desired byte to the address inputs. Once the address is
stable, OE is brought to a TTL low in order to enable the
chip. The WE pin must be at a TTL high during the entire
read cycle. The output drivers are made active by bringing
Output Enable (OE) to a TTL low. During read, the
address, OE, OE, and I/O latches are transparent.
Upon a low to high WE' transition, the ElM28C65 latches
data and starts the internal page load timer. The timer is
reset on the falling edge of the WE signal if another write
is initiated before the timer has timed out. The timer stays
reset while the WE pin is kept low. If no additional write
cycles have been initiated within tSLC after the last WE low
to high transition, the part terminates the page load cycle
and starts the internal write. During this time which takes
a maximum of 10 ms, the device ignores any additional
write attempts. The part can be read to determine the end
of write cycle (DATA polling).
Writes
To write into a particular location, the address must be
valid and a TTL low applied to the Write Enable (WE) pin
of a selected (OE low) device. This combined with Output
Enable (OE) being high, initiates a write cycle. During write
NOTES:
1. ROYIBUSY Pin 1(Pin 2 on PLCC) has an open drain output and requires an extemal3K resistor to Vcc' The value of the resistor
is dependent on the number of OR-tied ROY/BUSY pins.
seeQ
MD4000261C
Technology, Incorporated
6-48
EIM28C65
Extended Page Load
typical 3 K pull-up resister to Vee is required. The pull-up
value is dependent on the number of OR-tied ROYIBUSY
pins. If ROYIBUSYis not used, it can be left unconnected.
In order to take advantage of the page mode's faster
average byte write time, data must be loaded at the page
load cycle time (tBLd' Since some applications may not be
able to sustain transfers at this minimum rate, the
EIM28C65 permits an extended page load cycle. To do
this, the write cycle must be "stretched" by maintaining WE
low, assuming a write enable-controlled cycle, and leaving
all other control inputs (CE, OE) in the proper page load
cycle sta~Since the page load timer is reset on the falling
edge of WE, keeping this signal low will not start the page
load timer. When WE returns high, the input data is latched
and the page load cycle timer begins. In CE controlled write
the same is true, with CE holding the timer reset instead of
WE.
Chip Erase
Certain applications may require all bytes to be erased
simultaneously. This feature, which requires high voltage, is optional and timing specifications are available
fromSEEQ.
Power Up/Down Considerations
There is internal circuitry to minimize a false write during
power up or power down. This circuitry prevents writing
under anyone of the following conditions.
1. Vee is less than VWI V.
2. A high to low Write Enable (WE) transition has not
occurred when the Vee supply is between VwlVand
Vee with CE low and OE high.
DATA Polling
The EIM28C65 has a maximum write cycle time of 10 ms.
Typically though, a write will be completed in less than the
specified maximum cycle time. DATA polling is a method
of minimizing write times by determining the actual endpoint of a write cycle. If a read is performed to any address
while the EIM28C65 is still writing, the device will present
the ones-complement of the last byte written. When the
EIM28C65 has completed its write cycle, a read from the
last address written will result in valid data. Thus, software
can simply read from the part until the last data byte written
is read correctly.
Writing will also be inhibited when WE, GE, or OE are in
TTL logical states other than that specified for a write in the
Mode Selection table.
Absolute Maximum Stress Ratings*
Temperature
Storage ........................................... -65° C to +150°C
Under Bias ..................................... -65° C to + 13SO C
O.C. Voltage applied to all Inputs or Outputs with
respect to ground ............................. +6.0 V to -0.5 V
Undershoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with repect to ground ....................................... -1.0 V
Overshoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground ..................................... +7.0 V
A DATA polling read can occur immediately after a byte is
loaded into a page, prior to the initiation of the internal write
cycle. DATA polling attempted during the middle of a page
load cycle will present a ones-complement of the most
recent data byte loaded into the page. Timing for a DATA
polling read is the same as a normal read.
READY/BUSY Pin
EIM28C65 provides write cycle status on this pin. ROYI
BUSYoutput goes to a TTL low immediately after the falling
edge of WE. ROYIBUSY will remain low during the byte
load or page load cycle and continues to remain at a TTL
low while the write cycle is in progress. An internal timer
times out the required write cycle time and at the end of this
time, the device signals ROYIBUSYpin to a TTL high. This
pin can be polled for write cycle status or used to initiate a
rising edge triggered interrupt indicating write cycle completion. The ROYIBUSYpin is an open drain output and a
seeQ
M04000261C
"COMMENT: Stresses beyond those listed under '~bso
lute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only ancJ functional operation of the device at these or any other conditions
beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Technology, Incorporated
6-49
EIM28C65
Recommended Operating Conditions
I Temperature Range
M28C65
E28C65
(Case) -55°C to +125°C
(Ambient) -40°C to +85°C
5 V ± 10%
5 V± 10%
I Vee Power Supply
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
DC Characteristics
Condition
(Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol
Parameter
Min.
Max.
Units
Icc
Active Vee Current
60
rnA
CE = OE =V IL : All 110 Open;
Other Inputs = Vee Max;
Max read or write cycle time
Test Condition
IS81
Standby Vee Current
(TIL Inputs)
2
rnA
CE = V IH, OE = V IL; All 1/0 Open;
Other Inputs = ANY TIL LEVEL
IS82
Standby Vee Current
(CMOS Inputs)
250
JlA
CE = Vee -0.3
Other Inputs = V IL to V 1H
All 1/0 Open
I (2]
IL
Input Leakage Current
1
JlA
VIN = Vee Max.
IOL
V IL
Output Leakage Current
10
JlA
Your = Vee Max.
0.8
V
6
V
0.45
Input Low Voltage
-0.3
V IH
Input High Voltage
2.0
VOL
VOH
Output Low Voltage
V
IOL = 2.1 rnA
Output High Voltage
2.4
V
IOH = -400 JlA
VWI (1)
Write Inhibit Voltage
3.8
V
NOTES:
1. Characterized. Not tested.
2. Inputs only. Does not include 1/0.
seeQ
AfD4000261C
Technology, Incorporated
6-50
EIM28C65
Capacitance [1} TA =25°C, f = 1 MHz
Symbol
Parameter
Max
Conditions
A.C. Test Conditions
CIN
Input Capacitance
6 pF
VIN = OV
COUT
Data (1/0) Capacitance
12 pF
V I/O = OV
Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45V to 2.4V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V
E.S.D. Characteristics
Symbol
Parameter
Value
Test Conditions
VZAP (2)
E.S.D. Tolerance
>2000 V
MIL-STD 883
Test Method 3015
AC Characteristics
Read Operation (Over operating temperature and Vcc range, unless otherwise specified)
Limits
Test
EIM28C65·200 E1M28C65-250 E1M28C65·300 E1M28C65·350
Symbol
Max. Units Conditions
Parameter
Min. Max.
Min. Max. Min. Max. Min.
t RC
Read Cycle Time
200
250
ns
CE =OE =VIL
tCE
Chip Enable Access Time
200
250
300
350
ns
OE = VIL
tAA
Address Access Time
200
250
300
350
ns
CE = OE = VIL
tOE
Output Enable Access Time
80
90
90
90
ns
CE = VIL
tOF
Output or Chip Enable High to
output not being driven
0
80
ns
CE = VIL
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, which ever occurs first
0
ns
CE = OE = VIL
60
0
0
350
300
60
0
0
80
0
0
Read/Data Polling Cycle Time
14-----tRC-----I~
ADDRESSES
ADDRESSES AN
CE
OE
DATA_--:.H.:,:.;IG:::,H...,Z=--+-_ _ _ _ _ _+<
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capac~ance.
2. Characterized. Not tested.
seeQ
MD4000261C
Technology, Incorporated
6-51
EIM28C65
AC Characteristics
Read Operation (Over the operating Vcc and temperature range)
Limits
ElM28C65-200
Symbol Parameter
Min.
ElM28C65-250
Max.
Min.
10
Max.
ElM28C65-300
Min.
10
Max.
ElM28C65-350
Min.
10
Max.
Units
10
ms
twc
t AS
Write Cycle Time
Address Set-up Time
10
10
10
10
tAH
Address Hold Time (see note 1)
150
150
150
150
ns
tcs
Write Set-up Time
0
0
0
0
ns
tCH
Write Hold Time
tcw
CE Pulse Width (note 2)
ns
0
0
0
0
ns
150
150
150
150
ns
tOEs
OE High Set-up Time
10
10
10
10
ns
tOEH
OE High Hold Time
10
10
10
10
ns
lwp
WE Pulse Width (note 2)
150
150
150
150
ns
tos
Data Set-up Time
50
50
50
50
ns
tOH
t BLC
Data Hold Time
0
0
0
0
ns
t LP
Last Byte Loaded
to DATA Polling
200
200
tOB
Time to Device Busy
100
100
Byte Load Timer Cycle
(Page Mode Only) (note 3)
0.2
200
0.2
200
0.2
200
0.2
200
us
200
200
ns
100
100
ns
Write Timing
WE CONTOLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
DATA
DATA
RDvliiiS'i"----;......"t.
RDYIBUSY ---';"';':""-,1.
NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. talC min. is the minimum time before the next byte can be loaded. talC max. is the minimum time the byte load timer waits before initiating
the intemal write cycle.
seeQ
MD4000261C
Technology, Incorporated
6-52
EIM28C65
Page Write Timing
Ordering Information
D
L
PACKAGE
TYPE
D = CERAMIC DIP
L=LCC
P= PLCC
seeQ
MD4000261C
M
~
TEMPERATURE
RANGE
M = -55°C to + 125°C
(MILITARY)
E = -40°C to +85°C
(EXTENDED)
s:
28C65 -250
DEVICE
8Kx8EEPROM
Technology, Incorporated
6-53
18
T
ACCESS TIME
200 = 200 ns
250 = 250 ns
300 = 300 ns
350 = 350 ns
1
MIL 883
CLASS B
SCREENED
6-54
seeQ
EIM28C256
Timer E2
256K Electrically Erasable PROM
October 1989
Features
•
•
•
Military and Extended Temperature Range
• -55°C to + 125°C Operation (Military)
• -40° to +85°C Operation (Exended)
CMOS Technology
LowPower
• 60 mA Active
• 250 pA Standby
•
Page Write Mode
• 64 Byte Page
• 160 us Average Byte Write Time
•
Byte Write Mode
•
Write Cycle Completion Indication
• DATA Polling
•
On Chip Timer
• Automatic Erase Before Write
•
High Endurance
• 10,000 Cycles/Byte
·10 Year Data Retention
•
Power Up/Down Protection Circuitry
•
200 ns Maximum Access Time
•
JEDEC Approved Byte Wide Pinout
Description
SEEQ's EIM28C256 is a CMOS 5V only, 32K x 8 Electrically Erasable Programmable Read Only Memory
(EEPROM). It is manufactured using SEEQ's advanced
1.25 micron CMOS Process and is available in a 28 pin
Cerdippackage a Plastic Leadless Chip Carrier (PLCC) as
well as a Leadless Chip Carrier (LCC). The 28C256 is ideal
for applications which require low power consumption,
non-volatility and in system reprogrammability. The en-
Pin Configuration
DUAL-IN-L1NE
TOP VIEW
vee
WE
A14
Block Diagram
A12
E2
MEMORY
ARRAY
LEAD LESS CHIP CARRIER
BOTTOM VIEW
A7
1. 13
A&
1.8
As
Ag
A4
All
1.3
OE
A2
1. 10
Al
CE
1.0
1.0 7
1.0 0
1.0&
1.0 1
l,os
1.0
2
1.04
GND
1.03
Pin Names
1100•7
seeQ
MD4000211E
Technology, Incorporated
6-55
Ao-As
A6- A14
ADDRESSES - COLUMN
CE
CHIP ENABLE
ADDRESSES - ROW
OE
OUTPUT ENABLE
WE
WRITE ENABLE
110
DATA INPUT (WRITE)/DATA
OUTPUT (READ)
EIM28C256
durance, the number of times a byte can be written, is
specified at 10,000 cycles per byte and, is typically
1,000,000 cycles per byte. The extraordinary high endurance was accomplished using SEEQ's proprietary oxynitride EEPROM process and it's innovative Q CelfTM
design. System reliability, in all applications, is higher
because of the low failure rate of the Q Cell.
Writes
To write into a particular location, the address must be
valid and a TTL low applied to the Write Enable (WE) pin
of a selected (CE low) device. This combined with Output
Enable (OE) being high initiates a write cycle. During a
byte write cycle, all inputs except data are latched on the
falling edge of WE or CE, whichever occurred last. Write
enable needs to be at a TTL low only for the specified
twp time. Data is latched on the rising edge of WE or CE
whichever occurred first. An automatic erase is performed
before data is written.
The 28C256 has an internal timer which automatically
times out the write time. The on-chip timer, along with input
latches free the microprocessor for other tasks while the
part is busy writing. The 28C256's write cycle time is 10 ms
maximum. An automatic erase is performed before a
write. The DATA polling feature of the 28C256 can be
used to determine the end of a write cycle. Once the write
cycle has been completed, data can be read in a maximum
of 200 ns. Data retention is greater than 10 years.
The 28C256 can write both bytes and blocks of up to 64
bytes. The write mode is discussed below.
Write Cycle Control Pins
For system design simplification, the 28C256 is designed
such that either the CE or WE pin can be used to initiate a
write cycle. The device uses the latest high-to-Iow transition of either CE or WE signal to latch addresses and the
earliest low-to-high transition to latch the data. Address
and OE set up and hold are with respect to the later ofCE
or WE; data setup and hold is with respect to the earlier of
WEorCE.
Device Operation
Operational Modes
There are five operational modes (see Table 1) and,
except for the chip erase mode, only TTL inputs are
required. A write can only be initiated under the conditions
shown. Any other conditions for CE, OE, and WE will
inhibit writing and the I/O lines will either be in a high
impedance state or have data, depending on the state of
a forementioned three input lines.
Mode Selection
Mode
CE
Read
Standby
Write
Write
Inhibit
Chip Erase
V'L
V'H
V'L
X
X
V'L
To simplify the following discussion, the WE pin is used as
the write cycle control pin throughout the rest of this data
sheet. Timing diagrams of both write cycles are included
in the AC Characteristics.
(Table 1)
OE
WE
1/0
V'L
X
V'H
X
DOUT
High Z
V'H
X
V'L
VH
V'L
V'H
X
D'N
High ZlDouT
High ZlDouT
X
V'L
Write Mode
One to 64 bytes of data can be randomly loaded into the
device. The part latches row addresses, A6-A 14, during
the first byte write. These addresses are latched on the
falling edge of the WE signal and are ignored after that until
the end of twc. This will eliminate any false write into
another page if different row addresses are applied and
the page boundary is crossed.
X: Any TTL level
VH: High Voltage
The column addresses, AO-A5, which are used to select
different locations of the page, are latched every time a
new write is initiated. These addresses and the OE state
(high) are latched on the falling edge of WE signal. For
proper write initiation and latching, the WE pin has to stay
low for a minimum of twp ns. Data is latched on the rising
edge of WE, allowing easy microprocessor interface.
Reads
A read is typically accomplished by presenting the addresses of the desired byte to the address inputs. Once
the address is stable, CE is brought to a TTL low in order
to enable the chip. The WE pin must be at a TTL high
during the entire read cycle. The output drivers are made
active by bringing Output Enable (OE) to a TTL low. During
read, the addresses, CE, OE, and input data latches are
transparent.
Upon a low to high WE transition, the 28C256 latches data
and starts the internal page load timer. The timer is reset
on the falling edge of the WE signal if another write is
Q Cell is a trademark of SEEQ Technology, Inc.
seeQ
MD400021/E
Technology, Incorporated
6-56
EIM28C256
initiated before the timer has timed out. The timer stays
reset while the WE pin is kept low. If no additional write
cycles have been initiated within tSLe after the last W£ low
to high transition, the part terminates the page load cycle
and starts the internal write. During this time which takes
a maximum of 10 ms, the device ignores any additional
write attempts. The part can now be read to determine the
end of write cycle (DATA Polling).
the ones-complement of the last byte written. When the
28C256 has completed its write cycle, a read from the last
address written will result in valid data. Thus, software can
simply read from the part until the last data byte written is
read correctly. A DATA polling read should not be done
until a minimum of tLP microseconds after the last byte is
written. Timing for a DATA polling read is the same as a
normal read once the tLP specification has been met.
Extended Page Load
Chip Erase
In order to take advantage of the page mode's faster
average byte write time, data must be loaded at the page
load cycle time (tsLe). Since some applications may not
be able to sustain transfers at this minimum rate, the
28C256 permits an extended page load cycle. To do this,
the write cycle must be "stretched" by maintaining WE low,
assuming a write enable-controlled cycle, and leaving all
other control inputs (C£, O£) in the proper page load cycle
state. Since the page load timer is reset on the falling edge
of W£, keeping this signal low will inhibit the page load
timer. When WE returns high, the input data is latched and
the page load cycle timer begins. In C£ controlled write the
same is true, with C£ holding the timer reset instead of WE.
Certain applications may require all bytes to be erased
simultaneously. This feature, which requires high voltage,
is optional and timing specifications are available from
SEEQ.
Power Up/Down Considerations
There is internal circuitry to minimize a false write during
power up or power down. This circuitry prevents writing
under anyone of the following conditions.
1. Vee is less than VWI V.
2. A high to low Write Enable (W£) transition has not
occurred when the Vee supply is between VWI V and
Vee with C£ low and O£ high.
DATA Polling
The 28C256 has a maximum write cycle time of 10 ms.
Typically though, a write will be completed in less than the
specified maximum cycle time. DATA polling is a method
of minimizing write times by determining the actual endpoint of a write cycle. If a read is performed to any address
while the 28C256 is still writing, the device will present
seeQ
AfD4000211E
Writing will also be inhibited when WE, C£, or O£ are in
TTL logical states other than that specified for a byte write
in the Afode Selection table.
Technology, Incorporated
6-57
EIM28C256
Overshoot pulse of less than 10 ns (measred at
50% point )applied to all inputs or outputs
with respect to ground ..................................... + 7.0 V
Absolute Maximum Stress Range*
Temperature
Storage .............................................. -65°C to + 150°C
Under Bias ......................................... -65°C to + 135°C
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. Voltage applied to all Inputs or Outputs
with respect to ground ....................... +6.0 V to -0.5 V
Undershoot pulse of less then 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground ...................................... -1.0 V
Recommended Operating Conditions
I Temperature Range
I Vee Power Supply
M28C256
E28C256
(Case) -55°C to + 125°C
(Ambient) -40°C to +85°C
5V
± 10%
5V
± 10%
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
DC Characteristics
Condition
Read Operation (Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol
Parameter
Icc
Max.
Units
Active Vee Current
60
mA
CE = OE =V IL : All 1/0 open;
Other Inputs = Vcc Max.
Min. read or write cycle time
ISBI
Standby Vee Current
(TIL Inputs)
2
rnA
CE = VIH , OE = V IL; All 1/0 Open;
Other Inputs = VIL to V IH
ISB2
Standby Vcc Current
(CMOS Inputs)
250
IlA
CE = Vee -0.3
Other Inputs = VIL to V IH
All 1/0 Open
1
IlA
IlA
VIN
10
V
I [2)
IL
Min.
Input Leakage Current
[3)
Test Condition
IOL
V IL
Output Leakage Current
Input Low Voltage
-0.3
0.8
V IH
Input High Voltage
2.0
6
V
VOL
V OH
Output Low Voltage
0.45
V
IOL
IOH
VWI
[1)
Output High Voltage
2.4
V
Write Inhibit Voltage
3.8
V
NOTES:
1. Characterized. Not tested.
2. Inputs only. Does not include VO.
3. For 110 only.
seeQ
MD4000211E
Technology, Incorporated
6-58
= Vee Max.
= Vee Max.
VOUT
= 2.1 rnA
= -400 J,JA
EIM28C256
Capacitance [1]
T A = 25°C, f
= 1 MHz
Parameter
Max.
Conditions
C IN
Input Capacitance
6 pF
VIN = OV
C OUT
Data (1/0) Capacitance 12 pF
Symbol
A.C. Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V
VItO = OV
E.S.D. Characteristics
Symbol
VZAP
[21
Parameter
Value
Test Conditions
E.S.D. Tolerance
>2000 V.
M,L-STD 883
Test Method 3015
AC Characteristics
Read Operation (Over operating temperature and Vee range, unless otherwise specified)
Limits
EIM28C256-200 EIM28C256-250 jEIM28C256-300 E1M28C256·350
Test
Max. Units Conditions
Symbol Parameter
Min. Max.
Min. Max. Min. Max. Min.
t Re
Read Cycle Time
200
250
ns
CE = OE =VIL
teE
Chip Enable Access Time
200
250
300
350
ns
OE = V IL
tAA
Address Access Time
200
250
300
350
ns
CE = OE = VIL
tOE
Output Enable Access Time
80
90
90
90
ns
CE = VIL
tOF
Output or Chip Enable High to
output in Hi-Z
0
80
ns
CE = VIL
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
ns
CE = OE = VIL
60
0
0
300
60
0
0
350
80
0
0
Read IDATA Polling Cycle
1-4----- tRC----ADDRESSES
ADDRESSES A N
CE
DE
HIGHZ
DATA-----+------~<
~---tAA----~
NOTES:
1. This parameter is measured only for the innial qualification and after process or design changes which may affect capacnance.
2. Characterized. Not tested.
seeQ
MD4000211E
Technology, Incorporated
6-59
EIM28C256
AC Characteristics
Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
Symbol
Parameter
t
·wc
t AS
tAH
Write Cycle Time
tcs
EIM28C256·200
EIM28C256-250
Min.
Min.
Max.
10
Max.
EIM28C256·300
EIM28C256·350
Min.
Min.
10
Max.
10
Max.
Units
10
ms
Address Set·up Time
20
20
20
20
ns
Address Hold Time (see note 1)
150
150
150
150
ns
Write Set·up Time
0
0
0
0
ns
tCH
Write Hold Time
0
0
0
0
ns
tcw
CE Pulse Width (note 2)
150
150
150
150
ns
tOES
OE High Set-up Time
20
20
20
20
ns
tOEH
OE High Hold Time
20
20
20
20
ns
twp
WE Pulse Width (note 2)
150
150
150
150
ns
tos
Data Set·up Time
50
50
50
50
ns
tOH
Data Hold Time
0
0
0
0
ns
tSlC
Byte Load Timer Cycle
(Page Mode Only) (note 3)
t lP
Last Byte Loaded
to DATA Polling
0.2
200
0.2
200
650
650
0.2
200
0.2
650
200
/-ls
650
/-ls
Write Timing
WE CONTROLLED WRITE CYCLE
CE
CE CONTROLLED WRITE CYCLE
WE
WE
Ce
DATA
DATA
NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. less than a 20 nsec write pulse will not activate a write cycle.
3. fat.c min. is the minimum time before the next byte can be loaded. fat.c max. is the minimum time the byte load timer waits before initiating
internal write cycle.
seeQ
MD4000211E
Technology. Incorporated
6-60
EIM28C256
Page Write Timing
~;:::::::~~::::~;:::::~PA~G~E~L~O:A~D------------------~4----
~~~~~~~~
------;;;,-.
----,,~.!~
DATA
..
HIGHZ
Ordering Information
o
M
28C265 - 250
18
~~_T----,
PACKAGE
TYPE
D=CERAMIC
L=LCC
F=FLATPACK
P=PLCC
seeQ
AfD4000211E
TEMPERATURE
RANGE
M = -55°C to + 125°C
(MILITARY)
E = -4O"C to +85°C
(EXTENDED)
PART TYPE
32K
x 8 EEPROM
Technology, Incorporated
6-61
ACCESS TIME
200 = 200 ns
250= 250 ns
300 = 300 ns
350 = 350 ns
SCREENING OPTION
MIL 883 CLASS B
SCREENED
6-62
seeQ
EIM28C256A
256K High Speed EEPROM
PRELIMINARY DATA SHEET
November 1989
FEATURES
•
Military and Extended Temperature Range
• -55° C to +125° C Operation (Military)
• -40° C to +85° C Operation (Extended)
• High Endurance
• 10,000 Cycles/Byte
• 10 Year Data Retention
•
HlghSpeed
• 150 nsec Maximum Access Time
• 5V +/- 10% Power Supply
•
Low Power CMOS Technology
• 80 mA Active Current
• 300 IIA Standby Current
•
Fast Write Cycle Times
• 64 Byte Page Write Operation
·5 ms Typical Byte/Page Write Time
• 80llssc A verage Byte Write Time
•
• CMOS & TTL Compatible I/O
• Packages
·28 Pin DIP, 32 Pad LCC, 28 Lead Flatpack
&28PinPGA
Pin Configuration
DUAL-IN-LlNE,
FLAT PACK
TOP VIEW
On-Chip Timer
• Automatic Erase before Write
LEAD LESS CHIP CARRIER
TOP VIEW
• End of Write Detection
• DATA Polling
• Toggle Bit
• Software Accessible Control Register
• Disable Software Protection Mode
• Chip Erase
• Disable Automatic Erase before Write
• Data Protection
• Hardware: Power Up/Down Protection Circuitry
• JEDEC Approved Software Write Protection
Block Diagram
Pin Names
seeQ
AdD400078/B
Technology, Incorporated
6-63
Ao-As
ADDRESSES - COLUMN
A6 -A'4
CE
CHIP ENABLE
ADDRESSES - ROW
OE
OUTPUT ENABLE
WE
1100_7
WRITE ENABLE
DATA INPUT (WRITE)/DATA
OUTPUT (READ)
EIM28C256A
PRELIMINARY DATA SHEET
DESCRIPTION
The SEEQ 28C256A is a high performance 5V only,
32Kx8 Electrically Erasable Programmable Read Only
Memory (EEPROM). It is manufactured using SEEQ's advanced 1.0 micron CMOS process and is available in 28
pin Cerdip, 32 pad Leadless Chip Carrier (LCC), 28 Lead
Ceramic F!atpack, and 28 pin Po4G. The 28C256A is ideal
for high speed applications which require low power consumption, non-volatility, and in-system reprogrammability. The endurance, the number of times which a byte may
be written, is specified at 10,000 cycles per byte minimum.
OE, and WE will inhibit writing and the 110 lines will either
be in a high impedance state or have data, depending on
the state of the aforementioned three input lines.
Reads
A read is accomplished by presenting the addresses of the
desired byte to the address inputs. Once the address is
stable, CE is brought to a CMOSITTL lowin order to enable
the chip. The WE pin must be at a CMOSITTL high during
the entire read cycle. The ouput drivers are made active
by bringing output enable, OE, to a CMOSITTL low.
During read, the addresses, CE, OE, and 110 latches are
transparent.
The 150 ns maximum access time meets or exceeds the
requirements of most of today's high performance microprocessors. To allow the system designer maximum
flexibility, the following features have been added to the
device. The 28C256A has an internal timer which automatically times out the write time. The on-chip timer, along
with the high speed input latches, frees the microprocessor for other tasks during the write time. The 28C256A's
write cycle time is 5 msec typical. An automatic erase is
performed before each write. The DATA PollingIToggle Bit
feature can be used to determine the end of a write cycle.
A built-in control register allows a software controlled chip
erase as well as the ability to disable the autoerase feature.
This permits the user to effectively shorten the write time
by half. Once the write cycle has been completed, data
can be read in a maximum of 150 nsec. All inputs are
CMOSffTL for both write and read modes. Data retention
is specified to be greater than 10 years.
Writes
To write into a particular location, addresses must be valid
and a CMOSITTL low is applied to the write enable, WE,
pin of a selected (CE low) device. This combined with the
output enable, OE, being high, initiates a write cycle.
During a byte write cycle, all inputs except data are latched
on the fallng edge of WE or CE, whichever one occurred
last. Write enable needs to be at a CMOSITTL low only for
the specified twp time. Data is latched on the rising edge
of WE or CE, whichever one occurred first. An automatic
erase is performed before data is written. Automatic erase
before write can be disabled to shorten the write cycle time.
The 28C256A can write both bytes or blocks of up to 64
bytes. The write mode is discussed below.
DEVICE OPERA TlON
Write Cycle Control Pins
For system design simplification, the 28C256A is designed such that either the CE or WE pin can be used to
initiate a write cycle. The device uses the latest high-to-Iow
transition of eitherCE or WE signal to latch addresses and
the earliest low-to-high transition to latch the data. Address and OE set up and hold are with respect to the later
of CE or WE; data set up and hold is with respect to the
earlier of WE or CEo
Operational Modes
There are five operational modes (see Table 1) and,
except for the hardware chip erase mode, only CMOSITTL
inputs are required. A write cycle can only be initiated
under the conditions shown. Any other conditions for CE,
Table 1 Mode Selection
Mode
<5E
OE
WE
Read
Standby
Write
Write
Inhibit
Chip Erase
V1L
V1H
V1L
X
V1H
X
VIL
V1L
X
VIH
X
X
V1L
VIL
V1H
X
VIL
VIH
X
X
VIL
V1L
VH
V1L
1/0
To simplify the following discussion, the WE pin is used as
the control pin throughout the rest of this document.
Dour
HighZ
Write Mode
One to 64 bytes of data can be loaded randomly into the
28C256A. Addresses A6-A14 select the page address
and must remain the same throughout the page load cycle.
These addresses are latched on the falling edge of the WE
signal (assuming WE controlled write cycle).
DIN
High ZlDour
High Z
High ZlDOlJT
No Operation
(HighZ)
The column addresses, AO-A5, which are used to write into
different locations of the page, are latched every time a
new write is initiated. These addresses along with OE
X
X: Any CMOSITTL level
VH : 12V ± 10%
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MD4000781B
Technology, Incorporated
6-64
EIM28C256A
PRELIMINARY DATA SHEET
state (high) are latched on the falling edge of WE signal.
For proper write initiation and latching, the WE pin has to
stay low for a minimum of twp ns. Data is latched on the
rising edge of WE, allowing easy microprocessor interface.
/106 Toggle Bit Polling
In addition to the polling method described above, the
28C256A provides 1106 Toggle Bit to determine the end of
the internal write cycle. While the internal write cycle is in
progress, 1106 toggles from 1 to 0 and 0 to 1 on sequential
polling reads. When the internal write cycle is complete the
toggling stops and the 28C256A is ready for additional
read or write operations. This feature is particularly useful
when writing to multiple devices simultaneously.
Upon a low to high WE transition, the 28C256A latches
data and starts the internal page load timer. The timer is
reset on the falling edge of WE signal if another write is
initiated before the timer has timed out. The timer stays
reset while the WE pin is kept low. If no additional write
cycles have been initiated in (taLc) after the last WE low to
high transition, the part terminates the page load cycle and
starts the internal write. During this time, which takes a
maximum of twe the device ignores any additional load
attempts. The part can now be read to determine the end
of write cycle (DA TA Polling/Toggle Bit). A 80 J.ls average
byte write time can be achieved if the page is fully utilized.
The write time can be further optimized to 40 J.lS average
by disabling automatic erase before write.
Hardware Chip Erase
Certain applications may require all bytes to be erased
simultaneously. This can be achieved by clearing one
byte at a time, however, this would require a clock cycle for
each byte or page clear. The high voltage chip erase
function completes this task with a single clock cycle, thus
reducing the total erase time considerably. Please refer to
the Hardware Chip Erase waveforms for timing specifics.
Write Data Protection
Hardware Feature
There is internal circuitry to minimize a false write during
Vcc power up or down. This circuitry prevents writing
under anyone of the following conditions:
Extended Page Load
In order to take advantage of the page mode's faster
average byte write time, data must be loaded within the
page load cycle time (taLc
Since some applications
may not be able to sustain transfers at this minimum rate,
the 28C256A permits an extended page load cycle. To do
this, the write cycle must be "stretched" by maintaining WE
low, assuming a write enable controlled cycle and leaving
all other control inputs (CE, OE) in the proper page load
cycle state. Since the page load timer is reset on the falling
edge of WE, keeping this signal low will prevent the page
load cycle timer from beginning. In a CE controlled write
the same is true, with CE holding the timer reset instead of
WE.
maJ
1) Vcc is less than Vwr
_
2) A high to low Write Enable (WE) transition has not
occurred when theVcc supply is between VW1 and
Vcc with CE low and OE high.
Writing wiJ/ also be inhibited when WE, CE, or OE are in
logical states other than that specified for a byte write in the
Mode Selection Table.
Sohware Write Protect (SWP)
The 28C256A has the ability to enable and disable write
operations under software control by accessing an internal
control register. Software control of write operations can
reduce the probability of inadvertant writes resulting from
power up, power down, or momentary power disturbances. The 28C256A is shipped with the software write
protect mode deactivated (default power-up mode) to
provide compatibility with parts not having this mode. The
software write protection mode is set by performing a page
write operation (using page mode write timing) using
specific addresses and data.
DATA Polling
/107 DATA Polling
The 28C256A has a maximum write cycle time of twc'
However, a write will typically be completed in less than the
specified maximum cycle time. DATA polling is a method
of minimizing write times by determining the actual end
point of a write cycle. If a read is performed to any address
while the 28C256A is still writing, the device will present
the ones-complement of data bit 1107. When the 28C256A
has completed its write cycle, a read from the last address
written will result in valid data. Thus, software can simply
read from the part until the last data byte written is read
correctly. A DATA polling read should not be initiated until
a minimum of tIP nanoseconds after the last byte is written.
DATA polling attempted during the middle of a page load
cycle will present a ones-complement of the most recent
data bit 1107 loaded into the page. Timing for a DATA
polling read is the same as a normal read once the tLP
specification has been met.
seeQ
MD4000781B
Set Software Write Protect
A three step write sequence shown below in TABLE 2 is
used to set the protect mode. Page mode write timing is
to be used. A violation of this sequence or the time-out of
the page timer (taLC) will abort the set protection mode (see
note). Reads attempted during the access sequence will
Technology, Incorporated
6-65
EIM28C256A
PRELIMINARY DATA SHEET
volatile write cycle. The features are available for use both
in the protected and unprotected (standard) modes. Page
mode write timing is to be used. A violation of this
sequence or the time-out of the page timer (tsu) will abort
the access sequence and undesired writes could occur if
the part is not software protected. Reads attempted during
the access sequence will be assumed to be DATA polling
read.
be assumed to be a DATA polling read and result in the
device presenting a ones complement of the last data bit
1/07 written.
Protected Write Operation
Once the software protect mode is set, the software
algorithm shown in TABLE 3 must be used for every byte
write or page write cycle. The write operation uses the
same three sequential steps shown in TABLE 2 to unlock
the write protection for each byte/page write. The first
three bytes unlock write protection while the fourth and
successive bytes if any are written into the device.
Software Chip Erase
5 V only software chip erase is performed by executing the
six step access sequence shown in TABLE 5. Control data
word 10 hex should be written to the secondary control
register. DATA polling can be done during chip erase to
determine the completion of chip erase. The six step write
need not be followed by a byte or page data load. At the
end of the six step access sequence, the device begins
and completes chip erase internally. Chip erase command
can only be issued with the autoerase before write function
enabled.
Only single byte or page loads can be performed. After
completion of internal write cycle, the device returns to the
protected mode. The access sequence shown in TABLE
3 must be repeated to write an additional byte or page.
Disable Software Write Protection
The software protection can be disabled by following the
six step sequence shown in TABLE 4. The device will be
reconfigured to hardware protect mode only after this
sequence. Page mode write timing is to be used. A
violation of this sequence or the time-out of the page timer
(tsu) will abort the reset protection mode. Reads attempted during the access sequence will be assumed to
be DATA polling read.
Disable Autoerase
This command disables the automatic erase before write
cycle and is used typically after a chip erase operation to
reduce the programming time of the device. The six step
write sequence shown in TABLE 6 is used to perform the
operation. Control data word 40 hex should be written to
the secondary control register on the sixth step. At the end
of the six step sequence auto erase before write is disabled
for the current byte or page write sequence. At end of the
internal byte or page write cycle automatic erase before
write is re-enabled. Autoerase before write is always
enabled on power-up/reset (default).
SOFTWARE CONTROLLED SPECIAL FUNCTIONS
Chip erase and disable auto erase functions are accessed
using the six step sequence shown in TABLES 5 & 6. The
six step access sequence need not be followed by a non-
TABLE 2 Set Software Write Protect Operation Sequence
Step
Mode
Address A 14-AO
Data 110 7-0
1
Write
5555 Hex
AAHex
Dummy write.
2
Write
2AAA Hex
55 Hex
Dummy write.
3
Write
5555 Hex
AD Hex
Dummy write.
SWP state activated.
4-67
Write
Address
Data
Write data to address.
Byte or Page write.
Comment
NOTE: SWP protected state will be activated at the end of write even if a byte or page data load is NOT
attempted after the three step access sequence. In such a case, after the three step access sequence
AND t BLC timeout, SWP bit is set by performing a non-volatile write cycle. The SWP non-volatile bit
is set for protected mode operation during the first access sequence to the part. Once the SWP nonvolatile bit is set, subsequent writes require the 3 step sequence to enable byte or page writes.
Undesired writes could occur as a result of first access sequence violation while attempting to set SWP.
seeQ
MD400078/B
Technology, Incorporated
6-66
EIM28C256A
PRELIMINARY DATA SHEET
TABLE 3 Protected Mode Write Operation Sequence
Step
Mode
Address A14-AO
Data 1/0 7.(J
1
Write
5555 Hex
AAHex
Dummy write.
2
Write
2AAA Hex
55 Hex
Dummy write.
3
Write
5555 Hex
AO Hex
Dummy write.
Enable byte/page writes.
4-67
Write
Address
Data
Write data to address.
Byte or page write.
Comment
TABLE 4 Disable Protected Mode Operation Sequence
Step
Mode
Address A 14-AO
Data 1/07-0
1
Write
5555 Hex
AAHex
Dummy write.
2
Write
2AAA Hex
55 Hex
Dummy write.
3
Write
5555 Hex
80 Hex
Dummy write.
4
Write
5555 Hex
AA Hex
Dummy write.
5
Write
2AAA Hex
55 Hex
Dummy write.
6
Write
5555 Hex
20 Hex
SWP state deactivated.
7-70
Write
Address
Data
Write data to address.
Byte or Page Write.
Comment
NOTE: The SWP protected mode will be reset at the end of the write even if the six step access sequence
is not followed by a byte or page data load. An internal non-volatile write cycle is performed to
reset SWP bit after the six step access sequence AND ~c timeout.
TABLE 5 Chip Erase Operation Sequence
Step
Mode
Address A 14-AO
Data 1/0 7-0
Comment
1
Write
5555 Hex
AA Hex
Dummy write.
2
Write
2AAA Hex
55 Hex
Dummy write.
3
Write
5555 Hex
80 Hex
Dummy write register.
4
Write
5555 Hex
AA Hex
Dummy write.
5
Write
2AAA Hex
55 Hex
Dummy write.
6
Write
5555 Hex
10 Hex
Chip Erase
TABLE 6 Disable Autoerase Operation Sequence
seeQ
AfD4000781B
Step
Mode
Address A 14-AO
Data 1/0 7-0
Comment
1
Write
5555 Hex
AA Hex
Dummy write.
2
Write
2AAA Hex
55 Hex
Dummy write.
3
Write
5555 Hex
80 Hex
Dummy write register.
4
Write
5555 Hex
AA Hex
Dummy write.
5
Write
2AAA Hex
55 Hex
Dummy write.
6
Write
5555 Hex
40 Hex
Disable Autoerase
7-70
Write
Address
Data
Load Page
Technology, Incorporated
6-67
EIM28C256A
PRELIMINARY DATA SHEET
Absolute Maximum Stress Range*
·'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature
Storage .............................................. -65°C to + 150°C
Under Bias ......................................... -65°C to + 135°C
D.C. Voltage applied to aI/Inputs or Outputs
with respect to ground ....................... +7.0 V to -3.0 V
Recommended Operating Conditions
I Temperature Range
M28C256A
E28C256A
(Case) -55°C to +125°C
(Ambient) -40°C to +S5°C
I Vcc Power Supply
5V
± 10%
5V
± 10%
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 100S
DC Characteristics
Condition
(Over operating temperature and Vcc range, unless otherwise specified)
Limits
Symbol
Parameter
Max.
Units
Icc
Active Vee Current
60
mA
CE = OE = V'L: All 1/0 open;
Other Inputs = Vcc Max.
Min. read or write cycle time
1581
Standby Vcc Current
(TTL Inputs)
2
mA
CE = VIH, OE = V IL; All I/O Open;
Other Inputs = VIL to V IH
1582
Standby Vcc Current
(CMOS Inputs)
300
f.1A
CE = Vee -0.3
Other Inputs = V IL to V IH
All 1/0 Open
I (2]
IL
Min.
Test Condition
= Vcc Max.
Input Leakage Current
1
f.1A
VIN
IOL
V IL
Output Leakage Current
10
f.1A
VOUT = Vcc Max.
Input Low Voltage
-1.0
V IH
Input High Voltage
2.0
VOL
V OH
Output Low Voltage
Output High Voltage
2.4
V
V WI
Write Inhibit Voltage
3.S
V
(3]
0.8
V
Vcc + 1.5
V
0.4
V
101. = 8 mA
IOH = -4 rnA
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect it.
2. Inputs only. Does not include lID.
3. For lID only.
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MD4000781B
Technology, Incorporated
6-68
EIM28C256A
PRELIMINARY DATA SHEET
Capacitance {1l
TA
= 25°C, f =1 MHz
Symbol Parameter
Max.
Conditions
A.C. Test Conditionsl2}
6 pF
VIN = OV
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level: 1.5 V
C IN
Input Capacitance
C OUT
Data (1/0) Capacitance 12 pF
VI/o = OV
E.S.D. Characteristics
Symbol
Parameter
Value
Test Conditions
V ZAP (1)
E.S.D. Tolerance
>2000 V.
MIL-STD 883
Test Method 3015
AC Characteristics
Read Operation (Over operating temperature and Vee range, unless otherwise specified)
Limits
ElM28C256A·150
Symbol
ElM28C256A·200
ElM28C256A·250
Test
Conditions
Max.
Units
ns
CE = OE =V IL
200
250
ns
OE = V IL
150
200
250
ns
CE = OE = VIL
55
55
55
ns
CE = Vil
55
ns
CE = Vil
ns
CE = OE = Vil
Parameter
Min.
Max.
t RC
Read Cycle Time
150
teE
Chip Enable Access Time
150
tAA
Address Access Time
tOE
Output Enable Access Time
tOF
Output or Chip Enable High to
output in Hi-Z
0
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
Min.
Max.
200
55
0
0
Min.
250
55
0
0
Read IDATA Pol1lng Cycle
1 4 - - - - - tRC-------1~
ADDRESSES
NEXT ADDRESS
ADDRESSES AN
OE
HIGHZ
DATA---------+------------~~
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect it.
2. For MIL-STD-833 class B compliant product, all timing levels will be as defined in MIL-STD-883 method 5004.
seeQ
MD4000781B
Technology, Incorporated
6-69
EIM28C256A
PRELIMINARY DATA SHEET
AC Characteristics
Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
EIM28C256A·150
Symbol
Parameter
t
'wc
t AS
Write Cycle Time
tAH
Address Hold Time (see note 1 )
tcs
Write Set·up Time
Address Set-up Time
Min.
Max.
EIM28C256A·200
EIM28C256A·250
Min.
Min.
10
Max.
Max.
Units
10
ms
10
0
0
0
50
50
50
ns
ns
0
0
0
ns
tCH
Write Hold Time
tcw
CE Pulse Width (note 2)
tOEs
OE High Set·up Time
0
0
0
ns
tOEH
OE High Hold Time
0
0
0
ns
twp
WE Pulse Width (note 2)
50
50
50
ns
tos
Data Set-up Time
40
40
40
ns
tOH
Data Hold Time
tSlC
Byte Load Timer Cycle
(Page Mode Only) (note 3)
t lP
Last Byte Loaded
to DATA Polling Output
0
0
0
ns
50
50
50
ns
0
0
0.2
200
150
0.2
0
200
200
0.2
ns
200
Ils
200
ns
Byte Write Timing
WE CONTROLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CE".
2. WE and CE" are noise protected. Less than a 10 nsec write pulse will not activate a write cycle.
3. ~c min. is the minimum time before the next byte can be loaded. ~c max. is the minimum time the byte load timer waits before initiating
internal write cycle.
seeQ
MD4000781B
Technology, Incorporated
6·70
EIM28C256A
PRELIMINARY DATA SHEET
Page Write Timing/ WE Controlled
~
_____________________ MGELOAD ________________
~.-
__
'J
CE
WE
DATA
HIGHZ
>--1~--«
Hardware Chip Erase
VIH
"
CE
)
VIL
IELWL
,
VIH
/
IOHEL
\
IOVHWL
IWHOH
VIH
\
DATA/-V
seeQ
~D400078/B
\
IWLWH
WE
ADDRESSES~~
~
IWHEH
VH
OE
\
VIL
J
DON'T CARE
~
_______________________________________________________
~
Technology, Incorporated
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EIM28C256A
PRELIMINARY DATA SHEET
Hardware Chip Erase
Parameter
Description
t
Chip Enable Setup TIme
5
Jls
tOVHEL
Output Enable Setup TIme
5
Jls
t
Write Enable Pulse Width
10
ms
tWHEH
Chip Enable Hold TIme
5
Jls
t WHOH
Output Enable Hold TIme
5
tOHEL
Erase Recovery TIme
VH
High Voltage
ELWL
WLWH
Min.
Max.
Units
Jls
10.8
50
ms
13.2
V
Ordering Information
o
M
28C256A - 150
/8
~S!-T----,
PACKAGE
TYPE
TEMPERATURE
RANGE
D = CERAMIC DIP
L= LCC
F=FLATPACK
T=PGA
seeQ
MD4000781B
M = -55°C to + 125°C
(MILITARY)
E = -40°C to +85°C
(EXTENDED)
PART TYPE
32K x 8 EEPROM
Technology, Incorporated
6-72
ACCESS TIME
SCREENING OPTION
150 = 150 ns
200= 200 ns
250=250 ns
MIL 883 CLASS B
SCREENED
seeQ
EIM28HC256
256K High Speed EEPROM
November 1989
PRELIMINARY DATA SHEET
FEATURES
•
Military and Extended Temperature Range
• -55° C to + 125° C Operation (Military)
• -40° C to + 85° C Operation (Extended)
• High Endurance
·10,000 Cycles/Byte
• 10 Year Data Retention
•
HighSpeed
• 70 nsec Maximum Access Time
• CMOS & TTL Compatible I/O
•
Low Power CMOS Technology
• 80 mA Active Current
• 300 IlA Standby Current
• Packages
·28 Pin DIP, 32 Pad LCC, 28 Lead Flatpack,
&28PinPGA
•
Fast Write Cycle Times
• 64 Byte Page Write Operation
• 5 ms Typical Byte/Page Write Time
• 80 Ilsec Average Byte Write Time
•
• 5V +/- 10% Power Supply
Pin Configuration
DUAL-IN-L1NE,
FLAT PACK
TOP VIEW
On-Chip Timer
• Automatic Erase before Write
• End of Write Detection
• DATA Polling
• Toggle Bit
Vee
WE
A14
A12
A7
"13
As
• SOftware Accessible Control Register
• Disable Software Protection Mode
• Chip Erase
• Disable Automatic Erase before Write
• Data Protection
• Hardware: Power Up/Down Protection Circuitry
• JEDEC Approved SOftware Write Protection
Block Diagram
LEAD LESS CHIP CARRIER
TOP VIEW
A8
As
A9
A4
A11
"3
DE
A2
A 10
AI
CE
Ao
110 7
110 0
IlOs
110 1
IIO S
110 2
1104
GND
110 3
Pin Names
seeQ
MD4000821A
110 _
07
Technology, Incorporated
6-73
ADDRESSES - COLUMN
Ao-As
A6- A14
ADDRESSES - ROW
CE
CHIP ENABLE
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00-7
DATA INPUT (WRITE)/DATA
OUTPUT (READ)
EIM28HC256
PRELIMINARY DATA SHEET
DESCRIPTION
The SEEQ 28HC256 is a high performance 5V only,
32Kx8 Electrically Erasable Programmable Read Only
Memory (EEPROM). It is manufactured using SEEQ's advanced 1.0 micron CMOS process and is available in 28
pin Cerdip, 32 pad Leadless Chip Carrier(LCC), 28 Lead
Ceramic F/atpack, and 28 pin PGA. The 28HC256 is idea;
for high speed applications which require low power consumption, non-volatility, and in-system reprogrammability. The endurance, the number of times which a byte may
be written, is specified at 10,000 cycles per byte minimum.
bE, and WE will inhibit writing and the VO lines will either
be in a high impedance state or have data, depending on
the state of the aforementioned three input lines.
Reads
A read is accomplished by presenting the addresses of the
desired byte to the address inputs. Once the address is
stable, CE is brought to a CMOSITTL low in order to enable
the chip. The WE pin must be at a CMOSITTL high during
the entire read cycle. The ouput drivers are made active
by bringing output enable, OE, to a CMOSITTL low.
During read, the addresses, CE, OE, and VO latches are
transparent.
The 70 ns maximum access time meets or exceeds the
requirements of most of today's high performance microprocessors. To allow the system designer maximum
flexibility, the following features have been added to the
device. The 28HC256 has an internal timer which automatically times out the write time. The on-chip timer, along
with the high speed input latches, frees the microprocessor for other tasks during the write time. The 28HC256's
write cycle time is 5 msec typical. An automatic erase is
performed before each write. The DATA PollingIToggle Bit
feature can be used to determine the end of a write cycle.
A built-in control register allows a software controlled chip
erase as well as the ability to disable the autoerase feature.
This permits the user to effectively shorten the write time
by half. Once the write cycle has been completed, data
can be read in a maximum of 70 nsec. All inputs are
CMOSITTL for both write and read modes. Data retention
is specified to be greater than 10 years.
Writes
To write into a particular location, addresses must be valid
and a CMOSITTL low is applied to the write enable, WE,
pin of a selected (CE low) device. This combined with the
output enable, OE, being high, initiates a write cycle.
During a byte write cycle, all inputs except data are latched
on the fallng edge of WE or CE, whichever one occurred
last. Write enable needs to be at a CMOSITTL low only for
the specified twp time. Data is latched on the rising edge
of WE or CE, whichever one occurred first. An automatic
erase is performed before data is written. Automatic erase
before write can be disabled to shorten the write cycle time.
The 28HC256 can write both bytes or blocks of up to 64
bytes. The write mode is discussed below.
DEVICE OPERA TION
Write Cycle Control Pins
Operational Modes
There are five operational modes (see Table 1) and,
except for the hardware chip erase mode, only CMOS/TTL
inputs are required. A write cycle can only be initiated
under the conditions shown. Any other conditions for CE,
For system design simplification, the 28HC256 is designed such that either the CE or WE pin can be used to
initiate a write cycle. The device uses the latest high-to-Iow
transition of eitherCE or WE signa/to latch addresses and
the earliest low-to-high transition to latch the data. Address and OE set up and hold are with respect to the later
of CE or WE; data set up and hold is with respect to the
earlier of WE or CEo
Table 1 Mode Selection
Mode
CE
OE
WE
1/0
Read
VIL
VIL
VIH
Dour
Standby
VIH
X
X
HighZ
Write
VIL
VIH
VIL
DIN
Write
Inhibit
X
VIH
X
X
VIH
X
High ZlDour
HighZ
X
VIL
VIL
VIL
X
VIL
High ZlD our
No Operation
(HighZ)
VIL
VH
VIL
X
Chip Erase
To simplify the following discussion, the WE pin is used as
the control pin throughout the rest of this document.
Write Mode
One to 64 bytes of data can be loaded randomly into the
28HC256. Addresses A6-A14 select the page address
and must remain the same throughout the page load cycle.
These addresses are latched on the falling edge of the WE
signal (assuming WE controlled write cycle).
The column addresses, AO-A5, which are used to write into
different locations of the page, are latched every time a
new write is initiated. These addresses along with OE
X: Any CMOSrrTL level
VH : 12V ± 10%
seeQ
MD4000821A
Technology, Incorporated
6-74
EIM28HC256
PRELIMINARY DATA SHEET
1106 Toggle Bit Polling
In addition to the polling method described above, the
28HC256 provides 1106 Toggle Bit to determine the end of
the internal write cycle. While the internal write cycle is in
progress, V06 toggles from 1 to 0 and 0 to 1 on sequential
polling reads. When the internal write cycle is complete the
toggling stops and the 28HC256 is ready for additional
read or write operations. This feature is particularly useful
when writing to multiple devices simultaneously.
state (high) are latched on the falling edge of W£ signal.
For proper write initiation and latching, the WE pin has to
stay low for a minimum of twp ns. Data is latched on the
rising edge of WE, allowing easy microprocessor interface.
Upon a low to high WE transition, the 28HC256 latches
data and starts the internal page load timer. The timer is
reset on the falling edge of WE signal if another write is
initiated before the timer has timed out. The timer stays
reset while the W£ pin is kept low. If no additional write
cycles have been initiated in (tSLC) after the last W£ low to
high transition, the part terminates the page load cycle and
starts the internal write. During this time, which takes a
maximum of twe the device ignores any additional load
attempts. The part can now be read to determine the end
of write cycle (DATA PollingIToggle Bit). A 80 I1s average
byte write time can be achieved if the page is fully utilized.
The write time can be further optimized to 40 I1s average
by disabling automatic erase before write.
Hardware Chip Erase
Certain applications may require all bytes to be erased
simultaneously. This can be achieved by clearing one
byte at a time, however, this would require a clock cycle for
each byte or page clear. The high voltage chip erase
function completes this task with a single clock cycle, thus
reducing the total erase time considerably. Please refer to
the Hardware Chip Erase waveforms for timing specifics.
Write Data Protection
Hardware Feature
There is internal circuitry to minimize a false write during
Vcc power up or down. This circuitry prevents writing
under anyone of the following conditions:
Extended Page Load
In order to take advantage of the page mode's faster
average byte write time, data must be loaded within the
page load cycle time (tSLC max)' Since some applications
may not be able to sustain transfers at this minimum rate,
the 28HC256 permits an extended page load cycle. To do
this, the write cycle must be "stretched" by maintaining W£
low, assuming a write enable controlled cycle and leaving
all other control inputs (0£, O£) in the proper page load
cycle state. Since the page load timer is reset on the falling
edge of WE, keeping this signal low will prevent the page
load cycle timer from beginning. In a C£ controlled write
the same is true, with C£ holding the timer reset instead of
WE.
1) Vec is less than VWI'
occurred when theVee supply is between VW1 and
Vec with CE low and OE high.
Writing will also be inhibited when WE, C£, or O£ are in
logical states other than that specified for a byte write in the
Mode Selection Table.
Software Write Protect (SWP)
The 28HC256 has the ability to enable and disable write
operations under software control by accessing an internal
control register. Software control of write operations can
reduce the probability of inadvertant writes resulting from
power up, power down, or momentary power disturbances. The 28HC256 is shipped with the software write
protect mode deactivated (default power-up mode) to
provide compatibility with parts not having this mode. The
software write protection mode is set by performing a page
write operation (using page mode write timing) using
specific addresses and data.
DATA Polling
1107 DATA POlling
The 28HC256 has a maximum write cycle time of tweHowever, a write will typically be completed in less than the
specified maximum cycle time. DATA polling is a method
of minimizing write times by determining the actual end
point of a write cycle. If a read is performed to any address
while the 28HC256 is still writing, the device will present
the ones-complement ofdata bit 1107. When the 28HC256
has completed its write cycle, a read from the last address
written will result in valid data. Thus, software can simply
read from the part until the last data byte written is read
correctly. A DATA polling read should not be initiated until
a minimum of tLP nanoseconds after the last byte is written.
DATA polling attempted during the middle of a page load
cycle will present a ones-complement of the most recent
data bit 1107 loaded into the page. Timing for a DATA
polling read is the same as a normal read once the tLP
specification has been met.
seeQ
MD4000821A
_
2) A high to low Write Enable (W£) transition has not
Set Software Write Protect
A three step write sequence shown below in TABLE 2 is
used to set the protect mode. Page mode write timing is
to be used. A violation of this sequence or the time-out of
the page timer (tsLe ) will abort the setprotection mode (see
note). Reads attempted during the access sequence will
Technology, Incorporated
6-75
EIM28HC256
PRELIMINARY DATA SHEET
volatile write cycle. The features are available for use both
in the protected and unprotected (standard) modes. Page
mode write timing is to be used. A violation of this
sequence or the time-out of the page timer (tBLcJ will abort
the access sequence and undesired writes could occur if
the part is not software protected. Reads attempted during
the access sequence will be assumed to be DATA polling
read.
be assumed to be a DATA polling read and result in the
device presenting a ones complement of the last data bit
1/07 written.
Protected Write Operation
Once the software protect mode is set, the software
algorithm shown in TABLE 3 must be used for every byte
write or page write cycie. The write operation uses the
same three sequential steps shown in TABLE 2 to unlock
the write protection for each byte/page write. The first
three bytes unlock write protection while the fourth and
successive bytes if any are written into the device.
Sohware Chip Erase
5 Vonly software chip erase is performed by executing the
six step access sequence shown in TABLE 5. Control data
word 10 hex should be written to the secondary control
register. DATA polling can be done during chip erase to
determine the completion of chip erase. The six step write
need not be followed by a byte or page data load. At the
end of the six step access sequence, the device begins
and completes chip erase internally. Chip erase command
can only be issued with the auto erase before write function
enabled.
Only single byte or page loads can be performed. After
completion of internal write cycle, the device returns to the
protected mode. The access sequence shown in TABLE
3 must be repeated to write an additional byte or page.
Disable Sohware Write Protection
The software protection can be disabled by following the
six step sequence shown in TABLE 4. The device will be
reconfigured to hardware protect mode only after this
sequence. Page mode write timing is to be used. A
violation of this sequence or the time-out of the page timer
(tBLcJ will abort the reset protection mode. Reads attempted during the access sequence will be assumed to
be DATA polling read.
Disable Autoerase
This command disables the automatic erase before write
cycle and is used typically after a chip erase operation to
reduce the programming time of the device. The six step
write sequence shown in TABLE 6 is used to perform the
operation. Control data word 40 hex should be written to
the secondary control register on the sixth step. At the end
of the six step sequence autoerase before write is disabled
for the current byte or page write sequence. At end of the
internal byte or page write cycle automatic erase before
write is re-enabled. Autoerase before write is always
enabled on power-up/reset (default).
SOFTWARE CONTROLLED SPECIAL FUNCTIONS
Chip erase and disable autoerase functions are accessed
using the six step sequence shown in TABLES 5 & 6. The
six step access sequence need not be followed by a non-
TABLE2Set S 0 It ware
"te rotect operat/on S equence
Step
Mode
Address A 14-AO
Data 1107-0
Comment
1
Write
5555 Hex
AA Hex
Dummy write.
2
Write
2AAA Hex
55 Hex
Dummy write.
3
Write
5555 Hex
AO Hex
Dummy write.
SWP state activated.
4-67
Write
Address
Data
Write data to address.
Byte or Page write.
NOTE: SWP protected state will be activated at the end of write even if a byte or page data load is NOT
attempted after the three step access sequence. In such a case, after the three step access sequence
AND t BLC timeout. SWP bit is set by performing a non-volatile write cycle. The SWP non-volatile bit
is set for protected mode operation during the first access sequence to the part. Once the SWP nonvolatile bit is set. subsequent writes require the 3 step sequence to enable byte or page writes.
Undesired writes could occur as a result of first access sequence violation while attempting to set SWP.
seeQ
MD4000821A
Technology, Incorporated
6-76
EIM28HC256
PRELIMINARY DATA SHEET
TABLE 3 Protected Mode Write Operation Sequence
Step
Mode
Address A 14-AO
Data I/O 7-0
1
Write
5555 Hex
AA Hex
Dummy write.
2
Write
2AAA Hex
55 Hex
Dummy write.
3
Write
5555 Hex
AO Hex
Dummy write.
Enable byte/page writes.
4-67
Write
Address
Data
Write data to address.
Byte or page write.
Comment
TABLE 4 Disable Protected Mode Operation Sequence
Step
Mode
Address A 14-AO
Data 1/07-0
Comment
1
Write
5555 Hex
AA Hex
Dummy write.
2
Write
2AAA Hex
55 Hex
Dummy write.
80 Hex
Dummy write.
3
Write
5555 Hex
4
Write
5555 Hex
AA Hex
Dummy write.
5
Write
2AAA Hex
55 Hex
Dummy write.
6
Write
5555 Hex
20 Hex
SWP state deactivated.
7-70
Write
Address
Data
Write data to address.
Byte or Page Write.
NOTE: The SWP protected mode will be reset at the end of the write even if the six step access sequence
is not followed by a byte or page data load. An internal non-volatile write cycle is performed to
reset SWP bit after the six step access sequence AND
timeout.
tac
TABLE 5 Chip Erase Operation Sequence
Step
Mode
Address A 14-AO
Data I/O 7-0
Comment
1
Write
5555 Hex
AA Hex
Dummy write.
2
Write
2AAA Hex
55 Hex
Dummy write.
3
Write
5555 Hex
80 Hex
Dummy write register.
4
Write
5555 Hex
AA Hex
Dummy write.
5
Write
2AAA Hex
55 Hex
Dummy write.
6
Write
5555 Hex
10 Hex
Chip Erase
TABLE 6 Disable Autoerase Operation Sequence
seeQ
MD4000821A
Step
Mode
Address A 14-AO
Data I/O 7-0
1
Write
5555 Hex
AA Hex
Dummy write.
2
Write
2AAA Hex
55 Hex
Dummy write.
3
Write
5555 Hex
80 Hex
Dummy write register.
4
Write
5555 Hex
AA Hex
Dummy write.
5
Write
2AAA Hex
55 Hex
Dummy write.
6
Write
5555 Hex
40 Hex
Disable Autoerase
7-70
Write
Address
Data
Load Page
Technology, Incorporated
6-77
Comment
EIM28HC256
PRELIMINARY DATA SHEET
Absolute Maximum Stress Range*
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device refiability.
Temperature
Storage .............................................. -65 °C to +150°C
Under Bias ......................................... -65°C to + 135°C
D.C. Voltage applied to all Inputs or Outputs
with respect to ground ........................ +7.0 V to -3.0 V
Recommended Operating Conditions
M28HC256
(Case) -55°C to +125°C
5 V ± 10%
I Temperature Range
I Vee Power Supply
E28HC256
(Ambient) -40°C to +85°C
5 V ± 10%
Endurance and Data Retention
Symbol
N
Parameter
Minimum Endurance
Value
10,000
Units
Cycles/Byte
TOR
Data Retention
>10
Years
DC Characteristics
Condition
MIL-STD 883 Test
Method 1033
MIL-STD 883 Test
Method 1008
(Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol
Parameter
Max.
Units
Icc
Active Vco Current
80
rnA
CE = OE =VIL: All 1/0 open;
Other Inputs =Vcc Max.
Min. read or write cycle time
IS81
Standby Vcc Current
(TTL Inputs)
2
rnA
CE =VIH, OE =V IL; All 1/0 Open;
Other Inputs =VIL to VIH
IS82
Standby Vcc Current
(CMOS Inputs)
300
~A
CE =Vcc -0.3
Other Inputs =VIL to VIH
All 1/0 Open
I (2)
IL
(3)
IOL
VIL
VIH
Input Leakage Current
Output Leakage Current
1
~A
VIN
10
0.8
~A
Vour
IOL =8 mA
IOH =-4 rnA
Min.
-1.0
2.0
VOL
VOH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
2.4
V
V
V
V
VWI
Write Inhibit Voltage
3.8
V
Vcc + 1.5
0.4
Test Condition
= Vcc Max.
= Vcc Max.
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect it.
2. Inputs only. Does not include VO.
3. For I/O on[y.
seeQ
MD4000821A
Technology, Incorporated
6-78
EIM28HC256
PRELIMINARY DATA SHEET
Capacitance [1} T A =25°C, f = 1 MHz
Parameter
Max.
Conditions
C IN
Input Capacitance
6 pF
VIN
C OUT
Data (I/O) Capacitance 12 pF
Symbol
VItO
A.C. Test Conditionsl2}
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level: 1.5 V
= OV
= OV
E.S.D. Characteristics
Symbol
V ZAP
[I)
Parameter
Value
Test Conditions
E.S.D. Tolerance
>2000 V.
MIL-STD883
Test Method 3015
AC Characteristics
Read Operation (Over operating temperature and Vcc range, unless otherwise specified)
Limits
E/M28HC256-70
Symbol Parameter
Min.
Max.
70
E/M28HC256-90
Min.
Max.
E/M28HC256-120
Min.
Max.
Units
Test
Conditions
t RC
Read Cycle Time
ns
CE = OE =V IL
tCE
Chip Enable Access Time
70
90
120
ns
OE = V ,L
tAA
Address Access Time
70
90
120
ns
CE = OE = V ,L
tOE
Output Enable Access Time
35
45
50
ns
CE = V ,L
tOF
Output or Chip Enable High to
output in Hi-Z
0
50
ns
CE = V ,L
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
ns
CE = OE = V ,L
90
35
0
0
120
45
0
0
Read IDATA Polling Cycle
1 4 - - - - - tRC----~~
ADDRESSES
ADDRESSES AN
OE
HIGHZ
DATA---------+------------~~
NOTES:
1.This parameter is measured only for the initial qualification and after process or design changes which may affect it.
2. For MIL-STD-883 class B compliant product, all timing levels will be as defined in MIL-STD-883 method 5004.
seeQ
MD4000821A
Technology, Incorporated
6-79
EIM28HC256
PRELIMINARY DATA SHEET
AC Characteristics
Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
E/M28HC256-70
Symbol
Parameter
t
'wc
t AS
Write Cycle Time
tAH
Address Hold Time (see note 1)
tcs
tCH
tcw
CE Pulse Width (note 2)
tOES
tOEH
twp
Max.
Min.
Max.
E/M28HC256-120
Min.
~I\
10
IV
Max.
Units
IV
iriS
."
0
0
0
ns
50
50
50
ns
Write Set-up Time
0
0
0
ns
Write Hold Time
0
0
0
ns
50
50
50
ns
OE High Set-up Time
0
0
0
ns
OE High Hold Time
0
0
0
ns
WE Pulse Width (note 2)
50
50
50
ns
tos
Data Set-up Time
40
40
40
ns
tOH
t BlC
Data Hold Time
0
0
0
t lP
Address Set-up Time
Min.
E/M28HC256-90
Byte Load Timer Cycle
(Page Mode Only) (note 3)
Last Byte Loaded
to DATA Polling Output
0.2
200
70
0.2
200
0.2
90
ns
200
Jls
120
ns
Byte Write Timing
WE CONTROLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 10 nsec write pulse will not activate a write cycle.
3. lac min. is the minimum time before the next byte can be loaded. lac max. is the minimum time the byte load timer waits before initiating
internal write cycle.
seeQ
MD4000821A
Technology, Incorporated
6-80
EIM28HC256
PRELIMINARY DATA SHEET
Page Write Timing/ WE Controlled
~----------------------PAGELOAD----------------~~--
'I
WE
DATA
HIGHZ
>-I~--«
Hardware Chip Erase
VIH
"
CE
~
VIL
tELWL
I
..
..
.. tWHOH ..
VIH
tOHEL
~
tWLWH
\
VIL
/
---v_________________________________________________________
DON'T CARE
V--
ADDRESSES~
seeQ
MD4000821A
~
\
tOVHWL
WE
DATAl
\
.. tWHEH--.
VH
VIH
I
~
Technology, Incorporated
6-81
EIM28HC256
PRELIMINARY DATA SHEET
Hardware Chip Erase
Parameter
Description
t ELWL
Chip Enable Setup Time
Min.
5
Il s
tOVHEL
t WLWH
Output Enable Setup Time
5
Write Enable Pulse Width
10
Il s
ms
tWHEH
t WHOH
Chip Enable Hold Time
5
Output Enable Hold Time
5
tOHEL
VH
Erase Recovery Time
High Voltage
Max.
Units
Il s
Ils
10.8
50
ms
13.2
V
Ordering Information
D
M 28HC256 - 70
IB
~~_T_
PACKAGE
TYPE
TEMPERATURE
RANGE
D = CERAMIC DIP
L=LCC
F =FLATPACK
T=PGA
seeQ
MD4000821A
M = -55°C to + 125°C
PART TYPE
32K x 8 EEPROM
(MILITARY)
E = -40°C to +85°C
(EXTENDED)
ACCESS TIME
70 = 70 ns
120 = 120 ns
Technology, Incorporated
6-82
SCREENING OPTION
MIL 883 CLASS B
SCREENED
seeQ
EIM36C16
EIM36C32
High Speed CMOS Electrically Erasable PROM
October 1989
Features
Description
•
SEEQ's E/M36C16/32 are high speed 2K x 8/4K x 8 Electrically Erasable Programmable Read Only Memories,
manufactured using SEEQ's advanced 1.25 micron
CMOS process.
•
••
•
•
•
•
•
•
•
•
•
Military and Extended Temperature Range
• -55°C to +125°C Operation (Military)
• -40°C to +85°C Operation (Extended)
High Speed:
• 45 ns Maximum Access Time
CMOS Technology
Low Power:
·400mW
10 Year Data Retention
High Output Drive
• Sink 16 mA at 0.45 V
• Source 4 mA at 2.4 V
5V ±10% Power Supply
Power Up/Down Protection Circuitry
Fast Byte Write
.5mslByte
Automatic Byte Clear Before Write
JEDEC Approved PROM Pinout
Direct Replacement for Bipolar PROMS
Slim 300 mil Packaging A val/able
The 36C16/32 are intended as bipolar PROM replacements in high speed applications. The 45 ns maximum
read access time meets the requirements of many of
today's high performance processors. The endurance,
the number of times the part can be erased/written, is
specified to be greater than 100 cycles. The 36C16/32 are
built using SEEQ's proprietary oxynitride EEPROM process and its innovative Q Cell™ design.
Data retention is specified to be greater than 10 years.
Block Diagram
31
c)
ROW
DECODERS
"
E2
MEMORY
ARRAY
Pin Configuration
LEADLESS CHIP CARRIER
BOTTOM VIEW
DUAL-IN-LiNE
TOP VIEW
36C16/36C32
(24 pins)
A ,O
CS,
3q
------
COLUMN
ADDRESS
GATING
COLUMN
DECODER
--ERASE
CONTROL
LOGIC
--WRITE
_ _ READ
110
BUFFER
.I.
CS31Al1[41
V
1100_7
cS2
Pin Names
1107
Ao-A3
ADDRESSES -
COLUMN
A4 -A 1 PI
ADDRESSES -
ROW
CS1
CS 2
NOTES:
1. Pin 19 is A'l on the 36C32.
2. CS3 is on the 36C16 only.
3. A4 - A,o on 36C16.
4. Pin 23 is CS3 on 36C16 and is A11 on 36C32.
MD400028/C
CHIP SELECT INPUTS
CS3
1/00 _7
Q Cell is a trademark of SEEQ Technology, Inc.
seeQ
i>
Technology, Incorporated
6-83
DATA INPUT (WRITE)
DATA OUTPUT (READ)
EIM36C16136C32
Device Operation
Operational Modes
CS1
MODE PIN
Read
VIL
VIH
f----.-
X
X
Standby
V
Write
(1)
H
CSz
VIH
CSpl
VIH
DOUT
X
VIL
X
X
High Z
X
VIL
VIL
X
1/0
DIN
X: Any TIL level
The 36C16132 are available in 24 pin Slim 300 mil
CERAMIC DIP, and 28 pin LCC. Full featured EEPROM
versions are also available (38C16132) in 24128 pin DIP
and 32 pin surface mount packages.
Read
A read is started by presenting the addresses of the
desired byte to the address inputs. Once the address is
stable, the chip select inputs should be brought to the
proper levels in order to enable the outputs. (see Table
above.)
Write
To write into a particular location, addresses and data
must be valid, CS2 must be TTL low and a ViI] pulse has
to be applied to CS I for 5ms. An automatic internal byte
clear is done prior to the byte write. The byte clear feature
is transparent to the user.
NOTES:
1. V - High Voltage.
2.
3 applies only to the 38C16. This pin because A11 in the 36C32.
dS
seeQ
MD4000281C
Technology, Incorporated
6-84
EIM36C16136C32
Absolute Maximum Range
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature
Storage ............................................ -65°C to +150°C
Under Bias ........................................ -65°C to +135°C
AI/Inputs and Outputs
with Respect to Ground ................... -3 V to +7 V D. C.
CSt with Respect to Ground ...... -0.5 V to + 14 V D.C.
Recommended Operating Conditions
E36C16
E36C32
I Vee Supply Voltage
I Temperature Range (Read Operation)
DC Operating Characteristics
M36C16
M36C32
SV± 10%
SV± 10%
(Ambient) -40°C to +SsoC
(Case) -SsoC to + 12SoC
(Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol
Parameter
Icc
Vee Active Current
liN
Input Leakage Current
lOUT
V IL
VIH
Output Leakage Current
VH
Input High Voltage During
Write/Chip Erase
VOL
VOH
I [1](2)
Output Low Voltage
V
Input Undershoot Voltage
os
el
(2)
Input Low Voltage
Input High Voltage
Min.
Max.
Units
SO
rnA
CS2 = CS3 =VIH : CS1 = VIL ;
Address Inputs = 20 MHz
I/O = OmA
1
IlA
0.1 V > = VIN <
10
VOUT = Vee Max.
O.S
IlA
V
2
Vee + 1.S
V
10.S
13.2
V
For CS1 Input Only
V
10L = 16 rnA, Vee
Output High Voltage
2.4
V
10H = -4 rnA, Vee
Output Short Circuit Current
-20
rnA
-3
V
0.4S
1. Only one input at a time for less than one second.
2. Characterized. Not tested.
MD4000281C
=Vee Max.
-O.S
NOTES:
seeQ
Test Condition
Technology, Incorporated
6-85
=Vee Min.
= Vee Min.
Vee = Vee Max,
VOUT = 0
VIN Undershoot Pulse Width < 10 ns
EIM36C16136C32
A.C. Test Conditions
Capacitance {1} TA =25°C, f = 1 MHz
Symbol
Parameter
Max
Conditions
C IN
Input Capacitance
6 pF
VIN
C OUT
Data (1/0) Capacitance 12 pF
VIIO
Output Load: 10 TTL gate and total CL = 30 pF
Input Rise and Fall Times: < 5 ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level:
Inputs 1.5 V
Outputs 1.5 V
=0 V
=0 V
E.S.D. Characteristics
Symbol
V ZAP [2J
Parameter
E.S.D. Tolerance
3.0V
>2000 V.
~""'10%
10%....,r-
GND
MIL-STD883
Test Method 3015
..... .-- 90%
r-90%
1
Test Conditions
Value
~
~
INPUT PULSES
~5ns---
4-~5ns
AC Characteristics
Read Operation (Over operating temperature and Vcc Range, unless otherwise specified)
Limits
E/M36C16-45
E/M36C32-45
Symbol
Parameter
Min.
t RC
Read Cycle Time
45
tCE
Chip Select Access Time
tAA
Address Access Time
45
tOF
Output Enable to Output
not being Driven
25
tOH
Max.
E/M36C16-55
E/M36C32-55
E/M36C16-70
E/M36C32-70
Min.
Min.
-cS
1
CS 2
CS 3
ns
55
70
ns
30
35
ns
0
ADDRESSES VALID
ns
~~
/~
~li\
~k'
,~
~r-
/
1\
J~ICE~
~ID~
__.IOH
//11/
\\\1\
VO _
O7
ns
.
IRC
~~
45
70
0
0
/\
Units
35
Read Cycle Timing
ADDRESSES
Max.
55
30
Output Hold from Address
Change or Chip Select
whichever occurs first
Max.
VALID OUTPUT
.-
\\\.1 ,-NOTE3
//11 NOTE 3
~IAA-----
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not tested.
3. Transition is measured at steady state level-Q.5 V or steady state low level +0.5 V on the output from the 1.5 V level on the input.
-
seeQ
MD4000281C
Technology, Incorporated
6-86
EIM36C16136C32
AC Characteristics Write Operation (All Speeds)
=25° ± 5°C, unless otherwise specified)
(Over Vcc Range, TA
36C16
36C32
Symbol
Parameter
Min.
Max.
Units
lwp
Write Pulse Width
5
50
ms
t AS
Address Set-up Time
0
lIs
tAH
Address Hold Time
0.5
lIs
tcs
CS 2 Set-up Time
0
lIs
tCH
CS 2 Hold Time
0
lIS
tos
Data Set-up Time
0
lIs
tOH
Data Hold Time
0
tWR
Write Recovery
lIS
10
lIs
Write Cycle Timing
ADDRESSES VALID
ADDRESSES
V H MIN_
6.5V_
V1H - - - - - - o f l
V1L
-----.1
tDS
V°0-7
DATA OUT
DATA IN
.,..1------- WRITE CYCLE - - - - - - - I..... ~
1i00i
NOTE:
1. CS3 is A, 1 on 36C32.
seeQ
MD4000281C
Technology, Incorporated
6-87
READ CYCLE
EIM36C16136C32
Ordering Information
D
D
M 36C16 -45
M 36C32-45
TT--r-T
PACKAGE
TYPE
D -SLIM
CERAMIC DIP
L-LCC
2~
TEMPERATURE
RANGE
M _ -55°C to +125°C
(MILITARY)
E _ -40°C to +85°C
(EXTENDED)
/8
/8
L
PART TYPE
36C16 - 2K x 8 EEPROM
36C32 - 4K x 8 EEPROM
ACCESS TIME
45 - 45 ns
55 - 55 ns
70-70ns
SCREENING OPTION
IB - MIL 883 CLASS B
SCREENED
The "Preliminary Data Sheet" designation on a SEEO data sheet indicates that the product is not fully characterized. The specifications
are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. SEEO Technology or an
authorized sales representative should be consulted for current information before using this product. No responsibility is assumed by
SEEO for its use, nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. SEEO reserves
the right to make changes in specifications at any time and without notice.
seeQ
MD4000281C
Technology, Incorporated
6-88
seeQ
EIM38C16
EIM38C32
High Speed CMOS Electrically Erasable PROM
October 1989
PRELIMINARY DATA SHEET
Features
•
Military and Extended Temperature Range
.-55°Cto +125°C Operation (Military)
• -40° C to +85°C Operation (Extended)
•
High Speed:
• 45 ns Maximum Access Time
•
•
CMOS Technology
Low Power:
• 400mW
High Endurance:
• 10,000 Cycles/Byte Minimum
• 10 Year Data Retention
On-Chip Timer and Latches
• Automatic Byte Erase Before Write
• Fast Byte Write: 5 mS/Byte
•
•
•
•
•
•
•
•
High Speed Address/Data Latching
50 ms Chip Erase
5V ±10% Power Supply
Power Up/Down Protection Circuitry
DATA Polling of Data Bit 7
JEDEC Approved PROM Pinout
• 38C16: 2816A Pin Compatible
• 38C32: 28C64 Pin Compatible
Description
SEEQ's ElM38C16/32 are high speed 2K x 8/4K x 8 Electrically Erasable Programmable Read Only Memories
(EEPROM), manufactured using SEEQ's advanced 1.25
micron CMOS process.
Pin Configuration
38C16
(24 pins)
DUAL-IN-LiNE
TOP VIEW
Pin Names
38C32
(28 pins)
'k:c
AS
As
A3
WE
A6
OE
AS
A2
A,
7
1107
AO
110 0
110 6
Ao-A3
A4 -A11 [1]
ADDRESSES - COLUMN
CE
CHIP ENABLE
ROW ADDRESSES
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1100 •7
DATA INPUT (WRITE)
DATA OUTPUT (READ)
A,
Block Diagram
GND
LEADLESS CHIP CARRIER
BOTTOM VIEW
38C16
38C32
CE
DE
NOTES:
1. A4 - A,o on 38C16.
2. NC - No connect.
seeQ
MD400030/C
Technology, Incorporated
6-89
Il00·7
EIM38C16138C32
PRELIMINARY DATA SHEET
read cycle. The output drivers are made active by bringing
output enable (OE) to a TTL low. During read, the address,
eE, OE, and 110 latches are transparent.
The EIM38C16132 are ideal for high speed applications
which require non-volatility and in-system reprogrammability. The endurance, the number of times a byte may be
written, is specified to be greater than 10,000 cycles per
byte minimum. The high endurance is accomplished using
SEEQ's propietary oxyntride EEPROM process and its
innovative Q CelfTM design. System reliability in applica-
Write
To write into a particular location, addresses must be valid
and a TTL low is applied to the write enable (WE) pin of a
selected (CE low) device. This initiates a write cycle.
During a write cycle, all inputs except for data are latched
on the falling edge of WE (or eE, whichever one occurred
last). Write enable needs to be at a TTL low only for the
specified twp time. Data is latched on the rising edge of WE
(or eE, which ever one occurred first). An automatic byte
erase is performed before data is written.
tions where writes are frequent is increased because of the
low endurance-failure rate of the Q Cell. The 45 ns maximum access time meets the requirements of many of
today's high performance processors. The ElM38C16132
have an internal timer which automatically times out the
write time. The on-chip timer, along with the input latches,
frees the microprocessor for other tasks during the write
time. DATA Polling can be used to determine the end of a
write cycle. All inputs are TTL compatible for both write and
read modes.
DA TA Polling
The EEPROM has a specified twe write cycle time of 5ms.
The typical device has a write cycle time faster than the
twe . DATA polling is a method to indicate the completion of
a timed write cycle. During the internal write cycle, the
complement of the data bit 7 is presented at output 7 when
a read is performed. Once the write cycle is finished, the
true data is presented at the outputs. A software routine
can be used to HpollH, i.e. read the outputs, for true or
complemented data bit 7. The polling cycle specifications
are the same as for a read cycle. During data polling, the
addresses are don't care.
Device Operation
Operational Modes
MODE PIN
CE
OE
WE
1/0
Read
VIL
VIH
DOUT
Standby
VIH
VIL
VIL
X
Write
Write
Inhibit
X
VIH
X
VIL
Chip Erase[1]
X:
VIH
VIH
X
X
VIL
VIL
V
[2]
H
X
VIL
High Z
VIH
X
VIH
VIL
High ZlDoUT
High Z
High ZlDoUT
No Operation
(HighZ)
High Z
VIH
DIN
Chip Erase
Certain applications may require all bytes to be erased
simultaneously. This feature, which requires high voltage,
is optional and timing specifications are available from
SEEQ.
Any TIL level
Data retention is specified to be greater than 10 years.
Power Up/Down Considerations
The EIM38C16 is available in 24 pin CERAMIC DIP; the EI
M38C32 in 28 pin CERAMIC DIP; 32 pad LCC package
versions are also available. 24 pin versions of both EI
M38C16 and EIM38C32 intended for bipolar PROM replacement are also available (36C16136C32). Allparts are
available in commercial as well as military temperature
ranges.
Protection against false write during Vee power up/down
is provided through on chip circuitry. Writing is prevented
under anyone of the following conditions:
1. Vee is less than VWI V.
_
2. A high to low Write Enable (WE) transition has not
occurred when the Vee supply is between VWI V and
Vec with eE low and OE high.
Read
A read is started by presenting the addresses of the
desired byte to the address inputs. Once the address is
stable, OE is brought to a TTL low in order to enable the
chip. The WE pin must be at a TTL high during the entire
Writing will also be inhibited when WE, eE, or OE are in
TTL logical states other than those specified for a byte
write in the Mode Selection table.
NOTES:
1. Chip erase is an optional mode.
2. VH - High Voltage.
a Cell is a trademark of SEEO Technology, Inc.
seeQ
MD400030lC
Technology, Incorporated
6-90
EIM38C16138C32
PRELIMINARY DATA SHEET
COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Range
Temperature
Storage ................................................ - 6SOC to +15(J'C
Under Bias ........................................... -6SOC to +13SOC
AI/Inputs and Outputs
with Respect to Ground ...................... -3 V to +7 V D.C.
Recommended Operating Conditions
M38C16
M38C32
E38C16
E38C32
I Vee Supply Voltage
I Temperature Range
5V± 10%
5V±10%
(Ambient) -40 °C to 85°C
(Case) -55°C to 125°C
Endurance and Data Retention
Condition
Symbol
Parameter
Value
Units
N
Minimum Endurance
10,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
DC Characteristics
(Over operating temperature and Vee range, unless otherwise specified)
Limits
Parameter
Max.
Units
lee
Vee Active Current
80
rnA
CE = OE =Vll;
Address Inputs = 20 MHz
I/O = 0 rnA
ISB
Stand by Vee Current
40
rnA
CE = VIH ;
All I/O Open;
All Other Inputs TTL don't care;
liN
Input Leakage Current
lOUT
Output Leakage Current
Vll
Input Low Voltage
Min.
Test Condition
Symbol
1
~A
0.1 V? VIN =:; Vee Max.
10
~A
VOUT = Vee Max.
-0.5
0.8
V
2
Vee + 1.5
V
0.45
V
IOl = 2.1 rnA, Vee = Vee Min.
IOH = -400 !lA, Vee Min.
V IH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
V
VWI III
Write Inhibit Voltage
3.8
V
V
Input Undershoot Voltage
-3
V
el
(1)
NOTES:
1. Characterized. Not tested.
seeQ
MD400030/C
Technology, Incorporated
6-91
VIN Undershoot Pulse Width < 10 ns
EIM38C16138C32
PRELIMINARY DATA SHEET
A.C. Test Conditions
Capacitance 11} T" =25°C, f .. 1 MHz
Symbol Parameter
Max
Conditions
CIN
Input Capacitance
6 pF
VIN = 0 V
COUT
Data (I/O) Capacitance 12 pF
Output Load: 1 TTL gate and total CL = 30 pF
Input Rise and Fall Times: < 5 ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level:
Inputs 1.5 V
Outputs 1.5 V
VI/O = 0 V
E.S.D. Characteristics
3.0V
Symbol Parameter
Value
Test Conditions
VZ"p(2)
>2000 V
MIL-STD 883
Test Method 3015.3
E.S.D. Tolerance
----lr-----~I
GND~~OO%
~~
INPUT PULSES
AC Characteristics
Read Operation (Over operating temperature and Vcc Range, unless otherwise specified)
Limits
ElM38C16-35
ElM38C32-35
ElM38C16-40 ElM38C16-45
ElM38C32-40 ElM38C32-45
Parameter
Min.
Min.
t RC
Read Cycle Time
45
ns
CE =OE =VIL
tCE
Chip Enable Access Time
30
35
45
ns
OE = VIL
Address Access Time
45
55
70
ns
CE =OE = VIL
Output Enable Access Time
25
30
40
ns
CE = VIL
tOF
Output or Chip Enable
to Output not being Driven
25
30
35
ns
CE = VIL
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, Which ever occurs first
ns
CE orOE
Symbol
t""
tOE
Max.
0
0
I~
0
Test
Conditions
=V IL
..
lAC
~~
Max. Units
Min.
70
55
Read Cycle Timing
ADDRESSES
Max.
ADDRESSES VALID
~~
/~
CE
~r
If
\~'---I-oe---..1I'i4-H'OF'"
ICEf4--~
IOH
-+-__+/L+-~HV
~\~r- NOTE 3
VOO_7 _ _ _ _ _
\\\~
VALID OUTPUT
/ /
hi- NOTE 3
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which affect capacitance.
2. Characterized. Not tested.
3. Transition is measured at steady state level- 0.5 V or steady state low level + 5.0 V on the output from the 1.5 V level on the input.
'-- SeeQ Technology, Incorporated
MD400030/C
6-92
EIM38C16138C32
PRELIMINARY DATA SHEET
AC Characteristics Write Operation
(Over the operating temperature and Vcc Range, unless otherwise specified)
ElM38C16-45
ElM38C32-45
Symbol
Parameter
twc
t AS
Write Cycle Time
Min.
tAH
ElM38C16-55
ElM38C32-55
Max.
Min.
Max.
5
ElM38C16-70
ElM38C32-70
Min.
5
Max.
Units
5
ms
0
0
0
ns
Address Hold Time
25
30
40
ns
tcs
Write Set-up Time
0
0
0
ns
tCH
Write Hold Time
0
0
0
ns
tcw
CE Pulse Width
25
30
40
ns
tOEs
OE High Set-up Time
5
5
5
ns
tOEH
OE High Hold Time
0
0
0
ns
twp
WE Pulse Width
25
30
40
ns
tos
Data Set-up Time
25
30
40
ns
tOH
Data Hold Time
0
0
0
top
Time to DATA Polling
from Byte Latch
Address Set-up Time
45
55
ns
70
Write Cycle Timing
WE CONTROLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
DATA
r;:===,:B~YT~E:::::W~RIT~E=~rl=~"I~'~,--!-POLLlNG~
I~J;:-'
ADDRESSES
ADDRESSES
I~WP
DATA
HIGHZ
--=:..:---~
lOS
IDH--J
DATAIN
-~
~r---ISIJ---
DATA--~~-~
NOTES
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
seeQ
MD400030/C
Technology, Incorporated
6-93
ns
EIM38C16138C32
PRELIMINARY DATA SHEET
Ordering Information
o
o
M
M
38C16
38C32
...-----_ _ _----'T T T
~
PACKAGE
TYPE
D - CERAMIC DIP
L- LCC
-45
-45
T
IB
IB
TL.-_~~_
r-------'I ~ ,---I_ - . . ,
TEMPERATURE
RANGE
M - -55OC to + 1250C
(MILITARY)
E - -40°C to +85°C
(EXTENDED)
PART TYPE
ACCESS TIME
38C16 - 2K x 8 EEPROM
38C32 - 4K x 8 EEPROM
45 - 45 ns
55-55ns
70-70ns
_____,
SCREENING OPTION
I8-MIL 883 CLASS B
SCREENED
The "Preliminary Data Sheet" designation on a SEEQ data sheet indicates that the product is not fully characterized. The specifications
are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. SEEQ Technology or an
authorized sales representative should be consulted for current information before using this product. No responsibility is assumed by
SEEQ for its use, nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. SEEQ reserves
the right to make changes in specifications at any time and without notice.
seeQ
MD400030/C
Technology, Incorporated
6-94
seeQ
MODULES M28C010
Timer E2
1024K Electrically Erasable PROM
October 1989
Description
Features
SEEQ's MM28C010 is a CMOS 5Vonly, 128K x 8 Electrically Erasable Programmable Read Only Memory
(EEPROM). The MM28C01 0 consists of 4 28C256 (32K
x 8) CMOS EEPROMs and a 2 to 4 line decoder in LCC
packages, mounted on and interconnected on a ceramic
substrate. The MM28C01 0 is available in a 32 pin module
package and is ideal for applications which require low
power consumption, non-volatility and in-system reprogrammability.
•
CMOS Technology
•
Military Temperature Range
•
Low Power Operation
• 70 mA Active Curent
·2 mA Standby Current
•
On-Chip Timer
• Automatic Erase Before Write
•
64 Byte Page Mode. . • Fast Effective
Write Time
• 80 pSBC A verage Byte Write Time
Pin Names
•
Write Cycle Completion Indication
• Data Polling
•
SV:t 10% Power Supply
Ao-A16
CE
•
Power Up/Power Down Protection Circuitry
OE
OUTPUT ENABLE
•
JEDEC Approved Byte Wide Pinout
WE
WRITE ENABLE
1/°0•7
DATA INPUT (WRITE)/DATA
OUTPUT (READ)
ADDRESSES
CHIP ENABLE
Block Diagram
AO·A16
ADDRESS
AO·A16
...l\.
-v ,
I
"'
AO.~14
"'
~
Pin Configuration
0
NC
WE
A
0 OE
~
-OE
---..
AO·A14
000 0 000
g
~
~
-WE
WE
AO·A14
~DOODDOoc::l
A
c::l
0
16
15
A12
A15
-
SEL1
A 1 6 _ SEL2
CE
EN
0
1
f
eEl
1/°0.7
CE2
,
2
3
CE4
CE3
ID DUUIIUL U 0
2T04
DECODER
-WE
DATA
1/°0.7
J...
-v
, "'
1/00-7
seeQ
MD400044/B
~
~ -WE
-
g
g
CE '----
I
~D
Oe
L.l
t
1/°0.7
Technology, Incorporated
6-95
D
=
I
1
....
1/°0-7
:(
Vcc
WE
NC
A14
A7
A
A6
AS
A5
Ag
13
0
<
~
A4
All
A3
DE
g
~
g
AO
1/°7
0
11°0
IIOS
1/°1
VO S
1/00-7
11°2
1/°4
Vss
1/°3
A2
AlO
Al
eE
MM28C010
The MM28CO 10 has an internal timer which automatically
times out the write time. The on-chip timer, along with input
latches, frees the microprocessor for other tasks during
the write time. The MM28CO 1O's write cycle time is 10 ms
maximum. An automatic erase is performed before a
write. The Data Polling feature of the MM28C01 0 can be
used to determine the end of a write cycie. Data retention
is greater than 10 years.
Write enable needs to be at a TTL low only for the
specified twp time. Data is latched on the rising edge of
WE (or CE whichever occurred first). An automatic erase
is performed before data is written.
Device Operation
For system design simplification, the MM28C010 is designed such that either the CE orWE pin can be used to
initiate a write cycle. The device uses the latest high-to-Iow
transition of either CE or WE signal to latch the data. Address and OE set up and hold are with respect to the later
of CE orWE; data setup and hold is with respect to the
earlier of WE or CEo
The MM28C010 can write both bytes and blocks of up to
64 bytes. The wiite mode is discussed below.
Write Cycle Control Pins
Operational Modes
There are four operational modes (see Table 1); only TTL
inputs are required. Write can only be initiated under the
conditions shown. Any other conditions for CE, OE, and
WE will inhibit writing and the I/O lines will either be in a
high impedance state or have data, depending on the state
of the forementioned three input lines.
Mode Selection
(Table 1)
Mode Pin
CE
OE
WE
Read
VIL
VIH
VIL
X
VIH
X
VIL
X
VIH
X
X
VIL
VIH
X
VIL
VIH
X
X
Standby
Write
Write
Inhibit
To simplify the following discussion, the WE pin is used as
the control pin throughout the rest of this document.
Timing diagrams ofboth write cycles are included in the AC
characteristics.
1/0
Write Mode
DOUT
HighZ
One to 64 bytes of data can be loaded randomly into the
MM28C010. Address lines A 15 and A 16 must be held
valid during the entire page load cycle. The part latches
row addresses,A6-A 14 during the first byte write. These
addresses are latched on the falling edge of WE signal
(assuming WE control write cycle) and are ignored after
that until the end of the write cycle. This will eliminate any
false write into another page if different row addresses are
applied and the page boundary is crossed.
DIN
High Z or Dovr
High Z
High Z or Dovr
X: any CMOsnTL level
Reads
A read is typically accomplished by presenting the ad-
The column addresses, AO-A5, which are used to write into
different locations of the page, are latched every time a
new write is initiated. These addresses along with OE
state (high) are latched on the falling edge of WE signal.
For proper write initiation and latching, the WE pin has to
stay low for a minimum of twp ns. Data is latched on the
rising edge of WE, allowing easy microprocessor interface.
dresses of the desired byte to the address inputs. Once
the address is stable, CE is brought to a TTL low in order
to enable the chip. The WE pin must be at a TTL high
during the entire read cycle. The output drivers are made
active by bringing output enable (OE) to a TTL low. During
read, the addresses, CE, OE, and input data latches are
transparent.
Upon a low to high WE transition, the MM28CO 10 latches
data and starts the internal page loader timer. The timer is
reset on the falling edge of the WE signal if a write is
initiated before the timer has timed out. The timer stays
reset while the WE pin is kept low. If no more write cycles
have been initiated in (tBLd after the last WE low to high
transition, the part terminates the page load cycle and
starts the internal write. During this time, which takes a
Writes
To write into a particular location, the addresses must be
valid and a TTL low is applied to the write enable (WE) pin
of a selected (CE low) device. This combined with output
enable (OE) being high, initiates a write cycle. During a
byte write cycle, all inputs except data are latched on the
falling edge of WE (or CE, whichever one occurred last).
seeQ
MD4000441B
Technology, Incorporated
6-96
MM28C010
point of a write cycle. If a read is performed to any address
while the MM28CO 10 is still writing, the device will present
the Ones-complement of the last data byte written. When
the MM28C01 0 has completed its write cycle, a read from
the last address written will result in valid data. Thus,
software can simply read from the part until the last data
byte written is read correctly. A DATA polling read should
not be done until a minimum of tLP microseconds after the
last byte is written. Timing for a DATA polling read is the
same as a normal read once the tLP specification has been
met.
maximum of 10 ms, the device ignores any additional load
attempts. The part can be now read to determine the end
of write cycle (DATA polling). A 160Jlsmaximumeffective
byte write time can be achieved if the page is fully utilized.
Extended Page Load
In order to take advantage of the page mode's faster
average byte write time, data must be loaded at the page
load cycle time, (tsLe). Since some applications may not
be able to sustain transfers at this minimum rate, the
MM28C010 permits an extended page load cycle. To do
this, the write cycle must be 'stretched' by maintaining WE
low, assuming a write enable controlled cycle, and leaving
all other control inputs (GE, OE) in the proper page load
cycle state. Since the page load timer is reset on the falling
edge of WE, keeping this signal low will inhibit the page
load timer. When WE returns high, the input data is latched
and the page load cycle timer begins. In CE controlled
write the same is true, with GE holding the timer reset
instead of WE.
Power Up/Down Considerations
There is internal circuitry to minimize a false write during
Vee power up or power down. This circuitry prevents
writing under anyone of the following conditions:
1. Vee is less than VW/ V.
2. A high to low Write Enable (WE) transition has not
occurred when the Vee supply is between VWI V and
Vee with GE low and OE high.
Data Polling
The MM28CO 10 has a maximum write cycle time of 10 ms.
Typically though, a write will be completed in less than the
specified maximum cycle time. DATA polling is a method
of minimizing write times by determining the actual end
seeQ
MD4000441B
Writing will also be inhibited when WE, GE, or OE are in
TTL logical states other than that specified for a byte write
in the Mode Selection table.
Technology, Incorporated
6-97
MM28C010
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
Absolute Maximum Stress Range'"
Temperature
Storag9 .............................................. -65°C to +150°C
Under Bias ......................................... -65°C to + 135°C
not implied. Exposure to absoiuie maximum rating condi-
AI/Input or Output Voltages
witth Respect to Vss ............................ + 6 V to - O.5V
tions for extended periods may affect device reliability.
Recommended Operating Conditions
MM28C010
Temperature Range
-55°C to + 125°C
(case temp.)
5V ± 10%
Vee Power Supply
Endurance and Data Retention
Symbol
Parameter
Value
Units
N
K
Minimum Endurance(4]
10,000
1,000
Cycles/Byte
MIL-STD 883 Test
Method 1033
TOR
Data Retention
>10
Years
MIL-STD 883 Test
Method 1008
DC Characteristics
Condition
Read Operation (Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol
Parameter
Max.
Units
lee
Active Vee Current
70
rnA
CE = OE = V 1L; All 1/0
Addr = 5 MHz
1581
Standby Vee Current
(TTL Inputs)
10
rnA
CE
1582
Standby Vee Current
(CMOS Inputs)
2
rnA
CE = Vee -02;
A15, A16 = Vee -0.2
Other Inputs = V 1H
All 1/0 = 0 rna
I (2]
IL
I i3]
OL
V 1L
Input Leakage Current
5
flA
V 1N
Output Leakage Current
25
flA
VOUT
Input Low Voltage
-0.3
0.8
V
V 1H
Input High Voltage
2.0
6
V
VOL
V OH
Output Low Voltage
0.45
VW1
(I]
Min.
MD4000441B
= Vee Max.
= Vee Max.
V
IOL = 2.1 rnA
2.4
V
IOH
Write Inhibit Voltage
3.8
V
Technology, Incorporated
6-98
= 0 rna;
=V 1H, OE =V 1L; All 1/0 = 0 rna;
Output High Voltage
NOTES:
1 . Charaeterized. Not tested.
2. Inputs only. Does not include flO.
3. For flO only.
4. Endurance can be specified as an option to be 1000 or 10000 cye/es/byte minimum.
seeQ
Test Condition
= -400 IJA
MM28C010
Capacitance [1]
TA = 25°C, t = 1 MHz
Symbol
Parameter
C IN
30 pF
Data (1/0) Capacitance 40 pF
Max.
C OUT
A.C. TestCondiUons
Conditions
Input Capacitance
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V
V IN = OV
VI/0 = OV
E.S.D. CharacterisUcs
Symbol
VZAP
[2]
Parameter
Value
E.S.D. Tolerance
>1000 V. M,L-STD 883
Test Conditions
Test Method 3015
AC Characteristics
Read Operation (Over operating temperature and Vee range, unless otherwise specified)
Limits
MM28C010-250 MM28C010-300
Symbol
Parameter
Min.
Max.
t RC
Read Cycle Time
250
tCE
Chip Enable Access Time
250
300
tAA
Address Access Time
300
tOE
Output Enable Access Time
250
150
tOF
Output or Chip Enable High to
Output in Hi-Z
0
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
Min.
Max.
300
60
0
0
MM28C010-350
Min.
Max.
350
150
80
350
350
0
0
Units
Test
Conditions
ns
CE = OE =VIL
ns
150
ns
OE = V IL
CE = OE = V IL
CE = V IL
80
ns'
CE = V IL
ns
CE
ns
= OE =VIL
Read IDATA Polling Cycle
t4-----tRC----...-t
ADDRESSES
ADDRESSES A N
HIGHZ
DATA-----+--------<
NOTES:
1. This parameter is measured only for the initial qual~ication and after process or design changes which may affect capacitance.
2. Characterized. Not tested.
seeQ
MD4000441B
Technology, Incorporated
6-99
MM28C010
AC Characteristics
Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
MM28C010-250
MM28C010-300
Parameter
twc
t AS
Write Cycle Time
Address Set-up Time
20
20
20
ns
150
150
150
ns
Min.
Max.
Min.
MM28C010-350
Symbol
10
Max.
Min.
10
Max.
Units
10
ms
tAH
Address Hold Time (see note 1)
tcs
Write Set-up Time
0
0
0
ns
tCH
Write Hold Time
0
0
0
ns
tcw
CE Pulse Width (see note 2)
150
150
150
ns
tOES
OE High Set·up Time
20
20
20
ns
tOEH
twp
OE High Hold Time
20
20
20
ns
WE Pulse Width (see note 2)
150
150
150
ns
tos
Data Set-up Time
50
50
50
ns
tOH
Data Hold Time
0
0
0
tBlC
Byte Load Timer Cycle
(Page Mode Only) (see note 3)
t lP
Last Byte Loaded
to DATA Polling
0.2
200
1
0.2
200
0.2
1
ns
200
~s
1
ms
Write Timing
WE CONTROLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. tat.c min. is the minimum time before the next byte can be loaded. k max. is the minimum time the byte load timer waits before initiating
internal write cycle.
seeQ
MD4000441B
Technology, Incorporated
6-100
MM28C010
Page Write Timing
~------------------------PAGELOAD------------------~4----
WE
DATA
HIGHZ
>-IJ----«
Ordering Information
PACKAGE
TYPE
M=MOOULE
seeQ
MD400044IB
TEMPERATURE
RANGE
M = -55°C to + 125°C
(MILITARY)
PART TYPE
ENDURANCE
ACCESS TIME
SCREENING OPTION
128 K x 8
EEPROM
K = 1000 CYCLES
N = 10000 CYCLES
250 = 250 ns
300 = 300 ns
350 = 350 ns
MILITARY PROCESSED
MODULE COMPONENTS
MIL 883 CLASS B
SCREENED
Technology, Incorporated
6-101
6-102
seeQ
EIM28 CO 10
1024K High Speed EEPROM
ADVANCED INFORMATION DATA SHEET
October 1989
Features
•
Military and Extended Temperature Ranges
• -55°C to + 125°C Operation (Military)
• -40°C to+85°C Operation (Extended)
•
Data Protection
• Hardware: Power Up/Down Protection Circuitry
• JEDEC-Approved Software Write Protection
•
High-Speed:
• 120 nsec Maximum Access Time
•
•
Low-Power CMOS Technology
• 120 mA Active Current
• 350 pA Standby Current
High Endurance
• 10,000 Program/Erase Cycles
• 10 Year Data Retention
•
5V:t 10% Power Supply
•
Fast Write Cycle Times
• 128 Byte Page Write Operation
• 10 ms Typical Byte/Page Write Time (28C010)
• 5 ms Typical Byte/Page Write Time (28C010H)
•
On-Chip Timer
• Automatic Clear before Write
•
End-ot-Wrlte Detection
• DATAPol/lng
• Toggle Bit
•
Software Accessible Control Register
• Disable Software Protection Mode
• Chip Clear
• Disable Automatic Clear Betore Write
•
CMOS & TTL Compatible I/O
•
Packages
• 32-pln Sidebraze, 32-Lead Flatpack
• 44-padLCC
Pin Configuration
LEAD LESS CHIP CARRIER
TOP VIEW
DUAL-IN-LlNE,
TOP VIEW
Block Diagram
E2
MEMORY
ARRAY
Pin Names
Ce
We
Ao-A6
A7 -A16
ADDRESSES-COLUMN
CE
CHIP ENABLE
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00 _7
DATA INPUT (WRITE)/DATA
OUTPUT (READ)
NC
NO CONNECT
VO O-7
seeQ
MD400085/A
Technology, Incorporated
6-103
ADDRESSES-ROW
EIM28C010
ADVANCED INFORMATION DATA SHEET
Description
The SEEO 28CO 10 is a high-performance 5 Vonly, 128K
x 8 Electrically Erasable Programmable Read Only
Memory (EEPROM). It is manufactured using SEEO's
advanced 1.0 micron CMOS process and is available in
32-pin sidebraze, a 44-pad LCC and 32-lead ceramic
flatpack.. The 28C01 0 is ideal for high10
Years
MIL·STD 883 Test
Method 1008
DC Characteristics
Condition
Read Operation (Over operating temperature and Vee range, unless otherwise specified)
Limits
Symbol
Parameter
Icc
Active Vcc Current
Max.
Units
120
rnA
CE = OE =V ll: All I/O open;
Other Inputs =Vee Max.
Min. read or write cycle time
IS81
Standby Vcc Current
(TTL Inputs)
2
rnA
CE =VIH, OE =V Il; All I/O Open;
Other Inputs =VIH
IS82
Standby V cc Current
(CMOS Inputs)
350
~A
CE =Vee -0.3
Other Inputs =VIH
All I/O Open
I (2)
Il
(3)
IOl
V il
Input Leakage Current
1
~
VIN
Output Leakage Current
10
~A
VOUT
Input Low Voltage
-1.0
V IH
Input High Voltage
2.0
VOL
V OH
Output Low Voltage
V
10l =2.1 rnA
Output High Voltage
2.4
V
IOH
V WI
Write Inhibit Voltage
3.8
V
Min.
0.8
V
Vee + 1
0.4
V
Test Condition
= Vee Max.
= Vee Max.
=-400 ~A
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect it.
2. Inputs only. Does not include VO.
3. For 1/0 only.
seeQ
MD4000851A
Technology, Incorporated
6·108
EIM28C010
ADVANCED INFORMATION DATA SHEET
Capacitance (tl
TA = 25°C, f = 1 MHz
Symbol
Parameter
Max.
Conditions
A.C. Test Conditions
C IN
Input Capacitance
6 pF
VIN = OV
C OUT
Data (1/0) Capacitance 12 pF
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V
VI/o = OV
E.S.D. Characteristics
Symbol
Parameter
Value
V ZAP (1)
E.S.D. Tolerance
>2000 V. MIL-STD 883
Test Method 3015
Test Conditions
AC Characteristics
Read Operation (Over operating temperature and Vee range, unless otherwise specified)
Limits
ElM28C010·120
Symbol Parameter
Min.
t Re
Read Cycle Time
120
teE
Chip Enable Access Time
tAA
Address Access Time
tOE
Output Enable Access Time
tOF
Output or Chip Enable High to
output in Hi-Z
0
tOH
Output Hold from Address
Change, Chip Enable, or Output
Enable, whichever occurs first
0
Max.
ElM28C010·150
Min.
150
120
120
50
50
0
0
ElM28C010·200
Max. Min.
Max.
200
150
150
55
55
0
0
ElM28C010·250
Min. Max.
250
200
200
55
55
0
0
Test
Units Conditions
ns
250
250
55
55
ns
ns
ns
CE = OE = V 1L
CE = VIL
ns
CE = V IL
ns
CE = OE = V1L
Read IDATA Polling Cycle
1'4-----tRC-------I~
ADDRESSES
ADDRESSES AN
HIGHZ
DATA---------+------------~r<
NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect it
seeQ
MD4000851A
Technology, Incorporated
6-109
CE = OE =V1L
OE = VIL
EIM28C010
ADVANCED INFORMATION DATA SHEET
AC Characteristics
Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
E1M28C010-120
Symbol
Parameter
twc
Write Cycle Time
t AS
tAH
Min.
E1M28C010-25O
Min.
Min.
Max.
Max.
Max. Units
10
10
10
10
L"H" Family
5
5
5
5
Address Set-up Time
Address Hold Time (see note 1)
Write Set-up Time
tCH
tcw
Write Hold Time
CE Pulse Width (note 2)
OE High Set-up Time
tos
tOH
EIM28C010-200
Min.
! Standard Family
tcs
tOEs
tOEH
twp
Max.
E1M28C010-15O
OE High Hold Time
WE Pulse Width (note 2)
Data Set-up Time
tBLC
Data Hold Time
Byte Load Timer Cycle
(Page Mode Only) (note 3)
t LP
Last Byte Loaded
to DATA Polling Output
0
50
0
0
50
0
0
50
40
0
0.2
200
120
0
50
0
50
0
0
50
0
0
50
0
0
50
0
0
0
50
0
0
50
0
50
40
0
0.2
40
0
40
200
150
0.2
0
50
ns
ns
ns
ns
ns
ns
ns
ns
0
200
0.2
200
ma
ms
ns
ns
200
Il s
200
ns
Byte Write Timing
WE CONTROLLED WRITE CYCLE
CE CONTROLLED WRITE CYCLE
NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 10 nsec write pulse will not activate a write cycle.
3. tae min. is the minimum time before the next byte can be loaded. fate max. is the minimum time the byte load timer waits before initiating
internal write cycle.
seeQ
MD40008SIA
Technology, Incorporated
6-110
EIM28C010
ADVANCED INFORMATION DATA SHEET
Page Write Timing/ WE Controlled
~---------------------PAGELOAD----------------~~--
WE
DATA
HIGHZ
Hardware Chip Clear
VIH
"-
)~
VIL
tELWL
/
\
tOVHWL
.. tWHOH--.
VIH
\
WE
DATAl
----v
ADDRESSES~~
seeQ
MD4000851A
~
tWHEH
VH
VIH
\
tOHEL
..
~
tWLWH
--
VIL
J
'v--
DON'TeARE
_____________________________________________________
Technology, Incorporated
6-111
~
EIM28C010
ADVANCED INFORMATION DATA SHEET
Hardware Chip Erase
Min.
Max.
Units
Parameter
Description
t ELWL
Chip Enable Setup Time
5
tOVHEL
tWLWH
Output Enable Setup Time
5
Jls
Write Enable Pulse Width
10
ms
tWHEH
t WHOH
Chip Enable Hold Time
5
Jls
Output Enable Hold Time
5
tOHEL
VH
Erase Recovery Time
High Voltage
10.8
Jls
Jls
50
ms
13.2
V
Ordering Information
C
Q
M
28C010
,----I
PACKAGE
TYPE
TEMPERATURE
RANGE
PART TYPE
C - SIDEBRAZE
L-LCC
F - FLATPACK
M - -55"C to + 125"C
128K x 8 EEPROM
seeQ
MD4000851A
(MILITARY)
E - -4O"C to +85°C
(EXTENDED)
H
-120
/B
T TL---_T_-----,
EEPROM BYTE
WRITE TIME
(BLANK) - STANDARD WRITE TIME
H - FAST WRITE TIME
Technology, Incorporated
6-112
ACCESS TIME
SCREENING OPTION
120 - 120 ns
15O-15On5
2OO-2OOn5
250- 25On5
MIL 883 CLASS B
SCREENED
seeQ
M27641M27128
(Military Temperature Range)
E27641E27128
(Military Temperature Range)
2764/27128 EPROM
November 1989
Features
•
•
Pin Configuration
•
Programmed Using Intelligent Algorithm
21 V V,.,. Programming Voltage
•
JEDEC Approved Bytewlde Pin Configuration
• 2764 8K x 8 Organization
• 2712816K x 8 Organization
•
2764127128
Vpp
A12
A7
A6
As
A4
A3
A2
Al
Ao
°0
°1
°2
GND
200 ns Access Times at -5S°C to +125°C
•
•
DUAL-IN-lINE
TOPVlEW
Military and Extended Temperature Range
• -5S°C to +125°C: M2764
• -5S°C to +125°C: M27128
• -40°C to +85°C: E2764IE27128
Low Power Dissipation
• 120 mA Active Current
• 40 mA Standby Current
Silicon Signature®
Description
SEEQ's 2764 and 27128 are ultraviolet light erasable
EPROMs which are organized 8K x 8 and 16K x 8
respectively. They are specified over the military and
extended temperature range and have access times as
fast as 200 ns over the Vee tolerance range. The access
time is achieved without sacrificing power since the
maximum active and standby currents are 120 mA and 40
mA respectively. The 200 ns allows higher system
~
MODE
Read
X
VIH
Vee
X
Program Verify
VIH
VIL
VIL
VIH
Program Inhibit
X
VIL
Output Disable
Standby
Program
VIL
X
VIH
VIL
VIL
VIH
Silicon Signature· VIL
VIL
VIH
Vpp
(1)
c::J
Dour
HighZ
Vee Vee
Vpp Vee
High Z
X
Vpp Vee
Vpp Vee
Dour
HighZ
VIH
Vee Vee
Encoded
Data
X ean be either V1l or V1H
*For Silicon Signature: Ao is toggled,
addresses are at a TTL low.
Ag
A10
CE
°7
°6
Os
°4
Oa
OE
CE
PGM
-------
ROW
DECODERS
MEMORY
ARRAY
COLUMN
DECODER
COLUMN
ADDRESS
GATING
CONTROL
LOGIC
I/O
BUFFER
~
DIN
= 12V, and all other
Silicon Signature is a registered trademark of
SEEQ Technology, Inc.
SeeG Technology, Incorporated
MD4000111A
q
Outputs
(28) (11-13,15-19)
Vee Vee
OE
Block Diagram
vee
Vee Vee
PGM
A13 11J
As
Ag
All
PIN 2615 ANO CONNECT
ON THE DIP 2764.
Mode Selection
CE OE PGM
(20) (22) (27)
VCC
6-113
~...7
00-7
Pin Names
AC
ADDRESSES - COLUMN (LSB)
AR
ADDRESSES - ROW
CE
CHIP ENABLE
OE
OUTPUT ENABLE
0 0- 0 7
PGM
OUTPUTS
PROGRAM
M27641M27128
E271281E27128
this fast algorithm for SEEQ's EPROMs. If desired, the
27128 and the 2764 may be programmed using the
conventional 50 ms programming specification of older
generation EPROMs.
efficiency by eliminating the need for wait states in today's
8 - or 16-bit micro-processors.
Initially, and after erasure, all bits are in the "1" state. Data
isprogrammedbyapplying21 Vto Vppanda TTL "0"topin
27 (program pin). They may be programmed with an
intelligent algorithm that is now available on commercial
programmers. nIls faster time improves manufactoring
throughput time by hours over conventional 50 ms
algorithms.
Commercial programmers (e.g. Data 110,
Pro-log, Digelec, Kontron, and Stag) have implemented
Incorporated on the 27128 and 2764 is Silicon Signature.
Silicon Signature contains encoded data which identifies
SEEQ as the EPROM manufacturer, and programming
information. This data is encoded in ROM to prevent
erasure by ultraviolet light.
Absolute Maximum Ratings
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature
Storage ........................................... -65°C to +150°C
Under Bias ....................................... -6SOC to + 13SOC
AI/Inputs and Outputs
with Respect to Ground ....................... + 7 V to -0.6 V
Vpp During Programming
with Respect to Ground ..................... +22 V to -0.6 V
Voltage on Ag
with Respect to Ground .................. + 15.5 V to -0.6 V
Recommended Operating Conditions
M2764
M27128
Vee Supply Voltage(1)
Temperature Range (Read Mode)
E2764
E27128
5V± 10%
5V±10%
(Case) -55°C to +125°C
(Ambient) -40°C to 85°C
21 ± 0.5 V
21 ± 0.5 V
V pp During Programming
DC Operating Characteristics During Read or Programming
Limits
Symbol
Parameter
Max.
Units
Test Condition
liN
Input Leakage Current
10
~A
VIN = Vee Max.
10
Ipp[2)
Output Leakage Current
10
~A
VOUT = Vee Max.
5
mA
Vpp = Vee Max.
30
mA
Vpp = 21.5 V
40
mA
120
mA
CE = VIH
CE =OE =VIL
Vpp Current
Min.
Read Mode
Prog. Mode (25°C)
lee1
(2)
Vee Standby Current
(2)
lee2
V IL
Vee Active Current
Input Low Voltage
-0.1
0.8
V
V IH
Input High Voltage
2
Vee + 1
V
VOL
Output Low Voltage
VOH
Output High Voltage
0.45
2.4
V
IOL=2.1 mA
V
10H =-400 ~
NOTES:
1. Vee must be appied simultaneously or before Vpp and removed simultaneously or after Vpp'
2. Vpp may be connected directly to Vee except during programming. The supply current is the sum of Icc and Ipp.
SeeQ
MD4000111A
Technology, Incorporated
6-114
M27641M27128
E271281E27128
AC Operating Characteristics During Read
Limits (nsec)
ElM2764-20
ElM27128-20
ElM2764-25
ElM27128-25
Min.
Max.
Min.
Max.
Output Enable to
Output Float
0
200
200
75
60
0
250
250
100
85
Output Hold from Chip
Enable, Addresses, or
Output Enable, whichever
occured first
0
Symbol Parameter
tAA
Address Access Ti me
tCE
Chip Enable to Data Valid
(2]
Output Enable to Data Valid
tOE
t (3]
OF
tOH
0
Capacitance It]
Symbol
Parameter
Typ.
Max
Unit
Conditions
CIN
Input Capacitance
4
6
pF
VIN = 0 V
COUT
Output Capacitance
8
12
pF
VOUT = 0 V
ElM2764-35
ElM27128-35
Min.
Max.
0
350
350
125
105
0
M2764-45
Test
Min.
Max.
Conditions
CE=OE=V IL
0
450
450
150
130
0
OE=V IL
CE=V IL
CE=V IL
CE=OE=VIL
Equivalent A.C. Test Conditions [4]
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times::5 20 ns
Input Pulse Levels: 0.45V to 2.4V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
A.C. Waveforms
ADDRESSES
CE
ADDRESSES VALID
------+--..,.
OE
OUTPUT
-----+--..;..;.;.;;;;..;..;;;;..---+-+++-f-<
~---- tAA -----II~
NOTES:
1. This parameter is sampled and is not 100% tested.
2. OE may be delayed to tAA ~E after the falling edge of CE without impact on tAA .
3. ~F is specified from OE or CE, whichever occurs first.
4. These are equivalent test conditions and actual test conditions are dependent on the tester.
seeQ
MD4000111A
Technology, Incorporated
6-115
HIGHZ
M27641M27128
E271281E27128
Erasure Characteristics
The 2764 and 27128 are erased using ultraviolet light
The
which has a wavelength of 2537 Angstroms.
integrated dose, i.e. intensity x exposure time, for erasure
is a minimum of 15 watt-secondlcm 2 • The EPROM should
be placed within one inch of the lamp tube during erasure.
Table 1shows the typical EPROM erasure time for various
light intensities.
2 bytes of data available. The data (see Table 2) appears
onoutputs 0 0 to 0 6 , with 0 7 used as an oddparitybit. This
mode is functional at 2SO ± SOC ambient temperature.
Table 2. Silicon Signature Bytes
Table 1. Typical EPROM Erasure TIme
Light Intensity
(Mlcro-Watts/cm2)
Erasure Time
(Minutes)
15,000
20
10,000
30
5,000
55
Silicon Signature
Incorporated in SEEQ's EPROMs is a row of mask
programmed read only memory (ROM) cells which is
outside of the normal memory cell array. The ROM
contains the EPROMs Silicon Signature.
Silicon
Signature contains data which identifies SEEQ as the
manufacturer and gives the product code.
Silicon
Signature allows programmers to match the programming
specifications against the product which is to be
programmed. If there is verification, the the programmer
proceeds programming.
Silicon Signature is activated by raising address A9 to 12V
± 0.5V, bringing chip enable and output enable to a TTL
low, having Vee at 5V, and having all addresses except Ao
at a TTL/ow. The Silicon Signature data is then accessed
by toggling (using TTL) the column address Ao. There are
seeQ
MD4000111A
AO
Data Hex
SEEQ Code (Byte 0)
V1l
94
Product Code (Byte 1)
2764
27128
V1H
V1H
40
C1
Programming
The EPROMs may be programmed using an intelligent
algorithm or with a conventional 50 msec programming
pulse. The intelligent algorithm improves the total
programming time by approximately 10 times over the
conventional 50 msec algorithm.
The intelligent algorithm requires Vee =6V and Vpp =21 V
during byte programming. The initial program pulse width
is one millisecond, followed by a sequence of one millisecond pulses. A byte is verified after each pulse. A single
program pulse, with a time duration equal to 4 times the
number of one millisecond pulses applied, is additionally
given to the address after it is verified as being correctly
programmed. A maximum of 15 one millisecond pulses
per byte should be applied to each address. When the
intelligent algorithm cycle has been completed, all bytes
must be read at Vee = Vpp = 5V.
Technology, Incorporated
6-116
M27641M27128
E271281E27128
Intelligent Algorithm Flowchart
seeQ
MD4000111A
Technology, Incorporated
6-117
M27641M27128
E271281E27128
Intelligent Algorithm
ADDRE=S ::
----I..
~tAS~!
(2)
VIH
DATA
VIL
--'
(2)
Vpp
VIH
eE V
IL
VIH
PGM V
IL
VIH
OE V
IL
\\\\\~
I--
tOH
I--
tOFP
~
(0.13)
(2)
MAX.
",
".".
f4-IV~~~
"
)1--
".".
f4- tvcs~
(2)
1"
j.-'CES~
(2)
"".
.,
F-----:.
'PW ~
(0.95ms)
topw
(3.8ms)
,,;
J
~
~'oEs~1
(2)
tOE
~
(0.15)
MAX.
\~
~
1. All times shown in ( ) are minimum and in flSec unless otherwise specified.
2. The input timing reference level is .8V for a V1L and 2V for a V1H•
3. tOE and loFP are characteristics of the device but must be accommodated by the programmer.
MD4000111A
(0)
""
NOTES:
seeQ
. r-''"i
~
DATA OUT VALID
/1--
Vee + 1
Vee
"
HIGHZ /////:
~
Vee
Vee
r-
DATA IN STABLE
"1
~tDS~
VPP
.:k=
=J::~=======~~-A~DD-PR-~-ss-:-7-A-B-L=E=========:"::I·~========-_V_E~R:lJFY~-_-:_---
Technology, Incorporated
6-118
"1r
,,,
~
M27641M27128
E271281E27128
Intelligent Algorithm
AC Programming CharateristicsTA =25° ± 5°C, VCC [l.4] = 6.0 v ± 0.25 v, Vpp = 21
Limits
Typ.
Min.
V ± 0.5
v
Unit
Symbol
Parameter
tAS
Address Setup Time
2
J-lS
tOES
OE Setup Time
2
J-ls
tos
Data Setup Time
2
J-ls
tAH
Address Hold Time
0
J-ls
tOH
t OFP
Data Hold Time
2
J-ls
Output Enable to Output Float Delay
0
lvps
VPP Setup Time
2
lvcs
tpw[2]
Vcc Setup Time
topw
[3.4]
Max.
130
2
PGM Initial Program Pulse Width
0.95
PGM Overprogram Pulse Width
3.8
tCES
CE Setup Time
tOE
Data Valid from OE
J-ls
1.0
1.05
ms
63
ms
2
J-lS
150
NOTES:
1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp'
2. Initial Program Pulse width tolerance is 1 msec ± 5 %.
ns
J-ls
ns
3. The length of the overprogram pulse will vary from 3.8 msec
to 63 msec as a function of the iteration counter value X.
4. For 50 ms programming, Vee = 5 V± 5%, Tpw = 50 ms ± 10 %,
and T OPW is not applicable.
Ordering Information
o
o
M 27128 - 25
M 2764 - 25
Tl
.....------'T
PACKAGE
TYPE
TEMPERATURE
RANGE
D=CERDIP
M = -55°C to + 125°C
(MILITARY)
E = -4Q°C to +85°C
(EXTENDED)
seeQ
MD4000111A
T~T~
PART TYPE
2764 - 8K x 8 EPROM
27128 -16K x 8 EPROM
Technology, Incorporated
6-119
/B
ACCESS TIME
20 - 200 ns
25- 250 ns
35- 350 ns
45- 450 ns
SCREENING OPTION
MIL 883 CLASS B
SCREENED
6-120
seeQ
M27C2561E27C256
256K CMOS EPROM
November 1989
Pin Configuration
Features
•
256K (32K x 8) CMOS EPROM
•
Military and Extended Temperature Range
• -55°C to +125°C: M27C256
• -40°C to +85°C: E27C256
•
•
DUAL-IN-L1NE
LEADLESS CHIP CARRIER
BOTTOM VIEW
Vee
~
<
A14
~
0
Z
8:: ~ ...
> '" '"
A13
AS
Ultra Low Power
• 150 IlA Max. Vee Standby Current
• 50 mA Max. Active Current
Ag
All
6E
Programmed Using Intelligent Algorithm
• 12.5 V Vpp
A 10
CE
Al
°7
•
200 ns Access Times
•
5 V± 10% Vee
•
JEDEC Approved Bytewide Pin Configuration
•
Silicon Signature®
°1
°4
OJ
0
.. o..
.,,,z
0
~
N
°
0-
Block Diagram
Description
SEEQ's 27C256 is the industry's first 256K CMOS
EPROM. It has a 32K x 8 organization and has very low
power dissipation. Its active current is less than one half
the active power of n-channel EPROMs. In addition the
standby current is orders of magnitude lower than those
A 6 - A1
Mode Selection
~
CE
OE
MODE
(20)
Read
VIL
X
Program
VIH
VIL
Program Verify
VIH
VIH
VIL
VIH
Silicon Signature· VIL
VIH
VIL
Output Disable
Standby
Program Inhibit
Vpp
vee
(22)
(1)
(28)
VIL
VIH
Vee
Vee
Vee
X
Vee
Vpp
X can be either V1L or V1H
*For Silicon Signature: Ao is toggled,
addresses are at a TTL low.
Outputs
(11-13,15-19)
MD4000131B
ROW
DECODERS
sq
COLUMN
DECODER
OE
~
CE
~
CONTROL
LOGIC
"v
MEMORY
ARRAY
"
COLUMN
ADDRESS
GATING
~
110
BUFFER
L.
;..
Vee
DOUT
HighZ
'\,.7
Vee
HighZ
0 0 -7
Vee
DIN
Vpp
Vee
Vpp
Vee
DOUT
HighZ
Vee
~ =
Vee
Pin Names
Encoded
Data
12V, and all other
Silicon Signature is a registered trademark of
SEEQ Technology, Inc.
seeQ
4~
Technology, Incorporated
6-121
Ao-As
ADDRESSES - COLUMN (LSB)
As - A14
CE
ADDRESSES - ROW
OE
OUTPUT ENABLE
CHIP ENABLE
00- 07
OUTPUTS
NC
NO CONNECT
M27C256
E27C256
The 27C256 is specified over both the extended and
miitary temperature ranges at 5 V ± 10% Vce' The access
time is specified at 200 ns, making the 27C256 compatible
with most of today's microprocessors. Its inputs and
outputs are completely TTL compatible.
same EPROMs. Consequently, system memory sizes can
be substantially increased at a very small increase in
power. Low active and standby power is important in
applications which require portability, low cooling cost,
high memory bit density, and long term reliability.
Absolute Maximum Ratings
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature
Storage ........................................... - 65° C to + 150° C
M27C256 Under Bias ...................... -65°C to + 135°C
E27C256 Under Bias ......................... -500 C to +95° C
All Inputs or Outputs
with Respect to Ground ....................... + 7 V to -0.6 V
Vpp with Respect to Ground .............. + 14.0 V to -0.6 V
Voltage on Ag
with Respect to Ground .................. + 14.0 V to -0.6 V
Recommended Operating Conditions
M27C256-20, M27C256-25
M27C256-30
vee Supply Voltage[1)
Temperature Range (Read Mode)
E27C256-20, E27C256-25
E27C256-30
5V± 10%
5V± 10%
(Case) -55°C to + 125°C
(Ambient) -40°C to +85°C
Vee
12.5 ± 0.3V
Vee
12.5 ± 0.3V
V pp During Read[2)
V pp During Programming[3)
DC Operating Characteristics During Read or Programming
Limits
Symbol
Max.
Units
Test Condition
Input Leakage
1
/lA
V IN = Vee Max.
Output Leakage
10
/lA
VOUT = Vee Max.
Vpp Current
Standby Mode
Read Mode
Programming Mode
150
1
30
/lA
mA
mA
CE=Vec -1 v. min.
F = 5 MHz, CE = VIL
Vpp = 12.5 v.
lee1
Vee Standby Current
150
/lA
CE ~Vee-1 v.
Icc2
Vec Standby Current
2
mA
lee3
Vee Active Current
50
mA
CE = VIH
CE = OE =VIL' 0 0 _ 7 = 0,
F =5 MHz.
V IL
Input Low Voltage
-0.1
0.8
V
V IH
Input High Voltage
2.0
Vce + 1
V
VOL
Output Low Voltage
VOH
Output High Voltage
[4)
liN
I [5)
0
Ipp
Parameter
Min.
0.45
2.4
V
IOL = 2.1 ma
V
IOH = -400 /lA.
NOTES:
1. Vee must be appied simultaneously or before Vpp and removed simultaneously or after Vpp'
2. Vpp cannot be left floating and should be connected to Vee during read.
3. 0.1 ~F ceramic capacitor on Vpp is required during programming only, to suppress voltage transients.
4. Inputs only. Does not include 1/0.
S. For 110 only.
seeG
MD4000131B
Technology, Incorporated
6-122
M27C256
E27C256
AC Operating Characteristics During Read
Limits (nsec)
M27C256-20
E27C256-20
Symbol Parameter
Min.
Max.
M27C256-25
E27C256-25
Min.
Max.
M27C256-30
E27C256-30
Min.
Max.
Test
Conditions
tAA
Address Access Time
200
250
300
CE=OE=VIL
teE
Chip Enable to Data Valid
200
250
300
OE=VIL
120
CE=VIL
105
CE=VIL
tOE
tOF
(2)
Output Enable to Data Valid
75
100
(3)
Output Enable or Chip Enable
60
60
to Output Float
tOH
0
Output Hold from Chip Enable,
Addresses, or Output Enable
whichever occured first
0
Capacitance [1J
CE=OE=VIL
Equivalent A.C. Test Conditions[4]
Typ.
Max
Unit
Conditions
C IN
Input Capacitance
4
6
pF
V IN = 0 V
COUT
Output Capacitance
8
12
pF
VOUT = 0 V
Symbol Parameter
0
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times:;5:; 20 ns
Input Pulse Levels: 0.45V to 2.4V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
A.C. Waveforms
ADDRESSES
CE
ADDRESSES VALID
-----+--..,.
OE
OUTPUT------~-----~~~_+~~
VALID OUTPUT
~----tAA ----~
NOTES:
1. This parameter is sampled and is not 100% tested.
2. OE may be delayed to tAlI ~E after the falling edge of CE without impact on tAlI'
3. ~F is specified from OE or CE, whichever occurs first.
4. These are equivalent test conditions and actual test conditions are dependent on the tester.
seeQ
MD400013/8
Technology, Incorporated
6-123
HIGHZ
M27C256
E27C256
Initially and after erasure, all bits are in the"1 state. An
intelligent algorithm is used to program the 27C256 typically in four minutes. Data is programmed using a 12.5V
Vpp and an initial chip enable pulse of 1.0 ms.
the programming specification against the product which
is to be programmed. If there is verification, then the
programmer proceeds to program.
Incorporated on the 27C256 is Silicon Signature. Silicon
Signature contains encoded data which identifies SEEQ
as the EPROM manufacturer and gives the product code.
This data is encoded in ROM to prevent erasure by
ultraviolet light.
± 0.5V, bringing chip enable and output enable to a TTL
low, hav1ng all addresses except AD at a TTL low. The
H
Silicon Signature is activated by raising address Ag to 12V
Silicon Signature data is then accessed by toggling AD.
The data appears on outputs 0 0 to 0 6 , with 0 7 used as an
odd parity bit (see Table 2).
Erasure Characteristics
The 27C256 is erased using ultraviolet light which has a
wavelength of 2537Angstroms. The integrated dose, i. e.,
intensity x exposure time, for erasure is a minimum of 15
watt-seconds/cm 2 • The EPROM should be placed within
one inch of the lamp tube during erasure. Table 1 shows
the typical EPROM erasure time for various light intensities.
Table 2. Silicon Signature Bytes
Table 1. Typical EPROM Erasure Time
Programming
Light Intensity
(Mlcro-Watts/cm2)
Erasure Time
(Minutes)
15,000
20
10,000
30
5,000
55
Silicon Signature
Incorporated in SEEQ's EPROMs is a row of mask programmed read only memory (ROM) cells which is outside
of the normal memory cell array. The ROM contains the
EPROM's Silicon Signature. Silicon Signature contains
data which identifies SEEQ as the manufacturer and gives
the product code. This data allows programmers to match
seeQ
MD4000131B
Ao
SEEQ Code (Byte 0)
Product Code (Byte 1)
Data (Hex)
V'L
94
V'H
C2
The 27C256 is programmed using the industry standard
intelligent algorithm.
The intelligent algorithm requires Vee=6 VandVpp = 12.5
V during byte programming. The initial program pulse
width is 1.0 millisecond, followed by a sequence of 1.0
millisecond pulses. A byte is verified after each pulse. A
single program pulse, with a time duration equal to 3 times
the number of 1.0 millisecond pulses applied, is additionally given to the address after it is verified as being
correctly programmed. A minimum of one to a maximum
of 25 1-ms pulses, plus one 3X overpulse, may be applied
to each byte. When the intelligent algorithm cycle has
been completed, all bytes must be read at Vee= Vpp =5 V.
Technology, Incorporated
6-124
M27C256
E27C256
Intelligent Algorithm Flowchart
seeQ
MD4000131B
Technology, Incorporated
6-125
M27C256
E27C256
Intelligent Algorithm
""·--------PROGRAM-------I..
~I"'I~------VERIFY-----·~II
V IH
)
ADDRESSES
V IL
-,.,
ADDRESS STABLE
~
(2)
V 1H
1
DATA
t-
DATllN STABLE
HIGHZ
'-LLLl1/~
~\\\\~~
-'
V 1L
Vee
Vee +1
~
J
14-- tv(~~~
-"
j
~t-J - - -
V 1L
'PW
(O.95ms) ~
f4--- t OES
(2)
V 1H
topw
(2.85ms)
-1 ~~~~)~
~
~
MAX.
'/-
,
"
NOTES:
1. All times shown in ( ) are minimum and in J.LSee unless otherwise specified.
2. The input timing reference level is 0.8 V for a V 1L and 2 V for a V1W
3. tOE and fuFP are characteristics of the device but must be accomodated by the programmer.
4.0.1 IJ.F ceramic capacitor on Vpp is required during programming only. to suppress voltage transients.
seeQ
MD4000131B
-
~
1~
eE
V 1L
-
tOFP
(0.13)
Max.
J14-- 'v~~--.-
(4)
OE
"
-"
Vpp
Vpp
V 1H
~TV~LlD
~'c~~"
(2)
Vee
"
DATA
.~A~--1
(0)
~
~tDS~
Vee
X
1~
~tAs~1
Technology, Incorporated
6-126
M27C256
E27C256
Intelligent Algorithm
AC Programming Charateristics
TA =25 0
± 5°C, Vee [1 J = 6.0 v ± 0.25 v, Vpp = 12.5 V
Min.
Limits
Typ.
Max.
Unit
Symbol
Parameter
t AS
Address Setup Time
2
Il S
tOEs
OE Setup Time
2
Ils
tos
Data Setup Time
2
Il s
tAH
Address Hold Time
0
IlS
tOH
Data Hold Time
2
t oFP
Output Enable to Output Float Delay
0
t vps
Vpp Setup Time
2
Il s
130
Il s
2
Ils
tves
Vee Setup Time
tpw
CE Initial Program Pulse Width
0.95
CE Overprogram Pulse Width
2.85
topw
[3]
1.0
Data Valid from OE
tOE
NOTES:
1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after V pp'
2. The length of the overprogram pulse will vary from 2.85 msec
to 78.75 msec as a function of the iteration counter value X.
ns
1.05
ms
78.75
ms
150
ns
AC Conditions of Test
Input Rise and Fall Times (10% to 90%) ............... 20 ns
Input Pulse Levels .................................. 0.45 V to 2.4 V
Input Timing Reference Level ................ 0.8 V and 2.0 V
Output Timing Reference Level ............. 0.8 V and 2.0 V
Ordering Information
=2ld=T-----,
o
M 27C256 - 25
IB
PACKAGE
TYPE
TEMPERATURE
RANGE
PART TYPE
D_ CERDIP
L-LCC
M _ -55°C to + 125°C
(MILITARY)
E --40°C _ +85°C
(EXTENDED)
32K x8 EPROM
seeQ
AfD4000131B
Technology, Incorporated
6-127
ACCESS TIME
SCREENING OPTION
20·200 ns
25 - 250 ns
30·300 ns
MIL 883 CLASS B
SCREENED
6-128
seeQ
82005
MILITARY DRAWING
64KUVEPROM
May 1988
Description
Features
•
•
•
•
•
•
•
•
SEEQ's 82005 is a military drawing compliant, 21-volt
programming, 65,532-bit (8192 x 8), ultraviolet erasable
EPROM. The 64K EPROM is fabricated and tested in
SEEQ Technology's DESC-approved manufacturing facility and has been processed per the requirements of
Method 500415005 of MIL-STD-883. The 82005 EPROM
provides continuing support for applications which utilize a
21-volt programming 64K EPROM in their design.
82005 Military Drawing Compliant
Processing Per Method 500415005
MIL-STD-883
21-Volt Programming
JEDEC-Approved 8ytewlde Pin
Configuration
200 ns Access Time
MIL-M-38510 Compliant Package Design
Using the 82005 will satisfy MIL -STD-454K which dictates
the use of military drawing parts over 883C compliant parts
if they are available. Furthermore, designing with standard
military drawing devices eliminates the needforcustomergenerated source control drawings, while ensuring the
highest level of device reliability.
Programmed Using Intelligent Algorithm
Silicon Signature~
Block Diagram
~
ROW
DECODERS
)
"
COLUMN
DECODER
)
"
MEMORY
ARRAY
~
Mode
Read
Output Disable
Standby
110
D
CE
(20)
OE PGM
(22) (27)
VIL
X
VIL
VIH
VIH
VIL
Program
Program Verify
A12
BUFFERS
Mode Selection
Program Inhibit
VIL
VIH
Silicon Signature·
VIL
OUTPUTS
(1)
vee
(28)
Vee
Vee
Vee
Vee
Dour
High Z
Vee
Vpp
Vee
HighZ
Vee
DIN
Vpp
Vee
Vpp
(11-13,15-19)
X
VIH
Vee
X
VIH
VIL
VIL
VIH
X
X
Vpp
Vee
Dour
HighZ
VIL
VIH
Vee
Vee
Encoded Data
X ean be either V1l or V 1H
• For Silicon Signature: Ao is toggled,
are at a TTL low.
A, = 12 V, and all other addresses
Silicon Signature is a registered trademark of SEEa Technology, Inc.
seeQ
MD4000591-
vcc
Vpp
COLUMN
ADDRESS
GATING
..
CONTROL
LOGIC
Pin Configuration
Technology, Incorporated
6-129
PGM
A7
N/C
As
As
As
Ag
A4
A11
A3
OE
A2
A 10
Al
CE
Ao
°7
°0
Os
°1
Os
°2
°4
GND
03
Pin Names
Ao- A4
ADDRESSES-COLUMN
As- A12
ADDRESSES-ROW
CE
CHIP ENABLE
OE
OUTPUT ENABLE
0 0- 0 7
OUTPUTS
PGM
PROGRAM
82005
MILITARY DRAWING
64KUVEPROM
The 82005 is manufactured using JEDEC approved bytewide pinouts and 28-pin package. Access times as fast as
200 ns eliminate the need for wait states in high-performance microprocessor systems. Programming can be
accomplished using either the intelligent algorithm or the
50 mslbyte algorithm available on commercial programmers.
82005 Assembly /Test Flow Chart
Screening per MIL-STD-883 Method 5004 and qualityconformance acceptance per Method 5005.
Quality-Assurance Provisions
Quality-assurance screening for the 82005 is performed
on 100% of the devices in accordance with Method 5004
of MIL-STD-883. In addition, burn-in (Method 1015,
125°C min) and data retention bake are performed on
each device after Method 5004 screening and prior to submitting for quality conformance inspection testing.
ASSEMBLY
ENVIRONMENTAL SCREENS
FINE/GROSS LEAK
CONSTANT ACCELERATION
TEMPERATRE CYCLE
Quality-Conformance Inspection
Quality-conformance inspection is performed in accordance with Method 5005 of MIL-STD-883. This includes
GroupA, Group B, Group C, and Group D inspections tests
as defined in military drawing 82005. Generic QCI summary data will be provided upon request.
Electrical Performance Characteristics
The 82005 can be ordered from SEEQ Technology with
device access times =200 ns (82005 - 07), 250 ns (82005
- 02), and 450 ns (82005 - 01). Details on device specific
electricalperformance can be found in the complete DESC
82005 military drawing or SEEQ's data sheet for generic
part type DM2764. SEEQ's testing meets or exceeds all
electrical performance screening and test limits as specified on the 82005 military drawing.
SHIP
seeQ
MD400059/-
Technology, Incorporated
6-130
82005
MILITARY DRAWING
64KUVEPROM
Programming
Erasure Characteristics
The 82005 may be programmed using an interactive intelligent algorithm or with a conventional 50 ms/byte programming pulse. Use of the intelligent algorithm improves
the total device programming time by approximately 10
times over the 50 ms/byte algorithm.
The 82005 is erased by exposure to high-intensity ultraviolet light with a wave length of 2537 angstroms. The
minimum integrated dose for erase (i.e. intensity x exposure time) is 15 watt-secondlcm 2 • The device should be
placed within one inch of the lamp tube during erasure.
After erasure, all bits are in the high state.
To program using the intelligent algorithm requires Vee =
6V, Vpp= 21 V, andCE =V'c The initial programming pulse
Silicon Signature
applied to the PGM pin is one millisecond in duration,
followed by a byte verification. Additional one millisecond
program pulses are applied and checked until the byte
passes verification. After verification, an overprogram
pulse equal to 4 x the number of one millisecond pulses
required to initially program the byte is applied to the
address. A maximum of 15 one millisecond pulses per
byte is allowed. When the intelligent programming cycle
has been completed, all bytes must be read with Vee =Vpp
= 5.0 volts to verify correct programming.
Incorporated in SEEQ's 82005 EPROM is a row of maskprogrammed read-only memory (ROM) cells, located
outside of the normal memory cell array. These ROM cells
contain the EPROM's Silicon Signature. Silicon Signature
identifies SEEQ as the manufacturer and gives the device's product code for programming. This allows the programmer to match the product to be programmed with the
correct programming specification. Once the device code
and programming specification have been verified, programming of the part can proceed.
Ordering Information
82005
01
Y
A
~S=
DRAWING NUMBER
(8192 x 8 UV EPROM)
DEVICE TYPE
CASE OUTLINE
Device Type
Generic Number
01
2764-45
02
2764-25
07
2764-20
LEAD FINISH PER
MIL-M-38510
Access Time
450 ns
250 ns
200 ns
Case Outline
Y
= D -10 (28 PIN, 1/2" x 1-3/8"), DUAL-IN-LiNE PACKAGE
Lead Finish
A
seeQ
MD400059/-
= HOT SOLDER DIPPED
Technology, Incorporated
6-131
6-132
seeQ
82025
MILITARY DRAWING
128K UV EPROM
May 1988
Features
Description
•
82025 Military Drawing Compliant
•
Processing Per Method 500415005
AfIL·STD·883
SEEQ's 82025 is a mHitary drawing compliant, 21-volt
programming, 131,064-bit (16,384 x 8), ultraviolet erasable EPROM. The 128K EPROM is fabricated and tested
in SEEQ Technology's DESC-approved manufacturing
facility and has been processed per the requirements of
Method 500415005 of MIL-STD-883. The 82025 EPROM
provides continuing support for applications which utilize a
21-volt programming 128K EPROM in their design.
•
21· Volt Programming
•
JEDEC·Approved Bytewlde Pin
Configuration
•
200 ns Access Time
•
AfIL·M·38510 Compliant Package Design
•
Programmed Using Intelligent Algorithm
•
Silicon Signature@
Using the 82025 will satisfy MIL -STD-454K which dictates
the use of military drawing parts over 883C compliantparts
if th ey are available. Furthermore, designing with standard
military drawing devices eliminates the need for customergenerated source control drawing, whHe ensuring the
highest level of device reliability.
Block Diagram
ROW
DECODERS
..'")
MEMORY
ARRAY
COLUMN
DECODER
..)
COLUMN
ADDRESS
GATING
Pin Configuration
....
Vpp
a
CONTROL
LOGIC
1/0
BUFFERS
D
Mode Selection
~
CE
°5
Vee
Vee
High Z
°4
03
VIL
VIH
Vpp
Vee
DIN
Vpp
Vee
X
X
Vpp
Vee
DOUT
High Z
VIL
VIH
Vee
Vee
Encoded Data
Vee
Vee
Vee
Vee
X
X
VIH
VIL
X can be either V1l or V 1H
* For Silicon Signature: Ao is toggled, Ag
= 12 V, and all other addresses
are at a TTL low.
Silicon Signature is a registered trademark of SEEQ Technology, Inc.
MD4000601-
AlO
Al
°1
VIL
VIH
VIH
X
eeeQ
OE
A2
°2
VIL
VIL
A3
DOUT
High Z
Read
Output Disable
Silicon Signature·
All
Vee
vee
(28)
Program Inhibit
Ag
A4
°7
Os
(1)
VIL
VIH
As
A5
Ao
Vpp
(27)
Program Verify
As
°0
PGM
(22)
Program
A13
OUTPUTS
OE
(20)
VIH
VIL
PGM
A7
(11·13,15-19)
CE
Mode
Standby
VCC
A12
Technology, Incorporated
6-133
GND
Pin Names
Ao- As
ADDRESSES-COLUMN
As- A13
ADDRESSES-ROW
CE
CHIP ENABLE
OE
OUTPUT ENABLE
0 0 -07
OUTPUTS
PGM
PROGRAM
82025
MILITARY DRAWING
128K UV EPROM
The 82025 is manufactured using JEDEC approved bytewide pinouts and 28-pin package. Access times as fast as
200 ns eliminate the need for wait states in high-performance microprocessor systems. Programming can be
accomplished using either the intelligent algorithm or the
50 ms/byte algorithm available on commercial programmers.
82025 Assembly /Test Flow Chart
Screening per MIL-STD-883 Method 5004 and qualityconformance acceptance per Method 5005.
Quality-Assurance Provisions
Quality-assurance screening for the 82025 is performed
on 100% of the devices in accordance with Method 5004
of MIL-STD-883. In addition, burn-in (Method 1015,
125°C min) and data retention bake are performed on
each device after Method 5004 screening andprior to submitting for quality conformance inspection testing.
ASSEMBLY
ENVIRONMENTAL SCREENS
FINE/GROSS LEAK
CONSTANT ACCELERATION
TEMPERATRE CYCLE
Quality-Conformance Inspection
Quality-conformance inspection is performed in accordance with Method 5005 of MIL-STD-883. This includes
Group A, Group B, Group C, and Group D inspections tests
as defined in military drawing 82025. Generic QCI summary data will be provided upon request.
Electrical Performance Characteristics
The 82025 can be ordered from SEEQ Technology with
device access times =200 ns (82025 - 08), 250 ns (82025
- 02), 300 ns (82025 - 09), and 450 ns (82025 - 01). Details
on device specific electrical performance can be found in
the complete DESC 82025 military drawing or SEEQ's
data sheet for generic part type DM27128. SEEQ's testing
meets or exceeds all electrical performance screening and
test limits as specified on the 82025 military drawing.
SHIP
seeQ
MD4000601-
Technology, Incorporated
6-134
82025
MILITARY DRAWING
128K UJ/ EPROM
Programming
Erasure Characteristics
The 82025 may be programmed using an interactive
intelligent algorithm or with a conventional 50 ms/byte
programming pulse. Use of the intelligent algorithm improves the total device programming time by approximately 10 times over the 50 ms/byte algorithm.
The 82025 is erased by exposure to high-intensity ultraviolet light with a wave length of 2537 angstroms. The
minimum integrated dose for erasure (i.e. intensity x exposure time) is 15 watt-secondlcm 2 • The device should be
placed within one inch of the lamp tube during erasure.
After erasure, all bits are in the high state.
To program using the intelligent algorithm requires Vee =
6V, Vpp=21 V, andCE= V/L. Theinitialprogrammingpulse
applied to the PGM pin is one millisecond in duration,
followed by a byte verification. Additional one millisecond
program pulses are applied and checked until the byte
passes verification. After verification, an overprogram
pulse equal to 4 x the number of one millisecond pulses
required to initially program the byte is applied to the
address. A maximum of 15 one millisecond pulses per
byte is allowed. When the intelligent programming cycle
has been completed, all bytes must be read with Vee = Vpp
= 5.0 volts to verify correct programming.
Silicon Signature
Incorporated in SEEO's 82025 EPROM is a row of maskprogrammed read-only memory (ROM) cells, located
outside of the normal memory cell array. These ROM cells
contain the EPROM's Silicon Signature. Silicon Signature
identifies SEEO as the manufacturer and gives the device's product code for programming. This allows the programmer to match the product to be programmed with the
correct programming specification. Once the device code
and programming specification have been verified, pro·
gramming of the part can proceed.
Ordering Information
82025
01
Y
A
~~
DRAWING NUMBER
(16,384 x 8 UV EPROM)
DEVICE TYPE
CASE OUTLINE
Device Type
Generic Number
01
27128-45
02
27128-25
08
27128-20
09
27128-30
LEAD FINISH PER
MIL-M-38510
Access Time
450 ns
250 ns
200 ns
300 ns
Case Outline
Y
= D -10 (28 PIN, 1/2" x 1-3/8"), DUAL-IN-LiNE PACKAGE
Lead Finish
A
seeQ
MD4000601-
= HOT SOLDER DIPPED
Technology, Incorporated
6-135
6-136
seeQ
86063
MILITARY DRAWING
256K CMOS UV EPROM
May 1988
Features
Description
•
86063 Military Drawing Compliant
•
Processing Per Method 500415005
MIL-STD-883
SEEQ's 86063 is a military drawing compliant, 262, 144bit (32,768 x 8), ultraviolet erasable CMOS EPROM. The
256K EPROM is fabricated and tested in SEEQ Technology's DESC-approved manufacturing facility and has
been processed per the requirements of Method 50041
5005 of MIL-STD-883. It's CMOS design draws less than
one-half the active current and several orders of magnitude less standby current than equivalent density Nchannel EPROMS.
•
Low Power CMOS
•
JEDEC-Approved 8ytewlde Pin
Configuration
•
200 ns Access Time
•
MIL-M-38510 Compliant Package Design
•
Programmed Using Intelligent Algorithm
•
Silicon Signature@
The 86063 is manufactured using JEDEC approved bytewide pinouts for both the 28-pin dual-in-line and 32-pin
leadless chip carrier packages. Access times as fast as
Pin Configuration
Pin Names
Dua/-/n-Llne
Ao-~
ADDRESSES-COLUMN
Vpp
Vee
As-AI4
ADDRESSES-ROW
A12
A14
CE
CHIP ENABLE
A7
A13
AS
AS
OE
OUTPUT ENABLE
AS
Ag
0 0 -07
OUTPUTS
A4
All
NC
NO CONNECT
A3
OE
A
A2
10
CE
07
Os
Block Diagram
01
05
04
GND
ROW
DECODERS
....
)
....
MEMORY
ARRAY
03
Lead/ess Chip Carrier
Bottom View
..,
0
0. N
« : 9 ~ >0.<':: ;
~
COLUMN
DECODERS
OE~
CE~
CONTROL
LOGIC
....
./
..
...
COLUMN
ADDRESS
GATING
AS
A9
I/O
BUFFERS
An
NC
OE
U
Silicon Signature is a registered trademark of SEEQ Technology, Inc.
seeQ
MD4000611-
Technology, Incorporated
6-137
INDEX
CORNER
86063
MILITARY DRAWING
256K CMOS UV EPROM
86063 AssemblylTest Flow Chart
200 ns eliminate the need for wait states in high-performance microprocesssor systems. Device programming is
accomplished using the interactive intelligent algorithm
available on commercial programmers.
Screening per MIL-STD-883 Method S004 and qualityconformance acceptance per Method SOOS.
Using the 86063 will satisfy MIL -STD-4S4K which dictates
the use of military drawing parts over 883C compliant parts
if they are available. Furthermore, designing with standard
military drawing devices eliminates the need for customergenerated source control drawings, while ensuring the
highest level of device reliability.
ASSEMBLY
ENVIRONMENTAL SCREENS
FINE/GROSS LEAK
CONSTANT ACCELERATION
TEMPERATRE CYCLE
Quality-Assurance Provisions
Quality-assurance screening for the 86063 is performed
on 100% of the devices in accordance with Method 5004
of MIL-STD-883. In addition, burn-in (Method 101S,
12SoC min) and data retention bake are performed on
each device after Method S004 screening and prior to submitting for quality conformance inspection testing.
Quality-Conformance Inspection
Quality-conformance inspection is performed in accordance with Method S005 of MIL-STD-883. This includes
GroupA, Group B, Group C, and Group D inspections tests
as defined in military drawing 86063. Generic QCI summary data will be provided upon request.
Electrical Performance Characteristics
The 86063 can be ordered from SEEQ Technology with
device access times =200 ns (86063 - 01), 2S0 ns (86063
- 02), and 300 ns (86063 - 03). Details on device specific
electrical performance can be found in the complete DESC
86063 military drawing or SEEQ's data sheet for generic
part type DM272S6. SEEQ's testing meets or exceeds all
electrical performance screening and test limits as specified on the 86063 military drawing.
Mode Selection
~
CE
OE
Vpp
vee
OUTPUTS
DOUT
High Z
Mode
Read
Vil
Vil
Vee
Vee
Output Disable
Vil
Vee
Vee
Standby
VIH
VIH
X
Vil
Vee
Vpp
Vee
6.0V
High Z
Program
Program Verify
VIH
VIH
Vil
Program Inhibit
Silicon Signature·
VIH
Vil
Vpp
6.0V
VIH
Vpp
6.0V
DOUT
High Z
V1l
Vee
Vee
Encoded Data
X can be either V1L or V 1H
• For Silicon Signature: Ao is toggled,
are at a TTL low.
seeQ
MD400061/-
SHIP
DIN
Ag =
12 V, and all other addresses
Technology, Incorporated
6-138
86063
MILITARY DRAWING
256K CMOS UV EPROM
Programming
minimum integrated dose for erasure (i. e. intensity x exposure time) is 15 watt-secondlcm 2 • The device should be
placed within one inch of the lamp tube during erasure.
After erasure, all bits are in the high state.
To program the 86063 using the intelligent algorithm requires Vee = 6 V, Vpp = 12.5 V, and CE = V,w The initial
programming pulse applied to the CE pin is one millisecond in duration, followed by a byte verification. Additional
one millisecond program pulses are applied and checked
until the byte passes verification. After verification, an
overprogram pulse equal to 3 x the number ofone millisecond pulses required to initially program the byte is applied
to the address. A maximum of 25 one millisecond pulses
per byte is allowed. When the intelligent programming
cycle has been completed, all bytes must be read with
Vee = Vpp =5.0 volts to verify correct programming.
Silicon Signature
Incorporated in SEEQ's 86063 EPROM is a row of maskprogrammed read-only memory (ROM) cells, located
outside of the normal memory cell array. These ROM cells
contain the EPROM's Silicon Signature. Silicon Signature
identifies SEEQ as the manufacturer and gives the device's product code for programming. This allows the programmer to match the product to be programmed with the
correct programming specification. Once the device code
and programming specification have been verified, programming of the part can proceed.
Erasure Characteristics
The 86063 is erased by exposure to high-intensity ultraviolet light with a wave length of 2537 angstroms. The
Ordering Information
86063
DRAWING NUMBER
(32.768 x 8 UV EPROM)
01
X
A
~~
DEVICE TYPE
Device Type
01
02
03
CASE OUTLINE
Generic Number
27C256-20
27C256-25
27C256-30
LEAD FINISH PER
MIL-M-38510
Access Time
200 ns
250 ns
300 ns
Case Outline
Y = D -10 (28 PIN, 1/2" x 1-3/8"), DUAL-IN-LiNE PACKAGE
Y = C -12 (32 TERMINAL, .450" x .550"),
RECTANGULAR CHIP CARRIER PACKAGE
Lead Finish
A = HOT SOLDER DIPPED
G = GOLD PLATE
seeQ
MD400061/-
Technology, Incorporated
6-139
6-140
seeQ
EIM47F512
512K Bit CMOS FLASH EPROM
October 1989
PRELIMINARY DATA SHEET
Block Diagram
Features
•
64K Byte FLASH Erasable Non-Volatile Memory
•
Input Latches for Writing and Erasing
•
Fast Byte Write: 225 ps max
•
-55°C to +125°C Temp Read (M47F512)
•
-40°C to + 85°C Temp Read (E47F512)
•
25°C::t 5°C Temp Write/Erase
•
Ideal for Low-Cost Program Storage Applications
• In-Circuit Alterable
• 100 Program/Erase Cycles
• Minimum 10 Year Data Retention
•
JEDEC Standard Byte Wide Pinout
• 32PinPLCC
• 32 Pin Dip
• 32PadLCC
•
Silicon Signature@
ARRAY
64Kx 8
Pin Names
Ao-A8
A9 -A15
COLUMN ADDRESS INPUT
CE
CHIP ENABLE
1100-7
ROW ADDRESS INPUT
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00-7
N.C.
DATA INPUT (WRITE)/OUTPUT (READ)
Vpp
D.U.
WRITE/ERASE INPUT VOLTAGE
NO INTERNAL CONNECTION
Pin Configurations
DUAL-IN-LiNE
TOP VIEW
DON'T USE
PLASTIC LEADED CHIP CARRIER
TOP VIEW
LEADLESS CHIP CARRIER
TOP VIEW
INDEX ~
CORNER
N
'"
"-
<)
A10
FE
AO
I~
V0 7
fil r~l f!l r~l r~l r~l r~l
g~~ggg~
§§:~g"'1~~
Silicon Signature is a registered trademark of SEEQ Technology.
seeQ
MD400083/-
WE
NC
I!l!
- -z
<)
"- <)
<)
«
»
>z
Al
VO O
Vee
Technology, Incorporated
6-141
A12
A7
As
As
A4
A3
A2
Al
Ao
VOo
VOl
VO:!
Vss
S
A14
A13
As
Ag
All
9
OE
11
CE
A10
VO]
VOs
VOs
V04
V0 3
EIM47F512
PRELIMINARY DATA SHEET
Description
The EIM47F512is a 512Kbit CMOS Flash EPROM organized as 64Kx 8 bits and specified over the Industrial/Military
Temperature Range. The E/M47F512 brings together the
high density and cost effectiveness of UVEPROMs with
the in-circuit reprogrammability and package options of full
featured EEPROMs. SEEQ's patented spiit gate Fiash
EPROM cell design reduces both the time and cost required to alter code in program and data storage applications.
The EIM47F512's fast electrical erase and 0.2 ms/byte
programming is 20 times faster than reprogramming of
UVEPROMs. Electrical erase and reprogramming make
the EIM47F512 ideal for applications with high density requirements, but where ultraviolet erasure is either impractical or impossible.
On chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to perform other
tasks once write/erase cycles have been initiated. Endurance, the number of times each byte can be written and
erased, is specified at 100 cycles. Electrical erase allows
the ElM47F512 to be packaged in a wide range of windowless plastic, ceramic and surface mount packages.
Read
Reading is accomplished by presenting a valid address on
Ao - A,s with chip enable (CE) and output enable (OE) at V1L
and write enable (WE) at ~H' The Vpp pin can be at any
TTL level or Vp during read operations. See page 5 for
additional information on A. C. parameters and read timing
waveforms.
Erase and Write
Erasing and writing of the E/M47F512 can only be accomplished when Vpp =Vp. Latches on address, data and control inputs permit erasing and writing using normal microprocessor bus timing. Address inputs are latched on the
falling edge of write enable or chip enable, whichever is
later. While data inputs are latched on the rising edge of
write enable or chip enable, whichever is earlier. The write
enable input is noise protected; a pulse of less than 20 ns
will not initiate a write or erase. In addition, chip enable,
output enable and write enable pins must be in the proper
state to initiate a write or erase. Timing diagrams depict
write enable controlled writes; the timing also applies to
chip enable controlled writes.
be written at one time. If a bit in a byte needs to be changed
from a 0 to a 1, the E/M47F512 must first be erased via chip
erase and then reprogrammed with the desired data. Any
byte write operation requires that the Vpp pin be at high
voltage (Vp).
The E/M47F512 uses a software controlled looping algorithm (figure 1) to perform writes and verify successful byte
programming. During a byte write operation, all non tiFF'"
bytes are incrementally written using a 75J.ls minimum twc'
Each byte write is automatically latched and timed on-chip,
so that the microprocessor can perform other tasks once
the write cycle has been initiated. Write cycle time duration can be controlled by the microprocessor, or the onchip timer will automatically terminate twe after 150 ps.
One write loop has been completed when all non tiFF" data
for all desired bytes have been written. After 3 programming loops, a read-verification cycle is performed. For any
bytes which do not verify, a fill-in programming loop is
performed.
Chip Erase
Chip Erase will change all bits in the memory to a logical
1. The EIM47F512 uses a two-step, software controlled
looping algorithm to perform the chip erase operation.
Each loop requires that a chip erase select be performed
prior to the start of each chip erase cycle.
The chip erase select is activated by initiating a write cycle
with the Vpp pin at V1H or lower. During the chip erase
select, address and data lines can be at any TTL level.
Following a chip erase select, the E/M47F512 will start
chip erase if all data inputs are tiFF'; Vpp = Vp and a write
cycle initiated. After 20 loops, a device erase verify is
performed to insure all bytes = tiFF': After erase, the Vpp
pin can be brought to any TTL level or left at high voltage.
Refer to page 8 for chip erase timing diagram and figure 2
for the erase algorithm.
Power Up/Down Protection
This device contains a sense circuit which disables internal erase and write operations when Vcc is below 3.5 volts.
In addition, erases and writes are prevented when any
control input (CE, OE, WE) is in the wrong state for writing
/erasing (see mode table).
High Voltage Input Protection
Byte Write
A byte write is used to change any 1 in a byte to a O.
Individual bytes, multiple bytes or the entire memory can
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification for the Vpp pin
which must not be exceeded, even briefly, or permanent
10nly non "FF" bytes can be written.
seeQ
MD400083/-
Technology, Incorporated
6-142
EIM47F512
PRELIMINARY DATA SHEET
device damage may result. To minimize switching transients on this pin, we recommend using a minimum 0.1 IJf
decoupling capacitor with good high frequency response
connected from Vpp to ground at each device. In addition,
sufficient bulk capacitance should be provided to minimize
Vpp voltage sag when a device goes from standby to a
write or erase cycle.
Silicon Signature
contains data which identifies SEEQ as the manufacturer
and gives the product code. This allows device programmers to match the programming specification against the
product which is to be programmed.
Silicon Signature is read by raising address Ag to 12:t 0.5
volts and bringing all other address inputs, plus chip
enable, and output enable to V;L with Vee at 5 V. The two
Silicon Signature bytes are selected by address input Ao'
A row of fixed ROM is present in the E/M47F512 which
contains the device's Silicon Signature. Silicon Signature
Silicon Signature Bytes
Data (Hex)
Ao
SEEQ Code
VIL
94
Product Code 47F512
VIH
1A
Mode Selection Table
Mode
CE
OE
WE
Vpp
A O • 15
Do -7
Read
VIL
VIH
X
Address
X
X
X
X
DOUT
High Z
VIH
VIH
VIL
VIL
Vp
Address
Chip Erase Select
VIL
VIH
VIL
VIL
TTL
X
DIN
X
Chip Erase
VIL
VIH
VIL
Vp
X
'FF'
Standby
Byte Write
Absolute Maximum Stress Range*
Temperature
Storage ..................................... - 65°C to + 150°C
Under Bias ................................ -65°C to + 150°C
AI/Inputs except Vpp and
outputs with respect to Vss ........ +7 V to -0.5 V
E.S.D. Characteristics*
Symbol
Parameter
VZAP
E.S.D. Tolerance >2000 V
* Characterization data - not tested.
Vpp and Ag with respect to Vss .......................... 14 V
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
seeQ
MD400083/-
Value
Technology, Incorporated
6-143
Test Condition
MIL-STD 883
Method 3015
EIM47F512
PRELIMINARY DATA SHEET
Recommended Operating Conditions
E47F512
M47F512
Vcc Supply Voltage
5V ± 10%
5V ± 10%
Temperature Range
(Read mode)
-40°C to +85°C
-55°C to +125°C
Temperature Range
(Write/Erase mode)
25°C ±5°C
25°C ±5°C
Capacitance *
TA = 25°C. f =1 MHz
Value
Test Condition
Symbol
Parameter
C IN
Input Capacitance
6 pF
VIN = 0 V
C OUT
Output capacitance
12 pF
VI/o = 0 V
* This parameter is measured only for initial qualifications and
after process or design changes which may affect capacitance.
DC Operating Characteristics
Over specified Vcc and temperature range
Limits
Symbol
Parameter
Min.
Max.
Unit
III
Input Leakage
1
IlA
VIN = 0.1V to Vcc
I Lo
Output Leakage
10
IlA
VIN = 0.1 V to Vcc
Vp
Program/Erase Voltage
12.50
13.00
V
V pR
Vpp Voltage During Read
0
Vp
V
Ipp
Vp Current
200
200
30
60
IlA
IlA
mA
mA
CE = V IH • Vpp = V pR
Standby Mode
Read Mode
Byte Write
Chip Erase
Test Condition
CE = VIL' Vpp = VpR
Vpp = Vp
Vpp = Vp
Iccl
Standby Vcc Current
400
IlA
CE = Vcc -0.3V
Icc2
Standby Vcc Current
5
mA
40
mA
CE = V IH min.
CE = V IL
Icc3
Active V cc Current
V IL
Input Low Voltage
-0.3
0.8
V
V IH
Input High Voltage
2.0
7.0
V
VOL
Output Low Voltage
0.45
V OHl
Output Level (TTL)
V OH2
Output Level (CMOS)
seeQ
MD400083/-
V
IOL = 2.1 ma
2.4
V
IOH = -400 J,JA
Vcc -1.0
V
IOH = -100 J,JA
Technology, Incorporated
6-144
EIM47F512
PRELIMINARY DATA SHEET
READ
AC Characteristics
(Over specified Vcc and Temperature Range)
E/M47F512
-250
E47F512
-200
Symbol
Max.
Min.
Max.
E/M47F512
-300
Parameter
Min.
t RC
Read Cycle Time
200
tAA
Address to Data
200
250
300
ns
teE
CE to Data
OE to Data
tOF
OE/CE to Data Float
250
100
60
300
150
100
ns
tOE
200
75
50
tOH
Output Hold Time
250
0
0
Min.
Max.
Unit
300
ns
ns
ns
0
ns
Read Timing
110 0-7
t----t---t DF------i
WE
\Xxxx
XXYYJY
A. C. Test Conditions
Output Load: 1 TTL gate and C(load) = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45V to 2.4 V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
seeQ
MD4000B31-
Technology, Incorporated
6-145
EIM47F512
PRELIMINARY DATA SHEET
Byte Write
AC Characteristics
(Over specified Vcc and temperature range)
ElM47F512
Symboi
Parameter
Min.
t vps
tv PH
Vpp Setup Time
Vpp Hold Time
tcs
CE Setup Time
tCH
CE Hold Time
tOES
OE Setup Time
tOEH
t AS
OE Hold Time
tAH
Address Hold Time
tos
Data Setup Time
tOH
Data Hold Time
twp
WE Pulse Width
twc
Write Cycle Time
2
150
0
0
10
10
20
100
50
10
100
75
tWA
Write Recovery Time
Address Setup Time
Max.
Unit
Jls
Jls
ns
ns
ns
ns
ns
ns
ns
ns
ns
Jls
1.5
ms
NOTE: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the
user must provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device,
e.g. access time, erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.
Byte Write Timing
, =jxXXXXXXX
vpp
IVPH
ADDRESS
OE
WE
r-----1WR-----i
seeQ
MD400083/-
Technology, Incorporated
6-146
EIM47F512
PRELIMINARY DATA SHEET
Figure 1
EIM47F512 Write Algorithm
SET Vpp = Vp
WAITtvps J.1S
LOOP _ COUNT = 0
SET ADDRESS
1ST LOCATION
RE-WRITE
BYTE
FOR twellS
RE-WRITE
BYTE
FOR twc~s
SET ADDRESS
1ST LOCATION
RE·WRITE BYTE
FOR
tweJ.1S
WAIT tWRrns
WRITE BYTE
FOR t WCJ.1S
INC. ADDRESS
INCREMENT
ADDRESS
EIM47F512
PRELIMINARY DATA SHEET
Chip Erase
AC Characteristics
(Over specified Vcc and temperature range)
I
I
i
I
E/M47F512
Symbol
Parameter
t vps
2
J.1s
t VPH
Vpp Setup Time
Vpp Hold Time
500
ms
tcs
CE Setup Time
0
ns
0
ns
Min.
Max.
Unit
tOES
OE Setup Time
tos
Data Setup Time
50
ns
tOH
Data Hold Time
10
ns
twp
WE Pulse Width
100
ns
tCH
CE Hold Time
0
ns
tOEH
OE Hold Time
0
ns
tERASE
Chip Erase Time
500
ms
tER
Erase Recovery Time
250
Chip Erase Timing
seeQ
MD4000831-
Technology, Incorporated
6-148
ms
EIM47F512
PRELIMINARY DATA SHEET
Figure 2
EIM47F512 Chip Erase Algorithm
WRITE FF
TO ANY
ADDRESS
NO
seeQ
MD400083/-
Technology, Incorporated
6-149
EIM47F512
PRELIMINARY DATA SHEET
Ordering Information
D
T
M
T
iemperaiute
Package
Type
Range (Read)
D = Ceramic Dip
E = -40 to +85°C
L= Ceramic
Leadless Chip
Carrier
M =-55 to +125°C
47F512
-r
-250
Device
Access
Time
64K x8 FLASH
EPROM
MD400083/-
200 = 200 ns
(-40 to +85°C
Temp Range Only)
250 = 250 ns
300 = 300 ns
N = Plastic Leaded
Chip Carrier
(-40 to +85°C
Temp Range
Only)
seeQ
T
Technology, Incorporated
6-150
IB
T
Screening
MI L 883 Class
BScreened
(Optional)
seeQ
EIM48F512
512K CMOS FLASH EEPROM
October 1989
PRELIMINARY DATA SHEET
Block Diagram
Features
•
•
•
•
•
•
•
•
•
64K Byte Flash Erasable Non- Volatile Memory
FLASH EEPROM Cell Technology
Electrical Chip and 512 Byte Sector Erase
Input Latches for Writing and Erasing
-SS°C to + 125°C Temp Read (M48F512)
-SS°C to + 85°C Temp Write/Erase (M48F512)
-40°C to+ 85°C Temp ReadlWritelErase
(E48F512)
Ideal for Program and Data Storage Applications
• Minimum 100 Cycle Endurance
• Optional 1000 Cycle Endurance
• Minimum 10 Year Data Retention
ARRAY
128.512.8
Silicon Signature@
Pin Names *
COLUMN ADDRESS INPUT
Ao-A8
A g -A 1S
ROW ADDRESS INPUT
CE
CHIP ENABLE
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/°0 _7
DATA INPUT (WRITE)/OUTPUT (READ)
1/0 0-7
N.C.
NO INTERNAL CONNECTION
Vpp
WRITEIERASE INPUT VOLTAGE
Pin Configurations
*Note: Pin 30 on the PLCC package is a DON'T CONNECT.
32 PIN FLATPACK
TOP VIEW
LEADLESS CHIP CARRIER
TOP VIEW
INDEX
CORNER\
];f~ >'t. »I~ 0z
32
Vcc
2
31
WE
3
30
NC
4
29
A7
A14
A14
5
28
A14
A 13
A6
A
A 13
6
27
A8
AS
A8
A8
7
26
Ag
25
A4
Ag
Ag
8
AU
9
24
Of
A3
All
10
23
Al0
A2
Oe
11
22
CE
12
21
V07
13
20
V06
14
19
V05
15
18
V04
16
17
V03
WE
NC
13
Al
A 10
Ao
CE
1100
110
7
r.;, r.;;, roO' r,:::., roO'
1_11_1 I_I 1_11_1
Silicon Signature is a registered trademark of SEEQ Technology.
MD400068/A
Vee
1
§ ~
SeeQ
DUAL-IN-L1NE
TOP VIEW
Technology, Incorporated
6-151
ro,
!'-IINI
1;;;'
~ '5,'" '5,'" ~
g
A11
Oe
A 10
CE
1107
110 6
110 5
1104
1103
EIM48F512
PRELIMINARY DATA SHEET
Description
The ElM48F512 is a 512K bit CMOS FLASH EEPROM organized as 64K x 8 bits and specified over the Industrial/
Military Temperature Range. SEEQ's ElM48F512 brings
together the high density and cost effectiveness of
UVEPROMs, with the electrical erase, in-circuit reprogrammabiiity and package options of EEPROMs.
SEEQ's patented split gate FLASH EEPROM cell design
reduces both the time and cost required to alter code in
program and data storage applications.
The E/M48F512's fast electrical erase and 0.5 ms/byte
programming is 20 times faster than reprogramming of
UVEPROMs. Electrical erase and reprogramming make
the ElM48F512 ideal for applications with high density requirements, but where ultraviolet erasure is either impractical or impossible.
SEEQ's FLASH memories provide users with the flexibility
to alter code in all or small sections of the memory array.
The memory array is divided into 128 sectors, with each
sector containing 512 bytes. Each sector can be individually erased, or the chip can be bulk erased before reprogramming.
On-chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to perform other
tasks once write/erase cycles have been initiated.
Endurance, the number of times each byte can be written,
is specified at 100 cycles with an optional screen for 1000
cycles available. Electrical write/erase capability allows
the E/M48F512 to accommodate a wide range of plastic,
ceramic and surface mount packages.
Read
Reading is accomplished by presenting a valid address on
Ao - A,s with chip enable (CE) and output enable (OE) at ~L
and write enable (WE) at V1H • The Vpp pin can be at any
TTL level or Vp during read operations. See page 5 for
additional information on A. C. parameters and read timing
waveforms.
Erase and Write
Erasing and writing of the E/M48F512 can only be accomplished when Vpp = Vp. Latches on address, data and
control inputs permit erasing and writing using normal
microprocessor bus timing. Address inputs are latched on
the falling edge of write enable or chip enable, whichever
is later, while data inputs are latched on the rising edge of
write enable or chip enable, whichever is earlier. All control
pins are noise protected; a pulse of less than 20 ns will not
1
initiate a write or erase. In addition, chip enable, output
enable and write enable must be in the proper state to
initiate a write or erase. Timing diagrams depict write
enable controlled writes; the timing also applies to chip
enable controlled writes.
Sector Erase
Sector erase changes all bits in a sector of the array to a
logical one. It requires that the Vpp pin be brought to a high
voltage and a write cycle performed. The sector to be
erased is defined by address inputs Ag through A ,S' The
data inputs must be all ones to begin the erase. Following
a write of 'FF', the part will wait for time tABORT to allow
aborting the erase by writing again. This permits recovering from an unintentional sector erase if, for example, in
loading a block of data a byte of 'FF' was written. After the
tABORT delay, the sector erase will begin. The erase is accomplished by following the erase algorithm in figure 2.
Vpp can be brought to any TTL level or left at high voltage
after the erase.
Chip Erase
Chip erase will change all bits in the memory to a logical 1.
The E/M48F512 uses a two-step, software controlled looping algorithm to perform the chip erase operation. Each
loop requires that a chip erase select be performed prior to
the start of each chip erase cycle.
Byte Write
A byte write is used to change any 1 in a byte to a
Data is organized in the E/M48F512 in a group of bytes
called a sector. The memory array is divided into 128
sectors of 512 bytes each. Individual bytes are written as
part of a sector write operation. Sectors need not be
written separately; the entire device or any combination of
sectors can be written using the write algorithm.
The ElM48F512 uses a software controlled looping algorithm (figure 1) to perform writes and verify successful byte
programming. During a byte write operation, all non "FF'"
bytes are incrementally written using a 7511S minimum twc.
Each byte write is automatically latched and timed on-chip,
so that the microprocessor can perform other tasks once
the write cycle has been initiated. Write cycle time dura-
Only non "FF" bytes can be written.
seeQ
MD400068/A
o.
Individual bytes, multiple bytes or the entire memory can
be written at one time. If a bit in a byte needs to be changed
from a 0 to a 1, the byte must first be erased via sector or
chip erase and then reprogrammed with the desired data.
Any byte write operation requires that the Vpp pin be at
high voltage (Vp).
Technology, Incorporated
6-152
EIM48F512
PRELIMINARY DATA SHEET
tion can be controlled by the microprocessor, or the onchip timer will automatically terminate twe after 150 JJs.
One write loop has been completed when all non "FF" data
for all desired bytes have been written. After 7 programming loops, a read-verification cycle is performed. For any
bytes which do not verify, a fill-in programming loop is
performed.
Because bytes can only be written as part of a sector write,
if data is to be added to a partially written sector or one or
more bytes in a sector must be changed, the contents of
the sectors must first be read into system RAM; the bytes
can then be added to the block of data in RAM and the
sector written using the sector write algorithm.
any control input (CE, OE, WE) is in the wrong state for
writing or erasing (see mode table).
High Voltage Input Protection
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification which must
notbe exceeded, even briefly, orpermanent device damage
may result. To minimize switching transients on this pin we
recommend using a minimum O. 1 uf decoupling capacitor
with good high frequency response connected from Vpp to
ground at each device. In addition, sufficient bulk capacitance should be provided to minimize Vpp voltage sag
when a device goes from standby to a write or erase cycle.
Power Up/Down Protection
Silicon Signature
This device contains a Vee sense circuit which disables
internal erase and write operations when Vee is below 3.5
volts. In addition, erases and writes are prevented when
A row of fixed ROM is present in the EIM48F512 which
contains the device's Silicon Signature. Silicon Signature
contains data which identifies SEEQ as the manufacturer
and gives the product code. This allows device programmers to match the programming specification against the
product which is to be programmed.
Silicon Signature Bytes
Data (Hex)
Ao
VIL
VIH
SEEQCode
Product Code 48F512
Silicon Signature is read by raising address A9 to 12 ± 0.5
V and bringing all other address inputs, plus chip enable,
and output enable to V,L with Vee at 5 V. The two Silicon
Signature bytes are selected by address input Ao'
94
1A
Mode Selection Table
Mode
CE
OE
WE
Vpp
Ag • 15
Read
VIL
VIL
VIH
Address
Standby
VIH
X
X
X
X
X
X
DOUT
High Z
Byte Write
VIL
VIH
VIL
Vp
Address
Address
DIN
Chip Erase Select
VIL
VIH
VIL
TIL
V1L
V1H
V1L
Vp
Block Erase
VIL
VIH
VIL
Vp
Address
X
X
X
X
Chip Erase
X
X
Absolute Maximum Stress Range*
Temperature
Storage ..................................... -65°C to +150°C
Under Bias ................................ -65°C to + 150°C
All Inputs except Vpp and
outputs with Respect to Vss ........ +7 V to -0.5 V
Vpp pin with respect to Vss .......................... 14 V
seeQ
MD4000681A
Do .7
Ao.a
Address
'FF'
'FF'
E.S.D. Charateristics l1]
Symbol
VZAP
Parameter
Value
E.S.D. Tolerance >2000 V
Test Condition
MIL-STD 883
Method 3015
Note 1: Characterization data - not tested.
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Technology, Incorporated
6-153
EIM48F512
PRELIMINARY DATA SHEET
Recommended Operating Conditions
E48F512
M48F512
Vee Supply Voltage
5V ± 10%
5V
Temperature Range
(Read mode)
-40°C to +85°C
-55°C to +125°C
Temperature Range
(Write/Erase mode)
-40°C to +85°C
-55°C to +S5°C
Capacitance[2}
± 10%
TA = 25°C, f =1 MHz
Value
Test Condition
Symbol
Parameter
C IN
Input Capacitance
6 pF
V IN = 0 V
C OUT
Output capacitance
12 pF
VI/o = 0 V
Note 2: This parameter is only sampled and not 100% tested.
DC Operating Characteristics
Over the Vee and temperature range
Limits
Symbol
Parameter
III
Input Leakage
ILO
Output Leakage
Min.
Vp
Program/Erase Voltage
V pR
V pp Voltage During Read
Ipp
Vp Current
Max.
Unit
1
IlA
10
IlA
Test Condition
V IN = 0.1V toVee
V IN = 0.1V toVee
11.4
13
V
0
Vp
V
Standby Mode
Read Mode
Byte Write
200
200
40
IlA
IlA
rnA
CE = V IH ' Vpp = V pR
CE = V IL ' Vpp = VpR
Vpp = Vp
Chip Erase
Sector Erase
SO
15
rnA
rnA
Vpp = Vp
Vpp = Vp
lecl
Standby Vee Current
400
IlA
CE = Vee -0.3V
lec2
Standby Vee Current
5
rnA
CE = VIHmin.
lec3
V IL
V IH
Active Vee Current
60
rnA
CE
O.S
V
7.0
V
VOL
Output Low Voltage
V OHl
Output Level (TTL)
V OH2
Output Level (CMOS)
seeQ
MD4000681A
Input Low Voltage
-0.3
Input High Voltage
2.0
= V IL
V
IOL = 2.1 rna
2.4
V
IOH = -400 IJA
V ee-1.0
V
IOH = -100 IJA
0.45
Technology, Incorporated
6-154
EIM48F512
PRELIMINARY DATA SHEET
READ
AC Characteristics
(Over the Vcc and temperature range)
E48F512
-200
Symbol
Parameter
Min.
t RC
Read Cycle Time
200
tAA
Address to Data
E/M48F512
-250
Max.
Min.
Max.
E/M48F512
-300
Min.
Unit
Max.
300
250
ns
ns
tCE
250
250
300
CE to Data
200
200
300
ns
tOE
OE to Data
75
100
150
ns
tOF
OE/CE to Data Float
50
60
100
ns
tOH
Output Hold Time
0
0
0
ns
Read Timing
AOOR=~~~:~[=~~_~=~~=.=!=_t~~~~~~~~~~~~XXXXX
1/0 0-7
1'4--t---tDF--~
WE
,«xxx
Xx~XY
A. C. Test Conditions
Output Load: 1 TTL gate and C(load) = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45V to 2.4 V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs 0.8V and 2V
seeQ
MD4000681A
Technology, Incorporated
6-155
EIM48F512
PRELIMINARY DATA SHEET
Byte Write
AC Characteristics
(Over the Vcc and temperature range)
ElM48F512
Symbol
Parameter
Min.
t vps
Vpp Setup Time
t VPH
Vpp Hold Time
Ils
Ils
tcs
CE Setup Time
tCH
CE Hold Time
tOES
OE Setup Time
tOEH
t AS
OE Hold Time
Address Setup Time
2
150
0
0
10
10
20
tAH
Address Hold Time
100
ns
tos
Data Setup Time
50
10
100
75
ns
tOH
Data Hold Time
twp
WE Pulse Width
twc
Write Cycle Time
tWR
Write Recovery Time
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
J,Ls
1.5
ms
NOTE: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the
user must provide a valid state on that input or wait for the state minimum time to assure proper operation~ All outputs from the device,
e.g. access time, erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.
Byte Write Timing
seeG
MD4000681A
Technology, Incorporated
6-156
EIM48F512
PRELIMINARY DATA SHEET
Figure 1
ElM48F512 Write Algorithm
SETVpp=Vp
WAIT tvps lIS
LOOP _ COUNT = 0
SET ADDRESS
1ST LOCATION
RE-WRITE
BYTE (4X)
FOR twellS
SET ADDRESS
RE-WRITE BYTE
FOR
twellS
WAIT t WRrns
1ST LOCATION
WRITE BYTE
FOR twe lIS
INC. ADDRESS
INCREMENT
ADDRESS
INCREMENT
LOOP _COUNT
YES
END
NO
INCREMENT
LOOP_COUNT
WAIT t WRrns
LOOP_COUNT = 0
NO
seeQ
MD4000681A
YES
Technology, Incorporated
6-157
DEVICE
FAILED
EIM48F512
PRELIMINARY DATA SHEET
Sector Erase
AC Characteristics
(Over the Vee and temperature range)
E/M48F512
Symbol
Parameter
Min.
t vps
Vpp Setup Time
t VPH
Vpp Hold Time
2
500
Max.
Unit
tcs
CE Setup Time
OE Setup Time
a
a
ns
tOEs
tAS
Address Setup Time
20
ns
tAH
Address Hold Time
100
ns
tos
Data Setup Time
50
ns
tOH
Data Hold Time
10
ns
twp
WE Pulse Width
100
ns
tCH
CE Hold Time
tOEH
OE Hold Time
a
a
ns
tERASE
Sector Erase Time
tABORT
Sector Erase Delay
tER
Erase Recovery Time
Ils
ms
ns
ns
500
ms
250
250
Ils
ms
Sector Erase Timing
Vpp
Roo~~:t=~==~~~~~~~~~~r------nJ~~~~~~~dooooooo~
ADDRESSES ~~'~--+-+-
__.f~~D.L~:lODt.:.~ru.:.~~~\'_ _ _~~\D.L.~OL~~>DJ.~D.L.~:lOOL'J:j,J.~oc.
NEXT LOOP
lS1LOOP
seeQ
MD4000681A
Technology, Incorporated
6-158
EIM48F512
PRELIMINARY DATA SHEET
Figure 2
EIM48F512 Sector Erase Algorithm
WAITIER ms
THEN VERIFY
ALL BYTES - FF
SErVpp=Vp
WAlTlvps lIS
WRITEFF
TO SECTOR
ADDRESS
NO
L=24
seeQ
A4D4000681A
Technology. Incorporated
6-159
EIM48F512
PRELIMINARY DATA SHEET
Chip Erase
AC Characteristics
(Over the Vee and temperature range)
E/M48F512
Min.
Max.
Unit
Symbol
Parameter
t vps
Vpp Setup Time
2
t VPH
Vpp Hold Time
500
Ils
ms
tcs
CE Setup Time
0
ns
tOES
OE Setup Time
0
ns
tos
Data Setup Time
50
ns
tOH
Data Hold Time
10
ns
twp
WE Pulse Width
100
ns
tCH
CE Hold Time
0
ns
tOEH
OE Hold Time
0
ns
tERASE
Chip Erase Time
500
ms
tER
Erase Recovery Time
250
Chip Erase Timing
seeQ
MD4000681A
Technology, Incorporated
6-160
ms
EIM48F512
PRELIMINARY DATA SHEET
Figure 3
EIM48F512 Chip Erase Algorithm
WAITtER ms
THEN VERIFY
ALL BYTES - FF
SET
LOOP_COUNT - 0
WRITEFF
TO ANY
ADDRESS
WRITEFF
TO ANY
ADDRESS
NO
L=24
seeQ
MD4000681A
Technology, Incorporated
6-161
EIM48F512
PRELIMINARY DATA SHEET
Ordering Information
D
M
T
T
Package
Type
Temperature
= Ceramic
Leadless Chip
Carrier
T
Device
Endurance
Ra!"!g~
D = Ceramic Dip
L
K
48F512
-r
64KxS FLASH
EEPROM
BLANK = 100
K = 1000
M = -55 to +125°C
(Read)
-55 to +S5°C
(Write/Erase)
Access
Time
200 = 200 ns
(-40 to +S5°C
Temp Range Only)
300 = 300 ns
N = Plastic Leaded
Chip Carrier
(-40 to +S5°C
Temp Range
Only)
MD4000681A
T
250 = 250 ns
F = Flatpack
seeQ
-250
Technology, Incorporated
6-162
IB
T
Screening
MIL 883 Class
BScreened
(Optional)
seeQ
EIM47F010
1024K Bit CMOS Flash EPROM
October 1989
PRELIMINARY DATA SHEET
Features
Block Diagram
•
128K Byte Flash Erasable Non-Volatile Memory
•
Input Latches for Writing and Erasing
•
Fast Byte Write: 225 ps max
•
-55°C to +125°C Temp Read (M47F010)
•
-40°C to +85°C Temp Read (E47F010)
•
25°C ± 5°C Temp Write/Erase
•
Ideal for Low-Cost Program Storage Applications
• In-Circuit Alterable
• 100 Program/Erase Cycles
• Minimum 10 Year Data Retention
•
JEDEC Standard Byte Wide Pinout
• 32PinPLCC
• 32 Pin Dip
• 32PadLCC
•
Silicon Signature@
ARRAY
128Kx8
Pin Names
Ao-A9
A10 -A 16
COLUMN ADDRESS INPUT
CE
CHIP ENABLE
1100•7
ROW ADDRESS INPUT
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00-7
DATA INPUT (WRITE)/OUTPUT (READ)
N.C.
NO INTERNAL CONNECTION
Vpp
WRITE/ERASE INPUT VOLTAGE
D.U.
DON'T USE
Pin Configurations
PLASTIC LEADED CHIP CARRIER
TOP VIEW
i\
INDEX
CORNER
9
2
~
N
II)
fL ~ ~ ~
A7
A13
DUAL-IN-LlNE
TOP VIEW
LEADLESS CHIP CARRIER
TOP VIEW
Technology, Incorporated
6-163
VOs
EIM47F010
PRELIMINARY DATA SHEET
Description
The ElM47F01 0 is a 1024K bit CMOS FLASH EPROM organized as 128K x 8 bits and specified over the IndustrialI
Military Temperature Range. The ElM47F010 brings together the high density and cost effectiveness of
UVEPROMs with the in-circuit reprogrammability and
package options of fuli featured EEPROMs. SEEO's
patented splitgate Flash EPROM cell design reduces both
the time and cost required to alter code in program and
data storage applications.
The ElM47F010's fast electrical erase and 0.2 ms/byte
programming is 20 times faster than reprogramming of
UVEPROMs. Electrical erase and reprogramming make
the EIM47F01 0 ideal for applications with high density requirements, but where ultraviolet erasure is either impractical or impossible.
On chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to perform other
tasks once writelerase cycles have been initiated. Endurance, the number of times each byte can be written and
erased, is specified at 100 cycles. Electrical erase allows
the EIM47F010 to be packaged in a wide range of windowless plastic, ceramic and surface mount packages.
Read
Reading is accomplished by presenting a valid address on
Ao - A'6 with chip enable (CE) and output enable (OE) at
VtL and write enable (WE) at V1ft. The Vpp pin can be at
any TTL level or Vp during read operations. See page 5
for additional information on A.C. parameters and read
timing waveforms.
Erase and Write
Erasing and writing of the EIM47F01 0 can only be accomplishedwhen Vpp= Vp. Latches on address, data and control inputs, permit erasing and writing using normal microprocessor bus timing. Address inputs are latched on the
falling edge of write enable or chip enable, whichever is
later. While data inputs are latched on the rising edge of
write enable orchip enable, whichever is earlier. The write
enable input is noise protected; a pulse of less than 20 ns
will not initiate a write or erase. In addition, chip enable,
output enable and write enable pins must be in the proper
state to initiate a write or erase. Timing diagrams depict
write enable controlled writes; the timing also applies to
chip enable controlled writes.
The ElM47F01 0 uses a software controlled looping algorithm (figure 1) to perform writes and verify successful byte
programming. During a byte write operation, all non tiFF'"
bytes are incrementally written using a 75 JiS minimum t we '
Each byte write is automatically latched and timed on-chip,
so that the microprocessor can perform other tasks once
the write cycle has been initiated. Write cycle time duration can be controlled by the microprocessor, or the onchip timer will automatically terminate twe after 150 Jis.
One write loop has been completed when all non "FF" data
for all desired bytes have been written. After 3 programming loops, a read-verification cycle is performed. For any
bytes which do not verify, a fill-in programming loop is
performed.
Chip Erase
Chip Erase will change all bits in the memory to a logical
1. The EIM47F010 uses a two-step, software controlled
looping algorithm to perform the chip erase operation.
Each loop requires that a chip erase select be performed
prior to the start of each chip erase cycle.
The chip erase select is activated by initiating a write cycle
with the Vpp pin at ~H or lower. During the chip erase
select, address and data lines can be at any TTL level.
Following a chip erase select, the EIM47F010 will start
chip erase if all data inputs are tiFF': Vpp = Vp and a write
cycle initiated. After 20 loops, a device erase verify is
performed to insure all bytes = tiFF". After erase, the Vpp
pin can be brought to any TTL level or left at high voltage.
Refer to page 8 for chip erase timing diagram and figure 2
for the erase algorithm.
Power Up/Down Protection
This device contains a sense circuit which disables internal erase and write operations when Vee is below 3.5 volts.
In addition, erases and writes are prevented when any
control input (CE, OE, WE) is in the wrong state for writing
lerasing (see mode table).
High Voltage Input Protection
Byte Write
A byte write is used to change any 1 in a byte to a O.
Individual bytes, multiple bytes or the entire memory can
I
be written at one time. If a bit in a byte needs to be changed
from a 0 to a 1, the ElM47F01 0 must firstbe erased via chip
erase and then reprogrammed with the desired data. Any
byte write operation requires that the Vpp pin be at high
voltage (Vp).
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification for the Vpp
pin which must not be exceeded, even briefly, or perma-
Only non tiFF" bytes can be written.
seeQ
MD4000841-
Technology, Incorporated
6-164
EIM47F010
PRELIMINARY DATA SHEET
nent device damage may result. To minimize switching
transients on this pin, we recommend using a minimum 0.1
Jlf decoupling capacitor with good high frequency response connected from Vpp to ground at each device. In
addition, sufficient bulk capacitance should be provided to
minimize Vpp voltage sag when a device goes from
standby to a write or erase cycle.
Silicon Signature
contains data which identifies SEEQ as the manufacturer
and gives the product code. This allows device programmers to match the programming specification against the
product which is to be programmed.
Silicon Signature is read by raising address Ag to 12:t 0.5
volts and bringing all other address inputs, plus chip
enable, and output enable to ~L with Vee at 5 V. The two
Silicon Signature bytes are selected by address input Ao.
A row of fixed ROM is present in the EIM47F010 which
contains the device's Silicon Signature. Silicon Signature
Silicon Signature Bytes
Ao
V IL
V IH
SEEQ Code
Product Code 47F010
Data (Hex)
94
1C
Mode Selection Table
Mode
CE
OE
WE
Vpp
A O • 16
Do -7
Read
VIL
VIH
X
VIL
VIL
VIL
Address
Chip Erase
VIL
X
VIH
VIH
VIH
X
Chip Erase Select
VIL
VIH
VIL
VIL
Standby
Byte Write
Absolute Maximum Stress Range*
Temperature
Storage ..................................... -65°C to +150°C
Under Bias ................................ -65°C to + 150°C
All Inputs except Vpp and
outputs with respect to Vss ........ +7 V to -0.5 V
X
X
Dour
High Z
Vp
Address
DIN
TTL
X
X
Vp
X
'FF'
E.S.D. Characteristics*
Symbol
Parameter
V ZAP
E.S.D. Tolerance >2000 V
* Characterization data - not tested.
Vpp and Ag with respect to Vss .......................... 14 V
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
seeQ
MD4000841-
Value
Technology, Incorporated
6-165
Test Condition
MIL-STD 883
Method 3015
EIM47F010
PRELIMINARY DATA SHEET
Recommended Operating Conditions
E47F010
M47F010
Vcc Supply Voltage
5V ± 10%
5V ± 10%
Temperature Range
(Read mode)
-40°C to +85°C
-55°C to +125°C
Temperature Range
(Write/Erase mode)
25°C ±5°C
25°C ±5°C
Capacitance"
TA = 25°C, f =1 MHz
Symbol
Parameter
Value
Test Condition
CIN
Input Capacitance
6 pF
VIN = 0 V
COUT
Output Capacitance
12 pF
VI/o = 0 V
* This parameter is measured only for initial qualifications and
after process or design changes which may affect capacitance.
DC Operating Characteristics
Over specified Vcc and temperature range
Limits
Symbol
Parameter
Max.
Unit
Test Condition
ILl
I LO
Input Leakage
1
VIN = 0.1V to Vcc
Output Leakage
10
Il A
Il A
Vp
Program/Erase Voltage
12.50
13.00
V
0
Vp
V
200
200
30
60
Il A
Il A
mA
mA
Min.
V pR
Vpp Voltage During Read
Ipp
Vp Current
Standby Mode
Read Mode
Byte Write
Chip Erase
VIN = 0.1 V to Vcc
CE = VIH ' Vpp = VpR
CE = VIL' Vpp = VpR
Vpp = Vp
Vpp = Vp
Icci
Standby Vcc Current
400
!lA
CE = Vcc -fl.3V
Icc2
Standby Vcc Current
5
mA
Icc3
VIL
VIH
Active Vcc Current
40
mA
CE = VIH min.
CE = VIL
VOL
V OH1
V OH2
Output Low Voltage
seeQ
MD400084/-
Input Low Voltage
-fl.3
0.8
V
Input High Voltage
2.0
7.0
V
0.45
Output Level (TTL)
Output Level (CMOS)
V
IOL = 2.1 ma
2.4
V
IOH = -400 IJA
Vcc -1.0
V
IOH = -100 IJA
Technology, Incorporated
6-166
EIM47F010
PRELIMINARY DATA SHEET
READ
AC Characteristics
(Over specified Vcc and Temperature Range)
E/M47F010
-250
E47F010
-200
Symbol
Parameter
Min.
t Rc
Read Cycle Time
200
tAA
Address to Data
tCE
CE to Data
tOE
OE to Data
tOF
OE/CE to Data Float
tOH
Output Hold Time
Max.
Min.
Max.
250
Min.
0
Max.
Unit
300
ns
300
300
150
100
250
250
100
60
200
200
75
50
0
E/M47F010
-300
ns
ns
ns
ns
0
ns
Read Timing
ADDRESS
~
XXXx
I------~- t R C - - - - - - - I 1 n
Ir---------~mxxxxxxx
f-oI----- tAA --~.I
1/°0-7
1--4---tDF---.j
WE
\XXXX
XXXXYY
A.C. Test Conditions
Output Load: 1 TTL gate and C(load) = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45V to 2.4 V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
seeQ
MD4000B4/-
Technology, Incorporated
6-167
EIM47F010
PRELIMINARY DATA SHEET
Byte Write
AC Characteristics
(Over specified Vcc and temperature range)
ElM47F010
Symbol
Parameter
t vps
V pp
Setup Time
t VPH
Vpp
Hold Time
tcs
CE Setup Time
tCH
CE Hold Time
tOES
OE Setup Time
tOEH
OE Hold Time
t AS
Address Setup Time
tAH
Address Hold Time
tos
Data Setup Time
tOH
Data Hold Time
twp
WE Pulse Width
twc
Write Cycle Time
tWR
Write Recovery Time
Min.
Max.
Unit
2
150
0
0
10
10
20
100
50
10
100
75
Il s
Ils
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ils
1.5
ms
NOTE: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the
user must provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device,
e.g. access time, erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.
Byte Write Timing
vpp
ADDRESS
t----'WR---+i
seeQ
MD400084/-
Technology, Incorporated
6-168
EIM47F010
PRELIMINARY DATA SHEET
Figure 1
EIM47F010 Write Algorithm
RE-WRITE
BYTE
FOR twc}1S
SET ADDRESS
1ST LOCATION
SET ADDRESS
1ST LOCATION
RE-WRITE BYTE
FOR
twcllS
WAIT twRms
INCREMENT
ADDRESS
YES
INCREMENT
LOOP_COUNT
YES
seeQ
MD400084/-
Technology, Incorporated
6-1 69
EIM47F010
PRELIMINARY DATA SHEET
Chip Erase
AC Characteristics
(Over specified Vcc and temperature range)
ElM471=010
..
Symbol
t vps
Parameter
Min.
Vpp Setup Time
t VPH
Vpp Hold Time
2
500
0
tcs
CE Setup Time
tOES
OE Setup Time
tos
Data Setup Time
tOH
Data Hold Time
twp
WE Pulse Width
tCH
CE Hold Time
tOEH
OE Hold Time
tERASE
Chip Erase Time
tER
Erase Recovery Time
MD400084/-
J.Ls
ns
ns
ns
ns
ns
ns
ns
ms
250
Technology, Incorporated
6-170
Unit
ms
0
50
10
100
0
0
500
Chip Erase Timing
seeQ
Max.
ms
EIM47F010
PRELIMINARY DATA SHEET
Figure 2
EIM47F010 Chip Erase Algorithm
SETVpp • Vp
WAITtvps f1S
INCREMENT
LOOP_COUNT
NO
L=20
seeQ
A4D400084~
Technology, Incorporated
6-171
EIM47F010
PRELIMINARY DATA SHEET
Ordering Information
o
T
M
T
-r-
47F010
-250
Access
TIme
Package
Type
Temperature
Range (Read)
Device
D = Ceramic Dip
E = -40 to +85°C
128K x 8 FLASH
EPROM
L = Ceramic
Leadless Chip
Carrier
M =-55 to +125°C
MD400084/-
200 = 200 ns
(-40 to +85°C
Temp Range Only)
250 = 250 ns
300 = 300 ns
N = Plastic Leaded
Chip Carrier
(-40 to +85°C
Temp Range
Only)
seeQ
T
Technology, Incorporated
6-172
18
T
Screening
MIL 883 Class
8 Screened
(Optional)
seeQ
EIM48F010
1024K CMOS FLASH EEPROM
October 1989
PRELIMINARY DATA SHEET
Block Diagram
Features
•
128K Byte FLASH Erasable Non-Volatile Memory
•
FLASH EEPROM Cell Technology
•
Electrical Chip and 1024 Byte Sector Erase
•
Input Latches for Writing and Erasing
•
-55°C to +125°C Temp Read (M48F010)
•
-55°C to +85°C Temp Write/Erase (M48F010)
•
•
-40°C to +85°C Temp Read/Wrlte/Erase
(E48F010)
Ideal for Program and Data Storage Applications
• Minimum 100 Cycle Endurance
• Optional 1000 Cycle Endurance
• Minimum 10 Year Data Retention
•
Silicon Signature@
ARRAY
128.1024.8
Pin Names'"
AO-Ag
A10 -A 16
COLUMN ADDRESS INPUT
CE
CHIP ENABLE
ROW ADDRESS INPUT
1/°0·7
OE
OUTPUT ENABLE
WE
WRITE ENABLE
1/00•7
N.C.
DATA INPUT (WRITE)/OUTPUT (READ)
Vpp
WRITE/ERASE INPUT VOLTAGE
NO INTERNAL CONNECTION
Pin Configurations
*Note: Pin 30 on the PLCC package is a DON'T CONNECT.
32 PIN FLATPACK
TOP VIEW
LEADLESS CHIP CARRIER
TOP VIEW
l
INDEX
CORNER
1
32
Vcc
2
31
WE
3
30
NC
04
29
5
28
6
Z1
7
26
8
26
9
24
10
23
11
22
12
21
13
20
104
19
15
18
16
17
N."
0
I
f:!l f~l f~l f61 f§l ~1 f~l
§ §
MD400069/A
0..
All
Silicon Signature is a registered trademark of SEEQ Technology.
seeQ
'"
0
«
<
»0.."0 ' ~
Z
Technology, Incorporated
6-173
~ g'"
g
~
g
DUAL-IN-LiNE
TOP VIEW
EIM48F010
PRELIMINARY DATA SHEET
Description
The ElM48F010 is a 1024K bit CMOS FLASH EEPROM
organized as 128K x 8 bits and specified over the Industrial/Military Temperature Range. SEEQ's ElM48F010
brings together the high density and cost effectiveness of
UVEPROMs, with the electrical erase, in-circuit reprogrammabiiiiy and package options of EEPROMs.
pins are noise protected; a pulse of less than 20 ns will not
initiate a write or erase. In addition, chip enable, output
enable and write enable must be in the proper state to
initiate a write or erase. Timing diagrams depict write
enable controlled writes; the timing also applies to chip
enable controlled writes.
SEEQ's patented split gate FLASH EEPROM cell design
reduces both the time and cost required to alter code in
program and data storage applications.
Sector Erase
The E/M48F010's fast electrical erase and 0.5 mslbyte
programming is 20 times faster than reprogramming of
UVEPROMs. Electrical erase and reprogramming make
the EIM48FO 10 ideal for applications with high density requirements, but where ultraviolet erasure is either impractical or impossible.
SEEQ's FLASH memories provide users with the flexibility
to alter code in all or small sections of the memory array.
The memory array is divided into 128 sectors, with each
sector containing 1024 bytes. Each sector can be individually erased, or the chip can be bulk erased before reprogramming.
On-chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to perform other
tasks once write/erase cycles have been initiated.
Endurance, the number of times each byte can be written,
is specified at 100 cycles with an optional screen for 1000
cycles available. Electrical write/erase capability allows
the EIM48FO 10 to accommodate a wide range of plastic,
ceramic and surface mount packages.
Read
Reading is accomplished by presenting a valid address on
Ao - A with chip enable (CE) and output enable (DE) at V'L
'6
and write enable (WE) at V'H' The Vpp pin can be at any
TTL level or Vp during read operations. See page 5 for
additional information on A. C. parameters and read timing
waveforms.
Erase and Write
Erasing and writing of the ElM48F01 0 can only be accomplished when Vpp = Vp. Latches on address, data and
control inputs permit erasing and writing using normal
microprocessor bus timing. Address inputs are latched on
the falling edge of write enable or chip enable, whichever
is later, while data inputs are latched on the rising edge of
write enable or chip enable, whichever is earlier. All control
1
Sector erase changes all bits in a sector of the array to a
logical one. It requires that the Vpp pin be brought to a high
voltage and a write cycle performed. The sector to be
erased is defined by address inputs Ag through A'6" The
data inputs must be all ones to begin the erase. Following
a write of 'FF', the part will wait for time tABORT to allow
aborting the erase by writing again. This permits recovering from an unintentional sector erase if, for example, in
loading a block of data a byte of 'FF' was written. After the
tABORT delay, the sector erase will begin. The erase is accomplished by following the erase algorithm in figure 2.
Vpp can be brought to any TTL level or left at high voltage
after the erase.
Chip Erase
Chip erase will change all bits in the memory to a logical 1.
The ElM48FO 10 uses a two-step, software controlled looping algorithm to perform the chip erase operation. Each
loop requires that a chip erase select be performed prior to
the start of each chip erase cycle.
Byte Write
A byte write is used to change any 1 in a byte to a O.
Individual bytes, multiple bytes or the entire memory can
be written atone time. If a bitin a byte needs to be changed
from a 0 to a 1, the byte must first be erased via sector or
chip erase and then reprogrammed with the desired data.
Any byte write operation requires that the Vpp pin be at
high voltage (Vp).
Data is organized in the E/M48F010 in a group of bytes
called a sector. The memory array is divided into 128
sectors of 1024 bytes each. Individual bytes are written as
part of a sector write operation. Sectors need not be
written separately; the entire device or any combination of
sectors can be written using the write algorithm.
The ElM48F01 0 uses a software controlled looping algorithm (figure 1) to perform writes and verify successful byte
programming. During a byte write operation, all non "FF'"
bytes are incrementally written using a 75 J.ls minimum twe'
Each byte write is automatically latched and timed on-chip,
Only non "FF" bytes can be written.
seeQ
MD400069/A
Technology, Incorporated
6-174
EIM48F010
PRELIMINARY DATA SHEET
High Voltage Input Protection
so that the microprocessor can perform other tasks once
the write cycle has been initiated. Write cycle time duration can be controlled by the microprocessor, or the onchip timer will automatically terminate twe after 150 Jis.
One write loop has been completed when all non "FF" data
for all desired bytes have been written. After 7 programming loops, a read-verification cycle is performed. For any
bytes which do not verify, a fill-in programming loop is
performed.
Because bytes can only be written as part of a sector write,
if data is to be added to a partially written sector or one or
more bytes in a sector must be changed, the contents of
the sectors must first be read into system RAM; the bytes
can then be added to the block of data in RAM and the
sector written using the sector write algorithm.
Silicon Signature Bytes
Ao
V IL
V IH
SEEQCode
Product Code 48F010
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification which must
notbe exceeded, even briefly, orpermanentdevice damage
may result. To minimize switching transients on this pin we
recommend using a minimum O. 1 uf decoupling capacitor
with good high frequency response connected from Vpp to
ground at each device. In addition, sufficient bulk capacitance should be provided to minimize Vpp voltage sag
when a device goes from standby to a write or erase cycle.
Silicon Signature
A row of fixed ROM is present in the EIM48F010 which
contains the device's Silicon Signature. Silicon Signature
contains data which identifies SEEQ as the manufacturer
and gives the product code. This allows device programmers to match the programming specification against the
product which is to be programmed.
Data (Hex)
Silicon Signature is read by raising address Ag to 12
94
± 0.5 V and bringing all other address inputs plus chip
enable and output enable to V,L with Vee at 5 V. The two
1C
Silicon Signature bytes are selected by address input Ao'
Mode Selection Table
Mode
CE
OE
WE
Vpp
Read
VIL
VIH
VIL
VIL
VIL
VIL
VIL
VIH
X
Standby
Byte Write
Chip Erase Select
Chip Erase
Block Erase
A
_
1o 16
Address
A O • II
Address
Do .7
X
X
X
X
X
DOUT
High Z
VIH
VIH
VIH
VIH
VIL
VIL
VIL
Vp
Address
Address
DIN
TTL
X
X
X
Vp
X
X
'FF'
VIL
Vp
Address
X
'FF'
Absolute Maximum Stress Range*
Temperature
Storage ..................................... -65°C to +150°C
Under Bias ................................ -65°C to + 135°C
E.S.D. Charateristics[1]
Symbol
Parameter
VZAP
E.S.D. Tolerance >2000
Value
Test Condition
V MIL·STD883
Method 3015
All Inputs except Vpp and
outputs with Respect to Vss ........ +7 V to -0.5 V
Note: Characterization data -
Vpp pin with respect to Vss .......................... 14 V
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
seeQ
MD4000691A
Technology, Incorporated
6-175
not tested.
EIM48F010
PRELIMINARY DATA SHEET
Recommended Operating Conditions
E48F010
M48F010
Vee Supply Voltage
5V ± 10%
5V ± 10%
Temperature Range
(Read mode)
-40°C to +85°C
-55°C to +125°C
Temperature Range
(Write/Erase mode)
-40°C to +85°C
-55°C to +85°C
Capacitance f2]
TA = 25°C. f =1 MHz
Symbol
Parameter
CIN
Input Capacitance
Value
6 pF
COUT
Output Capacitance
12 pF
Test Condition
VIN = 0 V
VItO
=0V
Note 2: This parameter is only sampled and not 100% tested.
DC Operating Characteristics
Over the Vcc and temperature range
Limits
Symbol
Parameter
Max.
Unit
Test Condition
III
Input Leakage
1
VIN = 0.1V to Vee
ILO
Output Leakage
10
IlA
IlA
Vp
Program/Erase Voltage
11.4
13
V
V pR
V pp Voltage During Read
0
Vp
V
Ipp
Vp Current
Standby Mode
Read Mode
Byte Write
200
200
40
IlA
IlA
rnA
CE = VIH • Vpp = V pR
CE = V IL• Vpp = VpR
Vpp = Vp
Chip Erase
Sector Erase
80
15
rnA
rnA
Vpp
Vpp
Min.
VIN = 0.1V to Vcc
= Vp
= Vp
Iccl
Standby Vcc Current
400
JlA
CE = Vcc -0.3V
Icc2
Standby Vcc Current
5
rnA
CE
Icc3
V IL
Active Vee Current
60
rnA
CE
Input Low Voltage
-0.3
0.8
V
V IH
Input High Voltage
2.0
7.0
V
VOL
V OHl
Output Low Voltage
0.45
V
IOL
2.4
V
IOH
V OH2
Output Level (CMOS)
Vcc -1.0
V
IOH = -100 IJA
seeQ
MD4000691A
Output Level (TTL)
Technology, Incorporated
6-176
= VIHmin.
= V IL
= 2.1 rna
= -400 IJA
EIM48F010
PRELIMINARY DATA SHEET
READ
AC Characteristics
(Over the Vcc and temperature range)
E48F010
ElM48F010
-200
-250
Symbol
Parameter
Min.
t RC
Read Cycle Time
200
tAA
Address to Data
tCE
CE to Data
tOE
OE to Data
tOF
OE/CE to Data Float
tOH
Output Hold Time
Max.
Min.
Max.
250
200
200
75
50
0
ElM48F010
-300
Min.
Unit
ns
300
300
150
100
250
250
100
60
0
Max.
300
ns
ns
ns
ns
0
ns
Read Timing
AOO_S~~~:~~=~==~=~~=~,=,=_t~~~~~~~~~~~~XXXXZ
VOO-7
'-------I--------~--l--tDF--~
xxxxx
A.C. Test Conditions
Output Load: 1 TTL gate and C(load) = 100 pF
Input Rise and Fall Times: < 20 ns
Input Pulse Levels: 0.45V to 2.4 V
Timing Measurement Reference Level:
Inputs 1V and 2V
Outputs O.BV and 2V
seeG
MD4000691A
Technology, Incorporated
6-177
EIM48F010
PRELIMINARY DATA SHEET
Byte Write
AC Characteristics
(Over the Vcc and temperature range)
ElM48F010
Symbol
Parameter
Min.
tyPS
Vpp Setup TIme
2
150
0
0
10
10
20
100
50
10
100
75
tYPH
Vpp Hold TIme
tcs
CE Setup TIme
tCH
CE Hold TIme
tOEs
OE Setup TIme
tOEH
OE Hold TIme
tAS
Address Setup TIme
tAH
Address Hold TIme
tos
Data Setup TIme
tOH
Data Hold TIme
twp
WE Pulse Width
twc
Write Cycle TIme
tWR
Write Recovery TIme
Max.
Unit
Ils
Ils
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
Il s
ms
NOTE: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the
user must provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device,
e.g. access time, erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.
Advance Data Sheets contain target product specifications which are subject to change upon device characterization over the full
specified temperature range. These specifications may be changed at any time, without notice.
Byte Write Timing
Ypp
ADDRESS
1-o----tWR----I
seeQ
MD4000691A
Technology, Incorporated
6-178
EIM48F010
PRELIMINARY DATA SHEET
Figure 1
EIM48F010 Write Algorithm
SET Vpp = Vp
WAITtvps !IS
LOOP _ COUNT = 0
SET ADDRESS
1ST LOCATION
RE-WRITE
BYTE (4X)
FOR twcl.lS
SET ADDRESS
1ST LOCATION
RE-WRITE BYTE
F
twc!lS
WAIT tWRms
WRITE BYTE
FOR twc!lS
INC. ADDRESS
INCREMENT
ADDRESS
INCREMENT
LOOP _COUNT
YES
NO
INCREMENT
LOOP_COUNT
WAITtwRms
LOOP_COUNT
seeQ
MD4000691A
=0
NO
YES
Technology, Incorporated
6-179
EIM48F010
PRELIMINARY DATA SHEET
Sector Erase
AC Characteristics
(Over the Vee and temperature range)
E/M48F010
Min.
Max.
Symbol
Parameter
t vps
Vpp Setup Time
2
Unit
t VPH
Vpp Hold Time
500
Ils
ms
tcs
CE Setup Time
0
ns
tOES
t AS
OE Setup Time
0
ns
Address Setup Time
20
ns
tAH
Address Hold Time
100
ns
tos
Data Setup Time
50
ns
tOH
Data Hold Time
10
ns
twp
WE Pulse Width
100
ns
tCH
CE Hold Time
tOEH
0
0
ns
OE Hold Time
tERASE
Sector Erase Time
500
ms
tABORT
Sector Erase Delay
250
tER
Erase Recovery Time
250
ns
Il s
ms
Sector Erase Timing
Vpp
R~\7~~--H-----~J~?v~~~~70~~~,r-------~~~~~~~~~~jo~~~~7\J
ADDRESSES
..DJ.~(~--1H-----....f '.f.j,£.lLl.~\£ll.lLl.UL.l.UD.L.l.O~ '----------f-I \£l.D.Ll.UD.LlqPC\.Q./~~~lJL~~.D.L.ll.!
NEXTLOOP
, .. LOOP
seeQ
MD4000691A
Technology, Incorporated
6-180
EIM48F010
PRELIMINARY DATA SHEET
Figure 2
ElM48F010 Sector Erase Algorithm
WAITtER ms
THEN VERIFY
ALL BYTES - FF
SETVpp .Vp
WAITtvps 1'.5
WRITE FF
TO SECTOR
ADDRESS
NO
L = 24
seeQ
MD4000691A
Technology, Incorporated
6-181
EIM48F010
PRELIMINARY DATA SHEET
Chip Erase
AC Characteristics
(Over the Vcc and temperature range)
E/M48F010
Max.
Symbol
Parameter
t vps
Vpp Setup Time
2
~s
t VPH
Vpp Hold Time
500
ms
tcs
CE Setup Time
OE Setup Time
0
0
ns
tOES
tos
Data Setup Time
ns
tOH
Data Hold Time
twp
WE Pulse Width
50
10
100
tCH
CE Hold Time
0
ns
tOEH
OE Hold Time
0
ns
tERASE
Chip Erase Time
500
ms
tER
Erase Recovery Time
Min.
seeQ
MD4000691A
ns
ns
ns
250
Chip Erase Timing
Technology, Incorporated
6-182
Unit
ms
EIM48F010
PRELIMINARY DATA SHEET
Figure 3
EIM48F010 Chip Erase Algorithm
SET Vpp. Vp
WAITtvps ILs
WRITE FF
TO ANY
ADDRESS
NO
L = 24
seeQ
MD4000691A
Technology, Incorporated
6-183
EIM48F010
PRELIMINARY DATA SHEET
Ordering Information
M
D
T
T
48F010
K
~
T
Endurance
Package
Type
Temperature
Range
Device
D - Ceramic Dip
E - -40 to +85°C
128K x 8 FLASH
EEPROM
L=Ceramic
Leadless Chip
Carrier
M .. -55 to + 125°C
(Read)
-55 to+85°C
(Write/Erase)
BLANK .. 100
K .. 1000
Access
Time
200 = 200 ns
(-40 to +85°C
Temp Range Only)
300 = 300 ns
N '" Plastic Leaded
Chip Carrier
(-40 to +85°C
Temp Range
Only)
MD4000691A
T
250 .. 250 ns
F = Flatpack
seeQ
-250
Technology, Incorporated
6-184
/B
T
Screening
MIL 883 Class
B Screened
(Optional)
seeQ
EEPLD
M20RA10Z
November 1989
PRELIMINARY DATA SHEET
Features
•
CMOS EEPLD with Zero Standby Power:
• 10llA Typical, 150 pA Maximum
•
Quickly and Easily Reprogrammable In All
Package Types
•
Operating Power Rises at Less Than
SmA/MHz
•
100 Reprogramming Cycles, Minimum
•
Silicon Signature Bit for Design Secrecy
•
Propagation Delay: 45 ns
•
100 % Field Programming Yield
•
Asynchronous Architecture:
• 10 Output Macro Cells with Individually
Programmable Clocks, Preset and Reset
Signals
•
10 Years Data Retention Guaranteed
•
Supported By: ABELTIl, CUPL 711, PALASM2,
PLDeslgnerTII
Individually Programmable and Global Output
Enable
•
Programmed on Standard PAL Device
Programmers
•
Programmable Output Polarity
•
•
Registers Can Be Bypassed Individually
Space Saving 0.3" Wide 24-Pln
Ceramic DIP
•
Preloadable Output Registers Facilitate
Testing
•
•
28-PlnLCC
Military Temperature Range
• -55°C to + 125°C Operation
•
Block Diagram
INPUTI
OUTPUT
INPUTI
OUTPUT
INPUTI
OUTPUT
INPUTI
OUTPUT
ABEL is a trademark of DATA I/O Corporation
PLDesigner is a trademark of Minc Inc.
CUPL is a trademark of Logical Devices Inc.
seeG
MD 400086/-
Technology, Incorporated
6-185
INPUTI
OUTPUT
INPUTI
OUTPUT
INPUTI
OUTPUT
INPUTI
OUTPUT
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
General Description
FuncUonalDescnpUon
The 20RA 1OZ is functionally equivalent to the bipolar
PAL20RA10. SEEO's 20RA10Z consumes significantly
less power than its bipolar equivalent: Standby power
consumption is typically less than 10 pA; active power
rises at less than 5 mA per MHz of operating frequency.
The 20RA 10Z has ten dedicated input lines and 10 programmable 110 macrocells. The Registered Asychronous
(RA) macrocell is shown on page 3. Pin 1 of the EEPLD
serves as global register perload, pin 13 (DIP) or pin 16
(LCC) serves as global output enable. The exclusive-OR
in every macro cell allows choosing between active high
and active low output polarity, and ensures highest possibility utilization of the AND-OR array.
Bipolar devices can not be reprogrammed while UV erasable PLDs can be reprogrammed only in windowed, ceramic packages. Electrically erasable device offer reprogrammability without constraints in all package types.
Reprogrammability reduces development costs and eliminates the risks involved in preprogramming production
quantities. Systems can be updated quickly by reconfiguring the EEPLDs. Reprogrammability helps SEEO to
extensively test the entire device and offer 100% field programming yield.
The asynchronous 20RA 1OZ adds a new dimension to
PAL device flexibility. Its unique architecture allows the
designer to individually clock, set or reset each of the 10
output macro cells, and to enableldisable each output
buffer individually.
Third party software packages allow users to enter PLD
designs on personal computers or engineering workstations. Common input formats are: Boolean Algebra,
Truth- Tables, State Diagrams, Wave Forms or schematics. The software automatically converts such specifications into fuse patterns. These files, once downloaded to
PAL programmers, configure PLDs according to the user's
specifications.
Programmable Preset and Reset
In each macrocell, two product lines are dedicated to
asynchronous preset and asynchronous reset. If the
preset product term is HIGH, the 0 output of the register
Pin Configuration
(Top View)
.:-
20RA10Z
20RA10Z
LCC PINOUT(1)
SLIM DIP PINOUT
_0
I~ ~
>8 '50'"
gtt:l
Pin Designations: I = Input
VO = Input/Output
j5[ = Preload
OE = Output Enable
Vee = Supply Voltage
GND=Ground
NC = No Connection
Note:
1. Surface mount packages pinout conform
seeQ
MD 400086/-
to JEDEC standard.
Technology, Incorporated
6-186
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
RA Macrocell Configuration
INPUT TERMS
J
PL
PRODUCT TERMS:
~T ENABL~ISA;:-E
OE
-
CLOCK
ASYNCR. RESd
1/0
INPUT
PRELOAD
becomes logic 1. If the reset product term is HIGH, the Q
output of the register becomes a logic O. The operation of
the programmable preset and reset overrides the clock.
Programmable Clock
The clock input to each flip-flop comes from the programmable array, Allowing any flip-flop to be clocked independently if desired.
Bypass Mode/Registered Mode
If both the preset and reset product terms are HIGH, the
flip-flop is bypassed (Bypass Mode) and the output becomes combinatorial. Otherwise, the output is from the
register (Registered Mode). Each output can be configured to be combinatorial or registered.
Programmable Polarity
The outputs can be programmed either active-LOW or
active-HIGH. This is represented by the Exclusive-OR
gate shown in the 20RA 1OZ logic diagram. When the
output polarity bit is programmed, the lower input to the
Exclusive-OR gate is HIGH, so the output is active-HIGH.
Similarly when the output polarity bit is unprogrammed, the
output is active-LOW. The programmable output polarity
feature allows the user a higher degree of flexibility when
writing equations.
seeQ
MD 4000861-
OUTPUT ENABLE
The device provides a product term dedicated to local
output control. There is a global output control pin. The
output is enabled if both the global output on is LOWand
the local output control product is HIGH, all outputs will be
disabled. If the local output control product term is LOW,
then that output will be disabled.
Remark: The output buffer inverts the sum of products signal.
Register Preload
Register preload allows any arbitrary state to be loaded
into the PAL device output registers. This allows complete
logic verification, including states that are impossible or
impractical to reach otherwise. To use the preload feature,
first disable the outputs by bringing OE HIGH, and present
the data at the output pins. A LOW level on the preload pin
(PL) will then load the data into registers. (See Register
Preload Waveform on the bottom of page 193.)
OE Product Term
OEPin
1/0
I
0
Indiv. output enabled
0
X
Indiv. output disabled"
X
I
All outputs disabled"
• Output pin(s) floating or used as input(s)
Note: Roating outputs, as well as unused or floating inputs
should be pulled HIGH or Low. Otherwise noise , amplified
through the feedback paths or input buffers, may constantly
trigger the edge defection circuitry within the 20RA 1OZ and inhibit
standby mode.
Technology, Incorporated
6-187
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
Security Bit
A security bit prevents copying ofyour proprietary design.
When this bit is set, the verify data path in the PLD is
disabled, making it impossible to copy your pattern. Since
EEPLDs store patterns as electrical charges on floating
polysilicon gates (and not in blown fuses, like other PLD
technologies) it is not possible to determine the pattern by
simply examining the die. A copy protected EEPLD can be
reused after a block erase, which clears both the previously programmed pattern and the security bit at the same
time.
Output Macrocell Configurations
REGISTER OUTPUT/ACTIVE HIGH
REGISTERED OUTPUT/ACTIVE LOW
ASYNCHRONOUS PRESET
PRODUCT TERM
SUM OF
PRODUCTS
110
SUM
vo
SU~~
CLOCK
AR
AR
ASYNCHRONOUS RESET
PRODUCT TERM:
COMBINATIONAL OUTPUT/ACTIVE LOW
(REGISTER BYPASS MODE)
COMBINATORIAL OUTPUT/ACTIVE HIGH
(REGISTER BYPASS MODE)
Output Buffer with Individually Programmable
and Global Output Enable
OUTPUT ENABLE
PRODUCT TERM
1 = OUTPUT ENABLED
o = OUTPUT DISABLED
110
GLOBAL
OUTPUT
ENABLE
seeQ
MD400086/-
OE
-------1
._---"-=---{)IC ....
OUTPUT ENABLE
Techno/ogy.lncorporatsd
6-188
OE
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
EEPLD 20RA 10Z Logic Diagram
PL 1 (2)
....
....
0
I
~9t
7
10 2 (3)
~
~i11... ,
,
8
~9t ~
ARP
15
11 3 (4)
16
~9t ~
I
~ARP~II
23
12 4 (5)
.A
,
24
~9t
31
13 5 (6) -t.A
e
PLAR~I I
.!.o
I
,-
...... I
''"''''T
22 (26) 110 8
........ 1
21 (25) 1107
"'J
f-----,
......
~
ARP
~9t ~
39
14 6 (7)
40
I
~9t
47
15 7 (9) -I.A
2
.......... I
'"""I
20 (24) 1106
e
PLAR~II
.2
........ T
19 (23) 1105
~J
f----=-1
......
2,
........ 1
18 (21) 1104
...
f-----,
48
~9t ~
I
55
16 8 (10)
9_......... 1
17 (20) 1103
""J
r-----t
56
~9t ~
I
~I
63
17 9 (11) -I.A
,
64
~qt
71
1810 (12) -I.A
72
79
~
1911 (13)
..-001
PLAR;II
6-189
2_........ 1
....
.......
,
......... 1
~~ ~
.oR"
PIN NUMBERS REFER TO DIP PINOUT (PLCC PINOUT)
Technology, Incorporated
~
~ ~""'r
39
SeeQ
~
f-----,
32
MD 400086/-
23 (27) 110 9
~,
......... I
'"""f
....
'"""
16 (19) 1102
15 (18) 1101
14 (17) 110 0
13(16)OE
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
Absolute Maximum Ratings
Stresses above those listed under ABSOLUTE MAXIMUM RA TING may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods
may affect device reliability.
Supply voltage, Vee" ................................ -0.5 V to 7 V
DC input voltage, VI ...................... -0.5 V to Vee + 0.5V
DC output voltage Vo' ................. -0.5 V to Vee + 0.5 V
DC output source/sink
current per output pin, ' 0 , •••••••••••••••••••••••••••••••••• :t35 mA
DC Vee or ground current, Icc or 'GND • • ••••••• •••• :t 100 mA
Input diode current, Ille
V, <0 ............................................................. -20mA
V, > Vee ........................................................ +20 mA
Output diode current, laC
Vo < 0 ............................................................ -20mA
Vo> Vee' ...................................................... +20mA
Storage temperature ............................. -65°C to 150°C
Static discharge voltage ................................... > 2001 V
Latchup current ............................................... > 100 mA
Ambient temperature under bias ......... -55°C to + 125°C
DC Characteristics
Operating Ranges
Military (M) Devices
Temperature (Te)
Case ..................... '" ...................... -55°C to + 125°C
Supply voltage, Vee ........................... 4.5 V to 5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
(over operating conditions unless otherwise specified)
Min.
Max.
Unit
VIL
Low-level Input Voltage
Guaranteed Input Logical Low
Voltage for all Inputs(1)
0
0.8
V
VIH
High-level Input Voltage
Guaranteed Input Logical High
Voltage for all Inputsl1)
2
Vee
V
IlL
Low-level Input Current
Vee = Max.
IIH
High-level Input Current
Vee = Max.
VI = GND
VI = Vee
1
IlA
IlA
VOL
Low-level Output Voltage
Vee = Min.
IOL = 8 mA
0.5
V
Vee = 5V
IOL = 1 ~A
0.05
Vee = Min.
ICH = -4.0 mA
3.80
Vee = 5V
IOL = -1 ~A
Vo = GND(4)
(4)
Vo = Vee
4.95
Symbol
High-level Output Voltage
VOH
Off-state Output Current
10ZL
Test Conditions
Parameter
Vee = Max.
10ZH
lee
-1
-10
IlA
IlA
10
Standby Supply Current(2)
10 = 0 mA, VI = GND or Vee
150
IlA
Operating Supply Current(3)
f = 1 MHz, 10= 0 mA, VI = GND or Vee
25
mA
Notes: 1. These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or
tester noise. Do not attempt to test these values without suitable equipment.
2. Disabled output pins = Vee or GND.
3. Frequency of any input. See gragh page 194 for Icc versus frequency
4. I/O pin leakage is worst case of IL and 1021. (or IH and 10Hz),
Capacitance
Parameter
Symbol
CIN
COUT
Parameter Description
Test conditions
Input capacitance(1)
VIN = 2.0 V at f = 1.0 MHz
Vee = 5 V TA = 25°C
7
Output capacitance(1)
VOUT =2.0 V at f = 1.0 MHz
Vee = 5 V TA = 25°C
8
Note: 1. Sampled but not 100% tested.
seeG
MD 400086/-
Technology, Incorporated
6-190
Typ.
Unit
pF
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
Switching Characteristics
(over specified operating range)
-45
-40
Symbol
Parameter [1)
Min.
Max.
Min.
40
tpo
Input or Feedback to Output
ts
Setup Time for Input or Feednack to Clock
20
20
tH
Hold Time
15
15
teo
Clock to Output or Feedback(2)
twp
Preload Pulse Width
tsup
t HP
Max.
Unit
45
ns
ns
ns
45
40
ns
ns
30
30
Preload Setup Time
25
25
ns
Preload Hold Time
25
25
ns
tAP
Asynchronous Preset to Registered Output[2)
t APW
Asynchronous Preset Pulse Width
25
t APR
Asynchronous Peset Recovery Time
15
tAR
Asynchronous Reset to Registered Output(2)
tARW
Asynchronous Reset Pulse Width
25
30
ns
tARR
Asynchronous Reset Recovery Time
15
15
ns
tWL
Width of Clock LOW
20
20
ns
tWH
HIGH
20
20
ns
16.6
15.3
MHz
25
25
MHz
f MAX
Maximum
Extenal Feedback 1/(ts = teo)
Frequency
No Feedback 1I(~ = lwH)
45
45
30
15
45
ns
ns
ns
45
ns
tpzx
Common Enable to Output Buffer Enabled
25
30
ns
tpxz
25
30
ns
tEA
Common Enable to Output Buffer Disabled
Input to Output Buffer Enabledl31
40
45
ns
tER
Input to Output Buffer Disabled(3)
40
45
ns
Notes:
1.
2.
3.
4.
Test conditions are specified in table on page 194.
Minimum values of these parameters are guaranteed to be larger than the hold time ~.
Equivalent functions to t,.zx/tpxz but using product term control.
Preliminary specification.
Remarks: All specified input-to-output delays include the time it takes the input edge detection circuitry to activate the device (from
standby mode into operating mode).
Data Retention and Endurance
Symbol
Parameter
Value
Unit
Conditions
tOR
Pattern data retention time
>10
years
Max. storage temperature
Mil-STD 883 Test Method 1008
N
Min. reprogramming cycles
100
cycles
Operating conditions
seeQ
MD 400086/-
Technology, Incorporated
6-191
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
Switching Waveforms
~
VT
INPUT OR
FEEDBACK
______________~tPD-V-----COMBINATORIAL
OUTPUT
T
COMBINATORIAL OUTPUT (BYPASS MODE)
,,,
INPUT OR
FEEDBACK
~~
J~VT
-
J\
ts
CLOCK
_ tH--",
,
j~VT
t
REGISTERED
OUTPUT
______________~~co-V----T
REGISTERED OUTPUT (REGISTERED MODE)
OE
OUTPUT
IINPUT
OUTPUT
INPUT TO OUTPUT DISABLE/ENABLE
seeQ
MD 400086/-
Technology, Incorporated
6-192
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
Switching Waveforms (continued)
CLOCK WIDTH
ASYNCHRONOUS
PRESET - - - '
REGISTERED
OUTPUT
----~~~~~~~~----~--------
--JFT'APR
CLOCK _ _ _ _ _ _ _ _ _ _ _ _ _
ASYNCHRONOUS PRESET
ASYNCHRONOUS
RESET
REGISTERED
OUTPUT __
~~~~u.~~~
--JFT'ARR
CLOCK _ _ _ _ _ _ _ _ _ _ _ _ _
ASYNCHRONOUS RESET
L
OE
I/O
I~Wfl
------+--~
~--~------
PL
PRELOAD TIMING
seeQ
MD 400086/-
Technology, Incorporated
6-193
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
Switching Test Laod
~A1
OUTPUT!:
Specification
-€) TEST POINT
-<
:::::i' CL
CL
Measured
Output Value
R1
R2
tlL,teo
50 pF 440
190
1.5V
tpzx' ~
50 pF 440
190
Z-H: 2.0V
Z-L: O.SV
190
H - Z: V OH -0.5 V
L - Z: VOL + 0.5V
5pF
tpxz' tER
~
440
Icc Versus Frequency
TYPICAL: VCC
= 5V, T A =25°C
100
~::~ ~
2SV
. .
I
o
5
10
15
20
INPUT FREQUENCY (MHz)
Key to Timing Diagrams
WAVEFORM
//////!II
'---- SeeQ
MD 400086/-
INPUTS
OUTPUTS
DON'T CARE:
CHANGE PERMITTED
CHANGING:
STATE UNKNOWN
NOT APPLICABLE
CENTER LINE IS
HIGH IMPEDANCE STATE
MUST BE STEADY
WILL BE STEADY
MAY CHANGE FROM
HTOL
WILL BE CHANGING
FROM HTOL
MAY CHANGE FROM
L TOH
WILL BE CHANGING
FROM L TOH
Technology, Incorporated
6-194
Notes:
1.Vr =1.5V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times 2 - 5 ns typical
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
fMAX Parameters
The parameters fMAX is the maximum clock rate at which
the device is guaranteed to operate. Because flexibility
inherent in programmable logic devices offers a choice of
clocked flip-flop designs, fMAX is specified in this case for
two types of synchronous designs.
tion with an equivalent speed device. This fMAX is designated l'fMAX' External Feedback."
The second type of design is a simple data path application. In this case, input data is presented to the flip-flop and
clocked through; no feedback is employed. Under these
conditions, the period is limited by the sum of the data
setup time and the data hold time (ts + tJ. However, a
lower limit for the period of each fMAX type is the minimum
clock period (tWH + twJ. Usually, this minimum clock period
~etermines th; period for the second fMAx ' designated
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a multichip state machine. The slowest path defining the period
is the sum of the clock-to-output time and input setup time
for the external signals (ts + ted' The reciprocal, fMAX' is the
maximum frequency with external feedback or in conjunc-
f MAX.
r-----lOGIC
ClK
1
REGISTER
- - - -
...
....................~ (SECOND CHIP)
- - ~I"
ts
No feedbaCK •
~I
teo
f MAX, External Feedback; 1/(ts + teo)
r
- - - - lOGIC
I...
L
ts
ClK
--,
REGISTER
-I .. tH~
..J
f MAX, No Feedback; 1/(ts + t H) or 1/(tWH + twd
seeQ
MD 400086/-
Technology, Incorporated
6-195
..
ts~
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
PLD Development
PLD Programmer Vendors
Development software assists the user in implementing a
design in one or several PLDs. The software converts the
user's input into a device dependent fuse map in JEDEC
format. The software packages listed below support the
20RA 1OZ EEPLD. For more information about PLD de·
velopment software contact SEEO Technology or the soft·
ware vendor directly:
Adams MacDonald
800 Airport Road, Monterey, CA 93940
(408) 373·3607
DATA 110 Corp.
10525 Willows Road, NE, P.O. Box 97046,
Redmont, WA 98073·9746
(800) 247·5700
Software offered: ABEL, PLD Test
Minc.lncorporated
1575 York Road, Colorado Springs, C080918
(719) 590·1155
Software offered: PLDesigner
Log/cal Devices, Inc.
1021 N. W. 65th Place, Fort Lauderdale, FL 33309
(305) 974·0967
Software offered: CUPL
PLD Programming
The 20RA10Z can be programmed on standard logic
programmers. Previously programmed devices can be
reprogrammed easily, using exactly the same procedure
as required for blank EEPLDs. If the user wants to erase
a 20RA 10Z, but not program it to a new pattern, an empty
JEDEC file should be loaded into the device programmer.
DATA 110 Corp.
10525 Willows Road NE, P.O. Box 97046
Redmont, WA 98073·9746
(800) 247·5700
PLD Programming equipment:
System 29A or 29B
Logic Pak™ 303A·V04
Adaptor 303·011A for 24 pin DIP
303·011B for 28 pin PLCC
Family Pinout Code for 20RA 10Z: 9EI45
D/g/lee Inc.
22736 Vanowen, Canoga Park, CA 91307
(800) 367·8750; CA: (818) 887·3755
Logical Devices Inc.
1201 N. W. 65th Place, Fort Lauderdale, FL 33309
(305) 974·0967
PROMOC
see Adams MacDonald
Stag Microsystems Inc.
1600 Wyatt Dr., Santa Clara CA 95054
(408) 988·1118
For more information about PLD programmers contact
SEEO Technology or the programmer vendor directly.
Logic Pak is a trademark of DATA I/O Corporation.
seeG
MD 400086/-
Technology, Incorporated
6·196
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6-197
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6-200
EEPLD M20RA10Z
PRELIMINARY DATA SHEET
Ordering Information
o
M
20
RA
10
Z - 40 18
I
3
PACKAGE TYPE
D =CERAMIC DIP
L=LCC
PROCESSING
MILITARY
883 CLASS B
--SPEED
- 40 = 40 ns t PO
OPERATING RANGE - M = MILITARY
- 45
=45 ns
t PO
ZERO STANDBY POWER
NUMBERS OF ARRAY INPUTS
NUMBER OF OUTPUTS
OUTPUT TYPE
R = REGISTERED
A =ASYCHRONOUS
seeQ
MD 400086/-
Technology, Incorporated
6-201
6-202
RELIABILITY
(Reliability Report)
SEEQ EEPROM Reliability Report
Introduction and Product Description
Memory Cell Operation
SEEa offers a family of EEPROMs (Electrically Erasable
Read Only Memories) which range in size from 4K to 256K
bits in CMOS and NMOS technologies. They conform to
the JEDEC configurations for byte wide memories. One
family has internal input latches, a second family has
internal input latches as well as a timer and a third with
input latches, timer, and a page mode feature forfastwrite.
New developments in process technology, circuit design
techniques, and memory cell design combine to provide
high performance from these EEPROMs that require only
a single 5-volt power supply. SEEa uses an innovative aCell™ design on all its EEPROMs designed since 1983.
The a-Cell combined with oxynitride in the tunnel dielectric, substantially improves the write/erase endurance of
EEPROMs. This gives higher reliability to systems requiring infrequent write (Le., once a day for ten years) as well
as to systems Writing 5-10 times per day.
The SEEa EEPROM Memory Cell consists of aMOS
Floating Gate Memory Transistor and a Select Transistor.
See the Device Cross Section in Figure 1 and schematic
representation in Figure 2. The Memory Cell defines the
logic state, either "1" or a "0", by stori ng negative or positive
charge on the Floating Poly Silicon Gate (Poly 1 in Figure
1). When the reference voltage is applied to the top Poly
Silicon Gate (Poly 2 in Figure 1), the Memory Cell will or
will not conduct a current. This cell current is detected by
the sense amplifier and transmitted to the output buffer as
the appropriate Logic state.
Charge is transferred on and off the Floating Gate through
the thin Oxynitride Tunnel Dielectric by Fowler-Nordheim
Tunneling; (A auantum Mechanical transmission mechanism of an electron penetrating through the energy
bandgap for the thin oxide MOS structure). Fowler
Nordhiem Tunneling occurs when a high voltage, typically
17-20 Volts, is placed across the Tunnel Dielectric region
of the Memory Cell. This high voltage is generated internal
tothe device, the user need only to apply an external 5 Volt
level.
Programming the state of the memory cells (via the write
and erase modes) is accomplished by charging and discharging a floating gate device via Fowler-Nordheim tunneling. This tunneling occurs throlJgh a proprietary oxynitride dielectric under the floating gate (see Figure 1). The
use of oxynitride provides fast write/erase times at internal
voltages that are 25% lower than those required for conventional oxide-only approaches due to a lower barrier
height than thermal oxide. In addition, oxynitride provides
lower charge trapping characteristics which gives improved write/erase endurance of each cell. The use of
oxynitride in the dielectric area and SEEa's proprietary aCell design allows endurance to be specified up to
1,000,000 cycles/byte.
For a Logic "1 ", electrons are stored on the Floating Gate;
using the conditions defined For "erase" For a Logic "0",
holes are stored on the Floating Gate; using the conditions
defined for ''write''. The Memory Cells Thresholds for a
Logic "1" and "0" are shown in Figure 3.
Column
Row
Sense
Bit
Array Vss
Floating Gate
VT
I Cell
A1
VAPOX
FIELD
OXIDE
Erase
Read
17V
20V
0
17V
Floating
-Vp
<-5V
40llA
5V
20V
20V
0
0
+VE
>+2V
OIlA
5V
5V
0
2V
0
The select transistors are used to isolate the Memory
Transistor in order to prevent data disturb. Memory cells
and Peripheral Logic are combined to from the a-Cell,
which is a Memory Error Correction technique transparent
to the user.
Figure 1. EEPROM N-MOS
Through the use of the proprietary Oxynitride process for
the Tunnel Dielectric and use of the a-Cell, SEEa provides EEPROM's with typical data retention times of
Q-Cell is a trademark of SEEQ Technology, Inc.
seeQ
Program
Technology, Incorporated
MD500003/-
7-1
greater than 100 years, and Intrinsic Endurance Failure
Rates of less than .03%/1000 cycles. Devices with a
guaranteed Endurance of 1,000,000 cycles are possible.
The typical failure mechanisms are mobile ion contamination or trapped charges.
The "static" stress mode may be used either for screening
or determining the long term reliability of the product.
Static Life
"Static" refers to the D.C. bias of the cell periphery. Failure
modes for static life include threshold shifts and leakages.
Operating Life
The operating life of an EEPROM is limited by its general
reliability which includes integrity of the peripheral circuitry
as well as the memory cells. The operating life is characterized using a dynamic high temperature life stress.
SENSE AMP
COLUMN(Y)
SELECT LINE
Dynamic high temperature life stress is a standard approach used to evaluate the failure rate distribution of a
product under accelerated conditions. The failure rate is
statistically derived from the experimental results obtained
at elevated temperatures, then extrapolated to typical
operating temperature conditions. This extrapolated is
accomplished using the Arrhenius relationship and an
apparent activation energy consistent with the failure
mechanisms observed. This acceleration technique
works well for common causes of failure such as oxide
defects, interconnect voids, and defective bonding.
BIT LINE
ROW (X)
SELECT LINE
SENSE
(SELECT) LINE
ARRAYVSS
Memory Transistor
Row Select Transistor
Column Select Transistor
Byte Select Transistor
Sense Select Transistor
FLOATING GATE 85 ANGSTROMS OXY-NITRIDE
Q,
Q2
Q3
Q4
Qs
=
=
=
=
=
For ease of calculation, the instantaneous failure rate is
assumed to be constant throughout the lifetime of the
product (Le., the probability density function of the time to
failure is assumed to be exponential).
Units to be stressed were drawn from finished goods
inventory and written with a data pattern selected to
program both logic states of "1" and "0" into locations in
each row and each column of the array. Initial, intermediate, and final electrical testing of units was conducted at
room temperature using a test program that checks parametrics, functionality and timing parameters.
Figure 2. Generic EEPROM Memory Cell
--- -----
LOGIC 1 MARGIN
w
51!
~>
SENSE AMPLIFIER
REFERENCE VOLTAGE
o
o
-r
ADDrrlONAL
OXYN ITR IDE
MARGIN
:I:
I/)
The dynamic high temperature stress was applied in
accordance with the conditions prescribed in MIL-STD883, Method 1015, Condition D. Oven ambient temperature was maintained at 125 degrees C. The schematics
are available upon request.
W
a:
LOGIC 0 MARGIN
;:r:
..
10
- __ 1li~,!Ak~~~ ___ OXYNrrRIDE
------\
------
10
10'
The results are summarized in Table 2. The predictions
use an assumed activation energy of Ea = 0.4 ev for Ta =
NUMBER OF WRrrElERASE CYCLES
Figure 3. EEPROM Cell Margin Characteristics
Table 1.
Predicted Failure Rate
@90%
Confidence @ Ta = 55°C
(Ea = 0.6 eV)
Product
Total
Devices
Stressed
Total Device
Stress Hours
@Ta= 125°C
Number of
Failures
52813
324
324,000 hrs.
0
0.019%/1000 hrs.
2816
87
309,000 hrs.
0
0,020%/1000 hrs.
seeG
MD500003/-
Static Life Stress Results
Technology, Incorporated
7-2
from the production flow as well as predicting expected
retention lifetimes of outgoing product.
55 degrees C. The predicted charge gain failure rate is
less than one-half the intrinsic failure rate of NMOS, as
would be expected. This implies the field usage failure rate
would be accurately predicted by dynamic life test.
In order to determine the data retention capability of
SEEQ's products, unbiased devices are subjected to high
temperature bake at 250 degrees C. The failure mode is
a change in state of the memory cell, and the typical failure
mechanism is a dielectric defect resulting in "charge loss".
Because dielectric defects can be induced by the electric
fields generated during write/erase cycles, data retention
and endurance are related topics. The effects of cycling on
data retention are covered in the endurance section. In
this section, the intrinsic data retention characteristics are
evaluated and compared againstthe minimum data retention goal of ten years.
Data Retention Bake
Intrinsic data retention is defined as the ability to retain
valid data over a prolonged period of time under storage
conditions. At the cell level, data retention is a measure of
the ability of the floating gate to retain charge in the
absence of applied external gate bias. Data retention
failures in a floating gate structure are commonly caused
by dielectric defects and can be accelerated by high
temperature bake stress. This characteristic provides a
technique for both screening potentially defective product
Units to be stressed are drawn from finished goods inventory and erased to an all 1's pattern (e.g., negative charge
on floating gate). After erasing and initial testing, parts
were temperature stressed at 250 degrees C. Voltage
stress is not required for this evaluation; therefore, all
leads are held at ground potential.
_K
The results are summarized in Table 3. Using an activation energy of 0.6 ev, the data retention lifetime predicted
by the data exceed 100 years at a 55 degrees C temperature. This period exceeds the industry 10 year standard for
erasable memories.
r'~ o, ~
__
Endurance
- - OXYNITRIDE
10"'------1._ _- ' -_ _..1.--_--.1._ _- ' - _ - - - '
14
10
11
12
13
15
16
Endurance is defined as the ability of an EEPROM to
operate to data sheet specifications after repeated write/
erase cycles to each byte. SEEQ specifies an endurance
option of either 10,000 or 1,000,000 cycles/bytes. The
extraordinary high endurance is accomplished using
STRESS FIELD (MVICM)
Figure 4. Comparison of Positive Charge Trapping at
Tunneling-Dielectrlc/Si Interface.
Table 2.
High Temperature Dynamic Life Stress Resuts
Product
Total
Devices
Stressed
Total Device
Stress Hours
Stress
Temperature
Number of
Failures
Predicted Failure Rate @
90% Confidence @ 55°C
(Ea 0.4 eV)
0.034%/1000 hrs.
=
=
52913
1089
1,009,000
125°C
1
2816/2817
1307
1,782,000
125°C
3
0.0330/011000 hrs.
36C16
80
14,720
150°C
0
0.7118°/011000 hrs.
52933
1086
1,142,000
125°C
2
0.0112°/011 000 hrs.
2864
370
467,000
125°C
1
0.0411 °/011000 hrs.
2864
77
38,500
150°C
1
0.459°/011000 hrs.
28C64
237
157,000
125°C
1
0.145°/011 000 hrs.
28C64
157
53,536
150°C
0
0.196°/011000 hrs.
28C256
350
230,302
125°C
3
0.258°/011000 hrs.
28C256
77
38,500
150°C
1
0.459°/011000 hrs.
seeQ
Technology, Incorporated
M0500003/-
7-3
SEEQ's proprietary oxynitride process and its innovative
Q-Cell design.
Products which are specified with
1,000,000 cycle endurance designated with "55" series
part numbers.
As seen from endurance plot of Figure 3, the threshold
window achieved using the SEEQ oxynitride dielectric
represents an improvement over the traditional silicon
dioxide case by at least a factor of ten. The oxynitride
window demonstrates very little closing at 106 cycles, and
provides a very useable window at 107 cycles.
Endurance failures are characteristically caused by dielectric breakdown occurring in the tunnel dielectric itself.
This breakdown is associated with charge trapping that
occurs during repeated write/erase cycles. 8ecause this
behavior is central to the device physics of an EEPROM
memory cell, endurance will be discussed in two parts,
first, at the cell level, then, at the product level.
The improved performance of oxynitride over oxide is
directly related to the superior trapping characteristics of
the oxynitride film, as shown in Figure 4 and 5. In Figure
4, the positive charge trapping characteristics of oxynitride
and oxide are compared as a function of field strength
(principal independent variable). The positive charge trap
density is consistently lower for oxynitride by approximately a factor of four. In Figure 5, the negative charge
trapping characteristics of oxynitride and oxide are compared as a function of total injected charge (the principal
independent variable in this case). Note the benefit of
oxynitride in this case continues to increase with increasingcharge, thus verifying the endurance improvement first
observed in Figure 3.
During each write/erase operation of a floating-gate
EEPROM cell, a miniscule amount of charge is trapped in
the dielectric through which the programming charge
tunnels (Ref. 1) The cumulative effect of this charge trapping has a strong impact on the effective threshold voltage
that the cell exhibits at each write/erase cycle. The
envelope of the "written" threshold voltage and the
"erased" threshold voltage plotted over a number of cycles
is referred to as the cell threshold ''window'' and is a key
figure of merit for any EEPROM cell. Referring to the
representative threshold window shown in figure 3 the net
effect of charge trapping results in an initial widening of the
window (due to positive trapped charge). Ultimately,
negative charged trapping sets the upper limit on endurance when the window becomes too narrow to be useful.
Units were pulled from finished goods inventory and
stressed by performing repeated write/erase cycles on
every byte in the memory. Data retention, read/write
functionality, AC performance, and parametrics were
periodically tested against data sheets specs. Failures
(typically caused by the selective failure of random bits)
were analyzed and complied for failure rate calculations.
A summary of the results is shown in Table 4. It shows that
all of SEEQ's EEPROM meet or exceed the intrinsic MOS
failure rate of 0.05%/1 000 hours if you write once per day.
It should also be noted that the Q-Cell EEPROMs have
higher endurance than the non Q-Cell 52813. All of
SEEQ's EEPROMs are Q-Cell except for the 52813. For
applications where writing occurs more frequently or
where a failure rate of less than 0.03%/1000 hours is
required, then a 1,000,000 cycle part such as the 16K
5516A should be considered.
Reference
M«lUNTOF INJECTED CHARGES (ClCI")
(1) Ching S. Jeng et ai, IEDM Technology Digest 1982,
p.811.
Figure 5. Comparison of Negative Charge Trapping
Table 3.
MDS00003/-
Predicted Failure Rate
@90%
Confidence @ Ta = 55 DC
(Ea = 0.6 eV)
Total
Devices
Stressed
Total Device
Stress Hours
@Ta=250D C
Number of
Failures
52813
82
118,000
2
0.0023%/1000 hrs.
2816
133
133,000
0
0.000873%/1000 hrs.
52833
100
50,000
0
0.0014%11 000 hrs.
28C256
15
2,520
0
0.0461%/1000 hrs.
Product
~seeQ
High Temperature Bake Test Results
Technology, Incorporated
7-4
Table 4.
Product
Total
Devices
Stressed
Write/Erase Endurance Test Results
Total Device
Stress Cycles
Number of
Failures
Predicted Failure Rate
@ 90% Confidence
(Ea ~ 0.125 ~V)
Failure Rate
with One Write
Cycle per Day
52813
189
4,400,000
5
0.305%/1 000 cycles
0.013%11 000 hrs.
2816/2817
8,917
3,355,820,000
190
0.009%/1000 cycles
0.0004%11 000 hrs.
0.00008%/1000 hrs.
5516
7,481
7,798,000,000
88
0.0018%/1000 cycles
52833
4,013
1,787,810,000
68
0.006%1000 cycles
0.0003%/1000 hrs.
2864
434
35,100,000
6
0.043%/1000 cycles
0.0018%/1000 hrs.
28C64
240
2,400,000
5
0.555%/1 000 cycles
0.023%/1000 hrs.
28C256
450
45,000,000
11
0.0529%11 000 cycles
0.002%/1000 hrs.
Accelerated stress Is updated quarterly and Is available from SEEa Technology.
seeQ
M0500003/-
Technology, Incorporated
7-5
7-6
seeQ
Radiation and MOS
I. Introduction
The effect of radiation on non-volatile memories is of
concern when the devices may be exposed to radiation
and are expected to continue functioning, (such environments include, battlefields, near and deep space). SEEQ
EEPROM's have demonstrated better performance than
other MOS non-volatile reprogrammable memories and
can be successfully used in the above listed environments,
as well as other applications requiring functionality during
and after radiation exposure. SEEQ EEPROM's have
proven particularly resistant to charged particles.
2. Loss of stored charge on the Floating Gate resulting in
a repeatable data error during read. Devices may be reprogrammed and then will still retain charge and read
correctly.
IV. MODELS
A. Total dose Ionizing radiation: Simulated by exposure
to gamma rays, usually from a Co 60 source. Expect MOS
devices to withstand 103 to 106 RAD (Si) of total dose
before permanent damage. Concerns are with loss of
stored charge on the Floating Gate and loss offunctionality
or parametric drift due to changes in the MOS Transistor
preformance charateristics.
Variables include:
II. Concerns
A. Permanent damage can be a function of:
1. Total dosage of ionizing radiation
2. Neutron flux
3. Gamma dose rate
4. Charged particles
1. Thinner oxides are less likely to trap charge or generate
electron/hole pairs.
2. Bias applied during irradiation aggravates charge trapping.
B. Transient errors (temporary upset) can be a
function of:
1. Charged particles, e.g. Cosmic rays
2. Gamma dose rate
3. Dose rate of the source, i.e. lower dose rates result
in high cummulative levels before failure, or annealing i.e.
waiting after irradiation until the device anneals and regains some level of performance.
III. Failure Mechanisms
A. Permanent Damage:
1. Build up of trapped charge in dielectrics, primarily gate
oxides; caused by charge generated by the radiation flux
congregating at defects in the oxide. This results in
threshold shifts and subsequent non-functionality or parametric drift.
B. Dose rate: Simulated by exposure to gamma rays
usually generated by a linear accelerator or Flash X-ray
machine. Expect MOS devices to withstand 107 to 108
RAD (Si)/sec before transient errors and 10'0 to 10" RAD
(Si) before permanent damage. EPI substrates will reduce
susceptability to Latch-up or Lock-up.
2. Build up of interface states caused by charge generated
by the radiation flux accumulating at layer boundaries.
This results in degradation in transconductance or
threshold shifts and subsequent non-functionality or parametric drift.
C. Neutron flux: Simulated by exposure to neutrons, usually generated by a nuclear reactor. Expect MOS devices
to withstand greater than 10'4 neutronslcm2• Normally
MOS devices are not tested for neutrons.
3. Formation of interstitials and vacancies in the crystal
lattice structure caused by neutron flux. This results in
changes in the electrical characteristics of the bulk silicon
and subsequent non-functionality.
D. Cosmic rays (SEU-Single Event Upset): Simulated
byexposureto high energy, heavyions, usually generated
by a particle accelerator. Baseline standards are not well
established for MOS devices. Concerns are with data loss
or Latch-up as hard failures; or temporary data upset
during read or write.
4. Mechanical damage to silicon structures caused by
charged particles. This results in transistor performance
degradation and subsequent non-functionality.
V. DATA FOR SEEQ MOS DEVICES (ATTACHED)
A. Total dose is better than average for non-hardened
MOS devices. Failures in read mode are due to charge
loss; failures in write mode are due to charge trapping in
the memory transistors. Although minor parameter drift
has been observed, loss of functionality occurs first in the
memory transistor.
B. Transient Errors:
1. Generation of false electrical signals from photocurrents in semi-conductor junctions caused by high energy particles or gamma rays. These result in a temporary
data upset during a read cycle.
seeQ
MD5000041-
Technology, Incorporated
7-7
multiplying the absorbed dose (in RADS) by a "quality
factor" for the particular radiation.
B. Dose rate for both transient and permanent damage is
typical for MOS devices on bulk silicon. CMOS devices
built on EPI substrate have significantly improved dose
rate tolerance because of less suseptability to Latch-up,
e.g. > 1010•
E. Radioactivity - The spontaneous emission of radiation, e.g. particles and lor electro-magnetic waves (photons), from the nuclei of an unstable isotope, which eventually decays to a stable non-radioactive isotope.
C. No data for neutron flux, butexpectto be similar to other
MOS devices, e.g. greater than 1014/cm2.
VII. REFERENCES
D. Data for single event upset (SEU) is using different ions
to simulate worse case cosmic rays. The devices appear
to perform better than expected; i.e. No upsets in SEEQ
EEPROMs, probably due to the bit error correction benefits of the Q-Cell. Potential latch-up concerns are reduced
by use of EPI substrates.
1. "Radiation Response of Floating Gate EEPROM NonVolatile Memory Cells" by E.S. Snyder, P.J. Mc Whorter;
T.A. Dellin; IEEE Trans. Nucl. Sci. Dec. 1989.
2. "Ionizing Radiation Effects in MOS Devices &Circuits";
T.P. Ma, Paul V. Dressendorfer; Wiley Interscience Publications; New York, 1989.
VI. DEFINITIONS
3. "The Effects of Radiation on Electronic Systems"; Messenger and Ash; Van Nostrand Reinhold Publishers, New
York, Copyright 1986.
A. Curle - A quantity of radioactive material undergoing
3.7 times 1010 disintegrations per second.
B. RAD - Radiation Absorbed Dose - The absorbtion of
100 ergs of radiation energy per gram of absorbing material.
4. "Non-Destructive Testing Handbook"; Second Edition;
Lawrence Bryant, Technical Editor; Paul Mcintire, Editor;
American Society of Non-Destructive Testing"; Copyright
1985.
C. Roentgen - The amount of gamma rays required to
produce ions carrying 1 electro-static unit of charge in 1
cubic centimeter of dry air.
5. "Principals and Techniques of Radiation Hardening";
Vol I-XII ; Norman J. Rudie; Western Periodicals Company;
Copyright 1986.
D. REM - Radiation Equivalent (in) Man - The measure of
the biological effect of radiation exposure is obtained by
Radiation Test Results
16K EEPROM
(5516/2816A
5517/2817A,52B13)
64K EEPROM
(52B33, 2864)
STRESS
CONDITIONS
FAILURE MODE
Unbiased total
dose
Alternating data
patterns, (e.g.
1st exposure all O's
next exposure all 1's
Co 60 gamma ray
source (10 RAD/sec)
Device will read
but some
locations fail
to write
- 9000 +/- 2000
RAD(Si)
-6500 +/- 500
RAD(Si)
Biased total dose
Alternating data
patterns, (e.g.
1st exposure all O's
next exposure all 1's
Co 60 gamma ray
source (10 RAD/sec)
Device will read
but some
locations fail
to write
-3000 +1- 1500
-3000 +1- 500
RAD(Si)
RAD(Si)
Biased dose rate
upset
Erased (1 's state),
Linear accelerator
gamma ray source
Upset during
read; not
permanent
3 +/- .75 X 107
RAD (Si)/sec
1.6 +1- .02 x 107
Biased dose rate
survival
Erased (1 's state),
Linear accelerator
gamma ray source
(200 RAD/20 ns Pulse)
Device will
read, all
locations fail
to write
>1010 RAD (Si)/sec
-10 10 RAD (Si)/sec
seeQ
MD5000041-
FAILURE RANGE
Read only
Technology, Incorporated
7-8
FAILURE RANGE
11000 +/- 2500
RAD(Si)
RAD (Si)/sec
Radiation Test Results
256K EEPROM
(28C256)
FAILURE RANGE
FAILURE MODE
STRESS
CONDITIONS
Biased
Dose Rate
Upset
Byte Checkerboard
Data Pattern; 54 ns
to 1 .5 us Pulse
widths; Linear
Accelerator
Single Bits
Change State
Byte Checkerboard
Data Pattern; 54 ns
to 1 .5 us Pulse
widths; Linear
Accelerator
Parts Fail to
Read, Recover
after Power Down
BULK 5 X 107 to 1 x 108
RAD (Si)/sec
No failures
EPI > 5 X 109 RAD (Si)/sec
Alternating data
patterns (e.g. 1st
exposure all O's
next exposure all 1's
Co 60 gamma ray
source (100-300
RAD/sec)
Device will read
but some locations
fail to write
BULK
~1
Read only
BULK
~20000
.01-.1 RAD/sec
Read only
BULK ~25000 - 30000 RAD (Si)
~ .06 RAD/sec
(Cesium source)
Read and Write
EPI -25000 - 30000 RAD (Si)
Biased Dose
Rate Lock-Up
Biased total
dose
BULK 1.1 X 109 TO 6.6 X 1010
RAD (Si)/sec
EPI > 5 X 109 RAD (Si)/sec
0000 +/- 1500 RAD (Si)
+/- 2000 RAD (Si)
16K EEPROM
(36C16)
STRESS
CONDITIONS
FAILURE RATE
Biased total
Dose
Alternating Data
Pattern (e.g. Checkerboard) Co 60 gamma
ray source (25-200
RAD/sec)
Single Bits Fail
to Write
~1 0000
+/- 2000 RAD (Si)
Read
~20000
+/- 2000 Rad (Si)
FALURE RANGE
128K FLASH EEPROM
(48F128)
STRESS
CONDITIONS
Biased total
Dose
Alternating Data
Pattern (e.g. checkerboard) Co 60 gamma
ray source (25-50
RAD/sec)
seeQ
FAILURE RATE
Single Bits Fail
to Read
Technology, Incorporated
MD5000041-
7-9
FALURE RANGE
~20000
+/- 2000 RAD (Si)
Radiation Test Results
256K EPROM
(27C256)
Memory programmed
to all O's, Exposed
to Co 60 source
(1-35 RAD/sec)
Biased total
dose
FALURE RANGE
FAILURE RATE
CONDITIONS
STRESS
Device fails
to read, multiple
bits read 1's
-15000 +1- 2000 RAD (Si)
EEPLD
(20RA10Z)
STRESS
FAILURE RATE
CONDITIONS
Programmed to
worst case functinal
pattern
Biased total
dose
FALURE RANGE
Loss of functionality
at rated speed
-10000 -15000 RAD (Si)
Single Event Upset
64K EEPROM (52833)
Samples were programmed and subjected to different levels of radiation to simulate a cosmic flux.
The devices are read after Irradiating for upsets.
RUN#
IONS
LET
FACILITY
1
2
3
4
5
Fe
Fe
Fe
Fe
Kr
Ar
Ne
8
BEVATRON
BEVATRON
BEVATRON
BEVATRON
CYCLOTRON
CYCLOTRON
CYCLOTRON
CYCLOTRON
CYCLOTRON
CYCLOTRON
0
6
7
N
P
CF-252
6
4
3.8
41
15.4
5.7
1.8
2.9
.004
42
ENERGY
RAD H2 O
TIME
UPSETS
144
144
288
288
30 SEC
30 SEC
2MIN
2MIN
NONE
NONE
NONE
NONE
200 MeV
160 MeV
88 MeV
217 MeV
68 MeV
148 MeV
105 MeV
-
NONE
NONE
NONE
256K EEPROM (28C256)
RUN#
IONS
LET
FACILITY
ENERGY
1
CF-252
42
-
105 MeV
seeQ
MD5000041-
Technology, Incorporated
7-10
RAD H2O
TIME
UPSETS
NONE
Memory Products
Reliability Note
Calculation of EEPROM
BoardMTBF
November1987
I
seeQ
7-11
Technology, Incorporated
Calculation of EEPROM Board MTBF
The increasing use of EEPROMs for large arrays of nonvolatile memory storage has raised interest in how to
calculate the MTBF (meantime between failures) ofthe resulting assembly. This paper will demonstrate how to
calculate the board MTBF as well as compare the results
of using different EEPROM technologies and failure rates.
Even though the microcircuitfailure rate is among the least
significant factors in board failures, the effects of other
components will be ignored for the purpose of simplicity.
Most failure mechanisms are thermally accelerated, so
with a lower operating temperature, the board MTBF will
be longer. CMOS EEPROMs consume less current, both
active and standby, than comparable NMOS EEPROMs.
Therefore, the power requirements for CMOS-populated
PCBs are less and the system will operate at a lower
temperature.
In order to calculate the board MTBF, the number of
EEPROMs, the read, endurance and data retention failure
rates, the reprogramming frequency, the rail temperature,
the appropriate thermal resistances and the device power
consumption must be known.
The MOS Floating Gate EEPROM has two reliability
characteristics which require consideration beyond that of
a normal MOS memory. Endurance, the number of times
an EEPROM may be erased and reprogrammed, is finite
because of the effects of the Fowler-Nordheim tunneling
current on the floating gate isolation dielectric(s). Data
retention, the length oftime the EEPROM will retain stored
data, is finite because of the impossibility of permanently
storing an electronic charge. The read or operating life
reliability will be similar to other MOS memories of like density.
The calculation of the board MTBF is best illustrated
through the use of an example. A comparison will be made
between NMOS and SEEQ CMOS 256K bit EEPROMs to
demonstrate the effects of power consumption, and the
intrinsically lower endurance failure rate of SEEQ
EEPROMs with Q-Cell on-chip error correction.
The following assumptions have been made:
SEEQ builds EEPROMs with Q-Cell on chip error correction in order to reduce the endurance failure rate. The
cumulative reprogramming cycles in the operational life of
the application must be less than the number of cycles
before the onset of endurance wear-out; therefore, the
average reprogramming frequency (cycles/hour) times
the expected operational life of the application should be
less than the typically specified 10,000 cycle endurance
limit. During the operational life, the failure rate should be
as low as possible in order to increase the system MTBF.
The read and data retention failure rates of SEEQ
EEPROMs appear similar to other vendors, although
these rates should theoretically improve as a larger statistical data base is acquired.
MiI-Hdbk-217 is frequently used to calculate failure rates
for microcircuits. Historically 217 has not made accurate
predictions regarding LSI or VLSI devices such as MOS
memories. This is exacerbated with EEPROMs that have
the additional application-dependent considerations of
data retention and endurance. In order to make accurate
predictions of expected failure rates, manufacturers use
data from accelerated stressing. This data is then deaccelerated to normal operating temperatures using the
Arrhenius relationship and the apparent activation energy
for the associated failure mechanism mortality function.
Similar in methodology to operating life (read) calculations, failure rates for data retention in %11 000 hours and
endurance in %11 000 cycles, may be calculated.
seeG
Technology. Incorporated
7-12
1. Number of devices per board = 96; 3 active, 93 standby,
during the operating life of the board.
2. The Icc of each device at the operating temperature
will be 50% ofthe maximum specified at -55 degrees C.
and maximum operating frequency. Programming Icc
is slightly less than read Icc; therefore, programming
Icc will be ignored. The devices are operated at a
nominal 5 volts.
3. The average reprogramming frequency is once every 8
operating hours.
4. The rail (heat sink) temperature is 71 degrees C.
Uniform heat dissipation across the PCB.
5. Thermal resistances:
a. board - rail, 9br. 3 0 CIW
b. case - board, 9cb: 2.50 CIW
c. junction - case, 9jc: 20 0 CIW
6. Base failure rates are at degrees SSC. and 90% Confidence Interval. Failure rates are accelerated according
to the Arrhenius relationship, with following apparent
activation energies (Ea):
a. read: .4 ev.
b. data retention: .6 ev.
c. endurance: .12 ev.
e. MTBF = (1/(# parts * failure rate)) * 105 • See note.
f. Board MTBF =(1/(# parts * (failure rate read + failure
rate retention + failure rate endurance)) * 105 •
7. The characteristics for the SEEQ 28C256
EEPROM are:
a. Icc active: 60 rna. max.
b. Icc standby: 250 ~a. max.
c. read failure rate: .02%/1000 hours
d. data retention failure rate: .001 %/1 000 hours
e. endurance failure rate: .05%/1000 cycles
The results of the calculations are summarized in the
following table.
The approximately 500% improvement in MTBF through
use of the SEEQ CMOS EEPROMs compared with the
NMOS EEPROMs may be attributed to two factors: the
almost 50 degrees C. higher junction temperature caused
by the higher power dissipation of the NMOS parts significantly accelerated the read and data retention failure
rates; and the initial lower endurance failure rate of the
SEEQ CMOS EEPROMs, which is not greatly affected by
temperature.
8. The characteristics for the NMOS EEPROM are:
a. Icc active: 120 rna. max.
b. Icc standby: 60 rna. max.
c. read failure rate: .02%/1000 hours
d. data retention failure rate: .001 %/1 000 hours
e. endurance failure rate: .2%/1000 cycles
9. The basic equations to be used are:
a. Junction temperature = (rail temperature + 8br *
POboard) + (8cb * PO part) + (8jc * POpart)); where
Oxx is the appropriate power dissipation.
b. Power dissipation/part Vcc nominal * Icc max. *
50%.
c. Power dissipation/board = (3 * POactive) +
(93 * POstandby).
.ll ( ..1:.. -L)
d. Arrhenius acceleration factor = e K Tn - Tj
where K = Boltzman's constant (8.62 x 10-5 )
and Tn and Tj are the normalized and junction
temperatures expressed in degrees Kelvin.
Each application will have different initial conditions;
however, through use of the above equations a board may
be calculated. The board failure rate will always be
reduced through the use of a CMOS EEPROM with lower
power requiremnts and will always be reduced when using
a SEEQ EEPROM with a lower endurance failure rate.
=
TABLE
PARAMETER
CMOS
Device power dissipation
active
standby
0.150 watts
.000625 watts
0.300 watts
0.150 watts
Board power dissipation
0.5081 watts
14.85 watts
71° C
72.52°C
72.89°C
75.89°C
71°C
115.55°C
116.3°C
122.3°C
.0466 %/1000 hrs
.0035 %/1000 hrs
.0080 %/1000 hrs
.2223 %/1000 hrs
.0370 %/1000 hrs
.0514%/1000 hrs
MTBF of Devices:
read
retention
endurance
22,318 hours
292,191 hours
129,252 hours
4,684 hours
28,097 hours
20,229 hours
MTBF of BOARD
17,868 hours
3,350 hours
Rail temperature
Board temperature
Case temperature
Junction temperature
Failure rates at calculated T J
read
retention
endurance
NOTE: Actual MTBF
seeQ
= (1-(l-f~ure rate)
III par1S
Technology, Incorporated
but equivalent to
7-13
(# par1S • faiure rate)
NMOS
for very low failure rates.
:I
.
7-14
APPLICATIONS
(Application Notes)
Memory Products
Application Note
MICROPROCESSOR
INTERFACING
WITHSEEQ's
LATCHED EEPROM
March 1985
I
seeQ
Technology, Incorporated
8-1
Microprocessor Interfacing
with SEEQ's Latched EEPROM
Introduction
This application note describes the interfacing of SEEQ's
"latched" Electrically Erasable Read Only Memory
(PROM or P) to a microprocessor bus. The latched
PROM family is comprised of a 16K 52813 and 64K
52833. On each ofthese devices there are internal latches
on all inputs except write enable. A byte must first be
erased before it can be written. In addition to the latched
PROM family, SEEQ has a timer PROM family. This
family iscomprisedofa 16K 2816A (24 pins), a 16K2817A
(readylbusy) and a 64K 2864 (ready/busy). The timer
family has internal latches on all inputs and has an internal
timer which automatically performs a byte erase before
write. In this application note, the P used is SEEQ's
52B13, a 2K x 8 memory. Since the timing of the higherdensity members of the family is compatible, the circuits
given can be extended to interface equally well with the
52B33 (8K x 8). Both bus timing and software timing are
used to gate the control signals. The case presented here
uses general control signals to permit adaptation to any
system's bus structure. In addition, modifications are
given for interfacing to specific processors.
if necessary. In the example bus interfaces shown in this
application note, gating for one device is assumed, and
E2ROM SELECTis tied directly to CHIP SELECT.
Interface Signals
The first step is initiation of a write cycle. First, the
processor issues addresses, and the system's decoding
circuitry brings CHIP SELECT valid. Although the chip is
enabled at this point, a write to the chip has not yet begun,
because MEMORY WRITE has not yet been issued. This
prevents inadvertently writing to an incorrect address as
the address lines are allowed to settle out before a write is
initiated. Following the timing events above, the active
level of MEMORY WRITE sets the flip-f~ bringing WE
low to the E2. Data, Addresses, CE and OE are latched at
this point.
The bus interface components perform other tasks common to a memory/bus interface. For a multiplexed data
bus, the bus interface components must demultiplex the
data and addresses. In addition, this bus interface circuitry
may generate MEMORY READ and MEMORY WRITE ,if
required. Details of this bus interface are given in the
section "Considerations for Special Applications," beginning on page 5.
Details of Operation
Byte Write or Erase
The timing diagram in Figure 2 shows the details of a byte
write or erase operation for SEEQ's latched PPROM
family. The two modes are the same, except that hex "FF"
is presented to the 110 lines for erasure. Due to this
similarity, only the write mode will be discussed.
The solution presented here (see Figure 1) uses an S ..ft
flip-flop (74LSOO) with TIL gates (74LS32) to latch WE for
the 52813. This flip-flop causes valid data to be latched
correctly, satisfies device setup and hold times, and allows
easy latch/unlatch to the WE signal.
The system-dependent direct bus interface components
form the second part of the interface circuit. These
components will generate CHIP SELECT and E2ROM
SELECTto enable this part of memory. CHIP SELECTis
usually generated separately for each word-wide group of
devices. In this way, it chooses the actual devices to be
written. E2ROM SELECT would be an "OR"function ofthe
CHIP SELECT signals for all the devices for which this
latch gates WE. With WE wired in common, only one
gated latch is required for the E2ROM array. Of course,
fanout must be considered, with a high current driver used
seeG
In the second part of a write, WE continues to be active low
for the entire write cycle. This requires a timeout, which
can be effected in any of several ways. The designer can
use a timing loop in software, or trigger a timer which
interrupts the processor after the correct time. The software timeout may require less hardware on-board. The
hardware timeout, on the other hand, allows the CPU to
perform other tasks. Obviously, a good compromise is a
Technology, Incorporated
8-2
ADDRESS
BUS
[===================:::::>1
ADDRESSES
OE
r-------------I
SYSTEM RESET
MEMORY READ
E2 ROM SELECT
MEMORY WRITE
CHIP SELECT
>
>
>
>
>
I
I
WE
I
I
I
I
I
~
SEEa
52BXXI
52BXXH
_ _ _ _ _ _ _ _ _ _ 14lSOj> ~
IL 74LS32
_ _ _ II
CE
110
DATA BUS
+5
CC (FOR 52833)
Figure 1. E2ROM Interface Circuit
ADDRESSES
DATA
E2 ROM SELECT
..IX
==X",,"-__
V_AL_ID
__
----IX
\\\
VALID
OONTCARE
X
OONTCARE
X____\. . \. . . .\~.
_\~\\~\L-a....\\~\\~\\-I......I\
X,,--OON_TCA_RE
m
\\\
/711
MEMORY WRITE
MEMORY READ = OE
I
CHIP SELECT = CE
WE
Figure 2. Write-Cycle TIming Diagram Latched EZROM Interface Application
seeQ
Technology, Incorporated
8-3
processor-independent flowchart handles all the erasure
and writing for storing data in the PROM, using the circuit
from Figure 1. In addition, a segment of example code
(written for the Z8) is shown (see Figure 4).
software architecture with regular (perhaps one-millisecond) timing interrupts, for system real-time synchronization. Division of the task between hardware and software
is best left to the individual systems engineer.
Regardless of the method used in the timeout, the write
pulse is terminated by WE being brought high. This is
effected by a read to any location in the device, which
resets the flip-flop to bring WE high. A second read cycle
is required for byte verify. System designers should allow
extra time between the two reads to meet write recovery
time (\vR) requirement. This method of write-cycle termination provides another form of protection against inadvertent writing to the chip. Even if a statistically unlikely
succession of glitches were to trigger both flip-flops, enable the gates, and bring WE low, a subsequent read to
the device could terminate the write before data would be
written.
Read Operation
The timing for a read (see Figure 5) is simpler than for a
write. In the read mode, the on-chip latches are transparent. The leading (falling) edge of CHi'P SELECT brings
CE low, and the falling edge of MEMORY READ brings
OE low. Data is available from the 52BXX PROM after a
delay of Toe (from OE) or TCE (from CE) . Table 1 shows the
TACC required for operation with sample microprocessors,
using no wait states. Memory devices currently available
from SEEO feature TCE as fast as 200 nanoseconds. For
certain new microprocessors (for example, the 68000 or
8085A-1) which may require faster access, SEEO offers a
high speed timer family with access times as fast as 35
nanoseconds.
For the case of a fully software-timed write, a flowchart is
given for the sequence of operations (see Figure 3). This
LOAD COUNTER
WITH PULSE
WIDTH. lms FOR
52BXXH; 10ms
FOR 52BXX
ERASES E2ROM;
WE GOES LOW
TURN OFF ERASE;
FORCES WE TO
HIGH STATE
LATCH ADDRESS
AND DATA INTO
E2ROM;
We GOES LOW
TURN OFF WRITE;
WE GOES HIGH
RETURN TO CALLING PROGRAM
* Data Is not valid during this cycle.
Figure 3. Flowchart for 52BXX EraselWrlte -
seeQ
Software Timing
Technology, Incorporated
8-4
186
187
188
189
190
191
192
193
P
P
P
P
0060
0062
0064
0067
7C
92
D6
82
FF
70
0071
80
P 0069 92
P 006B D6
P 006E 82
90
0071
80
P 0070 AF
P 0071 EC
OA
P
P
P
P
P
007E
EE
007D
F6
0073
0076
0078
007B
007D
D6
00
6D
8B
AF
P 007E FC
6A
P
P
P
P
EF
0088
F8
0080
0081
0083
0086
FF
00
6D
8B
P 0088 AF
11----------------------II The following is a general routine for
II data contained in the working register
II DataReg to an EEPROM in
II the location pointed to by the working
II pair AdReg. This EEPROM is assumed to
II external data memory of Z8.
II Write FF to erase byte.
register
be in the
194 EEWR:
LD
OutReg,
#%FF
195
LDE
@AdReg ,
OutReg
196
CALL
WaitWP
I I Wait for Twp
197
LDE
NowReg,
@AdReg I I Turn off WE
198 II Now, write the data to the part.
199
LDE
@AdReg,
DataReg
200
CALL
WaitWP
I I Wait for Twp
201
LDE
NowReg,
@AdReg I I turn off WE
202
203 FinWr: RET
II return from routine
204 II End of EEPROM Write Routine
205 11-------------------------------------------------206
207 II Timing routines
208 WaitWP:LD
RLoop2,
#Twp II # of ms to wait
209
II 10-> wait 10 mS.
210
II 1 -> wait 1 mS.
211
Wait1ms
212 WPLoop: CALL
213
DEC
RLoop2
214
JP
Z, DunWP
215
JR
WPLoop
216 DunWP: RET
II Done with Twp.
217
218 II Basic 1 msec timing routine219 II adjust for microprocessor crystal freq.
220 II The value of Hex58 (Dec88) works with
221 II a Z8 with a 6.144 MHz xtal.
222 II Use %6A for 7.3728 MHz xtal.
Elimination
223 II of NOP, or xtal substitution, will
224 I I require recalibration.
225 Wait1ms: LD
RLoop3,
#%6A
226
227 Timlp: NOP
228
DEC
RLoop3
229
JP
Z, Dun1ms
230
JR
Timlp
231
232 Dun1ms: RET
II Done with wait
233
234 II End of EEPROM Timing Routines
235 11---------------------------------
Figure 4. Sample Z8 Code for 52BXX Write
seeG
writing
Technology, Incorporated
8-5
I
Table 1. Zero-Walt State Required Minimum TAcc
(Assuming zero delay for buffers and drivers)
To terminate the read, the rising edge of MEMORY READ
brings OE high. CE, however, is dependent only on CHIP
SELECT, and remains active low for the entire microprocessor cycle.
Clock Freq.
(MHz)
Required TACC
(nanoseconds)
72720
S085A1S085AH
SOS5A-2/S085AH-2
10
3
5
350
S085A-1/S0S5AH-1
S086/S0SS
SOS6-2/8088-2
S086-1
Z8
ZSO
ZSOA
Z80B
6S00
6
5
S
10
8
2
2.5
175
402
267
227
310
575
325
190
605
Microprocessor
Considerations for Special Applications
Use with Z8, Z8000 Systems
The implementation of the circuit shown in Figure 1 in a
Z-BUS application allows simple generation of the control
signals. First, the control signals MEMORY READ and
MEMORY WRITE can be generated by one half of a
74LS139 decoder, as in Figure 6. In addition, for the Z8,
the lower byte of addresses must be latched, due to multiplexing of address and data. This can be easily accomplished with an 8212 octal latch, as in figure 6. Interfacing
to a Z8000 (or 16-bit Z-Bus) requires an additional 8212
latch, to demultiplex ADs-AD,s' ps, the Z-Bus address
strobe, is active low, and must be connected to the active
low input in order to clock these latches.
460
270
6
1
Use with ZOO Systems
Use with 8085 Systems
The circuit shown in Figure 7 provides a bus interface to a
Z80, Z80A, or Z80B processor. In Figure 7, MEMORY
READ and MEMORY WRITE are generated from combining MREQ with the Z80 RD and WR, respectively. Since
address and data are issued by the Z80 processor on
separate lines, the 8212 latch is not needed.
The implementation of the PROM interface circuit in an
80S5 system is extremely simple. Figure S shows the bus
interfacing necessary. MEMORY READ and MEMORY
WRITE are issued by the processor directly. However,
MEMORY WRITE must be delayed, as shown in Figure 8,
to ensure latching of valid data. CHIP SELECT is gener-
ADDRESSES
DATA
E2ROM SELECT
CHIPSELECT=CE
MEMORY READ = OE
DON'T CARE
X. . ______
X
_ _ _ _ _ _ _ _ _ _ _ _ _..I
VALID DATA
DO_N_'_T_CA_R_E_ _
X"'________
'1//1 \.......a...\\..I...--_ _--&...,.j/ZL....&.-Z""'--'"I/..,&.,.,..ZZl....'II/I \-..-.\\________1 \\\\\
'111/
Figure 5. Read-Cycle Timing Diagram
seeQ
..IX. . __
VA_L_ID_ _ _ _ _ _
Technology, Incorporated
8-6
RESET
SYSTEM RESET
+i16
-
4
2
RIW
MEMORY WRITE
112
-OS
3
74LS1~
S
MEMORY READ
pI
Gl
-
E2ROM SELECT
+S
124
ZS
A15
A14
A13
A12
All
19
20
21
22
23
G2
0
+S
C74LS154
B
A
rm
CHIP SELECT
0
GNO
112
12~
1
T24
~
OOa
00 7
00 6
MO
OS2
~
L.l!.
CLR
-AS
005
00 4
00 3
00 2
8212
~
~
OSI
001
~
~
~
TO CIRCUIT
IN FIGURE 1
~
~
~
~
..L-.
Ola 017 DiS 01 014 Oh 01 2 011
A0 7
AD6
ADs
AD4
AD3
AD2
A01
22120118116
9
7
S
3
1 I
1
ADo
A a ·A1o
Figure 6. Interfacing to a Z8
Interfacing with 72720 Systems
ated from the top 5 address bits and IOiM , using a
74LS154decoder. The RESETtothe 8085 processor also
supplies RESETforthe PROM interface. Finally, the demultiplexing of address and data lines is accomplished by
a 74LS373 latch triggered by ALE. Alternatively, an 8212
latch can be used but requires more board space.
The 52BXX PROM can be interfaced to SEEQ's new
72720 microcomputer (with 2K x 8 on-board PROM) more
easily than to any other processor. The 72720 PRG
instruction operates off-board, to program an external
PROM. This instruction initiates latching and timing of
WE, as well as presentation of valid data. These tasks are
handled automatically within the 72720. As a result, the
write enable latch circuit of Figure 1 is not required. Total
52BXX interface hardware, shown in Figure 9, is very
simple, even including a 74LS373 latch to demultiplex the
lower eight bits of address. The software required for
programming is shown in Figure 10. This example subroutine erases and writes one byte.
Interfacing to 8088/8086 (Minimum Mode) Systems
The above considerations for implementation of this solution in an 8085 system may also apply to an 8088/8086
system operation in minimum mode, with two additions.
As above, the processor issues ALE, RD, WR, and multiplexed address/data. However, an inverter is required in
order to produce 101M from MIlO. In addition (for an 8086),
another octal latch must be added, in order to demultiplex
ADa-AD 1s'
Interfacing with the 6800
One example of a complete interface between a 6800
processor and a 52BXX is shown in Figure 11. The DBE
signal from the 6800 is delayed for a time between 250 and
350 nanoseconds, in order to provide a strobe for valid
data. This data strobe clocks RiW into the flip-flop at the
correct time, so that the falling edge of WE can satisfy
The time delay indicated in Figure 8 depends on the type
of processor used and its clock frequency. For a 5 MHz
8088/8086, this time delay should be 100 nanoseconds;
for an 8088-2/8086-2 at 8 MHz, it should be 60 nanoseconds. For a 10 MHz 8086-1, the time delay should be 50
nanoseconds.
seeQ
Technology, Incorporated
8-7
I
R-E-SE-T D - - - - - - - - - - - - - - - - - - - - - - - - - -.... SYSTEM RESET
RD
r----I
}J)_-::~---------------l
..
D-------~-I--a
1
MEMORY WRITE
i --- 1
~J)-~:~---------------l.. MEMORY READ
MREQ P-------4......
WA
1
RFRSH
Z80 BUS
1
~~""o----+I-a:J
:
~
~ ~4 ~L~~ ~
TO CIRCUIT
IN FIGURE 1
AO-A,O~========================~======================~~
DO-D7~=======================t====================~
-'15
19 G2
J--------=20~D
-'143 J-_____
--=2.;.1-1C
-'12
22 B
-'I,
23 A
5
1124
OXD------------4I...--~~ CHIP SELECT
'---~~
74LS154
E2ROM SELECT
GND
Figure 7. Bus Interface -
zao
'Oi
1
s-y--STBIRESET
....
~
I
L~
1
AD
\VA
1
.-1
I
1
I
cc
(FOR 52833)
'----1I .. ~I --...,
1
I
~
DECODER
-
Ox
I-D--s
ill
WE
I
%-+5
-./ : j
2.2K~
CE
I
~ _ _ _ _ _ _ _ _ _7~S~ ~
80
70
80
50
40
8085
OCTAL
LATCH
~
OE
1
1
leo
1___
Au-A,s
30 6
20 5
10
ENABLE
,
19
16
15
12
8
2
A7
As
11' 117 114 113
7
4
A,
AD
3
D7
Ds
Ds
D.
D,
1 J I
1 1
D2
D,
DD
Aa-A,D
Figure a. Bus Interface Circuitry - 8085 System
Technology, Incorporated
8-8
52BXX
E2ROM
As
A.
A3
A2
8D 7D 6D 5D 4D 3D 2D lD
A,-A,D
seeG
C
I
I~
-
IcVM
AD7
AD,
ADs
AD.
AD,
AD2
AD,
ADD
PO:
D Pol'"
ClK
ALE
l
I
ideas. PROM technology, while still advancing rapidly
has proven to be the memory breakthrough ofthe eighties.
With a reliably nonvolatile approach to alterable program
memory, systems for control of avionics, manufacturing,
and data acquisition can be enhanced in usefulness. With
the timing to use the advanced technology of PROMs, the
system designer can incorporate more features now, while
allowing still more flexibility for the future.
timing requirements with respect to valid address, data,
and control signals.
Conclusion
This application note has been prepared to assist the
designer in implementing the technology of latched
PROMs in systems requiring adaptability. The designer
is encouraged to create new designs based on these
Z-Bus, za, zaooo, ZaOA, and zaOB are trademarks of Zilog.
28
9 VO o
PORT Co
29
C1
10 V0
C 2 30
C3
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11
13
14
15
31
32
33
34
35
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3
4
7
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13 114117 T18
2
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6
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16
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38
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11
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6
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SEEQ72720
SEEQ 52BXX
27
DO
0 1 26
O 24
23
As
22
Ag
19
2
03
04
05
06
07
vss
A 10
23
22
21
20
19
Bs
Bs
39
1
23
22
21
20
18
~+5
A
B
C
0
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74LS154
18
Ox
~~
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116
ENABLE
3
RIW
2
1
112
74LS139
G1
Lf
40
Figure 9. 72720 Interface
seeQ
1
V0
2
V0
3
V0
4
1105
16 V0
6
17 V0
7
Technology, Incorporated
8-9
-
CE
+5-0 CC (FOR 52B33)
4
21
-
5
20
-OE
WE
I
o
ERRORS
7000 ASSEMBLER REV 1.3
>
*********************************************************
0001 9000
*
0002 9000
*
EEPROM AUTO ERASE BEFORE WRITE ROUTINE
*
*
0003 9000
*
0004 9000
*
DATA TO BE PROGRAMMED IN REGISTER 102
*
*
0005 9000
LOCATION TO BE PROGRAMMED IN REGISTERS 100/101 *
0006 9000
*
*
*
0007 9000
*********************************************************
0008 9000
0010 9000
*
DATA TO BE PROGRAMMED
EQU R102
0020 9000 0066 EEDAT
POINTER TO LOCATION
EQU R101
0030 9000 0065 EEADR
SAVE ACCUMULATOR
EEWR
PUSH A
0040 9000 B8
MOV %>FF,A
IS LOCATION ALREADY ERASED?
0050 9001 22
9002 FF
CMPA *EEADR
0060 9003 9D
9004 65
JEQ PROG
0070 9005 E2
9006 00
PRG *EEADR
IF NOT PROGRAM WITH FF HEX
0080 9007 04
9008 65
MOV EEDAT,A
IF ERASED PROGRAM DATA
PROG
0090 9009 12
900A 66
PRG *EEADR
0100 900B 04
900C 65
0110 900D B9
POP A
RESTORE ACCUMULATOR
RETURN
RETS
0120 900E OA
END
0130 900F
<
Figure 10. 72720 Code for Programming 52B13/33
SYSTEM RESET
~
-
RIW
OE
V
6800
Microproc:easor
--Ao PR
"'5
G2
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0
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-
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112
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CE
+5--<:
DBE
CC (FOR 52833)
Ao·A,o
Ao·A,o
0 0 .0 7
110 0 .00 7
NOTE: THIS ELEMENT OF THE CIRCUIT SHOULD DELAY A
RISING EDGE (A TTL LOW·TO-HIGH TRANSITION)
BY 250 (MIN) TO 350 (MAX) NANOSECONDS.
Figure 11. 68OO/52BXX Interface
seeQ
Technology, Incorporated
8-10
Communications Products
Application Brief
INTERFACING
THE 8003 EDLC @
TO A 16-BIT BUS
March 1985
I
seeQ
EDLC is
Technology I Incorporated
a registered trademark of SEEQ Technology, Inc.
8-11
Interfacing the 8003 EDLC®
to a 16-Bit Bus
Introduction
is connected to the Transceiver by the Access Unit Interface (AUI) cable. This cable consists of 78Q balanced,
shielded twisted-pair connections, DC biased at the station end and transformer-coupled at the Transceiver end.
The SEEO 8003 Ethernet Data Link Controller (EDLC )
chip together with the SEEO 8023A Manchester Code
Converter (MCCTM) chip provide an economical two-chip
solution for the Data Link Layer and Physical Layer of the
Ethernet protocol. These chips are fully Ethernet compatible and suitable for use in terminals, personal computers,
workstations, printers, disk drives and host computers.
Besides a passive tap to the Trunk Coax, the transceiver
provides signal amplification, preconditioning on the receive path, impedance matching, DC isolation, collision
detection and collision signaling generation. DC power for
the Transceiver circuits is provided through the cable.
The 8003 is a VLSI data link controller chip in a 40-pin
package. It replaces approximately 60 MSI and SSI components in a typical Ethernet node configuration. The
choice of which one to use is governed by the system
interface requirements for the design. The 8003 provides
protocol functions like frame formatting, link access control and error control. The part is optimized for Direct
Memory Access techniques for frame storage.
Host-Dependent System Interface
There are three basic methods for interfacing the CSMAI
CD channel to the system bus. The first one employs FirstIn, First-Out (FIFO) buffer memory to temporarily hold the
transmit and receive frames. On the system-bus side of
the FIFOs, data is transferred serially a byte at a time by the
processor. The second method uses Direct Memory
Access to transfer data directly between the Ethernet Data
Link Controller and the system memory. In the third
method, Direct Memory Access is also used, this time with
a temporary buffer memory intervening between the system memory and the EDLC chip. The intervening buffer relieves the system bus of some of the traffic and timing
requirements associated with the channel. (For more information on DMA-type interfaces, see SEEQ's Application Brief 6).
The 8023A MCC Manchester Code Converter performs
the signal encoding and decoding in Manchester Code at
10 million bits per second. It also monitors the channel for
"carrier" and "collisions" (two nodes transmit simultaneously). Low-power CMOS technology is used in the
8023A, which is in the 0.3 inch 20-pin package.
Ethernet Node Configuration
A typical Ethernet node is shown in Figure 1. The System
Interface on the left connects the host system bus to the
network. This interface varies depending on processor
and system requirements.
The station-resident hardware, consisting of the System
Interface, the 8003 EDLC chip and the 8023A MCC chip,
MCC is a trademark of SEEQ Technology, Inc.
seeQ
Technology, Incorporated
8-12
AUI
CABLE
SYSTEM
BUS
SYSTEM
INTERFACE
I
HOST-DEPENDENT
INTERFACE
/'11..----1 TRANSCEIVER
I
DATA LINK
LAYER
I
PHYSICAL
LAYER
TRUNK
COAX
Figure 1. Ethernet Node Configuration
IEEE 802.3 CSMAlCD Standard Protocol for
Local Area Networks (Alias Ethernet)
access method used in Ethernet alias IEEE 802.3
CSMAlCD. Carrier Sense means all nodes on the
network can detect all signals transmitted on the
network from any source. Multiple Access means all
nodes can have equal access to the network without
need for centralized control. A node is permitted to
transmit if the network is not already busy. If, however, two or more nodes start to transmit simultaneously, it is called a collision. Collision Detection
means that all nodes can detect a collision by monitoring the medium. When a collision occurs, the transmitting nodes resolve which will retransmit first by
differential backoff timing.
The first Ethernet local area network was implemented in Palo Alto, California in 1975 as a joint effort
of Stanford University and Xerox Corporation. Since
then, Ethernet has been expanding in use and accumulating history. Over the years, it has proven to be
reliable and efficient in a wide variety of network
applications. As a result, it has become the first
industry-standard protocol for local area networks,
supported internationally by computer manufacturers
in the U.S. and Europe.
In 1980 the Institute of Electrical and Electronics Engineers (IEEE) sponsored a committee to review,
document and publish this protocol as an international industry standard. After three years of review
and refinement, this specification is about to be published by IEEE Press under the title IEEE 802.3
CSMAlCD Local Area Network Standard Protocol,
("CSMAlCD" describes the medium access method,
Carrier Sense, Multiple Access with Collision Detection). The IEEE 802.3 document supersedes all
previously published Ethernet specifications.
Data is transmitted in "packets" or "frames" which
begin with a preamble for synchronization and end
with a CRC field for error detection. In between, the
frame has source and destination addresses, a bytecountfield and an information field. Total frame length
is 72 to 1526 bytes.
The physical signaling format used in Ethernet is
baseband Manchester Code transmitted at a rate of
10 million bits per second. In Manchester Code, each
bit is encoded by a transition. A "one" is encoded as
a low-to-high transition and a "zero" as a high-to-Iow.
In this way there is a continuous supply of bit-framing
information for the receiver, since the transmitted
signal is never stationary for more than one bit time.
CSMAlCD • Carrier Sense, Multiple Access with
Collision Detection
CSMAlCD: This expression describes the medium
I
seeQ
Technology, Incorporated
8-13
Interface Techniques for 16-Blt Busses
Split-Word 16-81t Data Interface
Ethernet is a byte-oriented protocol. That is to say, the
smallest unit of data which can be transmitted is a byte.
Hence, the 8003 EDLC chip has byte-wide data bus.
Whether the System Interface is the FIFO-buffer type or
the DMA type, the data transfers to and from the 8003 are
byte-wide. This application brief describes some techniques for interfacing this byte-wide communication channel to a 16-bit wide bus.
Refer to Figure 3 for a circuit diagram of this technique.
The split-word method splits the 16-bit word into two
halves, using one half for transmit data and the other for
receive data. In Figure 3, the upper byte ofthe system data
bus is used for the transmit memory buffer and the lower
half for receive. Two 74LS244 tristate buffers isolate the
system bus lines from the RxTxDO-7 bus of the 8003. The
upper 74LS244 is enabled by TxACK from the DMA Controller. TxACK is the DMA Acknowledge signal for the
transmit channeL When enabled, this buffer transfers a
byte of data from the upper byte of system memory to the
8003's Transmit FIFO. Similarly, the lower 74LS244
transfers data from the 8003's Receive FIFO to the lower
byte of system memory. Configured in this way, the transmit and receive buffers in system memory can occupy the
same word-address space.
In designing an Ethernet node, trade-offs have to be made
between processing speed and communication speed,
cost and performance, flexibility and simplicity, etc. The
right balance may be different for each piece of equipment
designed, depending on its purpose and system requirements. In order to help you strike the right balance for your
design, several interface techniques will be given in the
following sections. They are covered in order of increasing
cost/complexity/performance.
Full-Word 16-Blt Interface Using Byte-Wide Memory
Transfers
In an 8-bit system, the 8003 can be interfaced directly to
the data bus as shown in Figure 2. The RxTxDO-7 bus is
the bus for transferring frame data. It connects to the
internal 16-byte transmit and receive FIFOs. The CdStO-7
bus is a separate input/output port for control and status.
It interfaces to the system bus so that the processor has
direct access to all command and status bits. In a 16-bit
system, CdStO-7 would connect either to the upper or
lower data byte.
Another type of 16-bit interface is one that assembles and
disassembles words by transferring the upper byte and th e
lower byte separately. For example, suppose the convention is chosen that the upper byte is to be the first of the two
bytes to be transmitted and the lower byte the second.
Then the first byte of a frame and all odd-numbered bytes
are always transferred to/from the upper byte of memory,
and the second and all even-numbered bytes to/from the
lower.
0 0-7
..01 .......
0.!-15
HI DATA
A
...
"4
,..
00-7
"" LODATA
TxWR
r-:
CdSt O_7
E
-
-
~
74LS244
BUFFER
r--
r--
RxACK*
i
8003
66
...
"
E
...
,..
,;4-- 74LS244
' r - BUFFER
RxTxD O_7
'"OATABUS' ....
~","
,
8003
RxRD
...
RxTxD o_7
* FROM OMA CONTROLLER
DATABUS
Figure 3. Split-Word 16-81t DMA Data Interface
Figure 2. 8-81t DMA Data Interface
seeG
Technology, Incorporated
8-14
This is the simpler and more economical oftwo "Full-Word"
data interfaces described in this application brief. The
other one, shown in Figure 5, assembles and disassembles words in registers, and transfers 16 bits at a time.
The advantage of the latter approach is in saving bus
bandwidth, since it uses half as many bus cycles to transfer
the same amou nt of data; but there is some additional cost
in hardware.
The data interface forthis approach is a variation ofthe one
shown in Figure 3. Two tristate buffers are replaced by two
bi-directional transceivers. AO, the least-significant bit of
the DMA Controller'S address is decoded with TxACK and
RxACK to enable the transceivers. The more significant
address bits from the DMA Controller, A1 through AN' are
used as the memory address. Upper and lower memory
strobes are also controlled by AO. Refer to Table 1 forthe
truth table.
Table 1. AO Address Decoding or Full-Word 16-Blt Interface Using Byte-wide Memory Transfers
DMA Controller
Outputs
AO
Transceiver Enabled
Toward (MemorYi 1/0)
Upper
RxACK
1
1
-
-
0
0
1
1/0
-
1
0
1
-
1/0
0
1
0
Memory
1
1
0
-
-
Note: -
Memory Activity
Lower
TxACK
Upper
Read
-
-
Write
-
Memory
Lower
Read
Write
indicates not active.
a.No Request, No Walt
b. With Request
REQUEST ASSERTED
c. With Request and Acknowledge
d. With Request, Acknowedge and Bus Arbitration
REQUEST ASSERTED
Figure 4. Data Transfer State Diagrams -
seeQ
REQUEST ASSERTED
Four Types
Technology, Incorporated
8-15
I
Helpful Hints for State Machine Designers
Four types of data transfers are shown in Figure 4.
The first, labeled a, is an unconditional transfer sequence such as the type that would be used to refresh
a CRT screen. This type has no use in an Ethernet
interface since it is not controlled by availability of
storage space or stored data.
As with writing a program, it is desirable to start with
a ''flow chart" or "state diagram". Examples of state
diagrams can be seen in Figure 4. The following are
the definitions used in the circle-and-arrow state diagrams used here.
The diagram in Figure 4 Part b, illustrates a transfer
which is initiated "on demand". The transfer takes
place only when a "request" is given. An example of
this type is data moved by a processor on its own synchronous bus. Physically the request is generated by
the processor, manifesting itself as a set of buscontrols, and an address.
1. Each circle represents a single physical machine
state or an unconditional sequence of machine
states such that there are no "hidden branches"
omitted from the diagram.
2. All conditional branches, and wait states (which
may be viewed as conditional branches) are indicated explicitly by arrows. Each arrow is labeled
with the condition which determines the branch.
Part c illustrates a transfer that is requested by one
entity and acknowledged by another. The acknowledge signal is used to notify the requesting entity that
the transfer is about to take place. This implementation provides the requesting entity verification that the
transfer is taking place. The diagram represents the
response of the acknowledging party to the request.
The requesting party normally waits for the acknowledgement to occur. This allows the acknowledging party to delay, if necessary, for data access.
This mechanism is used on asynchronous busses,
like that of the .68000 microprocessor.
Following these or similar guidelines will help to avoid
unforseen anomalies in the operating flow.
Care should be taken in defining the programs for
state machines when inputs are asynchronous with
respect to the state-register clock. Problems can
result when making a conditional branch based on an
asynchronous input. Such problems can cause intermittent branching failures with possibilities of perverse consequences. Intermittency makes this type
of problem hard to diagnose, so it pays off to avoid
them by following these design rules:
The diagram in Part d is that of a transfer with request,
acknowledge, and bus arbitration. This implementation is one that is used to transfer information using a
OMA controller on the main system bus. There are
actually two request/acknowledgement sequences in
this transfer, one for bus acquisition and one to
transfer information on the acquired bus, Initially a
request generated by one of the two '1ransferees"
queues the DMA controller to exit its idle state, and
arbitrate for the system bus by generating a "bus
request" signal. When the bus master relinquishes
the bus, a "bus grant" acknowledgement is received,
notifying the DMA controller that it now owns the bus.
The DMA controller then performs the transfer, or
transfers, by generating a "DMA Acknowledge" to the
original requesting device, and generating the appropriate addresses and read/write control signals. Finally the sequence is terminated with control of the
bus returning to the main processor through another
arbitration.
1. When a branch is conditional on an asynchronous
input bit, assign next-state addresses such that
only one state-register flip-flop is affected by the
asynchronous bit.
2. For a 3 or more-way conditional branch based on
more than one independent asynchronous bit,
break it down into independent 2-way branches
which conform to rule 1.
3. For inputs which are mutually-dependent combinations of 2 or more bits, it is best to synchronize
them with an input register whose clock is synchronized to the state-register clock.
When you have finished the state diagram, you have
defined the operating program design. The next step
is to choose the hardware that can run your program
most efficiently.
Diagrams like these can be used to design state
machine programs for interfaces like the one in Figure
5, which employs a single-chip state machine.
seeQ
After choosing the hardware, you can translate the
state diagram, verbatim into program code for the
state machine.
Technology, Incorporated
8-16
-TxC
-ACKl
-REaO
-ACKO
REOl
82371
116171
QUAD
DMA
-TxREO
lL-
J
TxACK
-RxREO
RxRDY
RxRD
TxRDY
-TxWR
RxACK
~
4.7K :: :4.7K
+5
CONTROLLER
I
e.g. 82S159
OR 82S10SA
STATE
MACHINE
CK
::~4.7K
.,;>-
EOF
-<
+5
EOP
D8-15
I~~~~~T~
D0-7
..
8003
-
~
~
INT
I-
~ OEA
¢:: ~
CKA
OEB
14-
CK~ f4-
A
+5~
B
.
10K~
~ SBA
74Lse62
SAB~
-
'--
-
-
I
REGISTERED
VOPORT
.
-OEA
OEB
CKA
CK~ f4-
...
RxTxDo_7
f4A
B
A
74Lse62
REGISTERED
VOPORT
r- SBA
.
HI DATA
LODATA
DATA BUS
SAB~
~~10K
+
•
Figure 5. 16-Blt FUll-Word DMA Data Interface with 8237/9517 Using Registered 1/0 Ports
Full-Word 16-81t Interface Using Registered
1/0 Ports
This data interface method assembles/disassembles 16bit words in a pair of 8-bit registered 1/0 ports. The data
transfers betwee n the memory and the 1/0 ports are 16 bits
wide. Transfers between the ports and the 8003 EDLC
chip are byte-wide.
A state machine is used to sequence the assembly and
disassembly processes. Programmable single-chip state
machines and logic blocks, available from multiple
sources, are excellent for this type of design. Most are
field-programmable one time by burning fuseable links.
Normally, the state machine portion of the design can be
done in one or two chips.
Registered 1/0 ports are configured by taking two 8-bit Dtype registers with tri-state outputs and connecting them
front-to-back. The result is two 8-bit bus connections,
each connected to the D inputs of one register and the tristate outputs of the other. The port has two register clocks
and two output-enable controls. An example of such a chip
is the 74L5652. The more popular 8-bit registered 1/0 port
chips on the market are in the 0.3 inch 24-pin package.
A circuit example with the 8237/9517 DMA Controller
appears in Figure 5. A single-chip state machine, such as
the 5ignetics 825159 or 8251 05A, coordinates the timing
for all other components. Two 74L5652s are the two
registered 1/0 ports. The bus lines on the right side of the
ports are commoned to make an 8-bit connection to the
RxTxDO-7 pins of the 8003. On the left, the 16 port lines
connect to the data bus.
This interface technique can be used with some variation
for any of the three basic types of system interface, i.e. 1.
with FIFO frame buffers, 2. with DMA to off-line frame
buffers or 3. with DMA to system memory.
seeQ
Technology, Incorporated
8-17
I
moved to the Transmit FIFO, ending the cycle.
Refer to Figure 7 for the word assembly state diagram.
Word assembly starts in the Idle 1 State. Here, the state
machine waits for a signal from the Receive FIFO (RxRDY
pin) indicating data is present. When RxRDY is high, the
machine advances to load the first byte of the word being
assembled to the upper port. As the data is read out of the
FIFO, the 8003's EOF line is tested to determine if it is the
last byte of the frame. If it is, reading of the second byte is
skipped. If not, the Idle 2 State is entered. When ready, the
second byte will be loaded into the lower port. Then a DMA
Request is given. The DMA Controller will then request the
bus, acquire it and give the DMA Acknowledge. Then the
state machine passes through the Transfer State, writing
the 16-bit word to system memory. That ends the word
assembly cycle.
Most of the command signals associated with data transfer
are sequenced by the state machine. DMA requests
(REOO and REOO1 ), port output-enable line OEB, register
clock CKB, Transmit FIFO write (TxWR) and Receive
FIFO read (RxRD) are all under state machine control.
Output-enable OEA and register clock CKA are controlled
by the DMA Acknowledge lines. All the status lines for data
transfer connect to the state machine's inputs.
Figures 6 and 7 summarize the state-machine state diagrams for the application in Figure 5. Refer to Figure 6 for
the word disassembly diagram. The disassembly process
starts with a DMA request issued to the DMA's transmit
channel. Ifthe channel is not enabled, no acknowledge will
be given and the state machine will remain in the DMA
Request State. If the channel is enabled, the DMA Controller will request and acquire the system bus, then issue the
DMA Acknowledge. A 16-bit word of data is then read from
system memory into the two ports. The next state is Idle
1. Here the state machine waits for a TxRDY ready signal
from the 8003 if not already present. When TxRDYis high,
the machine goes to the Read First Byte State. This state
moves the upper data byte from the upper port into the
Transmit FIFO of the 8003. Another idle state occurs
where TxRDY is checked for Transmit FIFO readiness.
When ready, the lower data byte from the lower port is
Further References Available from SEEQ
8023A MCC Data Sheet
8003 EDLC Data Sheet
Application Note 3: Manchester Encoding and Decoding
for Local Area Networks
Application Brief 6: DMA Interconnection to the 8003
EDLCTM
NO
ACKNOWLEDGE
Figure 6. State Diagram for 16-81t Word Disassembly
seeQ
Technology, Incorporated
8-18
Figure 7. State Diagram for 16-81t Word Assembly
Communications Products
Application Brief
DMA
INTERCONNECTION
TO THE
B003EDLC@
March 1985
I
seeQ
Technology, Incorporated
EDLC is a registered trademark of SEEQ Technology, Inc.
8-19
DMA Interconnection
to the 8003 EDLC
Introduction
SEEQ's 8003 Ethernet-compatible data link controller
provides an economical communication interface for terminals, personal computers, workstations, printers, disk
drives and host computers. The 8003 is a 40-pin VLSI
device which can replace approximately 60 MSI and SSI
components in a typical Ethernet node configuration.
expanding in use and accumulating history. Over the
years, it has proven to be reliable and efficient in a wide varietyof network applications. As a result, it has become the
first industry-standard protocol for local area networks,
supported internationally by computer manufacturers in
the U.S. and Europe.
This application brief is about design techniques for an
Ethernet node when direct-memory access (DMA) is
chosen as the means of transferring data between the
system bus and the channel. The methods described
herein can be applied to virtually any computer or system
bus architecture.
In 1980 the Institute of Electrical and Electronics Engineers(IEEE) sponsored a committee to review, document
and publish this protocol as an international industrystandard. After three years of review and refinement, this
specification is about to be published by IEEE Press under
the title IEEE 802.3 CSMAlCD Local Area Network Standard Protocol. ("CSMAlCD" describes the medium access
method, Carrier Sense, Multiple Access with Collision
Detection.) The IEEE 802.3 document supersedes all
previously published Ethernet specifications.
Ethernet local area networks use the broadcast network
topology. That is to say, a signal transmitted by any station reaches all other nodes on the network. This is in
contrast to other types of networks, such as the "star" and
the "ring", which use point-to-point interconnections.
Transmitted messages in Ethernet are "broadcast" on a
segment of 50 coaxial cable. Communication nodes are
attached to this cable via passive taps, so that new nodes
can be added at any time without interrupting the network
service. Nodes on the network can be addressed individually, in "multicast" groups, or by the "broadcast mode" to all
nodes simultaneously. The broadcast topology is a very
efficient mode of communication, yet it is simple and
inexpensive to implement.
CSMAlCD· Carrier Sense, Multiple Access with Colli·
slon Detection
CSMAlCD: This expression describes the medium access
method used in Ethernet alias IEEE 802.3 CSMAlCD.
Carrier Sense means all nodes on the network can detect
all signals transmitted on the network from any source.
Multiple Access means all nodes can have equal access
to the network without need for centralized control. A node
is permitted to transmit if the network is not already busy.
If, however, two or more nodes start to transmit si multaneously, it is called a collision. Collision Detection means
that all nodes can detect a collision by monitoring the
medium. When a collision occurs, the transmitting nodes
resolve which will retransmit first by differential backoff
timing.
Ethernet alias IEEE 802.3 CSMAlCD
The first Ethernet local area network was implemented in
Palo Alto, California in 1975 as a joint effort of Stanford
University and Xerox Corp. Since then, Ethernet has been
seeQ
Technology, Incorporated
8-20
bits per second. In Manchester Code, each bit is encoded
by a transition. A "one" is encoded as a low-to-high
transition and a "zero" as a high-to-Iow. In this way there
is a continuous supply of bit-framing information for the
receiver, since the transmitted signal is never stationary
for more than one bit time.
Data is transmitted in "packets" or ''frames'' which begin
with a preamble for synchronization and end with a CRC
field for error detection. In between, the frame has source
and destination addresses, a bytecount field and an information field. Total frame length is 72 to 1526 bytes.
The physical signaling format used in Ethernet is baseband Manchester Code transmitted at a rate of 10 million
SYSTEM
BUS
SYSTEM
INTERFACE
I
HOST-DEPENDENT
INTERFACE
14----~
I
DATA LINK
LAYER
I
PHYSICAL
LAYER
/ ' 4 - - - - f TRANSCEIVER
TRUNK
COAX
Figure 1. Ethernet Node Configuration
Figure 1 shows a typical CSMAlCD node configuration. The System Interface connects the host system
bus to the network. This interface varies depending
on processor and system requirements.
The Data Terminal Equipment hardware, consisting
of the System Interface, the 8003 EDLC chip and the
8023A MCC chip, is connected to the Transceiver by
the Access Unit Interface (AUI) cable. This cable
consists 78 balanced, shielded twisted-pair connections, DC biased atthe Data Terminal end and transformer-coupled at the Transceiver end.
Data Link functions are performed by SEEQ's 8003
EDLC Ethernet Data Link Controller chip. Thisdevice
performs medium access control, frame formatting
and error detection.
Besidesthe passive tap to the Trunk Coax, the Transceiver provides signal amplification, preconditioning
on the receive path, impedance matching, DC isolation, collision detection and collision signaling generation. DC power for the Transceiver circuits is provided
through the cable.
The Physical Layer functions, carrier sense, collision
signal detection, data signal encoding and decoding
are performed by SEEQ's 8023A MCCTM Manchester
Code Converter chip, Manchester Code is the physical signaling format used on the network. Data is
transmitted on the network at a rate of 10 million bits
per second.
I
MCC is a trademark of SEEQ Technology, Inc.
seeG
Technology, Incorporated
8-21
DMA DIRECTLY TO/FROM
SYSTEM MEMORY
SYSTEM
BUS
DMA WITH DEDICATED BUFFERS
SYSTEM
BUS
Figure 2. SEEQ's Ethernet Chip Family: 8003 EDLC
Ethernet Data Link Controller I 8023A MCC
Manchester Code Converter
Figure 3. DMA System Interface Techniques-
Direct Memory Access System Interface
nel. The DMA Controller must meet this speed requirement or frames will be lost. If the system is to support
loopback diagnostics, both transmit and receive DMA
channels will have to operate simultaneously, together
transferring 2.5 million bytes per second. Not just any
DMA Controller will do.
There are two basic methods for interfacing the CSMAlCD
channel to the system bus using DMA, illustrated in Figure
2. The first method uses DMA to transfer data directly
between the Ethernet Data Link Controller and the system
memory. In the second method, a temporary buffer
memory intervenes between the system memory and the
EDLC chip. The intervening buffer relieves the system bus
of some of the traffic and timing requirements associated
with the channel. These two methods will be the subject
of the following sections.
Bus Bandwidth
This is only a consideration for systems with heavy communications traffic and/or critical response timing. The
transfer of data on the system bus can sometimes use up
a considerable percentage of the bus time, at least for
short bursts. If this is a problem, the method with dedication buffer memory can be used to offload the system bus
(see Figure 2 bottom).
DMA Design ConSiderations for Ethernet
In designing an Ethernet node, some trade-offs have to be
made between processing speed and communication
speed, cost and performance, flexibility and simplicity, etc.
The right balance can be different for each piece of equipment designed, depending on its purpose and system requirements. In order to help you evaluate the trade-offs for
your design, this section discusses some of the key
parameters for you to consider at the outset.
With or Without Dedicated Buffer Memory
It the system architecture does not support 1.25M Bytesls
DMA, the dedicated buffer approach can solve the timing
problem. If the system architecture does support highspeed DMA, then bus bandwidth is the key factor which influences this decision. In this case it is clearly a cost-performance issue. The dedicated buffer can relieve system
bus traffic, but it takes more hardware to implement.
Time Is Data
Cycle-steal or Burst Mode DMA
Since the data transmission rate for Ethernet is 10 million
bits per second, data transfers during active periods will
have to keep up. That means data has to be moved at 1.25
million bytes per second to/from the communication chan-
seeQ
Refer to Figures 3 and 4. In the Cycle-steal DMA Mode, the
DMA Controller "steals" a bus cycle to transfer one and
only one byte or word of data. In the Burst DMA Mode,
Technology, Incorporated
8-22
A transfer to the transmitter of the 8003 begins with a DMA
Request given by the 8003 (its TxRDYpin goes high). The
DMA Controller then issues a Bus Request to the processor. Aftercompletingthe current cycle, the processor halts
and gives a bus grant to the DMA Controller, which then
transfers the data by issuing a DMA Acknowledge and all
necessary address and control signals. Additional transfers would take place if Burst Mode is used until the
Transmit FIFO is full, indicated by the TxRDY pin going
low. Then the bus is released to the processor and the
DMA cycle is over.
each time the DMA Controller acquires the bus, it can
transfer several bytes or all the data to fill or empty a buffer.
Either of these two modes can work for Ethernet in principle if the transfer speed is adequate. The Burst Mode is
usually preferred by reason of timing efficiency. In Burst
Mode, bus arbitration and change-over delays are kept to
a minimum. Also, Burst Mode allows the DMA Controller
to fill or empty a buffer in one DMA cycle.
On Demand
Transfers between memory and the communication circuitry must be done on demand. Some DMA Controller
chips will only transfer blocks of data in predetermined
lengths. This will not work since the processor and DMA
Controller cannot know in advance how many bytes of
data can be transferred at a given time.
Data transfer from the Receive FIFO happens in the same
way but with data flowing in the opposite direction. It starts
with a DMA Request from the 8003 (its RxRDY pin goes
high). If Burst Mode is used, the DMAwill continue to transfer until the Receive FIFO is empty, indicated by a Iowan
the RxRDY pin.
Maximum Bus Grant Latency
The time it takes to get the bus after a request is made is
called bus grant latency. If the DMA method without buffer
memory is used, each time a DMA transfer to/from the
S003 EDLC chip begins, the DMA Controller must arbitrate
for and acquire the system bus. If the latency is too long,
the transmitter may underflow or the receiver overflow.
The 8003 has transmit and receive FIFOs which are 16
bytes deep, so it must transfer data at least once every
12.S microseconds when active (16 x SOO nanoseconds).
Maximum bus grant latency should be deterministic and
always less than that required to prevent underflow and
overflow.
The Data Interface for a DMA node with buffer memory
appears in Figure 6. In this case, a 4-channel DMA
Controller is used. Two channels are needed as before to
transfer data between the 8003 and memory. These two
channels operate "off-line" and do not require bus arbitration. The other two transfer data between the buffer
memory and the system bus. They do require the usual
bus arbitration.
For this design, the RxTxD0-7 ReceivelTransmit Data Bus
of the 8003 connects to a separate bus which is isolated
from the system bus by a transceiver. This bus gives the
S003 immediate access to the buffer memory without the
need for arbitration.
8003/DMA Node Hardware
The S003 has an 8-bit bi-directional data bus (RxTxDo-7)
for data transfers to and from its internal FIFOs. In Figure
6, the node hardware is configured to transfer data directly
to/from system memory over this bus. (This is the technique referred to previously in Figure 3 at the top.) A twochannel DMA Controller is used, providing one channel for
transmit data and one for receive data.
The two channels for memory-to-memory transfer use the
usual bus arbitration method to access the system bus.
For these two channels, data being transferred passes
through the transceiver shown in the top center of the
figure. The tri-state buffer appearing at the bottom center
passes the address from the DMA Controller to the System
DMA REQUEST
I
Figure 4. DMA Cycle-steal Mode State Diagram
seeQ
Figure 5. DMA Burst Mode State Diagram
Technology, Incorporated
8-23
."'"
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h~RXTXD()'7
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Figure 4. Implementing a local bufer for Ethernet traffic, using static RAM(a), and dynamic RAM (b).
DRAMs are lower In cost, but require refresh circuitry.
seeQ
Technology, Incorporated
8-32
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Figure 5.
The 8005 Advanced Ethernet Datallnk Controller: It supports a local buffer via DRAM, keeps its
Ethernet address and configuration data In Its own on-board PROM, and provides a very flexible
and sophisticated link between your system and Ethernet,
seeG
Technology, Incorporated
8·33
I
COAX.
r-----------
:L
- - - - - - - cLusTER"CONrRcX.LER 1
HARDWARE
PRINTER
PRINTER
PRINTER
NETWORK
ADDR=XX
NETWORK
ADDR=YV
NETWORK
ADDR=ZZ
TERMINAL
ORP.C.
TERMINAL
ORP.C.
TERMINAL
ORP.C.
Figure 6. You can connect up to six devices to one Ethernet node using the capability of the 8005 to decode
up to six station addresses. In this example, three printers and three PCs or terminals are
connected to one Ethernet Node. The 8005 and Its system CPU controls Ethernet access to and
from the devices.
DRAM chips provide an ample 64 Kbytes of Packet Buffer
storage. The 8005 allows you to partition this buffer into
receive and transmit areas of your own choice.
fields per packet (destination and source), eight bytes are
saved.
Ethernet specifies a minimum "slottime" of 51.2 microseconds. This represents the time required for one round trip
of a packet on a maximum length cable, and is required for
reliable collision detection. The 8005 may be configured
for a slot time of 12 microseconds, which shortens waiting
time after a collision. Additionally, when you select the
shorter slot time, the 8005 automatically reduces the
Collision Jam Pattern from 8 to two bytes, and reduces the
interframe spacing from 9.6 to 2.4 microseconds.
Finally, the diode RC network provides a power on reset
pulse (minimum 10 microseconds wide) for both the 8005
and 80186.
The 8005 In Non Ethernet Applications
The Ethernet, because of its simplicity and high speed, is
often used in smaller physical con figurations than those
for which it was originally intended. Applications include
communications between processors in a large parallel
process ing engine.
Refer to the 8005 data sheet for more detail on selecting
these optional parameters.
The 8005, because of its configurability, can be "trimmed
down" for use in networks which need not strictly follow the
Ethernet format.
Configuring the 8005
This step is required following hardware reset or software
reset. Note that a hardware reset must be provided following power on. Following reset, allow 10 microseconds after
the reset before attempting access to the part.
The Ethernet address is six bytes long. The 8005 may be
configured to accept just a 2 byte address, saving four
bytes per address in a packet. Since there are two address
seeG
Technology, Incorporated
8-34
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Technology, Incorporated
8-36
39.2 OHMS 1%
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INTERCONNECT DIAGRAM
8005,16 BIT BUS, MOTOROLA MODE
seeQ
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8005 AND INTEL 80186
Figure 9. The use of the 8005 and the Intel 80186 to implement a board level intelligent Ethernet data link. The
80186 Is a good companion for the 8005, since it has an on-chip DMA controller. The 8005 supports
an address PROM, and 64 Kbytes of DRAM to serve as a local Packet Buffer.
Configuring includes loading the Ethernet station
address(es), selecting transmit and receive packet buffer
size and defining interrupt conditions and an optional
interrupt vector.
when in 16 bit mode, and is shown as a "Don't Care" (X).
In 8 bit mode, Ao selects the low order byte when a ZERO,
and the high order byte when a ONE.
Reading the Address (EE) PROM
All this information may be stored in a PROM on the same
PC board as the 8005. This allows the assigned Ethernet
station address(es) to travel with the board.
After reset, if you are using a local Address PROM, write
that location to the DMA Address Register which points to
the first configuration byte in the PROM. Select access to
the Address PROM by writing 0006 to the Buffer Code Bits
in Configuration Register #1. The 8005 will then drive the
chip enable line of the PROM via APEN (pin 10) for each
Read or Write to the Buffer Window Register. When all
configuration and station address bytes have been moved
into system RAM, the next step is to write them into the
8005.
Register Architecture
The general approach to initializing the 8005 consists of
reading information from the PROM into system RAM and
writing it back into several registers inside the chip. See
Figure 10, which depicts the Register Model of the 8005.
There are nine 16-bit registers which are directly accessible by using the signals Chip Select, I/O read, I/O write
and A1 through A3 • There are also four registers which are
selected by the buffer window code bits and accessed
indirectly through the buffer window register.
In the discussion below, note that the 8005 has been
configured for a 16 bit bus. Input Ao (pin 54) is ignored
seeQ
Loading Indirect Registers
Indirect registers are selected by the buffer code in Configuration Register #1 and accessed through the buffer
window register. All indirect registers are 8 bits wide and
therefore only use data bits DoD7'
Technology, Incorporated
8-37
I
Station Address Registers
Configuration Register #2
To load the station address registers, select the desired
station address register set by writing a value from 0000 to
0005 to Configuration Register #1. Then write the appropriate 6 byte address to the buffer window register, one
byte at a time, with the most significant byte first, and the
least significant byte last. Each write automatically increments an internal pointer register to the next byte of the
station address. Repeatthis process until you have loaded
all desired station address registers.
Following reset, this register is configured for IEEE 802.3
compatible network interface. It contains bits to select nonIEEE 802.3 network operation, diagnostic modes (CRC
enable/disable for both receive and transmit), enable
receiving packets with errors (short frames, dribble errors,
CRC errors, overflow errors), select byte order for 16 bit
bus and enable automatic receive end area update.
Specify Transmit Buffer Size
Load this register with the same value as the Receive Start
Area (16 bit Transmit End Area address plus hex 0100).
Save this value, since it points to the first byte of the next
packet header, and you will need itto find the next received
packet.
Initialize Receive Pointer Register
Write a 0007 to Configuration Register #1 to select the
Transmit End Area register. Write an 8 bit value to the
Buffer Window register which specifies the most significant byte of the last address in the Transmit Buffer space.
In the example above, the Transmit End Area address was
hex 17FF. Therefore, the Receive Pointer Register should
be loaded with hex 1800.
For example, to define space for four packets, each 1514
bytes long:
1514 X 4 =
4X4=
6056
16
bytes for data
bytes for header
6072
bytes required;
---
60721256
=
Initialize DMA Address Register
If no packets are to be loaded into the transmit area, load
this register with the contents of the Receive Pointer
Register.
23+, or hex 0017
Command/Status Register
Thus, we would write hex 0017 to the transmit end area
register. This also sets the receive buffer area, by default,
to start at hex 1800, which leaves 58 Kbytes (hex FFFF
minus hex 1800) for receive packets.
Set RxON (bit 9), and, if desired, RxlNT Enabl (bit 1) to
ONEs. If you are not using interrupts, you may poll RxlNT
(bit 5) to see if a frame has been received.
If interrupts will be enabled and an interrupt vector is
required, write a 9 into Configuration Register #1 to select
the Interrupt Vector Register, and then write the 8 bit
interrupt vector into the Buffer Window Register.
Transmitting a Frame
This discussion assumes that the system is connected to
an IEEE 802.3 compatible network. The contents of a
Transmit frame have no meaning to the Packet Buffer
Controller and the Ethernet Data Link Controller circuitry,
and can be arbitrary in length and content. As discussed
above, transmission of the Preamble and CRC (frame
check sequence) can be suppressed under software
control for specialized network requirements or diagnostic
tests.
Specify Receive Buffer Size
Write an 8 bit value into the least significant byte of the
Receive End Area Register to specify the most significant
byte of the last buffer address for receive packets. This
would normally be hex FF if the rest of the local buffer is to
be used for received frames.
After you have gone through the configuring as outlined
above, the 8005 is ready to receive or transmit frames.
Refer to Figure 2 and recall that a frame consists of from
64 to 1514 bytes, which includes a 6 byte destination
address, a 6 byte source address, and an area for data all
of which is supplied by your system software. The entire
frame has a prefix containing a 62 bit preamble (which
synchronizes the phase-locked-loop in the Manchester
Code Converter with respect to the received packet), and
a 2 bit start frame delimiter. Following the data field there
is a 4 byte frame check sequence. All of the components
of the prefix and the CRC are supplied by the 8005.
Loading Direct Access Registers
Initialize Transmit Pointer Register
Write 0000 to this register.
Configuration Register #1
Loading this register defines receiver match modes, enables station address register sets and sets up DMA burst
interval and size. Access this register by setting A3 - Ao to
001X.
seeQ
Technology, Incorporated
8-38
BUSSIZE
STATUS
REGISTER
CONFIGURATION
REGISTER'1
CONFIGURATION
REGISTER'2
NOT USED
RE.A. REGISTER
RECV. POINTER
REGISTER
TRAN. POINTER
REGISTER
D.M.A. ADDRESS
REGISTER
4
16
4
BUSSIZE ----I~
~----~------------~~--~
48 BIT STATION REG' 1
48 BIT STATION REG'2
48 BIT STATION REG #3
48 BIT STATION REG'4
48 BIT STATION REG #5
8 BIT TRANS. END AREA
8 BIT INTERRUPT VECT.
64K BYTE
16
PACKET
BUFFER
Figure 10. Register Model, which Illustrates the register architecture Inside the 8005. Using both directly and
Indirectly accessable registers lowers pin count. All access to Indirect registers and the Packet
Buffer Is through the Buffer Window Register.
seeQ
Technology, Incorporated
8-39
I
A packet is prepared for transmission by writing into the
Transmit Buffer Area a 4 byte header, followed by the
destination address, the source address, and finally the
data field. Refer to Figure 11. You may choose to do this
via programmed 1/0, or via an external DMA controller.
Frames may be chained together up to the capacity of the
available Transmit Buffer Area by using the Next Packet
Pointer (first two bytes) and the Chain Continue bit (bit 6)
in the Transmit Header Command byte.
BUFFER
BUFFER
ADDRESS CONTENTS
X'OOOO'
BiTt
7
6
5
<4
3
2
1
0
0
NEXT {
PACKET
POINTER
0
HEADER
COMMAND BYTE 1
HEADER 0
STATUS BYTE
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
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Refer to Figure 12. Read the Status Register to see if the
DMA FIFO direction is set to write to the Packet Buffer (bit
15 cleared). If it is and the DMA register is not going to be
loaded with a new value then data can be written immediately. If the DMA register is to be changed, then check to
ensure that the FIFO is empty (Status Register bit 4 set).
If the FIFO is not empty, continue testing bit 14 until the
FIFO is empty. If you change the FIFO direction or write to
the DMA Register, FIFO contents will be cleared.
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If necessary, load the DMA Register with the address for
the first byte of the Packet Header, and write Packet
Header and data into the FIFO. The first Packet Header
address is normally 0000.
~
~
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Figure 13 depicts the same operation, only under DMA
control, After you set up the system DMA controller, set
DMA ON (Command Register, bit 8), and DMA Interrupt
Enable (Command Register, bit 0), if desired. The former
enables the DMA request logic, and the latter causes an
interrupt to be generated at the completion of a DMA operation i.e., when terminal count has been input.
NEXT {
PACKET
POINTER
HEADER
COMMAND BYTE
HEADER
STATUS BYTE
0
0
0
0
0
0
0
0
X'OO'
1
0
0
0
1
1
1
1
X'SF'
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
cm
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After all of the packets in a given chain have been written
into the Transmit Buffer Area, load the Transmit Pointer
Register with the address of the first byte of the first
transmit packet header, set TxON (bit 10) and, optionally,
TxlNT Enabl (bit 2) to ONEs in the Command/Status Register.
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The 8005 will then read the first header, which is pointed
to by the Transmit Pointer Register, and process that
packet, and all additional packets in the packet chain in
turn. Any retransmission of a packet due to a collision will
be automatically handled by the 8005, thus relieving your
system from having to transfer that packet of data more
than once.
~
X'OOSF'
When a packet has been successfully transmit ted (or 16
collisions occur), the Done bit (bit 7) in the transmit header
status byte will be set to a ONE. The Transmit Buffer Area
occupied by that packet is now available for another
packet, and may be written to at the same time as subsequent packets are being transmitted. The 8005 will move
to the next packet in the chain.
LAST BYTE OF DATA
Figure 11. Transmit Packet Chain, residing In the
Packet Buffer, and ready to be transmitted. Two
packets are In this chain. Note that the Packet
Buffer Is nondestructively read, and the packets are
stili In the buffer after they have been transmitted.
after transmission, the 8005 updates the Header
Status Byte (byte 4). The first two bytes of the
Packet Header point to the address of the first byte
of the second Packet Header.
When all packets in a chain have been completed (transmitted successfully or collided 16 times), the 8005 resets
TxON (bit 10) in the status register to indicate that it is
seeQ
NEW PACKET
HEADER CHAIN
STARTS HERE
Technology, Incorporated
8-40
ready to transmit another packet chain. If 16 collisions
occur on a packet, the 8005 stops transmission attempts
for that packet only and moves to the next packet in the
chain, if one exists. In the example in Figure 11, bits 2 and
3 are ON in the transmit header command byte which will
cause the 8005 to set the transmit interrupt bit in the status
register and, if enabled, interrupt the processor when 16
collisions occur or the transmission is successful.
2. As a linear buffer, where you reset the transmit pointer
to 0000 after each packet chain transmission.
Receiving Frames
Once the 8005 has been configured and the receiver
enabled, frames which meet the match mode and station
address requirements specified in Configuration Register
#1 and the enable bits 2·5 in Configuration Register #2 will
be moved into the Receive Buffer Area beginning at the
address contained in the Receive Pointer Register.
The last packet inthe chain is denoted by havingthe Chain
Continue bit cleared to a ZERO. The Next Packet Pointer
points to the address follow ing the last byte of the last
packet.
When one or more packets are available in the receive
area, the 8005 sets Rx Interrupt (bit 5) in the Command!
Status Register to a ONE. If receive interrupts are enabled.
(Command Register bit 1 set), then the external interrupt
(pin 11) is asserted. Frame header and data can now be
read by loading the DMA Register with the start ing
address of the Packet Header and executing successive
You may treat the transmit packet buffer in one of two
ways:
1. As a circular buffer with wraparound, where you remember the address to load new packet headers and packet
data. The DMA register automatically wraps around to
address 0 when the transmit end area has been reached.
SET FIFO TO WRITE
DIRECTION
SET FIFO TO WRITE
DIRECTION
LOADING TRANSIIT PACKETS INTO
LOCAL BUFFER PROGRAMMED 1/0
SET DMA INTERRUPT
ACKNOWLEDGE BIT
LOADING TRANSMIT PACKETS INTO LOCAL
BUFFER DMA TRANSFER WITH INTERRUPT
Figure 12. Loading Transmit Packets Into the local
Buffer. under Programmed 1/0 conditions. Note
that. If you change the direction of the DMA FIFO. or
load the DMA Pointer Register. you will lose any
data stored In the FIFO.
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DMA INTERRUPT
Figure 13. Loading Transmit Packets into the Local
Buffer under DMA transfer. using Interrupt.
Technology, Incorporated
8-41
I
ized, the address is the beginning of the Receive Packet
Buffer which was determined earlier in this note (hex
1S00). If packets have been previously been read this
address will be the location of the header last read that had
the chain continue/end bit reset.
reads. If Auto Update REA (bit 1 of Con figuration Register
#2) is set, the Receive End Area Register will be updated
with the upper byte of the DMA register each time a DMA
read occurs. This releases buffer space as its contents are
read, and allows for the receipt of more data at the same
time as data is being read out.
The next step, referring to Figure 17, is to turn off the Auto
Updat REA (Configuration Register #2, bit 1). This insures
that the S005 will not use the area occupied by this packet
chain for new receive data.
The action taken on a receive packet depends on the
status of the packet and its contents. If the packet status is
bad, it may be skipped entirely without transferring any of
its data to system memory by loading the Receive End
Area Register with the most significant byte of the next
packet pointer. This will release the buffer space of the
previous packet for future packets. In like fashion, if the
packet data shows it to be an "overhead" packet (such as
a Packet Acknowledgement), this can be so noted in
network software and the packet skipped. Thus, unnecessary transfer of the packet over the system bus can be
avoided, and system bandwidth preserved. If the packet
data must be processed, just the information portion of a
packet (exclusive of any bytes used to pad the packet to a
minimum size) can be read to system memory by programmed 110 or by an external DMA controller.
Read each Packet Pointer in turn, and then read the
Header Status byte immediately after the Pointer, which is
Byte #3. Bit 6 of Byte #3 is the Chain Continue bit. Continue
reading this bit in each packet header until this bit goes to
ZERO. This signals the end of the chain. Save the local
buffer address of the first byte of this last header as this is
the address of the header for the next packet received.
Subtract the address of the first header in the chain from
this address. If the result is a positive number, you have the
chain length directly.
If the result is negative it denotes that the Receive Pointer
Register has wrapped around past the beginning address
of the receive area. The chain length will be equal to the
sum of the receive buffer size plus the value (including
sign) of this result. You already know the buffer size, since
you defined it during configuration of the S005: hex FFFF
minus the receive start address (defined during configuration) plus 1. For the previous example, the buffer length is
hex ESOO (FFFF -1S00 + 1). Load the chain length into the
DMA controller, and set Auto Updat REA. You are now
ready to read data out ofthe receive buffer and into system
memory.
Receive Packet Chaining
The 8005 automatically chains together receive packets
using a circular FIFO buffer structure. Each packet is
prefaced by a 4 byte header whose first two bytes form a
16 bit address that points to the next header. A chain of
packets always ends with a header-only packet whose 4
bytes equal 00. The address of this header-only packet
should be saved, since it will contain the header of the next
packet received. It is a simple matter to follow the packet
chain from header to header until the chain Continue/End
bit is read as a ZERO, calculate the length of the chain and
set up the DMA Register and an external DMA con troller
to transfer the entire chain of packets to system memory if
desired. This is advisable in applications where high
average receive data rates are expected and data must be
moved quickly from the local buffer to the system memory
at the expense of bus bandwidth. To minimize system bus
utilization, packets can be moved one at a time; this
permits moving only the information content of a packet.
There are two ways to read Packets out of the Local Buffer:
1. Via programmed I/O.
2. Via DMA transfer.
The front end portion of each procedure is the same: first,
check to see if the FIFO is empty; then set it to Read. If the
FIFO is not empty, check to see if it is in the Write direction.
If not, load the DMA Register with the address of the next
Packet Header. If this is the first Packet to be read, this
address will be that which was derived when you defined
the Transmit Buffer size during configuration of the S005.
Calculating Packet Chain Length
In order to perform a DMA transfer, you need to give the
DMAcontrolierthe "count"; i.e., how many bytes (or words,
in a 16 bit system) will be transferred. To do that, you need
to calculate how many bytes are available in the Packet
Buffer as a result of receive activity.
Reading Packets Using Programmed 1/0
The data path between the local buffer and the host bus is
buffered by a 16 byte FIFO called the DMA FIFO. It serves
as a rate buffer between the host and the local buffer,
especially for 16-bit data transfers. Because the local
buffer is a shared resource (there are 4 ports including the
DRAM refresh port), the initial read from the buffer window
which follows loading the DMA register may take eight
microseconds worst case. The S005 signals this delay by
Refer to Figure 17. This flow chart illustrates the steps
required to calculate the length of the packet chain.
The first step requires that you know the Packet Buffer
address ofthe last packet header read in the most previous
receipt of Ethernet data. If the S005 has just been initial-
seeG
Technology, Incorporated
8-42
Reading Packets Using DMA
deasserting Ready (if Busmode = 1) or delaying Dtack
(if Busmode = 0). If this initial read wait state is unacceptable, then the buffer window interrupt feature can be used.
The buffer window interrupt is asserted for programmed II
o reads (not DMA reads) when the DMA FIFO has data
available.
The second approach is by DMA transfer. See Figure 15.
After loading the DMA Register, load the system DMA
controller with the destination address in system memory,
and the previously calculated packet chain length. Then
set DMA ON (bit 8 inthe Command Register). This enables
the DMA Request logic inside the 8005. Optionally, set
DMA Interrupt Enable, which will cause an Interrupt to be
generated when the DMA controller has asserted Terminal Count. The DMA Request output signal will be asserted when there are a sufficient number of bytes in the
DMA FIFO to satisfy the DMA Burst Size (2, 4, 8, or 16
bytes) which you selected earlier when configuring the
8005.
Under Programmed 1/0 control (see Figure 14), after you
load the DMA Register, read Status Register bit 7, Buffer
Window Interrupt or wait for a hardware Buffer Window
Interrupt if it is enabled. When the interrupt is asserted,
read Packet Header and data out of the receive FIFO, via
the Buffer Window, until all bytes have been transferred.
SET DMA INTERRUPT
ACKNOWLEDGE BIT
READING A PACKET FROM LOCAL
BUFFER PROGRAMMED 110
DMA INTERRUPT
READING A PACKET FROM LOCAL BUFFER
DMA TRANSFER WITH INTERRUPT
Figure 14. Reading Packets out of the FIFO using
the Programmed 110 procedure.
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Fgure 15. Reading the Local Buffer under DMA
control.
Technology, Incorporated
8-43
I
Interrupts
Babble Interrupt
There are several interrupt sources in the 8005. This
section describes these interrupts and how to service
them. For this discussion, refer to Figure 18.
The 8005 will transmit packets as large as will fit in the
transmit buffer. The IEEE 802.3 standard specifies a
maximum packet size of 1514 bytes. The babble interrupt
indicates that a packet larger than 1514 bytes was transmitted.
Transmit Interrupts
There are four transmit interrupt sources in the 8005;
Babble, Collision, 16 Collisions, and Transmit Success.
Each of these can set the transmit interrupt bit in the status
register if so programmed in the transmit header command
byte. If Tx Interrupt Enable (Command Register bit 2) is
set, the 8005 will also assert an interrupt on pin 11. The
transmit interrupt is cleared by setting TxlNTACK (bit 6) in
the command register.
Collision Interrupt
When a packet collision occurs, the 8005 packet buffer
controller automatically restores its transmit pointer to the
beginning of the packet and schedules retransmission
following the back off time. In some applications it may be
desirable to record the number of collisions that occur.
This bit enables setting the TxlNT bit in the status register
for each collision.
CHAIN LENGTHBUFFER SIZE +
RESULT
BUFFER WINDOW INT.
READING A PACKET FROM LOCAL BUFFER
USING BUFFER WINDOW INTERRUPT
Figure 17. The steps necessary to calculate the
length of a Packet Chain. You need to
save address of the last header in the
last the packet read, in order to perform
the calculation.
Figure 16. Reading a Packet from the local Packet
Buffer using the Buffer Window Interrupt
approach.
seeQ
Technology, Incorporated
8·44
PACKET PACKET
BUFFER BUFFER
ADDRESS CONTENTS
X'l88E'
X'188F'
8
5
..
3
2
1
LAST
BYTE ~----Itl------I
OF
PACKET
NEXT HEADER I--_ _ _.....~--___I
WILL GO HERE_lt--_---'-F;.;.;RE;;.:;;E..:;.BU.:..;.F..;..;FE.:..;.R'--_
X'F840'
The 8005 counts the number of collisions that occur on
each packet. If a packet has collided 16 times, the usual
cause is a network fault such as an unterminated coaxial
cable or an open in the cable. This interrupt notifies the
host that a packet has collided 16 times, and the packet
buffer controller will now abandon transmit attempts for
that packet and move on to the next packet in the chain if
one exists.
---1
ll-----~
X'1800'
16 Collisions Interrupt
BIT.
7
__I;
FIRST { 1 1 1 1 1 1 0 0
PACKET
I----------i
POINTER
0 1 0
0 0
1 0
0
HEADER ~---------I
1 0
1
1 0 0
COMMAND BYTE 1 1
HEADER 1 0
0
1 0
0 0 0
STATUS BYTE
Transmit Successful Interrupt
This interrupt indicates that a packet was successfully
transmitted with less than 16 collisions.
If:
!!l
~
i
•
Receive Interrupts
0
0
The 8005 sets the receive interrupt bit (status register bit
5) whenever a packet that meets the criteria in bits 2 - 5 of
Configuration Register #2 has been placed in the local
buffer. It will remain set and, if the receive interrupt enable
bit is also set, the external interrupt will remain asserted
until the receive interrupt acknowledge bit is set. If a
separate interrupt for each packet is desired, the receive
interrupt should be acknowledged within 70 microseconds, which is the minimum time for receipt of a subsequent 64 byte packet. If more than 70 microseconds
elapses before acknowledging a receive interrupt, it is
possible for additional packets to be added to the packet
chain.
ift
8!
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0
~
X'FC44'
0
NEXT {
PACKET
1
POINTER
HEADER 1
COMMAND BYTE
HEADER 1
STATUS BYTE
0
0
1
1
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
0
The 8005 protects the receive interrupt condition such that
if a new interrupt is being generated while the host is
setting the receive interrupt acknowledge, the receive
interrupt will persist. If, however, a new frame is received
after the interrupt acknowledge and before the calculation
of the packet chain length, the packet chain which is read
will include the new packet associated with the new
interrupt. The new interrupt, when serviced, will now be
associated with an empty packet since it was part of the
previous chain.
0010000
I--_ _ _ _~If:----__I
I--_ _ _ _z3 ______
~
~
I-----:i------~
I-----~-----~
I-------~----~
I-------~------~
DMA Interrupts
The DMA interrupt bit in the status register is set following
receipt of terminal count from the external DMA controller.
if the DMA interrupt enable bit (command register bit #0) is
also set, an external interrupt will be asserted. The interrupt is cleared by writing a 1 to the DMA interrupt acknowledge bit.
t--------~------~
X'FFFF'
Figure 17a. Example of two receive packets In a
packet chain with wraparound.
seeG
Technology, Incorporated
8-45
I
Self-Test and Network Diagnostics
violate the Ethernet specification), it does receive while
transmitting, as long as the packet destination address fits
the receiver match mode.
The 8005 contains a number of special features for selftest and network diagnostic support.
Loopback
Cable Opens/Missing Terminator
Two forms of loopback are possible with the 8005. Local
loopback is accomplished when the 8005 is connected to
an 8020 Manchester Code Converter. When bit 11 of
Configuration Register #2 is set, the loopback pin of the
8020 will be brought low. This causes transmitted data to
be looped back to the receiver of the 8020. If the packet
transmitted meets the match mode and is addressed to
one of the 8005's enabled station addresses, it will be
received and placed in the local buffer. Using diagnostic
control bits 9 and 10 in Configuration Register #2, it is
possible to transmit packets with CRC errors to check the
receive CRC logic, and to include the CRC in a receive
packet to check the transmit CRC logic. Loopback can
also be accomplished by connect ing the 8020 to an
Ethernet transceiver. Because the network is half-duplex,
any data transmitted will also be received. Thus the same
loopback test as above can be performed while the network is active by simply sending a packet to oneself.
An open coaxial cable or a missing cable terminator results
in the transmission line being terminated in an infinite
impedance. Thus, any data transmitted will be reflected
back from the impedance mismatch some time delay after
it is transmitted. This time delay depends on the physical
distance to the impedance mismatch, so the length of the
packet must be large enough to insure that data are still
being transmitted after one round trip propagation delay to
the mis match. A 256 byte packet should be an adequate
size. The reflected signal will partially cancel the transmitted signal and cause a collision to be detected by the
transceiver. Thus an open is indicated by repeated collisions when transmit ting a packet or, if the network is
known to be quiet (no other nodes active), asinglecollision
when transmitting. It is also possible to make a rough
determination of where the fault is by enabling receipt of
packets with errors (Configuration Register #2 bits 3 - 5)
and then counting the number of bytes correctly received.
Note that if the cable open is very close to the transmitting
node, the collision may occur during the preamble and the
8005 would unconditionally reject the receive packet.
Interrupts
The 8005 has separate control bits for turning on an off the
receive logic, transmit logic and DMA logic. The interrupts
for these fu nctions can be tested without actually performing the function by setting both the on and off control bits
simultaneously. For example, if the receive interrupt logic
is to be tested set both RxON and RxOFF bits in the
command register. This will cause the receive interrupt bit
in the status register to be set and, if the receive interrupt
enable bit is also set, will cause an external interrupt. This
mode has no effect on any logic other than the interrupt
logic and associated status register bit, i.e., packets can be
transmitted and received while this diagnostic mode is set.
Cable Shorts
A shorted coaxial cable causes premature loss of carrier
sense to the receiver of the 8005 while it is transmitting. It
is therefore possible to send a packet of at least 256 bytes
to oneself with the receiver enabled to accept frames with
errors. A cable short results in a truncated receive packet;
the size of the receive packet indicates the rough distance
to the cable short.
Detecting Network Cable Faults
It is possible to make a gross determination of cable faults
by taking advantage of the full-duplex nature of the 8005:.
although it will not transmit while receiving (that would
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Technology, Incorporated
8-46
UJ
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~
iii
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iii
~
~
XMIT SUCCESSFUL
STATUS
REGISTER
16 COLLISIONS
a:
UJ
0
<:
UJ
J:
Tx INT. ACK.
~
COLLISION
iii
0
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D-§
~
iii
BABBLE
11
PACKET AVAILABLE
COMMAND
Rx INT. ACK.
COMMAND
REGISTER
REGISTER
DMAFIFO
LOAD COMPLETE
STATUS
REGISTER
BUF.WINDOW
INT. ACK.
TERM COUNT
STATUS
REGISTER
DMA INT. ACK.
Figure 18. Functional diagram of Interrupt logic.
I
seeQ
Technology, Incorporated
8-47
8-48
Memory Products
Application Note
EEPROM
INTERFACING
April 1987
I
seeQ
Technology, Incorporated
8-49
EEPROM Interfacing
Introduction
The continuing rapid evolution in semiconductor PROM
memory device technology offers the system designer an
ever-increasing choice of function and capability. With
these increasing choices for PROM devices, however,
comes the problem of standardization (or lack thereof)
concerning such specifications as endurance, timing characteristics, interface requirements, ad infinitum. Today,
there are two popular types of commercially available
E2ROM devices.
When the designer attempts to use the advantages of both
in the same system, a problem is encountered.
One of the most frustrating problems facing a system designer is the design of an PROM/microprocessor interface that will allow compatible operation of timer and
latched type PROM devices in the microprocessor-based
system. The purpose of this application note is to give
examples of cost-effective designs of PROM/microprocessor interfaces, which allow the use of both timer and
latched E2ROM devices in the system with no changes
required to either the controlling software or the hardware.
With the interfaces shown in this application note, it is
possible to operate with BOTH latched and timer devices
simultaneously in the system if the device access times
are compatible.
Both of these types of devices have the JEDEC approved
pinout shown in Figure 1, including the multi-functional pin
1, but differ in the timing of the control interface. The first
PROM type, the latched type device, such as SEEQ's
52B33 latches the addresses, control, and data inputs on
the falling edge of WRITE ENABLE (WE). For this type
device, the WE input must remain active low for the
duration of the write cycle. The second type of PROM, the
timer-type device, latches addresses, data, and control
signals on the rising edge of WRITE ENABLE or the
risingedgeof CHIP ENABLE (CE). Forthetimerdevice,
such as SEEQ's 2864 the WE input need not be held low
for the entire write cycle. The primary difference between
the latched and timer devices is the control timing required
to interface to the microprocessor. Each of these types of
devices has advantages depending on system performance and configuration requirements.
LATCHED
SEEQ 52833
The microprocessor interfaces described in this application note are for the 8085, 8086, 8088, Z80™, and 71840.
Software examples are provided for the Z80 and 71840
processors. By extension, the Z80 code is easily transportable to 808X processors. In most cases, the hardware
required for compatibility consists of only two additional
standard (14-pin) TIL packages.
It is hoped thatthese example interfaces will assist the system designer in implementing PROMs in his system. By
no means are these special cases presented to limit the
system designer, but to provide a starting point for his
design. The interface circuits presented are for the family
of PROM devices (16K, 32K, and 64K). Other extensions
ofthe ideas presented may permit lower power, lower cost,
or optimization of other parameters deemed more important.
TIMER
SEEQ2864
Vcc
MF
Vcc
WE
NIC
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AS
AS
Ag
A11
A9
An
OE
OE
A10
A10
WE
CE
CE
1/07
1/07
I/Os
I/OS
1/05
1/04
1/0 3
Figure 1. JEDEC Pinout -
1/00
1/0 1
1/0 2
GND
The body of this application note consists of two sections.
First, the Basic Operation section gives the theory of operation of all of the interfaces and should be read to familiarize oneself with those factors common to all of the microprocessor interfaces. Second, the Microprocessor Interface section details the design of the TIL interface required for the given microprocessor.
1/05
1/04
1/03
64K E2ROMs
Z80 is a trademark of Zilog, Inc.
seeQ
Technology, Incorporated
8-50
Basic Operation
Each of the E2ROM microprocessor interfaces described
in the next section integrates hardware and software to
achieve compatibility between latched and timer PROM
devices. Naturally, both hardware and software are processor-dependent. However, the write cycle used is basically the same for all the examples shown.
have timing compatible with both, since the major difference between latched and timer PROM devices is the
timing of the write control interface to the microprocessor
(see Introduction). The basic waveforms for latched and
timer PROMs are shown in Figures 2a and 2b, respectively. The latched type PROM device acquires data on
the leading edge of WRITE ENABLE (WE). The timer
type device acquires data on either the traili ng edge of WE
or the trailing edge of CHIP
ENABLt£E). Interface
For compatibility between the latched and timer E2ROM
devices, the interface provides control waveforms that
ADDRESS
~
OE
We
VO
'OS
HIGHZ
(WRITE)
VO
HIGHZ
(ERASE)
r-
BYTE ERASEIWRITE PERIOD-------.-.,..,I..I>--START OF NEXT MODE
Figure 2a. Latched E2ROM Write Cycle
I
Figure 2b. Timer E2ROM Write Cycle
seeQ
Technology, Incorporated
8-51
The flow chart for writing to the E2ROM is the same for all
microprocessors and is shown in Figure 5. After a Write
command is issued, time is required to allow proper writing
to the storage cell of the E2ROM device. A Read command
is then issued to terminate the write operation. Note that
this Read command is not to be used to actually read the
E2ROM device, but is inserted to reset the logic circuits
used to drive the WE input of the PROM device.
compatibility is achieved between the latched and timer
devices by strobing the data, control, and addresses on
the leading edge of the Write Enable pulse for the latched
device and then by strobing the data on the trailing edge of
CHIP ENABLE for the timer device (see Figure 3). By
using this technique, the hardware interface is greatly
simplified.
The software part of an E2ROM interface is very simple,
but very important. A read operation for both latched and
timer PROM devices is accomplished by a straightforward issuance of a microprocessor Read command at a
particular address (see Figure 4). A write operation, however, involves a more complex process.
AO ·A 10
~
voo·va,
~
~ 7/Il!lf/&!l1#,z
VALID
VALID
CE\
The implementation of this timing can be accomplished in
either hardware or software. In hardware timing, a timer
can interrupt the processor at regular intervals, or at the
end of the desired write time (1wP). In software timing, the
processor simply counts down, waiting for the desired lwp.
For ease of general implementation, the given examples
utilize software timing (see Figure 5). The tradeoffs, however, between software and hardware timing comprise an
involved topic. The system designer must make this decision, considering such factors as processor throughput,
board space, and expense.
~.~!l&//,z
I
\
WE
Between initiation and termination of a write cycle, the
interface uses some timing mechanism to assure proper
write conditions to the PROM and to know when the
PROM is available for another read/write cycle. The duration of the timeout (1wP) depends upon the type of
PROM used. For all types, 1wP should fall between the
minimum and maximum specifications of all E2ROMs for
which the application is designed. The latched type of
device requires less write time than does the timer type
device.
I I
\~~\\\~\\~\\
I~
'V-
OE
After the cycle described by Figure 5 is complete, the
PROM device is available to be accessed for another
Figure 3. LatchedlTlmer Compatible EZROM Write
Cycle
ADDRESSES
VALID
ADDRESS
CE
OE
HIGHZ
OUTPUT
tACC
Notes:
1. OE' may be delayed up to tACC - foe after the falling edge of CE without impact on tACC'
2. taF is specified from OE or CE, whichever occurs first.
3. This parameter is periodically sampled.
Figure 4. EZROM Read Cycle
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Technology, Incorporated
8-52
WRITE ROUTINE
Read or Write command. Often, another read will be
performed in order to verify the written data. With the
solution proposed, this subsequent read cycle will have
normal timing, and all required write recovery parameters
will be satisfied.
WAIT ROUTINE
The general description provided above applies to most of
the processors shown in the specific examples below. For
more detailed information, the reader should refer to the
schematic, waveforms, and software that apply to a specific processor.
Microprocessor Interfaces
8085 Interface
The schematic for the 8085 interface to a timer or latched
PROM device is shown in Figure 6. This interface consists of one each of a 74LS02 and 74LS74 type package
and allows the system designer to use the WR signal from
the 8085 to initiate the write cycle to the PROM device.
The design permits use of either a timer OR a latched
PROM device with no change required to the controlling
software or hardware. The following discussion of the
Figure 5. Software Flowchart - E2ROM Write Cycle
r- A- I
I
SYSTEM RESET
1
WR
RESET
'.-
ClK
:~2
8085
IOiJl
I--<
E
DECODER
ADO·AD7
SEl~
.A
11
~
I
6
P
C
0
I
WE
-0 ~
L_Y_
1
6E
~
~2.2K
~
+5
CE
...
...
Ao·A7
",..
IIOO·I/Or
...
A8-~O
...
Figure 6. 8085/E2ROM Interface
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I
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74LS74
ID
I
CLKW "
I
1
E2ROM
L-
OCTAL
LATCH
ALE
I
-~.,.,. II
--= - --'
OxP-:::...-
>
A11 -A15 I
1
0
Y
I
I
p
C
I
RD
Lc
D
Technology, Incorporated
8-53
A8'~O
I
operation of the BOBS interface relies on the BOB5 timing
diagram summary for read and write cycles shown in
Figures 7a and 7b respectively.
The basic write operation waveforms for this interface are
shown in Figure B. The write cycle begins with the
addresses becoming valid and being decoded to drive
SELECT active low. in order to drive the CHIP ENABLE
(CE) active low atthe PROM device pin (selecting the desired device) (see
in Figure 6). An active low level on
WR from the BOBS (indicating a write cycle initiation) allows
the WRITE ENABLE latch of the interface to be clocked
Initiating a write cycle requires the software control routine
as charted in Figure 5. Should the reader desire a specific
example. the ZBO code (see Figure 12) is transportable to
the BOBS.
X
X. . . _____
AS -A15
I
\
\
X
ADDRESS
ADo-AD 7 __
ALE
I
\
l
C L K \ ' -_ _....I
®
J
--~IJJJ
....UJ.6..~'_I};.L'{.6.06'_li1;.LR'E.6.0'J/)JL........
L.L _D_A_T_A_IN_.....I). ...---~(..._y!'1/!llljl{I/,F{j/\
AD_D_R_E_SS
_ _ _.) ...
_
\~-----------------------~I
\'---_ _ _ _ _-.....11
RDIINTA
Figure 7a. 8085 Read TIming Summary
CLK!
As-A15
X
ADDRESS
ADO-AD 7
X
ADDRESS
ALEJ
\
1
1
\
1
X
X
X
DATA OUT
\
I
\
WR
1
Figure 7b. 8085 Write TIming Summary
SeeQ
\
Technology, Incorporated
8-54
_ __
to V1H (See @ in Figure 8). As indicated in Figure 8, this
read cycle does not produce valid data from the E2ROM.
This read cycle is used merely to terminate the write cycle.
~the nextfalling edge ofthe 8085 clock output (ClK) (see
@' Addresses, data, and control inputstothe latched type
PROM are latched in at the falling edge of WRITE
ENABLE (WE) - shown as@in Figure 8. For the timer
type PROM device, however, data is latched on the rising
in Figure 8.
edge of CHIP ENABl E (CE) - shown as
Note that CE is held active low for a relatively short period
of time, while WRITE ENABLE (WE) is held low for the
entire write time of the PROM device. In this manner, the
waveforms shown in Figure 3 are produced, providing
signals compatible with both the latched and timer type
devices.
The latched and timer devices respond identically in a read
cycle. The 8085 read cycle, shown in Figure 7a, produces
the read cycle waveforms shown in Figure 4.
©
lao Interface
A sample interface is shown for a Z80 processor (see
Figure 9). The timing diagram for write cycle waveforms at
this interface is also shown (see Figure 10). The basic
circuit is very similar to the 8085 interface, with the differhas data valid at both
ences based on the fact that the
edges of WR (see Figure 11). This simplified timing allows
a more simple interface. The ClK output from the proces-
To end the write cycle, the 8085 issues a Read command
to the PROM device. This read cycle enables the Write
ResetlatchwhichinturnpresetstheWRITE ENABl8atch
(shown in Figure 6). The preset to the WE latch brings WE
zao
WRITE CYCLE
INITIATION
WRITE CYCLE
TERMINATION
VALID
VALID
ClK
SEl
ClKW
CE
WE
®
®
©
@
*Ao-A,: ADDRESS SIGNALS MULTIPLEXED WITH DATA SIGNALS MUST BE DEMULTIPLEXED USING OCTAL LATCHES.
FIGURE 8. Timing Diagram - 8085/E2ROM Interface
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Technology, Incorporated
8-55
I
oriented system, this interface can be used with a Z80,
ZaOA, or ZaOB operating with no wait states at up to 6 MHz
clock frequency. The individual system designer, of
course, must check his own application to ensure satisfaction of applicable setup and hold requirements in the
specific system for which the application is intended.
sor is not necessary, and WR alone provides timing for the
write cycle initiation.
The operation of the circuit is otherwise very similar to the
8085 interface. After addresses are brought valid on the
address bus, they are decoded to drive SEL active low,
which drives CE active low at the PROM device pin (see
Figure 9, and@ in Figure 10). At the falling edge of WR
(when this device is selected), the WE latch is clocked,
bringing WE active low (see@in Figure 10). At this time,
the latched type device latches address, data, and control
signals, while the timer type device latches address and
control signals. At the falling edge of WR, the gating
circuitry brings CE high, latching data for the timer type
in Figure 10). Within a normal processor
part (see
cycle, a write cycle has been initiated with timing in
accordance with the general approach of Figure 3. Even
with additional buffers which may be common in a bus
The termination of a write cycle is very straightforward. As
shown in the Basic Operation section (see Figure 5), a
read operation to the E2ROM terminates the write cycle,
but does not provide valid data. For the interface operation
in write cycle termination, the reader should refer to Figure
10. The addresses are brought valid on the address bus,
and are decoded to drive SEL active low (see @inFigure
10). The gating circuitry, however, inhibits CE, and CE
remains at V1H• At the rising edge of RD, the flip-flop
receives a positive edge trigger, and clocks in the SEL sig-
©
r -A I
-,
ar-t-
P
D
SYSTEM RESET
r
.-
WR
~
;~2
Z80
AW A15
C
I
Y
I
AD
-< RESET
I
>
I
ReFRSH P------
,
I
I
1
I
~I
SelECT ~
--
j
74LS74
f.a
D
p
C
I
a
OE
I
WE
Q~
~ ~- ~
+5
2.21<
.... I
SEL
DECODER
CLKW
I
I
CE
I
-
-
-
J
E2 ROM
MReQ h - -
Do-D7
...
...
A
I<::
~
'"
...
...")
Ao-A10
Figure 9. Z80/E2ROM Interface
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Technology, Incorporated
8-56
1/°0-1/°7
Ao-A1o
WRITE CYCLE
TERMINATION
WRITE CYCLE
INITIATION
Figure 10. Timing Diagram - E2ROM Interface {Write Cycle}
nal to preset the WE latch. At this point, WE is brought high
(see@ in Figure 10), terminating the write cycle. For the
remainder of this processor bus cycle, CE becomes valid
for a short while. However, AD is no longer active low, and
no valid data is read in this bus cycle. There is no problem
with 1wR since the write recovery time occurs during the
remaining part of this bus cycle.
seeQ
Frequently, one may wish to read again from the device, in
order to verify data written. This read will be a normal read,
following the general waveforms of Figure 4. In a read operation, the interface drives CE active low to select the
device, and AD enables the output from the PROM
device.
Technology, Incorporated
8-57
I
J\
CLOCK
AO-A15
==><---------l; ;
VALID ADDRESS ;
;~-------_x=
\----~~ ~f__--____ff Jr------!
\~-----{IJf-----~I}~----~/
RD
READ
OPERATION
{
0 0-07
==>
WR
WRITE
OPERATION
{
0 0-0 7
------C(\-_____-{: :f_---DA-T-A-OU-T---------J>-
Figure 11. zao Read and Write Cycle
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Technology, Incorporated
8-58
LOC
EEWRZ80.1
OBJ CODE M STMT SOURCE STATEMENT
009B
0090
009E
00A1
3EFF
12
CDAEOO
1A
00A2
00A3
00A4
00A7
00A8
00A9
OOAA
OOAD
78
12
CDAEOO
1A
1A
B8
C2C800
C9
OOAE
78
OOAF
3202CO
00B2
00B4
00B5
00B7
00B8
OOBA
OOBB
OOBC
OOBF
OOCO
00C3
00C6
00C7
3E07
47
3E06
4F
3EOO
OB
B8
C2BAOO
B9
C2BAOO
3A02CO
47
C9
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
,-----------------------------------------Z80 EEROM Write routine.
Incorporates auto-erase and timing
in software.
Accepts: address to be written: Reg DE
Data
to be written: Reg B
Uses: A, B, 0, E Destroys: A
,-----------------------------------------EEWR: LD
LD
CALL
LD
A,OFFH
(DE), A
WaitTwp
A,
(DE)
LD
LD
CALL
LD
LD
CP
JP
RET
A,B
(DE),
A
WaitTwp
A,
(DE)
A,
(DE)
B
NZ,
FF for erasure.
BEGIN ERASE
END ERASE
Data to be written
BEGIN WRITE
Read to end Write
Read to Verify
Check Verification
ERR1
,-----------------------------Wait routine for EEROM Byte/ Erase
Uses: Registers A, B, C
Destroys: A, C
,-----------------------------WaitTwp:LD A, B
Store B reg in TMPl
LD
(TMP1), A
Set timing constant for Twp.
This 16-bit constant is loaded
into Registers BC, and depends
on the speed of the CPU clock.
LD
A, 07
LD
B, A
LD
A, 06
LD
C, A
The following loop performs the wait,
by decrementing BC until the 16-bit
number contained in BC equals zero.
LD
More: DEC
CP
JP
CP
JP
DUN: LD
LD
RET
Figure 12. Z80 E2ROM EraselWrlte Routine
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ASM 5.9
Technology, Incorporated
8-59
A, OOH
BC
B
NZ, More
C
NZ, More
A, (TMP1)
B,
A
Restore B Reg
I
8088 Interface
An example interface is shown between an 8088 (operating in minimum mode) and a 16K PROM (see Figure 14).
The reader may note that this is almost identical to the
8085 E2ROM interface (see Figure 6), with only minor differences. First, the NOR gates used cannot be a standard
TTL or lSTTl device, but must be a CMOS or other high
impedance input, so thatthe ClK signal is not loaded. The
ClK signal, as output by the 8284, is used as the clock
input to the 8088. The VOH level on this signal can fall
below specification as a result of a TTL load. A CMOS
NOR package, such as a 74C02 or similar device, elimi-
nates this problem. Since the 74lS74 operates from
bussed control and data lines, its requirements are not so
stringent, and a 74lS74 will work fine in most applications.
The operation of this circuit is almost identical to the operation of the 8085 interface, as a comparison of the timing
diagrams will show (see Figures 7b and 15). Because
these processors share similar bus timing, the signals
differ only in magnitudes of setup and hold times. All
required setup and hold times should be confirmed to the
satisfaction of the system designer.
CLK (8284 OUTPUT)
x=
x
101M, SSO
X
X
ALE
As -A 15 (FLOAT DURING INTA)
/
ADO-AD7
READ CYCLE
(NOTE 1)
(WR, INTA=VoH )
X
A1S-A 19
\
X
I
, ---I
}
ADo-AD7
FLOAT
{
DATA IN
\
ADO-AD7
WRITE CYCLE
NOTE 1
X
X
ADo-AD7
\
Figure 13. 808818086 Bus Timing - Minimum Mode
seeQ
S3-8 7
X
X
Technology, Incorporated
8-60
~
/
DATA OUT
X
/
~-l
10
1
I r
Ro
Lc
WR
RESET
'I~02
ClK
'\
FROM
8284
OUTPUT
8088
M/iO f---All -A 15
~
1
I
~'
OxP=:-
~I
SEl
I
DECODER
L-
_
-
OCTAL
lATCH
ALE
AOo-AD7
Pat--:-
II
SYSTEM RESET
I
C
I
I
74lS74
I
I
6
I 0
ClKW
I
L-
1
j
6E
P
C
I
a
WE
I
ap+-
-¥- _
J
~
~2.2K
+~
CE
E2 ROM
_..I
..
r
A
,
II
..
r
..
AS-Al0
An-A 7
IIOo-V~
AS- Al0
Figure 14 E2ROM Interface - 8088 (Minimum Mode)
I
eeeG
Technology, Incorporated
8-61
*Aa-A1,: ADDRESS SIGNALS MULTIPLEXED WITH STATUS AND DATA SIGNALS MUST BE DEMULTIPLEXED USING OCTAL
Figure 15. Timing Diagram - 8088/8086 E2ROM Interface
8086 Interface
A sample PROM interface shown for the 8086 (see Figure
16) compares very closely in layout and operation to that
for the 8088 (see Figure 14). The 8086 interface accounts
for the 16-bit 8086 data bus by latching both bytes of
address and implementing a pair of devices to read and
write an entire word at a time. PROM interface control
signals are identical to those for the 8088 interface (see
Figure 15).
duction, access time, and availability have made nonvolatile, memory suitable for more applications than ever
before. It is the purpose of this application note to contribute to this evolution in semiconductor memory by assisting
the system designer in the task of E2ROM implementation.
Armed with basic hardware and software examples of
working PROM applications, the designer can more
easily complete a feasible PROM design, using the flexible, cost-effective devices currently offered.
Conclusion
The development in PROM memory is continuing at an
ever increasing pace. Recent strides in PROM cost re-
seeG
Technology, Incorporated
8-62
SYSTEM RESET
Ro'
OE
OE
eLK
WE
...
FROM
OUTPUT
wiO
'--___-qCE
CE
8086
E2ROM
Ae-Al0
1======::>1
A16-AI9
ADe-ADI5
VO -V0
O
A
Ae- l0
7
ALE
AO-A7
Figure 16. E2ROM Interface - 8086 (Minimum Mode)
I
seeQ
Technology, Incorporated
8-63
8-64
Memory Products
Application Note
SOFTWARE DOWNLINE
LOAD USING SEEQ'S
CMOS EEPROMS
June 1987
I
seeQ
Technology I Incorporated
8-65
Software Downline Load Using
SEEQ's CMOS EEPROMS
Introduction
Non-volatile semiconductor memories have been commercially available for some time but these early devices
required multiple power supplies, high voltages and were
slow in programming. The RAM-like nature of the new
Electrically Erasable Read Only Memory (EEPROM)
greatly simplifies their use in all areas of microprocessor
based design. The elimination of complex timing and
voltage requirements makes it attractive to the designer to
incorporate in a design an EEPROM such as SEEQ's
28C64 or 28C256. These EEPROMs are self-supporting
and as simple to use as a static random access memory.
In addition, because of internal control over the write
cycle, they can plug into the standard socket of the 8K by
8 bit and 32K by 8 bit static RAM.
and EPROMs. It will operate with the signals normally
applied to a RAM, with the only restriction being the worstcase delay of 10ms after starting a write cycle before
accessing data.
These EEPROMs are true non-volatile memories. Nonvolatility is provided in the same way as EPROM. Unlike
EPROM they can be written to without prior ultra violet
light erasure. The bytewrite requirements are identical to
that of static RAM except that the EEPROM write cycle,
once initiated by normal static RAM timing takes as long
as 10ms. Once a write operation begins, the EEPROM is
self supporting freeing the processor and all external
circuitry for other tasks. This is accomplished through
latches, as internal self-timing circuit and wave shaping
circuitry. It also generates all necessary high-voltage programming pulses. These features fit well in a RAM environment where 5 volts is the only voltage level available.
The read timing cycle of the EEPROM is identical to that
of a standard EPROM, RAM or ROM.
Each byte can be written to any location withi n the address
space boundary ofthe currently active page. Because the
device ignores the row address input after the first byte
write, an attempt to load data bytes beyond this bou ndary
will not affect data elsewhere in the EEPROM array, but
will cause the data to be written to the page buffer at a
location determined by the lower 6 bits of the address
bytes. The procedure to transfer a data byte from the bus
to the EEPROM array consists of three steps: the load
cycle, the write cycle and the optional data polling.
Device Operation
The internal circuitry of the 28C64 and 28C256 EEPROM
does not write entered data bytes immediately to the array
of memory cells. The bytes first accumulate in a 64 byte
page buffer and subsequently transfer to a specific "page"
of the array in an independently timed manner. As a
result, up to 64 bytes can be written within one 10 ms write
cycle to the EEPROM array.
The load cycle
Th~ load .cycle is basically a byte-load window (tBlC)
dUring which a data byte can be entered into a 64 byte
page buffer before the write cycle starts. If an additional
data byte is entered within the byte-load window the initial
window timer is retriggered and the internal write cycle is
prevented from commencing. Taking in consideration the
lwp min and tBlC min specifications, it will require only 22.4
(..Is to enter a string of 64 bytes into the page buffer. The
latest high to low transition of either the Chip Enable signal
(CE) or Write Enable signal (WE) latches the address bits
into the address latches. It also resets the internal page
load timer. In order to ensure proper latching and write
cycle initiation the WE and the CE signals must meet twp
min. Upon the earliest low to high transition of either CE
or WE the EEPROM latches the data byte, places it in the
page buffer and starts the internal page load timer tBlC'
The early EEPROMs had small storage capability. For
this reason, they were not seriously considered as main
program storage medium. Therefore, most of the initial
EEPROM applications used the EEPROM for limited data
storage, such as calibration parameters and system
configuration. The use of the EEPROM for main program
storage was obviously reserved for those who could
afford the cost and the board space required. The availability of the 28C256 EEPROM along with the reduction in
cost of lower density devices has created new interest
among design engineers. The EEPROM is now considered a cost effective approach to non-volatile main program storage, either by itself or in combination with ROMs
seeQ
Technology, Incorporated
8-66
The write cycle
Software examples
If no data byte has been loaded within the byte-load
window the EEPROM terminates its load cycle and initiates its write cycle. During this write cycle, which takes
maximum 10 ms, additional load attempts are ignored.
The EEPROM, during these 10 ms, is not on the bus and
requires no processor service.
Processors with MOVE STRING or LOOP/ REPEAT instructions might be able to load a group of data bytes
faster than the EEPROM allows. In that case the data
transfer rate of the processor is in conflict with the minimum byte-load-time specification of that EEPROM. The
solution to this problem is to emulate the MOVE STRING
instruction in assembly code. This approach might cause
conflict with the maximum byte-load-time specification.
The timing diagram on the 28C64 and 28C256 data sheet
shows that itcan complete a byte load cycle within 170 ns.
Example 1, the talC min specification
i.e. (tAS + lwP + t OH)
= 20 + 150 + 0 = 170 ns.
The MOVE BLOCK instruction of the 8086 processor
moves data bytes so rapidly that it conflicts with the t Ble
min of the EEPROM specification from several manufacturers. The following code instructions illustrate this.
The remaining 9.99983 ms ofthe 10 mswrite cycle can be
used to execute other system tasks. The write cycle is
illustrated in Figure 1.
DESTADD Eau
SRADD
Eau
DATA polling
During the write cycle, the data bus of the EEPROM
exhibits high impedance. The write cycle ends when the
internal operations are completed, at which time the
EEPROM is immediately available for access. A read
command will then present true data at the output port.
The maximum write cycle time is 10 ms, but typically it
takes less time. The 28C64 and 28C256 have a built-in
software feature to take advantage of this shorter write
cycle.
-
-
-
-
-
-
-
-
-
--
-
-
-
MOV ex, NDLOAD
REP MOVS DESTADD, SRSADD
code instructions to
cause registers to point
to EEPROM address and
data source address.
; load page size
; do page load till ex=o
RET
When the EEPROM, while still in its write cycle, is read
anywhere in its address space, the software feature will
present at the EEPROM data bus the ones-complement
of the data byte at the last address loaded. For example,
data byte 10001101 is read as 01110010. With this
feature the end of the write cycle can be detected and data
loading can immediately be resumed. As a result the
processor waiti ng time is reduced. This polling procedure
is illustrated in Figure 2.
The REP MOVS DESTADD, SRSADD instruction requires 9 clock periods to initiate the byte-move process
and 17 clock periods to move each consecutive byte.
Consequently, the 8086 driven by a 6 MHz clock can
move a byte in2.83IJs. This isin conflict with the minimum
value for the t Ble specification ofthe 64K EEPROM made
by manufacturers #1,#2, #3 and #4.
Any solution to this problem would reduce the data
transfer rate. SEEO EEPROMs are much faster and, as
the table below illustrates, accommodate these data rates
easily.
Design Considerations
The page mode feature can reduce the overall write-time
by a factor equal to the page size. Unfortunately, page
sizes as well as timing specifications for EEPROMs vary
significantly among manufacturers and may not always
match the timing requirements of a particular processor.
For instance, a tight byte-load window specification, i.e.
t Ble min to t Ble max, might not take full advantage of the
page load feature. Consequently, the maximum possible
data transfer rate is not obtained. To illustrate this, the
specifications of the most significant EEPROM parameters, as given by different manufacturers, are shown in
Figure3. The byte-Ioadwindowspecificationofthe SEEO
28C64 and 28C256 EEPROMs accommodates a large
number of piOcessors.
seeQ
-
ES:BYTE PTR [01]
DS:BYTE PTR [SI]
PROCESSOR
CLOCK RATE
80186
8 MHz
1.0 IJslbyte
80286
8MHz
O.5lJslbyte
DATA RATE
Example 2, the talC max specification
Since the 8051 processor does not have BLOCK MOVE
instructions it must emulate a BLOCK MOVE with 13
instructions, each requiring 24 clock periods.
Technology, Incorporated
8-67
I
OPTIONAL PATH
NO
WRITE 1 TO 64
BYTES
STORE LAST WRITE
ADDRESS, DATA
WRITE CYCLE COMPLETE
EEPROM AVAILABLE FOR ACCESS
READ
LAST WRITE ~-------,
ADDRESS
Figure 1. Page Mode EEPROM Write Cycle
DATA POLLING
LOOP
(OPTION: CAN PERFORM
OTHER TASKS IN LOOP)
NOT EQUAL
EEPROM
AVAILABLE
FOR ACCESS
Figure 2. Page Mode Write DATA Polling
seeQ
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8-68
Specification Comparison Table for
64K EEPROM
MANUFACTURER
talc MIN.
talc MAX.
200 ns
200 us
#1
3 us
20 us
#2
3 us
#3
#4
SEEO*
tplW MIN.
infinite
PAGE SIZE
64 bytes
150 us max.
16 bytes
100 us
infinite
32 bytes
30 us
100 us
infinite
32 bytes
100 us
500 us
infinite
32 bytes
Specification Comparison Table for
256K EEPROM
MANUFACTURER
talc MAX.
200 ns
200 us
infinite
64 bytes
2 us
100 us
infinite
64 bytes
#1
tplw MIN.
PAGE SIZE
talc MIN.
SEEO*
*Times are shown for military temperature range devices.
Figure 3.
At a clock cycle rate of 12 MHz the data rate is 26 IJs per
byte. This conflicts with the tBlC max specification of
manufacturer #1. Other examples, which violate the
specification of manufacturer #1 are shown in the table
below.
PROCESSOR
CLOCK RATE
6805
4 MHz
20 IJslbyte
6801
4 MHz
36IJslbyte
EEPROM Download
The cost of updating software contained in ROM or
EPROM in the field is very high. EEPROMs allow the
system software to be changed remotely, either through
a termi nal or a modem link to a main computer. Therefore,
the key advantage of the EEPROM is reduced service
cost for it allows update of software contained in nonvolatile memory, without removing the memory device
from the system. These remote software updates are
very attractive for updating system software, self-calibration or changing the system configuration or capabilities.
Data load rates in excess of 50,000 bitslsec are possible
using the page mode feature of SEEO's 28C256 and
28C64.
DATA RATE
Example 3, the \.lW max specification
EEPROMS from some manufacturers require that all
bytes be loaded into the page within a specified maximum
time (tplW)' For example, if a processor has a data load
rate of 10 I-Is per byte then this value complies with the tBlC
specifications of an EEPROM from manufacturer #1. The
tplW specification of the same EEPROM is 150 IJs and
therefore, the processor can only load 150/10=15 bytes
before the write cycle starts. As a result, the page buffer
capacity is notfully utilized, and ittakes longer to program
the EEPROM.
EEPROM and resident PROM configuration
In the case of an EEPROM and processor resident
bootstrap PROM combination, the actual download routine resides in the PROM as shown in Figure 4. The
processor can now fetch instructions from the PROM
during the EEPROM write cycle.
All EEPROM configuration
SEEO does not specify a limitfortpLW' The total page-load
window time is infinitely long assuming the time between
byte loads meets tBlC max.
seeQ
If only EEPROM is used for the program storage and the
code to be modified is on a different EEPROM than the
one from which the processor is executing then a situation
Technology, Incorporated
8-69
I
PROM
EEPROM
DOWNLOAD ROUTINE
PROGRAM
TO BE
MODIFIED
-------OTHER ROUTINES
Figure 4.
RAM
EEPROM
SYSTEM STACK
DOWNLOAD ROUTINE
- - - -- - -
-----PROGRAM TO BE
DATA STORE
MODIFIED
Figure 5.
RAM
EEPROM
SYSTEM STACK
DOWNLOAD ROUTINE
-----DATA STORE
-------
-----PROGRAM TO BE
MODIFIED
DOWNLOAD ROUTINE
Figure 6.
RAM
EEPROM
SYSTEM STACK
DOWNLOAD ROUTINE
- - - -- - -
------NEW VERSION OF
DATA STORE
PROGRAM
Figure 7.
eeeG
Technology, Incorporated
8-70
Applications
si milar to figure 4 exists. A more general approach which
allows any EEPROM in the system to be written is the
EEPROM and RAM configuration.
EEPROM is the preferred memory device when variable
data storage is required. There are three important characteristics associated with EEPROM
EEPROM and RAM configuration
In the case of the EEPROM and RAM configuration, the
following approach is required. The procedure starts with
the memory contents as shown in Figure 5.
1. Data contained within the EEPROM is retained
when power is removed.
2. The EEPROM can store sufficient data to accom
modate large lookup tables or computer programs.
3. Data in the EEPROM is easily alterable, remotely
or locally.
In the first step both the download routine and the system
program are stored in EEPROM. Once the system is
instructed that the new version of the program is to be
downloaded, the system copies the download routine
from EEPROM to the RAM. At this point, the memory
contents are as shown in Figure 6.
The list below illustrates that EEPROM applications are
as various as they are numerous.
•
•
•
•
The processor then jumps to the RAM and executes the
download routine and loads the new main program in the
EEPROM. Next, the processor jumps to the new main
program in EEPROM to continue its normal task, leaving
the RAM available for other services. Figure 7 shows the
final contents of the memory devices.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Data lookup tables.
Smart cards
Electronic toys
Terminal configuration (baud rate, data format,
parity)
Measurement instruments
Digital positioning machinery
Boot-up storage
Calibration data
Traffic control equipment
Telemetry
Navigational reference system
Music synthesizers
Signal synthesizers
Radio and TV program control
Disc Drive Servo
Robotics
Data encryption
Self-modifying code.
I
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Technology, Incorporated
8-71
8-72
Memory Products
Application Note
POWER-UP/DOWN
WITHSEEQ'S
EEPROM
I
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Technology I Incorporated
8-73
Power-Up/Down with
SEEQ's EEPROM
Introduction
Electrically Erasable programmable Read-Only Memories
(PROMs) are semiconductor devices offering high-density non-volatile random-access data storage. A read operation with P devices as similar to that for an EPROM or
static RAM. The write operation, however, requires a
millisecond or longer. Previous generations of PROMs
required high-voltage wave-shaped pulses during a write
operation. With such strict requirements for the write
control signal, the typical P system designer was careful
to ensure the correct level of this signal under all conditions, including power-related situations when the system
is turned off or on. Only recently has the convenience of
PROM been available in devices which can be written
with simple TTL-compatible signals. SEEQ offers such
devices in several densities.
included on-board the PROMs, and is described below.
At the system designer's option, system reliability may be
enhanced by absolute prevention of false writes.
The purpose of this application note is to provide the
system designer with a simple method by which to prevent
false writes during power-up and power-down situations.
A simple circuit is shown (see Figure 1), its operation is
explained, and some useful design considerations are
outlined.
With the advent of five-volt PROMs, non-volatile memory
has shown far greater flexibility and ease of implementation. The ease of use allowed by TTL interfaces cannot
release the designer from the normal constraint of ensuring reliable operation during power on/off situations. What
signals should the interface devices provide when the
system is turned off or on (or otherwise loses power)?
Under conditions of extreme or repeated brownouts?
During times such as these, when Vee may be outside of
specified limits for correct operation of support logic, this
support logic can supply signals to the PROM which initiate an undesired write cycle. This causes an inadvertent
write to a location in the PROM. In order to ensure system
reliability in such situations, it is very important to ensure
that inputs (during power up/down conditions) from support devices do not cause inadvertent writes to an E2ROM
device. A certain amount of the required protection is
OUTPUT
63.4Kn (1 % Metal Film)
71.5 Kn (1 % Metal Film)
51 Kn
1.5 Mn (1 % Metal Film)
10 Kn
LT1004 - 2.5
Figure 1. E2ROM Write-Protection Circuit
seeQ
Technology, Incorporated
8-74
already low, this will be interpreted as a continuous low on
WE and will not initiate a write cycle, because a falling
edge on WE is required AFTER Vee rises. Inadvertent
writes are prevented when Vee is less than 3.0 V (see
Table 2); all that is left to external circuitry is writeprotection for Vee between levels of 3.0 V (the lowest Vee
level at which the device can write) and the Vee level at
which the support logic issues valid signals.
The ideas and designs presented in this note are meant to
serve as a starting point for the designer, to assist him in
accomplishing his goal. The solution given, however, is
not the only approach. There are many ways to ensure
desired signals to the PROM during power up/down
conditions. The designer is encouraged to tailor his
solution to the specified requirements of his application.
Using E2 ROM's Built-In Protection
External Write-Protection Circuitry
In SEEQ's PROMs, protection against false writes has
been simplified by 3 built-in protection mechanisms on the
chip. This protection logic (transparent to the user) does
not make writing any less convenient. Table 1 shows the
conditions which are required in order to guarantee initiation of a write cycle Vee must be within specified limits, CE
must be active low, and OE must be V1H, T es (50 ns) before
the falling edge of WE. Due to PROM's protection logic,
under certain other conditions, there are modes in which
writing is inhibited (see Table 2). First, if Vee is less than
3.0 V, writing is prevented, regardless of the other input
signals. Second, OUTPUT ENABLE (OE) at V1L (satisfying TeslJ!lhibits writing. Third, in order to inhibit a write
cycle, WE or CE can be held at V1H •
With the protection logic on board the PROMs, the part
can be protected against inadvertent writes in any of
several ways. The system designer can ensure that CE is
high during power-up and power-down. Alternately, one
can ensure that WE never has a falling edge during powerup or power-down. For example, one could ensure that
WE stays at V1L on power-up until a latch is reset, releasing
a pull-down. This would ensure write prevention.
Another manner of write protection has been to bring OE
low during power-up and power-down. This inhibits writing
(see Table 2), often allows the simplest realization, and is
the general path chosen in this application note. Yet the
timing and levels of signals provided must be scrutinized
here, as well.
Several failure modes are prevented by protection logic
described above. For example, if Vee comes up with WE
Merely inserting a pull-up on OE will tend to pull OE down
when Vee is low, but may not force a valid V 1L level.
Inserting a low forward voltage drop diode between the
system-wide RESET signal and the PROM's OE signal
may work, but depends on the timing of Vee and RESET.
Table 1. Conditions Required to Guarantee
Write-Cycle Initiation In E2ROMs
WE
CE
OE
Vee
All
Other
Pins
V1L
V1H
4.5-5.5 V
X
The specific form of protection against inadvertent write
cycles chosen for this application note, one with more
certainly of protecting against inadvertent writes, is to force
either OE low (V1L) or CE High (V1H) during power-up and
power-down. Figure 1 shows a circuit that can be used to
fulfill this requirement.
Notes:
1. Active levels shown in above table require T s set-up time of
50 ns (see E2ROMs data sheet).
2. X = TIL Don't Care.
Table 2. Conditions Required to Inhibit Write-Cycle Initiation in E2ROMs
WE
CE
OE
Vee
All Other Pins
Inhibition Mode 1
V1H
X
X
X
X
Inhibition Mode 2
X
V1H
X
X
X
Inhibition Mode 3
X
X
V1L
X
X
Inhibition Mode 4
X
X
X
Under 3.0 V
X
Notes:
1. Active levels shown in above table require T s set-up time of 50 ns (see E2ROMs data sheet).
2. X = TIL Don't Care.
seeG
Technology, Incorporated
8-75
I
The circuit shown in Figure 1 provides a proper output
signal (comparator's output) to prevent false write. During
power-up, as is shown in Figure 2A, the output of the comparator is kept low from the time that Vee is 2.5 V until it
reaches 4.8 volts. The output switches to V1H when Vee
goes above 4.8 volts. During power-down, however as is
shown in Figure 29, the comparator's output is forced low
as soon as Vee falls below 4.6 V and is kept low until Vee
goes below 2.5 volts. Circuit functionality is not guaranteed below this point.
,
,
OUTPUT
To prevent inadvertent writes, either OE or CE pin can be
used. The first method is by forcing and keeping OE low
(V1L) when Vee is below 4.5 volts. This can be done, as is
shown in figure 3A, by connecting comparator's output directlyto E2ROM's OE pin. As soon as Vee falls below 4.6V,
the OE is forced low preventing any internal write initiation.
This pin is kept low (valid) until Vee goes below 2.5 volts.
Internal protection circuitry protects the part beyond this
point (activated when Vee falls below 3.0 V).
\\~
:/777
,
\\,\,
,
1771/,
The second method of protecting the part against inadvertent write is by forcing and keeping CE high when Vee is
below 4.5 and above 2.5 volts. This can be done, as is
shown in Figure 39, by NAND gating (74HCTOO) the comparator's output with a CS signal. The output of the NAN 0
gate, which is connected to PROM's CE pin, is controlled
by the CS input when Vee is above 4.6 volts. The other
input controls NAND gate's output when Vee is below 4.6
V (above 2.5V). Keep in mind that the CS line must be a
high true signal and the NAND gate should be a high speed
CMOS device.
'/777
I
,
'\\\\
,
,
Figure 2A. Timing Dlagram-Power-Up Using
Either CE or OE Protection
Either method described above can be used for protection
against inadvertent writes. System designers have to
determine their need first and based upon that, select one
of the above circuits or one of their own.
,
,
2.5V
Circuit Operation
OUTPUT
The circuit shown in Figure 1 is designed to provide a high
(V1H ) output (comparator's output) when Vee is above 4.8
volts and a low (V1L) output when Vee falls below 4.6 V
(above 2.5 V). This is done by using a comparator (LM193
available from National Semiconductor), a temperature
compensated voltage reference device (LT1 004MH·2.5
available from Linear Technology) and a few resistors.
The circuit has been designed to operate over military
temperature range.
'
:/777
,
'/777
,
I
111'1,
As it can be seen in Figure 1, the negative input of the
comparator is connected to ground through a temperature
compensated voltage reference device (0 1) and to Vee
through a resistor (R3). As long as Vee is below 2.5 V, 0 1
is not conducting (no currentflowthrough it). However, as
soon as Vee goes above 2.5 V and stays there, 0 1
conducts providing a 2.5 V reference voltage at the negative input (no current flow into negative input). The resister
(R3) is used to limit the amount of current through 0 1 •
seeQ
--r-\'f""""'\\M~
'\\\\
,
Figure 28. Timing Dlagram-Power-Down
Using Either CE" or OE Protection
Technology, Incorporated
8-76
RS
74 HCTOO
cs----------------------------,
TO E2ROM 's
OEPIN
+5V
TOE2ROM's
OEPIN
Figure 3A. OE Protection Circuit
Figure 3B. OE Protection Circuit
The positive input on the other hand is, connected to a
voltage divider (R1 & R2) as well as the output (through R4 ),
The voltage at this input forces the output to go either high
(V1H ) or low (V1L). When Vee is below 4.6 V, the voltage
divider causes this input to be below reference voltage with
respect to ground forcing the output low. On the other
hand, when Vee goes above 4.8 V, the positive input
voltage goes above reference voltage forcing the output
high. The output stays high as long as Vee is above 4.8
volts. The feedback resister (R4) is used to enforce output
voltage on the positive input while Rs is used as a pull-up
resister. Proper device selection, as is recommended in
this Application Note, can insure correct operation of the
circuit over military temperature range.
ommendedto use 1% metal film resistor for R1 , R2 and R4 •
The other two can be carbon film resistors.
If CE pin is used for protection, the comparator's output
must be NAND gated with a CS signal. Proper gate output
is guaranteed if a high speed CMOS gate is used. Also,
designers have to make sure that the CS input is a high true
signal. However, no NAND gate is needed if OE pin is used
to protectthe part againstfalse write. Comparator's output
can be connected to OE (through Rs)' A choice of values
for Rs Resistor depends on OE driver (RD line). The RS
resistor is used to insure a low OE input when Vee is below
4.6 V (comparator's output is low). If open collector driver
is used, the pull-up resistor can replace Rs'
System Consideration
Conclusion
As was mentioned above, correct circuit operation requires proper device selection. The comparator and
temperature compensated voltage reference device (0 1 )
selections are critical. You have to be sure that 0 1 provides
2.5 V drop across allowing half a volt safety margin
between external protection circuit and the internal one
(3.0 V internal power protection). It is suggested to use
devices recommended in this Application Note. Other
circuit elements that can influence circuit operation are the
resistors. For correct operation over temperature, it is rec-
It has always been important for a system designer to
ensure reliability as his system is turned off and on.
Currently, the importance of this area of design is increasing. As the usage of five-volt E2ROMs increases, applications are expanding into environments where Vee may be
undependable, power glitches may exist, and in general a
system must be more fault-tolerant. With the circuit
contained in this application note, the designer can more
easily ensure that his system meets applicable specifications and is able to utilize the convenience of E2ROMs.
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Technology, Incorporated
8-77
I
8-78
Memory Products
Application Note
POWER FAIL PROTECTION
WITH SEEQ'S CMOS
EEPROMS
October 1987
I
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Technology, Incorporated
8-79
/
Power Fail Protection With SEEQ's
CMOS EEPROMS
Since 1982, SEEO Technology Inc. has been producing
EEPROMs that can be programmed in-circuit using only a
5 volt supply. All of the high voltages necessary for programming are generated by an on-chip charge pump.
Therefore, the external signals required to initiate a write
need only be at TTL levels. Unfortunately, these external
signals can do unpredictable things during power-up or
power-down. If during these power transitions (or during
a brown-out), the signals needed to initiate a write to the
EEPROM are generated, the system's non-volatile memory may be corrupted.
3.
Obviously, software write-protection has some limitations
which can only be overcome through the use of external
hardware.
HARDWARE WRITE-PROTECTION
Hardware write-protection is just that; the use of hardware
to eliminate false writes. Much of this circuitry is contained
onboard the EEPROM itself. Absolute protection against
false writes is thus accomplished with the addition of some
external hardware (which we have seen is needed even if
software write-protection is used). An additional benefit of
hardware write-protect is that it is totally transparent to the
system's software designer.
Several methods of insuring the integrity of a system's
data have been proposed, and these methods are often
referred to as ''Write protection". The two major classifications of write-protection are "software write-protection"
and "hardware write-protection".
SOFTWARE WRITE-PROTECTION
For these reasons, the remainder of this article will
address the various aspects of hardware protection.
Software write-protection involves the use of decoders
and latches which need to be written to by the system
processor in a specific manner. This "unlock code" sequence must be executed before the EEPROM's control
signals can become valid, allowing a write into the
EEPROM. These latches and decoders can be on the
EEPROM die itself or part of the external circuitry.
SEEQ'S ON-CHIP WRITE-PROTECT
CIRCUITRY
A. Bandgap Reference Voltage
Internal to all of SEEO's CMOS EEPROMS is a bandgap
voltage level detector.
This detector disables the
EEPROM whenever Vee is below the WRITE INHIBIT
VOLTAGE, VW1 ' Characterization data (see figure 1) has
shown VWI to be between 3.85 volts and 4.25 volts over the
entire military temperature range. When Vee is below VWI'
two things will be true:
The idea is that during power-ups and power-downs the
chances of the proper sequence'of signals needed to
program the EE being generated randomly are very slim.
While this is true, there are some limitations to this technique which need to be discussed:
1.
2.
Since the unlock code used must be resident somewhere in the system's software, a "runaway" processor could easily execute the unlock sequence, causing false writes. The only way to preventthis from happening during power-up or power-down isby generating a system reset signal via a low voltage detector.
How to prevent this during "normal" processor operations is beyond the scope of this article.
What happens if power fails after the system has executed a legitimate unlock sequence to perform a desired write? In this case, the EEPROM is vulnerable
to false writes on power down unless some form of low
voltage detector disables the EEPROM.
seeQ
If power fails during the EEPROM's internal programming cycle (while new data is actually being written
into the memory array), data may be corrupted.
Technology, Incorporated
8-80
1.
The internal charge pump is disabled, preventing the
high voltages which are necessary for programming
the EEPROM from being generated. It is impossible
for any data to be altered when the charge pump is
disabled.
2.
The EEPROM's internal oscillator is disabled, forcing
the device into a low-power standby mode. This
feature results in an orderly shutdown of the device
when the system's power fails or is turned off. Also,
this feature will save power in an all CMOS system
where a low Vee standby mode is used.
FAILURE IMMINENT (PFI) signal can be generated at
least 10 ms before Vee fails.
Since SEEQ's EEPROMs are guaranteed to be disabled
when Vee is below 3.85 volts, but TTL signals are only valid
when Vee is above 4.5 volts, some external circuitry must
disable the EEPROM (and probably hold the system in
reset) while Vee is between 3.85 volts and 4.5 volts. In a
CMOS system, logic signals are valid with Vee as low as
3.0 volts, which is well below the Vwt threshold of the
EEPROM. It would seem then that an external voltage
detector might not be needed in a CMOS system. We will
see that this assumption may not be valid.
This PFI signal can then be used to warn the system
processor that there is time for only one more programming cycle before shut-down. Up to 64 bytes of data can
be stored in one 10 ms programming cycle and return to its
standby mode before Vee fails. The final store is accomplished, and all data is intact.
Now we must turn our attention to disabling the EEPROM
when V ce is between 3.8 volts and 4.5 volts.
On power-up, this assumption would be valid because the
EEPROM would be idle and disabled until well after the
system's bus had settled down into valid logic levels.
Unfortunately, if power is lost while the EEPROM is in the
midst of an internal programming cycle, the data being
programmed may be stored incorrectly.
B. Multiple Control Pins
There are three control signals on SEEQ's EEPROMs,
and each signal must be at the proper logic level for a write
cycle to begin. Therefore, writes can be inhibited if any of
the following input conditions are met:
Of course, with the orderly shutdown feature of SEEQ's
EEPROMs, and because the page address is latched into
the device upon the first falling edge of WE, only those
locations being changed when power was lost might be
corrupted. All other locations will remain unchanged.
Also, if the system processor was doing a page load on
SEEQ's EEPROMs and Vee was to drop below 3.85 volts
before the TaLC Timer timed out (see data sheet), then that
programming cycle would never start and no locations
would be changed.
WE
OE
Vee
WRITE MODE
V IH
X
V IH
X
X
X
X
INHIBITED
X
X
X
VII
X
INHIBITED
CE
X
X
X BELOWVWl
INHIBITED
INHIBITED
1. 3.8 < VWI < 4.25
2. X - Don't Care
3. All other inputs are don't care
4. Set-up and hold times on transition are in the specific data
sheets for each part.
Fortunately, there is a way to eliminate the possibility of
having the EEPROM in an internal programming cycle,
while allowing one final data store, when Vee fails. This is
accomplished by detecting a drop in the raw DC or AC
voltage used to power the system (see Figure 2). As long
as CF is large enough, which is load dependent, a POWER
By using an HCMOS logic gate and a RESET signal (see
figure 2) we can force anyone of the control lines to a
4.25
4.20
w
~
~
!:::
ED
:E
~
4.15
4.10
w
4.00
~
3.95
~
I
4.05
3.90
3.85
MINIMUM
AVERAGE
MIN. AVERAGE AND MAXIMUM VWI
Figure 1. Write Inhibit Voltage - 28C256 and 28C64
seeQ
Technology, Incorporated
8-81
MAXIMUM
RAW DC
+5 VOLT
Vee
----.----U.--.--;REGU~TORr-~.---------------------~~-------------.
~F .....-.....--....
Vee
EEPROM
Vee
)l.PNMI
HCOO
WE
RESET
RESET
Figure 2.
known state to disable the EEPROM when Vee is below 4.5
volts. We could also use the RESET signal to remove
power from the device, which will accomplish the same
thing. An HCMOS gate should be used since it will drive
the control line to either power rail even with Vee as low as
3.0 volts.
any false writes from occuring during power-up. However,
the RESET line will only prevent false writes during powerdown if the EEPROM was not already in an internal
programming cycle. If this does happen, only those bytes
which were being reprogrammed could possibly be corrupted.
Why must we have a separate RESET line? Why not use
the PFlline to disable the EEPROM? Well, that would
allow the EEPROMtimetofinish an internal programming
cycle before Vee fails, but there are several problems with
this approach.
The PFI signal will prevent this from happening, as well as
allowing the system enough time to save any vital data
priorto power failure. By making CF large enough (which
is load dependent), PFI will warn the pP 10 ms before Vee
fails. After being warnea, the pP can initiate one more
programming cycle. The EEPROM will then have enough
timeto complete its internal programming cycle before it is
disabled.
First, during power-up, the unregulated voltage could be
above threshold (enabling the EEPROM) some time before Vee has reached 4.5 volts. This could lead to false
writes. Second, if the EEPROM is disabled as soon as an
imminent power failure is detected, the system would be
unable to initiate any final programming cycles prior to
shut-down. This could lead to the loss of valuable data.
In conclusion, the possibility of false writes can be totally
eliminated ifthe system makes use of a RESET signal and
a PFI signal in combination with SEEQ's on-board writeprotection circuitry.
From this, we can see that the EEPROM disable signal
must be generated from a low voltage detector on the Vee
line. This disable signal would be the system's normal
RESET line (see figure 2).
A MONOLITHIC SOLUTION
(SEE FIGU RE 3)
An alternative to using op-amps and discrete components
to produce the PFI and RESET signals can be seen in
Figure 3. This circuit makes use of a monolithic supply
voltage supervisor family from TEXAS INSTRUMENTS.
These devices are useful to detect power-up, powerdown, and brown-outs. In addition, CT can be chosen to
determine how long the RESET signals will remain active
after Vee is above threshold, which guarantees proper
EXTERNAL WRITE-PROTECT
CIRCUITRY (SEE FIGURE 2)
In this circuit, the RESET signal will disable the EEPROM
and hold the pP in RESET any time Vee is below 4.5 volts
(or whatever other threshold is chosen). This will prevent
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Technology, Incorporated
8-82
system initialization on power-up. The readershould refer
to T.I's data sheet for details.
In other words, if I, is 550 rnA, then CF must be 1000 J.lF for
proper operation of the PFI protection.
In this example, a TL7715 is used to produce PFI while a
TL7705 is used to generate the RESET signal. This
arrangement ensures that the EEPROM is disabled anytime Vee is below 4.5 volts, and the PFI warning is issued
anytime the raw DC powering the system falls below 13.2
volts. (See TL7705 and TL7715 data sheets for detailS).
CONCLUSION
Designers must be careful to avoid false writes to a
system's EEPROM during power-up, power-down, and
brown-outs. This is especially true in CMOS systems
where "brown-outs" are often entered purposely to
achieve low Vcc/low power standby states.
Lets assume that:
We have seen that to completely eliminate the possibility
of false writes, the system must monitor the voltages on
both sides of the Vee regulator This is true whether
software or hardware write-protection is used.
a. power is lost abruptly
b. VF of D1 is 0.7 volts
c. The drop-out voltage of the regulator is 2.0 volts
SEEQ Technology has incorporated all of the on-chip
hardware write-protection needed to design a trouble-free
system using EEPROMS. In addition, this form of writeprotection is completely transparent to the system, making
Then we can see that the voltage across CF must take at
least 10 ms to drop from 12.5 volts to 7.0 volts at the given
load, I,. (13.2 - 0.7= 12.5 and 5.0 + 2.0 = 7.0). Since I, =
CF dv/dt and dv = 5.5 volts, dt = 10ms, we have this
relationship: I, = 550 C F•
seeQ
the software interface more convenient.
Technology, Incorporated
8-83
8-84
Memory Products
Application Note
EEPROM AS A
SUBSTITUTE FOR
BUBBLE MEMORY
October 1987
I
seeQ
Technology I Incorporated
8-85
sixteen decoder such as the 74LS154. In comparison, that
1.25 cubic inch bubble pack required a series of controllers, coil drivers, current drivers, etc. In the final analysis,
semiconductor EEPROM memory will occupy a fraction of
the space of bubble memories.
As more systems designers are dropping bubbles,
EEPROM-based designs are rapidly increasing. In the
early to mid 80's, we were told bubbles would take over
mass storage designs. Surely bubbles were the design of
the future for core memories and even to replace disc
memories. As many of these dreams fade, let us consider
some of the pro's and con's of each technology.
Access time is the time from the issuance of the valid
address or name of a file, datablock, word or byte until the
first full size segment of data is available. A full size
segment would be the first bit of a serial data stream or the
first full byte or word in a parallel data bank. Common 4
megabit bubble memories today have average random
access times on the order of 50 to 90 milliseconds. Some
of the new small size modules have average access times
less than 10ms, but specify maximums above 500ms.
SEEO Technology's 28C256 has a maximum access time
of 200 nanoseconds. Comparing the two technologies,
bubble memory's average access time is 250,000 times
longer than the EEPROMs worst case; the EEPROMs
could deliver 250,000 bytes of data while the bubble
memory is accessing the first bit.
Common design considerations include density, power
consumption, weight, access time, data rate, and environmental susceptability.
Density is certainly one issue that gets a lot of discussion.
Commonly available 4 megabit bubble packs are approximately 1.25 cubic inches for the basic block. SEEO
Technology's 256K PLCC package has a volume of approximately .0125 cubic inches or 1% ofthe volume of the
bubble pack. Therefore, an equivalent 4 megabit EE
memory using 16 256Kbit devices has less than 20%of the
volume of the bubble memory. Mounting of either device
was not taken into consideration; neither was the volume
of the required support chips. The EEPROMs would take
more area mounted than was implied strictly with a volume
specification. Spacing between packages could increase
total volume, although the ratio between EE and bubble
would still be substantial. Additionally, the high profile of
a bubble memory device would greatly increase overall
board volume as boards cannot be spaced closer together
than the tallest component height. Decoding of a 4
megabit EEPROM array can be done with a simple one-of-
Weight is one area that seldom becomes an issue in most
designs but does come up on occasion. Once again, the
comparison is not straight forward. Basic bubble memory
devices commonly have weights in the vicinity of 75 grams
per 1 megabit device. This, of course, does not take the
weight of support circuitry into consideration. The equivalent EEPROM bank of four 256K devices would have an
approximate weight of 5 grams. With the bubble memory
FIGURE 1
COMPARISON CHART
BUBBLES TO EEPROMs
BUBBLE
Power Consumption
Access Time in microseconds
5
EEPROM
.5
RATIO
10/1
50,000
.20
250,000/1
Average Data Rate
(Read) K Bits/Second
125
32,000
1/256
Data Rate
(Write) K Bits/Second
125
800
1/6.5
75
5
15/1
1.25
.2
6/1
Weight (Grams)
1 Megabit Volume
(Unit only) Cubic Inches
seeQ
Technology, Incorporated
8-86
REMARKS
Considerable current
would be drawn by
bubble memory
support circuitry
4 Megabit bubble and
sixteen 256K EEPROMsi
shown in fig. 3
Does not include
bubble support chips
per second (this would be 51.2K bits per second) is about
half the speed of the bubble's write data rate it can be
improved many fold for systems using multiple EE Devices.
support devices also taken into consideration, the ratio
would significantly surpass this 15 to 1 ratio.
Power consumption al most always warrants some consideration. Four megabit bubbles have power supply requirements around 4 watts typical and greater than 5 watts
maximum. Sixteen (16) of the 256K type EEPROMs and
a one-of-sixteen decoder under worst case conditions
would draw less than 100 ma at 5 volts. This would be onehalf watt or about 10 percent of the power of a bubble
memory. While the sixteen 256K's only require a single
decoding chip for support, the bubble requires numerous
support chips. This support draws power too. To get a
realistic feel for bubble power consumption, it becomes
necessary to examine then at the board level where the
host of necessary support devices are installed.
In the case of medium to large arrays, which would be the
case in mass storage applications, the common approach
is to decode chip selects from the high-order address
inputs (see figures 2 and 3). But positioning the chip select
decoder in the address space immediately above the page
address inputs would allow each consecutive device to
store the next logical page.
Applying this approach to a 4 megabit array, system
addresses Ao to As would go directly to Ao to A5 inputs of
the EEPROMs. For an array of 16 P devices, requiring 4
address inputs to select the 16 devices, system addresses
A6 - Ag would go to a 4 to 16 decoder network, providing
the 16 chip selects required. System address A,o would go
to address A6, system address A11 to address A 7 , continuing thru system address A'8 to address A,4. The 10 msec
write cycle would continue independently in each device
while the system wascontinuingto write logicallyconsecutive pages in the other devices. This makes the page size
1024 bytes, thus the system should stop writing and wait
for the write cycle to complete after 1024 sequential bytes
had been written.
The boards considered for comparison were not expandable, that is to say they were fully stuffed, 4 megabit
boards. Power consumption on these boards runs between 10 and 20 watts. Additionally, there were multiple
power supplies required, not the single 5 volt supply
required by the EEPROMs.
Data rate is the speed at which the data can be continuously delivered to the addressing device. In this area the
bubble is specified at maximum (burst) and average. Burst
data rates can be fast as 200,000 bits per second. Average
data rates can be on the order of 125,000 bits per second.
Making the EE comparison, data rates are the same as
access times, and therefore 200 nanoseconds per byte (8
bits). Putting this in perspective, after the bubble has taken
88 milliseconds to get started (initial access time), while
the bubble is fetching 256 bytes the EEPROM could
deliver 65,536 bytes.
For a 4 megabit array (sixteen 256K EEPROMs), this
design approach would produce a data rate in write mode
of greater than 100,000 bytes per second or 61/2timesthe
bubble's write data rate.
Temperature sensitivity is often a major design consideration. This is very true for military, industrial and space
applications. These designs often require operation or at
least storage down to -55 degree C and as high as 125
degree C. Bubble memories have problems at temperature extremes and often specify their minimum temperature for operation a few degrees above 0 C. This does not
comply with standard commercial grade temperature
ranges and falls far short of either military or industrial
grade temperature ranges. Similar problems exist at high
temperature. We commonly see maximum temperature
for operation between +30 degree C and +50 degree C.
Even the +50 degree C falls for short of the commercial
temperature specification of +70 degree C. Needless to
say both military and industrial temperature ranges are
completely missed. EEPROMs operate over the entire
commercial, industrial and military temperature ranges.
Data rate does not imply direction. This is to say that data
rate does not apply only to reads of data but also to data
writes. For a bubble memory, read and write data rates are
equal, butthe rates differ when EEPROMs are used. Read
data rates were discussed above. Write data rates in
EEPROMs are a bit more complex. In high density
EEPROMs, byte write times and page write times are the
same. A "page" is 64 consecutive bytes of data. This page
of data can be loaded as fast as 350 nanoseconds per
byte, thus a page load would take 22.4 microseconds.
After this time, a maximum of 10 milliseconds is required
for the write cycle to complete.
The microprocessor's write data process must halt during
this 1 0 milliseconds until the device is again ready to load
another page and begin the 10 millisecond write sequence
again. This would imply a write data rate of 350 nanoseconds per byte "burst-mode" with a maximum of 64 bytes
or an over all rate of 6400 bytes per second. This 6400
bytes per second rate is comprised of one hundred 10
millisecond write sequences of 64 bytes. While 6400 bytes
seeQ
Clearly, EEPROMs share the intrinsic nonvolatility of
bubble memories without the disadvantages in speed,
power consumption and temperature range. Figure 1
compares the imporant attributes of the two technologies.
Complete technical information is contained in Seeq's
28C256 datasheet.
Technology, Incorporated
8-87
I
NORMAL CHIP SELECT DECODE
I
0
DATA
~
I
A 6 -A 14
DATA
~
---
CD
---
<-.....
\
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READ
WRITE
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A 1S -A 18
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10F
16
DECODE
c
c
c
c
CS16
Figure 2.
seeQ
Technology, Incorporated
8-88
-
WE
•
[J
[J
[J
[J
DEVICE 16
----OE
CS
WE
DECODING METHOD TO ENHANCE
WRITE CYCLE DATA RATE
I
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DATA
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Figure 3.
S99Q
Technology, Incorporated
8-89
I
8-90
Memory Products
Application Note
USING HIGH SPEED
CMOS EEPROMS WITH
HIGH PERFORMANCE
MICROPROCESSORS.
October 1987
I
seeQ
Technology I Incorporated
8-91
Using High Speed CMOS EEPROMs with
High Performance Microprocessors.
Satisfying ever increasing demands on microprocessor
throughput can be achieved in several ways, the simplest
of which is to increase system clock frequency. However,
this technique yields higher performance only if the remainder ofthe system is capable of operating atthe higher
rate. Memory devices on the system must be able to
respond to the accelerated transfer rate to avoid insertion
of wait states. Speeding up clock rates without decreasing
access times will generally cause the microprocessor to
wait faster. The 38C16 and 38C32 high speed CMOS
EEPROMs from SEEQ technology are designed to satisfy
the performance requirements of high performance microprocessors.
38C16 and 38C32 are available in access times ranging
from 35 ns to 70 ns. The operational mode table is shown
in Table 1. Read operation for the devices is similar to any
standard memory device. Chip enable access times are
faster than address access times (see data sheet) which
can be a significant advantage in high speed microprocessor designs.
The 38C16 and 38C32 are 2K x 8 and 4K x 8 bit CMOS
EEPROMs manufactured using SEEQ's advanced 1.25
micron CMOS process. SEEQ's proprietary oxynitride
process and patented differential Q_CeIl™ design give the
parts fast access times and high endurance. The 38C16/
32 are ideal for high speed applications requiring nonvolatility and in-system reprogrammability. Both commercial and military temperature range products are available.
The write operation is similar to static RAM. Because of the
fast address and data latches, the write data latch cycle is
as fast as a read cycle. The address is latched on the falling
edge of CE or WE whichever occurs last and data is
latched on the rising edge of CE or WE whichever occurs
first. After the data is latched the built-in timer completes
the non-volatile write cycle within a maximum time of 5 ms.
A typical device has a write cycle time faster than the
Device Features:
Read Operation:
Write Operation:
38C16/32 OPERATIONAL MODES
MODE PIN
CE
OE
WE
I/O
Read
VIL
VIL
VIH
DOUT
Standby
VIH
X
X
HIZ
Write
VIL
VIH
VIL
Write
Inhibit
X
VIH
X
VIL
X
X
VIL
VIL
VIH
X
VIH
VIL
X: Any TIL Level
Table 1.
Q-Cell is a trademark of SEEQ Technology, Inc.
eeeQ
Technology, Incorporated
8-92
DIN
HI ZlDOUT
HIZ
HI ZlDouT
No Operation
(HIZ)
maximum specified 5 ms. The 38C16/32 feature DATA
polling to enable the user to optimize write time. During the
internal write cycle, the complement of bit 7 of the data byte
written is presented at the output 1107 when a read is
performed. Once the write cycle is completed, true data is
presented at the outputs. A software 'polling' routine (see
fig. 1) can be used to determine write cycle completion.
The data bit 7 polling cycle specifications are the same as
a read operation. During data polling, the addresses are a
don't care.
WRITE DATA
TO EEPROM
STORE ADDRESS,
DATA
READ
LAST WRITE ...- - - - -.....
ADDRESS
Write data protection:
om POLLING LOOP
38C16 and 38C32 provide protection against false write
during power-up/down using on chip circuitry. Writing is
prevented under anyone of the following conditions:
OPTION: CAN PERFORM OTHER
TASKS IN LOOP
1. When Vee is below write inhibit voltage VWI'
2. A high to low write enable transition has not occured
when Vee is between VWI and Vee min.
3. WE, CE or OE are in TTLiogical states other than those
specified for byte write in the mode table (Table 1).
NOT EQUAL
38C16 and 38C32 feature an on-board bandgap voltage
level detector. The detector disables the EEPROM write
circuitry whenever Vee falls below write inhibit voltage
VWI ' The internal charge pump (voltage multiplier) is disabled, preventing the high voltages which are necessary
for the programming cycle from being generated. It is
impossible for data corruption to occur when the charge
pump is disabled. SEEQ's EEPROMs are guaranteed to
be write disabled when Vee falls below write inhibit voltage
VWI' VWI is between 3.8 to 4.25 V over the military temperature range.
EEPROM AVAILABLE
FOR ACCESS
Figure 1. Byte Write with DATA Polling.
Since present day systems employ a mixmatch of both
TTL and CMOS components, it is recommended that
external hardware write protection circuitry be used in
addition to the on-board protection circuitry just described.
This is needed to eliminates false writes when Vee is
between 3.8 to 4.5 V (see Application Note 11). Absolute
protection from false writes can be thus achieved while
having the added benefit of being totally transparent to the
system software.
missiles and even ships or ground vehicles. The standard
specifies the microprocessor architecture and instruction
set. Also defined are two memory addressing modes, a
standard mode of 64K-word direct addressing and an
optional expansion mode of 1-Mword direct addressing.
The latter mode is segmented into 256 blocks of 4K-words
each. The 38C16 and 38C32 offer an excellent fit for
1750A processors and give system designers/programmers a wider array of choices to come up with the next
generation of flexible and more powerful adaptive systems.
System Interface examples:
MIL-STD-1750A is the U.S. Air Force's instruction set for
16-bit microprocessors embedded in avionic weapon
systems. This standard is also used by the Navy, Army and
NATO. Typical 1750A applications involve real-time avionic applications in systems incorporated into aircraft,
seeQ
Technology. Incorporated
8-93
I
MDC281 MIL-STD-1750A CPU Module:
the start of a new machine cycle and is used as the timing
reference. SYNC low indicates that address is on the AD
bus. The AD bus is a bidirectional multiplexed Address and
Data bus (ADoo - AD 1J. This bus is shared between the
external system and the internal module resources and
hence to avoid bus contention, the AD bus must be
isolated from the external system using a bidirectional
transceiver. Data Direction signal DO is used for transceiver direction control. DO low indicates read transfer,
while high indicates a write transfer. High to Low transition
of the address strobe AS is used to latch Address into a
transparent latch during AD bus de-multiplexing.
The McDonnell Douglas MDC281 is a certified MIL-STD1750A (Notice 1) 16-bit CPU consisting of three custom
CMOS/50S LSI chips MDC17501 (Execution unit), MDC
17502 (Control unit) and MDC 17503 (Interrupt unit)
mounted on and interconnected within a ceramic substrate. The MDC281 CPU is designed for military avionics
applications like sensor data processing, operation and
control of weapons systems. The CPU is particularly
suitable for embedded applications requiring less than
64K words of memory.
38C16/32 Interface:
All transfers between the module and the memory are
referenced to the AS and OS bus control signals and are
characterized by INIOP low and MIlO, CD high. Control
Direction signal CD is used to control direction of the
control signal transceiver. This signal goes high to indicate
thatthe module isdrivingthe AS, OS, MIlO, RDIWR and INI
OP signals.
A typical MDC281 interface to 38C16/32 memory is shown
in fig 2. 38C16-70 or 38C32-70 with a maximum address
access time of 70 ns can be used without wait states in the
memory subsystem for a 20 MHZ MDC281. For a complete description of pin assignments and signal functions
refer to the MDC281 data sheet. Each machine cycle
consists of a minimum of 5 OSC periods. The synchronization clock (SYNC) output high to low transition signals
38C32
.....
,/
.....
LATCH
MDC281
ADoo -AD15 ....
ADoo
AD15 I - -
~
.....-
ADDRESS A15 - Ao
r-----V
AS~ LE
DATA D15 - Do
.,...
DIR
DD
CONTROLS
~
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E
..
r--l
~
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.
II
!:.
!J..r--
"-
~
p... -CS
_
P
L....-
RiW
.....READ
-g-- OE
x
WE
I~
DS
Figure 2. MDC281 Interface to 38C16/32.
Technology, Incorporated
8-94
~
~~
ADDRESS
DECODER
'-y
Miio
seeQ
WE
CE
38C32
BUFFER
...
DATA 7 _0
OE
NOTE: ADDRESS
FOR 38C1
XCEIVER
,--L..t....
ADDRESS
A11- AO
ADDRESS
A11- A O
DATA 7 _0
OE
-WE
CE
Read Operation:
Read transfers begin with address bei ng placed on the AD
bus immediately following SYNC high to low transition.
This address is assured to be valid for the cycle by latchi ng
it in a transparent latch on the high to low transition of AS.
The DO signal is high during this portion of the transfer.
RDIW indicates direction of transfer. During read (fig. 3)
the AD bus drivers are placed in a high impedance state at
the low to high transition of SYNC to give the memory
access to the bus. Next OS signal goes low and is used
by the memory system to generate output enable (OE). DO
also goes low shortly after OS goes low and this signal
reverses the direction of the AD bus transceivers. The
memory then pulls ROY lowto conclude the transfer. Read
data from the 38C16/32 is latched into the module on the
SYNC high to low transition.
CPU stays in SI' extending the address phase of the bus
cycle. Otherwise, it proceeds to states S2 followed by S3.
Read Operation:
STRBA signal is pulled low in state S2 (fig. 6). The high to
low transition of this signal is used to latch the memory
address. The CPU then pulls STRBD output low and prepares to receive read data from 38C16/32 by turning the
address/data bus around. STRBO is used to enable data
from the memory.
Write Operation:
During write cycles the CPU starts driving the bus with the
write data immediately after the address (fig. 7). STRBD
signal is activated during S3' allowing enough write data
setup time to STRBO falling edge and hold time for the
rising edge of STRBD to write data. Atthe end of S3 RDYD
is sampled, and if low, state S3 is continued extending the
data phase. If the signal is sampled high the write cycle is
terminated.
Write Operation:
Write is indicated by RDIW going low (fig. 4). The address
is replaced by data when SYNC transitions from low to
high. Next, the OS signal goes low and is used by the
memory system to generate WE. Data is valid at the low to
high transition of OS and is latched into the 38C16/32. DO
stays high forthe duration of a write transfer. The memory
system pulls ROY low to conclude the transfer.
Software Considerations:
Examples of hardware interface of MIL-STD1750A microprocessors to 38C16/32 have been shown. 38C16/32
have a built-in timer to control the internal non-volatile write
cycle. The parts feature an automatic erase before write.
The write cycle takes a maximum of 5ms/byte. System
software has to take into account this byte write time of the
EEPROM. The system writes to the EEPROM and then
follows the write with a polling routine as shown in fig. 1 to
determine the end of the EEPROM internal write cycle. If
the system application demands thatthe 5ms write time be
utilized usefully, the technique shown in fig. 8 can be used.
The on-board timers A or B can be used. These timers can
be used to timeout the 5mswritetimeofthe EEPROM and
programmed to interrupt the CPU. The CPU can thus carry
out other tasks while the internal write cycle of the
EEPROM is in progress.
Fairchild 9450:
Fairchild 9450 is single chip solution implementing the
complete MIL-STD 1750A instruction set architecture
(ISA) and its floating point standard. It allows addressing
of up to 2M words of memory and with the addition of the
F9451 Memory management unit (MMU), upto 16M words
of memory.
38C16/32 Interface:
A typical minimal configuration 38C16/32 memory subsystem interface is shown in fig. 5. The 20 MHz F9450
provides for a 90 ns memory access time without wait
states. Hence, 38C16-70 or 38C32-70 with a maximum
address access time of 70 ns can be used in the memory
subsystem. Bus cycles are a minimum of 4 or 5 states long.
Memory and 1/0 cycles are identical and the status of the
MIlO line distinguishes the two cycles. State So is used for
bus acquisition. This state is followed by SI state. After the
start of SI state, the CPU outputs the address after a delay.
At the end of SI' ROYA input is sampled. If ROYA is low the
seeQ
DSP Applications:
Present day DSP processors are finding a wide range of
applications like Encryption/Decryption, voice-band, precision servo control, pattern recognition, adaptive control
and intelligent filtering. Most of today's applications use
ROM or EPROM based memories to store algorithms and
Technology, Incorporated
8-95
I
OSC
SYNC
AS
-=-\
es
~
/
BUS
~
Miio
J
RDiW
\
r-
\
7
DO
AD
\
/
\
;-
\
ADDRESS
(
)
DATA IN
.J
\
ROY
Figure 3. MDC281 Read Cycle.
seeG
Technology, Incorporated
8-96
/
)
OSC
SYNC
AS
OS
\ ~--------------~/
\'--/
~
\~---------------
=-;
\'---_ _--JI
7
DO
AD
BUS
~
MiiO
J
RDiW
ADDRESS
________________
-J~~____D_AT_A_O_U_T____~
~
\ /
ROY
Figure 4. MDC281 Write Cycle.
seeQ
Technology, Incorporated
8-97
I
TMS320C25:
The TMS320C25 is a high performance digital signal
processor featuring a single accumulator and a Harvard
type architecture in which program and data are implemented in separate address spaces. The processor features on-chip data RAM of 544 words, on-chip program
ROM of 4K words and supports direct addressing of up to
64K words of external program memory and 64K words of
as a result use is restricted to applications that utilize fixed
algorithms and co-efficients. Adaptive algorithms must
use RAM, thus forcing the processor to repeat its adaption
sequence each time power is turned on. SEEQ's high
speed CMOS EEPROMs 38C16 and 38C32 present an
excellent fit for manyoftoday's DSP processors and open
the door for system designers and programmers.
38C32
LATCH
ADDRESS
IBo
iB15
.if
I\.
"
-
\s- :--V
~
f-----
l~
F9450
~
-
y
LE
-
LATCH
DATA IN
OE
~
STRBD
LATCH
ANi
-
r---<
MIlO
LE
k~RCs
L,I
~
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"
~
-~
~~
~
DATA
...
Technology, Incorporated
8-98
READ
ADDRESS
A 11 -Ao
DATA
07 -Do
"
CE
~f-
6E
~
WE
1
I'-"
~E
Figure 5. F9450 Memory Interface.
seeQ
WE
y
A
Dii
6E
-
38C32
OE
LATCH
~
CE
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--<
DATA
.00
~
DATA OUT
r-Y
STRBA
ADDRESS
An-Ao
NOTE:
p
ADDRESS
U
-
~
~
A10-Ao
FOR 38C16
so
53
I
53
52
51
51
50
CLOCK
7
RDYA
RDYD
»»»»> ««««
»»»t» ««««<
MliORiW
oil
7
7
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IBo-IB 15
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5TRBD
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Figure 6. F9450 Read Cycle.
50
51
52
I
53
54
50
CLOCK
MliORiii
DIT
>a
««««<
'\
5TRBA
I
7 \
RDYA
/
RDYO
I
WIO
00
0.320 (8.13)
MAX.
0.200 (5.08)
0.150 (3.81)
-.J I---0.110 (2.79)
.090 (2.29)
TYP.
-+l f.-0.055 (1.40)
0.045 (1.14)
0.021 (0.53)
0.015 (0.38)
J
I~"0.610(15.49)
0.590 (14.99)
.1
(AT STANDOFF)
0.022 (0.56)
0.008 (0.20)
SEEa OUTLINE M001/-
NOTE: All dimensions in inches (millimeters).
seeQ
MD500001/-
Technology, Incorporated
----9-.1-6-------------------l
CERAMIC PIN GRID ARRAY PACKAGES
28 LEAD PGA PACKAGE TYPE T
.400 (10.16)
.560 (14.22)
.540 (13.72)
~
sse
"
1
]26
.660 (16.76)
1
.050 (1.27)
sse
.,....--t----i-----,i-
0.080 (2.03)
MAX .
"
./
,
.105 (2.67)
.080 (2.032)
SEEQ OUTLINE T001/-
NOTES
1. All dimensions are in inches and (millimeters).
seeQ
MD500001/-
Technology, Incorporated
----9--1-7------------------'
CERAMIC DUAL-IN-LINE PACKAGES
28 LEAD SIDEBRAZE PACKAGE TYPE C
1.425 (36.19)
1.375 (34.92)
"'
"
D
C
PIN 1
.225 (5.72)
.060 (1.52)
MAX., ~OO~I~~]
L - ~~=-6
I
II
-+I~
~X49)
.098
.
.060 (1.52)
.040 (1.02)
.021 (.53)
.015 (.38)
I
~
BASE PLANE
~SEATING
.150 (3.81)
PLANE
MIN .
.110 (2.79)
.090 (2.29)
SEEQ OUTLINE C001/-
NOTES
1. All dimensions are in inches and (millimeters).
seeQ
MD500001/-
Technology, Incorporated
-----9_-1-a---------------------.J
CERAMIC DUAL-IN LINE PACKAGES
32 LEAD SIDEBRAZE PACKAGE TYPE C
1 4 - - - - - 1.645 (41.77) -------i~
1.555 (39.50)
.620 (15.75)
.060 (1.52)
.040 (1.02)
I
.
.005(.13)
MIN.
~~
BASEPUWE
"-SEATING
.150 (3.81)
MIN.
.021 (.53)
.015(.38)
PLANE
I
I
r
I
.012 (.31)
.008 ( . 2 0 ) - +
(NOTE 2)
.630 (16.00)
.570 (14.48)
.110 (2.79)
.090 (2.29)
SEEQ OUTLINE C003/-
NOTES
1. All dimensions are in inches and (millimeters).
seeQ
~D500001/-
Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J
9-19
CERAMIC DUAL-IN-LINE PACKAGES
40 LEAD SIDEBRAZE PACKAGE TYPE C
1 4 - - - - - 2.025 (51.44) _ _ _ _~
1.975 (50.17)
.620 (15.75)
.060 (1.52)
.040 (1.02)
'00~1~~3)
~
~
BASEPLANE
",,-SEATING
PLANE
.150 (3.81)
MIN.
.021 (.53)
.015(.38)
.012
,.Ot,
.008 (.20)
(NOTE 2)
I
I
--r::
.630 (16.00)
.570 (14.48)
.110 (2.79)
.090 (2.29)
SEEQ OUTLINE COO2l-
NOTES
1. All dimensions are in inches and (millimeters).
seeQ
MD500001/-
Technology, Incorporated
-----9---2-0----------------------1
SURFACE MOUNT PACKAGES
28-PIN CERAMIC LEAD LESS CHIP CARRIER TYPE L
-.l
.040 x 45°
~ (1.02 x 45°)
&=======~'I
3PLCS
A .009 ± .005
(.23R)
,-
.020 x 45°
(0.51 x 45°)
PIN 1
~
T
rlnnnffioooll
.075 (1.91)
.060 (1.52)
~
T
.062 (1.57)
.050 (1.27)
SEEQ OUTLINE L001/-
NOTES
1. All dimensions are in inches and (millimeters).
seeQ
MD500001/-
Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---.J
9-21
SURFACE MOUNT PACKAGES
32 PIN CERAMIC LEADLESS CHIP CARRIER TYPE L
.458(11.63) ~
.442 (11.23)
COft=
1--:ii::6~: --I-~
R .009± .005
/ (.23 ±'13)
.020 ±.010 x 45°
,_
(.51 ± .25 x 45°)
INDEX
'I
.533 (11.00)
~~~---....s-...,..
i
.560 (14.22)
.400 (10.16)
ll~
~
T
BSC
.050BSC
(1.27)
.040 x 45°
(1.02 x 45°)
(TYP. 3 pies.)
~
T
Ilnnnnnnnll
.110(2.79)
.068 (1.73)
~
T
.072(1.80)
.059 (1.50)
SEEQ OUTLINE L002l-
NOTES
1. All dimensions are In Inches and (millimeters).
2. All tolerances shall be ± .010 (.25) unless otherwise specified.
seeQ
AfD500001/-
Technology, Incorporated - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J
9-22
SURFACE MOUNT PACKAGES
32 PIN WINDOWED CERAMIC LEAD LESS CHIP CARRIER TYPE L
R .009±.OO5
PIN 1
(.23± .13)
.020 ± .010 x 45·
(.51 ± .25 x 45·)
!
.400 (10.16)
Bse
j
.040 x 45·
(l.02x45·)
.015 MIN.
(TYP. 3 pies.)
(TYP.)(.38)
~
1T
11000000011
.117 (2.79)
~~~
T
.071 (1.80)
~~~
SEEQ OUTLINE L003/-
NOTES
1. All dimensions are in Inches and (millimeters).
seeQ
MD500001/-
Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J
9-23
SURFACE MOUNT PACKAGES
44 PAD CERAMIC LEADLESS CHIP CARRIER TYPE L
.040 x45°
(1.02 x 450 )
REF
---11
n
.640(16.26)
I
i
----+----
~IJ~====i====;;;;;/..4 (~ !~F:; )
039(0.99)
.033 (0.84)
~~
L
T
I
INDEX CORNER
~
>:<~~
.015 MIN
(0.38)
DETAIL A
n
l.t-cI ~t
___ 1__ _
L
.003 (.076)
.015 (.381)
T
PIN 1
.055(1.40)
.045(1.14)
I nnnnnffinnnnnil
.064 (1.63)
.120 (3.05)
~
T
.054 (1.37)
.088 (2.24)
.006 (.152)
.022 (.559)
SEEQ OUTLINE l004/-
NOTES
1. All dimensions are In Inches and (millimeters).
seeQ
MD500001/-
Technology,lncorporated - - - - - - - - - - - - - - - - - - - - - - - - - - '
9-24
SURFACE MOUNT PACKAGES
20 PIN PLASTIC LEADED CHIP CARRIER TYPE N
.048 (1.22) x 450
.200 (5.08)
PIN NO.1 IDENTIFIER
sse
.042 (1.07) x 450""
J'.~(9781
0rol
n
I ~
.356 (9.04)
.3WIJ~ .356(9.041~
jL j L
.350 (8.89)
.030 (.76)
REF.
.395 (10.03)
.385 (9.78)
1 r.056(1.42)l
.042 (1.07)
.050 (1.27)
sse
.012 (.30)
.008 (.20)
~1-1
I
r-.020 (.51) MIN .
I,
r'---.........L._
~
R .045 (1.14)
...---,. 1 I R .025 (.64)
-1.021 (.53)
1 .013 (.33)
L-~
r'---.........L._
.330 (8.38)
.290 (7.37)
~
l!3
.120 (3.05)
.090 (2.29)
.180 (4.57)
.165 (4.19)
SEEQ OUTLINE N001/-
NOTES
1. All dimensions are in inches and (millimeters).
2. Dimensions do not include mold flash. Max allowable
flash Is .008 (.20).
seeQ
MD500001/-
Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--...J
9-25
SURFACE MOUNT PACKAGES
28-PIN PLASTIC LEADED CHIP CARRIER TYPE N
PIN NO.1 IDENTIFIER
.048 (1.22) x 45°
.042 (1.07) x 45° ' "
r'~~
r
.495 (12.57)
.485 (12.32)
I
L - Y-
.300 (7.62)
.456 (11.58)
4°ODt=400(I1.~13
~
JL
.450(11.43)~
.030 (.76)
.495 (12.57)
.485 (12.32)
REF.
Ij
L
.050 (1.27)
esc
1"
.020 (.51) MIN.
SEEQ OUTLINE N002l-
NOTES
1. All dimensions are in inches and (millimeters).
2. Dimensions do not include mold flash. Maximum allowable
flash is .008 (.20).
eeeQ
MD5000011-
Technology. Incorporated
9-26
SURFACE MOUNT PACKAGES
32 PIN PLASTIC LEADED CHIP CARRIER TYPE N
PIN NO.1 IDENTIFIER
f-- .300 (7.620) -.J
I
sse
I
.048 (1.22)
.042 (1.07)
-;fTI
.595 (15.11)
.585 (14.86)
I
L
.050 (1.27)
sse
.400 (10.160)
sse
r
-.J ~
mMAAAtJJ
I
.430 (10.92)
\ . - - .390 (9.91)
---lI
~
T
.140 (3.56)
.120 (3.05)
.015 MIN. (.381)
.021 (.53)
.013(.33)
.530 (13.46)
.490 (12.45)
Y
.012 (.30)
.008 (.20)jl-
SEEQ OUTLINE N003/-
R .040 (1.02)
R .030 (.76)
L
.095 (2.413)
.070 (1.78)
NOTES
1. All dimensions are in inches and (millimeters).
2. A" tolerances shall be :t .003 (.076) unless otherwise
specified.
3. Dimensions do not include mold flash. Max allowable
flash is .008 (.20).
seeQ
MD500001/-
Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
9-27
SURFACE MOUNT PACKAGES
68 PIN PLASTIC LEADED CHIP CARRIER TYPE N
.048 (1.22)
.042 (1.07) x 45°
t--_ _ _ _ .800~g32)-----I
:~~!~!:~~l~1
14-_ _ _ _ _ .995 (25.27)
.985 (25.02)
R .045 (1.14)
R .025 (.64)
SEEQ OUTLINE N004/-
NOTES
1. All dimensions are in inches and (millimeters).
2. Tolerances are ± .003 (.08) unless otherwise specified.
3. Dimensions do not include mold flash. Max allowable flash is .008 (.20).
seeQ
MD5000011-
Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
9-28
SURFACE MOUNT PACKAGES
28-LEAD HERMETIC CERAMIC FLATPACK TYPE F
.050 (1.27)
sse
.019 (.48)
.015 (.38)
!
~
T
f
.740 MAX. (18.80)
.000 MIN.
!
L
.045 MAX. (1.14)
.130 (3.30)
.090 (2.29)
!
.420 (10.67)
.380 (9.65)
----l_~_ _ _ _ _ _ F=I-=======,·I
I
I
I
.006 (.15)
.003 (.08)
--L
L-~I~~~~--~~~~~IT
04J) I;:~::; MIN-1
.026 (.66)
.180 (4.57) MIN .
r . 2 5 0 (6.35)------1
SEEQ OUTLINE F001/-
NOTES
1. All dimensions are in inches and (millimeters).
seeQ
MD500001/-
Technology, Incorporated - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
9-29
SURFACE MOUNT PACKAGES
32-LEAD HERMETIC CERAMIC FLATPACK TYPE F
.050 (1.27)
sse
.019 (.48)
.015 (.38)
~
~
i
T
.000 MIN.
~
~
L
.045 MAX. (1.14)
.130 (3.30)
.090 (2.29)
.420 (10.67)
.380 (9.65)
1
!
I"
~--'----I
~
~~~------~I
f
.045(1.14)
.026 (.66)
.840 MAX. (21.34)
t
.030 (.76) MIN.-+
.370 (9.40)
.250 (6.35)
1
I
.006 (.15)
.003 (.08)
~
~I~~~~iT
t
I
~
.180 (4.57) MIN .
SEEQ OUTLINE FOO2l-
NOTES
1. All dimensions are In Inches and (millimeters).
seeQ
MD500001/-
Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - '
9-30
SURFACE MOUNT PACKAGES
28-LEAD SOIC PACKAGE TYPE S
.040 (1.02)
.050 (1.27)
J..
-1-T·
------.-
E9
.040 (1.02)
050
(1.27)
.340 (8.64)
.350 (8.89)
L.....r'I""TT""TT"''TT''''lI'T''Tlr-TT''TT''"~T''T'lr-rT'''''I''r-".-J
- 21.474
·1
(12.041
(12.551
~~
.014 (0.36)
.020 (0.48)
~...
I
:j~n~:~~l
I
N~e2
~-'-
:~gg !~:~l ~h nn n n nn n nn nnnnd::; !~:~!--1: .dJ~(======)~\. ~
t
.004 f!0.1021
-
.010 0.254
-
-
~~
-
-
-
T
,
.0060 (0.15)
.0125 (0.32)
.050 (1.27) BSC
-J ct
o
80
-
.026 (0.66)
.050 (1.27)
5EEQ OUTLINE 5001/-
NOTES
1. All dimensions are In Inches and (millimeters).
seeQ
MD500001/-
Technology, Incorporated
-------------------------1
9-31
SEEQ Die Sales
Description
Many of the SEEQ Technology Products contained in this Data Book are available in unencapsulated die form. Products sold in die form have been specifically screened to a special die sales test
flow and are ideally suited for hybrid and memory card applications. After screening, all die are
optically inspected per method 2010 condition B of MIL-STD-883C. Die are then placed in waffle
packs and enclosed in anti-static vacuum sealed bags prior to shipment.
Test Flow
All SEEQ Die are screened 100% to parametric, function and data retention tests. Properly
packaged devices are expected to perform to the AC and DC parameters listed on the product data
sheets. The following flow chart illustrates the typical die test flow.
Die Sales Test Flow
OPERATION
COMMENT
FROM FAB
PARAMETRIC FUNCTIONAL
CYCLlNG*, DITRACE*
2.5 HOURS AT 250 DEG C
OR 24 HOURS AT 170 DEG C
PATTERN VERIFY, DITRACE,
PARAMETRIC, FUNCTIONAL
883 METHOD 2010, CONDo B
883 METHOD 2010, CONDo B
1% AOQL
LOAD WAFFLE PKS/LBL
Q.C. LOT ACCEPTANCE
*DITRACE AND CYCLING ON EEPROM DIE ONCE
seeQ
Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - -
9-32
Die Sales Test Flow (cont.)
OPERATION
VACUUM SEAL
COMMENT
PACKING
FINISHED GOODS
PACK FOR SHIPMENT
Q.A. SHIPPING INSP.
SHIP
Standard Die Packaging
All die shipped by SEEO will be packaged in the following manner:
Die will be placed in a "waffle pack" with a cavity of proper size to restrain the die without causing
damage and without allowing the die to change orientation.
Lint-free paper insert is placed over the "waffle pack" followed by an antistatic poly-film insert. The
waffle pack lid is placed on top and then secured with plastic locking clips.
Label with such information as lot number, quantity, part number and datacode is placed on the waffle
pack.
Waffle packs are placed in an antistatic bag which is then vacuum sealed.
Label identifying the shipment is affixed to the top of the bag.
Additional Information
For your reference, the following pages detail product specific bond pad locations for the SEEO
products available in die form. Contact the factory or your local SEEO representative for addition
information on die characteristics or suggested assembly flow and conditions.
seeQ
Technology. Incorporated
9-33
••
18·
20 19
•• 21
22
·23
.24
~
c...>
52813
• 1
-2
.3
.4
5
14 13 12.
11 •
10 9_
6
7
••
I'"
seeQ
•
17
16.
15 •
Technology, Incorporated
8
••
.161
~I
----9-_3-4--------------'----1
••
21 • •
20~·
23 22
• 24
18 •
17 •
16.
15 •
• 25
:......
0')
<.0
• 27
.28
.1
• 2
52833
14 •
13 •
12.
11 •
10 •
8.9 •
• 3
• 4
• 5
.6 • 7
r-
seeQ
Technology, Incorporated
.206
--I
----9_3-5----------------J
••• •
3
2
24
1
••
23
N/C
•
21
20.
2804A
co
o
or-
8
9 10 11 12 13 14 15 16 17
• •••••••••
11"11
....
---------
seeQ
Technology, Incorporated
N/C.
18 •
. 1 8 9 - - - - - - - - - - ...~1
.
----9-3-6-----------------'
•
24
••
23
22
2816A15516A
CX)
o
T'"""
9
It--II~
10 11
•• • •••• ••
__- - - - - - -
seeQ
12 13 14 15 16 17
Technology, Incorporated
19 •
18 •
.189---------..,~1
---9-_3-7----------------1
.6 ••••. ...
• 7
5
4
3
1 28
27
25
N/C •
24
22 •
co
oor-
2817A/5517 A
11 12 13 14 15 16 17
• •
•
• •
• •
18 19
• •
21 •
20.
1"'II1~---------·189---------~~1
seeQ
Technology, Incorporated
----g_3-a-----------------l
••
••
23 22
21 20
19 •
• 24
18 •
17 •
• 25
• 27
16 •
15.
14 •
13 •
12 •
11 •
10 •
• 28
:.....
00
(0
2864
• 1
•
•
•
•
6
2
3
4
5
7
••
I. .
seeQ
Technology, Incorporated
••
8
.214
9
~I
----9--39--------------------
• •••• •• • • • •
.'Z,
4
7
3
2
N/C 28[1]
6
27
25 24
23
•
22
.168
28C64
21
•
8
•
9
10
11 12 13 14 14 15 16 17 18 19 20
• • • • • ••••••• •
r-
.231
"I
NOTE:
1. Should be double bonded.
seeQ
Technology, Incorporated
----9--4-0------------------'
•• • • • •
•
1 28[1]
27
25 24
23
22
28C65
21
8
•
9
10
••
•
•••••••••••
11 12 13 14 14 15 16 17 18 19 20
I~~----------------.243----------------~~~;
NOTE:
1. Should be double bonded.
seeQ
Technology, Incorporated - - - - 9 - - 4 - 1 - - - - - - - - - - - - - - - - - - '
••
••
23 22
• 24
• 25
.26
·27
.192
.28[1]
28C256
• 1
• 2
.3
• 4
10 •
• 5
.6.7
I....
21 20
19 •
18 •
17.
16.
15.
14 •
14.
13 •
12 •
11 •
8.9.
.328
~I
NOTE:
1. Should be double bonded.
seeQ
Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--.1
9-42
•
7 ••
67s"·
4.
3•
2•
1.
28 •
.8
.~9
• 11
• 12
• 13
.14
~
00
CAl
.15
.16
27C256
27.
26.
• 17
,~
-'--
seeQ
25 •
• 18
24 •
.19
20 21
2223
••
r-
Technology, Incorporated
••
.164
9-43
~I
••
••
23 22
• 24
• 25
• 26
.27
.192
• 28[1]
28C256A
• 1
• 2
• 3
.4
8.9.
10 •
.6.7
• 5
I....
eeeQ
Technology, Incorporated
21 20
19 •
18 •
17 •
16.
15.
14 •
14.
13 •
12 •
11 •
.328
"'1
----9--4-4_ _ _ _ _ _ _ _ _ _ _ _ _- - . J
.. .. ... .. .5 4
3 2 1 31 30 29 28
2726
•
25
48F512/47F512
.211
-9
•
24 •
10 1112 13 14 15 16
•• • • • •
17 18 19 20 21 22 •
• • • • • • 23
~r-1------.246------I"~1
seeQ
Technology, Incorporated - - - - - - - - - - - - - - - - - - - - '
9-45
••
7 6
•
••••
••• •• ••
5 4
3 2 1 31 30 29 28 27 26
•
~
8
.211
48F01 O/47F01 0
•109
24
•
·1112 1314 15 16
I
•• • • • •
23
17 18 19 20 21 22 •
• •••••
~1
1'4
........- - - - - - . 2 4 6 - - - - - - - - 1.....
seeG
Technology. Incorporated - - - - 9 - - 4 6 - - - - - - - - - - - - - - - - - '
U.S. Sales Offices
Corporate Sal..
and Marketing
Headquarters
SEEO Technology, Inc.
1849 Fortune Drive
San Jose, CA 95131
Tel: (408) 432-1550
Telex: 296609
FAX: (408) 432-9549
Southwest
Sales Office
SEEO Technology, Inc.
12702 Via Cortina, Suite #201
Del Mar, CA 92014
Tel: (619) 481-4005
FAX: (619) 792-1974
Southern California
Sales Office
SEEOTechnology,lnc.
23101 Lake Center Dr.
Suite 120
EI Toro, CA 92630
Tel: (714) 472-2015
FAX: (714) 472-0835
North Southwest
Sales Office
SEEO Technology, Inc.
5655 Lindero Canyon Road
Building 100, Suite 33
Westlake, CA 91362
Tel: (818) 597-1020
FAX: (818) 706-2910
Northwest
Sal. . Office
SEEO Technology, Inc.
2105 South Bascom Ave.
Suite 185
Campbell, CA 95008
Tel: (408) 371-2100
FAX: (408) 371-1392
Mid-America
Sales Office
SEEO Technology, Inc.
300 Martingale Road
Suite 650
Schaumburg, IL 60173
Tel: (708) 517-1515
FAX: (708) 517-1519
Southeast
Sales Office
SEEO Technology, Inc.
3450 East Lake Road
Suite 206-9
Palm Harbor, FL 34685
Tel: (813) 789-4195
FAX: (813) 787-6290
Northeast
Sales Office
SEEO Technology, Inc.
24 New England
Executive Park
Burlington, MA 01803
Tel: (617) 229-6350
FAX: (617) 273-0322
Authorized North American Manufacturer's Representatives
,Iabama
lep., Inc.
Huntsville, AL
(205) 881-9270
CM Marketing Inc.
Ft. Lauderdale, FL
(305) 722-9369
Vestem High Tech
Scottsdale, AZ
(602) 860-2702
Georgia
Rep., Inc.
Tucker, GA
(404) 938-4358
Atlanta,GA
:alifornla
iaarcom, Inc.
Mountain View, CA
(415) 960-1550
illinois
KMA Sales
Arlington Heights, IL
(708) 398-5300
::olorado
_uscombe Engineering Co.
Longmont, CO
(303) n2-3342
Monument, CO
(719) 481-3001
Indiana
Valentine & Assoc.
Greenwood,lN
(317) 888-2260
South Bend, IN
(219) 288-7070
Florida
eM Marketing Inc.
Clearwater, FL
(813) 443-6390
Sanford, FL
(407) 330-0529
Iowa
Advanced
Technical Sales
Cedar Rapids, IA
(319) 393-8280
~rlzona
Kansas
Advanced
Technical Sales
Olathe, KS
(913) 782-8702
Maryland
New Era Sales
Severna Park, MD
(301) 554-4100
Massachusetts
Compass Technology
Inc.
Wolbum,MA
(617) 933-3336
Missouri
Advanced Tech Sales
St.Louis, Me
(314) 878-2921
Oregon
Electronic Engineering Sales
Portland, OR
(503) 639-3978
New Mexico
Nelco Electronix
Alburquerque, NM
(505) 293-1399
Pennsylvania
Delta Technical Sales
Hatboro, PA
(215) 957-0600
New York
J-Square
Marketing, Inc.
Jericho, NY
(516) 935-3200
Tennessee
Rep., Inc.
Jefferson City, TN
(615) 475-9012
North Carolina
Rep., Inc.
Charlotte, NC
(704) 563-5554
Morrisville, NC
(919) 469-9997
Michigan
A. Blumenberg
Assoc. Inc.
Oak Park, MI
(313) 968-3230
Minnesota
Cahill, Schmitz, & Cahill
St. Paul,MN
(612) 646-7217
Ohio
Omega Sales Inc.
Centerville, OH
(513) 434-5507
Shaker Heights OH
(216) 751-9600
Texas
Southern States
Marketing
Austin, TX
(512) 835-5822
Richardson, TX
(214) 238-7500
Houston, TX
(713) 789-2426
Washington
Electronic Engineering
Sales
Redmond, WA
(206) 883-3374.
Wisconsin
KMASales
Milwaukee, WI
(414) 259-1771
Canada
Electro Source, Inc.
Langley, B.C.
(604) 888-2412
Kanata, Ontario
(613) 592-3214
Pointe Claire, Quebec
(514) 630-7486
Rexdale, Ontario
(416) 675-4490
Utah
Luscombe Engineering Co.
Midvale, UT
(801) 565-9885
Authorized North American Distributors
Arizona
Anthem
TempeAZ
(602) 966-6600
California
Anthem
Chatsworth CA
(818) 700-1000
E. IrvineCA
(714) 768-4444
Rocklin CA
(916) 624-9744
San DiegoCA
(619) 453-4871
SanJoseCA
(408) 453-1200
Zeus Components
Agoura Hills, CA
(818) 889-3838
SanJoseCA
(408) 629-4789
Yorba Linda CA
(714) 921-9000
1/10/89
Colorado
Anthem
Englewood CO
(303) 790-4500
Connecticut
Anthem
MeridianCT
(203) 237-2282
Florida
Zeus Components
Oviedo FL
(407) 365-2356
illinois
Anthem
Elk Grove Village IL
(312) 640-6066
Maryland
Anthem
ColumbiaMD
(301) 995-6640
Zeus Components
ColumbiaMD
(301) 997-1118
Massachusetts
Anthem
Wilmington MA
(508) 657-6008
Zeus Components
Lexington MA
(617) 863-8800
Minnesota
Anthem
Eden Prarie MN
(612) 944-5454
New Jersey
Anthem
Fairfield NJ
(201) 227-7880
New York
Anthem
Commack, NY
(516) 273-1660
Zeus Components
Port Chester NY
(914) 937-7400
Ohio
Zeus Components
DaytonOH
(513) 293-6162
Oregon
Anthem
Beaverton OR
(503) 643-1114
Pennsylvania
Anthem
Horsham PA
(215) 443-5150
9-47
Texas
Anthem
Richardson, TX
(214) 238-7100
Zeus Components
Richardson TX
(214) 783-7010
Utah
Anthem
Salt Lake City UT
(801) 973-8555
Washington
Anthem
Bothell, WA
(206) 483-1n3
Canada
Future Electronics
Calgary, Alberta
(403) 235-5325
Downsview, Ontario
Future Electronics
(416) 638-4n1
Edmunton, Alberta
(403) 438-2858
Ottawa, Ontario
(613) 820-8313
Pointe Claire,
Ouebec
(514) 694-n10
Vancouver,
British Columbia
(604) 294-1166
International Sales Offices
Corporate International
Sales Office
SEEO Technology, Inc.
1849 Fortune Drive
San Jose CA 95131
Tel: (408) 432-1550
TWX: 910-338-2313
Telex: 296609
FAX: (408) 432-9549
Northern European
Sales Office
SEEO International Ltd.
Dammas House
Dammas Lane
Old Town
Swindon SN1 3EF U.K.
Tel: 44 (793) 694999
Telex: 444588
Fax: 44793616201
Central European
Sales Office
SEEO Central Europe
Lussweg 2
8110 Murnau
Federal Republic of Germany
Tel: 49 (8841) 5951
FAX: 49 (8841)5955
Southern European
Sales Office
SEEO International Sari
4 Allee de Pomone, RN13
78100 Saint-Germaine-en-Laye
France
Tel: 33 (1) 30 61 21 23
Telex: 699912
Fax: 33 (1) 30 61 21 92
Far East
Sales Office
SEEO Technology, Inc.
1849 Fortune Drive
San Jose CA 95131
Tel: (408) 432-1550
FAX: (408) 432-1640
Authorized International Manufacturer's Representatives/Distributors
Australia
RAE Industrial
Electronics Pty, ltd.
Austinmer
Tel: (02) 2326933
Perth
Tel: (03) 4702702
Sydney
Tel: (02) 4397599
Melbourne
Tel: (03) 562 2280
Brisbane
Tel: (07) 3575355
Epping
Tel: (02) 868 3022
Austria
Sieg-Electronic
Vienna
Tel: 43 (222) 975626
Belgium
Alcom Electronics B.V.B.A.
Platanenlaan 68
Wilrijk
Tel: 32 (3) 828 38 80
Brazil
Hitech
Sao Paulo
Tel: 55-11 (531-9355)
Denmark
ExatekA.S.
Copenhagen
Tel: 451 191022
Farsoe
Tel: 45 863 3311
Finland
ITT Disti
Helsinki
Tel: 358-90739100
Federal Republic
of Garmany
Astek Electronic
Kaltenkirchen
Tel: 49(4191)80 07-0
Dacom Electronic
Stuttgart
Tel: 49(711 )78068-0
Vertriebs GmbH
Solingen
Tel: 49(212)5930 11
Dacom Electronic
Ismaning
Tel :089-964880
Sarstadt
Tel: 05066-5519
Buxheim
Tel: 49(8458)4003
Karlsruhe
Tel: 49(721)47193
Metronik GmbH
Munich
Tel: 49(89)611080
Hamburg
Tel: 49(40)522 80 91
Stuttgart
Tel: 49(711 )7640 33
Metronik
Dortmund
Tel: 49(231)432037
Numberg
Tel: 49(911 )5900 61
Mannheim
Tel: 49(6203)4701
Darrstadt
Tel: 06151-73050
Hong Kong
Electrocon Products ltd.
KwaiChung
Tel: 0-481602-2
SlngaporelMalaysla
WesTech Electronics Pte., ltd.
Singapore
Tel: (65) 7436355
India
Capricorn Systems
Bangalore
Tel: (0812) 642295
South Africa
Advanced Semiconductor
Devices (PYT) Ltd.
Sandton
Tel: (011) 802-5250
Franca
Radio Television
Francaise (RTF)
Gentilly
Tel: 33(1) 46 6411 01
RTF Composants
Chatillon SIS Bagneux
Tel: 33(1) 49652700
RTF Sud Quest
Escalquens
Tel: 33(61) 81 51 57
RTF Aquitaine
Bordeaux
Tel: 33(56) 52 99 59
RTF Rhone-Aples
Meylan
Tel: 33(76) 90 11 88
RTF Quest
Cesson Sevigne
Tel: 33(99) 83 84 85
RTF Rhone-Auvergne
Venissieux
Tel: 33(78) 00 07 26
RTF Provence
Marseille
Tel: 33(91) 06 0218
Reptronic
Orsay
Tel: 33(1) 69288700
Japan
Japan Macnics
Corporation (JMC)
Kawasaki-City
Tel: (0/44) 7110022
Osaka City
Tel: (0/6) 325 0880
Ireland
Allied Semiconductors
International ltd.
Shannon
Tel: 353 61 617n
Israel
Vectronics ltd.
Herzlia
Tel: (0/52) 556070 or 71
Haly
Moxel
Milano
Tel: 39 (2) 61 29 05 21
NewZaaland
VSI Electronics (N.l.) Ltd.
Epsom Auckland
Tel: 600760
Norway
Exatec. A.S.
Skaarer
Tel: 47 2 972950
Portugal
Teleprinta Lda
Usboa
Tel: 351 (1) 54 84 23
351 (1) 54 89 37
9-48
11/10189
Spain
Semiconductores
Barcelona
Tel: 34 (3) 217 23 40
Semiconductores S. A.
Madrid
Tel: 34 (1) 742 2313
Sweden
Svensk Teleindustri AB
Spanga
Tel: (46) 8761 7300
Taiwan
Bright Up Industries Co., Ltd.
Taipei
Tel: (0/2) n3 2194
Thlaland
Westech Electronics Co., ltd.
Bangkaen
Tel: (662) 511-3308
United Kingdom
Amega Electronics Ltd.
Hampshire, U.K.
Tel: 0256-843166
Pronto Electronic Systems Ltd.
Gants HilVEssex
Tel: (0/1) 554 6222
Yugoslavia
Sieg Electronic - Austria
Vienna
Tel: 43(222) 97 56 26
NOTES
SEEQ Hotline
1-800-3EEPROM
SEEQ Hotline
1-800-3EEPROM
NOTES
NOTES
SEEQ Hotline
1-800-3EEPROM
SEEQ Hotline
1-800-3EEPROM
NOTES
Dear SEEQ ...
Please send me more information. I am interested in:
DEEPROMs
D Military UVEPROMs
D Flash EEPROMs
D Ethernet Data Communications ICs
D SEEQ-LAN Designer Board
My need is:
D Immediate
D Next 3-months D In the coming year
The program is bugetted now, Dyes D no
Please have a - D salesmen, - D application engineer - Deall me.
D Just send more literature
My name Is _ _ _ _ _ _ _ _ _ _ _ _ Title _ _ _ _ _ _ _ __
My company is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Address
City, _ _ _ _ _ _ _ _ _ _ _ _ _ State, _ _ _ _ Zip _ _ _ __
Phone
Fax _______________
Dear SEEQ ...
Please send me more information. I am interested in:
D EEPROMs
D Military UVEPROMs
D Flash EEPROMs
D Ethernet Data Communications ICs
D SEEQ-LAN Designer Board
My need is:
D Immediate
D Next 3-months D In the coming year
The program Is bugetted now, Dyes D no
Please have a - D salesmen, - D application engineer - D call me.
D Just send more literature
My name Is _ _ _ _ _ _ _ _ _ _ _ _ Title
My company Is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Address
City, ______________ State, _ _ _ _ Zip _ _ _ __
Phone
Fax __~_____________
11111
No Postage
Necessary
lfMailed
In the
United States
BUSINESS REPLY MAIL
FIRST CLASS MAIL
PERMIT NO. 7153
SAN JOSE, CA
POSTAGE WILL BE PAID BY ADDRESSEE
seeQ
Technology, Incorporated
1849 Fortune Drive
San Jose, CA 95131
No Postage
Necessary
If Mailed
In the
United States
BUSINESS REPLY MAIL
FIRST CLASS MAIL
PERMIT NO. 7153
SAN JOSE, CA
POSTAGE WILL BE PAID BY ADDRESSEE
seeQ
Technology, Incorporated
1849 Fortune Drive
San Jose, CA 95131
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