1990_Samsung_AHCT_HCTLS_Data_Book 1990 Samsung AHCT HCTLS Data Book
User Manual: 1990_Samsung_AHCT_HCTLS_Data_Book
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Data Book
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AHCT/HCTLS
(High Speed CMOS Logic IC)
1990
INTRODUCTION
Samsung Semiconductor is a broad-line manufacturer of semiconductors that range
from VLSI circuits such as memories (DRAM, SRAM, EPROM and EEPROM),
microprocessors, gate arrays and programmable logic to transistors, linear circuits
and telecommunications products.
The KS54/74AHCT and the KS54/74HCTLS high-performance CMOS logic
families are Samsung's entry into the general purpose digital logic area.
The KS54/74AHCT advanced high-speed CMOS family is designed to provide
performance equivalent to or better than that of the bipolar 54/74ALS (Advanced
Low-power Scholttky) family with the additional CMOS advantages of low power
dissipation and high noise immunity. The AHCT parts can therefore be used as
direct plug-in replacements for their ALS counterparts (and in most applications
for FAST and Schottky) and Improve the system performance.
The 54/74HCTLS high-speed CMOS family offers similar benefits as a replacement for industry-standard 54/74LS (Low-power Schottky), 54/74HCT and
54/74HC. While meeting all of the HCT electrical specifications, it also provides improved speed and drive capability, so that LS parts can be replaced with no performance degradation.
PRINTED IN KOREA
Circuit diagrams utilizing SAMSUNG products are included as a means of illustrating typical
semiconductor applications; conseqLiently, complete information sufficient for construction
purposes is not necessarily given. The information has been carefully checked and is believed
to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
such information does not convey to the purchaser of the semiconductor devices described
herein any license under the patent rights of SAMSUNG or others. SAMSUNG reserve the right
to change device specifications.
High Performance CMOS Logic Data Book
KS54174AHCT
Advanced High-Speed CMOS
KS54174HCTLS
High-Speed CMOS
SAMSUNG
DATA BOOK LIST
I. Semiconductor Product Guide
II. Transistor Data Book
Vol. 1: Small Signal TR
Vol. 2: Bipolar Power TR
Vol. 3: TR Pellet
III. Linear IC Data Book
Vol. 1: Audio/Video
Vol. 2: Telecom/Industrial/TOY
Vol. 3: Data Converter IC
IV. CMOS Consumer IC Data Book
V. High Speed CMOS Logic Data Book
VI. MOS Memory Data Book
VII. SFET Data Book
VIII. MPR Data Book
IX. CPL Data Book
X. Dot Matrix Data Book
TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
7.
Product Guide ......................-................... 11
Parameter Measurement Information .................. 23
Technical Overview ................................... 31
KS54/74AHCT Data Sheets .......................... 57
KS54/74HCTLS Data Sheets ....................... 425
Package Dimensions & Ordering Information ....... 793
Samsung Sales Offices and Manufacturer's
Representatives ....................................... 799
HIGH SPEED
CMOS LOGIC ICs
FUNCTION GUIDE
1. Alphanumeric Index
1) K554174AHCT Family
Device
KS54/7 4A HCTOO
KS54/74AHCT01
KS54/74A HCT02
KS54/74AHCT03
KS54/74AHCT04
KS54/74AHCT05
KS54/74AHCT08
KS54/74A HCT09
KS54/7 4AHCT1 0
KS54/74AHCT11
KS54/74AH9T12
KS54/74AHCT14
KS54/74AHCT20
KS54/74AHCT21
KS54/74A H CT22
KS54/74AHCT27
KS54/74AHCT30
KS54/74AHCT32
KS54/74A H CT 42
KS54/74AHCT51
KS54/74AHCT58
KS54/74AHCT73
KS54/74AHCT74
KS54/74AHCT75
KS54/74AHCT76
KS54/7 4A HCTn
KS54/7 4A H CT78
KS54/74AHCT86
KS54/74AHCT90
KS54/74AHCT92
KS54/74AHCT93
KS54/74AHCT107
KS54/74AHCT109
KS54/74AHCT112
KS54/74AHCT123
KS54/74AHCT125
KS54/74AHCT126
KS54/74AHCT132
KS54/74AHCT133
KS54/74AHCT138
KS54/74AHCT139
KS54/74AHCT148
KS54/74AHCT151
KS54/74AHCT153
KS54/74AHCT154
KS54/74AHCT155
KS54/74AHCT157
KS54/74AHCT158
KS54/74AHCT160
KS54/74AHCT161
KS54/74AHCT162
KS54/74AHCT163
KS54/7 4AH CT164
KS54/74AHCT165
KS54/74AHCT166
Function
Quad 2-lnput NAND Gates
Quad 2-lnput NAND Gates with Open-Drain Outputs
Quad 2-lnput NOR Gates
Quad 2-lnput NAND Gates with Open-Drain Outputs
Hex Inverters
Hex Inverters with Open-Drain Outputs
Quad 2-lnput AND Gates
Quad 2-lnput AND Gates with Open-Drain Outputs
Triple 3-lnput NAND Gates
Triple 3-lnput AND Gates
Triple 3-lnput NAND Gates with Open-Drain Outputs
Hex Schmitt-Trigger Inverters
Dual 4-lnput NAND Gates
Dual 4-lnput AND Gates
Dual 4,lnput NAND Gates with Open-Drain Outputs
Triple 3-lnput NOR Gates
8-lnput NAND Gate
Quad 2-lnput OR Gates
BCD-to-Decimal Decoder
Dual AND-OR-Invert Gates
Dual AND-OR Gates
Dual J-K Negative-Edge-Triggered Filp-Flops with Clear
Dual D-Type Positive-Edge-Triggered Filp-Flops with Preset and Clear
Quad Bistable Transparent Latches
Dual J-K Negative-Edge-Triggered Filp Flops with Preset and Clear
Quad D-Type Latches
Dual J-K Negative-Edge-Triggered Filp-Flops with Preset, Common Clear and
Common Clock
Quad 2-lnput Exclusive-OR Gates
Decade Counters
Divide-by-Twelve Counter
4 Bit Binary Counter Divide by Two and Divide by Eight
Dual J-K Negative-Edge-Triggered Filp-Flops with Clear
Dual J-K Positive-Edge-Triggered Filp-Flops with Preset and Clear
Dual J-K Negative-Edge-Triggered Filp-Flops with Preset and Clear
Dual Retriggerable Monostable Multivibrators
Quad Buffers with 3-State Outputs
Quad Buffers with 3-State Outputs
Quad 2-lnput NAND Gates with Schmitt-Trigger Inputs
13-lnput 'NAND Gate
3-Line to 8-Line DecoderslDemultiplexers
Dual 1 of 4 Decoders/Demultiplexers
8-Line to 3-Line Priority Encoders
1 of 8 Data Selectors/Multiplexers
Dual 1 of 4 Data Selectors/Multiplexers
4·Line to 16·Line Decoders/Demultiplexers
Dual 2 to 4 Line DecoderslDemultiplexers
Quad 2-Line to 1-Line Data Selectors/Multiplexers
Quad 2-Line to 1-Line Data Selectors/Multiplexers
Synchronous 4-Bit Decade Counters
Synchronous 4-Bit Binary Counters
Synchronous 4-Bit Decade Counters
Synchronous 4-Bit Binary Counters
8·Bit Serial·ln/Paralle-Out Shift Registers
8-Bit Parallel-In/Serial-Out Shift Registers
8-Bit Parallel-In/Serial-Out Shift Registers with Clear
c8SAMSUNG
1:'1__ ...__ :_-
I
[
13
HIGH SPEED
F,UNCTION' GUIDE
CMOS LOGIC .ICs
KS54174AHCT Family
(continued)
Function
Device
KS54/74AHCT168
KS54/74AHCT169
KS54/74AHCT173
. KS54/74AHCT174
KS54/74AHCT175
KS54/74AHCT181
KS54/74AHCT182
KS54/74AHCT183
KS54/74AHCT190
KS54/74AHCT191
KS54/74AHCT192
KS54/7 4AH CT193
KS54/74AHCT194
KS54/74AHCT195
KS54/74AHCT210
KS54/74AHCT238
KS54/74AHCT239
KS54/74AHCT240
KS54/74AHCT241
KS54/74AHCT242
KS54/74AHCT243
KS54/74AHCT244
KS54/74AHCT245
KS 54/7 4AH CT251
KS54/74AHCT253
KS54/74AHCT257
KS54/74AHCT258
KS54/74AHCT259
KS54/7 4AH CT266
KS54/74AHCT273
KS54/74AHCT280
KS54/74AHCT299
KS54/74AHCT322
KS54/74AHCT352
KS54/7 4AH CT353
KS54/7 4AH CT365
KS54/74AHCT366
KS54/74AHCT367
KS54/74AHCT368
KS54/74AHCT373
KS54/7 4AHCT374
KS54/74AHCT377
KS54/74AHCT390
KS54/74AHCT393
KS54/74AHCT399
KS54/74AHCT423
KS54/74AHCT465
KS 54/74AH CT466
KS54/74AHCT467
KS54/74AHCT468
KS54/74AHCT518
KS54/74AHCT519
KS54/74AHCT520
KS54/74AHCT521
KS54/74AHCT522
KS 54/74AH CT533
KS54/74AHCT534
KS54/7 4AH CT540
Synchronous 4-Bit Up/Down Decade Counters
Synchronous 4-Bit Up/Down Binary Counters
4-Bit D-Type Registers with 3-State Outputs
Hex D-Type Filp-Flops with Clear
Quad D-Type Filp-Flops with Clear
4-Bit Arithmetic Logic Unit
Look-Ahead Carry Generator
Dual High Speed Adder
Presettable Synchronous BCD Decade Up/Down Counter
Synchronous 4-Bit Up/Down Binary Counters
Presettable Synchronous BCD Decade Up/Down Counter
Synchronous 4-Bit Up/Down Binary Counters with Dual Clock
4-Bit Bidirectional Universal Shift Registers
4-Bit Bidirectional Universal Shift Registers
Octal Butters and Line Drivers with 3-State Outputs
3-Line to 8-Line Decoders/Demultiplexers
Dual 1-of-4 Decoders/Demultiplexers
Octal Butters and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Quad Bus Transceivers with 3-State Outputs
Quad Bus Transceivers with 3-State Outputs
Octal Butters and Line Drivers with 3-State Outputs
Octal Bus Transceivers with 3-State Outputs
1 of 8 Data Selectors/Multiplexers with 3-State Outputs
Dual 1 of 4 Data Selectors/Multiplexers with 3-State Outputs
Quad 2-Line to 1-Line Data Selectors/Multiplexers with 3-State Outputs
Quad 2-Line to 1-Line Data Selectors/Multiplexers with 3-State Outputs
8-Bit Addressable Latches
Quad Exclusive-NOR Gatges with Open-Drain Outputs
Octal D-Type Filp-Flops
9-Bit Parity Generators/Checkers with Clear
8-Bit Universal Shift/Storage Registers with 3-State Outputs
a-Bit Shift Registers with Sign Extend
Dual 4-Line to 1-Line Data Selectors/Multiplexers
Dual 1 of 4 Data Selectors/Multiplexers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Octal D-Type Transparent Latches with 3-State Outputs
Octal D-Type Flip-Flops with 3-State Outputs
Octal D-Type Flip-Flops with Clock Enable
Dual 4-Bit Decade Counters
Dual 4-Bit Binary Counters
Quad 2-Port Registers
Dual Retriggerable Monostable Multivibrators
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
8-Bit Identity Comparators
8-Bit Identity Comparators
8-Bit Identity Comparators
a-Bit Identity Comparators
8-Bit Identity Comparators
Octal D-Type Transparent Latches with 3-State Outputs
Octal D-Type Flip-Flops with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
c8SAMSUNG
Electronics
14
HIGH SPEED
CMOS LOGIC ·ICs
FUNCTION GUIDE
KS54174AHCT Family (continued)
Device
KS54174A HCT541
KS54/74AHCT563
KS54/74A HCT564
KS54/74AHCT573
KS54/7 4AHCT~7 4
KS54/74AHCT590
KS54/74AHCT591
KS54/74AHCT592
KS54/74AHCT593
KS54/74AHCT595
KS54/74AHCT596
KS54/74AH CT597
KS54/74AHCT640
KS54/74AHCT643
KS54/74AHCT645
KS54/74AHCT646
KS54/74AHCT648
KS54/74AHCT651
KS54/74AHCT652
KS54/74AHCT658
KS54/74AHCT659
KS54/74AHCT664
KS54/74AHCT665
KS54/74AHCT670
KS54/74AHCT679
KS54174AH CT680
KS54/74AH CT682
KS54/74AHCT684
KS54/74AHCT686
KS54/74AHCT688
KS54/74AHCT689
KS54/74AHCT793
KS54/74AHCT794
KS54/74AHCT821
KS54/74AHCT822
KS54/74AHCT823
KS54/74AHCT824
KS54/74AHCT825
KS54/74AHCT826
KS54/74AHCT841
KS54/74AHCT842
KS54174AHCT843
KS54/74AHCT844
KS54/74AHCT845
KS54/74AHCT846
KS54/7 4AHCT4049
KS54/7 4AHCT4050
Function
Octal Buffers and Line Drivers with 3-State Outputs
Octal OoType Transparent Latches with 3-State Outputs
Octal OoType Flip-Flops with 3-State Outputs
Octal OoType Transparent Latches with 3-State Outputs
Octal OoType Flip-Flops with 3-State Outputs
8-Bit Binary Counters with 3-State Output Register
8-Bit Binary Counters with 3-State Output Register
8-Bit Binary Counters with Input Register
8-Bit Binary Counters with Bidirectional Input Register Counter Output
8-Bit Shift Registers with Output Latches
8-Bit Shift Registers with Output Latches
8-Bit Shift Registers with Input Latches
Octal Bus Transceivers with 3-State Outputs
Octal Bus Transceivers with 3-State Outputs
Octal Bus Transceivers with 3-State Outputs
Octal 3-State Bus Transceivers with Registers
Octal 3-State Bus Transceivers with Registers
Octal 3-State Bus Transceivers with Registers
Octal 3-State Bus Transceivers with Registers
Octal Bus Transceivers with Parity
Octal Bus Transceivers with Parity
Octal Bus Transceivers with Parity
Octal Bus Transceivers with Parity
4-By-4 Register Files with 3-State Outputs
12-Bit Address Comparators
12-Bit Address Comparators
8-Bit Magnitude Comparators
8-Bit Magnitude Comparators
8-Bit Magnitude Comparators
8-Bit Identity Comparators
8-Bit Identity Comparators with Open-Drain Outputs
Octal Latches with Readback
Octal Registers with Readback
10-Bit Bus Interface Registers with 3-State Outputs
10-Bit Bus Interface Registers with 3-State Outputs
9-Bit Bus Interface Registers with 3-State Outputs
9-Bit Bus Interface Registers with 3-State Outputs
8-Bit Bus Interface Registers with 3-State Outputs
8-Bit Bus Interface Registers with 3-State Outputs
10-Bit Bus Interface OoType Latches with 3-State Outputs
10-Bit Bus Interface OoType Latches with 3-State Outputs
9-Bit Bus Interface OoType Latches with 3-State Outputs
9-Bit Bus Interface OoType Latches with 3-State Outputs
8-Bit Bus Interface OoType Latches with 3-State Outputs
8-Bit Bus Interface OoType Latches with 3-State Outputs
' Hex Inverting Logic Level Down Converters
Hex Logic Level Down Converters
. c8SAMSUNG
Electronics
II
15
HIGH SPEED
CMOS LOGIC ICs
2) KS54174HCTLS Family
(continued)
Function
Device
KS54/7 4H CTLSOO
KS54/74 H CTLS01
KS54/74 H CTLS02
KS54/74 H CTLS03
KS54/74HCTLS04
KS54/74HCTLS05
KS54/74HCTLS08
KS54/7 4H CTLS09
KS54/74HCTLS10
KS54/74HCTLS11
KS54/74HCTLS12
KS54/74HCTLS14
KS54/74HCTLS20
KS54/74HCTLS21
KS54/74HCTLS22
KS54/74HCTLS27
KS54/7 4H CTLS30
KS54/7 4H CTLS32
KS54/74HCTLS42
KS54/74HCTLS51
KS54/74HCTLS58
KS54/74HCTLS73A
KS54/74HCTLS74A
KS54/74HCTLS75
KS54/74HCTLS76A
KS54/74HCTLS77
KS54/74HCTLS78A
KS54/7 4H CTLS86
KS54/74HCTLS90
KS54/74HCTLS92
KS54/74HCTLS93
KS54/74HCTLS107A
KS54/74HCTLS109A
KS54/74HCTLS112A
KS54/74HCTLS123
KS54/74HCTLS125
KS54/74HCTLS126
KS54/74HCTLS132
KS54/74HCTLS133
KS54/74HCTLS138
KS54/74HCTLS139
KS54/7 4HCTLS 148
KS54/74HCTLS151
KS54/74HCTLS153
KS54/74HCTLS154
KS54/74HCTLS155
KS54/74HCTLS157
KS54/74HCTLS158
KS54/74HCTLS160A
KS54/74HCTLS161A
KS54/74HCTLS162A
KS54/74HCTLS163A
KS54/74HCTLS164
KS54/74HCTLS165
KS54/74HCTLS166
KS54/74HCTLS168
Quad 2-lnput NAND Gates
Quad 2-lnput NAND Gates with Open-Drain OutPl4ts
Quad 2-lnput NOR Gates
Quad 2-lnput NAND Gates with Open-Drain Outputs
Hex Inverters
Hex Inverters with Open-Drain Outputs
Quad 2-lnput AND Gates
Quad 2-lnput AN D Gates with Open-Drain Outputs
Triple 3-lnput NAND Gates
Triple 3-lnput AND Gates
Triple 3-lnput NAND Gates with Open-Drain Outputs
Hex Schmitt-Trigger Inverters
Dual 4-lnput NAND Gates
Dual 4-lnput AND Gates
Dual 4-lnput NAND Gates with Open-Drain Outputs
Triple 3-lnput NOR Gates
8-lnput NAND Gate
Quad 2-lnput OR Gates
BCD-to-Decimal Decoder
Dual AND-OR-Invert Gates
Dual AND-OR Gates
Dual J-K Negative-Edge-Triggered Filp-Flops with Clear
Dual D-Type Positive-Edge-Triggered Filp-Flops with Preset and Clear
Quad Bistable Transparent Latches
Dual J-K Ne~ative-Edge-Triggered Filp Flops with Preset and Clear
Quad D-Type Latches
Dual J-K Negative-Edge-Triggered Filp-Flops with Preset, Common Clear and
Common Clock
Quad 2-lnput Exclusive-OR Gates
Decade Counters
Divide-by-Twelve Counter
4 Bit Binary Counter Divide by Two and Divide by Eight
Dual J-!S Negative·Edge-Triggered Filp-Flops with Clear
Dual J-K Positive-Edge-Triggered Filp-Flops with Preset and Clear
Dual J-K Negative-Edge-Triggered Filp-Flops with Preset and Clear
Dual Retriggerable Monostable Multivibrators
Quad Buffers with 3-State Outputs
Quad Buffers with 3-State Outputs
Quad 2-lnput NAND Gates with Schmitt-Trigger Inputs
13-lnput NAND Gate
3-Line to 8-Line Decoders/Demultiplexers
Dual 1 of 4 Decoders/Demultiplexers
8-Line to 3-Line Priority Encoders
1 of 8 Data Selectors/Multiplexers
Dual 1 of 4 Data Selectors/Multiplexers
4-Line to 16-Line Decoders/Demultiplexers
Dual 2 to 4 Line Decoders/Demultiplexers
Quad 2-Line to 1-Line Data Selectors/Multiplexers
Quad 2-Line to 1-Line Data Selectors/Multiplexers
Synchronous 4-Bit Decade Counters
Synchronous 4-Bit Binary Counters
Synchronous 4-Bit Decade Courters
Synchronous 4-Bit Binary Counters
8-Bit Serial-In/Paralle-Out Shift Registers
8-Bit Parallel-In/Serial-Out Shift Registers
8-Bit Parallel-In/Serial-Out Shift Registers with Clear
Synchronous 4-Bit Up/Down Decade Counters
c8SAMSUNG
Electronics
.
16
HIGH SPEED
CMOS LOGIC ICs
FUNcnON GUIDE
KS54174HCTLS Family (continued)
Device
KS54/74 HCTLS 169
KS54/7 4H CTLS 173
KS54/74HCTLS174
KS54/74HCTLS175
KS54/74HCTLS181
KS54/74HCTLS182
KS54/74HCTLS183
KS54/74HCTLS190
KS54/74HCTLS191
KS54/74HCTLS192
KS54/74HCTLS193
KS54/74HCTLS194
KS54/74HCTLS195
KS54/74HCTLS210
KS54/74HCTLS238
KS54/74HCTLS239
KS54/74HCTLS240
KS54/74HCTLS241
KS54/74HCTLS242
KS54/74HCTLS243
KS54/74HCTLS244
KS54/74HCTLS245
KS54/74HCTLS251
KS54/74HCTLS253
KS54/74HCTLS257
KS54/74HCTLS258
KS54/74HCTLS259
KS54/74HCTLS266
KS54/74HCTLS273
KS54/7 4H CTLS280
KS54/74HCTLS299 A
KS54/74HCTLS322
KS54/74HCTLS352
KS54/74HCTLS353
KS54/74HCTLS365A
KS54/74HCTLS366A
KS54/74HCTLS367A
KS54/74HCTLS368A
KS54/74HCTLS373
KS54/74HCTLS374
KS54/74HCTLS377
KS54/74HCTLS390
KS54/74HCTLS393
KS54/74HCTLS399
KS54/74HCTLS423
KS54/74HCTLS465
KS54/74HCTLS466
KS54/74HCTLS467
KS54/74HCTLS468
KS54/74HCTLS518
KS54/74HCTLS519
KS54/74HCTLS520
KS54/74HCTLS521
KS54/74HCTLS522
KS54/74HCTLS533
KS54/7 4H CTLS534
KS54/74HCTLS540
KS54/74HCTLS541
Function
Synchronous 4-Bit Up/Down Binary Counters
4-Bit D-Type Registers with 3-State Outputs
Hex D-Type Filp-Flops with Clear
Quad D-Type Filp-Flops with Clear
4-Bit Arithmetic Logic Unit
Look-Ahead Carry Generator
Dual High Speed Adder
Presettable Synchronous BCD Decade Up/Down Counter
Synchronous 4-Bit Up/Down Binary Counters
Presettable Synchronous BCD Decade Up/Down Counter
Synchronous 4-Bit UplDown Binary Counters with Dual Clock
4-Bit Bidirectional Universal Shift Registers
4-Bit Bidirectional Universal Shift Registers
Octal Buffers and Line Drivers with 3-State Outputs
3-Line to 8-Line Decoders/Demultiplexers
Dual 1-of-4 Decoders/Demultiplexers
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Quad Bus Transceivers with 3-State Outputs
Quad Bus Transceivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Bus Transceivers with 3-State Outputs
1 of 8 Data Selectors/Multiplexers with 3-State Outputs
Dual 1 of 4 Data Selectors/Multiplexers with 3-State Outputs
Quad 2-Line to 1-Line Data Selectors/Multiplexers with 3-State Outputs
Quad 2-Line to 1-Line Data Selectors/Multiplexers with 3-State Outputs
8-Bit Addressable Latches
Quad Exclusive-NOR Gatges with Open-Drain Outputs
Octal D-Type Filp-Flops
9-Bit Parity Generators/Checkers with Clear
8-Bit Universal Shift/Storage Registers with 3-State Outputs
8-Bit Shift Registers with Sign Extend
Dual 4-Line to 1-Line Data Selectors/Multiplexers
Dual 1 of 4 Data Selectors/Multiplexers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Octal D-Type Transparent Latches with 3-State Outputs
Octal D-Type Flip-Flops with 3-State Outputs
Octal D-Type Flip-Flops with Clock Enable
Dual 4-Bit Decade Counters
Dual 4-Bit Binary Counters
Quad 2-Port Registers
Dual Retriggerable Monostable Multivibrators
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
8-Bit Identity Comparators
8-Bit Identity Comparators
8-Bit Identity Comparators
8-Bit Identity Comparators
8-Bit Identity Comparators
Octal D-Type Transparent Latches with 3-State Outputs
Octal D-Type Flip-Flops with 3-State Outputs
Octal Buffers and Une Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
I
17
HI~H SPEED
.
CMOS. LOGIC ICs
FUNCTION GUIDE
KS54174HCTLS Family (continued)
Function
Device
KS54/74H CTLS563
KS54/7 4H CTLS564
KS54f74HCTLS573
KS54f74HCTLS574
KS54f74HCTLS590
KS54f74HCTLS591
KS54f74HCTLS592
KS54f74HCTLS593
KS54f74HCTLS595
KS54f74HCTLS596
KS54f74HCTLS597
KS54f74HCTLS640
KS54/74HCTLS643
KS54f74HCTLS645
KS54174HCTLS646
KS54f74HCTLS648
KS54f74HCTLS651
KS54f74HCTLS652
KS54f74HCTLS658
KS54f74HCTLS659
KS54/74HCTLS664
KS54f74HCTLS665
KS54f74HCTLS670
KS54f74HCTLS679
KS54f74HCTLS680
KS54f74HCTLS682
KS54f74HCTLS684
KS54f74HCTLS686
KS54f74HCTLS688
KS54f74HCTLS689
KS54f74HCTLS793
KS54f74HCTLS794
KS54f74HCTLS821
KS54f74HCTLS822
KS54/74HCTLS823
KS54/74HCTLS824
KS54/74HCTLS825
KS54/74HCTLS826
KS54/7 4~· CTLS841
KS54/74HCTLS842
KS54/74HCTLS843
KS54/74HCTLS844
KS54/74HCTLS845
KS54/74HCTLS846
KS54/74HCTLS4049
KS54/74HCTLS4050
Octal OoType Transparent Latches with 3-State Outputs
Octal OoType Flip-Flops with 3-State Outputs
Octal OoType Transparent Latches with 3-State Outputs
Octal OoType Flip-Flops with 3-State Outputs
8-Bit Binary Counters with 3-State Output Register
8-Bit Binary Counters with 3-State Output Register
8-Bit Binary Counters with Input Register
8-Bit Binary Counters with Bidirectional Input Register Counter Output
8-Bit Shift Registers with Output Latches
8-Bit Shift Registers with Output Latches
8-Bit Shift Registers with Input Latches
Octal Bus Transceivers with 3-State Outputs
Octal Bus Transceivers with 3-State Outputs
Octal Bus Transceivers with 3-State Outputs
Octal 3-State Bus Transceivers with Registers
Octal 3-State Bus Tr.ansceivers with Registers
Octal 3-State Bus Transceivers with Registers
Octal 3-State Bus Transceivers with Registers
Octal Bus Transceivers with Parity
Octal Bus Transceivers with Parity
Octal Bus Transceivers with Parity
Octal Bus Transceivers with Parity
4-By-4 Register Files with 3-State Outputs
12-Bit Address Comparators
12-Bit Address Comparators
8-Bit Magnitude Comparators
8-Bit Magnitude Comparators
8-Bit Magnitude Comparators
8-Bit Identity Comparators
8-Bit Identity Comparators with Open-Drain Outputs
Octal Latches with Readback
Octal Regi.sters with Readback
10-Bit Bus Interface Registers with 3-State Outputs
10~Bit Bus Interface Registers with 3-State Outputs
9-Bit Bus Interface Registers with 3-State Outputs
9-Bit Bus Interface Registers with 3-State Outputs
8-Bit Bus Interface Registers with 3-State Outputs
8-Bit Bus Interface Registers with 3-State Outputs
10-Bit Bus Interface OoType Latches with 3-State Outputs
10-Bit Bus Interface OoType Latches with 3-State Outputs
9-Bit Bus Interface OoType Latches with 3-State Outputs
9-Bit Bus Interface OoType Latches with 3-State Outputs
8-Bit Bus Interface OoType Latches with 3-State Outputs
8-Bit Bus Interface OoType Latches with 3-State Outputs
Hex Inverting Logic Level Down Converters
Hex Logic Level Down Converters
c8SAMSUNG
Electronics
18
HIGH SPEED
CMOS LOGIC ICs
FUNCTION GUIDE
2. Functional Selection Guide
Function
Gates and
Inverters
Buffers
and
Line
Drivers
Level
Shifters
Flip-Flops
Part Number
KS54174AHCT
KS54174HCTLS
00
01
02
03
04
05
08
09
10
11
12
14
20
21
22
27
30
32
51
58
86
132
133
266
125
126
210
240
241
244
365
366
367
368
465
466
467
468
540
541
4049
4050
73
74
76
78
107
109
112
173
174
175
273
374
Description
Quad 2-lnput NAND Gates
Quad 2-lnput NAND Gates with Open-Drain Outputs
Quad 2-lnput NOR Gates
Quad 2-lnput NAND Gates with Open-Drain Outputs
Hex Inverters
Hex Inverters with Open-Drain Outputs
Quad 2-lnput AND Gates
Quad 2-lnput AND Gates with Open-Drain Outputs
Triple 3-lnput NAND Gates
Triple 3-lnput AND Gates
Triple 3-lnput NAND Gates with Open-Drain Outputs
Hex Schmitt-Trigger Inverters
Dual 4-lnput NAND Gates
Dual 4-lnput AND Gates
Dual 4-lnput NAND Gates with Open-Drain Outputs
Triple 3-lnput NOR Gates
8-lnput NAND Gate
Quad 2-lnput OR Gates
Dual AND-OR-Invert Gates
Dual AND-OR Gates
Quad 2-lnput Exclusive-OR Gates
Quad 2-lnput NAND Gates with Schmitt-Trigger Inputs
13-lnput NAND Gate
Quad Exclusive-NOR Gatges with Open-Drain Outputs
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
16
16
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
Quad Buffers with 3-State Outputs
Quad Buffers. with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Hex Bus-Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Octal Buffers and Line Drivers with 3-State Outputs
Hex Inverting Logic Level Down Converters
Hex Logic Level Down Converters
Dual J-K Negative-Edge-Triggered Filp-Flops with Clear
Dual D-Type Positive-Edge-Triggered Filp-Flops with Preset and Clear
Dual J-K Negative-Edge:Triggered Filp Flops with Preset and Clear
Dual J-K Negative-Edge-Triggered Filp-Flops with Preset,
Common Clear and Common Clock
Dual J-.!S Negative-Edge-Triggered Filp-Flops with Clear
Dual J-K Positive-Edge-Triggered Filp-Flops with Preset and Clear
Dual J-K Negative-Edge-Triggered Filp-Flops with Preset and Clear
4-Bit D-Type Registers with 3-State Outputs
Hex D-Type Filp-Flops with Clear
Quad D-Type Filp-Flops with Clear
Octal D-Type Filp-Flops
Octal D-Type Flip-Flops with 3-State Outputs
14
14
20
20
20
20
16
16
16
16
20
20
20
20
20
20
16
16
14
14
16
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
14
14
16
16
16
16
16
20
20
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP·
c8SAMSUNG
Elp-ctronics
Package
19
a
HIGH SPEED
CMOS LOGIC ICs
Functional Selection Guide
Function
Latches
Multiplexers
Shift
Registers
Transceivers
(continued)
Part Number
KS54/74AHCT
KS54/74H cns
Description
Package
377
399
534
564
574
670
794
821
822
823
824
825
826
75
77
259
373
533
563
573
793
841
842
843
844
845
846
151
153
157
158
251
253
257
258
352
353
164
165
166
194
195
299
322
595
596
597
Octal D-Type Flip-Flops with Clock Enable
Quad 2-Port Registers
Octal D-Type Flip-Flops with 3-State Outputs
Octal D-Type Flip-Flops with 3-State Outputs
Octal D-Type Flip-Flops with 3-State Outputs
4-By-4 Register Files with 3-State Outputs
Octal Registers with Readback
10-Bit Bus Interface Registers with 3-State Outputs
10-Bit Bus Interface Registers with 3-State Outputs
9-Bit Bus Interface Registers with 3-State Outputs
9-Bit Bus Interface Registers with 3-State Outputs
8-Bit Bus Interface Registers with 3-State Outputs
8-Bit Bus Interface Registers with 3-State Outputs
Quad Bistable Transparent Latches
Quad D-Type Latches
8-Bit Addressable Latches
Octal D-Type Transparent Latches with 3-State Outputs
Octal D-Type Transparent Latches with 3-State Outputs
Octal D-Type Transparent Latches with 3-State Outputs
Octal D-Type Transparent Latches with 3-State Outputs
Octal Latches with Readback
10-Bit BuS Interface D-Type Latches with 3-State Outputs
10-Bit Bus Interface D-Type Latches with 3-State Outputs
9-Bit Bus Interface D-Type Latches with 3-State Outputs
9-Bit Bus Interface D-Type L~tches with 3-State Outputs
8-Bit Bus Interface D-Type LatchEls with 3-State Outputs
8-Bit Bus Interface D-Type Latches with 3-State Outputs
1 of 8 Data Selectors/Multiplexers
Dual 1 of 4 Data Selectors/Multiplexers
Quad 2-Line to 1-Line Data Selectors/Multiplexers
Quad 2-Line to 1-Line Data Selectors/Multiplexers
1 of 8 Data Selectors/Multiplexers with 3-State Outputs
Dual 1 of 4 Data Selectors/Multiplexers with 3-State Outputs
Quad 2-Line to 1"-Line Data Selectors/Multiplexers with 3-State Outputs
Quad 2-Line to 1-Line Data Selectors/Multiplexers with 3-State Outputs
Dual 4-Line to 1-Line Data Selectors/Multiplexers
Dual 1 of 4 Data Selectors/Multiplexers with 3-State Outputs
8-Bit Serial-In/Paralle-Out Shift Registers
8-Bit Parailel-In/Serial-Out Shift Registers
8-Bit Parallel-In/Serial-Out Shift Registers with Clear
4-Bit Bidirectional Universal Shift Registers
4-Bit Bidirectional Universal Shift Registers
8-Bit Universal Shift/Storage Registers with 3-State Outputs
8-Bit Shift Registers with Sign Extend
8-Bit Shift Registers with Output Latches
8-Bit Shift Registers with Output Latches
8-Bit Shift Registers with Input Latches
20 DIP/SOP
16 DIP/SOP
20 DIP/SOP
20 DIP/SOP
20 DIP/SOP
16 DIP/SOP
20 DIP/SOP
24 DIP/SOP
24 DIP/SOP
24 DIP/SOP
24 DIP/SOP
24 DIP/SOP
24 DIP/SOP
16 DIP/SOP
14 DIP/SOP
16 DIP/SOP
20 DIP/SOP
20 DIP/SOP
20 DIP/SOP
20 DIP/SOP
20 DIP/SOP
24 DIP/SOP
24 DIP/SOP
24 DIP/SOP
24 DIP/SOP
24 DIP/SOP
24 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
14 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
20 DIP/SOP
20 DIP/SOP
16 DIP/SOP
16 DIP/SOP
16 DIP/SOP
242
243
245
640
643
645
646
648
Quad
Quad
Octal
Octal
Octal
Octal
Octal
Octal
14
14
20
20
20
20
24
24
/
·qsSAMSUNG
Electronics
FUNCTION GUIDE
Bus Transceivers with 3-State
Bus Transceivers with 3-State
Bus Transceivers with 3-State
Bus Transceivers with 3-State
Bus Transceivers with 3-State
Bus Transceivers with 3-State
3-State Bus Transceivers with
3-State Bus Transceivers with
Outputs
Outputs
Outputs
Outputs
Outputs
Outputs
Registers
Registers
I
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
20
HIGH SPEED
CMOS LOGIC ICs
FUNCTION GUIDE
Functional Selection Guide (continued)
Function
Counters
Decoders
Encoders
Multivibrators
Arithmetic
Circuits
Part Number
KS54/74AHCT
KS54/74H CTLS
651
652
658
659
664
665
90
92
93
160
161
162
163
168
169
190
191
192
193
390
393
590
591
592
593
42
138
139
148
154
155
238
239
123
423
181
182
183
280
518
519
520
521
522
679
680
682
684
686
688
689
Description
Octal 3-State Bus Transceivers with Registers
Octal 3-State Bus Transceivers with Registers
Octal Bus Transceivers with Parity
Octal Bus Transceivers with Parity
Octal Bus Transceivers with Parity
Octal Bus Transceivers with Parity
Decade Counters
Divide-by-Twelve Counter
4 Bit Binary Counter Divide by Two and Divide by Eight
Synchronous 4-Bit Decade Counters
Synchronous 4-Bit Binary Counters
Synchronous 4-Bit Decade Counters
Synchronous 4-Bit Binary Counters
Synchronous 4-Bit Up/Down Decade Counters
Synchronous 4-Bit Up/Down Binary Counters
Presettable Synchronous BCD Decade Up/Down Counter
Synchronous 4-Bit Up/Down Binary Counters
Presettable Synchronous BCD Decade Up/Down Counter
Synchronous 4-Bit Up/Down Binary Counters with Dual Clock
Dual 4-Bit Decade Counters
Dual 4-Bit Binary Counters
8-Bit Binary Counters with 3-State Output Register
8-Bit Binary Counters with 3-State Output Register
8-Bit Binary Counters with Input Register
8-Bit Binary Counters with Bidirectional Input Register Counter Output
BCD-to-Decimal Decoder
3-Line to 8-Line Decoders/Demultiplexers
Dual 1 of 4 Decoders/Demultiplexers
8-Line to 3-Line Priority Encoders
4-Line to 16-Line Decoders/Demultiplexers
Dual 2 to 4 Line Decoders/Demultiplexers
3-Line to 8-Line Decoders/Demultiplexers
Dual 1-of-4 Decoders/Demultiplexers
Dual Retriggerable Monostable Multivibrators
Dual Retriggerable Monostable Multivibrators
4-Bit Arithmetic Logic Unit
Look-Ahead Carry Generator
Dual High Speed Adder
9-Bit Parity Generators/Checkers with Clear
8-Bit Identity Comparators
8-Bit Identity Comparators
8-Bit Identity Comparators
8-Bit Identity Comparators
8-Bit Identity Comparators
12-Bit Address Comparators
12-Bit Address Comparators
8-Bit Magnitude Comparators
8-Bit Magnitude Comparators
8-Bit Magnitude Comparators
8-Bit Identity Comparators
8-Bit Identity Comparators with Open-Drain Outputs
c8SAMSUNG
Electronics
Package
24
24
24
24
24
24
14
14
14
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
20
16
16
16
16
24
16
16
16
16
16
24
16
14
14
20
20
20
20
20
20
20
20
20
20
20
20
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DI P/SOP')
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
DIP/SOP
21
II
NOTES
,
.~
.
PAR:A,METeR MEASUREMENT INFORMATION
AC SWITCHING TEST CIRCUITS
Totem-Pole Outputs
Vee
DEVICE
UNDER
INPUT
TEST
• CL includes load and test jig capacitance
3-State Outputs
Sf
Vee
DEVICE
UNDER
INPUT
TEST
* CL Includes load and test jig capacitance
Vcc for tPZL and tpLZ measurements
S = GND for tPZH and !PHZ measurements.
st =
Open-Drain Outputs
Vee
DEVICE
INPUT
UNDER
TEST
• CL includes load and test jig capacitance
."
CasSAMSUNG
Electronics
25
PARAMETER MEASUREMENT INFORMATION
TIMING WAVEFORMS
INPUT
--I:'
Propagation Delays
~1~3~ -
1.3V
- lpLH
_ lpHL
-
~
I
IN-PHASE
- -- - - - - - ::
_
I
I
~VOH
11.3V
OUTPUT
I
I
I
I
\1.3V
OUT·OF·PHASE
OUTPUT
VOL
- lpLH ~
-IPHL-:
•
~
V
•
VOL
OH
Setup & Hold Times, Input Rise & Fall Times
-: rio
~ ~t.
2. 7Vl.J------2-.-7v~i.II:° ~ - - - - -- O.3V
1.3V
.V\.--
REFERENCE
INPUT
t.,~.3
o
r-t.ul
2.7V :rt,~O.3V:':
!/'
DATA _2:..:'V
INPUT ~ 1.3V
-- '"-I,
~.;; -- ---
-0 ....
Input Pulse Width
POSITIVE
INPUT _ _ _ _
I'------~-
..Jf 1.3V
3V
ov
3V
ov
If
------
~
I--- Iw - - - -
PULSE
N E G A T I V E - Iw- - - - '
INPUT
\1.3V
PULSE
~
3V
OV
3V
OV
Enable & Disable Time for 3-State Outputs
OUTPUT CONTROL
(Low·level enabling)
OUTPUT
WAVEFORM 1*
\1.3V
OUTPUT _ _ _ _ _,
WAVEFORM 2*
1.3V
* Waveform 1 is for an Qutput with internal conditions such that the output is low except when disabled
by the output control. This waveform is applicable to both 3-state and open-drain outputs.
* Waveform 2 is for an output with internal conditions such that the output is high except when disabled
by the output control.
=8SAMSUNG
Electrbnics
26
PARAMETER MEASUREMENT INFORMATION
DEFINITIONS OF TERMS & SYMBOLS
FUNCTION TABLE SYMBOLS
H
Steady state high level
L
Steady state low level
t
+
Transition from low to high level
Transition from high to low level
X
Don't care (high, low states or transitions)
Z
High-impedance state of a 3-state output
a .. h
I
The level of steady-state inputs at inputs A thru H, respectively
00
Level of 0 before the indicated steady-state input conditions were established
00
Complement of 0 0 or level of Q before the indicated steady-state conditions were established
On
Level of 0 before the most recent active transition indicated by t or
+
I i = One high-level pulse
-u =
TOGGLE· =
One low-level pulse
each output changes to the complement of its previous level on each active transition indicated by
t or +
If, in the input columns, a row contains only the symbols H, L, and/or X, this means the indicated output is valid whenever
the input configuration is achieved and regardless of the sequence in which it is achieved. The output persists so long as
the input configuration is maintained.
If, in the input columns, a row contains H, L, and/or X together with t and/or t, this means the output is valid whenever
the input configuration is achieved but the transition(s) must occur following the achievement of the steady-state levels.
If the output is shown as level (H, L, 0 0 , or 0 0 ). it persists so long as the steady-state input levels and the levels that terminate indicated transitions are maintained. Unless otherwise indicated, input transitions in the oppOSite direction to those
orU, the pulse follows the indicated input transishown have no effect at the output. (If the output is shown as pulse,
tion and persists for an interval dependent on the circuit)
n
DC Characteristics Terms
VIH
High-Level input. voltage
An Input voltage within the more positive (less negative) of the two ranges of values used to represent the binary
variables. A minimum is specified that is the least-positive value of high-level input voltage f.or which operation of the
logic element within specification limits is guaranteed.
VIL
Low-Level input voltage
An input voltage level within the less positive (more negative) of the two ranges of values used to represent the binary
variables. A maximum is specified that is the most-postive value of low-level input voltage for which operation of the
logic element within specification limits is guaranteed.
VOH
High-Level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification, will establish
a high level at the output.
VOL
Low-Level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification, will establish
a low level at the output.
VT+
Positive-Going threshold level
The voltage level at a tranSition-operated input that causes operation of the logic element according to specification
as the input voltage rises from a level below the negative-going threshold voltage, VT -.
c8SAMSUNG
Electronics
'
27
PARAMETER MEASUREMENT INFORMATION
VT-
Negative-Going threshold level
The voltage at a transition-operated input that causes operation of the logic element according to specification as
the input voltage falls from a level above the positive-going threshold voltage, VT +.
10
Output Current
The current into· an output with input conditions applied that, according to the product specification, will establish
a high or a low level at the output.
liN
Input CurentThe current into * an input when a high or a low level voltage is applied to that input.
101
Off-State (high-Impedance-state) output current (of a three-state output)
The current flowing into· an output having three-state capability with input conditions established that, according
to the product specification, will establish the high-impedance state at the output level voltage applied to the output.
This parameter is measured with other input conditions established that would cause the output. to be at a low-voltage
level (if it were enabled) when the externally applied voltage is high; or high-voltage level when the externally applied
voltage is low.
Icc
Supply current
The current into· the Vcc supply terminal of an integrated circuit.
'Current out of a terminal Is given as negative value.
AC CHARACTERISTICS TERMS
tr
Rise time
The time interval between two reference points (10% and 90% unless otherwise specified) on a waveform that is
changing from the defined low level to the high level.
tf
Fall time
The time interval between two reference pOints (90% and 10% unless otherwise specified) on a waveform that is
changing from the defined high level to the defined low level.
.
f max
Maximum clock frequency
The highest rate at which the cock input of a bistable circuit can be driven through its required sequence while main~
taining stable transitions of a logic level at the output with input conditions established that should cause changes
of output logiC level in accordance with the specification.
tpLH
Propagation delay time, low-to-hlgh-Ievel output
The time between the specified reference pOints on the input and output voltage waveforms with the output changing
from the defined low level to the defined high level.
tPHL
Propagation delay time, hlgh-to-Iow-Ievel output
The time between the specified reference pOints on the input and output voltage waveforms with the output changing
from the defined high level to the defined low level.
tpIH
Enable time (of a three-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms with the threestate outputs changing from a high-impedance (off) state to the defined high level.
IpIl
Enable time (of a three-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms with the threestate outputs changing from a high-impedance (off) state to the defined low level.
c8SAMSUNG
Electronics
28
PARAMETER MEASUREMENT INFORMATION
tpHZ
Disable time (of a three-state output) from high level
The time interval between the specified reference pOints on the input and output voltage waveforms with the threestate outputs changing from the defined high level to high-impedance (off) state.
tpLZ
Disable time (of a three-state output) from low level
The time interval between the specified reference points on the input ana output voltage waveforms with the threestate outputs changing from the defined high level to high-impedance (off) state.
tw
Pulse width
The time interval between specified reference points on the leading and trailing edges of the pulse waveform.
tsu
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent active transition
at another specified input terminal.
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by the system
in which the digital circuit operates. A minimum value is specified that is the shortest interval for which
correct operation of the digital circuit is guaranteed.
2. The setup time may have a negative value in which case the minimum limit defines the longest interval
(between the active transition and the application of the other signal) for which correct operation of the
digital circuit is guaranteed.
th
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition occurs at another
specified input terminal.
NOTES: 1. The hold time is the actual time interval between two signal events and is determined by the system
in which the digital circuit operates. A minimum value is specified that is the shortest interval for which
correct operation of the digital circuit is guaranteed.
2. The hold time may have a negative value in which case the minimum limit defines the longest interval (between the release of the signal and the active transition) for which correct operation of the digital circuit
is guaranteed.
CPO
Power dissipation capacitance
Used to determine the no-load dynamic power dissipation per logic function (see individual circuit pages):
= CPD VCC 2f
.
PD
29
NOTES
TECHNICAL OVERVIEW
INTRODUCTION
The 54/74AHCT Advanced High-Speed CMOS and the 54/74HCTLS High-Speed CMOS logic families were designed to
offer the most desirable features of their CMOS and bipolar predecessors. They have the low. power dissipation, superior
noise immunity, wide voltage and temperature ranges and the very low input currents of the other high-speed CMOS logic
families, in addition to the high speed and drive capability of LS and ALS bipolar logic.
The AHCT family is an equivalent of the bipolar ALS and can readily replace ALS in most existing applications to reduce power
dissipation. In many applications, AHCT parts can also be used as replacements for FASTTM and S (Schottky). The HCTLS
parts, on the other hand, meet and exceed all of industry-standard LS and HCT specifications, and can be used as replacements
to these to lower the power dissipation and improve performflnce. The design tips section on page 53 gives speCific details
for direct replacement. Figure 1 shows how AHCT and HCTLS families rank with the other bipolar technologies in terms
of speed and power dissipation.
100
II
80
LOW-POWER TIL
54/74L
~
>::sUJ
30
Q
Z
0
<
r-
.~
m
~
~
TECHNICAL OVERVIEW
The Samsung CMOS logic families include a comprehensive set of buffers, registers, latches and transceivers that are offered in 8, 9 and 1 O-bit versions. A wide variety of gates, f/ip4 flops, multiplexers, shift registers, encoder/deco~ers, schmitt
triggers and multivibrators complete the family of :157ipart types. Each function is available in both AHCT and HCTLS version.
Characteristic
Symbol
Conditions
Ta=25°C
Typ
Commercial
Military
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum
High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Minimum
Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vcc- 0 .1
Vcc- O. 1
CMOS loads
Minimum
High-Level
Output Voltage
VO H
VIN = VIH or VIL Standard Outputs
IOH=-4 mA
I--Bus-Driver Outputs
IOH=-6 rnA
VOL
VIN = VIH or VIL
V
4.2
3.98
3.84
3.7
4.2
3.98
3.84
3.7
0.1
0.1
0.1
0.1
Standard Outputs
IOL=4 mA
IOL=8 mA
0.2
0.3
0.26
0.39
0.33
0.5
0.4
Bus-Driver Outputs
IOL=12 mA
10L =24 mA
0.2
0.3
0.26
0.39
0.33
0.5
0.4
V
CMOS loads
IOL =20 /-IA
Minimum
Low-Level
Output Voltage
Vcc Vcc- 0 .1
IOH=-20/-iA
V
Maximum Input
Leakage Current
II
Vcc=Max, VIN=VCC or GND
±0.1
±1.0
1.0
/-I A
Maxinium 3-State
Leakage Current
loz
Vcc=Max, Enable=VIH or VIL
VOUT=VCC or GND
:1:0.5
*5.0
±10.0
/-I A
SSI Circuits
2.0
20.0
40.0
Dual and Quad
Flip-Flops & Latches
4.0
40.0
80.0
MSI Circuits &
Circuits with
High-Current Outputs
8.0
80.0
Maximum
Quiescent
. Supply Current
Icc
Vee = Max
VIN=VeC or
GND
All Outputs
Open
/-IA
160.0
FIGURE 3. DC characteristics of the 54/74AHCT and 54/74 HCTlS Families (Vcc=5.0V :!:10%)
c8SAMSUNG
CIft.I'+""'l"'Ioi,..~
35
I
TEC.HNICAL OVERVIEW
P~OCESSTECHNOLOGY
The high performance of the AHCT and HCTlS is a result of a unique self-aligned metal-gate CMOS process technology
that features 1.2101m effective gate lengths and double metallization. The following table compares the general characteristics
of this process with other existing CMOS and bipolar technologies used for logic circuits:
SAMSUNG CMOS
INDUSTRY CMOS (HC & HCT)
INDUSTRY ALS
Number of Masking Steps
8
12-14
13
Number of Metal Layers
2
1
2
2 101m
3-4 101m
4 101m
All Metal
Poly & Metal
All Metal
Minimum Feature Size (drawn)
Interconnections
Relative Die Size
Manufacturing Equipment
1X
2.5-5X
1.5-2X
Standard
Standard
Standard
Samsung's CMOS process was designed from the ground up to be a scaled two-layer metal CMOS process (see Figure
4 for a cross section). The goal was to make the process as simple as possible, and be able to readily control gate length
and gate dielectric thickness. The process uses 8 masking steps. Other semiconductor manufactures, in trying to go to
two-layer metal short-channel processes have generally embellished pre-existing silicon-gate processes and have wound
up with 12-14 masking steps. More masking steps, of course, make wafers more costly, but most importantly, reduce yield
because of more chances for random defects.
DIELECTRIC LAYERS
METAL LAYER 2
N-CHANNEL TRANSISTOR
METAL LAYER 1
P-CHANNEL TRANSISTOR
P-WELL
N-SUBSTRATE
FIGURE 4 .. Samsung CMOS process cross section for an inverter stage
The Samsung process, with the short 2 101m channel lengths (1.2 101m effective), yields gate delays as fast as those of the
bipolar lS and AlS processes, and the same short channel lengths allow high-current output drivers to occupy a modest
silicon area. Generally, the AHCT and HCTlS logic chips are much smaller than their CMOS and bipolar equivalents (see Figure
5). In achieving this small size, two-layer metal is as important as having short channels. For example, in the on-chip busing
of ground and Vcc to the output drivers, very wide metal lines have to be used that take considerable area. In this case,
if these lines are in Metal 2, no extra area is wasted since the circuitry can be placed underneath.
c8SAMSUNG·
Electronics
36
TECHNICAL OVERVIEW
2.57X
MM74HC240
National Semiconductor
1.42X
74F240
Fairchild
1.S7X
SN74ALS240
Texas Instruments
II
1X
KS74AHCT240
KS74HCTLS240
Samsung
FIGURE 5. Die size compar ison for a 74XXX244 from various technologies.
INPUT CHARACTERISITICS
The input stage of an AHCT or HCTLS circuit is illustrated in Figure 6. It consists of a diode protection network and a CMOS
inverter stage that has very high input impedance. The ultra-low input current specified in the data sheets (1 ",A maximum) is
due to the reverse leakage currents of the diodes and is not used for "driving" the CMOS transistors i.e. the inputs are
voltage-driven. This makes AHCT and HCTLS inputs very easy to drive and results in a very high fan-in capability.
TTL-compatible input threshold voltages of O.8V VIL and 2.0V VIH are accomplished by properly sizing the p- and n-channel
transistors of the CMOS inverter stage. The actual logic transition takes place mid-way between these values, at 1.4V, and
is very sharp compared to TTL logic due to the very high gain of the first inverter stage. This is illustrated in Figure 7 for
a two-input NAND gate. Note that the input threshold for CMOS is much more stable with temperature than that for LS.
While the AHCT and HCTLS parts are recommended as direct replacements for ALS and LS, one needs to pay attention
to not leaving any inputs floating, i.e. unconnected. Since the inputs have very high impedance, they can easily pick up
external noise which can result in random switching of the device and high power consumption. Therefore, all unused inputs
must be terminated to either Vce or ground.
c8SAMSUNG
Electronics
37
TECHNICAL OVERVIEW
Vee
P
Input o---+---~'----..---"
Pin
FIGURE 6. The input circuit of AHCT and HCTlS parts.
--....-'!. . .-;---;---r--,---.
5.0 ...
5.0
V~e=5.0V
4. 0 1 - - - - t - 1 f H - - i - - - - - 1 i - - - - - 1 - - - - I
J.- Taj125°C
~
~
~
~
~ 3.0
~
~
f:J
§
4.0
UJ
j.-Taj25°C
3.01----+-IHt:::o:I' Ta= -55°C -+----+---~
~ 2.
2.0
5
1.01----+--'1-H--+----+----1-------I
V~e=5.0V
~
,1\
-~
T.=125°C
T.==25°C
l-rT.=-~5°C
1. 0
I
1.0
2.0
3.0
INPUT VOLTAGE
{al
3.0
5.0
1.0
2.0
3.0
5.0
INPUT VOLTAGE
(bl
FIGURE 7. Input-Output transfer characteristics for {a) AHCT/HCTLSOO, (b) LSOO.
c8SAMSUNG
Electronics
38
TECHNICAL OVERVIEW
OUTPUT CHARACTERISTICS
A typical output stage of an AHCT or HCTlS part consists of a complementary pair of transistors and a diode protection
network (see Figure 8). Unlike the bipolar outputs, the voltage swing is rail-to-rail, which is responsible for the improved
noise margine of AHCT/HCTlS systems. The drive capability of these outputs is similar to the bipolar parts, i.e. 24mA or
8mA 10L (at 0.5V Vod for bus-driver and standard outputs, respectively. This meanS that AHCT and HCTlS parts can drive
as many loads or as large bus capacitances as their ALS and lS counterparts. Figure. 9 shows a comparison of the output
drive capabilities of AHCTIHCTlS and lSI ALS outputs. Figure 10 illustrates the variations of 10L and IoH with supply voltage
and temperature for a standard output ('00) and a bus driver ('244).
vee
t----....----<)
II
OUTPUT PIN
FIGURE 8. A typical output circuit of an AHCT or HCTLS part.
The upper diode is parasitic and embedded in the p-channel transistor.
0
.s« -10
70
T.=25°C
Vee=5V
60
«
I-
.s
Z
w
a:
§
I-
z
-20
UJ
a:
a:
()
w
::l
()
()
§ -30
~
z
0
en
en
l-
I-
ir
-40
l-
I-
0
0
::l
a.
::l
::l
-50
20
10
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
5.0
5.0
OUTPUT VOLTAGE (V)
FIGURE 9. Comparison of standard AHCT/HCTLS and standard LS output (a) Source, and (b) sink currents.
=8 !e!"SUNG
39
"tECHNICAL OVERVIEW
10H(mA)
loL(mA)
100
Ta=~5:C
90
80
V
70
V
60
/
---
l
V.
,.0~
-20
-30
Vee~ ~
Vee~ ~
I
20
I~ ~
Vee=4.5V
V
30
A"
-10
Vee~
I~V
40
~
T.=~5OC
Vee=5.5V
I~ /
50
10
o
l
1
Vee=~
74AHCTOO _
CTL O
7r
r
/
-40
V
/ ' ~ ~/
/
V.
./' "'/"
V
"""
74AHCTOO _
74tCTLioO
V
VodV)
5
-50
Vee 5
VOH(V)
Vee-4
Vee 3
(a)
200
Ta=125°C
-10
Vee=t5V
160
~V
~
....l/ . /V
140
120
I~V
100
~V
80
o
V ...
V
A'
-20
~
Vee=
10- +--
-30
~.5V
/
-40
-70
74AHCT244 _
j, ~
-8 0
741CTLsr4
~W
~
~V
V
-50
-60 r v e R
I~V
I
T.=~5OC
Vee=5~
~~ V
V ~v
V
L ~v
~V
74AHCT244
v~V-
5 VodV)
-10 0
Vee-5
VOH (V)
Vee- 4
(e)
Vee -3
Vee -2
o
Vr;c
J
),
Vee~5.0V
90
v: --
80
70
60
Ja=-5'5..-.
C
0
I---
~
-10
Ta=125°C
-20
~V
-30
II '/
rtf
JV
/~
./ ~
Ta=25°C
~V/ V
50
10
1
loH(mA)
V~=5.0~
20
Vee
(d)
lot. (rnA)
100
30
-
74iCTLSr4-
-90
0"
40
Vee
(b)
180
0
Vee 1
10H (rnA)
10L(mA)
60
Vee 2
74AHCTOO
-4()
.,,/ ~V
-
~V L ~
flOC
V
flOC ~
~
r--- ~~
74AHCTOO _
7rCTLiOO-
If
74tCTLiOO
VOL(V)
-50
VOH (V)
5
(e)
c8SAMSUNG
Electronics
5
(I)
40
TECHNICAL OVERVIEW
loH(mA)
loL(mA)
200
Vcc l5 .oV
180
-10
T:=-5;OC
160
,
140
I"
1/
100
"..
80
~V
60
20
-40
T:=12;OC
/~V
-50
.,.
-60
Ta=~25~
74AHCT244
~~
J/I
)(jJ
-30
-70
~V
40
--
J
J
-20
~25ob
, ......... ~
L lLl"
JV ~
120
.........
VCC~5.0V
-80
7rCTli244
LV ~ /
Ta=2~ ~ .,/
Ta~
74AHCT244 _
74HCTLS244
I
-90
/
-
......... . /~V
I
-100
5 Vc>JV)
(h)
(g)
II
FIGURE 10. Output current variations with supply voltage and temperature for standard [(a), (b), (e) (f)] and
bus driver [(c), (d), (g), (h)] outputs.
NOISE IMMUNITY & NOISE MARGINS
The term "noise" in the context of digital circuits and systems means unwanted transient variations of voltages and currents
at logic nodes. Typically noise is transferred to logic nodes or interconnecting lines by unwanted capacitive or inductive
coupling, as illustrated in Figure 11.
Mutual inductance
/ . with another
~
logicnode
external sources
Inductive and
resistive drops
Capacitive coupling
from another node
FIGURE 11. Sources of noise in digital systems.
Noise becomes a particularly critical issue in high-speed systems where fast voltage transitions accentuate these parasitic
capacitances and inductances. Also, higher speeds allow the device to respond more quickly to noise transients. Therefore,
special board layout and decoupling techniques have to be employed to confine noise to an "acceptable range". Obviously,
the wider this range, the easier it is to design a clean system. This range is dictated by the input and output characteristics
of the les in the system, as illustrated in Figure 12, and is measured in terms of "noise margins".
=8SAMSUNG
Electronics
41
TECHNICAL OVERVIEW
OUTPUTS
signal~
The output
should be Vee
as close to the supply rails
VOH
as possible. This allows
more margin for noise to
distort the output signal
without violating the logic
level requirements of the
driven inputs.
A A 1 ,L A.
--ly vyHI('-
The voltage range for each
logic level should be as wide
as possible. This relaxes the
requirements for the cleanliness
of incoming signals.
VOl~
I
GND
FIGURE 12. Requirements for good noise immunity.
Noise margins specify the maximum amplitude noise pulse that will not change the state of a driven stage, assuming the
driving stage presents a worst-case logic level to the driven stage. Specifically, the high-level and the low-level noise margins
(NMH and NMd are defined as:
NMH=VOH - VIH,
NML =VIL - VOL,
where the voltage values are the guaranteed worst-case extremes for each case. Figure 13 shows the noise margins f,or
several different interfaces.
TTL to TTL
or
Interface
5V
4.75
4.5
4.4
AHCT to AHCT,
ACHT TO TTL,
HC to AHCT
HC to HC
AHCT to HC
3.15
2.7' ,
2.0
1.35
0.8
OA'
0.1
FIGURE 13. Noise margins for various interfaces. Noise margins for HCTLS are tbe same as those for AHCT.
* When an AHCT output drives TIL loads the VOH level will be dependent on how many
loads are driven. For example if an AHCT244 drives 60LS loads, the VOH will rise to
O.4V
For some, TIL\parts, VOH is 2.4V, instead of 2.7V
c8SAMSUNG
Electronics
42
TECHNICAL OVERVIEW
It is immediately obvious that the TTL-to-TTL interfaces have the poorest noise immunity and those driven by CMOS have the
best. This is due to the rail-to-rail voltage swings of CMOS outputs.
Note the HC logic has almost symmetrical noise margins while AHCT (or HCTLS) has a very large noise margin for high
level and a smaller low-level one. This is due to the fact that AHCT (or HCTLS) inputs are designed for direct interface with
TTL and NMOS outputs as well as other CMOS. Notice, however, that the low-level noise margin (NMd for AHCT is only
0.1 V less than that for HC, which means that it provides nearly as much immunity to ground noise. In addition, since AHCT
drive capability is two to four times better than HC, it is less susceptible to noise currents coupled to its outputs. That is,
lower stray voltages are induced for a given amount of current coupling than for HC.
ESO PROTECTION
Historically, MOS devices have always been considered to be more susceptible to damages due to electrostatic discharges
(ESD), which can occur during handling and assembly procedures. However, the new protection circuitry, design, and special
processing used for AHCT and HCTLS have improved the ESD immunity for these devices where it is now much better
than that of bipolar logic.
Figure 6 and 8 show the input and output ESD protection circuitry employed. All AHCT and HCTLS pins are protected to
ESD levels typically greater than±2kV, the tests are conducted using the "human-body" model that is shown in Figure 14.
10MQ
II
1.5KQ
Of--------4\jIl,/"'ftI!I---~-
To Device
Under Test
High
Voltage
Supply
FIGURE 14. Test circuit used to measure ESD damage in AHCT and HCTLS circuits.
LATCHUP CHARACTERISTICS
SCR iatchup is an undesirable parasitic phenomenon which is inherent in circuits fabricated using bulk CMOS technology.
A parasitic four-layer (P-N-P-N) SCR structure that appears between Vce and ground can be triggered when voltages greater
than Vcc or less than ground are applied to inputs or outputs. When this happens, Vec gets effectively shorted to ground,
and the only way to get the device off the latchup mode is to shut off the power supply. If large currents are allowed to
flow through the chip, it may be destroyed. Samsung CMOS logic parts have been designed and processed to virtually
eliminate this possibility in real-life situations where voltages out of the supply range many appear at the input or output pins
(overshoots, undershoots, power-up & power-down situations).
=8SAMSUNG
Electronics
43
TECHNICAL OVERVIEW
GND
Vee
FIGURE 15. Simplified cross section of a CMOS inverter
Vee
---~Es
Rs
GND
FIGURE 16. CMOS SCR structure
GATE 1
N
A-"----+--- GATE 2
GATE 2
GATE 2
GATE 1
N
-_----c
FIGURE 17. Simplified four layer SCR structure
c8SAMSUNG
Electronics
44
TECHNICAL OVERVIEW
The parasitic SCR structure in a CMOS inverter cross section is illustrated in Figure 15, where vertical and lateral NPN and
PNP transistors are formed back-to-back by the Nand P diffusions. RA and Rs are the P-well and the N-substrate power
supply connections. Figure 16 is a schematic representation of this par~sitic structure that looks like a cross-coupled transistor model of an SCR (Figure 17). The exceptions are the RA and Rs resistors and the fact that the real SCR is triggered
at the gates, while the CMOS parasitic SCR is triggered at its emitters. This happens when either the EA is raised above
Vcc enough to turn on OA, or Es is lowered below ground enough to turn on as. When EA is brought above Vcc, current
is injected from the emitter of OA and is swept to its collector. This current, in turn, will increase the voltage at the Os gate
and once it is above O.7V, Os will turn on and feed current from its collector back into RA and into OA. When O.7V drop
appears across RA, OA will turn on even more.
If the two transistors have enough gain and enough current is provided by the supply to sustain the SCR, it will turn on
and remain on even after EA and Es are returned to the rail voltages. Notice that low resistor values effectively reduce
the gain of the transistors by stealing current away from their bases. Therefore, transistors should actually have much higher
gains in order to have an overall SCR loop gain greater than one and enable SCR to trigger.
Samsung CMOS logic parts are designed and processed to have very low RA, Rs values and low gains for the parasitic
transistors. In addition, large diodes exist between each Signal pin and the supply rails to shunt out voltages above Vcc
and below ground. In fact, traditionally, one refers to the current that flows through these diodes as the element that triggers
latchup, i.e. we talk of "Iatchup trigger currents", not voltages.
Measured on a static basis, i.e. by applying DC voltages above Vcc and below ground, Samsung parts can withstand currents typically well above 200mA-even under the worst-case conditions of 7V Vcc and +125°C operation. Figure 18
illustrates the test set-up used for static latchup tests.
A common occurence of v'lltages above Vcc and below ground in systems is overshoots and undershoots that are caused
by signal line ringing and power supply transients. '" this case, unlike the static operation, only short pulses cause forwardbias diode currents and hence possible latch-up. It turns out, fortunately, that the parasitic SCR has extremely slow response
time to transients, i.e. very poor frequency characteristics. Figure 19 shows the increased peak currents required to latch
an AHCT or HCTlS device up when the pulse width is decreased. For pulse widths in the range of several tens of nanoseconds,
it is virtually impossible to latch the device up.
vee DIODE TEST CIRCUIT
GROUND DIODE TEST CIRCUIT
A
vee
+
-=-
'---tr-lf--+- INPUT OR
OUTPUT
,
INPUT OR
OUTPUT
7V
~
7V-="
GND
OUT
T.=25·C
FIGURE 18. Test setup for measuring DC latch-up
c8SAMSUNG
Elp-ctrnnics
45
II
TECHNICAL OVERViEW
800
C(
.§..
~
(..l
700
600
Co
=?
~
n
"-
500
'" '"
---l
Vcc=7.0V
T.=25°C
L_
--jtpwr-
~
~
'"
~
-r-----
400
300
0.2
0.4
0.6
0.8
1.0
Pulse Width (ms)
FIGURE 19. Pulsed latch-up characteristics
POWER DISSIPATION
low power dissipation is by far the most important advantage of CMOS over any other technology. Particularly in the quiescent state, the AHCT and HCTlS circuits consume up to seven orders of magnitude less power than the equivalent TTL
functions. This makes them ideal for battery-operated or ultra-low power systems where the system may be put to "sleep"
by shutting off the system clock.
The dynamic power dissipation, however, depends on:
1. Cross-over currents of the internal CMOS transistors,
2. InternallQad capacitances,
3. External load capacitances, and
4. Input voltage levels.
All of the above add up every time there is a logic transition and dynamic power dissipation is the sum of these contributions
averaged at a given operating frequency. A practical formula is developed to calculate the dynamic power dissipation (PD)
resulting from the first three items: (input voltage transitions are rail-to-rail)
PD=(CL +CPD) Vcc 2 f,
where CL is the load capacitance; CpD is the "internal power dissipation capacitance", Vcc is the supply voltage and f is
the operating frequency. The CPD value, as specified in each data sheet, sums up the contributions of the first two factors
(crossover currents and internal load capaCitances) as a capacitance value for purposes of this calculation. The equation
indicates that the dynamic power dissipation is directly proportional to frequency.
The contribution of the fourth factor listed above, the input voltage levels, can also be significant when AHCT or HCTlS
inputs are driven by TTL outputs. Figure 20 shows the typical crossover currents generated at the input inverer stage as
the input voltage swings from 0 to Vcc. This is because both the n-channel and the p-channel transistors turn on partially
and provide a low-resistance current path between Vec and ground when tne input voltage is near the threshold voltage
of the complementary pair. At 2. 7V, which is the worst cas~ VOH for TTL parts, the Icc can be as high as O.5mA per input.
This has to be taken into account when calculating the worst-case power dissipation of an AHCT or HeTlS part operating
in a TTL environment.
c8SAMSUNG
Electronics
46
TECHNICAL 'OVERVIEW
Figure 21 shows the internal power dissipation for an AHCT244 (same for HCTLS244) and compares it with the dynamic
power dissipation for LS, ALS and F244. It can be seen that the curves for the bipolar parts are essentially flat for frequencies
up to 1 MHz where the quiescent currents mask out the dynamic effects. However, as the frequency goes up, the currents
that charge the internal capacitances start adding to the quiescent currents and increase the overall power dissipation. The
AHCT244 driven by worst· case TTL voltage levels (all inputs, 50% duty cycle) displays a similar trend but still dissipates
an order of magnitude less power than the lowest· power TTL. When CMOS input voltage levels are used, however, the
power dissipation is directly proportional to frequency as predicted by the above mentioned formula, and is less than
those for the TTL parts, Although the power dissipation becomes comparable to ALS levels at around 10MHz, a crossover
does not happen below 50MHz, which is already beyond the maximum clock frequencies of most systems. This behaviour
is pretty much the same for all parts in the AHCT and HCTLS families.
In calculating the power dissipation of a system, however, note that only a small percentage of the devices operate at the
maximum clock frequency while others operate at a fraction of that. Therefore the average operating frequency tends to be
much lower where CMOS has a clear advantage.
IcdmA)
I
II
5000
I
Vcc=4.5V _ Ta=25°C
Vcc =5.0V
-
Ta=25°C
500
2.0
74F244
~
Eo:
UJ
1.0
:s:0
\
c..
l\.
)
V
0.0
1.0
0.5
~
2.0
"-
~
3.0
V'N(V)
4.0
5.0
FIGURE 20. Typical crossover current of an AHCT
or HCTLS input.
'c8$A~SUNG
0.05
lK
100M
FIGURE 21. Typical dynamic power consumption
(no-load) of the 74XXX240 octal buffer
with all inputs toggling.
47,
TECHNICAL OVER,EW
AC CHARACTERISTICS
All AHCT and HCTLS parts are designed to meet or exceed the ALS and LS propagation delay specifications, respectively.
Coupled with the equivalent drive capability, this makes them ideal replacements for the ALS and LS in existing designs.
In addition the AC specifications for AHCT and HCTLS parts are improved to reflect more realistic design situations. First
of all, unlike LS, the AHC"T & HCTLS propagation delays are specified with a 50pF load for all part types and guaranteed
over the entire voltage and temperature ranges (5V ± 1 0%, - 40 ° C to + 85 ° C). Standard LS propagation delays are specified
with a 15pF load and guaranteed only at room temperature and 5V Vcc. In addition, all bus drivers specify the propagation
delays with a 150pF load capacitance to enable the designer to predict a worst-case maximum speed degradation due to
capacitive loading.
The effect of the supply voltage variations on propagation delay is illustrated in Figure 22 for a bus-driver (AHCT244). It
can be seen that the parts are functional over a very wide range of voltages and that they slow down as Vcc goes down.
Howejer, propagation delays are specified and guaranteed only over the 4.5 to 5.5V range.
Figure 23 shows the effect of temperature on the propagation delays for the same part. As for' all CMOS circuits, AHCT
and HCTLS parts slow down as temperature goes up. Typically speeds derate linearly from 25°C at about 0.02 ns/oC.
The propagation delay at any temperature (between -55°C and + 125°C) can therefore be calculated using the following
formula:
tpD (T)=tPD (25°C)+kT (T -25°C)
where:
tpD (T)=Propagation delay at the desired T temperature,
tPD (25°C)=Propagation delay at 25°C,
kT=Temperature derating factor=0.02 ns/oC
The effect of capacitive loading of the outputs on the propagation delay is illustrated in Figure 24: the higher the load capacitance,
the slower the propagation delay gets. To determine the maximum limit for propagation delay at any value of capacitive loading'
up to 500pF, the following equation is used:
tpD (CLl=tpD (50pF)+kc (Cl -50pF)
where:
tpD (CLl=Maximum propagation delay at the desired Cl,
tpD (50pF)=Maximum propagation delay from device data sheet,
kc=Maximum multiplicative factor (ns/pF):
• 0.04 for standard outputs, and
• 0.02 for bus-drivers.
tpD (ns)
tpo (ns)
I
Ta =J5 0 C._
CL =50pF
30
18 t----t--+--+--+------jr___-I---+---t Vee =4.5V
CL =50pF
16t----t--+--+--+-~r___-I---+--_t_-r__4
14t----t--+-4--+-~~-+-~-+_-~~
20
10
""
12t----t--+--+--+-~r_-I---+--_t_-r__4
10t----t--+--+--+-~r_-+--+--_t_-r_~
Specified
Operating Range
~
.......
~
...........
......... ""'-
4t----t--+--+--+-~~_+-_+_-_t_-r__;
VedV)
2
3
4
5
FIGURE 22. Propagation delay versus supply voltage
for an AHCT244.
'.: c8SAMSUNG
Electronics
-55 -35 -15 -5
25
45
65
85
105 125
T.(OC)
FIGURE 23. Propagation delay versus ambient
temperature for an AHCT244.
48
TECHNICAL OVERVIEW
tpo (ns)
tpo (ns)
Ta =d5 0 C
Vcc=4.5V
30
Ta =d5 0 C
Vcc =4.5V
30
VIV
./
20
~
10
V
V
./
20
./
.".,.10
/"'"
o
50
100 150
200 250
300
350 400
450
Cc(pF)
o
---50
~
100
~
150
"..-
-'
" . ,".-
-----
200
(a)
250
300 350
400 450
Cc(pF)
(b)
FIGURE 24. Propagation delay versus capacitive load for a (a) standard output (HCTLSOO),
(b) bus-driver output (HCTLS374)
INTERFACING 54174AHCT AND 54174HCTLS
WITH OTHER LOGIC FAMILIES AND LOADS
Speed and power, while paramount in the initial choice of a logic family, are not the only basis of decision. Another very
important factor is the interface flexibility: the inherent capacity of a family to interface with other types of logic and to drive
various loads. The Samsung CMOS logic families have this very attractive feature that they can easily be interfaced to all other
kinds of digital logic with minimal or no external components.
AHCT and HCTLS parts can be coupled directly with all other TTL, NMOS and CMOS parts if they operate from the same
supply voltage. The list includes Standard TTL, Schottky(S), Low-Power Schottky(LS), Advanced Low-Power Schottky(ALS),
Advanced Schottky (AS and FAST); all industry-standard CMOS logic families (HC, HCT, CD4000, 14000); all bipolar, NMOS
and CMOS microprocessors, microcontrollers, peripherals and memory circuits (see figure 25). This is due to the TTl·compatible
input voltage levels coupled with CMOS (rail·to-rail) output voltage swings.
Interface with ECl logic, however, requires external components as shown in Figure 26.
Methods of interfacing with standard CMOS logic families (4000 and 14000), when supply voltages are different, are il·
lustrated in Figure 27 and 28.
Standard TTL
s
LS
ALS
FAST
AS
HC
HCT
NMOS
CMOS (5V)
OUTPUTS
Vcc=5V
Vcc=5V
·1
1
-..,
-.L
AHCT
or
HCTLS
AHCT
or
HCTLS
INPUTS
OUTPUTS
-L
Standard TTL
S
LS
ALS
FAST
AS
HC
HCT
NMOS
CMOS (5V)
INPUTS
FIGURE 25. Interfacing with TTL, NMOS and other CMOS logic. No extra components are needed.
c8SAMSUNG
Electronics
49
I
TECHNICAL OVERVIEW
5V
r---'--..;;.......... 101251
f}
5V
10525
Inputs
Outputs 1 - - - - - 1 "
AHCT
or
HCTlS
ECl
System
..,
AHCT
or
HCTlS
.......1
ECl
INPUTS
OUTPUTS
Inputs .----..........-Jr~----, Outputs
1
-5.2V
-5.2V
(b)
(a)
FIGURE 26. (a) General ECl interface
(b) Driving ECl from same power supply.
Vcc =9-15V
Vcc=5V
Vcc=9-15V
I
Vcc=5V
1
I
1
.~
:!>R
Standard
CMOS
AHCT
or
HCTlS
INPUTS
OUTPUTS
Standard
CMOS
OUTPUTS
r
":"
(a)
(b)
Vcc =9-15V
Standand
CMOS
M5~90'
AHCT
or
HCTlS
INPUTS
Vcc=5V
AHCT
or
HCTlS
INPUTS
R,
OUTPUTS
Vcc=9-15V
Vcc=5V
I
I
Standard
CMOS
OUTPUTS
R
-T rT
AHCT
or
HCTlS
INPUTS
R,
'":"
.1
(e)
(d)
FIGURE 27. Methods of interfacing standard CMOS (4000 and 14000 series) outputs with AHCT and HCTLS
inputs when supply voltages are different.
(a). Using logic down converters,
(b) Using Open-drain CMOS
(b) Using resistor divider (VOH'R2/(RI+R2)~5V)
(d) Using series resistor
c8SAMSUNG
Electronics .
50
TECHNICAL OVERVIEW
Vcc=5V
Vcc=9-15V
1
1
I
I
~R
I"
AHCT
or
HCTLS
OUTPUTS
K
Standard
CMOS
INPUTS
54C906
-b
FIGURE 28. Interfacing AHCT and HCTLS outputs with standard CMOS (4000 and 14000)
using an open-drain CMOS circuit.
High Voltage and Industrial Control Interfaces
Interfacing with high voltage industrial control circuitry where 4000 or 14000-type of CMOS logic is used has been described in Figure 27 and 28. In rugged industrial and automotive environments, more care may be required to prevent large transients from harming AHCT and HCTlS logic. Figure 29 shows a typical connection that utilizes external diode clamps for
input and output protection. The values of R, and R2 depend on the output voltage of the driving circuit and' C depends
on the noise level and speed. The values of RJ and R4 depend on supply voltage and transistor type.
Driving Relays
The high-drive of AHCT and HCTlS outputs enable direct interface with relays, but additional isolation is recommended.
Clamp diodes can be used to prevent spikes generated by the relay from harming the circuit. For higher current drive, an
external transistor may be employed (Figures 30 (a) and (b)). Alternatively, multiple gates may be connected in parallel
to increase the current sinking and sourcing capability.
Driving LED's
Any AHCT or HCTlS output can be used to drive light-emitting diodes (lED's) directly. Figure 31 shows two methods of
doing this. The resistor performs the founction of current limiter. The luminous intensity of the lED depends on the amount
of forward current.
12-24V
Vcc=5V
12V-24V
R.
Industrial
or
Automotive
Control
Logic
R,
R3
R,
Industrial
or
Automotive
Control
Logic
-:FIGURE 29. Interfacing between AHCTiHCTLS logic and high-voltage industrial and
automotive circuitry in rugged environments.
c8SAMSUNG
Electronics
51
II
TECHNICAL OVERVIEW
r - - - - - - - - --,
AHCTor
; HCTLS
I
11
I
1N4148
r---------,
I
50-100Q
I
I
I
I
I
L ___ _
1N4148
I
I
I
____ J
__ .JI
I
I
I
<>---t-
I
I
8
I
I
Relay
-,
o
o
I
I
t ___ _
L
I
I
___ J
(a)
(b)
FIGURE 30. Methods of driving relays. (a) Direct and (b) Through a transistor for higher drive (R = Vcc - 0.7)/lclfJ».
AHCT
or
HCTLS
Vee
R
./f/ LED
ACHT
or
HCTLS
FIGURE 31. Methods of driving LED's
cas··SAMSUNG
Electronics
52
TECHNICAL OVERVIEW
Design Tips
Although the AHCT and HCTLS families are functionally equivalent to the ALS and LS families, some conditions have to
be satisfied in order to be able to simply replace them in existing designs. The AHCT and HCTLS families essentially integrate
TTL and CMOS characteristics into one family. Therefore, in general, the do's and don'ts of both families apply to the AHCT
and HCTLS.
• Don't leave any AHCT or HCTLS input floating. This is frequency overlooked problem with bipolar devices although
it is discouraged by every bipolar manufacturer. CMOS inputs have extremely high input impedance and if left unterminated,
can pick up noise that causes excursions through the threshold. The result is random switching of the device and high power
consumption which can be excessive, especially if the inputs stay very close to the device threshold. Prolonged exposure
to these conditions can damage the device. The thing to do is to simply tie the unused inputs to Vcc or ground (or they
can be tied to nearest operational pin although this may cause more power consumption).
• Don't power up inputs before both Vcc and ground are connected, and don't plug boards into or out of powered connectors unless input currents are limited to the absolute maximum ratings specified for the device: and are short-lived. Both
conditions can forward bias the input and output ESD protection diodes, resulting in excessive diode currents (see Figure
32). If these conditions cannot be avoided, one of the following methods should be used to prevent damage to the AHCT/HCTLS
circuits:
Use connectors that apply power before signals.
Add series resistors at each input to limit currents to the absolute maximum ratings (Figure 33a).
Add logic to board interfaces that forces all outputs to either ground or high-impedance state when they are connected
to unpowered devices (Figure 33b).
Add logic to board inputs to prevent direct interface with un powered HCTLS inputs (Figure 33c). Circuits designed for
this purpose are 7 4AHCT 4049 (Hex Inverting Logic Level Down Converter) and 7 4AHCT 4050 (Hex Logic Level Down
Converter). These parts have a modified input protection structure that enables them to be used as logic level translators
which convert high-level logic to low-level logic while operating from the low logic supply. In this case, since the low
logic supply is zero (unpowered), the outputs of the 4049 and 4050 will always be zero regardless of the inputs.
POWERED SYSTEM
UNPOWERED SYSTEM
-,------,-- UNPOWERED Vee
LINE
ANY TTL
TYPICAL CMOS
INPUT STAGE
NMOSORCMOSI------~==T__+~
OUTPUT
--'----='=- SYSTEM
f-
GROUND
UNPOWERED Vee
LINE
3-ST ATE OUTPUT STAGE
I- L__--::I-::--_
SYSTEM GROUND
FIGURE 32. Direct interface to unpowered CMOS ICs presents a dangerous situation where high-level
signals forward-bias input and output protection diodes and try to "power-up" the Vcc line.
Excessive currents at such an interface can cause damage to the circuitry.
c8SAMSUNG
FI~('trnni('~
53
II
TECHNICAL OVERVIEW
POWERED
SYSTEM
UNPOWERED
SYSTEM
POWERED
SYSTEM
UNPOWERED
SYSTEM
-
A~A
"'R'"
INTER
FACE
LOGIC
..
A~A
.......
AAA
-
(a)
(b)
POWERED
SYSTEM
UNPOWERED
SYSTEM
I--INTER·
FACE
LOGIC
r(c)
FIGURE 33. Methods of protection in power-down situations: (a) Use of series resistors to limit input currents
to absolute maximum ratings, (b) Interface logic circuitry that forces all outputs to either ground or highimpedance state, (c) Interface circuitry at board inputs that acts as buffer between powered and unpowered
devices; ideal components for this purpose are the 74AHCT4049 and 74AHCT 4050 Hex Logic Level Down
Converters that lack the Vce diode in their protection circuitry.
- In bus-oriented systems, don't allow the bus to stay in high-impedance state for extended periods of time if it is not
terminated, because this will have the same effect as leaving inputs open. Two simple ways of terminating the bus are illustrated in Figure 34. Most microprocessor-based systems, however, do not keep the bus in 3-state for long periods, in
which case, the bus capaCitance can maintain valid logic levels. In these cases, pull-up or pull-down circuitry may not be
necessary.
-The edge-rates of the AHCT and HCTLS part are similar to the very high-speed TTL parts. Tnerefore, system grounding
and supply-decoupling techniques normally employed in high-speed TTL designs should be duplicated in AHCT/HCTLS designs
to ensure proper operation. A good rule of thumb to reduce the affects of PC board trace inductance is to place 0.01 to
0.1 j.lF RF-grade capaCitors every two-to-five ICs (octal flip-flops and buffers may require more decoupling). This, of courSe,
has to be accompanied by careful pc board layout to minimize these inductances.
- The testing problems encountered in ALS, LS and FAST apply also to AHCT and HCTLS. Most of these problems
result from the noise produced by the interactions of the device being tested and the test system. Typical test fixtures
have lead inductances several times that of a PC board socket. This inductance, especially in the device ground path is
the source of these problems.
The outputs, for example, can cause transient currents in the 50 to 200 mA range within a couple of nanoseconds while
changing state. These appear as changes in the voltage drop across the device ground lead. The test system's input and
output reference voltages are set with respect to tester ground and are not affected by these transients. Consequently
the effective input voltages to the device will vary. If the ground pin goes up 1 volt, all the inputs effectively go down 1
volt. This must be considered in selecting input and output voltage levels. In functional tests, for example, solid input logic
levels should be applied, instead of 0.8 and 2.0 volts.
Furthermore, if TTL test programs are to be used, one must be particularly careful not to apply voltages to inputs and outputs
that are below ground or above Vcc in excess of the absolute maximum limits specified in the data sheets.
c8SAMSUNG
Electronics
54
TECHNICAL OVE~VIEW
3-STATE BUS
. . .
~
I-
R
~
R
R
R :
R
~
R
R :
Vee or GND
(a)
AHCT/HCTLS
541 or 244
(3-State Octal
Buffers)
R
R
R
R
R
R
R
R
1
3-STATE
BUS
(b)
FIGURE 34. Methods of terminating 3-state buses; (a) Pullup or pulldown resistors (b) Use of 3-state buffers.
The latter approach terminates the bus to the last active logic level and dissipates no static power.
c8SAMSUNG
~I
__ "'",__ :-""
55
II
NOTES
J ...
,
~
"
KS54AHCT
KS74AHCT
00
Quad 2-lnput NAND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 rnA @ VOL .=O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These dp.vices contain four independent 2-input NAND
gates that perform the Boolean functions Y = A. B or
PIN CONFIGURATION
Y=A+B
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground .
LOGIC DIAGRAM
(1)
1A
Vee
18
48
1Y
4A
2A
4Y
28
38
2Y
3A
GND
3Y
1A
1B
~
(3)
(2)
~
~~~
II
1Y
2Y
(9)
3A~3Y
3B~
(12)
4A~4Y
4B~
FUNCTION TABLE
(Each Gate)
Inputs
Output
A
B
Y
H
L
X
H
X
L
L
H
H
59
00
KS54AHCT
KS74AHCT
Quad 2-lnput NAND Gates
Absolute Maximum Ratings *
Supply Voltage Range Vcc, ........ -0.5V to +7V
DC Input Diode Current; hK
(VI < -0.5V or VI > Vcc +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) ......... ±35 mA
Continuous Current Through
Vec or GND pins . . . . . . . . . . . . . . .. ± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt. . . . . . 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc .............. 4.5V to 5.5V
DC Input & Output Voltages *. VIN. VOUT . . OV to Vcc
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V±10% Unless Otherwise Specified)
TII =25°C
Symbol Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits \
Minimum High-level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum low-level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-level
Output Voltage
VOH
VIN = VIH or VIL
lo=-20",A
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum low-level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/oiA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
/oI A
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Icc
Vee Vce -0.1
4.2
3.98
0
VIN=VCC or GND
IOUT=O",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
louT=O",A
AC ELECTRICAL CHARACTERISTICS
(Input tr , tf~2 ns), AHCTOO
Ta =25°C
Characteristic
Symbol Conditions t Vce=5.0V
Typ
tpLH
Propagation Delay
t - - - CL=50pF
tpHL
Input CapaCitance
CIN
Power Dissipation CapaCitance *
Cpo
• Cf'; deterlTlflleS ttle
(per gate)
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta = -55°C to +125°C
Vee =5.0V:1: 10%
Min
7
8
Max
11
11
Vec=5.0V:1: 10%
Min
Unit
Max
14
ns
14
5
pF
15
pF
no·load dynamiC power diSSipation: Po=Cpo Vee I
waveforms see section 2.
t For AC switching test circuits and timing
1
=8SAMSUNG
Electronics
60
KS54AHCT
KS74AHCT
01
Quad 2-lnput NAND Gates
with Open-Drain Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Driv.Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to S.SV
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2-input NAND
gates with open-drain outputs. Using a suitable pull-up
resistor, these outputs may be connected to other opendrain outputs to implement wired-AND functions.
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
II
(1,4,10,13)
lY
Vee
lA
4Y
18
48
2Y
4A
2A
3Y
28
38
GND
3A
;
(2'5'8'11)~~Y
(3,6.9,12)
J..-
FUNCTION TABLE
(Each Gate)
Inputs
Output
A
B
y
H
L
X
H
X
L
L
H
H
c8SAMSUNG
Electronics
61
01-
KS54AHCT
KS74AHCT
Quad 2-lnput NAND Gates
with Open-Drain Outputs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/o C from 65 ° C to 85 ° C
Supply Voltage Range Vee,
__ -0.5V to +7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vec +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
± 1 25 mA
Storage Temperature Range, T5 1g •.. -65°C to +150°C
Power Dissipation Per Package, Pdt .. _ . _ . 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, Your
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C~ +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf .. _
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may OCCUI
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
Test Conditions
KS74AHCT
KS54AHCT
Ta =-400Cto +85°C Ta = -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-L.evel
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20jAA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
jAA
Maximum Output
Leakage Current
loz
VIN=V'H or VIL
Vour=Vee
±0.5
±5.0
±10.0
jAA
0
--
Maximum Quiescent
Supply Current
Icc
-----~
i:itio:al-Worst---
ICase
Supply
Current
. t.lce
V'N=Vce or GND
lour=OjAA
per Input pin
VI=2.4V
other Inputs:
at Vee or GND
lour=OjAA
2.0
------;---.-;-~------r__
--1-
jAA
----
3.0
I
ImA
(Input tr , tf~2 ns), AHCT01
KS74AHCT
KS54AHCT
Til =25°C
Ta = -40°C to +85°C T. = -55°C to +125°C
Symbol Conditions t Vcc=5.0V
Unit
Vcc=5_0V±10%
Vcc=5.0V± 10%
Typ
Propagation Delay
40.0
---
2.9
2.7
AC ELECTRICAL CHARACTERISTICS
Characteristic
20.0
--~--
tpLH
f------
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance·
Cpo
Min
Max
Min
Max
CL=50pF
RL =1 kO
17
25
29
10
16
19
5
pF
(per gate)
15
pF
ns
* CPD determines the no-load dynamic power dissipation: PD=CPD Vce' fin-
t
For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
62
KS54AHCT
KS74AHCT
02
Quad 2-lnput NOR Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.SV to S.SV
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2-input NOR gates
that perform the Boolean functions Y=A+B or Y=A·S.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
1Y
Vee
1A
4Y
18
48
2Y
4A
2A
3Y
2B
3B
GND
3A
1A~
1B~'
II
1Y
2A~
2B~
3A~
3B~'
2Y
3Y
4A~
4B
JE~
4Y
FUNCTION TABLE
(Each Gate)
Inputs
A
B
H
X
X
H
L
L
Output
y
=8SAMSUNG
Electronics
L
L
H
63
KS54AHCT
KS74AHCT
02
Quad2-lnput NOR Gates
Absolute Maximum Ratings·
Supply Voltage Range Vcc. . ....... -0.5V to + 7V
DC Input Diode Current. 11K
(VI < -0.5V or VI > Vcc +O.5V) ... " ±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin. 10 .
(-0.5V < Vo < Vcc +0.5V) ......... ±35 mA
Continuous Current Through
Vcc or GND pins . . . . . . . . . . . . . . .. ± 125 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vcc .............. 4.5V to 5.5V
DC Input & Output Voltages *. VIN. VOUT . . OV to Vcc
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times. tr • tf . . . . . . . . . Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V± 10% Unless Otherwise Specified)
Ta =2S O C
Symbol Test Conditions
Typ
KS74AHCT
KS54AHCT
T8= -40°C to +85°C T8= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum low-level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-level
Output Voltage
VOH
VIN=VIH or VIL
10=-2OIlA
10=-4mA
Vee "-0.1
3.84
Vee -0.1
3.7
V
Maximum low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vce or GND
±0.1
±1.0
±1.0
IlA
Maximum Quiescent
Supply Current
lee
2.0
20.0
40.0
IlA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Iee
Vee Vee -0.1
4.2
3.98
0
VIN=Vee or GND
10UT=01lA
per input pin
V\=2.4V
other Inputs:
at Vee or GND
IOUT=OIlA
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r • tf~2 ns). AHCT02
KS74AHCT
KS54AHCT
T. =2S O C
T. = -40°C to +85°C T. = -55°C to +125°C
t
Symbol Conditions Vcc=5.0V
Unit
Vcc=5.0V%10%
Vcc=S.OV% 10%
Typ
Propagation Delay
~
CL=50pF
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance *
CPD
(per gate)
Min
Max
Min
Max
7
12
14
7
12
14
ns
5
pF
15
pF
CI':J det(:rfllrnes the no-load dynamic power dissipation PO=CPD Vee' I",.
For AC sWitching test crfcilits and tlmrllq w;welorflls spp snctr()11 2
c8·SAMSUNG
Electronics
64
KS54AHCT
KS74AHCT
03
Quad 2-lnput NAND Gates
with Open-Drain Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wi~e operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
These devices contain four independent 2-input NAND
gates with open-drain outputs. Using a suitable pull-up
resistor, these ootputs may be connected to other opendrain outputs to implement wired-AND functions.
• P.ackage options include "small outline" packages
(Available Tape & Reel), standard DIPs_
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
.
1A
Vee
18
48
1Y
4A
2A
4Y
28
2Y
38
GND
3Y
:
(1,4,9,12)
D--[>o--1
(2,5,10,13)
l
r(3.6.8.11 Y
.•
.
3A
FUNCTION TABLE
(Each Gate)
Inputs
Output
A
B
y
H
L
H
X
L
L
H
H
X
=8SAMSUNG
Electronics
65
I
KS54AHCT
KS14AHCT
03
Quad 2-lnput NAND Gates
with Open-Drain Outputs
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Supply Voltage Range Vee, ., ...... -0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ' ±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . . .
±35 rnA
Continuous Current Through
Vee or GND pins . . . . . . . ..
. ... , ± 1 25 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
. Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee .............. 4.5V to 5.5V
• DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 10% Unless Otherwise Specified)
Ta=25°C
test Conditions
Typ
Minimum High-Level
Input Voltage
Maximum Low-Level
Input Voltage
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C fa= -55°C to +125°C Unit
Guaranteed Limits
VIH
2.0
2.0
2.0
V
VIL
0.8·
0.8
0.8
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/lA
lo=4mA
lo=8mA
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
/lA
Maximum Output
Leakage Current
loz
VIN=VIH or VIL
VOUT=VCC
±0.5
±5.0
±10.0
/lA
Maximum Quiescent
Supply Current
---
----
I Additional
Worst
ICase Supply
lcur~ent
b
VIN=VCC or GND
IOUT=O/lA
- perinput-p;nVI=2.4V
bolee other Inputs:
at Vee or GND
louT=O/lA
-----
I
40.0
-
-----
----
1----
2.9
/lA
---~
3.0
'----
rnA
(Input tr , tf~2 ns), AHCT03
KS74AHCT
KS54AHCT
Ta =25°C
Ta = -40°C to +85°C Ta = -55°C to +125°C
Symbol Conditions t Vcc=5.0V
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Propagation Delay
------_._-
2.7
AC ELEC.TRICAL CHARACTERISTICS
Characteristic
20.0
2.0
Icc
-
tpLH
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
Min
Max
Min
Max
CL=50pF
RL=1kO
17
25
29
10
16
19
5
pF
(per gate)
15
pF
ns
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 1 fint For AC switching test circuits and timing waveforms see "3ection 2.
c8SAMSUNG
Electronics
66·
KS54AHCT O~
KS74AHCT
Hex Inverters
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT:· -55°C to +125°C
• Package options include" small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain six independentinverters. They perform the Boolean function Y = A.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
around.
LOGIC DIAGRAM
PIN CONFIGURATION
1A
Vee
lY
6(,.
2A
6Y
2Y
5A
3A
5Y
~ lY
lA~---
~
····2Y
2A-~
_(5)~(6)
3A~3Y
~
3Y
4A
4A~
GND
4Y
~
5A-~5Y
4Y
-.l13~(1~
6A~6Y
FUNCTION TABLE
(Each Inverter)
Input
Output
A
y
H
L
L
H
c8~~~SUNG
67
04
KS54AHCT
KS74AHCT
Hex Inverters
Absolute Maximum Ratings·
t Power Dis~ipation temperature derating:
Plastic Package (N): -12mW/oe from 65°C to 85°C
Supply Voltage Range Vcc. . .
. . -0.5V to + 7V
DC Input Diode Current. hK
(V, < -0.5V or V, > Vee +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vce +0.5V)
±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vce +0.5V) . .
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt
500 mW
Recommended Operating Conditions
Supply Voltage. Vcc . . .
4.5V to 5.5V
DC Input & Output Voltages·. Y,N. Your .. OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times. tr • tf
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device ator beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V±10% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta,= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
V,H
2.0
,2.0
2.0
V
Maximum Low-Level
Input Voltage
VrL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VrN=VrH or VrL
10=-20J..lA
10=-4mA
Vcc -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VrN=VrH or VrL
10=20J.lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VrN=Vcc or GND
±0.1
±1.0
±1.0
J.lA
2.0
20.0
Maximum Quiescent
Supply Current
.....
-._-------I Additional
Icc
--~
Worst
ICurrent
Case Supply
blce
VrN=Vcc or GND
10ur=OJ.lA
per input pin
V,=2.4V
other Inputs:
at Vee or GND
lour=OIlA
f-------~~-
Vcc Vce -0.1
4.2
3.98
0
[---
Characteristic
tpLH
r - - - CL=50pF
tPHL
elN
Power Dissipation Capacitance *
Cpo
t
__ _---..
3.0
J.lA
r-~
mA
Min
c8 SAMSUNG
Max
Max
11
14
7
11
14
ns
pF
5
(per gate)
Min
7
pF
15
Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee'
For AC switching test circuits and timing waveforms see section 2.
Electronics',
..
KS74AHCT
KS54AHCT
Ta =25°C
Ta = - 40°C to + 85°C Ta = -55°C to +125°C
Unit
Symbol Conditionst Vcc=5.0V
Vcc=5.0V~10%
Vcc=5.0V~ 10%
Input Capacitance
*
------~-
(Input tr • tf~2 ns). AHCT04
Typ
Propagation Delay
~
2.9
2.7
AC ELECTRICAL CHARACTERISTICS
40.0
-..
, . _ _ _ - - _ _ 00
fill
Icc Vcc.
68
KS54AHCT
KS74AHCT
05
Hex Inverters with Open-Drain Outputs
'FEATURES
DESCRIPTION
These devices contain six independent inverters with opendrain outputs. Using a suitable pull-up resistor, these outputs may be connected to other open-drain outputs to implement wired-AND functions.
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directfy with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
LOGIC DIAGRAM
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vec and
ground.
(2,4,6,8, 10, 12)
1A
Vee
1Y
6A
2A
6Y
2Y
5A
3A
5Y
3Y
4A
GND
4Y
I~r'
II
FUNCTION TABLE
(Each Inverter)
Input
Output
A
y
H
L
L
H
c8SAMSUNG
Electronics
69
KS54AHCT
KS74AHCT
05",
Hex Inverters with Open-Drain Outputs
Absolute Maximum Ratings*
t Power Dissipation, temperature derating:
Plastic Package (N): -12mW/OC from 65°C to 85°C
Supply Voltage Range Vcc,
-0.5V to +7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) .
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, T519 . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, Your
OV to Vec
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C to +125°C
, , . Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functi~nal operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vcc=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
-,--
KS74AHCT
Ta= -40°C to +85°C
Typ
T~=
KS54AHCT
-55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/AA
lo=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±.1.0
±1.0
loz
VIN = VIH or VIL
VouT=Vce
Maximum Quiescent
Supply Current
Icc
- --
I
i
/AA
------
Maximum Output
Leakage Current
:Additional Worst
Case Supply
I Current
0
±0.5
VIN=VCC.or GND
10uT=0/AA
per input -pin--VI=2.4V
-----
-
40.0
-
J.lA
-- ----
------
i
I
2.7
2.9
3.0
mA
I
)
AC ELECTRICAL CHARACTERISTICS
(Input t r , tf";2 ns), AHCT05
KS54AHCT
KS74AHCT
Ta = 25°C
T. = - 40°C to + 85°C Til = -55°C to +125°C
Symbol Conditions t Vcc=5.0V
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Propagation Delay
J.lA
i
"'cc Iother
Input"
at Vcc or GND
Characteristic
±10.0
20.0
2.0
I
louT=OJ.lA
±5.0
tpLH
r - - - CL=50pF
RL=1kn
tPHL
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per inverter)
Min
Max
Min
Max
17
25
29
8
14
33
ns
5
pF
15
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc'
fin-
cc Vee .
t For AC switching test circuits and timing waveforms see section 2,
:CJSAMSUNG
• • Electronics
70
08
KS54AHCT
KS74AHCT
Quad 2-lnput AND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 rnA @VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: ~40°C to +85°C
KS54AHCT: - 55°C to + 125°C
- Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2-input AND. gates.
They perform the Boolean functions Y=A-B or Y=A+B.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any. external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
(1\
1A
Vee
18
48
1Y
4A
2A
4Y
28
38
2Y
3A
GND
3Y
1A-'~3) 1Y
II
(2)
18(4)
(6)
2A~2Y
28~
(9)
(8)
3A~3Y
3B~(12)
(11)
4A~~4Y
4B~
FUNCTION TABLE
I
(Each Gate)
Inputs
f--._-_._-
Output
B
Y
H
H
H
L
X
X
L
L
L
A
c8SAMSUNG
Electronics
71
08 .
KS54AHCT
KS74AHCT
Quad 2-lnput AND Gates
Absolute Maximum Ratings*
t Power DisSipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ....... -0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continu.ous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) .
±35 mA
Continuous Current Through
Vce or GND pins. . . . . . . . .
±125 mA
Storage Temperature Range, Tstg . . . - 65 0 C to + 150 0 C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vcc
Operating Temperature
Range
KS74AHCT: -4poC to +85°C
KS54AHC~ -55°C~ +125°C
... Max 500 ns
Input Rise & Fall Times, tr , tf ...
.. Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V± 1 0% Unless Otherwise Specified)
Ta ==25°C
Symbol Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta ==-40°Cto +85°C Ta ==-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
",A
2.7
2.9
3.0
rnA
I,
Additional Worst
Case Supply
Current
I
6.lcc
'.
VIN=VCC or GND
10UT=0",A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10UT=0",A
Vcc Vcc -0.1
4.2
3.98
0
:
I
1
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr , tf~2 ns), AHCT08
KS74AHCT
KS54AHCT
Ta == 25°C
Ta== -40°C to +85°C Ta == - 55°C to + 125°C
Unit
Symbol Conditions t Vec == 5.0V
Vcc==5.0V± 10%
Vce=5.0V±10%
Typ
Propagation Delay
-
tpLH
CL=50pF
tpHL
Input Capacitance
CIN
Power DiSSipation Capacitance"
Cpo
(per gate)
Min
Max
Min
Max
8
14
17
8
14
17
ns
5
pF
15
pF
.. Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
72
KS54AHCT
KS74AHCT
09
Quad 2-lnput AND Gates
with Open-Drain Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2-input AND gates
with open-drain outputs. Using a suitable pull-up resistor,
these outputs may be connected to other open-drain outputs to implement wired-AND functions.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
(3.6.8,11)
1A
Vee
18
48
1Y
4A
2A
4Y
28
38
2Y
3A
GNO
3Y
A (1.4.9.12)
B /2.5. W. '"
~Y
~1
FUNCTION TABLE
(Each Gate)
Inputs
Output
f-----~
A
B
Y
H
L
H
X
X
L
H
L
L
c8SAMSUNG
Electronics
73
KS54AHCT
KS74AHCT
09
Quad 2-lnputAND Gates
. with_ Open-Drain Outputs
Absolute_ Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vce.+0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vec +0.5V) . . . . . .
±35 mA
Continuous Current Through
Vec or GND pins . . . . . . . . . . . . . . .. ± 1 25 mA
Storage Temperature Range, Tstg . . . - 65 ° C to + 150 ° C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc ....... ; . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vcc
Operating Temperature
KS74AHCT: -40°C to +85"C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta =-40°Cto +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O fJ A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0,·1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
fJA
loz
VIN=VIH or VIL
VOUT=VCC
±0.5
±5.0
±10.0
~
Maximum Output
Leakage Current
Maximum Quiescent
Supply Current
Additional Worst
Supply
Icurrent.
Icc
.-
j
i Case
~Icc
0
VIN=VCC or GND
10uT=OfJA
_.._-_
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
lOUT = OfJA
--
2.0
2.7
AC ELECTRICAL CHARACTERISTICS
Characteristic
20.0
--------.
..-
-----
.-
,
fJA
-_
-----~
2.9
3.0
.. - -
..
mA
(Input tr , tl:::;;2 ns). AHCT09
KS54AHCT
KS74AHCT
Ta =25°C
Ta =-40°Cto +85°C Ta = -55°C to +125°C
Symbol Conditions t Vcc= 5.0V
Unit
Vcc=5.0V± 10%
Vcc = 5.0V ± 1.0 %
Typ
Propagation Delay
40.0
------
tpLH
~
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
Min
Max
Min
Max
CL=50pF
RL=1 kO
18
27
31
9
15
18
5
pF
(per gate)
15
pF
ns
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
74
KS54AHCT
KS74AHCT
10
Triple 3-lnput NAND Gates
FEATURES
DESCRIPTION
- Function, pin-out, speed ~md drive compatibility with
54174ALS logic family
- Low power consumption characteristic of CMOS
- High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
- Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
- Wide operating voltage range: 4.5V to 5.5V
- Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain three independent 3·input NAND
gates. They perform the Boolean functions Y=A-B-C or
PIN CONFIGURATION
LOGIC DIAGRAM
Y=A+B+C.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
(1)
1A~
1A
Vee
1B
1C
2A
1Y
2B
3C
2C
2Y
38
3A
GND
3Y
II
~~~-1Y
2A
(3)
3A
(9)
2B~2Y
2C~
3B~3Y
3e~
FUNCTION TABLE
(Each Gate)
Inputs
Output
A
B.
C
y
H
L
H
H
X
X
X
L
X
X
X
L
L
H
H
H
cRSAMSUNG
• • Electronics
75
KS54AHCT
KS74AHCT
1.0
Triple 3-lnput NAND Gates
Absolute Maximum Ratings·
t Power Dissipation temperature derating: .
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, . . . .
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
. . .. ± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee
..... '.' . . . 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, t r , tf
.. Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
KS74AHCT
KS54AHCT
Ta = - 40°C to + 85°C Ta =-55°Cto +125°C Unit
Typ
Minimum High-Level
Input Voltage
Guaranteed Limits
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/J A
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
",A
~tional
Worst
ICurrent
~ase Supply
..6.lee
Vee Vee -0.1
3.98
4.2
0
VIN=Vee or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
- - f----
2.7
AC ELECTRICAL CHARACTERISTICS
Characteristic
2.9
KS74AHCT
KS54AHCT
T.=25°C
T. = -40°C to +85°C T.=-55°Cto +125°C
Symbol Conditionst Vcc=5.0V
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
~
CL=50pF
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
Min
:8SAMSUNG
Min
Max
15
18
9
15
18
ns
pF
5
(per gate)
Max
9
pF
15
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee l
t For AC switching test circuits and timing waveforms see section 2.
Electronics
mA
3.0
(Input t r , tf~2 ns), AHCT1 0
Typ
Propagation Delay
. - - - - - - - - . - -f.,---
fin.
76
KS54AHCT
KS74AHCT
11
Triple 3-lnput AND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40o'C to +85°C
KS54AHCT: - 55°C to + 125°C
- Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain three independent 3-input AND
gates. They perform the Boolean functions Y=A-B-C or
y=A+B+C.
These devices provide· speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
. static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
(1)
1A~2)
(12)
1A
Vee
18
1C
2A
1Y
28
3C
2C
38
2Y
3A
GND
3Y
18
1C
2A
1Y
(13)
(3)
28~2Y
2C~····
(9)
3A~10)
(8)
38
3C
(11)
3Y
FUNCTION TABLE
. (Each Gate)
h--"'PU~~
ABC
H
L
X
X
H
-X
L
X
H
X
X
L
=8SAMSUNG
1:I.o.,..+ ..""_i,.. ....
Output
Y
H
L
L
L
77
KS54AHCT
KS74AHCT
11·-
Triple 3-lnput AND Gates
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Supply Voltage Range Vee, ... . . . . -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, io
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins ............... , ± 1 25 mA
Storage Temperature Range, T8 tg •.. -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Plastic Package (N): -12mW{OC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc ..... : ........ 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . .. Max 500 ns
" Absolute Maximum Ratings are those values beyond
Which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
Vil
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or Vil
10=-20J.lA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or Vil
10=20J.lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
J.lA
2.0
20.0
Maximum Quiescent
Supply Current
Icc
I
I
IAdditionaJ Worst
Case Supply
Current
t:.lee
Vee Vee -0.1
3.98
4.2
0
VIN=VCC or GND
10uT=_0J.lA
per input pin
VI=2.4V
other Inputs:
at Vec or GND
10uT=0l-'A
--
mA
KS54AHCT
KS74AHCT
Ta =25°C
Ta = - 40°C to + 85°C Ta = -55°C to +125°C
Symbol Conditionst Vce=5.0V
Unit
Vee = 5.0V:i: 10%
Vcc=5.0V:i: 10%
~
tpHl
Input Capacitance
CIN
Power Dissipation Capacitance"
Cpo
Cl=50pF
Rl=1kO
9
9
(per gate)
15
Min
c$!SAMSUNG
Max
Min
Max
15
18
15
18
ns
pF
5
" Cpo determines the no-load dynamic power dissipation: PO=CPD VCC 2
t For AC switching test circuits and timing waveforms see section 2.
• • Electronics
3_0
-
(Input tr , tf~2 ns), AHCT11
Typ
Propagation Delay
J.lA
--------"--
2.9
2.7
AC ELECTRICAL CHARACTERISTICS
Characteristic
40.0
----
pF
fin.
78 .
KS54AHCT
KS74AHCT
12
Triple 3-lnput NAND Gates
with Open-Drain Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
,
• Low power consumption characteristic of CMOS
• High--Driv.current outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military .temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain three independent 3·input NAND
gates with open·drain outputs. They perform the Boolean
functions Y=A.S·C or y=A+B+C.
Using a suitable pull-up resistor, these outputs may be connected to other open-drain outputs to implement wired-AND
functions.
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
LOGIC DIAGRAM
A~(1'3'9)
.
1A
Vee
18
1C
2A
1Y
28
3C
2C
38
2Y
3A
GND
3Y
(2,4.10)
: "3,5.'"
r-
P2 6 s
• • )y
_.
FUNCTION TABLE
(Each Gate)
Inputs
Output
A
B
C
y
H
L
X
X
H
X
L
X
H
X
X
L
L
H
H
H
I
cHSAMSUNG
79
KS54AHCT
KS74AHCT
12'
Triple 3-lnput NAND" Gates
with Open-Drain Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vee •....... -0.5V to +7V
DC Input Diode Current. 11K
(VI < -0.5V or VI > Vee +O.5V) . " " .. ±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0.5V) . . .. ±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vcc or GND pins . . . . . . . . . . . . . . .. ± 125 mA
Storage Temperature Range. TSlg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vcc .............. 4.5V to 5.5V
DC Input & Output Voltages·. VIN. VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to. +125°.(;
Input Rise & Fall Times. tr • tf ...... " " . Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions Q1ay affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V± 10% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Symbol Test Conditions
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
0.8
0.8
0.8
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
±0.5
±5.0
±10.0
2.0
20.0
40.0
2.9
3.0
Maximum" Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20,..A
10=4mA
10=8mA
o
Maximum Input
Current
Maximum Output
Leakage Current
102
Maximum Quiescent
Icc
Sup~ly gurre~__ __
!Additionat Worst
lcase Supply
Current
VIN=VIH or VIL
VOUT=VCC
VIN=VCC or GND
-~~rT~g~;prn---b.lcc
I
VI=2.4V
other Inputs:
at Vec or GND
10UT=0,..A
AC ELECTRICAL CHARACTERISTICS
(Input tr • tf~2 tis). AHCT12
T8 =25°C
Symbol Conditions t Vcc=5.0V
Characteristic
Typ
~
Propagation Delay
CL=50pF
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance·
Cpo
KS74AHCT
T.
= - 40°C to + 85°C
Vcc=5.0V:t:10%
Min
Electronics
,"
Vcc=5.0V:t: 10%
Min
Unit
Max
27
31
11
18
22
ns
- - f-----
pF
pF
15
• Cpo determines the no-load dynamic power dissipation: PD=CPD VCC 2
t For AC switching test circuits and timing waveforms see section 2.
ci$SAMSUNG'
Max
KS54AHCT
Ta = -55°C to +125°C
19
5
(per gate)
rnA
fin.
80
KS54AHCT
KS74AHCT
14
Hex Schmitt-Trigger Inverters
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOl =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5 ..5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These Schmitt-trigger devices contain six independent inverters. They perform the Boolean function Y=A.
PIN CONFIGURATION
LOGIC DIAGRAM
lA
Vee
lY
6A
2A
6Y
2Y
5A
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
II
lA~lY
2A
~
~
·2Y
~
3A~3Y
3A
5Y
3Y
4A
4A
GND
4Y
~
5A~5Y
~
_~ __
4Y
~
6A~_6Y
FUNCTION TABLE
(Each Inverter)
Input
I
Output
A
'
Y
H
L
L
H
cg·SAMSUNG
Electronics
81
Hex
Schmitt-Trigg~r
Inverters
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vee,
-0.5V to +7V
DC Input Diode Current, 11K
(VI < -0.5V orVI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -:-0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
±35 mA
(-0.5V < Vo < Vee +0.5V).
Continuous Current Through
Vee or GND pins.
±125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee . . . . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40.oC to +85°C
KS54AHCT: -55°C~ +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
KS74AHCT
T8= -40°C to +85°C T8
Ta =25°C
Typ
KS54AHCT
to +125°C Unit
= -55°C
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20j.lA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20",A
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
40.0
",A
3.0
mA
i
IAdditional
Worst
Case Supply
icurrent
f
I "'cc
~
_
.
.
.
.
.
.
.
.
.
----
2.9
(Input t r , tf~2 ns), AHCT2U
KS74AHCT
KS54AHCT
Ta'=25°C
Ta = -40°C to +85°C Ta = - 55°C to +125°C
Conditions
t
Unit
Vcc=5.0V
. Symbol
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Propagation Delay,
Any input to Y
__________
2.7
AC ELECTRICAL CHARACTERISTICS
Characteristic
20.0
.
2.0
.
VIN=Vee or GND
10uT::::0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
louT=Oj.lA
.
Icc
0
c
Maximum Quiescent
Supply Current
Vee Vce -0.1
4.2
3.98
tpLH
r---
CL=50pF
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance·
Cpo
(per gate)
Min
Max
Min
Max
7
11
13
7
11
13
ns
5
pF
15
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
85
II
KS54AHCT
KS74AHCT
21
Dual 4-lnput AND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOl =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
These devices contain two independent 4-input AND gates.
They perform the Boolean functions Y = A· B. C· D or
Y=A+B+C+E> in positive logic.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs .
. PtN CONFIGURATION
LOGIC DIAGRAM
1A
1A
Vee
18
2D
NC
2C
18
1Y
1C
NC
1D
28
1Y
2A
GNO
2Y
1C
10
2A
28
2Y
2C
20
FUNCTION TABLE
(Each gate)
INPUTS
--
OUTPUT
A
B
C
0
Y
H
L
H
H
H
X
L
X
X
X
X
L
X
X
X
X
L
H
L
L
L
L
X
X
X
c8SAMSUNG
Electronics
.
86
KS54AHCT
KS74AHCT
21
Dual 4-lnput AND Gates
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Ceramic Package (J): -12mW/oC from 100°C to 125°C
Supply Voltage Range Vcc. . .
-0.5V to + 7V
DC Input Diode Current. hK
(VI < -0.5V or VI > Vce +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt
500 mW
Recommended Operating Conditions
Supply Voltage. Vcc
4.5V to 5.5V
DC Input & Output Voltages·. VIN. VOUT
OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times. t r • t,
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL .CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 1 0% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta = -55°C to +125°C Unit
Ta =25°C
Test Conditions
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
V
f---
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=- 2OIlA
lo=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2OIlA
lo=4mA
10=8mA
Maximum Input
Current
hN
VIN=VCC or GND
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
VIN=VCC or GND
IOUT=OIlA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
louT=OIlA
--- -------_.-
.6.lcc
Vcc Vcc -0.1
3.98
4.2
0
r-
Vcc -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
IlA
20.0
40.0
2.0
---
IlA
-----
I
2.7
AC ELECTRICAL CHARACTERISTICS
Characteristic
Vcc -0.1
3.84
2.9
mA
3.0
(Input t r • tf~2 ns). AHCT21
KS74AHCT
KS54AHCT
Ta =25°C
Ta = - 40°C to + 85°C Ta = -55°C to +125°C
Unit
Symbol Conditions t Vcc=5_0V
Vcc=5_0V::t10%
Vcc=5.0V::t 10%
--
Typ
Propagation Delay.
Any input to Y
~ CL =50pF
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per gate)
Min
8
14
8
14
Min
Max
17~
17
ns
- -- -
pF
5
15
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
Max
pF
fin.
87
II
'Dual 4-lnput NAND Gates
with Open-Drain Outputs
KS54AHCT22
KS74AHCT
FEATURES
DESCRIPTION
- Function, pin-out, speed and drive compatibility with
54174ALS logic family
- Low power consumption characteristic of CMOS
- High-Dri~e-Current outputs:
IOL =8 mA @ VOL =O.5V
- Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
- Wide operating voltage range: 4.5V to 5.5V
- Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape. & Reel), standard DIPs.
These devices contain two independent 4·input NAND
gates. These gates perform the Soolean fucntions
Y-A-S-C-Dor Y=A+B+C+D in positive logic. The
open-drain outputs require pull-up resistors to perform
correctly. They may be connected. to other open-drain
outputs to implement active low wired-OR or active high
wired-AND functions.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components .
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
1A
Vee
A
1B
20
B
NC
2C
C
1C
NC
0
10
2B
1Y
2A
GNO
2Y
(1,9)
(2,10)
(4, 121
(5,13)
~
r'
FUNCTION TABLE
(Each Gate)
INPUTS
OUTPUT
A
B
C
D
Y
H
L
X
X
X
H
X
L
X
X
H
X
X
L
X
H
X
X
'X
L
L
H
H
H
H
Q'SAMSUNG
••
•
~lectroniCS
88
KS54AHCT
KS74AHCT
22
Dual 4-lnput NAND Gates
with Open-Drain Outputs
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee.
-0.5V to + 7V
DC Input Diode Current. hK
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin. 10
(-O.5V < Vo < Vee +O.5V)
±35 rnA
Continuous Current Through
Vee or GND pins
± 125 rnA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt.
500 mW
Recommended Operating Conditions
Supply Voltage. Vee
4.5V to 5.5V
DC Input & Output Voltages * • VIN. Your .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
D
KS54AHC~ -55°C~ +125 C
Max 500 ns
Input Rise & Fall Times. t r • tf ...
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2O/lA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/lA
Maximum Output
Leakage Current
loz
VIN=VIH or VIL
Vour=Vee
±0.5
±5.0
±10.0
/lA
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
/lA
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
bolee
0
VIN=Vee or GND
10ur=0/lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour = OI-lA
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r • tf~2 ns). AHCT22
KS74AHCT
KS54AHCT
T.= 25°C
T. = -40°C to +85°C Ta = -55°C to +125°C
Symbol Conditions t Vcc=5.0V
Unit
Vcc = 5.0V ± 1 0%
Vcc=5.0V± 10%
Typ
Propagation Delay.
Any input to Y
-
tpLH
tpHL
Input Capacitance
GIN
Power Dissipation Capacitance *
Gpo
CL=50pF
RL =1 kO
Min
Min
Max
29
34
11
18
22
·5
(per gate)
Max
19
15
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
89
II
27.
KS54AHCT
KS74AHCT
Triple 3-lnput NOR Gates
FEATURES
e
e
e
e
e
e
•
DESCRIPTION
Function, pin-out, speed and drive compatibility with
54174ALS logic family
Low power consumption characteristic of CMOS
High-Drive-Current outputs:
IOl =8 mA @ VOL =O.5V
Inputs and outputs interface directly with TTL, NMOS
.and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
Package options include" small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
These devices contain two independent 3·input NOR gates.
They perform the Boolean functions Y=A+B+C or
Y=Aei3eC in positive logic.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
1A
1A
Vee
1B
1C
2A
1Y
2B
3C
2C
38
2Y
3A
GND
3Y
(1)
'B~
(12)
1Y
1C (13)
2A~
2B~2Y
2C
(5)
3A
(9)
3C
(11)
3A~3Y
•
FUNCTION TABLE
(Each Gate)
INPUTS
OUTPUT
A
B
C
y
H
X
X
L
X
H
X
L
X
X
H
L
·L
L
L
H
ci$SAMSUNG
Electronics
.
90
KS54AHCT
KS74AHCT
27
Triple 3-lnput NOR Gates
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
i;35 mA
Continuous Current Through
Vee or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Max 500 ns
Input Rise & Fall Times, tr , tt
• Absolute Maximum Ratings are those values beyond
whieh permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 10% Unless Otherwise Specified)
Ta =25°C
Test Conditions
KS74AHCT
KS54AHCT
Ta = - 40°C to + 85°C Ta = - 55°C to + 125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OIlA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=201lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
IlA
Maximum Quiescent
Supply Current
lee
2.0
20.0
40.0
Il A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Iec
Vee Vee -0.1
4.2
3.98
0
VIN=Vee or GND
10UT=01lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10UT=OIlA
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r , tt':;;2 ns), AHCT27
KS54AHCT
KS74AHCT
T. =25 0 C
Ta = -40°C to +85°C Ta = -55°C to +125°C
Unit
Symbol Conditions t Vcc=5.0V
Vcc=5.0V± 10%
Vcc=5.0V±10%
Typ
Propagation Delay,
Any input to Y
~
Input Capacitance
CIN
Power Dissipation Capacitance·
CL=50pF
tpHL
CPD
Min
14
10
16
15
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
Min
Max
17
20
ns
pF
5
(per gate)
Max
8
pF
fin.
91
II
KS54AHCT
KS74AHCT
30
8-lnput Nand Gate
FEATURES
DESCRIPTION
• Function, pirH)ut, speed and drive compatibility with
54/74AlS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.SV to S.5V
• Characterized for operation over industrial and
military temperature ranges:
KS14AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
The '30 contains a single a-input NANO gate. It performs
the boolean functions (in positive logic):
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
Y=A·B·C·O·E·F·G·H
Y=A+B+C+D+E+F+G+H
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps. to Vcc and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
A
A
Vee
2
B
NC
3
C
H
4
D
G
5
E
INC
6
F
NC
11
y
GND
12
B
C
G
H
FUNCTION TABLE
Inputs A Through H
All Inputs
One or more inputs
Output Y
H
L
dCSAMSUNG
". Electronics
L
H
9"2
KS54AHCT
KS74AHCT
30
8-lnput Nand Gate
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee •........ -0.5V to +7V
DC Input Diode Current. hK
(V, < -0.5V or V, > Vce +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vee +0.5V) . . . .
±35 mA
Continuous Current Through
Vee or GND pins
± 1 25 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage. Vee . . . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages". V'N. VOUT . . OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
.. Max 500 ns
Input Rise & Fall Times. tr • tf
.. Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vec=5V± 10% Unless Otherwise Specified)
Ta=25°C
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
V'H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V'L
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
V'N = V'H or V'L
10=- 2OIAA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
V'N=V'H or V'L
10=201AA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
V'N=Vee or GND
±0.1
±1.0
±1.0
IAA
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
IAA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
b.lee
Vee Vee -0.1
4.2
3.98
V'N=Vee or GND
10UT=0",A
per input pin
V,=2.4V
other Inputs:
at Vcc or GND
10uT=01AA
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr • t~2 ns). AHCT30
KS74AHCT
KS54AHCT
Ta =25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Conditions
t
Unit
Symbol
Vcc=5.0V
Vcc=5.0V:t: 10%
Vcc=5.0V:t:10%
Typ
Propagation Delay
Input CapaCitance
Power Dissipation Capacitance"
Min
Max
Min
Max
6
11
14
tPHL
6
11
14
C'N
Cpo
5
15
~ CL=50pF
.. Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2
t For AC switching test circuits and timing waveforms see section 2.
ns
pF
pF
fin.
93
II
'I,
KS54AHCT
KS74AHCT
32
Quad 2-lnput OR Gates
FEATURES
DESCRIPTION
• Function, pifH)ut, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2-input OR gates,
They perform the Boolean functions Y=A+B or y=A.S,
PIN CONFIGURATION
These devices provide speeds and. drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL. NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damaged due
to static discharge by internal diode clamps to Vee and
ground.
LOGIC DIAGRAM
1A
Vee
18
48
1Y
4A
2A
4Y
28
38
2Y
3A
GND
3Y
1)
1A(2)
18
~
3)
\
1Y
2A~
28~2Y
3A~3Y
38~
4A(~
48(~4Y
FUNCTION TABLE
(Each Gate)
Inputs
Outputs
A
B
Y
H
X
L
X
H
L
H
H
L
c8SAMSUNG
Electronics
94
'KS54AHCT
KS74AHCT
32
Quad 2-lnput OR Gates
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Supply Voltage Range Vee, . . .
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±35 mA
. Continuous Current Through
Vee or GND pins
± 1 25 mA
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ..... 500 mW
Plastic Package (N): -12mW/o C from 65 ° C to 85 ° C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages *, VIN, Vour . . OV to Vce
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C~ +125°C
... Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Test Conditions
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/lA
lo=.,-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O /lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/lA
Maximum Quiescent
Supply Current
lee
2.0
20.0
40.0
/lA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.6.lee
Vee Vee -0.1
4.2
3.98
0
VIN=Vce or GND
10ur=0/lA
per input pin
VI=2.4V
other Inputs:
at Vce or GND
10ur=0/lA
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r , tf~2 ns). AHCT32
KS74AHCT
KS54AHCT
T. =25°C
T. = -40°C to +85°C Ta = -55°C to +125°C
Symbol Conditionst Vcc=5.0V
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Propagation Delay
tpLH
f----
CL=50pF
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
Min
Max
17
9
14
17
ns
pF
pF
15
* Cpo determines the no-load dynamic power dissipation: Po=CPD Vce 2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG.
Electronics
Min
14
5
(per gate)
Max
8
fin.
95
II
4'I:,
1
KS54AHCT
KS74AHCT
"
B.CD-to Decimal Decoder
FEATURES
DESCRIPTION
•
•
•
•
The' 42 decoder accepts for active-high BCD inputs and
provides 1 0 mutually exclusive active-low outputs, as
shown by logic symbol or diagram. The active-low outputs facilitate addressing otherMSI units with a9tive low
input enables .
•.
•
•
•
•
•
Full decoding of Input Logic
All outputs are High for Invalid BCD Conditions
Also for application as 3-Line to 8-Line Decoders
Function, pin-out, speed and drive compatibility with
54/74ALS logic family
Low power consumpti0!l. characteristic of CMOS
High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4:5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The logiC design of the '42 ensures that all outputs are
high when binary codes greater than nine are applied to
the inputs.
The most significant input, D, produces a useful inhibit function when the '42 is used as a 1-of·a decoder. The D input can also be used as the Data input in an a-output
demultiplexer application.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc 'and
ground.
0
Vee
A
B
3
4
C
0
5
9
6
8
LOGIC DIAGRAM
GND
FUNCTION TABLE
Inputs
No.
Outputs
D
C
B
A
0 1 2 3 4 5 6 7 8 9
0
1
2
3
4
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
L
H
L
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H H H H
H H H H
H H H H
.L H H H
H L H H
5
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H L H
H L H
H H L
H H L
H H H
H H H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
6
7
a
9
INVALID
c8SAMSUNG
Electronics
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H'H
H H
H H
H H
H H
H H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
96
KS54AHCT
KS74AHCT
42
BCD-to Decimal Decoder
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ....... -0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee. +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . . .
±35 mA
Continuous Current Through
± 125 mA
Vee or GND pins . . . . . . . . . .
Storage Temperature Range, TSlg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc ........... : .. 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vcc
Operating Temperature
Range
KS74AHCT: --40°C to +85°C
KS54AHCT: -55°C to +125°C
.... Max 500 ns
Input Rise & Fall Times, t r , tf ..
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
~Characteristic
Symbol
(Vec=5V±10% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20",A
lo=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20",A
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
±0.1
±1.0
±1.0
",A
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Maximum Input
Current
hN
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
AC
~Ice
ELECTRICA~
Vee Vce -0.1
4.2
3.98
0
VIN=Vee or GND
VIN=Vee or GND
10UT=0",A
per input pin
VI=2.4V
other Inputs:
at Vce or GND
IOUT=O",A
:
CHARACTERISTICS
Characteristic
(Input t r , tf~2 ns), AHCT42
KS54AHCT
KS74AHCT
Ta =25°C
T. = - 40°C to + 85°C Ta = -55°C to +125°C
Unit
Symbol Conditions t Vcc=5.0V
Vcc=5.0V± 10%
Vcc=5.0V± 10%
Typ
Propagation Delay,
Any input to Y
~
Min
Max
Min
Max
tpLH
11
18
22
tpHL
11
18
22
r - - - - CL=50pF
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
5
(per gate)
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vce 2 fin.
t For AC switching tes~ circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
97
I
Dual AND-OR-Invert Gates
and Dual AND-OR Gates
KS54AHCY/51158
KS74AHeT ' . "
FEATURES
DESCRIPTION
- Function, pin-out, speed and drive compatibility with
54174ALS logic family
- Low· power consumption characteristic of CMOS
- High-Drive-Current outputs:
IOL =8 rnA @ VOL =O.5V
- Inputs and outputs interf~ce directly with TTL, NMOS
and CMOS devices
- Wide operating voltage range: 4.5V to 5.5V
- Characterized for operation O\fer industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '51 performs the following Boolean functions:
1 Y=(1 A-1 B-1 C)+(1 0-1 E-1 F)
2Y=(2A-2B)+(2C-20)
The '58 performs:
1 Y=(1 A-1 B-1 Cj+(1 0-1 E-1 F)
2Y=(2A-2B)+(2C-2D)
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels . .;rhe input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAMS
PIN CONFIGURATION
'51
1A
Vee
1A
1B
1C
2A
1C
28
18
2C
1F
20
1E
2Y
10
GNO
1Y
1Y
10
1E
1F
2A---'=-'----'.........
28--'J
2C
20--L--~
FUNCTION TABLES
'58
Inputs
1----
Output 1Y
1A
1B
1C
1D
1E
1F
'51
'58
H
X
H
X
H
X
X
H
X
H
X
L
L
H
H
H
L
Any other combination
H
I
2A-----.:.::~.........
Inputs.
- - - - - - - ..
2C
2B
2A
I
I
H
X
H
X
X
H
Output 2Y
2D
'51
'58
X
L
L
H
H
H
L
H
Any other combination
c8SAMSUNG
Electronics
2B
----.,~
98
KS54AHCT
KS74AHCT
51158
I.
Dual AND-DR-Invert Gates
and Dual AND-OR Gates
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI <: -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V <, Vo < Vee +0.5V)
±35 mA
Continuous C~rrent Through
Vee or GND pins. . ..
±125 mA
Storage Temperature Range, T5 tg . . . -65°Cto +150°C
Power Dissipation Per Package, Pdt
500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may_ occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (eitner Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
KS54AHCT
KS74AHCT
Ta:;; -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
Vec -0.1
3.84
Vce -0.1
3.7
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
liN
Maximum Quiescent
Supply Current
Icc
VIN=VIH or VIL
lo=-20~A
lo=-4mA
Vcc Vee -0.1
4.2
3.98
I
V
VIN=VIH or VIL
Additional Worst
Case Supply
Current
.t:..lce
lo=20~A
lo=4mA
lo=8mA.
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=Vce or GND
±0.1
±1.0
±1.0
~A
2.0
20.0
40.0
~A
2.7
2.9
3.0
mA
0
VIN=Vee or GND
louT=O~A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
IOUT=O~A
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr , tf~2 ns), AHCT51, AHCT58
KS54AHCT
KS74AHCT
T. =25°C
T. = - 40°C to + 85°C T.
55°C to + 125°C
Unit
Symbol Conditionst Vcc=5_0V
Vcc=5.0V±10%
Vcc=5.0V± 10%
=-
Typ
Propagation Delay
tpLH
f----
CL=50pF
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per gate)
Min
Max
Min
Max
9
15
18
9
15
18
ns
5
pF
15
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
99
I
.
.
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
KS54AHCT73
KS74AHCT
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10l =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
.
(Available Tape & Reel), standard DIPs.
These devices contain two independent J-K negative-edgetriggered flip-flops. A low level at CLR input resets the outputs regardless of the levels of the other inputs. When CLR
is inactive (high), data at the J and K inputs meeting the
setup time reqUirements are transferred to the outputs on
the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to
the rise time of the clock pulse. Following the hold time
interval, data at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile flip-flops
can perform as toggle flip-flops by tying J and K high.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN· CONFIGURATION
lCLK
FUNCTION TABLE
lJ
lClR
10
1K
10
GND
Vee
2ClK
2ClR
2K
20
2J
20
--=-ClR
L
H
H
H
H
H
Inputs
ClK
X
+
+
+
+
H
Outputs
J
K
Q
Q
X
L
H
L
H
X
X
L
L
H
H
X
L
H
00
0
0
L
H
H
L
TOGGLE
0
00
0
LOGIC DIAGRAM
ClR
o
K
c
C
c~
c
c8SAMSUNG
Electronics
100
KS54AHCT
KS74AHCT
73
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vee, ....... -0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended .Operating Conditions
Supply Voltage, Vee . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125J>C
Input Rise & Fall Times, t r , t, . .. . .... Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20",A
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
4.0
40.0
80.0
",A
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
lee
.6.lee
VIN=Vee or GND
louT=O",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
louT=O",A
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
101
II
KS54AHCT,73
KS74AHCT
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
AC. ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input tr , tf~2 ns),AHCT73
KS74AHCT
KS54AHCT
Ta =25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Unit
Vcc=5.0V
Vcc:;:5.0V± 10%
Vcc=5.0V±10%
Typ
Min
fmax
45
30
Propagation Delay,
ClK to Q or
~
10
17
20
10
17
20
Propagation Delay,
ClR to Q or
~
10
17
20
10
17
20
Maximum Clock Frequency
a
tpHl
a
Setup Time
before ClK~
tpHl
I J or K
I ClR
tsu
Inactive
Hold Time, J or K after ClK~
Pulse Width
Cl=50pF
IClK High or low
IClR low
th
tw
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per flip-flop)
Max
Min
Max
25
8
13
15
8
13
15
-3
0
0
8
13
15
8
13
15
MHz
ns
ns
ns
ns
ns
5
pF
40
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
102
KS54AHCT
KS74AHCT
74
Dual D-Type Positive-Edge-Triggered
Flip-Flops with Preset and Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High·Orive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain two independent positive· edgetriggered D-type flip-flops. Each flip-flop has its own data,
clock, preset and clear inputs and complementary Q and
Q outputs. The preset and clear inputs are active-low and
operate independently of the clock. Data at the D input is
transferred to the Q outputs on the positive transition of
the clock, provided setup requirements have been met.
Vee
1D
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
.
FUNCTION TABLE
PIN CONFIGURATION
1CLR
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
2CLR
1CLK
2D
1PRE
2CLK
10
2PRE
16
20
GND
20
..
--=~--
PRE
L
H
L
H
H
H
H
H
Inputs
Outputs
= = - - - - - - - - . - - - t---~.---=--
ClR
H
L
L
H
H
H
H
H
ClK
0
Q
X
X
X
X
X
X
t
H
L
L
H
X
X
X
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
+
Q
* Both outputs will remain high as long as PRE and CLR are low,
but the output states are unpredictable if PRE and CLR go high
simultaneously.
LOGIC DIAGRAM
~--------------------------~------~
CLK~;
o
D-------I
eLR----------------~------------------------------~
c8SAMSUNG
Electronics
103
I
Dual D..Type Positive-Edge-Triggered
Flip-Flops with Preset and Clear
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V) . . .
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
.. ± 125 mA
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per Package, Pdt .. , ... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
Range
KS74AHCT; -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, t r , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
KS74AHCT
KS54AHCT
Ta = -40°C to +85"C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/AA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/AA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
/AA
Maximum Quiescent
Supply Current
Icc
4.0
40.0
80.0
/AA
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
Alec
VIN=Vee or GND
10uT=0/AA
per input pin
V,=2.4V
other Inputs:
at Vee or GND
10uT=01lA
-c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
104
KS54AHCT
KS74AHCT
74
Dual D-Type Positive-Edge-Triggered
Flip-Flops with Preset and Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
Maximum Clock
Fr~quency
Symbol Conditions t
f max
Propagation Delay,
ClK to a or
~
Propagation Delay,
PRE or ClR to a or Q
~
tpHL
a
Setup Time
before ClKt
tpHL
I Data
JPRE or ClR Inactive
Hold Time, Data after ClKt
Pulse Width
I elK
High or low
IPRE or ClR low
(Input tr , tf~2 ns), AHCT74
tsu
CL=50pF
KS74AHCT
KS54AHCT
T.=25°C
Ta = - 40°C to + 85°C Ta= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V% 10%
Vcc=5.0V%10'Yo
Typ
Min
55
13
34
Max
Min
Max
30
MHz
18
18
19
9
17
18
9
17
18
13
19
7
12
15
5
8
10
th
0
0
0
tw
9
9
14
17
15
17
ns
ns
ns
ns
ns
Input Capacitance
CIN
5
pF
Power Dissipation CapaCitance *
Cpo
40
pF
* Cpo determines the no-load dynamic power dissipation: PO=CPD VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2. -
c8SAMSUNG'
Electronics
I
105
177.
KS54AHCT '7J:
KS74AHCT. I ~/j
4-Bit Bistable Latches
DESCRIPTION
FEATURES
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
, IOL 8mA @ VOL O.5V
• Inputs and outputs Interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
=
The '75 and '77 consist of 4 high-speed Ootype latches
that can be used as temporary storage for binary information between processing units. The '75 features complementary a and Q output while the '77 features single
nail output. These devices are ideal for high component
density application.
=
The latches are transparent: when the enable (E) is high,
the a output will follow the data input. When the enable
goes low, the output latches at the level that was set up
at the O-input.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
'75
FUNCTION TABLE
'77
10
10
10
10
Inputs
10
2D
20
20
20
20
0
E
a
E3 . 4
E'.2
E3· 4
E"2
Vee
qNO
L
L
H
H
H
H
H
L
X
L
00
00
Vee
GNO
3D
NC
3D
40
3Q
4'£)
30
30
NC
40
40
4Q
Outputs
Q*
*0: '75 only
'75
D
Q
LOGIC DIAGRAM
r-- ---- -.----,
I
E
I
I
I
I
COMMON TO ONE
OTHER LATCH
I
I
L-- _________ .l
'77
D
Q
r ---- - - - - - - - - :
E
:
I
COMMON TO ONE
OTHER LATCH
I
I
L _ _ _ _ _ _ _ _ _ _ _ _ -'
cRSAMSUNG
•• Electronics
106
KS54AHCT
KS74AHCT
75177
4-Bit Bistable Latches
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW{OC from 65°C to 85°C
Supply Voltage Range Vcc, ....... -0.5V to +7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Va > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Va < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, Tstg . . . - 65 ° C to + 150 ° C
Power Dissipation Per Package, Pdt . . . .
500 mW
Recommended Operating Conditions
Supply Voltage, Vcc
.... .. ..
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf . .
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 10% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
Minimum High-Level
Input Voltage
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
~utput Voltage
VOH
VIN = VIH or VIL
lo=- 2OflA
lo=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN = VIH or VIL
lo=20flA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
flA
Icc
VIN=VCC or GND
louT=OflA
8.0
80.0
160.0
flA
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
per input in
VI=2.4V
. .t:.lec other Inputs:
at Vcc or GND
lour = OflA
=8SAMSUNG
Electronics
Vee Vce-0. 1
4.2
3.98
0
107
I
'71:177
KS54AHCT
KS74AHCT I ~I
j
4-Bit Bistable, Latches
.
AC' ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r • t~2 ns). AHCT75
KS74AHCT
KS54AHCT
T.=25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Vee=5.0V
Unit
Vee = 5.0V::!:: 10%
Vee=5.0V::!:: 10%
Typ
Min
Max
Min
Max
10
16
20
10
10,5
16
20
15
18
tpHL
9
15
18
Data Set up Time D to Enable
tsu
Data Hold Time Enable to D
th
6
10
CIN
5
Propagation Delay
E to Q or
a
Propagation Delay
D to Q or Q
Input Capacitance
~
CL=50pF,
~
CL=50pF
tpHL
10
12
0
Characteristic
Propagation Delay
E to Q
Propagation Delay
D toO'
Symbol
Conditions t
~
CL=50pF
tpLH
r---tPHL
CL=50pF
tPHL
ns
pF
pF
(Input tr • tf~2 ns), AHCT77
KS54AHCT
KS74AHCT
Ta=25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Unit
Vee = 5.0V
Vee 5.0V::!:: 10%
Vee=S.OV::!:: 10%
=
Typ
8
Max
Min
Max
17
8
14
8
13
17
15
8
13
15
6
0
Input Capacitance
CIN
5
Power disipation Capacitance *
Cpo
tsu
Min
14
th
Data Set up Timejl-kJc-nable
Data Hold lTme Enable to D
ns
ns
10
Power disipation Capacitance *
Cpo
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
AC ELECTRICAL CHARACTERISTICS
ns
12
10
0
5
0
ns
ns
ns
6
ns
pF
pF
* Cpo determines the no·load dynamic power dissipation: Po=Cpo VCC 2 ' fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
108
KS54AHCT
KS74AHCT
76
Dual J-K Flip-Flops with Preset and Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10l =8 rnA @ VOL =O.5V
• Inputs and outputs interface directty with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These parts consist of two negative-edge-triggered J-K flipflops with Independent J, K, preset, clear and clock inputs
and complementary outputs. The J-K inputs at each flipflop are enabled when the clock goes high. The input data
are transferred to the outputs on the negative-going edge
of the clock pulse, provided the setup requirements have
been met.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
I
FUNCTION TABLE
PIN CONFIGURATION
lCU<
lK
lPRE
10
lClR
lJ
lQ
Inputs
GND
Vee
2K
2CU<
2PRE
20
20
2ClR
2J
Outputs
PRE
CLR
CLK
J
K
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
H
L
H*
L
H
H*
~
L
L
H
H
00
0
~
L
H
L
H
H
L
L
H
TOGGLE
H
X
X
00
~
~
0
0
0
• Both outputs will remain high as long as preset and clear are low,
but the output states are unpredictable if preset and clear go high
simultaneously.
LOGIC. DIAGRAM
K
C
e
c~
PRE------------~--------~
c8 !e!'lSUNG
e
109
KS54AHCT '7~
KS74AHCT IU,'
Dual J-K Flip-Flops with Preset and Clear
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/o C from 65°C to 85°C
Supply Voltage Range Vee. . ...... -0.5V to + 7V
DC Input Diode Current. hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
. . . . . . . . . . . .. ± 125 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage. Vee . . . . . .
4.5V to 5.5V
DC Input & Output Voltages·. VIN. VOUT .. OV to Vec
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times. tr • tf . . ..
. .. Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 10% Unless Otherwise Specified)
Ta.=25°C
Test Conditions
Typ
KS74AHCT
KS54AHCT
T a =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
4.0
40.0
80.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.6.lee
VIN=Vee or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lOUT = O",A
=8SAMSUNG
Electronics
Vee Vee -0.1
3.98
4.2
0
110
KS54AHCT
KS74AHCT
76
Dual J-K Flip-Flops with Preset and Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr , tf~2 ns), AHCT76
Symbol Conditions t
KS54AHCT
KS74AHCT
T.=25°C
T.= -40°C to +85°C Ta= -55°C to +125°C
Unit
Vcc=5.0V
Vee =5.0V± 10%
Vcc=5.0V±10%
Min
Typ
Min
,Maximum Clock Frequency
f max
45
30
Propagation Delay,
ClK to Q or 0
tpLH
17
20
I---
10
10
17
20
Propagation Delay,
PRE or ClR to Q or Q
I---
tpLH
10
17
20
tpHL
10
17
20
Setup Time
before ClK.j.
IJ or K
IPRE or CLR Inactive
Hold Time, Data after ClK.j.
Pulse Width
IClK High or low
IPRE or CLR low
tpHL
CL=50pF
tsu
th
tw
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
17
20
10
17
20
-3
0
0
8
13
15
8
13
15
.qsSAMSUNG
Electronics
MHz
ns
ns
ns
ns
ns
pF
pF
40
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2
t For AC switching test circuits and timing waveforms see section 2 .
Max
25
10
5
(per flip-flop)
Max
fin.
I
111
'KS54AHCT 78~
KS74AHCT
Dual J~K Flip-Flops with Preset,
Common Clear'; Common· Clock
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74AlS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOl =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V t05.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These parts consist of two negative·edge-triggered J-K flipflops with independent J, K and preset inputs and complementary outputs. The clear and clock inputs are common to both flip-flops. The J-K inputs are enabled when
the clock goes high. The input data are transferred to the
outputs on the negative-going edge of the clock pulse, provided the setup requirements have been met.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
. CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components .
A" inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
PIN CONFIGURATION
Inputs
ClK
1K
1PRE
10
1J
1~
Vee
GND
ClR
2J
2PRE
2'0
2K
20
I
Outputs
CLR
ClK
J
K
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
H
H
L
H
H*
00
00
+
+
X
L
H
L
H
H
L
H*
H
X
X
+
~
!
--'
PRE
H
L
H
L
TOGGLE
00
.00
* Both outputs will remain high as long as preset and clear are low,
but the output states are unpredictable if preset and clear go high
simultaneously.
LOGIC DIAGRAM
K
c
c
c~
PRE----------~--------~
c8SAMSUNG
Electronics
c
112
KS54AHCT
KS74AHCT
78
Dual J-K Flip-Flops with Preset,
Common Clear &. Common Clock
Absolute Maximum Ratings*
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V) . . .
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . .
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee .............. 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf ...... .
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
whieh permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Test Conditions
KS54AHCT
KS74AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OIolA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2OIolA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
lolA
Maximum Quiescent
Supply Current
lee
4.0
40.0
80.0
lolA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.6.lee
VIN=Vee or GND
10UT=01olA
per input pin
VI=2.4V
other Inputs:
at Vec or GND
10UT=01olA
Vee Vee -0.1
4.2
3.98
0
--
=8SAMSUNG
. Erectronics
113
II
. Dual J-K Flip-Flops with Preset,
Common Clear & Common Clock
KS54AHCT·::¥8
KS74AHCT
AC ELECTRICAL CHARACTERISTICS
(Input t r ,
KS74AHCT
KS54AHCT
T.=25°C
T.= -40°C to +85°C T.= -55°Cto +125°C
Unit
Symbol Conditions t Vce=5.0V
Vee=5.0V:t10%
Vee = 5.0V:t 10%
Characteristic
f maX
Maximum Clock Frequency
Propagation Delay,
elK to Q or Q
tpLH
r--CL=50pF
tpHL
Propagation Deiay,
PRE or ClR to Q or Q
~
Setup Time
before ClK-l-
Pulse Width
tPLH
IJ or K
-
..
IClK High or low
IPRE or ClR low
tsu
th
- - - -f---.
tw
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
Typ
Min
45
30
- - - - - _...
Max
MHz
17
10
17
10
17
10
17
-3
0
8
13
8
13
20
_- _
10
.... _ - - - -
ns
20
1 - - - - - - - -I - - -
20
--
ns
20
----
20
--
r--ns
20
- - - - - - --_._._-
0
-------._- - - - - - - -
------
--
15
_._---
------
ns
ns
15
pF
pF
40
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2
Min
25
17
10
5
(per flip-flop)
Max
17
10
r--------I-.
tpHL
IPRE or ClR Inactive
Hold Time, J or K after ClK-l-
tf~2 ns), AHCT78
fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
i
114
KS54AHCT
KS74AHCT
86
Quad 2-lnput Exclusive-OR Gates
DESCRIPTION
FEATURES
• Function, pin-out, speed and drive compatibility with
S4/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.SV
• Inputs and outputs interface directly with TTL, NMOS
, and CMOS devices
• Wtde operating voltage range: 4.SV to S.SV
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KSS4AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
These devices contain four independent 2,·input ExclusiveOR gates. They perform the Boolean functions y=A$B or
y=AB+AB.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to .
static discharge by internal diode clamps to Vee andground.
LOGIC DIAGRAM
1A
Vee
18
48
1Y
4A
2A
(2)
1A~
18
I
1Y
2A~
28 (5)
2Y
4Y
28
38
2Y
3A
GND
3Y
38 (10)
3A~
3'0'
4A~
48 (13)
4Y
FUNCTION TABLE
(Each Gate)
Inputs
Output
Y
A
B
L
L
L
L
H
H
H
L
H
H
H
L
c8SAMSUNG
Electronics
115
KS54AHCT86
KS74AHCT
Quad 2-lnput Exclusive-OR Gat$s
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) . . .. ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . .
± 125 mA
Storage Temperature Range, T8 1g ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vec . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN, Your .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
KS54AHCt
KS74AHCT
Ta: -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10==-20jJA
10==-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20jJA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
jJA
2.0
20.0
40.0
jJA
2.7
2.9
3.0
mA
Maximum Quiescent
. Icc
Supply Current
Additional Worst
Case S.upply
Current
Ll.lee
VIN=Vee or GND
10uT=OjJA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=OjJA
c8SAMSUNG
Bectronics
Vee Vee -0.1
4.2
3.98
0
116
'KS54AHCT
KS74AHCT
86
Quad 2-lnput Exclusive-OR Gates
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr ,
Ta =25°C
Vcc =5.0V
Typ
tt .... 2 ns), AHCT86
KS74AHCT
Ta= -40°C to +85°C
Vcc=5.0V±10%
Min
Max
KS54AHCT
Ta=-55°Cto +125°C
Vcc=5.0V± 10%
Min
tpLH
10
16
19
tpHL
10
16
19
10
16
10
16
20
20
Propagation Delay,
A or B to Y (Other Input Low)
r----
Propagation Delay,
A or B to Y (Other Input High)
~
CL=50pF
tPHL
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per flip-flop)
Unit
Max
ns
ns
5
pF
15
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 ' fin.
t For AC switching test circuits and timing waveforms see section 2.
II
c8SAMSUNG
Electronics
,
117
KSS4AHCT
KS74AHCT
90192193
Oecade,Oivide by 12, and
Binary Counters
FEATURES
DESCRIPTION
• Various counting mode.
These devices contain four master-slave flip· flops and addition gating to provide a divide by a counter and a threestage binary counter for which the count cycle length is
divide by five for the. AHCT90, divide by six for the
AHCT92, and divide by eight for the AHCT93, All of these
counters have a gated zero reset and the AHCT90 also
has gated set·to·nine inputs for use in BCD nine's complement applications.
To use their maximum count length (decade, divide-bytwelve, or four bit binary), the CKB input is connected to
the QA output. The input count pulses are applied to CKA
~nd the outputs are as described in the appropriate truth
table. A symmetrical divide·by-the count can be obtained
from the AHCT90 counters by connecting the Qo output
to the CKA input and applying the input count to the CKB
input which gives adivide-by-ten square wave at output
• Function, Pin-out, speed and drive compatibility with
54174 ALS logic family.
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
ioL =8mA @ VOL=O.5V
• Input and output interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
• Package options include plastic "small outline"
packages, standard plastic and ceramic 3t10-mil DIPs
QA.
PIN CONFIGURATION
'90
'92
'93
CKA
CKB
CKA
CKB
MR1
NC
NC
NC
MR1
NC
MR2
Q,
Q,
MR2
QA
NC
QD
Vee
GNO
QB
Vee
GND
NC
Vee
CKA
QD
GND
MS1
QB
MR1
Qe
NC
QB
MS2
'Q e
MR2
QD
NC
Qc
:8~SUNG
118
KS54AHCT
KS74AHCT
90192193
Decade, Divide by 12, and
Binary Counters
FUNCTION TABLE
'90
'90
'92
BCD COUNT SEQUENCE
(See Note A)
BI-QUINARY (5-2)
(See Note B)
COUNT SEQUENCE
(See Note C)
Output
Count
0
1
2
3
4
5
6
7
8
9
Qc
Qs
QA
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
L
L
Output
Count
~"-
QD
=:l
0
1
2
3
4
5
6
7
8
9
QA
QD
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
H
H
H
H
Qc
L
L
H
H
L
L
L
H
"H
L
Output
Count
-~--~-~-~-
Qs
L
H
L
H
L
L
H
L
H
L
0
1
2
3
I
4
5
6
7
8
9
10
11
I
QD'
Qc
Qs
QA
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
'93
COUNT SEQUENCE
(See Note C)
Count
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
'90
RESET/COUNT TRUTH TABLE
Output
--
r--~
Reset Inputs
Output
-~
QD
Qc
Qs
QA
MR1
MR2
MS1
MS2
aD
Qc
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
X
X
L
L
X
H
H
X
L
X
X
L
L
X
H
X
L
X
L
X
L
H
L
X
L
X
L
L
H
L
I
I
c8SAMSUNG
Electronics
QA
L
L
L
L
L
COUNT
COUNT
COUNT
COUNT
L
L
H
'92, '93
RESET/COUNT TRUTH TABLE
Reset Inputs
Note A: Output QA is connected to input CKB for BCD count.
Note B: Output QD is connected to input CKA for bi-quinary
count.
Note C: Output QA is connected to input CKB.
Note D: H=High Level, L=Low Level, X=Don't Care.
Qs
Output
MR1
MR2
QD
H
L
X
H
X
L
L
Qc
Qs
L
L
COUNT
COUNT
QA
L
119
II
KS54AHCT
KS74AHCT
90192193
Decade, Divide by 12, and
Binary Counters
LOGIC DIAGRAMS
'90
'92
(6)
MS1:::j[J~______1
MS2 (7)
(14)
CKA - - - - - 1 - - - 6
(9)
CKB_(1_)__~~____~_
.Os
(S)Oe
(11)
00
'93
Note: The J.K inputs shown without connection are for
reference only and are functionally at a high state.
c8SAMSUNG
Electronics
120
~~~::~g~ 90192193
Decade, Divide by 12, and
Binary Counters
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Ceramic Package (J): -12mW/oC from 100°C to 125°C
Supply Voltage Range Vee, ....... -0.5V to +7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V) . . .
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, Your . . OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , t, . . .
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not im~lied. long exposure to these conditions may affect device reliability.
• Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vec=5V± 10% Unless Otherwise Specified)
T.=25°C
Symbol Test Conditions
Typ
KS74AHCT
KS54AHCT
T.= -40°C to +85°C T.= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum low-level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-level
Output Voltage
VOH
VIN=VIH or VIL
10=-20,.,A
10=-4mA
Vee -0.1.
3.84
Vee -0.1
3.7
V
Maximum lOW-level
Output Voltage
VOL
VIN=VIH or VIL
10=20,.,A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
,.,A
Maximum Quiescent
Supply Current
Icc
VIN=Vee or GND
10ur=0,.,A
8.0
80.0
160.0
,.,A
~Iec
per input in
VI=2.4V
other Inputs:
at Vee or GND
10ur=0,.,A
2.7
2.9
3.0
mA
f---
Additional Worst
Case Supply
Current
=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
121
II
KS54AHCT
KS74AHCT
90
Decade Counter
AC ELECTRICAL CHARACTERISTICS' (Input tr • t~2
Characteristic
Symbol
Maximum clock
CKA to OA
Frequency
CKB to Os
Condltlons t
fmax
ns). AHCT90
KS74AHCT
KS54AHCT
TA=25°C
TA= -40°C to +85°C TA= -55°C to +125°C
Unit
Vee=5.0V
Vee = 5.0V:t 1o'Yo
Vee=5.0V:t 10%
Typ
Min
50
40
Max
35
25
20
18
Min
Max
MHz
8
14
17
8
14
17
21
42
50
21
42
50
8
14
17
9
15
18
14
28
33
14
28
33
14
28
33
14
28
33
tpLH
13
25
30
ns
Maximum Propagation
Delay MS to Os. Oc
tpHL
18
35
42
ns
Maximum Propagation
Delay MR to any 0
tpHL
18
35
42
ns
Maximum Propagation
Delay. CKA to OA
~
Maximum Propagation
Delay CKA to 00
~
Maximum Propagation
Delay CKB to Os
~
Maximum Propagation
Delay CKB to Oc
~
tPHL
Maximum Propagation
Delay CKB to 00 .
~
tpHL
Maximum Propagation
Delay MS to OA. 00
f------
Pulse Width
tpHL
tpHL
tpHL
-
CL=50pF
f------
CKA
10
15
20
CKB
20
30
40
10
15
20
10
15
20
24
29
MS
tw
MR
Recovery Time
MR to CKA. CKB
tree
17
Maximum Input Capacitance
CIN
5
Power DiSsipation Capacitance
Cpo
ns
ns
ns
ns
ns
ns
ns
pF
pF
*CPO determines the no-load dynamic dissipation: Po=Cpo Vcc 2 f+lee Vee
For AC Switching test circuits and timing waveforms see sections
t
c8SAMSUNG
Electronics
122
KS54AHCT
KS74AHCT
92
Divide-by· Twelve Counter
AC ELECTRICAL CHARACTERISTICS
Symbol
Characteristic
Maximum clock
CKA to OA
Frequency
CKB to Os
Condltlons t
f max
tpLH
Maximum Propagation
Delay, CKA to OA
,-------
tpHL
(Input tr• tf~2 ns), AHCT92
KS74AHCT
KS54AHCT
TA==25°C
TA= -40°C to +85°C TA= -55°C to +125°C
Unit
Vec=5.0V
Vee = 5.0V:t 10%
Vee==5.0V:t 10%
Min
Typ
Min
50
40
35
25
20
18
Max
Max
MHz
8
-8
13
15
14
17
21
42
48
21
42
48
Maximum Propagation
Delay CKA to 00
~
Maximum Propagation
Delay CKB to Os
~
8
14
16
tpHL
10
15
17
Maximum Propagation
Delay CKB to Oc
tpLH
r-----tpHL
10
14
16
11
16
21
Maximum Propagation
Delay CKB to 00
~
tpHL
Maximum Propagation
Delay MR to any 0
CL=50pF
14
28
33
tpHL
14
20
24
tpHL
18
35
42
CKA
10
~---
Pulse Width
CKB
tw
20
--
15
20
30
40
.-----~
MR
15
20
24
29
tree
17
Maximum Input Capacitance
C,N
5
Power Dissipation Capacitance
Cpo
ns
ns
ns
ns
ns
ns
~-
10
Recovery Time
MR to CKA. CKB
ns
ns
pF
pF
*CPO determines the no-load dynamic dissipation: Po=Cpo Vee2f+lee Vee
t For AC Switching test circuits and timing waveforms see sections
c8SAMSUNG
Electronics
123
I
KS54AHCT
KS74AHCT
93
4-Bit Binary Counter Divide
by Two and Eight
AC ELECTRICAL CHARACTERISTICS
Symbol
Characteristic
Maximum clock
CKA to QA
Frequency
CKB to Os
Condlt/ons t
fmax
(Input tr• tf~2 ns), AHCT93
KS74AHCT
KS54AHCT
TA=25°C
TA= -40°C to +85°C TA= -55°C to +125°C
Unit
Vee 5.0V
Vee = 5.OV:t 10%
Vee=5.0V:t 10% _
=
Typ
Min
50
40
Max
35
25
20
18
Min
Max
MHz
B
B
13
15
tPHL
14
17
tpLH
30
56
70
tpHL
30
56
70
8
14
17
9
15
18
~
16
29
34
tPHL
17
29
34.
Maximum Propagation
Delay CKB to 00
~
24
42
50
tpHL
24
42
50
Maximum Propagation
Delay MR to any 0
tPHL
17
35
42
10
15
20
tw
20
10
30
15
40
24
29
Maximum Propagation
Delay. CKA to OA
~
Maximum Propagation
Delay CKA to 00
r----
Maximum Propagation
Delay CKB to Os
~
Maximum Propagation
Delay CKB: to Oc
tpHL
CKA
Pulse Width
CKB
MR
CL=50pF
Recovery Time
MR to CKA. CKB
tree
17
Maximum Input Capacitance
CIN
5
Power Dissipation Capacitance
Cpo
ns
ns
~
ns
ns
ns
,ns
ns
20
ns
pF
pF
*CPO determines the no-load dynamic dissipation: Po=Cpo Vcc2f+lcc Vcc
t For AC Switching test circuits and timing waveforms see sections
c8SAMSUNG
Electronics
124
KS54AHCT
KS74AHCT
107
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174AlS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized . for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs,
These devices contain two independent J-K negative-edgetriggered flip-flops. A low level at the CLR input resets the
outputs regardless of the levels of the other inputs. When
CLR is inactive (high). data at the J and K inputs meeting
the setup time requirements are transferred to the outputs
on the negative-going edge of the clock pulse. Clock trig- ,
gering occurs at a voltage level and is not directly related
to the rise time of the clock pulse. Following the hold time
interval, data at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile flip-flops
can perform as toggle flip-flops by tying J and K high.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
1J
Vee
10
1CLR
10
, 1K
1CLK
2K
20
2CLR
20
2CLK
GND,
II
FUNCTION TABLE
PIN CONFIGURATION
2J
Inputs
Outputs
ClR
ClK
J
K
a
L
H
H
H
H
H
x
x
L
H
J,
J,
J,
J,
L
H
L
H
X
X
L
L
H
H
X
00
0
H
a
0
H
L
L
H
TOGGLE
00
0
0
LOGIC DIAGRAM
K-I-Jr-_
Q
CLK~:
CLR---------------~ ~----------------~--------~
c8SAMSUNG
Electronics
125
KS54AHCT'
KS74AHCT
107
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . .
±35 mA
Continuous Current Through
Vee or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
......... 4.5V to 5.5V
DC Input & Output Voltages·, Y,N, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C~ +125°C
Input Rise & Fall Times, tr , tf ....
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
ofthe device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 1 0% Unless Otherwise Specified)
0=-J.
KS74AHCT
KS54AHCT
Ta =25 C
Ta = -400C to +85°C Ta = -55°C to +125°C Unit
Test Conditions
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
V,H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V,L
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
V,N=VIH or V,L
10=-20/lA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
V,N=VIH or V,L
lo= 2O/lA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/lA
4.0
40.0
80.0
/lA
2.7
2.9
.3.0
mA
f-----
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
lllee
V'N=Vee or GND
IOUT=O/lA
per input pin
V,=2.4V
other Inputs:
at Vee or GND
lour=O/lA
=8SAMSUNG
Electronics
Vee Vec -0.1
4.2
3.98
0
--
126
KS54AHCT
KS74AHCT
107
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r , tf~2 ns), AHCT107
KS74AHCT
KS54AHCT
Ta=25°C
Ta = -40°C to +85°C To = -55°C to +125°C
Unit·
Vee=5.0V
Vee = 5.0V ± 10%
Vee=5.0V± 10%
--
- - - - r---~-
Maximum Clock Frequency
fmax
Min
45
r--10
30
Max
Min
Max
25
MHz
17
20
10
17
20
tpLH
10
17
tpHL
10
17
~
Propagation Delay,
ClK to Q or Q
Typ
tpHL
CL =50pF
~-
Propagation Delay,
ClR to Q or Q
Setup Time
before ClK~
IJ
or K
I ClR Inactive
Hold Time, J or K after
Pulse Width
ClK~
I ClK High or low
I ClR low
- - 1-------
10
tsu
th
tw
CIN
Power Dissipation Capacitance *
Cpo
17
20
17
20
--c--(per flip-flop)
--
-~
0
0
8
13
15
8
13
5
' - . ..
15
_--
----
40
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
20
--
-3
f--------
ns
-------
---------
10
Input Capacitance
20
ns
- - r--
ns
ns
--
ns
_.- pF
pF
fin.
I
127
KS54AHCT
KS74AHCT
109
Dual J-K Positive Edge-Triggered
Flip-Flops with Preset and Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74AlS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C, to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain two positive,-edge-triggered J-R flipflops with independent preset and clear inputs and complementary Q and Q outputs. The present and clear inputs
are active-low and operate independently of the clock Data
at the J and R inputs are transferred to the ouptutson the
positive transition of the clock provided setup requirements
have been met. These versatile flip-flops can perform as
toggel flip-flops by grounding K and tying J high. They
can also perform as D-type flops if J and R are tied together.
These devices provide speeds and drive capability
equivalent to their ALST \ '_ counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
1CLR
1J
1K
1CLK
1~
10
1Q
GND
FUNCTION TABLE
Inputs
Vee
2CLR
2J
2K
2CLK
2PRE
20
2Q
Outputs
PRE
ClR
ClK
J
K
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
L
H
L
H
X
X
X
X
L
L
H
H
X
H
L
L
H
H*
H*
L
H
TOGGLE
t
t
t
t
L
Q
Qo
0
H
L
Qo
0
0
0
'Both outputs will remain high as long as PRE and CLR are low.
but the output states are unpredictable if PRE and CLR go high
simultaneously,
LOGIC DIAGRAM
PRE----------------------------------~--------~
o
CLK~:
CLR------------------------~~--------------------------------J
c8SAMSUNG
Electronics '
128
KS54AHCT
KS74AHCT
109''
Dual J-K Positive Edge-Triggered
Flip-Flops with Preset and Clear
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) .. ,
±35 mA
Continuous Current Through
Vee or GND pins. ,
±125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt . , , ... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall 'Times, tr , tf
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
Minimum High-Level
Input Voltage
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta = -55°C to + 125°C Unit
Guaranteed Limits
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/AA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/AA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
/AA
Maximum Quiescent
Supply Current
Icc
4.0
40.0
80.0
/AA
2.7
2.9
3.0
mA
Additional Worst
. Case Supply
Current
~Iee
VIN=Vee or GND
10uT=0/AA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10UT=0/AA
c8SAMSUNG
Electronics
,
Vee Vee -0.1
4.2
3.98
0
129
I
Dual J·l? Positive Edge-Triggered'
Flip-Flops with Preset and Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr , tf~2 ns), AHCT1 09
KS74AHCT
KS54~HCT
Ta =25°C
Ta= -40°C to +85°C Ta=-55°Cto +125°C
Symbol Conditions t Vee = 5.0V
Unit
Vee=5.0V:t 10%
Vee=5.0V:t10%
- , -
Maximum Clock Frequency
f max
Propagation Delay,
ClK to
or
tpLH
a
a
Propagation Delay,
PRE or ClR toO or Q
Setup Time
before ClKt
I Data
I PRE or ClR Inactive
Hold Time, Data after ClKt
Pulse Width
IClK High or low
I PRE or ClR low
-
tpHL
-
Min
55
34
r------
17
17
10
10
.... _--
-
--
7
tsu
=8 ~t!'ISUNG
14
1---"'---
10
14
--,,-,-
12
5
8
- - f---------- 1-----.. _--1---
0 0, - -1-.... _
1---"--14
9
th
tw
--I---'
9
CIN
--"-
MHz
15
~
20
-,,----~
20
- -
1---'--
..
1---'--
,
20
ns
20
15
-."
10
0
~-
- - I-----
ns
--
1 - - - - - - - !-----------
- - - - - - r---~~-- - - - - - 1 - '
_~--L,_ _
Power Dissipation Capacitance *
Cpo
40 I
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fin,
t For AC switching test circuits and timing waveforms see section 2.
Input Capacitance
.-
- - - ' - - ~-- --,,-_._- c----- f----,_
Max
30_._. __ .
10
CL =50pF
Min
Max
1 - - ---
tpLH
tpHL
Typ
._.
--,
ns
'-----
ns
.., - , - "..-- , - - - - - - - - - r - - -
17
ns
17
pF
pF
130
KS54AHCT
KS74AHCT
112
Dual J-K Negative-~dge-Triggered
Flip-Flops with Preset and Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
These parts consist of two negative·edge-triggered J-K flipflops with independent J, K, preset, clear and clock inputs
and complementary outputs. The J-K inputs at each flipflop are enabled when the clock goes high. The input data
are transferred to the outputs on the negative-going edge
of the clock pulse, provided the setup requirements have
been met.
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
lCLK
lK
lJ
lPRE
10
10
.20
GND
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
Vee
lCLR
2CLR
2CLK
2K
2J
2PRE
20
Outputs
Inputs
--
-~
Q
PRE
CLR
CLK
J
K
Q
L
H
L
H
H
H
H
L
X
X
X
X
X
X
X
X
X
H
L
H*
L
H
H*
.j.
L
H
L
L
L
00
00
H
L
H
L
H
H
H
1.
H
H
H
H
H
.j.
.j.
H
H
X
~
TOGGLE
I
00
00
* Both outputs will remain high as 10n'g as PRE and CLR are low,
but the output states are unpredictable if PRE and CLR go high
simultaneously.
LOGIC DIAGRAM
PRE------------------------------------~---------_.
o
K
CLR---------------------------*----------------________________~
c8SAMSUNG
Electronics
131
Dual J-K Negative-Edge-Triggered
Flip-Flops with Preset and Clear
KS54AHC'Y'1,12
KS74AHCT
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ....... -O.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI> Vee +0.5V) . . .
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) . .
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . . . . . .
±35 mA
Continuous Current Through
Vee or GND pins .. . .
.. ± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee .............. 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
.
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
, Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
Ta=2S0C
Symbol Test Conditions
Typ
KSS4AHCT
KS74AHCT
Ta= -40°C to +8S oC Ta= -55°C to +12SoC Unit
Guaranteed Limits
Minimum High-Level
Input yoltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND ,
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
4.0
40.0
80.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Alec
VIN=Vee or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
.0
132
KS54AHCT
KS74AHCT
112
Dual J-K Negative-Edge-Triggered
Flip-Flops with Preset and Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r , tf~2 ns), AHCT112
KS54AHCT
KS74AHCT
T.=25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Symbol Condltlons t Vcc=5.0V
Vcc=5.0V%10%
Vcc=5.0V% 10%
Typ
Min
Maximum Clock Frequency
fmax
50-
30
Propagation Delay,
ClK to Q or Q
tPLH
10
17
20
10
17
20
10
17
20
10
17
20
t---
tpHL
Propagation Delay,
PRE orClR to Q or Q
Setup Time
before ClK~
IJ or K
IPRE or ClR Inactive
Hold Time, Data after
Pulse Width
ClK~
IClK High or low
I PRE or ClR low
CL=50pF
~
tpHL
tsu
th
tw
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo (per flip-flop)
Max
Min
Max
25
10
17
20
10
0
17
20
0
0
10
17
20
6
10
15
MHz
ns
ns
ns
ns
ns
5
pF
40
pF
* Cpo determines the no·load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2 .
.c8SAMSUNG
Electronics
II
133
KS54AtlCT
KS74AHCT
123
Dual Retriggerable -Monostable
Multivibrator with Clear
FEATURES
DESCRIPTION
• Simple pulse width formula tw = 0.45RC
DC triggered from active HIGH or active Low inputs
• Retriggerable for very long output pulses up to 100 %
duty cycle
• Overriding clear terminates output pulse
• Schmitt trigger A & B inputs allow infinite rise and
fall times on these inputs
• Functions, pin-out, speed and drive compativility with
54/74ALS logic family
• Low power consumption characteristic of. CMOS
• High drive current outputs:
IOL=8mA @ VOL=0.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range; 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '1 23 contains dual retriggerable monostable
multivibrators with output pulse width control by three
methods.
The basic pulse time is programmed by selection of an externed resistor (Rext) and capacitor (Cext). The external
resistor and capacitor are normally connected as shown
timing component.
Once triggered, the basic output pulse width may be extended by retriggering the gated active Low going edge
input (Ai) or the active HIGH going edge input (Si). Sy
repeating this process, the output pulse period (nQ=HIGH,
nQ=LOW) can be made as long as desired. Alternatively
an output delay can be terminated at any time by a Lowgoing edge on input CLR, which also inhibits the triggering.
An internal connection from CLR to the input gates makes
it possible to trigger the circuit by a positive-going signal
at input CLR as shown in the function table when
CExT>10nF, the typic~1 output pulse width is defined as;
tw=0.45XREXTXCEXT(typ).
Where tw is in seconds. R is in ohm. and C is in fards.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
PIN CONFIGURATION
FUNCTION TABLE
Inputs
~-----
A1
Vee
B1
REXT1/CEXT
ClR1
CEXTl
0"1
Q1
Q2
02
C EXT2
REXT2/CEXT
CLR2
B2
-----------
Outputs
--
------ ---- 1------ -- - - ,
CLR
A
B
Q
a
L
X
X
H
H
t
x
X
X
L
t
H
H
L
L
L
H
H
H
H
X
L
,I.
L
Jl.
lS
JL
1l..
U
U
A2
H=
L=
X=
t=
,1.=
Il.=
1S=
=8~SUNG
HIGH voltage level
LOW voltage level
don't care
LOW to HIGH transition
HIGH to LOW transition
one HIGH level output pulse
one LOW level output pulse
134
KS54AHCT
KS74AHCT
123
Dual Retriggerable Monostable
Multivibrator with Clear
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package(N}: -1 2mW/o C from 65 0 C to 85 0 C
Supply Voltage Range Vcc, ..
-0.5V to +7V
DC Input Diode Current, 11K
(VI<-0.5V or VI>Vcc+0.5V) ..
±20 rnA
DC Output Diode Current, 10k
(Vo<-0.5V or Vo>Vcc+0.5V)
±20 rnA
Continuous OUtput Current Per Pin, 10
(-O.5V-_ _~(6:...)_ _
2Y
>-_ _(:....8)'-----'
3Y
~_---'\'-11.....;.)-_ 4Y
137
1251126
.
KS54AHCT
KS74AHCT' .
Quad 3-State Buffers
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vee,
.... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI> Vee +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V·< Vo < Vee +0.5V) .. .
±70 mA
Continuous Current Through
Vee or GND pins. . . . . . . . . . . . . .
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
... 4.5V to 5.5V
DC Input & Output Voltages·, VIN, Vour : . OV to Vce
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
KS74AHCT
KSS4AHCT
Ta= -40°C to +8S oC Ta=-SSOCto +12SoC Unit
Ta =2SoC
Test Conditions
Typ
Minimum High-Level
I~~~ Voltag~ ______
Maximum Low-Level
Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
2.0
V
2.0
---~--------
0.8
VIL
-
0.8
-~----------.-
---~--
----
0.8
V
- - 1 - - - _ . - - - - - - - - - - - - - - -----
VOH
VOL
hN
Maximum 3-State
Leakage Current
loz
Additional Worst
Case Supply
Current
2.0
VIH
- - - - - - - - - - _ . _ - - - - --------
Maximum Input
Current
Maximum Quiescent
Supply Current
Guaranteed Limits
VIN=VIH or VIL
10=-20j.lA
10= -6mA
VIN=VIH or VIL
10=20j.lA
10=12mA
10=24mA
VIN::::::Vee or GND
Vee Vee -0.1
4.2
3.98
Vee -0.1
3.84
- - f - - - - - - - - - - - - f-----
0
0.1
0.26
0.39
0.1
0.33
0.5
--_._--------.-
±0.1
±1.Q
Vee -0.1
3.7
--~~----
V
------ ---_. _ . -
0.1
0.4
V
-------------- -
±1.0
j.lA
._- . -
Icc
~Iee
Output Enable
=VIH
Vour=Vcc or GND
VIN=Vee or GND
10ur=Oj.lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=Oj.lA
c8SAMSUNG
Electronics
±0.5
±5.0
·±10.0
8.0
j.lA
--_ ...__ . _ -
--
80.0
160.0
r--'--
j.lA
- - r------
2.7
2.9
3.0
mA
138
KS54AHCT
KS74AHCT
125.112_6
AC ELECTRICAL CHARACTERISTICS
Characteristic
Condltlons l
Symbol
Quad 3-State Buffers
(Input t r ,
tf~2 ns), AHCT125, AHCT126
KS74AHCT
KS54AHCT
T.=25°C
T.= -40°C to +85°C T.= -55°C to + 125°C
Unit
Ycc=5.0Y
Ycc=5.0Y±10%
Ycc:: 5•OY ± 10 0; '
Typ
Propagation Delay,
A toY
tpLH
CL=50pF
CL =150pF
6
tpHL
CL=50pF
CL=150pF
tPZH
Output Enable Time
Enable to Y
r--------- RL=1 kO
Output Disable Time,
Enable to Y
tPHZ
r--------- RL=1kO
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance· (per stage)
tPZL
tpLZ
Max
Min
Max
9
10
15
12
18
7
10
13
17
15
19
CL=50pF
CL=150pF
11
14
18
23
22
28
CL=50pF
CL =150pF
11
14
18
23
22
28
13
18
13
18
CL=50pF
CIN
Min
--
5
ns
ns
22
- -- - - - - - 22
ns
pF
-r--
COUT
Output disabled
10
pF
Cpo
G or G=Vcc
G or G=GND
5
30
pF
I
* Cpo determines the no-load dynamic power dissipation: PO=CPD VCC ' fint For AC switching test circuits and timing waveforms see section 2_
=8SAMSUNG
Electronics
139
KS54AHCT
KS74AHCT
.13... 2
Quad
Schmi~t- Trigger
NAND Gates
FEATURES
DESCRIPTION
• Functior'l, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA@ VOL =O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These Schmitt-trigger devices contain four independent
NAND gates. They perform the Boolean function Y=AeB=
A+B in positive logic.
PIN CONFIGURATION
The input threshold levels are temperature compensated
and can be triggered from the slowest of input ranges and
still give jitter-free output signals:
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL. NMOS and CMOS devices
without any external components.
All inpu!s and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
1A
Vee
1B
4B
1Y
4A
2A
4Y
2B
3B
2Y
3A
GND
3Y
1A~)
ff
1Y
1B (2)
2A~) 2Y
(5).J:J
.
2B
3A~
(10)..IT
. 3Y
3B
4A~)
. 4Y
4B (13).J:J
FUNCTION TABLE
(Each Gate)
INPUTS
OUTPUTS
A
B
y
L
L
H
H
L
H
L
H
H
H
H
L
c8SAMSUNG
Electronics
140
132
KS54AHCT
KS74AHCT
Quad Schmitt-Trigger NAND Gates
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins . . .
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt . . . .
500 mW
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Ta =25°C
Symbol Test Conditions
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-2o"A
10=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=201AA
10=4mA
10=8mA
(Vee=5V± 10% Unless Otherwise Specified)
KS54AHCT
KS74AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
vee Vee -0.1
4.2
3.98
Vee -0.1
3.84
Vee -0.11
3.7
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
0
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
IAA
Maximum Quiescent
Supply Current
Icc
VIN=Vee or GND
10UT=01AA
2.0
20.0
40.0
IAA
per input pin
VI=2.4V
other inputs:
at Vee or GND
10uT=01AA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
bolee
DC ELECTRICAL CHARACTERISTICS
Characteristic
Positive-Going
Symbol
VT+
Threshold Voltage
Negative-Going
VT-
Threshold Voltage
Hysteresis
(VT+-VT-)
c8SAMSUNG
Electronics
VH
Test Conditions
KS74AHCT
KS54AHCT
Ta=25°C
Unit
Ta= -40°C to +85°C Ta=-55°Cto +125°C
Min Max
Min
Max
Min
Vee=4.5V
1.2 1.9
1.2
1.9
1.2
1.9
Vec=5.5V
1.4 2.1
1.4
2.1
1.4
2.1
Vce=4.5V
0.5 1.2
0.5
1.2
0.5
1.2
Vee=5.5V
0.6
1.4
0.4
1.4
1.4
0.6
Vcc=4.5V
0.6 1.4
0.4 1.4
0.4
1.4
Vcc=5.5V
0.4 1.5
0.4
1.5
0.4
1.5
Max
V
V
V
141
I
KS54AHCT
KS74AHCT
1:.3,..2
Quad Schmitt· Trigger NAND Gates
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr , tf~2 ns), AHCT132
KS54AHCT
KS74AHCT
Ta=25°C
T.a= -40°C to +85°C Ta= -55°C to +125°C
Symbol Conditions t Vcc=5.0V
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Propagation Delay,
Any input to Y
~
CL=50pF
tPHL
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per gate)
Min
Max
Min
Max
8
14
17
8
14
17
ns
5
pF
15
pF
* CPD determines the no-load dynamic power dissipation: PD=CPO VCC 2 fin·
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
142
KS54AHCT
KS74AHCT
133
13-lnputNAND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
High-Drive-Current outputs:
IOl =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
The '133 contains a single 13-input NANO gate.
It performs the boolean functions (in positive logic):
Y = A·S·C·O·E·F·G·H·I·J·K·L·M
y = A+B+C+D+E+F+CHH+T+J+R+I+M
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
LOGIC DIAGRAM
A
Vee
B
M
e
D
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
K
E
A
B
e
D
F
E
G
H
GND
y
I
(1)
(2)
(3)
(4)
(5)
(6)
y
G
H
(7)
(10)
(11)
(12)
K
FUNCTION TABLE
(14)
M
(15)
OUTPUT
y
INPUTS A THRU M
All inputs
One or more inputs
(13)
H
L
c8SAMSUNG
Electronics
L
H
143
KS54AHCT
KS74AHCT
"1:3B
13-lnputNA'ND 'Gates
.Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Ceramic Package (J): -12mW/oC from 100°C to 125°C
Supply Voltage Range Vcc, , ...... -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vcc +0.5V) . , ... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V) , . , . ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) ... , . , ... ±35 mA
Continuous Current Through
Vcc or GND pins .... , , .. , .... ' ., ±125 mA'
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt, ... , . 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc ... , .... , ..... 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT ' . OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
, . , . Max 500 ns
Input Rise & Fall Times, tr , k ..
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at 'or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol lest Conditions
(Vcc=5V± 10% Unless Otherwise Specified)
Ta=25°C
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Alcc
Vcc Vcc -0.1
3.98
4.2
0
VIN=VCC or GND
10UT=0",A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
lOUT = o",A
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr • tf~2 ns). AHCT133
KS74AHCT
KS54AHCT
Ta ~25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Symbol Conditionst Vcc=5.0V
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Propagation Delay,
Any input to Y
Min
Max
tpLH
11
18
tpHL
11
18
r---- CL=50pF
Input Capacitance
CIN
5
Power Dissipation Capacitance·
Cpo
15
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG'
Electronics
Min
Max
22
22
ns
pF
pF
fin,
144
KS54AHCT
KS74AHCT
138
3-Line to 8-Line Decoders/Demultiplexers
FEATURES
DESCRIPTION
• Designed specifically for high-speed memory
decoders and data transmission systems
• Incorporates 3 enable inputs to simplify cascading
and/or data reception
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices are designed to be used in highperformance memory-decoding or data-routing applications
requiring very short propagation delay times. In highperformance memory systems, these decoders can be
used to minimize the effects of system decoding. When
used with high·speed memories utilizing a fast-enable
circuit, the delay times of these decoders and the enable
time of the memory are usually less than the typical access
time of the memory. This means that the effective system
delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the three
enable inputs select one of eight input lines. Two activelow and one active-high enable inputs reduce the need for
external gates or inverters when expanding. A 24-line
decoder can be implemented without external inverters and
a 32-line decoder requires only one inverter. An enable
input can be used as a data input for de multiplexing
applications.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
A
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
Vee
8
YO
C
Y1
G2A
Y2
G28
Y3
G1
Y4
Y7
Y5
GND
YB
LOGIC DIAGRAM
FUNCTION TABLE
Enable
Inputs
Select
I.nputs
Outputs
G1
G2*
C B A
YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
H
X
X X X
X X X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
H
L
L
H H
L
H
L
H
L
H
L
H H H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
c8SA~SUNG
Electronics
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
L
H
H
145
I
S-Line to 8-Lin.e Decoders/Demultiplexers
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode, Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±35 mA
Continuous Current Through
Vee or GND pins
±·125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee .............. 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . .. Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Ta=25°C
Symbol Test Conditions
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
",A
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
VIN=VIH or VIL
lo=-:W",A
10=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10 = 20",A
10=4mA
10=8mA
Maximum Input
Current
hN
VIN=Vee or GND
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
61ee
VIN=Vee or GND
10UT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10UT=0",A
=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
--f------
0
146
KS54AHCT
.KS74AHCT
138
3-Line to 8-Line Decoders/Demultiplexers
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr •
tf~2
ns). AHCT138
KS74AHCT
KS54AHCT
Ta=25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Unit
Symbol Conditions t Vcc=5.0V
Vcc = 5.0V:!: 10%
Vcc=5.0V:!: 10%
Typ
Min
Max
Min
Max
Propagation Delay.
A. B. C or any Y
~
12
20
24
tpHL
12
20
24
Propagation Delay.
G1 to any Y
-
12
18
20
12
18
20
Propagation Delay.
G2A or G2B to any Y
-
tpLH
12
18
20
tpHL
12
18
20
tpLH
tpHL
CL=50pF
ns
ns
ns
Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
50
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
fin.
t For AC switching test circuits and timing waveforms see section 2.
II
c8SAMSUNG
Electronics
147
KS54AHCT
KS74AHCT
139
.
Dual 1-01-4 Decoders/Demultiplexers
DESCRIPTION
FEATURES
• Designed specifically for high-speed memory
decoders and data transmission systems
• Incorporates 2 enable inputs to simplify cascading
and/or data reception
• Function, pin-out, .speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characteri.zed for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices are deSigned to be used in highperformance memory-decoding or data-routing applications
requiring very short propagation delay times. In highperformance memory systems, these decoaers can be
used to minimize the effects of system decoding. When
used with high-speed memories utilizing a fast·enable
circLiit, the delay times of these decoqers and the enable
time of the memory are usually less than the typical access
time of the memory, this means that the effective system
. delay introduced by the decoder is negligible.
The '139 consists of two individual two· line to four-line
decoders in a single package. The active·low enable input
can be used as a data line in demultiplexing applications.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
(Each Decoder/Demultiplexer)
1<3
Vee
1A
2G
1B
2A
1YO
29
1Y1
2YO
1Y2
2Y1
1Y3
2Y2
GND
2Y3
ENABLE
G
YO
Y1
OUTPUTS
Y2
Y3
FUNCTION TABLE
Inputs
Enable
G
H
L
L
L
L
Outputs
Select
A
B
X
X
L
L
H
H
L
H
L
H
YO
Y1
Y2
Y3
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
c8SAMSUNG
Electronics
'
148
KS54AHCT
KS74AHCT
139
Dual 1-of-4 Decoders/Demultiplexers
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 rnA
Continuous Current Through
Vee or GND pins . . . . . .
± 1 25 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf .
.. Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the deviee at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vce=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vce -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN = VIH or VIL
10=20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
lee
8.0
80.0
160.0
",A
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
.6.lee
VIN=Vee or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
c8SAMSUNG
Electronics
Vee Vce -0.1
3.98
4.2
0
149
II
KS54AHCT
KS74AHCT
139..
Dual 1-01-4 Decoders/Demultiplexers
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr , tf~2 ns), AHCT139
KS74AHCT
KS54AHCT
Ta=25°C
Ta= -40°C to +85°C Ta= - 55°C to +125°C
Symbol Conditionst Vcc=5.OV
Unit
Vcc= 5.OV:t 10%
Vcc=5.OV:t 10%
Typ
tPlH
11
tPHL
11
Propagation Delay,
AorBtoY
f------
~opagation
~
Delay,
GtoanyY
Input Capacitance
Power Dissipation Capacitance *
CL=50pF
Min
Max
Min
Max
17
17
20
18
21
18
21
ns
20
tpHL
11
11
C'N
Cpo
5
pF
50
pF
ns
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For
A(~
switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
.
150
KS54AHCT
KS74AHCT
148
8-Line to 3-LinePriority Encoders
FEATURES
DESCRIPTION
•
•
•
•
•
The '1 48 provides three bits of binary coded output
representing the position of the highest order active input,
along with an output indicating the presence of any active
input. It is easily expanded via input and output enables
to provide priority encoding over many bits.
•
•
•
•
•
•
Encodes eight data lines in priority
Provides 3-bit binary priority code
Input enable capability
Easily cascadable
Function, pin-out, speed and drive compatibility with
54174ALS logic family
Low power consumption characteristic of CMOS
High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
These devices p~ovide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components. .
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
II
FUNCTION TABLE
4
Inputs
Vee
5
EO
EI
0 1 2 3 4 5 6 7
6
GS
H
L
X
H
X
X
X
X
X
X
X
3
EI
A2
A1
GND
c8SAMSUNG
Electronics
0
AO
I
Outputs
1----,---
L
L
L
L
L
L
L
L
X X
H H
X X
X X
X X
X X
X X
X L
L H
L H H
X
H
X
X
X
X
X
H
X
X
X
X
H
X
X
L
L H
L H H
H H H
H H H
H H H
X X
H H
X L
L H
H H
H H
H H
H H
H H
H H
A2 A1 AO
GS EO
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
I
151
KS54AHCT
KS74AHCT
148
8-Line to 3-Line Priority Encoders
LOGIC DIAGRAM
(10)
II
o~~~w-r~
(15) EO
(11)
GS
(12)
2--~-4~~~+-+-~
3
(13)
4~(1~)____~~-+~-O__-+~
(2)
5----------~+-+_~.~~i~o_+_--~
(3)
(4)
-------------0 ~-------------------......-4-..,
EI_{_5_)
Absolute Maximum Ratings*
Supply Voltage Range Vee, ..
-0.5V to + 7V
DC Input Diode Current, I,K
(VI < -0.5V or VI> Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins . . . .
± 125 mA
Storage Temperature Range, T5 1g ••. -:65°C to +150°C
Power Dissipation Per Package, Pdt. . . . . . 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
=8SAMSUNG
1:1..."trnril... ",
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . .
. ....... 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
152
148
KS54AHCT
KS74AHCT
8-Line to 3-Line Priority Encoders
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
KS54AHCT
KS74AHCT
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Ta=25°C
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0 .
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
Vee -0.1
3.84
Vee -0.1
.3.7
V
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
liN
VIN=VIH or VIL
lo=-20~A
Vee Vee -0.1
4.2
3.98
lo=-4mA
VIN=VIH or VIL
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
ll.lee
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=Vee or GND
±0.1
±1.0
±1.0
~A
8.0
80.0
160.0
~A
2.7
2.9
3.0
mA
lo=20~A
0
VIN=Vee or GND
louT=O~A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
louT=O~A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r , tf~2 ns), AHCT148
KS54AHCT
KS74AHCT
To =25°C
To = -40°C to +85°C To = -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Propagation Delay,
1-7 to AO, A1 or A2
Propagation Delay,
0~7 to EO
Propagation Delay,
0-7 to GS
Min
Max
Max
Min
tpLH
10
17
20
tpHL
10
17
20
tpLH
11
18
22
tPHL
11
18
22
24
29
24
29
14
_.. - ---------
tpLH
tpHL
CL=50pF
14
Propagation Delay,
EI to AO, A1 or A2
tpLH
10
16
19
tpHL
10
16
19
Propagation Delay,
EI to GS
tpLH
10
17
20
tPHL
10
17
tpLH
11
18
22
tpHL
11
18
22
Propagation Delay,
EI to EO
.... -
20
f------~--.-
ns
ns
ns
ns
ns
ns
Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
50
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SA~SUNG
ElectroniCS
153
II
KS54AHCT
KS74AHCT
151
.
1-0'-8 Data Selectors/Multiplexers
FEATURES
DESCRIPTION
• Can perform as:
Boolean Function Generators
Parallel-ta-Serial Converters
Data Source Selectors
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High drive currents outputs
. (IOL 24 rnA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT:- -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These monolithic data selectors/multiplexers provide full
binary decoding to select one of eight data sources. The
strobe input (<3) must be at a low logiC level to enable the
inputs. A high level at the strobe terminal forces the W
output high and the Y output low.
=
=
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vec and
ground.
FUNCTION TABLE
PIN CONFIGURATION
OUTPUTS
INPUTS
STROBE
SELECT
03
Vee
02
04
01
05
DO
06
Y
07
W
A
G
GNO
B
e
C
B
A
G
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
y
W
L
DO
D1
02
D3
D4
D5
D6
D7
H
DO
D1
D2
D3
D4
D5
D6
D7
H = high level, L = low level. X = irrelevant
DO. D1 ... D7 = the level of the D respective input
Absolute Maximum Ratings*
Supply Voltage Range Vee. . . .
-0.5V to + 7V
DC Input Diode Current. hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
COt:Jtinuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±70 mA
Continuous Current Through
Vee or GND pins ................ ±250 mA
Storage Temp~rature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
• Absolute Maximum Ratings are those values beyond
which permanent. damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long ex·
posure to these conditions may affect device reliability.
=8~SUNG
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN. Vour .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
154
KS54AHCT
KS74AHCT
151
1-of-8 Data Selectors/Multiplexers
LOGIC DIAGRAM
(7\
14)
DO
"'
r----
;::::::L..I
~
f=L.-./
13)
01
\.
12)
02
>---
V-
(1)
03
>---
DATA
INPUTS
115)
04
,---,
~
I--
~
(14)
05
(13)
06
I--
--_A.
~
Fl--'"'
(5)
(6)
y
w
I
II
112)
(11)
A
"
..
~t:::::L...I
110)
B--
C
19)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
KS74AHCT
KS54AHCT
Ta = -40°C to +8SoC Ta=-55°Cto +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage-
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN = VIH or VIL
lo=-20",A
lo=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20",A
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Ice
VJN=Vec or GND
lOUT = o",A
per input pin
VJ=2.4V
other Inputs:
at Vcc or GND
IOUT=O",A
=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
155
KS54AHCT
KS74AHCT
151
1-01-8 Data Selectors/Multiplexers
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr • tf~2 ns). AHCT151
KS74AHCT
T.=25°C
T. = -40°C to +85°C
Vcc=5.0V
Vcc=5.0V:t10%
KS54AHCT
T.= -55°C to +125°C
Vcc=5.0V:t 10%
Symbol
Condltlonat
tPLH
CL=50pF
CL=150pF
13
16
21
26
25
31
tpHL
CL=50pF
CL=150pF
13
16
21
26
25
31
tPLH
CL=50pF
CL=150pF
15
18
24
29
27
33
tpHL
CL=50pF
CL=150pF
15
18
24
29
27
33
tpLH
CL=50pF
CL=150pF
9
12
15
20
18
24
tpHL
CL=50pF
CL=150pF
9
12
15
20
18
24
tPLH
CL=50pF
CL=150pF
8
11
15
20
18
24
tpHL
CL=50pF
CL =150pF
8
11
15
20
18
24
tpLH
CL=50pF
CL=150pF
12
15
19
24
23
29
tPHL
CL=50pF
CL =150pF
12
15
19
24
23
29
tpLH
CL=50pF
CL=150pF
13
16
21
26
25
31
tpHL
CL=50pF
CL =150pF
13
16
21
26
25
31
Typ
Propag~tion
Delay.
A. Bor C tQ Y
Propagation Delay.
A. B or C to W
Propagation Delay.
AnyDtoY
Propagation Delay
Any D to W
Propagation Delay.
G to Y
Propagation Delay.
G to W
Input Capacitance
Power Dissipation Capacitance *
C'N
Cpo
Min
5
Max
Min
Unit
Max
ns
ns
ns
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc1fin.
t For AC switching test circuits and timing waveforms see section 2. "
c8SAMSUNG
Electronics
156
KS54AHCT
KS74AHCT
153
Dual 1-of-4 Data Selectors/Multiplexers
FEATURES·
DESCRIPTION
• Allows Multiplexing from N Lines to 1 Line
• Performs Parallel-to-Serial Conversion
• Strobe (Enable) Line Provided for Cascading
(N lines to n lines)
• '253 is the 3-State Version of this part
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
.
• Low power consumption characteristic of CMOS
• High drive currents Outputs
(IOL 24 rnA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
Each of these data selectors/multiplexers contains inverters
and drives to supply full binary decoding data selection to
the AND-OR gates. Separate strobe inputs (G) are provided for each of the. two four-line sections.
PIN CONFIGURATION
FUNCTION TABLE
=
=
1<3
Vee
B
2<3
lC3
A
lC2
2C3
lCl
2C2
lCO
2Cl
1Y
2CO
GND
2Y
These devices provide speeds and drive c~pability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
SELECT
INPUTS
DATA INPUTS
CO C1
B
A
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
C2 C3
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
I
STROBE
OUTPUT
G
y
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
Select inputs A and B are common to both sections.
c8SAMSUNG
Electronics
157
153
.
KS54AHCT
KS74AHCT·
Dual 1-0'-4 Data Selectors/Multiplexers
\
LOGIC DIAGRAM
~'"I
lCO
(8)
lCl _(_5)_ _
lC2
l
lC3
2CO
IV
(4)
(3)
(10)
DATA 2
2C2 (12)
2C3
(13)
20
(15)
2Y
Absolute Maximum Ratings*
Supply Voltage Range Vee, ... . . . . -O.5V to + 7V
DC Input Diode Current, 11K
(V) < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) ......... ±70 inA
Continuous Current Through
Vcc or GND pins ................ ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . . .. 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vcc .
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
158
153
KS54AHCT
KS74AHCT
Dual 1-01-4 Data Selectors/Multiplexers
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 1 0% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
T.= -40°C to +85°C T.= -55°C to +125°C Unit
T. =25°C
Test Conditions
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20,.,A
lo=-6mA
Vec -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20,.,A
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
,.,A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
,.,A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
81cc
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
louT=O,.,A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
IOUT=O,.,A
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r , tf~2 ns), AHCT153
KS54AHCT
KS74AHCT
T.=25°C
T.= -40°C to +85°C T.=-55°Cto +125°C
Unit
Vee=5.0V
Vcc=5.0V::t 10%
Vee = 5.0V::t 10%
Symbol
Condltlons t
tpLH
CL=50pF
CL=150pF
13
16
21
26
25
31
tpHL
CL=50pF
CL =150pF
13
16
21
26
25
31
tPLH
CL=50pF
CL =150pF
9
12
15
20
18
24
tpHL
CL=50pF
CL =150pF
9
12
15
20
18
24
tpLH
CL=50pF
CL=150pF
11
14
18
23
22
28
tpHL
CL=50pF
CL =150pF
11
14
18
23
22
28
Typ
Propagation Delay,
AorBtoY
Propagation Delay,
Data (Any C) to Y
Propagation Delay,
G to Y
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
Min
5
Max
Min
Max
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC z fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
159
II
KS54AHCT
KS74AHCT
154
4-Line to 16-Line. Dflcoders/Demultiplexers
FEATURES.
DESCRIPTION
• Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive OUtputs
• Performs the Demultlplexing Function by Distributing
Data From One Input to Any One of 16 Outputs
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• ·Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
T~ese
PIN CONFIGURATION
LOGIC DIAGRAM
monolithic, 4-line to 16-line decoders decode four
binary-coded inputs into one of sixteen mutually exclusive
outputs when both the strobe inputs. G1 and G2, are low.
The demultiplexing function is performed by using the 4
input lines to address the output line, passing data from
one ofthe strobe inputs with the other strobe input low.
When either strobe input is high, all outputs are high. These
demultiplexers areidenally suited for implementing hiQhperformance memory decoders.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diod~ clamps to Vee and
ground.
A
.vcc
A
(18)
6
<31
... ---
0
A
B
<32
.- .........
ii C _
Gl
G2 (19)
~-B,--I--
11
(3)
(4)
t---I--
14
13
(2)
G
15
12
(1)
~--
(5)
~--
(6)
c-)--
~
(22
.----
>----
.---
8
(21
>-r------
c
(8)
>-y
C
'0(20
(7)
0----
B
... -
0
;:::::
f-~)
l--_
0
5
~
----
...
...
.... ...
t::::::
...
f-)--
(11
~~
~- f--f--
C
~
ii
(14
(15
;:::: ~
A
~)- f - -
A
~:::
~
--~
B"cI:::I=::: ....-
c8SAMSUNG
Electronics
(13
~~
(17
160
KS54AHCT
KS74AHCT
15'6fA
4-Line to 16-Line Decoders/Demultiplexers
FUNCTION TABLE
Inputs
Outputs
G1
G2
0
C
B
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Va < -0.5V or Va> Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Va < Vee +0.5V) . . .
±35 rnA
Continuous Current Through
Vee or GND pins . .
± 125 rnA
Storage Temperature Range, T8 1g •.. -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
.
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
161
I
15'A
..,
KS54AHCT
KS74AHCT
4-Line to 16-Line DecoderSIDem;,Jltiplexers
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V±10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Ta
KS74AHCT
+85°C Til
= -40°C to
KS54AHCT
+125°C Unit
=-55°C to
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
~aximum Low-Level
Input Voltage
VIL
O.B
O.B
O.B
V
Minimum High-Level
Output Voltage
VOH
Vcc -0.1
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2OIolA
lo=4mA
lo=BmA
Maximum Input
Current
liN
VIN=VCC or GND
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
.6.lcc
VIN=VIH or VIL
lo=- 2OIolA
lo=-BmA
Vcc Vcc -0.1
4.2
3.9B
0
VIN=VCC or GND
louT=OIolA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
louT=OIolA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
lolA
B.O
BO.O
160.0
lolA
2.7
2.9
3.0
mA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
3.B4
(Input tr , tt~2 ns), AHCT154
T a =25°C
Vcc=5.0V
Typ
KS74AHCT
Ta= -40°C to +85°C
Vcc=5.0V±10%
Min
Max
KS54AHCT
Ta= -55°C to +125°C
Unit
Vcc=5.0V± 10%
Min
Max
Propagation Delay,
A, B, C, D to. Any Output
tpLH
12
20
24
tpHL
12
20
24
Propagation Delay,
<31 or <32 to .Any Output
tpLH
12
20
24
tpHL
12
20
24
CL=50pF
ns
ns
Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
50
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
162
KS54AHCT
KS74AHCT
155
Dual 2-to-4 Line Decoders/Demultiplexers
FEATURES
DESCRIPTION
• Typical applications:
Dual 2-t0-4 line decoder
Dual 1-t0-4 line demultiplexer
3-t0-8.line decoder
1010-8 line demultiplexer
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '155 consists of two 1-to-4 line demultiplexers with
independent strobes and common binary address inputs.
When both sections are enabled by the strobes, the common address inputs sequentially select and route
associated input data to the appropriate output of each secton. The individual strobes permit activating or inhibiting
each of the 4-bit sections as desired. Data applied to input C1 is inverted at its outputs and data applied to C2
is true through its outputs. The inverter following the C1
data input permits use as a 3-to-8 line decoder, or 1-to-8
line demultiplexer, without gating.
PIN CONFIGURATION
c8SAMSUNG
Electronics
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
I
LOGIC DIAGRAM
163
KS54AHCT
KS74AHCT
'155'
Dual 2-to-4 Line Decoders/Demultiplexers
FUNCTION TABLES
2-t0-4 Line Decoder or 1-t0-4 Line Demultiplexer
Inputs
Select
Strobe
Data
Select
Outputs
a
A
G1
C1
1YO
1Y1
1Y2
1Y3
X
L
L
H
H
X
X
L
H
L
H
X
H
L
L
L
L
X
X
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
Inputs
Select
Strobe
Data
Outputs
Strobe
or Data
BA
G*
X XX
H
L
L
L
L
L
L
L
L
ct
L
L
L
L
H
H
H
H
L L
L H
H L
HH
L L
L H
H L
HH
(0)
(1 )
(2)
(3)
(4)
(5)
(6)
(7)
2YO 2Y1 2Y2 2Y3 1YO 1Y1 1Y2 1Y3
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
t = Inputs C1 and C2 Connected together
t = Inputs G1 and G2 Connected together
a
A
G2
C2
2YO
2Y1
2Y2
2Y3
X
L
L
H
H
X
X
L
H
L
H
X
H
L
L
L
L
X
L
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
X
Ho-8 Line Decoder or 1010-8 Line Demultiplexer
Absolute Maximum Ratings*
Supply Voltage Range Vee. . . . . . . . -0.5V to + 7V
DC Input Diode Current, hK
(V, < -0.5V or V, > Vee +0.5V) . .
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vec .............. 4.5V to 5.5V
DC Input & Output Voltages·, V'N, VOUT .. OV to Vce
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
164
KS54AHCT
KS74AHCT
155
DuaI2-to-4 Line Decoders/Demultiplexers
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V±10% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
Ta= -40"C to +85°C Ta= -55°C
to +125°C Unit
- - ...
Ta =25°C
Symbol Test Conditions
-----.~.
Typ
-~--
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vcc -0.1
3.84
Vcc -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
/-lA
8.0
80.0
160.0
/-lA
2.7
2.9
3.0
mA
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
10=8mA
Maximum Input
Current
liN
VIN=VCC or GND
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
.6.lcc
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
10uT=0/-lA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10uT=0",A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr , tf~2 ns), AHCT155
T. =25°C
Vcc=5.0V
Typ
Maximum Propagation Delay,
A, S, C2, G1 or G2 to any
Output (2 levels of logic)
KS74AHCT
Ta =-40°Cto +85°C
Vee = 5.0V %10%
Min
Max
KS54AHCT
T.= -55°C to +125°C
Unit
Vcc=5.0V% 10%
Min
Max
tpLH
12
20
24
tpHL
12
20
24
14
23
28
Maximum Propagation Delay,
A or B to any Y
(3 levels of logic)
tpLH
tpHL
14
23
28
Maximum Propagation Delay,
C1 to any Y
tpLH
13
22
26
tpHL
13
22
26
Maximum Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
CL=50pF
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
165
II
KS54AHCT
KS74AHCT
,1571158
Quad 2-Line t01 ~Line Data
Selectors/Multiplexers
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for ,operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These are data selectors multiplexers which select a 4-bit
word from one of two sources via the control of a common select input (AlB). A separate strobe input (G) is provided. The '157 presents true data whereas the '158
presents inverted data at the outputs.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
PIN CONFIGURATION
AlB
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any ,external components.
Vee
Output Y
Inputs
f-.
1A
G
Strobe
Select
1B
4A
1Y
4B
G
AlB
A
B
H
L
L
L
L
X
L
L
H
H
X
L
H
X
X
X
X
X
2A
4Y
2B
3A
2Y
3B
GND
3Y
Data
L
H
'157
'1·58
L
L
H
L
H
H
H
L
H
L
LOGIC DIAGRAMS
'157
'158
(2)
1A~(2~)____________~~
1B (3)
1A
1Y
(3)
1B
2A (5)
2A (5)
2B (6)
2B (6)
3A (11)
3A (11)
3B (10)
4A (14)
4B (13)
STROBE G .:,,(1n"5;....)-_-a-~
SELECT AlB ..!..(1;,.:.)_ - + - ( l - J
c8SAMSUNG
Electronics
(10)
3B
(14)
4A
4B (13)
_ (15)
STROBE G
(1)
SELECT AlB
166
KS54AHCT 15~/158
KS74AHCT
I
Quad 2-Line to 1-Line Data
Selectors/Multiplexers
Absolute Maximum Ratings*
Supply Voltage Range Vee, . .
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Va > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
± 125 mA
Storage Temperature Range, T51g ••. -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C ~ +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conC:itions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20~A
10=-4mA
Vee Vee -0.1
4.2
3.98
Vee -0.1 .
3.84
Vee -0.1
3.7
V
-~
f-~-
VIN=VIH or VIL
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
hN
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
.6. Icc
10=20~A
lo=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=Vee or GND
±0.1
±1.0
±1.0
~A
8.0
80.0
160.0
Ji.A
2.7
2.9
3.0
mA
VIN=Vee or GND
10UT=0Ji.A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0Ji.A
c8SAMSUNG
Electronics
0
167
II
KS54AHCT
KS74AHCT
157,/158
I
AC ELECTRICAL CHARACTERISTICS
Characteristic
Quad '2-Line to 1-Line Data
Selectors/Multiplexers
J
Symbol
Condltlons t
(Input tr , tf~2 ns), AHCT157, AHCT158
Ta=25°C
Vee=5.0V
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta = - 55°C to +125°C
Unit
Vee = 5.0V: 10%
Vee=S.OV: 10%
Typ
Propagation Delay,
Aor B to Y
Min
Max
Min
Max
tpLH
11
15
18
tpHL
11
15,5
18
13
22
26
13
22
26
Propagation Delay,
AlB to Y
tpLH
Propagation Delay,
Y
tpLH
12
19
23
tPHL
12
19
23
Input Capacitance
CIN
5
Power Dissipation Capacitance"
Cpo
G to
tpHL
CL=50pF
.. Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
ns
ns
ns
pF
pF
fin,
168
KS54AHCT
KS74AHCT
1601161
1621163
Synchronous 4-Bit Decade
and Binary Counters
FEATURES
DESCRIPTION
•
•
•
•
•
These are synchronous, presettable 4·bit binary counters
featuring internal carry-look-ahead for high-speed counting.
The '1 60 and '1 62 are decade counters, and the '161
and '163 are 4-bit binary counters. The buffered clock input triggers all flip-flops simultaneously on the riSing edge
of the input waveform. This eliminates the output counting
spikes normally associated with asynchronous counters.
•
•
•
•
•
•
Internal look Ahead for Fast Counting
Carry Output for n-bit cascading
Synchronous Counting
Synchronously Programmable
Function, pin-out, speed and drive compatibility with
54174AlS logic family
low power consumption characteristic of CMOS
High-Drive-Current outputs:
10l =8 rnA @ VOL =0.5V
Inputs and outputs interface directly with TTL, NMOS·
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
ClR
Vee
ClK
RCO
A
QA
B
Os
C
Oe
D
QD
ENP
ENT
GND
lOAD
FUNCTION TABLES
'160, '161
Function
ClK ClR ENP ENT lOAD
X
X
X
X
t
t
L
H
H
H
H
H
X
X
X
H
L
L
L
H
L
H
H
H
L
H
X
X
H
H
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment Counter
'162, '163
ClK ClR ENP ENT lOAD
t
X
X
X
t
t
L
H
H
H
H
H
X
X
X
H
L
L
L
H
L
X
X
H
H
H
L
H
H
H
Function
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment counter
=8SAMSUNG
Electronics
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables
the counter and causes the outputs to agree with the setup
data after the next clock pulse regardless of the levels of
the enable inputs.
The clear function for the' 160 and' 1 61 is asynchronous
and a low level at the clear input sets all four of the flipflop outputs low regardless of the levels of the clock, load
or enable inputs.
The clear function for the '162 and 163 is synchronous
and a low level at the clear input sets all four of the· flipflop outputs low after the next clock pulse, regardless of
the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily as decoding
the maximum count desired can be accomplished with one
external NAND gate. The gate output is connected to the
clear input to synchronously clear the counter. r
Two enable inputs and a ripple carry output allow easy
cascading of the counters. Both count-enable inputs (ENP
and ENT) must be high to count, and ENT is fed forward
to enable the ripple carry output. The ripple carry output
(RCO) thus enabled will produce a high-level pulse while
the count is maximum (9 or 15 with QA high). This highlevel overflow ripple carry pulse can be used to enable successive cascaded stages. Transitions at the ENP or ENT
are allowed regardless of the level of the clock input.
These counters feature a fully independent clock circuit.
Changes at control inputs (ENP, ENT, or LOAD) that will
modify the operating model have no effect on the contents
of the counter until clocking occurs. The function of the
counter (whether enabled, disabled, loading, or counting)
will be dictated solely by the conditions meeting the stable
setup and hold times.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
169
II
KS54AHCT
KS74AHCT
1601161
1621163
Synchronous 4-Blt Decade
and Binary Counters
LOGIC DIAGRAMS
'160 or '162
OB
CK
CK
ern
ern
RCO
(3)
(4)
C
'161 or'163
CK
CK
CK
ern
CK
CLR
ern
ern
ENT
ern
v - - -.. .,.,----,
__
Reo
13}
14}
C
CLK
c8SAMSUNG
Electronics
.
170
1601161
1621163
KS54AHCT
KS74AHCT
Synchronous 4-Bit Decadeand Binary Counters
Typical Clear, Preset, Count. and Inhibit Sequences
'160 and '162
'161 and '163
l:iJI
COl
160
161
COl
COl
162
LOAD
---- ---------- ---....
.DATA
rnm
r---___________
-________ __
1---+--.--r---+-~L= ======= ===
--+--.... - - - - - - - - - - - - - ---+--.... - - - - - - - - - - - - - :, _ _
-+_...&------ ___ - ___ _
{:
INPUTS
163
=
=
=
ClK
160
CLK
162
--I-r.~------!::==~
0.==
0.--
OUTPUTS
==
Oc _ _
RCO
---;---t--+~
CLEAR
ENT _ _
OUTPUTS
100==
(:==
Oc:==
-
-
00==
2
3
- -......- - I N H I B I T - -
PRESET
Sequence:
(1) Clear output,s to zero
(2) Preset to BCD seven
(3) Count to eight, nine, zero, one, two, and three
(4) Ihhibit
-+--+'ri-----,...__--.J
-+--+,
ENP _ _
ENP
ENT - - - I - - t '
4--4-~-_-+f_-'---,,--4.-----~
.
RCO---+--+-~~~
1
2
~_.....--INHIBIT-_
CLEAR PRESET
Sequence:
(1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one and two
(4) Inhibit
Absolute Maximum Ratings*
Supply Voltage Range Vcc, ... ,.
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vce +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vec +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
±125 mA
Vce or GND pins, ,
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ... , . , 500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional. operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fa" Times, tr , tf ......... Max 500 ns
Unused inputs must a1ways.be tied to an appropriate logiC
voltage level (either Vee or GND)
171
II
KS54AHCT
KS74AHCT
1601161
1621163
Synchronous 4-Bit Decade
and Binary Counters
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 10% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Ta=25°C
Test Conditions
Typ
Guaranteed Limits
Minimum High-level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum low-level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20",A
lo=-4mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum low-level
Output Voltage
VOL
VIN=VIH or VIL
lo=20",A
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
b.lcc
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
louT=O",A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
louT=O",A
AC ELECTRICAL CHARACTERISTICS
. Characteristic
Symbol
(Input t r , tf~2 ns), AHCT160, AHCT161
KS74AHCT
T. =25°C
T. = -40°C to +S5°C
Conditions t Vcc=5.0V
Vcc=5.0V±10%
Min
Unit
Max
Typ
Min
Maximum Clock Frequency
f max
50
40
Propagation Delay,
ClK to RCO
tpLH
20
24
I--
15
tPHL
15
20
24
Propagation Delay,
ClK to any Q
I--
tpLH
10
16
19
tpHL
10
16
19
Propagation Delay,
ENT to RCO
tpLH
9
r----
13
16
tpHL
9
13
16
Propagation Delay,
ClR to any Q
tpHL
15
24
29
ns
Propagation Delay,
ClR to RCO
tpHL
17
33
ns
Pulse Width
Setup Time
before ClKt
CL=50pF
Max
KS54AHCT
T.= -55°C to +125°C
Vcc=5.0V± 10%
35
23
8
12
16
ClR low
10
15
20
A, B,C, D
10
15
20
lOAD
10
15
20
10
15
20
6
10
10
0
0
0
ClK High or low
tw
tsu
ENP, ENT
ClR inactive
Hold time,
All Synchronous Inputs after ClKt
th
MHz
ns
ns
ns
ns
ns
ns
Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
80
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
172
KS54AHCT
KS74AHCT
1601161
162/163
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Synchronous 4-Bit Decade
and Binary Counters
(Input tr , tf~2 ns), AHCT162, AHCT163
Ta =25°C
Conditions t Vcc=5.0V
KS74AHCT
Ta= -40°C to +85°C
Vcc=5.0V±10%
Max
KS54AHCT
Ta = -55°C to +125°C
Vcc=5.0V± 10%
Typ
Min
f max
50
40
Propagation Delay,
ClK to RCO
tPLH
r---tpHL
15
20
15
20
Propagation Delay,
ClK to any Q
CL =50pF
tpLH
r---tpHL
10
16
20
10
16
20
Propagation Delay,
ENT to RCO
~
9
15
18
tpHL
9
15
18
tw
8
12.5
20
A, B,C, D
10
15
20
lOAD
10
15
20
15
15
20
ClR inactive
6
10
10
ClR low
6
15
20
th
0
0
0
Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
CPD
80
pF
Maximum Clock Frequency
Pulse Width,
ClK High or low
Setup Time
before ClKt
tsu
ENP, ENT
Hold time,
All Synchronous Inputs after CLKt
Min
Unit
Max
35
MHz
24
.
ns
24
ns
ns
ns
ns
ns
* CPD determines the no-load dynamic power dissipation: PD=CPD VCC2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
173
I
161A
KS54AHCT
KS74AHOT •
. ..,.
8-Bit Seria/-/nIParal/e/-Out Shift Registers
FEATURES
DESCRIPTION
•
•
•
•
These are high·speed 8·bit registers with AND-gated serial
inputs and an asynchronous clear. Data is entered serially
through either one of the two inputs, A and B. A high on
one input enables the other one, which will then determine
the state of the first flip-flop. A low at either or both inputs
inhibits data entry and resets the first flip-flop to a low level
at the next positive clock transition.
•
•
•
•
•
•
AND-Gated (enable/disable) serial inputs
Fully buffered clock and serial inputs
Direct clear
Function, pin-out, speed and drive compatibility with
54/74ALS logic family
Low power consumption characteristic of CMOS
High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
Ihputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to + 125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
Data at the serial inputs may be changed while the clock
is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-.
level transition of their clock input.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
A
Vee
B
aH
aG
a.
aE
aA
aB
ae
aD
GND
ClR
ClK
FUNCTION TABLE
Outputs
Inputs
Qe ••• QH
CLR
CLK
A
B
QA
L
X
L
L
L
QAO
QBO
QHO
H
QAn
QGn
L
X
X
H
X
L
H
H
H
H
X
X
H
QAn
QGn
X
L
L
L
QAn
QGn
t
t
t
H = high level (steady state), L = low level (steady state)
X = irrefevant (any input, including transitions)
t = transition from low to high level.
QAO. QBO. QHo=the level of QA •. QB or QH. respectively. before the indicate steadystate input conditions were established.
QAn. QGn = the level of QA or QG before the most-recent t transition of the clock;
indicates a one-bit shift.
c8SAMSUNG
Electronics
174
KS54AHCT
KS74AHCT
164
8-Bit Seriai-inIParallei-Out Shift Registers.~
LOGIC DIAGRAMS
-a
C~_(9~)__
~
____~____~______~____~______~____~______+-____~
-+__~__~~__~__~__~~__-+__~__~-+__~~
C~_(8_)__~ ~~__
(3)
(4)
(5)
I
(11)
(12)
(13)
Oe
OD
Oc
Os
(10)
(6)
PARALLEL OUTPUTS
I
Typical Clear, Shift, and Clear Sequences
C~~~--------------------------------I
SERIAL
INPUTS
Ir
"
B
L-fl
I
A
I
I
_-+-___---'
~
I
----------~I----------I
I
I
CLK--.t---
I
I
=:. _______
I
I
OA
"~,
LJrl______~I------__
...J
--,
Oe _ _ .&.'--______--J
--.,
Oc _ _
I
.J
..&.I_ _ _ _ _ _ _ _ _ _
~----~I--------~
LJrl~_+:--------
--,
--,, _ _ _ _ _ _ _ _ _ _ _ _ _....J
Oe _ _ ...
OD _ _ -LI_ _ _ _ _ _ _ _ _ _ _--...J
OUTPUTS
LJI~i---
--.,
QF _ _ I
~----------------------~
_ _ .,
~--..&.,
U11----I I
I
__________________J~~-----------
_ _ .,
n _______
I
OH _ _ ...
' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.I
CLEAR
c8SAMSUNG
Electronics
I
CLEAR
175
KS54AHCT
KS74AHCT
164
8-Bit Serial-lnIParaliel-Out Shift· Registers
Absolute Maximum Ratings·
Supply Voltage Range Vee, . . . . . . . -0.5V to + 7V
DC Input Diode Current, I,K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . . . .
±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N); -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vec . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vee
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V+
- 10% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
Ta
:1
KS74AHCT
+85°C Ta
= -40°C to
KS54AHCT
+125°C Unit
= -55°C to
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10- 4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage.
VOL
VIN=VIH or VIL
10=20",A
lo=4mA
10-8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
I,N
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
ll.lee
VIN=Vee or GND.
10UT-0",A
per input pin
VI=2.4V
other Inputs;
at Vee or GND
louT-O",A
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
176
KS54AHCT
KS74AHCT
164
8-Bit Serial-lnIParallel-Out Shift Registers
AC ELECTRICAL CHARACTERISTICS
(Input t r •
tf~2
Ta =2S0C
Characteristic
Symbol
Maximum Clock Frequency
f max
Propagation Delay.
ClR to any Q
tpHL
Propagation Delay.
ClK to any Q
I---
PulsE! Width
Conditions t
Vcc=S.OV
ns). AHCT164
KSS4AHCT '
KS74AHCT
Ta = -40°C to +BSoC Ta= -SsoC to +12SoC
Unit
Vee = S.OV ± 10%
Vee=S.OV± 10%
Typ
Min
60
36
Max
Min
Max
30
MHz
12
20
tpLH
11
18
21
tpHL
11
18
21
24
ns
CL=50pF
ClR low
tw
ClK High or low
Data
Setup
Time before ClKt ClR Inactive
tsu
Hold Time
Data after ClKt
th
8
12
15
8
12
15
8
12
15
8
12
15
a
4
5
ns
ns
ns
ns
--f--
Input Capacitance
CIN
Power Dissipation· Capacitance *
Cpo
(per package)
5
pF
120
pF
* Cpo determines the no·load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
177
KS54AHCT
KS74AHCT
165
8-Bit Paral/e/-/nISeria/-Out Shift Registers
FEATURES
•
•
•
•
•
•
•
•
•
•
. DESCRIPTION
Complementary outputs
Direct overriding load (data) inputs
Gated clock inputs
ParalleHo-Serial data conversion
Function, pin-out, speed and drive compatibility with
54/74AlS logic family
low power consumption characteristic of CMOS
High-Drive-Current outputs:
10l =8 rnA @ VOL =O.5V
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
SH/05
ClK
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
Inputs
Vee
ClK INH
0
F
C
G
B
H
A
QH
Clocking is accomplished through a 2-input NOR gate which
permits one of the clocks to be used as a clock inhibit function. Holding either clock input high inhibits clocking. Either
clock input is enabled by holding the other clock input low
.
while the SH/LD input is high.
FUNCTION TABLE
E
GND
These are high-speed 8-bit parallel-load or serial-in shift
registers with complementary serial outputs available from
the last stage. Parallel-in access is asynchronous and is
enabled by pulling the SH/LD input low. When SH/LD is
high, data is entered serially at the SER input and shifted
one place to the right with each positive clock transition.
SEA
QH
ClK
INH
Function
X
H
X
L
X
X
H
t
L
PARALLEL LOAD
NO CHANGE
NO CHANGE
SHIFT *
SHIFT*
SH/LD
ClK
l
H
H
H
H
t
·Content of each internal register shifts toward output QH. Data
at serial input is shifted into first register.
c8SAMSUNG
Electronics
178
KS54AHCT
KS74AHCT
165
8-Bit Parallel-lnISerial-Out Shift Registers
LOGIC DIAGRAMS
PARALLEL INPUTS
II
Typical Shift, Load and Inhibit Sequences
CLK
CLK INH
SER.,L__________
SH/[5
~-------------------------------
---r..J
I
A~~--~-----------------B
1
I
__--__
L
c~~--~--------------------------_
PARALLEL
DATA
INPUTS
1
IL
D L __~I--------~-------------------------------
I
E~~
__~--------------------------_
I
1 IIL
F •
G~~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
H~
I
~---~-------------------------
I·
r
I
...·t-------
INHIBIT -tI·~I
SERIAL-SHIFT
LOAD
c8SAMSUNG
ElectroniCs
179
KS54AHCT
KS74AHCT
165
8-Bit. Paralle!-!nISeria!-Out Shift Registers
Absolute Maximum Ratings·
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) ......... ±35 mA
Continuous Current Through
Vcc or GND pins
. . . . . . . . .. ± 1 25 mA
Storage Temperature Range, T5 1g •.. -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating: .
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vec .............. 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
.
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
. Characteristic
Symbol Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
Ta =25°C
Typ
Ta
KS74AHCT
+85°C Ta
=-40°C to
KS54AHCT
+125°C Unit
=-55°C to
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20JAA
lo=-4mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20JAA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
JAA
Maximum Quiescent
Supply Current
Icc
8·.0
80.0
160.0
JAA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Icc
VIN=VCC or GND
louT=OJAA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND,
louT=OJAA
c8SAMSUNG
ElectrElnics
Vcc Vcc -0.1
4.2
3.98
0
180
KS54AHCT
KS74AHCT
165
8-Bit Paral/e/-/nISeria/-Out Shift Registers
AC ELECTRICAL CHARACTERISTICS
Characteristic
Maximum Clock Frequency
Propagation Delay.
SH/[i) to QH or QH
Symbol Conditions t
Typ
Min
50
30
~
15
25
30
15
25
30
19
31
37
19
31
37
tpHL
tpLH
~
Propagation Delay,
H to QH or QH
r----
Setup Time
Hold Time
SH/lD low
KS54AHCT
KS74AHCT
Ta =25°C
T. = -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V± 10%
Vcc=5.0V±10%
f max
Propagation Delay.
ClK to QH or QH
Pulse Width
(Input t r • tf~2 ns), AHCT165
tpHL
CL=50pF
Max
Min
tPLH
12
20
24
12
20
24
8
12
15
8
12
15
SH/lD High
before ClKt
7
15
20
SER before ClKt
8
12
15
7
15
20
ClK INH High
before ClK-l-
7
15
20
Data before SH/lDt
5
8
10
0
0
0
0
0
0
SER Data after ClKt
MHz
tpHL
ClK High or low
ClK INH low
before ClKt
Max
25
tw
tsu
th
PAR Data after SH/lDt
ns
ns
ns
ns
ns
ns
Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
100
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
181
II
\ KS54AHCT
KS74AHCT
166
8-Bit Paral/el-lnISerial-Out
Shift Registers with Clear
FEATURES
DESCRIPTION
•
•
•
•
These devices feature parallel-in or serial-in, serial-out
registers, gated clock inputs and an overriding clear input.
The paralled-in or serial-in modes are established by the
shift/load input. When high, the input enables the serial data
input and couples the eight fill-flops for serial shifting with
each clock pulse. When low, the paralled data inputs are
enabled and synchronous loading occurs on the next clock
pulse. During parallel loading, serial data flow is inhibited.
Clocking is accomplished on the low-to-high edge of the
clock pulse through a two-input positive NOR gate permitting one input to be used as a clock-enable or clock-inhibit
function. Holding either of the clock inputs high inhibits
clocking; holding either low enables the other clock input.
This allows the system clock to be free-running and the
register can be stopped on command with the clock input. The clock-inhibit input should be changed to the high
level only when the clock input is high. A buffered direct
clear input overrides all other inputs, including the clock,
and sets all flip-flops to zero.
•
•
•
•
•
•
Synchronous load
Direct .overriding clear
Parallel to serial conversion
Function, pin-out, speed and drive compatibility with
54/74ALS logic family
Low power consumption characteristic of CMOS
High-Drive-Current outputs:
IOl =8 mA @ VOL =O.5V
Inputs and outputs interface directly with TTl, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Package options include "small outline" packages
(Available Tape & ~eel), standard DIPs.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
PIN CONFIGURATION
SER
A
a
C
0
FUNCTION TABLE
H
CLR SH/LD
ClK
INH
ClK
SER
X
X
L
L
L
L
H
L
X
X
X
QH
G
ClK INH
ClK
E
GND
ClR
c8SAMSUNG
·Electronics
Inputs
Vee
SH/[5
L
H
H
H
H
H
X
X
L
H
H
X
t
t
t
t
H
L
X
Internal
Output
Parallel Outputs . QH
A ... H QA QB
X
X
a ... h
X
X
X
L
L
OAoOao
a
H
L
OHO
b
h
OAn
OGn
LOAn
OGn
GAOOaO
OHO
182
166
KS54AHCT
KS74AHCT
8-Bit Parallel-lnISerial-Out
Shift Registers with Clear
LOGIC DIAGRAM
PARALLEL INPUTS
•
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
CLK
CLK INH
CLR
SER
SH/LD
,....--
-u
-
~h
L~
fHh
A
L
B
fH'rI
C
L
PARALLEL
INPUTS
D
fHl
E
L
F
rHh
G
H
IHIl
--,
OUTPUT OH __ J
H
I I
...._ - - SERIAL SHIFT
CLEAR
c8SAMSUNG
Electronics
_I
-----1I--.j.
I~NHIBI:
H
L
I r--I-
H
L
H
SERIAL SHIFT
L
H
----<1-
LOAD
183
8-Bit Paral/el-lnISerial-Out
Shift Registers with Clear
KS54AHCT'166
KS74AHCT
Absolute Maximum Ratings·
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-O.5V < Vo < Vcc +0.5V) . . . . . . . . . ±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 1 25 mA
Storage Temperature Range, T519 ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°~
Recommended Operating Conditions
Supply Voltage, Vec .......... '. . . . 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vce
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . .. . Max 50~ ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 10% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
KS54AHCT
KS74AHCT
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low~Level
Input Voltage
VIL
0.8
0.8
0.8
1/
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=- 2OI-'A
10=-4mA
Vce -0.1
3.84
Vce -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=201-'A
lo=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vec or GND
±0.1
±1.0
±1.0
I-'A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
I-'A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Icc
VIN=Vec or GND
louT=OI-'A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10UT=01-'A
c8SAMSUNG
Electronics
Vce Vcc -0.1
4.2
3.98
0
184
KS54AHCT
KS74AHCT
166
8-Bit Parallel-lnISerial-Out
Shift Registers with Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Maximum Clock Frequency
fmax
Propagation Delay.
ClR to QH
tPHL
Propagation Delay.
ClK to QH
ClR low
Pulse Width
ClK High or low
Setup Time
Ta =25°C
Vcc=5.0V
KS74AHCT
KS54AHCT
T. = - 40°C to + 85°C ,T.= -55°C to +125°C
Unit
Vee = 5.0V :t: 10%
Vcc=5.0V:t: 10%
Typ
Min
60
36
Max
Min
Max
MHz
30
10
17
20
ns
13
13
21
21
25
25
ns
CL=50pF
~
tpHL
tw
SH/lD High
before ClKt
SER before ClKt
ClK INH before
before ClKt
Hold Time
Conditions t
(Input tr • tf~2 ns). AHCT166
tsu
8
12
15
8
12
15
8
12
15
8
12
15
8
12
15
Data before SH/lDt
8
12
15
ClR Inactive
before ClK
8
12
15
SH/lD High
after ClKt
5
8
10
SER after ClKt
5
8
10
ClK INH after ClKt
5
8
10
Data after SH/lDt
5
8
10
ClR Active
after ClKt
5
8
10
Input Capacitance
Power Dissipation Capacitance *
th
C'N
Cpo
5
ns
ns
II
ns
pF
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
185
KS54AHCT
KS74AHCT
16101
169
01
Synchronous 4-Bit Up/Down
Decade and Binary Counters
FEATURES
DESCRIPTION
• Fully Synchronous Operation for Counting and Programming
• Internal Look Ahead for Fast Counting
• Carry Output for N-bit Cascading
• Fully Independent Clock Circuit
• Function, pin-out; speed and drive compatibility with
-54/14ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These synchronous presettable counters feature an internal
carry look-ahead for cascading in high-speed counting applications. The '168 is a decade counter and the '169 is
a 4-bit binary counter. Synchronous operation is provided
by having all flip-flops clocked simultaneously so that the
outputs change coincident with each other when so in·
structed by the count enable inputs and internal gating. This
mode of operation helps eliminate the output counting
spikes that are normally associated with asynchronous (rip·
pie clock) counters. A buffered clock input triggers the four
flip-flops on the rising (positive-going) edge of the clock
waveform.
PIN CONFIGURATION
UfD
Vee
ClK
RCa
A
OA
B
Os
C
Oc
D
00
ENP
ENT
GND
lOAD
These counters are fully programmable; that is, the outputs may each be preset to either level. The load input circuitry allows loading with the carry-enable output of
cascaded counters. As loading is synchronous, setting up
a low level at the load input disables the counter and causes
the outputs to agree with the data inputs after the next clock
pulse.
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous application without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a carry output. Both count enable
inputs (ENP and ENT) must be low to count. The direction
of the count is determined by the level of the uio input.
When uio is high, the counter counts up; when low, it
counts down. Input ENT is fed forward to enable the carry
output. The ripple carry output (RCO) thus enabled will produce a low-level pulse while the count is zero (all inputs
low) counting down or maximum (9 or 15) counting up.
This lOW-level overflow carry pulse can be used to enable
successive cascaded stages. Transition at ENP or ENT are
allowed regardless of the level of the clock input.
These counters feature a fully independent clock circuit.
Changes at control inputs (ENP, ENT, LOAD, UiO) that will
modify the operating mode have no effect on the contents
of the counter until clocking occurs. The function of the
counter (whether enabled, disabled, loading, or counting)
will be dictated solely by the conditions meeting the stable
setup and hold times.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
c8SAMSUNG
Electrbnics
186
KS54AHCT
KS74AHCT
1681169
IJ
Synchronous 4-Bit Up/Down
Decade and Binary Counters
LOGIC DIAGRAMS
'168
I
c8SAMSUNG
Electronics
187
KS54AHCT
KS74AHCT
Synchronous 4·Blt Up/Down
Decade and Binary Counters
1681169
LOGIC DIAGRAMS
(continued)
LOAD ...,;(:,;;:.9:....)_---,
'169
(13)
B
Qa
(4)
C (5)
D (6)
'168
. lOjA:]:::+L
DATA
INPUT
'169
=
B~L=
~-
C-.J
: L.._
.,-D-----fJ -:-
ClK
.
aD::] .'
RCO::::~
: 7:: 8
9
0
1
2,
2
I II--COUNT UP-+INHIBIT~
...............
,
2: 1
LJr----0
9
~COUNT
8
DOWN--
lOAD
IIIstrated above is the following sequence:
1. Load (preset) to BCD seven
2. Count up to eight nine (maximum). zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum). nine, eight, and seven
c8SAMSUNG
Electronics
7
"
w
~,
RCO::~
,
:' .
LJ
::
.13,' 14 15 0 1 2.
2,2 I 1
0 15 14 13
tJJ--COUNT UP--+INHIBIT~
J---COUNT DOWNlOAD
IIIstrated above is the following sequence:
1. Load (preset) to BCD seven
2. Count up to eight nine (maximum). zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), nine, eight, and seven
188
KS54AHCT
KS74AHCT
168'169
If
Synchronous 4-Bit Up/Down
Decade and Binary Counters
FUNCTION TABLE
OUTPUTS
INPUTS
OPERAllNG MODE
ClK
u/D
ENP
ENT
lOAD
Dn
an
RCO
Parallel load
t
t
X
X
X
X
X
X
I
i
i
h
L
H
(1 )
(1 )
Count Up
t
h
I
I
h
X
Count Up
(1 )
Count Down
t
I
I
I
h
X
Count Down
(1 )
Hold
t
t
X
X
h
X
X
h
h
h
X
X
qn
qn
(1 )
H
H=HIGH voltage level steady state
h=HIGH voltage level'one setup time prior to the LOW-to-HIGH clock transition
L= LOW voltage level steady state
I=LOW voltage level one setup time prior to the LOW-to-HIGH clock transition
X=Don't care
q=Lower case letters indicate the state of the referenced output prior to the LOW-to-HIGH clock transition
t=LOW-to-HIGH clock transition
NOTE:
1. The AGO is LOW when ENT is LOW and the counter is at Terminal Count Terminal Count Up is (HHHH) and Terminal
. Count Down is (LLlL) for '169.
The RCO is LOW when ENT is LOW and the counter is at Terminal Count. Terminal Count Up is (HLLH) and Terminal
Count Down is (LLLL) for '168.
Absolute Maximum Ratings·
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI> Vec +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vce +0.5V)
±35 rnA
Continuous Current Through
Vcc or GND pins . .
± 125 rnA
Storage Temperature Range, Tstg ... -65°C to +150' o C
Power Dissipation Per Package, Pdt ...... 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
. Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vcc
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
189
I
KS54AHCT
KS74AHCT
16'01169
UI
Synchronous 4-Bit Up/Down
Decade and Binary Counters
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
Ta= -40°C to +85°(: Ta = -55°C to +125°C Unit
Ta=25°C
Test Conditions
Typ
Guaranteed Limits
Minimum High-level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum low-level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/AA
10= -4mA
Vee -0.1
3,84
Vee -0.1
3.7
V
Maximum low-level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/AA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/AA
Maximum' Quiescent
Supply Current
Icc
8.0
80.0
160.0
/AA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Iee
Vee Vee -0.1
3.98 .
4.2
0
VIN=Vee Qr GND
lour=O/AA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0/AA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Maximum Operating Frequency
f max
Propagation Delay,
ClK to RCO
tpLH
T. =25°C
Vcc=5.0V
KS74AHCT
KS54AHCT
T.= -40°C to +85°C T.=-55°C to +125°C
Vcc=5.0V:t10%
Vcc=5.0V:t 10%
Typ
Min
50
14
40
Max
Min
35
MHz
27
14
20
27
~
12
18
22
tpHL
12
18
22
Propagation Delay,
ENT to RCO
-
Propagation Delay,
UfO to RCO
-
Pulse Duration,
ClK high or low
tPHL
1----
CL=50pF
tPLH
10
16
19
tpHL
10
16
19
tPLH
13
19
24
tpHL
13
19
24
tw
8
12
15
20
Setup Time,
A, B, Cor 0
9
15
Before ClKt
ENP or ENT
9
15
15
lOAD
9
15
20
UfO
9
15
.20
th
0
0
Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
Hold Time,
Data after ClKt
:
'0
0
Unit
Max
20
-
Propagation Delay,
ClK to Any Q
Conditions t
(Input tr, tf~2 ns), AHCT168, AHCT169
ns
ns
ns
ns
- -f---
ns
ns
ns
pF
pF
, * Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
190
KS54AHCT
KS74AHCT
173
4-Bit 0-Type Registers with 3-State Outputs
FEATURES
DESCRIPTION
• Gated output control lines for enabling or disabling
the outputs
• Fully independent clock for operation in parallel-load
or hold modes
• For application as bus buffer registers
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOl = 24 mA @ VOL = O.5V for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 4-bit registers contain D-type flip-flops with 3-state outputs, capable of driving highly-capacitive or low-impedance
loads. This provides the device with the capability of being connected directly to and driving the bus lines in a busorganized system without need for interface or pull-up components,
Gated enable inputs are provided for controlling the entry
of data into the flip-flops. When both data-enable inputs
are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered
clock input. Gated output control inputs are also provided. When both are low, the normal logic states of the four
outputs are available for driving the loads or bus lines. The
outputs are di$abled independently from the level of the
clock by a high logiC level at either output control input.
The outputs then present a high impedance and neither
load nor drive the bus line. Detailed operation is given in
the function table.
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels, the output control circuitry is deSigned so that the average output disable
times are shorter than the average output enable times.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
PIN CONFIGURATION
M
Vee
N
ClR
10
20
30
40
ClK
GNO
10
20
3D
40
G2
G1
Input
ClR
H
L
L
L
L
L
elK
Output
Data Enable
Data
G1
G2
0
X
L
X
X
t
t
t
t
H
X
X
X
H
L
L
X
X
X
X
L
H
X
L
L
0
L
00
00
00
L
H
When either M or N (or both) is (are) high the output is disabled
to the high-impedance state; however sequential operation of the
flip-flo'ps is not affected.
c8SAMSUNG
Electronics
191
II
KS54AHCT 17~
KS74AHCT 10
4-Bit D-Type Register$'i with 3-State Outputs
LOGIC DIAGRAM
OUTPUT
CONTROL
{MI_(~1) - -
N-(2)-c1~-------------------'
o
(14)
DATA 10
------4---1--...
r----Q: ..... ClK
DATA {G1 (9)
ENABLE.G2 -~.J
(10)
DATA 20
ClR
o
~(13....:...)_ _+-_-+_-r-.....
e--t"~I"""
ClK
20
ClR
ClK
(12)
DATA 3 0 - - - - + - - - + - - - 1 - - . . .
30
(11)
0
0
DATA 40
ClK
a
(6)
40
ClR
CLR
c8SAMSUNG
Electronics
192
KS54AHCT
KS74AHCT
173
4-Bit D-Type Registers with3-State Outputs
Absolute Maximum Ratings·
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(V, < -0.5V or V, > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
. . . . . . . . . .. 4.5V to 5.5V
DC Input &. Output Voltages *, Y,N, Your
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
1nput Rise & Fall Times, t r , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Un'used inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed limits
Minimum High-Level
Input Voltage
V,H
2.0
2.0
Maximum Low-Level
Input Voltage
V,L
0.8
Minimum High-Level
Output Voltage
VOH
2.0
V
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
1----
V,N=V,H or V,L
10=-20/JA
10=-6mA
V,N=V,H or V,L
10= 2O/JA
10=12mA
10=24mA
Vee Vee -0.1
4.2
3.98
V
-.-t---
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
liN
V'N=Vee or GND
±0.1
±1.0
±1.0
/JA
Maximum 3-State
Leakage Current
loz
Output Enable
=V,H
Vour=Vee or GND
±0.5
±5.0
±10.0
/J A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/J A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
blcc
V'N=Vee or GND
10ur=0/JA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=0/JA
=8~SUNG
0
193
II
KS54AHCT
KS74AHCT
173
4-Bit D-Type Registers with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
fmax
Propagation Delay,
ClK to any Q
Pulse Width
ClK High
or low
Hold Time
After ClKt
Max
25
MHz
25
31
tpHL
CL=50pF
CL=150pF
13
16
21
26
25
31
tpHL
CL=50pF
CL=150pF
15
18
25
30
30
36
CL"'"50pF
CL"'"150pF
12
15
20
25
24
30
CL"'"50pF
CL"'"150pF
1.2
15
20
25
24
30
10
17
20
10
17
20
tpZH
-
-
tpHZ
ns
ns
RL = 1 kO
RL = 1kO, CL =50pF
tpLZ
7
12
15
7
12
15
tsu
8
15
20
7
12
15
7
12
15
th
-3
0
0
-3
0
0
CIN
Output Cipacitance
COUT Output Disabled
Power Dissipation
Capacitance *
Cpo
ns
ns
tw
Data
Input Capacitance
30
Min
21
26
CLR
Inactive
G1 and <32
50
Max
13
16
G1 and G2
Data
Min
CL=50pF
CL=150pF
CLR High
Setup Time,
before ClKt
Typ
tpLH
tPZL
Output Disable Time,
M or N to any Q
KS74AHCT
KS54AHCT
Ta=25°C
T.= -40°C to +85°C Ta= -55°C to +125°C
Unit
Vcc=S.OV
Vcc=S.OV±10%
Vcc=5.0V± 10%
ns
Propagation Delay,
ClR to any Q
Output Enable Time,
M or N to any Q
Conditions t
Symbol
Maximum Clock Frequency
(Input tr , tf~2 ns), AHCT173
ns
ns
5
pF
10
pF
pF
2
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
194
KS54AHCT
KS74AHCT
174/175.
Hex/Quad O-type Flip-Flops
with Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '1 74 contains six, and the' 1 75 contains four D·type
filp·flops all sharing a common clock and a common clear.
The '1 74 features single nail outputs for every flip-flops
whereas the '175 has complementary outputs.
Information at the D inputs meeting the setup time requirements is transferred to the 0 outputs on the positivegoing edge of the clock pulse. Clock triggering occurs at
a particular voltage level and is not directly related to the
transition time of the positive-going pulse. When the clock
input is at either the high or low level, the D input signal
has no effect at the output.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
PIN CONFIGURATIONS
'174
(Each Flip-Flop)
Inputs
Outputs
CIA
Vee
10
10
60
CLR
CLK
D
a
at
60
L
x
X
L
H
20
50
H
L
50
't
t
H
20
H
H
H
L
X
L
H
40
30
40
CLK
GNO
L
00 00
t '175 only
'175
CLR
Vee
10
10
10
20
20
40
40
30
20
30
GNO
c8SAMSUNG
Electronics
40
30
CLK
195
I
KS54AHCT
KS74AHCT
1741175
Hex/Quad D-type Flip-Flops
withe/ear
LOGIC DIAGRAMS
'175
'174
(3)
10
(4)
(2)
0
a
la
0
10
CLOCK
la
a
CLOCK
10
CLEAR
CLEAR
(4)
(5)
(5)
0
20
a
2a
(7)
a
0
20
CLOCK
CLOCK
a
(6)
(12)
(7)
a
0
(6)
20
CLEAR
CLEAR
3D
2a
3a
3D
a
0
(10)
3a
CLOCK
a
(11)
30
CLEAR
(11)
4a
a
(15)
(13)
(10)
4D
a
0
40
4a
(9)
CLK
CLOCK
(14)
0
CLEAR
40
CLEAR
CLR
50
(13)
(12)
0
a
50
CLOCK
CLEAR
(15)
(14)
60
CLK
a
0
6a
CLOCK
CLEAR
CLR
c8SAMSUNG
Electronics
196
KS54AHCT
KS74AHCT
1741175.
Hex/Quad D-type Flip-Flops
with Clear
Absolute Maximum Ratings·
Supply Voltage Range Vee, .. ,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
±125 mA
Vee or GND pins. . . . . . . .
Storage Temperature Range, TSlg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce . . . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
whieh permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
. Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta=-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level.
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/AA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/AA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
/AA
8.0
80.0
160.0
/AA
2.7
2.9
,3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Ice
.6.lee
VIN=Vee or GND
10uT=0/AA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10UT=0/AA
c8SAMSUNG.
Electronics
Vee Vee -0.1
3.98
4.2
0
'197
II
KS54AHCT 1~~/1~~
KS74AHCT
'/
Hex/Quad D-type Flip-Flops
with Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
f max
(Input t r , ft:~2 ns), AHCT174, AHCT175
KS74AHCT
KS54AHCT
T A=25°C TA== -40°C to +85°C TA= -55°C to +125°C
Vee == 5.0V
Vee==5.0V±10%
Vee=5.0V± 10%
Unit
Typ
Min
70
50
Max
Min
11
Input Capacitace
CIN
Power Dissipation Capacitance *
Cpo
5
--------------- ---------
MHz
20
o
>-------'---"-----~----------_+--"-'---+--
Max
40
0
+------------ -
o
ns
ns
pF
---------------t---------------l---------I---'----!
pF
* CPD determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SA~SUNG
Electronics
198
KS54AHCT
KS74AHCT
181
Arithmetic Logic Unitt
Function Generator
FEATURES.
DESCRIPTION
• Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus 12 other arithmetic operations
• Logic function modes:
Exclusive-OR
Comparator
AND,NAND,OR, NOR
Plus 10 other logic operations
• Full look-ahead for high-speed operations
on long words
The '1 81 is an Arithmetic LogiC Unit (ALU)/Function
Generator that performs 1 6 binary arithmetic operations
on two 4-bit words as shown in table 1 and 2. These operations are selected by the four functions select lines (SO,
S1, S2, S3) and include addition, subtraction, decrement
and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a
low level voltage to the mode control input(M). A full carry
look-ahead scheme is made available in these devices for
fast, simultaneous carry generation by means of 2 cascadeoutputs (p and (3) for the 4-bits in the package. When used in conjunction with AHCT182, high-speed arithmetic
operation can be performed. The typical addition times
shown in table below illustrates how little is required for
addition of longer words when full carry look-ahead is
emploved.
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current Outputs:
IOl=8mA @ VOl=O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include plastic "small outline"
packages, standard plastic and ceramic 300-mil DIPs
If high speed is not important, a ripple-carry input (C n ) and
a ripple-carry output (C n+4) are available. However, the
ripple-carry delay has also been minimized so that arithmetic
manipulations for small lengths can be performed· without
external circuitry.
The '1 81 will accommodate active-high or active-low data,
if the pin deSignations are interpreted as shown below.
Subtraction is accomplished by 1 's complement addition
where the 1 's complement of the subtrahend is generated
internally. The resultant output is A-B-1 , which requires and
end-around or forced carry to provide A-B.
The '181 can also be utilized as a comparator. The A=B
output is internally decoded from the function outputs (Fa,
F1, F2, F3) so that when two words of the equal magnitude
are applied at the A and B inputs, it will assume a high level'
to indicate equality (A=B). The ALU should be in the subtract mode with Cn=H when performing the comparison.
The A=B output is open-drain so that it can be wire-AND
connected to give a comparison for more than four bits.
The carry output (C n+4) can also be used to supply
relative magnitude information. Again, the ALU should be
placed in the subract mode by placing the function select
input S3, S2, S1, SO at L,H,H,L respectively.
PIN CONFIGURATION
BO
AO
S3
S2
S1
SO
Vee
A1
B1
1\2
B2
A3
B:3
G
C"
M
FO
F1
F2
These circuits have been designed to not only incorporate
all of the designer's requirements for arithmetic operations,
but also to provide 16 possible functions of two boolean
variables without the use of external circuitry. These logical
functions are selected by use of the four function select
inputs (SO, S1, S2, S3)with the mode control input (M)
at a high level to disable the internal carry.
The 16 logic functions are detailed in Tables 1 and 2 and
include exclusive-OR, NAND, AND, OR and NOR functions.
C,,+4
15
A=B
F3
GND
2
1
23
22
21
20
19
18
9
10
11
13
7
16
15
17
Ao
Bo
A1
81
A2
82
A3
83
Fa
F1
F2
F3
'Cn
Cn+4
P
G
Active-High Data (Table 2) Ao
Bo
A1
B1
A2
B2
A3
B3
Fa
F1
F2
F3
Cn
Cn+4
X
Y
Pin number
Active-Low Data (Table1)
=8SAMSUNG
Electronics
199
II
KS54AHCT
KS74AHCT
181
Arithmetic Logic Unitl
Function Generator
ALU SIGNAL DESIGNATION
The '181 can be used with the signal designations.
The logic functions and arithmetc operations obtained with
signal designations as in Table 1.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS P?wer levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
~;
(3)
(4)
81-----.
80
(16)
»-_ _ _Q..-/--- Cn +4
(15)
P
(13) _
>--<_--F3
(11) _
F2
81 (22)
(23)
A1
(10) _
F1
(1)
80
(9) FO
AO (2)
M
Cn
(7)
"'7
c8SAMSUNG
Electronics
200
181
KS54AHCT
KS74AHCT
Arithmetic Logic Unit/
Function Generator
o Table 1
Actl¥fH.ow Dati
Selection
M = L; Arithmetic Operations
M=H
S3
S2
S1
SO
Logic
Functions
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
F=A
F=AB
F=A + B
F=1
F=A + B
F=B
F=A?eB
F=A + B
F=AB
F=A EEl B
F=B
F=A + B
F=O
F=AB
F=AB
F=A
H
H
H
H
H
Cn=L
(no carry)
Cn=H
(with carry)
F=A Minus 1
F=AB Minus 1
F=AB Minus 1
F=Minus 1 (2's Camp)
F=A Plus (A + S)
F=AB Plus (A + S)
F=A Minus B Minus 1
F=A + B
F=A Plus (A + B)
F=A Plus B
F=AS Plus (A + B)
F=(A + B)
F=A Plus A*
F=AB Plus A
F=AB Plus A
F=A
F=A
F=AB
F=AB"
F=Zero
F=A Plus (A + "8) Plus 1
F=AB Plus (A + B) Plus 1
F=A Minus B
F=(A + B) Plus 1
F=A Plus (A + B) Plus 1
F=A Plus B Plus 1
F=A'e Plus (A + B) Plus I
F=(A + B) Plus 1 •
F=A Plus A Plus. 1
F=AB Plus A Plus 1
F=AB Plus A Plus 1
F=A Plus 1
II
o Table 2
Active-High Data
Selection
M = L; Arithmetic Operations
M=H
S3
S2
81'
80
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
L
L
L
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
logic
Functions
tn=l
(no carry)
Cn=H
(with carry)
F=A
F=A+B
F=AB
F=O
F=AS
F=B
F=A
F=A + B
F=A + B
F=Minus 1 (2's Camp)
F=A Plus AS
F=(A + B) Plus AS
F = A Minus B Minus 1
F=AB Minus 1
F=A Plus AB
F=A Plus B
F=(A + B) Plus AB
F=AB Minus 1
F=A Plus A*
F=(A + B) Plus A
F=(A + B) Plus A
F=A Minus 1
F=A Plus 1
F=(A + B) pius 1
F=(A +B) Plus 1
F=Zero
F=A Plus AS Plus 1
F=(A + B) Plus AS Plus 1
F=A Minus B
F=AB
F=A Plus AB Plus 1
F=A Plus B Plus 1
F=(A + B) Plus AB Plus 1
F=AB
F=A Plus A Plus 1
A=(A + B) Plus A Plus 1
F=(A + B) Plus A Plus 1
F=A
F=~
F=AS
F=A + B
F=A $B
F=B
F=AB
F=1
F=A + B
F=A + B
F=A
* Each bit is shifted to the next more significant position
c8SAMSUNG
Electronics
201
KS54AHCT
KS74AHCT
181
Arithme-tic Logic Unit/
Function Generator
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) ......... ±35 mA
Continuous Current Through
Vcc or GND pins . . . . . . . . . . . . . . .. ± 125 mA
Storage temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditioos
Supply Voltage, Vee .............. 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . ov to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
IKS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these cotlditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
T.=25°C
Symbol Test Conditions
Typ
KS54AHCT
KS74AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input .Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20l-'A
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20l-'A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
. 0.1
0.4
Maximum Input
Current
hN
VIN=Vce or GND
±0.1
±1.0
±1.0
IJ.A
Maximum Quiescent
Supply Current
Ice
VIN=Vee or GND
10uT=0l-'A
8.0
80.0
160.0
IJ.A
Additional Worst
Case Supply
Current
per input in
VI=2.4V
t.lee other Inputs:
a.t Vee or GND
10UT=0l-'A
2.7
2.9
3.0
mA
••
qsSAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
V
202
KS54AHCT
KS74AHCT
181
Arithmetic Logic Unitt
Function Generator
INPUT PAIRS HIGlfi/NOT HIGH TEST TABLE
FUNCTION INPUTS: S~! M 4.5 V,
S1 S3 0
= =
PARAMETER
INPUT
UNDER
TEST
tpLH
OTHER INPUT
SAME BIT
APPLY 4.5 V
OTHER DATA INPUTS
APPLY GND
;!;i
Si
None
Bi
Ai
None
so = = = v
Ai
Bi
None
APPLY GND
TEST
Remaining
e
p
A, Cn
In-Phase
Remaining
Remaining
p
In· Phase
B, Cn
A
Remaining
Remaining
e
Cn+4
Out-ot-Phase
A, Cn
Remaining
Remaining
e, Cn
Cn+4
Out-ot-Phase
A
OUTPUT
OUTPUT
UNDER
WAVEFORM
tpHL
tpLH
Bi
Ai
None
WAVEFORM
Remaining
tpHL
tpHL
OUTPUT
UNDER
APPLY 4.5 V
tpHL
tpLH
OUTPUT
tPHL
PARAMETER MEASUREMENT INFORMATION
SUM MODE TEST TABLE
FUNCTION INPUTS: SO S3 4.5 V, S1 S2
= =
INPUT
PARAMETER
tpLH
UNDER
OTHER INPUT
SAME BIT
TEST
APPLY 4.5 V
APPLY GND
Ai
Bi
None
tpHL
tPLH
tPLH
OTHER DATA INPUTS
APPLY 4.5 V
Remaining
A and B
Bi
Ai
None
tpHL
Remaining
A andB
Ai
Si
None
None
tpHL
tpLH
Bi
Ai
None
None
Ai
None
-
Bi
tpHL
tpLH
Bi
None
Ai
tpHL
tpLH
tpi-tL
tpLH
Cn
None
Ai
None
None
"Bi
tpHL
tpLH
tpHL
Bi
None
.c'SAMSUNG
-C
.
ElectrOnics
APPLY GND
TEST
Cn
Fi
In-Phase
Cn
Fi
In-Phase
15
In-Phase
15
In-Phase
G
In-Phone
G
In-Phase
Remaining
A and S,
Cn
Remaining
A and S, Cn
tpHL
tpLH
II
= =M =0 V
Ai
Remaining
Remaining
8
A, Cn
Remaining
Remaining
S
A, Cn
All
All
AnyF
A
B
or Cn+4
Remaining
Remaining
B
A, Cn
Remaining
Remaining
B
A, Cn
In-Phase
Cn+4
Out-ot-Phase
Cn+4
Out-ot-Phase
203
KS54AHCT
KS74AHCT
181
Arithmetic Logic Unitt
Function Generator
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
CL=50pF
tpLH
Propagation Delay,
Cn to Cn +4
f-------
Propagation Delay,
A orSto Cn +4
f-------
Propagation Delay,
A orB to Cn +4
f-------
Propagation Delay
AorBtoG
f-------
Propagation Delay
A. or Ijto G'
Propagation Delay
Po. orBto
P
tpHL
tPLH
tpHL
TPLH
tpHL·
tPLH
tpHL
tpLH
f-------
tpHL
tPLH
f-------
tPHL
tpLH
·Propagation Delay
A or B to is"
f-------
Propagation Delay
A or B to Fi
f-------
Propagation Delay
Po. or B to Fi
Propagation Delay
A orB to ~
Propagation Delay
Po. orB to A=B
tpHL
tpLH
tpHL
tPLH
M=SO=S3=OV
S1 =S2=4.5V
Max
16
24
29
16
24
29
17
17
17
·17
17
25
30
25
30
25
30
17
25
30
25
30
25
30
15
23
27
15
23
27
M=S1 =S2=OV
SO=S3=4.5V
16
24
29
16
24
29
M=S1 =S2=OV
SO=S3=4.5V
20
29
35
20
29
35
32
M=4.5V
tPZL
tpLH
Min
M=SO=S3=OV
S1 =S2=4.5V
tPLH
tpLZ
Max
17
17
M=SO=S3=OV
S1 =S2=4.5V
M=S1 =S2=OV
SO=S3=4.5V
Min
14
14
M=S1 =S2=OV
SO=S3=4.5V
tpHL
r---
Typ
8
8
M=SO=S3=OV
S1 =S2=4.5V
r---
KS74AHCT
KS54AHCT
T. =25°C
T. = -40°C to +85°C T.= -55 D C to +125°C
Vcc=5.0V
Unit
Vcc=5.0V:t10%
Vcc=5.0V:t 10%
M=OV,
Suiii or Diff Mode
tpHL
f-------
(Input tr , t~2 ns), AHCT181
M=SO=S3=OV
S1 =S2=4.5V
19
27
19
27
16
24
32
29
16
24
29
19
27
32
16
24
29
Propagatio!! Delay
Cn to any F
I-'---
15
23
24
tpHL
15
23
27
Ihput Capacitance
CIN
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Power Dissipation Capacitance *
pF
c8SAMSUNG
Electronics
204
Cpo
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
KS54AHCT
KS74AHCT
181
Arithmetic Logic Unitl
Function Generator
PARAMETER MEASUREMENT INFORMATION
LOGIC MODE TEST TABLE
FUNCTION INPUTS: 51 52 M 4.5 v, SO
= = =
INPUT
PARAMETER
UNDER
TEST
tpLH
Ai
OTHER INPUT
SAME BIT
APPLY 4.5 V
Si
OTHER DATA INPUTS
APPLY GND
None
APPLY 4.5 V
APPLY GND
Remaining
None
A and
tpHL
tpLH
=53 =0 v
Bi
Ai
None
OUTPUT
UNDER
WAVEFORM
TEST
Fi
Out-ot-Phase
Fi
Out-ot-Phase
S, C n
Remaining
None
OUTPUT
A and S, C n
tpHL
INPUT BITS EQUAL/NOT EQUAL TEST TABLE
FUNCT10N INPUTS: SO 53 M 4.5 V, 51 S2 0 V
= = =
INPUT
PARAMETER
UNDER
TEST
tpLH
Ai
OTHER INPUT
SAME BIT
APPLY 4.5 V
Si
APPLY GND
None
tPHL
tpLH
Si
Ai
None
tpHL
tpLH
Ai
None
Si
Bi
None
Ai
tpHL
tpLH
Ai
Si
None
tpHL
tpLH
Si
Ai
None
tpHL
tpLH
Ai
None
Remaining
A and
A and
Bi
Bi
None
c8SAMSUNG
Ai
OUTPUT
OUTPUT
UNDER
WAVEFORM
APPLY GND
TEST
None
j5
Out-ot-Phase
None
P
Out-ot-Phase
None
P
In-Phase
None
15
In-Phase
None
C n +4
In-Phase
None
C n+4
In-Phase
None
C n +4
Out-of-Phase
None
C n +4
Out-ot Phase
S, C n
Remaining
S, en
Remaining
Remaining
A and S,
en
Remaining
A and S,
Cn
Remaining
S,
Cn
Remaining
A and
tpHL
Electronics
APPLY 4.5 V
A and
tpHL
tPLH
OTHER DATA INPUTS
A and S, Cn
tpHL
tPLH
= =
S,
en
Remaining
A and S,
Cn
205
II
KS54AHCT
KS74AHCT
181
Arithmetic Logic Unit!
Function Generator
DIFF MODE TEST TABLE
FUNCTION INPUTS: S1 S2 4.5 V,
so =S3 =M =0 v
= =
PARAMETER
INPUT
OTHER INPUT
UNDER
SAME BIT
TEST
tpLH
Ai
APPLY 4.5 "oj
None
APPLY GND
Si
tpHL
tpLH
Si
Ai
None
APPLY 4.5 V
. APPLY GND
Remaining
Remaining
A
S, C n
Remaining
Remaining
A
tpHL
tPLH
OTHER DATA INPUTS
Ai
None
Bi
None
Bi
Ai
None
None
tPHL
tpLH
Ai
Si
None
None
Si
None
Ai
None
Ai
None
Bi
tpHL
tpLH
Bi
Ai
None
Remaining
A
Remaining
tpHL
A
tpLH
All
Cn
None
None
Ai
Bi
None
None
A and B,
Fi
In-Phase
Fi
Out-ot-~hase
15
In-Phase
15
Out-ot-Phase
..
.-
Cn
Remaining
A and B,
Remaining
S,
Cn
Remaining
B,
Bi
None
tpHL
=8SAMSUNG
Electronics
Ai
None
In-Phase
_._-
G
Out-ot-Phase
A==B
In-Phase
A==B
Out-ot-Phase
Cn
Remaining
S,
G
Cn
Cn
None
....
C n+4
or any
Remaining
A, S, C n
tpHL
tPLH
Remaining
A and S
tpHL
tpLH
TEST
Cn
Remaining
A and
tpHL
tpLH
WAVEFORM
--
tpHL
tpLH
OUTPUT
UNDER
A and S, C n
tPHL
tpLH
S,
OUTPUT
Remaining
A, B,
Cn
In-Phase
F
C n+4
Out-ot-Phase
C n+4
In-Phase
206
KS54AHCT
KS74AHCT
182
Look Ahead Carry Generator
FEATURES
DESCRIPTION
• Compatible Carry Functions for direct ALU connection
• Cascadable to perform look-ahead across n-bit
adders.
• High output current drive: IOL=8mA @ VOL= O.5V
• Low power consumption characteristic of CMOS
• Direct interface capability to TTL, NMOS and CMOS
devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
The '182 is a high-speed, look-ahead carry generator,
capable of anticipating a carry across four binary adders
or group of adders. These devices can be cascaded to
perform full look-ahead across n-bit adders. Carry,
generate-carry, and propagate-carry functions are provided
as shown in the pin deSignation table.
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
Carry input and output of the ALU's are in their true from,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, outputs, generate, and propagate) of the look-ahead
generators are implemented in the compatible forms for
direct connection to the ALU. Reinterpretations of carry
functions, as explained on the 181 data sheet are also applicable to and compatible with the look-ahead generator.
Logic equations for the 182 are:
PIN CONFIGURATION
"G"1
P1
GO
"G2
Po
Cn
G3
P3
Cn + x
When used in conjuction with the AHCT181 arithmetic logic
unit, these generators provide high-speed carry look-ahead
capability for any word length. Each 182 generates the
look-ahead (anticipated carry) across a group of four ALUs
and, in addition, other carry look-ahead circuits may be
employed to anticipate carry across sections of four lookahead packages up to n-bits. The method of cascading circuits to perform multi-level. look-ahead is illustrated under
typical application data.
Vee
P2
Cn+x=GO + PO Cn
Cn+y=G1 + P1 GO + P1 PO Cn
Cn+z=G2 + P2 G1 + P2 P1 GO + P2 P1 PO Cn
G=G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 GO
P-P3 P2 P1 PO
Cn + y
p
G
GND
C n+ z
PIN DESIGNATIONS
DeSignation
Pin No
Function
GO,G1,G2,G3
3,1,14,5
Active Low Carry Generate Inputs
PO,P1,P2,P3
4,2,15,6
Active Low Carry Propagate Inputs
Carry Input, Active HIGH
Cn
13
Cn+x,Cn+Y,Cn+z
12,11,9
G
10
P
7
Vcc
16
Supply Voltage
GND
8
Ground
=8SAMSUNG
Electronics
Carry Outputs
Active Low Carry Generate Output
Active Low Carry Propagae Output
207
I
KS54AHCT
KS74AHCT
182
Look Ahead Carry Generator
FUNCTION TABLES
LOGIC DIAGRAM
FOR GOUTPUT
INPUTS
OUTPUT
<33
G2
G1
GO
P3
P2
P1
~
L
X
X
X
X
L
X
X
X
X
X
L
X
L
L
L
X
X
L
L
X
X
X
L
L
L
L
L
H
X
L
X
X
All other combinations
OUTPUT
L
INPUTS
OUTPUT
PO
P
GO
PO
Cn
'C n+ x
L L L
All other
L
L
X
X
H
X L H
All other
H
H
P3 P2 P1
combinations
L
combinations
Cn+y OUTPUT
j52 (15)
G2
(14)
OUTPUT
INPUTS
<31
GO
P1
PO
Cn
C n+ y
L
X
X
X
X
X
L
L
L
X
X
L
H
H
H
L
X
~
FOR C n + x OUTPUT
FORPOUTPUT
INPUTS
\7)
X
H
All other combinations
P1 '(2)
<31 .:....(1..:....)t---t-+--H~
Cn+z OUTPUT
OUTPUT
INPUTS
G2
G1
L
X
X
X
X
GO
P2 P1
X
X X
L
X
L X
L
X
L
L
L
X
X
L
All other combinations
PO
Cn
Cn+z
X
X
X
X
X
X
L
H
H
H
H
H
L
H = high-level, L = low level, X = don't care
Any inputs not shown in a given table are don't care
with respect to that output.
Figure; THE '182 IN A 64-BIT LOOK-AHEAD CARRY CIRCUIT
'qsSAMSUNG
Electronics
208
KS54AHCT'182
KS74AHCT
Look Ahead Carry Generator
Absolute Maximum Ratings·
Supply Voltage Range Vce. . ...... -0.5V to + 7V
DC Input Diode Current. hK
(VI < -0.5V or VI > Vec +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vcc +0.5V) . . ..
±35 mA
Continuous Current Through
Vcc or GND pins . . . . . . . . . . . . .
± 125 mA
Storage Temperature Range, T519 . . . -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vcc
4.5V to 5.5V
DC Input & Output Voltages *. VIN. Your . . OV to Vee
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times. tr • tf . .
Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
-
(Vcc=5V+ 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltag.e
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-2OIAA
10=-4mA
Vee -0.1
3.84
Vec -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=201AA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
IAA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vcc or GND
±0.5
±5.0
±10.0
iJ A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
j.lA
2.7
2.9
3.0
mA
, Additional Worst
Case Supply
Current
~Icc
VIN=VCC or GND
10ur=OiJA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=OiJA
c8SAMSUNG
Electronics
Vcc Vee -0.1
4.2
3.98
0
209
II
KS54AHCT
KS74AHCT
182
Look Ahead Carry Generator
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input t r • ttE02 ns). AHCT182
KS74AHCT
KS54AHCT
T. =25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.0V
Vco=5.0V:t 10%
Vcc=5.0V::!:10%
Typ
Propagation Delay.
Pi or Gi to Cn+xCn+ y • Cn+ z
~
tpLH
Propagation Delay.
Pi or Gi to G
I--
Propagation Delay.
~
C n to Cn+ x. Cn+ y • Cn+ z
CL=50pF
tpHL
CL=50pF
tpHL
CL=50pF
tpHL
Min
Max
Min
Max
12
20
24
12
20
24
12
20
24
12
20
24
15
21
26
15
21
26
11
18
21
tP'HL
11
18
21
Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
Propagation Delay
PitoP
tpLH
I--
CL=50pF
ns
ns
ns
ns
pF
pF
* Cpo determines the no·load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8 SAMSUNG
Electronics
JCTOR
210
KS54AHCT
KS74AHCT
183
Dual Carry-Save Full Adders
FEATURES
DESCRIPTION
-
The '1 83 is a dual full adder features an individual carry
output from each bit for use in multiple-input, carry· save
techniques to produce the true sum and true carry out·
puts with no more than 2 gate delays.
For use in high-speed wallace-tree summing
Fast addition operation
Low power consumption characteristic of CMOS
High output current drive: IOL 8mA @ VOL O.5V
Direct interface capability with TTL, NMOS and
CMOS devices
-Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
=
=
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
- Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
LOGIC DIAGRAM
A..
NC
Vee
At,
B.
S.
S.
Cb
Cob
NC
GND
St,
c.
Coa
II
C
FUNCTION TABLE
(Each Half)
Output
Inputs
A
B
L
H
L
L
H
H
L
H
L
L
H
L
H
L
H
H
c8SAMSUNG
Electronics
C
S
Co
L
L
L
H
L
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
H
H
H
H
211
183
KS54AHCT
KS74AHCT
DUB' CBrry-8Bve Full Adders
Absolute Maximum Ratings·
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Sup~ly Voltage Range Vcc, .. . . . . . ~0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vcc +0.5V) . . . .. ±20 mA
DC Output Diode- Current, 10K
(Va < -0.5V or Va > Vce +0.5V) . . .. ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Va < Vcc +0.5V) ......... ±70 mA
Continuous Current Through
Vcc or GND pins . . . . . . . . . . . . . ... ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, fr, tf . . . . . . . . . Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
KS54AHCT
KS74AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Ta=25°C
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OI-'A
lo=-4mA
Vee -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2OiJA
lo=4mA
lo=8mA
0.1
0:26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
iJA
Maximum Quiescent
Supply Current
Icc
VIN=Vee or GND
IOUT=OiJA
2.0
20.0
40.0
iJA
Additional Worst
Case Supply
Current
per input in
VI=2.4V
.t.lec other Inputs:
at Vee or GND
IOUT=OiJA
2.7
2.9
3.0
rnA
Vee Vee -0.1
4.2
3.98
0
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input tr , t~6 ns), AHCT183
KS74AHCT
KS54AHCT
T.=25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Vee = 5.0V
Unit
Vce=5_0V± 10%
Vee=5.0V±10%
Typ
Min
Max
Min
Max
10
15
18
tpHL
13
20
24
Input CapaCitance
CIN
5
Power dissipation Capacitance·
Cpo
Propagation Delay
~
CL=50pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
ns
pF
pF
fin.
212
KS54AHCT
KS74AHCT
190
Synchronous 4-Bit Up/Down
Decade Counters
FEATURES
DESCRIPTION
• Single down/up count control line
• Look-ahead circuit enhances speed of cascaded
counters
• Fully synchronous In count modes
• Asynchronously presettable with load control
• Function, pilH)ut, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.SV to 5.SV
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small ·:;utline" packages
(Available Tape & Reel), standard DIPs.
These are high-speed synchronous reversible 4-bit decade
counters. Synchronous counting operation is provided by
having all flip-flops clocked simultaneously SO that the outputs change with each other when so instructed by the
steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous
(ripple clock) counters.
B
Vee
A
aA
CLK
ROO
CTEN
Diu
MAXIMIN
ae
~
aD
C
GND
D
FUNCTION TABLE
OPERATING MODE
parallel load
INPUTS
OUTPUTS
ilOOI
DID
~
ClK
Input
L
l
X
X
X
X
X
X
L
H
On
counl up
H
L
I
t
X
counl up
H
H
I
t
X
count down
hold (do nothing)
H
X
H
X
X
no change
~-
~ AND MAXIMIN FUNCTION TABLE
TERMINAL COUNT STATE
INPUTS
H
l
I
eTER
ClK
OA
08
Oc
H
l
l
l
H
H
H
X
X
H
H
H
L
l
l
X
X
X
X
X
X
L
l
l
L
l
l
z
=
=
X =
t =
l..f -
""L =
H
l
H
LS
H
X
X
l
LS
OD
H
H
H·
l
l
l
Two outputs have been made available to perform the
cascading function: ripple clock and maximum/minimum
count. The latter output produces a high-level output pulse
with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (9 or 15) counting up. The ripple clock
output produces a low-level output pulse under those same
conditions but only while the clock output to the enable
input of the succeeding counter if parallel clocking is used,
or to the .clock input if parallel enabling is used_ The
maximumlminimum count output can be used to accomplish
look-ahead for high-speed operation_
L
H
count down
DID
These counters feature a fully independent clock circuit.
Changes at the control inputs (CTEN and DID) that will
modify the operating mode have no affect on the contents
of the counter until clocking occurs_ The function of the
counter will be dictated solely by the condition meeting
the stable setup and hold times.
These counters are fully programmable; that is, the outputs may each be preset to either level by plaCing a low
on the load input and entering the desired data at the data
inputs. The output will change to agree with the data inputs independently of the level of the clock input. This
feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
PIN CONFIGURATION
as
The outputs of the four flip-flops are triggered on a low-tohigh-level transition of the clock input if the enable input
(CTEN) is low_ A high at CTEN inhibits counting. The direction of the count is determined by the level qf the downlup
(DID) input. When DID is low, the counter counts up and
when DID is high, it counts down.
OUTPUTS
MAXlMINr~
L
H
H
H
L
LS
l
H
H
H
L
LS
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
HIGH voltage level
lOW voltage level
lOW voltage level one setup lime prior to the LOW·to-HIGH ClK transition
Don't cere
lOW-la-HIGH CLK Iransilior>
one LOW level pulse
MAXIMIN goes lOW ON A lOW-la-HIGH CLK Iransition
c8SAMSUNG
Electronics
213
a
190
KS54AHCT
KS74AHCT· .
Synchronous 4-81t Up/Down
Decade Counters
LOGIC DIAGRAM
CTEN
DIU
ClK
lOAD
A
c
Typical load, count, and Inhibit sequences
:~.' :~~
(1) Load (preset) to BCD seven.
cSTJ'L
(2) Count up to eight, mine(maximum)
".'{O..
INPUTS'
I
I.
I
I
:
I
,
"
Sequence;
=
r -
.. o-+f- -
zero, one, and two.
(3) Inhibit
--------'
(4) Count down to one, zero
-=~j==~-:
(minimum), nine,egiht,
and seven
,
:
,
:
NOTE A: Clear overrides load data, and count inputs.
M"~'~:~L-_-;"_---;'---:-'--..JnL_ __
RC;--~r-';-i----u
U'---
Note B:When count up, count-down input must be high;
when counting down, countup intput must be high.
--- i 'i~--:oU"U:__+'NH""~' !---COUNTDOWN----/
~
ci$SAMSUNG
Electronics
.
214
KS54AHCT
KS74AHCT
190
Synchronous 4-Bit Up/Down
Decade Counters
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 rnA
Continuous Current Through
Vee or GND pins
± 125 rnA
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, Your
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these eOlldltions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vce or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
K5.S4AHCT
KS74AHCT
Ta = -40°C to +85°C Ta= -55°C to +1~~ Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
Maximum Low-Level
Input Voltage
VIL
2.0
2.0
2.0
0.8
0.8
0.8
V
f---------~-~----
--
Vce -0.1
3.7
V
-- ----
-----~----.-
----~
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2Ol-lA
10=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20l-lA
10=4mA
10=8mA
Maximum Input
Current
hN
VIN=Vec or GND
Maximum Quiescent
Supply Current
Icc
V
Vee Vee -0.1
4.2
3.98
0
Vee -0.1
3.84
0.1
0.26
0.39
0.1
0.33
0.5 ----_ .. -
0.1
0.4
V
±0.1
±1.0
±1.0
I-IA
8.0
80.0
160.0
I-IA
2.9
3.0
rnA
- -
VIN=Vec or GND
10ur=0l-lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=0l-lA
----~--------
[::-itional Worst
lease
Sopply
Current
~Ice
=8 ~t'!'ISUNG
1-----
i-----~
2.7
215
II
KS54AHCT
KS74AHCT
190
Synchronous 4-Bit Up/Down
Decade Counters
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input tr , tt~2 ns), AHCT190
KS74AHCT
KS54AHCT
T. =25°C
T. = -40°C to +85°C T.= -55°C to +125°C
Vcc=5.0V
Vcc=5.0V± 10%
Vcc=5.0V± 10%
Typ
Min
fmax
50
30
Propagation Delay,
lOAD to any Q
tpLH
r-----tpHL
18
30
36
18
30
36
Propagation Delay,
A,B,C, 0 to any Q
tpLH
r-----tpHL
13
21
25
13
21
25
Propagation Delay,
ClK to RCO
tpLH
r-----tpHL
12
20
24
12
20
24
Propagation Delay,
ClK to any Q
r--
11
18
22
11
18
22
19
31
37
19
31
37
Maximum Clock Frequency
tpLH
tpHL
Propagation Delay,
ClK to MAXIMIN
tPLH
r-----tpHL
Propagation Delay,
DID to RCO
r--
CL=50pF
Max
Min
Max
25
MHz
tpLH
19
32
38
tpHL
19
32
38
Propagation Delay,
0/0 to MAXIMIN
tpLH
r-----tpHL
15
25
30
15
25
30
Propagation Delay,
CTEN to RCO
r--
tpLH
11
18
22
tpHL
11
18
22
Pulse Width
Setup Time
10
17
20
lOAD low
12
20
25
Data before lOADt
10
17
20
CTEN before ClKt
10
17
20
DIU before ClKt
10
17
20
lOAD Inactive
before ClKt
10
17
20
ClK High or low
tw
tsu
Data after lOADt
Hold Time
CTEN after ClKt
th
DIU after ClKt
Input Capacitance
r--
2
4
5
a
a
0
a
0
0
--
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
. CIN
5
pF
CpD
80
pF
Power Dissipation Capacitance *
* CPD determines the no-load dynamic power dissipation: PD=CPD VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
I
c8SAMSUNG
Electronics
216
191
KS54AHCT
KS74AHCT
Synchronous 4-Bit Up/Down
Binary Counters
FEATURES
DESCRIPTION
• Single down/up count control line
• Look-ahead circuitry enhances speed of cascaded
counters
• Fully synchronous in count modes
• Asynchronously presettable with load control
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These are high-speed synchronous, reversible 4-bit binary
counters_ Synchronous counting operation is provided by
having all flip-flops clocked simultaneously so that the outputs change with each other when so instructed by the
steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous
(ripple clock) counters.
The outputs of the four flip-flOps are triggered on a low-tohigh-level transition· of the clock input if the enable input
(CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up
(DiD) input. When DiD is low, the counter counts up and
when O/U is high, it counts down.
These counters feature a fully independent clock circuit.
Changes at the control inputs (CTEN and O/U) that will
modify the operating mode have no affect on the contents
of the counter until clocking occurs. The function of the
counter will be dictated solely by the condition meeting
the stable setup and hold times.
These counters are fully programmable; that is, the outputs may each be preset to either level by placing a low
on the load input and entering the desired data at the data
inputs. The output will change to agree with the data inputs independently of the level of the clock input. This
feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
PIN CONFIGURATION
B
Vcc
as
A
OA
ClK
CTEN
Reo
Diu
Two outputs have been made available to perform the
cascading function: ripple clock and maximum/minimum
count. The latter output produces a high-level output pulse
with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (9 or 15) counting up. The nipple clock
output produces a low-level output pulse under those same
conditions but only while the clock output to the enable
input of the succeeding counter if parallel clocking is used,
or to the clock input if parallel enabling is used. The
maximum/minimum c')unt output can be used to accomplish
look-ahead for high-speed operation .
MAXIMIN
Oc
Il5A5
00
C
GND
D
FUNCTION TABLE
parallel load
-
DIU
CTEN
ClK
L
l
X
X
X
X
X
X
----
count up
H
I
H
--
hold (do nothing)
.
L
--
count/down
~----
LOAD
---
-
OUTPUTS
INPUTS
OPERATING MODE
H
H
j
X
I
t
I
I
t
H
X
-_
Input
-
l
H
t- ......
-t-o
-I-
... -
On
l
H
--
X
count up
X
j count_down
X
no change
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
RCO AND MAXIMIN FUNCTION TABLE
INPUTS
TERMINAL COUNT STATE
DIU
CfEN
ClK
QA
H
L
L
L
H
H
H
H
L
H
H
L
X
X
H
H
H
L
L
L
H =
L =
I =
X =
t =
V =
L =
li
X
X
li
r
i
I
Qs
X
X
X
L
L
L
Qc
Qo
X
H
H
H
L
L
L
X
X
L
L
L
OUTPUTS
MAXIMIN I EO
tl
H
H
1S
I
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
H
H
1S
HIGH voltage level
LOW voltage level
LOW voltage level one setup time prior to the LOW·to-HIGH eLK transition
Don't care
LOW-to-HIGH eLK transitior>
one LOW level pulse
MAXIMIN goes LOW ON A LOW-la-HIGH eLK transition
c8SAMSUNG'
Electronics
217
II
Synchronous 4-Bit Up/Down
Binary Counters
KS54AHCT·191
KS74AHCT.
LOGIC DIAGRAM
(12)
CTEN
~M~
~
DIU
CLK
MAX MIN
(4)
(14)V
~
tg
1
"I
1
'---
""
s
r-EL
r-- D
~~
J
~s~
r__
.
~i1t?
ft) u_
rL~
1
.....,.
--
--
I
~,
I
-p
D
D
~
~
0
C
---'--
~
0
B
(13)
~
LV
~
]
~;-~ Q c
~~
1_
rL~
~
r"""-!'
'f
I
1
I
~
~
~s
-
rB
~i1?7'
[~
rL~
'f
I
I
T
Typical Load, Count, and Inhibit Sequence
~~----------------------------DATA { :
INPUTS
~
CLK
DIU
CTEN
Q c ::,..'-tt-----,
__ I
~
~---r~~-+--~
_ _ ~I~--~
, - -_ _ _ __
_ ...J
MAXIMIN -
-l
RCO : :
1
H ~_____
Lr-------
-113 1415 0
.12
2 2 1 0
15 14 13
COUNT UP~ I-COUNT DOWN-I
Ur-
Sequence:
(1) Load (preset) to binary thirteen
(2) Count up to fourteen, fifteen, zero, one, and two
(3) Inhibit
(4) Count down to one, zero, fifteen, fourteen, and thirteen
LOAD
c8SAMSUNG
Electronics
218
KS5.4AHCT
KS74AHCT
191
Synchronous 4-Bit Up/Down
Binary Counters
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±.35 mA
Continuous Current Through
Vee or GND pins
. . . . . . . . . .. ± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always .be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
Typ
Ta
KS74AHCT
KS54AHCT
I
+85°C Ta= -55°C to +125°C Unitl
= -40°C to
--
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
Minimum High-Level
Output Voltage
VOH
Vee -0.1
3.84
Vee -0.1
3.7
Maximum Low-Level
Output Voltage
Maximum Input
Current
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
VOL
hN
Icc
L'llee
VIN=VIH or VIL
10=-20J.lA
10=-4mA
VIN=VIH or VIL
10=20J.lA
10=4mA
10=8mA
VIN = Vee or GND
VIN=Vee or GND
10uT=OJ.lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=OJ.lA
c8SA~SUNG
ElectrOnics
I
I
Guaranteed Limits
Vee Vee -0.1
3.98
4.2
vi
vl
V
0
I
-j
I
I
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
±0.1
±1.0
±1.0
8.0
80.0
160.0
i I-IA I
2.7
2.9
3.0
mA
i
V
I
I
:~i
219
II
KS54AHCT
KS74AHCT
191
Synchronous 4-Bit Up/Down
Binary Counters
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditlonst
(Input tr , tf~2 ns), AHCT191
KS74AHCT
KS54AHCT
T. ::;:25°C
T. = -40°C to +85°C T. = -55°C to + 125°C
Vcc=5.0V
Vcc=S.OV±10%
Vcc=S.OV± 10%
Typ
Min
f max
50
30
Propagation Delay,
lOAD to any Q
~
18
30
36
18
30
36
Propagation Delay,
A,B,C, D to any Q
~
13
21
25
tpHL
13
21
25
Propagation Delay,
ClK to RCO
-
Propagation Delay,
ClK to any Q
I----
Propagation Delay,
ClK to MAXIMIN
~
tpHL
Propagation Delay,
DIO to RCO
tpLH
r----tPHL
Propagation Delay,
DIU to MAXIMIN
tpLH
r----tpHL
Propagation Delay,
CTEN to RCO
tpLH
11
18
22
tpHL
11
18
22
Maximum Clock Frequency
Pulse !Width
Setup Time
tPHL
Min
Max
25
MHz
tPLH
12
20
24
tpHL
12
20
24
tPLH
11
18
22
tpHL
11
18
22
19
31
37
19
31
37
19
32
38
19
32
38
15
25
30
15
25
30
I----
CL=50pF
10
17
20
lOAD low
12
20
25
Data before lOADt
10
17
20
CTEN before ClKt
10
17
20
DIO before ClKt
10
17
20
lOAD Inactive
before ClKt
10
17
20
ClK High or low
tw
tsu
Data after lOADt
Hold Time
Max
CTEN after ClKt
th
DIU after ClKt
2
4
5
a
a
0
0
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
80
pF
* Cpo determines the no-load dynamic power dissipation: PO=CPD VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
220
KS54AHCT
KS74AHCT
192
Synchronous 4-Bit Up/Down
Decade Counters with Dual Clock
FEATURES
DESCRIPTION
• Look-ahead circuit enhances cascaded counters
• Fully synchronous in count modes
• Parallel asynchronous load for modulo-N count
lengths
• Asynchronous clear
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
These are high-speed synchronous reversible 4-bit decade
counters. Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the outputs change
coincidently with each other when so instructed by the
steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous
(!ripPie clock) counters.
The outputs of the four flip-flops are triggered by a low-tohigh-level transition of either count (clock) input (Up or
Down). The direction of counting is determined by which
count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the
load input and entering the desired data at the data inputs.
The output will change to agree with the data inputs independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
A clear input has been provided that forces all outputs to
the low level when a high level is applied. The clear function is independent of the count and the load inputs.
These counters were deSigned to be cascaded without the
need for external circuitry. The borrow output (80)
produces a low-level pulse while the count is zero (all outputs low) and the count-down input is low. Similarly, the
carry output (CO) produces a lOW-level pulse while the
count is maximum (9 or 15) and the count-up input is low.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count-down and countup inputs, respectively, of the succeeding counter.
PIN CONFIGURATION
B
Vee
OB
A
OA
ClR
00
DOWN
co
UP
Oc
LOAD
Qo
C
GND
0
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
INPUTS
OPERATING MODE
OUTPUTS
CLR
LOAD
UP
DOWN
A
B
C
D
QA
Qs
Qc
QD
CO
BO
reset (clear)
H
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
L
H
paraiel load
L
L
L
L
L
L
L
L
X
X
L
H
L
H
X
X
L
L
H
H
L
L
X
X
L
L
X
X
L
L
H
H
L
L
A
A
L
L
8
8
L
L
C
C
L
L
D
D
H
H
L
H
L
H
H
H
X
count up
L
H
t
H
X
X
X
count down
L
H
H
t
X
X
X
* CO=Up at terminal count up (HHHH)
* * 80=Down at terminal count down (LLLL)
H = HIGH voltage level
=8 !e!"SUNG
count up
H*
H
count down
H
H* *
=
L
LOW voltage level
X = don't care
t = LOW to HIGH clock transition
221
II
KS54AHCT192
KS74AHCT
Synchronous 4-Bit Up/Down
Decade Counters with Dual Clock
LOGIC DIAGRAM
(12)
Co
(13)
BO
up-------+----~+--+--~~_t
~-+~----------~~
Typical load, count, and Inhibit sequences
..
'{"':~,: ~ ~
INPUTS.
.....
I
1'_
c.J;:L -
D~=
• I
:
~,
---i---~
----,- -,'.:.,----------J
CTE~=~~=-~,t;.!:-----
Sequence;
(1) Load (preset) to BCD seven.
(2) Count up to eight, mine(maximum)
zero, one, and two.
(3) Inhibit
(4) Count down to one, zero
(minimum), nine, egiht,
and seven
NOTE A: Clear overrides load data, and count inputs.
Note B:When count up, count-down input must be high;
when counting down, countup intput must be high.
c8SAMSUNG
Electronics
.
222
KS54AHCT
KS74AHCT
192
Synchronous 4-81t Up/Down
Decade Counters with Dual Clock
Absolute Maximum Ratings·
t Power Dissipation temperatute derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ....... -0.5V to +7V
DC Input Diode Current, 11K
(V, < -0.5V or V, > Vee +0.5V) ..... ±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +O.SV) .... ±20 mA
Continuous Output Current Per Pin. 10
(-O.SV < Vo < Vee +O.SV) ......... ±3S mA
Continuous Current Through
Vee or GND pins ................ ±125 mA
Storage Temperature Range. Tstg ... -6SoC to +1S0°C
Power Dissipation Per Package. Pdt ...... SOO mW
Recommended Operating Conditions
Supply Voltage. Vce . . . . . . . . . . . . . . 4.SV to 5.5V
DC, Input & Output Voltages", VIN, VOUT . . OV to Vee
Operating Temperature
KS74AHCT: -40°C to +8SoC
Range
KSS4AHCT: -SsoC to +125°C
Input Rise & Fall Times, tr , tf ... , . . . . . Max SOO ns
.. Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee-5V± 10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +85°CTa= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
V,H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V,L
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
V'N=V'H or V,L
10=-20,u\
1e--4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=V,H or VIL
1e-20,u\
1e-4mA
1e=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
V'N=Vee or GND
±0.1
±1.0
±1.0
fAA
Icc
VIN-Vee or GND
IouT-O,u\
8.0
80.0
160.0
fAA
l!.1cc
per input in
V,=2.4V
other Inputs:
at Vee or GND
IouT-OfAA
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
c8SAMSUNG
Vee Vee -0.1
4.2
3.98
0
KS54AHCT
KS74AHCT
192
Synchronous 4-81t Up/Down
Decade. Counters with Dual Clock
AC ELECTRICAL CHARACTERISTICS
Characteristic
Maximum Clock Frequency
Propagation Delay.
UP to CO
: Propagation Delay.
DOWN to any Q
(Input tr • tfli;2 ns). AHCT192
KSS4AHCT
KS74AHCT
T.=2SoC
T... ~400C to +85°C T.= -55°C to +125°C
t
Unit
Symbol Condltlons Vcc=S.OV
Vcc=S.OV± 10%
Vcc=S.OV±10%
Typ
Min
fmax
50
30
~
11
18
22
11
18
22
11
18
22
11
18
22
tPLH
tPHL
tPLH
"---
tPHL
CL=50pF
Max
Min
Max
25
MHz
Propagation Delay.
UP or DOWN to any Q
I-----
11
19
23
tPHL
11
19
23
Propagation Delay.
LOAD to any Q
~
17
29
35
tPHL
17
29
35
Propagation Delay.
CLR to any Q
tPLH
10
17
20
6
10
15
tw
10
17
20
UP or DOWN High
or Low
10
17
20
Data before LOADt
10
17
29
CLR Inactive before
uPt or DOWNt
10
17
20
10
17
20
CLR High
LOAD Lo.w
Pulse Width
Setup Time
LOAD Inactive before
uPt or DOWNt
tsu
UP high before
DOWNt
Hold Time
10
17
17
Down high before uPt
8
15
15
Data after LOADt
0
0
0
0
0
0
3
8
6
UP High after DOWNt
th
DOWN High after uPt
ns
ns
ns
ns
ns
ns
ns
ns
Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
80
pF
* CpD determines the no-load dynamic power dissipation: PO=CPD Vee' fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
224
KS54AHCT
KS74AHCT
193
Synchronous 4-BitUplDown
Binary Counters with Dual Clock
FEATURES
DESCRIPTION
• Look-ahead circuitry enhances cascaded counters
• Fully synchronous in count modes
• Parallel asynchronous load for modulo-N count
lengths
• Asynchronous clear
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.SV
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These are high-speed synchronous reve(sible 4-bit binary
counters. Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the outputs change
cOincidently with each other when so instructed by the
steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous
(Iripple clock) counters.
The outputs of the four flip-flops are triggered by a low-tohigh-level transition of either count (clock) input (Up or
Down). The direction of counting is determined by which
count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by placing a Iowan the
load input and entering the desired data at the data inputs.
The output wi!1 change to agree with the data inputs independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
A clear input has been provided that forces all outputs to
the low level when a high level is applied. The clear function is independent of the count and the load inputs.
PIN CONFIGURATION
B
These counters were designed to be cascaded without the
need for external circuitry. The borrow output (80)
produces a low-level pulse while the count is zero (all outputs low) and the count-dowh input is low. Similarly, the
carry output (CO) produces a low-level pulse while the
count is maximum (9 or 15) and the count-up input is low.
The counters can then be easily cascaded by feeding the'
borrow and carry outputs to the count-down and countup inputs, respectively, of the succeeding counter.
Vee
OB
A
OA
CLR
DOWN
eo
UP
CO
Oe
l.OAD
c
00
D
GND
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground,
FUNCTION TABLE
OUTPUTS
INPUTS
OPERATING MODE
. _ - _ ..
CLR
LOAD
UP
DOWN
A
8
C
D
QA
Qs
Qc
QD
CO
80
reset (clear)
H
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
L
H
parailel load
L
L
L.
L
L
L
L
L
X
X
L
H
L
H
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
L
L
H
H
L
L
H
H
H
H
L
H
L
H
H
H
X
count up
L
H
t
H
X
X
X
count down
L
H
H
t
X
X
X
H= HIGH voltage level
L = LOW voltage lovel
X = don't care
H
-
count up
H*
H
couAt down
H
H* *
t=
LOW-to-HIGH clock transition
* CO = UP at terminal count up (HHHH)
* *. 80 = DOWN at terminal count down (LLLL)
=8SAMSUNG
Electronics
225
II
193.
KS54AHCT
KS74AHCT
Synchronous 4-81t Up/Down
Binary Counters with Dual Clock
LOGIC DIAGRAM
(12)
(13)
CLR (~
UP
DOWN
~
~)
(5)
(4)
LU
)1!.!lct>
LOAD
A
(151
~
B
FLJ
FU
,
~
~s
-
O.
~ Oc
..""'f
J
r--
FLJ
V_
Q
~ ~ rL~
~I>
R.J
0(9)
1--
'"'I
FU
~
....-
~ frU7
1'-'
FU
(10)
.
,-'"
(
C
rrEL·O.
~P
r: ~
~
~
-
-1J-
.A-
(1)
so
~ ~S~
~.
= -
~ cD
A
~
00
rL~
Typical Clear, Load, and Count Sequences
CUI
~--~~ ~--------------~--------------
.-+4-4-0-------------------
"{ ~
.-+4-4-0------------------.-++--+-i-------------------
DATA
D:C
COUNT UP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+-1-++---.
coum __~__~_4------------~
DOWN
ro--~-4~-+--~
10 1 ~31
~~
I
14
r---
15
r-----+-~----------_+-
0
1
2
I I
COUNT UP----1
r1
I
0
15
14 13
COUNT DOWN - ,
Sequence:
(1) Clear outputs to zero_
(2) Load (preset) to binary thirteen_
(3) Count up to fourteen, fifteen, carry, zero,
one and two.
(4) Count down to one, zero, borrow, fifteen,
fourteen, and thirteen.
Note A: Clear overrides load data, and count
inputs.
Note B: When counting up, count-down input
must be high; when counting down, count1
up input must be high_
CLEAR PRESET
c8SAMSUNG
. Electronics
226
KS54AHCT
KS74AHCT
193
Synchronous4-Bit Up/Down
Binary Counters with Dual Clock
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, ItK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vec or GND pins
± 125 mA
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to + 125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vec=5V±,10% Unless Otherwise Specified)
'Ta =25°C
Typ
KS74AHCT
KS54AHCT
+12~ Unit
Ta = -40°C to +85°C Ta = -55°C to
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
---_._- -
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
Vee -0.1
3.7
V
VIN=VIH or VIL
10=-20J-lA
10=-4mA
Vee Vee -0.1
4.2
3.98
Vee -0.1
3.84
.'-~'
Maximum Low-Level
Output Voltage
Maximum Input
Current
VOL
liN
VIN=VIH or VIL
10 = 20J-lA
10=4mA
10=8mA
VIN=Vee or GND
0
0.1
0.26
0.39
0.1
0.33
0.5
±0.1
±1.0
--~---
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
~Iee
VIN=Vee or GND
10UT=0J-lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=01.{A
=8SAMSUNG
Electronics
8.0
80.0
-
- - - - - - - - - - - t----
0.1
0.4
V
- - I~
±1.0
J-lA
r--.------. - -
- !-----
160.0
J-lA
--
2.7
2.9
3.0
mA
227
II
KS54AHCT
KS74AHCT
193
Synchronous 4-Bit Up/Down
Binary Counters with Dual Clock
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr ,
tf~2
T.=25°C
T.
Symbol Conditions t Vcc=5.0V
ns), AHCT193
KS74AHCT
=-40°C to +85°C
Vcc=5.0V:!:10%
Min
Max
Typ
Min
f max
50
30
Propagation Delay,
UP to CO
~
11
18
22
11
18
22
Propagation Delay,
DOWN to any Q
r--
Maximum Clock Frequency
,-------
Propagation Delay,
UP or DOWN to any Q
f--- ..
tpHL
Max
KS54AHCT
Ta= -55°C to +125°C
Unit
Vcc=5.0V:!: 10%
25
MHz
11
18
22
11
18
22
tpLH
11
19
23
tpHL
11
19
23
tpLH
tpHL
t---
CL=50pF
Propagation Delay,
LOAD to any Q
~
17
29
35
tpHL
17
29
35
Propagation Delay,
CLR to any Q
tpLH
10
17
20
6
10
15
tw
10
17
20
UP or DOWN High
or Low
10
17
20
Data before LOADt
10
17
29
CLR Inactive before
uPt or DOWNt
10
17
20
10
17
20
10
17
17
Down high before uPt
8
15
15
Data after LOADt
0
0
0
0
0
3
8
0
6
CLR High
LOAD Low
Pulse Width
Setup Time
LOAD Inactive before
uPt or DOWNt
tsu
UP high before
DOWNt
Hold Time
UP High after DOWNt
th
DOWN High after uPt
Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
80
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vce 2
t For AC switching test circuits and timing waveforms see section 2.
·c8SAMSUNG
Electronics
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
fin.
228
KS54AHCT
KS74AHCT
194
4-Bit Bidirectional
Universal Shift Registers
FEATURES
DESCRIPTION
•
•
•
•
•
•
These bidirectional shift registers feature parallel outputs,
right-shift and left-shift serial inputs, operating-mode-control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation:
•
•
•
. •
•
•
Parallel-ta-Serial, Serial-ta-Parallel Conversions
Left or Right Shifts
Parallel Synchronous Loading
Direct Overriding Clear
Temporary Data Latching Capability
Function, pin-out, speed and drive compatibility with
54174ALS logic family
Low power consumption characteristic of CMOS
High-Drive-Current outputs:
IOL =8 rnA @ VOL =0.5V
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: ~55°C to +125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
-
Inhibit clock (temporary data latch/do nothing)
Shift-right (in the direction QA toward QD)
Shift-left (in the direction QD toward QA)
Parallel (broadside) load
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs,
SO and S1, high. The data is loaded into the associated
flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow
is inhibited.
Shift-right is accomplished synchronously with the rising
edge of the clock pulse when SO is high and S1 is low.
Serial data for this mode is entered at the shift-right data
input. When SO is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial
inputs. Clocking of the flip-flop is inhibited when both mode
control inputs are low.
PIN CONFIGURATION
CLR
SR SER
A
B
c
D
SL SER
GND
Vee
aA
as
ae
aD
ClK
S1
SO
FUNCTION TABLE
.
INPUTS
CtR
L
H
H
H
H
H
H
H
MODE
CLK
S1 SO
X
X
H
L
L
H
H
L
X
X
H
H
H
L
L
L
X
L
t
t
t
t
t
X
OUTPUTS
SERIAL
PARALLEL
LEFT RIGHT
A B C D
X
X
X
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
a
X
X
X
X
X
X
X
b
X
X
X
X
X
X
X
c
X
X
X
X
X
X
X
d
X
X
X
X
X
QA
Qs
Qc
QD
L
QAO
a
H
L
QBn
QBn
QAO
L
QBO
b
QAn
QAn
QCn
QCn
QBO
L
Qco
c
QBn
QBn
QDN
QDn
Qco
L
QDO
d
QCn
QCn
H
L
QDO
H=high level (steady state)
L=low level (steady state)
X=irrelevant (any input, including transitions)
t=transition from low to high level
a,b,c,d=the level of steady-state input at
inputs A,S,C, or D, respectively.
QAO, QBO, Qco, QDo=the level of QA,
Qs, Qc, or QD, respectively, before
the indicated steady-state input conditions were established.
QAn, QBn, QCn, QDn=the level of QA,
Qs, Qc, respectively, before the mostrecent t transition of the clock.
229
II
4-Bit Bidirectional
Universal Shift Registers
LOGIC DIAGRAM
PARAllEL INPUTS
CON~
{51
so ..l!!L-D.......>---+-++-*----=J
INPUT
CLK (II)
CLR~I~I)~~-------4------"1~~---~---~.._---~--_r.TIO---~
ac
a.
(12)
aD
PARALLEL OU1PUTS
typical clear, load, right-shift, inhibit, and clear sequences
MODE {SO::..!
CONTROL
INPUTS
:
I
51 :::r-TlL...;.._______---1
ClEAR--:U !
I
I
SERIAL \
DATA
INPUTS
R
-';,-r-,-..;.----------:---r.....
,
'
I
L,
I
•
A~~--------+--7------~------~.' ,
PARALLEL
DATA
INPUTS
C--+FT1~
I
I
I
L
____________
~~
____.______ ________ __
~
~
'
I
I
OUTPUTS
---11---- INHIBIT----I
CLEAR
c8SAMSUNG
Electronics
230
KS54AHCT
KS74AHCT
194
4-Bit Bidirectional
Universal Shift Registers
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mWrC from 65°C to 85°C
Supply Voltage Range Vee.
. . . -0.5V to + 7V
DC Input Diode Current. 11K
(VI < -0.5V or VI > Vee +0.5V) ..... ±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current .Per Pin. 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
±125 mA
Storage Temperature Range. T8 tg . . . -65°C to +150°C
Power Dissipation Per Package. Pdt
500 mW
Recommended Operating Conditions
Supply Voltage. Vee
4.5V to 5.5V
DC Input & Output Voltages*. \tIN. VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times. tr • tf ...
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee""5V± 10% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Ta =25°C
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20J.lA
10= -4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20J.lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
J.lA
80.0
160.0
J.lA
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
l!.lee
VIN=Vec or GND
10UT==OJ.lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lOUT = OJJA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
8.0
2.7
I
231
I
KS54AHCT
KS74AHCT
194
4-Bit Bidirectional
Universal Shift Registers
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Input t r , tf~2 nS),·AHCT194
T. =25°C
Conditions 1 Vcc=5.0V
KS74AHCT
KS54AHCT
T.=-400Cto +85°C T. -55°C to +125°C
Vcc=5.0V±10%
Vcc=5.0V± 10%
=
Typ
Min
Maximum Clock Frequency
f max
60
35
Propagation Delay,
ClK to QH
tPLH
r---
10
17
20
10
17
20
Propagation Delay,
ClR to QH
tPHL
11
19
22
Pulse Width
ICLR lOW
IClK High Or lOW
Setup Time,
Any Input before CLKt
Hold Time,
Data after ClKt
tpHL
CL=50pF
Max
Min
17
20
10
17
20
ts
10
17
20
ts
-:-3
0
0
Input Capacitance
CIN
5
Power Dissipation Capacitance *
CPO
80
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
Max
MHz
30
10
tw
Unit
ns
ns
ns
ns
ns
pF
pF
fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
232
KS54AHCT
KS74AHCT
195
4-Bit Bidirectional
Universal Shift Registers
FEATURES
DESCRIPTION
• Parallel-to-Serial, Serial-ta-Parallel Conversions
• Parallel Synchronous loading
• J and K Inputs to First Stage
• Right-shift Only with Complementary Outputs on last
Stage
• Direct Overriding Clear
• Function, pin-out, speed and drive compatibility with
54/74AlS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 4-bit rigisters feature 'parallel inputs, parallel outputs,
J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation:
Parallel (broadside) load
Shift (in the direction AA toward QD)
Parallel loading is accomplished by applying the four bits
of data and taking the shift/load control input low. The data
are lOaded into the associated flip-flops and appear at the
outputs after the positive transition of the clock input. During
loading serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load
control input is high. Serial data for this mode is entered
at the J-K inputs. These inputs permit the first stage to perform as a J-K, D-, or T-type flip-flop as shown in the function table.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage leyels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
PIN CONFIGURATION
Vee
OA
K
Os
A
Oe
B
C
00
OD
D
ClK
GND
SH/[5
FUNCTION TABLE
INPUTS
CLR
L
H
H
H
H
H
H
SH/LD
X
L
H
H.
H
H
H
ClK
X
t
L
t
t
t
t
c8.sAMSUNG
Electronics
OUTPOUTS
SERIAL
PARAllEL
J
K
A B C D
X
X
X
L
L
H
H
X
X
X
H
L
H
L
X
a
X
X
X
X
X
X
b
X
X
X
X
X
X
c
X
X
X
X
X
X
d
X
X
X
X
X
QA
QB
Qc
QD
L
a
QAO
QAO
L
H
OAn
L
b
QBO
QAO
QAn
QAn
QAn
L
c
Qco
QBn
QBn
QBn
QBn
L
d
QDO
Qcn
Qcn
QCn
Ocn
QD
H
d
aDO
OCn
OCn
Ocn
QCn
H=high level (steady state)
L=low level (steady state)
X=irrelevant (any input, including tranSitions)
t=transition from low to high level
a,b,c,d=the level of steady-state input at
A,B,C, or D, respectively.
QAO, QBO, Qeo, QDo=the level of QA,
QB, ac, or QD, respectively, before
the indicated steady-state input conditions were established.
QAn, QBn, QCn=the level of QA, QB or Qc,
respectively, before the mostrecent
transition of the clock.
233
II
19'5
KS54AHCT
KS74AHCT
4-Bit Bidirectional'
Universal Shift Registers
LOGIC DIAGRAMS
SERIAL INPUT
~
J
(2)
K
(3)
PARALLEL INPUTS
~----------------~~--------------~
o
C
B
A
SH/ili ~(9~)~~-+~~~+-________~tCONTROL
(7)
(11)
(5)
(4)
________~~__________~
CLK (10)
CLRJ(~1)----~~----~~-+--~~~~--+---~---r+--t--~r---rt--t---~
(11)
00
PARALLEL OUTPUTS
typical clear, shift, and load sequences
CLK
I
I
-......:.----'~L----------....;..--i---------Ii"'"IL__________....!.._ _: -_ _ _ _ _ _ _ __
J
SERIAL {
INPUTS
K
SH/Lo--~----~I-------------__,~~~----------~----PARALLEL
IN~~~~
OUTPUTS
i
A__. . . :._____~___________________~L......:.------------------L
B
:
FHT'L......:..------------------
C
D
L
I
QA:::l
1
Q
s
:::::1,j,--------.;....---I
________ ______
________ ________ __
Qc:::~~:
~
Qo:::~~
~
I
I
CLEAR
c8SAMSUNG
Electronics
~
~
~
I
~---SERIAL SHIFT -----I
LOAD
r----SERIAL SHIFT - -
234
KS54AHCT
KS74AHCT
195
4-Bit Bidirectional
Universal Shift Registers
Absolute Maximum Ratings·
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI> Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins. . . . . . . .
± 125 mA
Storage Temperature Range, TSlg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, Your .. OV to Vee
Operating Temperature
Range
KS74AHCT: . -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level ,(either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/AA
lo=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2O/AA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/AA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/AA
2.7
2.9
3.0
mA
[Additional Worst
Case Supply
,current
.6.lee
VIN=Vee or GND
10ur=OiJA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour=OiJA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
235
I
KS54AHCT
KS74AHCT
195
4-Bit Bidirectional
Universal Shift Registers
AC ELECTRICAL CHARACTERISTICS
.Characteristic
Symbol
Conditions t
(Input tr , tf~2 ns), AHCT195
T. =25°C
Vee=5.0V
KS74AHCT
T.= -40°C to +85°C
Vee = 5.0V:t 10%
Typ
Min
Maximum Clock Frequency
fmax
60
35
Propagation Delay,
ClK to QH
tpLH
17
I---
10
20
10
17
20
Propagation Delay,
ClR to QH
tPHL
11
19
22
Pulse Width
Setup Time
before ClKt
Hold Time
after ClKt
tpHL
ClR Low
ClK High or Low
tw
SH/LD High
Serial or Parallel
Data
tsu
CL=50pF
Max
KS54AHCT
T.= -55°C to +125°C
Vce=5.0V:t 10%
Min
17
20
10
17
20
10
17
20
10
17
20
ClR inactive
10
17
20
SH/lD High
-3
0
0
Serial or Parallel
Data
-3
0
0
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
5
Max
30
10
Unit
MHz
ns
ns
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
236
KS54AHCT
KS74AHCT
210
Octal Buffers and Line Drivers
with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =24 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
. KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages·
(Available Tape & Reel), standard DIPs.
These high·speed octal buffers and line drivers are design·
ed specificaly to improve both the performance and density of 3·state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The deSigner has the choice of combinations of inverting
non·inverting outputs and symmetrical complementary input control (both active·low, or one active-low, the other
active·high).
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
I
LOGIC DIAGRAM
1<3
Vee
1A1
2G
2'(4
1'(1
1A2
2A4
2\(3
1Y2
(14) 1'(3
1A3
2A3
(12)
iV2
1'(3
1A4
2A2
2\(1
1'(4
GND
2A1
(18)
(16)
(9)
(7)
2A2
(5)
2A3
FUNCTION TABLE
Input
G
L
L
H
A
L
H
X
(3)
2A4
1Y1
_
1Y2
_
1Y4
2Y1
2V2
2V3
2'(4
Output
y
H
L
Z
c8SAMSUNG
Electronics
237
KS54AHCT
KS74AHCT
210
Octal Buffers and Line Drivers
with 3-State Outputs'
Absolute Maximum Ratings*
Supply Voltage Range Vee, ...... .-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) . .
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±70 mA
Continuous Current Through
Vec or GND pins ................ ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
'!'
Recommended Operating Conditions
Supply Voltage, Vee .............. ' 4;5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500ns
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS54AHCT
KS74AJ'lCT
Ta =-40°Cto +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits'
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20J.lA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20J.lA
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
J.lA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VOUT=VCC or GND
±0.5
±5.0
±10.0
/AA
Maximum Quiescent
Supply Current
Icc
VIN=VCC or GND
10uT=OJ.lA
8.0
80.0
160.0
J.lA
=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
238
KS54AHCT
KS74AHCT
210
Octal Buffers and Line Drivers
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Condltlons t
Symbol
(Input tr , tf~2 ns), AHCT210
KS74AHCT
KS54AHCT
T.=25°C
T.= -40°C to +85°C T.=-55°Cto +125°C
Vee = 5.0V
Vee=5.0V±10%
Vee=5.0V± 10%
Typ
proPfation Delay,
A to
Output En~ble Time,
Enable to Y
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance •
Max
Min
CL=50pF
CL=150pF
6
9
10
15
12
18
tpHL
CL=50pF
CL=150pF
7
10
16
12
19
20
25
24
30
24
30
tPZH
I----
RL=1kO
tpHZ
t-----
tpLZ
CL=50pF
CL=150pF
CL=50pF
CL=150pF
RL=1kO
CL=50pF
11
12
15
12
15
13
20
25
18
13
18
Unit
Max
tpLH
tpZL
Output Disable Time,
Enable to Y
Min
22
22
ns
ns
ns
5
pF
COUT
Output Disabled
10
pF
Cpo·
Output Disabled
Output Enabled
5
30
pF
CIN
• Cpo determines the no-load dynamic power dissipation: Po=Cpo
II
VCC 1 fin.
t For AC switching test circuits and timing waveforms see section 2 .
.c8SAMSUNG
Electronics
239
KS54AHCT238
KS74AHCT
3-Line 8-Line 'Dec~derSIDemultiplexers
FEATURES
DESCRIPTION
• Designed specifically for high-speed memory
decoders and data transmission systems.
• Incorporates 2 enable Inputs to simplify cascading
andlor data reception
These devices are designed to be used in highperformance memory-decoding or data-routing applications
requiring very short propagation delay times. In highperformance memory systems, these decoders can be
used with high-speed memorie!> utilizing a fast enable
circuit, the delay times of these decoders and the enable
time of the memory are usually less than the typical access
time of the memory. This means that the effective system
delay introduced by the decoder is negligible.
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & ~eel), standard DIPs.
This conditions at the binary select inputs and the three
enable inputs select one of eight input lines. Two activelow and one active-high enable inputs reduce the need for
external gates or inverters when expanding.
A 24-line decoder can be implemented without external
in'verters and a 31 -line decoder requires only one inverter.
An enable input can be used as a data Input for
demultiplexing applications.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
PIN CONFIGURATION
FUNCTION TABLE
A
Vee
B
C
yo
G2A
Y2
G2B
Y3
Gl
Y4
Y7
Y5
GND
Y6
c8'SAMSUNG
Electronics
Yl
Enable
Inputs
G1
G2*
X
L
H
H
H
H
H
X
L
L
Select
Inputs
Outputs
C B A
YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
L
L
X
X
L
L
L
L H
L
H
L
H
H
H
L
H L
H L
H L
L
L
H H
H H
X
X
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
L H L
L L H
L L L
L L L
L L L
L L L
L L L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H L
L H
L L
L L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H L
L
H
240
KS54AHCT
KS74AHCT
238
3-Line 8-Line Decoders/Demultiplexers
LOGIC DIAGRAM
II
Absolute Maximum Ratings*
Supply Voltage Range Vee, . . . . .
-0.5V to +7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±35 mA
Continuous Current Through
Vee or GND pins
± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability .
..c8.SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating. Conditions
Supply Voltage, Vee . . .. ........ 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, tt, tf ...
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
241
K$54~HC.J.
KS74AHCT
'238.
3-LineS-Line DecoderslDemultiplexlJrs
DC ELECTRICAL CHARACTERISTICS
(Vcc=5V±10% ,Unless Otherwise Specified)
.'
Characteristic
Symbol Test Conditions
TA=25°C
KS54AHCT
KS74AHCT
TA= .,..40°C to +85°C TA= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VII.j
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Lc;wel
Output Voltage
VOH
VIN=VIH or VIL
lo=- 2OIlA
lo=-4mA
Vcc -0.1
3.84
Vcc-0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=201lA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
O. i
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
IlA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
IlA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
lllcc
Vec Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
IOUT=OIlA
per Ihput pin
VI=2.4V
other Inputs:
at Vcc or GND
IOUT=OIlA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input tr , tf~2 ns), AHCT238
KS74AHCT
KS54AHCT
TA=25°C
TA= -40°C to +85°C TA= -55°C to +125°C
Vcc=5.0V
Vcc=5.0V±10%
Vcc=S.OV± 10%
Typ
Min
Max
Min
tPLH
12
20
24
tpHL
12
20
24
Propagation Delay,
A, B, Cor Y
-
Propagation Delay,
G1 to any Y
-
10 .
17
20
tpHL
10
17
20
Propagation Delay,
G2A or G2B to any Y
~
10
17
20
tPHL
10
17
20
tPLH
CL=50pF
Unit
Max
ns
ns
ns
Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
50
pF
* Cpo determines the no-load dy'namic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
242
KS54AHCT
KS74AHCT
239
Dual 1-0'-4 Decoderll)emulfiplexers
FEATURES
DESCRIPTION
• Designed specifically for high-speed memory
decoders and data transmission systems
• Incorporates 2 enable inputs to simplify cascading
and/or data reception
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices are designed to be used in highperformance memory-decoding or data-routing applications
requiring very short propagation delay times in highperformance memory systems, these decoders can be
used to minimize the effects of system decoding. When
used with high-speed memories utilizing a fast-enable
circuit, the delay times of these decoders and the enable
time of the memory are usually less than the typical access
time of the memory.
This means that the effective system delay introduced by
the decoder is negligible.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
A" inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
FUNCTION TABLE
PIN CONFIGURATION
Vee
1A
20
Enable
G
18
2A
1YO
28
1Y1
2YO
1Y2
2Y1
1Y3
2Y2
GND
2Y3
c8SAMSUNG
Electronics
Outputs
Inputs
1G
H
L
L
L
L
Select
B
A
X
X
L
L
H
H
L
H
L
H
--
YO
Y1
Y2
Y3
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
I
243
I
KS54AHCT
KS74AHCT
239
Dual 1-of-4 Decoder/Demultiplexers
LOGIC DIAGRAM
lYO
ENABLE
1<3
lYl
lY2
SELECT
INPUTS
lA
{
ENABLE
lB
(2)
(3)
lY3
DATA
OUTPUTS
_(15)
2G'
(14)
SELECT
INPUTS
2A
{
2B
(13)
Absolute Maximum Ratings*
Supply Voltage Range Vcc, . . .
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per' Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins . . . . . . . . . . . . . . .. ± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
• .Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc .............. 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf ......... Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
244
KS54AHCT
KS74AHCT
239
Dual 1-01-4 Decoder/Demultiplexers
DC ELECTRICAL CfiARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
Ta=25°C
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= .-55°C to +125°C Unit
Typ
Guaranteed limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
'lo=-20/AA
lo=-4mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2O/AA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
IrN
VIN=VCC or GND
±0.1
±1.0
±1.0
/AA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/AA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.6.lcc
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
louT=O/AA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
louT=O/AA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr • tf~2 ns). AHCT239
T. =25°C
Vee=5.0V
KS74AHCT
T. = -40°C to +85°C
Vee = 5.0V::!: 10%
Typ
Propagation Delay.
~or B to any Y
Propagation Delay.
G to any Y
Min
Max
KS54AHCT
T. = -55°C to +125°C
Vee=5.0V::!: 10%
Min
Max
tpLH
12
20
24
tpHL
12
20
24
CL =50pF
tpLH
10
17
20
tpHL
10
17
20
I----"
Unit
ns
ns
Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
50
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
~45
II
KS54~HCT'~B40124112440~tal Bufferssnd Lin,S Drivers
KS74AHCt, ' . : ; y , " .
.
with 3-State Outputs
"
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with drive current
(loL 24 mA @ VOL 0.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These high·speed octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
=
=
The designer has the choice of combinations of inverting/
non-inverting outputs and symmetrical complementary input control (both active-low, or one active-low, the other
active-high) .
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected frOAl damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAMS
PIN CONFIGURATION
'240
1G
,ii
Vee
lAl
2G/2G *
2Y4
1Y1
lA2
2A4
2Y3
1Y2
lA3
2A3
2Y2
1Y3
lA4
GND
1181
141
1181
'A2
181
181
_
2G
2A1
2A'
*2<3 for '240 and '244
2G for '241
2A2
2A3
2A4
,v,
'V2
'A2
1141 'V3
'A3
2A2
lY4
2Y1
_
,G
121
'244
'241
Itl
1'21
1'31
111
1'51
151
1111
. 131
1'81
141
1181
181
1'41
'V3
,ii
1'1
'A'
121
1121
2V'
1181
181
2A2
1'31
111
1151
151
1111
131
2V4
141
1'81
181
('4)
181
1121
,v3
_ 1'81
2G
2A' 1"1
2A3
1181
'A3
'V4
2G
181
121
181
1'81
1111
1'1
111;
181
1'31
2A2-'--
111
2V2
2V3
2~
tlSl
151
2V4
2A4
2Vl
2Y2
2Y3
1111
FUNCTION TABLE
'241, '244
Output
Input
'240
Output
G
G
A
Y
Y
H
H
L
L
L
L
L
H
H
H
X
H
Z
Z
cg !il!.'lSUNG
L
246
KS54AHCT 240/241/244octal Buffers and Line Drivers
KS74AHCT·
with 3-State Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vcc. . . . . . . . -0.5V to + 7V
DC Input Diode Current. hK
(VI < -0.5V or VI > Vcc +O.5V) .... , ±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vcc +0.5V) ... , ±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vcc +0.5V) ......... ±70 mA
Continuous Current Through
Vce or GND pins .............. '" ±250 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vce .............. 4.5V to 5.5V
DC Input & Output Voltages*. VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These. are stress ratings only and functional operation
of the device ator beyond them is not implied. Long exposure to these conditions mB:Y affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta == -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0:8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20/-IA
lo=-6mA
Vee -0.1
3.84
Vec '-0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2O/-lA
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
. 0.5
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/-IA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
/-I A
Maximum Quiescent
Supply Current
Icc
VIN=Veeor GND
10uT=O/-lA
8.0
80.0
160.0
/-IA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
0.1
-
247
I
KS54At:'CT~2~OI24112440Cfa/Bu"ersand Lin-. Drivers
KS74AHCT ,,';
,
with 3-8tate Outputs
AC ELECTRICAL CHARACTERISTICS
C~.r.cterlstlc
Condltlons t
Symbol
(Input t r • t~2 ns). AHCT240. AHCT241 • AHCT244
T. =2SOC
T.
Vce=S.ov
Typ
Propagation Delay.
A to Y
Output Enable Time.
Enable to Y
tpLH
CL=50pF
CL-150pF
6
tpHL
CL=50pF
CL=150pF
6
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance *
Min
9
Max
KSS4AHCT
T. = - Ssoc to + 12SOC
Unit
Vec=S.OV:!: 10%
Min
Max
10
15
12
18
12
18
ns
9
10
15
CL=50pF
CL=150pF
12
15
20
25
24
30
CL-50pF
CL=150pF
12
15
20
25
24
30
RL=l kO
CL=50pF
13
18
22
13
18
22
5
pF
COUT
Output Disabled
10
pF
Cpo
Output Disabled
Output Enabled
5
30
tPZH
f---
RL=lkO
tPZL
Output Disable Time.
Enable to Y
KS74AHCT
=- 40°C to + 8SOC
Vee =S.OV:!: 10%
~
tpu
CIN
'c8SAMSUNG
Electronics
ns
pF
* Cpo determines the no-load dynamic power dissipation: Po-Cpo VCC
t For AC switching test circuits and timing waveforms see section
ns
2
fin.
2.
248
KS54AHCT
KS74AHCT
2421243
I~
Quad Bus,,;'Transceivers
with 3-State Outputs
FEATURES
DESCRIPTION
• 2-Way Asynchronous Communication Between Data
Buses
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL =24 mA @ VOL =O.5V) for direct bus interface
• Inputs and outputs interface directfy with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.SV
• Characterized . for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These four-data line transceivers are designed for
asynchronous two-way communications between data
buses.
These devices provide speeds and drive capability
equivalent k> their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
FUNCTION TABLE
PIN CONFIGURATION
INPUTS
Vee
G8A
A1
NC
GAB
'242
GBA
'243
L
L
A to B
A to B
H
H
B to A
B to A
A2
81
A3
82
H
L
Isolation
Isolation
83
L
H
Isolation
Isolation
84
LOGIC DIAGRAMS
'242
'243
A1.;...;...------i
c8SAMSUNG
Electronics
II
KS54A~CI~'2421243
KS7 4AI;"ICT,:;: ,~f.q
....
Quad 'BusTransceivers
''Wifh3-State Outputs'
..•, ,
Absolute Maximum Ratings*
Supply Voltage; Range Vee. ' , , , , , , ~0.5V to + 7V
DC Input Diode, Current. 11K
M < -0.5V or VI > Vee +0.5V) , .... ±20 mA
DC Output Diode Current. 10K
(Vo <·-O.SV or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vee +0.5V) ......... ±70 mA
Continuous Current Through
Vee or GND pins .............. " ±250 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plast,c ~ackage (N): -12rnW/oC from 65,oC to 85,oC
Recommended Operating Conditions
Supply Voltage; Vee . . . . . . .. . . . . .. 4,5V to 5:5V
DC Input & Output Voltages·. VIN. VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times. tr.tl ......... Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unu~d inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 1..0% Unless Otherwise Specified)
Ta =25°C
Typ
KS14AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.t.lee
VIN=Vee or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
250
KS54AHCT
. KS74AHCT
24. 2'243
,~
AC ELECTRICAL CHARACTERISTICS
Chllr.ctwlstlc
CondHlon,t
Symbol
Quad Bus. Transceivers
with 3-State Outputs
(Input tr, t,<2 ns), AHCT242, AHCT243
KS74AHCT
KS54AHCT
T. -2S·C
T•• -40·C to +,soc T.;"-5S0Cto +12SOC
Unit
Ycc-s.o y
Ycc=5.0Y:t: 10%
Ycc- S•OY :t:10%
Typ
Propagation Delay,
AtoBorBtoA
Output Enable Time
GAB to B, GBA to A
tPLH
CL=50pF
CL=150pF
tPHL
CL=50pF
CL=150pF
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance * (per stage)
10
7
10
CL=50pF
CL=150pF
12
15
CL=50pF
CL =150pF
12
15
Mu
Min
Mu
11
16
15
21
11
16
15
21
25
21
25
ns
RL=1kO
CL=50pF
12
20
25
20
25
20
12
20
5
pF
COUT
Output Disabled
10
pF
Cpo
Output Enabled
Output Disabled
30
5
pF
tPZH
r----- RL=1kO
tPZL
Output Disable Time,
GAB to B, GBA to A
Min
7
~
tpLZ
CIN
* Cpo determines the no-load dynamiC power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
.
ns
25
21
25
ns
II
fin.
251
. KS54AHCT
KS74AHCT
2.4.5
Octal Bus Transceivers with
3-StateOutputs .
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/7 4A~S logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(loL 24 mA @ VOL O.5V) for direct bus interface
.' Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These high-speed octal bus transceivers are designed
for synchronous two-way communication between data
buses. The control function implementation minimizes
external timing requirements.
=
=
The devices allow data transmission from the A bus to
the B bus or from the B bus to the A bus depending
upon the logic level at the direction control (DIR) input.
The enable input (G) can be used to disable the device
so that the buses are effectively isolated.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
OIR
Vee
A1
G
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
GNO
B8
(19)
G
(1S)
61
(17)
62
(16)
B3
(15)
64
FUNCTION TABLE
(14)
65
(13)
Inputs
66
Operation
G
DIR
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
Isolation
A7
(12)
B7
AS
(11)
6S
c8SAMSUNG
Electronics
252
KS54AHCT
KS74AHCT
245
Octal Bus Transceivers with
3-State Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vee, ..
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins. . . . . . . . .
±250 mA
Storage Temperature Range, Tstg . . . - 65 ° C to + 150 ° C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vce
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, t r , tf
... Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
Typ
KS54AHCT
KS74AHCT
Ta = -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20J.lA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20J.lA
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
J.lA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
J.lA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
J.lA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
ll.lee
VIN=Vee or GND
10uT=OJ.lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=OJ.lA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
253
I
Octa/BuB Transceivers-with
3-StateOutputs'. .
'
KS54AHCT·245
KS74AHCT
AC ELECTRICAL CHARACTERISTICS
(Input
tr. tf~2
ns). AHCT245
"
Chtracterlltlc
Condltlons t
Symbol
KS74AHCT
KS54AHCT
T.-2S·C
T.... -40·C to ,+85°C T.", -5SOC to +125·C
Unit
Ycc-S.OY
Ycc=S.OY:t 10%
Ycc-S.OY:t10%
Typ
Propagation Delay.
AtoBorBtoA
Qutput Enable Time
GtoAorB
tpLH
CL=50pF.CL==150pF
tpHL
CL=50pF
CL=150pF
tPZH
I - - - - RL=1 kG
Input Capacitance
Output Capacitance
.Power Dissipation
Capacitance *
~
tpLZ'
Cpo
Min
Max
11
15
14
20
10
15
14
20
CL=50pF
CL=150pF
12
1.15
20
25
25
31
CL=50pF
CL=150pF
12
25
31
ns
ns
17
RL=1kG
CL==50pF
13
18
22
13
18
22
5
pF
Output Disabled
10
pF
~=Vcc
5
30
CIN
COUT
9
7
9
Max
20
25
tPZL
Output Disable Time.
Gto Aor B
Min
7
G=GND
(per stage)
ns
pF
2
* Cpo determines the no-load dynamic power dissipation: PO=CPD VCC fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
,254
1-of-8 Data Select~/Multiplexers
with 3-State Outputl \~ . ,;. . .
KS54AHCT251
KS74AHCT
FEATURES
DESCRIPTION
• Three-State Version of '151
• Three-State Outputs Interface Directly with System
Bus
• Performs Parallel-ta-Serial Conversion
• Compiementary Outputs Provide True and Inverted
Data
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3~tate outputs with high drive current
(Iol = 24 mA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These· data selectors/multiplexers contain full binary
decoding to select one-of-eight data sources and feature
strobe-controlled complementary three-state outputs.
The three-state outputs can interface with and drive data
lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state), the lowimpedance of the single enabled output will drive the bus
line to a high or low logic level. Both outputs are controlled by the strobe (<3). The outputs are disabled when G is
high.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
D3
Vee
02
04
01
05
DO
Y
06
W
A
00(-4)------F~~~~)
--:-----lrF~~~:J
Ol.>.:C(3.:....)
07
G
B
GNO
C
03(1)
I~~~~
04 (15)
.:...-..:....----i=!=~~J
FUNCTION TABLE
INPUTS
SELECT
C
STROBE
A
G
X X X
H
L
L
L
L
L
L
L
L
L
L
L
L
B
OUTPUTS
L L
L H
H L
H H
H L ·L
H L 'H
H H L
H H H
Y
W
Z
DO
Z
DO
01
02
03
04
05
06
07
51
02
03
04
05
06
07
c8SAMSUNG
Electronics
2'55
I
KS54AHC'T
KS74AHCT
251
f-of-8 DiI,ta ~Se/ectorslMulll.iplexers
with 3-State Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vee, '...... -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5\1 or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) .... , .... ±70 mA
Continuous Current Through
Vec or GND pins . . . . . . . . . . . . . . .. ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc ........... , . . 4.5V to 5.5V
DC Input & Output Voltages *, VIN, Your . . OV to Vcc
Operating Temperature
~
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ... , ... , . Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
()f the device, at or beyond them is not implied. Long exposure to these conditions may affect device reliability,
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTI'CS
c:!laracteristic
Symbol Test Conditions
(Vec=5V±10% Unless Otherwise Specified)
Ta =25°C
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20jJA
10= -6mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20jJA
lo=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
JJA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vcc or GND
±0.5
±5.0
±10.0
JJA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
JJA
3.0
mA
Additional Worst
Case Supply
Current
,
KS54AHCT
KS74AHCT
Ta = -40°C to +85°C Ta = -55°C to +125°C Unit
.6lcc
VIN=Vee or GND
lour=OjJA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=OjJA
c8SAMSUNG
Electronics
.
Vee Vce -0.1
4.2
3.98
0
.
2·l
2.9
256
KS54AHCT
KS74AHCT
251.
1-0'-8 Data Selectors/Multiplexers'
';'k'~
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Conditions t
Symbol
(Input tr , tf<2 ns), AHCT251
T. =25°C
T.
Vee = 5.0V
i
Typ
Propagation Delay,
A, B or C to Y
Propagation Delay,
A, B or C to W
Propagation Delay,
Any D to Y
Propagation Delay,
Any D to W
Qutput Enable Time,
GtoYorW
-
Input Capacitance
Min
Max
Min
Milic
tPLH
CL=50pF
CL=150pF
13
16
21
26
25
31
tPHL
CL=50pF
CL=150pF
13
16
21
26
25
31
tPLH
CL=50pF
CL=150pF
15
18
24
29
27
33
tPHL
CL=50pF
CL=150pF
15
18
24
29
27
33
tPLH
CL=50pF
CL=150pF
9
12
15
20
18
24
tPHL
CL=50pF
CL =150pF
12
15
20
18
24
tpLH
CL=50pF
CL=150pF
8
11
15
20
18
24
tpHL
CL=50pF
CL=150pF
8
11
15
20
18
24
CL=50pF
CL=150pF
11
14
18
23
28
CL=50pF
CL=150pF
11
14
13
18
23
18
CL=50pF
13
18
5
pF
Output Disabled
10
pF
tPZH
RL=1kO
tPZL
Output Disable Time,
GtoYorW
KS54AHCT
KS74AHCT
+85°C T.= -55°C to +125°C
Unit
Vee=5.0V±10%
Vec=5.0V± 10%
=-40°C to
~ RL=1k:O
tpLZ
CIN
Output Capacitance
COUT
Power Dissipation
Capacitance *
Cpo
9
ns
ns
ns
ns
22
ns
22
28
22
22
·ns
pF
* Cpo determines the no-load dynamic power. dissipation: Po=Cpo VCC 1 , fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
257
I
;K'S5:4~HCt"2S3
KS74AHCT
,"
-
FEATUR,ES
DESCRIPTION
•
•
•
•
Each of these data selectors/multiplexers contains inverters
and drivers to supply full binary decoding data selection to
the AND-OR gates. Separate output control inputs are provided for each of the two four-line sections.
•
•
•
•
•
•
Three-State Ver.sion of '153
Permits Multiplexing from N Lines to 1 Line
Performs Parallel-to-Serial Conversion
Function, pin-out, speed and drive compatibility with
54/74ALS logic family
Low power consumption characteristic of CMOS
3-5tate outputs with high drive curr~nt
(loL = 24 mA @ VOL = O.5V) for direct bus interface
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°b to + 125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
1G
:~
Vee
B
-
The three-state outputs can interface with and drive data
lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state) the lowimpedance of the single enabled output will drive the bus
line to a high or low logic level. Each output has its own
strobe (G). The output is disabled when its strobe is high.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
SELECT
DATA INPUTS
OUTPUT
CONTROL
OUTPUT
CO C1 C2 C3
G
y
H
L
L
L
L
L
L
L
L
Z
2G
1C3
A
1C2
1C1
2C3
1CO
2C1
2C2
1Y
GND
"
Dual 1-01·4' Data Selectors/Multiplexers
with 3-State Outputs '
',
.
,
B
A
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X L
X (H
L
H
L
H
L
H
L
H
Address inputs A and 8 are common to both sections.
,
........
\
c8SAMSUNG
Electronics
258
KS54AHCT
KS74AHCT
253
.Dual 1-01-4 Data Selectors/Multiplexers
with 3-State Outputs
LOGIC DIAGRAM
lG
(6)
lCO
DATA 1
lCl
(5)
OUTPUT
lY
lC2
lC3
~~cr(
(4)
(3)
B
I
A
2CO
2Cl
(101
(11)
DATA 2
2C2
(12)
2C3
(13)
2G
(15)
OUTPUT
2Y
Absolute Maximum Ratings*
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . . . . . .. ±70 mA
Continuous Current Through
Vee or GND pins ................ ±250 mA
Storage Temp~rature Range, T8 1g ••• -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power DiSSipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . , ........ , .... 4.5V to 5.5V
DC Input & Output Voltages·, V/N, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf .
Max 500ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
259
253
KS54AHCT
KS74AHCT
Dual 1-01-4 Data Selectors/Multiplexers
with 3-5tate-:Outputs
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V± 1 0% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
T.=-40°Cto +85°C T.=-55°Cto +125°C Unit
T.=25°C
Symbol Test Conditions
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20JolA
10=-6mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20JolA
10=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
JoIA
Maximum 3-State
.Leakage Current
loz
Output Enable
=VIH
VOUT=VCC or GND
±0.5
±5.0
±10.0
jJA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
JoIA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
louT=OjJA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
IOUT=OJolA
~Icc
AC ELECTRICAL CHARACTERISTICS
Characteristic
Conditions t
Symbol
(Input tr • tl"2 ns). AHCT253
KS74AHCT
KS54AHCT
T. = 25°C
T. = -40°C to +85°C T. = -55°C to +125°C
Vcc=5.0V
Vcc=5.0V::t:10%
Vcc=5.0V::t: 10%
Min
Typ
Propagation Delay.
A or 8 to any Y
Propagation Delay.
Data (any C) to -any Y
tpLH
13
16
21
26
tpHL
CL=50pF
CL=150pF
13
16
21
26
-
tpLH
CL=50pF
CL=150pF
9
12
CL=50pF
CL =150pF
tpHL
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance *
-
--
tpHZ
tpLZ
-
ns
13
20
18
34
CL=50pF
CL=150pF
10
13
16
21
19
35
CL=50pF
CL =150pF
10
13
16
21
19
35
RL=1kO
CL =50pF
13
18
22
13
18
22
5
pF
Output Disabled
10
pF
CIN
COUT
25
31
25
31
9
12
tPZL
Output Disable Time.
G to Y
13
Max
18
34
RL=1kO
-
-
Min
20
tPZH
Qutput Enable Time
G to Y
Max
CL=50pF
CL=150pF
Unit
--
ns
ns
ns
pF
Cpo
2
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
260
KS54AHCT
KS74AHCT
2571258
Quad 2-Line to 1-Line Data Selectorl
Multiplexers with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL = 24 mA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include" small outline" packages
(Available Tape & Reel), standard DIPs.
The '257 and '258 multiplex signals from for-bit data
sources to four-output data lines in bus organized systems.
The data presented at the outputs is non-inverted for the
'257, and inverted for the '258.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
FUNCTION TABLE
PIN CONFIGURATION
Inputs
AlB
Vee
1A
G
1B
4A
1Y
4B
2A
4Y
2B
3A
2Y
3B
GND
3Y
Output Y
Output
Control
Select
G
AlB
A
B
H
X
L
L
X
L
H
H
H
X
X
X
X
X
L
H
L
L
L
L
Data
'257
'258
Z
Z
H
L
H
L
L
HO
H
L
LOGIC DIAGRAMS
'257
1A ____________
'258
-+~~
1Y
1B-----------+~~~
2A-----------+~~
1Y
1B
2Y
2A
2Y
2B
2B-----------+~~~
3A-----------+~4_~
1A
3Y
3Y
3B-----------+~~-I
4A __________
-+~~-I
4Y
4B~
________
~~~
=8SAMSUNG
Electronics
261
II
.
,
,
.'
"zr"58
Qua.d 2-Line to. 1-Line Data5electorl
~ ...... Multiplexers with a-State Outputs
KS54AHCT 2·5·
.KS74AHCT ... ' I.J~
Absolute Maximum Ratings*
Supply Voltage Range Vee, ....... ~0.5Vt~ + tv
DC Input Diode Current, hK
('11< -o.sv or VI > Vee +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -O.SV or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(--0.5V Vo <: Vce +0.5V) ......... ±70 mA
Continuous Current Through
.
\Icc or GND pins ................ ±250 mA
Storage Temperature Range, T8 1g ••• -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mWI.°C from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . .. . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN, Your .. OV to Vcc
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
<
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These ar,e stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V± 10% Unless Otherwise Specified)
Ta =25°C
I
KS74AHCT
KS54AHCT
Ta = -40!»C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20jJA
10=-6mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20jJA
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
Maximum Inpu)
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vce or GND
±0.5
±5.0
±10.0
JJA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
JJA
2.7
2.9
3.0
mA
'.
Additional Worst
Case Supply
Current
~Icc
VIN=VCC or GND
10ur-OjJA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10ur=OjJA
c8~SUNG
Vcc Vcc -0.1
4.2
3.98
0
V
,
JJA
262
KS54AHCT
KS74AHCT
257/258
Quad 2-Line to 1-LiitliiPiJitS,/-fi*ftor/
Multiplexers with 3-5JI.I, OU'tRlIt~'1
AC ELECTRICAL CHARACTERISTICS
Characteristic
tf~2 ns). AHCT257
KS54AHcf"
KS74AHCT
T. =25°C
T. = -40°C to +85°C T. = -55°C to+.125°C
Vcc=5.0V
Vcc=5.0V%10%
Vcc=5.0V% 1~%
Conditions t
Symbol
(Input t r •
Typ
14 . ,.
20
tpHL
CL=50pF
CL=150pF
7
10
12
17
14"
20
tPLH
CL=50pF
CL=150pF
12
15
20
25
30
CL=50pF
CL=150pF
12
15
20
25
?1.
~q
CL=50pF
CL=150pF
13
16
18
23
22
28,
CL=50pF
CL=150pF
13
16
18
23
22
28
Output Disable Time.
tPZH
RL =1 kO
tPZL
tPHZ
f---------
tpLZ
Input Capacitance
RL =1 kO
CL=50pF
-
Output Capacitance
COUT
Power Dissipation
Capacitance *
Cpo
Output Disabled
'.
"
ns
24
"
"
.
ns
12
15
2;2,"~ .
15
22
',j
"
ns
12
5
CIN
Unit
"',ax .
12
17-
tpHL
G to any Y
Min
7
10
Eropagation Delay.
AlB to any Y
Output Enable Time.
G to any Y
Max
CL=50pF
CL =150pF
tPLH
Propagation Delay.
A or B to any Y
Min
ns
',"
pF
pF
10
pF,,;
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
AC ELECTRICAL CHARACTERISTICS
Condltions t
Symbol
Characteristic
(Input tr • tf~2 ns). AHCT258
KS74AHCT
KS54AHCT
T. =25°C
T. = -40°C to +85°C T. = -55°C to :+:125°C
Vcc=5.0V
Vcc=5.0V%10%
Vcc=5.0V% 10%
Typ
Qutput Enable Time.
G to any Y
Input Capacitance
tpHL
CL=50pF
CL=150pF
6
9
8
13
8
13
tpLH
CL=50pF
CL=150pF
14
17
23
28
tpHL
CL=50pF
CL=150pF
14
17
23
,28
·28
34
CL=50pF
CL=150pF
11
14
18
23
~d
28
CL=50pF
CL=150pF
11
14
18
23
22
28
tPZH
RL = 1 kO
-
tpHZ
f---------
tpLZ
Power Dissipation
Capacitance *
COUT
,
ns
14
c',
1~
28
34'
ns
,",
;,:
"
;,
ns
13
18
22
13
18
22
5
pF
Output Disabled
10
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC fin.
t For AC switching test circuits and timing waveforms see section 2.
cSiSAMSUNG
ns
pF
Cpo
'
14 '
19
RL =1kO
CL=50pF
2
• • Electronics
Unli
Max
6
9
CIN
Output Capacitance
Min
CL=50pF
CL=150pF
tPZL
Output Disable Time.
G to any Y
Max
tpLH
Propagation Delay.
A or B to any Y
Eropagation Delay.
AlB to any Y
Min
I
259
KS54AHCT
KS14AHCT ,.;, '.
8-Bit Addressable Latches
FEATURES
DESCRIPTION
• 8-Blt paraJlel-out storage register performs serial-toparallel conversion with storage
• Asynchronous parallel clear
• Active high decoder
• Enable/Disable input simplifies expansion
• Expandable for N-blt applications
• Four distinct functional modes
• Function, pj,n-out, speed and drive compatibility with
54174ALS logic family
• Low power .consumption characteristic of CMOS
'. High-Drlve-Current outputs:
10l =8 mA @ VOL =0.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over Industrial and
military temperature ranges:
KS74AHCT: -: 40°C to + 85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
T~e
so
Vee
S1
CLR
S2
G
00
01
07
GND
L
H
L
H
Output of
Addressed
Latch
Each
Other
Output
0
alo
0
aiO
alo
L
In the clear mode, all outputs are low and unaffected by
the address and data inputs.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
L
L
Select Inputs '
Function
Addressable Latch
Memory
a-Une Demultiplexer
Clear
D - the level at the data input.
010 - the level of 010 (i = 0, 1, ... 7, 88 appropriate) before the
indicated steady-state input conditions were established .
..'- c8SAMSUNG
Electronics
In the demultiplexing mode, addressed outputs will follow
the state of the 0 input and all other outputs will remain low.
LATCH SELECTION TABLE
FUNCTION TABLE
Ci
In the memory mode, all latches remain in their previous
state and ate unaffected by the data' of address inputs.
06
05
04
03
H
H
L
L
In the addressable latch mode, data on the data input (D)
is written into the addressed latch. In this mode, data will
be written into the addressed latch with all non-addressed
latches remaining in their previous states.
0
Q2
CLR
The '259 has four distinct modes of operation that are
selected via the clear (CLRf and enable (G) inputs: 1) addressable latch; 2) memory; 3) active-high eight-channel
demultiplexer; and 4) clear.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
Inputs
'259 is a high-speed addressable latch deSigned for
general purpose storage applications in digital systems. It
can be used for implementing working registers, serialholding registers and active-high decoders or
, demultiplexers.
S2
L
L
L
L
H
H
H
H
Latch
S1
SO
Addressed
L
L
H
L
H
L
H
L
H
0
L
H
H
L
L
H
H
1
2
3
4
5
6
7
,264.
KS54AblCT259
KS74·AHCT'
8-Sit Addressable Latches
LOGIC DIAGRAM
o
(13)
00
01
02
03
04
as
06
I
07
Absolute :Maximum Ratings*
Supply Voltage Range Vcc, .. .
-0.5V to + 7V
DC Input Diode Current, hK
(V, < -0.5V or V, > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V).
±35 mA
Continuous Current Through
Vcc or GND pins.
±125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. kong exposure to these conditions may affect device relfability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
265
, KS54AHC:J:~;259
KS744HCT . ,.~ \;.".
8-Bit Addressable, Latches
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V± 1 0% Unless Otherwise Specified)
T.=25°C
KS74AHCT
KS54AHCT
T. = -40°C to +85°C T. = -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
hipot Voltage
VIH
2.0
2.0
2.0
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Ou.tput Voltage
VOH
VIN=VIH or VIL
10=-20/-lA
10=-4mA
Vcc -0.1
3.84
Vcc :-0.1'
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL'
10 = 20/-lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
JAA
8.0
80.0
160.0
JAA
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
~Icc
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
10uT=OJAA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
IOUT=OJAA
AC ELECTRICAL CHARACTERISTICS
Symbol
Characteristic
Conditions t
Propagation Delay,
Data to any Q
-
Propagation Delay,
Address to any Q
-
T.=25°C
Vee=5_0V
Propagation Delay,
Q
-
G to any
Pulse Width
I CLR Low
I GLow
KS74AHCT
T. = -40°C to +85°C
Vee =5.0V:t 10%
Min
Max
KS54AHCT
T. = -55°C to +125°C
Vce=5.0V:t 10%
Min
9
15
18
tPLH
12
19
23
tpHL
12
19
23
CL=50pF
13
22
27
tpHL
13
22
27
tpLH
12
20
24
tpHL
12
20
24
tw
6
10
10
9
15
20
Unit
Max
tpHL
tpLH
,;:V
(Input tr , tf"2 ns), AHCT259
Typ
Propagation Delay
CLR to any Q
' .
ns
ns
ns
ns
ns
Setup Time
Data or Address before
Gt
tsu
10
15
:20
ns
Hold Time,
Data or Address before
Gt
th
-3
0
0
ns
Input Capacitance
CIN
5
pF
Power DisSipation Capacitance *
Cpo
80
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcd fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
266
KS54AHCT
KS74AHCT
266
Quad Exclusive-NOR Gates
with Open-Drain Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
.
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40~C to +85°C
KS54AHCT: -55°C to +125°Q
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent exclusive-NOR
gates with open-drain outputs. Using a suitable pull-up
resistor, these outputs may be connected to other opendrain outputs to implement wired-AND functions.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive .capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power .Ievels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
I
(3,4,10,11)
1A
Vee
1B
4B
A (1,5,8,12).
1Y
4A
B
2Y
4Y
2A
3Y
2B
3B
GND
3A
(2,6,9,13)
)I:>--;
~Y
FUNCTION TABLE
Inputs
Output
A
B
y
L
L
L
H
H
H
H
L
L
L
H
H
c8SAMSUNG
Electronics
267
KS54AHCT
KS74AHCT
266
Quad Exclusive-NOR Gates
with Open-Drain Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vcc, ... . .. . -0.5V to + 7V
DC Input Diode Current, hK
(VI < -O.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 101<
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) . . . . . .
±35 mA
Continuous Current Through
Vcc or GND pins . . . . . . . . . . . . . . .. ± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oCfrom 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . .
4.5V to 5.5V
DC Input & Output Voltages *, VIN, Your . . OV to Vcc
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf ...... .
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logiC
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V± 10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20l-'A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
I-'A
Maximum Output
Leakage Current
loz
VIN=VIH or VIL
Vour=Vcc
±0.5
±5.0
±10.0
I-'A
Maximum Quiescent
Current
Icc
2.0
20.0
40.0
I-'A
3.0
mA
~_
Additional Worst
Case Supply
Current
Dolcc
0
VIN=VCC or GND
10ur=OJ-lA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10ur=0l-'A
----
2.7
AC ELECTRICAL CHARACTERISTICS
Characteristic
Propagation Delay
(Input tr ,
-
2.9
tf~2 ns). AHCT266
KS74AHCT
KS54AHCT
Ta =25°C
Ta= -40°C to +85°C Ta =-55°Cto +125°C
t
Symbol Conditions Vcc=5.0V
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Min
Max
Min
Max
~
tpHL
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
CL=50pF
RL=1kO
19
29
35
11
18
22
5
pF
(per gate)
15
pF
ns
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
268
KS54AHCT
KS74AHCT
273
Octal 0-Type Flip-Flops with Clear
FEATURES
DESCRIPTION
• Eight positive-edge-triggered Ootype flip-flops with
single-rail outputs
• Buffered common clock and asynchronous clear
• Function, pin-out, speed and drive compatibility with
54/74AlS logic family
• low power consumption characteristic of CMOS
• High-Orive-Current outputs:
10l = 24mA @ Val = O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.. 5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices are high-speed octal registers. They consist of eight positive-edge-triggered Ootype flip-flops with
individual 0 inputs and outputs. All flip flops are loaded
and cleared simultaneously by the common buffered clock
(ClK) and clear (ClR) inputs.
a
Information at the 0 inputs meeting the setup time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse. When the clock input is at
either the high or low level, the 0 input Signal has no effect at the output.
These devices provide speeds and drive capability
equivalent to their AlSTTl counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
I
FUNCTION TABLE
(Each Flip-Flop)
ClR
Vee
10
10
80
Inputs
80
70
70
20
20
30
3D
40
40
60
60
SO
Output
ClR
ClK
0
Q
l
H
H
H
X
t
t
X
l
H
l
H
l
X
l
00
SO
GNO
ClK
LOGIC DIAGRAM
10
(11)
3D
20
(3)
40
(7)
(4)
60
SO
(13)
(8)
80
70
(14)
(18)
(17)
ClK
(2)
10
c8SAMSUNG
Electronics
(S)
20
(6)
30
(9)
40
(1S)
(12)
SO
60
(16)
70
(19)
80.
269
273
"
KS54AHCT
KS74AHCT··
Octal D-Type Flip-Flops .with Clear'
Absolute Maximum Ratings*
Supply Voltage Range Vee, " " ' " -0.5V to +7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vce +0.5V), , , , , ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vce +0.5V) , , . , ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vce +0.5V) , , , , , . , , , ±70 mA
Continuous Current Through
Vee or GND pins , , , , .... , .... , " ± 250 mA
Storage Temperature Range, Tslg . . . - 65 ° C to + 150 ° C
Power DisSipation Per Package, Pdt ..... , 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . , . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +S'5°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ..... '.' . . Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
* Absolute Maximum Ratings are those values' beyond
which permanent'damage to the device may occur.
These are stress ratings only and functional operation '
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum LOW-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN = VIH or VIL
lo=-20",A
lo:<::::-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20",A
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
,0.33
0.5
0.1
0.4
V
Maximum Input
Current
lIN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
'r---'
80.0
,160.0
,.,A
2.9
3.0
mA
Additional Worst
Case Supply
Current
Alec
VIN=Vee or GND
louT=O,.,A '.
per input pin
VI=2.4V,
other Inputs:
at Vee or GND
IOUT=O,.,A
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
2.7
270
KS54AHCT
KS74AHCT
273
Octal D-Type
AC ELECTRICAL CHARACTERISTICS
Characteristic
Maximum Clock Frequency
Propagation Delay.
ClK to any
a
Propagation Delay.
CLR to any
a
Pulse Width
ClR low
Symbol
Conditions t
f max
CL=50pF
Setup Time
before ClKt
Data
Min
35
tpLH
CL=50pF
CL=150pF
tpHL
CL=50pF
CL=150pF
tPHL
CL=50pF
CL=150pF
tsu
Clear inactive
State
Hold time. Data after ClKt
KS74AHCT
KS54AHCT
T. =25°C
T. = -40°C to +85°C T.= -55°C to +125°C
Vcc=5.0V
Vcc=5.0V:1: 10%
Vcc=5.0V:1:10%
50
13
13
tw
th
with. Clear
(Input tr • tf~2 ns). AHCT273
Typ
ClK High or low
F/iP-Fi;,ps
Max
Min
Max
30
MHz
f---
18.5
20
19
34
13
13
17.5
20
19
34
13
14
18.5
23
28
22
8
14
17
8
14
17
6
10
10
9
15
15
-3
0
0
Unit
ns
ns
ns
ns
ns
-~
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per package)
5
pF
150
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
271
I
4'1)·0
KS54AHCT
KS74AHCT ..4t,o.
I
9-Bit Parity GeneratorstCheckers
FEATURES
DESCRIPTION
• Generates Odd or Even Parity for Nine Data Lines
• Cascadable for N-Bits Parity
• Can be used to Upgrade Existil"!g Systems using MSI
Parity Circuits
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
(IOL 24 mA @ VOL O.SV) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.SV to S.SV
• Characterized for operation. over Industrial and
military temperature ranges:
KS74HCTLS: -40°C to +8S o C
KSS4HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These universal, nine-bit ~ity generators/checkers feature
odd and even outputs to facilitate operation of either odd
or even parity application. The word-length capability is easily expanded by cascading.
=
=
The devices can be used to upgrade the performance of
most systems utilizing the '180 parity generator/checker,
Although the '280 is implemented without expander inputs,
the corresponding function is provided by the availability
of an input at pin 4 and the absence of any internal connection at pin 3. This permits the '280 to be substituted
for the' 180 in existing deSigns to produce an identical function even if the devices are mixed. with existing '180's.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOs and CMOS devices
without any external components.
All inputs and outputs are protected from .damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
PIN CONFIGURATION
G
Vee
H
F
NC
E
0
1: EVEN
C
1:000
B
GNO
A
c8SAMSUNG
Electronics
NUMBER OF INPUTS A
THRU I THAT ARE HIGH
0,2,4,6,8
1,3,5,7,9
OUTPUTS
~
EVEN
~ODD
H
L
L
H
272
KS54AHCT
KS74AHCT
280
.
9-Bit Parity Generators/Checkers
LOGIC DIAGRAM
A
B
c
(81
(91
(101
I
EVEN
0
E
(111
(121
(131
I
000
(11
G
H
(21
(41
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±70 mA
Continuous Current Through
Vee or GND pins. . . . . . . . . .
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
.
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee ............. 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vce
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
273
I
·KS54AHCT
KS74AHCT
280
9-Bit Parity Generators/Checkers
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
T. =25°C
KS74AHCT
KS54AHCT
T.= -40°C to +85°C T.=-55°Cto +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
M~imum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=- 2OI-'A
lo=-6mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=201-'A
lo=12mA
lo=2.4mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
I-'A
8.0
80.0
160.0
I-'A
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
Alcc
Vcc Vcc -0.1
3.98
4.2
0
VIN=VCC or GND
louT=OI-'A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
lOUT = Ol-'A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input tr , tf:E;;2 ns), AHCT280
T.=25°C
Vcc=5.0V
Typ
Propagation Delay,
Any input to I Even
Propagation Delay,
Any input to I Odd
KS74AHCT
T.= -40:C to +85°C
Vcc=5.0V:t10%
Min
Min
CL=50pF
CL=150pF
12
15
21
25
24
30
tpHL
CL=50pF
CL=150pF
12
15
21
25
24
30
tPLH
CL=50pF
CL=150pF
13
16
22
27
26
32
tpHL
CL=50pF
CL=150pF
13
16
22
27
26
32
CIN
Power Dissipation Capacitance *
Cpo
5
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
Unit
Max
tPLH
Input Capacitance
c8SAMSUNG
Electronics
Max
KS54AHCT
T. = -55°C to +125°C
Vcc=5.0V:t 10%
ns
ns
pF
pF
KS54AHCT
KS74AHCT
299
8-Bit Universal Shift/Storage Registers
with 3-State Outputs
FEATURES
DESCRIPTION
• Multiplexed 110 ports provides improved bit density
• Four modes of operation: hold (store), shift right, shift
left, and load data
• Operates with outputs enabled or at high impedance
• Can be cascaded for N-bit word lengths
• Direct overriding clear
• Application:
Stacked or push-down registers, buffer storage, and
accumulator· registers
These eight-bit universal registers feature multiplexed I/O
ports to achieve full eight·bit data handling. Two functionselect inputs and two output·control inputs can be used
to choose the modes of operation listed in the function
table.
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
Low power consumption characteristic of CMOS
3-State outputs with drive current
(lOL 24 rnA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -.40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages·
(Available Tape & Reel), standard DIPs.
=
=
Synchronous parallel loading is accomplished by taking both
function·select lines SO and S1 high. This places the threestate outputs in a high-impedance state and permits data
that is applied on the 1/0 ports to be clocked into the
register. Reading out of the register can be accomplished
while the outputs are enabled in any mode. Clearing oc·
curs asynchronously when CLR is low. Pulling either of the
output controls, G1 or G2, high disables the outputs but
this has no effect on clearing, shifting, or storage of data
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
so
Vee
<31
S1
132
Sl
G/OG
O~
E/OE
H/OH
C/O e
F/O F
AJO A
0/0 0
O~
BlOB
ClR
ClK
GND
SR
c8SAMSUNG
Electronics
275
I
KS54AHCT
KS74AHCT
299
8-Bit Universal Shift/Storage Registers
with 3-State Outputs
LOGIC DIAGRAM
(18) SHIFT lEFT
rH-H---'--- SERIAL INPUT
SERIAL INPUT
ClK -----'-(1-'-2)--Do+.....---t---tH4...--t--ttt--'l
(13)
(7)
'AlO.
SlOB
1/0 PORTS NOT SHOWN:
(6) C/Oe (5) E/O E
(14) D/QD (15) F/O F
(4)
(16)
OIOG
H/OH
FUNCTION TABLE
110 Ports
Outputs
A/QA B/Qs C/Qc D/QD E/QE F/QF G/Qo H/QH
QA' QH'
Inputs
51 50
Output
Control
G1 G2
Mode
ClR
ClK
5l 5R
Clear
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
X
X
X
X
X
X
X
X
X
L
L
X
Hold
H
H
L
X
L
X
L
L
L
L
X
L
X
X
X
X
Shift Right
H
H
L
L
H
H
L
L
L
L
t
t
X
X
Shift Left
H
H
H
H
L
L
L
L
L
L
t
t
Load
H
H
H
X
X
t
L
l
X
L
l
X
L
L
X
l
l
X
L
l
X
OAO
OSO
OCO
ODO
OEO
OFO
OGO
OHO
OAO OHO
OAO
OSO
OCO
ODO
OEO
OFO
OGO
OHO
OAO OHO
H
L
H
L
OAn
OSn
OCn
ODn
OEn
OFn
OGn
OAn
OSn
OCn
ODn
OEn
OFn
OGn
H
L
OGn
H
L
X
X
OSn
OSn
OCn
OCn
ODn
ODn
OEn
OEOn
OFn
OFn
OGn
OGn
OHn
OHn
H
L
OSn
OSn
H
L
X
X
a
b
c
d
e
f
g
h
a
h
L
l
X
L
L
X
l
L
L
l
L
L
OGn
When one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however,
sequential operation or clearing of the register is not affected.
c8SAMSUNG
Electronics
276
KS54AHCT
KS74AHCT
299
8-Bit Universal Shift/Storage Registers
with 3-State Outputs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oCfrom 65°C to 85°C
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
... 1±70 mA
Continuous Current Through
Vee or GND pins. . . . . . . . . . . . .
'±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt . . . .. 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vce
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf ....
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may Qccur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta :;;:25°C
Typ
KS74AHCT
KS54AHCT
Ta =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum
High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum
Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
Vee -0.1
3.84
3.7
Minimum HighLevel Output
Voltage
Miximum
Low-Level
Output Voltage
Maximum Input
Current
VOH
VOL
VIN=VIH or VIL
10=-20/AA
Vee Vee -0.1
Q'A and Q'H outputs:
10= -4mA
4.2
3.98
QA thru QH outputs:
10= -6mA
4.2
3.84
VIN=VIH or VIL
10= 2O/AA
Q'A and Q'H outputs:
10=4mA
10=8mA
QA thru QH outputs:
lo=12mA
lo=24mA
0
V
3.7
0.1
0.1
0.1
0.26
0.39
0.33
0.5
0.4
0.26
0.39
0.33
0.5
0.4
V
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
/AA
Maximum 3-State
Leakage Current
loz
Output Enable = VIN
VouT=Vee or GND
±0.5
±5.0
±10.0
/AA
Maximum
Quiescent
Supply Current
Icc
VIN=Vee or GND
10lJT=0/AA
8.0
80.0
160.0
/AA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~ICe
c8SAMSUNG
Electronics
277
II
KS54AHCT
KS74AHCT
29·9
8-EJit Universal Shift/Storage RegIsters
with 3-State Outputs .
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Input tr , t,<2 ns), AHCT299
Condltlonst
KS74AHCT
KS54AHCT
T.=2SOC
T.= -40°C to +8SoC T.= -SS°(: to +12SoC
Unit
Vee = S.OV
Vee=5.0V:10%
Vec=5.0V: 10%
Typ
MIl"!
Maximum Clock Frequency
fmax
50
30
Propagation Delay,
ClK to O'A or O'H
tpLH
f---
10
17
20
10
17
20
Propagation Delay,
ClR to O'A or O'H
tPHL
13
22
26
Propagation Delay,
ClK to OA thru OH
tpHL
QutP!!t Enable Time,
G1, G2, to OA thru OH
Pulse Width
ClK High or low
16
21
19
25
tpHL
CL=50pF
CL=150pF
10
13
16
21
19
25
tPHL
CL=50pF
CL=150pF
13
16
22
27
26
31
CL=50pF
CL=150pF
11
14
19
24
23
29
CL=50pF
CL=150pF
11
14
19
24
23
29
11
18
22
11
18
22
tPZH
I---
~
tpLZ
RL=1 kO
RL=1kO
CL=50pF
9
15
20
5
8
10
SO and S1
12
20
10
8
13
15
8
13
15
8
13
15
0
0
0
Setup time
before ClKt low-Level Inputs
tw
tsu
CLR Inactive
Hold Time
after CLKt
SO and S1
th
All Inputs
Input Capacitance
MHz
10
13
ClR low
High-level Inputs
Max
25
CL=50pF
CL=150pF
tPZL
Output Disable Time,
G1, G2 to OA thru OH
Min
tpLH
1---.
Propagation Delay,
£lR to OA thru OH
CL=50pF
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
CIN
Output Capacitance
COUT
Power Dissipation Capacitance *
Cpo
Output Disabled
5
pF
10
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
=8~~SUNG
pF
fin.
278
KS54AHCT
KS74AHCT
322
8-Bit Shift Registers
with Sign Extend
FEATURES
DESCRIPTION
• Multiplexed inputs/outputs provide improved bit
density
• Sign extend function
• Direct overriding clear
• 3 state outputs drive bus lines directly
• Function pin-out, speed and drive compatibility with
54/74 ALS logic family
• Low power consumption characteristic of CMOS
• High drive current output
(loL=24mA @ VOL=O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices.
• Wide Operating voltage range: 4.5V to S.SV
~ Characterized for operation over industrial and
military temperature range:
KS74AHCT: -40°C to +85°
KS54AHCT: - 55°C to + 125°
• Package options include plastic "small outline"
packages, standard plastic and ceramic 30D-mil DIPs
These a bit Shift registers have multiplexed input/output
data ports to accomplish full a·bit data handling in a single
20'pin package. Serial data may enter the shift·right register
through either Do or 01 input as selected by the data
select pin. A serial output is also provided. Synchronous
parallel loading is ach'ieved by taking the register enable
and the SIP inputs low. This places the three-state input/output ports in the data input mode. Data are entered
on the low-to-high clock transition. The data extend function repeats the sign in the QA flip flop during shifting. An
overriding clear input clears the internal register when taken
low whether the outputs are enabled or off. The output
enable does not affect synchronous operation of the
register.
I
PIN CONFIGURATION
Register
enable
SIP
Do
Vee
Data select (OS)
Sigh extend (SE)
AlO A
0,
CIOe
BIOa
E/OE
0100
G/OG
Output
enable
clear
FIOF
H/OH
OH'
GNO
:8 ~!!"SUNG
279
KS54AHCT
KS74AHCT
322,
8-BitShift Registers
with Sign Extend
FUNCTION TABLE
INPUT/OUT~~~____
INPUT
OPERATION
Clear
Register
enable
SIP
Sign
extend
Data
select
Output
enable
Clock
X
X
X
X
L
L
X
X
L
L
L
L
L
L
A/aA
BlaB
Clear
Hold
H
H
X
X
X
L
X
QAO
QBO
Qco
Shift Right
H
H
L
L
H
H
H
H
L
H
L
L
t
t
Do
01
QAn
QAn
QBn
QBn
Sign Extend
H
L
H
L
X
L
t
QAn
QAn
QBn
Load
H
L
L
X
X
X
t
a
b
c
~
Output
a
i
H
X
! ____
C/ac ... H/aH'
L
L
X
H
j
H
L !
L
L i
L
-QHo-1-o:;--
-g:-l
QGo
h
~]
2J
'
h
When the output enable is high, the eight input/output terminals are disabled to the high-impedance state: however,
sequential operation or clearing of the register is not affected. If both the register enable input and the SIP input are
low while the clear input is low, the register is cleared while the eight input/output terminals are disabled to the highimpedance state.
H= high level (steady state)
L= low level (steady state)
X= irrelevant (any inputs, including transitions)
t = transition from low to high level
QAo ... QHo= the level of QA through QH, respectively, before the indicated steady-state conditions were established.
QAn ... QHn= the level of QA through QH, respectively, before the most recent t transition of the clock.
Do. 01 = the level of steady-state inputs at inputs Do and 01 respectively
a... h= the level of steady-state inputs at input A through H respectively.
LOGIC DIAGRAM
REGISTE.R (1)
ENABLE
G
,t
OUTPUT (8)
ENABLE :....:...--------<1......J
DE
c8SAMSUNG
~Iectronics .
280
322
8-BltShilt Registers
with Sign Extend
KS54AHCT .
KS74AH.CT
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Ceramic Package (J): -12mW/oC from 100°C to 125°C
Supply Voltage Range Vee, ....... -0.5V to +7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 125 mA
Storage T~mperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommend8c:t Operating Conditions
Supply Voltage, Vee . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT . .
to Vee
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
ov
• Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur
These are stress ratings only and functional operation
of the device at or beyond them is not im~ied. Long ex-posure to these conditions may affect device reliability
DC ELECTRICAL CHARACTERISTICS
Characteristic
T.=25°C
Symbol Test Conditions
KS74AHCT
KS54AHCT
T.= -40°C to +85°C T.- -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20,..A
lo=-4mA
Vee -0.1·
3.84
Veo -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2OIolA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±1.0
lolA
-
Maximum Input
Current
I
Vee Vee -0.1
3.98
4.2
0
liN
VIN=VCC or GND
±0.1
±1.0
Maximum Quiescent
Supply Current
lee
VIN=VCC or GND
louT=O,..A
8.0
80.0
Additional Worst
Case Supply
Current
per input in
VI=2.4V
~Icc other Inputs:
at Vee or GND
IOUT=O,..A
-.
c8SAMSUNG
Electronics
I
(Vce=5V± 1 0% Unless Otherwise Specified)
160.0
,..A
--------- - -
_._--
.'-"'-
I
i
2.7
2.9
!
mAl
j
j
281
8·Blt SfJlhRtigISf.,.
wlth . Slgn Extend
AC ELECTRICAL CHARACTERISTICS
, ,
Symbol
Charact.'at'c
Condltlon,t
(Input tr, tf<2 ns), AHCT322
KS74AHCT
. KS54AHCT
T._25·C
T.- -40·C to +85·C T.-,-55·C to +125·C
Unit
Vcc-S.ov
Vcc-S.OV:t::10%
Vcc-S.OV:t:: 10%
Typ
Min
f max
50
30
M8ximum Propagation
Delay, Clock to OH
~
12
20
24
12
20
24
Maximum Propagation
Delay, Clear to OH'
tpHL
13
21
25
Maximum Propagation
Delay, Clock to OA-OH
~
Maximum Clock Frequency
tPLH
Propagation Delay
Clear to OA-OH
."
12
20
24
20
24
tPHL
13
21
25
13
21
25
13
21
25
~
tP'LZ
Clock Pulse Width
Max
25
12
tPZL
Output Disable Time
Min
tPLH
~
Output Enable Time
CL=50pF
Max
IHigh
ILow
RL=1kO
CL=50pF
11
18
21
11
18
21
tw
7
12
15
tw
7
12
15
Clear Pulse Width. Low
tw
7
12
15
Data Set up Time
ts
8
15
20
Select Set up Time
ts
8
15
20
Data Hold Time
th
-3
0
0
Select Hold Time
th
5
8
10
Recovery Time
tree
10
17
20
Maximum Input Capacitance
Cjn
5
Power Dissipation Capacitance
Cpo
Hio
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc1 f
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
ns
ns
pF
pF
+ Icc Vee.
282
KS54AHCT
KS74AHCT
352
Dual 4-Line to 1-Line Data
Selectors/Multiplexers
FEATURES
DESCRIPTION
•
•
•
•
Each of these data selectors/multiplexers contains Inverters
and drivers to supply fully complementary binary decoding
data selection to the AND·OR·invert gates. Separate strobe
inputs (<3) are provided for each of the two four·line
sections.
•
•
•
•
•
•
•
Inverting Version of '153
Permits Multiplexing from N Lines to 1 Line
Performs Parallel-ta-Serial Conversion
Strobe (Enable) Line Provided for Cascading
(N Lines to n Lines)
Function. pin-out, spaed and drive compatibility with
54/74ALS logic family
Low power consumption characteristic of CMOS
High drive current outputs
(IOL= 24 mA @ VOL = O.5V) for direct bus interface
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS,and CMOS devices
without any external components.
All inputs an(j outputs are protected from damage due to
static discharge by internal diode clamps toVcc and
ground.
I
LOGIC DIAGRAM
PIN CONFIGU.RATION
1G(1)
1<3
Vee
B
---t-r-t-t~
2G
1C3
A
1C2
2C3
1C1
2C2
1CO
:::..l::!-::
2C1
1Y
DATA
1C3-~(3~)-----t---t---t--t--"',
2Y
SELECT [
FUNCTION TABLE
SELECT
INPUTS
-B
A
X
X
L
L
L
L
L
L
H
H
L
L
H
H
H
H
H
H
STROBE
OUTPUT
CO C1 C2 C3
G
y
H
H
L
L
L
L
L
L
L
L
H
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
B (2)
A P4 )
DATA INPUTS
X
1Y
---:-+-+-+H-4--'
1 C2.:.(4:..:.)_ _ _
1
2CO
GND
1
DATA
21
- - :- -:-1=t= Ft=:f~
::::..!..:::..:::.:...:
2Y
2C3 (13)
L
H
L
H
L
H
L
Select inputs A and B are common to both sections.
=8SAMSUNG
Electronics
283
KS54AH'CT
KS74AHCT
35,/2
'
DUsl4-Line to 1-Line·Data
Selectors/Multiplexers
Absolute Maximum Ratings*
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or V, > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) .... '..... ±70 mA
Continuous Current Through
Vcc or GND pins ................ ±250 mA
. Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc .............. 4.5V to 5.5V
DC Input & Output Voltages·, V'N, VOUT .. OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V±10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
I
Minimum High-Level
Input Voltage
V,H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V,L
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
V'N=V'H or V,L
10=-20IlA
10=-6mA
Vcc -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
V'N=V'H or V,L
10=20",A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximul]1 Input
Current
hN
V'N=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.6.lcc
V'N=Vec or GND
10uT=Of.lA
per input pin
V,=2.4V
other Inputs:
at Vec or GND
10uT=0",A
c8SAMSUNG
Electronics
Vcc Vcc -0.1
4.2
3.98
0
284
KS54AHCT
KS74AHCT
352
Dual 4-Line to 1-Line Data
Selectors/Multiplexers
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr •
tf~2 ns). AHCT352
KS74AHCT
KS54AHCT
T. =25 DC
T.= _40DC to +85°C T.=-55°Cto +125°C
Vcc=5.0V
Vcc=5.0V%10%
Vcc=5.0V% 10%
Symbol
Condltlons t
tpLH
CL=50pF
CL=150pF
14
17
23
28
28
34
tpHL
CL=50pF
CL =150pF
14
17
23
28
28
34
tpLH
CL=50pF
CL=150pF
11
14
18
23
21
27
tpHL
CL=50pF
CL=150pF
11
14
18
23
21
27
tpLH
CL=50pF
CL=150pF
12
15
20
25
24
30
tPHL
CL=50pF
CL=150pF
12
15
20
25
24
30
Typ
Propagation Delay.
AorBtoY
Propagation Delay.
Data (Any C) to Y
~ropagation
Delay.
G to Y
Input Capacitance
Power Dissipation Capacitance *
C'N
Cpo
5
* Cpo determines the no· load dynamic power dissipation: Po=Cpo Vee 2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
Min
Max
Min
Unit
Max
ns
ns
ns
pF
pF
I
fin.
285
.
:'-
,;
.
.
:",
'
.
.
'
\
Dual 1-of-4 Data'Selectors/Multiplexers
with 3..State Outputs
KS54AHCT353
KS74AHCT
FEATURES
DESCRIPTION
•
•
•
•
Each of these data selectors/multiplexers Contains inverters
and drivers to supply, full binary decoding data selection
to the AND~bR~invert gates. Separate strobe inputs (0) are
provided for each of the two four-line sections.
Inverting Version of '253
Permits Multiplexing from N lines to 1 line
Performs ParaJlel-to-Serlal Conversi9n
Function, pin-ol.it, speed and drive compatibility with
54174ALS logic family
• Low power consumption c,haracteristic of CMOS
• 3-State outputs with high drive current
(IOL 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide, operating voltage' range: 4.SV toS.5V
• Characterized for operation over industrial and
military temperature rar'lges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C ,to + 125°C
• Package options include "small outline" packages
'(Available Tape & Reel), standard DIPs.
=
The three-state outputs can interface with and, drive data
lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state) the lowimpedance of the single enabled output will drive the bus
line to a high or low logic leveL Each output has its own
strobe (G), The output is disabled when its strobe is high,
=
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outplits are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground. ,
PIN CONFIGURATION
1(3
Vee
B
213
1C3
A
1C2
2C3
1C1
2C2
1CO
2C1
1Y
2CO
GND
LOGIC DIAGRAM
STROBE
ENABLE
2Y
DATA 1
- (1)
1G
j::.::..:.:-----,--+--+-+-l--I....-J
1Y
1C3,.l;(3::!.)-----+--+-+-I~-L.J
FUNCTION TABLE
B (2)
SELECT
INPUTS
SELECT {
DATA INPUTS
OUTPUT
CONTROL
OUTPUT
CO C1 C2 C3
G
y
H
'L
L
L
L
L
L
L
L
H
l..
H
L
H
L
H
L
B
A
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
I<
L
H
X
X
X
X
L
H
X
X
X
X
A (14)
Z
DATA
2'f: : ~,)
2C2!-'-"'-----'i=::t==t:==I
2Y
2C31~(~13~)-----tjt===~~
STROBE _(15}
ENABLE 2G
Select inputs A and B arecomrrion to both sections,
=82!'1SUNG
286
KS54AHCT
KS74AHCT
353
Dual 1-of-4 Data SeleQldjs/Multiplexers
with 3-State Outputs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee ........ -O.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
,(-0.5V < Vo < Vee +0.5V) . . . .
±70 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . . .
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ..... . 500 mW
Recommended Operating Conditions
Supply Voltage, Vce . . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, Your .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times. tr , tf
• AbSolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Ta =25°C
Symbol Test Conditions
-
(Vce=5V± 10% Unless Otherwise Specified)
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/.lA
10= -6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum 'Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vee or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
~---
-
Additional Worst
Case Supply
Current
~Iee
VIN=Vee or GND
10ur=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=0",A
c8SAMSUNG
FI"'~trnni~J::
Vee Vee -0.1
4.2
3.98
0
287
I
. KS54AHCT
KS74AHCT
3,6·-3
Dual 1- 01-4 DatIJSfJ/ect~,IMultiplexers
with 3-8tate Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Condltlons t
Symbol
(Input tr , tf~2 ns), AHCT353
KS74AHCT
KS54AHCT
T. =2S·C
T. = -40°C to +8SOC .T.=-SSOCto +12S0C
Unit
Ycc-S.OY
Ycc=S.OY:10%
Ycc=S.OY: 10%
Typ
Propagation Delay,
AorBtoanyY
Propagation Delay,
Data (Any C) to Any Y
Min
Max
tpLH
24
29
28
34
tpHL
CL=50pF
CL=150pF
14
17
24
29
28
34
tpLI:i
CL=50pF
CL=150pF
10
13
18
23
21
27
tpHL
CL=50pF
CL=150pF
10
13
18
23
21
27
10
13
16
21
10
13
16
21
19
25
. ,19
25
CL=50pF
tPZH
CL =150pF
RL=1k'O
r---CL=50pF
tPZL
CL=150pF
Output Disable Time,
Y
r------
Input' Capacitance
Max
14
17
Output Enable Time,
G to Y
G to
Min
CL=50pF
CL=150pF
tpHZ
tpLZ
COUl
Power DisSipation
Capacitance *
Cpo
ns
ns
RL=1kO
CL=50pF
10
18
22
10
18
22
5
pF
Output Disabled
10
pF
CIN
Output Capacitance
ns
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
ns
pF
fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
288
KS54AHCT
KS74AHCT
3651366
3671368"
Hex Bus-Drivers with
3-State Outputs
FEATURES
DESCRIPTION
• Function, pln-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These high-speed Hex bus drivers are designed specifically
to improve both the performance and density of 3-state
memory address drivers, clock drivers, and bus oriented
receivers and transmitters.
=
=
The '365 and '366 have two output enables (<31 and (32)
NOR'ed together to control aI/ six gates. The '367 and
'368 have two output enables which are configured so that
one enable (<31) controls four gates and the other (<32) controls the remaining two gates. The '366 and '368 have inverting data paths. The '365 and '367 have noninverting
data paths.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without ariy external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLES
PIN CONFIGURATION
'365 and '366
<31
Vee
A1
<32
Y"1
A6
A2
Y6
Y2
A5
A3
Y5
Y3
A4
GND
Y4
Inputs
G1
'367 and '368
nputs
--------1---~
Y Outputs
G2 A '365
'366
L
L
H
L
L
L
H
L
H
H
L
X
X
H
X
X
Z
Z
Z
Y Outputs
---
l G1 & G2 i A '367 '368
z
!
L
ILL
H
I
~
I I
~ ~
~
I
LOGIC DIAGRAMS
'365
'366
'367
'368
Yl
Yl
Yl
Yl
Y2
Y2
Y2
Y2
Y3
Y3
Y3
Y3
Y4
Y4
Y4
Y4
Y5
Y6
Y5
Y5
Y6
Y6
Y5
Y6
G1
c8SAMSUNG
Electronics
289
II
KS54AHC'T,.3651366
KS74AHCT
Hex Bus-Drillers with
3-State Outputs
367/368
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or.vo > Vcc +0;5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) . . . . .
±70 rnA
Continuous Current Through
Vcc or GND pins .............. " ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , t, . . . . . . . . . Max 500 ns
• .Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
T8 =25°C
Symbol Test Conditions
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
Maximum Low-Level
Input Voltage
KS74AHCT
KS~4AHCT
T8= -40°C to +85°C T8= -55°C to +125°C Unit
2.0
V
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
2.0
VIH
0.8
VIL
2.0
0.8
,
Minimum High-Level
Output Voltage
VOH
V,N=VIH or V,L
lo=-20",A
lo=-6mA
Maximum Low-Level
Output Voltage
VOL
V,N = V,H or V,l
lo=20",A
lo=12mA
lo=24mA
Maximum Input
Current
hN
V,N=V!:e or' GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Le~ka~e Current
loz
Output Enable
=V,H
VouT=Vee or GND
±0.5 .
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Alce
V'N=Vce or GND
IOUT=O",A
per input pin
V,=2.4V
other Inputs:
at Vcc or GND
IOUT=O",A
=8SAMSUNG
Electronics
.
Vec Vcc -0.1
4.2
3.98
0
I
290
KS54AHCT
KS74AHCT
3651366
3671368
Hex Bus-Drivers with
3-State Outputs
AHCT365. AHCT366.
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input tr •
tf~2 ns). AHCT367. AHCT368
KS74AHCT
KS54AHCT
T. =2SOC
T.=-40°Cto +85°C T. = -55°C to + 125°C
Unit
Vcc=S.ov
Vcc=S.OV:t10%
Vcc=5.0V:t 10%
Typ
Min
Max
Min
Max
tPLH
CL= 50pF
CL =150pF
8
11
14
19
17
33
tpHL
CL= 50pF
CL =150pF
8
11
14
19
17
33
Output Enable Time.
G to Y
CL= 50pF
tPZH
CL=150pF
I - - - RL=1kO
CL= 50pF
tPZL
CL =150pF
14
17
23
28
28
34
14
17
23
28
28
34
Output Disable Time.
~
Propagation Delay.
A to Y.
G to Y
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance· (per driver)
tpLZ
Cpo
ns
RL=1kO
CL=50pF
15
20
22
15
20
22
5
pF
Output Disabled
10
pF
CIN
COUT
ns
G=Vcc
G=GND
5
• Cpo determines the no-load dynamic power dissipation: Po=CpO Vec
ns
pF
2
I
fin.
t For AC switching test circuits and timing waveforms see section 2.
.
c8SAMSUNG
Flp~trnni~~
291
KS54AHCT'
KS74AHCT
373
Octal D-TypeTransparent Latches
with 3-State Outputs
FEATURES
DESCRIPTION
• 8 latches il1 a single package
• Full parallel access for loading
• Function; pin-out, speed and drive compatibility with
54174ALSIogic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOl =24 mA @ VOL =O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KSS4AHCT: -55°C to +12SoC
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '373 consists of 8 high-speed O-type latches coupled to 3-state output buffers with high drive current capability. It can be used in implementing buffer registers, 1/0 ports,
bidirectional bus drivers and working registers.
5C
Vee
80
The output buffers are controlled by a common Signal (OC)
which places the outputs at a high-impedance state when
it is taken high. The OC signal does not affect the internal
operations of the latches. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
10
10
20
The latches are transparent: when the enable (E) is high,
the 0 outputs follow the data (0) inputs. When the enable
is low, the outputs latch at the levels that were set up at
the 0 inputs.
FUNCTION TABLE
80
(Each Latch)
70
20
70
30
3D
40
40
60
60
50
50
GNo
E
Inputs
Output
OC
E
D
Q
L
L
L
H
H
H
L
X
H
L
X
X
H
L
00
Z
LOGIC DIAGRAM
10
20
3D
40
50
60
70
80
10
20
30
40
50
60
70
c8SAMSUNG
Electronics
80
292
KS54AHCT
KS74AHCT
373
Octal O-Type Transparent Latches
with 3-State Outputs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, . . . . .. -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
........
± 250 mA
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Yoltages~, VIN, VOUT
OV to Vce
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
. ... Max 500 ns
Input Rise & F=all Times, t r , tf ..
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
Ta=25°C
Symbol ' Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
VIN=VIH or VIL
10=-20~A
10=-6mA
Vee Vee -0.1
4.2
3.98
VIN=VIH or VIL
lo=20~A
10=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
~A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
~A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
~A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Iee
VIN=Vee or GND
10uT=0~A
per input pin
V,=2.4V
other Inputs:
at Vee or GND
0
10uT=0~A
c8SAMSUNG
Electronics
293
II
Octal 0-Type Transparent Latches·
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
KS74AHCT
KS54AHCT
T.=25°C
T. = -40°C to +85°C T. -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V:t 10%
Vcc=5.0V:t 1,00/.0
=
Conditions t
Symbol
(Input tr , tf~2 ns), AHCT373
Typ
Propagation Delay,
D to Q
Propagation Delay,
Eto Q
Min
Max
tpLH
16
19
tpHL
Cl= 50pF
Cl =150pF
11
14
16
19
19
23
19
23
tplH
Cl= 50pF
Cl=150pF
14
17
23
28
27
33
tpHl
Cl= 50pF
Cl =150pF
14
17
23
28
27
33
12
15
20
25
24
30
20
25
24
30
13
18
22
13
18
22
Cl= 50pF
Cl=150pF
r----- Rl=l kO
tpHZ
r----- Rl=1kO
tpLZ
.
/
Cl= 50pF
Cl=150pF
tPZl
Output Disable Time,
OC to any Q
Max
11
14
tPZH
Output Enable Time,
OC to any Q
Min
Cl= 50pF
Cl=150pF
Cl=50pF
12
15
ns
ns
ns
ns
Pulse Width,
E High
tw
9
15
18
ns
Setup Time,
D before E'
tsu
6
10
10
ns
Hold Time,
Dafter E'
th
3
5
7
ns
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance * (per latch)
5
pF
COUT Output Disabled
10
pF
OC=Vcc
OC=GND
5
30
CIN
Cpo
pF
2
* Cpo determines the no-load dynamic power dissipation: PO=CPD Vcc fin.
t for AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
294
i~
KS54AHCT
KS7'4AHCT
374
Octal D-Type Flip-Flops
with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74AlS logic family
• low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOl =24 rnA @ VOL =O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '374 consists of 8 high-speed D-type edge-triggered
flip-flops coupled to 3-state output buffers with high drive
current capability. It can be used in implementing buffer
registers, 1/0 ports, bidirectional bus driver and working
registers.
The flip-flops are edge-triggered on the positive transition
of the clock. The Q outputs are set to the logic levels that
were set up at the D. inputs.
The output buffers are controlled by a common signal (OC)
which places the outputs at a high-impedance state when
it is taken high. The OC signal does not affect the internal
operations of the flip-flops. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
6C
Vee
10
80
10
80
20
20
7D
30
30
60
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
70
(Each Flip-Flop)
60
50
40
40
Inputs
Output
50
ClK
G,NO
Q
OC ClK D
L
L
L
H
t
t
L
X
H
L
X
X
H
L
Qo
Z
LOGIC DIAGRAM
10
c8SAMSUNG
Electronics
20
30
40
50
60
70
10
20
30
40
50
60
80
295
II
Octal D~Type Flip-Flops
with 3-State Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vee, . . . . . . . -0.5V to + 7V
DC Input Diode Current, hK
!VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±70 mA
Continuous Current Through
Vee or GND pins ................ ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only ,and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
Vil
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or Vil
10=-20",A
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or Vil
10=20",A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/AA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
VIN=Vee or GND
louT=O",A
per input pin
0
Yi==~2.4V
~Iee
other Inputs:
at Vee or GND
10UT=01AA
c8SAMSUNG
Ele~tronics
Vee Vee -0.1
4.2
3.98
296
KS54AHCT
KS74AHCT"
3'7A
,..,.
Octal 0- Type Flip-Flops
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Maximum Operating
Frequency
Propagation Delay,
ClK to any Q
fmax
T.=25°C
Vcc=5.0V
Conditions r
Symbol
(Input tr , tf~2 ns), AHCT374
CL= 50pF
KS74AHCT
T. = -40°C to +85°C
Vcc=5.0V:10%
Typ
Min
50
35
tpLH
CL= 50pF
CL=150pF
10
13
- - - t-----j-
CL= 50pF
CL=150pF
Output Enable Time, " f RL=1 kG
OC to any Q
tPZL
CL= 50pF
CL=150pF
CL- 50pF
CL=150pF
Output Disable Time, tPHZ
RL=1 kfl
I--OC to any Q
CL=50pF
tpLZ
Pulse Width,
ClK High or low
tw
Setup Time,
D before ClKt
tsu
Hold Time,
Dafter ClKt
th
Power Dissipation
Capacitance *
Unit
--
Max
Min
Max
30
15
19
MHz
17
23
c--
15
19
-----
10
13
~-~--~
tpzH
Input Capacitance
KS54AHCT
+125°C
Vcc=5.0V: 10%
= -55°C to
I----
tpHL
Output Capacitance
T.
ns
17
23
- - - ~----- 1-------
-~-
----
1---------
11
14
11
14
18
23
18
23 - -
13
18
22
13
18
22
7
22
28
22
28
r---
- - - r-----
15
18
ns
ns
ns
- - -1-----
9
14
13
ns
- - - - - - - - t--
-3
5
CIN
COUT
0
Output Disabled
OC=Vcc
OC=GND (per stage)
10
i
0
ns
--1--------
I--P~I--~~
5
30
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSU.NG
Electronics
297
I
Octal D-Type Flip-Flops
with Clock Enable
DESCRIPTION
FEATURES
• Can be used for implementing
- Buffer/Storage Registers
- Shl.ft. Registers
- Pattern Generators
• Function, pln-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High~Drive-Current outputs:
10L =8mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and· CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
Information at the 0 inputs meeting the setup time requirements is transferred to the 0 outputs on the positivegoing edge of the clock pulse if G is low. Clock triggering
occurs at a particular voltage level and is not directly related
to the transition time of the positive-going pulse. When the
clock input is at either the high or low level, the 0 input
signal has no effect at the output. The circuits are design~
ed to prevent false clocking by transitioins at the G input.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
PIN CONFIGURATION
G
The '377 contains eight positive-edge-triggered Ootype flipflops with an enable ihput. This part is similar to '273 but
features a latched clock enable (G) instead of a common
clear.
FUNCTION TABLE
Vee
1Q
8Q
10
80
(EACH FLIP-FLOP)
20
7D
INPUTS
2Q
7Q
.3Q
6Q
G
ClK
DATA
3D
60
H
X
40
50
5Q
L
L
X
t
;t
X
H
L
X
4Q
CLK
GNO
L
OUTPUT
Q
00
H
L
00
LOGIC DIAGRAM
10
(3)
20
(4)
c8SAMSUNG
Electronics
3D
(7)
40
(8)
50
(13)
80
(14)
70
(17)
80
(18)
298
KS54AHCT
KS74AHCT·
377
.
Octal D-Type Flip-Flops
with Clock Enable
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, .... . . . -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . . . . . .
±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 1 25 mA
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vce .............. 4.5V to 5.5V
DC Input & Output Voltages·, VIN. Your .. OV to Vee
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf ......... Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always .betied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
Typ
Ta
KS74AHCT
+85°C Ta
=-40°C to
KS54AHCT
+125°C Unit
= -55°C to
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
VI
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
vi
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Iee
VIN=Vee or GND
10ur=0j.iA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=0",A
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
299
II
377
Octal O-Type Flip-Flops
with Clock·Enable
KS54AHCT
KS74AHCT;, "
AC ELECTRICAL CHARACTERISTICS
Characteristic
Maximum Clock Frequency
Propagation Delay,
ClK to any Q
Symbol
Condltlons t
f max
(Input tr , tf~2 ns), AHCT377
KS74AHCT
KS54AHCT
Ta =25°C T.=-400Cto +85°C
T.=-55°C to +125°C
Unit
Vcc=5.OV
Vcc=5.OV:t10%
Vcc=5.OV:t 10%
Typ
Min
50
35
Max
Min
Max
30
MHz
10
16
19
tpHL
10
16
19
~
CL=50pF
ns
Pulse
Width
G" low
ClK High or low
tw
8
8
14
14
17
17
ns
Setup time
before ClKt
Data
G High or low
tsu
6
9
10
15
10
15
ns
th
-3
0
0
Hold Time, Data after ClKt
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
per package
ns
5
pF
50
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
300
KS54AHCT
KS74AHCT
390
Dual 4-Bit Decade Counters
FEATURES
DESCRIPTION
• Individual clock for A and B flip-flops provide dual + 2
and + 5 counters
• Direct clear for each 4-bit counter
• Significant improvement in system density through
reduced counter package count.
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
(IOL = 8 rnA @. VOL =O.5V)
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices incorporate dual divide-by-two and dividefive counters, which can be used to implement cycle
lengths equal to any whole and/or cumulative multiple of
2 and/or 5 up to divide-by-1 00. When conneoted as a biquinary counter, the ~eparate divide-by-two circuit can be
used to provide symmetry (a square ware) at the final outpur stage. The '390 incorporates dual divide-by-two and
divide-by-five counters, which can be used to implement
cycle lengths equal to any whole and/or cumulative
multiples of 2 and/or 5 up to divide-by-1 00. When connected as a bi-quinary counter, the separate divide-by-tow
circuit can be used to provide symmetry (a square wave)
.at the final outpur stage. The '390 has parallel outputs from
each counter stage so that any submultiple of the input
count frequency is available for system-timing signals.
PIN CONFIGURATION
1CKA
Vee
1CLR
2CKA
1QA
These devices prOVide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
2CLR
1CKB
2QA
1Qe
2CKB
1Qe
2Qs
1Qo
2Qe
GNO
2Qo
FUNCTION TABLES
BIQUINARY (5-2)
(EACH COUNTER)
(See Note B)
BCD COUNT SEQUENCE
(EACH COUNTER)
(See Note A)
OUTPUT
COUNT
0
1
2
3
4
5
6
7
8
9
OUTPUT
COUNT
Qo
Qc
Qs
QA
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
I
0
1
2
3
4
5
6
7
8
9
Qo
Qc
Qs
QA
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
H
H
L
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
I
NOTES A. Output QA is connected to input CKB for BCD count.
B. OutputQo is connected to input CKA for biquinary count.
c8SAMSUNG
Electronics
301
II
Dual 4-Bit Decade Counters
LOGIC DIAGRAM
CKA
(1,15)
T
CLEAR
OB (5,11) OB
CKB
(4,12)
T
(7,9)
00
00
(2,14)
CLEAR
CLR
- Absolute Maximum Ratings*
Supply Voltage Range Vco. . . . . . . . -O.SV to + 7V
DC Input Diode Current, hK
(VI < -O.SV or VI > Vcc +O.SV) . . . .. ±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) ......... ±35 mA
Continuous Current Through
Vcc or GND pins . . . . . . . . . . . . . . .. ± 125 mA
Storage Temperature Range; Tstg ... -65°C to +1S0°C
Power Dissipation Per Package. Pdt ...... SOO mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 6SoC to 85°C.
Recommended Operating Conditions
Supply Voltage. Vcc .............. 4.5V to 5.5V
DC Input & Output Voltages·, VIN, Vour .. OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf .. . . . . . . . Max 500 ns
Unused inputs must always be tied to an. appropriate logic
voltage level (either Vccor GND)
302
390
KS54AHCT
KS74AHCT
Dual 4-Bit Decade Counters
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Ta =25°C
Test Conditions
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
VOH
VIN=VIH or VIL
10=-20,.,A
10= -4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20,.,A
10=4mA
10=8mA
Maximum Input
Current
hN '
VIN=Vee or GND
Additional Worst
Case Supply
Current
Icc
~Iee
Vee Vee -0.1
4.2
3.98
0
VIN=Vee or GND
10uT=0,.,A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0,.,A
Vee -0.1
3.84
Vee -0.1
3.7
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
,.,A
8.0
80.0
160.0
,.,A
2.7
2.9
3.0
mA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Propagation Delay,
CKA
QA or CKB to Qs
to
Symbol
V
"- -
Minimum High-Level
Output Voltage
Maximum Quiescent
Supply Current
V
Conditions t
f max
V
(Input tr , tf~2 ns), AHCT390
KS54AHCT
KS74AHCT
Ta=25°C
Ta = -40°C to +85°C Ta =-55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0Vz10%
Vcc=5.0Vz 10%
Typ
Min
50
30
Max
Min
Max
25
MHz
Propagation Delay,
CKA to QA
~
9
15
18
ns
. tpHL
9
15
18
ns
Propagation Delay,
CKA to Qe
tpLH
r--
24
40
48
ns
tpHL
24
40
48
ns
Propagation Delay,
CKB to Qs
~
10
17
21
ns
tpHL
10
17
21
ns
Propagation Delay,
CKB to Qe
tpLH
r---
16
27
33
ns
tpHL
16
27
33
ns
Propagation Delay,
CKB to Qo
~
10
17
21
ns
tpHL
10
17
21
ns
Propagation Delay,
CLR to Any Q
tpHL
19
30
35
ns
I
CKA or CKB
High or Low
CLR High
CL =50pF
7
12
15
7
12
15
tsu
5
8
10
Input Capacitance
CIN
5
Power Dissipation Capocitance
Cpo
Pulse Width
Minimum Setup Time,
CLR inactive before CKA or CKB
tw
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vec 2
t For AC switching test circuits" and timing waveforms see section 2.
c8SAMSUNG
Electronics
ns
ns
pF
pF
fin.
303
I
393
'.'
KS,~;4A.HCT
KS74AHCT'
Dual 4-bitBin.ry Co",nte,fs
FEATURES
DESCRIPTION
• F.. nctlon, pin-out, speed and drive compatibility with
54174ALS. logic family
• Low power consumption characteristic of CMOS
• High-Drlv.Current outputs:
10l =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '393 consists of two independent 4-bit binary counters
each with its own clear and clock inputs. N-bit. binary
counters can be implemented with each package providing
the capability of divide-by-256. parallel outputs from .each
counter stage provided any submultiple of the input count
frequency for system timing signals.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
Vee
lCLK
lClR
OA
CLK------1I:t.
2ClK
2ClR
lOA
20A
20a
lOa
10e
100
20c
20 0
GND
Oc
00
LOGIC TIMING WAVEFORMS
o
I
1
I
2
I
3
I
4
I
5
I
6
1
7
1
8
1
9
1 10
I
11
I
12
1 13
114
1 15
I
0
I
ClK
ClR
~L
______________________________________________________________________
OA
Oa ]
Oc
J
00
J
I
=8~SUNG
L
L
L
304
KS54AHCT
KS74AHCT
393
Dual 4-blt BilJllry Counters
Absolute Maximum Ratings*
Supply Voltage Range Vcc. . . . . .
-0.5V to +7V
DC Input Diode Current. hK
(VI < -0.5V or VI> Vcc +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vcc +0.5V) . .
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vcc
........ 4.5V to 5.5V
DC Input & Output Voltages *. VIN. Your . . OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Ri 3e & Fall Times. t r • tf ..
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vcc=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
Minimum High-Level
Input Voltage
VIH
Maximum Low-Level
Input Voltage
VIL
KS74AHCT
KS54AHCT
Ta =-40°Cto +85°C Ta=-55°Cto +125°C Unit
Guaranteed Limits
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Vcc -0.1
3.84
Vcc -0.1
3.7
V
VIN=VIH or VIL
Minimum High-Level
Output Voltage
VOH
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
hN
Maximum Quiescent
Supply Current
Icc
10=-20~A
10=-4mA
Vcc Vcc -0.1
4.2
3.98
VIN=VIH or VIL
Additional Worst
Case Supply
Current
~Icc
10=20~A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=VCC or GND
±0.1
±1.0
±1.0
~A
8.0
80.0
160.0
~A
2.7
2.9
3.0
mA
VIN=VCC or GND
10UT=0~A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10u~=0~A
c8SAMSUNG
~1"l'trnnil'''
0
305
a
393
KS54AHCT
KS74AHCT .
Dual 4-bit Binary Counters
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr ,
tf~2 ns), AHCT393
KS74AHCT
KS54AHCT
Ta=25°C
Ta":: -40°C to +85°C Ta= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V:t10%
Vcc=5.0V:t 10%
Typ
Min
Maximum Clock Frequency
f max
50
30
Propagation Delay,
A to OA
tpLH
'---
14
22
26
tpHL
14
22
26
Propagation Delay,
A to Os
-
tPLH
18
27
32
tpHL
18
27
32
Propagation Dealy,
A to Oc
-
tpLH
20
33
40
tPHL
20
33
40
Propagation Delay,
A to 00
-
Propagation Dealy,
CLR to any 0
Pulse
Width
I A Input High
or Low
ICLR High
Setup Time,
CLR Inactive before A
CL=50pF
Min
Max
25
MHz
tpLH
26
40
48
tpHL
26
40
48
tPHL
15
25
30
tw
tsu
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
7
12
15
7
12
15
5
8
10
ns
ns
ns
ns
ns
ns
ns
pF
5
(per counter)
pF
40
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
·c8SAMSUNG
Max
fin.
306
KS54AHCT
KS74AHCT
399
Quad 2-Port Registers
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOl =8 mA @ VOL =O.5V
• .Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These are high-speed quad 2-port registers. They are the
logical equivalent of a quad 2-input multiplexer followed by
a quad 4-bit edge-triggered register. A common select input (SELl selects between two 4-bit input ports. The
selected data is transferred to the output register on the
low-to-high transition of the clock input.
PIN CONFIGURATION
Vee
0.
1A
00
10
20
28
18
Os
GNO
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
SEL
2A
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
SEL
Port 1
I
..
I
_
J
I
I
~lIIput_
Inputs
a
Pori 2
x
I
_.--l-...-
L
I
I
2C
1C
Oe
ClK
I
= Low Voltage Level one setup time prior to the low-to-high
clock transition
h = High Voltage Level one setup time prior to the low-to-high
clock transition
c8SAMSUNG
1:I.o.I'+..n.ni,...~
307
KS54AHCT
KS74AHCT
399
Quad 2-Port Registers
LOGIC DIAGRAM
Q.
1B(~6~1-----------+~--~,
281£L------+-+---,-4..,..,J
1C
~1~1~________-+-+-__~~
12
2C (,.:..
: : l - - - - -_ _ _ _ _ _+-11-----4.....J
1o (:..:.1-"41'--______-+-+-__..--,
20
(~13=1
_ _ _ _ _ _ _ _ _~~
ClK (_91_ _ _ _ _ _ _ _ _ _--1
Absolute Maximum Ratings·
Supply Voltage Range Vcc, .. .
-0.5V to + 7V
DC Input Diode Current, J,K
(VI < -0.5V or VI > Vce +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vce +0.5V)
±35 rnA
Continuous Current Through
Vee or GND pins .........
± 1 25 rnA
Storage Temperature Range, Tstg . . . - 65 ° C to + 150 ° C
Power Dissipation Per Package, Pdt ...... 500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
'::Io,..tr"ni,..~
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . . . . . 4.5V to .5.5V
DC Inpul& Output Voltages·, VIN, VOUT .. OV to Vce
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
308
KS54AHCT
KS74AHCT
399
Quad 2-Port Registers
DC ELECTRICAL CHARACTERlsnCS
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Ta=25°C
Symbol Test Conditions
Characteristic
(Vcc=5V± 1 0% Unless Otherwise Specified)
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/AA
10= -4mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/AA
10=4mA
10==8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
/AA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/AA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Icc
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
10uT=0/AA
per input pin
VI==2.4V
other Inputs:
at Vcc or GND
louT=O/AA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditionst
(Input tr • tf~2 ns), AHCT399
KS54AHCT
KS74AHCT
Ta =25°C
Ta = -40°C to +85°C Ta = -55°C to +125°C
Vcc=5.0V
Vcc=5.0V± 10%
Vcc=5.0V±10%
Typ
Propagation Delay.
ClK to Q
Time
ibefore ClKt
I Data
I Word Select
Max
Min
Max
19
23
tpHL
12
19
23
tw
6
t---
Pulse Width.
ClK High or low
Min
12
tpLH
tsu
th
Hold Time. Data after ClKt
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
CL=50pF
10
ns
ns
10
15
6
10
15
0
0
5
ns
15
6
-3
Unit
ns
pF
pF
* .Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
309
I
423
..
Dual Retriggerable Monostable
Multivibrator with Clear
KS54AHCT
KS74AHCT·
FEATURES
DESCRIPTION
• Simple pulse width formula tw = 0.45RC
• DC triggered from active HIGH or active Low inputs
• Retriggerable for very long output pUlses up to 100 %
duty cycle
• Overriding clear terminates output pulse
• SchmiU trigger A & B inputs allow infinite rise and
fall times on these inputs
• Functions, pin-out, speed and drive compativility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High drive current outputs:
IOL=8mA @ VOL=0.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range; 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '423 contains dual retriggerable monostable
multivibrators with output pulsewidth control by two
methods. The basic pulse time is programmed by selection of an external resistor (REXT) and capacitor (CEXT). The
external resistor and capacitor are normally connected as
shown timing component.
Once triggered, the basic output pulse width may be extended by retriggering the gated active Low-going edge
input (Ai) or the active High-going edge input (8i). 8y
repeating this process, the output pulse period (nQ=HIGH,
nQ=LOW) can be made as long as desired.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques.
The output pulse equation is simply;
tw=0.45X(REXT) (CEXT)
Where tw is in seconds. R is in ohm. and C is in fards.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
PIN CONFIGURATION
Inputs
A1
Vee
B1
Ron/COT
Grn1
0"1
02
C EXT2
REXT2/CEXT
COT.
01
0"2
Grn2
A
B
Q
Q
L
X
X
H
H
X
H
X
L
X
X
L
t
H
L
L
L
H
H
H
JL
Il..
l.S
l.S
+
B2
1\2
c8SAMSUNG
Electronics
Outputs
CLR
H=
L=
X=
t=
HIGH voltage level
LOW voltage level
don't care
LOW to HIGH transition
+= HIGH to LOW transition
Jl..= one HIGH level output pulse
LS= one LOW level output pulse
310
KS54AHCT
KS74AHCT
423
Dual Retriggerable Monostable
Multivibrator with Clear
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package(N): -'12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ............... -0.5V to + 7V
DC Input Diode Current, hK
(VI<-0.5V or VI>Vce+0.5V) ................. ±20 mA
DC Output Diode Current, 10k
(Vo<-0.5V or Vo>Vee+0.5V) ............... ±20 mA
Continuous OUtput Current Per Pin, 10
(-0.5V Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±70 mA
Continuous Current Through
Vec or GND pins
. . .. ± 250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee .............. 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf . . . . . . . . . Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability
Unused inputs must always be tiep to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta=-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
Vee -0.1
3.84
Vee -0.1
3.7
V
VIN=VIH or VIL
10=-20/JA
10=-6mA I
Vee Vee -0.1
4.2
3.98
VIN=VIH or VIL
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
10=20~A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
~A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
/AA
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
~Iee
0
I
VIN=Vee or GND
10UT=0~A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
8.0
80.0
160.0
~A
2.7
2.9
3.0
rnA
I
I
10uT=0~A
c8SAMSUNG
Electronics
314
KS54AHCT ~D:J/~DD
KS74AHCT
4671468
AC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Octal Buffers and Line Drivers
with 3-State Outputs
AHCT465, AHCT466,
(Input tr, t,4I02 ns), AHCT467. AHCT468
T.=2SoC
Vee=S.OV
KS74AHCT
S4AHCT
T.= -40·C to +8S·C T. = + 55°C to -+ 125°C
Unit
Vee=5.0V:t:10%
Vee'" S.OV:t: 10%
Typ
Propagation Delay,
A to Y
Min
Max
Min
Max
tpLH
CL=oOpF
CL=150pF
7
10
12
17
14
20
tPHL
CL=50pF
CL=150pF
7
10
12
17
14
20
20
25
Output Enable Time,
Enable to Y
CL=50pF
tPZH
CL ==150pF
r----- RL=1k!l
CL=50pF
tPZL
CL=150pF
12
15
12
15
20
25
24
30
Output Disable Time,
Enable to Y
tPHZ
- tpLZ
RL=1k!l
CL=50pF
13
18
22
13
18
22
Output Disabled
Output Disabled
Output Enabled
10
Input Capacitance
CIN
Output Capacitance
COUT
Power Dissipation
Capacitance· (per stage)
Cpo
24
30
-~
-------
- ns
-
c8SAMSUNG
Electronics
ns
pF
5
-~
5
30
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
For AC switching test circuits and timing waveforms see section 2.
ns
t----~-----
pF
pF
I
fin.
315
KS54AHCT
5181519
8-Bit Identity
Comparators
KS74AHCT.,52015211522
FEATURES
DESCRIPTION
• Compares two 8-bit words
• '518, '520 and 522 have 20kO pull-up Resistors on
Q Inputs
These identity comparators perform comparisons on two
eight-bit binary or BCD words. The '518 and '519 provide
P=Q outputs, while the '520, 521, and '522 provide P=Q
outputs. The '518; '519, and '522 have open-drain
outputs. The '518, '520, and '522 feature 20-kO inputs
for analog or switch data.
Ty'PE
INPUT
PULL-UP
RESISTOR
OUTPUT FUNCTION
AND
CONFIGURATION
'518
Yes
P=Q Open-Drain
'519
No
P=Q Open-Drain
'520
Yes
P=Q Totem-Pole
'521
No
P=Q Totem-Pole
'522
Yes
P=Q Open-Drain
t '521 is identical to '688
These devices provide. speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL =24 mA @ VOL =0.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5_5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
FUNCTION TABLE
PIN CONFIGURATION
G
INPUTS
Vee
PO
P=O/P=Ot
00
P1
07
01
06
P2
P6
02
05
PQ
L
L
H
L
L
H
H
L
H
t P=.Q for '518
and '519;
P=Q for '520, '521, '522.
c8SAMSUNG
Electronics
316
KS54AHCT
KS74AHCT
518/519
520/521/522
..8-8it Identity
Comparators
LOGIC DIAGRAMS
'5181'519
'5201'5211'522
P7
P7
07
P6
P6
06--..., .......---
06
P5
P5----t1
05
~ou-1
05
P4
04
P3-----.~~
P3-----.~~
o~
03----. ...~
P2
02
P2
(7)
P1~\_
I
I
01~
PO
I
I
01----.~~
(2)
OO--""~~
Absolute Maximum Ratings·
Supply Voltage Range Vee, ...... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V <- Vo < Vec +0.5V) . . .
±70 mA
Continuous Current Through
Vee or GND pins. . . . . . .
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt. . . .. 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
CI.o.,,+rnni,...o-
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/o.C from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vce
Operating Temperature·
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
.. Max 500 ns
Input Rise & Fall Times. tr , tf
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
317
KS54AHCT
'KS74AHCT
518/519
520/521/522
DC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
~:
------------
I
Maximum Low-Level
Input y,?~!age
Minimum High-Level
Output Voltage
(Totem-pole Outputs)
I
Maximum Low-Level
Output Voltage
(All Outputs)
----Maximum Input
i Current,
(,518, '520 and '522
(Vcc""5V± 1 0% UnlesS Otherwise Specified)
~a=250_~
typ
---
Test Conditions
!
Minimum High-Level
Input Voltage
8-Bit Identity
Comparators
54AHCT
KS74AHCT
TA = -400C to +850C Ta =-55°Cto +125°C Unit
Guaranteed Limlt$
---~
2.0
VfH
...
~.---
-~-
2.0
2.0
c--- - - - - - - - - - 1 - - - - - - - - - - - 0.8
V,L
VOH
V'N=V'H or V,L
lo=-20/AA
lo=-6mA
- -- - - V'N=V'H or V,L
lo= 2O/AA
VOL
lo=12mA
lo=24mA
0.8
o l~put)
- - - - - - - - - -1 - - - - - - - - - - - - -
0
I---- -
0.1
0.26
0.39
~-------------
Vee -0.1
3.84
Vcc Vcc -0.1
4.2
3.93
--~-
----
V
--- - - - - - - - - - - -
0.8
-1---- - - - - - 1 - - - - - - - - - - - - - -
~-
V
-V
Vce -0.1
3.7
~----------
---
0.1
0.4
V
0.1
0.33
0.5
--
~-
----
--
-- ---
Vee=Max
V'N=2.7V
V'N=0.4V
-0.2
-0.6
-0.2
-0.6
-0.2
-0.6
mA
Maximum Input
Current
(All other Inputs)
liN
V'N=VCC or GND
±0.1
±1.0
±1.0
IJA
Maximum Output
Leakage Current
(Open-Drain Outputs)
loz
V'N=V'H or V,L
Vour=Vee
±0.5
±5.0
±10.0
IJA
For '518, '520 and
'522:
V'N=GND (00-07)
V'N=VCC or GND
(all other inputs)
3.5
3.5
3.5
mA
For '519 and '521:
VIN=Vce or GND
lour=O/AA
8.0
80.0
160.0
IJA
per input pin
V,=2.4V
other Inputs:
at Vce orGND
lour = OJAA
2.7
2.9
3.0
mA
Maximum
Ouiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
.6. Icc
c8SAMSUNG
Clft.......,..,_;,,~
318
518/519
~~~::~g~ 520/521/522
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions
(Input tr • tf~2 ns). AHCT518. AHCT5·19
54/74ACHT
T.=25°C
Vcc=5V
Typical
Propagation Delay.
P or Q to P=Q
Propagation Delay.
G to P=Q
tpHL
CL=50pF
CL=150pF
15
18
25
30
30
36
tpLH
C=50pF
CL=150pF
16
19
23
28
27
33
tpHL
CL=50pF
CL=150pF
11
14
18
23
22
28
Symbol
Conditions
(Input tr • tf~2 ns). AHCT520. AHCT521
54174ACHT
KS74AHCT
T,.=25°C T. = - 40°C to + 85°C
Vcc=5V:t10%
Vcc=5V
Max
Min
19
24
23
29
tPHL
CL=50pF
CL=150pF
12
15
19
24
23
29
tPLH
C=50pF
CL=150pF
11
14
17
22
20
26
tpHL
CL=50pF
CL=150pF
11
14
17
22
20
26
Conditions
(Input tr • tf~2 ns). AHC522
54174ACHT
KS74AHCT
54AHCT
T,.=25°C T. = -40°C to +85°C T. = -55°C to +125°C
Vcc=5V
Vcc=5V± 10%
Vcc=5.0V± 10%
Min
Max
Min
CL=50pF
CL=150pF
19
22
28
33
33
39
tPHL
CL=50pi=
CL=150pF
14
17
23
28
28
34
tpL:H
C=50pF
CL=150pF
16
19
23
28
27
33
tpHL
CL=50pF
CL=150pF
11
14
18
27
22
33
CIN
Cpo
5
Unit
Max
tpLH
Power Dissipation Capacitance *
ns
.pF
Typical
Input Capacitance
ns
pF
5
AC ELECTRICAL CHARACTERISTICS
Symbol
Unit
Max
12
15
CIN
Propagation Delay.
G to P=Q
Min
54AHCT
T. = -55°C to + 125°C
Vc c =5.0V:t 10%
CL=50pF
CL=150pF
Cpo
ns
pF
tpLH
Power Dissipation Capacitance *
ns
pF
5
Typical
Input Capacitance
Unit
Max
35
41
AC ELECTRICAL CHARACTERISTICS
Pr.opagation Delay.
P or Q to P=Q
Min
tPLH
CIN
Characteristic
Max
30
35
Cpo
Propagation Delay.
G to P=Q
Min
54AHCT
T. = -55°C to + 125°C
Vcc=5.0V:t 100/.
20
23
Power Dissipation Capacitance *
Propagation Delay.
P or Q to P=Q
KS74AHCT
T. = -40°C to +85°C
Vcc=5V:t10%
CL=50pF
CL =150pF
Input Capacitance
Characteristic
B-Bit Identity
Comparators
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms' see section 2.
cHSAMSUNG
319
I
Octal.. D-Type Tra:nsparent Latches
. .
with "~-State Outputs
FEATURES
DESCRIPTION
• 8 I~tches"in a single package
• Full parallel access for loading
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL 24 rnA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
• Package options Include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '533 consists of 8 high-speed Ootype latchescQupled to 3-state output buffers with high drive current capability.lt can be used in implementing buffer registers, I/O ports,
bidirectional bus drivers and working registers.
=
The latches are transparent: when the enable (E) is high,
the Q outputs follow the complements of the data (0) inputs. When the enable is low, the outputs latch at the levels
that were set up at the. 0 inputs.
=
The output buffers are controlled by a common signal (OC)
which places the outputs at high-impedance state when
it is taken high. The OC signal does not affect the internal
operations of the latches. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive caJjability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage. levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
FUNCTION TABLE
oc
Vee
10
10
20
20
30
3D
80
80
(Each Latch)
Inputs
70
70
6<:1'
60
50
50
40
40
E
0
Q
L
L
L
H
H
L
X
H
L
X
X
L
H
H
E
GNO
Output
OC
00
Z
LOGIC DIAGRAM
10
=8
20
3D
SAMSUNG SEMICONDUCTOR
40
50
60
70
80
320
KS54AHCT
KS74AHCT
533
Octal D-Type Transparent Latches
with 3-State Outputs
Absolute Maximum Ratings*·
Supply Voltage Range Vee, ....... -075V to +iv
DC Input Diode Current, irK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins . .. . . . . . .
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
·t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device· may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
Recommended Operating Conditions
Supply Voltage, Vee .............. 4.5V to 5:5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
KS74AHCT: ~40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, fr, tf . . . .
Max 500 ns
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
Vil
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or Vil
10=-20}olA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or Vil
10=20,.,A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
IrN
VIN=Vee or GND
±0.1
±1.0
±1.0
,.,A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±S.O
±10.0
,.,A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
,.,A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Alec
VIN=Vee or GND
10uT=0,.,A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0,.,A
=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
321
I
KS54AHCT
KS74AHCT
533
Octal 0-Type Transparent Latches
with 3-State Outputs
AC E~ECTRICAL CHARACTERISTICS
Characteristic
Symbol Condltlons t
(Input tr , tf<2 ns), AHCT533
KS54AHCT
KS74AHCT
T. ==25 0 C
T. = -40°C to +85°C T. == - Ssoc to + 12SoC
Unit
Vee-5.0V
Vee 5.0V:t 10%
Vee=S.OV:I: 10%
=
Typ
Propagation Delay,
Dto Q
a
Max
tpLH
16
21
19
25
tpHL
CL=50pF
CL=150pF
10
13
16
21
19
25
tPLH
C=50pF
CL=150pF
13
16
21
26
25
31
tpHL
CL=50pF
CL=150pF
13
16
21
26
25
31
CL=50pF
CL=150pF
11
14
18
23
22
28
CL=50pF
CL=150pF
11
14
18
23
22
28
13
18
22
13
18
22
tPZH
I---
Output Disable Time,
OC to any
f--
a
Min
10
13
Output Enable Time.
OC to any
a
Max
CL=50pF
CL=150pF
f--
Propagation Delay,
Eto
Min
RL=1 kO
tpZ\.
tpHZ
tpLZ
RL =1 kO
CL=50pF
ns
ns
ns
ns
Pulse Width,
E High
tw
9
15
18
ns
Setup Time,
D before EJ.
tsu
9
15
18
ns
Hold Time,
Dafter E J.
th
3
5
7
ns
Input
Capacitance
CIN
5
pF
Output
Capacitance
Cout
Output Disabled
10
pF
Power Dissipation
Capacitance· (per stage)
Cpo
OC=Vcc
OC=GND
5
30
-
pF
2
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
322
KS54AHCT
KS74AHCT
534.
Octal ·0-Type Flip-Flops
with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174AlS logic family
• low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL 24 mA@ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +~5°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape Be Reel), standard DIPs.
The '534 consists of 8 high-speed D-type edge-triggered
flip-flops coupled to 3-state output bufters with high drive
current capability. It can be used in implementing buffer .
registers, I/O ports, bidirectional bus driver and working
registers.
=
=
The flip-flops are edge-triggered on the positive transition
of the clock: the Q outputs are set to the complement of
the logic levels that were set up at the D inputs.
The output buffers are controlled by a common signal (OC)
which places the outputs in high-impedance state when it
is taken high. the OC signal does not affect the internal
operations of the flip-flops. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
oc
10
10
20
20
30
3D
40
40
GNO
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
Vee
80
80
70
7Q
FUNCTION TABLE
60
(Each latch)
60
50
Output
Inputs
50
OC ClK D
ClK
L
L
L
H
t
t
L~
X
Q
H
L
L
X
X
H
00
Z
LOGIC DIAGRAM
10
c8SAMSUNG
Electronics
20
3D
40
50
60
70
80
323
KS54AHCT
KS74AliCT
534
Octal 0-Type· Flip-Flops
with 3-State Outputs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vee, ..... ~ . -0.5V to + 7V
DC Input Diode Current, "K
.
(VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) . . . . ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±70 mA
Continuous Current Through
Vee or GND pins ................ ±250 mA
Storage Temperature Range, Tstg . . . - 65 ° C to + 150 ° C
Power Dissipation Per Package, Pdt ...... 500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, fr, tf . . . . . . . . . Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
KS74AHCT
KS54AHCT
Ta = -40°C to +85 0 C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
O.B
0.8
V
Minimum High-Level
Output Voltage
VOH
Vee -0.1
Vee -0.1
3.7
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20,.,A
10=12mA
10=24mA
Maximum Input
Current
"N
Maximum 3-State
Leakage Current
loz
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
~Iee
VIN=VIH or VIL
10=-20,.,A
10=-6mA
Vee Vee -0.1
4.2
3.98
3.B4
4
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=Vee or GND
±0.1
±1.0
±1.0
,.,A
Output Enable
=VIH
VouT==Vee or GND
±0.5
±5.0
±10.0
,.,A
B.O
BO.O
160.0
,.,A
2.7
2.9
3.0
mA
VIN=Vee or GND
10uT=0,.,A
per input pin
V,=2.4V
other Inputs:
at Vee or GND
10uT=0,.,A
.=8~SUNG
0
324
KS54AHCT
KS74AHCT
534
Octal D-Type Flip-Flops
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Maximum Operating
Frequency
Propagation Delay,
CLK to any
a
Output Enable Time,
OC to any
a
Output Disable Time,
OC to any Q
Symbol Condltions t
(Input tr , t,402 ns), AHCT534
KS74AHCT
KS54AHCT
T.=25°C
T. = -40°C to +85°C T. = -55°C to + 125°C
Unit
Ycc= 5.0Y
Ycc=5.0Y%10%
Ycc=5.0Y% 10%
Typ
Min
35
Max
Min
Max
fmax
CL=50pF
50
tpLH
CL=50pF
CL=150pF
8
11
14
19
17
23
tpHL
CL=50pF
CL=150pF
8
11
14
19
17
23
tPZH
ICL=50PF
RL = 1 kP. CL = 1 50pF
11
14
18
23
22
28
ICL=50PF
CL =150pF
11
14
18
23
22
28
13
18
22
13
18
22
I------~
tPZL
~
RL=1kU
CL=50pF
tpLZ
MHz
30
ns
ns
ns
Pulse Width,
ClK High or low
tw
9
15
18
ns
Setup Time,
o before ClKt
tsu
9
14
17
ns
Hold Time,
Dafter ClKt
th
0
0
0
ns
Input Capacitance
t--.
5
pF
COUT
Output Disabled
10
pF
Cpo
OC=Vee
OC=GND
5
30
pF
CIN
-----
Ol'~put
Capacitance
Power Dissipation
Capacitance· (per stage)
t----
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fin.
t For AC switching test circuits and timing waveforms see section 2.
=8~SUNG
325
II
KS54AtiCT
KS74AHCT
54'01541
I·
Octa/Buffers and Line Drivers
with 3-State Qutputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOl 24 mA@ VOL = 0.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '540 and '541 are general purpose high-speed octal
line drivers/buffers with 3-state outputs. The inputs and
outputs are located on opposite sides of the 20-pin
package, thus improving circuit board density. The '540
provides inverted data and the '541 provides true data at
the outputs.
=
The three-state control gate is a 2-input NOR such that
if either <31 or <32 is high, all eight outputs are in the high
impedance state.
These devices provide speeds and drive capability
equivalent to their ALSTTLcounterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
LOGIC DIAGRAMS
PIN CONFIGURATION
(1)
81
Vee
A1
<32
A2
Y1
A3
Y2
A4
Y3
AS
Y4
A6
YS
A7
Y6
A8
Y7
GNO
Y8
'540
(1)
<31
131
82
<32
A2
Y1
A1
Y2
A2
(16)"
(16) Y3
(1S)
(1S)
Y4
Y4
(14)
(14)
AS
YS
YS
(13)
A6
Input
Output
G,
Vcc +0.5V) .
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) . .
±70 mA
Continuous Current Through
Vce or GND pins
± 250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vce
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to + 125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vec==5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/JA
10=-6mA
Vcc -0.1
3.84
Vce -0.1
3.7
V
Maximum Low-Level
Output Voltage
VbL
VIN=VIH or VIL
10=2O/J A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/J A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VOUT=VCC or GND
±0.5
±5.0
±10.0
/J A
Maximum Quiescent
Supply Current
Icc
VIN=Vee or GND
10uT=0/JA
8.0
80.0
160.0
/J A
c8SAMSUNG
Electronics
Vcc Vce -0.1
4.2
3.98
0
327
II
KS54AHCT
KS74~HCT
54'0'541
,.
Octal Buffers an,d Line Drivers"
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
(Input tr •
tf~2 ns).
AHCT540. AHCT541
I
Characteristic
Symbol Conditions t
KS54AHCT
KS74AHCT
T. =25°C
T. = -40°C to +85°C T. = -55°C to +125°C
Unit
Vee = 5.0V
Vce=5.0V:!:10%
Vec=5.0V:!: 10%
Typ
Propagation Delay.
A to Y
-
Output Disable Time
G to Y
-
tPLH
12
tpHL
CL= 50pF
CL =150pF
7
12
RL=1kO
tPZL
tPHZ
tpLZ
Input Capacitance
Output Capacitance
Power Dissipation \
Capacitance * (per s~ge)
Max
7
10
tPZH
Output Enable Time.
Gto Y
Min
CL= 50pF
CL=150pF
17
12
15
20
25
24
30
CL=50pF
CL=50pF
12
15
20
25
24
30
10
14
1----"----
19
~------
14
--
f---------
19
ns
------
"--
---~~-.-.-
-- ns
23
- - - - , ns
23
--
5
-pF
pF
Caul
Output Disabled
10
Cpo
G=Vcc
G=GND
5
30
pF
2
.. Cpo determines the rio·load dynamic power dissipation: PO=CPD VCC fin.
t For AC switching test circuits and timing waveforms see'section 2.
=8~SUNG
14
20
17
CL= 50pF
CL =150pF
CIN
\
Max
14
20
RL =1 kO
CL=50pF
\\
Min
KS54AHCT
KS74AHCT
563
OctalD-Type Transparent·Latches
with 3-5tate Outputs .
FEATURES
DESCRIPTION
• 8 latches in a single package
• Full parallel access for loading
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-8tate outputs with high drive current
(IOL 24mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to + 85°C
KS54AHCT: -55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '563 consists of 8 high·speed Ootype latches coupled to 3-state output buffers with high drive current capability. It can be used in implementing buffer register, 1/0 ports,
bidirectional bus drivers and working registers.
=
=
PIN CONFIGURATION
oc
Vee
10
10
20
3D
40
50
20
30
40
60
70
80
GNO
50
60
70
80
E
The latches are transparent: when the enable (E) is high,
the Q outputs follow complements of the data (0) inputs.
When the enable is low, the outputs latch at the leveis that
were set up at the 0 inputs.
The output buffers are controlled by a common signal (OG)
which places the outputs at a high-impedance stage when
it is taken high. The OC Signal does not affect the internal
operations of the latches. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
FUNCTION TABLE
(Each latch)
Output
Inputs
OC
E
b
L
L
L
H
H
H
X
H
L
X
X
L
Q
L
H
00
Z
LOGIC DIAGRAM
=8SAMSUNG
8ectronics
329
I
KS'54AHCT 5B3~~';"\;
KS74AHCT
. <:"':i!
Octal D-Type Transparent Latches
with 3-State Outputs
Absolute Maximum Ratings*
Supply Voltag~ Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, hK
(V, < -:-'0.5V or VI > Vcc +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-O.5V < Vo < Vcc +0.5V)
±70 mA
Continuous Current Througtl
Vce or GND pins
. . . . . . .. ± 250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vcc
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
_.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
(Vcc=5V± 10% Unless Otherwise Specified)
Ta =25°C
Ta
KS74AHCT
KS54AHCT
+85°C Ta = -55°C to +125°C Unit
= -40°C to
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/AA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O /JA
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
j.lA
Maximum 3-State
Leakage Current
102
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
/AA
Maximum Quiescent
Supply Current
Icc
8,0
80.0
160.0
/AA
2.7
2.9
3.0
mA
I
Additional Worst
Case Supply
Current
t.lee
VIN=Vee or GND
10UT=0/JA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10UT=0/AA
.c8SAMSUNG
Electronics
Vee Vee -0.1
3.98
4.2
0
330
KS54AHCT
KS74AHCT
563
Octal 0-Type Tra'(lsparent Latches
with 3-8tate Outputs
AC ELECTRICAL CHARACTERISTICS
Characterlatlc
Symbol
Condltlona t
(Input tr , tf~2 ns), AHCT563
T. =25 0 C
T.
Ycc=5.OY
Typ
Min
Max
Min
Max
CL= 50pF
tPLH CL =150pF
12
15
18
23
22
28
tpHL
CL= 50pF
CL =150pF
12
15
18
23
22
28
tpLH
C= 50pF
CL=150pF
14
17
22
27
27
33
tpHL
CL= 50pF
CL =150pF
14
17
22
27
27
33
Output Enable Time,
OC to any
CL= 50pF
tPZH
CL=150pF
r------ RL=1kO
CL= 50pF
tPZL
CL=150pF
11
14
18
23
22
28
11
14
22
28
Output Disable Time,
OC to any
tpHZ
r------ RL=1kO
13
18
23
19
22
13
19
22
Propagation Delay,
D to
a
I
KS54AHCT
KS74AHCT
+85°C T.=-55~Cto +125°C
Unit
Ycc .. 5.OY:t 10%
Ycc=5.0Y:t10%
= -40°C to
ProPa.9ation Delay,
Eto
a
a
a
tpLZ
CL=50pF
ns
ns
ns
ns
Pulse Width,
E High
tw
9
15
18
ns
Setup Time,
D before E+
tsu
6
10
10
ns
Hold Time,
Dafter E +
th
3
5
7
ns
Input
Capacita~ce
Output Capacitance
Power Dissipation
Capacitance· (per stage)
5
pF
COUT
Output Disabled
10
pF
Cpo
OC=Vcc
OC=GND
5
30
pF
CIN
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin,
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
331
II
Octal D-Type Flip-Flops
with 3-Sta'te Outputs'
FEATURES
DESCRIPTION
• Function, pilH)ut, speed and drive compatibility with
54174AlS logic family
• low power consumption charaCteristic of CMOS
• 3-State outputs with high drive current
(IOL 24mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C + 85°C
KS54HACT: - 55°C + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '564 consists of 8 high-speed Ootype edge-triggered
flip-flops coupled to 3-state output buffers with high drive
current capability. It can be used in implementing buffer
registers, I/O ports, bidirectional bus driver and working
registers.
=
=
The flip-flops are edge-triggered: on the positive transition
of the clock, the Q outputs are set to the complement of
the logiC levels that were set up at the 0 inputs.
The output buffers are controlled by a common signal (OC)
which places the outputs at high impedance stat when
it is taken high. The OC signal does not affect the internal
operations of the flip-flops. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maint Vcc +0.5V) . . . .. ±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vcc +0.5V) ......... ±70 mA
Continuous Current Through
Vcc or GND pins ................ ±250 mA
Storage Temperature Range, T5 tg ..• -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mWfOC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vcc . . . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages·. VIN. VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times. tr • tf ......... Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the de~ice may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vec=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20,..A
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20,..A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
,..A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
p.A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
,..A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
h.lcc
VIN=Vee or GND
10uT=0,..A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10uT=0,..A
=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
333
I
KSS4AHCT
KS74AHCT
86'
Octal D-Type Flip-FlOps
with 3-State Outputs'
AC ELECTRICAL CHARACTERISTICS
Ch.r.cterlatlc
Maximum Operating
Frequency
Propagation Delay,
ClK to any Q
Output Enable Time,
DC to any
a
Output Disable Time,
oc to any
a
Symbol
Condltlon. t
(Input tr , tt<2 ns), AHCT564
KS74AHCT
kS54AHCT
T. _25°C
T. - -40°C to +85°C T. _ -55°C to +125°C
Unit
Vcc-5.0V
Vcc-5.0V:t 10%
Vcc-5.0V:i:10%
Typ
Min
35
Mex
Min
Mu
fmax
CL= 50pF
50
tPLH
CL= 50pF
CL=150pF
8
11
14
19
17
23
tPHL
CL= 50pF
CL=150pF
8
11
14
19
17
23
CL= 50pF
CL=150pF
11
14
18
23
22
28
CL= 50pF
CL=150pF
11
14
22
28
13
18
23
19
13
19
28
tPZH
I---
RL=1kO
tPZL
~
tpLZ
RL=1kO
CL=50pF
MHz
30
22
ns
ns
ns
Pulse Width,
ClK High or low
tw
9
15
18
ns
Setup Time,
D before ClKt
tau
9
14
17
ns
Hold Time,
Dafter ClKt
th
a
0
0
ns
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance * (per stage)
5
pF
Output Disabled
10
pF
OC=Vcc
OC=GND
5
30
pF
CIN
COUT
Cpo
* Cpo determines the no·load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
.
334
KS54AHCT It:
KS74AHCT ~
73
Octal D- Type Trilpsparent Latches
with 3-State Outputs
FEATURES
DESCRIPTION
• 8 latches in a single package
• Full parallel access for loading
• Function, pin-out, speed and drive compability with
54174ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface direclty with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to + 85°C
KS54HACT: -40°C to + 125°C
• Package options include "small outline" packages
(Available Tape & ~eel), standard DIPs.
The '573 consists of 8 high-speed O-type latches coupled to 3-state output buffers with high drive current capability. It can be used in implementing bufer registers, flO ports,
bidirectional bus drivers and working registers.
=
=
The latches are transparent: when the enable E is high,
the outputs follow the data (0) inputs. When the enable
is low, the outputs latch at the levels that were set up at
the 0 inputs.
a
The output buffers are controlled by a common signal (OC)
which places the outputs at a high-impedance state when
it is taken high. The OC signal does not affect the internal
operations of the latches. Old data can be retained or new
data can be entered while outputs are off. .
There devices provide speeds and drive capability
equivalent ot their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
PIN CONFIGURATION
6C
FUNCTION TABLE
Vee
10
20
3D
40
10
20
30
40
50
60
70
80
50
6Q
70
80
GNo
E
(Each Latch)
Inputs
Output
OC
E
D
Q
L
L
L
H
H
H
L
X
H
L
X
X
H
L
00
Z
LOGIC DIAGRAM
10
c8SAMSUNG
Electronics
20
3Q
40
50
60
70
80
335
I
KS54AH'CT 573~
KS74AHCT
Octal 0-Type TrIIIftIpII:rent ,Latches
with 3-State Outputs
Absolute Maximum Ratings·
Supply Voltage Range Vee, . . . . . . . -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) . . . . ±20 mA
90ntinuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±70 mA
Continuous Current Through
Vee or GND pins ................ ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . ... . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
• Absolute Maximum Ratings are those values beyond
which. permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 1 0% Unless Otherwise SpeCified)
Ta =25°C
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High.lLevel
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20,.,A
10=-6mA
Vec -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10 = 20,.,A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
,.,A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
,.,A
Maximum Quiescent
Supply Current
lee
8.0
80.0
160.0
,.,A
2.7
2.9
3.0
mA
-
Additional Worst
Case Supply
CurFent
.6.lee
VIN=Vee or GND
10UT=0,.,A
per input pin
VI=2.4V
other Inputs:
at Vccor GND
10UT=0,.,A
=8~SUNG
Vec Vee -0.1
3.98
4.2
0
336
KS54AHCT
KS74AHCT
573
Octal D-Type Transparent Latches
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input tr tf~2 ns), AHCT573
KS74AHCT
KS54AHCT
Ta =25°C
Ta = -40°C to +85°C Ta =-55°Cto +125°C
Unit
Vee=5.0V
Vee = 5.0V ~ 10%
Vee=5.0V~ 10% __
Min
Typ
Propagation Delay,
D to Q
Propagation Delay,
Eto Q
Output Enable Time
OC to any Q
Pulse Width,
E High
Min
Max
tpLH
9
12
16
19
20
23
tpHL
CL= 50pF
CL=150pF
9
12
16
19
20
23
tpLH
C=50pF
CL=150pF
12
15
20
25
24
30
tpHL
CL= 50pF
CL =150pF
12
15
20
25
24
30
CL= 50pF
CL =150pF
11
14
18
23
22
28
CL= 50pF
CL=150pF
11
14
18
23
13
19
tPZH
f---
RL=1k!2
tPZL
Output Disable Time
OC to any Q
Max
CL= 50pF
CL=150pF
tpHZ
~
tpLZ
RL =1 kG
CL =50pF
--
ns
ns
22
.28
- - - -~
22
ns
22
19
13
ns
tw
9
15
18
ns
Setup Time,
D before E ~
tsu
6
10
12
ns
Hold Time,
D after E~
th
4
7
9
ns
5
pF
Output Capacitance
CouT
Output Disabled
10
pF
Power Dissipation
Capacitance· (per stage)
Cpo
OC=Vcc
OC=GND
5
30
Input Capacitance
CIN
- - f-'---
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC fin.
2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
337
II
KS54Al-iCT
KS74AHCT
574
.
Octal 0-Type Flip-Flops
with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pln-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOl :; 24 mA @ VOL O.5V) for direct bus interface'
• Inputs and outputs Interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '574 consists of 8 high-speed Ootype edge-triggered
flip-flops coupled to 3-state output buffers with high drive
current capability. It can be used in implementing buffer
registers. I/O ports. bidirectional bus drivers and working
registers.
=
The flip-flops are edge-triggered on the positive transition of the clock. The 0 outputs are set to the logic levels
that were set up at the 0 inputs.
The output buffers are controlled by a common Signal (OC)
which places the outputs at a high-impedance state when
it is taken high. The OC signal does not affect the internal'
operations of the flip-flops. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL. NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to V cc and
ground.
PIN CONFIGURATION
FUNCTION TABLE
(Each Flip-Flop)
oc
Vee
10
20
30
40
20
30
40
SO
SO
60
70
80
GNO
Output
Inputs
10
60
70
SO
OC
CLK
D
Q
L
L
L
H
t
t
H
L
X
X
H
L
L
X
00
Z
ClK
LOGIC DIAGRAM
10
c8SAMSUNG
Electronics
20
30
40
SO
60
70
80
10
20
30
40
SO
60
70
338
KS54AHCT
KS74AHCT
574
Octal D-Type Flip-Flops
with 3-State Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 1,K
(V, < -0.5V or V, > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins.
±250 mA
Storage Temperature Range, T519 ... -65"C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N); -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages * , Y,N, VOUT
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may oe,eur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
V,H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V,L
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
V'N=V'H or V,L
10=-20j..lA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
V,N=V,H or V,L
10= 2O /J A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
j..IA
Maximum 3-State
Leakage Current
loz
Output Enable
=V,H
VouT=Vee or GND
±0.5
±5.0
±10.0
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
blee
V'N=Vee or GND
10uT=0/JA
per input pin
V,=2.4V
other Inputs:
at Vee or GND
10uT=Oj..lA
=8SAMSUNG
Electronics
Vee Vee -0.1
3.98
4.2
0
/J A
--
8.0
80.0
160.0
/J A
2.7
2.9
3.0
mA
339
II
KSS4AHCT
KS74AHCT
574
Octal 0-Type Flip-Flops
with 3-State Outputs·
AC ELECTRICAL CHARACTERISTICS
Characteristic
Maximum Operating
Frequency
Propagation Delay,
ClK to any
a
Output Enable Time.
OC to any
a
Output Disable Time.
OC to any
a
Symbol Condltlons t
(Input tr • tf~2 ns). AHCT574
KS74AHCT
- KS54AHCT
IT. =25 0 C
T. = -40°C to +85°C T. = -55°C to +125°C
Unit
Vee = 5.0V
Vce=5.0V±10%
Vce=5.0V± 10%
Typ
Min
35
Max
Min
Max
fmax
CL= 50pF
50
tpLH
CL= 50pF
CL=150pF
8
11
14
19
17
23
tpHL
CL= 50pF
CL=150pF
8
11
14
19
17
23
CL= 50pF
CL=150pF
11
14
18
23
22
28
CL= 50pF
CL=150pF
11
14
18
23
22
28
tPZH
r------- RL=1
kO
tPZL
tPHZ
r-------
tpLZ
RL=1 kO
CL =50pF
30
MHz
13
18
22
13
18
22
ns
ns
ns
Pulse Width,
ClK High or Low
tw
9
15
18
ns
Setup Time.
D before ClKt
tsu
9
14
17
ns
Hold Time,
Dafter CLKt
th
-3
0
0
ns
Input Capacitance
5
pF
Output Capacitance
COUT
Output Disabled
10
pF
Power Dissipation
Capacitance* (per stage)
Cpo
OC=Vcc
OC=GND
5
30
CIN
pF
2
* Cpo determines the no-load dynamic power pissipation: Po=Cpo VCC fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
340
KS54AHCT
KS74AHCT
59011591
/.
8-Bit Binary Counters wi(h
Output Registers
FEATURES
DESCRIPTION
• Choice of 3-State ('590) and Open-Drain ('591) Outputs
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL 24 rnA @ VOL 0.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices each consist of an a-bit binary counter which
feeds an a-bit register. The counter is incremented on the
rising edge of the CCK input, provided that clock enable,
CCKEN, is low. When the counter increments to the all
ones condition, ripple carry out, RCO, will go low. This
enables either synchronous cascading of the counters by
connecting the RCO of the first stage to the CCKEN of
the second, or clocking both circuits in parallel. Ripple
cascading is accomplished by connecting the RCO of the
first to the CCK of the second stage. A clear input is also
provided which will reset the counter to the all zeros state.
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
=
=
Os
Vee
OA
The output register is loaded with the contents of the
counter on the rising edge of the register clock, RCK. The
outputs of this register feed the outputs which are enabled when the enable input, G, is taken low. This enables
connection of this part to a system bus. The Q outputs of
the '590 are 3-State and those for '591 are Open-drain.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
G
RCK
CCKEN
CCK
CCLR
RCO
FUNCTION TABLE
INPUTS
FUNCTION
G
RCK
CCLR'
CCKEN
H
X
X
X
X
L
X
X
X
X
Q Outputs enable
X
X
X
Counter data is stored into register
X
X
X
Register state is not changed
X
Coun'ter clear
S
L
L
L
CCK
L
X
L
X
L
X
H
L
S
L
X
H
L
L
L
X
H
H
X
Q Outputs disable
Advance one count
No count
No count
X: Don't care
-------------------------------
RCO =
QA'· Qs' Qc' • QD' QE' • QF' QG' • QH'
(QA'
("\J
QH': Internal outputs of the counter)
c8SAMSUNG
Electronics
341
II
KS54AHCT
KS74AHCT
5901/591
/1
8-Bit Binary Counters with
Output Registers
LOGIC DIAGRAM
=8SAMSUNG
• Electronics
342
KS54AHCT
KS74AHCT
5901/591
II
8-Bit Binary Counters with
Output Registers
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
±250 mA
Vee or GND pins
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vec
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vce or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta = 25°C
f---,-'
Typ
KS74AHCT
KS54AHCT
Ta =-40°Cto +85°C,Ta =-55°Cto +125°C Unit:
I
!
Guaranteed Limits
I
I
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
Vee -0.1
3.84
Vee -0.1
3.7
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Minimum High-Level
Output Voltage
(All '590 Outputs and
~91 RCO Output)
V
VOH
VIN=VIH or VIL
10=-20JAA
10=-6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20J.lA
lo=12mA
10=24mA
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
J.lA
Maximum Output
Leakage Current
loz
Output Enable
=VIH
VouT=Vee
±0.5
±5.0
±10.0
J.lA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
JAA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Alcc
VIN=Vee or GND
10uT=OJAA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10uT=OJAA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
V
343
II
KS54AH,CT
KS74AHCT
5901591
I·
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
8-Bit Binary Counters with
Output Registers
(Input tr , tf~2 ns), AHCT590
54AHCT
54/74ACHT
KS74AHCT
Ta=25°C T.= -40°C to +85°C T.=-55°Cto +125°C
Unit
Vcc=5V±10%
Vcc=5.0V± 10%
Vcc=5V
Typical
Min
f max
50
30
Propagation Delay,
CCKt to RCO
~
15
25
29
15
25
29
Propagation Delay,
CCLR-I- to RCO
tpHL
17
28
33
Propagation Delay,
RCKt to 0
tpLH
r--tpHL
10
16
19
10
16
19
Output Enable Time,
<3-1- to Q
r------
13
18
22
13
18
22
Output Disable Time,
Gt to 0
r------
13
18
22
13
18
22
Maximum Clock Frequency
Pulse
Duration
Setup Time
tpHL
CL=50pF
tPZH
tPZL
tpHZ
CL=50pF
RL=1K!l
tpLZ
CCK or RCK
High or Low
Max
Min
10
15
20
CCLR Low
10
15
20
CCKEN-I- before
CCKt
10
15
20
6
10
10
15
20
25
tw
CCLRt before
CCKt
tsu
CCKt to
RCKttt
Input Capacitance
Output Capacitance
(0 Outputs)
CIN
COUT Output Disabled
Power Dissipation Capacitance *
Max
25
ns
ns
ns
ns
ns
ns
ns
ns
5
pF
10
pF
CPD
pF
* CPD determines the no-load dynamic power dissipation: PD=CPD VCC 2 fin.
t
For AC switching test circuits and timing waveforms see section 2.
tt This setup time ensures the register will see stable data from the counter outputs. The clocks may be tied together in
which case the register state will be one clock pulse behind the counter.
c8SAMSUNG
Electronics
344
KS54AHCT
KS74AHCT
5901591
1.
8-Bit Binary Counters with
Output Registers
AC ELECTRICAL CHARACTERISTICS
(Input t r , tf~2 ns), AHCT591
i
54AHCT
54/74ACHT
KS74AHCT
Ta=-25°C Ta = -40°C to +85°C Ta = -55°C to +125°C
Unit
Vcc=5.0V:t: 10%
Vcc=5V:t:10%
Vcc=5V
Characteristic
Symbol Conditions t
Typical
Min
Maximum Clock Frequency
f max
50
30
Propagation Delay,
CCKt to RCO
tpLH
15
25
29
tpHL
15
25
29
17
28
33
-
Propagation Delay,
CCLR.(. to RCO
Propagation Delay,
RCKt to Q
tpHL
Propagation Delay,
Gt to'Q
I
Max
25
MHz
CCK or RCK
High or Low
ns
18
31
37
10
16
19
tpHL
14
20
24
ns
tpLH
14
20
24
ns
10
15
20
CClR Low
10
15
20
CCKEN.(. Low to
CCKt
10
15
20
6
10
10
15
20
25
CClRt High to
CCKt
ns
tpHL
tpLH
Propagation Delay,
Setup Time
Min
~
<3.(. to Q
Pulse
Duration
CL =50pF
RL=1kO
Max
tw
tsu
CCKt to
RCKttt
Input Capacitance
C IN
Power Dissipation Capacitance *
Cpo
5
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin_
t
tt
For ACswitching test circuits and timing waveforms see section 2.
This setup time ensures the register will see stable data from the counter outputs. The clocks may be tied together in
which case the register state will be one clock pulse behind the counter.
c8SAMSUNG
Electronics
345
I
KSS4AHCI
KS74AHCT
592/593
8"'!Bit Binary Counters with
IhputRegisters
.
FEATURES
DESCRIPTION
• Parallel Register Inputs ('592)
• Parallel 3-State 110: Register Inputs/Counter Outputs
('593)
• Counter Has Direct Overriding Load and Clear
•
Function, pin-out, speed and drive compatibility with
54/74ALS logic family
Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(Iol 24 mA @ VOL O.5V) for direct bus interface
• lliputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '592 and '593 both contain an 8-bit register which feeds
an a-bit binary counter. The counter is incremented on the
rising edge of the CCK input, provided that clock enable,
CCKEN, is low. When the counter increments to the all
ones condition, ripple carry out, RCa, will go low. This
enables either synchronous cascading of the counters by
connecting the RCa or the first stage to the CCKEN of
the second, or clocking both circuits in parallel. Ripple
cascading is accomplished by connecting the RCa of the
first to the CCK of the second stage. A clear input is also
provided which will reset the counter to the all zeros state.
=
=
PIN CONFIGURATIONS
'593
'592
S
Vc~
A/OA
C
A
SlOB
G
C/O e
G
RCKEN
0
RCK
CCKEN
O/OD
E/O~
RCK
G
CCK
FlO,
H
CCLR
G/OG
CCKEN
CCKEN
H/OH
RCa
GNO
The '592 differs from the '593 in that the latter device has
bidirectional I input/output pins. The 3-state outputs of the
counter can be enabled and are active when enable input,
G, is taken low and input G is taken high. The outputs of
the counter then appear on the register inputs. This enables
connection of this part to a system bus. The '593 also has
a second clock enable pin, CCKEN, which is active high
and it also has an active low register clock enable, RCKEN.
Vee
F
E
The input register is loaded on the rising edge of the register
clock, RCK. The outputs of this register feed the counter.
The counter is loaded with the register's contents when
the clock load, CLOAD, input is taken low.
CCK
CCLR
CLOAO
GNO
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and qMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
RCa
FUNCTION TABLE
INPUTS '(592)
RCK
FUNCTION
CLOAD
CCLR
CCKEN
CCK
X
L
H
X
X
Register data is loaded into counter
X
H
L
X
X
Counter clear
S
H
H
X
X
The data of a thru H inputs is stored into
register
L
H
H
X
X
Register state is not changed
X
H
H
L
X
H
H
L
S
L
X
H
H
H
X
Counter advances the count
No count
No count
X: Don't car.::e_ _ _ _ _ _ _ _ _ _ _ _ _ __
RCa
QA'· Qs' Qc' • Qo' QE' • QF' QG' • QH'
(QA'rv QH': Internal outputs of the counter)
c8 !e!"SUNG
346
KS54AHCT
KS74AHCT
592/593
/.
8-Bit Binary Counters with
Input Registers
LOGIC DIAGRAMS
'592
CCiJi
(10)
~!~
~
CCK
(11)
CLOAD
RCK
*H>'
A
,..
r--
-
-v
;--
I
(13)
r--
(15)
D
---
r---<= I>C
-
(1)
B
0
~
c
>C
D
----
r---
(3)
D
r-c
-
~C
-
(4)
E
D
~ >C
-
F
D
----
r-< ~c
D
r-c ~c
~
r--
(7)
H
D
L..-.(:
I>C
~
c8SAMSUNG
Electronics
.r.
o
~~ R
L r-<
>T
--
~M
r'"""":
0
I
~
~
""
o
~ ~T
r---<:
L
1-.
---R
r~
0
r--JO
D LI-
~~
~T
R 0
-
,., o
L l-
----
~R
0
~
JO
~~
~
~~
,....t;::
"'--
LO ~T
roo--
(6)
G
L I-
10...-
r---
(5)
D
~ R a
r---
(2)
~ ~c
o
~
~
~ ~T
o
~
R
L I-
0
L..--..
r--D
L I-
I>T
R
a
"'--
ILC~T
..
r~
M
M
.
n
~~
1
-Ct:~
7""71-
~R
---a
347
1593
KS54AH.:CT 592~
KS74AHCT
I~
8~l3lt Binary Counters with"
Input Registers
LOGIC DIAGRAMS (Continued)
'593
(19)
G
G
(18)
(12)
CCLR
:~I~
CCKEN
CCKEN
(11)
(14)
CCK (13)
~
~
RCK
AlaA
(9)
IS SIMILAR IN DETAIL
0-:=-
TO THAT SHOWN FOA
CCK
-
~
(1"
J...G
(16)
(1)
I
1 '";;""""'
~
f>
Cl
~
.
(2)
BIO 8
..
C1
l~
~ r>
Cl
I.......,-
lr;-
(4)
0/00
~
-
~A
"""
~
(3)
o~t-<
~~T
l~
~ I>
ciac
R
GATING FOR RCK
~ po
C1
a
r-D
L t-
L
I ~t4>T
Cl
----
~A
'---'"
Jr;-
(6)
FI OF
-<:p> C1
I.....--...
GIOG
[r:-
(7)
I ~t-
'
4
--
'Lap> T
~A
j
a
r-;;-;: r-
~f>T
--- ---
~ PCl
HI OH
a
(8)
..oL
....
l~
L-....o po
~A
I
a
P-J
....
1
...... f -
~
~
...I
~';::::f
¢-
~~*
a
L-f-
......
1
=J
LCpT
Cl
'--
c8SAMSUNG
Electronics
~
~
'---c
--R
348
KS54AHCT
KS74AHCT
592'593
,.
8-Bit Binary Counters with
Input Registers
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Va < -0.5V or Va> Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Va < Vee +0.5V) ........ ±70 rnA
Continuous Current Through
Vee or GND pins
±250 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages·, VIN, Your .. OV to Vec
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C~ +125°C
Input Rise & Fall Times, tr , tf
.... Max 500 ns
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability ..
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V± 10% Unless Otherwise Specified)
Ta=2SoC
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +8S o C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
. VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN = VIH or VIL
lo=- 2OI-lA
lo=-6mA
Vee -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=201-lA
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
iJ A
Maximum 3-State
.Leakage Current
loz
Output Enable
=VIH
Vour=Vcc or GND
±0.5
±5.0
±10.0
I-IA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
I-IA
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
.6. Icc
VIN=VCC or GND
lour=OJ.tA
per input pin
VI=2.4V
other Inputs:
at Vec or GND
lour=OI-lA
=8SAMSUNG
Electronics
Vee Vec -0.1
4.2
3.98
0
349
I
B.-Bit Binary Counters with
Input Registers
AC ELECTRICAL CHARACTERISTICS
I
Characteristic
Symbol
KS74AHCT
KS54AHCT
Ta =25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=S.OV
Vcc=5.0V± 10%
Vcc.= 5.0V:t 10%
Typ
Min
f max
50
30
~
15
25
29
15
25
29
Maximum Clock Frequency
Propagation Delay,
CCKt to RCO
Conditions t
(Input tr , tf~2 ns), AHCT592
tpHL
Propagation Delay,
Max
Min
Max
MHz
25
15
25
29
tpHL
15
25
29
Propagation Delay.
CCLR+ to RCO
tpHL
15
25
29
Propagation Delay.
RCKt to RCO
~
18
30
36
18
30
36
CLOAD+ to RCO
Pulse
Width
Setup Time
tpLH
I---
tpHL
CCK or RCK
High or Low
CL=50pF
CL=50pF
CLOAD=GND
10
15
20
10
15
20
CLOAD Low
10
15
20
CCKEN+ before
CCKt
10
15
20
6
10
10
RCKt before
CLOADtt
10
15
20
Data A·Ht before
RCKt
10
15
20
-3
0
0
CCLR Low
CCLRt before
CCKt
Hold Time
tw
tsu
th
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
5
ns
ns
ns
ns
ns
ns
ns
pF
pF
* Cpo determines the no·load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switchirtg test circuits and timing waveforms see section 2.
tt The RCKt to
CLOAD setup time ensures that the counter will see stable data from the register output.
c8SAMSUNG
Electronics
350
KS54AHCT
KS74AHCT
5921593
I~
AC ELECTRICAL CHARACTERISTICS
Symbol Conditions t
Characteristic
Maximum Clock Frequency
f max
tPLH
Propagation Delay,
CCKt to 0
I-----
tpHL
tpLH
Propagation Delay,
CCKt to ReO
I-----
Propagation Delay,
CLOAD+ to 0
-
tpHL
Propagation Delay,
to RCO
-
Propagation Delay,
RCKt to RCO
-
CLOAD~
Pulse
Width
CL=50pF
CL=150pF
15
18
25
30
29
35
15
25
29
15
25
29
CL=50pF
29
35
tpHL
CL=50pF
CL=150pF
15
18
25
30
29
35
15
25
29
15
25
29
36
tpLH
CL=50pF
30
tpHL
CL=50pF
CL=150pF
15
18
25
30
29
35
ns
tpLH
CL=50pF
15
25
29
ns
CL=50pF
CL =150pF
13
16
20
25
24
30
CL=50pF
CL=150pF
13
16
20
25
24
30
13
20
24
13
20
24
RL=1kO
tPHZ
RL=1 kO
CL=50pF
10
15
20
10
15
20
10
15
20
6
10
10
RCKt before
CLOADtt
10
15
20
Data A-H
before RCKt
10
15
20
-3
0
0
tw
CLOAD Low
before
CCKt
to
RCKt
Hold Time
Input Capacitance
ns
30
20
before
ns
18
15
CCLR~
ns
18
10
CCKt
ns
CL=50pF
CLOAD=GND
tPLH
20
RCKEN~
MHz
29
35
15
CCLR Low
Max
25
10
CCKEN~
Setup
Time
Min
25
30
tpLz
CCK or RCK
High or Low
Max
25
30
tPZL
-
30
15
18
tPZH
Disable Time,
Min
50
15
18
I-----
G~ or Gt to·O
Typ
CL=50pF
CL =150pF
CCLRt to 0
Enable Time,
Gt or G~ to 0
KS54AHCT
KS74AHCT
T. =25°C
T.= -40°C to +85°C T.=-55°C to +125°C
Unit
Vcc=5.0V
Vee = 5.0V::t 10%
Vce=5.0V::t 10%
tpLH
tpHL
Propagation Delay,
CCLR~ to RCO
(Input tr , tf~2 ns), AHCT593
CL=50pF
CL =150pF
tPHL
Propagation Delay,
8-Bit Binary Counters with
Input Registers'
tsu
th
CIN
Output Capacitance
COUT Output Disabled
Power Dissipation
Capacitance *
Cpo
ns
ns
ns
ns
ns
ns
5
pF
10
pF
pF
2
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC fin.
t For AC switching test circuits and timing ~aveforms see section 2.
t t The RCKt to CLOAD setup time ensures that the counter will see stable data from the register output.
c8SAMSUNG
Electronics
351
I
KS54A'HCT
KS74AHCT
5951596
II
8-Bit Shift· Registers with
.Output Latches
FEATURES
DESCRIPTION
• 8-Bit Serial-In, Parallel-Out Shift Registers With
Storage.
• Choice of 3-State ('595) or Open-Drain ('596) Parallel
Outputs.
• Shift Register Has Direct Clear.
• Function; pin-out, speed and drive compatibility with
5417 4ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL = 24 mA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices each contain an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage register.
The storage register has parallel 3-state ('595) or opendrain ('596) outputs. Separate clocks are provided for
both the shift register and the storage register. The shift
register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register and storage register clocks are
positive-edge triggered. If the user wishes to connect both
clocks together, the shift register state will always be one
clock pulse ahead of the storage register.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
Vee
QA
SER
G
RCK
SRCK
SRCLR
Q'H
FUNCTION TABLE
INPUTS
FUNCTION
SER
SRCK
SRCLR
RCK
G
X
X
X
X
H
X
X
X
X
L
QA thru QH outputs enable
X
X
L
X
X
Shift register is cleared.
H
X
X
First stage of S.R: becomes "L". Other stages store
the data of previous stage, respectively.
H
X
X
First stage of S.R. becomes "H". Other stages store
the data of previous stage, respectively.
X
L
J
H
~
X
L
H
X
X
X
X
X
X
S
L
QA thru QH outputs disable
X
State of S.R. is not changed.
X
S.R. data is stored into storage register.
X
Storage register state is not changed,
X: DON'T CARE
c8SAMSUNG
Electronics
352
KS54AHCT
KS74AHCT
595'596,."
,.
8-Bit Shi,I! MMf,M,rs with
Output L.:f\J
LOGIC DIAGRAM
'595 or '596
(15)
c8SAMSUNG
Electronics
Q.
(1)
0
(2)
Oc
(3)
0
(4)
OE
(5)
OF
(9)
0,
0
II
0
353
B-Bit Shift Registers with
Output Latches
Absolute Maximum Ratings·
Supply Voltage Range Vee, .,. . . . . -0.5V to + 7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . . . .
±70 mA
Continuous Current Through
Vee or GND pins
.......... ±250 mA
Storage Temperature Range, Tsig . . . -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC fro~ 65°C to 85°C
* 'Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
Recommended Operating Conditions
Supply Voltage, Vee ............ , . 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & FaU Times, tr , tf . . . . . . . . . Max 500 ns
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS54AHCT
KS74AHCT
Ta = -40°C to +85°C Ta= - 55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Minimum High-Level
Output Voltage
(All '595 Outputs and
'596 QH' Output)
VOH
VIN=VIH or VIL
10=-20",A
10= -6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20",A
10=12mA
10=24mA
Maximum Inpur
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vec or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Ico.
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
fllcc
VIN=Vec or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
IOUT=O",A
c8SAMSUNG
Electronics
.
Vee Vee -0.1
4.2
3.98
0
354
KS54AHCT
KS74AHCT
5951596
I,
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Condltlons l
8-Bit Shift Registers with
Output Latches
(Input tr , tf~2 ns), AHCT595, AHCT596
KS74AHCT
KS54AHCT
T.=25°C
T. = -40°C to +85°C T. = - 55°C to + 125°C
Unit
Vcc=S.ov
Vcc=5.0V:t 10%
Vcc=5.0V:t10%
Typ
Propagation Delay,
SRCKt to Q'H
Propagation Delay,
RCKt to QA thru QH
Output Enable Time,
G+ to QA thru QH
('595 only)
Output Disable Time,
Gt to QA thru QH
('595 only)
~ CL=50pF
tPHl
Cl=50pF
tpLH
Cl=150pF
r---Cl=50pF
tPHl
CL=150pF
CL=50pF
CL =150pF
tPZH
r---- RL=1 kG
CL=50pF
tpzL
CL =150pF
RL= 1kG
~ CL=50pF
tpLZ
20
20
11
14
22
27
21
25
11
14
17
22
20
26
14
17
20
25
24
30
14
17
20
25
24
30
14
20
24
14
20
24
20
25
24
30
ns
20
25
24
30
ns
14
Propagation Delay,
G+ to QA thru QH
('596 only)
tpHL
CL=50pF
CL=150pF
14
SRCLR Low
Setup
Time
tw
SRCLRt to
SRCKt
SER to SRCKt
tsu
SRCKt to
RCKtt
Hold Time,
Input Capacitance
Max
17
CL=50pF
CL=150pF
Width
Min
15
tpLH
SRCK or RCK
Max
17
Propagation Delay,
Gt to QA thru QH
('596 only)
Pulse
Min
15
17
17
-
ns
-
-
10
15
20
10
1:
20
6
10
12
10
15
20
15
20
25
0
0
ns
ns
ns
ns
ns
-
th
CIN
Output Capacitance
COUT Output Disabled
Power Dissipation
Capacitance *
Cpo
-3
I---
ns
5
pF
10
pF
pF
2
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC fin.
t For AC switching test circuits and timing waveforms see section 2.
Note: The RCKt to CCKt setup time ensures that the counter will see stable data from the register output.
c8SAMSUNG
Electronics
355
II
8-Bit Shift-Registers with
Input Latches
FEATURES
DESCRIPTION
• 8-Blt Parallel Storage Register Inputs
• shift Register has Direct Overiding Load and Clear.
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '597 consists of an 8-bit storage latch feeding a
parallel-in, serial-out 8-bit shift register. Both the storage
register and the shift register have positive-edge triggered
clocks. The shift register also has direct load (from storage)
and clear inputs.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground .
Sire[ft 101
SRC
8
Vee
C
0
A
SER
SRLOAD
RCK
SRCK
SRCLR
QJ..
E
F
G
H
GND
=8SAMSU~G
Electronics
.
11
~13
356
8-Bit Shift-;R egiS fers with
Input Latches
FUNCTION TABLE
INPUTS
SER
SRCK
FUNCTION
SRCLR
SRLOAD
RCK
X
X
L
H
X
S.R. is cleared to "L"
X
X
H
J
X
Input register data is stored into S.R.
L
S
H
H
X
First stage of S.R. becomes "L". Other stages store
the data of previous stage, respectively.
H
I
H
H
X
First stage of S.R. becomes "H". Other stages stores
the data of previous stage, respectively.
X
X
X
X
X
X
X
X
X
X
X
X
State of S.R. is not changed.
..J
L
Input data on ANH line is stored into input register
Storage register state is not changed.
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vce,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
±125 mA
Storage Temperature Range, T5 1g ••• -65°C to +150°C
Power Dissipation Per Package, Pdt ..... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc
........ 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN = VIH or VIL
10=-20/AA
10= -4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
V,N = V,H or V,L
10= 2O/AA
10= 4 mA
10= 8 mA
0.1
0.26
0.39
0.1
0;33
0.5
0.1
0.4
V
Maximur,n Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/AA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/AA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.t.lee
VIN=Vee or GND
10UT=0/AA
per input pin
VI=2.4V
other Inputs:
at Vec or GND
10uT=0/AA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
357
II
KS54AHCT
KS74AHCT
59. 7
8-SitShift-Registers with
Input Latches
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr ,
tf~2 ns), AHCT597
KS74AHCT
KS54AHCT
Ta=25°C
T. = -40°C to +85°C T.=-55°Cto +125°C
Unit
Vcc=5.0V
Vee = 5.0V::t 10%
Vcc=5.0V± 10%
Typ
Min
Maximum Clock Frequency
f max
50
30
Propagation Delay,
SRCKt to Q'H
tpLH
e.-
15
17
20
tpHL
17
20
Propagation Delay,
SRLOADt to Q'H
e.-
15
14
20
tpHL
14
20
24
Propagation Delay,
SRCLRt to Q'H
tPHL
11
18
21
Propagation Delay,
RCKt to Q'H
e.-
15
25
29
15
25
29
Pulse
Width
tpLH
tPLH
tpHL
RCK or SRCK
High or Low
CL=50pF
SLOAD=Low
MHz
"
15
10
15
20
6
10
12
15
20
25
SER before
SRCKt
10
15
20
A thru H before
RCKt
10
15
20
-3
0
0
SRCLR or
SRLOAD Low
RCKt before
SRCKttt
tsu
Hold Time
th
CIN
Power Dissipation Capacitance *
Cpo
24
ns
ns
ns
ns
20
ns
ns
ns
pF
5
* Cpo determines the no-load dynamic power dissipation: PO=CPD VCC 2
t
Max
25
10
Input Capacitance
tt
Min
tw
SRCLRt before
SRCKt
Setup Time
CL =50pF
Max
pF
fin.
For AC switching test circuits and timing waveforms see section 2.
The RCKt to CCKt setup time ensures that the counter will see stable data from the register output.
c8SAMSUNG
ElectroniCS
358
KS54AHCT
KS74AHCT
64016431645
/1
II
Octal Bus Transceivers
with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pilH)ut, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL 24 mA @ VOL 0_5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4_5V to 5_5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -:-40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & ~eel), standard DIPs.
These high-speed octal/bus transceivers are designed for
asynchronous two-way communication between data
buses. A direction control input (DIR) controls the flow
direction of data. When DIR is high, data flows from the
A inputs to the B outputs. When DIR is low, data flows from
B to A. The '643 transfers inverted data from the A bus
to the B bus and non-inverted data from the B bus to the
A bus. The '640 transfers inverted data in both directions.
=
=
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interlace with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps. to V cc and
ground.
DIR
Vee
A1
G
A2
81
A3
82
A4
63
A5
84
A6
85
A7
86
A8
67
GND
88
=8SAMSUNG
Electronics
a
FUNCTION TABLE
PIN CONFIGURATION
Control
Inputs
Operation
G
OIR
'640
'643
'645
L
L
Inverted data
transmitted from
Bus B to Bus A
Data transmitted
from Bus B
to Bus A
Data transmitted
from Bus B
to Bus A
L
H
Inverted data
transmitted from
Bus A to Bus B
Inverted data
transmitted from
Bus A to Bus B
Data transmitted
from Bus A
to Bus B
H
X
Buses isolated
(High-impedance
state)
Buses isolated
(High-impedance
state)
Buses isolated
(High-impedance
state)
359
'1645:
/1
KS54ANQtt~Lf'OI/643'
KS74AHc::n~:K~~
,/1
Octal Bus Transceivers
with 3-State Outputs
LOGIC DIAGRAMS
'640
'643
'645
Absolute Maximum Ratings·
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI> Vee +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +O.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ... , ..... ±70 mA
Continuous Current Through
Vee or GND pins ................ ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Powet Dissipation Per Package, Pdt ...... 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operatiQn
of the device at or beyond them is not implied. Lc>ng.exposure to these conditions may affect device reliability.
c8sAIUISUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
\
Supply Voltage, Vee .............. 4.5V to 5.5V
DC Input & Output Voltages *, VIN, Vour . . OV to Vee
Operating Temperature
KS74AHCT:-40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
360
64016431645
/l
/'l
KS54AHCT
KS74AHCT
DC ELECTRICAL CHARACTERISTICS
Characteristic
Tlamce;vers
(Vcc=5V± 10% Unless Otherwise Specified) ,
KS74AHCT
KSS4AHCT
T.= -40°C to +85°C T.= -55°C to +125°C Unit
T. =2S O C
Symbol Test Conditions
OctalfM~i
with 3-StMe'!Outputs
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN = VIH or VIL
lo=-20",A
lo=-6mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20",A
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vcc or GND
±0.5
±5.0
±10.0
J.lA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
2.7
2.9
3.0
Additional Worst
Case Supply
Current
6 1cC
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
lour=OJ.lA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
lour = OJ.lA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlonat
KS54AHCT
KS74AHCT
T. =25°C
T. = -40°C to +85°C T.:: -55°C to +125°C
Vee=5.0V
Vec=5.0V:!: 10%
Vee =5.0 V:!: 10%
Min
Max
Min
tpLH
12
17
14
20
tpHL
CL=50pF
CL=150pF
7
10
12
17,
14
20
CL=50pF
CL=150pF
12
15
20
25
25
31
CL=50pF
CL =150pF
12
15
20
25
25
31
tPZH
Output Disable Time.
G to A or B
~ RL=lkO
tPZL
tpLZ
ns
ns
13
18
22
CL=50pF
13
18
22
10
pF
5
30
pF
5
CIN
Output Capacitance
CouT
Output Disabled
Power Dissipation
Capacitance •
Cpo·
G=Vcc (per stage)
G=GND
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 1
t For AC switching test circuits and timing waveforms see section 2.
"qsSAMSUNG
Electronics
Unit
Max
7
10
t - - - - RL=lkO
Input Capacitance
mA
CL=50pF
CL =150pF
Output Enable Time.
GtoAorB
J.lA
(Input tr • tf~2 ns), AHCT640. AHCT643
Typ
Propagation Delay.
A to B. or B to A
i
'.
fin.
ns
pF
I
KS54AHC,~'~840/643/645
KS74AHCT
AC ELECTRICAL CHARACTERISTICS
Characteristic
Octal Bus. Transceivers
with 3-State Outputs
'
Condltlons t
Symbol
(Input tr , tf~2 ns), AHCT645
T. =25°C
T.
Vee = 5.0V
Typ
Propagation Delay,
A to B, or B to A
Output Enable Time
G to A or B
Output Disable Time,
GtoAorB
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance *
KS74AHCT
KS54AHCT
+85°C T. -55°C to +125°C
Unit
Vee=5.0V±10%
Vee=5.0V± 10%
= -40°C to
Min
=
Max
Min
Max
tpLH
CL=50pF
CL=150pF
6
9
10
19
14
25
tPHL
CL=50pF
CL=150pF
6
9
10
19
14
25
CL=50pF
CL=150pF
12
18
20
29
25
36
CL=50pF
CL =150pF
12
18
20
29
25
36
RL=1kO
CL=50pF
13
18
22
13
18
22
5
pF
Output Disabled
10
pF
§=Vcc (per stage)
G=GND
5
30
tPZH
f---
RL=1kO
tPZl
tpHZ
f---
tpLZ
CIN
COUT
Cpo*
* Cpo determines the no· load dynamic power dissipation: Po=Cpo VCC
ns
ns
ns
pF
l
fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
,I
362
:~
KS54AHCT
KS74AHCT
646·/648
I~
Octal 3-State Bus Transceivers
with Registers
FEATURES
DESCRIPTION
•
•
•
•
The '646 and '648 are bi-directional bus transceivers with
Ootype flip-flops and control circuitry to facilitate high speed
multiplexed data transmission. The '646 transmits true data
and the '648 transmits inverted data.
•
•
•
•
•
•
8 bi-directional data paths
Transmits direct or stored data in either direction
24-pin slim DIP package
Function, pin-out, speed and drive compatibility with
54/74ALS logic family
Low power consumption characteristic of CMOS
3-State outputs with high drive current
(loL =24 mA @ VOL =O.5V) for direct bus interface
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.SV
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54HACT: -55°C to + 125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
Oata can be transmitted directly from one port to the other
in either direction. It also can be stored in the flip-flops from
either or both ports for subsequent transmission to the opposite port. Six control inputs govern the data flow:
G
OIR (direction control) disables A or S outputs permitting the pins to be used as inputs thus determining the direction of a data flow. When
OIR=high, data flows from A to S.
SAS,SSA (data source AS and SA) determines whether
data transmitted is from the data inputs or the
registers associated with those inputs.
PIN CONFIGURATION
(21) (3)
CAB
Vee
CBA
OIA
SBA
Al
G
A2
Bl
A3
82
A4
83
A5
84
A6
B5
A7
86
A8
87
GNO
88
(1)
(23)
(2)
(22)
G OlA CAB CSA SAS SBA
L
X
X
X
CAS,CSA (Clock AS and SA) clocks data from the A inputs and the S inputs, respectively, into their
associated registers. Since the clocks are not
gated with the G and DIR pins, data at the A
and S pins can be clocked into the flip-flops
at any time.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
'lilow direct interface with TIL, NMOS and CMOS devices
without any external components ..
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
(21) (3)
G
H
L
(1)
(23)
(2)
(22)
OlR CAB eBA SAB SBA
X
X
L
X
(21) (3)
G
X
Real-Time transfer
bus A to bus B
c8SAMSUNG
Electronics
(1)
(23)
(2)
(22)
OlA CAB eSA sAB SBA
X
t
X
X
X
x x
H
Real·Time transfer
bus B to bus A
(output enable) when high, all outputs are
disabled, isolating the A and S ports. When
low, one port is enabled at a time as determined by the OIR pin.
X
X
Storage from
A AND/OR B
x
x
x
(21) (3)
G
(1)
(23)
(2)
(22)
DIA CAB CBA SAB SBA
H
x
x
X
X
X
H
H
x
Transfer stored data
to A AND/OR B
363
II
KS54AHC;17~\B;461648
KS74AHCT
II
Octal :3-State Bus Transceivers
with Registers
FUNCTION TABLE
Inputs
G DIR
CAB
CBA
X X
X X
t
X
X
t
Data 110·
SAB SBA A1 thruA8
X
X
X
X
X
X
X
H or L
X
X
X
X
L
H
H
H
X
t
t
X H or L H or L
L
L
L
L
L
L
H
X
H H or L
X
X
X
Operation or Function
B1 thru B8
input
input'
Not specified Not !specified
'646
'648
Store A, B unspecified
Store B, A unspecified
Store A, B unspecified
Store B, A unspecified
Store A and B data
Isolation, hold storage
Store A and B data
isolation, hold storage
Input
Input
L
H
Output
Input
Real-Time B data to A bus Real-Time B data to A bus
Stored B data to A bus Stored B data to A bus
X
X
Input
Output
Real-Time A data to B bus Real-Time A data to B bus
Stored A data to B bus
Stored A data to B bus
X
"The data output functions may be enabled or disabled by various signals at the Gand DIR inputs. Data input functions are always enabled,
ie., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
LOGIC DIAGRAMS
'646
DIR
(3)
(21)
SAB
-0.
SBA
- Vee +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins ................ ±250 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage. Vee
.......... 4.5V to 5.5V
DC Input & Output Voltages·. VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fa" Times. tr • tf . . . . . . . . . Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logiC
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of. the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
Minimum High-Level
Input Voltage
VIH
Maximum Low-Level
Input Voltage
VIL
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Vce -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.4
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20jAA
10=-6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20jAA
10=12mA
10=24mA
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
jAA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VOUT=VCC or GND
±0.5
±5.0
±10.0
jAA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
Additional Worst
Case Supply
Current
.t.lcc
VIN=VCC or GND
lOUT=OjAA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT-0,..A
c8SAMSUNG
Electronics
Vec Vcc -0.1
3.98
4.2
0
0.1
jAA
~
2.7
2.9
3.0
I---
mA
365
I
KS54AHCT~,'
KS74AHCT
6461648
'I' .,
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditionst
Oct., 3-$tilt,Bus Transceivers
with Registers·'
(Input tr , tt<2 ns), AHCT646, AHCT648
KS74AHCT
KS$4AHCT
T. =2SOC
T•• -40·C to +8SOC T.= -5SOC to +125°C
Vcc-S. OV
Un"
Vcc=S.OV~ 10%
Vcc·S.OV~10%
Typ
Maximum
Frequency
Propagation Delay,
A or B Input to
B or A Output
Propagation Delay,
CBA or CAB Input to
A or B Output
Propagation Delay, t t
SBA or SAB Input to
A or B Output
(with A or High)
Propagation Delay, t t
SBA or SAB Input to
A or B Output
(with A or Low)
Max
Min
Max
f max
CL=50pF
45
30
25
MHz
tPLH
CL=50pF
CL=150pF
11
14
18
23
22
28
ns
tpHL
CL=50pF
CL=150pF
11
14
18
23
22
28
tpLH
CL=50pF
CL=150pF
15
18
25
30
30
36
tpHL
CL=50pF
CL =150pF
15
18
25
30
30
36
tpLH
CL=50pF
CL=150pF
16
19
27
33
32
38
tPHL
CL=50pF
CL =150pF
16
19
27
33
32
38
tpLH
CL-50pF
CL=150pF
15
18
25
30
30
36
tpHL
CL=50pF
CL""150pF
15
18
25
30
30
36
14
17
14
17
22
27
22
27
26
32
26
32
13
22
26
13
22
26
tPZH
Out Enable Time,
or DIR Input to
A or B Output
f------
Output Disable Time,
G or DIR Input to
A or B Output
f------
a
Min
RL=lkO
CL=50pF
CL=150pF
tPZL
tpHZ
tpLZ
CL=?OpF
CL=150pF
RL=lkO
CL=50pF
ns
\
ns
ns
ns
ns
Pulse Duration, Clocks
High or low
tw
8
12
15
ns
Set up Time, A before CABt
or B before CBAt
tsu
8
12
15
ns
Hold Time, A after CABt
or B after CBM
th
0
0
0
ns
Input Capacitance
5
CIN
Output Capacitance
COUT
Power Dissipation
Capacitance ..
Cpo
Output Disabled
10
pF
pF
pF
.. Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 1 fin.
t For AC switching test circuits and timing waveforms see section 2.
t t These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
c8SAMSUNG
Electronics
366
KS54AHCT
KS74AHCT
6511652
II
Octal 3-State SC!s Transceivers
with Registers
FEATURES
DESCRIPTION
• Independent Registers and Enables for A and B Buses
• Multiplexed Real-Time and Stored-Data
• Choice of Tim'e and Inverting Data Paths
Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(I0L 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices consist of bus transceiver circuits. D·type
flip· flops, and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the
internal storage registers. Enable GAB and GBA are pro·
vided to control the transceiver functions. SAB and SBA
control pins. are provided to select whether real· time or
stored data is transferred. A low input level selects realtime data, and a high selects stored data. The following
examples demonstrate the four fundamental busmanagement functions that can be performed with the octal
bus transceivers and registers.
=
=
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by low-to-high transitions at the appropriate clock pins (CAB or CBA) regardless of the select
or enable control pins. When SAB and SBA are in the realtime transfer mode, it is also possible to store data without
using the internal D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration each output reinforces its input. Thus, when all other data sources to the
two sets of bus lines are at high impedance, each set of
bus lines will remain at its last state.
PIN CONFIGURATION
CAB
Vee
SAB
CBA
GAB
SBA
Al
GBA
A2
Bl
A3
B2
A4
B3
A5
B4
A6
B5
A7
A8
B6
B7
GND
B8
(3) (21) (1) (23) (2) (22)
GAB GBA CAB eSA SAS SSA
X
X
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS apd CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
(3) (21) (1) (23) (2) (22)
GAB GSA CAB eSA SAB SBA
H
H
X
X
(3) (21) (1) (23) (2) (22)
GAB GBA CAB eBA SAB SBA
X
X
t
X
X
X
X
X
t
X
H
Real-Time transfer
bus B to bus A
Real-Time transfer
bus A to bus B
c8SAMSUNG
Electronics
X
Storage from
A AND/OR B
x
(3) (21) (1) (23) (2) (22)
AB GBA CAS CBA SAB SSA
x
H
X
H
H
x
Transfer stored data
TO A AND/OR B
367
I
KS54A_~.·,,'
',.·~.1'
KS74AH.'
1652 .
, ., /1
Ogtal 3·Stat,~,ljIMs ,rr,anscei'vers
with Registers
.
.. 2-
FUNCTION TABLE
INPUTS
GABGBA CAB
DATAI/O·
OPERATION OR FUNCTION
CBA SABSBA A1'THRU A8 B1 THRUB8
L
L
H H or L H or L X
t
t
X
H
X
H
H
H
t
t
L
L
X
L
Hor L
t
t
t
L
L
H
H
L
L
H
H H
H
L
'651
'652
Isolation
Store A and B Data
X
X
Input
Input
Isolation
Store A and B Data
H or L X
X
t
X" X
Input
Input
Not specified
Output *
Store A, Hold B
Store A in both registers
Store A Hold B
Store A in both registers
Inpuf
Input
Hold A, Store B
Store B in both registers
Hold A, Store B
Store B in both registers
X
X H
X
or L
X
X
X Not specified
X**
Output *
X
X
or L X
X
L
X
H
L
H
X
X
H or L H or L H
H
Output
Input
Input
Output
Output
Output
Real-Time B Data to A Bus Real-Time B Data to a Bus
Stored B Data to A Bus
Stored B Data to A Bus
Rea.l-Time A Data to B Bus Real-Time A Data to B Bus
Stored A Data to Bus
Stored A Data to B Bus
Stored A Data to B Bus and Stored A Data to B Bus and
Stored B Data to A Bus
Stored B Data to A Bus
* The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions
are always enabled, ie., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
* * Select control=L: clocks can occur simultaneously
Selectcontrol=H: clocks must be staggered in order to load both registers
LOGIC DIAGRAMS
'651
'652
GBA-=~--<[>""1
GBA -="-----4:>--.
GAB-=----1>-~----------------,
GAB~---~>-~-----------------'
CBA~~------~--------~~----_h
CBA~~------~--------~~-----h
SBA~~------~~~~~
SBA-=~------~~O-~~
CAB
CAB
SAB~--_+--~~~~
SAB~---+--~~~~
I
:,(20)
+-+-+-'-- B1
A1--+-t-+...
I
I
I
..J
~----~----~vr----------J
TO 7 OTHER CHANNELS
c8SAMSUNG,
Electrpnics .
~----~----~vr-----------J
TO 7 OTHER CHANNELS
368
KS54AHCT
KS74AHCT
6511652
Octal 3-State Bus Transceivers
with Registers
Absolute Maximum Ratings*
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -:-0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±70 mA
Continuous Current Through
. Vec or GND pins .............. " ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating' Conditions
Supply Voltage, Vee .............. 4.5V to 5.5V
DC Input & Output Voltages * , VIN, Vour .. OV to Vee
Operating Temperature'
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation .
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test.Conditions
(Vee=5V±10% Unless Otherwise Specified)
T. =25°C
Typ
KS54AHCT
KS74AHCT.
T.= -40°C to +85°C T.= -55°C to +125°C Unit
Guaranteed limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum' Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIHor VIL
10=-20JlA
lo=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20JlA
10=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
JlA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vee or GND
±0.5
±5.0
±10.0
fiA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
JlA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
ll.lee
VIN=Vee or GND
lour=OJlA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour = OJlA
c8,SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
~
369
II
KS54AHCT
-KS74AHCT
651"1652
AC ELECTR,CAL CHARACTERISTICS
.Chlrlcterlstlc
Symbol
Condltlons t
Octal 3-8tate Bus· Transceivers
with Registers
(Input tr , tf"";2 ns), AHCT651, AHCT652
1(S74AHCT
KS54AfofCT
T.=25°C
T. = -40°C to +85°C T.=-55°Cto +125°C
Unit
Vcc=5.0V
Vcc=5.0V± 10%
Vcc=5.0V±10%
Typ
Min
f max
CL=50pF
45
30
Propagation Delay,
A or B Input to
B or A Ouput
tpLH
CL=50pF
CL=150pF
11
14
18
23
22
28
tpHL
CL=50pF
CL=150pF
11
14
22
28
Propagation Delay,
CSA or CAB Input to
A or· B Output
tpLH
CL=50pF
CL=150pF
30
36
tpHL
CL=50pF
CL =150pF
15
18
15
18
18
23
25
30
25
30
30
36
Propagation Delay,
SSA or SAB Input to
A or B Output
(with A or B High)
tpLH
CL=50pF
CL :;150pF
16
19
27
32
32
38
tpHL
CL=50pF
CL=150pF
16
19
27
32
32
38
Propagation Delay,
SSA or SAB Input to
A or B Output
(with A or BLow)
tpLH
CL=50pF
CL =150pF
15
18
25
30
30
36
tpHL
CL=50pF
CL=150pF
15
18
25
30
30
36
Output Enable Time,
GSA to A or
GAB to B
tPZL
-
CL=50pF
CL=150pF
19
22
32
37
38
44
CL=50pF
CL =150pF
19
22
32
37
38
44
Output Disable Time,
GSA to A or GAB to B
-
13
22
26
13
22
26
Clock Frequency
AL=1kO
tPZH
tpHZ
tpLZ
AL=1 kO
CL=50pF
Max
Min
MIx
MHz
25
ns
ns
ns
ns
ns
ns
Pulse Width Clocks
High or Low
tw
8
12
15
ns
Setup Time, A before CABt
or B before CBAt
tsu
8
12
15
ns
Hold Time, A after CABt
or B after CBAt
th
a
0
0
Maximum Input Capacitance
maximum Output
Capacitance
Power Dissipation
Capacitance *
CIN
COUT Output Disabled
,
ns
5
pF
10
pF
Cpo
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t.~or AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
370
1659
KS54A.HCT 658~
KS74AHCT
/1
Octal Bus Transceivers
with Parity
FEATURES
DESCRIPTION
• Bus Transceivers with Inverting Outputs('658) or True
Outputs ('659)
?• Generates a Parity Bit for A Bus and B Bus
• Easily Cascadab/e
• Internal Active Pull-Ups and Pull-Downs
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(/ol
24 mA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These octal bus transceivers are designed for asynchronous, bidirectional communication between data
buses. The devices transmit data from the A Bus to the
B Bus, or from the B Bus to the A Bus, depending on the
levels at the direction control inputs, GAB and GBA. These
devices a/so generate parity outputs. APO and BPO, which
reflect the number of high levels at the A Bus and B Bus,
respectively, taking into account the parity inputs API and
BPI.
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
=
GAB
Vee
A1
A2
GBA
The bidirectional/IO ports feature active circuits on the input
stage that, when the output shar.ed by that pin is disabled,
will maintain the input in the last state taken by the output.
This state will be maintained until changed by activity on
the bus. The advantage of this arrangement is that when
all outputs on the bus are disabled, the inputs will be
prevented from floating, resulting in minimum power dissipation and minimum susceptibility to noise. This eliminates
any need for external pull-up or pull-down resistors. The
parity inputs API and BPI have similar circuits.
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
BPI
B8
BPO
API
GND
APO
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
CONTROL
INPUTS
GBA
GAB
L
L
H
H
L
H
L
H
NUMBER OF HIGH
INPUTS ON
A BUS AND API
NUMBER OF HIGH
INPUTS ON
B BUS AND BPI
X
D, 2, 4, 6, 8
Z
H
X
1, 3, 5, 7, 9
Z
L
0, 2, 4, 6, 8
X
H
Z
1,3,5,7,9
X
L
Z
Z
X
X
X
0, 2, 4, 6, 8
X
. 1, 3, 5, 7, 9
OUTPUTS
APO BPO
'658
'659
B Data to A Bus
B Data to A Bus
A Data to B Bus
A Data to B Bus
Isolation
Isolation
8 Data to A Bus,
A Data to B Bus
B Data to A Bus,
A Data to B Bus
H
L
0, 2, 4, 6, 8
X
H
1, 3, 5, 7, 9
X
L
c8SAMSUNG
Electronics
Z
OPERATION
371
II
KSS4AHCT
KS74AHCT
6581659
II,
Octal Bus Transceivers'
with Parity
LOGIC DIAGRAM
GBA
GAB
(23)
(1)
L-t>
....... i ) v
T .....
....... I.,)
.......
.....
-
-
!---~~-~~~J
.....
:
A1 __~(2~)__________~~~~
I
h
~~ ~ht-:..J...
(3)
'659
v
~
'658
TG
_
1
--'659
: __~__________
(22)
~~
~~
L _ .... ~~51!... _ _ _ _ ~ ___ .... _ j
A2--~--------~~--~
A3--~(4~)--------~-+__~
A4--~(5~)------~~-+__~
A5--~(6~)-----'4-~-+--~1
A6--~(7~)--~-+4-~-+__~
A7--~(8~}--~~~1-~r---~1
A8 __~(9~).-~~+-~-+~~1
B1
I
:
(21)
(20)
(19)
(18)
(17)
(16)
(15)
~--~~--------~~ B2
7 INVERTING (NONIVERTING FOR '659)
CHANNELS IDENTICAL TO CHANNEL
1 ABOVE
I
B3
B4
B5
B6
B7
B8
(13)
APO
(10)
BPI
Absolute Maximum Ratings*
Supply Voltage Range Vcc, ' ...... -0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +O.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±70 mA
Continuous Current Through
Vcc or GND pins. , ...... '
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device, reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
' .... , ... 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf ...... .
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
372
KS54AHCT
KS74AHCT
6581/659
/l
Octal Bus Transceivers
with Parity
DC ELECTRICAL CHARACTERISTICS
Chafacteflstlc
Symbol Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
KS74AHCT
KS54AHCT
T.= -40°C to +85°C T.= -55°C to +125°C Unit
T. =25°C
Typ
Guafanteed Limits
Minimum High-Level
Input Voltage
V,H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V,L
0.8
0.8
0.8
V
Vcc -0.1
3.84
Vec -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
flA
±0.5
±5.0
±10.0
flA
8.0
80.0
160.0
flA
2.7
2.9
3.0
mA
Minimum High-Level
. VOH
Output Voltage
V'N=V'H or V'L
lo=- 2OflA
10= -6mA
V,N=V,H or V,L
lo=20flA
lo=12mA
lo=24mA
Vee Vcc -0.1
4.2
3.98
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
hN
V'N=VCC or GND
Maximum 3-State
Leakage Current
loz
Output Enable
.. =V,H
VOUT=VCC or GND
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
~Icc
0
V'N=VCC or GND
10uT=OflA
per input pin
V,=2.4V
other Inputs:
at Vcc or GND
louT=OflA
-
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input t r, tf~2 ns) AHCT658· AHCT659
KS54AHCT
KS74AHCT
T. =25°C
T. = -40°C to +85°C T.=-55°Cto +125°C
Unit
Vee = 5.0V
Vee=5.0V:t 10%
Vee=5.0V±10%
Min
Typ
Propagation Delay,
AorBtoBorA
Propagation Delay,
API or BPI to APO or Bf:'O
Enable Time, GABor
GBA to APO or BPO
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance *
Max
18
23
22
28
CL=50pF
CL =150pF
CL=50pF
CL =150pF
11
14
16
19
18
23
27
32
22
28
32
38
tpHL
CL=50pF
CL=150pF
CL=50pF
CL =150pF
27
32
18
23
32
38
tpLH
16
19
11
14
tpHL
CL=50pF
CL =150pF
11
14
18
23
22
28
CL=50pF
CL =150pF
16
19
27
32
32
38
CL=50pF
CL =150pF
16
19
16
27
32
27
32
38
32
tpHZ
16
27
32
C,N
5
tpLH
tPZH
I----
RL=1kO
tPZL
Disable Time, GAB or
GBA to APO or BPO
Min
11
14
tPHL
Propagation Delay,
A or B to APO or BPO
Max
CL=50pF
CL =150pF
tpLH
RL=1kO
~ CL=50pF
ns
ns -
ns
ns :
pF
pF
COUT
pF
Cpo
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC
22
28
ns
2
fin.
t For AC switching test circuits and timing waveforms see section ~.
c8SAMSUNG
Electronics
373
II
KS54AHCT
KS74AHCT
6641665
/1
Octal Sus. Transceivers
with Parity
FEATURES
DESCRIPTION
• Bus Transceivers with Inverting Outputs ('664) or True
Outputs ('665)
• Generates a Parity Bit for A Bus and B Bus
• Easily Cascadable
• Internal Active Pull-Ups and Pull-Downs
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
..
• low power consumption characteristic of CMOS
• 3·State outputs with high drive current
(IOL 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMO~
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These octal bus transceivers are designed for asynchronous, bidirectional communication between data
buses. The devices transmit data from the A Bus to the
B Bus or from the B Bus to the A Bus, depending on the
level at the direction control input, DIR. The enable input~
G, can be used to disable the device so that the buses
are isolated. These devices will also generate parity outputs, APO and BPO, which reflect the number of high levels
at the A Bus and B Bus, respectively, taking into account
the parity inputs API and BPI.
=
=
These devices provide $peeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CNlOS devices
without any external components.
·PIN CONFIGURATION
DIR
Vee
A1
G
A2
91
A3
82
A4
83
A5
84
A6
85
A7
86
A8
87
8PI
BPa
88
API
GND
APO
The bidirectional I/O ports feature active circuitry on the
input stage that, when the output shared by that pin is
disabled, will maintain the input in the last state taken by
the output. This state will be maintained until changed by
the activity on the bus. The advantage of this arrangement
is tht when all outputs on the bus are disabled, the
inputs will be prevented from floating, resulting in minimum
power dissipation and minimum susceptibility to noise. This
eliminates any need for external pull-up or pull· down
resistors. The parity inputs API and BPI have similar circuitry.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground. -,
FUNCTION TABLE
CONTROL
INPUTS
G
DIR
L
L
L
H
H
X
NUMBER OF HIGH
INPUTS ON
A BUS AND API
NUMBER OF HIGH
INPUTS ON
BBUS AND BPI
OUTPUTS
APO
BPO
X
0, 2, 4, 6, 8
Z
H
X
1,3,5,7,9
Z
L
0, 2, 4, 6, 8
X
H
Z
1,3,5, 7, 9
X
L
Z
X
X
Z
Z
=8SAMSUNG
Electronics
OPERATION
'665
'664
B Data to
A Bus
B Data to A Bus
A Data to
B Bus
A Data to B Bus
Isolation
Isolation
374
KS54AHCT
KS74AHCT
664/665
/1
Octal Bus Transceivers
with Parity
LOGIC DIAGRAM
DIR;_~(1.!...1-----.:=---n~+___--lL......l
r-,;..------------ -1
I
A1
(2)
(22)
B1
----- Vee +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vce +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo< Vee .f-0.5V) .
±70 mA
Continuous Current Through
Vee or GND pins ................ ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
... 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c5!SAMSUNG
• • Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc .............. 4.5V to 5.5V
DC Input &' Output Voltages *, VIN, VOUT . . OV to Vce
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHC~ -55°C~ +125°C
Input Rise &' Fall Times, tr , tf ' . , , .... , Max 500 ns
Unused inputs must always be tied to an appropriate .logic
voltage level (either Vee or GND)
375
I
Octal Bus'Transceivers
with Parity
DC ELECTRICAL CHARACTERISTICS
(Vce=,5V± 10% Unless Otherwise Specified)
,',
Characteristic
Symbol Test Conditions
T. =25°C
KS74AHCT
KS54AHCT
T.= -40°C to +85°C T.= -55°C to +125°C Unit
Guaranteed, Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10= -6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vec or GND
±0.1
±1.0
±1.0
/.lA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
/.lA
Maximum Quiescent
Supply Current
lee
8.0
80.0
160.0
/.lA-
2 ..7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
Alee
VIN=Vce or GND
10UT=0",A
per. input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
c8PIUISUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
376
KS54AHCT
KS74AHCT
664/6:65
,
'
Octal Bus Tran$celvers
with Parity
AC ELECTRI,CAl CHARACTERISTICS
Characteristic
(Input tr , t,<2 ns), AHCT664, AHCT665
KS74AHCT
KS54AHCT
T. =25°C
T." -40°C to +85°C T... -55°C to,+ 125°C
Unit
Vcc= S.OV
Ycc=S.OV:i:10%
Vcc=S.OV:i:10%
Symbol ,Conditions t
Typ
Propagation Delay,
AorBtoBorA
Propagation Delay,
A or B to APO or BPO
Propagation Delay,
API or BPI to APO or BPO
Output Enable Time,
GtoAorB
Output Enable Time,
DIR to A or B
Input Capacitance
MIx
tpLH
22
28
ns
tpHL
CL=5OpF
CL=150pF
11
14
18
23
22
28
ns
tpLH
CL=5OpF
CL=150pF
16
19
27
32
32
38
ns
tpHL
CL=50pF
CL=150pF
16
19
27
32
32
38
ns
tpLH
CL=5OpF
Cl=150pF
11
14
18
23
' 22
28
ns
tpHL
CL=5OpF
CL =150pF
11
14
18
23
22
28
ns
CL=5OpF
CL=150pF
16
19
27
32
32
38
ns
C~=5OpF
16
19
27
32
32
38
ns
tpzH
'~
'h
RL~1kO
tpHZ
tpLZ
CL=150pF
tPZH
-
RL=lkO
tPHZ
tpLZ
t---
\
16
27
32
ns
16
27
32
ns
CL=50pF '\
CL=150pF'
16
19
27
32
32
38
ns
CL=5OpF
CL=150pF
16
19
27
32
32
38
ns
16
27
32
ns
16
27
32
ns
RL=lkO
CL=5OpF
tPZL
Output Disable Time,
DlR tt> A or B
Min
18
23
-
MIx
11
14
tPZL
Output Disable Time,
GtoAorB
Min
CL=5OpF
CL=150pF
RL=lkO
CL=5OpF
GIN
Output Capacitance
COUT Output Disabled
Power Dissipation
Capacitance *
Cpo
pF
5
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC
pF
pF
2
fin,
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
377'
II
~S54AHCT··610
KS74AHCT ... ,
4-Sy-4 Register Files
with 3-State Outputs
FEATURES
DESCRIPTION
·Seperate Read Write
Addressing Permits Simultaneous Reading and
Writing
• Expandable to 512 Words of 7-bits
• For use as:
- Scratch pad memory
- Buffer Storage between processors
- Bit storage in fast multiplication designs
The '670 is a 16-bit 3-State Register File organized as 4
words of 4 bits each. Separate Read and Write Address
and enable inputs are available, permititng simultaneous
writing into one word location and reading from another
location. The 4-bitword to be stored Is presented to four
Data inputs. The Write Address inputs (W A and We) determine the location of the stored word. When the Write
Enable (Gw) input is LOW, the data is entered into the addressed location. The addressed location remains
transparent to the data while the Gw is 'LOW. Data supplied at the inputs wiH be read out in true (non-inverting)
form from the 3-State outputs. Data and Writ~ Address inputs are inhibited when Gw is HIGH.
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with drive current
(IOL = 24 mA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range:. 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
02
03
04
RB
Direct acquisition of data stored in any of the four registers
is made possible by individual Read Address inputs (R A
and Rs). The addressed word appears at the four outputs
when the Read Enable (GR) is LOW. Data outputs are in
the HIGH impedance "off" state when the read enable
input is HIGH. This permits outputs to be tied together to
increase the word capacity to very large numbers.
Up to 128 devices can be stacked to increase the word
size to 51 2 locations by tying the 3-State outputs together.
Since the limiting factor for expansion is the output HIGH
current, further stacking is possible by tying pull-up resistors
to the outputs to increase the 10H current available. Design
of the read enable signals for the stacked devices must
ensure that there is no overlap in the LOW levels which
would cause more than one output to be active at the same
time. Parallel expansion to generate n-bit words is accomplished by driving the enable and address inputs of
each device in parallel.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
R~
04
03
GNO
FUNCTION TABLES
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
WRITE MODE SELECT TABLE
READ MODE SELECT TABLE
OPERATING
MODE
Write Data
Data
Latched
INPUTS
OW
Dn
INTERNAL
LATCHESCe)
L
L
L
H
L
H
H
X
no change
NOTE:
a. The Write Address (WA and We) to the "Internal
latches" must be stable while Ow is LOW for conventional operation.
c8SAMSUNG
Electronics
.
INPUTS
OPERATING
MODE
OUTPUT,
On
GR
INTERNAL
LATCHESlb)
Read
L
L
L
H
L
H
Disabled
H
H
(Z)
NOTE:
b. The selection of the "internal latches" by Read Address
(RA and Rs) are not constrained by Gw or GR
operation.
378
KS54AHCT
KS74AHCT
670
4-8y-4 Register Files
with 3-State Outputs
LOGIC DIAGRAM
I
Absolute Maximum Ratings*
Supply Voltage Range Vee •........ -0.5V to +7V
DC Input Diode Current. 11K
(V, < -0.5V or V, > Vee +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
...... ±250 mA
Storage Temperature Range. Tstg ... -65°C to :+-150°C
Power Dissipation Per Package. Pdt
500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to' the device may occur.
These are stress ratings only .and functional operation
of the device at or beyond them is not implied. Long ex- .
posure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vee
4.5V to 5.5V
DC Input & Output Voltages·. ViN. VOUT
OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times. tr • tt ..
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
379
67'0
4-By~
Register File$ ,
with 3-State 'Outputs
KS54AHCT
KS74AHCT· ' '
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
T. =2S O C
Typ
Minimum High-Level
Input Voltage
Maximum Low-Level
Input Voltage
VIH
VIL
Minimum High-Level
Output Voltage
VOH
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
hN
Maximum 3-State
.Leakage Current
loz
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
I
61ee
VIN=VIH or VIL
lo=-20lAA
lo=-6mA
VIN=VIH or VIL
lo=20,..A
lo=12mA
lo=24mA
VIN=Vee or GND
Output Enable·
=VIH
Vour=Vee or GND
VIN=Vec or GND
lour=O,..A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour=O,..A
Guaranteed Limits
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Vee -0.1
3.84
Vcr; -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
,..A
±0.5
±5.0
±10.0
,..A
8.0
80.0
160.0
lAA
2.7
2.9
3.0
mA
Vee Vee -0.1
4.2
3.98
0
KS74AHCT
KS54AHCT
T. = -40°C to +8S o C T. = -55°C to +125°C Unit
380
KS54AHCT
KS74AHCT
670
4-8y-4 Register Files
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Input tr , tf~2 ns), AHCT670
Conditions T
KS74AHCT
KS54AHCT
T.=25°C
T.= -40°C to +85°C To = - 55°C to + 125°C
Unit
Vcc=5.0V
Vee= 5.0V± 10%
Vee=5.0V± 10%
Typ
Maximum Propagation Delay,
RA or Rs to Output
Propagation Delay,
Gw to Output
Propagation Delay,
Data to Output
Qutput Enable Time
GR to Output
Dn to Gw
Set up
Time
WA,WB to Gw
Hold
Time
WA, Ws to Gw
On to Gw
Input Capacitance
Max
Min
Max
23
28
23
34
28
34
tpLH
tpHL
CL=50pF
CL =150pF
17
23
28
tpLH
CL =50pF
CL =150pF
15
18
25
30
30
36
tpHL
CL=50pF
CL=150pF
15
18
25
30
30
36
tpLH
CL=50pF
CL=150pF
14
17
23
28
28
34
tpHL
CL =50pF
CL =150pF
28
34
tPZH
r----- RL=1 kO
tPZL
Output Disable Time
GR to Output
Min
14
CL =50pF
CL=150pF
14
14
17
23
28
CL=50pF
CL=150pF
13
16
21
26
25
31
CL=50pF
CL=150pF
13
16
21
26
25
31
17
28
34
17
28
39
~ RL =1 kO
tpLZ
17
CL =150pF
tsu
th
CIN
Output Capacitance
COUT Output disabled
Power Dissipation Capacitance *
Cpo
6
10
12
10
14
16
a
a
a
a
a
a
ns
ns
n~
ns
ns
ns
ns
5
pF
10
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin
t For AC switching test circuits and· timing waveforms see section 2.
=8~SUNG
381
I
KS54AHCT
KS74AHCT
67"'91//168' 0
12-8;t Address Comparators
DESCRIPTION
FEATURES
The '679 and '680 address comparatofs simplify addressing of memory boards and/or other peripheral devices. The
four P inputs are normally hard wired with a preprogrammeq address. An internal decoder determines what input information applied to the 1 2 A inputs must be low or high
to cause a low state at the output (Y). For example, a
positive-logic bit combination of 0111 (decimal 7) at the
P input determines that inputs A 1 through A7 must be low
and that inputs A8 through A 1 2 must be high to cause the
output to go low. Equality of the address applied at the A
inputs to the preprogrammed address is indicated by the
output being low.
• '679: 12-blt to 4-bit comparator with enable
• '680: 12-bit to 4-bit comparator with latch
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
(IOL =24 mA @ VOL =0.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
.
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" ,packages
(Available Tape & Reel), standard DIPs.
The '679 features an enable inpu (G). When G is low, the
device is enabled. When G is high, the device'ls disabled
and the output is high regardless of the A and P inputs.
The '680 features a transparent latch and a latch enable
input (E). When C is high, the device is in the transparent
mode. When C is low, the previous logical state of Y is
latched.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
PIN CONFIGURATIONS
'679
'680
Vee
A1
Vee
A1
A2
G
A2
E
A3
y
A3
y
A4
P3
A4
P3
A5
P2
A5
P2
A6
P1
A6
P1
A7
PO
A7
PO
A8
A12
A8
A12
A9
A11
GNC
=8SAMSUNG
Electronics
A9
A11
GND
A10
382
KS54AHCT
KS74AHCT
6791/680'
11
12-8it Address Comparators
LOGIC DIAGRAMS
'680
'679
A1
A2
A3
A4
A5
A6
A7
A8
A9
AI10
A11
(1)
A1
(2)
(3)
(4)
A2
A3
A4
(5)
A5
(6)
A6
(7)
A7
(8)
A8
(9)
AI9
(11)
(12)
(1)
(2)
(3)
(4)
(5)
(6)
I
(7)
(8)
(9)
A10 (11)
A11 (12)
(13)
c8SAMSUNG
Electronics
383
"~I
:
KS54AHCT
:KS74AHCT
, .' , ' '.
'!
.
~
.
,
679.1680
/1
·1'2:.rJit Address··Comparators
FUNCTION TABLE
'679
'680
G
E
P3
P2
P1
PO
- INPUTS COMMON TO'679 AND ,'680
A1
A2
A3
A4
AS
A6
A7
A8
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
L
L
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
,L
L
L
H
H
H
H
L.
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
H
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
H
L
H
L
L
.L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
'L
H
H
L
OUTPUT
A11
A12
y
H
H
H
H
H
H
.,
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
H
L
L
H
H
H
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
H
H
H
L
L'
L
L*
L*
L*
L
L
L
L
L
L
L
All other combinations
A9
A10
'
";"
L
H
'679: Any combination
H
'680: Any combination
Latched
Note: These three rows of the function table show combinations that would normally not be used in address comparator ap, plicatlons. The logic symbols above are not valid for all combinations in Which P = 1 2, 13 and 1 4. If symbols valid for
all combinations are required, starting with the fourth Exclusive-OR from the bottom, change P~9 to P=9 ... 11/13 ...
15,P~10 to P=10/11/14/15, and P~11 to P=11/15.
Absolute Maximum Ratings·
Supply Voltage Range Vcc, .... '. . . -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V.or VI > Vcc +0.5V) ..... ±20 mA
DC Output Diode Current, 10K
.
(Vo < -0.5V or Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) ......... ±70 mA
CJl.ntinuous ClJrrent Through
Vcc or GND pins ................ ±250 mA
iStorage Temperature Range, Tstg ... -65°C to +150 o C
Power Dissipation Per Package, Pdt ...... 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposLire to these conditions may affect device reliability.
c8SAMSUNG
Eleptronics '
,
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages *, VIN, Your . . OV to Vcc
Operating Temperature
Range
KS74AHCT: ·-40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
',>
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
384
KS54AHCT 6'7t'1/~80
KS74AHCT . I "/UI
12-BitAddress Comparators
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
T. =25°C
Typ
Minimum High-Level
Input Voltage
KS74AHCT
KS54AHCT
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
VIH
2.0
2.0
2.0
V
Maximum Low-Level
. VIL
Input Voltage
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OIAA
10= -6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=201AA
10=12mA
10=24mA
Maximum Input
Current
lIN
VIN=Vce or GND
±0.1
±1.0
±1.0
IAA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
IAA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
IAA
2.7
2.9
3.0
mA
Additionaf Worst
C~se Supply
Current
tilee
Vee Vee -0.1
4.2
3.98
0
VIN=Vec or GND
10uT=01AA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
IOUT=OIAA
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr , tf~2 ns), AHCT679
KS54AHCT
KS74AHCT
T. =25°C
T. = -40°C to +85°C T. = -55°C to +125°C
Vee = 5.0V
Vcc=5.0V% 10%
Vee=5.0V%10%
Symbol
Conditions t
tpLH
CL=50pF
CL=150pF
18
21
30
35
36
42
tPHL
CL=50pF
CL=150pF
18
27
30
35
36
42
tpLH
CL=50pF
CL=150pF
16
19
26
31
31
37
tPHL
CL=50pF
CL=150pF
16
19
26
31
31
37
tPLH
CL=50pF
CL=150pF
12
15
19
24
23
29
tPHL
CL=50pF
CL=150pF
12
15
19
24
23
29
Typ
Propagation Delay,
Any P to Y
Propagation Delay,
AnyAtoY
Propagation Delay,
G to Y
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
Min
5
Max
Min
Unit
Max
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC1 fin:
t For AC switching test circuits and timing w8vefofms see section 2.
c8SAMSUNG
Electronics
..
385
I
KS54AHCT
KS74AHCT
679.1/680
. ,/1
12-811 Address Comparators·
AC ELECTRICAL CHARACTERISTICS
&
Characteristic
(Input fr, ~2 ns), AHCT680
T.=25°C
Vcc= S.OV
Propagation Delay,
Any A to Y
II
I
KS54AHCT
T.= -55°C to +125°C
Vcc=S.OV± 10%
Conditionst
fru.t
Cl=50pF
Cl=150pF
21
24
35
40
42
48
lAil
Cl=-50pF
CL=150pF
21
24
42
48
fru.t
CL=50pF
Cl=150pF
18
21
35
40
30'
35
36
42
tpHl
CL=50pF
Cl=150pF
18
21
30
35
36
42
tpLH
Cl=50pF
CL=150pF
13
16
21
26
25
31
tpHl
Cl=50pF
Cl=150pF
13
16
21
26
25
31
Typ
Propagation Delay,
AnyPtoY
KS14AHCT
T.= -40°C to +85°C
Vcc=S.OV±10%
Symbol
Propagation Delay,
E to Y
Min
Max
Min
Unit
Max
ns
ns
ns
Set up Time
An before E
tsu
6
10
12
ns
Hold Time
An after E
ltJ
0
0
0
ns
Input Capacitance
CIN
5
Power Dissipation Capacitance"
Cpo
pF
pF
.. Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fint For AC switching test circuits and timing waveforms see section 2_
=8SA11SUNG
EIecIronics
386
8-Bit Magnitude
Comparators
FEATURES
DESCRIPTION
• Compares Two Hit Words
• '682 has 2OkO pullup Resistors on the Q Inputs
• Function, pilHMd, speed and cIriwe compatibility with
S4174ALS logic family
• Low power consumption characteristic of CMOS
• Higft.Driwe.Current outputs:
(loa. =24 IDA .. VOL =O.SV) for"reeI bus interface
• Inputs and 0UIputs interface cIracIIy with TTl, NMOS
and CMOS deIices
• Wide operating woItage range: 4.SV to S.SV
• Characterized for operation 01181' industrial and
military temperature ranges:
These magntude comparators perfonn compaisollS of two
eight-bit binary or BCD words. AI types provide P=Q and
P>Q outputs. The '682 fea...es 20-k2 puIup termination
resistors on the Q inputs for analog or switch data.
KS74AHCT: -40°C to +85°C
KS54AHCT: - ssoC to + 12SoC
These devices provide speeds and drive capability
equivalent to their ALSTTl counterparts and yet main1ain
CMOS power levels. The input and output voltage levels
aIow direct interface with TTL, NMOS and CMOS devices
without any external components.
AI inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
• Package options include "small outline" packages
(Available Tape & Reel). standard DIPs.
PIN CONFIGURATIONS
FUNCTION TABLE
I
'682 and '684
INPUTS
Va;
P>O
PO
p=o
ao
07
P1
P7
01
Q6
P2
P6
02
Q5
P3
P5
Q3
:l4
GND
P4
OUTPUTS
DATA
ENABLES
P,Q
P=Q
P>Q
PQ
X
G2
X
P=Q
L
L
P>Q
H
X
X
L
X
H
H
H
H
X
H
X
H
H
H
H
H
H
H
H
L
NOTES: 1. The last 31i1es of the fmction table apply only
to the device havng enable qus, i.e., '686.
2. The PO outputs to a 2-input
NAND gate.
'686
Va;
G2
p=o
07
P7
NC
Q6
P2
P6
02
Q5
P3
Q3
GND
----
P5
Q4
P4
NC-No internal connecIion
=8~SUNG
387
\
KS54AHCT
KS74AHCY'
.
68216841686
8-BitMagnitude
Comparators
LOGIC DIAGRAMS
'682 or '684
:k
PO
00
P1
01
P2
~
~
02
P3
03
P4
04
PS
05•
P6
06
P7
~
....
(6)
....
(7)~
-V-
(8)
....
..)~
.....
(11)
....
(19)
~
&-
~
-
J
-t>o-
-
-
~
(121?P....
~
(14)
(15)
.....
....
,~
~I
o 7 (18)
.....
c8SAMSUNG
Electronics
~>-
(1)
~~
==I"
--
~)
~
L.r
388
KS54AHCT
KS74AHCT
68216841886
LOGIC DIAGRAMS
8-Bit 'Magnitude
Comparators
(continued)
'686
(23)
.~
(22)
(3)
PO
00
(4)~
P1
(5t..~
02
P3
03
P4
04
P5
05
P6
06
P7
o7
-
So-
.....
(6l£
~
.....
01
P2
~
.....
(8)
-
....
~
II
.....
(10)
....
(11)~
.....
(132.
(
~
-h
-
..)~
(15)
~~
.....
.....
~&
(17)
~~
.....
-
(16~
....
-
~[:;;:;I
(20)
(21)
(1)
I
t
c8SAMSUNG
Electronics
)'
~.
J~
r
-
389
KS54AMCT
KS74AHCT
682II16,841686.'.
II
S-Sit'Magnitude'
, Comparators
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/~C from 65°C to 85°C
Supply Voltag~ .Range Vee •....... -0.5V to +7V
DC Input Diode Current. ',K
(V, < -0.5V or V, > Vee +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . .
± 1 25 mA
Storage Temperature Range. Tslg ... - 65 ° C to + 150 ° C
Power Dissipation Per Package. Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage. Vce. . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages *. Y,N. VOUT . . OV to Vce
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times. t r • tf . . . . . . . . . Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL, CHARACTERISTICS
Parameter
Symbol
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
IMinimum
High-Level
V,H
Input Voltage
- - - - - - - - - - rMaximum Low-Level
V,L
Input Voltage
54AHCT
KS74AHCT
Ta =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limit.
2.0
2.0
2.0
0.8
0.8
0.8
---------1-.
Minimum High-Level
Output Voltage
(Totem-pole Outputs)
V,N=V,H or V,L
10=-20",A
10=-6mA
VOL
V'N=V'H or V,L
10=20",A
10=12mA
10=24mA
Maximum Low-Level
i Output Voltage
(All Outputs)
-_._.""- -_. "._---.---
Maximum Input
Current.
('682 Q Inputs)
V
Vce -0.1
3.84
Vce -0.1
3.7
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
Vee=Max
V'N=2.7V
V'N=O.4V
-0.2
-0.4
-0.2
-0.4
-0.2
-0.4
mA
0
V
hN
V'N=Vec or GND
±0_1
±LO
±LO
IlA
Maximum 3-State
Leakage Current
loz
Output Enable
=V,H
VOUT=VCC or GND
±0.5
±5.0
±10.0
.1lA
For '682:
V'N=GND (00-07)
V/N=Vcc or GND
(all other inputs)
3.5
3.5
3.5
rnA
For '684 and '688
Vw=Vcc or GND
1our"';01lA
8.0
80.0
160.0
IlA
2.7
2.9
3.0
rnA
Icc
I
I
I
per input pin
I
Addilional Worst
~ Case SupPly
II
Vee Vee -0.1
4.2
3.93
Maximum Input
Current
(All other Inputs)
'Maximum
iOuiescent
! Supply Current
t,
V
.-
VOH
--------'--------'-1--
V
Current
I
V,=2.4V
Alec
other Inputs:
at Vccor GND
1our=01lA
c8SAMSUNG
ElecbOlics
390·
KS54AHCT
KS74AHCT
682'684'686
,I
AC ELECTRICAL CHARACTERISTICS
Characteristic
8-Bit Magnitude
Comparators
(I
(Input tr •
T. =25°C
Vcc=5.0V
tf~2 n5). AHCT682. AHCT684. AHCT686
KS54AHCT
KS74At:lCT
T. = -40°C to +85°C T. = -55°C to +125°C
Vcc=5.0V:10%
Vcc=5.0V: 10%
Symbol
Condltions t
tpLH
CL=50pF
CL =150pF
17
16
22
27
27
33
tpHL
CL=50pF
CL =150pF
17
16
22
27
27
33
tpLH
CL=50pF
CL =150pF
16
19
27
32
32
38
tpHL
Cl=50pF
CL=150pF
16
19
27
32
32
38
tpLH
CL=50pF
CL=150pF
10
13
16
21
19
25
tpHL
CL=50pF
CL=150pF
10
13
16
21
19
25
tpLH
C=50pF
Cl=150pF
11
14
19
24
23
29
tPHL
CL=50pF
CL =150pF
11
14
19
24
23
29
Typ
Maximum ~gation Delay.
P or 0 to P=O
Propagation Delay.
P or 0 to P>O
E!opagati08 Delay.
G1 to P= (,6860niy)
E!opagation Delay.
G2 to PQ
P Vee +O.5V) ..... ±20 mA
DC Output Diode Current,' .10K
(Vo <-0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Curr:ent Per Pin, 10
(-0.5V < Vo < Vee +O.5V) ......... ±70 mA
Continuous Current Through
Vee or GND pins ................ ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mWt
Recommended -Operating Conditions
Supply Voltage, Vee .. _...... _ .... 4.5V to 5.5V
DC Input & Output Voltages·, VIN, Vour:. OV to Vee
Operating Temperature
KS74AHCT: -40°·C to +85°C
Range
KS54AHCT: -55°C to+125°C
Input Rise & Fall Times, tr , tf _ .. _ . . . .. Max 500 ns
• Absolute Maximum Ratings .are those· values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND) .
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
T. =25°C
KS14AHCT
KS54AHCT
T. = -40°C to +85°C T.=-55°Cto +125°C Unit
Typ
Minimum High-Level
Input Voltage
Maximum Low-Level
Input Voltage
Minimum High-:Level
Output Voltage,
C688 only)
Guaranteed Limits
VIH
2.0
2.0
2.0
V
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee- 0 .1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
IlA
i
VOH
VIN=VIH or VIL
10=-20,.,A
10=-6mA
Maximum Low-Level.
Output Voltage
VOL
VIN=VIH or VIL
10=201lA
10=12mA
10=24mA
Maxiinum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
Maximum Output
Leakage Current
('689 only)
loz
VIN=VIH or VIL
Vour=Vce
±0.5
±5.0
±10.0
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Ice
~Iee
VIN=Vee or GND
10ur=0,.,A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=0,.,A
Vee Vee -0.1
3.98
4.2
0
IlA
.:
i
8.0
80.0
160.0
IlA
2.7
2.9
3.0
mA
:<'";
=8SAMSUNG
Electronics
'39~":
I
KS54AHCT.··.688'
KS74AHCT
1689·
8-8/f Identity. Comparators
/1
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr , t~2 ns), AHCT688
T. =25°C
Vee = 5.0V
Propagation Delay,
Oto p=O
Propagation Delay,
G to P=O
KS54AHCT
T... -55°C to +125°C
Vee=5.0V:t 10%
Condltlons t
tpLH
CL=50pF
CL=150pF
12
15
19
24
23
29
tpHL
CL=50pF
CL=150pF
12
15
19
24
23
29
tpLH
CL=50pF
CL=150pF
12
15
19
24
tpHL
CL.=50pF
CL=150pF
12
15
19
28
23
29
tpLH
(~~150pF
Co =50pF
11
14
17
22
20
26
tPHL
CI.=50pF
CL=150pF
11
14
17
22
20
26
Typ
PrQpagation Delay,
p'to p=O
KS74AHCT
T.... -40·C to +85°C
Vee" 5.0V:t 10%
Symbol
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
Min
Max
Unit
Max
Min
,
23
29
ns
ns
ns
pF
5
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r , tf"2 ns), AHCT689
KS74AHCT
KS54AHCT
T. =25 0 C
T.... -40°C to +85°C T. = -55°C to +125°C
Vee = 5.0V
Vee=5.0V:t 10%
Vee=5.0V:t10%
Symbol
Conditions t
tpLH
CL=50pF
CL =150pF
19
22
28
33
33
39
CL=~pF
CL="50pF
14
17
23
28
28
34
tpLH
CL=50pF
CL=150pF
19
22
28
33
33
39
tPHL
CL=50pF
CL=150pF
14
17
23
28
28
tpLH
CL=50pF
CL=150pF
16
19
23
fJ>Hl
Cl=50pF
Cl=15OpF
11
16
Typ
Propagation Delay,
P to p=O
Propagation Delay,
to P=Q
o
Propagation Delay.
Gto~
Input Capacitance
Power Dissipation Capacitance·
tpHL
CIN
Cpo
Min
5
Max
Min
Unit
Max
ns
ns
34
28
27
33
18
22
23
28
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: PD=CPO VccJ fin.
test circuits and timing. waveforms see section 2.
t For AC switching
c8 SAlliSUNG
EJectroncs
394
KS54AHCT
KS74AHCT
7931794
I,
8-Bit Latch/Register
with. Readback
FEATURES
DESCRIPTION
• I/O port configuration enables output data back onto
input bus
• Latch ('793) and and Register (,794) options
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with drive ,current
(IOL 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for. operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These are 8-bit latches/registers that allow temporary
storage and retriev~1 of data on a bus, This operation is
important in control algorithms which make decisions based on the previous status of output controls. Rather than
storing a redundant copy of the output data in memory,
simply reading the register as an I/O port allows the data
to be retrieved from where it has been stored in a '793
or '794, for verification and/or updating.
=
=
The Data is loaded in the registers on the positive-edge
of the clock (ClK) for the '794. The data is passed through
the '793 when E is high, and it is latched when E goes low.
The output control (OC) is used to erable data on the DO-D7
pins. when OC is low the output of the latches/registers
is enabled on DO-D7, enabling 0 as an output bus so that
the host can perform a read operation. When OC is high,
DO-07 are inputs to the latches/registors configuring D ·as
an input bus.
These devices provide speeds and drive capability
equivalent to their AlSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATIONS
'793
OC
Vee
DO
00
01
01
02
02
03
03
04
04
05
05
06
06
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLES
'793
07
E
E
OC
Q
D
L
L
Ht
H
L
H
L
H
00**
00**
0*
D
Output, 0
Input
Output, 0*
Input
In this case the output of the latch feeds the input, and
a "race" condition results.
* * 00 represents the previous "latched" state.
t This transition is not a normal mode of operation and
may produce hazards.
*
'794
6C
Vrx;
DO
QO
01
01
02
02
D3
Q3
D4
D5
Q5
D6
Q6
D7
07
GND
=8~NG
a..K
"794
eLK
oc
LorHor'LorHor't
t
L
Q
L
00
00
00
H
0
H
D
Output,O
Input
Output,O*
Input
* In this case the output of the regISter is clocked to the
inputs and the overaI Q output is oochauged at 00.
395
I
KS54AHCT;'7931794
KS74AHCT, .
8-Bit, Latch/Register
with Readback
LOGIC DIAGRAMS
'794
'793
DO
(2)
DO
(2)
01 .--:.:;(3;,:..)-'-'---+--+-1
01
(3)
02
(4)
02
(4)
03
(5)
03
(5)
04
(6)
04 _...:..(6..:..)_-'-_-+-+-1
05
(7)
05
(7)
06
(8)
06
(8)
07
(9)
07
(9)
06
(11) E
c8SA~SUNG
Electronics
(11) elK
396
KS54AHCT'793 1794
KS74AHCT
I,
8-Bit Latch/Register
with Readback
Absolute Maximum Ratings*
Supply Voltage Range Vee, ., ..... -0.5V to + 7V
DC Input Diode Current, irK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±70 mA
Continuous Current Through
Vee or GND pins. . . . .
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OIJA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2OIJ A
10=12mA
10=24mA
0.1
0.2,6
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
IrN
VIN=Vee or GND
±0.1
±1.0
±1.0
IJA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
IJA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
IJA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Iee
VIN=Vee or GND
10uT=OIJA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=OIJA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
397
I
~~:~~~~ 793/794
8-Bit· Latch/Register
with Readback
AC ELECTRICAL CHARACTERISTICS (~ .... tr<2 ns). AHCT793. AHCT194
ChaiiCleilsllc
Operating Frequency
f'194
P
onlY)
.
Delage
to Any a (,793 only)
.
Delage
ClKI E to Any a
SJIIIbG
t.nax
CondIIIDnst
OisabIeTme
OCto 0
CL=50pF
60
40
Ct.=5OpF
10
13
16
21
Ct.=50pF
10
13
16
21
Ct.=50pF
12
15
20
25
Ct.=50pF
12
15
ftatL Ct.=150pF
IRH Ct.=15OpF
ftatL Ct.=150pF
tplH I\.=1kO
Ca..=1~
C=L.ow
Ca..=50pF
for
'193)
tpZL
Ca..==15OpF
lin
Ycc=5.0Y;t: 10%
MIn
~-1KO
ftottz Ir-..
50pF
Itu rc-:...L.ow for '793)
tw
o before H ('793)
o before CLKt('194)
o after E' (,793)
o after CLKt (,794)
feu
fh
c..
QJut Capcitance
~ Capacn.1Ce
Coot ~==GND
Power Dissipetion CapacitalICe·
CPO
UnIt
lin
35
MHz
19
25
19
25
ns
ns
20
25
24
30
24
30
11
14
18
23
22
28
11
13
18
23
22
28
11
18
22
11
18
22
I
~
Pulse Width.
HoIdTme
Ycc""S.OY;t:10%
MIn
IRH Ct.=150pF
ClK/C High or low
Setup time
vcc=s.eV
TJP
Ca..=50pF
~Ir.ne.
toO
KS74AHCT
KS54ARtT
IT. ::25-C T.= -40-C
10 +15-C IT. =-55-C 10 +125-C
9
14
19
6
10
12
10
15
20
9
10
12
0
0
0
ns
ns
ns
ns
ns
5
pF
10
pF
ns
• CPO determines the no-load dynamic power dissipation: Po==CPO Va:;z fin·
t For AC switcIW1g test circuits and timilg waveforms see Section 2.
c8SA11SUNG
ElecbOlics
398
KS54AHCT
KS74AHCT
821'822
,~
DESCRIPTION
FEATURES
• Functionally Equivalent to MID's Am29821 and
Am29822
ExIra Data Width Necessary for Wider AddressIData Paths or BuSes with Parity
Poww-Up-itig....mpedance Slate
Function, pilHMll, speed and driwe compatibility with
54174ALS logic family
Low power consumption charact.-istic of CMOS
3-State outputs with high driYe current
(Icx. =24
VOl. =O.5Y) for clreeI bus int.race
Inputs and outputs interface direcIIy with TTl., NMOS
and CMOS deIices
Wide operating 1IOItage range: 4.5Y to 5.5Y
C,haract.-ized. far opa-ation ewer industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +12SoC
• Prowides
•
•
•
•
•
•
•
10-Bit Bus Interface Flip-Flops
with 3-State Outputs
mA.
• Package options include "small outline" packages
(Available Tape It Reel), standard DIPs.
PIN CONFIGURATIONS
These 1O-bit IJus-interhK:e flip-flops featue ttwee-sIale outputs designed speciIicaIIy for driving highly-capacitive or
relatively Iow-impedance loads. They are suitable for implementing wider buffer registers, 1/0 ports, bidirectional
bus drivers with parity, and working registers.
AD of ~ flip-flops are edge-triggered and O-type. On the
positive transition of the clock the
outputs on the '821
will be true, and on the '822 will be complementary to the
data input.
a
A buffered output-control input can be used to place the
ten outpuIs in either a nonnaIlogic slate (tigh or low levels)
or a high-impedance state. The high-impedance state and
increased drive provide the capability to drive the bus lines
in a bus-organized system without need for interface or
pull-up components. The output control (OC) does not affect the internal operation of the flip-flops. Old data can
be retained or new data can be entered while the outputs
are in the high-impedance state.
These devices provide speeds and drive capability
equivalent to their ALSTTL comterparts and yet maintain
CMOS power levels. The input and output voltage levels
aIow direct interface with TTL. NMOS and CMOS devices
without any external components.
AI inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
'821
Vex:
ground.
10
20
3Q
40
50
sa
6D
70
70
aD
8Q
90
100
90
100
GND
CLJ(
'822
oc
Vex:
10
20
3Q
FUNCTION TABLES
(Each Flip-Flop)
'821
Inputs
Output
OC
ClK
D
Q
L
l
l
l
t
t
H
l
H
L
L
H
00
00
H
X
X
X
X
Z
40
'822
50
sa
70
8Q
9D
100
90
100
GND
CLJ(
c8SAMSUNG
ElecbOlIics
Output
Inputs
oc
ClK
0
Q
l
l
l
l
H
t
H
l
l
H
X
X
X
00
00
t
l
H
X
Z
399
I
10..B;, ,"us Interface ,Flip-Flops
wit/J' 3-State .Outputs
:'(001(: DIAGRAMS
'821
QC
'822
(1)
OC
eLK
(1)
ClK
(23)
10
20
3D
40
50
6D
70
80
90
(2)
(3)
(4),
(5)
(6)
(7)
(8)
(9)
(10)
10
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
(14)
100
(11)
c8SAMSUNG
Electronics
(23)
10
20
30
40
50
60
70
80
90
20
3D
40
50
60
70
80
90
'(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
(14)
100
100
(11)
10
20
30
40
50
60
70
80
90
100
400
KS54AHCT
KS74AHCT
821'/1822
j'
10-Bit Bus Interface Flip-Flops
with 3-State Outputs
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ...... . -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.6V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±70 mA
Continuous Current Through
Vec or GND pins ....•........... ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee .............. 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: "':'55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vec=5V±10% Unless Otherwise Specified)
T. =25°C
Typ
KS74AHCT
KS54AHCT
T. = -40°C to +85°C T. = - 55°C to + 125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OIlA
10=-6mA,
Vce -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=201lA
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximumlnp'ut
Current
liN
VIN=Vec or GND
±0.1
±1.0
±1.0
IlA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VOUT=VCC or GND
±0.5
±5.0
±10.0
IlA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
IlA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Icc
VIN=Vce or GND
IOUT=OIlA
per input pin
VI=2.4V
other Inputs:
at Vec or GND
lOUT = OIlA
c8SAMSUNG
Electronics
.
Vee Vee -0.1
4.2
3.98
0
401
I
kS54AHCt8211822
,/~
KS74AHCT,
1O-Blt' Suslnf."BceFIIp.Flops
with a-$tBte Outputs_
AC ELECTRICAL CHARACTERISTICS, (Input fr,
K$74AHOT
\
Char.cterlstlc
Symbol
a
Output Enable Time,
to any
oc
a
Output Disable Time,
de to any Q
Condltlona t
Typ
Min
50
35
CL=50pF
'tpLH
CL=150pF
13
16
13
16
tPZL
tPZL
RL=1kO
Max
Min
Max
30
15
MHz
20
18
23
18
23
CL=50pF
CL=150pF
11
14
18
23
28
CL=50pF
CL=150pF
11
14
18
23
13
18
22
13
18
22
CL=50pF
tpHL
CL=150pF
I---
KS54AHOT
T.-25·0
T•• -4O·C to +85"C T._ -5~.<:to +12S·C
Unit
Vcc-S.ov
Vcc-5.0Yz10%
Vcc-S.OYz 10%
CL=50pF _
Maximum Operating Frequency fmax
Propagation Delay
CLK to any
tt<2 ns), AHCT821, AHCT822,
tPHZ RL=1kO
I--, tpLZ CL=50pF
20
15
ns
22
ns
22
28
ns
Pulse Width,
ClK High or low
tw
9
15
18
ns
Setup Time,
Data before ClKt
tau
9
14
17
ns
Hold Time,
Data after ClKt
th
0
0
0
ns
5
pF
Output Capacitance
COUT O~tput Disabled
10
pF
Power DiSSIpation
Capacitance* (per stage)
Vee +0.5V)
±20 inA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ... , , .. , ±70 mA
Continuous Current Through
Vee or GND pins
' , ,,,. ,,
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt, , , , , , 500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT ' , OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf
, , , , , Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20IJA
'lo=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2OIJ A
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vce or GND
±0.1
±1.0
±1.0
J.lA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
IJA
Maximum Quiescent
Supply Current
lee
8.0
80.0
160.0
IJA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
llice
VIN=Vee or GND
IOUT=OJ.lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
louT=OJ.lA
-c8SAMSUNG
Electronics
Vcc Vce -0.1
3.98
4.2
0
405
I
9-Bit Bus Interface Flip-Flops
with 3-State Outputs
KS54AHCt;'B23/824
KS74AHCT' "
AC ELECTRICAL CHARACTERISTICS
Characteristic
Propagation Delay
ClK to any
a
Propagation Delay,
ClR to Any
a
Min
50
35
CL=50pF
tpLH
CL =150pF
17
20
19
24
23
28
17
20
23
28
17
20
19
24
20
25
25
31
CL=50pF
CL =150pF
11
14
18
23
22
28
CL=50pF
CL=150pF
11
14
18
23
17
20
22
28
25
17
20
25
tpHL
CL=50pF
CL=150pF
tPHL
CL=50pF
CL=150pF
tPZH
Output Disable Time,
OC to any
f-----
RL=1kO
tPZL
,-
tpHZ RL=1kO
tpLZ CL=50pF
a
ClR low
tw
ClK, high or I~~ 1-------f--ClR inactive
Setup
Time before
ClKt
Data
tsu
ClKEN high
or low
f-----'----------Hold Time,
ClKEN or data after ClKt
--~
------
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance* (per stage)
=
KS74AHCT
KS54AHCT
+8SOC T.=-SS·Cto +12S·C
Un"
Vcc=5.0V:10%
Vcc-5.0V: 10%
=-40·C to
Typ
f-----
a
T. =2S·C
T.
Vee S.OV
fmax ' CL=50pF
Output Enable Time,
OC to any
Pulse Width
Condltlonsl
Symbol
Maximum Operating Frequency
(Input tr , tf4t2 ns), AHCT823, AHCT824
th
f--
Max
Min
Max
30
9
15
18
9
15
18
9
14
17
9
14
17
9
14
17
0
0
0
MHz
ns
ns
ns
--
ns
-
ns
ns
ns
1-----
CIN
- - 1------1-
5
COUT Output Disabled
10
OC=Vee
OC=GND
5
30
Cpo
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee'
.
pF
pF
pF
pF
fin,
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
406
KS54AHCT
KS74AHCT
825/826
FEATURES
DESCRIPTION
• Functionally Equivalent to AMD's Am29825 and
Am29826
• Improved IOH Specifications
• Multiple Output Enables Allow Multiuser Control of
the Interface
• Power-Up High-Impedance State
• Function, pin-out, speed and drive compatibility with
54174ALS .Iogic family
• Low power consumption characteristic of CMOS
3-State outputs with "-igh drive current
(IOl 24 mA@ Val O;5V) for direct bus interface
• •,nputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
=
8-Bit Bus Interface Flip-Flops
with 3-State Outputs
=
PIN CONFIGURATIONS
'825
OC1
OC2
1D
2D
3D
4D
5D
6D
Vee
OC3
10
20
30
40
50
60
70
7D
aD
ClR
GND
These 8-bit flip-flops feature three-state outputs designed
specifically for driving highly capacitive or relatively lowimpedance loads. They are suitable for implementing multiuser buffer registers, I/O ports, bus drivers and working
registers.
With the clock enable (CLKEN) low, all Ootype edgetriggered flip-flops enter data on the low-to-high transition
of the clock. Taking CLKEN high will disable the clock buffer, thus latching the outputs. The '825 has non-inverting
o inputs and the '826 has inverting i5 inputs. Taking the
CLR inputs low causes the eight Q outputs to go low independently of the clock.
Multiuser buffered output-control inputs (OC1, OC2, and
OC3) can be used to place th.e eight outputs in either a
normal logic state (high or low level) or a high-impedance
state. The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized
system without need for interface or pull-up components .
The output controls do not affect the internal operation of
the flip-flops. Old data can be retained or new data can
be entered while the outputs are in the high-impedance
state.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels, The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
so
ClKEN
ClK
'826
OC1
OC2
15
25
35
40
50
60
75
s5
ClR
GND
Vee
OC3
10
20
30
40
50
60
70
SO
ClKEN
ClK
c8SAMSUNG
Electronics .
407
II
KS54AHCT~: Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee+0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
........ ±250 mA
Storage Temperature Range, T519 ... -65°C to +150°C
Power Dissipation Per Package, Pdt
... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . .
4.5V to S.5V
DC Input & Output Voltages·, VIN, Vour .. OV teVee
Operating Temperature
Range
KS74AHCT: -40°C to +8SoC
-KS54AHCT: -5SoC to +125°C
Input Rise & Fall Times, tr , tf ......... Max SOO ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=SV± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta = -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20JlA
10= -6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20JlA
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
JlA
Maximum 3-State
Leakage Current
loz
Outp'lt Enable
=VIH
Vour=Vee or GND
±0.5
±5.0
±10.0
IJA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
JlA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.t..lee
VIN=Vee or GND
10ur=OJlA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=OJlA
c8SAMSUNG
Electronics
,
Vee Vce -0.1
4.2
3.98
0
409
I
8-Bit Bus Interface Flip-Flops
with 3·State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Input t r , tf~2 ns), AHCT825, AHCT826
Condltlons t
Maximum Operating Frequency fmax CL=50pF
Propagation Delay
ClK to any
a
~agation
ClR to Any
Delay,
a
Output Enable Time,
OC to any
a
Output Disable Time,
.OC to any
a
Pulse Width
ClR 10....
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance· (per stage)
50
35
Max
Min
Max
30
MHz
17
20
19
24
tpHL
CL=50pF
CL=150pF
17
20
19
24
23
28
23
28.
tPHL
CL=50pF
CL=150pF
12
15
19
22
23
27
CL=50pF
GL=150pF
11
14
18
23
22
28
CL=50pF
CL=150pF
11
14
18
23
22 .
28
13
18
22
13
18
22 -
tPZH
r---- RL=1kO
tPZL
tPHZ RL=1kO
tpLZ CL=50pF
f----
tw
tsu
CLKEN high
or low
Hold Time,
ClKEN or data after ClKt
Min
CL=50pF
CL=150pF
CLR inactive
Data
=
Typ
KS54AHCT
+125°C
Unit
Vee=5.0V± 10%
T.=~55°Cto
tPLH
ClK high or low
Setup
Time before
ClKt
KS74AHCT·
T.=25°C
T.=-400Cto +85°C
Vee = 5.0V
Vee 5.0V ± 10%
th
CIN
COUT Output Disabled
OC=Vcc
Cpo
OC'=GND
9
15
18
9
15
18
9
14
17
9
14
17
9
14
17
0
0
0
-
-.-
ns
r--ns
-.
--
ns
ns
ns
ns
ns
5
pF
10
pF
5
30
pF
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
fin-
t For AC switching test circuits and timing waveforms see section 2_
c8SAMSUNG
Electronics
410
KS54AHCT
KS74AHCT
841/842
10-Bit Bus Interface O-Type
Latches with 3-State Outputs
FEATURES
DESCRIPTION
., Bus-Structured Pinout
., Provides Extra Bus Driving Latches
., Necessary for Wider Address/Data Paths or Buses
with Parity
• Power-Up High-Impedance State
• Function, pin-out, speed and drive compatibility with
54174ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL = 24 mA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 1O-bit bus interface latches feature three-state outputs designed specifically for driving highly capacitive or
relatively low-impedance loads. They are suitable for implementing wider buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
PIN CONFIGURATIONS
'841
The ten latches are transparent O-type. The '841 h~
noninverting data (0) inputs and the '842 has inverting (0)
inputs.
A buffered output control (OC) input can be used to place
the ten outputs in either a normal logic state (high or low
levels) or a high-impedance state. The high-impedance
state and increased drive provide the capability to drive
the bus lines in a bus-organized system without need for
interface or pull-up components.
The output control does not affect the internal operation
of the latches. Old data can be retained or new data can
be entered while the outputs are off.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
6C
Vee
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
GNO
E
OC
E
0
Q
H
H
L
X
H
L
X
X
H
L
vee
L
L
L
H
'842
oc
10
20
3D
40
50
60
70
8D
90
100
GNO
10
20
30
40
50
60
70
80
90
100
E
c8SAMSUNG
Electronics
FUNCTION TABLES
'841
Inputs
Output
00
Z
'842
Inputs
Output
OC
E
0
Q
L
L
L
H
H
H
L
X
H
L
X
X
L
H
00
Z
411
II
10-Bit Bus Interface D-TYRe
Latches with 3-State Outputs
KS54AHCTS411842
KS74AHCT . . .
LOGIC DIAGRAM S
'841
Oc
'842
(1)
Dc
(1)
E
(23)
(2),
10 -
(22)
20
(3)
20
20
(21)
30
(4)
30
3D
. (20)
(5)
40
40
40
(19)
50
(6)
(7)
(8)
(16)
(9)
70
(10)
c8SAMSUNG
Electronics
(4)
(5)
(6)
(22)
(21)
(20)
(19)
(7)
(8)
(9)
90
90
(14)
(11)
(3)
(17)
(16)
10
20
30
40
50
60
70
80
86
(15)
100
70
80
80
90
(2)
(18)
60
60
(17)
70
50
50
(18)
60
(23)
10
10
(10)
(15)
(14)
100
100
(11)
90
100
412
KS54AHCT
KS74AHCT
841/842
10-Bit Bus. In(fJrface D-Type
Latches with 3-State Outputs'
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to +7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output 'Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 rnA
Continuous Current Through
Vce or GND pins. . . . . . . .
±250 rnA
Storage Temperature Range, T5 tg . . . -65°C to +150°C
Power Dissipation Per Package, Pdt. . . .
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
......... 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf ..
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Typ
I
KS74AHCT
KS54AHCT
T = -40°C'to +85°C Ta = -55°C to +125°C Unit
a
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN = VIH or VIL
10=20",A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vec or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
61ee
VIN=Vee or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
c8SAMSUNG
Electronics
Vce Vee -0.1
4.2
3.98
0
413
I
1·0·8i,. Sus/nterface D- Type
Latches with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Input tr , tf"2 ns), AHCT841, AHCT842
Condltlons t
KS74AHCT
KS54AHCT
T. =25°C
T. = -40°C to +85°C Ta =-550C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V%10%
Vcc=5.0V% 10%
I
Typ
Propagation Delay,
Data to Q
Propagation Delay,
E to any Q
Min
Max
Min'
Max
tpLH
CL=50pF
CL=150pF
10
13
13
21
19
25
tpHL
CL=50pF
CL=150pF
10
13
13
21
19
25
tpLH
CL=50pF
CL=150pF
15
18
24
29
29
35
tPHL
CL=50pF
CL=150pF
15
18
24
29
29
35
CL=50pF
CL =150pF
13
16
18
23
22
28
CL=50pF
CL=150pF
13
16
- -t---.
13
18
23
22
28
18
22
13
18
22
1----.
tPZH
Output Enable Time,
·OC to any a
I----------
Output Disable Time,
OC to any Q
f---
RL=1 kO
tPZL
tpHZ
tpLZ
RL=1 kO
CL=50pF
1------'
ns
--
ns
--
ns
ns
Pulse Width,
E High
.tw
12
20
25
ns
, Setup Time,
Data before E~
tsu
6
10
12
ns
f-----.
,,-
Hold Time,
Data after E~
Input Capcitance
Output Capacitance
Power Dissipation
Capacitance* (per stage)
th
3
CIN
5
pF
COUT Output Disabled
10
pF
OC=Vcc
OC=GND
5
30
pF
pF
Cpo
* Cpo determines the no· load dynamic power dissipation: Po=Cpo VCC 2
5
7
ns
fin.
t For AC switching test circuits and timing waveforms see section 2.
cS2
.
•• SAMSUNG
Electronics
414
KS54AHCT
KS74AHCT
843/844
9-Bit Bus Interface' D~Type
Latches with3-State Outputs
FEATURES
DESCRIPTION
• Bus-Structured Pinout
• Provide Extra Bus Driving Latches
Necessary for Wider Address/Data Paths or Buses
with Parity
• Power-Up High Impedance
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOl = 24 mA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 9-bit bus interface latches feature three-state outputs designed specifically for driving highly capacitive or
relatively low-impedance loads. They are suitable for implementing wider buffer registers, I/O ports, bidirectional
bus drivers and working registers.
'843
6C
Vee
10
20
3D
40
70
80
90
10
20
30
40
50
60
70
80
90
CLR
PRE
GNO
E
'844
be
10
20
30
40
50
60
70
85
90
Vee
10
20
30
40
50
60
70
80
90
CCR
PRE
GNO
E
c8SAMSUNG
Electronics
A buffered output control (DC) input can be used to place
the nine outputs in either a normal logic state (high or low
levels) or a high-impedance state. The high-impedance
state and increased drive provide the capability to drive
the bus lines in a bus-organized system without need for
interface or pull-up components.
The output control (OC) does not affect the internal operation of the flip-flops. Old data can be retained or new data
can be entered while the outputs are off.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATIONS
•
The nine latches are transparent Ootype. The '843 has
non inverting data (0) inputs and the '844 has inverting 5
inputs.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
FUNCTION TABLES
'843
INPUTS
OUTPUT
PRE
CLR
OC
E
D
Q
L
H
H
H
H
X
L
H
H
H
L
L
L
X
X
X
X
H
L
H
H
L
H
H
X
X
L
X
X
X
L
L
H
L
00
Z
. '844
INPUTS
OUTPUT
PRE
CLR
OC
E
D
Q
L
H
H
H
H
X
L
X
L
X
X
X
H
L
H
H
H
L
H
H
L
H
X
L
X
X
X
00
X
L
L
L
H
H
L
Z
415
I
9-Bit Bus Interface'O-Type
Latches with"3-Sfate Outputs
LOGIC DIAGRAMS
'844
'843
00
~(~1)____~.>
____~__- .
PRE (:..:.1.;:.4)-,.-~~()-
(2)
(23) 10
(3)
(22) 2Q
20
(22)20
(4)
(21) 30
3D
(21) 30
(5)
(20) 40
40
(20) 40
(6)
(19) 50
50
(19) 50
(7)
(18) 60
60
(8)
(17) 70
7D
(17) 70
(9)
(16) 80
80
(16) 80
90 (10)
(15) 90
10
20
30
40
50
60
70
80
c8SAMSUNG
Electronics
(23) 10
(18) 60
(15) 90
416
KS54AHCT
KS74AHCT
843'1844
Ij
9-Bit Bus Interface D-Type
Latches with 3-State Outputs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, . .
-d.5V to +7V
DC Input Diode Current, ',K
(V, < -0.5V or V, > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vce or GND pins, .... , . , .. ,
±250 mA
Storage Temperature Range, T5 tg . . . -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vec .. ,
4.5V to 5.5V
DC Input & Output Voltages·, V'N, VOUT .. OV to Vcc
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHC~ -55°C~ +125°C
Input Rise & Fall Times, tr , tf ' ....... , Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74AHCT
KS54AHCT
Ta =-40°Cto +85°C Ta = -55°C to + 125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
V,H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V,L
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
V'N=V'H or V,L
10=-20JJA
10= -6mA
Vce -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
V,N=V,H or V,L
10=20JJA
10=12mA
10=24mA
0.1
"",,' 0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
V'N=Vec or GND
±0.1
±1.0
±1.0
JJA
Maximum 3-State
Leakage Current
loz
Output Enable
=V'H
VouT=Vce or GND
±0.5
±5.0
±10.0
J.lA
8.0
80.0
160.0
JJA
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
r---
Additional Worst
Case Supply
Current
Icc
~r----
~Icc
V'N=Vee or GND
- 10uT=OJJA
Vcc Vcc -0.1
4.2
3.98
0
~
per input pin
V,=2.4V
other Inputs:
at Vee or GND
10uT=0",A
cKSAMSUNG
417
KS54AHCT
KS74AHCT
8431844
I~,
AC ELECTRICAL CHARACTERISTICS
Chlrlcterlltlc
Symbol
Condltlonl t
9-Bit Bus Interface D-Type
Latches with 3-State Outputs
(Input t" t,<2 ns), AHCT843, AHCT844
KS74AHCT
KSS4AHCT
T. -25·C
T•• -40·C to +8S·C T•• -ss·c to +12S·C
Unit
Ycc-5.0Y
Ycc-S.OYz10%
Ycc-5.0Vz 10%
Typ
Propagation Delay,
Data to
a
Propagation Delay,
E to any 0
Propagation Delay,
PRE to 0
Propagation Delay,
CLA to 0
Output Enable Time,
oc to any 0
6utput Disable Time,
OC to any 0
-
Min
MIX
Min
MIX
tpLH
CL=50pF
CL=150pF
13
16
18
23
22
28
tpHL
CL= 50pF
CL=150pF
13
16
18
23
22
28
tPLH
CL=50pF
CL=150pF
16
19
26
31
31
31
tpHL
CL=50pF
CL=150pF
16
19
26
31
31
37
tPLH
CL=50pF
CL=150pF
17
20
27
32
32
38
ns
tpHL
CL=50pF
CL=150pF
17
20
27
32
32
38
ns
CL=50pF
CL=150pF
11
14
18
23
22
28
CL=50pF
CL=150pF
11
14
18
23
22
28
tPZL
RL=1kO
tPZL
tPHZ
f---
tpLZ
RL=1.kO
CL=50pF
13
18
22
13
18
22
ns
ns
ns
ns
Pulse Width,
E High
tw
12
20
25
ns
Setup Time,'
Data before E+
tsu
8
10
12
ns
Hold Time,
Data atter +
th
3
5
7
ns
f--
Input Capacitance
Output CapaCitance
Power Dissipation
Capacltance* (per stage)
C'N
COUT
Cpo
5
pF
Output Disabled
10
pF
OC=Vcc
OO=GND
5
30
pF
• CPD determines the no-load dynamic power dissipation: Po=Cpo VCC 3
fin,
t For AC switching test circuits and timing wavetorms see section 2.
c8SAMSUNG
EIAt'!trnnit'!Q
418
KS54AHCT
KS74AHCT
845/846
.
8-Bit Bus Interface O-Type
Latches with 3-State Outputs
FEATURE
DESCRIPTION
• 3-state buffer-type outputs drive bus-lines directly
• Bus-structured pinout
• Provides extra bus driving latches necessary for
wider address/data paths or buses with parity
• Low power consumption characteristic of CMOS
devices
• 3-state outputs with high drive current (loL = 24mA
@ VOL = O.5V) for direct bus interface
• Direct interface capability with TTL, NMOS and
CMOS devices
• Wide operating volage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54AHCT: -55°C to 125°C
These 8-bit latches feature three-state outputs designed
specifically for driving highly capacitive or relatively low impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers.
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATIONS
The eight latches are transparent D-type. The '845 has
noninverting data{D) inputs. The '846 has inverting D inputs. Since CLR and PRE are independent of the clock,
taking the CLR input low will cause the eight Q outputs to
go low. Taking the PRE input low will cause the eight Q
outputs to go high. When both PRE and CLR are taken low,
the outputs will follow the preset condition.
The buffered output control inputs (OC1, OC2, and OC3)
can be used to place the eight outputs in either a normal
logic state (high or low levels) or a high-impedance state.
In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impendance state
and increased drive provide the capability to drive the bus
lines in a bus-organized system without need for interface
or pull-up components. The output controls do not affect
the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are
in the high-impedance state.
'845
OC1
OC2
10
20
3D
40
50
60
Vcr;
OC3
10
20
30
40
50
60
70
SO
19
SO
ern
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vec and
ground.
PRE
GNO
E
'846
Vcr;
~3
5D
10
20
30
40
50
e6
eo
7D
sD
70
80
~
PRE
GNO
E
419
I
KS54AHCT
KS74AHCT
845/846
FUNCTION TABLE
PRE CLR
H
L
L
H
H
H
X
X
X
L
H
L
H
H
H
X
X
X
INPUTS
OC1 OC2
L
L
L
L
L
L
X
X
H
8-Bit Bus Interface D-Type
Latches with 3-State Outputs
'846
'845
OUTPUT
OC3
E
0
Q
PRE
L
L
L
L
L
L
L
L
L
L
L
X
X'
X
H
H
L
X
X
X
X
X
X
L
H
X
X
X
X
H
L
H
L
H
L
H
L
H
H
H
X
X
X
L
X
H
X
H
X
X
00
Z
Z
Z
INPUTS
CLR OC1 OC2
OC3
E
D
Q
L
L
L
L
L
L
X
X
X
H
H
L
X
X
X
X
X
X
H
L
H
H
L
H
L
L
H
H
H
X
X
X
L
L
L
OUTPUT
L
L
L
L
L
X
X
H
L
L
X
H
X
L
L
H
X
X
L
H
X
X
X
X
00
Z
Z
Z
LOGIC DIAGRAMS
'846
OC1-1.!.L-----,
OC2------ Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Clirrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . . . .
±70 rnA
Continuous Current Through
Vee or GND pins
....... ±250 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc .............. 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vec
Operating Temperature
KS74AHCT: -40°C to +85°C
Range
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . .. Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vce=5V± 10% Unless Otherwise Specified)
Ta =2S0C
Symbol Test Conditions
Typ
KS54AHCT
KS74AHCT
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/AA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O /AA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
/AA
Maximum Quiescent
Supply Current
Icc
VIN=Vee or GND
louT=O/AA
8.0
80.0
160.0
/AA
Additional Worst
Case Supply
Current
per input in
VI=2.4V
1I. Iec other Inputs:
at Vee or GND
10uT=0/AA
2.7
2.9
3.0
mA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
421
II
KS54AHCT
KS7·4AHCT
8451846
8-Bit'Buslnterface D-Type
Latches with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons l
(Input t r ,
T.=25°C
Vcc=5.0V
tf~2 ns), AHCT845
KS74AHCT
T.= -40°C to +85°C
Vee= 5.0V:!: 10%
Typ
Max
Min
13
22
26
tpHL
13
22
26
r-------
Propagatlo Delay
D to
r-------
Propagation Delay
CLR to Q
r-------
I Propagation Delay
: PRE to Q
r-------
Unit
Max
tPLH
Propagation Delay
E toO
ns
tpLH
8
15
20
tPHL
8
15
20
tPLH
16
26
31
tPHL
16
26
31
tpLH
16
26
31
tpHL
16
26
31
tPZH
·12
20
24
tPZL
12
20
24
tpHZ
12
20
24
tpLZ
12
20
24
tsu
8
10
12
ns
th
0
0
0
ns
Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
a
,
I
Min
KS54AHCT
T.= -55°C to +125°C
Vec=5.0V:!: 10%
Output Enable Time
OC to Q
r-------
Output Disable Time
OC to Q
r-------
Set up Time
Dn before E
Hold Time
Dn after E
ns
ns
ns
ns
ns
pF
--
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC! fin,
t For AC switching test circuits and timing waveforms see section 2,
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltions l
(Input tr ,
T.=25°C
Vee=5.0V
tf~2 ns), AHCT846
KS74AHCT
To= -40°C to +85°C
Vee=5.0V±10%
1------ -
Typ
i
Propagation Delay
E to Q
rE,ropagation Delay
D to Q
Max
Min
Max
tPLH
14
24
32
tpHL
14
24
32
f--------- .-
tpLH
10
17
22
tPHL
10
17
22
r-------
Unit
ns
ns
13
22
26
tpHL
13
22
26
tpLH
13
22
26
tpHL
13
22
26
tPZH
12
20
24
tPZL
12
20
24
tpHZ
12
20
24
tpLZ
12
20
24
tsu
8
10
12
ns
th
0
0
0
ns
Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
Propagation Delay
CLR to Q
!----------i Propagation
PRE to
a
Delay
tpLH
r-------
r-------
Output Enable Time
OC to Q
r----
Output Disable Time
OC to Q
r----
Set up Time
Dn before E
Hold Time
Dn after E
I
Min
KS54AHCT
To= -55°C to +125°C
Vee=5.0V:!: 10%
f--._-- --
--
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee l
ns
ns
ns
ns
pF
pF
fin,
t For AC switching test circuits and timing waveforms see section 2,
c8SAMSUNG
Electronics
422
KS54AHCT
KS74AHCT
4049'4050
'j
Hex Logic Level
Down Converters
FEATURES
DESCRIPTION
• Modified Input structure allows voltages up to 1SV
• Hlgh-Drlve-current Outputs:
IOL=8mA @ VOL=O.SV
• Low power consumption characteristic of CMOS
• Inputs and outputs Interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.SV to S.SV
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +8SoC
KSS4AHCT: - SsoC to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '4049 and '4050 have a modified input protection
structure that enable them to be used as logic level
translators which will convert high level logic to a low level
logic while operating from the low logic supply. For exam·
pie, 0·15V logic can be corverted to 0·5V logic when using a 5V supply. The modified input protection has no diode
connected to Vee. thus allowing the input voltage to exceed the supply. The lower zener diode protects the input from both positive and negative static voltages. In
addition the' 4049 and' 4050 can be used as simple buffersor inverters without level translation.
These devices provide speeds and drive capability
equivalent to their ALSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL. NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
LOGIC DIAGRAMS
'4049
NC
Vee
6Y
1Y
1A
2Y
2A
6A
NC
5Y
3Y
5A
~ lY
lA~.
~ 2V
2A~-V-
~
3A - - - - y v - - 3Y
~~
3A
4Y
404 - - - - - y v - - 4V
GND
4A
J~21J"_.~
504 - - - - y v - - 5Y
~
SA-----yv--SV
'40S0
lA~IV
FUNCTION TABLE
2A~2Y
3A~3V
4A~4V
Output Y
Input
A
'4049
'40S0
H
L
L
H
H
L
c8SAMSUNG
Electronics
~.~
112ll_
5A~5V
6A~6V
423
II
KSS4AHCT
KS74AHCT
404914050
Hex Logic Level
Down Converters
Absolute Maximum Ratings·
Supply Voltage Range Vee •....... -0.5V to +7V
DC Input Diode Current. hK
(VI < -0.5V or VI >' + 15.5V) '- ..... ±20 mA
DC Output Diode Current. "Ioi<'
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins ................ ±125 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vec .............. 4.5V to 5.5V
DC Input & Output Voltages". VIN. VOUT . . OV to Vee
Operating Temperature
Range
. KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times. tr • tf . . . . . . . . . Max 500 ns
.. Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long ex- .
posure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logiC
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
T. =25°C
KS74AHCT
KS54AHCT
T.= -40°C to +85°C Ta = -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20IAA
10=-4mA
Vcc -0.1
3.84
Vec -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL .
10=20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
Maximum Input
Current
liN
iV 1N=15V
±0.1
±1.0
±10.0
.±TO.O
",A
2.0
20.0
40.0
flA
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
!ce
.6. Icc
Vcc Vcc -0.1
4.2
3.98
0
VIN=Vce or GND
VIN=Vee or GND
10UT=0",A
per input pin
VI=2.4V
other Inputs:
at Vec or GND
lOUT = O",A
I
(Input tr , tf~2 ns)., AHCT4049, AHCT4050
=
T. 250C
T.
Symbol Conditions t Vcc=5.0V
KS54AHCT
KS74AHCT
+ 85°C Ta -55°C to +125°C
Unit
Vcc=5.0Vj: 10%
Vee = 5.0V j: 10%
Propagation Delay
-
CL =50pF
tpHL
Input Capacitance
CIN
Powell;Dissipation Capacitance *
Cpo
(per gate)
=
= - 40°C to
Typ
tpLH
±1.0
i
AC ELECTRICAL CHARACTERISTICS
Characteristic
V
Min
Max
Min
Max
7
12
14
7
12
14
ns
5
pF
15
pF
* Cpo determines the no-load dynamiC power diSSipation: Po=Cpo Vee 2 fin·
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
.. Electronics
424
I
il
I
II.
I~
I
KS54HCTLS
KS74HCTLS
00
Quad 2-lnput NAND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
'IOL SmA @ VOL O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +S5°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2·input NAND
gates that perform the Boolean functions Y=A. B or
=
=
PIN CONI=IGURATION
Y=A+B.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
1A~
18~
1A
.1Y
Vee
18
48
1Y
4A
2A
4Y
28
,38
2Y
3A
GND
3Y
2A~
28~2Y
3A~(9)
(8)
(10)
II
3Y
38
4A~
48~···4Y
FUNCTION TABLE
(Each Gate)
Inputs
Output
Y
A
B
H
H
L
L
X
X
L
H
H
c8SAMSUNG
Electronics
427
KS54HCTLS
KS74HCTLS
00
Quad 2 ../nput NAND Gates
Absolute Maximum Ratlngs*
t Power DIssipation temperature derating:
Supply Voltage Range Vee, .... . . . -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V) ..... ±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) .......... ±35 rnA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 125 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN,. VOUT . . OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee-5V± 10% Unless Otherwise Specified)
T.=25°C
Symbol Test Conditions
KS74HCTLS
KS54HCTLS
T.= -40°C to +85°C T.= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OIlA
lo=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum' Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=201lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
IlA
2.0
20.0
40.0
IlA
2.7
2.9
3.0
rnA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
.6. Icc
Vee Vee -0.1
4.2
3.98
0
VIN=Vee or GND
IOUT=OIlA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
IOUT=OIlA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r , tf~6 ns). HCTLSOO
T.=25°C
Vcc=5.0V
KS74 HCTLS
T.= -40°C to +85°C
Vcc=5.0V±10%
Typ
Maximum Propagation Delay
-
tpLH
CL=50pF
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance·
Cpo
15
18
22
10
15
18
22
c8SAMSUNG'
Electronics
ns
pF
pF
15
Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee z
t For AC switching test circuits and timing waveforms see section 2.
~
Unit
Guaranteed Limits
10
5
(per gate)
KS54HCTLS
T.=-55°Cto +125°C
Vcc=5.0V± 10%
fin.
428
KS54HCTLS
KS74HCTLS
01
Quad 2-lnput NAND Gates
with Open-Drain Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L = 8mA @ VOL = O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial· and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2·input NAND
gates with open·drain outputs. Using a suitable pull-up
resistor, these outputs may be connected to other opendrain outputs to implement wired-AND functions.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direcUnterface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
(1.4,10,13)
1Y
Vee
1A
4Y
18
48
2Y
4A
2A
3Y
28
38
GND
3A
: ,2 5 11'D--{>o-ir
8,
y
I
(3,6,9,12)
FUNCTION TABLE
(Each Gate)
Inputs
Output
A
B
H
H
L
L
X
X
L
H
H
cRSAMSUNG
Y
429
01
KS54HCTLS
KS74HCTLS
Quad 2-lnput NANDt;;stes.
with Open~Drain Outputs-
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Supply Voltage Range Vcc, ... . . . . -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI> Vce +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . .
±35 mA
Continuous Current Through
Vee or GND pins . . . . . .
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce . . . . . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: - 55 ° C to + 125 ° C
Max 500 ns
Input Rise & Fall Times, tr , tf
• Absolute Maximum Ratings are those· values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Maximum Low-Level
Output Voltage
VOL
ViN=VIH or VIL
10=20J.(A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current -
hN
VIN=Vec or GND
±0.1
±1.0
±1.0
J.(A
Maximum Output
Leakage Current
loz
VIN=VIH or VIL
VouT=Vec
±0.5
±5.0
±10.0
J.(A
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
J.(A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Ll.lee
0
VIN=Vec or GND
10UT=0J.(A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0J.(A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlonst
(Input t r , tf~6 ns), HCTLS01
T.=25°C
Vcc=5.0V
KS74HCTLS
T. = - 40°C to + 85°C
Vcc=5.0V:!:10%
Typ
Maximum Propagation Delay
-
tpLH
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance·
Cpo
CL=50pF
RL=1kO
(per gate)
KS54 HCTLS
Ta= -55°C to +125°C
Vcc=5.0V± 10%
Unit
Guaranteed Limits
24
30
36
43
15
20
25
30
ns
5
pF
15
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
cRSAMSUNG
430
KS54HCTLS a~
KS74HCTLS
Quad 2-lnput NOR Gates
FEATURES
DESCRIPTION
• Function, pln-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• Hlgh-Drlve-Current outputs:
IOL 8mA @ VOL O.5V
• Inputs and outputs Interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLSc -55°C to +125°C
- Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2·input NOR gates
that perform the Boolean functions Y=A+B or Y=A-S.
PIN CONFIGURATION
LOGIC DIAGRAM
=
=
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
(2)
1A
Vee
4Y
18
48
2Y
4A
1Y
2A
3Y
28
3B
GND
3A
1A~1Y
1B~
2A~5)
(6)
(4)
I
2Y
28
(8)
3A~3Y
3B~
4A~
4B~4Y
FUNCTION TABLE
(Each Gate)
Inputs
I
------B
A
H
X
X
H
L
L
Output
cRSAMSUNG
Y
L
L
H
431
KS54HCTLS
KS74HCTLS
02.
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vee, ........ -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . .
±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee .............. 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vec
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vce or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
T.=25°C
Symbol Test Conditions
KS74HCTLS
KS54HCTLS
T.= -40°C to +85°C T.= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vee -0.1
3.84
Vec -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
",A
2.0
20.0
40.0
",A
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
~Icc
Vee Vee -0.1
3.98
4.2
0
VIN=Vce or GND
10UT=0",A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
lOUT = o",A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input t r , tf~6 ns), HCTLS02
T.=25°C
Vee=5.0V
KS74HCTLS
T.= -40°C to +85°C
Vee 5.0V::I: 10%
=
Typ
Maximum Propagation Delay
tpLH
f---
CL=50pF
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
9
10
KS541HCTLS
+125°C
Vee=5.0V::I: 10%
=-55°C to
Unit
Guaranteed limits
15
18
22
15
18
22
5
(per gate)
T.
pF
15
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
ns
pF
fin.
t For AC switchi.ng test circuits and timing waveforms see section 2.
·cRSAMSUNG
432
KS54HCTLS
KS74HCTLS
03
Quad 2-lnput NAND Gates
with Open-Drain Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current Outputs:
IOL =8mA @ VOL = O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54t:tCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2-input NAND
gates with open-drain outputs. Using a suitable pull-up
resistor, these outputs may be connected to other opendrain outputs to implement wired-AND functions.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
LOGIC DIAGRAM
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
(3.6,8,11)
1A
Vee
18
48
1Y
4A
2A
4Y
28
38
2Y
3A
GND
3Y
;
(1,4,9,12)D----[>o:--1~Y
(2,5,10, 13)
~
I
FUNCTION TABLE
(Each Gate)
Inputs
Output
A
B
Y
H
L
X
H
X
L
L
H
H
dCSAMSUNG
• • Electronics
433
KS54HCTLS
KS74HCTLS
03
Quad 2-lnputNAND Gates
with Open-Drain Outputs
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, hK
(VI"< ,0.5V or VI> Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Va > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Thro.ugh
Vec or GND pins
±125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vce
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VauT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
... Max 500 ns
Input Rise & Fall Times, t r , tf
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
* Absolute Maximum' Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
J'!;
- °
KS74HCTLS ~~.KS54HCTLS
~a.-25 C_ T~_:-40o~_~_+850C Ta=...:-550C !~.:!'"~ Unit
Typ
Minimum High-Level
Input Voltage
r- ---..-----.... -. ----.--.--
Guaranteed limits
Maximum Low-Level
Input Voltage
2.0
2.0
VIH
f------- r----
..
_- f - - - - - - ..- - - -.. -
2.0
V
f---
0.8
0.8
0.8
V
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=VCC or GND
±0.1
±l.O
±1.0
~A
VIN=VIH or VIL
VOUT=VCC
±0.5
±5.0
±10.0
~A
20.0
40.0
~A
2.9
3.0
mA
VIL
1----
VIN=VIH or VIL
Maximum Low-Level
Output Voltage
~-------~
Maximum Input
Current
-~~------
Maximum Output
Leakage Current
r--~------~
Maximum Quiescent
Supply Current
r-------.-.~------
Additional Worst
Case Supply
Current
10=20~A
VOL
- .. ---- ---f--
hN
0
----
f--------~~--~
f---
--
loz
f - - - - - - t--
Icc
._----------
b.lcc
VIN=VCC or GND
10uT=0~A
2.0
---
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
+----
2.7
lauT=O~A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r , tf~6 ns), HCTLS03
Ta ::25°C
Vec=5.0V
Ta
KS741HCTLS
to +85°C
Vee= 5.0V:!: 10%
-= -40°C
Typ
Maximum Propagation Delay
tpLH
CL=50pF
r-----RL=1kO
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per gate)
KS54 HCTLS
Ta= -55°C to +125°C
Vee=5.0V:!: 10%
Unit
Guaranteed Limits
24
28
15
28
30
30
38
ns
38
5
pF
15
pF
* CPD determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
cRSAMSUNG
• • Electronics
434
KS54HCTLS
KS74HCTLS
04
Hex Inverters
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
These devices contain six independent inverters. They perform the Boolean function Y = A .
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
LOGIC DIAGRAM
PIN CONFIGURATION
~-
lA
Vee
lY
6A
2A
6Y
2Y
5A
3A
5Y
3Y
4A
GND
4Y
lA~lY
2A
~
~
2Y
I
f'..-..
3Ai5)
(6)
~3Y
4A~4Y
~(10)
5A~5Y
~~(12)
6A~6Y
FUNCTION TABLE
(Each Inverter)
I
i
Input
Output
A
y
H
L
L
H
c8SAMSUNG
Electronics
435
04
KS54HCTLS
KS74HCTLS
Hex Inverters
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ....... -0.5V to +7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
... Max 500 ns
Input Rise & Fall Times, tr , tf ..
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyondJhem is not implied. Long exposure to these conditions may affect device reUability.
DC ELECTRICAL CHARkCTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V± 10% Unless Otherwise Specified)
Ta =25°C
KS74HCTLS
KS54HCTLS
Ta = -40°C to +85°C Ta = - 55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10 = 20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
IrN
VIN=VCC or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Dolcc
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10uT=0",A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr , tf~6 ns), HCTLS04
Ta =25°C
Vcc=5.0V
KS741HCTLS
Ta= -40°C to +85°C
Vcc=5.0V:t:10%
Typ
I
Maximum Propagation Delay
tpLH
f----
CL=50pF
tpHL
,Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
Unit
Guaranteed limits
9
15
18
22
10
15
,,18 ,
22
pF
15
* Cpo determines the no-load dynamic power dissipation: PO=CPD VCC 2
ns
pF
5
(per gate)
KS54 HCTLS
Ta=-55°C to +125°C
Vcc,=5.0V:t: 10%
fin,
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
436
KS54HCTLS
KS74HCTLS
05
Hex Inverters with Open-Drain O·utputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interfSlce directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "sma" outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain six independent inverters with open·
drain outputs. Using a suitable pull·up resistor, these out·
puts may be connected to other open·drain outputs to im·
plement wired-AND functions.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
LOGIC DIAGRAM
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
(2,4,6,8,10,12)
lA
Vee
1Y
6A
2A
6Y
2Y
SA
3A
SY
3Y
4A
GND
4Y
AI~rY
I
-=-
r=UNCTION TABLE
(Each Inverter)
Input
Output
A
y
H
L
L
H
.c'SAMSUNG
"C E .
lectronlcs
437
KS54HCTLS
KS74HCTLS
05
Hex Inverters with Open-Drain Outputs
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, . .
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI> Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per .Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±35 rnA
Continuous Current Through
Vee or GND pins
± 1 25 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt . .
500 mW
Recommended Operating Conditions
Supply Voltage, Vee . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, tr , tl
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage .to the device may occur.
These are stress ratings only and functional operation
of the device at or beybnd them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Vee=5V± 10% Unless Otherwise Specified)
°
Characteristic
Symbol Test Conditions
_1,
KS74HCTLS
KS54HCTLS
+85°C Ta= ~55°C to +125°C Unit
Guaranteed Limits
~:..:.25_~ T~_= -:.~00C to
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Maximum Low-Level
Output Voltage
VOL
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
j.lA
loz
VIN=VIH or VIL
VouT=Vee
0
-----
Maximum Output
Leakage Current
Maximum Quiescent
Supply Current
Icc
c--------.
Additional Worst
Case Supply
Current
VIN=VIH or VIL
10=20j.lA
10=4mA
10=8mA
.6. Icc
VIN=Vee or GND
10uT=0j.lA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND.
10uT=0j.lA
±0.5
±5.0
±10.0
j.lA
2.0
20.0
40.0
j.lA
2.7
2.9
3.0
mA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr , tl~6 0"5), HCTLS05
To =25°C
Vcc=5.0V
KS74HCnS
Ta=-40°C to +85°C
Vcc=5.0V±10%
Typ
Maximum Propagation Delay
tpLH
~
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
CL=50pF
RL=1kO
Unit
Guaranteed Limits
24
30
36
43
16
22
28
33
5
(per gate)
KS54 HCnS
To= -55°C to +125°C
Vcc=5.0V± 10%
..
15
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2
-
ns
I
pF
I
pF
fin.
t For AC switching test circuits and timing waveforms see section 2.
=SAMSUNG
•• EI~ctronics
438
08
KS54HCTLS
KS74HCTLS
Quad 2-lnput AND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Orive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2-input AND gates.
They perform the Boolean functions Y=A.B or Y=A+B.
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
1A~-..i3)
1A
Vee
1B
4B
1Y
4A
2A
4Y
2B
3B
2Y
3A
GND
3Y
1B~1Y
2A~
2B~2Y
I
3A~_
3B~3Y
4A~
4B~-4Y
FUNCTION TABLE
(Each Gate)
Inputs
1'1
Output
A
B
Y
H
L
H
X
X
L
H
L
L
c8SAMSUNG
Electronics
439
KS54HCTLS
KS74HCTLS
08
Quad 2-lnput AND Gates
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ....... -0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
.. ± 125 mA
Storage Temperature Range, Tst9 ... -65°C to +150°C
Power Dissipation Per Package, Pdt'
500 mW
Recommended Operating Conditions
Supply Voltage, Vee . . . . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vcc
Operating temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf
.. Max 500 ns
Unused inputs must always be tied to an appropriate logiC
voltage level (either Vce or GND)
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vec=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
1--,-----
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vee -0.1
3.84
Vce -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
",A
2.0
20.0
40.0
",A
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
.6.lee
Vee Vee -0.1
4.2
3.98
0
VIN=Vee or GND
10uT=0}JA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
louT=O",A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr , tf~6 ns), HCTLS08
Ta =25°C
Vcc=5.0V
KS74 HCTLS
T.= -40°C to +85°C
Vcc=S.OV±10%
Typ
Maximum Propagation Delay
tpLH
I-----
CL=50pF
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance·
Cpo
Guaranteed Limits
10
15
10
20
22
25
30
ns
pF
15
• Cpo determines the no-load dynamic power dissipation: PO=CPD Vee 2
. t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
.
18
---
5
(per gate)
KS54HCTLS
Ta =-55°Cto +125°C
Unit
Vcc=5.0V± 10%
pF
fin .
440
KS54HCTLS
KS74HCTLS
09
Quad 2-lnput AND Gates
with Open-Drain Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Cur'rent outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V I
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2·input AND gates
with open·drain outputs. Using a suitable pull-up resistor,
these outputs may be connected to other open-drain outputs to implement wired-AND functions.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
LOGIC DIAGRAM
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
r
I
(3.6,8,11)
1A
Vee
18
48
1Y
4A
2A
4Y
28
38
2Y
3A
GND
3Y
:
(1,4,9,12)
(2,5,10,13)
D---1
y
FUNCTION TABLE
(Each Gate)
Inputs
Output
A
B
Y
H
L
H
X
X
L
H
L
L
c8SAMSUNG
.
Electronics
441
KS54HCTLS
KS74HCTLS
09
Quad 2-lnputAND Gates
with Open-Drain Outputs
Absolute Maximum Ratings*
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vec,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI> Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, T51g ••• -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages *, VIN, Your
OV to Vce
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , t;
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
.Symbol Test Conditions
(Vce=5V± 1 0% Unless Otherwise Specified)
Ta=2S0C
---- --------
J
KS74HCTLS
TYP
Minimum High-Level
Input Voltage
Maximum Low-Level
Input Voltage
----
- - - - - _..
VOL
-
V
0.8
liN
VIN=Vec or GND
0
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
±0.1
±1.0
±1.0
V
/AA
----
----
Maximum Output
Leakage Current
loz
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
0.8
--
--f---
VIN=VIH or VIL
10= 2O/AA
10=4mA
10=8mA
_-_._-
Maximum Input
Current
V
2.0
----~
0.8
VIL
Maximum Low-Level
Output Voltage
-
2.0
- - -- - - 1---------
~-~-----
,
Guaranteed Limits
2.0
VIH
KS54HCTLS
_,.a_:::=~~oC to +85°C Ta= -55°C to +125~~ Unit
.6.lec
VIN=VIH or VIL
Vour=Vec
VIN=VCC or GND
10ur=01-lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=01-lA
±0.5
±5.0
±10.0
2.0
20.0
40.0
2.7
2.9
3.0
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditionst
Maximum Propagation Delay
I-----
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
CL=50pF
RL=1kO
Ta=25°C
Vcc=5.0V
KS741HCTLS
Ta= -40°C to +85°C
Vcc=5.0V±10%
KS54HCTLS
Ta= -55°C to +125°C
Vcc=5.0V± 10%
mA
Unit
Guaranteed Limits
26
32
38
45
16
22
28
33
ns
pF
5
(per gate)
/AA
- - 1-------
(Input t r , tf~6 ns). HCTLS09
Typ
tpLH
/AA
---r-
pF
15
(
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
fin.
t For AC switching test circuits and timing' waveforms see section 2.
cSaSAMSUNG
•• Electronics
442
KS54HCTLS
KS74HCTLS
10
Triple 3-lnput NAND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74lS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTlS: -40°C to +85°C
KS54HCTlS: - 55°C to + 125°C
- Package options incl4de "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain three independent 3·input NAND
gates. They perform the Boolean functions Y=A-B-C or
y=A+B+C.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
(1)
1A
Vee
18
1C
2A
1Y
28
3C
2C
38
2Y
3A
GNO
3Y
1A~ 1Y
18
1C
2A
113)
I
(3)
28 ~2Y
(5)
2C
(9)
~~~3Y
(11)
3C
FUNCTION TABLE
r-- Inpu~~ ~~J
(Each Gate)
I
__
ABC
H
L
X
X
H
X
L
X
Output
I
H
X
X
L
=SAMSUNG
• • Electronics
y
L
H
H
H
443
KS54HCTLS
KS74HCTLS
10
Triple 3-lnput NAND Gates
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V) . . .. ±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin,lo
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vce or GND pins. . . .
±125 mA
Storage Temperature Range, Tslg ; .. - 65 ° C to + 150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vce
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf
* Absolute Maximum Ratings are those. values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either VyC or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V± 10% Unless Otherwise Specified)
T8 =25°C
Symbol Test Conditions
KS74HCTLS
KS54HCTLS
T8= -40°C to +85°C T8= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
Vil
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or Vil
10=-20/AA
10=-4mA
Vce -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or Vil
lo= 2O /AA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
+1.0
±1.0
/AA
2.0
20.0
40.0
/AA
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
~Icc
Vce Vcc -0.1
4.2
3.98
0
VIN=Vce or GND
lOUT = O/AA
per input pin
V,=2.4V
other Inputs:
at Vee or GND
10uT=0/AA
AC ELECTRICAL CHARACTERISTICS
Symbol
Characteristic
Conditions t
(Input tr , tf~6 ns), HCTLS10
T.=25°C
Vcc=5.0V
KS74 HCTLS
T8= -40°C to +85°C
Vcc=5.0V±10%
Typ
Maximum Propagation Delay
-
tplH
CL=50pF
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per gate)
Guaranteed Limits
11
15
19
23
11
15
19
23
ns
5
pF
15
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vce 2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
KS541HCTLS
T8=-55°Cto +125°C
Unit
Vcc=5.0V± 10%
fin.
444
11
KS54HCTLS
KS74HCTLS
Triple3-lnput AND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O:5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to + 125°C
These devices contain three independent 3·input AND
gates. They perform the Boolean functions Y=A-B·C or
y=A+B+C.
These devices provide speeds .and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
- Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
LOGIC DIAGRAM
PIN CONFIGURATION
1
1A
Vee
18
1C
2A
1Y
28
3C
2C
38
2Y
3A
GND
3Y
(1)
A~2)
(12)
18 (13)
1C
1Y
(3)
I
2A~4)
(6)
2Y
28
2C
(5)
3A
(9)
38~3Y
3C~
FUNCTION TABLE
(Each Gate)
Inputs
Output
A
B
C
y
H
L
H
H
X
X
X
L
X
X
X
L
H
L
L
L
cS!SAMSUNG
Electronic~
••
445
KS54HCTLS
KS74HCTLS
11
Triple 3-lnput AND Gates
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc,
-0.5Vto +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 rnA
DC Qutput Diode Current, 10K
(Vo < -0.5V or Vo > Vec +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 rnA
Continuous Current Through
Vee or GND pins
. ,,, ,,, ,
± 125 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
ReCommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & OutPl,Jt Voltages·, VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C.
KS54HCTLS: -55°C to + 125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied, Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V± 10% Unless Otherwi,se Specified)
Ta=25°C
Symbol Test Conditions
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Minimum High-Level
Input Voltage
VIH
Maximum Low-Level
Input Voltage
VIL
Minimum High-Level
Output Voltage
VOH
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Vcc -0.1
3.84
Vcc -0.1
3.7
V
f---
VIN = VIH or VIL
10=- 2OIJA
10=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2OIJ A
lo=4mA
lo=8mA
Maximum Input
Current
hN
VIN=VCC or GND
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Guaranteed Limits
Icc
61cc
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
10UT=OIJA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10uT=OIJA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
IJA
2.0
20.0
40.0
IJA
2.7
2.9
3.0
rnA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr , tf~6 ns), HCTLS11
T8 =25°C
Vcc=5.0V
KS74HCTLS
T8 = -40°C to +85°C
Vcc=5.0V±10%
Typ
Maximum Propagation Delay
-
tpLH
CL =50pF
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance·
Cpo
(per gate)
--t---
KS54 HCTLS
T8= -55°C to +125°C
Vcc=5.0V± 10%
Unit
Guaranteed Limits
13
18
22
26
13
18
22
26
ns
5
pF
15
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
=SAMSUNG
• • Electronics
446
KS54HCTLS
KS74HCTLS
12
Triple 3-lnput NAND Gates
with Open-Drain Outputs
FEATURES
DESCRIPTION
- Function, pin-out, speed and drive compa1ibility with
54174LS logic family
- Low power consumption characteristic of CMOS
- High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
- Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
- Wide operating voltage range: 4.5V to 5.5V
- Characterized for operation over industrial and
military temperature ranges:
KS74HCTlS: -40°C to+85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
-, hese devices contain three independent 3-input NAND
gates with open-drain outputs. They perform the Boolean
functions Y=A-B-C or y=A+B+C.
PIN CONFIGURATION
LOGIC DIAGRAM
1A
Vee
18
1C
2A
1Y
28
3C
2C
38
2Y
3A
GND
3Y
Using a suitable pull-up resistor, these outputs may be connected to other open-drain outputs to implement wired-AND
functions.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
I
A~(1'3'9) rr-(12,6,8)y
(2,4,10)
:
(13,5.11)
FUNCTION TABLE
(Each Gate)
Output
Inputs
A
B
C
y
H
H
X
L
X
H
X
X
L
L
H
H
H
L
X
X
••
=SAMSUNG
• • Electronics
447
II
KS54HCTLS
KS14HCTLS.
12
Triple .3-lnput NAND,.Gates
with Open-Drain Outputs
Absolute Maximum Ratings*
t Power Dissipati()n temperature derating:
Plastic Package (N): -;-12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc •....... -0.5V to +7V
DC Input Diode Current. hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 rnA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 rnA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vcc +0.5V) . . . . . .
±35 rnA
Continuous Current Through
Vec or GND pins . . . . . . . . . . . . . . .. ± 1 25 rnA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage. Vcc
4.5V to 5.5V
DC Input & Output Voltages·. VIN. VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times. tr • tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V±10% Unless Otherwise Specltled)
Ta=25°C
Symbol Test Conditions
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-i..evel
Input Voltage
VIL
0.8
0.8
0.8
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2O/AA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
/AA
Maximum Output
Leakage Current
loz
VIN=VIH or VIL
VOUT=VCC
±0.5
±5.0
±10.0
/AA
2.0
20.0
40.0
/AA
2.7
2.9
3.0
rnA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
0
'vIN=VCC or GND
louT=O/AA
per input pin
VI=2.4V
Ll.lcc other Inputs:
at Vcc or GND
louT=O/AA
Icc
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr • tl";6 ns). HCTLS12
Ta =25°C
Vcc=5_0V
KS74 HCTLS
KS54 HCTLS
Ta= -40°C to +85°C Ta = - 55°C to + 125°C
Unit
Vcc=5_0V± 10%
Vcc=5.0V±10%
Typ
Maximum Propagation Delay
tpLH
t----
tpHL
o
Maximum Input Capacitance
CIN
Power Dissipation Capacitance·
Cpo
CL=50pF
RL =1 kll
(per gate)
Guaranteed Limits
26
32
38
45
16
22
28
33
ns
5
pF
15
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
448
KS54HCTLS
KS74HCTLS
14
Hex Schmitt-Trigger Inverters
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 rnA @ VOL = O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These Schmitt-trigger devices contain six independent inverters. They perform the Boolean function Y=A.
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
lA
Vee
lY
6A
2A
6Y
2Y
5A
3A
5Y
3Y
4A
GND
4Y
lA~lY
2A
~
I
2Y
3A~3Y
4A
5A
6A
~
~
~
.
4Y
5Y
6Y
FUNCTION TABLE
(Each Inverter)
Input
Output
A
y
H
L
L
H
c8SAMSUNG'
Clft,..+ ..__ i_,..
449
14
KS54HCTLS
KS74HCTLS
Hex Schmitt-Trigger Invert,rs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0;5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
± 125 mA
Vee or GND pins .........
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vcc
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Ta =25°C
Test Conditions
Minimum High-Level
Output Voltage
VOH
VIN=VIH or Vll
IO=-2o/AA
lo=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or Vll
10=201lA
10=4mA
lo=8mA
(Vcc=5V± 1 0% Unless Otherwise Specified)
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Vcc Vce -0.1
4.2
3.98
Vce -0.1
3.84
Vcc -0.11
3.7
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
0
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
IlA
Maximum Quiescent
Supply Current
Icc
VIN=VCC or GND
IOUT=OIlA
2.0
20.0
40.0
Il A
per input pin
VI=2.4V
other inputs:
at Vcc or GND
IOUT=OIlA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
6/cc
DC ELECTRICAL CHARACTERISTICS
Ta=25°C
Characteristic
Positive-Going
Symbol
VT+
Threshold Voltage
Negative-Going
VT-
Threshold Voltage
Hysteresis
(VT+-VT-)
c8~~~SUNG
VH
Test Conditions
KS74HCTLS
KS54HCTLS
Unit
Ta= -40°C to +85°C Ta= -55°C to +125°C
Min Max
Min
Max
Min
Vec=4.5V
1.2 1.9
1.2
1.9
1.2
1.9
Vce=5.5V
1.4 2.1
1.4
2.1
1.4
2.1
Vcc=4.5V
0.5 1.2
0.5
1.2
0.5
1.2
Vcc=5.5V
0.6 1.4
0.6
1.4
0.6
1.4
vcc=4.5V
0.4 1.4
0.4
1.4
0.4
1.4
Vce=5.5V
0.4 1.5
0.4
1.5
0.4
1.5
Max
V
V
V
450
KS54HCTLS
KS74HCTLS
14
Hex Schmitt-Trigger Inverters
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Input tr , t,<6 ns), HCTLS14
Ta=25°C
Vcc=5.0V
Conditionst
KS74 HCTLS
Ta= -40°C to +85°C
Vcc=5.0V± 10%
KS54 HCTLS
Ta= -55°C to +125°C
Vcc=5.0V± 10%
Unit
~~-
Typ
Maximum Propagation Delay
tpLH
f-------
15
CL=50pF
---
16
tpHL
CIN
Power Dissipation Capacitance *
Cpo
25
30
28
33
~~-
22
----
~-
Maximum Input Capacitance
Guaranteed Limits
20
~-
5
--
(per gate)
~.--
~~
15
ns
-----
..-
pF
- - - f-~-
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
I
=8SAMSUNG
Electronics
451
KS54HCTLS
KS74HCTLS
20
Dual 4-lnput NAND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristi~ of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to + 12.5°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain two independent 4-input NAND
gates. They perform the Boolean functions Y - A· B· C. D
or Y=A+'B+c+B in positive logic.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
1A
1A
Vee
1B
20
2C
1B
NC
1C
2B
2A
10
NC
1C
10
1Y
GNO
2Y
1Y
2A
2B
2Y
2C
20
FUNCTION TABLE
(Each gate)
INPUTS
f---------
A
B
C
D
H
H
X
L
X
X
H
X
X
L
X
H
X
X
X
L
L
X
X
X
OUTPUT
Y
L
H
H
H.
H
452
20
KS54HCTLS
KS74HCTLS
Dual 4-lnput NAND Gates
Absolute Maximum Ratings·
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vec +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vce +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
• (-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
K$54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logiC
voltage level (either Vec or GNO)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20I-/A
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2OI-/A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
I-/A
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
I-/A
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
D.lee
Vee Vee -0.1
4.2
3.98
0
VIN=Vee or GND
10uT=01-/A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
louT=OI-/A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r , tf~6 ns), HCTLS20
T.=25°C
Vee=5.0V
Typ
Maximum Propagation Delay
Any Input to Y
tpLH
r--tpHL
Maximum Input Capacitance
CIN
Power DisSipation Capacitance *
Cpo
CL =50pF
--I-
T.=-55°Cto +125°C
Vee=5.0V± 10%
Unit
Guaranteed Limits
11
15
19
23
11
15
19
23
ns
5
pF
15
pF
- - r-----
(per gate)
KS54 HCTLS
KS74 HCTLS
T. = - 40°C to + 85°C
Vee = 5.0V ± 10%
* Cpo determines the no-load dynamic power dissipation: PO=CPD Vce 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
cSCSAMSUNG
• • Electronics
453
I
KS54HCTLS,
KS74HCTLS
21
Dual 4-lnput AND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain two independent 4-input AND gates.
They perform the Boolean functions Y = A. B. C. D or
Y=A+B+C+D in positive logic.
PIN CONFIGURATION
1A
1B
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain.
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
)
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
Vee
2D
NC
2C
NC
2B
2A
1C
10
1Y
GNO
2Y
1Y
1C
2A-:";"":""-'---,
2B
2Y
2C
20 --'--'---'
FUNCTION TABLE
(Each gate)
INPUTS
A
B
H
L
X
X
X
H
X
L
X
X
C
H
X,
X
L
X
OUTPUT
0
Y
H
X
X
X
L
H
L
L
L
L
=8SAMSUNG
Electronics
454
21
KS54HCTLS
KS74HCTLS
Dual 4 ..lnput AND Gates
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V) .
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 rnA
Continuous Current Through
Vcc or GND pins
± 125 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vce
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , t,
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vec=5V± 1 0% Unless Otherwise Specified)
KS74HCTLS
?~S54HCTLS
Ta= -40°c:_t()2!~oc: Ta= -~~oC to__~__~~oC Unit
Ta=25°C
1------,---'
Typ
Minimum High-Level
Input Voltage
Maximum Low-Level
Input Voltage
Additional Worst
Case Supply
Current
---
-
-
2.0
----
-~-
0.8
VOH
VOL
~--
liN
VIN = VIH or VIL
10=- 2OilA
10= -4mA
VIN=VIH or VIL
10=20ilA
10=4mA
10=8mA
1------.
0
1-.
VIN=Vce or GND
V
2.0
-~-
...
-- j - - - - - _ . -..
O.B
Vec Vcc -0.1
4.2
3.98
..... - - -
Vee -0.1
3.84
V
0.8
_..
-
- - - - - - --
f-~-
Vee -0.1
3.7
V
_._- t - . - - - - - - .
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
il A
2.0
20.0
40.0
il A
2.9
3.0
rnA
_.
. _ - - c-.
VIN=Vee or GND
10uT=OilA
1-- .._ - - per input pin
VJ=2.4V
L::,.lcc other Inputs:
at Vce or GND
10uT=OilA
Icc
------
.. -
-'
2.7
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
:,1
(Input t r , t,<6 ns), HCTLS21
~T.;KS7'HCTLS
T.= -400C to +85°C
Conditions t
-
T.=25°C
Vcc=5.0V
~
Vcc=5.0V±10%
-~.----
Typ
Maximum Propagation Delay
Any Input to Y
tpLH
r------
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
CL =50pF
18
12
18 _._ ..._ -22- - -' -
1-------t - -
- - - - [-.--t-
5 I
(per gate)
I
cSCSAMSUNG
KS5.Hcns
Ta= -55°C to +125°C
Vcc=5.0V± 10%
-
~-----.
Unit
---
Guaranteed Limits
12
_.-
22
- - - - - t---~
27
-~----
-
-
27
~
~~-----
~~~
pF
- - - - - - j----- - - - - - - - - - t -
15
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
• • Electronics
....
- - t - - - - - - -.. -
Maximum Low-Level
Output Voltage
---".-.--~
1----.
VIL
Minimum High-Level
Output Voltage
Maximum Quiescent
Supply Current
2.0
VIH
-.~
e--------Maximum Input
Current
Guaranteed Limits
pF
455
I
KS54HCTLS
KS74HCTLS
22
Dual 4-lnput NAND Gates
with Open-Drain Outputs
FEATURES
DESCRIPTION
- Function, pin-out, speed and drive compatibility with
54174LS logic family
- Low power consumption characteristic of CMOS
- High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
- Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
- Wide operating voltage range: 4.5V to 5.5V
- Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain two independent 3-input NOR gates.
gates. These ga.tes perform the Soolean fucntions
Y=A-S-C-D or Y=A+B+C+D in positive logic. The
open-drain outputs require pull-up resistors to perform
correctly. They many be connected to other open-drain
outputs to implement active low wired-OR or active high
wired-AND functions.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components .
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
1A
Vee
A
16
20
6
NC
2C
C
1C
NC
0
10
28
1Y
2A
GNO
2Y
(1.9)
(2.10)
(4.121
(5.13)
~
r
v
FUNCTION TABLE
(Each gate)
INPUTS
A
B
C
0
OUTPUT
Y
H
L
X
X
X
H
X
L
X
X
H
X
X
L
X
H
X
X
X
L
L
H
H
H
H
c8SAMSUNG
Electronics
456
KS54HCTLS
KS74HCTLS
22
Dual 4-lnput NAND Gates
with Open-Drain Outputs
Absolute Maximum Ratings*
Supply' Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/ °C from 65 ° C to 85 ° C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages *, VIN, Your
OV to Vee
Operating" Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vec=5V± 10% Unless Otherwise Specified)
Ta=25°C
Test Conditions
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +~ Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20J.lA
lo=4mA
lo";8mA
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
J.lA
Maximum Output
Leakage Current
loz
VIN=VIH or VIL
Vour=Vee
±0.5
±5.0
±10.0
J.lA
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
/-I A
2.7
2:9
3.0
mA
Additional Worst
Case Supply
Current
.6.lcc
0
VIN=Vee or GND
lour=O/-IA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour=O/-IA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr , tf~6 ns), HCTLS22
T.=25°C
Vcc=5.0V
KS74 HCTLS
T. = -40°C to +85°C
Vcc=5.0V±10%
Typ
Maximum Propagation Delay
Any Input to Y
~
CL=50pF
tPHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per gate)
KS54 HCTLS
T.= -55°C to +125 O C
Vcc=5.0V± 10%
Unit
Guaranteed Limits
26
33
40
47
15
20
25
30
ns
5
pF
15
pF
.. Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fin.
t For AC switching test circuits and timing waveforms see section 2.
cRSAMSUNG
• • Electronics
457
I
KS54HCTLS
KS14HCTLS
27
Triple 3-lnput NOR Gates
FEATURES
DESCRIPTION
e Function, pin-out, speed and drive compatibility with
54/74LS .Iogic family
e Low power consumption characteristic of CMOS
e High-Drive-Current outputs:
IOL=8 mA @ VOL =O.5V
e Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
e Wide operating voltage range: 4.5V to 5.5V
e Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to + 125°C
• Rackage options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain two independent 3·input NOR gates.
They perform the Boolean functions Y=A+B+C or
y=,A.egeC in positive logic.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds _ and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground .
1A
lA
Vee
18
1C
2A
IY
28
3C
2C
38
2Y
3A
GNO
3Y
(1)
"IJD
(12)
1Y
1C (13)
2A~
2B~2Y
2C
(5)
3A
(9)
3C
(11)
.
3A~3V
FUNCTION TABLE
(Each Gate)
INPUTS
OUTPUT
A
B
C
Y
H
X
X
L
X
H
X
L
X
X
H
L
L
L
L
H
c8SAMSUNG
Electronics
458
KS54HCTLS
KS74HCTLS
27
Triple 3-lnput NOR Gates
Absolute Maximum Ratings*
Supply Voltage Range Vcc,
-0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -'-0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, T519' .. -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vcc
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V±10% Unless Otherwise Specified)
Ta= 25°C
Test Conditions
KS74HCTLS
KS54HCTLS
1a= -40°C to +85°C Ta= -55°C to +125°C Unit
--
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20fJA
10= -4mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN = VIH or VIL
10=20fJA
10=4mA
10=8mA
0.1
0.26
0.39
0:1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
fJA
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
fJA
2.7
2.9
3.0
~nput
Additional Worst
Case Supply
Current
.6lcc
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
10uT=OfJA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10uT=OfJA
Symbol
Conditions t
(Input t r , tf~6 ns), HCTLS27
Ta=25°C
Vcc=5.0V
KS74HCTLS
Ta= -40°C to +85°C
Vcc=5.0V::!:10%
Typ
Maximum Propagation· Delay
Any Input to Y
tPLH
I-----------
CL =50pF
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per gate)
...
I'
AC ELECTRICAL CHARACTERISTICS
Characteristic
I-J
KS54 HCTLS
T. = -55°C to +125°C
Vcc=5.0V::!: 10%
Unit
Guaranteed Limits
11
15
19
23
13
15
19
26
ns
5
pF
15
pF
* CPO determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
cRSAMSUNG
• • Electronics
459
I
KS54HCTLS
KS74HCTLS
30
-B-Input Nand Gate
FEATURES
DESCRIPTION
• Function, pifH)ut, speed and drive compatibility with
54/74lS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10l =8 mA @ VOL =D.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.SV to 5.SV
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package' options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '30 contains a single a-input NAND gate. It performs
the boolean functions (in positive logic):
PIN CONFIGURATION
LOGIC DIAGRAM
Y-A·B·C·b·E·F,G·R
Y=A+B+E+D+E+F+G+R
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
AU inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
A
A
Vee
B
NC
C
H
0
G
2
3
4
E
B
C
8
6
F
NC
y
GNDI
11
12
FUNCTION TABLE
Output Y
Inputs A Through H
All Inputs
One or more inputs
H
L
c8SAMSUNG
Electronics
L
H
460
KS54HCTLS
KS74HCTLS
30
8-lnput Nand Gate
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vee. . ...... -0.5V to + 7V
DC Input Diode Current. hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
±125 mA
Vee or GND pins. . . . . . . . . . . . .
Storage Temperature Range. Tstg . . . - 65 ° C to + 150 ° C
Power Dissipation Per Package. Pdt ...... 500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vee . . . . . . . . . . . .. 4.5V to 5.5V
DC Input & Output Voltages *. VIN. VOUT . . OV to Vcc
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times. t r • tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta = - 55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20j.lA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20j.lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
j.lA
2.0
20.0
40.0
j.lA
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
~Iee
Vee Vec -0.1
4.2
3.98
VIN=Vce or GND
10uT=Oj.lA
Iper input pin
VI=2.4V
lother Inputs:
:at Vee or GND
10UT=Oj.lA
AC ELECTRICAL CHARACTERISTICS. (Input tr • t~6
Characteristic
Symbol
Conditions t
ns). HCTLS30
KS54HCTLS
KS74HCTLS
Ta=25°C
Ta = -40°C to +85°C Ta = -55°C to +125°C
Vcc=5.0V
Unit
Vcc=5.0V:!:10%
Vcc=5.0V:!: 10%
Typ
Guaranteed Limits
)
11
15
19
22
tpHL
11
15
19
22
Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
5
15
Propagation Delay
~
CL=50pF
..
"
ns
pF
pF
* Cpo determines the no-load dynamiC power diSSipation: Po=Cpo Vee' fin .
t For AC switching test circuits and timing waveforms see section 2.
cHSAMSUNG
461
I
KS54HCTLS 3~~
KS74HCTLS ~
Quad 2-lnput OR Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs;
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V tol 5.5V
• Characterized .for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include" small outline" packages
(Available Tape & ~eel), standard DIPs.
These devices contain four independent 2-input OR gates.
They perform the Boolean functions Y = A + B or Y = A. B.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damaged due
to static discharge by internal diode clamps to Vee and
ground.
1)
1A
Vee
1B
4B
1Y
4A
2A
4Y
2B
3B
2Y
3A
GND
3Y
~
(3)
1A (2)
1B
1Y
2A~
2B~2Y
3A~3Y
3B~
4A(~2)
(11)
(13)
4B·
4Y
FUNCTION TABLE
(Each Gate)
Inputs
Output
A
B
y
H
X
L
X
H
L
H
H
L
c8SAMSUNG
EI~drnni~~
462
32
KS54HCTLS
KS74HCTLS
Quad 2-lnput OR Gates
Absolute Maximum Ratings*
Supply Voltage Range Vcc,
-0.5V to +7V
DC Input Diode Current, 11K
(VI < -O.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C ~ +125°C
Max 500 ns
Input Rise & Fall Times, tr,t,
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logiC
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
. These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Vcc=5V± 10% Unless Otherwise Specified)
D
Characteristic
Symbol
Ta=25 C
Test Conditions
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85 D C Ta= -55 D C to +125 D C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vcc -0.1
3.84
Vcc -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
/-I A
2.0
20.0
40.0
/-I A
2.7
2.9
3.0
mA
Minimum High-Level
Output Voltage
VOH
VIN = VIH or VIL
10=-20/-IA
10=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/-lA
10=4mA
10=8mA
Maximum Input
Current
liN
VIN=VCC or GND
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
.t.lcc
Vcc Vcc -0.1
3.98
4.2
0
VIN=VCC or GND
10uT=O/-lA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10uT=O/-lA
AC ELECTRICAL CHAR.ACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr,
T.=25°C
Vee=5.0V
t,~6 ns), HCTLS32
KS74 HCTLS
T.= -40°C to +85°C
Vec= 5.0V ± 10%
Typ
Maximum Propagation Delay
-
tpLH
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
13
Unit
Guaranteed Limits
22
CL=50pF 1-------22
13
(per gate)
KS54 HCTLS
T.= -55°C to +125°C
Vee=5.0V± 10%
25
28
25
28
ns
5
pF
15
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
1=1",('trnni('~
.463
I
KS54HCTLS
KS74HCTLS
42
BCD.,to Decimal Decoder
FEATURES
DESCRIPTION
•
•
•
•
The' 42 decoder accepts for active· high BCD inputs and
provides 10 mutually exclusive active· low outputs, as
shown by logic symbol or diagram: The active·low outputs facilitate addressing other MSI units with active-low
input enables.
•
•
•
•
•
•
Full decoding of Input Logic
All outputs are High for Invalid BCD Conditions
Also for application as 3-Line to 8-Line Decoders
Fun~tion, pin-out, speed and drive compatibility with
54/74LS logic family
Low power consumption characteristic of CMOS
High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over' industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
The logic design of the' 42 ensures that all outputs are
high when binary codes greater than nine are applied to
the inputs.
The most significant input, D, produces a useful inhibit function when the' 42 is used as a 1-of-8 decoder. The D input can also be used as the Data input in an 8-output
demultiplexer application.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
Vee
A
B
LOGIC DIAGRAM
C
D
9
GND
FUNCTION TABLE
Outputs
Inputs
No.
D
C B A
0
1
2
3
4
L
L
L
L
L
L
L
L
L
L
L
H
H
H L
5
6
7
L
L
L
H L
H
H
H H
H L L
H L L
L
8
9
H
INVALID
H
H
H
H
L
H
L
H
L
0 1 2 3 4 5 6 7 8 g
H H H
H H H
H H H
H H H
L H H
H H H
H H H
H H H
H H H
H H H
H, H H L H
H H H H L
H H H H H
H H H H H
H H H H H
H H H
H H H
L H H
H L H
H H L
L hi H H
L H H
H L H
H H L
H H H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H L
H H
H L L
H H L
H H H
H
H
H
H
H
H H
H H
H H
H H
H H
H
L
L
H
L
cRSAMSUNG
....
H H H
H H H
H H H
H H H
H H H H H H H
H H H H
H H H H
H H H H
H H H H
464
KS54HCTLS
KS74HCTLS
4'1)
BCD-to Decimal Decoder
~
Absolute Maximum Ratings*
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, hK
(V, < -0.5V or V, > Vcc +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Va < -0.5V or Va > Vcc +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.9V < Va < Vcc +0.5V)
±35 rnA
Continuous Current Through
Vce or GND pins
± 125 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , Y,N, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vce=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Test Conditions
KS74HCTLS
KS54HCTlS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Levei
Input Voltage
V,H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V~L
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/AA
lo=-4mA
Vce -0.1
3.84
Vee -0.1
3.7
V
VOL
VIN=V'H or VIL
lo= 2O/AA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
/AA
B.O
80.0
160.0
/AA
2.7
2.9
3.0
rnA
Maximum Low-Level
Output Voltage
Maximum Input
Current
hN
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
~Icc
Vec Vee -0.1
4.2
3.98
0
--
VIN=Vce or GND
V'N=Vce or GND
louT=O/AA
per input pin
V,=2.4V
other Inputs:
at Vec or GND
louT=OJAA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditionst
(Input tr , tf~6 ns). HCTLS42
Ta =25°C
Vcc=5.0V
KS74 HCTLS
Ta= -40°C to +85°C
Vcc=5.0V±10%
Typ
Maximum Propagation Delay
Any Input to Y
tpLH
t---
Maximum Input Capacitance
Power Dissipation Capacitance *
CL=50pF
tpHL
C'N
Cpo
KS54 HCTLS
Ta= -55°C to +125°C
Vcc=5.0V± 10%
Unit
Guaranteed Limits
19
25
32
38
19
25
32
38
5
(per gate)
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
·465
I
51'58
/-
KS54HCTLS
KS74HCTLS
Dual AND-O.R-/nvert Gates
and Dual AND-OR Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• ,Low power consumption characteristic of CMOS
- High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
- Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
- Wide operating voltage range: 4.5V to 5.5V
- Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to + 125°C
The '51 performs the following Boolean functions:
1 Y=(1 A-1 B-1 C)+(1 D-1 E-1 F)
2Y=(2A-2Bl+(2C-2D)
- Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
LOGIC DIAGRAMS
1A
Vee
2A
1C
28
18
1F
2C
20
2Y
1E
10
GNO
1Y
The '58 performs:
1 Y = (1 A- 1 B-1 C) + (1 D - 1 E - 1 F)
2Y=(2A-2B)+(2C-2D)
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
(1)
'51
1A
18
1C
10
1E
1F
2A
28
2Y
2C
20
FUNCTION TABLES
Output 1Y
Inputs
1A
18
1C
10
1E
1F
'51
'58
H
X
H
X
H
X
X
X
X
H
H
Any other combination
H
L
L
H
H
H
L
1Y
2A
28
Output 2Y
Inputs
2A
28
2C
20
'51
'58
H
H
X
X
L
L
H
H
H
L
X .
X
H
H
Any other combination
=8SAMSUNG
Electronics
----,'-----~
2Y
2C
20
-----1L--~
466
51158
I.
KS54HCTLS
KS74HCTLS
Dual AND-DR-Invert Gates
and Dual AND-OR Gates
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipatton temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to + 125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
°
Ta=25 C
f---.
KS54HCTLS
Ta= -400C to +85°C Ta= -55°C to +125°C Unit
------------.-
Typ
Minimum High-Level
Input Voltage
2.0
2.0
~~-
Maximum Low-Level
Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
Current
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
0_8
VIL
VOH
VOL
hN
Vce Vee -0.1
4.2
3.98
VIN=VIH or VIL
10=20J-lA
10=4mA
10=8mA
0
VIN=Veeor GND
-------- - _ .
------
--
--.~---
Icc
--+-_.
tl.1cc
-----
±1.0
2.0
V
-
V
J-IA
- - ~----
40.0
----------
2.9
---
--I--
------
±1.0
- - - - - - -f - - -
AC ELECTRICAL CHARACTERISTICS
_. +-----
--',-
-------.~-----
20.0
2.7
.. _ - - -
0.1
0.4
--
VIN=Vee or GND
10uT=OJ-lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10UT=OJ-lA
--~-.-
I
V
---
----
----
Vee -0.1
3.7
._-
0.1
0.33
0.5
±0.1
----
0.8
--
Vee -0.1
3.84
0.1
0.26
0_39
V
----
0.8
--c-------
VIN = VIH or VIL
10=-20J-lA
10= -4mA
-~--
Guaranteed Limits
2.0
VIH
J
_~S74HCTLS
---~---
3.0
J-IA
~---
mA
(Input t r , tf~6 ns), HCTLS51, HCTLS58
_ 2 :~,
KS74HCTLS
KS54 HCTLS
Ta- 5 C Ta= -400C to +85°C [Ta= -55°C to +125°C
Vcc=5.0V
Vcc=5.0V:t10%
Vcc=5.0V:t 10%
!
Characteristic
Symbol
Conditionst
f---- -
----.--.----
Typ
Maximum Propagation Delay
tpLH
1----
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
13
18
CL =50pF r------ t--13
18
---
23
23
27
- -- - - - - - - - - 27 .
15
"";, I
ns
_.
5
(per gate)
------------
Guaranteed Limits
pF
1
pF
* CPO determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
467
I
J\
KS54HCTLS '73,.
KS74HCTLS I,
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear .
FEATURES
DESCRIPTION
• Function, pil'l-out, speed and drive compatibility with
54/74LS logic family'
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOl =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V t05.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to ~ 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain two independent J-K negative-edgetriggered flip-flops. A low level at CLR input resets the outputs regardless of the levels of the other inputs. When CLR
is inactive (high), data at the J and K inputs meeting the
setup time requirements are transferred to the outputs on
the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to
the rise time of the clock pulse. Following the hold time
interVal, data at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile flip-flops
can perform as toggle filp-flops by tying J and K high.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any externarcomponents.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
FUNCTION TABLE
Inputs
Outputs
1ClK
1J
1CLR
10
CLR
CLK
J
K
Q
Q
1K
10
L
H
H
H
H
H
X
X
L
H
L
H
X
X
L
L
H
H
X
L
H
00
0
Vee
GND
2CLK
2K
2CLR
20
2J
2Q
.I.I.I.I-
H
0
H
L
L
H
TOGGLE
00
00
LOGIC DIAGRAM
CLR __________________________. -__________________~------_.
o
K
c
c8SAMSUNG
Electronics
468
KS54HCTLS "7~ A
KS74HCTLS I ~11
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
. DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Va > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Va < Vee +0.5V)
±35 mA
Continuous Current Through
Vec or GND pins
± 1 25 mA
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
• Absolute Maximum Ratings are those values beyond
which· permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always betied to an appropriate logic
voltage level (either Vce or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
VIN=VIH or VIL
Minimum High-Level
Output Voltage
VOH
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
hN
10=-20~A
10=-4mA
Vee Vee -0.1
4.2
3.98
VIN=VIH or VIL
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
lee
..6.lcc
lo=4mA
lo=8mA
"'0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=Vee or GND
±0.1
±1.0
±1.0
~A
4.0
40.0
80.0
fAA
2.7
2.9
3.0
mA
10=20~A
VIN=Vee or GND
louT;=O~A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
louT=OfAA
=8SAMSUNG
Electronics
0
469
I
KS54HCTLS 7~A
KS74HCTLS I ~11
Dual J-K Negative-Edge-Triggered
Flip-FlOps with Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r ,
tf~6 ns), HCTlS73A
KS74HCTLS
KS54HCTLS
Ta =25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Guaranteed Limits
Maximum Clock Frequency
f max
40
30
25
21
Maximum Propagation Delay,
ClK to Q or Q
tpLH
!----------
15
20
25
30
15
20
25
30
Maximum Propagation Delay,
- ClR to Q or Q
!----------
---
l
tpHL
CL=50pF
tpLH
15
20
25
30
tpHL
15
20
25
30
10
13
17
20
10
13
17
20
a
a
0
0
10
13
17
20
10
13
17
20
J or K
Minimum Setup
Time before ClK~ I ClR Inactive
tsu
Minimum Hold Time,
J or K after ClK~
th
--
- -
-~--
Minimum Pulse
Width
~~
High or low
ClR low
Maximum Input Capacitance
--
Power Dissipation Capacitance *
- - ----
ElectrOnics
ns
ns
-ns
(per flip-flop)
ns
pF
5
CIN
pF
40
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee'
t For AC switching test circuits and timing waveforms see section 2 .
.c'SAMSUNG
-0
.
ns
----
tw
Cpo
MHz
fin.
470
KS54HCTLS
KS74HCTLS
7.A A
Dual D-Type Positive-Edge-Triggered
Flip-Flops with Preset and Clear
6fM
FEATURES
DESCRIPTION
• Function, pin-Qut, speed and drive compatibility with
54/74lS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL=O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTl& -40°C to +85°C
KS54HCTLS: - 55 ° C to + 125 ° C
• Package options include "small outline" pack~ges
(Available Tape & Reel), standard DIPs.
These devices contain two independent positive-edgetriggered D-type flip-flops. Each flip-flop has its own data,
clock, preset and clear inputs and complementary Q and
Q outputs_ The preset and clear inputs are active-low and
operate independently of the clock. Data at the D input is
transferred to the Q outputs on the positive transition of
the clock, provided setup requirements have been met.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components .
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to V cc and
ground.
FUNCTION TABLE
PIN CONFIGURATION
i
Inputs
~~-PRE -~-- CLR--~--
-~-~--
I
1CLR
Vee
10
2CLR
2D
2CLK
1CLK
1PRE
10
2PRE
2Q
10
GND
20
,l
i
I
H
Ii l
I
H
H
H
H
H
H
l
l
H
H
H
H
H
Outputs
a
elK
D
I
Q
X
X
X
t
X
I
x
x
I
i
H
l
l
H
H*
H*
H
L
L
H
No Change
No Change
No Change
L
H
H
L
X
X
X
--j
I
i
i
I
!
* Both outputs will remain high as long as PRE and CLR are low,
but the output states are unpredictable if PRE and CLR go high
simultaneously.
LOGIC DIAGRAM
PRE--------------------------~------~
CLK~;
D
o
---------1
arn---------------~--------------------------~
-.c:
-c: SAMSUNG
EIectronlcs
.
471
I
KS54HCTLS
KS74HCTLS
,,~A
Dual D-Type Positive-Edge-Tr(ggered
Flip-Flops with Preset and Clear
7-,'
Absolute Maximum Ratings*
Supply Voltage Range Vee, " " ' " -0.5V to +7V
DC Input Diode Current, 11K
(VI < -0.5V or VI> Vce +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V <"Vo < Vce +0.5V)
±35 mA
Continuous Current Through
Vec or GND pins, .
±125 mA
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
vol~age level (either Vce or GND)
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voitages*, VIN, VOUT
OV to Vec
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: --:55°C to +125°C
Max 500 ns .
Input Rise & Fall Times, t r , tf
DC ELECTRICAL CHARACTERISTICS
C haracteri stic
Symbo1
(Vec=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
I
KS74HCTlS
KS54HCTlS
Ta =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
M'inimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2Of.4A
10=-4mA
Vcc -0.1
3.84
Vce -0.1
3,7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20f.4A
10=4mA
10=8mA
0, I
0.26
0,39
0.1
0.33
0,5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
/AA
4.0
40.0
80.0
/AA
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
.t:.lcc
VIN=VC;C or GND
louT=O/AA
per input pin
VI=2.4V
other Inputs:
at Vec or GND
10uT=0/AA
··qsSAMSUNG
f:lectronics
Vcc Vcc -0.1
4.2
3.98
0
I
472
KS54HCTLS
KS7-4HCTLS
74A
Dual D-Type Posltlve-Edge-Triggered
Flip-Flops with Preset and Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Input t r , tf~6 ns), HCTlS74A
KS54HCTLS
KS74HCTLS
T.=25°C T.= -40°C to +85°C T.=-55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V±10%
Vcc=5.0V± 10%
Conditions t
Typ
Guaranteed Limits
Maximum Clock Frequency
f max
40
30
25
20
Maximum Propagation Delay,
ClK to Q or Q
tpLH
18
25
31
37
18
25
31
37
18
25
31
37
18
25
31
37
10
13
17
20
10
13
17
20
0
0
0
0
8
15
20
25
8
15
20
25
Maximum Propagation Delay,
PRE or ClR to Q or Q
I
Data
Minimum Setup
Time before ClK t PRE or ClR Inactive
I
Minimum Hold Time,
J or K after ClK.j,
Minimum Pulse
Width
IClK High or low
IPRE or ClR low
r----------
tpHL
tpLH
r----------
tpHL
tsu
th
tw
CL=50pF
MHz
ns
----
-
ns
ns
ns
ns
Maximum Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo (per flip-flop) 40
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
I
dCSAMSUNG
• • Electronics
473
KS54HCTLS
KS74HCTLS
75/77
4-Bit Bistable Latches
FEATURES
DESCRIPTION
• Function,' pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8mA @ VOL .=O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS; - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '75 and '77 consist of 4 high-speed D-type latches
that can be used as temporary storage for binary information between processing units. The '75 features complementary Q and Q output while the '77 features single
nail output. These devices are ideal for high component
density application.
The latches are transparent: when the enable (E) is high,
the Q output will follow the data input. When the enable
goes low, the output latches at the level that was set up
at the D-input.
These device provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
PIN CONFIGURATION
FUNCTION TABLE
. '77
'75
10
10
10
10
Inputs
10
20
20
20
20
20
D
E
Q
Q*
E",
E3 ·4
E'.2
Vee
E'·2
GNO
L
L
Vee
GNA
H
H
L
3D
40
40
30
30
40
3D
40
H
H
30
X
L
Qo
'NC
40
NC
*0:
Outputs
H
00
'75 only
'75
o
LOGIC DIAGRAM
o
r-----------,
I
E
I
I
I
COMMON TO ONE
OTHER LATCH
I
I
L__________ JI
'77
o
o
r---- --------:
:
E
COMMON TO ONE
I
L___ ~~:R~~T~~ __ J
=8SAMSUNG
Electronics
474
KS54HCTLS
KS74HCTLS
75177
4-Bit Bistable Latches
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, irK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-O.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins . . . . . . . . . . .
± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . .
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta=25°C
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20J.tA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20J.tA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
J.tA
Maximum Quiescent
Supply Current
Icc
VIN=Vee or GND
10uT=0J.tA
8.0
80.0
160.0
J.tA
Additional Worst
Case Supply
Current
per input in
VI=2.4V
.6lee other Inputs:
at Vee or GND
10uT=0J.tA
2.7
2.9
3.0
mA
cRSAMSUNG
• ., Electronics
Vee Vee -0.1
4.2
3.98
0
475
I
KS54HCTLS
KS74HCTLS
75177
4-Bit Bistable Latches
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr • t~6 ns). HCTLS75
T a=2S0C
Vee S.OV
=
KS74HCTLS
Ta= -40°C to +8S oC
Vee=S.OV±10%
Typ
Propagation Delay.
E to Q or Q
~
CL=50pF
Propagation Delay.
D to Q or Q
~
CL=:=50pF
tpHL
KS54HCTLS
Ta= -55°C to +12S oC
UnH
Vee=S.OV± 10%
Guaranteed Limits
19
25
31
38
19
25
31
38
13
21
26
32
tPHL
13
21
26
32
tsu
12
15
18
22
th
0
0
0
0
Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
Data Set up Time D to E
Data Hold Time E to D
~
Propagation Delay.
D to Q or Q
~
Conditions t
CL=50pF
tpHL
(In'put tr • tf~6 ns), HCTLS77
Ta=25°C
Vcc =5.0V
KS74HCTLS
Ta= -40°C ~o +85°C
Vee = S.OV ± 10%
KS54HCTLS
Ta= -55°C to +12SoC
Vcc=S.OV± 10%
13
18
23
27
13
18
23
27
13
18
23
27
13
18
25
27
tsu
12
15
18
22
th
0
0
0
0
Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
Data Set up Time D to E
CL =50pF
Unit
Guaranteed Limits
tpHL
Data Hold Time E to D
ns
fin,
Typ
Propagation Delay.
E to Q
ns
pF
AC ELECTRICAL CHARACTERISTICS
Symbol
~~
pF
* CPD determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2,
Characteristic
ns
ns
... <>
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc 2 fin,
t For AC switching test circuits and timing waveforms see section 2,
..
=SAMSUNG
Electronics
.•
.
476
KS54HCTLS
KS74HCTLS
76A
Dual J-K Flip-Flops with Preset and Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174lS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These parts consist of two negative-edge-triggered J-K flipflops with independent J, K, preset, clear and clock inputs
and complementary outputs. The J-K inputs at each flipflop are enabled when the clock goes high. The input data
are transferred to the outputs on the negative-going edge
of the clock pulse, provided the setup requirements have
been met.
PIN CONFIGURATION
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
Outputs
Inputs
lCLK
lK
PRE
10
lCLR
1Q
1
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components .
lJ
GND
Vee
2K
2CLK
20
2PRE
20
2CLR
2J
PRE
ClR
ClK
J
K
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
L
H
L
H
X
X
X
X
L
L
H
H
X
H
L
H"
L
H
H·
00
0'0
+
+
+
+
H
I
L
H
H
L
TOGGLE
00
0'0
* Both outputs will remain high as long as preset and
clear are low, but the output states are unpredictable
if preset and clear go high simultaneously.
LOGIC DIAGRAM
K
c
c
c~
PRE----------~~------~
c8SAMSUNG
Electronics
c
477
KS54HCTLS '7~ A
KS74HCTLS L IV,..
Dual J-K Flip-Flops with Preset and Clear
Absolute Maximum Ratings*
Supply Voltage Range Vcc,
-O.SV to + 7V
DC Input Diode Current, ilK
(VI < -O.SV or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +O.SV)
±20 mA
Continuous Output Current Per Pin, 10
(-O.SV < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, T8 tg . . . -65°C to +150°C
Power Dissipation Per Package, Pdt ..... SOO mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.SV to S.5V
DC Input & Output Voltages * , V~N, Vour .. OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V±10% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
Minimum High-Level
Input Voltage
VIH
Maximum Low-Level
Input Voltage
VIL
KS74HCTLS
KS54HCTLS
Ta =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Vcc -0.1
3.84
Vcc -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
J.lA
4.0
40.0
80.0
--
VOH
VIN = VIH or VIL
10=-20J.lA
10=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20J.lA
10=4mA
10=8mA
Maximum Input
Current
liN
VIN=VCC or GND
Minimum High-Level
Output Voltage
Maximum QuieSCent
Supply Current
Additional Worst
Case Supply
Current
VIN=VCC or GND
Icc
10ur=OJ.lA
-per .input pin
VI=2.4V
.L:.lcc other Inputs:
at Vce or GND
10uT=OJ.lA
c8SAMSUNG
Electronics
Vcc Vcc -0.1
4.2
3.98
0
J.lA
L_
2.7
2.9
3.0
mA
478
KS54HCTLS 7~A
KS74HCTLS U.
Dual J-K Flip-Flops with Preset and Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r , tf~6 ns), HCTlS76A
KS74HCTLS
KS54HCTLS
Ta=25°C T.=-40°Cto +85°C T.=-55°Cto +125°C
Unit
Vcc=5.0V
Vcc=5.0V±10%
Vcc=5.0V± 10%
Symbol Conditions t
Typ
Guaranteed Limits
Maximum Clock Frequency
f max
40
30
25
21
Maximum Propagation Delay,
ClK to Q or Q
tpLH
r----~-
15
20
25
30
15
20
25
30
Maximum Propagation Delay,
PRE or ClR to Q or Q
f----
Minimum Setup I Data
Time before ClK~ I PRE or ClR Inactive
Minimum Hold Time,
J or K after ClK~
"tPHL
CL =50pF
tpLH
15
20
25
30
tpHL
15
20
25
30
tsu
--
13
17
20
10
th
-~
10
13
17
0
0
0
0
10
13
17
20
10
13
17
20
-~I--~
MHz
ns
ns
ns
20
ns
I ClK High or low
Minimum Pulse
Width
IPRE or ClR low
r--Maximum Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
(per flip-flop) 40
pF
tw
-
ns
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vce 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
I
=SAMSUNG
• • Electronics
479
Dual J-I( Flip~FIQPsw;th Pre~et,
Common Clear & Common Clock
KS54HCTLS .,~~ A
KS74HCTLS
8#'1
DESCRIPTION
'FEATURES
• Function, pin-out, speed and drive compatibility with
54/74lS logic family
• low power consumption characteristic of CMOS
• Hlgl)-Drive-Current outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
'
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These parts consist of two negative-edge-triggered J-K flipflops with independent J, K and preset inputs and complementary outputs, The clear and clock inputs are common to both flip-flops, The J-K inputs are enabled when
the clock goes high, The input data are transferred to the
outputs on the negative-going edge of the clock pulse, provided the setup requirements have been met.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels, The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components,
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
PIN CONFIGURATION
Outputs
Inputs
ClK
1K
1PRE
10
PRE
ClR
ClK
J
K
Q
Q
1J
10:
Vee
GND
L
H
L
H
L
L
X
X
X
X
X
X
X
X
X
H
L
H'
L
H
H'
00
ern
2J
2'PRE
20
2K
2Q
H
H
~
l
l
00
H
H
H
H
H
H
H
H
~
H
L
H
X
L
H
H
X
H
L
L
H
TOGGLE
~
t
H
00
00
* Both outputs will remain high as long as preset and
clear are low, but the output states are unpredictable
if preset and clear go high simultaneously,
LOGIC DIAGRAM
K
c~
=8SAMSUNG
Electronics
PRE----------~--------~
c
480
KS54HCTLS
KS74HCTLS
78A
Dual J-K Flip-Flops with Preset,
Common Clear & Common Clock
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) .
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per. Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input" & Output Voltages·, VIN,. VOUT
OV to Vcc
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & .Fall Times, t r , tf
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
Ta=25°C
Typl
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vce -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
J.lA
4.0
40.0
80.0
J.lA
2.7
2.9
3.0
mA
Maximum Low-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20J.lA
10=-4mA
VOL
VIN=VIH or VIL
10=20J.lA
10=4mA
10=8mA
Maximum Input
Current
hN
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
1
Guaranteed Limits
Minimum High-Level
Input Voltage
Minimum High-Level
Output Voltage
,I'
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
.6.lee
VIN=Vee or GND
VIN=Vce or GND
10uT=OJ.lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=OJ.lA
c8SAMSUNG
efectronics
I
I
I
vcelvee -0.1
4.21 3.98
I
01
I
I
481
KS54HCTLS
KS74HCTLS
7B--I.A
Dual J-K Fiip-Flops with Preset,
Common Clear & Common Clock
~
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr ,
Symbol Conditions t
tf~6
ns), HCTlS78A
KS74HCTLS
KS54HCTLS
T.=25°C
T.= -40°C to +85°C Ta= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Guaranteed Limits
Maximum Clock Frequency
f max
40
30
25
21
Maximum Propagation Delay,
ClK to Q or Q
tpLH
15
20
25
30
15
20
25
30
Maximum Propagation Delay,
PRE or ClR to Q or Q-
I
J or K
Minimum Setup
Time before ClK-!- PRE or ClR Inactive
I
Minimum Hold Time,
J or K after ClK-!Minimum Pulse
Width
IClK High or low
IPRE or ClR low
MHz
ns
~
tpHL
tpLH
CL=50pF
15
20
25
30
15
20
25
30
10
13
17
20
10
13
17
20
ns
~
tpHL
tsu
----
th
a
tw
---
b
0
0
10
13
17
20
10
13
17
20
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo (per fllp·flop) 40
ns
-~
-~
ns
ns
pF
5
~--
* CPO determines the no-load dynamic power dissipation: Po=Cpo Vee 2 f
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
pF
+
lee Vee. fin.
482
86
KS54HCTLS
KS74HCTLS
Quad 2-lnput Exclusive-OR Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent 2-input ExclusiveOR gates. They perform the Boolean functions Y=A~B or
Y=AB+AB.
PIN CONFIGURATION
LOGIC DIAGRAM
1A
Vee
18
48
1Y
4A
2A
4Y
28
38
2Y
3A
GND
3Y
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clam·ps to Vce and
ground .
18 (2)
1A~
1Y
2A~
28 (5)
2Y
3A~
(10)
3Y
4A~
4Y
38
48 (13)
I
FUNCTION TABLE
(Each Gate)
Inputs
Output
y
A
B
L
L
L
L
H
L
H
H
H
L
H
H
c8SAMSUNG
Electronics
483
86
KS54HCTLS
KS74HCTLS . .
Quad 2-lnput Exclusive-OR Gates
Absolute Maximum Ratings·
Supply Voltage Range Vee. ,., .... -0.5V to + 7V
DC Input Diode. Current. hK
(VI < -0.5V or VI > Vee +0.5V) . .
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic. Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
........
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf ..
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTlCS
Characteristic
Symbol Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
Typ
Minimum High-Level
Input Voltage
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OI-lA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20j.lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
I-lA
Maximum Quiescent
Supply Current
lee
VIN=Vee or GND
louT=Oj.lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10UT=01-lA
2.0
20.0
40.0
I-lA
2.7
2.9
3.0
mA
c-
Additional Worst
Case Supply
Current
.6.lee
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
484
KS54HCTLS
KS74HCTLS
86
Quad 2-1nput Exclusive-OR Gates
AC ELECTRICAL CHARACTERISTICS
Symbol
Characteristic
Conditions t
(Input t r • tf~6 ns). HCTLS86
Ta=25°C
Vcc =5.0V
KS74 HCTLS
Ta= -40°C to +85°C
Vcc=5.0V:!:10%
Typ
Maximum Propagation Delay.
A or B to Y (Other Input Low)
Maximum Propagation Delay.
A or B to Y (Other Input High)
-
-
Maximum Input Capacitance
Power Dissipation Capacitance *
KS54 HCTLS
Ta
=-55°C to
+125°C
Vcc=5.0V:!: 10%
Guaranteed Limits
tPLH
15
20
25
30
tpHL
15
20
25
30
tpLH
18
25
31
37
tpHL
18
25
31
37
C'N
CpD
CL=50pF
15
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
ns
ns
pF
5
(per gate)
Unit
pF
fin.
I
c8SAMSUNG
Electronics
485
KS54HCTLS
KS74HCTLS
90/92/93
Decade, Divide by 12, and
Binary Counters
FEATURES
DESCRIPTION
• Various counting mode.
• Function, Pin-out, speed and drive compatibility with
54/74 ALS logic family.
• Low power consumption characteristic of CMOS
• High-Drlve-Current outputs:
IOL=8mA @ VOL=0.5V
• Input and output interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage rllnge: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include plastic "small outline"
packages, standard plastic and ceramic 300-mil DIPs
These devices contain four master-slave ftip~flops and'addition .gating to provide a divide by a counter and a threestage binary counter for which the count cycle length is
divide by five for the HCTLS90, divide by six for the
HCTLS92, and divide by eight for the HCTLS93, All of
these counters have a gated zero reset and the HCTLS90
also has gated set-to-nine inputs for use in BCD nine's complement applications.
To use their maximum count length (decade, divide-bytwelve, or four bit binary), the CKB input is connected to
the aA output. The input count pulses are applied to CKA
and the outputs are as described in the appropriate truth
table. A symmetrical divide-by-the count can be obtained
from the HCTLS90 counters by connecting the aD ou!put to the CKA input and applying the input count to the
CKB input which gives a divide-by-ten square wave at outPUt.OA.
PIN CONFIGURATION
'90
'92
'93
CKB
CKA
CKB
CKA
CKB
MR1
NC
NC
NC
MR1
NC
MR2
NC
a.
as
MR2
NC
a.
aD
a.
aD
Vee
GND
MS1
MS2
as
ae
c8SAMSUNG
Electronics
NC
Vee
MR1
MR2
NC
CKA
GND
Vee
GND
ae
aD
NC
as
ae
NC
486
90192193
KS54HCTLS
KS74HCTLS
Decade, Divide by 12, and
Binary Counters
FUNCTION TABLE
'90
'90
'92
BCD COUNT SEQUENCE
(See Note A)
BI-QUINARY (5-2)
(See Note B)
COUNT SEQUENCE
(See Note C)
Output
Count
0
1
2
3
4
5
6
7
8
9
Qc
Qs
QA
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
Output
Count
-~
Qo
0
1
2
3
4
5
6
7
aD
ac
as
L
L
L
L
L
H
H
H
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
H
8
9
H
Output
Count
QA
0
1
2
3
4
5
6
7
8
9
10
11
Qo
Qc
Qs
QA
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
I
'93
'90
COUNT SEQUENCE
(See Note C)
RESET/COUNT TRUTH TABLE
Output
Count
0
1
2
3
4
5
6
7
8
9
10
11 '
12
13
14
15
Reset Inputs
Output
aD
Qc
as
aA
MR1
MR2
MS1
MS2
aD
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
X
L
X
X
L
L
X
H
X
L
X
L
X
L
H
L
X
L
L
H
H
X
X
L
L
X
L.
X
ci$SAMSUNG
Electronics
;
aA
L
L
H
RESET/COUNT TRUTH TABLE
Reset Inputs
aD
as
L
L
L
L
L
L
COUNT
COUNT
COUNT
COUNT
'92, '93
H
Note A: Output QA is connected to input CKB for BCD count.
Note B: Output
is connected to input CKA for bi-quinary
count.
Note C: Output QA is connected to input CKB.
Note D: H=High Level, L=Low Level, X=Don't Care.
ac
Output
MR1
MR2
aD
H
L
X
H
X
L
L
Qc
as
L
L
COUNT
COUNT
QA
L
487
KS54HCTLS
KS74HCTLS
90.,~. 2193
9.
Decade, Divide by 12., and
Binary Counters
LOGIC DIAGRAMS
'90
'92
(6)
MS1~=j:J~______1
MS2 (7)
(14)
CKA -----+---~_
(11)
(9)
CKB (1)
as
as
(9)Oc
(S)Oc
(8)
(11)
aD
aD
'93
(12)
--OA
(9)
Note: The J.K inp'uts shown without connection are for
reference only and are functionally at a high state.
(8)
Oc
(11)
c8SAMSUNG
Electronics
as
aD
488
KS54HCTLS
KS74HCTLS
90/92/93
Decade, Divide by 12, and
Binary Counters
Absolute Maximum Ratings *
t Power DiSSipation temperature derating:
Supply Voltage Range Vcc, ....... -0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
± 125 mA
Vcc or GND pins . .
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Ceramic Package (J): -12mW/oC from 100°C to 125°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages·. VIN. VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times. tr • tf . . . .
Max 500 ns
• Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vce=5V± 1 0% Unless Otherwise Specified)
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Ta=25°C
Symbol Test Conditions
--
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20JlA
10=-4mA
Vee -0.1
3.84
Vec -0.1
3.7
V
VOL
VIN=VIH or VIL
10=20JlA
10=4mA
10=8mA
0.1
0.33
0.5
0.1
0.4
2.0
---~------
Maximum Low-Level
Output Voltage
Maximum Input
Current
Vee Vee -0.1
4.2
3.98'
0
0.1
0.26
0.39
/
...
V
.- --
V
-- ,...--
hN
VIN=VCC or GND
±0.1
±1.0
:1;;1.0
JlA
Maximum Quiescent
Supply Current
Icc
VIN=Vee or GND
10UT=OJlA
8.0
80.0
160.0
JlA
Additional Worst
Case Supply
Current
per input in
VI=2.4V
ll.lce other Inputs:
at Vce or GNb
10UT=OJlA
2.7
2.9
3.0
mA
c8SAMSUNG
Electronics
489
I
90
KS54HCTLS,
KS74HCTLS '
Decade Counter
AC ELECTRICAL CHARACTERISTICS
Symbol
Characteristic
Condltlons t
(Input tr• t,"6 ns), HCTLS90
TA=25°C
Vcc=5.0V
KS74HCTLS
KS54HCTLS
TA= -40°C to +85°C TA= -55°C to +125°C
Unit
Vcc=5.0V:t10%
Vcc=5.0V:t 10%
Typ
Maximum Clock
Frequency
CKA to OA
fmax
CKB to Os
Maximum Propagation
Delay, CKA to OA
tpLH
r--tpHL
Maximum Propagation
Delay CKA to 00
~
Maximum Propagation
Delay CKB to Os
~
Maximum Propagation
Delay, CKB to Oc
~
tpHL
Maximum Propagation
Delay MS to OA, 00
tpLH
Maximum Propagatiorl
Delay MS to Os, Oe
Maximum Propagation
Delay MR ,to any 0
Guaranteed Limits
42
32
26
21
20
16
13
11
10
16
20
24
12
18
23
27
ns
32
48
60
72
34
48
60
72
1Q
16
20
24
14
21
26
32
21
32
40
48
.23
35
43
52
20
30
37
45
ns
tpHL
26
40
50
60
ns
tpHL
26
40
50
60
ns
tpHL
tpHL
CL=50pF
ns
ns
ns
,-
CKA
12
15
18
22
CKB
24
30
36
44
MS
12
15
18
22
MR
12
15
18
22
tree
20
25
31
37
Maximum Input Capacitance
CIN
5
Power Dissipation Capacitance
Cpo
Pulse Width
MHz
tw
Recovery Time
MR to CKA, CKB
* Cpo determines the no·load dynamic power dissipation: Po=Cpo Vee 1 f
t For AC switching 'test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
ns
ns
pF
pF
+
Icc Vee.
490
92
KS54HCTLS
KS74HCTLS
Divide-by-Twelve· Counter
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr , tf~6 ns), HCTLS92
TA=25°C
Vee=5.0V
KS74HCTLS
KS54HCTLS
TA= -40°C to +85°C TA= -55°C to +125°C
Unit
Vee = 5.0V ± 10%
Vee=5.0V± 10%
Guaranteed Limits
Typ
Maximum Clock
Frequency
CKA to QA
f max
~---
CKB to Qs
42
32
26
21
20
16
13
11
10
16
20
24
12
18
23
27
~
32
48
60
72
tpHL
34
48
60
72
Maximum Propagation
Delay, CKA to QA
tpLH
-tpHL
Maximum Propagation
Delay CKA to Qo
Maximum Propagation
Delay CKB to Qs
-
Maximum Propagation
Delay, CKB to Qc
~
~
tpHL
tpHL
CL=50pF
10
16
20
24
14
21
26
32
10
16
20
24
14
21
26
32
Maximum Propagation
Delay CKB to Qo
f---
tpLH
21
30
40
48
tpHL
23
35
43
52
Maximum Propagation
Delay: MR to Any Q
tpHL
26
40
50
60
CKA
12
15
18
22
CKB
24
30
36
44
MR
12
15
18
22
tree
20
25
31
37
Maximum Input Capacitance
CIN
5
Power Dissipation Capacitance
Cpo
Pulse Width
Recoyery Time
MR to CKA, CKB
.. Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc 2 f
MHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
+ Icc Vee.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
491
I
93
KS54HCTLS
KS74HCTLS
4-Bit Binary Counter Divide
by Two and Eight
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input tr, tf~6 ns), HCTLS93
TA=25,OC
Vee=5.0V
TA
KS74HCTLS
KS54HCTLS
+85°C TA= -55°C to +125°C
Unit
Vee = 5.0V::t 10%
Vee=5.0V::t 10%
= -40°C to
Typ
Maximum Clock
Frequency
CKA to OA
fmax
CKB to OB
Guaranteed Limits
42
32
26
21
20
16
13
11
Maximum Propagation
Delay, CKA to OA
~
10
16
20
24
tpHL
12
18
23
27
Maximum Propagation
Delay CKA to 00
~
46
70
87
105
46
70
87
105
Maximum Propagation
Delay CKB to OB
~
tpHL
tpHL
CL=50pF
10
16
20
24
14'
21
26
32
Maximum Propagation
Delay, CKB to Oc
t---
tpLH
21'
32
40
48
tpHL
23
35
44
53
Maximum Propagation
Delay CKB to 00
~H_
tpHL
34
50
60
70
34
50
60
70
Maximum Propagation
Delay: MR to Any 0
tpHL
26
40
50
60
12
15
18
22
tw
24
30
36
44
12
15
18
22
tree
20
25
31
37
Maximum Input Capacitance
CIN
5
Power Dissipation Capacitance
Cpo
CKA
Pulse Width
CKB
MR
Recovery Time
MR to CKA, CKB
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc 2 f
MHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
+
Icc Vee.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
" Electronics
492
KS54HCTLS
KS74HCTLS
107A
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174lS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current Outputs:
lOL=8mA @ VOL=O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTlS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain two independent J-K negative-edgetriggered flip-flops. A low level at the CLR input resets the
outputs regardless of the levels of the other inputs. When
CLR is inactive (high), data at the J and K inputs meeting
the setup time requirements are transferred to the outputs
on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related
to the rise time of the clock pulse. Following the hold time
interval, data at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile flip-flops
can perform as toggle flip-flops by tying J and K high.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts· and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
PIN CONFIGURATION
1J
Vee
10
1CIJi
1CLK
2K
2CLR
2CLK
10
1K
20
2Q
GND
2J
Inputs
I
Outputs
ClR
ClK
J
K
a
a
L
H
H
H
H
H
x
x
X
L
H
.J.
L
H
L
H
X
L
L
H
H
X
00
00
.J.
.J.
.J.
H
L
H
H
L
TOGGLE
00
0
0
LOGIC DIAGRAM
o
Q.
CLR-----------------q
II
c8SAMSUNG
Electronics
493
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
KS54HCTLS·101A
KS74HCTLS
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V) . .
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins . . . .
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Volta.ge, Vcc . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf ..
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to ·the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta =-55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/-tA
10=-4mA
Vcc -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10 = 20/-tA
10';"4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
·±1.0
/-t A
Maximum Quiescent
Supply Current
lee
4.0
40.0
80.0
/-t A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
lllee
VIN=Vee or GND
10uT=0/-tA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0/-tA
c8SAMSUNG
Electronics
Vee Vec -0.1
4.2
3.98
0
494
KS54HCTLS
KS74HCTLS
107A
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r • tf~6 ns). HCTlS1 07 A
KS74HCTLS
KS54HCTLS
T.=25°C
T.= -40°C to +85°C T.= -55°C to +125°C Unit
Vcc=5.0V
Vcc=5.0V:!:10%
Vcc=5.0V:!: 10%
r-~--~--------------~----------~
Typ
Guaranteed Limits
Maximum Clock Frequency
f max
40
30
25
21
Maximum Propagation Delay.
. ClK to Q or Q
tpLH
r----tpHL
15
20
25
30
15
20
25
30
Maximum Propagation Delay.
ClR to Q or Q
tpLH
r----tpHL
15
20
25
30
15
20
25
30
CL=50pF
-
-
MHz
ns
-+---ns
~----------~-----------+----1---------r-~---+--------------r--------------+--~
I
Minimum Setup
J or K
Time before ClK~ IClR Inacti~~
tsu
Minimum Hold Time.
th
J or K after ClK.).
-------,-------------T--------r----IMinimum Pulse ClK High or low tw
Wi~
I
IClRlow
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
10
13
17
20
10
13
17
20
0
0
0
0
17
20
17
20
f------
(per flip-flop)
10 13
- ---10 13
~---
ns
ns
ns
5
pF
40
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
I
=8SAMSUNG
Electronics
495
KS54HCTLS 10r'~
KS74HCTLS
;:,.
Dual J-K Positive:,Edge-Triggered
Flip-Flops with'Pr~set and Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current Outputs:
IOL=8mA @ VOL=O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation, over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
These devices contain two positive-edge-triggered J-K flipflops with independent preset and clear inputs and complementary Q and Q outputs. The present and clear inputs
are active-low and operate independently of the clock Data
at the J and K inputs are transferred to the ouptuts on the
positive transition of the clock provided setup requirements
have been met. These versatile flip-flops can perform as
toggel flip-flops by grounding K and tying J high. They
can also perform as D-type flops if J and K are tied together.
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
FUNCTION TABLE
PIN CONFIGURATION
1m
1J
1R
" Inputs
Outputs
Vee
2CLR
2J
21<
2CLK
10
2~
1~
20
GND
2~
PRE
CLR
ClK
J
K
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
L
H
X
X
X
L
L
H
H
X
H
L
L
H
H*
H*
L
H
TOGGLE
t
t
t
t
L
L
H
X
Q
Qo
0
H
L
0
0
Qo
0
• Both outputs will remain high as long as PRE and CLR are low,
but the output states are unpredictable if PRE and CLR go high
simultaneously.
LOGIC DIAGRAM
PRE--------------------------------~~--------~
Q
eLR------------------------~------------------------------~
•••
qsSAMSUNG
Electronics
496
,I
KS54HCTLS
KS74HCTLS
109A
Dual J-K Positive Edge-Triggered
Flip-Flops with P,asat and Clear
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85 °C
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 rnA
Continuous Current Through
Vee or GND pins
± 125 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Pow~r Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vce
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the deviee may oecur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +~~ Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20JlA
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20JlA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
JlA
Maximum Quiescent
Supply Current
lee
4.0
40.0
80.0
JlA
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
t:..lee
VIN=Vee or GND
10uT=OJlA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=OJlA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
497
I
Dual J-K Positive Edge- Triggered
Flip-Flops with Preset and Clear
AC ELECTRICAL CHARACTERISTICS
(Input t r ,
ns), HCTlS109A
KS74HCTLS
KS54HCTLS
Ta=25°C Ta= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V±10%
Vcc=5.0V± 10%
Symbol Conditions t
Characteristic
tf~6
Typ
Maximum Clock Frequency
---
fmax
tpLH
1----'---
Maximum Propagation Delay,
. PRE or ClR to Q or Q
1---
Minimum Setup
-
-~
Maximum Propagation Delay,
ClK to Q or Q
tpHL
25
20
18 25
31
37
18 25
31
37
~-
--
tsu
-
MHz
--~
18 25
31
37
18 25
31
37
10 13
-10 13
17
20
-.
tpHL
Ti~e_~~fore_£lKtJ.~or ClR Inactive
30
----
CL =50pF
tpLH
IData
Guaranteed Limits
40
17
-- ns
--I----'--
20
-----------~
Minimum Hold Time,
Data after ClK~
Minimum Pulse
Width
-----------
~lK. High or
a
a
8 ·15
8 15
tw
--
Maximum Input Capacitance
20
20
Cpo
--
25
25
(per flip·flop)
40
ns
1-----
ns
---
f--
ns
---.---- 1 -
5
'CIN
~-
Power Dissipation Capacitance *
•
a
-~~--
low
PRE or ClR low
.
a
th
ns
--~------------~-
rE~
pF
* Cpo determines the no·load dynamic power dissipation; Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
cS2SAMSUNG
• • Electronics
498
KS54HCTLS
KS74HCTLS
11"
II
~,..
Dual J-K Negative-Edge-Triggered
Flip-Flops with Preset 'and Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current Outputs:
IOL=8mA @ VOL=O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These parts consist of two negative-edge-triggered J-K flipflops with independent J, K, preset, clear and clock inputs
and complementary outputs. The J-K inputs at each flipflop are enabled when the clock goes high. The input data
are transferred to the outpLits on the negative-going edge
of the clock pulse, provided the setup requirements have
been met.
PIN CONFIGURATION
1CLK
1K
1J
1,PRE
10
fCi
20
GND
These devices provide speeds and drive capability
equivalent to their lSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components,
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
FUNCTION TABLE
Vee
1CLR
2CLR
2CLK
2K
2J
2PRE
20
Inputs
1----:::-,
Outputs
PRE
CLR
CLK
J
K
Q
Q
L
H
L
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
L
L
H
L
H*
L
H
H*
00
0
H
H
~
H
H
H
X
X
X
L
H
L
H
X
~
~
+
H
H
X
0
H
L
L
H
TOGGLE
-
00
00
"Both outputs will remain high as long as PRE and CLR are low,
but the output states are unpredictable if PRE and CLR go high
simultaneously.
LOGIC DIAGRAM
Q
K
eLR--------------------------~--------------------------------~
=8SAMSUNG
Electronics
.
499
I
KS54HCTLS 112~ JI
KS74HCTLS'.·
M
Dual J-K Negative-Edge-Triggered
Flip-Flops with Preset and Clear
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
,Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, ilK
(VI < -0~5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vct +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vec or GND pins . .
± 1 25 mA
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
.. Supply Voltage, Vec
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
. Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect de~ice reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
KS54HCTLS
KS74HCTLS
Ta =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8·
V
Minimum High-Level
Output Voltage
VOH
Vee -0.1
3.84
Vee -0.1
3.7
V
VIN=VIH or VIL
lo=-20~A
Vee Vee -0.1
4.2
3.98
lo=-4mA
VIN=VIH or YIL
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current.
liN
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
!lice
10=20~A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=Vee or GND
±0.1
±1.0
±1.0
~A
4.0
40.0
80.0
~A
2.7
2.9
3.0
mA
0
VIN=Vee or GND
IOUT=O~A
per input pin
V,=2.4V
other Inputs:
at Vee or GND
.
louT=O~A
c8SAMSUNG
Electronics
500
112A
KS54HCTLS
KS74HCTLS
Dual J-K Negative-Edge-Triggered
Flip-Flops with Preset and Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Input t r , tf~6 ns). HCTlS112A
KS74HCTLS
KS54HCTLS
Ta=25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Conditions t .Vcc=5.0V
Unit
Vcc=5.0V ± 10%
Vcc=5.0V± 10%
Typ
Maximum Propagation Delay,
ClK to Q or Q
Maximum Propagation Delay,
ClR to Q or Q
IJ
I
40
30
25
21
~
15
20
25
30
15
20
25
30
tpHL
-
15
20
25
30
tpHL
15
20
25
30
tsu
Minimum Hold Time,
Data after ClK ~
th
lClK High or low
IPRE
CL=50pF
tpLH
orK
Minimum Setup
Time before ClK~ ClR Inactive
Minimum Pulse
Width
Guaranteed Limits
fmax
Maximum Clock Frequency
tw
or ClR low
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per flip-flop)
10
13
17
20
10
13
17
20
a
0
0
0
10
13
17
20
10
13
17
20
MHz
ns
ns
ns
ns
ns
5
pF
40
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
I
cRSAMSUNG
• • Electronics
501
KS54HCTLS
KS74HCTLS
123
Dual Retriggerable Monostable
Multivibrator with Clear
FEATURES
DESCRIPTION
• Simple pulse width formula tw = 0.45RC
• DC triggered from active HIGH or active Low inputs
• Retriggerable for very long output pulses up to 100 %
duty cycle
• Overriding clear terminates output pulse
• Schmitt trigger A & B inputs allow infinite rise and
fall times on these inputs
• Functions, pin-out, speed and drive compativility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High drive current outputs:
IOL=8mA @ VOL=0.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range; 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '123 contains dual retriggerable monostable
multivibrators with output pulse width control by three
methods.
The basic pulse time is programmed by selection of an external resistor (Rext) and capaCitor (Cext). The external
resistor and capaCitor are normally connected as shown
timing component.
Once triggered, the basic output pulse width may be extended by retriggering the gated active Low going edge
input (Ai) or the active HIGH going edge input (Bi). By
repeating this process, the output pulse period (nQ=HIGH,
nQ=LOW) can be made as long as desired. Alternatively
an output delay can be terminated at any time by a Lowgoing edge on input CLR, which also inhibits the triggering.
An internal connection from CLR to the input gates makes
it possible to trigger the circuit by a positive-going Signal
at input CLR as shown in the function table when
CEXT>1 OnF, the typical output pulse width is defined as;
tw=O.45XREXTXCEXT(typ).
Where tw is in seconds. R is in ohm. and C is in fards.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
FUNCTION TABLE
--------T-------A Inputs
711
Vee
B1
REXTl/CEXT
CLR1
RE.XT2
C Exr l
0"1
01
Q2
02
CEXT2
L
X
X
H
H
CLR2
iC EXT
B2
GND
A2
t
a
a
X
X
L
L
L
L
H
H
H
L
t
.1l..
~
H
H
JL
JL
I
x
I
H
I
x
I
Outputs
B
CLR
L
U
U
U
HIGH voltage level
LOW voltage level
don't care
LOW to HIGH transition
~= HIGH to LOW transition
Jl...= one HIGH level output pulse
lS= one LOW level output pulse
H=
L=
X=
t=
c8SAMSUNG
Electronics
502
KS54HCTLS
KS74HCTLS
123
Dual Retriggerable Monostable
Multivibrator with Clear
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package(N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ............... -0.5V to + 7V
DC Input Diode Current, hK
(VI<-0.5V or VI>Vee+0.5V) ................. ±20 mA
DC Output Diode Current, 10k
(Vo<-0.5V or Vo>Vee+0.5V) ........
·l ±20 mA
Continuous OUtput Current Per Pin, 10
(-0.5V
B>
B>
B>
(3)
(6)
(8)
(11)
lY
2Y
3Y
4Y
505
KS54HCJ'~~'·:·'1 ~·6·1126
(Juad3-State Buffers
KS'7 4HCTLS""'~' .
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(V, < -0.5V or V, > Vec +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vec +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-O.5V < Vo < Vee +0.5V) . . .
±70 mA
Continuous Current Through
Vee or GND pins. .
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Plastic Package (N): -12mW/oC from 65°C to 85.oC
R.ecommended Operating Conditions
Supply Voltage, Vec
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. ,?V to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and .functional operation
of the device at or beyc,nd them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Minimum High-Level
Input Voltage
(Vec=5V± 1 0% Unless Otherwise Specified)
2.0
2.0
2.0
V
--~~--t~-·--t____-------~~~-+--"-r--~--·---r-----------·r---
Maximum Low-Level
!nput Voltage
Minimum High-Level
Output Voltage
0.8
VOH
VIN = VIH or VIL
10=-20J.lA
10=-6mA
Vcc Vec -0.1
4.2
3.98
Vce -0.1
3.84
f--~~~~~----+---~--+----~~~~~-+--+--~~-t----.----.--Maximum Low-Level
Output Voltage
VOL
VIN=VIH or V'L
10=20J.lA
10=12mA
10=24mA
~----1f------f---.----'=------------
Maximum Input
Current
0.8
0.8'
~~---+~-+-~----"+-------------'--r-'''-
0
f--
- 0.1
0.26
0.39
----~-r-----.--
±0.1
hN
...
-- f---------
0.1
0.33
Q
5
- --.. --
V
--
Vcc -0.1
3.7
-_.
_.
---
V
----c---
0.1
0.4
V
±1.0
J.lA
----f----
±1.0
5
f- ~-~-~- -+- - -+~- -"~- ";-~-=-'~-;- "- -~.~ ~;:' --:0-0- ~•-.-----:::-- ·E~~::~ ~-~~
Maximum 3-State
Leakage Current
loz
Maximum Quiescent
Supply Current
Icc
f-----'-~-~----+-~-----+-p-e·---r~-i-n-p....:.u-,--t-p-C-in-----t----Additional Worst
Case Supply
Current
-- -------..-------------
--- --- -- -t-II
ll.lcc
VI=2.4V
other Inputs:
at Vce or GND
10uT=01-lA
c8SAMSUNG
Electronics
I
2.7
2.9
[
30
i
mA
506
KS54HCTLS
KS74HCTLS
1251126
I
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
Quad3-State Buffers
(Input tr , tf~6 ns), HCTLS125, HCTLS126
KS74HCTLS
KS54HCTLS
T =2SoC
•
T.= -40°C to +85°C T.= -55°C to +125"C
Unit
Vcc=5.0V
Vcc=5.0V:t10%
Vcc=5.0V:t 10%
Typ
Maximum Propagation Delay,
A to Y
Maximum Output Enable
Time, Enable to Y
13 18
16 21
22
27
27
33
CL=50pF
CL=150pF
13 18
16 21
22
27
27
33
29
34
34
40
29
34
34
40
26
32
26
32
tpHL
tPZH
I----- RL=1kO
tPZL
Maximum Output Disable
Time, Enable to Y
Maximum Input Capacitance
Guaranteed Limits
CL=50pF
tPLH
CL=150pF
CL=50pF 17 23
CL=150pF 20 26
"-
CL=50pF 17 23
CL=150pF 20 26
~ RL=1 kO
tpLZ CL=50pF
-
CIN
Maximum Output Capacitance
COUT Output [li!3abled
Power Dissipation Capacitance * Cpo * Ol.ltput Disabled
(per stage)
Output Enabled
16
'----
16
1
ns
ns
ns
5
pF
10
pF
5
30
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching. test circuits and timing waveforms see section 2.
I
=8SAMSUNG
Electronics
507
KS54HCTLS
KS74HCTLS
132
Quad Schmitt-Trigger NAND
Gates
FEATURES
DESCRIPTION
- Function, pin-out, speed and drive compatibility with
54174LS logic family
- Low power consumption characteristic of CMOS
- High-Driv&-Current outputs:
These Schmitt-trigger devices contain four independent
NAND gates. They perform the Boolean function Y=A-B=
A+B in positive logic.
IOL =8 rnA @ VOL =O.5V
- Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
- Wide operating voltage range: 4.5V to 5.5V
- Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55 ° C to + 125 ° C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The input threshold levels are temperature compensated
and can be triggered from tre slowest of input ranges and
still give jitter-free output signals.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
1A~)
1A
Vee
1B
4B
1Y
4A
2A
4Y
2B
3B
2Y
3A
GND
3Y
1B~-1Y
2A~'
2B~2Y
3A~(8:
3B~3Y
4A~)
4B~·····4Y
FUNCTION TABLE
INPUTS
A
B
OUTPUTS
Y
L
L
H
H
L
H
L
H
H
H
H
L
c8SAMSUNG
Electronics
508
132
KS54HCTLS
KS74HCTLS
Quad Schmitt-Trigger NAND Gates
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI> Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . .
± 125 mA
Storage Temperature Range, TSlg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/o C from 65 ° C to 85° C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: - 55 ° C to + 125 ° C
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Ta=25°C
Symbol Test Conditions
Minimum High-Level
Output Voltage,
Maximum Low-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-2o,..A
10=-4mA
VOL
VIN=VIH or VIL
10=20j.lA
10=4mA
10=8mA
(Vee=5V±10% Unless Otherwise Specified)
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Vee Vee -0.1
4.2
3.98
Vee -0.1
3.84
Vee -0.11
3.7
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
0
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
j.lA
Maximum Quiescent
Supply Current
Icc
VIN=Vee or GND
10UT=0j.lA
2.0
20.0
40.0
j.lA
per input pin
VI=2.4V
other inputs:
at Vee or GND
10uT=0j.lA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Iee
DC ELECTRICAL CHARACTERISTICS
KS74HCTLS
Characteristic
Positive-Going
Symbol
VT+
Threshold Voltage
Negative-Going
VT-
Threshold Voltage
Hysteresis
VH
(VT+-VT-)
c8SA~SUNG
Electronics
Test Conditions
KS54HCTLS
Unit
Ta=25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Min Max
Min
Max
Min
Vee=4.5V
1.2 1.9
1.2
1.9
1.2
Max
1.9
Vee=5.5V
1.4 2.1
1.4
2.1
1.4
2.1
Vee=4.5V
0.5 1.2
0.5
1.2
0.5
1.2
Vee=5.5V
0.6 1.4
0.6
1.4
0.6
1.4
Vee=4.5V
0.4 1.4
0.4
1.4
0.4
1.4
Vee=5.5V
0.4 1.5
0.4
1.5
0.4
1.5
V
V
V
509
I
Quad Schmitt-Trigger NAND Gates
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r , tf.s;;6 ns), HCTLS132
T.=25°C.
Vcc=5.0V
KS74 HCTLS
T.= -40°C to +85°C
Vcc=5.0V%10%
Typ
Maximum Propagation Delay
Any Input to Y
tpLH
t------
CL=50pF
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
• Electronics
Unit
Guaranteed Limits
17
22
28
33
17
22
28
33
os
pF
5
(per gate)
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
KS54 HCTLS
Ta= -55°C to +125°C
Vcc=5.0V% 10%
pF
fin.
510
KS54HCTLS
KS74HCTLS
133
13-lnput NAND Gates
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
The' 133 contains a single 13-input NAND gate,
It performs the Boolean functions (in positive logic):
Y = A-B-C-D-E-F-G'H'I'J'K'L'M
Y = A+B+C+5+E+i=+G+R+T+J+R+L+M
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs_
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode oIamps to Vce and
ground .
LOGIC DIAGRAM
A
Vee
B
M
A
B
C
0
K
E
C
0
E
G
H
GND
y
F
G
H
(1)
(2)
I
(3)
(4)
(5)
(6)
y
(7)
(10)
(11)
," ,
(12)
K
FUNCTION TABLE
M
INPUTS A THRU M
All inputs
H
One or more inputs L
cRSAMSUNG
•• Electronics
(13)
(14)
(15)
OUTPUT
y
L
H
511
133
.
KS54HCTLS
KS74HCTLS
13-lnput NAND Qates
Absolute Maximum Ratings*
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vce or GND pins
± 125 mA
Storage Temperature Range, T5 1g ..• -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logiC
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vec=5V±10% Unless Otherwise Specified)
Ta=25°C
-'--.
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20J.tA
10=-4mA
Vcc -0.1
3.84
Vce -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20J.tA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
J.tA
Maximum Quiescent
Supply Current
Icc
2.0
20.0
40.0
J.tA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Icc
Vcc Vcc -0.1
4.2
3.98
0
VIN=Vee or GND
10uT=0J.tA
per input pin
VI=2.4V
other Inputs:
at Vce or GND
10UT=0J.tA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr , tf~6 ns), HCTLS133
Ta =25°C
Vcc=5.0V
KS74 HCTlS
Ta =-40°Cto +85°C
Vcc=5.0V±10%
Typ
Maximum Propagation Delay
Any Input to Y
tpLH
f-------
CL=50pF
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
Unit
Guaranteed Limits
18
24
30
36
18
25
30
36
pF
15
* CPD determines the no-load dynamic power dissipation: Po=Cpo VCC 2
ns
- - i------
pF
5
(per gate)
KS54 HCTlS
Ta = -55°C to +125°C
Vcc=5.0V± 10%
fin.
t For AC switching test circuits and timing waveforms see· section 2.
c8SAMSUNG
Electronics
512
KS54HCTLS
KS74HCTLS
138
3-Line to 8-Line Decoders/Demultiplexers
FEATURES
DESCRIPTION
• Designed specifically for high-speed memory
decoders and data transmission systems
• Incorporates 3 enable inputs to simplify cascading
andlor data reception
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with nL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices are designed to be used in highperformance memory-decoding or data-routing applications
requiring verv short propagation delay times. In highperformance (·lemory systems, these decoders can be
used to minimize the effects of system decoding. When
used with high-speed memories utilizing a fast-enable
circuit, the delay times of these decoders and the enable
time of the memory are usually less than the typical access
time of the memory. This means that the effective system
delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the three
e lable inputs 'select one of eight input lines. Two activelow and one active-high enable inputs reduce the neea for
external gates or inverters when expanding. A 24-line
decoder can be implemented without external inverters and
a 32-line decoder requires only one inverter. An enable
input can be used as a data input for demultiplexing
applications.
These devices' provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
Vee
B
YO
C
Y1
G2A
G2B
Y3
Y2
G1
Y4
Y7
Y5
GND
Y6
LOGIC DIAGRAM
FUNCTION TABLE
Enable
Inputs
G1
G2*
X
L
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
Select
Inputs
Outputs
C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
I
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
c8SAMSUNG
J=lpt'trnn;t'Cl.
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
513
I
3-Line to 8-Line DecoderSIOemultiplexers
Absolute Maximum Ratings·
Supply Voltage Range Vee,
.. -0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI> Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:,
Plastio Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
~S54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fa" Times, tr , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to. the device may oeeLlr.
Tl:lese are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
r------~.
Typ
Minimum High-Level
Input Voltage
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C fa= -55°C to +125°~ Unit
Guaranteed Limits
2.0
VIH
I
2.0
2.0
r - - - - - - . - - - -... - 1------- 1-.
Maximum Low-Level
Input Voltage
VIL
Minimum High-Level
Output Voltage
VOH
-~
0.8
0.8
V
c---
0.8
V
"" I-
r---------"
Maximum Low-Level
Output Voltage
VOL
f-.
Maximum Input
Current
Maximum Quiescent
Supply Current
r----~--.---
Additional Worst
Case Supply
Current
liN
Icc
-"-~-
61ee
VIN=VIH or VIL
10=- 2OIlA
10=-4mA
VIN=VIH or VIL
10=201lA
lo=4mA
10=8mA
VIN=Vee or GND
VIN=Vee or GND
10uT=01lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=01lA
c8SAMSUNG
•
I=lo.,..+rnni,...c::
Vee Vee -0.1
3.98
4.2
Ve.e -0.1
3.84
- - r-----------.--~
0
Vee -0.1
3.7
-~-~--~-----
V
r-------
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
±0.1
±1.0
±1.0
IlA
8.0
80.0
160.0
Il A
2.7
2.9
3.0
mA
V
---_.. _ - - - --
..
-~
514
KS54HCTLS
. KS74HCTLS
138
3-Line to 8-Line Decoders/Demultiplexers
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr • t,"6 ns), HCTLS138
Ta=25°C
Vcc=5.0V
KS74 HCTLS
Ta= -40°C to +85°C
Vcc=S.OV±10%
Typ
KS54 HCTLS
Ta =-55°Cto +125°C
Vcc=S.OV± 10%
Guaranteed Limits
tpLH
22
30
37
45
tpHL
22
30
37
45
24
32
40
48
24
32
40
48
18
25
31
37
18
25
31
37
Maximum Propagation Delay.
A or B to Y
f------
Maximum Propagation Delay.
G1 to any Y
r---
tPLH
tpHL
Maximum Propagation Delay.
G2A or G2B to any Y
~
CL=50pF
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
\)
Unit
ns
ns
ns
5
pF
50
pF
--
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
I
c8SAMSUNG'
Electronics
515
KS54HCTLS
KS74HCTLS
139
Dual 1.-01-4 Decoders/Demultiplexers
FEATURES
DESCRIPTION
• Designed specifically for high-speed memory
decoders and data transmission systems
• Incorporates 2 enable inputs to simplify cascading
and/or data reception
These devices are designed to be used in highperformance memory-decoding or data-routing applications
requiriring very short propagation delay times. In highperformance memory systems, these decoders can be
used to minimize the effects of system decoding. When
used with high·-speed memories utilizing a fast-enable
circuit, the delay times of these decoders and the enable
time of the memory are usually less than the typical access
time of the memory. This means that the effective· system
delay introduced by the decoder is negligible.
• Function, pin-out, speed arid drive compatibility with
54/74lS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10l =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '1 39 consists of two individual two-line to four-line
decoders in a Single package. The active-low enable input
can be used as a data line in demultiplexing applications.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
(Each DecoderlDemultiplexer)
1(3
vee
1A
2(3
1B
2A
1YO
2B
1Y1
2YO
1Y2
2Y1
1Y3
2Y2
GND
2Y3
ENABLE
G
"'X>~F===~[)
Y1
OUTPUTS
Y2
Y3
FUNCTION TABLE
Inputs
Enable
G
H
L
L
L
L
Outputs
Select
B
A
I
YO
Y1
Y2
Y3
X
L
L
X
L
H
L
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
ci$SAMSUNG
Electronic~
516
KS54HCTLS
KS74HCTLS
139
Dual 1-01-4 Decoders/Demultiplexers
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±35 mA
Continuous Current Through
Vee or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vce
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55 ° C to + 1 25 ° C
Input Rise & Fall Times, tr , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vce=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
Typ
KS74HCTLS
KS54HcTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20J.lA
lo=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20f-lA
10=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vec or GND
±0.1
±1.0
±1.0
f-IA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
f-IA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
f:l.lcc
VIN=Vee or GN[)
louT=Of-lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=OJ.lA
·c!5SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
517
I
13'9
K'S54HCTLS
KS74HCTLS . ,
Dual 1-of-4 Decoders/Demultiplexers
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions
t
(Input tr , tf~6 ns), HCTLS139
HClLS
!::~tTa= KS74
-40°C to +85°C
Ta=25°C
_~-=-~5.0V
Vcc=5.0V±10%
Typ
Maximum Propagation Delay,
r--!~LH__
A_o_r_B_t_O_Y~ _________--+_---,-tp_~
f-__
Maximum Propagation Delay,
G to any Y
,Maximum Input Capacitance
----------~---~
tpHL
r-21
21
CIN
--------------
5
-------
Unit
Guaranteed Limits
2~__~f--_
----------------- - -------1-..
Cpo
KS54 HCTLS
55°C t +125°C
10%
a~c~=5.0V:
_2_2_--t __3_0--+-_____~3_7___ ~__ i__-~--4-5-CL=50pF
I-!!'~.!!_
Power Dissipation Capacitance *
T
28
28
37
45
35
35
42
----f---------------------
--
--- --------
50
---
ns
~
ns
42
----------~-----~
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin,
t For AC switching test circuits and timing waveforms see section 2,
=8S~MSUNG
Electronics
518
KS54HCTLS
KS74HCTLS
148
8-Line to 3-Line Priority Encoders
.
FEATURES
DESCRIPTION
•
•
•
•
•
The '1 48 provides three bits of binary coded output
representing the position of the highest order active input,
along with an output indicating the presence of any active
input. It is easily expanded via input and output enables
to provide priority encoding over many bits.
•
•
•
•
•
•
Encodes eight data lines in priority
Provides 3-bit binary priority code
Input enable capability
Easily cascadable
Function, pin-out; speed and drive compatibility with
54/74LS logic family
Low power consumption characteristic of CMOS
High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V·
Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
Package options include "small outline" packages
(Available Tape & Ree!), standard DIPs.
7
GS
3
E1
A2
A1
GND
c8SAMSUNG
Electronics
Inputs
Vee
EO
6
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
PIN CONFIGURATION
4
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
0
AO
Outputs
--f------
EI
0 1 2 3 4 5 6 7
A2 A1 AO
H
L
L
L
L
L
L
L
L
L
X X X X
H H H H
X X X X
X X X X
X X X X
X X X X
X X X L
X X L H
X L H H
L H H H
H
H
L
L
L
L
H
H
H
H
X X
H H
X X
X X
X X
H H
X L
L H
X L H H
L H H H
H H H H
H H H H
H H H H
H H H H
H
H
L
L
H
H
L
H
H
H
H
L
L
H
H
H
H
L
L
L
GS EO
H
H
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
519
I
148
KS54HCTLS
KS74HCTLS
8-Line to 3-Line Priority Encoders
LOGIC DIAGRAM
(10)
O~~~~~EO
(11)
GS
(12)
3
(13)
(1)
(2)
(3)
(4)
(5)
E I - - - - - - - - Q ~_----------+--4.-
Absolute Maximum Ratings*
Supply Voltage Range Vcc, ... .
-O.5V to + 7V
DC Input Diode Current, hK
(VI < -O.5V or VI> Vcc +O.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vce +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
* Absolute Maximum Ratings are those values beyond
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, Vour
OV to Vee
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t F, tl
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
, .Electronics
522
KS54HCTLS
.KS74HCTLS
151
1-of-8 Data Selectors/Multiplexers
LOGIC DIAGRAM
(7)
(4)
DO
,..--(3)
01
>-----
~
(2)
02
>-----
~
(1)
03
~
DATA
INPUTS
'\
FL..J
(IS)
04
r-
~
~
-~
(5)
y
(6)
w
(14)
05
.-- ~
(13)
os
....- ;:::::L-I'\
(12)
"'
'--=L-I
(II)
I
A
(10)
B--
C
....
(9)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vce=5V±10% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
Minimum High-Level
Input Voltage
VIH
Maximum Low-Level
Input Voltage
VIL
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20j.lA
10= -6mA.
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20j.lA
10=12mA
10=24mA
KS54HCTLS
Guaranteed Limits
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
±0.1
±1.0
±1.0
j.lA
8.0
80.0
160.0
j.lA
2.7
2.9
3.0
mA
------
Maximum Input
Current
VIN=Vee or GND
liN
- - - - - -1 - - - Maximum Quiescent
VIN=Vee or GND
Icc
Supply Current
10uT=0j.lA
per input pin
VI=2.4V
Additional Worst
Case Supply
~Ice other Inputs:
at Vee or GND
Current
10uT=0j.lA
cg·SAMSUNG
Electronics
KS74HCTLS
Ta= -40°C to +85°C Ta= -55°C to + 125°C Unit
Vee Vee -0.1
3.98
4.2
0
V
\
523
KS54HCTLS
KS74HCTLS
151
1-01-8 Data Selectors/Multiplexers
AC ELECTRICAL CHARACTERISTICS
I
Characteristic
Symbol
Conditions t
tpLH
CL=50pF
CL=150pF
I
(Input t r , tf~6 ns), HCTLS151
T.=25°C
Vcc=5.0V
KS74HCTLS
T.= -40°C to +85°C
Vee = 5.0V: 10%
Typ
Maximum Propagation Delay,
A,B or C to Y
Maximum Propagation Delay,
A, B or C to W
Maximum Propagation Delay,
Any D to Y
Maximum Propagation Delay,
Any D to W
Maximum Propagation Delay,
G to Y
Maximum Propagation Delay,
G toW
I
l Maximum Input Capacitance
Power Dissipation Capacitance *
24
27
KS54HCTLS
T.= -55°C to +125°C
Vcc=5.0V: 10%
Guaranteed Limits
32
35
40
45
48
54
--~----------~-
tpHL
CL=50pF
CL=150pF
24
27
32
35
40
45
48
54
tpLH
CL=50pF
CL=150pF
27
30
36
39
45
50
54
60
tpHL
CL=50pF
CL=150pF
27
30
36
39
45
50
tPLH
CL=50pF
CL=150pF
20
23
26
29
33
38
tpHL
CL=50pF
CL=150pF
20
23
26
29
33
38
39
45
tpLH
CL=50pF
CL=150pF
16
19
21
24
26
31
32
38
tpHL
CL=50pF
CL=150pF
16
19
21
24
26
31
32
38
tpLH
CL=50pF
CL=150pF
20
23
26
29
33
38
39
45
tpHL
CL=50pF
CL=150pF
20
23
26
29
33
38
39
45
tpLH
CL=50pF
CL=150pF
20
23
26
29
33
38
39
45
tpHL
CL=50pF
CL=150pF
20
26
29
33
38
39
45
--t-------
---~~---~-
54
60
------
------
ns
--
t---~
39
45
23
~-t---
5
ns
ns
-ns
t---
ns
pF
CpD
.. Cpo determines the no-load dynamic power dissipation: PD=CPD Vcc 2
ns
-------- t - -
~~------~---
CIN
Unit
pF
fin-
t For AC switching test circuits and timing waveforms see section 2.
dCSAMSUNG
• • Electronics
524
KS54HCTLS
KS74HCTLS
153
FEATURES
DESCRIPTION
• Allows Multiplexing from N Lines to 1 Line
• Performs Parallel-to-Serial Conversion
• Strobe (Enable) Line Provided for Cascading
(N lines to n lines)
• '253 is the 3-State Version of this port
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
(IOL = 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +8S o C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
Each of these data selectors/multiplexers contains inverters
and drivers to supply full binary decoding data selection to
the AND-OR gates. Separate strobe inputs (0) are provided for each of the two four-line sections.
These devices provide speeds and drive capability'
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
FUNCTION TABLE
=
1<3
Vee
B
2<3
1C3
1C2
1C1
1CO
1Y
GND
IIII
Dual 1-01-4 Data Selectors/Multiplexers
A
2C3
2C2
2C1
2CO
2Y
c8SAMSUNG
Electrnnic!':
'
All inputs and outputs are protected from damage due to
static discharge by internal diode· clamps ,to Vcc and
ground.
SELECT
INPUTS
DATA INPUTS
B
A
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
CO C1
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
C2 C3
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
H
L'
STROBE
OUTPUT
G
y
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
525
I
Dual 1-01-4 Data SelectorslMultipiJlxers
LOGIC DIAGRAM
IV
2V
Absolute Maximum Ratings·
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vec +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vec +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±70 mA
Continuous Current Through
Vce or GND pins
. . . . . . . . . . . .. ±250 mA
StorageTemperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
• Absolute Maximum' Ratin9s are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
.
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/o C from 65 ° C to 85 ° C
Recommended Operating Conditions
Supply Voltage, Vce
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
.
526
153
KS54HCTLS
KS74HCTLS
Dual 1-of-4 Data Selectors/Multiplexers
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
KS74HCTLS
~J:
KS54HCTLS
T.= -40°C to +85°C T.==-.-55°C t~ +125~~ Unit
T.=25°C
Test Conditions
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
Maximum Low-Level
Input Voltage
VIL
Minimum High-Level
Output Voltage
VOH
V
.. t----
0.8
0.8
Vee -0.1
3.84
Vee -0.1
3.7
0.1
0.26
0.39
0.1
0.33
0.5
0.4
±0.1
±1.0
±1.0
8.0
80.0
160.0
0.8
VIN=VIH or VIL
lo=-20jJA
lo=-6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20jJA
lo=12mA
lo=24mA
Maximum Input
Current
liN
VIN=Vee or GND
Vee Vee -0.1
4.2
3.98
0
V
V
---------- --- --
0~1
V
-----
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
2.0
2.0
2.0
Icc
Lllee
VIN=Vee or GND
louT=OjJA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour=OjJA
.-- - - - - - - -
._--
2.7
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
2.9
3.0
::1
mA
I
(Input t r , tf~6 ns), HCTLS153
T.=25°C
Vcc=5.0V
KS74HCTLS
T. = - 40°C to + 85°C
Vcc=5.0V±10%
KS54HCTLS
T.= -55°C to +125°C
Vcc=5.0V± 10%
Unit
- -
Typ
Maximum Propagation Delay,
A or 8 to Y
tPLH
23
26
30
33
38
43
45
51
tpHL
CL=50pF
CL =150pF
2;3
26
30
33
38
43
45
51
tpLH
CL=50pF
CL=150pF
15
18
20
23
25
30
30
36
tpHL
CL =50pF
CL =150pF
15
18
20
23
25
30
30
36
tpLH
CL=50pF
CL=150pF
21
24
28
31
35
40
42
48
tpHL
CL=50pF
CL=150pF
21
24
28
31
35
40
42
48
r-
Maximum Propagation Delay,
Data (Any C) to Y
Maximum Propagation Delay,
Y
G to
Guaranteed Limits
CL =50pF
CL=150pF
--~--
ns
---
-------
----
CIN
Power Dissipation Capacitance *
Cpo
5
ns
. _ - - - 1----
-~
Maximum Input Capacitance
---
ns
t----
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronic!':
527
15'HA
KS54HCTLS
KS74HCTLS··
4-Line to 16-Line Decoders/Demultiplexers
FEATURES
DESCRIPTION
• Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive Outputs
.
• Performs the Demultlplexing Function by Distributing
Data From One Input to Any One of 16 Outputs
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These monolithic, 4·lineto 16·line decoders decode four
binary· coded inputs into one of sixteen mutually exclusive
outputs when both the strobe inputs. <31 and (32, are low.
The demultiplexing function is performed by using the 4
input lines to address the output line, passing data from
one of the strobe inputs with the other strobe input low.
When either strobe input is high, all outputs are high. These
demultiplexers ,are ideally suited [for implementing highperformance memory decoders.
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
r-'_
A_
B
0
(1)
C
0
Vee
A
~
A
B
3
4
C
0
5
<32
6
7
8
~
Gl
G2
B ...------- H
(18)
(4)
(19)
I
~-
I
>----
12
(5)
c ,----
15
AI
(23)
>-0--
~
13
GND
(3)
G
<31
14
(2)
>-""""-
B
(22
11
(21
61
~-
cl
cl
o-r-----
>----
I
(7)
(8)
>-~
,I
(20
(6)
~-
I
i 0-;- f - -
-- ~-- r--
D
0
I
~
~
~~
>- r---
>--- ~-
c
o-~
o-~
ii
>-~
0-
A
(10)
-
(13
-
(15
-~
~:::::::
>-- r---1-
'13
(16
~t--~
A
G~
(17
BL--d
CD~
c8SAMSUNG
Electronics
528
KS54HCTLS
KS74HCTLS
154
4-Line to 16-Line Decodillfll8lemultiplexers
FUNCTION TABLE
Inputs
Outputs
G1
G2
D
C
B
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
I
Absolute Maximum Ratings*
Supply Voltage Range Vee, ...
.. -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
± 125 mA
Vee or GND pins
Storage Temperature Range, TSlg ... -65°C to +150°C
Power Dissipation Per Package, P d t . . . 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to\+125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GN D)
529
KS54HCT'~~":)164
KS74HCTLS" ."
4-Line to 16-Line Decoders/Demultiplexers
DC ELECTRICAL CHARACTERISTICS
(Vcc=5V±10% Unless Otherwise Specified)
o
Characteristic
Symbol Test Conditions
~
I
KS74HCTLS
I
KS54HCTLS
to +12~~ Unit
~a,~~~~a= -=~~~o +8~Ta= ~55°C
Typ
Guaranteed Limits
Minimum High-Level
V
2.0
2.0
2.0
Input Voltage
IH
---------.---- -------- ----------_.. _-------+-+----+---------------+---------+-------I
Maximum Low-Level
0.8
V
0.8
0.8
Input Voltage
VIL
v
f - - .. - - - - - - - - - - --------
Minimum High-Level
Output Voltage
------------------+----t----t------ - ..- - - - - - - - - + - - - - - - - - - - - - - + - - - - 1
VOH
t-----------.. - - - - - - - -
Maximum Low-Level
Output Voltage
f------------------
VIN=VIH or VIL
lo=- 20 /AA
Vcc Vcc -0.1
Vcc -0.1
Vcc -0.1
V
lo=-4mA
4.2
3.98
3.84
3.7
-=-------+----+--------f-----------..--------- - - ----- ------------------- ---VIN=VIH or VIL
lo=20/AA
0
0.1
0.1
0.1
lo=4mA
0.26
0.33
0.4
V
lo=8mA
0.39
0.5
- - - - - - - - - - - - -.. ----+---+--------------r---------
-
Maximum Input
Current
±0.1
--..---~-------------
±1.0
±1.0
/AA
}----------------+-----t----------- - f - - - - - - I - - - - - - - - - - - - - - - ------ ..- - - - - - - - - + - - - - I
Maximum Quiescent
Supply Current
-
--~-------
--------
Additional Worst
Case Supply
Current
I
cc
VIN=VCC or GND
IOUT=O/AA
input pin~ --
80,0
8.0
160.0
/AA
-- ------ Per
bolcc
VI=2.4V
other Inputs:
at Vcc or GND
lour=O/AA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
3.0
2.7
Conditions t
(Input t r , tf~6 ns), HCTLS154
::~T
T =25°C
a
V
Vcc=5.0
----
a
- - _ .. _ - - - - - - -
c---
a
Vcc=5.0V± 10%
Guaranteed Limits
28
35
42
21
28
35
42
21
28
35
42
21
- - c-5
28
35
42
~
tpHL
tpLH
-tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
CL=50pF
Unit
------------
21
tpLH
t----------------- - - -
Maximum Propagation Delay,
G 1 or G2 to Any Output
HCTLS~,
KS54HCTLS
T =-55°Cto+125°C
KS74 '
=-40°Cto+85°C
Vcc=5.0V±10%
Typ
Maximum Propagation Delay,
A, S, C or D to Any Output
R
ns
ns
pF
pF
* CpD determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
530
KS54HCTLS
KS74HCTLS
155
Dual 2-to-4 Line
Decoder~/Demultiplexers
FEATURES
DESCRIPTION
• Typical applications:
Dual 2-t0-4 line decoder
Dual 1-t0-4 line demultiplexer
3-t0-8 Ii ne decoder
1-t0-8 line demultiplexer
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOl =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '1 55 consists of two 1 -to-4 line demultiplexers with
independent strobes and common binary address inputs.
When both sections are enabled by the strobes, the common address inputs sequentially select and route
associated input data to the appropriate output of each secton. The individual strobes permit activating or inhibiting
each of the 4-bit sections as desired. Data applied to input C1 is inverted at its outputs and data applied to C2
is true through its outputs. The inverter following the C1
data input permits use as a 3-to-8 line decoder, or 1-to-8
line demultiplexer, without gating.
PIN CONFIGURATION
These devices provide' speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
I
LOGIC DIAGRAM
C1
Vee
G1
C2
B
G2
1Y3
A
1Y2
2Y3
1Y1
2Y2
1YO
2Y1
GND
2YO
G1
C1
B
1Y3
2YO
A
C2
G2
=8SAMSUNG
Electronics
2Y3
531
KS54HCTLS155
KS74HCTLS
Dual 2-to-4 Line Decoders/Demultiplexers
FUNCTION TABLES
2-t0-4 Line Decoder or 1-t0-4 Line Demultiplexer
Inputs
Select
B
X
L
L
H
H
X
A
X
L
H
L
H
X
Data
G1
C1
H
L
L
L
L
X
Select
Outputs
Strobe
X
H
H
H
H
L
1YO
1Y1
H
L
H
H
H
H
H
H
L
H
H
H
1Y2
H
H
H
L
H
H
1Y3
H
H
H
H
L
H
Inputs
Outputs
Select
Strobe
Data
A
G2
C2
2YO
2Y1
2Y2
2Y3
X
L
L
H
X
H
L
L
L
L
X
X
L
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
I~
X
ct
BA
X XX
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
Strobe
or Data
G*
H
L
L
L
L
L
L
L
L
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2YO 2Y1 2Y2 2Y3 1YO 1Y1 1Y2 1Y3
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
t = Inputs C1 and C2 Connected together
B
L
H
L
H
3-to-8 Line Decoder or Ho-8 Line Demultiplexer
:I: = Inputs G1 and G2 Connected together
Absolute Maximum Ratings*
Supply Voltage Range Vcc, .. ,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-O.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins . . . . . . . .
± 125 mA
Storage Temperature Range, T5 tg . . . -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may.affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
532
155
KS54HCTLS
KS74HCTLS
Dual 2-to-4 Line Decoders/Demultiplexers
DC ELECTRICAL CHARACTERISTICS
Charact9ristic
Symbol
Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
Ta =25°C
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
liN
Maximum Quiescent
Supply Current
Icc
VIN=VIH or VIL
lo=-20~A·
Vcc Vcc -0.1
4.2
3.98
lo=-4mA
VIN=VIH or VIL
Additional Worst
Case Supply
Current
E.lcc
lo.=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=VCC or GND
±0.1
±1.0
±1.0
~A
8.0
80.0
160.0
~A
2.7
2.9
3.0
mA
lo=20~A
0
VIN=VCC or GND
louT=O~A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
louT=Oj.lA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r ,
KS74 HCTLS
KS54 HCTLS
T. = 25°C
T. = -40°C to +85°C T. = -55°C to +125°C
Unit
Vce=5.0V
Vee = 5.0V:!: 10%
Vee=5.0V:!: 10%
Typ
Maximum Propagation Delay,
tpLH
A, S, C2, G1 or G2 to any Output r--------(2 levels of logic)
tpHL
I
tf~6 ns), HCTLS155
Guaranteed Limits
17
23
29
35
17
23
29
35
21
28
35
42
tpHL
21
28
35
42
. Maximum Propag?tion Delay,
A or S to any Y
(3 levels of logic)
r---------
Maximum Propagation Delay,
C1 to any Y
r---------
tpLH
CL =50pF
tpHL
20
27
34
41
tpHL
20
27
34
41
Maximum Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
533
KS54HCTLS
KS74HCTLS
15·~/158
I
Quad 2-Line to 1-Line Data
Selectors/Multiplexers
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL.=8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These are data selectors;multiplexers which select a 4-bit
word from one of two sources via' the control of a common select input (AlB). A separate strobe input (<3) is provided. The '157 presents true data whereas the '158
presents inverted data at the outputs.
PIN CONFIGURATION
FUNCTION TABLE
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
Output Y
Inputs
AlB
Vee
1A
G
Strobe
Select
1B
4A
G
AlB
A
B
1Y
4B
2A
4Y
H
2B
3A
X
L
2Y
3B
X
L
L
H
GND
3Y
H
H
X
X
X
X
X
L
L
L
L
L
Data
H
'157
'158
L
L
H
H
H
L
L
H
H
L
LOGIC DIAGRAMS
'158
'157
(2)
1A
1A
(2)
lB~(3~)__________~~~
1Y
2A
2A (5)
2B
(6)
2Y
(13)
1Y
(5)
(6)
2B
2Y
3A
3Y
3B (10)
(14)
4A--
4A (14)
4B-------------+~~
(3)
(11)
(11)
3A------------~~~
3B (10)
1B
4Y
4B (13)
STROBE (15)
G"-------cr~
SEL~~ (1)
c8SAMSUNG
Electronics
SELECT
AlB (1)
534
15.7,'158
,
KS54HCTLS
KS74HCTLS
Quad 2-Line to 1-Line Data
Selectors/Multiplexers
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) .
±35 mA
Continuous Current Through
Vcc or GND pins
± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce
4.5V to 5.5V
DC Input & Output Voltages·, YIN, Vour
OV to Vcc
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Minimum High-Level
Input Voltage
(Vcc=5V± 1 0% Unless Otherwise Specified)
2.0
---- ...
~--r-----
Maximum Low-Level
Input Voltage
-----~-----.-
Minimum High-Level
Output Voltage
r----.---~~---
V
r----
0.8
IL
~~j---------
VOH
2.0
VIN=VIH or VIL
lo=- 20IlA
10=-4mA
----+----t---
------~-
=8SAMSUNG
Electronics
0.8
-- r---
-
Vee Vee -0.1
4.2
3.98
- -- - t--------
2.0
I
----~-------
--
Vee -0.1
3.84
--_.,--
0.8
Vee -0.1
3.7
, 535
15'7115
Quad· 2-Line to 1-Line Data
Selectors/Multiplexers
'0
KS54HCTLS
KS74HCTlS"· " ··,.10
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr • tf~6 ns). HCTLS157. HCTLS158
Ta =25°C
Vee=5.0V
KS74 HCTLS
Ta= -40°C to +85°C
Vee = 5.0V:!: 10%
Typ
Maximum Propagation Delay.
AorBtoY
tpLH
r----tpHL
11
11
Maximum Propagation Delay.
AlB to Y
r------
tPLH
17
tPHL
17
Maximum Propagation Delay.
to Y
r------
tpLH
15
15
5
G
" tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
KS54 HCTLS
Ta= -55°C to +125°C
Vee=5.0V:!: 10%
Unit
Guaranteed Limits
15
15
23
23
20
20
19
19
29
29
25
25
22
22
34
34
30
30
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
536
KS54HCTLS
KS74HCTLS
160Al161A
162A1163A
Synchronous 4-Sit Decade
and Binary Counters
FEATURES
DESCRIPTION
•
•
•
•
•
These are synchronous, presettable 4-bit binary counters
featuring internal carry-look-ahead for high-speed counting.
The '160 and '162 are decade counters, and the '161
and '163 are 4-bit binary counters. The buffered clock input triggers all flip· flops simultaneously on the rising edge
of the input waveform. This eliminates the output counting
spikes normally associated with asynchronous counters.
Internal Look Ahead for Fast Counting
Carry Output for n-bit cascading
Synchronous Counting
Synchronously Programmable
Function, pin-out, speed and drive compatibility with
54/74LS logic family
Low power consumption characteristic of CMOS
High-Drive-Current outputs:
10l =8 mA @ Val =0.5V
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
Package 9ptions include "small outline" packages
(Available Tape '& Reel), standard DIPs.
•
•
•
•
•
•
ClR
ClK
A
B
Two E;mable inputs and a ripple carry output allow easy
cascading of the counters. Both count-enable inputs (ENP
and ENT) must be high to count, and ENT is fed forward
to enable the ripple carry output. The ripple carry output
(RCO) thus enabled will produce a high-level pulse while
the count is maximum (9 or 15 with QA high). This highlevel overflow ripple carry pulse can be used to enable successive cascaded stages. Transitions at the ENP or ENT
are allowed regardless of the level of the clock input.
C
D
ENP
GND
FUNCTION TABLES
'160, '161
CLK CLR ENP ENT LOAD
t
t
L
H
H
H
H
H
X
X
X
H
L
L
L
H
L
H
H
H
L
H
X
X
H
H
Function
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment Counter
'162, '163
CLK
t
I
I
X
X
X
t
t
CLR ENP ENT LOAD
L
H
H
H
H
H
X
X
H
L
L
L
H
L
X
H
X
H
X
H
H
H
L
H
The clear function for the' 1 60 and' 1 61 is asynchronous
and a low level at the clear input sets all four of the flipflop output::; low regardless of the levels of the clock, load
or enable inputs.
The clear function for the '162 and 163 is synchronous.
and a low level at the clear input sets all four of the flipflop outputs low after the next clock pulse, regardless of
the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily as decoding
the maximum count desired can be accomplished with one
external NAND gate. The gate output is connected to the
clear input to synchronously clear the counter.
PIN CONFIGURATION
X
X
X
X
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables
the counter and causes the outputs to agree with the setup
data after the next clock pulse regardless of the levels of
the enable inputs.
Function
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
",crement Counter
c8SAMSUNG
Electronics
These counters feature a fully independent clock circuit.
Changes at control inputs (ENP, ENT, or LOAD) that will
modify the operating model have no effect on the contents
of the counter until clocking occurs. The function of the
counter (whether enabled, disabled, loading, or counting)
will be dictated solely by the conditions meeting the stable
setup and hold times.
These devices provide speeds and drive capability
equivalent to their ALSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
537
I
KS54HCTL~ 160Al161A
KS74HCTLS
162A1163A
Synchronous 4-Bit Decade
and Binary
Counters
_- --
..
-
_
..
---
LOGIC DIAGRAMS
'160A or '162A
OB
CK
CK
a::R
a::R
ENT
RCO
13)
14)
C
D
'161A or '163A
CK
CK
CK
CK
a::R
ClR
ClR
ClR
Reo
(3)
14)
A
c8SAMSUNG
Electronics
538
KS54HCTLS
KS74HCTLS
160Al161A
162A1163A
Synchronous 4-Bit Decade
and Binary Count,rs
Typical Clear, Preset, Count and Inhibit Sequences
'161A or '163A
'160A or '162A
CLR
160
CLA
162
LOAD
A
.----- ------- --
_
_-4--.... -_ -_ ._
-_
- _
- _
- _
- _
- _
- _
- _
- _
- -_
--4----'
.,-
--- - - --- - - - - --+----..&_- - - - - - - - - - - - -
--+--.... - - - - - - - - - - - - - OATA
INPUTS
==============
CLK
CLK
160
HI1
CLK
CLK
162
ENP
---+---4J
-+--4I't------+----.
ENT _ _
OUTPUTS
L= =============
-+-_..& ____________ .__
8
: __
{
::==
{00==
~::, ___t__l.ri------"l__--..J
ENT--4--4I
Oc : : ::
RCO
--+_-+--+-...J
2
I
CLEAR
3
--+---INHIBIT-PRESET
Sequence:
( 1) Clear outputs to zero
(2) Preset to BCD seven
(3) Count to eight, nine, zero, one, two, and three
(4) Inhibit
I
1
2
-_+---INHIBlT--
CLEAR PRESET
Sequence:
( 1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one and two
(4) Inhibit
I
Absolute Maximum Ratings·
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -6SoC to +1S0°C
Power Dissipation Per Package, Pdt
500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.SV to S.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -5SoC to +125°C
Max SOO ns
Input Rise & Fall Times, t r , tf
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
539
KS54HCTLS
·KS74HCTLS
160Al161A
·162A1163A
DC ELECTRICAL CHARACTERISTICS
Characteristic
Synchronous 4-Bit Decade
and Binary Counters
(Vcc=5V±10% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
V,H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V,L
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
V,N=V,H or VrL
lo=-20/AA
lo=-4mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
V,N=V,H or VrL
lo= 2O/AA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
VrN=Vcc or GND
±0.1
±1.0
±1.0
I-'A
V'N=VCC pr GND
IOUT=Of.'A
per input pin
V,=2.4V
other Inputs:
at Vcc or GND
louT=Of.'A
8.0
80.0
160.0
/AA
2.9
3.0
mA
Maximum Input
Current
liN
Maximum Quiescent
~y Current
Icc
------~--
Additional Worst
Case Supply
Current
.6. Icc
Vcc Vcc -0.1
4.2
3.98
0
/---
2.7
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Input tr, tf~6 ns), HCTLS160A, HCTLS161A
T.=25°C
Conditions t Vcc=5.0V
KS74HCTLS
KS54HCTLS
T.= -40°C to +85°C T.=-55°C to +125°C
Vec=5.0V:t: 10%
Vee = 5.0V:t: 10%
Typ
40
30
25
20
Maximum Propagation Delay,
CLK to RCO
tpLH
r---tpHL
26
35
44
53
26
35
44
53
Maximum Propagation Delay,
CLK to any Q
~-
Maximum Propagation Delay,
ENT to RCO
I---
tpLH
20
26
33
39
tpHL
20
26
33
39
CL =50pF
Unit
Guaranteed Limits
f max
Maximum Clock Frequency
V
- - +--
MHz
ns
ns
tpLH
11
14
18
21
tpHL
11
14
18
21
Maximum Propagation Delay,
CLR to any Q
tpHL
21
28
35
42
ns
Maximum Propagation Delay,
CLRto RCO
tpHL
21
28
35
42
ns
Minimum Pulse
Width
Minimum Setup
Time before
CLKt
10
13
17
20
10
13
17
20
A, B~ C, D
10
13
17
20
LOAD
10 13
17
20
10
13
17
20
10
13
17
20
0
0
0
0
CLK High or Low
CLR Low
ENP, ENT
tw
tsu
CLR inactive
Minimum I Hold Time,
All Synchronous Inputs after CLKt
th
ns
ns
ns
ns
Input Capacitance
C,N
5
pF
Power Dissipation Capacitance *
Cpo
80
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vce 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
540
KS54HCTLS
KS74HCTLS
160Al161A
162A1163A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Synchronous 4-Bit Decade
and Binary Counters
(Input t r , tf~6 ns), HCTlS162A, HCTlS163A
To=25°C
Conditions t Vcc=5.0V
KS74HCTLS
KS54HCTLS
To= -40°C to +85°C To= -55°C to +125°C
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Guaranteed Limits
Maximum Clock Frequency
fmax
40
30
25
20
Maximum Propagation Delay,
ClK to RCa
tpLH
r------------
26
35
44
53
tpHL
26
35
44
53
Maximum Propagation Delay,
ClK to any Q
r------------
20
26
33
39
20
26
33
39
Maximum Propagation Delay,
ENT to RCa
r--
tpLH
11
14
18
21
tpHL
11
14
18
21
Maximum Propagation Delay,
ClR to any Q
tpHL
21
28
35
42
ns
Maximum Propagation Delay,
ClR to RCa
tPHL
21
28
35
42
ns
Minimum Pulse
Width
Minimum Setup
Time before
ClKt
tPLH
tpHL
ClK High or low
CL=50pF
10
13
17
20
ClR low
10
13
17
20
A, B,C, D
10
13
17
20
lOAD
10
13
17
20
10
13
17
20
ClR inactive
10
13
17
20
ClR low
10
13
17
20
0
0
0
0
tw
ENP, ENT
Minimum Hold Time,
All Synchronous Inputs after ClKt
tsu
th
ns
ns
ns
ns
ns
ns
CIN
5
pF
Power Dissipation Capacitance *
CPD
80
pF
c8SAMSUNG
•
MHz
Input Capacitance
* CPD determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
IIII
Unit
Electronics
fin
541
I
16
KS54HCTLS
A
KS74HCTLS .' .&.f
1
8-Bit Seriai-in/Parallei-Out Shift Registers
DESCRIPTION
FEATURES
•
•
•
•
•
•
•
•
•
•
AND-Gated ~nable/disable) serial inputs
Fully buffered clock and serial inputs
Direct clear
Function, pin-out, speed and drive co'mpatibility with
54/74lS logic family
low power consumption characteristic of CMOS
High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74HCTlS: -40°C to +85°C
KS54HCTlS: -55°C to +125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These'are high-speed 8-bit registers with AND-gated serial
inputs and an asynchronous clear. Data is entered serially
through either one of the two inputs, A and B. A high on
one input enables the other one, which will then determine
the state of the, first flip-flop. A low at either or both inputs
inhibits data entry and resets the first flip-flop to a low level
at the next positive clock transition.
Data at the serial inputs may be changed while the clock
1s high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-highlevel transition of their clock input.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
FUNCTION TABLE
Inputs
Vee
--+-, ..,-",.
Outputs
--.
OH
Clear
Clock
A
B
QA
O.
OG
O.
L
OF
X
X
H
L
X
X
X
H
X
L
L
L
L
H
H
X
L
Q'AO
OBO
OHO
Oc
OE
OD
CLR
3ND
H
CLK
H
t
t
t
Oa ..• OH
H
OAn
OGn
L
L
OAn
OGn
OAn
OGn
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input. including tranSitions)
t = transition from low to high level.
OAO. OBO. OHo=the level of OA. OB or OH. respectively. before the indicate steadystate input conditions were established.
OAn. OGn = the level of OA or OG before the most,recent t transition of the clock;
indicates a one-bit shift.
c8SAMSUNG
Electronics
542
16~A
KS54HCTLS
KS74HCTLS
1
8-Bit Seria!-!nIParalle!-OutShift Registers
LOGIC DIAGRAM
CIR...:...19..:..'_--4!II
(3)
o.
(4)
as
(5)
(6)
(10)
I
00
Oc
(11)
Oe
OF
(12)
(13)
OG
OH
PARALLEL OUTPUTS
I
Typical Clear, Shift, and Clear Sequences
U
1
A
--+------.
,B
--+------'
SERIAL {
INPUTS
L-fl----------~l--~-----I
I
--,
08 _ _ """_ _ _ _ _ _ _ _---J
LJI
LJl
Oc: : .,""',_ _ _ _ _ _ _ _ _ _--1
--,
--,
0 0 __
OUTPUTS
I
I
i
LJrl~_+I--~--__
....
' _ _ _ _- - - '_ _ _ _ _ _---J
LIli---T-
Oe _ _ ....
, - -_ _ _ _ _ _ _ _ _ _ _..J
1
LJ1~1-
-----
--.,
I
I
-.,....' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-..JJr---. _______
OG __
OF _ - ...., - - - -_ _ _ _ _ _ _ _ _ _ _...J
1
I~
--,
rl....I _ _ _ _ __
OH __ .r..'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J
CLEAR
c8SAMSUNG
Electronics
I
CLEAR
543
KS54HCTLS
KS74HCTLS
'164
8-Bit Serial-lnIPatalle/-Out",ShiftRegfsters
Absolute Maximum Ratings·
Supply Voltage Range Vee, ...... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V) . . .. ±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) .
±35 rnA
Continuous Current Through
Vee or GND pins
± 125 rnA
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt . . . .. 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress' ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these eondition's may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
Recommended Operating Conditions
Supply Voltage, Vee . .
. ....... 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to + 125°C
Max 500 ns
Input Rise & Fall Times, t r , tf ...
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20JlA
10=-4mA
Vee -0.1
3.84
Vee .,-0.1
3.7
V
Maximum Low-Level
Output Voltage,
VOL
VIN=VIH or VIL
10=20,..A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
,..A
Maximum Quiescent
Supply Current
lee
8.0
80.0
160.0
Additional Worst
Case Supply
Current
t:.lee
VIN=Vce or GND
10UT=0,..A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0,..A
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
,..A
-~---
2.7
2.9
3.0
rnA
544
KS54HCTLS
KS74HCTLS
164.
,8-Bit Serial-lnIParallel-Out Shift Registers
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr •
tf~6
ns), HCTlS164
KS74HCTLS
KS54HCTLS
Ta=25°C Ta= -40°C to +85°C Ta= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V±10%
Vcc=5.0V± 10%
Guaranteed Limits
Typ
Maximum Clock Frequency
fmax
I Maximum
Propagation Delay.
ClR to any Q
Maximum Propagation Delay.
ClK to any Q
Minimum
Pulse Width
ClR low
tpLH
40
30
25
20
MHz
27
36
45
54
ns
CL=50pF
-
tpLH
22
30
37
45
tpHL
22
30
37
45
10
13
17
20
10
13
17
20
tw
ClK High or low
Data
Minimum Setup
Time before ClKt ClR Inactive
tsu
Minimum Hold Time
Data after ClKt
8
10
13
15
8
10
13
15
th
0
5
5
5
Maximum Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo. (per package) 120
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc 2
t For AC switching test circuits and timing waveforms see section 2.
ns
ns
ns
ns
pF
pF
fill
I
c8SAMsUNG
Electronics
545
KS54HCTLS
KS74HCTLS
165
8-Bit Parallel-lnISerial-Out Shift Registers
FEATURES
DESCRIPTION
•
•
•
•
•
These are high-speed 8·bit parallel-load or serial-in shift
registers with complementary serial outputs available from
the last stage. Parallel-in access is asynchronous and is
enabled by pulling the SH/LD input low. When SH/LD is
high, data is entered serially at the SER input and shifted
one place to the right with each positive clock transition.
•
•
•
•
•
•
Complem;entary outputs
Direct overriding load (data) inputs
Gated cldck inputs
Paraliel-t~Serial data conversion
Function, pin-out, speed and drive compatibility with
54/74LS lOgic family
Ldw pow~r consumption characteristic of CMOS
High-Drive..current outputs:
IOL =8 miA @ VOL =O.5V
Inputs antt outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74HCTlS: -40°C to +85°C
KS54HCTlS: -55°C to +125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
SHILo
ClK
These devices provide speeas and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
Inputs
Vee
elK JNH
F
o
c
G
B
H
A
E
Clocking is accomplished through a 2-input NOR gate which
permits one of the clock.s to be used as a clock inhibit function. Holding either clock input high inhibits clocking. Either
clock input is enabled by holding the other clock input low
while the SH/LD input is high.
SER
SHILD
L
H
H
H
H
CLK
INH
Function
H
X
X
X
H
PARALLEL LOAD
NO CHANGE
NO CHANGE
SHIFT·
SHIFT·
CLK
X
L
t
t
L
'Content of each internal register shifts toward output QH. Data
at serial input is shifted into first register.
c8SAMSliNG
Electronics
546
KS54HCTLS
KS74HCTLS
165
8-Bit Parallel-lnISerial-Out Shift Registers
LOGIC DIAGRAM
PARALLEL INPUTS
Typical Shift, Load and Inhibit Sequences
I
CLK
ClK INH
I.
SER"~__________~_______________________________
SH/[O~
I
____
A~
B
1
~
_______________________ _
:L
c~~__+-________________________
PARALLEL
DATA
INPUTS
1
D
I
L
E~~__~___________________________
I
:~~--~----------------------------~H~~__~________________________________
a~r--------+-H----H"""'I~
-111-------
!--INHIBIT ....
lOAD
c8SAMSUNG
Electronics
SERIAL-SHIFT
547
KS54HCTLS
KS74HCTLS
165
8-Bit Parallel-lnISerial-Out Shift Registers
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V) .. .' .. ±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-O.5V < Vo < Vce +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins . . . . . . . .
. . . .. ± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . .
4.5V to 5:5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf ........ Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vce or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
Ta=25°C
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20jJA
lo=-4mA
Vce -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20jJA
lo=4mA
lo=8mA
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vec or GND
±1.0
'±1.0
jJA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
jJA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Alec
VIN=VCC or GND
louT=OjJA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
IOUT=OjJA
c8SAMSUNG
Electronics
Vee Vec -0.1
4.2
3.98
0
0.1
0.26
0.39
±0.1
II
548
KS54HCTLS
KS74HCTLS
165
8-Bit Paral/e/-/n/Seria/-Out Shift Registers
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions l
(Input tr, tf~6 ns), HCTlS165
KS74HCTLS
KS54HCTLS
T. =25°C
Ta= -40°C to +85°C Ta=-55°C to +125°C
Unit
Vee=5.0V
Vcc=5.0V:!: 10%
Vee = 5.0V:!: 10%
Guaranteed Limits
Typ
Maximum Clock Frequency
f max
40 30
25
20
Maximum Propagation Delay,
SH/iJ) to QH or QH
~
26 35
44
53
26 35
44
53
Maximum Propagation Delay,
ClK to QH or QH
~
30 40
50
60
tpHL
30 40
50
60
Maximum Propagation Delay,
H to QH or QH
tpLH
r--tPHL
20 27
34
41
20 27
34
41
tpHL
7 10
13
15
13 16
20
25
SH/lD High
before CLKt
13 16
20
25
SER before ClKt
10 13
17
20
13 16
20
25
13 16
20
25
5
7
8
10
-3
0
0
0
-3
0
0
0
SH/lD low
Minimum
Pulse Width ClK High or low
Minimum
ClK INH low
Setup Time before ClKt
tw
tsu
ClK INH High
before GlK~
Data before SH/lDt
Minimum
Hold Time
CL "';50pF
SER Data after ClKt
th
PAR Data after SH/lDt
Maximum Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
100
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
MHz
ns
ns
ns
ns
ns
ns
pF
pF
fin.
549
I
KS54HCTLS
KS74HCTLS
168.:"
/
8-Bit Parallel-lnISerial-Out
Shift Regi~ters with Clear
FEATURES
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
Synchrono~sload
Direct overriding clear
Parallel to serial conversion
Function, pin-out, speed and drive compatibility with
54/74LS logic family
Low power consumption characteristic of CMOS
High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices feature paraileHn or serial·in. serial·out
registers. gated clock inputs and an overriding clear input.
The paralled·in or serial-in modes are established by the
shift/load input. When high. the input enables the serial data
input and couples the eight fill-flops for serial shifting with
each clock pulse. When low. the paralled data inputs are
enabled and synchronous loading occurs on the next clock
pulse. During parallel loading. serial data flow is inhibited.
Clocking is accomplished on thelow-to-high edge of the
clock pulse through a two-input positive NOR gate permitting one input to be used as a clock-enable or clock-inhibit
function. Holding either of the clock inputs high inhibits
clocking; holding either low enables the other clock input.
This allows the system clock to be free-running and the
register can be stopped on command with the clock input. The clock-inhibit input should be changed to the high
level only when the clock input is high. A buffered direct
clear input overrides all other inputs. including the clock.
and sets all flip-flops to zero.
'These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL. NMOS and CMo"S devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
PIN CONFIGURATION
SER
A
FUNCTION TABLE
sH/D5
s
c
QH
0
G
ClK INH
F
H
ClK
E
GND
ClR
.c8SAMSUNG
Electronics
'
Inputs
Vee
ClR
L
H
H
H
H
H
SHI
LD
X
X
L
H
H
X
Internal
Parallel Outputs
ClK
INH
elK
SER
X
X
L
L
L
L
H
L
X
X
X
a ... h
H
L
X
X
X.
X
t
t
t
t
Output
QH
A ... H QA Qs
X
X
L
L
OAOOSO
a
H
L
L
OHO
b
h
OAn
OGn
OAn
OGn
GAOOSO
OHO
550
166
KS54HCTLS
KS74HCTLS
8-BitParallel-lnISerial-Out
Shift Registers with Clear
LOGIC DIAGRAM
PARAllEL INPUTS
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
I
-
CLK
CLK INH
LJ
SER - ~
SHILD
L~
JHh
A
L.
B
JHh
C
l
PAAALLEl
INPUTS
0
r;:;-h
E
l:
L
JHh
JHh
--,
OUTPUT Q H __ J
I
H
_I
....~-- SERIAL SHIFT - - -.....-~.
I
CLEAR
c8SAMSUNG
Electronics
I!HIBI~
lOAD
H
l
I_
r---
H
l
H
l
H
SERIAL S H I F T - - - -
'
551
KS54HCTLS
KS74HCTLS
166.···
8-Bit Parallel-lnISerial-Out
Shift Registers with Clear
Ab$olute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ....... -0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vce +0.5V) ......... ±~5 mA
Continuous Current Through
Vce or GND pins . . . . . . . . . . . . . . .. ± 125 mA
Storage Temperature Range, T5 1g .•• -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc .............. 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vcc
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=- 2OfJA
10=-4mA
Vce -0.1
3.84
Vec -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20fJA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vec or GND
±0.1
±1.0
±1.0
j.lA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
fJA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
.b.lee
VIN=Vee or GND
louT=OfJA
per input pin
VI=2.4V
other Inputs:
at Vec or GND
louT=OfJA
c8SAMSUNG
. Electronics
Vcc Vce -0.1
3.98
4.2
0
.552
KS54HCTLS
KS74HCTLS
166
.
8-Blt Paralle/;;'/nISerlal-Out
Shift Registers with Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r • tf~6 ns), HCTlS166
Ta =25°C
Vcc=5.0V
KS74HCTLS
KS54HCTLS
T. = -40°C to +85°C T. = -55°C to +125°C
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
I Maximum
Guaranteed Limits
40
30
25
20
MHz
22
30
37
45
ns
26
36
44
53
26
35
44
53
10
13
17
20
10
13
17
20
10
13
17
20
10
13
17
20
10
13
17
20
Data before SH/lDt
10
13
17
20
ClR Inactive
before ClK t
10
13
17
20
SH/lD High after ClKt
7
10
12
15
SER after ClKt
7
10
12
15
T.
10
12
15
7
10
12
15
7
10
12
15
fmax
Clock Frequency
Maximum Propagation Delay.
ClR to QH
tpHL
Maximum Propagation Delay.
ClK to QH
tpLH
r---tpHL
CL =50pF
----
ClR low
Minimum
Pulse Width ClK High or low
-
tw
Minimum
SH/lD High
Setup Time before ClKt
SER before ClKt
ClK INH before ClKt
tsu
ns
ns
ns
I
I
Minimum
Hold Time
ClK INH after ClKt
th
Data after SH/lDt
I
ClR Active after ClKt
fMaximum Input Capacitance
Power Dissipation Capacitance *
CIN
5
Cpo
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
553
I
KS54HCTLS
KS74HCTLS
16101169
01
Synchronous 4-Bit Up/Down
Decade and Binary Counters
FEATURES
DESCRIPTION
• Fully Synchronous Operation for Counting and Programming
• Internal Look Ahead for Fast Counting
• Carry Output for N-bit Cascading
• Fully Independent Clock Circuit
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Driv&-Current outputs:
10L =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These synchronous presettable counters feature an internal
carry look·ahead for cascading in high·speed counting ap·
plications. The '168 is a decade counter and the '169 is
a 4-bit binary counter. Synchronous operation is provided
by having all flip-flops clocked Simultaneously so that the
outputs change coincident with each other when so instructed by the count enable inputs and internal gating. This
mode of operation helps eliminate the output counting
spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four
flip-flops on the rising (positive-going) edge of the clock
waveform.
PIN CONFIGURATION
UfO
v""
ClK
RCO
A
OA
B
Os
C
Oc
D
00
ENP
ENT.
GND
lOAD
These counters are fully programmable; that is, the outputs may each be preset to either level. The load input circuitry allows loading with the carry-enable output of
cascaded counters. As loading is synchronous, setting up
a low level at the load input disables the counter and causes
the outputs to agree with the data inputs after the next clock
pulse.
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous application without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a carry output. Both count enable
inputs (ENP and ENT) must be low to count. The direction
of the count is determined by the level of the U/O input.
When ufo is high, the counter counts up; when low, it
counts down. Input ENT is fed forward to enable the carry
output. The ripple carry output (RCO) thus enabled will produce a low-level pulse while the count is zero (all inputs
low) counting down or maximum (9 or 15) counting up.
This low-level overflow carry pulse can be used to enable
successive cascaded stages. Transition at ENP or ENTare
allowed regardless of the level of the clock input.
These counters feature a fully independent clock circuit.
Changes at control inputs (ENP, ENT, LOAD, UfO) that will
modify the operating mode have no effe~t on the contents
of the counter until clocking occurs. The function of the
counter (whether enabled, disabled, loading, or counting)
will be dictated solely by the conditions meeting the stable
setup and hold times.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
c8SAMSUNG
Bectronics
554
KS54HCTLS
KS74HCTLS
1601169
01
Synchronous 4-Bit Up/Down
Decade and Binary Counters
LOGIC DIAGRAMS
'168
I
=8SAMSUNG
Electronics
555
KS54HCTLS
KS74HCTLS
168'1.6
.9
'I
Synchronous 4-Bit Up/Down
Decade and Binary Counters
LOGIC DIAGRAMS (Continued)
LOAD -,-(9-=-)_ __
B
'169
(4)
(12)
Oc
C (5)'
D (6)
'168
'169
LO~A:~~=
8~~=
DATA
INPUTS
C~~=
lo---lr=
UfO::: . :!
CLKV1i.r......
" __________~
ENPandENT-'L~~:~:
Oo::J
RCO---:'~~
--- : 7:: 8
9
I
0
I
21
• .'
2: 2 :
II-----COUNT UP-l,NHIBIT-1
-----
1
Uo
9
Load (preset) to BCD seven
Count up to eight nine (maximum), zero, one, and two
Inhibit
Count down to ohe, zero (minimum), nine, eight, and seven
=8SAMSUNG
Electronics
7
- - :13,: 14
I
I- COUNT DOWN-
LOAD
IIIstrated above is the following sequence:
1.
2.
3.
4.
8
,
RCO--:'~
15
i:
1
0
1
2:
U
,
2: 2i
I~COUNT UP--+-INHIBIT~
1
0
15 14
~COUNT
13
DOWN--
LOAD
Ilistrate~
above is the following sequence:
1. Load (preset) to BCD seven
2. Count up to eight nine (maximum), zero, one. and two
3. Inhibit
4. Count down to onl!. zero (minimum), nine. eight. and seven
556
KS54HCTLS
KS74HCTLS
1681169
~
Synchronous 4-Bit Up/Down
Decade and Binary Counters
FUNCTION TABLE
OUTPUTS
INPUTS
OPERATING MODE
ClK
UfD
ENP
ENT
lOAD
Dn
an
RCO
Parallel Load
t
t
X
X
X
X
X
X
I
i
i
h
L
H
(1 )
(1)
Count Up
t
h
I
I
h
X
Count Up
(1 )
Count Down
t
I
I
I
h
X
Count Down
(1)
Hold
t
t
X
X
h
X
X
h
h
h
X
X
qn
qn
(1 )
H
H = HIGH voltage level steady state
h=HIGH voltage level'one setup time prior to the LOW-to-HIGH clock transition
L=LOW voltage level steady state
I=LOW voltage level one setup time prior to the LOW-to-HIGH clock transition
X=Don't care
q=Lower case letters indicate the state of the referenced output prior to the LOW-to-HIGH clock transition
t';"LOW-to-HIGH clock transition
NOTE:
1. The RCO is LOW when ENT is LOW and the counter is at Terminal Count Terminal Count Up is (HHHH) and Terminal
Count Down is (LLLL) for '169.
The RCO is LOW when ENT is LOW and the counter is at Terminal Count. Terminal Count Up is (HLLH) and Terminal
Count Down is (LLLL) for '168.
Absolute Maximum Ratings*
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vec +0.5V)
±20 rnA
uC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 rnA
Continuous Current Through ,
Vce or GND pins
± 125 rnA
Storage Temperature Range, TsIg . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tl
Unused inputs must always be tied to an appropriate logiC
voltage level (either Vee or GND)
557
I
1681169
1/
KS54HCTLS
KS74HCTLS
Synchronous 4-BitUplDown
Decade and Binary Counters
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vce=5V±10% Unless Otherwise Specified)
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Ta=25°C
Symbol Test Conditions
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
ViN = VIH or VIL
10=-20",A
lo=-4mA
Vee -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20",A
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0:1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc·
8.0
80~0
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Ice
Vee Vee -0.1
3.98
4.2
0
VIN=VCC or GND
lOUT = O",A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
IOUT=O",A
AC ELECTRICAL CHARACTERISTICS
Conditions t
(Input tr , tf~6 ns), HCTLS168, HCTLS169
T.=25°C
Vcc=5.0V
KS74HCTLS
KS54HCTLS
T.=-40°Cto +85°C T.= -55°·C to +125°C
Vcc=5.0V:t 10%·
Vcc=5.0V:t 10%
Characteristic
Symbol
Maximum Operating Froguency
f max
35
30
25
20
Maximum Propagation Delay,
CLK to RCO
~
26
35
44
52
26
35
44
52
Maximum Propagation Delay,
CLK to Ary Q
-
tpLH
17
22
28
33
tpHL
17
22
28
33
Maximum Propagation Delay,
ENT to RCO
~
15
20
25
30
tPHL
15
20
25
30
Maximum Propagation Delay,
UfO to RCO
~
20
27
34
40
tPHL
20
27
34
40
tw
12
16
20
24
ns
A, B, Cor 0
12
16
20
24
ns
ENP or ENT
12
16
20
24
12
16
20
24
Typ
tpHL
Minimum Pulse Duration,
CLK high or low
I
Minimum
Setup Time
Before CLKt
tsu
LOAD
UfO
CL=50pF
Unit
Guaranteed Limits
MHz
ns
ns
ns
ns
II;:)
ns
12
16
20
24
ns
th
0
0
0
0
ns
Maximum Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
Minimum Hold Time,
Data after CLKt
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
pF
pF
fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
558
KS54HCTLS
KS74HCTLS
173
4-Bit D-Type Registers with 3-State Outputs
DESCRIPTION
FEATURES
.• Gated output control lines for enabling or disabling
the outputs
• Fully independent clock for operation in parallel-load
or hold modes
• For application as bus buffer registers
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10l = 24 rnA @ VOL = O.SV for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.SV
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +8SoC
KSS4HCTLS: -55°C to +12SoC
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 4-bit registers contain D-type flip-flops with 3-state outputs, capable of driving highly-capacitive or low-impedance
loads. This provides the device with the capability of being connected directly to and driving the bus lines in a busorganized system without need for interface or pull-up components.
Gated enable inputs are provided for controlling the entry
of data into the flip-flops. When both data-enable inputs
are low, data at the 0 inputs are loaded into their respective flip-flops on the next positive transition of the buffered
clock input. Gated output control inputs are also provided. When both are low, the normal logic states of the four
outputs are available for driving the loads or bus lines. The
outputs are disabled independently from the level of the
clock by a high logic level at either output control input.
The outputs then present a high impedance and neither
load nor drive the bus line. Detailed operation is given in
the function table.
To minimize the possibility that two outputs will attempt to
take a common bus to oPPosite logic levels, the output control circuitry is designed so that the average output dis?ble
times are shorter than the average output enable times.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vec and
ground.
FUNCTION TABLE
PIN CONFIGURATION
M
Vee
N
CLR
10
20
30
10
20
40
30
40
CLK
<32
GNO
61
Input
Clear
H
L
L
L
L
L
Clock
X
L
t
t
t
t
Output
Data Enable
Data
G1
G2
0
X
X
H
X
L
L
X
X
X
X
X
H
L
L
X
X
L
H
Q
L
00
00
00
L
H
I
When either Mor N (or both) is (are) high the output is disabled
to the high-impedance state; however sequential operation of the
flip-flops is not affected.
=8SAMSUNG
Electronics
559
I
KSS7544HHCCTTLLSS
K
17~J
1·~·4·Bit D-Type Registers
wifff3-State (j·utput'S:'~:·
LOGIC DIAGRAM
OUTPUT
CONTROL
f
l
M
(1)
N -(-2)~..J
DATA 1 0 ....:..(1....:..4)~_ _ _ _
DATA
ENABLE
JG1
+---r-......
>-------10
01
(9)
ClR
1
<32 (1 0)
(13)
DATA 2D----+---~---
>---+--+----1 0
. . . . . . . ._ _1 ......
ClK
Q
~--r-.. ~.--(4)_
02
ClR
>--1-+---1 0
(12)
DATA 3D----+-----1f--.......--r-.....
03
ClR
DATA 4D ...:(....;..11....:..)-f--.......~----I~
ClK
a "---1 >c:>--_(6_)-
04
ClR
\ .
c8SAMSUNG
Electronics
560
KS54HCTLS
KS74HCTLS
173
4-Sit D-Type Registers with 3-State Outputs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 rnA
Continuous Current Through
Vee or GND pins
±250 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional oparation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vce=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
KS74HCTLS
KS54HCTlS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
I
f-----.
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20!-,A
10= -6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20!-,A
10=12mA
10=24mA
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
!-,A
Maximum 3-State
Leakage Current
102
Output Enable
=VIH
VOUT=Vee or GND
±0.5
±5.0
±10.0
!-,A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
!-,A
2.7
2.9
3.0
Additional Worst
Case Supply
Current
t:..lee
VIN=Vee or GND
IOUT=O!-,A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
IOUT=O!-,A
c8 SAI\IISUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
I
mAl
561
KS54HCtLS' 17~
KS74HCTLS I,;} 4-Bit D-Type Registers with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Maximum Clock Frequency
f max
(Input tr , tf~6 ns), HCTlS173
KS74HCTLS
KS54HCTLS
T.=25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vee = 5.0V
Vee=5.0V±10%
Vee=5.0V± 10%
Condltlons t
Guaranteed Limits
Typ
45
30
25
20
CL=50pF
CL=150pF
20
23
27
30
34
39
41
47
CL=50pF
CL=150pF
r-----CL,=50pF
tpHL
CL =150pF
20
23
34
39
41
47
22
25
27
30
---c----30
33
37
42
45
51
CL=50pF
CL=150pF
18
21
25
28
37
43
CL=50pF
CL=150pF
18
21
25
28
31
36
31
36
15
20
25
30
15
20
25
30
10
13
17
20
10
13
17
20
15
20
25
30
8
11
tpLH
Maximum Propagation
Delay, ClK to any Q
Maximum Propagation
Delay, ClR to any Q
Maximum Output Enable
Time, M or N to any Q
tpHL
tPZH
r----- RL=1 kG
tPZL
Maximum Output Disable
Time, M or N to any Q
tpHZ
f--
RL = 1 kG, CL =50pF
tpLZ
ClK High
Minimum
or low
Pulse Width ClR High
tw
G1 and G2
Minimum
I---~~-----before ClKt Data
tsu
~~--
Minimum
Hold Time
After ClKt
---
-.-~---~------
<31 and <32
---.-
th
Data
~-
Maximum Input Capacitance
Maximum Output
Capacitance
r---Power Dissipation
Capacitance *
ns
ns
1----
--
ns
--
ns
37
43
14
17
-~-.-
ClR Inactive
MHz
5
7
8
10
a
a
0
0
0
0
0
0
ns
---
ns
~.~~~--~--
GOUT
~-
pF
5
CIN
Output Disabled
pF
10
- - - 1--------
-- - - ----_.-- ---_ .. - --_. -------
Cpo
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
ns
- ------
pF
2
fin.
562
KS54HCTLS 1;r~/1;r~
KS74HCTLS
'/
Hex/Quad O-type Flip-Flops
with Clear
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The'1 74 contains six, and the' 1 75 contains four D-type
flip-flops all sharing a common clock and a common clear.
The'1 74 features single rail outputs for every flip-flops
whereas the '175 has complementary outputs.
Information at the D inputs meeting the setup time requirements is transferred to the outputs on the positivegoing edge of the clock pulse. Clock triggering occurs at
a particular voltage level and is not directly related to the
transition time of the positive-going pulse. When the clock
input is at either the high or low level, the D input signal
has no effect at the output.
a
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
I
FUNCTION TABLE
PIN CONFIGURATIONS
'174
(Each Flip-Flop)
ern
Vee
10
60
10
60
20
50
20
50
3D
40
30
40
GNO
ClK
Inputs
Outputs
CLR
ClK
D
Q
ot
L
H
H
H
'X
X
H
l
X
L
H
L
H
l
H
00
00
t
t
l
t '175 only
'175
ClR
Vee
10
40
10
10
40
2D
2Q
30
20
30
GNP
ClK
40
3D
c8SAMSUNG
Electronics
II
563
KS54HCTLS
KS74HCTLS
17411·75
Hex/Quad tJ-type Flip-Flops
with Clear
LOGIC DIAGRAMS
'175
'174
(3)
a
0
10
(4)
(2)
10
a
0
10
CLOCK
CLOCK
CI.EAR·
CLEAR
a-
(4)
a
0
20
(5)
(5)
20
a
0
20
(2)
10
(3)
10
(7)
20
CLOCK
CLOCK
(6)
Ci
(6)
3D
a
0
20
CLEAR
CLEAR
(12)
(7)
30
3D
0
a
(10)
a
(11)
30
CLOCK
30
CLEAR
a
(11)
4D
0
(10)
40
CLOCK
a
40
(15)
40
CLK
(14)
0
CLEAR
40
CLEAR
CLR
(13)
50
(12)
Q
0
50
CLOCK
CLEAR
(14)
60
CLK
a
0
(15)
60
CLOCK
CLEAR
CLR
c8SAMSUNG
Electronics
564
KS54HCTLS 17~/17.5
KS74HCTLS I
j
Hex/Quad D-type FIi-Flops
with Clear
'/
Absolute Maximum Ratings*
Supply Voltage Range V e e , - 0 . 5 V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, IC)K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 rnA
Continuous Current Through
Vee or GND pins
± 125 rnA
Storage Temperature Range, T5tg . . . -6SoC to +1S0°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 6SoC to 8SoC
Recommended Operating Conditions
Supply Voltage, Vee
4.SV to S.SV
DC Input & Output Voltages *, VIN, Vour
OV to Vee
Operating Temperature
KS74HCTLS: -40°C to +8SoC
Range
KSS4HCTLS: -SsoC to +1_2SoC
Max SOO ns
Input Rise & Fall Times, t r , t,
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=SV±10% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2_0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vce -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
O.S
0.1
0.4
V
±0.1
±1.0
±1.0
J.lA
8.0
80.0
160.0
J.lA
2.7
2.9
3.0
rnA
f---
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20J.lA
lo=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20J.lA
10=4mA
10=8mA
Maximum Input
Current
liN
VIN=Vee or GND
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
t:.lee
VIN=Vee or GND
lour=OJ.lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour=OJ.lA
=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
--
565
I
Hex/Quad D-type Flip-Flops
with Clear
KS54HCTLS 1;r~/1;r~
KS74HCTLS
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input tr , tf~6 ns), HCTlS174, HCTlS175
KS74HCTLS
T,.=25°C
TA = -40°C to +85°C TA= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V:10%
Vcc=5.0V: 10%
Typ
Maximum Clock Frequency
Maximum Propagation Delay,
ClK to Q or Q
Maximum ProQagation Delay,
ClR to Q or Q
I
40
30
25
20
~
22
30
37
45
tPHL
22
30
37
35
~
26
35
43
tpHL
Data
Minimum Setup
Time before ClKt I ClR Inactive
tsu
Minimum Hold Time,
Data after ClKt
th
Minimum Pulse
Width
IClK High or low
Guaranteed Limits
f max
tw
IClR low
Maximum Input Capacitace
CIN
Power Dissipation Capacitance·
Cpo
CL=50pF
26
35
43
52
52
10
13
17
20
12
16
20
25
a
0
0
0
10
13
17
20
10
13
17
20
c8SAMSUNG
Electronics
--
ns
ns
ns
ns
pF
5
" Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
MHz
pF
fin.
566
KS54HCTLS
KS74HCTLS
181
Arithmetic Logic Unit/
Function Generator
FEATURES
DESCRIPTION
• Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus 12 other arithmetic operations
• logic function modes:
Exclusive-OR
Comparator
AND,NAND,OR,NOR
Plus 10 other logic operations
• Full look-ahead for high-speed operations
on long words
The '181 is an Arithmetic Logic Unit (ALU)lFunction
Generator that performs 16 binary arithmetic operations
on two 4-bit words as shown in table 1 and 2. These operations are selected by the four functions select lines (SO,
81,82,83) and include addition, subtraction,. decrement
and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a
low level voltage to the mode control input(M). A full carry
look-ahead scheme is made available in these devices for
fast, simultaneous carry generation by means of 2 cascadeoutputs (p and (3) for the 4-bits in the package. When used in conjunction with HCTL8182, high-speed arithmetic
operation can be performed. The typical addition times
shown in table below illustrates how little is required for
addition of longer words when full carry look-ahead is
employed.
• Function, pin-out, speed and drive compatibility with
54174lS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current Outputs:
IOL=8mA @ VOL=O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS:-55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
If high speed is not important, a ripple-carry input (C~) and
a ripple-carry output (C.+4) are available. However, the
ripple-carry delay has also been minimized so that arithmetic
manipulations for small lengths can be performed without
external circuitry.
The'1 81 will accommodate active-high or active-low data,
if the pin deSignations are interpreted as shown below.
8ubtraction is accomplished' by 1's complement addition
where the 1 's complement of the subtrahend is generated
internally. The resultant output is A-B-1 , which requires and
end-around or forced carry to provide A-8.
The '181 can also be utilized as a comparator. The A=8
output is internally decoded from the function outputs (FO,
, F1, F2, F3) so that when two words of the equal magnitude
are applied at the A and 8 inputs, it will assume a high level
to indicate equality (A=8). The ALU should be in the subtract mode with C.=H when performing the comparison.
The A=8 output is open-drain so that it can be wire-AND
connected to give a comparison for more than four bits.
The carry output (C n +4) can also be used to supply
relative magnitude information. Again, the ALU should be
placed in the subract mode by placing the function select
input 83, 82, 81, 80 at L,H,H,L respectively.
PIN CONFIGURATION
80
AO
S3
S2
S1
SO
c.
81
A2
82
A3
83
M
G
vee
1\1
1'0
1'1
F2
C.+4
P
A=B
J!3
GND
Pin number
2 .
1
23
22
21
20
19
18
9
10
11
13
7
16
15
17
Active-Low Data (Table1)
Ao
80
A1
81
A2
82
A3
83
Fa
F1
F2
F3
Cn
Cn +4
P
Active-High Data (Table 2) Ao
80
A1
81
A2
82
A3
83
Fa
F1
F2
F3
Cn
Cn +4
X
G
y
cRSAMSUNG
• • Electronics
II
These circuits have been d to not only incorporate all of
the designer'S requirements for arithmetic operations, but
also to provide 16 possible functions of two boolean
variables without the use of external circuitry. These logical
functions are selected by use of the four function select
inputs (80, 81,82, 83) with the mode control input (M)
at a high level to disable the internal carry.
The 16 logic functions are detailed in Tables 1 and 2 and
include exclusive-OR. NAND. AND. OR and NOR functions.
567
I
KS54HCTLS
KS74HCTLS
181
Arithmetic Logic Unitl
Function Generator
ALU SIGNAL DESIGNATION .
The '181 can be used with the signal designations.
The logic functions and arithmetc operations obtained with
signa/designations as in Tab/e 1.
These devices provide speeds and dri~e capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
LOGIC DIAGRAM
(3)
~~-,-(4.:.-)_ _....,
S1---....,
so
~
(16)
___.a.../----Cn+4
(15) j5
(13) F3
(11) _
F2
B1 (22)
(23)
A1
(10) F1
80(1)
(9) FO
AO (2)
'M
Cn
(7)
/'=8 SAMSUNG
Electronics
568
181
KS54HCTLS
KS74HCTLS
Arithmetic Logic Unitl
Function Generator
a Table 1
Actlv.Low Data
Selection
M = L; Arithmetic Operations
M=H
Logic
Functions
Cn=L
(no carry)
F=A
F=AS
F=A + B
F=1
F=A + B
F=B
F=A Minus 1
F=AB Minus 1,
F=AB Minus 1
F=Minus 1 (2's Comp)
F=A Plus (A + '9')
F=AB Plus (A + S)
F = A Minus B Minus 1
F:=A + B
F:=A Plus (A + 8)
F:=A Plus B
F=AB Plus (A + B)
F=(A + 8)
F=A Plus A*
F:=AB Plus A
F=AS Plus A
F=A
S3
S2
S1
SO
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H'
H
L
L
H
H
H
L
F:=~
H
L
L
H
H
H
H
L
L
H
H
H
H
F:=A + B
F=AB
F=A EE> B
F=B
F:=A + 8
F=O
F=AB
F=AB
F=A
H
H
H
ti
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
Cn=H
(with carry)
F=A
F=AB
F=AB'
F=Zero
F=A Plus (A + "9) Plus 1
F:=AB Plus (A + B) Plus 1
F=A Minus B
F:=(A + '9') Plus 1
F:=A Plus (A + B) Plus 1
F:=A Plus B Plus 1
F=AB Plus (A + B) Plus 1
F=(A + B) Plus 1
F:=A Plus A Plus 1
F=AB Plus A Plus 1
F:= AS Plus A Plus 1
F:=A Plus 1
a Table 2
M == L; Arithmetic Operations
M=H
Logic
Functions
S3
S2
S1
SO
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
L
L
H
H
H
L
F=~
H
L
L
L
F=AS
F==A + B
H
F:=~
L
F=B
F=AB
F=1
F=A + 8
F=A + B
F=A
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
I
Activ.High Data
Selection
L
L
L
H
H
H
L
L
H
H
H
H
L
L
F=A
F=A+""'S'
F=AB
F:=O
F=AS
F:=8
~n=L
(no carry)
F=A
F:=A + B
F==A + 8
F:=Minus 1 (2's Comp)
F=A Plus AS
F=(A + B) Plus AS
F == A Minus 8 Minus 1
F==AS Minus 1
F:=A Plus AB
F==A Plus B
F=(A + '9') Plus AB
F=AB Minus 1
F=A Plus A*
F=(A + B) Plus A
F=(A + S) Plus A
F=A Minus 1
'l:!n=H
(with carry)
F=A Plus 1
F=(A + B) Plus 1
F:=(A + B) Plus 1
F:=Zero
F:= A Plus AS Plus 1
F:=(A + B) Plus AS Plus 1
F=A Minus B
F:=AS
F:= A Plus AB Plus 1
F:=A Plus B Plus 1
F:=(A + '9') Plus AB Plus 1
F=AB
F:=A Plus A Plus 1
A:=(A + B) Plus A Plus 1
F:=(A + S) Plus A Plus 1
F:=A
* Each bit is shifted to the next more significant position
=8SAMSUNG
Electronics
569
KS5.4HCTLS
181
Arithmetic' Logic Unitl
KS74HCTLS
Function Generator
Absolute Maximum Ratings·
t Power Dissipation temperature d,erating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ..... . . -O.SV to + 7V
DC Input Diode Current, hK
(VI < -O.5V or VI > Vec +O.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
.
(Vo < -O.5V or Vo > Vcc +O.5V) .... ±20 mA
Continuous Output Clirrent Per Pin, 10
(,..-O.5V < Vo < Vcc +O.5V) .. , , ..... ±70 mA
Continuous Current Through
Vce or GND pins ................ ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt, ... ' .. 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages *, VIN, Your . . OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure ~o these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
Ta=25°C
Typ
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
lee
VIN=Vee or GND
10ur=0",A
8.0
80.0
160.0
/AA
Additional Worst
Case Supply
Current
per input in
VI=2.4V
.6. Icc other Inputs:
at Vee or GND
lour=O",A
2.7
2.9
3.0
mA
=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
570
KS54HCTLS
KS74HCTLS
181
Arithmetic Logic Unitl
Function Generator
INPUT PAIRS HIGH/NOT HIGH TEST TABLE
FUNCTION INPUTS: S2 = M = 4.5 V. so = S1 =' S3 = 0
INPUT
PARAMETER
UNDER
TEST
tpLH
Ai
OTHER INPUT
SAME BIT
APPLY 4.5 V
Bi
APPLY GND
None
tpHL
tpLH
Bi
Ai
None
tpHL
tpHL
Ai
Bi
None
tpHL
tPLH
Bi
AI
None
tpHL
v
OTHER DATA INPUTS
OUTPUT
OUTPUT"
UNDER
WAVEFORM
APPLY 4.5 V
APPLY GND
TEST
Remaining
Remaining
p
B
In-Phase
A. C n
Remaining
Remaining
p
In-Phase
C n +4
Out-ot-Phase
C n +4
Out-ot-Phase
B.
Cn
A
Remaining
Remaining
A. C n
B
Remaining
Remaining
B, C n
A
PARAMETER MEASUREMENT INFORMATION
SUM MODE TEST TABLE
FUNCTION INPUTS: SO=S3=4.5 V. S1 =S2=M=0 V
INPUT
PARAMETER
UNDER
TEST
tpLH
Ai
OTHER INPUT
SAME BIT
APPLY 4.5 V
Bi
APPLY GND
None
OTHER DATA INPUTS
APPLY 4.5 V
A and B
tpLH
Remaining
Bi
Ai
None
Ai
Bi
Bi
Ai
None
None
Ai
None
Bi
Bi
None
Ai
tpHL
tpLH
Cn
None
Ai
None
None
tpHL
tPLH
Bi
tPHL
tPLH
tpHL
Fi
In-Phase
Cn
Fi
In-Phase
Remaining
p
In-Phase
None
p
In-Phase
G
In-Phone
G
In-Phase
Remaining
-
-
A and B. C n
tpHL
tpLH
Cn
Ii: andB. C n
tPHL
tpLH
TEST
None
tpHL
tpLH
WAVEFORM
A and B
tpHL
tpLH
OUTPUT
UNDER
APPLY GND
Remaini,ng
tPHL
OUTPUT
Bi
None
Ai
Remaining
B
Remaining
B
Remaining
-
A,C n
Remaining
A,
Cn
All
All
Any F
A
B
or C n+4
Remaining
Remaining
B
A,C n
Remaining
Remaining
B
A.
Cn
In-Phase
Cn +4
Out-ot-Phase
Cn +4
Out-ot-Phase
571
I
KS54HCTLS
KS74HCTLS
181.
Arithmetic Logic Unitl
Function Generator
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons f
CL=50pF
i
KS74HCTLS
KS54HCTLS
T.=25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
~cc=5.0
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
14 18
M=OV
I--tPHl Sum or Diff Mode 14 18
23
27
23
27
Propagation Delay.
Cn +4
M=S1 =S2=OV
SO=S3=4.5V
20 28
35
42
I---
20 28
35
42
Propagation Delay.
Cn +4
1------
M=SO=S3=OV
S1 =S2=4.5V,
25 34
42
50
25 34
42
50
M=S1 =S2=OV
SO=S3=4.5V
22 31
39
47
22 31
39
47
M=SO=S3=OV
S1 =S2=4.5V
23 32
40
48
23 32
40
48
M=SO=S3=OV
S1 =S2=4.5V
25 34
43
51
25 34
43
51
M=S1 =S2=OV
SO=S3=4.5V
25 34
42
50
25 34
42
50
M=S1 =S2=OV
SO=S3=4.5V
25 34
42
50
25 34
42
50
M=SO=S3=OV
S1 =S2=4.5V
25 34
42
50
25 34
42
50
A or B to
Propagation Delay
A or B to IT
Propagation Delay
A or B to G
Propagation Delay
A or B to 15
Propagation Delay
A or B to P
i Propagation
Delay
A or B to Fi
Propagation Delay
A or g to Fi
tplH
tplH
tpHl
tplH
tpHl
tplH
r----tPHl
tplH
r----tpHl
tpLH
r----tpHL
tplH
r----tPHL
tplH
r----tPHL
tpLH
I---
tpHl
ns
ns
ns
ns
ns
ns
ns
ns
ns
~~----:-
-~~
iPropagation Delay
A or B to
A=B
~ropagation Delay
A or B to A=B
Propagation Delay
tplH
I---
M=4.5V
tpHL
20 29
35
42
20 28
35
42
tplH
M=SO=S3=OV
25 34
42
50
tpHl
S1 =S2=4.5V
25 34
42
50
20 28
35
42
20 28
35
42
I---
tplH
tpHl
i Input Capacitance
IPower Dissipation
CIN
I Capacitance *
Cpo
5
--ns
- - f-----
ns
----
f--------.
Cn to any F
Unit
Guaranteed Limits
Propagation Delay.
C n to Cn +4
A or B to
I
(Input tr • tfE;;6 ns), HCTLS181
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: PO=CPD Vee' fin~
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
572
KS54HCTLS
KS74HCTLS
181
Arithmetic Logic Unitl
Function Generator
PARAMETER MEASUREMENT INFORMATION
LOGIC MODE TEST TABtE
FUNCTION INPUTS: S1 =S2=M=4.5 V, SO=S3=0 V
INPUT
PARAMETER
UNDER
TEST
tpLH
Ai
OTHER INPUT
SAME BIT
APPLY 4.5 V
Bi
APPLY GND
None
OTHER DATA INPUTS
APPLY 4.5 V
Remaining
None
A and B.
tpHL
tpLH
Bi
Ai
None
APPLY GND
A and B.
OUTPUT
UNDER
WAVEFORM
TEST
Fi
Out·ot-Phase
Fi
Out-ot-Phase
Cn
Remaining
None
tpHL
OUTPUT
Cn
INPUT BITS EQUAUNOT EQUAL TEST TABLE
FUNCTION INPUTS: SO=S3=M=4.5 V, S1 =S2=0 V
INPUT
PARAMETER
UNDER
TEST
tpLH
Ai
OTHER INPUT
SAME BIT
APPLY 4.5 V
Bi
APPLY GND
None
tpHL
tpLH
Bi
Ai
None
Ai
None
Bi
tPHL
tPLH
Bi
None
Ai
Ai
Bi
None
tpHL
tpLH
tpHL
tpLH
Bi
Ai
None
Ai
None
Bi
tpHL
tpLH
Bi
None.
tpHL
c8SAMSUNG
Electronics
Remaining
A and B.
Remaining
Remaining
Ai
B.
A and B. C n
Remaining
Remaining
Remaining
APPLY GND
TEST
None
P
Out-ot-Phase
None
P
Out-ot-Phase
None
P
In-Phase
None
is
In-Phase
None
C n +4
In-Phase
None
Cn +4
In-Phase
None
C n +4
Out-ot-Phase
None
C n +4
Out-ot Phase
Cn
Remaining
A and B.
WAVEFORM
Cn
Aand B. C n
A and B.
OUTPUT
UNDER
Cn
Remaining
B.
OUTPUT
Cn
A and B. Cn
A and
tpHL
tpLH
APPLY 4.5 V
A and
tpHL
tplH
OTHER DATA INPUTS
Cn
573
I
KS54HCTLS
KS74HCTLS
181
Arithmetic Logic Unitl
Function ~enerBtor
DIFF MODE TEST TABLE
FUNCTION INPUTS: S1 S2 4.5 V,
= =
INPUT
PARAMETER
TEST
tpLH
OTHER INPUT
SAME BIT
UNDER
Ai
APPLY 4.5 V
None
APPLY GND
Si
tpHL
tPLH
8i
Ai
None
tpHL
tpLH
Ai
None
ei
so =S3 = M =0 v
OTHER DATA INPUTS
APPLY 4.5 V
APPLY GND
Remaining
Remaining·
A
e, C n
Remaining
Remaining
A
e, Cn
None
Si
Ai
None
None
Ai
Bi
None
None
Bi
None
Ai
None'
Ai
None
Bi
tpHL
tpLH
Si
Ai
None
tpHL
tpLH
Cn
None
None
tpHL
tpLH
Remaining
Remaining
Remaining
A
S, C n
Remaining
Remaining
A
S, C n
All
None
In-Phase
Fi
Out-ot-Phase
p
In·Phase
p
Out-ot-Phase
G
In-Phase
G
Out-ot-Phase
A=B
In-Phase'
A=B
Out-ot-Phase
Ai
Si
None
None
Bi
None
ai
None
Remaining
A,
'
In-Phase
Cn +4
Out-ot-Phase
C n +4
In-Phase
S, C n
Remaining
A, e, C n
c8SAMSUNG
C n +4
or any F
AandB
tPHL
Electronics
Remaining
Remaining
tpHL
tPLH
Fi
A and S, C n
tPHL
tPLH
TEST
A and e, C n
tpHL
tPLH
WAVEFORM
A and S, C n
tpHL
tpLH
OUTPUT
UNDER
A and S, C n
tpHL
tPLH
Remaining
OUTPUT
574
KS54HCTLS
KS74HCTLS
182
Look Ahead Carry Generator
FEATURES
DESCRIPTION
• Compatible Carry Functions for direct AlU connection
• Cascadable to perform look-ahead across n-bit
adders.
• High output current drive: IOL=8mA @ VOL=05V
• Low power consumption characteristic of CMOS
• Direct interface capability to TTL, NMOS and CMOS
devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
The '182 is a high-speed, look-ahead carry generator,
capable of anticipating a carry across four binary adders
or group of adders. These devices can be cascaded to
perform full look-ahead across n-bit adders. Carry,
generate-carry, and propagate-carry functions are provided
as shown in the pin designation table.
KS74AHC;T: - 40°C to + 85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
Carry input and output of the ALU's are in their true from,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, outputs, generate, and propagate) of the look-ahead
generators are implemented in the compatible forms for
direct connection to the ALU. Reinterpretations of carry
functions, as explained on the 1 81 data sheet are also applicable to and compatible with the look-ahead generator.
Positive logic equations for the 182 are:
PIN CONFIGURATION
131
Vee
P1
P2
GO
PO
Cn
When used in conjuction with the AHCT181 arithmetic logic
unit, these generators provide high-speed carry look-ahead
capability for any word length. Each 182 generates the
look-ahead (anticipated carry) across a group of four ALUs
and, in addition, other carry look-ahead circuits may be
employed to anticipate carry across sections of four lookahead packages up to n-bits. The method of cascading circuits to perform multi-level look-ahead is illustrated under
typical application data.
~2
Cn+x=GO + PO Cn
Cn+y=G1 + P1 GO + P1 PO Cn
Cn+z=G2 + P2 G1 + P2 P1 GO + P2 P1 PO Cn
G-G3 + P3 G2 + P2 G1 + P3 P2 P1 GO
P=P3 P2 P1 PO
G3
P3
P
GND
Cn + z
PIN DESIGNATIONS
Function
Designation
Pin No
GO,G1,G2,G3
3,1,14,5
PO,P1,P2,P3
4,2,15,6
Cn
13
Cn+x, Cn+y, Cn+z
12,11,9
G
10
Active Low Carry Generate Output
j5
7
Active Low Carry Propagae Output
Vec
16
Supply Voltage
GND
8
Ground
=8SAMSUNG
Electronics
Active Low Carry Generate Inputs
Active Low Carry Propagate Inputs
Carry Input, Active High
Carry Outputs
575
I
KS54HCTLS
KS74HCTLS
·182
Look Ahead ,Carty Generator
FUNCTION TABLES
LOGIC DIAGRAM
FOR GOUTPUT
INPUTS
<33
L
X
X
X
00
OUTPUT
P2
P1
G
X
X
X
X
X
L
X
X
L
X
X
L
X
L
L
X
X
L
L
L
All other combinations
X
L
X
I:.
L
G2
G1
P3
FOR P OUTPUT
INPUTS
9UTPUT
PO
P3 P2 P1
L
L L L
All other
combinations
X
L
(7)
~
L
H
FOR C n+ x OUTPUT
INPUTS
OUTPUT
P
GO
L
L
X
X
X
H
L
All other
combinations
H
PO
Cn
Cn+ x
H
H
L
Cn+y OUTPUT
OUTPUT
INPUTS
G1
L
X
X,
GO
P1
PO
Cn
Cn+ y
X
X
H
H
H
H
L
X
X
X
L
X
L
L
L
X
All other combinations
Cn+z OUTPUT
OUTPUT
INPUTS
G2
L
X
X
X
<31
GO
P2 P1
X
X X
X
X
L X
L
L
L
L
X
L
X
L
X
All other combinations
PO
Cn
Cn+z
X
X
X
L
X
X
X
H
H
H
H
H
L
H = high-level, L =.Iow level, X = dont' care
Any inputs not shown in a given table are don't care
witn respect to that output.
Figure; THE '182 IN A 64-BIT LOOK-AHEAD CARRY CIRCUIT
576
182
KS54HCTLS
KS74HCTLS
Look Ahead Carry Generator
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ..
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vcc +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) ......... ±35 rnA
Continuous Current Through
Vcc or GND pins
. .. ± 125 rnA
Storage Temperature Range, TSIg ... -.65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf ...
Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
Vil
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
hN
Maximum Quiescent
Supply Current
Icc
VIN=VIH or Vil
10=-20~A
10= -4mA
Vcc Vcc -0.1
4.2
3.98
VIN=VIH or Vil
Additional Worst
Case Supply
Current
10=4mA·
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=VCC or GND
±0.1
±1.0
±1.0
~A
8.0
80.0
160.0
~A
2.7
2.9
3.0
rnA
10=20~A
VIN=VCC or GND
10uT=0~A
Iper input pin
VI=2.4V
L'llcc lother Inputs:
/,at Vcc or GND
0
10uT=0~A
=8SAMSUNG
Electronics
577
I
KS54HCTLS 182
KS74HCTL.S ~:". ,
Look Ahead Carry Generator
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlonsl
(Input tr , t~6 ns), HCTLS182
T.=25 Q C
Vc c =5.0V
KS74HCTLS
T.= -40°C to +85°C
Vcc=5.0V±10%
Typ
Propagation Delay Pi or Gi to
Cn +x C n+y, Cn +z
tpLH
r - - - CL=50pF
tpHL
~opa.9.8tion_Delay
Pi or Gi to G
tpLH
r - - - CL =50pF
tpHL
Propagation Delay Cn to
Cn + x, Cn +y, Cn +z
~
tPLH
. tpLH
r--tpHL
Propagation Delay
PI to P
CL=50pF
tpHL
CL=50pF
KSS4HCLTS'
T.=-55°Cto +125°C
Unit
Vee = 5.0V ±. 10%
Guaranteed Limits
19
26
32
39
19
26
32
39
19
26
32
39
19
26
32
39
25
27
34
41
25
27
34
41
15
20
25
30
15
20
25
30
ns
ns
ns
ns
--.-~.
Capacita~~
5
C'N
Cpo
*CPD determines the no-load dynamic power diSSipation: PD=Cpo Vee l
tFor Acc switching .test circuits and timing waveforms see section 2.
Input
pF
pF
Power Disipation Capacitance *
c8SAMSUNG
Electronics
fin.
578
KS54HCTLS
KS74HCTLS
183
Dual Carry-Save Full Adders
FEATURES
DESCRIPTION
•
•
•
•
•
The '1 83 is a dual full adder features an individual carry
output from each bit for use in multiple-input, carry-save
techniques to produce the true sum and true carry outputs with no more than 2 gate delays.
For use in high-speed wallace-tree summing
Fast addition operation
Low power consumption characteristic of CMOS
High output current drive: IOL=8mA @ VOL=O.5V
Direct interface capability with TTL, NMOS and
CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
_
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
e-4~~~----+---'---'---+---,-----~
A.
Vrx;
He
B.
At,
C.
Cb
Coo
Coli
S.
He
GND
s..
e.,-
I
A
s
FUNCTION TABLE
(Each Half)
Output
Inputs
--
A
B
C
S
Co
L
H
L
L
L
H
L
H
L
H
H
L
L
L
H
L
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
H
H
H
H
L
H
H
L
H
=8SAMSUNG
Electronics
579
KS54HCTLS
KS74HCTLS
183
Dual Carry-Save Full Adders
Absolute Maximum Ratings*
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI> Vcc +0.5V) . . .. ±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-O.5V < Vo < Vcc +0.5V)
±35 rnA
Continuous Current Through
Vce or GND pins. .
±125 mA
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
* Absol\Jte Maximum Ratings are those values beyond
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vce
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTlS: - 55 0 C to + 1 25 ° C
Input Rise & Fall Times, tr , tf
.. Max 500 ns
which permanent damage to the device may (j)ccur.
These are stress ratings only and functional operation
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc==5V± 10% Unless Otherwise Specified)
T.=25°C
Symbol Test Conditions
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
. VIN=VIH or VIL
10=-20",A
VOH
10=-4mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Vcc Vcc -0.1
4.2
3:.98
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=4rnA
10=8mA
Maximum Input
Current
hN
VIN'""VCC or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
VIN=VCC or GND
lOUT == o",A
2.0
20.0
40.0
",A
~Icc
per input in
VI=2.4V
other Inputs:
at Vcc or GND
10UT=OJAA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
0
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tro t~6 ns), HCllS 183
KS54HCTLS
KS74HCTLS
Ta=25°C
Ta= -40°C to +85°C Ta= -55°C to +125°C
Vee=5.0V
Vce=5.0V:t: 10%
Vee = 5.0V:t: 10%
Typ
Propagation Delay
tpLH
~
tpHL
Input Capacitance
CIN
Power dissipation Capacitance *
CPD
CL =50pF
c8SAMSUNG
Electronics
Guaranteed Limits
15 22
27
33
17 23
29
35
* Cpo determines the no-load dynamic power dissipation: PD=CPO VCC 2
t For AC switching test circuits and timing waveforms see section 2.
Unit
ns
pF
pF
fin.
580
KS54HCTLS
KS74HCTLS
190
Synchronous 4·Bit Up/Down
Decade Counters
FEATURES
DESCRIPTION
• Single down/up count control line
• Look-ahead circuitry enhances speed of cascaded
counters
• Fully synchronous in count modes
• Asynchronously presettable witl'! load control
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These are high-speed synchronous reversible 4·bit decade
counters, Synchronous counting operation is provided by
having all flip-flops clocked simultaneously so that the outputs change with each other when so instructed by the
steering logic. This mode of operation eliminates the output counting spikes normally associated with a synchronous
(ripple clock) counters.
B
vcc
A
aA
ClK
Ci'EN
~
MAXIMIN
DIU
ac
WAD
aD
C
GND
D
FUNCTION TABLE
OPERATING MODE
parallel load
DID
Cffil
CLK
Input
L
X
X
X
X
X
X
l
H
count down
H
hold (do nothing)
H
On
l
H
X
l
I
t
count up
- - t---.~ 1---- t-------- - - H
t
X
count down
I
H
t------.
OUTPUTS
INPUTS
LOAJ)
l
count up
-~--
X
X
H
X
no change
~ AND MAXIMIN FUNCTION TABLE
INPUTS
TERMINAL COUNT STATE
DID
~
ClK
OA
H
l
l
l
H
H
H
H
l
H
H
l
X
H
H
H
l
l
l
X
Lf
X
X
Lf
Oa
X
X
Oc
OD
X
X
H
H
H
l
l
l
X
X
l
l
l
l
l
l
These counters feature a fully independent clock circuit.
Changes at the control inputs (CTEN and DIU) that will
modify the operating mode have no effect on the contents
of the counter until clocking occurs. The function of the
counter will be dictated solely by the condition meeting
the stable setup and hold times.
These counters are fully programmable; that is, the outputs may each be preset to either level by placing a low
on the load input and entering the desired data at the data
inputs. The output will change to agree with the data inputs independently of the level of the clock input. This
feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
PIN CONFIGURATION
as
The outputs of the four flip-flops are triggered on a low-tohigh-level transition of the clock input if the enable input
(CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the downlup
(DIU) input. When DIU is low, the counter counts up and
when DIU is high, it counts down.
OUTPUTS
MAX/MINrJiCO
l
H
I
L
H
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs arid outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
Lf
l
I
H
I Lf
H
L
Two outputs have been made available to perform the
cascading function: ripple clock and maximum/minimum
count. The latter output produces a high-Ie~el output pulse
with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (9 or 15) counting up. The ripple clock
output produces a lOW-level output pulse under those same
conditions but only while the clock output to the enable
input of the succeeding counter if parallel clocking is used,
or to the clock input if parallel enabling is used. The
maximumlminimum count output can be used to accomplish
look-ahead for high-speed operation.
H
H=
l =
I =
X =
t =
l..f =
HIGH voltage level
lOW voltage level
lOW voltage level one setup time prior to the lOW-to-HIGH ClK transition
Don't care
lOW-to-HIGH ClK transition
one lOW level pulse
L= MAXIMIN goes lOW ON A lOW-to-HIGH ClK transition
=8SAMSUNG
Electronics
581
I
19·0
KS54HCTLS
KS74HCTLS
LOGIC DIAGRAM
CTEN
DIU
ClK
~~:~----4-~+--rr+--~
L5A5
A ~~~-r~Pr+-~-+~----------~r+---r.~~--;-~
B --_+-I
C
D
Typical load, count, and inhibit sequences
'{O~,X-.
,
I
DATAI3~
:.:L..=
INPUTS
.•
'I'
cJ"T:L=
I
Ir-
:
I
, D-+f -
Sequence;
(1) Load (preset) to BCD seven.
(2) Count up to eight, mine(maximum)
zero, one, and two.
(3) Inhibit
(4) Count down to one, zero
(minimum), nine, egiht,
and seven
NOTE A: Clear overrides load data, and count inputs.
Note B:When count up, count·down input must be high;
when counting down, countup in\put must be high.
c8SAMSUNG
Electronics
582
KS54HCTLS
KS74HCTLS
190
Synchronous 4-Bit Up/Down
Decade Counters
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee. . . . . . . . -0.5V to + 7V
DC Input Diode Current. hK
(VI < -0.5V or VI > Vee +0.5V) ... " ±20 rnA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 rnA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 125 rnA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage. Vec .............. 4.5V to 5.5V
DC Input & Output Voltages" ,VIN. VOUT . . OV to Vec
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times. tr • tf ......... Max 500 ns
.. Absolute Maximum Ratings are those values beyond
whieh permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25·C
Symbol T.st Conditions
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8.
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Minimum High-Level
Output Voltage
VOH
VIN==VIH or VIL
1o--20,..A
1o=-4mA
MaximUm Low-Level
Output Voltage
VOl
VIN=VIH or VIL
10 = 20,..A
1o-4mA
1o-8mA
Maximum Input
Current
lIN
VIN=Vee or GND
±0.1
±1.0
±1.0
,..A
Maximum Quiescent
Supply Current
Icc
VIN=Vee or GND
lour-O,..A
8.0
80.0
160.0
,..A
Additional Worst
Case Supply
Current
per input in
VI=2.4V
Alec other Inputs:
at Vee or GND
lour==O,..A
2.7
2.9
3.0
mA
c8SAMSUNG
• Electronics
II
KS54HCTLS
KS74HCTLS
Ta= -40·C to +85·C Ta= -55·C to +125·C Unit
Vee Vee -0.1
4.2
3.98
0
583
I
KS5~HCTLS190
KS74HCTLS
Synchronous 4-Bit Up/Down
Decade Counters
AC ELECTRICAL CHARACTERISTICS
Symbol Condltlons t
Characteristic
(Iflput t r • t~6 ns). HCTLSI190
KSS4HCTLS
KS74HCTLS
T.=2S II C
T.= _40DC to +8S DC T. = -55°C to +125 DC
Unit
Vee S.OV
Vee=S.OV:t10%
Vee=S.OV:t 10%
=
Typ
Maximum Clock Frequency
Guaranteed Limits
f max
30
20
16
14
Maximum Propagation Delay.
LOAD to any Q
~
30
40
50
60
tpHL
30
40
50
60
Maximum Propagation Delay,
A,B,C, 0 to any Q
tpLH
r---tpHL
27
36
45
64
27
36
45
54
Maximum Propagation Delay,
CLK to RCO
I TpLH
tpHL
Maximum Propagation Delay,
CLK to any Q
~
tpHL
CL=50pF
17
22
28
33
17
22
28
33
23
30
37
45
23
30
37
45
Maximum Propagation Delay,
CLK to MAXIMIN
~
35
47
59
70
tpHL
35
47
59
70
Maximum Propagation Delay,
DIU to RCO
tpLH
r---tpHL
33
45
56
67
33
45
56 '
67
Maximum Propagation Delay,
DIU to MAXIMIN
tpLH
r---tpHL
25
33
41
50
25
33
41
50
~
25
33
41
50
25
33
41
50
Mmcimum Propagation Delay.
CTEN to ReO
tpHL
13
17
21
25
LOAD low
13
17
21
25
Data before LOADt
10
13
17
20
CTEN before CLKt
20
26
34
40
10
.13
17
20
15
20
25
30
1
3
5
5
a
a
0
0
0
0
0
0
Minimum
Pulse Width
CLK High or Low
Minimum
Setup Time
DIU before CLKt
tv,
tsu
LOAD Inactive
before CLKt
Minimum Hold
Time
Data after LOADt
CTEN after CLKt
th
DIU after CLKt
Maximum Input capacitarice
CIN
5
POwer Dissipation Capacitance *
Cpo
80
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
. Electronics
MHz
ns
ns
ns
ns
ns
ns
ns
ns
os
ns
pF
pF
fin.
584
191
KS54HCTLS
KS74HCTLS
Synchronous 4-Bit Up/Down
Binary Counters
FEATURES
DESCRIPTION
These are high-speed synchronous, reversible 4-bit binary
counters. Synchronous counting operation is provided by
having all flip-flops clocked simultaneously SO that the outputs change with each other when so instructed by the
steering logic. This mode of operation eliminates the output counting spikes normally associated with a synchronous
(ripple clock) counters.
• Single down/up count control line
• Look-ahead circuitry enhances speed of cascaded
counters
• Fully synchronous in count modes
• Asynchronously presettable with load control
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The outputs of the four flip-flops are triggered on a low-tohigh-level transition of the clock input if the enable input
(CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up
(D/U) input. When D/U is low, the counter counts up and
when D/U is high, it counts down_
These counters feature a fully independent clock circuit.
Changes at the control inputs (CTEN and D/U) that will
modify the operating mode have no effect on the contents
of the counter until clocking occurs. The function of the
counter will be dictated solely by the condition meeting
the stable setup and hold times.
PIN CONFIGURATION
B
These counters are fully programmable; that is, the outputs may each be preset to either level by placing a low
on the load input and entering the desired data at the data
inputs. The output will change to agree with the data inputs independently of the level of the clock input. This
feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
Vce
Qs
A
QA
ClK
Two outputs have been made available to perform the
cascading function: ripple clock and maximum/minimum
count. The latter output produces a high-level output pulse
with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (9 or 15) counting up. The ripple clock
output produces a low-level output pulse under those same
conditions but only while the clock output to the enable
input of the succeeding counter if parallel clocking is used,
or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish
look-ahead for high-speed operation.
Rro
CTEN
MAXIMIN
DIU
Qe
COA5
Qo
C
GND
0
FUNCTION TABLE
INPUTS
OPERATING MODE
parallel load
count up
OUTPUTS
LOAD
DID
CTEN
CLK
Input
l
l
X
X
X
X
X
X
l
H
H
On
l
H
L
I
t
X
count up
H
I
t
X
count down
-~
count down
These devices provide speeds and drive capability.
equivalent to their LSTIL counterparts and yet maintain
CMOS power leiJels. The input and output yoltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
.~
H
-~.--.-
hold (do nothing)
H
X
H
X
X
no change
ReO AND MAXIMIN FUNCTION TABLE
INPUTS
DIU
H
L
L
L
H
H
i CTEN
H
H
l
H
H
L
TERMINAL COUNT STATE
ClK
QA
08
X
X
H
H
H
l
L
L
X
X
U
X
X
U
!
!
I
I
X
L
L
L
I
I
I
I
i
OUTPUTS
Oc
00
IMAX/MIN!
.~
X
X
H
H
H
L
l
L
L
H
H
H
X
L
l
l
H =
l =
I =
X =
I
I
I
L
L
H
L
U
I
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
H
H
U
HIGH voltage level
LOW voltage level
LOW voltage level one setup time prior to the LOW-to-HIGH ClK transition
Don't care
t = lOW-lo-HIGH ClK IransitiOfl
u = one lOW level pulse
L = MAXIMIN goes lOW ON A lOW-to-HIGH ClK transition
=8SAMSUNG
Electronics
585
I
191
KS54HCTLS
KS74HCTLS
Synchronous 4~Bit Up/Down
Binary Counters
LOGIC DIAGRAM
(12)
(4)
CTEN
~M-~
(5)
DIU
ClK
MAX MIN
(14)
~
Ig
1
B
~ -~~
~
D
Lcr;- r-EL
ft) ..- ~iP 7L~
---l-~
r-....t
1
~
I
D
(9)
l
""
D
~tp
-
T
~~
---
C
~ r-EL
.--cP
)
'---
(13)
P
R->
I
I
1
Lc;- ~
~~
1
rL~
H
r-....t
-
""'-
I
I
J
~~;-c-fl
rL~
.....,.
~~ r::
L:D
I
J
J
Typical Load, Count, and Inhibit Sequence
lOAD~-----------------------------
DATA {:
INPUTS
:
ClK
DIU
CTEN
"""-----+----t-tl---' H
-113 1415
Ut--
0
1 2
COUNT UP
lOAD
c8SAMSUNGElectronics
2
I INHIBIT I
2 1
L -_ _ _ __
0 L 15 14 13
t- COUNT DOWN --I
Sequence:
(1) load (preset) to binary thirteen
(2) Count up to fourteen, fifteen, zero, one, and two
(3) Inhibit
(4) Count down to one, zero, fifteen, fourteen, and thirteen
KS54HCTLS
KS74HCTLS
191
Synchronous 4-Bit Up/Down
Binary Counters
Absolute Maximum Ratings*
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 rnA
Continuous Current Through
Vee or GND pins
± 125 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
4.5V to 5.5V
Supply Voltage, Vee
OV to Vee
DC Input & Output Voltages *, VIN, VOUT
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to thes~ conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions.
(Vee==5V± 1 0% Unless Otherwise Specified)
j
Ta=25°C
t--- ---.-----
-~
KS74HCTLS
Typ
Minimum High-Level
Input Voltage
--------~---
--- -
Maximum Low-Level
Input Voltage
Minimum High-Level
Output Voltage
-+--~--
2.0
- -
0.8
VOH
I---------+--~--j__---
Vee Vee -0.1
4.2
3.98
o
0.1
0.26
0.39
I--------_+_---+---~----_+_-+__'_----t__----
Additional Worst
Case Supply
Current
Icc
VIN=Vee or GND
_ 10.tJ..~""'_~~_
per input pin
VI=2.4V
boice other Inputs:
at Vee or GND
10UT=OJAA
c8SAMSUNG
Electronics
Vee -0.1
3.84
----
8.0
-------+---
0.1
0.33
0.5
----
±1.0
--------- ----
80.0
t - - - - - - - - - - - - - - - - - f-----
0.8
- r----- -------.----
--1---- - - - - - ------
±0.1
V
2.0
----~---
0.8
-~--.----_+_--+__-~... -t_~---.--------
VIN = VIH or VIL
Maximum Low-Level
10=20JAA
VOL
Output Voltage
10=4mA
1-----________+-______ 10=8mA
Maximum Input
Current
Maximum Quiescent
Supply Current
- ---- ..
- - t - - - - - - - - 1---
VIN==VIH or VIL
10==-20JAA
10= -4mA
KS54HCTLS
Guaranteed Limits
2.0
f-..:.--------'=-----+---
.1
Ta= -40°C to +85°CITa = -55°C to +125°C Unit
.. - - - - - - - ------------.---
.----~--
Vee -0.1
3.7
V
.
-
---
V
-- --1------
0.1
J~~--~--,:~-:~~---~-=~
r--~-----~-~--
2.7
2.9
3.0
rnA
587
I
KS54HCTLS
KS74HCTLS
t -,
191
Synchronous 4-Bit Up/Down.
Binary Counters
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r , tf~6 ns). HCTLS191
KS74HCTLS
KSS4HCTLS
T.=2SOC
T.= -40°C to +8S oC T. = -55°C to +12SoC
Symbol Conditions t Vee=S.OV
Vee = S.OV ± 10%
Vee=S.OV± 10%
Guaranteed Limits
TY9
Maximum Clock Frequency
f max
30
20
16
14
Maximum Propagation Delay,
lOAD to any Q
-
tPLH
30
40
50
60
tpHL
30
40
50
60
Maximum Propagation Delay,
A,B,C, 0 to any Q
-
27
36
45
64
27
36
45
54
Maximum Propagation Delay,
ClK to RCO
TpLH
-tpHL
17
22
28
33
17
22
28
33
Maximum Propagation Delay,
ClK to any Q
~
23
30
·37
45
tpHL
23
30
37
45
tPLH
35
47
59
70
tpHL
35
47
59
70
tpLH
33
45
56
67
tPHL
33
45
56
67
tpLH
25
33
41
50
tpHL
25
33
41
50
tpLH'
tpHL
Maximum Propagation Delay,
ClK to MAXIMIN
'--
Maximum Propagation Delay,
DID to RCO
f----------
Maximum Propagation Delay,
DID to MAXIMIN
~
Maximum Propagation Delay,
CTEN to RCO
~
tPHL
CL=50pF
25
33
41
50
25
33
41
50
13
17
21
25
13
17
21
25
20
Minimum
Pulse Width
ClK High or low
Data before lOADt
10
13
17
Minimum
Setup Time
CTEN before ClKt
20
26
34
40
10
13
17
20
15
20
25
30
lOAD low
DIU before ClKt
tw
!so
lOAD Inactive
before ClKt
Minimum Hold
Time
Data after lOADt
CTEN after ClKt
th
DIU after ClKt
1
3
5
5
0
0
0
-0
0
0
0
0
Maximum Input Capacitance
G,N
5
Power Dissipation Capacitance *
Gpo
80
* Cpo determines the no-load dynam •.:: power dissipation: PD=GpO VCC 2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
Unit
MHz
ns
ns
-,-
ns
ns
ns
ns
ns
ns
os
ns
pF
pF
fin.
588
KS54HCTLS
KS74HCTLS
192
Synchronous 4-Bit Up/Down
Decade Counters with Dual Clock
FEATURES
DESCRIPTION
• Look-ahead circuit enhances cascaded counters
• Fully synchronous in count modes
• Parallel asynchronous load for modulo-N count
lengths
• Asynchronous clear
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to S.SV
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & ~eel), standard DIPs.
These are high·speed synchronous reversible 4-bit decade
counters. Synchronous operation is provided by having all
flip· flops clocked simultaneously so that the outputs c}1ange
coinCidently with each other when so instructed by the
steering togic. This mode of operation eliminates the out·
put counting--spikes normally associated with asynchronous
(ripple clock) counters.
The outputs of the four flip-flops are triggered by a low-tohigh-level transition of either count (clock) input (Up or
Down). The direction of counting is determined by which
count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by plaCing a Iowan the
load input and entering the desired data at the data inputs.
The output will change to agree with the data inputs independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by Simply modifying the count length with the preset inputs.
A clear input has been provided that forces all outputs to
the low level when a high level is applied. The .clear function is independent of the count and the load inputs.
PIN CONFIGURATION
B
Vee
Os
OA
CLR
DOWN
UP
Oe
OD
GND
A
BO
CO
LOAD
C
D
These counters were designed to be cascaded without the
need for external circuitry. The borrow output (BO)
produces a lOW-level pulse while the count is zero (all outputs low) and the count-down input is low. Similarly, the
carry output (CO) produces a lOW-level pulse while the
count is maximum (9 or 15) and the count-up input is low.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count-down and countlip inputs, respectively, of the succeeding counter.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
statiC discharge by internal diode clamps to Vee and
ground.
:8SAMSUNG
Electronics
589
I
192
KS54HCTLS
KS74HCTLS
Synchronous 4-Bit Up/Down
Decade Counters with Dual Clock
LOGIC D1AGRAM
(12)
Co
Typical load, count, and Inhibit sequences
'{OADA~f=t =
,
I
I
"_
I
'r-
om o-I-::t=
rNPUTS.
c~L_
, o----+-f :
I
Sequence;
(1) Load (preset) to BCD seven.
(2) Count up to eight, mine(maximum)
zero, one, and two.
(3) Inhibit
(4) Count down to one, zero
(minimum), nine, egiht,
and seven
NOTE A: Clear overrides load data, and count inputs.
Note B:When count up, count-down input must be high;
M::t~======:===~===~n--,u~======
l ' i~:ou"' U:---+"HIBIT'-i ' I-----cOU",OOWN----j
when counting down, countup intput must be high.
~
=8 !!'ror!"SUNG
590
KS54HCTLS
KS74HCTLS
192
Synchronous 4-Bit Up/Down
Decade Counters with Dual Clock
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vcc, '" .... -0.5V to + 7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vcc +0.5V) . . .
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND. pins . . .
± 1 25 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vcc . . .
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf
* Absolute Maximum Ratings are. those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vce=5V± 10% Unless Otherwise Specified)
Ta=25°C
Typ
Minimum High-Level
Input Voltage
VIH
Maximum Low-Level
Input Voltage
VIL
Minimum High-Level
Outpvt Voltage
VOH
VIN=VIH or VIL
lo=-20/JA
lo=-4mA
Maximum Lo.w-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/J A
lo=4mA
10=8mA
Maximum Input
Current
liN
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
per input in
VI=2.4V
~Icc other Inputs:
at Vce or GND
10uT=0/JA
KS74HCTLS
KS54HCTLS
Ta=-400Cto +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=Vec or GND
±0.1
±l.b
±1.0
/J A
VIN=VCC or GND
louT=O/JA
8.0
80.0
160.0
/J A
2.7
2.9
3.0
mA
-
cRSAMSUNG
• • Electronics
Vcc Vee -0.1
4.2
3.98
0
591
I
KS54HCTLS~r192
KS74HCTLS
Synchronous 4-Sit"UpIDoJIIln
Decade Counters with Dual Clock
AC ELECTRICAL CHARACTERISTICS
(Input tr , tf~6 ns), HCTLS 192
KS54HCTLS
KS74HCTLS
T.=25°C T '= -400C to +8S o C T = -55°C to +125°C
Unit
Symbol Condltlonst V =5.0V •
• Vcc=5.0V~ 10%
cc
Vcc=5.0V~10%
Characteristic
Typ
Maxim~
Propagation Delay,
. UP to CO
Maximum Propagation Delay,
DOWN to BO
Maximum Propagation Delay,
UP or DOWN to any
a
Guaranteed Limits
fmax
35
25
20
18
tpLH
r--tPHL
18
25
31
37
18
25
31
37
18
tpLH
r--tpHL CL=50pF 18
24
30
36
24
30
36
Maximum Clock Frequency
I
TpLH
tpHL
32
42
52
63
32
42
52
63
MHz
ns
ns
ns
Maximum Propagation Delay,
LOAD to any
~
30
40
50
60
tpHL
30
40
50
60
Maximum Propagation Delay,
CLR to any
tPHL
18
24
30
36
10
13
17
20
tw
10
13
17
20
10
13
17
20
Data before LOADt
10
13
17
20
CLR Inactive before
uPt or DOWNt
10
13
17
20
ns
20
ns·
a
a
CLR High
Minimum Pulse LOAD Low
Width
UP or DOWN High
or Low
Minimum Setup LOAD Inactive before
Width
uPt or DOWNt
10
13
17
UP high before
DOWNt
10
13
17
20
DOWN high before uPt
10
13
17
20
1
C
3
5
5
0
0
0
0
0
0
0
Minimum Hold
Time
tsu
Data after LOADt
UP High after DOWNt
th
DOWN High after uPt
Maximum Input Capacitance
Power Dissipation Capacitance"
. CIN
5
Cpo
80
ns
ns
ns
....
--
ns
.-
pF
1----.-
pF
.. Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fjn.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronic~
592
KS54HCTLS
KS74HCTLS
193
Synchronous 4-Bit Up/Down
Binary Counters with Dual Clock
FEATURES
DESCRIPTION
• Look-ahead circuitry enhances cascaded counters
• Fully synchronous in count modes
• Parallel asynchronous load for modulo-N count
lengths
• Asynchronous clear
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These are high-speed synchronous reversible 4-bit binary
counters. Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the outputs change
coinCidently with each other when so instructed by the
steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous
(ripple clock) counters.
The outputs of the four flip-flops are triggered by a low-tohigh-level transition of either count (clock) input (Up or
Down). The direction of counting is determined by which
count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by placing a Iowan the
load input and entering the desired data at the data inputs.
The output will change to agree with the data inputs independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by Simply modifying the count length with the preset inputs.
A clear input has been provided that forces all outputs to
the low level when a high level is applied. The clear function is independent of the count and the load inputs.
PIN CONFIGURATION
B
These counters were designed to be cascaded without the
need for external circuitry. The borrow output (80)
produces a low-level pulse while the count is zero (all outputs low) and the count-down input is low. Similarly, the
carry output (CO) produces a lOW-level pulse while the
count is maximum (9 or 15) and the count-up input is low.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count-down and countup inputs, respectively, of the succeeding counter.
Vee
Os
A
OA
CLR
SO
CO
LOAD
DOWN
UP
Oe
OD
C
GND
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
D
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
OUTPUTS
INPUTS
OPERATING MODE
CLR
LOAD
UP
DOWN
A
8
C
D
QA
Qs
Qc
QD
CO
80
reset (clear)
H
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
L
H
parailel load
L
L
L
L
L
L
L
L
X
X
L
H
L
H
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
H
L
H
L
H
H
H
X
count up
L
H
t
H
X
X
X
count down
L
H
H
t
X
X
X
H = HIGH voltage level
L= LOW voltage love I
X= don't care
H*
H
H
H* *
t= LOW-to-HIGH clock transition
* CO = UP at terminal count up (HHHH)
* * aO = DOWN at terminal count down (LLLL)
c8·sAMSUNG
Electronics
count up
COUAt down
593
I
SynchronoUs: 4-Sit up/Down
Counters with Dua1- Clock
Sina~y
LOGIC DIAGRAM
~
(13)
CLR (~
~)
(5)
UP
(4)
DOWN
U5Ao
'1illct>
A
lU
-
(15)
~
.~
:t.>~~ o.
HI>
FU
r:
,- -
FU
~
~
I
1'- .
FU
-
~
y
n
~~
""
~
(9)
~~
"'"
~
(10)
o
~ ~
l~
~
~
(1)
B
c
~
-~~~~
- ~ rL.~
_
9
LeI>,
a.
Oc
00
"
CO
T,yplcal Clear, Load, and Count Sequences
CUI
L'OAO ---li-+-...,
r---------------
r++--+--- - - - - - - - - - - - - - - - - - - -
COUNT _
++-+-+-..,
UP
c~:--~~~~-------4-~
OO--~-++-4---..., r--~~------~
....--
('tClMroutpuillo lIfO.
12,LOod_'"
--._.
up towteen ......... ceny.
_....... . ----.. . . ---.-.. -1:.--.
NIO. one, ....
_A:~ ______
. two.
10 1
~31
,---....~
I
I I 1 0 15 14 131
r-- COUNT UP --1 t-- COUNT DOWN ---1
14
15
0
CLEAR PREseT
=8SAMSUNG
Electronics
1
2
131 Count
10
(41 Count down 10
one, zero. ttortow, MMn......... 1M 1I*teIn.
594
193
KS54HCTLS
KS74HCTLS
Synchronous 4-Bit Up/Down
Binary Counters with Dual Clock
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, ilK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current ThrolJgh
Vee or GND pins
± 125 mA
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt. .
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
..... Max 500 ns
Input Rise & Fall Times, tr , tf
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4·
V
±0.1
±1.0
±1.0
J.(A
8.0
80.0
160.0
JAA
2.7
2.9
3.0
mA
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20J.(A
10=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20J.(A
lo=4mA
lo=8mA
Maximum Input
Current
liN
VIN=Vec or GND
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
~Icc
VIN=Vce or GND
10uT=0J.(A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
IOUT=O/AA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
I
595
I
:·+l93
KS74HCTLS
Synchronous 4-Bit Up/Down
Binary Counters with Dual Clock
AC ELECTRICAL CHARACTERISTICS
(Input tr , tf~6 ns), HCTLS193
KS54HCT~S
Characteristic
Symbol Condltions t
T.=250~
Vcc=5.0
KS54HCTLS
KS74HCTLS '
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Guaranteed Limits
f max
35
25
20
18
Maximum Propagation Delay,
UP to Co
tpLH
r----tpHL
18
25
31
37
18
25
31
37
Maximum Propagation Delay,
DOWN to 80
~
Maximum' Propagation Delay,
UP or DOWN to any Q
r----------
Maximum Propagation Delay,
LOAD to any Q
f---
Maximum Propagation Delay,
CLR to any Q
Maximum Clock Frequency
MHz
ns
18
24
30
36
24
30
36
TpLH
CL=50pF 18
32,
42
52
63
tpHL
32
42
52
63
tpLH
30
40
50
60
tpHL
30
40
50
60
tpHL
18
24
30
36
10
13
17
20
10
13
17
20
10
13
17
20
Data before L.OADt
10
13
17
20
CLR Inactive before
uPt or DOWNt
10
13
17
20
ns
10
13
17
20
ns
UP high before
DOWNt
10
13
17
20
DOWN high before uPt
10
13
17
20
Minimum Hold. Data after LOADt
Time
UP High after DOWNt
1
3
5
5
0
0
0
0
0
0
0
0
tpHL
CLR High
Minimum Pulse LOAD Low
Width
UP or DOWN High
or Low
Minimum Setup LOAD Inactive before
Width
uPt or DOWNt
tw
tsu
th
ns
ns
ns
ns
ns
ns
-~
DOWN High after uPt
Maximum Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
80
pF
* CPD determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
596
KS54HCTLS
KS74HCTLS
194
4-Bit Bidirectional
Universal·Shift Registers
FEATURES
DESCRIPTION
•
•
•
•
•
•
These bidirectional shift registers feature parallel outputs,
right-shift and left· shift serial inputs, operating-mode·control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation:
•
•
•
•
•
•
Parallel-to-Serial, Serial-to-Parallel Conversions
Left or Right Shifts
Parallel Synchronous Loading
Direct Overriding Clear
Temporary Data Latching Capability
Function, pin-out, speed and drive compatibility with
54174LS logic family
Low power consumption characteristic of CMOS
High-Drive-Current outputs:
.
IOl =8 mA @ VOL =0.5V
Inputs and outputs interface directly with TTL, N.MOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
-
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs,
SO and S1, high. The data is loaded into the associated
flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow
is inhibited.
Shift-right is accomplished synchronously with the rising
edge of the clock pulse when SO is high and S 1 is low.
Serial data for this mode is entered at the shift-right data
input. When SO is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial
inputs. Clocking of the flip-flop is inhibited when both mode
control inputs are low.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
ClR
SR SER
A
Vee
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
OA
Os
B
Oe
C
D
00
Inhibit clock (temporary data latch/do nothing)
Shift·right (in the direction OA toward OD)
Shift-left (in the direction OD toward QAI
Parallel (broadside) load
qLK
51
SO
FUNCTION TABLE
INPUTS
CLR
MODE
L
H
H
H
H
H
H
H
X
X
H
L
L
H
H
L
SERIAL
PARALLEL
LEFT RIGHT
A B C D
CLK
S1 SO
X
X
X
H
H
H
L
L
L
L
t
t
t
t
t
X
OUTPUTS
X
X
X
X
X
H
L
X
=8SAMSUNG
Electronics
X
X
X
H
L
X
X
X
X X X X
X X X X
a
X
X
X
b c
d
X X X
X X X
X X X
X X X X
X X X X
QA
QB
Qc
QD
L
OAO
a
H
L
OSn
OSn
OAO
L
OSO
b
OAn
OAn
OCn
OCn
OSO
L
OCO
c
OSn
OSn
ODn
ODn
OCO
L
ODD
d
OCn
OCn
H
L
ODD
H=high level (steady state)
L = low level (steady state)
X=irrelevant (any input, including transitions)
t = transition from low to high level
a,b,c,d=the level of steady-state input at
inputs, A,B,C, or D, respectively.
OAO, OSO, OCO, ODo=the level of OA,
Os, Qc, or OD, respectively, before
the indicated steady-state input conditions were established.
OAn, OSn, OCn, OOn=the level of OA,
Os, Oc, respectively, before the mostrecent t transition of the clock.
597
I
KS54HCTLS
KS74HCTLS
1,94
4~Bit Bidirectional
Universal Shift Registers
LOGIC DIAGRAM
(positive logic)
PARALLEL IN~UTS
MODE {
CONTROL
INPUTS
SI
so -,,9"'-l1><>~--+--HH+----ff----t---t-t-rl-~+----+--t+~-rl----+---tlh+----,
SHIFT
SHIFT
.--I1-H-_--l....!:(7:..!.) LEFT
SERIAL
INPUT
S~~': ...:(~2)'--_ _ _ _d
INPUT
CLK~(~lf~)~~------~~---~------~----+--__-~____
r-____~
CDA~(~I)~~_ _ _ _ _ _ _ _- 4_ _ _ _ _~~_ _ _~_____~~_ _ _ _~____-+~
______~
(12)
a,
Q,
ac
aD
PARALLEL OUTPUTS
typical clear, load, right-shift, inhibit, and clear sequences
MODE
CONTROL
INPUTS
SERIAL {
DATA
INPUTS
PARALLEL {
DATA
INPUTS
I
I
I
SI
:::r-'lL..-;-'_______~
R
L_...,...-io-_"'-_ _ _ _ _ _ _-"-......,,.....
:_~ .;. .; ~. :_. :. . .
_ _ _ _ _. . ; - . , . . . _ - - - - - - - - - - ' - -
:
Cn--..:.-----.....;.---:--i--------:--------:-OIL I
I I
I----
CLEAR LOAD
cRSAMSUNG
• ., Electronics
_
SHIFT RIGHT---\
~SHIFT LEFT---t----INHIBIT---I
CLEAR
598
I~
KS54HCTLS
KS74HCTLS
194
4-Bit Bidirectional
Universal Shift Registers
Absolute Maximum Ratings*
Supply Voltage Range Vcc,
-O.5V to + 7V
DC Input Diode Current, hK
(VI < -O.5V or VI > Vcc +O.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -O.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
* Absolute Maximum R·atings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V±10% Unless Otherwise Specified)
Ta=25°C
Test Oonditions
Guaranteed limits
Typ
Minimum High-Level
Input Voltage
VIH
Maximum Low-Level
Input Voltage
VIL
0.8
0.'8
V
Vcc -0.1
3.84
Vcc -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±O.1
±1.0'
±1.0
/lA
160.0
/lA
3.0
mA
0.8
VOH
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O /lA
lo=4mA
10=8mA
Maximum Input
Current
liN
VIN=VCC or GND
Maximum Quiescent
Supply Current
Icc
r---.
Vcc Vcc -0.1
4.2
3.98
0
--t--o
- - - - -
VIN=VCC or GND
louT=O/lA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
louT=O/lA
~_.-
Worst
Supply
Current
V
2.0
- - r-----
VIN=VIH or VIL
10=-20/lA
10=-4mA
lease
2.0
2.0
Minimum High-Level
Output Voltage
I Additional
KS54HCTlS
KS74HCTlS
Ta = -40°C to +85°C Ta = - 55°C to +125°_~ Unit
.6.lcc
.-~----------
cRSAMSUNG
• • Electronics
8.0
.....
-
80.0
...
-~------.--
2.7
2.9
599
I
KS54HCTLS
KS74HCTLS
1't:l4
a
4-Bit Bidirectional
Universal Shift Registers
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions 1
(Input tr ,
Ta =25°C
Vcc=5.0V
tf~6 ns), HCTlS194
KS74HCTLS
T. == -40°C to + 85°C
Vcc=5.0V:10%
Typ
Maximum Clock Frequency
Maximum Propagation Delay,
ClK to QH
Maximum Propagation Delay,
ClR to QH
Minimum
Pulse Width
I ClR
I ClK
f max
tpLH
r--tpHL
CL=50pF
tpHL
to low
tw
High or low
Minimum Setup Time,
Any Input before ClKt
ts
KS54HCTLS
Ta= -55°C to +125°C
Vcc=5.0V: 10%
Unit
Guaranteed limits
40 30
25
20
18 24
30
36
MHz
18 24
30
36
21 28
35
42
12 16
20
24
12 16
20
24
10 17
20
20
ns
0
0
ns
ns
ns
ns
-~~
Minimum Hold Time,
Data after ClKt
ts
0
,0
--~
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
5
pF
pF
* Cpo determines the no-load dynamic power dissipation: PD=CPD VCC 2 fin,
t For AC switching test circuits and timing waveforms see section 2.
-c8SAMSUNG
'.
Electronics
600
KS54HCTLS
KS74HCTLS
195
4-Bit Bidirectional
Universal Shift Registers
FEATURES
DESCRIPTION
• Para"el-tOoSerial, Serial-tOoPara"el Conversions
• Parallel Synchronous Loading
• J and K Inputs to First Stage
• Right-shift Only with Complementary Outputs on Last
Stage
• Direct Overriding Clear
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and·
military temperature ranges:
KS74HCTlS: -40°C to +85°C
KS54HCTlS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 4-bit registers feature parallel inputs, parallel outputs.
J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation:
Parallel (broadside) load
Shift (in the direction AA toward OD)
Parallel loading is accomplished by applying the four bits
of data and taking the shift/load control input low. The data
is loaded into the associate flip-flops and appears at the
outputs after the positive transition of the clock input. During
loading serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load
control input is high. SEl,J)al data for this mode is entered
at the J-K inputs. These inputs permit the first stage to perform as a J-R, 0-, or T-type flip-flop as shown in the function table.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
CLR
Vee
J
Q.
K
QB
A
Qc
B
C
D
Qo
Co
I
CLK
GND
SH/[5
FUNCTION TABLE
----
CLR
SHIFT/LOAD
INPUTS
L
X
X
L
H
H
t
L
t
t
t
t
H
H
H
H
H
H
PARALLEL
1-------
I--~----
=8SAMSUNG
Electronics
~--.~-
SERIAL
CLK
H
H
H
OUTPOUTS
.~
J
K
X
X
X
X
X
X
H
L
L
H
H
L
H
L
OA
08 Oc
ABC D
X
a
X
X
X
X
X
X
b
X
X
X
X
X
X
c
X
X
X
X
X
X
d
X
X
X
X
X
L
L
L
a
b
c
OAO OBO OCO
OAO OAO OBn
L OAn OBn
H OAn OBn
QAn OAn OBn
00 00
L
H
d
d
000 000
Oen
OCn
Oen
Ocn
aCn
aCn
CCn
aCn
H=high level (steady state)
L=low level (steady state)
X=irrelevant (any input, including transitions)
t = transition from low to high level
a,b;c.d=the level of steady-state input at
A,B,C. or 0, respectively.
OAO. OBO. OCO. Ooo=the level of OA.
OB. Oc. or OD, respectively, before
the indicated steady-state input conditions were established.
OAn, OBn, OCn=the level of OA, OB or Oc.
respectively. before the mostrecent
transition of the clock.
601
4-81t Bidirectional
Universal Shift Registers
LOGIC DIAGRAM
SERIAL INPUT
PARALLEL INPUTS
~
J
(2)
K
(3)
C
B
A
D
(6)
(5)
(4)
(7)
SHIFTI
LOAD (~9~) ~~-+--+-~~------~~----------~r---------~
CONTROL
ClK
(10)
ClA~(~l)----~~--~-+--+---~--~+--+--~r-~-r--r---~--ri--i---1
(11)
~---------------y---------------------~
PARALLEL OUTPUTS
typical clear, shift, and load sequences
CLK
,
,
J
SERIAL {
-~---'~
~L-----------":"'--7----------
INPUTS
K
SHIFT/LOAD
-------------------,l..:.......Jr....;.---------
PARALLEL
IN~~~~
i
A _ _ _ _ _ _....;._ _ _ _ _ _ _ _ _ _ _ _ _~~--------------B
L
:
FHT'L---:-----------
C
D
L
( O':::l
I
~-------
OR : ; : .,
...
~ ------;.'----"
OUTPUTS
~---------~
{ Oc:::.,
Oo:::.,...__________________
I
I
CLEAR
c8SAMSUNOElectronics
~
·~---SERIAL SHIFT
1-01
,
----1
I'----SERIAL SHIFT - -
LOAD
602
KS54HCTLS
KS74HCTLS
195
4-Bit Bidirectional
Universal Shift Registers
Absolute Maximum Ratings·
Supply Voltage Range Vcc.
-0.5V to +7V
DC Input Diode Current. 11K
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package. Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vcc
4.5V to 5.5V
DC Input & Output Voltages·. VIN. VOUT
OV to Vce
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C~ +125°C
Input Rise & Fall Times. tr • tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V±10% Unless Otherwise Specified)
KS74HCTLS
KS54HCTLS
Ta =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Ta=25°C
Symbol Test Conditions
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vcc -0.1
3.84
Vcc -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
I-/A
80.0
160.0
I-/A
Minimum High-Level
Outp.ut Voltage
VOH
VIN=VIH or VIL
10=-20I-/A
10= -4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
.10= 2OI-/A
10=4mA
10=8mA
Maximum Input
Current
liN
VIN=Vec or GND
Maximum Quiescent
Supply Current
Icc
-
Additional Worst
Case Supply
Current
~Icc
VIN=VCC or GND
10UT=01-/A
....
per input pin
VI=2.4V
other Inputs:
at Vce or GND
IOUT-OI-/A
--
c8SAMSUNG
Electronics
-
Vcc Vcc -0.1
4.2
3.98
0
8.0
---
-.
-
2.7
-
---
-.
2.9
3.0
mA
603
I
KS54HCTLS
KS74HCTLS
195
4-Bit Bidirectional
Universal Shift Registers
AC ELECTRICAL CHARACTERISTICS
Symbol Conditions t
Characteristic
(Input t r , tf~6 ns), HCTLS195 .
KS74HCTLS
Ta=25°C
Ta= -40°C to +85°C
Vcc=5.0V
Vcc=5.0V:t10%
Typ
Maximum Clock Frequency
Maximum Propagation Delay,
CLK to QH
-
Maximum Propagation Delay,
CLR to QH
Maximum
Pulse Width
CLR Low
CLK High or Low
Minimum
Setup Time
before CLKt
SH/LD High
Minimum
Hold Time
after CLKt
Serial or Parallel
SH/LD High
Unit
Guaranteed Limits
f max
50 30
25
20
MHz
tpLH
18 24
30
36
ns
18 24
30
36
ns
21
35
42
ns
10 12
15
20
12 16
20
24
15 20
25
25
12 15
20
24
15 20
25
25
tpHL
tpHL
tw
tsu
CLR inactive
Serial or Parallel
Data
KS54HCTLS
Ta= -55°C to +125°C
Vcc=5.0V:t 10%
CL=50pF
th
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
-
28
0
0
0
0
0
0
5
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2. I
c8SAMSUNG
Electronics
604
KS54HCTLS
KS74HCTLS
210
Octal Buffers and Line Drivers
with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =24mA @ VOL .. O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "smlill outline" packages
(Available Tape & Reel), standard DIPs.
These high-speed octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direcfinterface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
LOGIC DIAGRAM
1<3
Vee
lAl
2G
2)14
lVl
lA2
2A4
2V3
lV2
lA3
2A3
2V2
1Y3
lA4
2A2
2Yl
1Y4
GND
2Al
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vec and
ground.
(18)
(16)
{'h
_
lY2
I
(14) "V3
(12)
_
lY4
2G
(9)
2Al
(7)
2A2
(5)
2A3
(3)
2Yl
2Y2
2~3
2Y4
FUNCTION TABLE
Input
G
L
L
H
A
L
Output
Y
H
H
L
X
Z
c8SAMSUNG
Electronics
605
Octal Buffers 'and Line Drivers
~ith 3-State Outputs
KS54HCTLS210
KS74HCTLS .......
,1
.
Absolute Maximum Ratings·
Supply Voltage Range Vee, . .
-0.5V to + 7V
DC Input Diode Current, 11K
(VI <-0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu"rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vec or GND pins
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°·C
Power Dissipation Per Package, Pdt
500 mW
t power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vec
Operating Temperature
-Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +1'25°C
Max 500 ns
Input Rise & Fall Times, tr , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logiC
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vce=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
Minimum High-Level
Input Voltage
Maximum Low-Level
Input Voltage
Guaranteed Limits
2.0
VIH
KS74HCTlS
KS54HCTlS
Unit
Ta = -40°C to +85°C
Ta = -55°C to +125°C
. --
2.0
2.0
._-
0.8
VIL
0.8
0.8
--~
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20/iA
lo=-6mA
Maximum Low-Level
Output Voltage
VOL
VIN = VIH or VIL
10= 2O/iA
lo=12.mA
10=24mA
Vce Vee -0.1
4.2
3.98
0
V
--~~~----~-.-
V
..
f---
Vee -0.1
3.84
Vee -0.1
3.7
0.1 I
0.26
0.39
0.1
0.33
0.5
0.1
0.4
----
_- J.----
- - ------------
V
V
~~
Maximum Input
Current
liN
VIN=Vce or GND
±0.1
±1.0
±1.0
/i A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VOUT=VCC or GND
±0.5
±5.0
±10.0
JAA
Maximum Quiescent
Supply Current
lee
VIN=Vce or GND
10ur=OJiA
8.0
80.0
160.0
/i A
=8SAMSUNG
Electronics
606
I"
KS54HCTLS
KS74HCTLS
210
Octal Buffers and Line Drivers
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input t r , tf~6 ns), HCTLS210
KS74HCTLS
KS54HCTLS
Vcc=5.0V:!:10%
Vcc=5.0V:!: 10%
T.=25~C T.=-400Cto +850C T.=-550Cto +125 0C
Vcc=S.OV
Typ
Maximum Propagation Delay,
A toY
fMax;mum OutpuLEnable
tpLH
13 18
16 21
22
27
27
33
tpHL
CL=50pF
CL=150pF
13 18
16 21
22
27
27
33
17 23
CL=50pF
CL=150pF 20 26
29
34
34
40
17 23
CL=50pF
CL =150pF 20 26
29
34
34
40
tPZH
Time, Enable to Y
RL=1kO
tPZL
Maximum Output Disable
Time, Enable to Y
Maximum Input Capacitance
Guaranteed Limits
CL=50pF
CL=150pF
~
tpHZ
- - RL =1 kO
tpLZ CL =50pF
Unit
16 21
26
32
16 21
26
32
-------
ns
ns
ns
5
pF
Maximum Output Capacitance COUT Output Disabled
10
pF
Output Disabled
Output Enabled
5
30
pF
Power Dissipation
Capacitance· (per stage)
CIN
Cpo
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fin.
t For AC switching test circuits and timing waveforms see section 2.
I
c5CSAMSUNG
• • Electronics
607
KS54HCTLS'~.9B
KS74HCTLS'
3-Line to 8-Llne DecoderslDomultiplexers
..
FEATURES
DESCRIPTION
• Designed specifically for high~speed memory
decoders and data transmission systems
• Incorporates 2 enable inputs to simplify cascading
and/or data reception
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOl =8 mA@ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +8,5°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices are designed to be used in highperformance memory-decoding or data-routing applications
requiring very short propagation delay times. In highperformance memory systems, these decoders can be
used with high-speed memories utilizing a fast enable
circuit. The delay times of these decoders and the enable
time of the memory are usually less than the typical access
time of the memory. This means that the effective system
delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the three
enable inputs select one of eight input lines. Two activelow and one active-high enable inputs reduce the need for
external gates or inverters when 'expanding.
A 24-line decoder can be implemented without external
inverters and a 31 -line decoder requires only one inverter.
An enable input can be used as a data input for
demultiplexing applications.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
FUNCTION TABLE
Enable
Inputs
I
Select
I
Outputs
A
Vee
8
YO
C
Yl
G1
G2*
C B A
YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
G2A
Y2
G2B
X
Y3
L
H
X
X X X
X X X
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L L L
L L H
L H L
H L L
H L L
H L H
H H L
Gl
Y4
Y7
Y5
GND
Y6
....
_- Inputs
~~~~
H H H
.-.--~-----
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
--
--
-
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
--
*(32=G2A+G28
c8SAMSUNG
Electronics
608
KS54HCTLS
KS74HCTLS
238
3-Line 8-Line /Jecot/ers/Demultiplexers
LOGIC DIAGRAM
Absolute Maximum Ratings·
Supply Voltage Range Vcc, ., .
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI> Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt . .
500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
·qsSAMSUNG
III
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS.74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise.& Fall Times, t r , t#
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
609
I
KS54HCTLS
KS74HCTLS
238
3-Line 8-Line DeCOClerslDemultiplexers
DC ELECTRICAL CHARACTERISTICS
(Vcc=5V± 1 0% Unless Otherwise Specified)
Characteristic
Minimum High-Level
Input Voltage
V
IH
2.0
2.0
2.0
v
0.8
0.8
0.8
V
f-------.--t-----.
Maximum Low-Level
V,L
I~~!_~ol~a.g~___._ ... f------.
Minimum High-Level
Output Voltage
1 - - - - .... - - ..- - f - - - - . .
VOH
Maximum Low-Level
Output Voltage
V,N=V,H or V,L
10=-20/AA
VOL
Vee -0.1
3.84
Vce Vee -0.1
10= -4mA_~~1---3-.~~V,N=V,H or V,L
10=20/AA
0
0.1
10=4mA
0.26
_ _ I -___
1 - - - - - - - - - .. - - - - -
..~-.--
l----
~2..~.~~_A~___ ~__+--O. 39__ e---.
'---. -- 1 - - - - .
t>lec
per input pin
Vz=2.4V
Other Inputs:
At Vee or GND
10=0
AC ELECTRICAL CHARACTERISTICS
160.0
-------
/AA
- - - - _ . _ - - - - - - - - - - - -----
3.0
mA
(Input tr , tl<::;6 nsl, HCTLS238
Unit
22 30
tpLH
Maximum Propagation Delay,
tpHL
- - - - - - - - - - - - - - - - - . - . - -.. ----.---.-l----~
I-~
tpHL
---f---.---t--------
l--~axi~_um_'~p_u_t_C_~_~i!ance
Power Dissipation CapaCitance *
45
37
45
24 32
24 32
40
40
~-- •..
. ----- ----.- -.---------- .
___ .\--___ . 4~ ______ _
48
I---.\------jf---.. - - - - - . - - - - - - I - - - - - . ---.---. -. --.
~+_~
18 25
ns
- - - - . - ._-----------
I----~- ----I--~--.-----------
~l:':I.._ CL=50pF
Maximum Propagation Delay,
G1to any Y
37
22 30
--\----
1-----
A, B, C or any Y
tpHL
. . _---_._-----------_._---+---
Maximum Propagation Delay,
G2A or G2B to any Y
I1A
_._---
Symbol
Characteristic
1------
---_.-
±1.0
2.9
2.7
V
.
Maximum Input
Current
--------.---- --.
Additional Worst
Case Supply
Current
V
----
0.1
0.4
0.1
0.33
0.5
±1.0
±0.1
-- - e---.... . --,-1--- -.--.-- - - -'--I----- ------..-1----.----.---Maximum Quiescent
I
VIN=VCC or'GND
80
800
Supply
Current
ee -- 10ur=0/AA
.
_._------.- _._--.- •. _------- - - - - - - - - - - \--._-_... -----_. __ ._.-. .
Vcc -0.1
3.7
1---_ _ _ _ _~1_~____________3_7
_____
-------1--------
31
ns
--\------
.~
ns
37
~1t_!._j_-----+-5__+-._+_-----_- . ________________ \--e.~_
Cpo
50
pF
* Cpo determines the no-load dynamic power dissipation: PD=CPD Vee 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
610
KS54HCTLS
KS74HCTLS
239
Dual 1-01-4 Decoders/Demultiplexers
FEATURES
DESCRIPTION
• Designed specifically for high-speed memory
decoders and data transmission systems
• Incorporates 2 enable inputs to simplify cascading
and/or data reception
These devices are designed to be used in highperformance memory-decoding or data-routing applications
requiring very short propagation delay times. In highperformance memory systems, these decoders can be
used to minimize the effects of system decoding. When
-used with high-speed memories utilizing a fast-enable
circuit, the delay times of these decoders and the enable
time of the memory are usually less than the typical access
time of the memory_
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Driv~Current outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
This means that the effective system delay introduced by
the decoder is negligible.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components .
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
I
FUNCTION TABLE
1G
Vee
1A
2G
1B
2A
1YO
28
1Y1
2YO
1Y2
2Y1
1Y3
2Y2
GND
2Y3
c8SAMSUNG
Electronics
Inputs
-Select
B
A
---"
Enable
G
H
L
L
L
L
X
X
L
L
H
H
L
H
L
H
j----- .
i
i
I
I
I
Outputs
YO
Y1
Y2
Y3
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
!
I
611
KS54HCTLS
KS74HCTLS
239'
'
Dual
1~f-4
Decoders/Demultiplexers
LOGIC DIAGRAM
ENABLE
16
(2)
SELECT
lA
INPUTS
(3)
{
lB
DATA
OUTPUTS
_(15)
ENABLE 2G
(14)
SELECT
INPUTS
{
2A
(13)
2B
Absolute Maximum Ratings*
Supply Voltage Range Vce,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vec +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 rnA
Continuous Output Cu'rrent Per Pin, 10
(':"0.5V < Vo < Vee +0.5V)
±70 rnA
Continuous Currenf Through
Vee or GND pins
±250 rnA
Storage Temperature Range, Tstg . . . - 65 ° C to + 150 ° C
Power Dissipation Per Package, Pdt
500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf .
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
612
'I
'I
1
KS54HCTLS
KS74HCTLS
239
Dual 1-of-4 Decoders/Demultiplexers
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 1 0% Unless Otherwise Specified)
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
T. =25°C
Test Conditions
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20j./A
lo=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20j./A
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
j./A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
j./A
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
boIce
Vee Vee -0.1
4.2
3.98
0
VIN=VCC or GND
lour=Oj./A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour=Oj./A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
Ta=25°C
Vcc=5.0V
KS74HCTLS
Ta= -40°C to +85°C
Vcc=5.0V±10%
Typ
Maximum Propagation Delay.
A or B any Y
Maximum Propagation Delay.
G to any Y
tpLH
r-tpHL
tPLH
t------
tPHL
CL=50pF
I
(Input t r • tf~6 ns), HCTLS239
KS54HCTLS
Ta= -55°C to +125°C
Vcc=5.0V± 10%
Unit
Guaranteed Limits
22 30
37
45
22 30
37
45
21
8
35
42
22
8
35
42
ns
ns
Maximum Input Capacitance
CIN
5
pF
Power Dissipation Capacitance *
Cpo
50
pF
* Cpo determines the no-load dynamic power dissipation: PO=CPD VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
EI~ctronic~
613
2401/"41'
'''44 Drivers
Octal Buffers and Line
. '/~'
,~
with 3-State Outputs
KS54HCTLS
KS74HCTLS'
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(loL 24 rnA @ VOL = 0.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTlS: -40°C to +85°C
KS54HCTlS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These high-speed octal buffers and line drivers are designed specifically to improve both the performance and densityof 3-state memory address drivers. clock drivers. and
bus-oriented receivers and transmitters.
=
The designer has the choice of combin~tions of inverting/
non-inverting outputs and symmetrical complementary input control (both active-low. or one active-low. the,other
active-high).
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels, The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
LOGIC DIAGRAMS
PIN CONFIGURATION
'240
Vee
1<3
1A1
2(3/2G
2Y4
1Y1
1A2
2A4
2Y3
1Y2
1A3
2A3
2Y2
1Y3
1A4
2A2
2Y1
1Y4
GND
2A1
(11
lG
lAl~
(18)
(2)
(41
(16)
(4)
(61
(14)
(8)
(121
lG
(18)
(1)
(2)
(18)
(4)
(16)
(6)
(l4J
(8)
(12)
(AI
(16)
(61
lY3
lA4_(_61_
(19)
?G
2G
·213 for '240 and '244
2G for '24.1
'244
'241
(11
10
('21
~
20
{19)
(11;
(9)
(11
2A2~~
(1)
(15)
('1
(15)
(5)
(17)
(3)
111}
(9)
(13J
I7J
(13)
(15)
(5)
(17)
(3)
(9)
2Y1
(l7J
2Y2
2Y3
_ ( 3 _ ) 2Y4
FUNCTION TABLE
'241, '244
Output
Input
~~.
'240
Output
~--'-.-~--,-
G
G
A
y
y
H
H
L
L
L
H
L
H
X
L
H
Z
H
L
Z
c8SAMSUNG
Electronics
--
614
KS54HCTLS
KS74HCTLS
24011/~"41'11"44
Octal Buffers and Line
~
Drivers with 3-State Outputs
Absolute Maximum Ratings·
Supply Voltage Range Vcc,
-0.5V to +7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vec +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±70 mA
Continuous Current Through
±250 mA
Vcc or GND pins
Storage Temperature Range,Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW'
t Power Dissipation temperature derating:
Plastic Package (N): -'12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Minimum High-Level
VIH
Input
Voltage
- -_ ... _.- .- -- --------- _. __ ._-- _._---Maximum Low-Level
ViL
Input Vol_t_a..:::g_e____~_+__---~
Minimum High-Level
Output Voltage
VOH
Maximum Low-Level
Output Voltage
VOL
Test Conditions
Maximum Quiescent
Supply Current
2.0
0.8
0.8
_____________ _
2_0
Output Enable
=VIH
VOUT=VCC or GND
-----t---------- - .. --~
Icc
--1-----
Vcc -0.1
3.7
VIN=VCC or GND
10uT=OJ.l.A
dCSAMSUNG
• • Electronics
±0.5
.
8.0
±1.0
-------
J.l.A
f--------
---- ----
±10.0
-----
80.0
V
-1-------
f-------- ---
±5.0
r--
V
0.1
0.4
±1.0
--~----+-~-------
~---
- ------
Vcc -0.1
3.84
±0.1
------ .-- 1----
V
-----------
VIN=VIH or VIL
0.1
10=20J.l.A
0
0.1
0.26
0.33
10= 12mA
'2.= 24mA____ t-_ _0_._3_9___+--~_. _____ . 0.5
--- ----
loz
V
0.8
--
VIN=VIH or VIL
10= - 20J.l.A
Vcc Vcc - 0.1
lo_==_-=-~~~ __ ~___~ _ 3.98
Maximum Input
Current
r---~-----------
2.0
-
1------------- -------------------------------
Maximum 3-State
Leakage Current
(Vcc=5V±10% Unless Otherwise Specified).
J.l.A
---
1----
160.0
-----
t----
J.l.A
615
I
KS54HCTLS
KS7~HCTLS
24'0'.''F/"4'
1"/"44 Drivers
Octal Buffers and Line
I~·, /~
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlonst
(Input tr • t,"6 ns). HCTlS240. HCTLS241. HCTLS244
KS74HCTLS
KS54HCTLS
T. =25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vc c =5.0V
Vcc=5.0V%10%
Vcc=5.0V% 10%
Typ
Maximum Propagation Delay.
A to Y
Maximum Output Enable
Time. Enable to Y
Guaranteed Limits
~PLH
CL=50pF
CL=150pF
13 18
16 21
22
27
27
33
tpHL
CL=50pF
CL =150pF
13 18
16 21
22
27
27
33
CL=50pF
17 23
CL=150pF 20 26
29
34
34
40
17 23
CL=50pF
CL=150pF 20 26
29
34
34
40
16 21
26
32
16 21
26
32
tPZH
f----
RL=1kO
tPZL
~~
i
Maximum Output Disable
Time. Enable to Y
~
tpLZ
ns
RL=1kO
CL,=50pF
- -
CIN
Maximum Output Capacitance COUT Output Disabled
Output Disabled
Power Dissipation
Cpo
Output Enabled
Capacitance· (per stage)
5
--~
ns
~-
Maximum Input Capacitance
ns
I------
pF
------ I------
10
pF
5
30
pF
.~
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc' f,
t For AC switching test circuits and timing waveforms see section 2.
cRSAMSUNG
• • Electronics
616
'''43
KS54HCTLS 242~
KS74HCTLS
,~
Quad Bus Transceivers
with 3-State Outputs
FEATURES
DESCRIPTION
• 2-Way Asynchronous Communication Between Data
Buses
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL = 24 mA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These four· data line transceivers are designed for
asynchronous two-way communications between data
buses.
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their LSTTl counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
INPUTS
Vee
NC
G8A
A1
NC
A2
61
A3
GND
GAB
'242
'243
L
L
A to B
A to B
82
H
H
B to A
B to A
83
H
L
Isolation
Isolation
L
H
Isolation
Isolation
84
I
GBA
LOGIC· DIAGRAMS
'242
'243
A1~----------~
·diSAMSUNG
". Electronics
617
K$54HCTLS
KS14HCTLS
24212.
4·3
14
Quad· Bus Transceivers
with 3-State Outputs
Absolute Maximum Ratings*
Power Dissipation temperature derating:
Plastic Package (N): -12mW!OC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-O.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, Tstg . . . - 65 ° C to + 150 ° C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vce
4.5V to 5.5V
DC Input & Output Voltages *, VIN, Your
OV to Vee
Operating Temperature
KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Vee=5V± 1 0% Unless Otherwise Specified)
°
Characteristic
Symbol
Minimum High-Level
Input Voltage
----_._-_._-_
........-
VIH
Test Conditions
Ta
=25.. C
r-"'--'
J =Ta
Typ
------
2.0
2.0
V
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.33
0.5
0.1
0.4
- - - _ . _ - _ ... _ - - - - - .
Maximum Low-Level
V
0.8
Input Voltage
__. _ - - - - - -IL- - - - ._..__ .._-----_._-_. -_ _--VIN=VIH or VIL
Minimum High-Level
10=-20/AA
Vee Vee -0.1
VOH
Output Voltage
10= -6mA \
4.2
3.98
---_.
...
- - - - - - - - - - - - - - - - - - - - _.. _ . _ - - . - - - - - -
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20/AA
10= 12mA
10=24mA
0
--
-_._-
0.1
0.26
0.39
------
r - - - - - - · - - - - t - - - - - - t - - - - - -------------- - -----.-- . - .. --.-- -----.. --..
Maximum Input
Current
±0.1
VIN=Vee or GND
c - - - - - - - - - - - - - - - - - - - - . - . - - - - - --- ----.-------
Maximum 3-State
Leakage Current
-----_._----_.
Maximum Quiescent
Supply Current
------.-----------.-
Additional Worst
Case Supply
Current
KS54HCTLS
to + 125°C Unit
= - 55°C
Guaranteed Limits
2.0
- _.
;1
KS74HCTLS
40°C to +85°C Ta
.----..-. ------ ...--.-.-- .-.---------
Output Enable
loz
=VIH
.
VouT=Vee or GND
- _ . _ - - .... - - - - -...
I
ec
±0.5
VIN=Vee or GND
10ur=0/AA
8.0
1l.lee
per input pin
VI=2.4V
other Inputs.
at Vec or GND
10ur=0/AA
c8SAMSUNG
Electronics
-
±1.0
±1.0
/AA
- - - - - - -. ---.---- ---.-------... - - - - - - f - - -
±10.0·
±5.0
-.- -- - -- ----c-- - ---.-----
-----.------.-- .. - - - - - - - - -
---
--.---+-------------f-~
80.0
--.--.----f---------- . - - . - - . - - - - - - -
160.0
.--.-----.-.----- ---
I
2.7
2.9
3.0
mA
I
618
KS54HCTLS
KS74HCTlS
242/~
/"43
AC ELECTRICAL CHARACTERISTICS
Characteristic
Quad Bus Transceivers
with 3-State Outputs
1
(Input tr ,
Symbol Conditions t
tf~6 ns), HCTLS242, HCTLS243
KS74HCTLS
KS54HCTLS
T.=25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V± 10%
Vcc=5.0V±10%
-- - ----------- --
Guaranteed limits
Typ
tpLH
Maximum Propagation Delay,
AtoBorBtoA
CL=50pF
CL=150pF
14 18
17 21
22
27
c---
---.---~----
CL=50pF
CL =150pF
14 18
17 21
22
27
CL=50pF
tPZH
CL =150pF
- - RL=1 kO f - CL=50pF
tPZL
CL=150pF
23 30
26 33
38
43
23 30
26 33
38
43
~ RL =1 kO
18 25
31
18 25
31
tpHL
GAB to B, GBA to A
Maximum Output Disable
Time, GAB to B, GBA to A
Maximum Input Capacitance
Maximum Output Capacitance
tpLZ
CL=50pF
i
27
33
ns
---
--------
45
51
r----------
--
ns
45
51
r---------37
ns
37
------------
---
pF
5
CIN
--
COUT Output Disabled
!Power Dissipation Capacitance· CPD
(per stage)
-
27
33
--
Maximum Output
Enable Time
--
Output Disabled
Output Enabled
10
5
30
- _.... _----
--
-
-
--
pF
-------- -----
1----
pF
I
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fill
t For AC switching test circuits and timing waveforms see section 2_
I
c8SAMSUNG
Electronics
619
KS54HCTLS
KS74HCTLS
245
.
Octsl Bus Transceivers with
3-State Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• 3-state outputs with high drive current
(lOL 24mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55 ° C to + 125 ° C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These high-speed octal bus transceivers are designed
for synchronous two-way communication between data
buses. The control function implementation minimizes
external timing requirements.
=
=
The devices allow data transmission from the A bus to
the B bus or from the B bus to the A bus depending
upon the logic level at the direction control (DIR) input.
The enable input (<3) can be used to disable the device
so that the buses are effectively isolated.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
PIN CONFIGURATION
LOGIC DIAGRAM
DIR
Vee
A1
G
A2
81
A3
82
A4
83
A5
84
A6
85
A7
85
A8
87
GND
88
DIR
(19)
G
A1
(18)
81
A2
(17)
82
(16)
83
(15)
84
(14)
85
FUNCTION TABLE
(13)
85
Inputs
G
Operation
(12)
87
DIR
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
Isolation
c8SAMSUNG
Electronics
(11)
88
620
· KS54HCTLS
KS74HCTLS
245
Octal Bus Transceivers with
3-State Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
-KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
Range
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V+
- 1 0% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
I
KS74HCTLS
:I
KS54HCTLS
Ta = -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OI-'A
6mA
10
Maximum Low-Level
Output Voltage
VOL
VIN = VIH or VIL
10=201-'A
10=12mA
10 24mA
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
I-'A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VOUT Vee or GND
±0.5
±5.0
±10.0
I-'A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
I-'A
2.7
2:9
3.0
mA
Additional Worst
Case Supply
Current
VIN=Vee or GND
10UT-01-'A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10UT-01-'A
.t.lee
=8SAMSUNG
• Electronics
I
Vee Vee -0.1
3.98
4.2
0
621
I
· KS54HCTLS245
KS74HCTLS
_
Octal Bus, Transceivers with
3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Condltlons t
(Input t r , tf"6 ns), .HCTLS245
KS74HCTlS
KS54HCTlS
T.=25°C T.= -400C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.OV±10%
Vcc=5.OV± 10% __
Vcc=5.OV
Typ
Maximum Propagation Delay,
A to B or B to A
tpLH
9
12
12 15
15
20
tpHL
CL=50pF
CL = 150pF
9 12
Maximum Output Enable
Time, G to A or B
- - - RL =1 kO
Maximum Output Disable
Time, G to A or B
~ RL=1kO
~m
18
34
ns
~---------
tPZH
f--.
Guaranteed Limits
CL=50pF
CL=150pF
tPZL
tpLZ
12 15
15
20
CL=50pF
30 40
CL=150pF 33 43
50
55
CL=50pF
30 40
CL =150pF 33 43
50
55
CL=50pF
- -1----- _.-
18
34
- - - - - - - -_._.. _.-
+----
60
66
ns
--------~.-
60
66
- - - -_ _ .__ .0-
18 25
31
37
18 25
31
37
ns
-~
Input Capacitance
5
CIN
Maximum Output Capacitance COUT Output Disabled
10
Power Dissipation
Capacitance* (per stage)
5
30
Cpo
G=Vcc
G=GND
--
f-------
pF
--------~---
..
I-'--
- - J'£..
pF
* CPD determines the no-load dynamic power dissipation: PO=CPD Vee' f,flt For AC switching test circuits and timing waveforms see section 2,
=8SAMSUNG
Electronics
622
KS54HCTLS
KS74HCTLS
251
1-01-8 Data Selectors/Multiplexers
with 3-State Outputs
FEATURES
DESCRIPTION
• Three-State Version of '151
• Three-State Outputs Interface Directly with System
Bus
• Performs Parallel-to-Serial Conversion
• Complementary Outputs Provide True and Inverted
Data
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL 24 rnA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
.. Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These data selectors/multiplexers contain full binary
decoding to select one·of-eight data sources and feature
strobe-controlled complementary three-state outputs.
=
The three-state outputs can interface with and drive data
lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state), the lowimpedance of the single enabled output will drive the bus
line to a high or low logic level. 80th outputs are controlled by the strobe (G). The outputs are disabled when G is
high.
=
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
03
Vee
02
04
01
05
DO
06
y
07
W
A
G
B
GNO
C
I
LOGIC DIAGRAM
(4)
01(3)
o
(1)
I~~~ 04.:..(1:,.:5.:..)--------t=t-=t=i~~gJ
o
FUNCTION TABLE
(14)
os (13)
~
~-~
OUTPUTS
INPUTS
. SELECT
. . --~-
--
STROBE
-
C
B
A
G
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
Y
Z
00
01
02
03
04
05
06
07
W
Z
00
51
52
53
54
55
56
57
~
dCSAMSUNG
• • Electronics
623
KS54HCTLS
KS74HCTLS
251
....
1-01-8 Data 5elec,IorslMulliplexers
wilh 3-51ale OU.tputs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, . . . .
-O.5V to + 7V
DC Input Diode Current, 11K
(VI < -O.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins. . . .
. .. ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
.... 500 mW
ReCommended Operating Conditions
Supply Voltage, Vee . . . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta == 25°C
Typ
KS74HCTLS
KS54HCTLS
Ta == -40°C to +85°C Ta == -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/-IA
10= -6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/-lA
lo=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
/-I A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
/-I A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/-I A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
blee
VIN=Vee or GND
10uT=O/-lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=O/-lA
c8SAMSUNG
Electronics
Vee Vee -0.1
3.98
4.2
0
I
I
!
I
624
KS54HCTLS
KS74HCTLS
251
1-of-8 Data Selectors/Multiplexers
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Symbol Conditions t
Characteristic
(Input tr , tf~6 ns), HCTLS251
~S74HCTLS :1
KS54HCTLS
Ta =25°C T a = -400C to +85°C Ta= -55°C to +125°C
Vcc=5.0V
Unit
f--__
Vcc=5.0V±10%
I Vcc=5.0V± 10%
Typ
CL =50pF
CL=150pF
tpLH
jMaXimUm Propagation Delay,
A, B or C to Y
- -
~
~-
-
f-----
40
46
ns
.--~~---
tpHL
CL=50pF
CL =150pF
20 26
23 29
33
38
40
46
fPLH
CL=50pF
CL =150pF
25 34
28 37
42
47
50
56
tpHL
CL=50pF
CL=150pF
25 34
28 37
42
47
50
56
tpLH
CL=50pF
CL=150pF
11 15
14 18
19
24
22
28
tpHL
CL=50pF
CL=150pF
11 15
14 18
19
24
22
28
tpLH
CL=50pF
CL =150pF
17 22
20 25
28
33
33
39
tpHL
CL=50pf
CL =150pF
17 22
20 25
28
33
33
39
CL=50pF 24 32
CL=150pF 27 35
40
45
48
54
CL=50pF 24 32
CL=150pF 27 35
CL=50pF 24 32
RL = 1 kO CL=150pF 27 35
CL=50pF 24 32
CL=150pF 27 35
40
45
48
54
40
45
48
54
40
45
48
54
Maximum Propagation Delay,
Any D to Y
------,
Maximum Output Enable Time,
G to Y or W
tPZH
RL =1 k:O
t-------
tPZL
-~--.-
tpHZ
Maximum Output Disable Time,
G to Y or W
r-:---tpLZ
Maximum Input Capacitance
--
~
ns
COUT Output Disabled
i
Cpo
10
~
1
ns
!'lSI
--
~-
ns
pF
- -[ - - pF
5
CIN
f--
,Maximum Output Capacitance
.Power Dissipation
Capacitance·
ns
-~-
Maximum Propagation Delay,
Any D to W
--
33
38
~-----
Maximum Propagation Delay,
A, B or C to W
f----~
Guaranteed Limits
20 26
23 29
pF
0
i
* Cpo determines the no-load dynamic power dissipation: PD=CPO Vee 2 fin-
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
625
I
KS54HCTLS
KS74HCTLS
253
Dual 1-0'-4 Data Selectors/Multiplexers
with 3-State Outputs
FEATURES
DESCRIPTION
•
•
•
•
Each of these data selectors/multiplexers contains inverters
and drivers to ~upply full binary decoding data selection to
the AND-OR gates. Separate output control inputs are pro·
vided for each of the two four-line sections.
•
•
•
•
•
Three-State Version of '153
Permits Multiplexing from N lines to 1 line
Performs Parallel-to-Serial Conversion
Function, pin-out, speed and drive compatibility with
54/74LS logic family
Low power consumption characteristic of CMOS
3-State outputs with high drive current
(IOL 24 mA @ VOL O.5V) for direct bus interface
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
=
=
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
Vee
B
lC3
lC2
lC1
The three· state outputs can interface with and drive data
lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state) the lowimpedance of the single enabled output will drive the bus
line to a high or low logic level. Each output has its own
strobe (G). The output is disabled when its strobe is high.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components .
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
SELECT
DATA INPUTS
OUTPUT
CONTROL
OUTPUT
CO C1 C2 C3
G
y
H
L
L
L
L
L
L
L
L
Z
L
H
L
H.
L
H
·L
H
2<3
A
2C3
2C2
2C1
·8
A
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
Address inputs A and B are common to both sections.
c8SAMSUNG
Electronics
626
KS54HCTLS
KS74HCTLS
253
Dual 1-of-4 Data Selectors/Multiplexers
with 3-State Outputs
LOGIC DIAGRAM
OUTPUT
lY
I
OUTPUT
2Y
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, ilK
(V, < -0.5V or V, > Vee +0.5V)
±20 mA
DC Output Diode Current,loK
(Vo < -0.5V or Vo > Vee +0.5V). :;!:20 mA
Continuous Output Curret1t Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vce or GND pins
± 125 mA
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
.. Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
III
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages·, V'N, VOUT
OV to Vce
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
627
KS54HCTLS
KS74HCTLS
253
Dual 1-01-4 Data Selectors/Multiplexers
with 3-State Outputs
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V±10% Unless Otherwise Specified)
KS74HCTLS
KS54HCTLS
T.= -40°C to +85°C T.= -55°C to +125°C Unit
T. =25°C
SymbOl Test Conditions
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
V,H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V,L
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
V'N=V'H or V,L
lo=-20JolA
lo=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
V,N=V,H or V,L
lo=20JolA
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
/AA
Maximum 3-State
Lel;lkage Current
loz
Output Enable
=V,H
VOUT=VCC or GND
±0.5
±5.0
±10.0
JolA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/AA
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
6 1cc
Vee Vee -0.1
4.2
3.98
0
V'N=VCC or GND
louT=OJolA
per input pin
V,=2.4V
other Inputs:
at Vee or GND
louT=OJolA
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input t r , tf~6 ns), HCTLS253
KS74HCTLS
KSS4HCTLS
T.=2SOC
T.=-400Cto +8S OC T.=-SSOCto +12SoC
Vcc=S.OV
Unit
Vcc=S.OV±10%
Vcc=S.OV± 10%
Typ
Maximum Propagation Delay,
A or B to Any Y
Maximum Propagation Delay,
Data (any C) to any Y
Maxim!!.m Output Enable
Time, G to Y
tpLH
24 32
27 35
40
45
48
54
tpHL
CL=50pF
CL =150pF
24 32
27 35
40
45
48
54
tpLH
CL=50pF
CL=150pF
15 20
18 23
25
30
30
36
tpHL
CL=50pF
CL =150pF
15 20
18 23
25
30
30
36
CL=50pF
17 22
CL=150pF 20 25
28
33
33
39
CL=50pF
17 22
CL=150pF 20 25
28
33
33
39
tPZH
f------
RL=1kO
tPZL
Maximum Output Disable
Time, G to Y
Maximum Input CapaCitance
tpHZ
I---
tpLZ
RL=1kO
CL=50pF
C,N
. Maximum Output CapaCitance COUT Output Disabled
Power Dissipation
CapaCitance *
Guaranteed LImits
CL=50pF
CL=150pF
17 22
28
33
17 22
28
33
ns
ns
ns
ns
5
pF
10'
pF
Cpo
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee fin.
2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
'
628
KS54HCTLS
KS74HCTLS
2571258 Quad 2-Line to 1-Line Data Selectors/
Multiplexers with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
• Package options include" small outline" packages
(Available Tape & Reel), standard DIPs.
The '257 and '258 multiplex signals from for-bit data
sources to four-output·data lines in bus organized systems.
The data presented at the outputs is non-inverted for the
'257 and inverted for the '258.
PIN CONFIGURATION
FUNCTION TABLE
=
=
Aia
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
Inputs
Vee
1A
~
1B
1Y
2A
2B
2Y
4A
4B
4Y
3A
3B
3Y
GND
Output
Control
Output Y
I···· select
Data
'257
G
AlB
A
B
H
L
L
L
L
X
L
L
H
H
X
L
H
X
X
X
X
X
L
H
'258
Z
Z
L
H
L
H
H
L
H
L
LOGIC DIAGRAMS
'257
'258
1A------------~L-~
(3)
1Y
1Y
...
1B----------4-~ ~
(51
2A----------4-~
2A~--------~~-J
(6)
2B-----------r~L-~
2Y
2B---------~~-J
(11)
3A-----------r4-L-~
(10)
3A---------~~-J
3Y
3B---------~4-L-~
(14)
4A
-------r+-i..-J
(13)
4Y
4B---------~4-~_J
c8SAMSUNG
Electronics
629
I
KS54HCTLS
KS74HCTLS
2571258
Quad 2-Line to 1-Line Data Selectors/
Multiplexers with 3-State Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vcc. .. . .
-0.5V to + 7V
DC Input Diode Current. hK
(VI < -0.5V or V, > Vcc +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo <-0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin. 10
(-0.5V < Vo < Vcc +0.5V)
±70 mA
Continuous Current Through
Vcc or GND pins. .
±250 mA
Storage Temperature Range. Tstg ... -65°C to +-150°C
Power Dissipation Per Package. Pdt .
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vcc . .
4.5V to 5.5V
DC Input & Output Voltages·. V,N. VOUT .. OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise ~ Fall Times. t r • tf
Max 500 ns
I
* Absolute. Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long ex·
posure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 10% Unless Otherwise Specified)
Test Conditions
Minimum High-Level
V,H
2.0
In__p_u_t_V__o__
'ta_g~::...e__ ._--+~ ___ ._______._.__._
Maximum Low-Level
0.8
V,L
111~~_~?'tage__ .__--+-___-+-____.__ ._..__ f- ..-.- _ .
V,N=V,H or V'L
Minimum High-Level
10=-20IJA
Vcc Vce -0.1
VOH
Output Voltage
'
10=-6mA
4.2
3.98
.+-
- - - - - - - - - - + - - - - 1 - - - - - - - ' ' - - . - - - - --.. -
Maximum Low-Level
Output Voltage
VOL
V'N=V'H or V,L
10=201JA
10=12mA
10=24mA
o
0.1
0.26
0.39
2.0
v
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.33
0.5
0.1
0.4
±1.0
±l-.O
±5.0
±10.0
-~--r-------
Maximum Input
hN
VIN=Vce or GND
±0.1
Current .----+----+---------e----r---.--.-Output Enable
Maximum 3-State
±0.5
loz
=V'H
Leakage Current
VouT=Vee or GND
--..... ---.------I-------t---=--'~~-.---
2.0
+----
V
. ----. -. f---
'MaXirnum Quiescent Icc
VIN=Vee or GND I
8.0
80,0
160.0
jS~u~~'::p~p~ly__C=_u=r.:...re:.:.n:.:.t_ __+--__l_'.=o::-U-T:..=-O---IJ-A---_+__~-- ____ .___.________---+___________ ._
per input pin
IAdditional Worst
V,=2.4V
iCase Supply
~Iee other Inputs:
2.7
2.9
3.0
I Current
at Vee or GND
I
10UT=0/JA.
r
dCSAMSUNG
• • Elec~ronics
IJA
--
mA
630
KS54HCTLS
KS74HCTLS
257/258 Multiplexers
Quad 2-Line to 1-Line.Oata Selectors/
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input t r , tf~6 ns), HCTLS257, HCTLS258
KS74HCTlS
KS54HCTLS
T. =25°C
T.=-40°Cto +85°C T.= -55°C to +125°C
Unit
Vee=5.0V
Vee = 5.0V:!: 10%
Vee=5.0V:!: 10%
Guaranteed Limits
Typ
Maximum Propagation Delay,
A to B to any Y
tPLH
CL=50pF
CL =150pF
14 18
17 21
23
28
27
33
tpHL
CL=50pF
CL =150pF
14 18
17 21
23
28
27
33
tpLH
CL=50pF
CL =150pF
16 21
19 24
26
31
31
37
tpHL
CL=50pF
CL =150pF
16 21
19 24
26
31
31
37
CL=50pF
22 30
CL=150pF 25 33
37
42
45
51
CL=50pF
22 30
CL =150pF 25 33
37
42
45
51
Maximum Propagation Delay,
AlB to any Y
Maxim~m
Output Enable
Time, G to any Y
tPZH
I-----
RL =1kO
tPZL
Maximum Output Disable
Time, G to any Y
Maximum Input Capacitance
tPHZ
I-----
tpLZ
RL =1kO
CL =50pF
CIN
Maximum Output Capacitance COUT Output Disabled
Power Dissipation
Capacitance *
20 27
34
41
20 27
34
41
"--
I---
ns
ns
-~
5
~
t---- ----
10
CpD
ns
ns
pF
--~~
pF
. Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fin.
t
For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
631
I
KS54HCTLS
KS74HCTLS
25.9
8-Bit Addressable Latches
FEATURES
DESCRIPTION
• 8-Bit parallel-out storage register performs serial-toparallel conversion with storage
• A,synchro'nous parallel clear
• Active high decoder
• Enable/Disable input simplifies expansion
• Expandable for N-bit applications
• Four distinct functional modes
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10L =8 mA @ VOL =0.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
The '259 is a high·speed addressable latch designed for
general purpose storage applications in digital systems. It
can be used for implementing working registers, serial·
holding registers and active·high decoders or
demultiplexers.
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
In the clear mode, all outputs are low and unaffected by
the address and data inputs.
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output VOltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
80
Vee
81
ClR
82
G
D
00
01
07
02
06
03
05
GND
04
CLR
G
H
H
L
L
L
H
L
H
Output of
Addressed
Latch
Each
Other
Output
D
QiO
QiO
QiO
0
L
L
L
In the addressable latch mode, data on the data input (D)
is written into the addressed latch, In this mode, data will
be written into the addressed latch with all non-addressed
latches remaining in their previous states.
In the memory mode, all latches remain in their previous
state and are unaffected by the data of address inputs,
In the demultiplexing mode, addressed outputs will follow
the state of the D input and all other outputs will remain low.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LA TCH SELECTION TABLE
FUNCTION TABLE
Inputs
The '259 has four distinct modes of operation that are
selected via the clear (CLR) and enable (<3) inputs: 1) ad·
dressable latch; 2) memory; 3) active·high eight-channel
demultiplexer; and 4) clear.
Select Inputs
Function
Addressable Latch
Memory
a-Une Demultiplexer
Clear
o ... the level at the data input.
010 = the level of 010 (i = 0, 1, '" 7, as appropriate) befate the
Indicated steadY'state input conditions were established,
c8SAMSUNG
Electronics
Latch
52
51
50
Addressed
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
632
KS54HCTLS
KS74HCTLS
259
8-Bit Addressable Latches
LOGIC DIAGRAM
ern
(15\
so
G
Sl
S2
(14\
D
(13)
00
01
02
03
04
05
06
I
07
Absolute Maximum Ratings*
Supply Voltage Range Vee, ...... -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±35 mA
Continuous Current Through
Vce or GND pins
± 125 mA
Storage Temperature Range, T 51g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
=8SAMSUNG
Electronics
Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tl
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
633
KS54HCTLS2
KS74HCTLS '
59
8-Bit Addressable Latches
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Test Conditions
f~r-~~·--···--
J
KS74HCTLS
KS54HCTLS
_!"a = - 40°C to + 85°C Ta = - 55°C to +"I!~~ Unit
Typ
Minimum High-Level
Input Voltage
Guaranteed Limits
2.0
V,H
2.0
V
2.0
-~
Maximum Low-Level
Input Voltage
V,L
0.8
r----------~ r----~ r----.--.---~----
Minimum High-Level
Output Voltage
VOH
~-.--
Y,N = V,H or V,L
lo=- 2O/AA
lo=-4mA
0.8
0.8
----- r------ ... -. -- ---_...._ - - - - - - - - - - - - - -
Vee Vee -0.1
4.2
3.98
Vee -0.1
3.84
V
---.---~.--
~
Vee -0.1
3.7
---
V
~--.-
Maximum Low-Level
Output Voltage
VOL
------~--r_
V,N=V,H Qr V,L
lo=20",A
lo=4mA
lo=8mA
0
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
--~
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
-
~-
Maximum Quiescent
Supply Current
Icc
r·
Additional Worst
Case Supply
Current
!llcc
V'N=VCC or GND
IOUT=O/AA
per input pin
V,=2.4V
other Inputs:
at Vec or GND
10UT=0",A
8.0
Symbol
Conditions t
--- - ---
--"
-
160.0
__ 0_-
AC ELECTRICAL CHARACTERISTICS
Characteristic
__.-
------_. __.
80.0
2.7
V
-----_._--------- - ---
2.9
-
3.0
~--
/AA
---
/AA
c-
mA
(Input t r • tl<6 ns). HCTLS259
T. =25°C
Vcc=5.0V
KS74HCTLS
T.= -40°C to +85°C
Vcc=5.0V:!: 10%
Typ
KS54HCTLS
T.= -55°C to +125°C
Vcc=5.0V:!: 10%
Unit
Guaranteed Limits
Maximum Propagation Delay
CLR to any Q
tpHL
22 30
37
45
Maximum Propagation Delay.
Data to Any Q
tpLH
r----tpHL
20 27
34
41
20 27
34
41
Maximum Propagation Delay.
Address to any Q
I - - - - - CL=50pF
tpLH
26 34
43
51
tpHL
26 34
43
51
tpLH
22 30
37
45
tpHL
22 30
37
45
8 10
13
15
8 10
13
15
8 10
13
15
ns
0
0
ns
----
Maximum Propagation Delay.
G to any Q
Minimum Pulse
Width
I
CLR LOW
I GLow
I-----
tw
Minimum Setup Time.
Data or Address before
Gt
tsu
Minimum Hold Time.
Data or Address before
Gt
th
-3
Maximum Input Capacitance
C'N
5
Power Dissipation Capacitance *
CPD
80
0
determines the no-load dynamic power dissipation: PD=CPD Vcc'
t For AC switching test circuits and timing waveforms see section 2.
* CpD
c8SAMSUNG.
Electronics
ns
ns
ns
ns
ns
pF
pF
fin.
634
Quad Exclusive-NOR Gates
with Open-Drain Outputs
KS54HCTLS·266
KS74HCTLS
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74lS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOl =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTlS: -40°C to +85°C
KS54HCTlS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices contain four independent exclusive-NOR
gates with open-drain outputs. Using a suitable pull-up
resistor, these outputs may be connected to other opendrain outputs to implement wired-AND functions.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
r
(3,4,10,11)
1A
Vee
18
49
1Y
4A
2Y
4Y
2A
3Y
29
38
GND
3A
:
(1,5,8,12)
(2,6,9,13)
)D---1
y
I
.
FUNCTION TABLE
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
H
L
L
H
=8SAMSUNG
Electronics
635
KS54HCTLS
KS74HCTLS
266
Quad Exclusive-NOR Gates
with Open-Drain Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±35 inA
Continuous Current Through
Vce or GND pins
± 125 mA
Storage Temperature Range, T519 ... -65°C to +150°C
Power Dissipation Per Package, Pdt. . .
500 mW
t Power Dissipation temperature. derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, Your
OV to Vec
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
.. Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
The'se are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
I
KS74HCTLS
KS54HCTLS
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
Vil
0.8
0.8
0.8
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or Vil
10=20J.lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
J.lA
Maximum Output
Leakage Current
loz
VIN=VIH or Vil
Vour=Vcc
±0.5
±5.0
±10.0
J.lA
Maximum Quiescent
Supply Current
Icc
20.0
40.0
J.lA
2.9
3.0
mA
~-.--
Additional Worst
Case Supply
Current
ll.lec
0
VIN=Vee or GND
10ur=OJ.lA
per input pin
VI=2.4V
other Inputs:
at Vce or GND
10ur=OJ.lA
2.0
--
Symbol
Conditions t
~
2.7
AC ELECTRICAL CHARACTERISTICS
CharacteristiC
.-
(Input t r ,
Ta=25°C
Vee=5.0V
tf~6
ns), HCTLS266
KS74 HCTLS
KS54 HCTLS
Ta=-40°C to +85°C Ta = - 55 ° C to + 125 ° C
Unit
Vee = 5.0V ± 10%
Vee=5.0V± 10%
Typ
Maximum Propagation Delay
tplH
CL=50pF
r---RL =1 kO
tpHL
Maximum Input CapaCitance
Power Dissipation Capacitance *
CIN
Guaranteed Limits
18
25
31
37
16
22
28
33
5
(per gate)
15
CPD
* CPD determines the no-load dynamic power diSSipation: Po=Cpo Vee' fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
• Electronics
ns
pF
pF
636
KS54HCTLS
KS74HCTLS
273
Octal 0-Type Flip-Flops with Clear
FEATURES
DESCRIPTION
• Eight positive-edge-triggered D-type flip-flops with
single-rail outputs
• Buffered common clock and asynchronous clear
These devices are high-speed octal registers. They consist of eight positive-edge-triggered D-type flip-flops with
individual D inputs and Q outputs. All flip flops are loaded
and cleared simultaneously by the common buffered clock
(ClK) and clear (ClR) inputs.
• Function, pin-out, speed and drive compatibility with
54174lS logic family
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
(IOl = 24mA @ Val = O.5V) for direct bus Interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse. When the clock input is at
either the high or low level, the D input Signal has no effect at the output.
These devices provide speeds and drive capability
equivalent to their lSTIl counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
FUNCTION TABLE
I
(Each Flip-Flop)
ClR
Vee
10
80
10
80
20
70
20
70
30
60
3D
60
40
SO
SO
40
GNO
Inputs
Output
Q
ClR
ClK
0
L
H
H
X
X
l
t
t
H
L
H
H
l
X
Qo
l
ClK
LOGIC DIAGRAM
10
(11)
20
(3)
3D
SO
40
(7)
(4)
60
(13)
(8)
80
70
(14)
(17)
(18)
ClK
(2)
10
c8SAMSUNG
Electronics
(S)
20
(6)
30
(9)
40
(1S)
(12)
SO
60
(16)
7Q
(19)
80
637
273
KS54HCTLS
KS74HCTLS ........ , .
Octal D-Type Flip-Flops with Clear
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-o;sV to + 7V
DC Input Diode Current, 11K
(VI < -O.SV or VI> Vee +(}.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -O.SV or Vo > Vee +O.SV)
±20 rnA
Continuous Output Cu'rrent Per Pin, 10
(-O.SV < Vo < Vee +O.SV)
±70 rnA
Continuous Current Through
Vee or GND pins
±2S0 rnA
Storage Temperature Range, Tstg . . . -6SoC to +1S0°C
Power Dissipation Per Package, Pdt
SOO mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 6SoC to 6SoC
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . . . .
4.SV to S.SV
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +8SoC
KSS4HCTLS: -SsoC to +12SoC
Input Rise & Fall Times, tr , tf
.. Max SOO ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vce or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=SV± 10% Unless Otherwise Specified)
Ta =25°C
Typ
Minimum High-Level
!~put Voltage
Maximum Low-Level
Input Voltage
VIH
VIL
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Vee -0.1
3.84
Vce -0.1
0.1
0.26
0.39
0.1
0.33
O.S
0.1
0.4
V
±0.1
±1.0
±1.0
J.lA
8.0
80.0
160.0
J.lA
2.7
2.9
3.0
rnA
f-.
Minimum High-Level
Output Voltage
VOH
f-.
VIN=VIH or VIL
10=-20J.lA
10=-6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/JA
10=12mA
10=24mA
Maximum Input
Current
liN
VIN=Vce or GND
Maximum Quiescent
Supply Current
lee
Additional Worst
Case 'Supply
Current
l:I.lcc
VIN=Vec or GND
10uT=0/JA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10uT=OJ.lA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
3.7
V
638
KS54HCTLS
KS74HCTLS
273
Octal 0-Type Flip-Flops with Clear
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input tr • tj";;6 ns). HCTlS273
T. =25°C
Vcc=5.0V
KS74HCTLS
KS54HCTLS
-40°C to +85°C T. = -55°C to +125°C
Unit
Vcc=5.0V:t10%
Vcc=5.0V:t 10%
'1'. =
Typ
Maximum Clock Frequency
Maximum Propagation Delay.
ClK to any
Maximum Propagation Delay.
ClR to any Q
ClR low
Minimum Pulse
ClK High or low
Width
Minimum Setup Data
Time before
Clear inactive
ClKt
State
Minimum Hold Time. Data after ClKt
CL=50pF
40 30
25·
20
tpLH
CL=50pF
CL=150pF
20 27
23 30
33
38
40
46
tPHL
CL=50pF
CL=150pF
20 27
23 30
33
38
40
46
tpHL
CL=50pF
CL=150pF
20 27
23 30
33
38
40
46
10 13
17
20
10 13
17
20
10 13
17
20
13 17
21
25
0
0
tw
tsu
CIN
Power Dissipation Capacitance"
Cpo
r
-3
th
Maximum Input Capacitance
*
Guaranteed Limits
f max
0
5
(per package)
=8SAMSUNG
Electronics
ns
ns
ns
ns
ns
--f - -
pF
pF
150
Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee'
For AC switching test circuits and timing waveforms see section 2.
MHz
fin
I
639
KS54HCTLS
KS74HCTLS
2Q6
0'
9-Bit Parity GeneratorslCheckers
FEATURES
DESCRIPTION
• Generates Odd or Even Parity for Nine Data Lines
• Cascadable for N-Bits Parity
• Can be used to Upgrade Existing Systems using MSI
Parity Circuits
• Function, pln-out, speed and drive compatibility with
54174lS logic family
,
• low power consumption characteristic of CMOS
• High-Drive-Current outputs:
(loL =24 mA @ VOL =O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These universal, nine-bit parity generators/checkers feature
odd and eve/) outputs to facilitate operation of either odd
or even parity application. The word-length capability is easily expanded by cascading.
The devices can be used to upgrade the performance of
most systems utilizing the '180 parity generator/checker,
Although the '280 is implemented without expander inputs,
the corresponding function is provided by the availability
of an input at pin 4 and the absence of any internal con~
nection at pin 3. This permits the '280 to be substituted
for the '180 in existing designs to produce an identical function even if the devices are mixed with existing '180's.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps ,to Vee and
ground.
FUNCTION TABLE
PIN CONFIGURATION
G
Vee
H
NC
E
0
l: EVEN
C
l:ODD
B
GND
A
=8 SAMSUNG
Electronics
NUMBER OF INPUTS A
THRU I TJiAT ARE HIGH
0,2.4,6,8
1,3.4,5,9
OUTPUTS
~
EVEN
H
L
~
ODD
L
H
640
KS54HCTLS
KS74HCTLS
280
9-Bit Parity Generators/Checkers
LOGIC DIAGRAM
A (8)
B (9)
C (10)
I
eVEN
o
(11)
(12)
F (13)
000
I
(1)
G
H
I
(2)
(41
Absolute Maximum Ratings*
Supply Voltage Range Vee, ..
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -O.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-O.5V < Vo < Vee +0.5V)
±35 rnA
Continuous Current Through
Vee or GND pins
± 125 rnA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/o C from 65 ° C to 85 ° C
Recommended Operating Conditions
Supply Voltage, Vee . . . .
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vce or GND)
641
28'" 0
,KSS4HCTLS
KS74HCTLS
9-Bit Parity Generators/Checkers
DC ELECTRICAL CHARACTERISTICS
Symbol Test Conditions
Charac:teristlc:
(Vcc=5V± 1 0% Unless Otherwise Specified)
KS74HCTLS
KS54HCTLS
T.= -40°C to +85°C T.= -55°C to +125°C Unit
T. =25°C
Typ
Guaranteed Limits
~
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
u.8
u.B
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/oiA
10= -6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/oiA
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
IJA
8.0
BO.O
160.0
/oIA
2.7
2.9
3.0
mA
--
Maximum Input
Current
Maximum Quiescent
Supply ~~~~_~_
Additional Worst
Case Supply
Current
Icc
-----
llicc
Vee Vee -0.1
4.2
3.98
0
VIN=VCC or GND
10ur=O/oiA
per input pin
VI=2.4V
other Inputs:,
at Vee or GND
10uT==O/oiA
AC ELECTRICAL CHARACTERISTICS
Characteristic
--_ ...
KS54HCTlS
~ KS7 Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu·rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±70 mA
Continuous Current Through
Vee or GND pins . . .
± 250 mA
Storage Temperature Range, T5 tg . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vee
Operating Temperature
Range
·KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 10% Unless Otherwise Specified)
T. =25°C
Test Conditions
Typ
KS74HCTLS
T. = -40°C to +85°C T.
KS54HCTLS
+125°C Unit
= -55°C to
Guaranteed Limits
Minimum
High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum
Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
Vee -0.1
3.84
3.7
VIN=VIH or VIL
Minimum HighLevel Output
Voltage
VOH
f-
10=-20~A
Vee Vee -0.1
Q'A and Q'H outputs:
4.2
3.98
10= -4mA
QA thru QH outputs:
10=-6mA
4.2
3.84
V
3.7
VIN=VIH or VIL
10=20~A
Miximum
Low-Level
Output Voltage
VOL
Q'A and Q'H outputs:
10=4mA
10=8mA
QA thru QH outputs:
10=12mA
10=24mA
0
0.1
0.1
0.1
0.26
0.39
0.33
0.5
0.4
0.26
0.39
0.33
0.5
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
j.tA
Maximum 3-State
Leakage Current
loz
Output Enable = VIN
VouT=Vee or GND
±0.5
±5.0
±10.0
j.tA
Maximum
Quiescent
Supply Current
Icc
VIN=Vee or GND
10uT=0j.tA
8.0
80.0
160.0
j.tA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0j.tA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Iee
c8SAMSUNG
Electronics
645
I
KS54HCTLS
KS74HCTLS
299
8-Bit ·Universal Shift/Storage Registers
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r • tf:Et6 ns)'. HCTLS299
T = 250C
KS74HCTLS
KS54HCTLS
•
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V±10%
Vcc=5.0V± 10%
Conditions t
Symbol
Typ
Guaranteed Limits
Maximum Clock Frequency
fmax
35 25
20
18
Maximum Propagation Delay.
CLK to QIA or Q'H
tpLH
26. 35
4
53
26 35
44
53
30 40
50
60
24 32
27 35
f-.
40
45
48
54
24 32
27 35
40
45
48
54
30 40
33 43
50
55
60
66
20 26
23 29
33
38
39
45
20 26
23 29
33
38
39
45
13 17
21
26
13 _17
.. -
21
26
-
CL=50pF
tpHL
t------------------ ---
Maximum Propagation Delay.
CLR to Q'A or Q'H
tpHL
1-----
Maximum Propagation Delay.
ClK to QA thru QH
,/
tpLH
CL=50pF
CL=150pF
tpHL
CL=50pF
CL=150pF
-
--I-
CL=50pF
CL =150pF
- - .------.--t-CL=50pF
tPZH
Maxi!!!um Output Enable Time. _._--_._-- RL = 1 kG CL=150pF
G1. G2. to QA thruQH
CL =50pF
tPZL
CL=150pF
- - - ---_._-"
-tpHZ
Maximum Output Disable Time. _._RL = 1 kG
<31. <32 to QA thru QH
CL=50pF
tpLZ
- -.... -..
...--_. - - --ClK High or low
Minimum
tw
Pulse
Width CLR low
. - _... _._.- - ..
-----SO and S1
Minimum
High-level Inputs
tsu
Setup time
High-level Inputs
before ClKt
ClR Inactive
- - - - - _.. _-_.._ - - -
--~-.-----.---
-
----.--.-.-~----
rd
- --------- -
-- -
-
--
-
--"-
th
All Inputs
---- -
.
-----
MaXimum Input Capacitance
-------------- -
-----_._.•. _ - - - - -
1------
c---
---
10 13
17
20
17
20
13 17
21
25
10 13
...
17
20
17
20
--..
--~-
------
10 13
.
----
--
.-------
10 13
-----~
10 13
~~
f---
- .------
.
5
7
--,--.
0
a--
f--
_10
.. -
-----
- - - - - ~-
---------
--_
---.---_._------ ---
CpD
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee'
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
17
_--- ------8
-_.-
..
0
.
5
CIN
__ __
Maximum
Output . Capacitance
Output Disabled
---_... _-_._. ---_ ...
. _ - - - - -COUT
- - -- - - - - - - - - - - - - Power Dissipation Capacitance *
- -f----
--------~--.-.-----
---------- - - - - -
SO and S1
T;me
after CLKt
-~-
-~
~---
Minimum
tpHL
-----
-~---
ns
ns
1--
-----.-~-----
Maximum Propagation Delay.
ClR to Qa thru QH
MHz
.. _--
ns
ns
ns
ns
---
ns
ns
20
10
ns
0
pF
pF
pF
fin.
646
KS54HCTLS
KS74HCTLS
322A.
8-Bit Shift Registers
with Sign Extend
FEATURES
DESCRIPTION
• Multiplexed inputs/outputs provide improved bit
density
• Sign extend function
• Direct overriding clear
• 3 state outputs drive bus lines directly
• Function pin-out, speed and drive compatibility with
54174 LS logic family
• Low power consumption characteristic of CMOS
• High drive current output
(loL=24mA @ VOL=O.5V) for for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices.
• Wide Operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and military
temperature range:
KS74HCTLS : -40°C to +85°
KS54HCTLS : -55°C to +125°
• Package options include plastic "small outline"
packages, standard plastic and ceramic 300-mil DIPs
These B bit Shift registers have multiplexed input/output
data ports to accomplish full B-bit data handling in a single
20-pin package. Serial data may enter the sHtt-right register
through either Do or 01 input as selected by the data
select pin. A serial oytput is also provided. Synchronous
parallel loading is achieved by taking the register enable
and the SIP inputs low. This places the three-state input/output ports in the data input mode. Data are entered
on the low-to-high clock transition. The data extend function repeats the sign in the QA flip flop during shifting. An
overriding clear input clears the internal register when taken
low whether the outputs are enabled or off. The output
enable does not affect synchronous operation of the
register.
,I
PIN CONFIGURATION
Register
enable
SIP
Do
Sigh extend (SE)
A/O,
0,
C/O e
BlOB
E/O E
D/O D
G/OG
Output
enable
FlO,
H/OH
Clear
OH'
GND
Clock
c8SAMSUNG
• Electronics
Vee
Data select (OS)
647
KS54HCTLS 3.1~" A
KS74HCTLS. ~~11
8-Bit Shift Registers
with Sign Extend
FUNCTION TABLE
INPUT
"SIgn
Clear
Register
enable
SIP
L
L
H
X
X
H
Hold
H
H
Shift Right
H
H
L
L
Sign Extend
H
L
H
L
Load
H
L
L
X
OPERATION
Clear
INPUT/OUTPUTS
extend
Data
select
Output
enable
Clock
A/QA
B/QB
X
X
X
X
L
L
X
X
L
L
L
L
L
L
L
L
L
L
X
X
X
L
X
QAO
QBO
Qco
QHO
QHO
H
H
H
H
L
H
L
L
t
t
Do
01
QAn
QAn
QBn
QBn
QGn
QGN
QGn
QGn
X
L
t
QAn
QAn
QBn
QGn
QGn
X
X
t
a
b
c
h
h
C/Qc --- H/QH
Output
QH'
When the output enable is high, the eight input/output terminals are disabled to the high-impedance state: however,
sequential operation or clearing of the register is not affected. If both the register enable input and the SIP input are
low while the clear input is low, the register is cleared while the eight input/output terminals are disabled to the highimpedance state.
H== high level (steady state)
L= low level (steady state)
X= irrelevant (any inputs, including transitions)
t = transition from low to high level
QAo ... OHo= the level of QA through QH, respectively, before the indicated steady-state conditions were established.
QAn ... OHn= the level of QA through QH, respectively, before the most recent t transition of the clock.
Do, D1 = the level of steady-state inputs at inputs Do and D1 respectively
a... h= the level of steady-state inputs at input A through H respectively.
LOGIC DIAGRAM
REGISTER (1)
ENABLE
G
OUTPUT (8)
ENABLE
DE
-------- Vee +0.5V) .... , ±20 r
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0.5V) .... ±20 mA
Continuous Output Current Per Pin. 10
(-0.5V < Vo < Vee +0.5V) ....... , ±35 mA
Continuous Current Through
Vee or GND pins . . . . . . . . . . . . . . .. ± 125 mA
Storage Temperature Range, Tsto ... -65°C to +150°C
Power Dissipation Per Package. Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage. Vee .............. 4.5V to 5.5V
DC Input & Output Voltages * • V,N. VOUT . . OV to Vcc
Operating Temperature
.
Range
KS74AHCT: -40°C to +85°C
KS54AHCT: -55°C to +125°C
Input Rise & Fall Times. tr • tt ......... Max 500 ns
* Unused inputs must always be tied to an appropriate logic
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not im~ied. Long exposiJre to these conditions may affect device reliability.
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 1 0% Unless Otherwise Specified)
T.=25°C
Symbol Test Conditions
Typ
KS54AHCT
KS74AHCT
T.= -40°C to +85°C T.= - 55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
V,H
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V,L
0.8
0.8
. 0.8
V
Minimum High-Level
Output Voltage
VOH
V,N=V,H or V,L
lo=-20,.,A
lo=-4mA
Vee -0.1.
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
V,N=V,H or V,L
10=20,.,A
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
,.,A
Maximum Quiescent
Supply Current
lee
V'N=Vee or GND
lOUT = O,.,A
8.0
80.0
160.0
~.
2.7
2.9
3.0
rnA
1---'
Additional Worst
Case Supply
Current
per input in
V,=2.4V
~Iec other Inputs:
at Vee or GND
louT=O,.,A
c8SAMSUNG
• Electronics
Vee Vee -0.1
4.2
3.98
0
649
I
KS54HCTLS
KS74HCTLS
322A
8-Bit Shift Registers
with Sign Extend
AC ELECTRICAL CHARACTERISTICS
. Symbol
Characteristic
Condltlons t
(Input t"
TA=25°C
Vcc=5.0V
t,~6 ns), HCTLS322A
KS74HCTLS
KS54HCTLS
TA= -40°C to +85°C TA= -55°C to +12SoC
Unit
Vee = S.OV ± 10%
Vcc=S.OV± 10%
Typ
Maximum Clock Frequency
Maximum Propagation
Delay, Clock to QH I
f max
40
30
25
20
~
22
33
41
50
tpLH
22
33
41
50
27
35
44
53
Maximum Propagation
Delay, Clear to QH'
tPHL
Maximum Propagation
Delay, Clock to QA-QH
~
22
33
41
50
16
25
31
38
tpHL
22
35
44
53
~
15
35
44
53
15
35
44
53
tPZL
Clock Pulse
Width
I High
ILow
RL=1 kO
CL=50pF
15
25
31
38
tpu
15
25
31
38
tw
12
16
20
24
tw
12
16
20
24
~
Output Disable Time
CL=50pF
tpLH
Propagation Delay
Clear to QA-QH
Output Enable Time
#
Guaranleed Limits
Clear Pulse Width Low
tw
12
16
20
24
Minimum Data Set up Time
ts
13
16
20
25
Minimum Select Set up Time
ts
13
16
20
25
Minimum Data Hold Time
th
-3
0
0
0
Minimum Select Hold Time
th
7
10
12
15
20
25
30
Minimum Recovery Time
tree
15
Maximum Input Capacitance
Cin
5
Power Dissipation Capacitance
CPD
100
* CPD determines the no-load dynamic power dissipation: PD=CPD Vcc 2 f
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
MHz
ns
ns
ns
ns
ns
ns.
ns
ns
ns
ns
ns
pF
pF
+
Icc Vce.
650
KS54AHCT
KS74AHCT
352
Dual 4-Line to 1-Line Data
Selectors/Multiplexers
FEATURES
DESCRIPTION
• Inverting Version of '153
• Permits Multiplexing from N Lines t01 Line
• Performs Parallel-tOoSerial Conversion
Strobe (Enable) Line Provided for Cascading
(N Lines to n Lines)
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
(loL =24 mA @ VOL =O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to +85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
Each of these data selectors/multiplexers contains inverters
and drivers to supply fully complementary binary decoding
data selection to the AND-OR-invert gates. Separate strobe
inputs (G) are provided for each of the two four-line
sections.
PIN CONFIGURATION
LOGIC DIAGRAM
1<3
Vee
B
2G
lC3
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
2C3
1Cl
1CO
2C2
2C1
lY
2CO
GND
I
CD 161
A
1C2
'
I
1 _ _ _ _ _-+-++4-4.-/
lCl....:;15:c..
DATA 1
lC2 --'14""-1_ _ _ _---+-+-t--+-t---l.----./
2Y
lC3--'13-'-1--_ _--f-+-+-+---L---/
SELECT [
,'"
FUNCTION TABLE
" 1141
SELECT
B
A
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
·H
H
DATA INPUTS
STROBE
CO C1 C2 C3
G
y
H
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
H
L
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X.
L
H
2CD 1101
OUTPUT
2Cl 1111
uATA 2
2C2....:.ll""21C-.------l;:::j:==:t:l~1
1
----t=l===+=:r""l
2C3--,1.;..;;13,-1
26 (151
Select inputs A and B are common to both sections.
c8SAMSUNG
Electronics
651
KS54HCTLS
KS74HCTLS
352,
Dual 4-Line to 1-Line Data
Selectors/Multiplexers
Absolute Maximum Ratings·
o
Supply Voltage Range Vcc,
. -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI> Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±70 mA
Continuous Current Through
Vcc or GND pins. . . . . .
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vcc
Operating Temperature
·KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V+10%
Unless Otherwise Specified)
-
Ta=25°C
Test Conditions
Typ
I
I
KS74HCTLS
:
KS54HCTlS
T8 = -40°C to +85°C T8 = -55°C to + 125°C Unit
Guaranteed limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20j../A
10- 6mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20J-tA
10=12mA
'0 24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
J-tA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
j../A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.6.lcc
VIN=VCC or GND
10UT-0J-tA
per input pin
Vi=2.4V
other Inputs:
at Vcc or GND
10UT-0J-tA
c8SA~SUNG
ElectrOnics
Vcc Vcc -0.1
4.2
3.98
0
652
KS54HCTLS
KS74HCTLS
352
Dual 4-Line to 1-Line Data
Selectors/Multiplexers
AC ELECTRICAL CHARACTERISTICS
Symbol
Characteristic
(Input t r • t,.t;;6 ns). HCTLS352
T.=25°C
Vee=5.0V
Conditions!
KS74HCTLS
KS54HCTLS
T.= -40°C to +85°C T.= -55°C to ~125°C
Vce=5.0V:t 10%
Vee = 5.0V:t 10%
Typ
tpLH
Maximum Propagation Delay.
A or B to Y
1-------
----
Maximum Propagation Delay.
Data (Any C) to Y
f-------------
-
f-----
tpHL
1-----
tpLH
---
-----
Power Dissipation Capacitance *
-
CL=50pF
CL =150pF
30
33
38
43
45
51
23
26
30
33
38
43
45
51
19
21
26
29
32
37
39
45
32
37
_ .. _------
39
45
C-----
I
CL=50pF
CL =150pF
CL=50pF
CL =150pF
19
21
26
29
tpLH
CL=50pF
CL =150pF
19
21
26
29
~-
-- ------
-"
f-------
tpHL
-------
---
Guaranteed Limits
23
26
tpHL
Maximum Propagation Delay.
G to Y
,Maximum Input Capacitance
CL=50pF
CL =150pF
f------- - - - -
---
CIN
-----
CL=50pF
CL =150pF
----- --------
f---
-
--
~
32
37
39
45
32
37
39
45
---
19
21
- - - 1-----
Unit
26
29
5
f----t-
CPD
---"-----
ns
ns
~~
pF
---
pF
• CPD determines the no-load dynamic power dissipation: PD=CPD Vee l fin
t For AC switching test circuits and timing waveforms see section 2.
I
=8SAMSUNG
Electronics
653
353
KS54HCTLS
KS7·4HCTLS
Dual 1-01-4 Data' Selectors/Multiplexers
with 3-State Outputs'
FEATURES
DESCRIPTION
•
•
•
•
Each of these data selectors/multiplexers contains inverters
and drivers to supply full binary decoding data selection
to the AND-OR-invert gates. Separate strobe inputs (<3) are
provided for each of the two four-line sections.
•
•
•
•
•
Inverting Version of '253
Permits Multiplexing from N lines to 1 line
Performs Parallel-to-Serial Conversion
Function, pin-out, speed and drive compatibility with
54174LS logic family
Low power consumption characteristic of CMOS
3-State outputs with high drive current
(IOL 24 rnA @ VOL O.5V) for direct bus interface
Inputs and outputs interface directly with TTL, NMOS
and CMOS deviceS'
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to + 125°C
=
=
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
The three-state outputs can interface with and drive data
lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state) the lowimpedance of the Single enabled output will drive the bus
line to a high or low logic level. Each output has its own
strobe (G). The output is disabled when its strobe is high.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage 9ue to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAM
STROBE
1G (11
ENABLE
lG
Vee
B
2G
lC3
A
lC2
2C3
lCl
2C2
lCO
2Cl
lY
2CO
1CO...:;16:.:..1_ _ _ _ _ _-+-+-1~_
1C1 151
OUTPUT
1Y
1C2-'(4::!..1-------f-+-+-HH..-/
2Y
GND
1C3 (31
B 121
FUNCTION TABLE
A (141
SELECT
DATA INPUTS
OUTPUT
CONTROL
OUTPUT
2CO 1101
CO C1 C2 C3
G
y
2C1 1111
H
Z
L
L
L
L
L
L
L
L
H
B
A
X
X
X
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
X
X
X
H
X
X
L
X
X
X
X
X
X
X
L
H
2C2 1121
L
H
2C3 (131
L
H
L
STROBE _ (151
ENABLE 2G
H
L
Select inputs A and B are common to both sections.
c8SAMSUNG
Electronics
654
KS54HCTLS
KS74HCTLS
353
Dual 1-01-4 Data Selectors/Multiplexers
with 3-State Outputs
Absolute Maximum Ra.tings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu-rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V) .
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages*, VIN, VOUT
OV to Vee
Operating Temperature
·KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an ap:->ropriate logic
voltage level (either Vec or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vec=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
I
KS74HCTlS
KS54HCTlS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2_0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
f---
VOH
VIN=VIH or VIL
lo=-20/AA
" = -6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2O/AA
lo=12mA
lo-24mA
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/AA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
/AA
8.0
80.0
160.0
/AA
2.7
2.9
3.0
mA
Minimum High-Level
Output Voltage
I---
'----
Maximum Quiescent
Supply Current
f------'-------Additional Worst
Case Supply
Current
Icc
L1lee
VIN=Vee or GND
IOUT-O/AA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
.IOUT=O/AA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
655
I
Dual. 1-0'-4 Data Se/flctOlslMuUiplexers
with 3-State Outputs
.J.
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input t r , tf~6 ns), HCTLS353
KS74HCTLS
KS54HCTLS
T. =25°C T = -400C to +85°C T = -55°C to +125°C
Unit
Vcc-50V
• Vcc=5.0V::t10%
• Vcc=5.0V::t 10%
.
--
Typ
tpLH
24 32
27 35
40
45
48
54
tpHL
CL=50pF
CL =150pF
24 32
27 35
40
45
48
54
tpLH
CL=50pF
CL=150pF
15 20
18 23
25
30
30
36
tpHL
CL=50pF
CL=150pF
15 20
18 23
26
31
31
37
CL=50pF
17 23
CL=150pF 20 26
29
34
35
41
CL=50pF
17 23
CL=150pF 20 26
29
34
35
41
20 27
34
41
20 27
34
41
Maximum Propagation Delay,
A or B to Any Y
Maximum Propagation Delay,
Data (any C) to any Y
Maxim)!m Output Enable
Time, G to Y
tPZH
f---
RL=1 kO
tPZL
Maximum Output Disable
Time, G to Y
Maximum Input Capacitance
~
tpLZ
CIN
Maximum Output Capacitance COUT
Power Dissipation
Capacitance *
Guaranteed limits
CL=50pF
CL=150pF
RL=1 kO
CL=50pF
5
10
Cpo
ns
ns
ns
ns
pF
pF
pF
* Cpo determines the no-load dynamic power dissipation: PO=CPD VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMS.UNG
Electronics
656
KS54HCTLS
KS74HCTLS
365AI366A
367AI368A
~ Hex Bus-Drivers
~ 3-State Outputs
with
DESCRIPTION
FEATURES
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL = 24 rnA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These high-speed Hex bus drivers are designed specificaliy
to improve both the performance and denSity of 3-state
memory address drivers, clock drivers, and bus oriented
receivers and transmitters .
The '365 and '366 have two output enables (G1 and G2)
NOR'ed together to control all six gates. The '367 and
'368 have two output enables which are configured so that
one enable (G1) controls four gates and the other (G2) controls the remaining two gates. The '366 and '368 have inverting data paths. The '365 and '367 have noninverting
data paths.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
FUNCTION TABLES
PIN CONFIGURATION
Vee
A1
G2
f---
G1
A6
Y6
Y2
AS
A3
YS
Y3
A4
GND
Y4
Inputs
Y Outputs
Inputs
-~---
<32
A '365
I
'367 and '368
'365 and '366
<31
01
'366
L
L
H
L
L
L
H
L
H
H
L
X
X
H
X
X
Z
Z
Z
Z
----
L
L
H
Y Outputs
------~~--
'367
'368
L
H
L
H
H
L
X
Z
Z
& <32 A
LOGIC DIAGRAMS
'365
A1
Y1
Y1
Y2
Y2
Y3
Y3
Y4
-------'---' ....."'"'---Y4
YS
YS
Y6
Y6
<31
(1)
G2
G2
(lS)
c8SAMSUNG
Electronics
'368
Yl
Yl
----.-. __- - - -Y2
"'-J--
Y2
Y3
- - t · U I Q - - - Y3
>-_ _ Y4
_ - , - , __. . . , - - - Y4
YS
- - , - - , - , ~.r-- Y5
L .......- - - -
--,---r-ol ___, , - - -
Y6
Y6
Gl
G1-~---"
(lS)
'367
'366
657
KS54HCTLS
KS74HCTLS
365A/366A
36'7A/368A
Hex Bus-Drivers with
3-State Outputs
Absolute Maximum Ratings·
Supply Voltage Range Vee.
-0.5V to + 7V
DC Input Diode Current. hK
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current. 10K
(Va < -0.5V or Vo > Vee +0.5V)
±20 rnA
Continuous Output Current Per Pin. 10
(-O.5V < Vo < Vee +0.5V)
±70 rnA
Continuous Current Through
Vee or GND pins. .
±250 rnA
StorageTernperature Range. TSlg ... -65°C to +150o~
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vee
4.5V to 5.5V
DC Input & Output Voltages". VIN, VOUT .. OV to Vee
Operating Temperature
Range
-KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times. tr • tf
Max ·500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V± 1 0% Unless Otherwise Specified)
_~~74HCTLS
~=250C_
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20J.lA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20J.lA
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
J.lA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
IJ.A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
J.lA
--
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
61ee
VIN=Vee or GND
10uT=OJ.lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND.
10uT=OJ.lA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
658
KS54HCTLS
KS74HCTLS
365A/366A
367A/368A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
Hex Bus-Drivers with
3-State Outputs
(Input t r , tf~6 ns), HCTLS365A, HCTLS367 A
KS74HCTLS
KS54HCTLS
T. =25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vee=5.0V
Vee =5.0V:t: 10%
Vee=5.0V:t: 10%
Typ
tpLH
14 19
17 22
24
29
28
34
tpHL
CL =50pF
CL=150pF
14 19
17 22
24
29
28
34
CL=50pF
26 35
CL =150pF 29 38
44
49
52
58
CL=50pF
26 35
CL=150pF 29 38
44
49
52
58
26 35
44
52
26 35
44
52
Maximum Propagation Delay,
A to Y
tPZH
Maxim\Lm Output Enable
Time, G to Y
~
Maximum Output Disable
Guaranteed Limits
CL=50pF
CL=150pF
'-------
RL =1 kG
. tPZL
tpHZ
~
Time, G to Y
tpLZ
Maximum Input Capacitance
CIN
RL = 1 kG
CL=50pF
ns
ns
ns
5
pF
Maximum Output Capacitance COUT Output disabled
10
pF
Power Dissipation
Capacitance * (per driver)
5
30
pF
Cpo
G=Vcc
G=GND
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc' fin
t For AC switching test circuits and timing waveforms see section 2.
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input tr , tf~6 ns), HCTLS366A, HCTLS368A
KS74HCTLS
KS54HCTLS
T.=25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vee=5.0V
Vee=5.0V:t:10%
Vee=5.0V:t: 10%
Typ
tpLH
13 17
16 20
21
26
25
31
tPHL
CL=50pF
CL=150pF
13 17
16 20
21
26
25
31
CL=50pF
26 35
CL=150pF 29 38
44
49
52
58
CL=50pF
26 35
CL=150pF 29 38
44
49
52
26 35
44
52
26 35
44
52
Maximum Propagation Delay,
A to Y
tPZH
Maxim\Lm Output Enable
Time, G to Y
f----
RL =1 kG
tPZL
Maximum Output Disable
Time, G to Y
Guaranteed Limits
CL=50pF
CL=150pF
tpHZ
f----
tpLZ
RL = 1 kG
CL=50pF
ns
ns
58
ns
5
pF
Maximum Output Capacitance COUT Output disabled
10
pF
Power Dissipation
Capacitance * (per driver)
5
30
pF
Maximum Input Capacitance
CIN
Cpo
G=Vcc
G=GND
* Cpo determines the no-load dynamic power dissipation: PO=CPD,VCC' fin
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
659
I
KS54HCTLS
KS74HCTLS
373·.
Octal D-Type Transparent Latches
with 3-State Outputs
FEATURES
DESCRIPTION
• 8 latches in a single package
• Full parallel access for loading
• Function, pln-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOl 24 rnA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '373 cons-ists of 8 high-speed Ootype latches coupled to 3-state output buffers with high drive current capability. It can be used in implementing buffer registers, I/O ports,
bidirectional bus drivers and working registers.
=
The latches are transparent: when the enable (E) is high,
the outputs follow the data (0) inputs. When the enable
is low, the outputs latch at the levels that were set up at
the 0 inputs.
a
=
The output buffers are controlled by a common Signal (OC)
which places the outputs at a high-impedance state when
it is taken high. The OC signal does not affect the internal
operations of the latches. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
PIN CONFIGURATION
FUNCTION TABLE
6C
Vee
10
10
20
80
80
70
70
60
60
50
50
20
30
3D
40
40
(Each Latch)
Inputs
E
GNO
Output
OC
E
0
Q
L
L
L
H
H
H
L
H
X
X
00
H
L
X
L
Z
LOGIC DIAGRAM
10
20
10
c8SAMSUNG
-=I __ ..__:-~
3D
40
50
60
7D
80
20
30
40
50
60
70
80
660
KS54HCTLS
KS74HCTLS
373
Octal 0-Type Transparent Latches
with 3..State O.utputs
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -O.SV or VI> Vee +O.SV)
±20 mA
DC Output Diode Current, 10K
(Vo < -O.SV or Vo > Vee +O.SV)
±20 mA
Continuous Output Cu-rrent Per Pin, 10
(-O.SV < Vo < Vee +O.SV)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, TSl9 ... -6SoC to +1S0°C
Power Dissipation Per Package, Pdt
SOO mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 6SoC to 8SoC
Recommended Operating Conditions
Supply Voltage, Vee
4.SV to S.SV
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
KS74HCTLS: -40°C to +8SoC
Range
KSS4HCTLS: -S5°C to +12SoC
Input Rise & Fall Times, t r , tf
Max SOO ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 1 0% Unless Otherwise Specified)
TA=25°C
Test Conditions
KS54HCTLS
KS74HCTLS
TA= -40°C to +85°C TA= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0_33
0.5
OA
V
Minimum High-Level
Output Voltage
VOH
VIN = VIH or VIL
10=-20f.lA
10=-6mA
Maximum Low-Level
Output Voltage
VOL
VIN = VIH or VIL
10=20f.lA
10=12mA
10=24mA
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0'
±1.0
f.lA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vee or GND
±O.S
±5.0
±10.0
f.lA
Maximum Quiescent
Supply Current
Icc
VIN=Vee or GND
10ur=OfAA
8.0
80.0
160.0
fAA
per input pin
Vz=2.4V
Other Inputs:
At Vee or GND
10=0
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
l::.lee
=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
0.1
--t--
661
I
KS54HCTLS
KS74HCTLS
373
OctalD-Type Transparent Latches
with 3-State Output
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Condltlons l
(Input'tr , tl<;6 ns), HCTLS373
KS74HCTLS
KS54HCTLS
T.=25°C T.= -400C to +85°C T.= -55°C to +125°C
Unit
Vee=5.0V
Vee =5.0 V::!: 10%
Vee=5.0V::!: 10%
Typ
Maximum Propagation Delay,
D to Q
tPLH
14 18
17 21
23
28
27
33
tPHL
CL=50pF
CL=150pF
14 18
17 21
23
28
27
33
CL~50pF
CL=150pF
22 30
25 33
37
42
45
51
CL=50pF
CL=150pF
22 30
25 33
37
42
45
51
24 32
CL=50pF
CL =150pF 27 35
40
45
48
54
CL =50pF
24 32
CL=150pF 27 35
40
45
48
54
~
tpLH
Maximum Propagation Delay,
E to any Q
Guaranteed Limits
CL= 50pF
CL""150pF
tpHL
--
tPZH
Maximum Output Enable
Time, OC to any Q
-
Maximum Output Disable
Time, OC to any Q
1----:-
RL=1kO
tpzL
tPHZ
tpLZ
RL=1kO
CL=50pF
19 25
31
37
19 25
31
37
ns
ns
ns
ns
Minimum Pulse Width,
E High
tw
6
10
12
15
ns
Minimum Setup Time,
D before E.
tsu
2
3
4
5
ns
Minimum Hold Time,
D after E.
th
6
10
12
15
ns
--
f-------
f---
Maximum Input Capacitance
10
Power Dissipation
Capacitance * (per latch)
5
30
Cpo
OC=Vcc
OC=GND
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee'
t For AC switching test circuits and timing waveforms see section 2_
c8SAMSUNG
Electronics
pF
5
CIN
Maximum Output Capacitance COUT Output Disabled
-----
pF
pF
fin
662
KS54HCTLS
KS74HCTLS
374
Octal O-Type Flip-Flops
with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(tOl 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '374 consists of 8 high-speed D-type edge-triggered
flip-flops coupled to 3-state output buffers with high drive
current capability. It can be used in implementing buffer
registers, 1/0 ports, bidirectional bus driver and working
registers.
=
=
The flip-flops are edge-triggered on the positive transition
of the clock. The Q outputs are set to the logic levels that
were set up at the D inputs.
The output buffers are controlled by a common signal (OC)
which places the outputs at a high-impedance state when
it is taken high. The OC signal does not affect the internal
operations of the flip-flops. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to their lSTTl counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATION
oc
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
Vee
10
80
80
10
20
20
30
30
40
40
50
GNO
elK
I
FUNCTION TABLE
70
70
(Each Flip-Flop)
60
60
Output
Inputs
50
OC ClK D
L
L
L
H
t
t
H
L
X
X
X
L
a
H
L
Qo
Z
LOGIC DIAGRAM
10
20
30
40
50
60
7D
80
10
20
30
40
50
60
70
elK
oe
c8SAMSUNG
Electronics
80
663
KS54HCTLS
KS74HCTLS
374:
""." .
Octal D-Type Flip-Flops
with 3-State Outputs
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ....... -O.5V to + 7V
DC Input Diode Current, hK
(VI < -O.5V or VI > Vee +O.5V) . .
±20 mA
DC Output Diode Current, 10K
(Vo< -O.5V or Vo > Vee +0.5V) . .. ±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND p.ins . . .
±250 mA
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee .
. . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
·KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times., t r , tf ..
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
* Absolute Maximum Ratings are those values beyond
whieh permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V±10% Unless OtherwisQ Specified)
Ta =25°C
KS74HCTLS
Ta
= - 40°C to
KS54HCTlS
+ 85°C Ta = - 55°C to + 125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
t:..lee
VIN=Vee or GND
10uT=0,.,A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
---
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
664
KS54HCTLS
KS74HCTLS
374
Octal D-Type Flip-Flops
with 3-State Outputs .~
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input tr , tf~6 ns). HCTlS374
Symbol Conditions t
KS14HCTLS
KS54HCTLS
T. =25°C
T.=-40°Cto +85°C T. =-55°C to +125°C
Unit
Vcc=5.0V
Vec=5.0V:t10%
Vee = 5.0V:t 10%
Typ
Maximum Operating Frequency
Maximum Propagation Delay,
ClK to any Q
Guaranteed limits
f max
CL=50pF
45 35
30
25
tPLH
CL=50pF
CL =150pF
21 28
24 31
35
40
42
48
tpHL
CL=50pF
CL=150pF
21 28
24 31
35
40
42
48
21 28
24 31
35
40
42
48
21 28
CL=50pF
CL=150pF 24 31
35
40
42
48
tPZH
Maximum Output Disable
Time, OC to any Q
r - - RL =1 kG
MaxImum Output Disable
Time, OC to any Q
I--
tPZL
tPHZ
tpLZ
CL=50pF
CL=150pF
RL=1kO
CL=50pF
19 25
31
37
19 25
31
37
MHz
ns
ns
ns
Minimum Pulse Width,
ClK High or low
tw
7 10
12
15
ns
Minimum Setup Time,
D before ClKt
tsu
10 13
17
20
ns
Minimum Hold Time,
Dafter ClKt
th
-3
0
0
ns
Maximum Input Capacitance
0
5
pF
Maximum Output Capacitance COUT Output Disabled
10
pF
Power Dissipation
Capacitance· (per stage)
5
30
pF
CIN
Cpo
OC=Vcc
OC=GND
* CPO determines the no·load dynamiC power dissipation: Po=Cpo VCC 2
fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
665
I
KS54HCTLS
KS74HCTLS
377
Octal O-Type Flip-Flops
with Clock Enable
FEATURES
DESCRIPTION
• Can be used for implementing
- BufferlStorage Registers
- Shift Registers
- Pattern Generators
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10l =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '377 contains eight positive·edge-triggered Ootype flipflops with an enable input. This part is similar to '273 but
features a latched clock enable (<3) instead of a common
clear.
Information at the 0 inputs meeting the setup time reo
quirements is transferred to the 0 outputs on the positivegoing edge of the clock pulse if Gis low. Clock triggering
occurs at a particular voltage level and is not directly related
to the transition time of the positive-going pulse. When the
clock input is at either the high or low level, the 0 input
signal has no effect at the output. The circuits are designed to prevent false clocking by transitioins at the G input.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
PIN CONFIGURATION
FUNCTION TABLE
G
Vee
10
10
20
80
20
30
30
40
40
GNO
(EACH FLIP-FLOP)
80
70
70
60
60
50
50
elK
INPUTS
G
CLK
DATA
OUTPUT
Q
H
L
L
X
t
t
X
00
H
L
H
L
X
L
X
00
LOGIC DIAGRAM
dCSAMSUNG
• • Electronics
666
KS54HCTLS
KS74HCJ"LS
377
Octal D-Type Flip-Flops
with Clock Enable
Absolute Maximum Ratings*
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vce or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
f----,--'
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
I1A
VOH
VIN=VIH or VIL
lo=-20/AA
lo=-4mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2O /AA
lo=4mA
10=8mA
Maximum Input
Current
hN
VIN=Vce or GND
Maximum Quiescent
Supply Current
lec
Minimum High-Level
Output Voltage
Additional Worst
Case Supply
Current
Vee Vee -0.1
3.98
4.2
0
_._--
Dolee
VIN=Vee or GND
10UT=0/AA
per input pin
VI=2.4V
other Inputs:
at Vec or GND
10uT=011A
c8SAMSUNG
Electronics
8.0
80.0
160.0
/AA
2.7
2.9
3.0
mA
667
I
KS54HCTLS
KS74HCTLS
377
Octal D-Type Flip-Flops
with Clock Enable
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r , tf~6 ns), HCTlS377
KS74HCTLS
KS54HCTLS
Ta =25°C
T.= -40°C to +85°C T. = -55°C to +125°C
Symbol Condltionst Vcc=5.0V
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Maximum Clock Frequency
Maximum Propagation Delay,
ClK to Any Q
Minimum
Pulse Width
*
t
Glow
ClK high or low
Guaranteed Limits
f max
45 35
30
25
~
18 27
32
38
18 27
32
38
12 16
20
25
12 16
20
25
6 10
15
20
15 20
25
25
0
0
tPHL
tw
Data
Minimum Setup
Time before ClKt G high or lOW
tsu
Minimum Hold Time,
Data after ClKt
th
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
CL=50pF
-3
0
5
Cpo determines the no-load dynamic power dissipation: Po=Cpo Vec 2
For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
MHz
ns
ns
ns
ns
pF
pF
fin.
668
KS54HCTLS
KS74HCTLS
390
Dual 4-Bit Decade Counters
FEATURES
DESCRIPTION
• Individual clock for A and B flip-flops provide dual + 2
and + 5 counters
• Direct clear for each 4-bit counter
• Significant provement in system density through
reduced counter package count.
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
Vee
2CKA
These devices incorporate dual divide-by-two and dividefive counters, which can be used to implement cycle
lengths equal to any whole and/or cumulative multiple of
2 and/or 5 up to divide-by-1 00. When conneoted as a biquinary counter, the ~eparate divide-by-two circuit can be
used to provide symmetry (a square ware) at the final outpur stage. The '390 incorporates dual divide-by-two and
divide-by-five counters, which can be used to implement
cycle lengths equal to any whole and/or cumulative
multiples of 2 and/or 5 up to divide-by-1 00. When connected as a bi-quinary counter, the separate divide-by-tow
circuit can be used to provide symmetry (a square wave)
.at the final outpur stage. The '390 has parallel outputs from
each counter stage so that any submultiple of the input
count frequency is available for system-timing signals.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
2CLR
20 A
2CKB
200
lOe
100
20 e
GND
200
FUNCTION TABLES
BIQUINARY (5-2)
( Each Counter)
(See Note B)
BCD COUNT SEQUENCE
( Each Counter)
(~ee Note A)
OUTPUT
COUNT
0
1
2
3
4
5
6
7
8
9
OUTPUT
COUNT
Qo
Qc
QB
QA
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
8
9
Qo
Qc
Qs
QA
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
NOTES A. Output QA is connected to input CKB for BCD count.
B. Output QD is connected to input CKA for biquinary count.
c8SAMSUNG.
Electronics
669
I
KS54HCTLS
KS74HCTLS
390
Dua/4-Blt Decade Counters
LOGIC DIAGRAM
CKA
(1.15)
CLEAR
Oe (5. 11) Oe
CKB~~·_12~)+-____________~~~
Absolute Maximum Ratings·
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vce +0.5V)
±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Vo > Vce +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vec +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
±125 mA
Storage Temperature Range, T5 1g ..• -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
=8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
670
KS54HCTLS
KS74HCTLS
390
Dual 4-Bit Decade Counters
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Test Conditions
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20jiA
lo=-4mA
Vce -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2O/lA
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vce or GND
±0.1
±1.0
±1.0
/lA
Maximum Quiescent
Supply Current
lec
8.0
80.0
160.0
/lA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
!llee
VIN=VCC or GND
louT=O/l~ __
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
louT=O/lA
Vee Vcc -0.1
4.2
3.98
0
AC ELECTRICAL CHARACTERISTICS
Characteristic
(Input t r , tf~6 ns), HCTLS390
KS74HCTLS
KS54HCTLS
Ta =25°C
Ta= -40°C to +85°C Ta=-55°C to +125°C
Symbol Conditions t Vcc=5.0V
Unit
Vcc=5.0V:!:10%
Vcc=5.0V:!: 10%
Typ
Maximum Clock Frequency
CKA to QA or CKB to QB
*
t
Guaranteed Limits
f max
35
25
20
20
tpLH
15 20
25
30
tpHL
15 20
25
30
tpLH
36 48
60
72
tpHL
36 48
60
72
Maximum Propagation Delay,
CKA to QA
I---
Maximum Propagation Delay,
CKA to Qc
I---
Maximum Propagation Delay,
CKB to QB
I---
Maximum Propagation Delay,
CKB to Qc
I---
Maximum Propagation Delay,
CKB to QD
I---
tpHL
Maximum Propagation Delay,
CLR to Any Q
tpHL
16 21
26
31
tpHL
16 21
26
31
tpLH
24 32
40
48
tpHL
24 32
40
48
16 21
26
31
16 21
26
31
24 32
40
48
12 16
20
24
12
16
20
24
15 20
25
30
tpLH
tpLH
ICKA or CKB high or low
Minimum
Pulse Width I CLR high
tsa
Minimum Setup Time,
CLR inactive before CKA or CKB
tsu
Maximum Input Capacitance
CIN
Power Dissipation Capocitance
CpD
CL =50pF
r-----r-
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
CPD determines the no-load dynamic power dissipation: Po=Cpo VCC' fin.
For AC switching test circuits and timing waveforms see section 2.
dCSAMSUNG
• • Electronics
671
I
KS54HCTLS 3";·.~
KS74HCTLS ,.!~,.
,
Dual4~bit
Binary Counters
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54[74LS logic family
• Low power consl,lmption characteristic of CMOS
• High-Drive-Current outputs:
IOL =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '393 consists of two independent 4·bit binary counters
each with its own clear and clock inputs. N-bit binary
counters can be implemented with each package providing
the capability of divide-by-256. Parallel outputs from each
counter stage provide any submultiple of the input count
frequency for system timing Signals.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
LOGIC DIAGRAMS
PIN CONFIGURATION
CLK
-~----i"
Vee
lCLK
1 CLR
2CLK
lOA
2CLR
10e
20A
10e
20e
lao
20e
GNO
200
as
Qc
LOGIC TIMING WAVEFORMS
I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
10
I
11
I
12
I
13
I
14
I
15
I
0
I
CLK
CLR
Jl__________________________________________
OA
08
J
Oe
J
aD
]
c8SAMSUNG
Electronics
L
L
L
672
KS54HCTLs
KS74HCTLS
393
Dual 4-bit Binary Counters
Absolute Maximum Ratings *
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±35 mA
Continuous Current Through
Vee or GND pins
± 125 mA
. Storage Temperature Range, T5 tg . . . -65°C to +150°C
Power Dissipation Per Package, Pdt. . . .
500 mW
Recommended Operating Conditions
Supply Voltage, Vcc
.......... 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf ....
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Vee=5V± 1 0% Unless Otherwise Specified)
~.
Characteristic
Symbol
Ta =25°C
Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
lo=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
±0.1
±1.0
±1.0
",A
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Maximum Quiescent
~y Current
Additional Worst
Case Supply
Current
lee
.6.lee
Vee Vee -0.1
4.2
3.98
0
VIN=Vee or GND
VIN=Vee or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
c8SAMSUNG
Electronics
!
673
I
KS54HCTLS
KS74HCTLS
393
Dual 4-bit Binary Counters
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input tr , tf~6 ns), HCTlS393
KS74HCTLS
KS54HCTLS
T. =25°C
T.=-40°Cto +85°C T. = -55°C to +125°C
Vcc=5.0V
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Guaranteed Limits
Maximum Clock Frequency
f max
40 30
25
20
Maximum Propagation Delay,
A to QA
tpLH
15 20
25
30
;------
tpHL
15 20
25
30
Maximum Propagation Delay,
A to Qs
-
tPLH
26 35
44
53
tpHL
26 35
44
53
CL=50pF
Maximum Propagation Delay,
A to Qc
~
34 45
56
67
tpHL
34 45
56
67
Maximum Propagation Delay,
A to Qo
~
45 60
75
90
tpHL
45 60
75
90
Maximum Propagation Delay,
ClR to any Q
tpHL
29 39
49
58
I
Minimum Pulse A Input High or low
Width
IClR High
tw
Minimum Hold Time,
ClR Inactive before A
tsu
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
(per counter)
10 13
17
20
10 13
17
20
10 13
17
20
MHz
ns
ns
ns
ns
ns
ns
ns
5
pF
40
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
674
KS54HCTLS
KS74HCTLS
399
.
Quad 2-Port Registers
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Driv.current outputs:
IOL =8 rnA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These are high-speed quad 2-port registers. They are the
logical equivalent of a quad 2-input multiplexer followed by
a quad 4-bit edge-triggered register. A common select input (SELl selects between two 4-bit input ports. The
selected data is transferred to the output register on the
low-to-high transition of the clock input.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
FUNCTION TABLE
Inputs
Output
SEL
Vee
OA
OD
SEL
Port 1
Port 2
1A
10
20
I
I
X
L
28
2C
I
h
X
H
18
1C
h
X
I
L
h
X
h
H
2A
Os
GNO
Q
Oe
ClK
I
h
c8~SUNG
= Low Voltage Level one setup time prior to the low-to-high
=
clock transition
High Voltage Level one setup time prior to the low-to-high
clock transition
675
I
KS,54HCTLS399
KS74HCTLS
Quad 2-Port Registers
LOGIC DIAGRAM
CLK~(9~)
____________________~
Absolute Maximum Ratings·
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, hK
(V, < -0.5V or V, > Vee +0.5V) ... " ±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Va > Vcc +0.5V) .... ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vce +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins ................ ±125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
.. Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
'
EI~Qtronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages", V'N, VOUT .. OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55 ° C to + 1 25 ° C
Input Rise & Fall Times, tr • tf
.. Max 500 ns
Unused inputs must always be tied to
voltage level (either Vce or GND)
an appropriate logic
676
KS54HCTLS
KS74HCTLS
39.9
Quad 2-Port Registers
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V±10% Unless Otherwise Specified)
't.=25°C
Symbol Test Conditions
KS74HCTLS
KS54HCTLS
T.= -40°C to +85°C T.= -55°C ~o +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20",A
lo=-4mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20",A
lo=4mA
lo=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
t:..lee
Vee Vee -0.1
3.98
4.2
0
VIN=Vee or GND
louT=O",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
louT=O",A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
Ta =25°C
Vcc=5.0V
KS74HCTLS
Ta= -40°C to +85°C
Vcc=5.0V±10%
Typ
Guaranteed Limits
45
tPHL
22 30
37
45
tw
10 13
17
20
CL=50pF
Unit
.•
37
r-----
Minimum Pulse Width,
KS54HCTLS
Ta= -55°C to +125°C
Vcc=5.0V± 10%
22 30
tpLH
Propagation Delay,
, CLK to Q or Q
I
(Input tr , tf~6 ns), HCTLS399
ns
ns
CLK High or Low
Data
Minimum Setup
Time.before CLKt
Word Select
Minimum Hold
Time after CLKt
Word Select
Data
Maximum Input Capacitance
tsu
th
CIN
10 13
17
20
10 13
17
20
-3
0
0
0
-3
0
0
0
c8SAMSUNG
Electronics
I'IS
pF
5
pF
Power Dissipation Capacitance *
Cpo
* Cpo determines the no-load dynamic power dissipation: PO=CPD Vee'
t For AC switching test circuits and timing waveforms see section 2.
ns
fin.
677
KSS4HCTLS
KS74HCTLS
423
Dual,Retriggerable'Monostable '
Mullivibrator wlth,j'Clear
" "
FEATURES
DESCRIPTION
• Simple pulse width formula tw = 0.45RC
• DC triggered from active HIGH or active Low Inputs
• Retrlggerable for very long output pulses up to 100 %
duty cycle
• Overriding clear terminates output pulse
• SchmlH trigger A & B Inputs allow infinite rise and
fall times on these Inputs
• Functions, plrH)ut, speed and drive compatlvllity with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High drive current outputs:
IOL=8mA @ VOL=0.5V
• Inputs and outputs Interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range; 4.5V to 5.5V
• Characterized for operation over industrial and
rnilitary temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
The '423 contains dual retrigg~rable monostable,
mUltivibrators with output pulsewidth control by two
methods. The basic pulse time is programmed by selec·
tion of an external resistor (REXT) and capacitor (CEXT). The
external reSistor and capacitor are normally connected as
shown timing component.
Once triggered, the basic output pulse width may be extended by retriggering the gated active Low-going edge
input (Ai) or the active High-going edge input (8i). 8y
repeating this process, the output pulse period (nQ=HIGH,
nQ=LOW) can be made as long as desired.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques.
The output pulse equation is simply;
tw=O.45XREXTXCEXT(typ).
Where tw is in seconds. R is in ohm. and C is in fards.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATION
FUNCTION TABLE
Inputs
, A1
81
CLR1
0"1
02
C exT2
ReXT2/CeXT
Vee
RexTl/CeXT
C exTI
01
0"2
-ei:R2
A
B
Q
Q
L
X
X
H
H
X
H
X
L
+
X
X
L
t
H
L
L
L
n..
H
H
H
1S
...f1.
1S
82
A2
c8SAMSUNG
Electronics
Outputs
CLR
H=
L=
X=
t=
+=
Jl.=
"l..f=
HIGH voltage level
LOW voltage level
don't care
LOW to HIGH transition
HIGH to LOW transition
one HIGH level output pulse
one LOW level output pulse
678
KS54HCTLS
KS74HCTLS
423
Dual Retriggerable Monostable
Multivibrator with Clear
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Supply Voltage Range Vee, .... , .......... -0.5V to +7V
DC Input Diode Current, hK
(VI<-0.5V or VI>Vee+0.5V) ................. ±20 mA
DC Output Diode Current, 10k
(Vo<-0.5V or Vo>Vee+0.5V) ............... ±20 mA
Continuous OUtput Current Per Pin, 10
(-0.5V--+-""-Yl
>--~:L..Y2
A3
__--.--Y3
A4
>--+~Y4
>--j-!-!-!.l..Y5
__- - . - - Y 6
__--.--Y7
AS
>--....!..!.!.L-Y6
=8SAMSUNG
Electronics
, 681
I
·
'4651466
68'
Octa/Buffers and Line Drivers
with 3-8tate Outputs'
KS54.HCTLS '46',' '7/, A,'
KS74HCTLS '. ,1/""
, Absolute Maximum Ratings*
Supply Voltage Range Vcc, : ...... -0.5V to + 7V
DC, Input Diode Current, irK
(VI < -0.5V or VI > Vcc +0.5V) . . . .. ±20 mA
DC Output Diode Current, 10K
(Vo <-0.5Vor Vo > Vcc +0.5V) .... ±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vcc +0.5V) ......... ±70 mA
Continuous Current-Through
Vcc or GND pins ................ ±250 mA
Storage Temperature Range, T5 1g . . . -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
Recommended Operating Conditions
Supply Voltage, Vcc .............. 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vcc
Operating Temperature
Range
·KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55 ° C to + 1 25 ° C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V±10% Unless Otherwise Specified)
T8 =25°C
Typ
KS74HCTLS
KS54HCTLS
T8= -40°C to +85°C T8= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
Vee -0.1
3.84
Vce -0.1
3.7
V
VIN=VIH or VIL
10=-20~A
10= -6mA
Vcc Vce -0.1
4.2
3.98
VIN=VIH or VIL
Maximum Low-Level
Output Voltage
VOL
Maximum Input
Current
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
liN
VIN=Vec or GND
±0.1
±1.0
±1.0
~A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
~A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
~A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Iee
10=20~A
VIN=Vec or GND
10uT=0~A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
0
10uT=0~A
c8SAMSUNG
Electronics
682
KS54HCTLS
KS74HCTLS
4651466
4671468
AC ELECTRICAL CHARACTERISTICS
Octal Buffers and Line Drivers"
with 3-State Outputs
tf~6 ns), HCTLS465, HCTLS466,
(Input t r ,
HCTLS467, HCTLS468
Characteristic
54174ACHT
KS74HCTLS
54HCTLS
T.=25°C T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5V%10%
Vcc=5.0V% 10%
Vcc=5V
Symbol Conditions
Typ
Maximum Propagation Delay,
A to Y
Maximum Output Enable Time,
Enable to Y
tpLH
11
14
15
18
19
24
22
28
tpHL
CL=50pF
CL =150pF
11
14
15
18
19
24
22
28
CL=50pF
CL=150pF
24
27
32
35
40
45
48
54
CL=50pF
CL =150pF
24
27
32
35
40
45
48
54
24
32
40
48
24
32
40
48
tPZH
RL=1kO
tPZL
Maximum Output disable Time, tpHZ RL=1kO
r-------Enable to Y
tpLZ CL=50pF
Maximum Input Capacitance
Guaranteed Limits
CL=50pF
CL=150pF
CIN
Maximum Output Capacitance COUT Output Disabled
Output Disabled
Power Dissipation
Cpo
Output Enabled
Capacitance * (per stage)
ns
ns
ns
4
pF
10
pF
5
30
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo
VCC 2
fin.
t For AC switching test circuits and timing waveforms see section 2.
I
c8SAMSUNG
Electronics
.
683
5181519
~~~:~g~t~ 52015211522
8-SIt Identity Cotpparators·
FEATURES
DESCRIPTION
• Compares two 8-blt words
• '518, '520 and '522 have 20KOPull-up resistors on
Q inputs
These identity comparators perform comparisons on two
eight-bit binary or BCD words. The '518 and '519 provide
P=O outputs, while the '520, '521, and '522 provide P=O
outputs. The '518, '51 9, and '522 have open-drain
outputs. The '518, '520, and '522 feature 20-kQ inputs
for analog or switch data.
TYPE
INPUT
PULL-UP
RESISTOR
'518
Yes
OUTPUT FUNCTION
AND
CONFIGURATION
P=O open-drain
'519
No
P=O open-drain
'520
Yes
P = 0 totem-pole
'521
No
P =0 totem-pole
'522
Yes
P=O open-drain
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• 3-8tate outputs with high drive current
(lOL =24 mA @ VOL =0.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface:with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
FUNCTION TABLE
PIN CONFIGURATION
INPUTS
Vee
P=Q/P=Ot
Q7
P1
P7
Q1
Q6
DATA
P, Q
OUTPUTS
ENABLE
G
P=Q
P=Q
P=O
L
H
L
L
P2
P6
P>O
L
H
Q2
05
P-'
P2 --'-'-'---I
~~
01-----. ....~
I
G~~~=>-------------~
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, Tsig . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -1,2mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vee
Operating Temperature
·KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
685
, 5181519
~~~g~t~ 52015211522
DC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
(Vee=5V=10% Unle.ss Otherwise Specified)
T. =2S DC
Test Conditions
8-Bit Identity
Comparators
Typ
KS74HCTLS
TA
= _40DC to
KS54HCTLS
+8S DC T.= -5S DC to +12S DC Unit
Guaranteed L1mltt
Minimum High-level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum low-level
Input Voltage
VIL
.0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
(Totem-pole Outputs)
VOH
VIN=VIH or VIL
lo=-20JAA
lo=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
VOL
VIN=VIH or Vil
lo=20JAA
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
Vee=Max
VIN=2.7V
VIN'=0.4V
-0.2
-0.6
-0.2
-0.6
-0.2
-0.6
±0.1
±1.0
±1.0
JAA
±0.5
±5.0
±10.0
JAA
3.5
3.5
3.5
rnA
8.0
80.0
160.0
fAA
2.7
2.9
3.0
mA
Maximum Low-Level
Output Voltage
(All Outputs)
Maximum Inpul
Current,
(,518, '520 and '522
o input)
I
0
V
mA
-
Maximum Input
Current
(All other Inputs)
liN
VIN=Vee or GND
Maximum Output
Leakage Current
(Open-Drain Outputs)
loz
VIN=VIH or VIL
Vour = Vee
Maximum
Icc
~uiescent
Supply Current
Additional Worst
Case Supply
Current
Vee Vee -0.1
4.2
3.93
I
I
~Iee
For '518, '520 and
'522:
V'N=GND (00-07)
VIN=Vee or GND
(all other inputs)
For '519 and '521:
VIN=Vee or GND
lour=OJAA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour=OJAA
c8SAMSUNG
Electronics
686
KS54HCTLS
KS74HCTLS
5181519
52015211522
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions
8-Bit Identity
Comparators
(Input t r • tfoEi;6 ns). HCTLS518. HCTLS519
54/74ACHT
T. =25°C
Vcc=5V
54HCTLS
KS74HCTLS
T. = -40°C to +85·C T.=-55°Cto +125°C
Unit
Vcc=5V±10%
Vcc=5.0V± 10%
Typ
Maximum Propagation Delay.
from P or Q to P=Q
Maximum Propagation Delay.
from G to P=Q
tpLH
26
29
33
36
40
45
47
53
tPHL
CL=50pF
CL =150pF
21
24
28
31
35
40
42
48
tpLH
C=50pF
CL=150pF
23
26
29
32
35
40
41
47
tPHL
CL=50pF
CL=150pF
18
21
24
27
30
35
36
42
Maximum Input Capacitance
Maximum Output Capacitance
Power Dissipation Capacitance *
5
CIN
Maximum Propagation Delay.
from G to P=Q
pF
Cpo
pF
Symbol Cond"lons
(Input t r • tfoEi;6 ns). HCTLS520. HCTLS521
54/74ACHT
T.=25°C
Vce=5V
KS74HCTLS
54HCTLS
T. = -40°C to +85°C T.=-55°Cto +125°C
Unit
Ycc=5.0Y:!: 10%
Vcc=5V:!:10%
Guaranteed Limits
tpLH
CL=50pF
CL=150pF
12
15
22
25
28
33
33
39
tpHL
CL=50pF
CL =150pF
16
19
22
25
28
33
33
39
tPLH
C=50pF
CL=150pF
15
18
20
23
25
30
30
36
tPHL
CL=50pF
CL=150pF
15
18
20
23
25
30
30
36
Maximum Input Capacitance
5
CIN
ns
ns
pF
Maximum Output Capacitance
COUT
pF
Power Dissipation Capacitance *
Cpo
pF
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions
(Input t r • tf~6 ns). HCTLS522 ~
54/74ACHT
T.=25°C
Ycc=5Y
T.
t Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
. Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range,Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): --12mW/oC from 65°Cto 85°C
Recommended Operating Conditions
Supply Voltage, Vee . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55 ° C to + 1 25 ° C
Input Rise & Fall Times, t r , t,
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or b~yond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
..
Characteristic
Symbol
(Vec=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VOH
VIN=VIH or VIL .
10=-20/AA
10=-6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/AA
10=12mA
10=24mA
Maximum Input
Current
liN
VIN=Vce or GND
±0.1
±1.0
±1.0
/AA
Maximum 3-State
Leakage Current
102
Output Enable
=VIH
VouT=Vec or GND
±0.5
±5.0
±10.0
/AA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/AA
2.7
2.9
3.0
mA
Minimum High-Level
Output Voltage
f-
Additional Worst
Case Supply
Current
L\lee
VIN=Vce or GND
10UT=0/AA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0/AA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
689
I
KS54HCTLS
KS74HCTLS
533
OctalD-Type Transparent Latches
with 3~S~ate Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Condltlons t
(Input tr , tf~6 ns), HCTLS533
KS74HCTLS
KS54HCTLS
T. =25°C
T. = -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.OV
Vcc=5.OV:t::10%
Vcc=5.OV:t:: 10%
Typ
Maximum Propagation
Delay, D to
a
Maximum Propagation
Delay E to
a
tPlH
14
17
18
21
23
28
27
33
tPHl
Cl=50pF
CL=150pF
14
17
18
21
23
28
27
33
tplH
C=50pF
Cl=150pF
22
25
30
33
37
43
45
41
tpHl
CL=50pF
CL=150pF
22
25
30
33
37
43
48
54
24
27
32
35
40
45
48
54
24
27
32
35
40
45
48
54
19
25
31
37
19
25
31
37
Cl=50pF
tPZH
Maximum Output Enable
CL=150pF
I------ Rl=1kO
Time, OC to any
CL=50pF
tPZl
Cl=150pF
a
Maximum Output Disable
Time, OC to any
a
Guaranteed Limits
Cl=50pF
Cl=150pF
~
tpl!Z
Rl=1kO
Cl=50pF
ns
ns
ns
ns
Minimum Pulse Width,
E High
tw
6
10
12
15
ns
Minimum Setup Time,
D before E~
tsu
2
3
4
5
ns
Minimum Hold Time,
D after E~
tn
6
10
12
15
ns
CIN
5
pF
Maximum Input
Capacitance
Maximum Output
Capacitance
COUT
Output Disabled
10
pF
Power Dissipation
Capacitance· (per stage)
Cpo
OC=Vcc
OC=GND
5
30
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 1 fin.
t
For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
690
KS54HCTLS
KS74HCTLS
534
Octal 0-Type Flip-Flops
with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74lS logic family .
• low power consumptio.n characteristic of CMOS
• 3-State outputs with high drive current
(Iol = 24 mA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline'·' packages
(Available Tape & Reel), standard DIPs.
The '534 consists of 8 high-speed D-type edge-triggered
flip-flops coupled to 3-state output buffers with high drive
current capability . It can be used in implementing buffer
registers, I/O ports, bidirectional bus driver and working
registers.
The flip-flops are edge-triggered on the positive transition
of the clock: the Q outputs are set to the complement of
the logic levels that were set up at the D inputs.
The output buffers are controlled by a common signal (OC)
which places the outputs in high-impedance state when it
is taken high. The OC signal does not affect the internal
operations of the flip-flops. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to. their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
oc
20
8'0
80
70
2'0
70
3'0
60
3D
60
40
4<:)
5c:i
GNO
eLK
10
I
FUNCTION TABLE
Vee
10
(Each latch)
L~I~~!!--t!~~~
loc
ClK D:
I L
t H II
ILL
ILL
X
I H X X[
50
Q
L
H
00
~
I
I
I
I
lOGIC DIAGRAM
10
20
c8SAMSUNG
Electronics
3D
40
50
60
70
80
691
KS54HCTLS
KS74HCTLS
534
Octal D-Type Flip-Flops
with 3-State Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vee. . . . . . . . -0.5V to + 7V
DC Input Diode Current. J,K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current. 10K
(Vo < -0.5V or Vo > Vee +0 5V)
±20 mA
Continuous Output Cu-rrent Per Pin. 10
(-0.5V < Vo < Vee +0.5V) ......... ±70 mA
Continuous Current Through
Vee or GND pins ................. ±250 mA
StorageTemperature Range. Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vee .............. 4.5V to 5.5V
DC Input & Output Voltages *, VIN. VOUT . . OV to Vee
Operating Temperature
·KS74HCTLS: -40°C to +B5°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times. tr • t, . . . . . . . . . Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V±10% Unless Otherwi~e Specified)
Ta =25°C
Symbol Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
O.B
O.B
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/JA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10 = 20iJA
lo=12mA
10=24mA
0,1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
J,N
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Icc
B.O
BO.O
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
61ee
VIN=Vee or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
692
KS54HCTLS
KS74HCTLS
534
Octal D-Type Flip-Flops
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input tr • t~6 ns). HCTlS534
KS74HCTLS
KS54HCTLS
T.=2S·C
T.- -40·C to +8S·C TI - -55·C to +125°C
Unit
Vee=5.0V
Vec=5.0V::t: 10%
Vee 5.0V::t: 10%
=
Typ
Maximum Operating
Frequency
Maximum Propagation
Delay. ClK to any Q
f max
CL=50pF
50
35
30
25
tpLH
CL=50pF
CL=150pF
21
24
28
31
35
40
42
48
tPHL
CL=50pF
CL =150pF
21
24
28
31
35
40
';'2
48
CL=50pF 21
CL =150pF 24
28
31
35
40
42
48
CL=50pF 21
CL=150pF'24
28
31
35
40
42
48
19
25
31
37
19
25
31
37
tw
9
13
15
18
ns
tsu
10
13
17
20
ns
th
-3
0
0
0
ns
tPZH
Maximum Output Enable
Time. oc to any
f---
Maximum Output Disable
Time. OC to any
f---
a
a
Minimum Pule Width,
ClK High or low
Minimum Setup Time,
D before CLKt
Minimum Hold Time,
Dafter ClKt
Maximum Input Capacitance
Guaranteed Umlts
RL=1kO
tPZL
tpHZ
tpLZ
RL=1kO
CL=50pF
MHz
ns
ns
ns
5
pF
Maximum Output Capacitance COUT Output Disabled
10
pF
Power DiSSipation
Capacitance* (per stage)
5
30
pF
CIN
Cpo
OC=Vcc
OC=GND
*
Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC' fin.
t
For AC switching test circuits and timing waveforms see section 2.
=8 !!e!'ISUNG
693
I
KS54HCTLS
KS74HCTLS
5401/541
·/l
Octal Buffers and -Line Drivers
with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pilH)ut, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL ~ 24 mA @ VOL = O.5V) for direct bus Intt,rface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.SV
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +8S o C
KSS4HCTLS: -55°C to +125°C
• Package options include "small outline" packages.
(Available Tape & Reel), standard DIPs.
The '540 and '541 are general purpose high-speed octal
line drivers/buffers with 3-state outputs. The inputs and
outputs are located on OPPOSite sides of the 20·pin
package, thus improving circuit board density. The '540
provides inverted data and the' 541 provides true data at
the outputs.
The three-state control gate is a 2-input NOR such that
if either G1 or G2 is high, all eight outputs are in the high
impedance state.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
, allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected trom damage due to
static discharge by internal diode clamps to Vcc and
ground
LOGIC DIAGRAMS
PIN CONFIGURATION
G1
<31
Vee
A1
G::!
A2
Y1
A3
Y2
A4
Y3
A5
Y4
A6
Y5
A7
Y6
A8
Y7
GND
Y8
(1)
'540
'541
G1
G2
G2
(18)
(18)
A1
Y1
A1
Y2
A2
Y3
A3
Y1
(H)
(7)
(16)
A3
Y2
(.1S)
(15)
(15)
Y4
Y4
A4
(14)
(14)
Y5
A5
Y5
(13)
(13)
FUNCTION TABLE
V6
AS
Input
A7
Output
G,
G2
A
'540
'541
L
L
H
X
L
L
X
H
L
H
X
X
H
L
L
H
Z
Z
Z
Z
c8SAMSUNG
Electronics
'
A8
Y3
Y6
AS
(12)
(12)
Y7
Y7
(11) .Y8
A
(9)
(11)
Y8
694
KS54HCTLS
KS74HCTLS
5401541
I·
Octal Buffers and Line Drivers
with 3-State Outputs
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vec
Operating Temperature
Range
KS74HCnS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
KS74HCTLS J5_0_~
KS54HCTLS
Ta= -40°C to +85°C Ta= -~5°~~--±~~~_~ Unit
Ta =25°C
Test Conditions
Guaranteed limits
Typ
Minimum High-Level
Input Voltage
~-
-
Maximum Low-Level
Input Voltage
- - - - f--------------------- f-----
Minimum High-Level
Output Voltage
VIN=VIH or VIL
10=-20J.tA
10=-6mA
---- ---- -
Vee Vee -0.1
4.2
3.98
- - - - - - - - + - - - - I - - - - - - . : ; ' - - - - - - - - / - - - - - -1------------- -- -
VIN=VIH or VIL
10=20J.tA
10= 12mA
10=24mA
Maximum Low-Level
Output Voltage
f---------------t---+-------~--
Maximum Input
Current
liN
VIN = Vee or GND
0
2.0
--
--j
0.8
VIL
f-~---------
VOH
2.0
2.0
VIH
/-------f--- - - - ------------1---- +------------
0.8
V
--------t-------------------t-----
0.8
V
--- -------t---------------------------f---
Vee -0.1
3.84
Vee -0.1
3.7
V
-------------------+------j
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
±0.1
± 1.0
± 1.0
V
-----/------------r-- - - - - -----.------------ - - - - - - - - - - + - - - - - 1
J.tA
f------------+-----f------------ f-------------f----------------t------------------
Maximum 3-State
Leakage Current
Output Enable
±5.0
±10.0
j.lA
±0.5
loz
=VIH
f____-+_ _--+V_O_U_T
__
=_V___e_e _or GN~ __ t - - - - - - - r------------------ _____________-+------I
Maximum Quiescent
lee
VIN=Vee or GND
80.0
8.0
160.0
10uT=0j.lA
Supply Current
c8SAMSUNG
Electronics
695
I
KS54HCTLS
KS74HCTLS
540'54'1
'/.
AC ELECTRICAL CHARACTERISTICS
Characteristic
Octal Buffers and Line Drivers
,with 3-State Outputs
(Input tr, tf~6 ns), HCTLS540, HCTLS541
KS74HCTLS
KS54HCTLS
T.=25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V~10%
Vcc=5.0V~ 10%
Symbol
Condltlons t
tpLH
CL= 50pF
Cl,=150pF
11
14
15
18
19
24
23
29
tpHL
CL= 50pF
CL =150pF
11
14
15
18
19
24
23
29
18
21
25
28
25
30
37
43
18
21
13
25
28
31
36
37
43
18
23
27
13
18
23
27
Typ
Maximum, Propagation
Delay, A to Y
CL= 50pF
tPZH
Maximum Output Enable
CL=150pF
r - - - - RL=1kO
Time, G to Y
Cl,=50pF
tPZL
CL=50pF
Maximum Output Disable r -tpHZ
RL=1kO
--Time, G to Y
tpLZ CL=50pF
Maximum Input
Capacitance
CIN
Guaranteed Limits
ns
ns
ns
5
pF
pF
Maximum Output
Capacitance
COUT
Output Disabled
10
Power Dissipation
Capacitance· (per stage)
Cpo
G=Vcc
G=GND
5
30
pF
2
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC fin,
t For AC switching test circuits and timing waveforms see section 2,
c8SAMSUNG
Elec~~onics
696
KS54HCTLS
KS74HC:rLS
563
Octal D-Type Transparent Latches
with 3-State Outputs
FEATURES
DESCRIPTION
• 8 latches in a single package
• Full parallel access for loading
• Function, pin-out, spee~and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high -drive current
(IOL = 24mA @ Vo~ = O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMqS devices
• Wide operating voltage range: 4.5\1 to 5.. 5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: ·-40°C to, + 85°C
KS54AHCT: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.,
The '563 consists of 8 high· speed D-type latches coupled to 3-state output buffers with high drive current capability. It can be used in implementing buffer register, I/O ports,
bidirectional bus drivers and working registers.
40
50
The output buffers are controlled by a common signal (OC)
which places the outputs at ahigh-impedance stage when
it is taken high. The OC signal does not affect the internal
operations of the latches. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
PIN CONFIGURATION
OC
10
20
3D
The latches are transparent; when the enable (E) is high,
the Q outputs follow complements of the data (0) inputs.
When the enable is low, the outputs latch at the levels that
were set up at the 0 inputs.
Vee
10
20
30
40
5-e5
60
60
70
80
70
80
GNo
E
I
FUNCTION TABLE
(Each Latch)
L____lnpU!~_.
_____
0
I
OC
·E
I
L
H
H
L
H
L
L
L___~ ______
_
~-L O~~~~._~~J
i
-l----i
LX!
._~
X____1 __
__ .___
-
:
H
00
Z .. ___
I
J
LOGIC DIAGRAM
=8SAMSUNG
Electronics
697
563
KS54HCTLS
KS74HCTLS
OctalD-Type Transparent Latches
with 3-StateOutputs
Absolute Maximum Ratings*
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vec +0.5V) .... ±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
.. ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vce +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 rnA
Storage Temperature Range, T8 tg . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages", VIN, VOUT
OV to Vec
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf
Max 500 ns
.. Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
Typ
Minimum High-Level
Input Voltage
--
J;
f-~-------~-
VOH
__
VIN=VIH or VIL
10=-20I-/A
VIN = VIH or VIL
10= 20I-/A
10=12mA
~--------------_+~~-+~-'0~=24mA
Maximum Input
Current
Guaranteed Limits
2.0
2.0
V
0.8
Vee Vee -0.1
3.98__ _
VIN=Vee or GND
o
0.8
V
1 - - -________________________ 1 -_____________________ _
---f--!9-===='=-~~---- 4.2
Maximum Low-Level
Output Voltage
KS54HCTLS
--~---------~~--
- - - - - - - - - r----t--------- -------------.-- -- - ..---------.. 1----- . - -------.-- ----
Maximum Low-Level
VIL
0.8
~nput VOltage
__ 1 -_______--------------_ +-~e__---Minimum High-Level
Output Voltage
~~_
--------- - - - - - - - - - - -
2.0
VIH
f-----.-~
KS74HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
I---------~----------
0.1
0.26
0.39
±0.1
f------------------- - - - - - + - - - - - - - - - - + - - 1------------
Vce -0.1
3.84
Vee -0.1
3.7
0.1
0.33
0.5
0.4
-- ------ --- -----+--
±1.0
V
0.1
----------
±1.0
V
---
IlA
----------~--i~-----------------~-
Maximum 3-State
Output Enable
loz
=VIH
±0.5
±5.0
± 1 0.0
IlA
_L_e_a_k_ag_e_c
__u_rr_e__
nt~_+-___-+-V..::..O.c::..UT,-=_V__e~c_~~_G_N_D ~ _______ \-______________ ~________ ~--_--~_~-------- ____
Maximum Quiescent
[~Iy Current
Additional Worst
Case Supply
Current
Icc
..6.lcc
VIN=Vee or GND
10UT=01lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10UT=01lA
c8SAMSUNG
Electronics
8.0
80.0
160.0
IlA
2.7
2.9
3.0
mA
698
KS54HCTLS
KS74HCTLS
563'
OctalD-Type Transparent Latches
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Condltlons l
(Input tr ,
tf~6
ns), HCTLS563
KS74HCTLS
KS54HCTLS
T.=25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.0V
Vcc=5.0V:!:10%
Vcc=5.0V:!: 10%
Typ
Maximum Propagation
Delay, D to
a
Maximum Propagation
Delay E to Q
Maximum Output Enable
Time, OC to any
a
tPLH
14
17
18
21
23
28
27
33
tpHL
CL= 50pF
CL =150pF
14
17
18
21
23
28
27
33
tpLH
C= 50pF
CL=150pF
22
25
30
33
37
42
45
51
tpHL
CL= 50pF
CL=150pF
22
25
30
33
37
42
45
51
CL= 50pF 24
CL=150pF 27
32
35
40
45
48
54
CL= 50pF 24
CL=150pF 27
32
35
40
45
48
54
tPZH
RL=1kO
-
tPZL
Maximum Output Disable
Time, OC to any
a
Minimum Pulse Width,
E High
-
Guaranteed Limits
CL= 50pF
CL =150pF
tpHZ
tpLZ
RL=1kO
CL=50pF
tw
19
25
31
37
19
25
31
37
9
13
15
18
ns
ns
ns
ns
ns
..
Minimum Setup Time,
D before E~
tsu
6
8
10
10
ns
Minimum Hold Time,
o after E~
th
6
10
12
15
ns
CIN
5
pF
Maximum Output Capacitance COUT Output Disabled
10
pF
Power Dissipation
Capacitance* (per stage)
5
30
Maximum Input Capacitance
Cpo
OC=Vcc
OC=GND
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC fin.
2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
699
11
. KS54HCTLS·
KS74HCTLS
564
.
Octal D~ Type Flip-Flops
with 3-State Outputs
FEATURES
DESCRIPTION
• Function, pin-ollt, speed and drive compatibility with
54/74lS logic family
• low power consumption characteristic of CMOS
• 3-State Qutputs with high drive current
(IOL = 24 mA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over. industrial and
military temperature ranges:
KS74HCTlS: -40°C to +85°C
KS54HCTlS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '564 consists of 8 high-speed D-typeedge-triggered
flip-flops coupled to 3-state output buffers with high drive
current capability. It can be used in implementing buffer
registers, 1/0 ports, bidirectional bus driver and working
registers.
The flip-flops are edge-triggered: on the positive transition
of the clock, the Q outputs are set to the complement of
the logic levels that were set up at the D inputs.
The output buffers are controlled by a common signal (OC)
which places the outputs at high impedance state when
It is taken high. The OC signal does not affect the internal
operations of the flip-flops. Old data can be retained or new
data can be entered while outputs are off.
These' devices provide speeds and' drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to V cc and
ground.
PIN CONFIGURATION
Oc
FUNCTION TABLE
Vee
10
1Q
20
20
30
30
40
40
50
60
50
60
70
80
GNO
70
80
ClK
(Each Flip-Flop)
Output
Inputs
-----~
I
OC
ClK
D
L
L
L
H
t
t
L
X
H
L
X
X
f------
a
L
H
00
Z
LOGIC DIAGRAM
c8SAMSUNG
Electronics
700
KS54HCTLS
KS74HCTLS
564
Octal D-Type Flip-Flops
with 3-State OutPLlts
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins ................ ±250 mA
Storage Temperature Range, Tstg . . . - 65 ° C to .+ 150 ° C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vee
Operating Temperature
Range
·KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf ..
* Absolute Maximum Ratings are those values beyond
Unused inputs. must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect de'fice reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2~0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vce -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Minimum High-Level
Output Voltage
VOH
VIN = VIH or VIL
10=-20/-LA
10=-6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O /-L A
10=12mA
10=24mA
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
/-LA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vec or GND
±0.5
±5.0
±10.0
/-LA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/-LA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
ll.lee
VIN=Vee or GND
10UT=0/-LA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10UT=0/-LA
:8 !e!'lSUNG
Vee Vee -0.1
4.2
3.98
0
701
I
KS54HCTLS
KS74HCTLS
564
Octal 0-Type Flip-Flops
with 3';'State Outputs
AC ELECTRICAL CHARACTERISTICS
I
Characteristic
Symbol Conditions t
tf~6
ns), HCTlS564
KS74HCTLS
KS54HCTLS
T.=25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.OV
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
I
I Maximum
Operating
Frequency
i
Maximum Propagation Delay,
ClK to any Q
Maximum Output Enable
Time, OC to any Q
CL= 50pF
45
35
30
25
tPLH
CL= 50pF
CL=150pF
21
24
28
31
35
40
42
48
tPHL
CL= 50pF
CL=150pF
21
24
28
31
35
40
42
48
CL= 50pF 21
CL=150pF 24
28
31
35
40
42
48
CL= 50pF 21
CL=150pF 24
28
31
35
40
42
48
19
25
31
37
19
25
31
37
tPZH
f---------------
RL =1 kO
tPZL
Maximum Output Disable
Time, OC to any
a
Guaranteed Limits
f max
1-
I
(Input tr ,
tpHZ
r------
tpLZ
RL=1kO
CL=50pF
MHz
ns
ns
ns
Minimum Pulse Width,
ClK High or low
tw
9
12
15
18
ns
Minimum Setup Time,
D before ClKt
tsu
10
13
17
20
ns
Minimum Hold Time,
Dafter ClKt
th
-3
0
0
0
ns
Maximum Input Capacitance
10
Power Dissipation
Capacitance· (per stage)
5
30
Cpo
pF
5
CIN
Maximum Output Capacitance COUT Output Disabled
OC=Vcc
OC=GND
---t-----
pF
pF
• Cpo determines the no-load dynamic power dissipation: PD=CPD VCC fin.
2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
702
KS54HCTLS
KS74HCTLS
573
Octal D-Type Transparent Latches
with 3-:-State Outputs
FEATURES
DESCRIPTION
• 8 latches in a single package
• Full parallel access for loading
• Function, pin-out, speed and drive compatibility with
54/74ALS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOl 24 rnA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface direclty with TTl, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: -40°C to + 85°C
KS54HACT: -40°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '573 consists of 8 high-speed Ootype latches coupled to 3-state output buffers with high drive current capability. It can be used in implementing buffer registers, I/O ports,
bidirectional bus drivers and working registers.
=
=
The latches are transparent: when the enable (E) is high,
the outputs follow the data (D) inputs. When the enable
is low, the OlJtputs latch at the levels that were set up at
the 0 inputs.
a
The output buffers are controlled by a common signal (OC)
which places the outputs at a high-impedance state when
it is taken high. The OC signal does not affect the internal
operations of the latches. Old data can be retained or new
data can be entered while outputs are off.
There devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and €MOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode cli:i:-'1ps to Vee and
ground.
PIN CONFIGURATION
oc
Vee
10
20
10
20
3D
40
50
(Each Latch)
30
Inputs
40
60
70
50
60
70
80
80
3
OC
Output
0
--
Q
-~
H
H
L
L
L
E
GNO
I
FUNCTION TABLE
H
H
H
L
X
L
X
X
00
70
80
L
Z
LOGIC DIAGRAM
10
20
c8SAMSUNG
Electronics
30
40
50
60
703
KS54HCTLS
KS74HCTLS
573
Octal D-Type Transparent Latches
with 3-StateOutputs
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to. +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +O,5V)
±70 mA
Continuous Current Through
± 250 mA
Vee or GND pins . . . . .
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per Package, Pdt. . . .. 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , it . . . . . . . . . Max 500 ns
• Absolute Maximulll Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to .+125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/JA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/J A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
/J A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
/J A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/J A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
lllee
VIN=Vee or GND
10uT=0/JA
per input pin
VI=2.4V
other Inputs:
at Vce or GND
10UT=OjAA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
704
KS54HCTLS
KS74HCTLS
573
OctalD-Type Transparent Latches
with 3-State Outputs
.
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input tr • t,,,6 ns). HCTLS573
KS74HCTLS
KS54HCTLS
O
T. =2S C T. = -400C to +85 0C T.= -55°C to +125°C
Unit
Vee S.OV
Vec=5.0V±10%
VcczS.OV± 10%
=
Typ
Maximum Propagation
Delay. D to
a
Maximum Propagation
Delay E to
a
Maximum Output Enable
Time.
to any
oc
a
Maximum Output Disable
Time.
to any
oc
a
14
Guaranteed Limits
18
21
23
28
27
33
23
28
27
33
tpLH
CL= 50pF
CL=150pF
tpHL
CL= 50pF
CL =150pF
17
18
21
tpLH
C=50pF
CL =150pF
22
25
30
33
37
42
45
51
tpHL
CL= .50pF
CL =150pF
22
25
30
33
37
42
45
51
CL= 50pF 24
CL=150pF 27
32
35
40
45
48
54
CL= 50pF 24
CL=150pF 27
32
35
40
45
48
54
tPZH
~
RL =lkfi
tPZL
tPHZ
r---
tpLZ
RL =1kfi
CL=50pF
17
14
19
25
31
37
19
25
31
37
ns
ns
ns
ns
Minimum Pulse Width.
E High
tw
9
12
15
18
ns
Minimum Setup Time,
D before E.
tsu
6
8
10
12
ns
Minimum Hold Time.
D after E.
th
6
10
12
15
ns
CIN
5
pF
10
pF
Maximum Input Capacitance
Maximum Output Capacitance COUT Output Disabled
Power Dissipation
Capacitance *
Cpo
OC=Vcc (per stage) 5
30
OC=GND
pF
2
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC fint For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
,
705
I
574
K-SS4HCTLS
KS74HCTLS
OctatD·Type FUp;.F/ltJ/Js
with3.-,Stat. Od~,1J,.· u, ts "
•
. !
•
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• low pOwer consumption characteristic of CMOS
• 3~Sta.e oldputs. with high drive current
(IOL 24 mA @' VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.SV to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '574 consists of 8 high-speed Ootype edge-triggered
flip-flops coupled to 3-state output buffers with high drive
current capability. It can be used in implementing buffer
registers, 1/0 ports, bidirectional bus drivers and working
registers.
=
=
!
The flip-flops are edge-triggered on the positive transition of the clock. The Q outputs are set to the.,logicl,evel 13
that were set up at the 0 inputs.
The output buffers are controlled by a common signal (OC)
which places the outputs at a high-impedance state when
it is taken high. The OC signal does not affect the internal
operations of the flip-flops. Old data can be retained or new
data can be entered while outputs are off.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with DL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to V cc and
ground.
PIN CONFIGURATION
oc
Vee
10
20
10
60
70
80
20
30
40
50
60
70
80
GNO
ClK
30
40
50
FUNCTION TABLE
(Each Flip-Flop)
Inputs
oroutput
f . - - - _ _ ._ _ _. _
OC
ClK
0
_ _ _ __
Q
LOGIC DIAGRAM
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
c8SAMSUNG
Electronics
80
706
KS54HCTLS
KS74HCTLS
574
Octal D-Type Flip-Flops
with 3-State Outputs
Absolute Maximum Ratings·
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current,ilK
(VI < -0.5V or VI> Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V) .
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, T8 tg . . . -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages *, VIN,· Vour . . OV to Vee
Operating Temperature
Range
·KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf . . . . . . . . . Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may oecur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% UnlesS Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20/AA
10=-6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VII..
10= 2O/AA
10=12mA
10=24mA
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/AA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vee or GND
±0.5
±5.0
±10.0
/AA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/AA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
61ce
VIN=Vee or GND
10ur=0/AA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour = O/AA
c8SAMSUNO
Electronics
Vee Vee -0.1
4.2
3.98
0
707
I
KS54HCTLS
KS74HCTLS
574
Octal 0-Type Flip-Flops
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Condltlons l
(Input tr , t, Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±70 mA
Continuous Current Through
±250 mA
Vee or GND pins
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT
OV to Vec
Operating Temperature
Range
·KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55 ° C to + 1 25 ° C
Max 500 ns
Input Rise & Fall Times, tr , tl
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
(Vce=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
_~_
f-,------
Typ
Minimum High-Level
Input Voltage
--
Guaranteed limits
2.0
VIH
KS74HCTLS
KS54HCTLS
Ta= -400C to +85°C Ta= -55°C to +125°C Unit
2.0
2.0
f--------
Maximum Low-Level
Input Voltage
Minimum High-Level
Output Voltage
(All '590 Outputs and
'591 RCO Outputs)
V
-
0.8
Vil
--- ---
0.8
0.8
V
j----
VOH
VIN = VIH or Vil
lo=-20J-lA
lo=-6JT1A
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or Vil
lo=20J-lA
lo=12mA
lo=24mA
Maximum Input
Current
hN
VIN=Vee or GND
IOl
Output Enable
=VIH
VouT=Vee or GND
Vee Vee :-0.1
4.2
3.98
Vee -0.1
3.84
Vee -0.1
3.7
V
c------
0
0.1
0.26
0.39
0.1
0.33
0.5
±0.1
±1.0
0.1
0.4
--f--
-r----~
±1.0
J-lA
- - f----
--
Maximum 3-State
Leakage Current
V
±0.5
±5.0
±10.0
,.,.A
--~
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
~Iee
VIN=Vee or GND
8.0
10uT=Oj.lA
--f------- ,------per input pin
VI=2.4V
other Inputs:
2.7
at Vee or GND
lOUT = OJ-lA
c8SAMSUNG
Electronics
f------
80.0
160.0
,.,.A
2.9
3.0
mA
711
I
KS54HCTLS
KS74HCTLS
5901/591
/.
AC ELECTRICAL CHARACTERISTICS
Conditions t
Symbol
Characteristic
.8-Bit Binary Counters with
Output Registers
(Input tr ,
tf~6 ns), HCTlS590
T. =25°C
Vcc=5.0V
KS74HCTLS
KS54HCTLS
T.=-40°Cto +85°C T.= -55°C to +125°C
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Typ
Maximum Clock Frequency
Maximum Propagation Delay,
CCKt to RCO
f--
35
25
20
20
~
24
32
40
48
tpHL
24
32
40
48
26
35
44
52
Maximum Propagation Delay,
to RCO
tpLH
Maximum Propagation Delay,
RCKt to Q
~
Maximum Output Enable Time,
~
CClR~
G~ to Q
CL=50pF
tpHL
RL=1kO
CL=50pF
tPZL
Maximum Output Disable Time,
<3t to Q
tpHz
~
tp\.Z
Minimum Pulse CCK or RCK
High or Low
Width
CClR low
CCKEN~
tw
before
CCKt
Minimum
Setup Time
CClRt before
CCKt
tsu
16
21
26
31
16
21
26
31
18
24
30
36
18
24
30
36
18
24
30
36
18
24
30
36
12
16
20
24
12
16
20
24
12
16
20
24
12
16
20
24
24
32
40
48
ns
ns
ns
ns
ns
ns
ns
ns
I
CCKt to
RCKttt
Maximum Input CapaCitance
Guaranteed Limits
fmax
5
pF
Maximum Output Capacitance
COUT Output Disabled 10
pF
Power Dissipation Capacitance *
Cpo
pF
CIN
* Cpo determines the no-load dynamic power dissipation: PD=CPD VCC 2 fin.
t For AC switching test circuits and timing waveforms see. section 2.
t t The RCKt to CCKt setup time ensures that the counter will see stable data from the register output.
c8SAMSUNG
E~ctronics
712
8-Bit Binary Counters with
Output Registers
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input tr,tf~6 ns), HCTlS591
Ta =2SOC
Vcc=5.0V
Typ
Ta
KS74HCTLS
KSS4HCTLS
+85°C Ta= -55°C to +125°C
Unit
Vcc=5.0V:i: 10%
Vcc=5.0V:i:10%
='-40°C to
Guarantied Umlts
Maximum Clock Frequency
fmax
35
25
20
20
Maximum·. Propagation Delay,
CCKt to RCO
tpLH
24
32
40
48
tpHL
24
32
40
48
26
35
44
52
-
Maximum Propagation Delav,
CClRt to RCO
tpui
Maximum Propagation Delay,
RCKt to Q
~
27
37
46
55
tpHL
16
21
26
31
Maximum Output Enable Time,
G+ to Q
tPZL
18
24
30
Maximum Output Oisable Time,
Gt to Q
.
.
tpLZ
18
24
12
Minimum Pulse CCK or RCK
High or low
Duration
CClR Low
CL=50pF
RL=1kfl
tw
/
"
CCKENt before
CCKt
Minimum
Setup Time
CClRt before
CCKt
tsu
CCKt to
RCKttt "
Maximum Input Capacitance
CIN
V
ns
~
ns
ns
ns
36
ns
30
361
ns
16
20
24
12
16
20
24
12
16
20
24
12
16
20
24
24
32
40
48
5
ns
ns
pF
Maximum Output Gapacitance
COUT Output Disabled
pF
Power Dissipation Capacitance *
Cpo
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2..tin.
t For AC switching test circuits and timing waveforms see section 2. I'
tt The clocks may be tied together, in whicg. case the register state will be one clock pulse behind the counter.
c8SAMSUNG
Electronics
713
I
2/593
V~Pit Bina,ry Counters
KS54HCTLS 5.·.,9,
KS74HCTLS
""Jnput Registers H '
FEATURES
with·
DESCRIPTION
• Parallel Register Inputs ('592)
• Parallel 3-State I/O: Register Inputs/Counter Outputs
('593)
• Counter Has Direct Overriding Load'and Clear
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOl =24 rnA @ VOL =O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for opera.tion over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: \ - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
PIN CONFIGURATIONS
'592
'593
B
vee
AJO,
Vee
C
A
B/O.
G
D
CLOAD
C/Oe
G
RCKEN
E
RCK
0/00
CCKEN
E/O E
RCK
G
CCK
FlO.
CCKEN
H
CCLR
G/OG
CCKEN
RCa
H/OH
CCK
GND
CLOAD
CCLR
RCO
GNO
The '592 and '593 both contain an B-bit register which feeds
an S-bit binary counter. The counter is incremented on the
rising edge of th~ CCK input, provided that clock enable,
CCKEN, is low. When the counter increments to the all
ones condition, ripple carry out, RCa, will go low. This
• enables either synchronous cascading of the counters by
connecting the RCO of the first stage to the CCKEN of
the second, or clocking both circuits in parallel. Ripple
cascading is accomplished by connecting the RCO of the
first to the CCK of the second stage. A clear input is also
provided which will reset the counter to the all zeros state.
The input register is loaded on the rising edge of the register
clock, RCK. The outputs of this register feed the counter.
The counter is loaded with the register's contents when
the clock load, CLOAD, input is taken low.
The '592 differs from the '593 in that the latter device has
bidirectional input/output pins. The 3-state outputs of the
counter can be enabled and are active when enable input,
G, is taken low and input G is taken high. The outputs of
the counter then appear on the register inputs. This enables
connection of this part to a system bus. The '593 also has
a second clock enable pin, CCKEN, which is active high
and it also has an active low register clock enable, RCKEN.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external co'mponents. .
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
INPUTS (' 592)
RCK
FUNCTION
CLOAD
CCLR
CCKEN
CCK
X
L
H
X
X
Register data is loaded into counter
X
H
L
X
X
Counter clear
S
H
H
X
X
The data of a thru H inputs is stored into
register
~
H
H
X
X
X
H
H
L
X
H
H
L
S
L
X
H
H
H
X
Register state is not changed
Counter advances the count
No count
No count
X: Don't car.:;..e_ _ _ _ _ _ _ _ _ _ _ _ _ __
RCa
OA'· OB' Oc' • OD' OE' • OF' OG' • OH'
(OA'
f\J
OH': Internal outputs of the counter)
c8SAMSUNG
Electronics
714
592/593
8-Bit Binary Counters with
Input Registers
KS54HCTLS
KS74HCTLS '
LOGIC DIAGRAMS
'592
CCLA
(10)
~I~
CCK
(11)
CLOAD
RCK
.~
(13)
A
B
~
.----
---
v
...-
1
-
.....--
r-<: I>c
""""--
R a
~6 i.....-
...-
r--
(15)
0
D
ll)
D
k t>'c
L...-.-
C
D
......-(l
l>c
'--(4)
r--< ~c
(5)
""""--
-o
~R
~
L h
a
0
L0-
o
L I-
R
a
I>
I
_.
....
--
i.o--
.
r--;::
~
.
n
>-~
1
r---
~~
...-
L-c I>c
=8SAMSUNG
Electronics
. .
a
LC >T
...~ i>c
H (7)
R
0
Fl
L...-.-
r---
""""--
(6)
Lh
i.o--
k >c
G
~~
o
I>T
'--0
..-~
Lh
L..--
~
0
F
o
t>T
r--
0
fl
.----
-
(3)
~--
I.......--
.~
A
--
~ R a
~ R a
0
.--
L f-<
~ t>c
L..---;.
E
o
LC I>T
........-
(2)
L-1
>T
o
L I-
R
a
I>T
'---
-~cF1
r---
~
o
L I-
I>T
R a
r..-
715
KS54HCTLS
KS74HCTLS
LOGIC
5921593
"'
,'8-Sit'Sinary Counters with
'Iflput Registers
DIAGRAMS(Continued)
'593
(19)
G
(18)
G
. (12)
CCiJf
'·~I~
CCKEN
CCKEN
CCK
(14)
(13)
,
(9)
-
I
(17)
....J
RCK
G
'l
(16)
AlO A
..
~
(1)
I
...
D
1
(2)
k
(3)
rb>c
~R
...
.
'--
I
~
D
~
[ rD
~ ~C
~R
(6)
[~
D
I>c
H:L
-.-
(7)
GIOG
l~
D
H: t>c
HIOH
I~
D
.
L--< t>c
i.....-
c8SAMSUNG
. Electronics
¢-
rLT
---<: R 0
'-M
M
L
~~
L..--
~f-
~
r
I
~
~
L.(;D
~T
~R
LI-
0
L..--
I
~R 0
"---
1
~D
0
L..--
I ~ __
L.(t>T
R 0
L--..c
~
...
~
u-
>T
~R
_I-
4-
r-
L.OD
LIt>T
i.....-
(8)
,...
0
r
i.....-
FI OF
L'-
;>T
t>c
~A
¢-
~
i.....-
(5)
0
!......--
~ D
~ t>c
E/O E
\,,1-
D
~T
-
~
r--
LO
i.....-
k
~
0
"---
D
D
0/0 0
~R
[ r-
C/Oc
Lf-
L..c~T
'.
*
(11)
R
r-----'"""
~
~
D
'-
B/O B
TO THAT SHOWN FOR
CCK
~
~ ~C·
(4)
~
GATING FOR RCK .
IS SIMILAR IN DETAIL
~
~
~
'-"~
~
1
~
~
716
KS54HCTLS
KS74HCTLS
592/593
8-Bit Binary Counters with
Input Registers
Absolute Maximum Ratings·
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
± 250 mA
Vce or GND pins
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt . . .
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce . ..
. ........ 4.5V to 5.5V
DC Input & Output Voltages * " VIN, VOUT . . OV to Vce
Operating Temperature
·KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf .' ........ Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stre~s ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
KS74HCTLS
KS54HCTLS
Ta =-40°Cto +85°C Ta=-55°Cto +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20,.,A
10= -6mA
Vce -0.1
3.84
Vee -0.1
. 3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20,.,A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
,.,A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
,.,A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
Additional Worst
Case Supply
Current
6 1ee
VIN=Vec or GND
10UT=0,.,A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lOUT = O,.,A
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
,.,A
..
2.7
2.9
3.0
_- c---..
mA
717
I
·KS54HCTLS
KS74HCTLS
5'"'9·2"5'
93"
/1
8-Blt Binary
Count.rs with
'Input Ftegist8r,$,:'
.J
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
(Input tr ,
tf~2 n~), HCTLS592
T. =25°C
Vee=5.0V
KS74HCTLS
KS54HCtLS
T.=-400Cto +85°C T.= -55°C to +125°C
Unit
Vee = 5.0V % 10%
Vcc=5.0V% 10%
Typ
Maximum Clock Frequency
Guaranteed Limits
fmax
35
25
20
20
~
24
32
40
48
24
32
40
48
~
24
32
40
48
tpHL
24
32
40
48
Maximum Propagation Delay,
to RCO
tpHL
24
32
40
48
Maximum Propagation Delay,
RCKt to RCO
~
26
CL=50pF
CLOAD=GND 26
35
44
52
35
44
52
12
16
20
24
Maximum Propagation Delay,
CCKt to RCO
Maximum Propagation Delay,
CLOAD~
to RCO
CCLR~
tpHL
tPHL
tw
CLOAD Low
before
CCKt
Minimum
Setup Time
ns
CL=50pF
CCK or RCK
Minimum Pulse
High or Low
Width
CCLR Low
CCKEN~
MHz
CCLRt before
CCKt
tsu
RCKt before
CLOADtt
Data A-Ht before
RCKt
12
16
20
24
12
16
20
24
12
16
20
24
12
16
20
24
24
32
40
48
12
16
20
24
th
a
0
0
0
Maximum Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
Minimum Hold Time
ns
ns
ns
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin,
t For AC switching test circuits and timing waveforms see section 2.
t t The RCKt to CLOAD setup time ensures that the counter will see stable data from the register output.
c8SAMSUNG
Electronics
718
KS54HCTLS
KS74HCTbS
5921593
I.
or
.:
'3"
r
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
8-Bit Binary Counters with
Input Registers
Conditionst
(Input tr • tf~6 ns). HCTLS593
T.=25°C
Vcc=5.0V
Typ
Maximum Clock Frequency
f max
KS74HCTlS
KS54HCTlS
T.= -40°C to +85°C T.== -55°C to +125°C
Unit
Vcc=5.0V%10%
Vcc =5.0V% 10%
Guaranteed Limits
35
25
20
20
tPLH
CL=50pF
CL=150pF
24
27
32
35
40
45
48
54
tpHL
CL=50pF
CL =150pF
24
27
32
35
40
45
48
54
24
32
40
48
24
32
40
48
MH2
,
Maximum Propagation Delay.
CCKt to
a
Maximum Propagation Delay.
CCKt to RCO
Maximum Propagation Delay.
CLOAm to
a
Maximum Propagation Delay.
CLOAD+ to RCO
~ CL=50pF
tpHL
tpLH
CL=50pF
CL=150pF
24
27
32
35
40
45
48
54
tpHL
CL=50pF
CL =150pF
24
27
32
35
32
40
45
40
48
54
48
24
32
40
48
26
35
44
52
26
35
44
52
CL =50pF
CL =150pF
24
27
32
35
40
45
48
54
CL =50pF
24
32
40
48
~ CL =50pF
tpHL
Maximum Propagation Delay. I -tpLH
CL =50pF
---RCKt to RCO
tpHL CLOAD=GND
Maximum Propagation Delay.
CCLR+ to
a
Maximum Propagation Delay.
CCLR+ to RCO
Maximum Enable Time.
Gt or <3+ to
a
tPHL
tPLH
24
tPZL
I-----
RL=1kO
39
CL=50pF 21
CL=150pF 24
28
31
44
42
48
CL=50pF 21
CL=150pF 24
28
31
35
44-_._--
42
48
RL=1 kO
~ CL
=50pF
24
28
35
42
28
35
42
12
16
20
24
12
16
20
24
CLOAD ' Low
12
16
20
24
CCKEN+ before
CCKt
12
16
20
24
12
16
24
12
16
20
24
RCKt before
CLOADtt
24
32
40
48
Data A-H
before RCKt
12
16
20
24
th
0
0
0
0
C,N
5
CCK or RCK
High or Low
Minimum
Pulse Width CCLR Low
RCKEN+ to
Minimum
RCKt
Setup Time CCLR+ before
CCKt
ns
ns
- -j
----
..
.-
ns
-
ns
--,Ins
------t-
21
a
ns
ns
--
tPZL
Maximum Disable Time
<3+ or Gt to
---'- 1---
tpLZ
tw
tsu
ns
ns
-
ns
--
ns
--- --
ns
-~
Hold Time
Maximum Input Capacitance
Maximum Output Capacitance COUT Output Disabled
Power Dissipation Capacitance*
10
ns
pF
10
Cpo
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fin,
For AC switching test circuits and timing waveforms see section 2,
tt The RCKt to CLOAD setup time ensures that the counter will see stable data from the register output.
t
719
i
I
I
595'I,1596
KS54HCTlS
KS74HCTLs
8..Bit Shift Registers with
Output:';Latches
FEATURES
DESCRIPTION
• 8-Bit Serial-In, Parallel-out Shift Registers With Storage
• Choice ot3-State ('595) or Open-Drain ('596) Parallel
Outputs
• Shift Register Has Direct Clear
• Function, pin-out, speed and drive compatibility with
54174LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(lOL 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
T,hese devices each contain an 8-bit serial-in, parallel-out
shift register that feeds an a-bit D-type storage register.
The storage register has parallel 3-state ('595) or opendrain ('596) outputs, Separate clocks are provided for
both the shift register and the storage register. The shift
register has aditect-overriding clear, serial input, and serial
output pins for cascading.
.
=
Both the shift register and storage register clocks are
positive-edge triggered. If the user wishes to connect both
clocks together, the shift register state will always be one
clock pulse ahead of the storage register.
=
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output VOltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATION
as
Vee
Oe
PA
aD
SER
Of
G
Of
RCK
OG
OH
SRCK
SRCLR
O'H
GND
FUNCTION TABLE
INPUTS
--
SER
X
SRCK
X
J
--
SRCLR
j
X
RCK
1
X
I
H
QA thru QH outputs disable
-
X
X
X
X
L
QA thru QH outputs enable
X
X
L
X
X
Shift register is cleared.
X
X
First stage of S.R. becomes "L". Other stages store
the data of previous stage, respectively.
L
J
H
H
S
H
X
X
First stage of S.R. becomes "H". Other stages store
the data of previous stage, respectively.
X
L
H
X
X
State of S.R. is not changed.
1---.
x:
FUNCTION
G
,
.-
X
X
X
X
X
X
S
L
---------t'--
X
S.H. data is stored into storage register.
X
Storage register state is not changed.
------
DON'T CARE
c8SAMSUNG
Electronics
720
KS54HCTLS
. KS74HCTLS
5951596
1~
8-Bit Shift Registers with
Output Latches
LOGIC DIAGRAM
(15)
A.
(2)
oc
(3)
00
(4)
OE
(5)
Q
I
F
(6)
Q
G
c8SAMSUNG.
Electronics
721
59·5' 11:96
KS54HCTLS·
KS74HCTlS~, ',,~, I~
;. r
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC trom 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0,5V < Vo < Vee +0.5V) . ,
±70 mA
Continuous Current Through
Vee or GND pins. .
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: '- 55 ° C to + 1 25°C
Input Rise & Fall Times, tr , tf
Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vec=5V±'10% Unless Otherwise Specified)
Ta=25°C
KS74HCTLS
KS54HCTLS
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
(All '595 Outputs and
'596 Q'H Output)
VOH'
VIN=VIH or VIL
lo=- 2OIAA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=201AA
10=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
ItN
VIN=Vee or GND
±0.1
±1.0
±1.0
lolA
loz
Output Enable
=VIH
Vour=Vee or GND
±0.5
±5.0
±10.0
lolA
8.0
80.0
160.0
lolA
2.7
2.9
3.0
mA
Vee Vee -0.1
4.2
3.98
0
~-
Maximum Input
Current
Maximum Output
Leakage Current
Maximum Quiescent
VIN=Vee or GND
.SUPPlrGu~entl-'C~ _lour=OIAA
per input pin
~-"'-----'-~
Additional Worst
Case Supply
Current
J
l:.lee
VI=2.4V
other Inputs:
at Vee or GND
lour=OIAA
c8SAMSUNG
Electronics
722
KS54HCTLS
KS74HCTLS
595.1596
I·
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlons t
8-Bit Shift Registers with
Output Latches
(Input tr , tf~6 ns), HCTLS595, HCTLS596
T. =25°C
Vcc·S.OV
KS54HCTLS
KS74HCTLS
T.= -40°C to +85°C Ta= -55°C to +12SoC
Unit
Vcc=5.0V:t10%
Vcc=S.OV:t 10%
Guaranteed Llmlt.ll
Typ
Maximum Propagation
Delay, SACKt to O'H
15
18
25
30
15
18
25
30
17
20
22
25
28
33
33
39
17
20
22
25
28
33
33
39
18
21
24
27
30
35
36
42
18
21
24
27
30
35
36
42
18
21
24
27
30
35
36
42
CL=50pF
18
21
24
27
30
35
36
42
tPLH
r----- CL=50pF
tpHL
CL=50pF
tPLH
Maximum Propagation
CL=150pF
r----Delay, ACKt to OA thru OH
CL=50pF
tpHL
CL =150pF
Maximum Output Enable
Time, G~ to OA thru OH
('595 only)
Maximum Output Disable
Time, Gt to OA thru OH
('595 only)
Maximum Propagation
Delay, Gt to OA thrc OH
('596 only)
Maximum Propagation
Delay, G~ to OA thru OH
('596 only)
rSACK or ACK
Minimum
Pulse Width
SACLA Low
SACLRt to
Minimum
SACKt
Setup Time SEA to SACKt
CL=50pF
tPZH
CL=150pF
r----- AL=1kO
CL=50pF
tpZL
CL==150pF
tpHZ AL=1 kO
r-----tpLZ
tPLH
tPHL
CL=50pF
18
24
30
36
CL=150pF
21
27
35
42
CL=50pF
18
24
30
36
CL=150pF
21
27
35
42
12
16
20
24
12
16
20
-----
24
12
16
20
24
tw
12
16
20
24
SACKt to
ACKtt
24
32
40
48
Minimum Hold Time
th
-3
0
0
0
CrN
5
Maximum Input Capacitance
tsu
Maximum Output
Capacitance
COUT Output Disabled
Power Dissipation
Capacitance*
Cpo
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
10
pF
-
f----
pF
* Cpo determines the no-load dynamic power dissipation: PO=CPD Vee' fin.
For AC switching test circuits and timing waveforms see section 2.
t t This setup time ensures the register will see stable data from the register output.
t
723
I
KS54HCTL~
KS74HCTLS
597
8-Bit Shift-Registers with
Input Latches
FEATURES
DESCRIPTION
• 8·Bit Parallel Storage Register Inputs
• shift Register has Direct Overiding Load and Clear
• Function, pin-out, speed and eJrive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• Hlgh-Drive-Current outputs:
10l =8 mA @ Val =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '597 consists of an 8-blt storage latch feeding a
parallel-in, serial-out 8-bit shift register. 80th the storage
register and the shift register have positive-edge triggered
clocks. The shift register also has direct load (from storage)
and clear inputs.
PIN CONFIGURATION
LOGIC DIAGRAM
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
Vee
A
SER
E
SRlOAO
F
RCK
G
SRCK
H
SRCi:A
GNO
Q~
1111
1>----4:>--0..
=8SAMSUNG
Electronics
i
.
724
8-Bit Shift-Registers with
Input Latches
FUNCTION TABLE
INPUTS
SER
SRCK
X
X
FUNCTION
SRCLR
SRLOAD
RCK
X
L
H
X
X
H
J
X
Input register data is stored into S.R.
S.R. is cleared to "L"
L
S
H
H
X
First stage of S.R. becomes ~·L". Other stages store
the data of previous stage, respectively.
H
I
H
H
X
First stage of S.R. becomes "H". Other stages stores
the data of previous stage, respectively.
X
X
X
X
X
X
X
X
X
X
X
X
State of S.R. is not changed.
I
L
Input data on A"'H line is stored into input register
Storage register state is not changed.
Absolute Maximum Ratings*
Supply Voltage Range Vcc, ..
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-O.SV < Vo < Vcc +0.5V) . .
±35 mA
Continuous Current Through
Vcc or GND pins
± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/o C from 65 ° C to 85 ° C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages * , VIN, Your
OV to Vce
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vce or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vcc=5V± 10% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
Typ
KS74HCTLS
Ta= -40°C to +85°C Ta
KS54HCTLS
+125°C Unit
= -55°C to
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OIlA
10= -4mA
Vec -0.1
3.84
Vec -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=201lA
10=4mA
10=8mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vce or GND
±0.1
±1.0
±1.0
IlA
8.0
80.0
160.0
IlA
2.7
2.9
3.0
mA
Maximum Quiescent
~Current
Additional Worst
Case Supply
Current
Icc
bolee
VIN=Vce or GND
10ur=01lA
per input pin
VI=2.4V
other Inputs:
at Vce or GND
10ur=01lA
c8SAMSUNG
Electronics
Vec Vcc -0.1
4.2
3.98
0
I
725
I
KS54HCTLS5,
KS74HCTLS,;
97
.>
(Input tr , tf~6 ns), HCTLS597
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
8-Bit Sh,ft-Registers with"
, 'Input Latches"
T. =25°C
Vc c=5.0V
Conditions t
KS74HCTLS
KS54HCTLS
T.=-400Cto +85°C T.=-55°Cto +125°C
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Guar,anteed limits
Typ
Maximum Clock Frequency
Maximum Propagation Delay,
SRCKt to Q'H
Maximum Propagation Delay,
SRLOAD+ to Q'H
Maximum Propagation Delay,
f max
35
25
20
20
tpLH
i----'--=-~
15
18
25
30
tpHL
15
18
25
30
tpLH
I--
CL =50pF
tPHL
-
tpHL
rLRlto O'H
Maximum Propagation Delay,
RCKt to Q'H
Minimum
l"u'S. Width
tPLH
f---
tpHL
RCK or SRCK
High or Low
CL=50pF
SLOAD=Low
RCKt before
SRCKttt
I
SER before
SRCKt
~
30
36
30
36
17
22
28
33
21
29
35
42
21
29
35
42
12
16
20
24
12
16
20
24
12
16
20
24
24
32
40
48
12
16
20
24
tsu
A thru H before
RCKt
Minimum Hold Time
th
12
16
20
24
0
0
0
Maximum Input Capacitance
CIN
0
Power Dissipation Capacitance *
Cpo
ns
ns
ns
ns
ns
SRCLRt before
SRCKt
Setup Time
24
24
tw
SRCLR or
SRLQAD Low
IMln;mum
18
18
MHz
-_.-
5
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin,
t
For AC switching test circuits and timing waveforms see section 2,
,
t t The RCKt before SRCKt setup time ensures that shift 'register will see stable data comming from the register output.
c8SAMSUNG
Bectronics
726
Octal Bus Transceivers
with 3-StataOutputs
FEATURES
DESCRIPTION
• Function, pin-out, speed and drive compatibility with
54174lS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOl = 24 rnA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These high-speed octal/bus transceivers are designed for
asynchronous two-way communication between data
buses. A direction control input (DIR) controls the flow
direction of data. When DIR is high, data flows from the
A inputs to the B outputs. When DIR is low, data flows from
8 to A. The '643 transfers inverted data from the A bus
to the B bus and non·inverted data from the B bus to the
A bus. The '640 transfers inverted data in both directions.
=
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
PIN CONFIGURATION
FUNCTION TABLE
OIR
Vee
A1
G
Control
Inputs
A2
81
G
A3
82
A4
83
A5
84
A6
85
A7
86
A8
87
GNO
88
c8SAMSUNG
Electronics
I
Operation
DIR
'640
'643
'645
L
L
Inverted data
transmitted from
Bus B to Bus A
Data transmitted
from Bus B
to Bus A
Data transmitted
from Bus B
to Bus.A
L
H
Inverted data
transmitted from
Bus A to Bus B
Inverted data
transmitted from
Bus A tv Bus B
Data transmitted
from Bus A
to Bus B
H
X
Buses isolated
(High-impedance
state)
Buses isolated
(High-impedance
state)
Buses isolated
(High-impedance
state)
I
727
KS54HCTLS
KS74HCTLS:.
640/643/645
.
Octal Bus Transceivers
with 3-State Outputs
LOGIC DIAGRAMS
'640
'643
'645
Absolute Maximum Ratings·
Supply Voltage Range Vee,
-0.5V to +7V
DC Input Diode Current, hK
(V, < -0.5V or V, > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Va < -0.5V or Va > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Va < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
. Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vec
4.5V to 5.5V
DC Input & Output Voltages * , Y,N, VOUT .. OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
728
6401/6431645
/l
/l
KS54HCTLS
KS74HCTLS
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 1 0% Unless Otherwise Specified)
KS74HCTLS
KS54HCTLS
T.= -40°C to +85°C T.= -55°C to +125°C Unit
T.=25°C
Test Conditions
Octal Bus Transceivers
with 3-State Outputs
Typ
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OlAA
lo=-6mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Mwtimum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20lAA
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
lAA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VOUT=VCC or GND
±0.5
±5.0
±10.0
lAA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
lAA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Icc
Vcc Vcc -0.1
3.98
4.2
0
VIN=VCC or GND
10UT=OlAA
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
louT=O,.,A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditions t
(Input tr , tt-~6 ns), HCTLS640, HCTLS643, HCTLS645
KS74HCTLS
KS54HCTLS
T.=25°C T.= -400C to +85°C T.= -55°C to +125°C
Unit
Vcc=5_0V
Vcc=5.0V:!:10%
Vcc=5.0V:!: 10%
Typ
Maximum Propagation
Delay, A to B, or B to A
Maxim!!.m Output Enable
Time, G or DIR to A or B
tpLH
9 12
12 15
16
21
19
25
tPHL
CL=50pF
CL =150pF
9 12
12 15
16
21
19
25
CL=50pF 30 40
CL=150pF 33 43
50
55
60
65
CL=50pF 30 40
CL =150pF 33 43
50
55
60
65
20 27
34
40
20 27
34
40
tPZH
-
RL=1kO
tPZL
Maximum Output Disable
Time, G or DIR to A or B
Maximum Input CapaCitance
Maximum Output Capacitance
Power Dissipation
Capacitance* (per stage)
Guaranteed Limits
CL=50pF
CL=150pF
~- RL=1kO
tpLZ
CL=50pF
ns
ns
ns
5
pF
COUT Output disabled
10
pF
G=Vcc
G=GND
5
30
CIN
. Cpo
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vcc fin.
2
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
729
I
KS54'HCTLS
KS74HCTLS
646'648
,I
Octa!.~~-StateBus Transceivers
with·"Registers
-
.
FEATURES
DESCRIPTION
•
•
•
•
The '646 and '648 are bi-directional bus transceivers with
D-!lJpe flip-flops and control circuitry to facilitate high speed
multiplexed data transmission. The '646 transmits true data
and the '648 transmits inverted data.
•
•
•
•
•
•
8 bi-directional data paths
Transmits direct or stored data in either direCtion
24-pin 0.3" slim DIP package
Function, pin-out, speed and drive compatibility with
54/74LS logic family
Low power consumption characteristic of CMOS
3-State outputs with high drive current
(I0L 24 rnA @ VOL 0.5V) for direct bus interface
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74AHCT: - 40°C to + 85°C
KS54HACT: - 55°C to + 125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
=
Data can be transmitted directly from one port to the other
in either direction. It also can be stored in the flip-flops from
either or both ports for subsequent transmission to the oppOSite port. Six control inputs govern the data flow:
=
G (output
enable) when high, all outputs are
disabled, isolating the A and B ports. When
low, one port is enabled at a time as determined by the DIR pin.
DIR (direction control) disables A or B outputs per·
mitting the pins to be used as inputs thus determining the direction of a data flow. When
DIR=high, data flows from A to B.
SAB,SBA (data source AB and BA) determines whether
data transmitted is from the data inputs or the
registers associated with those inputs.
PIN CONFIGURATION
CAB
Vee
SAB
CBA
DIR
SBA
A1
G
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
GND
B8
(21) (3) (1) (23) (2) (22)
G DIR CAB CBA SAB SBA
X
X
X
Real-Time transfer
bu!> B to bus A
c8SAMSUNG
Electronics
CAB,CBA (Clock AB and BA) clocks data from the A inputs and the B inputs, respectively, into their
associated registers. Since the clocks are not
gated with the G and DIR pins, data at the A
and B pins can be clocked into the ffip-flops
at any time.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode cfamps to Vcc and
ground.
(21) (3) (1) (23) (2) (22)
G DIR CAB CBA SAB SBA
H
X
L
Real-Time transfer
bus A to bus B
X
(21) (3) (1) (23) (2) (22)
G DIR CAB CBA SAB SBA
x
x
X
H
X
X
X
t
x
x
x
t
X
X
x
Storage from
A AND/OR B
X
(21) (3)
G
(1)
(23)
(2)
(22)
DIR CAB CBA SAB SSA
x
x
X
H
H
X
H
X
Transfer stored
data to A ANDIOR B
730
KS54HCTLS
KS74HCTLS
646/648
Octal 3-State Bus Transceivers'
with Registers
FUNCTION TABLE
Inputs
Data 11O·
Operation or Function
C=----
G DIR
X
X
CAB
CBA
t
X
X
t
t
X
X
~
rt
X
X
A1 thru A8
81 thru 88
input
input
Not specified Not specified
X
X
X
X
H or L H or L
X
X
X
X
Input
Input
f--o--.
H
SAB SBA
t
'646
'648
Store A, B unspecified
Store B, A unspecified
Store A, B unspecified
Store B, A unspecified
Store A and B data
Isolation, hold storage
Store A and B data
isolation, hold storage
L
L
X
X
X
H or L
X
X
L
H
Output
Input
Real-Time B data to A bus Real-Time B data to A bus
Stored B data to A bus Stored 8 data to A bUS
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real-Time A data to B bus Real-Time A data to B bus
Stored A data to B bus
Stored A data to B bus
·The data output functions may be enabled or disabled by various signals at the Gand DIR inputs. Data input functions are always enabled,
ie., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
LOGIC DIAGRAMS
'646
DIR
(3)
(21).
SAB
Ll..
(2)
1 OF 8
CHANNELS
-----
I
----I
I
I
I
I
I
I
I
I
_ _ _ ---II
L---------------------~v~------------~--------~/
TO 7 OTHER CHANNELS
'648
OIR
(21)
(3)
SAB
(2)
r----
----I
II
I
I
I
I
I
I
I
L___
____
____
_
I
__ ---I
\~----------------__,v~~-------~-------J/
TO 7 OTHER CHANNELS
c8SAMSUNG
Electronics
731
KS54HCTLS
KS74HCTLS
6. 46II1648
Octal. a."State Bus Transceivers
with>:'Registers
...,
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -O.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current; 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-O.5V <: Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins . .
. . . . . . .. ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages * , VIN, Vour .. OV to Vee
Operating Temperature
·KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf ..
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vec=5V± 10% Unless Otherwise Specified)
Ta =25°C
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
Maximum Low-Level
Input Voltage
VIL
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20/-IA
10=-6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2O/-lA
10=12mA
10=24mA
Maximum 'Input
Current
liN
Maximum 3-State
Leakage Current
loz
Maximum Quiescent
Supply Current
Ice
Additional Worst
Case Supply
Current
.6.lee
KS74HCTLS
KS54HCTLS
Ta= -40°C to + 85'oC Ta= -55°C to +125°C Unit
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
VIN=Vee or GND
±0.1
±1.0
±1.0
/-I A
Output Enable
=VIH
Vour=Vee or GND
±0.5
±5.0
±10.0
/-I A
8.0
80.0
160.0
/-I A
2.7
2.9
3.0
mA
.'
VIN=Vee or GND
10ur=O/-lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=O/-lA
c8SAMSUNG
"
Electronics
Vee Vee -0.1
4.2
3.98
0
732
KS54HCTLS
KS74HCTLS
6461648
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Condltlons t
Octal 3-5tate Bus Transceivers
with Registers
(Input tr • tt~6 ns). HCTLS64f), HCTLS648
KS74Hr.TlS
KS54HCTLS
T.=25°C
T.=-40°C .<1 +85°C T.=-55°C to +125°C
Unit
Vee=5.0V
Vee =- ...OV± 10%
Vce=5.0V± 10%
Typ
Maximum Clock
Frequency
Guaranteed limits
fmax
CL=50pF
40 30
25
20
MHz
Maximum Propagation
Delay, A or B Input
to B or A Output
tpHL
CL=50pF
CL =150pF
14 19
17 22
24
29
29
35
ns
tpHL
CL=50pF
CL =150pF
14 19
17 22
24
29
29
35
Maximum Propagation
Delay, CBA or CAB Input
to A or B Output
tpLH
CL=50pF
CL=150pF
22 30
25 33
37
42
45
51
tpHL
CL=50pF
CL=150pF
22 30
25 33
37
42
45
51
tPLH
CL=50pF
CL=150pF
26 35
29 38
44
49
53
59
to A or B Output
(with A or B High)
tpHL
CL=50pF
CL=150pF
26 35
29 38
44
49
53
59
Maximum Propagation
Delay, SBA or SAB Input
tpLH
CL=50pF
CL=150pF
26 35
29 38
44
49
53
59
tpHL
CL=50pF
CL=150pF
26 35
29 38
44
49
53
59
CL=50pF
CL=150pF
33 45
36 48
56
61
67
73
CL=50pF
CL =150pF
33 45
36 48
56
61
67
73
Maximum Propagation
I Delay, t t SBA or SAB input
I
I(with
to A or B Output
A orB Low)
IMaxim~m
Output Enable
I Time, G or DIR Input to
. A or B Output
Maximum Output Disable
Time, G or DlR Input to
A or B Output
tPZL
~
RL = 1 kO
tPZH
tpHZ
~
tpLZ
RL = 1kO
CL=50pF
26 35
44
53
26 35
44
53
ns
ns
ns
ns
ns
Pulse Duration, Clocks
High or Low
tw
10 13
17
20
ns
Setup Time, A before
CABt or B before CBM
tsu
10 13
17
20
ns
Hold Time, A after CABt
or B after CBM
th
0
ns'
Maximum Input Capacitance
CIN
Maximum Output
ICapacitance
COUT Output Disabled
IPower Dissipation
iCapacitance·
Cpo
a
0
pF
.\.5
10
pF
---
• Cpo determines the no-load dynamic power dissipation: PO=CPD
pF
VCC
2
fin.
t For AC switching test circuits and timing waveforms see section 2,
tt
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
c8SAMSUNG
Electronics
733
I
KS54HCTLS
KS74HCTLS
6511652
/1
OcflJl"r3..Sta,e' Bus Transceivers
with~~lIegisters
FEATURES
DESCRIPTION
•
•
•
•
These devices conSist of bus transceiver circuits, Ootype
flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the
internal storage registers. Enable GAB and GBA are provided to control the transceiver functions. SAB and SBA
control pins are provided to select whether real-time or
stored data is transferred. A low input level selects realtime data, and a high selects stored data. The following
examples demonstrate the four fundamental busmanagement functions that can be performed with the octal
bus transceivers and registers.
•
•
•
•
•
•
Independent Registers and Enables for A and B Buses
Multiplexed Real-Time and Stored Data
Choice of Time and Inverting Data Paths
Function, pin-out, speed and drive compatibility with
54/74LS logic family
Low power consumption characteristic of CMOS
3-State outputs with high drive current
(loL = 24 rnA @ VOL = O.5V) for direct bus interface
Inputs and outputs Interface directly with TTL, NMOS
arid CMOS devices
Wide operating Yoltage range: 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by low-to-high transitions at the appropriate clock pins (CAB or CBA) regardless of the select
or enable control pins. When SAB and SBA are in the realtime transfer mQde, it is also possible to store data without
using the internal Ootype flip-flops by simultaneously enabling GAB and GBA. In this configuration each output reinforces its input. Thus, when all other data sources to the
two sets of bus lines are at high impedance, each set of
bus lines will remain at its last state.
PIN CONFIGURATION
CAB
Vee
SAB
CBA
SBA
A1
A2
GBA
B1
A3
B2
A4
B3
AS
B4
A6
B5
A7
A8
B6
B7
GND
B8
(21) (3) (1) (23) (2) (22)
G DIR CAB CBA SAB SBA
X
X
X
Real-Time transfer
bus B to bus A
L
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
(21) (3) (1) (23) (2) (22)
G DIR CAB CBA SAB SBA
H
X
X
Real-Time transfer
bus A to bus B
c8SAMSUNG
Electronics
X
(21) (3) (1) (23) (2) (22)
G DIR CAB CBA SA!,! SBA
X
X
H
X
X
X
t
X
t
X
t
Storage from
A AND/OR B
X
X
X
X
X
X
(21) (3) (1) (23) (2) (22)
G DIR CAB CBA SAB SBA
'L
L
H
X
X
X
X
X
H
H
X
Transfer stored data
to A and/or B
734
KS54HCTLS
KS74HCTLS
6511652
Octal 3-State Bus Transceivers
with Registers
FUNCTION TABLE
INPUTS
GABGBA CAB
DATA I/O·
L
L
H H or L H or L X
t
t
H
X
X
H
H
H
t
t
L
L
X H or L
L
L
H
H
L
L
H
H H
H
L
t
L
X
X
X
OPERATION OR FUNCTION
CBA SABSBA A1 THRU A8 B1 THRU B8
X
'652
X
X
Input
Input
Isolation
Store A and B Data
Isolation
Store A and B Data
X
X·· X
Input
Input
Not specified
Output·
Store A, Hold B
Store A in both registers
Store A Hold B
Store A in both registers
Hold A, Store B
Store B in both registers
Hold A, Store B
Store B in both registers
H or L X
t
t
t
'651
X
X
X Not specified
X"
Output"
Input
Input
X
L
H
Output
Input
X
X
Input
Output
H
Output
Output
H or L X
L
X
or L X
H
H or L H or L H
Real-Time 8 Data to A Bus Real· Time B Data to a Bus
Stored B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus Real·Time A Data to B Bus
Stored A Data to Bus
Stored A Data to B Bus
IStored A !:lata to B Bus and Stored A Data to B Bus and
Stored B Data to A Bus
Stored B Data to A Bus
• The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions
are always "enabled, .ie., data at the bus pins will be stored on every low-to-high transition on the clock inputs .
.... Select control=L: clocks can occur simultaneously
Select control=H: clocks must be staggered in order to load both registers
I
LOGIC DIAGRAMS
'652
'651
Get.
1211
GSA
G..a
GAB
121)
____
----;1>--+-_ _ _ _ _ _ _ _ _----'
_1~31
----+------D<>-----h
CIA
CBA _1:.:.:23:!..)
122)
S8A
c..a
SAIl
141
I
I
I
- ----------rt.J
------------~vr-----------~
TO 7 OTHER CH_LS
=8SAMSUNG
Electronics
I
------------~vr----------~
TO 7 OTHER CHANNELS
735
KS54HCTLS
KS74HCTLS
6511652.
II
Octal 3-State,,~.:#JIJs,Transceivers
with Registers
Absolute Maximum· Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee,
-0.5V to + 7V
DC Input Diode Current, hK
(VI <-0.5V or VI> Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . . . . .
±70 mA
Continuous Current Through
Vce or GND piOs . . .
........
±250 mA
Storage Temperature Range, Tstg . . . - 65 ° C to + 150 ° C
Power Dissipation Per Package, Pdt ...... 500 rnW
Recommended Operating Conditions
Supply Voltage, Vee .............. 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vee
Operating Temperature
·KS74HCTLS: -40°C to +85°C
Range
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t;, tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10= -6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
3.0
mA
Additional Worst
Case Supply
Current
Alec
VIN=Vee or GND
10uT=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
c8SAMSUNG
Electronics
Vee Vee -0.1
3.98
4.2
0
--
2.7
2.9
736
KS54HCTLS
KS74HCTLS
65-11652
Octal 3-State Bus Transceivers'
with Registers
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Input tr • tf~6 ns). HCTLS651. HCTLS652
KS74HCTLS
KSS4HCTLS
T.=2SoC T.= -40°C to +8S oC T.= -55°C to +12S o C
Unit
Vcc= S.OV:!: 100/0
Vcc=S.OV:!: 10%
Vcc=S.OV
Condltlons t
Guaranteed Limits
Typ
f max
CL=50pF
40
30
25
20
tpLH
CL =50pF
CL=150pF
14
17
19
22
24
29
29
35
tPHL
CL=50pF
CL =150pF
14
17
19
22
21
26
20
26
tpLH
CL=50pF
CL = 150pF
22
25
30
33
37
42
45
51
tpHL
CL=50pF
CL=150pF
22
25
30
33
37
42
45
51
Maximum _Propagation
Delay. SBA or SAB Input to
A or B Output
(with A or B High)
tpLH
CL=50pF
CL=150pF
26
29
35
38
44
49
53
59
tpHL
CL=50pF
CL=150pF
26
29
35
38
44
49
53
59
Maximum Propagation
Delay. SBA or SAB Input to
A or B Output
(with A or BLow)
tpLH
CL=50pF
CL=150pF
26
29
35
38
44
49
53
59
tpHL
CL=50pF
CL=150pF
26
29
35
38
44
49
53
59
CL=50pF 33
CL =150pF 39
45
48
56
61
CL=50pF 33
CL=150pF 39
45
48
56
61
67
73
Maximum Clock Frequency
f--
Maximum Propagation
Delay. A or B Input to
B or A Ouput
Maximum Propagation
Delay. CBA or CAB Input to
A or B Output
Maximum Output Enable
Time. GBA to A or
GABio B
Maximum Output Disable
Time. GBA to A or GAB to
B
tPZL
!-------------
RL=1 kO
tPZH
67
7,3
----
tpHZ
RL=1 kO
26
35
44
53
tpLZ
CL=50pF
26
35
44
53
r-----------
MHz
ns
ns
ns
ns'
.'
'~
ns
ns
Minimum Pulse Width
Clocks High or Low
tw
10
- -I--
13
17
20
ns
Minimum Setup Time. A before
CABt or B before CBAt
tsu
10
13
17
20
ns
Minimum Hold Time. -A after
CABt or B after CBM
th
0
0
ns
Maximum Input Capacitance
a
..
--
CIN
Maximum Output Capacitance COUT Output Disabled
Power Dissipation
Cpo
Capacitance •
--~
5
-
0
r-----
pF
-
10
I
pF
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin.
t For AC switching test circuits and timing waveforms see section 2_
c8-SAMSUNG
Electronics
737
I
659
.
KS54HCTLS-\1l5811
KS74HCTLS ~i\,.
/1
FEAT\JRES
DESCRIPTION
• Bus Transceivers with Inverting Outputs ('658) or True
Outputs ('659)
• Generates i Parity Bit for A Bus Ind 8 Bus
• Easny Clscadable
• Internll Active Pull-Ups and Pull-Downs
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOL =24 mA @ VOL =O.5V) for direct bus interface
• Inputs and outputs interface direct'y with .TTL, NMOS
and CMOS devices
• Wide operating Yoltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These octal bus transceivers are designed for asynchronous, bidirectional communication between data
buses. The devices transmit data from the A Bus to the
B Bus, or from the B Bus to the A Bus, depending on the
levels at the direction control inputs, GAB and ~BA. These
devices also generate parity outputs, APO and BPO, which
reflect the number of high levels at the A Bus and B Bus,
respectively, taking into account the parity inputs API and
BPI.
PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
GAB
Vee
A1
A2
G8A
B1
A3
A4
B2
83
A5
B4
A6
A7
B5
86
A8
BPI
87
B8
8PO
API
GND
APO
The bidirectional I/O ports feature active circuits on the input
stage that, when the output shared by that pin is disabled,
will maintain the input in the last state taken by the output.
This state will be maintained until changed by activity on
the bus. The advantage of this arrangement is that when
all outputs on the bus are disabled, the inputs will be
prevented from floating, resulting in minimum power dissipation and minimum susceptiblity to noise. This eliminates
any need for external pull-up or pull-down resistors. The
parity inputs API and BPI have similar circuits.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
FUNCTION TABLE
CONTROL
INPUTS
GBA
GAB
L
L
H
1----
H
L
H
+---~--~
L
H
NUMBER OF HIGH
INPUTS ON
A BUS AND API
NUMBER OF HIGH
INPUTS ON
B BUS AND BpI
X
0, 2, 4, 6, 8
Z
H
X
1, 3, 5, 7, 9
Z
L
0, 2, 4, 6, 8
X
H
Z
1,3,5,7,9
X
L
Z
X
X
Z
Z
X
0, 2, 4, 6, 8
X
1,3-,5,7,9
0, 2, 4, 6, 8
X
H
1, 3, 5, 7, 9
X
L
---------~-
c8SAMSUNG
Electronics
OPERATION
OUTPUTS
APO BPO
1-----------_. _-- f------
HCTLS658
HCTLS659
B Data to A Bus
B Data to A Bus
A Data to B Bus
A Data to B Bus
Isolation
Isolation
B Data to A Bus,
B Data to A Bus,
A Data to B Bus
H
L
A Data
to B Bus
738
KS54HCTLS
KS74HCTLS
658/659
Octal Bus Transceivers
with Parity
LOGIC DIAGRAM
GBA
(23)
GAB--~I~l)~--------__________~________~--~~
T ~
~ ~~~----~
(22)
7 INVERTING (NONIVERTING FOR '659)
CHANNELS IDENTICAL TO CHANNEL.
1 ABOVE
I
I
(21)
(20)
(191
(18)
(17)
(16)
(15)
B1
B2
B3
B4
B5
B6
B7
B8
(13)
APO
(10)
BPI
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to +7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins. . . .
±250 mA
StorageTemperature Range, TSlg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ..... 500 mW
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
suppiy Voltage, Vce . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·. VIN, VOUT
OV to Vce
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times. tr • tf . . . . . . .. Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage leliel (either Vee or GND)
739
Octa/~us
KS54HCTLS'6'S8/659
KS74HCTLS ..,
with Parity
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
Transcelvers
,
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74HCTLS
Ta
KS54HCTLS
= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10= -6mA
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=12mA
10=24mA
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vec or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
Dolce
VIN=Vec or GND
10ur=0",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=0",A
c8 SAMSUI\IG
Electronics
Vee Vee -0.1
4.2
3.98
a
740
KS54HCTLS
KS74HCTLS
6581/659
/1
Octal Bus Transceivers
with Parity
AC ELECTRICAL CHARACTERISTICS
Char.ct..lltlc
Symbol
CondHlon. t
(Input fr. tt<6 ns). HCTLS658. HCTLS659
T. -25°C
Vcc-s.OV
KS74HCTLS
KS54HCTLS
T.- -40°C to +8S·C T. - - SSoC to + 12S·C
UnH
Vcc-S.OV±10%
Vcc-S.OV±10%
Typ
Maximum Propagation
Delay. A or B to B or A
Maximum Propagation
Delay. A or B to B or A
Maxlmum Propa~ation
Delay A or B to
APO or BPO
Maximum Enable Time,
GAB or GBA to
APO or BPO
Maximum Disable Time,
GAB or GBA to
APO or BPO
Maximum Input Capacitance
Gu.r.ntMd LlmH'
tpLH
CL==50pF
CL=150pF
20
23
25
28
30
35
39
45
tpHL
CL=50pF
CL=150pF
20
23
25
28
30
35
39
45
CL==50pF
tPLH CL=150pF
24
27
32
35
40
45
48
54
tpHL
CL=50pF
CL=150pF
24
27
32
35
40
45
tPLH
CL=50pF
CL=150pF
20
23
25
28
30
35
48
54
39
45
tPHL
CL=50pF
CL=150pF
20
23
25
28
30
35
39
45
CL=50pF 20
CL=150pF 23
25
28
30
35
39
45
CL=50pF 20
CL=150pF 23
25
28
30
35
39
45
20
20
25
25
30
30
39
39
tPZH
f--
RL=1kO
tPZL
~ RL=1kO
tPHZ
CIN
CL=50pF
5
ns
ns
ns
ns
ns
ns
pF
Maximum Output
Capacitance
COUT
pF
Power Dissipation
Capacitance *
Cpo
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
Electronics
741
I
Octal Bus Transceivers
"'ith Parity!,;
,j
"
d
FEATURES
DESCRIPTION
• Bus Transceivers with Inverting Outputs ('664) or True
Outputs ('665)
• Generates a Parity Bit for A Bus and B Bus
• Easily Cascadable
• Internal Active Pull-Ups and Pull-Downs
• Function, pin-out, speed and drive compatibility with
54174lS logic family
• low power consumption characteristic of CMOS
• 3-8tate outputs with high drive current
(IOL 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These octal bus transceivers are designed for asynchronous, bidirectional communication between data
buses. The devices transmit data from the A Bus to the
B Bus or from the B Bus to the A Bus, depending on the
level at the direction control input, DIR. The enable input,
Gcan be used to disable the device so that the buses are
isolated, These devices will also ger)erate parity outputs,
APO and BPO, which reflect the number of high levels at
the A Bus and B Bus, respectively, taking into account the
parity inputs API and BPI.
=
=
.PIN CONFIGURATION
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power IEwels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
Vee
DIR
The bidirectional I/O ports feature active circuitry on the
input stage that, when the output shared by that pin is
disabled, will maintain the input in the last state taken by
the output. This state will be maintained until changed by
the activity on the bus. The advantage of this arrangement
is tht when all outputs on the bus are disabled, the
inputs will be prevented from floating, resulting in minimum
power dissipation and minimum susceptibility to noise. This
eliminates any need for external pull-up or pull-down
resistors. The parity inputs API and BPI have similar circuitry.
G
81
62
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vec and
ground.
63
64
65
66
87
68
API
APO
FUNCTION TABLE
CONTROL
INPUTS
----- ,---_..-
G
L
DIR
L
NUMBER OF HIGH
INPUTS ON
A BUS AND API
NUMBER OF HIGH
INPUTS ON
B BUS AND BPI
X
0, 2, 4, 6, 8
f------------------
X
L
H
1, 3, 5, 7, 9
0, 2, 4, 6, 8
X
1,3,5,7,9
-~
X
=8SAMSUNG
Electronics
---.---~-
APO
BPO
Z
H
-----
Z
1----
I---------~------
t------ e------ r---
H
---~~--.-~-
X
f------
X
-----~--------
X
OPERATION
OUTPUTS
1--
-~--
,--~--.--------
'664
'665
B Data to A Bus
B Data to A Bus
A Data to B Bus
A Data to B Bus
Isolation
Isolation
L
- -----
H
Z
L
Z
Z
Z
- - - - - -"------
r - - - - '------..
742
Octal ~us Transceivers
with PlIrity
lOGIC DIAGRAM
Go
CIR
1231
(1)
-"'"
......
v
-
~-
~
T ....
- "'
......
......
......
I
oJ
~---~~-~;~J
......
_J----r:
Th'lQ
I
~
......
-,,-,.r;-
rv-v- "" 1
L _ .... :-.!6~
_
_
_
_
~
_
I
_
1
7 INVERTING (NONIVERTING FOR '665)
CHANNELS IDENTICAL TO CHANNEL 1
ABOVE
1
(22)
'665
Bl
I
_
~~~.----~--~~--~~
~
i
'664
---
_
J
(21)
Ir----r~--------~~ B2
i20)
B3
(19)
B4
(18)
B5
(17)
i
.
(16)
(15)
(13)
B6
B7
B8
APO
(10)
BPI
Absolute Maximum Ratings*
Supply Voltage Range Vee,
--0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or V, > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±70 mA
Continuous Current Through .
Vee or GND pins
±250 mA
Storage Temperature Range, Tstg . . . -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
" Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t P0wer Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages", VIN, VOUT
o.V to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55 0 C to + 125 ° C
Max 500 ns
Input Rise & Fall Times, t r , tl
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
743
I
KS54HCTLS
KS74HCTLS
6641665
. /j
,Octal Bus Transceivers
with Parity
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vcc=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=V,H or VIL
10=-20jAA
10= -6rnA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or V,L
10=20jAA
10=12mA
10=24mA
Maximum Input
Current
liN
Maximum 3-State
Leakage Current
loz
Maximum Quiescent
Supply Current
Icc
Additional Worst
Case Supply
Current
~Icc
Vcc Vcc -0.1
4.2
3.98
0.1
0.26
0.39
0.1
0.33·
0.5
0.1
0.4
V
V'N=VCC or GND
±0.1
±1.0
±1.0
jAA
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
jAA
8.0
80.0
160.0
jAA
2.7
2.9
3.0
rnA
VIN=VCC or GND
10UT=UjAA
per input pin
VI=2.4V
other Inputs:
at Vce or GND
10UT=OjAA
c8SAMSUNG
Electronics
0
744
KS54HCTLS
KS74HCTLS
Octal Bus Transceivers
with Parity
6641665
AC ELECTRICAL CHARACTERISTICS
Chiracterlstlc
Symbol
Condltlons t
(Input fr. t,<6 ns). HCTLS664/655
T.-2S·C
Ycc:zS.OY
KS74HCTLS
KS54HCTLS
T.- -40·C to +8S·C T.... -ss·c to +12SOC
Unit
Ycc-S.OY±10%
Ycc-S.OY± 10%
Typ
Maximum Propagation
Delay. A or B to B or A
Maximum Propagation
Delay. A or B to
,.
APO or BPO
Maximum Propagation
Delay. API or BPI to
APO or·BPO·
Maximum Output Enable
Time. G to A or B
tpLH
20
23
25
28
30
35
39
45
tpHL
CL=50pF
CL=150pF
20
23
25
28
30
35
38
36
tPLH
CL=50pF
CL=150pF
24
27
32
35
40
45
48
54
tpHL
CL=50pF
CL=150pF
24
27
32
35
40
45
48
54
tpLH
CL=50pF
CL=150pF
20
23
25
28
30
35
39
45
CL=50pF
20
23
25
28
30
35
39
45
CL=50pF 24
CL=150pF 27
CL=50pF 24
CL=150pF 27
32
35
40
45
48
54
32
35
40
45
48
54
tpHL
~L=150pF
tPZH
I---
RL=1kO
tPZL
Maximum Output Delay
Time. G to A or B
Maximum Output Enable
Time DIRtoA or B .
~
tP'LZ
tPZH
I---
Maximum Input CapaCitance
Maximum. Output
CapaCitance
Power Dissipation
Capacitance *
tPHZ
r--
tHLZ
24
32
40
48
24
22
40
50
CL=50pF 24
CL=150pF 27
32
35
40
45
48
54
CL=50pF 24
CL=150pF 27
32
35
40
45
48
54
20
32
40
48
24
32
40
48
RL=1kO
CL=50pF
RL=1kO
tPZH
Maximum Output Disable
Time. DIR to A or B
GuarantHd Limits
CL=50pF
CL=150pF
RL=1kO
CL=50pF
CIN
COUT Output Disabled
ns
ns
ns
ns
ns
ns
ns
5
pF
10
pF
Cpo
pF
2
* Cpo determines the no·load dynamic power dissipation: Po=Cpo VCC fin.
t For AC switching test Circuits and timing waveforms see section 2.
:8SAMSUNG·
Electronics
745
I
KS54HCTLS ~670.
KS74KCTLS ';'
4-Sy-4 .Register Flies with
with 3-State Output$·t
FEATURES
DESCRIPTION
• Separate Read/Write
Addressing Permits Simultaneous Reading and
Writing
• Expandable to 512 Words of N-bits
• For use as:
- Scratch pad memory
- Buffer storage between processors
- Bit storage in fast multiplication designs
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
10l =8 mA @ VOL =O.5V
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '670 is a 16-blt 3-State Register File organized as 4
words of 4 bits each. Separate Read and Write Address
and Enable Inputs are available, permitting simultaneous
writing into one word location and reading from another
location. The 4-bit word to be stored is presented to f04r
Data inputs. The Write Address inputs (WA and WB) determine the location of the stored word. When the write
enable ( Gw) input is LOW, the data is entered into the addressed location. The addressed location remains
transparent to the data while the Gw is LOW. Data supplied at the inputs will be read out in true (non-inverting)
form from the 3-State outputs. Data and Write Address inputs are inhibited when Gw is HIGH.
PIN CONFIGURATION
02
Vee
03
01
04
WA
RB
WB
RA
Gw
04
GR
03
01
GNO
02
Direct acquisition of data stored in any of the four registers
is made possible by individual Read Address inputs {FfA
and RB). The addrssed word appears at the four outputs
when the read enable (GA) is LOW. Data outputs are in
the HIGH impedance "off" state when the read enable
input is HIGH. This permits outputs to be tied together to
increase the word capacity to very large numbers.
Up to 128 devices can be stacked to increase the word
size to 51 2 locations by tying the 3-State outputs together.
Since the limiting factor for expansion is the output HIGH
current, fu!1her stacking is possible by tying pull-up resistors
to the outputs to increase the IOH current available. Design
of the read enable signals for the stacked devices must
ensure that there is no overlap in the LOW levels which
would cause more than one output to be active at the same
time. Parallel expansion to generate n-bit words is accomplished by driving the Enable and Address inputs of
each device in parallel.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vce and
ground.
FUNCTION TABLES
I~/
READ MODE SELECT TABLE
WRITE MODE SELECT TABLE
OPERATING
MODE
Write Data
Data
Latched
INPUTS
Gw
On
INTERNAL
LATCHES(a)
L
L
L
H
L
H
H
X
no change
NOTE:
a. The Write Address (WA and Ws) to the "Internal
latches" must be stable while Gw is LOW for conventionaloperation.
:8SAMSUNG
Electronics
OPERATING
MIODE
INPUTS
GR
-INTERNAL
LATCHES(b)
OUTPUT
Qn
Read
L
L
L
H
L
H
Disabled
H
H
(Z)
NOTE:
b. The selection of the "internal latches" by Read Address
(RA and Rs) are not constrained by Ow or GA
operation.
746
KS54HCTLS
KS74HCTLS
670
4-8y-4 Regi$ter Files with
with 3-State Outputs
LOGIC DIAGRAM
DATA
INPUT)
I
Rs
WRITE INPUT
GR
RA
--------'
READ INPUT
Absolute Maximum Ratings*
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI >Vcc +0.5V}
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V}
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vcc +0.5V}
±70 mA
Continuous Current Through
Vcc or GND pins
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
* Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
.
t .Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vcc
Operating Temperature
Range
·KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fa~1 Times, t r , tf
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
747
KS54HCTLS
KS74HCTLS
,6.....70
4..l3y-4
Register Files with
with 3-State OutP:CJts.
1
DC ELECTRICAL CHARACTERISTICS
Charact~ristic
Symbol Test Conditions
(Vee=5V± 10% Unless Otherwise Specified)
Ta =25°C
Typ
KS74HCTLS
KS54HCTLS
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
, V,H·
Input Voltage
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
V,L
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
V'N=V'H or V,L
lo=- 2OIolA
lo=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
V,N=V,H or V,L
lo= 2OIolA
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
V'N=Vec or GND
±0.1
±1.0
±1.0
lolA
Maximum 3-State
Leakage Current
loz
Output Enable
=V,H
VouT=Vee or GND
±0.5
±5.0
±10.0
lolA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
lolA
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Alec
V'N=Vec or GND
louT=OIolA
per input pin
V,=2.4V
other Inputs:
at Vee or GND
IOUT=OIolA
c8SAMSUNG
Electronics'
.
Vee Vee -0.1
4.2
3.98
0
748
KS54HCTLS
KS74HCTLS
670
4-By-4 Register Files with
with 3-State Outputs
AC ELECTRICAL CHARACTERISTICS
I
Characteristic
Symbol
Conditions t
I
---~--.--
--
~=150pF
40
45
48
54
CL =50pF
tpHL
CL=150pF
20
23
32
35
40
45
48
54
tpLH
CL =50pF
CL =150pF
27
30
36
39
45
50
59
65
tpHL
CL=50pF
CL =150pF
27
30
36
39
45
50
59
65
tpLH
CL =50pF
CL=150pF
27
30
38
39
45
50
59
65
tpHL
CL =50pF
CL =150pF
27
30
36
39
45
50
54
60
CL =50pF 24
CL =150pF 27
32
35
40
45
48
54
CL =50pF 24
CL =150pF 27
32
35
40
45
48
54
24
32
40
48
24
32
40
48
Maximum Propagation Delay,
Gw to Output
IMa::~ pmpagati:De;a~
Data to Output
CL =50pF
tPZH
Maximum Output Enable Time
GR to Output
---
tPZL
--------------
}----
I,:,a"mum Output D,.able T,me
GR to Output
Time
to~",_
WA,WS to Gw
-
-
Hold
tpHZ
tpLZ
,Set up ] _ Do
-
-
- -------
RL =1 kO
CL=150pF
-th
----~
WA, Ws to Gw
RL=1 kO
tsu
On to Gw
---
Maximum Input Capacitance
-CIN
Maximum Output Capacitance
COUT Output disabled
-
-
-
---------
f-------------
[Power Dissipation Capacitance *
Guaranteed Limits
32
35
f-----
I
Time
KS74HCTLS
KS54HCTLS
T. = 25°C
T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vee=5.0V
Vee=5.0V~ 10%
Vee= 5.0V ~ 10%
20
23
tpLH
[Maximum Propagation Delay,
IRA or Rs to Output
f
(Input t r , tf~6 ns), HCTLS670
Typ
!
9
12
15
18
15
18
23
27
0
0
0
0
0
0
0
0
.
ns
ns
ns
ns
ns
ns
ns
5
pF
10
pF
CPD
pF
* CPD determines the no-load dynamic power dissipation: PD=CPD VCC 2 fin
• For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
,
749
I
I
FEATURES
DESCRIPTION
• '679: 12-bit to 4-bil comparator with enable
• '680: 12-bit to 4-bit comparator with latch
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High-Drive-Current outputs:
(IOL =24 rnA @ VOL = 0.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '679 and '680 address comparators simplify addressing of memory boards and/or other peripheral devices. The
four P inputs are normally hard wired with a preprogrammed address. An internal decoder determines what input information applied to the 1 2 A inputs must be low or high
to cause a low state at the output (Y). For example, a
positive-logic bit combination of 0111 (decimal 7) at the
P input determines that inputs A 1 through A7 must be low
and that inputs A8 through A 1 2 must be high to cause the
output to go low. Equality of the address applied at the A
inputs to the pre programmed address is indicated by the
output being low.
The '679 features an enable input (<3). When G is low, the
device is enabled. When G is high, the device is disabled
and the output is high regardless of the A and P inputs.
The '680 features a transparent latch and a latch enable
input (C). When C is high, the device is in the transparent
mode. When C is low, the previous logical state of Y is
latched.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components ..
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
PIN CONFIGURATIONS
'679
'680
Al
Vee
Al
Vee
A2
G
A2
C
A3
Y
A3
Y
A4
P3
A4
P3
A5
P2
AS
P2
A6
Pl
A6
Pl
A7
PO
A7
PO
AS
A12
A8
A12
A9
All
A9
All
GNO
Al0
GNO
Al0
c8SAMSUNG
Electronics
750
KS54HCTLS
KS74HCTLS
,
6791/680
/1
12-8it Address Comparators
LOGIC DIAGRAMS
'679
'680
(1)
Al
,0.2
,0.3
AS
(1)
Al
(21
,0.2
(31
,0.3
(41
(51
(51
,0.6
,0.8
,0.9
,0.10
All
(3)
(41
(61
,0.7
(2)
(7)
(61
(7)
(81
,0.8
(91
(81
I
(9)
,0.9
(111
(11)
,0.10
.(121
(12)
All
,0.12
PO
PO
P2
P2
P3
P3
PI
G
c8SAMSUNG
Electronics
751
6791/680
/1
KS54HCTLS
KS74HCTLS'
12-BitAddrsss 'Comparators
FUNCTION TABLE
'679
'680
~
C
INPUTS COMMON TO '679 AND '680
P3
OUTPUT
A12
y
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
AS A6 A7 A8 A9 A10 A11
P2
P1
PO
A1
A2
A3
A4
L
H
L
H
H
L
L
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
'L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
H
L
L
H
H
H
L
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
H
H
H
L
L
L
L*
L*
L*
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
All other combinations
L
H
'679: Any combination
H
'680: Any combination
Latched
Note: These three rows of the function table show combinations that would normally not be used in address comparator applications. The logic symbols above are not valid for all combinations in which P= 12, 13 and 14. If symbols valid for
all combinations are required, starting with the fourth Exclusive-OR from the bottom, change P~9 to P=9 ... 11/13 ...
15, P~10 to P=10/11/14/15, and P~11 to P=11/15.
Absolute Maximum Ratings*
Supply Voltage Range Vee,
-0.5V to +7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Cu"rrent Per Pin, 10
(-O.5V < Vo < Vee +0.5V) . .
±70 mA
Continuous Current Through
Vcc or GND pins . . . . . . . . . . .
± 250 mA
Storage Temperature Range, T519 . . . - 65 ° C to + 150 ° C
Power Dissipation Per Package, Pdt
500 mW
* Absolute Maximu.m Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
c8SAMSUNG
Electronics
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc
........
4.5V to 5.5V
DC Input & Output Voltages * , VIN, Vour .. OV to Vce
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf ..... .
Max 500 ns
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
752
KS54HCTLS 67n/~80
KS74HCTLS
I "lUI
12-8it Address Comparators
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V± 10% Unless Otherwise Specified)
T. =25°C
Test Conditions
KS74HCTLS
KS54HCTLS
T.=-40°Cto +85°C T.=-55°Cto +125°C Unit
Guaranteed Limits
Typ
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20uA
10=-6mA
Vcc -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20,..A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
,..A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
,..A
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
.t.lcc
Vcc Vcc -0.1
4.2
3.98
0
VIN=VCC or GND
lOUT = o,..A
per input pin
VI=2.4V
other Inputs:
at Vcc or GND
10UT=0,..A
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
T. '=25°C
Vcc=5.0V
KS74HCTLS
T.= -40°C to +85°C
Vcc=5.0V:t10%
Typ
Maximum Propagation Delay,
G to Y
KS54HCTLS
T.= -55°C to +125°C
Vcc=5.0V:t 10%
CL=50pF
CL=150pF
24 32
27 35
40
45
48
54
tpHL
CL=50pF
CL=150pF
27 32
30 35
40
45
48
54
tpLH
CL=50pF
CL=150pF
21 28
24 31
35
40
42
48
tpHL
CL=50pF
CL =150pF
21 28
24 31
35
40
42
48
tpLH
CL=50pF
CL=150pF
18 24
21 27
30
35
36
42
tpHL
CL=50pF
CL =150pF
18 24
21 27
30
35
36
42
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
·5
Unit
Guaranteed limits
tpLH
Maximum Propagation Delay,
Any P to Y
Maximum Propagation Delay,
Any A to Y
I
(Input t r , tf~6 ns), HCTLS679
ns
-
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin,
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electrnnir.~
753
:"\'~'~Bit Address 'Comp_rators
AC ELECTRICAL CHARACTERISTICS
(Input t r • tf~6 ns). HCTLS680
Ta=25°C
Vee=5.0V
KS74HCTLS
T. = - 40°C to + 85°C
Vee = S.OV:t 10%
KS54HCTLS
Ta= -55°C to +125°C
Vee=5.0V:t 10%
Symbol
Conditions t
tpLH
CL=50pF
CL=150pF
27
30
36
39
45
50
54
60
tpHL
CL=50pF
CL=150pF
27
30
32
35
40
45
48
64
tpLH
CL =50pF
CL=150pF
24
27
32
35
40
45
48
64
tpHL
CL=50pF
CL=150pF
24
27
32
35
40
45
48
64
tpLH
CL=50pF
CL=150pF
19
22
26
29
32
37
38
44
Y
tpHL
CL=50pF
CL=150pF
19
22
26
29
32
37
38
44
Set up Time
,An before E
tsu
9
12
15
18
ns
th
0
0
0
0
ns
Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
Characteristic
!
Typ
!
I
Maximum Propagation Delay.
Any P to Y
Maximum Propagation Delay.
Any A to Y
I
I
I Maximum
~c to
Propagation Delay.
I Hold
Time
An after E
Unit
Guaranteed Limits
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 2 fin, .
t For AC switching test circuits and timing waveforms see section 2,
c8SAMSUNG
Electronics
754
,8·Bit Magnitude
Comparators
FEATURES
DESCRIPTION
• Compares Two 8-Bit Words
• '682 has 20kO pull· up Resistors on the Q Inputs
These magnitude comparators perform comparisons of two
eight·bit binary or BCD words. All types provide P=O and
P>O outputs. The '682 features 20·kO pull·uptermination
resistors on the 0 inputs for analog or switch data.
•
•
•
•
•
•
Function, pin-out, speed and drive compatibility with
54/74LS logic family
Low power consumption characteristic of CMOS
High drive current outputs:
(lOL = 24 mA @ VOL = O.5V) for direct bus interface
Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
Wide operating voltage range:. 4.5V to 5.5V
Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage (jue to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLE
PIN CONFIGURATIONS
'682 and '684
INPUTS
P>Q
Vee
PO
p;Q
ao
07
P1
P7
01
06
P2
P6
02
05
P3
P5
03
04
GND
P4
OUTPUTS
DATA
ENABLES
P,O
P=O
P>O
P9
X
X
X
H
H
I
p;;a P50
NOTES: 1. The last 3 lines of the function table apply only to the device
having enable inputs. i.e., ·686.
2. The Po
Vcc
<31
PO
G2
ao
07
p;;o
P1
P7
01
NC
NC
Q6
P2
02
05
P3
03
04
GND
P4
P6
P5
NC-No internal connection
c8SAMSUNG
Electronics
755
KS54HCTL~~,6:'82 1684 1686
KS74HCTLS
Ij
11
',8-8it Magnitude
Comparators
LOGIC DIAGRAMS
'682 or '684
~
PO
00
~
-
.....
~
~
...
~~
V
~
P1
01
P2
02
P3
03
P4
04
P5
05
P6
06
P7
o
(2)
(6)
(19)
-
....
(7)~
~
V
(8)
-
....
I
,9,22
...
F=t-
~
(12)
--
~->-
~
y
(13)
.....
114'~
...
(15)
~t:::1
....
7~
"
.--L.r
F=I }:
I'I
c8SAMSUNG
1:1~""r_...i,,o
(1)
~~
.....
&
(17)
-t>v
~
756
.KS74HCTLS
KS54HCTLS68216841686
LOGIC DIAGRAMS
8·Bit Magnitude
Comparators
(continued)
'686
._-_
....
(23)
~
PO
00
Pl
(3)
(8)
P2
04
PS
os
P6
07
~
-
_.....
I
".122.....
~
~
~~
~
(16)
.
(17)
(20)
.....
....
.....
-"
~
(1)
~~
~
I?E?
18
I
~
t-I
.....
06 '
P7
-
-"
.....
(10)
P3
P4
~&-
-b
"I~
02
03
-
,,~
.....
01
(22)
-~
-"
~
(S)...
~
t:=I j '
II
I
.....
c8SAMSUNG
Electronics
-- ]:
~
I~
.-L..r
757
~S54HCTLS',tQ8"
2"684'/1',6'8' 6;~"'I\,'~~"~,"~'i'
KS74HCTLS,.~/l
8-Bit, M.lJQllitude
Compfl.tlJfArs
Absolute Maximum Ratings*
Supply Voltage Range Vcc, ....... -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vce +0.5V) ......... ±35 mA
Continuous Current Through
Vcc or GND pins .............. " ± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vce
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
,'f I 1
DC ELECTRICAL CHARACTERISTICS
Parameter
r
i
I
Test Conditions
------- ------- - - - - - - - - - - - - - - 1-----'
. Minimum High-Level
Input Voltage
I
Symbol
---------~-------
Maximum Low-Level
Input Voltage
: Maximum Low-Level
: Output Voltage
: (All Outputs)
VOH
VIN=VIH or VIL
10=- 2O/AA
lo=-6mA
a
- -----Inpuls)
Maximum Input
Current
(All other Inp~) __
f.aximum 3-Slale
Leakage Current
VOL
VIN=VIH or VIL
10=20/AA
10=12mA
10=24mA
2.0
2.0
0.8
0.8
0.8
V
V
0.1
0.33
0.5
0.1
0.4
Vce=Max
VIN=2.7V
VIN=O.4V
-0.2
-0.4
-0.2
-0.4
-0.2
-0.4
mA
liN
VIN=VCC or GND
±0.1
±1.0
±1.0
IAA
loz
Output Enable
=VIH
VouT=Vce or GND
±0.5
±5.0
±10.0
IAA
For '682:
VIN=GND (00-07)
VIN=Vee or GNP
(all other inputs)
3.5
3.5
3.5
mA
For '684 and '688
VIN=Vee or GND
10uT=OlAA
8.0
80.0
160.0
IAA
per input pin
VI=2.4V
other Inputs:
at Vce or GND
10uT=OlAA
2.7
2.9
3.0
mA
-,--
Icc
~----i
, Current
I
2.0
0.1
0.26
0.39
ISupply Current
I Additional Worst
ICase Supply
Guaranteed Limit
Vee -0.1
3.7
Maximum
i Ouiescent
54AHCT
+125°C Unit
= -55°C to
Vee -0.1
3.84
.--------_.-
~--
KS74AHCT
TA= -40°C to +85°C TA
--
Maximum Input
Current,
~82
Typ
VIL
,Minimum High-Level
i (Totem-pole Outputs)
TA=25°C
f - - - 1-----
I------~----f_
IOutput Voltage
(Vcc=5V±10% Unless Otherwise Specified)
r---
VIH
1
,,1/'fli
II
ll.lec
c8SAMSUNG
Electronics
Vee Vcc -0.1
4.2
3.93
0
V
V
758
~."t Magnitude
Comparators
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Conditionst
Maximum Propagation Delay,
<32 to P«l ('686 Only)
KS74HCTLS
+85°C
Vee=5.0V±10%
=-40°C to
Typ
KS54HCTLS
T.=-55°Cto +125°C
Vee=5.0V± 10%
31
36
38
44
tPHL
CL=50pF
CL=150pF
18 25
21 28
31
36
38
44
tpLH
CL=50pF
CL=150pF
22 32
25 35
38
43
45
51
tPHL
CL=50pF
CL=150pF
22 30
25 33
38
43
45
51
tPLH
CL=50pF
CL=150pF
15 20
18 23
25
30
30
36
tpHL
C,.=50pF
CL =150pF
15 20
18 23
25
30
30
36
tPLH
C=50pF
CL=150pF
~1
18 25
28
31
36
38
44
tpHL
CL=50pF
CL =150pF
18 25
21 28
31
36
38
44
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
5
Unit
Guaranteed Limits
18 25
21 28
tpLH
Maximum Propagation Delay,
G1 to P=Q ('686 Only)
T. =25°C
T.
Vee = 5.0V
CL=50pF
CL=150pF
Maximum Propagation Delay,
P or Q to P=Q
Maximum ~agation Delay,
PorQto>
.
(Input tr , t,~6 ns), HCTLS682, HCTLS684, HCTLS686
ns
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 1 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
759
I
6.881689
II
KS54HCTLS
KS74HCTLS
8-Bit Identity Comparators
•
FEATURES
DESCRIPTION
• Compares Two 8-Blt Words
• Choice of Totem-pole ('688) and open-drain ('689)
outputs ('688 is identical to '521)
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High drive current outputs:
(Iol 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized ·for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These identity comparators perform comparisons of two
8-bit binary or BCD words. The output of '688 is totempole while '689's are open-drain.
=
=
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
LOGIC DIAGRAM
PIN CONFIGURATION
G
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
Vee
(Positive Logic)
07
p=o
PO
00
07
P1
P7
01
06
P2
P6
05
02
P5
P3
03
04
GND
P4
06
P5
05-----,,~~
P4
04
02 ---- . - -......~-
FUNCTION TABLE
01--
INPUTS
DATA ENABLE
P.Q
G
......~
PO
OUTPUT
P=Q
P=Q
P>Q
P Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo <~Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
StorageTel']lperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per package, Pdt '...... 500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT
OV to Vee
Operating Temperature
Range
-KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55 ° C to + 1 25 ° C
Input Rise & Fall Times, t r , tf ......... Max 500 ns
* Absolute Maximum R.atings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
Typ
Minimum High-Level
Input Voltage
Maximum Low-Level
Input V.olt9ge
Minimum High-Levell
Output Voltage
('688 only)
Maximum Low-Level
Output Voltage
Maximum Input
Current
Maximum 3-State
Leakage Current
('689 only)
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
KS54HCTLS
KS74HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
VIH
2.0
2.0
2.0
V
VIL
0.8
0.8
0.8
V
Vee -0.1
3.84
Vee -0.1
3.7
V
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
±0.1
±1.0
±1.0
lolA
±0.5
±5.0
±10.0
lolA
8.0
80.0
160.0
lolA
2.7
2.9
3.0
mA
VOH
VIN=VIH or VIL
10=- 2OIolA
10= -6mA
VOL
VIN = VIH or VIL
10= 2OIolA
10=12mA
10=24mA
hN
VIN=Vee or GND
loz
VIN=VIH or VIL
Vee Vee -0.1
4.2
3.98
0
VouT=Vee
Icc
.6. Icc
VIN=Vee or GND
10UT=01olA
per input pin
VI=2AV
other Inputs:
at Vee or GND
10UT=01olA
=8SAMSUNG
Electronics
761
I
KS54HCTLS
KS74HCTLS.
6,.
88/689
/1
~~;:,8-Bit Identity Comp~(ators
(Input tr • tf~6 ns). HCTLS688
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol ('·.lndltlons t
KS74HCTLS
KS54HCTLS
T. =25°C
T.=-40°Cto +85°C T. - -55°C to +125°C
Vee = S.OV
Vee=S.OV% 10%
Vee = 5.0V %10%
Typ
Maximum Propagation Delay.
P to P=Q
Maximum Propagation Delay.
Q to P=Q
Maximum Propagation Delay.
G to P=Q
Guaranteed Limits
tpLH
CL=50pF
CL=150pF
16 22
19 25
28
33
33
39
tpHL
CL=50pF
CL=150pF
16 22
19 25
28
33
33
39
tpLH
CL=50pF
CL=150pF
16 22
19 25
28
33
,33
39
tpHL
CL=50pF
CL=150pF
16 22
19 25
28
33
33
39
tpLH
CL=50pF
CL=150pF
15 20
18 23
25
30
30
36
tpHL
CL=50pF
CL=150pF
15 20
18 23
25
30
30
36
Maximum Input Capacitance
CIN
Power Dissipation Capacitance·
Cpo
Unit
ns
ns
ns
pF
5
pF
• Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 1 fin.
t For AC switching test circuits and timing waveforms see section 2.
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Condltlons t
(Input t r • tf~6 ns). HCTLS689
T. =25°C
Vee=5.0V
KS74HCTLS
KS54HCTLS
T. = -40°C to +85°C T. = -55°C to +125°C
Unit
Vee=5.0V:t 10%
Vee=5.0V:t10%
Typ
Maximum Propagation Delay.
P to P=Q
Maximum Propagation Delay.
to P='O
o
Guaranteed Limits
tpLH
CL=50pF
CL=150pF
24 31
27 34
37
42
43
49
tPHL
CL=50pF
CL=150pF
19 26
22 29
32
37
38
44
tpLH
CL=50pF
CL=150pF
24 31
27 34
37
42
43
49
tpHL
CL=50pF
CL=150pF
19 26
22 29
32
37
38
44
tpLH
CL=50pF
CL=150pF
23 29
27 32
35
40
41
47
tPHL
CL=50pF
CL=150pF
18 24
21 27
30
35
36
42
Maximum Propagation Delay.
G to P=Q
Maximum Input Capacitance
CIN
Power Dissipation Capacitance·
Cpo
5
ns
ns
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo VCC 1 fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
762
KS54HCTLS
KS74HCt'i..S
793
/794
. /.
8-Bit ',Latch/Register
1
with Readback
FEATURES
DESCRIPTION
• 1/0 port configuration enables output data back onto
input bus
.
• Latch ('793) and and Register (,794) options
• Function, pin-out, speed and drive compatibility with
54/74lS logic far:nily
• low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(IOl 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TIL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTlS: - 40°C to + 85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These are 8-bit latches/registers that allow temporary
storage and retrieval of data on a bus. This operation is
important in control algorithms which make decisions based on the previous status of output controls. Rather than
storing a redundant copy of the output data in memory,
simply reading the register as an I/O port allows the data
to be retrieved from where it has been stored in a '793
or '794, for verification and/or updating.
=
=
The data is loaded in the registers on the positive-edge
of the clock (CLK) for the '794. The data is passed through
the '793 when E is high, and it is latched when E goes low
The output control (OC) is used to enable data on the DO-D7
pins. when OC is low the output of the latches/registers
is enabled on DO-D7, enabling D as an output bus so that
the host can perform a read operation. When OC is high,
DO-D7 are inputs to the latcheslregisters configuring D as
an input bus.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet· maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS dev!ces
without any external components,
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
PIN CONFIGURATIONS
'793
6C
vee
DO
00
01
02
01
02
03
04
FUNCTION TABLES
'793
:
E
L
L
Ht
H
05
06
07
E
OC
Q
D
L
H
L
H
Qo* *
Qo**
D*
D
Output, Q
Input
Output, Q*
Input
In this case the output of the latch feeds the input, and a "race"
condition results.
* * Qo represents the previous "latched" state.
t This transition is not a normal mode of operation and may produce hazards.
*
'794
DC
Vee
DO
00
Q1
01
02
03
04
05
06
07
GNO
02
03
04
05
06
07
ClK
'794
ClK
OC
LorHod
LorHod
L
H
L
H
t
t
Q
Qo
Qo
Qo
D
D
Output, Q
Input
Output, Q*
Input
* In this case the output of the register is clocked to the inputs
and the overall Q output is unchanged at Qo.
c8SAMSUNG
Electronics
763
I
1794
KS54HCTLS 79'3~
KS74HCtL~'.
I,
8-Bit LatcfJ/~lfJgister
with Rea:dback
LOGIC DIAGRAMS
'793
DO
'794
(2)
DO
(2)
01
(3)
02
(4)
01
(3).
02
(4)
03
(5)
03
(5)
04
(6)
D4
(6)
05
(7)
05
(7)
De
(6)
D6
(8)
07
(9)
07
(9)
(11)
c8SAMSUNG
Electronics
.
.
E
00
(11) eLK
KS54HCTLS
KS74HCTLS
7931794
1
8-Bit Latch/Register
with Readback
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oCfrom 65°C to 85°C
Supply Voltage Range Vee, ....... -0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins ............... , ±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Recommended Operating Conditions
Supply Voltage, Vee . . . . . . . . . . . . . . 4.5V to 5.5V
DC Input & Output Voltages·, VIN, Vour .. OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, fr, tf ......... Max 500 ns
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vee=5V±10% Unless Otherwise Specified)
Ta=25°C
Test Conditions
Typ
KS74HCTLS
KS54HCTlS
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20,..A
10= -6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20,..A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
,..A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vee or GND
±0.5
±5.0
±10.0
,..A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
,..A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
Alec
VIN=Vee or GND
10ur=OjAA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=0,..A
=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
765
I
1794
'8~8;t L~,fJ:trlJfegis'er
KS54HCTI.,$;<193
KS74HCTLS,'
I.
with
Re.sU.ck.
- -4.,""
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Condltlonst
(Input tr , tt~6 ns), HCTlS793, 794
KS74HCTLS
KS54HCTLS
T.=25°C
T.= -40°C to +85°C T.=-55°Cto +12SoC
Unit
Vee 5.0V
Vcc=5.0V:10%
Vcc ... 5.0V: 10%
=
Typ
Maximum Clock Frequency
('794 only)
Maximum Propagation Delay,
D to Any a ('793 only)
Maximum Propagation Delay,
CLK/E to Any a
Maximum Disable Time,
OC to D
Minimum Pulse Width,
ClK/ E High or low
Minimum
Setup Time
Minimum
Hold Time
D before
D after.
50 40
35
30
Cl=50pF
tplH
Cl=150pF
14 18
17 21
23
28
27
33
tpHl
CL=50pF
Cl=150pF
14 18
17 21
23
28
27
33
tPLH
CL=50pF
Cl=150pF
15 20
18 23
25
30
30
36
tpHL
Cl=50pF
Cl=150pF
15 20
18 23
25
30
30
36
20
23
20
23
25
30
25
30
30
36
30
36
ns
20
20
25
25
30
30
ns
10 15
18
20
ns
8 10
13
15
10 15
18
20
8 10
13
15
0
0
0
tw
E~
('793)
D before
ClKt(,794)
E~
('793)
tau
th
Dafter ClKt
(,794)
Maximum Input Capacitance
Maximum Output Capacitance
Power Dissipation Capacitance *
~
trilax CL=50pF
Cl=50pF 15
tPZH
Cl=150pF 18
Rl=1kO
r-(C=low Cl=50pF 15
tPZl for '793) CL=150pF
18
, tPHZ Rl=1kO, CL=50pF 1- 15
tpLZ (C=low for '793)
15
Maximum Enable Time,
oc to D
Guaranteed Limits
0
ns
ns
ns
ns
CIN
5
pF
COUT
Cpo
10
pF
ns
determines the no-load dynamic power dissipation: PD==CPD Vee' fin,
For AC switching test circuits and timing waveforms see section 2,
• CPD
t
c8SAMSUNG
Electronics
766
KS54HCT!.S
KS7 4HCTLS
821'I~1822
10-Bit Bus Interface Flip-Flops
with 3-State Outputs
Preliminary Specifications
FEATURES
DESCRIPTION
• Functionally Equivalent to AMO's Am29821 and
Am29822
• .Provides Extra Data Width Necessary for Wider Address/Data Paths or Buses with Parity
• Power-Up High-Impedance State
• Function, pin-out, speed and drive compatibility with
54/74lS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive current
(lOl =24 mA @ VOL =O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 1D.bit bus·interface flip·flops feature three-state outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. They are suitable for implementing wider buffer registers, I/O ports, bidirectional
bus drivers with parity, and working registers.
PIN CONFIGURATIONS
'821
Oc
Vee
10
20
3D
40
50
60
80
90
1(\0
10
20
30
40
50
60
70
80
90
100
3NO
ClK
7D
All of the flip-flops are edge-triggered and Ootype. On the
positive transition of the clock the a outputs on the '821
will be true, and on the '822 will be complementary to the
data input.
A buffered output-control input can be used to place the
ten outputs in either a normal logic state (high or low levels)
or a high-impedance state. The high-impedance state and
increased drive pr-ovide the capability to drive the bus lines
in a bus-organized system without need for interface or
pull-up components. The output control (OC) does not affect the internal operation of the flip-flops. Old data can
be retained or new data can be entered while the outputs
are in the high-impedance state.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internai diode clamps to Vce and
ground.
FUNCTION TABLES
1Each Flip-Flop)
'821
'822
DC
10
20
3D
40
60
70
80
90
100
GNO
Inputs
1--.
Vee
10
20
30
40
50
SO
70
80
90
100
ClK
ClK
0
L
L
L
L
t
t
L
H
H
H
X
L
X
X
X
Q
H
L
00
00
Z
'822
I
Inputs
Output
OC
ClK
0
Q
L
L
L
L
t
t
H
L
H
H
c8SAMSUNG
Electronics
Output
OC
L
H
X
L
X
X
X
00
00
Z
767
I
1O-Bit BuslnMr#st!eFlip~Flops
with 3-State Outputs
KS54HCTLS821'822
KS74HCTLS
'j
LOGIC DIAGRAMS
'821
OC
'822
(1)
oc
eLK
(1)
ClK
(23)
(2)
10
(22)
20
3D
40
(3)
(21)
(4)
(20)
(6)
(7)
70
70
(16)
(9)
80
80
(10)
(20)
(6)
(7)
(8)
(9)
(17)
(16)
(11)
----
c8SAMSUNG
Flp('trnni('!::.
(15)
90
90
(14)
100
(5)
(21)
10
20
30
40
50
60
70
80
80
(15)
90
(4)
(18)
60
60
(8)
(3)
(19)
50
50
(17)
70
40
40
(18)
613
30
3D
(5)
(2)
(22)
20
20
(19)
50
(23)
10
10
(10)
(14)
100
100
(11)
90
100
768
KS54HCTLS
KS74HCTLS
821'822
,~
10-Bit Bus Interface Flip-Flops
with 3-State Outputs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to
Supply Voltage Range Vcc,
-0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vcc +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vcc +0.5V)
±20 mA
Continuous Output Cu'rrent Per Pin, 10
(-0.5V < Vo < Vcc +0.5V)
±70 mA
Continuous Current Through
Vcc or GND pins
± 250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vcc
4.5V to 5.5V
DC Input & Output Voltages·, VIN, VOUT .. OV to Vcc
Operating Temperature
Range
·KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, t r , tf
• Absolute Maximum Ratings are those values beyond
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
Unused inputs must always be tied to an appropriate logic
voltage level (either Vcc or GND)
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vcc=5V±10% Unless Otherwise Specified)
Ta =2S0C
Test Conditions
85~C
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta = -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
MiniTum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20!-,A
10=-6mA
Vee -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10 = 20!-,A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
!-,A
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VOUT=VCC or GND
±0.5
±5.0
±10.0
!-,A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
!-,A
2.7
2.9
3.0
mA
~dditional
Worst
I~ase Supply
Current
b.lcc
VIN=VCC or GND
10uT=0!-,A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0!-,A
.=8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
769
I
211822
1 q~'t Bus Interface. Flip..FIOps
KS54HCTLSs'G
KS74HCTLS ~
w1fh~3-State Outputs ',1' ~.~
AC ELECTRICAL CHARACTERISTICS
(Input tr ,
tf~6 ns). HCTlS821, HCTlS822
KS74HellSel.
Characteristic
Symbol
-
Maximum Propagation Delay,
ClK to any Q
CL=50pF
40 35
30
25
tpLH
CL=50pF
CL=150pF
15 20
18 23
25
30
30
36 -
tpHL
CL=50pF
CL=150pF
15 20
18 23
25
30
30
36
SOPF
CL =150pF
18 24
21 27
30
35
36
42
CL=50pF
CL=150pF
18 24
21 27
,,--
30
35
36
42
18 24
-18 24
30
36
30
36
12 16
20
24
,,---
tPZL
i-
RL = 1 kO
-- - - - - f - - - - - -
------~
----
tpHZ RL=1 kO
Maximum Output Disable
Time, OC to any Q
tpLZ CL=50pF
- - - - - - - - - -- - - - Minimum Pulse Width,
tw
ClK High or low
-
----------=--------~--
~
- - - --
- - - - >------- - - - - - - - - - - , , - - - - - -
Minimum Setup Time,
Data before ClKt
-
---
--- - --------- ---
---
5
CIN
Cpo
OC=Vee
OC=GND
----
ns
------
- ---.
ns
24
1---
a a
th
ns
ns
_.-
20
ns
-- _._-"
----
Maximum Output Capacitance COUT OC=Vcc
1-_
Power Dissipation
'Capacitance· (per stage)
MHz
- - r-------
12 16
tsu
c-----------
Minimum Hold Time,
Data after ClKt
- - - - - - - - - - _....•. _-- _.. _-Maximum Input Capacitance
~---~~------.-
f max
tPZL
Maximum Output Enable
Time, OC to any Q
.
Guaranteed limits
Typ
Maximum Operating Frequency
KS54HelLS
T. =2!OC T.= -400C to +85°C T.= -55°C to +125 0C
Unit
Vee= .OV
Vec=5.0V±10%
Vee=5.0V± 10%
Condltlons t
10
a
0
~O
---
---
----
pF
-_._---_._---_._-_...
--1---- - - - 1------------------- - - - - - - - - -
5
ns
-- - - - - - - - - - - -
- -_
..
_._-
pF
----
pF
* Cpo determines the .no-Ioad dynamic power dissipation: Po=Cpo Vee' fin.
t For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
770
KS54H,CTLS
KS74HCTLS
I
8231824
..
1~
9-Bit Bus Interface Flip-Flops
with 3-State Outputs
FEATURES
DESCRIPTION
• Functionally Equivalent to AMO's Am29823 and
Am29824
• Provides Extra Data Width Necessary for Wider Address/Data Paths or Buses with Parity
• Power-Up High-Impedance State
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• low power consumption characteri!5tic of CMOS
• 3·State outputs with high drive current
(IOL 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs Interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTlS: - 40°C to + 85°C
KS54HCTlS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 9-bit bus interface flip-flops feature three-state outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. They are suitable for implementing wider buffer registers, I/O ports, bidirectional
bus drivers, parity bus interfacing and working registers.
=
With the clock enable (CLKEN) low, the D-type edgetriggered flip-flops enter data on the low-to-high transitions
of the clock. Taking CLKEN high will disable the clock buffer, thus latching the outputs. The '823 has non inverting
o inputs and the '824 has inverting 0 inputs. Taking the
CLR input low causes the nine Q outputs to go low independently of the clock.
'
=
A buffered output-control input (OC) can be used to place
the ten outputs in either a normal logic state (high or low
levels) or a high-impedance state. The high-impedance
state and increased drive provide the capability to drive
the bus lines in a bus-organized system without need for
interface or pull-Up components. The output control does
not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in the high-impedance state.
These devices provide. speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
PIN CONFIGURATIONS
'823
oc
Vee
10
10
20
30
40
50
3D
60
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLES
70
80
90
90
'823
INPUT
CLKEN
CLK
Ci:R
GNo
'824
DC
10
20
3D
Vee
4
10
20
30
40
50
60
70
SO
90
a:KEN
CLK
c8SAMSUNG
Electronics
I
OUTPUT
OC
CLR
CLKEN
ClK
0
a
L
L
L
L
H
L
H
H
H
X
X
L
L
H
L
H
L
X
X
X
t
t
X
X
H
L
X
X
00
Z
'824
INPUTS
OUTPUT
OC
ClR
ClKEN
ClK
0
a
L
L
L
L
H
L
H
H
H
X
X
X
L
L
H
t
t
H
L
L
L
H
X
X
X
X
X
X
00
Z
771
I
KS54HCTLS;-S2
KS74HCTLS
3'824'
/j
9-Bit Bus Interfa'ce Flip-Flops
with 3-State Outputs
LOGld DIAGRAMS
'823
'824
(23)
(22)
(211
120)
(181
(UI)
(17)
(US)
(15)
c8SAMSUNG
Electronics
'
10
20
3Q
40
(23)
10
(22)
20
(21)
3Q
1201
40
(19)
50
50
eo
70
eo
(18)
(17)
(18)
(15)
to
eo
70
eo
to
772
KS54HCTLS
KS74HCTLS
823'824
,~
9-Bit Bus Interface Flip-Flops
with 3-State Outputs
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N):, -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ., . . . .
-0.5 to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V)
±20 rnA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vec +0.5V)
±20 rnA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vcc +0.5)
±70 rnA
Continuous Current Through
Vcc or GND pins
±250 rnA
Storage Temperature Range, TSIg ... -65°C to +150°C
Power Dissipation Per Package, Pdt . .
500 mW
Recommended Operating Conditions
Supply Voltage, Vce
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Max 500 ns
Input Rise & Fall Times, tr , tf ...
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logiC
. voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
(Vce=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta= -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2'.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20/AA
10= -6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo= 2O/AA
lo=12mA
lo=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
/AA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vce or GND
±0.5
±5.0
±10.0
/AA
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
/AA
2.7
2.9
3.0
rnA
Additional Worst
Case Supply
Current
b.lee
VIN=Vee or GND
louT=O/AA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0/AA
c8SAMSUNG
Electronics
Vee Vce-0. 1
4.2
3.98
0
773
I
9~/t
KS54HCTLS'823 1824 "
KS74HCTLS "/~
.
AC ELECTRICAL CHARACTERISTICS
CMr.cterlstlc
Bu, Interface Flip-Flops
with3-State Outputs'" H
(Input
Symbol Condltlons t
tr.
t,<6 ns). HCTlS823. HCTlS824
KSS4HCTLS
KS74HCTLS
T.-2S·C
TA- -40·C to +8S·C TA"" -sS·C to +12S·C
Unit
Vcc-5.0V
Vec=S.OV:t 10%
Vee-S.OV:t 10%
Typ
Maximum Operating Frequency
Maximum Propagation Delay.
ClK to any
a
Maximum Propagation Delay.
CLR to Any
a
CL-50pF
40 35
30
25
tpLH
CL-50pF
CL-150pF
15 20
18 23
30
36
tpHL
CL=50pF
CL'""150pF
15 20
18 23
25
30
25
30
tpLH
CL=50pF
CL-150pF
17 22
20 25
28
33
34
40
CL-50pF
18 24
CL-150pF 21 27
30
35
36
42
18 24
21 27
30
35
36
42
18 24
30
36
18 24
30
36
tpZL
Maximum Output Enable
Time. ~ to any
-
Maximum Output Disable
Time. be to any
-tpHZ
tpLZ
a
a
CLR low
Minimum
Pulse Width ClK high or low
ClR Inactive
Minimum
Setup Time 6ata
Before ClK ClKEN high
or low
Minimum Hold Time,
ClKEN or data after ClKt
Gu.r.nteed Limits
fmax
RL-1kO
CL-50pF
CL-150pF
tpZL
RL=1kO
CL=50pF
t.
tau
It!
12 16
20
24
20
24
12 16
20
24
12 16
20
24
20
24
0
0
Maximum Input Capacitance
CIN
Maximum Output Capacitance COUT Output Disabled
Power Dissipation
Cpo OC-Vcc
Capacitance* (per stage)
OC=GND
0
0
ns
ns
ns
ns
I
I
ns
ns
5
pF
pF
5
30
pF
* CPD determines the no-load dynamic power dissipation: PD=CPD Vee' fin,
I
I
10
t For AC switching test circuits and timing waveforms see section 2,
c8SAMSUNG
Electronics
ns
30
36
12 16
12 16
MHz
KS54HCTLS
KS74HCTLS
825/826
. . '{
8-Bit Bus Intef.~~ce Flip"!'Flops
with 3-State (j-tJtputs
FEATURES
DESCRIPTION
• Functionally Equivalent to AMD's Am29825 and
Am29826
• Improved IOH Specifications
• Multiple Output Enables,Allow Multiuser'Control of
the Interface
• Power-Up High-Impedance State
• Function, pin-out, speed and drive compatibility with
54174lS logic family
• Low power consumption characteristic of CMOS
• 3-State outputs with high drive currem .
(IOL 24 rnA @ VOL = O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Cl'laracterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 8-bit bus interface flip-flops leature three-state outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. They are suitable for implementing multiuser buffer registers, 1/0 ports, bidirectional bus drivers and working registers.
=
PIN CONFIGURATIONS
'825
OCl
OC2
10
20
3D
40
50
60
70
80
Vee
Oc3
10
20
30
40
50
60
70
80
Ci:Fi
CLKEN
GNO
ClK
With the clock enable (CLKEN) low, all D-type edgetriggered flip-flops enter data on the low-to-high transitions
of the clock. Taking CLKEN high will disable the clock buffer, thus latching the outputs. The '825 has non-inverting
D inputs and the '826 has inverting is inputs. Taking the
CLR inputs low causes the eight Q outputs to go low independently of the clock.
Multiuser buffered output-control inputs (OC1 , 0':2, and
OC3) can be used to place the eight outputs in either a
normal logic state (high or low level) or a high-impedance
state. The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized
system without need for interface or pull-up components.
The output controls do not affect the internal operation of
the flip-flops. Old data can be retained or new data can
be entered while the outputs are in the high-impedance
state.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
'826
OC1
OC2
10
20
3D
45
50
65
70
85
Vee
Oc3
10
20
30
40
50
60
70
80
CLR
ClKEN
GNO
ClK
c8SAMSUNG
Electronics
775
I
KS54HCTLS
KS74HCTLS
B·25'826
'j
8-Bit Bus Interface Flip-Flops
with 3-State Outputs
FUNCTION TABLES
'826
'825
'nputs
oc·
L
L
L
L
H
ClR
L
H
H
H
X
ClKEN
X
L
L
H
X
Inputs
Output
ClK
X
t
t
X
X
D
X
H
L
X
X
Q
OC·
L
L
L
L
H
L
H
L
00
Z
Output
ClR
ClKEN
ClK
0
Q
L
H
H
H
X
X
X
X
t
t
L
H
X
H
L
L
L
H
X
X
t
X
00
Z
X
* OC = H if any of OC1, OC2, or OC3 are high.
* OC = H if any of OC1, OC2, or OC3 are high.
OC = l of OC1, OC2, and OC3 are low.
OC = l of OC1, OC2, and OC3 are low.
LOGIC DIAGRAMS
'826
'825
(22)
10
b--d">--4-..:.:(2;,...:1)_ 20
(20)
30
b--d:>--+-(_19_)_ 40
b-~~+_(18_)_ 50
c8SAMSUNG
Electronics
(22)
10
(21)
20
(~O)
10--<1 ~>---t--- 30
(19)
40
~.~~----, __
(18_)_ 50
(17)
60
(17)
60
(16)
70
(16)
70
(15)
80
(15)
P------'--- 80
776
KS54HCTLS
KS74HCTLS
8251826
I
8-Bit Bus Interface Flip-Flops
with 3-State Outputs
j
Absolute Maximum Ratings*
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Supply Voltage Range Vee, ..
-0.5V to + 7V
DC Input Diode Current, ilK
(VI < "':'0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) . .
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, Tstg ... ~65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
Recommended Operating Conditions
Supply Voltage, Vee . .
4.5V to 5.5V
DC Input & Output Voltages", VIN, Your
OV to Vee
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, t r , tf . . . . . . .. Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta = -40°C to +85°C Ta =-55°Cto +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
fy1aximJjm Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN = VIH or VIL
10=-20J.lA
10=-6mA
Vee -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=20",A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum InputCurrent
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
J.lA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
Vour=Vee or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
J.lA
2.7
2.9
3.0
mA
Additional worst
Case Supply
Current
,t,.lee
VIN=Vee or GND
10ur=0J.lA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10ur=0J.lA
=8SAMSUNG
Electronics
Vee Vee -0.1
3.98
4.2
0
I
777
I
KS54HCTL~t'62
51826
81Bit Bus.lnterface . Flip-Flops
wi,h 3-State Outputl
KS74HCTLS···· -
,j~-
.,~...... i .
AC ELECTRICAL CHARACTERISTICS
(Input tr • tf~6 ns), HCTLS825. HCTLS826
Conditions t
KS74HCTlS
KS54HCTlS
T =25°C
V;c=5.0V T.= -40°C to +85°C T.= -55°C to +125°C
Unit
Vcc=5.0V±10%
Vcc=5.0V± 10%
Characteristic
Symbol
Maximum Operating Frequency
fmax
Cl==50pF
40 35
30
25
tplH
Cl==50pF
Cl=150pF
15 20
18 23
25
30
30
36
tpHl
Cl==50pF
Cl ==150pF
15 20
18 23
25
30
30
36
tplH
Cl==50pF
Cl ==150pF
17 22
20 25
28
33
34
40
-Cl==50pF
Cl==150pF
18 24
21 27
30
35
36
42
Cl=50pF
CL==150pF
18 24
21 27
30
35
36
42
18 24
30
36
18 24
30
36
12 16
20
24
12 16
20
24
12 16
20
24
12 16
20
24
12 16
20
24
Typ
Maximum Propagation Delay.
ClK to any Q
Maximum Propagation Delay.
CLR to Any Q
Maximum Output Enable
Time. OC to any Q
tPZl
f----
RL==l kG
tPZl
Maximum Output Disable
Time. OC to any Q
CLR low
Minimum.
Pulse Width ClK high or low
CLR Inactive
Minimum
Setup Time Data
Before ClKf CLKEN high
or Low
tpHZ
RL == 1 kG
r--tpLZ CL==50pF
tw
tsu
Guaranteed limits
MHz
ns
ns
ns
I
ns
I
ns
ns
I
i
i
Minimum Hold Time.
CLKEN or data after ClKt
0
CIN
5
pF
Maximum Output Capacitance COUT
10
pF
Power Dissipation
Capacitance" (per stage)
5
30
Cpo
• Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee' fint For AC switching test circuits and timing waveforms see section 2.
c8SAMSUNG
Electronics
0
0
i ns
th
Maximum Input Capacitance
0
!
i
~
778
KS54HCTLS
KS74HCTLS'
8411°42'
. 10 ,.'
. z "_.
10-Bit Bus Interface D-Type
Latche.s with 3-~tate Outputs
FEATURES
DESCRIPTION
• Bus-Structured Pinout
• Provides Extra Bus D!'i'!!r!~ !.atche!.i
• Necessary for Wider Address/Data Paths or Busr,s
with Parity
• Power-Up High-Impedance State
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption ,characteristic of CMOS
• 3-State outputs with high drive current
(IOl 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: - 40°C tq + 85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 1O-bit bus interface latches feature three state outputs designed specifically for driving highly capacitive or
relatively low-impedance loads, They are suitable for implementing wider buffer registers. I/O ports, bidirectional
nus drivers, and working registers.
=
=
PIN CONFIGURATIONS
'841
oc
Vee
10
20
10
20
30
40
50
60
3D
40
50
60
7D
80
90
100
GNO
70
-----
40
55
60
70
80
The output control does not affect the internal operation
of the latches. Old data can be retained or new data can
be entered while the outputs are off.
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vcc and
ground.
FUNCTION TABLES
'841
INPUTS
E
oc
3D
A buffered output control (OC) input can be used to place
the ten outputs in either a normal logic state (high or low
levels) or a high-impedance state. The high-impedance
state and increased drive provide the capability to drive
the bus lines in a bus-organized system without need for
interface or pull-up components.
80
90
100
'842
10
25
The ten latches are transparent Ootype. The '841 has
noninverting data (0) inputs and the '842 has inverting (0)
inputs.
10
20
30
40
50
60
70
80
90
90
105
100
GNO
E
c8SAMSUNG
Electronics
'
OUTPUT.
OC
E
0
Q
L
L
L
H
H
H
L
X
H
L
X
X
H
L
00
Z
'842
INPUTS
OUTPUT
OC
E
0
Q
L
L
L
H
H
H
L
X
H
L
X
X
L
H
00
Z
779
·1
KS54HCTLS
,841/842
.
K~74HCTLS····
10-Slt Bus. Interface D-Type
Latches with 3~State Outputs
LOGIC DIAGRAMS
'a41
oc
'842
(1)
oc
(23/
(2)
(3)
(4)
(21/
(5)
(6)
(T)
(8/
(9)
40
50
60
60
(17)
TO
(16)
TO
80
80
(15)
90
(10)
(11)
c8SAMSUNG
Electronics
TO
eo
90
90
(14/
100
3D
50
(18)
60
30
40
(19)
50
20
20
(20)
40
(2)
10
10
(22)
3D
(23)
10
10
20
(1)
(3)
(4)
(5)
(6)
(T)
(8/
(9)
(10)
(22)
(21/
(20)
(19)
(18)
(17)
(16)
(15)
(14)
100
100
(11)
20
30
40
50
60
TO
80
90
100
780-
KS54HCTLS
KS74HCTLS
841',~'842
10-Bit Bus Interface D-type
Latches with 3-State Outputs
Absolute Maximum Ratings*
- Supply Voltage Range Vee,
.... -O.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous Output CU'r,ent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Curr~nt Through
Vee or GND pins . . . . . . . .
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vcc . . . . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. OV to Vcc
Operating Temperature
Range
-KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times, tr, tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V±10% Unless Otherwise Specified)
Ta =25°C
Symbol Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta =-40°Cto +85°C Ta=-55°C to +125°C Unit
Guaranteed Limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=- 2OIAA
10=-6mA
Vce -0.1
3.84
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10= 2OIAA
10=12mA
10=24mA
0.1
0,26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
liN
VIN=Vee or GND
±0.1
±1.0
±1.0
IAA
Maximum 3-State
Leakage Current
loz
Output Enable
=VIH
VouT=Vee or GND
±0.5
±5.0
±10.0
",.A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",.A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
.6.lee
VIN=Vee or GND
10uT=0",.A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=01AA
c8SAMSUNG
Electronics
Vee Vee -0.1
4.2
3.98
0
J81
I
/842
J 0-8it 8us' Interf4c.~,tJ· Type
KS54HCTLS~:~841
KS74HCTLS,
£afcIJeswith3-Stare:,''(}utputs
AC ELECTRICAL CHARACTERISTICS ,(Input tr , tf~6
Characteristic
Condltions t
Symbol
ns), HCTLS841, HCTLS842
KS74HCTLS
KS54HCTLS
T.=25°C T.= -40°C to +85°C T.= -55°C to +125°C
V.cc=5.0V
Vc c =5.0V:t:10%
Unit
Vcc =5.0V:t: 10"10
Typ
tPLH
CL = 50pF
Guaranteed Limits
1 5 20
25
30
Maximum Propagation Delay, ~_---J...::C~L,--=--.:1:...:::5:...:0:..!:p.:.-.F_ _ __+_1.:.-.8=+2=-3=--+------.:3::..:0=------,--+-~-----=3~6-----1 OS
Data to Q
CL =50pF
15 20
25
30
tpHL CL = 1 50pF~
18 23
30
36
tPLH CL =50pF
21 28
35
42
Maximum Propagation Delay. 1--_.......j..::C~L'--=--.:1:...:::5:..::0..':.P.:....F_ _ _+2=-4+3::..:1~____4.:....:0=---_ _-+-___4_8_ _ _--l ns
E to any
tpHL CL=50pF
21 28
35
42
CL =150pF
24 31
40
48
a
30
36
35
42
Maximum Output Enable
ns
Time, OC to any
CL =50pF
18 24
30
36
~_ _ _ _ _ _ _ _ _+-t_PZ_L-+_ _~_C~L_=_1_5_0~P_F~2_1+=2_7~_ _ _3_5_____r-____4_2______ ~-
a
~1=8+=2~4_+_---=3=0---~---3=-6=----~ ns
Maximum Output Disable
Time, OC to any
a
Minimum Pulse Width,
I--E H i g h ,
Minimum Setup Time,
Data before E.l
tsu
Minimum Hold Time,
Data after E~
Maximum Output Capacitance COUT
* Cpo
30
36
15 20
25
30
ns
12 16
20
24
ns
10
12
ns
6
Maximum Input Capacitance
Power Dissipation
Capacitance* (per stage)
18 24
Cpo
.
OC=Vcc
OC=GND
8
5
pF
10
pF
5
pF
30
determines the no-load dynamic power dissipation: PD=CPD Vee'
waveforms see section 2.
fin.
t For AC switching test circuits and timing
=8 !e!'lSUNG
782
KS54HCTLS
KS74HCTLS
843184.4.
1~
9-Bit Bus Interface D-Type
Latches with 3-State Outputs
FEATURES
DESCRIPTION
• Bus-Structured Pinout
• Provide Extra Bus Driving Latches
Necessary for Wider Address/Data Paths or Buses
with Parity
• Power-Up High Impedance
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption chai1lcteristic of CMOS
• 3-State outputs with high drive current
(IOL 24 mA @ VOL O.5V) for direct bus interface
• Inputs and outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 9-bit bus interface latches feature three-state outputs'designed specifically for driving highly capacitive or
relatively low-impedance loads. They are suitable for implementing wider buffer registers, I/O ports, bidirectional
bus drivers, parity bus interfacing and working registers.
=
=
PIN CONFIGURATIONS
'843
oe
vee
10
20
3D
40
50
60
10
20
30
40
50
60
70
80
90 ..
7D
80
90
eLR
PRE
GNO
E
'844
oe
1'0
215
3D
4D
5D
60
70
8D
915
Vee
10
20
30
40
50
60
70
80
90
ClR
PRE
GNO
E
c8SAMSUNG
Electronics
The nine latches are transparent D-type. The '843 has
non inverting data (D) inputs and the '844 has inverting i5
inputs.
A buffered output control (OC) input can be used to place
the nine outputs in either a normal logic state (high or low
levels) or a high-impedance state. The high-impedance
state and increased drive provide the capability to drive
the bus lines in a bus-organized system without need for
interface or pull-up components.
The output control (OC) does not affect the internal operation of the flip-flops. Old data can be retained or new data
can be entered while the outputs are off.
These devices provide speeds and drive capability
equivalent to their LSTTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and·
ground.
FUNCTION TABLES
'843
OUTPUT
INPUTS
PRE
CLR
OC
E
D
Q
L
H
H
H
H
X
X
L
H
H
H
X
L
L
L
L
L
H
X
X
H
H
L
X
X
X
L
H
X
X
H
L
L
H
00
Z
'844
OUTPUT
INPUTS
PRE
CLR
OC
E
D
Q
L
H
H
H
H
X
X
L
H
H
H
X
L
L
L
L
L
H
X
X
H
X
X
L
H
X
X
H
L
H
L
H
L
X
00
Z
783
I
KSS4HCTLS
KS74HCTLS
8431844
.
9-Bit Bus,·In'ertsJce D.. .Type
Latches with 3-State Outputs
LOGIC DIAGRAMS
'843
oc
'844
OC ~(...:.11_ _ _q~________--,
(11
PRE':...1..;;.41_~~_
PRE (:....14.:.:.)_~~)-,
CLR :.:.'1..;;.11---c~>,
10
20
3D
40
50
60
(21
10
(3)
20
(4)
30
(5)
40
(6)
(19)50
(7)
(181
50
(2)
(3)
(4)
(5)
(6)
m
60
60
(81
(17) 70
70
(9)
(16) 80
80
90 (10)
(15) 90
90 (10)
70
80
c8SAMSUNG
Electronics
(8)
(9)
(23)10
(22)20
:21)30
(20)40
(19)50
(18) 60
(17) 70
(16) 80
(15) 90
784
KS54HCTLS
KS74HCTLS
843/844
9-Bit Bus Interface D-Type
Latches with 3-State Outputs
Absolute Maximum Ratings *
Supply Voltage Range Vee.
-0.5V to + 7V
DC Input Diode Current, 11K
(VI < -0.5V or VI > Vee +0.5V)
±20 mA
DC Output Diode Current, 10K
(Vo < -0.5V or Vo > Vee +0.5V)
±20 mA
Continuous, Output Clirrent Per Pin, 10
(-0.5V < Vo < Vee +0.5V)
±70 mA
Continuous Current Through
Vee or GND pins
±250 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt
500 mW
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vee .. '
4.5V to 5.5V
DC Input & Output Voltages *, VIN, VOUT . . OV to Vee
Operating Temperature
Range
-KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times. tr , tf
Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vec=5V± 1 0% Unless Otherwise Specified)
Ta =25°C
Typ
KS74HCTLS
KS54HCTLS
Ta =-40°Cto +85°C Ta =-55°Cto +125°C Unit
Guaranteed limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
10=-20",A
10=-6mA
Vec -0.1
3.84
Vcc -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20",A
10=12mA
10=24mA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=VCC or GND
±0.1
±1.0
±1.0
",A
Maximum 3-State
Leakage CurIent
loz
Output Enable
=VIH
Vour=Vec or GND
±0.5
±5.0
±10.0
",A
Maximum Quiescent
Supply Current
Icc
8.0
80.0
160.0
",A
2.7
2.9
3.0
mA
Additional Worst
Case Supply
Current
~Ice
VIN=VCC or GND
10UT=01-'A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=0",A
c8~SUNG
Vee Vce -0.1
4.2
3.98
0
I
785
I
KS54HCTLS
KS74HCTLS
8431844
1
j
AC ELECTRICAL CHARACTERISTICS
Characteristic
9-Bit Bus Interface D-Type
Latches with 3-State Outputs
Symbol Condltlons t
(Input tr , tf~6ns), HCTLS843, HCTLS844
KS74HCTLS
KSS4HCTLS
T. =25°C
T.= -40°C to +8S o C T.= -55°C to +12SoC
Unit
Vcc=S.OV
Vcc=S.OV±10%
Vcc=S.OV:!: 10%
Typ
. Maximum Propagation Delay,
to
Maximum Propagation Delay,
E to any
a
~imum
Propagation Delay,
PRE to Q
Maximum Propagation Delay,
CLR to Q
tpLH
18 24
21 27
30
35
36
42
tPHL
c'L =50pF
CL=150pF
18 24
21 27
30
35
36
42
tPLH
CL=50pF
CL=150pF
2.1 28
24 31
35
40
42
48
tPHL
CL=50pF
CL=150pF
21 28
24 31
35
40
42
48
tpLH
CL=50pF
CL =150pF
23 30
26 33
38
43
46
52
tPHL
CL=50pF
CL=150pF
23 30
26 33
38
43
18 24
CL=50pF
CL=150pF 21 27
30
35
46
52
36 .
42
CL=50pF
18 24
CL=150pF 21 27
30
35
36
42
18 24
30
36
18 24
30
36
tpZH
Maximum Output Enable
Time, i5C to any
a
Maximum Output Disable
Time, 6C to any
a
Guaranteed Limits
CL= 50pF
CL=150pF
I--
RL=1kO
tPZL
tPHz
t----
tpLZ
RL=lkO
CL=50pF
ns
ns
ns
ns
ns
ns
Minimum Pulse Width,
E High
tw
15 20
25
30
ns
Minimum Setup Time,
Data after E~
tsu
12 16
20
24
ns
Minimum Hold Time,
Data before E ~
th
10
12
ns
Maximum Input Capacitance
6
C,N
Maximum Output Capacitance COUT
Power Dissipation
Capacitance (per stage)
*
t
Cpo
OC=Vcc
OC=GND
8
5
pF
10
pF
5
30
pF
Cpo determines the no-load dynamic power dissipation: PD=CPD Vee' fin.
For AC switching test circuits and timing waveforms see section 2.
c8
SAMSUNG SEMICONDUCTOR
786
KS54HCTLS B'AJ:IOA6
KS74HCTLS "'~/g..,.
8-Bit Bus Interface D-Type
Latches with 3-State Outputs
FEATURE
DESCRIPTION
• 3-state buffer-type outputs drive bus-lines directly
• Bus-structured pinout
• Provides extra bus driving latches necessary for
wider address/data paths or buses with parity
• Low power consumption characteristic of CMOS
devices
• 3-state outputs with high drive current (IOl = 24mA
@ VOL =O.5V) for direct bus interface
• Direct interface capability with TTL, NMOS and
CMOS devices
• Wide operating volage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
These 8-bit latches feature three-state outputs designed
specifically for driving highly capacitive or relatively low impedance loads. They are particularly suitable for implementing buffer registers, 1/0 ports, bidirectional bus drivers,
and working registers.
PIN CONFIGURATIONS
The eight latches are transparent D-type. The '845.has
noninverting data(D) inputs. The '846 has inverting D inputs. Since CLR and PRE are independent of the clock,
taking the CLR input low will cause the eight Q outputs to
go low. Taking the PRE input low will cause the eight Q
outputs to go high. When both PRE and CLR are taken low,
the outputs will follow the preset condition.
The buffered output control inputs (OC1, OC2, and OC3)
ean be used to place the eight outputs in either a normal
logic state (high or low levels) or a high-impedance state.
In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impendance state
and increased .drive provide the capability to drive the bus
lines in a bus-organized system without need for interface
or pull-up components. The output controls do not affect
the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are
in the high-impedance state.
'845
OC1
OC2
10
20
3D
40
50
60
Vrx
OC3
10
20
30
40
50
60
70
80
7D
8D
ClR
PRE
GND
E
These devices provide speeds and drive capability
equivalent to their LSTIL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TIL, NMOS and CMOS devices
without any external components.
All inputs and outputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
'846
OC1
Vrx
&:2
10
20
30
40
50
QC3
10
20
30
40
50
e~
eo
to
70
80
8~
ern
PRE
GNO
E
:8SAMSUNG
Electronics
787
I
KS54HCTLS
KS74HCTLS
84~/O""
J: 10 A6
8-Bit Bus Interface D-Type
Latches with 3-State Outputs
FUNCTION TABLE
'848
'845
INPUTS
OUTPUT
INPUTS
OUTPUT
-~
PRE
CLR
OC1
OC2
OC3
E
D
Q
L
H
H
L
L
L
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
H
H
X
X
X
H
H
H
X
L
L
L
L
L
L
x
x
x
X
X
H
X
H
X
H
X
X
X
PRE
CLR
OC1
OC2
OC3
E
D
Q
H
L
H
H
H
L
L
L
L
L
H
H
H
H
X
H
H
H
X
L
L
L
L
L
L
X
X
X
H
H
X
X
H
X
H
X
L
L
L
L
L
L
H
X
X
X
H
L X
X X
X X
X X
L
L
L
L
L
L
H
L
00
Z
Z
Z
x
x
x
X
X
X
L
X
X
X
L
H
H
L
H
L
X
X
X
X
00
Z
Z
Z
LOGIC DIAGRAMS
0C1
0C2
0C3
(1)
'845
(1)
OC1
(2)
0C2
5C3
PRE (14)
(23)
'846
(2)
(23)
L (13)
10
2'()
3D
40
50
60
70
(3)
(41
(51
(61
(71
(8)
(9)
1221
/21 1
20
20
(21) 20
30
30
(20) 30
(19) 40
40'
(191
50'
(181
(201
(18)
50
(17) 60
(16) 70
(15) 80
c8SAMSUNG
Electronics
(22) 10
10
40
50
(H) 60
70'
(16) 70
(15) 80
788
KS54HCTLS
KS74HCTLS
8451846
8-Bit Bus Interface D-Type
Latches with 3-State Outputs
Absolute Maximum Ratings·
t Power Dissipation temperature derating:
Supply Voltage Range Vee, . . . . . . . -0.5V to + 7V
DC Input Diode Current, hK
(VI < -0.5V or VI > Vee +0.5V) ..... ±20 mA
DC Output Diode Current, 101<
(Vo < -0.5V or Vo > Vee +0.5V) ... , ±20 mA
Continuous Output Current Per Pin, 10
(-0.5V < Vo < Vee +0.5V) ......... ±35 mA
Continuous Current Through
Vee or GND pins .............. " ± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage, Vce .............. 4.5V to 5.5V
DC Input & Output Voltages * , VIN, VOUT .. ' OV to Vee
Operating Temperature
Range
KS74HCLTS: -40°C to +B5°C
KS54HCLTS: -55°C to +125°C
Input Rise & Fall Times, tr , tf ......... Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vee or GND)
which permanent damage to the device may occur.
These are stress ratings only and functional operation
of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
(Vee=5V± 10% Unless Otherwise Specified)
Ta=25°C
Symbol Test Conditions
Typ
KS74HCTLS
KS54HCTLS
Ta = -40°C to +85°C Ta= -55°C to +125°C Unit
Guaranteed limits
Minimum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
O.B
O.B
O.B
V
Minimum High-Level
Output Voltage
VOH
VIN = VIH or VIL
10=- 2OIolA
10=-4mA
Vee -0.1
3.B4
Vee -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
10=201olA
10=4mA
10=BmA
0.1
0.26
0.39
0.1
0.33
0.5
0.1
0.4
V
Maximum Input
Current
hN
VIN=Vee or GND
±0.1
±1.0
±1.0
lolA
B.O
BO.O
160.0
lolA
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
.6.lee
VIN=Vce or GND
10uT=01olA
per input pin
VI=2.4V
other Inputs:
at Vee or GND
10uT=01olA
c8SAMSUNG
Electronics
Vee Vee -0.1
3.98
4.2
0
789
I
1°46
841:
~/a
8-Bit Bus Interface D-Type
Latches with 3-State Outputs
KS54HCTLS
KS74HCTLS·
AC ELECTRICAL CHARACTERISTICS
I
Characteristic
Symbol
(Input t r • tj"';6 ns). HCTLS845
Ta=25°C
Vcc=5.0V
Conditions!
KS74HCTlS
Ta= -40°C to +85°C
Vcc=5.0V±10%
Typ
Propagation D!3lay
I E to Q
~
Delay
~pa~ation
KS54HCTLS
Ta= -55°C to +125°C
Vcc=5.0V± 10%
Guaranteed Limits
23
30
38
46
tpHL
23
30
38
46
~
18
24
30
36
tPHL
18
24
30
36
Propagation Delay
CLR to Q
~
27
36
45
54
tpHL
27
36
45
54
Propagation Delay
~
27
36
45
54
tpHL
27
36
45
54
~
23
30
38
46
tPZL
23
30
38
46
o to
Q
l PRE to Q
Output Enable Time
to Q
OC
...
----~---
~
Unit
ns
ns
ns
ns
ns
- .,----
16
21
26
31
tpLZ
16
21
26
31
up Time
On before E
tsu
12
16
20
24
ns
Hold Time
On after E
0
0
0
ns
Output Disable Time
I OC to Q
[-----------_.
I Set
th
0
Input Capacitance
CIN
5
Power Dissipation Capacitance *
Gpo
ns
pF
pF
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vce' fin.
t For AC switching test circuits and timing waveforms see section 2.
AC ELECTRICAL CHARACTERISTICS
I
Characteristic
Symbol
Conditions t
(Input t r • tl.,,;6 ns). HCTLS846
Ta=25°C
Vcc=5.0V
KS74HCTLS
Ta= -40°C to +85°C
Vcc=5.0V±10%
Typ
KS54HCTLS
Ta= -55°C to +12SoC
Vcc=5.0V± 10%
Guaranteed Limits
~
25
34
42
65
tpHL
25
34
42
65
Propagation Delay
to Q
~
20
27
34
40
tPHL
20
27
34
40
Propagation Delay
CLR to Q
~
26
35
44
53
tpHL
26
35
44
53
Propagation Delay
~RE to 0
~
26
35
44
52
tpHL
26
35
44
52
Output Enable Time
I OC toO
~
19
26
32
19
26
32
38
Output Disable Time
OC to 0
~
Propagation Delay
E to Q
i5
tPZL
Unit
.t-.
38
ns
ns
ns
ns
ns
14
19
24
30
tpLZ
14
19
24
30
. Set up Time
On before E
tsu
12
16
20
24
ns
Hold Time
On after E
th
0
0
0
0
ns
Input Capacitance
CIN
5
Power Dissipation Capacitance *
Cpo
r
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vce' fin.
t For AC switching test circuits and timing waveforms see section 2.
=8SAMSUNG
1::1 __ ..... __ : __
ns
pF
pF
KS54HCTLS
KS74HCTLS
404914050
Ii
Hex Logic Level
Down Converters
FEATURES
DESCRIPTION
• Modified input structure allows voltages up to 15V
• Function, pin-out, speed and drive compatibility with
54/74LS logic family
• Low power consumption characteristic of CMOS
• High drive current outputs:
IOL=8mA @ VOL=0.5V
• Inputs aod outputs interface directly with TTL, NMOS
and CMOS devices
• Wide operating voltage range: 4.5V to 5.5V
• Characterized for operation over industrial and
military temperature ranges:
KS74HCTLS: -40°C to +85°C
KS54HCTLS: - 55°C to + 125°C
• Package options include "small outline" packages
(Available Tape & Reel), standard DIPs.
The '4049 and '4050 have a modified input protection
structure that enable them to be used as logic level
translators which will convert high level logic to a low level
logiC while operating from the low logic supply. For example, 0-15V logic can be corverted to 0-5V logiC when using a 5V Sllpply. The modified input protection has no diode
connected to Vee, thus allowing the input voltage to exceed the supply. The lower zener diode protects the input from both positive and negative static voltages. In
addition the '4049 and '4050 can be used as simple buffers or inverters without level translation.
PIN CONFIGURATION
LOGIC DIAGRAMS
I
'4049
Vee
NC
1Y
6Y
1,A
6A
2Y
NC
2A
5Y
3Y
3A
5A
4Y
4.A
~
1A~
1Y
~
. - ~
2Y
2A
(7)~_
3A-yv--3Y
~~
4A-yv--4Y
(1D~_
5A-~5Y
.. (1~
6A-yv--6Y
FUNCTION TABLE
'4050
1A~1Y
OUTPUT Y
.INPUT
A
'4049
'4050
H
L
H
L
H
L
2A~2Y
3A~3Y
4A~4Y
-.i!2L~(13l
5A--v-5Y
6A~6Y
c8SAMSUNG
Electronics
791
KS54HCTLS
KS74HCTLS
·...
404914050
I
Hex Logic Level
Down Converters
j
Absolute Maximum Ratings·
o
Supply Voltage Range Vee, ....... -0.5V to +7V
DC Input Diode Current, .ilK
.
(VI < -005V or VI >, +1505V)
..... ±20 mA
DC Output Diode Current, lo~-'
~
(Vo < -005V or Vo > Vee +005V)
±20 mA
Continuous Output Current Per Pin, 10
(-005V < Vo < Vee +005V) .. 0 ...... ±35 mA
Continuous Current Through ..
." Vee or GND pins . . . . . . . . . . . . . . .. ± 125 mA
Storage Temperature Range, Tstg ... -65°C to +150°C
Power Dissipation Per Package, Pdt ...... 500 mW':' .
t Power Dissipation temperature derating:
Plastic Package (N): -12mW/oC from 65°C to 85°C
Recommended Operating Conditions
Supply Voltage. Vcc . . . . . . . .
4.5V to 5.5V
DC Input & Output Voltages * • VIN, Vour .. OV to Vcc
Operating Temperature
Range
KS74HCTLS: -40°C to +85°C
KS54HCTLS: -55°C to +125°C
Input Rise & Fall Times. tr • tf ........ Max 500 ns
* Absolute Maximum Ratings are those values beyond
Unused inputs must always be tied to an appropriate logic
voltage level (either Vec or GND)
which permanent damage to the device may occur.
,These are stress ratings only and functional operation
. of the device at or beyond them is not implied. Long exposure to these conditions may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Test Conditions
(Vec=5V± 10% Unless Otherwise Specified)
Ta =.25°C
KS74HCTLS
KS54HCTLS
Ta= -40°C'to +85°C Ta= -55°C to +125°C Unit
Guaranteed Limits
Typ
MinifTIum High-Level
Input Voltage
VIH
2.0
2.0
2.0
V
Maximum Low-Level
Input Voltage
VIL
0.8
0.8
0.8
V
Minimum High-Level
Output Voltage
VOH
VIN=VIH or VIL
lo=-20",A
10= -4mA
Vee -0.1
3.84
Vce -0.1
3.7
V
Maximum Low-Level
Output Voltage
VOL
VIN=VIH or VIL
lo=20J.lA
10=4mA
lo=8mA
0.1
0.33
0.5
0.1
0.4
Maximum Input
Current
liN
VIN=Vee or GND
VIN=15V
0.1
0.26
0.39
±0.1
±1.0
±10.0
±1.0
±10.0
J.lA
2.0
20.0
40.0
J.lA
2.7
2.9
3.0
mA
Maximum Quiescent
Supply Current
Additional Worst
Case Supply
Current
Icc
t.lce
Vce Vce -0.1
402
3098
0
VIN=Vec or GND
louT=O",A
per input pin
VI=2.4V
other Inputs:
at Vee or GND
lour=OJ.lA
I
I
AC ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Conditions t
(Input t r ,
Ta=25°C
Vcc=5.0V
tf~6 ns). HCTLS4049. HCTLS4050
KS74AHCTLS
Ta =-40°Cto +85°C
Vee = 5.0V:!: 10%
Typ
Maximum Propagation Delay
tPLH
t----
CL=50pF
tpHL
Maximum Input Capacitance
CIN
Power Dissipation Capacitance *
Cpo
V
KS54HCTLS
Ta= -55°<6 to +125°C
Vee=5.0V:!: 10%
Unit
Guaranteed Limits
13
17
21
26
13
17
21
26
5
pP'
(per gate)
* Cpo determines the no-load dynamic power dissipation: Po=Cpo Vee 2
ns
pF
fin.
t For AC switching test circuits and timing waveforms see section 2.
=8~~SUNG
792
PACKAGE DIMENSIONS
1. PLASTIC PACKAGES
14·Pin DIP
Units: mm
Units: mm
16·Pin DIP
E"":J~: l1L1_
~
""
o
~0-100
L
.~
::
.!.J2~
~
1.77
~
0.30
WWWWI'~
U.
~'~
4.06
4.06
2.92
3.43
~92
~ h- --H-~~:
3.43
2.54 I
I
~
~~
0.36
~.~~
0.51
1.02
0.56
20·Pin DIP
Units: mm
24·Pin DIP
Units: mm
t:::::::::~
:b[: lJ4t
~'-'"
-J~15
~
1.77
wvwwvw
0.30
2.54 I
I
~
~~
0.36
0.56
=8SAMSUNG
Electronics
~~4.19
5.07
-L
4.06
I ".3
2.92
3.43
0.51
1.02
3.17
2.54
TYP
~~
3.93
0.36
0.51
1.02
795
I
PACKAGE DIMENSIONS
14-Pin SOP
mm
16-Pin SOP
Unit: mm
Unit: mm
24-Pin SOP
Unit:
Unit:
I~:::::JI~~
~
II
0.49
~
8.75
20-Pin SOP
mm
~"
2.65
--l I ~;:
c8SAMSUNG
Electronics
:
796
PACKAGE DIMENSIONS
2. CERAMIC PACKAGES
14-Pin Ceramic DIP
DIM
Mlllmetora
Min
Ma.
"
8
0.38
508
0.58
8.
C
1:40
1.78
o
E
E.
DIM
"
B
B.
C
0.20
0.38
18.16 18.56
6.10' 749
0
E
MIII",-'".
M..
Min
-
508
058
1.78
0.38
1.40
0.20
19.05
610
038
19.94
7.49
E.
F
7.62 1003
2.54'
L
3.181 4.19
L
0.51
1 91
0
318
0.51
419
o
S
0.51
114
S
I
1.02
2.29
Units: mm
I
24-Pin Ceramic DI·P
1.02
Units: mm
DIM
Mllimetora
Min
Max
DIM
MI"metora
Min
....
"
4.06
0.38
5.08
0.53
1.14
1.52
"
B
B.
4.06
0:38
1.14
8
B.
C
o
c8SAMSUNG
Electronics
Units: mm
7.62 10.03
2.54
F
20-Pin Ceramic DIP
16-Pin Ceramic DIP
Units: mm
508
053
1.52
0.20
0.38
25.78 25.83
C
eo
E
7.24
7.75
7.77
7.98
2.54
E.
7.77
7.98
F
2.54
3.731 401
0.38
0.89
L
o
3.731 4.01
0.508 1 1 771
1 114
S
1851 193
E
E.
F
6.10
L
o
S
0.51
8
o
0.20 038
31.50 32.64
797
I
ORDERING INFORMATION
The ensure prompt and accurate processing of your order, please use the product code system as described in the following example.
KS
T
-'
SAMSUNG IDENTIFICATION P R E F I X - - - - -
74
AHCT
xxx
N
J
OPERATING TEMPERATURE RANGE DESIGNATiON-----------J
COMMERCIAL: 74 (-40 to +85°C)
MILITARY: 54 (-55 to +125°C)
PRODUCT FAMILY DESIGNATION - - - - - - - - - - - - - - '
GENERIC PART N U M B E R - - - - - - - - - - - - - - - - - . J
PACKAGE DESIGNATOR - - - - - - - - - - - - - - - - - N: DIP
D:SOP
.
DT: SOP(Tape & Reel)
Pin
Quantity/Reel
SO-14
3000
~--'-
SO-16
3000
SO-20
1000
SO-24
1000
c8SAMSUNG
Electronics
798
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SAMSUNG SEMICONDUCTOR SALES OFFICES-U.S.A.
CALIFORNIA
22837 Ventura Blvd.
Suite 305
Woodland Hills, CA
91367
(818) 346-6416
FAX: (818) 346-6621
2700 Augustine Drive
Suite 198
Santa Clara, CA 95054
(408) 727-7433
FAX: (408) 727-5071
ILLINOIS
MASSACHUSETTS
TEXAS
901 Warrenville Road
Suite 120
Lisle, IL 60532-1359
(312) 852-2011
FAX: (312) 852-3096
20 Burlington Mall Road
Suite 205
Burlington, MA 01803
(617) 273-4888
FAX: (617) 273-9363
15851 Dallas Parkway
Suite 745
Dallas, TX 75248-3307
(214) 239-0754
FAX: (214) 392-4624
SAMSUNG SEMICONDUCTOR REPRESENTATIVES
U.S.A. and CANADA
CONNECTICUT
ARIZONA
HAAS & ASSOC. INC.
77 441 East Butherus Drive
Suite 300
Scottsdale, AZ 85260
TEL: (602) 998-7195
FAX: (602) 998-7869
PHOENIX SALES
257 Main Street
Torrington, CT 06790
TEL: (203) 496-7709
FAX: (203) 496-0912
FLORIDA
CALIFORNIA
QUEST REP INC.
9444 Farnham St.
Suite 107
San Diego, CA 92123
TEL: (619) 565-8797
FAX: (619) 565-8990
MEC
700 W. Hillsboro Blvd.
Bldg. 4, Suite 204
Deerfield Beach, FL 33441
SYNPAC_
3945 Freedom Circle
Suite 650
Santa Clara, CA 95054
TEL: (408) 988-6988
FAX: (408) 988-5041
MEC
511 Carriage Road
Indian Harbour Beach,
FL 32937
WESTAR REP COMPANY
2472 Chambers Road
Suite 100
Tustin, CA 92680
TEL: (714) 832-3325
FAX: (714) 832-7894
MEC
830 North Atlantic Blvd.
Suite B401
Cocoa Beach, FL 32931
WESTAR REP COMPANY
25202 Crenshaw Blvd.
Suite 217
Torrance, CA 90505
TEL: (213) 539-2156
FAX: (213) 539-2564
TEL: (407) 332-7158
(407) 773-1100
FAX: (407) 830-5436
TEL: (407) 799-0820
FAX: (407) 799-0923
TEL: (813) 522-3433
FAX: (813) 522-3993
ILLINOIS
IRI
8430 Gross Point Road
Skokie, I L 60076
CANADA
TERRIER ELEC_
145 The West Mall
Etobicoke, Ontario, Canada
M9C 1C2
TEL: (416) 622-7558
FAX: (416) 626-1035
TERRIER ELEC_
3700 Gilmore Way, 106A
Burnaby, B.C. Canada
V5G 4M1
TEL: (604) 433-0159
FAX: (604) 430-0144
TERRIER ELEC.
6600 Transcanadienne
TEL: (514) 695-4421
Suite 750-17
FAX: (514) 695-3295
Pointe Claire, Quebec, Canada
H9R 452
COLORADO
CANDAL INC.
7500 West MiSSissippi Ave.
Suite A-2
Lakewood, CO 80226
MEC
1001 45th, N.E.
St. Petersburg, FL 33703
TEL: (305) 426-8944
FAX: (305) 426-8799
TEL: (312) 967-8430
FAX: (312) 967-5903
INDIANA
STS & ASSOC_ INC_
3003 E. 96th st.
Suite 102
Indianapolis, IN 46240
TEL: (317) 844-9227
FAX: (317) 844-1904
MARYLAND
ADVANCED TECH SALES
809 Hammonds Ferry Rd.
Suite D
Linthicum, MD 21090
TEL: (301) 789-9360
FAX: (301) 789-9364
MASSACHUSETTS
TEL: (303) 935-7128
FAX: (303) 935-7310
NEW TECH SOLUTIONS, INC.
111 South Bedford Street
Suite 102
Burlington, MA 01803
TEL: (617) 229-8888
FAX: (617) 229-1614
...
C:CSAMSUNG
. . Electronics
801
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S"W'
SAMSUNG SEMICONDUCTOR REPRESENTATIVES
OREGON
MICHIGAN
JENSEN C.B.
2145 Crooks Rd.
TroY,MI48084
TEL: (313) 643-0506
FAX: (313) 643·4735
MINNESOTA
IRI
1120 East 80th Street
Bloomington, MN 55420
EARL & BROWN CO.
9735 SW. Sunshine Ct.
Suite 500
Beaverton, OR 97005
TEL: (503) 643·5500
FAX: (503) 644·9230
PENNSYLVANIA
TEL: (612) 854·1120
FAX: (612) 85~·8312
RIVCO JANUARY INC.
RJI Building
78 South Trooper Road
Norristown, PA 19403
TEL: (215) 631·1414
FAX: (215) 631·1640
NEW JERSEY
PUERTO RICO
NECCO
2460 Lemoine Avenue
Ft. Lee, NJ07024
TEL: (201) 461·2789
FAX: (201) 461·3857
DIGIT·TECH
P.O. Box 1945
Calle Cruz #2
Bajos, San German 00753
TEL: (809) 892·4260
FAX: (809) 892:3366
NEW ,MEXICO
S.W. SALES, INC.
7137 Settlement Way, N.W.
Albuquerque, NM 87120
TEXAS
TEL: (505) 899·9005
NEW YORK
T-5aUARE
6443 Ridings Road
Syracuse, NY 13206
TEL: (315) 463·8592
FAX: (315) 463·0355
T·SaUARE
7353 Victor·Pittsford Road
Victor, NY 14564
TEL: (716) 924·9101
FAX: (716) 924·4946
NORTH CAROLINA
GODWIN & ASSOC,
1100 Logger Ct.
Suite B102
Raleigh, NC 27609
GODWIN & ASSOCIATES
2812 Oak Leigh Drive
Charlotte, NC 28213
S.W. SALES INC.
2267 Trawood, Bldg. E3
EI Paso, TX 79935
TEL: (915) 594·8259
FAX: (915) 592·0288
VIELOCK ASSOC.
720 E. Park Blvd.
Suite 102
Plano, TX 75074
TEL: (214) 881·1940
FAX: (214) 423·8556
VIELOCK ASSOC.
9600 Great Hills Trail
Suite 150·W
Austin, TX 78759
TEL: (512) 345·8498
FAX: (512) 346·4037
UTAH
TEL: (919) 878·8000
FAX: (919) 878·3923
ANDERSON & ASSOC.
270 South Main, #108
Bountiful, UT 84010
TEL: (801) 292~8991
FAX: (801) 298·1503
VIRGINIA
TEL: (704) 549·8500
FAX: (704) 549·9792
ADVANCED TECHNOLOGY SALES, INC.
406 Grinell Drive
TEL: (804) 320·8756
Richmond, VA 23236
FAX: (804) 320·8761
OHIO
WASHINGTON
BAILEY, J.N. & ASSOC.
129 W. Main Street
New Lebanon,OH 45345
TEL: (513) 687·1325
FAX: (513) 687·2930
BAILEY, J.N. & ASSOC.
2679 Indianola Avenue
Columbus, OH 43202
TEL: (614) 262·7274
FAX: (614) 262-0384
BAILEY, J.N. & ASSOC.
1667 Devonshire Drive
Brunswick, OH 44212
TEL: (216) 273·3798
FAX: (216) 225·1461
c8SAMSUNG
EleCtronics
EARL & BROWN CO.
2447 A 152nd Ave. N.E.
Redmond, WA 98052
TEL: (206) 885·5064
FAX: (206) 885·2262
WISCONSIN
IRI
631 Mayfair
Milwaukee, WI 53226
TEL: (414) 259·0965
FAX: (414) 259-0326
802
SAMSUNG SEMICONDUCTOR SALES OFFICES-EUROPE
SAMSUNG
SEMICONDUCTOR
EUROPE GmbH
Mergenthaler Allee 38·40
06236 Eschborn
(West Germany)
Tel: 06196/9009'()
Fax: 0196/9009·89
PARIS
MILANO
MONCHEN
Centre d'Affaires La
Boursidiere RN 186, Bat.
Bourgogne, BP 202
F·92357 Le Plessis·Robinson
(France)
Tel: 0033·1·40 94 07 00
Fax: 0033·1·40 94 02 16
Viale G. Matteottl, 26
1·20095 Cusano Mllanino
(Italy)
Tel: 0039·2·6 13 28 88
Fax: 0039·2·6192279
Carl·Zeiss·Ring 9
0-8045 Ismaning
(West Germany)
Tel: (49) 0·89 96 48,38
Fax: (49) 0·89 96 48 73
SAMSUNG SEMICONDUCTOR REPRESENTATIVES
EUROPE
AUSTRIA
GERMANY (WEST)
SATRON HANDELSGES. MBH
Hoffmeistergasse 8-10/1/5 TEL: 0043·222·87 30 20
A·1120 Wien
FAX: 0043·222·85 95 93
TLX: 047·753 11 85 1
TERMOTROa.. GmbH
Pilotystr 4,
0·8000 MOnchen 22
BELGIUM
CIS ELECTRONICS NV
Heembeekstraat 111
B·1120 Brussels
SILCOM ELECTRONICS VERTRIEBS GmbH
Neusser Str. 336·338
TEL: (49)'()·2161-607 52
0·4050 M6nchengladbach FAX: (49).()·2161-6516·38
TLX: 85 2189
TEL: 0032·2·2442974
FAX: 0032·2·2 42 89 30
TLX: 046·2 58 20
TEL: (49)·0·89·2303 52 52
FAX: (49).()·89·2303 52 80
TLX: 178984 53
ING. THEO HENSKES GmbH
Laatiener Str. 19
TEL: (49).()·511·86 50 75
Postfach 72 12 26
FAX: (49)'()·724979 93
0·3000 Hannover 72
TLX: 92 35 09
DENMARK
EXATEC ALS
Oortheavj 1·3
OK·24oo Kopenhagen
TEL: 00453·1·19 1022
FAX: 00453·1 1931 20
TLX: 27253
TEL: (49)-0·89-61 30 303
FAX: (49)-0-89-61 31 668
TLX: 5 21 61 87
MSC VERKAUFSBORO MITTE
Wormser Str. 34
TEL: (49)-0·62·332 66 43
Postfach 37
FAX: (49)·0·332 02 98
0-6710 Frankenthal
TLX: 46 52 30
FINLAND
INSTRU COMPONENTS
P.O. Box 64, Vitikka 1
SF'()2631·ESPOO
Helsinki
ASTRONIC GmbH
Grunwalder Weg 30
0·8024 Oeisenhofen
TEL: 00358-0·5 28 43 25
FAX: 00358'()·5 28 43 33
TLX: 057·12 44 26
MICRONETICS GmbH
Wail Our SUidter Str. 45
0·7253 Renniilgen
TEL: (49)·0·7159·60 19
FAX: (49).()·715 951 19
TLX; 72 47 08
ITALY
FRANCE
ASIA MOS (OMNITECH ELCCTRONIQUE)
Batiment Evolic 1 165,
TEL: 0033·1·47 60 1247
Boulevard Oe Valmy
FAX: 0033·1·47 60 1582
F·92705Colombes
TLX: 042-61 38 90
DIS. EL. SPA
Via Orbetello 98
1·10148 Torino
SONEL·ROHE (SCAIB)
6, Rue Le Corbusier
Silic 424
F·94583 Rungis, Cedex
MOXEL S.R.L.
Via C. Frova, 34
TEL: 0039·2·61 29 05 21
1·20092 Cinisello Balsamo FAX: 0039-2-6172582
TLX: 043·35 20 45
TEL: 0033·1·46 86 81 70
FAX: 0033·1·45 60 55 49
TLX: 042·20 69 52
c8SAMSUNG
Electronics
TEL: 0039·1·12 20 15 22
FAX: 0039-1·12 16 59 15
TLX: 043·21 51 18
803
I
SAMSUNG SEMICONDUCTOR REPRESENTATIVES
THE NETHERLANDS
UNITED KINGDOM
MALCHUS BV HANDEIMIJ.
Fokkerstraat 511·513
TEL: 0031·10·4 27 77 77
Postbus 48
FAX: 0031·10-4 154867
NL·3125 BD Schiedam
TLX: 044·2 1598
NORWAY
EXATEC ALS
Solheimveien 50
Postbox 314
N·1473 Skarer
TEL: 0047·2·97 29 50
FAX: 0047·2·97 29 53
KORD DISTRIBUTION LTD.
P.O. Box 294, Camberley, TEL: 0276 685741
Surry GU 153JJ
FAX: 0276 691334
TLX: 859919 KORDIS G
BYTECH LTD.
3 The Western Centre,
Western Road,
Bracknell Berkshire
RG121RW
TEL: Sales 0344 482211
Account/Admin
0344424222
FAX: 0344 420400
TLX: 848215
SPAIN
SEMICONDUCTORES S.A.
Ronda General Mitre
TEL: 0034·3·2 172340
240 Bjs .
FAX: 0034·3·2 176598
E·OB006 Barcelona
TLX: 052·9 77 87
SWEDEN
MIKO KOMPONENT AB
Segers by Vagen 3
P.O. Box 2001
S·14502 Norsborg
TEL: 0046·753·89080
FAX: 0046·753·75 34 0
TLX: 052·9 77 87
lIT MULTI COMPONENTS
346 Edinburgh Avenue
TEL: 0753 824212
Slough SL1 4TU
FAX: 0753824160
TLX: 849804
NELTRONIC LIMITED
John F. Kennedy Road,
Naas Road, Qublin 12,
Ireland
TEL: (01) 503560
FAX: (01) 552789
TLX: 93556 NELT EI
SWITZERLAND
PANATEL AG
Grundstr. 20
CH-6343 Rotkreuz
TEL: 0041·42 64 30 30
FAX: 0041·42 64 30 35
TLX: 045·86 87 63
c8 SAIUISUNG
Electronics
.
804
SAMSUNG SEMICONDUCTOR REPRESENTATIVES
ASIA
SANT SONG CORP.
Room A, 8F No. 180, Sec-4,
Chung Hsiao E. Rd., Taipei,
Taiwan, R.O.C.
HONG KONG
AV, CONCEPT LTD.
ROOM 804, Tower A, 8/F1.,
TEL: 3629325
Hunghom Commercial Centre, FAX: 7643108
37·39 MA Tau Wai Road,
TLX: 52362 ADVCC HX
Hunghom, Kowloon,
Hong Kong .
PROTECH COMPONENTS LTD.
Flat 3, 10/FI., Wing Shing Ind. TEL: 3522181
Bldg., 26 NG Fong Street,
FAX: 3523759
San Po Kong, Kowloon,
TLX: 38396 PTLD HX
Hong Kong
WISEWORLD TECHNOLOGY CO.
Room 708, Tower A, 7/FI.,
TEL: 7658923
Hunghom Commercial Centre, FAX: 3636203
37-39 MA Tau Wai Road,
Kowloon, Hong Kong
RIGHT SYSTEM CO., LTD.
Room A19, 6/FI.,
Proficient Ind. Centre,
Block A, 6 Wang Kwun Road,
Kowloon Bay, Kowloon,
Hong Kong
TEL: 7566331
FAX: 7998985
TLX: 52896 OSPCl HX
SOLARBRITE ENTERPRISE CO.
(CALCULATOR & WATCH)
Room 903, The Kwangtung
TEL: 7701010
Provincial Bank Bldg.,
FAX: 7700559
589-591 Nathan Road,
TLX: 52543 SECl HX
Kowloon, Hong Kong
SOLARI COMPUTER ENGINEERING LTD.
(4 BIT/8 BIT ONE CHIP SOFTWARE HOUSE)
Unit 703-4, 7/FI., Jordan House, TEL: 7213318
6-8 Jordan Road, Kowloon,
FAX: 7235288
Hong Kong
CENTRAL SYSTEMS DESIGN LTD.
(ASIC DESIGN HOUSE) .
Room 1704, Westlands Centre, TEL: 5620248
20 Westlands Road,
FAX: 5658046
Quarry Bay, Hong Kong
TLX: 73990 CSD HX
DATAWORLD INTERNATIONAL LTD.
(MIYUKI ELECTRONICS (HK) LTD.)
(ASIC DESIGN HOUSE)
Flat No. 3-4, 5tFl.,
TEL: 7862611
Yuen Shing Ind. Bldg.,
FAX: 7856213
1033, Yee Kuk Street, West,
TLX: 45876 MYK HX
Kowloon, Hong Kong
TAIWAN
YOSUN INDUSTRIAL CORP.
Min-Sheng Commercial Bldg.,
10F No. 481 Min-Sheng East
Rd., Taipei, Taiwan, R.O.C.
KINREX CORP.
2nd. Fl., 514-3, Tun Hwa S.
Rd., Taipei, Taiwan, R.O.C.
TEL: (02) 501-0700-9
FAX: (02) 503-1278
TLX: 26777 YOSUNIND
TEL: 02-700-4686-9
FAX: 02-704-2482
TLX: 20402 KIN REX
cRSAMSUNG
. . Electronics
TEL: (02) 775-2506
FAX: (02) 771-8413
JAPAN
ADO ELECTRONIC INDUSTRIAL CO., LTD.
7th Fl., Sasage Bldg., 4-6
TEL: 03-257·1618
Sotokanda 2-Chome Chiyoda- FAX: 03-257-1579
ku, Tokyo 101, Japan
INTERCOM PO INC.
Ihi Bldg., 1-6-7, Shibuya,
Shibuya-ku, Tokyo 150 Japan
TEL: 03-406-5612
FAX: 04-409·4834
CHEMI-CON INTERNATIONAL CORP.
Mitauya Toranomon Bldg.,
TEL: 03·508-2841
22·14, Toranomon 1·Chome,
FAX: 03·504-0566
Minato-ku, Tokyo 105, Japan
TOMEN ELECTRONICS CORP.
1-1, Uschisaiwai-cho 2-Chome TEL: 03-506·3473
Chiyoda·ku, Tokyo, 100
FAX: 03·506·3497
DIA SEMICON SYSTEMS INC.
Wacore 64 1-37-8, Sangenjaya, TEL: 03-487-0386
Setagaya·ku, Tokyo 154 Japan FAX: 03-487·8088
RIKEI CORP.
Nichimen Bldg., 2-2-2,
Nakanoshima, Kita-ku,
Osaka 530 Japan
TEL: 06-201-2081
FAX: 06-222-1185
SINGAPORE
GEMINI ELECTRONICS PTE LTD.
315, Outram Road, #12-08,
TEL: 65-2263066
Tan Boon Uat Building,
FAX: 65-2262781
Singapore 0315
TLX: RS-42819
INDIA
COMPONENTS AND SYSTEMS MARKETING
ASSOCIATES (INDIA) PVT. LTD.
100, Dadasaheb Phalke Road,
Dadar, Bombay 400
014
TEL: 4114585
FAX: 4112546
TLX: 001-4605 PDT IN
TURKEY
ELEKTRO SAN. VE TIC. KOlL.
Hasanpasa, Ahmet Rasim Sok
No. 16 Kadikoy Istanbul,
Turkey
STI.
TEL: 337·2245
FAX: 336-8814
TLX: 29569 elts tr
THAILAND
VUTIPONG TRADING LTD., PART.
51-53 Pahurat Rd. (Banmoh)
TEL: 221-9699-3641
Bangkok 10200 THAILAND
223-4608
FAX: 224-0861
TlX: 87470 Vutipong TH
805
I
SAMSUNG SEMICONDUCTOR REPRESENTATIVES
KOREA
NAEWAE SEMICONDUCTOR
Room 503, 22·dong, Sunin
Bldg., 16-1, Hankangro-2ka,
Yongsan-ku, Seoul, Korea
Cable: ELECONAEWAE
SEOUL
c.p.a. BOX 1409
CO., LTD.
TEL: 717·4065-7
702-4407-9
FAX: 702-3924
TLX: NELCO K27419
SAMSUNG LlGHT·ELECTRONICS CO., LTD.
4th FI. Room 2-3,
TEL: 718-0045,
Electronics Main Bldg., 16-9,
718-9531-5
Hankangro-3ka, Yongsan·ku, FAX: 718·9536
SeouJ, Korea
N~W CAS.TLE SEMICONDUCTOR CO., LTD.
4th Fl.Room 10-11,
TEL: 718·8531-4
Electronics Main Bldg., 16-9, FAX: 718-8535
Hankangro-3ka, Yongsan-ku,
Seoul, Korea
HANKOOK SEMICONDUCTOR &
TELECOMMUNICATIONS CO., LTD.
402 Suite, Sowon Bldg.,
TEL: 338-2015-8
354-22, Seokyo-dong,
FAX: 338-2983
Mapo-ku, Seoul, Korea
c8SAMSUNG
Electronics
SEG YUNG INTERISE CORP.
21-301, Sunin Bldg., 16-1,
TEL: 701-6811-6,
Hankangro-2ka, Yongsan-ku,
701-6781-4
Seoul, Korea
FAX: 701-6785
SEGYUNG ELECTRONICS
182-2, Jangsa-dong,
Jongro-ku, Seoul, Korea
SAMTEK
Room 704, Euylim Bldg.,
16-96, Hankangro-3ka,
Yongsan-ku, Seoul, Korea
TEL: 273-6781-3
FAX: (02) 273-6597
TLX: K24950
SUKSEMT
TEL: 703-9656-8
FAX: 703-9659
SUNIN INDUSTRIES CO., LTD.
Sunin Bldg., 7Fl., 16-1,
TEL: 718-7113-6
702-1257-9
Hankangro-2ka, Yongsan-ku,
Seoul, Korea
FAX: 715-1031
806
SAMSUNG SEMICONDUCTOR DISTRIBUTORS
ALABAMA
HAMMOND
4411·B Evangel Circle, N.W.
Huntsville, AL 35816
(205) 830·4764
ARIZONA
ADDED VALUE
7741 East Gray Road
Suite #9
Scottsdale, Al 85260
(602) 951·9788
CYPRESS/RPS
2164 E. Broadway Road #310·8
Tempe, AZ 85282
(602) 966·2256
(805) 495·9998
JACO
2880 lanker Road
Suite 202
San Jose, CA 95134
(408) 432·9290
JACO
23·441 South Pointe Drive
Laguna Hills, CA 92653
(714) 837-8966
MICRO GENESIS
2880 lakeside Drive
Santa Clara, CA 95054
(408) 727·5050
CANADA
CALIFORNIA
ADDED VALUE
3320 East Mineral King
Unit D
Visalia, CA 93291
(209) 734·8861
ADDED VALUE
1582 Parkway Loop
Unit G
Tustin, CA 92680
(714) 259·8258
ADDED VALUE
6397 Nancy Ridge Road
San Diego, CA 92121
(619) 558-8890
ADDED VALUE
31194 La Baya Drive, #100
Westlake Village, CA 91362
(818) 889·2861
ALL AMERICAN
369 Van Ness Way #701
Torrance, CA 90501
(BOO) 669·8300
BELL MICRO PRODUCTS
18350 Mt. Langley
Fountain Valley, CA 92708
(714) 963·0667
ELECTRONIC WHOLESALERS
1935 Avenue De L'Eglise
Montreal, Quebec, Canada
H4E 1H2
(514) 769·8861
PETERSON, C.M.
220 Adelaide Street North
London, Ontario, Canada
N6B 3H4
(519) 434·3204
SAYNOR VARAH
99 Scarsdale Road
Don Mills, Ontario, Canada
M3B 2R4
(416) 445·2340
SA YNOR VARAH
1·13511 Crestwood Place
Richmond, B.C., Canada
V6V 2G5
(604) 273·2911
WESTBURNE IND. ENT., LTD.
300 Steep rock Drive
Downsview, Ontario, Canada
M3J 2W9
(416) 635·2950
COLORADO
BELL MICRO PRODUCTS
550 Sycamore Drive
Milpitas, CA 95035
(408) 434·1150
CYPRESS/RPS
6230 Descanso Avenue
Buena Park, CA 90620
(714) 521·5230
CY.,.PRESS/RPS
10054 Mesa Ridge Ct
Suite 118
San Diego, CA 92121
(619) 535·0011
CYPRESS/RPS
2175 Martin Avenue
Santa Clara, CA 95050
CYPRESS/RPS
21550 Oxnard, #420
Woodland Hills, CA 91367
c8SAMSUNG
Electronics
JACO
2260 Townsgate Road
Westlake Village, CA 91361
ADDED VALUE
4090 Youngfield
Wheat Ridge, CO 80033
(303) 422·1701
CYPRESS/RPS
12503 E. Euclid Drive
Englewood, CO 80111
(303) 792·5829
CONNECTICUT
ALMO ELECTRONICS
31 Village Lane
Wallingford, CT 06492
(203) 288·6556
(408) 980·8400
JACO
384 Pratt Street
Meriden, CT 06450
(203) 235·1422
(818) 710·7780
JV
690 Main Street
East Haven, CT 06512
(203) 469·2321
807
I
SAMSUNG SEMICONDUCTOR DISTRIBUTORS
FLORIDA
ALL AMERICAN
16251 N.W. 54th. Avenue
Miami, FL 33014
(305) 621-8282
HAMMOND
6600 N.w. 21st. Avenue
Fort Lauderdale, FL 33309
(407) 973-7103
HAMMOND
1230 W. Central Blvd
Orlando, FL 32802
(407) 849-6060
MICRO GENESIS
2170 W. State Road 434 #324
Longwood, FL 32779
(407) 869-9989
JACO
Rivers Center
10270 Old Columbia Road
Columbia, MD 21046
(301) 995-6620
MASSACHUSETS
ALMO ELECTRONICS
60 Shawmut Avenue
Canton, MA 02021
(617) 821-1450
GERBER
128 Carnegie Row
Norwood, MA 02062
(617) 329-2400
JACO
222 Andover Street
Wilmington, MA 01887
(617) 273-1860
GEORGIA
HAMMOND
5680 Oakbrook Parkway
#160
Norcross, GA 30093
(404) 449-1996
QUALITY COMPONENTS
6145 Northbelt Parkway
Suite B
Norcross, GA 30071
(404) 449-9508
MICHIGAN
CALDER
4245 Brockton Drive
Grand Rapids, MI 49508
(616) 698-7400.
CHELSEA INDUSTRIES
34443 Schoolcraft
Livonia, MI 48150
(313) 525-1155
MINNESOTA
ILLINOIS
(312) 860-7171
ALL AMERICAN
11409 Valley View Road
Eden Prairie, MN 55344
(612) 944-2151
GOOLD
101 Leland Court
Bensenville, IL 60106
(312) 884-6620
CYPRESS/RPS
7650 Executive Drive
Eden Prairie, MN 55344
(612) 934-2104
QPS
101 Commerce Dr. #A
Schaumburg, IL 60173
VOYAGER
5201 East River Road
Fridley, MN 55421
(612) 571-7766
INDIANA
ALTEX
12744 N. Meridian
Carmel, IN 46032
(31.7) 848-1323
CHELSEA INDUSTRIES
8465 Keystone CrOSSing, #115
Indianapolis, IN 46240
(317) 253-9065
MISSOURI
CHELSEA INDUSTRIES
2555 Metro Blvd.
Maryland Heights, MO 63043
(314) 997-7709
NEW JERSEY
MARYLAND
(301) 251-1205
ALMO ELECTRONICS
12 Connerty Court
East Brunswick, NJ 08816
(201) 613-0200
ALL AMERICAN
1136 Taft Street
Rockville, MD 20853
(301) 953-2566
GENERAL RADIO SUPPLY
600 Penn St. @ Bridge Plaza
Camden, NJ 08102
(609) 964-8560
ALMO ELECTRONICS
8309B Sherwick Court
Jessup, MD 20794
(301) 995-6744
JACO
Ottilio Office Complex
555 Preakness Avenue
Totowa, NJ 07512
(201) 942-4000
GENERAL RADIO SUPPLY
6935L Oakland Mills Road
Columbia, MD 21045
cRSAMSUNG
. . Electronics
808
SAMSUNG SEMICONDUCTOR DISTRIBUTORS
OKLAHOMA
NEW YORK
ALL AMERICAN
33 Commack Loop
Ronkonkoma, NY 11779
(516) 981-3935
CAM/RPC
2975 Brighton Henrietta TL Road
Rochester, NY 14623
(716) 427-9999
JACO
145 Oser Avenue
Hauppauge, NY 11788
(516) 273-5500
MICRO GENESIS
90-10 Colin Drive
Holbook, NY 11741
(516) 472-6000
QUALITY COMPONENTS
3158 S. 108th East Avenue
Suite 274
Tulsa, OK 74146
(918) 664-8812
OREGON
NORTH CAROLINA
QUALITY COMPONENTS
3029-105 Stonybrook Drive
Raleigh, NC 27604
(919) 467-4897
DIXIE
2220 South Tryon Street
Charlotte, NC 28234
(704) 377-5413
HAMMOND
2923 Pacific Avenue
Greensboro, NC 27420
(919) 275-6391
RESCO/RALEIGH
Hwy. 70 West & Resco Court
Raleigh, NC 27612
(919) 781-5700
CYPRESS/RPS
15075 S. Koll Parkway
Suite 0
Beaverton, OR 97006
(503) 641-2233
PENNSYLVANIA
ALMO ELECTRONICS
9815 Roosevelt Blvd.
Philadelphia, PA 19114
(215) 698-4003
CAM/RPC
620 Alpha Drive
Pittsburgh, PA 15238
(412) 782-3770
ALMO ELECTRONICS
220 Executive Drive
Mars, PA 16046
(412) 776-9090
SOUTH CAROLINA
OHIO
DIXIE
4909 Pelham Road
Greenville, SC 29606
(803) 297-1435
DIXIE
1900 Barnwell Street
Columbia, SC 29201
(803) 779-5332
HAMMOND
1035 Lowndes Hill Rd.
Greenville, SC 29607
(803) 233-4121
CAM/RPC
749 Miner Road
Cleveland; OH 44143
(216) 461-4700
CAM/RPC
15 Bishop Drive #104
Westerville, OH 43081
(614) 888-7777
CAM/RPC
7973-B Washington Woods Drive
Centerville, OH 45459
(513) 433-5551
ADDED VALUE
4470 Spring Valley Road
Dallas, TX 75244
(214) 404-1144
CHELSEA INDUSTRIES
10979 Reed Hartman, Highway
#133
Cincinnati, OH 45242
(513) 891-3905
ADDED VALUE
6448 Highway 290 East
#A103
Austin, TX 78723
(512) 454-8845
CHELS"EA INDUSTRIES
1360 Tomahawk
Maumee, OH 43537
(216) 893-0721
ALL AMERICAN
1819 Firman Drive, #127
Richardson, TX 75081
(214) 231-5300
SCHUSTER
11320 Grooms Road
Cincinnati, OH 45242
(513) 489-1400
CYPRESS/RPS
2156 W. Northwest Highway
Dallas, TX 75220
(214) 869-1435
SCHUSTER
20570 East Aurora Road
Twinsburg, OH 44087
(216) 425-8134
JACO
1209 Glenville Drive
Richardson, TX 75080
(214) 235-9575
....
OCSAMSUNG
Electronics
TEXAS
809
I
SAMSUNG SEMICONDUCTOR REPRESENTATIVES
THE NETHERLANDS
UNITED KINGDOM
MALCHUS BV HANDEIMIJ.
Fokkerstraat 511-513
TEL: 0031-10-4 27 77 77
Postbus 48
FAX: 0031-10-4 154867
NL-3125 BO SChiedam
TLX: 044-2 15 98
NORWAY
EXATEC ALS
Solheimveien 50
Postbox 314
N-1473 Skarer
TEL: 0047-2-97 29 50
FAX: 0047-2-97 29 53
STC ELECTRONIC DISTRIBUnON
Edinburgh Way Harlow TEL: (0279) 441144
FAX: (0279) 441787
Essex CM20 20F
BYTECH LTD.
3 The Western Centre,
Western Road,
Bracknell Berkshire
RG121RW
TEL: Sales 0344 482211
Account/Admin
0344424222
FAX: 0344 420400
TLX: 848215
SPAIN
SEMICONDUCTORES S.A.
Ronda General Mitre
TEL: 0034-3-2 172340
240 Bjs
FAX: 0034-3-2176598
E-D8006 Barcelona
TLX: 052-9 77 87
SWEDEN
MIKO KOMPONENT AB
Segers by Vagen 3
P.O. Box 20p1
S-14502 Norsborg
TEL: 0046-753-89080
FAX: 0046-753-75 34 0
TLX: 052-9 77 87
ITT MULTI COMPONENTS
346 Edinburgh Avenue
TEL: 0753 824212
Slough SL 1 4TU
FAX: 0753 824160
TLX: 849804
NELTRONIC LIMITED
John F. Kennedy Road,
Naas Road, Qublin 12,
Ireland
TEL: (01) 503560
FAX: (01) 552789
TLX: 93556 N ELT EI
SWITZERLAND
PANATEL AG
Grundstr. 20
CH-6343 Rotkreuz
TEL: 0041-42 64 30 30
FAX: 0041-42 64 30 35
TLX: 045-86 87 63
c8SAMSUNG
Electronics
810
NOTES
NOTES
NOTES
NOTES
••
c:cSAMSUNG
•• Electronics
Semiconductor Business
HEAD OFFICE:
8/10FL SAMSUNG MAIN BLDG.
250, 2-KA, TAEPYUNG-RO,
CHUNG-KU, SEOUL, KOREA
C.P.O. BOX 8233
TELEX: KORSST K27970
TEL: (SEOUL) 751-2114
FAX: 753-0957
BUCHEON PLANT:
82-3, DODANG-DONG,
BUCHEON, KYUNGKI-DO, KOREA
C.P.O. BOX 5779 SEOUL 100
TELEX: KORSEM K28390
TEL: (SEOUL) 741-0066, 664-0066
FAX: 741-4273
KIHEUNG PLANT:
SAN #24 NONGSUH-RI, KIHEUNG-MYUN
YONGIN-GUN, KYUNGKI-DO, KOREA
C.P.O. BOX 37 SUWON
TELEX: KORSST K23813
TEL: (SEOUL) 741-0620/7
FAX: 741-0628
GUMI BRANCH:
259, GONDAN-DONG, GUMI,
KYUNGSANGBUK-DO, KOREA
TELEX: SSTGUMI K54371
TEL: (GUMI) 2-2570
FAX: (GUMI) 52-7942
SAMSUNG SEMICONDUCTOR INC.:
3725 NORTH FIRST STREET
SANJOSE, CA 95134-1708, USA
TEL: (408) 954-7000
FAX: (408) 954-7873
HONG KONG BRANCH:
24FL TOWER 1 ADMIRALTY CENTER
18 HARCOURT ROAD HONG KONG
TEL: 8626900
TELEX: 80303 SSTC HX
FAX: 8661343
TAIWAN OFFICE:
RM B. 4FL NO 581
TUN-HWA S, RD, TAIPEI, TAIWAN
TEL: (2) 70tHl025/7
FAX: (2) 784-0847
SAMSUNG ELECTRONICS JAPAN CO., LTD.
9F. SUDACHO VERDE BLDG.
2-3, KANDA-SUDACHO
CHIYODA-KU, TOKYO 101, JAPAN
TELEX: 2225206 SECJPN J
TEL: (03) 258-9601
FAX: (03) 258-9696
SAMSUNG SEMICONDUCTOR EUHOPE GMBH:
MERGENTHALER ALLEE 38-40
0-6236 ESCHBORN, WIG
TEL: 0-6196-90090
FAX: 0-6196-900989
TELEX: 4072678 SSED
SAMSUNG (U.K.) LTD.:
SAMSUNG HOUSE 3 RIVERBANK WAY
GREAT WEST ROAD BRENTFORD
MIDDLESEX TW8 9RE
TEL: 862-9312 (EXT) 304
862-9323 (EXT) 292
FAX: 862-0096, 862-0097
TELEX: 25823
SINGAPORE OFFICE:
10 COllYER QUAY 114-07
OCEAN BUILDING S'PORE 0104
TEL: 535-2808
FAX: 532-6452
PRINTED IN KOREA
MARCH,1990
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