1990_Sharp_Microcomputers_Data_Book 1990 Sharp Microcomputers Data Book

User Manual: 1990_Sharp_Microcomputers_Data_Book

Open the PDF directly: View PDF .
Page Count: 470

Download
Open PDF In Browser	View PDF

SHARP

MICROCOMPUTERS
DATABOOK ·

MICROCOMPUTERS' DATA BOOK

General Information

11

4-bit Single-chip Microcomputers

12

8-bit Single-chip Microcomputers

Is

Development Support Tools

14

8-bit Microprocessors/Peripherals

15

1 6-bit Microprocessors

Is

· Preface

As we become more and more an information-oriented
society, microcomputers have come to playa major role in
numerous areas of computer application. As computerrelated services grow ever more sophisticated and diverse, we are faced with a growing demand for microcomputers using most advanced technology.
To keep pace with this rapid progress, we at SHARP
will continue to direct our efforts at understanding the
crucial trends of the moment in this area and supply our
customers with products that truly meet their needs in
short to contribute to a better life for all of us in this age
of expanding technology.
SHARP has developed a wide range of 4-bit, 8-bit and
16-bit microcomputer units which have numerous areas of
computer-related applications from home and consumer
appliances to office and industrial equipment.
This databook has been especially compiled for the use
of our customers. Listed here is the entire range of microcomputer products developed and manufactured by
SHARP, with detailed explanations of their many functions and outstanding features. We hope that you find this
book useful in determining which SHARP products are
best suited to your needs. Please contact us directly if you
have any further questions.

Notice
Specifications contained in this databook are current as
of the publication dated September, 1990.
SHARP reserves the right to make changes in the circuitry or specifications described herein at any time without notice in order to improve design or reliability. The
system configuration examples described herein are just
intended for LSI evaluation; the external circuit configuration, constants and other related conditions must be studied for application to an actual system. The information
in this databook has been carefully checked to be accurate, however, SHARP makes no warranty for any errors
which may appear in this document. Contact SHARP to
obtain the latest version of device specifications before
placing your order.
SHARP makes no representations that circuitry described herein is free from infringement of patent or other
rights of third parties which may result from its use. No
license is granted by implication under any patent rights
or other rights of SHARP CORPORATION.

This is a newly revised 1990/91 Microcomputers Databook which can be used in place of the former editions.

Contents

1. General Information ...................................................................... 1
Alphanumeric Index ...................................................... ~......... 2
Product Lineup ...................................................................... 3
Package Outline ..................................................................... 9
Quality Assurance ........ ; ........................................................ 16
2. 4-bit Single-chip Microcomputers .................................................... 25
3. 8-bit Single-chip Microcomputers .................................................. 187
4. Development Support Tools .................................... ~.................... 253
5. 8-bit Microprocessors/Peripherals ......... .. .. . . .. .. . . . . . . .. . . . .. . . . . .. .. . . . . . . . .. 267
6. 16-bit Microprocessors ..............,................................................. 369

Sharp's Ie Data Book Family

/ 4-bit Single-chip Microcomputers
/

8-bit Single-chip Microcomputers

--t-/ Development Support Tools
/

8-bit Microprocessors/Peripherals

/

16-bit Microprocessors

- /

Dynamic RAMs

- / Static RAMs

MEMORY

I

EPROMs/OTPROMs

- / Mask Programmable ROMs

-j

Dual Port RAMs

~! FIFO Memories
- / Gate arrays/Standard cells
- / Display drivers, Telecommunications

MOS

t--+-/ MODEMs, CCDs/CCD peripherals
- /

ICs for audio/visual equipment

- / Voice/Melody generators, ICs for clock, etc.

BIPOLAR

-

Operational amplifiers/Comparators

f--

Transistor arrays, Voltage regulators

t--+-/

AID, D/A converters,Bus interfaces

I -/

ICs for audio/visual equipment

'--

CCD peripherals, ICs for telephone, etc.

General Information

Alphanumeric Index

Alphanumeric Index
Model No.
SM4A
SM500
SM510
SM511
SM512
SM530
. SM531
SM550
SM551
SM552
SM563
SM578
SM579
SM590
SM591
SM595
SM5E4
SM5J5
SM5J6
SM5K1

Page
141
119
149
i59
159
100
110
36
36
36
172
49
49
26
26
26
65
83
83
128

Model No.
SM803
SM803A
SM805
SM805A
SM8202·
SM8203
SM8320
SME-30
LH0080
LH0080A
LH0080B
LH0080E
LH0081
LH0081A
LH0081B
LH0081E
LH0082
LH0082A
LH0082B
LH0082E

Page
207
207
207
207
226
226 .
243
259
284
284
284
284
309
309
309
309
319
319
319
319

Model No.
LHQ083
LH0083A
. LH0084
LH0084A
LH0084B
LH0085
LH0085A
LH0085B
LH0086·
LH0086A
LH0086B
LH0087
LH0087A
LH0087B
LH0801
LH0801A
LH0811
LH081lA
LH0881
LH0881A

Page
329
329
344
344
344
344
344
344
344
344
344
344
344
344
188
188
188
188
203
203

Model No.
LH5080
LH5080A .
LH5081
LH5081A
LH5081B
LH5082
LH5082A
LH5082B
LH70108
LH70116
LH8530
LH8530A
LU5E4POP
LU800V1
LU800AV1
LU805BV2
LU8200H7
LU820XH4
LUXXXH2

Page
268
268
274
274
274
279
279
279
370
414
354
354
75
220
220
220
263
263
254

-~'--""""'------SHARP~-----'~'-~--

2

.....

.-.-

..... ........... - . -..................... Product Lineup

.-

~.-.-.-

Product Lineup

•

4-bit Single-chip Microcomputers'

(1 ) Controller Series
ROM (bit)

RAM (bit)

O.5K
O.7K

32X4

IH
IH

SM590
SM595

15

Application
Compact system

15

Compact system

1/0

Model No.

II
II

32X4

56X4

SM591

Compact system

80X4

SM550

General-purpose

lK

I

2K

II

128X4
192X4

[!j

General-purpose

48

SM551

I
I

Built-in AID

SM578

4K
256X4

SM552

General-purpose

256x4

SM579

Built-in AID

SM5E4

Multi-I/O

6K
320X4

Built-in OTPROM

LU5E4POP
8K

BuilHn AID

52

SM5J6

256X4

(2) VFD Driver Series

VFD
segment
256X4

8K

Memory(bit)

Port

AID

Instruction
cycle

,ion

(PsI

Model No.

ROM

. RAM

SM590

50axg

32X4

SM595

762X8

32X4

SM591

1016X8

56X4

SM550

lO24X8

80X4

SM551

2048X9

128X..f.

SM552

4096X8 .

259X4

0

15

4064x9

192X4

SM579

6096X9

256X4

(MAX)

15

24

36

28

LU5E4POP
SM5J6

6144XS

320X4

6144XS*1

320X4

8192X9

256X4

Supply
voltage

Operating

·IV)

(oq

Ceramic
Resistor

2.5 to 5.5

-10 to 70

Resistor

2.7 to 5.5

-20 to 70

OSC
(rnA)

1.6

Standby
(PAl

50

temp.

Package

16D1P
laDIP

18~~~14c3

48

1.6

50

Rasistor

2.7 to 5.5

Evaluation
board

Ramarks

LU590H2A

p...

26

48QFP
LU550H2A

SIO(8·bit)

36

LU578HZA

SIOIS·bit)

49

r--

-20to7Q

64SDlP
64QFP

9·bit
41

SM5E4

Total

Current
consumption
Opera~inlJ

60QFP

16

SM578

110

Controllers

SM5J5

52

Caramie

1.6

2.7 to 5.5

-100070

20 piDs

64SDlP

50
16

48

68

15
12

31

52

S·bit
10 pins

52

S·bit
10 pins

-10 to 70

SOQFP

LU5E3H2

SIO(8·bit)

Caramie

2.7 to 5.5

-10toSO

64QFP
64SDlP

LU5J5H2

SIO(8·bit)

Caramie
Resistor

4.5 to 5.5

-10 to 70

64QFP
64SDlP

LU5J5H2

SlO(8·bit)
Medium power
output -40V

120
10

65

2.7 to 5.5

r--

Resistor

1.6

75

4.5 to 5.5

83
SM5J5

*1
*2
*3

i!'1

I"

S192X9

256X4

12

31

.2.5

3*2

OTPROM
Vosp open
Applicable to SM595. SM591

. -....... -----~-------SHARP ~.--. --~------3

Product Lineup

........................................................................................
(3)

LCD Driver Series

ROM (bit)

RAM (bit)

Model No.

40X4

SM500

Application
General-purpose

52X4

SM531

Clocks

80x4

SM5Kl

General-purpose

88X4

SM530

1.2K

Clocks

2K
2.7K

General-purpose

96X4

SM4A

128X4

SM510

132

SM511

General-purpose

SM512

Multi-segment system

SM563

Controllers

128X4
4K
160X4

Memory(bit)

Port

LCDrlrive

Model No.

ROM
SM530
SM531

RAM

2016x8

0

lIO

Total

Segment

Duty ratio

(Ps)

consumptIon

OSC
Operating
(PAl

Standby

Supply
voltage

Operating
temp.
(C)

Package

(V)

Evaluation
board

Remarks

Page

(PA)

64X4
2.tX4

8

58

66

..tgX2

112 duty
liZ bias

91.6

12

1.5

Crystal

1.5

-10 to 60

80QFP LU530H2A

Built-in melody
generator

100

1260xg
128X7

3ZX,l
20X4

6

42

48

40X2

1/2 duty
112 btas

91.6

10

1.5

Crystal

1.5

-10 to 60

60QFP LU530H2A

Built-in melody
generator

110

40

28X2
(MAX)

-20 to 70

48QFP LU500H2A

-20 to 70

48QFP
LU5KIH2A
42SDlP
LU041H2A

8*2

.lOX4

SM5K1

1280xg

64X4
16X-l

6

25

SM4A

2268xg

96X4

6

40

50

SM510

2772X8

96X4
32X4

6

47

53

SM511

-I032X8
256X6

96x4
32X4

SM512

4032Xg
2S6X6

80X4
48X4

6

63

SM563

4096X8

128x4
32x4

4

21

ROM (Upper:
Lower:
RAM (upper:
Lower:

4

Current
Instruction
eyele

256X6

1197xg

SM5DO

IGeneral-purpose

6

6

26

39

Program ROM]
Melody ROM
Data RAM ]
Display RAM

1
+/5 *2

*1
*2
*3

20

Crystal

114 duty

1000

1/3 bias

(5V)

*3

112 bias

61

2.4 to 5,5

34'><2

112 duly
112 bias

61

50

10

Crystal

-5 to 55

33X4

114 duty
113 bias

61

40

15

Crystal

o to 50

3-1X-1

114 duly
1/3 bias

69

SOX4

114 duly
113 bias

61

50

20

51

32x4

1/4 dul)'

2

400

8

113 bias

(5V)

(3V)

(3V)

53

47

16X4

112 duty

61

Emulation by a bread board
Available for segment output
Crystal or ceramic oscillator

45

IS

o to 50

Crystal

o to 50

Crystal
Resistor

2.7 to 5.5

-20 to 70

60QFP

119
LED direct drive
113 duty

141
149

60QFP LU510H2A

60QFP

*1

Built·in melody
generator

80QFP

*i

Built·in melody
generator

64QFP LU563H2A

128

SIO (8-blts)

159

172

Product Lineup

_ _~_ _ _.-..r_ _~

~~~--~~--~--"""'

•

8-bit Single-chip Microcomputers
(1)

Controller Series (Z8® Family/SM Series)
ROM (byte)
ROMless

Process

Model No.
LH0881/A

RAM (bit)

Application
Controllers

124X8
Controllers

I LU800Vl/AVl
ROMless

236X8

II

LU805BV2

I HNMOS I

2K

128X8

II

LH0801/A

IHNMOSI Controllers

124X8

LH0811/A

Controllers

4K

SM803/A

Controllers

SM805

Contorllers

I
8K

256X8

II

Controllers

[I

(2) ASSP Series

ROM (byte)

RAM (bit)

Model No.

Process

Application

~~~~~~====~~~2~5~6X~8~~~====l[11:S:M8~2~02~/~S~M~82:0:3I11~~C~M~O;S~IV;C=R=S======~==~
12K
512 X8
II
SM8320
I H CMOS IInverter air conditioners I
10K

[

Memory(bit)

Model No.

Process

ROM

RAM

Pari

External
memory
(bit)

I

0

4

4

110 Total

LH0881/A

NMOS

-

lZ4X8

128K

LH0801/A

NMOS

Z04BXB

124X8

124K

. LH0811/A

NMOS

4096X8

124XB

120K

LU8OOV1/AV1

CMOS

-

124XB

128K

4

8

16

CMOS

-

•

LU805BV2

236x8

128K

4

4

8

16

SMS05IA

124XS

120K

CMOS

S192X8

236X8

112K

4

4

24

32·

SU8202
256X8

-

4

24

32

*1
*2
*3

CMOS

122~8X8

231

1.5/1

Current
consumption

OSC
(mA)

(JlA)

180

-

16

24

256X4

-

6

40

Operating
temp.
11:)

Package

o to 70

40DlP
44QFJ

LHBOH321

HOFP
40DIP
44QFJ

*1
LH80H321

Evaluation

boa,.

Remarks

Page

Built·in
[ull duplex
UART Z8

r---

lICE)
203

.....

6

6

233

1.5/1

IS

0.3

U",

6

233

0.75

15

0.3

.".

48

RAM
area

54

RAM
area

Crystal

Crystal

6

233

1.5/1

10

64

0.8

U",

8

Supply
voltage

IV)

Operating Siandby

15

U..,

8

SM8203

SU8320

ion sel

tion
cycle
(PS)

RAM

CMOS

lO240X8

n·
true·

U..,

4096X8

CMOS

I'Istruc

ater,upt

16
RAM

4

5MB03IA

8

.

Sub·
rout
;

8

81

1

10

-

4.S
to 5.25

'.5
to 5.5

Oto 70

CMOSZS

0.3

-

-

Crystal

Crystal
Ceramic

'.5
to 5.5

-2"
to 70

64SDIP

4.5
to 5.5

-2"
to 70

64SDIP
64QFP

Built·in
fuU"duplex
UART

LU8200H7

SEon·o
controller

188

220

r--207

226

Increased
function

-

*2. *3

243

There is a slight difference in the 110 characteristics betweefl the LH8DH321 and the SM800 series.
Built-in PWM generator circuits
Built·in AID, SIO

-~----·---'---'~SHARP~---.--~~.--

5

.

................,....,................,..........,....,....,..........,..........,....,....,......
Product Lineup

Support Tools for 4-bit Single-chip Microcomputers

•
(1)

4-bit Single-chip Microcomputer Development Support System

The software program for. 4-bit singlechip microcomputers can be developed
through a simple system composed of a
personal computer running on an MSDOS™ operating system serving as a
host computer, and a debugging unit that
includes an emulator and an evaluation
board. Sharp also offers a highperformance SM emulator (SME-30).

MS-DOSTMis a trademark of Microsoft Corporation.

(2)

4-bit Single-chip Microcomputer Development Support Tools (SME-30 System)
SME-30 System

• Target microcomputers:
4-bit single-chip microcomputers
• Emulator:
SME-30 (LU4DH300)
• Evaluation board
• Host computer
• Optional software:
Cross-assembler
Emulator software
PROM programmer

SM series

Evaluation board

Evaluation card

SM4A

LU041H2

LU041H4

-

SM500

LU500H2A

LU500H4A

-

SM510

LU510H2A

LU510H4A

-

SM511/512

Emulation by a
bread board

Emulation by a
bread board

-

SM530/531

LU530H2A

LU530H4A

-

SM550/5.51/552

LU550H2A

LU550H4A

LU563H2

LU563H4

SM578/579

LU578H2A

LU578H4A

LU578H6

SM590/591/595

LU590H2A

LU59.0H4A

LU590H6

SM5E4

LU5E3H2

LU5E3H4

SM5J5

LU5J5H2

LU5J5H4A

SM563

Piggy-back

Page

254

-

LU550H6
-

254

-

LU5J5H6

--------------SHARP,,---~------...-; ....... - - -

6

Product Lineup
.-..r.-..r.-..r.-_.-..r.-.-..r.-.-.-.-..r.-.-~.-..r.-.-..r

•

Support Tools for 8-bit Single-chip Microcomputers
(1)

8-bit Single-chip Microcomputer Development Support System

The software program for 8-bit single·chip microcomputers can be developed
through a system consisting of a personal
computer (MS_DOSTM) serving as a host
and in·circuit emulator tailored to each
model.

MS-DOSTM is a trademark of Microsoft Corporation.

IBM PC AT.)
Emulator

(2)

8-bit Single-chip Microcomputer Development Support Tools
Model No.

Piggy-back

SM8202

In-circuit emulator
LU8200H71-LU8202H4

LU8203H6
SM8203

Page
263

LU8200H71-LU8203H4

*

The SM82 ICE (LU8200H7) with applicable emulation pods (LU820XH4) will meet each model of the
SM82 series.

Support tool

SM82 In·circuit emulator
(LU8200H7)

Features
• 64K bytes of emulation memory
• RS232C interface with the host
• Instruction cycle time count
• Line assembler and reverse
assembler

Page

• Centronics interface
• Coverage function
263

----------SHARP ....-..--..-.---.-.-7

Product Lineup

...................................................................................
(3) a-bit Microprocessors (ZaO® Family)
Clock frequency

Process

Product

Model No.

(MHz)

Function
2.5

LH5080/M

CPU

Central Processing Unit

LH5080A/AM
LH5081 1M

CMOS

PIO

LH5081A1AM

Parallel liD Unit

LH5081B
LH5082/M

CTC

LH5082A1AM

Counter/Timer Circuit

LH5082B
LHOO80/M/U
LH0080Al AMIAU

CPU

Central Processing Unit

LHOO80B/BU
LHOO80E
LHOO81/M/U
LHOO81A1AM/AU

PIO

Parallel 110 Unit
LHOO81B/BU
LHOO81E
LHOO82/M/U
LHOO82A1 AMIAU

CTC

Counter/Timer Circuit

LHOO82B/BU
LHOO82E

NMOS

LHOO83

DMA

Direct Memory Access

LHOO83A
LHOO84/85/86

LHOO87M/U
LHOO84A185A186A

SID

Serial I/O Unit

LHOO87AM/AU
LHOO84B/85B/86B
LHOO87BU

SCC'!

LH8530P/U
LH8530AP/AU

*1

Serial Communications
Controller

Z8500™ family

(4)

4

6

8

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Clock

Product

Function

Model No.

frequen~y
(MHz)
5

V20'!

LH70108-5
LH70108-8

CMOS

16-bit Microprocessors (V Series)

V30'!

LH70116-5
LH70116-8

a

Supply
voltage

Package

Page

(V)

40DIP/44QFP
138

5±10%

268
40DIP/44QFP
40DIP/44QFP

44

5±1O%

40DIP/44QFP

274

40DIP
28DIP/44QFP
44

5±10%

28DIP/44QFP

279

28DIP
40DIP/44QFP/44QFJ
40DIP/44QFP/44QFJ
1050

284

5±5%
40DIP/44QFJ
40DIP
40DIP/44QFP/44QFJ
40DIP/44QFP/44QFJ

525

5±5%

309
40DIP/44QFJ
40DIP
28DIP/44QFP/44QFJ
28DIP 144QFP/44QFJ

630

319

5±5%
28DIP/44QFJ
~

28DIP
40DIP
1050

329

5±5%
40DIP
40DIP
40QFP/44QFJ
40DIP

525

344

5±5%
40QFP/44QFJ
40DIP
44QFJ
40DIP 144QFJ

1313

354

5±5%
40DIP144QFJ

1470

16-bit Microprocessors (V Series)

Process

*1

Power
conswnption
(mW)MAX.

V20/V30 is a trademark of NEC Corporation.

Power
consumption

(mW)MAX.

Supply
voltage

Package

Page

(V)

8

•
•
•
•

40DIP
370
40DIP
420

5±5%
40DIP
414
40DIP

.....

.....

.-.-.-~

.-~.-~.-.-

.....

Package Outline

~....,....,.-~

Package Outline
16DIP (DIP16-P-300)

16

9

18DIP (DIP18-P-300)

7.62TI"I'.

20DIP (DIP20-P-300)

20

11

9

....- ........

........

Package Outline

.-..-..-.~.-..-.~.-.~

.-.~

.-.

28DIP (DIP28-P-600)
28

I

1

36.0. 0. 3

-G:::::C::~}~
15

14 ~
ij, ~

r----+-~~::-T-~~
·11 r: 0.5.·±0.5
~

I:

15.24

TYP

~I

~ u:: ~,
I

""
M

40DlP (DIP40-P-600)

42SDIP (SDIP42-P-600)

--lI---

---+-

-f....H--l"-~

M

38.2±0.3

15.24TYP.

'-'---~---~-SHARP--,---,--------

10

..........

~~

..... ............... .........................

Package Outline

~....."

~

64SDIP (SDIP64-P-750)
64

~

~

33

58.0-,-0.3

32 I' ~M I~'

--------------;.I~ ~l

""'
<'>

"'18~~(

<'>
""'M

~I

19.05 TY I'·

<'>
".;

I

~

440FP (OFP44-P-1010A)

---~---~--SHARP----'-'-'---

11

Package Outline
_ _Nl_ _ _

~~~

_ _ _" " ' _

""'_""'_""'~""'

44QFP (QFP44-P-1414)

0.38±0.1

'"
......

--~

p;

>-

E00

0

34

,

-$

.-.J-.-.
-$-

I

22

~

d

d

~

~

""

00

;::~

12

'"
~

(1.9)

48QFP (QFP48-P-1010)
0.75 TYP . 0.33±0.1

d

;;;-

":

......
......

~

:::;

---------~-SHARP----.-------12

---------------------Package Outline

60QFP (QFP60-P-1414)
O.8 TYP .

O.38±o.1

O.15±O.os

17.8±o.4

64QFP (QFP64-P-1420)

O.}±O.l-~<-

-;;-.--_---.-:51

.,;
~

-~~.

ci

"

00

~

~

;:!;

1~

I
!

;H:=:::f1~rrrn;rn7i"mnlrrn;::::;:;=;:;=;rt=iT'i'i~1"""'191120
(2.4)

20.0±O.2.

(2.4)

~L.
I
(22.98)

,,/

.,;
~

~

o

--·--------.---r-SHARP------.-......-.-.....-.·.-...-.
13

................,..............-.....,.....,.....,..........-.-.....,.....,........
Package. O~tline

80QFP (QfP80-P-1818)

80QFP (QFP80-P-1420)

+

8°immooUOOiXiOOoorn~oom
~. (2.4)

~

I: . I..

24.8~o.4

1<

:1

fiMzmIDlJmnrm!MnMnnnnnn~4
I. .
...1
(22.98) .

I!l

'"...."
or.>

o

14

Package Outline
.-...-...-...-...-...-..~.-..~.-...-..-~.-...-...-...-...-..

44QFJ (QFJ44-P-S650)

1.27TYI'~

C1.1

6·'

29

17
18

16.6
17.5±0.1

28

15

....... - . -......-.-.-...-................ -.....-.-..-_.Quality Assurance

Quality Assurance
1.

Quality Assurance System

Sharp develops and manufactures a wide range
of consumer and industrial-use semiconductor products.
In recent years, the applications of ICs have expanded significantly, into fields where extremely
high levels of quality are critical.
In response, Sharp has implemented a total quality assurance system that encompasses the entire
production process from planning to after-sales
service. This system ensures that reliability is a
priority in the planning and manufacturing stages,
and guarantees product quality through rigorous
reliabirity testing. We will introduce a part of this
system here.
Sharp's quality and reliability assurance activities are based on the following guidelines:
(1) All personnel should participate in quality
assurance by continually cultivating a higher
level of quality awareness.
(2) In the developmental stage of new products,
create designs that consider reliability in every respect..
(3) In addtion to quality control in all manufacturing processes, all working environments, materials, equipment, and measuring devires
should be carefully monitored to ensure quality and reliability from the very begining of the
process.
(4) Confirm long-term reliability and obtain a
thorough understanding of practical limits
through reliabilty tesing.
(5) Continually work to improve quality through
application of data from process inspections,
reliabilty testing, and market surveys.

2.

Quality and Reliability Contol in New
Product Development

The development of new products begins with a
thorough understanding of the product specifications and quality that will satisfy the purpose for
which the product is intended and with developmental planning that carefully considers pricing,
quantity, the time of introduction to the market and
the target reliability.
In the design stage, reliability is designed into
the product based on test data, process capability,
and field data, and experimental models are made.
These trial products are referred to as TS (technical samples), and are evaluated primarily for their

16

Product planning

Desision of target
reliability

~

.~

....

.~

8

~
.~

"CJ

I -_ _ _ Evaluation of functions

and performance

~

:E
.~

"
i>::

Evaluation of quality
1 - - - - and mass producibility

I----~Evaluation

I--~

Fig. 1

of reliability

_ _ Decision to mass
produce

New Product Development Steps

ability to function and their perfomance.
Next, ES (engineering samples) are made and evaluated to detemine whether the functions, performance and quality aimed for in the disign stage
can be guaranteed under the existing manufacturing conditions. These ES are also evaluated in
quality and reliability tests to determine whether
their long-term reliability can be guaranteed.
At the final stage, the availability for massproduction will be deliberated based upon the
evaluation result of TS and ES. After transition to
the mass production step, pilot production will be
performed to confirm the quality and reliability
obtained on the way of designing, and variations in
the process. It will be judged whether or not massproduction is available according to the result.
DR (Desing Review) is performed to prevent
from faulty operation and to enhance the functions,
usability, quality and reliability, upon completion
of structural design, software design, circuit design, TS/ES evaluation and reliability tests. Fig. 1
shows the steps in the development of new products.

Quality Assurance

Process

~~

Silicon
wafers

C

Control items
..

~ ~------~--t----------------------I

Purchase of material
Inspection upon receipt

Appearance, dimensions,
specific resistance

Eliminate items with incorrect dimensions,
scratches, and crystal defects and assure
resistance values,

Appearance, film thickness

Confirm the absence of pin holes and
assure firm thickness,
Check the cleanliness of surfaces.

Oxidation
Oxidation inspection
On line QC

Surface cleanliness

Development, etching

Check the suitability of development and
etching.

Wire width

Control the wire width.

Electrical characteristics

Elminate items with unsuitable electrical
characteristics.

Appearance

Confirm the absence of breakage and
chips.

Appearance, bond strength

Check quality of die bond.

Wire bonding inspection

Appearance, tensile strength

Check position and shape of bond and
assure sufficient tensile strength.

Sealing/molding
Monitoring

Heat, time, pressure
Wire bond

Assure original shape
Assure wire shape

Lead surface
finishing

Ingredient,
temperature, pollution

Assure finishing quality

Finishing inspection
Monitoring

Thickness, uniformity
(soldering conditions)
Plate making,
plate thickness

Approval

Temperature, time,
marking material

Assure marking quality

Lead cutting

Mold sharpness
damage-proof

Irregular stress to resin,

Forming

Mold dimensions

Dimensions

On line QC
Ion implantation
I

I

Chip electrical inspection

I
I

Dicing
Breakage screening
Die inspection

Die bonding
Die bonding inspection
Wire bonding

Stabilized baking

Fig. 2

Assure plating quality

Example of process quality control

----------SHARP----------17

Quality Assurance

..................................................................................
3.

Quality and Reliability Control in Mass
Production

(1) Quality Control of Materials
The quality and reliability of a product is
affected by its component materials as weIl as the
manufacturing processes and conditions.
The quality control of purchased component
materials is' basicaIly ensured by a material sup·
plier, based upon the quality control system be·
tween SHARP and a supplier as foIlows.
· Selection of suppliers prior to the placement of
purchase order.
• Material qualification upon receipt of new
materials. (Evaluation of device quality and
reliability used with new materials.)
• Regular quality meeting based upon quality in·
formation when mass production between both
parties.
The incoming inspection may be p~rformed
according to the inspection standard based upon
approved specifications.
(2) Control of Manufacturing Environment
Environmental conditions in the manufacturing
process-such as temperature, humidity and dust
-significantly affect the finished quality of semi·
conductor products.
Temperature is especiaIly critical in maintaining
the accuracy of the measurements of electrical char·
acteristics and the accuracy of various devices.
Humidity control is important for the prevention of
moisture penetration into a device and the preven·
tion of static electricity. Temperature and humidity
are thus strictly maintained at constant levels.
A dust·free environment is vital in the manufac·
ture of refined semiconductor circuits, as dust can
be the critical determining factor in their quality
and reliability. Thus, cleanliness of everything
from air conditioning equipment to work benches
to work clothes and office items is carefuIly con·
troIled.
Sharp is also concerned about creating an en·
vironment conductive to error· free high-precision
work, and so provides background music and interior colors appropriate for specific tasks.
(3) ControL of Manufacturing Equipment and
Measuring Devices
Tremendous technological innovations and progress has been made in integrated circuits and in
the processes and equipment by which they are
produced.
To achieve even higher levels of product uniformity and quality, Sharp is continuaIly further·
ing the automation of its processes, strictly manag·

ing the maintenance of its manufacturing equipment, and carefuIly monitoring the accuracy of all
measuring devices through daily and periodic inspections.
The productive control is systematized based
upon TPM (Total Productive Maintenance). Sharp
is cultivating experts in productive maintenance
through a self-maintenance, a planning maintenance, a repair maintenance.
The measuring device is controlled with the regular proof by an officially authorized constitution
based upon national standard, in order to keep
high precision.
In the process

Regular reliability tests

*1
Warehousing

*
*

Fig.3

Static and dynamic
burn·in
2 Electrical characteristics
and visual inspection
3 Sampling inspection
(per lot)

Product inspection system

(4)

Process Quality Control and Product
inspections
'
'Based on the fundamental concept of ensuring
quality and reliability throughout the manufactur·
ing process, we check at each stage to determine
whether the prescribed characteristics are being
obtained and to prevent defective items from going
on to the next stage. We do this thorough strict
monitoring, inspection of all items, sampling in·
spections, and other standardized methods of management.
We perform a final inspection of all finished products as well as further quality assurance inspections through sampling to fully ensure quality.

---.----.....-.,~--SHARP---~-----·-.-

18

Quality Assurance

Detects ,found in these inspections are promptly
reported to the design and production sections, and
improvements made in the processes to upgrade
our uniform quality capabilities.
Fig. 3 shows the product inspection system.
Fig. 4 shows an example of process quality
conto!.
(5) Reliability Assurance
To guarantee the long-term reliability of our products, we periodically sample products and subject

Table 1
Type

Life tests

Thermal
environmental
tests

Mechanical
environment tests

them to reliability testing such as life tests and environmental tests.
These tests are long-term reliability tests and
the obtained data will be given to the related sections.
The inspections and tests for quality assurance
are made to maintain and enhance the quality as
well as to predict the reliability of products in the
market. Thus assures quality and reliability of products from many aspect.

ReliabUity test 10' memmy p,od,cts

Test item

Test condition

Test objectives

High temperature
storage

Ta= 150"C

Evaluate resistance to high temperature in
long-term storage.

High temperature
operation

Ta=125·C or 150"C
power supply voltage (MAX.)

Evaluate resistance to long-term high temperature and electrical stress.

High temperature,
humidity storage

C!)85·C 85% RH
®PressUre cooker test, 121·C
100%RH, 15PSIG

Evaluate resistance to high temperature and
humidity in long-term storage.

High temperature,
humidity bias

85·C 85% RH
Power supply voltage (MAX.)

Evaluate resistance to long-term high temperature, humidity and electrical stress.

Low temperature
storage

Ta=-65·C

Evaluate resistance to low temperature in longterm storage.

Temperature
cycling

Tstg(MAX.)-Tstg(MIN.)
- 65 "C to 150"C air

Evaluate resistance to sudden extreme temperature changes.

Thermal shock

Tstg(MAX.)- Tstg(MIN.)
-65"C to 150·C liq

Evaluate resistance to sudden extreme temperature changes.

Resistance to solder heat

260·C lOs

Evaluate resistance to thermal stress during
soldering

Mechanical shock

1,500G, 0.5 ms ±X, ±Y, ±Z

Evaluate structural and mechanical resistance
to strong shocks.

Variablefrequency vibration

20G, 100 to 2,000 Hz, X, Y, Z

Evaluate resistance to vibration during transport and use.

Constant
accelration

20,000G±X, ±Y, ±Z

Evaluate resistance to constant acceleration.

Lead fatigue

Lead pull: holds fixed load for 10
seconds
Lead bend: bend once 90 in forward
and reverse directions
(Load is determined based on pin
shape and the surface area of pins section.)

Evaluate resistance to mechanical stress applied to pins.

Hermecity

Test for minute leaks using helium gas
and large leaks using foaming.

Evaluate hermetic sealing.

Salt atmosphere

Spray 5% salt solution
at Ta=35·C for 24 hours

Evaluate resistance to corrosion in salt spray
environment.

Solderibility

230·C for 5 seconds (with flux)

Evaluate solderability of pins.

19

r:i""]
LlJ

Quality Assurance

....-.....-.--....-.....-.-....-.---....-.---....-.-....-.
~t
Step

Sales

(

Planning

I

I

Engineering

I

I Production
I Quality
assurance
control

P fOd ucrIOn

)

Market research
~

( Development) (

Elementary technology development

Planning

(

)

Investigation of specification
~

I

(

I

(
(

Function )lES

I
TS

'"'

I

TS

•
Logic design )

DR I logic design & software
t
Layout
)
t
DRII layout
t
TS/ES making
)

(

Development,
desing,
trial production

I

Development plan decision (New product planning conference)

(

J
I

•
t
• I
DRIll TS evaluation, process evaluation
I
•
Productive evaluation
) ( Reliability test)
~

t

~

I

ES

I

DRN ES evaluation

t

I

General evaluation (New product debut conference)

~prOduction standard/Inspection standard making
(

I
)

)

Pilot production
~

(

)

Sample evaluation
~

I

I

General evaluation (Mass production go ahead conference)
Production control

K
Mass-production

(

Interim inspection

r

(

Final inspection

}-

Measuring control

t

Regular sampling

~
Warehousing)
\.

Feedback
Market

(Market claimr-

Fig. 4

quality information

Reliability test

1

Failure analysis

t

)--

)

.r--

Correction instruction

'" Recejpt and reply )

Quality assurance system

-----------------$HARP

20

)

Process control
Inspection
Burn-in

~Shipping inspection

(

)

Raw material control

J Production
\.

)

-~.-----~--.-,

......-...-......,.....,.....,.....,.-...-......,.....,.....,.....,.-..
Quality Assurance

.-...-.......,.....,
4.

findings concerning the design, manufacturing process, or method of use to the departments concerned for preventive action against recurrence of
the malfunction. We then submit a report to the
customer.
This process of tracking the performance of our
products in actual use is an extermely effective
way to enchance product reliabilty. We direct a lot
of energy forwards its full implementation.
Fig. 5 shows the quality information flowchart,
and Fig. 6 shows the procedures used in their
analysis.

Reliability Tests

In addition to determining the extent to which
product reliability can be assured, the objectives of
reliability testing include getting an understanding
of design limitations and the catastrophic failure
mode, and prediction reliability in the field.
The major categories of reliability testing are
life tests, thermal environmental tests, and mechanical environment tests. The standardized test
methods used are those prescribed by official standards or associaitions such as the International
Electronics Commission (IEC), and the U. S. Military Specifications (MIL). Sharp standardizes all
specifications to conform with these standerds.
Table 1 shows a representative reliability test.

5.

6.

All of the semiconductor products listed in this
data book were manufactured based on exacting
designs and under compreshensive quality control.
However, to take full advantage of the features
offered and assure the products' long-life service,
please refer to this manual to help in designing systems that make best use of their capabilities.
(1) Maximum Ratings
It is generally known that the failure rate of
semiconductor products increases as the tempera-

After-sales Service

If a product malfunction after shipment, we have
the customer return the product for detailed analysis. We also obtain complete information concerning conditions of use, frequency of occurrence, and
symptoms.
When the cause has been determined, we report

Tro uble, accident
Clai m
Qua lity requirement

/
/

I

Handling Precautions

-----

Customer

bwer supply (2.5 to 5.5V)
11. Instruction cycle'
Voo=3V: 41-'-s (MIN.)
Voo=5V: 11-'-s (MIN.)
12. 16-pinDIP (DIP16-P-300)
IS-pin DIP (DIP1S-P-300)
20-pin DIP (DIP20-P-300)

26

.•

18DIP

20DIP

o

. Top View

SM590/SM591/SM595

4-Bit Microcomputer (Controller for Low Power Systems)

•

Block Diagram

SM590 32X4
SM591 56X4
SM595 32X4

ROM

SM590 508x8
SM591 1016x8
SM595 762X8

Symbol description
Ace
: Accumulators
ALU
: Arithmetic logic unit
B
: RAM address register
C
: Carry F/F
CG
: Clock generator

Note:

•

PC
RO-R3
SP
SR
X

: Program counter
: Registers

: Stack pointer
: Stack register
: Temporary register

Pin numbers apply to 20-pin DIP only.

Pin Description
Pin name
RO o-R0 3
Rl o-R1 3
R2 o-R2 3
R3 0 -R3 2

ACL
CL I
R3 3 /CL 2
V DD

GND
Note 1:
Note 2:
Note 3:

110
110
110
110
110
I

0

Pull
Pull
Pull
Pull
Pull

Circuit type
down
down
down
down
down

Function
Input/Output ports
Input/Output ports
Input/Output ports
Input/Output ports
Auto clear
System clock oscillation
Output! system clock oscillation
Power supply for logic circuit
Ground

Note
1
1
2
1

3

Open drain 110 or CMOS outputs selectable with a mask option.
Open drain 110 is selectable with a mask option.
An external clock should be applied when the R3 3 output port is selected with a mask option.

27

SM590lSM591lSM595

4-Bit Microcomputer (Controller for Low Power Systems)

•

Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Source output current sum
Sync output current sum
Operating temperature
Storage temperature

•

Symbol
VDD
VI
Vo
::£IoH
::£IoL
Topr
Tstg

Rating
-0.3 to +7.5
-0.3 to VDD +0.3
-0.3 to VDD +0.3
120
20
-10 to +70
-55 to +150

Unit
V
V
V
rnA
rnA

"C
"C

(Ta=-10 to +70·C)

Recommended Operating Conditions
Parameter
Supply voltage
Instruction cycle

Symbol
VDD
tSYS

Conditions
VDD =3V±0.5V
VDD=5V+0.5V

---"'-'~---------SHARP

28

MIN.
2.5
4

1

TYP.

MAX.
5.5
50
50

Unit
V
ps

- - . . . - - - . . - - - - - - - - - ......... -

SM590/SM591/SM595

4-Bit Microcomputer (Controller for Low Power Systems)

•

Electrical Characteristics
Parameter

Input voltage

Symbol
VIHI
VILI
VIH2
VIL2
VIL3
11 VI
VIH3

(Voo=2.7 to 5.5V, Ta=-lQ-to +70'C)
Conditions

Voo =5V±10%
Voo=3V
Voo=5V
Voo =5V±10%
Voo=3V
Voo=5V

IIHI

VIN=Voo

IIH2

VIN=Voo

IAI

tsys=2 ps

IA2

tsys=10ps

1ST

Standby mode
Voo =5V±10%
VoH =V oo -2V
VoH =Voo -0.5V
VOL =O.4V
CMOS output
VOL =O.4V
Pull-down output
Voo=5V±1O%
VoH =Voo -2V

Input current

Current
consumption

10Hl

lOLl

IOH2

VoH =Voo -0.5V
IOL2

IOH3

IOL3

IOH4

VOL =O.4V
CMOS output
VOL =O.4V
Pull-down output
Voo =5V±10%
VoH =Voo -2V
VoH =Voo -0.5V
Voo =5V±10%
VoH =Voo -2V
VoH =Voo -0.5V

IOL4

TYP.

1.4

SM595
SM595
SM590/SM591

SM595
SM595
Voo-3V±1O%
Voo =5V±10%
Voo =3V±10%
Voo =5V±10%
Voo=5V±1O%
Voo =3V±10%
Voo =5V±10%

1.1
2.8
4.6
15
70

2.0

SM595
Voo=5V±1O%
Voo -5V+10%
SM590/SM591

SM595
SM590/SM59,l

SM595
Voo =5V±10%

SM590/SM591

SM,595
Voo =5V±10%
Voo =5V±10%
SM590/SM591

SM595
SM590/SM591

SM595
SM590/SM591

SM595
VOL =O.4V
Voo =5V±10%
CMOS output
VOL =O.4V
Voo =5V±10%
Pull-down output

10
7
1
1.6
0.8
15
8
4
3
0.5
0.4
15
8
4
3
0.5
0.4
1.6
0.8
15
8
10
7
1
3
2
0.4
0.3
1.6
0.8
15
8

MAX.
Voo
0.3Voo
Voo
0.5
2.1
0.5
0.7
3.1

Unit
V
V
V
V

Note
1
2

V
V

3

V
70
250
7
20
1
100
200
L

SM590/SM591

VOL =O.4V
Pull-down output
Voo =5V±10% SM590/SM591
VoH =Voo -2V
SM595
VoH =Voo -0.5V

Output current

SM590/SM591

MIN.
0.7Voo'
0
Voo -0.5
0
0.7

200
750
20
60
3
200
500
2

pA

1

pA

4

mA

pA

5

pA
mA
mA

6

pA

mA
7

pA

mA
8
mA

pA
9,10
mA

t--9,11

mA
9

pA

- - - - . - " . - - - - - - - ! 5 t i A R P --~ .......... - - - - - - - - -

29

SM590/SM591 ISM 595

4""'Bit Microcomputer (Controller for Low Power Systems)

Parameter

Output current

Symbol

IOH5

IOL5
Note 1:
Note 2:
Note 3:

Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
NoteIO:
Notell:
NoteI2:

•

Conditions
VDD =5V±10%
SM590/SM591
VOH =V DD -2V
SM595
SM590/SM591
VOH =V DD -0.5V
SM595
VDD =5V±10%
VoL=Oo4V
CMOS output

MIN.
1
0.7
0.15
0.1
0.6
0.3

TYP.

MAX.

Unit

Note

rnA
12
rnA

Applied to pins ROo-R03• Rio-RI3. R2o-R23. R3 0 -R3 3.
Applied to pins ACL and CLI'
Applied to pin R2 2 • (When a standby clear signal is input.)
VIL3: Oscillation start input voltage (No oscillation is occurred under this level.)
V IH3 : Systemclock start voltage (See Fig. 7)
b. VI: V'H3-V'L3
Applied to pin ACL.
No load condition.
Applied to pins ROo-R0 3• Rio-RI3. R3 1 •
Applied to pins R2o-R23'
Applied to pin R3~.
Applied to pin R3 2 •
When the content of R latch is output from the pin R3 2 •
When the clock input to the pin CL I is output from pin R3 2 •
Applied ~o pin CL 2 /R3 3.

Oscillator Circuits

CL I and CL z are the clock oscillator input and
output ports respectively. The basic clock signal
can be obtained by the ceramic oscillator and resis·
tor. The external clock signal may also be pro·
vided. (See Fig. 1.)

For an external clock input. provide the external
clock to the CL I pin. In this case. the CL z pin can
be used as the output pin (R3 3 pin) with a mask op·
tion.
The internal system clock is equivalent to the
basic clock supplied to the CL I pin divided by four.

~ tr

R
(capacitor is built-in)

~

J;

Ceramic oscillator

CR oscillator

External clock

Fig. 1 Reference clock generator circuit

•

External Input Signal AC Characteristics
Parameter
Clock rise time
Clock fall time
Clock pulse width
Note:

30

Symbol
t,
tf
tL
tH

When external clock is input.

Conditions
VDD=2.5 to 5.5V
VDD=2.5 to 5.5V
V DD =5V±0.5V
VDD=3V+0.5V

MIN.

0.08
0045

TYP.

MAX.
50
50
6.3
6.3

Unit
ns
flS

4-Bit Microcomputer (Controller for Low Power Systems)

•

Pin Descriptions

(1) V oo • GND (Power supply)
Apply 2.5 to 5.5V power supply to the VDD pin
with respect to GND pin which provides a reference level of the LSI.
(2) ACL (Reset pin)
The ACL pin is used to initialize the LSI. The
LSI will be reset upon completion of two instruction cycles after ACL pin goes High. The ACL (reset) mode will be cleared upon completion of one instruction cycle after ACL pin goes LOW.
Connect a capacitor between ACL and V DD to reset when power on. Two or more instruction cycles
should be taken for the ACL input.
When a ceramic oscillator is used for a system
clock, take a certain period of ACL time with the
oscillation to be stabled.

ACL

ACL

switch

'T
~

O.l.uF

Vrn

Fig. 2

ACL circuit

SM590/SM591 /SM595·

(3) R3 1-RO I 0=0 to 3) I/O pin
R3 j -RO j (i=O to 3) pins may be used for both input and output, and a pull-down resistor is connected to the output buffer.
Data should be transferred between ports
(R3 j -RO j ) specified by the BL and the accumulator
(Ace) or data memory by instructions.
When R3 j -RO j pins are used as inputs, reset the
output latch and connect a pull-down resistor to
the I/O pins.
Note: Upon completion of RTA instruction for R3 2 pin, the
contents of an internal output latch are loaded into the accumulator Ace.

The circuit type of R3 j -RO j can be used not only
as a pull-down type but also as the following two
types with a mask option.
Mask option I
When the R port is used as only output port with
a large sink current, it can be replaced with the
CMOS buffer.
Applicable pins:
RO o-R0 3 , Rl o-R1 3 , R3 0 -R3 2
Not applicable pins:
R2 o-R2 3
Mask option n
When the R port is used as only input port with
a reduced current flowing into the pull-down resistor, it can be replaced with an open drain with a
protective diode not to be pulled-down.
Note: The CL 2 /R3 3 pin can be used as R3 3 output pin with a
mask option. and the circuit type should be set to the CMOS
buffer.

31

[gj
2
_=~

4-Bit Microcomputer (Controller for Low Power Systems)

•

SM590/SM591/SM595
,
-

Hardware Configuration

(1) Program counter and stack
The ROM addresses can be specified by a program counter (PC).
The program counter (PC) consists of 10 bits including1 bit (Pu) for the field specification, 2 bits
(PM) for the page specification and 7 bits (Pd for
the step specification.
The PM for the page specification is a binary
counter, and the P L for the step specification is a
polynomial counter (provided that it is inhibited
forP L =7F).
.A 4-bit stack register enables 4 levels of subroutine nesting.
(2) Program memory (ROM)
The program memory (ROM) is used to store
programs. See Fig. 3 and Fig. 4 for ROM configuration.
1 field has a configuration of 4 pages X 127 steps
X8 bits.
The SM590 has 508 bytes of ROM which consists of 1 field (0) X 127 steps X 4 pages.
The SM591 has 1016 bytes of ROM which consists of 2 fields (0 and 1)X127 stepsX4 pages.
The SM595 has 762 bytes of ROM which consists of 1 field (0) X 127 steps X 4 pages + 1 field
(1)X127 steps X 2 pages.
The ACL program starts at field 0, page 0 and
step O.
When the standby mode is cleared, execute the
program at field 0, page 1 and step O.

The TR instruction is used to jump within a
page, while the TL (two-word) instruction is used
to jump to any desired address. The TLS instruction executes a subroutine jump to any desired
address.
(3) Data memory (RAM) and B register
The data memory (RAM) is used to store data.
The RAM size of the SM590 and SM595 is 16X2
X 4 (128 bits), while that of the SM591 is 16 X 3.5
X 4 (244 bits).
Each file consists of a 16 word X 4- bit configuration ·as shown in Fig. 5.
The RAM address is specified by a B register
composed of 1 -bit for the SM590/SM595 or 2 bits
for the SM591 of BM and 4 bits of BL •
--;;:'File
~u

1

i

0

2

3

0
1
2
3
4

5
6
7

8
9
A
B

C
D

I p::----------!u
Page
Page
Page
Page

0
1
2
3

Field 0
ACL start
Standby mode start

<- SM 590/595->
~--SM

~-'~

SM590 -~;;:.

~--SM591

Fig.3

E
F

Field 1

;;:.1

Fig. 5

591

;;:.1

RAM Configuration

ROM configuration (SM590/SM591)

~u
Field 0
Page 0
ACL start
Page 1
Standby mode start
Page 2
Page 3

Fig. 4

Field 1

ROM configuration (SM595)

(4) Accumulator (Ace> and X register
The accumlator (Ace) is a 4-bit register. It
transfers data to I/O ports and performs operations in combination with an arithmetic and logic
unit (ALU), a carry flag (C) and a RAM.
The X register is a 4-bit register used as a temporary register which transfers and compares data
with the Ace.

----------SHARP---..-..-.----32

SM590/SM591/SM595

4-Bit Microcomputer (Controller for Low Power Systems)

(5)

Arithmetic and logic unit (ALU) and carry
flag (C)

The arithmetic and logic unit (ALU) performs
4-bit parallel arithmetic operations. Executing the
ADC and ADCS instructions shifts the carry of operations into the carry flag (C).

"High"
R2 2 input

CL2

(6)

Output latches (R [0], R [1] R [2], R[3])

The output latches consist of 16 bits. 11 bits for
16 pin package, 13 bits for 18 pin package and 15
bits for 20 pin package of the output latches are
connected to external pins. The rest of the output
latches not connected to external pins can be used
as temporary registers.
The R output latches are specified by BL •

l

C

Fig. 6

(7)

System clock generator circuit

The system clock generator circuit divides the
basic clock supplied from the CLI pin, generates
the system clock.
The circuit externally outputs the clock signals
generated from clock oscillators (CLIo CL 2 ) through
R3 2 pin with a mask option.
This function enables to be synchronized with
other LSls.
Note that the instruction cycle time of 1 word instruction is equivalent to 1 cycle of system clocks.

i.~lIillllllll\l\l1111l111i

Oscill~tion Syste~ clock

start
Standby mode ..

I..

' start

·1

Oscillation
stabled

Fig. 7

(8)
SM590
SM591 R22 t---,--".Nv_ _ Standby clear
SM595
R
input

~

"Low"---- Unstabled Stabled

Clock timing for a ceramic ascillator

Standby function

Executing an instruction places the device in
standby mode to reduce current consumption.
The oscillator and the system clock are iactivated in standby mode.
When the R22 accepts High level in standby
mode, the standby mode is cleared and restarts
program execution at fie'ld 0, page 1 and step O.
If a ceramic oscillator is used as a clock generator, a delay circuit shown in Fig. 6 is required to
obtain the clock oscillation time to be stabled.
Fig. 7 shows the timing in this case.
(9)

Reset function (ACL)

Applying a High level signal to the ACL pin resets the carry flag (c) and the output latch, and the
input pins are pulled-down.
Be sure not to apply High level to both R20 and
R21 pins in the reset (ACL) mode.
Applying a Low level signal to the ACL pin
starts execution of the program at field 0, page 0,
step O.

-'---~---SHARP-------~

33

SM590/SM591/SM595

4-Bit,Microcomputer (Controller for Low Power Systems)

•

Instruction Set
(1)

ROM address instructions

Mnemonic Machine code
80-FE
TR x
78-7B
TL xyz
OO-FE
7C-7F
TLS xyz
OO-FE
RTN
4C
RTNS
4D

(~)

Operation
PL-1 6 -1 0 (jump within a page)
P u -I9 , PM+-I B, 17
PL+-1 6 -10 (jump to any page)
SP;-SP+l, SR+:-PC+2
Pu+'-IIi, PM+-I B, 17, P L +-16 -1 0
SP+-SP-'-l, PC+-SR
SP+-SP-,l, PC+-SR, Skip

Data transferinstruction$

Mnemonic Machine code
LAX x

30-3F

LBLX x
LBMXx
STR
LDA
EXC

20-2F
74-77
4A
40
41

EXCI

42

EXCD

43

EXAX
ATX
XBLA
BLTA

5D
5C
57
56

Operation
Acc- I 3 -I o Skip if last instruction is. LAX.
BL +-1 3 -1 0
BM+-lb 10
M+-Acc
Acc+-M
M-Acc
M-Acc , BL+-BL +1
Skip if Carry = 1
M-Acc,BL+-B L-1
Skip if Borrow = 1
Acc-X
X+-Acc
Acc-B L
AcC+-BL

(3)" Arithmetic instructions
Mnemonic
ADXx
ADD
ADS
ADC

Machine code
OO-OF
70
71
72

ADCS

73

COMA
INBL
DEBL
INBM
DEBM

44
52
53
50
51

34

Operation
Acc+-Acc+x, Skip if Carry=1
Acc+-Acc+ M
Ace+-Ace + M, Skip if Carry = 1
Acc+-Acc+M+C, C+-Carry
Acc+-Acc+ M +C, C+-Carry
Skip if Carry = 1
Acc+-Acc
BL +-BL + 1, Skip if Carry= 1
BL rBL -1, Skip if Borrow = 1
BM+-B M+l .
BM+-M M- l

(4)

Test instructions

Mnemonic
TAX x
TBA x
TMx
TAM
TC

Machine code
10-IF
64-67·
60-63
45
54

Skip
Skip
Skip
Skip
Skip

Operation
if Acc=x
if Accx=l (x=3 to 0)
if Mx= 1 (x=3 to 0)
if Acc=M
if C~1

(5)· Bit manipulation instructions
Operation
Mx""': 1 (x "=3 to 0)
Mx+-O (x=3 to 0)
C+-l
C+-O

Mnemonic Machine code
6C-6F
SM x
68-6B
RMx
49
SC
48
RC

(6)

I/O instructions

Mnemonic
ATR
MTR
RTA

Operation
Machine code
46
R (BLl+-Acc
R (Bd+-M
47
55
Acc+-R (BLl

(7) Special instructions
.'

Operation
Mnemonic Machine code
No Operation
NOP
00
Standby Mode
CCTRL 4B

SM590/SM591/SM595

4-Bit Microcomputer (Controller for Low Power Systems)

•

System Configuration Example

Amplifier

Detector

J--

~

PO,

System code set

PDs

Received
~ignal

POe

SYS,
SYS,

V DD

20
Q
Q

19
N

0

:>

'"i:>:: i:>::""

6

c5

SYS s

SYS 3

18 17
N

16
~

i:>::

i:>::

~

0

15
...<'

i:>::

SYS I

14
~

DIN

13 12 11
M ,.::; ,....,0
i:>::

i:>::

i:>::

,s ""
i:>::
U

....l
U

Q

i:>::

S

i:>::

PD o

1

i:>::

2

cS
i:>::

i:>::

M

i:>::

5

3 J4

U
';:,
i:>::

""

N

7

6

8

Z

~

9

"

10

POI

f-wv-

r--

PD7

-

PO,

Reset
input

~m-

PD 3

-

Receiver data

T

f

~

Remote control receiver

- - - - - - - - S H A R P . - . . . . . - , - _ _ -----~35

SM550/SM551/SM552

4-Bit Microcomputer (Controller)

SM550/SM551/SM552
•

Description

The SM550/SM5511SM552 is a CMOS 4-bit
microcomputer which integrates a 4-bit parallel
processing function, a ROM, a RAM, 110 ports, a
serial interface, a timer/event counter in a single
chip.
It provides five kinds of interrupt and a subroutine stack function using the RAM area, and
accesses on a byte-by-byte basis.
Operated from 3 to 5V single power supply with
high speed, this microcomputers applicable to
many applications from a battery back-up system
to a high performance system.

•

4-Bit Microcomputer
(Controller)

Pin Connections

SM550

17 RESET

SM551/SM552,_--__...

SM551/SM552

Top View
-'-"-'-'---~SHARP,-----'-----

36

4-Bit Microcomputer (Controller)

•

Features
1. CMOS process
2. ROM capacity
SM550: 1,024 X 8 bits
SM551: 2,048X8 bits
SM552: 4,096 X 8 bits
3. RAM capacity
SM550: 80X4 bits
SM551: 128X4 bits
SM552: 256X4 bits
4. Instruction set: 94
5. Subroutine stack: using RAM area
6. Instruction cycle:
1.74,us (MIN.) (VDD=5V)
5.3,us (MIN.) (V DD =3V)
7. Interrupts
External interrupts: 2
Internal interrupts: 3

•

SM550/SM551/SM552

8. Input/output ports
SM550: I/O ports 24
Input ports 4
Output ports 8
SM551/SM552: I/O ports 28
Input ports 4
Output ports 16
9. 8-bit serial I/O
10. Timer/counter: 1 set
11. On-chip crystal oscillator circuit and clock di·
vider circuit
12. On-chip system clock oscillator
13. Standby function
14. Expandable external data ROM/RAM
15. Supply voltage: 2.7 to 5.5V
16. SM550: 48-pin QFP (QFP48-P-1010)
SM551/SM552: 60-pin QFP
(QFP60-P-1414)
64-pin SDIP
(SDIP64-P-750)

Block Diagram
SM550

OSCIN
OSCoUT

37

SM550/SM551/SM552

4-Bit Microcomputer (Controller)

SM551/SM552

ROM

SM551 2,048 x 8
SM552 4,096 x 8

RESET· 60

OSC IN
OSC OUT

4
5

CK1
CK2

2

INTB

7

INTA

6

1

Symbol description
A,B
: Accumulators
ACL
: Auto clear circuit
ALU
: Arithmetic logic unit
CG
: Clock generator
DIV
: Divider
H, L, D, E : General-purpose registers
IE
: Interrupt enable F IF
1FT, IF A, IFS, IFB, IVV : Interrupt requests
IME
: Interrupt mask enable F IF
Note:

38

Pin numbers apply to a 60-pin QFP.

PU,PX
PO-PB
PSW
RD,RE,RF
SB
SP
TC
TM

: Program counters
: Registers
: Program status word register
: Mode registers
: Shift registers
: Stack pointer
: Count registers
: Module registers

SM550/SM551/SM552

4-Bit Microcomputer (Controller)

•

Pin Description
Symbol
PO O-P0 3 , Pl o-P1 3 , P4 o-P4 3 ,
P5 0 -P5 3 , P6 o-P6 3 , P8 o-P8 3
P9 0 -P9 3
P2 0 -P2 3 , P3 0 -P3 3
PA o-PA 3 , PB o-PB 3
P7 0 -P7 3
INTA,INTB
CK}, CK 2
OSC IN , OSC OUT

I/O

1>

0

Voo, GND
TEST
RESET

I
I

Note 1:

•

Function

Circuit type

I/O

Pull-up (I)

I/O
0
0
I
I

Pull-up (I)

Pull-up
Pull-up

Pull-down
Pull-up

Note

Input! output ports
Input/ output ports
Output ports
Output ports
Input ports
, Interrupt input ports
System clock CR oscillator
Crystal oscillator
Synchronous clock output
Power supply
Test input (normally connected toGND)
Reset input

1
1

Applied to the SM5511SM552.

Absolute Maximum Ratings
Parameter
Supply voltage
In put voltage
Output voltage
Output current
Operating temperature
Storage temperature
Note 1:
Note 2:

•

Symbol
Voo
VIN
VOUT

Rating
-0.3 to +7.5
-0.3 to Voo +0.3
-0.3 to Voo+0.3
40
-20to +70
-55 to + 150

lOUT

Topr
Tstg

Unit
V
V
V
mA

Note
1
1
1
2

"C
°C

The maximum applicable voltage on any pin with respect to GND.
Sum of current output from (or flowing into) output pin.

Recommended Operating,Conditions
Parameter
Supply voltage
Crystal oscillator frequency
Basic clock oscillator frequency
Note 1:
Note 2:

Symbol
Voo
fosc
f

Conditions

MIN.
2.7

TYP.

MAX.
5.5

32.768
Voo=5V
Voo=3V

0.25
0.25

2.3
0.75

Unit
V
kHz

Note

MHz

2

1

Oscillation starting time: within 10 seconds
Degree of fluctuation frequency: ± 30%
(Tolerance of voltage fluctuation: ± 10%)

.-----,-----.----SHARP-.-------~

39

SM550/SM551/SM552

4-Bit Microcomputer (Controller)

•

(VDD=2.7 to 5.5V, Ta=-20 to +70"C)

Electrical Characteristics
Parameter

Input voltage

Input current

Output current

Symbol
VIHl
VILl
V IH2
VIL2
lIN
IOHl
lOLl
IOH2
IOL2
IOH3
IOL3
lop

Conditions

MIN.
0.7VOD
0
Voo-0.5
0
2
VIH=OV
. I Voo=5;OV± 10% 20
VOH =V DO -0.5V
50
250
VOL =0.5V
100
VOH=V oo-0.5V
VoL =0.5V
500
100
VOH =V OD -0.5V I V oo =5.0V±10%
400
0.5
VOL =0.5V
I Voo =5.0V±10% 1.6
f=0.5MHz, Voo=3.0V+ 10%
f=lMHz, VDD =5.0V±10%

.Current consumption
1ST

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note .7:
Note 8:
Note 9:

Standby current

I Voo=3.0V±10%
I Voo=5.0V±10%

TYP.

MAX.
Voo
0.3Voo
Voo
0.5
200
200

Unit
V
V
V
V

Note

pA

1,9

pA
pA
pA
pA

1
2, 9

3
4

pA
5
rnA
0.3
1
1
12
50

1.2
4
5
40
200

rnA

pA

6

~
8

Applied to pins PO O-P0 3 , Pl o-PI 3 • P4 o -P4 3 • P5 0 -P5 3 • P6 o-P6 3 , P8 o-P8 3 (during input mode),
P7 o-P7 3 • RESET.
Applied to pins CK" OSC lN, TEST.
Applied to pin CK 2 •
Applied to pin 1>.
Applied to pins PO O-P0 3 • Pl o-PI 3 • P4 o-P4 3 , P5 0 -P5 3 , P6 o-P6 3 , P8 o-P8 3 (during output mode), P2 o-P2 3 • P3 0 -P3 3 •
No-load condition.
No-load condition when crystal oscillation circuit is not operating. Connect OSC 1N pin to GND.
No-load condition when crystal oscillation circuit is operating.
Applied to pins lNTA, lNTB .

.....-..-------,-SHARP,-----.-r---.-.~

40

4-Bit Microcomputer (Controller)

•

SM550/SM551/SM552

AC Characteristics

(Voo=2.7to S.5V. Ta=-20 to +70·C)

Parameter
Reference clock
oscillator frequency
(CR oscillator)
Reference clock input
frequency (CK tl
CK 1 input rise time
CK 1 input fall time

Symbol

CK 1 input HIGH width

tKH

CK 1 input LOW width

tKL

Crystal oscillator frequency
OSC OUT input cycle time
OSC OUT iuput rise time
OSC OUT input fall time
OSC OUT input HIGH width
OSC OUT input LOW width
INT A HIGH width
INT A LOW width
INTB HIGH width
INTB LOW width
SCK cycle time
SCK HIGH width
SCK LOW width
SCK rise time
SCK fall time
RESET pulse LOW width

fosc
tfY
tlR
tfF
tfH
tIL
tAH
tAL
tBH
tBL

Note 1:
Note 2:
Note 3:

fCR

fK

Conditions
Voo=5V± 10%
Voo=3V± 10%
R=SOkO ±5%
V oo =S.OV±10%

MIN.
1.7
O.S
O.S
0.25
0.25

TYP.
2.0
0.75
0.7S

tKR
tKF
V oo =S.OV±10%
V oo =S.OV±10%

tSY
tSH
tSL
tSR
tSF
t RST

MAX.
2.3
1.0
1.0
2.3
1.0
100
100

0.1
0.4
0.1
0.4

Note
1
2

MHz
ns
ns
fls
fls

32.768

kHz

2
SOO

sao
1
1
2
2
2
2
1
112
112

tCYC
ns
ns

3

tcYC
tCYC

3
3
3
3
3
3
3
3
3

tcYC
tCYC
tCYC

sao
SOO
300

Unit
MHz
MHz
MHz

tcYC
tCYC
tCYC
tcyC
ns
ns
ns

SM550: R=17kO ±5%. SM5511SM552: R= lOkO ±5%
SM550: R=50kO ±5%. SM5511SM552: lR=33kO ± 5%
Cycle time at one fouth of a reference clock frequency.

41

SM550/SM551/SM552

4-Bit Microcomputer (Controller)

•

Timing Diagram

CK input

OSC input

INTA }_
INTB mput

O.7VDD

,..----VDD

SCK input

RESET input

.--------'--.SHARP'.---.----..-.----

42

4-Bit Microcomputer (Controller)

•

SM550/SM551JSM552

Hardware Configuration

(1) Program memory (ROM)
The on-chip ROM of the SM550/SM5511
SM552 has a configuration of 16/32/64 pagesX
64 steps X 8 bits respectively, and stores programs
and table data.
The program counter of the SM550/SM551/
SM552 consists of a 4-bit/5-bit/6-bit page
address counter Pu and a 6-bit binary counter PL
used to specify the steps within a page.
Fig. 1 shows the locations allocated in the
on-chip ROM.
(2) Data memory (RAM)
Data memory of the SM550/SM551/SM552 has
80-word/ 128-word/ 160-word X 4 bit configuration respectively.
Fig. 2 shows the RAM configuration.

(3) General-purpose registers (H, L, 0, E)
Registers Hand L are 4-bit general-purpose
registers. They can transfer and compare data with
the Ace on 4-bit basis.
Registers D and E are 4-bit registers and can
transfer data with the Hand L registers on an

I~
~Ul-PUg

0

1

2

(4) Clock divider (DIV)
The device contains a crystal oscillator and a
15-stage divider. A real-time clock can be provided by connecting an external crystal oscillator
between the oscillator pins.
The on-chip divider is reset by an ACL operation or an IDlV instruction. The low-order 8 bits
of the divider can be loaded into the B/ A register
pair by the LDDlV instruction.
When an external 32.768kHz crystal oscillator
is used, the final state signal is set at a frequency
of 1Hz.

(5) Timer/event counter (Te)
The timer/event counter consists of an 8-bit
count register (TC) and an 8-bit modulo register
(TM).

3

0

I~ 0 1 2 3 4 5 6 7 8 9 A,B C D E F

1

4

1
2
3
4

5

5

2
3

6

6

7

7

I

8-bit basis.
The Hand L as well as the D and E registers can
be combined into 8-bit register pairs, and can be
used as pointers to data memory locations.
The L register can be incremented or decremented and is used to access I/O ports and
mode registers.

8
9

8
9

0

A

A
B

B

C
D

C

E
F

D
E
F

<-SM55II-i

I---SM551

---J

1+~
__
SM_55~~---J

~

SM552

Fig. 1

I

~~-------SM552--~-----I'
U: Upper

L: Lower

Fig. 2

RAM configuration

ROM configuration

- - - - - - - - - - S H A R P " - - - - - - - ......... '.-....43

.SM550/SM551/SM552

4-Bit Microcomputer (Controller)

T~ble

Interrupt reque~t
INTT
INTA
INTS
INTB
INTV

Timer / event counter interrupt
External signal INT A interrupt
Serial I/O interrupt
External signal,INTB and
frame frequency interrupts
Divider overflow interrupt

The count register is an 8-bit incremental binary counter. !tis incremented by one at the falling
edge of its count pulse (CP) input. If the count register overflows, the timer interrupt request flag
1FT is set, and the contents of the modulo register
(TM) are loaded into the count register. The contents of the count register can be loaded into the
Bf A register pair by the LDTC instruction.
(6) Serial Interface (SIO)
The serial interface consists of an 8-bit shift
register (SB) and a 3-bit counter, which is used to
input and output the serial data.
In serial shift operations, the highest bit data of
the shift register (SB) is output from the SO pin at
the falling edge of the serial clock, and the data input from the SI pin is loaded into the lowest bit of
the shift register.
When the internal clock is used, the serial operation stops with 8 clocks of serial shift operations
which are output from the SCK pin.
Interrupts
The interrupts can be selected within three
kinds of internal interrupts and two kinds of external interrupts as shown in Table 1.
(7)

lID ports and mode registers (RD. RE.
RF)
The device has I/O ports and three mode registers (RED, RE, RF). Data can be transferred between these ports and registers under instruction
control or L register control.
• Ports PO, PI, P4, P5, P8 and P9* can be switched between input and output modes,4 bits at a
time.
· Ports P2, P3, PA * and PB* are 4-bit parallel
output ports.
'. Port P7 is a 4-bit parallel input port.
• Each bit of portP2 can be indepen'dently placed
in input or output mode by setting the corresponding bit of mode register RF.
'
(8)

44

1 Interrupt request
Priority

Int.lExt.
Int.
Ext.
Int.
Ext.

1
2
3
4

,

Int.

5

Interrupt routine
start address
Page 1, Address 0
Address ,2
Address 4
Address 6
Address 8

• Ports (PO, PI),' (P2, P3), (P8, P9) *, and (PA,
PB) * can be paired for use in data transfer on a
byte-by-byte basis. However, port pairs (P2,
P3) and (PA, PB)* are usable only for output.
· The mode registers RD, RE and RF are treated in
much the same way as output ports.
• Each bit of port P2 can be set to the 110 modes
(SI, SO and SCK) of a serial interface under program control.
• Pins P50 and P5t can output the OD and RfW
signals respectively when an external memory is
accessed. In those cases, these pins should be
kept High in output mod'e.

*Applicable to the SM551. and SM552.

Every input port has pull-up resistors.
Pull-up resistors can be omitted and output
ports can be designed to consist of open-;-drain
transistors with a mask option.
(9) Standby mode
Executing the CEND instruction places the device in standby mode. To reduce power consumption, the system clock is inactivated.
Standby mode may be cleared with the Interrupt
request or the RESET signal.
Reset function (ACL)
Applying a Low level signal to the RESET pin
resets the internal logic of the device, and starts
execution of the program at address 0, page O.
,
. Once the device is reset, all 110 ports are placed
in input mode to disable all interrupts. The mode
registers RD, RE and RF are all cleared. The output ports P2, P3, PA * andPB* are all cleared to
output "0". The device is also reset when it is powered up. The program starts (master clock period
X 214) clock periods after the reset signal is ineffected.
'
(10)

* Applicable to the SM5,5J and SM552.

I;
,
"

4-Bit Microcomputer (Controller)

SM550/SM551/SM552

(11) Master clock oscillator circuit
The master clock oscillator requires an external
resistor across pins CK 1 and CK z. Instead of using
on-chip oscillator, an external clock may be applied to pin CK!. In this case, pin CK z should be
left open.
The system clock '" has a frequency of one
fourth that of the clock applied to pin CK 1 . When
applying an external clock to pin OSC OUT , the external clock frequency should be set at one eighth
of the master clock frequency.

External clOCk-R
open-tj

(a) CR oscillator

(b)

External clock

Fig. 3

r

OSC IN
CG

OSCOUT
rystal

t
DI---1 CD

I

Open- OSCIN
External clock ...... OSCOUT

Cc =15pF,C D =22pF

(a)

(b)

Crystal oscillator

External clock

Fig. 4

-.-..-.----~SHARP-.....-,-----~-.-

45

4-Bit Microcomputer (Controller)

•

SM550/SM551/SM552

Instruction Set
(1)

RAM address instructions

Operation
Mnemonic Machine code
L+-A
STL
69
H+-A
STH
68
H-D
EXHD
3F
L-E
LIHL xy 3D
H+-x(I 7 -I.), L+-y(I 3-I o)
(2-byte) OO-FF

(2)

ROM address instructions

Operation
Machine code
80-BF
P L+-x(Is - 10 )
EO-EF
P u +-x(I g -I 6 )
OO-FF
P L+-y(Is-Io)
(SI:'-l), (SP-2), (SP-3)+-PC
SP+-SP-4
CO-DF
P u +-0(SM550),
TRS x
Pu+-1 OH(SM5 51 ISM5 5 2)
P L+-x(I.I3I2I,I oO)
(SP-1), (SP-2), (SP-3)+-PC
CALL xy FO-FF
SP+-SP-4, P u +-x(I g -I 6 )
(2-byte) OO-FF
P L+-x(l514hIzI,Io)
P U5 - P uz +-x(l3- Io)
7F
JBA x
PUb P uo , P L5 , P L4 +-B,
(2-byte) 30-3F
P L3 -PLQ+-A
P u , P L+-(SP+ 1), (SP+2),
RTN
61
(SP+3), SP+-SP+4
P u , P L+-(SP+ 1), (SP+2),
RTNS
62
(SP+3), SP+-SP+4
P u , P L+-(SP+ 1), (SP+2)
(SP + 3), PSW +-(SP),
RTNI
63
SP+-SP+4,IME+-1

1:1nemonic
TR x
TL xy
(2-byte)

46

(3)

Data transfer instructions

Mnemonic
EX pr
LOX adr
(2-byte)
STX adr
(2-byte)
EXX adr
(2-byte)
LAX x
LIBA xy
(2-byte)

Machine code
5C-5F
7D
OO-FF
7E
OO-FF
7C
OO-FF
10-IF
3C
OO-FF

LBAT

60

LOL
LO pr
ST pr
EXH
EXL
EXB
STB
LOB
LOH

65
54-57
58-5B
6C
60
6E
6A
66
64

PSHBA

28

PSHHL

29

POPBA

38

POPHL

39

STSB
STSP
STTC
STTM
LOSB
LOSP
LOTC
LODIV

70
71

72
73
74
75
76
77

Operation
A-(pr)
A+-(adr)
(adr)+-A
A-(adr)
A+-x(I 3-I o)
B+-x(I 7 - I.) .
A+-y(I3- Io)
B+-ROM(P u5 -P uz , B, A)H
A+-ROM(P U5 -P UZ , B, AlL
A+-L
A+-(pr)
(pr)+-A
A+-H
A+-L
A+-B
B+-A
A+-B
A+-H
(SP-1) +-B, (SP+-2)+-A,
SP+-SP-2
(SP-1) +-B, (SP+-2)+-A,
SP+-SP-2
B+-(SP + 1), A +-(SP),
SP+-SP+2
H+-(SP+ 1), L+-(SP),
SP+-SP+2
SB H+-B, SB L+-A
SPH+-B, SP L+-A
TC+-TM
TMH+-B, TML+-A
B-SB H, A +-SB L
B+-SP H, A+-SP L
B+-TC H, A +-TC L
B+-OIV H, A+-DIVL

4-Bit Microcomputer (Controller)

(4)

ADX x

OO-OF

ADD

36

ADDC

37

OR
AND
EaR
AN DB
ORB
EORB
COMA
ROTR
ROTL
INCB
DECB
INCL
DECL
DECM
adr
INCM
adr

31
32
33
22
21
23
6F
25
35
52
53
50
51
79
OO-FF
78
OO-FF

(5)

Operation
A+-A +x(I 3-I o),
Skip if Cy= 1
A+-A+(HL)
A+-A+(HL)+C, C+-Cy
Skip if Cy=1
A+-A+(HL)
A+-A - (HL)
A+-AEB(HL)
A+-A-B
A+-A+B
A+-AEBB
A+-A
C--+ A3--+ A 2--+ AI--+ Ao--+C
C+-A3+-A2+-AI +-Ao+-C
Skip if B=F, B+-B+ 1
Skip if B=O, B+-B-l
Skip if L=F, L+-L+l
Skip if L=O, L+-L-l
Skip if (adr)=O,
(adr)+-(adr) -1
Skip if (adr)=F,
(adr)+-(adr) + 1

Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip

if
if
if
if
if
if
if
if
if
if
if
if

Operation
A=(HL)
A=H
A=L
A=B
C=O
(HL)x = 1
Ax= 1
IFT=I, IFT+-O
IFA=I, IFA+-O
IFS= 1, IFS+-O
IFB= 1, IFB+-O
IFV = 1, IFV +-0

liD instructions

Mnemonic Machine code
IN
67
6B
OUT
INA x
7F
(2-byte) AO-A9
OUTA x 7F
(2-byte) BO-BF
7F
INBA x
80; 82
OUTBA x 7F
(2-byte) 90-93
SP xy
7A
(2-byte) 00-F6
RP xy
7B
00-F6
(2~byte)
READ
7F
(2-byte) 60
WRIT
7F
(2-byte) 70
READB 7F
(2-byte) 61
WRITB 7F
(2-byte) 71

(8)

Test instructions

Mnemonic Machine code
TAM
30
24
TAH
TAL
34
TAB
20
TC
2A
48-4B
TM x
4C-4F
TA x
TSTT
2B
TSTA
2C
2D
TSTS
TSTB
2E
TSTV
2F

(6)

(7)

Arithmetic instructions

Mnemonic Machine code

SM550/SM551/SM552

A+-P(x)
P(x), R(x)+-A
B+-P(x+ 1)
A-P(x)
P(x+l)-B
P(x)+-A
P(y)+-P(y) + x
P(y)+-P(y) x
A-PO with OlD
PO-A with RIW
B-Pl
A-PO with OlD
PI-B
PO-A with RIW

Special instructions

Mnemonic Machine .code
SIO
3E
IDIV
7F
(2-byte) 10
SKIP
00
7F
CEND
(2-byte) 00
Note:

Operation
A+-P(L)
P(L), R(L)+-A

Operation
Speria\ 110 start
DIV+-O
No operation
System clock stop

The machine code consists of 8 bits including I7 • I6 • Is,
I 4 , I 3 ,I 2• II and Io,

Bit manipulation instructions

Mnemonic Machine code
40-43
SM x
44-47
RM x
26
RC
27
SC
RIME
3A
3B
SIME
7F
DIx
(2-byte) CO-DF
EI x
7F
(2 byte) EO-FF

Operation
(HL)x+-l
(HL)x+-O
C+-O
C+-l
IME+-O
IME+-l
IEF+-IEF-x
IEF+-IEF+x

----------SHARP.--..-------47

4-Bit Microcomputer (Controller)

•

SM550/SM551/SM552

System Configuration Example (Mechanism controller)
+5V

u
Z

:>""

PA 3
\
Pulse input {
P4 0

\
P4 3
POo

)

Control signals

PAo
P9 3

\

Control signals'

P9 0
P8 3

\
P8 0

P0 3

Pl o

*Ports P8 o-P8

48

3

P9 0 -P9 3 • PA o-PA 3 apply to the SM551 and SM552.

} Input signals

4-Bit Microcomputer (Controller with AID Converter)

SM578/SM579

SM578/SM579
4-Bit Microcomputer .(Controller with AID Converter)
•

Description

•

The SM578/SM579 is a CMOS 4-bit microcomputer which integrates a 4-bit parallel processing function, interrupts, an A/D converter, a comparator, a counter/timer circuit, and a tone output
function in a single chip.
An A/D conversion can be executed by one instruction with simple software, and provides a high
speed processing. This feature enables to accept
analog signals from sensors.
Provided with unique features of 52 I/O ports, a
couple of programmable counter/timers, and many
instruction sets, this microcomputer is applicable
to many applications such as home appliances,
office equipment, simple measuring instruments,
and battery backup systems.

Pin Connections

.------------------------------------,
60QFP

Q

NNNNNNNt5NNNJt-S~J
5

4

4 4

64QFP

2930313

NNNN

Top View

~,~-----'------SHARP

---------'-.-...-.-

49

4-Bit Microcomputer (Controller with AID Converter)

•

Features
L CMOS process
2. ROM capacity
SM578: 4,064 X 9 bits
SM579: 6,096 X 9 bits
3. RAM capacity
SM578: 192 X 4 bits
SM579: 256X4 bits
4. Instruction set
SM578: 93
SM579: 94
5. Subroutine nesting: 6 levels
6. Instruction cycle: 2 f.1. s (MIN.)
7. Interrupts
External interrupts: 2
Internal interrupts: 3

•

SM578/SM579

8, Input/Output ports
I/O ports: 41
Input ports: 9
Output ports: 2
9. 8-bit serial I/O
10. Counter/timer: 2 sets
1 L A/D converter:
8 bits (20 channels MAX.)
12. Standby function:
2-stage system clocks
13 On -chip crystal! system clock
Oscillator circuits
14. Supply voltage: 2.7 to 5.5V
15. 60-pin QFP (QFP60-P-1414)*
64-pin QFP (QFP64-P-1420)
64-pin SDIP (SDIP64-P-750)

* Usable when ser,ial 110 ports are not used.

Block Diagram

..s
..s
U
U

E-<
~

'z

r3

rJl

Symbol description
ALU
: Arithmetic logic unit
X
: X register
B
: RAM address register
C
: Carry F/F
PC
: Program counter
SP
: Stack pointer
CG
: System clock generator
Note:

f-o

'"
0

U

rJl

0

0
: Multiplexer
AID
: AID converter and Comparator unit
: Accumulator
Ace
: Stack register
SR
RO,Rl,R2,R3 : Latch
: Divider
DIV

MPX;

Pin numbers apply to a 64 pin QFP.

'....-~---~----~----SHARP -------------~

50

4-Bit Microcomputer (Controller with AID Converter)

•

Clock Generator Circuit (preliminary constant)
Signal
PO-P 3 , QO-Q3
RO o-R0 3
Rl o-R1 3
R2 0 -R2 3
R3 0 -R3 3

2 0 -2 15

*
•

SM578/SM579

KC o-KC 3
KH,KL
KI
OSCIN/KT
OSCOUT
F
fOUT
CL I
CL 2
ACL
VRH , VRL
Voo
GND
T
SIN
SOUT
SCLOCK

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I

0
0

I

I
I

0
I/O

Pin name
Input/Output ports (nibble unit)
Input/Output ports (nibble unit)
Input/Output ports (nibble unit)
Input/Output ports (nibble unit)
Input/Output ports (nibble unit)
Input/Output ports (Bit unit)
Input ports or analog input ports
Input ports
Interrupt input port or input port
Timer clock input port or input port
Timer clock oscillator
Sound output port or output port
System synchronous signal output port
Clock signal input port
Clock signal oscillator
Auto clear input port
A/D conversion
Power supply
Ground
Test input port
Serial I/O data input port *
Serial I/O data output port *
Serial I/O clock I/O port *

Applicable only to 64-pin QFP and 64-pin DIP.

Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Output current *
Operating temperature
Storage temperature

Symbol
Voo
VIN
VOUT
lOUT
Topr
Tstg

Rating
-0.3 to +7.5
-0.3 to VDD +0.3
-0.3 to Voo +0.3
30
-10 to +70
-55to+150

Unit
V
V
V
rnA

·C
"C

* SO,urce current. from output pin or sum of sink current.
•

Recommended Operating Conditions
Parameter
Supply voltage

Symbol
Voo

System oscillator frequency

fCL

System clock frequency

fs

Timer clock frequency

fosc

Rating
2.7 to 5.5
4 to 0.2 (Voo=5V)
2 to 0.2 (Voo=3V)
500 to 50 (Voo=5V)
250 to 50 (Voo=3V)
32.768 (TYP.)

Unit
V
MHz
kHz
kHz

51

SM578/SM579

4-BitMiorooomputer (Controller with AID Converter)

•

(Voo=2.7 to (j.(jV, Ta=-lO to +70"(;)

Eleotrioal9haraoteristios'
Parameter

Input voltage

Symbol
VIH1
VIL1 VIH2
V1L2
VIH3
VIL3
IIHI
IIH2

Input current
IIH3
IlL
IOHI

iOLl
IOL2
Output current

IOH3
IOL3
IOH4
IOL4

ACL input pulse width

t ACL
IA

Current consumption
1ST

Note 1:
Note
Note
Note
Note
Note
Note

2:
3:
4:
5:
6:
7:

Note
Note
Note
Note
Note

8:
9:
10:
11:
12:

52

Conditions

MIN.
TYP.
0.7Voo
0
Voo -0.5,
0
VDo -O.4
0
VDo =5.0V±10%
80
300
VIH = VDD
VDD =3.0V±10%
15
90
VDD =5.0V±10%
10
25
VIH=VOO
VDo =3.0V±10%
1
8
VDo =5.0V±10%
100
400
VIH=VOO
10
80
VOD~3.0V±10%
10
100
VoD =5.0V±10%
IIL=OV
15
VoD =3.0V±10%
2
Voo =5.0V±10%
1.0
VoH =V oo -0.5V
VoD =3.0V±10%
0.4
10
Voo=5.0V±1O%
VoL =0.5V
4
VDo =5.0V±10% 1.0
VOL ='o.5V
0.4
VOH =V OD -0.5V
100
100
VOL =0.5V
VoD =5.0V±10%
0.6
VOH =VOD -0.5V
0.3
Voo =5.0V±10%
1.0
VoL =0.5V
0.4
Voo =5.0V±10%
1
Voo=3.0V±10%
fs=500kHz
Voo =5.0V±10%
1.8
Voo =5.0V±10%
0.8
fs =100kHz
Voo =3.0V±10%
0.5
1
Voo=5.0V±1O%
Voo =3.0V±10%
0.5
Off mode
Voo =5.0V±10%
Voo =3.0V±10%
Voo =5.0V±10%
Hold mode
Voo =3.0V±10%,
Voo=3.0V±10%

Applied to pins KH, KL, KI, P3- PO, Q3-QO, R0 3-RO o,
RI 3-Rl 0, R2 3-R2 0, R3 3-R3 0, KC 3-KC o
Applied to pins Z'5-Zo,CL" OSC'N/KT, ACL
Applied to pin SIN
Applied to pin Sol"'.
Applied to pins Q3-QO;Z'5-Z0, R03-ROo, R1 3 -Rl 0
Applied to pill ACL
Applied to pins Q3-QO·, Z'5-Z0 *, R0 3-RO o, R1 3-Rl o
(*If CMOS buffer is specified for mask option, note 8 ap"
plied to these pins.)
Applied to pins P3-PO
Applied to pin CL z
Applide to pins Sol",.. SoUT, F, fOUT
No-load condition
When the OSCIN/KT pin is connected to GND and in
no-load condition. (The reference clock has a frequency
of 4 times of fs.)

MAX.
Voo
0.3VOD
VDD
.0.5
VDD
0.4
800
300
120
50
800
300
200
60

Unit

Note

V

1

V

2

V

3,4

pA

5

pA

6

pA

3

pA

4

mA

7, 8

pA

7

mA

8

pA

9

rnA

1.0

ps

16

mA

11

pA

12

pA

13

pA

14

' [!A

15

Note 13: When the timer clock crystal oscillation circuit and timer
1 are operating and in no-ioad condition. (The refere'lce
clock has a frequency of 4 times of fs.)
Note 14: When the OSC'N/KT pin is connected to GND and in
no-load condition, fs=100kHz (The reference clock has
a frequensy of 4 times of fs.)
Note 15: When the OSC'N/KT- pin is connected to ,GND and in
no-load condition, fs=500kHz (The reference clock has
a frequency of 4 times of fs.) ,
Note 16: tACL is the ACL input pulse width required to cause ACL _
to operate when VDO has" completely risen.

SM578/SM579

4-Bit Microcomputer (Controller with AID Converter)

•

Electrical Characteristics for AID Conversion Block
(fs=100kHz, Vnn =5V, VRH =4.608V, Ta=25°C)
Parameter
Non-linearity error
Diffrential non-linerarity error
Zero error
Full-scale error

MIN.

±Yz

MAX.
±1

±1

±lYz

±Yz

±1
± 1 Yz
±1
±1 Yz
±1
±1
300

±Yz
±1

±Yz
±Yz
100
±1
±1 Yz

GND
Open

Total error

TYP.

±1

-

VRH pin voltage

Note:

VRL pin
GND
Open
GND
Open
GND
Open
GND
Open

±lYz
±2

Unit

LSB
LSB
LSB
LSB
pA

LSB

No quantizing tolerance (± Yz LSB) should be specified.

(fs=100kHz, Vnn =3V, VRH =3V, Ta=25"C)
Parameter
Non-linearity error
Diffrential non-linerarity error
Zero error
Full-scale error
VRH pin voltage
Total error
Note:

VRL pin
GND
Open
GND
Open
GND
Open
GND
Open

MIN.

GND
Open

TYP.

±lYz
±2
±1
± 1 Yz

MAX.
±2
±2 Yz

±lYz

±Yz

±2
±1

±1

±lYz

±Yz
±Yz

±1
±1
200
±2
±2 Yz

60
±1 Yz
±2

Unit

LSB
LSB
LSB
LSB
pA

LSB

No quantizing tolerance (± Yz LSB) should be specified.

53

4-BitMicrocomputer (Controller with AID Converter)

•

SM578/SM579

Clock Generator Circuit (preliminary constant)
(1)
(a)

100

System clock generator circuit example 1
400kHz clock
Oscillator KBR-400B: KYOSERA
or CSB400P: MURATA
R,=lMO
Rd=3.3kO
CI =220pF
C2 =220pF

=VDD-5.0V ~ V DD-3.0V Ta 25'C
fs = Reference
clock fcd8

"-."

ac
~

...0

10

,

.~

...

"OJ

(b)

CL I

CL.!

Q~
CIJ; J;Ci
(2)

"iii

2MHz clock
Oscillator KBR-2.0MS: KYOSERA
R,=lMO
Rd=lkO
CI =22pF
C2 =68pF

System clock generator circuit "example 2

E

VDD=5.0V .

2

~

V

\0
.

"

I

1000

100
System clock fs (kHz)

(4)

External clock Input circuit
OSCIN/KT

~
(3)

~3.0V

DID I I I

OSCOUT

t

Open

Pulse generator

Timer clock generator example

fosc= 32.768kHz "
Rd=560
Cl =30pF, C2 =16pF
Crystal: 32.768kHz

Note: The resistors, capacitors and crystal oscillators should be located as close to the LSI chip as possible to minimize the influence of stray
capacitance.

54

4-Bit Microcomputer (Controller with AID Converter)

•

SM578/SM579

(Voo=2.7 to 5.5V)

AC Characteristics for External Clock Input Signal
Parameter

Symbol

Input rise time

tR

Input fall time

tF

Conditions

Voo =5V±10%
Clock HIGH pulse

Clock LOW pulse

Note 1:
Note 2:

tH

tL

Voo =5V±10%

MIN.

TYP.

MAX.

100
200
100
200
2.5
2.5

0.125
0.25
4
4

Voo =5V±10%

0.125
0.25

Voo =5V±10%

4
4

Unit
ns
ns
ns
ns

I's
I's

I's
I's

2.5
2.5

I's
I's
I's

I's

Note

1
2
2
2
1
2
1
2

Applied to eLI pin.
Applied to OSKIN/KT pin.

V1L2

External clock timing

55

SM578/SM579

4-Bit Microcomputer (Controller with AID Converter)

•

Pin Functions
(1)

GND, Voo (Power supply inputs)

The V DD pin should be positive (2.7 to 5.5V)
with respect to GND.
The GND pin is the resference power supply for
the LSI.
VRH , VRL·(AlD converter inputs)
The V RL pin is a GND pin for the AID converter.
The V RH pin provides the reference voltage V RH
for the AID converter.
The current consumption and operating accuracy of the AID converter must be changed according
to the case where the V RL pin is used to be left
open or provide GND level.
(2)

(3)

ACL (Reset input)

The ACL pin is used to reset the LSI.
The LSI should be reset with a transition of two
instruction cycles after the rising edge of ACL.
Applying a Low level signal to the ACL pin
starts execution of the program at field 0, page 0,
step 0 after a transition of tACL.
The device is automatically reset when power
on. But it is recommended to apply a capacitor between ACL pin and V DD pin in order to prevent
from external noise which affects the ACL circuit.
(4)

KC o-KC 3 (Analog inputs)

Executing theKCT A instruction transfers the
KC input data to the accumulator Acc through input buffers.
The KC input pin also provides analog input signals given to the AID conversion block.
(5)

KH, KI, OSC1N/KT, KL (Inputs)

The KH and KI input pins are connected to the
noise debounce circuit, and the KL and OSCIN/KT
input pins to input buffers.
The KL, OSCIN/KT, KH and KI should be loaded
into the Ao, AI, A2 and A3 bits of the accumulator
Acc upon execution of KLT A instruction.
The noise debounce circuit does not accept the .
pulse iqput shorter than two instruction cycle
width.
(6)

ZO-Z15 (Input/output)

The 2 0 -2 15 can be controlled with the output
latch F IF to be set or reset by instructions.
When used for the inputs, the 2i should be used
with the outputs to be pulled down, and the input
mode of Zi specified by lower 4 bits of B regi'ster
BL can be tested by instructions.

The 2i pin transfers analog signals into the compator of AID converter.
The Zi pin transfers analog signals into the comparator of AID converter.
(7)

PO-P3 (Input/output)

The P O-P 3 are three-state I/O pins.
Executing the A TP instruction transfers the
accumulator Acc to the output latch F IF which is
loaded into the PO-P 3.
The Po - P 3 can be loaded into the Acc upon execution of the PTA instruction. Then the Po - P 3 remain high impedance.

(8) 0 0 -0 3 (Input/output)
Executing the A TQ instruction transfers the
accumulator Acc to the output latch F IF which is
loaded into the QO-Q3'
While, the QO-Q3 can be loaded into the Acc
upon execution of the QT A instruction. Then, the
QO-Q3 should be used to reset the output latch F IF
with the outputs to be pulled down.
(9)

ROo-R0 3 , R1 o-R1s, R2 0 -R2 3 , R3 0 -R33
(Input/output)

Upon execution of the ATR instruction, the
ROi-R3i outputs the accumulator Ace specified by
the lower 4 bits (BL) of the B register. While, executing the MTR instruction provides the RAM
contents specified by the B register from the
ROi-R3i.
The R3i-ROi are loaded into the Aee by an RTA
instruction. Then, the output port resets the output
latch F IF to be pulled down.
8-bit data transfer can be performed in parallel
among the R [11 i, R [01 i and Aee or X register by
the RT AX or AXTR instruction.
F (Tone output)
The F output pin is used for a tone output as
well as a general-purpose output.
(10)

(11)

tOUT

The fOUT pin outputs the signal in synchronizing
with the system clock fs.
Note:

When the I/O pins Z, Q, R are used for the outputs, the
buffer with a pull down resistor can be replaced by the
CMOS buffer with a mask option.
The output buffer wIth a pullcdown resistor can also be
structured by an open-drain transistor.
However, the R0 3 -RO o, R1 3 -Rl o and R20 can not be replaced by the COMS buffer.

~---------~SHARP''-~-,---------,-''''''''''

56

4-B.it Microcomputer (Controller with AID Converter)

•

SM578/SM579

.Hardware Configuration

(1) Program counter and stack
The program counter (PC) is used to address a
ROM location.
The PC consists of 12 bits (SM579: 13 bits) allocated 3 bits (P u) (SM579: 4 bits) to the field specification· of ROM, 2 bits (PM) to the page specification, and 7 bits (PLl to the step specification. The
PM is a binary counter and the PL is a polynomial
counter for the page specifications.
The SM578 is unable to use the area of the ET 1
(feilds 8 to 11).
The SR consists of 6 stages available for up to 6
levels of subroutine nesting.

~
PM

ET=O (0 to 7 field)
Field
0

Page
0

ACL

Page

Standby
clear

1

Page

Field
1

Field

Field
3

2

ET=l (8 to 11 field)

Field
4

Field
5

Field
7

---

Ii

Interrupt

Field
6

~

b::::::::::::

_TL

COMET
TL .......

Field
9

Field
8

Field
10

~

~

COMET
......TL
COMET

'-l-r:::==

~TLS

RT"N"

SUb~

COMET
TLS- ~ ~RTN

TRC
cover

Field
11

~TRS

V

.......... ~

/

2

Page
3

(2) Prog,am memory (ROM)
The ROM is used to store programs.
The SM578 has a 4096 X 9-bit ROM, and the
SM579 has a 6096X9-bit. The ROM consists of 8
fields (SM579: 12 fields)X4 pages X 127 steps.
When power on with the ACL to be reset, the
program starts exe~ution at field 0, page 0, step 0.
Fig. 1 shows the example of a jump to the ROM
address by a ROM address instruction.
The TR instruction is used to jump within a
page, and the TL instruction is used to jump to any
address. A subroutine jump is executed by the TLS
or TRS instruction.

.-- I---

.......TL/

V

V

SM578
SM579

Fig. 1 ROM configuration
--->

I~
BL

O'

File
E

1

F

0

1

2

-~----

E

F

/
I Ms

~
M21 Ml

Mo

I Word

(The SM578 has a configuration allocated from 0 through B)

Fig. 2

RAM configuration

57

4-Bit Microcomputer (Controller with AID Converter)

However, when the ET value may change due to
a jump or subroutine jump on the SM579, execute
the TL or TLS instruction following the COMET
instruction.
(3) Data memory (RAM) and 8 register
The RAM is used to store data.
The SM578 has a 768-bit RAM organized as 12
X 16 X 4 which consists of 12 files as shown in
Fig. 2. The SM579 has 16 files of RAM organized
as 16 X 16 X 4. A file consists of 16 words X 4 bits.
The RAM address is specified by a B register
which consists of a 4-bit BM for the file specification and a 4-bit BL for the word specification.
(4) Accumulator Ace, X and G registers
The accumulator Ace is a 4-bit general-purpose
register which transfers numerics and data. The
Ace can be decremented and shifted to the left in
combination with the carry flag (C).Furthermore,
the Ace together with the arithmetic and logic unit
(ALU), a carry flag (C) and RAM executes arithmetic operations.
It also transfers data to II a ports.
The X register is a 4-bit register which can be
used for a temporary register. It is incremented by
instructions. It performs, in conjunction with the
Ace, logical sum and logical product.
An 8-bit parallel data of the Ace and X register
can be transferred to R [OJ and R [lj, a G register
or a counter/timer.
On the other hand, each data on ROi and R1i, a G
register or a countere timer can also be transferred
to the Ace and X register with an 8-bit parallel
data.
The G register is an 8-bit register which is used
for A/D conversion or comparison of analog signals.
(5)

Arithmetic and logic unit (ALU), carry flag
(C)
The arithmetic and logic unit (ALU) performs
binary addition in conjunction with a .RAM, a carry
flag C and an accumulator Ace.
The carry flag C latches the data incremented by
the ADC or ADCS instruction.
(6) S8 register
The SB register is an 8-bit register used for a
save register.

SM578/SM579

(7)

P, Q, R [3J-R [OJ, Z (Output latch registers)
Registers p. Q, RO, R2, R3, Z connect with the
output latch F /F.
The accumulator Ace can be transferred to reg.isters P, Q, R [3j-R [OJ, and an 8-bit data of the
Ace and X register can be transferred, at the same
time. to the output latch registers R [OJ and R [lj.
System clock generator circuit
The system clock generator circuit generates a
system clock of a base frequency input from the
CLI pin divided by 4 or 8.
The system clock speed can be controlled by a
program. If it is not required for high speed operation, the system clock can be switched to the low
speed in order to save the power consumption.
This function is also applicable to the case where
the power supply is replaced by a battery backup
power.
The system clock when reset is equivalent to the
base frequency divided by 8.
The system clock fs is used to determine the in·
struction execution cycle. and the system clock cycle should be identical to the instruction execution
cycle. However, the instruction execution cycle of a
two word instruction should be two times as long
as a one-word instruction.
(8)

(9) Counter/timer
A timer 1 and timer 2 are 8-bit counter/timers.
The data incremented by a count up is latched into
the flags TF1 and TF2 to be used for an interrupt
request. Executing the TTF 1 and TTF2 flags
checks the flags TF1 and TF2.
. Timer 1: An 8-bit data of the Ace and X register
can be transferred to the timer l. To the contrary, the timer 1 can be read out from the Ace
and X register.
• Timer 2: The timer 2 contains a modulo register
(MR register). The contents of the modulo register (TM) are loaded into the timer 2 each time
the register is incremented by one.
An 8-blt data can be loaded into the MR register
by instructions. and executing the next instruction cycle transfers the data to the timer 2 which
can be read out from the Ace and X register.
The count up pulses of a counter/timer include
(1/2)9fs• (1/2)3fs. (1/2)6f T and fT. under conditions
of a system clock fs and KT input pulse h. which
can be selected by a program.
A carry output of one counter can be used for a
count up pulse of the other counter. and it can be
counted up by a TCTRL instruction .

.---------SHARP.----...---.-.--..58

4-Bit Microcomputer (Controller with AID Converter)

SM578/SM579

Mask flag

E3
Stack
register

Interrupt request flag'
Timer 1

TFI r----------+---+--~----~_/

Program
counter

1.

INT signal
Timer 2

TF2

KI input

IF

r-------------~--_r--~

E

Analog input
comparator

Interrupt enable flag

AF

Fig. 3

Interrupt block

Table 1 Interrupt jump address
Interrupt request flag
Timer 1 carry (TFl)
Timer 2 carry (TF2)
KI input (IF)
Analog input comparator (AF)

(10) Interrupt
A KI input, the timer 1 and timer 2 carry and an
analog input are available for the interrupt request, and the interrupt request flags include the
IF, TF1, TF2 and AF flags.
The interrupt block consists of the mask flags
(E3, E z, E t and Eo), E flag and interrupt processing
circuits.
(See Fig. 3)
Table 1 shows the jump address caused by an
interrupt request.
(11) AID converter
The AID conversion block consists of an 8-bit
DI A converter, a comparator, an AM flag and AF
flag.
The KC and Z pins input the analog signals.
Executing the COMP instruction allows the AID
conversion and the largelsmall comparison automatically. (See Fig. 4.)
The result of AID conversion is stored in the G
register with the interval of 16 instruction cycles
after the COMP instruction is executed.
The result of the largel small comparison is
stored in the AF flag with the interval of 3 instruction cycles.

Jump destination address
Field
Page
Step (PL)
0(00)
2
0
2 (60)
2
0
4 (78)
2
0
6 (7E)
2
0

Priority

1
2
3
4

The G register is an 8-bit register which can be
transferred to the Acc and X register with the
GT AX instruction.
The KC o pin can also be used for an external interrupt.
The DI A converter generates the voltage VREF
according to the contents of the G register.
Assuming that the "n" is placed in the G register
as a result of AID conversion, the analog input voltage may be regarded as a below expression.
256-n
256 V RH (n=O to 255)

*V

RH

is a reference voltage supply from the V RH pin.

When even more strict accuracy is required in
the AID conversion block, an external GND level
should be applied to the VRL pin.
The AID conversion is executed by the comparison among a G register,a DI A converter and a
comparator in order.
The largelsmall comparison is executed by the
comparator output VREF according to a G register
value and the analog signal of the KC o. The result
of comparison is stored in the AF flag.

-.---------SHARP-~-------

59

SM578/SM579

4-Bit Microcomputer (Controller with AID Converter)

V REF

Anarog signal

Fig. 4

(12) Tone output block
The F pin outputs the frequency obtained from a
count-up pulse generator circuit.
The pulse frequency can be selected among (1/
2)5fs, (1/2)6fs, (1/2)2fT and (1I2)3fr by programs.

*The fT is a timer clock frequency input from the OSC1N/KT pin,
and the fs is a system clock frequency.

(13) Standby mode
To reduce power consumption, the device is
placed in standby mode, and the program execution
is inactivated.
The following two types of standby mode can be
selected.
• Off mode
In the off mode, the system clock
generator circuits except for a counter/timer and a
count-up pulse generator circuit are inactivated.
• Hold mode
In the hold mode, the systems
except for a system clock generator circuit, a counter/timer and a count-up pulse generator circuit
are inactivated.
While in standby mode, if a KH input or an interrupt request from an unmasked KI, timer 1 or
timer 2, the device exits standby mode and starts
program execution.

60

AID converter block

(14) Reset function (ACL)
The device is reset with the interval of two instruction cycles from the rising edge of the ACL
pin.
Immediately after the reset is cleared, the device
starts execution of the program at the program
counter O.
In case the noise may harm the ACL operation,
apply a capacitor between ACL pin and VDD pin.
(15) Serial 1/0
The serial I/O consists of an 8-bit shift register,
a 3~bit counter and a 6-bit mode flag, which' have
the following features.
• Selectable either an 8-bit or a 4-bit transfer
system
· Interrupt request available at the end of transfer
• Selectable transfer clock among a system clock, a
timer 2, output or an external clock.
• Connectable to multiple chips.
• Usable in standby mode.
• An 8-bit shift register replaceable by the R/W
register when the serial I/O is not used.

4-Bit Microcomputer (Controller with AID Converter)

•

SM578/SM579

Instruction Set
(1)

ROM address instructions
Mnemonic
TR x
TL x
MTPL
TRS x
JUMP
TLS x
RTN
RTNS
RTNI
COMET

(2)

Machine code
Is 17 16 15 14 13 I z 1, 10
IOO-I7F
OFO-OF7
OOO-IFF
08A
180-IFF
OOO-IFF
OF8-0FF
OOO-IFF
OCO
OCI
OC2
08B

Operation
Jump (within a page) P L+-1 6-1 0
Jump
Pu+-Ill-I g • P M+-I s -1 7• P L-1 6-l o
Jump (within a page) (PL+-Az-A o M3-M o)
CALL (Indirect address)
Pu-I, PM+-Is. 17• P L+-1 6-l o• if DI=I
Call to subroutine
Pu-Ill-I g • P M+-I s -1 7, P L+-1 6-1 0
Return
Return and skip
Return from interrupt
ET+-ET

Data transfer instructions

LBMX x
LBLX x
STXlx

Machine code
Is 17 16 15 14 13 l z I, 10
040-04F
087
OOO-OFF
OEO-OEF
020-02F
050-05F

EXClx

070-077

EXCD x

078-07F

EXC x
LDA x
STR
EX AX
ATX
GTAX

068-06F
060-067
09E
OA6
OAE
OBD
08D
OBD
OB3
OBI
OB2
OBA
084
085
08D
OC8-0CF
OB4

Mnemonic
LAX x
WLAX x

AXTG
XBLA
BLTA
XBMA
BMTA
XBSB
BTSB
SAG
SGL x
ATIM

Operation
Acc+-1 3-l o• Skip if last instruction is LAX
X+-1 7-1 4• Acc+-1 3 -l o
BM+-1 3 -l o
BL +-1 3-1 0
M+-1 3 -l o• BL +-BL + 1. Skip if CY= 1
M-Acc, BM+-BMEBlz-lo
BL+-BL +1, Skip if CY=I
M-Acc, BM+-BMEBlz-lo
BL+-BL +F H , Skip if CY=I
M-Acc, BM+-BMEBlz-l o
Acc-M. BM+-BMEBlz-lo
M+-Acc
Acc-X
X-Acc
X-G 7 -G 4 • Acc+-G 3 -G O
G7-G 4+-X. G3 -G o+-Acc
BL-Acc
Acc-B L
BM-Acc
Acc+-BM
B-SB
SB+-B
BM+-O, only next step
BM=lz-l o, BL=FH • only next step
Ei+-Ai (i=3 to 0)

61

4-Bit Microcomputer (Controller with AID Converter)

(3)

Arithmetic instructions
Mnemonic
ADX x
ADA
ADD
ADS
ADC
ADCS
ADBL
AND
OR
COMA
ROT
DECA
INCX
INBL
DEBL
INBM
DEBM

(4)

TAX x
TBA x
TM x
TAM
TXM
TBLX x
TC
TS
TIF

Machine code
Is 17 16 Is 14 13 12 I I 10
010-01F
OD4-0D7
ODO-OD3
096
OB6
030-03F
OB8
OB9
OC7

THAF

OC6

TTF1
TTF2
TQZ
TZ

OC5
OC4
OAO
080

Operation
Acc-Acc+ 13-1 0, Skip if CY= 1
Acc-Acc+A H
Acc-Acc+M
Acc-Acc+M, Skip if CY=l
Acc-Acc+M+C, C-CY
Acc-Acc + M + C, C-CY, Skip if CY = 1
BL-Acc+BL
Acc-Acc/\x
Acc-AccVx
Acc-Acc
C-A 3-A 2-A I -A o-C
Acc-Acc+F H , Skip if CY=O
X-X+1, Skip if CY=l
BL -BL+ 1, Skip if CY= 1
BL-B L+ F H, Skip if CY=O
BM-B M+ 1, Skip if CY=l
BM-BM+FH , Skip if CY=O

Operation
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
Skip
k"
S Ip

if Acc=1 3-l o
if Ai=l (i=3 to 0)
if Mi =;' 1 (i = 3 to 0)
if Acc=M
if X=M
if BL =1 3-1 0
if C=l
if S=l
and reset if IF= 1
if HF=l (AM5=0)
and reset.If AF-1
-1
- (AM s-)
Skip and reset if TF 1 = 1
Ski p and reset if TF 2= 1
Skip if Q=O
SKip if Z IBd= 1

Bit manipulation instructions
Mnemonic
SM x
RM x
SC
RC
SS
RS
IE
ID

62

Machine code
18 17 16 Is 14 13 12 II 10
OOO-OOF
09A
090
091
092
093
OBB
OA1
OBO
086
09B·
09F
OA7
OA3
OAB
OA2
OAA

Test instructions
Mnemonic

(5)

SM578/SM579

Machine code
18 17 16 Is 14 13 12 II 10
ODC-ODF
OD8-0DB
099
098
OA9
OA8
095
094

I

Operation
Mi""':l (i=3 to 0)
Mi-O (i=3 to 0)
C--1

c-o
S-l
S+-;O
E-1
E-O

4-Bit Microcomputer (Controller with AID Converter)

(6)

1/0 instructions
Mnemonic
ATQ
QTA
ATP
PTA
ATR
RTA
AXTR
RTAX
MTR
KCTA
KITA
S2
R2
SF
RF

(7)

Machine code
18 17 16 Is 14 13 12 11 10
08E
OBE

08F
OM
08C
OC3
OAC
OAD
09C
OBC
OBF
083
082
089
088

TCTRL x

Machine code
18 17 16 Is 14 13 12 II 10
OAF

OOO-OFF

STMI
LTMI

097
09D
OB7

STM2 x

OOO-OFF

LTM2

(9)

Operation
Q-Acc
Acc-Q
P-Acc, PM-l
Acc-P, PM-O
R IBd-Acc
Acc-R IBd
Rill-X, RIOI-Acc
X-R 111, Acc-R [01
R IBd-M
Acc-KC
A3-K 1, A2-K H , A 1-K T , Ao-KL
2lBd-l
21Bd-0
F-l, FM 1-A 1, FMo-Ao

F-O

Timer control instructions
Mnemonic

(8)

SM578/SM579

081

Operation
DM-1 7-I o
TIMERl-X, Ace
X, Acc-TIMERI
TIMER2-MR, MR-h-I o
X, Acc-TIMER2

AID conversion instructions
Mnemonic

Machine code
Is 17 16 15 14 13 12 11 10

COMP

OA5

Operation
AMs-A2/\At. A4-A 2 /\A o, AM 3-A 3
AMi-A2, AMI-At. AMo-Ao
AID Conversion or comparison

Standby instructions
Mnemonic

Machine code
18 17 16 Is 14 13 12 II 10

CCTRL

OB5

Operation
CM 2-A 2, CMI-At. CMo-Ao
Standby mode if A3=0

---~"'------SHARP

---------....-.----63

4-Bit Microcomputer (Controller with AID Converter)

•

SM578/SM579

System Configuration Example (Air conditioner)
Power ON
signal

Thermister
Buzzer ON Operation
SW 1'_--;::j~In~d~o~o~r~t~he~r~m~o~m~e~t~er~'-~~INIr+-~
output
If..IINV-+-'

Relay

~~~~~~~~~~~FT~~~20

5V --+--"--t-'

19
'-------Mode set inputs
Remote control
detector unit

3.H

' - - - - - - I Revolution detector

-------...-.-------------SHARP . - - - - - - - - - - - - -

64

SM5E4

4-Bit Microcomputer (Controller with Multi-I/O Ports)

SM5E4
•

4-Bit Microcomputer (Controller with Multi 110 Ports)

Description

•

Pin Connections

The SM5E4 is a CMOS 4-bit microcomputer
which integrates a 4-bit parallel processing function, a ROM, a RAM, I/Oports, a serial interface, a
timer/event counter in a single chip.
Provided with five kinds of interrupt and a subroutine stack function using the RAM area, it
allows data transfer in byte unit.
Operated from 3 to 5V single power supply with
high speed, this microcomputer is applicable to
many applications from a battery back-up system
to a high performance system. Especially, it is best
suited to systems required for multiple control signals, due to equipped with 70 I/O pins.

•

Features
1. CMOS process

ROM capacity: 6,144 X 8 bits
RAM capacity: 320 X 4 bits
Instruction set: 98
Subroutine stack: using RAM area
Instruction cycle
1. 7 p. s (MIN.) at 5V power supply
3. 1 p. s (MIN.) at 3V power supply
7. Interrupts
External interrupts: 2
Internal interrupts: 3
8. Input/output ports
I/O ports: 48
Input ports: 6
Output ports: 16
9. 8-bit serial I/O
10. 8-bit counter/timer: 1 set
11. Standby function
12. Expandable external data ROM/RAM
13. 8-bit parallel I/O
14. On-chip crystal oscillator and clock divider
circuit
15. On chip system clock CR oscillator
16. Single power supply: 2.7 to 5.5V
17. 80-pin QFP (QFP80-P-1420)
2.
3.
4.
5.
6.

Top View

'-~-----"-'---SHARP-'-'--~----

65

4-Bit Microcomputer (Controller with Multi-I/O Ports)

•

Block Diagram

•

Pin Discription

66

Symbol
PO O-P0 3 • Pl o-PI 3
P4 0 -P4 3 • P5 0 -P5 3
P6 o-P6 3 • P8 o-P8 3
P9 0 -P9 3 • PG O-PG 3
PH o-PH 3 • PI o-PI 3
PIo - Ph PK o- PK 3
P2 o-P2.3 • P3 0 -P3 3
PA o-PA 3 • PB o-PB 3
P7 o-P7 3
INTA.INTB
CK b CK 2
OSCIN• OSCOUT

I/O

¢

0

VDD• GND
TEST
RESET

I

I/O

Function

I/O ports

0

Output ports

I
I

,
Input ports
Interrupt input ports
System clock CR oscillator
Crystal oscillator
Synchronous clock output port
Power supply
Test (normally connected to GND)
Reset input port

SM5E4

4-Bit Microcomputer (Controll~r with Multi-I/O Ports)

•

SM5E4

Absolute Maximum Ratings

Note 1:
Note 2:

•

Rating
-0.3 to +7.5
-0.3 to Voo+0.3
-0.3 to Voo+0.3
40
-20 to +70
-55 to +150

Symbol
Voo
VI
Va

Parameter
Supply voltage
Input voltage
Output voltage
Output current
Operating temperature
Storage temperature

10

Topr
Tstg

Unit
V
V
V
rnA
·C
·C

Note
1
2

The maximum applicable voltage on any pin with respect to GND.
Sum of current output from (or flowing into) output pin.

Recommended Operating Conditions
Parameter
Supply voltage
Crystal oscillation frequency
Reference clock oscillation
frequency
Note 1:

•

Symbol

Conditions

Voo
fosc
f

Input voltage

Input current

Output current

Symbol
V IHI
VILI
VlH2
VIL2
IlH

lOLl
IOH2
IOL2
IOH3
IOL3
lop

Current consumption
1ST

Note 6:
Note 7:
Note 8:

2.3
1.3

1.7
0.7

Note

Unit
V
kHz

1

MHz

(Voo=2.7 to 5.5V, Ta=-20 to +70·C)

10Hl

2:
3:
4:
5:

MAX.
5.5

Oscillation start time: within 10 seconds.

Parameter

Note
Note
Note
Note

TYP.
32.768

Voo=5V
Voo=3V

DC Characteristics

Note 1:

MIN.
2.7

Conditions

MIN.
0.7Voo
0
Voo-0.5
0
Vpp=5.0V±10%
20
VlN=OV
2
VoH =V oo -0.5V
50
VoL =0.5V
250
VoH =V oo -0.5V
100
500
VOL =0.5V
400
Voo=5.0V±10%
VOH =V DD -O.5V
100
1.6
Voo=5.0V±10%
VOL =0.5V
0.5
f=lMHz
Voo=5.0V±10%
f=0.5MHz
Voo=3.0V±10%
Voo=5.0V±10%
Standby
Voo=3.0V± 10%
current

TYP.

MAX.
Voo
0.3Voo
Voo
0.5
200
200

Unit
V
V
V
V

Note

p.A

1

1
2

p.A
p.A
p.A
p.A

3
4

p.A
5
rnA
1
0.3
50
12
5

rnA

p.A

6
7
-

8

Applied to pins 1'0 0 -1'0 3 , Pl o-Pl 3 , 1'4 0 -1'4 3 , 1'5 0 -1'5 3 , 1'6 0 -1'6 3 ,
1'8 0 -1'8 3 ,1'9 0 -1'9 3 , (in input mode)
1'70 -1'7 3 , RESET. PG O-PG 3 , PHo-PH" 1'1 0 -1'1 3 • pJo-P]" pK o-pK 3 •
Applied to pins CK" OSClN , TEST o, INTA, INTB
Applied to pin CK 2
Applied to pin if.
Applied to pins 1'00 -1'0 3 , 1'1 0 -1'1 3 , 1'4 0 -1'4 3 • 1'5 0 -1'5 3 , 1'6 0 -1'6 3 ,
1'8 0 -1'8 3 .1'9 0 -1'9,. (In output mode)
1'2 0 -1'2 3 ,1'3 0 -1'3 3 , pAo-pA 3 • pBo-pB 3 •
pG o-pG 3 .I'Ho-pH 3 , 1'1 0 -1'1 3 , PJo-P]" pK o-pK 3 •
No-load condition
When crystal oscillation circuit is activated under no load conditions.
When crystal oscillation circuit is inactivated under no load conditions. OSCIN pin should be connected to GND.

---------.--.-SHARP~-----~-.-....

67

4-Bit Microcomputer (Controller with Multi-I/O Ports)

•

SM5E4

AC Characteristics
(1)

(Voo=2.7 to 5.5V, Ta=-20

Clock characteristics
Parameter

Reference clock oscillation
frequency (CR oscillation)

S;ymbol
fCR

Reference clock input
frequency (CKd
CK) input rise time
CK) input fall time

tKR
tKF

CK) input high range

tKH

CK) input low range

tKL

OSC crystal oscillation
frequency
OSC0l 1T input cycle time
OSC0l 1T input rise time
OSC0l1T input fall time
OSC0l 1T input high range
OSC0l 1T input low range
Note 1:

fK

Conditions
Voo =5V±10%, R=12kO±5%
V oo =3V±10%, R=39kO±5%
R=39kO±5%
V oo =5.0±10%

Voo =5.0V±10%

Voo~5.0V+10%

MIN.
1.7
0.5
0.5
0.25
0.25

·MAX.
2.3
1.0
1.0
2.3
1.0
500
500

0.3
0.6
0.3
0.6

Note

MHz

MHz
ns
ns

ps
kHz

2
500
500
1
1

!

Unit

ps

32.768

fosc
tfY
tlR
tittfH
tIL

TYP.
2.0
0.75
0.75

t~ +70"(;)

tCYC
ns
ns

1

tcYC
tcyC

1
1

tcyc: Cycle time of one fourth the reference clock oscillation frequency.

CK)Jnput

osc Input

Fig. 1 Clock timing
(2)

Interrupt input

Parameter
. INT A high range
INT A low range
INTB high range
INTB low range

(Voo=2.7 to 5.5V)
Symbol
tAH
tAL
tBH
tBL

Conditions

Note 1: tcyc: Cycle time of one fourth the reference clock oscillation frequency.

INTA} \
INTB Input

Fig. 2 Interrupt Input timing

68

MIN.
2
2
2
2

TYP.

MAX.

Unit

Note

tcYC
tcyC
tcyC
tcyC

1

4-Bit Microcomputer (Controller with Multi-I/O Ports)

(3)

SM5E4

(Voo=2.7 to 5.5V)

External Serial Input Clock
Symbol

Parameter
SCK cycle time

tSY

SCK high range

tSH

SCK low range

tSL

SCK rise time
SCK fall time
Reset pulse width (low)

MIN.
1
1
1/2
112
112
112

Conditions
Voo=5.0V± 10%
Voo =5.0V±10%
Voo =5.0V±10%

TYP;

MAX.

Note

tCYC
tcyC

1

tcyC
500
500

tSR
tSF
t RST

Unit

300

ns
ns
ns

Note 1: 1:cvc: Cycle time of one fourth the reference clock oscillation frequency.

r----Voo
O.7Voo

SCKinput

-------__.'

,.----------Voo

\:"'j3V,"

RESET input

Fig. 3

External serial input clock timing

69

SM5E4

4-Bit Microcomputer (Controller with Multi-I/O Ports)

•

Hardware Configuration

(1) Program counter (PC) and stack
The program counter consists of a 7-bit page
address register (Pu) and 6-bit binary counter (PLl
used to specify the steps within a page.
The stack pointer (SP) is a register which holds
the starting address of the stack area of RAM
space.
(2) Program memory (ROM)
The on-chip ROM has a configuration of 96
pages X 64 steps X 8 bits, and stores programs and
table data. Fig. 4 shows the ROM configuration.
1

0

PU6

~4

PU 3 -PU O

0

1

2

0

3

(4) General-purpose register
Registers Hand L are 4-bit general-purpose
registers. They can transfer and compare data with
the Ace on a 4-bit basis. Registers D and E are
4bit registers and can transfer data with the Hand
L registers on an 8-bit basis.
(5) Clock divider and IFV flag
The SM5E4 contains a crystal oscillator and a
15-stage divider. A real-time clock can be provided by connecting an external crystal oscillator
between the oscillator pins.

1

Timerlevent counter
The timer/event counter consists of an 8-bit
count register (TC) and an 8-bit modulo register
(TM).
The count register (TC) is an 8-bit incremental
binary counter. It is incremented by one at the falling edge of its CQunt pulse (CP) input. If the count
register overflows, the timer interrupt request flag
1FT is set, and the contents of the modulo register
(TM) are loaded into the count register.
(6)

0

1
2
3
4

5
6

7
8
9
A
B
C
D
E
F

(7) Serial interface
Fig. 4

ROM configuration

(3) Data memory (RAM)
Data memory has a 320 X 4-bit configuration,
and is used to store processing data and other information.
Data memory is also used as a subroutine stack.
Fig. 5 shows the RAM configuration.

~

Lower

Data memory is specified by a 9-bit address,
and the RY is placed in the highest bit.

RY-l

RY-O
0 1 2 3 4 5 6 7 8 9A

Be DE F

0

1

2
3
4

i

5
6
7
8
9

A
B
C
D
E

F

Fig. 5

RAM configuration

0 1 2 3

The serial interface consists of an 8-bit shift
register (SB) and a 3-bit counter, which is used to
input and output the serial data.
The input and output of serial data is controlled
by the serial clock which can be selected with
either an 'internal clock (system clock) or an external clock.
(8) Interrupts
The interrupts include three kinds of internal interrupts and two kinds of external interrupts (see
Table 1).
(9) 1/0 ports and mode register
The SM5E4 has seventeen 4-bit ports (PO-PB,
PG- PK), and three mode registers (RD, RE, RF).
Data can be transferred between these ports and
registers under direct instruction control or indirect L register control.
Ports PO, PI, P4, P5, P8, P9, PG, PH, PI, PJ and
PK can be placed in input or output mode, 4-bits at
a time.
Ports P2, P3, PA and PB are 4-bit parallel output ports. Port P7 is a 4-bit parallel input port.
Each bit of port P6 can be independently placed

-------------....--.---SHARP
70

---.-.----.-..-.-~

4-Bit Microcomputer (Controller with Multi-I/O Ports)

Table 1
Interrupt request
INTT
INTA
INTS
INTB
INTV

Timer / event counter interrupt
External signal INT A interrupt
Serial I/O interrupt
External signal INTB or frame
frequency interrupt
Divider overflow interrupt

Interrupt request

Int.lExt.

Priority

Int.
Ext.
Int.
Ext.

1
2
3
4

Int.

5

in input or output mode by setting or resetting the
corresponding bit of mode register RF as follows:

Interrupt routine
start' address
Page 1, Address 0
Address 2
Address 4
Address 6
Address 8

plied to pin CK 1. In this case, pin CK 2 should be
left open (see Fig. 6).
The real-time clock generator used for the divider circuit is shown in Fig. 7 (a). The system clock
¢ has a frequency of one fourth that of the clock
applied to pin CK 1. When applying an external
clock to pin OSC OUT, the master clock frequency
should be set at more than 8 times that of the external clock.

RFi =0: Pin P6i is an input pin.
RFi = 1: Pin P6i is an output pin.
(i=O, 1, 2, 3)
Ports (PO, PI), (P2, P3), (P8, P9), and (PA, PB)
can be paired for use in data transfer on a
byte-by-byte basis. However, port pairs (P2, P3)
and (P A, PB) are usable only for output.
(10) Standby mode
Executing the CEND instruction places the device in standby mode. To reduce power consumption, the system clock is inactivated. Standby mode
may be cleared with the interrupt request or the
RESETsignal.
(11) Reset function (ACL: Auto Clear)
Applying a Low level signal to the RESETpin resets the internal logic of the device.
When the device is reset, it is placed in the following initial state:
• The program starts execution at address 0 and
page O.
· I/O ports are placed in the input mode, mode
registers RD, RE and RF are cleared, and all output ports (P2, P3, P A, PB) are cleared to O.
• All interrupt flags are reset to disable all interrupts.
· The contents of RX and RY are cleared to O.

SM5E4

External_ CK,

clock
R

Open- CK2

(a)

CR oscillator

Fig. 6

(b)

External clock

Clock oscillator circuit

,--II-----

""'

I

--

150
150

ns
ns

55

ms

ps

~

-

Data input

""'
tOH

K

V IH

~

V1L

r-tAH~

High
inpedance

Data output

~~

~

---

Unit

ps
ps
ps
ps
ps
ps

1

)
""'

MAX.

2

PGM-Vpp

I+-t AS _
Data

MIN.
2
2
2
2
0
2
0

VOH
Hz
VOL

t--tOF---'"
Vpp
VOO

I--tvs ......
V IH

\

V1L
j+tCES....

l:1
f<-tpw

VIH

f-

V1L

~
~

I,

'VIH

J

V1L

-~---------SHARP--------'81

LU5E4POP

4-Bit Microcomputer (Controller with On-Chip OTPROM)

•

Hardware Configuration

The hardware configuration of the LU5E4POP is
the same as that of the SM5E4, except for an
on-chip program memory of an OTPROM for the
LU5E4POP, and a ROM for the SM5E4, Refer to
the SM5E4 for the hardware configuration.

•

•

PROM Programming

When data is written into an on-chip OTPROM,
apply the conversion socket adapter (LROE82) to

•

the commercial EPROM writers.
Use the EPROM writer which allows the
LH5764 mode set, and eliminates or clears the
electric signature mode.
See Pin Connections for the signals in parentheses used PROM programming.

Instruction set

See the SM5E4 for the instruction set which is
the same as that of the LU5E4POP.

System Configuration Example

Control signals

~~~~~~~__~~__~~~~~____~~4~1
~

~u"~t~~~~~~~~~~~~ii£iaa~S~
Uoo--1l.1l.1l.1l.1l.1l.1l.1l.1l.1l.1l.1l.1l.1l.1l.1l.1l.1l.1l.

Von ~
OSC'N
'OSCOUT

~

PB 2 t--..-.
PB ,
,PBo 1--'----

_-+~IINTA

LU5E4POP

PA3 I--'_~
PA2
PA,
PAo t----P9 3

Control
signal

GND
P9 2
P9 ,
P9 0
P8 3
P8 2
P8,
P80

Control signal

7X4key

Matrix

25

80

4

Input signal

82

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

SM5J5
SM5J6

SM5J5/SM5J6
4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)
•

Description

The SM5]5/SM5]6 is a CMOS 4-bit microcomputer which integrates a 4-bit parallel processing function, interrupts, an A/D converter, a comparator, a counter/timer circuit, and a sound output function in a single chip.
An A/D conversion can be executed by one instruction with simple software, and provides a high
speed processing. This feature enables to accept
analog signals from sensors.
Provided with unique features of 52 110 ports, a
couple of programmable counter/timers, and interrupt functions, this microcomputer is suitable for
controlling functions required for a timer set.
The SM5]5 directly drives a fluorescent display
tube, and the SM5]6 provides two modes of standby function for low power operations.

•

•

Features
L
2.
3.
4.
5.
6.

CMOS process
ROM capacity: 8,192 X 9 bits
RAM capacity: 256X4 bits
Instruction set: 94
Subroutine nesting: 6 levels
Instruction cycle
SM5]5: 2.5 f-'- s (MIN.)
SM5]6: 2 f-'- s (MIN.)
7. Interrupts
External interrupts: 2
Internal interrupts: 3
8. Input/output ports
I/O ports: 31
Input ports: 9
Output ports: 12
9. 8-bit serial I/O

Pin Connections

VOSp/Voo* 8

A.cL

OSCOUT 10
OSCoUT/KT 11

*

VDSP for SM5J5, Voo for SM5J6
Top View

83

4-Bit.Microcomputer (VFD Driver)
4;"'Bit Microcomputer (Controller with AID Converter)

10. AID converter:
8 bits (10-channels MAX.)
11. Counter Itimer: :2 sets
12. Standby function
SM516: 2-stage system clocks
13. High voltage output: -40V
SM515: 16-segment, 10-digit

•

SM5J5
SM5J6

14. Supply voltage
SM515: 4.5 to 5.5V
SM5]6: 2.7 to 5.5V
15. 64-pin Smp(SDIP64:-P-75Q)
64-pin QFP (QFP64-P-1420)

Block Diagram

V DD

GND
GND
fOUT

V RH

ACL

V RL

T

KCD
KC1
KC2

KH
KL

KCs

F

Symbol description
ALU
: Arithmetic logic unit
Ace
SR
X
: X register
RO,Rl,R2,R3
,B
: RAM address register
DlV
C
: Carry F/F
Program counter
SP
: Stack pointer
CG
: System clock generator
MPX.
: Multiplexer
AID
: AID .converter and comparator unit

ec

Note:

84

:

Pin numbers apply to a 64-pin QFP.

Accumulator
Stack register
Latch
Divider

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

•

SM5J5
SM5J6

Pin Description
Symbol
PO-P 3 , QO-Q3
RO o-R0 3
Ri o-RI 3
R2 o-R2 3
R3 0 -R3 3
ZO-Z9
ZlO-Zl5

KC o-KC 3
KH,KL
KI
OSC1N/KT
OSCOUT
F
fOUT
CL l
CL 2
ACL
VRH, VRL
Voo
GND
T
SIN
SOUT
SCLOCK
Vosp/Voo

110
110
110
110
I/O
110
0
110
I
I
I
I
0
0

I

I
I
0
I/O

Function
Input/output ports (Nibble unit)
Input/output ports (Nibble unit)
Input/output ports (Nibble unit)
Input/ output ports (Nibble unit)
Input/output ports (Nibble unit)
Output ports (ait unit)
Input/ output ports (Bit unit)
Input ports or analog input ports
Input ports
Interrupt input port or input port
Timer clock input port or input port
Timer dock oscillator
Sound output port or output port
System sync. signal output port
Clock signal input port
Clock signal oscillator
Auto clear input port
A/D converter
Power supply
Ground
Test input port
Serial 110 data input port
Serial 110 data output port
Serial 110 clock port
Power supply

Note

I
I
I
I
I

2
3

Note 1: SM5J5, -40V high voltage
Note 2: Input port ill the ACL
Note 3: SM515, -30V (TYP.)
SM5J6,

+ 5V (TYP.)

85

4-l3it Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

•

SM5J5
SM5J6

Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage

Output HIGH voltage

Symbol
VDD
Vasp
VI
Vm
Vo
VOD

IOH

Applicable model
SM5J5/5J6

SM5J5
SM5J5/5J6

SM5J5
SM5J5/5J6

SM5J5
SM5J5
SM5J6
SM5J5
SM5J6
SM5J5/5J6
SM5J5/5J6
SM5J5/5J6

SM5J5
SM5J6

Output LOW voltage

Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note

86

IOL

SM5J5/5J6
SM5J5/5J6
SM5J5/5J6
SM5J5/5J6
SM5J5/5J6

Rating
-0.3 to +7.5
VDD -40 to VDD +0.3
-0.3 to VDD +0.3
VDD -40 to VDD +0.3
-0.3 to V DD +0.3
V DD -40 tCl VDD +0.3
-40
-.20
-12
-10

-4
-2.5
-2
-80
-60
-20
4.0
400
2.0
25

Unit

Note
1

~
~

V

1,2

r-t3
~
~
1,5

6, 7

r-8

r--g-

rnA

r--

~
11

r-12

r-rnA
flA

rnA

13
14
15
11

r-u;

1: Referenced to GND.
2: Applied to all input ports except for the case' where the R (O)-R (3), 2o-Zg of the SM5]5 are used as high voltage input ports.
3: Applied to pins R (O)-R (3), ZO-Zg which are used as high voltage input ports.
,
4: Applied to all output ports except for the case where the R (O)-R (3), ZO-Zg of the SM5]5 are used as high voltage input
ports.
5: Applied to pins R (O)-R (3), ZO-Zg which are used as high voltage outputs.
6: Applied to the case where only one port of ZO-Zg is output.
7: Applied to the case where the duty ratio during High level output is less than 117 (cycle: lOms).
8: Applied to the case where only one port of R (O)-R (3) is output.
9: Applied to the case where only one port of P, Q, ZlO-Z'5 is output.
10: Applied to the case where only one port of F, fOUT, SCLOCK is output.
11: Applied to CL 2 pin.
'
12: Applied to the sum of R (O)-R (3), ZO-Zg.
13: Applied to the output ports except for ports mentioned in note 10.
14: Applied to the case where only one port of Q, ZlO-Z'5 (CMOS output), P is output.
15: Applied to the case where only one port of Q, ZlO-Z'5 (with a pull-down resistor) is output.
16: Applied to the sum of all ports.

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

•

SM5J5
SM5J6

Recommended Operating Conditions
(1) SM5J5
Parameter
Supply voltage
System clock frequency

Symbol
Voo
fs

Condition

Rating
+4.5 to +5.5V
312.5

Unit
V
kHz

Symbol
Voo

Condition

Rating
+2.7 to +5.5
50 to 500
50 to 250

Unit
V

(2) SM5J6
Parameter
Supply voltage
System clock frequency

•

fs

Voo=4.5 to 5.5V
Voo=2.7 to 3.3V

SM5J5 (Voo=4.5V to 5.5V, Ta= -10 to +80"C)
SM5J6 (Voo=2.7V to 5.5V, Ta=-10 to +80"C)

DC Characteristics
Parameter

Input voltage

Input current
Input leakage
current

Symbol
VIH1
VIL1
VIH2
VIL2
VUl3
VIL3
IIH
IlL

IOL4
IOH5

VoH =V oo -2.0V

VOL

Voo=5.5V, Vosp=-30V
Voo=5.0V
Voo=5.0V
Vo=Voo
Vo=Voo
Standby· mode
fCL ;= 500kHz,
Voo =5.0Voperation
fCL =312.5kHz,
Vosp: open
f cL =312.5kHz,
Vosp: -30V

IOL2
IOH3
IOL3
IOH4

Output voltage

Rl
Internal resistance
R2
1ST

100
Current
consumption

VIN=VOO
VIL=OV

VOH=V oo-0.5V
VoH =V oo -0.5V
VoL =0.5V
VOH=Voo-0.5V
VoL =0.5V
VoL =0.5V
VOIi=V oo -0,5V
VoH =V oo -0.5V
VOL=0.5V
VoH =V oo -2.0V
VoH =V oo -2.0V
VoL =0.5V

lOLl
IOH2

Output current

Condition

ILK
IOHl

IODl
1002

kHz

Applicable model
MIN.
SM5J5/5J6
0.8Voo
SM5J5/5J6
0
SM5J5/5J6
Voo-0.5
SM5J5/5J6
0
VDD -O.4
SM5J5/5J6
SM5J5/5J6
0
SM5J5/5J6
SM5J5/5J6

TYP.

MAX.
Voo
0. 2Voo
Voo
0.5
Voo
0.4

SM5J5
SM5J6
SM5J5/5J6
SM5J5/5J6
SM5J5
SM5J6
SM5J5
SM5J6
SM5J5/5J6
SM5J5
SM5J6
SM5J5/5J6
SM5J5
SM5J6
SM5J5
SM5J5
SM5J6
SM5J5
SM5J6
SM5J6

-0.8
-0.4

SM5J6

10
100
-0.8
-0.4
-0.5
-0.4
30

5

V

1
r--2

t-3

r-----sflA r - - 10

30
25
200
100

Note

4

50
-45

SM5J5/5J6

10
5
40
30

Unit

-15
-7
-100
-7
-4
28
60
50
500
200
10

6
rnA

7

flA

r----g

8

10
rnA r - - 11

flA

12

rnA

13

flA

9

rnA

14

V

15
10

kO

-

16

flA

17
18

10

,----

SM5J5

5

8

rnA

17

t-SM5J5

-----~~-~~-SHARP

15

30

19

- - - - - - - - . - - - - - - - .......
87

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

SM5J5
SM5J6

1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11:
12:
13:
14:
15:
16:

Applied to pins KH, KL, KI, P O-P 3, QO-Q3, KC o-KC 3.
Applied to pins 2 10 -2 ,5, CL" OSCJN/KT, ACL, R (O)-R (3).
Applied to SIN, SCLOCK.
Applied to ACL pin.
Applied to SCLOCK pin.
Applied to pins QO-Q3, 2 10 -2'5 without any pull-down resistors, or KH, KL, KI, KC o-KC 3, po-p., SIN, SCLOCK, OSCIN/KT, ACL.
Applied to pins PO-P 3, QO-Q3, 2 10 -2'5'
Applied to the case where QO-Q3, 2'0-2'5 are used as open drain outputs.
Applied to CL z pin.
Applied to pins QO-Q3, 2 10 -2'5 used as CMOS outputs, or PO-P 3, F, fOUT' SOUT, SCLOCK.
Applied to pins F, fOUT' SOUT, SCLOCK'
Applied to pins QO-Q3, 2 10 -2'5 with pull-down resistors.
Applied to pins 2 0 -2 9 ,
Applied to pins R (O)-R (3).
Applied to pins R (O)-R (3), 2 0 -2 9 with pull-down resistors. (pull-down to Vos P.)
Applied to pins R (O)-R (3), 2 0 -2 9 with pull-down resistors. (SM5J5: pull-down to Vosp or GND with a mask option. SM5J6:
pull-down to GND only.)
Note 17: No load condition. (the oscillation frequency should be 8 times of fs, and the OSCIN/KT port should be connected to GND.
Note 18: No load condition. (the oscillation frequency should be 8 times of fs.)
Note 19: No load condition. (the oscillation frequency should be 8 times of fs), ACL state, the 100 is a current flowing between VDO and
Vos P•

Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note

•

AID Conversion Characteristics.
SM5J5 (fs=312.5kHz, VDo =5.0V, VRH =5.0V)
SM5J6 (fs=500kHz, VDo =5.0V, VRH=5.0V)
Parameter
Non-linearity error
Integration non-linerarity error
Zero error
Full-scale error
V RH pin supply current
Total error

•

VRL pin
GND
GND
GND
GND
-

MIN.

TYP.

100

GND

MAX.

±3
±3
±3
±3
300
±3

Unit
LSB
LSB
LSB
LSB
pA
LSB

Oscillator Circuits
(1)

Recommended oscillator circuit for the SM5J5
eLz
Rr

R,=IMfl
Rd =330fl
C,=22pF
C z =22pF
X, = 2.5MHz Ceramic oscillator
Above constants apply to the case where the uscillator is used
with the CSA2.5MG (MURAT A)

(2)

Recommended oscillator circuit for the SM5J6
R,=IMfl
C,=15pF
C 2 =15pF
X, =4.0MHz Ceramic oscillator
Above constants apply to the case where the oscillator is used
with the KBR-4.0MS (KYOSERA)

----.-------SHARP-----..-..--88

. 4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

•

SM5J5
SM5J6

Pin Functions
(1)

Vee, Vesp, GND (Power supply)

The VDD pin is the positive power supply (3V to
5V) with respect to GND.
The SM5J5 provides the VDSP which is the nega:
tive power supply (-35V) with respect to GND.
The GND pin is the reference power supply for
the LSI.

the outputs with a pull-down resistor by a mask
option. They can also be used with an open-drain
transistor structure.
• SM5J6
The ZO-Z9 are nonrially be used as
the outputs with a pull-down resistor. They can be
used with an open-drain transistor structure.
(7)

(2)

V RH , V RL (AID conversion)

The VRL pin is a GND pin for the AID converter.
The VRH pin provides the reference voltage VRH
for the AID converter.
The current consumption and operating accuracy of the AID converter must be changed according
to the case where the VRL pin is used to be left
open or provide GND level.
(3)

ACL (Reset input)

The ACL pin is used to reset the LSI.
The LSI should be reset with a transition of two
instruction cycles after the rising edge of ACL.
Applying a Low level signal to the ACL pin
starts execution of the program at field 0, page 0,
step 0 after a transition of tACt..
It is recommended to apply a capacitor between
ACL pin and VDD pin in order to prevent from external noise which affects the ACL circuit.
(4)

KC o-KC 3 (Analog Inputs)
Executing the KCT A instruction transfers the
KC input data to the accumulator Acc through input buffers.
The KC input pin also provides analog input signals given to the AID conversion block.
(5)

KH, KI, OSC1N/KT, KL (Inputs)

The KH and KI input pins are connected to the
noise debounce circuit, and the KL and OSCI~/KT
input pins to input buffers.
The KL, OSC1N/KT, KH and,KI should be loaded
into the Ao, Ab A2 and A3 bits of the accumulator
Acc upon execution of KL T A instruction.
The noise debounce circuit does not accept the
pulse input shorter than two instruction cycle
width.

(6)

Z10-Z15 (lnpuVoutput)

The ZlO-Z15 can be controlled with the output
latch F IF to be set or reset by instructions.
When· used for the inputs, the input mode of Zi
specified by lower 4 bits of B register BL can be
tested by instructions.
Tho Zi pi..
,i..oI,
tho
parator of AID converter.
The Zi pins are normally used as 110 pins with
pull-down resistors. The Zi pins can be used as
CMOS outputs or the open-drain transistor with a
protection diode. After an ACL operation, the Zi
pins are placed in input mode. When used for the
inputs, the Zi pins can be used as the outputs to be
pulled down with the output latch F IF to be reset.

t,,,,,,f,, ..,log

(8)

into ,om-12

PO-P3 (lnpuVoutput)

The PO-P 3 are three-state 110 pins.
Executing the ATP instruction transfers the
accumulator Acc to the output latch F IF which is
loaded into the PO-P 3.
The PO-P 3 can be loaded into the Acc upon execution of the PTA instructions. Then the PO-P 3
remain high impedance.
(9)

0 0 -0 3 (lnpuVoutput)

Executing the ATQ instruction transfers the
accumulator Acc to the output latch F IF which is
loaded into the QO-Q3.
While, the QO-Q3 can be loaded into the Acc
upon execution of the QT A instruction. Then, the
QO-Q3 should be used with the outputs to be pulled
down.
The Qi pins are normally used as 110 pins with
pull-down resistors. The Qi pins can be used as
CMOS outputs or the open-dra·in transistor with a
protection diode. After an ACL operation, the Qi
pins are placed in input mode. When used for the
inputs. the Qi pins can be used as the outputs to be
pulled down with the output latch F IF to be reset.

Zo-Z9 (Outputs)

The ZO-Z9 can 'be controlled with the output
latch F IF to be set or reset by instruction .
• SM5J5
The ZO-Z9 are normally be used as
high voltage outputs (- 40V). They can be used as

(10)

RO o-R0 3 , R1 0 -R1 3 , R2 0 -R2 3 , R3 0 -R3 3
(inpuVoutput)

Upon· execution of the A TR instruction, the

----.-......--~.-~-SHARP.-.~--.----

89

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

ROi-R3i outputs the accumulator Ace specified by
the lower 4 bits (BL) of the B register.
8-bit data transfer can be performed in. parallel
among the Rli, ROi and Ace or X register by the
RT AX or AXTR instruction.
. SM5J5
The Ri pins are normally used as
high voltage I/O pins (-40V). They can be usedas
the I/O pins with pull-down resistors with a mask
option.
When, used for the inputs, the Ri pins can be
used as the I/O pins to be pulled down with the
output latch F IF to be reset.
The Ri pins can also be used as open-drain transistor structure.

SM5J5
SM5J6

• SM5J6
The Ri pins are normally used as the
I/O pins with pull--:down resistors.
.
When used for the inputs, theRi pins can be
used as the input pins to be pulled down with the
output latch F IF to be reset. They can also be used
as an open-drain transistor structure .
(11) F (Sound output)
The F output pin is used for a sound output pin
as well as a general-purpose output.
(12) fOUT
The fOUT pin outputs the the signal in synchronizing with the system clock fs.
The system clock immediately after power on is
a frequency of one eighth the reference clock frequency.

- - - . - - - - - - ............. -SHARP.-~-.----.90

~I

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

•

SM5J5
SM5J6

Hardware Configuration
address by a ROM address instruction.
The TR instruction i.s used to jump within a
page, and the TL instruction is used to jump to any
address. A subroutine jump is executed by a TLS
or TRS instruction. However, when the ET value
may change due to a jump or subroutine jump, execute a TL or TLS instruction following a COMET
instruction.

(1) Program counter and stack
The program counte~ (PC) is used to address a
ROM location.
The PC consists of 13 bits allocated 4 bits (ET,
Pu) to the field specification of ROM, 2 bits (PM) to
the page specification, and 7 bits (Pd to the step
specification. The PM and PL are binary counter for
the page specifications.
The stack register (SR) consists of 6 stages
available for up to 6 levels of subroutine nesting.

(3) Data memory (RAM) and B register
The RAM is used to store data.
The SM5J5/SM5J6 has a 1,024-bit RAM organized as 16 X 16 X 4 which consists of 16 files as
shown in Fig. 2. A file consists of 16 words X 4
bits.
The RAM address is specified by a B register
which consists of a 4-bit BM for the file specification and a 4-bit BL for the word specification.

(2) Program lTIemory (ROM)
The ROM is used to store programs.
The SM5J5/SM5J6 has a 8,192 X 9-bit ROM
which consists of 16 fields X 4 pages X 128 steps.
When power on with the ACL to be reset, the
program starts execution at field 0, page 0, step O.
Fig. 1 shows the example of a jump to the ROM

/I

I~
PM

Field

Field

0

1

Page
0

ACL

Page

Standby
crear

1
Page

3

Field
2

Field
4

Field

3

~

Interrupt

2

Page

ET=1 (8 to 15 field)

ET=O (0 to 7 frield)

Ir

....-

Field
5

~
I--TL

6

~
COMET
TL/

Field
7

Field

/

----COMET
TLS-

---

Fig. 1

BL
~

Field
10

Field
11

Field
15

l-TRS

~

V

V
~

'-

RTN'

t=::=

r::::
---

COMET
j...--TL
COMET
jo-TLS

_RTN

./

TL/

V

/

ROM configuration
--+

0

Field
9

8

~

~
ov~r

Subrutine
TRS

Field

File

..

E

1

F

..

0

..

1

..

2

..

E

F

~

,/

Fig. 2

RAM configuration

Word

I Ms

M2\ Ml

Mol

- - - - - , - - - - - - " - - S H A R P ---.~-------.;........-~
91

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

(4) Accumulator Ace, X and G registers
The accumulator Acc is a 4-bit general-purpose
register which. transfers numerics and data. The
Acc .can be decremented and shifted to the left in
combination with the carry flag (C). Furthermore,
the Ace together with the arithmetic logic unit
(ALU), a carry flag (C) and RAM executes arithmetic operations. It also transfers data to I/O ports.
The X register is a 4-bit register which can be
used for a temporary register. It is incremented by
instructions. It performs, in conjunction with the
Acc, logical sum and logical product.
An 8-bit parallel data of the Acc and X register
can be transferred to R [OJ and R [lJ, a G register
or a counter/timer.
On the other hand, each data on ROi and R1i, a G
register or a counter timer can also be transferred
to the Acc and X register with an 8-bit parallel
data.
The G register is an 8-bit register which is used
for A/D conversion or comparison of analog signals.
(5)

Arithmetic and logic unit (ALU), carry flag
(C)

The arithmetic and logic unit (ALU) performs, in
conjunction with a RAM, a carry flag C and an
accumulator Acc, binary addition on a 4-bit basis
by instructions.
The carry flag C latches the data incremented by
the ADC or ADCS instruction.
(6) S8 register
The SB register is an 8-bit register used for a
save register.
P, Q, R [3]-R [0], Z (Output latch registers)
Registers P, Q, RO, R2, R3, Z connect with the
output latch F /F.
The accumulator Acc can be tran$ferred to registers P, Q, R [3J-R [OJ, and an 8-bit data of the
Acc and X register can be transferred, at the same
time, to the output latch registers R [OJ and R [lJ.
(7)

(8) System clock generator circuit
The system clock generator circuit generates a
system clock of a reference frequency input from
the CLI pin divided by 4 or 8.
The system clock speed can be controlled with a
program. If it is not required for high speed operation, the system clock can be switched to the low
speed in order to save .the power consumption;
This function is also applicable to the case where

SM5J5
SM5J6

the power supply is replaced by a battery backup
power.
The system clock when reset is the reference frequency divided by 8.
The system clock fs is used to determine the'instruction execution cycle, and the system clock cycle should be identical to the instruction execution
cycle. However, the instruction execution cycle of a
two-word instruction should be two times as long
as a one-word instruction.
(9) Counter/timer
A timer 1 and a timer 2 are 8-bit counter/timers. The data incremented by a count up is latched
into the flags TF1 and TF2 to be used for an interrupt request. Executing the TTF1and TTF2 flags
checks the flags TFl and TF2.
. Timer 1: An 8-bit data of the Acc and X register
can be transferred to the timer 1. To the contrary, the timer 1 can be read out from the Acc
and X register.
• Timer 2: The timer 2 contains a modulo register
(MR register). The contents of the modulo register (TM) are loaded into the timer 2 each time
the register is incremented by one.
An 8-bit data can be loaded into the MR register
by instructions, and executing the next instruction cycle transfers the data to the timer 2 which
can be read out from the Acc and X register.
The count up pulses of a counter/timer include
(1I2)9fs, (1/2)6fs, (1/2)3fs, (1/2)6fr and fr, under
conditions of a system clock fs and KT input pulse
fT' which can be selected by a program.
A carry output of one counter can be used for a
count up pulse of the other counter.
(10) Interrupt
A KI input, the timer 1 and timer 2 carry and an
analog input are available for the interrupt request, and the interrupt request flags include the
IF, TF1, TF2, and AF flags.
The interrupt block consists of the mask flags
(E3, E a, EI and Eo), E flag and interrupt processing
circuits.
(See Fig. 3)
Table 1 shows the jump address caused by an
interrupt request.
(11) AID converter
The A/D conversion block consists of an 8-bit
D/ A converter, a comparator, an AM flag and AF
flag.
The KC and Z pins input the analog signals.
Executing the CaMP instruction allows the A/D

~~---------SHARP,''-'-'~'''''--'--'---.--r~

92

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

conversion and the large/small comparison automatically. (See Fig. 4.)
The result of AID conversion is stored in the G
register with the interval of 32 instruction cycles
after the COMP instruction is executed.
The result of the largel small comparison is
stored in the AF flag with the interval of 6 instruction cycles.
The G register is an 8-bit register which can be
transferred to the Ace and X register with the
GT AX instruction.
The KC o pin can also be used for external interrupt.
The DI A converter generates the voltage VREF
according to the contents of the G register.
Assuming that the "n" is placed in the G register
as a result of AID conversion, the analog input voltage may be regarded as a below expression.

SM5J5
SM5J6

When even more strict accuracy is required in
the AID conversion block, an external GND level
may be applied to the VRL pin. The AID conversion is executed by the comparison among a G register, a DI A converter and a
comparator in order.
The large/small comparison is executed by the
comparator output VREF according to the G register
value and the analog signal of the KC o. The result
of comparison is stored in the AF flag.
(12) Sound output block
The F pin outputs the frequency obtained by a
count-up pulse generator circuit.
The pulse frequency can be selected from (1 I
2)7fs, (1/2)9fs, (1/2)4f r and (1I2)6fT by programs.

*The fT is a timer clock frequency input from the OSC'N/KT pin,
and the fs is a system clock frequency.

256-n
256 V RH (n=O to 255)

*V

RH

is a reference voltage supply from the V RH pin.

Mask flag

Stack
register

Interrupt request flag '--.--.L--r--'--,............- ,........

Program
counter

Timer!

Timer2

KI input

TF2~------------4----r--~

IF
E

Analog input
comparator

Interrupt enable
flag

AF 1 - - - - - - - - - - - - - ;

Fig. 3
Table 1

Interrupt block
Interrupt jump address

Interrupt request flag
Timer 1 carry (TFl)
Timer 2 carry (TF2)
KI input (IF)
Analog input comparator (AF)

Jump destination address
Field
Page
Step (PL)
0
2
.0
0
2
2
0
2
4
0
2
6

Priority
1
2
3
4

93

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

SM5J5
SM5J6

comparator

Analog· signal

Fig. 4

AID converter block

(13) Standby mode (for SM5J6)
To reduce power consumption, the device is
placed in standby mode, and the program execution
is inactivated.
The following two types of standby mode can be
selected.
• Off mode
In the off mode, the system clock
generator circuits except for a counter/timer and a
count-up pulse generator circuit are inactivated.
. Hold mode
In the hold mode, the systems
except for a system clock generator circuit, a counter/timer and a count-up pulse generator circuit
are inactivated.
While in standby mode, if a KH input or an interrupt request from an unmasked KI, timer 1 or
timer 2, the device exits standby m()de and starts
program execution.

(14) Reset function '(ACL)
The device is reset with the interval of two instruction cycles from the· rising edge of the ACL
pin.
Applying a High level signal to the ACL pin resets the internal logic of the device and applying a

94

Low level signal starts execution of the program at
address 0, page 0.
In case the noise may harm the ACL operation,
apply a capacitor between ACL pin and V DD pin.
(15) Serial 110
The serial 110 consists of an 8-bit shift register,
a 3-bit counter and a 6-bit mode flag, which have
the following features.
· Selectable either an 8-bit, a 4-bit, a 2-bit or a
I-bit transfer system.
• Interrupt request available at the end of
transfer.
• Selectable transfer clock among a system clock, a
timer 2 output or an external clock.
· Connectable.to multiple chips.
· Usable in standby mode.
• An 8-bit shift register replaceable by the R/W
register when the serial 110 is not used.

_-_ _..-

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

.......-..-........-....................-.............

.-..-..-.
•

....

SM5J5
SM5J6

Instruction Set
(1)

ROM address instructions
Mnemonic
TR x
TL x
MTPL
TRS x
JUMP
TLS x
RTN
RTNS
RTNI
COMET

(2)

Machine code
Is 17 16 15 14 13 12 11 10
100-17F
OFO-OF7
OOO-lFF
08A
l80-lFF
OOO-lFF
OF8-0FF
OOO-lFF
OCO
OCI
OC2
08B

Operation
Jump within a page, P L+-1 6-1 0
Jump
Pu+-I ll - 19 , P M+-I s -1 7 • P L+-1 6 -1 0
Jump within a page, (PL+-A 2,-Ao M3-M o)
CALL indirect address
Pu+-l, PM+-I B, 17 , P L+-1 6-l o, if DI=l
CALL to sulbroutine
P u +-1 11 -1 9 , P M+-I s -1 7 , P L+-1 6 -1 0
Return
Return and skip
Return from interrupt
ET+-ET

Data transfer Instructions

LBMX x
LBLX x
STXI x

Machine code
18 17 16 15 14 13 12 11 10
040-04F
087
OOO-OFF
OEO-OEF
020-02F
050-05F

EXClx

070-077

EXCO x

078-07F

EXC x
LOA x
STR
EX AX
ATX
GTAX

068-06F
060-067
09E
OA6
OAE
OBO
080
OBO'
OB3
OBI
OB2
OBA
084
085
080
OC8-0CF
OB4

Mnemonic
LAX x
WLAXx

AXTG
XBLA
BLTA
XBMA
BMTA
XBSB
BTSB
SAG
SGL x
ATIM

Operation
Acc+-1 3-l o, Skip if last instruction is LAX
X+-1 7 -1 4, Acc+-1 3 -l o
BM+-I 3-l o
BL +-1 3 -1 0
M+-1 3 -l o, BL+-BL +1, Skip if CY=l
M-Acc, BM+-B MEBI 2-l o
,BL+-B L+1, Skip if CY=l
M-Acc, BM+-B MEBI 2-l o
BL +-BL + F H, Skip if CY= 1
M-Aee, BM+-BMEBI 2-I o
Acc+-M, BM+-B MEBI 2-l o
M+-Ace
Ace-X
X+-Ace
X+-G 7 -G 4, Acc+-G 3 -G O
G7 -G 4 +-X, G3 -G o+-Acc
BL-Aec
Aee+-BL
BM-Ace
Acc+-BM
B++SB
SB-B
BM+-O only next step
BM=I 2-I o BL =F H only next step
Ei+-Ai (i=3 to 0)

95

4-Bit Microcomputer (VFD Driver)
4""'Bit Microcomputer (Controller with AID Converter)

(3)

Arithmetic instructions
Mnemonic
ADX x
ADA
ADD
ADS
ADC
ADCS
ADBL
AND
OR
COMA
ROT
DECA
INCX
INBL
DNBL
INBM
DEBM

(4)

Machine code
18 17 16 15 14 Is 12 I, 10
OOO-OOF
09A
090
091
092
093
OBB
OA1
OBO
i.
086
09B
09F
OA7
OA3
OAB
OA2
OAA

Operation
Acc+--Acc+ 13 -1 0• Skip if CY= 1
Acc+--Acc + AH
Acc+--Acc+M
Acc+--Acc + M. Skip if CY = 1
Acc+--Acc+ M +C. C"-CY
Acc+--Acc+M+C. C+--CY. Skip if CY=1
BL+--Acc + BL
Acc+--Acc!\x
Acc+--Acc V x
Acc+--Acc
C+--A3+--A2+--A,+--Ao+--C
Acc+--Acc+F H• Skip if CY=O
X+--X+1. Skip if CY=l
BL +--BL + 1. Skip if CY = 1
BL +--BL + F H. Skip if CY=O
BM+--BM + 1. Skip if CY = 1
BM+--BM + F H. Skip if CY = 0

Test instructions
Mnemonic
TAX x
TBA x
TM x
TAM
TXM
TBLX x
TC
TS
TIF

Machine code
18 17 16 15 14 13 12 I, 10
010c01F
004-007
000-003

Operation
Skip if Acc - h 10
Skip if Ai-1 (i-3 to 0)
Skip if Mi-1 (i-3 to 0)

THAF

OC6

if Acc-M
if X-M
if BL -13-10
if C-1
if S-1
and reset if IF-1
if HF-1 (AM5~0)
Skip and reset if AF= 1 (AM 5 = 1)

TTF1
TTF2
TQZ

OC5
OC4
OAO
080

Skip
Skip
Skip
Skip

TZ

96

SM5J5
SM5J6

096
OB6
030-03F
OB8
OB9
OC7

Skip
Skip
Skip
Skip
Skip
Skip

and reset if TF, -1
and reset if TF 2-1
if Q-O
if Z [Bd-1

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

(5)

Bit manipulation instructions
Mnemonic

Machine code
Is 17 16 Is 14 13 12 11 10

ODG-ODF

SM x
RM x
SC
RC
SS
RS
IE

OD8~ODB

099
098
OA9
OA8
095
094

ID

(6)

Operation
Mi+-I (i=3 to 0)
Mi+-O (i=3 to 0)
C+-I
C+-O
S+-I
S-O
E-l
E-O

1/0 instructions
Mnemonic
ATQ
QTA
ATP
PTA
ATR
RTA
AXTR
RTAX
MTR
KCTA
KITA
SZ
RZ
SF
RF

(7)

.SM5J5
SM5J6

Machine code
Is 17 16 Is 14 13 12 11 10
08E
OBE
08F
0A4
08C
OC3
OAC
OAD
09C
OBC
OBF
083
082
089
088

Operation
Q+-Acc
Acc+-Q
P-Acc.PM+-I
Acc":'P. PM+-O
R [Bd-Acc
Acc-R [Bd
R [I)-X. R [O)+-Acc
X+-R [1). Acc-R (0)
R [Bd-M
Acc-KC
A3-K h A 2+-K H• A 1-K T• Ao+-KL
Z [BL)-I
Z [BL)-O
F+-I. FM 1-A h FMo+-Ao
F+-O

Timer control instructions
Mnemonic
TCTRL x
STMI
LTMI
STM2 x
LTM2

Machine code
Is 17 16 Is 14 13 12 11 10
OAF
OOO-OFF
097
09D
OB7
OOO-OFF
081

Operation
LM-I 7-I o
TIMER 1 +-X. Acc
X. Acc+-TIMERI
TIMER2+-MR. MR+-I 7-I o
X. Acc+-TIMER2

97

4-Bit Microcomputer (VFD Driver)
4-:-Bit Microcomputer (Controller with AID Converter)

AID conversion instruction

(8)

(9)

Mnemonic

Machine code
Is 17 Is Is I. 13 12 I, 10

COMP

OA5

Operation
AMs+--A2I\A" A4+--AZI\Ao. AM3+--A3
AM z+--A 2• AM,+--A" AM 3-A o
AID Conversion or Comparing

Standby instruction

(10)

•

SM5J5
SM5J6

Mnemonic

Machine code
Is 17 Is Is I. 13 12 I, 10

CCTRL

OB5

Operation
CM 2+--A z• CM,+--A" CMo+--Ao
Standby mode if A3 = 0

Table reference instruction
Mnemonic

Machine code
Is 17 Is Is I. 13 12 I, 10

LAT

08A
OOO-OFF

Operation
PUSH (SP+--SP+I. SR+--PC+I)
PL s -PL 4+--A 2-A o• PL 3 -PL o-M 3-M o
POP (SP+--SP-I. PC+--SR)
X+--I 7-I •• A+--I 3-I o

Comparison Table Between SM5J5 and SM5J6

The SM5]5 directly drives a fluorescent display
tubes. The SM5]6 provides two modes of standby
function for power saving.
Both models have the same function except for
the specifications in the electrical characteristics
and I/O ports. See the related sections for details.
Table 2
SM5]5
ROM
RAM
Instruction set
Power supply
Instruction cycle
System clock
Ports
R IOj-RI3j*
Ports
2 0 -2 9
Operating temperature
Package

98

SM5]6
8.I92X9 bits
256 X 4 bits
94 set

+4.5 to +5.5V
2.5 p.s (MIN.)
50 to 400kHz (3I2.5kHz TYP.)

+2.7 to +5.5V
2ps (MIN.)
50 to 500kHz

High voltage (-40V) I/O ports

I/O ports with a pull-down resistors

Highvotage (-40V) output ports

putput ports with a pull-down resistor

-IOto+80"C
64-pin SDIP
64-pin QFP

4-Bit Microcomputer (VFD Driver)
4-Bit Microcomputer (Controller with AID Converter)

•

SM5J5
SM5J6 .

System Configuration Example

Control input or
analog input

Serial clock

Serial input

SM5J5/SM5J6

v osp/v0 0 " - - - ' - - - - - - - '
Voo··-~--_I

Crystal
320768kHz 56kO

IMO

·SM5J5: VDSP= - 30V (TYPo)
SM5J6: VDD =+5V (TYPo)

-40.0
D

SM530

4-Bit Microcomputer (LCD Driver)

SM530
•

4-Bit Microcomputer (LCD Driver)

Description

The SM530 is a CMOS 4-bit microcomputer,
operated on a single 1.5V power supply with a 1.5
f1- A power consumption in standby mode. This
microcomputer integrates a 4-bit parallel processing function, a 2K byte ROM, an 88 word RAM, a
96-segment LCD driver, a real-time counter circuit, and a melody generator circuit in a single
chip. Provided with 1.5V single power supply and
a low power consumption design, it is applicable to
compact systems required for battery back-up operation.

•

•

Pin Connections
~

~

z

~ .. ~ ~ .. M~~d<~:E @~;j ~;: ~ ~ ~ ~

OOOO~~OO~~0»O>~OOOOO
59
57 56 5 54 3
51 5 9 4
4 44 4 42 41 40

3giQlB
380,8
3704 B
360lA
O'A
3403A

O'A
32019
31029
0,9

0.,

Features
1.
2.
3.
4.
5.
6.
7.

CMOS process
ROM capacity: 2,016X8 bits
RAM capacity: 88 X 4 bits
Instruction set: 49
Subroutine nesting: 1 level
Instruction cycle: 91.6 f1- s (TYP.)
Input/output ports
Input ports: 9
Output ports: 8
LCD output ports: 48 for segment
2 for common
Melody output port: 1
8. On-chip clock divider
9. On-chip crystal oscillator (32.768kHz)
10. Programmable interval timer
(10 se,c, 1 sec, 1/2 sec, 1110 sec)
11. 11100 sec counter
12. Melody generator circuit
13. Standby function
14. Single power supply: -1.5V (TYP.)
15. 80-pin QFP (QFP80-P-1818)

100

3.456789101112134567181

4-Bit Microcomputer (LCD Driver)

•

SM530

Block Diagram

ROM
(2.016X8)

RAM
(4X16x4)

Symbol description
ALU
: Arithmetic logic nuit
DDC
Ace
: Accumulator
DlV
ACL
: Auto clear
CG
C
: Carry FIF
BA
Pli. PL
: Program counter
BM • BL
S'T. SL
: Stack register of program counter

•

: LCD supply voltage generator
: Divider
: Clock generator
: Battery alarm circuit
: RAM address register

Pin Description
Symbol
K1 -K 4• KE 1 -KE 4
Sl-S4. F 1 -F 4
OlO-0 4B
H 1 -H 2

OSCIN • OSC OUT
SO
ACL
BA
Vee. DDC. VDD
VM• GND
Test

110
I
0
0
0

Circuit type
pull-down

0
I
I

Pull-down

I

Pull-down

Function
Input ports
Output ports
Segment signal output ports
Common signal output ports
Crystal oscillator
Melody output port
Auto clear input port
Battery alarm input port
Power supply for booster circuit
Power supply
Test input (normally connected to V M)

. . . - . - . - - - - ' - - - - - - S H A R P -~-.-..-.---..-.
101

SM530

4-'-Bit Microcomputer (LCD Driver)

•

Absolute Maximum Ratings
Parameter·

Symbol

YM
Pin voltage
Operating temperature
Storage temperature
Note 1:
Note 2:
Note 3:

•

Voo
VIN1
V1N2
Topr
Tstg

Rating.
-2.0 to +0.3
-4.0 to +0.3
VM -O;3 to +0.3
Voo-0.3 to +0.3
o to +50
-20 to +70

Unit
V
V
V
V
'C
'C

Note
1
1,2
1,3
1

The maximum applicable voltage on any pin with respect to GND.
Applied to pins Kr-K4, KE I -KE 4, SI-S4, F I -F4, SO, Test, DOC, !lA, ACL, OSCIN,
OSC OUT'
Applied to pins O'i (i=1 to 4, j=O to B) Hlo H2• Vee.

Recommended Operating Conditions
Parameter
Supply voltage
Oscillation start voltage
Oscillator frequency
Note 1:

•

Symbol
VM
Voo
. Vase
fose

Rating
-1.8 to-'--1.2
-3.6 to -2.3
-1.4
32.768(TYP.)

Note

1

Oscillation circuit constants: CG =15pF, Co =22pF
The oscillation start time should be within 10 sec.

(V M =-1.45 to 1.55V, Voo =-2.9 to -3.1V, Ta=25'C)

Electrical Characteristics
Parameter
Input voltage
Input current
Boost output voltage

Output current

Current consumption
Oscillation start time
Note 1:
Note 2:
t:/ote 3:
Note 4:
Note 5:
Note 6:
Note 7:
NoteS:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:

UIiit
V
V
V
kHz

Symbol
V!H
V1L
I!H1
1m2
VOO1
VOO2
101
102
103
104
IOHl
lOLl
IOH2
101.2
IOH3
IOL3
105
100
los
tosc

Conditions

VIN=OV
VIN=OV
VM =-1.55V,R L =5M.o .
VM =-1.30V, RL =5M.o
Vos=0.5V
Vos=0.5V
Vos=0.5V
Vos=0.5V
VouT =-0.5V
VOUT =V M +0.5V
VouT =-0.5V
VOU i=V M +0.5V
VouT =-0.5V
VOUT =V M +0.5V
Vos=0.5V
During full-range operation
During system clock stop

Applied to pins KI -K 4, KE I -KE 4, Test, ACL, OSC'N
Applied to pins KI-K., KE I -KE 4, ACL
Applied to pin Test
Applied to pin Voo
Applied to pins O'j (i = 1 to 4; j =0 to B)
Applied to pins Hlo H2
Applied to pin DOC
Applied to pin Vee
Applied to pin SO
Applied to pins SCS4
Applied to pin F I
Applied to pins F 2 -F4
Current consumption at 32.76SkHz .
.oscillation circuit constant, CG =15pF, Cp =22pF

MIN.
-0.5

TYP.

MAX.
VM +0.5
3
30
'-2.80
-2.30

0.155
1.55

Note

flA
flA

2
3

V
V

4

12
1.5

flA
flA
flA
flA
flA
flA
flA
pA
flA
flA
flA
flA
flA

10

s

10

60
60
120
160
10
10
1.5
100
3
100

1

5
6
7
8
9
10
11

12
13
14

.~-----.------GND
------ V M
..
--~----VIlIl

Cc =15pF.C n =22pF

Oscillation circuit

C, =C2 =C 3 =O.1,uF

Boost circuit

-'-~-'-"';'---SHARP----~

102

Unit
V
V

___ -,

i~

l~

SM530

4-Bit Microcomputer (LCD Driver)

•

Hardware Configuration
16 X 4 + 2 X 12 X 4, and its address is specified by
the data address registers (BM' BLl. The BM is used
to specify the file in the data memory, and the BL
used to specify the word within a file.
2 files (BM = 4 to 7) of data memory are allocated
to the display RAM. The data set herein is loaded
into the LCD segment pins. Fig. 2 shows the RAM
configuration.

(1) Program memory (ROM)
The on-chip ROM has a configuration of 32
pages X 63 steps X 8 bits (see Fig. 1).
The program counter consists of a 5-bit page
address counter (PU) used to specify the pages 0 to
31, and a 6-bit polynomial counter (PLl used to
specify the steps 0 to 62.
The stack register is an 11 bit register which
allows 1 level of subroutine nesting.

(3) K1-~' KE 1-KE4 ,BA (Inputs)
Ports K and KE are 4-bit input ports with pull-down resistors. The contents of these pins can be
loaded into the accumulator Ace by instructions.

(2)

Data memory (RAM) and data address
register (B M , Bd
The data memory has a 352 bit organized as 4 X
PUs,PU,

01

00

PU,-PU,

11

10

000

8
Page 0
Note 1 and 4

16

24

001

1

9

17

25

010

2

10

18

26

11

19

27

12

20

28

13

21

29·

22

30

23

31

Note 4
Note 4

011

3
Note 4

100

4
Note 4

101
110
111

5
Note 4

14

6
Note 4
7

Note 3
15

Note 4
Note
Note
Note
Note

1:
2:
3:
4:

Note 2

Page 0: The address where the clock restarts from the standby mode.
Page 15: The starting address with the ACL.
Page 14: Subroutine cover page
Pages 0 through 7: The address which allows a jump by the JUMP instruction. PL6 =0

Fig. 1
3

ROM configulation
8

ABC

D

E

F

!
3
4, 6'
5, 7'

Note: The shadowed area is allocated for a display RAM.
Executing the SABM instruction at the file 2 or 3 of the BM register specifies the file 6 or
7 of the BM in the same location of the file 4 or 5.

*

Fig. 2

RAM configuration

.....-..--....----------SHARP - . - . . - - - - - - - - 103

SM530

4.,.Bit Microcomputer (LCD Driver)

While in standby mode, if the K or KE pin ac
cepts an input signal, the CPU is initialized and sta
rts execution of the program at PU=OH, PL =OOH.
The BA pin can be used as an input pin which
allows testing the input fixed at High or Low, by
instructions.
(4) F1-F4 , 8 1-8 4 (Outputs)
Ports F and S are 4-bit output ports.The accumulator Ace can be transferred to these ports by
instructions.

1/2 duty and 1/2 bias scheme.
Fig. 3 shows the common and segment waveform.
The display frequency is 128Hz, and 3V of display
voltage is obtained through an internal booster circuit.
The display data is transferred through an LCD
driver circuit, and displayed on an LCD screen.
Fig. 4 shows an example of a seven-segment
numeric LCD digit. The RAM data of BM=4, 6 corresponds to the Hl segment, and BM=5, 7 corresponds to the H2 segment.

(5) Divider and clock counter
The device contains a real-time clock divider, 1
sec counter and 1/100 sec counter. These counters
generate signals of 10 sec, 1 sec, 112 sec, 1110 sec
which can be tested by instructions, and constitute
a real-time clock.
Either 1 sec counter or 11100 counter can be
directly indicated on an LCD screen through a decoder. The contents of 11100 sec counter can be
loaded into the accumulator Ace by instructions.
(6) LCD driver
The SM530 contains an on-chip LCD driver
which can directly drive a 96-segment LCD with a

(j=O-9)

Fig. 4

7-segment numeric LCD digit

--------------GND
----------VM
----------vnn

H2
--------vnn

----'-------GND
0;;

----- ------vnn

-- ~~~J-~-----~1;V

O;;-H,
(selected)

_ _

_ _ }-=-5Y--, -OV
-

1.5V

----

3V

---------- -

I_ ++·1 ·1· ·1
OFFONOFFONOFF

fE------'OFF--~----

Fig.3

104

- - - - - ---

LCD driving signal waveform

4-Bit Microcomputer (LCD Driver)

SM530

in two octaves from the SO pin.
The tone length can be selected between 250ms
and 125ms depending on the melody ROM. The
melody ROM provides a pause and a stop instruction.
Controlling the melody F IF (ME F IF) by instructions starts and stops melody. The melody
ROM stores up to 256 steps of musical notes.
Table 2 shows the musical scales in one octave.
Executing an instruction from a melody ROM outputs half frequencies of the standard frequencies
shown in table 2, and generates lower 12 musical
scales by one octave.

(7) Display decoder
The 1 sec counter or 11100 sec counter is
loaded into the display decoder, and output as segment signals through pins 010 -040 , The display
decoder can not be used when the RAM data is displayed on an LCD.
Fig. 5 shows the relationship between the display RAM and pins Oij. Table 1 shows the truth
table of the display decoder.
Table 1 Display decoder truth table
lset or 1/IOOsec
counter

Display
character

lsec or I/I00sec
counter

0000

n

0101

,,

LI

0001

0011
0100

e-:J

,-,,

U

0111

:,

1000

U

1001

I]

,-,

L'

:r

I

Note:

(9) ACL circuit
The ACL circuit contains a resistor and a capacitor, which does not require any external circuits.
The ACL may be cleared with the interval of about
0.5 sec after a crystal oscillator circuit starts
oscillation when the power is turned on, and starts
execution of the program at Pu=F H, PL =OOH'

C

0110

2-,

0010

Display
character

(10) Standby mode
Executing an instruction places the device in
standby mode. In this mode, the system clock is inactivated to reduce power consumption. While in
standby mode, if the K or KE pin receives an input
signal, or the selecting Y F IF is set, the device exits standby mode and the CPU starts execution of
the program at PU=OH, PL =OOH'

The display segment of a floating point is specified by
the first bit of a display RAM (BM' Bc)=(5, 0)

(8) Melody generator circuit
The contents ·of a melody ROM can be output
with standard 12 musical scales (555 to 2114Hz)

~L

1

2

3

4, 6

.,.

...

5, 7

...

...

.,.
...

0

4

r--

+
1 sec counter .....

1'

7

...

...

...
..,

8

9

A

'"

...

...

B

.. .

.. .

.. ,

.. .

...

(HI)

~.)" 7

7~

I-<

OJ
"Cl
0

u

~

»

1/100 sec
counter -'>

6

...

I(H 2 )

(HI)

(H 2 )

5

.- .

-a'"

a

I-<

!

OJ

.i':::

.e
Ci
U
...l

Ci

~

JJ
0'0

~

(i = lto 4)

Fig. 5

(i=lto4, j=ltoB)

Display RAM and Oij

- - - - - - - - - - - - S H A R P - - - - - . - - . - .......... - - - - 105

.SM530

4:"B!t Microcomputer (LCD Driver)

Table2
Musical
scale
Frequency
(Hz)

do#

re

re#

mi

Melody output frequency
fa

fa#

so

so#

La

La#

si

do

1110.8 1170.3 1236.5 1310.7 1394.4 1489.5 1560.4 1680.4 1771.2 1872.4 1985.9 2114.1

(11) Booster circuit
The device contains a booster circuit which
generates a voltage two times higher than the 1.5V
pow~r supply.
Then, it is necessary to apply external capacitors
betweeri DDC pin and Vee pin as well as VDD pin
and GND (see Fig. 6).

(12) System clock
The system clock has a frequency of one third
that of a 32.768kHz clock.
The instruction cycle time should be 91.5 p s.

DOC
Vee

LSI

C1 =O.lpF(TYP.)

V DD

J; G.=O.lpF(TYP.)
Fig. 6

Booster circuit

,

I',

106

\~

4-Bit Microcomputer (LCD Driver)

SM530

Instruction Set

•
(1)

RAM address instructions

Mnemonic Machine code
INCB

4C

DECB

4D

LB xy

30-3F

LBL xy

6B
OO-FF

SABM

72

SABL

73

EXBL

5A

Operation
BL +-BL +1
skip if BL = 7 or F
BL +-B L-1
skip if BL =0
BM3+-0
BM2• BMI +-X(i4. 13)
BL4 • BLl +-y(12. II)
BL3 • BL2+-(1. 1)
BM+-x(1 7 -1 5)
BL+-y(1 4-ld
BM3+- 1
next step only
BL4+-1
next step only

(3)

Mnemonic Machine code
Operation
10-lF
LAX x
A cc +-x(1 4-11)
LDA x

20-23

EXC x

24-27

EXCI x

28-2B

EXCD x

2C-2F

DTA

52

ROM address instructions

Mnemonic Machine code
Operation
80-BF
P L-x(1 6-11)
TR x
60-67
P U-x(l l l -1 7)
TL xy
OO-FF
P L-y(1 6-ld
P u -011l0. P L-x(1 6-ld
CO-FF
TRS x
SR+-PC+ 1
P U5 • PU4+-(0. 0)
JUMP xy OO-FF

ATPL
RTN

6A
68

RTNS

69

Ace+-M
BM2• BMI +-BM2• BMI ffiX(l2. Id
Acc- M
BM2• BMI +-BM2• BMI ffix(iz. II)
Aee+-+ M
BM2• BMI+-BM2.BMlffix(12. II)
BL+-BL +1
skip if BL =7 or F
Aee+-+ M
BM2• BMI +-BM2.BMI ffix(1 2• II)
BL+-BL -1
skip if BL =0
Acc+-lilOO SEC. C.

Aee+-+BL

(4)
(2)

Data transfer instructions

PU3-PUI-X(16. 18 • 17)
P L6 +-O
P L5 -P Ll -y(1 5-11)
P L4 - P Li +-Aee
PC-SR
PC-SR
skip the next step

Arithmetic instructions

Operation
Mnemonic Machine code
54
ADD
Aee+-Aee+ M
Acc"':'Aec+ M + C
C+-C 4
55
ADDC

ADX x

OO-OF

COMA

53

(5)

skip if C 4 =1
Aee+-Aec+ x(i4-11)
skip if C 4 =1
Ace-Ace

Test instructions

Mnemonic Machine code
48-4B
TM x
5B
TC
TAM
59
TABL
58
TG x

6C-6F

TBA

79

skip
skip
skip
skip
skip

if
if
if
if
if

Operation
Mi=1 (i=1 211)
C=O
Aee=M
Acc=BL
Y =1. Y+-O

(Y IOS• YIS • YO. 5S• YO•IS)
skip if BA=l

---'--~--SHARP~'---'-'-'--

107

SM530

4-Bit Microcomputer (LCD Driver)

(6)

Bit manipulation instructions

Mnemonic
RM x
SM x
RC
SC

(7)

Machine code
40-43
44-47
56
57

Operation
Mi ...... O (i=I 2 I 1 )
Mi ...... l (i=I2Id
C...... O
C...... l

(8)

Melody instructions

Operation
Mnemonic Machine code
78
PRE x
Melody ROM pointer preset
OO-FF
SME
77
ME""" 1
ME ...... O
RME
76
skip if MES=1
TMEL
75
MES ...... O

I/O instructions

Mnemonic
KTA
KETA
ATS
ATF
ATBP
SDS
RDS

Operation
Machine code
50
Acc ...... K
51
Acc ...... KE
S...... Acc
5C
F ...... Acc
5D
BP ...... Acc
5E
DS ...... 1
4F
DS ...... O
4E

(9)

Special instructions

Mnemonic Machine code
Operation
74
System clock stop
CEND
DlV ...... O
IDIV
70
1 SEC; C....... O
11100 SEC. c. ......0
INIS
71
No operation
00
SKIP

'--~-----SHARP--------

108

SM530

4-Bit Microcomputer (LCD Driver)

•

System Configuration Example (Calculator watch)

LCD
DC voltage cutout
O.02pF

a i ; (48 line)

aSCouTI-~--I

Test
gj

F,

asclN

"0

F2

ACL

F3

BA

Q)

~0
U

....
0

~

0

F•
SM530

SO

O.22pF

GND
VM

+
IpF

DOC
O.lpF
Vc

Key matrix

---.-..-.----.-.a.-,-SHARP - - - . - . - - - - - 109

SM531

4-Bit Microcomputer (LCD Driver)

SM531
•

4-Bit Microcomputer (LCD Driver)

Description

•

Pin Connections

The SM531 is a CMOS 4-bit microcomputer,
operated on a single 1.5V power supply with a
1.5 f1 A power cosumption in standby mode. This
microcomputer integrates a 4-bit parallel process·
ing function, a 1.2K byte ROM, a 52 word RAM, an
80-segment LCD driver, a real-time counter circuit, and a melody generator circuit in a single
chip. Provided with 1.5V single power supply and
a low power consumption design, it is applicable to
compact systems required for battery back-up operation.

•

Features
1.
2.
3.
4.
5.
6.
7.

8.
9.
10.
11.
12.
13.
14.
15.

CMOS process
ROM capacity: 1,260X8 bits
Rj-\M capacity: 52 X 1 bits
Instruction set: 45
Subroutine nesting: 1 level
Insturction cycle: 91.6 f1 s (TYP.)
Input/output ports
Input ports: 6
LCD output ports: 40 for segment
2 for common
Melody output ports: 2
On-chip clock divider
On-chip crystal oscillator (32.768kHz)
Programmable interval timer
(1 sec, 1/2 sec, 1110 sec)
11100 sec counter
Melody generator circuit
Standby function
Single -power supply: -1.5V (TYP.)
60-pin QFP (QFP60-P-1414)

Top View

-~----~~--SHARP,"""""'----""""'--'-'-'-

110

4-Bit Microcomputer (LCD Driver)

•

SM531

Block Diagram

Voo

DDC

ROM

DDC

(1,260XS)

Vee
RAM
(2x16X4)

Pu(5)

'--.,---/

GND

VM

Symbol description
AL U
: Arithmetic logic unit
Ace

: Accum1:l1ator

ACL
C
Pt!, PL

: Auto clear
:CarryF/F
: Program counter

OSCIN OSCOUT '

Test
Su, SL
DDC
DIV

: Stack register of program counter
: LCD supply voltage generator

CG
BM,B L

: Clock generator
: RAM address register

: Divider

•. Pin Description
Symbol
K1 -K 4 , KEto KEz
0 10 -0 49
HI-Hz
OSC 1N • OSC OUT
SOl> S02
ACL
BA
Vee, DDC. VDD
V M• GND
Test

I/O
I

Circuit type
Pull-down

0
0
O.
I
I

I

Pull-down

Function
Input ports
Segment signal output ports
Common signal output ports
Crystal oscillator
Melody output ports
Auto clear input port
Battery alarm input port
Power supply for booster circuit
Power supply
Test input (normally connected to V M)

-------------SHARP'.------------111

4-Bit Microcomputer (LCD Driver)

•

SM531

Absolute Maximum Ratings
Parameter

Pin voltage
Operating temperature
Storage temperature
Note 1:
Note 2:
Note 3:

•

Symbol
VM
VDD
VINI
VIN2
Topr
Tstg

Rating
to +0.3
~4.0 to +0.3
VM~0.3 to +0.3
VDD~0.3 to +0.3
o to +50
~20 to +70
~2.0

Unit
V
V
V
V
·C
·C

Note
1
1
1,2
1,3

The maximum applicable voltage on any pin with respect to GND.
Applied to pins KI -K 4 , KElo KE 2 , SOlo SO" Test, DDC, ACL, OSC IN , OSC OUT '
Applied to pins Oi; (i= 1 to 4, j=O to 9), HI, Hz, Vc.

Recommended Operating Conditions
Parameter
Supply voltage
Oscillation start valtage
Oscillator frequency
Note 1:

•

Symbol
VM
VDD
Vase
fose

Rating
to ~1.2
~3.6 to ~2.3

~1.8

~1.4

32.768 (TYP.)

Parameter
Input voltage
Input current
Boost output voltage

Symbol
VIH
V1L
IIBI
IIH2
VDDI
VDD2
101
102

Output current

103
10 •
105

Current consumption
Oscillation starting time
1:
2:
3:
4:
5:
6:
7:

Note

1

Oscillation circuit constant, Cc =15pF, Co =22pF.
Oscillation start time: within 10 seconds.

(VM=~1.45

Electrical Characteristics

Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note

Unit
V
V
V
kHz

100

los
Tose

to

~1.55V, VDD=~2.9

Conditions

MIN.

TYP.

to -3.1V, Ta=25·C)

MAX.

~0.5

0.155
1.55

VIN=OV
VIN=OV
VM =-1.55V, RL =5M!1
VM=-1.30V, RL =5M!1
VDs =0.5V
VDs =0.5V
VDs =0.5V
VDs =0.5V
Vos=0.5V
During full-range operation
During system clock stop

Applied to pins KI - K4 , KE,- KE 4 , ACL, OSC 1N
Applied to pins KI -K 4 , KE,-KE 4 , ACL
Applied to pin Test
Applied to pin Voo
Applied to pins Oi; (i= 1 to 4, j=O to 9)
Applied to pins HI> H,
Applied to pin DDC
8: Applied to pin Vee
9: Applied to pins SOh SO,
10: Current consumption at 32.768kHz
11: Oscillation circuit constant, Cc =15pF, Co =22pF

VM+0.5
3
50
~2.80

-2.30
10
60
60
120
900
10
1.5
10

Unit
V
V
pA
pA
V
V
pA
pA
pA
pA
pA
pA
pA
s

~ ------ V

Note
1
2
3
4
5
6
7
8
9
10

11

-----:-------GND

,

M

-------VIlIl
• H" H2 waveforms

OSC 1N

Cc

OSCOUT

fr.YD~

'Co~

Cc =. 15pF, C n =22pF

CI =C2 =C3 =O.l,uF

• Oscillation circuit

• Boost circuit

- -......... -'.----.--SHARP~----,--112

SM531

4-Bit Microcomputer (LCD Driver)

•

Hardware Configuration
(2)

Data memory (RAM) and data address
register (B M , Bd
The data memory has a 208-bit organized as 2
X 16 X 4 + 2 X 12 X 4, and its address is specified
by the data address registers (BM, Bd. The BM is
used to specify the file in the Qata memory, and the .
BL used to specify the word within a file.
2 files (BM = 2, 3) of data memory are allocated
to the display RAM. The data set herein is loaded
into the LCD segment pins. Fig. 2 shows the RAM
configuration.

(1) Program memory (ROM)
The on-chip ROM has a configuration of 20
pagesX63 stepsX8 bits (see Fig. 1). The program
counter consists of a 5-bit page address counter
(PU) used to specify the pages 0 to 19, and a 6-bit
polynomial counter (Pd used to specify the steps 0
to 62.
The stack register is an 11-bit register which
allows 1 level of subroutine nesting.

~PU~PtX:
000
001

01

00

Ua-P

10

8

16

Note 1 and 4
1
9

17

Page 0

Note 4
010

2

10

18

11

19

Note 4
011

3
Note 4

100

12

4
Note 4

101
110

13

5
Note 4

14

6

Note 4
'111

Note 3
15

7
Note 4

Note 2

Note 1:

Page 0 shows the address where the clock restarts from
the standby mode.
Note 2: Page 15 shows the starting address with the ACL.
Note 3: Page 14 shows the subroutine cover page.
Note 4: Pages 0 through 7 show the addresses which allow a
jump by the JUMP instruction, PLS = O.

Fig. 1 ROM configuration

A

Note:

B

c

D

F

The shadowed area is allocated for a display RAM.

Fig. 2 RAM configuration

113

SM531

4-Bit Microcomputer (LCD Driver)

(3) K1-K4 , KE 1, KE2 (Inputs)
Ports K and KE are 4-bit input ports with pull
-down resistors. The contents of these pins can be
loaded into the accumulator Ace by instructions.
While in standby mode, if the K or KE pin
accepts an input signal, the CPU is initialized and
starts execution of the program at P u = OH, PL =

OOH.
(4) Divider and clock counter
The device contains a real ~time clock divider
and a 11100 sec counter. These counters generate
signals of 1 sec, 1/2 sec, 1110 sec which can be
tested by instructions, and constitute a real-time
clock.
The 11100 counter can be directly indicated on
an LCD screen through a decoder. The contents of
1/100 sec counter can be loaded into the accumulator Ace by instructions.

(5) LCD driver
The SM531 contains an on-chip LCD driver.
which can directly drive an 80-segmentLCD with
a 112 duty and 1/2 bias scheme.
Fig. 3 shows the common and segment waveform.
The display frequency is 128Hz, and 3V of display
voltage is obtained through an internal booster circuit.
The display data is transferred through an LCD
driver circuit, and displayed on an LCD screen.
Fig. 4 shows an example of a seven-segment
numeric LCD digit. The RAM data of BM = 2 correspond to the H1 segment, and BM = 3 corresponds
to the H2 segment.

-------,-------GND
----------VM
----------Vnn
--- - --------GND
------------VM
--------Vnn
----------GND
------ ------Vnn

-- ~~~j-~------·-i;v.

Oij-H I
(selected)

_ _

_ _ }:.5.Y_ -OV
1.5V

- -------------

3V
-

I·OFF-I'ONOFFONOFF
"'·1 ·1· ·1
(not selected)

~~----~---'OFF------~---Fig. 3

LCD driving signal waveform

-..-..-.,-----~----SHARP-----·-.-.-.------

114

4-Bit Microcomputer (LCD Driver)

SM531

Table 1 Display decoder truth table
O2;

os;

1/100 sec counter

Display
1/100 sec counter
character

r,

,,

0000

L'

0001

:J
C

0010

-- ,

\

Fig. 4

7-segment numeric LCD digit

~L

'-'

Y

'-'
C,

1001

-'

The display segment of a floating point is specified by
the first bit of display RAM (B M • Bd=(3. 0)

2

3

5

6

7

8

9

...

...

...

...

...

5. 7

...

...

'"

'"

'"

...
...

...
.,.

0

~

»

'"
]Ci

0

'V

4

(Hz)

(HI)

....

~

j

:::l

8
....l

Ci

0;0"

(i = lto 4)

- Fig. 5

'"

(HI)

l~

Y

~

7

0;; (i

= lto4. j = lto9)

Display RAM and Oij

(6) Display decoder
The 11100 sec counter is loaded into the display
decoder, and output as segment signals through
pins 0 10 -0 40 , The display decoder can not be used
when the RAM data is displayed on an LCD.
Fig. 5 shows the relationship between the display RAM and pins Ojj. Table 1 shows the truth
table of the display decoder.
(7) Melody generator circuit

The contents of a melody ROM can be output
with standard 12 musical scales (555 to 2114Hz)
in two octaves from the SOl and S02 pins. The tone
length can be selected between 250ms and 125ms

1

II
I

1

.g

'jl

IJ

...

!

~.

0110

4. 6

(Hal

1/100 sec---llo
counter

Note:

S

1000

-'

0100

(j = Oto9)

0101

0111

:J

0011

\
H2 '----

Display
character

depending on the melody ROM. The melody ROM
provides a pause and a stop instruction.
Controlling the melody F IF (ME F IF) by instructions starts and stops the melody. The melody
ROM stores up to 128 steps of musical notes.
Table 2 shows the musical scales.in one octave.
Executing an instruction from a melody ROM outputs half frequencies of the standard frequencies
shown in the table 2, and generates lower 12
musical scales by one octave. Executing an instruction allows an envelope control for melodies. The
SOl output has an opposite phase with the S02
output.

......... --~--.--~SHA'RP'-.~--'-"'--115

SM531

4-Bit Microcomputer (LCD Driver)

Table 2 Melody output frequency
Musical
scale
Frequency
(Hz)

do#

re

re#

mi

fa

so

la

so#

la#

si

do

1110.8 1170.3 1236.5 1310.7 1394.4 1489.5 1560.4 1680.4 1771.2 1872.4 1985.9 2114.1

(8) ACL circuit
The ACL circuit contains a resistor and a capa·
citor, which does not require any external circuits.
The ACL may by cleared with the interval of about
0.5 sec after a crystal oscillator circuit starts
oscillation when the power is turned on, and statts
execution of the program at Pu=F H, P L =OOH'
(9) Standby mode
Executing an instruction places the device in
standby mode. In this mode, the system clock is in·
activated to reduce power consumption. While in
standby mode, if the K or KE pin receives an input
signal, or the selected r F IF is set, the device exits
standby mode and the CPU starts execution of the
program at PU=OH, P L =OOH'
(10) Booster circuit
The device contains a booster circuit which
generates a voltage two times higher than the 1.5V
power supply.
Then, it is necessary to apply external capaci·
tors between DDC pin and Vee pin as well as VDD
pin and GND (see Fig. 6) .

.-.. . . .
116

fa#

DDC
C1 =O.1,uF(TYP.)

Vee
LSI

VDD

J;
Fig. 6

C2 =O.1,uF(TYP.)

Booster circuit

(11) System clock
The system clock has a frequency of one third
that of a 32.768kHz clock.
The instruction cycle time should be 91.5 f1 s.

-~----SHARP-----,---

SM531

4-Bit Microcomputer (LCD Driver)

(4)

Instruction Set

•
(1)

RAM address instructions

Mnemonic Machine code
INCB

4C

DECB

4D

LBxy

30-3F

LBL xy

6B
OO-FF

SABL

73

EXBL

5A

(2)

Operation
BL-BL+1
skip if BL =7 or F
BL-B L-1
skip if BL =0
BM2• BM1 -x (14. 13)
BL4 • BLl -y (1 2.1 1)
BL3 • BL2 -(1. 1)
BM-x (17-15)
BL-y (1 4-1 1)
BL4 -1
next step only
Acc-B L

(5)

Test instructions

Mnemonic Machine code
48-4B
TM x
TC
5B
TAM
59
TABL
58
6C-6F

TG x

ROM address instructions

Mnemonic Machine code
Operation
80-BE
'P L-x (1 6 -lll
TR x
60-64
Pu-x (1 11 -1 7)
TL xy
OO-FE
P L-y (1 6 -1 1)
P u -01110. PL-x (1 6 -1 1)
TRS x
CO-FE
SR-PC+1
pus. P U4 -(0. 0) ,
P U3 - P U1 -x (Is. 18 • 17)
JUMP xy OO-FF
PLS-O
PLS-P Ll -y (Is-Ill
P L4 -P L1 -Acc
ATPL
6A
PC-SR
RTN
68
PC-SR
RTNS
69
skip the next step

(3)

Arithmetic instructions

Mnemonic Machine code
Operation
ADD
54
Ace-Acc+M
Acc-Acc+M+C
C-C 4
ADDC
55
skipifC 4 =1
Acc-Acc+x (14-11)
OO-OF
ADX x
skip if C4 =1
COMA
Ace-Acc
53

(6)

skip
skip
skip
skip
skip

if
if
if
if
if

Operation
Mi=l (i=1211)
C=O
Acc=M
Acc=BL
Y = 1. Y-O

(Y 15. Y 0.55. Y 0.15)

Bit manipulation instructions

Mnemonic Machine code
Operation
RM x
40-43
Mi-O (i=l)ll
44-47
SM x
Mi-l (i=I211)
C-O
RC
56
C-1
SC
57

(7)

I/O instructions

Mnemonic
KTA
KETA
ATBP
SDS
RDS

Machine code
Operation
Acc-K
50
51
Acc-KE
5E
BP-Acc
4F
DS-1
4E
DS-O

Data transfer instructions

Mnemonic Machine code
Operation
10-lF
Acc-x (1 4-1 1)
LAX x
Acc-M
20-23
LDA x
BM2• BM1 -BM2• BM1 E8x
Ace-M
24-27
EXC x
BM2• BM1 -BM2• BM1 E8x
Acc-M
BM2• BM1 -BM2• BM1 E8x
28-2B
EXClx
BL-B L+1
skip if BL =7 or F
Acc-M
BM2• BM1 -BM2• BM1 E8x
EXCD x 2C-2F
BL-BL-1
skip if BL =0
DTA
52
Aec-11100 SEC. C.

(8)

(1 2• 11)
(1 2• III
(1 2• 11)

(9)
(12• II)

Melody instructions

Mnemonic Machine code
Operation
78
Melody ROM pointer preset
PRE x
OO-FF
ME-1
SME
77
RME
ME-O
76
skip if MES= 1
TMEL
75
MES-O

Special instructions

Mnemonic
CEND
IDIV
INIS
SKIP

Machine code
Operation
74
System clock stop
DIV-O
70
11100 SEC. C.-O
71
No operation
00

-~-------SHARP""-''-'----'''-'---

117

SM531

4-Bit Microcomputer (LCD Driver)

•

System Configuration Example (Melody alarm watch) .
LCD

Sun Mon Tue Wed

Thu

Fri

Sat

PM

DC voltage cutout
0.021lF

Oij (40 lines)

OSCOUTI---.---u--'-----,

Sound
generator

OSC lN I----+-----,IF---+
15pF
IIlF

SOl

=
SO,

+

SM531

1.5V
V M !--------1It-----+

VDDI-------1
DDC

Vc
GND

ACL

ACL

118

SM500

4-Bit Microcomputer (LCD Driver)

SM500
•

4-Bit Microcomputer (LCD Driver)

Description

•

Pin Connections

The SM500 is a CMOS 4-bit microcomputer
which integrates a 4-bit parallel processing function, a l,197-byte ROM, a 40-word RAM, a
15-stage divider and a 56-segment LCD driver
circuit in a single chip_ This microcomputer is applicable to LCD systems with low power consumption and reduced cost.

•

o
6c3c5c58~c3c5cS8c3C§
2

Features
1.
2.
3.
4.
5.
6.
7.

CMOS process
ROM capacity: 1,197 X 8 bits
RAM capacity: 40 X 4 bits
Instruction set: 52
Subroutine nesting: 1 level
Instruction cycle: 61 p s (TYP.)
Input/output ports
I/O ports: 8
(for switching with segment pin)
Input ports: 6
Output ports: 4
LCD output ports: 28 for segment
(including 8 110 ports)
:2 for common
8. On-chip divider circuit for clock
9. On-chip crystal oscillatot circuit
10. LCD driver circuit
(56-segment, 112 bias, 1/2 duty)
11. Standby function
12. Single power supply: -3V or -5V (TYP.)
.13. 48-pin QFP (QFP48-P -1010)

a••
03.

Top View

119

4-Bit Microcomputer (LCD Driver)

•

SM500

Block Diagram

ROM
(1,197XS)

~

u

if)

5

0

U

°2
Symbol description

ALU
Ace

ACL
C
C A , Ca, Pu, PL
Cs Su, Su

CG
DIV

120

: Arithmetic logic unit
: Accumulator
: Auto clear
: Carry FIF
: Program counter
: Stack register of program counterr
: Clock generator
: Frequency divider

W j -W 4 , Wj'-W:
B M• BL

Bp
KF
Ks
S
K

: Static shift register
: RAM address register
: Backplate signal generator circuit
: 4-bit F IF
: 4-bit FIF
: 4-bit FIF (status register)
: Key input F IF

4-Bit Microcomputer (LCD Driver)

•

SM500

Pin Description
Symbol
K1-K 4
a, {3
0 11 -0 41
OSI-0S4
01Z-046
Ht. Hz
R1-R4
T
ACL
OSC IN , OSC OUT
VM
Voo, GND

•

I/O
I
I
I/O
I/O
0
0
0
I
I

Circuit type
Pull down
Pull up

Pull up
pull down

Function
Acc+--K 1-K 4
Independent test possible
Wand W' registers output or input/output to/from KF register
Wand W' registers output or input/output to/from Ks register
Wand W' registers output; used for LCD segment output
3-state level output possible; used for LCD common output
R1-R 4 +--Acc
For test (Connected to GND normally)
Auto clear
For clock oscillation
Power supply for LCD driver
Power supply for logic circuit

Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note 1:

•

Symbol
Voo
VM
VIN
VOUT
Topr
Tstg

Rating
-6.0 to +0.3
Voo to +0.3
Voo-0.3 to +0.3
Voo-0.3 to +0.3
-20 to +70
-55 to +150

Unit
V
V
V
V

Note

1

·C
"C

The maximum applicable voltage on any pin with respect to GND.

Recommended Operating Conditions
(1)

Parameter
Supply voltage
Oscillator frequency
Oscillation start voltage

(2)

(GND=OV)

3V power supply specification
Symbol
Voo
VM
fose
Vose

Rating
-2.7 to -3.3
VoD/2 (TYP.)
32.768 (TYP.)
-2.7

Supply voltage
Oscillator frequency
Oscillation start voltage
Note1:

Symbol
Voo
VM
fose
Vose

Note

1

(GND=OV)

5V power supply specification
Parameter

Unit
V
V
kHz
V

Rating
-4.5 to -5.5
Voo /2 (TYP.)
32.768 (TYP.)
-4.5

Unit
V
V
kHz
V

Note

1

The oscillation start time should be within 10 sec.

'-"-'~---'-'--SHARP----"-'------

121

4-Bit Microcomputer (LCD Driver)

SM500

Electrical Characteristics

•
(1)

Parameter
Input voltage

Input current

Output voltage

Output current

Supply current

(2)

(VDD= -3.0V± 10%, GND=OV, Ta= -20 to +70"C)

3V power supply specification
Symbol
VIH
V IL
IHl
1HZ
IL3
V OA
V OB
Voc
IOHl
lOLl
10H2
IOL2
103
104
IDA
IDS

Conditions

VIN'=OV
VIN=OV
VlN=VbD
-0.3
V M -0.3

No load V M =V DD /2
VoUT =-0.5V
VOUT=VDD+0.5V
VouT =-0.5V
V OUT =V DD +0.5V
V Ds =0.3V
V Ds=0.5V
During full-range operation
When system clock is stationary

Input voltage

Input current

Output voltage

Output current

Supply current
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:·
Note'lO:

Symbol
VIH
V 1L
IH'
IH2
IL3
V OA
V OB
Voc
10llI
lOLl
IOH2
10L2
103
104
IDA
IDs

MAX.
VDD +0.6
15
3
1
V M +0.3
V DD +0.3

Unit
V
V

Note

fLA
fLA
fLA

2
3

1

4

V
V
V

5

fLA
fLA
fLA
fLA
fLA
fLA
fLA
fLA

30
10
100
10
100
100
20
3

6
7

8
9
10

(VDD= -5.0V± 10%, GND=OV, Ta= -20 to +70°C)

5V power supply specification
Parameter

TYP.

MIN.
-0.6

Conditions

TYP.

MIN.
-0.6

MAX.

Unit
V
V

Note

fLA
fLA
fLA

2
3
4

VM +O.4
V DD +O.4

V
V
V

5

100
30

fLA
fLA
fLA
fLA
fLA
fLA
fLA
fLA

V DD +0.6
50
10
3

VIN=OV
VIN=OV
V1N=VDD
-0.3
V M -0.3

No load V M =V DD /2
V OlJT =-0.5V

35
12
120
12
120
120

VOlJT=VDD+0.5V
VollT =-0.5V
VOUT=VDD+0.5V
V Ds =0.3V
V Ds =0.5V
During full-range operation
When system clock is stationary

Applied to pins K,-K., a, (3, ACL, aI', 0 21 , 0 31 , 0", OS,-OS4
Applied to pins K,-K., 0 11 , O2 ,, 0 3 " 0,,, Os,-Os.
Applied to pin ACL
Applied to pins a, (3
Applied to pins H" Hz
Applied to pins OJ; (i = 1 to 4; j = 2 to 6)
Applied to pins 0" -04" OSl-0S.
Applied to pin RI
Applied to pins R2 , R3 , R,
fosc=3Z.768kHz, supply current with no load, oscillator
circuit' parameter: CD = Cc = ZZpF

50
10

~

1

6
7

8
9
10

-----------VOA

,

- - - - - - VOB

-------Voc

Fig. 1
OSC IN

Cc

H1, H2 waveforms
OSCOUT

r'~
CDl
,

ACL

O.l1;ol,uF

1
I

Cc = 15pF, CD =22pF

Fig. 2

Oscillator circuit

Fig. 3

ACLcircuit

-------~~'----SHARP -~--.-.----

122

4-Bit Microcomputer (LCD Driver)

SM500

.-..-..-..-.-..-..-.-..-.-.-.-..-.-.-.-..-.-.
•

Pin Functions

(1) Kl-~ (Inputs)
The K1-K 4 are 4-bit parallel input ports which
are connected to the accumulator Acc. The contents
of the K1- K4 are loaded into the Ace by the KT A
instruction.
When a system clock is inactivated, if a High
level signal is input to anyone bit of ports KCK4,
the system clock restarts, and the program counter
starts at page 0, step 0.
(2) 0:. 13 (Inputs)
The input ports a and f3 can be independently
tested by the T A and TB instructions respectively.
These ports are pulled-up to the High level within a chip.
(3) R1-R 4 (Outputs)
The R1-R 4 are 4-bit parallel output ports which
generate the data stored in the R register.
The R register is connected to the accumulator
Ace. The contents of the Acc are loaded into the R
register by the ATR instruction, which can be output at ports R 1-R 4.
The R1 of the R register performs, in conjunction
with the f1, f4 or f lZ of a divider, the logical product. It can also provide an alarm output.

(4) H2 , Hl (LCD common outputs)
The Hz and HI pins are used to drive the common of an LCD with a 112 duty, 112 bias scheme,
and provide a 3-level output.
The display can be turned on or off by the common outputs with the BP register.
(5) 011 (Segment output ports)
The segment output ports Oij (i = 1 to 4, j = 2 to
6) consist of 20 bits, which are used to output the
contents of W' and W registers for the display on
or off with the BP register.
(6) 0 11 , 0 21 • 0 31 , 0 41 (Input/output ports)
The I/O ports 0 11 -0 41 are used as segment output ports to generate the contents of W' and W registers with the S register. The I/O ports can also
be used as output ports as well a.s input ports for
the KF register. After ACL. operation, it should be
input ports with pull-down resistors.

(7) OSl, 0 52 , 0 53 • 0 54 (Input/output ports)
The I/O ports OSl -OS4 are used as segment output ports to generate the contents of W' and W registers with the S register. The I/O ports can also
be used for output ports as well af input ports for
the Ks register. After ACL operation, it should be
input ports with pull-down resistor.

....-.-.---------SHARP---.----~

123

4-Bit Microcomputer (LCD Driver)

•

SM500

Field

Hardware Configuration

(1) Program mernory(ROM)
The on-chip ROM has 1,197 bytes organized as
19 pagesX63 stepsX8 bits. Fig. 1 shows the ROM
configuration.
The program counter consists of a I-bit CA; CB,
a 4-bit page address counter Pu register and a
6-bit polynomial counter P L (inhibit code: P L =
111111).
The CA is used. to specify the field, the Pu for the
page, PL for the steps within a page and the CB for
the· case where the field boundary is crossed.
(2) Data memory (RAM)
The data memory has 160 bits organized as 4 X
10 X 4 bits. Fig. 2 shows the RAM configuration.
The RAM address is specified by a 2-bit BM reg·
ister for the file specification, find a 4-bit BL regis·
ter for the word (4-bit) specification.
(3) Crystal oscillator and Divider (DIV)
The device contains a crystal oscillator circuit
for the system clock and timer oscillator. A
16.384kHz system clock can be provided and 1 sec
signal can be obtained from the final stage of a di·
vider by connecting an external 32.768kHz crystal
oscillator between the oscillator pins.
The divider consists of 15 stages, and lower 4
stages can be loaded into. the accumulator by the
DTA instruction. The lowest 9 stages (fg-f1) can be
reset with the IDIV instruction or an ACL opera·
tion.
(4) Segment .decoder
The SM500 contains an on-chip LCD driver
which can directly drive an LCD with a 3V, 112
duty, 112 bias scheme. The device also contains a
segment decoder which helps the software to be reo
duced.
The truth table of a segment decoder is shown in
Fig. 5, the LCD segments relative to the decoder
shown in Fig. 4, and the LCD driving signal wave·
form shown in Fig. 6. The display characters. other
than those described in F'ig. 5 are available by
directly setting data to W' with the WR or WS in· '
struction.

CA=O

CA=1

-+<-

0

'10

1

II

2

12

-+

3

4
5
6
7

8
9
A

B

C
D

E

F

Fig. 1

ROM configuration
-+

.~
BL

File

1

0

2

3

0
1

2
3
4

5
6
7
8
9

Fig. 2

RAM configuration
LSI

OSCIN

.

OSCOUT

32.768kHz

(5) Standby mode
The SM500 is a low power consumption design
due to CMOS process. For' further low power requirement, executing the CEND instruction places
the device in standby mode. To reduce power consumption, the system clock is inactivated.

Fig. 3

Crystal oscillator circuit

.-......-----...:..-.-SHARP-------·124

Fig. 4

LCD segment layout for segment decoders

wered up. The ACL is cleared in about 0.5 sec
from a crystal oscillator circuit starts oscillation
after power on, and starts execution of the program
at CA=O, Pu=FH, PL=0.
While in power on, applying a High level signal
to the ACL pin activates the ACL operation.
However, it takes about 0.5 sec to start execution
of the program after the ACL goes Low. The lowest
9 stages of a divider are reset during the ACL goes
High.·

While in standby mode, if more than one input of
K1 - Kr goes High, or r F IF is reset, the device exits standby mode and starts execution of the program at address 0000 (CA=O, Pu=O, PL=O).
(6) Reset function
Connecting a capacitor between the ACL pin and
the GND activates the ACL circuit when it is poAcc

0
1

2
3
4
5

Fig. 5

Display
character

Ace

,-,

6

Ll

I
I

7

:1

8

:t

-,

9

'-I

A

'-

1:1

B

Display
character

SM500

I-

0

,-,
·1

0

U

,-,
J

Flg.7

ACL external circuit

Blank

Display decoder truth table
~7.8125ms--j
r--~------"--~----GND

'-----,-- - - ----VM
- - - - - -VDV

Display ON

,.....--,---- -----GND
----- -VM

H,

' - - -...... -- - -- -- -- -- - -- -- ~ - -,--V DD Display OFF

--IL

L.-_ _ _

0;;-----'

Fig.6

m

u

_

~-_-~:~::D

LCD driving signal waveforms'

125

4-Bit Microcomputer (LCD Driver)

Instruction Set

•
(1)

RAM address instructions

Mnemonic Machine code
40-4F
LB xy
LBL xy 5F
(2 step) OO-FF
EXBLA OB
INCB64
DECB
6C

(2)

Operation
BL-x (h 12), BM-y (11) 10 )
BM-x (Is,

I~),

BL -y (13, 10 )

Acc+---+BL
BL -B L+ 1, Skip if BL =7
BL -B L-1, Skip if BL =0

ROM address instructions

Operation
Mnemonic Machine code
CB-CB
COMCB 6D
CA-CS, Pu-Su, PL+-SL, R+-O
RTN
6E
CA+-CS, Pu+-S u , PL+-S L
RTNS
6F
R+-O, skip the next step
Su - x (1 3-1 0 ), E +-1 next step
70-7F
SSRx
only
if R=O;
80-BE
PL-X (1 5 -1 0 ), Pu-Su, CA-C B
TRx
if R=l; PL+-1 5 -1 0
if R=O, E=O; PL-x (klo)
Pu3 -1, PU2 -P UO -0, SL-P L+ 1,
Su-Pu, CS-C A -0, R-1
CO-FF
TRSx
if R =0, E= 1; P L-x (Is, 10 ),
Pu-Su, SL -PL+ 1, CS+-CA+-CB
R+-1
if R = 1; PUb Puo-x (I5, 14)
TRSAxy CO-FF
P L3 -PLQ-Y (I3-Io), PLS , PL4 -0

(3)

Arithmetic instructions

Operation
Mnemonic Machine code
Acc-Acc+M
08
ADD
Acc-Acc+M+C,
ADDC
09
C+-C y , Skip if Cy = 1
Acc+-Acc+x (1 3-1 0 )
Skip if Cy =l
31-3F
ADX x
No skip if 13121110= 1010 (30 defines inhibit)
Acc-Acc
COMA
OA

(4)

Data transfer instruction ,

Operation
Mnemonic Machine code
10-13
Acc-M, BM+-BMEBX (Ij, 10 )
EXCx
Acc-M, BM+-BMEBX (Ij, 10 )
14-17
EXClx
BL -B L+ 1, Skip if BL =7
Acc-M, BM-BMEBx (Ij, 10)
1C-1F
EXCDx
BL ~BL -1, Skip if BL =0

126

SM500

Mnemonic Machine code
20-2F
LAXx
18-1B
LDAx
ATBP
03
PTW
59
PDTW
61
TW
5C
DTW

5D

WR

62

WS

63

(5)

Operation
Acc-x (1 3-1 0)
Acc+-M, BMEBX (IJ, 10 )
Bp+-Acc
Wi6 -W'i6, Wi5 -W'iS (i=l to 4)
W'l5+-W'16+-DECi (i=1 to 4)
Wi-W'i (i=1, j=O to 6)
W'i6+-DECi
W'ij write shift (i = 1 to 4,
j=O to 6)
W'46+-0, W'36-AcC 2,
W'26-AcC I
W'16-AccO, W'i; write shift
(i=1 to 4,j=0 to 6)
W'46+-1, W'36-AcC 2
W' 26-Accj, W'16-AccO
W'i; write shift (i = 1 to 4,
j=O to 6)

1/0 control instructions

Mnemonic Machine code
ATR
R+-Acc
01
Acc+-K
6A
KTA
S+-Acc
ATS
30
if S2=1;
EXKSA 02
if S2=0;
if S4=1;
EXKFA 6B
if S4=0;

(6)

Operation

Acc-Ks
Ks+-Acc
Acc+-KF
KF+-Acc

Divider manipulation instructions

Operation
Mnemonic Machine code
DTA
5E
Acc3+-fl' Acc2+-f2
(2 step) 04
ACCl +-f3' Acco+-f4
f9 -f l +-0
IDIV
65

(7)

Bit manipulation instructions

Mnemonic
RMx
SMx
RMF
SMF
COMCN
RC
SC

Machine code
04-07
OC-OF
68
69
60
66
67

Operation
Mx+-O
Mx+-l
m' +-0, Acc+-O
m'+-1
CN-CN
C-O
C+-1

SM500

4-Bit Microcomputer (LCD Driver)

(8)

(9)

Test instructions

Operation
Mnemonic Machine code
GEND
5E
clock stop
(2 step) 00

Mnemonic Machine code
Operation
TA
Skip if a =1
50
TB
51
Skip if f3 = 1
52
TC
Skip if C=O
TAM
53
Skip if Acc=M
TMx
54-57
Skip if Mx=1
TG
58
Skip if r =0, r-o
TAO
5A
Skip if Acc=O
TABL
5B
Skip if Acc=BL

•

Clock control instruction

(10)

Special instruction
Operation
No operation

Mnemonic
SKIP

System Configuration Example (Digital watch)

VDD

lOon
R,

R

GND
ACL
1J.!F

a

T

12H/24H

K,
OSC IN

K2

OSCOUT
fJ

K,

K3
22pF

R2

R3 R, Os, OS2 OS3 Os,

For
control

-----.-..-.--$HARP,--------------127

-SM5K1

-4.,... Bit Microcomputer (LCD Driver)

SM5Kl
•

4-Bit Microcomputer (LCD Driver)

Description

The SM5K1 is a CMOS 4-bit microcomputer
which integrates a 4-bit parallel processing function, a 1,280X8-bit ROM, a 16X4-bit RAM, a
15-stage divider circuit in a single chip.
Provided with three kinds of interrupt, four
levels of subroutine stack, 64-segment of LCD
driver, two modes of standby, 4 bits of large current drive port (LED directly drive port), and. 2
kinds of sound output functions, this microcomputer is applicable to battery back-up compact systems to home appliances such as an electronic microwave oven with a minimal external parts count
and low power consumption .

•

•

Pin Connections
42SDIP

Features

1. CMOS process
2. ROM capacity: 1,280 X 8 bits
3. RAM c;apactity
Data RAM: 64 X 4 bits
Display RAM: 16X4 bits
4. Instruction set: 51
5. Subroutine nesting: 4 levels
6. Instruction cycle: 5 to 61 p s
7. Interrupts
External interrupts: 2
Internal interrupt: 1
8. Input/output ports
I/O ports: 8
Input ports: 6
Output ports: 5
LCD output ports: 16 for segment
4 for common
9. Built-in LCD driver circuit
113 bias
113 or 114 duty selectable'
10. Sound (pulse) output
2kHz or 2.5kHz
(400kHz ceramic oscillator)
2,048kHz or 4,096kHz
(32.768kHz crystal oscillator)
11. LED direct drive (PO o- PO s)
15mA (V DD =5V± 10%)
12. Built-in oscillator circuit
Ceramic oscillator (400kHz)
Crystal oscillator (32.768kHz)
13. 15-stage divider circuit
14. Single power supply: 2.4 to 5.5V
15. 42-pin SDIP (SDIP42-P-600)
48-pin QFP (QFP 48-P-1010)

48QFP

P3!
P32

So

S3

Top View

--~·-~""---·--SHARP -..--..~~-.-~------

128

4-Bit Microcomputer (LCD Driver)

•

SM5K1

Block Diagram

ROM

:;E

....:I
p...

..:
~
SRx4

1280x8

»CIS

!

~

p...

[l

,t

S6

~

S1

"t:l

C.

S8

U
....:I

RD
RE
RF

S14

Acc
ACL
ALU
BL , BM

DlV

: Accumulator
: Auto clear
: Arithmetic logic unit
: RAM address register
: Carry flag
: Clock generator
: Divider

HC

: Common signal circuit

IF A, IFB, IFD

: Interrupt request

C

CG

Note:

IME
OSC

Pu , PL
RD,RE,RF
SB
SR

X

: Interrupt mask enable F IF
: Clock generator
: Program counter
: Mode register
: SB register
: Stack register
: X register

Pin numbers apply to a 48-pin QFP.

.-.-~--- ......... ~SHARP-'-'-'----'-

129

4-Bit Microcomputer (LCD Driver)

•

SM5K1

Pin Description
Symbol

-

Function
Output ports: 15mA Max. sink cur·
rent at 5V±10%

-

PO O-P0 3

Pl o-P1 3
P2 0 -P2 3
P3 0 -P3 3
Ho-H 3
SO-SI5
INTA.INTB

•

Symbol

Function

F

Sound output port
Test input port (normally connected
to GND)
Ceramic or crystal oscillator
Reset input port
Power supply
LCD drive power supply

T

Input/outIlut ports
Input ports
Common signal output ports
Segment signal output ports
External interrupt input ports

OSCIN• OSC OUT
ACL
VDD • GND
VoA/V DSP. VOB

Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Source output current
on each pin

Sink output current
on each pin
Sum of source output current
Sum of sink output current
Operating temperature
Storage temperature
Note
Note
Note
Note

•

1:
2:
3:
4:

Applied
Applied
Applied
Applied

to
to
to
to

Symbol
VDD
VI
Vo
101
102
103
104
105
106
107
108
kloH
kloL
Topr
Tstg

Rating
-0.3 to 6.5
-0.3 to VDD +0.3
-0.3 to VDD +0.3
4
4
4
2
30
200
4
2
20
80
-20 to 70
-55 to 150

Unit
V
V
V
rnA
rnA
rnA
rnA
rnA
f-lA

rnA
rnA
rnA
rnA

Note

1
2
3
4
1
2
3
4

·C
·C

pins PO, (i=3 to 0)
pins P1,. P2, (i=3 to 0)
pin F
pins Ho~H3, SO~SI5

Recommended Operating Conditions
Parameter
Supply voltage
Instruction cycle time
Operating temperature

Symbol
VDD
tSys

Topr

Rating
2.4 to 5.5
61 to 5
-20 to 70

.----------------------'~-SHARP

130

Unit
V

Note

f-ls

·C

.......... . . - - . - - - - - . - . - . - -

4-Bit Microcomputer (LCD Driver)

•

SM5K1

DC Characteristics
Parameter

. (Voo=2.4V to 5.5V, Ta= -20'C to +70'C)

Symbol
V-.lHl.
V'L

Conditions

VTH~'

Input voltage

~

VIH3
V".~

IIH!

VIH=VOO

IIH2

VIH=VOO

IlH3

VlH=VOO

I'Ll
V
V.
V...2V
V
V--'l.
V2
V

V'L=O

Input current

Output voltage

-loH !
lOLl
-loH2
IOL2

IOL3
-loH4
IOL4

VoH =V oo -0.5V
VOL = 1.0V
VOH=Voo-0.5V
VC)H=0.5V
VoH =V oo -0.5V
VOL =0.5V
VoH =V oo -0.5V
VoL =0.5V

DeoM
Ds
Tsys=5.0 ps
lOA

Tsys=61.0 P s

IOHI

Ceramic oscillation
Tsys=5.0ps
Crystal oscillation

Current
consumption
(Hold mode)

T~v~=61.0JLS

Ceramic oscillation
IOH2

Tsys=5.0~s·

Crystal oscillation
'ts==61.0~s

Current
consumption
(Stop model
Note
Note
Note
Note
Note
Note

~I

1:
2:
3:
4:
5:
6:

Applied
Applied
Applied
Applied
Applied
Applied

IDS

8
1
20
2
25
3
4.2
2.7
1.2
0
2.7
1.7
0.7
0
1.0
0.3
15
4.5
1.0
0.3
1.0
0.3
1.0
0.3

25
7
55
15
70
20

5.5V
3.3V
5.5V
3.3V
5.5V
3.3V
5.5V
3.3V

Voo=3.0V

Output impedance
Current
cosumption
(Operating)

to
to
to
to
to
to
to
to

TYP.

Voo=4.5V

Output current
-loH3

V--==4.5V
Vno=2.4V
Von -4.5V
V--==2.4V
Vno -4.5V
Voo=2.4V
V--==4.5V
V--==2.4V

MIN.
0.8Voo
0
0.6V nn
0
Vnn 0.5
0

Ceramic. oscillation
Crystal oscillation
T~v~=61.0JLS

V-=.~4.5V

Voo=2.4V
V--=-4.5V
Vno=2.4V
Voo-4.5V
V--=-=2.4V
Vno -4.5V
Voo=2.4V
V--=-4.5V
V--==2.4V
Voo -4.5V
V--==2.4V
V--=-4.5V
Voo=2.4V
Vnn -4.5V
Yua-2.4V
Voo -4.5V
Vnn=2.4V
V--=-4.5V
V--==2.4V
Voo -4.5V
~-2.4V

V-=.-4.5V
Voo=2.4V
V-=.-4.5V
V-=.=2.4V
VOD-4.5V
Von=2.4V
V--=-4.5V
Vno=2.4V
Vnn -4.5V
V--=-2.4V
Vno-2.4V
Voo-4.5V
Vnn-2.4V

to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to 5.5V
to 3.3V
to5.5V
to 3.3V
to 3.3V
to 5.5V
to 3.3V

pins PI" P2, (i=O to 3)
pins P3, (i =0 to 3)
pins aSC IN , T, INTA, INTB,and ACL
pins T, INTA anll INTB
to pin ACL
to pins Ho-H 3 , SO-SI5
to
to
to
to

-----------..-~SHARP

3.0
1.5

2.0
1.0

MAX.
V-=.
0.2Voo
Vnn
0.5
Voo
0.5
1
2
70
20
150
50
150
55
4.5
3.3
1.8
0.3
3.0
2.3
1.3
0.3

Unit

Note

V

1

V

2

V

3

pA

1

pA

2

pA

4

pA

5

V
6
V

rnA

7

rnA

8

rnA
100
30

100
30
100
30
5
15
10
30
350
150
220
60
35
20
20
10
25
15
8.0
4.5
3.5
1.5

15
60
40
120
850
250
650
150
70
40
45
20
60
35
15
8.0
1.0
7.0
3.0

pA

1

pA

9

kO

r---

10
11

pA

12

pA

13

pA

14

pA

r-1L
16

~-----~=~:
.

-----------V2

---------- -VI

LCD terminal output waveform example

. - . - . - - - - - - - -........... 131

4-6it Microcomputer (LCD Driver)

Note
Note
Note
Note
Note
Note
Note
Note

7:

SM5K1

Applied to pins PO; (i=O to 3)

8: Applied to pin OSCOUT
9: Applied to pin F

10: Applied to pins Ho-H 3
11: Applied to pins SO-S'5
12: No load condition. Current consumption under the operation with an external clock input. LCD should be turned on.
13: No load condition. Current consumption when driving an oscillator and turning LCD ON placed the device in hold mode.
14: No load condition. Current consumption when driving an oscillator and turning an LCD bleeder resistor OFF placed the device in
hold mode.
Note 15: No load condition. Current consumption when the entire system including ceramic oscillation is inactivated.
Note 16: No IQad condition. Current consumption when the entire system except for crystal oscillator is inactivated.

•

(V DD =2.4 to 5.5V)

External clock Input characteristics
Parameter
Input rise time
Input fall time

Symbol

Clock pulse width

•

MIN.

Conditions

tM
tF
tL
tH

TYP.

1.20
1.20

MAX.
50
50
30.47
30.47

Unit
ns
ns

ps

External Input Clock Timing
~-----tL,------~

•

Oscillator Circuit

OSCOUT

C2

(a)
Note:

400kHz clock

Oscillator IT A722EOO
"-<>--.........----Q-' Crystal: 32.768kHz

Oscillator CSB-400R :

R

ITA722EOO
C1 =12pF
C2 =12pF
R{=lOMO
R.J=330kO

MURATA
Rf=lMO
C1 =220pF
C2 =220pF

(b)

32.768kHz clock

(c)

External clock input circuit

The resistors, capacitors and crystal oscillators should be located as close to the LSI chip as possible to minimize influence of stray
capacitance.

--'-'---'---SHARP--,-'---''-'~-

132

4-Bit Microcomputer (LCD Driver)

•

SM5K1

Pin Functions
(1)

GND, Vee (Power supply)

The GND pin should be grounded.
The VDD pin is the power supply input which
should be positive with respect to GND.
(2)

T (Test input)

The test pin must be grounded and should not be
used. It is connected to GND with a pull-down resistor.
(3)

ACL (Reset Input)

The ACL accepts an active-Low level which initializes the internal logic of the device. Normally a
capacitor is connected between this pin and GND to
,provide a power-on reset function.

(6) Ho-H 3 (Common drive outputs)
The Ho-H 3 pins are used to drive the common
output of an LCD.
SO-S15 (Segment drive outputs)

(7)

The SO-S15 pins are used to drive LCD segments.
(8)

INTA, INTB (External interrupt inputs)

The IF A flag is set at the rising edge of INT A
input pin, and the IFB flag is set at the falling edge
of INTB input pin.
Note:

(4)

OSC 1N , OSC OUT (Crystal or ceramic
oscillators)

The OSC IN and OSCOUT pins connect with an external crystal or ceramic oscillator, in conjunction
with an on-chip oscillator circuit, constitute a
real-time clock.
Either a crystal or ceramic oscillator is selectable with a mask option.

Both INT A and INTB pins are connected to the noise debounce circuit which does not accept the pulse shorter
than two instruction cycles.

(9)

POo-P03 (Output ports)

The PO port, output pins PO O-P0 3 are used to
directly drive an LED with a maximum of I5mA of
sink current (V DD =5V±10%).

V DD c)------.
POo POI P02 P0 3
OSC1N

I
(5)

OSCOUT

I

F (Sound output)

The pin F serves exclusively as a sound output
pin which can be selected between 2kHz and
2.5kHz at the base frequency of a 400kHz ceramic
oscillator, 2,048kHz and4,096kHz at a 32.768
kHz crystal oscillator.

P1 0 -P1 3 , P20 -P23 (1/0 ports)
The PI and P2 are 110 ports which can be
switched between Input and Output modes through
an instruction at a 4-bit unit.
These ports can also be used as output ports for
a key matrix.
'
(10)

(11)

P30 -P33 (Input ports)

The P3 port, input pins P 3o -P 33 are connected to
the positive supply with pull-down resistors,
which can be used for a keymatrix.

133

SM5K1

4-Bit Microcomputer (LCD Driver)

•

Hardware Construction

(1) Program counter and stack register
The program counter (PC) is used to specify the
ROM address.
The PC consists of 12 bits including a 6-bit .
page address count register (Pu) and a 6-bit binary
counter (Pd which addresses steps within each
page.
The stack register (SR) consists of 4 stages
which provides up to 4 levels of subroutine
nesting.

2X8X4 bits of RAM space, (4X16+2X8)X4
bits, is used as a display RAM area from which
data is output to LCD segment .driving pins. An
LCD with a 114 or 113 duty and 113 bias format
can be directly driven by writing display data into
the display RAM area.
Fig. 3 shows the relationship between the display RAM and LCD segments.

o
BM
~

(2) Program memory (ROM)
The SM5K1 has 1,280 steps of on-chip ROM·
organized as 20 pages X 64 steps.
When the ACL resets the device (power-on), it
starts execution of the program at page 0, step O.
Fig. 1 shows the jump address with a ROM address
instruction.
A jump within a page is executed by a TR instruction, and a jump out of a page is executed by a
TL instruction.
A subroutine jump is executed by a CALL or
TRS instruction.

Pu

1

0

000000 000001
ACL

Subroutine
TRS cover

2

3

Page
Pu

A

B

8
9

001010 001011

001100 001101
TRS x

7

8

9 A B C D E

F

I~ ~ ~ ~ ~ ~ ~ r;:;;;;

The shadowed area is allocated. for a display RAM
The file can be speCified as long as the BM should be 0,
1, 2, 3, 8 or 9.

Note:

. Fig. 2

RAM configuration

(4)

Accumulator (Ace), X register, arithmetic
and logic unit (ALU)
The accumulator (Acc) is a 4-bit general-purpose register which transfers data and numerics to
memory, 110 ports, and registers. The Acc performs arithmetic operations in conjuction with a
RAM, a carry flag and an ALU.
4

5

Table
reference
page at
the PAT
instruction
execution

D

5 6

I~ ~ ~ ~ ~ ~ ~ ~

Interrupt

C

4

2

000100 000101

t

3

3

000010 000011
Standby
clear

2

1

(3) Data memory (RAM) and B register
The RAM consists of a 256~bit data RAM organized as 4X16X4 bits and a 64'-bit display RAM
organized as 8 X 2 X 4 bits.
Fig. 2 shows the RAM configuration with 6 files
of architecture.
The B register consists of a 4-bit BM which
address files and a 4-bit BLwhich address words.
Page

1

0

E

6

/

9

001001

V

/

TL xy

TRS x

F

8

001000

7

000110 000111

lOH

llH

001110 001111 010000 010001

12H

13H

010010 010011

CALL
xy
RTN

Fig. 1

ROM configuration

---------~--~-SHARP'------.,-......--~-~-

134

I,

I

SM5K1

4-Bit Microcomputer (LCD Driver) .

The X register is a 4-bit register used as a temporary register which transfers and compares data
with the Acc. The ROM data can be loaded into the
X register and Acc using a table reference instruction.
The arithmetic and logic unit (ALU) performs
binary addition, in conjunction with a RAM, a carry flag and an Acc.
(5) SB register
The SB register is an 8-bit register which can
be used as a save register.
(6) Output latch register and mode register
Ports PO, PI and P2 connect with output latch
registers, and transfer the contents of the Acc to
the output latch registers with an instruction.
The SM5Kl has mode registers RD, RE and RF
for controlling an LCD and interrupt functions.
(7) System clock generator circuit, divider
The OSC IN and OSC OUT provide a system clock
fs with the base frequency divided by two. One cy(Register)

cle of the system clock is identical to the instruction cycle time.
The divider consists of 15 stages. The. lower
8-stage is reset with an instruction, and the lowest
4 -stage is transferred to the Acc by a DT A instruction.
The oscillator can be selected between the ceramic and crystal with a mask option.
The least stage of a divider fc can be selected between 2Hz and 1Hz under crystal oscillation with a
mask option (See Fig. 4).
(8) Sound output
The frequency obtained by a system clock generator circuit can be output from the F pin as a
sound pulse.
Setting the RD register outputs and stops the
sound pulse, and switches the frequency. The frequency can be selected between 2kHz and 2.5kHz
at 400kHz of a ceramic oscillator, while 2,048kHz
and 4,096kHz at 32.768kHz of a crystal oscillator.

Ho

L

Segment output

B M= 1000
BL =0000

->

80

->

82

B M=1001
BL =0000
BM=1000
BL =0001

LCD
driver

(BM register)

L

M3

L

M2

L

Ml

L

Mo (Bits in RAM area)

*The common outputs cannot be used when applied to an LCD with a 1/3 duty, 1/3 bias scheme.

Fig. 3

Display RAM and LCD segment outputs.

135

4-Bit Microcomputer (LCD Driver)

SM5K1

F port output LCD frame frequency
2kHz
500Hz
OSCIN
OSCOUT

OSC
(400kHz)

250Hz
LCD frame frequency

1/2 1/2 1/2

2.5kHz
F port output (ceramic oscillation)
fs=200kHz (ceraInic)
fs = 16.384 (crystal)

512Hz LCD frame frequency (crystal oscillation)

t
1/2 1/2 1/2 1/2

1/2 1/2 1/2 1/2

1/2 1/2 1/2 1/2

fc~
256Hz
F port output LCD frame frequency
(crystal oscillation)
(Under 400kHz ceramic or 32.768kHz crystal oscillation)

fc

fc=2Hz or 1Hz
(crystal oscillation)
fc=2aHz or aHz
a=400/32.768

(ceramic oscillation)

Fig. 4

System clock generator circuit (fc= 1Hz or 0.5Hz)

Interrupt enable flag

Priority order

Interrupt request flag
INTAinput

2
INTBinput

INT
Interrupt master
enable flag

DTiver
over flow

Fig. 5

Interrupt handling

(9) Interrupts
The INT A, INTB inputs and the divider over·
flow flag can be used for the interrupt request. The
IF A, IFB and IFD flags can be used as the inter·
rupt request flag.
The interrupt block consists of mask flags (REo,
REI. RE 2), an IME flag, and an interrupt processing
circuit.

(10) Standby mode
To reduce power consumption, the device is
placed in standby mode, and the program execution
is inactivated .
. Stop mode
In the stop mode, the entire system clock is in·
activated under ceramic oscillation, however, only
a reference clock is operative under crystal oscillation .

. - - . . . . - . - . - - -....... . - . - - - S H A R P - , - : - . - - - - - - - - . - . - - - . - , - - - 136

SM5K1

4-Bit Microcomputer (LCD Driver)

• Hold mode
Only a system clock generator circuit (CG circuit) is inactivated, while the OSC and DIV circuit
is in operative (see block diagram).
While in standby mode, if anyone bit of P3 input port goes High during ACL, or an interrupt
occurs from unmasked INT A, INTB or a divider,
tile device exits standby mode and starts program
execution.

(11) Reset function (ACL)
Applying a Low level signal to the ACL pin resets the internal logic of the device and applying a
High level signal starts execution of the program at
address 0, page O.
Once the device is reset, all I/O ports are placed
in input mode, and the mode registers RD, RE and
RF are cleared. The output port PO is cleared to
output a High level signal.
The interrupt enable flags IF A, IFB and IFD,
and the interrupt master enable flag IME are reset
to disable all interrupts.
In case the noise may harm the ACL operation,
apply a capacitor between ACL pin and V DD pin
(see Fig. 6).

which can directly drive an LCD with a 1/4 duty
and 1/3 bias as well as 1/3 duty and 1/3 bias
scheme.
Fig. 7 shows an example of LCD segment configuration for 1/4 duty.
Each segment of the LCD can be turned on or off
by software control of the setting of the corresponding bit" I" or "0" in the display RAM area (see
Fig. 3).
The LCD digit may have any shape, provided
that the maximum number of segments does not exceed 64 (see Fig. 7).
Fig. 8 shows an example of a seven-segment
numeric LCD digit.
• LCD driving signal waveform
Fig. 9 shows the LCD signal driving waveforms
required to display the number "5" on the
7-segment display for 1/4 duty shown in Fig. 8
(a).

Fig. 10 shows the LCD signal driving waveforms
required to display the number "2" on the
7-segment display for 113 duty shown in Fig. 8
(a).

So

Fig. 6

ACL circuit

( a)

(12) LCD driver
• Display segment
The SM5K1 contains an on-chip LCD driver

Ho

0-----

H3

0-----

1/4 duty

Fig. 8

(b)

1/3duty

7-segment numeric LCD digit

Common

Segment

So

Fig.7

LCD configuration for 1/4 duty

137

4-Bit Microcomputer (LCD Driver)

SM5K1

--- V DD (3V)
,-----VOA (2V)

,
:

---~--r----VOB

:
I

:

:

;

. (IV)

:---:---t----GND(OV)

I

r

:

:

:

:

I

I

•

I

'.

:

I

I

I

I

~
,
,.
,"
---V
'

HI

'

:

:-----VOD
-----VOA

',

,
I __
I

I

I

I

OB

GND

:":

~: _ _ _ _ Von

--i---- V OA
.,.---_

V OB

.---:--- -:- - - ~ --i-----GND

,,

_~

___

1 ___ 1-

____

I _ _ ...J.

I

I

I:
I

I

f

:

I

I

I

I

Sl

S
2

114 duty
Frame frequency=lIT=62_5Hz or 125Hz
Fig. 9

LCD driving signal waveform

VOA and VOB pins
The device contains bleeder resistors to allow 1/
3 bias driving. When VDD is 3V, voltages of .2V
and 1 V are applied to pins VOA and VOB respectively.
Normally pins VOA and VOB are left open. When
an LCD with a large display area is driven, connect
capacitors across pins VOA and VDD and across
VOB and VDD to improve the rise time of the LCD
driying signal.

138

,,

Von
V OA

___ L____ VOB

I

I

I

"

I

I

I

I

----GND

':;
--- V OA
~
-----V

I---~--~---:----VDD

J

:

:

:

I

I

I

I

I

J
I

:
I

I

'

,---,---:---:----VDD

I

I

I

I

:':

,

I

:
f

'

'

I

I

I

r

OB

'----GND
I

' '.
~
-'''----V
I

"'-----VOA
I
OB

:

:

;----GND

I

,

I

1/3 duty
Frame frequency = liT = 83.3Hz or 166.7Hz
Fig.10

LCD driving signal waveform

SM5K1

4-Bit Microcomputer (LCD Driver)

•

Instruction Set
(1)

ROM address Instructions

Operation
Mnemonic Machine code
80-BF
P L+-x (15-10)
TR x
Pu+-x (1 11 -1 6)
EO-E4
TL xy
P L+-y (1 5-1 0)
OO-FF
Push, P u +-01H,
CO-DF
TRS x
P L+-x (14 la 12 11 10 0)
Push, Pu+-x (1 11 -1 6)
FO-F4
CALL xy
OO-FF
P L+-y (15-10)
Pop
RTN
7D
Pop, Skip the next step
7E
RTNS
Pop,IME+-1
RTNI
7F

(2)

Data transfer instructions

Operation
Mnemonic Machine code
Acc+-x (Ia-Io)
10-lF
LAX x
30-3F
BM+-x (Ia-Io)
LBMX x
20-2F
BL +-x (Ia-Io)
LBLX x
Acc+-M, BMi+-BMi(BX(lhlo), (i=I, 0)
50-53
LDA x
M+-Acc, BMi+-BMi(BX (I h 10), (i = 1, 0)
54-57
EXC x
M-Acc, BL +-BL + 1
BMi+-BM;E£) X (110 10), (i=l, 0)
58-5B
EXClx
Skip if BL =F H
M-Acc, BL +-B L-1
BM;+-BM;E£) X (110 10), (i=l, 0)
5C-5F
EXCD x
Skip if BL =0
Acc-X
EX AX
64
X+-Acc
ATX
65
BM-Acc
EXBM
66
BL-Acc
67
EXBL
B-SB
EX
68

(4)

Test instructions

Mnemonic
TAM
TC x
TM
TABL
TPB x
TA
TB
TD

(5)

Bit manipulation instructions

Mnemonic
SM x
RM x
SC
RC
IE
ID

(6)

Machine code
Operation
44-47
M;+-l (i=3 to 0)
40-43
M;+-O (i = 3 to 0)
C+-1
61
C+-O
60
IME+-1
63
IME+-O
62

1/0 instructions

Mnemonic
INL
OUTL
ANP
ORP
IN
OUT

(7)

Operation
Machine code
Skip if Acc=M
6F
6E
Skip if C=l
48-4B
Skip if M;=l, (i=3 to 0)
Skip if Acc=BL
6B
4C-4F
Skip if P (R);=l, (i=llo 10 )
IFA+-O
Skip if IF A= 1
6C
IFB+-O
Skip if IFB= 1
6D
69
IFD+-O
Skip if IFD = 1
02

Machine code
Operation
Ace+-P1; (i=3 to 0)
70
71
PO;+-Acc (i=3 to 0)
72
Pi+-Pi "Acc U=2 to 0)
73
Pi+-PiVAcc U=2 to 0)
74
Acc+-Pi U=3 to 1)
Pi+-Acc 0=2 to 0), Pi+-Acc O=FH-DH)
75

Table reference instructions

Mnemonic Machine code

(3)

Arithmetic instructions

Operation
Mnemonic Machine code
OO-OF
Aec-AcC+x (klo) Skip if CY=l
ADX x
Acc+-Acc+M
7A
ADD
Acc+-Acc+M+C, C+-CY Skip if CY= 1
7B
ADC
Acc+-Acc
COMA
79
BL+-BL +1, Skip if BL -FH
INCB
78
BL +-BL -I, Skip if BL =0
DECB
7C

PAT

(8)

6A

Operation
Push
P u +-04H, PL+-(Xlo Xo, Acc)
X+-ROM H, Acc+-ROM L
Pop

Divider operation instructions

Operation
MnemoiIic Machine code
DIV (f7 -fo) Reset
69
DR
03
Acc+-DIV (fa-fo)
69
DTA
04

(9)

Special instructions

Mnemonic
STOP
HALT
NOP

Machine code
Operation
Standby mode (STOP)
76
Standby mode (HALT)
77
No operation
00

139

4-Bit Microcomputer (LCD Driver)

•

SM5K1

System Configuration Example (Audio-timer)

4X5
Voo

Key matrix

Piezo electric
buzzer

37
38
39
40
41
42
43
44
45
46
47

P3]
P32
P33
F
ACL
OSC IN
OSCOUT
So
S]

SM5Kl
(Top View)

S2
S3
48 S]2

23
22
21
20
19
18
17
16
Ho 15
V OB 14
V OA 13

LCD

140

PO]
PO o
T
INTB
INTA
H3
H2
H]

VOrJ

+ +

SM4A

4-Bit Microcomputer (LCD Driver)

SM4A
•

4-Bit Microcomputer (LCD Driver)

Description

The SM4A is a CMOS 4-bit microcomputer
which integrates a 4-bit parallel procesing function, a 2,268-byte ROM, a 96-word RAM, a
15-stage divider, and a 68-segment LCD driver
circuit in a single chip.
This microcomputer is applicable to the system
having multiple LCD segment, with low power consumption.

•

•

Pin Connections
o

66dc5c56c5C5666dac5d
5

4 4

3

Features
1.
2.
3.
4.
5.
6.
7.

CMOS process
ROM capacity: 2,268 X 8 bits
RAM capacity: 96 X 4 bits
Instruction set: 54
Subroutine nesting: 1 level
Instruction cycle: 61 p. s (TYP.)
Input/output ports
I/O ports: 4
Input ports: 6
Output ports: 4
LCD output ports: 34 for segment
2 for common
8. On-chip clock divider
9. On-chip crystal oscillator
10. External RAM access
11. LCD driver circuit
(68-segment, 1/2 bias, 112 duty)
12. Standby function
13. Single power supply: - 3V (TYP.)
14. 60-pin QFP (QFP60-P-1414)

Top View

141

4,.. Bit Microcomputer (LCO Driver)

•

SM4A

Block Diagram

2

00
S S
Symbol description

ALU
Acc
ACL

C.
ex, CA, Pu, PL
Cs• Suo SL

•

: Arithmetic logic unit
: Accumulator
: Auto clear
: Carry F/F
: Program counter
: Stack register of program counter

BM.BL
DIV

PLA
CG
W1-W •• W'l-W',

: RAM address register
: Frequency divider
: Programmable logic array
: Clock generator
: Static shift register

Pin Description
Symbol
KI -K 4
a

f3
DIO I -DI0 4
R1 -R 4
0 11 -0 48
OShOS2
HI; H2
BA'
Th T2
ACL
OSCII·i, OSCo~Tr
VM
GND, VDD

142

Circuit type
Pull down
Pull down
Pull down
3-state output
Complementary

I/O
I
I
I
I/O
0

Wand W' registers output: used for LCD segment output

0
0
I
I
I

Function
Acc+-K I -K 4
Set by t. reset after test instruction execution
Input signal is held for 1 instruction cycle, test possible
Acc+-'+DIO I -DI0 4
R1 -R 4 +-Acc

Pull up
,

3-state level output possible, used for LCD comm'on output
For test the input signal of High or Low,
For test (Connected to VDD normally)
Auto clear
For clock oscillation
Power s\1pply, for LCD driver
Power supply for logic circuit

4-Bit Microcomputer (LCD Driver)

•

SM4A

Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature
Note 1:

•

Symbol
Voo
VM
V IN
Topr
Tstg

Rating
-3.5 to +0.3
-3.5 to +0.3
VoD -0.3 to +0.3
-5 to +55
-55to+150

Unit
V
V
V
·C
·C

Note
1

The maximum applicable voltage on any pin with respect to GND.

Recommended Operating Conditions
Parameter

Voo
VM
fosc

Supply voltage
Oscillator frequency

•

Rating
-3.2 to -2.6
Voo/2 (TYP.)
32.768 (TYP.)

Symbol

Unit
V
V
kHz

(Voo=-3.2 to -2.6V, Ta=25·C)

Electrical Characteristics
Parameter

Symbol
VIR!
VILl
V IR2
VIL2
VOH!
VOLl
VOH2
VOL2
VOH3
VOL3
VOA
VOB
Voc
Iso
ISIN
lOA
los

Input voltage

Output voltage

Output current
Supply current
Note
Note
Note
Note
Note
Note
Note

1:
2:
3:
4:
5:
6:
7:

Applied
Applied
Applied
Applied
Applied
Applied
Applied

to
to
to
to
to
to
to

Conditions

MIN.
-0.6

TYP.

MAX.
Voo+0.6

-0.3
Voo +0.3
IouT=50pA to Voo
IOllT=5pA to GND
IouT=50pAto Voo
IouT=30 p A to GND
IOllT=50pA to Voo
IouT=50 p A to GND
No load
V oo =-3.0V
VM =-1.5V
VOllT =-0.2V
VOUT=VDO+0.2V
During full-range operation
When system clock is stationary

pins K" K2 • K3 • K4 , a.
pin ACL
pins 0 48 -0 11 • OS" OS2
pins DIOI-DIO.
pins R2• R3 • R4
pins H" H2
pin RI

-0.5
Voo+0.5
-0.5
Voo+0.5
-0.5
Voo+0.5
-0.3
-1.5
-2.7
100
100
50
lO

100
20

Unit
V
V
V
'V
V
V
V
V
V
V
V
V
V
pA
pA
pA
pA

Note
1
2
3
4

5
6

7

f3

--'-.......--.-----SHARP_------~-·--~

143

SM4A

4-Bit Microcomputer (LCD Driver)

•

Pin Functions

(1) K1-K4 (Inputs)
The input ports KCK4 are connected to the accumulator Acc. The contents of the K1 -K 4 are loaded
into the Acc.
a, ~ (Inputs)
The input ports a and f3 can be independently
tested. The a input latches the a F IF at the rising
edge of the input, and can be tested by the T A instruction. The a F IF is reset after the test. The f3
is used to put the input signal into the f3 F IF for
the interval of one instruction, and can be tested by
the TB instruction.
(2)

(3) 010 1-010 4 (I/O ports)
The DI0 1 - DI0 4 pins normally output the contents of the F 1 -F 4 F/F. The FCF4 F/F data can be
changed on transferring the accumulator Acc by
the ATF instruction. Connecting the DIOcDI0 4
with the Acc allows the data transfer between the
Acc and an external RAM by the READ and
WRITE instructions. The output buffer oJ the
F cF 4 F IF is designed to be a three-state output,
and it is kept high impedance when the DIO input
is loaded into the Acc by the READ instruction.

(4) R1-R4 (Outputs)
Connecting the DI0 1 - DI0 4 with the Acc outputs
the contents of the Acc. And selecting the programmable logic array PLA generates a sound output, and allows a segment output on pins OS3 and
OS4.

0'1 0=1 to 4, ]=1 to 8), OSl, OS2 (Outputs)
34-bits of output ports Oij, OSI and OS2 are used
to output the contents of the static shift register
W'in, Win (i = 1 to 4, n = 0 to 8). The output signal
can be used as a segment signal for a 1/2 duty
scheme, and a strobe signal for the key-scan,
according to the display mode. These ports output
the address of the external RAM upon execution of
the READ or WRITE instruction.
(5)

(6) H 1 , H2 (Output)
The HI and H2 are used to output the common
signal of an LCD with 1/2 bias, 112 duty scheme
in a three output level inculding VDD, GND and VM.

(7) BA (Inputs)
The BA pin is used to test the input level. of High
or Low by instructions.

--"'-~--~-~SHARP,~---'----~---'-"-'

144

4-BitMicrocomputer (LCD Driver)

•

SM4A

Hardware Cnfiguration

(1) Program memory (ROM)
The on-chip ROM has a 2,268 byte organized as
36 pagesX63 stepsX8 bits. The program counter
consists of 1-bit registers Cx and CA , a 4-bit register Pu, and a 6-bit polynomial counter PL. The PL
is used to specify the steps, the P u specify the
pages, and the CA specify the fields. The Cx register is only used to specify the subroutine pages.

(2) Data memory (RAM)
Data memory has a 6X16 wordX4-bit configuration, and is addressed by a 4-bit BL and a
4-bit BM•
(3) Oscillator circuit
An on-chip crystal oscillator allows the oscillation with the external circuit shown in Fig. 3.

-Field

Cx =1

Cx=O
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SM4A

-

CA=1

CA=O
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

32
33
34
35

OSCoUT 0---4---1

Fig. 3
(4) Divider
A 15-stage resettable divider outputs a 1 Hz
signal at the lowest stage when a 32.768kHz crystal oscillator is used. The output on each stage can
be loaded into the accumulator Acc on an 4-bit
basis.
(5) Reset function (ACL)
An on-chip reset circuit may sometimes require
a capacitor between the ACL pin and GND pin. It
takes 1 sec on an internal timer from the beginning
of oscillation to clear the ACL mode when power
on.

Fig. 1 ROM configuration (fields and pages)

BL

1

0

BM3
BM2
BMl

-

0
0

0
1

1
0

1
1

0

1

x

y

z

M

u

T

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Fig. 2

RAM configuration

145

4-Bit Microcomputer (LCD Driver)

•

SM4A

Instruction Set
Mnemonic
SBM
LB
LBL
INCB
DECB
RM
SM
ATPL
ADD
ADDl1
COMA
EXBLA
EXC
EXCI
EXCD
LOA
LAX
ADX
DC
DTA
ROT
ATBP
ATW
PATW
ATF
ATR
READ
WRITE
KTA
RC
SC

Machine code
Is 17 16 15 I. 13 12 II
02
40-4F
5F
OO-FF
64
6C
04-07
OC-OF
03
08
09
OA
OB
10-13
14-17
lC-IF
18-1B
20-2F
30-3F
3A
5E
04-07
6B
01
5D
00
60
61
68
69
6A
66
67

Operation
1-4BM3 (B M3 = 1 for nextstep only)
14 • 13-B L2• BLi 12• II-BM2• BMI
Is-I5-BM4-BMI

14 -1 I- BL4 - BLl

BL +1-B L if BL =a; skip
BL --:-1-+BL if BL =b; skip
O-+Mi (i=I2 II)
I-+Mi (i=I2 11 )
Acc- P L4 - P Ll
Acc+M-Acc
Acc + M +C-+ Acc . C 4-C if C4 = 1; skip
Acc-Acc
Acc-B L
Acc-M BM2, BMI EB 12 , II-BM2, BMI
Acc-M BM2, BMI EB 12, II-BM2, BM! BL+I-B L if BL =a; skip
Acc-M BM2, BMI EB 12, II-BM2, BM! BL-I-B L if BL =b; skip
M-Acc BM2, BMI EB 12, II-BM2, BMI
I.-II-Acc
14-1 1 + Acc-Acc if C 4 = 1; skip
10 + Acc-+ Acc
DIV-Acc
C-A 4-+ A 3 - A 2 -+ A1-C
Acc-Bp
ACC-W'iS (i=1 to 4) W'in Right Shift (i = 1 to 4. n = 7 to 0)
ACC-W'iS W'iS-+W'i7 (i=1 to 4)
Acc-F
Acc-+R
DIO-Acc
Acc-DIO
Ki-Acc
O-C
l-C

.......... . . - - . ' - - - - - - - - - S H A R P ' - - - - - · - - 146

4-Bit Microcomputer (LCD Driver)

COMCB
SSR

Machine code
Is 17 Is 15 14 13 12 11
5C
59
62
63
65
50
51
52
53
54-57
5A
5B
58
5E
02
5E
00
5E
03
60
70-7F

TRO

80-BF

TR1

CO-FF

RTNO
RTN1
JUMP

6E
6F
OO-FF

Mnemonic
TW
PTW
WR
WS
IDIV
TA
TB
TC
TAM
TM
TAO
TABL
TIS
®TAL
®CENO
®ST

SM4A

Operation
W'in-Win (i=l to 4, n=8 to 0)
W'in-Win (i=l to 4, n=8,7)
0-W'48 Win Right Shift
1-W'48 Win Right Shift
O-DIV
if a = 1; skip
if f3 = 1; skip
if C=O; skip
if Acc=M; skip
if Mi=l (i=I2 11); skip
if Acc=O; skip
if Acc=B L; skip
if lS=O; skip
if

BA=l; skip

Clock stop
1-T
CB-CB
I4-I1-Su4-SUl 1-E (next step only)
if R=O; Is-I1-PLs-PLl Su-Pu CB-CA
if R=l; Is-I1-PLs-PLl
if R=O, E=O; (IS-I1-PLs-PLl O-Pu-Su PL+l-S L
1-R 1-C A-Cs 1-0
if R=O, E=l; (IS-I1-PLs-PLl Pu-Su P L+l-S L
CB-CA-Cs 1-R
if R=l; Is, I5-P u2 , Pul I4-I1-PL4-PLl
CS-CA Su-Pu SL-PL O-R
CS-CA Su-Pu SL-PL O-R skip next step
if 0=1 I8-I s-P u4 , PU3 ' Pul I5-I1-PL5-PLl

147

SM4A

4-,BitMicrocomputer (LCD Driver)

•

System Configuration Example (Radio PLL controller)

LCD
DC voltage cutout 0.02pF
Oij

Band selection

32.768kHz 22pF
OSC OUT

,r~-~BA

OSC IN

Tape stop
Various

control~ {

Rl

R2
R3

VM
220kO

R4

PLL latch
PLL shift register clock
PLL shift register data

MUTE

15pF

GND

VD

DIO I
DI0 2
DI0 3
DI0 4

220kO
+10
pF

1000

+

10pF

-

3V

0.33pF

ACL
a

f3

0 47 - - - - 1

0 46 - - - - 1
0 45 - - - - 1
0 44 - - - - - I
0 43 - - - - - I

0 42 - - - - I

041 ---~
0 38 --~~

.-------------SHARP-----------148

SM510

4-Bit Microcomputer (LCD Driver)

SM510
•

4-Bit Microcomputer (LCD Driver)

Description

The SM510 is a CMOS 4-bit microcomputer
which integrates a 4-bit parallel processing function, a 2,772X8-bit ROM, a 128X4-bit RAM, a
15 stage divider and a 132-segment LCD driver
circuit.
This microcomputer is applicable to many applications having mUltiple LCD segments with low
power consumption.

•

Features

1. CMOS process
2. ROM capacity: 2,772 X 8 bits
3. RAM capacity: 94 X 4 bits· (Data RAM)
32X4,bits
(Display RAM)
4. Instruction set: 49
5. Subroutine nesting: 2 levels
6. Instruction cycle: 611'- s (TYP.)
7. Input/output ports
Input ports: 6 bits
Output ports: 10 bits
LCD output ports:
34 bits for segment
4 bits for common
8. 15 stage divider with reset
9. LCD drive circuit
3V, 114 duty, 113 bias,
132 segments (MAX.)
10. Crystal oscillator circuit (32.768kHz)
11. Standby mode
12. Single-3V (TYP.) power supply
13. 60-pin QFP (QFP60-P-1414)

•

Pin Connections
Cl

£ 2£ J,d
4

~J!l'f3 il.E;;.o <3.E

&

4

a,
b,

a,
H,
H3
H,
H,

all
bll

s,

a13
b13

s,

b14

S6

Top View

149

~

4-Bit Microcomputer (LCD Driver)

.•

SM51Q

Block Diagram

a,
alO
blO
Display RAM

au

(32X4)

bn

RAM

aI'
b 12

(96x4)

al3
b\3
al4
bl4
al5
bl5
al6
b!6

'--r-'

~

GND

Symbol description

ALU
Acc
C

pu. PM. P L
Su. SM. SL
Ru. RM • RL
DIV

•

W
BM• BL
Bp
H. L. Y
R
K
CG

b
o

U

Z

r3
rJ)

~ 0
: 8-bit shift register
: RAM address register
: Backplate signal generator circuit
: 4-bit F/F
: 2-bit F/F
: Key input F IF
: Clock Generator

Pin Description
Symbol
ai, bi
bs
HI-H.
SI-S8
T
KI -K.
OSCIN
OSCOUT
BA. (:J
GND. V DD
Rio R2
ACL

150

: Arithmetic logic unit
: Accumulator
: Carry F/F
: Program connter
: Stack register of program counter
: Stack register of program counter
: Divider

VDD

I/O

Circuit type

Function

0

Segment output ports (i = 1 to 16)

0
0
I
I

Common output ports
Strobe output ports
Test input port (normally connected to GND)
Key input ports

pull-down

Crystal oscillator
I

pull-up

0
I

pull-down

Independent input ports
Power supply
Melody output ports
Auto clear input port

SM510

4-Bit Microcomputer (LCD Driver)

•

Absolute Maximum Ratings
Parameter
Pin voltage
Operating temperature
Storage temperature

Symbol
VDD
VIN
Topr'
Tstg

Rating
-3.5 to +0.3
VDD to +0.3
o to +50
-55 to + 150

Unit
V
V

Note
1

'Ct

Note 1: The maximum applicable voltage on any pin with respect to GND.

•

Recommended Operating Conditions
Parameter.
Supply voltage
Oscillator frequency

•

Symbol
VDD
fose

Rating
-3.2 to-2.6
32.768 (TYP.)

(V DD =-3.2 to -2.6V, Ta=O to 50t)

Electrical Characteristics
Parameter

Input voltage

Input current

Output voltage

Output current
Supply current
Note
Note
Note
Note
Note
Note
Note
Note

1:
2:
3:
4:
5:
6:
7:
8:

Symbol
VIH1
VIL1
VIH2
VIL2
IIH
IlL
VOH
VOL
VOA
VOB
Voc
VOD
Iso
ISIN
IDA
IDs
to pins KcK •• fJ IN

Unit
V
kHz

Conditions

MIN.
-0.6

TYP.

MAX.
VDD +0.6

-0.3
VIN=OV
VIN=V DD
Iou1' = 50 p.A to VDD
IOUT=5p.A to GND
VDD =-3.0V
No load
VouT=-0.2V
VOUT=VDD+0.2V
During full-range operation
When system clock is stationary

VDD +0.3
15
15

1
1
-0.5
-0.3
-1.3
-2.3
-3.0
100
100

-1.0
-2.0

40
15

VDD +0.5
0
-0.7
-1.7
-2.7

80
25

Unit
V
V
V
V
p.A
p.A
V
V
V
V
V
V
p.A
p.A
p.A
p.A

Note
1
2

:3
4
5

6

7
8

Applied
Applied to pins ACL. BA
Applied to pins KcK.
Applied to pinfJ
Applied to pins S, -Sa
Applied to pins al-aI6. bl-bIG• bs• HI cH.
Applied to pins Rio Rz
When a bleeder resistor is turned on.

151

4-Bit Microcomputer (LCD Driver)

•

SM510

Pin Functions

K1~~ (Inputs)
The K1-K 4 ports normally pulled down are connected to, and loaded into the accumulator (Ace) by
instructions.
A matrix composed of K input ports and strobe
outplit ports (Sl -Sa) enables up to 32 kinds of keys
to be connected.
In this case, be sure to take the interval at least
1 step between strobe outputs and K inputs.

(1)

(2) BA, 13 (Individual inputs)
The individual input ports BA and f3 normally
- pulled up can be tested using the TAL and TB instructions.
Applying a High level to these ports skips the
next instruction.
(3) S1-Sa (Strobe outputs)
The strobe outputs (Sl -Sa) are used to output an
8-bit W register, and constitute a key input matrix
in. combination with the input ports K1-K 4 •
The W register is an 8-bit register transferred
by the PTW instruction in parallel.
The W'register is an 8-bit shift register of
which the least significant bit WI is set and reset
by WS and WR instructions, and the entire contents of W'register are shifted by one bit.

(4) a1-a16, b 1-b 16 • bs
The segment outputs al-a16, b 1-b 16 are connected to the display RAM. By transferring
appropriate data to the display RAM, alphanumeric
characters are automatically displayed.
The bs is used to output the contents of the L or
Y register. Segment output ports are designed to
drive an LCD with 1I4'duty cycle. The bs is used
to flash the display such as a colon under the control of Y register.
(5) H 1-H 4 (Common outputs)
The H1-H4 are used to drive an LCD with 114
duty cycle and 113 bias, and have the 4 levels of
output.
The common outputs control the BP F IF, BC F I
F to select the display mode or blanking mode.
Below shows the conditions of a display mode to
be selected.
BP=l and BC=O
R (Buzzer output)
The Rl and R2 output ports are used to directly
drive a piezo electric buzzer.
The R port can generate the contents of the R
register with a mask change, and used as a control
signal.
(6)

---------SHARP~--------.-.- ..........

152

4-Bit Microcomputer (LCD Driver)

•

SM510

Hardware Configuration

Program counter and stack
The program counter consists of a 2-bit register
Pu , a 4-bit register RM and a 6-bit polynomial
counter PL. The Pu and PM specify the pages and
the PL specifies the steps within a page.
The stack consists of registers Su, SM, SL and Ru,
RM , RL , and has 2 levels of nesting.
(1)

PM
~

0

(2) Program memory (ROM)
An on-chip 2,772-bit ROM is organized as 44
pagesX63 steps. Fig. 1 shows the ROM configuration.
. When power on, the program starts execution
from the address Pu = 3, PM = 7, PL= 0 specified
by an ACL circuit.

1

2

3

0

0 Subroutine
cover page

Start from
10 CEND

20

30

1

1

11

21

31

2

2

12

22

32

3

3

13

23

33

4

4

14

24

34

5

5

15

25

35

6

6

16

26

36

7

7

17

27

37 Power on

8

8

18

28

38

9

9

19

29

39

A

A

lA

2A

3A

Note:

1 page consists of 63 steps.

Fig. 1

PM
I~

ROM configuration

1

0

0

0

1

1

IIDX~ 10

2

[START]

\\ II::::---

2

12

2

3

3

4

4

/

14

5

5

T)

15

6

6

16

7

7

17

8

8

18

9' 9

19

A

lA

\TM /

A

~

1~
.'\

.........

3

20

30

21

31

[22--23..,

---

32
33 __

\

34

--....

TL(Note2) 25

35

TML(Not~l)

/

26

36

27

37

28

38

29

39

2A

3A

24 ............

[ACL]

Note 1: Jump address of TML, PM=O to 3
Note 2: Jump address of TL, all addresses

Fig. 2

Jump instruction and jump addresser

153

SM510

4...,Bit Microcomputer (LCD Driver)

o

When the program starts execution from the system clock halt state by a IS signal or a key input
signal, the address starts at P u = 1, P M= 0, PL=

0.
o

o

For the instructions except fora jump instruction, the polynomial counter PL is shifted by 1
step according.to a polynomial code.
The combination of jump instructions including
T, TL, TM, TML, RTNO, RTNI and ATPL enables to jump to any page or any subroutine. Fig.
2 shows the relationship between jump instructions and jump addresses on a ROM map.

(3) Data memory RAM
A 512-bit data RAM consists of 8X16X4-bits.
The RAM is specified by a 3-bit BMand a 4-bit
BL. The BM is used to specify the files and the BL
specify the words. Note that 1 word consists of 4
bits.
The SM510 has 2 X 16 X4 bits of display RAM
area out of the entire RAM, and the display RAM is
connected to external pins for segment outputs.
Writing data to the display RAM directly drives
. an LCD with 1/4 duty and 1/3 bias scheme.
Fig. 3 shows the RAM map.
BL
~
0000

x

y

000

001

Z
010

M
011

P

Q

100

101

R
110

S
III

0001
0010
0011
0100
0101
0110'
0111
1000
1001
1010
1011
1100
1101
1110
1111
The area (R. S) enclosed by a thick frame is allocated for a display RAM.

Fig. 3

RAM configuration

(5) Standby function
The SM511/SM512 is a low power consumption
design due to CMOS process. Further low power
feature can also be obtained by halting almost all
the system clocks through the CEND instruction
for low power requirements.
Y F IF must be reset or one or more inputs of
K1 -K 4 must go High in order to restart the system
clock from the halt state. Then the program starts
at the ROM address 1000 (Pu=l, PM=O, PL=O).
(6) Clock generator (CG)
The device contains an on-chip crystal oscillator
circuit which consists of the external circuit shown
in Fig. 4. The system clock has a frequency of one
second that of the oscillator frequency.

OSC IN

SM510
OSCOUT n----4--!

Fig. 4
(7) ACL circuit
Resistors and Capacitors are mounted in an ACL
circuit which does not normally require any external circuits.
The ACL will be cleared in about 0.5 sec from a
crystal oscillator circuit starts oscillation after
power on, and the program starts at P u =3, PM=7,
PL=O.
The ACL operations can be obtained by transferring signals into the ACL pin after power on. Note
that it takes about 0.5 sec to start execution of the
program after the ACL signal is released.
In case noise may harm the ACL operation, apply
a 0.01 to 0.1 JL F of capacitor between ACL pin and
GND pin.

Fig. 5 shows the sample circuit.

(4) Divider circuit for clock function
An internal 15-stage divider circuit is used to
make a clock system.
The divider outputs the signal at 1 sec. unit (IS),
and Y F IF is set at the rising edge of IS signal. Y
F IF can be tested by an instruction, and reset by
the test. A 1 sec. count is notified upon execution
of this instruction.

SM510

ACL

O.OltoO.l,u F

Fig. 5

154

GND

Compensator for ACL

4-Bit Microcomputer (LCD Driver)

SM510

(8) Buzzer output function
The Rl and Rz are buzzer output ports which are
llsed to directly drive a piezo electric buzzer at a
frequency of 4,096kHz with a 32.768kHz crystal
oscillator.
The Rl and R z ports output different pulse
phases which allow the volume control of a buzzer
with the circuit shown in fig. 6. These ports can
directly drive a piezo electric buzzer. However, it
is recommended to use the drive circuits shown in
Figs. 6 and 7, to prevent from the malfunction of a
system caused by the counter electromotive force
from a piezo electric buzzer.
,...-----.....-0 GND

(9) LCD driver
• LCD segment
The SM510 has an on-chip LCD driver circuit
which can directly drive an LCD with a 3V, 1/4
duty and 1/3 bias scheme.
The display RAM is connected to segment outputs of ai, bi (i = 1 to 16) according to LCD common outputs of H1 - H4 as shown in fig 8.
The segment outputs provide I-digit data
(M l -M 4) of the display RAM in synchronizing with
Hl -H 4 outputs.
Each segment of the LCD can be turned on or off
by controlling the corresponding bit data "1" or
"O"in the display RAM area.
The LCD driving waveform relative to the dis·
play mode is automatically generated. The device
provides the maximum of 132 segments. Fig. 9
shows the segment display example.

SM510

R2Lr--------------------------~

(a) Volume control circuit

Fig. 9

--Volume MAX.(b)

_ _ Volume MIN.---;.
Output wavefon;n

Fig. 6

Piezo electric buzzer driver circuit 1

SM510

R,

Piezo
c::J electric

buzzer
GND

Fig. 7

Piezo electric buzzer driver
circuit 2 (Direct driver circuit)

7-segment numeric LCD digit

· Display waveform
Fig. 10 shows the display waveforms required to
display the number "5" on the LCD pattern shown
in Fig. 9 (segment outputs al> b l are used).
In the combination that the potential difference
between the common output and segment output is
3V (in the combination of H4and all, shown in Fig.
10, the segment is turned on, and in the case of 2V
or less (in the combinaiton of H4 and all, the segment is turned off.
· LCD flashing output (bs)
The bs output is used to flash symbols displayed
on the LCD screen. Otherwise, the bs is used as a
segment output in the same way as ai, bi (i = 1 to
16).
· Blanking the display
There are two ways for blanking the entire display depending on applications.
1. For Blanking the display in a short period of
time.

.---------~--SHARP.-~-------

155

[gj
2

4-Bit Microcomputer ,(LCD Driver)

SM510

!

~

~-

BL

r

~.

r 1 1

0000

I

I

I

I

I

I

1

1

0001

I

I

I

I

I

I

1

1

0010

I

r

r

I

I

1

1

1

Rfile

"-

S file

rr-

--

-LCD
dnver

1110
1111

Fig_ 8

r-Tl
~

------VOA(=OV)

--------V
,
. OB (= -IV)

,, .
:

Display RAM and LCD segment output

I

1 :

-----c-~--------Voc(=-2V)

-

'I-------~--------VOD (= -3V)

I

I

I

I

I

I
:

I'
I

I
I

I
I

I
I

:

I

I

I

'---------VOB

I

,-----:--------VOD

I

.

-----1--r-------~-~-----VOA

Hs

I

I

I

I
:I
I

------Voc

:I

-t -~-i-- --t~~~~~~~::
I

------V Oc.

I--~--- -----VOD
I

~

I. -

I

I

.i : : :

:---~- t--~---

I

I

I

----V

f--------.v
,

OA
OB

------Voc

------VOB

---------Voc
~ --- - -'- ----:------VOD
Frame frequency =l/T=64H~'

Fig. 10 LCD driving Signal waveform

156

Control the common signal generator circuit
by the ATBP instruction_
2. For blanking the display in a long period of time
to decrease power consumption.
Use the BDC instruction to turn on· and off the
liquid crystal bleeder current. In this case, cutting off the bleeder current decreases great
amount of power consumption.

4-Bit Microcomputer (LCD Driver)

SM510

Instruction Set

•
(1)

Mnemonic Machine code
LB x

40-4F

LBL xy
(2-byte)

5F
OO-FF

SBM
EXBLA
INCB
DECB

02
OB
64
6C

(2)

(4)

RAM address instructions

Mnemonic Machine code
Operation
Acc+-K
KTA
6A
ATBP
BP+-Acc
01
L+-Acc
ATL
59
ATFC
60
Y-Acc
ATR
61
Ri+-Acc. i=l. 2

Operation
BL3 • BL2 -X (1 3)EBx (1 2)
BLl • BLO-x (1 3• 12)
BMI • BMO-x (110 10 )
BM-x (1 6-1 4). BL -y (1 3-1 0 )
BM2 -1 (only next step)
AcC-BL
Skip if BL =F H. BL-BL+ 1
Skip if BL =0. BL-B L-1

(5)

Operation
Mnemonic Machine code
P L3 -P LO -Acc
ATPL
03
Pu-Su-R u • PM+-SM+-RM
RTNO
6E
PL-SL-RL
Pu+-Su+-Ru. PM+-SM-RM
RTN1
6F
P L-SL -RL• Skip next step
70-7A
TL xyz
PM-X (1 3-1 0 ). Pu+-y (1 7-1 6)
(2-byte) OO-FE
P L-z (1 5-1 0 )

TMx
IDX yz
(2-byte)
T xy

(3)

CO-FE
OO-FE
80-BF

R-S-PC+ 1. P M3 • PM2-(0. 0)
PMI • PMO+-x (110 10 ). Pu+-y (17. 16)
P L+-z (1 5-1 0 )
R-S-PC+1. Pu+-O. PM-O
P L+-x (1 5-1 0 ), Pu+-y (17. 16)
P L-z (15-10). P M-(0100h
P L+-x (1 5-1 0 )

Data transfer instructions

Mnemonic Machine code
EXC x

10-13

BDC

6D

EXClx

14-17

EXCD x

1C-1F

LDA x

18-1B

LAX x

20-2F

WR
WS

62
63

Operation
Acc-M
BM10 BMO +-B M1o BMOEBX (110
BC-C
Display on if C=O
Display off if C= 1
Acc-M
BM10 BMO +-B M1o BMOEBX (110
Skip if BL =F H. BL +-BL + 1
Acc-M
BM10 BMO +-B M1o BMOEBX (110
Skip if BL =0. BL -B L-1
Acc+-M
BM10 BMO +-B M1o BMOEBX (110
Acc-x (l4-ltl
Skip when in succession
W 7+-W 6+-···+-W 0+-0
W 7+-W 6+-···+-W 0+-1

Arithmetic instructions

Mnemonic Machine code
Operation
ADD
08
Acc+-Acc+M
Acc+-Acc+M+C. C-CY
ADD 11 09
Skip if CY=l
Acc+-Acc+x (1 3-1 0 )
30-3F
ADX x
Skip if CY=l
COMA
OA
Acc+-Acc
Acc+-Acc+(1010)2
DC
3A

ROM address instructions

TML XY2 7C-7F
(2-byte) OO-FE

I/O Instructions

10 )

ROT

6B

RC
SC

66
67

(6)

(7)
10 )

'C
C+-O
C+-1

Test instructions

Mnemonic
TB
TC
TAM
TMI x
TAO
TABL
TIS
TAL

TFl
TF4

[Acco-AccI +-... Acc31

Machine code
Operation
51
Skip it f1 =1
52
Skip if C=O
53
Skip if Acc=M
54-57
Skip if M = 1. (i = x (I}, 10))
5A
Skip if Acc = 0
5B
Skip if Acc=BL
58
Skip if 1S=0. Y-O
5E
Skip if BA=l
68
Skip if fl = 1
69
Skip if f4 = 1

Bit manipulation instructions

Mnemonic Machine code
Operation
RMx
04-07
Mi-O. i=(I}, 10)
SM x
OC-OF
Mi+-1. i=(I1o 10)

10 )

(8)
10 )

SpeCial instructions

Mnemonic Machine code
Operation
SKIP
00
No operation
CEND
5D
clock stop
IDIV
65
DIV-O

---.-.----------SHARP -.....-.------....-..------157

4-Bit Microcomputer (LCD Driver)

•

SM510

System Configuration Example (Electronic calculator with real-time clock function)

LCD

DC voltage cutout
O.02t is a divided clock equivalent to 1/4 of the clock applied to pin CK 1•
(15) LCD driver
• Display segment
The SM563 contains an on-chip LCD driver
which can directly drive an LCD with a 1/4 .duty
and 1/3 bias scheme. Fig. 13 shows an example of
LCD segment configuration for 1/4 duty.
Each segment of the LCD can be turned on or off
by software control of the setting of the corresponding bit "I" or "0" in the display RAM area (see
Fig. 3).

Common

H,

0-----

H3

0- - - --

H,

0------

Segment

S31

S'6

Fig. 13

So

LCD segment configuration for 1/4 duty

-----..-.---SHARP-~--------....-.

182

....

4-Bit Microcomputer (LCD Driver)

.-.

SM563

.-.~.-..-.~.-.~~~.-.~.-..-..-..-..-.

The LCD digit may have any shape, provided
that the maximum number of segments does not exceed 128 (see Fig. 13). Fig. 14 shows an example
of a seven-segment numeric LCD digit.

':

:- -: I

_ _ _I ) ( r - - -

I
I

I

I

I

t

I

I

,.. . , -

I
I

I

I

I

I
t

I
I

I
I

- . -1- -t- - 1 - T -

I

I

I

:

I

-- - - - - - ---V Dsp(3V)
,-----------VoA (2V)
t - - - - - - - - -- -V OB(1 V)
.. - - - - - - - - - - -GND(OV)

I

- - - - - - -- Vosp

~

r -

'------------VOA

I

,- ~ -~ - ==~ ------- ~ ~~-~~D
I

Hs

------

" '-

I

I

I

I

:

I

I

I

I

I

t

I

I

,

I

1

I

I _

~

_

I

~
I

7-segment numeric LCD digit

I

I

I

I

- -

- -:- -

_

~

_

~

-

-

-

- -

-

-

---VOB

-

-

-

-GND

__________ ~

V nsp

'--:------------VOA
---------·-VOB

I,
• LCD driving signal waveform
Fig. 15 shows the LCD signal driving waveforms
required to display the number "5" on the 7-segment display shown in Fig. 14 (segment outputs So
and S1 are used). A voltage of 3V is applied to pin
VDSP in the Fig. 15.
The frame frequency (liT) can be selected between 64Hz and 128Hz by mask opticJns.
• VOA and Voe pins
The device contains bleeder resistors to allow 1/
3 bias driving. When VDSP is 3V, voltages of 2V
and 1 V are applied to pins VOA and VoB. respectively.
Normally pins VOA and VOB are left open. When
an LCD with a large display area is driven, connect
capacitors across pins VOA and VDSP and across
VOB and VDSP to improve the rise time of the LCD
driving signal.

1 - - - - - - - - - - - - vOA

I

I

Fig. 14

:

I

- ~ - -} -:- ~ - r - - - - - .- - - - -- V nsp

,-----------GND
I:
I

I

1___________

V nsp.

- - - - - - - - - - -VOA

So

- - - - - - - - - --VOB

,

- - - - - --- - -GND

I

I

I

, __________

,

I
I

--VDSP

----------VOA

- ~ -l.iJ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~~~~~D
I

I

I

I

I

I

I
I

_ _ _v r - - -

.... -----,

,
'-

So

Fig.15

LCD driving signal waveform
(reguired to display the number 5)

183

4-Bit Microcomputer (LCD Driver)

•

SM563

Instruction Set
(1)

ROM address instructions

Mnemonic
TR x
TL xy
(2-byte)

Machine code
Operation
80-BF
PL-x (I5-lo)
EO-EF
PU-x (1 11 -1 4)
OO-FF
PL-y (1 5-1 0)
(SP-2), (SP-3), (SP-4)-PC
SP-SP-4
TRS x
CO-DF
PU-(IOOOOh
PL-x (141)211100)
(SP-2), (SP-3), (SP-4)-PC
CALL xy FO-FF
SP-SP-4, PU-x (111-16),
(2-byte) OO-FF
PL-y (I5-lo)
PU 5-PU 2- X (I3~la),
JBA x
7F
PU" PUo, PL 5, PL 4+-B,
(2-byte) 30-3F
PL 3-PL o-A
PU, PL-(SP), (SP+ 1),
RTN
61
(SP+2)
PU, PL-(SP), (SP+ 1),
RTNS
62
(SP+2), SP-SP+4
PU, PL-(SP), (SP+ 1),
RTNI
63
(SP+2), PSW-(SP+3),
SP-SP+4,IME+-I

(2)

RAM address instructions.

Mnemonic Machine code
Operation
STL
69
L-A
STH
68
H-A
H-D
EXHD
3F
L-E
LIHL xy 3D
H-x (1 7-1 4), L-y (Ia-I a)
(2-byte) OO-FF

(3)

Data transfer instructions

Mnemonic
.EX pr
LDX adr
(2-byte)
STX adr
(2-byte)
EXX adr
(2-byte)
LAX x
LIBA xy
(2-byte)

Machine code
5C-5F
7D
OO-FF
7E
OO-FF
7C
OO-FF
IO-IF
3C
OO-FF

LBAT

60

LDL
LD pr
ST pr
EXH
EXL
EXB
STB
LDB
LDH

65
54-57
58-5B
6C
6D
6E
6A
66
64

PSHBA

,

28

PSHHL

29

POPBA

38

POPHL

39

STSB
STSP
STTC
STTM
LDSB
LDSP
LDTC
LDDIV

70
71
72
73
74
75
76
77

Operation
A-(pr)
A+-(adr)
(adr)+-A
A-(adr)
A-x (I3-lo)
B+-x (17-14)
A +-y (13 - 10)
B+-ROM (PU5-PU2, B, A)H
A+-ROM (PU5-PU2, B, AlL
A+-L
A-(pr)
(pr)-A
A-H
A-L
A-B
B-A
A-B
A-H
(SP-I)+-B, (SP-2)-A,
SP+-SP-2
(SP-I)+-H, (SP- 2)-L,
SP+-SP-2
B+-(SP+ 1), A-(SP),
SP-SP+2
H-(SP+ 1), L-(SP)
SP-SP+2
SB H- B, SBL+-A
SPH-B, SP L+-A
TC-TM
TMH+-B, TML +-A
B-SB H, A-SB L
B-SP H, A+-SP L
B-TC H , A-TC L
B+-DIVH' A+-DIVL

. - - - - - - - - - - S H A R P , ' - . - . . - . - . . . . . . _ _ . . _____ .....-- _ _ _
184

SM563

4-Bit Microcomputer (LCD Driver)

(4)

Arithmetic instructions

Mnemonic Machine code
ADXx

OO-OF

ADD

36

ADDC

37

OR
AND
EOR
ANDB
ORB
EORB
COMA
ROTR
ROTL
INCB
DECB
INCL
DECL

31
32
33
22
21
23
6F
25
35
52
53
50
51
79
DECM ad
OO-FF
78
lNCM adr
OO-FF

(5)

Operation
A ..... A+x (1 3 -1 0 ),
Skip if Cy =1
A ..... A+(HL)
A .....A+(HL)+C, C.....Cy
Skip iF Cy =1
A ..... A V (HL)
A ..... A /\ (HL)
A ..... A$(HL)
A ..... A /\ B
A ..... A V B
A ..... A$B
A .....
C-A 3 -A 2 -A,-A o-C
C..... A 3 ..... A 2 ..... A, ..... A o.....C
B..... B+l, Skip if B=FH
B..... B-l, Skip if B=O
L..... L+l, Skip if L=FH
L..... L-l, Skip if L=O
(adr) .....(adr)-I,
Skip if (adr)=O
(adr) .....(adr)+ 1,
Skip if (adr)=FH

A

Test instructions

Mnemonic Machine code
30
TAM
24
TAH
TAL
34
20
TAB
2A
TC
48-4B
TMx
4C-4F
TAx
TSTT
2B
TSTA
2C
20
TSTS
2E
TSTB
2F .
TSTV

(6)

(7) 1/0 Instructions

Operation
Skip if A=(HL)
Skip if A=H
Skip if A=L
Skip if A=B
Skip if C=O
Skip if (HL) x= 1
Skip if Ax=1
Skip if IFT=I, IFT ..... O
Skip if IFA=I, lFA ..... O
Skip if IFS= 1, IFS ..... O
Skip if IFB= 1, IFB ..... O
Skip if IFV=I, IFB ..... O

Bit manipulation instructions

Mnemonic Machine code
40-43
SM x
44-47
RMx
26
RC
27
SC
3A
RIME
3B
SIME
7F
DIx
(2-byte) CO-OF
EI x
7F
(2-byte) EO-FF

Operation
(HL) x ..... l
(HL) x.....O
C..... O
C..... l
IME ..... O
IME ..... 1

Mnemonic
IN
OUT
INA x
(2-byte)
OUTA x
(2-byte)
INBA x
DUTSA x
(2-byte)
SP xy
(2-byte)
BP xy
(2-byte)
RDS
(2-byte)
RBR
(2-byte)
SDS
(2-byte)
SBR
(2~byte)

READ
(2-byte)
WRIT
(2-byte)
READB
(2-byte)
WRITB
(2-byte)

(8)

Machine code
67
6B
7F
AO-A9
7F
BO-BF
7F
80-81
7F
90-91
7A
00-F3
7B
00-F3
7F
60
7F
70
7F
61
7F
71
7F
62
.7F
72
7F
63
7F
73

Operation
A ..... PO
Pl ..... A
A ..... P (x), R (x)
P (x), R (x) ..... A
B..... R (x+l)
A ..... R (x)
R (x+l) .....B
R (x) .....A
P (y) ..... p (y) x
P (y) ..... p (y) x
DS ..... O
BR ..... O
DS ..... 1
BR ..... O
A ..... P4
with 1001
P4 ..... A
with I R/W I
A ..... P4, with IJ.IDJ
B..... P5
P4 ..... A, with I R/W I
P5 ..... B

Special instructions

Mnemonic
SIO
IDIV
(2-byte)
SKIP
CENO
(2-byte)

Machine code
Operation
3E
Serial I/O start
7F
DIV .....O
10
00
No operation
7F
System clock stop
00

*The
machine code consists of 8-bits of 1
1

7,

0•

16 , .1 5 , 14 , 13 , 12, I, and

•

IEF .....IEF /\ x
IEF V x

185

4-BitMicrocomputer (LCD Driver)

•

SM563

System Configuration Example

buzzer

~

Control signal ( II )

---.-.------SHARP,.--~.-.-,-----.--

186

8-bit Single-chip Microcomputers

Z8 Microcomputer Unit

.LH0801 ILH0801 AlLH0811 ILH0811 A

LH080 l/LH080 lA
LH0811/LH0811A
•

Description

The LH08011 A, LH0811/ A are 8-bit single
chip microcomputers (Z8) which have 2K bytes and
4K bytes of ROM respectively.
The Z8 offers faster' execution; more efficient
use of memory, more sophisticated interrupt, input/output and bit-manipulation capabilities, and
easier system expansion.
Under program control, the Z8 can be tailored to
the needs of its user. It can be configured as a
stand-alone microcomputer with 2K bytes for the
LH08011 A or 4K bytes for the LH081 11 A of internal ROM, a traditional microprocessor that manages up to 124 bytes for the LH0801lA or 120
bytes for the LH0811/ A of external memory, or a
parallel processing device in a system with other
processors and peripheral controllers linked by the
Z-BUS. In all configurations, a large number of
pins remain available .for 110.

•

Pin Conections
LH0801/LH0801A, LH0811/LH0811A

Vee
XTAL2
XTALl

0

P31
P30

RESET

R/W

Features

1. Complete single-chip microcomputer with internal ROM, RAM and 110
RAM capacity: 124 bytes
ROM capacity: 2K bytes (LH080i/ A)
4K bytes (LH0811/ A)
I/O ports: 32
, 2. On-chip two programmable 8-bit
counter/timers, each with a 6-bit
programmable prescaler
3. Full-duplex UART
4. 144 byte register file
5. Register pointer so that short, fast instructions
can access any Working register groups
6.,Vectored, priority interrupts for 110, counter/
timers; and UART
7. Up to 62K bytes for the LH0801/ A or 60K
bytes for the LH0811/ A addressable external
space each for program and data memory
8. On-chip oscillator
9,. Maximum clock frequency ,
8MHz (internal 4MHz): LH0801lLH0811
12MHz (internal 6MHz) :LH0801A1LH0811A

188.

•

ZS Microcomputer Unit

LH0801U/UH0801AU, LH0811U1LH0811AU

RESET 1

R!W

8

Z8 Microcomputer Unit

LH0801/LH0801A/LH0811/LH0811A

10. High speed instruction execution
(8MHz/12MHz)
Working register execution time:
1.5 .u siLO .u s
Average instruction execution time:
2.2 .u sl 1.5 .u s
Maximum instruction execution time:
5.0.u s/3.3.u s
11. Low power standby option which retains contents of general-purpose registers
12. Single +5V power supply
13. All pins are TTL compatible
14. 40-pin DIP (DIP40-P-600):
LH0801/A.LH0811/A
44-pin QFJ (QF]44-P-S650):
LH0801U/AU.LH0811U/AU

•

•

Ordering Information

LH08XX X X

[

Package
Blank: 40-pin DIP (DIP40-P-600)
U: 44-pin QFJ (QF]44-P-S650)

Clock frequency
Blank: 8MHz
A: 12MHz
'------Model No.
LH0801 (On-chip 2K byte ROM)
LH0811 (On-chip 4K byte ROM)

Block Diagram

Vee

GND

)------( l}-------{ll}------{

Machine Timing
&

Instruction Control

ALU
UART
Flags
Counter Timer

Register Pointer

Interrupt Control

(Note) Pin numbers apply to 40-pin DIP.

.-.--..--.-..------SHARP .---..---------.-.-189

Z8 MicrocomputerUnit

•

LH0801/LH0801A/LH0811/LH0811A

Pin Description
Pin
PO O-P0 7
Pl o-P1 7
P2 o-P2 7
P3 0 -P3 7
AS
DS
R/W
RESET
XTALI
XTAL2

•

110
110
110
110
110
0
0
0

Meaning
Port 0
Port 1
Port 2
Port 3
Address Strobe
Data Strobe
Read/Write
Reset
Clock 1
Clock 2

I
I

0

Function
8-bit 110 port, programmable for 110.
Programmable for I/O in bytes.
Programmable for I/O in bits.
P3 0 -P3 3 for input, P3 4 -P3 7 for output.
Active "Low", activated for external address memory transfer.
Active "Low", activated for external data memory transfer.
Read at "High", Write at "Low".
Active "Low", Initializes.
Clock terminal pin.
Clock terminal pin.

Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature
Note 1:

•

Symbol
VIN
VOUT
Topr
Tstg

Ratings
-0.3 to +7
-0.3 to +7
o to +70
-65 to +150

Note

Unit
V
V
·C
·C

1

The maximum applicable voltage on any pin with respect to GND.

(Vee=5V±5%, Ta=O to +70·C)

DC Characteristics
Parameter
Clock input high voltage
Clock input low voltage
Input high voltage
Input low volltage
Reset input high voltage
Reset input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Reset input current
Supply current
Back-up power supply
Note 1:

Symbol
VeH
VeL
VIH
VIL
V RH
VRL
VOH
VOL
IlL
IOL
IIR
lee
VMM

Condition
Driven by external clock oscillator
Driven by external clock oscillator

IoH = - 250,uA
IOL=+2.0mA

MIN.
3.8
-0.3
2.0
-0.3
3.8
-0.3
2.4

TYP.

MAX.
Vee
0.8
Vee
0.8
Vee
0.8
0.4
10
10
-50
180
Vee

-10
-10

OV~VIN~+5.25V

OV ~VIN~ + 5.25V
Vee=5.25V, V RL =OV

3

Power down

Unit
V
V
V
V
V
V
V
V
,uA
,uA
,uA
rnA
V

Note

1
1

I;H= -100 p A and IOL = l.OmA as to Ao- All, MDS, SYNC, SCLK and lACK in LH0802 / A

2.1kO

From output
under test

Vee

Vee

Vee

18kO
From output
under test

o----?--~_M__+

74LS04

Vee
1.5kO

1.5kO

»--~>-I

JoD--+-'--CrystaI2
74LS04;J; CL = 15pF MAX.

250
'----_--Crystall

JlA

Test load 1

I

Test load 2

---~~-----------SHARP

190

CL= 15pF MAX.

External clock generator circuit

-..-..-.-----------

Z8 Microcomputer Unit

LH0801/LH0801A/LH0811/LH0811A

External 1/0 or Mermory Read/Write

•

Parameter

8MHz
MIN.
MAX.
50
70

Symbol

Address valid to AS t delay
AS t to address float dalay
AS t to input data required
valid delay
AS t low width
Address float to DS ~ delay

TdA (AS)
TdAS (A)
TdAS (DR)

1:
2:
3:
4:
5:

(Vcc=5V±5%, Ta=O to +70·C)
12MHz
MIN.
MAX.
35
45

360

TwAS
TdAz (DS)
TwDSR
I Read
DS low width
TwDSW
I Write
DS ~ to input data required valid
TdDSR (DR)
Input data hold time
ThDSR (DS)
DS t to address active delay
TdDS (A)
DS t to AS ~ delay
TdDS (AS)
TdR/W (AS)
Read valid to AS t delay
DS t to read not valid
TdDS (R/W)
Output data valid to DS ~ dalay
TdDW (DSW)
DS t to output data not valid delay TdDS (DW)
Write valid to AS t dalay
TdA (DR)
DS to write not valid delay
TdAS (DS)
Note
Note
Note
Note
Note

(Note1. 2)

80
0
250
160

220
55
0
185
110

200
0
70
70
50
60
50
70

130
0
45
55
30
35
35
45

410
80

255
55

Unit

Note

ns
ns

3,4
3,4

ns

3,4,5

ns
ns
ns

3,4
3,4,5
3,4,5
3,4,5

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

3, 4
3, 4
3,4
3,4
3,4
3, 4
3, 4, 5
3, 4

All timing references use 2.0V for a logic "1" and O.SV for a logic "0".
Test load 1
The timing is defined at the minimum cycle of TpC.
See "Clock Cycle Time Dependency" described later.
Apply double cycle of input clock TpC for the expansion memory timing.

RW

--~)~----------------------------~-4J<~--­
TdDS(R/WlI-'--~

~TdR/W(AS)

PORT 0

DM

1--~)~~~~~~~~==~~~~):==
<_ Do-D,
TdA(DR) TdAS(DR)

----;;.Jt------1H.

PORT 1 _ _..J)r--_-++_A,_l-A_,----rl)

~

IN

TdAS(A)

ThDR(DS)

~TdDSR(DR)----~

AS

1~~)
_ -Ii
DS _ _ _r-_T_w_A_S_~-+-_ _ _,-~
(READ )
I-<-TdAS(DS;=:t{
PORT 1
______J

~

____A_o_-_A_,____J

}

~

<1'-_ _

1
~

TdDS(AS~)---

TWDSR-----ylr--_t-_ __
TdDS(A) I

~::::::::~----D-o--D-,--O-U-T----~~~~t::::JX~ ~-------

TdDW(DSWli-<

DS --------------~~~~~--------~ ~~-----TwDSW
(WRITE )

TdDS(DWlk------4

j;¥--------------

~--------~

~iI

.-..-.-------SHARp.-.-.----,-191

LH0801 ILH0801 AlLH0811 ILH0811 A

Z8Microcomputer Unit

•

Input Clock, Timer Input, Interrupt Request Input
(V cc =+5V±5%, Ta=O to +70'C)
Parameter
Input clock cycle
Input clock rise, fall time
Input clock width
Timer input low width
Timer input high width
Timer input cycle
Timer input rise, fall time
Interrupt request input low time
Interrupt request input high time
Note
Note
Note
Note

1:
2:
3:
4:

CLOCK

SMHz
MIN.
MAX.
TpC
1000
125
25
TrC.TfC
37
TwC
TwTinL
100
3TpC
TwTinH
TpTin
STpC
TrTin. TfTin
100
100
TwIL
3TpC
3TpC
TwIH
Symbol

12MHz
MAX.
MIN.
1000
S3
15
26
70
3TpC
STpC
100
70
3TpC
3TpC

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

. Note
1
1
1
2
2
2
2
2,3
2, 4
2, 3

The clock timing references use 3.8V for a logic "I" and 0.8V for a logic "0".
The timing references use 0.2V for a logic "I" and 0.8V for a logic "0".
Interrupt request from port 3 (P3, - P3 3 ).
Interrupt request from port 3 (P3 0 ).

\1..-_---1)
TfTin

TwTinH

IRQ, t:TWILLWIH=>i'•

Handshake Timing
Parameter

(V cc =5V±5%, Ta=O to +70'C)

(Note 4)

Symbol

TsDI(DAV)
TsDI (DAV)
TwDAV
TdDAVIf
DAV ! input to RDY ! delay time
(RDY)
TdDAVOf
DA V ! output to RDY ! delay time
(RDY)
TdDAVIr
DA V t input to RDY t delay time
(RDY)
TdDAVOr
DA V t output to RDY t delay time
(RDY)
TdDO (DAV)
Data output to DA V! delay time
TdRby
RDY ! input to DAV t delay time
(DAV)

Data input setup time
Data input hold time
Data valid signal input width

Note
Note
Note
Note

192

1:

2:
3:
4:

SMHz
MIN.
MAX.
0
230
175

12MHz
MAX;
MIN.
0
160
120

175

120
0

0
175

120

Unit

Note

ns
ns
ns
ns

1,2

ns

1,3

ns

1,2

0

0

ns

1,3

50

30

ns

1

ns

1

0

200

Test load 1.
Input handshake
Output handshake
All timing references use 2.0V for a logic "I" and 0.8V for a logic "0".

0

140

Z8 Microcomputer Unit

DATA IN

LH0801/LH0801A/LH0811/LH0811A

_ _ _ _-,-._..1

DAV
(Input)
RDY
(Output)

~--TwDAV

TdDAVlr(RDY

TdDAVIf (RDY)-*---jE--

--------...:.;..-...:..........:....~

Input handshake

DATA OUT

DATA OUT VALID

DAV -2T~dDO~(~DA~V:!.)t:::==~
(Output)
TdDAVOr(RDY

RDY
TdDAVOf(RDY)
(Input) ---------..:-...-------"'ll.I+~~

Output handshake

•

Clock Cycle Time Dependency
Symbol
TdA (AS)
TdAS (A)
TdAS (DR)
TwAS
TwDSR
TwDSW
TdDSR (DR)
Td (DS) A
TdDS (AS)
TdR/W (AS)
TdDS(R/W)
TdDW (DSW)
TdDS (DW)
TdA (DR)
TdAS (DS)
Note 1:

8MHz
TpC-75
TpC-55
4TpC-140
TpC-45
3TpC-125
2TpC-90
3TpC-175
TpC-55
TpC-55
TpC-75
TpC-65
TpC-75
TpC-55
5TpC-215
TpC-45

(V cc =5V±5%, Ta=O to +70·C)
12MHz
TpC-50
TpC-40
4TpC-110
TpC-30
3TpC-65
2TpC-55
3TpC-120
TpC-40
TpC-30
TpC-55
TpC-50
TpC-50
TpC-40
5TpC-160
TpC-30

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Note

1
1
1
1

1

Apply double cycle of input clock TpC for the expansion memory timing.

------~------SHARP-.--.---------

193

LH0801/LH0801A/LH0811/LH0811A

Z8 Microcomputer Unit

•

Power Down Standby Option

In low power standby mode, power dissipation
can be reduced with retaining the contents of a
124 byte general-purpose register. Use the
XT AL2 pin as the VMM power supply input with a
bonding option to enter this mode.
Then, an external clock must be input in place of
a crystal oscillator through the XT ALI pin. An
appropriate status must be saved in the register
file with a software control prior to power reduction caused by a power down function or a lack of
power. Fig. 1 shows the example of a power supply
circuit with a battery back-up.

+ 5V O---------

r].r2

6.5

10/12.1 12/14.1

:c
z

JR,

R,

Q)

e.

R,
6.5

I--

10.5

6.0

NOP

~--------~---------~--------------------'-------------y----------~--------------Bytes per Instruction
3
2
3

Execution
Cycles
Upper Opcode
Nibble
-

First

Pipeline Cycles

.----- Mnemonic

Operand

Legend:
'R=8-Bit Address
r =4-Bit Address
RI or rl =Dst Address
R2 or n = Src Address
Sequence:
Opcode. First Operand, Second Operand
Note: The blank areas are not defined.

Second Operand

---'-'-'--'-'-~SHARP ~---.------~-- ........

199

Z8 Microcomputer Unit
(6)

Instruction Summary

I
and Operation I
Instruction

Addr Mode

dst src
(Note 1)
ADC dst,src
dst+-dst+src+C
ADD dst,src
(Note 1 )
dst+-dst + src
ANDdst,src
(Note 1)
dst+-dst AND src
CALL dst
DA
SP+-SP-2
IRR
@SP+-PC;PC+-dst
CCF
C+-NOTC
CLR dst
R
IR
dst+- 0
COM dst
R
dst+-NOT dst
IR
CP dst,src
(Note 1 )
dst+-src
DA dst
R
dst+-DA dst
IR
DEC dst
R
dst+-dst-1
IR
DECW dst
RR
dst+-dst-l
IR
DI
IMR(7)+-0
DJNZ r,dst
RA
r+-r-l
if r o PC+-PC + dst
Range: + 127, -128
EI
IMR(7) +-1
INC dst
r
dst+-dst+l
R
IR
INCW dst
RR
IR
dst+-dst+ 1
IRET
FLAGS+-@SP; SP+-SP+l
PC+-@SP;SP+-SP+2;IMR(7)<-1
JP cc,dst
DA
if cc is true
PC+-dst
IRR
JR cc,dst
RA
if cc is true,
PC+-PC+ dst
Range: + 127, -128
LD dst,src
1M
r
dst+-src
r
R
R
r

LElC dst,src
dst<-src
LDCI dst,src
dst+-src
r<--r + l;rr<--rr + 1
LDE dst,src
dst<--src

200

LH0801/LH0801A/LH0811/LH0811A

Instruction

Opcode Byte Flags Affected
(Hex)
CZSVDH

FF

------

OR dst,src
dst<--dst OR src

(Note 1)

40

-**0--

POP dst
dst<--@SP
SP+-SP+ 1

R
IR

50
51

------

70

- - -

NOP

-**0--

* - - - - -

****--

PUSH src
SP+-SP -1;@SP+-src
RCF
C+-O
RET
PC @SP;SP+-SP+ 2

40
41
00
01
80
81
8F

***x--

RLdst ~ R
c . 7 0
IR

rA
r=O-F

- - - - - -

9F

------

rE
r=O-F
20
21
AO
Al
BF

-***--

BO
B1
60
61
AD

------

-**0--

-***--***-- - -

-

- -

R
IR

AF

**** 1 *

DF

1 - -

R
IR

DO
D1

***0--

1M

31

------

20

****1*

FO
Fl

X**X--

60

-**0--

(Note 1)

SCF
C+-l

l@Jrj;lpJ

TCM dst,src
(Note1)
(NOT dst) AND src

------

------

r
Irr

Irr
r

82
92

(Note 1)
R
IR

- -

TM dst,src
dst AND src

(Note 1)

70

-**0--

XOR dst,src
dst+-dst XOR src

(Note 1 )

BO

-**0--

Note 1 These instructions have an identical set of addressing
modes, which are encoded for brevity. The first ope ode nibble is
found in the instruction set table above. The second nibble is ex·
pressed symbolically by a 0 in this table, and its value is found
in the following table to the left of the applicable addressing mode
pair.
, For example, to determine the opcode of an ADC instruction use
the addressing modes r (destination) and Ir (source). The result is
13

-

------

****

3D

SBC dst,src
dst+-dst - src - C

------

-

10

****

cD
c=O-F
30
cB
c=O-F

-

****--

CO
C1

SWAPdst [~

-

90
91

I{6:[Ii}J
R
C
7 0
IR

RRC dst

0

SRP src
RP+-src

-

- - - -

11

******

X
r
Ir
r
R
IR
1M
1M
R
Irr
r
Irr
Ir

-

- - - -

****

7

0

SUB dst,src
dst +-dst - src

r
X
r
Ir
R
R
R
IR
IR
r
Irr
Ir
Irr

o-

EO
El

C

7

-***--

rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5
C2
D2
C3
D3

- -

Lti]:{"ijJJ IRR
l[i] L["ii]J IRR
C

RR dst

-

71

CF

RLC dst

SRA dst

------

Opcode Byte Flags Affected
(Hex)
C Z SV D H
------

****0*

EF

src

83
93

00

~-----

dst

Irr
Ir

****0*

D6
D4

Addr Mode

LDEI dst,src
Ir
dst<--src
Irr
r<--r + 1; rr+-rr + 1

10

50

I

and Operatidnl

Addr Mode
dst

src

r
R
R
R
IR

r
Ir
R
IR
1M
1M

Lower
Opcode Nibble

i

Z8 Microcomputer Unit

•

LH0801 ILH0801 AlLH0811 ILH0811 A

Register
R244 (TO)
0 Register
(F4H: Read/Write)

R240 (SIO)
Serial I/O Register
(FOH: Read/Write)

Co~nter/Timer

ID71 D61 Dsl D.I D31 D21 DII Do I

ID71 D61 Dsl D.I D31 D21 DII Do I

LTo INITIAL VALUE
(WHEN WRITTEN)
(RANGE: 1-256 DECIMAL
01-00 HEX)
To CURRENT VALUE
(WHEN READ)

[SERIAL DATA (Do=LSB)

R245 (PREO)
Prescaler 0 Register
(F5H: Write Only)

R241 (TMR)
Timer Mode Register
(FlH : Read/Write)

I
-r

LI

D7/ D6 / Ds / D./ D3/ D2/ DI / Do

TOUT MODES
NOT USED=OO
To OUT=01
TI OUT = 10
INTERNAL CLOCK OUT = 11
T IN MODES
EXTERNAL = 00 .
CLOCK INPUT
"GATE INPUT = 01
TRIGGER INPUT = 10
(NON - RETRIGGERABLE)
TRIGGER INPUT =11
(RETRIGGERABLE)

I

I

D71 D6 / Ds / D.I D31 D2/ DilDo

L O~NO
FUNCTION
1-LOAD To

LLCOUNT MODE
O=To SINGLE-PASS

O=DISABLE To COUNT
1=ENABLE To COUNT

1 = To MODULO -N
RESERVED

O=NO FUNCTION
1=LOAD TI
O=DISABLE TI COUNT
1=.ENABLE TI COUNT

ID71 D61 Dsl D.I D31 D21 DII Do I

I~/~I~I~I~I~I~I~I

Lp 20- P 27 I/O DEFINITION
o DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT

LTI INITIAL VALUE
(WHEN WRITTEN)
(RANGE 1-256 DECIMAL 01-00 HEX)
TI CURRENT VALUE
(WHEN READ)

R243 (PRE1)
Prescaler 1 Register
(F3H: Write Only)

R247 (P3M)
Port 3 Mode Register
(F7H: Write Only)

.

COUNT MODE
O=TI SINGLE-PASS
1=TI MODULO-N
CLOCK SOURCE
1=TI INTERNAL
O=TI EXTERNAL TIMING INPUT
(TIN) MODE
PRES CALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

1LL

ID71 D61 DsID.1 D31 D21 DII Do I

IDd D61 Dsl D.I D31 D21 Dd Dol
I

PRES CALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

R246 (P2M)
Port 2 Mode Register
(F6H: Write Only)

R242 (n)
Counter Timer 1 Register
(F2H : Read/Write)

I

I

L 0 PORT 2 PULL-UPS OPEN DRAIN

1 PORT 2 PULL-UPS "ACTIVE
RESERVED
o P 32 = INPUT
P 3s = OUTPUT
1 P32=DAVO/RDYO P3s=RDYO/DAVO
00 P33=INPUT
P3,=OUTPUT
~np33=INPUT
P3,=DM
11 P33=DAV1/RDYl
P3.=RDY1/DAV1
o P31 =INPUT (TIN)
P36=OUTPUT (TOUT)
1 P31=DAV2/RDY2
P36=RDY2/DAV2
o P30=INPUT
P37 =OUTPUT
1 P30=SERIAL IN
P37=SERIAL OUT
o PARITY OFF
1 PARITY ON

201

~
=
~

Q

=

=

LH0801/LH0801A/LH0811/LH0811A

Z8 Microcomputer Unit

R252 (FLAGS)
Flag Register
(FCH: Read/Write)

R248 (P01M)
Port 0 and 1 Mode Register
(F8H: Write Only)

J

I D,I D61 D51 D.I D31 D,I D,I

----r

PO.-PO, MODE
OUTPUT = 00
INPUT=OI
A12-A'5=IX
EXTERNAL MEMORY
TIMING
NORMAL=O
EXTENDED=1

1~1~1~1~1~1~1~1~1

Dol

Llll

C'.

POO-P03 MODE
LOO=OUTPUT
01 = INPUT
lX=As-A ll
STACK SELECTION
O=EXTERNAL
I =INTERNAL
Plo-PI, MODE
OO=BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD7
11 = HIGH ·IMPEDANCE ADo-AD"
AS ,DS, R/W,As-All,AwA15
IF SELECTED

HALF CARRY FLAG
DECIMAL ADJUST FLAG

OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
CARRY FLAG

R253 (RP)
Register Pointer
(FDH: Read/Write)

R249 (IPR)
Interrupt Priority Register
(F9H: Write Only)

RESERVE~ I
(
)
IRQ3,IRQ5 PRIORITY GROUP A

INTERRUPT GROUP
PRIORITY
RESERVED=OOO
0=IRQ5>IRQ3l-..--+-+~-C· > A > B=OOI
I=IRQ3>IRQ5
IRQO, IRQ2 PRIORITY (GROUP B)
A > B > C=OlO
0=IRQ2>IRQO
A > C > B=Oll
I =IRQO>IRQ2
B > C > A = 100
IRQI,IRQ4 PRIORITY (GROUP C)
C > B > A=101
O=IRQI>IRQ4
B > A > C=1I0
I=IRQ4>IRQI
RESERVED=l1l

R250 (IRQ)
Interrupt Request Register
(F AH : Read/Write)

ID71 D61 D51 D.I D31 D,I D, I Dol
r'~J~
~LLDON'T
CARE
r6
DON'T CARE
r5

DON'T CARE
r.

DON'T CARE

REGISTER POINTER

R254 (SPH)
Stack Pointer
(FEH: Read/Write)

ID,I D61 D51 D.I D31 D,I Dd Do I

1

IRQO=P32 INPUT
IRQ 1 = P 33 INPUT
IRQ2=P3, INPUT
IRQ3=P3o INPUT, SERIAL INPUT
IRQ4=To, SERIAL OUTPUT
IRQ5=T,
RESERVED

R251 (IMR)
Interrupt Mask Register
(FBH: Read/Write)

l[ ·

6SER FLAG FI
USER FLAG F2

ID,I D6I D5ID.I D3ID21 DdDol
[ I ENABLES IRQO-IRQ5
(Do=IRQO).

RESERVED

[STACK POINTER UPPER
BYTE (SPS-SP'5)

R255 (SPL)
Stack Pointer
(FFH : Read/Write)

ID71 D61 D51 D.I D31 D21 D, I Do I
[STACK POINTER LOWER
BYTE (SPo-sp,)

I ENABLES INTERRUPTS
......-.-..------SHARP-------~

202

28 Microcomputer Unit (ROM less)

LH0881 ILH0881 A

LH 0881/LH 0881A
•

Description

The LH08811A is a ROMless version of the
LH0801/ A and LH08111 A Z8 single-chip microcomputers and offers the outstanding feature of the
Z8 family architecture.
Because some I/O ports are used for address/
data bus, this device accesses up to 128K bytes of
the external memory space. Using the external
memory in place of an on-chip ROM allows designing more powerful microcomputer system.

•

•

~:or:;;~omputer Unit
Pin Connections

LH0881/LH0881A

Vee
XTAL2
XTALl

0

P3 7
P30
RESET

R/W

Features
1. Complete microcomputer, 24 I/O lines, and up
to 64K bytes addressable external space each
for program and data memory.
2. 143 bytes register file
124 general-purpose registers
3 I/O port registers
16 status and control registers
3. Register pointer so that short, fast instructions
can access anyone of the nine working-register
groups.
4. Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit programmable prescaler.
5. Vectored priority interrupts for I/O, counter/
timers, and UART.
6. On-chip oscillation circuit
7. External clock
8MHz MAX. (internal 4MHz): LH08811U
12MHz MAX. (internal 6MHz): LH0881A1 AU
8. Single + 5V power supply
9. 40-pin DIP (DIP40-P-600)
LH08811LH0881A
44-pin QFJ (QFJ44-P-S650)
LH0881U/LH0881AU

LH0881 U/LH0881AU

RESET 7

R/W

8

•
Ordering Information
LHO 1 X X

r-pa<,

Blank:40- Pin DIP (DIP40-P-600)
U: 44-pin QFJ (QFJ44-P-S650)

Clock frequency
Blank: 8MHz
A: 12MHz
'-----Model No.

,

Top View

203

Z8 Microcomputer Unit (ROM less)

•

LH0881 ILH0881 A

Block Diagram

Vee

GNO

}----'----{ll-'------{ll}--------{

Machine Timing
&

Instruction Control
ALU
UART
Flags
Counter Timer

Register Pointer

Interrupt Control

(Note)

•

Pin numbers apply to 40-pin .DIP.

Pin Description
Pin
PO O-P0 7
Pl o-P1 7
P2 o-P2 7
P3 0 -P3 7
AS
OS
R/W
RESET
XTALl
XTAL2

Meaning
Port 0
PortIo
Address/ data bus
Port 2
Port 3
Address Strobe
Oa,ta Storobe
Read/Write
Reset
Clock 1
Clock 2

I/O
I/O

Function
4 bits X 2, programmable for 110.

lIO

Multiplexed address/data bus

lIO
lIO

Programmable foriiO in bits.
P3 0 -P3 3 for input, P3.-P3 7 for output.
Active "Low", activated for external address memory transfer.
Active "Low", activated for external data memory transfer.
Read at "High", Write at "Low".
Active "Low". Initializes.
Clock terminal pin.
Clock terminal pin.

0
0
0
/

I
I

0

Pin functions of the LH08811 A are identical to those of the LH08011 A, LH081 11 A, except for pins Pl o-PI 7 •

.....-.-.------....------SHARP -----~.----.-.
204

LH0881 ILH0881 A

Z8 Microcomputer Unit (ROM less)

•

Address space

(1) Program Memory
The LH08811 A, having a 16-bit program counter, addresses 64K -bytes of external program
memory. All the command codes are fatched from
these external program memories.
For the LH08811 A, the first 12 bytes of program memory are reserved for the interrupt vectors.
These locations contain six 16-bit vectors that
correspond to the six available interrupts. Program
execution begins at location OOOCH after a reset.
Data Memory
The LH08811 A can address 64K bytes of external data memory. External data memory may be included with or separated from the external program memory space. DM, an optional I/O function
that can be programmed to appear on pin P3 b is
used to distinguish between data and program
memory space.
(2)

(3) Register File
The 143-byte register file includes three I/O
port registers (RO, R2, R3), 124 general-purpose

registers (R4-R127) and 16 control and status registers (R240-R255).
These registers are assigned the address locations shown in Fig 2.
LH08811 A instructions can access registers
directly or indirectly with an 8-bit address field.
This also allows short 4-bit register addressing
using the Register Pointer (one of control registers). In the 4-bit mode, the register file is divided
into nine working register groups, each occupying
16 contiguous locations. The Register Pointer
addresses the starting location of the active working-register group.
Satcks
Either the internal register file or the external
data memory can be used for the stack. A 16-bit
Stack Pointer (R254 and R255) is used for the ex'een,1
whkh "n
,.ywhm in
memory. An 8-bit Stack Pointer (R255) is used for
the internal stack that resides within the 124
general-purpose registers (R4-R127).
(4)

""k.

,,,ide

LOCATION
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240

65,535

Location of fir st
byte of instruc tion
executed after

r~

Interrupt
vector
(Lower byte)
Interrupt
vector
(Upper byte)

12
11
10
9
8

~--------------~-

7
6
51'"4f;,-3
2

1
0

IRQ5
IRQ5
IRQ4
IRQ4
lRQ3
IRQ3
IRQ2
IRQ2
IRQl
IRQl
IRQO
IRQO

Fig. 1 Program memory map

External
memory

d",

IDENTIFIERS
STACK POINTER (BITS 7 0)
STACK POINTER (BITS 15 8)
REGISTER POINTER
PROGRAM CONTROL FLAGS
INTERRUPT MASK REGISTER
INTERRUPT PRIORITY REGISTER
INTERRUPT PRIORITY REGISTER
PORTS 0-1 MODE
PORT 3 MODE
PORT 2 MODE
TO PRESCALER
TIMER/COUNTER 0
Tl PRESCALER
TIMER/COUNTER 1
TIMER MODE
SERIAL I/O

SI'L
SPH

Rl'
FLAGS
IMR
IRO
IPR
POIM
P3M
P2M
PREO
TO
PREI
Tl
TMR
SIO

NOT
IMPLEMENTED
127

GENERAL - PURPOSE
REGISTERS

4
3

2
1

o

PORT 3
PORT 2
NOT IMPLEMENTED
PORT 0

P3
P2
PO

Fig. 2 The register file

205

Is

Z8 Microcomputer Unit (ROM less)

•

LH0881/LH0881 A

Port Functions

•

The LH0881/ A has a dedicated memory interface port (Port 1) and input/output ports (Port 0,
2, 3). These ports are. given eight lines each. The
funtions of Port 0, 2 and 3 are the same as those of
the LH0801/ A, LH0811/ A.
Port 1 is a dedicated Z-bus compatible memory
interface. The operations of Port 1 are supported
by the Address Strobe (AS) and Data Strobe (DS)
lines, and by the Read/Write (R/W) and Data Memory (DM) control lines.
The low-order program and data memory
address (Ao-A7) are output through Port 1 and are
multiplexed with data in/out (Do-D7)' Instruction
fetch and data memory read/write operations are
done through this port.
Port 1 cannot be used as a register nor can a
handshake mode be used with this port.
If more than eight address lines are reqired with
the LH0881/ A, additional lines can be obtained by
programming Port 0 bits as address bits. The leastsignificant four bits of port 0 can be configured to
supply address bits As-All for 4K byte addressing or both nibbles of Port 0 can be configured to
supply address bits As- A15 for 64K byte addressing.

Fig 3

Registers

The LH0881/ A control registers are the same as
on the LH8011 A, LH0811!A, except two bits D3
and D4 in the Port 0, 1 Mode Register (R248).

•

Serial Input/Output

The LH0881 / A serial input/output functions
are the same as those of the LH08011 A, LH0811/
A. (Refer back to the LH08011 A description.)

•

Counter/Timers

The LH0881/ A counter/timer functions are the
same as those of the LH0801/ A, LH081 11 A, (Refer back to the LH08011 A description.)

•

Interrupts

The LH08811 A interrupt functions are the same
as those of the LH08011 A, LH0811/ A, (Refer back
to the LH0801l A description.)

•

·Instructions and AC/DC Characteristics

These data of the LH0881/ A are the same as for
the LH0881/ A, LH0811/ A. (Refer back to the
LH0801/ A description.)

R248 (P01 M) Port 0, 1 Mode Register (F8 H Write only)

I 07 I 06 I D" I D, I D,
PO,-PO,

MOOE~

OUTPUT=OO~
INPUT=Ol
A 12 -A 15=lX

EXTERNAL MEMORY TIMING
NORMAL=O--~--~~

* EXTENOEO= 1

~
PO" I'll;, MODE
LOO=OUTI'UT
Ol=lNPUT
lX=A5 All
STACK SELECTION
~------O=EXTERNAL

l=INTERNAL
'-------------RESERVEO (MUST BE 0)

206

I

I.

CMOS 8-Bit Single Chip M!crocomuputer

SM803/SM803A1SM80S/SM80SA

SM803/SM803A
SM805/SM805A
•

CMOS 8-Bit Single Chip
Microcomuputers

Description

•

The SM8031 A, SM8051 A are CMOS 8-bit single chip microcomputers which have 4K bytes and
8K bytes of ROM respectively.
The devices offer faster execution; more efficient
use of memory, more sophisticated interrupt, input/output and bit-manipulation capabilities, and
easier system expansion.
Under program control, the devices can be tailored to the user's needs. It can be configured as a
stand-alone microcomputer with 4K bytes for the
SM8031 A or 8K bytes for the SM8051 A of internal ROM, a traditional microprocessor that manages up to 120 bytes for the SM803/A or 112
bytes for the SM8051 A of external memory, or a
parallel processing device in a system with other
processors and peripheral controllers linked by the
BUS. In all configurations, a large number of pins
remain available for 110.

Pin Connections

SM803/SM803A
SM805/SM805A

SM803U/SM803AU
SM805U/SM803AU

SM803M/SM803AM
SM805M/SM805AM

:1

u

.... ""

z

.... ...l

~..,;:;: ij~

~~><><>(,!)

CD

_

CD

t-

~

~

CO>

~

..::
E-<
><

~

CO>

~

.;;

~

~

""

~

~

~

~

""

~

Ir,I

('I')

C¥')

~

N

N

~

~

~

~

~

NC

RESET

P2.
P23
P22
P2.!
P20
P33
P3.
Ph
P16
Ph

R/W

DS
AS
P35

.GND
P32
PO o
PO;
P02

NC

RESET

7

R/W

8

0

AS

P32
POo
POI

p02
NC

oo~~o52

~~~~~(,!)

u

ii

0

CO>

Q.

_

ON

""

"'"

P:5:P::P:P::

M

<::>

~

~

<::>

~

~

0
~

& Q

~

~

..

p:; p:; ~....
0

~,,,:

~

~

~----'-"""-"""-'~'-SHARP -.------~--~

207

SM803/SM803A1SM80S/SM80SA

CMOS 8-Bit Single Chip Microcomuputer

•

10. High speed instruction execution
(8MHzI12MHz)
Working register execution time:
1.5 fL siLO fL s
Average instruction execution time:
2.2 fL s/1.5 fL s
Maximum instruction execution time:
5.0 fL s/3.3 fL s
11. Single + 5V power supply
12. 40-pin DIP (DIP40- P-600):

Features
1. Complete single-chip microcomputer with internalROM, RAM and 110
RAM capacity: 124 bytes (SM8031 A)
: 236 bytes (SM8051 A)
ROM capacity: 4K bytes (SM8031 A)
: 8K bytes (SM8051 A)
110 ports: 32
2. On-chip two programmable 8-bit
couter/timers, each with a 6-bit programmable
prescaler
3. Ful1-duplex UART
4. 144 byte register file (SM8031 A)
256 byte register file (SM8051 A)
5. Register pointer so that short, fast instructions
can access any working register groups
6. Vectored, priority interrupts for 1/0, counter I
timers, and UART
7. Up to 60K bytes for the SM8031 A or 56K
bytes for the SM8051 A addressable external
space each for program and data memory
S. On-chip oscillator
9. Maximum clock frequency
8MHz (internal 4MHz): SM803/SMS05
8MHz (internal 6MHz): SM803A/SM805A

•

SM8031 A, SM8051 A

44-'pin QFP (QFP44-P-1414)
SM803MI AM, SM805MI AM
44-pin QFJ (QFJ44-P-S650):
SM803UI AU, SM805U1 AU

•

Ordering Information

SM80X X X

Package
Blank: 4,0, -pin DIP (D"IP, 40- P-600)
M: 44-pin QFP (QFP44-P-1414)
U: 44-pin QFJ (QFJ44-P-S650)
Clock frequency
Blank: 8MHz
A: 12MHz
L---Model No.
SM803 (On-chip 4K byte ROM)
S.M805 (On-chip 8K byte ROM)
[

Block Diagram

GND

Vee

Machine Timing
&
Instruction Control

ALU
UART
Flags
Counter ITimer

Register Pointer

Note: Pin numbers apply to 40cpin DIP.

~----~----------SHARP

208

-

............ ~--------.-

I

SM803/SM803A1SM805/SM805A

CMOS 8-Bit Single Chip Microcomuputer

•

Pin Description
Pin
PO O -P0 7
P1 o -P1 7
P2 o -P2 7
P3 0 -P3 7
AS
DS
R/W
RESET
XTALl
XTAL2

•

Meaning
Port 0
Port 1
Port 2
Port 3
Address Strobe
Data Strobe
Read/Write
Reset
Clock 1
Clock 2

Function
S-bit I/O port, programmable for I/O.
Programmable for I/O in btyes.
Programmable for I/O in bits.
P3 o-P3 3 for input, P3 4 -P3 7 for output.
Active "Low", activated for external address memory transfer.
Active "Low", activated for external data memory transfer.
Read at "High", Write at "Low".
Active "Low". Initializes.
Clock terminal pin.
Clock terminal pin.

I/O
I/O
110
I/O
I/O
0
0
0
I
I
0

Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperatuer
Note:

•

Symbol
VIN
VOUT
Topr
Tstg

Ratings
-0.3 to Vee
-0.3 to Vee
o to +70
-65to+150

Unit
V
V
·C

Note
1

"C

The maximum applicable voltage on any pin with respect to GND.

(Vce=5V± 10%, Ta=O to +70·C)

DC Characteristics
Parameter

Clock input high voltage
Clock input low voltage
Input high voltage
(handshaking)
Input low voltage
(handshaking)
Reset input high voltage
Reset input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Reset input current
Supply current
Standby current
Notel:

Symbol

Condition

VeH
VCL

Driven by external clock oscillator
Driven by external clock oscillator

VlH
V IL
V RH
V RL
VOH
VOL
IlL
IOL
IIR
Iec
IcC!
lec2

IoH = -250 fl A
IOL=+2.0mA
OV~VIN~+5.5V

OV:O;:V IN :O;:+5.5V
Vce=5.5V, VRL=OV

SMHz
MIN.
MAX.
3.S
Vee
-0.3
O.S
2.0
Vee
(2.2)
-0.3
0.8
(0.5)
3.8
Vee
-0.3
0.8
2.4
0.4
-10
10
-10
10

12MHz
MIN.
MAX.
3.S
Vee
-0.3
0.8
2.0
Vee
(2.2)
-0.3
0.8
(0.5)
3.8
Vee
-0.3
0.8
2.4
0.4
-10
10
-10
10

Unit

Note

V
V
V

1

V
V
V
V
V
flA
flA
flA

HALT instruction
STOP intstruction

10
200

7
200

rnA
rnA
flA

For the SM8051 A, the minimum value should be 2.2V as well as when handshaking.

Vee
Vee

Vee

2.1 kO
From output
under test

Clock in

:>0>---+--- Crystal 2
*CL=15 PF MAX.
'--------'l>----Crystal1
lCL=15 PF MAX.

Test load 1

External clock generator circuit

---'-"~-------SHARP-------'-'

209

CMOS a':"SitSingle Chip Microcomuputer

External 1/0 or Memory ReadlWrite

•

Parameter

Symbol

Address valid to ASt delay
AS t to input data required
valid delay
AS t low width
,I Read
DS.low width
Write
DS ~ to input data required valid
Input data hold time
DS t to address active delay
DS t to AS ~ delay
Read valid to AS t delay
DS t to read not valid
Output data valid to DS ~ delay
DS t to output data not valid delay
Write valid to AS t delay
DS to write not valid delay

TdA (AS)

I

Note
Note
Note
Note

1:
2:
3:
4:

SM803/SM803AlSM805/SM805A

,8MHz
MIN.
MAX.
50

TdAS(DR)
TwAS
TwDSR
TwDSW
TdDSR (DR)
ThDSR (DS)
TdDS (A)
TdDS (AS)
TdR/W (AS)
TdDS (R/W)
TdDW (DSW
TdDS (DW)
TdA (DR)
TdAS (DS)

(V cc =5V±10%, Ta=O to +70·C)

(Note 1)

12MHz
MIN.
MAX.
35
220

360
80
250

55
185
110

160
200
0
70
70
50
60
50
70

130
0
45
55
30
35
35
45

410
80

255
55

Unit

Note

ns

2,3

ns

2,3,4

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

2,3
2,3,4
2,3.4
2,3.4
2
2, 3
2. 3
2. 3
2.3
2.3
2.3
2. 3, 4
2, 3

All timing references use 2.0 V for a logic "1" and 0.8 V for a logic "0".,
Test load 1
The timing is defined at the minimum cycle of TpC.
Apply double cycle of input clock TpC for the expansion memory timing.

R!W

,l<

~

~Tdj)S(R!W)

~TdR!W(AS)

PORTO
DM
PORT!

~

TaA(DR)

)~

~
TdAS(DR)

TdMAsil/
k-TwAS-

DS
(READ)
PORT!

TdDSR(DR)
TdA(DS)~

TwDSR

*-TdAS(DS)J
Ao-A,

,210

--Td"nS(~
'j?
TdDS(A)

)(

,~

Do-D, OUT
TdDW(DSW)

DS
(WRITE)

<

~ThDR(DS)

TaAS(A)
AS

}



-y

T;"DSW

,~

~

TdDS(DW)

SM803lSM803AlSM80SlSM80SA

CMOS 8-Bit Single Chip Microcomuputer

•

Input Clock, Timer Input, Interrupt Request Input
(V cc= 5V ± 10%, to=O to + 70"C)
Symbol

Parameter
Input clock cycle
Input clock rise, fall time
Input clock width
Timer input low widtl>
Timer input high width
Timer input cycle
Timer input rise, fall time

TpC
TrC, TfC
TwC
TwTinL
TwTinH
TpTin
TrTin. TfTin

Interrupt request input low time

TwIL

Interrupt request input high time

TwIH

Note
Note
Note
Note

1:
2:
3:
4:

Unit

Note

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

1
1
1
2
2
2
2
2, 3
2,4
2, 3

Handshake Timing
Parameter

TWC={

(Vcc=5V± 10%, Ta=O to +70·C)

(Note 1)

Symbol

TsDI (DAV)
ThDI (DAV)
TwDAV
TdDAVIf
DA V ~ input to ROY ~ delay time
(ROY)
TdDAVOf
DA V ~ output to ROY ~ delay time
(ROY)
TdDAVIr
DA V t input to RDY t delay time
(ROY)
TdDAVOr
DA V t output to ROY t delay time
(ROY)
TdDO (DAV)
Data output to DAV ~ delay time
TdRDY
RDY ~ input to DA V t delay time
(DAV)
Data input setup time
Data input hold time
Data valid signal input width

}=

It Tfe :!CCl:TwCj

.... _ _ _..J
TfTin

•

12MHz
MIN.
MAX.
S3
1000
15
2.6
70
3TpC
STpC
100
70
3TpC
3TpC

The clock timing references use 3.SV for a logic" 1" and O.SV for logic "0".
The timing references use 2.0V (2.2V for SMS051 A) for a logic "1" and O.SV for a logic "0".
Interrupt request from port 3 (P3[-P3,).
Interrupt request from port 3 (P3 0 ).

) . . - - TpC
CLOCK \

SMHz
MIN.
MAX.
125
1000
25
37
100
3TpC
STpC
100
100
3TpC
3TpC

SMHz
MIN.
MAX.
0
230
175

12MHz
MIN.
MAX.
0
160
120

175

120
0

0
175

120

Unit

Note

ns
ns
ns
ns

2, 3

ns

2, 4

ns

2,3,5

~-

Note
Note
Note
Note
Note

1:
2:
3:
4:
5:

0

0

ns

2, 4

50

30

ns

2

ns

2

0

200

0

140

All timing references use 2.0V for a logic "1" and O.SV for a logic "0".
Test load 1.
Input handshake
Output handshake
When read out from the port before DA V t input.

~---------SHARP-----'--'--

211

CMOS 8-Bit Single Chip Microcomuputer

•

Architecture

(1) Address Spaces
( i) Program Memory
The 16-bit program
counter addresses 64K· bytes of program memory
space. Program memory can be located ih two areas
: one internal and the other external (Fig. 2). The
first 2048 bytes consist of on-chip mask-prog·
rammed ROM. At addresses 2048 and greater, the
Z8 executes external program memory fetches.
The first 12 bytes of program memory are reo
served for the interrupt vectors. These locations
'contain six 16-bit vectors that correspond to the
six available interrupts.
(ii) Data Memory
The Z8 can address 62K
bytes of external data memory beginnil1;g at loca·
tion 2048 (Fig. 3). External data memory may be
include with or separated from the external prog·
ram memory space. DM, an. optical I/O function
that can be programmed to appear on pin P3 4 , is
used to distinguish between data and program
memory. space.
(iii) Register File
The 144-byte register
file includes four I/O port registers (RO-R3), 124
general-purpose registers (R4-R127) and 16 con·
trol and status registers (R240-R255). These registers are assigned the address locations shown in
Fig. 4.
Z8 instructions can accesS reIDsters directly or
indirectly with an 8-bit address field. The Z8 also
allows short4~bit register addressing using the

212

SM803lSM803AlSM805lSM805A

Register Pointer (one of the control registers). In
the 4-bit mode, the register file is divided into nine
working-register groups, each occupying 16 contiguous locations. The Register Pointer addresses
the starting location of the active working-regsister group.
The 4-bit address specifies the nth (0 to 15)
address from the starting location (see Fig. 5),
'" The addresses OEOH-OEF H of SM805 register file can not be
directly accessed due to the essential function of the register pointer. Either of the following two methods is available for accessing
those 16 registers.

1)

Working register addressing
SRP # OEOH (set the RP to OEOH )
2) Register indirect addressing
ex.) LD 70H, # OEOH
. LD 40H, @70H (read)
LD @70H, 40H (write)
(iv) Stacks
.Either the internal register file
or the external data memory can be· used for the
stack. A 16-bit Stack Pointer (R254 and R255) is
~sedfor the external stack, which can reside anywhere in data memory between locations 4096
(8192 for SM805/A) and 65535. An 8-bit Stack
Pointer (R255) is used for the internal stack that
resides within the 124 (236 for SM8051 A) general-purpose registers.
Either an internal stack or an external stack may
. be selected with ports 0, 1 and the bit D2 of mode
register (248). The internal stack is specified with
the device to be reset.

CMOS 8-Bit Single Chip Microcomuputer

SM803/SM803A1SM80S/SM80SA

5,535
65,535 , - - - - - - - - - - - - - - - ,
External ROM or RAM
4,.096/8 ,192*
Location of firs t
byte of instructi
O~t\
excuted after reset

Interrupt vector
(Lower byte)

On-chip ROM
-------------------------------------.-----------------------

121'\0\
11

IRQ 5

10

IRQ 5

9

IRQ 4

8

IRQ 4

7

IRQ 3

~

IRQ 3

Interrupt vector
(Upper byte)

* SM803/ A=4,096

5~

IRQ2

41,#

IRQ2

3

IRQ 1

2

IRQ 1

1

IRQ 0

0

IRQ 0

External data memory

4,096/8,192* I--~~~~~~~~~~------j

Not addressable

OL-__________________

~

SM805/ A=8,192

Fig, 2

Program memory map

Fig. 3

Data memory map

IDENTIFIERS

LOCATION
255

STACK POINTER (BITS 7-0)

SPL

254

STACK POINTER (BITS 15-8)

SPH

253

REGISTER POINTER

252

PROGRAM CONTROL FLAGS

251

INTERRUPT MASK REGISTER

IMR

250

INTERRUPT REQUEST REGISTER

IRQ

249

INTERRUPT PRIORITY REGISTER

IPR

248

PORTS 0-1 MODE

P01M

247

PORT 3 MODE

P3M

246

PORT 2 MODE

P2M

245

TO PRESCALER

PREO

244

TIMER/COUNTER a

243

T 1 PRESCALER

242

TIMER/COUNTER 1

241

TIMER MODE

240

SERIAL I/O

239

NOT
IMPLEMENTED
FOR SM803/A

RP

-_-{--::::r===t--------------,

I __

FLAGS

TO
PRE1

255/255

I---,-,--",---,,,--,,-,---,-----,--",--c---'---I 253/253
'------------~-------' 240/240
The upper nibble of the register file address
provided by the register pointer specifies the
active working-register group.

127 /239

---{
---{

112/ 224
lll/ 223
96/2 08

T1
TMR
SIO

127
GENERAL-PURPOSE
REGISTER

4
3

PORT 3

P3

2

PORT 2

P2

1

PORT 1

PI

o

PORTO

P.o

Fig. 4 The register file

SM803/SM805

---{
----{
---{
---{
----{

63
SPECIFIED WORKING- ..,.
~
REGISTER GROUP
48
47

The lower nibble
of the register
file address
provided by the
instruction
points to the
specified
register

32
31

---.----------

16
15
------------------------- -----_._--- 3
I/O Ports
.0
Register file

Fig. 5 The register pointer

--------SHARP---------213

CMOS 8:... Bit Single Chip Micr,ocomuputer

SM803/SM803A1SM805ISM805A

I/O po,rts
The 28 has 32 lines dedicated to input and output. These lines are grouped into four ports of
eight lines each and are configurable as input, output or address/data" Under software control, the
ports can be programmed to provide address outputs, timing, status signals; serial 110, and parallel
110 with or without handshake. All ports have active pull-ups and pull-downscompatible with TTL
loads.
( i ), Port 1 can be programmed as a byte 110
port or an address/data port for interfacing external memory.
Memory locations greater than 4095 (8191 for
SM805/ A) are referenced through Port 1. To interface external memory, Port 1 must be programmed for the multiplexed Adress/Data mode. If more
than 257 external locations are required, Port
must output the additional lines.
(ii) Port can be programmed as a nibble 110
port, or as an address port for interfacing external
memory.
For external memory references, Port can provide address bits AsAl1 (lower nibble) or As- AI5
(lower and upper nibble) depending on the required
address space.
(iii) Port 2 bits can be, programmed independently as input or output. The port is always available for 110 operations. In addition, Port 2 can be
configured to provide open-drain outputs.
(iv) Port 3 lines can be configured as 110 or
control lines. In either cases, the direction of the
eight iines is fixed as four input (P3 0 -P3 3) and
four output (P3 4 -P3 7 ). For serial 110, lines 1'3 0
and P3 7 are programmed as serial in and serial out
respectively
•
handshake for Ports 0, 1 ind 2 (DA V and
RDY)
•
four external interrupt request signals
(IRQo-IRQ3)
•
timer input and output signals (TIN and
(2)

°

°

°

TOUT)

•

Data Memory Select (DM).

(3) Serial Input/Output
Port 3 lines P3 0 and' P3 7 can be programmed as
serial 110 lines for full-duplex serial asynchro-'
nous receiver/transmitter operation. The bit rate
is controlled by Counter/Timer 0, with a maximum
rate of 62.5K -bits/second.
The device autolI\atically adds a start bit and
two stop bits to transmitted data (Fig. 6). Odd parity is also aviliable as an option.

(4) Counter/Timer
The device contains two 8-bit programmable
counter/timers (To and T I ), each driven by its own
6-bit programmable prescaler. The T 1 prescaler
can be driven by internal or external clock
sources; however, the To prescaler is driven by the
internal clock only.
'
The counters can be started; stopped, restarted
to continue, or restarted from the initial value. The
counters can also be programmed to stop upon
reaching zero (single-pass mode) or to automatically reload the initial value and continue counting
(modulo-n continuos mode). The conters, but not
the prescalers, can be read any time without disturbing their value or count mode.
(5) Interrupts
The device allows six different interrupts from
eight sources: the four Port 3 lines P3 0 -P3 3, Serial
In, Serial Out, and the two conter/timers. These interrupts are both maskable and prioritized.
All device interrupts are vectored. Polled interrupt systems are also supported.

Transmitted Data (No Parity)

Transmitted Data (With Parity)

Received Data (No Parity)

1~1~1~1~1~1~IThIThI~I~1

'I

I

,

LSTART BIT
EIGHT DATA BITS
ONE STOP BITS

Received Data (With Parity)

1&lpl~l~t~IThIThIThI~ISTI

'I

LSTART BIT
SEVEN DATA BITS
PARITY ERROR FLAGS
' - - - - - - - - - - - - O N E STOP BITS

II

Fig. 6 Serial data formats

--------SHARP-------214

I'
I::

SM803/SM803A1SM80S/SM80SA

CMOS 8-Bit Single Chip Microcomuputer

•

Instruction Set Notation

(1) Addressing modes
The following notation is used to describe the
addressing modes and instruction _operations as
.
shown in the instruction summary.
IRR
Irr
X
DA
RA
1M
R
r
IR
Ir
RR

Indirect register pair or indirect
working-register pair address
Indirect working-register pair only
Indexed address
Direct address
Relative address
Immediate
Register or working-register address
Working-register address only
Indirect-register or indirect working-register address
Indirect working-register address only
Register pair or working register pair
address

(2) Symbols
The following symbols are used in describing -the
instruction set.
dst
Destination location or contents
src
Source location or contents
cc
Condition code (see list)
@
Indirect address prefix
SP
Stack pointer (control registers 254-255)
PC
Program counter
Table 1
Value
1000
0111
1111
0110
1110
1101
0101
0100
1'100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000.

Mnemonic
C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

FLAGS Flag register (control register 252)
Register pointer (control register 253)
RP
Interrupt mask register (control register
IMR
251)
Assignment ofa value is indicated by .the symbol
".... ". For example.
dst .... dst + src
indicates that the source data is added to the destination data and the result is stored in the destination location. The notation "addr (n)" is used to refer to bit "n" of a given location. For example,
dst (7) refers to bit 7 of the destination operand.

(3) Flags.
Control Register R252 contains the following six
flags:
C
Carry flag
Z
Zero flag
S
Sign flag
V
Overflow flag
D
Decimal-adjust flag
H
Half-carry flag
Affected flags are indicated by :
o
Cleared to zero
1
Set to one
Set or cleared according to operation
Unaffected
X
Undefined
(4) Condition codes
See Table 1.

*

Condition codes

Meaning
Always true
Carry
No carry
Zero
Not Zero
Plus
Minus Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater thim
Unsigned less than or equal
Never true

......

Flags set

C=l
C=O
Z=l
Z=O
S=O
S=l
V~1.

V=O
Z=l
Z=O
(S XOR V) =0
(S XOR V) ~1
[Z OR (S XOR V)) =0
[z qR (S XOR V)) =1
C=O
C=l
(C=OANDZ=O) =1
(C OR Z) =1

......

215

CMOS a-Bit Single Chip Microcomuputer

SM803/SM803A1SM805/SM805A

(5) Opcode map
Lower Nibble (Hex)

o
o

6.5

IR,

rio rz

6.5

6.5

6.5

5
6

><
Q)

:c
.0

Z
GiCo

8
9
A

F

10.5

6.5

6.5

12/10.5 12/10.0

LD

LD

DJNZ

JRIoIM

Tit H2

rz. R\

10.5

10.5

10.5

10.5

6.5

1H z• Rl

R\,IM

IRIoIM

10.5

10.5

10.5

10.5

IR,

rio rz

rit Irz

R 2 ,R 1

IR:.!t RI

6.1

6.5

6.5

10.5

10.5

10.5

10.5

fRR\

1M

rl. r2

rio Ir2

Hz. RI

IHz.H I

R1,IM

IRI.I-M

8.5

8.5

6.5

DA

OR

10.5

10.5

10.5

DA

6.5

10.5

OR

OR

OR

OR

OR

Tit

RA

JR
ce, RA

D

6.5

12/1.0.0

6.5

JP

INC

ce, DA

r,

LD
rh

1M

F

E

C

-

rl

t

r2

I-----

INC SUB SUB SUB SUB SUB SUB
Rl>lM IRi. IM

I-----

SRP SBC SBC SBC SBC SBC SBC

R,

IR,

10.5

10.5

rl

t

r2

rl

6.5

R2.Rl

1H z• RI

R],IM

IRIoIM

6.5

10.5

10.5

10.5

10.5

Hz. R.
10.5

1H z• HI

R\,IM

IR1.IM

10.5

10.5

10.5

IR1.IM

t

Irz

r--I-----

POP POP AND AND AND AND AND AND
R,

IR,

rl. r2

r"lrz

6.5

6.5

6.5

6.5

r--6.0
STOP

COM COM TCM TCM TCM TCM TCM TCM
IR,

rl

t

rz

r]. Irz

Hz. RI

1H 2 • RI

Rl.IM

6.5

10.5

10.5

10.5

6.5

PUSH PUSH TM
IL

IR,

rio r2

10.5

10.5

12.0

TM

10.5

----;;:0-

TM

TM

TM

HALT

Rz,Ri

1H z• R\

HI.IM

IRI.IM

TM
rl

t

lr2

co:!

.18.0

DECV'I DECV'I LDE LDEI
IR,

6.5

6.5

RL

RL

R,

JR,

10.5

10.5

rl.

Irrz

12.0

JR,

6.5

6.5

CLR

CLR
JR,

6.5

DI

Ir].l rT 2

-

18.0

LDE LDEI
r2.

I rrl

6.5

6.5

10.5

10.5

10.5

CP

CP

CP

CP

CP

rio IT:?

R z• RJ

IR2, RI

RJ.IM

IRI,IM

6.5

6.5

10.5

10.5

10.5

10.5

RI.IM

IRIo.M

XOR XOR

XOR XOR XOR XOR

TI. r2

R 2• RI

12.0

ITt

IR 2• Rl

18.0

JR,

6.5

6.5

R,

JR,

TI. 1rr2 Ir
12,.0

J,

rl. x.

18.0

20.0

20.0

SRA SRA LDC LDCI CALL'
r~.

IrTI

l6:()

IRET
---.;:s

LD

Jrr2

Jr2.Jrrl

IRR\

CALL
DA

14.0

RET

10.5

RRC RRC LDC LDCI
R,

-

10.5

rl. rz

rl.

6.1

EI

Irl.lrrJ

INCW INCW CP

RCF

R~

10.5

-.;:s

LD

SCF

r~.

x. RI

6.5

6.5

10.5

RR

10.5

10.5

10.5

-.;:s

RR

LD

LD

LD

LD

LD

CCF

R,

JR,

rl. I T2

R 2• RI

IRz• RI

RhlM

IRI,IM

8.5

8.5

6.5

LD

LD

R,

JR,

Irl. rz

Rz.IR I

6.5

E

10.5

H •• IM

R2.RJ

6.5

D

10.5

1H z• HI

6.5

JP

B

10.5

rio Irz

INC

A

Rz, R\

6.5

R,

C

Irz

6.5

RR,

B

t

IR,

RR,

Co

~

rl

9

RLC ADC ADC ADC ADC ADC A.DC

10/12.1 12/14.1

7

6.5

8

7

6

R,

R,

Q)

e.

5

4

6.5
R,

4

6.5

R,

8.0

3

6.5

3

DEC DEC ADD ADD ADD ADD ADD ADD
RLC

2

2

SWAP SWAP

6.0

10.5

NOP

-=~----~~--~~----,----------~-----------~------------------------~~-----------Bytes per InstrUction
3
2
3
Lower Opcode
Nibble
Execution
Cycles
Upper Opcode
Nibble
------

First

216

Operand

!

Pipeline Cycles

4----- Mnemonic

Second Operand

Legend:
R=8-Bit Address
r=4-Bit Address
R 1 or rt = Dst Address
R2 or rz = Src Address
Sequence:
Opcode ,. First Operand, Second Operand
Note: The blank areas are not defined.

CMOS 8-Bit Single Chip Microcomuputer

(6)
Instruction

SM803/SM803A1SM805/SM805A

I

Instruction Summary

Instruction

I

and Operation

Addr Mode

I

dst src
and Operatim
(Note 1)
ADC dst,src
dst+-dst + src + C
(Note 1 )
ADD dst,src
dst+-dst + src
ANDdst,src
(Note 1 )
dst+-dst AND src
CALL dst
DA
SP+-SP-2
IRR
@SP+-PC;PC+-dst
CCF
C+-NOTC
CLR dst
R
IR
dst+- 0
COM dst
R
dst+-NOT dst
IR
CP dst,src
(Note 1 )
dst+-src
OA dst
R
dst+-DA dst
IR
DEC dst
R
dst+-dst-l
IR
OECW dst
RR
dst+-dst-l
IR
01

IMR(7)+-0
OJNZ r,dst
RA
r+-r-l
if r o PC+-PC+dst
Range: +127,-128
EI
IMR(7) +-l

00

****0*

NOP

50

-**0--

OR dst,src
dst+-dst OR src

06
04

------

POP dst
dst+-@SP
SP+-SP+ 1

EF

* - - - -

BO
Bl
60
61
AO

- - -

40
41
00
01
80
81
8F

r
X
r
Ir
R
R
R
IR
IR
r
Irr
Ir
Irr

-

-

- -

X
r
Ir
r
R
IR
1M
1M
R
Irr
r
Irr
Ir

r· Irr
Irr
r

83
93

------

FF

------

(Note 1 )

40

-**0--

R
IR

50
51

------

70

- - - - - -

R
IR

****- -

RCF
C+-O
RET
PC @SP;SP+-SP+ 2

***x- -

RLdst ~ R
C
7 0
IR

-**0--

-***--***--

-

-

-

-

-

- -

-

-

-

-

------

Opcode Byte Flags Affected
(Hex)
CZSVDH

Irr
Ir

PUSH src
SP+--SP - 1;@SP+-src

71

CF
AF

RR dst

o - -

-

- -

- - - - -

90
91

****--

10

****

Lii]:[iI]J
R
C
7 0
IR
L[i)C l[iriJ
.IRR
7 0

EO
El

****

I{6:[iJJJ
R
C
7 0
IR

CO
Cl

****

30

**** 1 *

OF

1 - - - - -

R
IR

00
01

***0--

1M

31

------

RLC dst

RRC dst

SBC dst,src
dst+-dst - src - C
SCF
C+--l

11

(Note 1 )

Lmd il~ ~

SRA dst

INCW dst
dst+-dst+ 1
IRET
FLAGS+-@SP;SP<-SP+l
PC+-@SP;SP+-SP+2;IMR(7)+--1
JP cc,dst
DA
if cc is true
PC+-dst
IRR
RA
JR cc,dst
if cc is true,
PC+--PC+ dst
Range: +127,-128
LO dst,src
r
1M
dst+-src
r
R
R
r

LOC dst,src
dst+-src
LOCI dst,src
dst+-src
r+--r + 1;rr+-rr + 1
LOE dst,src
dst+-src

LDEI dst,src
Ir
dst+-src
Irr
r+-r + 1; rr+-rr + 1

7F

------

rE
r=O-F
20
21
AO
Al
BF

-***--

SRP src
RP+--src

-***--

SUB dst,src
dst +--dst - src

(Note 1)

20

****1*

******

SWAPdst

FO
Fl

X**X- -

------

TCM dst,src
(NOT dst) ANO src

R
IR
(Note 1 )

60

-**0--

FF

R
IR
RR
IR

Addr Mode
dst src

****0*

9F

r

I

10

rA
r=O-F

HALF
INC dst
dst+-dst+ 1

Opcode Byte Flags Affected
(Hex)
CZ'SVDH

cD
c=O-F
30
cB
c=o-F
rC
r8
r9
r=O-F
C7
07
E3
F3
E4
E5
E6
E7
F5
C2
02
C3
03
82
92

:-::--

STOP

------

6F

FF

@l

------

TM dst,src
dst ANO src

(Note 1)

70

-**0--

XOR dst,src
dst+-dst XOR src

(Note 1 )

BO

-**0--

Note 1 These instructions have an identical set of addressing
modes, which are encoded for brevity. The first opcode nibble is
found in the instruction set table above. The second nibble is ex·
pressed symbolically by a 0 in this table, and its value is found
in the following table to the left of the applicable addressing mode
pair.
For example, to determine the opcode of an ADC instruction use
the addressing modes r (destination) and Ir (source). The result is
13

Addr Mode
------

dst

src

r
R
R
R
IR

r
Ir
R
IR
1M
1M

------

------

Lower
Opcode Nibble

I

-------------SHARP.--..-.------217

CMOS 8-Bit'Single Chip Microcomuputer

•

SM803/SM803A1SM80S/SM80SA

Register
R244 (TO)'
Counter/Timer 0 Register
(F4H: Read/Write)

R240 (SIO)
Serial I/O Register
(FOH : Read/Write)

I~I~I~I~I~I~I~I~I

I D71 D61 D51 D.I D31D21 Dd Do

I

[TO INITIAL VALUE
(WHEN WRITTEN)
(RANGE: 1-256 DECIMAL
01-00 HEX)
To CURRENT VALUE
(WHEN READ)

[SERIAL DATA (Do=LSB)

R245 (PREO)
Prescaler 0 Register
(F5H: Write Only)

R241 (TMR)
Timer Mode Register
(FlH : Read/Write)

ID7/ D61 D5/ D./ D3 / D21 D11 Do I
ID7/ D6/ D51 D.I D31 D21 D1 I Do I
TOUT MODES ~
I L O=NO
FUNCTION
I LCOUNT
MODE
I=LOAD To
O=To SINGLE-PASS
NOT USED=OO

L

To OUT=OI
TIOUT=IO
INTERNAL CLOCK OUT = 11

T IN MODES
EXTERNAL =00
CLOCK INPUT
, GATE INPUT = 01
TRIGGER INPUT = 10
(NON - RETRIGGERABLE)
TRIGGER INPUT = 11
(RETRIGGERABLE)

PRES CALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

O=DISABLE TI COUNT
I=ENABLE T, COUNT

R246 (P2M)
Port 2 Mode Register
(F6H: Write Only)
I D7/ D6 1D51 D.ID31 D2/ DII Do

Dol

R243 (PRE1)
Prescaler 1 Register
(F3H: Write Only) ,

p 20-p 27 I/O DEFINITION
DEFINES BIT AS OUTPUT
I DEFINES BIT AS INPuT

R247 (P3M)
Port 3 Mode Register
(F7H: Write Only)
ID71 D 61

I D71 D6/ D51 D.I 0 31 D21 Dd Dol
COUNT MODE

SINGLE-P,ASS
'I'O=T,
I=TI MODULO-N
CLOCK SOURCE
I=TI INTERNAL
O=TI EXTERNAL TIMING INPUT
(TIN) MODE
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
.01-00 HEX)

I

Lo

LTI INITIAL VALUE
(WHEN WRITTEN)
(RANGE 1-256 DECIMAL 01-00 HEX)
TI CURRENT VALUE
(WHEN READ)

218

I=To MODULO-N
RESERVED,

. O=NO FUNCTION
I=LOAD TI

R242(T1)
Counter Timer 1 Register
(F2H: Read/Write)
I D71 D61 D51 D, I D31 D21 D1 I

L

O=DISABLE To COUNT
I=ENABLE To COUNT

1LL

D51~.ID31 D21 D dDo I

.

L,O PORT 2 PULL-UPS OPEN DRAIN

'
1 PORT 2 PULL -UPS ACTIVE
,RESERVED
o P32=INPUT
P35=OUTPUT
I P32=Di\VO/RDYO P35=RDYO/DAVO
00 P33=INPUT
P3.=OUTPUT

Y6}P3a=INPUT
P3.=DM
11 P3a=DAVl/RDYI
P3.=RDYI/DAVI
o P3, =INPUT (TIN)
P36=OUTPUT(ToUT)
, I P3I =DAV2/RDY2
P36=RDY2/DAV2
o P30=INPUTP37 =OUTPUT
I P30=SERIAL IN
P37=SERIAL OUT
o PARITY OFF
I PARITY ON

CMOS 8-Bit Single Chip Microcomuputer

SM803/SM803A/SM80S/SM80SA

R252 (FLAGS)
Flag Register
(FeH: Read/Write)

R248 (P01M)
Port 0 and 1 Mode Register
(F8H: Write Only)

J

I D,I D61 Dsl D41 D31 D21 DII Do

-r

PO.-PO, MODE
OUTPUT = 00
INPUT=01
A 12 -A 1S =lX
EXTERNAL MEMORY
TIMING
NORMAL =0
EXTENDED = 1

I

I~I~I~I~I~I~I~I~I

Llll

&SER FLAG F1
USER FLAG F2

LPOO-P03
MODE
LOO=OUTPUT
01 = INPUT
1X=As-All
STACK SELECTION
0 = EXTERNAL
1 = INTERNAL
Plo-Ph MODE
00 = BYTE OUTPUT
01 = BYTE INPUT
10 = ADo-AD,
11 =HIGH·IMPEDANCE ADo-AD"
AS,DS, R/W,As-All,AwA!5
IF SELECTED

HALF CARRY FLAG
DECIMAL ADJUST FLAG

OVERFLOW FLAG
SIGN FLAG
ZERO FLAG
CARRY FLAG

. R249 (lPR)
Interrupt Priority Register
(F9H: Write Only)

R253 (RP)
Register Pointer
(FOH: Read/Write)

RESERVE~ I
INTERRUPT GROUP
PRIORITY
)
(
IRQ3,IRQ5 PRIORITY GROUP A
RESERVED =000
0=IRQ5>IRQ3L---+-+---O~C > A > B=001
1=IRQ3>IRQ5
IRQO, IRQ2 PRIORITY (GROUP B)
A > B > C =010
0=IRQ2>IRQO
A > C > B=Ol1
1 =IRQO>IRQ2
B > C > A = 100
IRQ1,IRQ4 PRIORITY (GROUP C)
C > B > A=101
O=IRQ1>IRQ4
B > A > C=110
1=IRQ4>IRQ1
RESERVED = 111

"~m' I[L~DON'T

CARE
DON'T CARE

r6

rs

R254 (SPH)
Stack Pointer
(FEH: Read/Write)
I D71 D61 Dsl D,I D31 D21 Dl I Do 1

IRQO=P32 INPUT
IRQ 1 = P 33 INPUT
IRQ2=P31 INPUT
IRQ 3 = P 30 INPUT, S ERIAL INPUT
IRQ4=To, SERIAL OUTPUT
IRQ5=TJ
RESERVED

[STACK POINTER UPPER
BYTE (SPS-SP1S)

R255 (SPL)
Stack Pointer
(FFH : Read/Write)

R251 (lMR)
Interrupt Mask Register
(FBH: Read/Write)

l[

DON'T CARE

REGISTER POINTER

R250 (IRQ)
Interrupt Request Register
(F AH : Read/Write)

1

DON'T CARE
r.

ID,I D6I DsID.I D3ID21 DdDol

ID,ID61Dsi

~,I D,j D21 Dd Dol

[1 ENABLES IRQO-IRQ5
(Do=IRQO)
RESERVED

[STACK POINTER LOWER
BYTE (SPo-SP,)

1 ENABLES INTERRUPTS
.....-..-------SHARP----.---~---

219

Is

CMOS a-Bit Single Chip Microcomputers (ROM less)

LU800V1 ILU800AV1 ILU805BV2

LU800VI/LU800AVI/LU805BV2
CMOS 8Bit Single Chip Microcomputers (ROM less)
•

Description

The LU800VlILU800AV1/LU805BV2 is a
ROMless version of the SM8031 A and SM8051 A
CMOS 8-bit single-chip microcomputers and offers
the outstanding feature of the 28 family architecture.
Because some I/O ports are used for addr.essl
data bus, this device accesses up to 128K bytes of
the external memory space. Using the external
memory in place of an on-chip ROM allows designing more powerful microcomputer system.

•

Pin Connections
LU800V1 ILU800AV1 ILU805BV2

Vee

XTAL2
XTALl

0

P3, 4
P3 0
RESET

R/W

•

Features

DS
AS

1. Complete microcomputer, 24 I/O lines, and up
to 64K bytes addressable external space each
for program and data memory.
2. 143 bytes register file
(255 bytes register file for the LU805BV2)
124 general-purpose registers
(236 registers for the LU805BV2)
3 I/O port registers
16 status and control registers
3. Register pointer so that short, fast instructions
can access anyone of the 9 working-register
groups.
(16 groups for the LU805BV2)
LU800V1 M/LU800AVM/LU805BVM

P0 3

PO.
P0 5

LU800V1U/LU800AVU/LU805BVU

RESET 7

R!W

8

-.------.--..--SHARP-------....-..-220

LU800V1/LU800AV1/LU805BV2

CMOS 8-Bit Single Chip Microcomputers (ROM less)
4. FuJI-duplex UART and two programmable
8-bit counter/timers, each with a 6.-bit programmable prescaler.
5. Vectored priority interrupts for 110, counter I
timers, and UART.
6.. On -chip oscillation circuit
7. External clock
8MHz MAX. (internal 4MHz): LU800VI/M
12MHz MAX. (internal 6.MHz): LU800AVI/M
16.MHz MAX. (internal 8MHz): LU805BV2IM
8. Single + 5V power supply
9. 40-pin DIP (DIP40-P-6.00)
LU800VI/LU800AVlILU805BV2
44-pin QFP (QFP44-P-1414)
LU800VIM/LU800A VM/LU805BVM

•

44-pin QFJ (QFP44- P-S6.50)
LU800Vl UlLU800AVUlLU805BVM

•

Ordering Information
Model No.
LU800Vi
LU800ViM
LU800ViU
LU800AVi
LU800AVM
LU800AVU
LU805BV2
LU805BVM
LU805BVU

Clock
8MHz

i2MHz

i6MHz

Package
40DIP
44QFP
44QFJ
40DIP
44QFP
44QFJ
40DIP
44QFP
44QFJ

Block Diagram

Vee

GND

)------{ll)-------{

Machine Timing
&

Instruction Control
ALU
UART
Flags
Counter Timer

Register Pointer

Interrupt Control

Note: Pin numbers apply to 40-pin DIP.

•

Pin Description
Pin
PO O-P0 7
Pi l -P1 7
P2 o-P2 7
P3 0 -P3 7
AS
DS
R/W
RESET
XTALl
XTAL2

Meaning
Port 0
Address/ data bus
Port 2
Port 3
Address Strobe
Data Strobe
Read/Write
Reset
Clock 1
Clock 2

I/O
I/O
I/O
I/O
I/O
0
0
0
I
I
0

Function
8-bit I/O port, programmable for I/O.
Multipiexed Address/data bus
Programmable for I/O in bits.
P3 0 -P3 3 for input, P3 4 -P3 7 for output.
Active "Low", activated for external address memory transfer.
Active "Low", activated for external data memory transfer.
Read at "High", Write at "Low".
Active "Low", Initializes.
Clock terminal pin.
Clock terminal pin.

Pin functions of the LU800VlILU800AVI/LU805BV2 are identical to those of the SM8031 A, SM8051 A,except for pins Pl o-PI 7 •

------..-~-.---SHARP--- ........... ---.----~-

221

CMOS8-Bit Single Chip Microcomputers (ROM less)

•

Address space

(1) Program Memory
The ROM less device, having a I6-bit. program
counter, addresses 64K -bytes of external program
memory. All the command codes are fetched from
these external program memories.
For the ROMless device, the first 12 bytes of
program memory are reserved for the interrupt
vectors. These locations contain six 16-bit vectors
that correspond to the six available interrupts.
Program execution begins at location OOOC H after a
resed.
(2) Data Memory*
The ROMless device can address 64K bytes of
external data memory. External data memory may
be included with or separated from the external
program memory space. DM, an optional 110 function that can be programmed to appear on pin P3 1 ,
is· used to distinguish between data and program
memory space.

indirectly with an 8-bit address field. This also
allows short 4-bit register addressing using the
Register Pointer (one of the control registers). In
the 4-bit mode. the. regiter file is divided into nine
working register groups, each occupying 16 contiguous locations. The Register Pointer addresses
the starting location of the active working-register
group.

(4) Stacks
Either the internal register file or· the external
data memory can be used for the stack. A 16-bit
Stack Pointer (R254 and R255) is used for the external stack, which can reside anywhere in data
memory. An 8-bit Stack Pointer (R255) is used for
the internal stack that resides within the 12412 3 6
for the LU805BV2 general-purpose registers
(R4-RI27/R4-R239).
LOCATION .---_ _ _ _ _ _ _ _ _ _-, IDENTIFIERS

(3) Register File
The 143-byte register file inculdes three 110
port registers (RO, R2, R3), 124 general-purpose
registers (R4-RI27) and 16 control and status registers (R240-R255).
These registers are assigned the address locations shown in Fig 2.
The instructions can access registers directly or

Program start
addres after rese t~ s;:---------- 12
11

Interrupt vector
(Lower byte)
Interrupt vector
(Upper byte)

Fig. 1

222

LU800V1 ILU800AV1 ILU805BV2

10
9
8
7
6
5~

4 -""_
3
2
1
0

IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQO
IRQO

Program memory map

External
memory

255

STACK POINTER (BITS 7-0)

SPL

254

STACK POINTER (BITS 15-8)

SPH

253

REGISTER POINTER

252

PROGRAM CONTROL FLAGS

-------

~..

RP
FLAGS

251

INTERRUPT MASK REGISTER

IMR

250

INTERRUPT REQUEST REGISTER

IRQ

249

INTERRUPT PRIORITY REGISTER

IPR

248

PORTS 0-1 MODE

P01M

247

PORT 3 MODE

P3M

246

PORT 2 MODE

P2M

245

TO PRESCALER

PREO

244

TIMER/COUNTER 0

243

T 1 PRESCALER

242

TIMER/COUNTER 1

241

TIMER MODE

240

SERIAL I/O

239

NOT
IMPLEMENTED

~~~~~~~~~~~

TO
PRE1
T1
TMR
SIO

127
GENERAL-PURPOSE
REGISTER
4
3

PORT 3

P3

2

P2

1

PORT 2
NOTIMPLEMENTED

0

PORTO

PO

Fig. 2

PI

The register file

LU800V1 /LU800AV1 /LU805BV2

CMOS e-Bit Single Chip Microcomputers (ROM less)

•

Port Functions

•

Registers

The LU800Vl/LU800AVlILU805BV2 control
registers are the same as on the SM803/ A,
SM805/ A, except two bits D3 and D4 in the port 0,
1 mode register (R248).

The LU800VlILU800AVlILU805BV2 has a
dedicated memory interface port (Port' I) and input/output ports (Port 0, 2, 3). These ports are
given eight lines each. The functions of port 0, 2
and 3 are the same as those of the SM803/ A,
SM805/A.
Port 1 is a dedicated Z-bus compatible memory
interface. The operation~f Port 1 are supported
by the Address Strobe (AS) and---'pata Strobe (DS)
lines, and by the Read/Write (R/W) and Data Memory (DM) control lines.
The low-order program and data memory
address (Ao-A7) are output through Port 1 and are
multiplexed with data in/out (D o-D 7). Instruction
fetch and data memory read/write operations are
done through this port.
Port 1 cannot be used as a register nor can a
handshake mode be used with this port.
H more than address lines are required with the
ROMless device, additional lines can be obtained
by programming Port 0 bits as address bits. The
least significant four bits of Port 0 can be configured to supply address bits As-Au for 4K byte
addressing or both nibbles of Port 0 can be configured to supply address bits As- A 15 for 64K byte
addressing.

•

Serial Input/Output

The LU800VlILU800AVlILU805BV2 serial
input/ output function's are the same as those of the
SM803/ A, SM805/ A, (Refer back to the SM803/
A, SM805/ A description.)

•

Counter/Timers

The LU800Vl/LU800AVlILU805BV2 counter/timer functions are the same as those of the
SM803/ A, SM805/ A, (Refer back to the SM803/
A, SM805/ A description.)

•

Interrupts

The LU800Vl/LU800A Vl/LU805BV2 interrupt functions are the same as those of the
SM803/ A, SM805/ A, (Refer back to the SM803/
A, SM805/ A description.)

•

Instructions and AC/OC Characteristics

These data of the LU800VlILU800AVlI
LU805BV2 are the same as for the SM803/ A,
SM805/ A. (Refer back to the SM803/ A, SM805/ A
description.)

R248 (P01 M) Port 0, 1 Mode Register (F8 H Write only)

D7
PO, - PO,

D6

D5

MODE~

OUTPUT=OO~
INPUT=Ol
A12 - A15=lX

EXTERNAL MEMORY TIMING
NORMAL=O--------~

*EXTERNAL=l

D,

D:l

D2

DJ

Do

I

POo - P03 MODE
LOO=OUTPUT
Ol=INPUT
1 X=A5 - All
STACK SELECTION

L--------O = EXTERNAL
1= INTERNAL
L-------RESERVED (MUST BE 0)

.-.-----"'--SHARP.--------------~

223

CMOS8-Bit Single Chip Microcomputers (ROM less)

•

Reset

•

+5V
1 Vee

>

r

LU800Vl

lkO

6

"-

RESET

~= lJlF

I

Fig. 3

After reset, ports 0 and 2 are used as input
ports, the program counter is reset at OOOHand the
interputs are disabled.
When the reset input inactivated, the program
memory starts execution at OOOCH.

Portl

Initialization

When the program, after reset, starts execution
at OOOCH, the device must be initialized. Ports 0
-and 2 after reset are used as inputs, and an ex·
panded memory timing and an internal stack are
selected with the DM signal not to be output. The
valid address lines include 8 lines of port 1 only.
Usable memory sholud be limited to the first 256
bytes and the port 0 must be programmed as
address lines within 256 bytes of memory for use
of more than 257 bytes of memory.
Port 0, PO O·P0 7 , is used as input port after reset,
if is used as address lines, a constant address
value must be held with an external circuit until it
is initialized.
The port initialization sequence is:
(1) Write upper byte of address of an initializa·
tion routine to port 0 register.
(2) Configure port 0 and 1 mode register P01M.
(D 1 = 1; lower 4 bits of pOrt 0 should be AsAu address lines, D7= 1 every bit of port 0
should be As ·A 15 address lines.)

When the NU800V1 is reset, the device must be
kept Low for at least 50msec from the device is
stabled with the reset switch is turned on, or for
18 clock cycles from the power supply and clock
oscillator are stabled.
The intervals reset the LU800Vl is obtained by
connecting external capacitor of 1,uF and resistor
of lOOk n as shown in Fig. 3.

»
<'-

>
<;

Fig. 4

224

<;

<

Vee

t

Memory interface with pull-up resistors

(4Kbyte)

LU800V1 ILU800AV1 ILU805BV2

CMOS 8-Bit Single Chip Microcomputers (ROM less)

After reset, in this case, the "b" inputs are
selected and address bits A8-Au go Low because
the SELECT input to the LS157 is kept High until
the R/W goes Low. If the R/W goes Low, the
SELECT goes Low and PO O-P0 3 will be valid.
Initialization of port 0
(1) Write OOH (upper byte address of initialization routine) to port 0 register.
(2) Set the proper bits in the port 0 and 1 mode
registers.
(3) Write into the external memory upon execution of an LOC or LOE intruction. (This
allows the R/W to go Low and the LS 15 7 to
switch to the "a" inputs.

Initialization of port 0
(1) Jump to the address FXX H in order to match
the program counter to the address being
accessed.
(2) Write OF H (upper byte of the address)into
port 0 register at FXX H.
(3) Set the proper bits in the port 0 and 1 mode
register to output the port O.
(4) Set the proper bits in the port 0 and 1 mode
register to use the port 0 as address lines.
Initialization with The LS157
Fig. 5 shows the memory interface between upper 4 bits (PO O-P0 3) of port 0 and a 4K byte memory with the LS157 and a flip-flop.

pocn<

)

ADo-AD,
AS, DS, R/W

LU800Vl

POo

As

1a
------;;. 1b

POI
PortO
PO,

---->-----<00

PO,

(4Kbyte)
A9

2a
2b

Program
memory

LS157
AlO

3a
3b

An

4a
4b

SELECT
,,,. STroBE

R/W

R

Q

LS74A

S

Fig. 5

Memory interface with the LS157

225

8-Bit Microcomputer (VCR System Controller)

SM8202/SM8203

SM8202/SM8203
•

8-Bit Microcomputer
(VCR System Controller)

Description

The SM8202/SM8203 is an 8-bit microcomputer which integrates an 8-bit CPU core, a ROM, a
RAM, serial I/O ports,a timer, an AID converter
and a digital servo controller in a single chip_
An on-chip CPU core is organized as a new
architecture with a full lineup of instruction sets,
which allows the software to be easily developed_
An on-chip servo controller contains the hardware for controlling the speed and the phase of
capstan and drum motors as well as for special
playback with a software controL This microcomputer is applicable to a variety of VCR systems
for an NTSC, a PAL, a movie, a 4-head mechanism,
etc_

•

The SM8203 omits the CTL duty discriminating
output circuit. (VISS) and adds the following two
functions from the SM8202_
. An internal 4-head switching circuit for special
playback of slow and search modes decreases external parts count
• Switching the CTL signal with the timer input
simplifies programming of a real time count

•

Features
L
2_
3_
4_

CMOS process
ROM capacity: 10,240 X 8 bits
RAM capacity: 256 X 8 bits
SM82 core

Pin Connections
SM8202

o

SM8203

o

---:-------SHARP-..--,-----~-----

226

8-Bit Microcomputer (VCR System Controller)

• Instruction set: 64
(including for multiple and division function,
. a bit manipulation)
· Addressing mode: 22
• General-purpose register: 8-bit X 8
16-bit X 4
5. An on-chip servo controller
• Applicable to NTSC, PAL systems
• PWM: 10 bits/4 channels
6. Applicable to a 4-head VCR
7. Instruction cycle: 0.8 f1 s (MIN.)
8_ Interrupt
• External interrupts: 2
• Internal interr~pts: 8

•

SM8202/SM8203

9. Inputloutput ports
· I/O ports: 24
· Input ports: 8 (for switching with AID converter)
· Output ports: 16 (for switching with a servo
controller)
Serial I/O
11. Timer: 8 bits X 3
12. AID covnerter: 8 bits/8 channels
13_ Built-in watchdog. timer
14. Built-in crystal oscillation circuit
15. Supply voltage: 5V ± 10%
16_ 64-pin SDIP (SDIP64:-P-750)

10:

Block Diagram
SM8202

VDD GND
TEST
RESET

...-.-........: -......... ----SHARP---~ ..........· · - - - - - - 227

8-Bit Microcomputer (VCR System Controller)

SM8202/SM8203

SM8203

VDD

TEST
RESET

--------.---~-SHARP ~.-.....-------~--.-......

228

8-Bit Microcomputer (VCR System Controller)

•

SM8202/SM8203

Pin Description
Signal
PO O-P0 7
Pl o-P1 7
P2 o-P2 7
P30/INTo. P3 1 IINT 1
P3 2 /TO
P3 3 /S1
P3 4 /SCLK
P3 5 /S0

P3 6 /VISS
P3 6 /A-HSW
P3 7/A-HSW
P3 7/ENV
P4 o/ ADo-P47/ AD7
P5 0 /PWM o
P5 1 /PWM 1
P5 2 /PWM 2
P5 3 /PWM 3
P5 •• P5 5
P5 6 • P57
P5 6 /HAMP
P5 7/CHRO
PG-ADJ
D-PG
D-FG
VSYNC
FV
HSW
C-FG
PB-CTL
REC-CTLEB
REC-CTL8

JlO
0
JlO
JlO
lIO / I
JlO / 0
lIO / I
JlO
lIO / 0
lIO / 0
lIO / 0
lIO / 0
JlO / I
I
0
0
0
0
0
0
0
0
I
I
I
I
0
lIO
I
I
0
0

Xl. X 2

RESET
TEST
VDD• GND

I
I

Function
Output ports (medium voltage)
JlO ports (resettable JlO on each bit)
JlO ports (resettable JlO on each bit)
lIO ports/External interrupt input port
lIO port/Timer output port
lIO portt/Serial input port
lIO port/Serial clock
JlO port/Serial output port
lIO port/CTL duty output port for VISS
JlO port/Audio HSW
lIO port/Audio HSW
lIO port/ENV comparator input port
Input PQrt/ Analog input port
Output port/PWM output port (negative)
Output port/PWM output port (negative)
Output port/PWM output port (negative)
Output port/PWM output port (negative)
Output ports
Output ports
Output port/Head amp. control signal output port
Output port/Chroma rotation signal output port
HSW adjustment
Drum PG input port
Drum FG input port
Vertical synchronous signal (negative)
False synchronous signal output port
Head switching pulse
Capstan FG input
PB-CTL input port
REC-CTL output port
REC-CTL inverting output port
System clock oscillator
Reset in put port
Test input port
Power supply. Ground

SM8202
SM8203
SM8202
SM8203

SM8202
SM8203

.......... .-.-.------SHARP'~-----.-229

8~ait Microcomputer

•

SM82q2lSM8~03

(VCR System Controller)

. Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Operating temperature
Storage temperature

Symbol
Condition
VDD
VIN
VOUT
VOUTO Applied to port 0
10

Topr
Tstg

Unit
V
V,
V
V
mA
t
·C

Rating
-0.3 to +7.0
-0.3 to V DD +0.3
-0.3 to V DD +0.3
-0.3 to +12
20
-20 to +70
-55 to +150

Note

1

Note 1: The sum of source current or sink current from output ports.

Oscillation circuit
•

Operating Conditions
Unit

Condition
VDD =5V±10%

Parameter
Oscillation frequency

MHz
R

•

(Voo =5V±10%, Ta=~20 to +70t)

DC Characteristics
Parameter

Input voltage

Input current

Symbol
VlHl
VILl
VlH2
VIL2
IlHl
IILl
VOH1
VOLl
VOH2

Output current
VOL2
VOL3
VOL4
Current consumption
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:

230

Condition

VIN=VOO
VIN=O
IOH=-1.5mA
IOH=-6mA
IOL=1.5mA
IOL=6mA
IOH=-4mA
IOH=-16mA
IOL=4mA
IOL=16mA
IOL=2mA
IOL=8mA
IOL=2mA
IOL=8mA

MIN.
0.8Voo
0
0. 75Voo
0

TYP.

MAX.
Voo
0.2VDO
VDO
0. 15VoD
10
10

Voo-0.5
Voo -2.0.
0.5
2.0
VDD -0.5
Voo -2.0
0.5
2.0
VoD -0.6
VDo -2.0

lop

Applied to all pins except for D-PG. D-FG. C-FG. PB~CTL
Applied to pins D-FG. D-PG. C-FG. PB~CTL
Applied to all input pins.
Applied to all output pins except for REC-CTLEe. REC-CTL8. PG-ADJ. POo
Applied to REC-CTLEe
Applied to pins REC~CTL8. PG-ADJ
Applied to pins 'PO O-P0 7
No load condition

0.5
2.0
10

Unit
V
V
V
V
pA
pA
V
V
V
V
V
V
V
V
V
V
V
V
mA

Note
1
2
3

4

5

6
7
8

8-Bit Microcomputer (VCR System Controller)

SM8202/SM8203

AC Characteristics

•

(V oo =5V±10%, Ta=-20 to +70"C)

• SIO Characteristics
Symbol
Parameter
SIO clock cycle
tsCYC
SIO transmission data delay
tsoo
SIO receiving data setup
t SIS
time
SIO receiving data hold time
tSIH
SIO input clock pulse width tSCKW
SIO input clock pulse width tSCKR
SIO input clock fall time
tSCKF

MIN.
16

Condition

TYP.

MAX.
300

Unit
tcyC
ns

300

ns

1
0.4

Note
1

0.6
200
200

tcyC
tSCYC
ns
ns

1

Note 1: tCYc: 2 X (oscillation frequency)-l

Shift clock

Transmission data

Receiving data
tSYNC
tSCKW

tSCKW

tSCKR

•

AID Converter Accuracy
Parameter
Non linearity error
Differential non -linearity
Zero-scale error
Full-scale error
Total tolerance

MIN.

tSCKF

Clock timing

(Voo=5V, Ta=25"C)
TYP.

MAX.
6
6
6
6
6

Unit
LSB
LSB
LSB
LSB
LSB

231

SM8202/SM8203

8-Bit Microcomputer (VCR System Controller)

•

Pin Function

The device is provided with 58 I/O ports which
include 8 X 6 ports and 10 ports only for servo
controller.
Figures 1 and 2 show the pin function diagram.
The function on each ports can be set with a software.
• I/O ports
• External interrupt input ports
• Serial I/O ports
• Timer output ports
• A/D converter input ports
• PWM output ports
• A - HSW output ports
• VISS output ports (for the SM8202 only)
• HAMP output port (for the SM8203 only)
· CHROMA output port (for the SM8203 only)

be switched between input and output modes with
a directional register.
Port PO is a medium voltage output port, and
serves exclusively as an 8-bit output port.

(1) Ports PO, P1, P2
Ports PO, PI, P2 are 8-bit I/O ports which can

(3) Port P4
Port P4 is an only input port. This port can be

\

(2) Port P3
Port P3 is an 8-bit I/O port the same as ports
PI and P2. Port P3 is allocated P3 0 -P3 1 for interrupt input ports, P3 for a timer output port, .
P3 3 -P3 s for serial I/O ports. For the SM8202, the
P3 6 is allocated for a VISS output port and P3 7 for
an A-HSW output port. For the SM8203, the P3 6
is allocated for the A-HSW output, and the P3 7 is
allocated for the ENV comparator input port for
P5 6 /HAMP, P5 7 /CHRO outputs, when used as the
input port.

Voo

P5 0/PWMo
P5dPWM]
P5'/PWM,
P5,/PWM 3
P5.
P55
P56
P5,
C-FG
D-FG
D-PG
VSYNC
PB-CTL
PG-ADJ
REC-CTLffi
REC-CTL8
FV
HSW

P4o/ADo
P4]/AD]
P4,/AD,
P4,!AD,
P4./AD.
P45/AD5
P46/AD6
P4,/AD,

POo
PO]
PO,
PO,
PO.
p0 5
P06
PO,

P50/PWMo
P5I!PWMI
P5,fPWM2
P5,/PWM,
P5.
P55
P56/HAMP
P5'/CHRO

POo
PO]
PO,
PO,
PO.
P05
P06
PO,

C-FG
D-FG
D-PG
VSYNC
PB-CTL
PG-ADJ
REC-CTLffi
REC-CTL8
FV
HSW

P2 0
P2]
P22
P2 3
P2.
P25
P26
P2,

Fig. 1 SM8202 pin functions

Von

Fig. 2

SM8203 pin f4nctions

. - . - . . . - - - - -........... ----SHARP-.--------~
232

SM8202/SM8203

8-Bit Microcomputer (VCR System Controller)

set to an analog data input port of AID converter
with a program control.
(4) Port P5
Port P5 is only output port. Each bit of P5 0 -P5 3
may be set to PWM output mode.
For the SM8203, the P5 6 /HAMP may be set to
the HAMP switching signal output port, and the
P5 7 /CHROMA to the CHROMA switching signal
output port.
(5) C-FG, D-FG, DPG
The C-FG pin is used to input the signals from
the FG (frequency generator) of a capstan motor,
and control the speed and the phase, compared to
the reference signals.
The D-FG pin is used to input the signals from
FG of a drum motor, and control the speed, compared to the reference signals.
The D-PG pin is used to input the signals from
the PG (pulse generator) of a drum motor, and control the drum phase, compared to the reference signals.

(6) PB-CTL, REC-CTLEB, REC-CTL8
The PB-CTL pin is used to input the signals for
the speed control of a capstan motor when playback.
The REC-CTL+ and REC-CTL- control pins
are used to record the control signals when recording.
(7) HSW, PG-ADJ
The HSW pin outputs the head switching signals
or inputs the head switching pulses.
The PG- ADJ input pin is used to contorl the
phase of a head positionning with an external capacitor and a: variable resistor.
(8) V SYNC , FV

The VSYNC pin inputs the vertical synchronous
signals, and the FV pin outputs the synchronous
signals when a trick motion.

233

8-Bit Microcomputer (VCR System Controller)
SM8202/SM8203
..-,...-,...-,...-,..-,...-,...-,..-,...-,..-,..-,..-,...-,---..-,•

Hardware Configuration

(1) Address space
The device contains an internal RAM an 110
register and a status register which are ~o-called
register file. The registers are located in the
64K-byte address at the same memory space with
the program memory. Fig. 3 shows the address
space.
(2) Program memory (ROM)
The program memory space is allocated in the
addresses from 1000 to FFFF within a program/
register memory. The first 10K bytes of the program memory is a mask ROM within a chip. 16 interrupt vectors should be inserted into the addresses from 1000 to 101F. After the device is reset,
user's program starts execution at the address
1020 (see Fig. 4).
(3) Register file
The addresses from 0000 to OOFF are allocated
for a register file, and 0100 to OFFF for an internal RAM expansion.
The register file consists of a 16 bit general-purpose register, a 7 bit 110 register, a 256 byte
internal RAM and some control registers (see Fig.
5). The file may be accessed from an 8 bit address
field.

64Kbyte

FFFF

(4) Register configuration
General-purpose registers Ro-R 7 can be used as
an 8 bit register as well as a 16 bit register with a
couple of registers. Registers Rs -R 15 can be used
as a 16 bit register with a couple of registers.
(5) Interrupt
The device has 10 different interrupt functions
(see Table 1), and the priority order should be 7-+
6-+ ... 2-+ 1 shown in table 1. For the interrupt inhibit,. the device accepts the interrupt with higher
priority than that specified by an interrupt mask
1M of a processor status 0 (PSO).
Reseting the bit "I" of the processor status 1
(PSI) through DI instruction inhibits all of maskable interrupts (see Fig. 6).
. (6) Reset function
Applying a High level signal to the RESET pin
resets the internal logic of the device and starts execution of the program at address 1020.
After reset, the following blocks are initialized.
• The output port is set to "0", and 110 ports may
be placed in input mode.
• The interrupt enable flag is reset.
• The peripheral 110 registers are initialized.

3800

14K byte
On-chip ROM

1020

lOlE

Not used

101C
lOlA

380 0

14K
On-chip ROM

1000

4K
Not used

0100
Register file
0000

Fig. 3

234

0

Address architecture

1018
1016
1014
1012
1010
100E
100C
100A

1008
1006
1004
1002
1001 ~r2.c!ss~~!!.n!Sl2.w!.r_bg)
1000 Process routine (higher bit

Fig. 4

4K byte

Program memory map

SM8202/SM8203

8-Bit Microcomputer (VCR System Controller)

007F

OOFF
Control register

0020
OOIF
OOIE
OOlD
OOIC
OOIB
OOIA
0019
0018
0017
0016
0015

SP
Not used
Not used
Not used
SYS
Not used
SIO
Not used
P5

0011
0010
OOOF

PI
PO
Rl5

Port PI
Port PO
General purpose
register R15

0001
0000

Rl
RO

General purpose register Rl
General purpose register RO

PSI

pso

Processor status 0
Processor status 1
Stack pointer
On-chip RAM
System configration
Serial port
Port P5

Fig. 5

0000

The register file

Table 1 Interrupt
Vector location

Source

1000

External interrupt INTO

1002
1006
1008
100A
100C
100E
1012
1014
101E

External interrupt INTI
Watchdog timer
Timer TO
Timer T1
Timer T2
SIO
AID converter
Servo controller
Irregal instruction

Priority
7
(Most priority)
4
6
3
3
1
2
5
-

External interrupt INTO - - - - - - 1
Timer TO
Servo controller - - - - - - 1
External interrupt INTI - - - - - - 1
Timer n, T2
AID converter
SIO
Watchdog timer

Fig. 6

Interrupt mask

235

. 8-Bit Microcomputer (VCR System Controller)

(7) AID converter
The control register ADC allows 8 bit input
ports P4 o-P4 7 to be selected from,the input ports,
the AID converters or the comparators.
• Input ports
The port status with a digital data may be read
out from the input ports.
• AID converter
The analog data of anyone of channels P4 o-P4 7
specified by the ADC is converted· into the digital
data through the AID converter, the result of AID
conversion may be read out as a data register of
port P4. The AID converter may be started with a
bit manipulation of ADC. Then the CPU acknowledges the interrupt if it is enabled. The AID conversion is executed by the comparison between the
analog input and the voltage based upon the ladder
resistor applied between Vee and GND. The conversion time should be 68,u sunder 4MHz of the
clock frequency.
• Comparator mode
Selecting the comparator mode writes data into
the internal register instead of the data register of
port P4. The DI A conversion of the contents of an
internal register is executed to compare with an
analog data. The corresponding 1 bit of the ADC is
set or reset specify the result of comparison.

(8) Serial I/O (SIO)
The serial I/O port transfers and receives an
8-bit data in synchronization with the shift clock.
The serial I/O consists of a couple of registers, an
octal counter and some controllers.

SM8202/SM8203

Timer
The device contains 4 timers including three
8-bit interval timers and a watchdog timer which
may be selected by an 8-bit select register (TS) ..
A 14-bit prescaler commonly used for each timer has the output which becomes the input clock at
each timer. The input timer is a clock (1) 11)
equivalent to the reference clock divided into 2 .
The corresponding input clock at each tiqIer may
be set with a program.
Note that the timer 0 of the SM8203 can also be
used as a counter which counts the input clock of
the CTL signal.
(9)

(10) Sound output (P3 2/TO)
The P3 2 /TO may be switched to either an I/O
port or a prescaler output port through the select
register (TS). A 4kHz clock for the sound output
is output from the P3 2 /T o.
(11) Timing
The internal clock of the device is a half frequency of the reference clock. The read cycle of the
internal ROM is generated with 2 clocks, and that
of the internal RAM or I/O register with 1 clock.
A high speed operation is obtained from the
function that the operation code fetch overlaps the
execution cycle and the next instruction operation
code is taken during execution of one instruction
cycle.

----.. ........... - . . . . . - . - . . - . . - , - - $ H A R P

236

~---.----~

SM8202/SM8203

8-Bit Microcomputer (VCR System Controller)

•

Servo Control Function

The device is provided with the hard block for
exclusive use of servo control, which offers flexible
servo control with a software. The hard block reo
quires less software and performs servo control by
simple load instructions and arithmetic instructions. Figures 7 and 8 show the block diagram of a
servo controller.
(1) Drum servo speed comparator (D-AFC)
The drum speed signal (D-FG) is compared to
the reference clock to calculate the tolerance.
(2) Drum phase comparator (D-APC)
The drum phase comparator signal (D-PG) is
compared to the VSYNC or reference clock to calculate the tolerance.

the reference clock to calculate the tolerance.
(4) Capstan phase comparator (C-APC)
The capstan phase comparator signal (HSW) is
compared to the divided signal C-PG of either the
CTL or C-FG signal to calculate the tolerance.
(5) Head switching circuit (HSW)
The head switching circuit. generates the head
switching pulse (HSP) necessiiry for switching a
drum head, based upon FG and PG signals of a
drum. The mono multicircuit of a register allows a
digital tracking control of a delay from the signal
to the head with the head switching pulse to be delayed:

(3) Capstan speed comparator (C-AFC)
The capstan speed signal (C-FG) is compared to

48

a

D

D-FG

52

r--"

54

f-

HSW

~

Clock

.~

+
D-AFC

C-APC
"

J
I

U

1
~

t

r-C-FG

5~

C-AFC

PB- CTL 4~

J
VISS

J

~

Internal data bus

+
1-+

~

,5?

D-APC

PG -ADJ

J

,4~

50

FV

;r;

I

9

t

._-

jPWMIIPWMIIPWMl1 pWMI

I

~

@---@-0--0:i

:i

:i

Jl"

Jl"
';:;

Jl"

~

'Jl":8
Fig. 7

~

~

i

~

Jl"

II:>

.....

';;;

Jl"

Jl"

Jl"

II:>

II:>

SM8202 servo control, block

237

8-Bit Microcomputer (VCR System Controller)

HSW

SM8202/SM8203

D-APC

;;

C-APC

PG-ADJ
Clock

~
Internal data bus

C-FG

541~------------------~--~

PB-CTL

48r-------~~---------+--~

Fig. 8

SM8203 servo control block

(6) False synchronous circuit block (FV)
The false synchronous circuit block sets and outputs the intervals of programmable 3 levels of
High, Low and High impedance, referenced to the
rising edge and falling edge of a head switching
pulse.
(7) Pulse width mudulation output block
(PWM)
4. sets of the pUlse width modulation (PWM) output circuits constitute a digital filter through an internal arithmetic operation, which may be allocated
2 sets for a drum and a capstan, or 4 sets. for
D-AFC, D-APC, C-AFC and C-APC.
The PWM signal performs a modulation by 1 bit
rate of a 10 bit differential data divided by upper
7 bits and lower 3 bits. And 1 pulse is incremented
to the PWM signal of upper 7 bits according to the
lower 3-bit data. An 8 pulse is defined as one cycle. This function allows high resolution and high
speed PWM features under the conditions of a

238

C-AFC

10-bit quantization and a 28kHz frequency (fsc=
3.579545MHz).

(8) VISS circuit
The VISS circuit discriminates the CTL signal
duty between "1" and "0", and counts the cascading
data of ''1"' to be stored into the latch circuit. The
contents of the latch circuit may be transferred to
the CPU through the data bus line, which allows a
simple detection of the VISS signal.
The SM8202 outputs the discrimination results
of the CTL signal duty from the P3 6 /VISS pin.

8-Bit Microcomputer (VCR System Controller)

(9) HAMP/CHROcircuit (only for the SM8203)
The head amp./chroma-rotation circuit (HAMP/
CHRO) outputs the switching signal for a head
amp. and chroma-rotation when a special playback.
Provided with these features, this microcompu:
ter is applicable to 2-head and HiFi 4-head camcoders, a variety of servo controllers of NTSC,
PAL and VHS-C.
Typical features are mentioned below:
• Applicable to a variety of video head system of a
2-head, and a-double azimuth 4 head, recording
systems of an NTSC and a PAL, and high resolution system of VHS-C.
• A variety of trick motion with a software con-

SM8202/SM8203

trol.
• Built-in a tracking circuit and a REC CTL signal
delay circuit.
• CTL signal duty discriminating circuit and VISS
counter circuit.
• Variable. CTL output signal (REC CTL) duty
'ratio when recording.
• High resolution and 4 high frequency RWM outputs.
• 1 PG system HSP signal generator circuit, and
external HSP input capability.
• False synchronous signal generator circuit.
• Automatic mode discrimination with a software
control.

239

SM8202/SM8203

8-BitMicrocomputer (VCR System Controller)

•

(1 )

Instruction set
Load instructions

Instruction
CLR
MOV
MOVM
MOVW
POP
POPW
PUSH
PUSHW

Operand
dst
dst, src
dst, 1M, src
dst, src
dst
dst
src
src

(4)
Function
Clear
Move
Move Under Mask
Move Word
Pop
Pop Word
Push
Push Word

(2) Arithmetic instructions
Operand
src
src
src
src
src
src

Instruction
ADC
ADCW
ADD
ADDW
CMP
CMPW
DA
DEC
DECW
DIV
INC
!NCW
MULT
NEG
SBC

dst,
dst,
dst,
dst,
dst,
dst,
dst
dst
dst
dst,
dst
dst
dst,
dst
dst,

SBCW

dst, src

SUB
SUBW

dst, src
dst, src

src

src
src

Function
Add With Carry
Add Word With Carry
Add
Add Word
Compare
Compare Word
Decimal Adjust
Decrement
Decrement Word
Divide
Increment
Increment Word
Multiply
Negate
Subtract With Carry
Subtract Word With
Carry
Subtract
Subttact Word

(3) Logic instructions
Instruction
AND
COM
OR
XOR

Operand
dst, src
dst
dst, src
dst, src

Function
Logical And
Complement
Logical Or
Logical Exclusive Or

Program control instructions

Instruction
BBC
BBS
BR
CALL
CALS

Operand
src, dst
src, dst
cc, dst
dst
dst

DBNZ

r, dst

IRET
JMP
RET

cc, dst

(5)

Bit manipulation instructions

Instruction
BAND
BCLR
BCMP
BMOV
BOR
BTST
BSET
BXOR

(6)

Operand
src
src
dst
src
src
src

Function
Bit And
Bit Clear
Bit Compare
Bit Move
Bit Or
Bit Test
Bit Set
Bit Exclusive Or

Rotate and shift instructions
dst

RLC

dst

RR

dst

RRC

dst

SLL
SRA
SRL
SWAP

dst
dst
dst
dst

Operand

Function
Rotate Left
Rotate Left through
Carry
Rotate Right
Rotate Right through
Carry
Shift Left Logical
Shift Right Arithmetic
Shift Right Logical
Swap Nibbles

CPU control instructions

Instruction
COMC
CLRC
DI
DM
EI
HALT
NOP
SETC
STOP

240

BF,
dst
BF,
src,
BF,
dst,
dst
BF,

Instruction
RL

(7)

Function
Branch on Bit Clear
Branch on Bit Set
Branch
Call Subroutine
Short Call Subroutine
Decrement and Branch
on Non-Zero
Interrupt Return
Jump
Return

Operand

src

Function
Complement Carry Flag
Clear Carry Flag
Disable Interrupt
Data Memory Prefix
Enable Interrupt
Halt CPU
No Operation
Set Carry Flag
Stop CPU

8-Bit Microcomputer (VCR System Controller)

SM8202/SM8203

System Configuration Example (VCR)

•
(1)

SM8202
Serial
interface

Drum
D-FG

P33/SI
Microcomputer
for a timer

P50/PWMo

P3,/SCLK

P5J!PWM I
P3s/S0

D-PG

RESET

C-FG
P5z/PWM 2
P53/ PWM 3

P4o/ADo

REC-CTL8
CTL head
REC-CTLEB
N

Mechanism sensor

P4J!AD I

Cassette sensor

P4z/AD 2

Mechanism control

Pl o

Cassette control

Ph

Reel sensor

PI.

0

N
00

~

en

PB-CTL

PG-ADJ

;J;
HSW

~

XI

P3 adjust

Head switching pulse

VSYNC

Vertical synchronous signal

FV

False synchronnous signal

Crystal c::::::J

~

X2
P32iTO
VDD
TEST

P31/AHSW

Buzzer output
Audio head switch

Vss

- . - . - - - - - - - - - S H A R P -.-----------...-:~
241

~

8.,..Bit Microcomputer (VCR System Controller)

SM.8202/SM8203

(2) SM8203
.Serial
interface
Drum

D-FG

P33/S1
icrocompute.....- t - - -..... P3./SCLK
for a timer
P3s/S0
RESET

P50/PWMo
P5i/PWM I
D-PG
C-FG
P52/PWM2
P53/PWM3
Capstan

P4o/ADo

REC-CTL8
CLT head
REC-CTLEB

Mechanism sensor - - - - - I... P4i/AD1
Cassette sensor---..... P42/AD2
Mechanism sensor ......- - ; Plo
Cassette control ......- - ; Ph
Reel sensor - -............ Ph

(Y)

0

N

00

:E

CJ)

PB-CTL Head amp
P56/HAMP Control
Chroma

8-"""'"""

P5i/CHRO rotation
Head switching
HSW
pulse
P37/ENV
ENV comparator input

XI

PG-ADJI------...

Voo
TEST
VSYNC i+------:-Vertical synchronous signal
FV
Vss

P32/TO
P36/AHSW

False synchronous signal
Buzzer output
Audio head switch

,I"

242

SM8320

8-Bit Microcomputer (Controller with An Inverter Drive Circuit)

SM8320
•

8-Bit Microcomputer
(Controller with An Inverter Drive Circuit)

Description

The SM8320 is a CMOS 8-bit microcomputer
which integrates an 8-bit core CPU, a ROM, a
RAM, serial 110, a timer/event counter, a watchdog
timer, an A/D converter and a PWM waveform
generator circuit. It is best suited to inverter airconditioners required for an inverter drive capability of the 3-phase AC motor .

•

•

Pin Conections

o

Features
1.
2.
3.
4.
5.
6.
7.

CPU core: SM83
ROM capacity: 12,288. X 8 bits
RAM capacity: 256 X 8 bits
Instruction set: 81
Subroutine nesting: using RAM area
Instruction cycle time: I p. s (MIN.)
Interrupts
External interrupt: 1
Internal interrupts: 7
8. Input/Output ports
110 ports: 40
Input ports: 8 (for switching with A/D
input)
PWM output ports: 6
9. A/D converter: 8 bits (8 channels)
10. Counter/timer: 2 sets
1 L PWM waveform generator circuit
12. Watchdog timer
13. Standby function: STOP/HALT mode
14. Crystal" or ceramic oscillator circuit
15. Supply voltage: 5V ± 10%
16. Package
64-pin SDIP (SDIP64-P-750)
64-pin QFP (QFP64-P-1420)

Top View

24.3

SM8320

8-Bit Microcomputer (Controller with An Inverter Drive Circuit)

•

Block Diagram

r-----------------------------------,
SM83
I
INC/DEC
CPU core:
I
I

PC

SP

1
u

F

A
B

C

D

E

L ________________ _

ROM
(12,288 x 8)

RAM
(256 x 8)

I
______________ J

Timer A

Timer B

PWM

Signal
Generator

Timer C
J - f - - - - - I (Watchdog
Timer)

.-~.------SHARP

244

---.-.-.-.--...-.-.---

8-Bit Microcomputer (Controller with An Inverter Drive Circuit)

•

SM8320

Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Output HIGH current

Symbol
Voo
VI
Vo
IOH
lOLl
IOL2
IOL3

Output LOW current

~IoH

Total output HIGH current

~IoLl
~IoL2

Total output LOW current

~IoL3

Operating temperature
Storage temperature

•

Rating
-0.3 to +7.0
-0.3 to VoD +0.3
-0.3 to Voo+0.3
-4
4
30
,
15
-20
20
80
45
-20 to +70
-55 to +150

Conditions

All output ports
Output ports except for PWM o-PWM 5 , P3 0 -P3 3
PWM o-PWM 5
P3 0 -P3 3
All output ports
Output ports export for PWM o-PWM 5 , P3 0 -P3 3
PWM o-PWM 5
I
P3 0 -P3 3

Topr
Tstg

Unit
V
V
V
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
"C
"C

Recommended Operating Conditions
(Ta=-20 to +70"C)
Parameter
Supply vortage
Instruction cycle
Oscillating clock frequency

•

Symbol
Voo
tSYS
f

Rating
+4.5 to +5.5
16.0 to 0.95
0.25 to 8.0

Unit
V
ps
MHz

(V oo ",,4.5 to 5.5V, Ta=-20 to +70"C)

DC Characteristics
Parameter
Input voltage

Symbol
VIHl
VILl
VIHl

Conditions

VI~l

Input current

Output voltage

.

Current consumption
Note
Note
Note
Note
Note
Note
Note
Note

1:
2:
3:
4:
5:
6:
7:
8:

IIHl
IILl
IIH2
IIL2
VOHl
VOLl
VOH'2
VOL2
VOH3
VOL3
100
IOOH
Ioos

VIN=Voo
VIN=OV
VIN=VOO
VIN=OV
IoH =-lmA
10L=lmA
10H=-lmA
IOL=10mA
10H= -400 P A
IOL=20mA
fs=IMHz
fs =IMHz HALT
Oscillation STOP

MIN.
0.7Voo
0
Voo-0.5
0

TYP.

MAX.
Voo
0.3Voo
Voo
0.5

50
-50
10
10

Unit

Note

V

1

V

2

pA
pA

3
4

pA

5

V

6

V

7

V

8

Voo-0.5
0.5
Voo -0;5
2
Voo-0.5
2
6
2
1

10

rnA
rnA
pA

Applied to pins PO O-P0 7• Pl o-P1 7• P2 o-P2 7• P3 0-P3 7• P4 o-P4 7• P5 0-P5 7• and RESET.
Applied~to pins TEST" TEST 2 • and CK ,.
Applied to pins PO O-P0 7• Pl o-PI'7. P2 o-P2 7• P30~P37. and P4 o-P4 7 that have a pull-down resistor.
Applied to pin SCK that has a pull up resistor.
Applied to pins P5 0-P5 7• RESET. TEST" TEST 2• and PO-P4 that have no pull down resistor (when in input mode).
Applied to pins PO O-P0 7• Pl o-PI 7• P2 o-P2 7• P4 0-P4 7• and CK 2 •
Applied to pins P3 0-P3 7.
Applied to pins PWMo-PWM 5 •

245

8-Bit Microcomputer (Controller with An Inverter Drive Circuit)

•

SM8320

Pin Functions

(1) GND, Voo (Power supply inputs)
The V DD pin should be positive +5V (TYP.)
with respect to GND.
(2) TESTj, TEST2 (Device test inputs)
The TEST pins must normally be connected to_
GND.
(3) RESET (System reset)
The RESET accepts an acvtive-Low system reset which initializes the internal logic of the device.
It is internally connected to the positive supply
V DD with a pull-up resistor. Normally a capacitor
is connected between this pin and GND to provide
a power-on reset function. _

(6) VRF, AGND (Reference power for AID
converter)
The VRF and AGND pins are reference power
supplies for AID conversion. A High level of reference voltage (MAX. V DD) should be input to the
VRF with respect to AGND, and a minimum GND
level of voltage should be input tothe AGND.
(7) PO O-P0 7 , P1 o-P1 7 , P2 o-P2 7 , P3 o-P37 (I/O
ports)
Ports PO, PI, P2 and P3 may be independently
set to Input or Output mode. These ports are all set to Input mode after reset. The P3 port can output a
large drive current (sink current).
(8) P4o-P47 (I/O ports)

(4) CK1 , CK 2 (System clock oscillator)
The CK 1 and CK z pins, in conjunction with an
external ceramic or crystal oscillator, provide a
system clock oscillator. An external clock must be
input to the CK 1 pin.

Port P4 may be independently set to Input or
Output mode. It serves for switching with a serial
110, a timer, an input clock or a PWM output pause
input.
(9) P5 0 -P5 7 (Input port)

(5) 4J (Clock output)
1> , the system clock output pin, provides a clock
frequency which is one eighth the master clock frequency (CK 1).

•

The P5 is an input port, which can be used to
input an analog data for AID conversion.
(10) PWMo-PWM 5 (PWM output ports)
The PWM output port is used to output the inverter drive signals for a 3-phase AC motor converted from the internal ROM data through an internal PWM generator circuit.

Functiond Connections
Voo

246

8-Bit Microcomputer (Controller with An Inverter Drive Circuit)

•

Hardware Configuration

(1) Address architecture
The on-chip ROM is allocated in the address at
0000-2FFF (12K bytes), a RAM at FE80-FF7E
(256 bytes) and port register at FFDO-FFFF.

SM8320

tion are allocated in the address shown in Fig. 2.
Applying a Low level signal to the RESET pin
starts excution of the user's program at address
0000.
(3) Data memory (RAM)
The data memory has 256 bytes and is allocated
in the address at FE80-FF7F,

0000

(4) Control register
The control registers including an I/O register
and a mode register are allocated in the address at
FFDO-FFFF.

On-chip ROM (12K bytes)

2FFF
3000

(5) CPU c~re structure
The internal CPU core consists of an accumulator, a general-purpose register, a program counter,
a stack pointer, an interrupt mask. register, an interrupt master enable flag and an arithmetic logic
unit (ALU).

Not addressable

FE80

On-chip RAM (256 bytes)

FF7F
Not addressable

8-bit
A

8-bit
F

B

C

Accumulator
B register

D

E

D register

L

H register
L register
Program counter (16-bit)
Stack pointer (16-bit)

FFDO
FFFF

Port, register

H

PC
SP

Fig. 1 Address architecture
(2) Program memory (ROM)
The program memory has 12K bytes and is allocated in the address at 0000-2FFF. 9 interrupt
vectors and a jump destination of an RST instrucAddress
0000
0008
0010
0018
0020
0028
0030
0038
0040
0048
0050
0058
0060
0068
0070
0078
0080

Flag register
C register
E register

~ Interrupt mask register (FFFF)
~ Interrupt master enable flag

Fig. 3

SM83 CPU core internal register structure

Vector
Start address/RSTO
RSTl
RST2
RST3
RST4
RST5
RST6
RST7
INTO: External STPinterrupt
INT1: Start/End bit inten'tiptfrom a PWM generator circuit
INT2: CNT121CNTGG counter interrupt from a PWM generator circuit
iNT3: TIMA overflow interrupt
·INT4: Interrupts for the end of A/D conversion, comparison and SIO transfer
INT5: TIMB overflow interrupt
INT6: TIMC overflow interrupt
INT7: DIV overflow interrupt
NMI: Mask disable interrupt (watchdog timer overflow interrupt)

Flg.2 Vector addresses

~i
.1

--.----.------~SHARP.-~-- ......... '.-.~-247

8-Bit Microcomputer (Controller with An Inverter Drive Circuit)

(6) PO, P1, P2 and P3 (I/O ports)
The PO, PI, P2 and P3, 8-bit I/O ports may be
switched between Input (0) and Output (1) modes
with a directional register. The corttents of the output data register should also be transferred to the
accumulator Ace.

(7) P4 (I/O port)
The P4 is an 8-bit I/O port, and with a program,
pins P4 3 -P4 5 serve as serial ilo (SIN, SCK, SOUT),
pin P4 6 serves as a counterltimer input (KT) and
pin P4 7 as a stop signal input of a PWM output
and an external interrupt input (STP).
(8) SIN, SCK, SOUT (Serial 1/0)
The serial I/O ports consist of a couple of register, 8/4/211 counter and controllers, which are
used to transmit and receive 8-bit data synchronized with the shift clock.
(9) P5 (Input port)
The P5, input port, can be set to the analog data
input for an AID converter with a program.
(10) AD o-AD 7 (AID converter)
The device contains an 8-bit AID converter
with 8-channel multiplexer analog inputs. The AI
D converter inputs can be set to 3 modes including
an automatic AID conversion mode, a comparator
mode between analog input value and internal register, and an input mode. The mode is normally set
to the input mode.

• Input mode
When in input mode, there is no
data transfer from accumulator to port P5, and the
current status (digital value) of the port should be
loaded into the accumulator.
• AID conversion mode
In the AID conversion
mode, an analog data of selected channel (one of
ports P5 0 -P5 7) is converted into digital data which

SM8320

will be loaded into the accumulator. Then, if an interrupt is enabled, the CPU acknowledges the interrupt. The AID conversion will be performed by
comparing voltages determined by a ladder resistor
placed between VRF and AGND with analog inputs. The AID conversion cycle should be 68 f1 s at
8MHz bf oscillation frequency (1 f1 s of system
clock).
• Comparator mode
In the comparator mode,
one bit location of control register is determined
according to large or small data obtained by the
comparison between data registers and analog inputs. Upon completion of comparator operation, the
port is used for switching with general-purpose
input.
(11) Timer
The timer circuit consists of a 6-stage prescaler,
an 8-bit divider (DIV), an 8-bit timer A, B, C, and
a timer control register (TMODE). The timer C can
be used as a watchdog timer. The prescaler input
clock is used for a system clock 1> (reference clock
fl8).
(12) Interrupts
The interrupt functions include 8 kinds of maskable interrupts (internal: 7, external: 1) and a
non -maskable interrupt (see table 1).
The interrupt request flag (IF o-IF 7) is set if a
mask able interrupt (IRQo-IRQ7) occurs. Then, presetting the corresponding bit of interrupt masterenable flag (1M E) and interrupt mask register
issues the interrupt.
If more than one interrupt occurs simultaneously, all of the corresponding interrupt request flags
will be set, but the CPU will only acknowledge that
interrupt with the highest priority and other interrupts will be queued.

Table 1 Interrupt reguest
Priority
1
2
3
4
5
6
7
8
9

248

Address
0080
0040
0048
0050
0058
0060
0068
0070
0078

Interrupt
NMI: Mask disable interrupt (Overflow interrupt of watchdog timer)
IRQ 0: External STP interrupt
IRQ 1: Start/End bit interrupt from aPWM generatorcircuit
IRQ 2: CNT12/CNTGG counter interrupt from a PWM generator circuit
IRQ 3: TIMA overflow interrupt
IRQ 4: Interrupts for the end of A/Dconversion, comparison and SIO transfer
IRQ 5: TIMB overflow interrupt
IRQ 6: TIMC overflow interrupt
IRQ 7: DIV overflow interrupt

Mask
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable

8-Bit Microcomputer (Controller with An Inverter Drive Circuit)

SM8320

(13) Reset function
Applying a Low level signal (master clock period
X 2) to the RESET pin resets the internal logic of
the device and starts execution of the program at
address 0000.
The following two reset functions are also avail·
able:
1) The interrupt master enable flag IME, interrupt mask register IE and interrupt request flag IF
are reset to disable all mask able interrupts.
2) The port and mode registers are initialized.
The other registers are indefinite. Applying a High
level signal to the RESET pin with a double master
clock frequency (32.76SkHz at SMHz master clock)
starts execution of the program.

Basic operation of PWM waveform
generator circuit
The PWM waveform data is written to the program area of ROM, and the start address and the
waveform data output interval (sampling time) are
specified on the register. Thus, every time waveform data is read from ROM, the waveform ROM
address counter is automatically incremented or
decremented, and the waveform data at the addressed area is directly transferred to the waveform
data buffer.
Then, PWM waveforms are automatically generated via the data conversion circuit and the rise delay circuit, and output from the PWM o-PWM 5
pins.

(14) Standby mode
The standby mode includes HALT mode and
STOP mode. In each standby modes, output ports,
internal registers and internal RAM remain operative.
HALT mode
Executing the HALT instruction places the device in HALT standby mode.
To reduce power consumption, the system clock is
inactivated. However, the oscillator circuit between
CK 1 and CK 2 is operating, and the DIY, SIn and
timer remain operative, provided their operations
do not depend on the system clock. The PWM circuit is inactivated. While in HALT mode, if a Low
level signal is applied to the RESET pin, or an interrupt enable flag is set, the device exists HALT
mode.
• STOP mode
Executing the STOP instruction places the device in STOP standby mode,
and the entire system clock except for external
clock of SIO and timers is inactivated. While in
STOP mode, if a Low level signal is applied to the
RESET pin, or an interrupt occurs such as a High
level signal is applied to the SIO, timer A or STP
pin, the device exists STOP mode.

(2) PWM waveform data preparation
The waveform data provided in any way are
generally obtained by comparing 3-phase AC
waveforms (3 different sine curves having a phase
difference of 120 degrees) with delta waveforms
and converted into 3-bit data and then written to
ROM.
Fig. 4 shows an example for PWM waveform
data preparation.
It is not necessary to have data for one cycle
(360 degrees). Only having data for 30, 60, 120 or
ISO degrees allows waveforms of 360 degrees.

•

PWM Waveform Generator Circuit

The PWM waveform generator circuit automatically outputs inverter drive PWM waveforms
which are· 3-phase AC waveforms required for
driving compressors such as inverter air conditioners, from the PWM 3 -PWM 5 pins. This circuit
greatly reduces loads on software.
In addition, the lower 6 bits of the internal ROM
data can be automatically output as they are from
the PWM 3.-PWM 5 pins. They can be used as drive
waveform output Jor stepping motors.

(1)

(3) Sampling time
The sampling time can be set in steps of 0.25 p s.
in the range from 10 p s to 256 p s.
The frequency of the PWM waveform (sine
curve) can be varied based on the waveform data
written to ROM by 'changing the sampling time.
(4) Delay time setting
When external transistors are used as the drive
elements for the inverter and a pair of transistors
which are vertically connected in push-pull configuration are alternately switched, one transistor
must be turned ON corisidering the delay time at
the time when the other transistor is turned OFF
in order to prevent short circuit in the vertical
direction.
The delay time varies depending ontarnsistor
types and must be changed in accordance with
them.
Tbis microcomputer allows this delay time to be
freely set in steps of 2 p s in the range from 0 to
30 p s or in steps of 0.25 p s in the range from 0 to
3.S5 ps.

-.-----~-...-.--SHARP,~.-~-~----

249

SM8320·

8-Bit Mictocomputer (Controller with An Inverter Drive Circuit)

1--------~·3600--------..j

(a)
3~phase

3-phase AC waveform
a, band c indicate the 30 degree sam-

ple waveform of one cycle. 360 degree
waveform can be obtained by combining
I-phase~--+-~~~~~~-+--~--4---+---+-~~~--~

inverted waveforms of a, band c with inverted-timeframe waveforms.

2-phase

,
,,
,..

_'-

(b)

1
1
1
I

Itt

In comparing AC wave with daltas at
certain interval (sampling time), if delta

I

-,- ... -.J c 1 1
I-"'-.J
1

Comparison with deltas

wave is positioned iii upper part of AC

,

,
1

a

wave, the binary code should be 1, and in

1
l

lower part of AC wave, it should be O.

,
1
1
1

I

,
1
1

1
:

:

I

,I

I

I

I

1

"

:

"""'---',-+-W
- +--,--;- "1'-..,-

, , ,

I

1

(c)
a

0 0 0

0 1

1

1

1

b

0 0 0

0 0

0

1

0

0

0

0

0

c

1 1 0

1 1

1

1 1

1

1

0

0

1 0 0 0

1

1 1

1

0

0 1

0

1

1

1

1

,

30 degree PWM waveform data
One cycle of PWM waveform is auto-

matically formed by an internal conver-

,,
,
,

sion circuit based upon 30 degree PWM
waveform data.

I

I

~~--~

1

I

:

:a

I..j--+-.......-j

~-r--~~--~-r--I~ r'--r--+'--+:--r-----i--'

:,cJ.1

I

~I--~!--~~:--r-~~~

W-rR

::
I

I

PWM 5

I

I

'

r-A

,~I

::

PWM 4

:

:

,.

I

,+__.--;-'--""'-;---i--!',

I

(d)

Output data from PWM

The ON signal is output with delay
time not to simultaneously turn on the ex-

,

ternal power transistor composed of ex-

I

ternal push-pull type (see System Con-

R.n,: b

,

.:~

:

PWM 3

,

: i Ir-~~-+~
:-~
, ,
,

r-~~--r-~~~~

PWM 2

,

I

,

PWMo

~

figuration Example).

",
I

I

I

':: c
i

'r-~~--~~--~~--~'-, r'--.,...~--~~'-...

~

::RJ

- : ON signal delay time

Fig. 4

Example of PWM )Navefrom data

.....-.--.-.---------~SHARP

250

___ ~ _ _ -.--~-.-r

8-Bit Microcomputer (Controller with An Inverter Drive Circuit)

•

Instruction Set

The SM8320 has 77 instruction set.

(1)

(2)

(3)

(4)

SM8320

(5)

8-bit transfer instructions,
I/O instructions
(2 kinds, 19 instructions)
LD,LDX

Rotate, shift instructions
(12 kinds, 12 instructions)
RLA,RLC,RLCA,RL,RRA,RRC,
RRCA, RR, SLA, SRA, SRL, SWAP

(6)

16-bit transfer instructions
(4 kinds, 6 instructions)
LD,LDHL, POP, PUSH

Bit manipulation instructions
(3 kinds, 6 instructions)
BIT, RES, SET

(7)

Jump instructions
(2 kinds, 5 instructions)
JP,JR

(8)

Call, return instructions
(4 kinds, 6 instructions)
CALL, RET, RET!, RST

(9)

CPU control instructions
(7 kinds, 7 instructions)
CCF, DE, EI, HALT, NOP, SCF,
STOP

8-bit arithmetic instructions,
Logic instructions
(12 kinds, 12 instructions)
ADC, ADD, AND, CP, CPL, DAA,
DEC, INC, OR, SBC, SUB, XOR
16-bit arithmetic instructions
(3 kinds, 4 instructions)
ADD, DEC, INC

~

. - . - . - - - - - - - - - - - S H A R P .-.-..-.---~--251

--.~

8-Bit Microcomputer (Controller with An Inverter Drive Circuit)

•

SM8320

System Configuration Example (Outdoor unit of inverter air-conditioner)

IGBT or Power transistor

Power
supply

Compressor

-

Photocoupler

-= Vl.;r:=

Voo
VRFI------A/D reference voltage

r-- PWM5

~

~:~:

P57

t,r--PWM,

x6

r-- PWM I

P5,
P53

-PWMo

I

Erro~ detection
ClrcUlt

!---c-0utdoor air temperature

P56
Thermal I - - Heat exchange temperature
P551------I sensor r---- Discharge duct temperature
I-Suction temperature
valve temperature

I - - Two-way

P5,
P47/STP

Pulse signal--------tP46/KT

,-------,

t---------iP45/S0VT
:.\licrocomputer i - - - - - - - - - - I P 4 4 /SCK
for indoor unit
i - - - - - - - - - I P 4 3 /SIN
-----IP4,
-----IP41
-----IP40
Control signal

-----IP37
-----IP36
----_IP35

+5V

----_IP3,

r.
t---t\!.""t+-.JNIr----------1P33
~~-+~-~---------IP3,

?=
;:.

i

SM8320

P031------.f(O~u;;;tt;:dko:;;o;rtf:;a_;;n~m;;:;;;o;.to:;;r:_;;re;;jI;a~yl
I 1 - - - - - - - 1 Four-way value relay

Load resistor
P00r::---=----t.=.::..:..=:.::.:...-_ _--1
P1 7 t - - - - }
I
1
Control signal
Pl,I---~

P13~-~-----~~Efll;ecdt;r~ol~1i;c----_,
expansion valve

I

P l o l - - - - - -__-_--lStepping motor

~}

P27

P2 4 t------<:.

Reset
circuit

---.-J

I

P2 3
I

I

:
,

:

........

~}

........

P2ot-----<:·

Waveform, data select switch

-0-

Delay time select switch

~

r--~_iTEST I
t----~TEST 2

t----IGND

CK

1

+

CK,I---~¥r-8~M~H~z----1
' -_ _ _ _ _ _ _ _ _ _--,..1
Ceramic

252

I

Input for operation check

I
PO,i------

L---H~-~--------~P3o

--I.-----~RESET

}

P0 7 1------ }

~--+~-~---------IP31

Fault indicator LED

Load current
detection circuit
Input signal

I

P5 1
P5 ol - - - - - - AGNDI----.J-

=i

Development Support Tools

LUXXXH2

Evaluation Board for SM Series

LUXXXH2
•

Evaluation Board for SM Series

Description

• , . Outline

The LUXXXH2 is an evaluation board for use in
developing programs of 4-bit single chip microcomputer SM series. It is available for any types of
evaluation board applicable to each SM series.
The evaluation board is equivalent to the SM
series with ROMless in functions and electrical
characteristics. It is designed to develop programs
together with an EPROM or the development support tool SME-30 emulator in RAM basis.

•

Features

1. System debug with EPROM
2. Debug in RAM basis in conjunction with an
emulator SME-30
3. Typical functions of the evaluation board
· Hold function
• One-step function
• Auto-stop function
· Program counter indicator
· Accumulator and carry F IF indicator
· RAM address register and memory indicator
• Instruction code indicator
• PLA specification function

----.----~---SHARP-------~--- ~

254

LUXXXH2

Evaluation Board for SM Series

•

Block Diagram (LU500H2A)

Vcc (+5V) GND

Vcd-5V) VDD (-3V)GND(OV)

!

I ~i~~l~~e II ~uto:stop L

I~~~~:~ircuit

,--,:;:c~ir~cu<:,i.;;..t--' ,--c_lr~c:;>,U1:::-t_-I1

Idisplay circuit

LU500H5
GND,VC,vDD
ACLi+-

li f- li

SCTRLv-----------~

J1L-----Jr l~ ~

~ ~~DlJ*

STEP
'--'0
0:
8
HOLDSr-____~____~ r-' u
.s.s
Al-A,I-_ _ _ _ _ _"I

I
ACLI

ACL,

I

~ - ~ ~I r
r-

System
osciJ.lator
circuit

User program area
EPROM 2764 to 27256
'-

RAM address
display
~circuit

Evaluation Board of SM Series

The evaluation board consists of a couple of
printed circuit boards including a control board
and an evaluation card integrating with an evaluation chip and an EPROM socket (see Fig. 1).
For example, the evaluation board of single chip
microcomputer SM500 consists of an evaluation
card (LU500H4A) and a control board.(SM-EVBOARD-2).

One-step
circuit

RUN
/HOLD
circuit

I

I

rIkn~/STOpll
circuit

I

RAM data
display
circuit

Flag
circuit

I

~ Register
display
circuit

I

I

SM EVBOARD 2
Control board

LU500H4A
Evaluation card

•

ACL/ACLI

HOLD2
SCTRL
SWDo-SWD3

'-

ACL
circuit

Control board

/

q~T~\~
Evaluation chip

Fig. 1

Evaluation card
(LUXXXH4)

Evaluation board structure

---....--------SHARP---------.255

LUXXXH2

Evaluation Board for SM Series

Components Layout on The Board

•

In explaining the LU500H2A, see Fig. 2 for the ,.
evaluation card (LU500H4A) and Fig. 3 for the
control board (SM - EVBOARD).

LU500H5

6

Fig. 2

Table 1
No.
1
2
3
4
5
6
7

8

Components
C2 connector
(50-pin connectpr)
IC socket for
programmed EPROM
C 1 connector
(40-pin connector)
Power supply terminal
EPROM select switch
Evaluation chip
C3. connector
(50-pin connector)
PLASW

LU500H4A component layout

LU500H4A Component Description
Description

Inputs and outputs data.
Adapts an EPROM written with user's program.
Inputs and outputs data,
Applies DC voltage.
Selects between 2764 and 27256 for EPROMs.
LU500H5, provides the logic function of SM500~
User's connector
Connects with the cable from the user's system.
Specifies the PLA.

-'---~---SHARP'-'--------

256

LUXXXH2

Evaluation Board for SM Series

17 }--t--t--'O FRO

D

OFRI
OFR2L_O
OFR3
L-l
OFR:4

OFR5
SAB

DODD
L-7 L-8 L-9 L-IO

~----------------------4-~~5

Fig. 3 SM-EVBOARD-2 component layout
Tble 2 SM-EVBOARD-2 Component Description
No.
1

2

3
4
5
6
7
8
9
10
11
12
13

14
15
16
17

Description
Inputs and outputs data
L-O to L-13 indicate registers and operation codes.
• L-l and L-2 indicate the RAM address counters BM and BL.
• L-4 indicates the RAM contents specified by BM and BL.
Data indicator LED
- • L-6 indicates the contents of the accumulator.
· L-7 to L-9 indicate the contents of the program counter.
• L-ll to L-13 indicate the operation codes.
Applies DC voltage
Power supply terminal
(Applies + 5V to the Vee with respect to GND.)
CSW indicator LED
Turns on with the CSW switch ON, and turns off with the CSW switch OFF.
Bit numbers of the step PL for the program counter. (set to 6 in the LU500H2A)
BitSW
Selects data output from the data pins Do-D 7 ,
CSW switch
(not used in the LU500H2A)
STEP switch
Turning on this switch checks the program at everyone step.
.
'RUN/HOLD switch
Executes program at the RUN side and stops at the HOLD side.
Turning on this switch activates an auto-stop function.
BP switch
Controls the clock start with 1 sec. signal.
1Hz switch
ACL switch
, Turning on this switch enables the evaluation chip to activate the ACL operation.
ACL polarity select SW Selects the ACL polarity. Set to the ACL in the LU500H2A.
CTRL switch
When developed using the LU500H2A only, turn this switch on.
ADDRESS switch
When used with an auto-stop function, specify the stop address with this switch.
(address specification)
Sets the connector according to the field and page of a program counter.
SAB AB connector
40-pin connector
Inputs and outputs data
The FRO lights up with the C F IF to be set, and turns off with the C F IF to be reset.
Flag indicator LED
Components
50-pin connector

".,": ~~

257

LUXXXH2

Evalu~tionBoard for SM Series

•

!

System Configuration Example

Connection between the emulator SME-30 and
the evaluation board LU500H2A.

Host computer

Fig.4

258

System configuration

SME-30 (LU4DH300)

Emulator for 4-Bit Microcomputers

SME-30 (LU4DH300)
•

Description

•

Emulator for 4-Bit
Microcomputers

Outline

The SME-30 (LU4DH300) is an emulation system for programming a 4-bit single chip microcomputer SM series. This system is used to develop
programs in combination with a PROM writer as
well as each type of evaluation board available for
any of the 4-bit microcomputer SM series.
Provided with the serial interface (RS-232C),
this system, connecting to the host system applicable to the software such as cross-assembler, debugs the program.
The host system is a personal computer which
can be driven under control of the MS-DOS™ operation system.

*
•

MS-DOS™ is a trademark of Microsoft Corporation.

Features
1. Exchanging the evaluation board and control
software applies to any type of 4-bit microcomputer SM series.
2. User's program area up to 16K words (16
bits/word) for all of SM series can be supported.
The user's program area is expandable up to
64K words at a 16K word unit.
3. A 16-bit step counter measures the program
execution time.
4. Historical memory for tracing the program run.
5. Symbols defined by a cross-assembler for the
operand.
6. Data rewrite with assembly languages
7. Symbolic reverse assembling
8. Allows transition of the register and flag contents.
9. Program execution from any addresses

10. B,,,k po;ot ~t ,ond;tion,
• Program counter: 2
• RAM address: 1
• Logical product of RAM address and RAM
data: 1
· External signal: 1
11. Operation mode
• Real-time execution
• Single-step execution
· Trace execution
• Dummy execution
• Snap shot execution

259

14

Emulator for 4c..Bit Microcomputers

•

SME-30 (LU4DH300)

Block Diagram

SME-30

(LU4DH300)

Monitor

Monitor

ROM

RAM

Break
circuit

I

CPU

1

User
r-

Evaluation board

RAM
~

I

4-bit SM
series
evaluation
chip

I-<

~o::!

Tenninal
Host

Serial
controller

"-

I

Buffer

I

Real time
trace
circuit
User's system

PROM write
(LU4DH160)

•

Specifications
Parameter
Clock

Specification
Switchable between
internal and user clocks

Emulation CPU

Evaluation chip

User's RAM
History RAM
Dummy RAM
Break point
Serial port
External current capacitance
Power supply
Operating temperature

16K words (16KX16 words)
2K steps
256 words
5 circuits (hardware)
RS-232CX2
1A (MAX.)
AC100V± 10%, 50/60Hz
o to 40°C

Outer dimensions

310X270X98

260

Remarks

4-bit single-chip
microcomputer SM series
Expandable up to 64K words (MAX.)

(110 to 9600BPS) at 8 levels
Current te be output

WXLXH (Unit: mm)
Not including projections

SME-30 (LU4DH300)

Emulator for 4-Bit Microcomputers

•

Connection Method

Two connection methods between the SME-30
emulator and the host system are available depending upon the types of the host system.

(1) Local mode
The local mode is available for the CRT separation type of host system. In this mode, connection is
possible only with the RS-232C interface between

(RS-232C)
Host unit

HOST
TERM

the emulator and the host system. Fig. 1 shows the
connection diagram of the system in this mode.

(2) Remote mode
The remote mode is available for the host system
embedded CRT. In 'this mode, the RS-232C interface and the software interface connect the emulator with the host system. Fig. 2 shows the connection diagram of the system in this mode.

SME-30
emulator

(RS-232C)

-

SM-series
evaluation
board

r--

User's
system

(RS-232C)

CRT with
keyboard

Printer

Fig. 1 Connection at the local mode

(RS-232C)
Host unit

HOST

SME-30
emulator

t--

SM-series
evaluation
board

t--

User's
system

Note: The TERMIN AL pin is non connection.
Printer

fig. 2 Connection at the remote mode

-----------------SHARP--------261

SM E-30{LU4DH300)

Emulatoi-for 4-Bit Microcomputers

• . Develppment Circumstances of MSDOS™ personal computer and SME-30
MS-DOSTM ~
Personal
~
0
u
computer
Cross-assembler
Mapper

RS-232C

--- -z..-

1

(2) Cross-assembler
The cross-assembler is used to assemble the
source program provided by the editor, and make a
list file and an objection file .on request.

SME-30

System program

f-<

I
4bit
microcomputer revaluation board

User's
system

(1) System Program
The system program is given by the each
MS-DOS™ disk which depends on models.

262

(3) Mapper,
.The objection mapper program is used to replace
the objection file on the .disk'ette assembled by a
cross-assembler with. the steps and pages for
easy-to-read report.
(4) Terminal controller
The terminal controller is a program for the connection between the SME-30 emulator and the personal computer. The program depends on the personal computers.

LU8200H7
LU820XH4

SM82 Series In-circuit Emulator
SM82 Series Emulation Pod

LU8200H7/LU820XH4
SM82 Series In-circuit EmulatorlEmulation Pod
•

Description

•

The SM82 in-circuit emulator is designed to
effectively program an 8- bit single chip micro·
computer SM82 series.
This system consists of an in-circuit emulator
(LU8200H7) and a replaceable emulation
pod (LU820XH4), which is available for any type of
'
the SM82 series.
The host system must be controlled under the
MS-DOS™ operation system as well as provided
with the RS-232C interface unit or the Centronics
interface unit which allows a high speed transfer of
the program to the emulator unit.

*
•

Outline
Emulator unit (LU8200H7)

Emulation pod (LU8202H4)

MS-DOS™ is a trademark of Microsoft Corporation.

Features
L 64K bytes of emulation memory
A variety of brake and trace functions
Real-time operation
Execution time scale
Reverse assembler and line assembler
Symbolic debugger
The coverage function checks nonaccessed area
under programming
8. Centronics interface unit allows a high speed
down load and a connection to the printer
9. Exchangeable emulation pod applicable to any
type of the SM82 series
2.
3.
4.
5.
6.
7.

•

Specifications
Parameter
Clock
Emulation
Emulation memory
Break point
Break counter
Serial interface
Parallel interface
Power supply
Operating temperature
Unit

Specification
On-chip/user clock switching
SM82 evaluation-chip
64K byte
2 (hardware)
16-bitX2
RS-232CX2
Centronics input X 1
output X 1
AC100V±10% 50/60Hz
o to 40·C
330 (W)X315 (D)X150 (H)

--.-.----------SHARP - - - - - - - - - - - - - 263

LU8200H7
LU820XH4

SM82 Series In-circuit Emulator
SM82 Series Emulation Pod

•

Block Diagram

Emulator unit (LU8200H7)

Monitor
ROM

Monitor
RAM

Emulation pod
(W820XH4)

User
RAM

Break
circuit

~

I

CPU

Terminal
Host

Serial
controller

1

~ controller
Parallel

I

Prmter Host

•

r--

Buffe

Buffer t -

'---

"""-

Real-time
trace
circuit

I

~ monitor
SM82ROM

,I

1evaluation
SM82
chip

To user system

System Configuration

Below shows the development support system of
an 8-bit single chip microcomputer SM82 series.

(1)

SM82 in-circuit emulator
• Emulator unit
. SM82 emulation pod

(2) Host system
The host computer system operates under control of the MS-DOS™ operation system, which is
designed to make a program of the SM82 with the
cross-software mentioned below. The program

should be down-loaded into the SM82 in-circuit
emulator, and debugged with the emulator. The
host system must be provided with the RS-232C
interface unit.

(3) SM82 cross-software
The cross-software consists of an assembler, a
linker, HEX dumper and an emulator control software, which is offered by SHARP.
Note: The emulator may have some different function from an
actual device. The operation must finali y be checked with a pig·
gy- back device.

---~-----SHARP'---~--""""",~"""",

264

SM82 Series In-circuit Emulator
SM82 Series Emulation Pod

•

LU8200H7
LU820XH4

Connection Method

(1) Connection between the emulator unit
and the emulation pod
Fig. 1 shows the emulator unit from a front view,
and Fig. 2 shows from a back view. Fig. 3 shows
the emulation pod. The connector of the emulation
pod must be connected to the connector located in
the front of the emulator. The side of the emulation
pod is provided with a connector for eight external
ternal probe cables which accept the maximum of 0
to 5.5V of input voltage.
RESET

D

CNl 1
...._ _ _-,'

POWER

CN211..._ _ _ _.....

D

CN31

Front side of emulator

Fig. 1

HoollORM

nPAfr 0 gs
UU

ACINPUT

D

PARA.OUT

Fig. 2

I
Connector for

Rear end of emulator
CN-3

~=::;::;:===:

CN-2
emulator unit \!=:=~=~
CN-l

Emulation
pod

Connector for
external probe

probe cables which accept the maximum of 0 to
5.5V of input voltage.
(2)

Connection between the emulation pod
and the user's system
The connector of user's system must be inserted
into the socket, adjusting the pin No.1 (see Fig. 3).
And at the same time, connect a ground clip to the
ground of user's system. The external probes receive signals from user's system to store the signal
levels into the trace memory and to be broken.
(3) Connection to the peripheral equipment
The connectors equipped with the back of the
emulator unit may be used to connect with
peripheral equipment (see Fig. 2). It is designed to
connect to the host system in a serial interface
cable (RS-232C) or in a parallel interface cable
(Centronics).
The emulator makes a command control in a serial communication with the RS-232C interface. Be
sure to connect the serial connector of a host system with the TERM connector of the emulator. A
down-load interface type of user's program deyelped with a host system can be specified with a
command control between the RS-232C serial interface and the Centronics parallel interface. When
a high speed parallel down-load interface is
selected, connect the printer connector of a host
system with the PARA. IN connector of an emulator. When the display contents are printed using a
printer, connect the Centronics interface connector
of a printer with the PRINTER connector of an
emulator. Fig. 4 shows the connection diagram between each equipment.

Serial connector

RS-232C

Host unit
Printer connector

I
Connector for
user system

Pin 1

Pin 64

Fig. 3

Emulation pod

Printer

Fig. 4

CENTRONICS

TERM
Emulator
PARA.IN
PRINETR

I

CENTRONICS

Connection diagram between systems

SHARP offers the emulator control program
together with the cross-assembler which enable the
emulator command/data to be controlled by a
keyboard/CRT of a host system.

- - - - . - . . - - - - - - - - S H A R P . - - - - . - . - - -.........
265

LU8200H7

SM82 Series In~circuit Emulator
SM82 Series Emulation Pod

•

~U820XH4

Trigger Function of SM82 in-circuit emulator

Trigger conditions
• Memory address
.. ' Memory data
• Register address
• Register data
• Bus control signals (command fetch; memory read and write, register read and
write)
• External probe signal
• Passing-through count
The above conditions can be set ,with the specifications for data area and "Don't care data" with a
bit unit.
(1)

(2) Trigger mode
· 2-level of a sequencial trigger
When a multiple nesting program is
triggered, a passing point must be specified by a sequencial trigger. This function
become.s effective only when it passed
through two points in order.
• Pre-trigger, center trigger and post trigger functions

266

• Acquisition trigger
The acquisition trigger function traces'
a necessary condition, and specifies the
trigger conditions as weJl as the machine
cycle count to be traced.
, • Time count .
The execution time from the start condition to the stop condition is measured.

(3) Real-time trace
The trace capacity has a configuration of 64 bit
words X 8,192 steps which stores:
• Memory address
• Memory data
• Register address
• Register data
• Bus control signals
• External probe signal
The pre-trigger and post-trigger conditions can
also be checked.

I',

8-bitM icrop rocesso rs/ Peripherals

Z80 CMOS CPU Central Processing Unit

LH5080
•

Z80 CMOS CPU Central Processing Unit

Description

The LH5080 is a 280 CPU fabricated with
CMOS silicon-gate process technology and is compatible with the conventional 280 NMOS CPU
(LH0080)
Due to the CMOS static structure, it provides
low power consumption and large operating
margin.
The power save mode can be obtained with a
software control on the models suffixed with "L".

•

LH5080

•

Pin Connections
LH5080/LH5080L/LH5080A/LH5080AL

CLOCK 6

Features

1. 280 CMOS CPU
2. Compatible with the 280 NMOS CPU
(LH0080)
3. 158 instructions
4. 22 registers
5. 3 modes of maskable interrupt and a nonmaskable interrupt
6. Instruction fetch cycle 1.6,ll sf 1.0 ,ll s
7. Single +5V power supply and single phase
clock
8. All inputs and outputs except clock input fully
TTL compatible
9. Fully static operation DC to 2.5MHzfDC to
4MHz
10. Low p0wer consumption
11. Power save mode (L suffix)
12. 40-pin DIP (DIP40-P-600)
44-pin QFP (QFP44-P-1010A)

25 BUSRQ
WAIT

BUSAK
WR

LH5080M/LH5080LM/LH5080AM/LH5080ALM

Note: The 280 CMOS CptJ (LH5080) is compatible with the 280
NMOS CPU (LH0080). So there is no description here about
the pins, CPU registers, architecture, interrupts, basic timings, and instruction sets. Refer back to the 280 NMOS
CPU described earlier.

--------------'--SHARP - - - - - - - - . . . . - . - - 268

Z80 CMOS CPU Central Processing Unit

•

LH5080

Block Diagram

.

System Data Bus

Halt State
Memory Request
Data Bus Interface

Input IOutput Request
Read
Write
Bus Acknowledge
Machine Cycle 1
Refresh

CPU
Timing
Control

Instruction
Decoder

Interrupt Request

Inst.
Reg.

ALU

Register Array

Non Maskable Interrupt
Wait
Bus Request
Reset
Address Logic and Buffer

Vee GND
(+SV)(OV)

System Address Bus

*Pin numbers apply to 40-pin DIP:
•

Ordering Information

L

LH5080 X X X

paCkage
Blank: 40-pin DIP (DIP40-P-600)
M: 44-pin QFP (QFP44-P-IOIOA)

Power save mode
Blank: No power save
L: Power save
Clock frequency
Blank: 2.5MHz
A: 4MHz
L----Model No.

-----.--------SHARP~--.---.-..--

269

Z80 CMOS CPU Central Processing Unit

•

LH5080

Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature

•

Symbol
Vee
V IN
VOUT
Topr
Tstg

Ratings
-0.3 to +7.0
-0.3 to Vee+0.3
-0.3 to Vee+0.3
o to +70
-65 to +150

Unit
V
V
V

·c
·c

(Vee=5V± 10%, Ta=O to+70'C)

DC Characterisitics
Parameter
Clock input low voltage
Clock input high voltage
Input low voltage
Input high voltage
Output low voltage

Symbol
VILe
VIHe
VIL
VIH
VOL

Output high voltage

VOH

Currerit consumption

Icc

Input leakage current
3·state output leakage current
3-state output leakage current .
Data bus leakage current
Current consumption in PS
mode (LH50S0LlLH50S0LM)
Note 1:
Note 2:

I ILl I
I lLOH I
I lLOL I
I ILD I
Ieeps

Conditions

MIN.
-0.3
Vee-O.6
-0.3
2.4

IOL =1.SmA
IoH = -250,u A
2.4
IoH =-50 ,uA
Vee -O.4
VIL =OAV,VIH=Vcc-OAVI LH50S0/L
Outputs open
I LH5080AI AL
VIN=OV, Vee
VouT=Vee
VOUT=OV
O;;;;VIN;;;;V ee
I LH50S0L
VIH=OV, Vee
I LH50S0AL
Outputs open

TYP.

MAX.
0.45
Vee+ 0.3
O.S
Vee
0.4

Unit
V
V
V
V
V

Note

V
10
15

50
SO

15
20
10
10
10
10
150
200

mA

- 1
2
3

,uA
,uA
,uA
,uA
,uA

4
4

1

"2

TcC=400ns
TcC = 250ns

Note 3 -(1):

Note 3 and 4:

For I III I Specification, see below circuits

For I III I , I lLOH I and I lLOL I Specifications,
see below circuit of Do-D 7 pins.

of INT pin.

Do-D7

Note 4:
Note 3 -(2):

For-I lLOH I and I lLOL I Specifications, see below
circuit of Ao - A 15 pins.

For I III I Specification, see below circuits

of WAIT, NMI and BUSRQ.

•

Capacititance
Parameter
Clock capacitance
Input capacitance
Output capacitance

(f=lMHz, Ta=25"C)
Symbol

Conditions

CeLoeK
CIN
COUT

Unmeasured pins returned
to ground

MAX.
5
6
10

Unit
pF
pF
pF

-----------..-.---SHARP .0----.-.-.-._-.-..--

270

LH5080

Z80 CMOS CPU Central Processing Unit

•

(V cc =5V±10%. Ta=O to+70°C)

AC Characteristics
No.

Parameter

Symbol

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Clock cycle time
Clock pluse high width
Clock pluse low width
Clock fall time
Clock rise time
Clock t to address valid delay
Address valid to MREQ ! delay
Clock! to MREQ ! delay
Clock t to MREQ t delay
MREQ pulse high width
MREQ pulse low width
Clock! to MREQ t delay
Clock! to RD ! delay
Clock t to RD t delay
Data setup time to clock t
Data hold time after RD t
WAIT setup time to clock!
WAIT hold time after clock!
Clock t to Ml ! delay
Clock t to Ml t delay
Clock t to RFSH ! delay
Clock t to RFSH t delay
Clock! to RD t delay
Clock t to RD ! delay
Data setup to clock t during
Mz• M3 • M4 or Ms cycles
Address stable prior to IORQ !
Clock t to IORQ ! delay
Clock! to IORQ t delay
Data stable prior to WR !
(memory cycle)
Clock! to WR ! delay
WR pulse width
Clock! to WR t delay
Data stable prior to WR ! (I/O cycle)
Clock t to WR ! delay
Data stable from WR t
Clock! to HALT t
NMI pulse width
BUSREQ setup time to clock t
BUSREQ hold time after clock t
Clock t to BUSACK ~ delay
Clock ~ to BUSACK t delay
Clock t data float delay
Clock t to control output float delay
----(MREQ. IORQ. RD. and WR)

TcC
TwCh
TwCI
TfC
TrC
TdCr (A)
TdA (MREQf)
TdCf (MREQf)
TdCr (MREQr)
TwMREQh
TwMREQI
TdCf (MREQr)
TdCf (RDf)
TdCr (RDr)
TsD (Cr)
ThD (RDr)
TsWAIT (Cf)
ThWAIT (Cf)
TdCr (Mlf)
TdCr (Mlr)
TdCr (RFSHf)
TdCr (RFSHr)
TdCf (RDr)
TdCr (RDf)

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

t Rising edge,

LH5080
MIN.
MAX.
400*
180*
180
30
30
145
125 *
100
100
170*
360*
100
130
100
50
15
70
15
130
130
180
150
110
100

TsD (Cf)

60

TdA (IORQf)
TdCr (IORQf)
TdCf (IORQr)

320*

TdDm (WRf)

190*

TdCf (WRf)
TwWR
TdCf (WRr)
TdDi (WRf)
TdCr (WRf)
TdWRr (D)
TdCf (HALT)
TwNMI
TsBUSRQ (Cr)
ThBUSRQ (Cr)
TdCr (BUSAKf)
TdCf (BUSAKr)
TdCr (Dz)
TdCr (CTz)

LH5080A
MIN.
MAX.
250*
110*
110
30
30
110
65*
85
85
110*
220*
85
95
85
35
15
70
15
100
100
130
120
85
85

ns
os
os
ns
os
ns
os
ns
os
ns
os
ns
ns
os
os
ns
os
os
ns
op
os
ns
os
os
os

50
180*
75
85

90
110

Uoit

80*

os
ns
ns
ns

80

120
110
90

100
100
90

ns
os
os
ns
os
ns
os
ns
os
ns
os
ns
ns

110

80

ns

90
220*

360*

80

100
-10*

20*
80

65
60*

120*
300
80
80
15

300
80
50
15

*Falling edge.

--------------SHARP----------271

Z80CMOS CPU Central Processing Unit

No.

44
45
46
47
48
49
50
51
52.
53

t

Parameter

TdCr (Az)

LH5080
MIN.
MAX.
110

TdCTr (A)

160*

80*

ns

TsRESET (Cr)
ThRESET (Cr)
TsINTf (Cr)
ThINTr (Cr)
TdMIf (IORQf)
TdCf (IORQf)
TdCf (IORQr)
TdCf (D)

90
15
80
15
920*

60
15
80
15
565*

ns
ns
ns
ns
ns
ns
ns
ns

Symbol

Clock t to address float delay
MREQ t , IORQ t , RD t , and WR
to address hold time
RESET to clock t setup time
Clock t to RESET· hold time
INT to clock t setup time
Clock t to INT hold time
MI ! to IORQ ! delay
Clock! to IORQ! delay
Clock t to IORQ t delay
Clock! to data valid delay

Rising edge,

LH5080

t

LH5080A
MIN.
MAX.
90

110
100
230

85
85
150

Unit
ns

l Falling edge

* For clock periods other than the minimums shown in the table, calculate parameters using the expressions in the table below

Footnotes to AC Characteristics
No.
1
2
7
10
11
26
29
31
33
35
45
50

Symbol
TeC
TwCh
TdA (MREQf)
TwMREQh
TwMREQl
TdA (IORQf)
TdD (WRf)
TwWR
TdD (WRf)
TdWRr (D)
TdCTr (A)
TdMlf (IORQf)

Formula
TwCh + TwCI + TrC + TfC
MAX. 2001's
TwCh+TfC-75
TwCh+TfC-30
TeC-40
TeC-80
TeC-210
TeC-40
TwCI + TrC -180
TwCI+TrC-80
TwCl+TrC-40
2TeC+TwCh +TfC-80

AC Test Conditions

.Input voltage amplitude: OAV to 2.8V

.Clock input voltage amplitude: OAV to
Vcc-0.6V

• Input judge level: 0.8V and 2.0V
• Output judge level: O.SV and 2.0V
• Output load: ITTL + 100 pF

• Input signal rise and fall time : IOns

.....--.--------SHARP--------272

Z80 CMOS CPU Central Processing Unit

•

Power Save Function

The LH5080L series features the power save
(PS) function. After a HALT instruction has been
executed, the internal clock signal is automatically
cut off to bring the CPU into the halt mode.

(1 ) PS mode setting
With a HALT instruction executed, the PS mode
will be automatically established. In this mode, the
internal clock signal is cut off to save the power
consumed for the clock signal operation. Cutting an
external clock signal does not give any problem in·
side, therefore, in this mode. To cut off the external
clock, it is possible to utilize the rise timing of a
HALT signal output. It should be noted, however,
that this timing cannot be used to restart the external clock.
In the PS mode, the bus request (BUSRQ) is not
accepted and the memory refresh is not done,
either.

LH5080

is then cleared and the reset just as before is
carried out.
(ii) Cle,uing with NMI: Input the NMI signal
(edge trigger) to clear the PS mode and to carry out the instruction next to the HALT. Now
the non-maskable interrupt processing routine
will be introduced.
(iii) Clearing with INT: Input the INT signal
(level trigger) regardless of which state the interrupt enable flag is in. The PS mode is now
cleared and the HALT instruction executed. If
the interrupt enable flag is set up and the INT
signal is "Low" at the clock pulse rise timing
in the last clock cycle of the HALT instruction,
the mask able interrupt processing routine will
be introduced as the next machine cycle.
CLOCK

(HALT instruction)

~~--Ml------------~-------

CLOCK

Ml

* PS

is internal signal, and not output externally.

PS'

Halt clear by RESET

* PSis internal signal, and not output externally.
PS mode setting

CLOCK
HALT

(2)

I

PS mode clear

The PS mode is cleared by any of the following;
reset (RESET), non-maskable interrupt (NMI) and
maskable interrupt (lNT).
When the external clock is shut down in the PS
mode, a stable clock signal must be input before
clearing the PS mode.
(i) Clearing with RESET: Input the RESET signal for more than 3 clock cycles. The PS mode

NMI
INT

----~L__Jr---------

* PSis internal signal, and not output externally.
PS mode clear by NMI, INT signal

--------~-.----SHARP .----.-~-~----

273

LH5081

Z80 CMOS Pia Parallel I/O Controller

LH5081
•

Z80 CMOS PIO Parallel I/O Controller

Description

The LH50S1 is a 2S0 PIO fabricated with
CMOS silicon gate process technology and is compatible with the conventional 2S0 NMOS PIO
(LHOOSl)
Due to the CMOS static structure, it provides
low power consumption and large operating
margin.
The power save mode can be obtained with a
software control on the models suffixed with "L".

•

•

Pin Connections.
LH5081/LH5081A1LH5081 B
LH5081 L/LH5081AL/LH5081 BL

o
CE
C/O SEL 5

BIA SEL

6

Features

1. 2S0 CMOS PIO
2. Compatible with NMOS 280 PIO
(LHOOSl)
3. Tow independent S-bit bidirectional peripheral
interface ports with handshake data transfer
control
4. 4 programmable operating modes
• Byte input mode
• Byte output mode
• Byte bidirectional bus mode (Port A only)
• Byte control mode
5. Programmable interrupt on peripheral status
conditions
6. Vectored daisy chain priority interrupt
7. Darlington transistor drive capability (Port B
output)
S. All inputs and outputs except clock input fully
TTL. compatible
9. Single + 5V power supply and single phase
clock
10. Fully static operation
(DCto 2.5MHz/4MHz/6MHz)
11. Low power consumption
12. 'Power save mode (L suffix)
13. Status read mode (L suffix)
14. 40-pin DIP (DIP40-P-600)
44-pln QFP (QFP44-P-I0I0A)

LH5081 M/LH5081AM
LH5081LM/LH5081ALM
-I
~

rJJ

l~ Ifj C; 0 Q ~ Q Q Q I~ I~

Note: The Z80 CMOS CPU (LH5081) is compatible with the Z80
NMOS PIa (LH0081). So there is no description here about
the pins, programming, and basic timings waveforms. Refer
back to the Z80 NMOS PIO described earlier.
Top View

274

280 CMOS PIO Parallel I/O Controller

•

LH5081

Block Diagram

Internal
Control Logic
Port A
Input/
Output

System
Data
Bus

Port A/B Select
Command/Data
Select
Chip Enable
Machine Cycle 1
I/O Request
Read

Port A
Data Bus

CPU
Bus
Input/
Output
Logic

6

5

4
3
36
35

Port B
Input/
Output

Port B
Data Bus

Interrupt
Control Logic

>
""'
+
u

~

:>
<:>
Q

z

"

....
TsPD (STB). '
5 : Increase these values by 2 ns for each 10 pF increase in loading up to 100 pF max.
6 : TsCS (RI) may be reduced, However, the time substracted from TsCS (RI) will be added to TdRI (DO).
7: 2.5 TcC > (N-2) TdlEI (IEOf)+TdMl (lEO) + TslEI (IO)+TTL Buffer Delay, if any.
8 : M1 must be active for a minimum of two clock cycles to reset the PIO.

277

LH5D81

Z8D CMOS PIO Parallel I/O Controller

AC Test Conditions:
•
Input voltage amplitude: 004 V to 2.BV
•
Clock input voltage amplitude: OAV to Vcc-0.6V
•
Input signal rise and fall time : IOns
•
Input judge level: O.BV and 2~OV
•
Output judge level: O.BV and 2.0V
•
Output load: ITTL+ 100pF (unless otherwise specified)

•

Power Save and Status Information
Read Function

Unlike the LHOOBlILH50Bl, the LH50BIL
series has the power save (PS) and status information read functions.
(1) Power save function

(i) PS mode setting
When the CPU
(LH50BOL series) has executed an HALT instruction in the PS mode, the LH50Bl L series
reads this HALT instruction to automatically go
into the PS mode. Now the internal clock signal is
cut off. Therefore, cutting an external clock input
gives no problem inside in this mode.
T,

T3

T,

Data--------~v-----v-----t----------

PS'

- - - - - - - - - -________--'-__--1

PS mode set timing

Power save
state

(ii) PS mode clear
~e PS mode is cleared
by detecting the fall of the Ml signal. When the external clock is off in the PS mode, however, a stable
clock signal must be input before clearing the PS
mode.
When the CPU (LH50BOL series) is cleared
from the PS mode and comes into the next fetch
cycle, therefore, the LH50BIL series is a~ cleared
from its PS mode at the fall of the first Ml signal
in this cycle.
The PS mode clearing can be done by issuing an
interrupt request.
Set up the interrupt generate conditions in Mode
3 of the LH50BIL series. By this, an interrupt
request (INT) is issued even in the PS mode, the
CPU (LH50BOL series) is cleared from the PS mode,
and thus LH50BIL series is also cleared.
(2) Status information read
Under the following conditions, the mode setup
bits and handshake signals of Port A and Port B
are read from the data bus during the read cycle.
See the chart below.
Conditions: CE = "Low",-RD = "Low", IORQ
"Low", CID = "High", BI A = X (undefined)
Bits

7

6

5

4

3

2

1

0

IAMIjA MolARDylASTBI BMII BMO~RDY~STBI
PS'

Return to orig inal state

* PSis internal signal and not output externally.
PS mode clear timing

'--I

~most

~he

two bits of
Uppermost two bits. of the
B port mode control reglstor
Aport mode control registor
(Set mode bits)
(Set mode bits)

LH5081L series status information words

- - - - - - - - - - - - - - - - - S....ARP - - - - - , - - - - - - - - 278

Z80 CMOS CTC Counter Timer Circuit

LH5082
•

zao CMOS CTC Counter Timer Circuit

Description

The LH5082is a Z80 CTC fabricated with
CMOS silicon-gate process technology and is com·
patible with the conventional Z80 NMOS CTC
(LH0082)
The LH5082 is designed with CMOS fully static
circuits and so provides low power consumption
and wide range power supply voltage operation.
The LH5082L1LH5082LM provides power save
mode controlled by software.

•

LH5082

•

Pin Connections
LH5082/LH5082A/LH5082B
LH5082L/LH5082ALlLH5082BL

o

Features

1. Z80 CMOS CTC
2. Compatible with the Z80 NMOS CTC
(LH0082)
3. 4 independent programmable 8-bit counter/
16-bit timer channels
4. Selectable counter/timer mode for each channel
5. Programmable interrupt triggered by counter!
timer
6. Downcounters reloaded automatically at zero
count
7. Readable downcounters
8. Selectable 16 or 256 prescaler (timer mode)
9. Selectable positive or negative triggers for timer
and selectable positive or negative clock edge
forcounter
10. ZC/TO outputs of three channels capable of
driving Darlington transistors
11. Vectored and daisy chain piority interrupt
12. Single + 5V power supply and single phase
clock
13. All inputs and outputs except clock input fully
TTL compatible
14. Fully static operation
(DC to 2.5MHz/4MHz/6MHz)
15. Low power consumption
16. Power save mode (L suffix)
17. 28-pin DIP (DIP28-P-600)
44-pin QFP (QFP44-P-1010A)

LH5082M/LH5082AM
LH5082LM/LH5082ALM
u u

0

Ig 5~ 55 ~
Q

U

1
ZZ~2N<.:JNNO::<.:JZ

Note: The 280 CMOS CTC (LH5082) is compatible with the 280
NMOS CTC (LH0082). So there is no description here about
the pins, programming, and basic timing waveform. Refer
back to the 280 NMOS CTC described earlier.

~""'-"'-~-------SHARP-------'-

279

Z80 CMOS CTC Counter Timer Circuit

•

LH5082

Block Diagram

Zero Count/
Timeout 0
3 Clock/Trigger 0
Internal
Control
Logic

System
Data
Bus

~~ Z... Coo.'/
Timeout 1

Clock/Trigger

CPU Bus
Input/
Output
Logic

Chip Enable 6
I

Zero Count!
Timeout 2

Channel {18
Select
19

Clock/Trigger 2

Machine Cycle 1 .
I/O Request

Interrupt
Logic

0
I

6

lwL
-"

.,., > "13 ....
"" e
Q .-

U

>

Z(FJU

L'l

o Clock/Trigger

3

Q.~c..~~'S

e :e

~

_

E ta> goO
g.lii::C:g ;"'.,c
Io.'~
Q)

+01

~et:..9~!~
..!:i~

* Pin numbers apply to 28-pin DIP only.
•

Ordering Information

LH5082 X X-X

*

Package
Blank: 28-pin DIP (DIP28-P-600)
M: 44-pin QFP (QFP44-P-IOIOA)
Power save mode
Blank: No power save
L: Power save
Clock frequency
Blank: 2.5MHz
A: 4MHz
B: 6MHz
'-----Model No.
[

* The 6MHz type is packaged in 28-pin DIP only.

- - - - - - - . . . . . - . - - - - - - S H A R P - - - - - - - - - - - - - - - - - .........
280

Z8D CMOS CTC Counter Timer Circuit

•

Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature

•

LH5D82

Ratings
Symbol
-0.3 to +7.0
Vee
-0.3 to Vee +0.3
VIN
VOUT -0.3 to Vee +0.3
o to +70
Topr
Tstg
-65 to + 150

Unit
V
V
V

'C
t

(V ee =5V±10%, Ta=O to +70t)

DC Characteristics
Parameter
Clock input low voltage
Clock input high voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage

Symbol
VILe
VIHe
VIL
VLH
VOL
VOH

Current consumption

I Icc I

Input leakage current
3 ·state output leakage current
3·state output leakage current

I ILl I
I ILOH I
I IIOL I

Conditions

IOL =2mA
10 ,,= -250 p A
lou=-50pA

MIN.
-0.3
Vee- 0.6
-0.3
2.2

IOHD

Current consumption in PS
mode

Ieeps

Note
Note
Note
Note

•

1:
2:
3:
4:

MAX.
0.45
Vee+ 0.3
0.8
Vee
0.4

2.4
Vcc OAV

LH5082/L
V1L =O.4V,VJH=Vcc-D.4V,
LH5082A1AL
outputs open

2
3
5

LH5082B/BL

Darlington drive current

TYP.

VIN=OV, Vee
VouT=Vee
VOUT=OV
VoH =1.5V
Applicated to ZC/TO o-ZC/T0 2
LH5082L
VIN=OV, Vee
LH5082AL
Outputs open
LH5082BL

4

6
8
10
10
10

-1.5

Unit
V
V
V
V
V
V
V
mA
mA
mA
pA
pA
pA

Note

1
2
3
4

mA
1
1
1

100
100
100

pA

e-l-~
3

TcC=400ns
TcC=250ns
TcC= 167ns
For I III I specification, see below circuit of CLK/TRG o-CLK/TG 3•

(f=lMHz, Ta=25°C)

Capacitance
Parameter
Clock capacitance
Input capacitance
Output capacitance

Symbol
CeLOeK
CIN
COUT

Conditions
Unmeasured pins returned
to ground

MAX.
5
5
10

Unit
pF
pF
pF

- - -........... -----SHARP~---.-.---281

LH5082

Z80 CMOS CTC Counter Timer Circuit

•

(Vcc=5V±10%,.Ta=0 to +70"C)

AC Characteristics
No.

Parameter

Symbol

1
2
3
4
5
6
7
8
9
10
11
12
13
14

Clock cycle time
Clock high width
Clock low width
Clock fall time
Clock rise time
All hold times
CS to clock t setup time
CE to clock t setup time
!ORQ ~ to clock t setup time
RD ~ clock t setup time
Clock t to data out delay
Clock ~ to data out float dalay
Data In to clock t setup time
MI to clock t setup time
M1 ~ to lEO ~ delay (interrupt
immediately preceding MI)
!ORQ ~ to data out delay
(INT A cycle)
lEI ~ to lEO ~ delay
lEI t to lEO t delay t
(after ED decode)
Clock t to INT ~ delay
CLK/TRG t to INT ~ delay
(tsCTR (C) satisfied)
CLK/TRG t to INT ~ delay
(tsCTR (C) not satisfied)
CLK/TRG cycte time
CLK/TRG rise time
CLK/TRG fall time
CLK/TRG low width
CLK/TRG high width
CLK/TRG t to clock t setup time
for immediate count
CLK/TRG tto clock tsetup time for
enabling of prescaler on following clock t
Clock t to ZC/TO t delay .
Clock t to ZC/TO ~ delay
lEI setup time IORQ ~ (INT A cycle)

TcC
TwCh
TwCl
TIC
TrC
Th
TcCS (C)
TsCE (C)
TsIO (C)
TsRD (C)
TdC (DO)
TdC (DOz)
TsDI (C)
TsMl (C)

15
16
17
18
19

20

21
22
23
24
25
26
27
28
29
30

t

LH5082
MIN. MAX.
400 (Note 1)
170
170
30
30
15
250
200
250
240
240
230
60
210

LH5082A
MIN. MAX.
250 (Note 1)
105
105
30
30
15
160
150
115
115
200
110
50
90

LH5082B
MIN. MAX.
165
65
65
20
20
15
100
100
70
70
130
90
40
70

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

282

2

TdMl (lEO)

300

190

130

ns

3

TdIO (DOl)

340

160

110

ns

2

TdlEI (IEOf)

190

130

100

ns

3

TdlEI (IEOr)

220

160

110

ns

3

TdC (INT)

TeCt200

TeC+l40

TeCt 120

ns

4

TdClk (lNT)

TeCt230

TeCt 160

TeCt 130

ns

5

TdCLK (INT)

2TeCt530

2TeCt370

2TeCt280

ns

5
5

TcCTR
TrCTR
TfCTR
TwCTRl
TwCTRh

2TcC

200
200

200
200

120
120

ns
ns
ns
ns
ns

TsCTR (Cf)

300

210

150

ns

5

TsCTR (Ct)

210

210

150

ns

4

TdC (ZC/TOr)
TdC (ZC/TOf)
TslEI (10)

2TcC
50
50

260
190
140

2TcC
40
40

50
50

140
140

190
190
140

140

ns
ns
ns

Rising edge, l Falling edge
(AI 2.5 TcC>(n-2) TdIEI (IEOf) + TdMI (lEO) +TsIEI (IO)+TTL buffer delay, if any.
(BI RESET must be active for minimum of 3 clock cycles
Notel: TcC=TwCh+TwCI+TrC+TfC.
Note 2 : Increase delay by 10 ns for each 50 pF increase in loading, 200 pF maximum for data lines, and 100 pF for control lines.
Note 3 : Increase delay by 2 ns for each 10 pF increase in loading, 100 pF maximum.
Note 4 : Timer mode.
Note 5 : Counter mode,
All timing are preliminary and subiect to change.

*

Note

Z80 CMOS CTC Counter Timer Circuit

AC Test Conditions

• Input voltage amplitude: 0.4 V to 2.8 V
• Clock input voltage amplitude: 0.4 V to
Vee-0.6V

• Input signal rise and fall time: 10 ns
• Input judge level: 0.8 V and 2.0 V
• Output judg~ level: O.S V and 2.0 V
.Output load: ITTL + 100 pF (unless otherwise specified)

•

Power Save Function

The LH50S2L series has the power save (PS)
functions.
(1) PS mode setting
When the CPU (LH50S0L series) has executed a HALT instruction, the LH50S2L series

reads this HALT instruction to autmatically go into
the PS mode. In this mode, the internal clock
signal is cut off. The external clock may be off during the PS mode.
About the external clock stop, the same is true as
the power-saving CPU (LH50S0L series)

(2) PS mode clear
The PS mode is cleared by the fall of Ml signal
or the RESET signal.
When the external clock is off the PS mode,
however, a stable clock signal must be input before
clearing the PS mode.
Once cleared from the PS mode, the power-saving CPU (LH50S0L series) comes into the next
fetch cycle. At the time when the first Ml signal
during this cycle falls, the LH50S2L series is
also cleared from the PS mode.
CLOCK

CLOCK

RESET~

Ml

PS'

RD

I
Reset state same as LH5082

* PS is an internal signal and not output externally.

Date
PS'

LH5082

_ _ _ _ _ _ _ _ _-Z

PS mode clear by RESET signal

Power save
state

* PS is an internal signal and not output externally.
PS mode

set timing

CLOCK

Ml
PS'

~I
Return to originaistate

* PS is an internal signal and not output externally_
PS mode clear by MI signal

I

~I

283

LH0080

Z80 CPU Central Processing Unit

L H0080
•

Z80 CPU Central Processing Unit

Description

•

The LH0080 280 CPU (280 CPU for short below) is a general-purpose 8-bit microprocessor
fabricated using an N-channel silicon-gate process.
The LH0080A 280A, LH0080B 280B, LH0080E
280E CPU are the high speed version which can
operate at the 4MHz, 6MHz and 8MHz system
clock, respectively.

•

Pin Connections

LH0080/LH0080AlLH0080B/LH0080E
LH0080H/LH0080AH

o

Features
1. 8-bit parallel processing microprocessor

2. N-channel silicon-gate process
3. 158 instructions (The instruction of the 8080A
are included as a subset; 8080A software compatibility is maintained)
4. 22 registers
5. The capability of 3 modes maskable interrupt
and non-maskable interrupt
6. On-chip dynamic memory refresh counter
7. Instruction fetch cycle: 1.6,us(280), l.O,,us
(280A), 0.67 ,us (280B), 0.5,us (280E)
8. Single + 5 V power supply and single phase
clock
9. All inputs and outputs fully TTL compatible,
10. 40-pin DIP (DIP40-P-600)
44-pin QFP (QFP44-P-1010A)
44-pin QFJ (QFJ44-P-'S650)

LH0080U/LH0080AU/LH0080BU

LH0080M/LH0080AM

b

z~~~

....

HALT
MREQ

36

WAIT

42

BUSRQ

43

~

t5"l\'~-"'~....1

00~O~>

....

O~OU

37

29

BUSRQ

Top View

*The GND pins must be connected to the GND leveL
-~--------SHARP-'-----------'-

284

Z80 CPU Central Processing Unit

•

Ordering Information
Product
Clock frequency
Model No.

*

•

LH0080

280 CPU
2.5MHz
LH0080
LH0080H*
LH0080M
LH0080U

280A CPU
4MHz
LH0080A
LH0080AH*
LH0080AM
LH0080AU

280B CPU
6MHz
LH0080B

280E CPU
8M Hz
LH0080E

Package
40-pin DIP
44-pin QFP
44-pin QFJ

LH0080BU

Operating
temperature
O·C to +70·C
-20'C to +85'C
O'C to +60·C
O'C to +70'C

H suffix is a wide temperature spec, packaged in 40-pin DIP.

Block Diagram
System Data Bus

Halt State
M emory Request
Input/Output Request
Read
Write
Bus Acknowledge
Machine Cycle 1
Refresh

Data Bus Interface
"0

!::

c
o
U

..

[.:
Interrupt Request
Non- Maskable Interrupt
Wait
Bus Request
Reset

Instructionl.-L_ _ _----'

c

·S

Decoder

Register

ALU

~

0U

Register Array

Address Bus Interface

Vee GND System

(+5V) (OV)

Clock

System Address Bus

Pin numbers apply to 40-pin DIP.

285

Z80CPU Central Processing Unit

•

L.:.H0080

Pin Description
Signal
Ao-A15

Pin name
Address bus

Do-D-i

Data bus

-

Ml

--

Machine cycle one

110
3-state 0
,Bidirectional
3-state
0

MREQ

Memory request

3-state 0

IORQ

110 request

3-state 0

Memory read

3-state 0

Memory write

3-state 0

-'

RD
-

WR

--

Refresh

0

Halt state

0

Wait

I

--

Maskable interrupt
request

I

--

Non-maskable
interrupt request

I

RESET

Reset

I

BUSRQ

Bus request

I

Bus acknowledge

0

System clock

I

RFSH

-HALT

--

WAIT

INT

NMI

---

--BUSAK

, CLOCK

Function
System address bus
System data bus
Active "Low". Indicates that the current machine cyde
'is the OP code fetch cycle of an instruction execution.
Active "Low". Indicates that the address bus holds a
valid address for a memory read or memory write operation.
Active "Low". Indicates that the lower 8 bits of the
address bus holds a valid liD address for an liD read
or write operation. Also generated concurrently with
Mlduring an interrupt acknowledge cycle to indicate an
interrupt response.
Active "Low". Indicates that the CPU want~ to read data
from memory or an liD device.
Active "Low". Indicates that the CPU data bus holds
valid data to be stored at the addressed memory or 110
location.
Active "Low". Indkates that the lower 7 bits of the system address bus can be used as a refresh address 'to the
system·s dynamic memories. Together with MREQ at
"Low".
Active "Low". Indicates that a Halt instruction is being
executed. While halted, the CPU executes NOPs to maintain memory refresh. The Halt state is cleared with RE-- -- -SET, NMI, or INT (when allowed).
Active "Low". Indicates to the CPU that the address~d
memory or 110 devices are not ready for a data transfer.
The CPU continues to enter a wait state as long as this
signal is active.
Active "Low". Generated by liD devices. The CPU honors a request at the end of the current instructioJl if the
interrupt enable flip-flop is enabled.
Active "Low". Has a higher priority than INT. Always
recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop.
Automatically forces the, 280 CPU to restart at location
0066H.
Active "Low". Resets the interrupt enable flip-flop, the
program counter interrupt vector register and the memory refresh register, and sets the interrupt status to
Mode 0, in order to initialize the CPU.
Active "Low". Has a higher priority than NMI. Always
recognized at the end of the current machine cycle. Actjvated to allow a bus master other than the CPU to control the system bus.
Active "Low". Indicates to the requesting device that the
externill circuitry can control the system bus.
Inputs + 5V single-phase clock.

I

286

280 CPU Central Processing Unit

•

LH0080

Absolute Maximum Ratings
Parameter
Input voltage
Output voltage

Symbol
V IN
VOUT

Operating temperature

Topr

Storage temperature

Tstg

Note 1:
Note 2:
Note 3:

Ratings
-0.3 to +7.0
-0.3 to +7.0
o to +70
o to +60
-20 to +85
-65 to +150

Unit
V
V

"C

Note

1
2
3

·C

40-pin DIP and 44-pin QFJ
44-pin QFP
40-pin DIP with wide temperature spec.

Standard Test Conditions

All ac parameters assume a load capacitance of
100 pF. Add 10 ns delay for each 50 pF increase
in load up to a maximum of 200 pF for the data
bus and 100 pF for address and control lines.

The characteristics below apply for the following standard test conditions, unless otherwise
noted. All voltages are referenced to GND (OV).
Positive current flows into the referenced pin.

•

Parameter
Clock input low voltage
Clock input high voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage

Symbol
VILC
V IHC
V1L
VIH
VOL
VOH

Current consumption

Icc

Input leakage current
3-state output leakage
current in float

I ILl I

Note 1:

•

(Vcc=5V±5%, Ta=O to +70'C Note 1)

DC Characteristics

I ILEAK I

Conditions

MIN.
-0.3
Vcc- 0.6
-0.3
2.0

IOL =1.8mA
IOH = -250 pA

TYP.

MAX.
0.45
Vcc+ 0.3
0.8

150
200
200
200
10

Unit
V
V
V
V
V
V
rnA
rnA
rnA
rnA
pA

10

pA

Vcc
0.4

2.4
LH0080
LH0080A
LH0080B
LH0080E

O~VIN~VCC

VOUT =O.4V to Vcc

Ta=O to +60't for 44-pin QFP
Ta= -20 to +85't for 40-pin DIP with wide temperature spec.

(f=IMHz, Ta=25'C)

Capacitance
Parameter
Clock capacitance
Input capacitance
Output capacitance

Symbol
CCLOCK
CIN
COUT

Conditions
Unmeasured pins returned
to ground

MIN.

TYP.

MAX.
35
5
10

Unit
pF
pF
pF

-.---------SHARP-...--.---~~--..-.

287

Z80 CPU Central Processing Unit

LH0080

(Vcc=5V±5%, Ta=O to +70"C Note

AC Characteristics

•

LHOOSO
LHOOSOB
LHOOSOE"
LHOOSOA
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
165 ,.
125 *
250"
1
Clock cycle time
400"
TcC
65*
55*
1l0*
lS0*
2
Clock pulse width (High)
TwCh
TwCl
ISO 2000
110 2000
65 2000
55 2000
3
Clock pulse width (Low)
4
Clock fall time
20
10
TfC
30
30
20
Clock rise time
TrC
30
10
30
5
TdCr (A)
145
110
90
SO
6
Clock t to address valid delay
20*
65*
35*
Addreess valid to MREQ ~ delay TdA (MREQf) 125 *
7
70
60
TdCf (MREQf)
Clock ~ MREQ ~ delay
100
S5
S
70
TdCr (MREQr)
9
Clock t to MREQ t.delay
100
S5
60
45*
170*
1l0*
65*
10 MREQpuise width (High)
TwMREQh
220*
135 *
100*
360*
II MREQ pulse width (Low)
TwMREQI
TdCf (MREQr)
70
100
S5
60
12 Clock ~ to MREQ t delay
TdCf (RDf)
SO
70
13 Clock ~ to RD ~ delay
130
95
14 Clock t to RD t delay
TdCr (RDr)
100
70
60
S5
35
30
30
15 Data setup time to clock t
TsD (Cr)
50
ThD (RDr)
0
16 Data hold time from RD t
0
0
0
70
60
17 WAIT setup time to clock ~
TsWAIT (Ct)
50
70
ThWAIT (Cf)
0
IS WAIT hold time after clock ~
0
0
0
70
TdCr. (Mlf)
19 Clock t to M1 ~ delay
130
100
SO
20 Clock t to MIt delay
SO
70
TdCr (Mlr)
100
130
21 Clock t to RFSH ~ delay
TdCr (RFSHf)
ISO
130
110
95
. 100
22 Clock t toRFSH t delay
TdCr (RFSHr)
150
120
S5
TdCf (RDr)
70
60
110
S5
23 . Clock ~ to RD t delay
24 Clock t to RD ~ delay
TdCr (RDf)
100
70
60
S5
Data Setup to clock t during
25
40
30
TsD (Cf)
60
50
M2 , M3, M. or Ms cycles
75 *
1l0*
320*
26 Address stable prior to IORQ ~
TdA (IORQf)
~SO*
TdCr (lORQf)
27 Clock t IORQ ~ delay
75
65
55
90
70
60
2S Clock ~ to IORQ t delay
TdCf (IORQr)
110
S5
5*
25*
190*
SO*
29 Data stable prior to WR ~
TdDm (WRf)
30 Clock ~ WR l delay
TdCf (WRf)
SO
70
60
90
100*
360*
220*
135 *
31 WRpulse width
TwWR
32 Clock ~ to WR t delay
70
60
TdCr (WRr)
100
SO
-10*
-55*
-55*
20*
TdDi (WRf)
33 Data stable prior to WR l
34 Clock t to WR l delay
TdCr (WRt)
60
55
SO
65
15*
30*
120*
60*
TdWRr (D)
35 Data stable from WR t
36 Clock l to HALT t or l
TdCf (HALT)
300
260
225
300
SO
37 NMI pulse width
TwNMI
70
SO
SO
50
3S BUSREQ setup time to clock t
TsBUSRQ (Cr)
40
SO
50
0
39 BUSREQ hold time after clock t ThBUSRQ (Cr)
0
0
0
40 Clock t to BUSACK ~ delay
TdCr (BUSAKf)
120
100
90
SO
41 Clock ~ to BUSACK t delay
90
SO
TdCf (BUSAKr)
110
100
42 Clock t to data float delay
80
70
TdCr (Dz)
90
90
Clock t to control output float
----43
70
60
TdCr (CTz)
110
80
delay (MREQ, IORQ, RD, and WR)
44 Clock t to address float delay
70
TdCr (Az)
110
90
80
MREQ t , IORQ t , RD and WR t
20*
SO*
35*
45
160*
TdCTr (A)
to address hold time

No.

Parameter

Symbol

t Rising edge, ~ Falling edge
Note 1: Ta=O to +60°C for 44·pin QFP.
Ta= -20 to +85"(; for 40·pin DIP with wide temperature spec.

288

")

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Z80 CPU Central Processing Unit

No.
46
47
48
49
50
51
52
53

Parameter
RESET ~ to clock t setup time
RESET from clock! t hold time
INT to clock t setup time
INT from clock t hold time
M1 ~ to IORQ ~ delay
Clockk ~ to IORQ ~ delay
Clock t to IORQ t delay
Clock ~ to data valid delay

LH0080

LH0080
MIN. MAX.
TsRESET (Cr)
90
ThRESET (Cr)
0
TsINTf (Cr)
80
ThINTr (Cr)
0
TdMlf (IORQf) 920*
TdCf (IORQf)
110
TdCf (I0RQr)
100
TdCf (D)
230
Symbol

All ac parameters assume a load capacitance of 100 pF. Add 10
P s delay for each 50 pF increase in load up to a maximum of 200
pF for the data bus and 100 pF for address and control lines.
* For clock periods other than the minimums shown in the table,
calculate parameters using the following expressions.

LH0080A
MIN. MAX.
60
0
80
0
565*
85
85
150

LH0080B
MIN. MAX.
60
0
70
0
365*
70
70
130

LH0080E*
MIN. MAX.
45
0
55
0
270*
60
60
115

1t:i
r

Unit
ns
ns
ns
ns
ns
ns
ns
ns

+ 5V

Output pin

2.1kO

t

100PF

250,uA

,

•

,/

'II

Footnotes to AC Characteristics

No.
Symbol
LH0080
1
TcC
TwCh+TwCl+TrC+TfC
2
TwCh
MAX. 200 f1S
7 TdA (MREQf) TwCh+TfC-75
10 TwMREQh TwCh+TfC-30
11 TwMREQl TcC-40
26 TdA (IORQf) TcC-80
29 TdD (WRf) TcC-210
TcC-40
31
TwWR
33 TdD (WRf) TwCI +TrC-180
35 TdWRr (D) TwCI+TrC-80
45
TdCTr (M TwCI+TrC-40
50 TdMIf (IORQ!) 2Tch+TwCh+TfC-80

AC Test Conditions:
VIHC=Vcc-O.6V
VIH=2.0V
VIL=O.8V
VILc=0.45V

LH0080A
TwCh + TwCI + TrC + TfC
MAX. 200 f1S
TwCh+TfC-65
TwCh+TfC-20
TcC-30
TcC-70
TcC-170
TcC-30
TwCI+TrC-140
TwCI+TrC-70
TwCI+TrC-50
2TcC+TwCh+TfC-65

VOH=2.0V
VOL=O.8V

LH0080B
TwCh + TwCI + TrC + TfC
MAX. 200 f1S
TwCh+TfC-50
TwCh+TfC-20
TcC-30
TcC-55
TcC-140

LH0080E
TwCh+TwCl+TrC+TfC
MAX. 200 f1s
TwCh+TfC 45
TwCh+TfC 20
TcC-25
TcC-50
TcC-120
TcC~30
TcC-25
TwCI+TrC-120
TwCI +TrC-140
TwCI+TrC-50
TwCI+TrC-55
TwCI+TtC-50
TwCI+TrC 45
2TcC+TwCh+TfC-50 2TcC+TwCh+TfC-45

FLOAT = ±O.5

289

Z80 CPU Central Processing Unit

•

LH0080

CPU Timing

(1)

The 280 CPU executes instructions by proceeding through a specific sequence of operations:
•
Memory read or write
• 110 device read ~r write
•
Interrupt acknowledge
The basic clock period is referred to as a T time
or cycle, and three or more T cycles make up a
machine cycle (MI, M2 or M3 for instance).
Machine cycles can be extended either by the CPU
automatically inserting one or more Wait states or
by the insertion of one or more Wait states by the
user.

Instruction Opcode Fetch

The CPU places the contents of the Program
Counter (PC) on the address bus at the start of the
cycle (Fig. 1). Approximately one-hal~ock cycle
later, MREQ goes active. When active, RD indicates
that the memory data can be enabled onto the CPU
data bus.
The CPU samples the WAIT input with the faIling edge of clock state T,. During clock states T3
and T. of an MI cycle dynamic RAM refresh can
occur while the CPU starts decoding and executing
the instruction. When the Refresh Control signal
becomes active, refreshing of dynamic memory can
take place.

CLOCK

Do-D7

Note: Tw-Wait cycle added when necessary for slow ancilliary devices_

Fig. 1

(2)

Instruction opcode fetch

Memory Read or Write Cycles

Fig. 2 shows the timing of memo!:L!ead or write
cycles other than~ opcode fetch (MI) cycle.
The MREQ and RD signals function exactly as in
the fetch cycle. In a memory write cycle, MREQ
also becomes active when the address bus is stable.
The WR line is active when the data bus is stable,
so that it can be used directly as an R/W pulse to
most semiconductor memories.

290

(3)

Input or Output Cycles

Fig. 3 shows the timing for an 110 read or I/O
write operation.
During 110 operations, the CPU automatically inserts a single wait state (T w). This extra wait state
allows sufficient time for an 110 port to decode the
address from the port address lines.

LH0080

Z80 CPU Central Processing Unit

CLOCK

RD
Read operation

{

@

i

,

J

,

Do-D7

1

(

(

WR

~~-®!---r.::·~-D--at-a-o-ut------------~~----

Write operation

Do-D7

-------------~

Fig. 2

Memory read or write cycles

-.-----------------SHARP - - . - , - - - - - - - - - 291

LH0080

Z80 CPU Central Processing Unit

CLOCK

IORQ

RD

I/O read operation.{

Do-D7
WR

I/O write operation{

Do-D7

Note: Tw =One wait cycle automatically inserted by CPU.

Fig. 3

(4)

Input or output

Interrupt request/acknowledge cycle

The CPU samples the interrupt signal with the
rising edge of the last clock at the end of any in·
struction (Fig. 4). When an interrupt is accepted, a
special Ml cycle is generated. During this Ml cy-

cle, IORQ becomes active (instead of MREQ) to indio
cate that the interrupting device can place an 8-bit
vector on the data bus. The CPU automatically
adds two wait states to this cycle.

CLOCK

INT

Ml
IORQ

Notel: TL= Last state of previous instruction.
Note 2: Two wait cycles automatically inserted by CPU (*).

Fig. 4

-

292

Interrupt request/acknowledge cycle

......... . - - - . . - - . - - - S H A R p · . - . - - - - . - . - - - - - - - -

LH0080

Z80 CPU Central Processing Unit

(5)

Non-maskable interrupt request cycle

NMI is sampled at the same time as the maskable
interrupt INT but has higher priority and cannot be
disabled under software control.
The subsequent timing is similar to that of a nor·
-

Last Mcycle

mal instruction fetch except that data put on the
bus by the memory is ignored. The CPU instead ex·
ecutes a restart (RST) operation and jumps to the
NMI service routine located at address 0066H
(Fig. 5).

- - - - - ; ; . ¥ - - - - - - - - - - M 1----------~
Last T time TI
T,
T3
T4
T5

CLOCK

NMI

Ml

MREQ
RD

RFSH
'Although NMI is an asynchronous input, to guarantee its being
recognized on the following machine cycle, NMI's falling edge
must occur no later than rising edge of the clock cycle preceding

T LAST •

Fig. 5

(6)

Non-maskable interrupt request operation

Bus request/acknowledge cycle

The CPU samples BUSREQ with the rising edge
of the last clock period of any machine cycle (Fig.
6). If BUSREQ is active, t~CPU sets its address,
data, and MREQ, IORQ, RD, and WRlines to a
high-impedance state with the rising edge of the
next clock pulse. At that time, any external device
can take control of these lines, usually to transfer
data between memory and I/O devices.

(7)

Reset cycle

RESET must be active for at least three clock cy·
cles for the CPU to properly accept it. As long as
RESET remains active, the address and data buses
float, and the control outputs are inactive. Once
RESET goes inactive, three internal T cycles are
consumed before the CPU resumes normal proces·
sing operation. RESET clears the PC register, so
the first opcode fetch will be location 0000 (Fig. 8).

-----~~---,---SHARP-.--------

293

LH0080

Z80CPU Central Processing Unit

Tx

Tx

Tx

CLOCK

------~~{~-Float---l~@E=
Float

MREQ
RD,WR
IORQ

Float

Ml

Unchanged
Note:

state of any M cycle.
arbitrary clock cycle used by requesting device.

TL~Last

Tx~An

Fig. 6

Z-bus request/acknowledge cycle

M l---~:;.*IEo--------_-'--M 1

I

:> E'

M1

::::K
r----1"=._®

HAL T instruction received

.

NMI

~----~--------------------

Note: INT will also force a Haltexit.

Fig. 7 Halt acknowledge cycle

- - - - - - - . - - r - - - - - S H A R P - . - . ......... ~---294

Z80 CPU Central Processing Unit

LH0080

CLOCK

RESET

Ml

--------------------~r_~f-~----------------~~

----------------~I

MREQ. ------------~~rrrr----~J;~c--------------------T--------

II//Vl

RD. WR.

IORQ. RFSH.
BUSAK.
HALT

Fig. 8

\,-__

Reset cycle

T2

T3

CLOCK
Ml

RESET

Fig.9

..J/

\ ' -_ _ _ _ _

~'------------

Timing diagram when M1 cycle has no wait state

295

LH0080

Z80 CPU Central Processing Unit

(Reference>

The RAM contents may be adversely affected by
resetting the CPU while it is in operation.
To prevent this, a RESET signal should be input
in the following timings.
(1) No walt state.in the MI cycle
Input a RESET signal to start sampling this signal at the clock rising in the MI cycle's T2 state.
(See Fig. 9.)

A walt state in the MI cycle
Input a RESET signal to start sampling this signal at the clock rising in the Ml cycle's T3 state.
(See Fig. 10.)

(2)

CLOCK
Ml

MREQ

~~

____________~J
\.....______--'J
\....._---'J

RESET

,'--------

Fig. 10 Reset circuit and timing diagram when
M1 cycle has a wait state
L -____________________________________________________________________________

296

~

LH0080

Z80 CPU Central Processing Unit

•

CPU Registers
A Accumulator
B General Purpose
D General Purpose
H General Purpose

F Flag Register
C General Purpose
E General Purpose
L General Purpose

+----8 bits-----.
I Interrupt Vector
I
IX
Index Register
IY
Index Register
Stack pointer
SP
Program Counter
PC
,
1 6 bits

A' Accumulator
B' General Purpose
D' General Purpose
H' General Purpose

R Memory Refresh

.

/

•

F' Flag Register
C' General Purpose
E' General Purpose
L' General Purpose

Architecture
(1)

CPU Registers
(i) Program Counter (PC)
The program
counter holds the 16 bits memory address of a current instruction. The CPU fetches the contents
from memory address specified by the PC.
The PC feeds the data to the address line, automatically setting the PC value to. + 1. When a program jump takes place, a new value is directly set to
the Pc.
(ii) Stack Pointer (SP)
The stack pointer
holds the top 16-bit address of the stack with an
external RAM. An external file is based on LIFO
(Last-In, First-Out).
The data are transferred between a CPU -specified register and the stack by a PUSH or POP instruction. The last-pushed data are first popped
from the stack.
(iii) Index Register (IX & IY)
For index
mode addressing, there are independent index registers IX and IY, each of which holds 16-bit reference address.
In the index mode, the index registers are used to
designate the memory area for data input! output.
With an INDEX ADDRESSING instruction, an
effective address comes by adding a one-byte displacement to the register content. This displacement is an integral signed two's complement number
(iv) Interrupt Register (I)
The 280 CPU has
indirect subroutine call mode for any memory area
according to an interrupt. For this purpose, this
register stores the upper 8 bits of memory address
for vectored interrupt processing and the lower 8
bits for the interrupting device.

The built-in re(v) Refresh Register (R)
fresh register provides user-transparent dynamic
memory refresh. Its lower 7 bits are automatically
incremented during each instruction fetch cycle.
While the CPU records a fetched instruction and
executes the instruction, the refresh register data
are placed on the address bus by a REFRESH control signal.
(vi) Accumulator and Flag Register (A & F)
The CPU has also two independent 8-bit accumulators in combination with two 8-bit flag registers.
The accumulators store an operand or the results of an 8-bit operation. The flag registers, on
the other hand, deal with the results of an 8-bit or
16-bit operation; for example, seeing if the result
is equal to 0 or not.
(vii) General-Purpose Registers
There are
several pairs of general-purpose registers. In each
pair, they can be used separately or as a 16-bit
paired register. The paired registers are BC, DE,
HL, as well as BC' DE' HL'. Either of these sets can
work by an "Exchange" instruction at any time on
a program.

(2)

Arithmetic/Logical Unit (ALU)

An 8-bit arithmetic/logical operation instruction
is executed by the ALU inside the CPU. The ALU
connects to each register through the internal bus
for data transfer between them.

(3)

Instruction Register, CPU Control

Each instruction-is read out of the memory, held
in the instruction register, and decoded. The con-

297

LH0080

Z80 CPU Central Processing Unit

trol unit controls this action and gives control signals necessary to read and write data from and to
the registers_
The control unit also makes ALU control signal
and other external control signals_
 The 280 CPU
--accepts two interrupt input signals: NMI and INT_
The NMI is a non-maskable interrupt and has the
highest priority_ .!NT is a lower priority interrupt
and it requires that interrupts be enabled in software in order to operate_

(1)

vice places an instruction on the data bus_ This is a
Restart instruction or a Call instruction.
(ii) Mode 1 Interrupt Operation.
Mode 1
operation is very similar to that for the NMI. The
principal difference is that the Mode 1 interrupt
has a restart location of 0038H only.
(iii) Mode 2 Interrupt Operation.
This interrupt mode has been designed to utilize most
effectively the capabilities of the 280 microprocessor and its associated peripheral family. The
interrupting peripheral device selects the starting
address (16 bits) of the interrupt service routine. It
does this by placing an 8-bit vector on the data
bus during the interrupt acknowledge cycle. The
CPU forms a pointer using this byte as the lower
8-bits and the contents of the I register as the upper 8-bits. This points to an entry in a table of
addresses for interrupt service routines. The CPU
then jumps to the routine at that address.
All the 280 peripheral devices have the interrupt priority circuit with a daisy-chain configuration. During an interrupt acknowledge cycle, vectors are automatically fed. For more details, refer
to the 280 PIO description.

Non-Maskable Interrupt (NMi)

The non-maskable interrupt will be accepted at
all times by the CPU_ .
After recognition of the NMI signal, the CPU
jumps to restart location 0066R
(2) Maskable Interrupt (lNT)
The maskable interrupt, INT, has three programmable response modes available_
(i) Mode 0 Interrupt Operation.
This
mode is similar to the 8080A microprocessor interrupt service procedures_ The interrupting de-

Table

Lower byte
Upper byte

1

~pointe; bits

1

7 bits

I~

'-----From application device
I register contents

L -_ _ _ _ _

To the beg inning of service rotine

Fig. 1

Mode 2 interrupt diagram

- . - .......... . - - - - - . - , S H A R P - - - - - - . . - . . . . - - -

298

Z80 CPU Central Processing Unit

•

LH0080

Instruction Set
Table 1 8-bit load group
Mnemonic
,
LD r, r
LD r, n

Symbolic
operation
,
r-r
r-n

LD r, (HL)
LD r, (IX+d)

r-(HL)
r_ (IX+d)

LD r, (IY+d)

r- (IY+d)

LD (HL), r
LD (IX+d), r

(HL)-r
(IX+d)-r

LD (IY+d), r

(IY+d)-r

LD (HL), n

(HL)-n

LD (IX+d), n

(IX+d)-n

OP code
HEX code
76 543 210 (Basic) C
,
r
01
40+
r
00 r 110 06+
n --.
01 r 110 46+
DD
11 011 101
01 r 110 46+
d --.
11 111 101
FD
01 r 110 46
d --.
01 110 r
70+
11 011 101
DD
01 110 r
70+
d --.
11 111 101
FD
01 110 r 70+
d --.
00 110 110
36
n --.
11 011 101
DD
00 110 110
36

-

-

-+-

LD (IY+d), n

LD A, (BC)
LD A,(DE)
LD A, (nn)

LD (BC), A
LD (DE), A
LD (nn), A

(IY+d)_n

A - (BC)
A-(DE)
A-(nn)

(BC) - A
(DE)-A
(nn) - A

LD A, I

A-I

LDA,R

A-R

LD I, A

I-A

LDR,A

R-A

Notes
Flags

•
•
•
•

11
00

00
00
00

-00
00
00

-.11
01
11
01
11
01
11
01

Z

Flags
S

P/V

N

H

• • •
• ••
•••
•••

•
•
•
•

•••••

•
•
•
•

No. of No. of No. of
Bytes MCycles T States
1
1
4
2
2
7
1
3

2
5

7
19

•

3

5

19

• •• • ••
• • •• • •

1
3

2
5

7
19

• •• •• •

3

5

19

2

3

10

4

5

19

4

5

19

1
1
3

2
2
4

7
7
13

1
1
3

2
2
4

7
7
13

0

2

2

9

•0 0
••••••
••••••

2

2

9

2

2

9

2

2

9

• • •• • • •
• • ••• •

d

-+

n
111
110
d
n
001
011
111
n
n
000
010
110
n
n
101
010
101
011
101
000
101
001

--.
101
110

FD
36

--.
--.
010
010
010

OA
1A
3A

--.

--.
010
010
010

02
12
32

--.

••••••

'.

•••••
• • ••••
• • • •• •
• • • •• •
•• ••••
••••••

Comments

r,r
000
001
010
011
100
101
111

Reg.
B
C
D
E
H
L
A

-

--.
101
111
101
111
101
111
101
Ill.

ED
57
ED
5F
ED
47
ED
4F

•
•

t IFF t
t IFF

0

r, r' means any of the registers A, B, C, D, E, H, L, IFF the content of the interrupt enable flip-flop, (IFF) is copied into the P/V flag.
C (carry), Z (zero), S (sign), P/V (parity/overflow), H (half carry), N (add/substract).
.
• =unchanged, 0 = reset, 1 = set, X= undefined.
'
S set or reset according to the result of the operation.

299

LH0080

Z80 CPU Central Processing Unit

Table 2

LD dd, nn

Symbolic
operation
ct'd +- nn

LD IX, nn

IX +- nn

LD IY, nn

IY +- nn

LD HL, (nn)

H+-(nn+l)
L +- (nn)

LD dd, (nn)

ddH .... (nn+ 1)
ddL +- (nn)

LDIX, (nn)

IXH .... (no+1)
IXL +- (nn)

LD IY, (nn)

IYH .... (nn+1)
IYL +- (nn)

LD (nn), HL

(nn+ 1) +- H
(nn) +- L

LD (nn), dd

(nn+ 1) .... ddH
(nn) +- ddL

LD (nn), IX

(nn+ l) .... IXH
(nn) +- IXL

LD (nn), IY

(nn+ l) .... IYH
(nn) +- IYL

LD SP, HL
LD SP, IX

SP +- HL
SP +- IX

LD SP, IY

SP +- IY

PUSH qq

(SP-2) .... qqL
(SP-1) ....qqH
(SP-2) .... IXL
(SP-1) .... IXH
(SP-2) .... IYL
(SP-1) .... IYH
qqH .... (SP+1)
qqL +- (SP)
IXH ....(SP+1)
IXL +- (SP)
IYH .... (SP+1)
IYL +- (SF)

Mnemonic

PUSH IX
PUSHIY
POP qq
POP IX
POPIY
Notes:
Flags:

300

16-bit load group

OP code
HEX code
76 543 210 (Basic) C
00 ddO 001
01+
+- n -+
+- n -+
11 011 101
DD
00 100 001
21
+- n -+
+- n -+
11 III 101
FD
00 100 001
21
+- n -+
+- n -+
2A
00 101 010
+- n -+
+- n -+
ED
11 101 101
01 dd1 011
4B+
+- n -+
+- n -+
11 011 101
DD
00 101 010
2A
+- n -+
+- n -+
11 III 101
FD
00 101 010
2A
+- n -+
00 100 010
22
+- n -+
+- n -+
11 101 101
ED
01 ddO 011
43+
+- n -+
+- n -+
11 011 101
DD
00 100 010
22
+- n -+
.- n -+
11 III 101
FD
00 100 010
22
+- n -+
+- n -+
11 III 001
F9
11 011 101
DD
11 111 001
F9
11 III 101
FD
11 111 001
F9
11 qqO 101
C5+

Z

Flags
S

P/V

N

H

• • • • • •
• • • • • •

4

4

14

4

4

14

3

5

16

4

6

20

4

6

20

4

6

20

3

5

16

4

6

20

• • • • • •

4

6

20

••• •••

4

6

20

1
2

1
2

10

2

2

10

1

3

11

2

4

15

2

4

15

1

3

10

2

4

14

2

4

14

•• • • • •

•• ••••
• • • •••
• • • • • ••
•• • • • •
• • ••••
• • • • • •

11
11
11
11
11

011
100
111
100
qqO

101
101
101
101
001

11
11
11
11

011 101
100001
111 101
100 001

DD
E5
FD
E5
C1+
DD
El
FD
El

No. of No. of No. of
Bytes M Cycles T States
10
3
3

• • •
• • •
•••
• • •
• • •
• • •
• • •
• • •
• • •

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•

Comments

dd
00
01
10
11

nn : 2·byte number.
Lower byte just
after opcode.
Upper byte comes
next.

6

qq
00
01
10
11

dd is any of the register pairs BC, DE, HL, SP.
qq is any of the register pairs AF, BC, DE, HL.
(PAIR)H, (PAIR)L refer to high order and low order eight bits of the register pair respectively, e.g., BCL=C; AFH=A.
• =unchanged, o= reset, l=set, X=undefined, =set or reset according to the result of the operation

t

Reg.
BC
DE
HL
SP

Reg.
BC
DE
HL
AF

l80 CPU Central Processing Unit

Table 3
Mnemonic
EX DE, HL
EX AF, AF'
EXX

EX (SP), HL
EX (SP), IX
EX (SP), IY
LDI

LDIR

LDD

LDDR

CPI

CPIR

CPD

CPDR

Symbolic
operation
DE- HL
AF-AF'

(r~), f::)

DE-DE'
HL
HL'
H-(SP+1)
L-(SP)
IXH - (SP+1)
IXL - (SP)
IYH - (SP+l)
IYL - (SP)
(DE) - (HL)
DE +- DE+l
HL-HL+1
BC - BC-1
(DE) - (HL)
DE +- DE+l
HL - HL+1
BC-BC-1
If BC=O end
(DE) - (HL)
DE +- DE-1
HL - HL-1
BC-BC-1
(DE) - (HL)
DE +- DE-1
HL - HL-1
BC - BC-1
If BC=O end
A- (HL)

LH0080

Exchange, block transfer, block search groups

OP code
HEX code
76 543 210 (Basic) C
EB
11 101 011
00 001 000
08
11 011 001
D9

Z

Flags
S

PlY

N

H

•••• • •
• • • • • •
• • • •• •

11 100 011

E3

11
11
11
11
11
10

101
011
101
011
101
000

DD
E3
FD
E3
ED
AO

11 101 101
10 110 000

ED
BO

11 101 101
10 101 000

ED
A8

11 101 101
10 111 000

ED
B8

11 101 101
HL - HL+1 10 100 001
BC - BC-1
A- (HL)
11 101 101
HL - HL+1 10 110 001
BC - BC-1
If A= (HL) or
BC=O end
A- (HL)
11 101 101
HL - HL-1 10 101 001
BC - BC-1
A- (HL)
11 101 101
HL - HL-1 10 111 001
BC-BC-1
If A= (HL) or
BC=O end

ED
Al

011
100
111
100
101
100

ED
B1

ED
A9
ED
B9

• • • • • •
• • • • • •
• • • • • •
• • CDt • 0 0

No. of No. of No. of
Comments
Bytes MCycles T States
1
1
4
1
4
1
4
Register bank and
1
1
auxiliary register
bank exchange
1
5
19
2

6

23

2

6

23

2

4

16

Load (HL) into (DE),
increment the pointers and decrement
the byte counter (OC)
If Bcfo

••

0

•

0

0

2

5

21

• •

•

0

0

2
2

4
4

16
16

If BC=O

t
CD

••

0

•

0

0

2

5

21

If

•

t

1

t

2
2

4
4

16
16

If BC=O

f

t t t

1

t

2

5

21

If Bcfo and
Af(HL)

2

4

16

If BC=O or
A= (HL)

•

•
•

t

Bcf 0

® CD
® CD

t t t

1

t

2

4

16

1

t

2

5

21

If Bcfo and
Af(HL)

2

4

16

If BC=O or
A= (HL)

® CD

t t t
® CD

Note: (DP/V flag is 0 if the result of BC=O, otherwise P/V=l
@Z flag is 1 if A= (HL), otherwise Z=O
Flags: • = unchanged
o = set, 1 = reset
l = set or reset according to the result of the operation

"I

1

~'-'--~-------SHARP

---------------301

LH0080

Z80 CPU Central Processing Unit

Table 4
Mnemonic
ADD A, r
ADD A, n
ADD A, (HL)
ADD A, (IXtd)

ADD A, (lytd)

ADC A, s
SUB s
SBC A, s
AND s
OR s
XOR s
CP s
INC r
INC (HL)
INC (IX+d)

INC (IY+d)

DEC m

Symbolic
operation
A-A+r

8-bit arithmetic and Logical group

OP code
HEX code
76 543 210 (Basic)
10
r 80+
k
11 k 110 C6+
A~A+n
n
A +- At (HL)
10 k 110
86+
A +- At (lXtd) 11 011 101
DD
10 k 110
86+
d
A+- At (lytd) 11 111 101
FD
10 k 110
86+
d
A+- AtstC
4 types
A-A-s
available
A+- A-s-C
based on
A - Al\s
the above ADD
A-AVs
instruction
A - AEBs
(see Comments)
A-s
00 r
e 00+
r - r+1
(HL) +- (HL)t 1 00 110 i
30+
DD
11 011 101
(IX+d) (IX+d)+l 00 110 i
30+
d
11 111 101
FD
(IY+d) (IY+d)+l 00 110 i
30+
d
m-m-l
4 types
available
based on
the above INC
instruction

-

-

....

H

t t
t t

N
0
0

t t
t t

V
V

t
t

0
0

t
t

1
3

2
5

7
19

t t

V

t

0

t

3

5

19

Z

P/V

t
t

....

....

t t
t t
t t
0 t
0 t
0 t
t t
t
t
t

V
V
V
P
P
P
V
V
V
V

t
t
t
t
t
t
t
t
t
t

0
1
1
0
0
0
1
0
0
0

•

t

V

t

0

•

t

•
•
•

t
t
t
1
0
0

t
t
t
t

1l~1

Ill!!

2
1
3

2
2
5

4*1
7
7
19

1

1
3

1
3
6

4
11
23

3

6

23

Comments
r
000
001
010
011
100
101
111
Mnemonic
ADD
ADC
SUB
SBC
.AND
OR
XOR
CP

....

V

t

1

t
t

1 *2
1
3
3

1*2
3
6
6

Reg.
B
C
D
E
H
L
A
k

000
001
010
011
100
110
101
111

S=r, n, (HL),
(IX +d), (IY +d)

....

Note: V and P mean overflow and parity, respectively.
Flags: • = unchanged
O=reset
l=set
X=undefined
t = set or reset according to the result of the operation

302

No. of No. of No. of
Bytes MCycles T States
4
1
1
2
7
2

Flags
S
V t
V t

C

Mnemonic
INC
DEC

e
100
101

4*.2
m=r,.(HL),
11
(IX+d), (IY+d)
23
23
lIE 1: depends on s.
lIE 2: depends on m.

LH0080

Z80 CPU Central Processing Unit

Table 5

General purpose arithmetic and CPU control groups

CPL

HEX code
Symbolic
OP code
operation
76 543 210 (Basic) C
Decimal
00 100 111
27
t
adjustment
(add/subtract)
A-A
00 101 111
2F

NEG

A- O-A

CCF
SCF
NOP
HALT
DI
EI
1M 0

C-C
C-1
No operation
CPU halted
IFF - 0
IFF - 1
Set interrupt
mode 0
Set interrupt
mode 1
Set interrupt
mode 2

Mnemonic
DAA

1M 1
1M 2

Z

t

Flags
S
P t

PlY

•• • •

11
01
00
00
00
01
11
11
11
01
11
01
11
01

101 101
000 100
111 111
110 III
000 000
110 110
110011
111 011
101 101
000 110
101 101
010 110
101 101
011 110

ED
44
3F
37
00
76
F3
FB
ED
46
ED
56
ED
5E

t

t

V

t

t

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•

1

•
•
•
•
•
•
•

N

•

H

t

No. of No. of No. of
Comments
Bytes M Cycles T States
Decimal adjust
1
1
4
accumulator.

1

1

1

1

4

1

t

2

2

8

0
0

X
0

1
1
1
1
1
1
2

1
1
1
1
1
1
2

4
4
4
4
4
4

8

2

2

8

2

2

8

•
•
•
•
•
•

•
•
•
•
•
•
• •

Complement
accumulator
(one's complement).
Negate acc.
(two's complement).
Complement carry flag.
Set carry flag.

Interrupt not enable
Interrupt enable
Set interrupt mode.

Note : IFF indicates the interrupt enable flip-flop, CY indicates the carry flip-flop.
Flags: e = unchanged, O=reset, 1 =set, X=undefined, =set or reset according to the result of the operation

t

Table 6
Mnemonic
ADD HL, ss
ADC HL, ss
SBC HL, ss
ADD IX, pp
ADD IY, rr
INC ss
INC IX
INC IY
DEC ss
DEC IX
DECIY

16-bit arithmetic group

Symbolic
OP code
HEX code
76 543 210 (Basic) C
operation
09+ t
00 ssl 001
HL - HL
+ss
11 101 101
ED
t
HL - HL
+ss+C
01 ssl 010
4A+
11 101 101
ED
t
HL - HL
-ss-C
42+
01 ssO 010
DD
IX - IX +pp 11 011 101
t
00 pp1 001
09+
IY +-- IY+rr 11 III 101
FD
t
09+
00 rr1 001
03+
ss - ss+ 1 00 ssO 011
DD
IX - IX+1 11 011 101
00 100 011
23
FD
IY - IY+1 11 111 101
00 100 011
23
00 ssl 011
OB+
ss - ss-l
DD
IX - IX-1 11 011 101
00 101 011
2B
FD
IY - IY-1 11 III 101
00 101 011
2B

ss is any of the register pairs BC, DE, HL, SP.
pp is any of the register pairs BC, DE, IX, SP.
rr is any of the register pairs BC, DE, IY, SP.
Flags: e=unchanged, O=reset, 1 = set, X=undefinede,

•
•
•
•
•
•

Flags
S

Z

PlY

t

V

t

•
•
•
•
•
•
•
•

No. of No. of No. of
Bytes M Cycles T States
1
11
3

Comments

N
0

H
X

t

0

X

2

4

15

V

t

1

X

2

4

15

•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•

0

X

2

4

15

0

X

2

4

15

1
2

1
2

6
10

2

2

10

1
2

1
2

6
10

rr
00
01
10

2

2

10

11

• ••

• •
• •
••
• •

• •
• •

ss
00
01
10
11

Reg.
BC
DE
HL
SP

pp
00
01
10

Reg.
BC
DE
IX
SP

11

Reg.
BC
DE
IY
SP

Note:

:1

t =set or reset according to the result iJf the operation

.-.......------------SHARP----------303

Z80CPU Central Processing Unit

LH0080

Table 7
Mnemonic

Symbolic
operation

Rotate and shift groups

OP code
HEX code
76 543 210 (Basic) C

Flags
S

Z

P/V

•
•
•
•

•
•
•
•

•
•
•
•

No. of

No. of

No. of

Bytes MCycles T States

H

0

0

1

1

4

Rotate left circular
accumulator.

0

0

1

1

4

Rotate left
accumulator.

0

0

1

1

4

Rotate right circular
accumulator .

0

0

1

1

4

Rotate right
accumulator.
Rotate left circular
register r.

RLCA

~
A

00 000 III

07

t

RLA

~
A

00 010 111

17

t

~
A

00 001 III

OF

t

00 011 III

IF

t

11
00
11
00
11
11

CB
00+
CB
06+
DD
CB

t t

P

t

0

0

2

2

8

t t

P

t

0

0

2

4

15

t t

P

t

0

0

4

6

23

t t

p

t

0

0

4

6

23

t t

P

t

0

0

RRCA
..

RRA

L!i3=@}J
A

RLCr
RLC (HL)
RLC (IX+d)

~
r, (HL),
(IX+d),
(IY+d)

RLC (IY+d)

+-

00
11
11
+-

00
RL m

001 011
k
r
001 011
k 110
011 101
001 011
d
k 110
111 101
001 011
d
k 110

-

06+
FD
CB

Comments

N

r
000
001
010
011
100
101
111

Reg.
B
C
D
E
H
L
A

06+

L:f6HEjJ
.
m

Mnemonic
RLC
RRC
RL
RR
SLA
SRA
SRL

k

000
001
010
011
100
101
111

RRC m

4E3lI9

t t

P

t

0

0

RR m

LiEID=@J

t t

P

t

0

0

SLA m

~
m

t t

P

t

0

0

SRA m

~

t t

P

t

0

0

m=r, (HL),
(IX +d), (IY +d)

SRL m

~
m

t t

P

t

0

0

* depends on m.

RLD

A~

RRD

A~

m

m

11 101 101
(HL) 01 101 III

(HL)

11 101 101
01 100 111

2*
4
6
6

8*
15
23
23

ED
6F

•

t

P

t

0

0

2

5

18

ED
67

•

t

P

t

0

0

2

5

18

Flags: • = unchanged
O=reset
1 = set
X =undefined
f =set or reset according to the result of the operation

304

2*
2
4
4

Rotate digit left and
right between the
accumulator and
location (HL).
The content of the
upper half of the
accumulator is unaffected.

Z80 CPU Central Processing Unit

LH0080

Table 8 Bit set, reset and test group

BIT b, r

Symbolic
operation
Z +- fb

BIT b, (HL)

Z

+-

(HL)b

BIT b, (IX +d)

Z

+-

(IX+d)b

BIT b, (IY+d)

Z

+-

(IY+d)b

Mnemonic

SET b, r

rb

SET b. (HL)

(HL)b

SET b, (IX+d)

(IX+d)b

+-

1
+-

1
+-

1

HEX code
OP code
76 543 210 (Basic) C
11 001 011
CB
01
b
r
40+
11 001 011
CB
01 b 110 46+
11 011 101
DO
11 001 011
CB
+d --+
01 b 110 46+
11 111 101
FD
11 001 011
CB
+d --+
01 b 110 46+
11 001 011
CB
a
b
r
11 001 011
CB
a b 110
06+
11 011 101
DO
11 001 011
CB
d --+
a b 110
06+
11 111 101
FD
11 001 011
CB
+d
a b 110
06+

•
•
•
•

N

t

Flags
S
X X

0

H
1

t

X

X

0

1

2

3

12

t

X

X

0

1

4

5

20

t

X

X

0

1

4

5

20

Z

P/V

••••••
• • • • • •
• • • •• •

No. of No. of No. of
Bytes M Cycles T States
2
2
8

2

2

8

2

4

15

4

6

23

4

6

23

2·
2
4
4

2·
4
6
6

8·
15
23
23

--

SET b, (IY+d)

RES b. m

(IY+d)b

mb

+-

+-

1

.-

• • • •••

0

Comments
r
000
001
010
011
100
101
111

Reg.
B
C
0
E
H
L
A

b
000
001
010
011
100
101
110
111

Bit Tested
0
1
2
3
4
5
6
7

Mnemonic
SET
RES

a
11
10

m=r, (HL).
(IX+d). (IY+d)
• depends on m

Note: The notation mb indicates bit b (0 to 7) or location m.
Flags: • = unchanged
O=reset
l=set
X= undefined
t =set or reset according to the result of the operation

-~~'--·~--SHARP---'----'-----

305

LHooao

zao CPU Central Processing Unit
Table 9 Jump group
Mnemonic
JP nn

JP cc, nn

JR e

Symbolic
operation

OP code
HEX code
76543 210 (Basic) C
11 000 011
C3
PC - nn
n -+
n -+
If condition cc
11 cc 010
C2+
is true PC ... nn,
n -+
otherwise con·
n -+
tinue
18
PC - PC+e 00 011 000

e·2

JR NC, e

PC - PC+e +- e·2 -+
IfC=O
continue
If C=O
00 110 000

JR NZ, e

JP (HL)
JP (IX)
JP (IY)
DJNZ, e

Bio

00 111 000

+-

H

e-2

• • • • ••

30

• • • • • •

28

-+

100 000

e-2

38

-+

101 000

e-2

• • • • • •
• • •• ••

-+

If C=l

JR Z, e

N

• • •• • •

JR C, e

PC - PC+e +IfC=l
continue
IfZ=l
00
PC - PC+e +IfZ=O
continue
IfZ=O
00
PC - PC+e +IfZ=l
continue
PC -HL
11
11
PC - IX
11
11
PC - IY
11
If B - B-1 00

Flags
S

PIV

• • •• • •

--+-

Z

• • • • • •

20

-+

101
011
101
111
101
010

001
101
001
101
001
000

e-2

-+

• •
• •
• •
• •

E9
DD
E9
FD
E9
10

PC -PC+l
If B=O
continue

• • •
• • •
•••
• • •

•
•

•
•

No. of No. of No. of
Bytes M Cycles T States
10 .
3
3

3

3

10

3

3

10

2

3

12

2

3

12

2

2

7

2

3

12

2

2

7

2

3

12

2

2

7

2

3

12

2

2

7

1
2

1
2

4
8

2

2

8

2

3

13

2

2

8

Comments
cc
000
001
010
011
100
101
110
111

Condition
NZ
Z
NC
C
PO
PE
P
M

NZ : non-zero
Z : zero
C : carry
PO : parity odd
PE : parity even
P : sign positive
M : sign negative

Note: e represents the extension in the relative addressing mode.
e is a signed two's complement number in the range -126,129>
e - 2 in the opcode provides an effective address of pc + e as PC is incremented by 2 prior to the addition of e.
e itself is obtained from opcode position.
Flags: • = unchanged
O=reset
1 = set
X = undefined
t = set or reset according to the result of the operation

<

-----.-.---.--.-..SHARP'---~--~--

306

Z80 CPU Central Processing Unit

LHP080

Table 10 Call and return group
Mnemonic
CALL nn

CALL cc, nn

RET
RET cc

RETI
RETN

RST p

Symbolic
operation
(SP-l) -PCH
(SP-2) - PCL
PC -nn
If condition cc is
false continue,
otherwise same
as CALL nn
PCL .... (SP)
PCH - (SP+1)
If condition cc is
false continue,
otherwise same
as RET
Return from
interrupt
Return from
non-maskable
interrupt
(SP-l) +- PCH
(SP - 2) +- PCL
PCH .... 0
PCL .... P

HEX code
OP code
76 543 210 (Basic) C
11 001 101 CD
n
n ' ....
11 cc 100 C4+
n
n

---

Flags
Z PlY S

N

H

••••••

....

•• • •••

....
....

11 001 001

C9

11 cc 000

CO+

11
01
11
01

101
001
101
000

101
101
101
101

ED
4D
ED
45

11

t

111

C7+

•••• ••
••••••
••••••
• • • •••
• • • • • •

No. of No. of No. of
Bytes M Cycles T States
17
3
5

3

5

17

3

3

10.

1

3

10

1

3

11

1

1

5

2

4

14

2

4

14

1

3

11

Comments
cc
000
001
010
011
100
101
110
111

Condition
NZ
Z
NC
C
PO
PE
P

r
000
001
010
011
100
101
110
111

p
DOH
08H
lOH
18H
20H
28H
30H
38H

M

Flags: • = unchanged
O=reset
l=set
X= undefined
t = set or reset according to the result of the operation

307

Z80 CPU Central Processing Unit

LH0080

Table 11 Input and output group
Mnemonic
INA, (n)

Symbolic
operation
A+- (n)

IN r, (C)

r +- (C)

INI

(HL) +- (C)
B +- B-1
HL +- HL+1
(HL) +- (C)
B +- B-1
HL +- HL+1
Repeat until
B=O
(HL) +- (C)
B +- B-1
HL +- HL-1
(HL) +- (C)
B +- B-1
HL +- HL-1
Repeat until
B=O
(n) +- A

INIR

IND

IN DR

OUT (n), A
OUT (C), r

(C) +- r

OUT!

(C) +- (HL)
B +- B-1

OTIR

OUTD

OTDR

HEX code
OP code
76 543 210 (Basic) C
11 011 011
DB
+- n -+
11 101 101
01 r 000
11 101 101
10 100 010

ED
40+
ED
A2

11 101 101
10 110 010

ED
B2

Flags
S

P/V

N

H

•• • • • •
• t t t
P

X

t

X

0

X

1

X

No. of No. of No. of
Bytes M Cycles T States
n
2
3
11
2

3

12

2

4

16

CD
X

1

X

X

1

X

2

®

11 101 101
10 101 010

ED
AA

X

11 101 101
10 III 010

ED
BA

X

t

011

D3

-+

101
001
101
011

21

X

1

X

2

4

16

X

X

1

X

2

5
(If Bf 0)
4
(If B=O)

21

2

•• • • • •
•• • • • •

2

3

ED
B3

X

t

An-A,

-+ A~-AI"

-+

An-A,

-+

As-AIr,

Reg.
B
C
D
E
H
L
A

16

11

n

-+

Ace

_.-

ED
41+
ED
A3

-+

r
000
001
010
011
100
101
111

16

X

®
11 010
+- n
11 101
01 r
11 101
10 100

5
(If BfO)
4
(If B=O)

C
B

CD
1

Comments

Ace

2

HL +- HL+1
(C) +- (HL)
11 101 101
B +- B-1
10 110011
HL +- HL+1
Repeat until
B=O
(C) +- (HL)
B +- B-1
HL +- HL-1
(C) +- (HL)
B +- B-1
HL +- HL-1
Repeat until
B=O

Z

2

3

12

(A·BUS)o-,

-+

(A-BUS)8-15

X

X

1

X

2

4

16

C

-+

Ao-A,

X

X

1

X

2

5
(IfMO)
4
(If B=O)

21

B

-+

As-AIr,

4

16

5

21

CD
X

1

®

11 101 101
10 101 011

ED
AB

X

11 101 101
10 III 011

ED
BB

X

t

2

X

X

1

X

2

X

X

1

X

2

16

CD
1

(If Bfa)

®

2

4
(If B=O)

16

Note: (!)If the result of B-1 is zero the Z flag is set, otherwise it is reset.
@Z flag is set upon instruction completion only.
Flags: • = unchanged
O=reset
1=set
X = undefined
t = set or reset according to the result of the operation

-~~--'-----'-SHARP

308

_.-....r __________

~

280 PIO Parallel Input/Output Controller

LH0081
•

zao PIO Parallel Input/Output Controller

Description

The Z80 product line is a complete set of microcomputer components, development systems and
support software. The Z80 microcomputer component set includes all of the circuits necessary to
build high-performance microcomputer systems
with virtually no other logic and a minimum number of low cost standard memory elements.
The LH0081 Z80 PIO (Z80 PIO for short below)
is a programmable two port device which provides
TTL compatible interfacing between peripheral devices and the Z80 CPU. The Z80 CPU configures
Z80 PIO to interface with standard peripheral devices such as printers, keyboards, etc.
The LH0081A Z80A and LH0081B Z80B PIO
are the high speed version which can opeate at the
4MHz and 6MHz system clock, respectively.

•

LH0081

•

Pin Connections
LH0081/LH0081A/LH0081B/LH0081E

o
CE
c/o

SEL

B/A SEL

Features
1. Two independent 8-bit bidirectional peripheral
interface ports with "handshake" data transfer
control
2. N-channel silicon-gate process

LH0081U/LH0081AU

ule.l~ ~ ~ ~ ~ ~ ~I.,;g
zuuoooooo",,8

*The GND pins must be connected to the GND leveL
--.---------~--SHARP -.---.-.~----

309

Z80 Pia ParaliellnputlOutput Controller

LH0081

3. Anyone of the following four modes of operation may be selected.
• Byte output mode
• Byte input mode
• Byte bidirectional bus (available on Port A
only)
• Bit mode
4. Programmable interrupt
5. Vectored daisy chain priority interrupt logic

•

included
6 .. The port B outputs can drive Darlington transistors
7. All inputs and outputs fully TTL compatible
8. Single + 5V power supply and single phase
clock
9. 40-pin DIP (DIP40-P-600)
44-pin QFP (QFP44-P-IOIOA)
44-pin QFJ (QFJ44-P-S650)

Ordering Information
Product
Clock frequency
Model No.

•

280 PIO
2.5MHz
LH008l
LH008lM
LH008lU

280A PIO
4MHz
LH008lA
LH008lAM
LH008lAU

280B PIO
6MHz
LH0081B
LH008IBU

280E PIO
8MHz
LH008IE

Package
40-pin DIP
40-pin QFP
40-pin QFJ

Operating
temperature
O°C to+70°C
O°C to+60°C
O°C to+70°C

Block Diagram

Internal
Cant rol Logi c
Port A
Data Bus

...

~

System Data Bus

o
P-.

Port B
Data Bus

Machine Cycle 1

I/O

...

~

Interrupt
Control Logic

o
P-.

Port B St robe·

> >
0
""'
+ ;:;
u
u

>

Pin numbers apply to 40-pin DIP.

310

Z

c.!l

...

<.i
0

u
S
.


""
0::



~

..9

~

~

"'5

......::>

..9



~

..9

Z80 PIO Parallel Input/Output Controller

•

Pin Description
Pin
Do-D7

-

B/A SEL

Meaning
Data bus

I

Control or data select

I

CE

Chip enable

I

CLOCK

System clock

I

-

-

-Ml
--

Machine cycle one

IORQ

Input/ output
request

RD
lEI
lEO
INT

Read cycle status
Interrupt enable in
Interrupt enable out
Interrupt request

, Ao-A7

---

~

I

Port A bus

I
I
0
Open drain, 0
Bidirectional
3-state

Port A strobe

I

A RDY

Port A ready

0

Bo-B7

Port B bus

Bidirectional
3-state

B STB

Port B strobe

I

B RDY

Port Bready

0

Function
System data bus.
Defines which port is accessed. A high selects port B,
and a low port A.
Defines the type of data transfer on the data bus. A high
selects control, and a low data.
Active "Low·. A low enables the CPU to transmit and
receive control words and data.
Standard 280 system clock used for internal synchronization signals.
Active "Low". Indicates that the CPU is acknowledging
-an interrupt, when both Ml and IORQ are active.
Active "Low". Read operation when RD is active, and
write operation when it is not active. Indicates that the
CPU is acknowledging an interrupt, when both IORQ
and Ml are active.
Active "Low". Read operation when active.
Active "High". Forms a priority-interrupt daisy-chain.
Active "High" .. Forms a priority-interrupt daisy-chain.
Active "Low·. Active when requesting an interrupt.
Transfers information between port A and a peripheral
device.
Active "Low". Used as a b,andshake line for data transfer synchronization on port A. Not used in the bit control mode.
Active "High". Used as a handshake line for data transfer· synchronization on port A. Not used in the bit control mode.
Transfers information between port B and a peripheral
device.
Active "Low·. Used as a handshake line for data transfer synchronization on port B. Not used in the bit control mode.
Active "High". Used as a handshake line for data transfer synchronization on port B. Not used in the bit control mode.

Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Stor-age temperature

i

I

A STB

--

;;,1

I/O
Bidirectional
3-state

Port B or A select

C/D SEL

•

LH0081

Symbol
VIN
V OUT

Topr
Tstg

Ratings
-0.3 to +7.0
-0.3 to +7.0
o to +70
-65 to +150

Unit
V
V

t
t

-'-'-~-""';""~~SHARP .-....-~--.-.-~----311·

Z80 PIO Parallel Input/Output Controller

LH0081

(Vcc=5V±5%, Ta=O to +70'C Note 1)

DC Characteristics

•

Parameter
Symbol
Clock input low voltage
VILC
Clock input high voltage
VIHC
Input low voltage
V IL
Input high voltage
VIH
Output low voltage
VOL
Output high voltage
VOH
Supply current
Icc
Input leakage current
I ILl I
3 state outputl data
I Iz I
bus input leakage current
Darlington drive current
IOHD
Note 1: Ta=Oto +60"(; for 44-pin QFP.

•

Conditions

MIN.
-0.3
Vcc-0.6
-0.3
2.0

O~VIN~VCC

100
10

Unit
V
V
V
V
V
V
rnA
pA

O~VIN~VCC

10

pA

IOL=2mA
IOH= -250 pA
VoH =1.5V

TYP.

2.4

REXT =390n

-1.5

rnA

(f=lMHz, Ta=25'C)

Capacitance
Parameter
Clock capacitance
Input capacitance
Output capacitance

•

Symbol

Conditions

CCLOCK
CIN
COUT

MIN.

Parameter

Symbol

1
2
3
4
5

Clock Cycle time
Clock width (high)
Clock width (low)
Clock fall time
Clock rise time
CE, BI A, CID to RD, IO~O !
Setup time
Any hold times for specified
setup time
RD, IORQ to clock t setup time
RD, IORQ ! to deta out delay
RD, IORQ t to deta out
float delay
Data in to clock t setup time
IORQ ! to vector out delay
(INT ACK cycle)
Ml ! to clock t setup time
Ml t to clock ! setup time
(Ml cycle)
Ml ! to lEO ! delay (interrupt
immedietely preceding Ml 0
lEI to IORQ ! setup time
(INT ACK cycle)

TcC
TwCh
TwCl
TfC
TrC

8
9
10
11
12
13
14
15
16
17
18

312

Unit
pF
pF
pF

LH0081
MIN. MAX.
400 (Note 1)
170 2000
170 2000
30
30

LH0081E
LH0081A
LH0081B
Unit Note
MIN. MAX. MIN. MAX. MIN. MAX.
250 (Note 1) 165 (Note 1) 125 (Note 1) ns
ns
55 2000
105 2000
65 2000
ns
65 2000
55 2000
105 2000
10
ns
20
30
ns
10
20
30

TsCS (RI)

50

50

50

50

ns

Th

0

0

0

0

ns

TsRI (C)
TdRI (DO)

430

380

300

210

ns
ns

160

110

70

60

ns

ll5

TdRI (DOs)

60

70

ll5

6

2

=50pF

50

50

40

30

ns

TdIO (001)

340

160

120

90

ns

TsMI (Cr)

210

90

70

55

ns

TsMI (Cf)

0

0

0

0

ns

8

ns

5, 7

ns

7

TsRI (C)

TdMI (lEO)
TslEI (IO)

! to lEO ! delay

TdlEI (lEO f)

lEI t to lEO t delay
(After ED decode)

TdlEI (lEOr)

lEI

MAX.
12
7
10

(Vcc=5V±5%, Ta=O to+70'C)

No.

7

TYP.

Unmeasured pins returned
to ground

AC Characteristics

6

MAX.
0.45
Vcc+0.3
0.8
5.5
0.4

190

300
140

100

140
190

130

85

100
100
120

llO

ns

L

3

5
=5OpF

L

210

160

160

150

ns

5

Z80 PIO Parallel Input/Output Controller

No.

Parameter

19

IORQ t to clock ~ setup time
(to activate READY to next
clock cycle)

20

Clock! to READY t delay

21
22
23
24
25
26
27
28
29

Clock! to READY! delay
STROBE pulse width
STROBE t to clbck ! setup
time (to activate READY on
next clock cycue)
IORQ t to PORT DATA stable
delay (Mode 0)
PORT DATA to STROBEt
setup time (mode 1)
STROBE! to PORT DATA
stable (mode 2)
STROBE t to PORT DATA
float delay (mode 2)
PORT DATA match to INT !
delay (mode 3)
STROBE t to INT ! delay

LH0081

Symbol

LH0081
LH0081A
LH0081B
LH0081E
Unit Note
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

TelO (C)

220

200

170

160

ns

TdC (RDYr)

200

190

170

160

ns

TdC(RDYf)
TwSTB

150
150

140
150

120
120

110
100

ns
ns

5
=5OpF
5
4

TsSTB (C)

220

220

150

130

ns

5

ns

5

TdIO (PD)
TsPD (STB)

180

200
260

L

230

150

160
190

ns

170

TdSTB (PD)

230

210

180

160

ns

TdSTB (PDr)

200

180

160

140

ns

TdPD (INT)

540

490

430

380

ns

TdSTB (INT)

490

440

350

300

ns

5
L

=50pF

t Rising edge, l Falling edge
Ta=O to+60"C for 44-pin QFP.
Note 1: TcC=TwCh+TwCI+TrC+TfC.
Note 2: Increase TdRI (DO) by 10 ns for each 50 pF increase in load up to 200 pF max.
Note 3: Increase TdIO (DOl) by 10 ns for each 50 pF, increase in load up to 200 pF max.
Note 4: For Mode 2 : TwSTB>TsPD (STB).
Note 5: Increase these values by 2 ns for each 10 pF increase in load up to 100 pF max.
Note 6: TsCS (RI) may be reduced. However, the time subtracted from TsCS (RI) will be added to TdRI (DO).
Note 7: 2.5 TcC>(N-2) TdIEI (IEOf)+TdMl (IEO)+TsIEI (10)+TTL buffer delay, if any.
Note 8: M1 must be active for a minimum of two clock cycles to reset the PIO.
Note 9: 280B PIO numbers are preliminary and subject to change.

---.-----SHARP~--.-.----

313

Z80 PIO Parallel Input/Output Controller

•

LH0081

AC Timing Chart

CLOCK
CE
B/A,C/O
RD,IORQ
OUT
Do-D7 {

IN
IORQ

Ml

IEI

lEO
READY
(ARDY or BRDY)
STROBE
(ASTB or BSTB)

Mode 0

Ao- A7

Mode 1

Bo-B7

Mode 2
Mode 3

INT

·..· , - . - . - - - - - - - , - - - - S H A R P - . . . - . - - - - - - 314

Z80 PIO ParaliellnputlOutput Controller

Programming

•
(1)

LH0081

(3) Interrupt control
The interrupt control words are as follows.

Interrupt vector read

An interrupting device needs giving an 8-bit interrupt vector to the CPU. Using this vector, the
CPU forms an interrupt service routine address.
v

y

Indicates that the information
is interrupt control words

Effective in bit
control mode

Bit7= 1:

(2)

Operation mode select

An operation mode is selected by writing data to
the 2-bit mode control register in the following
manner.

777

1:1:1:1:1:1 1 1 1
'----y---'
Mode Words

Interrupt enable flag is set to enable an interrupt.
_
Bit7=0: Interrupt enable flag is reset to disable an interrupt.
Bit6 to 4: Defines interrupt conditions in the
bit mode. Ignored in other modes.
Bit3 to 0: Indicates interrupt control words.
If bit4 = 1, the following control words are supposed to be written in the mask register.

'-----y-------Indicates
Mode Words

X means they are not used

Mode
Byte output mode
Byte input mode
Bidirectional byte bus mode
Bit control mode

Ml

MO

0
0

0

1
1

0

1

Only the port data line with MB=O is monitored.
When the interrupt conditions are satisfied, an interrupt takes place.

1

In selecting the bit control mode, an input/output
direction should be set later.

Interrupt
enable
flag

X

X

X

0

0

1

1

~

Not affected by
these bits

Discriminator code

IiO=l:Input; 1/0=0: Output

•

Timing
(1) Output mode (Mode 0)

An output cycle is always started by the executidn of an output instruction by the CPU. The WR *
pulse from the CPU latches the data from the CPU
data bus into the selected port's output register.
-The WR * pulse sets the Ready flag after a Lowgoing edge of CLK, indicating data is available.

Ready stays active until the positive edge of the
strobe line is received, indication that data was
taken by the peripheral. T~positive edge of the
strobe pulse generates an INT if the interrupt enable flipflop has been set and if this device has the
highest priority.

315

Z80 PIO Parallel Input/Output Controller

LH0081

CLOCK

Port output

RDY

STB

INT
WR'=RD·CE·C/D·IORQ

Fig. 1

(2)

Byte output mode timing

Input mode (Mode 1)

When STROBE goes Low, data is loaded into the
selected port input register. The next rising edge of
strobe activates INT, if Interrupt Enable is set and
this is the highest-priority requesting device. The
following falling edge of CLK resets Ready to an in·
active state, indicating that the input register is full

and cannot accept any more data until the CPU
completes a read. When a read is complete, the
positive edge of RD sets Ready at the next Lowgoing transition of CLK. At this time new data can
be loaded into the PIO.

CLOCK

Port input

RDY

INT

RD'
RD'=RD·CE·C/D·IORQ

Fig. 2

(3)

Byte input mode timing

Bidirectional mode (Mode 2)

This is a combination of Modes 0 and 1 using all
four handshake lines and the eight Port A I/O
lines. Port B must be set to the bit mode and its
inputs must be masked. The Port A handshake
lines are used for output control and the Port B
lines are used for input control. If interrupts occur,

Port A's vector will be used during port output and
Port B's will be used during port input. Data is
allowed out onto the Port A bus only when ASTB
is Low, The rising edge of this strobe can be used
to latch the data into the peripheral.

~'-'~---'-'--SHARP-""""-'-~-----

316

LH0081

Z80 PIO Parallel Input/Output Controller

CLOCK

WR*

A RDY _ _ _ _ _ _ _ _ _- - J

A 5TB

Port A data !ius -----------~~~.rJ-""1~~lJ_r---

INT

B 5TB

B RDY
WR* =RD·CE·C/D·IORQ

Fig. 3

(4)

Byte bidirectional bus mode timing

Bit mode (Mode 3)

The bit mode does not utilize the handshake signals, and a normal port write or port read can be
executed at any time. When writing , the data is
latched into the output registers with the same timing as the output mode.
When reading the PIO, the data returned to the
CPU is composed of output register data- from those
port data lines assigned as outputs and input regis-

ter data from those port data lines assigned as inputs. The input register contains data that was present immediately prior to the falling edge of RD. An
interrupt is generated if interrupts from the port
are enabled and the data on the port data lines
satisfy the logical equation defined by the 8-bit
mask and 2-bit mask control registers. However, if
Port A is programmed in bidirectional mode, Port B
does not issue an interrupt in bit mode and must
therefore be polled.

CLOCK

Port data bus

IORQ

RD

L Data word 1 placed on bus
Fig. 4

Bit mode timing

-'--~-~--SHARP'--'-'--------

317

5 ==~

~

LH0081

Z80 PIO Parallel Input/Output Contr911er

(5) Interrupt acknowledge timing
During Ml time, peripheral controllers are inhi- .
bited from changing their interrupt enable status,
permitting the Interrupt Enable signal to ripple
through the daisy chain. The peripheral with IEI
High and lEO Low during INT ACK places a preLast T state

programmed 8~bit interrupt vector on the data bus
at this time. IEO is held Low until a Return From
Interrupt (RETI) instruction is executed by the
CPU while lEI is High. The 2~byte RETI instruction is decoded internally by the Pia for this purpose.
Tw'

Tw'

CLOCK

INT

MI

lEO

Fig. 5

(6)

Interrupt acknowledge timing

Return from interrupt cycle

If a Z~80 peripheral has no interrupt pending
and is not under service, then its IEO=IEI. If it has
an interrupt under service (i.e., it has already interrupted and received an interrupt acknowledge)
then its IEO is always Low, inhibiting lower priority devices from interrupting. If it has an interrupt
pending which has not yet been acknowledged, IEO
is Low unless an "ED" is decoded as the first byte
of a 2~byte opcode. In this case, lEO goes High until the next opcode byte is decoded, whereupon it

goes Low again. If the second byte of the opcode
was a "4D", then the opcode was an RETI instruction.
After an "ED" opcode is decoded, only the
peripheral device which has interrupted and is currently under service has its lEI High and its IEO
Low. This device is the highest~priority device in the
daisy chain that has received an interrupt acknowledge. All other peripherals have lEI = IEO. If the
next opcode byte decoded is "4D". this peripheral de'
vice resets its "interrupt under service" condition.

CLOCK
MI

lEI

lEO

Fig. 6

318

Return from interrupt cycle timing

LH0082

Z80 CTC Counter Timer Circuit

LH0082
•

zao CTC Counter Timer Circuit

Description

The Z80 product line is a complete set of microcomputer components, development systems and
support software. The Z80 microcomputer component set includes all of the circuits necessary to
build high-performance microcomputer systems
with virtually no other logic and a minimum number of low cost standard memory elements.
The LH0082 Z80 CTC (Z80 CTC for short below) is a programmable, four channel device that
provides counting and timing functions for the Z80
CPU. The Z80 CPU configures the Z80 CTC's four
independent channels to operate under various
modes and conditions as required.
The LH0082A Z80A and LH0082B Z80B CTC
are the high speed version which can operate at the
4MHz and 6MHz system clock, respectively.

•

•

Pin Connections

LH0082/LH0082A/LH0082B/LH0082E

Features

17 RESET

1. Four independent programmable 8-bit counterl16-bit timer channels
2. N-channel silicon gate process
3. Each channel may be selected to operate in
either a counter mode or timer mode

LH0082U/LH0082AU/LH008.2BU

34

NC

33

CLK/TRG 1
CLK/TRG2
CLK/TRG 3

32
31

Top View

*The GND pins must be connected to the GND level.
....-.~-------~SHARP

---'.-.-----319

LH0082

Z80 CTC Counter Timer Circuit

9. Three channels I}ave ZC/TO outputs capable of
driving Darlington transistors
10. Vectored daisy chain priority interrupt logic
included
11. Single + 5V power supply and single phase
clock
12. All inputs and outputs fully TTL compatible
13. 28-pin DIP (DIP28-P-600)
44-pin QFP (QFP44-P-1010A)
44-pin QFJ (QFJ44-P-S650)

4. Programmable interrupts on counter or timer
states
5. When the down-counter reaches the zero count
the CTC reloads its time constant automatically
and continues it's channel operation
6. Readable down counter
7. Selectable 16 or 256 clock prescaler for each
timer channels
8. Selectable positive or negative trigger may in·
itiate timer or counter operation

•

Ordering Information
Product
Clock frequency
Model No.

•

Z80 CTC
2.5MHz
LH0082
LH0082M
LH0082U

Z80A CTC
4MHz
LH0082A
LH0082AM
LH0082AU

Z80B CTC
6MHz
LH0082B
LH0082BU

Z80E CTC
8MHz
LH0082E

Package
28-pinDIP
44-pin QFP
44-pin QFJ

Operating
tern perature
O°C to+70°C
O°C to+60°C
O°C to+70°C

Block Diagram

Zero Count/
Timeout Output
Clock/Trigger
Input
Internal
Cont rol Logi c

.,

System

.

C)

Data

Zero Count/
Ti meout Output
Clock/Trigger
Input

o

..J

Bus

Zero Count/
Timeout Output
Clock/Trigger
Input

Clock/Trigger
Input

t

:>
U")

'" +


....." :;
0
"
:c
p::;
:c
Ei
"'" '"
!! "
>.
'"
"......"'" ..."'" 15rJl
"
...
.]'" !! "......

:>

"'"
0

Ui


Z

"

C)

 (n-2) TdlEI (IEOf) + TdMI (lEO) + TslEI (10) + TTL buffer delay, if auy.
[BI·RESET must be active for a minimum of 3 clock cycles.
Note 1: TcC=TwCh+TwCl+TrC+TfC.
Note 2 : Increase delay by 10 ns for each 50 pF increase in loading, 200 pF maximum for data lines, and 100pF for control lines.
Note 3 : Increase delay by 2 ns for each 10 pF increase in loading, 100 pF maximum.
Note 4 : Timer mode.
Note 5 : Counter mode.

322

Z80 CTC Counter Timer Circuit

•

LH0082

AC Timing Chart

~CD---;>o

CID~
CLOCK
CSO,CSI

n®

®

r

~~@

,

}(

IX

k-CV-

-

CE

~ -®

~

L

I-®--

IORQ

R ead

r""""\~ C""\~ ~
f-;-t--- -®

¥

\-

®---k----..

-"
RO

@--1

-I,

\,
@~

@- ~

0 0 -07
~-@~

)(

CSo, CSI

-

--

,~,

{

IORQ

¥

X

MI

--

~ @

®-k---;.
J(
X
i--@- k-I--®

0 0 -0 7

-@

/

\i.,I-® __

IORQ

Inter
acknowl edge

J(

k-CV~ ~

CE

write

-@ -+J

-+
i

I

ct

~@ h
\

~

I

0 0 -0 7

@

..-@

I

-@~

IEI

k-@

f--;:o-

IEO
- ~

$
®---I~@

--J
\.

~®~

~

~~

®>\-

..,.:::..,.j

323

zaG eTC Counter Timer Circuit
•

LHooa2

Programming
(1) Operation mode select

To select a channel operating mode, write a channel control word having bit 0 changed to 1 in the
channel control- register.
D6
Interrupt
enable

Ds

Prescaler
Mode v·alue

D.
D3
eLK/ Trigger Time
TRO
mode
edge
selection

constant
Reset
mode

Do
1

D3 and Ds are used in timer mode only.
• Bit 7 = 0: Disables a channel interrupt.
• Bit 7 = 1: Enables a channel interrupt each
time the down-counter counts down to zero.
No interrupt is produced even with bit 7 as 1,
after the counter has counted down to zero
with bit 7 as O.
• Bit 6 = 0: Selects the timer mode, having the
prescaler output as the down-counter clock.
The timer's period comes in te. P. TC. Where
te represents system clock period, P has 16
or 256 (divisional scale by the prescaler), and
TC means an 8-bit programmable time constant (max. 256).
'
• Bit 6 = 1: Selects the counter mode, having the
external dock (CLK input) signal-as the downcounter clock. The prescaler is not used.
.Bit 5 = 0: Used for the timer mode only. The
prescaler divides the system clock into 16 sections.
• Bi~ 5 = 1: Used for the timer mode only. The
prescaler divides the system clock into 256
sections.
• Bit 4 = 0: Starts the timer operation at the trigger input falling edge in the timer mode. In the
counter mode, the down-counter comes on at
the clock input rising edge.
• Bit 4 = 1: Starts the timer operation at the trigger input rising edge in the timer mode. In the
counter mode, the down-counter comes on at
the clock input rising edge.
• Bit 3 = 0: Effective in the timer mode only.
With bit 1 =1, the timer starts at the rising
edge of the machine cycle T2 which is next to
the write cycle of a time constant. With bit
1 =0, the timer starts _at the rising edge of the
machine cycle Tl which is next to the write cycle of this control information.
• Bit 3 = 1: Effective in the timer mode only. The
timer starts by an external trigger input that
is given after the rising of the machine cycle
·T2 next to the write cycle of a time constant.

324

The operation starts at the second clock rising .
if the trigger input meets the set-up time,and
at the third clock rising if it does not. If an external trigger input is given before writing a
time constant the condition of bit 3 = 0 is
caused .
• Bit 2 = 0: Indicates that there is no time constant written after the channel control word.
This bit cannot be 0 for the channel control
word to be immediately given when the channel is reset.
• Bit 2 = 1: Indicates that there is a time constant
written after the channel control word. When
a time constant- is written during a downcounter operation, the new constant is set into
the time constant register. But the counter
keeps on counting. Once the counter counts
zero, the new constant is available to use.
.Bit 1 = 0: The channel acts as a down-counter .
• -Bit 1 = 1: Stops the operation as a down-counter. With bit 2 = 1, the operation restarts after
a time contant is written.
With bit 2 =.0, the channel does not act until a
new control word is -given.
(2)

Time constant programming

An 8-bit time constant is written into the time
constant register, following the channel control
word with bit 2 = 1. "00" (hexadecimal) indicates
the time constant 256.
~

TC7

(3)

~

lli

I TC6 I TCs

~

lTC,

lli

~

~

~

TC3

TC2

TCI

TCo

Interrupt vector programming

If the Z-'-80 CTC has one or more interrupts enabled, it can supply interrupt vectors to the Z-80
CPU. To do so, the Z-80 CTC must be pre-programmed with the most-significant. five bits of the
interrupt vector. Programming consists of writing
a vector word to the 110 port corresponding to the
Z-80 CTC Channel O. Note that Do of the vector
word is always zero, to distinguish the vector from
a channel control word. Dl and D2 are not used in
programming the vector word. These bits are supplied by the interrupt logic to identify the channel
requesting interrupt service with a unique interrupt vector. Channel 0 has the highest priority.

LH0082

Z80 CTC Counter T'imer Circuit

D6
V6

•

D5
V5

v,

D,
0
0

Dl
0
1

1

1
1

0

2
3

1

D3

D,

v,

Do
VI

Vo

Channel
0

Timing

(1) Write cycle timing
Fig, 1 shows write cycle timing for loading control, time constant or vector words.
The CTC does not have a write signal input, so it
generates one internally when the read (RD) input
is High during Tl. During T, IORQ and CE inputs
are Low. Ml must be High to distinguish a write
cycle from an interrupt acknowledge. A 2'-bit binary code at inputs CSI and CSo selects the channel
to be addressed, and the word being written is
placed on the Z-80 data bus. The data word is
latched into the appropriate register with the rising edge of clock cycle T3.
(2) Read cycle timing
Fig. 2 shows read cycle timing. This cycle reads
the contents of a down-counter without disturbing
the count.
During clock cycle Tz, the Z-80 CPU initiates a
read cycle bzjriving the following inputs Low: RD,
IORQ, and CEo A 2-bit binary code at inputs CSI

and CSo selects the channel to be read. Ml must be
High to distinguish this cycle from an interrupt
acknowledge. No additional wait states are allowed.
(3) Interrupt acknowledge timing
Fig. 3 shows .interrupt acknowledge timing. After an interrupt request~e Z-80 CPU sends an
interrupt acknowledge (Ml and IORQ). All channels are inhibited from changing their interrupt request status when Ml is ~tive-about two clock
cycles earlier than IORQ. RD is High to distinguish
this cycle from an instruction fetch.
The CTC interrupt logic determines the highest
priority channel requesting an interrupt. If the
CTC interrupt enable input. (lEI) is High, the highest proiority interrupting channel within the CTC
places its interrupt vector on the data bus when
IORQ goes Low. Two wait states (TwA) are automatically inserted at this time to allow the daisy
chain to stabilize. Additional wait states may be
added.
(4) Return from interrupt cycle
If a Z-80 peripheral has no interrupt pending
and is not under service, then its lEO = lEI. If it has
an interrupt under service (i.e.,it has already interrupted and received an interrupt acknowledge)
then its lEO is always Low, inhibiting lower priority devices from interrupting. If it has an interrupt
pending which has not yet been acknowledged, lEO
is Low unless an "ED" is decoded as the first byte
of a 2-byte opcode. In this case, lEO goes High until th' next npcode byte i, dec,d,d. whmupnn it
goes Low again. If the second byte of the opcode

CLOCK
CSO.~SI--~----~r--~------~------~----~I--~------

Channel address

CE
IORQ

RD

Ml

Do-D7

Input

Fig. 1

Write cycle timing

-~------SHARP-"'--'------

325

15

LH0082

Z80 CTC Counter Timer Circuit

in the daisy chain that has received an interrupt
acknowledge. All other peripherals have IEI = IEO.
H the next opcode byte decoded is "4D", this
peripheral device resets its "interrupt under service" condition.

was a "4 D," then the opcode was an RETI instruction.
After an "ED" opcode is decoded, only the
peripheral device which has. interrupted and is
currently under service has its IEI High and its
lEO Low. This device is the highest-priority device

T2

Tl

T3

Tw'

T.

CLOCK
CS o, CS

1

Channel address

CE
IORQ

RO

Ml

Output

0 0 -0 7

Fig. 2

Last T
state
CLOCK

---'

Read cycle timing

Tl

T2

Tw'

T3

I Tw·

T.

h-~h-h-h-h-h-hII

1\

Ml

I--

lJ

\

IORQ
RO

l

lEI _

lEO

- ""'\
- "\

--- -~---

-- r--- --- --- --

~J

r----- --- ~L.J
Vector
1

Fig. 3

Interrupt acknowledge timing

~"""""'---------~-SHARP---""';;;;""'--""-'~-

326

Z80 CTC Counter Timer Circuit

TI

LH0082

T,

T,

Ta

Fig. 4

Return from interrupt cycle

T.

TI

Ta

TI

T.

CLOCK

Ml
RD
Do-D7

IEI
lEO

Channel 0

Channell

Channel 2

CD

Daisy chain prior to interrupt

®

When Channel 2 requests interrupt and receives acknow ledge.

Channel 3

During service

®

When Channel I requests interrupt and receives acknow ledge.
In this case, Channel 2 service is discontinued temporarily.
Service restart

@ When Channell service is completed and RET I instruction is executed.
In this case, Channel 2 service is restarted.

.------..,··Hi h··
lEI

®

lEO

g

When Channel 2 service is completed and RETI instruction is executed.

Fig. 5

Daisy-chain interrupt service

- - - . . . . . - . - - - - - - S H A R P _ . - . . - . _ _ _ _ .--r

327

LH0082

Z80 CTC Counter Timer Circuit

(5)

Daisy-chain interrupt service

(6)

Fig. 5 shows a typical nested interrupt order
with the CTC. Channel 2 first requests an interrupt to be serviced. If the higher-priority Channel
1 requests an interrupt while Channel 2 is in service, the Channel 2 service is interrupted and
Channell is serviced instead. Now the Channell
service routine has been completely executed, an
RET! instruction can be given to indicate that
Channel 1 has been serviced. At this moment,
Channel 2 will be in service again.

Counter operation/timer operation

In the counter mode, the CLK/TRG pulse input
decrements the down-counter. The trigger is asynchronous, but the count is .synchronized with CLK.
For the decrement to occur on the next rising edge
of CLK, the trigger edge must precede eLK by a
minimum lead time. In the timer mode, a CLK/TRG
pulse input starts the timer on the second succeeding rising edge of CLK. The trigger pulse is asynchronous,and it must have a minimun width. A
minimun lead time (210 ns) is required between the
active edge of the CLK/TRG and the next rising
edge of CLK to enable the prescaler on the following clock edge.

CLOCK

\....... _ _ _.....J/

CLK

Counter mode
Down counter

_ _ _....JI

ZC/TO

___--'I

\'---

Zero count

\~-----

CLOCK

TRG

Prescaler

\
I
__________----.......J/

Timer mode

Start operatig

Fig. 6

Counter operation/timer operation

. . . - - . - - - - - - - - - - - $ H A R P ----.-~,~------~

328

Z80 DMA Direct Memory Access

LH0083
•

LH0083

zao DMA Direct Memory Access

Description

The LH0083 Z80 DMA (Z80 DMA for short below) is a powerful and versatile device for controlling and processing of data transfers. Its basic
function of managing CPU -independent transfers
between two ports is augmented by an array of features that optimize transfer speed and control with
little or no external logic in systems using an 8-or
16-bit data bus and a 16-bit address bus.
Transfers can be done between any two ports
(source and destination), including memory-to-I/O,
memory-to-memory, and I/O-to-I/O. Dual port
addresses are automatically generated for each
transaction and may be either fixed or incrementing/
decrementing. In addition, bitmaskable byte searches
can be performed either concurrently with transfers
or as an operation in itself.
The LH0083A Z80A DMA is a high speed version which can operate at the 4MHz system clock.

•

Pin Connections
LH0083/LH0083A

o

BUSRQ 15

•

CE/WAIT

Features

1. Transfers, searches and search / transfers in
byte-at-a-time, burst or continuous modes
2. Cycle length and edge timing can be programmed
3. Dual port addresses generated for memoryto-I/O, memory-to-memory, or I/O-to-I/O operations Adderess may be fixed or automatically incremented/decremented
4. Next-operation loading without disturbing current operations via buffered starting-address
registers and an entire previous sequence can
be repeated automatically
5. Extensive programmability of functions CPU
can read complete channel status
6. Vectored daisy chain priority interrupt logic
7. Single + 5V power supply and single phase
clock
8. TTL compatible inputs and outputs
9. N-channel silicon-gate process
10. 40-pin DIP (DIP40-P-600)

Top View

•

Ordering Information

L

LH0083 X

Clock frequency
Blank: 2.5MHz
A: 4MHz
Model No.

------------SHARP------------329

Z80DMA Direct Memory Access

•

LH0083

Block Diagram
.. ~

+

~
0

u

.u

;>

Bus Acknowlege In
Bus Acknowlege Out
Interrupt Request
Interrupt Enable In
Interrupt Enable Out

Interrupt
and Bus
Priority
Logic

Pulse
Logic

Byte
Counter

System
Address
Bus

System Data Bus

Machine Cycle 1
110 Request
Memory

330

Bus
Control
Logic

Control
and
Status
Registers

Byte
Match
Logic

Z80 DMA Direct Memory Access

•

LH0083

Pin Description
Pin
Ao-A15

Meaning
Address bus

Do-D7

Data bus

110
0
Bidirectional
3-state
3~state

-

BAI

-BAO

BUSRQ

Bus acknowledge in

I

Bus acknowledge out

0

Bus request

Open drain, 0

CE/WAIT

Chip enable

I

CLOCK

System clock

I

Machine cycle one

I

---

-

Ml

-!ORQ

--

MREQ

Input/output request

Memory request

Bidirectional
3-state

3-state 0

lEI

Interrupt enable in

I

lEO

Interrupt enable out

0

----

INT/PULSE
-

Interrupt request/pulse

RD

Read

WR

Write

RDY

Ready

Open drain, 0
Bidirectional
3-state
Bidirectional
3-state
I

Function
System address bus.
System data bus.
Active "low". Used to form a bus priority-interrupt
daisy-chain.
Active "low". Used to form a bus priority-interrupt
daisy-chain.
Active "low". Active when controlling the bus.
Active "low". Acts as CE when the CPU accesses the
DAM, and as WAIT when the DAM is the bus master.
Standard Z80 system clock used for internal synchronization signals.
Active "low". Indicates that CPU is acknowledging an in-terrupt, when both Ml and !ORQ are active.
Active "low". Transmits and receives data from the CPU
-as an input line. Acts as 10RQ for another device as an
output line. Indicates that the CPU is acknowledging an
-interrupt, when both IORQ and Ml are active.
Active "low". Requests a transfer from or to memory
with the DMA as a bus master.
Active "high". Used to form a priority-interrupt
daisy-chain.
Active "low". Used to form a priority-interrupt
daisy-chain.
Active "low". Active when requesting an interrupt. Can
also generate pulses.
Active "low". Reads data from the CPU as an input line.
Acts as RD for another device as an output line.
Active "low". Writes data from the CPU as an input line.
Acts as WR for another device as an output line.
With the DMA as a bus master, starts DMA operation
when active, and stops it when not active.

331

Z80DMA Direct Memory Access

•

LH0083

Absolute Maximum Ratings
Parameter
Input voltage
Output voltage
Operating temperature
Storage temperature

•

Symbol
V IN
VOliT
Topr
Tstg

Ratings
-0.3 to +7.0
-0.3 to +7.0
o to +70
-'65 to + 150

Unit
V
V
t

·C

(Vcc=5V±5%, Ta=O to +70t)

DC Characteristics
Parameter
Clock input low voltage
Clock input high voltage
Input low voltage
Inputhigh voltage

Symbol

Output low voltage

VOL

Output high voltage

V OH

Current
consumption

l LH0083

I LH0083A

Input leakage current
3-state output leakage current
3-state output leakage current
Data bus leakage current in
input mode

•

Conditions

VILC
VIlle
V IL
VIH

Icc

I ILl I
I ILOII I
I ILOL I
Irw I

IOL =3.2mA for BUSREQ
IOL =.2.0 .mA for all others
IoH = - 250 p.A

MIN.
-0.3
Vec -0.6
0.3
2.0

332

MAX.
0.45
5.5
0.8
5.5

Unit
V
V
V
V

0.4

V

150
200
10
10
10

V
rnA
rnA
p.A
p.A
p.A

10

p.A

2.4

tc=400ns
t c =250ns
O::;;;:VIN::;;;:V ee
VollT -2.4V
VOllT =O.4V
OV~VIN~Vee

(f=IMHz, Ta=25·C)

Capacitance
Parameter
Clock capacitance
Input capacitance
Output capacitance

TYP.

Symbol
CCLOCK
CIN
COUT

Conditions
Unmeasured pins returned
to ground

MIN.

TYP.

MAX.
35
5
10

Unit
pF
pF
pF

Z80 DMA Direct Memory Access

•

LH0083

AC Characteristics
(1)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Acting as CPU peripheral (inactive state)
Parameter

(Vcc=5V±5%, Ta=O to +70"C)
Symbol

Clock cycle time
TcC
Clock width (high)
TwCh
Clock width (low)
TwCI
TrC
Clock rise time
Clock fall time
TfC
Hold time for any specified setup time
Th
IORQ, WR, CE ~ to clock t setup time
TsC(Cr)
TdDO(RDf)
RD ~ to data output delay
Data in to clock t setup (WR or M1)
TsWM(Cr)
IORQ ~ to data out delay (lNT A cycle)
TdCf(DO)
RD t to data float delay (output buffer disable)
TdRD(DZ)
lEI ~ to IORQ ~ setup (INT A cycle)
TsIEI(IORQ)
lEI t to lEO t delay
TdIEOr(lElr)
lEI ~ to lEO ~ delay
TdIEOf(IEIf)
M1 ~ to lEO ~ delay
TdM1(IEO)
(interrupt just prior to M1 ~ )
M1 ~ to clock t setup
TsMlf(Cr)
TsMlr(Cf)
MIt to clock ~ setup
RD ~ to clock t setup (M 1 cycle)
TsRD(Cr)
Interrupt cause to INT ~ delay
TdI(INT)
(I NT generated only when DMA is inactive)
TdBAIr(BAOr)
BAI t to BAO t delay
BAI ~ to BAO ~ delay
TdBAIf(BAOf)
TsRDY(Cr)
RDY active to clock t setup time

LH0083
MIN.
MAX.
4000
400
170
2000
2000
170
30
30
0
280
500
50
340
160
140
210
190

LH0083A
MIN.
MAX.
250
4000
110
2000
110
2000
30
30
0
145
380
50
160
110
140
160
130

300

190

210
20
240

150

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

90
-10
115
500

500

ns

200
200

150
150

ns
ns
ns

100

Note : t Rising edge, t Falling edge.
Note 1: Negative minimum setup values mean that the first-mentioned event can come after the second-mentioned event.

333

LH0083

Z80 DMA Direct Memory Access

eLK

RD
Do-D7

MI
lEI
lEO

I

Interrupt state

_ _ _ _-.---JF@=:)I
.

...:....----1-----

I

BAI
BAO

RDY

~_.
_r;=_@_11'_____
"t=_@--.;....J)_~~~®_~--+-I
-----,-~tive
r
Inactive

Acting as CPU peripheral (Inactive.state)

334

Z80 DMA Direct Memory Access

(2)

Acting as bus controller (active state)

No.

Parameter

1
2
3
4
5
6
7
8
9
*10
*11
12
*13
14
15
*16
17
*18
19
20

---

21
22
23
-24
*25

--26
27
28
*29
30
31
32
33
34
35
36
37
38
39
40
41

Note
Note
Note
Note
Note

:
1:
2:
3:
4:

Clock cycle time
Clock width (high)
Clock width (low)
Clock rise time
Clock fall time
Address output delay
Clock t to address float delay
Address to MREQ l setup (memory cycle)
Address stable to IORQ, RD, WR l setup
(110 cycle)
RD, WR t to addr. stable delay
RD, WR t to addr. float delay
Clock l to data out delay
' Clock t to data float delay (write cycle)
Data in to clock t setup
(read cycle when rising edge ends read)
Data in to clock l setup
(read cycle when falling edge ends read)
Data out to WR l setup (memory c1e1e)
Data out to WR l setup (110 cycle)
WR t to data out hold time
Hold time for any specified setup time
Clock t to MREQ l drlay
Clock l to MREQ l delay
Clock t to MREQ t delay
Clock l to MREQ t delay
MREQ low pulse width
MREQ high pulse width
Clock l to MREQ l delay
Clock t to IORQ l delay
Clock t to IORQ t delay
Clock l to IORQ t delay
Clock t to RD l delay
Clock l to RD l delay
Clock t to RD t delay
Clock l to RD t delay
Clock t toWR l delay
Clock l to WR l delay
Clock t to WR t delay
Clock l to WR t delay
WR Low pulse width
WAIT to clock l setup
Clock t to 8USREQ delay
Clock t to IORQ, MREQ, RD, WR float delay

LH0083

(Vcc=5V±5%, Ta=O to +70t)
Symbol
TcC
TwCh
TwCI
TrC
TfC
TdA
TdC(AZ)
TsA(MREQ)

LH0083
MIN.
MAX.
400
180
2000
180
2000
30
30
145
110
(21+(51-75

LH0083A
MAX.
MIN.
250
110
2000
110
2000
30
30
110
90
(21+(51-75

Unit
ns
ns
ns
ns
ns,
ns
ns
ns

TsA(IRW)

(1)-80

(1)-70

ns

TdRW(A)
TdRW(AZ)
TdCf(DO)
TdCr(Dz)

(31+(41-40
(31+(41-60

(31+(41-50
(31+(41-45

ns
ns
ns
ns

150
90

230
90

TsDI(Cf)

50

35

ns

TsDO(WfM)

60

50

ns

TsDO(WPI)
TsDO(WPI)
TdWr(DO)
Th
TdCr (Mf)
TdCf(Mf)
TdCf(Mr)
TdCf(Mr)
TwMI
TwMh
TdCf(Mf)
TdCr(If)
TdCr(Ir)
TdCr(lr)
TdCr(Rf)
TdCr(Rf)
TdCr(Rr)
TdGr(Rr)
TdCr(Wf)
TdCf(Wf)
TdCr(Wr)
TdCf(Wr)
TwWI
TsWA(Cf)
TdCr(8)
TdCr(Iz)

111-210
100
(31+(41-80
0

111-170
100
(31+(41-70
0
100

85

100
100
100

85
85
85
(1)-30
(21+(31-20

0)-40
(21+(51-30
110

85

90
100
110
100
130
100
110
80
90
100
100

75
85
85
85
95
85
85
65
80
80
80

0)-40
70

0)-30
70
150
100

100
80

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
,
ns
ns
ns
ns
ns
ns
ns
ns
ns

t Rising edge, ~ Falling edge
Numbers in parentheses are other parameter numbers in this table: their values should be substituted in equations.
All equations'imply DMA default (standard) timing.
Data must be enabled onto data bus when RD is active.
Asterisk (*) before parameter num'ber means the parameter is not illustrated in the AC Timing Diagrams.

335

LHooa3

zao DMA Direct Memory Access

CLK
Ao-A'5

Input
Do-D7 {

Output

--~+---H-~---++-----+---HJ

RD
WR

BUSR

Acting as bus controller (active state)

•

Programming

The Z-80 DMA has two programmable fundamental states .
• an enabled state, in which it can gain control
of the system -buses and direct the transfer
of data between ports, and
• a disabled state, in which it can initiate neither
bus requests nor data transfers. When the
DMA is powered up or reset by any means,
it is automatically placed into the disabled
state.
(1)

Reading

The Read Registers (RRO-RR6) are read by the
CPU by addressing the DMA as an I/O port using
an Input instruction. The readable bytes contain
DMA status, byte-counter values, and port addresses since the last DMA reset. The registers are always read, in a fixed sequence beginning with RRO
and ending with RR6.

•

Read Register 0
D7 D6 D5 D. D3 D2 D, Do
x x 0 0 0 x 0 1

I I I I I I I I I

T

111 t L

TRANSFER
HAS ocurnRED
0=DJIA
READY
ACTIVE
0= INTERRUPT PENDING
O=MATCH FOUND
O=END OF BLOCK
~--------------INTERRUPT PENDING

•

0

Read Register 1

I~~I~I__~I~I~I__~'~~I BYTE COUNTER
(LOW BYTE)

•

Read Register 2

rl---rl---"r-"'1---"--":-1-'1

•

B YT E COUNT E R
(HIGH BYTE)

Read Register 3

:::::J::=:;I~::::::J:':J,:::::::::r:JI PO RT A ADDRES S
-

•

COUNTER (LOW BYTE)

Read Register 4

I 1 1 , 1 1 1

336

STATUS BYTE

PORT A ADDRESS
COUNTER (HIGH BYTE)

Z80 DMA Direct Memory Access

•

LH0083

Read Register 5

•
PORT B ADDRESS
COUNTER (LOW BYTE)

•

D7 D6 D5 D4 D3 D2 Dl Do
I I I I 0 I 0 I 0 I BASE REGISTER
BYTE
O=PORT B IS MEMORY
I=PORT B IS I/O
o =PORT B ADDRESS DECREMENTS
! =PORT B ADDRESS INCREMENTS
o
=PORT B ADDRESS VARIABLE
1
=PORT B ADDRESS FIXED

L0 I

I PORT B ADDRESS
~..J....-I...--I.---l"--"'---'---'---' CO UNTE R (HIG H B YT E)
(2) Writing
Control or command bytes are written into one
or more of the Write Register groups(WRO-WR6)
by first writing to the base register byte in that
group. All groups have base registers and most
groups have additional associated registers. The
associated registers in a group are sequentially
accessed by first writing a byte to the base register
containing register-group identification and pointer bits (1, s) to one or more of that base register's
associated registers.
Write Register 0

D7 D6 D5 D4 D3 D2 D, Do
I 0 I I I I I I I I BASE REGISTER BYTE
DO NOT USE
J1 =TRANSFER

b

0
1 0 =SEARCH
1 1 =SEARCH/TRANSFER
O=PORT B-PORT A
I=PORT A-PORTB

I

I

I

1

I

Read Register 6

•

Write Register 2

rl-"""
I""I,..-r-I;--I-'--;--'--' PORT B VARIABLE
"-T""""'r'---I.---l'-r-ooL-,--'-,.-I-"""'" TIMING BYTE

b

J=CYCLE LENGTH =4
I=CYCLE LENGTH =3
1 O=CYCLE LENGTH=2
1 I=DO NOT USE
O=IORQ ENDS 112 CYCLE EARLY
0= MREQ ENDS 1/2 CYCLE EARLY
0= RD ENDS 1/2 CYCLE EARLY
0= WR ENDS 1/2 CYCLE EARLY

o

•

Write Register 3

D7 D6 D; D4 D, D2 D, Do BASE
1
I J I 0 I 0 I REGISTER
BYTE
DMA ENABLE =
I=STOPON
INTERRUPT ENABLE = 1
MATCH

i

L1 1

I J PORT A STARTING ADDRESS

I

I

1

j

I

I

J

I

J MASK

I

I

I

I

I MATCH
BYTE

(LOW BYTE)

I
I

I
I

•

I

I

I

I

I

I

I

I

I

I

L J PORT A STARTING ADDRESS

I

(HIGH BYTE)

•

Write Register 4

BLOCK LENGTH
(LOW BYTE)

I

J BLOCK LENGTH

I

(HIGH BYTE)

Write Register 1

D7 D6 D5 D, D3 D2 D, Do
I I I I 1 I 0 I 0 I BASE REGISTER BYTE

D7 D6 D5 D4 D3 D2 D, Do
0
1
I I I

I 1 I

I

!=PORT
I=PORT
=PORT A
1 =PORT A
=PORT A
=PORT A

o
1

I

I

I

I

I

I

I

~

o
1
1

I

A IS MEMORY
A IS I/O
ADDRESS DECREMENTS
ADDRESS INCREMENTS
ADDRESS VARIA,BLE
ADDRESS FIXED

J

~?JI1l BV1JABLE

d=CYCLE LENGTH=4
I=CLCLE LENGTH=3
O=CYCLE LENGTH=2
I=DO NOT USE

O=IORQ ENDS 112 CYCLE EARLY
O=MREQ ENDS 112 CYCLE EARLY
O=RD ENDS 112 CYCLE EARLY
0= WR ENDS 112 CYCLE EARLY

BASE
REGISTER
-BYTE

!!

BYTE=
CONTINU OU8= 0
BU RST= 1
DO NOT PROG RAM= 1

1

0
1

I0 I

o

BYTE
(0= COMPARE)

I

I

I

L0 I

I

I

I

j

INTERRU PT
ON R DY=!
STATUS AF FECTS
VE CTOR =1

l

1

I

I

PORT B STARTING
ADDRESS (LOW BYTE)
PORT B STARTING
ADDRESS (HIGH BYTE)

j

INTERRUPT CONTROL BYTE

1-INTERRUPT ON

MATCH
I=IN TERRUPT AT
.EN D OF BLOCK
I=PULSE GENERATED
L ~ 1 J I I I I I PULSE CONTROL
BYTE
INTERRUPT
I I I I I VECTOR
I
I
VECTOR IS AUTOMATICALLY { 0 o = INTERRUPT ON RDY
1
= INTERRUPT ON MATCH
MODIFIED AS SHOWN
0
o = INTERRUPT ON END
ONLY IF" STATUS 1
OF BLOCK
AFFECTS VECTOR" BIT IS SET i
1 = INTERRUPT ON MATCH
AND END OF BLOCK

-----~ ........., - . - - . . - - S H A R P .----.-.-.-.-~

337

Z80 DMA Direct Memory Access

.-..-..-.~..-:
•

LH0083

----.-.---.-.~.-.

Write Register 5
BASE REGISTER

~"""''''''''''r-'-'''''''''''''-=-'''''''''''''''"''''' BYT E

O=READY ACTIVE LOW
I=READY ACTIVE HIGH
O=CE ONLY
1= CE /WAIT MUL TIPLEXED
STOP RESTART ON .END
O=STOP ON END OF BLOCK
I=AUTO REPEAT ON END OF BLOCK

•

Write Register 6
D7 D6 D5 D4 D3 D, D\ Do
1 1 1 1 I. 1 1 1 1 BASE REGISTER BYTE

111

I

I

tit

1

0

0

0

0

0

0

0

1

INTERRUPT LINE RESET, INTERRUPT REQUEST AND BUS REQUEST DISABLE,
INTERNAL READY STATE CLEAR, CE MULTIPLEX DISABLE, AUTOMATIC REPEAT
STOP
PORT A TIMING TO Z80 STANDARD TIMING

CB

0

0

0

PORT B TIMING TO Z80 STANDARD TIMING

CF

0

0

0

1

0

ADDRESS CONTINUE FROM CURRENT VALUE, BYTE COUNTER CLEAR

0

INTERRUPT ENABLE

C3

C7

BOTH PORTS START ADDRESS LOAD, BYTE CONTER CLEAR

D3

1

AB

0

0

AF

0

0

1

A3

0

0

0

0

87

0

0

0

0

1

INTERRUPT CIRCUIT RESET AND DISABLE (SAME AS RET!), INTERNAL READY
STATE CLEAR
DMA ENABLE} EFFECTIVE FOR ALL SECTIONS BUT INTERRUPT.

83

0

0

0

0

0

DMA DISABLE NOT ALL FUNCTIONS RESETTABLE, HOWEVER

A7

0

1

0

0

BF

0

1

B3

0

88

o
o
o

B7
BB

0

1

lOt

0

0

INTERRUPT DISABLE

READ SEQUENCE START FOR 1ST REGISTER DESIGNATED BY READ MASTER
REGISTER
STATUS REGISTER READ SETUP. FROM STATUS REGISTER FOR NEXT READ

0

0

1

0

INTERNAL READY STATE TO BE FORCEDLY CLEAR OF "RDY" PIN (USED FOR
DMA BETWEEN MEMORIES NEEDING NO RDY SIGNAL. NOT OPERATIVE IN "BYTE
MODE")
REINITIALIZE. END - OF - BLOCK BIT CLEAR

o

1

ENABLE AFTER RET!. BUS REQUEST ONLY AFTER RETI EXECUTION

1

0

READ MASK FOLLOWS

tit

tit

r

I

!I

READ MASK (I=ENABLE)

f'----ByTE
STATUS BYTE
COUNTER

'------BYTE
PORT
'-------PORT
'--------PORT
'---'---------PORT

338

(LOW BYTE)
COUNTER (HIGH BYTE)
A ADDRESS (LOW BYTE)
A ADDRESS (HIGH BYTE)
B ADDRESS (LOW BYTE)
B ADDRESS (HIGH BYTE)

Z80 DMA Direct Memory Access

•

Timing
(1)

Inactiye state timing (DMA as CPU
Peripheral)

In its disabled or inactive state, the DMA is
addressed by the CPU as an I/O peripheral for
write and read (control and status) operations.
Write timing is illustrated in Fig. l.
Reading of the DMA's status byte, byte counter
or port address counters is illustrated in Fig. 2.

(2) Active state timing (DMA as BUS
Controller)
( i ) Default read and write cycles
By default, and after reset, the DMA's timing of
read and write operations is exactly the same as
the Z-80 CPU's timing of read and write cycles for
memory and I/O peripherals, with one exception:
during a read cycle, data is latched on the falling
- edge of T3 and held on the data bus across the
boundary between read and write cycles, through
the end of the following write cycle.
Fig. 3 illustrates the timing for memory to-I/O
port transfers and Fig. 4 illustrates I/O-to-memory
transfers. Memory~to-memory and I/O-to-I/O
transfer timings are simply permutations of these
diagrams.
The default timing uses three T -cycles for memory transactions and four T -cycles for I/O transactions, which include one automatically inserted

LH0083

wait cycle between T2 and T3. If the CE/WAIT line
is programmed to act as aWAIT line during the
DMA's active state, it is sampled on the falling edge
of T, for memory transactions and the falling edge
of Tw for I/O transactions. If CE/W AIT is Low
during this time another T -cycle is added, during
which the CE/W AIT line will again be sampled.
The duration of transactions can thus be indefinitely extended.

tr1------

JLFL.JUL

CLOCK

~;RQ
WR

Do-D 7

-- ------

Fig. 1 CPU-DMA write cycle timing

Fig. 2

CPU-DMA read cycle timing

- - - - . - . - . - - - - - S H A R P . - . - . -......... . - . - . _ - 339

LH0083

Z80 DMA Direct Memory Access

_

Memory Read
T,

CLOCK

X

-

Write

T3

roo-

1::.

J

'-

I

IORQ
{

I/O Write
T2
Tw

TJ

X

\

M.REQ

RO

T3

- ~-r-.-rL Il-rLr-r- L
-

Read {

T2

r-

1\

_

r r--

\

WR

I}-

0 0 -0 7

-- ---- 7
- ---- -'

r
\

\..

---- ---- ------ ---- ---

-r
I

-'

,- - - - - ~-\
~----....

Fig. 3 Transfer from memory to 110 device

I/O Read
T,

CLOCK

T2

- h-~

- IX

Tw

Memory Write - T3

-r-n-

TJ

T2

T3

n-~r-rL

X

lA

IORQ

\

I

RO

\

I

r--

Read {

J-

CE/WAIT

I

\

MREQ
Write { _
WR

'L W
-- ---- ----

-- ---

Fig.4

J \: ----

----

T t

----

--f----

Transfer from I/O device to memory

-----.-------SHARP_--..-.---~.-..-..--- ........

340

Z80 DMA Direct Memory Access

(ii) Variable cycle and edge timing
The
Z-80 DMA's default operation-cycle length for the
source (read) port and destination (write) port can
be 'independently programmed_ This variable-cycle
feature allows read or write cycles consisting of
two, three or four T-cycles (more if Wait cycles
are inserted), thereby increasing or decreasing the
speed of all signals generated by the DMA. ~ddi­
tion, the trailing edges of the IQRQ, MREQ, RD and
WR signals can be independently terminated
one-half cycle early. Fig. 5 illustrates this.
In the variable-cycle mode, unlike default timing,
IORQ c~mes active one-half cycle before MREQ,
RD and WR. CE/W AlT can be used to extend only
the 3 or 4 T-cycle variable memory cycles and
only the 4-cycle variable I/O cycle. The CE/W AIT
line is sampled at the falling edge of T, for 3-or
4-cycle memory cycles, and at the falling edge of
T3 for 4-cycle I/O cycles.
During transfers, data is latched..2!l the clock
edge causing the rising edge of RD and held
through the end of the write cycle.
(iii) Bus requests
Fig. 6 illustrates the bus
request and acceptance timing. The RDY line,
which may be programmed active High or Low, is
sampled on every rising edge of CLK.
If it is found to be active, and if the bus is not in
use by any other device, the following rising edge
of CLK drives BUSREQ low. After receiving BUSREQ the CPU acknowledges on the BAI input
either directly or through a multiple-DMA daisy
chain. When a Low is detected on BAI for two consecutive rising edges of CLK, the DMA will begin
transferring data on the next rising edge of CLK.
(iv) Bus release byte-at-a-time
In Byte at
a Time mode, BUSREQ is brought High on the rising edge of CLK prior to the end of each read cycle
(search-only) or write cycle (transfer and transferl
search) as illustrated in Fig. 7. This is done regardless of the state of RDY.
The next bus request fo!:_.!!!e next byte will come
after both BUSREQ and BAI have returned High.
(v) Bus release at end of block
In Burst
and Continuous modes, an end of block causes
BUSREQ to go High usually on the same rising
edge of CLK in which the DMA completes the
transfer of the data block (Fig. 8). The last byte in
the block is transferred even if RDY goes inactive
before completion of the last byte transfer.
(Vi) Bus release on not ready
In Burst
mode, when RDY goes inactive it causes BUSREQ
to go High on the next rising edge of CLK after the
completion of its current byte operation (Fig. 9).
The action on BUSREQ is thus somewhat delayed

LH0083

from action on the RDY line. The DMA always
completes its current byte operation in an orderly
fashion before releasing the bus.
By contrast, BUSREQ is not released in Continuous mode when RDY goes inactive.
Instead, the DMA idles after completing the current
byte operation, awaiting an active RDY again.
(vii) Bus release on match
If the DMA is
programmed to stop on match in Burst or Continuous modes, a match causes BUSREQ to go inactive on the next DMA operation, i.e., at the end of
the next read in a search or at the end of the following write in a transfer (Fig. 10). Due to the
pipelining scheme, matches are determined while
the next DMA read or write is being performed.
The RDY line can go inactive after the matching
operation begins without affecting this bus-release
timing.
(Viii) Interrupts
Timings for interrupt acknowledge and return from interrupt are the same
as timings for these in other Z-80 peripherals. (Refer to the Z80 PIO.)
Interrupt on RDY (interrupt before requesting
bus) does not directly affect the BUSREQ line. Instead, the interrupt service routine must handle
this by issuing the following commands.
a. Enable after return from interrupt (RETI)
(Command code 87H)
b. Enable DMA (Command code 87H)
c. An RETI instruction

'-~"""""~-'---SHARP-'-'--'--''----

341

LH0083

Z80 DMA Direct Memory Access

CLOCK

Ao- At5
IORQ

\I.....,---_~

M.REQ

~,-

- -

-"r--·..I1'- __ _

-..J\.---__
f-'

I

RD, WR

T-"7--,--T

I
,
.L_..J_

,

I

L._.L_

"7--,

I

~EARLY
CYCLE
END

2 CYCtE 3 !YCLE
EARLY END EARLY END

Fig. 5 Variable cycle and edge timing

CLOCK

INACTIVE

-----------~-__Ih

BUSRQ

______ J

,

,

BAI

_ _ .I

DMA
INACTIVE

342

Fig. 6

Bus request and acknowledgement

Fig. 7

Bus clear (byte mode)

DMA
ACTIVE

LH0083

Z80 DMA Direct Memory Access

CLOCK

-ILrLf

ACTIVE
RDY INACTIVE

BYTE
OPERA TION-----;......-DMA
f-- LAST
IN BLOCK

Fig. 8

End of block bus clear (burst, continuous mode)

ACTIVE
RDY INACTIVE

~.~---T-------L CURRENT BYTE
,OPERATION

Fig. 9

RDY

INACTIVE

DMA INACTIVE

No READY bus clear (burst mode)

INACTIVE

BUSRQ --'I'.------~/'f-----,I'B~Y~T~E~n~+~l'R~E~A~D~~
BYTE n - + I N MATCH FOUN
READ IN
ON BYTE n

Fig. 10

Mating bus clear (burst, continuous mode)

----.-------------SHARP - - - - - - - - - - - - - - - - 343

LH0084/5/617

Z80 SIO Serial Input/Output Controller

LH0084/LH0085
LH0086/LH0087
•

Z80 SIO Serial
Input/Output Controller
•

Description

The LH0084/85/86/87,.280 S10 (280 S10 for
short below) is a dual-channel multi-function
peripheral component designed to satisfy a wide
variety of serial data communications requirements
in microcomputer systems. Its basic function is a
serial-to-parallel, parallel-to-serial converter /
controller, but-within that role-it is configurable
by systems software so its "personality" can. be
optimized for a given serial data communications
application.
The 280 SIO is capable of handling asynchronous and synchronous byte-oriented protocols
such as IBM Bisync, and synchronous bit-oriented
protocols such as HDLC and IBM SDLC. This versatile device can also be used to support virtually
any other serial protocol fot applications other
than data communications (cassette or floppy disk
interfaces, for example).
The 280 SIO can generate and check CRC codes
in any synchronous mode and can be programmed
to check data integrity in various modes. The device also has facilities for modem controls in both
channels. In applications where these controls are
not needed, the modem controls can be used for
LH0087M/LH0087 AM

Pin Connections
LH0084/LH0084A/LH00848

o

i
i

LHOO85/LHOO85A/
LHOO85B
INT

5

lEO

7

36

32

W/RDYA
SYNCA
RxDA
TxCA
TxDA
DTkA
RTSA
CTSA
DCDA
CLOCK

31
))

IORQ
CE

. SYNCB
RxDB
. RxCB
•. TxCB
.•. TxDB

RD
GND
W/RDYB
SYNCB LHOO86/LHOO86A!
RxDB LHOO86B
RxTxCB
.. RxCB
TxDB
.,
TxCB
DTRB
...
TxDB
RTSB
•..• DTRB
CTSB

~DB

CCDB
RESET

LH0087U1LH0087AUiLH00878U

~~M-.l? ~ ~ w~1::t:i
I.....~ oooo~ooo81:->

-<
b
1°
I.....EZr-I.n~,...;Zo~"",!.O§3
OOOOc.!lOOOO .....

34

SYNCA

40

16

SYNCB

SYNCB

Top View

*The GND pins must be connected to the GND level.
~~---""""'---SHARP ~.-..r _ _ _ _ _ _ _ .-_~'-:-'

344

LHOOS4/5/6/7

ZSO SIO Serial Input/Output Controller

general-purpose 110.
The Z80 SIO has six types as below according
it's system clock and bonding option. The Z80A
SIO and the Z80B SIO are a high speed version
which can operate at the 4MHz and 6MHz system
clock, respectively.
• LH0084 280 SIO/O
• LH0084B 280B SIO/O
• LH0085B 280B SIO/l
• LH0085 280 SIOI1
• LH0086B 280B SI0/2
• LH0086 280 $10/2
• LH0087 280 SIO
• LH0087B 280B SIO
• LH0084A 280A SIO/O
• LH0085A 280A SIOI1
• LH0086A 280A SI0/2
• LH0087 A 280A SIO

•

Features

1. N-channel silicon-gate process
2. Single + 5V power supply and single phase
clock
3. Two independent full duplex channels
4. Data rates: 0 to 500K bits/second (at 2.5 MHz
system clock)
: 0 to 800K bits/second (at 4MHz system clock)
: 0 to 1200K bits/second (at 6MHz system clock)
5. Asynchronous operation
• 5, 6, 7 or 8 bits/character
• 1, 17f or 2 stop bits/character
• Even, odd or no parity
•

• Xl, X16, X32 and X64 clock modes
• Break generation and detection
• Parity, Overrun and Framing error detec·
tion
6. Binary synchronous operation
• Internal or external character synchroniza·
tion
• One or two Sync characters in separate registers
• Automatic Sync character insertion
• CRC generation and checking
7. HDLC or IBM SDLC operation
• Abort sequence generation and detection
• Automatic zero insertion and detection
• Automatic flag insertion
• Address field recognition
• I -field residue handling
• Valid receive messages protected from overrun
• CRC generation and checking
8. Vectored daisy chain priority interrupt logic
9. CRC-16 or CRC-CCITT block check
10. Separate modem control inputs and outputs for
both channels
11. Modem status can be monitored
12. 40-pin DIP (DIP40-P-600)
44-pin QFP (QFP44-P-IOIOA)
44-pin QFJ (QFJ44-P-S650)

Ordering Information
Product
Clock frequency

Model No.

X:

H:

2S0 SIO
2.5MHz
LHOOSX
LHOOSXH
LHOOS7M
LHOOS7U

2S0A SIO
4MHz
LHOOSXA
LHOOSXAH
LHOOS7AM
LHOOS7AU

·2S0B SIO
6MHz
LHOOSXB

LHOOS7BU

Package
40-pin DIP
44-pin QFP
44-pin QFJ

Operating
temperature
O°C to +70°C
-20°C to+S5°C
O°C to +60°C
O°C to+70°C

It is the bonding option to select one of SIO/G, SIO/l and SIO/2 on 40-pin DIP.
X=4: SIO/O
X=5: SIO/l
X=6: SIOI2
H affix indicates a wide temperature spec, packaged in 4G-pin DIP .

.--~~--------SHARP-----------~--~

345

LH0084/S16/7

Z80 SIO$erial Input/Output Controller

•

Block Diagram

A
Internal
Control
Logi~

14

010

Channel A
Control alld
Status
Registers

11

1

System Data Bus

18
~

6

.e-"
"
'..:;"""

1

0

Request To
Send B
Clear To Send B
Data Terminal
Ready B
22 Data Carrier
Detect B

'"

Chip Enable

"

CO
::J
0..
U

Machine Cycle 1
I/O Request
Read
Command/ Dat a
Select
Channel Select

Channel B
Control and
Status
Registers

Interrupt
Control
Logic

Receive Data A
Receive Clock A
Transmit Data A
Transmit Clock A
Wait/Ready A
Extarnal Char actor
Synchronization A
Request To
Send A
Clear To Send A
Data Terminal
Ready A
Data Carrier
Detect A

4 Receive Data B

it Receive Clock B
{¥ Transmit Data B
B

t. Transmit Clock B
30 Wait/Ready B
+;: External Char actor

. Synchronization B

Sonding option is as below

____.aaJ SYNCB
-""---f2i8il RxDB
_---fl!!l RxTxCB
.t.i

---o'{"l!'!&
.. l'

TxDB
---i.o(~·j..m
•. · DTRB

SIO/O

----o{il!'l SYNCB

t.i....!ft.
----<'o:!fJi·

Rx DB

_ _«t.i,."~').

RxDB

----min RxCB

_---f~ro

RxCB

---(\1lj
•.~
...',

--,fI
iI' lm

TxCB
TxDB

--~]iilTxDB

--~I!!n

SIO/l

-----<:::""----:;:><;:-------,

Hunt Mode (Bisync)

......-_..... CRC Result
Fig. 1 Transmit and receive data path

•

Programming

The system program first issues a series of com·
mands that initialize the basic mode of operation
and then other commands that qualify conditions
within the selected mode.
Both channels contain registers that must be
programmed via the system program prior to operation.
(1) Read Registers
The SIO contains three read registers for Channel B and three read registers for Channel A
(RRO-RR2) that can be read to obtain the status information. The status information includes error
conditions, interrupt vector and standard communications-interface signals

• Read Register 1 (RR 1)
The RRl contains the status bits for specific

receiving coditions as well as the one· field fraction
codes for the SDLC receive mode.

• Read Register 2 (RR 2)
D1
V1

Ds
Vs

Ds
Vs

D.
V.

D3
V3

D2
V2

DI
VI

Do
Vo

y

Valiable if .. status affects
vector" is programmed

• Read Register 0 (RR 0)
D6
Tx
Break
/abort underrun
/EOM

:·1

~

Ds
CTS

Sync
/hunt

D3
DCD

Do
INT RHhar·
Tx
buffer pending acter
empty (ch.A) avail·
only
able

(2) Write Registers
The SIO contains eight write registers for Channel B and eight write registers for Channel A
(WRO-WR7) that are programmed separately to
configure the functional personality of the channels.

~.-.,.-.-..;.-----'-SHARP·.-~-~-~~~

~

LH0084/S/S17

280 SIOSerial Input/Output Controller

• Write Register 0 (WR 0)
D7

D6

CRC
reset
code

CRC

reset

1

0

code

D2

D5

Commaod Command Command Pointer
bit
bit
bit
bit

2

1

2

0

,

Do
Pointer Pointer
bit
bit

1

0

)'

V

Control words

• Write. Register 4 (WR 4)
The WR4 has the bits control both receivers and
transmitters.
In initializing for transmitting and receiving,
these bits must be set up before the WR1, WR3,
WR5, WR6, and WR7.

Register pointers

• Write Register 1 (WR 1)
Ds

Do

Ds

Waitl Waitl Waitl Receive Receive Status
ready ready ready inter- interrupt
enable function onR/T rupt
mode 1 mode 0

Tx
Ext
affects INT
INT
vector enable enable

• Write Register 2 (WR 2)
The WR2 contains the Interrupt vector for both
channels and is only in the Channel B. When the
status affected vector (WR1, D2) is 1, the vector
from the SIO during the interrupt acknowledge cycle varies (V3 - V,) depending on the interrupt conditions. The WR2 contents do not vary then.

v,

Do

Ds

Vs

Vs

V4

V3

D,

Do

V2

Vo

• Write Register 3 (WR 3)
The WR 3 contains the bits and parameters to
control the receivers.
D,
Ds
Ds
Do
Rx bits Rx bits Auto
charchar- enable
acter
acter
1_
0

Enter
hunt
phase

• Write Register 5 (WR 5)
The WR5 contains the bits (except for D2) to
control the transmitters.

DTR

Ds
D6
Tx bits Tx bits Send
I char- Ichar- break

acter
1

D,
Tx
CRC16
enable ISDLC

acter

Do
RTS

Tx
CRC
enable

0

• Write Register 6 (WR 6)

• Write ReJ)ister 7 (WR 7)

Address Sync
Rx
Rx
CRC search charac- enable
enable mode ter load
inhibit

--'--''--~--SHARP----------~'"''''''''''''''''''

352

LH0084/S/617

....... - . - . - . -....

Z80 SIO Serial Input/Output Controller

.-.-.-.-.-.-.-.-.-.-.-.I,

•

ated by a Z-80 CPU output instruction to write a
data or control byte into the SIO.

Timing
(1)

Read cycle

(3) Interrupt cycle
The interrupt-acknowledging and return-from-interrupt cycles are of the same timing as for
other Z80 peripherals. (Refer to the Z80 PIa.)

The timing signals generated by a Z-80 CPU input instruction to read a data or status byte from
the SIO are illustrated in Fig. 2.
(2) Write cycle
Fig. 3 illustrates the timing and data signals gener-

CLOCK

Channel address

CE

IORQ
RD
Ml

(

DATA
Fig. 2

T,

Output

)

Read cycle timing

T,

Tw

~

T,

T3

CLOCK

Channel address

CE

IORQ
RD
Ml

X

DATA
Fig. 3

Input

X

Write cycle timing

....-. ........ ---~-----SHARP~------353

. LH8530

Z8530 SCC Serial Communications Controller

LH8530
•

Z8530™ SCC Serial Communications Controller

Description·

The LH8530 Z8530 SCC Serial CommuniCations
Controller is a dual-channel, multi-protocol data
communications peripheral designed for use with
conventio~al non-multiplexed buses_ The LH8530
functions as a serial-to-parallel, parallel-to-serial
converter controller_ The L1I8530 can be softwareconfigured to satisfy a wide variety of serial communications applications_ The device contains a
variety of new, sophisticated internal functions including on-chip baud rate generators, Digital
Phase- Locked Loops, and crystal oscillators that
dramatically reduce the need for external logic_
The LH8530 handles asynchronous formats,
Synchronous byte-oriented protocols such as IBM
Bisync, and Synchronous bit-oriented protocols
such as HDLC and IBM SDLC_ This versatile device supports virtually any serial date transfer application (cassette, disk tape drives, etc)_
The device can generate and check CRC codes in
any Synchronous mode and can be programmed to
check data integrity in various modes_ The
LH8530 also has facilities for modem controls in
both channels_ In applications where these controls
are not needed, the modem controls can be used for
general-purpose I/O_
The daisy-chain interrupt hierarchy is also supported by the LH8530_.
The LH8530A Z8530A SCC is the high speed
version which can operate at 6MHz system clock_

•

Features

•

Pin Connections
LH8530P/LH8530AP

----,

o

D2

D.
D,;
RD
WR

AlB
INTACK

CE

8

D/e
GND

W/REQA

W/REQB

SYNCA 11
RTxCA

SYNCB

RxDA

RTxCB

TRxCA

RxDB

TxDA

TRxCB

DTR/REQA

TxDB

RTSA

DTR/RE(Hl

CTSA

RTSB

DCDA

CTSB

PCLK

DCDB

LH8530U/LH8530AU

lEO
lEI
INTACK

7

8
9

10 Two independent, 0 to 105M bit/second, fullduplex channels, each with a separate crystal
oscillator, baud rate generator, and Digital
Phase-Locked Loop for clock recovery_
2_ Multi-protocol operation under program control; programmable for NRZ, NRZI, or FM data
encoding_
3_ Asychronou~. mode with five to eight bits and
one, one and one-half, or two stop bits per
character; programmable clock factor, break
detection and generation; parity, overrun, and
framing error detection_

------.-.~----SHARP ~~..--..r

354

Do

Top View

_

___..~_.-....,

Z8530 SCC Serial Communications Controller

4, Synchronous mode with internal or external
character synchronization on one or two synchronous characters and CRC generation and
checking with CRC-16 or CRC-CCITT preset
to either Is or Os.
5. SOLC/HOLC mode with comprehensive framelevel control, automatic zero insertion and de-

•

LH8530

letion. I-field residue handling, abort generation and detection, CRC generation and checking, and SOLC Loop mode operation.
6. Local Loopback and Auto Echo modes.
7. 40-pin DIP (DIP40-P-600)
44-pin QFJ (QFJ44-P-S650)

Block Diagram

Baud Rate
Generator
A

1l

Synchronization

Wait/Request
16 Data Terminal
Ready /Request
17 Request To Send

'--_ _ _....J-'"""'"\IO

Data Bus

23 Request To Send

Dat'a Terminal
Ready/Request
30 Wait/Request

24

Synchronization

Baud Rate
Generator
B

Channel Clock
Serial Data

....

"<>

U
Pin numbers apply to 40-pin DIP.

•

Ordering Information

LH8530 X

X

Package
P: 40-pin DIP (DIP40-P-6()O)
U: 44-pin QFJ (QFJ44-P-S650)
. Clock frequency
,
Blank: 4MHz
A: 6MHz
L----ModeI No.
[

~55

Z8530 SCC Serial Communications Controller

•

LH8530

Pin Description
Pin
-

Meaning
Channel AI
Channel B select

Function

I/O
I

Channel select signal.

Chip enable

I

Active low. Enables the CPU to transmit and receive
command and data when low.

Clear to send

I

Active low. Enables the respective transmitters.

D/C

Datal control select

I

This signal defines the type of information on the data
bus. High means data; Low indicates a command.

--

DCDA
DCDB

Data carrier detect

I

Active low. Enables the respective receivers.

Do-D7

Data bus

AlB
-

CE

CTSA
CTSB

--

Bidirectional
3-state

INTACK

Interrupt acknowledge

I

RD
RXDA
RXDB
RTXCA
RTXCB
RTSA
-RTSB
SYNCA
--SYNCB
TXDA
TXDB
TRXCA
TRXCB
WR

Read

I

Active low. These outputs follow the state programmed
into the DTR bit.
Active high. lEI is used to form a daisy chain that determines the interrupt priority order.
Active high. lEO is used to form a daisy chain that determines the interrupt priority order.
Active low, open-drain. Indicates an interrupt request to
the CPU.
Active low. This signal indicates an active interrupt
acknowledge cycle.
Active low. This signal indicates a read operation.

Recei ve data

I

Active high. These are receive data lines.

Receive/transmit clocks

I

Active low. These are communication clock lines.

Request to send

0

Active low. Goes high after the transmitter is empty.

Synchronization

110

DTR/REQA

Data terminal

DTR/REQB

ready/request

0

lEI

Interrupt enable input

I

lEO

Interrupt enable output

0

-

INT

---

Interrupt request

Open-drain

Active low. Indicates that a synchronization pattern has
been recognized.

0

Transmit data

Active high. These are transmit data lines.

110

Transmit/receive clocks

These are communication clocks.

I

Write

---

W/REQA

---

W/REQB

PCLK

•

System data bus.

Open-drain

Waitlrequest
Clock

Single-phase clock. It does not have to be the CPU clock.

I

+5V

Absolute Maximum Ratings

Parameter
Input voltage
Output voltage

Symbol
VIN
V OUT

Operating temperature

Topr

Storage temperature

Tstg

Ratings
-0.3 to +7.0
-0.3 to +7.0

o to

Active low. This signal indicates a write operation.
Active low. Operate as request lines when the DMAis
the bus master or as wait lines when the CPU is the bus
master.

+70

-65 to +150

Unit
V
V

From output
under test o-_-N~~

2.2kO

+5V
From output
under test

°C

.

~2'2kO
.

l.50PF

"C
Standard test load

Open-drain test load

.-..--.'---------SHARP----------356

28530 SCC Serial Communications Controller

LH8530

DC Characteristics

•

(Vcc=5V±5%, Ta=O to +70"(; )

Parameter
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current

Symbol

Current consumption

Icc

•

VIH
VIL
VOH
VOL
IIiL I
I 10L I

Conditions

MIN.
2
-0.3

10H= -250 pA
IOL=+2mA
0.4 ::;;; VIN ::;;; 2.4V
0.4 ::;;; VOUT ::;;; 2.4V
LH8530
LH8530A

Symbol

Conditions

CiN
COUT

Unmeasured Pins Returned to Ground

MIN.

CliO

AC Characteristics
CPU interface timing, interrupt timing, and interrupt acknowledge timing

No.

Symbol

Parameter

1

TwPCl
TwPCh
TfPC
TrPC
TcPC
TsA(WR)
ThA(WR)
TsA(RD)
ThA(RD)
TsIA(PC)
TsIAi(WR)
ThIA(WR)
TsIAi(RD)
ThIA(RD)
ThIA(PC)
TsCEl(WR)
ThCE(WR)
TsCEh(WR)
TsCEl(RD)
ThCE(RD)

PCLK low width
PCLK high width
PCLK fall time
PCLK rise time
PCLK cycle time
Address to WR ~ setup time
Address to WR t hold time
Address to RD ~ setup time
Address to RD t hold time
INTACK to PCLK t setup time
INT ACK to WR ~ setup time
INT ACK to WR t hold time
INT ACK to RD ~ setup time
INT ACK to RD t hold time
INT ACK to PCLK t hold time
CE low to WR ~ setup time
CE to WR t hold time
CE high to WR ~ setup time
CE low to RD ~ setup time
CE to RD t hold time
CE high to RD ~ setup time
RD low width
RD ~ to read data active delay
RD t to read data not valid delay
RD ~ to read data valid delay
RD t to read data float delay
Address required valid to read data valid delay
WR low width
Write data to WR ~ setup time

11

TsCEh(RD)
TwRDl
TdRD(DRA)
TdRDr(DR)
TdRDf(DR)
TdRD(DRz)
TdA(DR)
TwWRI
TsDW(WR)

pA
mA

(f=lMHz, Ta=O to +70'C)

•

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

V
V
V
V
p.A

0.4
10
10
250
280

(1)

2
3
4
5
6
7
8
9
10

Unit

2.4

CapaCitance
Parameter
Input capacitance
Output capacitance
Bidirectional
capacitance

MAX.
Vcc+0.3
0.8

LH8530
MIN.
MAX.
105
2000
105
2000
20
20
250 4000
80
0
80
0
0
200

Unit
pF
pF

20

pF

LH8530A
MIN.
MAX.
70 1000
70
1000
10
15
165
2000
80
0
80
0
0
160

0
200

0
160

0
100

0
100
0
0
70
0
0
70
250
0
0

0
0
100
0
0
100
390
0
0

MAX.
10
15

250
70
590

180
45
420

390

250

0

0

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Note

1
1

1
1
1
1

2

~"""""'-'---"--SHARP-'----'---

357

LH8530

Z8530 SCC Serial Communications Controller

No.

Symbol

30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

ThDW(WR)
TdWR(W)
TdRD(W)
TdWRf(REQ)
TdRDf(REQ)
TdWRr(REQ)
TdRDr(REQ)
TdPC(INT)
TdIAi(RD)
TwRDA
TdRDA(DR)
TsIEI(RDA)
ThIEI(RDA)
TdIEI(IEO)
TdPC(IEO)
TdRDA(lNT)
TdRD(WRQ)
TdWRQ(RD)
TwRES
Trc

48
49
Note
Note
Note
Note

1:

2:
3:
4:

Note 5:

LH8530
MIN.
MAX.
0
240

Parameter
Write data to WR t hold time
WR ~ to wait valid delay
RD ~ to wait valid delay
WR ~ to W IREQ not valid delay
RD ~ to W IREQ not valid delay
WR t to DTR/REQ not valid delay
RD t to DTR/REQ not valid delay
PCLK ~ to INT valid delay
INT ACK to RD ~ (acknowledge) delay
RD(acknowledge) width
RD ~ (acknowledge) to read data valid delay
lEI to RD ~ (acknowledge) setup time
IEI to RD t (acknowledge) hold time
IEI to lEO delay time
PCLK t to IEO delay
RD ~ to INT inactive delay
RD t to WR ~ delay for no reset
WR t to RD ~ delay for no reset
WR and RD coincident low for reset
Valid access recovery time

LH8530A
MIN.
MAX.
0

240
240
240

200
200
200
200

5TcPC+300
5TcPct300

5TcPC+250
5Tcpc+250

500

500

285

250
190

120
0

180
100
0
100

120
250
500

250
500

30
30
250

15
30
250

6TcPC+200

6TcPC+ 130

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Note

4
4

4
5

4

3

Parameter does not apply to Interrupt Acknowledge transactions.
Float delay is defined as the time required for a ± O.5V change in the output with a maximum DC load and minimum AC load.
Parameter applies only between transactions involving the SCC.
Open·drain output. measured with open· drain test load.
Parameter is system dependent. For any SCC in the daisy chain, TdlAi (RD) must be greater than the sum of TdPC (lEO) for the
highest priority device in the daisy chain, TsIEI (RDA) for the SCC, and TdlEif (lEO) for each device separating them in the daisy
chain.

PCLK
A/B,D/C-J'~~+-~__~__~__~______~~~~~~______
INTACK

WR _ _

~~~~=$~~~~~____~~

Do-D7(WRITE) ________1r.~~~~==~~r_--+_r_------------

W/REQ (WAIT)
W/REQ (REQUEST)
DTR/REQ (REQUEST)

--I~~

----------------~----~--~~

Read and write timing
--------------~-SHARP_--,------.-----

358

LH8530

Z8530 SCC Serial Communications Controller

PCLK
INTACK ________~~:=:!==~------~~~::~:::::
RO
0 0 -07

---t-~~gH;t--

IEI __~~~--~~~~~--------~"~------lEO ______,.".....

INT ________________________- - J

Interrupt acknowledge timing

Reset timing

CE
RD

or

---./,..--------15 \1------.\

~C·~-@~~~j---

WR~

\~____-J~l

,~._______

Cycle timing

(2) System timing
No.

Symbol

1
2
3
4
5.
6
7
8

TdRxC(REQ)
TdRxC(W)
TdRxC(SY)
TdRxC(INT)
TdTxC(REQ)
TdTxC(W)
TdTxC(DRQ)
TdTxC(INl')
TdSx(INT)
TdExT(INT)

9
10

Parameter
RxC t to W IREQ valid delay
RxC t to wait inactive delay
RxC t to SYNC valid delay
RxC t to INT valid delay
TxC ! to W IREQ valid delay
TxC ! to wait inactive delay
TxC l to DTR/REQ valid delay
TxC ! to INT valid delay
SYNC transition to INT valid delay
DCD or CTS transition to INT valid delay

LH8530
MIN. ·MAX.
8
12
8
12
4
7
10
16
5
8
5
8
4
7
6
10
2
6
2
6

LH8530A
MIN.
MAX.
8
12
8
12
4
7
10
16
8
5
5
8
4
7
6
10
2
6
2
6

Unit

Note

TcPC
TcPC
TcPC
TcPC
TcPC
TcPC
TcPC
TcPC
TcPC
TcPC

2
1,2
2
1,2
3
1,3
3
1,3
1
1

Note 1: Open·drain output, measured with open·drain test load.
Note 2: RxC is RTxC or TRxC, whichever is supplying the receive clock.
Note 3: TxC is TRxC or RTxC. whichever is supplying the transmit clock.

359

Z8530 SCC Serial Communications Controller

LH8530

RTxC, TRxC (RECEIVE)
W/REQ (REQUEST)
W/REQ (WAIT) ____________

~~~~-J

SYNC (OUTPUT)
INT
RTxC, TRxC (TRANSMIT)
W/REQ (REQUEST)
W/REQ(WAIT)

-------------+--~~Jl

DTR/REQ(REQUEST)

§

CTS, DCD,RI
SYNC (INPUT)
INT

.

------------~~~~_______________
System timing

(3) General timing
No.

Symbol

1
2
3
4

TdPC(REQ)
TdPC(W)
TsRXC(PC)
TsRXD(RXCr)
ThRXD(RXCr)
TsRXD(RXCf)
ThRXD(RXCf)
TsSY(RXC)
ThSY(RXC)
TsTXC(PC)
TdTXCf(TXD)
TdTXCr(TXD)
TdTXD(TRX)
TwRTXh
TwRTXl
TcRTX
TcRTXX
TwTRXh
TwTRXI
TcTRX
TwEXT
TwSY

5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20
21
22

Parameter
PCLK ~ to W IREQ valid delay
PCLK ~ to wait inactive delay
RxC t to PCLK t setup time (PCLK 7 4 case only)
RxD to RxC t setup time (Xl mode)
RxD to RxC t hold time (Xl mode)
RxD to RxC ~ setup tillie (Xl mode)
RxD to RxC ~ hold time (Xl mode)
SYNC to RxC t setup time
SYNC to RxC t hold time
TxC ~ to PCLK t setup time
TxC ~ to TxD delay (Xl mode)
TxC t to TxD delay (Xl mode)
TxD to TRxC delay (send clock echo)
RTxC high width
RTxC low width
RTxC cycle time
Crystal oscillator period
TRxC high width
TRxC low width
TRxC cycle time
DCD or CTS pulse width
SYNC pulse width

LH8530
MIN.
MAX.
250
350
80 TwPCl
0
150

LH8530A
MIN.
MAX.
250
350
70 TwPCl

0
150
-200

0
150
0
150
-200

3TcPCt200
0

3TcPCt200
0
300
300
200

180
180
400
250
180
180
400
200
200

1000

300
300
200
180
180
400
250
180
180
400
200
200

1000

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Note

1,4
1
1
1,5
1,5
1
1
2,4
2
2,5
6
6
6
3
3
6
6

.-.---.----SHARP-.------~---

360

Z8530 SCC Serial Communications Controller

LH8530

Note 1:

RxC is RTxC or TRxC, whichever is supplying the receive clock.

Note 2:

TxC is TRxC or RTxC, whichever is supplying the transmit clock.

Note 3:

Both RTxC and SYNC have 30 pF capacitors to ground connected to them.

Note 4:

Parameter applies only if the data rate is one· fourth the PCLK rate. In all other cases, no phase relationship between RxC and

Note 5:

Parameter applies only to FM encoding/decoding.

Note 6:

Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to chip PCLK

PCLK or TxC and PCLK is required.

requirements.

PCLK
W /REQ (REQUEST)

W/REQ (WAIT) _ _ _ _ _~--1-------...I
RTxC, TRxC (RECEIVE) _____-=--'I
RxD ____~,~~-~~--~~--~~--------

SYNC(EXTERNAL) ____~~__~_+------~---------------------

General timing

----...-------~-SHARP

---------------361

Z8530 SCC Serial Communications Controller

Data Communications Capabilities

•

The LH8530 provides two independent fullduplex
channels programmable for use in any common
Asynchronous or Synchronous data communication
protocol. Fig. 1 illustrates these protocols.

START
PARITY

1

~1TOP

lli&ilJ

':":M-:-A"'"R""KI"""N""'G""l@fill j ~r-DA""T""'A
rT,T'lj
LINE
ASYNCHRONOUS
I SYNclDATAI

::

LH8530

first secondary station by the same process. Any
secondary stations without messages to send merely
echo the incoming messages and are prohibited from
placing messages on the loop (except' upon recognizing an EOP).
SDLC Loop mode is a programmable option in the
LH8530. NRZ, NRZI, and FM coding may all be used
in SDLC Loop mode.

--

Ii

CONTROLLER

IDATAI CRC! I CRc,1

~__~__, -__~MrO~N~OSYNC

I SYNclSYNC IDATAl

;;

IDATAI CRC! I CRc,1

SIGNAL~YNC

,

~r:-'I~D~AT~A~I~C~R~C'd~C~R~C,1I

EXTERNAL SYNC

1r.:,F:;-L-:-AG~IAD:-::D""RE::-::-ss!""':i~RM.I CRc!1 CRC21FLAGI
SDLC/HDLC/X.25

Fig. 1

Some see protocols
Fig. 2

•

An SDLe loop

SDLC Loop Mode

The LH8530 supports SDLC Loop mode in addi· '
tion to normal SDLC. In an SDLC Loop, there is a
primary controller station that manages the message
traffic flow on the loop and any number of secondary
stations. In SDLC Loop mode, the LH8530 performs the functions of a secondary station while an
LH8530 operating in regular SDLC mode can act as
<:;
a controller (Fig. 2).
A secondary station in an SDLC Loop is alway
listening to the messages being sent around the loop,
and in fact must pass these messages to the rest of
the loop by retransmitting them with a one-bit-time
delay. The secondary station can place its own message on the loop only at specific times. The controller signals' that secondary stations may transmit
messages by sending a special character, called an
EOP (End Of Poll), around the loop. The EOP character is the bit pattern 11111110. Because of zero
insertion during messages, this bit pattern is unique
and easily recognized.
When a secondary station has a message to transmit and recognizes an EOP on the line, it changes
the last binary 1 of the EOP to a 0 before transmission. This has the effect of turning the EOP
into a flag sequence. The secondary station now
places its message on the loop and terminates' the
message with an EOP. Any secondary stations
further down the loop with messages to transmit can
then append their messages to the message of the

•

Data Encoding

The LH8530 may be programmed to encode and
decode the serial data in four different ways
(Fig. 3). In NRZ encoding, a 1 is represented by a
High level and a 0 is represented by a Low level. In
NRZI encoding, a 1 is represented by no change in
level and a 0 is represented by a change in level. In
FM1 (more properly, bi-phase mark), a transition
occurs at the beginning of every bit cell. A 1 is represented by an additional transition at the center of
the bit cell and a 0 is represented by no additional
transition at the center of the bit cell. In FMO (biphase space), a transition occurs at the beginning of
every bit cell. A 0 is represented by an additional
transition at the center of the bit cell; and a 1 is represented by no additional transition at the center of
the bit cell. In addition to these four methods, the
LH8530 can be used to decode Manchester (bi-phase
level) data by using the DPLL in the FM mode and
programming the receiver for NRZ data. Manchester encoding always produces a transition at the
center of the bit cell. If the transition is 0 to 1, the
bit is a O. If the transition is 1 to 0, the bit is a 1.

~'-'--~-------SHARP-'-'--""""",--~

362

- ................

Z8530 SCC Serial Communications Controller

....................................................
DA T A --'~_..:.....""\
NRZ

o

NRZI
FMl

FMO
MAN-

CHESTER
Fig. 3

•

Data encoding methods

Auto Echo and Local Loopback

The LH8530 is capable of automatically echoing
everything it receives. This feature is useful
mainly in Asynchronous modes, but works in Synchronous and SDLC modes as well. In Auto Echo
mode, TxD is RxD. Auto Echo mode can be used
with NRZI or FM encoding with no additional delay, because the data stream is not decoded before
retransmission. In Auto Echo mode, the CTS input is ignored as a transmitter enable (although
transitions on this input can still cause interrupts
if programmed to do so). In this mode, the transmitter is actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT/REQUEST on transmit.
The LH8530 is also capable of local loopback.
In this mode TxD is RxD, just as in Auto Echo
mode. However, in Local Loopback mode, the internal transmit data is tied to the internal receive
data and RxD is ignored (except to be echoed out
via TxD). The CTSand 0C0 inputs are also
ignored as transmit and receive enables. However,
transitions on these inputs can still cause inter·
rupts. Local Loopback works in Asynchronous,
Synchronous and SDLC modes with NRZ, NRZI or
FM coding of the data stream.

•

Baud Rate Generator

Each channel in the LH8530 contains a programmable baud rate generator. Each generator
consists of two 8-bit time constant registers that
form a 16-bit time constant, a 16-bit down counter, and a flip-flop on the output producing a
square wave. On startup, the flip-flop on the output is set in a High state, the value in the time constant register is loaded into the counter, and the
counter starts counting down. The output of the
baud rate generator toggles upon reaching 0, the
value in the time constant register is loaded into
the counter, and the process is repeated. The

LH8530

time constant may be changed at any time , but the
new value does not take effect until the next load
of the counter.
The output of the baud rate generator may be
used as either the transmit clock, the receive clock,
or both. It can also drive the Digital PhaseLocked Loop (see next section).
If the receive clock or transmit clock is not
programmed to come from the TRxC pin, the out·
put of the baud rate generator may be echoed out
via the TRxC pin.
The following formula relates the time constant
to the baud rate (the baud rate is in bits/second
and the BR clock period is in seconds).
baud rate

•

2(time constant + 2) X (BR clock period)

Digital Phase-Locked Loop

The LH8530 contains a Digital Phase-Locked
Loop (DPLL) to recover clock information from a
data stream with NRZI or FM encoding. The
DPLL is driven by a clock that is nominally 32
(NRZI) or 16 (FM) times the data rate. The DPLL
uses this clock, along with the data stream, to construct a clock for the data. This clock may then
be used as the SCC receive clock, the transmit
clock, or both.
For NRZI encoding, the DPLL counts the 32X
clock 60 create nominal bit times. As the 32X
clock is counted, the DPLL is searching the incoming data stream for edges (either 1 to 0 or 0 to 1).
Whenever an edge is detected, the DPLL makes a
count adjustment (during the next counting cycle),
producing a terminal count closer to the center of
the bit cell.
For FM encoding, the DPLL still counts from 0
to 31, but with a cycle corresponding to two bit
times. When the DPLL is locked, the clock edges
in the data stream should occur between counts 15
and 16 and between counts 31 and O. The DPLL
looks for edges only during a time centered on the
15 to 16 counting transition.
The 32X clock for the DPLL can be programmed
to come from either the RTxC input or the output
of the baud rate generator. The DPLL output may
be programmed to be enchoed out of the LH8530
via the TRxC pin (if this pin is not being used as
an input).

.--..-...:..-.---'-~SH~RP--------363

LH8530

Z8530 SCC Serial Communications Controller

Read Registers

•

• Read Register 0

• Read Register 10

Rx CHARACTER
AVAILABLE
ZERO COUNT
Tx BUFFER EMPTY
DCD
SYNC/HUNT
CTS
Tx UNDERRUN /EOM
BREAK/ABORT

• Read Register 1

o
LOOP SENDING

o
TWO CLOCKS MISSING
ONE CLOCK MISSING

• Read Register 12

I 0, I I 0 I D. 103 1O21D. 1Do I
D6

5

[

RESIDUE CODE 0
RESIDUE CODE 1
RESIDUE CODE 2
PARITY ERROR
Rx OVERRUN ERROR
CRC/FRAMING ERROR
END OF FRAME (SDLC)

• .Read Register 2

107 I ~ I ~I

D.

103102I D. 10, I
[

INTERRUPT VECTOR'

LOWER BYTE OF
TIME CONSTANT

• Read Register 13

I 071 10 1D. 103102 I O. 1Do I .
D6

5

[UPPER BYTE OF
TIME CONSTANT

'MODIFIED IN CHANNEL B

• Read Register 3*

CHANNEL B
EXT/STAT IP'
CHANNEL B Tx IP'
CHANNEL B Rx IP' .
CHANNEL A EXT/STAT IP'
CHANNEL A Tx IP'
CHANNEL A Rx IP'

o

• Read Register 15

o
DCDIE
SYNC/HUNT IE
CTS IE
TxUNOERRUN/EOMIE
BREAK/ABORT IE

"ALWAYS 0 IN CHANNEL B

-.-------SHARP-~--------

364

Z8530 SCC Serial Communications Controller

LH8530

Write Registers

•

• Write Register 0
D7

D6

D5

D.

D3

• Write Register 2
D2

D1

Do

0
0
0
0
1
1
1
1
0
0
0
0
1

0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1

1
1
0
0
0
0
1
1
1
1
0
0
1
1

0
1
0
0

0
0
1
1
0
0

1
1

0
1
0
1
0
1
0
1

1

1
0
0
1
1
0
0
1
1

I~I~I~I~I~I~I~I~I
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
SEGISTER
REGISTER
REGISTER
REGISTER

0
1
2
3
4
5
6
7
8
9
10

11
12
13
14
15

[INTERRUPT
VECTOR

• Write Register 3

*

NULL CODE
POINT HIGH
RESET EXT /STAT INTERRUPTS
SEND ABOR T (SDLC)
ENABLE INT ON NEXT Rx CHARACTER
RESET TxlN T PENDING
ERROR RES ET
RESET HIG HEST IUS

NULL CODE
RESET Rx CRC CHECKE R
RESET Tx CRC GENERA TOR
RESET Tx UNDERRUN/E OM LATCH

SYNC CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SDLC)
Rx CRC ENABLE
ENTER HUNT MODE
AUTO ENABLES

o
o

0
1

Rx
Rx
o Rx
r--::-t--:-i Rx

5 BITS/CHARACTER
7 BITS/CHARACTER
6 BITS/CHARACTER
8 BITS/CHARACTER

• Write Register 4

·WITH POINT HIGH COMMAND (D 5D.D3=001)
D7

D6

D5

D.

D.

0
0
1
1

D3

0
1
0
1

D2

D1

I 1lJ

• Write Register 1

I D7 I D6 I D5

D3

D2

0
0
1
1

I D1 I Do I

LL

EXT INT ENABLE
T : I NT ENABLE
PARITY IS SPECIAL CONDITION
Rx INT DISA BLE

0
0
1
1

Rx INT ON F IRST CHARACTER
OR SPACIA L CONDITION
INT ON ALL Rx CHARACTERS
OR SPECIAL CONDITION

Rx INT ON SP ECIAL CONDITION
ONLY
--WAIT/DMA REQUEST ON RECEIVE/TRANSMIT
~ WAIT/DMA REQUEST FU NCTION
- 'WAIT/DMA REQUEST ENABLE

0
0
1
1

---'----.-------~--SHARP

0
1
0
1

0
1
0
1

0
1
0
1

I Do I

Lp

ARITY ENABLE
PARIT Y EVEN/ODD
SYNC MO DES ENABLE
1 STOP BIT /CHARACTER
11/2 STOP BITS/CHARACTER
2 STOP BITS/CHARACTER

8 BIT SYNC CH ARACTER
16 BIT SYNC CH ARACTER
SDLC MODE (011 11110 FLAG)
EXTERNAL SYN C MODE

Xl CLOCK MODE
X16 CLOCK MODE
x32 CLOCK MODE
X64 CLOCK MODE

-------------365

LH8530

Z8530 SCCSerial Communications Controller

Write Register 5

Tx CRC ENABLE
RTS
SDLC/CRC·16
TxENABLE
SEND BREAK
1---+--'--ITx
1--'--+----ITx
1---+--,-0-tTx
'---'---' Tx
DTR

5
7
6
8

BITS (OR LESS )/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER

Write Register 6

D7

I.

1

D6

.------,1
1

I
SYNC7
SYNC,
SYNC7
SYNC3
ADR7
ADR7

SYNC,
SYNCo
SYNC6
SYNC,
ADR6
ADR6

1

DS~D' D~3.. D,

I

1

I

..

SYNCs
SYNCs
SYNCs
SYNC,
ADRs
ADRs

SYNC,
SYNC,
SYNC,
SYNCo
ADR,
ADR,

1

D,

1

Do

I.

I_

1---1

I

.
SYNC 3
SYNC3
SYNC,
1
ADR3

SYNC,
SYNC,
SYNC,

x

x

SYNC,
SYNC,
SYNC,

1

ADR,

1

ADR,

x

SYNCo MONOSYNC, 8 BITS
SYNCo MONOSYNC, 6 BITS
SYNCo BISYNC, 16 BITS
1
BISYNC, 12 BITS
ADRo SDLC ,8 BITS
x
SDLC, 4 BITS
(ADDRESS RUN)

Write Register 7

IDo I
10, 10.1 "'" IDC, Id. I
I

SYNC 7
SYNCs
SYNC 15
SYNC"
0

SYNC6
SYNC,
SYNC"
SYNC lO
1

I

SYNCs
SYNC3
SYNC'3
SYNC9
1

I

I

SYNC,
SYNC,
SYNC l2
SYNCs
1

I

SYNC3
SYNC,
SYNC"
SYNC7
1

1

SYNC,
SYNC.
SYNC lO
SYNC6
1

SYNC,
X

SYNC9
SYNCs
1

SYNCo MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
X
SYNCs BISYNC, 16 BITS
SYNC, BISYNC, 12 BITS
SDLC FLAG
0

-----------..--.--SHARP---------366

Z8530 SCC Serial Communications Controller

•

LH8530

Write Register 9

D7

D6

Ds

Write Register 12

I D, I D3 I D, I DI I Do I

LN~

I D7 ID6 I Ds I D, ID3 I D, I DI I Do I

I

VIS

LOWER BYTE OF TIME CONSTANT

'-DLC (IE O="Low")
L - MIE
'-STATUS HIGH/S TATUS LOW
'-0
0
0
1
1

0
1
0
1

•

NO RESET
CHANNEL B RESET
CHANNEL A RESET
FORCE HARDWARE RES ET

Write Register 13

I D7 ID6 ID5 ID, I D3 I D, I DI IDo I
I

UPPER BYTE OF TIME CONSTANT

Write Register 10
Write Register 14
D7

D6

I Ds I D, I D3 I D, I D, I Do J
BR GENERATOR ENABLE

LBR~ENERATOR SOURCE
=PC LK/RTxC PIN INPUT

ABORT /FLAG ON UNDERRUN
MARK/FLAG IDLE
GO ACTIVE ON POLL

o

NRZ
NRZI
1----''-+--''0-1 FMl (TRANSITION = 1)
1
FMO (TRANSITION = 0)

°

0

,-DTR/RE QUEST
FUNCTI ON
~AUTO ECHO
'-LOCAL LOOPBAC K

0
0
0
0
1
1
1
1

1

CRC PRESET I/O

°
°1
1
0
0
1
1

0
1
0
1
0
1
0
1

NULL COMMAND
ENTER SEARCH MO DE
RESET MISSING CL OCK
DISABLE DPLL
SET SOURCE = BR GENERATOR
SET SOURCE = --C
RTx
SET FM MODE
SET NRZI MODE

Write Register 11

I D,

D6

D5

D,

D3

I D,

Write Register 15
DI

Do

I

I

TRxC OUT XTAL OUTPUT
° °1 TRxC
OUT TRANSMIT CLOCK
°1
oor =
°1 TRxC OUT DPLL OUTPUTocnrur
1
=

TRxC

=
BR GFM:RATOR

=

'-- TRxC 0 /1

° °1
0
1
1

0
1

TRANSMIT CLOCK = RTxC PIN
TRANSMIT CLOCK = TRxC PIN
TRANSMIT CLOCK = BR GENERATOR OUTPUT
TRANSMIT CL OCK = DPLL OUTPUT

RECEIVE CLOCK
RECEIVE CLOCK
0 RECEIVE CLOCK =
1 1 RECEIVE CLOCK
'-- RTxC XTAL/NO XTAL

°° °1
1

DCDIE
SYNC/HUNT IE
CTS IE
Tx UNDERRUN /EOM IE
BREAK/ABORT IE

= R TxC PIN
= T RxC PIN
BR GENERATOR OUTPUT
= DPLL OUTPUT

.----------SHARP------------....--.
367

16-bit Microprocessors

LH70108(\l20)

High-Performance 16-Bit Microprocessor

LH70108(V20)
•

Description

High-Performance
I6-Bit Microprocessor
•

Pin Connections

The LH7010S(V20) is a CMOS 16-bit microprocessor with internal 16-bit architecture and an
S-bit external data bus. The LH7010S additionally has a powerful instruction set including bit processing, packed BCD operations, and high-speed
multiplication/division operations. The LH7010S
can also execute the entire SOSO instruCtion set
comes with a standby mode that significantly reduces power consumption. It is software-compatible with the LH7011616-bit microprocessor.
32

•

Features

1. Minimum instruction execution time: 250ns (at
SMHz)
2. ~aximum addressable memory: 1M byte
3. Abundant memory addressing modes
4. 14 X 16-bit register set
5. 101 instructions
6. Bit, byte, word, and block operations
7. Bit field operation instructions
S. Packed BCD instructions
9. Multiplication/division instruction execution
time: 2.4 p s to 7.1 p s (at 8MHz)
10. High-speed block transfer instructions:
1M byte/s (at 8MHz)
11. Hign -speed calculation of effective addresses:
2 clock cycles in any addressing mode
12. Maskable (INT) and nonmaskable (NMI) interrupt inputs
13. IEEE-796 bus compatible interface SOSO
emulation mode
14. CMOS technology
15. Low-power consumption
16. Low-power standby mode
17. Single power supply
IS. 5MHz or SMHz clock
19.40-pin DIP (DIP40-P-600)

RD

31 HLDRQ(RQ!AKo)
30 HLDAK(RQ,!AI\:I)
29 WR(BUSLOCK)

ADa
AD2

27 ;BUFR/W(BSd
26 BUFEN(BS o)
25 ASTB(QSo)

ADI
ADD.

NMI

17

24 INTAK(QSd

INT
CLK

GND
Top View

•

Ordering Information

T

LH70108-X

.

.

L Frequency
5: 5MHz
8: 8MHz
Model No.

*V20 is a trademark of NEe corporation.

~'--------~'----SHARP -----~-.. - - - 370

High~Performance

•

LH70108(V20)

16-Bit Microprocessor

Block Diagram

Alo/PS,
Als/PS.
AI,/PSI

Jt-

~
~
AI./PSo(38)+-

12

I

8

J)I

Bus
Buffer

-y

Y?--

AI5
Au 2 ) - Au
AI.
All
Alo ( 6)-A9
As

Internal Address/Data Bus
(IADo- IAD lo )

34) LBSo(HIGH)

~ BUFEN(BSo)
~ BUFR/W(BSil

(3)><

W-W--

~ IO!M(BS.)

4i¥
~~

AD,
AD.
ADs (ll)+AD,
AD,
~
AD2 (14)4ADI ~
ADo ~

PS
SS
DSo
DS I
PEP
DP
TEMP
Qo
QI
Q,
Q.

~IY-

@--

,--1\

r-v'

r

_@~U1J

Execution
Unit
(EXU)
;'l----

'r--

TA
TC
TBShifter

~

Sub Data Bus (16)

PSW

~ READY

~ RESET
~ POLL

I'r-

Control

Bus Hold
Control

Cycle
Decision

Interrupt
Control

1T-State

Vt-

_I

_

-,
I
I
I

L

I0

17 NMI
18 INT
~9 CLK

Effective Address
Generator

1

r---

c::

0

gj

~[)
.~ ~
;gt)
1---1\

L..t.,

.

30 HLDAK(RQ!AKI)

--------------

I\r---V

F

31 HLDRQ(RQ/ AKo)

Standby
Control

Queue
Control

~

e'~

~

.>l~

e

:;E

gj
~

'os

'---

"'"

M
I

~ SM

V<- --'\
---v'

---------------

LC
PC
AW
BW
CW
DW
IX
IY
BP
SP

~ WR(BUSLOCK)

rv

I I

Bus I
Control I
Unit I

~ ASTB(QSo)
~ INTAK(QSI)
~ RD

Status
Control

Cl

-y'

~e:

~

B
'5
.... Ul
.>l
:;E
Micro____ instruction

Microsequence
.Control

J

os

gJ

~

Instruction Decoder

I

~
..Main Data Bus (16)

- - - -.......... - - - - S H A R P - . - - , . ...................- - - - 371

LH70108(V20)

High-Performance 16-Bit Microprocessor

•

Pin Identification
No.

1
2-8
9-16
17
1~ :

19
20
21
22
23
24

Symbol
Direction
IC*
A 14 -A 8
Out
AD 7 -AD o In/Out
NMI
In
INT
CLK
GND
RESET
READY
POLL
INTAK
(QSd

In
In
In
In
In
Out

25

ASTB
(QSo)

Out

26

BUFEN
(BS o)
BUFR/W
(BS 1)

Out

27

Out

Function
Internally connected
Address but, middle bits·
Address/data bus
Nonmaskable interrupt
input
Maskable interrupt input
Clock input
Ground potential
Reset input
Ready input
Poll input
Interrupt acknowledge
output (queue status bit
1 output)
Address strobe output
(queue status bit 0 out·
put)
Buffer enable output
(bus status bit 0 output)
Buffer read/write output
(bus status bit 1 output)

No.

28
29
30

Symbol
Direction
10/M
Out
(BS z)
WR
Out
(BUSLOCK)
HLDAK
Out
(RQ/ AK 1) (In/Out)

31

HLDRQ
-(RQ/AKo)

In
(In/Out)

32
33

RD
S/LG

Out
In

34

LBS o
(HIGH)

Out

35-38 A 19 /PS 3 -

Out

A 16 /PS O
A15
V DD

Out

39
40
Notes:

Function
Access is I/O or memory
(bus status bit 2 output)
W rite strobe output
(bus lock output)
Hold acknowledge output,
(bus hold request input/
acknowledge output 1)
Hold request input (bus
hold request input/
acknowledge output 0)
Read strobe output
Small-scale/iarge-scale
system input
Latched bus status output 0 (always high in
large-scale systems)
Address bus, high bits or
processor status output
Address bus, bit 15
Power supply

* Ie should be connected to ground.
Where pins have different functions in small-and
large-scale systems, the large-scale system pin symbol
and function are in parentheses.
Unused input pins should be tied to ground or VDD to
minimize power dissipation and prevent the flow of
potentially harmful currents .

. - - - - - - - - - - S H A R P .--.----.--.-.~----

372

High-Performance 16-Bit Microprocessor

•

Absolute Maximum Ratings

LH70108(V20)

(Ta=+25"C)

•

Parameter Symbol Conditions MIN. MAX. Unit
Input
fc=IMHz
pF
15
CI
Unmeasured
capacitance
pF
pins returned
15
110
Cm
to OV
capacitance

Parameter
Symbol
Ratings
Units
Supply voltage
-0.5 to+7.0
VDD
V
Input voltage
-0.5 to V DD +0.3 V
VI
CLK input voltage
VK -0.5 to V DD +1.0 V
Output voltage
-0.5 to V DD +0.3 V
Vo
-40 to +85
Operating temperature Topr
"G
Storage temperature
Tstg
-65 to +150
"C

•

(LH70108-5, Ta= -40"C to+85"C, V pp= + 5V± 10%)
(LH70108-8, Ta=-10·C to+70"C, Vpp =+5V±5%)

DC Characteristics
Parameter
Input HIGH voltage
Input LOW voltage
CLK input HIGH voltage
CLK input LOW voltage
Output HIGH voltage
Output LOW voltage
Input leakage HIGH current
Input leakage LOW current
Output leakage HIGH current
Output leakage LOW current
HLDRQ input HIGH current
HLDRQ input LOW current

Supply current

(Ta=+25·C, VDD=OV)

Capacitance

Symbol
VIH
VIL
V KH
VKL
V OH
VOL
ILIH
ILIL
ILOH
ILOL
IHQH
IHQL
IDO

Conditions

IoH = -400 P. A
IOL =2.5mA
VI=VOO
VI=OV
Vo=V oo
Vo=OV
VI=VOO
VI=OV
Normal operation
Standby mode
Normal operation
Standby mode

70108-5
5MHz
70108-8
8MHz

MIN.
2.2
-0.5
3.9
-0.5
0. 7Voo

..

TYP.

30
5
45
6

MAX.
VDD +0.3
0.8
VDD +1.0
0.6
0.4
10
-10
10
-10
10
-0.5
60
10
80
12

Unit
V
V
V
V
V
V

p.A
p.A
p.A
p.A
p.A
rnA
rnA
rnA
rnA
rnA

~,-,-----.-..i;SHARP-'-------

373

High-Performance 16-Bit Microprocessor

•

(LH7010S-5, Ta=-40"Cto+S5·C, v DD =+5v±lO%)
(LH7010S-S, Ta=-10"C to+70·C, V DD =+5V±5%)

AC Characteristics

Parameter
Small/Large Scale
Clock cycle
Clock pulse HIGH width
Clock pulse LOW width
Clock rise time
Clock fall time
READY inactive setup to CLK ~
READY inactive hold after CLK t
READY active setup to CLK t
READY active hold after CLK t
Data setup time to CLK ~
Data hold time after CLK ~
NMI, INT, POLL setup time to
CLK t
Input rise time (except CLK)
Input fall time (except CLK)
Output rise time
Output fall time
Small Scale
Address delay time from CLK ~
Address hold time from CLK ~
PS delay time from CLK ~
PS float delay time from CLK t
Address setup time to ASTB ~
Address float delay time from
CLK ~
ASTB t delay time from CLK ~
ASTB ~ delay time from CLK t
ASTB HIGH width
Address hold time from ASTB ~
Control delay time from CLK
Address float to RD ~
RD ~ delay time from CLK ~
RD t delay time from CLK ~
Address delay time from RD t
RD LOW width
Data output delay time from
CLK ~
Data float delay time from CLK ~
WR LOW width
HLDRQ setup time to CLK t
HLDAK delay time from CLK ~
BUFEN t from WR t

37.4

LH70108(V20)

Conditions

tcVK
tKKH
tKKL
tKR
tKF

VKH=3.0V
V KL =1.5V
1.5V to 3.0V
3.0V to 1.5V

tSRVLK
tHKRYH
tSRVHK
tHKRYL
tSDK
tHKD

tOR
tOF

200
69
90

O.SV
2.2V
O.SV
2.2V

to
to
to
to

-S

30
tKKL -S
30
30
10

tKKL -S
20
20
10

2.2V
O.SV
2.2V
O.SV

tFKA

tHKA

tFKD
tww
t SHOK
tDKHA
t WeT

20

15
20
12
20
12

10
10
10
10

90
90
80

10
10
10
10

SO

tHKA

C L =100pF

110
165
150

tcvK-45
2tcyc 75
10
10
2tCyK -60
35
10
tKKL -20

tKKL -10
tKKH-lO
10
0
10
10

20
12
20
12

ns
ns
ns
ns

60

ns
ns
ns
ns
ns

60
60

60

ns

50
55

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

65
SO
SO

tCYK-40
2tcvc 5O
90
SO

160

10
10
2tcvK-40
20
10
tKKL -20

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tKKL -30

80
S5
tKKL -20
t KKH -I0
10
0
10
10

500

10
10

-S

tKKL -60

tDKD

125
44
60

10
10

tDKA
tHKA
t DKP
t FKP
t SAST

tDKSTH
tDKSTL
tSTST
t HSTA
tDKer
tAF~L
tDKRL
tDKRH
tDRHA
tRR

500

30

tSIK
tIR
tIF

Unit

60

ns

60

ns
ns
ns
ns
ns

100

High-Performance 16-Bit Microprocessor

•

LH70108(V20)

(LH7010S-5, Ta=-40'C to+S5·C, Voo =-5V±10%)
(LH7010S-S, Ta= -10·C to 70·C, voo= +5V±5%)

AC Characteristics (cont)

Parameter
Large Scale
Address delay time from CLK !
Addr.ess hold time from CLK !
PS delay time from CLK !
PS float delay time from CLK t
Address float delay time from
CLK!
Address delay time from RD t
ASTB delay time from BS !
BS ! delay time from CLK t
BS t delay time from CLK !
RD ! delay time from address
float
RD ! delay time from CLK !
RD t delay time from CLK !
RD LOW width
Data output delay time from
CLK!
Data float delay time from CLK
AK delay time from CLK !
RQ setup time to CLK t
RQ hold time after CLK !
RQ hold time after CLK t

Conditions

tOKA
tHKA
t OKP
tFKP

10
10
10
10

tFKA

tHKA

tORHA
tOBsT
tOKBL
tOKBH

tcYK-45

tOAFRL

t

Unit

10
10
CL=100pF

90
SO

10
10
10
10

60
60

ns
ns
ns
ns

SO

tHKA

60

ns

15
60
65

ns
ns
ns
ns

90

tcYK-40
15
110
130

0

10
10
0

tOKRL
tOKRH
tRR

10
10
21:cYK-75

165
150

t OKO

10

90

tFKo
tOKAK
tSRQK
tHKRQl
tHKRQ2

10

SO
70

20
0
40

60

10
10

ns
80
SO

ns
ns
ns

10

60

ns

10

60
50

ns
ns
ns
ns
ns

2tcyc 5O

10
0
30

.. - - - - - - - - - - - - - - - S H A R P ~.--.-.---- ............ ~375

High-Performance 16-Bit Microprocessor

•

Pin Functions

Some pins of the LH70108 have different functions according to whether the microprocessor is
used in a small- or large-scale system_ Other pins
function the same way in either type of system_
A15-As (Address Bus)
For small- and large-scale systems.
The CPU uses these pins to output the middle 8
bits of the 20-bit address data. They are threestate outputs and become high impedance during
hold acknowledge.
AD 7-AD o (Address/Data Bus)
For small- and large-scale systems.
The CPU uses these pins as the time-multiplexed address and data bus. When high, and AD
bit is a one; when low, an AD bit is a zero. This
bus contains the lower 8 bits of the 20-bit address
during Tl of the bus cycle and is used as an 8-bit
data bus during T2, T3, and T4 of the bus cycle.
Sixteen-bit data I/O performed in two steps. The
low byte is sent first, followed by the high byte.
The address/data bus is a three-state bus and can
be ata high or low level during standby mode. The
bus will be high impedance during hold and interrupt acknowledge.
NMI (Nonmaskable Interrupt)
For small~ and large-scale systems.
This pin is used to input nonmaskable interrupt
requests. NMI cannot be masked by software. This
input is positive edge triggered and must be held
high for five clocks to guarantee recognition.
Actual interrupt processing begins, however, after
completion of the instruction in progress.
The contents of interrupt vector 2 determine the
starting address for the interrupt-servicing
routine. Note that a hold request will be accepted
even during NMI acknowledge.
This interrupt will cause the LH70108 to exit
the standby mode.
INT (Maskable Interrupt)
For small- and large-scale systems.
This pin is an interrupt request that can be
masked· by software.
INT is active high level and is sensed during the
last clock of the instruction. The interrupt will be
accepted if the interrupt enable flag IE is set. The
CPU outputs the !NT AK signal to inform external
devices that the interrupt req uest has been
granted. INT must be asserted until the interrupt

376

LH70108(V20)

acknowledge is returned.
If NMI and INT interrupts occur at the same
time, NMI has higher priority than INT and INT
cannot be accepted. A hold request will be accepted
during INT acknowledge.
This interrupt causes the LH70108 to exit the
standby mode.
ClK (Clock)
For small- and largec-scale systems.
This pin is used for external clock input.
RESET (Reset)
For small- and large-scale systems.
This pin is used for the CPU reset signal. It is an
active. high level. Input of this signal has priority
. over all other operations. After the reset signal input returns to a low level, the CPU begins execution Of the program starting at address FFFFOH.
In addition to causing normal CPU start, RESET
input will cause the LH70108 to exit the standby
mode.
READY (Ready)
For small- and large-scale systems.
When the memory or I/O device being accessed
cannot complete data read or write within the CPU
basic access time, it can generate a CPU wait state
(Tw) by setting this signal to inactive (low level)
andrequesting a read/write cycle delay.
If the READY signal is active (high level) during
either the T3 or Tw state, the CPU will not generate a wait state.
This signal must be input in synchronization
with external clock signals to satisfy the setup/
hold time for normal operation.
POll (Poll)
For small- and large-scale systems.
The CPU checks this input upon execution of the
POLL instruction. If the input is low, then execu:
tion continues. If the input is high, the CPU will
check the POLL input every five clock cycles until
the input becomes low again.
The POLL and READY functions are used to
synchronize CPU program execution with the operation of external devices.
RD (Read Strobe)
For small- and large-scale systems.
The CPU outputs this strobe signal during data
read from an I/O device or memory. The IO/M sig-

LH70108(V20)

High-Performance 16-Bit Microprocessor

nal is used to select between I/O and memory.
The three-state output is held high during stand·
by mode and enters the high-impedance state during hold acknowledge.
S/LG (Small/Large)
For small- and large-scale systems.
This signal determines the operation mode of the
CPU. This signal is fixed at either a high or low
level. When this signal is a high level, the CPU will
operate in small-scale system mode, and when low,
in the large-scale system mode.
Pins 24 to 31 and pin 34 function differently depending on the operating mode of the CPU. Separate nomenclature is adopted for these signals in
the two operating modes.
Pin No.

24
25
26
27
28
29
30
31
34

S/LG-high
1NTAK
ASTB
BUFEN
BUFR/W
101M

WR
HLDAK
HLDRQ
LBS o

Function
S/LG-low
QSl
QSo
BS o
BS 1
BS 2
BUSLOCK
RQ/AK r
RQ/AKo
Always high

INTAK (Interrupt Acknowledge)
For small-scale systems_._ _
The CPU generates the INT AK signal low when
it accepts an INT signal.
The interrupting device synchronizes with this
signal and outputs the interrupt vector to the CPU
via the data bus (AD 7 - ADo).
ASTB (Address Strobe)
For smaU-scale systems.
The CPU outputs this strobe signal to latch
address information at an external latch.
ASTB is held at a low level during standby mode
however, goes high at one time for a half clock cycle to latch LBSO output.
BUFEN (Buffer Enable)
For small-scale systems
This is used as the output enable signal for an
external bidirectional buffer. The CPU generates
this signal during data transfer operations with external memory or I/O devices or during input of an
interrupt vector.
This three-state output is held high during
standby mode and enters the high-impedance state

during hold acknowledge.
BUFR/W (Buffer Read/Write)
For small-scale systems.
The output of this signal determines the direction of data transfer with an external bidirectional
buffer. A high output causes transmission from the
CPU to the external device; a low signal causes
data transfer from the external device to the CPU.
BUFR/W is a three-state output and becomes
impedance during hold acknowledge.
IO/M (lO/Memory)
For small-scale systems.
The CPU generates this signal to specify either
I/O access or memory access. A high-level output
specifies I/O and a low-level signaL specifies
memory.
101M's output is three state and becomes 'high
impedance during hold acknowledge.
WR (Write Strobe)
For small-scale systems.
The CPU generates this strobe signal during
data write to an I/O device or memory. Selection of
either I/O or memory is performed by the 101M
signal.
This three-state output is held high during
standby mode and enters the high-impedance state
during hold acknowledge.
HLDAK (Hold Acknowledge)
For small-scale systems.
The HLDAK signal is used to indicate that the
CPU accepts the hold request signal (HLDRQ).
When this signal is a high level, the address bus,
address/data bus, and the control lines become
high impedance.
HLDRQ (Hold Request)
For small-scale systems.
This input signal is used by external devices to
req uest the CPU to release the address bus,
addressl data bus, and the control bus.
This signal must be input in synchronization
with external clock signals to satisfy the setupl
hold time for normal operation.
LBS o (Latched Bus Status 0)
For small-scale systems.
The CPU uses the signal along with the 101M
and BUFR/W signals to inform an external device
what the current bus cycle is.

-..-.-------SHARP -----------.....-.
377

LH70108(V20)

High-Performance 16-Bit Microprocessor

101M

BUFR/W

0
0
0
0

0
0

1
1
1
1

0
0

1
1

1
1

LBS o
Bus Cycle
0
Program fetch
1
Memory read
Memory write
0
1
Passive state
Interrupt acknowledge
0
I/O read
1
0
I/O write
Halt
1

A19/PSa-A1S/PSO (Address Bus/Processor
Status)
For small- and large-scale systems.
These pins are time multiplexed to operate as an
address bus and as processor status signals.
When used as the address bus, these pins are the
high 4 bits of the 20-bit memory address. During
I/O access, all 4 bits output data O.
The processor status signal are provided for
both memory and I/O use. PS 3 is always 0 in the
native mode and 1 in 8080 emulation mode. The
interrupt enable flag (IE) is output to PS z. Pins PSi
and PS o indicate which memory segment is being
accessed.

A17 /PS l
0
0
1
1

Segment
A1S/PS o
Data segment 1
0
1
Stack segment
Program segment
0
1
Data segment 0

The output of these pins is three state and be·
comes ~igh impedance ,during hold acknowledge.
OSl, OSo (Queue Status)
For large-scale systems.
The CPU uses these signals to allow external devices, such as the floating-point arithmetic processor chip, about the status of the internal CPU instruction queue.

QSl
0
0

QSo

1
1

0

0
1
1

Instruction Queue Status
NOP (Queue does not change)
First byte of instruction
Queue empty
Subsequent bytes of instruction

The insturction queue status indicated by these
signals is the status when the execution unit (EXU)
accesses the instruction queue. The data output
from these pins is therefore valid only for one
clock cycle immediately following queue access.
These status signals are prov.ided so that the
floating-point processor chip can monitor the

378

CPU's program execution status and synchronize
its operation with the CPU when control is passed
to it by the FPO (Floating Point Operation) instructions.
BS2 -BSo (Bus Status)
For large-scale' systems.
The CPU uses these status signals to allow an
external bus controller to monitor what the current
bus cycle is.
The external bus controller decodes these signals and generates the control signals required to
perform access of the memory or I/O, device.

BS 2

BS 1

BS o

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1

Bus Cycle
Interrupt acknowledge
I/O read
I/O write
Halt
Program fetch
Memory read
Memory write
Passive state

The output of these signals is three state and becomes high impedance during hold acknowledge.
These signals will be high from the rising edge
of clock immediately after RESET signal is active
to the next clock rise.
BUSLOCK (Bus Lock)
For large-scale systems.
The CPU uses this signal to secure the bus while
executing the instruction immediately following the
BUS LOCK prefix instruction, or during an interrupt acknowledge cycle. It is a status signal to the
other bus masters in a multiprocessor system, inhibiting them from using the system bus during
this time.
The output of this signal is three state and becomes high impedance during hold acknowledge.
BUS LOCK is high during standby mode except if
the HALT instruction has a BUSLOCK prefix.
RO/AK 1. RQ/AKo (Hold RequestlAcknow- '
ledge)
For large-scale systems.
--.Ihese pins function as bus hold request inputs
(RQ) and as bus hold acknowledge outputs (AK).
RQI AKo has a higher priority than RQI AK i .
These pins have three-state outputs with
on-chip pull-up resistors which keep the pin at a
high level when the output is high impedance.
Bus Hold Request Input (RQ) must be inpl,lt in

High-Performance 16-Bit Microprocessor

LH70108(V20)

.-..-..-..-.-..-..-.-..-.-.-.-..-.-.-.-..-.-.
synchronization with external clock signals to
satisfy the setup/hold time for normal operation.
Voo (Power Supply)
For small- and large-scale systems.
This pin is used for the + 5 V power supply.
GNO (Ground)
For small- and large-scale systems. This pin is
used for ground.
IC (Internally Connected)
This pin is used for tests performed at the factor
by SHARP. The LH70108 is used with this pin at
ground potential.

•

. Register Configuration

Program Counter (PC)
The program counter is a 16-bit binary counter
that contains the segment offset address of the next
instruction which the EXU is to execute.
The PC increments each time the microprogram
fetches an instruction from the instruction queue.
A new location value is loaded into the PC each
time a branch, call, return, or break instruction is
executed. At this time, the contents of the PC are
the same as the Prefetch Pointer (PFP).
Prefetch Pointer (PFP)
The prefetch pointer (PFP) is a 16-bit binary
counter which contains a segment offset which is
used to calculate a program memory address that
the bus control unit (BCU) uses to prefetch the next
byte for the instruction queue. The contents of PFP
are an offset from the PS (Program Segment) register.
The PFP is incremented each time the BCU prefetches an instruction from the program memory. A
new location will be loaded into the PFP whenever
a branch, call, return, or break instruction is executed. At that time the contents of the PFP will be
the same as those of the PC (Program Counter).
Segment Registers (PC, SS, OSo, and OS1)
.
The memory addresses accesse.d by the
LH70108 are divided into 64K-byte logical segments. The starting (base) address of each segment
is specified by a 16-bit segment register, and the
offset from this starting address is specified by the
contents of another register or by the effective
address.
These are the four types of segment registers
used.

Segment Register
PS (Program Segment)
SS (Stack Segment)
DS o (Data Segment 0)
DS! (Data segment 1)

Default Offset
PFP
PS, effective address
IX, effective address

IY

General-Purpose Registers (AW, BW, CW, and
OW)
There are four 16,..bit general-purpose registers. Each one can be used as one 16-bit register
or as two 8-bit registers by dividing them into
their high and low bytes (AH, AL, BH, BL, CH, CL,
DH, DL).
Each register is also used as a default register
for processing specific instructions. The default
assignments are:
AW: Word multiplication/division, word I/O,
data conversion
AL: Byte multiplication/division, byte I/O, BCD
rotation, data conversion, translation
AH: Byte multiplication/ division
BW: Translation
CW: Loop control branch, repeat prefix
CL: Shift instructions, rotation instructions, BCD
operations
DW: Work multiplication/division, indirect
addressing I/O
Pointers (SP, BP) and Index Registers (IX, IY)
These registers serve as base pointers or index
registers when accessing the memory using based
addressing, indexed addressing, or based indexed
addressing.
These registers can also be used for data transfer and arithmetic and logical operations in the
same manner as the general-purpose registers.
They cannot be used as 8~bit registers.
Also, each of these registers acts as a default
register for specific operations. The default assignments are:
SP: Stack operations
IX:
Block transfer (source), BCD string operations
IY:
Block transfer (destination), BCD string operations
Program Status Word (PSW)
The program status word consists of the following six status and four control flags.
Status Flags
Control Flags
• V (Overflow)
. MD (Mode)
· S (Sign)
• DIR (Direction)
· Z (Zero)
• IE (Interrupt Enable)

---.....-.---------SHARP - . - - - - - - - - - - - 379

LH 701 08(V20)

High-'Performance 16-Bit Microprocessor

• AC (Auxiliary Carry) • BRK(Break)
• P (Parity)
• CY(Carry)
When the PSW is pushed on the stack, the word.
images of the various flags are as shown here.
PSW
15 14 13 12 11 10 9
M 1 1 1 V D I
DIE
R

8 7 6 5 4 3 2 1 0
B S Z 0 A 0 P 1 C
R
C
Y
K

The status flags are set and reset depending
upon the result of each type of instruction executed_
Instructions are provided to set, reset, and complement the CY flag directly.
Other instructions set anQ reset the control flags
. and control the operation of the CPU.
0 0 -0 3 (PrefetchOueue)

The LH70108 has 4 byte instruction queue
(FIFO), and it can store up to 4 instruction byte
prefetched by the BCU. The instruction codes
stored in the queue are fetched and executed by the
EXU. The queue is cleared and prefetched with
branch, call, return, or break instruction has been
executed and when external interrupt has been
acknowledged. Normally, the LH70108 prefetches
if the queue has one byte or more space. If the time
required to prefetch the instruction code from the
external memory is less than the mean execution
time of instructions which are executed sequentially, then the actual instructions cycle will be shortened by this amount of time i. e. the instruction
code to be next executed by the EXU can be available in the queue immediately after the completion
of one instruction. As the result, processing speed
is highly upgraded compared with the conventional
CPU which fetch and execute instructions one by
one. Queuing effect is lowered if there were many
instructions which clears queue like the branch instruction or in the case of continuous instructions
with too short instruction time.
DP (Data Pointer)

The data pointer is a 16-bit register indicates
. read/write addresses of variables. Effective
address made in the effective address generator
and the register contents including memory
address offsets are transferred to the DP.

EXU. The TEMP can be read or written by upper
byte or lewer byte independently for byte access.
Basically, the EXU completes write operation with
transferring data to the TEMP and completes read
operation with recognizing the data has been transferred to the TEMP from external data bus.
EAG (Effective Address Generator)

The Effective Address Generator (EAG) performs high-speed effective address calculation
necessary for memory access_ This completes all
the calculations with 2 clocks for every addressing
mode.
This fetches the instruction byte (2nd or 3rd
byte) which has operand specifying field, if the instruction needs memory access. Then calculates
effective address and transfers it to the DP (Data
Pointer) and generates control signals relating to
handling ALU and corresponding registers. In
addition, if it is necessary, the EAG requests to the
BCU for starting the bus cycle (memory read).
Instructlen Decoder

The Instruction Decoder classifies 1st byte of an
instruction code into some groups with specific
function and holds them during micro-instruction
execution_
Microaddress Register

The micro address register specifies the address
of a microinstruction ROM to be next executed. At
starting of a microinstruction execution, the 1st
byte of instruction bytes stored in the queue is
fetched in this register and it specifies a start'
address of the corresponding microinstruction
sequence.
Microinstruction ROM

The Microinstruction ROM has 1024 words by
29 bits of micro-instructions.
Microinstruction Sequencer

The Microinstruction Sequencer controls the
micro address register operation, microinstruction
ROM output, and synchronizing the EXU with
BCU.
ADM (Address Modifier)

Address Modifier performs the generation of
physical address (adding segment register and PFP
or DP) and increment of PFP (Prefetch Pointer).

TEMP (Temporary Communication Register)

This is a 16-bit temporary register used by
communications between external data bus and the

380

TAlTB (Temporary Register/Shifter A. B)

The TA/TB are 16-bit temporary register/shif- '

High-Performance 16-Bit Microprocessor

ter used with execution of mUltiply/divided and
shift/rotate (including BCD rotate) instructions.
When executing multiply or divide instruction T A
+TB operates as a 32-bit temporary register/
shifter when executing shift/rotate instructions.
Both the T A and TB can be read or written to and
from the internal bus by upper byte or lower byte
independently. The contents of the TA and TB are
input to the ALU.
TC (Temporary Register C)
The TC is a 16-bit temporary register used with
internal processing like the mUltiply or divide operation, etc. The TC content is output to the ALU.

LH70108(V20)

ALU (Arithmetic & Logic Unit)
The Arithmetic and Logic Unit consists of a full
adder and logical operation circuit and performs
these operations:
1) Arithmetic operation (Add, Subtract, Multiply,
Divide, increment, decrement, and complement)
2) Logical operation (test, AND, OR, XOR and bit
test, set, clear, and complement)
LC (Loop Counter)
The Loop Counter (LC) is a 16-bit register
which counts below items.
1) Loop number of the primitive block transfer and
input/output instructions (MOVBK, OUTM, etc.)
controlled with repeat prefix instructions (REP,
REPC, etc.).
2) Shift number of the multi-bit shift/rotate instructions.

381

High-:Performance 16-Bit Microprocessor

•

LH70108(V20)

High-Speed Execution of Instructions

This section highlinghts. the major architectural
features that enhance the performance of the
LH70108.
• Dual data bus in EXU
• Effective address generator
· 16/32-bit temporary registers/shifters (TA, TB)
• 16-bit loop. counter
• PC and PFP
Dual Data Bus Method
To reduce the number of processing steps for instruction execution, the dual data bus method has
been adopted for the LH70108 (figure 1). The two
data buses (the main data bus and the subdata bus)
are both 16 bits wide. For addition/subtraction
and logical and comparison operations, processing
time has been speeded up some 30% over single-bus systems.

Example
ADDAW, BW; AW+-AW+BW
Single Bus
Dual Bus
Stell 1 TA+-AW
. TA+-AW, TB+-BW
Step 2 TB+-BW
AW+-TA+TB
Step 3 AW+-TA+TB
Eff.ective Address Generator
This circuit (figure 2) performs high-speed processing to calculate effective addresses for accessing memory.
Calculation an effective address by the microprogramming method normally requires 5 to 12
clock cycles. This circuit requires only two clock
cycles for address to be generated for any addressing mode. Thus, processing is several times faster.

First and second byte of instruction

rim

Registers

EA Generator

Effective address

Fig.2

Subdata bus

Main data bus

Fig. 1

382

Dual Data Buses

Effective Address Generator

16/32-Bit Temporary Registers/Shifters (TA,
TB)
These 16-bit temporary registers/shifters (TA,
TB) are provided for multiplication/division and
shift/ rotation instructions.
These circuits have decreased the exec1!tion time
of multiplication/division instructions. In faCt,
these instructions can be executed about four times
faster than with the microprogramming method.
TA+TB: 32-bit temporary register/shifter for
multiplication and divison instructions.
TB 16-bit temporary register/shifter for shift/
rotation instructions.

LH70108(V20) .

High-Performance 16-Bit Microprocessor

Loop Counter (LC)
This counter is used to count the number of
loops for a primitive block transfer instruction
controlled by a repeat prefix instruction and the
number of shifts that will be performed for a multiple bit shift/ rotation instruction.
The processing performed for a multiple bit rotation of a register is shown below. The average
speed is approximately doubled over the microprogram method.
Example
RORC AW, CL; CL=5
Microprogram
LC method
method
8+(4X5)=28 clocks
7+5=12 clocks
Program Counter and Prefetch Pointer (PC and
PFP)
The LH70108 microprocessor has a program
counter, (PC) which addresses the program memory
location of the instruction to be executed next, and
a prefetch pointer (PFP), which addresses the program memory location to be accessed next. Both
functions are provided in hardware. A time saving
of several clocks is realized for branch, call, return, and break instruction execution, compared
with microprocessors that have only one instruction pointer.

15

,. Bit

•

Unique Instructions

Variable Length Bit Field Operation Instructions
This category tras two instructions: INS (insert
Bit' Field) and EXT (Extract Bit Field). These instructions are highly effective for computer
graphics and high-level languages. They can, for
example, be used for data structures such as packed arrays and record type data used in PASCAL.
(1) INS reg8, reg8/INS reg8, imm4
This instruction (figure 3) transfers low bits
from the 16-bit AW register (the number of bits is
specified by the second operand) to the memory
location specified by the segment base (DS 1 register) pulse the byte offset (IY register). The starting
bit position within this byte is specified as an
offset by the lower 4 bits of the first operand.
After each complete data transfer, the IY register and the register specified by the first operand
are automatically updated to point to the next bit
field.
Either immediate data or a register may specify
the number of bits transferred (second operand).
Because the maximum transferable bit length is
16 bits, only the lower 4 bits of the specified register (OOH to OF H) will be valid_
Bit field data may overlap the byte boundary of
memory.

length~1

Bit offset

Byte offset (IY)

::
Byte boundary

Fig. 3

:

Memory

I

t s
Segment base (DS 1)

Bit Field Insertion

383

LH70108(V20)

High-Performance 16-Bit Microprocessor

,~:

________+-________

~ ~Bi¥tl~f i~gt~.~ I·~Bi_to_f _se_t_.l~i. B_yt~eo~~
___

Byte Boundary
15

Segment base (DS 0)

0

AWL-I_o_~_~~

Fig. 4

Bit Field Extraction

(2) EXT reg8, reg8/EXT reg8, imm4
This instruction (figure 4) loads to the AW register the bit field data whose bit length is specified
by the second operand of the instruction from the
memory location that is specified by the DS o segment register (segment base), the IX index register
(byte offset), and the lower 4 bits of the first operand (bit offset).
Packed BCD Operation Instructions
The instructions described here process packed
BCD data either as strings (ADD4S, SUB4S,
CMP4S) or byte-format operands (ROR4, ROL4).
After the transfer is complete, the IX register
and the lower 4 bits of the first operand are automatically updated to point to the next bit field.
Either immediate data or a register may be specified for the second operand. Because the maximum
transferrable bit length is 16 bits, however, only
the lower 4 bits of the specified register (OR to
OFR) will be valid.
Bit field data may overlap the byte boundary of
memory.
ADD4S
This instruction adds the packed BCD string
addressed by the IX index register to the packed
BCD string addressed by the IY index register, and
stores the result in the string addressed by the IY
register. The length of the string (number of BCD
digits) is specified by the CL register, and the result of the operation will affect the overflow flag
(V), the carry flag (CY), and zero flag (2).
BCD string (IY, CL)+-BCD string (IY, CL)+ BCD
string (IX, CL)

(2) SUB4S
This instruction subtracts the packed BCD
string addressed by the IX index register from the
packed BCD string addressed by the IY register,
and stores the result in the string addressed by the
IY register. The length of the string (number of
BCD digits) is specified by the CL register, and the
result of the operation will affect the overflow flag
(V), the carry flag (CY), and zero flag (2).
BCD string (IY, CL)+-BCD string (IY, CL)-BCD
String (IX, CL)
(3) CMP4S
This instruction performs the same operation as
SUB4S except that the result is not stored and only
the overflow (V), carry flags (CY) and zero flag (2)
are affected.
BCD string (IY, CL)-BCD string (IX, CL)
(4) ROL4
This instruction (figure 5) treats the byte data of
the register or memory directly specified by the instruction byte as BCD data and uses the lower
4 bits of the AL register (ALd to rotate that data
one BCD digit to the left.

(1)

384

Fig. 5

BCD Rotate Left (ROL4)

High-Performance 16-Bit Microprocessor

(5) ROR4
This instruction (figure 6) treats the byte data of
the register or memory directly specified by the instruction byte as BCD data and uses the lower
4 bits of the AL register (ALLl to rotate the data
one BCD digit to the right

Fig. 6

BCD Rotate Right (ROR4)

Stack Operation Instruction
(1) PREPARE imm16, ilnm8
This instruction is used to generate "stack
frames" required by the block structures of highlevel languages such as Pascal and Ada. The stack
frame includes a local variable area as well as
pointers. These frame pointers point to the frame
containing the variables that can be referenced
from the current procedure.
The program example based upon Pascal language is shown below.
program EXAMPLE;
procedure P;
var a, b, c;
procedure Q;
var d, e;
procedure R;
var f, g;
begin
d:=a+f+g;
end:
begin
R;
b:=d+e;
end;
begin
a:=b+c;
Q;

end;
( * main program * )
begin
P;
end.

LH70108(V20)

This program is an example of a procedure block
with a triple nesting.
Procedure
P
Q

R

Variables
a, b, c
d, e
f, g

Accordingly, the global variables of a, band c
are referenced from the procedure Q, and a, b, c, d
and e from the procedure R.
This instruction copies frame-pointers to reserve the local variable area and to enable global
variable references. The first operand (16-bit immediate data) specifies (in bytes) the size of the local variable area. The second operation (S-bit immediate data) specifies the depth (or lexical level)
of the procedure block. The frame base address
generated by this instruction is set in the BP base
pointer.
To compile the EXAMPLE program follows the
assembler program shown next. (The DISPOSE instruction in the assembler program is used to return the stack pointer SP and the base pointer BP
to the state just before the PREPARE instruction is
executed. See DISPOSE section mentioned later.)
START: MOV
MOV
CALL
BR
P:
PREPARE
MOV
ADD
MOV
CALL
DISPOSE
RET
Q:
PREPARE
CALL
MOV
ADD
MOV
MOV
DISPOSE
RET
R:
PREPARE
MOV
ADD
MOV
ADD
MOV
MOV
DISPOSE
RET

SP, SPTOP
BP, SP
; CD
P
;@
SYSTEM
;@
6,1
AW, (BP) (B+BLEVEL*2)
AW, (BP) (C+CLEVEL*Z)
(BP) (A + ALEVEL * 2), AW
Q

;@
4,2
R
AW, (BP) (D+DLEVEL*2)
AW, (BP) (E+ELEVEL*2)
[Y, (BP) (BLEVEL * 2)
SS: Cry) (B+BLEVEL*2), AW

;@
4, 3
AW, (BP) (F+FLEVEL*2)
AW, (BP) (G+GLEVEL*2)
IY, (BP) (ALEVEL * 2)
AW, SS: (Iy) (A + ALEVEL * 2)
IY, (BP) (DLEVEL * 2)
SS: CrY) (D+ DLEVEL * 2), A W

Note: The variables are defined as the words.

-~---------SHARP-'-""""'------

385

~

LH70108(V20)

High-Performance 16-Bit Microprocessor

;A=-2
;B=-4
;C=-6
;D=-2
;E=-4
;F=-2
;G=-4

The process of the generation of the stack frame
according to the program is shown next. The numbers are referred to that in the program.

ALEVEL=-1
BLEVEL=-1
CLEVEL=-1
DLEVEL=-2
ELEVEL=-2
FLEVEL=-3
GLEVEL=-3

8

1I
rJJ~

~

11
u..c

Q)'O

Oll11
1

6
f-<

f-<

L:r.l
0:::

L:r.l
0:::

1
rJJ

------.

: r

•

-i
bO_

u..c

O then begin
repeat display -1 times
begin
SP=SP-2;
BP=BP-2;
(SP)=(BP);
end;'
SP=SP-2;
(SP)=temp;
end;
BP=temp/
SP = SP - dynamics

Data Access
(1) Local variable access
The local variables are assigned in the frame ~f
the procedure. The effective address EA. L of the
local variables is defined by the formula:
EA. L=SS: (BP+offset)
,The .offset value is defined as the sum of the
frame size (referenced frame base) and the variable
from the base of the local variable area.
(2) Global variable access
The global variable is located at the address
added by the offset of variables which are refer-

LH70108(V20)

High-Performance 16-Bit Microprocessor

enced to the accessed value of the base pointer of
the old one saved on the stack frame.
The effective address EA. G is defined as below.
EA. G=SS: ((SS: (BP+offset l))+offse~ 2)
The offset 1 is defined by the offset value from
the frame base (BP) to the address stored by the
base address of the frame including the global variables.
The offset 2 is defined by the offset value from
the frame base including variables to be referenced
to the variables.
DISPOSE
This instruction releases the last stack frame
generated by the PREP ARE instruction. It returns
the stack and base pointers to the values they had
before the PREP ARE instruction was used to call a
procedure.
SP=BP;
BP=(SP);
SP=SP+2
Check Array Boundary Instruction
This instruction is used to verify that index
values pointing to the elements of an array data
structure are within the defined range. The lower
limit of the array should be in memory location
mem32, the upper limit in mem32+2. If the index
value in reg16 is not between these limits when
CHKIND is executed, a BRK 5 will occur. This
causes a jump to the location in interrupt vector 5.
CHKIND reg16, mem32
When (mem32»reg16 or (mem32+2)¢> Test Points 

2.2 V

(7)

«<=:

2.2 V

Test P(lints

0.8 V

Read timing (small scale)

0.8 V

T4

Tl

T2

T3

T4

CLK

(3)

Clock timing

AD7-ADo

CLK
ASTB

tKKL

BUFEN

(4)

Wait (Ready) ti~ing
BUFR/W

Tl

T2

TW

T3

T4
RD

CLK

101M

Ready -----,.

A15-As _ _''''"_ _ _ _ _ _ _ _ _ _--''1-'tSRYHK

*Read signal must be held at LOW
or HIGH during this period.

(5)

POLL, NMI, INT input timing
Tn

CLK~

]Fl

~~

~

POLL
NMI.INT ~_ _ __

.-......-.--.--_...-.--$HARP - - - - - - - - - - - - - - 391

LH70108(V20)

High-Performance 16-Bit Microprocessor

(8) Write timing (small scale)

(10)

Write timing (large scale)

Tl

T4
T4

Tl

T2

T3

T4

eLK

T3

T2

T4

eLK

Al9/PS3
-AI6/PSo
LBSo

A15- As :-----1' '--+--+-,--,----+---1---1'
Data Output

AD7-ADo

-tHKA
_tDKD

AD,-ADo

Data Output

ASTB
(71088
Output)

ASTB

-1-

BS,-BSo

\

Bus Status

7

tDKCT

BUFEN

QSI-QSO

BUFR/W
AI5-As

WR-,-----·-f:~w=r

LB~-V
V-IO/M .../\~------~~

(9)

Read timing (large scale)
T4
eLK

LBSo

ADrADo
ASTB
(71088
Output)

392

Tl

T2

T3

T4

==x

~_ _ _ _ _~>C

High-Performance 16-Bit Microprocessor

(11)

LH70108(V20)

Interrupt acknowledge timing

CLK
AD7-ADo
ASTB
1NTAK
BUFEN
BUFR/W
101M

tOKA

BUSLOCK'
AIS-As

(12)

tFKA

~}=-:--------------------­
* Large Scale Mode

Only

Hold request/acknowledge timing (small scale)

lor 2
SLK
HLDRQ
HLDAK

--------1"

* ____~70~1~O~8_ _~~E_x_t_er_n_a_I_M_a_st_e_'r,

~

*_A_19/_P_S_3-_A_l_6/_P_S_o.~A_,_15-_A_8_._A_D~7--A-D-O-.-R-D-.-L-S-B--O.--10-/-~-.-B-U--F-R-/W--.___________~ I:I~__

...________________ WR BUFEN
(13)

Bus request/acknowledge timing (large scale)

CLK

::=GPulse 2 AK

_______
_

~~~

Pulse 3 RQ

0U~x=-:-~-FK-A-,- -\~7~O~1_08_1_n~p_ut~

______,r-_7_01_0_'__

__

:~Ii Coprocessor

* AI9/PS3-A16/PSo. AIS-As. AD7-ADo. BS2-BSo. RD. BUS LOCK
-~-'-----SHARP---~-'-""---

393

LH70108(V20)

High-Performance 16- Bit. Microprocessor

Instruction Set
The following tables briefly describe the
LH70I08's instruction set.
D Operation and Operand Type-'defines abbreviations used in the Instruction Set table.
D Flag Operations-defines the symbols used to describe flag operations.
D Memory Addressing-shows how mem and modcombinations specify memory addressing
modes.
D Selection of 8-and I6-Bit Registers-shows how
reg and W select a register when mod = 111.
D Selection of Segment Registers-shows how sreg
selects a segment register.
D Instruction Set-shows the instruction mnemonics, their sffect, their operation codes the number of bytes in the instruction, the number of
clocks required for execution, and the effect on
the LH70I08 flags.

Table 1 Operand Types

•

Identifier
reg
reg8
reg16
dmem
mem
mem8
mem16
mem32
imm
imm16
imm8
imm4
imm3
ace
sreg
src-table
src-block
dst-block
near-proc
far-proc
near-label
short-label
far-label
memptr16

memptr32

regptr16

pop-value

fp-op

Description
8- or 16-bit general-purpose register
8-bit general-pourpose register
16-bit general-purpose register
8- or 16-bit direct memory location
8- or 16-bit memory location
8-bit memory location
16-bit memory location
32 - bit memory location
Constant (0 to FFFFH)
Constant (0 to FFFFH)
Constant (0 to FFH)
Constant (0 to FH)
Constant (0 to 7)
AW or AL register
Segment register
Name of 256-byte translation table
Name of block addressed by the IX
register
Name of block addressed by the IY
register
Procedure within the current program
segment
Procedure located in another program
segment
Label in the current program segment
Label between -128 and + 127 bytes
from the end of instruction
Label in another program segment
Word containing the offset of the
memory location whin the current
program segment to which control is to
be transferred
Double word containing the offset and
segment base address of the memory
location to which control is to be
transferred
16-bit register containing the offset of
the memory location within the
program segment to which control is to
be transferred
Number of bytes of the stack to be
discarded (0 to 64K bytes, usually
even addresses)
Immediate data to identify the
instruction code of the external floating point operation

--.-.-.--------$HARP ....-..-.---------.-

394

High-Performance 16-Bit Microprocessor

Table 2

Operation Code Types

Identifier
R
W
reg
mem
mod
S:W
X,XXX,
YYY, ZZZ

Table 3

...)

disp
ext-disp8
temp

Description
Register set
Word/byte field (0 to 1)
Register field (000 to 111)
Memory field (000 to 111)
Mode field (00 to 10)
When S: W=Ol or 11, data=J6 bits.
At all other times, data = 8 bits.
Data to identify the instruction code of
the external floating point arithmetic
chip

Operational Description

Identifier
AW
AH
AL
BW
CW
CL
DW
BP
SP
PC
PSW
IX
IY
PS
SS
DS o ·
DS 1
AC
CY
P
S
Z
DlR
IE
V
BRK
MD
(

LH70108(V20)

Description
Accumulator (16 bits)
Accumulator (high byte)
Accumulator (low byte)
BW register (16 bits)
CW register (16 bits)
CW register (low byte)
DW register (16 bits)
Base pointer (16 bits)
Stack pointer (16 bits)
Program counter (16 bits)
Program status word (16 bits)
Index register (source)(16 bits)
Index register (destination)( 16 bits)
Program segment register (16 bit)
Stack segment register (16 bits)
Data segment 0 register (16 bits)
Data segment 1 register (16 bits)
Auxiliary carry flag
Carry flag
Parity flag
Sign flag
Zero flag
Direction flag
Interrupt enable flag
Overflow flag
Break flag
Mode flag
Values in parentheses are memory
contents
Displacement (8 or 16 bits)
16-bit displacement (sign -extension
byte + 8" bit displacement)
Temporary register (8/16/32 bit)
TA: Temporary resister A (16 bits)
TB: Temporary resister B (16 bits)
TC: Temporary resister C (16 bits)

Identifier
tmpcy
seg
offset
+-

+

X

%
AND A
OR V
XOR VXXH
XXXXH

Table 4

Flag Operations

Identifier
(blank)
0
1
X
U
R

Table 5
men
000
001
010
011
100
101
110
111

Description
Temporary carry flag (1 bit)
Immediate segment data (16 bits)
Immediate offset data (16 bit)
Transfer direction
Addition
Su btraction
Multiplication
Division
Modulo
Logical product
Logical sum
Exclusive logical sum
Two-digit hexadecimal value
Four-digit hexadecimal value

Description
No change
Cleared to 0
Set to 1
Set or cleared according to the result
Undefined
Value saved earlier is restored

Memory Addressing

00
BW+IX
BW+IY
BP+IX
BP+IY
IX
IY
Direct address
BW

mod
01
BW+IX+disp8
BW+IY+disp8
BP + IX + disp8
BP + IY + disp8
IX+disp8
IY+disp8
BP+disp8
BW+disp8

10
BW+IX+disp16
BW+IY+disp16
BP+IX+disp16
BP+IY+disp16
IX+disp16
IY+disp16
BP+disp16
BW+displ6

....-.......- - - - - - - $ H A R P - - - - - - - - - - - 395

High-Performance 16":'Bit

Microproc~ssor

Table 6 Selection of 8- and 16-Bit Registers
(mod 11)
reg
w=o
W=l
AL
000
AW
001
CL
CW
010
OL
OW
011
BL
BW
100
AH
SP
101
CH
BP
no
OH
IX
.111
BH
IY
Table 7 Selection of Segment Registers
sreg
00
01
PS
10
SS
11
OSo

396

.. LH70108(V20)

The table on the following pages shows the instruction set.
At "No. of Clocks," for instructions referencing
memory operands, the left side of the slash (/) is .
the number of clocks for byte opereands and the
right side is for word operands. For conditional
control transfer instructions, the left side of the
slash (I) is· the number of clocks if a control transfer takes place. The right side is the number of
clocks when no control transfer or branch occurs.
Some instructions show a range of clock times,
separated by a hyphen. The execution time of these
instructions varies from the minimum value to the
maximum, depending on the operands involved.
"No. of Clocks"includes these times:
• Decoding
· Effective address generation
• Operand fetch
• Execution
It assumes that the instruction bytes have been
prefetched.

I
I
I
I

I
I

I
I

iI
I

I
I
I
I
I

~I

Mnemonic

Operation

Operation Code

S Z

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0

Data Transfer Instructions
reg, reg
reg-reg
MOV
1 0
(mem)-reg
mem reK
1 0
reg, mem
reg-(mem)
1 0
(mem)-imm
mem imm
1 1
reg, imm
reg-imm
1 0
ace, dmem
When W - 0 AL-(dmem)
1 0
When W= 1 AH-(dmem+ll. AL-(dmem)
dmen, acc
When W-O (dmem)-AL
1 0
When W=1 (dmem+l)-AH.(dmem)-AL
sreg, regl6 sreg-reg16 sreg: SS DSO DSI
1 0
sreg,meml6 sreg-(mem16) sreg: SS DSO DSI
1 0
regl6 sreg reg16-sreg
1 0
mem16 sre~ (memI6)-sreg
1 0
DSO, reg16, reg16-(mem32)
1 1
mem32
DSO-(mem32 + 2)
DSl, reg16, regI6-(mem32)
1 1
DS1-(mem32 + 2)
mem32
AH PSW
AH -S Z x AC x P x CY
1 0
PSW AH
S Z x AC x P x CY-AH
1 0
LDEA reg16 mem16 regl6-meml6
1 0
TRANS src-table
AL-(BW+AL)
1 1
reg, reg
reg-reg
XCH
1 0
mem, reg
(mem)-reg
1 0
or reg, mem
AW, reg16 or AW-regl6
1 0
reg16 AW
Repeat Prefixes
REPC
While CWo!O, the next byte of the primitive 0 1
block transfer instruction is executed and
CW is decremented (-1). If there is a wait·
ing interrupt, it is processed. When CYo! I,
exit the loop.
REPNC
While CWo!O, the next byte of the primitive 0 1
block transfer instruction is executed and
CW is decremented (-1). If there is await·
ing interrupt, it is processed.When CYo!O,
exit the loop.

0
0
0
0
1
1

0
0
0
0
1
0

1
1
1
0
W
0

0 1 W 1 1
0 o W mod
0 1 W mod
1 1 W mod 0
reg
0 o W

1 0 0 0

reg
reg
reg
0 0

reg
mem
mem
mem

1 W

2
9113
11/15
11/15
4
10/14

2
2-4
2-4
3-6
2-3
3

9113

3

sreg
sreg
sreg
sreg
reg

reg
mem
reg
mem
mem

2
15
2
14
26

2
2-4
2
2-4
2-4

reg

mem

26

2-4

2
3
4
9
3
16124

1
1
2-4
1
2
2-4

3

1

1 0 0 1 0 1

2

1

1 0 0

2

1

0
0
0
0
0

0 1
0 1
0 1
0 1
0 0

1
1
1
1

1
1
0
0
1 0

0
0
0
0
1

1 1
mod
1 1
mod
mod

0 0 0

1 0 0 mod

0
0
0
0
0
0

1
1
0
1
0
0

1
1
1
1

0

1 0

1
1
1
0
0
0

1
1
0
1
1 1
1 1

1
0
1 mod
1
W 1 1
W mod

reg

1 0 0

0
0
0
0

reg

mem

reg
reg

reg
mem

I~

Ii
IiI
Ii
~

x x
x x

x x x
x x x

I
I

I
IiI~

~

I
I
I
I

I
I
I

Mnemonic 1 Operand
Repeat Prefixes (cont)
REP
REPE
REPZ

REPNE
REPNZ

Primitive
MOVBK

I

~

I
1
I
I

I
I

I
I

CMPBK

CMPM

10M

STM

--

. Operation

While cw=lo, the next byte of the primitive
block transfer instruction is executed and
CW is decremented (-1). If there is a wait·
ing interrupt, If is processed. If the primi·
tive block transfer instruction is CMPBK or
CMPM and Z=lI exit the loop.
While cw=lo, the next byte of the primitive
block transfer instruction is executed and
CW is decremented (-1). If there is a wait·
ing interrupt, it is processed.!f the primitive
block transfer instruction is CMPBK or
CMPM and z=lo exit the loop.
Block Transfer InstructIOns
dst-block,
When W= 0 (IY)-(IX)
src-block
DIR=O: IX-IX + 1, IY-IY + 1
DIR=l: IX-IX-I, IY-IY-1
When W= I(IY + 1,IY)-(IX + 1,IX)
DIR=O: IX-IX+2, IY-IY+2
DIR=1: IX-IX-2 IY-2
When W -0 (IX)-(IY)
src-block,
DIR=O: IX-IX+1, IY-IY+1
dst-block
DIR=I: IX-IX-I, IY-IY-t
When W=1 (IX+1, IX)-(IY+I, IY)
DIR = 0: IX -IX + 2, IY -IY + 2
DIR=1: IX-IX,--2 IY-IY-2
When W=O AL-(IY)
dst-block
DIR=O: IY-IY+1; DIR=1: IY-IY-1
When W=1 AW-(IY+1, IY)
DIR=O: IY-IY+2; DIR=1: IY-IY-2
WhenW=O AL-(IX)
src-block
DIR=O: IX-IX+1; DIR=1: IX-IX-1
When W=1 AW-(IX+1, IX)
DIR=O: IX-IX+2; DIR=1: IX-IX-2
dst-block
When W-O (IY)-AL
DIR=O: IY-IY + 1; DIR= 1: IY-IY-I
When W=1 (IY+1, IY)-AW
DIR=O: IY-IY+2- DIR=i: IY-IY-2

Operation Code
7 6 5 4 3 2 1 017 6 5 4 3 2 1 0
1 1 1 1

o

0 1 1

S Z
2

If

1 1 1 1 0 0

1 0

2

1

1 0

o

11+8n

1

1 0 0 1

W

U
I
~

11 + 16n
1 0

1 0

o

1 1 W

7+14n 1

x x x x x x

7+22n
1 0

1 0

1 1 1 W

7+10n 1
7+14n

1 0

1 0

1 1

o

W

7+9n

1

7+13n
1 0

1 0

1 0

1 W

n: number of transfers

I~

1

7+4n
7+8n

1

x x x x x x

Ii

I
I
I
IiI~

I
I
I
I
I
I
I
I

!

~~

I

I

I
I

I

I
I

Mnemonicl

Over and

Operation

Bit Field Instructions
INS
reg8, reg8

16-Bit field+-AW

reg8, imm4

16-Bit field+-AW

Bit Field Transfer Instructions (cont)
AW+-16-Bit field
EXT
reg8, reg8
reg8, imm4

AW+-16-Bit filed

II 0 Instructions
IN
acc, imm8

When W -0 AL+-(imm8)
When W=1 AH+-(imm8+1), AL+-(imm8)
When W=O AL+-(OW)
acc, OW
When W=1 AH+-(OW+l), AL+-(OW)
OUT
imm8, acc
When W=O (imm8)+-AL
When W=1 (imm8+1)+-AH (imm8)+-AL
DW, acc
When W -0 (DW)+-AL
When W=1 (OW+l)+-AH (OW)+-AL
Primitive 110 Instrctions
INM
dst-block, DW When W -0 (lY)+-(DW)
DIR=O: IY+-IY+l; DIR=I: IY+-IY-l
When W=1 (IY+l, IY)+-(OW+l, OW)
DIR=O: IY+-IY+2; DIR=1: IY+-IY-2
OUTM DW,src-block When W=O (OW)+-(lX)
DIR=O: IX+-IX+l; DIR=I: IX+-IX-l
When W=1 (DW+l, OW)+-(IX+l, IX)
DIR=O: IX+-IX+2; DIR=1: IX+-IX-2
Addition/Subtraction Instructions
reg+-reg+reg
ADO
reg, reg
(mem)+-(mem) + reg
mem reg
reg+-reg + (mem~
reg,mem
regm imm
reg+-reg+imm
mem jrnm
(mem)+-(mem) + imm
When W=O AL+-AL+imm
acc,imm
When W=1 AW+-AW+imm
reg+-reg+reg+CY
ADDC reg, reg
mem reg
(mem)+-(mem) + reg+ CY
reg+-reg+ (mem) +CY
reg, mem
reg, imm
reg+-reg+ imm + CY
(mem)+-(meml+imm +CY
mem imm

~I

OJ

11111111

7 6

5 4

Overation Code
3 2 1 017 6 5 4

S Z

3 2 1 0

0 0 0 0 1 1 1 1 0 0
reg
reg
1 1
0 0 0 0 1 1 1 1 0 0
reg
1 1 0 0 0

1

1 0

1

1

1 0

0 0 0 0 1 1 1 1 o 0
reg
reg
1 1
0 0 0 0 1 1 1 1 0 0
reg
1 1 0 0 0

1

1

1

1

1

35-133 3

0

1

35-133 4

0 0

1

1

34-59

3

1 0

1

1

34-59

4

0 0

1

1

1 0

0

1

o

W

9113

2

1

1

1 0

1

1

o

W

8112

1

1

1

1 0

0

1

1 W

8112

2

1

1

1 0

1

1

1 W

8/12

1

0

1

1 0

1

1

o

9+8n

1

W

Ii
B
If

9+16n

0

1

1 0

1

1

1 W

9+8n

0
0
0
1
1
0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

0 1 W
0 o W
0 1 W
0 S W
0 S W
1 o W

0
0
0
1
1

0
0
0
0
0

0 1 0 0 1
0 1 0 0 o
0 1 0 0 1
0 0 0 0 S
0 0 0 0 S

W
W
W
W
W

1 1
mod
mod
1 1
mod

reg
reg
reg

0 0 0
reg

reg
1 1
reg
mod
reg
mod
1 1 0 1 0
mod 0 1 0

1

9+16n

n: number I of transfers
reg
mem
mem
reg
mem

reg
mem
mem
reg
mem

2
16/24
11/15
4
18/26
4

2
2-4
2-4
3-4
3-6
2-3

2

2
2-4
2-4
3-4
3-6

16124
11/15
4
18/26

I~

x
x
x
x
x
x
x

x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x

x

x

x

x
x
x
x

x
x
x

x
x
x
x
x

x

x

x

x
x
x x

x
x
x
x

x
x
x

x

x

x

P
I
I
I

II

81

I

I
I

I
I

I
I

iI

Mnemonicl

I

Operation

Addition/Subtraction Instructions (cont)
When W-O AL-AL+imm+CY
ADDC ace, imm
When W='=1 AW-AW+imm+CY
reg, reg
reg-reg- reg
SUB
(mem)-(mem)-reg
mem reg
reg, mem
reg-reg-(mem~
reg, imm
reg-reg- imm
(mem)-(mem)-imm
mem imm
When W -0 AL-AL-imm
acc, imm
When W=1 AW-AW-imm
reg-reg-reg-CY
SUBC reg, reg
(mem)-(mem) - reg-CY
mem reg
reg-reg-(mem)-CY
reg, mem
reg-reg-imin-CY
reg, imm
(mem)-(mem)-imm -CY
mem imm
When W=O AL-AL-imm-CY
acc, imm
When W=1 AW-AW-imm-CY
BCD Operation InstructIOns
dst BCD string-dst BCD string
ADD4S
+ src BCD string
dst BCD string-dst BCD string
SUB4S
-src BCD string
CMP4S
dst BCD string-scrBCD string

Ooeration Code

ROL4

ROR4

reg8

reg
~upperILowe1j
L
4-bits
4-bits

mem8

mem
~upperILowe:l-]
L
4-bits 4-bits

reg8

reg

~upperILowe~
ALL
4-bits 4-bits
mem8

mem
L

4J~~ts

4-bits

S Z

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0
0 0 0 1 0 1
0
0
0
1
1
0

0 1 0 1
0 1 0 1
0 1 0 1
0 0 0 0
0 0 0 0
0 1 0 1

0
0
0
0
0
1

0
0
0
1
1
0

0
0
0
0
0
0

0
0
0
0
0
1

0
0
0
0
0
0

1
1
1
0
0
1

1
1
1
0
0
1

o

W

4

2-3

x

x

x

x

x

x
x
x
x
x
x
x

1 W
W
1 W
S W
S W
oW

reg
1 1
reg
mod
reg
mod
1 1 1 0 1
mod 1 0 1

reg
mem
mem
reg
mem

2
16/24
11115
4
18/26
4

2
2-4
2-4
3-4
3-6
2-3

x
x
-x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

1 W
W
1 W
S W
S W
o W

reg
1 1
reg_
mod
reg
mod
1 1 0 1 1
mod 0 1 1

reg
mem
mem
reg
mem

2
16/24
11/15
4
18/26
4

2
2-4
2-4
3-4
3-6
2-3

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

o

o

----

I

I
I
I
I
I

Ooerand

---

----- - -

x
x

0 0 0 0

1 1 1 1 0 0

1 0 0 0 0 0

7+19n 2

u x

u u u x

0 0 0 0

1 1 1 1 0 0

1 0 0 0

1 0

7+19n 2

u x

u u u x

0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0
n: number of BCD digits divided by 2
0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0
reg
1 1 0 0 0

7+19n 2

u x

u u u x

3

1 1 1 1 0 0
mem

1 0

1 0 0 0

28

3-5

0 0 0 0 1 1 1 1 0 0
1 1 0 0 0
reg

1 0

1 0

1 0

17

3

0 0 0 0 1 1 1 1 0 0
mod 0 0 0
mem

1 0 1 0 1 0

32

3-5

0 0 0 0
mod 0 0

If

n
I
~

en

x
x
x

---

13

I~

0

Ii
I
I
II

II

I
I
I
I

I
I
I

I
VI
iN

1J

I

I

I
I
I
I
I
~I

Mnemonicl

Ooerand

Operation

Increment/Decrement Instructions (cont)
reg8 ..... reg8 + 1
INC
reg8
(mem) .....(mem)+ 1
mem
reg16
reg16-regI6+ 1
reg8
regS ..... regS-l
DEC
(mem) .....imem)-1
mem
regI6 ..... regI6-1
reg16
Multiplication Instructions
AW ..... AL X regS
MULU regS
AH=O: CY-O. V-O
AH~O: CY-l V-I
mem8
AW-ALX (mem8)
AH=O: CY-O. V-O
AH~O: CY-l V-I
reg16
DW. AW-AWXregI6
DW=O: CY ..... O. V..... O
DW~O: CY-l.V ..... l
DW. AW-AWX(memI6)
mem16
DW=O: CY-O. V..... O
DW~O: CY-l.V-l
MUL
regS
AW+-ALXregS
AH=AL sign expansion: CY+-O. V+-O
AH ~ AL sign exoansion: CY +-1 V +-1
AW+-ALX(mem)S
memS
AH=AL sign expansion: CY+-O. V+-O
AH~AL sign exoansion: CY-l V+-l
reg16
DW. AW-AWXregS
DW=AW sign expansion: CY+-O. V+-O
DW~AW sign exoansion: CY+-l V+-l
mem16
DW. AW-AWX(mem)8
DW=AW sign expansion: CY+-O. V+-O
DW~AW sign expansion: CY+-l V+-l
regl6+-regl6 XimmS
regl6.
(regI6.)
Product~16 bits: CY+-O. V+-O
imm8
Product>16 bits: CY+-l V-I
regI6+-(memI6)XimmS
regl6.
meml6.
Product~16 bits: CY+-O. V+-O
imm8
Product>16 bits: CY+-l V+-l
regl6+-regl6 X imm16
regl6.
Product~16 bits: CY+-O. V+-O
(regI6.)
imm16
Product> 16 bits: CY+-l V+-l
regI6+-(memI6) Ximm16
regl6.
meml6,
Product~ 16 bits: CY+-O. V+-O
imm16
Product> 16 bits: CY+-l V+-l

OJ

11111111

7 6

5 4

Ooeration Code
3 2 1 017 6 5 4 3 2 1 0

1
1
0
1
1
0

1
1
0
1
1
0

1
1
0
1
1
1

1
1
1
1
1
1

1 1 0 0 0
mod 0 0 0

reg
mem

2
16/24
2
2
16/24
2

2
2-4
1
2
2-4
1

x
x
x
x
x
x

1 1 0 0
mod 0 0

1
1

reg
mem

1 1 1 1 0

1 1 0 1 1 1 0 0

reg

21-22

2

u x x u u u

1 1 1 1 0

1 1 0 mod

1 0 0

mem

27-28

2-4

u x x u u u

1 1 1 1 0

1 1 1 1 1 1 0 0

reg

29-30

2

u x x u u u

1 1 1 1 0

1 1 1 mod

mem

39-40

2-4

u x x u u u

1 1 1 1 0

1 1 0 1 1 1 0

1

reg

33-39

2

u x x u u u

1 1 1 1 0

1 1 0 mod

1 0

1

mem

39-45

2-4

u x x u u u

1 1 1 1 0

1 1 1 1 1 1 0

1

reg

41-47

2

u x x u u u

1 1 1 1 0

1 1 1 mod

1

mem

51-57

2-4

u x x u u u

1

1
0
1
1
0

1 1 0
1 1 W
reg
1 1 0
1 1 W
reg

s z
x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

I~

Ii
IiI

~

0'

1 0 0

1 0

1 0

1 0

1 1 1 1

reg

reg

2S-34

3

u x .x

0 1 1 0

1 0

1 1 mod

reg

mem

38-44

3-5

u x x u u u

0 1

u u u

0

1 1 0

1 0 0

1 1 1

reg

reg

36-42

4

u x x u u u

0

1 1 0

1 0 0

1 mod

reg

mem

46-52

4-6

u x x u u u

n

I
I
II

II

~

I
I
I
I
I
I
I
I

!
"I
I

I
I

I
I
I
I

Mnemonic

Operation Code

Operation

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0

Unsigned Division Instructions
temp+--AW
regS
DIVU
When temp-;-re,gS~FFH
AH+--temp%regS, AL+--temp-;-regS
When temp-;-regS > FFH
TA+--(OOIH, OOOH), TC+--(003H, 002H)
SP+--SP- 2,(SP+ 1, SP)+--PSW, IE+--O, BRK +--0
SP+--SP- 2,(SP+ 1, SP)+--PS, PS+--TC
SP+--SP- 2.(SP+ 1, SP)+--PC PC+--TA
temp+--AW
memS
When temp-;-(memS)~FFH
AH+--temp%(memS), AL+--temp-;-(memS)
When temp-;-(memS»FFH
TA+--(OOlH, OOOH), TC-(003H, 002H)
SP-SP-2,(SP+1, SP)-PSW, lE-O, BRK-O
SP-SP-2,(SP+ 1, SP)-PS; PS-TC
SP-SP-2,(SP+1 SP)-PC PC-TA
temp+--DW, AW
reg16
When temp-;-regI6~FFFFH
DW+--temp%regI6, AW+--temp-;-regI6
When temp-;-regI6>FFFFH
TA+--(OOIH, OOOH), TC+--(003H, 002H)
SP+--SP-2,(SP+ 1, SP)+--PSW, !E+--O, BRK+--O
SP+--SP-2,(SP+ 1, SP)+--PS, PS+--TC
SP+--SP- 2,{SP+ 1 SP)+--PC PC+--TA
temp+--DW, AW
mem16
When temp-;-(memI6)~FFFFH
DW+--temp%(memI6),A W+--temp-;-(memI6)
When temp-;-(memI6) > FFFFH
TA+--(OOIH, OOOH), TC+--(003H, 002H)
SP+--SP-2,(SP+ I,SP)+--PSW, !E+--O, BRK +--0
SP+--SP-2,(SP+ 1, SP)+--PS, PS+--TC
SP+--SP-2,(SP+ 1 SP)+--PC PC+--TA
Signed Division Instructions
regS
temp-AW
DIV
When temp7regS>0, temp7regS~7FH or
temp7regS<0, temp7regS>0-7FH-1,
AH-temp%regS, AL-temp7regS
When temp7regS>0, temp7regS>7FH or
temp7 regS < 0, temp7tempS~0-7FH-1,
TA-(OOlH, OOOH), TC-(003H, 002H)
SP-SP-2,(SP+1, SP)-PSW, IE-O, BRK-O
SP-SP- 2,(SP+ 1, SP)-PS,PS-TC
SP-SP-2.(SP+ 1 SP)-PC PC-TA

1 1 1 1 0

1 1 0

1 1 1 1 0

1 1 1 1 0

1 1 0 mod

S Z

reg

19

2

u u u u u u

1 1 0

mem

24

2-4

u u u u u u

1 1 1 1 0

1 1 1 1 1 1 1 0

reg

25

2

u u u u u u

1 1 1 1 0

1 1 1 mod

1 1 0

mem

34

2-4

u u u u u u

1 1 1 1 0

1 1 0

1 1 1 1 1

reg

29-34

2

u u u u u u

-

I~

IiI !
I·~~

If

P

I
I
I
IiI~

I
I
I--

I

I
I
I
I

~

I

I

I
I

I
I
8.".

I
I'

Mnemonic

Operation

Signed Division Instructions (cont)
DIV
mem8
temp+-AW
When temp7(mem8»O, temp7(mem8)~7FH or.
temp7(mem8)< 0, temp7(mem8) >0 -7FH-1
AH-temp%(mem8), AL-temp7(mem8)
When temp7(mem8»O, temp7(mem8»7FH or
temp7(mem8)< 0, temp7(mem8)~0-7FH-1
TA-(001H, OOOH), TC-(003H, 002H)
SP-SP-2,(SP+1, SP)-PSW, IE-O, BRK-O
SP-SP-2,(SP+1, SP)-PS, PS-TC
SP-SP-2.(SP+1 SP)-PC PC-TA
regI6
temp-DW,AW
When temp7reg16>O, temp7reg16~7FFFH or
temp7reg16O-7FFFH-1
DW-temp%reg16, AW-temp7reg16
When temp7reg16>O, temp7reg16>7FFFH
temp7reg169FH, or CY=I
AL-AL+60H CY-I
ADJSB
When(AL AND OFH»9 or AC=I,
AL-AL-6, AH-AH-I, AC-I,
CY-AC AL-AL AND OFH
ADJ4S
When (AL AND OFH»9 or AC=1,
AL-AL-6, AC-I
When AL>9FH or CY=I
AL-AL-60H CY-I

II~.I

7 6 5 4 3 2

Operation Code
I 017 6 5 4

3 2

I

z

0

I

I

I

I

0

I

I

0 mod

I

I

I

mem

34-39

2-4

u u u u

I

1 I

I

0

I

I

1 I

I

I

I

1

reg

38-43

2

u

u

u

u

I

I

I

I

0

I

I

I

mod

I

I

1

mem

47-52

2-4

u

u

u

0 0

I

I

0

I

I' I

7

I

0 0

I

0 0

I

I

I

3

0 0

I

I

I

I

I

I

0 0

I

0

I

I

1 I

u

u

u

u

u u

u

x x u

u

u

I

x x u

x x x

7

I

x x u u u

3

I

x x u

-

u

u

x x x

I~

Ii

n
I
~

11

I
I
I

II

~

I
I
I
I

I
I

I

I

f
"I
N

I

I
I

I

I
I

I

Mnemonic

Operation

Data Conversion Instructions
CVTBD
AH-AL=OAH AL-AL%OAH
CVTDB
AH-O AL-AHXOAH+AL
CVTBW
When AL0 then begin
, repeat display -1 times

High-Performance 16-Bit Microprocessor

begin
SP=SP-2 ;
SP=BP-2 ;
(SP)=(BP) ;
end;
SP=SP-2 ;
(SP)=temp;

end;
BP=temp;
SP=SP-dynamics

Mode Operating Instructions
The LH70116 has two operating modes (Fig. 7).
One is the native mode, the other is the emulation
mode in which the instruction set of the 8080A is
emulated. A mode flag (MD) is provided to select
between these two modes. Native mode is selected
when MD is 1 and emulation mode when MD is O.
MD is set and reset, directly and indirectly, by executing the mode manipulation instructions.
Two instructions are provided to switch operation from the native mode to the emulation mode
and back: BRKEM (Break for Emulation), and RETEM (Return from Emulation).
Two instructions are used to switch from the
emulation mode to the native mode and back:
CALLN (Call Native Routine), and RETI (Return
from Interrupt).
The system will return from the 8080 emulation
mode to the native mode when the RESET signal is
present, or when an external interrupt (NMI or
INT) is present.

RESET, NMI, INT

BRKEM

I~ Emulation mode

Fig. 7

V30 Modes

LH70116 (V30)

EA. L=SS : (BP+offset)
The offset value is defined as the sum of the
frame size (referenced frame base) and the variable
from the base of the local variable area.
(2) Global variable access
The global variable is located at the address
added by the offset of variables which are referenced to the accessed value of the base pointer of
the old one saved on the stack frame.
The effective address EA. G is defined as below.
EA. G=SS : ((SS : (BP+offset 1)) + offset 2)
The offset 1 is defined by the offset value from
the frame base (BP) to the address stored by the
base address of the frame including the global variables.
The offset 2 is defined by the offset value from
the frame base including variables t,o be referenced
to the variables.
DISPOSE
I
This instruction releases the last stack frame
generated by the PREP ARE i.nstruction. It returns
the stack and base pointers to the values they had
before the PREP ARE instruction was used to call a
procedure.
SP=BP;
BP=(SP) ;
SP=SP+2
Check Array Boundary Instruction
This instruction is used to verify that index
values pointing to the elements .of an array data
structure ate within the defined range. The lower
limit of the array should be in memory location
mem32, the upper limit in mem32 + 2. If the index
value in reg16 is not between these limits when
CHKIND is executed, a BRK 5 will occur. This
causes a jump to the location in interrupt vector 5.
CHKIND regl6, mem32
When (mem32»regI6 or (mem32+2)

CLK~0r-

2.2 V

Test Points

<:><:=

AC Output Test Points

(7)

(3)

0.8 V

0.8 V

If

Read Timing (Small Scale)
T4

==>¢> Test Points «<=
2.2 V

~'I

BUSLOCK

0.8 V

2.2 V

tD]ct- _A____

~Df-.

2.2 V

0.8 V

(2)

BUSLOCK Output Timing

Tl

T2

T4

Clock Timing

CLK
tKKL

(4)

Wait (Ready) Timing
T2

Tl

TW

T3

T4

CLK
Ready--~

tSRYHK

*Read signal must be held at LOW or HIGH during this period.

(5)

POLL, NMI, INT InputTiming
Tn

CLK~
j~~l

POLL
NMI.INT

-

~~-----~________

-'-------....-.-.--SHARP - - - - - - - - - . - . . . . .

435

High-Performance 16-Bit Microprocessor

(8) Write Timing (Small Scale)

eLK

T4

Tl

T2

LH70116 (V30)

(10) Write Timing (Large Scale)
T4

T3

T4

Tl

T3

T2

T4

eLK
A19-PS3 ----1\1-,.r-:~--:-==:-'Ii:____\
Program Status
A16/PSO

UBE

Data Output

AD7-ADo

ASTB
(71088

ASTB

tDKCT I-

BUFEN
BUFR/W

Output)
BS2-BSo

\

Bus Status

/

tDKCT
- f:tWW-JCT

WR

IO/M"J(

(9)

Read Timing (Large Scale)

T4

Tl

T2

T3

T4

eLK

ASTB
(71088

Output)

'-~--------SHARP-'-''--------~

436

LH70116 (V30)

High-Performance 16-Bit Microprocessor

(11)

Interrupt Acknowledge Timing

BUFR/W

IO/M

~B-U-SL~O~C-K-'--------~

________________

(12)

~/~---------------

Hold RequesVAcknowledge Timing (Small Scale)

CLK
HLDRQ
HLDAK

~

________-I"

* - - - - - -______
*A'9/PS3-A'6/PSo, AD'5-ADo, RD, UBE 0, IO/M, BUFR/W,
~~~~~~JI

~

~---------I B~_
WR BUFEN

(13)

Bus RequesVAcknowledge Timing (Large Scale)

CLK

~ ~~~~ -¥~~ k_Y_'~
__

RQ/AK

'Pulse 1 RQ
.70116 Input

70116

__

___

Pulse 2 AK
70116 Output

.",';
..'.

Pulse 3 RQ
70116 Input

Jr-~_t_FK_A____~ ",?<","
~

_ _ _ _ _ _ __

:::; Coprocessor

-.----~-------SHARP~.--.--.---

437

. L.H70116 (V30)

High-Performance 16-Bit Microprocessor

Table 2 Operation COde Types

Table 1 Operand Types
Identifier
reg
reg8
reg16
dmem
mem
mem8
mem16
mem32
imm
imm16
imm8
imm4
imm3
acc
sreg
sr.c-table
src-block
dst-block
near-proc
far-proc
near-label
short-label
far-label
memptr16

memptr32

regptr16

pop-value

fp-op

R

438

Description
.a-or 16-bit general-purpose register
8-bit general-pourpose register
' 16-bit general-purpose register
8-or 16-bit direot memory location
8 -or 16-bit memory location
8-bit memory location
16-bit memory locotion
32-bit memory location
Constant (0 to FFFFH)
Constant (0 to FFFFH)
Constant (0 to FFH)
Constant (0 to FH)
Constant (0 to 7)
AW or AL register
Segment register
Name of. 256-byte translation table
Name of block addressed by the IX
register.'
Name of block addressed by the IY
register
Procedure within the current program
segment
Procedure located in another program
segment
Label in the current program segment
Label between - i 28 and + 127 bytes
from tbe end of instruction
Label in another program segment
Word containing the offset of the
memory location within the current
program segment to which control is to
be transferred
Double word containing the offset and
segment base address of the memory
location to which control is to be
transferred
16-bit register containing the offset of
the memory location within the
program segment to which control-is to
be transferred
Number of bytes of the stack to be
discarded (0 to 64K bytes, usually
even addresses)
Immediate data to identify the
instruction code of the external floating point operation
Register set

Identifier
W
reg
mem
mod
S:W
X,XXX,
YYY, ZZZ

Description
Word/byte field (0 to 1)
Register field (000 to 111)
Memory field (000 to 111)
Mode field (00 tQ 10)
When S: W=Ol or 11, data=16 bits.
At all other tii)les, data = 8 bits.
Data to identify the instruction code of
the external floating point arithmetic
chip

Table 3 Operational Description Types
Identifier
AW
AH
AL
BW
CW
CL
DW
SP
PC
PSW
IX
IY
PS
SS
DSo
DS,
AC
CY
P
S
Z
DIR
IE

V
BRK
MD
( ...)

disp
ext-disp8
temp

Description
Accumulator (16 bits)
Accumulator (high byte)
Accumulator (low byte)
BW register (16 bits)
CW register (16 bits)
CW register (low byte)
DW register (16 bits)
Stack pointer (16 bits)
Program counter (16 bits)
Program status word (16 bits)
Index register (source 16 bits)
Index register (destination 16 bits)
Program segment register (16 bits)
Stack segment register (16 bits)
Data segment 0 register (16 bits)
Data segment 1 register (16 bits)
Auxiliary carry flag
Carry flag
Parity flag
Sign flag
Zero flag
. Direction flag
Interrupt enable flag
Overflow flag
Break flag
Mode flag
Values in p~rentheses are memory
contents
Displacement (8 or 16 bits)
16-bit displacement (sign-extension
byte + 8-bit,displacement)
Temporary register (8/16/32 bits)
TA: Temporary register A (16 bits)
TB: Temporary register B (16 bits)
TC: Temporary register C (16 bits)

LH70116 (V30)

High-Performance 16-Bit Microprocessor

Operational Description Types (cont)
Identifier
tmpcy
seg
offset
<-

+

X

%
AND
OR
XOR
XXH
XXXXH

Description
Temporary carry flag (1 bit)
Immediate segment data (16 bits)
Immediate offset data (16 bits)
Transfer direction
Addition
Subtraction
Multiplication
Division
Modulo
Logical prod uct
Logical sum
Exclusive logical sum
Two-digit hexadecimal value
Four-digit hexadecimal value

Table 4
Identifier
(blank)

a
1
X
U
R

Description
No change
Cleared to a
Set to 1
Set or cleared according to the result
Undefind
Value seved earlier is restored

Table 5
mem
000
001
010
011
100
101
110
111

Operations

00
BW+IX
BW+IY
BP+IX
BP+IY
IX
IY
Direct address
BW

Memory Address

mod
01
BW + IX + disp8
BW + IY + disp8
BP+ IX +disp8
BP+IY+disp8
IX+disp8
IY+disp8
BP+disp8
BW+disp8

10
BW + IX +disp16
BW+IY+disp16
BP+ IX +disp16
BP+IY+disp16
IX+disp16
IY+disp16
BP+disp16
BW+disp16

Table 7
sreg
00
01
10
11

Selection of Segment Registers

PS
SS
DS o

The table on the following pages shows the instruction set.
At "No. of Clocks," for instructions referencing
memory operands, the left side of the slash (I) is
the number of clocks for byte operands and the
right side is for word operands. For conditional
control transfer instructions, the left side of the
slash (/) is the number of clocks if a control transfer takes place. The right side is the number of
clocks when no control transfer or branch occurs.
Some instructions show a range of clock times,
separated by a hyphen. The execution time of these
instructions varies from the minimum value to the
maximum, depending on the operands involved.
Note: Add four clocks these times for each word transfer made to
an odd ad.dress.

"No. of Clocks" includes these times:
Decoding
• Effective address generation
Operand fetch
Execution
It assumes that the instruction bytes have been
prefetched.

Table 6 Selection of a-and 16-Bit Registers (mod 11)
reg
000
001
010
011
100
101
110
111

w=o
AL
CL
DL

BL
AH
CH
DH
BH

W=l
AW
CW
DW
BW
SP
BP
IX
IY

439

LH70116 (V30)

High-Performance 16-Bit Microprocessor

Table 8

Mnemonic
. MOVBK
CMPBK
Note:

Table 9

LDM
STM
INM
OUTM
Note:

Byte clocks
(W=O)
.11 +Sn
(11)
7+14n
(13)

Word clock (W=I)
Odd, Even address
11+12n
(15)
7+1Sn
(17)

Odd, Odd address
11 +16n
(19)
7+22n
(21)

Even, Even address
l1+Sn
(11)
7+14n
(13)

Values in parentheses apply to the case of single processing.

Primitive 1/0 Instructions

Mnemonic
CMPM

(n: number of transfers)

Primitive Block Transfer Instructions

Byte clocks
(W=O)
7+10n
(7)
7+9n
(7)
7+4n
(7)
9+Sn
(10)
9+Sn
(10)

(n: number of transfers)

Word clock (W=l)
Odd address
Even address
7+10n
7+14n
(7)
(11)
7+13n
7+9n
(7)
(11)
7+Sn
7+4n
(11)
(7)
9+16n
9+Sn
(IS)
(10)
9+16
9+S
(10)
(IS)

Values in parentheses apply to the case of single proccesing.

-'-'---~----SHAR-P--~--~----~~

440

I
I
I
I
I
I
I

I

~

~
I

I

I
I
I
I
I

~I

Mnemonic

Operation

Ooeration Code

Oata Transfer Instructions
reg+-reg
MOV
reg,reg
1
mem reg
(mem)+-rell;
1
reg+-(mem)
reg, mem
1
(mem)+-imm
mem, imm
1
reg.... imm
reg, imm
1
acc, dmem
When W -0 AL+-(dmem)
1
When W=1 AH+-(dmem+ll. AL+-(dmem)
dmem, acc
When W=O (drem)+-AL
1
When W=1 (dmem+l)+-AH (dmem)+-AL
sreg, reg16 sreg+-regl6 sreg: SS OSO OSI
1
sreg, mem16 sreg+-(memI6) sreg:SS OSO OSI
1
reg16 sreg reg16+-sreg
1
mem16 sreg (mem 16)+-sreg
1
OSO, regl6, regI6+-(mem32)
1
mem32 ~
OSO+-(mem32 + 2)
OSI, regl6, regI6+-(mem32)
1
mem32
OSI+-(mem32+2)
AH PSW
AH+-S Z x AC x P x CY
1
PSW AH
S Z x AC x P x CY+-AH
1
LOEA rel<16 mem16 red6<--'meml6
1
TRANS src-table
AL+-(BW + AL)
1
reg, reg
reg.......... reg
XCH
1
mem, reg
(mem)-reg
1
or reg, mem
AW,reg16
AW .......... regl6
1
or rel<16 AW
Repeat Prefixes
REPC
While CW =/= 0, the next byte of the primitive 0
block transfer instruction is executed and
CW is decremented (-1). If there is a wait~
ing interru pt, it is processed. When CY =/= 1,
exit the loop.
REPNC
While CW =/= 0, the next byte of the primitive 0
block transfer instruction is executed and
CW is decremented (-1). If there is a waiting interrupt, it is processed. When CY=/=O,
exit the loop.
REP
While CW=/=O, the next byte of the primitive 1
REPE
block transfer instruction is executed and
REPZ
CW is decremented (-1). If there is a wait~
ing interrupt, it is processed. If the primi·
tive block transfer instruction is CMPBK or
CMPM and Z=/= 1 exit the loop.

1 W
oW
1 W
1 W
reg
0 o W

0
0
0
1
0
0

0
0
0
0
1
1

0 1
0 1
0 1
0 0
1 W
0 0

0
0
0
1

0

1 0 0

0

1 W

0
0
0
0
1

0
0
0
0
0

1
1
1
1
0

1
1
1
1
1

1
1
0
0
0

1 0
0
0
0
1
0
0

0
0
0
0
0

0 0

0 1
0 1
0 0
0 1
0 0
0 0

0 0

1
1
1
0
0
0

0
0
0
0
1

1 0 0

OJ

reg
1 1
reg
mod
reg
mod
mod 0 0 0

1 1
mod
1 1
mod
mod
mod

1 1 1
1 1 0
1 0 1 mod
1 1 1
1 1 W 1 1
1 1 W mod

0
0
0
0

reg
mem
mem
mem

2
9/13
11115
11115
4
10/14

2
2-4
2-4
3-6
2-3
3

9/13

3

sreg
sreg
sreg
sreg
reg

reg
mem
reg
mem
mem

2
11/15
2
10/14
18/26

2
2-4
2
2-4
2-4

reg

mem

18126

2-4

2
3
4
9
3
16124

1
1
2-4
1
2
2-4

reg

mem

reg
reg

reg
mem

reg

1 0

1

3
---_._-

---

11111111

S Z

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0

-

----=---------

1 0

0

1 0

1

2

1

1 1 0

0

1 0

0

2

1

0

1

2

1

1

1

1 1 0

1

I~

IfI

~
I~

I !-

x x
x x

x x x
x x x

I)

I
I
I
U
I~

Sf

I
I
I

I
I
I
I

~
~
"0

I

I

I

1

I
I
I
I

Mnemonicl

Ooerand

Operation

Repeat Prefixes (cont)
REPNE
REPNZ

While cw =fo 0, the next byte of the primitive
block transfer instruction is executed and
CW is decremented (-1). If there is a waiting interrupt, it is processed. If the primitive block transfer instruction is CMPBK or
CMPM and Z =fo 0 exit the 1000.
Primitive Block Transfer Instructions
MOVBK dst-block,
When W=O (IY)+-(IX)
DIR=O: IX+-IX+I, IY+-IY+1
DIR=I: IX+-IX-l, IY+-IY-l
src-block
When W=1 (IY+l, IY)+-(IX+l, IX)
DIR=O: IX+-IX+2, IY+-IY+2
DIR=1:IX+-IX-2 IY+-IY-2
When W -0 (IX)-(IY)
CMPBK src-block,
DIR=O: IX+-IX+l, IY+-IY+1
DIR=I: IX+-IX-l, IY+-IY-l
When W = 1 (IX + 1, IX)+-(IY + 1, IY)
dst-block
DIR=O: IX+-IX+2, IY+-IY+2
DIR=I: IX+-IX-2 IY+-IY-2
CMPM dst-block
When W=O AL-(IY)
DIR=O: IY+-IY+1; DIR=l:IY+-IY-1
When W=1 AW-(IY+l, IY)
DIR = 0: IY +-IY + 2; DIR = l:IY +-IY - 2
When W-O AL-(IX)
LDM
src-block
DIR=O: IX+-IX+l; DIR=I:IX+-IX-1
When W=1 AW+-(IX+l, IX)
DIR = 0: IX +-IX + 2; DIR = 1:1 X+-IX - 2
When W=O (IY)+-AL
STM
dst-block
DIR=O: IY+-IY+I; DIR=l:IY+-IY-1
When W=I(IY+l, IY)+-AW
DIR=O: IY+-IY+2; DIR=l:IY+-IY-2
Bit Field Transfer Instructions
INS
reg8, reg8
16-Bit field+-AW

EXT

reg8, imm4

16-Bit field-AW

reg8, reg8

AW+-16-Bit field

reg8, imm4

AW+-16-Bit field

Ooeration Code
1 017 6 5 4 3 2

S Z

7 6 5 4 3

2

1

1 1 0

0

1 0

2

1 0

1 0

0

1

o

W

See
1
Table 8

1 0

1 0

0

1

1 W

7+13n 1

1

1 0
1

x

x x

x

x x

x

x x

7+21n
1 0

1 0

1 1

1 W

See
Table
7-9

1

1 0

1 0

1

o

W

See
Table
7-9

1

1 0

1 0

1. 0

1 W

See
Table
7-9

1

1

n: number of transfers
0
1
0
1
0
1
0
1

0
1
0
1
0
1
0
1

0 0
reg
0 0
0 0
0 0
reR
0 0
0 0

1
1
0
1
1
0

1 1
reg
1 1
reg
1 1
reK
1 1
reg

1 0

0

1

1 0 0

0

1

1 0

0

1

1 1 0

0

1

1 0

0

1

1 0 0

1

1

1 0

0

1

1 1 0

1

1

31-117 3
35-133
31-117 4
35-133
26-55 3

134-59
26-55

134-59

4

x x

x

I~

If
IiI f
Ii
I
I
I
II
I~

I
I
I
I

I
I
I

I

I
'0

I

I

I
I
I
I
I
£I

Mnemonic

Operation

II 0 Instructions
IN
ace, imm8

When W=O AL+-(imm8)
When W=1 AH+-(imm8+1), AL+-(imm8)
ace, DW
When W=O AL+-(DW)
When W=1 AH+-(DW+l), AL+-(DW)
OUT
imm8, ace
When W=O (imm8)+-AL
When W=1 (imm8+1)+-AH (imm8)+-AL
DW, ace
When W -0 (DW)+-AL
When W= 1 (DW + 1)+-AH, (DW)+-AL
Primitive 110 InstructIOns
INM
dst-block, DW When W -0 (IY)+-(DW)
DIR=O: IY+-IY+1; DIR=l:IY+-IY-1
When W=1 (IY+1, IY)+-(DW+1, DW)
DIR=O: IY..-IY+2· DIR=l:IY+-IR-2
OUTM DW,src-block When W=O (DW)+-(IX)
DIR=O: IX+-IX + 1; DIR= l:IX+-IX-1
When W=1 (DW+1, DW)+-(IX+1, IX)
DIR=O: IX+-IX+2; DIR=1:IX+-IX-2
Addition/Subtraction InstructIOns
ADD
reg+-reg+ reg
r~, reg
mem reg
(mem)+-(mem) + reg
reg+-reg+(mem)
reg, mem
reg+-reg + imm
r~m imm
mem imm
(mem)+-(mem) + imm
ace, imm
When W=O AL+-AL+imm
When W=1 AW+-AW+imm
ADDC reg, reg
reg+-reg+reg+CY
mem rel(
(mem)+-(mem)+ reg+ CY
reg, mem
reg+-reg+ (mem) +CY
reg, imm
reg+-reg + imm + CY
mem imm
(mem)+-(mem) + imm + CY
ace, imm
When W-OAL+-AL+imm+CY
When W=1 AW+-AW+imm+CY
reg, reg
reg+-reg - reg
SUB
(mem)+-(mem) - reg
mem reg
reg+-reg- (mem)
reg, mem
reg+-reg-imm
reg, imm
(mem)+-(mem)-imm
mem imm
When W=O AL+-AL-imm
ace, imm
When W=1 AW+-AW-imm

m

11111111

Operation Code
1 017 6 5 4

S Z

7

6

5 4

3

2

1

1

1 0

0

1

o

W

9/13

2

1

1 1 0

1

1

o

W

8/12

1

1 0 0

1

1 W

8/12

2

1 1

3 2

1 0

1

1 1 0

1 1

1 W

8/12

1

0

1

1 0

1

o

W

See
Table
7-9

1

0

1

1 0

1 1

1 W

See
Table
7-9

1

1

n: number of transfers

Ii

IiI

~

0 0 1 W
0 0 o W
0 0 1 W
0 0 S W
0 0 S W
0 1 o W

reg
1 1
reg
mod
reg
mod
1 1 0 0 0
reg
mod

reg
mem
mem
reg
mem

2
16/24
11/15
4
18126
4

2
2-4
2-4
3-4
3-6
2-3

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

0 1
0 1
0 1
0 0
0 0
0 1

0
0
0
0
0
0

0 1 W
0 o W
0 1 W
0 S W
0 S W
1 o W

reg
1 1
reg
mod
reg
mod
1 1 0 1 0
mod 0 1 0

reg
mem
mem
reg
mem

2
16/24
11/15
4
18/26
4

2
2-4
2-4
3-4
3-6
2-3

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

1
1
1
0
0
1

1
1
1
0
0
1

0
0
0
0
0
1

1 1
mod
mod
1 1
mod

reg
reg
reg
1 0 1
1 0 1

reg
mem
mem
reg
mem

2
16/24
11/15
4
18126
4

2
2-4

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x'
x
x

x
x
x
x
x
x

x
x
x
x
x
x

0
0
0
1
1
0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
1
1
0

0
0
0
0
0
0

0
0
0
1
1
0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
0

1 W
W
1 W
S W
S W
oW

o

2~4

3-4
3-6
2-3

I~

11

I
I
I

U
I~

tl
I
I
I

I
I
I

Mnemonicl

"I

I

I
I
I
I
I
I

Operation

Addition/Subtraction Instructions (cont)
reg+-reg-reg:-CY
SUBC reg. reg
mem reg
(mem\+-(mem\-rel!-CY
rel!+-rel!-(mem\-CY
rel!. mem
reg+-reg- imm - CY
rel!. imm
(meml-(mem\-imm -CY
mem imm
ace, imm
When W-O AL+-AL-imm-CY
When W=1 AW+-AW-imm~CY
BCD Operation InstructIOns
.dst BCD string+-dst BCD string
ADD4S
+ src BCD string
SUB4S
dst BCD string+-dst BCD string
-src BCD string
CMP4S
dst BCD string-scr BCD string
ROL4

reg8

.

reg

~upperILowe~
L
4bits "bits

I
!.
~

Operand

mem8

mem

~upperlLoweJj
. L
.bits 4bits
.

ROR4

Operation Code

S Z

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0
0
0
0
1
1
0

0
0
0
0
0
0

0
0
0
0
0
0

1 0 1
1 0 o
1 0 1
0 0 0 S
0 0 0 S
1 1 1 o
1
1
1

W
W
W
W
W
W

reg
1 1
reg
mod
mod
r~
1 1 0 1 1
mod 0 1 1

reI!
mem
mem
reg
mem

2
16/24
11/15
4
18/26
4

2
2 4
2-4
3-4.
3-6 .
2-3

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x x
x x
x
x ~
x x
x x

0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 7+19n 2

u x

u u

u x

0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 7+19n 2

u x

u u

u x

0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 7+19n 2
n: number of :sCD digits divided by 2
0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 13
3
reg
1 1 0 0 0

u x

u u

u x

0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 28
mem
0 0

3-5

reg

~upperlLowe:l-j
ALL
4bits 4bits

0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 17
reg
1 1 0 0 0

3

mem8

mem

~UpperlLowerh
.
L_.(bits ..bits
.

0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0
mem
0 0 0

32

3-5

Increment/Decrement Instructions
reg8
reg8 .... reg8 + 1
INC
(mem)+-(mem)+ 1
mem
red 6+-red 6 + 1
red6
reg8+-reg8 -1
DEC
reg8
(mem)+-(mem)-1
mem
red6+-rel!16-1
red6

2
16/24
2
2
16124
2

2
2-4
1
2
2-4
1

1
1

1
1
reg
1 1
1 1
reg

0 1 1 0 0 0
W mod 0 0 0

reg
mem

0 1 1 0 0 1
W mod o 0 1

reg
mem

9>
~

I~

I~

I:

~od

1 1 1 1 1
1 1 1 1 1
0 1 0 0 0
1 1 1 1 1
1 1 1 1 1
0 1 0 0 1

Ii1
P

nod

-

reg8

I~
I~

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x'
x
x

x
x
x
,x
x
x

II
I
I

U
I~

I
I
I
I

I
I
I
I

I
'0

I

I

I
I
I
I
I
£I

Mnemonic

Operation

Multiplication Instructions
MULU reg8
AW-ALX reg8
AH=O: CY-O, V-O
AHfo: CY-l V-I
AW-ALX (memS)
mem8
AH=O: CY-O, V-O
AHfo: CY-l V-I
reg16
DW, AW-AWXregI6
DW=O: CY-O, V-O
Dwfo: CY-l V-I
mem16
DW, AW-AWX(memI6)
DW=O: CY-O, V-O
Dwfo: CY-l V-l
MUL
regS
AW-AL X regS
AH=AL sign expansion: CY-O, V-O
AH f AL sign expansion: CY -I V-I
mem8
AW-ALX (mem)S
AH = AL sign expansion: CY -0, V-O
AH f AL sign expansion: CY -I V-I
reg16
DW, AW-ALX (reg)S
DW = AW sign expansion: CY -0, V-O
DwfAW sign expansion: CY-l V-I
mem16
DW, AW-ALX(mem)8
DW=AW sign expansion: CY-O, V-O
DwfAW sign expansion: CY-l V-I
regl6,
regl6-regl6 X immS
(regI6,)
Product~16 bits: CY-O, V-O
immS
Product>16 bits: CY-l V-I
regl6,
regI6-(memI6)XimmS
mem16,
Product~16 bits: CY-O, V-O
immS
Product> 16 bits: CY-l V-I
regl6,
regl6-regl6 Ximm16
(regI6,)
Product~16 bits: CY-O, V-O
imm16
Product> 16 bits: CY-l V-I
regl6,
regI6-(memI6) Ximm16
meml6,
Product~ 16 bits: CY -0, V-O
imm16
PrQ9J!ct> 16!:>its: CY -1, V-I

7 6

ODeration Code
5 4 3 2 1 017 6 5 4 3 2 1 0

s z

1 1 1 1 0

1 1 0 1 1 1 0 0

reg

21-22

2

u x x u u u

1 1 1 1 0

1 1 0 mod

1 0 0

mem

27-2S

2-4

u x x u u u

1 1 1 1 0

1 1 1 1 1 1 0 0

reg

29-30

2

u x x

1 1 1 1 0

1 1 1 mod

mem

35-36

2-4

u x x u u u

1 0 0

U

u u

139-40
1

1 1 1 0

1 1 0 1 1 1 0 1

reg

33-39

2

u x x

1

1 1 1 0

1 1 0

mod

U

u u

1 0

1

mem

39-45

2-4

u x x u u u

1 1 1 1 0

1 1 1 1 1 1 0

1

reg

41-47

2

u x x u u u

1 1 1 1 0

1 1 1 mod

1

mem

47-53

2-4

u x x u u u

2S-34

3

u x x u u u

34-40

3-5

u x x

U

U

u

36-42

4

u x x

U

U

u

42-48

4-6

u x x

U

U

u

1 0

151-57
0

1 1 0

1 0

1 1 1 1

reg

reg

0

1 1 0

1 0

1 1 !Dod

reg

mem

13S-44
0

1 1 0

1 0 0

1 1 1

reg

reg

0

1 1 0

1 0 0

1 mod

reg

mem

146-52
--

I~

If

U
I !11

I
I
II

~
I~
I~

£1

I

I
I

I
I
I
I

I
1

I

I
I
I
I
I

I

Mnemonic
Operation
Unsigned Division Instructions
DIVU
reg8
temp-AW
When temp+regS~FFH
AH-temp%regS, AL-temp+regS
When temp+regS>FFH
TA-(001H, OOOH), TC-(003H, 002H)
SP-SP-2, (SP+1, SP)-PSW, IE-O, BRK-O
SP-SP-2, (SH 1, SP)-PS, PS-TC
SP-SP-2 (SH1 SP)-PC PC-TA
memS
temp-AW
When temp+(memS)~FFH
AH-temp%(memS), AL-temp+(memS)
When temp+(memS»FFH
TA-(001H, OOOH), TC-(003H, 002H)
SP-SP-2, (SP+1, SP)-PSW, IE-O, BRK-O
SP-SP-2, (SH1, SP)-PS, PS-TC
SP-SP-2. (SH1 SP)-PC,PC-TA
reg16
temp-DW, AW
When temp+reg16~FFFFH
DW-temp%reg16, AW-temp+reg16
When temp+reg16>FFFFH
TA~(001H, OOOH), TC-(003H, 002H)
SP-SP-2, (SP+1, SP)-PSW, IE-O, BRK-O
SP-SP- 2, (SH 1, SP)-PS, PS-TC
SP-SP-2 (SH1 SP)-PC PC-TA
mem16
temp-DW, AW
When temp+(mem16)~FFFFH
DW-temp%(mem16), AW-temp+(mem16)
When temp+(mem16»FFFFH
TA-(OOlH, OOOH), TC-(003H, 002H)
SP-SP-2, (SP+ I, SP)-PSW, IE-O, BRK-O
SP"=-SP-2, (SP+ I, SP)-PS, PS-TC
SP-SP-2 (SP+1 SP)-PC PC-TA
Signed Oi vision InstructIOns
DIV
reg8
temp-AW
When temp+regS>O, temp+regS~7FH or
temp+regSO-7FH-1
AH-temp%regS, AL-temp+regS
When temp+regS>O, temp+regS>7FH or
temp+regS0, temp-:-(mem8);;;;7FH or
temp-:-(mem8)0 -7FH-l
AH+-temp%(mem8), AL+-temp-:-(mem8)
When temp-:-(mem8)>0, temp-:-(mem8»7FH or
temp-:-(mem8)0 -7FH-l
TA+-(OOIH, OOOH), TC+-(003H, 002H)
SP+-SP-2, (SH1, SP)+--PSW, IE+-O, BRK+-O
SP+-SP-2, (SP+!, SP)+--PS, PS+-TC
SP+-SP-2, (SP+l SP)+--PC PC+-TA
reg16
temp+-DW, AW
When temp-:-reg16>O, temp-:-regI6;:i;7FFFH or
temp-:-reg160 -7FFFH-l
DW+-temp%regI6, AW+-temp-:-regI6
When temp-:-regl6>O, temp-:-regI6>7FFFH or
temp-:-regI6O, temp-:-(memI6);:i;7FFFH or
temp-:-(memI6)O-7FFFH-l
DW +1emp%(memI6), AW+1emp"'imemI6)
When temp"'imemI6)>O, temp"'imemI6»7FFFH or
temp-:-(memI6)9FH, or CY=1
AL-AL+60H CY-l
ADJBS
When (AL AND OFH»9 or AC-1,
AL-AL-6, AH-AH -1, AC-1,
CY-AC AL-AL AND OFH
ADJ4S
When (ALAND OFH»9 or AC=1,
AL-AL-6, AC-1
When AL>9FH or CY=1
AL-AL-60H CY-1

uru

Operation Code

S Z

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0
1 1 1 1 0

1 1 0 mod

1 1 1

mem

34-39

2-4

I~

u u u u u u

U

1 1 1 1 0

1 1 1 1 1 1 1 1

reg

1 1 1 1 0

1 1 1 mod

mem

1 1 1

38-43

2

43-48 2-4
147-52

u u u u u u

u

u u u u u

0 0

1 1 0

1 1 1

7

1

x

x

u u u u

0 0

1 0 0 1 1 1

3

1

x

x

u x x x

0 0

1 1 1 1 1 1

7

1

x

x

u u u u

0 0

1 0

3

1

x

x

u x x x

1 1 1 1

U
II
11

I
I
I
U
1
<
.9

£I

I

Mnemonic

Operation

Rotation Instructions
reg, 1
ROL

I
I

mem, 1

reg, CL

I
I

mem,CL

I

reg, imm8

I

r

mem, imm8

N

'0

I

I

I
I
I
I
I

I

ROR

reg, 1

mem, 1

reg, CL

mem,CL

7 6 5 4 3

CY-MSBof reg, reg-regX2+CY
MSB of reg+CY: V-I
MSB of reg=CY:V-O
CY -MSB of (mem),
(mem)""':'(mem) X 2+ CY
MSB of (mem)+CY:V-l
MSB of (mem)=CY:V-O
temp-CL, while temp+O,
repeat this operation, CY-MSB of reg,
reg-reg X 2 + CY
temp-temp-l
temp-CL, while temp+O,
repeat this operation, CY-MSB of (mem),
(mem)-(mem) X 2 + CY
temp-temp -1
temp-imm8, while temp+O,
repeat this operation, CY-MSB of reg,
reg-reg X 2 + CY
temp-temp-l
temp-imm8, while temp+O,
repeat this operation, CY-MSB of (mem),
(mem)-(mem) X 2 +CY
temp-temp-l
CY-LSB of reg-reg-;-2
MSB of reg-CY
MSB of reg+bit following MSB of reg: V-I
MSB of reg=bit following MSB of reg: V-O
CY-LSB of (mem),(mem)-(mem)-;-2
MSB of (mem) X CY
MSB of (mem)+bit following MSB
of (mem): V-I
MSB of (mem)=bit following MSB
of (mem): V-O
temp-CL, while temp+O,
repeat this operation, CY-LSB of reg,
reg-reg-;- 2, MSB of reg-CY
temp-temp-l
temp-CL, while temp+O,
repeat this operation, CY-LSB of (mem),
(mem)-(mem)-;-2, MSB of (mem)-CY
temn-temn-l
---

-----------

2

Operation Code
1 017 6 5 4 3

2

S Z

1 0

1

1 0

1 0 0

o

W 1 1 0

o

0

reg

2

2

x

x

1

1 0

1 0 0

o

W mod

0

0 0

mem

16

2-4

x

x

1

1 0

1 0 0

1 W 1

1 0

0 0

reg

7+n

2

x

u

1

1 0

1 0

1 W mod

0 0 0

reg

19+n

2-4

x

u

1 0 00

reg

7+n

3

x

u

mem

19+n

3-5

x

u

0

1 1 0 0

0 0

o

W 1

1

1 0 0

0

0

o

W mod

1

1 0

1 0

0

1

1 0,1

0 0 0

n: number of shifts
oW 1 1 0 0

o

0 0

W mod

1

reg

2

2

x

x

0 Q 1

mem

16

2-4

x

x

1 1 0

1 0

0

1 W 1 1 0

0

1

reg

7+n

2

x

u

1 1 0

1 0

0

1 W ' mod

0

1

mem

19+n

2-4

x

u

0

n: number of shifts
---------

~~-----

..

-

I~

Ii

n
I
~

I~

P
I
I
I
U
I~

I
I

I
I
I
I
I
I

f

N
"0

I

I

I
I
I
I
I
£I

Mnemonic

Operation

Rotation Instructions (cont)
ROR
reg, imm8
temp+-imm8, while temp+O,
repeat this operation, CY +-LSB of reg,
reg+-reg-;- 2, MSB of reg+-CY
temp+-temp-l
mem, imm8 temp+-imm8, while temp+O,
repeat this operation, CY+-LSB of (mem),
(mem)+-(mem) -;- 2,
temp+-temp -1
ROLC
reg, 1
tmpcy+-CY, CY+-MSB of reg
reg+-regX 2+tmpcy
MSB of reg=CY: V+-O
MSB of reg+CY: V+-l
mem, 1
tmpcy+-CY, CY+-MSB of (mem)
(mem)+-(mem) X 2 + tmpcy
MSB of (mem)=CY: V+-O
MSB of (mem)+CY: V+-l
reg, CL
temp+-CL, while temp+O,
repeat this operation, tmpcy+-CY,
CY+-MSB of reg, reg+-regX2+tmpcy
temp+-temp-l
mem,CL
temp+-CL, while temp+O,
repeat this operation, tmpcy+-CY,
CY +-MSB of (mem),
(mem)+-(mem) X 2 +tmpcy
temp+-temp-l
reg, imm8
temp+-imm8, while temp+O,
repeat this operation, tmpcy+-CY,
CY+-MSB of reg, reg+-regX2+tmpcy
temp+-temp-l
mem, imm8 temp+-imm8, while temp+O,
repeat this operation, tmpcy+-CY,
CY +-MSB of (mem)
(mem)+-(mem) X 2 +tmpcy
temp+-temn-1

Operation Code

Flal!s
ACCY V P S

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0
1

1

0 0 0 0

o

W 1

1

1

0 0 0 0

o

W mod

1

1

0 1 0 0

o

W 1

1

1

0 1 0 0

o

W mod

1

1

0

1

1

1

1

1

0 0

1

reg

7+n

3

x

u

0 0

1

mem

19+n

3-5

x

u

n: number of shifts

0

1

0

reg

2

2

x

x

0

1

0

mem

16

2-4

x

x

1

0

1

0

reg

7+n

2

x

u

0 1 0 0

1 W mod

0

1

0

mem

19+n

2-4

x

u

1

0 0 0 0

o

W 1

1

0

1

0

reg

7+n

3

x

u

1

0 0 0 0

o

W mod

0

1

0

mem

19+n

3-5

x

u

1

0 0

1 W 1

1

Z

I~

II
IiI f'
11

I
I

n: number of shifts

I

U
I~

OJ

11111111

g

I
I
I
I
I
I
I
I

!

~

'tJ

I

I

I
I
I
I
I
I

Mnemonic

Operation

Rotation Instructions (cont)
RORC
reg, 1
tmpcy-CY, CY-LSB of reg
reg-reg72, MSB of reg-tmpcy
MSB of regi' bit following MSB of reg: V-I
MSB of reg=bit following MSB of r~ V-O
mem, 1
tmpcy-CY, CY-LSB of (mem)
(mem)-(mem)72,MSB of (mem)-tmpcy
MSB of (mem)i'bit following MSB
of (mem): V-I
MSB of (mem)=bit following MSB
of (mem): V-O
reg, CL
temp-CL, while tempi'O,
repeat this operation, tmpcy-CY,
CY-LSB of reg, reg-reg72,
MSB of reg-tmp_CYi temp-temp-l
mem,CL
temp-CL, while tempi'O,
repeat this operation, tmpcy-CY,
CY-LSB of (mem), (mem)-(mem)72
MSB of (mem)-tmpcy. temp-temp-l
reg, imm8
temp-imm8, while tempi'O
repeat this operation, tmpcy-CY,
CY -LSB of reg, reg-r~g7 2
MSB of reg-tmpcy. temp-temp-l
mem, imm8 temp-imm8, while tempi'O,
repeat this operation, tmpcy-CY,
CY-LSB of (mem), (mem)-(mem)72
MSB of (mem)+'-tmpcy, temp-temp-l
Subroutine Control Instructions
(SP-l, SP-2)-PC, SP-SP-2
CALL
near-proc
PC-PC+disp
(SP-:-l, SP- 2)-PC, SP-SP- 2
regptr16
PC-regptr 16
(SP-l, SP-2)-PC, SP-SP-2
memptr16
PC-(memptr 16)
(SP-l, SP-2)-PS, (SP-3, SP-4)-PC
far-proc
SP-SP-4 PS-seg, PC-offset
(SP-I, SP-2)-PS, (SP-3, SP-4)+-PC
memptr32
SP-SP-4, PS-(memptr32 + 2),
PC-(memptr32)

Operation Code

S Z

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0
1 0 0

o

W 1 1 1 0 1

reg

2

2

x

x

1 1 0 1 0 0

o

W mod

0 1 1

mem

16

2-4

x

x

0 1 0 0 1 W 1 1 0 1 1

reg

7+n

2

x

u

0 1 1

mem

19+n

2-4

x

u

1

1 0

11

1 1 0

1 0 0

1 W mod

1 1 0 0 0 0

o

W 1 1 0 1 1

reg

7+n

3

x

u

1 1 0 0 0 0

o

W mod

mem

19+n

3-5

x

u

16

3

0 1 1

n: number of shifts
1

1 0

1 0 0 0

1 1

1 1

1 1

1

1 1

1

1

1

1 0 0
1

1

1

1 1

1 0

1 1 1

1 1

1

1 0

reg

14

2

0 1 0

mem

23

2-4

21

5

31

2-4

1 1 0

1 mod

1 0
1 1

mod

0 1 1

mem

I~

Ii

Ii
I~

11

I
I
I

U
I~

I
I
I
I

I

I
I
I

!)

N

'0

I
I
I
I
I
I
I
~I

Mnemonicl

Ooerand

Operation

7 6

Subroutine Control Instructions (cant)
RET
PC-(SP+ 1 SP), SP-SP+ 2
pop-value
PC-(SP+ I, SP),
SP-SP + 2 SP + DoD-value
PC-(SP+l, SP), PS-(SP+3, SP+2)
SP-SP+4
pop-value
PC+---(SP+l, SP), PS-(SP+3, SP+2)
SP-SP + 4 SP-SP + oop-value
Stack Manipulation InstructIOns
SP-SP-2 (SP+ 1 SP)-(memI6)
PUSH mem16
SP-SP-2 (SP+l SP)-reg16
red6
sreg
SP-SP - 2 (SP + 1 SP)-sreg
PSW
SP-SP-2 (SP+ 1 SP)-PSW
R
Push registers on the stack
imm
(SP-l, SP-2)-imm
SP-SP-2 When S=1 sign extension
POP
mem16
(memI6)-(SP+l SP), SP-SP+2
reg16
regI6-(SP+ 1 SP). SP-SP+ 2
sregsreg+-(SP+ I, SP) sreg: SS, DSO, DSI
SP-SP+2
PSW
PSW -(SP + 1 SP).SP-SP + 2
R
POD registers from the stack
PREPARE imm16, imm8 Prepare new stack frame

- -

DISPOSE
Disj)os~ of stack frame
Branch InstructIOn
BR
near-label
PC-PC+disp
short-label PC-PC+ext-disp8
regptr16
PC-regptrl6
memptr16
PC-(mem~trI61
far-label
PS-seg. PC-offset
memptr32
PS-(memptr32+ 2). PS-(memptr32)
Conditional Branch Instructions
BV
short-label if V=1 PC-PC+ext-disp8
BNV
short-label if V=O PC-PC+ext-disp8
BC BL short-label if CY= 1 PC-PC+ext-disp8
BNCBNL short-label if CY -0 PC-PC+ext-disp8
BE BZ short-label if Z= 1 PC-PC+ext-disp8
BNEBNZ short-label if Z=O PC-PC+ext-disp8
BNH
short-label if CY OR Z-1 PC-PC+ext-disp8
BH
short-label if CY OR Z=O PC-PC+ext-disp8
BN
short-label if S= 1 PC-PC+ext-disp8
BP
short-label if S=O PC-PC+ext-disp8
BPE
short-label if P= 1 PC-PC+ext-diso8
-

5 4

3 2

Ooeration Code
1 017 6 5 4

S Z

3 2 1 0

1 1 0 0 0 0 1 1
1 1 0 0 0 0 1 0

15
20

1
3

1 1 0 0

1 0

1 1

21

1

1 1 0 0

1 0

1 0

24

3

-

1
0
0
1
0
0

-

1
1
0
0
1
1

-

~-

1 1 1
0 1 0
o sreg
0 1 1
1 0 0
1 0 1

1 1
reg
1 1
1 0
0 0
0 S

1 mod

18
8
8
8
35
7 or 8

2-4
1
1
1
1
2-3

0 0 0

mem

17
8
8

2-4
1
1

8
43

1
1
4

1 0 1
0 0 1
0 0 0
16
23+16 (imm8-1)
0 0 1I

1
1
1
1
1
1

1
1
1
1
1
1

1
1
1
1
1
1

0
0
1
1
0
1

1
1
1
1
1
1

0
0
1
1
0
1

0
1
1
1
1
1

1
1
1 1 1 1 0 0
1 mod 1 0 0
0
1 mod 1 0 1

0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1

0
0
0
0
1
1
1
1
0
0
0

0
0
1
1
0
0
1
1
0
0
1

0
1
0
1
0
1
0
1
0
1
0

*
-

-

reg
mem
mem

6

U
I~

L- _ _

mem

1 0 0 1 1
0 1 1 0 0
1 1 0 0 1
imm8<0:
imm8<1:
1 1 0 0 1

*:

-

II

1 1 0

0
0
0
0

1 0 0 0 1 1 1 1 mod
reg
0 1 0 1 1
1 1 1
0 0 o sreg

-

-

1

I~

R R R R R R

-

13
12
11
20
15
27

3
2
2
2-4
5
2-4

14/4
14/4
14/4
14/4
14/4
14/4
14/4
14/4
14/4
14/4
14/4

2
2
2
2
2
2
2
2
2
2
2

11

I
I
I
U
I~

~

I
I
I
I
I
I

I'

I

!
N

"I
I
I
I
I
I
I
I

Mnemonicl

Ooerand

Operation

Ooeration Code

7 6 5 4 3 2 1 017 6 5 4 3 2 1 0

Conditional Branch Instructions (cont)
BPO
short-label if P=O PC-PC+ext-diso8
0 1
BLT
short~ label
if S XOR V-I PC-PC+ext-diso8
0 1
BGE
short-label if S XOR V -0 PC-PC+ext-disp8
0 1
BLE
short-label if (S XORV) OR 2=1 PC-PC+ext-disp8 0 1
BGT
short-label if (S XOR V) OR 2=0 PC-PC+ext-disp8 0 1
DBNZNE short~label CW-CW-l
1 1
if 2=0 and CW+O PC-PC+ext-disp8
DBN2E short-label CW-CW-l
1 1
if 2= 1 and CW+O PC-PC+ext-disp8
DBN2 short-label CW-CW-l
1 1
if CW+O PC-PC+ext-diso8
BCW2 short~label if CW -0, PC-PC+ext-disp8
1 1
Interrupt Instructions
BRK
TA+-(OODH, OOCH), TA+-(OOFH, OOEH)
1 1
3
SP+-SP-2, (SP+ 1, SP)-PSW, IE+-O, BRK +-0
SP-SP-2, (SP+l, SP)-PS, PS-TC
SP-SP-2 (SP+l SP)-PC PC-TA
imm8
TA+-(4n+1, 4n), TC+-(4n+3, 4n+2) n-Imm8
1 1
SP+-SP-2, (SH1, SP)+-PSW, IE+-O, BRK+-O
(+3)
SP+-SP-2, (SH 1, SP)+-PS, PS+-TC
SP+-SP-2. (SP+1 SP)+-PC PC+-TA
BRKV
WhenV=l
1 1
TA+-(OllH, 010H), TC+-(013H, 012H)
SP+-SP-2, (SH1, SP)+-PSW, IE+-O, BRK+-O
SP+-SP-2, (SP+ 1, SP)+-PS, PS+-TC
SP+-SP~2 (SH1 SP)+-PC PC+-TA
RETI
PC-(SP+1, SP), PS-(SP+3, SP+2),
1 1
PSW-(SP+5 SP+4), SP-SP+6
CHKIND reg16,
When (mem32»reg16 or (mem32+2)< 0 1
reg16
mem32
TA+-(4n+1, 4n), TC+-(4n+3, 4n+2) n=
imm8
SP-SP- 2, (SP+ 1, SP)+-PSW, MO+-O
MD Bit Write Enable
SP-SP- 2, (SP+ 1, SP)-PS, PS+-TC
SP-SP-2 (SP+1 SP)-PC PC+-TA
BRKEM imm8
TA+-(015H, 014H), TC+-(017H, 016H)
o 0
SP-SP-2, (SH 1, SP)+-PSW, IE-O, BRK-O
SP-SP-2, (SH 1, SP)-PS, PS-TC
SP-SP-2 (SP+ 1 SP)+-PC PC-TA

S 2

0
1
0
1
0

14/4
14/4
14/4
14/4
14/4
14/5

2
2
2
2
2
2

1 0 0 0 0 1

14/5

2

1 0 0 0 1 0

13/5,

2

1 0 0 0

1 1

13/5

2

o

0

1 1

o

0

38

1

o

0

1

1 0

1

38

2

o

0

1 1 1 0

40/3

1

o

0

1 1 1 1

27

1

1
1
1
1
1
1

1
1
1
1
1
0

1
1
1
1
1
0

0
1
1
1
1
0

1 000

0 0

1
0
0
1
1
0

1

1 0 mod

reg

mem

1 1 1 1 1 1 1 1 1 1 1 1

53-56/ 2-4
18

38

3

I~

III !
I~
I~
I~

P

,I
R R R R R R

I
II

I~
I~

Ij

I
I
I
I

I
I

1

I

!"
I

I
I
I
I
I
I

Mnemonic

Operation Code

Operation

CPU Control Instructions
HALT
CPU Halt
BUSBus Lock Prefix
LOCK
fp-op
FPOI
No Operation
fp-op, mem data bns+-(meml
fp-op
FP02
No Operation
fp-op, mem data bus+-(meml
POLL
Poll and wait
NOP

DI

S Z

7 6 5 4 3 2 1 DI7 6 5 4 3 2 1 0

No Operation
IE+-O
IE+-l

EI
SOSO Mode InstructIOns
RETEM
PC+-(SP+ I, SP), PS+-(SP+ 3, SP+ 2),
PSW+-(SP+5, SP+4), SP+-SP+6, MD Bit
Write Disable
CALLN immS
TA+-(4n+1, 4n), TC+-(4n+3, 4n+2) n=imm8
SP<-SP-2, (SP+1, SP)<-PSW, MD<-l
SP<-SP-2, (SP+1, SP)<-PS, PS<-TC
SP+-SP-2, (SP+1 SPj+-PC PC+-TA
Data Conversion Instructions
CVTBD
AH+-AL=OAH AL+-AL%OAH
CVTDB
AH+-O AL+-AHXOAH+AL
CVTBW
When AL
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:10:21 07:19:10-08:00
Modify Date                     : 2013:10:21 07:23:09-07:00
Metadata Date                   : 2013:10:21 07:23:09-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:3a1caabd-b3c4-e044-973d-fa20228a6fa5
Instance ID                     : uuid:e76af027-759d-5d4a-8071-49118d648a49
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 470

EXIF Metadata provided by EXIF.tools