1990_Siemens_ICs_for_Communications 1990 Siemens ICs For Communications
User Manual: 1990_Siemens_ICs_for_Communications
Open the PDF directly: View PDF 
.
Page Count: 748
| Download | |
| Open PDF In Browser | View PDF |
-m
SIEMENS
~
m
Z
en
ICs for Communications
Databook
oen
o
o
:3
:3
c
:::J
o
0)
r-+-
o
:::J
en
.........
CD
CD
o
.............
CD
.........
1990/91
ICs for Communications
Data Book 1989/90
Siemens Components. Inc.
Published by Siemens Integrated Circuit Division
2191 Laurelwood Rd., Santa Clara, CA 95054
For the circuits, descriptions, and tables indicated no responsibility is assumed as far as patents
or other rights of third parties are concerned.
The information describes the type of component and shall not be considered as assured
characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery, and prices please contact the Offices of Siemens
Components.
Table of Contents
Summary of Types
General Information
ICs for Digital Exchange Systems
ICs for ISDN Exchange Systems
ICs for ISDN Terminals
Support Tools
ICs for Data Communication
Package Outlines
Siemens Sales Office Listings
I
I
Table of Contents
Summary of Types
Contents
Summary of Types
Page
1. Types in alphanumerical order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. Types in application-oriented order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
12
General Information
1.
2.
3.
4.
5.
6.
Type designation code for ICs ..............................................
Mounting instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processing guidelines for ICs ...............................................
Data classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quality assurance .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of the most important symbols .....................................
17
17
20
23
24
28
Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
Package Outlines .................................................................. 727
Siemens Sales Office Listings . ...................................................... 743
Siemens Components, Inc.
7
Summary of Types
1.1 Types in Alphanumerical Order
Type
S PEB 2025·P, .
PEB 2035·C
S PEB2035~N
PEB 2035-P
PEB 2045-C
S PEB2045~N
PEB 2045-P
PEB 2046·C
S PEB 2046-N·
PEB 2046·P
PEB 2050-C
S PEB2050-N
PEB 2050-P
'Y PEB 2052-C
'YS PEB 2052~N
'Y PEB 2052-P
'Y PEB 2055-C
'YS PEB 2055~N
'Y PEB 2055-P
'Y PEB 2056-C
'YS PEB2056-N
'Y PEB 2056-P
SPEB2060·N
PEB 2060-P
PEB 2070-C
SPEB2070-N
PEB 2070-P
'YS PEa2b75~N'
'Y PEB 2075·P
PEB 2080-C
s~eB2b'~;;N
PEB 2080-P
S PEB2081~N
PEB 2081-P
Ordering Code
Function
Page
067100·H6038 ISDN Exchange Power Controller (lEPC) ...•..•••• 227
067100-H8358 Advanced CMOS Frame Aligner (ACFA) .........
44
067100-H8684 Advanced CMOS Frame Aligner (ACFA) ..•.•••••. 44
067100-H8359 Advanced CMOS Frame Aligner (ACFA) . . . . . . . . . .
44
067100-H8323 Memory Time Switch CMOS (MTSC) . . . . . . . . . . . . .
90
067100"H8602 Memory Time SwitchQMOS (MTSC) ......... ~ •••. ;
90
90
067100-H8322 Memory Time Switch CMOS (MTSC) . . . . . . . . . . . . .
0671 00·H61 03 Memory Tir:ne Switch Small (MTSS) . . . . . . . . . . . . . . 119
067100-H6104 Memory Time Switch Small (MTSS)......... ...•••••• 119
0671 00-H61 05 Memory Time Switch Small (MTSS) . . . . . . . . . . . . . . 119
067100-Z157
Peripheral Board Controller (PBC) ............... 136
067100-H8392 Peripheral Board Controller (PSC) ...•.......... .136
067100-H3032 Peripheral Board Controller (PBC) ................ 136
067100-H6059 PCM Interface Controller(PIC) ....... ~.......... 154
.' 0671 QQ-He060 . PCM tnt~r:1a.¢e ContrcSUer (PIC) .•.•.•••• ;.; •
154
067100-H6061 PCM Interface Controller (PIC) .................. 154
067100-H6034 Extended PCM Interface Controller (EPICTM-1) .... 242
C)67100-H6035 . ExtendedPCM Interface ControJler(EPtCTM·t) .• : .'242
067100-H6036 Extended PCM Interface Controller (EPICTM-1) . . . . 242
067100-H6117 ExtendedPCMlnterface Controller (EPICTM-2) .... 274
Q67100·H6118 ',E)ctend$dPCM Intertace Controller(EP1CTM~2). . . . 274
067100-H6115 Extended PCM Interface Controller (EPICTM·2) . . . . 274
0671 OO~H8393 Signal proceSsing Codec Filter (SlCOFI@) ..•.•... 167
067100-Z170
Signal Processing Codec Filter (SICOFI®) ........ 167
067100-H8328 ISDN Communications Controller (ICC)..... ... ... 276
Q67100-H8394 ISPNCommYoicatfons ControUer(IC¢). ~ . . . . . . . . .276
067100-H2953 ISDN Communications Controller (ICC). . .. . . . . . . . 276
Q67100-HS6$S'ISDNp-Cha.r;lnel excha:hgeContro~;(IDEC) ••• .•. ; .316
067100-H8682 ISDN D-Channel Exchange Controller (IDEC) ..... 316
0671 OO ••H8329 . . . '.' S-8us Inte.rface Circuit (SBC) ;' .. . . . . . . . .. . . . .. . . 339
fI~'t1tiQ~H839i;;: $f~US IntM$Qfil pircUlH$eQ}:i;. ; ,\
'
.
;$3$
S·us Interface Circuit (SBC) ....... ~ .... ~ ......... 339
Q67100~H609:f'
Ifrt€1t1ace Circuit:extended~};:., '" •,:381
067100-H6091 SIT Bus Interface Circuit Extended (SBCX) . ...... 381
067100-H?954
strsus
-.=New Type
S= Surface Mounted Device (SMD)
SICOFI®, IOM®, ARCOFI®, ISACTM_S, ITACTM, IPATTM, ISACTM-P, EPICTM are registered trademarks of Siemens AG
Siemens Components, Inc.
9
I
Summary of Types
Page
s iIti ..iit4 G;Bf;It1lt~ttM";i t:1f~~I~:rau~fil)'t
PEB 2085-P
PEB 20901-C
4SS
495
415
.slHi~.
415
• PEB 20901-P
PEB 20902-C
067100-H8678
067100-H8680
PEB 20902-P
• PEB 2091-C
067100-H8681
415
415
.s "~IUIIaj.N .~.lgftji' i'l .
415
415
442
.s ·~·U.~·i
r::~A',mru......:.
j~42
PEB 2095-C
459
st••111-iI
:459
459
485
.~$5
485
70
: 7e
70
'1941
90
}1~~
90
119
:H9
119
s
·s
Siemens Components, Inc.
10
Summary of Types
Type
Ordering Code
Function
H~l&V~ISerlat;Cdmmllhl~"QkS>:'
Contro"er.e~ ~HSC>i).:,',. .,...... '.~., •.
High-Level Serial Communications
Controller (HSCC),," ........... : .. ~
Hrgt,l~l:..v.,se~al' c~mmttfilcMiOrts
~n~rOfl"'(1'iI$¢C)'>:i';};
,
S
SAF 82520-P
~SMF
l' ~!;~·,~t,/: .
~S~,
STU 2050
STU20S0
STUT20S0
High-Level Serial Communications
Controller (HSCC) : ... : ................ ,:' . . ,: . :658
';',~> ··.I~:>,··:::~~tll~~t
Q67100-Z166
QS7100-H3238
QS7100-HS058
Siemens Components, Inc.
PBC User Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SICOFI® User Board... ............... .........
SICOFI® Test 60ard ...........................
11
214
217
219
Summary of Types
1.2 Types in Application-Oriented Order
Page
ICs for Digital Exchange System
s M_~i,~+~,~}f\~{?i,~_ _~1}ii~~.1~~?l~~i~~~'r~i~~~~~~::t{1~~1'~:{;{,;J:~~·;
PEB 2035-P
Advanced CMOS Frame Aligner (ACFA) " " " " " " " " , , 4 4
:~,g~,~)~;~.,."".) ,,,,),t!~~~ri!1l~~,t'o~'~~~s, ~~f~l~~e~,,~~~~~l; ;' ,.::,.:, ~.' ':;'/;,' . •. ' ",,?-O
S!R.~~N5,·:1;~;.};'1:\:rjS~~If~,~~~IN'~;'~"l~'.l;'!f:·~;..:,£i;;f;t~";:,;;:';2':';l:fQ'
PEB 2235-P
ISDN Primary Access Transceiver (IPATTM) "",.".,.""
70
s ~~Wl$~~~·~·'N·0ft';f~';·~'_ _:~_ _ _~~:Aij~~;~,1;~j:';.i;.:~ti;i~i;:~\;i~§ . :.:6'
~
PEB 2045-P
PEF 2045-C
Memory Time Switch CMOS (MTSC) ... , . " , , , . , . , . , , , . , .
Memory Time Switch CMOS (MTSC) , .. , . , , , , ..... , , , , . , ,
90
90
PEF 2045-P
PEB 2046-C
Memory Time Switch CMOS (MTSC) , , , , , , , . , .. , , , , , , , . , ,
Memory Time Switch Small (MTSS), . , , , , . , . , . , , , , , , .... ,
90
119
PEB 2046-P
PEF 2046-C
Memory Time Switch Small (MTSS) , , , , ... , , , , , , , , . , .. , . .
Memory Time Switch Small (MTSS) . , . , . , ., , .,.,.,. .,.
119
~S ~j9f~~tji.~J;~J~l,,~;.~;g·~~~~'~~~::.f:;;.i;'h&~:£::~'L:.'.~:~~::!·~.··~~'d·~;;:;';('i~
~
~
~S ,~.·~J,~JSiJ~3.l.~.s~.l'.~}i\I~f~Jj:;;'J·;J,0:~·.t;%)j.li'. ;;{;,2);'L;);:i,?~1~
~
~
~S ~~~£I·U·Nif~rt(jtfil~~·~~.~t,$j
..•
~
PEF 2046-P
Memory Time Switch Small (MTSS) ...... , ........... , . . . 119
PEB 2050-C
'.' . Peripheral Board Controller(PBC)~ ... ~'.'.".' ~ ........ : .... : 136
S ~ •._~2;~N!\?1~:;l\7g\~Af;I~~(rpji{~;:f·ji}4;,,\;i:i;\:·;;. ;;:i2~'~;{i'fiii~\:I;i\:if~
PEB 2050-P
Peripheral Board Controller (PBC) ,.", .. ".",., .. ".,.' 136
~ PEB 2052-C
..
PCM Interface Controller (PIC) .. " .. ", .... , ..~. , , , . ,. , . , 154
~S f.~~J~{~)ftl~~N'aI}iljllAYl~"}iMAi\;;.':S;;J+J,1L~~~ ],;.;l~:':;J,\r)l.;:\};J:.).:;;;l;;,:~.~
. ,;,; .;::. ',' .:'.:'. ;:;'., ".:.
~ )F§~,~~;~.
.~~}~I~~~~1rt19~,~
)J5~.
S f!1:~~~Y;'~;N;i~{;~ltY;~'lD~J'~ ;"". ,~.. .. . '~"lll'l~~·A~l:.):::f{;'~;j.i:;'4):~f~;rlk'~~l;Wl;
')u"
•••• " .
p
~,:~29~~",;'P>:O/f#ff;{Y ~~~~;(o,~~.~~~~:~f~~98~~:l
',\'¥ij;if i':.'ji i;;;'J't'\t 1!~!.;
..• lJI.i.,~'.lI!!fJJI,P!I'J':lqt~J1!tJ.,~§f1:i:Qp,',,"5'
"'~"'''¥.'\. . .J.,,,·~;.>,l.
~ S 891~i• . .:: 2,1 Y;[!!Jd:iW t)Elii';,»
STU 2050
STU 2060
STUT 2060
PBC User Board ... , .. , . , ..... , . , .......... , . .. . . . . ....
SICOFI® User Board, . , ....................... , . . . . . . ..
SICOFI® Test Board ..... ,.............................
les for ISDN Exchange Systems
Siemens Components, Inc.
12
214
217
219
Summary of Types
Page
ICs for ISDN Exchange System (cont'd)
PEB 2070-C
S PES2070-N
PEB 2070-P
~S pee 2075-N
~ PEB 2075-P
PEB 2080-C
S PEB2080-N
PEB 2080-P
S"f:$2081-N
PEB 2081-P
PEB 20901-C
~S PEa.20901 ..N
PEB 20901-P
PEB 20902-P
PEB 20902-C
~Spe8 2()902~N
~
PEB 2091-C
~SP1:B'2091 "ri
PEB 2095-C
S PSs2095-N·
PEB 2095-P
~ PEB 20950-C
~S PE8a0950~N
~
PEB 20950-P
ISDN Communications Controller (ICC) . . . . . . . . . . . . . . . . . ..
276
(ICC) ............. , .... ~
276
ISDN Communications Controller (ICC) . . . . . . . . . . . . . . . . . ..
ISDN D·Channel Exchange Controller (IDEC) . : . . . . . . . . . . . .
ISDN D-Channel Exchange Controller (lDEC). ........... ..
S-Bus Interface Circuit (SBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.s~aus Interface Circuit (SaC) . . . . . . . . . . . . . . . . . . . . . . . . . . ..
S-Bus Interface Circuit (SBC) . . . . . . . . . . . . . . . . . . . . . . . .. . ..
SIT Sus Interface Circuit Extended (SSCX) ...............
SIT Bus Interface Circuit Extended (SBCX) ...............
ISDN Echo-Cancellation Circuit (IEC-T) .................. ,
ISDN Echo-Cancellation Circuit (IEC-T) ................. ...
ISDN Echo-Cancellation Circuit (IEC-T) . . . . . . . . . . . . . . . . . ..
ISDN Echo-Cancellation Circuit (IEC-T) . . . . . . . . . . . . . . . . . ..
ISDN Echo-Cancellation Circuit (IEC-T) . . . . . . . . . . . . . . . . . ..
JSONEC/'lo-Cancell~ion Circ!.Iit (~C~T) ...................
ISDN Echo-Cancellation Circuit (IEC-Q)..... ..............
ISON ECho~Canceflation Circuit (IEC-Q) . . . . . . . . . . • . . . • . . . .
ISDN Burst Transceiver Circuit (IBC) .....................
ISDN SurstTransceiverClrcuit (ISC) .....................
ISDN Burst Transceiver Circuit (lBC) .....................
ISDN Subscriber Access Controller (lSACTM_P) . .. .. . ... ...
ISDN Subscriber ACces$G~ntroller (ISACTM~P) . . . . . . . . . . . .
ISDN Subscriber Access Controller (ISACTM-P) . ...........
276
316
316
339
339
339
381
381
415
~SDN Communica.~ions Controller
415
415
415
415
415
442
442
459
459
459
485
485
485
ICs for ISDN Terminals
S PE$20S5-N
PEB 2085-P
SPSEl'2160-N
PSB 2160-P
SIi'•• 2~·,jO.;N
PSB 2110-P
~•.~;t26-p .
PSB 2121-P
~S .!?SS'212hT
!SOr\!'SUbscriberAcces$Controller (ISACTM·S) ........... . 495
ISDN Subscriber Access Controller (ISACTM-S) ........... .
AutfiPr:tihgingCodedFUfef(AROOFI@) .; ................ .
Audi~RingingCodec Filter (ARCOFI®) .................. .
;U~D~:r~min8,lAdlipter ¢ire!.l~ (rrACTM) ................. .
ISDNT~rminal Adapter Circuit (ITACTM) ................. .
i\id~f ~.motepowe'bontroltedlflPC) •..•...............
General Purpose Power ControHer (GPPC) ............... .
'~~eral Purpose Power Controller (GPPC) ............... .
495
557
557
Digital Subscriber Controller (DSC/E) ....................
592
ISDN PC Development System. . . . . . . . . . . . . . . . . . . . . . . . . .
625
594
594
596
613
613
Advance Information
PSB 79C30E
Support Tools
SIPS 5000
Siemens Components, Inc.
13
Summary of Types
ICs for Data Communication
Page
__,tI.;i.;__.1~~~t;'~i!~'il:ii;;;\:;::.~:;;.;i.·~j;>.·.·;~:.
·
SAB 82520-P
• SAF 82520-C
High-Level Serial Communications Controller. (HSCC) ..............
Hi h-Level Serial Communications Controller (HSCC) ..............
._~l: ~'0?[f.~"',"'i ."
• S
it
:j?
658
658
,, 50% a coat of pure cotton is sufficient. In the case of chargeable
synthetic fibers the clothing should be worn close-fitting. The wrist strap must be
worn snugly on the skin and be grounded across a resistor of 50 to 100 ka.
4. If conductive floors, R = 5 X 104 to 107 a are provided, further protection can be
achieved by using so-called MOS chairs and shoes with a conductive sole
(R"", 105 to 107 a).
Siemens Components, Inc.
20
General Information
5. All transport containers for ESS devices and assembled circuits boards must first
be brought to the same potential by being placed on the work surface or touched
by the operator before the individual devices may be handled. The potential equalization should be across a resistor of 106 to 108 a.
6. When loading machines and production devices it should be noted that the devices
come out of the transport magazine charged and can be damaged if they touch
metal, e. g. machine parts.
Example 1) conductive (black) tubes.
The devices may be destroyes in the tube by charged persons or come
out of the tube charged if this is emptied by a charged person.
Conductive tubes may only be handled at ESS work stations (highresistance work-station and person grounding).
Example 2) anti-static (transparent) tubes.
The devices cannot be destroyed in the tube by charged persons
(there may be a rare exception in the case of custom ICs with unprotected
gate pins). The devices can be engangered as in 1) when the tube is
emptied if the latter, especially at low humidity, is no longer sufficiently
anti-static after a long period of storage (> 1 year).
In both cases damage can be avoided by discharging the devices across a grounded
adapter of high-resistance material ("" 106 to 108 a/cm) between the tube and the
machine.
The use of metal tubes - especially of anodized aluminium - is not advisable
because of the danger of low-resistance device discharge.
Storage
ESS devices should only be stored in identified locations provided for the purpose.
During storage the devices should remain in the packing in which they are supplied.
The storage temperature should not exceed 60 aC.
Transport
ESS devices in approved packing tubes should only be transported in suitable containers
of conductive or longterm anti-static-treated plastic or possibly unvarnished wood.
Containers of both high-charging plastic or very low-resistance materials are unsuitable.
Transfer cars and their rollers should exhibit adequate electrical conductivity (R < 106 a).
Sliding contacts and grounding chains will not reliably eliminate charges.
Incoming Inspection
In incoming inspection the above guidelines should be observed. Otherwise any right
to refund or replacement if devices fail inspection may be lost.
Material and Mounting
1. The drive belts of machines used· for the processing of the devices, in as much as
they come into contact with them (e.g. bending and cutting machines, conveyor belts),
should be treated with anti-static spray (e.g. anti-static spray 100 from Kontaktchemie). It is better, however, to avoid the contact completely.
Siemens Components, Inc.
21
General Information
,i
2. If ESS devices have to be soldered or desoldered manually, soldering irons with
thyristor control may not be used. Siernens EMI.,.suppression capacitors of the
type B 81711-B31 ... -B36 have proven very effective against line transients.
3. Circuit boards fitted and soldered with ESS devices are always to be considered
as endangered.
Electrical Tests and Application Circuit
1. The devices should be processed with observation of these guidelines. Before
assembled and soldered circuit boards are tested, remove any shorting rings.
2. The sockets or integrated circuits must not be conducting any voltage when individual
devices or assembled circuit boards are inserted or withdrawn, unless works'
specifications state otherwise. Ensure that the test devices and power supplies do
not produce any voltage spikes, either when being turned on and off in normal
operation or if the power fuse blows or other fuses respond.
3. When supplying bipolar integrated circuits with current, the negative voltage
(-lIS or GND) has first to be connected. In general, an interruption of this potential
during operation is not permissible.
4. Signal voltages may only be applied to the inputs of ICs when or better after the
supply voltage is turned on. They must be disconnected when or better before the
supply voltage is turned off.
5. Power supplied of integrated circuits are to be blocked as near as possible at the
supply terminals of the IC. With bipolar ICs it is recommended to use a low-inductance
electrolytic capacitor or at least a paralleled cermaic capacitor of 100 nF to 470 nF
for example.
Using ICs with high output currents, the necessary value of the electrolytic capacitor
must be adapted to the test or application circuit. Transient behavior and dynamic
output resistance of the power supplied, line inductances in the supply and load
circuit and in particular inductive loads or motors have to be considered. When
switching off line inductances of inductive loads, the stored power has to be consumed externally, unless otherwise specified (e.g. by an electrolytic capacitor, diodes,
Z diodes or the power supply). Also a switching off of the supply voltage prior to
the load rejection should be taken into account.
6. ICs with low-pass character of the output stages (e.g. PNP drivers or PNP/NPN
end stages), normally need an additional external compensation at the output.
This applies particularly to complex loads. The output of AF power amplifiers is
compensated by the Boucherot element. In individual cases, bridge circuits only
need a capacitance for bypassing the load. Depending on the application it is,
however, also recommended to connect one capacitor from each output to ground.
7. Observe any notes and instructions in the respective data books.
Packing of Assembled PC Boards or Flatpack Units
The packing material should exhibit low volume conductiVity:
105 Q/cm < p < 1010 Q/cm.
Siemens Components, Inc.
22
General Information
In most cases - especially with humidity of > 40% - this requirement is fulfilled by
simple corrugated board. Better protection is obtained with bags of conductive polyethylene foam (e.g. RCAS 1200 from Richmond of Redlands, California).
One should always ensure that boards cannot touch.
In special cases it may be necessary to provide protection against strong electric
fields, such as can be generated by conveyor belts for example. For this purpose a
sheath of aluminium foil is recommended, although direct contact between the film
and the PCB must be avoided. Cardboard boxes with an aluminium-foil lining, such as
those used for shipping our devices, are available from Laber of Munich.
Ultrasonic Cleaning of ICs
The following recommendation applies to plastic packages. For cavity packages (metal
and also ceramic) separate regulations have to be observed.
Freon and isopropyl alcohol (trade name: propanol) can be used as solvents. These
solvents can also be used for plastic packages because they do not eat into the
plastic material.
An ultrasonic bath in double halfwave operation is advisable because of the low
component stress.
The ultrasonic limits are as follows:
sound frequency
> 40 kHz
exposure
t < 2 min
alternating sound pressure p < 29 kPa
sound power
N < 0.5 W/cm 2/liter
4. Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding anyone of these values may cause
irreversible damage to the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical charateristics specify mean values expected over the production spread.
If not otherwise specified, typical characteristics apply at TA = 25°C and the given
supply voltage.
Operating Range
In the operating range the functions given in the circuit description are fulfilled.
Siemens Components, Inc.
23
General Information
5. Quality Assurance
The high quality and reliability of integrated circuits from Siemens are the results of
carefully managed design and production which is systematically checked and controlled at each stage.
The procedures are subject to a quality assurance system; full details are given in the
brochure "Quality Assurance - Integrated Circuits".
Figure 1 and 2 show the most important stages of QA system. Quality assurance (QA)
department independent of production and development are responsible for the selected
measures, acceptance procedures and information feedback loops. Operating
QA departments have stat-of-the-art test and measuring equipment at is disposal,
work according to approved methods of statistical quality control, and provided with
facilities for accelerate life and are environmental tests used for both qualification and
routine monitoring tests.
The latest methods and equipment for preparation and analysis are employed to
achieve continuity of quality and reliability.
Conformance
Each integrated circuit is subjected to a final test at the end of the production process.
These are carried out by computer-controlled, automatic test systems because
hundreds of thousands of operating conditions as well as a large number of static
and dynamic parameters have to be considered. Moreover, the test systems are
extremely reliable and reproducible. The quality assurance department carries out a final
check in the form of a lot-by-Iot sampling inspection to additionally ensure this minimum
percent defectives as well as the acceptable quality level (AQL). Sampling inspection
is performed in accordance with the inspection plans of DIN 40080, as well as of the
identical MIL-STD-105 or IEC 410.
Siemens Components, Inc.
24
General Information
Figure 1
Specification
Product Plan
Proven Technology
and Design Ru les
Feedback
Loops
Concept Approval
QI
III
'"
a..
.J:.
Engineering Samples
....
C
QI
E
0.
o
Qj
>
QI
o
Testing of Samples
If Necessary Re -Design
or Procces Change
First Quality and
Reliability Testing
E. Samples for Customer
Preliminary Manufacturing
and Test Specs, Data Sheets
Pre series Release
Prototype Samples
Quality and
Reliability Testing
5l
'"
.J:.
Manufacturing Process
a..
c
o
:;:
Fullfilment of
Requirements
....::J
"t:>
o
co.
QI
c-
a..
Automatic Test Equipment
Manufacturing and Test Specs
Complete
Documentation
Series Release
Siemens Components. Inc.
25
General Information
Figure 2
QA
Inspection of
Incoming Material
Wafer Fabrication
Wafer
Probing Test
QA Visual Inspection
and Lot Acceptance
Process and
Manufacturing
Control
Assembly
QA Visual Inspec;tion
an d Lot Acceptance
~
Final Test
QA Shipping Inspection
and Lot Ac~eptance
QA
Samples
-----1
I
Warehouse
QA
+
Reliability
Monitoring
Customer
Returns
----QAl
I
I
Failure Analysis
I
Reliability
Measures Taken during Development
The reliability of ICs is already considerably influenced at the development stage.
Siemens has, therefore, fixed certain design standards for the development of circuit
and layout, e. g. specifying minimum width and spacing of conductive layers on a chip,
dimensions and electrical parameters of protective circuits for electrostatic charge, etc.
An examination with the aid of carefully arranged programs operated on large-scale
computers, guarantees the immediate identification and elimination of unintentional
violations of these designs standards.
Siemens Components, Inc.
26
General Information
In-Process Control during Production
The manufacturing of integrated circuits comprises several hundred production steps.
As each step is to be executed with utmost accuracy, the in-process control is of
outstanding importance. Some processes require more than a hundred different test
measures. The tests have been arranged such that the individual process steps can
be reproduced continuously.
The decreasing failure rates reflect the never ending effort in this direction; in the course
of the years they have been reduced considerably despite an immense rise in IC
complexity.
Reliability Monitoring
The general course of the IC failure rate versus time is shown by a so-called "bathtub"
curve. The failure rate has its peak during the first few operating hours (early failure
period). After the early failure period has decayed, the "constant" failure rate period
starts during which the failures may occur at an approximately uniform rate. This period
ends with a repeated rise of the curve during the wear-out failure period. For ICs,
however, the latter period usually lies far beyond the service life specified for the
individual equipment.
Reliability tests for ICs are usually desctructive examinations. They are, therefore, carried
out with samples. Most failure mechanisms can be accelerated by means of higher
temperatures. Due to the temperature dependence of the failure mechanisms, it is
possible to simultane future operational behavior within a short time by applying high
temperatures; this is called life test.
The acceleration factor B for the life test can be obtained from the Arrhenius equation
B =exp (EA
k
(~- ~))
T,
T2
where T2 is the temperature at which the life test is performed, T1 is the assumed
operating temperature, and k is the Boltzmann constant.
Important for factor B is the activation energy EA' It lies between 0.3 and 1.3 eV and
differs considerably for the individual failure mechanisms.
For all Siemens ICs, the reliability data from life tests is converted to an operating
temperature of TA = 40 DC, assuming an average activation energy of 0.4 eV. The
acceleration factor for life tests at 125°C is thus 24, compared with operational behavior.
This method considers also failure mechanisms with low activation energy, i.e. which
are only slightly accelerated by the temperature effect.
Various reliability tests are periodically performed with IC types that are representative
of a certain production line - this is described in the brochure "Quality AssuranceIntegrated Circuits". Such tests are e.g. humidity test at 85°C and 85% relative humidity,
pressure cooker test, as well as life tests up to 1000 hours and more. Test results
are available in the form of summary reports.
Siemens Components, Inc.
27
General Information
".:.
6. Summary of the Most Important Symbols
b
B
B
BI
BO
C
01
CIClK
Cl
D
DO
E
FI
Fa
FOH
FOl
'I
,
tCl'
t/l>
100
~
~H
III
I
11
12
I
loa
10
10H
10l
ISH
ISl
MO
as, GND
Ptot
Po
ClK
0
"0
Pulse duration
Current gain
Bandwidth
Input of output amplifier
Output of output amplifier
Capacitance
Input capacitance
Input capacitance of the clock input
load capacitance
Data input
Data output
Enable
Input load factor
Output load factor
Output load factor, H signal
Output load factor, l signal
Input frequency
Clock frequency
Maximum counter frequency
Drain supply current
Input current
H-input current
l-input current
Input
Input 1
Input 2
Input bias current
Output offset current
Short-circuit output current
H-output current
l-output current
H-supply current
l-supply cur~ent
Mixer output
Ground, earth
Total power consumption
Output power
Clock
0l:ltput
Output, inverted
Siemens Components, Inc.
28
General Information
R
Ra
RI
RCL
RL
Rp
RthJA
ROH
ROL
Ro
TA
Tstg
Tease
1j
TC
td
t OHLO
t OLHO
tOLH
tH
tl
tn
tn+1
tp
tSYO
tCLKY
t pHL
tpHLR,S
t po
tpR
tpR,s
tps
td
tp
tpc
tT
t,
ts
to
tTHL
tTLH
t THLO
tTLH 0
Resistance
Generator resistance
Input resistance
Collector load resistance
Load resistance
Adjustmente resistance
Therminal resistance (Junction to ambient)
H-output resistance
L-output resistance
Load resistance at output
Ambient temperature
Storage temperature
Case temperature
Junction temperature
Temperature coefficient
Pulse delay time
Delay time of the HL transition of the output signal
Delay time of the LH transition of the output signal
Delay time
Hold time
Input pulse duration
Bit time before clock pulse
Bit time after clock pulse
Average signal propagation time
Delay time
Clock period
Signal propagation time (from H to L)
Signal propagation time (set, reset input)
Pair-delay time
Reset pulse duration
Average signal propagation time (set, reset input)
Set pulse duration
Key debounce time
Key depression period
Counting pulse duration
Transmission time - t, rise time, tj fall time
Recovery time
Setup time
Output pulse duration
Signal transition time (from H to L)
Signal transition time (from L to H)
Signal transition time H-L of the output signal
Signal transition time L-H of the output signal
Siemens Components, Inc.
29
General Information
tSH
tSHI
t SHr
tSl
tSLI
tSlr
tWHI
tWll
tTHl I
tTlH I
t WHO
tw
V
Vs
Vnm
H-setup time
H-setup time, left shift pulse
H-setup time, right shift pulse
L-setup time
L-setup time, left shift pulse
L-setup time, right shift pulse
Pulse width of the H-input signal
Pulse width of the L-input signal
HL-transition time of the input signal
LH-transition time of the input signal
Pulse width of the H-output signal
Pulse width
Voltage, general
Supply voltage
Noise margin
VBB}
VEE
Negative supply voltage
Vee
Vss
Positive supply voltage
Substrate supply voltage
Drain supply voltage
Gate supply voltage
H-input voltage at information input
L-input voltage at information input
H-output voltage
Inverted output voltage VOH
L-output voltage
Inverted output voltage VOL
Differential input voltage
Input common mode voltage
Noise voltage
Functional voltage range
Input voltage at information input
Reset voltage
Input impedance
Output impedance
Voo
VGG
V;H
V;l
VOH
VOH
VOL
VaL
VOl
Vern
Vn
VF
V;
VR
ZI
Zo
Siemens Components, Inc.
30
ICs for Digital Exchange Systems
Digital Telephone Exchange System
•
•
•
Analog Subscriber Boards
Switching Network
Primary Access
Analog Subscriber Board
Subscriber 1
r:~~'
'I'
~....
'-'Y1
4,
P(M Line
Interface
PEB 2035
PEB 2235
!~voic'e-'-'~ P~=~:-'ll
1
i P(M
-
tL__
i!!II'I'__
"iiJ-=t==t~ SLI ( _
Subscriber 8 (16)
-
I
i
~Ciff!HL'it=t=t=1!
-- -.
I
I
SI(OFI®
~~~ m~
" ,
:
I
, i
'--
Bus
SU( '- m~~~
"
(ommand
Signaling
Highway
Peripheral
Board
I
--I1---,L
....
~;:r;~~: -
!
'I:
PEB 2051
PEB 2052
SI(OFI®
oVLme
S~ation
...;,i__
~
Route Line
Memory
Time
Switch
L=
PES 2045
PEB 2046
-+
r-
I
,1',
r--s,z---, !
I
I I
I
I
~P
L._,_._._._._~=~-=-J.j
Signal ing
Highway
{i'
0
,....._.¥..._...,
--
Group
,---,--_pr_oc_es_so_r.........
In a digital exchange system the subscriber line boards provide the link between the
subscriber and the switching network. The basic functions of analog line boards are known
under the acronym BORSHT (battery, overvoltage, rising, supervision, hybrid, testing).
Moreover, further important tasks are voice frequency band limitation, analog to digital
conversion into time discrete digital equivalents, time-slot assignment on the PCM highways and handling of signaling and control information.
Up to now implementation has been characterized by fixed adjustment of line interface
conditions although telephone line conditions vary considerably with national standards
and even with subscriber line installations. Under adverse conditions telecommunication
equipment must match the subscriber line and termination impedances while suppressing
return echoes in the two- to four-wire hybrid network. Compensating for line attenuation
is just as critical for balancing the voice signals in the transmission and reception paths.
To improve voice quality, subscriber line boards have to be matched to different line
conditions by means of interchangeable discrete components. This approach is very costly
regarding line board design and manufacturing. Furthermore, the reliability of a board
filled with parts, wires and connections will decrease rapidly.
The subscriber line board architecture proposed by Siemens Components Group and
supported by several other .companies is geared to eliminate many of these line board
trouble spots.
Siemens Components, Inc.
33
Digital Telephone Exchange System
Optimized Line Board Architecture
The key device for both analog and digital subscriber line boards is the Peripheral Board
Controller (PBC) PEB 2050/51. Basically the PBC is a highly intelligent multiplexerl
demultiplexer chip which performs the variable time-slot assignment for up to 16 PCM
channels and handles the data streams for control and signaling. It constitutes the interface between the subscriber line devices such as decoded filter or ISDN communication
. controller, the PCM lines, the central control unit and the optional onboard microprocessor.
As a characteristic architectural feature, for test, monitoring and control purposes, the
device permits efficient switching of data streams between all these interfaces and, therefore, ensures transparency between the PCM channels and control or signaling data.
This opens up attractive possibilities such as common-channel signaling and microprocessor
access to PCM data.
Due to the importance of reliability in system design, the PBC provides a backplane
interface with two or four fully redundant PCM highways. For the exchange of information
between a central control unit and the PBC working as a "slave" in a point-to-multipoint
configuration, the device supports a subset of the CCITT's High Level Data Link Control
(HDLC) communications protocol so that it can respond to certain HDLC frames without
microprocessor intervention or software supervision.
The hardwired implementation of the physical level of the HDLC protocol (e. g. cyclic
redundancy check) and of parts of the logical level (e.g. evaluation of HDLC commands
and preparation of response packets) in the on-chip HDLC controller permits very high
data rates of up to 4 Mbaud via the serial link to the central processor. By using a local
standard microprocessor, such as the SAB 8051, it is possible to expand the range of the
HDLC protocol to the full X.25 level, while still maintaining procedure handling, buffering
and distribution of data packets hardwired in the PBC. Furthermore, the PBC is able,
in conjunction with a microprocessor, to take over the "primary" function of a highspeed
HDLC communication link.
The PBC communicates with the subscriber line devices via a three-wire Subscriber Line
Data (SLD) bus based on a ping-pong type of protocol. The SLD bus ensures reduced
line board wiring.
.
To cover a broad range of applications the PBC is adaptable to all standard commercial
PCM systems (with 24, 32, 48, 64 channels per frame). Independently of the system clock
used, the circuit computes all timing signals required for the standardized SLD bus, thus
decoupling the subscriber line devices from the system clock. The PBC is an excellent
example of the efficient· realization of standard functions through the use of hardwired
logic in order to increase real-time processing and speed without loss of flexibility.
A further device for interfacing subscriber line devices with PCM lines is the PCM Interface
Controller (PIC) PEB 2052. This CMOS device performs the Time-Slot Assignment (TSA)
and the PCM interface functions. It is pin and software-compatible to the PBC PEB 2050,
but leaves out the HDLC controller and the hardwired last look logic.
.
The Extended PCM Interface Controller (EPICTM) PEB 2055 is intended to be used as central
PCM processor in new architectures. The CMOS device can be programmed to operate
at different data rates between 128 and 8192 kbitls the system interface consists of up
to four duplex ports with a tristate indication signal for each output line. The configurable
interface can be selected to incorporate either four duplex (10M®) or eight bidirectional
I/O ports (SLD).
Siemens Components, Inc.
34
Digital Telephone Exchange System
The EPIC can therefore be programmed to communicate either with SLD or with 10M
(ISDN Oriented Modular) and IOM-2-compatible devices. In both cases the device handles
the layer-1 functions of buffering the C/I and monitor channels for 10M-compatible devices
and the feature control and signaling channels for SLD compatible devices.
The EPIC can handle up to 32 ISDN subscribers with their 2B+D channel structure or
64 analog subscribers in 10M configuration or up to 16 subscribers in SLD configuration.
Since its interfaces can operate at different data rates, the EPIC is an ideal device for
data rate adaptation.
Moreover, the EPIC is one of the fundamental building blocks for networks with either
central, decentral or mixed signaling and packet data handling architectures.
Siemens Components therefore offer the optimum solution of PCM Interface Controller
for every application:
•
•
•
PCB 2050/51:
for up to eight ISDN and 16 analog subscribers.
Especially suitable for powerful PABX.
PIC PEB 2052: for up to eight ISDN and 16 analog subscribers.
Ideal for price sensitive systems, e.g. small PAX and public exchanges (CO).
EPIC PEB 2055: for up to 32 ISDN and 64 analog subscribers.
Suitable as the central PCM processor in new architectures.
The second device used in the advantageous analog line board architecture is the highly
sophisticated Signal Processing Codec Filter {SICOFI~ PEB 2060, fabricated in advanced
CMOS technology. Based on Digital Signal Processing (DSP) methods, in addition to the
standard functions of PCM coding and voice-band limitation that any codec filter features,
the SICOFI provides a variety of user-programmable filters for impedance matching, 2/4-wire
hybrid balancing, analog and digital gain adjustment as well as frequency response
correction.
A sophisticated level of performance can therefore be achieved under complete software
control. The use of external components or trimming procedures is completely avoided.
For impedance adjustments, the related filter implements a feedback loop to modify the
SUC's termination impedance. It can handle any complex impedance level, resulting in
optimized return loss for all subscriber line conditions. In a similar manner, the hybrid
"balance filter can be programmed for optimal balance between the transmit and receive
side and for minimum echoes.
For accurate adjustment of the gain in receive and transmit directions, four independently
programmable filters can vary the level of the analog voice signal in a range of ± 22 dB.
Independently of the actual gain setting, the device still holds the specified transmissiony/ /
performance. Similar to the level control, the SICOFI contains digital filters in receive ana
transmit directions, which allow modification of the frequency response characteristics.
Further features attractive for the realization of flexible exchange systems are selectable
All! law coding, three-party conference support, supply voltage supervision, hardware
and software reset, power-down mode and on-chip reference voltage. Different loopback
modes enable both the line board and the total system to be tested during operation.
The SICOFI can hook up directly to virtually any commercial SUC, because of its flexible
signaling interface consisting of ten ports. Three are dedicated to the status of voice
transmissions and three to receptions. The remaining four can be programmed individually
as either transmit or receive ports.
Siemens Components, Inc.
35
Digital Telephone Exchange System
Due to the fact that the SIFOFI needs extended control information, a message-oriented
protocol is used for byte transfer via the SLD bus. Two bits in each control byte are used
to define three different classes of commands, which contain information about the
configuration of the SICOFI, the coefficient exchange and the number of subsequently
transmitted data bytes. Per frame and direction, one control byte is transferred between the
SICOFI and the PSC. With the appropriate commands, data can be written into or read
back from the SICOFI. Selection of one of the two SICOFls connected to one SLD port
is accomplished by an address bit in the feature control byte. For programming the device
in the information usually is transferred via the HDLC link to the PSC, but all programming
can also be done by means of an onboard microprocessor.
There are numerous good reasons why, the world over, major attention is given to digital
signal processing methods. Compared to analog filtering, digital processing does not need
precision elements, allows much higher accuracy along with precisely predictable
transmission behavior including noise. It makes the device less sensitive to parameter
fluctuations such as drift with temperature or aging, and, moreover, it provides excellent
power supply rejection, better testability and crosstalk behavior of the circuit.
In addition, the DSP technique allows a better and easier shrinking of the device and the
implementation of codec/filter functions for two and more subscribers on one chip, which
is not economical or completely unpossible with switched capacitor methods. The next
development stage will produced a Dual Channel Codec Filter (SICOFI-2) PES 2260 that
performs the functions of the SICOFI-1 PES 2060 for two subscribers in one chip. Moreover
the CMOS device can be programmed to communicate either with SLD (PSC/PIC) or with
IOM-2 (EPIC) compatible PCM interface controller.
As shown with the SICOFI the DSP approach, in a costsaving and programmable manner,
allows the realization of new functions which would be very expensive or impractical in
the analog domain.
The all-over flexibility of the unique device concept gives the user the capability for designing
a standard line card which can be customized for each application under software control.
The SLD architecture leads to a highly modular line board configuration with low wiring,
reduced board area and, depending only on the SLiC to be used, very few discrete
elements. Moreover, since the peripheral board controller an the SLD bus concept are also
key elements of Siemens 10M (ISDN Oriented Modular) VLSI family, a high degree of
upward compatibility and modularity is achieved in fully digital voice and data communication
systems.
Siemens Components, Inc.
36
Digital Telephone Exchange System
Frame Structure of the SLD Bus
Subscriber
Subscriber Line Board
I
SICOFI~
I
PEB 2060
PEB 2260
Backplane
OIR
I
SCLK
I
SIP
PBC
PEB 2050/51/52
I
I
L.--SLO Bus
t-----
Receive
DlR
SCLK
SIP
1 Frame (125jJsl-512 kbitls
Transmit
512 kHz
B1
S
Voicel
Data
Voicel
Data
Voicel
Data
Voicel
Data
Feature
Control
Feature
Control
Signaling
Signaling
Advantages of Siemens Line Board Concept
•
•
•
•
•
•
•
•
System specific PCM interface is represented by a simple general line board internal
interface (SLD bus)
Pin and hardware reduction for codec filter circuit
Reduced line board wiring; per-line structure avoids cross-wiring
Design of one standard line board which can be customized for each requirement
through complete software control
Decoupling of subscriber line devices from the system clock
Transparency between control and PCM data
SLD concept is upward-compatible with Siemens ISDN circuit family
Multiple source for SLD circuits
Siemens Components, Inc.
37
Digital Telephone Exchange System
Analog Subscriber Board for up to 16 Subscribers
ClK SYP
Voice
Control
Signaling
a
BORST
(SLI ()
Voice
PCM
24/32
SICOFI®
SClK
(512 kHz)
Command
Signaling
SIGS
BORST
( SU()
b
48/64
DIR
o
a
Voice
8(16)K64kbit
Peripheral
Board
Controller
(PBC)
Cantrall
Signaling
SICOFI ®
15
SlO Bus
r--- ---I
I((e.g. SAB
~P
I
8051) I
BORST Battery, overvoltage, ringing, supervision,
testing (the hybrid function is integrated
in the SICOFI)
IL ______ ....lI
HOlC
1.5/2/3/4
Mbit
ClK
Clock
DIR
Direction
SIGS
Signal strobe
SClK
Slave clock
SLiC
Subscriber line interface circuit
Synchronization
SYP
SICOFI Signal-processing codec filter
The SLD Interface
The SLD bus is used by the PSC to interface with the subscriber line devices. A Serial
Interface Port (SIP) is used for the transfer of all digital voice and data, feature control
and Signaling information between the individual subscriber line devices, the PCM highways
and the control backplane. The SLD approach provides a common interface for analog
or digital per-line components. Through the PSC, which will be the key device in the SLD
architecture, the PCM data is transparently switched onto the PCM highways. The PSC
will make analog and digital subscriber line boards plug-compatible in a line equipment
rack.
There are three leads connecting each subscriber line device and the PSC: two common
clock signals shared among all devices, and a unique bidirectional data lead for each
of the eight SIP lines. The Direction signal (DIR) is an8-kHz clock output from the PSC
(master) that serves as a frame sync to the subscriber line devices (slave) as well as a
transfer indicator. The data are transferred at a 512-kHz rate, clocked by the Subscriber
Clock (SCLK). When DIR is high (first half of the SLD 125 (..Ls frame), four bytes of digital
Siemens Components, Inc.
38
Digital Telephone Exchange System
data are transmitted on the SLD bus from the PBC to the slave (receive direction). During
the second half of the frame when DIR is low, four bytes of data are transferred from the
slave back to thePBC (transmit direction).
Channel B1 and B2 are 64-kbiVs channels reserved for voice or data to be routed to and
from the PCM highways. In an application where one SICOFI is connected to a SIP, voice
is received on channel B1 and transmitted on channel B1 and B2. For a three-party
conference, channel B2 is the third-party voice channel. If two SICOFls are connected
to one SIP, channel B1 is assigned to one and channel B2 to the other SICOFI. Conferencing
is not possible in this configuration. With digital subscriber line devices the two bytes can
be used to carry 64-kbiVs data channels. The third and sixth byte locations are used to
transmit and receive control information for programming the slave devices The last byte
in each direction is reserved for signaling data.
Switching Network
Supervision and control of the entire system, including connection setup, maintenance
and testing, is performed in a powerful central processing unit. Besides this, the throughswitching of PCM channels is done in a switching network unit, whereas the tasks of a
frame alignment unit are to interface PCM transmission routes with the switching system.
Digital exchanges put calls through by newly arranging the speech signals coded with
8-bit words (PCM slots). The code words are transmitted serially on PCM lines. The sampling
frequency of 8 kHz produces PCM frames with a duration of 125 fJ.s. The transmission
rate on the line determines how many code words (speech channels) can be accommodated
within a sampling period. With a data rate of 2048 kbiVs for example, there are 32 time
slots of 8 bits each. Four lines with a data rate of 8192 kbiVs have a transmission capacity
of 512 channels.
In a digital switching matrix one distinguishes betwen two basic switching principles:
• time division multiplex
• space division multiplex
Siemens Components, Inc.
39
Digital Telephone Exchange System
A method that is frequently used involves a combination of the two principles, this being
called space/time division multiplex. The figure illustrates the different principles.
Time/Division MuHiplex
TSO
TS.1
TS2
TS3
TS 0
TS 1
TS 2
TS 3
.IA1~21.
Input Timing
Output Timing
Characteristic: the timing of the code words is changed
Space/Division Multiplex
TS 0
TSO
Line 1 --o_L-----J
Line 2 --o_L-----Jr.,..
Line 3 --o_L----J
Input Timing
L - - - l ._ _
2
L...---l._ _
3
Output Timing
Characteristic: the code words retain their timing,
but the lines are changed
SpacelTime-Division MuHiplex
TSO
TS1
TS2
TS3
TSO
TS1
TS2
Line 1__..I--...L--.L----J"--~
Line 2 __..1--..1--""'--..1-..---1
Line 3_..1-_..1-_""'-_..1-..---1
Input Timing
Siemens Components, Inc.
Output Timing
40
TS3
Digital Telephone Exchange System
In time division multiplex only the time slot is altered during switching. All signals from a
certain input PCM line are switched to a fixed output line, only the time-slot sequence may
change.
In space division multiplex incoming PCM data are only rearranged in space. The input
time slot equals the output time slot. However, input from one PCM line can be switched
to different output lines.
Siemens Components Group offers devices which take into consideration the needs for
efficient realization of these tasks. One of the switching network circuits offered is the
Memory Time Switch in CMOS (MTSC) PEB 2045, which has the ability to connect any
of 512 incoming PCM channels to any of 256 outgoing PCM channels on a single chip.
A non-blocking switch for 512 subscribers can be built up with two devices only. A further
expansion can be realized very easily too. Different kinds of operation modes enable the
use of the MTSC PEB 2045 in 2.048 Mbitls, 4.096 Mbitls and 8.192 Mbitls or mixed
PCM systems.
As an additional feature the MTSC PEB 2045 together with an Advanced CMOS Frame
Aligner (ACFA) PEB 2035 can realize the system interface of up to four primary multiplex
access lines.
The Memory Time Switch Small (MTSS) PEB 2046 is a smaller version of the MTSC
PEB 2045 performing time/space switch functions for a non-blocking switch of 256 subscribers.
Primary Access Applications
Applications for the primary rate interface include trunk lines between public central office
(CO) exchanges, from a PBX to a CO, interlinking PBXs, the gateway connecting a LAN
to the public network or a PBX, interlinking LANs, interfacing a large computer or data
intensive terminal (e.g. CAD graphics) with CO or a PBX, etc.
To facilitate the design of equipment for these applications, Siemens has developed an
architecture which optimizes the required functions on the following four integrated circuits:
PEB 2235
PEB 2035
PEB 2045
SAB 82520/SAB 82525
ISDN Primary Access Transceiver (IPAl'M)
Advanced CMOS Frame Aligner (ACFA)
Memory Time Switch CMOS (MTSC)
High-level Serial Communications Controller (HSCC/HSCX)
The functional architecture for the primary access chip set is shown on page 42.
The IPAT, together with the ACFA, implement the layer-1 physical interface. They are
connected to the other primary access devices over the internal primary highway. The
HSCC/HSCX is a powerful communications controller which handles protocol oriented
signaling (X.25 LAPB, ISDN LAPD) by accessing the signaling channel on the internal
primary highway. The MTSC is an equally powerful switching device which connects the
internal primary highway to a variety of possible system interfaces (2048, 4096, 8192 kbitls.
All of these devices can be readily accessed and controlled via the microprocessor interface.
Siemens Components, Inc.
41
Digital Telephone Exchange System
The IPAT is a monolithic line driver for primary access lines of either the PCM 24
(T1, N. America/Japan) or PCM 30 (CEPT, W. Europe) standards. In the receive direction,
the device recovers the clock and data signals from the line and forwards them to the
ACFA.
The IPAT is transparent to the received line code. In the transmit direction, the device takes
the signal received from the ACFA and forms it into transmission pulses according to CCID
recommendations for the PCM 30 or AT & T's OMI specifications for PCM 24.
Correspondingly, input/output jitter requirements comply with both CCID and AT&T
specifications.
Basic Connections in a Digital Switching System
SLD
Analog
PES
2050
2051
2052
.,
•
•
PCM Hw s.
I
I
---t',
I I
---------------------------------~
: :HDLC
I I
I I
~ ____ ,
I I
I
H I
r-=-=::-"':'"
SLD
••
PES
2050
2051
2052
1.5,2,(4lMbil/s
I
---tL-~
: ~-1
-------------------------------·--1 :
:
I
I
I
IOM~ 2
I
I
I
s :
( I
X__ J
L __
1.5, 2,(4,8l Mbitls
L __ _
.,
PES
2055
: 1
Subscriber Line Boards
Siemens Components, Inc.
PES
2045
I
I
I
I
••
• 4L..-_..... •
42
PES ' .
2045
•
•
2046
•8/16'---.....
---------------------------------~
2Mbil/.
• 2
2 Mbil/s
Cenlral Unil
Switching Network
Digital Telephone Exchange System
Frame alignment for all commonly used framing and multiframing formats is performed
by the ACFA. The device synchronizes the transmit and receive signals, interfaces the data
rate from the line to the 2048 kbiVs internal highway and codes/decodes one of three
selectable line codes.
I
For PCM 24, this transmission code can be either B8ZS or AMI-ZCS whereas for PCM 30,
it is always HDB3. Alarms and error conditions are reported to the microprocessor via
a maskable interrupt line. The ACFA can also be used for various signaling schemes.
Rather than using the HSCC/HSCX, signaling information can be handled by a less intelligent
communications controller without programmable time-slot access. For such devices, the
ACFA provides the required signaling information via special purpose pins. Additionally,
the ACFA has a DMA interface for transferring signaling information to/from a microprocessor
controlled memory. Finally, Signaling data can be accessed directly via the microprocessor
interface.
A Quad Primary Access Interface and Switch realized with 11 CMOS Devices.
Line
Interface
Internal
Primary
Highway
2048kbit/s
Dual Rail
Interface
~ 1544/2048 kbit/s
System
Interface
2048/40961
8192 kbit/s
~
j
[f
[f
r-
PES 2045
MTSe
[f
[
PES 2235
IPAT
™
PES 2035
MFA
[
1
SAS 82525
HSeX
Siemens Components, Inc.
43
SIEMENS
Advanced CMOS Frame Aligner (ACFA)
Preliminary Data
PEB2035
CMOSIC
Type
Ordering Code
Package
PEB 2035-C
067100-H8358
C-DIP40
~I; .Q67100-H8359
P-DIP40
Introduction (PEB 2035; Version A)
The Advanced CMOS Frame Aligner PEB 2035 (ACFA) is a monolithic CMOS device which
implements the interface to primary rate PCM carriers. It may be programmed to operate
in 24-channel (T1) and 32-channel (CEPT) carrier systems.
The ACFA features include: selectable multiframe (six multiframe formats), error checking
(CRC4, CRC6), multiple line codes (HDB3, B8ZS, AMI), and programmable signaling paths.
The device meets the newest cCln recommendations for primary rate interfaces and the
AT & T Digital Multiplexed Interface specifications (DMI). Controlling and monitoring of the
device is performed via a parallel eight-bit microprocessor bus.
The circuit contains a two-frame elastic memory which ensures wander absorption between
the PCM carrier and a synchronous, system internal highway..
All signaling types - CCS, CAS and bit-robbed signaling - are supported by the ACFA.
In addition, the ACFA allows flexible access to facility data link and service channels.
Extensive testing capabilities are included.
The ACFA is suitable for use in a wide range of voice and data applications such as the
connection of digital switches and PABX's to host computers (S1/S2 interfaces), the
implementation of primary ISDN subscriber loops, and the connection to primary rate fibre
optical transmission systems.
The ACFA is available in either 40 pin DIP or 44 pin PL-CC packages. As with all of the
ISDN circuits from Siemens, the ACFA has been implemented in advanced CMOS technology.
Total power consumption is less than 100 mW.
Features
Serial Interface to Line Interface Unit
• Frame alignmenVsynthesis for 2048 kbiVs (CEPT, PCM 30) and 1544 kbiVs
(T1, PCM 24) PCM
• Meets newest cCln Rec's (G703, 704, 732, 733, Nov. 1984) and AT & T technical
advisories (DMI, April 1985)
• Programmable formats for: PCM 30: Doubleframe, CRC Multiframe
PCM 24: 4-Frame Multiframe (F4), 12·Frame Multiframe
(F12, 03/4), Extended Superframe (ESF),
Remote Switch Mode (F72)
• Selectable line codes (HDB3, B8ZS, AMI with ZCS)
• Unipolar NRZ for interfacing fibre optical transmission routes
• Error checking via CRC4 or CRCe procedures
• Insertion and extraction of alarms and facility signaling
Siemens Components, Inc.
44
PEB 2035
Serial Interface to System Internal Highway
•
•
•
•
•
•
•
•
System clock frequency of either 4096 kHz or 8192 kHz
Selectable 2048/4096 kbiVs system internal highway with programmable receive/transmit
shifts
Two-frame deep elastic receive memory for receive route clock wander and jitter
compensation
One frame elastic transmit memory (PCM 24 mode only) for transmit route clock
wander and jitter compensation
Two different time-slot assignment procedures in PCM 24 mode
Support for different signaling schemes
Channel loop back capabilities
Channel parity error monitoring
Microprocessor Interface
•
•
•
•
Parallel, demultiplexed microprocessor interface for random access to control and status
registers
Alarm interrupt capabilities
Access to different signaling information:
-Sn, Si-bits (register)
-SN-bits (5 byte stack)
-FDL bits with the possibility of mixed insertion
-CCS, CAS-CC (common channel), CAS-BR (bit robbing) via 2/3 byte stacks
with DMAIinterrupt support
Extensive test and diagnostic capabilities
General
•
•
•
Advanced CMOS technology
Low power consumption « 100 mW)
Packaging: 40-pin DIP/DIC, 44-pin PL-CC
Important Remarks
If it is planned to use future design versions of the ACFA (e.g. ACFA- VB1) which will
meet newest CCITT recommendations and actual requirements of the market, SOFTWARE
development should take into account that
• unused control bits have to be programmed with a logical '0', although they are set
to logical' l' when reading the assignend registers,
• future design versions will have more status bits than now,
• future design versions will no longer support the HDB3 Full Error Detection mode.
Introduction; (PES 2035; Version B)
In addition to the features of PEB 2035 (ACFA) version A, the version B includes functions
which meet the newest CCITT and FTZ recommendations plus some additional features
requested by the market.
Siemens Components. Inc.
45
PEB 2035
The most important new functions are the clear channel capability (PCM 24) and the
extented support of the synchronization algorithm recommended by FTZ (PCM 30, Deutsche
Bundespost).
There are no differences in packaging, pin functions or hardware interfaces between the
ACFA's version A and version B.
General
Additions to PCM 30 Mode
• Slip direction indication [RSR.SOlj.
• Extended HOB3 error detection ['0000' string detection, CCR.EXTOj. HOB3 full detection
mode no longer supported.
• Indication of a CRC error in received submultiframes [SEl.SI1, SEl.SI2j and selectable
automatic insertion in Si bit position of outgoing CRC multiframe [XSP.AXSj.
• Multiframe synchronous updating of Si bit information.
• Additional alarm interrupt sources for start of transmit and receive CRC multiframes
[XSP.MXMB,XSP.MRMBj in conjunction with auto-reset multiframe status flags enable
multiframe synchronous access to Si and Sn bit information.
• Extension of CRC error counting (switchable 10-bit counter) simplifies CRC error limit
detection [CECX,CE8,CECX.CE9,RCO.ECEj.
• Two transparent modes for time-slot 0 in transmit direction [XSP.TTO,XSP.TTOSj extend
test capabilities and access to Sn and Si bit information via the system interface.
• Improved sychronization procedures.
• Single frame mode [LOOP.SFMj of receive speech memory for short data delays in
master/slave applications.
• Error on receive line [ARS.ERLj flags that signals at line inputs ROIP, ROIM) are both
active. This alarm may occur if line interface unit (e.g. PEB 2235, IPAT) detects bad signal
levels on receive line.
• Repeated transmission of the signaling information (last byte of XSIG, transmit signaling
stack) simplifies realization of HOLC procedures via board processor.
Additions to PCM 24 Mode
•
Clear channel capabilities for applications in mixed voice/data or data-only environments,
especially when using bit robbing Signaling schemes and pure AMI line coding with
zero code suppression (B7 stuffing). Selection of 'clear' channels is done by programming three byte register bank CCB1 ... CCB3 [enabled by CPV.SWTCHj.
• Extension of CRC error counting (switchable 10-bit counter) simplifies CRC error limit
detection [CECX,CE8, CECX.CE9, RCO.ECEj.
• Error on receive line [ARS.ERLj flags that signals at line inputs ROIP, ROIM are both
active. This alarm may occur if line interface unit (e.g. PEB 2235, IPAT) detects bad
Signal levels on receive line.
• Repeated transmission of the last signaling information (last byte of XSIG, transmit
signaling stack) simplifies realization of HOLC procedures via board processor.
Siemens Components, Inc.
46
PEB 2035
Logic Symbol
r---Sync.
} System
4096/8192 kHz Clocks
{
Optical
Interface
Rec, Route Clock
1544/2048 kHz
ROID
XOID
ROO
RRCLK
XOI
ROIP
ROIM
]
IPAT™
]
Transmit
Route Clock
1544/2048 kHz
PCM Carrier
Test Outputs
Frame Sync.
Pulse
PCM
Carrier
Interface
Signaling
Support
PES 2035
ACFA
XOOP
XOOM
XRCLK
Parity
Test
XTOP
XTOM
Reset
ISDN Primary Access Transceiver (IPAT) PES 2235 for receive line clock recovery, TTUline
voltage translation and pulse shaping.
Note: Some pins have mode dependent functions and thus may appear more than once
in the logic symbol.
Siemens Components, Inc.
47
PEB 2035
Pin Configurations
(top view)
PL-CC-44
P-OIP-40
XTOM
ROO
OFPY I AINTIFREEZS \I
6 5 4 3 2 1 44 43 42 41 40
RFSPQ
XOID/XMFB 'I
00
01
02
03
04
05
06
07
o
RSIGM/RREQ
Vss
XCHPY
ACKNLClI XSIG
RESQ
PES 2035
'I
XDI
ROIOI XRCLK 11
SYPQ
RDiP
RCHPY
XRCLK/RMFB 11
RFSPQ
XSIGM/XREn
XOIO/XMFB'1
RSIGMI RREQ
00
01
XCHPY
02
ACKNLQ I XSIG 11
RDIM
Voo
RESQ
PES 2035
RRCLK
XDI
18 19 20 21 22 23 24 25 26 27 28
ROID I XRCLK
SYPQ
ROIP
ROIM
RRCLK
SCLK
cos
CEQ
WRQ
1)
The function of the pin is mode dependent (2048/1544 kbit/s PCM)
Siemens Components, Inc.
48
\I
PEB 2035
Pin Definitions and Functions
PL-CC
P-DIP
Symbol
Pin No. Pin No.
44
Input (I)
Function
Output CO)
XTOP
XTOM
0
Transmit Text Data OUT Plus
Transmit Test Data OUT Minus
PCM (+) and PCM (-) output signals which may
be used for diagnostic loopback. Data will continue to be transmitted during AIS transmission
at XDOP/XDOM. The line code is determined
by the bits MODE.PMOD and MODE.CODE.
Output sense is selected via bit XCOXTDS
(after RESET: active lOw). Timing specifications
are equivalent to XDOP/XDOM.
2
ROO
0
Receive Data OUT
Received data which is sent to the system internal highway with 4096 kbiUs or 2048 kbiUs
(bit MODE.lMOD). Data is clocked with the
falling edge of SCLK. The delay between the
beginning of time-slot 0 and the initial edge of
SCLK (after SYPQ goes active) is determined
by the values of Receive Time-slot Offset
RC1.TRO and Receive Clock Offset RCO.RCO.
Additionally for PCM 24, the time-slot assignment between route and system side is selected via bit MODE.CTM.
3
DFPY
FREElS
0
PCM 30: Doubleframe Parity
Every parity signal which supplements the
number of ones of a received doubleframe to
an even quantity. The parity signal is sent out
during the following doubleframe (data changes four SCLK cycles before the next doubleframe begins).
PCM 24: Freeze Signaling
Synchronization status signal which informs
the signaling processor that current signaling
should be frozen. This signal goes actife if
- one or more framing bit errors are found in
a superframe,
- loss or receiver synchronization, or
- a receipe slip is detected
It is cleared after an error-free superframe.
FREElS will be inhibited by setting bit RCO.
DFRl. During alarm simulation, this signal goes
active during simulation steps 2 and 6 if not
disabled via RCO.DFRl.
3
40
1
4
5
AINT
Siemens Components, Inc.
49
PEB 2035
Pin Definitions and Functions (cont'd)
PL-CC P-DIP
Symbol
Pin No. Pin No.
5
3
Input (I)
Function
Output (0)
AI NT
0
Alarm Interrupt
Setting bit CCR.AINT switches the output to the
Alarm Interrupt function. It is triggered by any
of the alarm sources which are enabled via
register MASK. Acknowledging is done by
writing a "1" to bit LOOP.AIA.
6
4
RCHPY
0
Receive Channel Parity
Even/Odd parity signal which supplements the
number of ones of a received channel to an
even/odd quantity while sending channel data
to output ROO. The parity type is programmed
by bit RCO.RPYS.
7
5
RFSPQ
0
Receive Frame Synchronous Pulse
(Active Low)
Framing pulse derived from the received PCM
route signal. During loss of synchronization
(bit RSR.LOS), this pulse is suppressed (not
influenced during alarm simulation).
Pulse Frequency: 8 kHz
488 ns [PCM 30)
Pulse Width:
648 ns [PCM 24)
8
6
XOID/
XMFB
0
PCNI 30: Transmit Opticallntertace
Data
Unipolar NRZ data sent to fiber optical interface with 2048 kbiVs. The output sense is programmed via bit XCO.XDOS. Data is clocked
with the rising edge of XRCLK.
PCM 24: Transmit Multiframe Begin
Marks the beginning of every transmitted superframe (used for synchronizing). Additional
pulses are provided which mark
- frame 13 of the ESF-format to allow access
to the data link channel. The flag MRF.xMB
marks the multiframe begin.
- every 12 frames when using the F72 format.
The additional status flag MFR.XRS marks
the beginning of the DL-channel.
The pulses which are normally two frames
long may be reset by writing a "1" to the
acknowledge bit XFDL.XMAK.
Siemens Components, Inc.
50
PEB 2035
Pin Definitions and Functions (cont'd)
PL-CC P-DIP
Symbol
Pin No. Pin No.
Input (I)
Function Bus
Output (0)
9
10
11
12
13
14
15
16
7
8
9
10
11
12
13
14
00
01
02
03
04
05
06
07
I/O
Data Bus
8-bit bi-directional tristate data lines which
interface with the system's data bus. These
lines carry data and control/status information
to and from the ACFA.
17
15
Voo
I
Power +5 V Power Supply
18
19
20
21
16
17
18
19
AO
A1
A2
A3
I
Address Bus
These inputs interface with four lines of the
system's address bus to select one of the
internal registers. Write access to address "OE"
and "OF" is not allowed.
ROQ
I
Read Enable (Active Low)
This signal indicates a read operation. If both
CEQ and ROQ are active, status information
of the registers selected via AO-A3 will be read
from the ACFA. If access to the internal signaling stacks is enabled by setting bit XCO.lSIG,
the data from the stack: RSIG may be read
when ACKNLQ and ROQ are active.
22
25
21
WRQ
I
Write Enable (Active Low)
This signal indicates a write operation. If both
CEQ and WRQ are active control information
may be written to the registers selected via
AO-A3.lf access to the internal signaling stacks
is enabled by setting bit XCO.lSIG data may be
written to the stack XSIG when ACKNLQ and
WRQ are active.
26
22
CEQ
I
Chip Enable (Active Low)
A low signal enables normal read/write access
to the internal registers.
27
23
COS
I
Carrier OUT of Senrice
A high signal at this input enables transmission
of AIS via outputs XOOP, XDOM, and XOIO
without any framing structure.
Siemens Components, Inc.
51
PEB 2035
Pin Definitions and Functions (cont'd)
PL-CC P-DIP
Symbol
Pin No. Pin No.
Input (I)
Function
Output (0)
28
24
SCLK
I
System Clock
Working clock for the ACFA with a frequency
of 4096 kHz or 8192 kHz (selected by bit
MODE.SCLK)
29
25
RRCLK
I
Receive Route Clock
Extracted from the incoming data pulses by
the line interface unit (e.g., IPAT, PEB 2235).
Clock Frequency: 2048 kHz [PCM 30]
1544 kHz [PCM 24]
30
31
26
27
RDIM
RDIP
I
Receive Data in Minus
Receive Data in Plus
Inputs for received dual rail P"CM (+) and PCM
(-) route signals which will be latched on
negative transitions of RRCLK. Input sense is
selected by bit RCO.RDIS (after RESET: active
low). Signal decoding depends on the PCM
mode selected via bit MODE.PMOD:
- PCM 30: HDB3 line code with 2048 kbitls
- PCM 24: If optical interface mode is disabled
the selected line code with 1544 kbitls depends on bit MODE.CODE (B8ZS or AMI with
B7 stuffing). After enabling optical interface
mode via bit MODE.OPT port RDIP will be
switched to input for Single rail unipolar data.
In this case, port RDIM has no function.
32
28
SYPQ
I
Synchronous Pulse
Defines the beginning of time-slot 0 at system
highway ports RDO, and XDI in conjunction
with the values of registers RCO.RCO, RC1.RTO,
CXO.CXO, and XC1.XTO.
Pulse Cycle: Integer multiple of 1251J.s.
33
29
RaiD
I
PCM 30: Receive Optical Interface
Data
Unipolar data received from fiber optical interface with 2048 kbitls. The input sense is programmed via bit RCO.RDIS. Data is clocked on
the falling edge of RRCLK if optical interface
mode is enabled via bit MODE.OPT.
Siemens Components, Inc.
52
PEB 2035
Pin Definitions and Functions (cont'd)
PL-CC
P-DIP
Pin No. Pin No.
33
29
Symbol
Input (I)
Function
Output (0)
XRCLK
I
PCM 24: Transmit Route Clock
Inputtor 1544 kHz transmit route clock provided
from an external clock generator. To avoid
transmit slips it must be phase locked to a
common submultiple ofthe system ciockSCLK
such as 8 kHz. In case of an error condition
reported via bitASRXSLPthe transmittime-slot
counter has to be set to its initial start position
by programming its offset value XC1.XTO.
34
30
XDI
I
Transmit Data IN
Transmit data received from the system internal
highway with 4096 kbiVs or 2048 kbiVs (bit
MODE.lMOD). Data is clocked on the falling
edge of SCLK. The delay between the beginning of time slot 0 and the initial edge of SCLK
(after SYPQ goes active) is determined by the
values of Transmit Time-Slot Offset XC1XTO
and Transmit Clock-Slot Offset XCOXCO. Additionally, for PCM 24 the channel/time slot correspondence between route and system side
ist selected via bit MODE.CTM.
35
31
RESQ
I
RESET (Active Low)
A IQw Signal will initialize all internal flipflops.
The ACFA is switched to PCM 30 mode. All
output stages are tristated while RESQ is
active.
36
32
ACKNLQ
I
DMA Acknowledge (Active Low)
If access to internal Signaling stacks is enabled
via bit XCO.lSIG this input acts as an "access
enable" to the internal stacks RSIG and XSIG
in conjunction with a read/write command without the need of generating the chip enable
Signal CEQ. In this case is should be connected
to the acknowledge output of the DMA controller to enable I/O-to-memory transfers.
PCM30
No function if XCO.ISIG is set to "0". In that
case this input has to be fixed either to Voo
or to Vss.
Siemens Components, Inc.
53
PEB 2035
Pin Definitions and Functions (cont'd)
PL-CC P-DIP
Symbol
Pin No. Pin No.
36
32
XSIG
Input (I)
Function
Output (0)
I
PCM 24: Transmit Signaling Data
If XCO.lSIG is set to "0" the external signaling
mode is enabled. This port acts as input for
the signaling data requested by the marker
XSIGM. Data is clocked on the falling edge of
SCLK. If not used port XSIG should be tied
to port XDI.
37
33
XCHPY
I
Transmit Channel Parity
Externally generated even/odd parity signal
which supplements the number of ones of each
transmit channel on XOI to an even/odd quantity. Latching of data on XCHPY is coincident
with latching of the LSS (bit 8) of the corresponding time slot if the external transmit
channel parity mode is enabled via bitXCO.EPY.
The parity type is programmed by bitXCO.EPYS.
NOTE: To avoid difficulties for external parity
generation the parity signal related to channels
with signaling information is adjusted internally.
38
34
Vss
I
GND (0 V)
39
35
RSIGM
0
Receive Signaling Marker
- PCM 30: Marks time slot 16 of every received
frame at pin ROO.
- PCM 24: When using CCS or CAS-CC signal-
ing schemes (bit MOOE.SIGM = 0) RSIGM
marks
a) time slot 31 (speech channel 24) in channel
translation mode 0 (bit MOOE.CTM = 0)
b)time slot 23 (speech channel 24) in channel
translation mode 1. Setting bit FMR.SM24
shifts the marker to time slot 16
(speech channel 17).
When using the CAS-SR Signaling scheme,
every six frames the robbed bit of each channel
is marked.
Siemens Components, Inc.
54
PEB 2035
Pin Definitions and Functions (cont'd)
PL-CC
P-DIP
Pin No. Pin No.
39
35
Symbol
Input (I)
Function
Output (0)
RREQ
0
Receive Request
If access to the internal signaling stacks RSIG
and XSIG is enabled via bit XCO.ISIG, this pin
acts as a DMA or interrupt request. It requires
the controller to read the stack RSIG.
RREQ will be held active until the first read
access to RSIG is finished. It will be generated
- PCM 30: once a double frame
- PCM 24: every three frames in CCS/CAS-CC
mode, or once a signaling frame (every six
frames) at CAS-BR mode.
The output will be cleared with the first read
access to RSIG.
40
36
XSIGM/
XREQ
0
Transmit Signaling Marker
Its function is equivalent to RSIGM for the data
stream at ports XDI and XSIG
(XSIG: PCM 24 mode only).
Transmit request
Its function is equivalent to RREQ for writing
data to the stack XSIG.
41
37
XRCLK/
RMFB
0
PCM 30: Transmit Route Clock
2048 kHz clock derived from the internal clock
of 4086 kHz.
PCM 24: Receive Multiframe Begin
Marks the beginning of every received superframe (used for synchronizing). Additional pulses are provided which mark
- frame 13 of the ESF format to allow access
to the data link channel. The flag MFR.RMB
marks the multiframe begin.
- every 12 frames when the F72 format is used.
The additional status flag MFR.RRS signals
that the first six bits of the DL-channel have
been received (RMFB goes active with the
beginning offrame 37 ofthe F72 multiframe).
The pulses which normally are two frames
long may be reset by writing a "1" to the
acknowledge bit XFDL.RMAK.
Siemens Components, Inc.
55
PES 2035
Pin Definitions and Functions (cont'd)
PL-CC P-DIP
Symbol
Pin No. Pin No.
Input (I)
Function
Output (0)
42
38
XDOP
0
43
39
XDOM
Transmit Data OUT Plus
Transmit Data OUT Minus
Outputs for transmitted dual rail PCM (+) and
PCM (-) route signals which will be clocked
on rising edge of XRCLK. Output sense is selected by bit XCO.XDOS (after RESET: active
low). Signal encoding depends on the selected
PCM mode
(MODE.PMOD) :
- PCM 30: HDB3 line code with 2048 kbiVs
- PCM 24: If optical interface mode is disabled
the selected line code with 1544 kbiVs depends on programming bit MODE.CODE
(B8ZS or AMI with B7 stuffing). After enabling
optical interface mode via bit MODE.OPT
port XDOP will be switched to output single
rail unipolar data with 100% duty cycle.
Siemens Components, Inc.
56
PEB 2035
Block Diagram
RFSPo.
11
RRCLK
XRCLK
11
SYPQ
SCLK
,--'---- -' ACKNLQ 11
RSIGM I RREU
XSIGM/XRED.
RMFB 1}
XMFB 1}
I-----.----~ ROD
ROID
RDIP
RDIM
RCHPY
OFPY
11
lIXOIO
XOOP
XOOM
14--~XOI
'-'_--/ XSIG 1}
~...- - - - I XCHPY
XTOP
XTOM t - - - - '
Alarm
Interrupt
COS
AINT
11
A3-0
07-0
ROO. WRQ CEQ RESQ
The ACFA comprises complete paths for receive and transmit direction for connecting
the primary access line interface unit to the system internal PCM highway:
The receive/transmit link interface with encoder/decoder and alarm detectors connects
the ACFA to the line interface unit (e.g. IPAT, PES 2235).
The receiver/transmitter perform frame alignment/synthesis, CRC checking/generation,
alarm and signaling extraction/insertion.
The receive/transmit speech memory compensates the wander and jitter of the assigned
route clock. Time-slot assigment to the system internal highway is also handled via this
memory.
The parallel microprocessor interface can be used for controlling and monitoring of all
functions and alarms as well as extraction and insertion of signaling data. Additionally,
a Direct Memory Access (DMA) interface and bundel of specific signals enable powerfull
support for a varity of possible external signaling controllers.
Siemens Components, Inc.
57
PEB 2035
Functional Description
General Functions and Device Architecture
1 Receive Path
Receive Link Interface
For data input, two different data types with selectable input sense are supported:
• Dual rail data (PCM[+]. PCM[-]) at ports RDIP, RDIM received from a line interface unit
(e.g. PEB 2235, Siemens ISDN Primary Access Transceiver, IPAT)
• Unipolar data at port RaiD (PCM 30) or at port RDIP (PCM 24) received from a fibre
optical interface.
Latching of data is done using the falling edges of the Receive Route Clock (RRCLK,
2048 kHz or 1544 kHz) recovered from the PCM receive data stream. Dual rail data is
subsequently converted into a single rail, unipolar bit stream. In PCM 30 mode, the HDB3
line code is used along with double violation detection or full code violation detection
(selectable). In PCM 24 mode, a selection between B8ZS or simple AMI (ZCS) coding is
provided. In this case, all code violations that do not correspond to zero substitution rules
will be detected.
These errors increment the code violation counter.
When using the unipolar input mode, the decoder is by-passed and no code violations
will be detected.
Additionally, the receive link interface comprises the alarm detection for AIS (Alarm
Indication Signal: unframed bit stream with constant logical 'one') and NOS (no signal:
input signal with an insufficient bit rate or an insufficient density of ones).
The single rail bit stream is then processed by the receiver.
Receiver
For both the PCM 30 mode and the PCM 24 mode the following functions are performed:
• Synchronization on pulse frame
• Synchronization on multiframe
• Error indication when synchronization is lost. In this case, AIS is sent to the system side.
• Initiating and controlling of resynchronization after reaching the asynchronous state.
This may be automatically done by the ACFA, or user controlled via the microprocessor
interface.
• Detection of remote alarm indication from the incoming data stream.
• Separation of service bits and data link bits. This information is stored in special sta.tus
registers.
• Generation of control signals to synchronize the CRC checker, the parity generator,
and the receive speech memory write control unit.
If programmed and applicable to the selected multiframe format, CRC checking of the
incoming data stream is done by generating check bits for a CRC submultiframe (or ESF
multiframe) according to either the CRC 4 procedure (PCM 30, refer to CCITT Rec.
G704 § 2.3.3) or the CRC 6 procedure (PCM 24, refer to CCITT Rec. G704 § 3.1.1.3).
These bits are compared with those check bits that are received during the next CRC
(sub-)multiframe. If there is at least one mismatch, the CRC error counter will be incremented.
Siemens Components, Inc.
58
PEB 2035
Receive Speech Memory
The speech memory is organized as a two-frame elastic buffer with a size of 64 x 9 bit
or 48 x 9 bit for PCM 30 or PCM 24, respectively (8-bit channel data plus one parity bit).
The functions are:
•
•
Clock adaption between system clock (SCLK) and route clock (RRCLK).
Compensation of input wander and jitter. Maximum of wander amplitude:
PCM 30: 95 UI (1 UI = 488 ns)
PCM 24: 63 UI in channel translation mode 0
39 UI in channel translation mode 1
(1 UI = 644 ns)
• Frame alignment between system frame and receive route frame
• Reporting and controlling of slips
Controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel, channel-serial data which is circularly written to the speech memory
using the receive route clock (RRCLK). At the same time, a parity signal is generated
over each channel and also stored in the speech memory.
Reading of stored data is controlled by the system clock (SCLK) and the synchronous
pulse (SYPQ) in conjunction with the programmed offset values for the receive time-sloV
clock-slot counters. After conversion into a serial data stream and parity checking (errors
are reported via the status registers), the data is given out via port ROO. Channel parity
information is output at port RCHPY with selectable output sense. In PCM 24 mode, two
channel translation modes are provided (refer to § 2.3.4). Unequipped time-slots will be set
to 'FF' hex. For both PCM modes, two bit rates (2048/4096 kbiVs) are selectable via the
microprocessor interface.
A slip condition is detected when the write address pointer and the read address pOinter
of the speech memory are nearly coincident. In this case, a negative slip (the next received
frame is skipped) or a positive slip (the previous received frame is read out twice) is
performed, depending on the difference between RRCLK and SCLK.
2 Transmit Path
The inverse functions are performed for the transmit direction.
The PCM data is received from the system internal highway at port XDI with 2048 kbiVs
or 4096 kbiVs. The channel assignment is equivalent to the receive direction. All unequipped time-slots will be ignored. Latching of data is controlled by the system clock
(SCLK) and the synchronous pulse (SYPQ) in conjunction with the programmed offset
values for the transmit time sloVclock-slot counters.
Transmit Speech Memory
The transmit speech memory is operational only in the PCM 24 mode. This one-frame
elastic buffer with a size of 24 x 9 bit (8-bit channel data plus 1 parity bit) serves as a
temporary store for the PCM data to adapt the system clock (SCLK) to the externally
generated transmit route clock (XRCLK), and to re-translate channel structure used in the
system to that of the line side. Its optimal start position is initiated when programming
the above offset values. Normally, XRCLK has to be phase locked to a common submultiple
of SCLK such as 8 kHz. A difference in the effective data rates of system side and
Siemens Components, Inc.
59
PEB 2035
transmit side may lead to an overflow/underflow of the transmit speech memory: thus,
errors in data transmission to the remote end may occur. This error condition (transmit slip)
is reported to the microprocessor via the status registers. It signals that the external clock
generation is defective.
Maximum wander amplitude in PCM 24 mode:
• Channel translation mode 0: 29 UI
• Channel translation mode 1: 23 UI
(1 UI = 644 ns)
Because this is, under normal circumstances, a rare error condition no automatic action
is taken by the transmit speech memory as opposed to the receive speech memory in
the case of a positive or negative slip. In this case the ACFA requires are-initialization
of the transmit memory by re-programming of the transmit time-slot counter. After that,
this memory has its optimal start position.
In PCM 30 mode, the transmit route clock (XRCLK) is derived directly from the system
clock by an internal clock divider. Consequently, the data received from the system interface is switched through without the need of intermediate storage.
The parity generation/checking mechanism is symmetrical to the receive path. The channel
data is checked with the channel parity information generated internally or externally
(input at port XCHPY with selectable input sense). Errors are reported to the microprocessor
interface. To avoid difficulties with external parity generation, the parity signal for non-speech
data (e.g. signaling data or channels with bit robbing information) is computed internally.
Transmitter
The serial bit stream is then processed by the transmitter which has the following functions:
• Frame/multiframe synthesis of one of the six selectable framing formats
• Insertion of service and data link information
• Remote alarm generation
Transmit Link Interface
Similar to the receive link interface two different data types with selectable output sense
are supported:
• Dual rail data (PCM[+], PCM[-]) at ports XDOP, XDOM with 50% duty cycle transmitted
to a line interface unit (e.g. PEB 2235, Siemens ISDN Primary Access Transceiver, IPAT).
Single rail data is converted into a dual rail bit stream. In PCM 30 mode, the HDB3 line
code is employed. In PCM 24 mode, selection between B8ZS or simple AMI coding
with zero code suppression (B7 stuffing) is provided.
• Unipolar data at port XOID (PCM 30) or at port XDOP (PCM 24) with 100% duty cycle
transmitted to a fibre optical. interface.
Clocking of data is done with the positive transitions of the transmit route clock: XRCLK
(2048 kHz or 1544 kHz). In PCM 30 mode, XRCLK is generated by the ACFA, whereas in
PCM 24 mode it must be generated by an external clock generator.
Additionally, the dual rail outputs XTOP and XTOM are provided for test applications.
Siemens Components, Inc.
60
PEB 2035
3 Additional Functions
Signaling Support
Generation of all supporting signals to achieve simple access to signaling information
(CCS, CAS-CC, CAS-BR, FDL) at the system interface. In PCM 24 mode, the additional
input XSIG is provided for connection to a bit-robbed signaling controller. Furthermore,
the controlling of the internal signaling stacks is done by this unit.
Alarm Interrupt
Normally, the control of data transmission via the PCM line is done by polling the internal
status registers of the ACFA at equidistant time intervals.
However, for fast error handling the option exists to configure a specific output port as
interrupt port (AINT). This signal may be connected to an interrupt input of the board
processor. Triggering of this output may be caused by up to eight maskable interrupt
sources.
Single Channel Loop Back
As one of the extended test options, the single channel loop back enables reflection of
a selected channel back to the system interface at port ROO.
Siemens Components, Inc.
61
PEB 2035
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Ambient temperature under bias
TA
Oto 70
Storage temperature
Tstg
-65 to 125
°C
°C
Voltage on any pin
with respect to ground
Vs
-0.4 V to Voo +0.4 V
V
DC Characteristics
TA = 0 to 70°C; Voo = 5 V ± 5%; Vss = 0 V
Parameter
Symbol
L-input voltage
H-input voltage
VtL
VtH
L-output voltage
VOL
H-output voltage
H-output voltage
VOH
VOH
Power supply current
Icc
Input leakage current
Output leakage current
III
Characteristics
TA = 25°C; Voo = 5 V ± 5%; Vss
Limit Values
min.
max.
Unit
-0.4
0.8
V
Voo +O.4
V
0.45
V
IOL =2 mA
V
V
I oH =-400 ~A
I oH =-100 ~A
18
mA
Voo= 5 V
Inputs at OVIVoo ,
no output loads
10
~A
2.0
2.4
Voo-0.5
ILO
Test Conditions
OV < VtN< Voo to OV
OV < VOUT < Voo to OV
=0V
Limit Values
Parameter
Symbol
min.
max.
Unit
Input capacitance
C IN
5
10
pF
Output capacitance
C OUT
10
20
pF
liD
CIO
8
15
pF
Siemens Components, Inc.
62
PEB 2035
AC Characteristics
TA = 0 to 70°C; Vee = 5 V ± 5%, Vss = 0 V
Inputs are driven to 2.4 V for a logical '1' and to 0.4 V for a logical '0'. Timing measurements
are made at 2.0 V for a logical '1' and at 0.8 V for a logical '0'.
The AC testing input/output waveforms are shown in the figure 1.
Figure 1
Input/Output Waveform for AC Tests
2.0"-.....
/2.0
Test Points
0.8/
"-.....0.8
Output load: 150 pF load capacitance in connection with resistive loads for
and IOH = -100 uA.
Rise/fall times: 20 ns max.
Siemens Components, Inc.
63
IOL
= 2 mA
PEB 2035
(.LP Interface Timing
Figure 2
(.LP Read Timing
Read Cycle
AO - A7
CEO.
Roa
00 - 07
(.LP Read Timing
Limit Values
Parameter
Symbol
CEO and ADDRESS valid to DATA valid
tco
CEO and ADDRESS stable before ROO
tCR
ROO to DATA valid
tRO
ROO pulse width
tRR
DATA float after ROO
min.
120
ns
ns
110
120
tOF
10
tRC
ADDRESS hold after ROO
tRA
ROO control interval
tRI
0
0
70
64
Unit
0
CEO hold after ROO
Siemens Components, Inc.
max.
ns
ns
30
ns
ns
ns
ns
PEB2035
Figure 3
j.l.P Write Timing
Write Cycle
AO - A7
CEn
- - - t W1
WRQ
DO - 07
AI NT
RMFB
XMFB
1) :
1)
1)
---------4I(,'t~~------
_ _ _ _I-_tWAK_~
1)
In connection with assigned values of AO-A3 and 00-07
j.l.P Write Timing
Limit Values
Parameter
Symbol
min.
CEQ and ADDRESS valid to WRQ valid
max.
Unit
tcw
30
ns
DATA setup before end of write
tow
30
ns
DATA hold after WRQ
two
10
ns
WRQ pulse width
tww
70
ns
CEQ hold after WRQ
twc
10
ns
ADDRESS hold after WRQ
tWA
10
ns
WRQ control interval
tWI
70
Interrupt acknowledge delay
tWAK
Siemens Components, Inc.
65
ns
2xtCP4 +60
4xtcP8 +80
ns
PEB 2035
Figure 4
DMATiming
110 Read Cycle
..
tORR
ACKNLa" ROO.
-- t
DO - 07
ORO
___________.._t_oo__
~·~I
>________
--~...
_____
o_a_ta__-:-___
I-'",l.-
RREa
110 Write Cycle
ACKNLQ." WRQ.
DO - 07
__
i=-~~~_-~ t
__________
H-- --L
O_W_w_______
-
."
tOWI
towo
~~-- t.~O~a~ ~~I---------
XREa
~""'L
DMATiming
Limit Values
Parameter
Symbol
RDQ to DATA valid
t ORO
DATA float after RDQ
tOOF
RDQ pulse width
tORR
RDQ control interval
tORI
RREQ reset after RDQ
tRRE
DATA setup before end of write
toow
DATA hold afterWRQ
t owo
WRQ pulse width
. toww
WRQ control interval
tOWI
XREQ reset after WRQ
tXRE
Siemens Components, Inc.
66
min.
10
120
70
max.
110
30
Unit
ns
ns
ns
ns
130
30
10
70
70
ns
ns
ns
ns
ns
130
ns
PEB 2035
Serial Interface Timing
Figure 5
System Interface Timing
SCLK
8192 kHz
SCLK
4096 kHz
SYPQ
ROO
RSIGM, XSIGM
RMFB, XMFB '_1- t - - "
FREEZS
RCHPY
OFPY
--tsxoXRCLK 21
[PCM 301
....
Ir--~r--
XDI
XSIG
XCHPY
,1 :
21:
If not Reset via ~P Interface
For Even Values of XCO.XCO, Otherwise Inverted
Siemens Components, Inc.
67
PEB 2035
System Interface Timing
Limit Values
4096 kHz SCLK
Symbol
SCLK period 8 MHz
tcps
SCLK period 8 MHz low
tCPSl
SCLK period 8 MHz high
tCPSH
SCLK period 4 MHz
tCP4
SCLK period 4 MHz low
tCP4l
110
ns
tCP4H
110
ns
SYPQ setup time
tss
40
SYPQ hold time
tSH
40
SYPQ inactive setup
tSI
t CP4 +30
ROO propagation delay
tROO
90
110
ns
SCLK period 4 MHz high
min.
8192 kHz SCLK
Parameter
max.
min.
max.
typ.122
ns
40
ns
40
ns
tylll.244
tCP4 -30
Unit
ns
tCP8 -40
tcps +40
ns
ns
40
ns
2xtcps +30
Marker propagation delay
tMS
100
120
ns
Marker hold
tMH
100
120
ns
Parity propagation delay
tpyo
100
120
ns
XRCLK to SCLK delay
tsxo
110
130
ns
Transmit data setup
tXIS
30
30
ns
Transmit data hold
tXIH
30
30
ns
Reset Timing
Limit Values
Parameter
Symbol
min.
RESQ low
tREl
2000
Siemens Components, Inc.
68
max.
Unit
ns
PEB 2035
Figure 6
Line Interface Timing
RRCLK
ROIP, ROIM
ROID
RFSPQ
•
XRCLK
XOOP, XOOM
XTOP, XTOM
J
xoro
xOOP
1) :
1)
PCM 24, Optical Interface Mode
Line Interface Timing
Limit Values
PCM24
PCM30
Parameter
Symbol
RRCLK clock period
t CPR
RRCLK clock period low
t CPRL
220
300
ns
RRCLK clock period high
tCPRH
220
300
ns
Receive data setup
tRIS
30
30
ns
Receive data hold
tRIH
30
30
ns
RFSPQ propagation delay
t RFSD
XRCLK clock period
tcpx
XRCLK clock period low
t CPXL
XRCLK clock period high
t CPXH
Transmit data output delay
tXOD
Transmit data output hold
min.
min.
typ, 488
max.
typ.648
130
130
ns
300
69
50
ns
ns
50
t XOH
ns
ns
300
O·
Unit
typ.648
2xtCP4
4xtCP8
• Test conditions: O°C, CL = 50 pF
Siemens Components, Inc.
max.
20'
90
ns
90
ns
SIEMENS
ISDN Primary Access Transceiver (IPAT)
Preliminary Data
PEB2235
CMOSIC
Type
Ordering cOde
Package
PES 2235-C
067100-H8604
C-DIP-28
PES 2235-P
067100-H8603
P-DIP-28
The ISDN Primary Access Transceiver IPAf™ (PES 2235) is a monolithic CMOS device
which implements the analog receive and transmit line interface functions to primary rate
PCM carriers. It may be programmed or hard wires to operate in 24 channel (T1) or
32 channel (CEPT) carrier systems.
The IPAT recovers clock and data using an adaptively controlled receiver threshold. It is
transparent to ternary codes and shapes the output pulse following the AT&T Technical
Advisory # 34 or CCITI G.703. The jitter tolerance of the device meets the latest CCITI
(1.431 DRAFT), latest US recommendations (TR-TSY-000312), NTI specification and many
other specifications by AT& T/SELLCORE. Diagnostic facilities are included.
Specially designed line interface circuits simplify the tedious task of protecting the device
against overvoltage damage while still meeting the return loss requirements.
The IPAT is suitable for use in a wide range of voice and data applications such as for
connections of digital switches and PASX's to host computers, for implementations of
primary ISDN subscriber loops as well as for terminal applications. The maximum range is
determined by the maximum allowable attenuation.
The IPAT's power consumption is mainly determined by the line length and type of the cable.
Features
• ISDN line interface for 1544 and 2048 kbiVs (T1 and CEPT)
• Data and clock recovery
• Transparent to ternary codes
• Low transmitter output impedance for a high return loss with reasonable protection
resistors (CCITI G.703 requirements for the line input return loss fulfilled).
• Adaptively controlled receiver threshold
• Programmable pulse shape for T1 applications
• Jitter specifications of CCITI 1.431 DRAFT, TR-TSY -000312 and many AT &T I SELLCORE
publications met.
• Jitter tolerance of receiver: 0.43 UI s
• Implements local - and remote loops for diagnostic purposes
• Monolithic line driver for a minimum of external components
• Low power, reliable 2 \..I. CMOS technology
70
PES 2235
Pin Configurations
(top view)
PL-CC-28
P-DIP-28
N
VOOR
VSSR
RL1
RCLK
VOO2
RDObl
RL2
ROOP
XTAL2
PEB 2235
IPAT ™
LSD
14 1S 16
VI
::..
LS2
XOIN
Voox
XTIP
XL1
XTIN
Vssx
TEST
XL2
RL
X(LK
XDIP
XDIN
XTIP
X
N..Jt-Z
VI..J 0:: V1 _
XCLK
XOIP
Vsso
VOOO
XL1
vooo
LS1
ROON
ROOP
ES
Voox
VSSO
XTAL1
IX:::':::
RL2
LL
XTAL2 6
XTA L1
LSO ~ PES 2235
IPApM
LS1
LS2
rs
LL
Q:"
~~~~g
X
LJ.J
f-
t-
x
Pin Definition and Functions
Pin No.
Symbol
Input (I)
Output (0)
Function
1
VOOA
I
Positive power supply for the receive subcircuits
2
RL1
I
Line receiver pin 1
3
VOO2
0
Reference voltage output for tapping the input transformer
4
RL2
I
Line receiver pin 2
Siemens Components, Inc.
71
PES 2235
Pin Definition and Functions (cont'd)
Symbol
Input (I)
Output (0)
Function
5
LL
I
Local loopback: A high level selects the device for the
local loop back mode
6
7
XTAL2
XTAL1
I
I
Reference clock input: A 24704 or 32768 kHz crystal
reference should be connected to these pins for T1 or
CEPT applications, respectively. It is also possible to
connect an external precision clock to XTAL1 leaving
Pin No.
XTAL2 unconnected. The external reference must be
provided at full CMOS levels.
8
9
10
LSO
LS1
LS2
I
I
I
Line length select: determine to what extent the line output
signals are preshaped prior to transmission
11
Voox
I
Positive power supply for transmit subcircuits
12
XL1
0
Line transmitter pin 1
13
Vssx
I
Ground for transmit subcircuits
14
XL2
0
Line transmitter pin 2
15
RL
I
Remote loopback: A high level puts the device to the
remote loopback mode
16
TEST
I
Test input not connected or connected to Voo
17
18
XTIP
XTIN
I
I
Positive and negative transmit test data inputs, active low,
half or fully bauded
19
20
XDIP
XDIN
I
I
Positive and negative transmit data inputs, active low,
half or fully bauded
21
XCLK
I
Transmit clock
22
Vooo
I
Positive power supply for the digital subcircuits
23
Vsso
I
Power ground supply for the digital subcircuits
24
CS
I
Chip Select: A low level selects the PES 2235 for a register
write operation
25
26
RDOP
RDON
0
0
Receive data output positive and negative, fully bauded,
active low
27
RCLK
0
Receive clock
28
VSSR
I
Power ground supply for receive subcircuits
Siemens Components, Inc.
72
PEB 2235
Logic Symbol and Wiring
Figure 1
Logic Diagram of the IPAT
Microprocessor
Interface
,---:--~A'-_~
XTIN 14-----1
XTIP 14-----1
RCL K 1------1~
ROON
AC FA
ROOP Dual Rail
PES 2035
XCLK lnterface
XDIP i-*-----j
*
XDIN i-*-----j
IPApM
PES 2235
Ternary
Interface
SYSTEM
VOD Vss VD02
Supply
* Advanced CMOS Frame Aligner ACFA (PEB 2035) for frame alignment, coding/decoding,
error checking, elastic buffering and facility signaling
Figure 2
External Wiring of the IPAT
' ' ;]
Line
Rz
Over
Voltage
Protection
J..
100nF
28
27 100nF
26
25
3
4
5
PES 2235
IPApM
Rl
9
Rl
10
11
12
13
14
T'M'~
Over
Voltage
Protection
line
Siemens Components, Inc.
1fJF
~-
73
100nF
1~
18
17
16
15
PEB2235
Functional Description
Figure 3
Functional Block Diagram of the IPAT
LL
LSO LS 1 LS2
RL
Receiver
Basic Functionally
The receiver recovers data from the ternary coded signal at the ternary interface and
outputs it as two unipolar signals at the dual rail interface. One of the lines carries the
positive pulses, the other the negative pulses of the ternary signal.
The signal at the ternary interface is received at both ends of a center-tapped transformer
as shown in figure 4.
Figure 4
Receiver Configuration
__----<~--.. RL1
Line
~-+---"'VDD2
Siemens Components, Inc.
74
PEB 2235
The transformer is center-tapped at the IPAT-B side. The recommended transmission
factors for the different line characteristic impedances are listed in table 1.
Table 1
Recommended Receiver Configuration Values
Application
T1
Characteristic
Impedances [OJ
100
120
75
28.7
60
60
R2
± (2.5%) [OJ
t2 : t1
= t2: (t11 + t12)
CEPT
69:52
69:(26+26)
52:52
52 (26 + 26)
41:52
41 :(26+26)
Wired in this way the receiver has a return loss
ar > 12 dB for 0.025 fb~f~0.05 fb'
a r >18dB for 0.05
fb~f~1.0fband
a r >14dB for 1.0
fb~f~1.5fb'
with fb being 2048 kHz. Thus is complies with CCID G.703.
The receiver is transparent to the logical 1's polarity and outputs positive logical 1's on
RDOP and negative logical 1's on RDON. RDON and RDOP are active low and fully bauded.
The comparator threshold to detect logical 1's and logical O's is automatically adjusted
to be 56% of the peak signal level.
Provided the noise is below 10 IlV/-JRZ the bit error rate will be less than 10-7 . The data
is stable, and hence may be sampled at the falling edge of the recovered clock RCLK.
PLL
A digital PLL extracts the receive clock RCLK from the data stream received at the RL 1
and RL2 lines. The PLL uses as a reference either a crystal at XTAU and XTAL2 or an
external oscillator at XTAL 1. The IPAT-B does not remove any jitter. Since the crystal
frequency is 16 times the input data frequency the digital PLL adds an jitter of max. 0.0625 UI
(unit intervals). In the absence of an input signal the jitter of clock, and recovered data lies
within the tolerance range of the used reference.
Input Jitter Tolerance
The IPAT-B receiver's tolerance to input jitter complies to CelD and AT & T requirements
for CEPT and T1 application.
Figure·5 shows the curves of the different input jitter specifications stated above as well
as the IPAT-B performance at the S 1/S2 interfaces.
As can be seen in figure 5, the curve for the IPAT-B at low frequencies describes a
20 dB/decade fall off, and at high frequencies are horizontal (at least 0.43 UI).
Siemens Components, Inc.
75
PEB 2235
Figure 5
Comparison of Input Jitter Specification and IPAT Performance
-c...
OJ
~ 10 3
r
::0
Cl.
C
10
2
10' .. =.:::~;!::~
. . . . . . . . . . . ._._._.~._
43802
10°
Transmitter
Basic Functionality
The transmitter transforms unipolar data to ternary (alternate bipolar) return to zero signals
of the appropriate shape. The unipolar data is provided at XDIP (positive pulses) and XDIN
(negative pulses), synchronously with the transmit clock XCLK. XDIP and XDIN are active
low and can be half or fully bauded.
The transmitter includes a programmable pulse shaper to satisfy the requirements of the
AT & T Technical Advisory # 34 at the cross connect point for T1 applications. The pulse
shaper is programmed via the line length selection pins LSO, LS1 and LS2. The pulse
shape is formed using an analog PLL, which multiplies by four the transmit clock XCLK.
This signal is used internally to generate the four segment/bit transmit pulse (CEPT: two
segll)ent/bit).
For T1 application the line length selection supports both low capaCitance cable with a
characteristic line capacitance of C' S:40 nF/km 65 nF/mile (e.g. MAT, ICOT) and higher
capacitance cable with a characteristic line capacitance of 40 nF/km s: C' s: 54 pF/km
(65 nF/mile s: C' s: 87 nFlmile) e.g. ABAM, PIC and PULP cables. This ensures that for
various cable types the signal at the DSX-1 cross connect point complies with the pulse
shape of the AT & T Technical Advisory #34.
=
The line length is selected programming the LSO, LS1 and LS2 pins as shown in table 2.
Siemens Components, Inc.
76
PEB 2235
Table 2
Line Length Selection
PlC/PULP·Cable
range/m
LS2 LS1 LSO
-
CEPT
T1/NTI
T1
T1
T1
T1
T1
T1
000
001
010
01 1
100
1 01
110
111
0- 35
25 - 65
55- 95
85 -125
115-155
145 - 185
175 - 210
ICOT·Cable
range/m*
-
0- 80
65 - 145
130 - 210
195 - 275
260 - 340
325 - 405
390 - 470
Note; For ICOT-cable the characteristic impedance is 140 Q
By selecting an all-zero code for LSO, LS1 and LS2 the IPAT-B can be adopted for CEPT
applications.
The pulse shape for NTI applications is achieved by using the same line length selection
code as for the lowest T1 cable range. To switch the device into a low power dissipation
mode, XDIP and XDIN should be held high.
The transmitter requires an external step up transformer to drive the line. The transmission
factor and the source serial resistor values can be seen in figure 6 and table 3 for the
various applications.
Figure 6
Transmitter Configuration
1
R1 :.r----...--.
XL --t..:=
Rl
XL2
t12
[:2
Line
...
-----c:=J--~
Siemens Components, Inc.
77
PES 2235
Table 3
Transmitter Configuration Values
Application
T1
Characteristic line impedance [0]
100
120
75
26:69
26:52
26:41
4.3
15
15
t,,:t2 = t'2: t2
R, (± 2.5%) [0]
CEPT
Wired in this way the transmitter has a return loss
a r > 8 dB for 0.025 fb s: f s: 0.05 fb,
a r > 14 dB for 0.05 fb s: fS: fb and
a r > 10 dB for 1.0 fb s: fS: 1.5 fb.
with fb being 2048 kHz (CEPT applications). A termination resistor of 1200 is assumed.
In T1 applications the return loss is heigher than 10 dB.
Please note, that the transformer ratio at the receiver is half of that at the transmitter. The
same type of transformer can thus be used at the receiver and af the transmitter. At the
transmitter the two windings are connected in parallel, at the receiver in series. Thus,
unbalances are avoided.
output Jitter
In the absence of any input jitter the IPAT-B generates an output jitter at most 0.014 UI in
CEPT and 0.01 UI in T1 applications.
Local Loopback
The local loopback mode disconnects the receive lines RL 1 and RL2 from the receiver.
Instead of the signals coming from the line the data provided at XTIP and XTIN is routed
through the receiver. The XDIN and XDIP signals continue to be transmitted on the line.
The local loopback occurs in response to LL going high.
Remote Loopback
In the remote loopback mode the clock and data recovered from the line inputs RL 1 and
RL2 are routed back to the line outputs XL 1 and XL2 via the transmitter. As in normal
mode they are also output at RDOP, RDON and RCLK. XDIP and XDIN are disconnected
from the transmitter. In this mode a device jitter of 0.0765 UI for CEPT and 0.0725 UI
for T1 is added.
The remote loopback mode is selected by a high RL signal.
Siemens Components, Inc.
78
PEB 2235
Please keep in mind that the IPAT-B is not capable of removing jitter. Therefore in remote
loopback mode jitter is not reduced. In normal applications, however, the data stream
being output from the IPAT-B runs through an elastic buffer (e.g. the ACFA PEB 2035)
which itself reduces jitter.
Microprocessor Interface
The IPAT-B is fully controlled by five parallel data lines (LSD, LS1, LS2, LL and RL) and
one control line (CS). To adapt the device to a standard microprocessor interface the low
state of CS is decoded from the microprocessor address, CS, WR and ALE lines.
To hardwire the chip, CS must be fixed to ground.
Loss of Signal Indication
In the case that the signal at the line receiver input (pins RL 1, RL2) becomes smaller
than V1NS;OA Vop loss of signal is indicated. This voltage value correspondings to a line
attenuation of about 12 dB in the CEPT case. This is performed by turning both signals
RDOP, RDON after at least 16 bits simultaneously to 5 V, Le. a logical 0 or both lines.
The following ACFA processes this indication for the system.
Operational Description
• Reset
In order to work properly, the IPAfTM-B needs to be started with a software reset.
This is done by simultaneously setting the pins RL and LL to logical 1 (Le. 5 V) far
at least one bit period and releasing both lines thereafter simultaneously.
It is possible to connect the pins RL and LL to Voo and to consequently turn on the
power supply. In this way a power-up reset is achieved.
• Selection of CEPT of 11 Application
Besides the crystal frequency the selections of CEPT or T1 application is achieved
by setting the pins LS2, LS1, LSD simultaneously with the reset to 000 for CEPT
application or to a T1 line length code (001 ... 111 see table 2).
• Line Length Selection
In the second step the line selection code has to be given. This will be normally
the same one as in the first step.
The following figures explain the procedure in some examples.
Siemens Components, Inc.
79
I
PEB2235
Figure 7
Timing of Software Programming
for CEPT Applications
Figure 8
Timing of Software Programming
for T1 Application
LS~
LS
~
RL
-II'--_ __
RL
-II
LL
-II'--_ __
LL
-II
LS2 _ _ _ _ __
LS2
E8l
E8l
LS 1
LS 1
E8l
C8:I
LSO
C8:I
C8:I
LSO _ _ _ _ __
t
t--t
t
1.
2.
1. Reset and selection of CEPT application
2. Regular operation in CEPT application
Figure 9
Timing of Software Programming
for LL Operation at CEPT or T1 Application
RL
-II
LL
~
LS2
E8l
E8l
LS 1
C8:I
C8:I
LSO
C8:I
181
t
1.
t--t
2.
1. Reset
2. Local loop and line code selection
Siemens Components, Inc.
t--t
2.
1.
1. Reset and selection of T1 application
2. Regular operation in T1 application with
selected line code
80
PEB 2235
DC Characteristics
TA = 0 to 70 D C; Voo = 5 V ± 5%, Vss = 0 V.
Limit Values
Symbol
min.
max.
Unit
L-input voltage
ViL
-0.4
0.8
V
H-input voltage
ViH
2.0
Voo+0.4
V
L-output voltage
VOL
0.45
V
IOL=2 mA
H-output voltage
H-output voltage
VOH
VOH
V
V
IOH =-400 j.LA
I oH =-100j.LA
Input leakage current
Output leakage current
10
j.LA
fLO
OV OUT 0, OUT 2, OUT 4, OUT 6
~ TSC 0, TS[ 1, TS[ 2, TSC 3
v>
PE X
2045
system
} Interface
OClK
SynChrOn
IN 2, IN 6, IN 10, IN14 }
Interface
-"
v
III
Voo ~s SP ClK
Siemens Components, Inc.
IN 9,IN 13
94
OUT 1, OUT 3, OUT 5,OUT 7
PEB 2045
PEF2045
System Integration
The main application fields for the PEx 2045 are in switches and primary access units.
Figure 3 shows a non-blocking switch for 512 input and 512 output channels using only
two devices. Figure 4 shows how eight devices can be arranged to form a non-blocking
1024 channel switch.
Figure 3
\
Memory Time Switch 16/16 for a Non-blocking 512-Channel Switch
PE x
2045
c--
PCM 2MHz
IN
,
8
, 36
•
PCM 2MHz_
OUT
PE x
2045
-.
B
This is possible due to the tristate capability of the PEx 2045.
Figure 4
Memory Time Switch 32/32 for a Non-blocking 1024-Channel Switch
16
PEx
8
20451---+---..."./'---
PEx
2045
11
21
PEx
2045
12
PEx
2045
22
8
.---..---r--
-
PCM 2 MHz
PCM 2 MHz
IN
OUT
16
B
PE x
2045 I---_--r--
PE x
---;,~~--i 2045
13
23
PE x
2045
PEx
2045
24
Siemens Components, Inc.
14
95
B
\---...---r--
•
PEB2045
PEF2045
Functional Description
The PEx 2045 is a memory time switch device. It can connect any of 512 PCM input channels
to any of 256 output channels.
The input information of a complete frame is stored in the on-chip 4 kbit speech memory SM.
(See figure 5). The incoming 512 channels of 8 bits each are written in sequence into fixed
positions in the SM. This is controlled by the input counter in the timing control block with a
8 kHz repetition rate.
For outputting, the connection memory (CM) is read in sequence. Each location in CM pOints
to a location in the speech memory. The byte in this speech memory location is read into the
current output time slot. The read access of the CM is controlled by the output counter which
also resides in the timing control block.
Hence the CM needs to be programmed beforehand for the desired connection. The CM
address corresponds to one particular output time slot and line number. The contents of this
CM address points to a particular input time slot and line number (now resident in the SM).
The PEx 2045 works in standard configuration for usual switching applications, and in the
primary access configuration where it realizes, together with the PEB 2035 (ACFA) and the
PEB 2235 (I PAT) , the system interface for up to four primary multiplex address lines.
FigureS
Block Diagram of the
Il P
Interface
PEx 2045
'~~/I
Speech
Memory
SM
SP
Siemens Components, Inc.
elK
DUTO
96
DUT7
PEB2045
PEF2045
Operational Description
Power Up
Upon power up the PEx 2045 is set to its initial state. The mode and configuration register
bits are all set to logical 1, the clock shift register bits to logical O. The status register B-bit
is undefined, the Z-bit contains logical 0, the R-bit is undefined.
This state is also reached by pulling the WR and RD signals to logical 0 at the same time,
(software reset). For the software reset the state of CS is of no significance.
Initialization Procedure
After power up a few internal signals and clocks need to be initialized. This is done with the
initialization sequence. To give all signals and clocks a defined value the MTSC must
encounter three falling and two rising edges of the SP signal. The resulting SP pulses may
be of any length allowed in normal operation. the time interval between the two SP pulses
may be of any length down to 250 nsec.
With all signals being defined, the CM needs to be reset. To do that a logical 0 is written
into MOD:RC. STA:B is set. The resulting CM reset is finished after at most 250 f.Lsec and
is indicated by the status register B-bit being logical O. Changing the pulse shaping factor N
during CM reset may result in a CM reset time longer than 250 f.Lsec.
To prepare the PEx 2045 for programming the CM, the RI- bit in the mode register must be
reset. Note that one mode register access can serve to reset both RC and RI bits as well as
configurating to chip (i.e. selecting operating mode etc.).
Siemens Components, Inc.
97
PEB2045
PEF2045
Figure 6
Initializing the PEx 2045 for a 8192-kHz-Device Clock
Until 3 SP pu lses have passed
N
Figure 7
Initializing the PEx 2045 for a 4096-kHz-Device Clock
Until 3 SP pulses have pas
N
Siemens Components, Inc.
98
PES 2045
PEF2045
Operation with a 4096-kHz-Device Clock
In order for the MTSC to operate with a 4096-kHz-device clock the CPS-bit In the CFR
register needs to be reset. This has to be done before the CM reset and needs up to 1.8Ilsec.
Please keep in mind, MOD:RI has to be reset prior to performing an indirect register access.
For a flow chart of this process refer to figure 7.
Standby Mode
With MOD:SB being logical 1 the PEx 2045 works as a backup device in redundant systems.
It can be accessed via the IlP interface and works internally like an active device. However,
the outputs are high impedance. If the SB-bit is reset the outputs are switched to low
impedance for the programmed active channels and this MTSC can take over from another
device which has been recognized as being faulty. See figure 8.
Figure 8
Device Setup in Redundant Systems
P[M IN
n
r---
Data Bus
"
pP
WR
RD
AD
>----
'---
-
-J'\..
~
-----
~~ rsus
~
PEx 2045
Standby
r---
0
IData
IData
reus
Bus
WR
R
~
1h'E
I
rM-
rM-
~
Ii~==
~
~..Q._-
PEx 2045
Active
Decoder
[SO
CS 1
CS2
CSii
[51
L-
I
m~
~
U
P[M OUT
Siemens Components, Inc.
1[52
CS n
p.::-.:..:..--
~
99
~.
~
PEB 2045
PEF2045
Detailed Register Description
The following registers may be accessed:
Table 1
Addressing the Direct Registers
AddressAO
Write Operation
Read Operation
a
MOD
STA
1
IAR
IAR
The chapters in this section cover the registers in detail.
Mode Register (MOD)
Access: write on address
a
DB?
DBO
RC
TE
RI
SB
MI1
MIO
M01
MOO
Value after power up: FFH
RC:
Reset Connection memory; writing a zero to this bit causes the complete connection
memory to be overwritten with 200H (tristate). During this time STA:B is set. The
maximum time for resetting the connection memory is 250 I1s.
TE:
Tristate Enable; this bit determines which tristating scheme is activated:
TE = 1:
If the speech memory address written into the connection memory is
S8 - SO = 0, the output channel is tristated.
TE = 0:
The S9 bit written into the connection memory is interpreted as a validity
bit: S9 = 0 enables the programmed connection, S9 = 1 tristates the
output.
Note:
If TE = 1, time slot
switching.
a of
the logical input line 0 cannot be used for
RI:
Reset Indirect access mechanism; setting this bit resets the indirect access mechanism. RI has to be cleared before writing/reading IAR after reset.
SB:
Stand By; by selecting SB = 1 all outputs are tristated The connection memory
works normally. The PEx 2045 can be activated immediately by resetting SB.
M11/0:
M01/0:
Input/Output Operation Mode; these bits define M01/0 the bit rate of the input
and output lines. The bit rates are given in table 2, the corresponding pin functions
in table 3 (standard configuration) and table 4 (primary multiplex access configuration) ..
Siemens Components, Inc.
100
PEB 2045
PEF2045
Table 2
Input/Output Operating Modes
MI1
MID
M01
MOO
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
0
1
1
1
1
1
Output Mode
Input Mode
16x2
16x2
16x2
4x8
4x8
4x8
2x8/8x2
2x8/8x2
2x8/8x2
8x4
4x8
4x4/8x2
8x4
16x8
Mbitls
Mbitls
Mbitls
Mbitls
Mbitls
Mbitls
Mbitls
Mbitls
Mbitls
Mbitls
Mpitls
Mbitls
Mbitls
Mbitls
8x2
2x8
4x2/1 x8
8x2
2x8
4x2/1 x8
8x2
2x8
4x2/1 x8
4x4
4x4
4x2/2x4
2x8
2x8
Mbitls**
Mbitls
Mbitls
Mbitls
Mbitls
Mbitls
Mbitls
Mbitls
Mbitls**
Mbitls
Mbitls
Mbitls**
Mbitls
Mbitls*
unused
unused
0
0
* for space switch application only
** can also be used for primary access configuration
In the mixed modes the first bit rate refers to the odd line numbers, the second one to the
even line numbers.
Siemens Components, Inc.
101
PEB2045
PEF2045
Table 3
Input and Output Pin Arrangement for the Standard Configuration
Input Pin Arrangement
Pin No.
P-DIP Pl.-CC
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19 /
20
16x8 Mbitls
16x2 Mbitls
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
0
5
4
9
8
13
12
14
15
10
11
6
7
2
3
4x8
Mbitls
8x4
8x2+2x8
Mbitls
Mbitls
IN 0
Mbitls
IN 0
IN 4
IN 4
IN 8
IN 1
INO
IN2
IN3
8x2+4x4
IN 1
IN 12
IN 14
IN3
IN10
IN 1
INO
IN 5
IN 4
IN 6
IN 7
IN2
IN3
IN 1
IN 8
IN5
IN 12
IN 14
IN7
IN10
IN3
IN 6
IN 6
IN 2
IN 2
Note: The input line numbers shown are the logical line numbers to be used for programming the connection memory. In the case of 16 input lines the logical line numbers
are identical to the pin names.
Output Pin Arrangement
Pin No.
P-DIP Pl.-CC
32
33
34
35
36
37
38
39
35
36
37
38
40
41
42
43
8x2
2x8
Mbitls
Mbitls
OUT 7
OUT 6
OUT 5
OUT 4
OUT3
OUT 2
OUT 1
aUTO
4x4
4x2 + 1x8
Mbitls
Mbit/s
Mbitls
OUT 7
OUT 7
OUT 5
OUT 5
OUT 3
OUT 1
aUTO
4x2+2x4
OUT 1
aUTO
OUT 3
OUT 2
OUT 1
aUTO
OUT 3
OUT 2
OUT 1
Note: The logical output line numbers shown above are identical to the pin names.
Siemens Components,lnc.
102
OUT 1
PEB2045
PEF2045
Table 4
Input, Output and Tristate Pin Arrangement for the Primary Access Configuration
Pin No.
Pin·name
P·DIP
System
Interface Mode
PL·CC
2 MHz
4 MHz
8 MHz
5
TSCO
TSC1
TSCO
System interface
tristate control
signals, clock shift
programmable
TSCO
TSC1
TSC2
TSC3
4
6
8
10
10
12
TSCO
TSC1
TSC2
TSC3
OUT 0
OUT 2
OUT 4
OUT 6
39
37
35
33
43
41
38
36
OUT 0
OUT 1
OUT 2
OUT 3
OUT 0
OUT 1
OUT 0
System interface
outputs
clock shift
programmable
9
7
5
3
11
9
7
4
IN3
IN2
IN 1
INO
IN 1
INO
INO
System interface
inputs,
clock shift
programmable
OUT 1
OUT 3
OUT 5
OUT 7
38
36
34
32
42
40
37
35
OUT 0
OUT 1
OUT 2
OUT 3
OUT 0
OUT 1
OUT 2
OUT 3
OUT 0
OUT 1
OUT 2
OUT 3
Synchronous 2 MHz
interface
outputs
IN 14
IN 10
IN6
IN2
11
13
15
13
15
17
19
IN 3
IN2
IN 1
INO
IN3
IN 2
IN 1
INO
Synchronous 2 MHz
interface
inputs
17
3
2
1
0
0000
1111
1010
M11, Mia, M01, MOO
IN 13
IN9
IN5
IN 1
8
Mode
Note:
IN
IN
IN
IN
The input, output and tristate control line numbers shown in the center columns of
this table are logical line numbers. The corresponding pin names are listed in the
left most column.
Siemens Components, Inc.
103
PEB 2045
PEF2045
Status Register (STA)
Access: read at address 0
DB7
DBO
z
B
B
R
o
o
o
Busy: the chip is busy resetting the connection memory (B
after power up and logical 0 after the device initialization.
o
= 1)
o
B is undefined
Note: The maximum time for resetting the connection memory is 250 IJ.s.
Z
incomplete instruction; a three byte indirect instruction is not completed (Z = 1).
Z is 0 after power up.
Z is reset and the indirect access is cancelled by setting MOD:RI or
resetting MOD:RC
Note:
R
initialization Request. The conne.ction memory has to be reset due to loss of data
(R = 1). The R bit is set after power failure or inappropriate clocking and reset
when the connection memory reset is finished. R is undefined after power up and
logical 0 after the device initialization.
Siemens Components, Inc.
104
PEB 2045
PEF2045
Indirect Access Register (IAR)
(Read or Write Operation with Address AO = 1)
An indirect access is performed by reading/writing three consecutive bytes (first byte =
control byte, second byte = data byte, third byte = address byte) to/from IAR. The structure
is shown in table 5.
TableS
The 3 Bytes of the Indirect Access
Bit 7
Bit 0
0
0
K1
KO
0
0
C1
CO
Control Byte
07
06
05
04
03
02
01
00
Oata Byte
IA7
IA6
IA5
IA4
IA3
IA2
IA1
lAO
Address Byte
The control byte bits K1, KO, C1 and CO together with the address byte determine the type
of access being performed according to table 6.
Table 6
Encoding the Different Types of Indirect Accesses
K1
KO
C1
CO
Address Byte
0
1
0
0
0
09
09
09
08
08
08
CM-Address
CM-Address
CM-Address
Read
Write
Write
CM
CM
CM
1
1
1
1
1
1
1
1
0
0
1
0
1
FEH
FEH
FFH
FFH
Write
Read
Write
Read
CFR
CFR
CSR
CSR
1
Siemens Components, Inc.
0
0
0
105
Type of Access
PEB2045
PEF2045
Connection Memory Access
For a connection memory access the control byte bits C1 and CO contain the data bits 09
and 08, respectively. 09 is the validity bit which tqgether with 08 and the data byte 07-00
is written to the CM address IA7-IAO.
The function of the validity bit IS controlled by STA:TE. 08-00 and IA7-IAO contain the
information for the logical line and time-slot numbers of the programmed connection,
08-00 for the inputs, IA7-IAO for the outputs. Tables 7 through 11 show the programming
of these bits for the different configurations and modes.
Standard Configuration
Table 7
Time Slot and Line Programming for Standard Configuration
Standard Configuration, all Modes Except, Space Switch Mode
2 Mbitls input lines
Bit
Bit
Bit
03
08
09
to
to
DO
04
Logical line number
Time-slot number
Valididy bit
4 Mbitls input lines
Bit
Bit
Bit
02
08
09
to
to
DO
03
Logical line number
Time-slot number
Validity bit
8 Mbitls input lines
Bit
Bit
Bit
01
08
09
to
to
DO
02
Logical line number
Time-slot number
Validity bit
2 Mbitls output lines
Bit
Bit
IA2
IA7
to
to
lAO
lAO
Une number
Time-slot number
4 Mbitls output lines
Bit
Bit
IA1
IA7
to
to
lAO
IA2
Line number
Time-slot number
8 Mbitls output lines
Bit
Bit
lAO
IA7
to
IA1
Line number
time-slot number
Siemens Components, Inc.
106
PES 2045
PEF2045
Space Switch Mode
Table 8
Time Slot and Line Programming for Space Switch Mode
Space-Switch-Mode
(M11 = 1, MIO= 1; M01 = 0, MOO= 1)
8 Mbitls input lines
Bit
Bit
00
04
Bit
09
Bit
Bit
lAO
IA1
8 Mbitls output lines
to
to
03
08
to
IA7
Logical line number.
The lower 5 bits of
the time-slot number
Validity bit
Logical line number
Time-slot number
N is fixed to 70. The selection of one specific input time slot is possible by writing the
connection memory (CM) as shown below.
Table 9
Programming Input and Output Lines and Time Slots in Space Switch Mode
In CM address 00-3F:
In CM address 40-7F:
In CM address 80-BF:
In CM address CO-FF:
08-04
08-04
08-04
08-04
(SM
(SM
(SM
(SM
addr.)
addr.)
addr.)
addr.)
=
TSO -TS3
TS32 - TS63
TS6 - TS95
TS96 - TS127
In space switch mode the leading edge of the SP pulse must be applied with the first bit
of time slot 125. The input and output time-slot number must match.
Siemens Components, Inc.
107
PEB2045
PEF2045
Primary Access Configuration
Table 10
Time Slot and Line Programming for the Primary Access Configuration
2 MbiVs input lines
Bit
Bit
Bit
Bit
01
03
08
09
to
to
to
DO
02
04
Interface select in
line number
Time-slot number
Validity bit
4 MbiVs input lines
Bit
Bit
Bit
Bit
01
02
08
09
to
DO
to
03
Fixed to 01 (system interface)
Line numbers
Time-slot number
Validity bit
8 MbiVs input lines
Bit
Bit
Bit
01
08
09
to
to
DO
02
2 MbiVs output lines
Bit
Bit
Bit
lAO
IA2
IA7
to
to
IA1
IA3
Interface select out
Line number
Time-slot number
Bit
Bit
Bit
lAO
IA1
IA7
to
IA2
Fixed to 0 (system interface)
Line number
Time-slot number
Bit
Bit
lAO
IA7
to
IA1
Fixed to 0 (system interface)
Time-slot number
4 MiVs output lines
8 MbiVs output lines
Fixed to 01 (system interface)
Line number
Validity bit
The interface select bits have to be programmed as shown in the following table:
Table 11
Interface Selection Bits
input lines
output lines
Siemens Components, Inc.
System
Interface
.Synchronous
2 MHz Interface
01
10
0
1
108
PEB 2045
PEF2045
Configuration Register Access (CFR)
Access: read or write at indirect address FEH
For a read access the bit 0 of the control byte must be set to logical 1 and for a write access
to logical O.
Value after power up or software reset: FFH
DB7
DBO
1
CFS
CPS
CPS..
Clock Period Select: device clock is set to 8192 kHz (logical 1) or 4096 kHz
(logical 0)
CFS..
ConFiguration Select: The PEx 2045 works In either the primary access configuration (logical 0) or in standard configuration (logical 1). Setting this bit to
logical 1 resets the CSR to OOH'
Clock Shift Register Access (CSR)
Access: read or write at indirect address FEH
For a read access the bit 0 of the control byte has to be set to logical 1 and for a write access
to logical O.
The value after power up is OOH
DBO
DB7
RS2
RS1
RSO
RRE
XS2
XS1
XSO
XFE
RS2 .. RSO..
Receive clock Shift, bits 2-0. The received data stream is shifted in bit period
steps as shown in figure 9.
RRE...
Receive with Rising Edge. The data is sampled with the falling (RRE = 0) or
riSing edge (RRE = 1) of the data equivalent clock. (See figure 9).
XSO •. XS2..
Transmit clock Shift, bits 2-0. The transmitted data stream is shifted as shown
in figure 9.
XFE...
Transmit with Falling Edge; data is transmitted with the rising (XFE = 0) or
falling edge (XFE = 1) of the device clock.
Siemens Components, Inc.
109
PEB2045
PEF2045
Data stream manipulation according to these register entries only affects the system interface
and only in the primary access configuration. The frame structure can be moved relative
to the SP slope by up to seven clo~ periods in half clock period steps. This register can
hold non-zero values only for a CFR :CFS value of logical 0, Figure 9 illustrates the clock
shifting facility.
Identical non-zero entries for RS2-RSO and XS2-XSO as well as identical RRE and XFE
generate an output time-slot structure which is 1 time slot late relative to the input time-slot
structure.
Identical 000 entries RS2-RO and XS2-XSO as well as RRE and XFE being logical 0 cause
the input and output frames to coincide in time.
Figure 9
Clock Shifting
SP
ClK
~~I
TSO
CSR: 0000
____________~__T~S~O______~__________-+___
00'0
f ___________+--~~~O~----~----------~----~
-t~
________~--~T~S~O------+_----------_+-----TSO
--------r_--~------4_----------~--------
£ ______+_--~T~SO~----_+------------~--------
~----~Ir---T~S~O------~I------------~I----------
~ __~Ir_-~~O------~I~----------~I------------
TSO
0'00
o , '0
'000
'0'0
, , 00
", ,
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
XXXX
CSR: XXXX
0000
~---r------------r-------T~S~O--4-------------
XXXX
6 ____4_----------~------~T~S~0--+_----------
XXXX
" '0
, , 00
~'_u ______+_----------_+------~~--~--------
XXXX
'010
~o
~--------r-----------4-------~~~--------
XXXX
'000
£ ________~------------+_------~T~S~O--+_-----
XXXX
.¥!
~
~o
E
~-----------+------------+-------~~~o~~----
~ ____________~~----------+_------T~S~O--_+--
Siemens Components, Inc.
110
0' '0
XXXX 0' 00
XXXX 00' ,
PEB 2045
PEF2045
Absolute Maximum Ratings
Parameter
Symbol
Unit
Limit Values
Ambient temperature under bias PES 2045
TA
Oto 70
°C
Storage temperature PES 2045
Tstg
-65 to 125
°C
Ambient temperature under bias PEF 2045
TA
-40 to 85
°C
Storage temperature PEF 2045
Tstg
-65 to 125
°C
Voltage on any pin with respect to ground
Vs
-0.4 to Voo +0.4
V
DC Characteristics
Ambient temperature under bias range; Voo = 5 V
± 5%, Vss = 0 V.
Symbol
Limit Values
min.
max.
L-input voltage
IliL
-0.4
0.8
V
H-input voltage
IliH
2.0
Voo+0.4
V
0.45
V
IOL =
V
V
IOH
IOH
Parameter
Unit
Test Conditions
L-output voltage
VOL
H-output voltage
H-output voltage
VOH
VOH
Operational power supply current
Icc
10
mA
Voo=5 V,
inputs at 0 V or Voo ,
no output loads
Input leakage current
Output leakage current
ILl
10
!LA
OV---{ TS63,Bit6
----{ TSO,BitO } -
---{ TSO,Bit1
}--
E
.!
~ IN
t-
8 Mbit/s
50
.~{
§ ~ OUT
E.e
u ....
c
2 Mbit/s
Time Slot 31,Bit7
OUT
2 Mbit/s
TS31,Bit7
. .....
Vl':
t::>
.,u
........'"
0
OUT
2.: 4 Mbit/s
TSO,BitO
TS63,Bit6
TSO,Bit1
TS63,Bit6
TSO,Bit1
E
.!
~
Vl
OUT
8 Mbit/s
I~.,
....'"r...
TSC
2 Mbit/s
u
J!!
.:
TSC
4 Mbit/s
E
.!
.
Vl
TSC
8 Mbit/s
Siemens Components. Inc,
116
}
PEB 2045
PEF 2045
Figure 15
PCM Line Timing in Standard Configuration with a 4-MHz-Device Clock
510
o
511
ClK
SP
IN 2 Mbit/s
~-------~-o
----
OUT 2Mbit/s
Time Slot 0, BitO
--~ ~Nr--~--~---
IN 4 Mbit/s
our 4Mbit/s
~
TS63,Bit6
Siemens Components, Inc.
Xr--
to.t=
X
TS- 6-3,-Bi-t7---L-r-s-0,-B,-tO-.....
117
rs 0,Bit1
PEB 2045
PEF2045
Figure 16
PCM Line Timing in Primary Access Configuration with a 4-MHz-Device Clock and a
CSR Entry (00010001)
I
~
~
0
ClK
SP
i
VI
oS~{
u
c:
..C>..C>..a..C>..a..C>..a.VI
SIP2
SIP6
SIP1
SIP7
SIPO
Q:
Q:
VI VI VI VI VI VI VI VI
Q:
6 5 4 3 2 1 44 43 42 41 40
TxHW01
f5Yi
o
39
TxHWOO
RxHWO 1
RESET
RxHWOO
ill
TxHWO 1
N.L
TSC 1
N.C.
Tx HWOO
WR
TSCO
VOD
T5TIl
Syp
SClK
SIGS
OIR
PEB 2052
N.C.
N.c.
N.C
18 19 20 21 22 23 24 25 26 27 28
PEB 2052
SYP
07
SClK
06
SIGS
05
OIR
04
N.C
03
N[
02
V DD
01
l$
DO
ALE
RO
Vss
Siemens Components, Inc.
ClK
155
fNi'
VDD
N.C.
36
35
34
33
32
31
30
29
WR
1'00
07
06
05
04
03
02
PEB2052
Pin Definitions and Functions
Pin No.
PL-CC
Pin No. Symbol
P-DIP
Name
Function
Subscriber
interface port
(inpuVoutput)
These interface ports are used for bidirectional, bit-serial transfer of speech,
data and control words to and from
the signal processing codec filter
(SICOFI) or standard codec. Corresponding with the direction signal, the
PIC PES 2052 is transmitting during
the high level of DIR within the first half
of a 125 j..I.s frame.
Receive highway
data (input)
Receive highway
data (input)
Receive PCM highway 1 interface.
1
1
SIP4
4
4
SIP 7
5
5
RxHWD1
6
6
RxHWDO
7
7
TxHWD 1
Transmit highway
data (output)
Output of the transmit side onto the
send PCM highway 1 (serial bus). The
8-bit PCM word is serially sent out on
this pin at the programmed time slot.
Tristate output.
8
8
TSC 1
Tristate control
(output, active low)
Normally high, this signal goes low
while the PIC is transmitting an 8-bit
PCM word on the PCM highway 1.
9
9
TxHWDO
Transmit highway
data (output)
Output of the transmit side onto the
send PCM highway O.
10
10
TSCO
Tristate control
(output, active low)
Tristate control of highway O.
11
11
SYP
Synchronization
SYP is a frame synchronization pulse
which resets the on-chip time-slot
counters.
12
12
SCLK
Slave clock
(output)
C.lock output for the peripheral devices.
The signals between the codec filter
and the PIC are latched and transmitted
with the rising edge of SCLK.
13
13
SIGS
Signal strobe
(output, active
high)
The SIGS output supplies a programmabie strobe signal.
Siemens Components, Inc.
156
Receive PCM highway 0 interface.
The PIC serially receives a PCM word
(8 bits) through one of these leads at
the programmed time slot.
PEB 2052
Pin Definitions and Functions (confd)
Pin No.
Pin No. Symbol
P-DIP
Name
Function
PL-CC
14
14
DIR
Direction
(output, active
high)
DIR is an 8-kHz-symmetric frame signal
which controls the direction of data
transfer from and to the peripheral
devices. The PIC is able to receive data
during the low state of DIR.
15
15
N.C.
Not connected
16
16
N.C.
Not connected
38
17
Voo
Power supply: Voo = 5.0 V± 0.25 V
19
18
CS
Chip select
(input, active low)
CS is used to address the PIC. A low
level at this input enables the PIC to
accept commands or data from a IlP
within a write cycle, or to transmit data
during a read cycle.
20
19
ALE
Address latch
enable (input,
active high)
A high level at this input indicates that
the data on the external bus is an
address selecting one of the PIC-internal sources or destinations. Latching
into the address latch occurs during
the high-low transition.
22,23
20
Vss
25
21
CLK
Clock
(input)
A standard TTL clock provides the
basic timing of the controller. The clock
is synchronous to the PCM clock.
26
22
RD
Read strobe
(input, active low)
RD is used together with CS to transfer
data from the PBC to a IlP or memory.
27
23
DO
System data bus
The data bus transfers data and commands between the IlP or memory and
the PIC.
34
30
D7
35
31
Voo
Siemens Components, Inc.
Ground (0 V)
Power supply: Voo = 5.0 ± 0.25 V
157
PEB 2052
Pin Definitions and Functions (cont'd)
Pin No.
PL-CC
Pin No. Symbol
P-DIP
Name
Function
36
32
WR
Write strobe
(input, active low)
During the low state of WR data can
be transferred from ltle IlP or memory
to the PBC.
37
33
34
N.C.
N.C.
39
35
INT
Interrupt
request (output,
active low)
The signal is pulled down, when the
PIC is requesting an interrupt. In that
case, the IlP should enter an interrupt
routine for reading status register 1.
40
36
RESET
Reset (input,
active hogh)
A high on this input forces the PIC
into reset state. The minimum reset
pulse is 16 complete clock cycles.
41
37
SIP 0
Not connected
Not connected
Subscriber
interface port
(input/output)
44
40
SIP3
Siemens Components, Inc.
158
These interface ports are used for bidirectional, bit-serial transfer of speech,
data and control words to and from
the Signal Processing Filter (SICOFI)
or standard codec. Corresponding
with the direction signal, the PIC
PEB 2052 is transmitting during the
high level of DIR within the first half of a
125 Ils frame.
PES 2052
Block Diagram
SIP 0
--;I
SIP 7
OIR
SIGS
SClK
SYP
ClK
RESET
-----------I
I
I
/'
Subscriber
Interface Unit
A
~""
....
v
;".It
J\.
....
v
r--
PCM
Interface Unit
I--
_t
Timing
Control Unit
.It
~
....
v
~ PCM
~ Highways
I.. •
Bus Interface
Control Unit
t
Special Purpose
Registers
...
.It
TSA Module
v
--Vee
--GNO
Bus Interface
Registers
FC FIFO
CPU Bus
(S
Siemens Components, Inc.
ALE
159
RO
WR
INT 00-07 OMIR OMOR
PEB2052
Description of the Functional Blocks
The PIC has been designed especially for use in peripheral subscriber boards, but its
functional flexibility also permits its application in various parts of a digital exchange telecommunications system.
Used in peripheral subscriber boards it performs two essential functions:
1) Exchange of control data between an on-board processing unit and individual subscriber
connections.
2) The time-slot controlled transfer of PCM data (64-Kbaud channels) between the PCM
highways and the subscriber connections. Data transfers between both parts, such as
the access of the on-board f.LP to 64-Kbaud channels, are considerably simplified
by the IC.
The PIC Consists of the Following Functional Blocks
• Subscriber Interface Unit
• PCM Interface Unit
• TSA Module (Contents-Addressable Memory)
• Timing Control Unit
• f.LP Interface
• f.LP Control and Status Register
• Feature Control FIFO (16 byte)
• Bus Interface Register
Siemens Components, Inc.
160
PEB 2052
Maximum Ratings
Limit Values
Parameter
Symbol
min.
Storage temperature
Tstg
-65
TA
0
Voltage at any pin referred to ground
Vs
-0.5
Total power consumption
Ptot
I max.
Unit
I 125
°C
70
°C
7
V
35
mW
Range of Operation
Operating temperature
DC Characteristics
TA = 0 to 70°C; Vee = 5 V ± 0.25 V; GND = 0 V
Limit Values
Parameter
typo
Symbol
min.
max.
Unit
0.8
V
5.5
V
0.45
V
IliL
-0.5
H-input voltage
IliH
2.0
L-outplit voltage
IOL = +1.6 rnA
VOL
H-output voltage
I oH =-400j.LA
VOH
2.4
Input leakage current
IliN= Vee toOV
IlL
-10
10
j.LA
Output leakage current
VOUT = Vee to 0 V
IOL
-10
10
j.LA
Vee supply current
Vee=5 V
Icc
7
rnA
typo
max.
Unit
10
pF
L-input voltage
V
capacitance
TA = 25°C; Vee = GND= 0 V
Limit Values
Parameter
Symbol
min.
Input capacitance
fe= 1 MHz
CIN
5
InpuVoutput capacitance
CliO
10
20
pF
Output capacitance
unmeasured pins
returned to GND
COUT
8
15
pF
Siemens Components, Inc.
161
PEB 2052
AC Characteristics
TA = 0 to 70 DC; Vcc = 5 V ± 0.25 V; GND = 0 V
Microprocessor Interface
Read Cycle
Limit Values
Parameter
Symbol
Address hold after ALE
tLA
20
ns
Address to ALE setup
tAL
30
ns
Data delay from RD
t RO
AD pulse width
tRR
Output float delay
tOF
RD control interval
tRI
ALE pulse width
min.
max.
120
120
Unit
ns
ns
25
ns
ns
tAA
80
60
WR pulse width
tww
100
ns
50
25
50
ns
ns
Write cycle
Data setup to WR
tow
Data hold after WR
two
WR control interval
tWI
ns
ns
Read Cycle
ALE
t-----tRi-------l
DB
Write Cycle
DB
---fWi------t-~U,..----
---------------
__-
-""".~-,...,._-_-_-_-_-_-_-_-_-_-_-_--vo;;;;;-v-_________________
_l"lIO-_-T'-
Siemens Components, Inc.
~
162
PES 2052
Clock Timing
Limit Values
Parameter
min.
max.
Unit
4.2
MHz
40
125
60
Nx 125
%
60
10
50
tClK
ns
512
512
150
kHz
150
110
ns
System Clock
System clock frequency
fClK
Duty cycle
Sync pulse period
tspp
Sync pulse width
tSYp
Pulse delay to ClK
tdSYP
Setup time to ClK
tsSYP
j.Ls
ns
ns
Slave Clock
Clock frequency
Clock delay time
ns
DIR Clock
Delay time to ClK (rising edge)
Delay time to ClK (falling edge)
ns
SIU Interface
SIP data delay
200
120
120
t dSIP
ns
Data enable receive
tOER
Data disable receive
tOOR
Data enable transmit
tOEX
tOHX
0
0
ns
Data hold transmit
Data setup transmit (control data)
tosx
CP/2+200
ns
Data setup transmit
tosx
100
Signaling strobe delay (falling edge)
tOSIG F
Signaling strobe delay (rising edge)
tOSIG R
Siemens Components, Inc.
163
ns
ns
ns
ns
150
150
ns
ns
PEB2052
SIP Interface Timing
'._._.-'I
.
Detail B
Detail A
Syp
I
ClK
SClK
DlR
SIP IN
i
-t-
SIP OUT-------------
L._._..J
Detail B
Siemens Components, Inc.
164
I
PEB 2052
Serial Port Timing
PCM Interface
Parameter
I Symbol
Limit Values
max.
min.
Unit
Receive Timing
Receive data setup OCR = 1
tOSRF
20
ns
Receive data setup OCR = 0
tos RR
40
ns
Receive data hold DCR=1
tOH RF
40
ns
tOH RR
10
ns
Receive data hold DCR=O
Receive Timing
~CLK
RxHWO
OCR =1
RxHWO
OCR= 0
PCM Interface (confd)
Parameter
Test Conditions
Transmit Timing
Data enable DCX = 0
tOZXR
160
ns
C L =200 pF
Data enable DCX = 1
tOZXF
100
ns
C L =200 pF
Data hold time DCX = 0
tOHXR
160
ns
C L =200 pF
Data hold time DCX = 1
tOHxF
100
ns
C L = 200 pF
Data float on T8 EXIT
tHZX
80
ns
C L =150pF
Time slot x to enable DCX = 0
tSONR
130
ns
C L = 150 pF
Time slot x to enable DCX = 1
tSONF
100
ns
C L = 150 pF
Time slot x to disable
tSOFF
100
ns
C L = 150 pF
Siemens Components, Inc.
165
PEB 2052
Transmit Timing
\
-.-I
-
\
I
elK
TxHWO
K
tOZXR
I--
oex= 0
- - tOHXRI--
K:
1.
--
tOZXF
---
TxHWO
oex= 1
--- t OHXF I---
Tse
oex =0
--
tSONR
L
Tse
___ t
SONF
oex=1
~
AC Testing Input, Output Waveform
AC Testing Load Circuit
2.4
2.0"
Oevice
Under
Test
2.0
Test POints/
0.8 /
"O.S
0.45
AC testing: inputs are driven at 2.4 V for a logic "1" and at 0.45 V for a logic "0".
Timing measurements are made at 2.0 V for a logic "1" and at 0.8 V for a logic "0".
Siemens Components, Inc.
166
SIEMENS
Signal Processing Codec Filter (SICOR)
Preliminary Data
PEB2060
CMOSIC
Type
Ordering Code
Package
PEB 2060-P
PEB2060-N
067100-Z170
067100-Z8393
P-DIP-22
PL-CC-28 (SMO)
The Signal Processing Codec Filter (SICOFI ®) PEB 2060 is a fully integrated PCM codec
(coder/decoder) and transmit/receive filter fabricated in advanced CMOS technology for
applications in digital telecommunication systems. Based on a digital filter concept, the
PEB 2060 provides improved transmission performance and high flexibility. The digital signal
processing approach supports software controlled adjustment of the analog behavior,
including attractive features such as programmable transhybrid balancing, impedance
matching, gain and frequency response correction.
Features
•
•
•
•
Single chip codec and filter
Band limitation according to CCITI and AT& T recommendations
Digital Signal Processing techniques
Digital voice transmission
- PCM encoded (A-law or j.L-law)
- linear (16 bit 2s complement)
• Programmable digital filters for
- impedance matching
- transhybrid balancing
- gain
- frequency response correction
• Configurable three pin serial interface
- 512-kHz-SLD-Bus (e.g. to PEB 2050/51)
- burst mode with bit rates up to 8 MHz
• Programmable signaling interface to peripherals (e.g. SLlC)
• High performance AID and D/A conversion
• Programmable analog gain
• Advanced test capabilities
- three digital loop back modes
- two analog loop back modes
- on chip sine wave generation
• No trimming or adjustments
• No external components
• Variable SICOFI Master Clock selection
• Signaling expansion possible
• Prepared for three-party conferencing
• Advanced low power 2 j.LCMOS technology
• Power supply +/-5 V
167
PES 2060
Pin Configuration
(top view)
PL-CC-28
P-DIP-22
I-
voo
VIN
VOUT
SI3
GNDA
SI2
Vss
SI1
GNDD
TEST
SO 3
SIP
502
SA
SO 1
SB
RS
SC
DIR
SD
?LL
SCLK
Siemens Components, Inc.
g
u
c
z,.."
>:ZS'>Vl
3 2 1 28 27
N.C
GNDA
Vss
GNDD
S03
S02
S01
N.L
RS
26 SI2
25 N.C.
SI1
TEST
PEP 2060
NL
SIP
SA
SB
SC
0
O:::--'u~o
~~zLjVJ
VI
168
PEB2060
Pin Definitions and Functions
PinNa.
P-DIP
PinNa.
PL-CC
Symbol Input (I)
Output (0)
Function
1
4
1
6
Voo
Vss
I
I
Power supply +5 V
Power supply -5 V
3
5
GNDA
I
5
7
GNDD
I
Ground analog, not internally connected to GNDD.
All analog signals are referred to this pin.
Ground digital, not internally connected to GNDA.
All digital signals are referred to this pin.
22
2
28
3
VIN
VOUT
I
0
Analog voice input to transmit path.
Analog voice output of the received digital voice.
12
10
17
16
13
21
SCLK
DIR
SIP
I
I
I/O
Slave clock.
Frame synchronisation signal (direction signal).
Serial Interface Port, bidirectional serial data port.
9
12
RS
I
18
11
23
14
TEST
PLL
I
I
Reset input, active high, RS forces the SICOFI to
power down mode and resets the configuration
registers.
Test input, normally connected to GNDD.
Master clock selection (PLL/external clock).
19
20
21
24
26
27
SI1
SI2
SI3
I
I
I
Signaling Inputs. Data present at SI is sampled
and transmitted via the serial interface.
8
7
6
10
9
8
S01
S02
S03
0
0
0
Signaling Outputs. Data received via the serial
interface is latched and fed to these outputs.
16
15
14
13
20
19
18
17
SA
S8
SC
SO
I/O
I/O
I/O
I/O
Programmable I/O signaling pins. Each ofthese
pins may be declared input or output individually
with adequate SICOFI status settings. If 2
SICOFls are connected to 1 serial interface,
pin SA (highllow) assigns voice, control and
signaling bytes.
Siemens Components, Inc.
169
PEB2060
SICOFI Principles
The SICOFI codec filter solution is a highly digital approach utilizing the advantages of
digital signal processing such as excellent performance, high flexibility, easy testing, no
sensitivity to fabrication and temperature variations, no problems with crosstalk and power
supply rejection.
Figure 1
SICOFI Signal Flow Graph
SIP
DIR
SCLK
Transmit Direction
The analog input signal is AID converted, digitally filtered and transmitted either PCMencoded or linear. Antialiasing is done with a 2nd order Sallen-Key prefilter (PREFI). The
AID Converter (ADC) is a modified slopeadaptive interpolative sigma-delta modulator with a
sampling rate of 128 kHz. Digital downsampling to 8 kHz is done by subsequent decimation
filters D1 and D2 together with the PCM bandpass filter (BP).
Receive Direction
The digital input signal is received PCM-encoded or linear, digitally filtered and D/A converted to generate the ananlog output signal. Digital interpolation up to 128 kHz is done by
the PCM lowpass filter (LP) and the interpolation filters 11 and 12. The DIA Converter (DAC)
output is fed to the 2nd order Sallen-Key postfilter (POSI).
Programmable Functions
The high flexibility of the SICOFI is based on a variety of user programmable filters, which
are analog gain adjustment AGR and AGX, digital gain adjustment GR and GX, frequency
response adjustment R and X, impedance matching filter Z and the transhybrid balancing
filter B.
Siemens Components, Inc.
170
PEB 2060
Figure 2
SICOFI Block Diagram
Signaling
SA .. SO
SI
SO
OIR
Interface
S[LK
SIP
S
L
0
B
U
S
DSP
(oeff.
RAM
The SICOFI bridges the gap between analog and digital voice signal transmission in modern
telecommunication system.
High performance oversampling analog-to-digital converter (ADC) and digital-to-analog
converter (DAC) provide the conversion accuracy required. An analog antialiasing prefilter
(PREFI) and smoothing postfilter (POFI) is included. The dedicated on chip digital signal
processor (DSP) handles all the algorithms necessary, e.g. PCM bandpass filtering, sample
rate conversion and PCM companding. The three pin serial SLD-Bus interface handles
digital voice transmission and SICOFI feature control. Specific filter programming is done
by downloading coefficients to the coefficient ram (CRAM).
The ten pin parallel signaling interface provides for a powerful per line SLiC control.
Siemens Components, Inc.
171
PEB2060
Serial Interface
The exchange of data on the SLD-Bus is based on a bidirectional, bitserial interface consisting of three pins: SIP, DIR and SCLK.
Data is written or read out on the Serial Interface Port (SIP) under control of the frame
synchronisation signal DIR with a period of 125I-1s*). The interface clock frequency supplied
at the Slave CLocK pin SCLK is 512 kHz*). The rate of the serial data stream on the SIP
pin is 512 kbiVs, that is 64 bits per each 8 kHz frame*).
Starting with the riSing edge DIR, four bytes of information are transfered on the SLD-Bus
to the SICOFI, followed by four bytes from the SICOFI to the SLD-Bus.
Bit 7 is the first bit transfered and bit 0 is the last one of each byte.
Figure 3
Byte Sequence and Timing at Serial Interface Port SIP
Receive
DIR
Transmit
PBC --SICOFI®
SICOFI®--PBC
.1,..--""\ r - - " " \ r - - " " \ r - - " " \ r - - " " \ r - - " " \ r - - " " \ r _ _-,.I/ LlO
SIP ChannelA
00
SIP Channel A
SIP
01
Linear Voice
Linear Voice
10
~----------------------1~~s----------------------~
LlO: Field LlO (Linear Operating Mode)
DIR
inCR3
SCLK
J
X,-__B_it_63___XBit 62
SIP X,--_B_it_OO___
*) for applications with other clock rates see appendix A
Siemens Components, Inc.
172
PEB 2060
Programming
A message-orientated byte transfer is used, due to the fact that the SICOFI needs extended
control information. One control byte per frame and direction is transfered. With the appropriate received commands, data can be written to the SICOFI or read from the SICOFI
onto the SLO-bus.
Data transfer to the SICOFI starts with a write command, followed by up to 8 bytes of data.
The SICOFI responds to a read command with the requested information, starting at the
next transmission period. If no status modification or data exchange is required a NOP byte
is transfered (see Programming Procedure).
Classes of Control Bytes
The 8-bit control bytes consist of either commands, status information or data. There are
three different classes of SICOFI commands:
NOP
NO OPERATION:
no status modification or data exchange
SOP
STATUS OPERATION:
SICOFI status setting/monitoring
COP
COEFFICIENT OPERATION:
filter coefficient setting/monitoring
The class of command is selected by bit 2 and 3 of the control byte as shown below.
Due to the extended SICOFI feature control facilities, SOP- and COP-commands contain
additional information.
7
BIT
5
6
4
3
2
o
x
o
o
NOP
SOP
COP
NOPCommand
If no status modification of the SICOFI or control data exchange is required, a No Operation
Byte NOP is transfered.
SIT
7
6
5
4
x .... don't care
Siemens Components, Inc.
173
3
2
0
PEB 2060
SOP Command
To modify or evaluate the SICOFI status, the contents of up to four configuration registers
CR1, CR2, CR3 and CR4 may be transfered to or from the SICOFI. This is done by a
SOP-Command (Status Operation Command).
BIT
7
6
5
4
3
2
0
I
AD
RIW
PU
TR
0
LSEL
I
AD
Address Information
AD=O
A-SICOFI addressed
AD=1
B-SICOFI addressed
This bit is evaluated if two SICOFls are connected to one SLD-port.
A SICOFI is accessed, if AD is consistent with the level at pin SA
(see Signaling Byte, Programming Procedure).
R/W
ReadIWrite Information
PU
Power Up/Power Down
(see also CR3)
TR
Three Party Conference TR = 1
LSEL
Length Select Information (see also Programming Procedure)
This two bit field identifies the number of subsequent data bytes
LSEL = 0 0 no byte following
LSEL = 1 1 CR1 is following
LSEL = 1 0 CR2 and CR1 are following
LSEL = 0 1 CR4, CR3, CR2 and CR1 are following
in this case the PU and TR bits are not
overwritten.
R/W = 0
Write to SICOFI
R/W = 1
Read from SICOFI
Enables reading from the SICOFI or writing information to the SICOFI.
Siemens Components, Inc.
PU = 1
PU = 0
Sets the SICOFI to power-up mode (operating)
Resets the SICOFI to power-down
(standby mode)
The received voice bytes of Chanr:lel A and
Channel B are added (A+B). The result is
filtered, 0/A converted and transfered to
Analog Output VOUT (see also CR3).
174
PES 2060
CR1
Configuration Register 1
This configuration register is used for enabling/disabling the programmable digital filters
(DB .. RG) and for accessing tesmodes (TM1).
BIT
7
6
5
4
3
DB
RZ
RX
RR
RG
DB
Disable B-Filter
DB
DB
RZ
Restore Z-Filter
RZ
RZ
RX
Restore X-Filter
RX
RX
RR
Restore R-Filter
RR
RR
RG
Restore GX-GR - Filter
RG
RG
TM1
o
2
TM1
= 0 : B - Filter enabled
= 1 : B-Filter disabled
= 0: Z-Filter disabled
= 1 : Z-Filter enabled
= 0: X-Filter disabled
= 1 : X-Filter enabled
= 0: R-Filter disabled
= 1 : R - Filter enabled
= 0: GX-GR-Filter disabled
= 1 : GX-GR-Filter enabled
TESTMODES
0
0
0
No test mode
0
0
1
Analog loop back via Z-filter (H (Z) = 1) 1)
0
1
0
Disable highpass filter (part of bandpass BP)
0
1
1
Cut off receive path
1
0
0
Initialize data ram
1
1
0
Digital loop back via B-filter (H (B) = 1)2)
1
1
1
Digital loop back via PCM-register3)
1)
2)
3)
Output of the interpolation filter 1 11 is set to O.
Value of transfer function of the Z-filter is 1 (not programmable).
Output of the low pass decimation filter 2 D2 is set to O.
Value of transfer function of the B-filter is 1 (not programmable).
PCM in = PCM out. This testmode is also available in standby mode.
Siemens Components, Inc.
175
PEB 2060
CR2
Configuration Register 2
BIT
7
6
5
4
3
2
D
C
B
A
EL
AM
o
IJ./A
PCS
The first four bits D ... A in this register, program the four bidirectional signaling pins SD ... SA.
With two SICOFls on one SLD port only pin SD can be used, pin SA is always input in this
case and indicates the address of the SICOFI.
SA = 0: A-SICOFI, SA = 1 : B-SICOFI (see also bit AD in SOP-command).
D
Signaling Pin SD
D=O
D=1
C
Signaling Pin SC
C=O
C=1
SD is output
SD is input
SC is output
SC is input
B
Signaling Pin SB
B=O
B=1
SB is output
SB is input
A
Signaling Pin SA
A=O
A=1
SA is output
SA is input
EL
Signaling Expansion Logic
EL=O
EL= 1
No expansion logic
Expansion logic provided
signaling expansion logic is only possible with one SICOFI on port
(see also Signaling Byte)
AM
Address Mode
AM = 0
Two SICOFls on SLD port
AM = 1
One SICOFI on SLD port
The SICOFI access to the SLD-Bus voice channel is controlled by AM and TR.
Receive (SLD-Bus-SICOA)
AM TR
SICOFIA
SICOFI B
SICOFIA
SICOFI B
0
0
channel A
channelB
channel A
channelB
0
1
channelB
channel A
channelB
channel A
1
0
channel A
channel A, B1)
1
1
channel A + B2)
-
-
channel A, B1)
IJ./A= 0
IJ./A= 1
Programmed B-Filter Coefficient
PCS=O
PCS=1
PCM-Law
PCS
Transmit (SICOFI-SLD-Bus)
A-Law
IJ. - Law (1J.255 PCM)
Programmed coefficients
Fixed coefficients
1) The SICOFI transmits the same byte in channel A and B.
2) Three Party Conference.
Siemens Components, Inc.
176
PEB 2060
CR3
Configuration Register 3
BIT
7
6
AGX
AGX
AGX
AGX
AGX
AGR
3
2
PU
TR
=
=
=
=
0
0
o dB
0
1
6 dB amplification
0
12 dB amplification
14 dB amplification
Analog Gain Control Receive-Path
AGR
AGR
=
=
0
0
OdB
0
1
6 dB attenuation
0
12 dB attenuation
AGR
AGR
PU
4
Analog Gain Control Transmit-Path
AGX
AGR
5
=
14 dB attenuation
Power Up/Power Down1)
PU
0
Power Down (standby)
PU
Power Up (operating)
TR
Three Party Conference/Reverse Operating Mode (see CR2)1)
LlO
Linear Operating Mode (see serial interface)
LlO
= 0
LlO
= 0
LlO
=
0
PCMmode
Linear mode 12)
o
Linear mode 2
(Change of linear mode becomes valid in the next DIR-cycle).
1)
2)
The bits PU and TR may also be overwritten by a SOP command with
LSEL = 0 1 (PU and TR are part of the SOP command).
With LSEL = 0 1, the bits PU and TR in the SOP command are ignored.
Subsequent to a SOP/COP-read command the control and signaling information
is transmitted instead of linear voice.
Siemens Components, Inc.
177
o
PEB 2060
CR4
Configuration Register 4
BIT
6
7
5
TM3
0
0
0
0
1
0
3
o
o
o
2
TM4
TEST MODES
TM3
0
4
No test mode
0
Additional
+ 6 dB digital gain in transmit direction (GX)
i
Additional + 12 dB digital gain in transmit direction (GX)
0
Enable on chip sine wave generation1)
0
Far analog loop back21
TM4
TEST MODES
0
0
0
No test mode
1
0
0
Digital loop back via analog port (YIN = VOUT )
COP Command
With a COP command coefficients for the programmable filters can be written to the
SICOFI coefficient ram or transmitted on the SLD-bus for verification.
BIT
7
6
AD
RIW
5
4
3
2
o
: CODE:
A-SICOFI addressed
AD=O
B:'SICOFI addressed
AD=1
This bit is evaluated with two SICOFls on one SLD-port only.
With two SICOFls on port, a SICOFI is identified, if AD is consistent with the level
at pin SA (see Signaling Byte, Programming Procedure).
AD
Address Information
R/W
Write to SICOFI
RIW = 0
Read from SICOFI
RIW=1
This bit indicates whether filter coefficients are written to the SICOFI or read from
the SICOFI.
1)
2)
ReadIWrite Information
With the R-Filter disabled a 2 kHz, 0 dBmO sine wave signal is fed to the input of the
receive Lowpass Filter LP (other frequencies see Appendix B).
The output of the X-Filter is fed to the input of the R-Filter (8 kHz, 16 bit linear).
Siemens Components, Inc.
178
PEB 2060
CODE
0
0
0
0
1
1
B-Filter coefficients part 1
(followed by 8 bytes of data)
0
0
1
0
1
1
B-Filter coefficients part 2
(followed by 8 bytes of data)
0
1
0
0
1
1
Z-Filter coefficients
(followed by 8 bytes of data)
0
1
1
0
0
0
B-Filter delay coefficients
(followed by 4 bytes of data)
1
0
0
0
1
1
X-Filter coefficients
(followed by 8 bytes of data)
1
0
1
0
1
1
R-Filter coefficients
(followed by 8 bytes of data)
1
1
0
0
0
0
GX- and GR-Filter coefficients (followed by 4 bytes of data)
Other codes are reserved for future use.
Data Byte Format
BIT
7
6
5
4
~XPONEN1
SIGN
3
2
1
0
~XPONEN1
SIGN
COEFFICIENT 2
COEFFICIENT 1
Each four bit coefficient represents a factor of SIGNx2-EXPONENT
Subsequent to reading the filter coefficients form the SICOFI CR2 and CR1 are transmitted
additionally! !
Siemens Components, Inc.
179
PEB 2060
Signaling Byte
The signaling interface of the SICOFI consists of 10 pins.
3 transmit signaling inputs: S11, SI2 and SI3
3 receive signaling outputs: S01, S02 and S03
4 bidirectional programmable signaling pins: SA, SB, SC and SO
Data present at SI1 .. SI3 and possibly at some or all of SA .. SO (if programmed as inputs)
are sampled and transfered serially on SIP onto the SLO-bus. Data received serially on
SIP from the SLO-Bus are latched and fed to S01 .. S03 and possibly to some of SA .. SO
if programmed as output.
The signaling field format is generally:
In Receive Direction:
BIT
6
5
4
3
2
S02
S03
SO
SC
SB
7
I
S01
I
0
SEL
SA
In Transmit Direction:
BIT
7
6
5
4
3
2
SI1
SI2
SI3
SO
SC
SB
0
SA
SEL
where SEL is the signaling expansion bit if EL ::::; 1 in CR2.
For the different cases possible, the signaling byte format at SIP is
Receive Signaling Byte
Transmit Signaling Byte
7
6
4
3
2
1
0
7
6
S01
S02 S03 X
X
X
X
X
SI1
2
S01
S02 S03 X
X
X
X
X
3
S01
S02 S03 SO
SC
S8
SA
4
S01
S02 S03 SO
SC
S8
5 A-SIC
S01
S02 S03 X
X
X
X
X
S01
S01
802 S03 SO
X
X
X
S01
S02 S03 SO
Bit
1 Case
8-SIC
6 A-SIC
8-SIC
5
X
X
X
X
3
2
1
0
SI2 SI3 SO
SC
S8
SA
0
SI1
SI2 SI3 SO
SC
S8
SA
Z
X
SI1
SI2 SI3 0
0
0
0
0
SA
X
SI1
SI2 SI3 Z
Z
Z
Z
Z
X
X
SI1
SI2 SI3 SO
Z
Z
Z
Z
S02 803 X
Z
Z
811
812 SI3 SO
X
SI1
SI2 SI3 0
Z
Z
Z
Z
SI1
SI2 SI3 0
X
Z ... high impedance, X ... don't care
Siemens Components, Inc.
180
X
5
Z
Z
4
Z
Z
Z
Z
PEB 2060
Signaling Byte
cases
One SICOFI is connected to one SLO port, EL = a (no signaling expansion logic
provided); SA .. SO are programmed as transmit signaling inputs.
2 One SICOFI connected to one SLO port, EL = 1 (signaling expansion logic provided);
SA .. SO are programmed as transmit signaling inputs.
3 One SICOFI is connected to one SLO port; EL = a (no signaling expansion logic
provided); SA .. SO are programmed as receive signaling outputs.
4 One SICOFI is connected to one SLO port; EL = 1 (signaling expansion logic provided);
SA .. SO are programmed as receive signaling outputs.
If a signaling expansion logic is provided (see case 2 and 4), the signaling bits SA .. SO
which are programmed as signaling inputs or outputs can be used as additional
expansion bits in receive or transmit direction, respectively. As far as SICOFI is concerned, SIP is in a high-impedance (Z) state or "don't care" (Y) state while these bits
are transfered.
5 Two SICOFls are connected to one SLO port; SO is programmed as transmit signaling
input.
6 Two SICOFls are connected to one SLO port; SO is programmed as receive signaling
output.
If two SICOFls are connected to one SLO port, no signaling expansion logic is possible.
SA is programmed as input automatically, and defines the addressed SICOFI:
SA = :A-SICOFI
SA = 1 : 8-SICOFI.
a
S8 and SC are not usable with two SICOFls on one SLO port.
Siemens Components, Inc.
181
PEB 2060
Programming Procedure
The following table shows some control byte sequences. If the SICOFI has to be configured completly during initialization, up to 60 bytes will be transfered.
No Operation
I NOP I NOP I NOP I NOP I NOP I NOP I NOP I NOP I NOP I NOP I NOP
SOP Write
SOP
SOP
SOP
SOP
NOP
NOP
NOP
NOP
CR1
CR2
CR4
NOP
NOP
NOP
CR1
CR3
NOP
NOP
CR2
NOP
SOP
SOP
SOP
SOP
NOP
CR1
CR2
CR4
X
X
CR1
CR3
X
CR2
X
CR1
I COP
COP
NOP
NOP
DB4
DBa
NOP
NOP
DB3
DB?
NOP
DB2
DB4
DBa
X
X
DB3
DB?
DB1
DB1
X
LSEL=OO
LSEL= 11
LSEL= 10
LSEL=01
CR1
NOP
NOP
NOP
DB1
DB1
NOP
NOP
CR2
CR2
X
X
CR1
CR1
SOP Read
LSEL=OO
LSEL=11
LSEL= 10
LSEL=01
COP Write
4 Bytes
a Bytes
COP Read
4 Bytes
a Bytes
I COP
COP
X .... don't care
Siemens Components, Inc.
X
DB1, DB2 ... DBa ... coefficient Data Byte 1 .. a
182
PEB 2060
Operating Modes
Basic Setting
Upon initial application of VDD or reseting pin RS to "1" while operating, the SICOFI enters
a basic setting mode. Basic setting means, that the SICOFI configuration registers CR1 ... CR4
are initialized. All CR1 bits are set to "0" (all programmable filters are disabled except the
B-Filter where fixed coefficients are used, no test mode); CR2 is set to "1" (SA ... SO are
inputs, signaling expansion logic is provided, one SICOFI on SLO-port, Il-Iaw chosen and
fixed B-Filter coefficients used). All CR3 and CR4 bits are reset to "0" (no additional
amplification or attenuation, no linear mode, power down, no test mode). Receive signaling
registers are cleared. SIP is in high-impedance state, the analog output VOUT and the
receive signaling outputs SOl ... S03 are forced to ground.
The serial interface is active to receive commands starting with the next 8-kHz SLO-bus
frame. The serial interface port SIP remains tristate until CR2 has been defined.
If two SICOFls are connected to one SLO port, both SICOFls get the same SOP and CR2
information during initialization. The subsequent CR1 byte is assigned to the addressed
SICOFI only. If the two SICOFls need different CR2 information, the SOP-CR2 sequence
has to be provided once again (each SICOFI knows its address now).
Standby Mode
Upon reception of a SOP command to load CR2 from the basic setting, the SICOFI enters
the standby mode (basic setting replaced by individual CR2). Being in the operating mode,
the SICOFI is reset to standby mode with a Power-Up bit PU = 0 (in CR3 or in the SOPcommand directly). The serial interface is active to receive and transmit new commands
and data.
Operating Mode
From the standby mode, the operating mode is entered upon recognition of a Power-Up
bit PU = 1 (in CR3 or in the SOP-command directly).
Gain Adjustment
The transmit gain values are digitally programmable in the range of 0 to 8 dB in steps of
:5:0.25 dB.
The receive gain values are digitally programmable in the range of 0 to -8 dB in steps of
:5:0.25 dB.
Siemens Components, Inc.
183
PEB 2060
Transmission Characteristics - Preliminary
The target figures in this specification are based on the subscriber-line board requirements.
The proper adjustment of the programmable filters (transhybrid balancing: B; line termination: Z; frequency-response correction: X, R) needs a complete knowledge of the SICOFI®'s
analog environment. Unless otherwise stated, the programmable filters have the following
transfer functions:
H(Z) = H(B) = 0; H(X) = H(R) = 1; H(Gx) = 0 dB to 8 dB
H(GR) = 0 dB to -8 dB; H(AGX) = 0 dB to 14 dB; H(AGR) = 0 dB to -6 dB;
A 0 dBmO signal is equivalent to 1.5763 [1.5710] Vrms.
A 3.14 [3.17] dBmO Signal is equivalent to 2.263 Vrms which corresponds to the overload
point of 3.2 V. (A-law, [j..L-law]).
Limit Values
Parameter
Gain (either value)
Gain absolute
1000 Hz at OdBmO
RL> 1 kO
300 0 < RL < 1 kO
Symbol
min.
typo
max.
Unit
G
-0.2
-0.3
±O
0.2
0.20
dB
-0.05
-0.2
0
0.2
dB
Gain variation with supply voltage
and temperature
1000 Hz at OdBmO
Gv
Total harmonic distortion 1)
THD
-44
dB
Intermodulation
2f1-f2 2)
2f1-f2 3)
IMD
-42
-56
dB
Crosstalk
Transmit to receive
OdBmO
f = 300 Hz to 3400 Hz
Receive to transmit
OdBmO
f = 300 Hz to 3400 Hz
CTxR
-70
dB
CTxR
-70
dB
NRP
NRP
-67
-78
dBmOp
dBmOp
Idle channel noise
psophometric weighted
Transmit, VIN = 0 V
Receive, idle code +0
300 Hz and 3400 Hz produced by a 0 dBmO sine wave
in the range between 300 Hz and 3400 Hz.
2) Equal input levels in the range between -4 dBmO and -21 dBmO; different frequencies in the range
between 300 Hz and 3400 Hz.
3) Input level -9 dBmO, frequency range 300 Hz to 3400 Hz and -23 dBmO, 50 Hz.
1) Single-frequency components between
Siemens Components, Inc.
184
PEB 2060
Attenuation Distortion
Attenuation deviations stay within the limits in the figures below.
Figure 3
Receive: Reference frequency 1 kHz, input signal level 0 dBmO
1
c
0
:;::
2,0
dB
1,5
1,0
d
::J
c
J!
0,650dB
0,5
:d:
I
°
0,125 dB
0,125 dB
I
-0,5
3,4
-1,0
5 6 7 8910- 1
2
3
4 5 6 7 8910 0
f
..
2
kHz
4
Figure 4
Tl'ansmit: Reference frequency 1 kHz, input signal level 0 dBmO
2,0
dB
1,5
c
0
~:-:J
c
'"
«
1,0
0.650 dB
0,5
~
I
0,125dB
°
I
I
-0,5
3,4
-1,0
5 6 7 8910-1
2
3
4
5 6 7 B 910 0
f
Siemens Components, Inc.
..
185
2
kHz 4
0,125dB
PEB 2060
Group Delay
Maximum delays for operating the SICOFI with H(B) = H(Z) = 0 and H(R) = H(X) = 1,
including delay through AlD- and D/A converters. Specific filter programming may cause
additional group delays.
Group delay deviations stay within the limits in the figures below.
Group Delay Absolute Values: Input signal level 0 dBmO
Limit Values
Symbol
Parameter
Transmit Delay
f= 1.4 kHz
Receive Delay
f=300 Hz
typo
min.
max.
Unit
DXA
300
Ils
DRA
240
Ils
Figure 5
Group Delay Distortion: Input signal level 0 dBmO
500
f
)JS
1,.00
t
300
250---
200
100
0---
---
~
I
-
I~
- r-
I
I
2,8
I
o
o
0,7
0,5
1,0
1,5
Siemens Components, Inc.
2,5
2,0
f
..
186'
:
I
I
I
31
3,0 kHz 3,5
PEB 2060
Out-at-Band Signals at Analog Input
With an out-at-band sine wave signal with trequency f and level A applied to the analog
input, the level of any resulting frequency component at the digital output will stay at least
X dB below level A.
Figure 6
dB
,"
-6
I
I
-12
I
-18
Maximum input level A
at analog input
I
o
6
10-'
~
I
':&
1C'
5 kHz 10 2
5
5
f--_
40
Transmit out-at-band
discrimination X
dB
30
i
I
20
)
10
I
!
6
I
I
I
I:
t6
5 kHz 10 2
5
5
f
~
Out-at-Band Signals at Analog Output
With a 0 dBmO sine wave of frequency f applied to the digital input, the level at any resulting
out-of-band signal at the analog output will stay at least X dB below a 0 dBmO, 1 kHz
sine wave reference signal at the analog output.
Figure 7
50
dB
45-
t--
r-
r-- -
- t-
Receive out-of-band
discrimination X
---
40
J
30
I
I
I
I
20
I
15 - - -
- -
--
10
--
I
-
I
I
4,6
5
i
I
1,8
5 kHz 10 2
5
f----
Siemens Components, Inc.
187
PEB2060
Gain Tracking (receive and transmit)
The gain deviations stay within the limits in the figures below.
Figure 8
Gain Tracking: Measured with noise signal according to CCITT recommendations
Reference level is -10 dBmO
dB
2
.,dG
t
J]2~L
--"--
~1.@__ - - - 1 - -
o
OJ dB
-
r--
r-:o.5dB-
:0.2 dB
OJdB
r--
-1
-2
-70
-60 -55 -50
~40
-30
-20
o
-10
-
10 dBmO
Input Level
Figure 9
Gain Tracking: Measured with sine wave in the range 700 to 1100 Hz
Reference level is -10 dBmO
dB
2
1-=-4J!IL
.,dG
I
_L
Os dB
._-~1~-- - - - -
o
0.2dB
~0.5dB
-1
---
-14 dB
-2
-70
---
-- -
-r=
-60 -55 -50
-40
-30
-20
o3
-10
-
Siemens Components, Inc.
188
10 dBmO
Input Level
PEB 2060
Total Distortion (The signal-to-distortion ratio exceeds the limits in the following figures).
Figure 10
Receive: Measured with noise signal according to CCITT recommendations
dB
40
36.0
----34.3
---
......
-7
29.·'1
36.0
f--
~
:
,
,
I
o
-60 -55 -50
-40
I
I
I
!
I
I
10
28.4
I
20
14.7/
i\
:
I
I
I
I
:
I
I
I
I
·-34-30 -27
I
I
-20
I
-10 -6 -3 0 dBmO
Figure 11
Transmit: Measured with noise signal according to CCITT recommendations
dB
40
35.4
---
SID
!
i\
7r""""
.-
30
35,4
---
33,3-
7
28,7
I
20
13.2/
27,4.,..
10
o
-so
-60 -55
-40
-34-30-27
-20
-10 -6 -3 0 dBmO
Figure 12
Receive & Transmit: Measured with sine wave in the range 700 to 1100 Hz
excluding submultiples of 8 kHz
dB
40
3~5
SID
I
30
~9...?_
---,
__ r-_/
V
~H
20
10
-60
-50 -45 -40
-30
Siemens Components. Inc.
-20
-10
o dBmO
189
PEB 2060
Transhybrid Loss
The quality of transhybrid-balancing is very sensitive to deviations in gain and group delaydeviations inherent to the SICOFI A/D- and OfA-converters as well as to all external
components used on a line card (SLlC, OP's etc.).
The SICOFI transhybrid-Ioss is measured the following way: A sine wave signal with
level A and a frequency in the range of 300-3400 Hz is applied to the digital input. The
resulting analog output signal at pin VOUT is directly connected to IftN' e.g. with the SICOFI
testmode "Digital Loop Back via Analog Port" (see CR4). The programmable filters R, Gr, X,
Gx and Z are disabled, the balancing filter B is enabled with coefficients optimized for
this configuration (VOUT = IftN)'
The resulting echo measured at the digital output is at least X dB below the level of the
digital input signal as shown in the following figure.
Figure 13
--
40
1 dB
B
30
THL
-r--r---
25-
20
10
o
o
0.3
3;4
0.5
1,0
1,5
2,0
f
3,0
2,5
3,5 kHz 4,0
..
Note:
B-filter coefficients recommended for transhybrid loss measurement (VOUT = IftN)
B-filter part 1 (03) = DE, 12, 2B, 23, 15, 21, 31, 01
B-filter part 2 (03) = 00, 14, 4E, 5B, AC, DB, 1B, A3
B-filter delay (18) = 19, 19, 11, 19
Siemens Components, Inc.
190
PEB 2060
Absolute Maximum Ratings
Limit Values
Parameter
Symbol
min.
max.
Unit
Voo referred to GNDD
-0.3
5.5
V
Vss referred to GNDD
-5.5
0.3
V
GNDA to GNDD
-0.3
0.3
V
Analog input and output voltage
referred to Voo = 5 V; Vss = -5 V
referred to Vss = -5 V; Voo = 5 V
VtN
VtN
-10.3
-0.3
0.3
10.3
V
V
All digital input voltages
referred to GNDD = 0 V; Voo = 5 V
referred to Voo = 5 V; GNDD = 0 V
IliN
IliN
-0.3
-5.3
5.3
0.3
V
V
Po
Tstg
1
W
Storage temperature
-60
125
Ambient temperature under bias
TA
-10
80
°C
°C
Power dissipation
Operating Range
TA = a to 7aoC; Voo= 5 v ±5%; Vss=-5
v ±5%; GNDD= a V; GNDA= a V
Limit Values
Parameter
Symbol
Voo supply current
standby
operating
100
Vss supply current
Iss
min.
standby
operating
Power supply rejection
(of either supply/direction)
PSRR
Power dissipation standby
Power dissipation operating
POs
POo
Siemens Components, Inc.
typo
max.
Unit
Test Conditions
2.1
8
4
12
mA
mA
±5%supply
±5%supply
1.7
5
3
8
mA
mA
±5%supply
±5%supply
dB
1 kHz
80 mVrms ripple
mW
mW
±5%supply
±5%supply
35
20
70
191
37
105
PEB2060
Digital Interface
TA=Oto 70°C; Voo=S V±S%; Vss=-S V±S%; GNDD=OV; GNDA=OV
Limit Values
Parameter
Symbol
min.
max.
Unit
0.8
V
Voo+0.3
V
0.45
V
"iL
-0.3
H-input voltage
"iH
2.0
L-output voltage
10 =-2 rnA
VOL
L-input voltage
2.4
H-output voltage
V
10=400 f.l.A
Input leakage current
±1
IlL
f.l.A
-0.3 S; "iN S; Voo
Analog Interface
TA = 0 to 70°C; Voo= S V ±S%; Vss =-5 V ±S%; GNDD=OV; GNDA= 0 V
Limit Values
Parameter
Symbol
min.
Analog input resistance
RI
10
Analog output resistance
Input offset voltage
max.
Unit
MQ
Ro
10
Q
"io
±50
rnV
Output offset voltage
Voo
±50
rnV
Input voltage range
"iR
VOR
±3.2
V
Output voltage range
RL~300 Q;
CLS; .10 pF
Siemens Components, Inc.
±3.1
192
V
PEB2060
SIP Interface Timing (SLD-Bus)
Figure 14
SCLK
DIR
~
__________________+-______- J
SIP IN
SIP OUT
:==))-__________________=x=tdO=O=UT====»)-___
Switching Characteristics
Limit Values
Paramater
Period SCLK
Symbol
tSCLK
Duty Cycle
Period DIR
tOIR
DIR delay time
t dOIR
DIR high time
t hOIR
SIP data in setup time
tOIN S
SIP data in hold time
tOINH
SIP data out delay
min.
typo
max.
-10%
10
1/512 kHz
+10%
90
125
-20
500
50
20
SIP data out tristate delay VS. SCLK
250
RS high time
Siemens Components, Inc.
193
%
Ils
80
ns
ns
ns
ns
200
50
tdoOUT
Unit
ns
ns
ns
PES 2060
Signaling Interface Timing
Figure 15
SCLK
r--------------------- -----------------
SIP IN
t--'dSIGOUT
.j.------------------- ------ ----------
SIG OUT _ _ _ _-.II'T
SIP OUT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (
'SIGIN:}
__- - . . " j
SIG IN
--------------------------------
~
~-------
Switching Characteristics
Limit Values
Parameter
Symbol
min.
typo
max.
Unit
200
ns
Delay signaling out
vs.SCLK1)
tdSIGoul
time 2)
tSIGin S
50
ns
tSIGln H
100
ns
SIG in setup
SIG in hold time 2)
1) Pins S01 .. S03; Pins SA .. SO as output
2) Pins SI1 .. SI3; Pins SA .. SO as input
Siemens Components, Inc.
194
PEB 2060
Appendix A
The SICOFI can be used with three different SLD-bus type interfaces.
A specific interface type is selected with three pins: TEST, SI3 and PLL.
Figure 16
1) SLD-bus Interface1 )
TEST SI3
0
X
PLL
X
DIR
f=8kHz
SCLK
f= 512 kHz
MCLK
f= 4096 kHz
SIP Data
f =512 kHz
2) SLD-bus Interface with Variable Clock-frequencies 2 )
DIR
f/512 kHz
SCLK
f
MCLK
f
SIP Data
fl8kHz
3) Burst Mode Interface2 )
*J 813 cannot be
used as
Signalling pin
1)
2)
DIR
fl512 kHz
SCLK
f
MCLK
f
SIP Data
f
4096-kHz Masterclock.MCLK is generated from 512-kHz SCLK by on chip PLL
Maximum MCLK-frequency = 8 MHz
Siemens Components, Inc.
195
PES 2060
Appendix A (cont'd)
In burst-mode 8- or 16-bit bursts are received or transmitted, depending on the linear
mode selected (see field LID in eR3).
Figure 17
r-,
I r - - o J - - - - - - - - - -.....
DIR
I Vo·ce.A VoiceB
IA
I
LI 0
B
=211
iMSB+LSB
Control Signaling Voice A
(
n
(+S
S
A
n
VoiceB
B
C+S
Detail A
Detail A
J
SCLK
LlO=OO
Voice A
LlO=Ol
Voice A
LlO=10
Linear Voice
A.. .
voice A
C ... control
voice B
S ... signaling
MSB .. . bit 15 - 18 of linear in- or output
LSB .. . bit 7 - 0 of linear in- or output
B .. .
Siemens Components, Inc.
MSB
n
MSB+LSB
.... _ j
DIR
Control Signaling
196
LSB
A
r
PEB 2060
AppendixB
On Chip Sine-Wave Generation
By setting field TM3 in CR4 to '100' the on-chip sine-wave generator is activated with a
fixed frequency of 2 kHz. The frequency fSIN may be programmed via the R-filter coefficients
(R-filter enabled) in the range of 0 .. 4 kHz. The gain may be adjusted with the programmable
GR-filter.
The trapezoidal sine-wave generation algorithm used, provides for a harmonic distortion
better than 27 dB.
Calculation of the R-filter Coefficients:
f SIN : = 8192 * INCIfMcLK
with f MCLK' fSIN [kHz]
INC: = SRI * 2- EXPRI * (1 + SR2 * 2-EXPR2 * (1 + SR3 * 2-EXPR3 * ( .. ( .. (1
S ... SIGN, EXP ... EXPONENT
+ SR9 * 2-EXPR9) ..))
Figure 18
1
·LJ:I>I>I>I>I>l:'NC
R9
Al
R8
R7
R6
RS
R4
R3
R2
Rl
= INC
FORi:=1 T09DO
FIND Sj, EXPj : FOR (IAj - Sj * 2-EXPj l) = MIN; SjE (-1,1), EXPjE (0 ... 7)
Aj + 1 : = (AlSj * 2-EXPj) -1
R = [(-Sj + 1)12), BIN(EXPj)] (to be transfered to the SICOFI)
j :
NEXTi
Programming Byte Sequence for Selected Frequencies
Frequency
2000
1000
800
697
700
852
941
COP write
X
X X
X X
R, X
AB
00
00
00
00
8F
8F
8F
8F
AB
00
00
00
10
8F
8F
8F
8F
AB
00
00
00
10
AB
00
00
00
20
A1
2B
4B
B1
AB
00
00
00
10
CA
32
2D
B3
AB
00
00
00
10
3B
C1
BB
12
AB
00
00
00
10
CC
BB
12
DA
R3
R5
R7
R9
R2
R4
Re
Rs
AA
AA
AA
AA
X ... don't care
Siemens Components, Inc.
197
1209 1336 1477 1633
AB
00
00
00
10
B2
22
5F
8F
AB
00
00
00
10
22
A1
5F
1B
AB
00
00
00
10
D1
C1
BB
12
AB
00
00
00
00
1B
5C
CA
13
SIEMENS
Dual Channel Codec Filter (SICOR-2)
CMOSIC
Preliminary Data
Type
PES 2260
Ordering Code
Package
The Dual Channel Codec Filter PEB 2260 (SICOFI®-2) is a fully integrated PCM codec and
filter fabricated in low power CMOS technology for applications in digital communication
systems. Based on an advanced digital filter concept, the PEB 2260 provides excellent
transmission performance and high flexibility. The digital signal processing approach includes attractive programmable features such as transhybrid balancing, impedance matching, gain and frequency response correction.
The SICOFI-2 can be programmed to communicate either with SLD or withlOM®2 compatible
PCM interface controllers (e.g. PEB 2050/51/52/55).
The device bridges the gap between analog and digital voice signal transmission iR modern
telecommunication systems.
High performance oversampling Analog-to-Digital Converter (ADC) and Digital-to-Analog
Converter (DAC) provide the conversion accuracy required. Analog antialiasing Prefilters
(PREFI) and smoothing Postfilters (POFI) are included. The dedicated on chip Digital Signal
Processor (DSP) handles all the algorithms necessary, e.g. PCM bandpass filtering, sample
rate conversion and PCM companding. The SLD/IOM-2 interface handles digital voice
transmission, SICOFI-2 feature control and access to the SICOFI-2 signal pins. Specific filter
programming is done by downloading coefficients to the coefficient RAM (CRAM).
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual channel single chip codec and filter
Band limitation according to CCID and AT & T recommendations
Digital signal processing techniques
PCM encoded digital voice transmission (A-law or ~-Iaw)
Programmable digital filters for
- Impedance matching
- transhybrid balancing
- gain
- frequency response correction
SLD- and 10M2-interface
Programmable signaling interface to peripherals (e.g. SLlC)
High performance AID and D/A conversion
Programmable analog gain
Advanced test capabilities, per channel
- three digital loop back modes
- two analog loop back modes
- two programmable tone generators
No trimming or adjustments
.
No external components
Advanced low power CMOS technology
Power supply +/-5 V
198
PEB 2260
Pin Configuration for IOM·2 Mode
(top view)
Pin Configuration for SLD Mode
(top view)
o~z
>IIII!JIII>
Vss
CI2 A
C1A
C2A
TS1
SI3A
MODE
GNDD
RS
SBA
S01A
S02A
S03A
PES 2260
VSS
Voo
S039
S029
5019
S9B
C3A
MODE
GNDD
RS
PEB 2260
5139
Voo
DCl
FSC
DU
DO
TS 2
C2B
C19
CI28
SClK
D1R
eIJeIJeIJlDlD
I--C-Z
::l-z_~UI!J
>
eIJeIJeIJeIJlD
1- ....... 0 N Z
:::J-Z--
OV'l 1!JV'l >
>
Pin Definitions and Functions for SLD Mode
Pin No.
Symbol
Input (I)
Output (0)
Function
22
Voo
I
Power supply +5 V
8
Vss
I
Power supply -5 V
24
GNDD
I
Ground digital. Not internally connected to GNDA or GNDB.
All digital signals are referred to this pin.
1
GNDA
I
Ground analog channel A. Not internally connected
to GNDD or GNDB.
All channel A analog signals are referred to this pin.
15
GNDB
I
Ground analog channel B. Not internally connected
to GNDD or GNDA.
All channel B analog signals are referred to this pin.
27
VINA
I
Channel A analog voice input
VOUTA
0
Channel A analog voice output
17
VINB
I
Channel B analog voice input
13
VOUTB
0
Channel B analog voice output
25
MODE
I
Operating mode selection, connected to ground.
3
Siemens Components, Inc.
199
PEB 2260
Pin Definitions and Functions for SLD Mode (cont'd)
Pin No.
Symbol
Input (I)
Output (0)
Function
21
SCLK
I
Slave clock
20
DIR
I
Direction signal, 8-kHz-frame synchronization.
19
SIP
1/0
Serial interface port, bidirectional serial data port.
23
RS
I
Reset input, RS forces the SICOFI-2 to basic settings.
2
28
26
14
16
18
SI1A
SI2A
SI3A
SI1B
SI2B
513B
I
I
I
I
I
I
Signaling input: Data present at SI1 A ... SI3B are sampled
and transmitted via the serial interface
S01A
S02A
S03A
S01B
S02B
S03B
0
0
0
0
0
0
Signaling output: Data received via the serial interface
are latched and fed to S01A ... S03B.
SBA
SBB
1/0
1/0
5
6
7
11
10
9
4
12
Bidrectional signaling pin: SBA, SBB pins may be programmed as input or output individually with adequate
SICOFI-2 status settings.
Pin Definitions and Functions for IOM-2 Mode (cont'd)
Pin No.
Symbol
Input I
Output (0)
Function
22
Vee
I
Power supply + 5 V
8
Vss
I
Power supply -5 V
24
GNDD
I
Ground digital. Not internally connected to GNDA
andGNDB.
All digital signals are referred to this pin.
1
GNDA
I
Ground digital channel A. Not internally connected to
GNDD and GNDB.
All channel A analog Signals are referred to this pin.
15
GNDB
I
Ground analog channel B. Not internally connected to
GNDD and GNDA.
All channel B analog Signals are referred to this pin.
Siemens Components, Inc.
200
PEB 2260
Pin Definitions and Functions for IOM·2 Mode(cont'd)
Pin No.
Symbol
Input I
Output (0)
Function
25
MODE
I
Operating mode selection, connected to
27
VINA
I
Channel A analog voice input to transmit path
VOUTA
0
Channel A ·analog voice output of the received digital
voice
17
VINB
I
Channel B analog voice input to transmit path
13
VOUTB
0
Channel B analog voice output of the received digital
voice
21
DCLK
I
Data clock
20
FSC
I
Frame synchronisation clock
19
DU
0
Data upstream, serial data port output
18
DD
I
Data downstream, serial data port input
23
RS
I
Reset input, active high RS forces the SICOFI-2 to
power down mode and resets the configuration
registers
28
16
11A
11B
I
I
Indication input: Data present at 11A ... 11B are sampled
and transmitted via the serial interface.
5
6
26
11
10
C1A
C2A
C3A
C1B
C2B
0
0
0
0
0
Command output: Data received via the serial interface
are latched and fed to C1A ... C3A and C1 B ... C2B.
2
4
14
12
CI1A
CI2A
CI1B
CI2B
I/O
I/O
I/O
I/O
Bidirectional command/indication pin: C/1 A ... CI2B pins
may be programmed as input or output individually
with adequate SICOFI-2 status settings.
7
TS1
TS2
I
I
Time-slot selection pin 1 .. 2.
3
9
Siemens Components, Inc.
201
VOO.
PEB 2260
IOM-2 - Operating Modes
The SICOFI-2 is able to operate IOM-2-interfaces with two different Data Clock (DCl)
frequencies (512 kHz or 4096 kHz). Time-Slot Assignment of 8 time slots is available with
4096-kHz DClK frequency.
The IOM-2-operating mode and time-slot selection is set up by pin-strapping of two pins
TS1 and TS2, which work with ternary logic (-5 V, 0 V and +5 V).
TS1
N
o
o
'Slow' 10M-mode (DClK = 512 kHz)
'Fast' 10M-mode, time slot 0 selected
'Fast' 10M-mode, time slot 1 selected
'Fast' 10M-mode, time slot 2 selected
'Fast' 10M-mode, time slot 3 selected
'Fast' 10M-mode, time slot 4 selected
'Fast' 10M-mode, time slot 5 selected
'Fast' 10M-mode, time slot 6 selected
'Fast' 10M-mode, time slot 7 selected
N
o
N
o
p
p
N
P
o
o
N
P
N
P
P
_"- \/nl+ '\'
N .. .
TS2
\
.... - ..... " \-S5J
,'!u·,,'\IiL'!lr.'" +1"\ ..... ;..... Ta-t
..... ...,,.., .. ""'\001 '''''
tJUI
IT~"
IV II I V '
oVolt (GNDD) applied to pin TS1ITS2
+5 Volt (Voo) applied to pin TS1ITS2
0 .. .
P .. .
Block Diagram
PREFI
ADC
SLDI
IOM®·2
CHANNEL A
Interface
V~T_AI
I
PDFI
DAC
~
~------~--------~
DSP
PREFI
ADC
CHANNEL B
PDFI
CRAM
DAC
Siemens Components, Inc.
202
PES 2260
Transmission Characteristics
The target figures in this specification are based on the subscriber-line board requirements.
The proper adjustment of the programmable filters (transhybrid balancing B; line termination Z; frequency-response correction: X, R) needs a complete knowledge of the SICOFI-2's
analog environment. Unless otherwise stated, the programmable filters have the following
transfer functions:
H(Z) = H(B) = 0; H(X) = H(R) = H(GR) = H(GX) = H(AGR) = H(AGX) = 1
A 0 dBmO signal is equivalent to 1.5763 [1.5710] Vrms. A 3.14 [3.17] dBmO signal is equivalent to 2.263 Vrms which corresponds to the overload point of 3.2 V. (A-Iaw,[~-Iaw]).
Limit Values
Symbol
Parameter
Gain (either value)
Gain absolute
1 kHz at 0 dBmO
RL> 1 kQ
min.
typo
max.
-0.15
0
0.15
-0.25
0
0.15
-0.15
0
0.15
dB
G
Unit
dB
300 Q < RL < 1 kQ
Gain variation with supply voltage
and temperature
1 kHz at 0 dBmO
Gv
Total harmonic distortion')
THO
-44
dB
2'1-(22)
2'1-(2 3)
IMO
IMO
-44
-50
dB
dB
Crosstalk between
individual channels 0 dBmO
, = 300 Hz to 3400 Hz
CT
-70
dB
N RP
N RP
-67
-78
dBmOp
dBmOp
Intermodulation
Idle channel noise
psophometric weighted
transmit
receive 4 )
1) Single-frequency components between 300 Hz and 3400 Hz produced by a 0 dBmO sine wave
in the range between 300 Hz and 3400 Hz.
2) Equal input levels in the range between -4 dBmO and -21 dBmO; different frequencies in the range
between 300 Hz and 3400 Hz.
3) Input level-9 dBmO, frequency range 300 Hz to 3400 Hz and -23 dBmO, 50 Hz.
4) Test conditions to be defined.
Siemens Components, Inc.
203
PEB2260
Attenuation Distortion
Attenuation deviations stay within the limits in the figures below.
Figure 1
Receive: Reference frequency 1 kHz, input signal level 0 dBmO
2,0
dB
1,5
1
c:
0
1,0
~
c:I
::0
c:
~
1--
0,5
:::c
0,650dB
I
0,125 dB
0
0,125 dB
i
-0,5
3,4
-1,0
5678910- 1
2
3
45678910°
f
2
kHz
4
..
Figure 2
Transmit: Reference frequency 1 kHz, input signal level 0 dBmO
1
c
0
:g
2,0
dB
1,5
1,0
::0
c
'"
:::
0,650 dB
0,5
I
<.{
a
-
I
I
-0,5
3,4
-1,0
5 678910-1
2
3
4
5 6 7 8 910 °
..
f
Siemens Components, Inc.
204
2
kHz 4
0,125 dB
0,125dB
PES 2260
Gain Adjustment
Transmit gain values GX are programmable from 0 to 8 dB in steps ~ 0.25 dB. Receive
gain values GR are programmable from 0 to -8 dB in steps ~ 0.25 dB. Together with the
analog gain adjustments AGX, AGR (0, 6, 12, 14 dB) the SICOFI-2 offers a programming
range of 22 dB.
Group Delay
Maximum delays for operating the SICOFI-2 with H(B) = H(Z) = 0 and H(R) = H(X) = 1,
including delay through AlO- and O/A converters. Specific filter programming may cause
additional group delays.
Group delay deviations stay with the limits in the figures below.
Group Delay Absolute Values: Input signal level 0 dBmO
Limit Values
Parameter
Symbol
Transmit Delay
f= 1.4 kHz
Receive Delay
f=300 Hz
typo
min.
max.
Unit
DXA
340
J.Ls
ORA
280
J.Ls
Figure 3
Group Delay Distortion: Input signal level 0 dBmO
t
500
.us
400
t
300
-
250--- ' - -
200
100
70
I
:
I
r---
o
o
--+ 0.5
-I
I
I
I
I
0.7
2.8
31
1.0
2,0
1,5
f
Siemens Components, Inc.
2,5
...
205
3,0 kHz 3,5
PEB 2260
Out-ot-Band Signals at Analog Input
With an out-of-band sine wave signal with frequency f and level A applied to the analog
input, the level of any resulting frequency component at the digital output will stay at least
X dB below level A.
Figure 4
dB
o
I
-6
I
-12
I
-18
i'
I
6
10-'
Maximum input level A
at analog input
I""
I
lei
,:,
5 kHz 10 1
10'
5
f---_
5
40
Transmit out-of-band
discrimination X
dB
[JIIIIIIII IIII11111
30
I
I
20
,
10
1
I
6
I
!
:I
I
I
4,6
5 kHz 10 2
5
5
f
..
Out-of-Band Signals at Analog Output
With a 0 dBmO sine wave of frequency f applied to the digital input, the level of any
resulting out-of-band signal at the analog output will stay at least X dB below a 0 dBmO,
1 kHz sine wave reference signal at the analog output.
Figure 5
';0
dB
45-
r-- - r--
r-
---
f-
40
I
30
i
Receive out-of-band
discrimination X
I
I
I
20
I
15---
- -
f----
I
-- -
1
'0
I
5
1
I
4,0
',8
5
5 kHz 10 2
10'
f-,---
Siemens Components, Inc.
206
PEB 2260
Gain Tracking (Receive and Transmit)
The gain deviations stay within the limits in the figures below
Figure 6
Gain Tracking: Measured with noise signal according to CCITT recommendations
Reference level is -10 dBmO
dB
2
~:?@- --""'~l@__ - - - - -
o
-
-
-0.2 dB
0.3 dB
=o.5aB- -
O.3dB
r--
-1
-2
-70
-60
-55 -so
_40
-30
-20
o
-10
-
10 dBmO
Input Level
Figure 7
Gain Tracking: Measured with sine wave in the range 700 to 1100 Hz
Reference level is -1 0 dBmO
dB
2
o
11t.!!E!._
_L
0.5dB
._--
r-9. 2dB _
-_.
0.2dB
~0.5dB r ---1
--_ ..-
-14dB
-2
-70
-r
-60 -55 -50
-40
-30
-20
o3
-10
-
Siemens Components, Inc.
207
10 dBmO
Input Level
PES 2260
Total Distortion (Receive and Transmit)
The signal-to-distortion ratio exceeds the limits in the following figures.
Figure 8
Total Distortion: Measured with noise signal according to CCITT recommendations
dB
40
36.0
I-36.0-~ 1---- r-
34,3
T~
[2:
29.7
20
t.zC
I
-40
i
I
I
I
!
!
i
:
i
I
I
-60 -55 -50
i
I
I
I
o
I
I
I
I
10
28.4 -
I
I
:
I
14.7/
--
~
:
-34-30 -27
-20
I
-10 -6 -3 0 dBmO
Figure 9
Total Distortion: Measured with sine wave in range 700 to 100 Hz
dB
40,----,----,-----r----,----,----,
~~ - _. --- .... - - .-::;;;>+---t---t--~
I
SID
J1-- t:::.--...:;;~
30 ~---r--/
20r----+--~~----r----+-----t---~
10r----+--~~----r----+-----t---~
-60
-50 -45 -40
Siemens Components, Inc.
-30
-20
208
-10
o dBmO
PEB 2260
Transhybrid Loss
The quality of transhybrid-balancing is very sensitive to deviations in gain and group delay.
The SICOFI-2 transhybrid-Ioss is measured the following way: A sine wave signal with
level A and a frequency in the range of 300-3400 Hz is applied to the digital input. The
resulting analog output signal at pin VOUT is directly connected to Y;N e.g. with the SICOFI-2
testmode "Digital Loop Back via Analog Port" (see eR3). The programmable filters R, Gr, X,
Gx and Z are disabled, H(AGR) = H(AGX) = 1 and the balancing filter B is enabled with
coefficients optimized for this configuration Y;N = VOUT )'
The resulting echo measured at the digital output is at least X dB below the level of the
digital input signal as shown in the following figure.
Figure 10
I
THL
-- ----
40
dB
33
30
20
t--
25-
10
o
o
3,4
~3
0,5
1,0
1,5
2,5
2,0
f--..
3,0
3,5 kHz 4,0
Note:
B-filter coefficients recommended for transhybrid loss measurement
with VOUT = Y;N:
B-filter part 1 (03) = see PEB 2060 pp, 185
B-filter part 2 (08) = see PEB 2060 pp. 185
B-filter Delay (18) = see PEB 2060 pp. 185
Siemens Components, Inc.
209
PES 2260
Absolute Maximum Range
Limit Values
Symbol
min.
max.
Unit
Voo referred to GNDD
-0.3
5.5
V
Vss referred to GNDD
-5.5
0.3
V
GNDA, GNDB to GNDD
-0.3
0.3
V
Parameter
Analog input and output voltage
referred to Voo = 5 V; Vss = -5 V
referred to Vss = -5 V; Voo = 5 V
\liN
\liN
-10.3
-0.3
0.3
10.3
V
V
All digital input voltages
referred to GNDD = 0 V; Voo = 5 V
referred to Voo = 5 V; GNDD = 0 V
\liN
\liN
-0.3
-5.3
5.3
0.3
V
V
Power dissipation
Po
1
W
Storage temperature
Tstg
-60
125
Ambient temperature under bias
TA
-10
80
DC
DC
Operating Range
TA = to 70 DC; Voo= 5
a
v ±50f0; Vss=-5 v ±50f0; GNDD= OV; GNDA= OV
limit Values
Parameter
Symbol
Voo supply current
standby
operating
100
Vss supply current
standby
operating
Iss
Power supply rejection
(of either supply/direction)
PSRR
Power dissipation standby
Power dissipation operating
Pos
Poo
Siemens Components, Inc.
min.
typo
max.
Unit
Test Conditions
0.5
14
0.8
20
mA
mA
±5%supply
±5%supply
0.1
10
0.2
15
mA
mA
±5%supply
±5%supply
dB
1 kHz
80 mVrms ripple
mW
mW
±5%supply
±5%supply
35
3
120
210
5
175
PEB 2260
Digital Interface
TA = Oto 70°C; Voo= 5 V ±5%; Vss=-5 V ±5%; GNDD= OV; GNDA= OV
Limit Values
Parameter
Symbol
min.
max.
Unit
L-input voltage
~l
-0.3
O.B
V
H-input voltage
~H
2.0
Voo+0.3
V
L-output voltage
VOL
0.45
V
10=-2 mA
H-output voltage
10= 400 j.1A
VOH
Input leakage current
-0.3 :S: ~N:S: Voo
III
2.4
V
±1
j.1A
Analog Interface
TA = 0 to 70°C; Voo = 5 V ±5%; Vss =-5 V ±5%; GNDD= OV; GNDA= OV
Limit Values
Parameter
Symbol
min.
10
max.
Analog input resistance
RI
Analog output resistance
Ro
10
Unit
MQ
Q
Input offset voltage
~o
±50
mV
Output offset voltage
Voo
±50
mV
Input voltage range
~R
±3.2
V
Output voltage range
RL~300 Q;
Cl :S:50 pF
VOR
Siemens Components, Inc.
±3.1
211
V
PEB2260
SLD-Bus Interface Timing
Figure 11
SCLK
DIR
~-------
______+-______-J
SIP IN
-~E_=-m:-----t--t:::-~_
SIP OUT
==:J'""--------------------------m
=t'--.. ). ----
Switching Characteristics
Limit Values
Parameter
Period SCLK
Symbol
tSCLK
10
Period DIR
tOIR
DIR delay timw
t dOIR
DIR high time
t hOIR
SIP data in setup time
tOINS
SIP data in hold time
tOINH
max.
90
125
Unit
ns
50
0
ns
ns
ns
200
50
SIP data out tristate delay vs. SCLK
250
212
%
I1s
+20
500
tdoOUT
RS high time
Siemens Components, Inc.
typo
1/512 kHz
Duty Cycle
Thermal resistance junction to ambient
min.
ns
ns
ns
PES 2260
Signaling Interface Timing
Figure 12
SCLK
r------------------------
SIP IN
I-- t
dSIG OUT
f
SIG OUT
----~
SIP OUT ------------------------- - - ---------{
tSIGINJ
SIGIN
--------------------------------
~--~
Switching Characteristics
Limit Values
Symbol
Delay signaling out vs. SCLK1)
tdSIGout
SIG in setup time2 )
tSIGin S
50
ns
tSIGin H
100
ns
SIG in hold
time2 )
1) Pins S01A ... S03B; Pins SBA, SSB as output
2) Pins SI1A ... SI3B; Pins SBA, SeB as input
Siemens Components, Inc.
213
min.
typo
Parameter
max.
Unit
200
ns
SIEMENS
Application Support for Exchange ICs
STU 2050
The Siemens Telecom User Boards (STU 20xx family) provide quick and convenient introduction to the complex device functions. They allow all important functions to be tested
in a system-like configuration with the existing software and a terminal with an RS 232 CN.24
serial interface as well as application specific software to be developed with a microprocessor system.
The Siemens Telecom Software (STS 2060) is a FORTRAN program for calculating the
coefficients of the programmable filters in the SICOFI@ PEB 2060 in consideration of the
various subscriber line parameters.
MTS, PBC and SICOFi® Boards
I .,....------MTS User Board
PBC User Board
Subscriber A
SICOFI A
SIP 0
PCM IN 1
'--t-::PC:::-M"'IN""2--11 N 12
TxHW 1
'----t-'-"--'-'--"----il N 13
TxHW 0
MTS
PSC
OUT 0
OUT 1
RxHW 0
PCM OUT 1
PCM OUT 2
SICOFI B
RxHW 1
Subscriber B
SICOFI®
User Board
ClK
RxSO
TxSD
Signaling Highway
o
Secondary Station
Primary Station
214
SIEMENS
STU 2050
PBC User Board
Type
Ordering Code
STU 2050
Q67100-Z166
The PBC is connected as a peripheral device to a SAB 8031 ).LP system. This allows
the user to do programming himself. Thus the PBC caters for special application conditions.
This requires the use of a ).LC development system with an ICE-51 in-circuit emulator.
The I/O unit has an RS 232 CN.24 interface (receiver, transmitter). Without a IlC development
system the user board can also be used with the existing software, connected to a terminal
with a serial interface. The terminal acting as an I/O unit calls the PBC registers by the
corresponding names e.g. ABR = 78. By this means, the different PBC functions can be
set or data can be read or written (e.g. time-slot assignment, PCM-mode switching,
HDLC protocol, reading of status register).
The User Board Circuit Provides the Following Functions:
•
•
•
•
•
•
•
•
PCB: Peripheral Board Controller PEB 2050
).LC: microcomputer SAB 8031 (SAB 8051) with program memory and driver
MUX: multiplexer for selecting the SIP serial interface port lines
EX1, EX2: two exchange connections with control logic
The following interfaces help execute the various functions on the board:
Dual PCM interface (highway HW 0, HW 1)
Fast serial interface (HDLC)
Serial interface with the microcomputer (receiver, transmitter)
Codec interface (CHA Rec, CHB Rec and so on) via exchange connection 1, (EX 1)
Serial Interface with Microcomputer
Any terminal or teletype with an RS 232 C!V.24 interface (25-pin D-subminiature connector)
can be connected to the serial interface. The following baud rates can be set by DIL
switches:
300, 1200, 2400, 3600 Bd.
Codec Interface
(exchange connections 1 and 2)
In the exchange connections the serial data coming from the PBC are converted to parallel
form and loaded into the corresponding registers. Thus data for channel A (CHA), channel B
(CHB), control and signaling are then ready for use as parallel 8-bit data (receive direction).
In the reverse direction the parallel 8-bit data are converted into serial form and transmitted
to the PBC (transmit direction). The 8-bit receive and transmit data of connection 1 are fed
to a plug connector and are available for the user in the hardware. Here the user can
connect different codecs and peripheral circuits.
215
S11J 2050
Exchange connection 2 feeds the data to the I-LC data bus. The microcomputer can call
the data with a corresponding address.
Features
•
•
•
•
•
•
•
•
PBC PEB 2050 on board
SAB 8031 microprocessor system
32-Kbyte EPROM (program memory)
Two universal interfaces for connecting peripheral circuits and PCM
or signaling highways
Serial interface RS 232 CN.24 with selectable baud rates
of 300, 1200, 2400, 9600 Bd
Selectable PCM clock (2.048 MHz or 4.096 MHz)
Power supply:
+ 5 V ± 5%, 1.5 A central supply
± 12 V ± 5%,0.1 A for RS 232 C interface
Delivered with a detailed user manual
PBC User Board
,~ l·~~
ClK
CHA
SYP
Conlrol
Connector
Unill
EXl
Highways
Signaling
CHA
".
two
Conlrol
Signaling
HWl
HOlC
SClK
OlR
OlR
SClK
SIGS
ClK
SYP
Connector
Unil2
EX 2
RD
WR
Siemens Components, Inc.
}~
216
SIEMENS
SICOR User Board
Type
Ordering Code
STU 2060
Q67100-H3238
STU 2060
With the SICOFI® and the PSC user board an analog subscriber line circuit is generally
implemented. A subscriber branch contains a Subscriber Line Interface Circuit (SLlC) and
a Signal Processing Codec Filter (SICOFI).
Telephone terminals are connected by the a and b wires to the subscriber line circuit,
which implements primarily the line matching, the 2/4-wire conversion and AID or D/A
conversion of the voice signals. Control and supervision functions can additionally be performed by means of programmable inpuVoutput pins of the SICOFI.
STU 2060 can be broken down into four subscriber line circuits, connected by the SIP
lines of the SICOFI devices of the PSC on the STU 2050. The latter handles the switching
function for the individual voice channels and, in addition, the programming of the SICOFI
devices is performed by way of the PSC.
On the user board the Harris SLiC HC5502 is incorporated in two of the four subscriber
branches, while the other two subscriber branches are fitted with a user sLie. Seeing
as the two supplied transformer SLiCs are plugged into the user board, the user can
simply plug a self developed SLiC into a socket in order to check in transfer functions
of the SLiC in conjunction with the SICOFI.
The advantage of the SICOFI user board is thus that the user can quickly become familiar
with the functioning of the SICOFI and also with the use of the SICOFI in a system
environment made up of SLiC and PSC.
Features
• Four SICOFI PES 2060 on board
• Four analog subscriber lines
• Two electronic SLiCs
Harris HC 5502 on board
• Two transformer SLiCs on board
• Customer can develop his own SLiCs on two plug-in modules
• Interface for four telephones
• Digital 500-Hz tone
• 16-kHz pulse for maintenance
• Zero level detection for switching the ring voltage
217
S1\J 2060
SICOFI User Board
16kHz
Call-Charge Pulse
1---4r-~SCLK
I-~--+---o
SICOFI •
SIP 0
I--+_I-~DIR
a
a
I--+-+------<> SIP 6
a
1--+1----0 SIP 7
500Hz, Digital
1---------<> SIP 1
Call Synchronization
L - . . - - - - - - - - - - - - - -___......_-o Call
Siemens Components, Inc.
218
SIEMENS
STUT2060
SICOR Test Board
Type
Ordering Code
STUT2060
067100-H6058
The SICOFI® test board STUT 2060 offers the possibility of connecting any external customer
specific SUCs with the SICOFI for evaluation of customer specific combinations of SUC
and SICOFI. This setup allows measurements and tests covering the transfer functions
of the complete subscriber line module.
The board is programmable via an RS 232 interface by a terminal or PC. The registers
of PBC and SICOFI can be accessed and therefore the SUC can be programmed.
Different customer specific SUCs may be built up separately and may be connected to
the SICOFI test board STUT 2060 via a 64-pin connector.
With his specific SUC program and together with the SICOFI coefficient program STS 2060,
the customer is able to calculate SUC specific programming bytes in order to program
and test his SUC hardware.
Features
•
•
•
•
Two SICOFI PEB 2060 and one PBC PEB 2050 on board
SAB 8031 microprocessor system
Serial interface RS 232 C
Two interfaces for connecting customer specific SUC boards
219
(J)
en
(5"
8
!!
3(!l
:::J
C/)
~
o
o
3
o
Connector for SLIC 0
"0
!!1.
Connector for SLIC 1
:::J
(!l
o
:::J
§l VIN/1
o
CON 6
o
10
:::J
6
II I I I I
@GrOund Analog
9
,
YOUT/1
5
SICOFI@O Part
CON 5
':\
O
~
o
[?~l
RAM BKBI
15
RS 232
Interface
I
i r
:
r
!
SICOFI@ol
I
SIPO
r------------~
SICOFI@'I
I
SIP1
I
I
L-----T---~---------------
u
a
.
*
.------------, D1
r
PBC
1
I
N
U
r
o
8031
-
--J
10
I
S2
I
5
10
DIL2
02 12345678
~i
Highway
Connection
o
CON 3
to PBC Board
(not connected)
Clock Part
EHE3
1
5
o.uarz
10
ffiE3 CON4
1
111111111
6
6
DIL1
1 234
IIIIJ
6
111111
1
[JI]
I
PBC Part
Microprocessor Part
Z
o
VIN/2
BNC
YIN 12
Banana
jr.o
.........
~''--., V0 UTI 2
BNC
2a.
I
----------------,
Power
Supply
SICOFI@ 1 Part
I
OJ
I\)
I\)
o
CON 7
---.
Clock IN
5
(512 kHz)
o
Receive
HWO
Transmit
HWO
~
~
!
ICs for ISDN Exchange Systems
ICs for ISDN Exchange Systems
Introduction
The advent of the Integrated Services Digital Network (ISDN) and the office of the future has
emphasized the need for cost-effective silicon solutions to the problems of simultaneous
transmission of digitized voice and data over existing twisted-pair copper wiring. Basic access
ISDN can be considered as an international concept which supports two circuit switched
64-kbitls B channels and a message oriented 16-kbitls 0 channel for packetized data, signaling and telemetry information. According to CCITT recommendations, the basic architecture
for the subscriber access consists of an exchange and line termination (ET, LT), a remote network termination (NT), a two-wire loop (U interface) between NT and LT and the four-wire link
(S interface) which connects the subscriber terminal (TE) with the network termination. The
NT equipment serves as a link between the U interface on the exchange and the S interface
on the user side.
Typical problems which have to be overcome during the initial phase of ISDN are:
•
•
•
System implementation calls for a complete chip set supporting the subscriber access.
Technical and economical demands dictate the use of advanced VLSI technology; manual
designs to achieve sma" chip size result in high development effort.
The lack of international standards for fu"-duplex two-wire transmission as we" as different
application configurations call for highly flexible system architecture.
ISDN Oriented Modular System Architecture
The IOM® architecture and the interfacing of the VLSI circuits are designed according to the
following criteria:
•
•
•
•
High modularity ensures flexible interconnection of the devices for different applications.
Use of identical devices in different applications by mode switching results in a minimum
number of individual ICs. The resulting increase in device quantity enables the price
reduction crucial to initial ISDN introduction.
Suitable partitioning in the initial phase permits the implementation of devices of easily
managed complexity with regard to development risk, resources and time.
A we" defined ISDN Oriented Modular (10M) interface simplifies system design, provides
the security of an industry standard, supports flexible interconnection of the different
devices and, moreover, makes the use of different compatible transceivers possible.
Based on the 10M architecture, the product development strategy allowed a step by step
introduction of ISDN systems. While in the first step the layer-1 and layer-2 functions for a"
applications were implemented in separate devices, further optimization and cost reduction
has been achieved in a second step by forward integration. The combination of layer-1, layer-2
and further functions on single devices was planned from the beginning of development and
was taken into account in the circuit design.
The 10M architecture as introduced, supports the design of equipment for ISDN terminals,
terminal adaptors, network terminations and line cards for digital exchange equipment (see
figure on the following page).
Siemens Components, Inc.
223
ISDN Oriented Modular (10M) Architecture
Second Generation ISDN ICs, IOM®-2 Interface
Network Termination
Subscriber Terminal
Oigital Exchange
4 PCM
Hwys.
a --JI
PEB 2025
PEB 2055
PEB 2056
PEB 2075
PEB2081
PEB 2085
PEB 2090
PEB 2091
PEB 2095
PEB 20950
PSB 2110
PSB 2120
PSB 2160
SAB 82525
Note:
ISDN Exchange Power Controller
Extended PCM Interface Controller
Extended PCM Interface Controller
ISDN D-Channel Exchange Controller
SIT Bus Interface Circuit Extended
ISDN Subscriber Access Controller
ISDN Echo-CancellE\tion Circuit (4B3T)
ISDN Echo-Cancellation Circuit (2B 1Q)
ISDN Burst Transceiver Circuit
ISDN Subscriber Access Controller
ISDN Terminal Adaptor Circuit
ISDN Remote Power Controller
Audio Ringing Codec Filter
High-Level Serial Communications
Controller Extended
IEPC
EPICTM-1
EPICTM-2
IDECTM
SBCX
ISACTM-S
IEC-T
IEC-Q
IBC
ISACTM-P
ITACTM
IRPC
ARCOFI®
HSCX
The ISAC-P is used for 2-wire PBX terminals in place of the ISAC-S. Four
different transceivers (IEC-T, IEC-Q, SBCX, IBC) are available for different
digital exchange subscriber loops (PBX or public, 2- or 4-wire, short or long
lines).
Siemens Components, Inc.
224
10M Interface
The standardized interface which makes all of this flexibility possible is the same 10M interface that was developed by Siemens Semiconductor, but now with some additional features
suggested by ALCATEL, Siemens, Plessey and ITALTEL systems designers. The IOM-2
interface is identical to the General Circuit Interface (GCI). GCI is the working name that
was used within the "Group of Four" for this interface specification.
The 10M interface now has a flexible data clock. In this way, data transmission requirements
are optimized for different applications. Three different clock speeds are used with the
Siemens architecture shown below. For a network termination (NT 1), a 512-kHz-clock is
used resulting in a data transmission speed of 256 kbiVs. In a single 125 IJ.s frame, one
"10M channel" is transmitted containing the 28+0 channels plus maintenance and control
information for a single ISDN subscriber. For terminals, a 1536-kHz clock and a 768-kbitls
data rate enable three complete 10M channels to be transmitted in a single frame. The
extra bit rate is used for communication within the terminal (see ISDN terminals). On line
cards, a 4096-kHz clock has been selected so that up to eight 10M channels and thus,
eight ISDN subscribers can be multiplexed over a single interface.
The C/I channel is used for passing command and indication information for controlling
activation/deactivation and switching of test loops. The monitor channel can be used for
transmitting maintenance and additional control information. Data transfer in the monitor
channel is facilitated by using the bits MR and MX for a "handshaking protocol" to acknowledge
the transmission and reception of messages.
IOM·2 Frame Structure
,-
FSC
-I
125 Ils
J
r
8 kHz
I
Basic Mode
DCLK
NT 1, RPT
I
I
..Jl.Sl.SL ...
1
1
1
512 kHz
1
Data
>
S
HS(X
L
Signaling
Highway
P
I P
L
(011
Packet Handlers
The EPIC is an important building block for networks based on either central, decentral or
mixed signaling and packet data handling architectures. Its flexibility allows for the modification of the packet handling architecture according to the changing needs.
Thus, it may be useful to add central packet handling groups to a network originally based
on decentral signaling packet handling. This may be the case if growing data packet traffic
exceeds the initial capacity of the network. The result .is a mixed architecture.
On the other hand, increasing packet handling demand on a few dedicated subscriber lines
calls for solutions which back up the capacity at these few decentral line cards.
In both of these cases and several other applications, the EPIC is a powerful device for solving
the problem of packet handling. In most applications, it is used together with the IDEC (ISDN D
Channel Exchange Controller).
Decentralized and mixed packet handling has already been covered in the line card chapter.
In the following, the centralized signaling/data packet handlers built up with the EPIC will be
described.
Siemens Components, Inc.
255
PEB2055
Central packet handling is used if many subscribers with a generally low demand for packet
switching are to be connected to a system. Concentrating the packet servers for multiple
users eliminates the need to provide a packet server channel for every user. The overall
number of packet server channels can thus be reduced.
In such a central packet handling group, the EPIC performs the switching and concentrator
function. It connects a variable number of PCM highways to the packet handler internal
highway. HDLC controllers are also connected to this internal highway as illustrated in
figure 9.
Figure 9
Centralized Packet Handler with a Single Internal Highway Connectecl to 4 PCM Highways
PCM Highways
ABC
D
,
Packet Handler Internal Highway
I
EPIC™-1
1
I IDEC ™I
IIDEC ™I
-n
lr
1'1
~j.
I
II C
...
J
Centralized Packed Handler Unit
This figure shows one EPIC connecting four PCM highways to one packet handler internal
highway. These highways are accessed by the IDECs (ISDN 0 channel Exchange Controller)
which are 4 channel HDLC controllers and handle the packets. If more than four PCM
highways shall be connected to the centralized packet handler, further EPICs are necessary.
Such a situation is shown in figure 10, where 8 highways are switched to one packet handler
internal highway. In this case the two EPICs are connected in parallel at the packet handler
internal side.
Siemens Components, Inc.
256
PEB 2055
Figure 10
Centralized Packet Handler with 1 Internal Highway Connected to 8 PCM Highways
PCM Highways
ABC 0 E F G H
L~
Packet Handler Internal Highway
EPIC™-1
~
.It
. . .7
EPIC™_1
r.--
j
...
Id5
r
Centralized Packet Handler Unit
The data rate of the packet handler internal highway can be up to 4096 kbitls. If this capacity
is not sufficient, other packet handler internal highways may be added as shown in figure 11.
Figure 11
Centralized Packet Handler with 3 Internal Highways
PCM Highways
ABCDEFGH
t~
Packet Handler Internal Highways
EPlC™_1
Lt
~ ~
,t
.1
EPIC™_1
~
...
IJC
f=r--
t
Centralized Packet Handler Unit
Siemens Components, Inc.
257
PEB 2055
In some applications an additional collision resolution signal is required for the HOLC controllers. This information can be demultiplexed from the PCM highways to a third line for each
packet handler internal highway (see figure 12).·
Figure 12
Centralized Packet Handler with Internal Collision Line
PCM Highways
A B (
D
f
Packet Handler Internal Highways
EPIC M·1
HI
IlDEC™I
I IDEC ™ I
fr
1r
U
I I
~('''i'i,"
Indication
Line
JJC
Centralized Packed Handler Unit
The applications illustrated apply equally to centralized signaling as well as to data packet
handlers.
Siemens Components, Inc.
258
PEB 2055
Functional Description
The EPIC is a peripheral board controller. It combines the non blocking switching function
between the PCM and the configurable interfaces for 128 channels per direction with the
layer-1 control function for connection set-up/termination/maintenance on one chip.
A general block diagramm of the EPIC is shown in figure 13.
In the downstream direction, the input information of a complete frame is stored in the data
memory. The incoming channels are written in sequence into fixed positions in the data
memory. This is controlled by the downstream input counter with an 8-kHz-repetition rate.
A cyclic write sequence results.
For the downstream switching, the control memory (CM) is read in sequence. The addressed
location contains a pOinter to a location in the data memory. The byte in this data memory
location is read into the current configurable interface time slot, resulting in a random read
sequence.
The read access of the control memory is controlled by the downstream output counter,
correlating the data memory read operations with the downstream output time-slot sequence.
In the upstream direction, the data is written to the data memory randomly, under CM control
and read from there cyclically.
Hence, for the desired connection the control memory needs to be programmed beforehand
using the MAAR, MADR and MACR registers (see chapter Memory Access Register). The
control memory address corresponds to one particular configurable interface time slot and
line number. The contents of this control memory address point to a particular PCM interface
time slot and line number now resident in the data memory.
For upstream output, four control bits per time-slot are provided in the data memory. These
control the output driver state of any possible subtime slot.
Besides the data memory address, each CM address also points to four code bits determining
the bandwidth of the switched channel. These code bits are also used to mark the signaling
channels at the CFI.
The EPIC can be used in two different set-ups:
•
•
In the bidirectional set-up, every channel at the configurable interface can be programmed
to be either input or output. 8 equivalent bidirectional ports at the configurable interface
result.
In the duplex set-up, 4 of the 8 lines of the configurable interface are predetermined as
outputs, 4 as inputs. 4 duplex ports result.
In both of these set-ups, the EPIC provides a switching capability for up to 128 channels
and direction.
The 10M and the SLD configurations previously mentioned are special cases of these set-ups:
•
•
In the 10M, the EPIC switches the Band D channels of up to 32 subscribers working in the
duplex set-up. Additionally, the device handles the monitor and CII channel buffering to
the !J.P.
In the SLD configuration, the EPIC switches up to sixty four 64 kbiVs channels operating in
bidirectional set-up. Additionally, the device handles the feature control and signaling
channels buffering to the !J.P.
Siemens Components, Inc.
259
PEB 2055
Figure 13
Functional Block Diagram of the EPIC
RES
DCLK/SCLK
FS( /DIR
D01/SIPl
OU1/SIPS
D02/SIP2
DU2ISIP6
OD3/SIP3
DU3/SIP7
P
C
M
C
0
I
n
f
i
g
u
r
a
b
I
e
PFS
I
~
DDO/SIPO
DUO/SIP4
poe
I
Timing
I
I
n
t
e
r
f
a
c
e
.
Data Memory
r-v
I
Layer -1
Controller
Buffer
~
f\r"""-V
it
I
n
t
e
r
f
a
c
e
RxDO
TxDO
Tseo
RxDl
TxDl
TSCl
RxD2
TxD2
TSC 2
Ry.D3
TxD3
TSC 3
Control
Memory
~
jJP Interface
r
).
V
AOO ...7
RD
WR
ALE
CS
INT
In the 10M configuration, upon proper programming, the EPIC checks the incoming CII channels and generates interrupts if changes occur. In the case of the bidirectional configuration,
it implements the double last look algorithm with a period adaptable to a wide range of system
needs.
For handling the monitor or feature control channel, the EPIC is equipped with a FIFO buffering up to 16 bytes of information. The contents can be transferred or received upon a special
command. Or, they can be dealt with largely autonomously according to the 10M handshake
procedure.
Siemens Components, Inc.
260
PEB2055
Operational Description
Principles
Every time slot at the configurable interface is controlled by a control memory entry.
Thus, the functionality of every time slot may be chosen from the choices of table 1.
Table 1
CFI Time Slot Functionality Choices
Functionality
Application
Transparent
64 kbiVs
32kbiVs
16kbiVs
tolfrom PCM interface
·Switching
Transparent
64 kbiVs
from .... p interface
Idle code
Signaling channel bits 5 .. 2
10M CII channel
Signaling channel bits 7 .. 2
e.g. analog 10M channel
Signaling channel bits 7 .. 0
e.g. SLD signaling channel
MFFIFO channel
Monitor channel in 10M
Feature control channel in SLD
Every channel may be selected in either upstream or downstream direction. The selections
for the time slots are nearly independent of each other.
The only restriction is that MFFIFO and signaling channels must be programmed to adjacent
time slots, starting with the MFFIFO channel at the even time slot.
The choices of table 1 may be programmed independently of the selected mode.
By programming the time slots, the configurable interface may be configured e.g. as a
• transparent PCM interface (plain switching function)
• 10M interface
• SLD interface
Siemens Components, Inc.
261
PES 2055
Register Description*
The following symbols are used throughout this chapter
x...
don't care
u... used to ensure the intended function
n... not used. It has to be set to logical 0 in write accesses but may be switched by the
EPIC to either logical level in read accesses.
Table 2
Register Set
Group
nl"'l.l
rvlVI
CFI
MAR
Register
Name
Access
Reset
IJ.P Interface Mode
Write (WR)
Value
DEMUX.
Read (RD) MUX.
AD7 .. ADO A3 .. AO/RBS
Register Content
PMOD
PBNR
RD/WR
RDIWR
20H
22H
OH/1
1H/1
00
FF
POFD
RDiWR
24H
2H/1
00
POFU
RDIWR
26H
3H/1
00
PCSR
RDIWR
28H
4H/1
00
PICM
RD/WR
2AH
5H/1
-
PCM Mode Register
PCM Bit Number
Register
PCM Offset
Downstream Register
PCM Offset
Upstream Register
PCM Clock Shift
Register
PCM Input
Comparison
Mismatch Register
CMD1
CMD2
CBNR
RD/WR
RDIWR
RD/WR
2CH
2EH
30H
6H/1
7H/1
8H/1
00
00
FF
CTAR
RDIWR
32H
9 H/1
00
CBSR
CSCR
RDIWR
RDIWR
34H
36H
AH/1
BH/1
00
00
MACR
RDIWR
OOH
OHIO
-
MAAR
RD/WR
02H
1H/O
-
MADR
RDIWR
04H
2H/O
-
* For a detailed register description, refer to the EPIC Data Sheet 10/88
Siemens Components, Inc. :
262
CFI Mode Register 1
CFI Mode Register 2
CFI Bit Number
Register
CFI Time Slot
Adjustment Register
CFI Bit Shift Register
CFI Subchannel
Register
Memory Access
Control Register
Memory Access
Address Register
Memory Access
Data Register
PEB 2055
Group
STR
MFCH
SCR
Register
Name
Reset
Access
IJ.P Interface Mode
Write (WR)
Value
Read (RD) mux.
demux.
AD1 .. ADO A3 .. AO/RBS
STDA
RD/WR
06H
3 H/0
-
STDB
RD/WR
OBH
4H/0
-
SARA
RDIWR
OAH
5 H/0
-
SARB
RD/WR
OCH
6H/0
-
SAXA
RDIWR
OEH
7H/0
-
SAXB
RDIWR
10H
BH/O
-
SRCR
RD/WR
12H
9 H/0
00
MFAIR
RD
14H
AH/O
Undef.
MFSAR
WR
14H
AH/O
Undef.
MFFIFO
RDIWR
16H
BH/O
Empty
C/I FIFO
RD
1BH
CH/O
TIMR
STAR
CMDR
ISTA
WR
RD
WR
RD
1BH
1AA
1AH
1CH
CH/O
DH/O
DH/O
EH/O
Validity
0
00
05
00
00
MASK
OMDR
WR
RD/WR
1CH
1EH/3EH
EH/O
FH/X
00
00
VNSR
RD
3AH
DH/1
Register Content
Synchron Transfer
Data Register A
Synchron Transfer
Data Register B
Synchron Transfer
Receive Address
Register A
Synchron Transfer
Receive Address
Register B
Synchron Transfer
Transmit Address
Register A
Synchron Transfer
Transmit Address
Register B
Synchron Transfer
Control Register
MF Channel Actice
Indication Register
MFChannel
Subscriber Address
Register
MF Channel FIFO
Signaling Channel
FIFO
Timer Register
Status Register
Command Register
Interrupt Status
Register
Mask Register
Operation Mode
Register
Version Number
Register
Note: In the multiplexed IJ.P interface mode ADO is not used for address coding.
Siemens Components, Inc.
263
I
PEB 2055
Absolute Maximum Ratings
Symbol
Description
Limit Values
Ambient temperature under bias
TA
Oto 70
Storage temperature
Tstg
-65 to 125
Unit
°C
°C
DC Characteristics
TA = 0 to 70°C; Voo= 5 V, Vss= 0 V
Limit Values
Parameter
Symbol
min.
max.
Unit
L-input voltage
V,l
V,H
-0.4
0.8
V
Voo
V
H-input voltage
2.0
Test Conditions
+0.4
L-output voltage
VOL
H-output voltage
VOH
0.45
2.4
V
IOl=2 mA
V
I oH =-400 (.LA
V
IOH =-100 (.LA
Voo
H-output voltage
VOH
-0.5
Icc
Icc
9.5
6.5
mA
mA
Voo = 5 V, input at 0 V or
Voo , no output loads
clock frequency> 4096 kHz
clock frequency S; 4096 kHz
III
I lo
10
10
ILA
(.LA
oV < V,N < Voo to 0 V
oV< VOUT < Voo to 0 V
Operational power supply
current
Input leakage current
Output leakage current
Siemens Components, Inc.
264
PES 2055
Capacitances
TA = 25°C; Voo = 5 V, Vss = 0 V
Limit Values
Parameter
Symbol
Input capacitance
1/0 capacitance
Output capacitance
C IN
Cia
COUT
min.
max.
Unit
10
20
15
pF
pF
pF
AC Characteristics
Ambient temperature under bias range, Voo = 5 V ± 5%
Inputs are driven at 2.4 V for a logical 1 and at 0.4 V for a logical O. Timing measurements
are made at 2.0 V for a logical 1 and at 0.8 V for a logical O. The AC testing inpuVoutput
waveforms are shown below.
Figure 21
1/0 Waveform for AC Tests
2,4
2,0"
Device
Under
Test
2,0
Test Points/
0,8 /
"0,8
0,45
Siemens Components, Inc.
265
PES 2055
Microprocessor Interface Timing Parameters
Limit Values
Parameter
ALE pulse width
Symbol
min.
tAA
30
10
20
0
10
25
0
120
Address setup time to ALE
tAL
Address hold time form ALE
tLA
Address latch setup time to WR, RD
tALS
Address setup time to WR, RD
tAS
Address hold time from WR, RD
tAH
RD delay after WR setup
toso
RD pulse width
tRR
Data output delay from RD
t RO
Data float from RD
tRI
WR pulse width
tww
--
Data setup time to WR
+ CS
+ CS
tow
Data hold time from WR
two
WR control interval
tWI
Siemens Components, Inc.
70
60
30
10
70
266
Unit
ns
ns
ns
ns
ns
ns
ns
ns
100
25
tOF
RD control interval
max.
ns
ns
ns
ns
ns
ns
ns
PEB 2055
INTEL Bus Mode
j.J.p Read Cycle
,,-eo
~=J,",~
ADO-AD7
Data
j.J.P Write Cycle
Multiplexed Address Timing
Demultiplexed Address Timing
[SxWR
[SxRD
AO-A3
l=
(
-----"""1
=4,.,k:
~
Siemens Components, Inc.
Address
267
~
PEB2055
Motorola Bus Mode
j.Lp Read Cycle
ADO-AD?
Data
j.LP Write Cycle
R/W
CS+OS
~rc:,
~j
g,
~~"~
,,1two
ADO-AD?
Data
_ . _
Address Timing
CS.DS
AO-A?
.[
--L ~,l
~~-------~
_
Siemens Components, Inc.
268
PEB2055
Timing of PCM and Configurable Interfaces
Limit Values
Parameter
Symbol
max.
Unit
Conditions
240
80
100
ns
ns
ns
clock frequency
~4096 kHz
tcp
tCPL
tCPH
120
50
50
ns
ns
ns
clock frequency
>4096 kHz
Frame setup time
Frame hold time
tFs
tFH
15
50
ns
ns
Data clock delay time
toco
Serial data input
setup time
Serial data input hold time
ts
5
tH
35
ns
Serial data input
setup time
Serial data input hold time
ts
15
ns
tH
50
ns
Serial data input
setup time
Serial data input
ts
15
ns
tH
50
ns
Serial data input
setup time
Serial data input hold time
ts
0
ns
tH
75
PCM serial data
output delay time
to
55
ns
Tristate control delay
Clock period
Clock period low
Clock period high
tcp
tCPL
tCPH
Clock period
Clock period low
Clock period high
min.
125
ns
ns
ns
tT
60
ns
CFI serial data
output delay time
(falling clock edge)
tOF
60
ns
CFI serial data
output delay time
(rising clock edge)
tOR
80
ns
Siemens Components, Inc.
269
PCM input data
frequency
> 4096 kbit/s
PCM input data
frequency
~4096 kbiVs
CFI input data
frequency
> 4096 kbiVs
CFI input data
frequency
~4096 kbiVs
PEB 2055
AC Characteristics at the CFI with CMD: CSP 1.0 = 10 (Prescaler Divisor = 1)
""i.
X.
X
OO(CM02:CXF;O) _
-fJ~1
r------,.
r--1+----.l4 ts
'--_.....J '---I+----f~
X
1)
tH
X
2)
3)
'--~_J'-
-
r---T+----.I
-
1)
-fDr
_ __
( __-++---'I
X::f1
-n
fs
X
tH
:--
f{
J~f
$2
<..
0
c;
"
c:>
;;
~
u
;;
~
u
<:>
<:>
1)
'--
::."
0
~
u
c;
~
u
r-'---,
X
Last Bit of Frame
1st Bit of Frame
::."
>u
0
~
0
~
x.
OOK
((MD .. ".OOO::
1st Bit of Frame
~
~
~
1) 1st Bit of Frame; 2) 2nd Bit of Frame; 3) 3rd Bit of Frame; 4) Last Bit of Frame.
Siemens Components, Inc.
270
u
PEB2055
AC Characteristics at the CR with CMD: CSP 1.0 == 00 (Prescaler Divisor - 2)
x
DD(CMD2:CXF=OI
)(
I
x:
1)
X
21
31
l2
;--
~
0
} 0II
{
DU(CM02:CRR=OI
_.
C>
C)
X-
11
X
DO( CMD2: CXF=11 _ _...JX,'--_-+l...JX'--+-_I-'x:n:...-+-....;...w\.......~-..J
]
ts_
0
::f:
u
tH I~
)C
:{
DU(CMD2:CRR=11
'--
.+-
::f:
u
DD(CMD2: CXF=lI -:i....J\_ _ _ _-tl_--.,I-X,l\:--r1....
st...;Bo:.:irto
...f..:.F-T1raFrm:::..e-+1-''-_ _ _ _ __
.... ts
1+-.
--I tH 1-DU(CMD2 :CRR=OI -----cl=j--1--1t=1~1=li1----<==:J}
--tORr-
----y_..J,......._-++_-l_-l...J)t't...--i-!.1s_t...!:B~it....lO~f..!:F.!rlra~mi::.e-..J'--_ _ __
OD( CM02 :CXF=OI_
1 --rt
ts
DU(CMD2:CRR=1I
8II
0.
0
::f:
u
0
::f:
u
H
11
r'--,
-- tORrDD(CMD2: CXF=11 _ _.....:L:;;;as;.;.t...;;B;.;.it...;;of;,.,.;.;.Fr.;;.;am;;.;e+_-+'x:-,;;....-+-_ _-""-st~Biw..t.:::.l0f..!F~ra!!.Uml.::.e_ _ __
ts
DU(CMD2:CRR=OI
J+-
~
tH
r--
~
---.......:jt=4~1=)i--1--1-----------
DCLK
(CMD1 :Ox1000xxl
X
~
}
toet~_ _ _ _ _ _ _ _ __
111 st Bit of Frame;212 nd Bit of Frame; 313 rd Bit of Frame;4lLast Bit of Frame
Siemens Components, Inc.
::f:
u
::f:
u
--------+~~--+------------)
OCO- ·1 __
taco
FSC
C)
C)
-- tORrDD(CMD2: CXF=OI
:=
II
L
271
PEB 2055
AC Characteristics at the CR with CMD1 :CSP - 01 (Prescaler Divisor)
X
2)
3)
X
:;2
...
0
} ;;II
DDICMD2:CXF=1)
-=::f
__
>co~.
X
X
J'-_-+t--J
11
u
~
u
ts_r,- tH
}{
DUICMD2:CRR=1)
DDICMD2: CXF=1)
:I:
X
1)
}{
J
Y
X
1st Bit of Frame
X
-~-------#----~~--~~~~~~~-----------
~ ts ltH~
DUICMD2:CRR=O)
r-
-::::::x
___,,'-__-#____-+--+..-J)t~+__!l:....st~B~it...::O~f
-
DDICMD2:CXF=O)
=>ii-------{==:=)>
------
"
RxO(PCSR:ORE=O)
IX
u
a.
D
o
TxO(PCSR:URE=O)
_ _.J\_ _ _J
TSC(PCSR: URE =0)
_ _..J
:F-
a.
RxO(PCSR:ORE=l)
TxO(PCSR:URE=l)
TSC(PCSR:URE=1)
RxO(PCSR :ORE=O)
------1===)--+--~=}[=1t_-----C==)
"
IX
u
a.
D
TxO(PCSR :URE=O)
o
:Fa.
---'
TS((PCSR:URE=O)
--"""'\J-------~Jr--_;_--_t+-___. ,..------1
RxO(PCSR:ORE=1l
"------c=>--j
==:J(
)
-{
1) 1st Bit of Frame
2) 2nd Bit of Frame
3) 3 rd Bit of Frame
Siemens Components, Inc.
273
~1) tHJ..~____ ~r-!
~J
j--
SIEMENS
Extended PCM Interface Controller (EPlC-2)
Preliminary Data
PEB 2056
CMOSIC
Type
Ordering Code
Package
PE82056-C
PE82056-N
PEB 2056-P
Q67100-H6117
Q67100-H6116
Q67100-H6115
C-DIP-28
PL-CC- 44 (SMD)
P-DIP-28
The EPICTM-2 is a smaller version of the EPICTM-1. The functions that are performed remain
essentially the same but the EPIC-2 has been optimized for time-slot assignment and
switching functions on line cards with up to 8 ISDN subscriber lines:
EPICTM-1:
410M® interfaces
4 PCM highways
EPICTM-2:
1 IOM® interfaces
2 PCM highways
Up to 32 ISDN subscribers
Up to 8 ISDN subscribers
P-DIP-40/PL-CC-44 packages
P-DIP-44/PL-CC-44 packages
Features
•
•
•
•
•
•
•
•
•
•
PCM interface controller for up to 8 ISDN or 16 analog subscribers
Time-slot assignment freely programmable for all subscribers
Non-blocking switch for 24 channels (168 + 80)
Switching of 16 and 64 kbiVs channels
Two serial interfaces: PCM and IOM®-2
Interfacing to two full duplex PCM highways (1.5, 2 or 4 MbiVs)
Change detection ("last-look") logic for C/I channel
Buffering for monitor channel
Standard paraliellJ.P interface
Advanced low power CMOS technology
Siemens Components, Inc.
274
PEB 2056
8 ISDN Subscribers per PCM Interface Controller (EPlC-2)
r---,
EPI[TM_2
HSCX
(Opt.)
Siemens Components, Inc.
275
PCM HOLC
Hwys. Hwy.
SIEMENS
ISDN Communication Controller (ICC)
Preliminary Data
CMOSIC
Type
Ordering Code
PEB 2070-C
067100-H8328
"~i;i~ili.
r{0Jti~:'1if~~*'10~Z~.;j?\:~s?« F... ~
%<'''
PEB 2070-P
PEB2070
.
'"
Package
C-DIP-24
.i0~'~"~.:._ _ __
~%:iQ
067100-H2953
P-DIP-24
The transmission and protocol functions in an ISDN basic access can all be implemented
using the CMOS circuits of the ISDN Oriented Modular (IOM® -1) chip set. While three chips,
the S Bus interface Circuit SBC (PEB 2080), the ISDN Echo Cancellation circuit IEC
(PEB 2090) and the ISDN Burst Controller IBC (PEB 2095) perform the transmission functions
in different applications (8- and U-Inteiface), the ISDN Communication Controller ICC
(PEB 2070) acts as the D-channel-link-access protocol controller.
The 10M architecture makes possible a wide range of configurations for the basic access,
using the basic devices. These configurations essentially differ in the implementation of the
layer-1 OSI functions, while the layer-2 functions are provided by the ICC for all configurations.
In addition to that, the PEB 2070 provides the interface to B-channel sources in the terminal
and to a peripheral board controller (PEB 2050, 51, 52 etc.) at the exchange.
The HDLC packets of the ISDN D channel are handled by the ICC which transfers them to
the associated microcontroller. The ICC has on-chip buffer memories (64 bytes per direction)
for the temporary storage of data packets. Because of the overlapping I/O operations the
maximum length of the D-channel packets is not limited. In one of its operating modes the
device offers high level support of layer-2 functions of the LAPD protocol.
A side from ISDN applications, the ICC can be used as a general purpose communication
controller in all applications calling for LAPO, LAPB or other HOLC/SOLC based protocols.
276
PEB 2070
Features
•
•
•
•
Support of LAPD protocol
Different types of operating modes for increased flexibility
FIFO buffer (2 x 64 bytes) for efficient transfer of data packets
Serial Interfaces: IOM-1, SLD, SSI
IOM-2
• General purpose HDLC communication interface
• Implementation of IOM-1/10M-2 monitor and CII channel protocol to controllayer-1 and
peripheral devices
• D-channel access with contention resolution mechanism
• IJ.P access to B channels and intercommunication channels
• B-channel switching
• Watchdog timer
• Testloops
• Advanced CMOS technology
• Low power consumption: active
: 17 mW (IOM-2)
8 mW (IOM-1)
standby : 3 mW
Logic Symbol
SSI
{
(Serial Port A)
SLO{
OV
+5V
SOAX/SOS1
SOAR
SIP/EAW
lOP 0
(Serial Port B)
OCLK
«,,'
IF"., {
Synchronization
lOP 1
FSC
SCAlFS01SOS 2
CS
Siemens Components, Inc.
}OM®
WR
RO
(RfW) (oS)
277
TNT ALE
PEB 2070
Pin Configuration
(top view)
P-DIP-24
PL-CC-28
~Ln::;;;;N
AD4
99999
AD3
\OUl...:t",N
00000
ADS
AD2
AD6
AD1
«««««
3 2 1 28 27
AD7(o7)
A1
SDAR/A2
SDAX/SDS1
SCAlFSD/SDS2
ADO
RD
SDAX/SDS1
SCA/FSD/SDS2
PES 2070
WR
ICC
6
7
8
26
AD 1(01)
ADO(OO)
RD(~)
PES 2070
ICC
WR(R/W)
Voo
LS
FSC
A3
A4
Voo
RES
0
ALE
19 AO
INT
CS
LI1
FSC
ALE
SIP/EAW
INT
DCLK
IOPO
Vss
IOP1
~
til
or-
0
«-'~a..a..
__
3
0
...... : u
DO
«LLI
a:
Vi
Pin Definitions and Functions
Pin No.
P-DIP
Pin No.
PL-CC
Symbol
Input (I)
Function
Output (0)
21
22
23
24
1
2
3
4
25
26
27
28
1
2
3
4
ADO/DO
AD1/D1
AD2/D2
AD3/D3
AD4/D4
AD5/D5
AD6/D6
AD7/D7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Multiplexed Bus Mode: Address/Data bus.
Transfers addresses from the IJ.P system to
the ICC and data between the IJ.P system and
the ICC.
Non Multiplexed Bus Mode: Data bus.
Transfers data between the IJ.P system and
the ICC.
17
21
CS
I
Chip Select. A "Low" on this line selects the
ICC for a read/write operation.
Siemens Components, Inc.
278
PEB 2070
Pin Definitions and Functions (cont'd)
Pin No.
P-DIP
Pin No.
PL-CC
Symbol
Input (I)
Output (0)
Function
-
23
R/W
I
19
23
WR
I
Read/Write. When "High", identifies a vaild IlP
access as a read operation. When "Low",
identifies a valid IlP access as a write operatiorT (Motorola bus mode).
Write. This signal indicates a write operation
(Siemens/Intel bus mode).
-
24
DS
I
20
24
RD
I
15
18
INT
OD
Interrupt Request. The signal is activated
when the ICC request an interrupt. It is an
open drain output.
16
20
ALE
I
Address Latch Enable. A high on this line
indicates an address on the external address
bus (Multiplexed bus type only).
7
8
SCA
0
7
8
FSD
0
7
8
SDS2
0
Serial Clock Port A, IOM-1 timimg mode. A
128-kHz-data clock signal for serial portA (SSI).
Frame Sync Delayed, IOM-1 timing mode 1.
An 8-kHz-synchronization signal, delayed by
1/8 of a frame, for IOM-1 is supplied. In this
mode a minimal round-trip delay for 81 and 82
channels is guaranteed.
Serial Data Strobe 2, IOM-2 mode. A programmable strobe signal, selecting either one
or two 8 or IC channels on IOM-2 interface,
is supplied via this line.
After reset, SCAlFSD/SDS2 takes on the
function of SDS2 until a write access to SPCR
is made.
8
9
RES
I/O
Siemens Components, Inc.
Data Strobe. The rising edge marks the end
of a valid read or write operation (Motorola
bus mode).
Read. This signal indicates a read operation
(Siemens/Intel bus mode).
Reset. A "High" on this input forces the ICC
into reset state. The minimum pulse length is
four clock periods.
If the terminal specific functions are enabled,
the ICC may also supply a reset signal.
279
PEB 2070
Pin Definitions and Functions (cont'd)
Pin No.
P-DIP
Pin No.
PL-CC
Symbol
Input (I)
Output (0)
Function
9
10
FSC
I
Frame Sync.
Input synchronization signal.
IOM-2 mode: Indicates the beginning of 10M
frame.
IOM-2 mode: Indicates the beginning of 10M
and, if TSF = 0, frame (timing
mode 0).
Indicates the beginning of SLO
frame (timing mode 1).
HOLC mode: Strobe signal of programmable
polarity
11
14
OCLK
I
Data Clock.
10M modes:
HOLC mode:
Clock of frequency equal to
twice the data rate on the 10M
interrace.
Clock of frequency equal to
the data rate. on serial port B.
19
AO
I
Address bit 0 (Non-multiplexed bus type).
5
A1
I
Address bit 1 (Non-multiplexed bus type).
6
6
A2
SOAR
I
I
Address bit 2 (Non-multiplexed bus type).
Serial Data Port Receive.
Serial data is received on this pin at standard
TIL or CMOS level. An integrated pull-up
circuit enables connection of an open-drain/
open collector driver without an external pullup resistor. SOAR is used only if IOM-1 mode
is selected.
11
A3
I
Address bit 3 (Non-multiplexed bus type).
12
A4
I
Address bit 4 (Non-multiplexed bus type).
10
13
13
A5
SIP
I
I/O
10
13
EAW
I
Address bit 5 (Non-multiplexed bus type).
SLO Interface Port, IOM-1 mode. This line
transmits and receives serial data at standard
TIL or CMOS levels.
External Awake (terminal specific function).
If a falling edge on this input is detected,
the ICC generates an interrupt and, if enabled,
a reset pulse.
6
Siemens Components, Inc.
280
PEB2070
Pin Definitions and Functions (cont'd)
Pin No.
P·DIP
Pin No.
PL-CC
Symbol
Input (I)
Function
Output (0)
6
7
SDAX
0
6
7
SDS1
0
12
15
Vss
Ground (0 V)
18
22
Voo
-
14
13
17
16
IDPO
IDP1
I/O
I/O
10M Data Port 0, 1
Serial Data Port A transmit, IOM-1 mode.
Transmit data is shifted out via this pin at
standard TTL or CMOS levels.
Serial Data Strobe 1, IOM-2 mode. A programmable strobe signal, selecting either one or
two B or IC channels on IOM-2 interface, is
supplied via this line.
After reset, SDAXlSDS 1 takes on the function
of SOS 1 until a write access to SPCR is
made.
Power supply (5 V ± 5%)
Block Diagram
SSI
Serial
Port A
B ClKinnel
Interface
SLO
I
I
I
SIP
L-._~~"""
pP Interface
Siemens Components, Inc.
281
,.----,/1
(Serial
Port B)
PEB 2070
System Integration
ISDN Applications
The reference model for the ISDN basic access according to CCITT I series recommendations
consists of
an exchange and trunk line termination in the central office (ET, LT)
a remote network termination in the user area (NT)
a two-wire loop (U interface) between NT and LT
a four-wire link (S interface) which connects subscriber terminals and the NT in the user
area as depicted in figure 1.
Figure 1
ISDN Subscriber Basic Access Architecture
ISDN
ISDN
User Area
I TE
I
I
I
I
I
I
I
TE
r-
Central Office
u
S
I
I
I
I
-
I
I
I
I
I
I
NT
NT1
,
I
\
"
~
IT
LT
I
I
I
ET
The NT equipment serves as a converter between the U interface at the exchange and the
S interface at the subscriber premises. The NT may consist of either an NT1 only or an NT 1
together with an NT2 connected via the T interface which is physically identical to the S interface. The NT1 is a direct transformation between layer-1 of Sand layer-1 of U. NT2 may
include higher level functions like multiplexing and switching as in a PBX.
Siemens Components, Inc.
282
PEB 2070
In terms of channels the ISDN access consists of:
• a number of 64 kbiVs bearer channels (n x B)
e.g. n = 2 for basic rate ISDN access
n = 30 or 23 for primary rate ISDN access;
• and a signaling channel (D), either 16 (basic rate) or 64 (primary rate) kbiVs.
Figure 2
ISDN Basic Access Channel Structure
Layer 3 and Up
I
Layer 2
Layer 1
Layer 2
ISDNNetwork
ISDN
User
Terminals
I
I
I
I
I
Mainframe
D
I
I
I
I
I
I
I
I
I
I
I
Q.930/1
Q.920/1
Q.910/1;I.430
1.431
I
I
The B channels are used for end-to-end circuit switched digital connections between
communicating stations.
The D channel is used to carry signaling and data via protocols defined by the CCITI. These
protocols cover the network services layers of the open system interconnection model
(layers 1-3). At layer-2, the data link layer, an HDLC type protocol is employed, the Link
Access Procedure on the D channel LAPD (CCITI Rec. Q.920/1).
Siemens Components, Inc.
283
PEB2070
The ISDN communication controller PEB 2070 can be used in all ISDN applications involving
establishment and maintenance of a data link connection in either the D channel or B channel.
It also provides the interface to layer-1 functions controlled via the 10M which links the ICC
to any transceiver or peripheral device. Depending on the interface mode, the ICC supports
three serial interfaces and offers switching functions and IJP access to voice/data channels.
The applications comprise:
Use as a signaling controller for the D channel
Access to the D channel for data transmission
Source/sink for secured B channel data
and the target equipment include:
ISDN terminal
ISDN PBX (NT2) and Central Office (ET) line card
ISDN packet switches
"Intelligent" NT1.
Terminal Applications
The concept of the ISDN basic access is based on two circuit-switched 64-kbitls B channels
and a message oriented 16-kbitls D channel for packetized data, signaling and telemetry information.
Figure 3 shows an example of an integrated multifunctional ISDN terminal using the ICC.
The transceiver provides the layer-1 connection to the transmission line, either an S or aU
interface, and is connected to the ICC and other, peripheral modules via the 10M interface.
The D channel, containing signaling data and packet switched data, is processed by the ICC
LAPD controller and routed via a parallel IJP interface to the terminal processor. The high
level support of the LAPD protocol which is implemented by the ICC allows the use of a low
cost processor in cost sensitive applications.
The 10M interface is used to connect diverse voice/data appl'ication modules:
sources/sinks for the D channel
-
sources/sinks for the B1 and B2 channels.
Siemens Components, Inc.
284
PEB 2070
Figure 3
Example of ISDN Voice/Data Terminal
~ ~ fIc1\ ~ frC2\
[
SBCX
PEB2080
IBCPEB2095
ICC
rcc
PEB 2070
PEB 2070
Speech
Processing
ARCOFr@
PSB 2160
or
[ IEC PEB 2090
"-
~
~
7
~
s Packets
~
I I
HSCX
SAB B252x
"-
;..
~
7'
p Packets
.z
~C
~C
I
r
Data
Encryption
rOM ®
R
~C
I
Terminal Controller Packet Data
Speech Modules
Data Modules
Different D channel services (for different SAPI's) can be simply implemented by connecting
an additional ICC in parallel to the first one, for instance for transmitting p-packets in the D
channel.
Up to eight ICCs may thus be connected to the D and C/I (Command/Indication) channels.
The ICCs handle contention autonomously.
Data transfers between the terminal controller and the different modules are done with the
help of the 10M monitor channel protocol. Each voice/data module can be accessed by an
individual address. The same protocol enables the control of terminal modules that do not
have an associated microcontroller (such as the Audio Ringing Codec Filter ARCOFI@: PSB
2160) and the programming of intercommunication inside the terminal. Two intercommunication channels IC1 and IC2 allow a 2 x 64 kbiVs transfer rate between voice/data modules.
In the example above (figure 3), one ICC is used for data packets in the D channel. A voice
processor is connected to a programmable digital signal processing codec filter via IC1 and a
data encryption module to a data device via IC2. B1 is used for voice communication, B2 for
data communication.
The ICC ensures full upward compatibility with IOM-1 devices. It provides the additional
strobe, clock and data lines for connecting standard combos or data devices via 10M, or
serial SLD and SSI interfaces. The strobe signals and the switching of B channels is programmable.
Siemens Components, Inc.
285
PEB 2070
Line card Applications
An example of the use of the ICC on an ISDN LT + ET line card (decentralized architecture)
is shown in figure 4.
The transceivers (ISDN Echo Cancellation Circuit IEC: PES 2090) are connected to an Extended PCM interface Controller (EPIC PES 2055) via an 10M interface.
This interface carries the control and data for up to eight subscribers using time division
multiplexing. The ICCs are connected in parallel on 10M, one ICC per subscriber.
The EPIC performs dynamic Sand 0 channel assignment on the PCM highways. Since this
component supports four 10M intertaces, up to 32 subscribers may be accommodated.
Other Applications
If programmed in non-ISDN mode, the ICC serial port S operates as an HOLC communication
link without 10M frame structure. This allows the use of the ICC as a general purpose communication controller. The valid HOLC data is marked by a strobe Signal on serial port S.
Examples of the use of the ICC are: X.25 packet controllers, terminal adaptors, and packet
transmission e. g. in primary rate/OMI systems.
Figure 4
ISDN Line Card Implementation
PEB 2070
ICC
Ulntert;J
I
PEB 2090
IEC
I
I PCMHWO
III
::J
B+O
III
u
'4
II
U Intert;J
-
I
:..
L.
~
:
PEB 2090
IEC
Syste m
Inter tace
II
C\
V
0ct=r -
I
I I
_
PCM HW1
PEB 2055
EPIC ™
PEB 2070
ICC
o~~
1
. -G
"I
flP
SAB 82520
HSCC or
SAB 82525
HSCX
,
I
PCM HWO
I
i PCMHW1
I
Siemens Components, Inc.
286
PEB 2070
Microprocessor Environment
The ICC is especially suitable for cost-sensitive applications with single-chip microcontrollers
(e.g. 8048, 8031, 8051). However, due to its programmable micro interface and non-critical
bus timing, it fits perfectly into almost any 8-bit microprocessor system environment. The
microcontroller interface can be selected to be either of the Motorola type (with control
signals CS, R/W, OS), of the Siemens/Intel non-multiplexed bus type (with control signals
CS, WR, RD) or of the Siemens/Intel multiplexed address/data bus type ((:S, WR, RD, ALE).
Figure 5
Example of ICC Microcontroller Environment
SLD
SSI
+5V
mT(lNTX)
80CS1,
(80C188)
RD
WR
ALE
(PSCX)
INT
RD
WR
ALE
1m
WR
ALE
--------
A15
AS
----
ADO
Memory
Siemens Components, Inc.
287
ICC
PEB 2070
PEB 2070
Functional Description
General Functions and Device Architecture
Figure 6
Architecture of the ICC
OCLK
FSC
Timing Unit
IPOO
IPO 1
SOAR
B Channel
switching
IOM®
(Serial
Port B)
SOAX/SOS1
SCAlFSO/SO
SIP/EAW
HOLC
Receiver
: HOLC
I Transmitter
LAPO
Controller
Status/
Command
Registers
R FIFO
2" 32 byte
X FIFO
2,,32 byte
FIFO
Controller
RES
Vss
Voo
AOO-A07
(00-07)
WR(R/W)
(AO-AS)
Siemens Components, Inc.
288
ALE
PEB 2070
The functional block diagram in figure 6 shows the ICC to consist of:
serial interface logic for the 10M, SLD and SSI interfaces with B channel switching
capabilities
logic necessery to handle the D channel messages (layer 2).
The latter consists of an HDLC receiver and an HDLC transmitter together with 64-byte deep
FIFO's for efficient transfer of the messages tolfrom the user's CPU.
In a special HDLC controller operating mode, the auto mode, the ICC processes protocol
handshakes (1- and S-frames) of the LAPD (Link Access Procedure on the D channel) autonomously.
Control and monitor functions as well as data transfers between the user's CPU and the D
and B channels are performed by the a-bit parallel j.J.P interface logic.
The 10M interface logic allows interaction between layer-1 and layer-2 functions. It implements D-channel collision resolution for connecting other layer-2 devices to the 10M interface, and the CII and monitor channel protocols (IOM-1/10M-2) to control peripheral devices.
The timing unit is responsible for the system clock and frame synchronization.
Serial Interface Modes
The PEB 2070 can be used in different modes of operation:
• IOM-1 Mode
• IOM-2 Mode
• HDLC Controller Mode.
These modes are selected via bit IMS (Interface Mode Select) in ADF2 register and bits
DIM 2-0 (Digital Interface Mode) in MODE register. See table 1.
Table 1
Interface Modes
IMS
DIM2
Mode
0
0
IOM-1 Mode
1
HDLC Mode
X
IOM-2 Mode
1
Siemens Components, Inc.
289
PEB 2070
10M 1 Mode (IMS ... 0, DIM2 == 0)
Serial Port B is used as the IOM-1 interface, which connects the ICC to alayer-1 component.
The HOLC controller is always connected to the 0 channel of IOM-1 interface.
Two additional serial interfaces are available in this mode, the Synchronous Serial Interface
SSI (serial port A) and the Subscriber Line Oatalink (SLO) interface.
The SSI is used especially in ISDN terminal applications for the connection of B channel
sources/sinks. It is available if timing mode 0 (bit SPM = 0, SPCR register) is programmed.
The SLD is used:
-
in ISDN terminal applications for the connection of SLO compatible B channel devices
in line card applications for the connection of a peripheral line board controller (e.g.
PEB 2050).
The connections of the serial interfaces in both terminal and exchange applications are
shown in figure 7.
The-SSI interface is only available in timing mode 0 (SPM = 0). Timing mode 1 (SPM = 1) is
only applicable in exchange applications (figure 7b) and is used'to minimize the B channel
round-trip delay time for the SLD interface. Refer to section ISDN Oriented Modular Interface.
Figure 7
ICC Interface in IOM-1 Mode
ISDN
Basic Access
S or U Interface
I
I
I
I
I
I
I
I
IOM®
I
SBC PEB 2080
or
IBC PEB 2095
or
IEC PEB 2090
I
I
I IOPO
I IOP1
IOM®
I
I
I
FSC
OCLK
101 Timing Mode OISPM=OI
ISDN
Basic Access
S or U Interface
SBC PEB 2080
or
IBC PEB 2095
or
IEC PEB 2090
System
Interface
ICC
,------...,
:
I
Peripheral
Board Controller
PEB 2050/52155
lOP 1
I
I
I
I
I
'--....-...-.---' I
I
System Clock
Sync Pulse
F.SO
I bl Timing Mode 1 ISMP= 11
Siemens Components, Inc.
290
PEB 2070
The characteristics of the 10M interface are determined by bits DIM 1, 0 as shown in
table 2.
Table 2
IOM-1 Interface Mode Characteristics
DIM1
DIMO
Characteristics
o
o
o
Monitor channel upstream is used for TIC bus access.
Monitor channel upstream is used for TIC bus access. Bit 3 of
monitor channel downstream is evaluated to control D-channel
transmissions.
o
Monitor channel is used for TIC bus access and for data
transfer.
Monitor channel is use-d for TIC bus access, for data transfer
and for D-channel access control.
IOM-2 Mode (IMS = 1)
Serial port B is operated as an IOM-2 interface for the connection of layer -1 devices,
and as a general purpose backplane bus in terminal equipment. The auxiliary serial SSI
and SLD interfaces are not available in this case.
The functions carried out by the 10M are determined by bits SPM (terminal mode/non
terminal mode) and DIM2-0, as shown in table 3.
Table 3
IOM-2 Interface Mode Characteristics
DIM2
DIM1
DIMO
Characteristics
HDLC in D channel:
000
Last octet of 10M channel 2 is used for TIC bus access.
Applicable in terminal mode (SPM = 0).
o
Last octet of 10M channel 2 is used for TIC bus access,
bit 5 of last octet is evaluated to control D-channel transmission.
Applicable in terminal mode (SPM = 0).
o
o
o
No TIC bus access and no S bus D-channel access control.
Applicable in terminal and non-terminal mode.
o
Bit 5 of last octet is evaluated to control D-channel transmission.
Applicable in terminal mode (SPM = 0).
HDLC in B or IC channel:
1
1
0
No transmission/reception in D channel.
HDLC channel selected by D1 C2-0.
Note:
In IOM-2 terminal mode (SPM = 0, 12-byte IOM-2 frame), all DIM2-0 combinations
are meaningful. When IOM-2 non-terminal mode is programmed (SPM = 1),
the only meaningful combination is "10".
Siemens Components, Inc.
291
PEB2070
HDLC Controller Mode (IMS = 0, DIM2 = 1)
In this case serial port B has no fixed frame structure, but is used as a serial HOlC port.
The valid HOlC data is marked by a strobe signal input via pin FSC. The data rate is
determined by the clock input OCl (maximum 4096 MbiVs). The characteristics of the serial
port B are determined by bits OIM1, 0 as shown in table 4.
Table 4
HDLC Mode Characteristics
DIM1
DIMO
Characteristics
o
o
o
reserved
FSC strobe active low
o
FSC strobe active high
FSC strobe ignored
Interfaces
The ICC serves three different user-oriented interface types:
parallel processor interface to higher layer functions
10M interface: between layer 1 and layer 2, and as a universal backplane for terminals
SSI and SlO interfaces for B channel sources and destinations (in IOM-1 mode only).
IJ.P Interface
The ICC is programmed via an 8-bit parallel microcontroller interface. Easy and fast microprocessor access is provided by 8-bit address decoding on chip. The interface consists
of 13 (18) lines and is directly compatible with multiplexed and non-multiplexed microcontroller interfaces (Siemens/Intel or Motorola type buses). The microprocessor interface
signals are summarized in table 5.
Siemens Components, Inc.
292
PEB 2070
TableS
IJ.P Interface of the ICC
Symbol
Input (I)
Function
Output (0)
25
26
27
28
1
2
3
4
ADO/DO
AD1/D1
AD2/D2
AD3/D3
AD4/D4
AD5/D5
AD6/D6
AD7/D7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Multiplexed Bus Mode: Address/Data bus.
Transfers addresses from the IJ.P system to
the ICC and data between the IJ.P system
and the ICC.
Non-Multiplexed Bus Mode: Data bus.
Transfers data between the IJ.P system and
the ICC.
17
21
CS
I
Chip Select A 0 ("low") on this line selects
the ICC for a read/write operation.
-
23
RIW
I
19
23
WR
I
ReadlWrite. At 1 ("high"), identifies a valid
IJ.P access as a read operation. At 0, identifies
a valid IJ.P access as a write operation
(Motorola bus mode).
Write. This signal indicates a write operation
(Siemens/lntel bus mode).
-
24
OS
I
Pin No.
P-DIP
Pin No.
21
22
23
24
1
2
3
4
PL-CC
Data Strobe. The rising edge marks the end
of a valid read or write operation (Motorola
bus mode).
Read. This signal indicates a read operation
(Siemens/lntel bus mode).
20
24
RD
I
15
18
INT
00
Interrupt Request The signal is activated when
the ICC requests an interrupt. It is an open
drain output.
16
20
ALE
I
Address Latch Enable. A high on this line
indicates an address on the external address
bus (Multiplexed bus type only).
19
AO
I
Address bit 0 (Non-multiplexed bus type).
5
A1
I
Address bit 1 (Non-multiplexed bus type).
6
A2
I
Address bit 2 (Non-multiplexed bus type).
11
A3
I
Address bit 3 (Non-multiplexed bus type).
12
A4
I
Address bit 4 (Non-multiplexed bus type).
13
A5
I
Address bit 5 (Non-multiplexed bus type).
Siemens Components, Inc.
293
PEB 2070
ISDN Oriented Modular (IOM-1) Interface
IOM-1
This interface consists of one data line per direction (10M Data Ports 0 and 1: IDPO,1).
Three additional signals define the data clock (DCl) and the frame synchronization (FSC/FSD)
at this interface. The data clock has a frequency of 512 kHz (twice the data rate) and the
frame sync clock has a repetition rate of 8 kHz.
Via this interface four octets are transmitted per 125I-Ls frame (figure 8):
The first two octets constitute the two 64 kbitls B channels.
The third octet is the monitor channel. It is used for the exchange of data using the
IOM-1 monitor channel protocol which involves the E bit as a validation bit. In addition,
it carries a bit which enables/inhibits the transmission of HDlC frames (IDPO) and it
serves to arbitrate the access to the last octet (IDP1).
The fourth octet is called the Telecom IC (TIC) bus because of the offered busing
capability. It is constituted of the 16 kbitls D channel (2 bits), a four-bit Command/
Indication channel and the T and E bits. The C/I channel serves to control and monitor
layer-1 functions (e.g. activation/deactivation of a transmission line .. ). The T bit is a
transparent 8 kbitls channel which can be accessed from the ICC, and the E bit is used
in monitoi byte transfer.
Siemens Components, Inc.
294
PEB2070
Figure 8
IOM®-1 Frame Structure
- - - - - - - - - - - 1 2 5 f l S - - - - - - - - - o..
-
,Bits
.
8
.,.
8
.,.
8
Frome
I
Bl
B2
,
Monii"or
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I 0 I c/l
I
I
I
I
I
I
I
I
I
I
I
I TIE
I I
I
I
I
I
I
I
,
IOM®
I
Loyer 2 I Loyer 1
L_
L __
-<
<
<
L ______
L _________
: 8kbit/S)
I
: Bkbit/S)
I
TIC Bus
,
l32kbiliV
: 16kbit/S)o_Channel
I
}MonitorL----------.----<=t~
Channel
I
,
,
L - - - - - - - - - - _.. - ..- -. - - - - - - - - - - --<=Jr~
,
.<
L __________________. __
I
:64kbitli>
}-
Channels
TIC Bus and Arbitration via Monitor Channel
The arbitration mechanism implemented in the monitor channel allows the access of more
than one (up to eight) ICC to the last octet of 10M (TIC). This capability is useful for the
modular implementation of different ISDN services (different service access points) e.g. in
ISDN voice/data terminals. The IDP1 pins are connected together in a wired-or configuration,
as shown in figure 8.
Siemens Components, Inc.
295
I
PEB 2070
Figure 9
10M Bus (TIC Bus) Configuration
ICC
IPD 1
IPDO
FSC DCLK -
ISDN Basic
Access S or
U Interface
I
I
I
ICC
I
Layer 1
SBC,IBC
or IEC
or
Layer 1+ 2
ISAC™-S or ISAC™-9
IPD 1
IPD 0
FSC f----------'
DCLK f----------
I
I
I
I
I
I
The arbitration mechanism is described in the following.
An access request to the TIC bus may either be generated by software (J.1P access to the
CII channel) or by the ICC itself (transmission of an HOLC frame). A software access request
to the bus is effected by setting the BAC bit (CIXR/CIXO register) to "1 ".
In the case of an access request, the ICC checks the bus accessed-bit (bit 3 of IOP1
monitor octet, see figure 10) for the status "bus free", which is indicated by a logical "1 ".
If the bus is free, the ICC transmits its individual TIC bus address programmed in STCR
register. The TIC bus is occupied by the device which is able to send its address error-free.
If more than one device attempt to seize the bus simultaneously, the one with the lowest
address value wins.
Figure 10
Monitor Channel Structure on IDP1
7
6
5
3
4
[
o
2
~IC Bus Add:ess TBA2-~
Bus accessed = "1" (no TIC bus
access) if
- BAC = 0 (CIXR/CIXO
register) and
- no HOLC transmission
is in progress
Siemens Components,lnc.
296
PES 2070
When the TIC bus is seized by the ICC, the bus is identified to other devices as occupied
via the IOP1 monitor channel bus accessed bit state "0" until the access request is withdrawn. After a successful bus access, the ICC is automatically set into a lower priority class,
that is, a new bus access cannot be performed until the status "bus free" is indicated in
two successive frames.
If none of the devices connected to the 10M interface request access to the 0 and CII
channels, the TIC bus address 7 will be present. The device with this address will therefore
have access, by default, to the 0 and CII channels.
Bit BAC (CIXR/CIXO register) should be reset by the ~P when access to the CII
channel is no more requested, to grant other devices access to these channels.
Note
Monitor channel
When the ICC is used in connection with an S interface layer-1 transceiver, an indication
must be given to the ICC whether the 0 channel is available for transmission (TE applications
with short passive or extended bus configuration).
This indication is assumed to be given in bit 3 "Stop/Go" (S/G) of the monitor input channel
on IOPO (figure 11). When a HOLC frame is to be transmitted in the 0 channel, the ICC
automatically starts, proceeds with, or stops frame transmission according to the S/G bit
value:
Figure 11
Monitor Channel Structure on IDPO
S/G = 1: stop
S/G=O: go
7
6
5
4
3
2
o
S/G
IOM-1 Timing
In IOM-1 mode, the ICC may be operated either in timing mode 0 or timing mode 1. The
selections is via bit SPM in SPCR register.
Timing mode 0 (SPM = 0) is used in terminal applications. Timing mode 1 (SPM = 1) is
only meaningful in exchange applications when the SLO is used. Programming timing mode 1
minimizes the B channel round-trip delay time on the SLO interface.
In timing mode 0 the 10M frame begin is marked by a rising edge on the FSC input.
It simultaneously marks tthe beginning of the SLO frame (figure 11).
In timing mode 1 the 10M frame begin is marked by a rising edge on FSO output. The
FSO output is delayed by the ICC by 1/8 th of a frame with respect to FSC (figure 12).
Siemens Components, Inc.
297
PEB 2070
Figure 12
Interface Timing in IOM-1 Mode
nnnnnnnnnnnnnnnnnnnn
DCLK (I)
(512 kHz) IUUUUUUUUUUUUUUUUUUUL ......... .
FSC (I)
(8kHz)
\\\\\\
\\\L
125 fJs
SLD OUT
SIP
B1
I
I
B2
SLD IN
I
I
I
I
B1
B2
I
I
I
TIC
loM®Frame
I DP 0/1
I
B1
I
B2
Monitor
SSI Frame
SOARISOAX
B_2_ _ _ _....L._ _ _ _B;.,.1_ _ _ _..J
L . . 1_ _ _ _
(a) Timing Mode 0
OCLK (I)
(512 kHz)
..........
\\\\\L
\\\\\\
FSC (I)
125 fJs
,......--
I
FSO(O)
11 B Frame Period
SLO OUT
SIP
B1
B2
I
SLO IN
I
I
I
B1
I
T
I
Monitor
I
B2
IOM®Frame
lOP 0/1
B1
I
B2
I
(b) Timing Mode 1
Siemens Components, Inc.
298
TIC
PEB 2070
IOM-2
The IOM-2 is a generalization and enhancement of the IOM-1. While the basic frame structure
is very similar, IOM-2 offers further capacity for the transfer of maintenance information.
In terminal applications, the IOM-2 constitutes a powerful backplane bus offering intercommunication and sophisticated control capabilities for peripheral modules.
The channel structure of the IOM-2 is depicted in figure 13:
Figure 13
Channel Structure of IOM-2
81
82
Monitor
o
C/I
MR
MX
• The first two octets constitute the two 64 kbiVs 8 channels.
• The third octet is the monitor channel. It is used for the exchange of data between the
ICC and the other attached device(s) using the IOM-2 monitor channel protocol.
• The fourth octet (control channel) contains
two bits for the 16 kbitls 0 channel
- a four-bit command/indication channel
- two bits MR and MX for supporting the monitor channel protocol.
In the case of an IOM-2 interface, the frame structure depends on whether TE- or
is selected, via bit SPM in SPCR register.
non-TE
Non-TE timing mode (SPM = 1)
In thi.s case, the frame is a multiplex of eight IOM-2 channels (figure 14), each channel has
the structure in figure 13.
Thus the data rate per subscriber connection (corresponding to one channel) is 256 kbitls,
whereas the bit rate is 2048 kbitls. The IOM-2 interface signals are:
IDPO,1: 2048 kbiVs
DCLK
FSC:
4096 kHz-input
8 kHz-input
Siemens Components, Inc.
299
PEB 2070
Figure 14
Multiplexed Frame Structure of the IOM-2 Interface in Non-TE Timing Mode
t - - - - - - - - - - 1 2 5 }Js---------'~
FS(
DCLK
IPDO
10M (HO
(H 7
(H 0
IPDI
10M CHO
CH 7
CH 0
I
B1
B2
I Monitor
The ICC is assigned to one of the eight channels (0 to 7) via register programming.
This mode is used in ISDN exchange/line card applications.
TE Timing Mode (SPM = 0)
The frame is composed of three channels (figure 14):
• Channel 0 contains 144 kbiVs (for 2B + D) plus monitor and command/indication channels for layer-1 devices.
• Channel 1 contains two 64-kbiVs intercommunication channels plus monitor and
command/indication channels for other IOM-2 devices.
• Channel 2 is used for enabling/inhibiting the transmission of HOLC frames. This bit is
typically generated by an S-bus transceiver (stop/go: bit 5, or 3rd MSB of the last octet
on 10PO). On IOP1, bits 2 to 5 of the last octet are used for TIC bus access arbitration.
As in the IOM-1 case (figure 9), up to eight ICCs can access the TIC bus (0 and C/I
channels). The bus arbitration mechanism is identical to that described previously, except
that it involves bits 2 to 5 in channel 2.
Siemens Components, Inc.
300
PEB 2070
Figure 15
Definition of IOM-2 Channels in Terminal Timing Mode
~
FSC
IOM® Channel 0
/
II
IDPO
I B1 I B2
IDP 1
I B1
________________~rIOM® Channel 1
\
IMONOIO!CI1O~~
1 B2 IMONO~~I
I
II
IOM® Channel 2
\
/..-----.JII'--S-/G-----'
IC1 pC2
IMON11(/11~~
I I
I
1IC2
IMON 11 (/11 ~~
1(/121
I
IC1
TIC Bus ...--,._....
1_.....1_.....1___
-J1L....--J1L....--J1L....-___________
SOS 11Z _____
The IOM-2 signals are:
10PO, 1:
OCLK:
FSC:
768 kbiVs
1536-kHz input
&kHz input.
In addition, to support standard combos/data devices the following signals are generated
as outputs:
SOS1/2:
8-kHz programmable data strobe signals for selecting one or both B/IC
channel(s).
SSI (Serial Port A)
The SSI (Serial Synchronous Interface) is available in IOM-1 interface mode. Timing mode 0
(SPM = 0) has to be programmed.
The serial port SSI has a data rate of 128 kbiVs. It offers a full duplex link for B channels
in ISDN voice/data terminals. Examples: serial synchronous transceiver devices (USART's,
HSCX SAB 82525, ITAC PSB 2110, .... ), and COOEC filters.
The port consists of one data line in each direction (SOAX and SOAR) and the 128 kHz
clock output (SCA). The beginning of B2 is marked by a rising edge on FSC, see figure 15.
The!oLC system has access to B-channel data via the ICC registers BCR1/2 and BCX1/2.
The !oLC access must be synchronized to the serial transmission by means of the Synchronous
Transfer Interrupt (STCR).
Siemens Components, Inc.
301
PEB 2070
Figure 16
SSI and SLD Interface Lines
FSC(1l
(8 kHz)
SOAR (I)
SOAX(O)
SCA (0)
128 kHz
551
SIP (I/O)
OCLK (I)
512 kHz
SLD
The SLD is available in IOM-1 interface mode.
The standard SLD interface is a three-wire interface with a 512-kHz clock input (DCL), an
8-kHz frame direction signal input (FSC), and a serial ping-pong data lead (SIP) with an
effective full duplex data rate of 256 kbitls.
The frame is composed of four octets per direction. Octets 1 and 2 contain the two S channels, octet 3 is a feature control byte, and octet 4 is signaling byte (figure 16).
The SLD interface can be used in:
Terminal applications as a full duplex time-multiplexed (ping-pong) connection to Schannel sources/destinations.
CODEC filters, such as the SICOFI (PES 2060) or the ARCOFI (PSS 2160) as well as
other SLD compatible voice/data modules may be connected directly to the ICC.
Terminal specific functions have to be deselected (TSF = 0), so that pin SIP/EAW takes
on its proper function as SLD data line. Moreover, in TE applications timing mode 0
has to be programmed.
Siemens Components, Inc.
302
PEB 2070
Digital exchange applications as a full duplex time-multiplexed connection to convey
the B channels between the layer-1 devices and a Peripheral Board Controller (e.g. PBC
PEB 2050 or PIC PEB 2052), which performs time-slot assignment on the PCM highways,
forming a system interface to a switching network.
Timing mode 1 (SPM = 1) can be programmed in order to minimize the B channel roundtrip delay.
The j..I.C system has access to B-channel data, the feature control byte and the signaling
byte via the ICC registers:
C1R,C2R
~
B1/B2
-
CFCR and SFCX
~
FC
-
SSCR and SSCX
~
SIG
The j..I.P access to C1 R,C2R,SFCR, SFCR,SSCR and SSCX must be synchronized to the
serial transmission by means of the Synchronous Transfer Interrupt (STCR) and the BVS-bit
(STAR).
Register Description
The parameterization of the ICC and the transfer of data and control information between
the j..I.P and ICC is performed through the R- and XFIFO and two register sets. The address
map is shown in table 6.
The two FIFOs have an identical address range 00-1 FH.
The register set in the address range 20-2A pertains to the HDLC transceiver and LAPD
controller. The register set ranging from 30 to 3B pertains to the control of layer-1 functions
and of the 10M interface.
For a detailed register description please refer to the ICC Technical Manual.
Siemens Components, Inc.
303
PEB 2070
Table 6
ICC Address Map and Register Summary
Address
(hex)
Write
Read
Name
Description
Name
Description
RFIFO
Receive FIFO
XFIFO
Transmit FIFO
20
ISTA
Interrupt Status Register
MASK
Mask Register
21
STAR
Status Register
CMDR
Command Register
22
MODE
Mode Register
23
TIMR
Timer Register
24
EXIR
Extended Interrupt Register
XAD1
Transmit Address 1
25
RBCl
Receive Frame Byte
Count low
XAD2
Transmit Address 2
26
SAPR
Received SAP!
S~\P1
Individual SAPI 1
27
RSTA
Receive Status Register
00
1F
28
SAP2
Individual SAPI 2
TEI1
Individual TEl 1
TEI2
Individual TEl 2
29
RHCR
Receive HDlC Control
2A
RBCH
Receive Frame Byte
Count High
30
SPCR
31
CIRRI
CIRO
Command/lndication
Receive (0)
CIXRI
CIXO
Commandllndication Transmit
(0)
31
MORI
MORO
Monitor Receive (0)
MOXI
MOXO
Monitor Transmit (0)
33
SSCRI
SIP Signaling Code
Receivel
Commandllndication
Receive 1
SSCXI
SIP Signaling Code TransmiV
CIX1
Commandllndication
Transmit 1
SFCWI
SIP Feature Control Writel
MOX1
Monitor Transmit 1
CIR1
34
SFCRI
MOR1
Serial Port Control Register
SIP Feature Control
Readl
Monitor Receive 1
35
C1R
Channel Register 1
36
C2R
Channel Register 2
37
B1CR
B1 Channel Register
38
B2CR
B2 Channel Register
39
ADF2
3A
MOSR
STCR
Sync Transfer Control
Register
ADF1
Additional Feature Register 1
Additional Feature Register 2
Monitor Status Register
Siemens Components, Inc.
304
MOCR
Monitor Control Register
PES 2070
Absolute Maximum Ratings
Parameter
Symbol
Voltage on any pin with respect to ground
Limit Values
Unit
Vs
-0.4 to Voo +0.4
V
Ambient temperature under bias
TA
o to 70
°C
Storage temperature
Tstg
-65 to 125
°C
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
I
DC Characteristics
TA = 0 to 70°C, Voo = 5 V, Vss = 0 V.
Limit Values
Parameter
Symbol
min.
max.
Unit
L-input voltage
\liL
-0.4
0.8
V
H-input. voltage
\liH
2.0
Voo
+0.4
V
L-output voltage
VOL
0.45
V
H-output voltage
H-output voltage
VOH
VOH
Power
supply
current
Icc
operational
power down
Input leakage current
Output leakage current
Siemens Components, Inc.
III
I Lo
2.4
Voo
-0.5
Test Conditions
I OL = 7 rnA
IOL=2 rnA
pin IOPO, IOP1
all other pins
I OH =-400(.LA
V
V
I oH =-100(.LA
1.6
3.5
8.0
rnA
rnA
rnA
OCLK: 512 kHz
OCLK: 1536 kHz
OCLK: 4096 kHz
0.6
rnA
10
(.LA
305
Voo=5V,
inputs at
OVIVoo
no output
loads
oV < \liN, Voo to 0 V
oV < VOUT < Voo to 0 V
PEB 2070
capacitances
TA = 25 DC, Voo = 5 V ± 5%, Vss = 0 V, fc = 1 MHz, unmeasured pins returned to GND.
Limit Values
Parameter
Symbol
typo
max.
Unit
Input capacitance
CIN
5
10
pF
Output capacitance
fc= 1 MHz
COUT
10
20
pF
I/O capacitance
fc= 1 MHz
CIO
8
15
pF
AC Characteristics
TA = 0 to 70 ec, Voo = 5 V ± 5%
Inputs are driven to 2.4 V for a logical "1" anf to 0.4 V for a logical "0". Timing measurements
are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC testing input/output
waveforms are shown below.
Figure 17
Input/Output Waveform and Load Circuit for AC Tests
2.4
2.0"
Device
Under
Test
2.0
Test POints/
O.B /
"
0.8
0.45
Siemens Components, Inc.
306
PES 2070
Microprocessor Interface Timing
Siemens/Intel Bus Mode
IJ.P Read Cycle
~DC
00-07
~-o-a-t-a-
IJ.P Write Cycle
Multiplexed Address Timing
ALE
(S x WR - - - - - - - - - t + - - - - - " " " " " -
LSx
RO
Non-Multiplexed Address Timing
Siemens Components, Inc.
307
PEB 2070
Motorola Bus Mode
I-LP Read Cycle
I-LP Write Cycle
R/W
00-07
.-t"
Data
tW"~
_ ~
Address Timing
Siemens Components, Inc.
308
PEB 2070
Parameters and Values of the Bus Modes
Limit Values
Parameter
Symbol
min.
ALE pulse width
tAA
ns
Address setup time to ALE
tAL
Address hold time from ALE
tLA
50
20
10
Address latch setup time to WR. RD
tALS
tAS
Address hold time from WR. RD
tAH
ALE pulse delay
tAD
0
10
20
15
ns
Address setup time to WR. RD
0
110
ns
DS delay after RIW setup
toso
RD pulse width
tRR
Data output delay from RD
t RO
Data float from RD
tOF
max.
Unit
ns
ns
ns
ns
ns
ns
110
25
ns
ns
tRI
70
ns
WR pulse width
tww
tow
Data hold time from WR* CS
two
WR control interval
tWI
60
35
10
70
ns
bata setup time to WR* CS
RD control interval
Siemens Components, Inc.
309
ns
ns
ns
PEB 2070
Serial Interface Timing
10M Mode
10M Timing
OCLK
-1
j
h
~
,- tFSH -
t FSS ~
1
~
F5C
'--
F5D
r\
tFSWi--
~
H
t llS
IOPO/1(1)
1O~-1Mode
-----------------
IOPO/1(1)
IO~-2Mode
------------~~--------------
--
-----
---
----
- ----- (
,- -----
~=======(
- - - I-I-- tlOO-
IDPO/1 (0)
--
1-I--t
5051/2
Siemens Components, Inc.
310
tlOF
tSDF
f.-
>:=
PEB 2070
Parameters and Values of 10M Mode
Limit Values
Parameter
Symbol
min.
max.
Unit
10M output data delay
tloo
140
100
ns
ns
10M input data setup
tiiS
10M input data hold
10M output from FSC
tliH
20
20
40
20
20
Strobe signal delay
tsoo
tSOF
Frame sync setup
tFSS
Frame sync hold
tFSH
Frane sync width
tFSW
FSD delay
tFOO
Note:
50
30
40
20
311
ns
ns
ns
ns
140
See note
ns
ns
This delay is applicable in two cases only:
1) When FSC appears for the first time, e.g. at system power-up
2) When FSC appears before the excepted start of a frame
Siemens Components, Inc.
IOM-1
IOM-2
IOM-1
IOM-2
ns
80
120
120
tlOF
Strobe delay from FSC
ns
ns
Test
Conditions
ns
See note
PEB 2070
HDLCMode
FSC (Strobe) Characteristics
OCLK
f4----+--,tFS
,----1
FSC
tooz
High Impedance
High Impedance
IDP1
Limit Values
min.
100
30
Parameter
Symbol
FSC set-up time
t FS1
FSC hold time
tFH1
Output data from high impedance
to active
tOZD
80
ns
Output data from active to
high impedance
tODZ
40
ns
100
ns
max.
Unit
ns
ns
,-,
Output data delay from DCl
Input data setup
t lDS
Input data hold
tlDH
Siemens Components, Inc.
20
10
30
tODD
312
ns
ns
PES 2070
5erial Port A (551) Timing
551 Timing
91 Channel-----,,....---92 Channel
FSC
OCLK
seA
SOAX _ _ _ _ _ _ _ _ _ _ _ _~
~-----------
Limit Values
Parameter
Symbol
5eA clock delay
tSCD
551 data delay
tSSD
551 data setup
tsss
55i data holf
tSSH
Frame sync hold
tFSH
Frame sync width
tFsw
Siemens Components, Inc.
313
min.
20
20
40
20
30
40
max.
Unit
140
140
ns
ns
ns
ns
ns
ns
PEB 2070
SLDTiming
FSC
OCLK
Last Bit OUT
Limit Values
Parameter
SLD data delay
SLD data setup
min.
max.
Unit
tSLD
20
140
ns
t SLS
30
30
50
30
40
Symbol
SLD data hold
tSLH
Frame sync setup
t FSS
Frame sync hold
t FSH
Frame sync width
t FSW
Siemens Components, Inc.
314
ns
ns
ns
ns
ns
PEB 2070
Clock Time
Definition of Clock Period and Width
--twL-----I
I - - - - - - - - - - - - tp- - - - - - - - - - - - - 0 0 {
Limit Values
Parameter
Symbol
Clock period
min.
max.
Unit
Test
Conditions
tp
1000
ns
IOM-1
Clock width high
tWH
200
ns
IOM-1
Clock width low
tWL
200
ns
IOM-1
Clock period
tp
240
ns
IOM-2
Coock width high
tWH
100
ns
IOM-2
Clock width low
tWL
100
ns
IOM-2
Reset
Reset Signal Characteristics
t RES
\
/lllf
RES
I I I I I
I I I I I
l l L L I
Limit Values
Parameter
Symbol
min.
Test Conditions
Length of active
high state
tRES
2*DCL
clock
cycles
During power up
Siemens Components, Inc.
315
SIEMENS
ISDN D-Channel Exchange Controller (IDEC)
Preliminary Data
PEB2075
ACMOSIC
Type
Ordering code
PEB2075-P
PEB:2075·N
067100-H8682
P-DIP-28
Q61100,.;H8$83
~ee..44;~~'.
Package
The ISDN Digital Exchange Controller PEB 2075 (IDECTM) is a serial HDLC data communication circuit with four independent channels. Its telecommunication specific features make
it especially suited for use in variable data rate PCM systems. In addition, the device contains spohisticated switching functions and it implements automatic contention resolution
between packet data from different sources.
Its applications include: communication multiplexers, peripheral ISDN line cards, packet
handlers, X.25 packet switching devices. The IDEC is a fundamental building block for
networks with either centralized, de-centralized or mixed signaling/ packet data handling
architectures.
Features
•
•
•
•
•
•
•
•
•
•
Four independent HDLC channels
64 byte FIFO storage per channel and direction
Handling of basic HDLC functions
Flag detection/generation
Zero deletion/insertion
CRC checking/generation
Check for abort
Single connection and quad connection modes
IOM® interface or PCM interface
Programmable time slots and channel data rates (up to 4 Mbitls)
Different methods of contention resolution
8-bit parallel microcontroller interface with vectored interrupt
Advanced CMOS technology
Power consumption less than 50 mW.
316
PEB 2075
Logic Symbol
Timing
;---"---\
DCLK
Collision TriData
State
Receive Control
FSC
1
CDR
t
TSC
}...
SDOR
PCMIIOM
SDOX
5V
SD1R
Voo
IDEC M
OV
Vss
SD1X
SD2R
PCM
SD2X
SD3R
ADO. .7 RO
SD3X
WR LS ALE INT RES
U
Pin Configuration
(top view)
AD2
AD3
AD1
AD4
ADO
ADS
Rn
AD6
Wli
AD7
Vss
Voo
DCLK
FS~
PES 2075
IDECM
SD3R
SD3X
RES
SD2R
ALE
SD2X
ES
SDOR
INT
SDOX
CD~
SD1R
TSC
SD1X
Siemens Components, Inc.
317
PEB 2075
Pin Definitions and Functions
Pin No.
Symbol
Input (I)
Functions
Output (0)
3
2
1
28
27
26
25
24
ADO
AD 1
AD2
AD3
AD4
AD5
AD6
AD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Address-Data Bus. The multiplexed address-data bus
transfers data and commands between the ).lP system
and the IDEC.
11
CS
I
Chip Select A low on this line selects the IDEC for a
read/write operation.
5
WR
I
Write. A low on this line indicates a write operation.
RD
I
Read. A low on this line indicates a read operation.
INT
00
Interrupt Request. This line is activated when the IDEC
requests an inierrupt. it is an open drain output.
10
ALE
I
Address Latch Enable. A high on this line indicates an
address on the external address-data bus, selecting
one of the internal sources or destinations.
18
16
20
22
SDOR
SD1R
SD2R
SD3R
I
17
15
19
21
SDOX
SD1X
SD2X
SD3X
0
Serial
Serial
Serial
Serial
7
DCLK
I
Data Clock; supplies a clock signal either equal to or
twice the data rate.
8
FSC
I
Frame Synchronization or data strobe signal
14
TSC
0
Time-Slot Control. Supplies a control signal for an
external driver.
13
CDR
I
Collision Data Receive.
9
RES
I
Reset
6
Vss
I
Ground
23
Voo
I
Supply voltage +5 V
4
12
-
} Serlal Data Receive
Siemens Components, Inc.
Data transmit
Data transmit
Data transmit
Data transmit
318
Serial Data transmit
Serial Data transmit
Collision output
PEB 2075
Figure 1
Block Diagram
CDR
S01X
SOOR
SOOX
S01R
S02X
S02R
S03X
S03R
Serial Interface Logic
.(-::.
L
_V
OCLK
FSC
TSC
~
-V
r--
'(7
L)..
.()..
7
~7
'"
Timing
Timing
Timing
Timing
Switching
Swi tching
Switching
Switching
Call ision
~
Control
~
Collision
~
Control
r-
-::.
~f"
'(7
'" .7
"(7
"-
.;).
L
"'7
RFIFO XFIFO
.;).
'<.7
9
t-
Receiver
Transmitter
t-
L
Receiver
Transmitter
.;::..
~
'<.7
'" 7
'" ?
RFIFO XFIFO
RFIFO XFIFO
RFIFO XFIFO
.()..
L
'" 7
'<..7
"'7
Microcontroller Interface
ff
{t8
Siemens Components, Inc.
Control
V
Receiver
.(';-::.
INT
Collision
HOLC
Transmitter
;>.
I
.(-::.
HOLC
HOLC
Receiver
~
Control
L
Transmitter
~
Collision
.;;>.
HOLC
t-
-::.
AOO-7
~
RO
319
WR
CS
ALE
RES
~
PEB 2075
1. System Integration
Communication Multiplexers
The four independent serial HDLC communication channels implemented in the IDEC make
the circuit suitable for use in communication multiplexers.
The collision detection/resolution capability of the circuit allows statistical multiplexing of
packets in one or several physical data communication channels, for example in DMI (mode 3)
applications.
Centralized Signaling Data Packet Handlers
The IDEC can be used in central packet handlers of ISDN networks to process signaling or
packet data of four ISDN subscribers. In this application, it may be used with or without
the Extended PCM Interface Controller (EPIC) PES 2055.
The IDEC can be connected to the 10M interface of the EPIC, which is itself connected to
the PCM system highway. The EPIC implements concentration and time-slot assignment
functions. As an alternative, the IDEC may be directly connected to PCM highways (figure 2).
The size (from 1 to 8 bits) and the position of the time slot associated with each HDLC
controller are software programmable. In addition to the receive and tiaiismit data highways,
the IDEC accepts a third input connection for collision detection purposes. The mode of
collision detection is programmable. A "collision highway" (or time slot) can be used for
remote collision control, as a "clear to send" lead, or for local contention resolution among
several IDECs.
Siemens Components, Inc.
320
PES 2075
Figure 2
Use of IDEC in Central Signaling Data Packet Handlers
PCM Highway
PCM Highway
I I
I I
I I
I I
I I
I
I I
I
I I
Line
Line
Transmit T5
Receive T5
Transmit T5
Receive T5
Cards
L..--t-_ _>----....--.....:Transmit
,---+_.---+____+-_..;..Receive
.--'""l-__----_-Transmit
L....,.,......J--r-t---:-t-
---- C
---- C
L.-.--'-_ _ _ _ _ _ _ _ ~
PCM Highway
I I I
1 I I
~-----------~
PCM Highway
I I
I I
I I
I I
I I I
Line --
Line
Transmit T5
Receive T5
Co llision Detect T5
Transmit T5
Receive T5
Collision Detect T5
Cards::::::::::::::::
Cards--
Transmit
--- C
~-------------~
Siemens Components, Inc.
321
Receive
PEB 2075
Line Cards De-Centralized or Mixed Signaling/Data Packet Handling Architectures
The IDEC can be used on peripheral line cards to process D-channel packets for ISDN
subscribers. An Extended PCM Interface Controller PEB 2055 has the layer 1 contrOlling
capacity and a Band 0 channel switching capacity for a total of 32 subscribers. The Band
o channels and the control information for eight subscribers are carried over one 10M interface. Thus a line card dimensioned for 32 ISDN subscribers may employ up to eight IDECs,
two for each 10M connection (figure 3)" A High Level Serial Communication Controller (HSCC)
SAB 82520 with two HDLC channels, or another IDEC may be used to transmit and receive
signaling over the system highway in a common channel. Again, such a common channel
may be shared among several line cards, due to the statistical multiplexing capability of
these controllers.
In completely de-centralized D-channel processing architectures, the processing capacity
of a line card is usually dimensioned to avoid blocking situations even under maximum
conceivable D-channel traffic conditions. It may sometimes be more advantageous to perform
p-packet handling in a centralized manner while keeping s-packet handling on the line cards.
A statistical increase in p-packet traffic has then no effect on the line card, and can be easily
dealt with by one of the modular architectures for a central packet handler shown in the
previous section. A more effective sharing of the total p-packet handling capacity is the
result, especially in a situation where p-packet traffic pattems vary widely from one subscriber group to another.
'
The use of IDEC in the mixed D-channel processing architecture is illustrated in figure 4).
The additional "transparent data" connections supported by the IDEC enable a merging of
p- and s-packets into one D-channel. Possible collision situations are dealt with by the IDEC
which uses either the additional collision detect line (figure 4a) or a time slot on the system
highway (figure 4b) from the line card to the central packet handler.
Siemens Components, Inc.
322
PEB 2075
Figure 3
Line Card in a De-Centralized D-Channel Handling Architecture
Line Transceivers
XB
----B
IOM:R
c.c.s
+
c. c.p
System Highways
I
Legend:
c.c.s/p =Common channel for
signaling and for
packed data,
respectively
CII,Mon=Control/lndication and
Monitor channels of
the 10M interface
Siemens Components, Inc.
323
PES 2075
Figure 4aj 4b
IDEC on a Line Card in a Mixed D-Channel Processing Architecture
roM ®
B
---
Line
Transceivers
B
System
JHighwa y
Coll s-p
EPIC ™
~o
of
U
11
1
pC
s
s!)
--p
___ p(s)*
IOEC™
--p
roM ®
B+p
Line
Transceivers
B+p(s)*+Coll s-p
System
Highways
~o
of
P
IDEC™
Coll s-p
EPIC™
"-
sf
~s
* s-Packets will be discarded by the receiver
Legend:
J~
p = Time slot for p-packets
s = Time slot for s-packets
Coll s-p = Time slo t containing
information about a collision
between s-packets and p-packets
~7
pC
Siemens Components, Inc.
324
PEB 2075
2. Functional Description
General Functions and Device Architecture
The IOEC is an HOLC controller which handles four HOLC communication channels, each
channel fully independent and programmable by its own register set. The circuit performs
the following functions:
• Extraction (reception) and insertion (transmission) of the HOLC data packets in a time
division multiplex bit stream.
• Implementation of the basic HOLC functions of the layer-2 protocol.
• Interfacing of the data packets to the microprocessor bus. For the temporary storage of
data packets overlapping FIFO structures are used per channel and direction.
• Switching of data between serial interfaces.
• Implementation of different types of collision resolution.
• Test functions.
Operating Modes
Each HOLC controller of the IOEC is assigned to one time channel governed either by time
slot assignment or by an external strobe signal.
Two basic configurations are distinguished (figure 5):
•
•
In the quad connection configuration the four HOLC controllers (A-D) are connected to
individual time multiplexed communication lines;
In the single connection configuration the four HOLC channels are all connected to one
time multiplexed communication line.
Rgure 5
(a) Quad Connection and
(b) Single Connection Configuration.
A
A
B
Main
Connection _ _++....
-----}
--=:
B
C
o
a)
pC
b)
Siemens Components, Inc.
325
Auxiliary
Connections
PEB 2075
In the quad connection configuration two modes are distinguished as follows:
• Each connection is a time slotted highway, the lengths and positions of the time slot are
programmable (quad connection time-slot mode);
• Each connection is a communication line, the time channels are marked by an external
strobe signal (quad connection common control mode).
Two modes are distinguished in turn for the single connection configuration as follows:
• The connection is a standard 10M interface with predefined channel positions (single
connection 10M mode);
• The connection is a time slotted highway (single connection time-slot mode).
For simplicity, a time slotted highway will sometimes be referred to as a "PCM highway", or
PCM for short.
Table 1
Four Basic Operating Modes of the IDEC
Mode Description
MDS1
MDSO
0
0
Single connection time-slot mode
0
1
Quad connection common control mode
1
0
Single connection 10M mode
1
1
Quad connection time-slot mode
The four modes of operation are illustrated in figure 6. Via channel-by-channel programming, one of a number of collision detection modes may be selected in each of the basic
modes of operation. For future reference, they are also depicted in figure 6.
Siemens Components, Inc.
326
PEB 2075
Figure 6
Operating modes of the IDEC
b. Quad Connection Common Control Mode
a. Quad Connection TS Mode
Programmable Time Slots
I---
B
Receive
Transmit
-C
-D
Receive
Transmit
B
Receive
Transmit
Receive
Transmit
Receive
Transmit
,
'---
Collision
Data
Receive
Transmit
Slave /Hulti Master
C"lIision Hode
I
I
I
I
Receive
Transmit
B
C
I
I
I
I
A
Transmit
~
-I
Strobe
r----
A
Receive
1
.---A
I--
I
B
I
I--
I
I
I--
I
I
L...--
r
I
C
D
1
Collision
Data
Slave / Mu Iti Master
(ollision Mode
c. Single Connection TS Mode
B
A
A
A
Programmable Time Slots
Receive
Transmit
d. Single Connection 10M Mode
D
A
B
D
Receive
Transmit _ - I......-I*--"'*-~--+...J.4
B
D
B
D
Collision
Data
Collision --~I-4-I---+~--+-+-----_-.J
Data
Slave Multi Master
Collision Mode
Siemens Components,lnc.
Slave/Multi Master
Collision Mode
327
PES 2075
Figure 6 (continued overleat)
e. Single Connection TS Mode
Programmable Time Slots
Programmable Time Slots
o
Receive
Transmit
1-~;..j--I-'-~-40"""--fo-l-- Transmit
-+-++~I---+o.....-~t--+-~
' -__........~~--Ioo....j..--Io-l- Receive
1-__........+-~-40....j..--fo-l-- Collision
Data
--+-......~I---40......--I~ot--H-+
Master Collision Mode
f. Single Connection 10M Mode
Programmable Time Slots
B
A C
0
1-~1---++"""'-----IooI--Transmit
'-~I----l-I---IooI-----IooI- Receive
1-~1----l-I---IooI-----IooI--Collision
Receive
Transmit __-I~-+-I--~I--Io~--H-+
Data
Master Collision Mode
Interfaces
Microcontroller Interface
The IDEC is programmable over an 8-bit parallel microcontroller interface. Easy and fast
microprocessor access is provided by 8-bit address decoding on chip. The interface
consists of 13 lines and is directly compatible with processors of the multiplexed address/
data bus type.
Siemens Components, Inc.
328
PEB 2075
Table 2
Microcontroller Interface Signals of the IDEC
Symbol
Type
Name and Functions
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD?
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Address·Data bus. The multiplexed address/data bus transfers
data and commands between the IlC system and the IDEC.
CS
I
Chip Select. A low on this signal selects the IDEC for a read/
write operation.
WR
I
Write. This signal indicates a write operation.
RD
I
Read. This signal indicates a read operation.
INT
OD
Interrupt Request. The signal is activated when the IDEC requests
an interrupt. It is an open drain output.
ALE
I
Address Latch Enable. A high on this line indicates an address
on the external address/data bus.
._.
In addition to 8-bit processors, the IDEC supports a direct connection to 16-bit processors.
Thus, through an internal address transformation, it is possible to access all IDEC registers
using either even microprocessor addresses only or odd microprocessor only.
Note:
The IDEC is now also available in a PL-CC-44 package with a demultiplexed
address-data bus. For more information, see the latest IDEC Technical Manual.
Serial Interface
Depending on the selected mode, the IDEC supports four physically separate, full duplex
serial interfaces, or one full duplex interface.
In addition to the data input and data output lines, the serial interface requires a common
data clock (input DCLK) and a frame synchronization signal (input FSC). Input data is latched
on the falling edge of DCLK and output data is clocked off on the rising edge of DCLK. The
IDEC may be programmed so that the data clock rate is either equal to data rate, or twice
the data rate.
Siemens Components, Inc.
329
PEB 2075
Register Description
Register Address Layout
The register set consists of:
-
one configuration register common to all four channels (CCR)
-
a maskable vectored interrupt status register (VISR, VISM)
and, for each of the four channels, a set of individual registers (figure 7).
In order to support the use of a 16-bit microcontroller, each register can be accessed
with an even and an odd address value.
Figure 7
IDEC Register Map
Read
Write
OOr---------,----------,
} i: ~;,~',
Alo
ca" " ,
2F~~~~~~~~~~~
37 .3E
p..>.>""""'~~""""'~"""""'~~~">_>i
36. 3F
I_--~~--+---"':"':':'::':":"--_i
~Ol_--~~--+---~~--_i
} i::;~~',
Blocatio",
6F~~~~~~~~~~~
Siemens Components, Inc.
330
PEB 2075
The address map of the individual registers of each channel is shown in table 2. In order
to obtain the actual address of a register, a "base" has to be added to the address given
in the table, as follows:
Base = 00
40
80
CO
for channel A
for channel B
forchannelC
for channel D.
Table 2
Address
Odd
Read
Write
1F
RFIFO
XFIFO
20
29
ISTA
ISM
28
21
STAR
CMDR
22
2B
MODE
MODE
2C
25
RFBC
TSR
Even
00
to
For a detailed register description, see the IDEC data sheet.
Siemens Components, Inc.
331
PEB 2075
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Ambient temperature under bias
TA
Oto 70
DC
Storage temperature
Tstg
-65 to 125
DC
Voltage on any pin with respect to ground
Vs
-0.4 to Voo +0.4
V
DC Characteristics
TA = 0 to 70 DC; Voo= 5 V ±5%, Vss= OV
Limit Values
Parameter
Symbol
min.
max.
Unit
L-input voltage
VlL
-0.4
0.8
V
VlH
2.0
Vcc+O.4 V
H-input voltage
L-output voltage
VOL
H-output voltage
H-output voltage
VOH
VOH
Power
supply
current
0.45
V
V
V
2.4
Voo-Q·5
operational
rnA
Icc
power down
Input leakage current
Output leakage current
rnA
ILl
IOL =2 rnA
IOH = -400 IlA
IOH =-100 IlA
Voo=5V,
input at 0 VlVoo,
no output loads
oV < VlN < Voo to 0 V
+10 IlA
lLO
Test Conditions
OV < VOUT < Voo to OV
Capacitances
TA=25°C, Voo =5V±5%, Vss=OV
Limit Values
Parameter
Symbol
Input capacitance
liD
Siemens Components, Inc.
min.
max.
Unit
CIN
7
pF
CIO
7
pF
332
Test Conditions
PEB 2075
AC Chal1lcteristics
TA = 0 to 70 DC, VOO = 5 V ± 5%
Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements
are made at 2.0 V for a logical "1" and at 0.8 V for a logical "0".
The AC testing input/output waveforms are shown below.
Figure 8
InputlOutput Waveform for AC Tests
2,4
2,0"
Device
Under
Test
2,0
Test POints/
0,8
/
"-
0,8
0,45
Siemens Components, Inc.
333
PEB 2075
Microcontroller Interface Timing
IlP Read Cycle
ALE
~
ADO-AD7~
IlP Write Cycle
ALE
t----fW1·--------I
Siemens Components, Inc.
334
PEB2075
Interface Timing
Limit Values
Symbol
min.
ALE pulse width
Parameter
tAA
Address setup time to ALE
tAL
Address hold time from ALE
tLA
50
20
10
120
RD pulse width
tRR
Data output delay from RD
t Ro
max.
Unit
ns
ns
ns
ns
120
25
ns
Data float delay from RD
tOF
RD control interval
tRI
75
ns
WR pulse width
tww
tow
two
60
30
10
ns
Data setup time to WR + CS
tWI
70
ns
Data hold time from WR
+ CS
WR control interval
ns
ns
ns
Serial Interface Timing
DCLK Characteristics
Definition of DCLK Period and Width
O.BV
1-----fWH-----I
------<.,
1 - - - - - fWl
I-------------tp----------I~
DCLK Characteristics
Limit Values
Parameter
Symbol
min.
DCl period
tp
DCl high
tWH
DCl low
tWL
230
160
90
50
70
Siemens Components, Inc.
typo
max.
Unit
Test
Conditions
ns
ns
single clock rate
double clock rate
ns
ns
single clock rate
double clock rate
ns
335
PEB2075
Input/Output Characteristics
FSC in Single Connection Modes and Quad Connection TS Mode.
FSC Thning Characteristics
DCLK
FSC
Data OUT
DCLK Rate
equal to
Data Rate
Data IN
fOOD
Data OUT
1st Bit of Frame
DCLK Rate
equal to
twice the
Data Rate
Data IN
Limit Values
Parameter
Symbol
min.
FSC set-up time
tFs
60
30
typo
max.
Unit
ns
FSC hold time
tFH
Output data delay from DCLK
tODD
Input data set-up
tlDS
25
ns
Input data hold
tlDH
20
ns
Output data delay from FSC·
tODF
• This delay is applicable in two cases only:
1) When FSC appears for the first time, e.g. at system power-up.
2) When the number of bits in the PCM frame is not equal to either 256 or 512
Siemens Components, Inc.
336
ns
60
150
ns
ns
PEB 2075
FSC in Quad Connection Common Control Mode
~C (strobe) CharacteristiCs
DCLK
FSC
High Impedance
Data OUT
Data IN
Limit Values
Parameter
Symbol
min.
FSC set-up time
t FS 1
60
FSC hold time
tHF1
30
typo
max.
Unit
ns
ns
tOZD
80
ns
Output data from active to high
impedance
tODz
40
ns
Output data delay from DCl
tODD
Input data set-up
t lDS
25
ns
Input data hold
tlDH
20
ns
Output data from high impedance
to active
Siemens Components, Inc.
60
337
ns
PEB2075
Data 1/0 Characteristics
DCLK
Data OUT
---------++-----------t--..J
Data IN
----------------------~~
Limit Values
typo
Parameter
Symbol
Output data delay from DCLK
tODD
Input data set-up
t lDS
25
ns
Input data hold
tlDH
20
ns
TSC delay from DCLK
t reD
min.
Data OUT:
SDOX in single connection modes
SDOX, SD1X, SD2X, SD3X in quad connection modes
SD1X, SD2X in master mode
Data IN:
SDOR in single connection mode
SDOR, SD1X, SD2R, SD3R in quad connection modes
CDR in slave, multi-master and master modes
max.
Unit
60
ns
60
ns
max.
Unit
•
RES Characteristics
LlmltValuea
Parameter
Symbol
min.
RES high
t RWL
4 x tp
Siemens Components, Inc.
338
typo
ns
SIEMENS
S-Bus Interface Circuit (SBC)
PEB2080
Preliminary Data
Type
CMOS-IC
Ordering Code
Package
C-DIP-22
PEB 2080-C
067100-H8329
es.!08C~
'QG7;1'OO;"RI3H·· .····.·>;~~{SM"f
PEB 2080-P
067100-H2954
P-DIP-22
The S-Bus Interface Circuit (SBG) PEB 2080 implements the four-wire SfT -interface used to
link voice/data terminals to an ISDN. Through selection of operating mode, the device may
be employed in all types of applications involving an S-interface. Two or more SBCs can
be used to build a point-to-point, passive bus, extended passive bus or star configuration.
Specific ISDN applications of the SBC include: ISDN terminals, ISDN network termination
(Central Office and PBX applications), and PBX trunk lines to Central Office.
The device provides all electrical and logical functions according to CCrlT recommendation 1.430.
These include: mode-dependent receive timing recovery, D-channel access and priority
control, and automatic handling of activation/deactivation procedures. The SBC does not
require direct microprocessor control.
The SBC is an IOM@compatible, 22-pin CMOS device. It operates from a single +5 V supply
and features a power-down state with very low power consumption.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Full duplex 2B + D SIT-interface transceiver according to CCITT 1.430
Conversion of the frame structure between the SfT and 10M interfaces
D-channel access control
Activation and deactivation procedures according to CCITT 1.430
Built-in wake-up unit for activation from powerdown state
Adaptively switched receive threshold
Control via 10M interface
Several operating modes
Receive timing recovery according to selected operating mode
Frame alignment with absorption of phase wander in trunk line applications
SWitching of test loops
Advanced CMOS technology
Low power consumption: standby less than 4 mW
active max
60 mW
339
PEB 2080
Logic Symbol
SR2
SOl
2:1
~'OOO"
SR 1
r100nF
SX2
sse
MO
Clock
PES 2080
SX 1
CP
2:1
lEooo"
2.2 kSl :!:1%
XTAL1
=7.6BMHz:!:100ppm
XTAL2
RST
+5V
OV
Reset
* Terminating resistors only at the far ends of the connection
Siemens Components. Inc.
340
21
PEB 2080
Pin Configurations
(top view)
P-DIP-22; C-DIP-22
22
Voo
RREF
SX1
2
21 SY1
SX2
3
20 SY2
19 XTAl1
M1 t.
18 XTAl2
SOO
5
ClK
6
FSC
7
16 CP
SOl
8
15 MO
X2
9
1t.
PES 20BO
17 Vss
X1
RST 10
13 XO
X3 11
12 M2
PL-CC-28
~
u.... _ _
~~J~~
3 2 1 28 27
SX 2
SOO
OClK
FSC
SOl
0
PES 2080
N.C.
26 SR2
N.C.
XTAl1
XTAl2
Vss
CP
MO
X1
N.C.
O"""'UNC>
tiiXz:LX
0:
Siemens Components, Inc.
341
PEB 2080
Pin Definitions and Functions
Symbol
Input (I)
Function
Output (O)
2
SX1
0
Positive output S-bus transmitter
3
SX2
0
Negative output S-bus transmitter
5
SOO
0
Serial data out, 10M interface
8
SOl
I
Serial data in, 10M interface
6
OCLK
I/O
Serial data clock, 10M interface
7
FSC
I/O
Frame Sync, 10M interface
12
4
15
11
M2
M1
MO
X3
I
I
I
I
} Setting of operating mode
9
14
13
X2
X1
XO
I/O
I/O
I/O
see chapter Operating Modes
16
CP
I/O
Clock Pulse/special purpose
19
XTAL1
I
Connection for external crystal, or input for external
clock generator
18
XTAL2
0
Connection for external crystal, N.C., when external clock
generator is used.
20
SR2
I
S-bus Receiver, signal input
21
SR1
0
S-bus Receiver, 2.5 V reference output
22
RREF
0
Connection of reference resistor to ground
(2.2 kQ ± 1%)
1
VDD
I
Power supply, +5 V ± 5%
17
Vss
I
Power supply, ground
10
RST
I
Reset, active low
Pin
No.
Siemens Components, Inc.
Functions depending on the selected operating mode
342
PEB 2080
Block Diagram
SX1
t-----oSDI
Buffer
SX2
O-CH
'---7L-~Mode
1--1----. SOO
I-----:~-- Special
r + -__ Purpose
r..l.-----L--'-----L----....:..::.~1_-_ OCLK
L-__________________
Siemens Components, Inc.
...-.-- FSC
~
__-J----CP
343
PEB2080
System Integration
The SBC implements the four-wire Sand T interfaces used in the ISDN basic access.
It may be used at both ends of these interfaces.
The Applications Include
ISDN terminals (TE)
ISDN network termination (NT)
ISDN subscriber line termination (LT-S)
ISDN trunk line termination (LT -T)
(PBX connection to Central Office).
These applications are shown in figure 1, where the usual nomenclature as defined by the
CCITT for the basic access functional blocks and reference pOints has been used.
Figure 1
Applications of the SBC
Terminals
Exchange Termination
TE
LT-S
~~-----"'=l----1~-------in
I
I
Network Termination
NT
-J
r -__~T~E
'-------""~~~
------t _+_T/-rl/~~1I1-r-\,\--t-~----ill
u-____
I
I
-J
,
I
/
\
NT 2
NT1
\
1~B~ ~f----1f----""-~-----,-,I~
LT-S
LT-T
Siemens Components, Inc.
NT
344
PES 2080
Some of the S interface wiring configurations possible with the SBC are shown in figure 2,
with approximate typical distances.
*) (N.B.: "TR" stands for terminating resistor of value 100 Q).
Figure 2
Some S-Interface Wiring Configuration
j-------l
I
IIOM®
I
l
I
I
I
IL
_-----<=-1-.s-km-----.....oof
t-01
..
I
IIA1
TE/LT-T
_______
I
Point- to - Point Configurations
~
I..
<=1s0m
... 1
<=10m~
IA1
n ----,
--,
I
I
I
I
I
I
I
I
• • • • I
I
I
I
L_~~_J Short Passive
Bus
< = 500 m
<=3sm
IA1
:<=10m
IAl
r-- ---,
r-- -11
I
I
I
I
I
I
I
I
I
I
I
I _____
TE1 ...lI
L
....
I
I
I
I
SBC
I
I
I
I
I
L_~~._J Extended Passive
Bus
*) The maximum line attenuation tolerated by the SBC is 15 dB at 96 kHz.
Siemens Components, Inc.
345
PEB 2080
Figure 3
ISDN Oriented Modular (10M) Architecture
B@
Subscriber Terminal
Digital Exchange
Network Term ination
. . . - - - - - - - - - - - - , 4-Wire . . . - - - - - - - - - , 2-Wire . . . - - - - - - - - - - - - ,
S Bus
SBC
IEC
U Interface
2
IOM®
3
4
PBX
2-Wire U Interface (2 km )
4-Wire S Interface. Point-to- Point! Bus
PE B 2050
PEB 2070
PEB 2080
PEB 2085
PEB 2090
PEB 2095
PEB 20950
Peripheral Board Controller
ISDN Communication Controller
S Bus Interface Circuit
ISDN Subscriber Access Controller ( S Bus)
I$DN Echo Cancellation Circuit
ISDN Burst Transceiver Circuit
ISDN Subscriber Access Controller (PBX. U Interface)
Siemens Components, Inc.
346
PBC
ICC
SBC
ISAC™_ S
IEC
IBC
ISAC™_ P
PEB 2080
Figure 3 gives an example of an application of the SBC in an 10M (ISDN Oriented Modular)
architecture.
By separate implementation of OSI layer-1 and layer-2 functions, and through unified
control procedures, the architecture provides flexibility with respect to various transmission
techniques. The 10M devices are all low-power, high integration, single +5 V supply CMOS
devices. Through mode switching, each devices may be used in several applications:
thus with one and the same limited set of devices all ISDN basic access configurations
are covered. Note that none of the compatible layer-1 devices (SBC, IBC, lEG) requires
direct microprocessor control. This is due to the fact that 10M interface provides all the
necessary functions for layer-1 - layer-2 communication.
Functional Description
The S-bus interface circuit PEB 2080 performs the layer 1 functions for the SIT interface
of the ISDN basic access.
General Functions and Device Architecture
The common functions for all operating modes are:
line transceiver functions for the S interface according to the electrical specifications
of CCITT 1.430;
dynamically adaptive threshold control for the receiver;
conversion of the frame structure between 10M and S interfaces;
conversion from/to binary to/from pseudo-ternary code.
Mode specific functions are:
receive timing recovery;
S timing generation using 10M timing synchronous to system, or vice versa;
D-channel access control and priority handling;
D-channel echo bit generation;
activation/deactivation procedures, triggered by primitives received over the 10M interface
or by INFO's received from the line;
frame alignment according to CCITT 0.503;
execution of test loops.
For a block diagram, see figure Block Diagram
Analog Functions
The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter
which is realized as a voltage limited current source. A current of 7.5 mA is delivered
over SX1-SX2, which yields a voltage 1.5 V over 200 O.
The receiver is designed as a threshold detector with adaptively switched threshold levels.
Pin SR1 delivers 2.5 V as an output, which is the virtual ground of the input signal on
pin SR2.
An external transformer of ratio 2: 1 is needed in both receive and transmit direction to
provide for isolation and transform voltage levels according to CCITT recommendations.
Siemens Components, Inc.
347
PEB2080
Digital Functions
A DPLL circuitry working with a frequency of 7.68 MHz ± 100 ppm serves to generate the
192-kHz -line-clock from the reference clock delivered by the network and to extract the
192-kHz-line clock from the receive data stream.
I '
The 7.68-MHz-clock may be generated with the use of an external crystal between pins
XTAL 1 and XTAL2. It may also be provided by an external oscillator, in which case XTAL2
is left unconnected.
The "Control" block includes the logic to detect layer-1 commands and to communicate
with external layer-1 or layer-2 devices via the 10M interface.
An incorporated finite state machine controls ISDN layer-1 activation/deactivation.
The D-channel access procedure according to CCITT 1.430 including priority management
is fully implemented in the SBC. When used as an S-bus master in a multipoint configuration,
the device generates the echo bits necessary for D-channel collision detection. In the
NT-mode, moreover, the echo channel may ,be made externally available through an
auxiliary pin and thus "intelligent NT's" (star configuration) may be implemented.
In terminal applications (TE) the Q channel as specified by 1.430 is supported*).
The buffer memory serves to adapt the different bit rates of the S and the 10M interface.
In addition, in trunk line applications it absorbs the possible deviation between two system
clocks, according to CCID Q.503 (slip detection).
Operating Modes
The operating modes are determined by pin strapping on pins MO to M2. The four basic
operating modes are: TE, NT, LT-S, LT-T.
In three of these operating modes, the 10M may be programmed to function in the normal
mode, in the inverted mode (clock frequency 512 kHz) or in the inverted mux mode (clock
frequency 4096 kHz). To see which 10M timing mode is applicable in the four basic
operating modes, refer to table 1.
In table 1, the functions of the operating mode specific pins are given: these pins are DCLK
(10M interface data clock, input/output), FSC (10M interface frame sync, input/output),
CP (auxiliary clock/test pin), and XO to X3.
Depending on the selected mode, pins CP, X2 and X1 provide auxiliary clocks, either
asynchronous or synchronous to the S-interface:
3840kHZ]
2560 kHz
clocks derived from the 7680-kHz-crystal
1280 kHz
1536 kHZ]
clocks synchronized to S-interface.
512 kHz
These auxiliary clocks may be used to drive, e.g. a codec filter, or a microprocessor system
(TE applications).
*) Stepping A 6 and up. The SBC sends a binary one in FA bit position to allow another
terminal to use the extra transmission capacity.
Siemens Components, Inc.
348
PEB 2080
The other uses of the auxiliary pins are:
ENCK input
Enable clock. At "0", forces the SBC to deliver 10M timing at all times,
regardless of SOl input level; in TE mode, pin X3.
At "1 ", specifies a bus configuration (as opposed to pOint to point or
Bus
input
extended passive bus); in NT and LT-S modes, pin X3.
ECHO output
pushpull
Reproduces the E-bits received from the S-interface synchronously to 10M
frame "O"-bits (bit positions 24 and 25 of 10M frame). All other bit positions
are binary "1 "; in TE mode, pin X2.
SSZ
input
Send Single Zeros. At "0", forces the SBC to transmit alternating pulses
at 250 IJ.s intervals (period 2 kHz) on S-interface for test purposes; X2 in
NT mode.
ROY
output
push
pull
Ready. Provides a signal logically equal to bit 3 of monitor channel. Signals
the O-channel status ("0" = occupied, "1" = free) to layer 2 component;
XO in TE mode.
CON
input
Connected. At "0", prevents the SBC from activating and transmitting on
the S-interface. Indicates whether the device is connected to the S-interface
or not; XO in TE and LT-T modes.
OEX
input
External O-channel echo enable. At "1 ", makes the E-bit dependent on the
DE (XO) input. Used in NT mode to build a star configuration; X1 in
NT mode.
DE
input!
O-channel Echo. The DE outputs should be tied together (open drain)
output in an NT star configuration, to obtain the global echo bit; XO in NT mode.
open
drain
with
integrated
pull-up
resistor
TSOto
TS 2 inputs
Time slot 0 to 7. 10M interface time slot to be used =
4 x TS2 + 2 x TS1 + TSO;
LT-T and LT-S in 10M mux mode.
Siemens Components, Inc.
349
PEB 2080
Table 1
Operating Modes and Functions of Mode Specific Pins of PEB 2080
Application
TE
TE
TE
LT-T
LT-T
NT
LT-S
LT-S
LT-S
Operation
of 10M
Interface
Inverted
Mode
Inverted
Mode
Normal
Mode
Mux
Mode
Inverted
Normal
Mode
Normal
Mode
Mux
Mode
Inverted
Normal
Mode
Normal
Mode
M2
M1
MO
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
1
1
1
0
0
1
1
0
1
1
0
DCLI(
FSC
CP
0:512kHz' 0:512kHz' 0:512kHz' i:4096kHz i:512kHz
0:8kHz'
0:8kHz'
0:8kHz'
i:8kHz
i:8kHz
0:
0:
0:
1536kHz' 1536kHz' 1536kHz' 0:512kHz' 0:512kHz*
1
i:512kHz 1:4096kHz i:512kHz
i:512kHz
i:8kHz
i:8kHz
i:8kHz
i:8kHz
i:SCZ
i: fixed
at 0
i: fixed
at 0
i: fixed
at 0
X3
i:ENCLK
i:ENCLK
i:ENCLK
i: fixed
at 1
i: fixed
at 0
I: BUS
i:BUS
i:BUS
i: BUS
X2
0:
0:
2560kHz 1280kHz
o:ECHO
i:TS2
i: fixed
at 0
i:SSZ
i:TS2
i: fixed
at 0
0:192kHz
X1
0:
0:
0:
3840kHz 3840kHz 3840kHz
i:TS1
i: fixed
at 0
i:DEX
i:TS1
i:TSO
i:CON
i/o:DE
i:TSO
XO
o:RDY
*) synchronized to S
SCZ
ENCLK
BUS
TS2-0
SSZ
DEX
RDY
CON
DE
o:RDY
i:CON
i: input
0: output
Send continuous binary zeros (96 kHz)
Enable clock at all times
Bus configuration specified
Time-slot number of 10M
Send single binary zeros (2 kHz)
D-channel echo external/internal
D-channel status on S-interface
Connected to S bus
D-channel echo bit in NT star configuration
Siemens Components, Inc.
350
0:
0:
7680kHz 7680kHz
i: fixed
at 0
i:fixed
at 1
PEB 2080
Figure 4
Clocking of
sec in Different Operating Modes
IOM®Slave
u
I
S
I
I
I
iI
IEC
I
I
1
I
l__ central
1
I
I
I
Networ~
I
512 kHz
8 kHz
7,68 MHz
la) NT
S
I
I
1
1
1
_ _ Central
Network
ICC
1
I
I
I
512 kHz
8 kHz
IO~Slave
S
I
1
I
I
I __ Central
1
Network
ICC
1----------t~SDI
I
I
I
I
Ie) TE
'OM® Master
S
I
I
-
e,g, NT 2
1
1
I _ _ Central
I
ICC
Network
1
1
512 kHz
8 kHz
1
Id) LT-T
IEC = ISDN Echo Cancellation Circuit PES 2090
ICC = ISDN Communication Controller PES 2070
Note 1: Reference clock 1512 kHz, duty cycle 1,2) may be used to drive ,e,g, NT 2 clock generator
Siemens Components, Inc.
351
PEB 2080
Interfaces
S Interface
According to CCITT recommendation 1.430, pseudo-ternary encoding with 100% pulse width
is used on the S interface. A logical 1 corresponds to a neutral level (no current), whereas
logical O's are encoded as alternating positive and negative pulses. An example is shown
in figure 5.
Figure 5
S Interface Line Code
Binary Values
01001100011
+V
Line Signal
0V
-V
One S-frame consists of 48 bits, at a nominal bit rate of 192 kbiVs. Thus each frame carries
two octets of 81, two octets of 82, and four O-bits, according to the 81 +82+0 structure
defined for the ISDN basic access (total useful data rate: 144 kbiVs). Frame begin is marked
using a code violation (no mark inversion). The frame structures (from network to subscriber,
and subscriber to network) are shown in figure 6.
Siemens Components, Inc.
352
PEB 2080
Figure 6
Frame Structure at Reference Points Sand T (CCITT 1.430)
I. .
"I
48 Bits in 250 Microseconds
NT to TE
o L.F L.I--- B1---1E 0 A FA Nt--B2--JE 0 M I - B 1 - I E 0 SI--- B2-IE 0 l.F l.
~EPlIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII L
o l.F
~~~
TE to NT
l.1--- Bl---1-. 0 l.FA l . ! - - - B 2 - ! l . 0 l . t - - - B 1 - l . 0 lor-- B2 - I l . O l.E l.
It--F = framing Bit
L = DC Balancing Bit
o = 0 - Channel Bit
E = 0- Echo-Channel Bit
F = Auxiliary Framing Bit or Q- Bit
N = Bit Set to a Binary Value N=
r,:
B1
B2
A
S
M
= Bit within B-Channel 1
= Bit within B-Channel 2
= Bit Used for Activation
S-Channel Bit
= Multiframing Bit
Note: Dots Demarcate those Parts of the Frame that are Independently DC-Balanced.
Siemens Components, Inc.
353
PEB 2080
Digital Interface
10M Frame Structure
The SBC is provided with a digital interface, the 10M interface, for communication with
other ISDN devices, in other words with units realizing OSI layer-1 functions (such as the
ISDN Echo Cancellation Circuit IEC PEB 2090) or layer-2 functions (such as the ISDN
Communication Controller ICC PEB 2070).
The 10M interface is a four-wire serial interface with: a bit clock, a frame clock and one
data line per direction (figure 7).
The ISDN data rate of 144 kbitls (B1 + B2 + D) is transmitted transparently in both directions
over the interface. In addition, it is necessary to interchange control information for activation and deactivation of OSI layer-1 and for switching of test loops. This information is
transferred using time division multiplexing with a 125-l-Ls total frame length.
Figure 7
10M Interface Signals
FRAME
FSC
CLOCK
OCLK
o OUT
SOl/SOD
DIN
In LT-S:
In NT:
InLT-T:
In TE :
SOD/SOl
SBC
SBC
SBC
ICC
Siemens Components, Inc.
FRAME
CLOCK
DIN
OOUT
ICC
lEe
ICC
SBC
354
PEB 2080
The basic frame consists of a total of 32 bits, or four octets: B1 + B2 + D (18 bits) plus
14 bits of monitor and control information. The data in both directions are synchronous
and in phase (figure 8).
Figure 8
10M Interface Frame Structure
SOl
SDO
B1
B2
L -________
-L__________
L -________
1st octet B1:
2nd octet B2:
3rd octet:
4th octet B*:
B*
~----~--~
B channel (64 kbitls), most significant bit first
B channel (64 kbitls), most significant bit first
monitor channel (64 kbitls), most significant bit first
2 bit D channel (16 kbitls)
4 bit C/I channel
T channel: not used with SBC
E bit: not used with SBC.
The C/I channel is used for communication between the SBC and a processor via a layer-2
device, to control and monitor layer-1 functions. The codes originating from layer-2 devices
are called "commands", those sent by the SBC are called "indications". For a list of the
C/I codes and their use, see the SBC Technical Manual.
Three modes of the 10M are distinguished. These modes differ only with respect to the
physical data rate (256 or 8 x 256 kbitls) and to polarity of the clocks.
Siemens Components, Inc.
355
PEB 2080
Normal Mode
This timing mode is applicable in all operating modes of the SSC.
Nominal bit rate of data (SOl and SOO):
256 kbitlsec
Nominal frequency of OCLK:
512 kHz
Nominal frequency of FSC:
8 kHz
Transitions of the data occur after even-numbered rising edges of OCLK. Even-numbered
rising edges of the clock are defined as the second rising edge following the rising edge
of FSC and every second rising edge thereafter.
The frame is earmarked by the rising edge of FSC.
Figure 9
Timing of Data and Clocks of 10M in the Normal Mode
DC LK
(512 kHzl
J\JUUUUUUl
FSC
(BkHzl _ _....
Sal
sao
Inverted Mode
This timing mode is only applicable in TE mode.
The characteristics are the same as above, except that FSC is not a signal with 50% duty
cycle but an active low pulse, one OCLK clock period long, which occurs in the middle of
bit 27 (fourth bit of S¥).
Siemens Components, Inc.
356
PEB20SO
Inverted Mux Mode
This timing mode is applicable in the LT-T and LT-S operating modes.
2048 kbitlsec
Nominal bit rate of data bursts
(SOl and SOO)
Nominal frequency of OCLK
4096 kHz
8 kHz.
Nominal frequency of FSC
The frame clock FSC is an active low strobe clock. The strobe earmarks the second half
of bit no. 251 in the frame. The low state of the strobe is detected with the rising edge
of OCLK. Refer to figure 10.
The data at the input SOl is valid on the even-numbered rising edges of OCLK. Transitions
of the data on SOO occur after even-numbered falling edges of OCLK. The rising edge
earmarked by the frame strobe is an even-numbered rising edge of OCLK. The following
falling edge is an even-numbered falling edge.
The bursts are allocated to consecutive time slots in a frame by the static inputs XO(TSO),
X1(TS1), X2(TS2). Table 2 indicates the allocations. Figure 11 gives the positions of the
respective frames.
Figure 10
nming of Data and Clocks of 10M in the Inverted Mux Mode
DCLK (4096 kHz)
FSC (S kHz)
I
I
Frame Bit No.
SOl
(2048 kbitls)
soa (2048 kbitls)
I
250125112521253125412551 0 1 1 1 2 1 3 1 4 1 5 1 6 1
Siemens Components, Inc.
357
PEB 2080
Table 2
Allocation of Time Slots
Time Slot No.
TS2
TS1
TSO
Bit No.
0
1
2
3
4
5
6
7
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 ... 31
32 ... 63
64 ... 95
·96 ... 127
128 ... 159
160 ... 191
192 ... 223
224 ... 255
0
0
0
1
1
1
1
Figure 11
Position of 10M Frames as a Function of Time-Slot Allocation in Inverted Mux Mode
Frame (8 kHz)
I
I
D1 - - - - - - - - - - - - 1D1 - - - - -
Frame Slot No. 0
SOl (2048 kbit/s) - - - - - I
soa (2048 kbit/s)
Frame Slot No.1
SOl (2048 kbit/s)
soa (2048 kbit/s)
D1 - - - - - - - - - - - - /D)---D1 - - - - - - - - - - -D-
-~---I
Frame Slot No.2
SOl (2048 kbit/s) - - - - - - - - 1
soa (2048 kbit/s)
D1 - - - - - - - - - - - - /C
Frame SlotNo.3
SOl (2048 kbit/s)
soa 2048 kbit/s)
--------1
Frame Slot No. 4
SOl (2048 kbit/s)
soa (2048 kbit/s)
----------1
Frame Slot No.5
SOl (2048 kbit/s)
kbit/s)
------------1
soa (2048
D1 - - - - - - - - - - D1 - - - - - - - - - -
D1 - - - - - - - D1-------
Frame Slot No. 6
~
SOl (2048 kbit/s)
t-------------I
soa (2048 kbit/s)
Frame Slot No. 7
SOl (2048 kbit/s)
SOC 12048 kbit/s)
---D
r------------I
Siemens Components, Inc.
358
PEB 2080
The mux mode may be used to link up to eight SBC's over a single 2048 kbiVs interface
to an exchange or PBX (figure 12).
Figure 12
10M Interface 2048 kbitls Mux Mode
--------,
Exchange Termination I
PBX (Layer 2-3)
--------, I
- - - - - - - - , II
111
FRAME
/
/
/
/
FSC
/
111
CLOCK
/
/
/
/
DCLK
/
. III
DIN
/
/'
/'
/'
7'
SDO
111
DOUT
/
/
/
/
SOl
~J
/
..J
i-
2048 kbit Is
Interface to the
Exchange
rUp to
8" SBC
Siemens Components, Inc.
359
PEB 2080
Absolute Maximum Ratings
Parameter
Symbol
Voltage on any pin with respect to ground
Power dissipation
Ambient temperature under bias
Storage temperature
Vs
Po
TA
Tstg
Limit Values
-0.4 to Voo +0.4
1
Oto 70
-65 to 125
Unit
V
W
°C
°C
Stresses above those listed here may cause permanent damage to the device. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Line Overload Protection
The maximum input current (under overvoltage conditions) is given as a function of the
width of a rectangular input current pulse (figure 13).
Figure 13
Test Condition for Maximum Input Current
sac
I
'------+------1------I-t
Siemens Components, Inc.
360
Condition: All Other Pins Grounded
PEB 2080
Transmitter Input Current
The destruction limits are given in figure 14.
R;~2Q.
Figure 14
I
100A
SOA-I--_
I
I
II
10A
SA
I
I
I
I
1A
O.SA
----~----~---------I
I
I
I
I
I
I-----i---+---r----.----twl
10- 12
10- 9
10- 6
10- 3
15
Receiver Input Current
The destruction limits are given in figure 15.
R;
~3000.
Figure 15
I
100A
I
10A
I
I
I
I
1A
I
I
I
I
I
I
I
I
I
--1--------------+-------~-+--,r_.__.-.__.-~~-_r_~-_r_-_~I
10- 10
10- 8
10- 6
Siemens Components, Inc.
10- 4
10- 2
361
15
PEB2080
DC Characteristics
TA = a to 70°C; Voo= 5 V ±5%, Vss= OV
Limit Values
Parameter
Symbol
min.
max.
Unit
L-input voltage
Test Conditions
\liL
-0.4
0.8
V
H-input voltage
\liH
2.0
Voo
+0.4
V
L-output voltage
L-output voltage (SOO)
VOL
VOL1
0.45
0.45
V
V
IOL = 2 mA
I oL = 7 mA
except
H-output voltage
H-output I(oltage
VOH
VOH
V
V
IOH = -400 iJA
I oH =-100 !-LA
SX1,2
Power
supply
current
2.4
Voo
-0.5
operational
Input leakage current
mA
0.8
mA
10
iJ A
oV < \liN < Voo to 0 V
o V < VOUT < Voo to OV
ILl
Voo= 5 V
inputs at VsslVoo
no output loads
Output leakage current
lLO
Absolute value of
output pulse amplitude
(VSX2 - VSX1)
Vx
1.35
1.35
2.03
2.10
1.65
2.4
2.31
2.39
V
V
V
V
RL= 50 (1)
RL= 400 (1)
RL= 500 1)2)
RL = 400 0 1) 2)
Transmitter output current
Ix
7.5
13.4
mA
RL= 5.6 0 1)
Transmitter output
Rx
10
kO
inactive or during
binary one
80
0
during binary zer03 )
RL= 50 0
impedance
Receiver output voltage
VSR1
2.4
2.6
V
10<5 iJA
Receiver threshold
voltage VSR 1 - VSR2
VTR
225
375
mV
dependent on peak
level
Voltage at RREF
Vo
1.0
1.2
V
RREF = 2.2 kO
Output current
10
450
550
iJ A
RREF = 2.2 kO
Notes: 1)
2)
3)
4)
± 1%
± 1%
Due to the transformer, the load resistance as seen by the circuit is four times RL•
From
A7 onwards.
From A7 onwards, the 80 0 output impedance is external.
Applies only up to A6.
sse
Siemens Components, Inc.
362
SR1,2
RREF
12
Icc
power down
All
pins
SX1,2
SR1,2
RREF4)
PES 2080
Cpacitances
TA = 25°C, Voo = 5 V ± 5%, Vss = 0 V
Limit Values
Parameter
Symbol
Input capacitance
I/O capacitance
max.
Unit
GIN
G IO
7
7
pF
pF
All pins
except
SR1,2
XTAL1,2
Output capacitance
against VSSA
GOUT
10
pF
SX1,2
Input capacitance
GIN
7
pF
SR1,2
Load capacitance
G LD
50·)
pF
XTAL1,2
min.
Recommended Oscillator Circuit
Figure 16
6 XTAL 1
External
Oscillator
Signal
19 XTAL 1
'----t~---+---__'_I7 XTAL 2
N.C.
18 XTAL 2
CL
CrystalOsci llator Mode
Driving from External Source
.) for the version up to and including A4 this value should not exceed 20 pF. This maximum capacitance
is determined by the maximum oscillator startup time of 4 ms.
Siemens Components, Inc.
363
PEB 2080
Table 3
output Stages
Application
TE
Operation
of 10M
Interface
M2
M1
MO
TE
TE
LT-T
LT-T
NT
LT-S
LT-8
LT-8
Normal
Mode
Mux
Mode
Inverted
Normal
Mode
Normal
Mode
Mux
Mode
Inverted
Normal
Mode
Normal
Mode
0
0
0
0
0
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
Inverted Inverted
Mode
Mode
0
0
0
DCLK
Push/Pull PushlPull Push/Pull
FSC
Push/Pull Push/Pull Push/Pull
1
0
CP
Push/Pull Push/Pull Push/Pull Push/Pull Push/Pull
X2
PushIPull Push/Pull Push/Pull
Push/Pull
X1
Push/Pull Push/Pull Push/Pull
Push/Pull Push/Pull
XO
Push/Pull Push/Pull
SOO
Push/Pull Push/Pull Push/Pull
open
drain·
open
drain
Push/Pull
.) with integrated Pull-up
Siemens Components. Inc. \
364
open
drain·
open
drain
Push/Pull
PEB 2080
Table 4
SBC Clock Signals
Application
TE
TE
TE
LT-T
LT-T-
NT
LT-S
LT-S
LT-S
Operation
Of 10M
Interface
Inverted
Mode
Inverted
Mode
Normal
Mode
Mux
Mode
Inverted
Normal
Mode
Normal
Mode
Mux
Mode
Inverted
Normal
Mode
Normal
Mode
M2
M1
MO
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
1
1
1
1
0
0
1
1
0
1
1
0
DCLK
FSC
0:512kHz* 0:512kHz· 0:512kHz· i:4096kHz i:512kHz
1:2
1:2
2:1
0:8kHz·
63:1
0:8kHz·
63:1
0:8kHz·
i:8kHz
i:8kHz
CP
0:
0:
0:
1536kHz· 1536kHz· 1536kHz· 0:512kHz· 0:512kHz·
3:2
2:1
2:1
3:2
3:2
X2
0:
0:
2560kHz 1280kHz
1:2
1:2
X1
0:
0:
0:
3840kHz 3840kHz 3840kHz
1:1
1:1
1:1
i:512kHz
i:8kHz
i:8kHz
i:8kHz
1:1
i:8kHz
0:
192kHz
1:1
0:
0:
7680kHz 7680kHz
1:1
1 :1
XO
i: fixed
at 0
*) synchronized to S line
Siemens Components. Inc.
i:512kHz i:4096kHz i:512kHz
365
i: fixed
at 1
I
PEB 2080
Input and Output Pin Configurations
In TE, LT-T and LT-S 10M normal modes an integrated pull-up resistor is connected to SOL
For output pin configurations, see table 3.
AC Characteristics
TA = 0 to 70 DC, Voo = 5 V ± 5%
The AC testing input/output waveform is shown below.
Figure 17
2.4
2.0"
Device
Under
Test
2.0
.c
Test Points /
0.8
/
"-
0.8
0.45
Jitter
In TE mode, the timing extraction jitter of the SSC conforms to CCITT Recommendation 1.430
(-7% to + 7% of the S-interface bit period).
In the NT and LT-S applications, the clock input DCLK is used as reference clock to provide
the 192-kHz-clock for the S line interface. In the case of a plesiochronous 7.68-MHz-clock
generated by an oscillator,the clock DCLK should have ajitter of less than 100 ns peak-to-peak.
(In the case of a zero input jitter on DCLK, SSC generates at most 130 ns "self-jitter"
on S interface.)
In the case of a synchronous*) 7.68-MHz-clock (input XTAL 1), the SSC transfers the input
jitter of XTAL1, DCLK and FSC to the S interface. The maximum jitter of the NT/LT-S
output is limited to 260 ns peak-to-peak (CCITT 1.430).
*) fixed divider ratio of 15 between XTAL 1 and DCLK
Siemens Components, Inc.
366
PEe 2080
Clock timing
The clocks in the different operating modes are summarized in table 4, with duty ratios.
Clock CP is phase-locked to the receive S signal, and is derived using the internal DPLL
and the 7.68 MHz ± 100 ppm crystal (TR and LT-T).
A phase tracking of CP with respect to "S" is performed once in 250 (..I.s. As a consequence
of this DPLL tracking, the high state of CP may be either reduced or extended by one
7.68-MHz-period (CP duty ratio 2: 2 or 4: 2 instead of 3: 2) once every 250 ns.
Since DCLK and FSC are derived from CP (TE mode), the high state (FSC) or the high
or low state (DCLK) may likewise be reduced or extended by the same amount once
every 250 (..I.s.*)
The phase relationships of the auxiliary clocks are shown in figure 18.
Figure 18
Phase Relationships of Auxiliary Clocks
7.68 MHz
CP:1536 kHz*
-.I
* Synchronous to receive S, see 5.6.1 Duty ratio 3: 2 normally
X1:3840 kHz
X2:2560 kHz
X3: 1280 kHz
-.I
*) The phase adjustment may take place either in the sixth, seventh or eight CP cycle
counting from the beginning of an 10M frame in TE.
Siemens Components, Inc.
367
PES 2080
Tables S to 9 give the timing characteristics of the clock.
Rgure19
Definition of Clock Period and Width
O.8V
~-----~H----~~
~-----tWL------<~
~---------------~----------------~
TableS
XTAL1,2
Limit Values
Parameter
Symbol
min.
High phase of
crystal/clock
tWH
20
ns
Low phase of
crystal/clock
tWL
20
ns
Siemens Components, Inc.
368
max.
Unit
PES 2080
Table 6
DCLK
Limit Values
Parameter
Symbol
min.
typo
max.
Unit
(TE) 512 kHz
t po
1822
1953
2084
(TE) 512 kHz 2:1
tWHO
1121
1302
1483
(TE) 512 kHz 2:1
tWLo
470
651
832
(TE) 512 kHz 1:2
tWHo
470
651
832
(TE) 512 kHz 1:2
t WLO
1121
1302
1483
(NT, LT-S, LT-T)
tWHI
90
(NT, LT-S, LT-T)
tw LI
90
ns
ns
ns
ns
ns
ns
ns
Parameter
Symbol
min.
(TE) 1536 kHz
tPQ
(TE) 1536 kHz
t WHO
(TE) 1536 kHz
tWLO
(TE, LT-T)
t R, tF
Test
Conditions
ase ±100 ppm
ase ±100 ppm
ase ±100 ppm
ase ±100 ppm
ase ±100 ppm
Table 7
CP
Limit Values
typo
max.
Unit
Test
Conditions
520
651
782
240
391
541
240
260
ns
ns
ns
ns
ns
ns
ns
ns
ase ±100 ppm
ase ±100 ppm
ase ±100 ppm
eL = 100 pF
eL = 50 pF
ase ±100 ppm
ase ±100 ppm
ase ±100 ppm
281
20
10
(LT-T) 512 kHz
t po
1822
1953
2084
(LT-T) 512 kHz
tWHO
1121
1302
1483
(LT-T) 512 kHz
tw LO
470
651
832
Siemens Components, Inc.
369
PEB 2080
TableS
X1
Limit Values
Parameter
Symbol
min.
typo
max.
Unit
(TE) 3840 kHz
tPQ
-100 ppm
260
100 ppm
(TE) 3840 kHz
tWHQ
120
130
140
(TE) 3840 kHz
tWLQ
120
130
140
ns
ns
ns
Parameter
Symbol
min.
typo
max.
Unit
ns
ns
ns
270
100 ppm ns
ns
270
ns
531
Test
Conditions
OSC ±100 ppm
OSC ±100 ppm
OSC ±100 ppm
Table 9
X2
Limit Values
(TE) 2560 kHz
tPQ
-100 ppm
391
(TE) 2560 kHz
tWHQ
110
130
(TE) 2560 kHz
tWLQ
250
260
(TE) 1280 kHz
tPQ
-100 ppm
781
(TE) 1280 kHz
tWHQ
250
260
(TE) 1280 kHz
tWLQ
511
521
Siemens Components, Inc.
370
Test
Conditions
100 ppm
OSC ±100 ppm
150
OSC ±100 ppm
OSC ±100 ppm
OSC ±100 ppm
OSC ±100 ppm
OSC ±100 ppm
PEB 2080
CP, DCLK and FSC Relationships in 10M Master Mode
7.68 MHz
CP: 1536 kHz *
--1
* Synchronous
to receive S, see 5.6.1 Duty ratio 3: 2 normally
X1:3840 kHz
X2:2560 kHz
X3: 1280 kHz
--1
Limit Values
Parameter
Symbol
min.
max.
Unit
Test
Conditions
Clock delay CP - DCLK
tD C
0
50
ns
CL = 100 pF
Clock delay CP - "FSC
tF C
0
50
ns
CL = 100 pF
Delay DCLK - FSC
tF D
-20
20
ns
CL = 100 pF
Siemens Components, Inc.
371
PEB 2080
10M Interface
Normal mode
Master mode (TE)
FSC(O) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
OCLI< (0)
-"---------~--
"----
+-_-+_..J."\.. __________L-L __ ..l~ ___ _
SOl
tlOot
SOO
________~X~-------------~~~-Limit Values
Parameter
Symbol
min.
max.
Unit
Frame sync delay
CL = 100 pF
fF D
-20
20
ns
10M output data delay
f lOD
200
ns
CL = 100 pF
10M input data setup
fils
20
ns
10M input data hold
fliH
50
ns
Siemens Components, Inc.
372
PEB 2080
Slave Mode (NT, LT-5, LT-T)
IOM®Frame Un"
(.. .• B* Channel)
IOM®Frame"n+1"
(B1 Channel •... )
:.~. . . . . '.:.~~" ".:.~~ e. I.~.:.:"
e .......
eo:••: : ••
":'.:.~"
":.<" ":.:.~' ",:,:.:. "':.:.~
e.
"':.:.~ e •••~.:~ •••
OCLK(I)
lr---------=:c--.. . .Xr-------~
___1tIlSt-- __ ......
SOl
--~=c=l-
_oJ
SOO
'--------c=:l=~-J ~ _______L -
__________________
~x~
____________
Limit Values
Parameter
Symbol
min.
30
50
40
2150
Frame sync hold
fF H
Frame sync setup
fF S
Frame sync high
f FWH
Frame sync low
f FWL
10M output data delay
f loo
10M input data setup
fils
10M input data hold
fliH
max.
ns
ns
ns
ns
200
20
50
Unit
ns*)
ns
ns
") For push-pull output. For open drain output with integrated pull-up resistor. the maximum value is
900 ns.
Siemens Components, Inc.
373
I
PEB 2080
Inverted Mode
OCLK(O)
FSC(O)
SOl
Bit 3 Channel B x
Bit 4 Channel B x
Bit 5 Channel B x
Limit Values
Parameter
Symbol
min.
max.
Unit
Frame sync delay
CL = 100 pF
tF so
-20
20
ns
10M output data delay
t loo
200
ns
CL = 100 pF
10M input data setup
tiiS
20
ns
10M input data hold
tliH
50
ns
Siemens Components, Inc.
374
PEB 2080
Inverted Mux Mode
OCLK (I)
FSC (I)
SOl
__/'oor____----..
SOO
~-----Ch-Q-n-ne-l-7-.B-it-2-7-(_B_it_2_51_)______J)(~_______
Limit Values
Parameter
Symbol
Frame sync hold
min.
max.
Unit
tF H
50
ns
Frame sync setup
tF S
20
ns
Frame sync high
t FWH
124.8
Frame sync low
t FWL
70
10M output data delay
CL = 150 pF; 10 L = 7 mA
troD
10M input data setup
t liS
20
ns
10M output data hold
tr rH
50
ns
Siemens Components, Inc.
375
!-L s
200
ns
200
ns
PES 2080
Timing of Special Function Pins
RST Characteristics
Limit Values
Parameter
Symbol
min.
Length of active (low) state
tWL
1
I max.
1
Unit
IlS
RDY Characteristics
DCLK
SOO _ _ _ _ _ _ _ _ _ _ _- J I ' - - - - . J '-_ _ _--' '___ __
ROY _ _ _ _-'
Limit Values
Parameter
Symbol
min.
Length of low state
tWL
360
Ils
Length of high state
tWH
60
Ils
Siemens Components, Inc.
376
max.
Unit
PEB2080
DE Characteristics
The form of the DE inpuVoutput (pin XC, NT mode) is given by figure 20 for the case of two S
interfaces having a minimum frame delay and a maximum frame delay, respectively.
Figure 20
NT
+5V
I--~r_---SDI
~-~~~~-SDO
DE
+5V
SUbscriber{
Line S
--+__.
--+---
I
DE
I
I
I
I
I
I
I
( to other SSC's)
I
The AC characteristics of DE output and input are shown in figures 21 and 22 and table10.
Siemens Components, Inc.
377
PEB 2080
Figure 21
Timing of DE Output
SIT - Frame
L
\
0
I
L
TE to NT
!>4=
CEB Output
t cEsO 1
I
1----1
Figure 22
Timing of DE Input
SIT -Frame
NT
Bn7
to TE
CEB Input
'*
BnB
------c~
~
E
1
IP>---
1
1 1 tCESH
1- tCEBs-1 1 - =
Table 10
Limit Values
max.
Unit
2
J..Ls
Parameter
Symbol
DE delay
CL = 100 pF
tOED
DE setup
tOES
5
J..Ls
DE hold
tOEH
0
J..Ls
min.
ECHO Characteristics
The timing of the ECHO output (pin X2, TE mode) is identical with that of output SOO:
however, the signal is "1" everywhere except in bit positions 24 and 25 ("O"-bit positions)
of 10M frame, where it is equal to the E-bits received from the S interface.
Siemens Components, Inc.
378
en
:! II
(ii'
3_.
3
::l
o...
en
()
o
3
-c
o
Binary Value:
CD
NT to TE
o L. F L.I~ B 1 ---IE
::l
::l
•
::l
•
1
""
•
•
---IE 0 AFA NI--B 2 - - I E 0 MI--B1 ---IE 0 S l - - B2 ---IE 0 L.F
1
0
1
0
•
}
•
.1
•
•
Subscribel
Lrne B:
•
.1
•
.0 •
.,
•
l:Pl1 IIIIIII I lJlJll I IIIIII Ulil IIIIII LIlIIIII III LPl
(0
TE to NT
Sampling Points of E-Bits to Transmit
Common DE-Pin:
t
~
t
I
0-
lI
Sampl ing Points of Received
D-Bits
Affected
by A
Condition:
•
Affected
by A
Minimum D
(2 Bits)
L.
oL. F L~_ _ B 1 ----1L. D L. FA L.I------ B 2 ---IL.O Lob--- B 1 ---IL.D LoI------ B 2 ---IL. D L. F L.
1
Co)
SubscribeR.
Line A:
lTll I I I I I I I I I I I III I I II I I I I I I I I I I I I I I I I I I I I I I I I I II I L
Binary Value:
N
~
0 L. F L.
•
•
l:Pl1 IIII II IllJlJlllll IIII LJlIII.11111 LR IIIIIIII Lrl
o L. F L.I--B1
c.>
0
oL. F L.I------ B 1 ---IL.O L. FA L.I------ B 2 ---!L.O L.i--- B 1 ---!L.O L.I--- B 2 --IL.D L. F L.
1..
.0 • •
.1 •
.1 •
.1 • •
TE to NT
NT to TE
sl--- B 2 ---IE
I
Binary Value:
Binary Value:
0 A FA NI--- B 2 ---IE 0 MI--- B 1 ---IE 0
0
1
BTl II IIII II II II II I I II I I I II I I I II I III II II IIII II II II L
_en
p
CO
C
~ ~
CD
}
Maximum 0
(8 Bits)
~
I
t
Affected
by B
I
t
Affected
by B
All Transmit Frames NT --TE are in Phase,
~
m
N
o
-
g:
PEB20SO
Adaptive Receiver Characteristics
The integrated receiver uses an adaptively switched threshold detector. The detector controls
the switching of the receiver between two sensitivity levels. The hysteresis characteristics ofthe
receiver are shown in figure 23.
Figure 24
Switching of the Receiver between High Sensitivity and Low Sensitivity
Logical 0
Logical 0
-225 mV
~'-"-I.~,"",
Logical 0
- 375 mV
1'"-~""''"4
Logical 0
CD
state
High sensitivity
with VTR 1 =! 225 mV
ill
state
Low sensiti vity
with VTR2 =:!:375 mV
Vmox > 1V and Vmox < -1 V
in two consecutive frames
CCD
750 mV
~
Vmox ~ 1V
Vmox < 750 mV or Vmox > -750 mV
750mV~ Vmax ~
VSR2 - VSR1 = Input voltage
VTR 1 • VTR2 = Threshold voltages of the receiver threshold detector
Vmox = maximum value of VSR 2 - VSR 1 during one frame
Siemens Components, Inc.
380
1V
SIEMENS
SIT Bus Interface Circuit Extended (SBCX)
Preliminary Data
PEB 2081
CMOSIC
Type
Ordering Code
Package
PEB 2081-N
PEB 2081-P
PEB 2081-P
Q67100-H6093
Q67100-H6091
planned
PL-CC-28 (SMD)
P-DIP-28
P-DIP-22
The SIT Bus Interface Circuit Extended (SBCX) PEB 2081 implements the four-wire SIT
interface used to link voice/data ISDN terminals, network termination (Central Office and
PBX applications), and PBX trunk lines to Central Office. Through selection of operating
modes, the device may be employed in all types of applications involving an SIT interface.
Two or more PEB 2081 SBCX can be used to build a point-to-point, passive bus, extended
passive bus or star configuration.
The PEB 2081 SBCX provides the electrical and functional link between the analog SIT
interface according to cCln recommendation 1.430 and T1 D1 Basic User Network Interface
Specification, respectively and the ISDN Oriented Modular (IOM®) interface Rev. 2.
The PEB 2081 SBCX exceeds both the electrical and functional requirements of the SIT
interface in order to provide high flexibility to the user with respect of SIT interface wiring
configuration and implementation of layer-1 maintenance functions. By provision of some
additional features at the IOM-2 interface the user is able to combine the SBCX with other
IOM-2 devices in various configurations.
The PEB 2081 SBCX is a 28-pin CMOS device offered in both DIP and PL-CC packages
It operates from a single 5 V supply and features a power-down state with very low power
consumption.
Features
• Full duplex 2B + D SIT interface transceiver according to cCln 1.430
• Adaptive equalizer
• Receive timing recovery
• Built-in wake-up unit for activation from power-down state
• Conversion of the frame structure between the SIT interface and IOM-2 interface
• Activation and deactivation procedures according to cCln 1.430
• D-channel access control, also in trunk application
• Access to Sand Q bits of SIT interface
• Automatic handling of Sand Q bit messages
• Software controlled maintenance interface (i/o ports)
• Frame alignment with absorption of phase wander in NT2 network side applications
• Switching of test loops
• Several operating modes
• Advanced CMOS technology
• Low power consumption: standby less than 6 mW
active max. 80 mW
381
PEB 2081
Logic Symbol
IOM®Z
Maintenance
Auxi I iary
Interface
MAl
(6:0 I
Mode
MODE
Mode
Specific
Functions
VooZ
SI T Bus
Interface Circuit
Extended
(SBCX)
PEB 2081
SR 1
SX Z
10nF
T
1000'
2. 1
[E.
'000 "
SX1
XTAL 1
X3
XZ
X1
XO
VOOA
Voo
Vss
VSSA
XTAL2
RST
+SV
+SV
OV
OV
Reset
=
1) Terminating resistors only at the far end
2) For details of crystal see figures 22 and 25
3) 10 nF required only for A1 silicon.
Further versions will have a symmetrical receiver.
Siemens Components, Inc.
[I.
Z ·1
SR Z
DCLK
FSC
lOP 0
lOP1
382
H
7,68MHz :t100ppm Z )
H
PEB 2081
Pin Configurations
(top view)
P-Dip-22
PL-CC-28
vee
Vee2
SX1
VSSA
SX2
SR2
Vss
SR1
X3
~
X1
FSC
X2
DClK
XO
IOP1
XTAl2
IOPO
XTAL 1
MAIO
MODE
OOLLJ-N
0..-0"""" ......
-J:2:~>c
SR1
VeeA
MAl6
MAl1
X1
X2
MAl4
XO
IPD 1
XTAl2
IPDO
MAIO
Siemens Components, Inc.
SR2
SR1
VeeA
MAl6
X1
MAIS
X2
MAI4
XO
o':>':>'
MODE
383
PEB 2081
Pin Definitions·and Functions
Pin No.
P-DIP-28
PL-CC-28
Pin No.
P-DIP-22
Symbol
Input (I)
Function
Output (O)
2
2
SX1
0
Positive transmitter output
3
3
SX2
0
Negative transmitter output
13
10
IDPO
I/O
10M Data Port 0
12
9
IDP1
I/O
10M Data Port 1
11
8
DCLK
I/O
Data clock, 10M interface
9
7
FSC
1/0
Frame Sync, 10M interface
15
12
MODE
I
Setting of operating mode
6
5
16
17
15
X3
X2
X1
XO
1/0
1/0
1/0
1/0
Functions dependant on the selected operation mode, see chapter 2.
MAl (6:4)
0
Maintenance output pins controlled by
monitor channel
20
22
18
23,21,19
5,8,10,14
11
MAl (3:0)
I
Maintenance input pins
16
13
XTAL1
I
Connection for external crystal, or input
for external clock generator
17
14
XTAL2
0
Connection for external crystal, n. c. when
external clock generator is used
25
19
SR1
I
Receiver, signal input
26
20
SR2
I
Receiver, Signal input
28
22
VOO2
0
2.5 V reference voltage output;
10 nFto Vss
27
21
VSSA
I
Analog ground
24
18
VOOA
I
Analog power supply +5 V ± 5%
1
1
Voo
I
Digital power supply +5 V ± 5%
4
4
I
Digital ground
7
6
Vss
-RST
I
Reset, active low
Siemens Components, Inc.
384
PEB 2081
Figure 1
Block Diagram
FSC
-----
Receive
Buffer
L.-
OPLL
L,ll~
o
Siemens Components, Inc.
385
SI Q Bit
Handler
OCLK
r--- IPO 1
r--- IPOO
PEB 2081
System Integration
The PEB 2081 SBCX implements the four-wire Sand T interfaces used in the ISDN basic
access. By programming the corresponding operating mode it may be used at both ends of
these interfaces.
The operating modes are:
ISDN
ISDN
ISDN
ISDN
terminals (TE)
network termination (NT)
subscriber line termination (LT-S)
trunk line termination (LT-T)
(PBX connection to Central Office).
The basic use of these modes is shown in figure 2 where the usual nomenclature as
defined by the CCITT for the basic access functional blocks and reference points, has been
used.
Figure 2
Operating Modes
Terminals
Exchange Termination
.--_-.;T,;;,E
LT-5
~f----..-=I---+~-----ln
'--_-SA
I
I
....J
Network Termination
NT
TE
5
I
I
7
I
I
I
I
r---+--[,, u
~ II ,,,
I
NT1
/ NT2
~ ~B~' ~
LT-5
LT-T
Siemens Components, Inc.
T
I
~
NT
,,
,
I~
386
PES 2081
Terminals and Network Terminations
By adding IOM-2 compatible devices to the PEB 2081 SBCX different configurations
are possible ranging from the standard TE and NT implementations shown in figure 3 and 4
to more complex applications.
Figure 3
ISDN Voice/Data Terminal using the IOM-2 Architecture
PEB 2081
IOM®- Terminal Interface
SB(X
PEB 2070
PSB 2160
PSB 2110
1((
ARCOFI®
ITA( ™
Figure 4
Network Termination with only two Devices
u
PEB 2091
10M ® Interface
IE(- Q
Siemens Components, Inc.
PEB 2081
SB(X
387
PEB 2081
A more complex application is a microcontrolled NT using the PES 2070 ICC to provide
software controlled layer-1 maintenance functions (figure 5). The U and SIT interface
maintenance data is conveyed via the 10M interface's monitor channel to the PES 2070 ICC.
Figure 5
The ~C Controls all Layer-1 Maintenance Functions of the NT
u
PES 2091
IOM® -2 Terminal Interface
PES 2081
IEC- Q
SSCX
PES 2070
ICC
More terminal functions can be added to the NT resulting in a U interface terminal with an SIT
interface terminal (intelligent NT) (figure 6). The functionality of such a configuration includes
O-channel collision resolution in upstream direction and S channel switching functions for
internal communications.
Figure 6
An Intelligent NT Provides Both Terminal (voice/data) and Network
Terminating Functions (SIT interface)
PES 2081
SBex
IOM®-2 Terminal Interface
I - - . - - -.......----.-~
PSB2160
ARCOFI®
PSB2110
lTAC ™
Siemens Components, Inc.
PEB 2095
IBC
PEB2070
ICC
388
Two Wire
U Interface
PEB 2081
Line Terminations
The standard implementation of an SIT interface line card includes one D-channel controller.
per line. Due to the SIT interface's ECHO bit function this can be reduced to one D-channel
controller per up to eight lines. The PEB 2081 SBCX supports this architecture by handling the
ECHO bit externally as a common ECHO Bit (CEB) to all SIT interfaces (figure 7)
Figure 7
One LAP-D Controller is Sufficient for up to Eight SIT Interfaces.
IOM®2 Interface
PEB 2081
SBCX
PES 2055
EPIC™
PEB 2070
PEB 2081
SBCX
ICC
CEB
PEB 2081
SBeX
Siemens Components, Inc.
389
PEB 2081
SIT Interface Configurations
The adaptive equalizer integrated in the receiver of the PEB 2081 SBCX exceeds the electrical
requirements of the SIT interface. An overview of the different wiring configurations is given in
figure 8.
Since maximum attenuation of the line is not the limiting factor, the maximum length of a
point-to-point configuration depends on the round trip delay. For special applications it is possible to exceed this limitation by switching the upstream 0 channel to a transparent mode.
Obviously, the extended passive bus configuration benefits from the enhanced receiver characteristic resulting by increasing the loop length.
Figure 8
SIT Interfacing Wiring Configurations
(N.B.: ''TR" stands for terminating resistor of value 100 Q).
~-------l
II~
I~
< =2km
I"
~max( VCC1 0
SBCX ~
I
I
L~~!.-..! ___ J
--I
,-------1
~
~11
1
I
~Tl SBCX!
I
IA1
L ___N"!'0-!.:-~J
Point-to-Point Configurations
Short Passive Bus
1:=--
< = 1.5 km
< =35m
Extended Passive Bus
Siemens Components, Inc.
390
PES 2081
Functional Description
The PEB 2081 SBCX performs the layer-1 functions for the SIT interface of the ISDN basic
access.
SBCX Device Architecture and General Functions
The SBCX performs the layer-1 functions of the SIT interface according to CCITT recommendation 1.430 and T 101 Basic User Network Interface Specification, respectively. It can be used
at all ends of the SIT interface. Figure 9 depicts the device architecture.
Figure 9
SBCX Device Architecture
FSC
OCLK
IDP1
SX 1 - - - - I Transmitter 1 - - - - 1
SX 2
ropo
Activation
Control
S/Q Bits
Siemens Components, Inc.
Equalizer
Compa-
Filter
rators
391
Handler
PES 2081
The Common Functions for all Operating Modes
•
•
•
•
•
•
Line transceiver functions for the SIT interface according to the electrical specifications
of CCID 1.430;
Conversion of the frame structure between the 10M interface and SIT interface;
Conversion from/to binary to/from pseudo-ternary code.
Access to S and bits
Handling of S and channel messages
Level detect.
a
a
Mode Specific Functions
Receive timing recovery for point-to-point, passive bus and extended passive bus
configuration.
• SIT timing generation using 10M timing synchronous to system, or vice versa;
• D-channel access control and priority handling;
• D-channel echo bit generation by handling of the common echo bit.
• Activation/deactivation procedures, triggered by primitives received over the 10M interface or by INFO's received from the line;
• Frame alignment according to CCID 0.503;
• Execution of test loops.
•
Analog Functions
For both receive and transmit direction, a 2: 1 transformer is used to connect the PEB 2081
SBCX to the 4 wire SIT interface. The pseudo-ternary pulse shaping which meets the 1.430
pulse templates, is achieved with the integrated transmitter.
The integrated adaptive equalizer is designed to cope with all wiring configuration of the SIT
interface, point-to-point, passive bus, and extended passive bus. The maximum allowable line
attenuation is increased to more than 20 dB, with the corresponding distortion equalized, and
out-of-band noise suppressed.
The level detect block monitors the receive line and therefore initiates switching into power
down or power up state. Figure 10 depicts the analog connections of the PEB 2081 SBCX.
Siemens Components, Inc.
392
PES 2081
Figure 10
Connection of the Line Transformers and Power Supply to the SBCX
2 1
C;Xl
+5V
20 .. 40 rl
Voo
20 .. 40 rl
SX2
VOOA
PEB 20al
SBCX
10IJ F
E;'p,;,
10krl
Vss
SRl
Vss A
Voo2
GND
10IJF
T
SR2
2:1
f:"p';'
10 krl
Digital Functions
DPLL circuitry working with a frequency of 7.68 MHz ± 100 ppm in SIT interface master modes
generates the 192-kHz-line clock from the reference clock delivered by the network
(FSC: 8 kHz) and in SIT interface slave modes extracts the 192-kHz line clock from the
receive data stream.
The 7.68 MHz clock may be generated with the use of an external crystal between pins XTAL1
and XTAL2, or by an external oscillator, in which case XTAL2 is not connected.
The D-channel access procedure according to CCITT 1.430, including priority management, is
fully implemented in the SBCX. When used as an SIT interface master, the device generates
the E bits necessary for D-channel collision detection. The received D-bits are provided at pin
CEB (common echo bit) for a wired-AND connected NT star configuration.
The buffer memory serves to adapt the different bit rates of the SIT interface and the 10M
interface. In addition, in trunk line applications it absorbs the possible deviation between
two system clocks, according to CCITT 0.503 (slip detection).
In all applications, the PEB 2081 SBCX gives access to the Sand 0 bits via the monitor
channel. According to its specific S/O mode, it handles the Sand 0 channel messages
autonomously, i.e. without the aid of a j.LC (e.g. in Nn.
Siemens Components, Inc.
393
PEB 2081
Table 1
Operating Modes and Functions of Mode Specific Pins of the SBCX.
Application
TE
LT-T
NT
LT-S
MODE
i: Vss
i: Voo
i:Vss
i: Voo
DCLK
0: 1536 kHz1)
i: 512 kHz
to 8192 kHz
i: 512 kHz
to 8192 kHz
i: 512 kHz
to 8192 kHz
FSC
0: 8 kHz1)
i: 8kHz
i:8 kHz
i: 8kHz
X3
0:768 kHz1)
0: 1536 kHz1)
i/o:CEB
i/o:CEB
X2
i: Vss
i:ICN2
i: Voo
i:ICN2
X1
i: Vss
i:ICN1
i:Vss
i: ICN1
XO
o:PCK
i:ICNO
i:BUS
i:ICNO
1) synchronized to SIT interface
i: input
0: output
PCLK
BUS
CEB
Power Converter Clock
Bus configuration specified
Common Echo Bit in NT1 star
Note: Differentiation between LT-T mode and LT-S mode is done by software programming
of data bit 0 of the configuration register.
Siemens Components, Inc.
394
PEB 2081
Figure 11
Clocking of the SBCX in Different Operation Modes
u
SIT
I
I
I
I
I
I
I
I
rOM®·2 Slave
PES 2081
SSCX
rop 1 \ - - - - - - - - 1
lOPO 1--------<--1
IBC I IEC
I
I
I Central
I Network
I
..
I
I
I
512 kHz
8 kHz
768MHz
I
I
(a)
NT
S
rOM@.2 Master
I
I
I
I
I
PES 2081
SSCX
lOPO 1 - - - - - - - - 1
I
I
I
PES 2055
EPIC ™
Central
Network
..
512 kHz - 8192 kHz
8kHz
I
(b) LT-S
PES 2070
S
rcc
IOM®.2 Slaves
I
-----+-+-f---L---I IDPO
----+-+-1....----1 rOP1
1536 kHz
8 kHz
(c) TE
I
I
..
I
T
IDM®..2 Master
PEB 2055
EPIC ™
I
I
I Central
I Network
I
1-------...,--1 lOP 1
I
I
I
I
Central
Network
I
512 kHz - 8192 kHz
8kHz
I
I
(d) LT-T
Note 1: Reference clock (1536 kHz), may be used to drive NT2 clock generator.
Siemens Components, Inc.
395
...
PEB2081
Interfaces
SIT Interface
According to CCITT recommendation 1.430, pseudo-ternary encoding with 100% pulse width
is used on the SIT interface. A logical 1 corresponds to a high impedance level (no current),
whereas logical O's are encoded as alternating positive and negative pulses. An example is
shown in figure 12.
Figure 12
SIT Interface Line Code
01001100011
Binary Values
+V
Line Signal
OV
-V
One SIT frame consists of 48 bits, at a nominal bit rate of 192 kbitls. Thus each frame carries
two octets of 81, two octets of 82, and four O-bits, according to the 81 + 82 + 0 structure
defined for the ISDN basic access (total useful data rate: 144 kbitls). Frame begin is marked
using a code violation (no mark inversion). The frame structures (from network to subscriber,
and subscriber to network) are shown in figure 13.
Siemens Components, Inc.
396
PEB 2081
A multi-frame is realized by use of FA. N. and M bits in the NT to TE direction. Table 2 shows
the Sand Q bit positions within the multiframe.
Figure 13
Frame Structure at Reference Points Sand T (CCITT 1.430)
,-
o
48 Bits in 250 Microseconds
NT to TE
--I
0 L.F L.I--B1--jE 0 AFA NI------B2-----1E 0 MI---B1-IE 0 St---B2----IE 0 L.F L.
1
o
TE to NT
o L.F
L.I----- B1----~. DL.FA L.i---B2-IL.0 L.i---B1-IL. 0 LJ--- B2 - i L . D L.FAL.
l:Pl 1IIIIIIILflJIIIIIIIIIUIIIIIIIIIUIIIIIIIIIl::rl
It---
F = framing Bit
L = DC Balancing Bit
o = 0 - Channel Bit
E = 0- Echo-Channel Bit
F' = Auxiliary Framing Bit or Q- Bit
N = Bit Set to a Binary Value N =
r,:
B1
B2
A
S
M
= Bit within B-Channel,1
= Bit within B-Channel 2
=
Bit Used for Activation
= S-Channel Bit
= Multiframing Bit
Note, Dots Demarcate those Parts of the frame th.at are Independently DC-Balanced.
Siemens Components, Inc.
397
PEB 2081
Table 2
Sand Q Bit Position Identification and Multiframe Structure
Frame
Number
NT·to-TE
FA Bit
Position
NT·to-TE
M Bit
NT·to·TE
S Bit
TE·to·NT
FA Bit
Position
1
2
3
4
5
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
SC11
SC21
SC31
SC41
SC51
01
ZERO
ZERO
ZERO
ZERO
6
8
9
10
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
SC12
SC22
SC32
SC42
SC52
02
ZERO
ZERO
ZERO
ZERO
11
12
13
14
15
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
SC13
SC23
SC33
SC43
SC53
03
ZERO
ZERO
ZERO
ZERO
16
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
SC14
SC24
SC34
SC44
SC54
04
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ONE
ZERO
SC11
SC12
01
ZERO
7
17
18
19
20
1
2
etc.
Digital Interface
The PEB 2081 SBCX is provided with a digital (IOM-2) interface, for communication with
other ISDN devices to realize OSI layer-1 functions (such as a U transceiver) or upper
layer functions (such as ICC, ARCOFI, ITAC and EPIC).
The 10M interface is a four-wire serial interface with: a bit clock, a frame clock, and two
data lines per direction (figure 14).
The ISDN user data rate of 144 kbitls (B1 + B2 + D) is transmitted transparently in both
directions over the interface. In addition, it is necessary to interchange control information
for activation/deactivation of OSI layer-1 and maintenance functions. This information is
transferred using time division multiplexing of the 125 \-Ls SIT interface frame.
Siemens Components, Inc.
398
PES 2081
Figure 14
10M Interface Signals
FSC
FRAME
OCLK
CLOCK
IOM®
Slove
OU
o OUT
DO
DIN
FSC:
DCLK:
FRAME
CLOCK
DIN
IOM®
Moster
DOUT
Frame synchronization
Data clock
Data upstream
Data downstream
DU:
DD:
The basic frame consists of a total of 32 bits, or four octets: B1 + B2 + D (18 bits) plus
14 overhead bits for maintenance of monitor and control information. The data in both
directions is synchronous and in phase (figure 15).
Figure 15
10M Frame Structure
81
1st octet B1:
2nd octet B2:
3rd octet:
4th octet B*:
82
B channel (64 kbiVs)
B channel (64 kbiVs)
Monitor channel (64 kbiVs), most significant bit first
2 bit D channel (16 kbiVs)
4 bit C/I channel
MR, MX bit: used for monitor channel control.
The C/I channel is used for communication between the PEB 2081 SBCX and a processor
via a layer-2 device, to control and monitor layer-1 functions. The codes originating from
layer-2 devices are called "commands", those from the PEB 2081 SBCX are called "indications". For a list of the C/I codes and their use, refer to the SBCX Tech. Manual.
The monitor channel is used to convey Sand Q maintenance bit information and message
oriented local functions such as software programming or access to internal registers
(e.g. MAl-status).
Siemens Components, Inc.
399
PEB 2081
The PES 2081 SSCX has implemented the monitor channel protocol according to the
IOM-2 specification. It also performs a last look function on the monitor byte and, in transmit
direction, a monitor channel access procedure for bus configurations.
For the transfer of Sand Q channel information, the PES 2081 SSCX will autonomously start
the monitor channel procedure. Device internal registers are only transferred as a result of a
"read" command.
Nominal bit rate of data (IDP1 and IDPO):
256 kbitlsec
... 4096 kbitlsec
Nominal frequency of DClK:
512 kHz
... 8192 kHz
8 kHz
Nominal frequency of FSC:
For the exact electrical definition see page 419 and the IOM-2 interface specification.
Figure 16
Timing of Data and Clocks of the 10M Interface in the S12-kHz-Mode
DCLK
1512 kHz)
FSC
18 kHz)
1UU1JUUUUl.
---.J
~
____________~r--
IOP1
lOPO ---::::::..J.::.:.r.L..:.Ji.!:..1..::..t..::~c...1~...l-..L......JL.....L--L.-'-y--L-L.L-Ll.....L..L.-l--JLl.....L.LS~~~u.
Figure 17
Timing of Data and Clocks of the 10M Interface in the 4096-kHz-Mode
DCLK (4096 kHz)
FSC (8 kHz)
I
Frame Bit No.
lOP, (2048 kbit/s)
IOPO (2048 kbil/s)
I
I
250125112521253125412551 0 1 , 1 2 1 3 1 4 1 5 1 6 1
Siemens Components, Inc.
400
PEB 2081
Table 3
Allocation of 10M Channels
10M Channel No.
ICN2
ICN1
ICNO
Bit No.
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 ... 31
32 ... 63
64 ... 95
96 ... 127
128 ... 159
160 ... 191
192 ... 223
224 ... 255
Figure 18
Position of 10M Channels as a Function of Time-Slot Allocation in 4096-kHz-Mode
Frame (8 kHzl
IOM® Channel
Frame Slot No. 0
11
--~-------~---
Frame S lot No.1
11
- -- -{D-------- -(D---
Frame Slot No.2
11
------0---------0-
Frame Slot No.3
11
-------ill--------D
Frame Slot No.4
11
--------ffi--------
Frame Slot No.S
11
[IJ--------ffi-------
Frame Slot NO.6
11
--ffi--------ffi------
Frame Slot No.7
11
--
11
-0- -------IIJ----
IOP1 (2048 kbitlsl
IOPO (2048 kbitlsl
In TE mode, the data clock DCLK has a frequency of 1.536 MHz. As a consequence, the
10M interface provides three channels. The PEB 2081 SBCX only uses 10M channel 0, and
for O-channel access control, the CII field of 10M channel 2. The remaining two 10M channels
are for the use of other devices within the TE (figure 19).
Siemens Components, Inc.
401
PES 2081
Figure 19
Definition of the IOM-2 Terminal Interface
~
FSC
____________________
~r-
Data upstream
Data Downstream
B* _
1--
IOM® Channel 0
B*
--I--
IOM® Channel 1
B* in Channel 0
10,
B*in Channel 2
IE, E RD't; 1 , 1, 1 ,1 , 1
I
Downstream
B* in Channel 2
11, 1,
I
upstream
D,CII4,CII3CI12,CIII,MR,MXI
TIC -Bus
Siemens Components, Inc.
!
1
!
1
402
--1--
B*
IOM® Channel 2
--I
PES 2081
Absolute Maximum Ratings
Parameter
Symbol
Ambient temperature under bias
TA
o to 70
Limit Values
Unit
Storage temperature
Tstg
-65 to 125
°C
°C
Voltage on any pin with respect to ground
Vs
-0.4 to VDD +0.4
V
Power dissipation
PD
1
W
DC Characteristics
TA = 0 to 70°C; VDD = 5 V ± 5%; Vss = 0 V
All pins except SX1 ,2; SR1 ,2; XTAL 1,2; VDD2
Limit Values
Parameter
Symbol
min.
max.
Unit
L-input voltage
Test Conditions
VlL
-0.4
0.8
V
H-input voltage
VlH
2.0
VDD +0.4
V
L-output voltage
(IDP1 ,0 only)
VOL
V OL1
0.45
0.45
V
V
I OL
V
V
IOH =-400 IJ.A
IOH=-100IJ.A
12
rnA
0.8
rnA
VDD = 5 V
inputs at VSS/VDD
no output loads
10
rnA
H-output voltage
H-output voltage
V OH
Power } operational
supply
power down
current
Icc
Input leakage current
III
Output leakage current
Siemens Components, Inc.
V OH
2.5
VDD -5
110
403
I OL
= 2 rnA
= 7 rnA
o V:S: VlN:S:VDD
oV:S: Vour:S: VDD
PEB 2081
DC Characteristics
Pin SX1; SX2
Limit Values
Parameter
Symbol
min.
max.
Unit
Test Conditions
Absolute value of
output pulse amplitude
(VSX2-VSX1)
Vx
Vx
2.03
2.10
2.31
2.39
V
V
RL=
RL =
Transmitter output current
Ix
7.5
13.4
rnA
R L =5.6 (1)
Transmitter output impedance
Zx
10
kQ
80
kQ
inactive or during
binary one
(Voo = 0 ... 5 V)
during binary
zer0 2)
R L = 50 Q
50
(1)
400
(1)
Pin VDD 2
Receiver output voltage
2.4
2.6
V
Pin 5 R; SR 2
Receiver input impedance
Voo= 5 V
Voo= 0 V
PinXTAL1
H-input voltage
L-input voltage
Pin XTAL2
H-output voltage
VOH
L-output voltage
VOL
4.5
V
I oH = 5 rnA,
V
I oH = 5 rnA,
CL~50
0.4
CL~50
pF
pF
Notes: 1) Due to the transformers, the load resistance as seen by the circuit is four times RL .
,2) 80 ... 100 Q external resistance required
Siemens Components, Inc.
404
PEB 2081
capacitances
TA = 25 DC, Voo = 5 V ± 5%, Vss = 0 V
All pins except SX1,2
Limit Values
I max.
I7
pF
Co
10
pF
Co
50
pF
Symbol
Parameter
min.
Pin capacitance
Unit
SX1,2
Output capacitance against Vss
XTAL1,2
Load capacitance
Recommended Oscillator Circuits
r---I1--_--~6 XTAL 1
External
Oscillator
Signal
XTAL1
Cl
~_~~___~____~7 XTAL2
Crystal Osci llator Mode
Siemens Components, Inc.
N.C.
XTAL 2
Driving from External Source
405
PEB 2081
Clock Signals of the SBCX. Duty Ratios are Indicated High: Low
Operating Mode
DCLK
FSC
1E
LT-T
NT
LT-S
0: 1.536 MHz
i: 512 kHz
i: 512 kHz
i: 512 kHz
3:2
to 6172 kHz
to 6172 kHz
to 6172 kHz
0: 8 kHz
i: 8 kHz
i: 8 kHz
i: 8 kHz
1 :2
X3
XO
0: 768 kHz
0: 1536 MHz
1 :1
3:2
0: 32 kHzl16 kHz
1: 1
Input and Output Pin Configurations
lOP (1 :0) are open drain outputs.
CEB is an open drain outpuVinput.
All other output pins are push/pull outputs.
AC Characteristics
TA = 0 to 70 DC, Voo = 5 V ± 5%
AC testing: inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0". Timing
measurements are made at 2.0 V for a logic "1" and at 0.8 Vfor a logic "0".
2.4
2.0"
Device
Under
Test
2.0
Test POints/
0,8
/
"-
0,8
0,45
Siemens Components, Inc.
406
PEB 2081
Jitter
In TE mode, the timing extraction jitter of the PEB 2081 SBCX conforms to CCID Recommendation 1.430 (-7% to + 7% of the SIT -interface bit period).
In the NT and LT-S applications, the clock input FSC is used as reference clock to provide
the 192-kHz-clock for the SIT interface. In the case of a plesiochronous 7.68-MHz-clock
generated by an oscillator, the clock FSC should have a jitter of less than 100 ns peak-to-peak.
(In the case of a zero input jitter on FSC, the PEB 2081 SBCX generates 130 ns "self-jitter"
on the SIT interface.)
In the case of a synchronous 7.68-MHz-clock (input XTAL 1), the PEB 2081 SBCX transfers
the input jitter of XTAL1 and FSC to the SIT interface. The maximum jitter of the NT/LT-S
output is limited to 260 ns peak-to-peak (CCID 1.430).
Clock Timing
The clocks in the different operating modes are summarized in table 4, with duty ratios.
The 1.536-MHz-clock is phase-locked to the receive S signal, and is derived using the
internal DPLL and the 7.68 MHz ± 100 ppm crystal (TE and LT-T).
As a consequence of this DPLL tracking, the high state of CP may be either reduced or
extended by one 7.68-MHz-period (duty ratio 2:2 or 4:2 instead of 3:2). Since X3 and FSC
are derived from DCLK (TE mode), the high state or the low state may likewise be reduced
or extended by the same amount.
Figure 20
Definition of Clock Period and Width
O.BV
_·_-t wL- - -
~---tWH---
~---------tp-------'------
Table 4 to 8 give the timing characteristics of the clocks
Table 4
XTAL1,2
Limit Values
Parameter
Symbol
min.
High phase of crystal/clock
max.
Unit
tWH
20
ns
Low phase of crystal/clock
tWL
20
ns
Clock period
tp
130.08
Siemens Components, Inc.
407
130.34
ns
PEB 2081
Table 5
DCLK
Limit Values
Test
typo
max.
Unit
520
651
782
240
391
541
260
281
ns
ns
ns
ns
ns
Parameter
Symbol
min.
(TE) 1.536 MHz
fpo
(TE) 1.536 MHz
f WHO
(TE) 1.536 MHz
f WLO
240
(NT, LT-S, LT-T)
fWHI
90
(NT, LT-S, LT-T)
fWLI
90
fpo
520
651
782
(LT-T) 1536 kHz
f WHO
240
391
541
(LT-T) 1536 kHz
f WLO
240
260
281
(TE) 768 kHz
fpo
1150
1302
1450
(TE) 768 kHz
f WHO
520
651
782
(TE) 768 kHz
f WLO
520
651
(TE) 32 kHz
fpo
31.1
(TE) 32 kHz
f WHO
f WLO
Conditions
OSC ±100 ppm
OSC±100 ppm
OSC ±100 ppm
Table 6
X3
(LT-T) 1536 kHz
OSC±100 ppm
782
ns
ns
ns
ns
ns
ns
31.25
31.4
I-Is
OSC ±100 ppm
15.4
15.6
15.8
I-Is
15.4
15.6
15.8
I-Is
asc ±100 ppm
asc ± 100 ppm
asc ±100 ppm
OSC ±100 ppm
OSC ±100 ppm
OSC ±100 ppm
asc ±100 ppm
Table 7
XO
(TE) 32 kHz
Siemens Components, Inc.
408
PEB 2081
Figure 21
DClK, BClK and FSC Relationship in TE Mode
OCLK(O)
FSC (0) _ _-!'
BCLK(O) _ _- J
-------~t----~rLimit Values
max.
Unit
Test
Conditions
-200
50
ns
CL = 150 pF
-200
50
ns
CL = 150 pF
Parameter
Symbol
min.
Delay DCLK - BCLK
tao
Delay DCLK - FSC
tFO
typo
10M Interface
TE Mode
Figure 22
Timing of the 10M Interface in TE Mode
IOM® Frame n
Channel 2
(. .. ,8 *-Channel)
FSC (0) _ _ _ _ _ _ _ _ _ _ _-,-_ _ _ _ _ _- - J
OCLK(O)
--~r----------~IDP1(1) _____ +-_"""I __ .L~ _________ L_..L_
-'Xr---_
___ _
.L~
---'X. . . . _________--'
IDPO(O) _ _ _ _ _ _ _ _
Siemens Components, Inc.
409
PES 2081
10M Interface in TE Mode
Limit Values
Parameter
Symbol
min.
Frame sync delay
tFO
-200
Data delay
too
typo
max.
Unit
Test
Conditions
-50
ns
CL = 150 pF
100
ns
CL = 150 pF
Data setup
tos
20
ns
Data hold
tOH
50
ns
TE Mode
NT, LT·S, and LT·T Modes
Figure 23
Timing of the 10M Interface in NT Mode
IOM® Frame n IOM® Frame n+1
Lost Channels First Channel
(.. .• 6
Channel) (61 Channel)
*-
FSC III
DCLK II)
~IPD1 (I) --~=DIPDO 10)
-------~--\"r------y-_______ 0-=_...1 '- ______ . L -
.::~------------------~X'-______
=================t
Siemens Components, Inc.
410
PEB 2081
10M Interface in NT Mode
Limit values
Parameter
Symbol
min.
Frame sync hold
tFH
Frame sync setup
tFS
Frame sync high
tFWH
30
70
130
Frame sync
t FWl
tOCl
Data delay to clock
tooe
Data delay to frame
tOOF
Data setup
tos
Data hold
tOH
typo
max.
Unit
ns
ns
ns
100
150
20
50
ns
ns
ns
ns
Timing of Special Function Pins
RST Characteristics
Limit Values
Parameter
Length of active (low) state
Symbol
--
rwL
-
min.
..
~~
f-+
I max.
Unit
I
Il S
CEB Characteristics
The form of the CEB inpuVoutput (pin X3, NT and LT·S mode) is given by figure 27 for
the case of two SIT interfaces having a minimum loop delay and a maximum loop delay,
respectively.
Siemens Components, Inc.
411
PEB2081
Figure 24
Star Configuration in NT and LT -S Mode
r-------------------
1
NT ILT-S
I
I
Subscriber
Line A
=tJI
t---+-1~--
ssex
DO
I---Hf--+----<- 0 U
[EB
Subscriber
Line B
Figure 25
Timing of CEB Output
The AC Characteristics of CEB Output and Input are shown in Figures 5.8-9 and Table 11.
SIT - Frame
L
\
0
I
L
TE to NT
[EB Output
Figure 26
Timing of CEB Input
SIT -Frame
NT to TE
[EB Input
_B_n_7---1~
Bn 8
---<~
~
E
iP>---
1
I 1 tCEBH
1 - tCEBS-i I--=-
Siemens Components, Inc.
412
PEB 2081
Table 8
Limit Values
typo
max.
Unit
Test
Condition
5
lis
CL = 100 pF
Parameter
Symbol
min.
CEB delay
tCEBD
3
CEB setup
t CEBS
5
lis
CEB hold
tCEBH
0
lis
Figure 27
Timing of CEB
o L.FL.I--- B 1 ~IE
Binary Value:
NT toTE
••
0 AFA N I - - S2 - - I E 0 MI---J31 - I E 0 sl---s 2 - I E 0 L.F L.
a
1
o L. F L . I - S 1 ~IL. 0 L. FA L . I Binary Value:
1
NT tolE
• •
•
•
.0
•
•
S 2 ---1L. 0
.1
L.I~ S 1 -IL.O L.I-•
.1
•
S 2 -IL.O L. F L.
.1 •
•
tPll III I 1111 LPJlIII I 1111 LIlli II I1II LIlIIIIII IllPL
TE to NT
Binary Vatue:
a
1
EPlI 1111111111111111111111111111111111111111111111 L
oL.F• L.I--S1---jE
OAFA NI---s 2 - I E 0 MI---Bl
•
1
0
-IE 0
1
sl- B2 - I E0 0 L.F• L.•
EPlI I111111111111111I1I11111111111111111111I111111 L
OL.F L.f---S1
1 •
•
Binary Value:
---IL.~ L.FAL.I--- S2 ~IL.O L.I___ B1 ---IL.OL.f---B 2 _IL.O L. FL.
.1
•
•
.1
•
.0
•
.1.
•
tPll 1I1I III I LPdlllll III I LIlli 1IIIIIlSlii III I II lPL
t
~
~
t
TE to NT
Sampling Points of E-Sits to Transmit
---'1
Common Echo Bit:
1......._ _
0Sampling Points of Received
O-Bits
Affected
by A
Condition,
All Transmit Frames
NT~TE
Siemens Components, Inc.
Affected
by A
are in Phase.
413
t
Affected
by B
t
Affected
by B
PEB2081
SIT Interface Transformer
The PEB 2081 SBCX is connected to the 4 wire SIT interface by use of two transformers.
Both sides of the transformers must be center tapped.
Transformer Model
The model parameters of the transformer are defined below (all measurements at 10 kHz):
primary to secondary transformer ratio:
primary total DC resistance:
1 : 2 ± 1%
R S; 10 Q
primary inductance:
primary inductance with secondary short-circuited:
primary capacitance with secondary open:
LM >20 mH
Lp<20~H
C<40 pF
Figure 28
Transformer Model
2:1
Lp
Ideal
Transformer
Transmitter Characteristics
The DC characteristics of the transmitter are given in page 419 and 420. Rising and falling
edges of pulses on 50 Q load are typically 300 ns.
Siemens Components, Inc.
414
SIEMENS
ISDN Echo-Cancellation Circuit
(IEC-T)
PES 20901
PES 20902
CMOSIC
Preliminary Data
Type
Ordering Code
PES 20901-C
067100-H8679
PES 20901-P
PES 20902-C
067100-H8678
067100-H8680
PSS·2"09Q'"N.·., ,:QI1,>f·OQa11$l'j,~,:,
Package
C-DIP-40
,,:f:(~~J
P-DIP-40
C-DIP-24
lIS 209Oi~',i;i/."~*~~iit¥~f4:1t.iJWt~lIIItIi
PES 20902-P
067100-H8681
P-DIP-24
The PES 2090 ISDN Echo-Cancellation Circuit (IEC-T) is an advanced CMOS circuit for
transmission over public telephone lines. The transmission technique used is according
to the UkO interface speCification of the Deutsche Sundespost. The adaptive filter concept
of the IEC-T is based on a highly digital approach which utilizes sophisticated digital signal
processing capability.
The PES 2090 enables digital full duplex voice/data transmission via the standard twisted
pair telephone cable (U interface) with a user bit rate of 144 kbitls according to the ISDN
standards. Together with the flexible IOM® interface, it is fully compatible to operate with the
PES 2070 (ICC) and PES 2080 (SSC) devices and also enables a repeater (two IEC's back
to back) for longer telephone loops.
The IEC-T is capable of operating in the following applications by means of pin strapping:
the exchange, the network termination, the terminal equipment, and the trunk module
connecting a PSX to the public network.
At present, the complete U interfac,e functions are available in a two-chip set.
Features
• Full duplex transmission and reception of the UkO interface signals according to the FTZ
Guideline 1 TR 220 of the Deutsche Sundespost (DSP).
• Adaptive echo cancellation.
• Adaptive equalization.
• Automatic polarity adaptation.
• Clock recovery (frame and bit synchronization) in all applications.
• Transposition ofternary to binary data (4S 3T) and vice versa (coding, decoding, scrambling,
descrampling, phase adaptation),
• Suilt in wake-up unit for activation from power-down state.
• Activation and deactivation procedure according to CCITI 1.430 and to FTZ Guideline
1 TR 210 of the DSP.
• Optimized for working in conjunction with SSC and ICC telecom IC's via 10M interface.
• Handling of commands and indications contained in the 10M CII channel for (de-)activation, supervision of power supply unit and equipment for wire testing.
• Data availability via the MONITOR channel.
• Switching of test loops.
• Generation of a synchronized 7.68-MHz clock for the SSC in the NT mode.
415
PEB 20901
PEB 20902
The IEC-T in a Two-Chip Set
A 'Digital' Circuit, called IEC-D (PES 20901) contains the digital receiver functions and the
IOM-U ko interface functions.
An 'Analog' Circuit, called IEC-A (PES 20902) contains the crystal oscillator and all of the analog
functions of the line port, namely the AID converter in the receive path and pulse shaping 01A
converter and line driver in the transmit path.
Pin Configurations
(top view)
PEB 2091 IEC Digital Part
PEB 20902 IEC Analog Part
Voo
TSP
TMO
TMl
APF
TM2
CL?O
TM3
TCL?
TM4
ROl
TMS
voo 0
24
A OUT
POOW
2
23
BOUT
GNO 0
3
22
CL120
RANGE
4
21
HOil
LOOP
5
20
HOl
V REF
6
19
N.C.
CL 15
?
18
GNO A
LEVEL
8
17
POM
X OUT
9
16
VOOA
N. C.
10
15
A IN
MPF
X IN
11
14
BIN
poow
BURST
GNO
12
13
Voo
RANGE
CLOCK
(L15
FRAME
POM
TP
LEVEL
LT
CL960
RO 2
D1SS
OOUT
RESQ
DIN
GNO
CLS
HOl
TM6
HOO
SLOT 0
TX
SLOT 1
IOM®.2
LOOP
PEB 20901
IEC-O
Siemens Components, Inc.
SLOT 2
416
PEB 20902
IEC-A
PEB 20901
Pin Definitions and Functions of PEB 20901
Pin. No.
Symbol
Input (I)
Function
Output (0)
19
RESQ
I
Power On Reset (active low) must be low at least 300 Ils.
The clock on CLOCK pin has to be applied during reset
in the LT modes and in NT-PBX mode. If not used,
the RESQ pin must be clamped to high.
40
TSP
I
Test Single Pulses. IEC transmits single pulses of equal
polarity spaced 1 ms (active high). If not used, the TSP
pin must be clamped to low.
10
IOM-2
I
Enable IOM-2 Mode. If pin is high, the IEC is in the
IOM-2 mode, otherwise it is in originallOM-1 mode .
18
. DISS
0
Disable Supply (active high).
30
MPF
I
Monitor Power Feed. Serial data of power feed current
(active high).
3
APF
I
Alarm Power Feed. Power feed overload with short
response time. If not used, the APF pin must be clamped
to low (active high).
6,24
RD1, RD2
0
Two pins to control independently two relay drivers.
They are set via 10M MONITOR channel.
GND
I
Ground-pin for digital functions of IEC.
1
Voo
I
Voo pin for digital functions of IEC.
26
TP
I
Testpin. Only for internal test purposes. Must be
clamped to low during normal operations.
2,39,38,
37,36,35,
34
TMO ...TM6 I
Testpins. Only for internal test purposes. Must be
clamped to high during normal operations.
5
TCL7
I
Testpin. Only for internal test. Must be clamped to low
during normal operation.
4
CL70
0
Testpin. Only for internal test.
25
LT
I
Programs the IEC-D to LT mode (LT pin high) or NT
mode (LT pin low).
29
BURST
I
Programs the IEC-D to 256-kbiVs-LT, LT -RP, NT,
NT-PBX, NT-RP, or NT-TE mode (BURST pin low) or
to 2048-kbiVs-LT-BURST, NT-PBX-BURST mode
(BURST pin high).
20
Siemens Components, Inc.
417
I
PEB 20901
Pin Definitions and Functions of PES 20901 (cont'd)
Pin No.
Symbol
Input (I)
Function
Output (0)
33,32,31
SLOTO,
SLOT1,
SLOT2
I
These pins program the IEC-D to the different
256-kbitls modes if BURST pin is low or assign the
time slot in the BURST modes.
22
DIN
I
10M data input synchronous to CLOCK.
23
DOUT
0
10M data output synchronous to CLOCK.
28
CLOCK
1/0
Double 10M data clock.
27
FRAME
I
10M frame signal.
21
CLS
1/0
In all LT modes: Power feed off signal from power
controller. Must be clamped to low, if not used.
In NT modes: 7.68-MHz clock output synchronized to
the line signal.
In NT-PBX modes: 512-kHz clock output synchronized to the line signal.
In TE (IOM-2) mode: 768-kHz clock synchronized to
the line signal.
In TE (lOM-1) mode: 1.536-MHz clock synchronized
to the line signal.
12
PDOW
0
Activates power-down mode of the IEC-A.
13
RANGE
0
Activates 6 dB attenuation for the ADC input signal.
11
LOOP
0
Activates the analog test loop.
17
CL960
0
960-kHz clock. The TX signal is derived from this clock
by dividing it by 8.
9
TX
0
120-kHz clock. The transmitted data are synchronized
to this clock. In the one-chip solution, this clock is
given out on pin TMO during normal operation.
7
TTD1
0
Ternary data to be transmitted.
8
TTDO
0
Ternary data to be transmitted. TTDO and TTD1 are
binary coded. The combination TTDO = 1 and TTTD1 = 0
is not used. They change with the rising edge ± 10 ns
of CL 120.
14
CL15
I
15.36-MHz clock.
16
LEVEL
I
Gives the polarity of the differential input signal and is
used to awake signal detection.
15
PDM
I
15.36 Mbitls output signal ofthe ADC in phase with C15.
Siemens Components, Inc.
418
PEB20902
Pin Definitions and Functions of PES 20902
Pin No.
Symbol
Input (I)
Output (0)
Function
2
PDOW
I
Activates power-down mode, only oscillator and level
detect are operating during power-down.
4
RANGE
I
Activates 6 dB attenuation for the ADC input signal.
5
LOOP
I
Activates the analog test loop.
22
CL120
I
120 kHz clock input. Transmitter is synchronized to this
clock.
20
TTD1
I
Digital input signal to the DAC.
21
TTDO
I
Digital input signal to the DAC. TIDO and TTD1 are
interchangeable. They must change with the rising
edge (± 10 ns) of CL 120.
7
CL15
0
15-MHz clock. Capacitive load should be minimized.
8
LEVEL
0
Detects the zero crossing of the differential input signal
and is used to activate the IEC-D.
17
PDM
0
15 MHz, 1-bit output signal of the ADC in phase with
CU5. Changes with rising edge of CL15 +2 .. 4 ns.
Capacitive load should be minimized.
15,14
AIN,BIN
I
Received line-signal from hybrid.
24,23
AOUT,
BOUT
0
Transmitted line-signal to hybrid.
3
DGND
I
Ground-pin for digital functions of IEC-A.
1
Vooo
I
Voo-pin for digital functions of IEC-A.
18
AGND
I
Ground-pin for digital functions of IEC-A.
16
VOOA
I
Voo-pin for digital functions of IEC-A.
12
GND
I
Ground-pin for digital functions of IEC-A.
13
Voo
I
Voo-pin for digital functions of IEC-A.
6
VREF
0
VREd)in to buffer internally generated voltage with
capacitor 10 nF versus AGND.
11
XIN
I
In all NT modes, crystal connection. In all LT modes,
15.36-MHz clock input synchronized to 10M clocks.
XOUT
0
In all NT modes, crystal connection. In all LT modes,
to be left open.
9
Siemens Components, Inc.
419
I
PEB 20901
PEB 20902
All digital outputs use positive logic and CMOS levels. Drive capability is 10 pF for CL 15
and PDM and 25 pF for LEVEL. All input signals are active high and use CMOS logical
levels. XIN and XOUT supply a load of 2-3 pF vs. ground to the crystal.
The maximum power consumption without load at CL15 is 15 mWin power-down mode,
100 mW with open outputs AOUT/BOUT and 150 mW during normal transmission.
The sensitivity of the ADC can be reduced, if necessary, by putting a resistor between
AIN and BIN (10 .. 20 kQ).
Application Diagram of IEC-D and IEC-A (Two-Chip Solution)
+SV
100nF
10 ... 100jJF
OV
+SV
OV
vee
TMO ... 6
TSP
APF
TP
DIN
DOUT
CLOCK
FRAME
SLOT 0
SLOT 1
SLOT 2
BURST
LT
MPF
CLS
OISS
RESa
GND
RD1
RD2
IOM@.2
RANGE
PDM
CUS
LOOP
CL 960
TX
LEVEL
PDOW
TTO 1
TTDO
Vee
Veee
Vee A
RANGE
POM
CL1S
LOOP
N.r.
CL 120
LEVEL
PDOW
lTD 1
OV
N.r.
X OUT
T
X IN
GNOA
PES 20901
IEC-O
Siemens Components, Inc.
A IN
BIN
AOUT
BOUT
noo
VREF
TCL 7
CL70
GND
GNDD
GNDA
PEB 20902
IEC-A
420
HYBRID
15:'~
PES 20901
PES 20902
Operation Modes and Functions
10M Concept and Applications of the lEe-T
The IEC-T is designed to be used in: the Line Terminator (LT) part of the Digital Subscriber
Module (DSM), the Network Termination (NT), the Digital Trunk Basic Access (PBX) and in
the Terminal Equipment (TE).
Figure 1
Connecting S-8us to Public Network
Network Termination
I ~
3
line Termination
If(
SBC
2
Uko Repeater
NT
I
I
I
I
I
I
I
I
8-.-1
!
S Bus
IOM®1or·2
UkO
IOM®.1
IOM®.1
UkO
Figure 2
Connecting Private to Public Network
Network Termina tion T M 0
ICC
~
IEC
Line Termina tion
I
1 - - - - - - - - - - 1 '-_--'
NT - PABX
IOM®
Siemens Components, Inc.
421
PES 20901
PES 20902
Figure 3
Connecting Terminal Equipment within Private Network (1st Generation)
, Terminal Equipment
Private Exchange Line Termination
Voice I
Data
Module
Figure 4
Connecting Network Termination or Terminal Equipment to Exchange (2nd Generation)
Network Termination/Termination Equipment
Siemens Components, Inc.
Line Termination
422
PEB 20901
PEB 20902
To cater to these various applications, the IEC-T can be programmed via pin strapping
to different modes (see following table).
Table 1
Programming the IEC-T Operation Modes
Signal on Input Pin
LT
BURST
SLOT2
SLOT1
SLOTO
a
1
1
a
a
a
a
a
a
a
1
a
a
a
a
1
a
a
.
a
a
.
a
1
.
a
a
1
1
a
a
a
a
a
1
a
1
.
.
MODE
LT
LT-RP: Repeater downstream
LT-BURST: LT MUX mode
NT
NT-RP: Repeater upstream
NT-PBX: PBX continuous mode
NT-TE: Terminal Equipment
NT-PBX BURST: PBX MUX mode
.
Figure 5
Interfaces of the IEC-T
DIN
10M
Data
and
Clocks
BOUT
{ DOUT
Hybrid
CLOCK
AIN
FRAME
BIN
10M@.2
RD2 -
R01
b
-
VOOA
LT
Mode
Select,
Time
Slots
a
AOUT
VOO
BURST
VOO
lOOnF 10.. 1OOIlF
Vooo
GNDD
GND
GND
GNDA
MPF
APF
ClSS -----------4--1
CLS
-LT only
SLOT 2
SLOT 1
SLOT 0
Reset {RESQ
Test
Single
TSP
Pulses
XIN
15.36 MHz
v,"
1
Power
Supply
Feeding
Circuit
r
I
INT: Synchronized Clock
,
to SBC or PBX
• In these modes SLOT2, SLOT1 , SLOTa are used for selecting the time slot rather than the mode.
Siemens Components, Inc.
423
PEB 20901
PEB 20902
Mode Dependent Functions
Table 2
Mode Dependent Functions
Pin
LT
LTBURST1
LTBURST2
LT-RP
NT-RP
NT
LT
BURST
IOM-2
1
0
1
1
0
1
o or 1
1
1
1
0
0
0
0
0
0
0
Oor 1
SLOT 0
SLOT 1
SLOT 2
0
0
0
TimeSlot
select
TimeSlot
select
1
0
0
1
0
0
0
0
0
DIN
256kbiVs 2048
MbiVs
256 .. 2500 256kbiVs 256kbiVs 256kbiVs 256kbiVs 2048
MbiVs
MbiVs
256..2500 256kbiVs 768kbiVs
MbiVs
DOUT
256kbiVs 2048
MbiVs
256 .. 2500 256kbiVs 256kbiVs 256kbiVs 256kbiVs 2048
MbiVs
MbiVs
256 ..2500 256kbiVs 768kbiVs
MbiVs
CLOCK
512 kHz
IN
4096 kHz 512 .. 5000 512 kHz
IN
kHz iN
IN
512 kHz
OUT
512 kHz
OUT
512 kHz
IN
4096kHz 512 .. 5000 512 kHz
IN
kHz iN
OUT
FRAME
8 kHz
iN
8 kHz
IN
8 kHz
iN
8kHz
IN
8 kHz
1:1
OUT
8 kHz
1:1
OUT
8 kHz
IN
8 kHz
IN
8kHz
IN
8 kHz
1:1
OUT
CLS
PFOFF
IN
PFOFF
IN
PFOFF
iN
PFOFF
IN
7.68MHz
OUT
7.68 MHz 512kHz
OUT
OUT
512 kHz
OUT
512 kHz
OUT
1536MHz 768 kHz
OUT
OUT
XiN
15.36
MHz
15.36
MHz
15.36
MHz
15.36
MHz
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XOUT
NC
NC
NC
NC
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
Siemens Components, Inc.
424
NTPBX
NTPBXBURSTl
NTPBX-.
BURST2
NT-TEl
NT-TE2
o or 1
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
0
1
TimeSlot
select
TlmeSlot
select
1
0
1
1
0
1
1536 kHz
OUT
8 kHz
1:1
OUT
PEB 20901
PEB 20902
Survey of IEC Functional Blocks
Figure 6
Functional Block Diagram of IEC-T
MMS 43
Coder
Scrambler
Speed
Converter
Pulse
Shaping
DIA
Post
Filter
[>
~
~
I
Timing
Gen.
Providi ng all Blocks
with Clocks
t
Timing
Recovery
..-
Frame
MUX
2
to Ext.
Hybrid
~~
Awake
Signal
7.5 kHz
B+B+D
144kb Is
M-Bit
CLOCK
FRAME
DIN
IOM$
Interface
Unit
1
DOUT
B+B+D
144kb Is
+
Code
Errors
I--
Barker
Code
Control
Unit
Awake
Signal
Detection
r--
Coeff. Read
Coeff.
Adapt.
M-Bit
.--- Coeff. Adapt.
Speed
Converter
Descrambler
Decoder
Demux.
Siemens Components, Inc.
~
I--
I
r--
t
Equalizer
&
Detector
Echo
Canceller
AID
I-<~
Digital
AGC
425
~
Digital
Low
Pass
2
from Ext.
Hybrid
PEB20901
PEB 20902
Description of the Digital Module Interface
The IEC-T is provided with an 10M interface which operates in both a continuous and a burst
mode in order to interface units which realize OSllayer-1 functions like the SBC (PEB 2080)
and to layer-2 functions like the ICC (PEB 2070).
The IEC-T is designed for the original 10M interface (IOM-1), but with the IOM-2 pin it is
possible to give the IEC-T some physical features of the IOM-2 interface. Logically, the
IEC-T behaves like in IOM-1 mode.
There are three differences between IOM-1 and IOM-2 operation modes:
• In the BURST modes, IOM-2 frame synchronization is the same as in the 256-kbitls modes.
Additionally, the IEC-T enables clock frequencies on DCLK ranging from 512 to 5000 kHz
in increments of 8 kHz.
• Each E-bit (MX-bit) is reflected in the T-bit (MR-bit) in the next IOM-2 frame. For IOM-2
interfaces, the E-bit is always used to access the MONITOR channel, which is acknowledged in the T-bit.
• The transparent channel on UkO can't be used, because the T-bit is used for MONITOR
channel access.
All other features of IOM-2, like other CII and MONITOR channel codes, are not implemented in the IEC~T.
Figure 7
10M Interface in Different Applications of the IEC·T
FRAME
CLOCK
DIN
DOUT
In the
In the
In the
In the
In the
Exchange:
Repeater:
NT
TMD
TE
IEC
IEC
SBC
m
ICC
Siemens Components, Inc.
FSC
DCLK
DU
DO
FRAME
CLOCK
DIN
DOUT
ICC
IEC
IEC
ICC
IEC
426
PEB 20901
PEB 20902
Figure 8
10M Interface MUX Mode
I LI
/
FSC
/
DCl
/
DU or DO
/
DO or DU
FRAME
/
/
/
/
FRAME
111
/
CLOCK
/
/
CLOCK
/
1: :
/
/
DIN
/'
/
DOUT
I I I
/
DOUT
/
/
/
DIN
u
...J
r-
Up
Processor Interface
EPIC TM
to 8 x IEC
For each application, the ISDN data rate of 144 kbiVs (2 B + D) is transmitted transparently via
the modular interface. It is necessary to exchange control information for means of activation
and deactivation of 051 layer-1 functions and switching of testloops. In some applications,
access to maintenance information is additionally provided.
Siemens Components, Inc.
427
PES 20901
PES 20902
This information is transferred in a time multiplex procedure based on an 8-kHz framestructure (see following figure).
Rgure9
Frame Structure of the Digital Interface of IEC-T
DIN
--r--~~--~--~~--~--------~--------~------DOUT __
~I
B_1__~~___B_2__~___M_D_ni_tD_r__~I
~B·____~I ~B~1
____
____
__
~
/
I DID I(III (II ICIt I(II I TIE
A1
I
A2 A3 A4
Four octets are transmitted in each frame:
1st octet B1:
B channel (64-kbiVs data) MSB first.
B channel (64-kbiVs data) MSB first.
2nd octet B2:
MONITOR (8-bit monitor address for DIN, 8-bit monitor data with MSB
3rd octet:
first for DOUT.
2 bit D channel 16-kbiVs data
4th octet B*:
4 bit C/I channel.
T channel for 1-kbiVs transparent data with IOM-1 or for the handling
of the monitor channel with IOM-2 (MX-bit).
E extension bit for control of monitor channel and to hand over the
maintenance bit of UkO •
In the multiplexed modes, the 10M data of up to eight IEC-Ts are multiplexed. The data
streams consist of bursts of 4 octets per frame. The bursts are allocated to consecutive
time slots in a frame by the static inputs SlOTO, SlOT1, SlOT2. Outside of the allocated
time slot, the IEC-T must not read from DIN-pin and the DOUT-pin remains high impedance.
The next table indicates the allocations.
Table 3
Allocation of Time Slots in IOM-1 and IOM-2 Modes
Time Slot No.
SLOTO
SLOT1
SLOT2
Bit No.
0
1
2
3
4
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0 ... 31
32 ... 63
64 ... 95
96 ... 127
128 ... 159
160 ... 191
192 ... 223
224 ... 255
6
7
Siemens Components. Inc.
0
1
0
1
428
PEB 20901
PEB 20902
Clock Generation
The master clock is the clock signal with the highest frequency in the system.
NT Modes
The master clock is derived from a built-in orystal oscillator in the NT operating modes.
The crystal is connected to the pins XIN and XOUT. The maximum capacitive load at XIN
and XOUT is 60 pF each.
Nominal frequency:
15.36 MHz
Overall tolerance:
± 100 ppm
We recommend using a crystal (serial resonance) which meets the following specification:
Nominal frequency:
15.36 MHz
Overall tolerance:
±60 ppm
Load capacitance:
20 PF=
Resonance resistance:
200
Shunt capacitance:
7 pF
LTModes
In the LT modes, the timing signal is derived from the clock via an external phase locked
loop. The master clock is fed to pin XIN.
Nominal frequency:
15.36 MHz
Duty ratio:
0.4 ... 0.6
Rise and fall times:
<10 ns
Max. Difference of phase deviations
of master clocl - Vf 11'
I AGe
Il
'11'
I
DPLL
~
I
J
I
+_
Decoder~.Descrambler
SOl
J
Equalizer
Control
etup pins
2
5
10
4
3
3
7
12
6
4
XO
X1
X2
X3
X4
1/0
1/0
I
I
1/0
Multifunctional pins; mode specific functions
6
7
8
9
XTAL1
XTAL2
a
I
External crystal or o,xt~ ~nal oscillator input.
External crystal connection (n.c. when
external oscillator is used).
23
28
TST
I
Device test pin; not for general use; tie high
always.
22
27
DISS
a
Disable supply
9
11
RST
I
Hardware reset pin; active low
18
15
1
20
21,22
17,18
2
24
Voo
Vss
VSSA
I
I
I
I
Digital power supply 5 V ± 5%
Digital ground
Analog power supply 5 V ± 5%
Analog ground
19
23
VOO2
a
2.5 V output; connected to Voo via 10 nF
capacitor
connected to VSSA via 10 nF
capacitor
5;25
N.C.
VOOA
Siemens Components, Inc.
Input (I)
Function
Output (O)
Line transmitter, output t
Line transmitter; output 2
Line receiver
a
I
Serial data out
Serial data in
Serial data clock
Frame sync.
I
1/0
1/0
1
10M interface
Not connected internally
462
1 U interface
PEB 2095
System Integration
There are three operating modes:
LT: Line Termination i.e. in the Local Exchange/PBX
TE: Terminal Equipment i.e. in the Subscriber Terminal
NT: Network Termination
Two examples of LT mode are illustrated, one connected directly to the terminal, one connected
to a network termination. In the latter case, the terminal is connected over the S interface for
the network termination. Because of the multiplexing facility on the S-bus to eight terminals
may be connected to one network termination and hence to one subscriber line. In the
former case (without a network termination) only one terminal per subscriber line is possible.
The diagram also indicates that either the IBC or the IEC may be used for 2-wire transmission.
Choice is dependent upon the transmission line characteristics, but in general the IBC is
the more cost-effective for shorter range transmission applications (especially PBX).
In the LT mode, the IBC managers layer-1 functions and communicates over the 10M interface
with the ICC (ISDN Communication Controller) which handles most layer-2 functions. A
microprocessor (handling higher layer functions) controls and communicates with the ICC.
A similar configuration is required in the TE mode, employing the same division of tasks.
In the NT mode, however, the configuration is much different. In this case the network
termination is acting as an NT1 (according to CCITT notation). Figure 1 illustrates two possible
NT configurations.
Figure 1
NT Configuration
...__- - - - - - - - , . , - I S D N - - - -_ _ _ _..
·""'I_·I-----::--:-ISDN~-___t...
User Area
Central Office
NT
LT
I
T
...- - - - Interface
~---use of IBC
Siemens Components, Inc.
463
PEB2095
In both cases, NT1 refers to a simple layer-l translation between the U interface and the
SIT interface. This is achieved by the simple pairing of the IBC with an 10M compatible
S-bus interface circuit (e.g. the SBC PEB 2080).
In this configuration, no ICC or microprocessor is required because layer-2 and higher
are passed transparently through NT1. The 10M interface acts as an intermediate interface
common to both devices.
On the other hand NT2 in figure 1 differs from NTl .in that it includes higher level OSI
functions. It could, for example, be a PBX. In this case the PBX would be connected
directly over the S interface (not U interface) to the subscriber terminal(s).
Note:
Figure 1 illustrates the CCITI defintion of the U reference point i.e. between a local
exchange and a network termination. The direct connection of terminals to a PBX
over a 2-wire loop is not considered by CCITI since it is not in the public network
domain. Since the IBC can be used in both the afore,;.e,ltioned configurations,
this document, for simplicity, will use the term U reference point for both. Furthermore the term U interface will refer only to the time division multiplexing technique
for transmission over a 2-wire loop.
Functional Description
IBC Device Architecture and General Functions
The ISDN Burst Transceiver Circuit (IBC PEB 2095) performs the layer-l functions of the
time-division multiplex implementation of the U interface. This is a half duplex technique
(ping-pong) involving transmission by only one device at anyone time. Furthermore the
IBC acts a link between the U interface to the 10M interface and hence to other layer-l
or layer-2 devices within the system. Figure 2 depicts the device architecture.
Siemens Components, Inc.
464
PEB 2095
Figure 2
IBC Device Architecture
IOM® Interface
SOl
SOD
OCLK
FSC
I
I
I LD 1
I LD2
I
I
I
I
I
I
I
Interface Control Logic
AOPLL
=
I
Ll
AntiAliasing
Filter
Lowpass
Filter
I
U Interface (Line)
TC = Transmitter Clock
RC = Receiver Clock
MC = Master Clock
Siemens Components, Inc.
465
PEB 2095
Some of the relationships between the blocks of the device architecture and the IBC
functions outlined below can be traced at this stage. This section, however, will deal in
more detail with these relationships.
The following are the main functions of the IBC
• Activation/deactivation procedures. Activation may be initialized by either infos from the
line or primitives from the 10M interface
• To increase the quality of Signal received from the line, the receiver stage contains both
an adaptive amplifier and equalizer
• Synchronous timing must be maintained on both sides of the device. All internal clocks
are synchronized to the upstream data clock (system clock). All generated downstream
clocks are synchronized, in turn, to these internal clocks.
• Testing and diagnostic functions: Testloops may be closed, test signals may be generated.
Furthermore, the IBC must also link 2 different interfaces, the 10M interface and the
U interface. To do this transparently, the IBC must compensate for the following main
differences between them:
• The U interface is a burst mode interface while the 10M interface is continuous
• The frame structure and data transmission techniques on both interfaces are different
• The B channels are scrambled on the U interface and unscrambled on the 10M interface
• The clock rates are different and are transmitted in a different manner. In the U interface
the clock is impliCit in the data stream; in the 10M interface 2 separate clocks, DCLK
and FSC, must be provided.
Analog Functions
Figure 3 depicts the analog and power connections to the IBC. Both analog and digital
power may be connected to a single power source. The reference voltage V002 must be
linked by two 10 nF capacitors to Vss and VOOA • External to the transmitter and receiver
a transformer (ratio 1.25:1) and external resistance (REXT = 140 0 ± 1%) are connected
as shown. Voltage overload protection is achieved by splitting REXT into 120 0 and 20 0
(for current limitation) and adding clamping diodes. If required a resistor may be added
to the signal input line for current limitation.
The transmitter stage is realized as a voltage source with an internal resistance
Rj = 15 0 ± 40%. It delivers a pulse of amplitude 2 V ± 10% (O-to-peak). Assuming a
transformer winding resistance of the order of 1 0, the output resistance seen from the
U interface will be 100 O.
Referring again to figure 2, the receiver input stages can be seen. They consist of a variable
gain amplifier, to compensate for signal losses on the line (dynamiC range 30 dB). This is
followed by an anti-aliasing filter and a switched capacitor low pass filter. Finally a switched
capaCitor equalizer suppresses the out-of-band noise, which has passed the (anti-aliasing)
filter stage, while keeping the pulse distortion low (dynamic range 15.36 dB).
Siemens Components, Inc.
466
PEB 2095
Figure 3
IBC Analog Connections
Rp
Digital
Power
Input
Receiver
Voo
10 fJF
Vss
Voo 2
10nF
Analog
Power
Input
VOOA
Transmitter
VSSA
Note
VOO 2
is a 2.5 V Reference Output
Both the amplifier and the equalizer are adaptive. The amplifier has 128 possible settings
and the equalizer 8 (in this sense they are digital). The adaptive logic can be stopped by
externally setting the amplifier and equalizer over the 10M interface. Once set in this way,
the settings remain constant. The monitor channel can also be used to program some
other functions.
The level detection block monitors the receive line and informs the interface logic when an
incoming signal is present. It also monitors the test transmitter to perform a similar function
during test loop implementation.
Digital Functions
The DPLL circuitry works with an external oscillator or crystal of 15.36 MHz ± 100 ppm.
This is used to synchronize all bit and frame clocks with the incoming system clock
(Le. from upstream). In the LT mode, the system clock is supplied over the 10M interface.
Generation of half-bauded AMI pulses for the line is accomplished by deriving a synchronous
transmitter clock using the DPLL. At the NTITE end of the line, the data clock of 384 kHz
is implicitly received in the data stream and is extracted by the IBC. From this all synchronous
clocks are derived with the aid of the DPLL.
An incorporated finite state machine controls ISDN layer-1 activation/deactivation. This
includes wake signal recognition in the "deactivated" state.
Due to the burst nature of U interface communication and the continuous nature of communication on the 10M interface, a buffer memory is required to compensate for timing
differences.
The digital control logic also sets the adaptive coefficients on the AGC amplifier and the SC
equalization filter.
Siemens Components, Inc.
467
PEB 2095
Scrambler/Descrambler
B channel data on the U interface is scrambled to give a flat continuous power density
spectrum and to ensure enough pulses are present on the line for a reliable clock extraction
to be performed at the downstream end.
The IBC therefore, contains a scrambler and descramber, in the transmit and receive
directions respectively. The basic form of these are illustrated in figure 4 and figure 5.
The form is in accordance with the CCITI V.27 scramber/descrambler and contains supervisory circuitry which ensures no periodic patterns appear on the line.
Figure 4
IBC Scrambler
I Ds=DI <±l Os z-6eDsz~7
Scrambler
OUT
Os
Dsz-6
Dsz-7
Dsz-6 <±l Dsz-7
01
Scrambler
IN
FigureS
IBC Descrambler
Do =0 1= Ds(1ez- 6<±lDsZ-7)
•
Descrambler
IN
Os
Dsz-6
Do
Dsz-6 e Dsz-7
Descramb ler
OUT
Siemens Components, Inc.
468
Dsz-7
PES 2095
Interfaces
The IBC operates 3 interfaces:
• U interface
10M interface
• SLD interface
•
U Interface
Figure 6 demonstrates the general principles of the U interface burst mode communication
technique. A frame transmitted by the exchange (LT) is received by the terminal equipment
(TE) after a given propagation delay. The terminal equipment waits a minimum guard
time (5.2 J.Ls) while the line clears. It then transmits a frame to the exchange. The exchange
will begin a transmission every 250 J.Ls (known as the burst repetition period). However,
the time between the reception of a frame from the TE and the beginning of transmission
of the next frame by the LT must be greater than the minimum guard time. Communication
between an LT and an NT follows the exact same procedure.
Within a burst, the data rate is 384 kbitls and the 38-bit frame structure is as shown in
figure 4. The framing bit (LF) is always logical "1". The frame also contains the user
channels (2B + D). Note that the B channels are scrambled. It can readily be seen that in
the 250 J.Ls burst repetition period, 4 D bits, 16 B1 bits and 16 B2 bits are transferred in
each direction. This gives an effective full duplex data rate of 16 kbitls for the D channel
and 64 kbitls for each B channel.
The final bit of the frame is called the M bit. Four successive M bits, from four successive
U frames, constitute a superframe (figure 6). Three signals are carried in this superframe.
Every fourth M bit is a code violation (CV) and is used for superframe synchronization.
This can be regarded as the first bit of the superframe. From this reference, bit 3 of the
superframe is the service channel bit (S). The S channel bit is transmitted once in each
direction in every fourth burst repetition period. Hence the duplex S channel has a data
rate of 1 kbitls. It conveys test loop control information from the LT to the TE/NT and reports
of transmission errors from the TE/NT to the LT. Bit 2 and bit 4 of the superframe are T bits.
These constitute the 2 kbitls T channel which extends the T channel of the 10M frame
(figure 7) onto the U interface.
Siemens Components, Inc.
469
PES 2095
Figure 6
U Interface Transmission/Reception
r - - - - - - - - - - - f , -----------f>-=-t.,~~
...----------j
LT
\
\
\
\
\
~
\
\
\
\
\
\
\
\
I
\
I
I
I
I
I
I
I
I
!l
I
I
I
I
I
I
TE/NT
f,
fd
' - - - - - - - - - - - - 9 9 Il s - - - - - - - - - - - - f - - < . - I
LF Framing Bit
* M Channel
Superframe
Icvl Tis IT Icvl Tis I T Icvl
cv = Code Violation: for Superframe Synchronization
T
S
Timings: f,
fd
fg
= Transparent Channel (2 kbih/s)
= Service Channel'i'1 kbits/s}
= Burst Repetition Period = 250 ~s
= Line Delay
= 20.8 ~s max.
= Guard Time
= 5.2 Ils min.
The coding technique used on the U interface is half-bauded AMI code (Le. with a 50% pulse
width). Figure 7 illustrates the code. As can be seen, a logical '0' corresponds to a neutral
level, a logical '1' is coded as alternate positive and negative pulses. The figure also
illustrated how a code violation may be achieved (CV); either two successive positive
(as shown) or negative pulses.
Figure 7
Half-Bauded AMI Code
Binary Value
o
o
0
o
o
o
Line Signal
-V
Siemens Components, Inc.
470
PEB 2095
Absolute Maximum Ratings
Parameter
Symbol
Ambient temperature under bias
TA
o to 70
Storage temperature
Tstg
-65 to 125
°C
°C
Voltage on any pin with respect to ground
Vs
-0.3 to Voo +0.3
V
Limit Values
Unit
Line Overload Protection
The maximum input current (under overvoltage conditions) is given as a function of the
width of a rectangular input current pulse (figure 8).
Figure 8
Test Condition for Maximum Input Current
lBC
I
Condition: All Other Pins Grounded
tWI
Siemens Components, Inc.
471
PEB 2095
Figure 9
Transmitter Input Current
The destruction limits are given in figure 9
R1~250Q.
[
SOOA
I
I
-J.--
SOA
I
I
I
--+ - - - - - - "'""______
O,SA
I
I
~+__.__.___r__"•._11f--_r__,_,---,-"......---.,-- t WI
10-12
10-10 10- 8
10- 6
10- 4
10-2
15
Figure 10
Receiver Input Current
The destruction limits are given in figure 10
R1~250Q.
[
I
I
I
I
I
I
I
I
-t----------~----
'---+_-.---,--,-..,.---.---1--,-.----.----.- t WI
10-10
10-8
10- 6
Siemens Components, Inc.
10- 4
10- 2
15
472
PES 2095
DC Characteristics
TA = 0 to 70 DC; Voo = 5 V ± 5%; Vss = 0 V; VSSA = 0 V
Limit Values
Parameter
Symbol
L-input voltage
ViL
Vss-0.4 0.8
ViH
2.0
H-input ~oltage
L-output voltage 1)
L-output voltage 2)
min.
max.
Unit
Test Conditions
V
Voo+0.4 V
H-output voltage
H-output voltage
VOL1
VOL2
VOH
VOH
Power supply current operational
Icc
13
Power supply current power down Icc
1.3
mA
output loads.
Input leakage current
10
fJ.A
OV< ViN< Voo to OV
Output leakage current
0.45
0.45
2.4
Voo-0.5
III
I Lo
V
V
IOL=2 mA
I oL = 7 mA
V
V
I oH =-400 fJ.A
I oH =-200 fJ.A
mA
Voo = 5 V, inputs at
oV or Voo , no
10
fJ.A
OV 1.1 MHz
- minimum attenuation
> 1.1 MHz
- typical attenuation
Equalizer
30
35
- dynamic range
- resolution (8 settings)
Siemens Components, Inc.
0-15.36 dB
2.194
484
SIEMENS
ISDN Subscriber Access Controller
(ISAC-P)
PEB20950
CMOSIC
Preliminary Data
Type
Ordering Code
Package
PEB 20950-C
067100-H8613
C-OIP-40
......
§:, 067100-H8550
. ~~ '"
PEB 20950-P
~ P-OIP-40
The PEB 20950 ISACTM-P is a combination transceiver/HOLC controller for ISDN terminals
in a two-wire PBX environment. Transceiver functions are performed according to the
two-wire PBX industry standard Upo interface. This corresponds to all of the functions
available on the PEB2095 IBC. Similarly. the HOLC protocol is processed as described
for the PEB 2070 ICC. The ISAC-P represents both the IBC and ICC on a single IC.
Features
• Half duplex burst mode two-wire transceiver
• AMI line code
• Adaptive line equalization
• High-level support of LAPO protocol
• FIFO buffer (2x64 bytes) for efficient transfer of O-channel packets
• IOM® interface to other ICs
• Switching of test loops
• 8-bit J.LP interface
• Advanced CMOS technology
• Low power consumption
485
PEB 20950
ISACoP BloCk Diagram
]
IOM@
Interface
r-~A-:D~P~LL--l--~-~ Timing
IJP-Interface
o
Siemens Components, Inc.
486
PEB 20950
Pin Configuration
(top view)
P·DIPj C·DIP
Von
M1
A
RST
XO
X4
TST
X1
DlSS
XTAL 1
Ll
XTAL2
Vss •
X3
Voo ,
FSC
Voo
IDPO
PE8 20950
ISAC™ -P
IDP1
SIPIEAW
L01
LQi
Vss
INT
DCLK
ALE
SDClFSDISDS2
ES
SDAXISDS1
WR
SOAR
RD
AD7
VDO
AD6
ADO
ADS
AD1
AD4
AD2
AD3
Pin Definitions and Functions
Pin No.
Symbol
Input (I)
Function
Output (0)
1
Voo
I
Analog power supply (+5 V)
2
XO
0
Multifunctional Pin
M1 = 1: Software programmable output
M1 = 0: 3.B4-MHz clock output
3
X4
1/0
Multifunctional Pin
M1 = 1: PFOFF
M1 = 0: 2.56-MHz clock output
4
X1
0
Multifunctional Pin
M 1 = 1: 15.36-MHz clock output
M1 = 0: 1.536-MHz clock output in IOM-1 mode;
76B-kHz clock output in IOM-2 mode
P-.DIP
Siemens Components. Inc.
487
PEB20950
Pin Definitions and Functions (cont'd)
Pin No.
P-DIP
Symbol
Input (I)
Function
Output (0)
5
XTAL1
I
External Crystal or external clock input
6
XTAL2
0
External Crystal output
7
X3
I
Multifunctional Pin
M1 = 1: MPF input
M1 = 0: ENCK input
8
FSC
110
10M Interface Frame Synchronization
M1 = 1: 8-kHz input clock
M1 = 0: 8-kHz output clock
9
IDPO
110
10M Interface Data Port 0
LT application: Data upstream line
TE application: Data downstream line
10
IDP1
110
10M Interface Data Port 1
LT application: Data downstream line
TE application: Data upstream line
11
SIP/EAW
110
SLD Interface Port, IOM-1 mode
This line transmits and receives serial data at standard
TTL or CMOS level.
External Awake, terminal specific functions
If a falling edge on this input is detected, the ISAC-P
generates an interrupt andlor a reset pulse
12
INT
00
Interrupt Request
The signal is activated, when the ISAC-P requests
an interrupt.
The CPU may determine the particular source and
cause of interrupt by reading the ISAC-P interrupt
status register (ISTA, EXIR).
INT is an open drain output, thus the interrupt request
outputs of several ISAC-P's can be connected to
one interrupt input in a "wired-or" combination. This
pin must be connected to a pull up resistor.
13
ALE
I
Address Latch Enable
A high on this line indicates an address on the external
addressldata bus, which will select one of the
ISAC-P's internal registers. The address is latched
with the falling edge of ALE.
Siemens Components, Inc.
488
PEB 20950
Pin Definitions and Functions (cont'd)
Pin No.
P-DIP
Symbol
Function
Input (I)
Output (0)
14
CS
I
Chip Select
A low signal selects the ISAC-P for a read/write
operation.
15
WR
I
Write
This signal indicates a write operation. When CS is
active, the ISAC-P loads an internal register with
data provided via the address/data bus.
16
RD
I
Read
This signal indicates a read operation. When the
ISAC-P is selected via CS the read signal enables
the bus drivers to put data from an internal register
on the address/data bus.
17
Voo
I
Power supply (+5 V)
18
19
20
21
22
23
24
25
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Address Data Bus
26
SDAR
I
Serial Data Port A Receive
Serial data is received on this pin at standard TTL
or CMOS level. An integrated pull-up circuit enables
connection of an open drain/open collector driver
without an external pull-up resistor.
SDAR is used only if IOM-1 mode is selected.
27
SDAX/
SDS1
0
Serial Data Port A Transmit, IOM-1 mode
Transmit data is shifted out via this pin at standard
TIL or CMOS level.
Serial Data Strobe 1, IOM-2 mode
A programmable strobe signal, selecting either one
of two B/IC channels on IOM-2 interface, is supplied
via this line. After reset SDAX/SDS 1 remains at logical 0
until a write access to SPCR is made.
Siemens Components, Inc.
The multiplexed address data bus transfers data and
command/status information between the ISAC-P
and the IJ.P system.
489
PEB 20950
Pin Definitions and Functions (cont'd)
Pin No.
P-DIP
Symbol
Input (I)
Function
28
SCAlFSD
SDS2
0
Serial Clock Port A, IOM-1 timing mode 0
A 128-kHz data clock signal for serial port A is
supplied.
Frame Sync Delayed, IOM-1 timing mode 1
A 8-kHz synchronization signal, delayed by 1/8 of a
frame, for serial port B (IOM-1 interface) is supplied.
In this mode a minimal delay for B1 and B2 channels
is guaranteed.
Serial Data Strobe 2, IOM-2 mode
A programmable strobe signal, selecting either one
or two B/IC channels on IOM-2 interface, is supplied
via this line. After reset, SCA/FSD/SDS2 remains at
logical 0 until a write access to SPCR is made.
29
DCLK
1/0
10M Interface Data Clock
M1 = 1: input 512-kHz IOM-1 mode
input 4.096-kHz IOM-2 mode
M1 = 0: output 512-kHz IOM-1 mode
output 1.536-MHz IOM-2 mode
30
Vss
I
Ground (0 V)
31
L02
0
Line Transmitter Output
32
L01
0
Line Transmitter Output
33
Voo
I
Power supply (+5 V)
34
VOO2
0
2.5 V output; connected to both Voo and Vss via 10 nF
capacitor.
35
VSSA
I
Analog ground (0 V)
36
LI
I
Line Receiver Input
37
DISS
0
Disable Supply Indication
38
TST
I
Device Test Pin: tie always high
39
RES
1/0
RESET
A high signal on this input forces the ISAC-P into
reset state. The minimum pulse length is four clock
periods of DCLK.
If the terminal specific functions are enabled, the
ISAC-P may also supply a reset signal.
40
M1
I
Operating Mode for IBC-Part.
M1 = 1: IBC in LT mode
M1 = 0: IBC in TE mode
Siemens Components, Inc.
490
ICs for ISDN Terminals
les for ISDN Terminals
111-.
Siemens Components, Inc.
493
I
les for ISDN Terminals
Steps of Integration
As mentioned, the development of modularized chips has been made from a strategical point
of view to reduce development time, risk and effort; to enhance volume for cost reduction; and
to achieve high flexibility with regard to different system needs. In the follow-up step for
forward integration, the layer-1 and layer-2 functions consequently will be put together in
order to optimize the cost structure for high-volume applications. This step has been taken
into account in the present circuit topology and therefore will require little effort. Nevertheless,
the single components will continue to be available for realizing specific functions without
overheads. The combination of SBC and ICC will result in the ISDN subscriber access
controller with S interface (ISACTM-S); the IBC and ICC will result in the ISAC-P. Further
integration of these chips with the ARCOFI® -(audio ringing oodec filter) will lead to digital
telephone controller chips supporting the Sand U burst interface (OTC-S and OTC-P).
Integration Strategy
c::J
PEB 2080
S'Bus Interface Circuit
Transistors: 10,000
~.~
ARCOFI
~~
II
®
Digital Telephone Circuit
I
b~ ~:,l~'~'"l~: ' """ ~[::::::;~::::::]
~~~~~~r~"' ~'ro"" ~[:::::::~:::::]/
c:Jec/
r,'~,'l::~","" ,,,.~ '"""'".
Transistors: 45,000
Pins: 40
PEB 2095
ISDN Burst Transceiver Circuit
Transistors: 25,000
Pins: 22
Siemens Components, Inc.
494
m•• ,., ,.,,,,,", ''',"''
SIEMENS
ISDN Subscriber Access Controller (ISAC-S)
Preliminary Data
Type
PEB 2085
CMOSIC
Ordering Code
Package
The PEB 2085 ISACTM-S implements the four-wire SIT interface used to link voice/data
terminals to an ISDN.
The PEB 2085 combines the functions of the S-Bus Interface Circuit (SBC: PEB 2080) and
the ISDN Communications Controller (ICC: PEB 2070) on one chip.
The component switches Band 0 channels between the SIT and the ISDN Oriented Modular
(IOM®) interfaces, the latter being a standard backplane interface for ISDN basic access.
The device provides all electrical and logical functions of the SIT interface, such as:
activation/deactivation, mode dependenttiming recovery and D-channel access and priority
control.
The HDLC packets of the ISDN 0 channel are handled by the ISAC-S which interfaces
them to the associated microcontroller. In one of its operating modes the device offers high
level support of layer-2 functions of the LAPD protocol.
The ISAC-S is a CMOS device, available in a P-DIP-40 or PL-CC-44 package. It operates
from a single +5 V supply and features a power-down state with very low power consumption.
Features
Full duplex 2B + 0 SIT interface transceiver according to CCITT 1.430
Conversion of the frame structure between the SIT interface and 10M
Receive timing recovery according to selected operating mode
D-channel access control
Activation and deactivation procedures, with automatic wake-up from power-down state
Access to Sand Q bits of SIT interface
Adaptively switched receive thresholds
Frame alignment with absorption of phase wander in NT2 network side applications
Support of LAPD protocol
FIFO buffer (2x64 bytes) for efficient transfer of D-channel packets
8-bit microprocessor interface, multiplexed or non-multiplexed
Serial interfaces: IOM-1, SLD, SSI
IOM-2
• Implementation of IOM-1110M-2 monitor and CII channel protocol to control peripheral
devices
• IlP access to B channels and intercommunication channels
• B-channel switching
• Watchdog timer
• Test loops
• Advanced CMOS technology
• Low power consumption
•
•
•
•
•
•
•
•
•
•
•
•
495
I
PEB 2085
Figure 1
Logic Symbol
7,68MHz
! 100ppm
SOAX/SOS1
SOAR
SLO
SR1
SIT
SIP/EAW
OCLK
FSC1
CP/BCLK
SCAlFSO/SOS2
[IDR=
100Q *1
SX1
UFI
MO ... 1
XO ... 2
r--
*1 Terminating Resistors Only at
the Far Ends of the Connection
Siemens Components, Inc.
496
a
Special
Function
Pins
PEB 2085
Pin Configuration
(top view)
P-DIP-40
PL-CC-44
N
AD4
r-
c;
::0 Ui ::; ;;;N
:59 eee ee B B
a: r,... N
<>
«
0 0 C; 0
0
0
<>
0
:;;: 0VI 0« '"
« '"
« « « « « « «
AD3
~
AD 5
AD2
AD6
ADl
AD7
ADO
39
REi (OS)
WRIR/W)
RST
38
37
SIP/EAW/A5
36
SDAX/SDSl
WR
Vsso
DCLK
FSCl
FSC2
35
ALE
lOP 1
S(A/FSD/SDS2
cs
34
lOP 0
RST
ALE
PES 2085
Ml
lOP 1
SIPI EAW
0
SDAX/SDSl
SCAI FSD I SDS2
RB
SDAR
1 44 43 42 41 40
4
X2
Vsso
PES 2085
IOPO
DCLK
SX2
FS(l
SXl
FSC2
Voo
Ml
N. C.
X2
UFI
XO
SRl
Xl
SR2
MO
XTAL 1
CP/BCLK
XTAL2
INT
Siemens Components, Inc.
A4
22 23 24 25 26 27 28
,...
«
<>
X
~
X
<>
'w"' II--
.x: --' z
!2
0..
w
VSSA
497
.. N
~--'
~;:!
X
:;
I-«
X
a: ~
N
VI
VI
ES
33
SX2
32
sxi
31
30
N.L
29
UFI
voo
PEB 2085
Pin Definitions and Functions (cont'd)
Pin No.
p..DIP
Pin. No.
PL-CC
Symbol
Input (I)
Function
Output (0)
37
38
39
40
1
2
3
4
41
42
43
44
1
2
3
4
ADO/DO
AD1/D1
AD2/D2
AD3/D3
AD4/D4
AD5/D5
AD6/D6
AD7/D7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Multiplexed Bus Mode: Address/Data bus
Transfers addresses from the IlP system to
the ISAC-S and data between the IlP system
and the ISAC-S.
Non-multiplexed bus mode: Data bus.
Transfers data between the IlP system and
the ISAC-S.
34
37
CS
I
Chip Select. A "Low" on this selects the
ISAC-S for a read/write operation.
-
36
RIW
I
35
36
WR
I
Read/Write. When "High", identifies a valid
IlP access as a read operation. When "Low",
identifies a valid IlP access as a write operation (Motorola bus mode).
Write. This signal indicates a write operation
(Intel bus mode).
-
39
OS
I
36
39
RD
I
20
23
INT
00
Interrupt Request. The signal is activated
when the ISAC-S requests an interrupt. It is
an open drain output.
33
36
ALE
I
Address Latch Enable. A high on this line
indicates an address on the external address
bus (multiplexed bus type only).
10
11
VSSD
Digital ground
21
24
VSSA
28
31
VDD
-
23
22
26
25
XTAL1
XTAL2
0
24
25
27
28
SR2
SR1
0
26
29
UFI
0
Siemens Components, Inc.
I
I
Data Strobe. The rising edge marks the end
of a valid read or write operation (Motorola
bus mode).
Read. This Signal indicates a read operation
(Intel bus mode).
Analog ground
Power supply (5 V ± 5%)
Connection for crystal or external clock input.
Connection for external crystal. Left unconnected if external clock is used.
S Bus Receiver Input
S Bus receiver Output (2.5 V reference)
Connection for external pre-filter for S bus
receiver, if used.
498
PEB 2085
Pin Definitions and Functions (cont'd)
Pin No.
P-DIP
Pin No.
PL-CC
Symbol
Input (I)
Functions
Output (0)
29
30
32
33
SX1
SX2
0
0
S Bus Transmitter output (positive)
S Bus Transmitter output (negative)
31
32
34
25
IDPO
IDP1
I/O
10M Data Port 0, 1
1/0
7
8
SCA
0
7
8
FSD
0
7
8
SDS2
0
8
9
RST
1/0
Reset. A "High" on this input forces the
ISAC-S into reset state. The minimum pulse
length is four clock periods.
If the terminal specific functions are enabled.
The ISAC-S may also supply a reset signal.
12
13
FSC1
1/0
Frame Sync. 1
LT-S/NTILT-T: input synchronization signal,
IOM-1 and IOM-2 mode.
TE: a programmable strobe output, selecting
either one or two B channels on IOM-1
interface, IOM-1 mode.
TE: frame sync output, "High" during channel 0 on IOM-2 interface, IOM-2 mode.
13
14
FSC2
1/0
Frame Sync 2, IOM-1 mode.
LT-SILT -TINT: input synchronization signal
TE: programmable strobe output, selecting
either one or two B channels in IOM-1 interface.
Siemens Components, Inc.
Serial Clock Port A, IOM-1 timing mode O.
A 128-kHz data clock signal for serial port A
(SSI).
Frame Sync Delayed, IOM-1 timing mode 1.
An 8-kHz synchronization signal, delayed by
1/8 of a frame, for IOM-1 is supplied. In this
mode a minimal round trip delay for B1 and
Bs channels is guaranteed.
Serial Data Strobe 2, IOM-2 mode. A programmable strobe signal, selecting either one
or two B or IC channels on IOM-2 interface,
is supplied via this line.
After reset, SCAlFSD/SDS2 takes on the
function of SDS2 until a write access to SPCR
is made.
499
PEB 2085
Pin Definitions and Functions (cont'd)
Pin No.
P-DIP
Pin No.
PL-CC
Symbol
Input (I)
Function
Output (0)
11
12
OCLK
1/0
Data Clock. Clock of frequency equal to twice
the data rate on the 10M interface.
LT-S/LT-T: clock input 512-kHz IOM-1 mode
max 4096-kHz IOM-2
mode
TE: clock output
512-kHz IOM-1 mode
1536-kHz IOM-2 mode
NT: clock input
512 kHz
-
40
AO
I
Address Bit 0 (non-multiplexed bus type).
6
A1
I
Address Bit 1 (non-multiplexed bus type).
5
5
A2
SOAR
I
I
Address Bit 2 (non-multiplexed bus type).
Serial Data Port A Receive.
Serial data is received on this pin at standard
TTL or CMOS level. An integrated pull-up
circuit enables connection of an open-drainl
open collector driver without an external
pull-up resistor. SOAR is used only if IOM-1
mode is selected.
18
A3
I
Address Bit 3 (non-multiplexed bus type).
17
A4
I
Address Bit 4 (non-multiplexed bus type).
9
10
10
A5
SIP
I
1/0
9
10
EAW
I
Address Bit 5 (non-multiplexed bus type).
SLD Interface Port, IOM-1 mode. This line
transmits and receives serial data at standard
TTL or CMOS levels.
External Awake (terminal specific function).
If a falling edge on this input is detected,
the ISAC-S generates an interrupt and, if
enabled, a reset pulse.
6
7
SOAX
0
6
7
SOS1
0
5
-
Siemens Components, Inc.
Serial Data Port A Transmit, IOM-1 mode.
Transmit data is shifted out via this pin at
standard TTL or CMOS levels.
Serial Data Strobe 1, IOM-2 mode.
A programmable strobe signal, selecting either
one or two B or IC channels on IOM-2 interface, is supplied via this line.
After reset, SOAX/SOS 1 takes on the function
of SOS 1 until a write access to SPCR is
made.
500
PES 2085
Pin Definitions and Functions (cont'd)
Pin No.
P-DIP
Pin No.
PL-CC
Symbol
Input (I)
Function
Output (0)
14
18
15
21
M1
MO
I
I
Setting of operating mode
15
17
16
16
20
19
X2
X1
XO
liD
liD
I
Mode specific function pins
19
22
CP
liD
19
22
BCLK
0
Clock Pulses. Special purpose pin, IOM-1
mode and IOM-2 (except TE) mode.
Bit Clock. Clock of frequency 768 kHz, IOM-2
mode in TE.
Figure 2
Functional Diagram
SSI
S
I
I
I
I
ISDN
Basic
Access
~
I
Layer-1
Functions
---~---
Siemens Components, Inc.
501
I
~
PES 2085
System Integration
ISDN Applications
The reference model for the ISDN basic access according to CCITT I series recommendations
consists of
an exchange and trunk line termination in the central office (ET, L
a remote network termination in the user area (NT)
a two-wire loop (U interface) between NT and LT
a four-wire link (S interface) which connects subscriber terminals and the NT in the user
area as depicted in figure 3.
n
Figure 3
ISDN Basic Subscriber Access Architecture
ISDN
ISDN
Centra! Office
User Area
TE
t--
I
I
I
I
I
I
I
TE
,---
S
I
I
I
I
I
I
U
I
I
I
NT
I
I
NT1
I
I
\
\
\
~
IT
LT
I
I
I
ET
The NT equipment serves as a converter between the U interface at the exchange and the
S interface at the user premises. The NT may consist of either an NT1 only or an NT1 together
with an NT2 connected via the T interface which is physically identical to the S interface. The
NT1 is a direct transfomation between layer 1 of S and layer 1 of U. NT2 may include higher
level functions like multiplexing and switching as in a PBX.
The ISAC-S designed for the user area of the ISDN basic access, especially for subscriber
terminal equipment and for exchange equipment with S interfaces. Figure 4 illustrates the
general application of the ISAC-S.
Siemens Components, Inc.
502
PEB 2085
Figure 4
Applications of ISAC-S (ISDN Basic Access)
E(1)
~
I
:
,
[ TE(S)
I
PBX (NT2)
S
I
I
I
W- ~-rl
I
TE (1)
I
I
CP:: Control Processor
SN::Switching Network
I
~l
L...T_E_(
8 )--1~'" i
TE(1)
Direct Subscriber Access
(point-to-point,short and extended passive bus) S
I
I
I
I
I
U
I
8~
I
Terminal Applications
The concept of the ISDN basic access is based on two circuit-switched 64 kbiVs 8 channels
and a message oriented 16 kbitls 0 channel for packetized data, signaling and telemetry information.
Figure 5 shows an example of an integrated multifunctional ISON-S terminal using the
ISAC-S. The ISAC-S provides the interface to the bus and separates the 8 and 0 channels.
The 0 channel, containing signaling data and packet switched data, is processed by the
LAPO controller contained in the ISAC-S and routed via a paraliellJ.P interface to the terminal
processor. The high level support of the LAPO protocol is implemented by the ISAC-S
allows the use of a low cost processor in cost sensitive applications.
The 10M interface generated by the ISAC-S is used to connect diverse voice/data application
modules:
sources/sinks for the 0 channel
- sources/sinks for the 81 and 82 channels.
Siemens Components, Inc.
503
I
PEB 2085
Figure 5
Example of ISDN-8 Voice/Data Terminal
~ ~~ ~~
CISACTM-S
C PEB 20B5
..
~
<;
;.
ICC
PEB 2070
r
<;
IJC
Speech
Processing
ARCOFI®
PSB 2160
Data
Encryption
'r
7-
IData Module I I
HSCx
SABB252x
<;
Speech Modules
I
I
Data Modules
'7
I
Up to eight D channel components (ICC: ISDN Communication Controller PEB 2070) may be
connected to the D and CII (Commandllndication) channels. The ISAC-S and ICC handle contention autonomously.
Data transfers between the ISAC-S and the voice/data modules are done with the help of the
10M monitor channel protocol. Each V/D module can be accessed by an individual address.
The same protocol enables the control of 10M terminal modules and the programming of intercommunication inside the terminal. Two intercommunication channels IC1 and IC2 allow a
2 x 64 kbitls transfer rate between voice/data modules.
In the example above (figure 5), one ICC is used for data packets in the D channel. A voice
processor is connected to a programmable digital signal processing codec filter via IC1 and a
data encryption module to a data device via IC2. B1 is used for voice communication, B2 for
data communication.
The ISAC-S ensures full upward compatibility with IOM-1 devices. It provides the additional
strobe, clock and data lines for connecting standard combos or data devices via 10M, or
serial SLD and SSI interfaces. The strobe signals and the switching of B channels is programmable. Figure 6 shows the implementation of a basic ISDN feature telephone using the ISACS and the Audio Ringing Codec Filter (ARCOFI@: PSB 2160).
Line Card Applications
An example of the use of the ISAC-S on an ISDN PBX line card (decentralized architecture)
is shown in figure 7.
The ISAC-S is connected to an Extended PCM Interface Controller (EPIC PEB 2055) via an
10M interface.
Siemens Components, Inc.
504
PEB 2085
This interface carries the control and data for UP to eight subscribers using time division
multiplexing. The ISAC-S's are connected in parallel on 10M (IDPO output; IDP1, DCLK,
FSC1 as inputs), one ISAC-S per subscriber.
The EPIC performs dynamic Band D channel assignment on the PCM highways. Since this
component supports four 10M interfaces, up to 32 subscribers may be accomodated.
Microprocessor Environment
The ISAC-S is especially suitable for cost-sensitive applications with single-chip microcontrollers (e. g. 8048, 8031, 8051). However, due to its programmable micro interface and non-critical bus timing, it fits perfectly into almost any 8-bit microprocessor system environment. The
microcontroller interface can be selected to be either of the Motorola type (with control
signals CS, R/W, DS), of the Siemens/Intel non-multiplexed bus type (with control signals CS,
WR, RD) or of the Siemens/Intel multiplexed address/data bus type (CS, WR, RD, ALE).
Figure 6
Basic ISDN Feature Telephone
r----------------------,
I
I
I
I
I
l
I
I
I
PSB 2160
ARCOFI®
IOM®
PEB 2085
ISACTH-S
I
I
I
lE~------------t_" ----i--J
1--,..:.
LCD
Control
LCD
Display
7
7
~
00
Siemens Components, Inc.
80C51
80C188
505
Power
Controller
PSB 2120
IRPC
f--I --nI-
S-Bus
PEB 2085
Figure 7
ISDN PBX Line Card Implementation
S- Bus
S- Bus
5
5
System Interface
I
PEB 2085
ISAC™ -S(1)
I--_ _ _--IPCM
HWO
1--_ _ _- - 1 PCM HW 1
I
I
PEB 2085
ISAC ™ -S (8)
I
I
I
I
I
I
I
SAB 82520 1----1__----. PCM HW 0
HSCC or
SAB 82525 1----1__--1 PCM HW 1
HSCX
Siemens Components, Inc.
506
PEB 2085
Figure 8
5LO
55I
IOM~2
+5V
INT (INTX)
INT
RO
RO
80C51
(80C188)
WR
WR
ALE
(P5[X)
A15
[5
----
AS
Aq7
Ap7
ADO
ADO
Common Bus
A15 - AO, 07 - DO
Memory
Siemens Components, Inc.
5X1
WR
ALE
ALE
50
RO
507
ISAC™-S
5X2
PES 2085
5R1
I
0
0
I
5R2
I
PES 2085
Functional Description
General Functions and Device Architecture
The functional block diagram of the ISAC-S is shown in figure 9.
The left-hand side of the diagram contains the layer-1 functions, according to cCln I series
recommendations:
S-bus transmitter and receiver
riming recovery and synchronization by means of digital PLL circuitry
activation/deactivation
access to Sand Q channels
handling of D channel
test loops
send single/continuous AMI pulses (diagnostics).
Figure 9
Architecture of the ISAC-S
Ml
M2
IDPI
IDPO
~--~~~______________~~r----;---SDAR
r----{-- -- SDAX/SDSI
UFI
lice
XO-X2
CPI BCLK
DCLK
Siemens Components, Inc.
FSC2
ADO-AD?I
508
Control
PEB 2085
The right-hand side consists of:
the serial interface logic for the 10M and the SLD and SSI interfaces, with B channel
switching capabilities
the logic necessary to handle the D-channel messages (layer 2).
The latter consists of an HDLC receiver and an HDLC transmitter together with 64-byte deep
FIFO's for efficient transfer of the messages to/from the user's CPU.
In a special HDLC controller operating mode, the auto mode, the ISAC-S processes protocol
handshakes (1- and S-frames) of the LAPD (Link Access Procedure on the D channel) autonomously.
Control and monitor functions as well as data transfers between the user's CPU and the D
and B channels are performed by the 8-bit parallel J..LP interface logic.
The 10M interface allows interaction between layer-1 and layer-2 functions. It implements
D-channel collision resolution for connecting other layer-2 devices to the 10M interface,
and the C/I and monitor channel protocols (IOM-1/IOM-2) to control peripheral devices.
The timing unit is responsible for the system clock and frame synchronization.
Interface Modes
Two basic modes are distinguished, according to whether the ISAC-S is programmed to
operate with IOM-1 or with IOM-2 interface. This programming is performed via bit IMS in
ADF2 register.
IOM-1 Interface Mode (IMS
= 0)
The ISAC-S is configurable for the following applications:
ISDN Terminals
ISDN subscriber line termination
ISDN trunk line termination
(PBX connection to Central Office)
ISDN network termination
~
TE Mode
LT-S mode
LT-T mode
~
NT mode
~
~
Configuration is performed by pin-strapping (pins M1, MO), yielding different meanings to
the multifunctional pins (XO, X1, X2) as well as the clock and framing signal pins (DCLK,
FSC1, FSC2, CP) see table 1.
Siemens Components, Inc.
509
PEB 2085
Table 1
Operating Modes and Functions of Mode Specific Pins of ISAC-S PEB 2085 (IOM-1)
Application
M1 MO
DCLK
FSC1/2
CP
X2
X1
XO
0: ECHO
i: fixed
at 0
i: fixed
i:SSZ
0: 3840 kHz
0: 7680 kHz
I: CON
i: fixed
at 0
I: CON
TE
LT-S
0
1
0
0
0:512 kHz'
i: 512 kHz
0: 8 kHz'
i: 8 kHz
0: 1536 kHz'
i: fixed at 0
LT-T
NT
0
1
1
1
i:512kHz
i:512kHz
i: 8 kHz
i: 8 kHz
0: 512 kHz'
i:SCZ
* synchronized to S
i: input
0:
i: fixed at 0
i: fixed at 0
-
output
ECHO
Reproduces the E-bits received from the S interface synchronously to 10M frame
"D"-bits (bit pOSitions 24 and 25 of 10M frame). All other bit positions are binary 1.
CON
Connected to S bus.
SCZ
Send continuous binary zeros (96 kHz)
SSZ
Send single binary zeros (2 kHz)
Siemens Components, Inc.
510
PES 2085
Figure 10
Operating Modes of ISAC·S (IOM-1)
The different operating modes in relation to the timing recovery are illustrated in figure 10.
I
I
I
I
I
I
Clock Master
X~==============CI=Oc=k=M=as::te=1rI
...---~:........:....---SI.....,P
512,kbit/s
rS-IP- - - - - - - - ,
I
PEB 2050/52/55
PEB 2085
512kHz
I
I
T
4096 kHz
8kHz
SYSTEM INT.
LT - T Mode
Clock Master
~:==r==========~~:J5~12~k~b~it/~S:J~~~lI--~T
!
SIP
PEB 2085
I SLO
OCLK r-_5_12_k_Hz_---'
FS( 1r--------'-'.;.;.;.;;......
SO AX 1-...!12~8~k!!!bit~/s~__:;:=:_:__,
SOAR
128 kbit/s
128 kHz
I
.L
I
I
I SSI
I
I
+
TE Mode
I
I
r-----------~
SIP
I
:
I
Clock Master
KClOCk Slave
512 kbit/s ,....S-IP--------,
I
PEB 2050/52/55
PEB 2085
I
512kHz
I
I
I
T
!<
I
I
:
:
I
4096kHz
8kHz
SYSTEM INT.
LT-S Mode
Clock Master
Clock Slave
...----------,
IDPO ~.=;25~6~kH.:=.z__t
.--------------~
PEB 2085
25=.::6.:.:,:kH,:.=z--/
IOP1 t--..::.
PEB 2091
OCLK t---=5:.;,:12:..:,k::..:H=-.z--I
FSC 1
I
I
I
I
I
I
I
I
U
NT Mode
Siemens Components, Inc.
I
I
8kHz
S
I
511
PES 2085
IOM-2 Interface Mode (IMS == 1)
In this mode the 10M interface has the enhanced functionally of IOM-2. Moreover, the auxiliary
serial SSI and SLD interfaces are not longer available (as in IOM-1 mode), since they are
functionally replaced by the general purpose IOM-2 interface.
Table 2
Operating Modes and Functions of Mode Specific Pins of ISAC-S PEB 2085 (IOM-2)
Application
M1 MO
DCLK
FSC1
CP/BCLK
X2
X1
XO
i: fixed at 0
i:CON
i: fixed
at 0
i:CON
i: fixed at 0
-
TE
LT-S
0
1
0
0
0: 1536 kHz·
0: 8 kHz·
i: 8 kHz
0: 768 kHz·
0: ECHO
0: 3840 kHz
i: 4096 kHz
i: fixed at 0
0: 7680 kHz
LT-T
0
1
i: 4096 kHz
i: 8 kHz
0: 512 kHz·
NT
1
1
i: 512 kHz
i: 8 kHz
i:SCZ
i: fixed
at 0
i: fixed
at 0
i:SSZ
• synchronized to S
i: input
0:
output
ECHO:
Reproduces the E-bits received from the S interface synchronously to 10M frame
"D"-bits (bit positions 24 and 25 of 10M frame). All other bit positions are binary 1.
CON
Connected to S bus.
SCZ
Send continuous binary zeros (96 kHz)
SSZ
Send single binary zeros (2 kHz)
Siemens Components, Inc.
512
PES 2085
Figure 11
Operating Modes of ISAC-S (IOM-2)
The different operating modes in relation to the timing recovery are illustrated in figure 11.
I
I
I
I
I
I
I
I
t'\J
[lock Master
~
,...-------..,
IOPO t-----t_------.------!
IOP1 1--------1~--+-----~
I
I
I
PES 2085
I
I
I
1536 kHz
8kHz
I
'----------<_ 768 kHz
I
TE Mode
[lock Slave
.-------,
I
I
I
I
I
I
I
8~z
S
k:
I
I
IOPO
PES 2085
IOP1
[lock Master
2048 kbit/s
PES 2055
~-----I
4096kHz
I
I
I
[lock Master
LT-S Mode
X~==============[=IO=C=k=M::as::te::r=\
I
I
:
I
SYSTEM INT.
8kHz
S
IOPO
PES 2085
I
2048 kbit/s
PES 2055
IOP1 t - - - - - - I
4096 kHz
I
I
I
SYSTEM INT.
8kHz
T
LT - T Mode
!<
I
I
[lock Slave
,...-------..,
lOP 0
I
:
[lock Master
PES 2085
256 kbit/s
~------~
25:.:;6...:.:k;:.;bi.:.;.t/s::.......t
lOP 1 t--..:::
I
PES 2091
I
I
I
I
I
I
I
8kHz
U
NT Mode
Siemens Components, Inc.
I
I
I
512 kHz
I
S
I
513
PEB 2085
Interfaces
The ISAC-S serves three different user-oriented interface types:
parallel processor interface to higher layer functions
10M Interface: between layer 1 and layer 2, and as a universal backplane for'terminals
SSI and SLD interfaces for B channel sources and destinations (in IOM-1 mode only) .
.... p Interface
The ISAC-S is programmed via an 8-bit parallel microcontroller interface. Easy and fast
microprocessor access is provided by 8-bit address decoding on chip. The interface consists of 13 (18) lines and is directly compatible with multiplexed and non-multiplexed microcontroller Interfaces (Intel or Motorola type buses). The microprocessor interface signals are
summarized in table 3.
Table 3
Pin No.
P-DIP
Pin No.
PL-CC
Symbol
Input (I)
Function
Output (0)
37
38
39
40
1
2
3
4
41
42
43
44
1
2
3
4
ADO/DO
AD1/D1
AD2/D2
AD3/D3
AD4/D4
AD5/D5
AD6/D6
AD7/D7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Multiplexed Bus Mode: Address/Data Bus.
Transfers addresses from the .... p system to
the ISAC-S and data between the .... p system
and the ISAC-S.
Non-Multiplexed Bus Mode: Data Bus.
Transfers data between the .... p system and
the ISAC-S.
34
37
CS
I
Chip Select. A O' ("low") on this line selects
the ISAC-S for a read/write operation.
-
36
R/W
I
35
36
WR
I
-
39
DS
I
36
39
RD
I
ReadlWrite. At 1 ("high"), identifies a valid
.... p access as a read operation. At 0, identifies
a valid .... p access as a write operation
Siemens Components, Inc.
(Motorola bus mode).
Write. This signal indicates a write operation
(Intel bus mode).
Data Strobe. The rising edge marks the end
of a valid read or write operation (Motorola
bus mode).
Read. This signal indicates a read operation
(Intel bus mode).
514
PEB2085
Table 3 (cont'd)
Pin No.
P-DIP
Pin No.
20
23
INT
aD
Interrupt Request The signal is activated
when the ISAC-S requests an interrupt. It is
an open drain output.
33
36
ALE
I
Address Latch Enable. A high on this line
indicates an address on the external address
bus (Multiplexed bus type only).
-
40
AO
I
Address bit 0 (non-multiplexed bus type).
6
A1
I
Address bit 1 (non-multiplexed bus type).
5
A2
I
Address bit 2 (non-multiplexed bus type).
18
A3
I
Address bit 3 (non-multiplexed bus type).
17
A4
I
Address bit 4 (non-multiplexed bus type).
10
A5
I
Address bit 5 (non-multiplexed bus type).
Symbol
PL-CC
-
Input (I)
Function
Output (0)
ISDN Oriented Modular (10M) Interface
IOM-1
This interface consists of one data line per direction (10M Data Ports 0 and 1: IDPO,1).
Two additional signals define the data clock (DCLK) and the frame synchronization (FSC1/2)
at this interface. The data clock has a frequency of 512 kHz' (twice the data rate) and the
frame sync clock has a repetition rate of 8 kHz.
Via this interface four octets are transmitted per 125 f.l.s frame (figure 12). The first two
octets constitute the two 64 kbiVs B channels. In the ISAC-S the monitor channel (third
octet) serves:
for arbitration of the access to 10M-TIC bus on IPD1 in case severallayer-2 components
are connected together (figure 14).
to indicate the status on the S bus D channel (IDPO, bit 3 of the monitor octet), "stop/go"
for the exchange of data using the IOM-1 monitor channel protocol which involves
the E bit as data validation bit.
Siemens Components, Inc.
515
I
PEB 2085
Two bits in the fourth octet are used for the 16 bitls 0 channel. The controling and monitoring of layer-1 functions (activation/deactivation of the S interface ... ) is done via the command/indication bits. The T bis is not used in ISAC-S IOM-1 applications.
The last octet in the 10M frame is called the Telecom IC bus (TIC) because of the offered
busing capability.
Figure 12
IOM-1 Frame Structure
...- - - - - - - - - 125 I1 s -------~..
Bits 8
8
8
I-
Frome
Bl
B2
Monitor
I0 I
(I
I
I TIE
I
I
I
I
:
:
L-
I
I
I
I
I
layer 2 I layer I
I
: Bkbit/S)
I
L __ -<'----:~8"..kb,...."it:7/S)
:
I
IOr@.2
I
I
V
TIC Bus
:
L - - - - - -<'---:""32"""k"""bi"'"'"'
tl
I
I
L - - - - - - - - -<'---+:1"'"6:-:-kb"'"'it.,-J/S)O_Chonnel
I
L- - - - - - - - - - - - -
I
-<'---:1.,-64'-"'k"-:bi'"""'
tI
V
I
I
L--------------------<--+.:6~4k~bi~tIV
L - - - - - - - - - - - - - - _- - - - - - - - - -
-<
I
:64kbit/~
} MonitorChannel
B} Channels
I
IOM-1 Timing
In TE mode the 10M timing is intemally generated by DPLL circuitry from the S interface
and DCLK and FSC1/2 are outputs.
In LT-S, NT and LT-T modes the clock and frame synchronization signals are inputs.
The 10M interface can be operated either in timing mode 0 or in timing mode 1, selected
by SPM bit in SPCR register.
Timing mode 0 (SPM "'" 0) must be programmed when ISAC-S ism TE mode.
Timing mode 1 (SPM == 1) is only meaningfUl in exchange applications (LT-S, LT-T) when
the SLD is used.
Siemens Components, Inc.
516
PEB 2085
In timing mode 0 FSC1 and FSC2 should be connected to one another for correct operation
(when FSC1/2 are input, Le. in non-TE modes).
In timing mode 1 the 10M is synchronized by a frame signal FSD delayed in time with respect
to the frame sync pulse input via FSC1. This reduces the B channel round-trip delay time
when the SLD is used (figure 13).
For correct operation in timing mode 1, the output FSD should be connected to FSC2 input
(see figure 10).
Figure 13
IOM-1 Interface Signals
I
IOM®
Compatible
Communications
Controller
ISAC™-S
IDP1
IDPO
OClK
FSC1
FSC 2
IOPl
IOPO
lSAC™-S
OClK
FSC 1/2
!
i
I
TE Mode
Timing Mode 0
I
I
I
H
FSC (Syst.)
ClK (Syst.)
FSCl/2---t__
10M
IOM®
Compatible
Controller
I
I
®
IT-T.lT-S Mode
Timing Mode 0
r-
Frame---l
IIOM®
ISAC™ -S
FSC(Syst.1
ClK (Syst.l
-
FSCl
IDP'
IOPO
OClK
FSC 2
FSO
i
I
IOM®
Compatible
Controller
!
c----l
:
I
I
--h ~1/5 Frame Period
FSCl (System) ---.J I____
FSC 2 (IOM I
--------~
~I________~~
=I--------...Jn. . --
Siemens Components, Inc.
IT-T.LT-S Mode
Timing Mode 0
517
lOP 1 : = 256 kbit Is
IOPO: = 256 kbit/s
OCl : = 512 kHz
FSC:= 8kHz
PES 2085
The 10M interface has two different clocking states:
• Idle state
~
FSC1/2 and DCLK are disabled and both data lines are "High"
(Power Down)
.
• Clocked state
~
FSC1/2 and DCLK are enabled (Stand By) .
Unlike in digital exchange configurations, in which the 10M interface always remains in the
synchronized state, in terminal equipment both clocking states can be selected.
The idle state is reached if the CFS (Configuration Select) bit in register SQXR is set to "1"
and the SIT interface is inactive.
The transition from idle state to clocked state will be automatically initiated by an incoming
call from network side. An activation of the 10M interface from the subscriber end has to be
programmed by setting and resetting the SPU (Software Power Up) bit in the SPCR register,
before the 10M interface can be used (e.g. for the activation/deactivation procedure at the
S interface.
The arbitration mechanism implemented in the monitor channel of the 10M allows the access
of external communication controllers (up to 7) to the layer-1 functions provided in the
ISAC-S and to the D channel. (TIC bus; see figure 14). To this effect the outputs of the
controllers (ICC:ISDN Communication Controller 2070) are wired-or-ed and connected to
pin IDP1, a pull-up resistor being already provided in the ISAC-S. The inputs of the ICCs
are connected to pin IDPO.
Siemens Components, Inc.
518
PEB 2085
Figure 14
Applications of 10M Bus Configuration
~P
D- Channel
Telemetry I
Packet
Communication
I
I
I
I
I
I
ICC (7)
v.,.
I
I
I
I
I
I
I
I
I
I
I
I
S- Channel
Voice I Data
Communication
with D-Channel
Signaling
ICC (2)
I
Ai
""-T
I
I
I
I
I
I
j
I
I
E- Channel
IVD LAN
Appl ication
I
~
l-
I
J
J
E- Channel
Echo
J
...
:::>
I
J
I
S- Channel
Voice I Data
Communication
with D-Channel
Signaling
y
III
CD
J
DCLK
ICC(1) FSC
IDPO IDP1
I
J
I
I
I
J
ISAC™-S
I
I
I
I
~
~
oo
CCITT
S- Interface
I
IOM-2
The IOM-2 is a generalisation and enhancement of the IOM-1. While the basic frame structure
is very similar, IOM-2 offers further capacity for the transfer of maintenance information.
In terminal applications, the IOM-2 constitutes a powerful backplane bus offering intercommunication and sophisticated control capabilities for peripheral modules.
Figure 15
Channel Structure of IOM-2
81
82
Siemens Components, Inc.
Monitor
519
D
ell
MR
MX
PEB 2085
• The 64 kbitls channels, B1 and B2, are conveyed in the first two octets.
• The third octet (monitor channel) is used for transferring maintenance information. between
the layer-1 functional blocks (SBC, IBC, IEC) and the layer-2 controller.
• The fourth octet (control channel) contains
- two bits for the 16 kbitls D channel
- four command/indication bits for controlling activation/deactivation and for additional
control functions
- two bits MR and MX for supporting the handling of the monitor channel.
In the case of an IOM-2 interface the frame structure depends on whether TE- or non-TE
mode is selected, via bit SPM in SPCR register.
Non-TE Timing Mode (SPM = 1)
This mode is used in LT-S and LT-T applications. The frame is a multiplex of eight IOM-2
channels (figure 16), each channel has the structure in figure 15.
Thus the data rate per subscriber connection (corresponding to one channel) is 256 kbitls,
whereas the bit rate is 2048 kbitls. The IOM-2 interface signals are:
IDPO,1 : 2048 kbitls
DCLK:
4096 kHz input
FSC1:
8 kHz input
Figure 16
Multiplexed Frame Structure of the IOM-2 Interface in Non-TE Timing Mode
t - - - - - - - - - 1 2 5 ~s----------.j
FSC
OCLK
IPOO
CH 7
CH 0
IPDI
CH7
(HO
Siemens Components, Inc.
520
PEB 2085
The ISAC-S is assigned to one of the eight channels (0 to 7) via register programming.
The Timing Mode (SPM = 0)
The frame is composed of three channels (figure 17):
•
•
•
Channel 0 contains 144 kbiVs (for 28 + 0) plus monitor and command/indication
channels for the layer-1 device.
Channel 1 contains two 64 kbiVs intercommunication channels plus monitor and
command/indication channels for other IOM-2 devices.
Channel 2 is used for 10M bus arbitration (access to the TIC bus).
Figure 17
Definition of IOM-2 Channels in Terminal Mode
r
FSC
IOM® Channel 0
/
lOP a
I B1 1 B2
A
IOM® Channel 1
\/
IMONalolcl1O~~1
A
IOM® Channel 2
\/
Ie1 pC 2 IMON 11 C/11 ~~
"
S/G
1 1
\
I
lOP 1
SOS 1/2 _ _.L--..L_-,-_ _
TI_C_BU_S....11"""1...- _-_"TJ..-_-_"-1-'-_ _ _ _ _ _ _ _ _ _ __
The IOM-2 Signals are:
IOPO,1 :
768 kbiVs
OCLK:
1536 kHz output
FSC1:
8 kHz output.
In addition, to support standard combos/data devices the following Signals are generated
as outputs:
BCLK:
768 kHz bit clock
SOS1/2:
8 kHz programmable data strobe Signals for selecting one or both
BIIC channel(s).
The clocking states (idle/clocked) are identical to the IOM-1 case and are controlled in the
same manner via bits CFS and SPU.
Important Note: If the ISAC-S is configured in NT mode, the 10M frame structure is identical to that of the IOM-1 case.
Siemens Components, Inc.
521
I
PEB 2085
SSI (Serial Port A)
The SSI (Serial Synchronous Interface) is available in IOM-1 interface mode. Timing mode 0
(SPM = 0) and TE operation has to be programmed.
The serial port SSI serves as a full duplex connection to B- channel sources/destinations
in terminal equipment with a data rate of 128 kbiVs.
It consists of one data line in each direction (SOAX and SOAR), an 8-kHz strobe output
(FSC1 and/or FSC2) and the 128-kHz clock output (SOA).
Figure 18
Connection of B-Channel Sources/Destinations to the ISAC-S via SSI
SSI
I
a-Channel Source/Destination
/r-_ _ _ _ _ _...JA~_ _ _ _~,
ISDN'Subscriber Access
~
I
126l kbit /s
126 I kbit/s
1261 kHz
61 kHz
VlD
Module
SOAR
SDAX
SCA
FSC 112
I
B2
FSC 112 1)
ISAC TH.S
Timing Mode 0
TE Mode
I
[J Q
tJ [J
I
I
SSJ
SDAR.X
_ _ _ _~A~_ _ _ _ _ _~
S
B1
I
-.J
1) Default Polarity
(ADF 1 register)
This serial interface allows the connection of voice/data modules, such as serial synchronous
transceiver devices (USART's, ICC PEB 2070, HSCX SAB 82525, ITAC PSB 2110, ... ) and
various codec filters directly to the ISAC-S, as illustrated in figure 18.
By programming the AOF1 register it is possible to independently set the strobe signal
FSC1/2 polarities so that either B1 or B2 is selected by the V/O module.
The )JC system has access to B-channel data via the ISAC·S registers BCR1/2 and
BCX1/2.
The )JC access must be synchronized to the serial transmission by means of the Synchronous
Transfer Interrupt (STCR).
Siemens Components, Inc.
522
PEB 2085
SLD
The SLD is available in IOM-1 interface mode.
The standard SLD interface is a three-wire interface with a 512-kHz clock (DCLK), an 8-kHz
frame direction signal (TE mode: FSC1/2 output; LT-S/LT-T modes: FSC1 sync input), and
a serial ping-pong data lead (SIP) with an effective full duplex data rate of 256 kbiVs.
The frame is composed of four octets per direction. Octets 1 and 2 contain the two
B channels, octet 3 is a feature control byte, and octet 4 is a signaling byte (figure 19).
The SLD interface can be used in:
Terminal applications (TE) as a full duplex time-multiplexed (ping-pong) connection to
B-channel sources/destinations.
Codec filters, such as the SICOFI (PEB 2060) or the ARCOFI (PSB 2160) as well as
other SLD compatible voice/data modules may be connected directly to the lSAC-S as
depicted in figure 19. In TE applications timing mode 0 has to be programmed, hence
SLD operates in master mode. Moreover, terminal specific functions have to be deselected (TSF = 0).
Figure 19
Connection of B-Channel Destinations to the ISAC-S via SLD
9- Channel Source /Destination
/~
_ _ _ _ _ _~A~_ _ _ _~
i
I
_ _ _ _~A~_ _ _ _ _ _~
SIP
DCLK
FSC 112
I
I
SLD OUT
FSC 1/2
/~
I
512lkbit/s
512 kHz
8ikHz
SLD Compatible
Voice/Data
Module
SIP
ISDN Subscriber Access
SLD
SLD IN
I
91 192 1FC 1SIG 91 1 9 2 1FC 1SIG [
.-J
Siemens Components, Inc.
I
I
I
I
523
ISAC TH_S
Timing ModeO
TE Mode
0
tJ
I
S
Timing Mode 0
PEB 2085
Digital exchange applications (LT-S/LT-T) as a full duplex time-multiplexed connection
to convey the B channels between the SIT interface and a Peripheral Board Controller
(e.g. PBC PEB 2050 or PIC PEB 2052), which performs time-slot assignment on the PCM
highways, forming a system interface to a switching network (figure 20).
Timing mode 1 (SPM = 1) has to be programmed, hence SLD operates in slave mode.
Figure 20
Connection of the ISAC-S as B-Channel Source/Destination to a Peripheral Board
Controller via SLD
S
I
I
I
5121 k bitls
[]
SIP 1----+-----1
ISAC TH_S
I
5121 kHz
Timing OClK 1----+----1
Model
I
8 1kHz
FSC 11----1-__.--1
I
tJ
I
PBC
IT-SllT-T
ClK
" - - - - - - - -...
-
System Interface
SIP
FSC1
FSO
The IJ.C system has access to B-channel data, the feature control byte and the signaling
byte via the ISAC-S registers:
C1R, C2R
MOR1 and MOR2
CIR1 and CIR1
~
~
~
B1/B2
FC
SIG
The IJ.P access to C1R, C2R, MOR1/MOX1, CIR1 and CIX1 must be synchronized to the serial
transmission by means ofthe Synchronous Transfer Interrupt (STCR) and the BVS-bit (STAR).
Siemens Components, Inc.
524
PEB2085
Individual Functions
Layer-1 Functions for the ISDN Basic Access
The common functions in all operating modes are:
line transceiver functions for the SIT interface according to the electrical specifications
of CCID 1.430;
conversion of the frame structure between 10M and SIT interface;
conversion from/to binary to/from pseudo-ternary code;
level detect.
Mode specific functions are:
receive timing recovery for point-to-point, passive bus and extended passive bus configuration;
SIT timing generation using 10M timing synchronous to system, or vice versa;
D-channel access control and priority handling;
D-channel echo bit generation by handling of the global echo bit;
activation/deactivation procedures, triggered by primitives received over the 10M
C/I channel or by INFO's received from the line;
frame alignment according to CCID Q.503;
execution of test loops.
For a block diagram, see figure 9.
The wiring configurations in user premises, in which the ISAC-S can be used are illustrated
in figure 21.
Siemens Components, Inc.
525
I
PEB 2085
Figure 21
Wiring Configurations in User Premises
r-----.,,
I
~_1.5km1)
IIIsAc™-s Hllr---I·~
ITE
&..;----
§---HISAC T'2S II
J
r-----,I
,
r-----,
I
,
~-~----------------~~~I
1
IL... _ _ _LT-SI
_ :..J
1)
I_
r;:Rl
:i1.5km
r----5\1
-I
,I.IISAC TM_S I~
i
,
IOM®I
i J SBC II
fTRl
Poin!-to-~oint
~
. , Configurations
L___ ~~
L ____ J
1lThe maximum line attenuation tolerated by the rSAc™-S is 15 dB at 96kHz.
r--.... -;"'1
,
LT-S I
--HrsAcTM-s II
IL... ____ ...JI
:i150m
~I-~---------------J-I
~J
r--WM®j
L____
ll
:i10m 1 [ § - - - H s B c N.!..1
r- --,
Short Passive
Bus
r-- -.,
IIIsAcTM-SII-n---llrsAcTM-sll
L.!.
'T8____ J '
L.:.
I n____ JI
r----'
LT-S I
I
I:
:i SOOm
BSm
~I
----{1rsAc™-S II
IL ____ ...II
r--wi®l
~I
E'J-------~--------------~
[
. [ I :i10m
SBC
II
, ____NT'
L...
,;"J
r-- -,
r-- - ,
IIISAC™-S I l-nllrsAcTM-sl I
&..; _ _ _ _ ..J' IL..:.
In
T8____ .J'
Siemens Components, Inc.
526
Extended
Passive Bus
PEB 2085
Layer-2 Functions for the ISDN Basic Access
LAPD, layer 2 of the D-channel protocol (CCllT .441) includes functions for:
Provision of one or more data link connections on a D channel (multiple LAP). Discrimination between the data link connections is performed by means of a data link connection
identifier (DLCI = SAPI + TEl)
HDLC-framing
Application of a balanced class of procedure in point-multipoint configuration.
The simplified block diagram in figure 22 shows the functional blocks of the ISAC-S which
support the LAPD protocol.
Figure 22
D-Channel Processing of the ISAC-2
IOM®
Layer-1
~
I
HOLC
Receiver
HOLC
LAPO
Transmitter Controller
Status
Command
Registers
Layer-2
R-FIFO
2,,32 Byte
X-FIFO
2,,32 Byte
FIFO
Controller
{"t
~Z
l
jJC-System
Layer-1
Functions
:1 d
:1 Ij
I
I
I
S( O-Channel)
~
I
jJP-Interface
Upper
Layers
~
I
I
J
For the support of LAPD the ISAC-S contains an HDLC transceiver which is responsible for
flag generation/recognition, bit stuffing mechanism, CRC check and address recognition.
A powerful FIFO structure with two 64-byte pools for transmit and receive directions and an
intelligent FIFO controller permit flexible transfer of protocol data units to and from the
tJ.C system.
Siemens Components, Inc.
527
I
PES 2085
B Channel Switching (IOM-1)
The ISAC-S contains two serial interfaces, SLD and SSI, which can serve as interfaces to 8
channel sources/destinations. 80th channels 81 and 82 can be switched independently of
one another to the 10M interface and to the four-wire SIT interface (figure 23).
The following possibilities are provided:
Switching from/to SSI
Switching from/to SLD
10M looping
SLD looping
Figure 23
Principle of B-Channel Switching
III
c:
o
~
c:
I
:>:
11\
Qj
....
CJ
IOM®Interface
11\
Qj
l:
::::I
o
Layer -1
Functions
V'l
"'iii
c:
c:
ro
.c
y
CD
ISDN
Basic
Access
[j
I
q
I
SIT
III
11\
Qj
u
u
«
u
'iii
ro
CD
:z
CJ
!:2
Registers: C1R/C2R
B1CR/B2CR
SPCR
The microcontroller can select the 8-channel switching in the SPCR register. In figure 24
all possible selections of the 8-channel routes and access to 8-channel data via the microprocessor interface are illustrated. This access from the microcontroller is possible by writing
or reading the C1R/C2R register on reading the 81CR/82CR register.
Siemens Components, Inc.
528
PES 2085
Figure 24
B·Channel Routes and Access to B·Channel Data
FF
11
H
SSI Switching
---
SLD Switching
-:=~PAccess
:=B-Channel Route
SLD Loop
Siemens Components, Inc.
529
PES 2085
Access to BIIC Channels
IOM-1 Mode (IMS - 0)
The B1 and/or B2 channel is accessed by reading the B1CR/B2CR or by reading and writing
the C1 R/C2R registers. The iJ.P access can be synchronized to the serial interface by means
of a synchronous transfer programmed in the STCR register.
The read/write access possibilities are shown in table 4.
Table 4
iJ.p Access to B Channel
C_R
B_CR
C_C1
C_CO
Read
Write
Read
Application{s)
0
0
SLD
SLD
10M
B_not switched, SLD looping
0
1
SLD
10M
B_switched to/from SLD
1
0
SSI
-
10M
B_switched to/from SSI
1
1
10M
10M
-
10M looping
The synchronous transfer interrupt (SIN, ISTA register) can be programmed to occur at
either the beginning of a 125 iJ.s frame or at its center, depending on the channel(s) to be
accessed and the current configuration, see figure 25.
Siemens Components, Inc.
530
PEB 2085
Figure 25
B-Channel Access
(a) C_C1, C_CO
SLDloop
= 00
SIP
FS(
BVS
IPOO
L . . - -_ _
---.Jr----.L--_......
IOPO:==_'
SLO
--J,. -
,
----l
B'
,
B2
L..._----II
,_==
==~~TB1fB2T====Efu:r~~= I
~
FB
SIN (STO)
~PAccess
(b) C_C1, C_CO = 01
SLD - 10M connection
lOP'
SIP
IOPO
FS(
---.J
BVS
---.Jr-----.L..-_...J
lOP'
SIP
B'
B2
---------------,-~~,
~~--r----------
---------------~~--~
+-r-'-r-'-- - - - -- -- - -
IDPO
~P
Access
SIN (5TO)
Siemens Components, Inc.
531
PEB 2085
(c) C_C1, C_CO = 10
SSI - 10M connection
FS(
SOAR
SOAR
IOP1
SO AX
IOPO
---.J
----
~--------~----------T-----
----
I
=t~~~=-=---: -!~--I "
B2
I
IOP1
IOPO
SOAX
-
I
--
B1
I
----
82
----
I
--------
------------
,
+
B1
B2
~PAccess
~P Access
B1-SSI
®
B112-IOM R
82 -SSI
SIN (STOI
SIN (STlI
(d) C_C1, C_CO = 11
10M loop
IOP1
IOPO
L
---------.---~~--_r
IOP1
1000
81
lr---~----_r---------61
I 62
~P
Access
SIN (STOI
Siemens Components, Inc.
532
I
82
I
PEB 2085
IOM-2 Mode (IMS = 1)
The B1, B2 and/or IC1, IC2 channels are accessed by reading the B1CR/B2CR or by reading
and writing the C1 R/C2R registers. The ~P access can be synchronized to the 10M interface
by means of a synchronous transfer programmed in the STCR register.
The read/write access possibilities are shown in table 5.
Table 5
~p Access to B/IC Channels
C_C1
C_CO
C-R
C-R
B_CR
Read
Write
Read
Output
Application(s)
to
IOM-2
0
0
IC_
-
B_
-
B_monitoring, IC_ monitoring
0
1
IC_
IC_
B_
IC_
B_monitoring, IC_looping
from/to IOM-2
1
0
-
B_
B_
B-
B_access from/to So;
transmission of a constant value
in B_channel to So.
1
1
B_
B_
-
B_
B_looping from So; transmission
of a variable pattern in
B_channel to So.
The general sequence of operations to access the BIIC channels is:
(set configuration, register SPCR)
Program synchronous interrupt (STO)
Read register (B_CR, C_R)
(write register)
Acknowledge SIN (SCO)
C/I Channel Handling
The command/indication channel carries real-time status information between the ISAC-S
and another device connected to the 10M.
1) One CII channel (called CliO) conveys the commands and indications between a layer-1
device and a layer-2 device. This channel is available in all timing modes (IOM-1 or
IOM-2). It can be accessed by an external layer-2 device e.g. to control the layer-1
activation/deactivation procedures. CliO channels access is arbitrated via the TIC bus
access protocol:
in IOM-1 mode, this arbitration is done in the monitor channel
In IOM-2 TE timing mode, this arbitration is done in CII channel 2 (figure 17).
Siemens Components, Inc.
533
PES 2085
The CliO channel is accessed via register CIRO (in receive direction, layer 1 to layer 2)
and register CIXO (in transmit direction, layer 2 to layer 1). The CllO code is· four bits
long.
In the receive direction, the code from layer 1 is continuously monitored, with an interrupt being generated anytime a change occurs. A new code must be found in two consecutive 10M frames to be considered valid and to trigger a C/I code change interrupt
status (double last look criterion).
In the transmit direction, the code written in CIXO is continuously transmitted in CliO.
2) A second C/I channel (called C/11) can be used to convey real time status information
between the ISAC-S and various non-layer-1 peripheral devices e.g. PSB 2160 ARCOFI.
The channel consists of six bits in each direction. It is available only in the IOM-2 TE
timing mode (see figure 17).
The C/11 channel is accessed via registers GIR1 and CIX1. A change in the received
C/I1 code is indicated by an interrupt status without double last look criterion.
Monitor Channel Handling
IOM-1
The monitor channel protocol can be used to exchange one byte of information at a time
between the ISAC-S and another device (e.g. a layer-1 transceiver).
The procedure is as follows:
Monitor transmit channel 0 (MOXO) register is loaded with the value to be sent in the outgoing monitor channel. (Bytes of the form FXH are not allowed for this purpose because of
the TIC bus collision resultion procedure).
The receiving device interprets the incoming monitor value as a controllinformation byte,
FXH excluded. If no response is excepted, the procedure is complete. If the receiving device
shall react by transmitting information to the ISAC-S, it should set the E bit to 0 and send
the response in the monitor channel of the following frame. The ISAC-S
latches the value in the monitor channel of the frame immediately following a frame with
"E = 0" into MORO register.
generates a monitor status interrupt MaS (EXIR register) to indicate that the MORO
register has been loaded (see figure 26).
Figure 26
Monitor Channel Protocol (IOM-1)
SOl -SOO
--
I
Mon
X y
X=FH
I-----s
-----'>---~-----E
tion
----
------
~.
Mon - 0 -----.
-----------.
-------------
MORO Load,MOS Int.
Siemens Components, Inc.
534
-----
---
MaR 0 Load,MOS Int.
PEB 2085
IOM-2
In this case, the monitor channel protocol is a handshake protocol used for high speed
information exchange between the ISAC-S and other devices, in monitor channel 0 or 1
(see figure 17). In the non-TE mode, only one monitor channel is available ("monitor
channel 0").
The monitor channel protocol is necessary (see figure 27):
•
For programming and controlling devices attached to the 10M. Examples of such devices
are: layer-1 transceivers (using monitor channel 0), and peripheral V/D modules that do
not have a parallel microcontroller interface (monitor channell), such as the audio
ringing codec filter PSB 2160 .
•
For data exchange between two microcontroller systems attached to two different devices on one IOM-2 backplane. Use of the monitor channel avoids the necessity of a
dedicated serial communication path between the two systems. This greatly simplifies
the system design of terminal equipment (figure 27).
Figure 27
Examples of Monitor Channel Applications
Data Communication (Monitor 1)
Control (Monitor1)
V/D
Module
VlD
ISAC TM_S
Module
e.g.
Control (Monitor 0)
e. g.
IBC PEB 2095
lEe PEB 2090
®
ARCOFI
ITAC™
Layer-1
PSB 2160
PSB 2110
The monitor channel operates on an asynchronous basis. While data transfers on the bus
take place synchronized to frame sync, the flow of data is controlled by a handshake
procedure using the Monitor Channel Receive (MRO or 1) and Monitor Channel Transmit
(MXO or 1) bits. For example: data is placed onto the monitor channel and the MX bit is
activated. This data will be transmitted repeatedly once per a-kHz frame until the transfer
is acknowledged via the MR bit.
The microprocessor may either enforce a "1" (idle) in MR, MX by setting the control bit
MRC1,0 or MXC1,0 to "0" (MOnitor Control Register MOCR), or enable the control of these
bits internally by the ISAC-S according to the monitor channel protocol. Thus, before a data
exchange can begin, the control bit MRC(l ,0) or MXC(l ,0) should be set to "1" by the microprocessor.
The monitor channel protocol is illustrated in figure 28. Since the protocol is identical in
monitor channel 0 and monitor channel 1 (available in TE mode only), the index 0 or 1 has
been left out in the illustration.
Siemens Components, Inc.
535
PES 2085
The relevant status bits are:
Monitor Channel Data Received MDR (MDRO, MDR1)
Monitor Channel End of Reception MER (MERO, MER1)
C
for the reception of monitor data, and
Monitor Channel Data Acknowledged MDA (MDAO, MDA 1)
Monitor Channel Data Abort MAB (MABO, MAB1)
C
for the transmission of monitor data (Register: MOSR).
In addition, the status bit:
Monitor Channel Active MAC (MACO, MAC1)
indicates whether a transmission is in progress (Register: STAR).
Figure 28
Monitor Channel Protocol
MX
Transmitter
J.lP:
WR Data
MXC=1
MAC=1 Status
MDA Int.
WR Data
MDA Int.
o
MR
1
}--
0
1
1
---
MDR Int
-L- ~
~ 1----1---~
~- 1----
WR Data
Receiver
RD Data
MRC=1.MIE =1
MDR Int
RD Data
MDR Int.
~
MDA Int.
MXC=O
L-?
_:r
L--
MAC=O Status -
Siemens Components, Inc.
RD Data
r-----
1-----
-~
536
MDR Int.
MRC=O.MIE=O
PEB 2085
Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by
a "0" in the monitor channel active MAC status bit.
After having written the monitor data transmit (MaX) register, the microprocessor sets the
monitor transmit control bit MXC to 1. This enables the MX bit to go active (0), indicating
the presence of valid monitor data (contents of MaX) in the corresponding frame. As a result,
the receiving device stores the monitor byte in its monitor receive MaR register and generates
a MDR interrupt status.
Alerted by the MDR interrupt, the microprocessor reads the monitor receive (MaR) register.
When it is ready to accept data (e.g. based on the value in MaR, which in a point-tomultipoint application might be the address of the destination device), it sets the MR control
bit MRC to "1" to enable the receiver to store succeeding monitor channel bytes and
acknowledge them according to the monitor channel protocol. In addition, it enables other
Monitor channel interrupts by setting monitor interrupt enable to "1".
As a result, the first monitor byte is acknowledged by the receiving device setting the MR bit
to "0". This causes a monitor data acknowledge MDA interrupt status at the transmitter.
A new monitor data byte can now be written by the microprocessor in MaX. The MX bit is
still in the active (0) state. The transmitter indicates a new byte in the monitor channel by
returning the MX bit active after sending it once in the inactive state. As a result, the receiver
stores the monitor byte in MaR and generates a new MDR interrupt status. When the microprocessor has read the MaR register, the receiver acknowledges the data by returning
the MR bit active after sending it once in the inactive state. This in turn causes the
transmitter to generate a MDA interrupt status.
This "MDA interrupt - write data - MDR interrupt - read data - MDA interrupt" handshake
is repeated as long as the transmitter has data to send. Note that the monitor channel
protocol imposes no maximum reaction times to the microprocessor.
When the last byte has been acknowledged by the receiver (MDA interrupt status), the microprocessor sets the monitor transmit control bit MXC to O. This enforces an inactive ("1")
state in the MX bit. Two frames of MX inactive signifies the end of a message. Thus, a
monitor channel end of reception MER interrupt status is generated by the receiver when
the MX is received in the inactive state in two consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0, which in turn enforces an inactive state in
the MR bit. This marks the end of the transmission, making the monitor channel active MAC
bit return to "0".
During a transmission process, it is possible for the receiver to ask a transmission to be
aborted by sending a inactive MR bit value in two consecutive frames. This is effected by
the microprocessor writing the MR control bit MRC to O. An aborted transmission is indicated
by a monitor channel data abort MAB interrupt status at the transmitter.
Siemens Components, Inc.
537
PEB 2085
Terminal Specific Functions
In addition to the ISAC-S standard functions supporting the ISDN basic access, the ISAC-S
contains optional functions, useful in various terminal configurations.
The terminal specific functions are enabled by setting bit TSF (STCR register) to "1 ". This
has two effects:
• The SIP/EAW line is defined as external awake input (and not as SLD line);
• Second, the Interrupts SAW and WOV (EXIR register) are enabled:
- SAW (subscriber awake) generated by a falling edge on the EAW line
- WOV (watchdog timer overflow) generated by the watchdog timer. This occurs when
the processor fails to write two consecutive bit patterns in ADF1 :
ADF1
I
WTC1
I
WTC2'
I
Watchdog Timer Control 1, O.
The WTC1 and WTC2 bits have to be successively written in the following manner within
128 ms:
1.
2.
WTC1
WTC2
1
0
0
1
As a result the watchdog timer is reset and restarted. Otherwise a WOV is generated.
Deactivating the terminal specific functions is only possible with a hardware reset.
Having enabled the terminal specific functions via TSF = 1, the user can make the ISAC-S
generate a reset signal by programming the Reset Source Select RSS bit (CIXO register),
as follows:
~ A reset signal is generated as a result of
- a falling edge on the EAW line (subscriber awake)
- a C/I code change (exchange awake).
A falling edge on the EAW line also forces the IDP1 line of the 10M interface to zero.
The consequence of this is that the 10M interface and the ISAC-S leaves the powerdown state.
A corresponding interrupt status (CISa or SAW) is also generated.
1 ~ A reset signal is generated as a result of the expiration of the watchdog timer (indicated by the WOV interrupt status).
Note that the watchdog timer is not running when the ISAC-S is in the power-down
state (10M not clocked).
o
Note: Bit RSS has a signifinace only if terminal specific functions are activated (TSF = 1).
Siemens Components, Inc.
538
PEB 2085
The RSS bit should be set to "1" by the user when the ISAC-S is in power-up to prevent
an edge on the EAW line or a change in the C/I code from generating a reset pulse.
Switching RSS from 0 to 1 or from 1 to 0 resets the watchdog timer.
The reset pulse generated by the ISAC-S (output via RST pin) has a pulse width of:
125 ,",S when generated by the watchdog timer
16 ms when generated by EAW line or C/I code change.
Test Functions
The ISAC-S provides several test and diagnostic functions which can be grouped as follows:
• Digital loop via TLP (test loop, SPCR register) command bit: IDP1 is internally connected
with IDPO, output from layer 1 (SIT) on IDPO is ignored; this is used for testing ISAC-S
functionality excluding layer 1;
• Test of layer-2 functions while disabling all layer-1 functions and pins associated with
them (including clocking, in TE mode), via bitTEM (test mode, SQXR register); the ISAC-S
is the fully compatible to the ICC (PEB 2070) seen at the 10M interface.
• Loop at the analog end of the S interface; either info 0 (non-transparent loop: TE/LT-T
modes) or info 4 transparent loop: NT/LT-S modes) is sent over the SIT interface during
the loop, which is closed via a CII command written in CIXO register;
• Special loops programmed via C2C1-0 and C1C1-0 bits (register SPCR);
• Transmission of special test signals on the SIT interface according to the modified AMI
code, initiated via a C/I command written in CIXO register:
Single pulses of alternating polarity, one SIT interface bit period wide, with a 2-kHz
repetition frequency;
Continuous pulses of alternating polarity, one SIT interface bit period wide, with a
96-kHz repetition frequency.
Siemens Componerits, Inc.
539
PEB 2085
Absolute Maximum Ratings
Parameter
Symbol
Voltage on any pin with respect to ground
Vs
-0.4 to Voo +0.4
Ambient temperature under bias
TA
Tstg
o to 70
°C
-65 to 125
°C
Storage temperature
DC Characteristics
TA = 0 to 70°C; Voo = 5 V
± 5%, VSSA = 0 V,
Vsso
Limit Values
Unit
V
=0 V
Limit Values
Symbol
min.
max.
Unit
L-input voltage
VlL
-0.4
0.8
V
All pins except
SX1,2, SR1,2
H-input voltage
(all except XI and RST)
VlH
2.0
Voo
+0.4
V
All pins except
SX1,2 SR1,2
L-output voltage
L-output voltage (IDPO)
VOL
VOL1
0.45
0.45
V
V
IOL = 2 mA
I oL = 7 mA
All pins except
SX1,2 SR1,2
H-output voltage
H-output voltage
VOH
VOH
V
V
IOH =-400 iJ.A
IOH =-100 iJ.A
All pins except
SX1,2 SR1,2
DCLK = 512 kHz
DCLK = 1536 kHz
DCLK = 4096 kHz
Voo= 5 V
Inputs at
VsslVoo
No output
loads
Parameter
Power
supply
current
2.4
Voo
-0.5
Test Conditions
Remarks
operation
Icc
15
17
27
mA
mA
mA
power down
Icc
1.5
mA
10
iJ.A
o V.....>..........,.--"--'>.....>....~........,..a....>.....L."---'-_ _ _ _---'
o
300
200
1000
2000
3000
3600 4000 Hz 5000
3400
Group Delay Distortion in Transmit & Receive Direction (ref. 1500 Hz)
ms
800~--~~~~~~~~~~+_----~
750~--~~~~~~~~~~-+------~
t::::::::$~*~~~~~+-t---1
400
420 F
380
O~--~--~-------'-----~~---------'
o
500 600 1000
2000
Siemens Components, Inc.
2600 3000
2800
Hz
567
4000
PSB 2160
Gain Tracking in Transmit & Receive Direction (Method 1; Noise)
dB
-0.7 I--+-~'"
-1.0
I--+--.p..~rr~~~",,",~~~--+----j
- 2.0 ~_-L-.~...J>",.;"--"-.>.L..>..-"'->->-':"--"-.>....J>..--"--'.....:>..I._---'-_---'
-70 -60 -56-50
-40 -35
-20
-10
0 dBmO
Input Level
Gain Tracking in Transmit & Receive Direction (Method 2; Sinus)
2.0 ,-----.---,..,....,""""''''''''''''''''~J'''''C''''''''''''''''''''l'<'T'___,
dB
1.6 f---+----.,
1.4 f---+---{
-1.4 i---f-----t
-1.6 f---+--__+_2DL---L-.~~~UL~~~~~~~~~~
-70
-60 -56-SO
odBmO 0
- 40 -35
-20
Input Level
Siemens Components, Inc.
568
PSB 2160
Total Harmonic Distortion in Receive and Transmit *) Direction (Method 1; Noise)
40.0,-----,---------,-------,--------,
dB
35.4
f-+----+----7i:~~<:-..-~~~
33. 7 f----f-----+--,r:..
o~~~~~~~~~~~~~~~~
-60 -55
-40 -34
-27
-20
dBmO -6-3 0
Input Level
Method 1
*) Remark: Between brackets, values for transmit direction
Total Harmonic Distortion in Receive and Transmit Direction (Method 2; Sinus)
40.--.-,-----,--.------.-------,
dB
35r-+--+-r-~-~~~~~~~~~
-30
-45 -40
-20
d8mO
Input Level
Method 2
Siemens Components, Inc.
569
o
PSB 2160
Out-of-Band Signals at Analog Inputs
When applying an out-of-band sine-wave signal with frequency f and level A to the analog
inputs, the level of any frequency component below 4 kHz at the digital output is attenuated
according to the following table.
The reference level used for this measurement is a 800 Hz, OdBmO signal applied to the
FHM analog input in by-pass mode. The digital gain GX in configuration register CR1 has
to be set to a flat OdB.
Out-of-Band
Input Frequency f
o HZ<=f<=
Out-of-Band
Input Level A
Attenuation at
Digital Output
60 Hz
-45 dBmO<=A <=
0
dBmO
25dB
60 HZ<=f<= 100 Hz
-45 dBmO<=A<=
0
dBmO
10 dB
3400 HZ<=f<= 4000 Hz
-45 dBmO<=A<=
0
dBmO
OdB
4000 HZ<=f<= 4600 Hz
-45 dBmO<=A<=
0
dBmO
14 dB
-45 dBmO <=A <= -15.8 dBmO
35 dB
-45 dBmO < =A < = -23.2 dBmO
35 dB
dBmO
35 dB
4600 HZ<=f<=
12 kHz<=f<=
12 kHz
20 kHz
20 kHz<=f
Siemens Components, Inc.
-45 dBmO < =A < = -25
570
PSB 2160
Functional Description
The ARCOFI bridges the gap between the audio world of microphones, earphones, loudspeakers and the PCM digital world by providing a full PCM CODEC (coder + decoder)
with all the necessary transmit and receive filters. A block diagram of the ARCOFI is shown
in figure 1.
The ARCOFI can be subdivided in three main blocks;
•
The ARCOFI Analog Front End (AFE)
•
The ARCOFI Signal Processor (ASP)
•
The ARCOFI Digital Interface (ADI)
Figure 1
Block Diagram
ARCOFI ® Block Diagram
ARCOFI ® Signal Protessor
ASP
Analog Front End
AFE
ARCOFI®
Digital Interface
ADI
SPI
IIMUX
O/HUX
GNO
Siemens Components, Inc.
Digital
Signal
AID
DIA
Processor
Coefficient
R4H
GNO
571
SP2
f----Il0 SA
Peripheral
Control
Interface
56
SC
SLO-IOHInterfac.
r---f 7
SO
t-------i,~
00
J---..........- t 12 SIPIDU
f--o>----f 6 CLK/DCLK
f--o>----f 5 FCS
Re ..t
PSB 2160
Analog Front End
The Analog Front End section of the ARCOFI interfaces the analog transducers with the
subsequent signal processor. In the transmit direction the AFE function is to amplify the
transducer input signals (microphones) and convert them into digital signals. In the AFE
receive section, the incoming digital signals are converted to analog signals output to an
earpiece and a loudspeaker. The attenuation plan and electrical characteristics of the AFE
are adapted to meet commonly used voice transducers.
Analog Inputs
A high sensitive differential input MIP and MIN connects a handset microphone to a gain
programmable amplifier AHM. When selected, the differential X inputs can be activated
(amplifier AX) while deselecting the MIP/MIN inputs;
Coming from AHM or AX the signa:l is forwarded via a fixed amplification stage AR to the
input of the analog multiplexer driving the oversampling AID converter: A third analog input
source is provided through pin FHM. This "hands-free" microphone input connects the
multiplexer via amplifier AFHM. The programmable amplifier AHM provides a first gain
adjustment allowing a perfect adaptation to various types of microphone transducers.
This gain adjustment is then tuned in the digital domain via the programmable gain adjustment filter GX (see ARCOFI signal processing section).
Analog Outputs
Fully differential outputs HOP and HON connect the amplifier AHO to the hand-set earpiece.
Differential outputs LSN & LSP are provided for use with a 50 0 loudspeaker. Up to 100 mW
of power can be delivered to the loudspeaker via amplifier ALS. The power amplifier ALS
is short-circuit protected. All outputs are sourced by a digital-to-analogconverter via an
output analog multiplexer. The selection of the output source is performed through the
configuration register CR3 via the SLD interface.
ARCOFI Signal Processor (ASP)
The ARCOFI Signal Processor (ASP) has been conceived to perform all CCITI recommended
filtering in both the transmit and receive path and is therefore fully compatible to the
G.714 CCITI specification. The code processed by the ASP is provided in the transmit
direction by an oversampling AID converter situated in the analog front end (AFE). Once
processed the speech signal is converted into an 8 bit A-law or ~-Iaw PCM format or
remains a 16-bit linear word according to the bit setting in the configuration register 3.
In the receive direction the incoming PCM-signal is expanded in a linear format and
subsequently processed until passed to the D/A converter.
The entire ARCOFI signal flow plan is shown in figure 2.
Siemens Components, Inc.
572
PSB 2160
Figure 2
Signal Flow
Transmit P a t h >
<
o
1
~1 PM
;;
TG
Receive Path
Tone
Beat
Generator
Generator
TG
Ft A1
---".L-
Userprogrammable
SA
S8
T1
F2: A2
T2
F3, A3
T3
Transmit Path Signal Processing
In the transmit direction a series of decimation filters reduces the sampling rate down to
the 8-kHz PCM rate. These filters attenuate out-of-band noise by limiting the received signal
to the voiceband.
The decimation stages end with a low-pass filter which band limits the voice signal according
to the CCITI recommendation G.714. A high-pass filter is also provided to remove power
line frequencies. The ARCOFI meets or exceeds all CCITI, and North American recommendation on attenuation distortion and group delay distortion.
The GX gain adjustment stage is digitally programmable allowing the gain to be programmed
from -45 to +12 dB within a ± 0.25 dB tolerance range. However the CCITI templates are
not guaranteed in the whole area.
The voice Signal after being linearly processed can be output as an 8-bit PCM word
according to the CCITI G.711 A-Law or the North American Il-Law format. If desired the
compression stage can be by-passed. a 16-bit linear word is then outputed to the ARCOFI
digital interface.
The transmit path contains a frequency correction filter FX allowing an optimum adaptation
to different type of microphones (dynamic, piezoelectric or electret).
Siemens Components, Inc.
573
PSB2160
Receive Path Signal Processing
In the receive path the incoming PCM signal is expanded into a linear code according
to the selected A or ~-Law. If the linear mode is chosen, the PCM expander circuit is
by-passed and a 16-bit linear word has to be provided to the processor.
A programmable sidetone gain stage Z adds a sidetone signal to the incoming voice signal.
The sidetone gain can be programmed from -50 to -2.5 dB within a ± 1 dB tolerance
range (0 dB is also possible).
The FR frequency correction filter is similar to the FX filter allowing an optimum adaptation
to different type of loudspeakers and earpieces.
A low-pass EWDF filter limits the signal bandwidth in the receive direction according to
CCID recommendations. The GR gain adjustment stage is digitally programmable from
-45 dB to +12 dB within a 0.25 dB tolerance range. However the CCID templates are not
guaranteed in the whole area.
A series of low-pass interpolation filters increase the sampling frequency up to 128 kHz.
The last interpolator feeds the DIA converter.
Tone Ring and Tone Generator
The ASP receive path contains two signal generators; a tone ring and a beat tone generator
(TG & BT). Those generators can be used for tone alerting; call progress tones or other
audible feedback tones. All generated tones can be provided at either the handset earpiece,
the loudspeaker output or the piezo ringer output (SA & SB).
Distinctive alerting signals allowing for example the use of different multitone ringing patterns,
are all programmable using the beat tone generator in conjucntion with the tone ringer.
In the case of a two or three tone ringing signal, the tone ring generator controls the output
frequency pitch whilst the beat tone generator controls the repetition rate.
ARCOFI Digital Interface (ADI)
The ADI features are:
• A selectable SLD or IOM-2 serial bus interface through which the ARCOFI transfers
voice channels and communicates with the system microcontroller.
• A programmable multipurpose interface PCI (Peripheral Control Interface) which provides 4 programmable liD pins to control peripheral devices.
Siemens Components, Inc.
574
PSB2160
SlD Bus
The SlD serial interface consists of a bidirectional data line SIP, a synchronization clock
input ClK and a data direction input FSC. Data bits are loaded or read out of the serial
interface pin SIP under control of a direction signal FSC. Bits are clocked in or clocked out
on the rising edge of the slave clock pin ClK (512 kHz). FSC and ClK inputs must be
phase locked.
An SlD frame lasts 125 Ils and consists of 32 bits transferred to the ARCOFI (FSC high)
followed by 32 bits transferred from the ARCOFI to the SLD bus (FSC low).
The SlD interface thus provides a full duplex 256 kbiVs communication capacity. This
capacity is subdivided in two 64 kbiVs voice/data channels reserved for the ISDN B1
and B2 channels. The remaining bandwidth is used by a feature control channel (64 kbiVs)
and a signaling channel (64 kbiVs). Bytes in all channels are serialized MSB first.
A command received over the SlD-bus can cause a response over the SLD-bus within
the same frame. This leaves the ARCOFI 31.25 Ils to interpret the command and generate
the appropriate answer in the following SlD half-frame.
All ARCOFI internal registers are accessible via the SlD-bus in the time slot allocated
to the command channel. The first byte transferred in the command channel specifies the
type of operation and the number of bytes allocated to the transfer set-up.
When in power down (PU=Q ;CMDR), the command channel remains active in both transmit
and receive direction providing that the address bit (AD ;CMDR) matches the address
strapped on SP1, SP2.
In power down however both data channels are disabled; SIP being tristated during data
channel transmit time slots.
Transmit direction (TX)
ARCOFI---SLD
Receive direction (RX)
SlD --- ARCOFI
ClK
FSC
J
Btl:
I
Btl:
I
Fe
SIG
B:I+
I
FC
Transmit Di rection
Receive Direction
B:t:I: 1,2: Data Channel
FC
: Feature Control Channel
SIG
: Signali ng Channel
Siemens Components, Inc.
B:I+
575
SIG
PSB 2160
IOM-2 Interface
The IOM-2 interface consists of two data lines and two clock lines. DU: Data Upstream
carries data from the ARCOFI to the layer-1 device and DD: Data Down stream carries
data from the layer-1 device to the ARCOFI. A FSC Frame Synchronization Clock is supplied
to the ARCOFI as well as a DCLK 1.536-MHz data clock for bit clocking.
In terminal mode the IOM-2 frame consists of three 10M channels numbered respectively
0,1 and 2. The ARCOFI can receive and transmit voice data in the 10M 81 & 82 channels as
well as in the IC1 and IC2 intercommunication channels located in 10M channel 0 and 1
respectively.
The IC1 and IC2 intercommunication channels can be used in the terminal for local bearer
data communication. This makes post-processing of voice/data information possible.
FSC
Jr-------...........-,
L
r
DCl• • • . • . • . • • . . • . .
DU
DO
IOM-2 Monitor Channel
All programming data required by the ARCOFI including coefficients are transmitted
exclusively in the monitor 1 time slot in the 10M channel 1. The MON1 monitor channel
allows a point to multi-point access where the layer-1 component acts as master to programmable devices like the ARCOFI. Each programmable device is accessed by sending
a specific address byte at the start of each command stream followed by an identification
byte. The programmable device compares the received address byte with its own internally
wired 10M address before executing a command.
All programmed coefficients can be read back when issuing an appropriate CMDR read.
The ARCOFI responds by sending two IOM-2 specific bytes unambiguously identifying the
chip type and version followed by the issued SOP or COP read sequence.
Siemens Components, Inc.
576
PSB 2160
Monitor Transfer Protocol
The transfer of a low of commands in the MON 1 channel is regulated by a handshake
protocol mechanism implemented by two bits MX and MR in the fourth slot of the 10M
channel 1. The maximum effective transfer rate in the MON1 channel is 32 kbiVs. Thanks
to the implemented handshake mechanism a command sequence can be delayed at the
convenience of the transmitting 10M bus master device and resumed subsequently. An
abort mechanism allows the interruption of a command sequence. In that case the command
may be partially executed by the ARCOFI (i.e. coefficients partially modified in the ARCOFI
CRAM). If use of the abort mechanism is made, a new command has to be issued to
program the ARCOFI.
CII Channel
The first four bits of the 10M Channel 1 C/I channel are transparently routed to the four
ARCOFI PCI pins SA-SD. SA & sa from the presently addressed ARCOFI are shown in
the 3rd and 4th C/I bit position. The SP1 and SP2 strapping as well as the AD-bit in the
CMDR register determine which ARCOFI is adressed.
Pins SA-SD can be configured individually as input or output and will appear respectively
in the DD or DU CH1-C/1 channel.
Tihe mapping of the peripheral control interface (PCI) pins SA,Sa,SC,SD into the six CII
channel bits depends on the hardwired SP1 address as follows:
SP1
=1
DDand DU
sa
SA
SP1 =0
(AM = 0; two chip mode)
DDand DU
I SD I SC I - I - I
SP1 =0
(AM = 1; one chip mode)
DD and DU
SD
SC
sa
SD
SC
SA
The ARCOFI with the address pin SP1 strapped to 0 transmits/receives the SD and SC
values on DU/DD
In case a reset has been asserted, the SA to SD pins are programmed as input, however
the SA to SD values are not switched to the CII channel unless a CR1 to CR4 SOP _0 write
command is issued.
Siemens Components, Inc.
577
PSB 2160
Programmable Registers
The SLD or the IOM-2 bus mode is used to control and program the operations performed
by the ARCOFI. The following lists the ARCOFI internal registers.
ARCOFI Digital Interface (ADI)
•
CMDR:
8-bit command register
•
CR1-4:
four 8-bits configuration registers
ARCOFI Signal Processor (ASP)
•
Two transmit gain registers (GX)
•
Two receive gain registers (GR)
•
10 FX filter coefficient registers
•
10 FR filter coefficient registers
•
One Z sidetone gain register
•
Two DTMF frequency tone registers
•
6 Tone ring/tone generator frequency register
•
3 Tone ring/tone generator amplitude register
•
6 Beat tone generator timing register
To familiarize the user with ARCOFI, a program, named ARCOS, is available. (see description
of ARCOS page 602).
This software tool allows the user to program the different ARCOFI registers and to evaluate
the chip in a real environment.
Siemens Components, Inc.
578
PSB 2160
Filter Programming Ranges
Limit Values
Parameter
Symbol
GX-filter 1)
GR-filter
Z-filter
Tone generator gain
Tone generator frequency
Tone generator time
GTone
fTone
tTone
DTMF generator
min.
max.
Unit
Tolerance
0
-6
6
0
dB
dB
0.25 dB
0.25 dB
-00
0
dB
±1 dB
-00
dB
0
1
0
4000
16384
380
1630
Hz
Hz
ms
±1%
1) Remark: The programming of GX-filter depends on the programming of the half-channel (AFE).
A DTMF generator is also built into the ARCOFI transmit path.
A preemphasis of 2 dB is guaranteed between the high and the low DTMF frequency
groups. The total power level of all unwanted frequency components is at least 20 dB below
the level of the low frequency group component of the signal.
The level of any unwanted freque'ncy component does not exceed the following limits:
In the frequency band 0-300 Hz:
> -33 dB
- In the frequency band 300-3400 Hz:
> 20 dB
- In the frequency band 3400-4000 Hz: > -33 dB
All generated DTMF frequencies are guaranteed within a ± 1% deviation.
DTMF Frequency Programming
CCITT
Q.23
ARCOFI
Nominal
Relative Deviation
from CCITT*
Hex Coefficient
H nibble/L nibble
low Group
697
770
852
941
697.754
773.438
852.783
939.453
+1081
+4464
- 513
-1646
ppm
ppm
ppm
ppm
F8
A8
F9
BA
High Group
1209
1336
1477
1633
1203.125
1339.844
1476.563
1632.813
-4883
+2877
- 295
- 114
ppm
ppm
ppm
ppm
21
40
10
00
': The deviations due to the inaccuracy of the incoming clock ClK, when added to the nominal
deviations tabulated above give the total absolute deviation from the CCITT recommended frequencies.
Siemens Components, Inc.
579
PSB2160
Command Register (CMDR)
Logical 1
Logical 2
BIT 7
AD= 1; if bit AD matches the
address convention strapped
on SP1 ; pin SIP is active as output
during SLD transmit time slots.
AD=O; if address bit is not consistent
with the logical level strapped
on SP1 ; SIP is tristated
during SLD transmit time slots.
BIT 6
RIW= 1; reading from CR 1, CR2,
CR3, CR4 or CRAM.
RIW=O; writing to CR1, CR2,
CR3, CR4 or CRAM.
BIT 5
pu= 1; The ARCOFI is in a normal
operating mode (powered up).
PU=O; The ARCOFI is placed in
stand by (powered down).
All register contents are saved.
BIT
RCS=1; receive and transmit
in CH-B2.
RCS=O; receive and transmit
in CH-B1.
\
Note: RCS versus AM bit
a) In case of one chip mode (AM= 1) RSC operates as described above.
b) In case of two chip mode (AM=O) and pin SP1 is strapped to 0 same as above.
If SP1 is strapped to 1, RCS operates in reverse order:
RCS=1 RX and TX in channel B1
RCS=O RX and TX in channel 82
This provides a contention-free switching of the 81 & B2 channels while in twochip mode.
Siemens Components, Inc.
580
PSB 2160
A full sequence consists of a command byte followed by
BIT3210
< .. > n byte coefficients.
CMD
Name
Status
Mode
0 0 0
000 1
SOP_O
COP_1
R/W
RIW
5
5
o0
o0
0
COP-.2
COP_3
R/W
R/W
3
5
o1 o0
o1 o1
o1 0
o1 1 1
000
100 1
SOP_4
SOP_5
SOP_6
SOP_7
COP_S
COP_9
R/W
RIW
RIW
RIW
R/W
R/W
2
2
2
2
3
5
o1
0
COPJ,.
R/W
9
o1 1
o0
COP_B
COP_C
RIW
RIW
3
9
o1
COPJ)
R/W
5
>gr1>
1 0
COP~
R/W
5
NOP
R
o
1 1 1 1
CMD
CMD
Sequence Sequence
Length
Description
; Comments
W
W:
R:
< .. >
BITS
; Reset F flag
; Beat tone time span
; T1 & tone generation
; frequency F1
; GX gain
; Beat tone time span
; T2 & tone generation
; frequency F2
; Configuration reg. 1
; Configuration reg. 2
; Configuration reg. 3
; Configuration reg. 4
; DTMF frequencies
; GZ gain & tone
; generator amplitudes
; A1, A2, A3
; FX frequency correc; tion coefficient set 1
; GR gain
; FR frequency correc; tion coefficient set 1
; FX & FR coefficient
; set 2
; Beat tone time span
; T3 & tone generation
; frequency F3
; No operation; CMDR
; bits 7,6,5,4
; are masked
; No operation, CMDR
; bits 7,6,5,4 can be
; written
; write
; read
; mandatory byte coefficient sequence
7
6
5
4
3
2
AD
RIW
PU
RCS
CMB3
CMB2
Initial value on RESET: OFH (NOP)
Siemens Components, Inc.
581
0
CMB1
CMBO
I
PSB 2160
Configuration Register 2 (CR2)
Logical 1
Logical 0
BIT 7
SO=1; SO pin
programmed as input.
SO=O; SO pin
programmed as output.
BIT6
SC=1; SC pin
programmed as input.
SC=O; SC pin
programmed as output.
BIT 5
SB=1; SB pin
programmed as input.
SB=O; SB pin
programmed as output.
BIT 4
SA=1; SA pin
pr~rammed as input.
SA=O; SA pin
programmed as output.
BIT 3
ELS= 1; PCI pins SA-SO,
which are not programmed
as TX-SIG transmit inputs,
tristate SIP in TX direction.
ELS=O; pins SA-SO,
which are not TX-SIG inputs,
are sending zeros.
BIT 2
AM= 1; only one device is
connected to the SLO bus,
send NaP's during TX-FC.
AM=O; two devices are
to the SLD bus,
tristate SIP during TX-FC.
BIT 1
TR= 1 ; Three party conferencing
enabled CH-B1 is added to CH-B2
in the RX direction.
TR=O; Three party conferencing
disabled.
BIT 0
SLOMode
EFC= 1 ; Enable feature control.
TX-FC channel is enabled.
EFC=O; TX-FC channel disabled
(high Z).
IOM-2 Mode
SEL= 1; Bearer channels
transmit & receive in 10M channel O.
SEL=O; B channels
transmit & receive in 10M channel 1.
BITS
7
6
5
4
3
2
SO
SC
SB
SA
ELS
AM
Initial value on RESET: F9 H
Siemens Components, Inc.
582
o
PSB 2160
Configuration Register 1 (CR1)
Logical 1
Logical 0
7
GR= 1; GR gain
loaded from CRAM
GR=O; GR gain
set to 0 dB
BIT 6
GZ=1; Zgain
loaded from CRAM
GZ=O;Zgain
setto-18 dB
BIT 5
FX= 1; X filter
loaded from CRAM
FX=O; X filter
set to 0 dB flat
BIT 4
FR= 1; R filter
loaded from CRAM
FR=O; R filter
set to 0 dB flat
BIT 3
GX= 1; GX gain
loaded from CRAM
GX=O; GX gain
set to 0 dB
BIT
BIT 2
1
0
Test Mode
Configuration Description
0
0
0
0
0
0
1
NOT
ALS
ALM
0
1
No test mode
Analog loop back via converter registers.
The MICf)ON input is looped back to HaN & HOP.
(AHa amplifier) the FHM input is looped back to
analog MUX. FHM input is looped back to LSN & LSP.
(ALS amplifier)
By-pass: the analog front end is by-passed.
FHM serves as a direct single ended input to the
AID-converter while HOP outputs the single ended
signal generated by the D/A converter.
Data RAM initialisation, reset all data RAM locations
to hex 00.
Digital loop back via converter registers.
The DIA output is looped back to the AID input via
the analog 1/0 MUX.
Digital loop back via PCM registers.
0
0
BYP
0
IDR
0
DLS
DLM
0
DLP
BITS
7
6
5
4
3
2
GR
GZ
FX
FR
GX
TMB2
Initial value on RESET: OOH
Siemens Components, Inc.
583
o
TMB1
TMBO
I
PSB 2160
Configuration Register 3 (CR3)
BIT 7 6 5
Analog gain adjustment in transmit direction for the MIC input.
Gain factor tolerance range ± 0.5 dB
52.0 dB default on RESET
011
34.0 dB
000
001
46.0 dB
28.0 dB
o 0
40.0 dB
22.0 dB
o
0
o 1
X input enabled with a
17.0 dB
1
o
15.1 dB amplification factor
MIC input disabled
BIT 4
3
Code
2
Operating
mode
Configuration description
Analog Front End Control (AFEC)
State
MICIIN
FHM
HOUT
LOUT
Comments
0
0
0
POR
OFF
OFF
OFF
OFF
Power on reset
0
0
1
RDY
ON
OFF
ON
OFF
Ready
0
1
0
LH1
OFF
OFF
OFF
ON
Loud hearing 1
0
1
1
LH2
ON
OFF
OFF
ON
Loud hearing 2
1 0
0
LH3
ON
OFF
ON
ON
Loud hearing 3
1 0
1
HFS
OFF
ON
OFF
ON
Hands-free
1
1
0
MUT
OFF
OFF
ON
OFF
Mute
1
1
1
RES
X
X
X
X
Reserved
BIT
o
0
Operating
Mode
Linear Input/Output (LlO)
0
LlOO
Normal 1/0 Mode
IB#1IB#21 FC 1 SIG
I B#1 I B#2 I
LlO 1; ELS=O
Mixed 1/0 Mode
1B#1 18#2 1 FC 1 SIG
I B#1 I B#21 MSB 1 LSB
Ll02
Linear 1/0 Mode
1MSB I LSB 1 FC 1 SIG 1MSB 1 LSB 1 FC I SIG 1
o
o
FC
I SIG I
LlO 3 Reserved
BITS
7
6
4
5
AGX
AFEC
Initial value on RESET: OOH
·Siemens Components, Inc.
3
584
2
0
LlO
1
PSB 2160
Configuration Register 4 (CR4)
Logical 1
Logical 0
BIT 7
DHF= 1; digital high-pass in TX
direction enabled
DHF=O; digital high-pass in TX
disabled
BIT6
DTMF= 1; DTMF
generator enabled
DTMF=O; DTMF
generator enabled
BIT 5
TG= 1 ; tone ring enabled
TG=O; tone ring disabled
BIT 4
BT= 1; beat tone
generator enabled
BT=O; beat tone
generator disabled
BIT3
TM= 1; tone mode bit set,
incoming voice is activated
TM=O; incoming voice
is blocked
BIT 2
BM= 1 ; beat mode. 3 tone ring
activated when BT generator
enabled.
BM=O; 2 tone ring
activated when BT generator
enabled.
BIT 1
PM= 1; piezo mode bit set,
tone generator is outputed to the
piezo ring pins SA & SB
PM=O; the tone generator
is directed to the loudspeaker
(D/A out)
BIT 0
A/1J.=1;
IJ. law enabled
A/IJ.=O;
A law enabled
BITS
7
6
5
4
3
2
DHF
DTMF
TG
BT
TM
BM
X: don't care
Initial value of RESET: OOH
Siemens Components, Inc.
585
I
o
PM
PSB 2160
ARCOFI Software Tool: ARCOS
The ARCOS program kit provides the means to exercise the PSB 2160 ARCOFI in a real
environment. The ARCOFI capabilities are made easily understandable thanks to a "DIALOG MODE" allowing direct programming of the component. Various operating conditions
can be programmed into the ARCOFI registers so as to evaluate ist performances. The
support software has also been designed to generate all the necessary coefficients to program the Siemens PSB 2160 ARCOFI signal processor.
ARCOS supports:
• Generation of coefficients for the three ARCOFI tone generator registers
• Generation of coefficients for the ARCOFI DTMF tone generator registers
• Generation of coefficients for the two ARCOFI programmable gain registers GX and GR.
• Generation of coefficients for the Z side tone gain register
• Generation of coefficients for the FX and FR correction filter registers. Adaptive software
calculates coefficients to fit a target amplitude frequency response. All these features
are provided under the "Search Coefficient" mode.
• A user friendly dialogue mode allowing full programming of the ARCOFI configuration
registers and coefficient RAM.
• Statistical information menus allowing users to explore the programming possibilities
of the ARCOFI
• ARCOFI transmission measurements using the Wandel & Goltermann PCM-4.
Figure 3
ARCOS Main Menu
ARCOFl® COEFFICIENT SOFTWARE
ARCOS
Copyright 1988
Munich,
SiemensAG
Version 3.0
West-Germany
Search Coefficient. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. (S)
Statistical Information .................................................... (I)
Dialog-Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. (D)
Ouit .................................................................. (0)
ARCOS>
Siemens Components, Inc.
586
PSB 2160
Search Coefficient Mode
With this mode the user can ask whether a specific value of a filter is available or not.
The answer is the closest values available, their corresponding coefficient as well as the
deviation from the desired value.
Figure 4
Search Coefficient Mode
Syntax
D[TMF]
F[req]S
F[req]
T[ime]
Unit
I Frequency I
I Frequency I
I Frequency I
!Timel
GZ or G[ain]
GX or GR
GZ> or G>
GX> or GR>
IGainl
IGainl
IValuel
IValuei
Search Coefficient
Example
[Hz]
[Hz]
[Hz]
[ms]
T
6601200
500600.5
500600.5
100020333
[dB]
[dB]
[--]
[--]
GZ
GX
GZ>
GX>
8
122-4
0.34
2.340.54
0
FS
FT
Range
380 ..
0 ..
0 ..
1 ..
-
00
-
00 ••
••
0 ..
0 ..
FX or FR A gain Fb freq Fc freq [A gain Fb freq Fc freq]
FX or FR Filename [Fast I Middle I Best]
FX or FR ? [Filename I =]
S[ound]
O[utput]
Q[uit]
Sounds last specified
Square-Frequencies and Times
Output to PRN, Harddisk, Screen
Quit
This Picture
ARCOS>
Siemens Components, Inc.
587
1650 Hz
8000 Hz
4000 Hz
16400 ms
OdB
14dB
1
PSB 2160
Statistical Information Mode
The "Statistical Information" mode permits the generation of tables showing the coefficients
of different filters or generators and makes analysis of accuracy possible.
Figure 5
Statistical Information Menu
Statistical Information
Frequency DTMF-Tone Generator ....................................... (D)
Frequency Tone Generator (Trapezoid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. (F)
Frequency Tone Generator (Square) ..................................... (S)
Time Tone Generator .................................................. (T)
Gain Tone Generator and GZ-Filter ................................... (G, Z)
Gain GX- and GR-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. (X, R)
Output to PRN, Harddisk, Screen ........................................ (0)
Quit ................................................................. (Q)
ARCOS>T
Siemens Components, Inc.
588
PEB 2160
Dialog Mode
With the dialog mode the user becomes familiar with the ARCOFI chip in a real environment.
The configuration registers as well as coefficients in CRAM can be read and written.
Any change of register content is instantaneously carried out and the new status of ARCOFI
is displayed on the screen.
Figure 6
Dialog Mode
PCM-Output:
PCM - Input:
GR GZ
Test-Mode
I I I I I I
0
I
0
0
0
0
S
S
C
S
B
S
A ELS AM TR EFC
o
?? dB
FX FR GX
NOT
CR 1
liN liN liN liN I TR I II I 0 ION I CR2
??
TM~
Inc GR
LP
FR " E
TM
MIC-Gain
AGX
Analog
AFEC
52dB
paR
I
LlO
Norm I CR3
DT
DHF MF TG BT TM BM PM Law
?? Hz
?? dB
?? ms
? ? Hz
?? dB
?? ms
I I I I I I I I I
?? Hz
?? dB
?? ms
ARCOS DIALOG
0
AD
WINDOW
0
0
0
0
0
0
AL CR 4
PU RCS
lolRWlolBll
Command
ICMDR
ARCOS> Command Line
The program ARCOS runs on IBM- and IBM-compatible PC when the last is equipped with
a Siemens ISDN User Board SIPB 5000.
Nevertheless a shrinked version of ARCOS, named ARCOSD (ARCOS-DEMO), works without
user board and provides the user with the modes "Search Coefficient" and "Statisticallnformation".
Siemens Components, Inc.
589
PEB 2160
Application Suggestions
The ARCOFI forms, together with a PES 2070 ICC and a PES 2080 SSC (resp. a PES 2085
ISAC-S) a solution for a complete digital telephone as specified in the CCITT I-series
recommendation at the "S" reference point.
The digital telephone can be expanded for hands-free applications by adding the voice
switched speakerphone circuit PSS 45030.
Application Circuit
Handset
n--+--~--lHOP ARCOFI®
L1--\----l---lHON
r- ~~~~:---------~~;'~.~--~'·T§t,
ISAC™-S PEB 2085
AUX 0 - - - - - - - - - . ,
PSB 2160
MIN S8 S( ·SD
I
I
L___
I
_ ________________
MPU
SAB 8051
FHM
SP2
LS
Siemens Components,lnc.
123:;)
4
5
6
7
8
9
590
~
0000
u
,_, ,_, '-'
~
I
I
ISDN Plug
PEB 2160
The terminal mode IOM-2 frames consist of three 10M channels numbered respectively 0,1
and 2. The ARCOFI can receive and transmit voice data in the 10M 81 & 82 channels as well
as in the IC1 and IC2 intercommunication channels located in 10M channels 0 and 1 respectively.
The IC1 and IC2 intercommunication channels can be used in the terminal for local data
communication. This makes postprocessing of voice/data information possible (see figure 7).
Figure 7
Post Processing the ARCOFI Voice Channels
DCLKJlJl[l-----------------------------------------------------FSC
J
L ______________ ~ __________________________~
DU
B1
B2 IMONOIDIClIIMRIMXI IC1 I IC2IMON11C1IIMRIMXI
DO
B1
B2 I MONO I 0 I CII IMRIMXI Ie1 I Ie2 I MON1 I C/I IMRIMXI
DIN
LAYER 1
DOUT
1m ,
ITIC I
DU
----------------------------1
DO
B1
MON1
,--------------,
lC1/IC2
I
I
- - - -......... ----------:±-----------I-i:.t-....;;::t
--,
rr--------r---------fI Tl
B1 I I I
IC111C 2 I
I
IOM®-2 MASTER
I II
RX Signal
Processor
I II
IlLI L-.
L~ 1/0
Siemens Components, Inc.
I
II
L_
TX Signal
"-- DIN
I
I
I
I
.-..J
I
I101':"'~:J
Processor
I
I
I
I
I :
I I
I I
I L-.
ARCOFI
®
i
-.l
L":=;: DIN DOUTt--
RX
SIGNAL
TX
SIGNAL
ARCOFfE
SLAVE
SLAVE
SLAVE
591
I
I
I
I
SIEMENS
IOM-2 Digital Subscriber Controller
PSB 70C30E
(OSe/E)
ADVANCE INFORMATION
General Description
The PSB 79C30E Digital Subscriber Controller (DSC) provides the Terminal Equipment
access to the ISDN. The PSB 79C30E is compatible with the CCID I-Series recommendations at the 'S'- reference point allowing the user of the device to design TEs which
conform to the international ISDN standards.
The PSB 79C30E provides a 192 kbitls full duplex digital path between the TE located in
the subscriber's premises and the NT or PABX line card over 4-wires. The PSB 79C30E
separates the bit stream into the B 1- (64 kbitls), B2- (64 kbitls) and D- (16 kbitls) channels.
The B channels are routed to different sections of the PSB 79C30E under user control.
The D channel is partially processed in the PSB 79C30E and passed to the microprocessor
for further processing.
The transmission rate of 192 kbitls provides a 48-bit frame every 250 IJ.s for framing and
maintenance. The frame structure provides for frame synchronization and multiple terminal
contention resolution as described in the CCID I-series recommendations. Both point-topoint and point-to-multipoint connections are supported.
The PSB 79C30E can be used as a voice telephone, a digital data terminal, or a voice
and data terminal.
The audio processor in the PSB 79C30E, uses Digital Signal Processing (DSP) to implement
the codec and filter functions. The audio processor interfaces to a speaker, an earpiece,
and two separate audio inputs. In the receive and transmit paths the user may program
gain or alter the frequency response.
A serial port gives the user access to the B-channels of the PSB 79C30E multiplexer.
This serial port may be used by data terminals and provides, with additional circuitry,
access to the CCID 'R' reference point.
The PSB 79C30E is controlled via an interrupt driven microprocessor bus interface by an
external microprocessor. Using this interface, the microprocessor processes the D-channel
information and programs the PSB 79C30E accordingly. This includes programming a multiplexer within the PSB 79C30E to route the B-channels as specified by the D-channel
control information. The microprocessor can interrogate and program the PSB 79C30E
via its mode, status, and error registers.
592
PSB 79C30E
Features
•
•
•
•
•
•
Combines CCIlT 1.430 SIT interface transceiver, D-channel LAPD processor, and audio
processor in a single chip
Interrupt-driven microprocessor interface
CMOS technology, TIL compatible
'S' 'T' interface transceiver
Level-1 physical layer controller
Supports point-to-point, short or extended passive bus configurations
Multiframe support
D-channel processing capability
Flag generation/detection
CRC generation/checking
Zero insertion/deletion
Four 2-byte address detectors
Random number generation
16-byte transmit and 32-byte receive FIFOs
Audio processing capability
Dual audio inputs
Earpiece and loudspeaker drivers
Filter/codec with A/j.1-law selection
Programmable gain and equalization filters
Programmable sidetone level
Programmable DTMF, single tone, and ringer tone generation
•
IOM-2 interface
•
Packages: PSB 79C30E-P: P-DIP-40
PSB 79C30E-N: PL-CC-44
Siemens Components, Inc.
593
SIEMENS
ISDN Terminal Adaptor Circuit (ITAC)
PSB 2110
Advanced Information
Type
Ordering Code
ft8;I~~""';<"::;:~ll.~;;ii·
PSB 2110-P
Q67100-H8643
CMOSIC
Package
// .,~;_ _ >,
P-DIP-40
General Device Overview
The ISDN Terminal Adaptor Circuit (ITACTM) is a circuit designed to interface existing standard
Data Terminal Equipment (DTE) to an ISDN via the R reference point (CCITT 1.411).
The circuit autonomously adapts asynchronous or synchronous data according to
CCITT V.110, X.30 and 1.460.
It also supports rate adaption according to V.120 or DMI as well as in-band signaling.
System Implementation
A typical implementation of an ISDN S-interface access for a conventional X-or V-series
terminal using the ITAC is shown in the block diagram (terminal adaptor according to V.110,
X.30, ECMA.102).
The ITAC can be connected via a serial synchronous interface to an S-bus transceiver/LAPD
controller (in this case, the ISDN Subscriber Access Controller ISACTM-S). These two devices,
together with the terminal controller, convert V- and X-series interface characteristics to the
functional and procedural interface characteristics required by an ISDN at the S interface.
Features
• Terminal adaptor for ISDN (R interface), PCSN and CSPDN
• Support of async and sync interfaces (X.21 , X.21 bis, V.25 bis, V.24, RS232C).
• Programmable speeds from 300 biVs to 64 kbiVs
• Bit stuffing rate adaption according to latest standards (X.30, V.110, ECMA.102)
• Programmable subchannels for intermediate rates
• IOM® SSI compatible interface to network (up to 4 MbiVs)
• Parallel 8-bit microcontroller interface
• DMA interface
• Programmable test options
• Higher protocol support
• In-band signaling
• V.120, DMI (bit transparent)
• Single +5 V supply, low power CMOS technology
594
PSB 2110
Block Diagram
V.24
X.21
Asynchron
5ynchron
DCE
Interface
r--
IRC
I--
r--
IO~2,
551
BRC
5
N
I
f--
H
20 Bit
Counter
H
Clock
Generator
=
10.752
MHz
~C
Siemens Components. Inc.
DMA
595
SIEMENS
ISDN Remote Power Controller (IRPC)
Preliminary Data
PSB 2120
CMOSIC
Type
Ordering Code
Package
PSB 2120-P
067100-H8645
P-DIP-22
The PSB 2120 is a pulse width modulator circuit designed for fixed-frequency switching
regulators especially for telefony and ISDN environments.
The PSB 2120 is fully compatible with the CCID power recommendations on the S interface.
Coupled with few external components it provides a stable DC 5 V supply for subscriber
terminals (TEs) or network terminations (NTs). It can also be programmed for higher output
voltages, e.g. to supply the S-lines with 40 V. In telefony and ISDN systems a high conversion yield is crucial to maintain functionality in all supply conditions via "S" or "u" interfaces. The PSB 2120 design and technology realize high conversion efficiency and low
power dissipation.
It should be recognized that the PSB 2120 can also be used in numerous DC/DC conversion systems other than ISDN power supplies.
Features
• Switched mode DC/DC-converter
• CCID (1.430) ISDN compatible
• Integrated 200 V power FET
• Low power dissipation
• Supply voltage range 10 V to 60 V
• Input undervoltage protection
• Programmable overcurrent protection
• Soft start
• Control circuit achieve minimum start-up current
• Power housekeeping input
• Oscillator synchronization inpuVoutput
• Polarity reversal detection
• High voltage CMOS technology 60 V
596
PSB 2120
Pin Configuration
(top view)
SYNC
Vs
RC
VREF
COMP
Ip
Vp
IN
VN
VEXT
[55
GND
EME
CP
POL
eN
GA
co
DR
ENA
SO
[I
Pin Definitions and Functions
Symbol
Input (I)
Definition
Output (O)
1
SYNC
1/0
Synchronization
Input for synchronization of the
oscillator to an external frequency,
or output to synchronize multiple
devices.
2
RC
I
RC-Oscillator
The external timing components of
the ramp generator are attached to
thin pin.
3
COMP
0
Compensation
Error amplifier output and Pulse
Width Modulator (PWM) input for
loop stabilization network.
4
5
Vp
VN
I
I
Pos. voltage sense
Neg. voltage sense
Non inverting input of the error amp.
Inverting input ofthe error amplifier.
6
Gss
I
Soft start capacitor
The capacitor at this pin determines the soft start characteristics.
7
EME
0
Emergency
A low input voltage at POL will
active the output EME .
Pin No.
Siemens Components, Inc.
597
Function
PSB 2120
Pin Definitions and Functions (cont'd)
Pin No.
P-DIP
Symbol
Input (I)
Output (0)
Definition
Function
8
POL
I
Polarity detection
POL is the input to a non inverting
Schmitt-trigger.
9
10
11
GA
DR
SO
0
0
I
Gate
Drain
Source
Output of the FET driver.
Drain connection ofthe power FET.
Source connection ofthe power FET.
12
C1
I
Input capacitor
C1 has to be connected to the input
buffer -capacitor and a current
limiting charging-resistor.
13
ENA
I
Enable
A high input voltage at this pin will
stop the IRPC function.
14
15
CO
CN
0
Connection of the universal usable
comparator.
16
CP
I
Comparator output
Comparator
negative input
Comparator
positive input
17
GND
I
Ground
All analog and digital signals are
referred to this pin.
18
VSEXT
1/0
Externally supply
Output of the internal CMOS
supply. Via VEXT the internal CMOS
circuits can be supplied from an
external DC supply in order to reduce chip power dissipation.
19
IN
I
20
Ip
I
Neg. current
sense
Pos. current
sense
When the voltage difference between these two pins exceeds
100 mV, the digital current limiting
becomes active.
21
VREF
0
Reference voltage
Output of the 4.0 V reference
voltage.
22
Vs
I
Supply voltage
Vs is the positive input voltage.
I
Siemens Components, Inc.
598
VExl
3(I)
:J
C/l
CN
,
(J)
(5"
vsB
o
o
3
2V
-0
o
7.5V
:J
(I)
116
lSJ
~
"71
§ -'
g.
6~~~:~~~n
::l
7 _
>----r--EME
Comparator 1~A
CMOS
Supply
12
18
Jf
pr
9
~~~
POL
14
+
:J
:J
co
CP
'15
18
20
!.
o
iii"
IC
iii
I
p
3
19
1-----1r--] N
Release
U1
<0
<0
= .10V
GND
171
1 I
~b
Control
Logic
Under
Voltage
Detection
1Q... DR
11 SO
Sawtooth
Oscillator
I
r 1I I I
2
SYNC
RC
121
!-REF
15 14
VN
Vp
I
I
3
COMP
I I
6
13
[55
ENA
I
I
9
GA
CE
m
N
~
~
PES 2120
Functional Description
The reference provides a 4.0 V voltage for the regulation loop. A high gain error amplifier
compares the reference voltage with the switch mode supply output voltage. The output
of the error amplifier is compared with a periodic linear ramp, generated by the sawtoothoscilator circuit. The comparator output is a fixed-frequency, variable pulse width logic signal,
which passes through logic circuits to the high voltage power-switching-FET.
A digital current limiting device suppresses the PWM logic signal when the voltage difference
at the current limit sense input reaches 100 mV. In this case the control logic inhibits double
pulses during one oscillator period.
1. Start-Up Procedure
Before the switched-mode DCfDC-converter starts, a sequence of several conditions has to
be passed in order to avoid any system malfunction. The primary undervoltage detection
inhibits the converter function. This insures that all control functions have stabilized in
the proper state when the turn on voltage (ca. 10 V) is reached, and it prevents from startup glitches. In case of connectig the TE to powered lines or if a line is powered up, the
charge current of the primary buffer capacitor is limited by an external resistor (figure 2).
This resistor is short-circuited by the PSB 2120 when the voltage drop across it falls below
about 2.0 V. The residual resistance of this short-circuit is about 3 Q. In case of a primary
undervoltage detection the short-circuit will be always deactivated. So the DCfDC-converter does not start until the charging of the primary buffer capacitor is completed, and the
maximum line input voltage is reached. (If this feature is not desired, C1 has to be connected
to GND. In this case the primary current measuring circuit turns off, to reduce chip-power
dissipation from 9 mW to 6 mW). In order to avoid high current peaks during the charging
of the secondary capacitors or line capacitors in case of supplying a S interface, a soft
start circuit is implemented in the PSB 2120. This circuit requires an external capacitor,
connected between Css and GND.
In addition, the Enable input (ENA) allows an external switch-onfswitch-off control. In the
DCfDC-converter is disabled via ENA, the soft start-capacitor at pin Css is discharged.
This input can also be used for several other functions, e. g. secondary overvoltage protection.
Siemens Components, Inc.
600
PEB 2120
Figure 2
2V
Short
Circuit
Under
Voltage
Detection
~10V
GND
2. DCfDC-Conversion
The PSB 2120 contains a SIPMOS transistor for power handling. Non-isolated and isolated
SMPS configurations are possible. Logic and analog circuits are implemented in CMOS in
order to achieve low power dissipation.
The error amplifier compares the sensed voltage with a reference attached to Vp and thus
controls the Pulse With Modular (PWM). The conversion frequency is generated by a sawtooth oscillator which can be controlled by external RC-components or by an external synchronization signal. The PSB 2120 is synchronized by the rising edge of the SYNC signal,
whose frequency must be 10% higher than the free run frequency, determented by the RCcomponents. The SYNC pin can also be used as a tri~ger-outPut. As long as the capacitor
of the sawtooth oscillator is discharged, SYNC is high.
The output of the PWM is processed by the control logic and fed to the SIPMOS transistor
The control logic suppresses higher oscillations of the regulation loop caused e.g. in case
of current limit detection.
Siemens Components, Inc.
601
PES 2120
3. Polarity Detection
Emergency conditions are signaled to the TE by the reversed polarity of the line feeding
voltage. When polarity reversal is detected via pin POL of the PSB 2120, emergency
conditions are signaled to the microprocessor via pin EME, which should shut down all
activity except simple telephony functions to minimize power dissipation.
The polarity detection circuit can also be used for other detection or protection functions,
e. g. programmable primary undervoltage detection.
4. Power Housekeeping
An integrated 6 V linear voltage supplies the internal circuits during the start-up phase.
Power dissipation of this regulator can be reduced, if an auxiliary winding of the transformer or an external supply is used for that purpose by connecting it to VEXT ' If the input
voltage at VEXT reaches 6.3 V the internal linear voltage regulator turns off and the internal
circuits are fed from this external voltage. In this case the input current at VEXT is approx.
0.5 rnA.
Note: An internal 7.5 V Z-diode protects the VEXT input against overvoltages. The maximum
Z-current is 2 rnA! If the external supply isn't stabilized, the input current must be
limited (e. g. by a resistor)!
5. Interface to Microprocessor
The PSB 2120 offers two TTL-compatible signals: EME and CO.EME (Emergency) becomes
active, if polarity reversal is detected. CO is the output of a universal useable comparator;
e. g.: to generate a microprocessor-reset signal.
6. PSB 2120 Application in ISDN Environments
Figure 3 shows an example out of the wide application field of the PSB 2120. In the
network termination one PSB 2120 supplies the internallCs directly from the "U" interface.
A second IRPC, also powered from the "U" interface. A second IRPC, also powered from
the "U"-line, supplies the "S" interface if the main supply of the NT is out of order. A third
IRPC is used in the main supply to regulate the "S"-line feeding voltage.
In the subscriber terminal the PSB 2120 is used for feeding the internal circuits. The
PSB 2120 accomodates both galvanically isolated and non-isolated configurations. Considering the diversity of DC/DC-converter applications, this part of the specification only
shows how to use the special ISDN features of the PSB 2120.
The simpliest form of a flyback converter is shown in figure 4. The time constant of the
soft start circuit is programmed by a capacitor at pin 6 (Css )'
Siemens Components, Inc.
602
PSB 2120
Figure 3
IRPC in ISDN Concept
QU"
"S"
IC-Supply
IC-Supply
i
PSB 2120
J
r--
)~ r--!-
11[
~
Subscriber
Terminal
-
PSB 2120
-
PSB 2120
--
+
-
PSB 2120
I
Network
Termination
11[
I
I
220 V
Siemens Components, Inc.
603
en
ro"
CEl!
11...60V
+
m~
3([)
(JI
()
0
3
""C
0
::J
-
I
1OP
lp,J081Q
'
([)
!Il
$">
1\)01:00
0
::J
5"
~ iiJ
TR1
::J
N,
s:::
5"
BSY21-45
+5V
Nz
T
0
:::J
T100~F
=
co
c
14
OV
PSB 2120
N3
7
.j:>.
1 pF
,..
220pF
+1nF
$1~F
I
c
3
0
r
Ol
0
3"
L.J 14 kQ
1156 kQ
1100pF
I -
iii
cr.
0
:::J
-5V
BYS 21-45
TR 1: RM 6
AL = 140nH
N, = 2x93T
Nz = 37 T
N3 = 37 T
CB
ED
I\)
.....
~
PSB 2120
Figure 5
Advanced IRPC Application with Power Housekeeping and Polarity Reversal Detection
>
>
>
o
'"+
'"
I
-I
:I:
c:
"-
=>-
N
II
~
-:""7""
'" ~
1'-:"\
"-
IX>
N
~
-
..
~
II
II
II
II
Q:...-Nm4
VI
:.....:L
>IX>
....
o
'"
L~
*
*
~lr
Figure 5 shows the primary start-up current limitation by connecting pin 12 (q
To reduce chip power dissipation, an auxiliary winding of the transformer is used to switch
off the internal linear CMOS supply (pin 18 V EXT)' Polarity reversal is detected by pin POL.
Siemens Components, Inc.
605
PSB 2120
Figure 6
Generation of a J.l.P Reset Signal with the PSB 2120
11. .. 60V
22
PSB 2120
1 MQ
1S
14
1jJF
GND
I
I
I
I RES
Figure 6 shows the realization of a microprocessor reset signal with the universal useable
comparator of the IRPC.
Two galvanically isolated applications are shown in figure 7 and figure 8.
Siemens Components, Inc.
606
!!!
CD
3
11. ..60V
(E!1
m~
~i
VI
CD
::J
en
()
o
3
VI
o::J
CD
::J
Yl
~
2 kQ
:!!
±2.2 fl F
N,
.
-
::J
P
12
8
22
18
+5V
in
~
0
~
~11
19
'<
BYS 21-45
0
[]0.82 Q
h6
....
(;)
5·
±2.2~F
"0
N
TR1
200Q
~
N
N2
*220flF
::!I
IG
C
ii1
d:
0
10
b
~
b4
OV
§.
:r
-I
ii1~
a>
o
BAW76
PSB 2120
-...J
15
17
6
2
11
21
........
4
3
5
13
j17
VI
5;
T20~F
=
i=1~F
""I
'''''1
[]30kQ
5
=-220 pF
IA
=
=1nF
5; iii!
1~F
$100~F
~
.A
[]47kQ
[ ]100kQ
N3
1N 4001
I------<
N
...3a...CD
LA
[]56kQ
.
~_
N4
0.3~F
-5V
BYS 21-45
ii
g~
TR1: RM8 Al =630nH
N, = 2x35T
N2 = 19T
N3 = 19T
N4 = 22T
ex
III
N
.....
N
0
Q:! 11... 60VbI
PSB 2120
CD
i"n!!
~
100flF
N4
~
o
15
17
6
11
21
2
~ln30
l,JkR
~kn
"*
='=
720flF
=l=1~F
14
3
5
13
:::lI
F
-L... i i
047kR
KI •
-5V
_ _ _ _ _ _ _ _ _ _ _ _ _ _ ..Ji
~220pFi~ 51 kR=f"1nF
"""T""" 1~F
i
TR1 BYS 21-45
0100kR
....I.d.
N
L..
TR 1: RM a AL = 630 nH
N,=2x35T
Ni = 19 T
N3 = 19 T
N4 = 22 T
()J
m
N
...a.
~
PSB2120
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Supply voltage Vs (pin 22) referred to GND
Vs
60
V
Analog/digital input voltage referred to GND
(pins 2. 3. 4. 5. 7. 8. 13. 15. 16. 19. 20)
iii AID
6
V
Reference output current (pin 21)
10 REF
-5
mA
VEXT
input Z-current
liz
2
mA
VEXT
output current
10
-5
mA
mA
Driver output current (pin 9)
10 SYNC
10 DR
-5
-5
mA
Ambient temperature under bias
TA
-25 to 85
°C
Storage temperature
Tstg
-40 to 125
°C
Thermal resistance
Junction - ambient
1j
50
KlW
SYNC output current (pin 1)
MOS-Handling
Pin 9 must be protected against voltages of ± 10 V. All either pins are protected against ESO.
DC Characteristics
TA = 0 to 70°C, Vs = 11 to 60 V
Parameter
Test Conditions
Reference VREF (pin 21)
1j = 25°C
Output voltage
VREFO
Line regulation
VREF Line
3.92
4.0
4.08
V
60
mV
IL=O mAo
Vs =40 V
Vs =20to 60 V
IL=O mA
Load regulation
20
VREF Load
40
mV
IL = 0.1 to 0.3 mA
Vs = 40 V
Temperature stability
VREFTS
Load qurrent
IREF Load
Siemens Components, Inc.
25
mV
0.5
609
mA
over operating 1j
PSB 2120
DC Characteristics (cont'd)
Parameter
Test Conditions
Oscillator SYNC (pin 1), RC (pin 2)
'osc = 20 kHz, Rc = 39 kO ± 1%, CT = 1 nF ± 1%, TA = 25°C
Initial accuracy
Voltage stability
1
Temperature stability
5
Max. frequency
%
±10
'max
3
%
%
kHz
200
Rc=27 kO
CT =39 pF
H-sawtooth voltage
VH
3.2
V
Vs =40 V
L-sawtooth voltage
VL
1.8
V
Vs =40V
H-sync output level
VOH
5.25
V
IL =0.5 mA
L-sync output level
VOL
0.4
0.8
V
IL =
3
10
mV
2.4
Vs EXT~6.3 V
20 itA
Error Amplifier
COMP (pin 3), Vp (pin 4), VN (pin 5)
Input offset voltage
~o
Input current
I,
Common mode range
Vc
1.8
10
nA
4.5
V
DC open loop gain
Gvo
60
70
dB
Common mode rejection
kCMR
60
70
dB
Unit gain bandwidth
f
0.5
MHz
70
dB
Supply voltage rejection
H-output voltage
VOH
L-output voltage
VOL
Current Limit Comparator Ip (pin 20),
C L (pin) 10 pF
V
IL=1001tA
1
V
IL =
115
mV
Vs=40 V
4
10 itA
IN (pin 19)
TA=25°C
Sense voltage
VSense
Input current
I,
Input voltage range
~
Reponse time to signal at GA
(pin 9)
t Res
Siemens Components, Inc.
100
85
0
1
610
10
nA
1
V
2
its
PSB 2120
DC Characteristics (cont'd)
Test Conditions
Parameter
Pulse Width Modulator
Duty cycle
td
0
I Ie
2
50
%
8
I1A
Undervoltage Detection
Start-up threshold
Threshold hysteresis
Soft Start Gss (pin 6)
CT Charging Current
4
Output Driver GA (pin 9)
1j = 25 °C
H-output voltage
VOH
H-output voltage
VOH
V
Isource = 5 mA
VSEXT
V
Isource = 0 mA
4.5
L-output voltage
VOL
0.4
V
I sink = 5 mA
Rise time
tr
130
200
ns
CL =220 pF
Fall time
t,
130
200
ns
CL =220 pF
Output current
10
5
mA
External Supply VEXT (pin 18)
Output voltage
10
Input voltage
Vi
Z-current
V
6
Vo
Output current
6.0
lz
2
mA
7.5
V
2
mA
5.25
V
0.8
V
1
I1s
Isource = 1 mA
Enable Input ENA (pin 13)
H-input voltage
L-input voltage
ViH
ViL
2.0
Response time to signal at GA
(pin 9)
tRes
0.5
H-input current
IIH
2.5
Siemens Components, Inc.
611
I1A
7j = 25°C
PSB 2120
DC Characteristics (cont'd)
Parameter
Test Conditions
Comparator CN (pin 15), CP (pin 16), 7j = 25 ac
Input offset voltage
Vio
Input bias current
II
Input voltage range
Vi
Response time to signal at CO
(pin 14)
tRes
3
1.5
2.0
10
mV
10
nA
4.5
V
1
Il s
5.25
V
0.8
V
Short Circuit ~ (pin 12), 7j = 25 ac
Sense voltage
Polarity Detection POL (pin 8), EME (pin 7)
H-input voltage
ViH
L-input voltage
ViL
H-input current
IIH
1
10
IlA
Response time to signal
at EME (pin 7)
tRES
0.2
1
Il s
2.0
Digital Outputs EME (pin 7), CO (pin 14)
lOUT = 0.5 mA
Vs EXT~6.3 V
H-output voltage
L-input voltage
Power FEr GA (pin 9), DR (pin 10), SO (pin 11)
Vos
200
V
10
350
mA
6
g
Id (on)
I,
15
40
ns
ns
Id (off)
If
70
40
ns
ns
Ros
ton
=
Id(an)
+ I,
loft
=
Id(oft)
+ If
(on)
Leakage current
I Leak
Power consumption
Ptot
Siemens Components, Inc.
9
612
200
nA
Vos= 200 V
10
mA
Vs= 40 V
fose = 20 kHz
VSEXT = 6.3 V
SIEMENS
General Purpose Power Controller (GPPC)
CMOSIC
Preminimary Data
Type
Ordering Code
Package
PSB 2J21-P
Q67100-H8646
0671OD-H6032
P-DIP-16
P-DSO-20 (SMD)
PSa2121~T
PSB2121
The PSB 2121 is a pulse width modulator circuit designed for fixed-frequency switching
regulators with very low power consumption.
In telefony and ISDN systems a high conversion yield is crucial to maintain functionality
in all supply conditions via "S" or "U" interfac~s. The PSB 2121 design and technology
realize high conversion efficiency and low power dissipation.
It should be recognized that the PSB 2121 can also be used in numerous DC/DC conversion systems other than ISDN power supplies.
The PSB 2121 Contains the Following Functional Blocks
• Undervoltage lockout
• Temperature compensated voltage reference
• Sawtooth oscillator
• Error amplifier
• Pulse width modulator
• Digital current limiting
• Soft start
• Double pulse inhibit
• Power driver
Together with few external components it provides a stable 5 V DC supply for subscriber
terminals (TEs) or network terminations (NTs). It can also be programmed for higher output
voltages, e.g. to supply S-Iines with 40 V.
•
•
•
•
•
•
Switched mode DC/DC-converter
CCID ISDN compatible
Low power dissipation
Supply voltage range 8 V to 70 V
Programmable input undervoltage protection
Programmable overcurrent protection
•
•
•
•
Soft start
Power housekeeping input
Oscillator synchronization input/output
High voltage CMOS technology 70 V
613
PSB 2121
Pin Configurations
(top view)
P-DSO-20
P-DIP-16
DC
REF
DC
OR
N.C.
SYNC
Ip
OR
N.C.
SYNC
GND
GA
GND
UV
GA
EN
IN
VEXT
N.C.
[ss
Vs
EO
Siemens Components, Inc.
614
PSB 2121
uv
EN
EP
N.C.
EO
PWMP
PSB2121
Pin Definitions and Functions
Symbol
Input (I)
Definition
Output (O)
1
REF
0
Reference voltage
Output of the 4.0 V reference
voltage.
2
Ip
I
3
IN
I
Positive current
sense
Negative current
sense
When the voltage difference between these two pins exceeds
100 mV, the digital current limiting
becomes active.
4
GND
I
Ground
All analog and digital signals are
referred to this pin.
5
GA
0
Gate
Totem-pole output driver, has to
be connected with the gate of an
external power switch.
6
VEXT
I/O
External supply
Output of the internal CMOS supply.
Via VEXT the internal CMOS circuits
can be supplied from an external
DC-supply in order to reduce chip
power dissipation.
7
Css
I
Soft start
capacitor
The capacitor at this pin determines the soft start characteristic.
8
Vs
I
Supply voltage
Vs is the positive input voltage.
9
PWMP
I
Pulse width
modulator
Non inverting input of the pulse
width modulator.
10
EO
0
11
EP
I
12
EN
I
13
UV
14
15
16
Pin No.
P·DIP
Function
Error amplifier output.
Positive voltage
sense
Negative voltage
sense
Non inverting input of the error
amplifier.
Inverting input of the error amplifier.
I
Undervoltage
detection
The undervoltage lockout can be
programmed via UV.
SYNC
I/O
Synchronization
This pin can be used as an input
for synchronization of the oscillator
to an external frequency, or as an
output to synchronize multiple
devices.
OR
OC
I
I
R-Oscillator
C-Oscillator
The external timing components of
the ramp generator are attached
to OR and OC.
Siemens Components, Inc.
615
I
en
VEXT
(D"
3
-
+PW
=
8V
~+
Sawtooth
Oscillator
T
Soft
Start
1
~
GND
4
SYNC
14 15 16
1
OR OC
REF
9
PWMP
7
5
[55
GA
CE
m
I\)
...a.
I\)
...a.
PSB 2121
Absolute Maximum Ratings
Parameter
Supply voltage (pin
Limit Values
Symbol
Vs ) referred to GND
Unit
Vs
80
V
iliA
6
V
Reference output current (pin REF)
10 REF
-5
mA
SYNC output current (pin SYNC)
10 SYNC
10 Amp
-5
mA
-5
rnA
Analog input voltage
(pins I p, IN, PWMP, EP, EN, SYNC, OR, OC)
referred to GND
Error amplifier output current (pin EO)
Z-current (pin VEXT)
lzEXT
2
rnA
Output current (pin VEXT)
10 EXT
-5
rnA
Driver output current (pin GA)
lOR
-5
rnA
Ambient temperature under bias
TA
-25 to 85
DC
Storage temperature
Tstg
-40 to 125
DC
DC Characteristics
TA = 0 to 70 DC, Vs = 8 to 70 V
Limit Values
Parameter
Symbol
Supply current
Is
min.
1typo 1max.
130
Unit
Test Conditions
IJ-A
Vs EXT ~6.3 V
4.08
V
l.
60
mV
I
Reference VREF
Output voltage
VREFO
Line regulation
VREF Line
3.92
4.0
= 25 DC,
L=O rnA,
Vs=40V
Vs =20 to 60 V
l.
= 25°C,
L=OmA
Load regulation
VREF Load
20
Temperature stability
VREFTS
25
Load current
Siemens Components, Inc.
40
0.5
IREF Load
617
IL =
mV
0.1 to 0.3 rnA
Vs =40V,
1j = 25°C
mV
0 ... 70°C
rnA
PSB2121
DC Characteristics (cont'd)
Parameter
Test Conditions
OscillatorISYNC/OC
fosc
= 20 kHz, Rc = 39 kO ± 1%, Ro = 0 0, Cr = 1 nF ± 1%
Initial accuracy
~ =25°C
Voltage stability
Temperature stability
%
±10
1
5
3
%
%
Max. frequency
f max
Sawtooth peak voltage
Sawtooth valley voltage
Vs
Vs
H-sync output level
VSYNCH
L-sync output level
VSYNCL
Input offset voltage
\lio
Input current
II
Common mode range
CMR
1.8
DC open loop gain
Gvo
60
70
dB
kCMR
60
70
dB
kHz
Rc= 27 kQ
C r = 39 pF
V
V
Vs= 40 V
Vs= 40 V
5.25
V
IL =
0.4
0.8
V
IL =
3
10
mV
200
3.2
1.8
2.4
0.5 mA
VexT :S;6.3 V
20 IJ.A
Error Amplifier lEO IEP lEN
Common mode rejection
10
nA
4.5
V
Unity gain bandwidth
f
0.5
MHz
Supply voltage rejection
kSVR
70
dB
H-output voltage
L-output voltage
VOH
VOL
CL (pin) :s; 10 pF
1
V
V
IL=-100IJ.A
I L = 1O I-L A
115
mV
Vs= 40 V
10
nA
1
V
2
IJ.s
4
Current Limit Comparator [pi IN'
~ = 25°C
Sense voltage
VSense
Input bias current
II
Input voltage range
\Ii
Response time
(signal at GA)
tRes
Siemens Components, Inc.
100
85
0
1
618
PSB2121
DC Characteristics (cont'd)
Parameter
Test Conditions
Pulse Width Modulator
Duty cycle
td
0
50
%
Under Voltage Detection UV
Start up threshold
pin UV= Vs
Threshold hysteresis
pin UV = Vs
Soft Start Gss
Charging current
Cr
2
VOH
4.5
4
8
j.lA
Output Driver GA
7j= 25°C
High output voltage
Low output voltage
VOL
Rise time
tr
130
Fall time
t,
130
Output current
10
V
Isource = 5 mA
0.4
V
I sink = 5 mA
200
ns
CL =220 pF
200
ns
CL = 220 pF
5
mA
External Supply VEXT
Output voltage
Output current
10
Input voltage
~
Z-current
lz
Power Consumption
Ptot
Siemens Components, Inc.
V
6
Va
6.0
5
619
2
mA
7.5
V
2
mA
6
mW
Isource = 1 mA
Vs = 40 V
'ose = 20 kHz
VExr= 6.3 V
PSB2121
Application Information
Undervoltage Lockout
The undervoltage lockout circuit protects the PSB 2121 and the power devices· from inadequate supply voltage. If Vs is too low, the circuit disables this output driver. This ensures
that all control functions have been stabilized in the proper state when the turn on voltage
(8 V) is reached, and it prevents from the possibility of start up glitches. The undervoltage
lockout is programmable by connecting a Z-diode between Vs and UV from 8 V up to 70 V.
If UV is connected to Vs the default undervoltage lockout is 8 V.
Voltage Reference
The reference regulator of the PSB 2121 is based on a temperature compensated bandgap.
This circuitry is fully active at supply voltages above +6.0 V and provides up to 0.5 mA
of load current to external circuitry at +4.0 V. This reference has to be buffered by an
external capacitor> 0.5 f.LF.
Oscillator
The oscillator frequency is programmed by three components: Ro C, and Ro as shown
in figure 2. The oscillator timing capacitor CT is charged by VREF through Rc and discharged
by Ro. (Ro is series-connected with an internal 9 kQ discharge-resistor). So the rise-time
and the fall-time of the sawtooth oscillator can be programmed individually.
Figure 2
REF
PSB 2121
OC 1 - - - - - - - ;
OR I---{~---;
GND
The PSB 2121 could be synchronized by the rising edge of the SYNC signal, whose frequency must be 10% higher than the free run frequency, determined by the RC-components.
The SYNC pin can also be used as a trigger-output. As long as the capacitor of the
sawtooth oscillator is discharged, SYNC is high. So multiple devices can be synchronized
together by programming one master unit for the desired frequency.
Notice that the frequency of the output driver is half the oscillator frequency.
Siemens Components, Inc.
620
PSB2121
Soft Start Circuit
The soft start circuit protects the power transistors and rectifier diodes from high current
surges during power supply turn-on. When the supply voltage is connected to the PSB 2121
the undervoltage lockout circuit holds the soft start capacitor voltage at zero. When the
supply voltage reaches normal operating range an internal 4 f.LA current source will charge
the external soft start capacitor. As the soft start voltage ramps up to +5 V, the duty cycle
of the PWM linearly increases to whatever value regulation loop requires.
Pulse Width Modulator
The pulse width modulator compares the sawtooth-voltage of the oscillator output with the
input signal at PWMP and with the voltage of the external soft start capacitor at Css
(see figure 1).
Error Amplifier
Conventional operational amplifier for closed-loop gain and phase compensation. Low
output impedance: unity-gain stable.
Control Logic
The control logic inhibits double pulses during one duty cycle and limits the maximum
duty cycle to 50%.
Current Limiting
A differential input comparator terminates individual output pulses each time when the
sense voltage rises above threshold.
When sense voltage rises to 100 mA above threshold a shutdown signal is sent to the
control logic.
CMOS Supply
An integrated 6 V linear voltage regulator supplies the internal low-voltage CMOS circuits
from the input voltage. This supply voltage is connected to pin VEXT and has to be buffered
by an external capacitor (Cm;n = 1 f.LF). Power dissipation of the linear voltage regulator
can be reduced, if an external supply is used for that purpose by connecting it to pin VEXT '
If the input voltage at VEXT reaches 6.3 V the internal linear voltage regulator turns off and
the internal CMOS circuits are fed from the external voltage. In this case the input current
at VEXT is approx. 0.5 mA.
Note: An internal 7.5 V Z-diode protects the VEXT input against overvoltage. The maximum
Z-current is 2 mAl So if the external CMOS supply isn't stabilized the input current
must be limited (e.g. by a resistor).
Siemens Components, Inc.
621
PSB 2121
Extended Input Voltage Range
Some DC/DC-converter applications require a higher input voltage than the maximum supply
voltage of the psa 2121 which is limited to 70 V. Figure 3 shows a method to extend the
input voltage range by connecting a Z-diode between the input voltage and Vs ofthe psa 2121.
Figure 3
V1N
LS:
Vz
Vs
iii ~
iii ~
PSB 2121
GND
GND
If the psa 2121 is fed via VEXT • the input current at pin Vs is approx. 30 !-LA. The additional
power losses are accordingly 30 !-LA . Vz ; the minimum input voltage is Vz + 8 V.
Siemens Components. Inc.
622
Support Tools
I
ISDN PC Development System
Overview
This document is an introduction to the new Siemens ISDN PC Development System.
The system consists of:
•
Modular hardware in the form of the Siemens ISDN User Board (SIPB)
and of several software packages:
•
Mainboard Firmware (MF) to drive the Siemens ISDN PC Board hardware
•
Extensive user friendly Menu Software on PC
•
ISDN Operational Software (lOS) including ready-to-use ISDN Layer-2 and Layer-3
protocols for the Link Access Procedure and Call Control functions according to cCln
standards.
The above hardware and software makes a PC look like a terminal capable of communicating
with the outside world via a voice/ data ISDN network.
Finally, the
•
Siemens ISDN Software Development and Evaluation System (SIDES) contains all the
tools for the customer to develop and test new protocol software using a high-level
language based on Cln's Functional Specification and Description Language (SDL,
CCITT Z. 100 Series).
In short, the use of the Siemens hardware and software tools provides significant savings in
R&D time when designing a customer specific ISDN application.
The following first section of this overview document gives the scope of applications of the
ISDN software tools.
Siemens Components, Inc.
625
I
ISDN PC Development System
1
Introduction
1.1 Design Challenges in ISDN System Development
Designing an ISDN application is a time-consuming task in terms of hardware and software
development and testing. Proper tools can provide significant reductions in R&D costs.
Some of the challenges that engineer implementing an ISDN application has to face are as
follows:
A) Design of Hardware
A stable hardware environment is an absolute requirement to start developing any ISDN
communication application. Meaningful testing of hardware is often possible only with a
dedicated development system.
B) Creation of Firmware
The testing of firmware (including device drivers and interrupt handlers) is complicated
by the fact that firmware is, by definition, real-time. Dynamic hardware errors are difficult
to distinguish from errors in the firmware. An emulator often is necessary to detect,
analyze, and correct these errors.
C) Creation of a Software Development Environment
The entire development environment should ideally be inexpensive, for instance a PC,
for which compilers, editors and other tools are widely available.
D) Protocol Modifications
Without additional tools, the smallest change in the initial protocol often entails timeconsuming coding and verification. All modifications should be automatically documented.
E) Static and Dynamic Testing
Initial static and dynamic testing of the software should be possible independent of the
hardware, but without the need of an expensive emulator.
Siemens Components, Inc.
626
ISDN PC Development System
1.2 The Siemens ISDN PC Development System
The new Siemens ISDN PC Board and the associated software packages have been created
to considerably simplify the implementation of such highly complex and wide-ranging tasks.
To this end, the Siemens ISDN PC Development System offers the user:
A flexible, modular hardware architecture with options that cover virtually all ISDN applications, based on the advanced Siemens ISDN Oriented Modular (IOM®) architecture.
Comprehensive software according to the Open Systems Interconnection (OSI) layered
model.
Clear interface between the protocol software modules and the outside world.
Complete programm generation tools that enable the user to create his own protocol
software using a high-level SOL-like description language.
An advanced testing concept which allows software test on the PC before running it on
the target ISDN hardware.
1.3 What a Customer Needs
All the customer needs to provide to use the Siemens ISDN PC Development System is:
an IBM PC XT / AT or compatible including:
512 Kbyte of RAM
harddisk drive and diskette unit
Microsoft© C-compiler V4.0 or upwards.
Siemens provides the necessary ISDN hardware and the various software packages according to the particular needs and applications of the customer. The software is available on
51/4" diskettes (double sided double density).
Siemens Components, Inc.
627
I
ISDN PC Development System
1.4 Summary of the Hardware and Software Packages
Hardware is provided in the form of a modular Siemens ISDN PC User Board (SIPB) which
can be configured:
as an ISDN Voice/Data Terminal (TE)
as an ISDN Network Termination Simulator (NT-S)
or as an ISDN Line Card (LC) in a Telephone Switching System.
The SIPB is accompanied by resident Mainboard Firmware (MF) which includes the necessary device drivers, memory management and interrupt handlers for the ISDN hardware.
Extensive Menu Software (MS) allows the customer to program the ISDN components directly
from a PC.
Off-the-shelf protocol software is available in different packages known under the generic
name of ISDN Operational Software (lOS). This software includes:
data link layer for the ISDN user-network interface, in other words, the Layer-2 Link
Acces Procedure on the 0 channel (LAPD)
Layer-3 generic call control software, executing the basic voice and data service call
control procedures
switch specific call control software.
Although the lOS is essentially hardware independent, the highest possible efficiency can
be reached with the Siemens ISDN components based on the 10M architecture.
Finally, a comprehensive set of software tools is provided in the form of the Siemens ISDN
Software Development and Evaluation System (SIDES) that runs on a PC.
SIDES consists of:
the Program Coding Tools (PCT), and
the Siemens ISDN Protocol Software Test Tools (SITEST).
The PCT's enable the user to create complex protocol software for Layer 2 and Layer 3 of
the OSI communications model in a simple fashion. Thus, they allow:
to define the protocol using a language similar to SOL
to create object coede by applying only a few generators and a standard C compiler
to create on line and hardcopy documentation.
Siemens Components, Inc.
628
ISDN PC Development System
SITEST is an efficient software package for verifying the operation of protocol software
before it is downloaded on customer specific communication hardware. The package consists of:
• A Static Test Tool for Protocol Software (STEP).
This tool runs on a PC independent of any other hardware to provide a single step test
of the protocol.
• A Dynamic Real·Time Communication Tester (DYRECT).
This programm on a PC allows to verify the dynamic of the protocol software in association
with the firmware and a peer station.
In conclusion, with the new ISDN PC Development System Siemens offers the customer
the same flexibility as known from the ISDN 10M concept:
•
A modular ISDN PC Board
•
Off·the-shelf ISDN Protocol Software with clear interfaces
•
A complete set of ISDN Software Development Tools.
In chapter 2 of this overview document you will find a description of the SIPB hardware.
The firmware and the ready-to-use ISDN Operational Software and Menu Software are
explained in chapter 3. In chapter 4 a general step-by step strategy is outlined for developing
user specific protocol software using the SIDES. A list of manuals provided on the hardware
and software is given at the end of the document.
Siemens Components, Inc.
629
I
ISDN PC Development System
2
H.rdware Description
The heart of the Siemens ISDN PC Board (SIPB) is a mainboard designed to fit in a full-sized
card slot of a personal computer IBM XT/AT. The board includes a complete microcomputer
system with:
•
an SAB 80188 microprocessor
•
a 128 Kbyte (optional 64 Kbyte) EPROM which contains the Mainboard Firmware
•
256 Kbyte of RAM to which ISDN Operational Software from the PC is down - loaded
•
PC bus interface with a dual port RAM and DMA capability.
This interface allows the PC application software to control the SIPB.
As shown in figure 1, six connectors are provided for daughter boards. These contain the
Siemens VLSI circuits of the ISDN Oriented Modular (10M) family to fulfill different user
specific ISDN applications.
Figure 1
Siemens ISDN PC Board
Inside PC
/
A
I
I
Add·On Modules
PC
..I....
I
\
I
Outside PC
Service
Access
Modules
- CJ
Siemens Components, Inc.
630
ISDN PC Development System
Add-On Modules
All daughter boards that need direct microprocessor control have to be plugged into a 96-pin
Add-On Module connector.
Such add-on modules contain an EPROM. This EPROM can be read by the microprocessor
to identify the hardware of the add-on module.
E.g. layer-2, or audio interface add-on module.
Universal Service Access Modules
Daughter boards that do not require microprocessor control but are controlled by an add-on
module via a serial port are called Service Access Modules. A service access module is a
module which can be connected to a 9 pin service access slot corresponding to the controlling add-on module slot. There is a one-to-one correspondence between add-on module
slots and service access module slots (see figure 2).
Universal service access modules can also be plugged into an add-on slot if the user so
desires, because they have additionally a 96 pin connector. In this case the position of the
daughter boards in the add-on slots is not critical.
Figure 2
Add-On Modules
CD
Inside PC
CD
I
• I.
I
I
I
I
Outside PC
Service Access
Modules
'Pi'Om
,p;,O°
,p;'O®
96-Pin AddOn Module
Connector
Main board
9·Pin Service Access
Modu Ie Connector
Siemens Components, Inc.
631
I
ISDN PC Development System
Special Service Access Modules
These Service Access Modules can only reside outside the PC, because of their size or the
fact that they have only a 9-pin access connector. E.g. telephone module, or primary rate
line interface module.
An example of the SIPS in a terminal application is shown in figure 3. The board is configured as an ISDN TE connected to the basic access S bus via the layer-1 S bus service
access module. A layer-2 module contains an ISDN communication controller (ICC: PES 2070)
which offers the access to the ISDN signaling channel (0 channel). The module also contains
a High Level Serial Communication Controller (HSCC: SAS 82520) which may be used as a
source/sink for data in one or both of the ISDN circuit-switched S channels. The audio interface module contains the circuitry to interface the telephone into the SIPS architecture. The
telephone module contains the PSS 2160 Audio Ringing Codec Filter (ARCOFI) to perform
the AID conversion, compensation filtering and ringing functions. It also contains a DTMF
generator to transfer the keypad information to the audio interface module where it is decoded for microprocessor access.
Figure 3
SIPS in a Voice/Data Terminal
S-Layer 1
Siemens Components, Inc.
Layer 2
Audio
632
Interface
Telephone
ISDN PC Development System
Through the modularity of design, the ISDN PC Board offers the user flexibility inherent in
the 10M concept.
Kits of hardware and software are available for commonly used ISDN applications such as:
•
an ISDN Voice/Data Terminal for the S Basic Access
•
an ISDN Voice/Data Terminal for the two-wire (U) subscriber loop (using echo cancellation)
•
an ISDN Voice/Data Terminal for the two-wire (U*) subscriber loop (using time compression multiplexing)
•
an ISDN Network Termination Simulator (NT -S) for the S interface
•
an ISDN Line Card for Basic (S, U or U*) or Primary Access (1544kbiVs S1/T1 or
2048 kbiVs S2/CEPT interface).
3
Software Description
The following software packages are available to support the ISDN PC Board hardware:
•
Object Code:
- the Mainboard Firmware (MF) resident on SIPB
- the ISDN Operational Software (IDS) executed on the PC or downloaded and executed
on the SIPB hardware
- the Menu Software (MS) executed on PC.
These are briefly discussed in this chapter.
• Tools which run on a PC namely
- the Siemens ISDN Software Development and Evaluation System (SIDES).
The use of these tools is explained in chapter 4, where a general step-by step development
strategy is outlined for the design and testing of user specific ISDN protocol software.
Siemens Components, Inc.
633
ISDN PC Development System
3.1 Access to ISDN and Layered Protocol Architecture
The User Access to the ISDN consists of:
•
a number of 64 kbitls bearer channels (n x B)
e.g. n = 2 for basic rate ISDN access
n = 30 or 23 for primary rate ISDN access;
•
and a signaling channel (D), either 16 (basic rate) or 64 (primary rate) kbit/s
(see figure '4).
Figure 4
Layer 3 and Up I
Layer 2
Layer 1
I Layer 2
I
I
:-- -":---:"1"1
I
I
I
I
I
0 0
L
I
I
I I
I
I
I
II
I I
I
I
I
I I
I I
_LI
ISDNNetwork
ISDN
User
Terminals
I
Mainframe
I
I
D
I
I
I
I
I
I
I
I
I
I
I
I
I
0.930/1
Siemens Components, Inc.
0.920/1
0.910/1; 1.1.30
1.431
634
I
I
ISDN PC Development System
•
The B channels are used for end-to-end circuit switched digital connections between communicating stations. The D channel is used for transferring signaling information via CCITT
(0 series) and switch specific signaling protocols.
These protocols can be viewed in terms of the Open Systems Interconnection (OSI) model
of the International Standards Organisation, as shown in figure 5.
The three lowest layers of the OSI model are the services provided by the network (in this
case, the ISDN) for the transfer of information between the end user systems.
•
Each layer communicates with a peer layer via a Peer-to-Peer Protocol transmitted over
the physical link (L 1).
•
Each layer interfaces only with the layer immediately above and immediately below it
via a Service Access POint, e. g. L1- L2- L3.
•
The communication between two adjacent layers is done by the use of a set of Service
Primitives, e. g. DL-EST-RO data link establish request (L3 --c> L2) and DL-EST-IN data
link establish indication (L2 --c> L3).
Figure 5
Layered ISDN Protocol Structure according to the Open Systems Interconnection Model
Data Sourc! I Destination
Network
l7
Application layer
1-----------
Application
l6
Presentation layer
1-----------
Presentation
lS
Session layer
l4
Transport layer
.. _
-.-!'e~-
to. - Peer Protocol _ _ ..
Network layer
l2
Data link layer
l1
Physical layer·
..
- ...
---------,....--
,....--
l3
Data Source I Destination
-- ...
Network
Node
Siemens Components, Inc.
Network
Node
635
Session
Transport
Network
Data link
Physical
Services
}N"W'
"
ISDN PC Development System
The relationship of the Siemens ISDN PC Board and the associated software to the layered
communication model is depicted in figure 6.
Figure 6
I
I
--+-----I}
r-f------t----""I}
_L_3
L2
ICC,ISAC-S
S8C, 18C, IEC,
ACFA,IPAT
L1
PC
lOS
l) ~~~wl;r~Nplus
Mainboard Firmware
---~~~~~~~~~~
LAPD
Layer-3 Call Control
Link Access Procedure for the 0 channel
ICC
ISACTM-S
ISDN Communication Controller PEB 2070
ISDN Subscriber Access Controller for the S interface PEB 2085
L3CC
SBC
= S Bus Interface Circuit PEB 2080
IBC
=
IEC
ISDN Echo Cancellation Circuit PEB 2090
Advanced CMOS Frame Aligner PEB 2035
= ISDN Primary Access Transceiver PEB 2235
ACFA
IPATTM
ISDN Burst Transceiver Circuit PEB 2095
The advanced Siemens ISDN devices offer the PC the physical access to the Band 0 channels, e.g. the S Bus Interface Circuit (SBC: PEB 2080) orthe ISDN Primary Access Transceiver
(IPAT: PEB 2235) and the Adwlnced CMOS Frame Aligner (ACFA: PEB 2035). As shown in
figure· 6 part of the layer 2 is handled by the hardware. Specifically, the ISDN Communication
Controller (ICC:PEB 2(70) and the ISDN Subscriber Access Controller (ISAC-S: PEB 2085)
offer efficient support for the handling of the link access protocol (auto-mode).
Siemens Components, Inc.
636
ISDN PC Development System
The Mainboard Firmware (MF) provides the functions necessary to drive the user specific
hardware on the board.
The ISDN Operational Software (IDS) implements the layer-2 Link Access Protocol for the
D channel (LAPD) and the layer-3 call control functions. It can be run either on the PC or
downloaded and run on the SIPB 5000.
Figure 7 shows in the general SIPB structure.
Messages are transferred between the mainboard firmware and the IDS via a 16 byte mailbox. 8 bytes are used for commands from the IDS to the MF and 8 bytes for responses from
the MF to the IDS.
When the IDS is running on the PC, the host mailbox is used for the commands/responsed
to the mainboard firmware. When running on the SIPB 5000, the IDS mailbox is used for the
commands/responses to the MF and the host mailbox is used for controlling functions,
such as execution start/stop or upper layer services running on the PC.
Figure 7
General SIPB Software Structure
r ---------,
---( L3)
I
I
L2
I
----t
I
I
I
I
EB
ISDN PC User Board
ISDN
Operational
Software
PC
I
I
I
IL
C lOS Mailbox
On Board
RAM
L...-
MainBoard
Firmware
80188
Host Application
___
---- 1
I
CHost Mailbox
I
Dual Port
RAM
I
I
_ _ _ _ _ _ _
&
--..J
Siemens ISDN Components
I
L_______________ I
Siemens Components, Inc.
~
637
ISDN PC Development System
3.2 Mainboard Firmware
The firmware is contained in a part of a 128 Kbyte (or 64 Kbyte) EPROM on the SIPB 5000
mainboard. It includes an interrupt handler with dedicated interrupt service routines, a
memory management for data, drivers for the Siemens ISDN devices and information tables
to keep track of the hardware configuration. In addition, a command/response handler forms
the interface to the PC and lOS command/response mailboxes. These serve as a communication interface between the firmware and the application software on PC, and between the
firmware and the downloaded protocol software (lOS), making the lOS independent of the
hardware. Refer to figure 8.
Figure 8
Mainboard Firmware Architecture
IOS
Host Application
Menu Software
lOS on PC
Sof tware
(
-
dJ
~
lOS
Mail box
Mailbox
-,..-
-:--
FIRMWARE
'/
~
~
'/ /
'/
'/,
'////
I
'/
'//
'//
'////////// '//
'///////-j
~
Command - Response Handler
~
~
'V
~
rv
r
V
MMU
Low
Level
Device
Drivers
f----'--
INFO TABLES
I---
INTERRUPT
SERVER
~
/
~
~
~
~
~
~
~
~
~
~
~
~
~
v~
~
~////////
~
/
////////////,
//
/
/
/
Siemens ISDN Components
Siemens Components, Inc.
638
/////////////, //////.
ISDN PC Development System
3.3 ISDN Operational Software (lOS)
The ISDN Operational Software (lOS) contains:
•
a complete protocol software for the Link Access Procedure in the D channel LAPD
according to CCITT and the switch specific requirements
•
and. optionally. Layer-3 Basic Voice and Data Service Call Control Software according to
CCITT and the Switch Specific Requirements (SIEMENS EWSD. AT & T 5ESS ...).
The portability is ensured by a clear interface to layer 1 (and to the layers above lOS) via
service primitives that are transferred via the lOS mailbox (figure 7).
The lOS has a highly modular structure. As shown in figure 9, it consists of four blocks:
Figure 9
General lOS Architecture
I
L_-T-_J
I
I
lOS
IMMU
I
Layer 3
SOL Level
IPP
--
"LAPO"
IP(S
SOL Level
_
IM(
..
lOS Mailbox
Siemens Components. Inc.
639
ISDN PC Development System
•
lOS Protocol Part (IPP) with layer 2 and layer 3
The layer 2 is composed of five subblocks (called processes):
- The Multiple Frame Control (MFC)
process is responsible for acknowledged information transfer according to the 'Multiple
Frame Operation' specified in the CCID recommendations
- The Unacknowledged Information Transfer Control (UTC)
process for handling the transfer of unnumbered information (UI) frames in case of
link establishment from network side (SETUP UI - Frame)
- The TEl Assign Control (TAC)
process responsible for the automatic or non-automatic terminal endpoint identifier
value aSSignment
- The Physical Link Control (PLC)
responsible for the supervision and control of layer 1
- The Error Control (ERC)
process to support user programming for error processing and statistical functions.
Similary, the layer 3 consists of four processes:
- Call Controll (CC1)
process to execute call control transaction with the exchange (switch specific) and
interpret message types of the layer-3 call control frames
- Layer-3 Management (L3M) process
- Terminal 1 (TM1)
process which supervises and controls the state of the terminal
- Layer-3 Error Control (L3-ERC) process.
•
lOS Mailbox Control (IMC) block which builds the general interface of the lOS to the
outside environment
•
lOS Memory Management Unit (IMMU) is responsible of memory allocation and de-allo-
cation within the lOS
•
lOS Process Control System (I PeS) controls all processing within lOS through a task
scheduler and a task queue.
Siemens Components, Inc.
640
ISDN PC Development System
The IDS is written in C language and is available in different packages:
•
Full layer 2 for Terminal Equipment (TE)
•
Full layer 2 plus layer 3 Basic Voice and Data Service (TE) call control software (e.g. for
interaction with Siemens, AT & T, or Northern Telecom switches).
•
Network Termination Simulator (NT-5)
Software for layers 2 and 3 corresponding to the TE packages.
The scope of the IDS is summarized in figure 10. The NT-S version of the IDS provides a
user with a tool test user defined layer-2 and layer-3 software by setting up a voice/data
link between two ISDN PC Boards, as shown in figure 10c. For more details, refer to
chapter 4.
Figure 10
Scope of Application of the 105
User
Network
0...--___-,
rl---------------------~~~
u------------------ID
SIPB
ISDN Interface (Basic/Primary Access)
__
~;i~
JF?¥\bd
(a)
CD
ISDN
Protocol
Tester
18 [2g1
Switch e. g.
Siemens EWSD
AT & TSESS
1.--_ _ _..... NT OMS 100
.
SIP'Ir---I-O-S(-T-j-""
T- S
X
( b)
®r-----.........
SlP'i
JOSIT~q---------------p
~
~
(e)
TE =Terminal Equipment
Siemens Components, Inc.
;'IN'-SI I"-S
641
Network
Termination
Simulation
SIPB
I
ISDN PC Development System
3.4 ISDN Menu Software (MS)
The ISDN Menu Software (MS) is a user-friendly software package that enables the user
to program and evaluate the Siemens devices on the user board. In order to run the menu
software, the customer needs a SIPS 5000 plus the applicable modules.
The interface to the user is window-driven. Help functions can be called for information on
the hardware so that a novice can quickly get acquainted with the. functions of the registers
on the hardware modules, and test them. No special boot-up procedure is required for the
different configurations as the firmware determines the hardware configuration at power-up
and the menu software adjusts accordingly.
The menu software communicates with the firmware via the host mailbox (see figure 11).
To guide the user, a list of current instruction options constantly appears on the bottom line.
Figure 11
PC
Menu Software
--
_.- r - -ISDN
PC User Board
I
I
I
- - - - - - - - - - --,
Host Mailbox
I
I
I
I
Main board Firmware
(C
I
I
I R)
!
I
I
~
I
I
I
I
I
I
I
I
I
I
I
Hardware
I
Siemens ISDN Components
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JI
Siemens Components, Inc.
642
ISDN PC Development System
Track files of all user register accesses are created, which can be saved and edited (if
required) using the track window or a standard text editor, and re-run later.
These and other advanced features make the menu software an indispensable tool for
anyone wishing to save time when evaluating, programming, and debugging ISDN hardware.
Because the menu software obtains the register information from the firmware this package
will support both current and future Siemens devices.
4
Siemens ISDN Software Development and Evaluation System (SIDES)
Based on the general IDS architecture, a user is able to design his own ISDN protocol software by following the development steps listed below:
@
protocol description (4.1)
G)
static testing (4.2)
® dynamic testing (4.3)
@
downloading on user hardware (4.4)
® final testing in real environment
The Siemens ISDN Software Development and Evaluation System (SIDES), described in
the following sections, will accelerate the implementation of software.
4.1 Protocol Development Using the Program Coding Tools (PCT)
The general idea of the Program Coding Tools (PeT) is to allow the user to specify a protocol
in a simple form similar to the CCITT functional Specification and Description Language
(SDL). This can be done on an IBM PC (AT, XT or compatible) with any standard text editor,
as illustrated in figure 12.
It is important to take a structured approach when designing ISDN protocol software.
In such an approach the protocol is described as a combination of interacting processes.
This approach is taken further in that each process is described as a combination of states.
Siemens Components, Inc.
643
I
ISDN PC Development System
Transitions can be defined between the states. Finally messages are used for communication
between the processes. The PCT implementation of protocol software is based on the use
of a specially tailored task scheduler and message passing system (namely, the lOS Process
Control System IPCS, cf. section 3.3) which renders the processes independent of one
another, testable and easily modifiable.
The above protocol description elements are entered by the protocol designer in the form
of text files with a simple syntax. The text input files (one per process) are then automatically
translated by the PCTs into 'C' source code files.
For documentation and debugging purposes an additional graphic tool generates SOL
drawings in a format compatible with Ventura Publisher® and AutoCAO®. They enable the
user to verify immediately that the protocol behaves as it was intended to do.
The files can be linked together with object files (figure 12), which results in executable
code for the purpose of:
•
static test of the protocol behaviour on PC (IDS with STEP.LlB)
•
dynamic test of the protocol behaviour on PC (IDS with OYRECT.LlB)
•
downloading and execution on Siemens ISDN PC user board (IDS linked with CRTO.OBJ).
Figure 12
Program
Coding Tools
MS DOS 3.2
CD
STEP. LIB
r---- ----,
DYRECT. LIB
r---- ----,
r----
CRTO OBJ
----,
, Operational Software : : Operational Software : 'Operational Software I
Dynamic Test
I : for Downloading on Board
:L. for
Static Test
__________
.JI IL for
__________ ...J L _________ -'
l
Siemens Components, Inc.
644
ISDN PC Development System
4.2 Static Test Using the Static Test Tool for Protocol Software (STEP)
The Static Test Tool allows to test complete protocol behaviour in single step mode independent of any ISDN hardware.
The user's test interface communicates with the lOS over the lOS mailbox (figure 13, in this
case in PC-RAM).
Figure 13
Static Protocol Test on PC
PC
User Interface
,
I
I
I
I
I
IDS
I
P
C
S
lnterface
STEP
I
(C
I R)
I
IDS Mailbox
Thus, the user is able to send stimuli to the lOS (service primitives from the layer above or
below lOS) via the STEP user interface and check if the lOS reacts as expected. If not, the
user may examine the current states of the processes or the contents of the lOS task queue
in IPCS via an additional interface.
All interactions through the lOS mailbox are recorded in an 'Echo' and a 'Logging' file. After
the user has modified his protocol using the PCT, he may re-run the same test using the
'Echo' file. 'Echo' and 'Logging' files are in standard ASCII format.
Siemens Components, Inc.
645
ISDN PC Development System
4.3 Dynamic Test Using the Dynamic Real-Time Communication Tester (DYRECT)
In the next step the same protocol can be combined with a test environment which allows
to run the IDS inside the PC and use in real-time the functions of the ISDN PC Board via the
host mailbox (figure 14). As in the static case, the user is able to send stimuli (such as
layer-3-to-layer-2 commands if layer 3 is not included in IDS) to the IDS via the mailbox.
All interactions via the host mailbox are visible on screen (if desired). All the details, including
time stamps, are stored in a file and can be examined afterwards with a special screening
tool (Screening Tool for Report files, STORY).
This test facility gives the opportunity to test the software in a real system environment (e.g.
switch, or a network termination simulator with IDS available from Siemens, cf. section 3.3)
by examining the debugging information contained in the report file. As a result, in most
cases an expensive protocol analyzer is not necessary.
Figure 14
Dynamic Protocol Test on PC
User Interface
ISDN PC User Board
I
lOS
•
OYRECT
rl
Il
1 1
(c
IR
lOS Mailbox
1 IL
Host Mail box
I
l
Siemens Components, Inc.
Main board Firmware
~
Hardware
646
C
I R)
ISDN PC Development System
4.4 Downloaded 105 on SIPB
In this case, both the lOS mailbox and the host mailbox are located on the SIPS (figure 15).
Again, the host mailbox serves as the interface between the higher layers (,Host Application')
and the lOS protocol layer. The execution of the downloaded lOS is started and controlled
by primitives (e.g. suspend, continue ...) sent from the PC via the host mailbox. These primitives are recognized and delivered to the lOS by the C/R handler in the firmware.
The downloaded ISDN operational software can be tested . by using an SIPS 5000 with a
specially tailored NT-S version of lOS as counterpart as well as with a protocol analyzer
(e.g. Siemens K1195) and, finally, against an ISDN switching network.
Figure 15
Communication between 105, Firmware and PC
r------------,
ISDN PC User Board
ISDN
Operational
Software
lOS
(
Mail box
C
~
I
I
IL
PC
Host Application
_ _ _ _ I--+ _ _ _ _ -,
IR
Host
Mail box
On Board
RAM
Main
Board
Firmware
I
I
80188
Dual Port
RAM
Command I Response Handler
I
-----------------------~
&
Siemens ISDN Components
L _____________________
Siemens Components, Inc.
647
I
I
I
I
I
I
I
~
I
ISDN PC Development System
The Siemens ISDN Software Development and Evaluation System (SIDES is not only a
consistent set of tools, but represents a complete methodology for the implementation of
ISDN protocol software (figure 16). Use of SIDES considerably reduces software design
cycles. As a consequence, it entails a major reduction (up to 80 %) in overall R&D costs.
Figure 16
Development Strategy for ISDN Operational Software
lOS Development
(PCT)
Static Test of lOS
(STEP)
1-
l. Dynamic Test of lOS
( DYRECTl
I
II. (STORY)
Integration of lOS
in
User Hardware
Siemens Components, Inc.
648
ISDN PC Development System
5
Hard- and Software Packages
5.1 Hardware Sets
The various hardware sets and modules which are offered are listed below:
Basic Rate Configuration
Primary Rate Configuration
S-Interface Kit
S-Interface Terminal Equipment
S-Interface NT-Simulator (NT-S)
S-Interface Kit (ISAC-S)
S-Interface Terminal Equipment (ISAC-S)
S-Interface NT-Simulator (NT-S) (ISAC-S)
Uko-Interface Kit
Uko-Interface Terminal Equipment
Uko-Interface NT-Simulator (NT-S)
Upo-Interface Kit
Upo-Interface Terminal Equipment
Upo-Interface NT-Simulator (NT-S)
Primary Rate Kit
Hardware Options
Basic rate kits differ from each other only in the physical transmission module. The general
structure is shown in figure 17. These kits include hardware, firmware (on EPROM), and
menu software.
The block diagram of the primary rate kit is depicted in figure 18. This kit supports T1 and
CEPT applications and includes hardware and menu software as well as firmware on EPROM.
Siemens Components, Inc.
649
I
ISDN PC Development System
Figure 17
Configurations Supporting S-. UkO-' UpO-lnterfaces
~
I~~
TE KIT
NTIS KIT
Interface KIT
Basic Rate KIT
Figure 18
Primary Rate Kit
Primary Rate Kit
(MASTER* )
Primary Rate Kit
(SLAVE * )
+
• MASTER SLAVE Configurations differ only in Jumper Settings.
(
Siemens Components, Inc.
650
Pri mary Rate Kit
ISDN PC Development System
As a particular example the configuration of an S-Interface Kit is given in figure 19 below.
Figure 19
S-Interface Kit Configuration
NT-S
TE
S- Interface KIT
Description
Part Number
Ordering Code
S-Interface Kit
2 x Mainboard SIPS
(includes Mainboard Firmware + Menu Software)
2 x S-Layer-1
Module (SSC)
2 x Layer-2
Module (ICC/HSCC)
2 x Audio Interface Module
2 x Telephone Module
(SICOFI®)
(Optional telephone casing may be requested)
1 x Timing Module
SIPS 7030
Q67100-H8652
Siemens Components, Inc.
651
SIPS 5110
SIPS 5120
SIPS 5130
SIPS 5131
SIPS 5310
ISDN PC Development $ystem
5.2 Software Kits
The lOS is available in source and/or object code. The code for L3 consists of call control
software for basic voice and data services.
Table 1
Protocol Software Packages
Kit
Layer 2
Layer 213
TE
according to CCITI,
AT&T
according to CCITI,
AT&T
NT-S
according to CCITI,
AT&T
according to CCITI,
AT&T
Interface
i.e. TE& NT-S
i.e. TE&NT-S
The SIDES is available in object code. The program BOARD.EXE is used to verify the
firmware and lOS when it is downloaded to the SIPB.
Several possible packages are shown in table 2.
Table 2
Packages
Name
Single
BOARD.EXE
incl. BYT files
STEP
Library and EXE files
DYRECT/STORY
SITEST
PCT
A)
*) SITEST = STEP + DYRECT / STORY + BOARD.EXE
~) Incl. IPCS, C-Source Code Generator and Documentation Generator
Siemens Components, Inc.
652
ISDN PC Development System
5.3 Applications
The main applications are again summarized in table 3. This table also reflects the normal
steps of development, beginning with hardware evaluation and ending in complete user
system with adapted software.
Table 3
SIPS - lOS - SIDES Application Overview
1.
2.
ISDN development
platform including a
coprocessor system
Access to
all registers
Clear functional
interface to user
developed protocol
SW.
B
Functional unit,
with specific
layer-2 & -3 SW.
~
Allows
customer to run
various
applications
for voice
and data.
Control via
terminal
or host-mailbox
programming
SW
B
~
L3
4.
3.
Allows to establish a
voice and I or data
communication to a
peer station.
B
I~ul
B
~
~
I
SITEST
I
Simulation
and analysation
of protocol
Control of
MFand lOS
on board
Enables the
customer to
modify and
adapt the
delivered
SW packages to this
own
requirements.
B
~
SW
B
G
~
ISI1EST I
EJ
Siemens Components, Inc.
653
I
ISDN PC Development System
6
Literature References, Abbreviations and Definitions
Literature References
a) General Literature
CCITT Recommendation
CCITT Recommendation
CCITT Recommendation
0.920/1
1.440/1
0.930/1
b) Literature from Siemens
PCT Demo Guideline Rev. 1.0
SIPS C / R-Mailbox Interface Specification, Volume 3,2.89
SIPS User Manual, Volume 2, 4.89
SITEST Manual Rev. 1.1
PCT User Manual Rev. 2.1
lOS LAPD Protocol Reference Spec. Rev. 1.0
IPCS Technical Description Rev. 1.0
SIPS Firmware Manual, Volume 5; 1.89
Abbreviations, Definitions
LAPD
lOS
10M®
IPCS
SDL
SIPS
STEP
DYRECT
STORY
SITEST
SIDES
PCT
=
=
=
=
=
=
Link Access Procedure on the D channel
ISDN Operational Software
ISDN Oriented Modular
lOS Process Control System
Functional Specification and Description Language
Siemens'lSDN PC User Soard
Static Test Tool for Protocol software
Dynamic Real-Time Communication Tester
Screening Tool for Report Files
Siemens ISDN Protocol Software Test Tools
Siemens ISDN Software Development and Evaluation System
Program Coding Tools
Siemens Components, Inc.
654
Data Communication ICs
I
Data Communication ICs
I
Siemens Components, Inc.
657
SIEMENS
High-Level Serial
Communications Controller (HSCC)
Type
Ordering Code
SAB 82520-C
Q67100-H8830
SAB 82520
SAF82520
Package
SAB 82520, a High-level Serial Communications Controller (HSCC), has been designed to
free the user from tasks occuring in communication via networks and trunk lines.
SAB 82520 is an X.25 LAPB/LAPD controller which, to a large degree performs communicatiofls procedures independently of CPU support.
A parallel processor bus constitutes the j.l.C system. The communications interface is
implemented by two full-duplex HDLC channels, which can be operated independently
from one another. The HSCC is connected to the transmission line via additional line drivers
or modems. External logic is cost-effective because clock recovery can be performed by
an on-chip oscillator, DPLL circuits and a programmable baud rate generator.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Two independent HDLC channels
Implementation of X.25 LAPB/LAPD protocol
Programmable timeout and retry conditions
FIFO buffers for efficient transfer of data packets
Digital phase-locked loop for each channel
Baudrate generator and oscillator
Different modes for clock recovery and data encoding
High-speed data rate (up to 4 MHz)
Supports bus configuration by collision resolution
Telecom-specific features programmable
8-bit parallelj.l.P interface
Advanced CMOS technology
Low power consumption; active: 25 mW at 4 MHz
standby: 3 mW
• SAB 82520: operating temperature 0 to 70°C
• SAF 82520: operating temperature -40 to 85°C
658
SAB 82520
SAF82520
Logic Symbol
}serial Data
}serial Clock
Address!
Data Bus
}
CTSA!CxDA
Channel A
Modem Control
Bus Access
}serial Data
}serial Clock
Processor
Control
}
+5 V GND
Siemens Components, Inc.
RES
659
Modem Control
Bus Access
Channel B
SAB 82520
SAF 82520
Pin Configurations
P-DIP; C-DIP
(top view)
AD 4
AD 3
AD 5
AD 2
AD 6
AD 1
AD 7
ADO
RTSA
RD
CTSA/(xDA
WR
RxDA
Voo
TxDA
Rx (lK A
TxDB
Rx(lKB
RxDB
Tx(lK A
TxCLKB
CTSB/(xDB
(S
RTSB
RES
ALE
Vss
INT
PL-CC
AD7
ADI
RTSA
ADO
R5
CTSAlCxDA
RxDA
TxDA
WR
Vee
TxDB
RxClKA
RxDB
Rx ClK B
CTSB/(x[8
TxClKA
RTSB
TxCLKB
Siemens Components, Inc.
660
SAB 82520
SAF 82520
Pin Definitions and Functions
Pin No.
Symbol
Input (I)
Functions
Output (0)
25
26
27
28
1
2
3
4
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
lID
lID
lID
lID
lID
lID
lID
lID
Address Data Bus
The multiplexed address data bus transfers data and
commands between the ~p system and the HSCC.
5
12
RTSA
RTSB
0
0
Request to Send
When the RTS bit in MODE is set, the RTS signal goes
low. When the RTS bit is reset, the signal goes high
of the trans'mitter has finished and there is no further
request for a transmission. In a bus configuration,
RTS goes low during the actual transmission of a
frame shifted by a clock period, excluding collision
bits.
6
11
CTSAlCxDA I
CTSB/CxDB I
Clear to SendlCollision Data
A low on the inputs enables the respective transmitter.
If the transmitters are always enabled, CTS should be
connected to Vss. In a bus configuration the external
serial bus must be connected to the respective C x D
pin.
7
10
RxDA
RxDB
I
I
Receive Data
These lines receive serial data at standard TIL or
CMOS levels.
8
TxDA
TxDB
0
0
Transmit Data
These lines transmit serial data at standard TIL or
CMOS levels. They can be programmed as push-pull
or open-drain outputs.
13
RES
I
RESET
A high on this input forces the HSCC into reset state.
The HSCC is in power-up mode during reset and in
power-down mode after reset. The minimum pulse
length is 1.8 ~s.
14
Vss
15
INT
9
Ground (0 V)
0
Siemens Components, Inc.
Interrupt Request
The signal is activated when the HSCC requests an
interrupt. It is an open-drain output.
661
I
SAB 82520
SAF82520
Pin Definitions and Functions (cont'd)
Pin No.
Symbol
Input (I)
Functions
Output (0)
16
ALE
I
Address Latch Enable
A high on this line indicates an address on the external
address data bus, selecting one of the HSCC internal
sources or destinations
17
CS
I
Chip Select
A low on this signal selects the HSCC for a read/write
operation.
18
19
TxClKB
TxClKA
I/O
I/O
Transmit Clock
20
21
RxClKB
RxClKA
I
I
22
Voo
23
WR
These pins can be programmed in several different
modes of operation. T x ClK may supply the transmit
clock for the respective channel, a receive strobe
signal (T x ClKA) and a transmit strobe signal (T x ClKS)
or a frame synchronization signal (T x ClKA, clock
mode 5). Programmed as outputs, TxClK supply the
transmit clock of the respective channel or a tristate
control signal, indicating the· programmed transmit
time slot (T x ClKB, clock mode 5).
Receive Clock
These pins can be programmed in several different
modes of operation. In each channel R x CK may supply
the receive clock, the receive and transmit clock, the
clock for the baud rate generator or the clock for the
DPlL. They also can be programmed for use as a
crystal oscillator.
Power
+5 V power supply.
I
Write
This signal indicates a write operation.
24
RD
I
Read
This signal indicates a read operation.
Siemens Components, Inc.
662
SAB82520
SAF 82520
Applications
Figure1a
Point-to-Point Configuration
r----------,
r-----------,
I
I
I
I
Combined
Station
II
Combined
Station
I
I
I
I
i
CPU
CPU
IL _________ -lI
L _________ ..J
I
I
Figure1b
Point-to-Multipoint Configuration
I
Figure 1c
Multimaster Configuration
I
I
I
I
-----4~I----...~1 Station n
IStatiOn(n-lll"'"..
Siemens Components, Inc.
I
663
SAB 82520
SAF 82520
Description
In a point-to-multipointor in a multimaster configuration the HSCC can be used as a central
station (master) or a peripheral station. As a peripheral station tne HSCC can initiate the
transmission of data. An internal function block provides for collision avoidance, which may
occur if several stations start the transmitting simultaneously.
Furthermore, in a special operating mode the HSCC can transmit or receive data packets in
programmable time slots; this makes SAB 82520 especially suitable for applications in
systems designed for packet switching. In this application in particular, the integrated
collision-resolution mechanism provides optimal utilization of system-internal PCM paths.
Characteristics
A number of characteristics which distinguish the SAB 82520 from conventional lowlevel
HOLC devices are described below.
Support of Layer-2 Functions by HSCC
"Low-level" HOLC devices usually support various of protocols. When applying the HOLC
protocol mainly bit-oriented functions such as bit stuffing, CRC check, flag and address
recognition are performed. SAB 82520 has been especially designed to support the ISO
HOLe protocol. In addition to the bit-oriented functions, the device provides a high degree
of procedural support and evaluates the layer-2 control field. The communications procedures are processed between the communications controllers and not between the processors. As a result procedure handshaking is no longer necessary. The processor is informed
of the status of the procedure however. The dynamic load of the processor is thus largely
reduced. To maintain cost effectiveness and flexibility, not all layer-2 functions have been
implemented as hardware. Instead, functions such as connection setup/connection cleardown and error recovery in case of protocol errors are performed by the processor software.
Operating Modes
The distribution of functions between HSCC and CPU applies to the auto mode. As a prerequiste for this operating mode, the window size between transmitted and acknowledged
frames has to be limited to 1. Alternatively, transparent modes can be applied, the data
field as well as the layer-2 headers are forwarded directly to the CPU. The reception and
transmission of messages is fully controlled by the CPU. This operating mode is selected
when the component is used as a central station (master) or if the accepted distance
between transmitted and received frames (window size) is larger than 1.
Furthermore, there is a possibility to bypass the receiver and to get access to the received
'
data directly.
FIFO Buffers for Efficient Transfer of Data Packets
Another feature of the SAB 82520 can be seen in the buffers that are used for temporary
storage of data packets which are transferred between the serial communication interface
and the parallel system bus. Oue to the overlapping input/output operation (dual-port
behavior), the maximum length of the data packets is not limited by the buffer size. The
dynamic load of the processor is reduced by transferring the data packets block by block.
Siemens Components, Inc.
664
SAB 82520
SAF 82520
One FIFO buffer with a total capacity of 64 bytes per direction and channel is divided into
two memory pools of 32 bytes each. When a pool is filled (receive mode) or emptied (transmit mode) via the serial interface, the processor is prompted by interrupt to read or write
this pool. Subsequently the second pool is filled or emptied. During this time the CPU can
transfer the first block thereby ensuring availability of the pool. With a serial transfer rate
of 1 Mbitls the reaction time between the first prompting and data overflow with loss of data
is 256 Ils. In addition, the transmit FIFO provides the flexibility for temporarily storing blocks
of various lengths, which can be received in rapid succession. The FIFO will also store a
data packet when a preceding short data packet stored in the memory has not yet been
read by the processor.
The HSCC is especially suitable for cost-critical applications with Single chip processors
due to its memory organization and on-chip memory control.
Move string commands are available for high-performance applications where fast data
rates at the communication interface and a high level of processor performance are required.
The FIFO can then be addressed by the automatically incremented address.
Serial Interface
The serial interface provides two independent, high-performance communication interfaces.
As already mentioned, the ISO HDLC layer-2 protocol is supported by the HSCC. In addition,
layer-1 functions are provided by means of on-chip circuits. Eight different operating modes
can be selected to clock the serial data stream.
•
During the self-clocked operating mode, the transfer clock is recovered from the received
data stream by means of an external crystal only. On-chip oscillator and DPLL circuits
sample the received bit stream and adjust the clock edge to the center of the data bit.
•
The bit stream is synchronized in the externally clocked operation mode by external
clock signals. One the whole, 4 different clock Signals separated by direction and channel,
can be forwarded.
In addition to the data clock, an externally supplied strobe signal can be applied to determine the time period during which data is to be received or transmitted. Using another
operating mode, a time slot (up to 64 bit) can be programmed for transmitting data and
another time slot for receiving data. One time slot consists of eight clock cycles.
•
With the point-to-multipoint configuration, comprising a central station (master) and
several peripheral stations (slaves), data transmission can be initiated by a slave. If several
stations (slaves) transmit data simultaneously, the bus is assigned to one station by a
collision-resolution procedure implemented by the HSCC. The bus assignment functions
in accordance with the principle applied with the ISDN S bus. Its collision-resolution
procedure helps to ensure a sharing of priority among the slave stations.
•
The maximum data rate of the externally clocked operating mode is 4 Mbits per second.
In the self-clocked operating mode with an external reference clock or the crystal oscillator, the maximum clock rate is 12 MHz, the maximum data rate will be 750 kbitls.
Siemens Components, Inc.
665
I
SAB 82520
SAF 82520
Description of Block Diagram
The chip contains a serial interface for two channels, including a DPLL and collision-detection
block, a data-link controller and the FIFO buffers. The IJ.P interface, including the status and
command registers, is used for both channels. These functions are implemented in 2 IJ.m
CMOS technology.
Block Diagram
Channel A
Mode
Command
Status
•
ir''''
.:;J
.-
8·Bit
Address IData
Control
Signals
{
"
Bus
Interface
Unit
LAP
Controller
Controller
Lr
Transmit
FIFO
~
".Receive
FIFO
+
Data
Link
Controller
K=
...
Ii--
Time Slot
Assignment
Sp
Register
r
I
Channel B
Mode
Command
Status
Siemens Components, Inc.
j
Receive
FIFO
Transmit
FIFO
lb,..,
~
J=:::J
Controller
666
RxDA
Decoder
Collision
Detection
DPLL A
------
J-------WClock
Control
DPLL B
Data
Link
Controller
,
LAP
Controller
TxDA
RTSA
(TSAlCxDA
*
RxCLK A
RxCLK B
TxCLK A
TxCLK B
[TSB/CxDB
Decoder
Collision
Detection
RTSB
TxDB
RxDB
SAB 82520
SAF 82520
Absolute Maximum Ratings
Limit Values
Parameter
Storage temperature
Operating temperature:
Operating temperature:
SAB 82520
SAF 82520
Voltage at any pin vs. ground
Symbol
min.
Tstg
TA
TA
Vs
max.
Unit
-65
125
°C
0
-40
70
85
°C
°C
-0.4
Vee +0.4
V
DC Characteristics
SAB 82520: TA = 0 to 70 o G; Vee = 5 V ± 10%; GND = 0 V
SAF 82520: TA = -40 to 85°G; Vee = 5 V ± 5%; GND = 0 V
Limit Values
Parameter
Symbol
min.
L-input voltage
H-input voltage
lIil
lIiH
Vss-O.4
L-output voltage
H-output voltage
VOL
VOH
Input leakage current
Output leakage current
~l
Vee supply current
p. d.
p. u.
Icc
IOl
typo
2.4
Vee-0.5
Unit
0.8
Vee+0.4
V
V
0.45
V
V
V
IOl = 2 rnA
IOH =-400 f..LA
IOH =-100 f..LA
10
10
f..LA
f..LA
lIiN = Vee to 0 V
VOUT= Vee to 0 V
1.8
7
rnA
rnA
Vee
-10
-10
0.5
5
Icc
max.
Test Conditions
Vee = 5 V,
C p = 4 MHz
Inputs at Vss/Vee
No output loads
Capacitance
TA=25°C; Vee=GND=OV
Limit Values
Parameter
Input capacitance
fe= 1 MHz
InpuVoutput capacitance
Output capacitance
unmeasured pins
returned to GND
Siemens Components, Inc.
typo
max.
Unit
CIN
5
10
pF
CliO
10
20
pF
8
15
pF
Symbol
min.
COUT
667
I
8AB8252O
8AF82520
IJ.P Interface Timing
Read Cycle
AlE~~~-
__________________
AD
-J~~
.I1'---~'-----
_ _ _ _ _ _ _ _ _ _ _ __ _
- - -- - - --- -- - -- - ----
Write Cycle
-------------~;~~tf--'~-----~-] /
WR
AD ______________
Data
____________. Data
\rnA. __ _
Read Cycle
Limit Values
Parameter
Symbol
min.
Address hold after ALE
Address to ALE setup
tLA
tAL
25
20
Data delay from RD
RD pulse width
t RO
tRR
110
Output float delay
tOF
RD control interval
tRI
ALE pulse width
tAA
60
50
Parameter
Symbol
min.
WR pulse width
Data setup to WR
tww
tow
Data hold after WR
WR control interval
two
tWI
60
30
10
60
max.
Unit
ns
ns
110
ns
ns
25
ns
ns
ns
Write Cycle
Limit Values
Siemens Components, Inc.
668
max.
Unit
ns
ns
ns
ns
SAB 82520
SAF 82520
Serial Interface Timing
Bus,
---,......-----H-JI~----+_--- Timing Mode 2
Bus,
'I-r--------- Timing Mode 2
AC Characteristics
SAB 82520: TA = 0 to 70°C; Vcc = 5 V ± 10%; GND = 0 V
SAF 82520: TA = -40 to 85°C; Vcc = 5 V ± 5%; GND = 0 V
Limit Values
Parameter
_.
Symbol
min.
Receive data setup
Receive data hold
f RDS
fRDH
0
30
ns
ns
Collision data setup
Collision data hold
tCDS
tCDH
0
30
ns
ns
Transmit data delay
tXDD
20
68
ns
Request to send delay 1
Request to send delay 2
tRTD 1
tRTD 2
30
20
130
ns
ns
Clock period
tcp
240
ns
Clock period Low
Clock period High
t CPL
tCPH
90
100
ns
ns
Siemens Components, Inc.
669
max.
85
Unit
SAB 82520
SAF 82520
Clock Mode 5
RxCLK AlB _ _..J
TxCLK A _ _ _
~
____
~
_ _ _ _ _+-_.....J
TxCLK B _ _--I...
TxCLK B ----------h
Bus, Timing Mode 2
Limit Values
Parameter
max.
Symbol
min.
Unit
Sync pulse delay
tSD
30
ns
Sync pulse setup
tss
30
ns
Sync pulse width
tsw
40
Time-slot control 2 delay
Time-slot control 1 delay
tTCD 2
tReD 1
20
30
ns
95
120
ns
ns
Clock Mode 1
RxCLK AlB
TxCLK A _ _ _ _ _ _ _ _-+____
~
TxCLK B _ _ _ _ _ _ _ _ _ _ _ _ _
~
Limit Values
max.
Parameter
Symbol
min.
Receive strobe delay
Receive strobe setup
Receive strobe hold
tRSD
tRSS
tRSH
30
70
30
ns
ns
ns
Transmit strobe delay
Transmit strobe setup
Transmit strobe hold
tXSD
txss
tXSH
30
90
30
ns
ns
ns
Siemens Components, Inc.
670
Unit
SAS 82520
SAF 82520
AC Testing Input, Output Waveform
AC Testing Load Circuit
2,4
2,0"
Device
Under
Test
2,0
Test POints/
0,8 /
"0.8
0,45
ACTesting
Inputs are driven at 2.4 V for logic "1" and 0.45 V for logic "0".
Timing measurements are made at 2.0 V for logic "1" and at 0.8 V for logic "0".
Siemens Components, Inc.
671
SIEMENS
High-Level Serial
Communication Controller Extended
(HSCX)
Preliminary Data
SAB 82525
SAB 82526
SAF82525
SAF82526
CMOSIC
The SAB 82525 is a High-Level Serial Communications Controller compatible to the SAB 82520
HSCC with extended features and functionality (HSCX).
The SAB 82526 is pin and software compatible to the SAB 82525, realizing one HDLC
channel (channel B).
The HSCX has been designed to implement high-speed communication links using HDLC
protocols and to reduce the hardware and software overhead needed for serial synchronous
communications.
Due to its 8-bits demultiplexed adaptive bus interface it fits perfectly into every SIEMENS/
INTEL or Motorola 8- or 16-bit microcontroller or microprocessor system. The data throughput
from/to system memory is optimized transfering blocks of data (usually 32 bytes) by means
of DMA or interrupt request. Together with the storing capacity of up to 64 bytes. in on- chip
FIFO's, the serial interfaces are effectively decoupled from the system bus which drastically
reduces the dynamic load and reaction time of the CPU.
The HSCX directly supports the X.25 LAP B, the ISDN LAP p, and SDLC (normal response
mode) protocols and is capable of handling a large set of layer-2 protocol functions
independently from the host processor.
Furthermore, the HSCX opens a wide area for applications which use time division multiplex
methods (e.g. time-slot oriented PCM systems, systems designed for packet switching,
ISDN applications) by its programmable telecom-specific features.
The HSCX is fabricated using SIEMENS advanced ACMOS 3 technology and available in
a PL-CC-44 pin package.
672
SAB 82525
SAB 82526
SAF82525
SAF 82526
Features
Serial Interface
•
•
•
•
•
•
•
•
Two independent full-duplex HDLC channels (SAB 82526: one channel)
On chip clock generation or external clock source
On chip DPLL for clock recovery for each channel
Two independent baudrategenerators (SAB 82526: one baud rate generator)
Independent time-slot assignment for each channel with programmable time-slot length
(1 - 256 bit)
Different modes of data encoding
Modem control lines (RTS, CTS, CD)
Support of bus configuration by collision resolution
Programmable bit inversion
Transparent receive/transmit of data bytes without HDLC framing
Continuous transmission of 1 to 32 bytes possible
Data rate up to 4 Mbitls
Protocol Support
•
•
•
•
•
•
Various types of protocol support depending on operating mode
Auto mode
- Non auto mode
- Transparent mode
Handling of bit oriented functions in all modes
Support of LAPB/LAPD/SDLC/HDLC protocol in auto mode (1- and S-frame handling)
Modulo 8 or modulo 128 operation
Programmable timeout and retry conditions
Programmable maximum packet size checking
~p
Interface
•
•
•
•
•
64 byte FIFO's per channel and direction
Storage capacity of up to 17 short frames in receive direction
Efficient transfer of data blocks from/to system memory by DMA or interrupt request
8-bit demultiplexed or multiplexed bus interface
Intel or Motorola type MP interface
General
•
•
•
Compatible to SAB 82520 (HSCC)
Advanced CMOS technology
Low power consumption ~ active 25 mW at 4 MHz
standby 4 mW
Siemens Components, Inc.
673
SAB
SAB
SAF
SAF
82525
82526
82525
82526
The data link controller handles all functions necessary to establish and maintain an HOLC
data link, such as
Flag insertion and detection,
Bit stuffing,
CRC generation and checking,
Address field recognition.
Associated with each serial channel is a set of independent command and status registers
(SP-REG) and 64-byte deep FIFO's for transmit and receive direction.
OMA capability has been added to the HSCX by means of a 4-channel OMA interface
(SAB 82525) with one OMA request line for each transmitter and receiver of both channels.
Siemens Components, Inc.
674
SAB 82525
SAB 82526
SAF82525
SAF 82526
Pin Configurations
(top view)
PL-CC-44
6 5 4 3 2 1 44 43 42 41 40
WRIICO
o
7
ES
CTSA/CxDA
DRQRA
DRQTB
DRQRB
TxCLKA
RxCLKA
AxCLKA
RxCLKB
TxCLKB
AxCLKB
DACKA
DACKB
SAB 82525
SAF 82525
TxDB
CTSB/CxDB
RTSB
RxDB
RES
18 19 20 21 22 23 24 25 26 27 28
0
V'!..o LI"I ...j- m N . - 0 I~
~~~«««««««3
.-
......
u.J
....J
«
PL-CC-44
~
......
c
10
.
"--!
£"'-. ...0 If'I ....:t rn N
<:>
0
a::DDDDDDDD~:Z
6 543 2 1 444342 4140
WR/ICO
CS
0
N.C.
SAB 82526
SAF 82526
NL
TxDB
CTSBI CxDB
RTSB 15
RxDB
RES
N.L
DRQTB
DRQRB
N.C.
RxCLKA
AxCLKA
RxCLKB
TxCLKB
AxCLKB
N.C.
DACKB
18 19 20 21 22 23 24 25 26 27 28
-0
~~
V1...olf'l...:tmN
~ °l~
Vl««««« ««25
--~
......
UJ
....J
«
Siemens Components, Inc.
675
I
SAB 82525
SAB 82526
SAF82525
SAF 82526
Pin Definitions and Functions
Pin No.
Symbol
Input (I)
Function
Output (0)
42
43
44
1
2
3
4
5
DO
D1
D2
D3
D4
D5
D6
D7
I/O
RD/IC1
I
6
Data Bus
The data bus lines are bidirectional threestate lines
which interface with the system's data bus.
These lines carry data and command/status to and
from the HSCX.
Read, Intel bus mode, IM1 connected to low
This signal indicates a read operation. When the HSCX
is selected via CS the read signal enables the bus
drivers to put data from an internal register adressed via
AO-A6 on the data bus.
When the HSCX is selected for DMA transfers via DACK,
the RD signal enables the bus driver to put data from
the respective receive FIFO on the data bus. Inputs to
AO-A6 are ignored.
Input Control 1, Motorola bus mode IM1 connected
to high.
If Motorola bus mode has been selected this pin serves
either as
E = Enable, active high (IMO tied to low) or
DS = Data Strobe, active low (IMO tied to high)
input (depending on the selection via IMO) to control
read/write operations.
7
WR/ICO
I
Write, Intel bus mode
This signal indicates a write operation. When CS is active
the HSCX loads an internal register with data provided
via the data bus. When DACK is active for DMA transfers
the HSCX loads data from the data bus on the top of
the respective transmit FIFO.
Input Control Motorola bus mode
In Motorola bus mode, this pin serves as the RIW input
to distinguish between read or write operations.
8
CS
I
Chip Select
A low signal selects the HSCX for a read/write
operation.
Siemens Components, Inc.
676
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Pin Definitions and Functions (cont'd)
Pin No.
Symbol
Input (I)
Function
Output (0)
RXDA
RXDB
I
16
10
15
RTSA
RTSB
0
11
CTSA/
CXDA
CTSB/
CXDB
I
9
14
Receive Data (channel A/channel B)
Serial data is received on these pins at standard TIL
or CMOS levels.
Request to Send (channel Nchannel B)
When the RTS bit in the mode register is set, the RTS
signal goes low. When the RTS i reset, the signal goes
high if the transmitter has finished and there is no
further request for a transmission.
In a bus configuration, this pin can be programmed via
CCR2 to:
- go low during the actual transmission of a frame
shifted by one clock period, excluding collision bits
- go low during the reception of a data frame
- stay always high (RTS disabled).
Clear to Send (channel A/channel B)
A low on the CTS inputs enables the respective transmitter. Additionally, an interrupt may be issued if a state
transition occurs atthe CTS pin (programmable feature).
If no "Clear To Send" function is required, the CTS
inputs can be connected directly to GND.
Collision Data (channel A/channel B)
In a bus configuration, the external serial bus must be
connected to the respective CxD pin for collision detection.
12
13
TXDA
TXDB
0
17
RES
I
Transmit Data (channel Nchannel B)
Transmit data is shifted out via these pins at standard
TIL or CMOS levels. These pins can be programmed
to work either as push-pull, or open drain outputs
supporting bus configurations.
RESET
A high signal on this input forces the HSCX into the
reset state. The HSCX is in power-up mode during
reset and in power -down mode after reset. The minimum
pulse width is 1.8 ms.
Siemens Components, Inc.
677
I
SAB 82525
SAB 82526
SAF82525
SAF82526
Pin Definitions and Functions (cont'd)
Pin No.
Symbol
Input (I)
Function
Output (0)
18
IM1
I
Input Mode 1
Connecting this pin to either Vss or Voo the bus interface
can be. adapted to either SIEMENS/INTEL or Motorola
environment.
IM1 = LOW: Intel bus mode
IM1 = HIGH: Motorola bus mode
19
ALE/IMO
I
Address Latch Enable (Intel bus mode)
A high on this line indicates an address on the external
address/data bus, which will select one of the HSCX's
internal registers. The address is latched by the HSCX
with the falling edge of ALE. This allows the HSCX to be
directly connected to a CPU with multiplexed address/
data bus compatible to SAB 82520 HSCC.
The address input pins AO-A6 must be externally connected to the data bus pins (00-06 for 8-bit CPU's,
01-07 for 16-bit CPU's, i.e. multiply all internal register
addresses by 2).
Input Mode 0, Motorola bus mode
In Motorola Bus Mode, the level at this pin determines
the function of the IC1 pin (see description of pin 6).
20
Vss
I
27
26
25
24
23
22
21
AO
A1
A2
A3
A4
A5
A6
I
28
INT
0
Ground (0 V)
Address Bus
These inputs interface with seven bits of the system's
address bus to select one of the internal registers for
read or write.
They are usually connected at AO-A6 in 8-bit systems
or at A1-A7 in 16-bit systems.
Interrupt Request
The signal is activated, when the HSCX requests an
interrupt.
The CPU may determine the particular source and cause
of the interrupt by reading the HSCX's interrupt status
registers. (ISTA, EXIR).
INT is an open drain output, thus the interrupt requests
outputs of several HSCX's can be connected to one
interrupt input in a "wired-or" combination.
This pin must be connected to a pull-up resistor.
Siemens Components, Inc.
678
SAB82525
SAB 82526
SAF82525
SAF82526
Pin Definitions and Functions (cont'd)
Pin No.
Symbol
Input (I)
Function
Output (O)
30
DACKA
DACKB
I
29
DMA Acknowledge (channel A/channel B)
When low, this input signal from the DMA controller
notifies the HSCX, that the requested DMA cycle controlled via DRQxx (pins 37-40) is in progress, i.e. the
DMA controller has achieved bus mastership from the
CPU and will start data transfer cycles (either read or
write).
Together with RD, if DMA has been requested from the
receiver, or with WR, if DMA has been requested from
the transmitter, this input works like CS to enable a data
byte to be read from or written to the top of the receive
or transmit FIFO of the specified channel.
If DACKn is active, the input to pins AD-A6 is ignored
and the FIFOs are implicitly selected.
If the DACKn signals are not used, these pins must be
connected to Voo.
34
31
AxClKA
AxClKB
I
Alternative Clock (channel A/channel B)
These pins realize several input functions. Depending
on the selected clock mode, they may supply either a
- CD (= Carrier Detect) modem control or general
purpose input.
This pin can be programmed to functions as receiver
enable if the "auto start" feature is selected (CAS bit in
XBCH set). The state at this pin can be read from VSTR
register,
- or a receive strobe signal (clock mode 1)
- or a frame synchronization signal in time-slot oriented
operation mode (clock mode 5)
- or, together with RxClK, a crystal connection for
the internal oscillator (clock mode 4,6,7, AxClKA)
only).
Siemens Components, Inc.
679
I
SAB82525
SAB 82526
SAF 82525
SAF82526
Pin Definitions and Functions (cont'd)
Pin No.
Symbol
Input (I)
Function
Output (O)
36
32
TxCLKA
TxCLKB
110
Transmit Clock (channel A/channel B)
The functions of these pins depend on the programmed
clock mode, provided that the TSS bit in the CCR2
register is reset. Programmed as inputs (if the TID bit
in CCR2 is reset), they may supply either
- the transmit clock for the respective channel (clock
mode 0,2,6),
- or a transmit strobe signal (clock mode 1).
Programmed as outputs (if the TID bit in CCR2 is set),
the TxCLK pins supply either the
- transmit clock of the respective channel which is
generated either
• from the baud rate generator (clock mode 2,6; TSS
bit in CCR2 set),
• or from the DPLL circuit (clock mode 3,7),
• or from the cristal oscillator (clock mode 4)
- or a tristate control signal indicating the programmed
transmit time slot (clock mode 5).
35
33
RxCLKA
RxCLKB
I
Receive Clock (channel A/channel B)
The functions of these pins also depend on the programmed clock mode. In each channel, RxCLK may
supply either
- the receive clock (clock mode 0)
- or the receive and transmit clock (clock mode 1,5)
- or the clock for the baud rate generator (clock mode
2,3),
- or a crystal connection for the internal oscillator
(clock mode 4 6 7 RxCLKAlB together with AxCLKA)
39
37
DRQRA
DRQRB
0
DMA Request Receiver (channel A/channel B)
The receiver of the HSCX requests a DMA data transfer
by activating this line.
The DRQRn remains high as long as the receive FIFO
requires data transfers, thus always blocks of data
(32,16,8 or 4 bytes) are transfered.
DRQRn is deactivated immediately following the falling
edge of the last read cycle.
Siemens Components, Inc.
680
SAB82525
SAB82526
SAF82525
SAF82526
Pin Definitions and Functions (cont'd)
Pin No.
Symbol
Input (I)
Function
Output (0)
40
38
DRQTA
DRQTB
0
DMA Request Transmitter (channel A/channel B)
The transmitter of the HSCX requests a DMA data
transfer by activating this line.
The DRQTn remains high as long as the transmit FIFO
requires data transfers.
The amount of data bytes to be transfered from system
memory to the HSCX (= byte count) must be written
first to the XBCH, XBCL registers.
Always blocks of data (n * 32 bytes + REST, n = 0,1, ... )
are transfered till the byte count is reached.
DRQTn is deactivated immediately following the falling
edge of the last WR cycle.
41
Voo
I
Power +5 V power supply.
I
Siemens Components, Inc.
681
SAB
SAB
SAF
SAF
82525
82526
82525
82526
Block Diagram SAB 82525/SAB 82526
Channel A
AO-A6
SP - REG
LAP
Controller
Decoder
Collision
Detection
DO-D7
RD/IC1
WRIICO
IJP
Bus
Interface
RxDA
TxDA
RTSA
CTSAI
CxDA
DPLL
R.. CLKA
Clock
CS
Control
ALE/IMO
AxCLKA
TxCLKA
INT
RES
1M!
TxCLKB
DRQTA
RxCLKB
AxCLKB
DRQRA
DACKA
DMA
Interface
CTSBI
CxDB
RTSB
TxDB
RxDB
DRQTB
DRQRB
DACKB
Channel B
The HSCX SAB 82526 comprises one (channel B), the SAB 82525 two completely independent full-duplex HOLC channels (channel A and channel B), supporting various layer-1
functions by means of internal oscillator, Baud Rate Generator (BRG), Digital Phase Locked
Loop (DPLL), and Time-Slot Assignment (TSA) circuits.
Furthermore, layer-2 functions are performed by an on-chip LAP (Link Access Procedure,
e.g. LAP B or LAP 0) controller.
Siemens Components, Inc.
682
SAB 82525
SAB82526
SAF 82525
SAF 82526
System Integration
General Aspects
Figure 1 gives a general overview of the system integration of HSCX.
Figure 1
General System Integration of HSCX
"C
c:
CI
Memory
e
e0
CPU
u
III
....
::l
E
VI
t
System Bus
DRQTA. DRQRA. DACKA
DMA
Controller
DRQTB.
DRQRB. DACKs - -
HSCX
----,.;
'-._. _. _. _._. _.DATA
Seriel
Channel A
The HSCX bus interface consists of an 8-bit bidirectional data bus (DO - D7), seven address
line inputs (AO - AS), three control inputs (Fill/DS, WR/RIW, CS), one interrupt request
output (INT) and a 4-channel DMA interface (DRQTA, DRQRA, DACKA, DRQTB, DRQRB,
DACKB). Mode input pins (strapping options) allow the bus interface to be configured for
either SIEMENS/INTEL or Motorola environment.
Generally, there are two types of transfers occuring via the system bus;
command/status transfers, which are always controlled QY the CPU. The CPU sets the
operation mode (initialization), controls function sequences and gets status information
by writing or reading the HSCX's registers (via CS, WR or RD, and register address via
AO-AS).
data transfers, which are effectively performed by DMA without CPU interaction using
the HSCX's DMA interface (DMA Mode). Optionally, interrupt controlled data transfer can
be done by the CPU (interrupt mode).
Siemens Components, Inc.
683
SAB82525
SAB 82526
SAF 82525
SAF 82526
Specific Applications
HSCX with SAB 8051 Microcontroller
For cost-sensitive applications, the HSCX can be interfaced with a small SAB 8051 microcontroller system (without DMA support) very easily as shown in figure 2.
Figure 2
HSCX with 8051 CPU
+5V
SAB
8051
CPU
INTO
RO
WR
ALE
RO
WR
ALE
INT
RO
WR
ALE
CS
AB ... A15
SAB
82525
HS(X
ALA7
ADO ... A07
00... 07
IM1
LI"I
<
I
co
oCt
Although the HSCX provides a demultiplexed bus interface, it can optionally be connected
directly to the local multiplexed bus of SAB 8051 because of the internal address latch
function (via ALE, compatibility to SAB 82520 HSCC).
The address lines AO ... A6 must be wired externally to the data lines DO ... D6 (direct
connection) in this case.
Intel bus mode is selected connecting IM1 pin to low (Vss). Since data transfer is
controlled by interrupt, the DMA acknowledge inputs (DACKA, DACKB) are connected
to Voo (+5 V).
Siemens Components, Inc.
684
SAB
SAB
SAF
SAF
82525
82526
82525
82526
HSCX with SAB 80188 Microprocessor
A system with minimized additional hardware expense can be with a SAB 80188
microprocessor as shown in figure 3.
Figure 3
HSCX with SAB 80188 CPU
+SV
IM1
ORQO
SAB
80188
CPU
Serial
Channel A
OROTA
ORO 1
ORQRA
+5V
OACKA
SAB
82525
HS[X
Serial
Channel B
AO ... A6 00 ... 07
System Bus
Ao...AS
~O ... 07
The HSCX is connected to the demultiplexed system bus. Data transfer for one serial channel
can be done by the 2-channel on-chip DMA controller of the SAB 80188, the other channel
is serviced by interrupt. Since the SAB 80188 does not provide DMA acknowledge outputs,
data transfer from/to HSCX is controlled via CS, RD or WR address information (AO ... A6)
and the DACKA,
DACKB inputs are not used.
\
This solution supports applications with a high speed data rate in one serial channel with
minimum hardware expense making use of the on-chip peripheral functions of the
SAB 80188 (chip select logic, interruptcontroller, DMA controller).
Siemens Components, Inc.
685
I
SAB82525
SAB82526
SAF 82525
SAF 82526
HSCX with SAB 80186 Microprocessor and SAB 82258 Advanced DMA Controller (ADMA)
In applications, where two high-speed channels are required, a 16-bit system with SAB 801 a6
CPU and SAB 82258 ADMA is suitable. This shown in figure 4.
Figure 4
HSCX with SAB 80186 CPlJlSAB 82258 ADMA
+5V
SAB
80186
CPU
HLDA
DRQTA
DRQRA
DREQO
DREQI
DACKO
HOLD
SAB
82258
ADMA
DACKA
DACKI
DREa2
ORQ.TB
DREQ3
DRQRB
DACK2
Serial
Channel A
SAB
82525
HSCX
DACKB
DACK3
ADO ... AD19 SO ...52
A1...A7
System Bus
Siemens Components, Inc.
686
Serial
ChannelB
SAB82525
SAB82526
SAF 82525
SAF 82526
The four selector channels of AOMA are used for serving the four OMA request sources of
HSCX, allowing very high data rates at both the system bus and the serial channels.
Another big advantage of the AOMA is it's data chaining feature, providing an optimized
memory management for receive and transmit data. Recording the HSCX, a linked chain of
32 byte deep buffers can be set up, which are subsequently filled with the contents of the
HSCX's FIFOS during reception. Not used buffers can be saved and linked to another buffer
chain reserved for the reception of the next frame.
As a result, it's not necessary to reserve a very large space in system memory, determined by
the maximum frame length of every received frame.
In this example, the AOMA works directly at the CPU's local bus and shares the same bus
interface logic (address latches, transceivers, bus cbntroller) with the SAB 80186. Since one
OMA acknowledge line is provided for each OMA request, two OACK outputs must be
ANOed together for input to the HSCX.
The HSCX's data lines are connected to the lower half of the system data bus (00 ... 07)
and the address lines to A 1 ... A 7, thus (from the CPU's point of view) all internal register
addresses must be multiplied by two (even register addresses only).
e.g. CMOR register: HSCX address 61 H < = > system address C2 H•
Functional Description
General
The HSCX distinguishes from other low level HOLC devices by its advanced characteristics.
The most important are:
•
Enlarged support of link configurations.
Beyond the pOint-to-point configurations, the HSCX directly enables point-to-multipoint or
multimaster configurations without additional hardware or software expense.
In point-to-multipoint configurations, the HSCX can be used as a master as well as a slave
station. Even when working as slave station, the HSCX can initiate the transmission of data
at any time. An internal function block provides means of idle and collision detection and
collision resolution, which are necessary if several stations start transmitting simultaneously.
Thus also a multimaster configuration is possible.
Siemens Components, Inc.
687
I
SAB 82525
SAB 82526
SAF82525
SAF82526
Figure 5
Link Configuration
Point-to-Point Configuration
r----------,
r----------,
I
.1
I
I
1
1
I
I
Combined
Station
I
1
1
1
1
1
I
1
: Combined
1
:
1
1
1L
CPU
CPU
_________ ..J
1
1
1
1
L _________ -11
Point-to-Multipoint Configuration
Multimaster Configuration
I
I
I
IstatiOn(n-1)11""·---~---tl"~1 Station n I
Siemens Components, Inc.
1 Station
1
1
688
SAB82525
SAB82526
SAF 82525
SAF 82526
• Support of layer-2 functions by HSCX
Beside those bit-oriented functions usually supported with the HOLC protocol, such as bit
stuffing, CRC check, flag and address recognition, the HSCX provides a high degree of
procedural support. In a special operating mode (auto-mode), the HSCX processes the information transfer and the procedure handshaking (1-, and S-frames of HOLC protocol) autonomously. The only restriction is, that the window size (= number of outstanding unacknowledged
frames) is limited to 1, which will be sufficient in most applications. The communication procedures are mainly processed between the communication controllers and not between the
processors, thus the dynamic load of the CPU and the software expensive is largely reduced.
Figure 6
Procedural Support in Auto-Mode
~P
HSCC
rz-
HSCC
liP
S Frl1me
I Frl1me
U Frl1me
The CPU is informed about the status of the procedure and has to manage the receive and
transmit data mainly. In order to maintain cost effectiveness and flexibility, such functions as
link setup/disconnection and error recovery in case of protocol errors (U frames of HOLC
protocols) are not implemented in hardware and must be done by user's software.
• Telecomspecific features
In a special operating mode, the HSCX can transmit or receive data packets in one of up to
64 time slots of programmable width (clock mode 5). Furthermore, the HSCX can transmit
or receive variable data portions within a defined window of one or more clock cycles, which
has to be selected by an external strobe Signal (clock mode 1). These features make the
HSCX especially suitable for all applications using time division multiplex methods, such as
time-slot oriented PCM systems, systems designed for packet switching, or in ISON applications.
• FIFO buffers to efficient transfer of data packets.
A further speciality of HSCX are the FIFO buffers used for the temporary storage of data
packets transfered between the serial communications interface and the parallel system bus.
Also because of the overlapping input/output operation (dual- port behaviour), the maximum
message length is not limited by the size of the buffer. Together with the OMA capability, the
dynamic load of the CPU is drastically reduced by transfering the data packets block by
block via direct memory access. The CPU only has to initiate the data transmission by the
HSCX and determine the status in case of completely received frames, but is not involved
in data transfers.
Siemens Components, Inc.
689
I
SAB82525
SAB 82526
SAF 82525
SAF 82526
Operational Description
RESET
The HSCX is forced into the reset state if a high signal is input to the RES pin for a
minimum period of 1.8 ms. During RESET, the HSCX is temporarily in the power-up mode,
and a subset of the registers is initialized with defined values.
After RESET, the HSCX is in power down mode, and the following registers contain defined
values:
Table 1
RESET Values
Register
RESET
Value
Meaning
CCR1
OOH
- power down mode
serial port configuration; pt-pt, NRZ coding, transmit data
pins are open drain outputs
- clock mode 0
CCR2
OOH
RTS pin normal function
- CTS and RFS interrupts disabled
no data inversion
MODE
OOH
auto mode
1 byte address field
external timer mode
- receivers inactive
RTS output controlled by HSCX, timer resolution: k = 32.768,
no testloop
STAR
48H
XFIFO write enable
receive line inactive
no commands executing
ISTA
EXIR
OOH
-
CMDR
OOH
no commands
XBCH
RBCH
OOH
-
XCCR
RCCR
OOH
-
Siemens Components, Inc.
no interrupts masked
interrupt controlled data transfer (DMA disabled)
full-duplex LAPB/LAPD operation of LAP controller
carrier detect auto start of receiver disabled
1-bit time slot
690
SAB82525
SAB 82526
SAF 82525
SAF82526
Detailed Register Description
Register Address Arrangement
Table 2
Layout of Register Addresses
ADDRESS
~~
B
A
00
REGISTER
Read
Write
RFIFO
XFIFO
ReceivelTransmit FIFO
MASK
Interrupt STAtus/Mask
CMDR
STAtus/CoMnaD
40
1F
5F
20
60
ISTA
21
61
STAR
22
62
MODE
MODE
23
63
TIMR
TIMer
24
64
EXIR
XAD1
EXtended InterruptlTransmit ADdress 1
25
65
RBCL
XAD2
Receive Byte Count LowlTransmit ADdress 2
26
66
-
RAH1
Receive Address High 1
27
67
RSTA
RAH2
Receive STAtus/Rec. Addr. High 2
RAL1
Receive Address Low 1
28
68
29
69
RHCR
RAL2
Receive HDLC Control/Receive Addr. Low 2
2A
6A
Transmit Byte Count Low
6B
-
XBCL
2B
BGR
Baudrate Generator Register
2C
6C
20
60
RBCH
2E
6E
VSTR
2F
6F
30
70
31
71
32
72
33
73
CCR2
ReveivelTransmit Byte Count High
RLCR
Version STatus/Receive frame Length Check
CCR1
-
Channel Configuration Register 2
XBCH
Channel Configuration Register 1
TSAX
Time-Slot Assignment Transmit
TSAR
Time-Slot Assignment Receive
XCCR
Transmit Channel Capacity
RCCR
Receive Channel Capacity
Note: Channel A is not implemented in SAB 82526
Siemens Components, Inc.
691
I
SAB82525
SAB82526
SAF 82525
SAF 82526
Register Definitions
Receive FIFO (Read)
•
RFIFO (OO ...1F/40 ..• 5F)
Interrupt Controlled Data Transfer (Interrupt Mode)
selected if DMA bit in XBCH is reset.
Up to 32 bytes of receive data can be read from the RFIFO following an RPF
or an RME interrupt.
RPF Interrupt: Exactly 32 bytes to be read.
RMA Interrupt: Number of bytes to be determined by reading the RBCl, RBCH registers .
•
DMA Controlled DataTransfer (DMA Mode)
selected if DMA bit in XBCH
If the RFIFO contains 32 bytes, the HSCX autonomously requests a block data transfer by
DMA activating the DRQR line as long as the start of the 32nd read cycle. This forces the
DMA controller to continously perform bus cycles till 32 bytes are transfered from the HSCX
to the system memory. (level triggered, demand transfer mode of DMA controller).
If the RFIFO contains less than 32 bytes (one short frame or the last of a long frame) the
HSCX requests a block data transfer depending on the contents of the RFIFO according to
•
the following table:
RAFO
Contents
(Bytes)
DMA
Request
(Bytes)
(1) 2, 3
4
4-7
8
16
32
8-15
16-32
Additionally an RME interrupt is issued after the last byte has been transfered.
As a result, the DMA controller may transfer more bytes as actually valid in the current
received frame. The valid byte count must therefore be determined reading the RBCH, RBCl
registers following the RME interrupt.
Siemens Components, Inc.
692
SAB 82525
SAB82526
SAF 82525
SAF 82526
Transmit RFO (WRITE) XFIFO (OO ••. 1F/40 ... 5F)
•
Interrupt Mode
selected if DMA bit in XBCH is reset.
Up to 32 bytes of transmit data can be written to the XFIFO following an XPR interrupt.
•
DMAMode
selected if DMA bit in XBCH is set.
Prior to any data transfer, the actual byte count of the frame to be transmitted must be written
to the XBCH, XBCl registers by the user.
If data transfer is then initiated via the CMDR register (command XTF or XIF), the HSCX autonomously requests the correct amount of block data transfers (n*32+REST, n=0,1, ...).
Note: Addresses within the address space of the FIFO's are interpreted equally, i.e. the
actual data byte can be accessed with any address within the valid scope.
Interrupt Status Register (READ)
o
7
1ST A
I REM I RPF
RSC
XPR
TIN
ICA
EXA
EXB
(20/60)
Value after RESET: OOH
RME •.. Receive Message End
One message up to 32 bytes or the last part of a message greater then 32 bytes has been
received and is now available in the RFIFO. The message is complete!
The actual message lengh can be determined reading the RBCH, RBCl registers.
Additional information is available in the RSTA register.
RPF ... Receive Pool Full
A block of 32 bytes of a message is stored in the RFIFO. The message is not yet completed!
Note: This interrupt is only generated in interrupt Mode!
RSC ••• Receive Status Change (significant in auto mode only!)
A status change (receiver ready/receiver not ready) of the opposite station has been
detected in auto mode. (i.e. the HSCX has received a RR/RNR supervisory frame according to the HDlC protocol.) The current status can be read from the STAR register
(RRNR bit).
XPR ••• Transmit Pool Ready
A data block of up 32 bytes can be written to the transmit FIFO.
TIN •••nmer Interrupt
The internal timer and repeat counter has been expired. (See also description of TIMR
registerl)
Siemens Components, Inc.
693
I
SAS
SAS
SAF
SAF
82525
82526
82525
82526
ICA ... Interrupt of Channel A (Channel B only)
Indicates, that an interrupt is caused by channel A and the interrupt source(s) is (are)
indicated in the ISTA register of channel A (Le. at least one bit of the ISTA register of
channel A is set).
EXA •.. Extended Interrupt of Channel A (Channel B only)
An interrupt is caused by channel Band source(s) is (are) indicated in the EXIR register
of channel B.
Note: The ICA, EXA, and EXB bit are present in channel B only and point to the ISTA (CHA),
EXIR (CHA), and EXIR (CHB) registers.
After the HSCX has requested an interrupt by turning its INT pin to low, the CPU must
first read the ISTA register of channel B and check the state of these bits in order to
determine which interrupt source(s) of which channel(s) has caused the interrupt.
More than one interrupt source may be indicated by a single interrupt request.
After the respective register has been read, EXA, and EXB are reset. All other bits will be
reset after reading ISTA. To prevent malfunctions, each bit is individually monitored and
reset.
Mask Register (WRITE)
o
7
MASK
I RME I
RPF
I RSC
XPR
TIN
ICA
EXA
EXB
(20/60)
Value after RESET: OOH (all interrupts enabled)
Each interrupt source can be selectively masked by setting the respective bit in MASK
(bit positions corresponding to ISTA register). Masked interrupts are not indicated when
reading ISTA. Instead, they remain internally stored and will be indicated after the respective
MASK bit is reset.
Note: In the event of an extended interrupt, no interrupt request will be generated with a
masked EXA, EXB bit, although this bit is set in 1STA.
Siemens Components, Inc.
694
SAB
SAB
SAF
SAF
82525
82526
82525
82526
Extended Interrupt Register (READ)
Value after RESET: OOH
o
7
EXIR
PCE
RFO
CSC
RFS
o
o
(24/64)
XMR ... Transmit Message Repeat
The transmission of the last message has to be repeated because
- the HSCX has received a negative acknowledgment in auto mode,
- or a collision has occured after sending the 32nd data byte of a message in a bus
configuration.
- or CTS (transmission enable) has been withdrawn after sending the 32nd data byte of a
message in point-to-point configuration.
XDU/EXE ... Transmit Data Underrun/Extended Transmission End
The actual frame has been aborted with IDLE, because the XFIFO holds no further data,
but the frame is not yet complete!
In extended transparent mode, this bit indicates the transmission-end condition.
Note: It is not possible to send transparent-, or I-frames when a XMR or XDU interrupt is
indicated.
PeE ... Protocol Error (significant in auto mode only!)
The HSCX has detected a protocol error, Le. it has received
- an S-, or I-frame with incorrect N (R)
- an S-frame containing an I-field.
RFO ... Receive Frame Overflow
One frame could not be stored due to occupied RFIFO (i.e. whole frame has·been lost).
This interrupt can be used for statistical purposes and indicates, that the CPU does not
respond quickly enough to an incoming RPF, or RME interrupt.
CSC ... Clear To send Status Change
Indicates, that a state transition has occured at the CTS pin. The actual state can be read
from STAR register (CTS bit)
This interrupt must be enabled setting the CIE bit in CCR2.
RFS ... Receive Frame Start
This is an early receiver interrupt activated after the start of a valid frame has been
detected, Le. after a valid address check in operation modes providing address recognition, otherwise after the opening flag (transparent mode 0), delayed by two bytes.
After an RFS interrupt, the contents of
•
•
•
RHCR
RAL1
RSTA - bit 3-0
are valid and can be read by the CPU.
This interrupt must be enabled setting the RIE bit in CCR2.
Siemens Components, Inc.
695
SAB82525
SAB82526
SAF 82525
SAF 82526
Status Register (READ)
Value after RESET: 48 H
o
7
STAR
I XDOV I XFW I XRNR I RRNR I
RLI
CEC
CTS
WFA
(21/61)
XDOV ... Transmit Data Overflow
More than 32 bytes have been written to the XFIFO.
XFW ... Transmit FIFO Write Enable
Data can be written to the XFIFO.
XRNR ... Transmit RNR (significant in auto mode only!)
Indicates the status of the HSCX.
o ... receiver ready
1 ... receiver not ready
RRNR ... ReceivedRNR (significant in auto mode only!)
Indicates the status of the remote station.
o... receiver ready
1 ... receiver not ready
RLI ... Receive Line Inactive
Neither FLAGs as interframe time fill nor frames are received via the receive line.
Note: Significant in point-to-point configurations!
CEC ... Command Executing
o... no command is currently executed, the CMDR register can be written to.
1 ... a command (written previously to CMDR) is currently executed, no further command
can be temporarily written via CMDR register.
Note: CEC will be active at most 2.5 transmit clock periods. If the HSCX is in power down
mode CEC will stay active.
CTS ... Clear To Send State
If the CIE bit in CCR2 is set, this bit indicates the state of the CTS pin.
o... CTS is inactive (high signal at CTS)
1 ... CTS is active (lOW signal at CTS)
.WFA ... Waiting For Acknowledgement (significant in auto mode only).
Indicates the 'Waiting for Acknowledgement' status of HSCX.
Siemens Components, Inc.
696
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Command Register (WRITE)
Value after RESET: OOH
7
CMDR
RMC
RHR
I:~E~ I Sl1
XTF
XIF
XME
°
(21/61)
RMC ... Receive Message Complete
Confirmation from CPU to HSCX, that the actual frame or data block has been fetched
following an RPF or RME interrupt, thus the occupied space in the RFIFO can be released.
Note: In DMA mode, this command is only issued once after a RME interrupt. The HSCX
does not generate further DMA requests prior to the reception of this command.
RHR ... Reset HDLC Receiver
All data in the RFIFO and the HDLC receiver deleted.
In auto mode, additionally the transmit and receive sequence number counters are reset.
RNR/XREP ... Receiver Not ReadyITransmission Repeat
The function of this command depends on the selected operation mode (MDS1, MDSO,
ADM bit in MODE):
• Auto mode: RNR
The status of the HSCX receiver is set. Determines, whether a received frame is acknowled
via an RR, or RNR supervisory frame in auto mode.
Receiver Ready (RR)
1 ... Receiver Not Ready (RNR)
• Extended transparent mode 0,1 : XREP
Together with XTF and XME set (write 2AH to CMDR), the HSCX repeatedly transmits the
contents of the XFIFO (1 . . . 32 bytes) without HDLC framing fully tranparent, i. e. without
FLAG, CRC insertion, bit stuffing.
The cyclic transmission is stopped with an XRES command!
o...
STI ... Start Timer
The internal timer is started.
Note: The timer is stopped by rewriting the TIMR register after start.
Siemens Components, Inc.
697
SAB
SAB
SAF
SAF
82525
82526
82525
82526
XTF ... Transmit Transparent Frame
• Interrupt mode
After having written up to 32 bytes the XFIFO, this command initiates the transmission of a
transparent frame. An opening flag sequence is automatically added to the data by the
HSCX.
• DMA mode
After having written the length of the frame to be transmitted to the XBCH, XBCL registers,
this command initiates the data transfer form system memory to HSCX by DMA. Serial
data transmission starts as soon as 32 bytes are stored in the XFIFO.
XIF ... Transmit I-Frame (used in auto mode onlyl)
Initiates the transmission of an I-frame in auto mode. Additional to the opening flag
sequence, the address and control field of the frame is automatically added by HSCX.
XME ... Transmit Message End (used in interrupt mode only!)
Indicates, that the data block written last to the transmit FIFO completes the actual frame.
The HSCX can terminate the transmission operation properly by appending the CRC and
the closing flag sequence to the data.
In DMA mode, the end of the frame is determined by the transmit byte count in XBCH,
XBCl!
XRES ... Transmit Reset
The contents of the XFIFO is deleted and IDLE is transmitted. This command can be used
by the CPU to abort a frame currently in transmission. After setting XRES an XPR interrupt
is generated in every case.
Note: The maximum time between writing to the CMDR register and the execution of the
command is 2.5 clock cycles. Therefore, if the CPU operates with a very high clock in
comparison with the HSCX's clock, it's recommended that the CEC bit of the STAR register
is checked before writing to the CMDR register to avoid any loss of commands.
Mode Register (READ/WRITE)
Value after RESET: OOH
o
7
MODE
I MDS1 IMDSO I ADM
TMD
RAC
RTS
MDS1, MDSO ... Mode Select
The operating mode of the HDLC controller is selected.
00 ... auto mode
01 ... non-auto mode
10 ... transparent mode
11 ... extended transparent mode
Siemens Components, Inc.
698
TRS
TLP
(22/62)
SAS
SAS
SAF
SAF
82525
82526
82525
82526
ADM . .. Address Mode
The meaning of this bit varies depending on the selected operating mode:
• Auto mode, non-auto mode
Defines the length of the HDLC address field.
o ... 8-bit address field
1 ... 16-bit address field
In transparent modes, this bit differentiates between two sub-modes:
•
Transparent mode
o ... transparent mode 0; no address recognition.
1 ... transparent mode 1; high byte address recognition.
•
Extended transparent mode; without HDLC framing.
o ... extended transparent mode 0
1 ... extended transparent mode 1
Note: In extended transparent modes, the RAC bit must be reset to enable fully transparent
reception!
TMD ... Timer Mode
The operation mode of the internal timer is set.
o ... external mode
The timer is controlled by the CPU and can be started at any time setting the STI bit in
CMDR.
1 ... internal mode
The timer is used internally by the HSCX for timeout and retry conditions in auto-mode.
(refer to the description of the TIMR register)
RAe . .. Receiver Active
Switches the receiver to inoperational state.
o ... receiver inactive
1 ... receiver active
In extended transparent modes this bit must be reset to enable fully transparent reception!
RTS ... Request To Send
Defines the state and control of RTS pin.
o ... The RTS pin is controlled by the HSCX autonomously.
RTS is activated when a frame transmission starts and deactivated after the transmission
operation is completed.
1 ... The RTS pin is controlled by the CPU.
If this bit is set, the RTS pin is activated immediately and remains active till this bit is reset.
Siemens Components, Inc.
699
I
SAB 82525
SAB82526
SAF 82525
SAF82526
TRS ... Timer Resolution
The resolution of the internal timer (factor k, see description of TIMR register) is selected
0 ... k=32.768
1 ... k=512
TLP ... Test Loop
Input and output of the HDLe channels are intenally connected
(transmitter channel A - receiver channel AI
transmitter channel 8 - receiver channel 8)
Timer Register (READIWRITE)
7
TIMR
5
o
4
CNT
VALUE
(23/63)
VALUE ... Sets the time period t, as follows:
t1 = k x (VALUE
where
+ 1) x TXP
-
k is the timer resolution factor which is either 32.768 or 512-clock cycles dependent
on the programming of TRS bit in MODE.
-
TCP is the clock period of transmit data.
CNT ... Interpreted differently dependent on the selected timer mode (bit TMD in MODE).
•
-
Internal timer mode (MODE.TMD = 1)
retry counter (in HDLC known as N2)
CNT indicates the number of S-commands (max. 6) which are transmitted autonomously
by the HSCC after expiration of time period t1 , in case an I-frame is not acknowledged
by the opposite station.
If CTN is set to 7, the number of S-commands is unlimited.
•
External timer mode (MODE, TMD = 0)
CNT plus VALUE indicates the time period t2 after which a timer interrupt will be generated. The time period t2 is
t2 = 32 x k x CNT x TCP + 11
If CTN is set to 7, a timer interrupt periodically generated after the expiration of t1 •
Siemens Components, Inc.
700
SAS
SAS
SAF
SAF
82525
82526
82525
82526
Transmit Address Byte 1 (WRITE)
o
7
XAD 1 2-byte address
XAD1 (high byte)
o
(0)
(24/64)
XAD 1 (COMMAND)
1-byte address
XAD1 (and XAD2) can be programmed with one individual address byte which is appended
automatically to the frame by HSCX in auto mode. The function depends on the selected
address mode (bit ADM in MODE).
-
2-byte address field (MODE. ADM = 1)
XAD1 builds up the high byte of the 2-byte address field. Bit 1 must be set to O! According
to the ISDN LAP 0 protocol, bit 1 is interpreted as the C/R (COMMAND/RESPONSE) bit.
This is manipulated automatically by the HSCX dependet on the setting of the CRI bit in RAH 1 :
Bit 1 (C/R)
Commandstransmit
1
0
Responses transmit
0
1
CRI=1
CRI=O
(In the ISDN, the high address byte is known as SAPI).
In accordance with the HDLC protocol, bit 0 should be set to 0, indicating the extension of
the address field to two bytes.
1-byte address field (MODE.ADM = 0)
According with the X.25 LAP B protocol, XAD1 indicates a COMMAND.
Siemens Components, Inc.
701
I
SAB82525
SAB82526
SAF 82525
SAF 82526
Transmit Address Byte 2 (WRITE)
o
7
XAD2 2-byte address
XAD2 (low byte)
1-byte address
(25/65)
XAD2 (RESPONSE)
Second individually programmable address byte.
-
2-byte address (MODE.ADM = 1)
XAD2 builds up the low byte of the 2-byte address field
(In the ISDN, the low address byte is known as TEl)
1-byte address (MODE.ADM = 0)
According to the X.25 LAP B protocol, XAD2 indicates a RESPONSE,
Note: XAD1, XAD2 registers are used only if the HSCX is operated iii auto-mode.
Receive Byte Count Low (READ)
o
7
RBCL
I RBC7
RBCO
(25/65)
Together with RBCH (bits RBC11 - RBC8), the length of the actual received frame (1 ... 4095
bytes) can be determined. These registers must be read by the CPU following a RME interrupt.
Siemens Components, Inc.
702
SAB 82525
SAB82526
SAF 82525
SAF 82526
Receive Address Byte High Register 1 (WRITE)
a
7
RAH1
RAH1
CRI
a
(26/66)
In operating modes that provide high byte address recognition, the high byte of the received
address is compared with the individual programmable values in RAH 1, or RAH2.
RAH 1 ... Value of the first individual high address byte
CRI ... Command/Response Interpretation
The setting of the CRI bit affects the meaning of the C/R bit in RSTA as follows:
C/R meaning
C/Rvalue
Commands received
a
1
Responses received
1
a
CRI=1
CRI=O
Important: If the 1 byte address field is selected in auto mode, RAH 1 must be set to OOH'
Siemens Components, Inc.
703
I
SAB82525
SAB82526
SAF 82525
SAF 82526
Receive Address Byte High Register 2 (WRITE)
o
7
RAH2
MCS
RAH2
o
(27/67)
RAH2 ... Value of second individual programmable high address byte.
MCS ... - Module Count Select -; valid in auto mode only.
The MCS bit adjusts the control field format according to the HDLC (ISDN/LAPD).
basic operation (modulo 8)
1 ... extended operation (modulo 128)
o...
Note: When modulo 128 is selected, in auto mode the "RHCR" register contains compressed
information of the extended control field (see RHCR, register description). RAH 1, RAH2
registers are used in auto- and non-auto operating modes when a 2-byte address field
has been selected (MODE.ADM = 1) and in the transparent mode O.
Receive Status Register (READ)
o
7
RSTA
VFR
ROO
CRe
RAB
HA1
VFR ... Valid Frame
Determines whether a valid frame has been received.
1 ... Valid
0 ... Invalid
Siemens Components, Inc.
704
HAO
C/R
LA
(2)/67)
SAB 82525
SAB 82526
SAF 82525
SAF 82526
An invalid frame is either
- a frame which is not an integer number of 8 bits (n * 8 bits) in length (e.g. 25 bit), or
- a frame which is too short depending on the selected operation mode via MODE
(MDS 1, MDSO, ADM) as follows:
• Auto-/non-auto mode (16-bit address): 4 bytes
• Auto-/non-auto mode (8-bit address): 3 bytes
• Transparent mode 1:3 bytes.
• Transparent mode 0:2 bytes.
Note: Shorter frames are not reported.
RDO ...Receive Data Overflow
A data overflow has occured within the actual frame.
CRC •.. CRC compare/check
O ... CRC check failed; received frame contains errors.
1 ... CRC check o.k.; received frame is error-free.
RAB ... Receive Message Aborted
The received frame was aborted from the transmitting station.
According to the HDLC protocol, this frame must be discarded by the CPU.
HA1, HAO ... High Byte Address Compare; significant only if 2-byte address mode has been
selected.
In operating modes which provide high byte address recognition, the HSCX compares
the high byte of a 2-bytes address with the contents of two individual programable registers
(RAH 1, RAH2) and the fixed values FEH and FC H (group address).
Dependent on the result of this comparison, the following bit combinations are possible:
10 ... RAH 1 has been recognized
00 ... RAH2 has been recognized
01 ... group address has been recognized
Note: If RAH 1, RAH2 contain the identical values, the combination 00 will be omitted.
C/R ... Command/Response; significant only, if 2-byte address mode has been selected.
Value of the C/R bit (bit of high address byte) in the received frame. The interpretation
depends on the setting of the CRI bit in the RAH 1 register. Refer also to the description
of RAH 1 register.
LA ..• Low Byte Address Compare; not significant in transparent and extended transparent
operating modes.
The low byte address of a 2-byte address field, or the single address byte of a 1-byte
address field is compared with two programmable registers (RAL 1, RAL2)
RAL2 has been recognized
1 ... RAL 1 has been recognized
According to the X.25 LAP B protocol, RAL 1 is interpreted as COMMAND and RAL2 interpreted as RESPONSE.
o...
Note: RSTA corresponds to the last received HDLC fram; it is duplicated into RFIFO for every
frame (last byte of frame).
Siemens Components, Inc.
705
I
SAB82525
SAB82526
SAF 82525
SAF 82526
Receive Address Byte Low Register 1 (READIWRITE)
o
7
RAL1
I
RAL1
(28/68)
The general function (READ/WRITE) and the meaning or contents of this register depends
on the selected operating mode:
Auto-/non-auto mode (16-bit address) - WRITE:
RAL 1 can be programmed with the value of the first individual low address byte.
Auto-/non-auto mode (8-bit address) - WRITE:
According to X.25 LAP B protocol, the address in RAL 1 is recognized as COMMAND
address.
-
Transparent mode 1 (high byte address recognition) - READ:
RAL 1 contains the byte following the high byte of the address in the receive frame (i.e. the
second byte after the opening flag).
Transparent mode 0 (no address recognition) - READ:
RAL 1 contains the first byte after the opening flag (first byte of received frame).
Extended transparent modes 0,1 - READ:
RAL 1 contains the actual data byte currently assembled at the R x D pin, by passing the
HDLC receiver (fully transparent reception without HDLC framing).
Receive Address Byte Low Register 2 (WRITE)
a
7
RAL2
RAL2
(29/69)
Value ot the second individual programmable low address byte. If a one byte address field
is selected, RAL2 is recognized as RESPONSE according to X.25 LAP B protocol.
Siemens Components, Inc.
706
SAB82525
SAB 82526
SAF 82525
SAF 82526
Receive HDLC Control Register (READ)
7
RHCR
°
RHCR
(29/69)
Value of the HDCL control field of the last received frame.
Note: RHCR is duplicated into RFIFO for every frame.
Transmit Byte Count Low (WRITE)
°
7
XBCL
I'-X_B_C_7_ _ _ _ _ _ _ _ _ _ _ _ _ _
X_BC_o---'1
(2A16A)
Together with XBCH (bits XBC11 ... XBC8) this register is used in DMA mode only, to
programm the length (1 ... 4095 bytes) of the next frame to be transmitted.
This allows the HSCX to request the correct amount of DMA cycles after an XTF or XIF
command via CMDR.
I
Baud Rate Generator Register (WRITE)
°
7
BGR
II-B_R_7_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
B_RO---'1
(2B/6B)
BR7 - BRO ... Baude Rate, bit 7-0
Together with bits BR9, BR8 of CCR2, the division factor of the baud rate generator is
adjusted.
Dependent on the programmed value N in BR9 - BR8 (N =
1023), the division factor k
results as follows:
°...
k=(N+1)x2
Siemens Components, Inc.
707
SAB82525
SAB82526
SAF 82525
SAF 82526
Channel Configuration Register 2 (READIWRITE)
Value after RESET: OOH
The meaning of the individual bits in CCR2 depends on the selected clock mode via CCR 1
as follows:
[SOC1
SOCO
0
0
0
CIE
RIE
DIV
clock mode 2,61 BR9
BRB
BDF
TSS
TIO
CIE
RIE
DIV
clock mode 3,71 BR9
BRB
BDF
0
TIO
CIE
RIE
DIV
clock mode 5
ISOC1 SOCO xcso Rcsol TIO
CIE
RIE
DIV
clock mode 4
ISOC1 SOCO
TIO
CIE
RIE
DIV
CCR2 clock mode 0,1
0
0
I (2C/6C)
Soo1, SOCO ••. Special Output Control
In a bus configuration (selected via CCR1) the function of pin RTS can be defined
o 0 ... RTS output is activated during the transmission of a frame.
1 O ... RTS output is always high (RTS disabled).
1 1 ... RTS indicates the reception of a data frame (active low).
In point to point configuration (selected via CCR 1) the T x 0 and R x 0 pins may be flipped
OX ... data is transmitted on T x 0, received on R x 0 pin (normal case)
1 X ... data is transmitted on R x 0, received on T x 0 pin
BR9, BR8 .•• Baud Rate,Bit 9-8 (higher significant bits, refer to description of BGR register).
BDF ••• Baud Rate Division Factor
O ... The division factor of the baud rate generator is set to 1 (constant).
1 ... The division fachtor is adjusted with BR9 - BRO bits of CCR2 and BRG register.
TSS ••• Transmit Clock Source Select
The transmit clock is input to the T x ClKA/T x ClKB pins
1 ... The transmit clock is derived from the baud rate generators output divided by 16.
o...
TlO ••• Transmit Clock Input Output Switch
T x ClKA, T x ClKS pins are inputs
1 ... T x ClKA, T x ClKS pins are outputs
o...
CIE ••• Clear To Send Interrupt Enable
Any state transition at the CTS input pin may cause an interrupt which is indicated in the
EXIR register (CSC bit). The actual state at the CTS pin can be determined reading the CTS
bit of the STAR register.
0 ... disable
1 ... enable
Siemens Components, Inc.
708
SAB82525
SAB82526
SAF 82525
SAF 82526
RIE ... Receive Frame Start Interrupt Enable
When, the RFS interrupt (via EXIR) is enabled!
DIV •.. Data Inversion
Only valid if NRZ data encoding is selected. Data is transmitted and received inverted.
XCSO, RCSO ... TransmiVReceive Clock Shift, Bit 0
Together with bits XCS2, XCS1 (RCS2, RCS 1) in TSAX (TSAR) the clock shift relative to
the frame synchronization signal of the transmit (receive) time slot can be adjusted.
A clock shift of 0 ... 7 bits is programmable (clock mode 5 only!).
Transmit Byte Count High (WRITE)
Value after RESEr: OOOxxxxx
7
XBCH
3
0
L...-D_M_A--,-_N_R_M_,--C_A_S--,-_X_C_,-IX_B_C_1_1_ _ _X_B_C_B....JI
(2D/6D)
DMA •.• DMA Mode
Selects the data transfer mode of HSCX to system memory.
Interrupt controlled data transfer (interrupt mode)
1 ... DMA controlled data transfer (DMA mode)
o ...
NRM ••. Normal Response Mode
Valid in auto mode only!
Determines the function of the LAP controller:
full-duplex LAP B/LAP D operation
1 ... half-duplex NRM operation
o...
CAS ••. Carrier Detect Auto Start
When set, a high at the CD (AxCLK) pin enables the respective receiver and data reception is started.
XC ••. Transmit Continuously
Only valid if DMA mode is selected!
If the XC bit is set, the HSCX continuously requests for transmit data ignoring the transmit
byte count programmed via XBCX, XBCl.
XBC11 •••XBC8 .•• Transmit Byte Count (most significant bits)
Valid only if DMA mode is selected!
Together with XBC7 ... XBCO) the length of the frame to be programmed.
Siemens Components, Inc.
709
I
8AB
8AB
8AF
8AF
82525
82526
82525
82526
Received Byte Count High (READ)
Value after RESET: OOOxxxxx
3
7
RBCH
OMA
I NRM I
CAS
OV
I RBC11
0
RBC8
I
(20/60)
r-----L---~L---~----~--------------~
seeXBCH
DMA, NRM, CAS . .. These bits represent the read-back value programmed in XBCH (see
XBCH!)
OV ... Counter Overflow
More than 4095 bytes received!
The received frame exceeded the byte count in RBC11 '" RBCO.
RBC11 ... RBC8 ... Receive Byte Count (most significant bits)
Together with RBCl (bits RBC7 ... RBCO) the length of the received frame can be determined.
Version Status Register (READ)
VSTR
o
3
7
CO
o
o
o I VN3
CD ... Carrier Detect
This bit represents the inverted state at the CO (AxClK) pin.
1 ... CD active (lOW)
CD inactive (HIGH)
o...
VN3 ... VNO ... Version Number of Chip
o... Version A 1
2 ... Version A2
4 ... Version A3
Siemens Components, Inc.
710
VNO
(2E/6E)
SAB
SAB
SAF
SAF
82525
82526
82525
82526
Receive Length Check Register (WRITE)
o
7
RlCR
RC
I Rl6
RlO
(2E/6E)
RC ••• Receive Check (on/off)
receive length check feature disabled
1 ... receive length check feature enabled
o...
RL •.. Receive Length
The maximum receive length after which data reception is suspended can be programmed
here. Depending on the value Rl programmed via Rl6 ... RlO, the receive length is
(Rl + 1)x32 bytes! A frame exceeding this length is treated as if it was aborted by the
opposite station (RME Interrupt, RAB bit set).
In this case, the Receive Byte Count (RBCH, RBCl) is greater than the programmed
receive length.
Channel Configuration Register 1 (READ/WRITE)
Value after RESET: OOH
o
7
CCR1
PU
I
SC1
seQ
I ODS
ITF
OIN
ICM2 CM1 CMQ !
PU •.• Switches between Power Up and Power Down mode
0 ... power down (standby)
1 ... power up (active)
SC1, SCO .•• Serial Port Configuration
00 ... NRZ data encoding
10 ... NRZI data encoding
01 ... bus configuration, timing mode 1
11 ... bus configuration, timing mode 2
Note: It bus configuration is selected, only NRZ coding is supported.
Siemens Components, Inc.
711
(2F/6F)
I
SAB82525
SAB82526
SAF 82525
SAF 82526
ODS ••• output Driver Select
Defines the function of the transmit data pins (TxDA, TxDB)
TxD pins are open drain outputs
1 ... TxD pins are push-pull outputs
o...
ITF/OIN ••• Interface Time Fill/One Insertion
The function of this bit depends on the selected serial port configuration (bit SC1)
• POint-to-point configurations: ITF
Determines the idle (= no data to send) state of the transmit data pins (TxDA, TxDB)
O ... Continuous IDLE sequences are output (TxD pins remain in the "1" state)
1 ... Continuous FLAG sequences are output ("01111110" bit patterns)
• Bus configurations: OIN
In bus configurations, the ITF is implicitly set to 0, i.e. continuous "1 "s are transmitted, and
data encoding is NRZ!
When this bit is set, a "ONE" insertion (deletion) mechanism is activated, inserting a "1"
after seven consecutive "O"s in the transmit data stream or deleting a "1" in the receive
data stream.
Similar to the HDLC's bit-stuffing mechanism (inserting a "0" after five consecutive "1 "s),
this method proves to be advantageous when the receive clock is recovered from the
receive data stream by means of DPLL, because it is guaranted that at least after seven
bits a transition occurs in the receive data in case of long "0" sequences!
CM2, CM1, CMO •.. Clock Mode
Selects one of the 8 different clock modes
000
clock mode 0
111
clock mode 7
Time-Slot Assignment Register Transmit (WRITE)
This registers is only used in clock mode 5!
TSAX
o
2
7
TSNX
XCS2
I XCS1
(30170)
TSNX •.• Time-Slot Number Transmit
Selects one of up 64 possible time slots (00H-3FH) in which data is transmitted. The
number of bits per time slot can pe programmed via XCCR.
XCS2, XCS1 •.• Transmit Clock Shift, Bit 2-1
Together with bet XCSO in CCR2, the transmit clock shift can be adjusted.
Siemens Components, Inc.
712
SAB
SAB
SAF
SAF
82525
82526
82525
82526
Time-5lot Assignment Register Receive (WRITE)
This register is only used in clock mode 5!
o
7
TSAR
TSNR
RCS2
RCS1
(31/71 )
TSNR ... Time-5lot Number Receive
Defines one of up to 64 possible time slots (OOH-3FH) in which data is received. The
number of bits per time slot can be programmed via RCCR.
RCS2, RCS1 ... Receive Clock Shift, Bit 2-1
Together with bit RCSO in CCR2, the receive clock shift can be adjusted.
Transmit Channel Capacity Register (WRITE)
Value after RESET: OOH
o
7
XCCR
ILX_B_C_7_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
X_B_C---'OI
(32/72)
XBC7 ... XBCO ... Transmit Bit Count, Bit 7-0
I
Defines the number of bits to be transmitted with a time slot:
Number of bits = XBC + 1. (1 ... 256 bits/time slot)
Receive Channel Capacity Register (WRITE)
o
7
RCCR
RBCO
I RBC?
Value after RESET: OOH
RBC7 ... RBCO ... Receive Bit Count, Bit 7-0
Defines the number of bits to be received within a time slot:
Number of bits = RBC + 1. (1 ... 256 bits/time slot)
Siemens Components, Inc.
713
(33/73)
SAB82525
SAB82526
SAF82525
SAF82526
Absolute Maximum Ratings
Limit Values
Parameter
Symbol
Ambient temperature under bias: SAB
SAF
TA
TA
-40 to 85
Storage temperature
Tstg
-65 to 125
°C
°C
°C
Voltage on any pin with respect to ground
Vs
-0.4 to Voo +0.4
V
o to 70
Unit
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum ratings conditions for extended periods may affect
device reliability.
Characteristics
TA = 0 to 70°C; Voo = 5 V ± 5%, Vss = 0 V.
Limit Values
Parameter
Symbol
min.
max.
L-input voltage
0.8
V
Vcc+0.4
V
0.45
V
ViL
-0.4
H-input voltage
ViH
2.0
L-output voltage
VOL
H-output voltage
H-output voltage
VOH
VOH
Power
supply
current
Icc
operational
power down
Input leakage current
Output leakage current
Siemens Components. Inc.
III
lLO
Unit
Test Conditions
8
rnA
= 7 rnA (pins TxD, RxD)
= 2 rnA (all other)
IOH = -400 JJA
IOH = -100 JJA
Voo = 5 V. C p = 4 MHz
1.5
rnA
Inputs at 0 V/Voo •
no output loads
10
JJA
V
V
2.4
Voo-0.5
714
IOL
IOL
o V < ViN < Voo to 0 V
o V< VOUT < Voo to 0 V
SAB 82525
SAB 82526
SAF82525
SAF 82526
Capacitances
TA = 25°C, Voo = 5 V ± 5%, Vss = 0 V, fc
= 1 MHz, unmeasured pins returned to GND.
Limit Values
Parameter
Symbol
typo
max.
Unit
Input capacitance
fc= 1 MHz
GIN
5
10
pF
Output capacitance
GOUT
10
20
pF
1/0
Gila
8
15
pF
Characteristics
TA = 0 to 70°C, Voo = 5 V ± 5%
Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and at 0.8 V for a logical "0".
The AC testing inpugtloutput waveforms are shown below.
Input/Output Waveform for AC Tests
2.4
2.0"
Device
Under
Test
2.0
Test POints/
0.8 /
"0.8
0.45
Siemens Components, Inc.
715
SAB82525
SAB82526
SAF 82525
SAF 82526
Microcontroller Interface Timing
Intel Bus Mode
IlP Read Cycle
DRQR
--1
IlP Write Cycle
Multiplexed Address Timing
AO-A7
OACK
AO-A7
DACK
Siemens Components, Inc.
716
SAS
SAS
SAF
SAF
Motorola Bus Mode
IJ.P Read Cycle
RlW~
ORQT
t DsD
~
Address Timing
ALE
(S* WR
CS*RO
------+-1----_
Siemens Components. Inc.
717
82525
82526
82525
82526
SAB82525
SAB82526
SAF82525
SAF82526
Interface Timing
Limit Values
Parameter
Symbol
min.
ALE pulse width
tAA
Address setup time to ALE
tAL
Address hold time from ALE
tLA
Address latch setup time to WR, RD
t ALS
Address setup time to WR, RD
t AS
Address hold time from WR, RD
tAH
50
10
20
0
10
20
DMA request delay: SAB
SAF
tORH
RD pulse width
tRR
Data output delay from RD
t RO
Data float delay from RD
tOF
RD control interval
tRI
WR pulse width
tww
Data setup time to WR+CS
tow
Data hold time from WR+CS
two
WR control interval
tWI
Siemens Components, Inc.
718
max.
ns
ns
ns
ns
ns
ns
85
90
120
ns
ns
ns
120
25
60
60
30
10
60
Unit
ns
ns
ns
ns
ns
ns
ns
SAB82525
SAB82526
SAF82525
SAF 82526
Serial Interface Timing
Clock Mode 1
R (lock
RxDAlB
X (lock
TxDAlB
---t-------tt-~.r_----I_--- Bus
---+--~----t+-..J'1<----_+_---
Timing
Mode 2
(xDAlB
(TSAIB
RTSAIB
Bus
".,..-----+---- ~:~:g2
Bus
Timing
Mode I
I
Limit Values
Parameter
Symbol
min.
Receive data setup
t RDS
5
max.
Unit
ns
Receive data hold
tRDH
30
ns
Collision data setup
tCDS
0
ns
Collision data hold
tCDH
30
Transmit data delay
tXDD
20
Request to send delay 1
tRTD1
Request to send delay 2
tRTD2
ns
70
ns
30
120
ns
20
85
ns
Clock period
tcp
240
ns
Clock period Low
t CPL
90
ns
Clock period High
t CPH
90
ns
Siemens Components, Inc.
719
SAB 82525
SAB 82526
SAF82525
SAF82526
Strobe Timing
RxCLK
AxCLK
TxCLK
TxD
__________ txDDE-txczr_
Bus
Timing
Mode 2
Limit Values
max.
Unit
Parameter
Symbol
min.
Receive strobe delay
t RsD
Receive strobe setup
tRSS
Receive strobe hold
tRSH
Transmit strobe delay
t XSD
Transmit strobe setup
t xss
Transmit strobe hold
tXSH
30
60
30
30
60
30
Transmit data delay
tXDD
70
ns
90
50
50
ns
Strobe data delay
tsoo
High impedance from clock
txcz
High impedance from strobe
txsz
Siemens Components, Inc.
720
ns
ns
ns
ns
ns
ns
ns
ns
SAB 82525
SAB 82526
SAF82525
SAF82526
Clock Mode 5
Figure 17
Synchronization Timing
1 - - - - - tSD - - - - - - - I
RxCLK
AxCLK
TxCLK
Bus
Timing
Mode 2
LlmltValu..
Parameter
Symbol
min.
Sync pulse delay
teo
Sync pulse setup
tee
Sync pulse width
tew
Time-slot control delay
tTCD
30
30
40
20
Siemens Components, Inc.
721
max.
Unit
ns
ns
ns
75
ns
SAB 82525
SAB 82526
SAF82525
SAF 82526
Clock Mode 2, 3, 6, 7
Internal Clocking
Limit Values
Parameter
Symbol
Clock frequency
8audrate generator used
Clock frequency
8audrate generator not used
min.
max.
Unit
'ClK
12.3
MHz
'ClK
19.3
MHz
Reset Timing
RES Characteristics
Limit Values
Parameter
RES high
Siemens Components, Inc.
Symbol
min.
tRWH
1800
722
I max.
I
Unit
ns
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Appendix A
Upgrades of HSCX Version A3
The HSCX Version A3 is fully upward compatible to Version A2. The differences with respect
to HSCX Technical Manual Rev. 2.89 are shown in table 3.
Table 3
Differences HSCX A2 - HSCX A3
Differences
Ver. A2
Ver. A3
Data Book Chapter
TRI, TWI value
IOL value, pin TxD
VSTRvalue
70 ns
2mA
02 H
SO ns
SmA
04 H
Microcontroller Interface Timing
Characteristics
VSTR, Register Definition
The following additional are implemented in HSCX A3
•
Transmission of back to back frames
Two or more frames may be transmitted continuously without interframe time fill
•
TxD, RxD flip
In clock modes 0,1,4 and 5 pins RxD and Tx may beflipped
•
Status Register
In auto mode, STAR: bit 0 indicates the 'Waiting for Acknowledgement' status
Siemens Components, Inc.
723
SIEMENS
Integrated Data Protocol Controller
SAB 79C401
(IDPC)
ADVANCE INFORMATION
General Description
The SAB 79C401 Integrated Oata Protocol Controller (IOPC) provides many of the essential
building blocks for construction of a variety of communications systems. When combined
with ROM, RAM, a microprocessor, and the appropriate physical layer transceiver, a complete
ISON, X.25, SNA, or similar system can be constructed.
The IOPC contains hardware and software support features for use in a single-processor
environment (such as a terminal adaptor to an IS ON network) or a multi-processor
application (such as a communication interface for a PC or integrated voice/data work
station application). For multi-processor applications, the lOPe controls access to an
external "shared" RAM which serves as a data buffer and communications area ("mailbox"
concept). The IOPC arbitrates simultaneous requests for RAM access and supports an
inter-processor interrupt scheme.
Functionally, the lope consists of four sections: Oata Link Controller (OLe), Universal
Synchronous/Asynchronous ReceiveriTransmitter (USART), Oual-Port Memory Controller
(OPMC), and Microprocessor Interface (MPI).
Data Link Controller (OLC)
The OLe is a high-speed, bit-oriented protocol processor that supports either multiplexed
or non-multiplexed data transfer rates up to 2.048 Mbitls.
The OLe provides full-duplex (simultaneous transmit and receive) data transfer between
the chip's serial bus port and internal parallel bus. Through the use of a 32-byte receive
FIFO, 16-byte transmit FIFO, and two external OMA channels, the OLC provides efficient
movement of data to and from external memory and the serial bus port (network interface).
The OLC supports data transfers via OMA, interrupts, or polled I/O. The use of the FIFO
buffers minimize interrupt latency and frequency of interrupts.
Universal
Syn~hronous/Asynchronous
Receiver/Transmitter (USART)
The IOPC contains a built-in USART for exchanging data between terminals and the ISON
network in applications where there is no host processor. The USART provides a superset
of 8250 UART features and supports both synchronous and asynchronous serial communications. The USART is capable of full-duplex operation at speeds up to 56 bitls using
an internal programmable baud rate generator (or optional external clock sources).
The USART supports the following functions
• Program-selectable synchronous/asynchronous modes
• Software reset
• Line break recognition and generation
• Special character recognition
• Selectable stop bits (1-, 1.5-, or 2-stop bits)
• Full modem control handshake lines (RTS, CTS, OSR, and OTR)
• "Local Loopback" and "Stick Parity" test features
724
SAB 79C401
Dual-Port Memory Controller (DPMC)
The OPMC provides RAM access control and an inter-processor interrupt mechanism that
permits two processors to share common RAM memory without the expense of dual-port
RAM. These features are used in developing network interface applications for PCs and
Integrated Voice/Oata Workstations (lVOWs).
Microprocessor Interface (MPI)
The MPI consists of an 8-bit non-multiplexed data bus that allows the IDPC to function
with a 12.5-MHz 80188 processor (or other similar microprocessor) with zero wait states.
Features
•
Data Link Controller
Full featured bit-oriented communication controller supporting HOLC, SOLC, LAPS,
LAPO, and OMI
Oata transfer rate: 2.048 Mbitls
32-byte receive FIFO and 16-byte transmit FIFO with programmable thresholds and
OMA ha:ndshakes
Multiple (four plus broadcast) address recognition modes
Multiplexed serial interface with up to thirty-one 8-bit channels or non-multiplexed
serial interface
Local and remote loopback modes
Transpare'nt mode
56 kbitls mode
• USART
Superset of Industry-Standard 8250 UART features
4-byte transmitlreceive FIFOs
Special character recognition (up to 128 programmable)
Synchronous mode provides a transparent serial data path
Local loopback mode
•
Dual-Port Memory Controller
•
Microprocessor Interface
•
Memory bus arbitrator provides dual-port access to standard low-cost static RAM
Programmable inter-processor interrupts support RAM-based inter-processor mailboxed
8-bit non-multiplexed data bus
Operates with 12.5-MHz 80188 processor with zero wait states
General Features
Compatible with PSS 79C30 OSC
CMOS technology, single +5-V supply
Power-down mode
68-pinPL-CC
Siemens Components, Inc.
725
I
I
Package Outlines
I
Package Outlin~
Plastic Dual-in-Line Package, P-DIP-8
Plastic Dual-in-Line Package, P-DIP-16
20 A 8 DIN 41870 T9
20 A 16 DIN 41870 T9
4 O.4max
0,4max
20.2.0,3-'---1"--
Approx. weight 0.7 g
Approx. weight 1.2 g
Plastic Dual-in-Line package, P-DIP-20
Ceramic Dual-in-Line package, C-DIP-20
20 A 20 DIN 41870 T9
20 A 20 DIN 41870 T9
2.54
-.l7.62'06
~::::::t
:--",.:=; ., "
~I:::[~
Approx. weight 1.5 g
Apprix. weight 1.7 g
1
10
25.4. 0.3
Dimensions in mm
Siemens Components, Inc.
IJ~,,,~
C
729
I
Package Outlines
Plastic Dual-in-Line Package, P-DIP-22
20 D 22 DIN 41870 T11
22
12
11
~_ _ _ 27.8_0.3 _ _ _~1~4mQx
Approx. weight 2.1 g
Ceramic Dual-in-Line Package, C-DIP-22
20 D 22 DIN 41870 T11
10.16.0.6
22
12
.. ,....,....,....
-----ii
1-o---....,27.8_o.7---~
Approx. weight 2.5 9
Siemens Components, Inc.
Dimensions In mm
730
Package Outlines
Plastic Dual-in-Line Package, P-DIP-24
20 B 24 DIN 41870 T10
24
13
12
O.4max
1-----31.9_04-----It--Approx. weight 2.5 g
Ceramic Dual-in-Line Package, C-DIP-24
20 B 24 DIN 41870 T10
. O.25~&'14
.
I
f---15.24to.6-J
24
o
13
D
12
1-----31.5_1.5-----il~
Approx. weight 3 g
Siemens Components, Inc.
Dimensions in mm
731
Package Outlines
Plastic Dual-in-Line Package, P-DIP-28
20828 DIN 41870 T10
i15.24t02=1
15
28
14
O.4max
f-----35.9_04-------H- - Approx. weight 3 g
Ceramic Dual-in-Line Package, C-DIP-28
20828 DIN 41870 T10
11:25:814
I
15.24.0.6--1
D
14
f------36.5_1.s--------<~
Approx. weight 3.5 g
Siemens Components, Inc.
Dimensions in mm
732
Package Outlines
Plastic Dual-in-Line Package, P-DIP-40
20 B 40 DIN 41870
no
. 0.2S· 0.1
,
14_03
40
J
1S.24·1.2~
21
20
0.4 max
t----------sO.9_0.5--------~,...~~
Approx. weight 5.9 g
Ceramic Dual-in-Line Package, C-DIP-40
20 B 40 DIN 41870
no
o.2s:R6~
j'
1S.24tO 6
21
40
D
''1 ................................ -
,......------~S1.S_1.5--------.,
Dimensions in mm
Approx. weight 6.8 9
Siemens Components, Inc.
733
Package Outlines
Piggyback
r---- -----51,3_,--------1
1-------31_,-------t.-J
40
rt--t-+
21
. .~ . . . . . . ++-t.+
+-t+
20
Dimensions in mm
Siemens Components, Inc.
734
Package Outlines
Index Marking
I
._._.+._._.
I
I
Dimensions In mm
Siemens Components, Inc.
735
I
Package Outlines
(similar to P-DSO-8)
24 A 8 DIN 41870 T16
14
8
B
-
(Small Outlines)
24 A 16 DIN 41870 T16
16
24 B 20 DIN 41870 T17
9
20
R
[1:.::)
Siemens Components. Inc.
8.8_0,3
11
B
736
Package Outlines
~------10,B----------1
I
-t--t--+--f~~'-+-'~
I
0,6 max
~-------12,4,----------
Dimensions in mm
Siemens Components, Inc.
I
737
Package Outlines
0,03 min
O,6max
D
D
D
D
Dimensions In mm
Siemens Components, Inc.
738
Packaging Rails
Packages: P-DSO-6j 8j 14j P-MIP-6-Gj 8-G
=
~
!:B§~_=isJlillE:;~~=,==,
E
53'"
3!O,l
N
"'
;;
~:
'
Packages: P-MIP-6j 8
~
4-4£=*
~ ~
i""~------------S31·2_---------------tl.~~19.8
~-
ANTISTATIC"
£
,
,
1
~
393_2
.. I'
I'
403_2------<--1'
S23·1----------------tl..~
Packages: P-DSO-20
I
Dimensions in mm
Siemens Components, Inc.
739
Packaging Rails
Packages: P-DIP-4; 6; 8; 14; 16; 18; 20
[I-
I
jt
I
I
I
I
I
I
I
I
I
I
I
t---t t--t r---t t---t t--j +--j
I
+
I-j
528_z
r-------38tz-----~
r-----'13x10=130 - - - - - I
Packages: C·DIP·14; 16; 18; 20
rE~~======================~j~tr--~~'-t-+'-~rI
~
+
~
+
I
r
r
l
~4-+~--j+I-t~~r~~I~~-'j
~
""'-~-----------528_z-------------.j-l 15~o.
L_-¥!rHH=r
L
13x10=130!-------<~-
Packages: C-DIP·24; 28; 40; 48
E
-+j\r""++-I-+-l--+~--J~I--t-+!---i+--!-+--l-r,-;-l-!-++-1-++--_++-~+--tt""j
.r:=------------------------------------.
5'28_Z--------------~j
-_...J
__
r----~100_z----I....,1
-= .
12
I'
r------358_z-------!..,..------BK12=156-------t..
-.j
Dimensions In mm
Siemens Components, Inc.
740
11:
20~O.s
Packaging Rails
1B
Packages: P-DIP-22
---t---=============1,...---==+--t=1
--==---==t-j
l==t-==------~~
_ _~_jt-----~
L..~O------.--------528_2------------
Packages:PL~C-28
17'.1
~~
==========~===:=JC~~. 113'21 .
--------528_2-----------,--
r.:I=i...[o-l
+
-~
=::::~::~~~~~::~::~~::~~::=52~8_=2.~~~~-1~1~:~~~~~_-_-_-_-_-_:J._I
J,$
1=!1...
..
t· IlE~NS
SOtO,S
+
ANTISTATIC
.. ~
Dimensions in mm
Siemens Components, Inc.
741
20,1 ~
Lri
~
Packaging Rails
Packages:PL-C~68
I.....- - - - - - - - - - - - 5 2 8 _ 2 ' - -"
- - - - - -1
----.1:
3tO.1
--1 r---
- ._._._...... ~SIEMENS
ANTISTATIC
..t.-- 1--+-'-'-I
_62tQ5
I
403_2
DimenSions in mm
Siemens Components, Inc.
742
Siemens Sales Office Listings
I
Siemens Components, Inc. _____________
Semiconductor Group
North American
Sales Offices _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
UNITED STATES
• Siemens Components, Inc.
2 Lowell Research Ctr. Dr.
Suite 105
Lowell, MA 01852
508/454-0113
• Siemens Components, Inc.
307 Fellowship Road
Suite 202
Mt. Laurel, NJ 08054
609/273-6677
• Siemens Components, Inc.
120 Wood Avenue South
Suite 606
Iselin, NJ 08830
201/603-0600
• Siemens Components, Inc.
6525 The Corners Parkway
Suite 206
Norcross, GA 30092
404/449-3981
• Siemens Components, Inc.
39209 W. Six Mile Rd.
Suite 209
Livonia, MI 48152
313/462-1195
• Siemens Components, Inc.
5600 North River Rd.
Suite 735
Rosemont, IL 60018
312/692-6000
• Siemens Components, Inc.
625 The City Dr. South
Suite 320
Orange, CA 92668
714/385-1274
• Siemens Components, Inc.
19000 Homestead Rd.
Cupertino, CA 95014
408/725-3566
• Siemens Components, Inc.
3003 LBJ Freeway, 11115
Dallas, TX 75234
214/620-2294
CANADA
• Siemens Electric Ltd.
1180 Courtney Park Drive
Mississauga, Ont. L5T 1P2
416/564-1995
• Siemens Electric Ltd.
3600 Billings Court, Suite 100
Burlington, Ont. L7N 3N6
416/333-3773
• Siemens Electric Ltd.
6143 4th Street SE. 117
Calgary, Alberta T2H 2H9
403/252-2278
• Siemens Electric Ltee.
7300 Trans Canada Highway
Pointe Claire, Que. H9R 4R6
514/695-7300
• Siemens Electric Ltee.
11500 rue Janelle
Drummondville, Que. J2C 3E5
819/472-1155
• Siemens Electric Ltd.
9825 45th Avenue
Edmonton, Alberta T6E 5C8
403/436-6640
• Siemens Electric Ltd.
109 IIsley Avenue, Unit 111
Dartmouth, N.S B3B 1S8
902/469-9791
• Siemens Electric Ltd.
333 Consortium Court
London, Ontario N6E 2S8
519/685-7282
• Siemens Electric Ltd.
108 Prospect Street, Suite 1
Fredericton, New Brunswick
E3B4T9
506/458-9788
• Siemens Electric Ltee.
366 rue St-Patrick
Lasalle, Que. H8N 2W7
514/365-3315
• Siemens Electric Ltd.
260 Hearst Way, Suite 306
Kanata, Ontario K2L 3H1
613/592-2477
• Siemens Electric Ltd.
106B - 701 Cynthia Street
Saskatoon, Saskatchewan
S7L 6B7
306/652-3101
• Siemens Electric Ltee.
128 - 1990 bout. Charest ouest
Ste-Fay, Que. G1 N 4K8
418/687-4524
• Siemens Electric Ltd.
109 Clyde Ave.
Donovans Industrial Park
P.O. Box 668
Mount Pearl, Nlld. A1N 2X1
709/364-5131
• Siemens Electric Ltd.
1034 rue King Est
Sherbrooke, Que. J 1G 1E4
819/563-9656
• Siemens Electric Ltd.
P.O. Box 1204
Timmins, Ont. P4N 7J5
705/267-7755
• Siemens Electric Ltd.
8687 Yukon Street
Vancouver, B.C. V5X 4T5
604/321-8687
• Siemens Electric Ltd.
1260 Border Street
Winnipeg, Manitoba R3H OM6
204/633-8655
• Siemens Electric Ltd.
654 Burnside Road West
Victoria, B.C. V8Z 1M8
604/727-6465
Issued by Integrated Circuit Division
2191 Laurelwood Road, Santa Clara, CA 95054 (408) 980-4500
Siemens Components, Inc.
Cl1989 Siemens Components, Inc.
Siemens Components, Inc. ____________
Semiconductor Group
U.S. Regional
Representatives ______________________
• ALABAMA
Interep Associates, Inc.
Huntsville
205/881-1096
Interep Associates, Inc.
Mobile
205/478-1036
• ARIZONA
Reptronix
Tempe
602/345-4580
• CALIFORNIA-Northern
Siemens Components, Inc.
Cupertino
408/725-3588
• CALIFORNIA-Southern
Centaur Corp.
Calabasas
818/704-1655
Centaur Corp.
Irvine
714/281-2123
Varigon, Inc.
San Diego
619/576-0100
• COLORADO
Lange Sales Inc.
Littleton
303/795-3600
• FLORIDA
Conley &Associates, Inc.
Oviedo
407/365-3283
• GEORGIA
Interep ASSOCiates, Inc.
Norcross
404/449-8680
• ILLINOIS
KMA Sales Co.
Arlington Heights
312/398-5300
• INDIANA
Electro Reps, Inc.
Indianapolis
317/842-7202
Electro Reps
Ft. Wayne
219/489-2682
• IOWA
AEM, Inc.
Marion
319/377-1129
• KANSAS
AEM, Inc.
Lenexa
913/888-0022
• MARYLAND
Micro-Comp., Inc.
Baltimore
301/844-5700
• MASSACHUSETTS
Siemens Components, Inc.
Lowell
508/454-0113
Anchor Engineering
Westborough
617/898-2724
• MICHIGAN
Enco Marketing, Inc.
Bloomfield Hills
313/338-8600
• MINNESOTA
Cahill, Schmitz & Cahill Inc.
St. Paul
612/646-7217
• MISSOURI
AEM, Inc.
Bridgeton
314/298-9900
• NEW JERSEY-Southern
See PENNSYLVANIAEastern
• NEW MEXICO
F. P Sales
Albuquerque
505/345-5553
• NEW YORK (Metro)
See NEW JERSEYNorthern
• NEW YORK (UPltltl)
Ossmann Associates, Inc.
Henrietta
7181359-1200
• NORTH CAROLINA
ADI
Smithfield
919/934-8138
ADI
Matthews
704/847-4323
• OHIO
ElectroniC Salesmasters
Beachwood
216/831-9555
• OKLAHOMA
CompTech Sales, Inc.
Tulsa
918/622-7744
• OREGON
Micro Sales, Inc.
Beaverton
503/645-2841
• PENNSYLVANIAEastern
Delta Technical Sales
Hatboro
• PENNSYLVANIAWestern
See OHIO
• SOUTH CAROLINA
See NORTH CAROLINA
• TENNESSEE
Interep Associates, Inc.
Greeneville
615/639-3491/3492
• TEXAS
CompTech Sales, Inc.
Irving
214/751-1181
CompTech Sales, Inc.
Austin
512/343-0300
CompTech Sales, Inc.
Houston
713/492-0005
• UTAH
Lange Sales Inc.
Salt Lake City
801/487-0843
• VIRGINIA
See MARYLAND
• WASHINGTON
Micro Sales, Inc.
Bellevue
206/451-0568
• WASHINGTON, D.C.
See MARYLAND
• WISCONSIN
KMA Sales Co.
Milwaukee
414/259-1771
215/957-0600
• NEW JERSEY-Northern
Emtec Sales, Inc.
East Hanover
201/428-0600
Issued by Integrated Circuit Division
2191 Laurelwood Road, Santa Clara, CA 95054 (408) 980-4500
Siemens Components, Inc.
@
1989 Siemens Components, Inc.
Siemens Components, Inc.
Semiconductor Group
U.S. Regional
Distributors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
• ALABAMA
Hall-Mark
Huntsville
• CONNECTICUT
Hall-Mark
Chesire
• MARYLAND
Hall-Mark
Columbia
• NEW YORK
Hall-Mark
Ronkonkoma
• TEXAS
Allied/Hall-Mark
Ft. Worth
817/265-9341
205/837-8700
203/271-2844
301/988-9800
516/737-0600
Marshall
Huntsville
wallin~ford
Marshall
Marshall
Silver Sf.rin~
716/425-3300
Hall-Mark
Dallas
Marshall
214/553-4300
205/881-9235
• ARIZONA
Hall-Mark
Phoenix
602/437-1200
Insight Electronics
Temrai
20312 5-3822
• FLORIDA
Hall-Mark
Orlando
3051855-4020
Cassel Berr~
407/830-58 5
301162 -11
• MASSACHUSETTS
Hall-Mark
Billerica
Houston
713/781-6100
Marshall
Wilmington
716/235-7620
Marshall
Phoenix
305/971-9280
508/658-0810
Lar~o
813 530-4543
Western Microtechnology
Burlington
4081432-4000
Citrus Heights
916/722-8600
Marshall
Waukesah
414/797-8400
Rancho. Cordova
916/635-9700
Western Microtechnology
~~~~~t-1660
Marshall
Alta Monte Springs
407/767-8585
St. petersbur~
813/573-139
Ft. Lauderdale
3051977-4880
• GEORGIA
Hall-Mark
Norcross
4041447-8000
Marshall
Norcross
404/923-5750
• CALIFORNIA-Southern • ILLINOIS
Hallmark
Advent Electronics
Chatsworth
Rosemont
818/773-4500
312/297-6200
San Diego
619/268-1201
Hall-Mark
Wood Dale
Irvine
121860-3800
7141727-6000
Marshall
Schaumburg
Insight Electronics
San Diego
619/587-0471
Irvine
7141727-2111
Agoura
8181707-2100
Marshall
San Diego
619/578-9600
Irvine
714/458-5301
Chatsworth
818/407-4100
Western Micro
~~~,¥8lJ~h
Orange
714/637-0200
San Diego
619/453-8430
• COLORADO
Hall-Mark
En81ewood
312/490-0155
• INDIANA
Advent Electronics
Indianafolis
317/87 -4910
Hall-Mark
Indianafolis
317/87 -8875
Marshall
Indianapolis
317/297-0483
• IOWA
Advent Electronics
Cedar RaC:ids
319/363- 221
• KANSAS
Hall-Mark
Lenexa
512/258-8848
Johnson City
6071798-1611
Pompano Beach
• CALIFORNIA-Northern
Hall-Mark
San Jose
Austin
Hauppau~e
516/273- 424
617/935-9777,
508/667-0902
602 829-1800
602/496-0290
Fairport
617/273-2800
Mass Comp, Inc.
West peabod6'
617/535-727
• MICHIGAN
Advent
Farmin~ton
Marshall
Carrollton
Rochester
2141233-5200
Summit Distributors
Buffalo
Austin
716/887-2800
512/837-1991
Rochester
Houston
716/334-8110
713/895-9200
EI Paso
• NORTH CAROLINA
Hall-Mark
Raleigh
915/593-0706
Harlington
919/872-0712
Hills
313/47 -1650
Hall-Mark
Livonia
313/462-1205
Marshall
Livonia
313/525-5850
• MINNESOTA
Hall-Mark
Eden Prairie
919/878-9882
Worthington
918/254-6110
503/629-2082
Marshall
Fairfield
• WISCONSIN
Hall-Mark
New Berlin
414/797-7844
• OREGON
Marshall
Beaverton
503/644-5050
609/235-1900
Western Microtechnology
Redmond
206/881-6737
• OKLAHOMA
Hall-Mark
Tulsa
314/291-4650
MI. Laurel
206/486-5747
Dayton
• NEW JERSEY
Hall-Mark
Fairfield
201/575-4415
• WASHINGTON
Marshall
Bothell
Marshall
Solon
513/898-4480
Marshall
Bridgeton
Marshall
Salt Lake City
801/485-1551
614/888-3313
216/248-1788
314/291-5350
801/972-1008
216/349-4632
Marshall
Plymouth
612/559-2211
• UTAH
Hall-Mark
W. Valley City
• OHIO
Hall-Mark
Solon
612/941-2600
• MISSOURI
Hall-Mark
Earth City
512/542-4589
Marshall
Raleigh
Marshall
Milpitas
408/942-4600
Western Microtechnology
Beaverton
• PENNSYLVANIA
Marshall
Pittsburgh
412/963-0441
2011882-0320
Mt. Laurel
609/234-9100
913/888-4747
Marshall
Lenexa
913/492-3121
30 1790-1662
Marshall, Thornton
303/451-8383
Issued by Integrated Circuit Division
2191 Laurelwood Road, Santa Clara, CA 95054 (408) 980-4500
Siemens Components, Inc.
c 1989 Siemens Components, Inc.
Issued by Integrated Circuit Division
2191 Laurelwood Road, Santa Clara, CA 95054 (408) 980-4500
Siemens Components, Inc.
Ordering No. M12T021
Printed in U.S.A. 5K/989/RRD/TS
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:07:29 16:53:23-08:00 Modify Date : 2017:07:29 17:24:52-07:00 Metadata Date : 2017:07:29 17:24:52-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:e40770c2-119b-7842-a1ef-20d29a397e04 Instance ID : uuid:6da22e49-f47f-a543-aff7-b9a90043b216 Page Layout : SinglePage Page Mode : UseNone Page Count : 748EXIF Metadata provided by EXIF.tools