1990_Signetics_PLD_Data_Handbook 1990 Signetics PLD Data Handbook
User Manual: 1990_Signetics_PLD_Data_Handbook
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INTEGRATED
CIRCUITS
Signetics
Programmable
Logic
Devices
Signetics
Philips Components
PHILIPS
Signetics
Programmable logic Devices
PLD
Data Handbook
1990
Programmable Logic
Devices
PHILIPS
Signetics reserves !he right to make changes, without notice, in !he products, including
circuits, standard cells, and/or software, dascribedorcontained herein in order to improve
design and/or performance. Signetics assumes no responsibility or liability for the use
of any of these products, oonveys no license or tide under any patent, oopyright, or mask
workrightto these products, and makes no representations orwarranties that these products are free from patent, oopyrigh~ or mask work right infringement, unless otherwise
specified. Applications that are described herein for any of these products are for illustrative purposes only. Signetics makes no representation orwarranty that such applications
will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICATIONS
Signetics Products are not designed for use in life support appliances, devices, or
systems where malfunction of a Signetics Product can reasonably be expected to result
in a personal injury. Signetics customers using or selling Signetics Products for use in
such applications do so at their own risk and agree to fully indemnify Signetics for any
damages resulting from such improper use or sale.
Signetics registers eligible circuits under
the Semiconductor Chip Protection Act.
© Copyright 1990 NAPC.
All rights reserved.
Signetics
Preface
Programmable Logic Devices
The 1990 Philips Components-Signetics PLD Data Handbook is loaded with information on new parts. Using the fastest technologies in the most innovative architectures,
today's system designer can pick from the largest selection of PLDs in the industry.
Some highlights of this handbook include the fastest silicon PLDs available (PHD16NS
and PHD4SN22}-at 5 nanoseconds! These devices make ideal decoders to squeeze
maximum performance from powerful microprocessors.
Designers using DRAM, VRAM and graphics will appreciate the speed and power of
the new line of sequencers which include the PLC415, PLC42VA12, PLUS405 and
PLUS1 05. These sequencers also make innovative bus and LAN controllers for emerging standard protocols. At last, the logical power of dual programmable arrays comes
forth in the PLUS 153 and PLUS173 devices-at 10 nanosecond propagation delays.
The PLC1SVSZ is the only zero power 2Q--pin device which can replace 16VS's! And
finally, our-7 and D speed PAL-type devices are the industry's fastest. For maximum
density in a truly compact system, the Programmable Macro Logic family now boasts
four members-the PML2552 and PLHS601 are added to the original PLHS501 and
PLHS502. The PML2552 is the PLD industry's first dense device to implement SCAN
test.
To complement the devices, AMAZE design software is offered through our Sales
Offices (see Section 11) and SNAP software is available for high level support. Read
about them under Product Support.
Expanding customer service has been an ongoing effort. Our Applications staff is available to answer your technical questions on PLD designs and our free computer Bulletin
Board, with 24-hour service, is at (SOO}451-6644.
New PLD users are encouraged to read the Introduction and ANS for an overview of
PLD ideas. More seasoned PLD users are encouraged to go through the PLD applications and PML applications atthe end olthe handbook to gain understanding and ideas
for new designs.
January 1990
iii
Signetics
Product Status
Programmable Logic Devices
DEFINITIONS
Data Sheet
Identification
Product Status
Definition
Objecl/w s".cI'''''~.n
formative or In DHign
This data sheet contains the design target Of goal
specHlcations for prodUC1 development. Speclficalions may
change In any manner without notice.
-1JIIrY s".cI6..~.n
Preproduction Product
This data shoot contains pt'eliminary data and
supplementary data will be published at a tater date.
Signatics r96erves the right to make changes at any time
without notice in order to irrprove design and supply the best
possble product.
Producl s".cI'",,'ion
Full Production
reserves the right to make changes at anytlmewilhout notice
In order to irTl)f0Y8 design and supply the best possible
This data sheet contains Final Specifications. Signetics
product.
January 1990
iv
Signetics
Contents
Programmable Logic Devices
Preface ............................................................................................. iii
Product Status ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. iv
Section 1 - General Information
Alphanumeric Index ............................................................................... 3
Selection Guide ................................................................................... 4
Ordering Information .............................................................................. 6
Section 2 - Introduction
What Is Signetics Programmable Logic ............................................................... 9
Quality and Reliability ............................................................................ 27
Section 3 - PAL@.Type Devices Data Sheets
Series 20
PLHS16L8AIB
PAL@-TypeDevices(16x64X8) ..............................................
PAL @-Type Devices
PLUS 16R8D/-7
(Includes: PLUS16L8D/-7, PLUS16R4D/-7, PLUS16R6D/-7, PLUS16R8D/-7) ...........
PHD16N8-5
Programmable High Speed Decoder (16 x 16 x 8); 5ns ..............................
PLHS18P8A1B
PAL@-TypeDevices .........................................................
PLC18V8Z11
PAL@-Type Devices .........................................................
Series 24
1OH20EV8/1 0020EV8
ECL PAL@-Type Devices .....................................................
PLUS20R8D/-7
39
46
60
68
75
87
PAL@-TypeDevices
(Includes: PLUS20L8D/-7, PLUS20R4D/-7, PLUS20R6D/-7, PLUS20R8D/-7) .......... 101
Series 68
PHD48N22-7
Programmable High Speed Decoder (48 x 73 x 22); 7.5ns .......................... 115
Section 4 - Programmable Logic Array Devices Data Sheets
Series 20
PLSl53/A
Programmable Logic Arrays (18 x 42 x 10); 40130ns ............................... 127
PLUS153BID
Programmable Logic Arrays (18 x 42 x 10); 15/12ns ............................... 134
PLUS 153-1 0
Series 24
Programmable Logic Array (18 x 42 x 10); 10ns .................................. 141
PLS173
Programmable Logic Array (22 x 42 xl 0); 30ns .......•.......................... 148
PLUS173BID
Programmable Logic Arrays (22 x 42 x 10); 15/12ns ...•........................... 154
PLUS173-10
PLHS473
Programmable Logic Array (22 x 42 x 10); 10ns .................................. 161
Programmable Logic Array (20 x 24 x 11); 22ns ................................... 168
PLHS473S
Series 28
PLS100/101
Programmable Logic Array (20 x 24 x 11); 25ns ................................... 174
Janumy 1990
Programmable Logic Arrays (16 x 48 x 8); 50ns ................................... 181
v
Signetics Programmable Logic Devices
Contents
Section 5 - Programmable logic Sequencer Devices Data Sheets
Series 20
PLS155
Programmable Logic Sequencer (16 x 45 x 12); 14MHz
PLS157
Programmable Logic Sequencer (16 x 45 x 12); 14MHz
PLS159A
Programmable Logic Sequencer (16 x 45 x 12); 18MHz
Series 24
PLS167/A
Programmable Logic Sequencers (14 x 48 x 6); 14, 20MHz .......................
PLS168/A
Programmable Logic Sequencers (12 x 48 x 8); 14, 20MHz .......................
PLS179
Programmable Logic Sequencer (20 x 45 x 12); 18MHz ..........................
CMOS Programmable Logic Sequencer (42 x 105 x 12); 25MHz ...................
PLC42VA12
Series 28
PLC415-16
Programmable Logic Sequencer (17 x 68 x 8); 16MHz ...........................
PLS105/A
Programmable Logic Sequencers (16 x 48 x 8); 14, 20M Hz .......................
PLUS105-40
Programmable Logic Sequencer (16 x 48 x 8); 40MHz ...........................
PLUS105-55
Programmable Logic Sequencer (16 x 48 x 8); 55MHz ...........................
PLUS405-37/-45
Programmable Logic Sequencers (16 x 64 x 8); 37, 45MHz .......................
PLUS405-55
Programmable Logic Sequencer (16 x 64 x 8); 55MHz
329
344
Section 6 - Programmable Macro Logic Devices Data Sheets
PLHS501
Programmable Macro Logic ............................................... .
PLHS502
Programmable Macro Logic ............................................... .
PLHS601
Programmable Macro Logic ............................................... .
PML2552
Programmable Macro Logic ............................................... .
361
372
384
395
191
202
213
223
234
245
256
275
294
305
317
Section 7 - Military Products
Military Selection Guide ................................................... .
417
Section 8 - Development Software
AMAZE - Automatic Map and Zap Equations Design Software .................... .
SNAP - Synthesis Nellist Analysis and Program Software ........................ .
SNAP Data Sheet ....................................................... .
Device Programmer Reference Guide
421
425
427
429
Section 9 - Application Notes
PLD Application Notes
AN7
Single Chip Multiprocessor Arbiter .......................................... .
AN8
Introduction to Signetics Programmable Logic ................................. .
ANll
PLD Programmable Retriggerable One-Shot .................................. .
AN14
Latches and Flip-Flops with PLS153 ........................................ .
ANt5
PLS159 Primer ......................................................... .
ANt8
Schmitt Trigger Using PLS153 and PLS159 ................................... .
AN21
9-Bit Parity Generator/Checker with PLS153/153A ............................. .
AN23
PLS 168/168A Prim er ..................................................... .
AN24
PLS173asa 10-BitComparator, 74LS460 ....................................
AN26
PLHS18P8A Primer ......................................................
AN27
PLHS473 Primer. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN28
High-Speed 12-Bit Tracking AID Converter Using PLS179 .. ... .. .. .. . .. .. ... .....
PML Application Notes
AN29
PLHS501 Programmable Macro Logic Primer ..................................
PLHS501 Application Notes, Vol. 1: DeSigning with Programmable Macro Logic
Chapter 1
Introduction to PML Design Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Performance ............................................................
NAND Gate Flip-Flops ,...................................................
Chapter 2
Functional Fit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3
Design Examples .................................... ,...................
Chapter 4
Successor Architectures .................... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
January 1990
vi
435
447
459
463
476
487
495
501
514
520
529
537
547
562
562
569
572
575
580
Signeties Programmable Logic Devices
Contents
3upjJ(Jrt :,sSLiGS • . • • . • . • . . . . . . . • . • . . . . . . . • • • . • . • • • • • • . • • • • . . . . • • • • • . . . • • . •
PLHS501 Examples Using AMAZE Revision 1.6 ................................
Simple Gate Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-Bit Barrel Shifter .......................................................
12-Bit Comparator with Dual 1-01-8 Decoders ................................ .
8-Bit Carry Look-Ahead Adder ............................................. .
32-to-5-Bit Priority Encoder ............................................... .
8-Bit Shift Register with Sequence Detector ................................... .
4-Bit Synchronous Counter ............................................... .
PLHS501 Application Notes, Vol. 2: Designing with Programmable Macro Logic
Chapter 1
Introduction ............................................................ .
Chapter 2
PLHS501 Review ....................................................... .
Flip-Flop Basics ........................................................ .
Chapter 3
Notation ............................................................... .
Flip-Flop Merging ....................................................... .
Chapter 4
VME Bus Examples ...................................................... .
Omnibyte VSBC20 Mailbox Interrupt Structure ................................. .
VME Bus EPROM Interface ............................................... .
Chapter 5
Micro Channel Interface .................................................. .
Chapter 6
NuBus Interface ......................................................... .
Chapter 7
Nuggets ............................................................... .
Data Bus Parity ......................................................... .
Data Bus Operations ..................................................... .
PLHS502 Application Notes, Vol. 1: Designing with Programmable Macro Logic
Chapter 1
Introduction ............................................................ .
Chapter 2
Development Support .................................................... .
Chapter 3
Capacity and Partitioning Considerations ..................................... .
State Machine Design .................................................... .
Chapter 4
Additional Design Guidelines .............................................. .
Chapter 5
Additional PLHS501 Applications ........................................... .
Chapter 6
Chapter 7
Advanced Flip-Flop Merging ............................................... .
Programmable Logic Design and Application Notes
Introduction ............................................................ .
Acknowledgements ...................................................... .
AMAZE Software ........................................................ .
Product Section Introduction ..................................................................... .
PLA Devices ........................................................... .
Chapter 1
Signetics PLUS153D ..................................................... .
Signetics PLUS173D ..................................................... .
The PLHS473 .......................................................... .
Chapter 2
PAL-Type Devices ...................................................... .
Signetics PLHS18P8B .................................................... .
The PLUS 16L8D and -7 .................................................. .
The PLUS16R8D and -7 .................................................. .
The PLUS20L8D and -7 .................................................. .
The PLUS20R8D and -7 .................................................. .
The PLC18V8Z ......................................................... .
Chapter 3
Sequencer Devices ...................................................... .
Introduction ............................................................ .
State Equation Tutorial ................................................... .
The PLUS105 .......................................................... .
The PLS155 ........................................................... .
The PLS157 ........................................................... .
The PLS159A .......................................................... .
ThePLS167A
The PLS168A
Chapter 5
Chapter 6
January 1990
vii
581
582
582
585
591
594
597
602
608
612
613
615
615
615
621
621
626
633
638
644
644
651
652
654
656
657
668
670
689
691
691
691
691
692
692
692
692
696
696
698
699
700
701
701
703
703
704
704
707
708
709
710
711
Signetics Programmable Logic Devices
Contents
The PLS179 ............................................................
The PLUS405 ...........................................................
Application Section Introduction. . . .. . . . .. . . .. . . . .. . . . . . . . . .. . . .. . . . .. . . . . . . . . . . . . . . . . . .. . . . . . .. . . .
Chapter 4
Microprocessor Interfacing w~h Signetics PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Part~ioning ..... . . . . . .. . . . . . . . .. . . . .. . . . . . . . . . . . . .. . . . .. . . . . . . . .. .
Bus Size Decoding for the 68020 - PLUS18P8B ...............................
Interfacing to SPARC - PLUS20L8-7 ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The 80386 Pipeline Decoder - PLUS153D .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68030 Address Decoding - PLUS173D ......................................
The 29000, SRAM and the PLUS20L8D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Handler - PLS179 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCSI Target Interface - PLS105A and PLUS153B .. .. .. .. .. .. ... . . . .. .. ... .....
Introduction. . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . .. . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmer's Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbitration Software Sequence .........................................
RESELECT Software Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRANSFER Software Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DISCONNECT Software Sequence .....................................
Hardware Description ................................................
Chapter 5
Communications using PLDs ...............................................
The CCITT V2.7 Scrambler - PLC18V8Z ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Novel Speech Synthesizer - PLS 159A .....................................
CCITT Forward CRC Polynomial- PLUS405 ................................. ,
Chapter 6
Instrumentation ..........................................................
Heart Beat Mon~or - PLS159A, PLS168A and PLS153 ..........................
The Pulse Width Monitor - PLS168 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Scope Trace Sweep Circuit - PLS153 and PLS155 .............................
Chapter 7
General Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Motor Stepper Controller with the PLS155 .....................................
Chapter 8
Security Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Programmable Alarm System - PLS168 ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
712
713
715
715
715
715
716
717
721
725
727
730
735
735
735
735
736
737
737
737
737
738
750
750
752
755
757
757
764
769
772
772
776
776
Section 10 - Package Outlines
A
Plastic Leaded Chip Carrier ................................................
F
Ceramic Dual-In-Line .....................................................
FA
Ceramic Dual-In-Line with Quartz Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LA
Ceramic Leaded Chip Carrier with Quartz Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
N
Plastic Dual-In-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
785
788
790
792
793
Section 11 - Sales Offices
Office Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
799
January 1990
viii
Signetics
Section 1
General Information
Programmable Logic Devices
INDEX
Alphanumeric Index ................................................. 3
Selection Guide .................................................... 4
Ordering Information ..............................•................. 6
Alphanumeric Index
Signetics
Programmable Logic Devices
AN7
AN8
AN11
AN14
AN15
AN18
AN21
AN23
AN24
AN26
AN27
AN28
AN29
PHD16N8-5
PHD48N22-7
PLC18V8Z11
PLC42VA12
PLC415-16
PLHS16L8A1B
PLHS18P8A1B
PLHS473
PLHS473S
PLHS501
PLHS502
PLHS601
PLS100/101
PLS105/A
PLS153/A
PLS155
PLS157
PLS159A
PLS167/A
PLS168/A
PLS173
PLS179
PLUS16R8D/-7
PLUS20R8D/-7
PLUS105-40
PLUS105-55
PLUS153B/D
PLUS153-10
PLUS173B/D
PLUS173-10
PLUS405-37/-45
PLUS405-55
PML2552
1OH20EV8/10020EV8
January 1990
Series
Series
Series
Series
Series
Series
Series
Series
Series
20
68
20
24
28
20
20
24
24
Series 28
Series 28
Series 20
Series 20
Series 20
Series 20
Series 24
Series 24
Series 24
Series 24
Series 20
Series 24
Series 28
Series 28
Series 20
Series 20
Series 24
Series 24
Series 28
Series 28
Series 24
Single Chip Multiprocessor Arbiter ........................................ 435
Introduction to Signetics Programmable Logic ............................... 447
PLD Programmable Retriggerable One-Shot ................................ 459
Latches and Flip-Flops with PLS153 ...................................... 463
PLS159 Primer ....................................................... 476
Schmitt Trigger Using PLS153 and PLS159 ................................. 487
9-8it Parity Generator/Checker with PLS 153/153A ........................... 495
PLS 168/168A Primer ................................................... 501
PLS173 asa 10-BitComparator. 74LS460 ................................. 514
PLHS18P8A Primer .................................................... 520
PLHS473 Primer ...................................................... 529
High-Speed 12-Bit Tracking AID Converter Using PLS179 ..................... 537
PLHS501 Programmable Macro Logic Primer ................................ 547
Program mabie High-Speed Decoder (16 x 16 x 8); 5ns ......................... 60
Programmable High-Speed Decoder (48 x 73 x 22); 7.5n5 ..................... 115
PAL@-TypeDevices ................................................... 75
CMOS Programmable Logic Sequencer (42 x 105 x 12); 25Mfl7
.. ?S6
?I!,
Programmable Logic Sequencer (17 x 68 x 8); 1GMfll ..
PAL@-Type Devices (16 x 64 x 8) .... . . . . . . . . . . . . .
. . 39
PAL ®-Type Devices ................. . ............................... 68
Programmable Logic Array (20 x 24 x 11); 22ns .............................. 168
Programmable Logic Array (20 x 24 x 11); 25n5 .............................. 174
Programmable Macro Logic ............................................. 361
Programmable Macro Logic ............................................. 372
Programmable Macro Logic ............................................. 384
Programmable Logic Arrays (16 x 48 x 8); SOns .............................. 181
Programmable Logic Sequencers (16 x 48 x 8); 14. 20MHz .................... 294
Programmable Logic Arrays (18 x 42 x 10); 40/30ns .......................... 127
Programmable Logic Sequencer (16 x 45 x 12); 14MHz ....................... 191
Programmable Logic Sequencer (16 x 45 x 12); 14MHz ....................... 202
Programmable Logic Sequencer (16 x 45 x 12); 18MHz ....................... 213
Programmable Logic Sequencers (14 x 48 x 6); 14. 20MHz .................... 223
Programmable Logic Sequencers (12 x 48 x 8); 14. 20MHz .................... 234
Programmable Logic Array (22 x 42 x 10); 30ns ............................. 148
Programmable Logic Sequencer (20 x 45 x 12); 18MHz ....................... 245
~~: =~~~: ~:~:~:: ::::::::::::::::::::::::::::::::::::::::::::::::::'1~~
Programmable Logic Sequencer (16 x 48 x 8); 40MHz ........................ 305
Programmable Logic Sequencer (16 x 48 x 8); 55MHz ........................ 317
Programmable Logic Arrays (18 x 42 x 10); 15112ns .......................... 134
Programmable Logic Array (18 x 42 x 10); 10ns ............................. 141
Programmable Logic Arrays (22 x 42 x 10); 15/12ns .......................... 154
Programmable Logic Array (22 x 42 xl 0); 10ns ............................. 161
Programmable Logic Sequencers (16 x 64 x 8); 37. 45MHz .................... 329
Programmable Logic Sequencer (16 x 64 x 8); 55MHz ........................ 344
Programmable Macro Logic ............................................. 395
EeL PAL ®-Type Devices ............................................... 87
3
Signefics
Selection
Guide
Programmable Logic Devices
SIGNETICS
PART NUMBER
ARCHITECTURE
(INPUTS x TERMS
X OUTPUTS)
TOTAL
INPUTS
LOGIC
PACKAGE (I Dedicated) TERMS
INTERNAL STATE
REGISTERS
(I Dedicated)
OUTPUTS
C, I/O, R, R UO
tPD(MBx)
'MAX
Icc (Max)
PAL® -TYPE DEVICES
PLUS16L8-7
lSX64X8
2O-Pin
16(10)
64
0
2 C, S 00
7.5ns
PLUS16R4-7
16X64X8
2O-Pin
16(8)
64
4(0)
4 VO,4R
7.5ns
74MHz
180mA
PLUS16R6-7
16X64X 8
2O-Pin
lS(8)
64
6(0)
2 va, SR
7.5ns
74MHz
180mA
PLUS16R8-7
16X64X8
2O-Pin
lS(8)
64
8 (0)
8R
PLUS16L8D
16X64X8
2O-Pin
16(10)
64
0
2C,SIIO
10ns
PLUS16R4D
16X64X8
2O-Pin
lS(8)
64
4(0)
4 VO,4R
10ns
60MHz
180mA
PLUSl6RSD
lSXS4X8
2O-Pin
16(8)
64
6(0)
2 VO,SR
10ns
60MHz
180mA
PLUS16R8D
lSX64X8
2O-Pin
16(S)
64
8 (0)
8R
PLUS2OL8-7
2OX64X8
24-Pin
20(14)
64
0
2C,SIIO
7.5ns
PLUS2OR4-7
2OX64X8
24-Pin
20(12)
64
4 (0)
4 VO,4R
7.5ns
74MHz
210mA
PLUS20R6 7
2OX64X8
24-Pin
20(12)
64
S (0)
2110,6 R
7.5ns
74MHz
210mA
PLUS2OR87
2OX64X8
24-Pin
20(12)
64
8 (0)
SR
74MHz
210mA
PLUS2OL8D
2OX64XS
24-Pin
20(14)
64
0
2C,SIIO
10ns
PLUS2OR4D
2OX64X8
24-Pin
20 (12)
64
4 (0)
4 VO,4R
10ns
60MHz
210mA
PLUS20RSD
2OX64XS
24-Pin
20 (12)
64
S (0)
2 VO, SR
10ns
60MHz
210mA
PLUS2OR8D
2OX64X8
24-Pin
20 (12)
64
8 (0)
8R
60MHz
210mA
PLHS1SL8A
16XS4X8
2O-Pin
16(10)
64
0
2C,600
20ns
PLHS1SL8B
16X64XS
2O-Pin
lS (10)
64
0
2C,600
15ns
155mA
PLHS1SP8A
18X72X8
2O-Pin
18 (10)
72
0
81/0
20ns
155m!\
155mA
180mA
74MHz
180mA
180mA
60MHz
180mA
210mA
210mA
155mA
PLHS1SPSB
lSX72XS
2O-Pin
lS(10)
72
0
SilO
15ns
PHD16N8-5
16X16xS
2O-Pin
lS(10)
16
0
2 C, 6 00
5ns
180mA
PHD48N22-7"
48X73X22
68-Pin
48(36)
73
0
10C,1200
420mA
PLC1SV8Zl18VSZI
lSX74XS
2O-Pin
lS(S)
74
S (0)
Svaried
7.5ns
35,40ns
21MHz
l00~
lmAIMHz
1OH2OEVSI1 002OEVS"
2OX90XS
24-Pin
20(12)
PLS1001101
lSX48XS
28-Pin
PLS153
18X42Xl0
2O-Pin
90
0
8 varied
4.5ns
lS(16)
48
18(8)
42
222MHz
0
8C
50ns
170mA
0
10VO
40ns
155mA
230mA
PLA
PLS153A
lSX42Xl0
2O-Pin
lS(8)
42
0
10110
30ns
155mA
PLUSl53B
18X42Xl0
2O-Pin
18(8)
42
0
10110
15ns
200mA
PLUSl53D
18X42Xl0
2O-Pin
18(8)
42
0
10VO
12ns
200mA
PLUSl53-10"
lSX42X10
2O-Pin
18(8)
42
0
10110
10ns
200mA
PLS173
22X42X10
24-Pin
22(12)
42
0
10VO
30ns
170mA
PLUS173B
22x42x10
24-Pin
22(12)
42
0
10110
15ns
200mA
200mA
PLUSl73D
22X42Xl0
24-Pin
22(12)
42
0
10110
12ns
PLUSl73-10"
22X42x10
24-Pin
22(12)
42
0
10110 .
10ns
200mA
PLHS473
2OX42X11
24-Pin
20(11)
24
0
2C,911O
22ns
155mA
PLHS473S"
2OX42X11
24-Pin
20 (11)
24
0
2 C, 9 00
25ns
155mA
January 1990
4
Signetics Programmable Logic Devices
Selection Guide
SIGNETICS
PART NUMBER
I
ARCHITECTURE
(INPUTS x TERMS
X OUTPUTS)
I'
PACKAGE
.w.n., LOGIC ,........
~.-.~.-,
REGISTERS
INPUTS
(I Dedicated)
TERMS
(# Dedicated)
OUTPUTS
C. VO. R. R 110
I
tpo(Max)
I
fMAX
I
Icc (Max)
PLS
PLS105
22X48X8
28-Pin
22 (16)
48
6 (6)
8R
14MHz
180mA
PLS105A
22X48X8
28-Pin
22(16)
48
6 (6)
8R
20M Hz
180mA
PLS105-40
22X48X8
28-Pin
22(16)
48
6(6)
8R
40MHz
200mA
PLS105-55"
22X48X8
28-Pin
22(16)
48
6 (6)
8R
55MHz
200mA
PLUS405-37
24X64X8
28-Pin
24 (16)
64
8(8)
8R
37MHz
225mA
PLUS405-45
24X64X8
28-Pin
24(16)
64
8(8)
8R
45MHz
225mA
PLUS405-55"
24X64X8
28-Pin
24(16)
64
8 (8)
8R
55MHz
225mA
PLS155
16X45X12
2O-Pin
16(4)
45
4(0)
8 VO, 4 R I/O
50ns
14MHz
190mA
PLS157
16X45X12
2O-Pin
16 (4)
45
6(0)
6 VO, 6 R 110
50ns
14MHz
190mA
PLS159A
16X45X 12
20-Pin
16 (4)
45
8(0)
4 VO, 8 R I/O
35ns
18MHz
190mA
PLS167
22X48X6
24-Pin
22 (14)
48
8(6)
6R
14MHz
1SOmA
PLS167A
22X48X6
24-Pin
22 (14)
48
8 (6)
6R
20MHz
180mA
PLS168
22X48X6
24-Pin
22(12)
48
10(6)
8R
14MHz
1SOmA
PLS168A
22X48X6
24-Pin
22(12)
48
10 (6)
8R
20MHz
1SOmA
PLS179
20X45X12
24-Pin
20(8)
45
8 (0)
4 VO, 8 R I/O
35ns
18MHz
210mA
PLC42VA1r
42X105X12
24-Pin
42(10)
105
10 (0)
10CorRVO, 2 VO
35ns
25MHz
25X68X8
28-Pin
25 (17)
68
8 (8)
8R
PLC415-16
9OmA'
10~
SOmA
PMUM
PLHS501
104X 116 X24
52-Pin
24
116
0
16C,8 VO
22ns
PLHS502
128X144X24
68-Pin
24
144
16(16)
16CorR,
81!OorRVO
20ns
PLHS601"
68X134X24
68-Pin
28
134
0
12C,121/0
20ns
PML2552"
185 X 226 X 24
68-Pin
29
226
36(20)
24 C, 16 R, 161/0
40,50ns
PAL-Type = Programmable Array LogiC (Fixed OR Array)-Type
PHD = Programmable High-Speed Decoder
P LA = Programmable Logic Array
PLS = Programmable Logic Sequencer
PML = Programmable Macro Logic
OUTPUTS:
C = Combinatorial output
R = Registered output
I/O = Combinatorial 1/0
R I/O = Registered 1/0
NOTES:
fMAX = 1/(tlS + icKO) worst case
• Measured at 15MHz (TTL input level)
•• Under development
PAL is a trademark of AMD/MMI.
PML is a trademark of Philips Components-Signetics.
January 1990
5
295mA
50MHz
370mA
340mA
5O,33MHz
100mA
Signetics
Ordering
Information
Programmable Logic Devices
Signetics Programmable Logic Devices
may be ordered by contacting enher the
local Signetics sales office, Signetics representatives or authorized distributors. A
complete listing is located in the back of
this handbook.
Table 1 provides part number definition for
Signetics PLDs. The Signetics part number system allows complete ordering information to specnied in the part number.
The part number and product description
is located on each data sheet.
Milnary versions of these commercial
products may be ordered. Please refer to
the military products data handbook for
complete ordering information.
New Signetics PLD Pan Numbering System
I
P(L)
xx
yyyy
z
Package Designator
F - 20-, 24-, 28-Pin CERDIP DIP
N - 20-, 24-, 28-Pin Plastic DIP
A - 20-, 28-lead Plastic Leaded Chip Carrier
FA - 20-, 24-Pin CERDIP DIP with Quartz Window
Performance Indicator
(May be blank, A, B, D, etc. to designate speed variations in
basic part.)
Basic Part Number
(3 to 8 characters)
(e.g., 100, 105, 153, 168,173,18P8, 42VA12)
ProcesslArchnectIJre Indicator
S - Bipolar Junction Isolated Schottky - Nichrome fuses
C - CMOS - EPROM cells
HS - High Speed Bipolar Oxide Isolated - Vertical Fuse
US - High Speed Bipolar Oxide Isolated - Lateral Fuse
HD - High Speed Decoder
ML - Macro Logic
(Blank for ECL devices)
Indicator for Signetics Programmable Logic
(Can be either P, PL, or blank)
(P for PHD and PML and blank for ECL devices)
January 1990
6
Signetics
Section 2
Introduction
r-
Programmable logic Devices
INDEX
What is Signetics Programmable Logic .................................. 9
Quality and Reliability .................................•............ 27
Signetics
Introduction
Signetics
Programmable Logic
Programmable Logic Devices
WHAT IS PROGRAMMABLE
LOGIC
In 1975, Signetics Corporation developed
a new product family by combining its
expertise in semi-custom gate array
products and fuse-link Programmable
Read Only Memories (PROMs). Out of
this marriage came Signetics Programmable Logic Family. The PLS100 FieldProgrammable Logic Array (FPLA) was
the first member of this family. The FPLA
was an important industry first in two
ways. First, the ANDIOR/INVERT arch i-
PR
R
Op
STATE
REGISTER
NOTES:
1. P, C, N, F and PIE are user-prograrrmable connections.
Figure 1. High Speed Sequencer
January 1990
9
tecture allowed the custom implementations of Sum of Product logic equations.
Second, the three-level fusing allows
complete flexibility in the use of this device
family. All logic interconnections from
input to output are programmable.
Signelics Programmable Logic Devices
Introduction
Signetics Programmable Logic
Table 1. PLD Product Family
PART NUMBER
TYPE
CONFIGURATION
2O·PIN
PHD16N8
PLSI53/153A
PLUSI53B1153D/I53-10
PLSI55-159A
PLSI55
PLS157
PLSl59A
PLHSI8P8AlB
PLHS16l8A1B
PLC18V8Z11
PLUS16L8D/-7
PLUS16R4D/-7
PLUS16R6D/-7
PLUS16R8D/-7
PHD
PLA
PLA
PLS
PLS
PLS
PLS
PAL-Type
PAL-Type
PAL-Type
PAL-Type
PAL-Type
PAL-Type
PAL-Type
PLS167/A
PLS
PLSl68/A
PLS
PLS173/PLUS173B1DI-l0
PLSI79
PLHS473
PLC42VA12
PLUS20LBD/-7
PLUS20R4D/-7
PLUS20R6D/-7
PLUS20R8D/-7
PLA
PLS
PLA
PLS
PAL-Type
PAL-Type
PAL-Type
PAL-Type
PLSI 00/1 01
PLSI 05/105A1PLUSI 05
PLA
PLS
PLUS405
PLS
PLHSSOI
PLHSS02
PLHSSOI
PML2552
PHD48N22
PML
PML
PML
PML
PHD
12-1nputl8-Outpul
18-1nputll0-0utpUI- 42-Tenn
18-1nputll!H)utput - 42-Tenn
16-1 nputl12-Output - 45-Tenn
4 Registered Outputs
6 Registered Outputs
8 Registered Outputs
18-1nputll0-0utput - 72-Tenn
16-1nputl8-Output - 64-Tenn
16-1nputt8-Output-72-Tenn
16-1nputl8-Output-72-Tenn
16-1nputl4-0utput.4 Registers
16-1nputl5-Output.6 Registers
16-1nputl8-0utput.8 Registers
24·PIN
14-1nputl6-0utput- 48-Tenn
8--Bit State Registers
6-Output Registers
12-1nputl8-0utput - 48-Tenn
1O-Bil State Registers
8-Output Registers
22-1nputl1 !H)utput - 42-Tenn
22-1nputll0-0utput - 42-Term
2O-Inputill-Outpul- 24-Tenn
42-1nputlI2-OutpUI. 10 Registers
2O-Inputl8-0utpul
2O-Inputl4-0utput
20-1 nputl6-0utput
2O-Inputl8-Output
28-PIN
16-lnputl8-0utput - 48-Tenn
16-1nputl8-0utput - 48-Tenn
6-Bit State Register
8-Output Registers
16-1nputl8-0utpul - 64-Tenn
8-Bit State and Output Registers
52-, 68-PIN
January 1990
32-1nputl24-Output-II6-Tenn
32-1nputl24-Output-I44-Term
4O-Inputl24-Output-I50-Term
55-1nputl24-Output- 226-Term
48-1nputl22-OutpUI
10
Signetics Programmable Logic Devices
Introduction
Signetics Programmable Logic
o.
>-------L.Q1lo
Figure 2. PLUS153 20·Pln Functional Diagram
January 1990
11
Signetics Programmable Logic Devices
Introduction
Signetics Programmable Logic
Xo=AB+C"D+BU
in each equation simply becomes a direct entry
into the Logic Program Table. The following example illustrates this straightforward concept:
PLD LOGIC SYNTHESIS
No intermediate step is required to implement
Boolean Logic Equationswith PLDs. Each term
X,=}i;B + C"D + EFG
POLARITY
T -y- -,- 'L'H..L ...L. ...L.
-L.. -L.. -L..";"
AND
P-Terms
Po = AB
P, = CD
P2 = BD
P3 = AB
P4 = EFG
XO=PO+P,+P2
X,
= P3 + P, + P4
TERM
;-
,.
;- ;-
5
4
3
2
,. ,.
,
0
9
,
"8
-
7
0
l
-.2
0
2
,
2
2
2
2
2
2
2
3
4
5
6
7
2
3
A
W
_.,..
,
0
__
.
.
76543210
H
l
44
45
46
47
PIN
NQ
-6 -5 -4 -3 -2
H
2
3
4
c:;;
-------OUTPUTF.
•_
'T I
INPUT(lm )
H
H
B
A
H
-4
H
l
H
5
C
6
D
- ··
A
A
H
.....
="'"
••
""""'.--
r-
7
E
•
9
F
G
A
A
A
, , , , , , , ,
,
•
0
2
3
5
7
6
x, Xc
...J W
Ill:;
:!!:«
a:Z
~
T8019108
Figure 3. Field Programmable Logic Array
A
B
C
Xo
E
F
G
Figure 4. Equivalent Fixed Logic Diagram
JanuBIY 1990
X,
D
12
X,
=liB +t:Il+ EFG
Signetics Programmable Logic Devices
Signetics Programmable Logic
In the previous example, the two Boolean Logic
equations were broken into Product terms.
Each P-term was then programmed into the
P-tenn section of the PLA Program Table. This
was accomplished in the following manner:
Introduction
Step 1
Select which Input pins 10 - 115 will correspond to the input variables. In this case
A - G are the input variable names. 16 through
10 were selected to accept inputs A - G respectively.
I1:
INPUT(lm)
=r=:I~~<[H
.-~--~OUTPUT Fp
TERM
7
5
4
3
"
1
0
••
"
45
PIN
NO.
6
2
2
4
5
6
7
8
9
ABCDEFG
Figure 5
Step 2
This P-term translates to the Program Table by
selecting A = 16 = Hand B = 15 = H and entering
the information in the appropriate oolumn.
Transfer the Boolean Terms to the PLA
Program Table. This is done simply by defining
each!enn and entering iton the Program Table.
e.g., Po
= AB
P, = CD
PIN
NO
2
2
:2
2
2
3
2
4
5
6
3
6
7
7
5
ABC
Figure 6
January 1990
This term is defined by selecting C = 14 = Land
D = 13 = H, and entering the data into the
Program Table. Continue this operation until all
P-terms 'are entered into the Program Table.
13
F
G
6
Signetics Programmable Logic Devices
Signetics Programmable Logic
Introduction
Step 3
Select which output pins correspond to
each output function. In this case Fa = Pin 18
=><0. and F, = Pin 17 = X"
T""T'~L~;'IT-
AND
;TERM
5
,
., ,. ., .,, .,
3
4
INPUT(lm)
- ,-.-0
-9 "8 -7 -6 -5 -4 -3
a
2
..L....I....I..iR..L...L...L. _
H
0
L
H
H
H
2
0
2
,
2
2
2
2
2
2
2
3
4
5
6
7
2
5
4
3
2
•_
._
1
0
=
..,..---, , , , , , , ,
3
4
5
6
7
8
9
A
B
C
0
E
F
G
0
W
6
H
••
r-
PIN
NO
7
H
L
H
'-44
45
46
47
OUTPUT Fp
2
H
L
2
3
4
--------
,
2
3
5
6
7
8
X,
X.
....I W
CD=!!c(
a:Z
~
Ta01882S
Figure 7
Step 4
Select the Output Active Level desired for
each Output Function. For Xa the active level
is high for a positive logic expression of this
equation. Therefore. it is only necessary to
place an (H) in the Active Level box above Out-
put Function O. (Fa). Conversely. X, can be expressed as X, by placing an (l) in the Active
Level box above Output Function 1. (F,).
AND
INPUT(lm)
111111
TERM
54321098765
4" "3 ;- '·0
H H
L
H
L
L H
H
H
H
=
••
44
45
4.
"""'...-
47
PIN
2
2
2
2
2
2
2
2
NQ
0
1
2
3
4
5
6
7
2
3
A
4
B
5
C
•
7
D
E
Figure 8
January 1990
14
8
F
1
1
1
1
1
1
0
1
2
3
5
•
9
G
1
7
X,
Xo
Signetics Programmable Logic Devices
SigneticsProgrammable Logic
Introduction
Step 5
Terms which are not active for a given output
Step 6
Select the F-Term. you wish 10 make acllve
are made inactive by placing if (-) in the box un-
Enror the data into n Slgnetice approved pro-
der that P-term. Leave all unused P-terms unprogrammed.
grammer. The input format is identical to the
Signetics Program Table. You specify the Pterms. Output Active Level, and which P-terms
are active for each output exac~y the way it appears on the Program Table.
for each Output Function. In this case Xo =Po
+ P, + P2, sc an A has been placed in the intersection box for Po and Xc, P, andXoand P2 and
Continue this operation until all outputs have
been defined in the Program Table.
Xc.
POLARITY
AND
TERM
,-
., ,- ., ., .,
S
4
3
2
,
0
T T l " -r -r I LT H.l...J... .J... t.;..L..L..L-
INPUT(l m)
-
9
-
8
-7 -6 -5 -4 -3 -2
,
H
0
3
4
Xo = Po
X,
+ P, + P2
= P3 + P, + P4
L
H
H
0
2
,
2
2
2
2
2
2
2
3
4
5
6
7
2
3
A
5
4
3
2
4
5
6
B
C
D
',- -o-
.
H
A
A
H
--
...-
t::=="
...c:::-
7
8
9
E
F
G
A
A
A
..
.
, , , , , , , ,
,
0
W
-'W
6
A
••
2
- - QUTPuTF; - - 7
H
L
H
44
45
46
47
PIN
NO.
0
H
L
2
--.,-
,
2
3
5
6
7
8
X,
XO
ID:;
~«
a:Z
~
TB01861S
Figure 9
Jan uary 1990
15
Signetics Programmable Logic Devices
Signetics Programmable Logic
PLD LOGIC SYNTHESIS
(Continued)
When fewer inputs and outputs are required in
a logic design and low cost is most important,
the Signetics 2O--pin PLD should be considered
Introduction
first choice. The PLUSl53 is a PLA with
8 inputs, 10 1/0 pins, and 42 product terms. The
user can configure the device by defining the
direction of the 110 pins. This is easily accomplished by using the direction control terms
Do - 0 9 to establish the direction of pins
Bo - Bo. The D-lerms control the 3-State buffers found on the outputs of the Ex-QR gates.
Figures 10and 11 show how the D-term configures each Bx pin.
f®
hr~-----------+----------~--~~
>------*...L..ollo
~TATE
BUFFER
Figure 10. PLUS153 Functional Diagram
P"
Po
Po
INPUT
------4-0 8s
OUTPUT
r-D>----~ 8s
TRI-STATE
BUFFER INACTIVE
(OPEN)
a. 09 Active Makes B9 Appear as an Output
with Feedback
b. 0 9 Inactive Makes B9 Appear as an Input
Figure 11
January 1990
16
Signetics Programmable Logic Devices
Introduction
Signetics Programmable Logic
To control eech O-tenn. it is necessary to
IJnderstand that each control gate is a 36-lnput
AND gate. To make the 3-State buffer active
(Bx pin an output). the output of the control gate
must be at logic HIGH (1). This can be
accomplished in one of two ways. A HIGH can
be forced on all control gate input nodes. or
fuses can be programmed. When a fuse is
programmed. that-control gate input node is
internally pulled up to HIGH (1). See Figure 12
and Figure 13.
Programming the fuse permanently places a
HIGH (1) on the input to the control gate. The
input pin no longer has any effect on that state.
vee
1= HIGH(') 0 - - - + - - - " ' "
1= LOW (0)
A~:AYo---I.>-......---o8X=OUTPUT
A~:AY
0-=:::....+---......
0----11>-.....- - - 0 Bx = INPUT
Figure 12. Input Effect on Control Gates (Fuse Intact)
I = H I G H ( ' ) o - - - + - - -........
A~:AY 0---IJI~""--08x = OUTPUT
Figure 13. Effect on Control Gate If Fuse Is Programmed
January 1990
17
Signetics Programmable Logic Devices
Signetics Programmable Logic
Introduction
bucket or Write-Only-Memory (WOM), most
applications requireat least one output. Clearly,
the first task is to determine which of the Bxpins
are to be outputs. The next step is to condition
the control gate to make the 3-State buffer for
those gates active. To dedicate Be and B, as
outputs, it is necessary to program all fuses to
the inputs to Control Gates Do and 0,. This internally pulls all inputs to those gates to HIGH
(1) permanently. since all inputs to the Control
DEDICATING Bx PIN DIRECTION
Since each input to the D-terms is true and
complement buffered (see Figure 11), when the
device is shipped with all fuses intact, all control
gates have half of the 36 input lines at logic low
(0). The result of this is all Control Gate outputs
are low (0) and the 3-State buffers are inactive.
This results in all Bx pins being in the input condition. the resultant device is, therefore, an
18-input, O-output FPLA. While useful as a bit
Gates are HIGH (1),the output is HIGH (1) and
the 3-State buffers for Be and B, are active.
This permanently enables Be and B, as outputs. Note that even though Be and B, are outputs, the output data is available to the AND
array via the internal feedback (see Figure
l1a).
To program this data, the PLUS153 Program
Table is used as shown in Figure 14.
POLARITY
I ,1
~
~
I ; I.):}
~
I
AND
8(1)
a:1?:" I~I~K :
1
I
0 I ~ ~ l!z I := : If-":"o-+~t-:+=-+~t,-=-f-=-+-+-=-t-:+.:....j,-=-+-=+-=-i~-+,-=-+-=+~--=-J
7
a
•
S
4
w i t ; ~ 181 ~ 1
UJ
I~ I I;: ~ 11-':'2
3
2
,
0
9
•
I
7
•
S
4
I
3
2
'0
I
--+-+--+-+-+-,-f-+-+-+--+--+,-+--+--I-.J.,-+--+--I-I
~ -f---~~---r_:--r-~_r_+_;-r-~-r_+~r-+-4-_+-+-~+__r_+__j
~
I
~
I
8a:a:
Q.
~
01 ~:: ~ I
z,
I
4
,
"
I
(0
~
0
0
,-+--j1~+-+--j-4'-+-+-f-....j
r
I
I
1-+--+-+--+-+-+,-+--+-+---1
I
I
I
•
••
~
CD
f-9-r.-...
17-r-.-.-S.::;:::..-r'-3-r-2-.--,--c-O-l
"
~
I
I
I
w
c:( r
I
3
1,
~(:)
30
,
"
31
,
I
I' I
I I ' I
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I
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\-:=-+-=:~~:+:-+~:~:~:+~:+:-+~:+~:+:-+:~:~~:+~:+:~:~:~~:+:-+~:~t '-=r"l
07000
D6
0100000
010
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I
010000
000010000001000010000
05000010000001000010000
D4
000
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000
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a
0
010
03
000
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a
00010
0
0
010000
D2
000
010
a
a
0
0
0
010
0
0
010
a
0
0
8
5
3
2
1
19
18
16
15
14
12
11
9
000
t-------------l
01
00
PIN
7
6
4
17
13
NOTES:
1 The FPLA is Shipped with all links intact. Thus a
bacKground 01 entries corresponding to states 01
virgin links exists In the table, shown BLANK for
dariry.
2 Unused I and B bits 10 the AND array are normally
programmed Don'! Care (-}
3 Unused product terms can be left blank
Figure 14. Dedicating
January 1990
Be and Bl as Outputs and B2 Through B9 as Inputs
18
Signetics Programmable Logic Devices
Signetics Programmable Logic
Introduction
,.
By placing a (-) Don't Care in each input bex
you are specifying that the True and Complement fuses are programmed on each Control
Gate, thus permanently dedcating the Be and
B, pins as outputs. By placing a (0) in all input
boxes for B2 - Bs, you are specifying that beth
True and Complement fuses are intact. This
causes a low (0) to be forced on half of the
Control Gate inputs, guaranteeing the output of
the Control Gate will be low (0). When the
Control Gate outputs are low (0), the 3-State
buffer is inactive and the ~ - B9 pins are
enabled as inputs. All Bx pin directions can be
controlled in this manner.
done by programming the Control Gate to
respond to one or more input pins. ltis only necessaryto select which Ix and Bx pins will control
the pin directions and the active level HIGH (H)
or LOW (L) thatwill be used. The PLUS 153 Program Table in Figure 15 shows the method of
controlling Be - B9 with 17. When 17 is LOW (L).
pins Be - Bs are outputs; when 17 is HIGH (H),
pins Be - Bs are inputs. Note that by programming all other Ix and Bx pins as DON'T CARE
(-), they are permanenHy disconnected from
control of Bx pin direction.
ACTIVE DIRECTION CONTROL
Sometimes it is necessary to be able to actively
change the direction of the Bx pins without permanently dedicating them. Some applications
which require this include 3-State bus enable,
multi-function decoding, etc. This can easily be
POLARITY
I
AND
I ! I.) :; •
ffl 1'";'0- 10 1 ~
1-
~_
II
~
F
~
F
T
I
R
B(I)
~
II:
8
it:
I
I
~I
"'I
~
0
'"
-'
---
I
•
I
9
I
I
8
I7
5
6
4 I 3
2
I
I
I
I
I
I
I
I
I
I
1
0
•
••
~
~
! ~~~
I I
B(O)
•
M
7
6
1
0
9
1
0
6
8
7
3
4
3
IL-:-+++--r-:-t-=-H""''''''-+-+--+-+--t--t-i-t-H
-'Ir
I
0
I
I
'" I~~ I I;; g 11-':"'-+--+--4~+--+-I-+-+-t-+--i-+--+-t-+-i-t---t---;
I
1
I
•3
~ -}'=~~~---~~+-+-+-4-~-t-+~-1--r-t-t-i-i-~-t-t-i-i
I
I
I
~:
I
OR
I
•I •
• I •
101 a
- ;0-11-=-f---+-+--j-+-+-+-t-+--t---1~t----t--i-t---t---t-H
101
1
I
I
I
- 11:1~~ I!ZI
111: 1 '"
II:
01
I I
I
30
I
I
I
I
31
I
I
I
I
1
I
I
-
-I
09
L
D8
L
I
I
07
L
1
I
I
D6
L
I
I
1
os
L
1
I
I
D4
L
I
I
I
D3
L
I
I
I
D.
L
I
I
I
01
L
I
DO
L
I
PIN
•
7
• • •
.
I
3
•
1
"
,
I
17
,. "
I
I
I
I
I I
I I
~J
I
,.
1
13
12
11
9
NOTES:
1. The FPLA is shipped with all links inlact. Thus a
background of entries corresponding 10 stales of
virgin links exists in the table, shown BLANK for
darity.
2. Unused I and 8 bits in the AND array are normally
programmed Don't Care (-).
3 Unused product terms can be left blank.
Figure 15. Active Control of Bo - 8, Using 17 Active Low (L)
Janumy 1990
19
Signetics Programmable Logic Devices
Signetics Programmable logic
Introduction
pear on Bs and B7 . B, through 8 5 are not used
and therefore left unprogrammed.
The previous 28-pin logic synthesis example
could be done on the PLUS 153 as follows:
Xo=AB+t:"D+BU
lower density parts. However, to satisfy the
needs of Programmable Macro Logic users,
Signetics developed an additional software
package called SNAP. SNAP expands upon
the capabilities of AMAZE in its approach to design implementation, more closely resembling
a gate array methodology. Both of these products are described in more depth at a later point
in this handbook.
Signetics offers two packages for user friendly
design assistance. The first package, AMAZE,
has evolved over 10 years to support Signetics
programmable products with logic equation,
state equation, and schematic entry. AMAZE
can compile designs quite well for Signetics
X, = 1m + UD + EFG
Note that So was used as a CHANGE input.
When So is HIGH (H) the outputs appear on B8
and !!g. When Be is LOW (L), the outputs ap-
POLARITY
L
s I I
Ir-~ I.)
I
:r
ID a: ~ ~ I~l ~
I
~aJ °tI t;~ ~~
l!zrri
a
AND
T
E
8(1)
R
M
7
6
0
H
H
5
-
4
-
3
I-
2
-
1
-
0
-
9
-
8
-
I7
6
I-
-
5
-
8(0)
4
-
3
I-
2
-
1
-
0
4 1 3
-
A
~ _+~~lJ_'i:._~_.~f--_-2,..-,I-f---::--H--f+---~~~L~I-,t--~~~-~~~-~:-----I-f-----:--~:'~-~~~-~~----:--~~I~-~~~-~~----:--~..,
~:
~
I
~
ot
~ ~I
Q.
~
3
L
H
_ _ 1 _ _ _ _ _ _ 1 _ _ _ _ 1_
4
-
-
-
-I H
H
H
-
-I
-
I
~:=::' I
I
I
~
g
A
A I A
A
A I •
A
A
• I A
A
•
1 A
J L
30
31
-,-- -
-
-
-
-
-,-
-
I
D9
-
-
-
-1-
08
- - - - 1 - - - - - -1- -
-
-I-
07
I
I
I
===~
I
1 I 1
I
l...l
1
06
D5
000
010
0
0
0
001000
010
000
D4
0
0 10
0
0
0
0
0 10
0
0
0
010
0
0
0
0
03000010000001000
010000
02
0
0
0
010
0
0
0
0
010
0
0
010
0
01
0
0
0
010 1 0
0
0
0
010
0
0
0 10
a a
00
0
a
00100000
PIN
8
7
6
5
4
3
2
1
19
010
18
17
0
0
16
15
010
14
13
0
0
0
000
12
11
9
19
18
17
16
X, Xo x, Xo
ABCDEFG
C
H
A
N
G
E
Figure 16. PLUS153 Example
January 1990
A I •
••
•
~
co co
...l ...l
I
OR
~ 1-,--_-t-_-t-L-+-H+'----1---t---+--+--+--;,---t---+--+--1,~--t---+---t-----1
181
H1 L H...l...l
20
c
C
H
A
N
H
A
N
G
G
E
E
15
14
13
12
11
9
Signetics Programmable Logic Devices
Signetics Programmable Logic
SEQUENTIAL LOGIC
CONSIDERATIONS
Introduction
ClOCK----------.--------------,
The PLUS405(Programmable Logic Sequencer) is an example of a high-order machine
whose applications are many. Application
areas for this device include VRAM, DRAM,
Bus and LAN control. The PLUS405 is fully
capable of performing fast sequential operations in relatively high-speed processor
systems. By placing repetitive sequential operations on the PLUS405, processor overhead is
reduced.
0=
o=
o=
o=
The PLUS405, PLUS105 and PLC42VA12
represent significant increases in complexity
when compared to the combinatorial logic
devices previously discussed. By combining
the AND/OR combinatorial logic with clock
output flip-flops and appropriate feedback,
Signetics has created the first family of totally
flexible sequential logic machines.
"'PUT
PRESENT STATE
NEXT STATE
NEXT OUTPUT
COMBIN.
LOGIC
1-
Figure 17. Basic Architecture of PLS105 FPLS. I, P, N, and F are Multi-line
Paths Denoting Groups of Binary Variables Programmed by The User.
The following pages summarize the PLUS405
architecture and features.
Sequencer Architecture
The PLUS405 Logic Sequencer is a programmable state machine, in which the output is a
function of the present state and the present
input.
With the PLUS405, a user can program any logic sequence expressed as a series of jumps
between stable states, triggered by a valid input
condition (I) at clock time (t). All stable states
are stored in the State Register. The logic output of the machine is also programmable, and
is stored in the Output Register. The PLUS105
is a subset of the PLUS405.
Clocked Sequence
Figure 18. Typical State Diagram.
1, -3 Are Jump Conditions Which
Must be Satisfied Before Any
Transitions Take Place. Fr Are
Changes in Output Triggered by 1m,
and Stored in The Output Register.
State Transitions a -> band c -> d
Involve No Output Change.
A synchronous logic sequence can be represented as a group of circles interconnectedwith
arrows. The circles represent stable states,
labeled with an arbitrary numerical code
(binary, hex, etc.) corresponding to discrete
states of a suitable register. The arrows represent state transitions, labeled with symbols
denoting the jump condition and the required
change in output. The number of states in the
sequence depends on the length and complexity of the desired algorithm.
January 1990
21
Figure 19. Typical State Transition
Between Any Two States of Figure
18. The Arrow Connecting the Two
States Gives Rise to a Transition
Term Tn. I is the Jump Condition.
Signetics Programmable Logic Devices
Signetics Programmable Logic
Introduction
State Jumps
The state from which a jump originates is referred to as the Present state (P), and the state
to which a jump tenninates is defined as the
Next state (N). A stale jump always causes a
change in state, but mayor may not cause a
change in machine output (F).
A
B
B
State jumps can occur only via "transition
tenns' Tn. These are logical AND functions of
the clock (t), the Present state (P), and a valid
input (I). Since the clock is actually applied to
the State Register, Tn = I-P. When Tn is "true",
a control signal is generated and used at clock
time (I) 10 force the conlenls of the Stale Register from (P) 10 (N), and to change the conlents
of the Outpul Register (if necessary). The simple state jump in Figure 20, involving 2 inputs,
1 state bil, and 1 output bit, illustrates the equivalence of discrete and programmable logic implementations.
T
= ABO
Figure 20. Typical State Jump From State (0) to State (1),
if Inputs A = B = "1". The Jump Also Forces F = "1", as Required.
Sequencer Logic Structure
The Sequencer consists of programmable
AN D and OR gate arrays which control the Set
and Reset inputs of a State Register, as well as
monitor its output via an internal feedback path.
The arrays also control an independent Output
Regisler, added to slore output commands
generaled during stale transilions, and 10 hold
the output constant during state sequences involving no output changes. If desired, any number of bils of the OutpUI Register can be used
to extend the width olthe State Register, via external feedback.
_ _ _ LOGIC TEAMS T _ _ _
OPTION
10
.--.-!-- PAIOE
I"
C--~--------------+-~
Fo
CK
4746
Figure 21. Simplified Logic Diagram of PLUS105
January 1990
22
Signetics Programmable Logic Devices
Introduction
Signetics Programmable Logic
Figure 22. Typical AND Gate Coupled to (I) and (P) Inputs.
If at Least One Link Pair Remains Intact, Tn is Unconditionally Forced Low .
...)J,..
",Jj,..
1-0- T--D-
D-
Figure 23. Choice of Input Polarity Coupling to a Typical
AND Gate. With Both Links Open, (I) is Logically Don't Care.
Input Buffers
16extemal inputs (1m! and 6 internal inputs (Ps),
fed back from the State Register, are combined
in the AND array through two sets of Truel
Complement (TIC) buffers. There are a total of
22 TIC buffers, all connected to multi-input
AND gates via fusible links which are initially
intact.
Selective fusing of these links allows coupling
either True, Complement, or Don't Care values
of (1m! and (Ps).
"AND" Array
Figure 24. Typical Transition Terms
Involving Arbitrary Inputs and State
Variables. All Remaining Gate Inputs
Are Programmed Don't Care. Note
That T 2 Output is Slate Independent.
January 1990
State jumps and output changes are triggered
at clock time by valid transition terms Tn. These
are logical AND functions of the present state
(P) and the present input (I).
The PLUS 105 AN D Array contains a total of 48
AND gates. Each gate has 45 inputs - 44
connected to 22 TIC input buffers, and 1 dedicated to the Complement Array. The outputs of
all AND gates are propagated through the OR
Array, and used at clock time (t) to force the
contents of the State Register from (P) to (N).
they are also used to control the Output
Register, so that the FPLS 8-bit output F, is a
function of the inputs and the present state. The
PLUS405 contains 64 AND gates in its' AND
array.
23
Signetics Programmable Logic Devices
Signetics Programmable Logic
Introduction
"OR" Array
In general, a docked sequence will consist of
several stable states and transitions, as determined by the complexity of the desired algorithm. All state and output changes in the state
diagram imply changes in the contents of State
and Output Registers.
Thus, each flip-flop in both registers may need
to be conditionally set or reset several times
with Tn commands. This is accomplished by
selectively ORing through a programmable OR
Array all AND gate outputs Tn necessary to
activate the proper flip-flop control inputs.
The PLUS10S OR Array consists of 14 pairs of
OR gates, controlling the SIR inputs of 14 State
and Output Register stages, and a single NOR
gate for the Complement Array. All gates have
48 inputs for connecting to all 48 AND gates.
The PLUS40S uses 64 input gates.
The PLUS40S contains 16 pairs of OR gates
controlling state transitions and output stages
and two additional NOR gates for dual complement arrays.
CK
COmplement Array
The COMPLEMENT Array provides an
asynchronous feedback path from the OR
Array back to the AND Array.
Figure 25. Typical OR Array Gating of Transition Terms. T 1,2,3 Controlling Arbitrary State and Output Register Stages.
This structure enables the sequencer to perform both direct and complement sequential
state jumps with a minimum of transition (AND)
terms.
AND ARRAY
Typically direct jumps, such as T1 and T2 in
Figure 27 require only a single AND gate each.
But a complement jump such as T3 generally
requires many AND gates if implemented as a
direct jump. However, by using the Complement Array, the logic requirements for this type
of jump can be handled with just one more gate
from the AND Array. Because it can be split into
separate machines (2c1ocks), the PLUS40S incorporates two COMPLEMENT Arrays.
COMPLEMENT
ARRAY lOGIC
PATH
r-I
I
I
I
I
I
I
QRARRAY
Figure 26. The COMPLEMENT Array is Logically Constructed from a
multiple input Programmable NOR Gate. All AND Terms Coupled to the
OR Gale are Complemented at the Inverter Output, and Can be Fed Back
as Inputs 10 the AND Array.
January 1990
24
Signetics Programmable Logic Devices
Signetics Programmable Logic
Introduction
Po------------~
IL.. _ _ _ _ _ _ _ _ _.II
TRANSITION TERMS
COMPLEMENT ARRAY
T3 = Po{PoX + poy)
T 3 ;; Po[Po(X + V)]
DIRECT
{
T3
=Po[Po + (X + V)]
T3 ;; a + Po(X + Y)
T3 =Po(X.V)
COMPLEMENT
a. Typical State Sequence
b. Complement Jump
Figure 27. a. X And Y Specify the Conditional Logic for Direct Jump
Transition Terms T1 and T2. The Complement Jump Term T3 is True Only
When Both T 1 and T 2 are False. b. Note that the Complementary Logic
Expression for T 3, T 1 + T2, Corresponds Exactly to the Logic Structure of the
Complement Array.
January 1990
25
As indicated in Figure 28, the single Complement Array gate may be used for many states
of the state diagram. This happens because all
transition terms linked to the OR gate include
the present state as a part of their conditional
logic. In any particular state, only those transition terms which are a function of that state are
enabled; all other terms coupled to different
states are disabled and do not influence the
output of the Complement Array. As a general
rule of thumb, the Complement Array can be
used as many times as there are states.
Signelics Programmable Logic Devices
Introduction
Signetics Programmable Logic
Td1 = loi1PO
T d2
= 12P O
Tc3 = (Td1 + Td2)PO= (1011 + 12)Po
Td4 = 12P3
Td6= lol1P3
To.
=(Tdo + Td6)P, =(101, + i 2)p,
Ton = COMPLEMENT STATE TRANSITION TERM
T dn = DIRECT STATE TRANSITION TERM
p. = PRESENT STATE
b. Logic Definition
a. State Diagram
:>
'0
'0
" o---v
f-----O
" e~
'2O---V
'2 e r-----l2
---1.?
-------0
,.....-t:>_
.-----0
w
-"
1
ARRAY
J
00 S
R
i
~
RJ-a.
~
w
-"
COMPLEMENT
"--,--"
Te5
COMPLEMENT
ARRAY
J
02 S
R
8 TRANSITION TERMS USED
6 TRANSITION TERMS USED
d. State Logic Using the Complement Array
c. State Logic without Using the Complement Array
Figure 28. logic Reduction with the Complement Array. The Logic State Diagram in (a) Includes Complement Jumps TC3 and
TC5 Defined in (b). When Using the Complement Array, a Savings of 2 Transition Terms Results, as Shown in (e) and (d).
Additional features are available depending on
a specific part. In particular, the PLC42VA12
has everything mentioned here, and more.
January 1990
More details on PLAs, PAL-Type devices and
Sequencers can be found in the application
section later in the manual.
26
Programmable Macro Logic, Signetics very
high density logic is fully described in detail in
its own section.
Signetics
Quality
and
Reliability
Programmable Logic Devices
SIGNETICS PROGRAMMABLE
LOGIC QUALITY
Signetics has put together winning processes
for manufacturing Programmable Logic. Our
standard is zero defects, and current customer
quality statistics demonstrate our commitment
to this goal.
The PLDs produced in the Standard Products
Group must meet rigid criteria as defined by our
design rules and as evaluated with a thorough
product characterization and quality process.
The capabilities of our manufacturing process
are tneasured and the results evaluated and reported through our corporate--wide QAOS data
base system. The SURE (Systematic Uniform
Reliability Evaluation) program monitors the
performance of our product in a variety of accelerated environmental stress conditions. All of
these programs and systems are intended to
prevent product-related problems and to inform ourcuslomers and employees of our progress in achieving zero defects.
RELIABILITY BEGINS WITH THE
DESIGN
Quality and reliability must begin with design.
No amount of extra testing or inspection will
produce reliable ICs from a design that is
inherenUy unreliable. Signetics follows very
strict design and layout practices with its
circuits. To eliminate the possibility of metal migration, current density in any path cannot exceed 2 X 105 amps/cm 2 . Layout rules are
followed to minimize the possibility of shorts,
circuit anomalies, and SCR type latch-up effects. Numerous ground-to-substrate connections are required to ensure that the entire chip
is at the same ground potential, thereby precluding internal noise problems.
PRODUCT CHARACTERIZATION
Before a new design is released, the characterization phase is completed to insure that the
distribution of parameters resulting from 10Holot variations is well within specified limits. Such
extensive characterization data also provides a
January 1990
basis for identifying unique application-related
problems which are not part of normal
data sheet guarantees. Characterization takes
place from ..5soC to + 12SOC and at
supply voltage.
that represent all generic product groups in all
wafer fabrication and assembly locations.
± 10%
QUALIFICATION
Formal qualification procedures are required
for all new or changed products, processes and
facilities. These procedures ensure the high
level of product reliability our customers expect.
New facilities are qualified by corporate groups
as well as by the quality organizations of specific units that will operate in the facility. After qualification, products manufactured by the new
facility are subjected to highly accelerated environmental stresses to ensure that they can
meet rigorous failure rate requirements. New or
changed processes are similarly qualified.
QA05 - QUALITY DATA BASE
REPORTING SYSTEM
The QAOS data reporting system collects the
results of product assurance testing on all
finished lots and feeds this data back to
concerned organizations where appropriate
action can be taken. The QAOS reports EPQ
(Estimated Process Quality) and AOO (Average Outgoing Quality) results for electrical,
visuaVmechanicai, hermeticity, and documentation audits. Data from this system is available
upon request.
THE LONG-TERM AUDIT
One-hundred devices from each generic family
are subjected to each of the following stresses
every eight weeks:
• High Temperature Operating Life:
TJ = 150°C, 1000 hours, static biased or
dynamic operation, as appropriate (worst
case bias configuration is chosen)
• High Temperature Storage: TJ
1000 hours
= 150°C,
• Temperature Humidity Biased Life: 85°C,
85% relative humidity, 1000 hours,
static biased
• Temperature Cycling (Air-to-Air): ~oC to
+ 1SOOC, 1000 cycles
THE SHORT-TERM MONITOR
Every other week a 50-piece sample from each
generic family is run to 168 hours of pressure
pot (ISpsig, 121°C, 100% saturated steam)
and 300 cycles of thermal shock (~OC to
+ISOOC).
In addition, each Signetics assembly plant performs SURE product monitor stresses weekly
on each generic family and molded package by
pin count and frame type. Fifty-piece samples
are run on each stress, pressure pot to 96
hours, thermal shock to 300 cycles.
THE SURE PROGRAM
The SURE (Systematic Uniform Reliability
Evaluation) program audits/monitors products
from all Signetics' divisions under a variety of
accelerated environmental stress conditions.
This program, first introduced in 1964, has
evolved to suit changing product complexities
and performance requirements.
The SURE program has two major functions:
Long-term accelerated stress performance
audit and a short-term accelerated stress monitor. In the case of Bipolar Memory and Programmable Logic products, samples are selected
27
SURE REPORTS
The data from these test matrices provides a
basic understanding of product capability, an indication of major failure mechanisms and an estimated failure rate resulting from each stress.
This data is compiled periodically and is available to customers upon request.
Many customers use this information in lieu of
running their own qualification tests, thereby
eliminating time-consuming and cosUy additional testing.
Signetics Progranmable Logic Devices
Quality and Reliability
RELIABILITY ENGINEERING
In addition lO!he product performance monilOrs
encompassed in !he Programmable Logic
SURE program, Signetics' Corporate and
Division Reliability Engineering depar1ments
sustain a broad range of evaluation and quantication activities.
Included in !he engineering process are:
• Evaluation and qualification of new or
changed materials, assembly/wafer-fab
processes and equipment, product
designs, facilities and subcontractors
• Device or generic group failure rate studies
• Advanced environmental slJeSs development
• Failure mechanism characterization and
corrective action/prevention reporting
The environmental stresses utilized in !he engineering programs are similar 10 !hose utilized
for !he SURE monilOr; however, more highlyaccelerated conditions and extended durations
typify !he engineering projects. Additional
stress systems such as biased pressure pot,
power-temperature cycling, and cycle-biased
temperature-humidity, are also included in !he
evaluation programs.
FAILURE ANALYSIS
The SURE Program and !he Reliability Engineering Program bo!h include failure analysis
activities and are complemented by corporate,
divisional and plant failure analysis departments. These engineering units provide a service to our cuslOmers who desire detailed
failure analysis support, who in tum provide
Signetics with !he technical understanding of
!he failure modes and mechanisms actually experienced in service. This information is essential in our ongoing effort to accelerate and
improve our understanding of product failure
mechanisms and their prevention.
Those of you who invest in cosUy lest equipment and engineering 10 assure that incoming
products meet your specifications haw a special understancing of !he cost of ownership.
And your cost does not end there; you are also
burdened with inflated inventories, lenglhened
lead times and more rework.
SIGNETICS UNDERSTANDS
CUSTOMERS' NEEDS
Signetics has long had an organization ofquality professionals, inside aD operating units,
coordinated by a corporate quality department.
This broad decentralized organization provides
leadership, feedback, and direction fo achieving a high level of quality.
In 1980 we recognized !hat in order to achieve
outgoing lewis on the order of l00ppm (parts
per million), down from an industry practice of
1O,OOOppm, we needed to supplement our traditional quality programs wi!h one !hat encompassed all activities and all levels of the
company. such unprecedented low defect levels could only be achiewd by conllibutions
from all employees, from !he Rand 0 IaboralOry
to !he shipping dock. In short, from a program
that would effect a total cultural change wi!hin
Signetics in our attitude toward qUality.
QUALITY PAYS OFF FOR OUR
CUSTOMERS
Signetics' dediceted programs in productquality improvement, supplemented by close working relationships with many of our customers,
have improved outgoing product quality more
than twenty-fold since 1980. Today, many major customers no longer test Signetics circuits.
Incoming product moves direcUy from the receiving dock to !he production line, greatly
accelerating !hroughput and reducing invenlOries. Other cuslOmers have pared significantly
the amount of sampling done on our products.
Others are beginning 10 adopt !hese costsaving practices.
We closely monitor the electrical, visual, and
mechanical quality of all our products and review each retum to find and correct the cause.
Since 1981, over 90% of our customers report
a significant improvement in overall quality (see
Figure 1).
At Signetics, quality means more than working circuits. It means on-time deliwry of the
right product at the agreed-upon price.
Signetics considers Performance 10 Customer
Request and Performance 10 Original Schedule Date 10 be key Quality issues. Employees
treat delinquencies as quality defects. They
analyze !he cause for !he delinquency and seek
corrective action 10 prevent future occurrence.
Continuous effort is given 10 try 10 achieve !he
ultimate goal of zero delinquencies.
DEFECTIVE PARTS PER MILLION
(IN THOUSANDS)
12.0,-------------------~
10.8
9.6
ZERO DEFECTS PROGRAM
In recent years, United States industry has increasingly demanded improved product quality. We at Signetics believe that !he customer
has every right to expect quality products from
a supplier. The benefits which are derived from
quality products can be summed up in !he
words, lower cost of ownership.
1981
1982
1983
1984
1985
1986
Figure 1. Signetica Quality Progre..
. January 1990
28
1987
1988
Signetics Ptogrammable Logic Devices
Quality and Reliability
ONGOING QUALITY PROGRAM
The quality improvement program at Signetics
is based on "00 It Right the First Time". The inIBnt of this innovatiw program is to change the
perception of Signetics' employees that somehow quality is solely a manufacbJring issue
where some level of defects is inevitable. this
attitude has been replaced by one of acceptance of the fact that all errors and defects are
prevenlable, a point of view shared by all technical and adminislrativa functions equally.
This program extends into every area of the
company, and more than 40 quality improvement teams throughout the organization drive
ilB ongoing refinement and progress.
Key componenlB of the program are the Quality
College, the "Make Certain" Program, coireotive Action Teams, and the Error Cause Removal System.
The core conceplB of doing it right the first time
are embodied in the four absolUIBs of quality:
1. The definition of quality is conformance to
requiremenIB.
2. The syslBm 110 achieve quaHty improwment is prevention.
3. The performance slBnderd is zero
defects.
4. The measurement syslBm is continuous
improvement
JanLWY 1980
"MAKING CERTAIN"ADM!NISTRATIVE QUALITY
IMPROVEMENT
Signetics' experience has shown that the largest source of errors allecting product and service quality is found in paperwork and in other
adminislratiw functions. The "Make Certain"
program focuses the allllntion of management
and adminislrativa personnel on error prevention, beginning with each employee's own aclicns.
This program promotes defect prevention in
three ways: by educating employees as to the
impact and cost of adminislrativa errors, by
changing attitudes from accepting occasional
errors to one of accepting a personal work standard of zero defaclB, and by providing a formal
mechanism for the prevention of errors.
CORRECTIVE ACTION TEAMS
Employees with the perspective, knowledge,
and necessary skills to solve a problem are
formed into ad hoc groups called Corrective
Action Teams. These teams, a major force within the company for quality improvement,
resolveadminislrative,lBchnical and manufacturing issues.
ECR SYSTEM (ERROR CAUSE
REMOVAL)
The ECR System permits employees to report
to management any impedimenlB to doing the
job right the first time. Once such an impediment is reporlBd, management is obliged 110
respond promptty with a corrective program.
Ooing it right the first time in aN company activities produces lower cost of ownership through
defect prevention.
29
PRODUCT QUALITY PROGRAM
To reduce defecIB in OUlgoing products, we
created the Product Quality Program. This is
managed by the Product Engineering Council,
composed of the top product engineering and
test professionals in the company. this group:
1. SaIB aggressive product quality improvementgoals;
2. provides corporalB-level visibility and
focus on problem areas;
3. serves as a corporate resource for any
group requiring assistance in quality
improvement; and
4. drives quality improvement projects.
As a result of this aggressiw program, every
major cus1Dmer who reporlS back to us on
product parformance is reporting significant
progress.
VENDOR CERTIFICATION
PROGRAM
Our vendors are taldng ownership of their own
product quality by establishing improved process control and inspection systems. They subscribe to the zero defacIB philosophy. Progress
has been excellent.
Through inlBnsive work with vendors, we have
improved our lot acceptance rate on incoming
malBriais as shown in Figure 2. Simultaneously, waivers of incoming material haw been
eliminated.
Signetics Programmable Logic Devices
Quality and Reliability
PERCENT
100
00
80
r-88.7
81.1
1118.
1882
-84,4
r87.2
r--
"
r-88
-
MANUFACTURING: DOING IT
RIGHT THE FIRST TIME
88.1
"
'83:5
eo
50
40
30
10
o
11180
1983
1l1li5
,-
,_
'887
Figure 2. Lot Acceptance Rate From Signellca Vendor.
MATERIAL WAIVERS
1988 - 0
1987 - 0
1986- 0
1985- 0
1984- 0
1983- 0
1982- 2
1981 -134
Higher incoming quality material ensures higher outgoing quality products.
QUALITY AND RELIABILITY
ORGANIZATION
Quality and reliability professionals at the divisionallevel are involved with all aspects of the
product, from design through every step in the
manufacturing process, and provide product
assurance testing of outgoing product A separate corporate-level group provides direction
and common facilities.
Quality and Reliability Functions
• Manufacturing quality control
• Product assurance lesting
• Laboratory faci~ties - failure analysis,
chemical, metallurgy, thin film, oxides
• Environmental stress testing
• Quality and reliability engineering
• Customer liaison
Janua/y 1990
COMMUNICATING WITH EACH
OTHER
For information on Signetics' quality programs
or for any question concerning product quality,
the field salesperson in your area will provide
you with the quickest access to answers. Or,
write on your letterhead directly to the corporate
VP of quality at the corporate address shown at
the back of this manual.
We are dedicated 10 preventing defects. When
product problems do occur, we want to know
about them so we can eliminate their causes.
Here are some ways we can help each other:
• Provide us with one informed contact within
your organization. This will establish continuity and build confidence levels.
• Periodic face-to-face exchanges of data
and quality improvement ideas between
your engineers and ours can help prevent
problems before they occur.
• Test correlation data is very useful. Unepull information and field failure reports
also help us improve product performance.
• Provide us with as much specific data on
the problem as soon as possible 10 speed
analysis and enable us 10 take corrective
action.
• An advance sample of the devices in
question can start us on the problem
resolution before physical return of
shipment.
This teamwork with you win aliow us to achiew
our mutual goal 01 improved product quality.
30
In dealing with the standard manufacturing
flows, it was recognized that significant improvement would be achieved by "doing every
job right the first time", a key concept of the
quality improvement program. During developmenl of the program many profound changes
were made. Figure 3, Programmable Logic
Process Flow, shows the result. Key changes
included such things as implementing 100%
temperature testing on all products as well as
upgrading test handlers to insure 100% positivebinning. Someoftheotherchanges and additions were to tighten the outgoing QA lot
acceptance criteria to the tightest in the industry, with zero defect lot acceptance sampling
across all three temperatures.
The achievements resulting from the improved
process flow have helped Signetics to be recognized as the leading Quality supplier of Programmable Logic. These achievements have
also led to our participatioo in several Ship-toStock programs, which our customers use to
eliminate incoming inspection. such programs
reduce the user cost of ownership by saving
both time and money.
OUR GOAL: 100"k
PROGRAMMING YIELD
Our original goal back in the early 1970. was to
develop a broad line of programmable products
which would be recognized as having the best
programming yield in the industry. Within the
framework 01 a formal quality program, our efforts to improve circuildesigns and refine manufacturing controls have resulted in major
advances toward that goal.
Also within the framework of our lormal quality
program we have now established a stated goal
of 100% programming yield. through the increasing effectiveness 01 a quality attitude of
"Do II Right the First Time" we're moving ever
closer to that target
Signetics PLD programming yields have been
shown in collected data from inlemal audits and
customer reporting to be consistently higher
than comparable devices produced by our
competition. We use systematic methods involving publication of exacting specifications of
our programming algorithms, and through eValuation of those algorithms as implemented in
industry standard programming equipment.
Because 01 this we can assure our customers
who program Signelics PLOs on such qualified
equipment they will see consistenlly high
yields. Our data base shows thai average 101
programming yield exa!9ds 97%.
Signetics Programmable Logic Devices
Quality and Reliability
,.
WAFER
FABRlCA110N
0
I
I
SCANNNG ELECTRON IICIIOSCOPE CONTROL
_ _ are 88II'1>iod dally by tho Quality ConIroI LaborIOory from _ _1caI1on ""'" and subjaded 10 SEM
analyola. Thll _
control "",oaII manufacturing deI_ lWCh as _
and oxide BfAIp CXJY8IIIII8ln tho
motaI~atlon _
wtllch may ,..uIIln oarty fallu....
0
I
DIE ATTACH
WIRE BOND
~
DIE SORT WlUAL ACCEPTANCE
Product Ito InapecOad for deledl CIWI8d during fab_. wafer _Ing. or tho _lc:aIocrbo end brook
"""ration. DoIoc:I8 .uch .. ocratchoo ......... and glasolvatod bondilg pods .... Included In tho lot aoooptanco
allorla.
I
PRE-SEAL VISUAL ACCEPTANCE
I
rl
I
0
HERMElIC
IlEAL
PlAS1IC
EHCAPSULATION
----- ..... ~
Product Ie Inspeeled 10 detect orry damage Incurred at the die attach and wlro bonding stations. 001_ ouch ..
ocratch... contamination and ,",,",ad ball bondo are Included In tho lot aoooptanco critorto.
I
~
--------
I
--------
0
b
0
I
0
I
0
Uolng ML-S1O-i83Mothod tOtO.l Cond_CdeYlces ... cyctodfnxncoldlOhot...",....u... I"""'Ing.
_ _ degrading goocI_.AIooooned
during 100% _ _ •
bond 10 later _
--------
----- .. -- .. -_ .. _--
I
.. _----_ ..
I
0
~
IlEAL TESTS
~ ~
--- .. --_ ...
.............. -
0
TEMPERATURE CYCUNG ( _ )
veORdUre wIIh guard _
performance to data ._lmItII.
BURN IN (SUPR. LEVEL B QP11ON)
00vIc00 are burned In for 21 ..... atl56'C maximum junction 1an1>Oratura.
SYMBOL
00vIc00 are mark8d wIIh tho S....icllogo, deIIiclnuntIer and tho data code or cuatom Iyne,or per lndIvilual
opecfflcallon requlremonto.
VISUAL
All prGducI8 ... 100% vIouolly InopecIod per tho roqu_ -=Ifed In SIgnoIIca or
.............. -
---.
cua_ -.montL
.... PIICIDUC110N ELECTIICAl TEB1IHG
Every deIIiclll _
for tuncIIonat end ACIOO p a r _ • 25'C with guard _ 1 0 _
.. parformanco 10
FINAL QUAUTY ASSURANCE GATE
Tho final QA " - " ' " _ _ _ _ tho opocIfIed _
and otoctrIcat ..... haw_SIgnoIIcI
lao 00Iect ~ EMrr"",,",,",iI_ond_byCA--'
Figura 3. Cuatom. Specillc ProclUCIa Programmable LogIc " " - Flow
January 1990
10 .aura
31
Signetics Programmable Logic Devices
Quality and Reliability
As time goes on the drive for a product line that
has Zero Defects will grow in intensity. These
efforts will provide both Signetics and our customers with the ability to achieve the mubJai
goal of improved product quality.
The Customer Specific Quality Assurance department has monitored PPM progress, which
can be seen in Figure 4. We are pleased with
the progress that has been made, and expect
to achieve even more impressive results as the
procedures for accomplishing these tasks are
fine tuned.
In _ _
_
.. P.....
por-
4
0.5
~~~~~~~~~
len
1880
1881
1882
1883
1984
1985
1886
1887
1988
Figure 4. Programmable Logic EPQ (Estimated Process Quality)
~~lJary 1990
~
32
Signetics Programmable Logic Devices
Quality and Reliability
The Customer Specific Reliability Department
has established a" oogoing Infant Mort.ality
Monitor. This monitor is used to determine and
drive ongoing Corrective Action for the purposes of continuously improving product reliability.
The real measure of any quality improvement
program is the result that our customers see.
The meaning of Quality is more than just working circuits. It means commitment to OJ Time
Delivaryat the RightPlaceof the RightOuantity
of the Right Product at the Agreed Upon Price.
January 1990
33
Signetics Programmable Logic Devices
Quality and Reliability
CMOS RELIABILITY
INFORMATION
All Signetics' EPROM die are designed as low
power UV light erasable and electrically programmable read only memories. They have
been designed to perform over military and
commercial temperature ranges. These die are
assembled in EPROM packages that comply
with industry standard packages: CERDIP
(Quartz window), Plastic DIP (One Time Programmable) and Plastic Leaded Chip Carrier
(One Time Programmable).
The following descriptions are of the tests and
calculations performed on each device organization and package type to validate the quality
and reliability of the CMOS design and technology. All described tests are performed on each
package type, with the exception of the 'Program-erase cycling' test for the One Time Programmable devices.
ELECTROSTATIC DISCHARGE
PROTECTION (ESD)
This test is performed to validate the producfs
tolerance to electrostatic discharge damage.
Both MIL-ST0-883 criteria (human body model) and mechanical model charged device test
are performed.
HIGH TEMPERATURE STORAGE
LIFE TEST (HTSL)
DYNAMIC LOW TEMPERATURE
LIFE TEST (DLTL)
PROGRAM-ERASE CYCLING
AND PROGRAMMABILITY
This test is performed at -lO"C to detect the
effects of hot electron injection into the gate
oxide as well as package-related failures (Le.,
metal corrosion). The biasing and docking conditions for this test are identical to the DHTL #1
test
All four power supply voltage combinations for
Vee and Vpp are tested for programmability
(Vee =6.0V ± O.25V and Vpp =12.5V ± 0.5V in
program mode). The number of possible program/erase cydes is then tested to establish
program-erase cyding expectations.
TEMPERATURE CYCLE (TMCL)
This test consists of performing 200 cycles of
ambient air temperature of the chamber and
housing the unbiased subject devices from
-OSOC to +150°C and back. The 200 cycles are
performed at 20 minutes per cyde.
DYNAMIC HIGH TEMPERATURE
LIFE TEST (DHTL #1)
This test is used to accelerate failure mechanisms by operating the devices at 125°C ambient temperature with worst-case specified
power supply voltages of Vee and Vpp at 5.5V.
The memory is sequentially addressed to exercise the fully-loaded outputs. A checkerboard
complement data pattern is used to simulate
random patterns expected during actual use.
DYNAMIC HIGH TEMPERATURE
LIFE TEST (DHTL #2)
Anotherpopularname forthis test is data retention bake. This process is used to thermally accelerate charge loss from the floating gate. The
test is performed by subjecting devices that
contain a 100% programmed data pattem to a
25O"C bake with no applied electrical bias or
clocks.
This test is used to accelerate oxide breakdown
failures and to further accelerate the failure
mechanisms of DHTL #1. The test setup is
identical to the one used for the DHTL #1 test
except the temperature is 150"C and the Vee
and Vpppower supply voltages are 6.5V, resu~
ing in a 20% inaease over the specified operational electrical field across the gate oxides of
the device (1.25mVlcm for 325A oxide thick-
In addition to charge loss, this test is used to detect mechanical reliability (Le., bond integrity)
and process instability.
ness). This represents a 55 X electrical field induced acceleration in addition to the thermal
acceleration at 15O"C.
January 1990
34
FAILURE RATE PREDICTIONS
In preparation for the various life tests, a 168
hour, 125°C, 5.5V production bum-in is performed on the devices. The infant mortality rejects are removed from the population in order
to develop long-term failure rate information
during the random failure rate portion of the device life cyde.
The failure rate calculation combines all failure
mechanisms by activation energies and associated device hours for the 125°C, 5.5V Dynamic Life Test (DHTL #1), the 150"C, 6.5V
Dynamic Life Test (DHTL #2), the 15O"C, 7.5V
Static Life Test and the 250°C Bake.
The activation energies forthe various EPROM
failure mechanisms are:
Defective bit
0.6eV
charge gainlloss
(electron hopping conduction)
Oxide breakdown
0.3eV
Silicon defects
0.3eV
Contamination
1.0-1.2eV
Intrinsic charge loss
1.4eV
NOTE:
The combined failure rate forthe stresses is the
sum of failure rates by activation energies.
Signetics Programmable Logic Devices
Quality and Reliability
METHODS OF FAILURE RATE
CALCULATIONS
An additional 55 X acceleration factor should
be added !or !he 150"C/6.5V dynamic life test
Actual Device Hours = Number of Devices x
Number of Hours. In order to determine the
Equivalent Hours derated to a given operation
temperature, the junction temperatures of the
devices should be calculated using the known
due to the time-dependent oxide failure acceleration (20% higher than specified power supply voltage).
thermal resistance of the package (9JA ) and the
power dissipation of the devices:
(1)
Using the Arrhenius relation, the test temperatura and the derated operation temperature will
yield the thermal acceleration factor from
T, to T2:
A.exp[~J
R,
R; = A.exp[ EAJ
[EAJ [1
= exp
k
1]
r;-;:;
kT2
k = 8.617 X 10-6 eViKelvin (BoI12mann's
A
=
R, =
R. =
EA =
T, =
T. =
constant)
Proportionality constant for a given
failure mechanism
mean time to failure@T,
mean time to failure @ T.
activation energy for the failure
mechanism
operating temperature
life test temperature
January 1990
Multiplying the actual device hours by the acceleration factor for each failure mechanism
will result in the equivalent hours.
Poisson statistics are applied to estimate the
performance of the population from the life test
results of a sample test. This is useful when the
probability of failures is small and the failures
occur randomly in time. A commonly used formula for estimating the failure rate is the 'chisquared' equation:
x· x 100%
Fe= -
(3)
2nt
(2)
Fc = calculated failure rate estimate
(in %11000 hrs) at upper confidence limit
X·
Equation 3 will calculate the estimated failure
rates/l000 hrs for 60% confidence level (industry standard) for each failure mechanism.
THE SURE PROGRAM
The SURE (Systematic Uniform Reliability
Evaluation) program audits/monitors products
from all Signetics' divisions under a variety of
accelerated environmental stress conditions.
this program, first introduced in 1964, has
evolved to suit changing product complexities
and performance requirements.
The SURE program has two major functions:
long-term accelerated stress performance audit and a short-term accelerated stress monitor.
In the case of Memory products, samples are
selected that represent product groups from ali
wafer fabrication and assembly locations.
= 'chi-squared" value for 2FA + 2 degrees
offreedom for DC where FA is the number
of actual failures
(X2 comes from
available tables for a known DC)
n
t
= 1-8, where 8 is the confidence limit
(8 is stated in %).
= number of units in test
= test time in thousands of hours
(equivalent)
35
SURE REPORTS
The data from these test matrices provides a
basic understanding of product capability, an
indication of major failure mechanisms and an
estimated failure rate resulting from each
stress. This data is compiled periodically and is
available to customers upon request
Signefics
Section 3
PAL ®-Type Device
Data Sheets
Programmable Logic Devices
INDEX
Series 20
PLHS16L8A1B PAL®-Type Devices (16 x 64 x 8) ......................
PLUS16R8D/-7 PAL®-Type Devices
(Includes PLUS 16L8D/-7, PLUS 16R4D/-7,
PLUS16R6D/-7, PLUS16R8D/-7) " .....................
PHD16N8-5
Programmable High Speed Decoder (16 x 16 x 8) ..........
PLHS18P8A1B PAL®-Type Devices .................................
PLC18V8Z11
39
46
60
68
PAL®-Type Devices ................................. 75
Series 24
10H20EV81
10020EV8
ECL PAL ®-Type Devices ............................. 87
PLUS20R8D/-7 PAL®-Type Devices
(Includes PLUS20L8D/-7, PLUS20R4D/-7,
PLUS20R6D/-7, PLUS20R8D/-7) ...................... 101
Series 68
PHD48N22-8
Programmable High Speed Decoder (48 x 73 x 22) ........ 115
Signefics
Document No. 853-0960
ECN No.
97887
Date of Issue October 16, 1989
Status
Product Specification
-
PLHS 16L8AJB
Programmable AND Array Logic
(16 x 64 x 8)
-
,programmable LogiC ueVlces
DESCRIPTION
The PLHS16L8A is a high-speed "A" version, and the PLHS16L8B is a very highspeed "B"version PAL@-typedevice. The
sum of products (AND-OR) architecture is
comprised of 64 AND gates and 8 OR
gates. The Signetics PLHS16L8AIB devices offer 100% functional compatibility
with other PAL 16L8 devices. Specified at
a tpD of 20ns (maximum), the PLHS 16L8A
is 20% faster than other "A" version PAL
16L8 devices, and consumes 20% less
power than most other "A" speed 16L8devices. The PLHS16L8B, specffied at
155mA Icc (maximum), consumes 20%
less power than other "B" version PAL
16L8 devices.
All AND gates are linked to 10 dedicated
inputs, 6 bidirectionalI/O and 2 dedicated
outputs. On-chip buffers couple eithertrue
(I, B) or complement (1. "8) input polarities
to all AND gates. The 64 AND gates are
separated into eight groups of eight product terms each. Within each group, seven
of the AND terms are OR'ed together,
while the eighth is used to control the
3-State function olthe bidirectionalI/O. All
outputs (bidirectional and dedicated) are
inverting.
In the virgin state, the AND array fuses are
back-to-back CB-EB diode pairs which act
as open connections. Current is avalanched across individual diode pairs during fusing, which essentially short circuits
the EB diode and provides the connection
for the associated product term.
Order codes are listed in the Ordering
Information Table.
PIN CONFIGURATIONS
N Package
FEATURES
• "A" version 100% functionally and
pin-for-pin compatible with
AmPAL16L8A, MMI PAL16L8A,
TlBPAL16L8-25, and
NSC PAL16LBA devices
- 20% faster than other "A" version
PAL devices
- t pD
=20ns (max)
• "B" version 100% functionally and
pin-for-pin compatible with
AmPAL16L8B, MMI PAL16L8B,
TlBPAL16L8-15 and NSC PAL1618B
devices
- Consumes 20% less power than
other "B" version PAL devices
- 155mA Icc (worst case)
- 110 propagation delay: 15ns (max)
("B" verSion)
A Package
10 vee 07
• Field-programmable
• 10 dedicated inputs
• 8 outputs
- 6 bidirectional 110
- 2 dedicated outputs
Ia GND 19 00 B,
APPLICATIONS
• Individual 3-State control of all
outputs
.100% functional replacement for
20-pin 16L8 combinatorial PAL devicas
• 64 AND gates/product terms
• Random logic
• Security fuse
• Code converters
• Fault detectors
The PLHS 16L8AIB is field-programmable, allowing the user to quickly generate custom patterns using standard
programming equipment.
• Function generators
• Address mapping/decoding
• Multiplexing
®PAL is a registered trademark of Monolithic Memories. Inc., a wholly owned subsidiary of Advanced Micro DevIces, Inc.
PHILIPS
39
Product Specification
Signetics Programmable Logic Devices
PLHS16L8A/B
Programmable AND Array Logic (16 x 64 x 8)
FPLA LOGIC DIAGRAM
PlHS16LBAIB
15
~~12100
I.
18
o
INPUTS (<1-31)
31
NOTES:
1. All unprogrammed or virgin "AND" gate locations are pulled to logic "I".
2.
Programmable connections.
October 16, 1989
40
Product Specification
Signetics Programmable Logic Devices
PLHS16L8A/B
Programmable AND Array Logic (16 x 64 x 8)
FUNCTIONAL DIAGRAM
----------Po
P e a - - - - - - - - - - LOGIC TERIIS
~
-Q.>
-------------
I. -Q.>
8,
~
lie
<1-
l4¥ ut
------------
'(
,
,
,
B,
ORDERING INFORMATION
DESCRIPTION
THERMAL RATINGS
TEMPERATURE
ORDER CODE
20--Pin Plastic Dual In-Line (300mil-wide)
PLHS16LBAN, PLHS16LBBN
Maximum junction
150°C
20--Pin Plastic Leaded Chip Carrier
PLHS16LBAA,PLHS16L8BA
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
Vee
Supply voltage
VIN
Input voltage
VOUT
Output voltage
VOUTPRG
Output voltage (programming)
RATINGS
UNIT
-0.5 to +1
Voc
-0.5 to +5.5
Voc
-0.5 to Vee Max
Voc
+21
Voc
--30 to +5
mA
IJN
Input current
lOUT
Output current
+100
mA
IOUTPRG
Output current (programming)
+170
mA
TA
Operating temperature range
oto +75
°C
TSTG
Storage temperature range
~5to+150
°C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
October 16,1989
41
Product Specification
Signetics Programmable Logic Devices
PlHS16l8A/B
Programmable AND Array logic (16 x 64 x 8)
DC ELECTRICAL CHARACTERISTICS oOc -< TAS +75°C, 4.75 S
Vee < 5.25V
-
UMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ'
Max
UNIT
+0.8
V
Input voltage2
V il
Low
Vee=MIN
VIH
Vr:;
High
Vee = MAX
Vee = MIN, liN =-18mA
Clamp
V
+2.0
-{).9
-1.2
V
+0.50
V
Output voltage
Vee = MIN, V IN = V IH or Vil
VOL
V OH
low
High
10l = +24mA
10H = --3.2mA
+2.4
V
+3.5
Input current
Vee = MAX
III
Low
VIN = +0.40V
IIH
II
High
High
VIN = +2.7V
-20
VIN = +5.5V
-100
~
+25
+1.0
rnA
~
~
Output current
Vee = MAX, V il =
o.av, VIH = 2.0V
10ZH
Output leakage
VOUT = +2.7V
+100
lOll
VOUT = +0.40V
VOUT = +0.5V
-50
~
los
Output leakage
Short circuit 3
--BO
-90
rnA
lee
Vee current
Vee = MAX, All inputs = GND
100
155
rnA
Vee = +5V
VIN = 2.0V@f= lMHz
VOUT = 2.0V @ f = 1MHz
6
--30
Capacllance4
CIN
COUT
Input
1/0
9
pF
pF
NOTES:
1. Typical limits are at Vee = 5.0V and TA = +25°C.
2. These are absclute values with respect to device ground and all overshoots due to system or tester noise are included.
3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has
been chosen to avoid test problems caused by tester ground degradation.
4. These parameters are not 100% tested, but are periodically sampled.
October 16, 1989
42
Product Specification
Signetics Programmable Logic Devices
PLHS16L8A/B
Programmable AND Array Logic (16 x 64 x 8)
AC ELECTRICAL CHARACTERISTICS OOC 5, TA 5, +75°C
i
i
I
SYMBOL
PARAMETER
I
-
4755, Vee < 5.25V, R1 = 2000, R2 =3900
I
FROM
TO
I
CONDITIONS
I
L!MITS
PLHS16L8B
PLHS16L8A
TEST
Min
Typ
Max
Min
I
UNIT
Typ
Max
!Po
Propagation delay
Output±
Input±
CL = SOpF
14
20
12
15
ns
tEA
Output enable
Output-
Input±
CL = SOpF
14
20
12
15
ns
tER
Output disable
Output +
Input±
CL = 5pF
14
20
12
15
ns
NOTES:
1. Typical limits are at Vee = 5.0V and T A = +25°C.
2. (po is tested with switch S1 closed and CL = 50pF.
3. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and 51 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL .5pF. High-to-+iigh impedance tests are made to an output
voltage of VOH = ...().5V with 51 open, and Low-to-+iigh impedance tests are made to the VOL = +0.5V level with 51 closed.
VIRGIN STATE
TIMING DEFINITIONS
A factory shipped virgin device contains all
fusible links open, such that:
1. All outputs are enabled.
SYMBOL
PARAMETER
!Po
Input to output propagation
delay.
IER
Input to output disable
(3-State) delay (Output
Disable).
lEA
Input to Output Enable
delay (Output Enable).
2. All p--terms are enabled in the AND array.
TIMING DIAGRAM
WAVEFORM
Oc,tober 16, 1989
INPUTS
OUTPUTS
MUST BE
STEADY
WlUBE
WAVEFORM
~
}]) ([
STEADY
43
INPUTS
OUTPUTS
DON'T CARE;
ANY CHANGE
PERMlTTBl
CHANGING;
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
"OFF"STATE
Signetics Programmable Logic Devices
Product Specification
PLHS16L8A/B
Programmable AND Array Logic (16 x 64 x 8)
AC TEST LOAD CIRCUIT
VOLTAGE WAVEFORMS
R,
Byr,---------r--,
INPUTS
BZ~~-·
OUTPUTS
.,..
MEASUREMENTS:
AU drcuil delays are measured at the +1.5V Jevel of
Inputs and outputs, unless otherwise specified.
NOTE:
C, and C2 are to bypass
Vee to GNO.
Input Pulses
LOGIC PROGRAMMING
PLHS 16L8AlB logic designs can be generated
using any commercially available, JEDEC
standard design software that supports the
16L8 architecture. No JEDEC fuse map conversion or translation is necessary when using
the PLHSI6L8AlB.
To implement the desired logic functions, each
logic variable (I, B, P and D) from the logic
equations is assigned a symbol. TRUE (High),
COMPLEMENT (Low), DON'T CARE and
INACTIVE symbols are defined below.
PLHSI6L8NB designs can also be generated
using the program table format, detailed on the
following page. This program table entry (PTE)
format is supported on the Signetics AMAZE
PLD design software. AMAZE is available free
of charge to qualified users.
I,B1 I'B 1I'B I,B1 I,B1 I'B
"AND" ARRAY - (I, B)
~B
~
I,ll
1
I,ll
II
I,ll
'8
P,D
P,D
STATE
STATE
INAcnVE 2
TRUE
P,D
I
STATE
P,D
STATE
DONTCARE'
NOTE:
1. This is the initial state of all diodes pairs.
2. All unused product terms must be programmed with all pairs of diodes in the I NACTIVE state (all fuses on an unused p-term must be
programmed).
October 16, 1989
44
~
[
"i>
~
, "tI
OR (FIXED)
INACTIVE
I,B
I,B
DON'T CARE
SIGNETICS DEVICE #
CF (XXXX)
CUSTOMER SYMBOLIZED PART #
TOTAL NUMBER OF PARTS
PROGRAM TABLE #
REV
i1!fl ~!I SIll I!l~ g:s: ¥:l!l
~~
"'~
DATE
IU
t~ t~
f:t
it:!: $~ II!~ II! III
0
H
L
-
I DIRECTION
I AClIVE OUTPU
I,B(QI
I NOTUSED
D
A
k"
Care H In the virgin state.
3. AH p-terms are active until progranmed
u: I:l!! I!lfll Ill!:l Illtll ~t:! I:!~ Ill; ......
r
m
all pairs of fuses In the INACTIVE state (all fuses
to the fixed nature of the device architecture.
.
~
..w
"'~
.... ...... . .....
~
"'~ o
J:%lm-I
.
.
....
.
~
'"
:z
.
.
.Z
~
::
S»
2:
'<
w
;;;
3
3
S»
"8
f·
""I
»
z
5. Data cann01 be entered Into the OR array field due
~
Ij
~
Ol
~
X
(X)
'tI
;;;
f0-
~
w
.:
'"
;:
c:
Ul
to
-
~
; 1\ 1\1\ 1\1\ 1\1\ 1\ 1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ !\I\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\1\ 1\1\ 1\· •• •• •• " ....
;;; 1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\ ,\ 1\1\ 1\1\ 1\ 1\ 1\1\ 1\ 1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\ 1\ 1\1\ 1\1\ 1\1\ 1\ 1\ • » ,. ,.,. 1\1\ 1\]\ 1\,\ 1\1\ .. 0
,.,. ,.,. "1\ 1\1\ 1\ 1\ 1\1\ f\ 1\ 1\1\ 1\1\ 1\1\ ~ ~ 0
::1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ ]\1\ .1\1\ 1\ 1\ 1\1\ 1\]\ 1\1\ 1\1\ 1\1\ 1\ 1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\ 1\ 1\ •
'tI :c
;;;1\ 1\1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\1\ 1\1\ 1\ 1\ 1\1\ 1\1\ 1\1\ 1\ 1\ 1\1\ 1\1\ 1\1\ 1\ ,. ,.,. ,.,.
-:;;
"1\ 1\ 1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\ 1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ .. c:
-I
,.
w
III
><
1\,.
~I\ 1\1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\ 1\1\ 1\1\ 1\ 1\ 1\1\ 1\1\ 1\1\
"1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\ 1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\ 1\ )\1\ 1\1\ 1\1\ 1\1\ 1\1\ to m
,g
,.
1\
..
1\
1\
1\1\
"
.
1\1\
1\1\
1\1\
1\1\
1\1\
1\
1\
1\
.:1\ 1\1\ 1\1\ 1\ 1\
.1\1\
1\1\ 1\1\ 1\1\ 1\1\ 1\ )\1\ 1\1\ 1\1\ 1\ 1\
"1\ 1\1\ 1\1\ 1\1\ 1\1\ ]\1\
,. ,. "1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ ]\1\ 1\1\ ]\1\ )\1\ )\1\ 1\1\ 1\1\ 1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\ ~ .9
;:1\ 1\1\ 1\1\ 1\1\ 1\ ,.
;; .. ,. ........ ,. "1\1\1\1\1\1\1\ 1\ 1\1\ 1\1\1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\ 1\1\1\ 1\1\]\1\ 1\ 1\]\1\)\1\)\1\ 1\ 1\1\1\1\ 1\ 1\)\1\1\ 1\1\1\1\ 1\1\ 1\ ..
.... . .
, _____
aJ
on an unused p-term must be programmed).
'"
f-------
~
o~rI8rwise.
4. AU unused produd: tenns must be prograrrmed with
I
I
I
I
I
I
...
f-------
S»
»
1. The FPLA is shipped with aJllinks open.
2. Unused I and B bits In the AND array exist as Don't
....
~
3:
Gl
::
f------- ...
.
..
f------- .. -
:II
"'C
""I
0
CO
:II
0
~-------,-------- NOTES:
PURCHASE ORDER #
VARIABLE
NAME
I
AND
CUSTOMER NAME
.
... ....
.... . ....
.,.
...
."
"'C
rJ:
"t1
en
.....
ag.
r(X)
-g
o.
Ol
»
m
~
(J)
[
,;::>
Signefics
PLUS16R80/-7 SERIES
Document No. 853-1358
ECN No.
98103
Date of Issue November 14, 1989
Status
Product Specification
PAL®-Type Devices
16L8, 16R8, 16R6, 16R4
Programmable Logic Devices
FEATURES
DESCRIPTION
• Ultra high-speed
- t pD 7.5ns and fMAX 74MHz for
the PLUS16R8-7 Series
The Signetics PLUS16XX family consists
of ultra high-speed 7.5ns and 10ns versions of Series 20 PAL devices.
- t pD = 10ns and fMAX = 60 MHz for
the PLUS16R8D Series
The PLUS16XX family is 100% functional
and pin-compatible with the 16L8, 16R8,
16R6, and 16R4 Series devices.
=
=
• 100% functionally and pin-far-pin
compatible with Industry standard
20-pin PAL ICs
• Power-up reset function to enhance
state machine design and testabilIty
• Design support provided via
AMAZE and other CAD tools for
Series 20 PAL devices
• Field-programmable on Industry
standard programmers
• Security fuse
• Individual 3-State control of all
outputs
DEVICE NUMBER
The sum of products (AND-OR) architecture is comprised of 64 programmable
AND gates and 8 fixed OR gates. Multiple
bidirectional pins provide variable inpuV
output pin ratios.lndividuaI3-State control
of all outputs and registers with feedback
(R8, R6, R4) is also provided. Proprietary
designs can be protected by programming
the security fuse.
The PLUS16R8, R6, and R4 have D-type
flip-flops which are loaded on the
Low-to-High transition of the clock input.
In order to facilitate state machine design
and testing, a power-up reset function has
been incorporated into these devices to
DEDICATED
INPUTS
reset all internal registers to active-Low after a specific period of time.
The Signetics State-of-the-Art oxide isolation Bipolar fabrication process is
employed to achieve high-performance
operation.
The PLUS16XX family of devices are field
programmable, enabling the user to
quickly generate custom patterns using
standard programming equipment. See
the programmer chart for qualified programmers.
The AMAZE software package from
Signetics supports easy design entry for
the PLUS16XX series as well as other
PLD devices from Signetics. The
PLUS16XX series are also supported by
other standard CAD tools for PAL -type devices.
Order codes are listed in the Ordering
Information table.
COMBINATORIAL
OUTPUTS
REGISTERED
OUTPUTS
PLUS16L8
10
8(6110)
0
PLUS16R8
8
0
8
PLUS16R6
8
2110
6
PLUS16R4
8
4110
4
®pAL is a registered trademark of Monolithic Memories, inc., a wholly owned stbsldiary of Advanced Micro Devices. Inc.
PHILIPS
46
Product Specification
Signetics Programmable Logic Devices
PAL-Type Devices
PLUS16R8D/-7 SERIES
16L8, 16R8, 16R6,16R4
PIN CONFIGURATIONS
PLiJSi6LB
PLUS,tifi8
20
Vee
B,
Bs
B,
B,
B,
B,
O.
L-_ _ _ _ _----( 11
"
PLUS16L8
PLUS16R8
10
elK Vee
Or
B,
SYMBOL
DESCRIPTION
I
Dedicated Input
Dedicated cormlnatorlal Output
Registered output
Bidirectional (inpuVoutput)
Clock Input
Output Enct>le
Supply Vo~ag.
Ground
o
Q
B
ClK
OE
Vee
GND
November 14, 1989
0,
Bs
Qs
B,
Q,
B,
Q,
B,
Q,
SYMBOL
I
o
Q
B
ClK
OE
VCC
GND
DESCRIPTION
Dedicated Input
Dedicated corminatorial Output
Registered output
Bidirectional (input/output)
Clock input
Output Enable
Supply Voltage
Ground
47
Signetics Programmable Logic Devices
Product Specification
PAL-Type Devices
PLUS16R8D/-7 SERIES
16L8, 16R8, 16R6,16R4
PIN CONFIGURATIONS
PLUS16R4
PLUS16R6
elK
1
Vee
.,
elK
1
GND
10
a,
D,
0,
D,
D,
D,
·0
PLUS16R4
PLUS16R6
SYMBOL
Vee
DESCRIPTION
Dedicated Input
Dedicated corminatorial Output
Registered output
Bidirectional (input/output)
Clock input
Output EnIDls
Supply Voltage
GND
Ground
I
o
o
B
elK
OE
November 14. 1989
0,
B,
0,
05
0,
0,
0,
0,
0,
Q,
SYMBOL
DESCRIPTION
I
D
Dedicated Input
Dedicated cormi natorial Output
Registered output
Bidirectional (input/output)
Clock input
Output Enable
Supply Voltage
Ground
a
B
elK
DE
Vee
GND
48
Product Specification
Signetics Programmable Logic Devices
PAL-Type Devices
PLUS16R8D/-7 SERIES
16L8, 16R8, 16R6, 16R4
PLUS16L8
LOGIC DIAGRAM
12
Bs
13
!!i
...ffi
B4
It
g
c
~
B3
15
B2
31
INPUTS (0-31)
NOTES:
1. All unprogrammed or virgIn -AND" gate )ocations are pulled to logic "0".
2.
.zt
Programmable connections.
November 14, 1989
49
Product Specification
Signetics Programmable Logic Devices
PAL-Type Devices
PLUS16R8D/-7 SERIES
16L8, 16R8, 16R6, 16R4
PLUS16RB
LOGIC DIAGRAM
12
~
!Il
....ffi
....
(.)
13
:>
0
0
II:
03
31
INPUTS (0-31)
NOTES:
1.
2.
All unprogrammed or virgin "AND" gate locations are pulled to logic ''0".
F Programmable connections.
November 14, 1989
50
Product Specification
Signetics Programmable Logic Devices
PAL-Type Devices
PLUS16R8D/-7 SERIES
16L8,16R8, 16R6, 16R4
PLUS16R6
LOGIC DIAGRAM
I
ClK
11
as
1:1
04
1!i
~
13
t;
~
Q
~
03
14
02
I , '~""
31
INPUTS (G-31)
1101£8:
1. All unprogrammed Of' virgin -AND" gate locations are pulled to logic "0".
2.
~f programnabie amnectlons.
November 14, 1989
51
--, 01
Product Specification
Signetics Programmable Logic Devices
PAL-Type Devices
PlUS16R8D/-7 SERIES
16l8,16R8,16R6,16R4
PLUS16R4
LOGIC DIAGRAM
12
~
!IIa:
w
....
13
....0
"0
0
03
II:
14
02
31
INPUTS (0-31)
NOTES:
1.
2.
All unprogrammed or virgin MAND" gate locations are pulled to logic "0",
:\ Programmable connections.
November 14, 1989
52
Product Specification
Signetics Programmable Logic Devices
PAL-Type Devices
16L8, 16R8, 16R6, 16R4
PLUS16R8D/-7 SERIES
FUNCTIONAL DESCRIPTIONS
Programmable Bidirectional Pins
The PLUS16XX series utilizes the familiar
sum-<>f-products implementation oonsisting of
a programmable AND array and a fixed OR
array. These devices are capable of replacing
an equivalent of four or more SSI/MSI integrated circuits to reduce package count and
board area occupancy, consequently improving reliability and design cycle over Standard
Cell or gate array options. By programming the
security fuse, proprietary designs can be protected from duplication.
The PLUS16XX products feature variable
InputlOutput ratios. In acklition to 8 dedicated
inputs, each combinatorial output pin of the
registered devices can be individually programmedas an inputoroutput. The PLUS16L8
provides 10 dedicated inputs and 6 Bidirectional 1/0 lines that can be individually configured
as inputs or outputs.
The PLUS16XX series consists of four PALtype devices. Depending on the particular device type, there are a variable number of
combinatorial and registered outputs available
to the designer. The PLUS 16L8 is a oombinatorial part with 8 user configurable outputs (6 bidirectional), while the other three devices,
PLUS16R8, PLUS16R6, PLUS16R4, have
respectively 8, 6, and 4 output registers.
3-State Outputs
The PLUS16XX series devices also feature
3-Stateoutput buffers on each output pin wh ich
can be programmed for individual control of all
outputs. The registered outputs (an) are oontrolled by an external input (/oE), and the combinatorial outputs (On, Bn) use a product term
to oontrol the enable function.
Output Registers
The PLUS16R8 has 8 output registers, the
16R6 has 6, and the 16R4 has 4. Each output
register is a O-type ftip--llop which is loaded on
the Low-to-High transition of the clock input.
These output registers are capable of feeding
the outputs of the registers back into the array
to facilitate design of synchronous state machines.
Power-up Reset
By resetting all flip-flops to a logic Low, as the
power is turned on, the PLUS16R8, R6, R4enhance state machine design and initialization
capability.
by AMAZE, the PC-based software developmenttool from Signetics. The PLUS16XX famiiy of dev"",. are also supported by standard
CAD tools for PAL devices, including ABEL and
CUPL.
AMAZE is available free of charge to qualified
users.
Logic Programming
Logic designs for PLUS16XX series can be
generated using any commercially available
JEDEC standard design software that supports
the 2O-pin PAL devices. No JEDEC fuse map
conversion or translation is necessary when
transferring designs from slower 20-pin PAL
devices.
To implement the desired logic functions, each
logic variable from the logic equations is assigned a symbol. True (High), Complement
(Low), Don't Care and Inactive symbols are defined below.
Software Support
Like other Programmable Logic Devices from
Signetics, the PLUS 16XX series are supported
AND ARRAY - (I, B)
LB
4" 4" 4" 4"
__
I,B
I,B
__
I,B
P,D
I
I
STATE
INACTIVE', 2
I CODE I
I D I
I
STATE
I,B
1,8
P, D
P,D
IC~DE I
IC~E I
I
VIRGIN STATE
A factory shipped virgin device contains all fusible links intact, such that:
1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.
November 14,1989
I,B
LB
53
STATE
I,B
1,8
P,D
I
STATE
DON'T CARE
I C~DE I
Product Specification
Signetics Programmable Logic Devices
PAL-Type Devices
PlUS16R8D/-7 SERIES
16l8,16R8, 16R6, 16R4
THERMAL RATINGS
ORDERING INFORMATION
TEMPERATURE
ORDER CODE
DESCRIPTION
20-Pin Plastic Dual-In-Une
300m iI-wide
PLUS16R8DN
PLUS16R6DN
PLUS16R4DN
PLUS16L8DN
PLUSI6R8-7N
PLUSI6R8-7N
PLUS 16R4-7N
PLUS 16L8-7N
20-Pin Plastic Leaded Chip Carrier
(PLCC)
PLUS16R8DA
PLUS16R6DA
PLUS16R4DA
PLUS16L8DA
PLUS 16R8-7A
PLUSI6R6--7A
PLUSI6R4-7A
PLUSI6L8-7A
NOTE:
The PLUS16XX series of devices are also processed to military requirements for operation over
the military temperature range. For specifications and ordering information, consult the Signetics
Military Data Book.
ABSOLUTE MAXIMUM RATINGSI
RATINGS
SYMBOL
PARAMETER
Min
Max
UNIT
Vee
Supply voltage
--{l5
+7
Voc
VIN
Input voltage
--{l.5
+5.5
Voc
VOUT
Output voltage
+5.5
Voc
liN
Input currents
+30
mA
lOUT
Output currents
+100
mA
TSTG
Storage temperature range
+150
°c
-30
~5
NOTE:
1. .Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
OPERATING RANGES
RATINGS
SYMBOL
PARAMETER
Vee
Supply voltage
TA
Operating free-air temperature
November 14, 1989
Min
Max
UNIT
+4.75
+5.25
Voc
0
+75
°c
54
Maximum junction
150°C
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
Signetics Programmable Logic Devices
Product Specification
PAL-Type Devices
PLUS16R8D/-7 SERIES
16L8, 16R8, 16R6, 16R4
DC ELECTRICAL CHARACTERISTICS
ooc -<
TA -< +75°C, 4.75 -< Vee -<5.25V
UMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ'
Max
UNIT
0.8
V
Input voltage2
V IL
Low
Vee = Min
V IH
High
Vee = Max
Vie
Clamp
V
2.0
--{l.8
Vee = Min, liN =-18mA
-1.5
V
0.5
V
Output voltage
Vee = Min, VIN = VIH or Vil
VOL
Low
10l = 24mA
VOH
High
10H =~.2 mA
III
LowS
VIN = 0.40V
IIH
HighS
VIN = 2.7V
25
IlA
IlA
II
Maximum input current
VIN = Vee = VeeMAX
100
IlA
100
IlA
V
2.4
Input current
Vee = Max
-250
Output current
Vee = Max
10ZH
Output leakage
V OUT = 2.7V
lOll
Output leakage
VOUT = 0.4V
-100
los
Short circuit", 5
VOUT= OV
~O
Ice
Vee supply current
Vee = Max
IlA
-90
mA
180
mA
CapacitanceS
C IN
CB
Input
110 (B)
Vee = 5V
VOUT = 2.OV
8
pF
VOUT = 2V, f = 1MHz
8
pF
NOTES:
1. All typical values are at Vee = 5V, TA = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Leakage current for bidirectional pins is the worst case of III and lOll or IIH and 10ZH.
4. Test one at a time.
5. Duration of short circuit should not exceed 1 second.
6. These parameters are not 100% tested but periodically sampled.
NOll9mber 14,1989
55
Product Specification
Signetics Programmable Logic Devices
PAL-Type Devices
16L8,16R8,16R6,16R4
PLUS16R8D/-7 SERIES
AC ELECTRICAL CHARACTERISTICS R, = 2000, Rz = 3900, o°c -< TA.s +75°C, 4.75.s Vee .s 5.25V
LIMITS
SYMBOL
PARAMETER
FROM
D
-7
TO
Min'
Max
Min'
UNIT
Max
Pulse Width
IcKH
Clock High
CK+
CK-
5
7
ns
IcKL
Clock Low
CK-
CK+
5
7
ns
IcKP
Period
CK+
CK+
10
14
ns
Setup & Hold time
tiS
Input
Input or
feedback
CK+
7
9
ns
t'H
Input
CK+
Input or
feedback
a
a
ns
Clock
CK±
o±
3
IcKF
Clock3
CK±
0
IpD
Output (20LB, R6, R4j2
I, B
Output
toE'
Output enable4
OE
Output enable
3
B
toE2
Output enable4 ,5
I
Output enable
3
100'
Output disable4
OE
Output disable
1002
Output disable4 ,s
I
Output disable
tSKW
Output
Q
Q
1
IpPR
Power-Up Reset
Vee+
Q+
10
Propagation delay
IcKO
7.5
ns
3
7
ns
7.5
10
ns
3
10
ns
10
3
10
ns
3
B
3
10
ns
3
10
3
10
ns
1
ns
10
ns
6.5
3
Frequency (20R8, R6, R4)
fMAX
. ..
No feedback 11 (IcKL + IcKH)6
100
71.4
MHz
Internal feedback 11 (tiS + IcKF)6
100
62.5
MHz
External feedback 11 (tiS + IcKO)6
74
60.6
MHz
For deflmbons of the terms, please refer to the Timing/Frequency Definitions tables .
NOTES:
1. CL = OpF while measuring minimum output delays.
2. tpo test conditions: CL = 50pF (with jig and scope capacitance), V,H = 3V, V,L = OV, VOH = VOL = 1.5V.
3, tcKF was calculated from measured Internal fMAX .
4. In reference to 3-State outputs, output enable times are tested with CL = 50pF to the 2.0V or O.BV level. Output disable times are tested with
CL = 5pF. High to High-impedence tests are made to an output voltage of V T = VOH-D.5V; Low to High-impedence tests are made to the
VT = VOL +0.5V level.
5. Same function as IoE' and 100', with the difference of using product term control.
6. Not 100% tested, but calculated at initial characterization and at any time a modification in design takes place which may affect the frequency.
November 14, 1989
56
Product Specification
Signetics Programmable Logic Devices
PAL Type Devices
PLUS16R8D/-7 SERIES
16L8, 16R8, 16R6, 16R4
i.
TEST LOAD CIRCUIT
I
VCC
J:D
+5V
I
I
NClUDES SCOPE
AND JIG
CAPACITANCE
R,
I
I
DUT
I
In
o-L-
CK
0---
R2-=
I
Cl
GND
OUTPUT REGISTER SKEW
CK ______~l'r---------------------------3V
- - - - - - - ov
an
(REGISTERED OUTPUll
(REGISTERED
OU~~
3V
- - - - - - - -~"5V
OV
£~KW
OV
-------~
CLOCK TO FEEDBACK PATH
ClK
~
1
I.
November 14,1989
3V
UV
~KF
·1
57
Product Specification
Signetics Programmable Logic Devices
PAL-Type Devices
16L8,16R8,16R6,16R4
PLUS16R8D/-7 SERIES
TIMING DIAGRAMS1, 2
TIMING DEFINITIONS
SYMBOL
I,B
(INPUTS)
r-------------~
,--------------4V
!eKH
'--------------' '---------------~
r----
!eKL
Interval between clock pulses.
4V
!eKP
Clock period.
ov
tiS
Required delay between beginning of valid input and positive transition of clock.
tlH
Required delay between positive transition of clock and end
of valid input data.
!eKF
Delay between positive transition of clock and when intemal
output of flip-flop becomes
valid.
o
!eKO
Delay between positive transition of clock and when outputs
become valid (with OE Low).
IoEl
Delay between beginning of
Output Enable Low and when
outputs become valid.
IoDl
Delay between beginning of
Output Enable High and when
outputs are in the Off-State.
IoE2
Delay between predefined
Output Enable High, and when
combinational outputs become
valid.
IoD2
Delay between predefined
Output Enable Low and when
combinational outputs are in
the Off-State.
tpPR
Delay between Vcc(afterpower-on) and when flip-flop outputs become preset at "1" (internal outputs at "0").
CK
~---.J1----
,---------- 4V
OE
OV
Flip-Flop Outputs
1
~----------------------------------------------+3V
(INPU~S~
...
'.5_V______________________________________________ OV
f.-~---- IPD,-------!.!
O,B
(COMBINATORIAL
OUTPUTS)
'.5V
~
f,:_
_______
...J.~
_ _ _ VOL
too2
------------_
I,B
(OUTPUT
ENABLE) _ _ _ _ _- J
' -___________- J
:1.5V
PARAMETER
Width of input clock pulse.
+3V
OV
Gate Outputs
a
Vcc
tpD
Propagation delay between
combinational inputs and outputs.
vcc
OV
fMAX
O~~~~~~~d~----------~
(REGISTERED
OUTPUTS) ~~~~.J
VOL
+3V
I,B
(INPUTS)
OV
+3V
1.SV
CK
ov
No feedback: Determined by
the minimum clock period,
l/(!eKL + !eKH).
Internal feedback: Determined by the intemal delay
from flip-flop outputs through
the internal feedback and array
to the flip-flop inputs, l/(tls +
!eKF)·
External feedback: Determined by clock-to-output
delay and input setup time,
l/(tls + !eKO)·
NOTES:
1. Input pulse amplitude is OV to 3V.
2. Input rise and fall times are 2.50s.
Power-Up Reset
November 14,1989
FREQUENCY DEFINITIONS
58
Signetics Programmable Logic Devices
Product Specification
PAL-Type Devices
PLUS16R8D/-7 SERIES
16L8, 16R8, 16R6,16R4
PROGRAMMING
The PLUS16XX Series are programmable on conventional programmers for 2O--pin PAL® devices. Refer 10 the following charts for qualified
manufacturers of programmers and software Iools:
PROGRAMMER MANUFACTURER
DATA I/O CORPORATION
10525 WILLOWS ROAD, N.E.
P.O. BOX 97046
REDMOND, WASHINGTON 98073-9746
(BOO)247-5700
STAG MICROSYSTEMS, INC.
1600 WYATI DRIVE
SUITE 3
SANTA CLARA, CALIFORNIA 95054
(408)988-111B
PROGRAMMER MODEL
FAMILY/PINOUT CODES
SYSTEM 29B, LogicPak™ 303A-V04
ADAPTER
303A-OllA-VOB
303A-OllB-V04
UNISITE 40/48, V2.3 (DIP)
V2.5(PLCC)
MODEL 60, BOA/H, V. 13
ZL3O/30A PROGRAMMER
REV.3OA31
PPZ PROGRAMMER
TBA
SOFTWARE MANUFACTURER
16L8-7/16LBD : 18117
16RB-7/16RBD : 18/24
16R6-7/16R6D : 18124
16R4-7/16R4D: 18124
16LB-7/16LBD : 11/29
16RB-7/16RBD : 11/30
16R6-7/16R6D: 11/30
16R4-7/16R4D : 11/30
DEVELOPMENT SYSTEM
SIGNETICS COMPANY
Bll EAST ARQUES AVENUE
P.O. BOX 3409
SUNNYVALE, CALIFORNIA 94088-3409
AMAZE SOFTWARE
REV. 1.7
(408)991-2000
DATAVO
10525 WILLOWS ROAD, N.E.
P.O. BOX 97046
REDMOND, WASHINGTON 9B073-9746
ABELTM SOFTWARE
REV. 1.0 AND LATER
(BOO)247-5700
LOGICAL DEVICES, INC.
1201 NORTHWEST 65TH PLACE
FORT LAUDERDALE, FLORIDA 33309
CUPLTM SOFTWARE
REV. 1.01 AND LATER
(BOO)331-7788
November 14,1989
59
Signefics
PHD16N8-5
Document No.
ECN No.
Date of Issue October 1989
Status
Preliminary Specrrication
Programmable High-Speed
Decoder Logic (16 x 16 x 8)
Programmable Logic Devices
DESCRIPTION
The PHDI6N8-5 is an u~ra fast
Programmable High-speed Decoder featuring a 5ns maximum propagation delay.
The architecture has been optimized
using Philips Components-Signetics
state-of-the-art bipolar oxide isolation
process coupled with titanium-tungsten
fuses to achieve superior speed in any
design.
The PHDI6N8-5 is a single level logic
element comprised of 10 fixed inputs, 8
AND gates, and 8 outputs of which 6 are
bidirectional. This gives the device the
ability to have as many as 16 inputs. Individual 3-State control of all outputs is
also provided.
The device is field-programmable, enablingthe userto quickly generate custom
patterns using standard programming
equipment. Proprietary designs can be
protected by programming the security
fuse.
APPLICATIONS
• High speed memory decoders
The AMAZE software package from
Philips Components-Signetics supports
easy design entry for the PHDI6N8-5 as
well as other PLD devices.
• High speed code detectors
Order codes are listed in the pages
following.
• Machine state decoders
• Random logic
• Peripheral selectors
Ia GND 19 00 B,
• Footprint compatible to 16L8
• Fuse/Footprint compatible to
T1BPAD
A _ Plastic leaded Chip Carrier
PHILIPS
60
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder Logic (16 x 16 x 8)
PHD16N8-5
LOGIC DIAGRAM
1
•
0
8
12
I IPI'"
2.
20
16
...
28
~
....
~
~T
3
.2
Ii
I·.·•. ·.• .
Ii . .
I.····
Vb:
].
I Ii
Ii>
17
1+1'
IP~
I•
Is l(pi.l. I>· I. 1'.'L~
~
r
I.
Ii.
II,ri
I
c·
~
.>. 1,
h>
I"»'
L. ')'
.2
II
if
III
NOTES:
1. All unprogrammed or virgin" AND" gate locations .re pulled to logic "0"
2. -, :.,- Programmlble COlVWctlona
October 1989
~
..5-
lilil.H
9
I..
.2
I.'.
8
I·.··.·
..5-
I·i
7
I
..........
.2
L
6
,
..5-
.....
5
.
~
[In
.
•
1.
~
61
~~
15
I.
13
12
11
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder logic (16 x 16 x 8)
PHD16N8-5
FUNCTIONAL DIAGRAM
THERMAL RATINGS
ORDERING INFORMATION
TEMPERATURE
ORDER CODE
DESCRIPTION
20-Pin Plastic Dual In Une Package; (300m iI-wide)
20-Pin Plastic Leaded Chip Carrier; (35Omil square)
PHD16N8--5N
Maximum junction
150°C
PHD16N8--SA
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
ABSOLUTE MAXIMUM RATINGS1
RATINGS
SYMBOL
PARAMETER
Min
Max
UNIT
Vee
Supply voltage
-{l.5
+7
Voc
VIN
Input voltage
-{l.5
+5.5
Voc
VOUT
Output voltage
+5.5
Voc
liN
Input currents
+30
mA
lOUT
Output currents
+100
mA
TA
Operating temperature range
0
+75
°C
TSTG
Storage temperature range
~5
+150
°C
-30
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
OPERATING RANGES
RATINGS
SYMBOL
PARAMETER
Min
Max
UNIT
Vee
Supply voltage
+4.75
+5.25
Voc
TA
Operating free-air temperature
0
+75
°C
October 1989
62
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder Logic (16 x 16 x 8)
PHD16N8-5
DC ELECTRICAL CHARACTERISTICS OOG s
TA < +75°G, 4.75 S Vee s 5.25V
-
UMIIS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ1
Max
UNIT
0.8
V
-1.5
V
V
Input voltagr
VL
VIH
Vc
Low
High
Clamp
Vee =MIN
Vee = MAX
Vee = MIN, liN =-18mA
2.0
-0.8
Output voltage
VOL
V OH
Low
High
Vee = MIN, VIN = VIH or VIL
10L =+24mA
IOH=-3·2mA
0.5
V
V
-250
I.lA
I.lA
I.lA
2.4
Input current
Vee = MAX
-20
III
Low
V IN = +O.40V
IIH
High
VIN = +2.7V
25
II
High
VIN = Vee = Vee MAX
100
Output current
Vee = MAX
10ZH
Output leakage 3
VouT=+2.7V
100
1021..
VOUT = +O.40V
VOUT = OV
-100
I.lA
I.lA
los
Output leakage 3
Short circuit 4
-90
mA
lee
Vee supply current
180
mA
-30
Vee = MAX
115
Vcc = +5V
VIN = 2.0V@I= lMHz
VOUT = 2.0V@I= lMHz
8
CapacitanceS
GIN
GOUT
Input
110 (B)
8
NOTES:
1.
2.
3.
4.
5.
Typical limits are at Vee = 5.0V and TA = +25°G.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
Leakage current for bidirectional pins is the worst case 01 IlL and 10Z!. or IIH and 10ZH.
Not more than one output should be tested at a time. Duration 01 the short circuit should not be more than one second.
These parameters are not 100% tested, but are periodically sampled.
October 1989
63
pF
pF
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder Logic (16 x 16 x 8)
PHD16N8-5
AC ELECTRICAL CHARACTERISTICS ooc -< TA S +75°C, 4.75 s Vee -< 5.25V, Rl = 200il, R2 = 3900
LIMITS
TEST
PARAMETER
FROM
tpD l
IoE2
IoD2
SYMBOL
Min
Max
UNIT
TO
CONDITIONS
Propagatiqn delay
(I,B)±
Output±
CL =50pF
5
ns
Output Enable
(I, B)±
Output enable
CL = 50pF
10
ns
Output Disable
(I,B)±
Input disable
CL = 5pF
10
ns
NOTES:
1. tpD is tested with switch Sl closed and CL = 50pF.
2. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and Sl is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to--High impedance tests are made to an output voltage of VT = VOH - 0.5V with Sl open, and Low--to--High impedance tests are made to the VT = VOL + O.5V level with Sl closed.
VIRGIN STATE
TIMING DEFINITIONS
A factory shipped virgin device contains all
fusible links open, such that:
SYMBOL
1. All outputs are disabled.
PARAMETER
!PD
Input to output propagation
delay.
IoD
Input to Output Disable
(3-State) delay (Output
Disable).
2. All p--terms are disabled in the AND array.
~
Input to Output Enable
delay (Output Enable).
~'~-1--+--+--r-~~~~
Q
~
1=
~
if
~
IoE
6
~ 5r-+-~-T~--r-+-~-4
'r-4--+--i--r-4--+--i~
3r-+-~-+~--r-+-~-4
2 r-+-~-+~--r-+-~-4
0.
7
8
TEST CONDITIONS: TA - 7s<'C;
Vee - 4.75V; CL - SOpF;
R1 - 200A; R2 - 390Q
Worst-Case Propagation Delay va,
Number of Outputs Switching
TIMING DIAGRAM
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
WAVEFORM
~
STEADY
1» ?K
October 1989
64
INPUTS
OUTPUTS
DON'T CARE;
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
UNEIS HIGH
IMPEDANCE
"OFP'STATE
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder Logic (16 x 16 x 8)
PHD16N8-5
VOLTAGE WAVEFORMS
AC TEST LOAD CIRCUIT
Vee
INPUTS
2.SIlo
2.50.
MEASUREMENTS:
All circuit delays are measured at the + 1.5V level of
inputs and outputs, unless otherwise specified.
Inpul Pulses
LOGIC PROGRAMMING
PHD16N8-5 logic designs can be generated
using any commercially available, JEDEC
standard design software.
"AND" ARRAY - (I, B)
I,B
1
INACTIVE'
~B
I,B
1,8
I,B1 I
1I'B
I,B
'B
~B
P,D
STATE
P,D
I,B 1
P,D
I
STATE
STATE
65
1
I,B
'8
P,D
STATE
DON'TeARE
TRUE
NOTE:
1. This is the initial state.
October 1989
To implement the desired logic functions, each
logic variable (I, B, P and D) from the logic
equations is assigned a symbol. TRUE (High),
COMPLEMENT (Low), DON'T CARE and INACTIVE symbols are defined below.
PHD16N8-5 designs can also be generated
using the program table format, detailed on the
following page. This program table entry (PTE)
format is supported on the Signetics AMAZE
P LD design software. AMAZE is available free
of charge to qualified users.
1-:9
Signetics Programmable Logic Devices
Preliminary Specification
Programmable High-Speed
Decoder Logic (16 x 16 x 8)
PHD16N8-5
PROGRAM TABLE
,
Q
,
[dl
T
E
....
R
M
AND
a.
z
0
I-
• 17
8
1=
.,cw
8
.
i'
~
,
" ...
0
c,
~,
,
,
I
w
a:
~
,
II>
..:
,
I",
I":
~
W
!;(
c
it'
u
I
>
w
~
a:
..,
w
:E
-<
z
a:
w
a:
w
c
a:
0
w
fII
:E
-<
J:
fII
:::I
a:
;:)
r2
u
U
Q.
~
cw
N
~
!.!
>
w
C
fl
~
z
CJ
iii
October 1989
:::I
0
m
:E
>
fII
a:
w
:E
r2fII
;:)
u
a:
~
II:
~
u.
0
..,
w
a:
...J
m
:E
;:)
Z
:E
w
...J
~
r2
m
~
-<
a:
4
I3
I
I
2
!
I
3
1
2
1
0
e
5
41
!
I
5
I
I
I
6
I
I
I
7
I
I
I
8
I
I
I
•
I
I
I
10
I
I
I
11
I
I
12
I
I
I
I
I
I
I
I
I
I
I
m:E
I
I
I
I
a:z
~
I
I
w
...J
w
~-<
1
7
6
5
!4
I
I
I
I
I
I
1
18
17
16 1 ,5
I
I
I
I
I
I
:
]
5
4
I3
2
Q.
66
0
V / / /V / D/
V V V /v' / A/
/'V V V"lL /' L/'"
/ V V /i/ / V
••
13
18
18
17
16
1'5
14
I
I
I
I
I
I
:
NOTES:
1. The PHD16N8-5 is shipped with all links intact.
2. Unused I and B bits in the AND array exist as INACTIVE in the virgin state.
3. All p-terrns are inactive until programmed otherwise.
4. Data cannot be entered into the OR array field due to the fixed nature of the device architecture.
8a:
1
V / A/VV L/'" L
V / / oVV V /
V / / Ai/ V V /
V / / /lD V V /
V V V ViA V V /
V V V /I/ DV /
V 1/1/VIV AV /
i
2
6
A/ / /1/ V V /
V D/ /V V / /
V A/ /1/ V V V
V V o/VV V /
I
3
7
D,/ '/ /V V '/ '/
I
I
•!8
1
I
I
11
2
I
I
PIN
3
OUTPUTS (B, 0)
I
4
"IS
)(
)(
)(
5
I
13
x-
6
I
0
, ..,w 1=~ ::>
, isa: ~ i
,
._---------._--,
~:
OR (FIXED)
INPUTS (B)
INPUT~)
::I
><,
!!;.,
.. [""-
13
D
A
12
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder logic (16 x 16 x 8)
PHD16N8-5
DECODING 1/2 MEG STATIC MEMORY
AH31
A116
AH31
Al16
AH31
AL16
AH31
A1l6
••
••
••
•
•
PHDl6N8
16K X 4
SRAM
PHDl6N8
••
•
•
•
••
•
•
•
•
PHD16N8
PHD16N8
•
16KX 4
SRAM
October 1989
67
Signefics
Document No. 853-0863
ECN No.
97886
Date of Issue October 16, 1989
Status
PLHS 18P8A1B
PAL ®- Type Devices
Product Specification
Programmable Logic Devices
DESCRIPTION
FEATURES
The PLHS18P8A and the PLHS18P8B
are two-level logic elements consisting of
72 AND gates and 8 OR gates with fusible
connections for programming 1/0 polarity
and direction.
• "A" version 100% functionally
compatible with AmPAL 18P8A and
all 16L8, ISP8, ISH8, ISL2, ISH2,
14L4, 14H4, 12LS, 12HS, 10L8, 10H8,
ISL08 and 16H08 "A" speed
PAL-type products
All AND gates are linked to 10 inputs (I)
and 8 bidirectional 1/0 lines (B). These
yield variable 1/0 gate configurations via 8
direction control gates, ranging from 18
inputs to 8 outputs.
On-chip TIC buffers couple either True
(I, B) or Complement (1, B) input polarities
to all AND gates. The 72 AND gates are
separated into 8 groups of 9 each. Each
group of 9 is associated with one bidirectional pin. In each group, eight of the AND
terms are ORed together, while the ninth
is used to establish 1/0 direction. All outputs are individually programmable via an
Ex-QR gate to allow implementation of
ANDIOR or NANDINOR logic functions.
In the virgin state, the AND array fuses are
back-to-back CB-EB diode pairs which
will act as open connections. Current is
avalanched across individual diode pairs
during fusing, which essentially short circuijs the EB diode and provides the connection for the associated product term.
The PLHS18P8AIB is field-programmable, allowing the user to quickly generate custom patterns using standard
programming equipment.
PIN CONFIGURATIONS
N Package
vee
B7
B.
Bs
• "8" version 100% functionally
compatible with AmPAl18P88 and
alllSL8, ISP8, 16H8, 16L2, 16H2,
14L4, 14H4, 12L6, 12H6, 10L8, 10H8,
16L08 and 16H08 "8" speed
PAL-type products
• Field-programmable
B.o
83
0"
B,
Do
GND
.,0 inputs
A Package
• 8 bidirectional 110 lines
10 vee B7
• 72 ANO gates/product terms
- configured into eight groups of
nine
• Programmable output polarity
(3-State output)
• 1/0 propagation delay:
- PLHSI8P8A: 20ns (max)
- PLHSI8P88: 15ns (max)
18 GND 19
Do
B,
• Power dissipation: 500mW (typ)
• TIL compatible
• Security fuse
APPLICATIONS
.'00% functional replacement lor all
20-pin combinatorial PAL devices
• Random logic
• Code converters
Order codes are listed in the Ordering
Information Table.
• Fault detectors
• Function generators
• Address mapping
• Multiplexing
®PAL is a registered trademark of Monolithic Memories. Inc.• a wholly owned subsidiary of Advanced Micro Devices, Inc.
PHILIPS
68
Product Specification
Signetie. Programmable Logic Devices
PLHS18P8A/B
PAL-Type Devices
FPLA LOGIC DIAGRAM
35
NOTES:
1. All unprogrammed or virgin "AND" gate locations are pulled to logic "1".
2."
Programmable connections.
October 16,1989
69
Product Specification
Signetics Programmable Logic Devices
PLHS18P8A/B
PAL-Type Devices
FUNCTIONAL DIAGRAM
17,----------
LOGIC TERMS - - - - - - - - - - Po
--r::?---
I.
~
--------
-------- ------
~.
Bo
~
87
~
. - -...
r
r___
-
-
-
-
-
-
...
---
~
- - - ...
~l...
"
j
~
.J
,
~
y
,
Bo
r
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Dualln-Une (300mil-wide)
20-Pin Plastic Leaded Chip Carrier
PLHS18P8AA,PLHS18P8BA
RATINGS
UNIT
VDC
-D.5 to +5.5
VDC
-D.5 to Vee Max
VDC
+21
VDC
-30 to +5
mA
Output current
+100
mA
IOUTPRG
Output current (programming)
+170
mA
T"
Operating temperature range
o to +75
°C
TSTG
Storage temperature range
-<;5 to +150
°C
Supply voltage
VIN
Input voltage
V OUT
Output voltage
VOUTPRG
Output voltage (programming)
liN
Input current
lOUT
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
October 16, 1989
....
TEMPERATURE
PLHS18P8AN,PLHS18P8BN
-D.5to +7
PARAMETER
Vee
1
THERMAL RATINGS
ORDER CODE
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
II
,
,
70
Maximum junction
150°C
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
Product Specification
Signetics Programmable Logic Devices
PlHS18P8A/B
PAL-Type Devices
DC ELECTRICAL CHARACTERISTICS ooc -< TA -< +75°C, 4.75 -< Vee -< 5.25V
UM!TS
SYMBOL
PARAMETER
PLHS18P8B
PlHS18P8A
TEST CONDITIONS
Min
Typl
Max
Min
Typl
UNIT
Max
Input voltage"
Low
Va.
VH
High
Vc
Clamp
Vee
= MIN
+D.8
Vee = MAX
Vee = MIN, liN = -18mA
+0.8
-{l.9
-{l.g
-1.2
V
V
+2.0
+2.0
-1.2
V
Output voltage
Vee = MIN, VIN = VIH or Vil
VOL
Low
IOl = +24mA
VOH
High
IOH =--;3.2mA
+0.50
+0.50
+2.4
+3.5
+2.4
V
V
+3.5
Input current
Vee = MAX
II.
Low
VIN = +0.40V
IM-I
High
VIN = +2.7V
+25
+25
IJA
IJA
II
High
VIN = +5.5V
+1.0
+1.0
mA
-20
-20
-100
-100
Output current
Vee = MAX, Vil = O.SV, V IH = 2.0V
IOZH
Output leakage
VOUT = +2.7V
+100
+100
IOZL
Output leakage
VOUT = +0.40V
-250
-250
IJA
IJA
los
Short circuit 3
-SO
-90
mA
lee
Vee current
100
155
mA
-25
VOUT = +0.5V
Vee = MAX, All inputs = GND
-SO
--90
100
155
--;30
Capacllance4
Vee = +5V
C IN
Inpul
COUT
1/0
VIN
= 2.0V @ f = 1MHz
VOUT = 2.0V@f= lMHz
6
9
6
pF
9
pF
NOTES:
1. Typical limits are at Vee = 5.0V and T A = +25°C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has
been chosen to "",oid·test problems caused by tester ground degradation.
4. These parameters are not 100% tested, but are periodically sampled.
October 16, 1989
71
Product Specification
Signetics Programmable Logic Devices
PlHS18P8A/B
PAL-Type Devices
AC ELECTRICAL CHARACTERISTICS ooc -< TA -< +75°C, 4.75 -< Vee -< 5.25V, Rl
= 200Q, R2 = 390Q
UMITS
SYMBOL
PARAMETER
TEST
TO
FROM
CONDITIONS
!po
Propagation delay
Min
Min
Typ
Max
14
20
12
15
ns
15
ns
15
ns
Input±
CL = SOpF
14
20
12
CL = 5pF
14
20
12
lEA
Output enable
Output-
IER
Output disable
Oulput+
Input±
CL =SOpF
Max
Typ
Output±
Input±
UNIT
PLHS18P8B
PLHS18P8A
NOTES:
1. Typical limits are at Vee = 5.0V and T A = +25°C.
2. Ipo is lested with switch SI closed and CL = 50pF.
3. For 3-State output; output enable times are lesled with CL = 50pF 10 the 1.5V level, and SI is open for high-impedance 10 High tests and
closed for high-impedance to Low tests. Outpul disable times are tesled with CL • 5pF. High-to-High impedance tests are made to an output
voltage of VOH = --{).5V with SI open, and Low-to-High impedance tests are made to the VOL = +O.5V level with SI closed.
VIRGIN STATE
TIMING DEFINITIONS
A factory shipped virgin device contains all
fusible links open, such that:
1. All outputs are at "H" polarity.
SYMBOL
Input to output propagation
delay.
ItR
Input to output disable
(3-State) delay (Output
Disable).
itA
Input to Output Enable
delay (Output Enable).
2. All outputs are enabled.
3. All p--terms are enabled.
PARAMETER
tpD
TIMING DIAGRAM
WAVEFORM
INPUTS
MUST BE
STEADY
October 16, 1989
OUTPUTS
WAVEFORM
~
jJ) (K
WilL BE
STEADY
72
INPUTS
OUTPUTS
DON'TeARE;
ANY CHANGE
PERMITTED
CHANGING;
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
"OFF'STATE
Product Specification
Signetics Programmable Logic Devices
PLHS18P8A/B
PAL-Type Devices
VOLTAGE WAVEFORMS
AC TEST LOAD CIRCUIT
VCC
L.->
C'y~
A,
By
10
CL
A2
INPUTS
DUT
BZ
GND
1--"--.
OUTPUTS
'::'
MEASUREMENTS:
AN circuh delays are measured at the +1.5V level of
Inputs and outputs, unless otherwise speclUed.
NOTE:
C1 and C2 are 10 bypass
Vee to GND.
Input Pulses
LOGIC PROGRAMMING
OUTPUT POLARITY - (B)
PLHS18P8A1B logic designs can be generated
using Signetics' AMAZE PLD design software
or one of several other commercially available,
JEDEC standard PLD design software packages. Boolean andlor state equation entry is
accepted.
,~.
PLHS18P8A1B logic designs can also be generated using the program table format detailed
on the following pages. This program table
enby (PTE) format is supported by the
Signetics' AMAZE PLD design software (PTP
module). AMAZE is available free of charge to
qualified users.
ACTlVELEVEL
CODE
LOW
ACTlVELEVEL
CODE
IIGH'
H
To implement the desired logic functions, the
state of each logic variable from logic equations
(I, B, 0, P, etc.) is assigned a symbol. The
symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are delined below.
i l'B il'B
"AND" ARRAY - (I, B)
I,B
~B
I,ll'
~B
U
P,D
i
P, D
~B
til'
~B
i
~B
I,ll'
P,D
P,D
STATE
STATE
STATE
STATE
INACTlVE2
I,B
I,ll'
DON'T CARE'
NOTE:
1. This is the initial state of all link pairs.
2. All unused produclterms must be programmed with all pairs of fuses in the INACTIVE state (all fuses on an unused p-term must be
programmed).
October 16, 1989
73
i
;,
m
CUSTOMERNAME _______________________
PURCHASEORDER#____________________
SIGNETICS DEVICE #
CF (XXXX) _____
CUSTOMER SYMBOLIZED PART # _ _ _ _ ___
TOTAL NUMBER OF
~
AND
INACTIve
0
I, B
H
I ~
I ~
I, 11(1)
_
I, B
l
DON'T CARl
_
I
(POl)
OR (FIXED)
I
DIRECTION
0
I
ACTIVE OUTPU
A
I
I
DATE _ _
VA~":LE I~ 1*~~~~~I:i*******~I:l:I*I*~~ltl~lt~~~~I!lal~
!
1!:l~1t:1l:ltlli:ll~
JJ
oC)
NOTES:
1. Th. FPLA I,
t-------- -
PARTS'--_______________
PROGRAMTABLE# ____ REV _ _
"'II
CONTROL
i;--------r--------
&h\lP<>d w~h all links open.
JJ
>
2. Unused I and B bits in the AND array exist as Don't
Care (-lin Ihe virgin ,1Ot•.
3. All p-terlT6 are active until programmed otherwise.
3:
~
4. All unUBed product t.rms must be programmed with
all pairs of IU&8& In tho INACTIVE stat. (all fu...
III
r
m
on an unused p-term must be programrred).
5. Data cannot be entered into the OR array ftekl due
to the fixed nature d the device architecture.
NOT USED
~
r;-
~
'"CI
(1)
o
~1t!1~~Ii)l~~~I~I~I;;FrFI~I;:I;;:F:
1·.,
."
.8
~
~
(1)
CD
C;'
<
.8o·
(1)
5?
.,~.
en
ttl"ltttl"'ltl :"m-<
::
~
-
0>
I:;-
..
~-
~...
-
:;;!
ill~c
o
...
;;
..
.
-
0:
:::
111111111111~s
0;
;;;
;:
-"
-
;;:
;:;
;;; I\I\I\N\J\N\J\N\N\I\I~
0
l\f\l\N\N\N\N\l\I\f\[\J\N\N\N\J\N\N\N\~\f\I\j\j\J\J\j\J\J\f\ >1>1"'1>1>1,.1>101 ...
l\J\f\l\I\I\I\I\I\I\I\I\I\I\I\I\I\I\I\I\\ \ \ 1\1\
~I\I\I\I\ [\1\1\1\1\1\1\1\1\1\[\\ \\ 1\1\
1\1\1\1\1\1\1\1\1\1\1\1\1\»,.,.,. .. ,.,.0
1\1\1\1\ p. .. ,. .. >p.p.o 1\1\\\\ 1\1\
~>~~~»,.c 1\1\1\1\1\1\1\1\ [\[\'\\\ 1\1\
1\1\1\[\ 1\1\1\1\1\1\1\1\ 1\1\\\\ 1\1\
1\1\1\1\ 1\1\1\1\1\[\1\1\ I\!\\\\ I\!\
1\1\1\1\t'\.t\,I\I\p. p. ,.,.> >,.
»,. > ,.1» P I\!\!\'\ \\ \
1\1\1\1\1\1\1\1\1\1\\\\\\
1\1\1\1\1\1\1\1\1\1\:\\\\\
1\1\1\1\1\1\1\\\\\:\\\\
I\I\I\I\I\[\I\I\I\!\I\\\\\
I\I\[\[\[\I\I\!\!\I\\\\\\
0
1\
~
1\
1\
\
~
\4...'i,--ll--\--Hrlc-H_:D
."
0
"tJ
"J,.'
:0
en
o
'~<~+'l-4,t-'k't"'-j.!l'
0 ~
><
Cd
\..l(,+{4n-+'H--j~.9
~
;j
r-
:I:
"0
...I.
n
(XI
"tJ
(XI
»
--
OJ
~
~o.
[o
"
Signetics
Document No. 853-1396
ECN No.
97550
Date of Issue
September 1, 1989
Status
Product Specification
Pro~rammab!e
La9 !e Devices
DESCRIPTION
The PLC18V8Z3Sand PLC18V8Z1 are universal PAL-type devices featuring high performance and virtually zero-standby power for
power sensitive applications. They are reliable,
user-configurable substitutes for discrete TIU
CMOS logic. While compatible with TIL and
HCT logic, the PLC 18V8Z1 can also replace HC
logic over the Vee range of 4.S to S.SV.
The PLC18V8Z is a two-level logic element
comprised of 10 inputs, 74 AND gates (product
terms) and 8 output Macro cells.
Each output features an "Output Macro Cell"
which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. As a result,
the PLC18V8Z is capable of emulating all common 2O-pin PAL devices to reduce documentation, inventory, and manufacturing costs.
A power-up reset function and a Register Preload function have been incorporated in the
PLC18V8Z architecture to facilitate state machine design and testing.
With a standby current of less than I OO~ and
active power consumption of I.SmA/MHz, the
PLC18V8Z is ideally suited for power sensitive
applications in battery operatedlbacked portable instruments and computers.
The PLC18V8Z is also processed to industrial
requirements for operation over an extended
temperature range of -40"C to +85°C and supply voltage of 4.5V to S.Sv.
Ordering information can be found in the
Ordering Information table.
PLC18V8Z35/PLC18V8Z1
Zero Standby Power
Universal PAL ®-type Devices
I,,"
PIN CONFIGURATIONS
FEATURES
• 2D-pln Universal Programmable Array
Logic
N and FA Packages
vec
• Virtually Zero-Stand by-power
F7
• Functional replacement for Series 20
PALdevicea
- IOl 24mA
F6
=
FS
F.
• High-performance CMOS EPROM cell
technology
- Erasable
- Reconflgurable
- 100% testable
Fa
F2
F,
Fa
• 35ns Max propagation delay (comm)
• 40ns Max propagation delay (Industrial)
• Up to 18 Inputs and 81nputloutput
macro cells
GND
IsIOE
N .. Plastic
FA .. Ceramic with Quartz Window
A Package
• Programmable output polarity
12
• Power-up reset on all registers
101
ClKVec F7
• Register Preload capability
• Synchronous PresetiAsynchronous
Reset
• Security fuse to prevent duplication of
proprietary designs
• Design support provided using AMAZE
software development package and
other CAD tools lor PLDs
• Available In 300m ii-wide DIP with quartz
window, plastic DIP (OlP) or PLCC
(OlP)
APPLICATIONS
• Battery powered Instruments
Ie
• Medical Instruments
• Portable communications equipment
Fa
F,
OE
A .. Plastic Leaded Chip Carrier
PIN LABEL DESCRIPTIONS
Dedicated input
B
0
D
• Laptop and pocket computers
• Industrial control
GND 191
F
CLK
Of
Vee
GND
Bidirectional input'output
Dedicated output
Registered output
(D-type flip-flop)
MacrocelllnputiOutput
Clock Input
Output Enable
Supply Voltage
Ground
®PAL is a registered trademark of Monolithic Memories, Inc.• a wholly owned subsidiary of Advanced Micro Devices, Inc.
PHILIPS
75
Product Specification
Signelics Programmable Logic Devices
Zero Standby Power
Universal PAL-Type Devices
PLC18V8Z Series
NOTES:
In the _ranmed or virgin Blat.:
AI calls .... In a conducllve ._.
A! AND gateloc:allons are pulled 10 a Ioglc"C1' (Low).
Output polarity 10 inverting.
September1,1989
Plna 1 and 11 are ccnliglXed .. Inp... 0 and 9, reapedively, via tho ccnfIguratlon coil. The clock and
OE tUnc:l1ena are dlsablod.
All output """"" cola (OMe) are ccntlgurod .. bidirectionalI/O, with tho outpull dlsobled via the
diroctlontorm.
-Donat.. a prcgrammablo call location.
76
Product Specification
Signetics Programmable logic Devices
Zero Standby Power
Universal PAL-Type Devices
PLC18V8Z Series
I
i'~
FUNCTIONAL DIAGRAM
PAL DEVICE TO PLC18VSZ OUTPUT PIN CONFIGURATION
CROSS REFERENCE
PIN
NO.
PlC
lSVSZ
l6R4
l6RP4
l6R6
l6RP6
l6RS
l6RPS
l6l2
l6H2
l6P2
l4l4
l4H4
l4P4
l2L6
l2H6
l2P6
lOLa
10HS
lOPS
1
IciClK
I
ClK
ClK
ClK
I
I
I
I
19
F7
B
B
B
D
I
I
I
0
18
F6
B
B
D
D
I
I
0
0
17
F5
B
D
D
D
I
0
0
0
16
F4
B
D
D
D
0
0
0
0
15
F3
B
D
D
D
0
0
0
0
14
F2
B
D
D
D
I
0
0
0
13
F1
B
B
D
D
I
I
0
0
12
FO
B
B
B
D
I
I
I
0
11
Iw'OE
I
OE
OE
OE
I
I
I
I
The Signetics state-of-the-art Floating-Gate
CMOS EPROM process yields bipolar
equivalent performance at less than one-quarter the power consumption. The erasable nature of the EPROM process enables Signetics
to functionally test the devices prior to shipment
t
--t------,
ARRAY
r--------I
TOALLOMCa
:
I ~~~~~~~~4_~:--4
I
I
I
I
I
I
I
I
The PlC18V8Z series devices have 8individually programmable Output Macro Cells. The 72
AND inputs (or product terms) from the programmable AND array are connected to the 8
OMCs in groups of 9. Eight of the AND terms
are dedicated to logic functions; the ninth is for
asynchronous direction
control, which
enables/disables the respective bidirectional
110 pin. Two product terms are dedicated for
the Synchronous Preset and Asynchronous
Reset functions.
Each OMC can be independently programmed
via 16architecturecontrol bits, AC1 nandAC2n
(one pair per macro cell). Similarly, each OMC
has a programmable output polarity control bit
(Xn). By configuring the pair of architecture
control bits according to the configuration cell
table, 4 different configurations may be implemented. Note that the configuration cell is
automatically programmed based on theOMC
configuration.
..
DESIGN SECURITY
L---------+-+t-
tt
The PlC 18VBZ series devices have a programmable security fuse that controls the access to the data programmed in the device. By
using this programmable feature, proprietary
designs implemented in the device cannot be
copied or retrieved.
TO ALL 0MCa
NOTE:
Denotes a prog........- coIllocallon.
September 1, 1989
18
THE OUTPUT MACRO CELL
(OMC)
FROM AND
I
I
I
12
to the customer. Additionally, this allows
Signetics to extensively stress test, as well as
ensure the threshold voltage of each incjividual
EPROM cell. 100% programming yield is subsequendy guaranteed.
OUTPUT MACRO CELL (OMC)
•
I ~;>________~~~~
CLK
l6lS
l6HS
l6PS
l6PS
77
Product Specification
Signetics Programmable logic Devices
Zero Standby Power
Universal PAL-Type Devices
CONFIGURATION CELL
A single configuration cell controls the functions of Pins 1 and 11. Refer to Functional
Diagram. When the configuration cell is programmed. Pin 1 is a dedicated clock and Pin 11
is dedicated for output enable. When the configuration cell is unprogrammed. Pins 1 and 11
are both dedicated inputs. Note that the output
PLC18V8Z Series
enable for all registered OMCs is commonfrom Pin 11 only. Output enable control of the
bidirectional I/O OMCs is provided from the
AND array via the direction product term.
If anyone OMC is configured as registered. the
configuration cell will be automatically configured (via the design software) to ensure that
the dock and output enable functions are en-
abled on Pins 1 and 11. respectively. If none of
the OMCs are registered. the configuration cell
will be programmed such that Pins 1 and 11 are
dedicated inputs. The programming codes are
as follows:
Pin 1 = CLK. Pin 11 = OE
Pin 1 and Pin 11 = Input
CONTROL CELL CONFIGURATIONS
FUNCTION
AC1,
AC2 N
CONFIG. CELL
COMMENTS
Programmed
Programmed
Programmed
Dedicated clock from Pin 1. OE Control
for all registerd OMCs from Pin 11 only.
Bidirectional 1/0 mode'
Unprogrammed
Unprogrammed
Unprogrammed
Pins 1 and 11 are dedicated inputs.
3-State control from AND array only.
Fixed input mode
Unprogrammed
Programmed
Unprogrammed
Pins 1 and 11 are dedicated inputs.
Programmed
Unprogrammed
Unprogrammed
Pins 1 and 11 are dedicated inputs. The
feedback path (via FMUX) is disabled.
Registered mode
Fixed output mode
NOTE:
3. This is the virgin state as shipped from the factory.
ARCHITECTURE CONTROL-AC1 and AC2
SP
Si1[>---t>o-- F(O). F(U)
OMC CONAGURATION
FIXED OUTPUT
~--------------
fl
lKQ
SP
~I-------
FO)
A
O'E
OMC CONFIGURATION
CONFIGURATION CEll
CONAGURATION CEll
RXEDINPUT
PIN . . ClK
PINII=OE
PIN 1 INPUT
PIN 11 • INPUT
=
NOTE:
A factory shipped unprogrammed device is configured such that:
1. This is the initial unprogrammed state. All cells are in a conductive state.
2. All AND gates are pulled to a logic "0" (Low).
3. Output polarity is inverting.
4. Pins 1 and 11 are configured as inputs 0 and 9. The dock and OE functions are disabled.
5. All Output Macro Cells (OMCs) are configured as bidirectionalI/O. with the outputs disabled via the direction term.
6. This configuration cannot be used if any OMCs are configured as registered (Code = D). The configuration cell will be automatically configured
to ensure that the clock and output enable functions are enabled on Pins 1 and 11. respectively. if anyone OMC is programmed as registered.
September 1.1989
78
Signelics Programmable Logic Devices
Product Specification
Zero Standby Power
Universal PAL-Type Devices
PLC18V8Z Series
ORDERING INFORMATION
DESCRIPTION
OPERATING CONDITIONS
ORDER CODE
Commercial
Temperature Range
PLCI8V8Z35N
± 5% Power Supplies
PLC18V8Z35FA
2O-Pin Plastic Dualln-Une Package
300mil-wide (!Po =35ns)
20-Pin Ceramic Dualln-Une Package
3OOmil-wide with quartz window (tpo =35os)
20-Pin Plastic Leaded Chip Carrier
350mil square (!Po =35os)
PLCI8V8Z35A
2O-Pin Plastic Dualln-Une Package
300mil-wide (!Po =40ns)
20-Pin Ceramic Dualln-Une Package
3OOmil-wide with quartz window (tpo =4005)
Industrial
Temperature Range
PLC18V8ZIN
± 10% Power Supplies
PLC18V8ZIFA
2O-Pin Plastic Leaded Chip Carrier
350mil square (!Po =4Oos)
PLC18V8ZIA
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
Vee
Vee
THERMAL RATINGS
PARAMETER
Supply voltage
Operating supply voltage
RATINGS
UNIT
--{I.5to +7
Voc;
4.5 to 5.5 (Industrial)
4.75 to 5.25 (Commercial)
Voc;
VIN
Input voltage
--{I.5 to Vee + 0.5
Voc;
VOUT
Output voltage
--{I.5 to Vee + 0.5
Voc;
lIN
Input currents
-10to+l0
mA
lOUT
Output currents
+24
mA
TA
Operating temperature range
-40 to +85 (Industrial)
to +75 (Commercial)
°c
TSTG
Storage temperature range
~5to+l50
°c
o
TEMPERATURE
Maximum junction
150°C
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
NOTE:
1. Stresses above those listed may cause malfuncion or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
AC TEST CONDITIONS
VOLTAGE WAVEFORMS
+5V
FROM OUTPUT4J'
(BlC, FX)
UNDER TEST
R2 • :180 n
TEST POINT
CL'
'CL INCLUDES JIG AND PROBE TOTAL
CAPACITANCE
MEASUREMENTS:
All
ci",u~
delays are measured at the +l.SV level 01 inpu18 and outputs, unl... othorwlao apociflod.
Test Load Circuit
September 1, 1989
Input Pulses
79
Product Speafication
Signetics Programmable Logic Devices
Zero Standby Power
Universal PAL-Type Devices
DC ELECTRICAL CHARACTERISTICS
PLC18V8Z Series
Commercial = OOC S T" s +75°C, 4.75V s Vee s 5.25V;
Industrial = -4Q°C s T" s +85°C 4 SV s Vee < S.SV
-
UMITS
SYMBOL
PARAMETER
TEST CONDITION
Min
Typl
Max
UNIT
Input voltage
VII.
low
Vee = Min
-0.3
0.8
V
V IH
High
Vee = Max
2.0
Vee + 0.3
V
0.100
0.500
V
V
Output voltage!!
VOL
low
Vee = Min, IOL = 201lA
Vee = Min, IOL = 24mA
VOH
High
Vee = Min, IOH = -3.2mA
Vee = Min, IOH = -201lA
V
V
2.4
Vee- 0.1V
Input current
IlL
Low7
VIN = GND
-10
IIH
High
VIN
= Vee
10
IlA
IlA
VOUT = Vee
VOUT = GND
10
-10
IlA
IlA
mA
Output current
iO(OFF)
Hi-Z state
los
Short-circuit3
VOUT= GND
-130
lee
Vee supply current (Standby)
Vee = Max, VIN = 0 or Vee B
100
IlA
lcell
Vee supply current (Active)'
Vee = Max (CMOS inputs)5.6
1.5
mA/MHz
Capacitance
CI
Input
Vee =5V
VIN = 2.0V
12
pF
CB
1/0
VB = 2.0V
15
pF
NOTES:
1. All typical values are at Vee = 5V, T" = +25°C.
2. All voltage values are with respecllo network ground terminal.
3. Duration of short-circuit should not exceed one second. Test one at a time.
4. Tested with TIL input levels: VIL = O.45V, VIH = 2.4V. Measured with all outputs switching.
5. ~lcclTIl input = 2mA.
6. ~Iee vs frequency (registered configuration) = 2mA/MHz.
7. IlL for Pin 1 (ldCLK) is ± IOIlA with VIN = 0.4V.
8. VIN includes ClK and OE if applicable.
15
I
/
10
V
V
V
/
l00J:!A
/
y
V
/'
/
0 0
-1
4
S
~MHz)
Figure 1. Icc vs Frequency
(Worst Case)
September 1, 1989
v
10
-2
/
V
o
20 40 60 80 100 120 140 160 180 200
LOADING (pi')
OUTPUT CAPACITANCE
Figure 2. ~Ipo vs Output Capacitance
Loading (Typical)
80
Product Specification
Signetics Programmable Logic Devices
Zero Standby Power
Universal PAL-Type Devices
PLC18V8Z Series
AC ELECTRICAL CHARACTERISTICS Commercial =
..
OOC S TA S +75°C, 4.75V S Vee s 5.25V;
-
!ndustr;a! - -400 r. ,,; TA
- .8soG
< ..
< Vrr < 5 5V' R2 = 3900
, 4.. flV
-
PLC18V8Z35
(Commercial)
TEST CONDITIONI
SYMBOL
PARAMETER
PLC18V8Z1
(Industrial)
UNIT
Rl (0)
CL
(pF)
Min
CLK+
200
50
47
57
ns
FROM
TO
CLK+
Max
Min
Max
Pulse width
IcKP
Clock period
(Minimum
~ +!eKO)
!eKH
Clock width High
CLK+
CLK-
200
50
20
25
ns
!eKL
Clock width Low
CLK-
CLK+
200
50
20
25
ns
tARW
Async reset
pulse width
I±,F±
1+, F+
35
40
Input or feedback
data hold time
CLK+
Input±
200
50
0
0
ns
I±,F±
CLK+
200
50
25
30
ns
ns
Hold time
tlli
Setup time
tIS
Input or feedback
data setup time
Propagation delay
Delay from input
!Po
to active output
I±,F±
F±
200
50
35
40
ns
!eKD
Clock High to
output valid
access Time
CLK+
F±
200
50
22
27
ns
I±,F±
F±
Active-High R = 1.5k
Active-Low R =550
50
35
40
ns
I±, F±
F±
5
35
40
ns
5
25
30
ns
50
25
30
ns
35
40
ns
1oe1 3
Product term
enable to outputs
1001 2
Product term
disable to outputs
011
011
From VOH R =00
From VOL R =200
10022
Pin 11 output
disable High to
outputs 011
OE-
F±
1oe23
Pin 11 output
enable to active
output
OE+
F±
tARO
Async reset delay
I±,F±
F+
tARR
Asyncreset
recovery time
I±,F±
CLK+
25
30
ns
IsPR
Sync preset
recovery time
I±,F±
CLK+
25
30
ns
IppR
Power-tlp reset
Vee +
F+
From VOH R =00
From VOL R =200
Active-High R = 1.5k
Active-Low R =550
35
40
ns
21
18
MHz
Frequency of operation
fMAX
Maximum frequency
200
V(tIS + !eKO)
50
NOTES:
1. Refer also to AC Test Conditions. (Test Load CirCUit)
2. 3-State levels are measured ±o.5V from the active steady-state level.
3. Resistor values of 1.5k and 5500 provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level.
September 1, 1989
81
Product Specification
Signetics Programmable Logic Devices
Zero Standby Power
Universal PAL-Type Devices
PLC18V8Z Series
POWER-UP RESET
In order to facilitate state machine design and
testing, a power-up reset function has been
incorporated in the P lC 18V8Z. All internal registers will reset to active-low (logical "0") after
a specified period of time (IpPR)' Therefore, any
OMC that has been configured as a registered
output will always produce an active-High on
the associated output pin because of the inverted output buffer. The internal feedback (0)
of a registered OMC will also be set low. The
programmed polarity of OMC will not affect the
active-High output condition during a system
power-up condition.
TIMING DIAGRAMS
INPUTS
110, REG.
FEEDBACK
ClK
PlNllllE
REGISTERED
OUTPUTS
--+------'
ANY INPUT '77":"""'77":M"'77":7?"'77":M"'7'7-::'I"'7'7'"'7-::'I"'7'7'"'7-::'I"'7'7'"T:i'l"'7'7'"T:i"'7-rT:i~ , - - - , , - - - _
PROGRAMMED FOR
~REcnONcONTROl~~~~~~~~~~~~~~~~~~~~~~~~~~~~~" , _ _ _ _J , _____- '
COMBINATORIAL
OUTPUTS~~~~~~~~~~~I~
______________________________________- "
Switching Waveforms
~----__________________________________
.5V
ov
Vcc
VOH
F
{OUTPUTS}
VOL
+!IV
I,B
(INPUTS)
ov
+!IV
elK
ov
NOTE:
Diagram presuppooes that the outputs (F) are enabled. The reset occurs regardless eX the output condition (enctlled or disabled).
Power-Up Reset
September 1,1989
82
Product Specification
Signetics Programmable Logic Devices
Zero Standby Power
Universal PAL-Type Devices
PLC18V8Z Series
TIMING DIAGRAMS (Continued)
1-----
.ARW------I
~-----------------
ASYNCHRONOUS
RESET INPUT
REGISTERED
OUTPUT
L -__
~~
__
~
____
~~~~
CLOCK
Asynchronous Reset
~S
---1-0------
~H'------o-l+-----
tgPR------i
SYNCHRONOUS
PRESET INPUT
CLOCK
REGISTERED----------':"==========-tc-K-O======------.=l--i
~
OUTPUT
--------------------~------Synchronous Preset
September 1, 1989
83
Product Specification
Signelics Programmable Logic Devices
Zero Standby Power
Universal PAL-Type Devices
REGISTER PRELOAD FUNCTION
(DIAGNOSTIC MODE ONLY)
In order to facilitate the testing of state
machinelcontrollerdesigns, a diagnostic mode
register preload feature has been incorporated
into the PLC18vaz series device. This feature
enables the userto load the registers with pre-
PLC18V8Z Series
determined states while a super voltage is
applied to Pins 11 and 6 (I~ and '5). (See
diagram for timing and sequence.)
To read the data out, Pins 11 and 6 must be returned to normal TTL levels. The outputs, Fa _ 7,
must be enabled in order to read data out. The
Q outputs of the registers will reflect data in as
input via Fa _ 7 during preload. Subsequently,
the register Q output via the feedback path will
reflect the data in as input via Fa _7.
Refer to the voltage waveform for timing and
voltage references. IpL ~ 10J1.Sec.
REGISTER PRELOAD (DIAGNOSTIC MODE)
12.0Y
IgIO£
(PIN 11)
5.0V
FI'i'------------------llE(VoLJ
15
(PINS)
IgiCLK - - - - - - - -
I
-----r-----'"\
--------
, . . . . - - - - - - - IgiCLK
(PlNl) _ _ _ _ _ _ _ _ _ __+-----------+--------~I~------_+~--JI
1'0-7------.-1
~:.------+--.. , - - - '------
PRELOAD DATA IN
LOGIC PROGRAMMING
DATA OUT
F0-7
OUTPUT POLARITY - (0, 8)
The PLC lavaz can be programmed by means
of Logic Programming equipment.
0,11"
With Logicprogramming, theAND/OR/Ex-OR
gate input connections necessal)' to implement the desired logic function are coded direcdy from logic equations using the Program
Table. Similarly, various OMC configurations
are implemented by programming the Architecture Control bits AC 1 and AC2. Note that
the configuration cell is automatically programmed based on the OMC configuration.
I
I
ACTIVE LEVEL
INVERTING 1
I
I
CODE
L
I
I
I
I
ACTIVE LEVEL
NON-lNVERTING
I
I
CODE
H
I
I
In this lable, the logic state of variables I, P and
B associated with each Sum Term S is assigned a symbol which results in the proper
fusing pattem of corresponding link pairs, defined as follows:
1
1
,
8
11'
8
1
1
1
"AND" ARRAY - (1,8)
~B
I,B
I,B
~II"
I,B
P
P
P
STATE
STATE
STATE
STATE
DON'T CARE
INACTIVE'
I,B
I,ll"
NOTE:
1. A factol)' shipped unprogrammed device is configured such that all cells are in a conductive slate.
September 1, 1989
1
'9
I,ll"
U
84
'8
~II"
P
Product Specification
Signetics Programmable Logic Devices
Zero Standby Power
Universal PAL-Type Devices
ERASURE CHARACTERISTICS
(For Quartz Window Packages
Only)
The erasure characteristics of the PLC18Vaz
Series devices are such that erasure begins to
occur upon exposure to light with wavelengths
shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lighting could erase a typical PLC 18Vaz in approximately three years,
while it would take approximately one week to
cause erasure when exposed to direct sunlight.
PLC18V8Z Series
If the PLC18V8l is to be exposed to these
types of lighting ('.oodilian. for extended periods of time, opaque labels should be placed
over the window to prevent unintentional erasure.
The recommended erasure procedure for the
PLC 18V8l is exposure to shortwave ultraviolet
light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a
minimum of 15Wseclcm2 . The erasure time
with this dosage is approximately 30 to 35
minutes using an ultraviolet lamp with a
12,OOO)lW/cm2 power rating. The device
should be placed within one inch of the lamp
tubes during erasure. The maximum integrated
dose a CMOS EPLO can be exposed to without
damage is 7258Wseclcm2 ). Exposure of these
CMOS EPLDs to high intensity UV light for
longer periods may cause permanent damage.
The maximum number of guaranteed erase/
write cycles is 50. Data retention exceeds 20
years.
PROGRAMMING
The PLC18V8l35/1 is programmable on conventional programmers for 2(}...pin PAL devices. Refer to the following charts for qualified manufacturers
of programmers and software tools:
PROGRAMMER MANUFACTURER
DATA I/O CORPORATION
10525 WILLOWS ROAD, N.E.
P.O. BOX 97046
REDMOND, WASHINGTON 98073-9746
(800)247-5700
System 29B, LogicPak™
303A--<>11A; V09 (OIL)
303A--<>11B; V04 (PLCC)
UNISITE 40148
V2.5 (OIL)
Chipsite (PLCC) - TBA
MODEL 60
STAG MICROSYSTEMS, INC.
1600 WYATT DRIVE
SUITE 3
SANTA CLARA, CALIFORNIA 95054
FAMILY/PINOUT CODES
PROGRAMMER MODEL
86/4F
TBA
lL30130A PROGRAMMER
REV. 30A34 (OIL)
3OAOOl Adaptor (PLCC)
121205
PPZ PROGRAMMER
TBA
(408)988-1118
SOFTWARE MANUFACTURER
DEVELOPMENT SYSTEM
SIGNETICS COMPANY
811 EAST ARQUES AVENUE
P.O. BOX 3409
SUNNYVALE, CALIFORNIA 94088-3409
AMAZE SOFTWARE
REV. 1.8 AND LATER
(408)991-2000
DATA I/O
10525 WILLOWS ROAD, N.E.
P.O. BOX 97046
REDMOND, WASHINGTON 98073-9746
ABELTM SOFTWARE
(800)247-5700
LOGICAL DEVICES, INC.
1201 NORTHWEST 65TH PLACE
FORT LAUDERDALE, FLORIDA 33309
CUPLTM SOFTWARE
(800)331-7766
September 1, 1989
85
Signetics Programmable Logic Devices
Product Spedfication
Zero Standby Power
Universal PAL-Type Devices
PLC18V8Z Series
PROGRAM TABLE
T
E
OR RXED
F(B,O,D)
AND
F(I)
~
w
~
x
Cl
X
X
~
u..
U
I
"*
a::
it
>=
w
a::
I-
Cl
W
N
(/)
I-
a::
it
"* w"* 0 u..
a::
w U aJ 0
~ Cl
~ a::
« a:: > >w
z 0 w
Cl (/) aJ
a:: w (/) a:: ~
w (/) U W ::::l
~ «
f= ~ z
f2C/) ua::J: Wz C/)f2 ...J~
...J
w
::::l
::::l
(!)
::>
u c.. Ci5 u
f2
AND ARRAY
INACTIVE
F~
CONTROL
B
H
Fd B
L
-
II "DON'T CARE
OR ARRAY AXED
° tr==~OM~C~A=RC=H=,r=:;t;=:~O=U~TP~U~T~PO~L=AfI=T=Y:;:::=1l ~~i:~~::R~'f~~~g
R~~:~RED
0 I:=~RTlNG I~ I g~~~ ~~I~~~R~~:t
AXED INPUT
I
I-R",X:>,ED":,O",,U,,:,TPUT""":-:-:-1r:0:-1
BIDIRECTIONAL va B
CONRG. CELL'
TURE.
I PIN 1 =CLK; PIN 11 =orl tJ
PIN
=INPUT
PIN
1
11
H
II
DIRECTION CONTROL D
ACTIVE OUTPUT
A
NOT USED
VI
• THE CONRGURATION CEll IS AUTOMATICAllY PROGRAMMED BASED ON THE OMC ARCHITECTURE.
.. FOR SP, AR: "-" IS NOT AllOWED,
September 1, 1989
86
SigneHcs
1OH20EVS/1 0020EVS
Document No.
ECN No.
Eel Programmable Array logic
Date of Issue October 1989
Status
Preliminary Specffication
Programmable Logic DevicQs
DESCRIPTION
The 1OH20EV8/1 0020EV8 is an ultra
high-speed universal ECl PAl®-type device. Combining versatile output macrocells with a standard AND/OR single
programmable array, this device is ideal in
implementing a user's custom logic. The
use of Signetics state-of-the-art bipolar
oxide isolation process enables the
1OH20EV8/1 0020EV8 to achieve optimum speed in any design. The AMAZE
design software package from Signetics
simplffies design entry based upon
Boolean or state equations.
The 1OH20EV8/1 0020EV8 is a two-level
logic element comprised of 11 fixed inputs,
an input pin that can either be used as a
clock or 12th input, 90 AND gates, and 8
Output logic Macrocells. Each Output
Macrocell can be individually configured
as a dedicated input, dedicated output
with polarity control, a bidirectional I/o, or
as a registered output that has both output
polarity control and feedback to the AND
array. This gives the part the capability of
having up to 20 inputs and eight outputs.
The 1OH20EV8/1 0020EV8 has a variable
number of product terms that can be OR'd
per output. Four of the outputs have 12
AND terms available and the other four
have 8 terms per output. This allows the
designer the extra flexibility to implement
those functions that he COUldn't in a standard PAL device. Asynchronous Preset
and Reset product terms are also included
for system design ease. Each output has
a separate output enable product term.
Another feature added for the system
designer is a power-up Reset on all registered outputs.
The 1OH20EV8/1 0020EV8 also features
the ability to Preload the registers to any
desired state during testing. The Preload
is not affected by the pattern within the
device, so can be performed at any step in
the testing sequence. This permits full
logical verification even after the device
has been patterned.
PIN CONFIGURATION
F Package
FEATURES
• Ultra high speed ECl device
- t pD = 4.5ns (max)
~s = 2.5ns (max)
- tCKo = 2ns (max)
- fMAX = 222MHz
-
• Universal ECl Programmable Array
logic
- 8 user programmable output
macrocells
- Up to 20 Inputs and 8 outputs
- Individual user programmable
output polarity
A Package
• Variable product term distribution
allows Increased design capability
• Asynchronous Preset and Reset
capability
• 10KH and lOOK options
• Power-up Reset and Preload
function to enhance stste machine
design and testing
• Design support provided via
AMAZE and other CAD tools
• Security fuse for preventing design
duplication
• Available In 24-Pln 300mll-wide DIP
and 28-Pln PlCC.
®PAL 10 a ragiltered"- ofMonol1lh1c - . Inc.. a whoIy - * luboldlary of Advanced Miao 1leYIcoo. Inc.
PHILIPS
87
Signetics Programmable Logic Devices
Preliminary Specification
Eel Programmable Array logic
1OH20EV8/1 0020EV8
LOGIC DIAGRAM
ASYNCHRONOUS RESET
ASYNCHRONOUS PRESET
NOTES,
1. All unprogrammed or virgin "AND" gate locations are pulled to logic "0"
2. ::t:,LProgrammabie connection.
3. Pinout for F Package
October 1989
98
Preliminary Specification
Signetics Programmable Logic Devices
1OH20EVS/1 0020EVS
Eel Programmable Array logic
FUNCTIONAL DIAGRAM
CLKiI
FUNCTIONAL DESCRIPTION
The 10H20EV8/10020EV8 is an ultra highspeed universal ECl PAL -type device. Combining versatile Output Macrocells with a
standard ANDIOR single programmable array,
this device is ideal in implementing a user's
custom logic.
As can be seen in the Logic Diagram, the device is a two-level logic element with a programmable AND array. The 20EV8 ean have up to
20 inputs and 8 outputs. Each output has a versatile Macrocell whereby the output can either
beconfiguredasadedicatedinput, a dedicated
combinatorial output with polarity control, a bidirectional 1/0, or as a registered output that
has both output polarity control and feedback
into the AND array.
The device also features 90productterms. Two
of the product terms can be used for a global
asynchronous preset andior reset. Eight of the
product terms can be used for individual output
enable control of each Macrocell. The other 80
product terms are distributed among the outputs. Four of the outputs have eight product
terms, while the other four have 12. This arrangement allows the utmost in flexibility when
implementing user patterns.
Output Logic Macrocell
The 1OH20EVs/l 0020EV8 incorporates an
extremely versatile Output logic Macrocell
that allows the user complete flexibility when
configuring outputs.
As seen in Figure 1, the 1OH20EV811 0020EV8
Output Logic Macrocell consists of an edgetriggered D-type flip-flop, an output select
MUX, and a feedback select MUX. Fuses So
and Sl allow the user to select between the
various cells. Sl controls whether the output
will be either registered with internal feedback
or combinatorial 1/0. So controls the polarity of
the output (Active-HIGH or Active-LOW). This
allows the user to achieve the following
configurations: Registered Active-HIGH output, Registered Active-LOW output, Combinatorial Active-HIGH output, and Combinatorial
Active-LOW output. With the output enable
product term, this listean be extended by adding the configurations 01 a Combinatorial 1/0
with Polarity or another input.
Figure 1, Output logic Macrocell
October 1989
89
Preliminary Specification
Signetics Programmable Logic Devices
1OH20EVS/1 0020EVS
Eel Programmable Array logic
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
10H20EV8-6F
10H20EVB-4F
10020EV8-6F
10020EVB-4F
24-Pin Ceramic Duall~ne
(300mil~ide)
2~Pin
10H20EVS-OA
10H20EV8-4A
10020EVS-OA
10020EV8-4A
Plastic Leaded Chip Carrier
ABSOLUTE MAXIMUM RATINGSl
SYMBOL
VEE
PARAMETER
Supply voltage (Vee = 0)
RATING
UNIT
--a
Vrx;
VIN
Input voltage (Vee = 0)
o to VEE
Vrx;
10
Output source current
40
mAce
TA
Operating Temperature range
oto +75 (10KH)
o to +85 (100K)
°C
TSTG
Storage Temperature range
-05 to +150
"C
NOTE:
1. Stresses abow those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition abow those
indicated in the operational and programming specification of the device is not implied.
OPERATING RANGES
RATINGS
DEVICE
10H20EV8
10020EV8
October 1989
SYMBOL
PARAMETER
VEE
Supply voltage
TA
Operating free-air temperature
VEE
Supply voltage
TA
Operating free-air temperature
Min
Max
UNIT
-5.46
-4.94
Vrx;
0
+75
"C
-4.8
-4.2
Vrx;
0
+85
°C
90
Preliminary Specification
Signetics Programmable Logic Devices
Eel Programmable Array logic
1OH20EV8/1 0020EV8
D
Registered Actlv...LOW
Registered Actlve-HIGH
D
D
Combinatorial Actlve-HIGH
Combinatorial Actlve-L.OW
Figure 2. Output Macro Cell Configuratlona
OUTPUT MACRO CELL
CONFIGURATION
Shown in Figure 2 are the fourpossibleconfigurations of the output macrocell using fuses So
and S,. As seen, the output can either be registered Active-HIGH/LOW with feedback or
combinatorial Active-HIGH/LOW with feedback. If the registered mode is chosen, the
feedback is from the output to the AN 0 array
enables one to make state machines or shift
registers withcut having to tie the output to one
of the inputs. If a combinatorial output is chosen, the feedback gate is enabled from the pin
and allows one to aeate permanent outputs,
permanent inputs, or VO pins through the use
of the output enable (D) product term.
a
OUTPUT ENABLE
Each output on the 10H20EV8/1 0020EV8 has
its own individual product term for output enable. The use of the 0 product term (direction
control) allows the user three possible configurations of the outputs. They are always enabled, always disabled, and controlled by a
programmed pattern. A HIGH on the 0 term enables the output, while a LOW performs the disable function. Output enable control can be
achieved by programming a pattern on the 0
term.
The output enable control can also be used to
expand a designer's possibilities once a combinatorial output has been chosen. If the 0 term
is always HIGH, the pin becomes a permanent
October 1989
Active-H IGH/LOW output. If the 0 term is
always LOW (all fuses left intact), the pin now
becomes an extra input.
l0020EV8. The PRELOAD would allow a
designer to enter any state in the sequence
desired and start clocking from that particular
point. Any or all transitions could be verified.
PRESET AND RESET
The 10H20EV8/10020EV8also includesaseparate product term for asynchronous Preset
and asynchronous Reset. These lines are common for all registers and are asserted when the
specific product term goes HIGH. Being
asynchronous, they are independent of the
clock. It should be noted that the actual state of
the output is dependent on how the polarity of
the particular output has been chosen. If the
outputs are a mix of Active-HIGH and ActiveLOW, a Preset signal will force the ActiveHIGH outputs HIGH while the Active-LOW
outputs would go LOW, even though the Q output of all flip-flops would go HIGH. A Reset signal would force the opposite conditions.
PRELOAD
To simplify testing, the 10H20EV8/10020EV8
has also included PRELOAD circuitry. This
allows a user to Ioed any particular data desired
into the registers regardless of the programmed pattern. This means that the
PRELOAD can be done on a blank part and
after that same part has been programmed to
facilitate any post-fuse testing desired.
It can also be used by a designer to help debug
his/her circuit. This could be important if a state
machine was implemented in the 10H20EV8I
91
AMAZE
The AMAZE PLO Design Software development system also supports the 10H20EV8I
l0020EV8. AMAZE provides the following capabilities for the 10H20EV8Il0020EV8:
• State equation entry
• Boolean equation entry
• Logic and timing simulation
• Automatic test vector generation
AMAZE operates on an IBM PC/XT, PC/AT,
PS/2, or any compatible system with DOS 2.0
or higher. The minimum system configuration
for AMAZE is 640K bytes of RAM and a hard
disk.
AMAZE compiles the design after completion
for syntax and completeness. Programming
data is generated in JEOEC format.
DESIGN SECURITY
The 10H20EV8/10020EV8 has a programmable security fuse that controls the access to
the data programmed in the device. By using
this programmable feature, proprietary designs
implemented in the device cannot be copied or
retrieved.
Signetics Programmable logic Devices
Prelimin3/)' SpecifICation
Eel Programmable Array logic
DC ELECTRICAL CHARACTERISTICS
1OH20EV811 0020EV8
10H20EV8: oae.s TA.s +75°e, VEE
=-J!J.2V ± 5%, Vc;c = Vco, =Vroz = GND
=Vco, =VC02 = GND
l002OEV8· oae.s TA.s +85°e -4 8V.s VEE.s -42V Vc;c
LIMITS
SYMBOL
VOH
TEST eONDITIONS2
PARAMETER'
High level output voltage
VOHT
High level output threshold voltage
VOL
low level output voltage
VIN
=VIH Max. or VIL Min.
=VIH Max. or VIL Min.
VIN = VIH Max. or VIL Min.
VIN
= VIH Max. or VIL Min.
VOLT
High level output threshold voltage
VIN
VIH
High level input voltage
Guaranteed input voltage
high for all inputs
VIL
IIH
IlL
lEE
low level input voltage
High level input current
low level input current
Supply current
Guaranteed input voltage
low for all inputs
VIN
= VIH Max.
VEE = Max.
All inputs and outputs open
MIn
Max
UNITS
O"C
-840
-810
-735
mV
-880
10KH
+25oe
+75°e
-1020
-980
-920
lOOK
oae to 85°C
-1025
lOOK
ooe to 85°C
-1035
10KH
coe
+25°e
+75°e
-1950
-1950
-1950
-1630
-1630
-1600
mV
lOOK
ooe to 85°C
-1810
-1620
mV
lOOK
ooe to 85°C
-1610
mV
10KH
coe
+25°e
+75°e
-840
-810
-735
mV
lOOK
ooe to 85°C
-1165
-880
mV
10KH
coe
+25°e
+75°e
-1950
-1950
-1980
-1480
-1480
-1450
mV
lOOK
ooe to 85°C
-1810
-1475
mV
220
~
10KH
VIN = VIL Min.
Except 110 Pins
TA
-1170
-1130
-1070
mV
mV
O"C
+75°e
lOOK
oae to 85°C
10KH
coe
+75°e
0.3
lOOK
ooe to 85°C
0.5
10KH
ooe to 75°C
lOOK
ooe to 85°C
-230
IlA
rnA
NOTES:
1. All voltage measurements are referenced to the ground teonina!.
2. Each Eel 1OKH/l ooK series device has been designed to meet the DC specification after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 (150 meters) linear fpm is maintained.
Voltage levels will shift approximately 4mV with an air flow of 200 linear fpm. Outputs are teoninated through a 50Q resistor to -2V.
3. Teoninals not specifically referenced can be left electrically open. Open inputs assume a logic lOW state. Any unused pins can be terminated to -2V. If tied to VEE, it must be through a resistor> 10K.
October 1989
92
Signetics Programmable Logic Devices
Preliminary Specification
Eel Programmable Array logic
1OH20EV8/1 0020EV8
i~
AC TEST CIRCUIT
+2.OV ± o.o,ov
10.'""
'OIl" ....
l
I.- L, -...._-+1+-- t.,
...-----.
,-,
RT:t
t.,--of+----
Tl'JN
....
-2.5V ± O.O,OV FOR 'OO2OEva
-3.2V ± O.O,OV FOR ,oH2OEYa
NOTES:
1. Use decoupling capacitors of O.lIlF and 2SllF from GNO to Vee, and O.Q1IlF and 2SJ.LF from GNO to VEE (0.01 and O.lIlF capacitors
should be NPO Ceramic or MLC tyf,e). Oecoupling capacitors should be placed as close as physically possible to the OUT and lead
length should be kept to less than /4 inch (Smm).
2. All unused inputs should be connected to either HIGH or LOW state consistent with the LOGIC function required.
3. All unused outputs are loaded with soo. to GNO.
son
4. Ll and L2 are equal length
impedance lines. L3, the distance from the OUT pin to the junction of the cable from the Pulse Generator and the cable to the Scope, should not exceed 1/4 inch (Smm).
son
RT =
terminator internal to Scope.
The unmatched wire stub between coaxial cable and pins under test must be less than 1/4 inch (Smm) long for proper test.
CL = Fixture and stray capacitance.,; 3pF.
Any unterminated stubs connected anywhere along the transmission line between the Pulse Generator and the OUT or between the
OUT and the Scope should not exceed 1/4 inch (Smm) in length (refer to section on AC setup procedure).
9. All SOo. resistors should have tolerance of ± 1% or better.
10. Test procedures are shown for only one input or set of input conditions. Other inputs are tested in the same manner.
S.
S.
7.
8.
11. Two lOIlF capacitors between Vee and Veo1 and VC02 respectively located as close to the device as possible is recommended to
reduce ringing.
12. Normal practice in test fixtures layout should be followed. Lead lengths, particular to the power supply, should be as short as possible.
October 1989
93
Preliminary Specification
Signetics Programmable Logic Devices
1OH20EV8/1 0020EV8
Eel Programmable Array logic
VOLTAGE WAVEFORMS
NEGATIVE
PULSE
~-
~Jf
+111OmV (10H20EV8)
+ l050mV (10020EV8)
+31OmV
tw(L)
POSITIVE
PULSE
1C~
tw(H)
1
""'
_ +111OmV (10H20EV8)
+10SOmV (10020EV8)
+31OmV
10-
INPUT PULSE REQUIREMENTS
Vee
FAMILY
lOKH Eel
=VeOl = VC02 = +2.0V:tO.01DY, VEE = -3.2V.:t O.010Y. VT = GND (OY)
I AMPLITUDE I REP RATE I PULSE WIDTH I trLH I trHL
I SOOmVp-p I lMHz I SOOno 11.3±o.2ns I '.3±02ns
INPUT PULSE REQUIREMENTS
VCC = VCOI
FAMILY
l00KECl
=VC02 =+2.0V ±G.Ol0V, VEE =-2.5V ± O.010V, VT =GHD (OY)
I AMPLITUDE I REP RATE I PULSE WIDTH I
I
740mVp-p
I
lMHz
I
5OOno
Input Pulse Definition
October 1989
94
trLH
I
I O.7±O.lns I
trHL
O.7±O.lns
Signetics Programmable Logic Devices
Preliminary Specification
Eel Programmable Array logic
1OH20EV8/1 0020EV8
AC ELECTRICAL CHARACTERISTICS 10H20EV8: (lOC s TA S +75"C, VEE =-5.2V ±5%, Vc;c = VCOl =VC02 = GND
10020EV8' Oae s TA
~
~
'85"C
......'-'._w..:::r.'
RV ~ \lEE
,
I
- .V~~
~
-4?V
..
~
~
= VCC'
-
= V~02 =
UMITS
SYMBOL
PARAMETER
FROM
TEST
CONDITIONSl
TO
-4
Min
GND
UNIT
-6
Max
Min
Max
Pulse Width
IeKH
Clock High
CLK+
CLK-
2
3
ns
IeKL
Clock Low
CLK-
CLK+
2
3
ns
IeKP
Clock Period
CLK+
CLK+
.4
6
ns
tpRH
PreseVReset Pulse
(I,I/O)±
(I,IIO)±
4.5
6
ns
Setup and Hold Time
tIS
Input
(I,I/O)±
CLK+
2.5
4
ns
tH
Input
CLK+
(1,11Ol±
0
0
ns
tpRS
Clock Resume
after PreseVReset
(I,I/O)±
CLK+
4.5
6
ns
Propagation Delay
tpo
Input
(I,I/O)±
I/O±
4.5
6
ns
IeKO
Clock
CLK+
1I0±
2
3
ns
toE
Output Enable
(I,I/O)±
110
4.5
6
ns
100
Output Disable
(1,1I0l±
1/0
4.5
6
ns
tpRO
PreseVReset
(1,1I0)±
I/O±
4.5
6
ns
tPPR
Power-- 10K
-Open
October 1989
98
Preliminary Specification
Signelics Programmable Logic Devices
Eel Programmable Array logic
LOGIC PROGRAMMING
10H20EVSll0020Eva logic designs can be
generated using Signelics' AMAZE PLD design software or one of several other commercially available, JEDEC s18ndard PLD design
software packages. Boolean anellor s1818
equation entry is accepted.
10H20EV8/10020EV8
10H20EV8Il0020EV8 logic designs can also
be generated using the program table entry format de18iled on the following pages. This program table entry format is supported by the
Signetics' AMAZE PLD design software (PTP
module). AMAZE is available free of charge to
qualified users.
To implement the desired logic functions, the
s1818 of each logic variable from logic equations
(I, F, a, etc.) is assigned a symbol. The symbols
for TRUE, COMPLEMENT, INACTIVE, PRESET. etc., are defined below.
"AND" ARRAY - (I) , (F), (Q )
-4'" -4'" 4'" -4'"
i,F.Q
I.F.Q
P,D,Ap'AR
I
~~ij
~F,Q
I.F.Q
STATE
INAcnVE','
I~I
--
p'D,AP,AR
I
STATE
I,F,Q
I
~F,Q
I.F.Q
~F,Q
p'D,AP, AR
C~DE I
I
STATE
i,FoQ
Ic~1
P,D,Ap'AR
I
STATE
DONTCARE
NOTES:
1. This is the initial unprogrammed s18te of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (P, 0, AP, AR) will be unconditionally inhibited if anyone of the I, F or link pairs is left in18ct.
a
OUTPUT MACROCELL CONFIGURATIONS
OUTPUT MACROCELL CONFIGURATION
CONTROL WORD
FUSE
POLARITY FUSE
Registered Output, Active-HIGH
0
H
Registered Output, Active-LOW
0'
L1
Combinatorial 110, Activ&-HIGH
B
H
Combinatorial VO, Acitve--LOW
B
L
NOTES:
1. This is the initial (unprogrammed) s18te of the device.
October 1989
99
I~EI
Preliminary Specification
Signetics Programmable Logic Devices
1OH20EVSI1 0020EVS
Eel Programmable Array logic
PROGRAM TABLE
POlARITY
CONTROL WORD
T
E
R
M
PIN
OR AXED
F(O
AND
I
12 11
3
10
a
8
1
FIll
6
5
4
2322 16 15 14 13 11 10
~w
3
•
2
2
1
1
8
1
6
5
4
21 20 18 11 8
3
1
2
5
1
4
m:a;
~~
~
October 1989
100
8
1
6
5
4
3
2
1
Signefics
Document No. 853-1359
ECN No.
98104
Date of Issue November 14, 1989
Status
Product Specification
PLUS20R80/-7 SERIES
PAL ®- Type Devices
20L8,20R8,20R6,20R4
Programmable Logic Devices
FEATURES
• Ultra high-speed
- t po = 7.5ns and f MAx = 74MHz for
the PLUS20R8-7 Series
=
=
- t po 1Ons and f MAx 60 MHz for
the PLUS20R8D Series
• 100% functionally and pin-far-pin
compatible with industry standard
24-pin PAL ICs
• Power-up reset function to enhance
state machine design and
testability
• Design support provided via
AMAZE and other CAD tools for
Series 24 PAL devices
• Field-programmable on Industry
standard programmers
• Security fuse
• Individual 3-State control of all
outputs
DEVICE NUMBER
DESCRIPTION
The Signetics PLUS20XX family consists
of ultra high-speed 7.5ns and 10ns versions of Series 24 PAL devices.
The Signetics State-of-the-Art oxide isolation Bipolar fabrication process is
employed to achieve high-performance
operation.
The PLUS20XX family is 100% functional
and pin-compatible with the 20L8, 20R8,
20R6, and 20R4 Series devices.
The PLUS20XX family of devices are field
programmable, enabling the user to
quickly generate custom patterns using
standard programming equipment. See
the programmer chart for qualified
programmers.
The sum of products (AND-0R) architecture is comprised of 64 AND gates and 8
fixed OR gates. Multiple bidirectional pins
provide variable inpuVoutput pin ratios. Individual3-State control of all outputs and
registers with feedback (R8, R6, R4) is
also provided. Proprietary designs can be
protected by programming the security
fuse.
The PLUS20R8, R6, and R4 have D-type
flip-flops which are loaded on the
Low-to-High transition of the ciock input.
The AMAZE software package from
Signetics supports easy design entry for
the PLUS20XX series as well as other
PLD devices from Signetics. The
PLUS20XX series are also supported by
other standard CAD tools for PAL-type
devices.
Order codes are listed in the Ordering
Information table.
In order to facilitate state machine design
and testing, a power-up reset function has
been incorporated into these devices to
reset all internal registers to active-Low
after a specijic period of time.
DEDICATED
INPUTS
COMBINATORIAL
OUTPUTS
REGISTERED
OUTPUTS
PLUS20L8
14
8(61/0)
0
PLUS20R8
12
0
8
PLUS20R6
12
2110
6
PLUS20R4
12
41/0
4
®pAL 16 a registered trademark of
Monol~hic Memories, Inc., a whoay owned slbsidiary of Advanced Micro DevlC8S, Inc.
PHILIPS
101
Product Specification
Signetics Programmable Logic Devices
PAL®-Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
PIN CONFIGURATIONS
PLUS20L8-7
PLUS20R8-7
Vee
vee
113
I"
01
01
B.
a.
a,
a,
lis
B,
IIa
B,
a,
a,
a,
I.
B,
o.
112
111
I.
a.
I.
I,.
OE
GND
PLUS20L8-7
PLUS20R8-7
Ne Vee 113 0 7
I,
B,
B,
Q,
B,
Q.
He
B,
Q,
B,
B,
I,
SYMBOL
I
110 GND Ne
I"
I" 0,
B
CLK
OE
DESCRIPTION
Dedicated Inpol
Dedicated conillna1orial Ou1put
Registered output
Bidirectional (input/output)
Clock Input
Output Enable
Vee
GND
GlOOnd
NC
No Connection
0
a
Supply VoIIage
November 14, 1989
SYMBOl
I
DESCRIPTION
0
Dedical:ed combinatorial Output
Dedicated Input
a
Registered output
B
CLK
OE
Bidirectional (inpuVoutput)
Clock inpo1
Output Enable
VCC
GND
NC
Ground
Supply VoIIago
No Connection
102
Product Specification
Signetics Programmable Logic Devices
PAL®-Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
PIN CONFIGURATIONS
PLUS20R6-7
CLK
PLUS20R4-7
fTl---Co......
Vee
CLK
fTl---Co......
I"
H-11:)oo......~-IJ:~ B 7
1+fIi~~.......!!.Ia.
B.
Mli~~...-l2'DJ Q.
IH~-+r:,..-L~ Q.
HfI~-tC.....c;~ Q.
"'~~.......!!.I Q 3
HfI~-tC....i.!~ Q 2
tt\I~It'o......~
Q.
1fiI~1t'o......~
Q3
tt\I;m-It'o......~
Q2
"'~~......~Q,
B,
~>+-_-L!~ Bo
GND
GND
PLUS20R6-7
PLUS20R4-7
B,
'm
"
SYMBOL
I
0
0
B
ClK
OE
Vee
GND
NC
November 14.1989
Bo
0,
0,
o.
o.
Ne
Ne
0,
00
0,
0,
a,
B,
B,
DESCRIPTION
Dedlcatod Inpon
Dedicated combinatorial oonpon
Raglslenod outpon
Bldlrecllonal (1npuV0UIput)
Clock Input
Oonpon EIIIo
Supply Voltage
G"",nd
No Connection
a,
'"
"
SYMBOL
I
0
a
B
ClK
OE
VCC
GND
NC
B,
DESCRIPTION
Dedicaled Input
OodIcaIed COIrilin_1aI oonpon
Registered oonpon
Bidirectional Onpulloutpon)
Clock Input
DonponEn_
Supply \IoItago
GIOOnd
No Connection
103
Signetics Programmable logic Devices
Product Spedfication
PAL®-Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
LOGIC DIAGRAM
PLUS20L8
I.
I,
1'3
I,
I,
Bs
I,
ii
e.
til
:IE
a:
I!!
I-
u
Is
:>
0
0
..
a:
I,
I,
I,
I,.
111
o 1 .2
3
4 5 '7
• t1011
12131415 ,.111."
20212223 24252&27 21213031 323330135 3U7113t
INPUTS (O-39)
NOTES,
1.
~II
unprogrammed or virgin "AND" gate locations are pulled to logic "0"
2. -Jig: Programmable connections
November 14, 1989
104
Signetics Programmable Logic Devices
Product Specification
PAL®-Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
LOGIC DIAGRAM
PLUS20R8
NOTES:
1. All unprogrammed or virgin" AND" gate locations are pul!ed to logic "0"
2. ij, Programmable connections
November 14,1989
105
Product Specification
Signetics Programmable Logic Devices
PAL®-Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
PLUS20R6
LOGIC DIAGRAM
elK
10
)-~~+-------------122IB7
I,
a,
I,
as
..i
IJ
a,
U)
lIE
a:
w
lI-
I,
0
:::>
Q
Q
a:
oJ
0-
Is
I--H»-, 171
a,
I.
1--H1'>o-, 16 i a,
BO
I.
o 1:2
1
.. 5 • 1
• • ,0tl
12131415 11171.,' 20212223 14252827 21213031 3233:1435 .313U.
INPUTS (0-39)
NOTES:
1. ~II unprogrammed or virgin "AND" gate locations are pulled to logic "0"
2. q.% Programmable connections
November 14, 1989
106
Signetics Programmable Logic Devices
Product Specification
PAL®-Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
LOGIC DIAGRAM
PLUS20R4
J-~~+---------------i~IB7
B.
t-T1:>'>---j2Cl 05
a,
M
~
U>
::E
ffi
lI-
t)
:>
0,
0
0
a:
0-
0,
>-I1><>-t------t----j15
0123
'5' 7
• '1011
1~131A'5
lIU11,. 20212223 24252121 21283031 32333U6311373831
INPUTS (0-39)
NOTES:
All unprogrammed or virgin "AND" gate locations are pulled to logic "0"
~: Programmable connections
November 14, 1989
107
'-<:1>---1131
So
De
Product Spedfication
Signetics Programmable Logic Devices
PAL®-Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
FUNCTIONAL DESCRIPTIONS
Programmable Bidirectional Pins
The PLUS20XX series utilizes the familiar
sum-¢f-products implementation consisting of
a programmable AND array and a fixed OR
array. These devices are capable of replacing
an equivalent of four or more SSI/MSI integrated drcuits to reduce package count and
board area occupancy, consequenHy improving reliability and design cycle over Standard
Cell or gate array options. By programming the
security fuse, proprietary designs can be protected from duplication.
The PLUS20XX products feature variable
InputlOutput ratios. In addition to 12 dedicated
inputs, each combinatorial output pin of the
registered devices can be individually programmedas an input or output. The PLUS2018
provides 14 dedicated inputs and 6 Bidirectional 1/0 lines that can be individually configured
as inputs or outputs.
The PLUS20XX series consists of four PALtype devices. Depending on the particular
device type, there are a variable number of
combinatorial and registered outputs available
to the designer. The PLUS20L8 is a combinatorial part with 8 userconfigurable outputs (6 bidirectional), while the other three devices,
PLUS20R8, PLUS20R6, PLUS20R4, have
respectively 8, 6, and 4 output registers.
3-State Outputs
The PLUS20XX series devices also feature
3--Stateoutputbuffers on each output pin which
can be programmed for individual control of all
outputs. The registered outputs (On) are controlled by an external input (/OE), and the combinatorial outputs (On, Bn) use a product term
to control the enable function.
by AMAZE, the PC-based software development tool from Signetics. The PLUS20XX family of devices are also supported by standard
CAD tools for PAL devices, including ABEL and
CUPl.
AMAZE is available free of charge to qualified
users.
Logic Programming
Output Registers
The PLUS20R8 has 8 output registers, the
20R6 has 6, and the 2OR4 has 4. Each output
register is a D-type flip-flop which is loaded on
the Low-to-High transition of the clock input.
These output registers are capable of feeding
the outputs of the registers back into the array
to fad Ii tate design of synchronous state machines.
Power-up Reset
By resetting all flip-flops to a logic Low, as the
power is turned on, the PLUS20R8, R6, R4 enhance state machine design and initialization
capability.
Logic designs for PLUS20XX series can be
generated using any commerdally available
JEDEC standard design software that supports
the 24-pin PAL devices. No JEDEC fuse map
conversion or translation is necessary when
transferring designs from slower 24-pin PAL
devices.
To implement the desired logic functions, each
logic variable from the logic equations is
assigned a symbol. True (High), Complement
(Low), Don't Care and Inactive symbols are
defined below.
Software Support
Like other Programmable Logic Devices from
Signetics, the PLUS20XX series are supported
AND ARRAY - (I, B)
1" 1" 1" 1"
LB
__
I,B
I,B
P,D
I
STATE
INACTIVE',2
I
C~E I
I
STATE
I,B
I
i,a
i, a
P,D
P, D
P,D
C~DE I
I
VIRGIN STATE
A factory shipped virgin device contains all fusible links intact, such that
1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.
November 14, 1989
I,B
LB
i,a
108
STATE
I,B
IC~EI
I
STATE
DON'TCARE
I
C~OE I
Product Specification
Signatics Programmable Logic Devices
PAL®-Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
THERMAL RATINGS
ORDERING INFORMATION
,
DESCRIPTION
I
I
ORDER CODE
24-Pin Plastic Dual-In-Una
300mil-wide
PLUS20R8DN
PLUS20R6DN
PLUS20R4DN
PLUS20L8DN
PLUS20R8-7N
PLUS20R6-7N
PLUS20R4-7N
PLUS20L8-7N
28-Pin Plastic Leaded Chip Carrier
(PLCC)
PLUS20R8DA
PLUS20R6DA
PLUS20R4DA
PLUS20L8DA
PLUS20R8-7A
PLUS20R6-7A
PLUS20R4-7A
PLUS20L8-7A
NOTE:
The PLUS20XX series of devices are also processed to military requirements for operation over
the military temperature range. For specifications and ordering information, consult the Signetics
Military Data Book.
ABSOLUTE MAXIMUM RATINGS1
RATINGS
SYMBOL
Max
UNIT
Vee
Supply voltage
-D.5
+7
Voc
VIN
Input voltage
-D.5
+5.5
Voc
V OUT
Output voltage
+5.5
Voc
liN
Input currents
+30
mA
lOUT
Output currents
+100
mA
TSTG
Storage temperature range
+150
°c
PARAMETER
Min
~O
--S5
NOTE:
1. .Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
OPERATING RANGES
RATINGS
SYMBOL
PARAMETER
Vee
Supply voltage
TA
Operating free--air temperature
November 14, 1989
Min
Max
UNIT
+4.75
+5.25
Voc
0
+75
°c
109
._.. -
.. - -
Maximum junction
150°C
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
Sigi'fetics Programmable Logic Devices
Product Specification
PAL®-Type Devices
20L8,20R8,20R6,20R4
DC ELECTRICAL CHARACTERISTICS
PLUS20R8DI-7 SERIES
O°C.s TA.s +7S0C.4.7S.sVee .sS.2SV
UMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ'
Max
UNIT
Input voltage2
Vll
Low
Vcc=Min
V IH
High
Vee = Max
VIC
Clamp
O.B
--{J.B
Vee = Min. liN =-tBmA
V
V
2.0
-loS
V
0.5
V
Output voltage
Vee = Min. VIN = VIH or Vll
VOL
Low
10l = 24mA
VOH
High
IQH =-3.2 mA
V
2.4
Input current
Vee = Max
-250
III
Low!!
VIN =O.40V
IIH
High3
VIN = 2.7V
25
II
Maximum input current
VIN = Vee = VeeMAX
100
J.lA
J.lA
J.lA
Output current
Vee = Max
10ZH
Output leakage
VOUT = 2.7V
loZl.
Output leakage
VOUT = O.4V
-100
los
Short circui.... 5
VOUT=OV
-30
Icc
Vee supply current
Vee = Max
150
100
J.lA
J.lA
-90
mA
210
mA
Capacitance&
CIN
CB
Input
110 (B)
Vee =5V
VOUT = 2.0V
B
pF
VOUT= 2V. f = lMHz
B
pF
NOTES:
1. All typical values are at Vee = 5V. TA = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Leakage current for bidirectional pins is the worst case of III and IOZl or IIH and 10ZH.
4. Test one at a time.
5. Duration of short circuit should not exceed 1 second.
6. These parameters are not 100% tested but periodically sampled.
November 14. 1989
110
Signetics Programmable Logic Devices
Product Specification
PAL ®-Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
AC ELECTRICAL CHARACTERISTICS R1
i
•
= 200.0, R2 =390Q,
SYMBOL
PARAMETER
ooc
FROM
$ TA $ +75°C, 4.75$ Vee $5.25V
I
I
I
Min'
0
Max
I
I
LIMITS
-7
TO
Min'
UNIT
Max
Pulse Width
IcKH
Clock High
CK+
CK-
5
7
ns
IcKL
Clock Low
CK-
CK+
5
7
ns
IcKP
Period
CK+
CK+
10
14
ns
Setup & Hold time
tiS
Input
Input or
feedback
CK+
7
9
ns
tlH
Input
CK+
Input or
feedback
0
0
ns
a±
3
Propagation delay
IcKO
Clock
CK±
IcKF
CIock3
CK±
a
!Po
Output (2OLS, R6, R4)2
I, B
Output
IoE1
Output enable4
DE
Output enable
3
S
IoE2
Output enable4 •s
I
Output enable
3
1001
Output disable'
DE
Output disable
1002
Output disable4 •s
I
Output disable
tSKW
Output
Q
Q
1
1
ns
!PPR
Power-Up Reset
Vee+
Q+
10
10
ns
7.5
ns
3
7
ns
7.5
10
ns
3
10
ns
10
3
10
ns
3
S
3
10
ns
3
10
3
10
ns
6.5
3
Frequency (20R8, R6, R4)
No feedback 11 (lcKL + IcKH)6
Internal feedback 11 (tiS + IcKF)6
fMAX
.
. ..
External feedback 11 (tIS + IcKO)6
.
..
100
71.4
MHz
100
62.5
MHz
74
60.6
MHz
For defimnons of the terms, please refer to the Timing/Frequency Deflmbons tables .
NOTES:
1. CL = OpF while measuring minimum output delays.
2. tpo test conditions: CL = 50pF (with jig and scope capacitance), VIH = 3V, VIL = OV, VOH = VOL = 1.5V.
3. IcKF was calculated from measured Internal fMAX.
4. In reference to ~tate outputs, output enable times are tested with CL = 50pF to the 2.0V or O.SV level. Output disable times are tested with
CL = 5pF. High to HiglHmpedence tests are made to an output voltage of VT = Vrn;-O.5V: Low to HiglHmpedence tests are made to the
VT = VOL +0.5V level.
5. Same function as 1oE1 and 1001. with the difference of using product term control.
6. Not 100% tested, but calculated at initial characterization and at any time a modification in design takes place which may affect the frequency.
November 14, 1989
111
Product Specification
Signetics Programmable Logic Devices
PAL®-Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
TEST LOAD CIRCUIT
vr
10
<>--rI
I
I
I
I
In
r-r-
BoIOo
~
B"!o,,
I
DUT
--,-- Co
+sv
JTI~~
ANDJlG
CAPACITANCE
R,
I
o-L--
I
---..l- 0"
CK 0 - - - -
f---o
GND
R2.,..
llE
CL
~
OUTPUT REGISTER SKEW
CK
I r--------------------------3V
__________________
ov
0"
(REGISTERED OUTPUTj _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
0" .,
~"5V
~v~~
3V
ov
3V
(REGISTERED OUTPUTj ___________________
OV
CLOCK TO FEEDBACK PATH
~
I.
November 14. 1989
~KF
·1
112
Product Specification
Signeli<:s Programmable Logic Devices
PAL®~Type Devices
20L8,20R8,20R6,20R4
PLUS20R8D/-7 SERIES
I
f·
TIMING DIAGRAMS1. 2
~a
(INPUTS!
TIMING DEFINITIONS
, _ - - - - - _ ' , _ - - - - - - +3V
'--------------1
'--------------OV
,_--+3V
'-----,+---- ov
I RYMBOlI
tcKH
tcKL
Interval between dock pulses.
tcKP
Clock period.
tiS
Required delay between baginning of valid input and positive transition of dock.
tlH
Required delay between positive transition of clock and end
of valid input data.
!eKF
o output of flip-flop becomes
, - - - - - - - - - - +3V
'--r-----'--------
ov
!eKo
Delay between positive transition of clock and when outputs
become valid (with Of Low).
toe,
Delay between beginning of
Output Enable Low and when
outputs become valid.
100,
Delay between beginning of
Output Enable High and when
outputs are in the Off-State.
toe2
Delay between predefined
Output Enable High, and when
combinational outputs become
valid.
1002
Delay between predefined
Output Enable Low and when
combinational outputs are in
the Off-State.
IpPR
Delay between Vee (after power-on) and when flip-flop outputs become preset at "1" (internal outputs at "0").
Ipo
Propagation delay between
combinational inputs and outputs.
-------------------------------------------+3V
(INPU~:1_.5Y__________________________________________ ov
~-~---~D'-----~·'
o,a
(COMBINATORIAL
OUTPUTS)
'---------------~----V~
__________~~-~--2---------:V
I,a
(OUTPUT
Delay between positive transition of clock and when intemal
valid.
Flip-Flop Outputs
i
PARAMETER
Width of input clock pulse.
ENAaLE) __________J
Gate Outputa
a
Vee
Vee
OV
fMAX
Q~~~~~~~~----~
(REGISTERED
OUTPUTS)~~~~
VOL
+3V
~a
ONPUTS) _ _ _J
OV
+3V
CK
1.5V
OV
No feedback: Detennined by
the minimum clock period,
1/(IcKL + tcKH)·
Internal feedback: Determined by the internal delay
from flip-flop outputs through
the internal feedback and array
to the flip-flop inputs, I/(tls +
tcKF)·
External feedback: Determined by ctock-to-output
delay and input sebJp time,
1/(tlS + tcKO).
NOTES:
1. Input pulse amplitude is OV to 3V.
2. Input rise and fall times are 2.5os.
Power-tlp Reset
November 14, 1989
FREQUENCY DEFINITIONS
113
Signetics Programmable Logic Devices
Product Spedfication
PAL®-Type Devices
PlUS20R8D/-7 SERIES
20l8,20R8,20R6,20R4
PROGRAMMING
The PlUS20XX Series are programmable on conventional programmers for 24-pin PAl® devices. Refer 10 the following charts for qualified
manufacturers of programmers and software Iools:
PROGRAMMER MANUFACTURER
DATA I/O CORPORATION
10525 WilLOWS ROAD. N.E.
P.O. BOX 97046
REDMOND. WASHINGTON 98073-9746
(800)247-5700
STAG MICROSYSTEMS. INC.
1600 WYATI DRIVE
SUITE 3
SANTA CLARA. CALIFORNIA 95054
(408)988-1118
PROGRAMMER MODEL
FAMilY/PINOUT CODES
SYSTEM 29B. logicPak™ 303A-V04
ADAPTER
303A~11A-V08 (DIP)
303A~11 B-V04 (PLCC)
UNISITE 40/48. V2.3 (DIP)
V2.5(PLCC)
MODEL 60. SOA/H. V.13
ZL30/30A PROGRAMMER
REV.30A31
PPZ PROGRAMMER
TBA
SOFTWARE MANUFACTURER
2OL8-7/20L8D : 18126
2OR8-7/20R8D : 18127
2OR6-7/20R6D : 18127
2OR4-7/20R4D : 18127
2Ol8-7/20L8D
2OR8-7/20R8D
2OR6-7/20R6D
2OR4-7/20R4D
: 11156
: 11/57
: 11157
: 11157
DEVELOPMENT SYSTEM
SIGNETICS COMPANY
811 EAST ARQUES AVENUE
P.O. BOX 3409
SUNNYVALE. CALIFORNIA 94088-3409
AMAZE SOFTWARE
REV. 1.7
(408)991-2000
DATA 110
10525 WILLOWS ROAD. N.E.
P.O. BOX 97046
REDMOND. WASHINGTON 98073-9746
ABELTM SOFTWARE
REV. 1.0 AND LATER
(800)247-5700
LOGICAL DEVICES. INC.
1201 NORTHWEST 65TH PLACE
FORT LAUDERDALE. FLORIDA 33309
CUPLTM SOFTWARE
REV. 1.01 AND LATER
(800)331-7766
November 14. 1989
114
Signetics
PHD48N22-7
Document No.
ECN No.
Date of Issue November 1989
Status
Preliminary Spec~ication
Programmable High-Speed
Decoder Logic (48 x 73 x 22)
Programmable Logic Devices
DESCRIPTION
The PHD48N22-7 is an ukra fast
Programmable High-speed Decoder featuring a 7.5ns maximum propagation
delay. The arch~ecture has been optimized using Philips ComponentsSignetics state-of-the-art bipolar oxide
isolation process coupled with titaniumtungsten fuses to achieve superior speed
in any design.
FEATURES
• Ideal for high speed system
decoding
A Package
• Super high speed at 7.Sns tpo
• 36 dedicated Inputs
.22 outputs
- 12 bidirectional 110
- 10 dedicated outputs
The PHD48N22-7 is a two level logic
element comprised of 36 fixed inputs,
73 AND gates, 10 outputs, and 12 bidirectional VOs. This gives the device the
ability to have as many as 48 inputs. Individual 3-State control of all outputs is
also provided.
• Security fuse to prevent duplication
of proprietary designs.
The device is field-programmable, enabling the user to quickly generate custom
patterns using standard programming
equipment. Proprietary designs can be
protected by programming the security
fuse.
• Available In 68-Pln Plastic Leaded
Chip Carrier (PLCC)
The AMAZE software package from
Philips Components-Signetics supports
easy design entryforthe PHD48N22-7 as
well as other PLD devices.
• High speed code detectors
Order codes are listed in the pages
following.
PIN CONFIGURATION
2ti
• Individual 3-State control of all
outputs
• Fleld-programmable on Industry
standard programmers
APPLICATIONS
• High speed memory decoders
• Random logic
• Peripheral selectors
• Machine state decoders
Pin
Function
"'11
3
4
5
6
7
8
•
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
12
VCC3
13
14
15
16
17
18
Pin
35
36
37
38
39
40
41
42
43
44
45
I.
110
111
GND5
GND1
112
113
114
115
116
VCC2
117
118
11.
120
121
122
123
124
125
126
GND3
127
128
46
47
46
4'
50
51
52
53
54
55
56
57
56
59
60
61
62
63
64
65
66
67
68
function
129
130
131
VCC4
132
133
134
135
BO
81
82
83
B4
GNDS
GND2
B5
B6
B7
00
01
VCC1
02
03
04
05
06
07
08
09
ORO
OR1
GN04
OR2
OR3
PHILIPS
115
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder Logic (48 x 73 x 22)
PHD48N22-7
LOGIC DIAGRAM
I.
13~""111111~~:
07
06
05
04
03
O.
01
00
B7
14
15
B5
16
B4
17
B3
18
B.
III
Bl
110
BO
111
115
116
117
118
119
I~~~~~~~~~~ffit~~~~im~~~~~t#~~~~~~~n===~~--~
NOTES:
1..AN unprogrammed or virgin "AND" gate locadone are pulled to logic ''0''
2.3,{i Pro rammabte connection.
November 1989
116
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder Logic (48 x 73 x 22)
PHD48N22-7
FUNCTIONAL DIAGRAM
I
i
>
··
10
'35
>
~t----
>
-----12.
~
92
V
12
r-I
---D-C
J
THERMAL RATINGS
DESCRIPTION
ORDER CODE
68-Pin Plastic Leaded Chip Carrier
PHD48N22-7A
TEMPERATURE
ABSOLUTE MAXIMUM RATINGS1
RATINGS
PARAMETER
Min
Max
Vee
Supply voltage
~.5
+7
Vrx;
VtoI
Input voltage
~.5
+5.5
Vrx;
VOUT
Output voltage
+5.5
Vrx;
I.N
Input currents
+30
mA
lOUT
Output currents
+100
mA
TA
Operating temperature range
+75
·C
...,'3()
0
UNIT
Storage temperature range
·C
~5
+150
TSTG
NOTES:
1. Stresses abow those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification 01 the device is not implied.
OPERATING RANGES
RATINGS
SYIiBOL
PARAMETER
Vee
Supply voltage
T"
Operating lr8e-air temperature
Nowmber 1989
ORo
:::::: OR,- OR3
ORDERING INFORMATION
SYMBOL
00- 0 8
""
~r-D
~, 110- 8 7
IIln
lIax
UNIT
+4.75
+5.25
Vrx;
0
+75
OC
117
Maximum junction
150°C
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder Logic (48 x 73 x 22)
PHD48N22-7
DC ELECTRICAL CHARACTERISTICS O°C oS TA -< +75°C, 4.75 oS Vee oS 5.25V
UMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Vee=MIN
Vee = MAX
Vee = MIN, liN = -18mA
2.0
Typ1
Max
UNIT
0.8
V
V
-1.5
V
0.5
V
V
-250
IJA
IJA
IJA
Input voltage2
V IL
V IH
Vc
Low
High
Clamp
--{).8
Output voltage
Vee = MIN, VIN = VIH or VIL
VOL
VOH
Low
High
IOL= +24mA
IOH =-3.2mA
2.4
Input current
Vee = MAX
IlL
Low
VIN = +O.40V
IIH
High
VIN = +2.7V
-20
25
II
High
VIN = Vee = Vee MAX
100
Output current
Vee = MAX
IOZH
Output leakage 3
VOUT = +2.7V
100
loll.
los
Output leakage 3
VOUT = +O.40V
VOUT= +OV
-100
IJA
IJA
-90
mA
lee
Vee current
420
mA
Short circuit 4
-30
-60
Vee = MAX
CapacitanceS
CIN
COUT
Input
I/O
Vee = +5V
VIN = 2.0V@I= lMHz
VOUT= 2.0V@I= 1MHz
8
8
NOTES:
1.
2.
3.
4.
5.
Typical limits are at Vee = 5.0V and TA = +25°C.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
Leakage current lor bidirectional pins is the worst case 01 IlL and loll. or IIH and loll..
Not more than one output should be tested at a time. Duration 01 the short circuit should not be more than one second.
These parameters are not 100% tested, but are periodically sampled.
November 1989
118
pF
pF
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder Logic (48 x 73 x 22)
PHD48N22-7
AC ELECTRICAL CHARACTERISTICS OOC.s TA.s +75°C, 4.75 -< Vee.s 5.25V,
R1 = 2Oan, R2 = 3900
LIMITS
TEST
SYMBOL
TO
Max
UNIT
CL=5OpF
7.5
ns
Output±
C L = 50pF
10
ns
(I,B,OR)±
Output enable
CL = SOpF
10
ns
(I,B,OR)±
Output disable
CL = 5pF
10
ns
PARAMETER
FROM
Min
CONDITIONS
tP01 1
Propagation delay
through BIO outputs
(I,B,OR)±
Output±
1p[)21
Propagation delay
through OR outputs
(I,B,OR)±
IoE2
Output Enable
1002
Output Disable
NOTES:
1. tp01,2 are tested with switch S1 closed and CL = 50pF.
2. For 3-State output; output enable times are tested with C L = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C L = 5pF. High-to-High impedance tests are made to an output voltage of VT = VOH - 0.5V with S1 open, and Low-to-High impedance tests are made to the VT = VOL + 0.5V level with S1 closed.
VIRGIN STATE
TIMING DEFINITIONS
A factory shipped virgin device contains all
fusible links open, such that:
1. All outputs are disabled.
SYMBOL
PARAMETER
!pe1
Input to output propagation
delay (through BIO outputs).
!pe2
Input to output propagation
delay (through OR outputs).
100
Input to Output Disable
(3-State) delay (Output
Disable).
toE
Input to Output Enable delay
(Output Enable).
2. All p-tenns are disabled in the AND array.
TIMING DIAGRAM
aov
INPUTS, 110
"'IV"""
VOl.
WAVEFORM
Nowmber 1989
INPUTS
OU11'UTS
MUST BE
STEADY
WlLJ.BE
STEADY
WAVEFORM
~
]) ([
119
INPUTS
OU11'UTS
DON'T CARE;
ANY CHANGE
CHANGING;
STATE
UNKNOWN
PERIITTED
DOES NOT
APPLY
CENTER
UNEISHIGH
IMPEDANCE
"OFF'STATE
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder Logic (48 x 73 x 22)
PHD48N22-7
VOLTAGE WAVEFORMS
AC TEST LOAD CIRCUIT
vcc
INPUTS
2.500
2.500
MEASUREMENTS:
All circuit delays are measured at the + 1.5V level of
il1>ut8 and outputs, unless otherwise specified.
Input Pulses
LOGIC PROGRAMMING
PHD48N22-710gic designs can be generated
using any commercially available, JEDEC
standard design software.
To implement the desired logic functions, each
logic variable (I, B, P and D) from the logic
equations is assigned a symbol. TRUE (High),
COMPLEMENT (Low), DON'T CARE and
INACTIVE symbols are defined below.
PHD48N22-7 designs can also be generated
using the program table format, detailed on the
following page. This program table entry (PTE)
format is supported on the Signetics AMAZE
PLD design software. AMAZE is available free
of charge to qualified users.
1
1
11'
8
1
1
1
"AND" ARRAY - (I, B)
~B
I,B
I,B
1,8
r,B
P,D
I
STATE
INAcnve'
I
P,D
COOE
0
I
I
STATE
TRUE
I
r,B
'8
P,D
CODE
H
I
I
NOTE:
1. This is the initial state.
November 1989
I,B
I,B
'8
~B
120
STATE
COMPLEMENT
I
P,D
CODE
L
I
I
STATE
DON'TCARE
CODE
I - I
Preliminary Specification
Signetics Programmable Logic Devices
Programmable High-Speed
Decoder Logic (48 x 73 x 22)
PHD48N22-7
PROGRAM TABLE
ItlPUT"
T
~
E
B
OR
7
,
5
4
3
2
1
•
72
AN 42 41 40 39 37 36 3631 33 31 3. 29 2827 26 25 24 23 22 20 19 18 17 16 13 12 11 10 9
8
7
•
5
3
2
1 52 51 50 47 46 45 44 .. 68 67 65 64
R
II 36
•
I
3332 31 30 2929
2625 2423
21 20 18 18 17 16 1
14 13 1
11 10
8
7
6
5
4
3
2
1
•
3
2
1
•
1
2
3
4
,
,.•
5
7
8
11
"
13
"
15
16
17
18
18
20
21
22
23
24
25
26
27
28
29
30
31
32
33
31
36
311
37
38
38
40
"42
.
43
45
"
47
48
48
50
51
52
53
54
55
$6
57
58
50
60
61
62
63
"
65
16
67
..
68
70
71
'!I",
~~
~
November 1989
121
Signetics Programmable Logic Devices
Preliminary Specification
Programmable High-Speed
Decoder Logic (48 x 73 x 22)
PHD48N22-7
PROGRAM TABLE (Continued)
OUTPUTS
T
E
M
B
0
R
I
II
13
1
7
I
5
OR
2 1
4
3
4
46~ 4443
0
1
0
1
2
3
4
5
I
7
•
I
10
11
12
13
14
15
16
,.
17
11
20
21
22
23
:14
25
21
71
as
as
311
31
32
33
34
35
35
37
••
40
41
42
43
44
45
41
47
48
48
50
51
51!
S'I
54
35
51
S/
58
58
110
11
12
13
114
15
II
17
••
70
71
72
6
~
61
.
54
51
l!!.6 i!!.l!!.
!=J
November 1989
122
Signetics Programmable Logic Devices
Preliminary Specification
Programmable High-Speed
Decoder Logic (48 x 73 x 22)
PHD48N22-7
TYPICAL SYSTEM APPLICATION
r----------------------,
H
I
I
I
CLOCK
rRESET
CLK2
OPT10NAL
CACHE
s::"
:
PHD48N22h~
F1fI i
II
C::L
1----'--'----_ _
~-------~--~-::--J
ADDR'--ES,!"-'--I
811386
'-H----r------,
CPU
r
DATA
IN liN
.
~J
"
.1'\~r----"'------,
r-
LS
DRAM
DRAM
CONTROL
r-
L rr110 INTERFACE
,,,'_ _ _ _ _--,/ MULT1BUS 110
r--
r--
LOCAL
BUS
CONTROL
ADVANCED
DMA
1
Il I
II
I
~
~:~ II
II
1
INTERRUPT
CONTROUER
1r
EXTERNAL
INTERRUPTS
T1MER!
COUNTER
FLOPPY
DISK
CONTROL
~
FLOPPY
Nowmber 1989
CONTROL
LAN
II
I
~ D DD
I III
CONTROL
SERIAL
PORTS
>{}
GRAPHCS
6 ±:~~ b~I~J
RXEDDISK
123
I
CRT
I
I
D
EPROM
I
'------'
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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Signetics
Section 4
Programmable Logic Array
Device Data Sheets
Programmable Logic Devices
INDEX
Series 20
PLS153/A
Programmable Logic Arrays (18 x 42 x 10); 40/30ns ....... 127
PLUS153B/O
Programmable Logic Arrays (18 x 42 x 10); 15/12ns ....... 134
PLUS153-10
Programmable Logic Array (18 x 42 x 10); 10ns ........... 141
Series 24
PLS173
PLUS173B/O
PLUS173-10
Programmable Logic Array (22 x 42 x 10); 30ns ........... 148
Programmable Logic Arrays (22 x 42 x 10); 15/12ns ....... 154
Programmable Logic Array (22 x 42 x 10); 10ns ........... 161
PLHS473
PLHS473S
Programmable Logic Array (20 x 24 x 11); 22ns ........... 168
Programmable Logic Array (20 x 24 x 11); 25ns ........... 174
Series 28
PLS100/101
Programmable Logic Arrays (16 x 48 x 8); 50ns ........... 181
Signetics
Document No.
85~311
ECN No.
97883
PLS153/A
Field-Programmable Logic Arrays
(18 x 42 x 10)
Date of Issue October 16, 1989
Status
Product Specification
I Programmable Logic Devices
I
DESCRIPTION
The PLS 153 and PLS 153A are twcr-Ievel
logic elements, consisting of 42 AND
gates and 10 OR gates with fusible link
connections for programming I/O polarity
and direction.
All AND gates are linked to 8 inputs (I) and
10 bidirectional 110 lines (8). These yield
variable 110 gate configurations via 10
direction control gates (D), ranging from
18 inputs to 10 outputs.
On-chip T/C buffers couple either True
(I, 8) or Complement (1. B) input polarities
to all AND gates, whose outputs can be
optionally linked to all OR gates. Their
output polarity, in turn, is individually programmable through a set of Ex-OR gates
for implementing AND/OR or ANDINOR
logic functions.
PIN CONFIGURATIONS
FEATURES
• Field-Programmable (NI-Cr links)
N Package
.8lnputs
vcc
• 42 AND gates
8.
.10 OR gates
8a
87
.10 bidirectional 110 lines
lit;
• Actlve-Hlgh or -Low outputs
8.
a.
• 42 product terms:
- 32 logic terms
- 10 control terms
8,
~
GNO
• 110 propagation delay:
- PLS153: 40ns (max)
- PLS153A: 30ns (max)
N _ Plastic
A Package
• Input loading: -100fJA (max)
I,
10 VCC IIg
• Power dissipation: 650mA (typ)
• 3-State outputs
The PLSl53 and PLS153A are fieldprogrammable, enabling the user to
quickly generate custom patterns using
standard programming eqUipment.
• TTL compatible
Order codes are listed in the Ordering
Information Table.
APPLICATIONS
• Random logiC
• Code converters
110 GNO
B, ~
sa
A .. Plastic Leaded Chip Carrier
• Fault detectors
• Function generators
LOGIC FUNCTION
• Address mapping
TYPICAL PRODUCT TERM:
Pn.A·8·C·O· •••
• Multiplexing
TYPICAL LOGIC FUNCTION:
AT OUTPUT POLARITY. H
Z=PO+P1+P2 •••
AT OUTPUT POLARITY. L
Z=PO+P1+P2 + ...
Z.l'IJ·Pf·~·
..•
NOTES:
1. For each of the 10 outputs. either function Z (ActiveHigh) Of Z (AdiYe-low) is avaiiabie. but not both.
2.
The desired output polarity is prograrrrned via the
Ex-OR gates.
Z. A. B. C. etc. are USet defined connections to fixed
inpUis (I) and bidirectional pins (8).
PHILIPS
127
Product Specification
Signetics Programmable Logic Devices
Field-Programmable Logic Arrays {18 x 42 x 10}
LOGIC DIAGRAM
NOTES:
1. AN programmed 'AND' gate locations are pulled to loglc·1~.
2. All programmed 'OR' gate locations are pulled to logic "0".
3. ;:;-. Programmable conneCtion.
October 16, 1989
128
PLS153/A
Product Specificaticn
Signetics Programmable Logic Devices
PLS153/A
Field-Programmable Logic Arrays (18 x 42 x 10)
FUNCTIONAL DIAGRAM
~~~======t=====t==+
q~~======t=====t=~
H--l>--<>----h--o ..
=
THERMAL RATINGS
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE
ORDER CODE
20-Pin Plastic Dualln-Line, 300mil-wide
PLSl53N,PLS153AN
Maximum junction
150°C
20-Pin Plastic Leaded Chip Carrier
PLSl53A,PLSl53AA
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
7SoC
ABSOLUTE MAXIMUM RATINGS1
RATINGS
SYMBOL
PARAMETER
Min
Max
UNIT
Vee
Supply vcltage
+7
Vee
VIN
Input voltage
+5.5
Vee
VOUT
Output voltage
+5.5
Vee
lIN
Input currents
+30
mA
lOUT
Output currents
+100
mA
TA
Operating temperature range
0
+75
°C
TSTG
Storage temperature range
~5
+150
°C
-30
NOTES:
1. Stresses above those listed may cause malfunction or permanent demage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
October 16, 1989
129
The PLSl53/A devices are also processed to
military requirements for operation over the
military temperature range. For specifications
and ordering informaticn consult the Signetics
Military Data Handbook.
Product Specification
Signetics Programmable Logic Devices
PLS153/A
Field-Programmable Logic Arrays (18 x 42 x 10)
DC ELECTRICAL CHARACTERISTICS oOc S TA S +75°C, 4.75V S Vee S 5.25V
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ1
Max
UNIT
Input voltage!
VL
Low
VH
Vr;;
High
Clamp2,3
Vee = Min
Vee = Max
Vee = Min, liN = -12mA
0.8
V
-1.2
V
V
2.0
-0.8
Output voltage
Vee = Min
VOl
VOH
L0w2,4
HigtJ2.5
10l= 15mA
IOH=-2mA
0.5
V
V
2.4
Input current'
Vee = Max
IL
Low
VIN= 0.45V
-100
IIH
High
VIN =5.5V
40
IlA
IlA
Vour= 5.5V
80
IlA
Vour= 0.45V
-140
Output current
Vee = Max
IO(OFF)
Hi--ZstamB
los
Short circuit!· 5, B
Vour=OV
lee
Vee supply current?
Vee = Max
-15
130
-70
mA
155
mA
Capacitance
Vee =5V
Input
CIN
VIN = 2.0V
I/O
Ca
Va = 2.0V
NOTES.
1. All typical values are at Vee = 5V, TA = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with + 1OV applied to 17.
5. Measured with + 10V applied to 10-7. Output sink current is supplied through a resistor to Vee.
6. Duration of short circuit should not exceed 1 second.
7. lee is measured with 10, 1, at OV, 12 - 17 and B"-'l at 4.5V.
8. Leakage values are a combination of input and output leakage.
9. IL and IIH limits are for dedicated inputs only (10 -17)'
October 16, 1989
130
8
15
pF
pF
Signetics Programmable Logic Devices
Product Specification
Field-Programmable Logic Arrays (18 x 42 x 10)
PLS153/A
AC ELECTRICAL CHARACTERISTICS oOc :S;TA:S; +7SoC, 4.7SV:S; Vcc :S;S.2SV, Rl = 470Q, R2 = lkQ
I
i
,
I
SYMBOL
PARAMETER
FROM
,
,
TO
TEST
PLS153
CONDITION
I
Uiiii,l>
Min
UNIT
PLS153A
Typl
Max
Min
I
Typl
Max
Propagation delay
Input±
Output±
CL = 30pF
30
40
20
30
ns
toE
Output enable
Input±
Output-
CL = 30pF
25
35
20
30
ns
100
Output disable2
Input±
Output +
= SpF
2S
35
20
30
ns
!Po
NOTES:
1. All typical vaiues are at Vcc = SV, TA
2. Measured at V T = Vex + O.SV.
CL
=+2SoC.
VOLTAGE WAVEFORMS
TEST LOAD CIRCUIT
? vce
J:;.sv
~Io
I
I
I
I
o-l-- ~7
ANDJlG
Rl
BVT
001
~ Bw
o---L-
BZ
BX
GND
~
MEASUREMENTS:
AI circuit delays are measured at the + 1.5V level
of lf1Juts and outputs, unl888 otherwise specified.
Input Pulses
TIMING DEFINITIONS
SYMBOL
TIMING DIAGRAM
PARAMETER
tpo
Propagation delay between
input and output.
100
Delay between input change
and when output is off (Hi-Z
or High).
toE
Delay between input change
and when output reflects
specified outputleve\.
October 16,1989
131
I
I
f-J.-
R2,:"
CAPACITANCE
J
Cl
Product Specification
Signetics Programmable Logic Devices
PLS153/A
Field-Programmable Logic Arrays (18 x 42 x 10)
OUTPUT POLARITY - (8)
LOGIC PROGRAMMING
PLSl531A logic designs can be generaIBd
using Signetics AMAZE PLD design software
or one of several other commercially available,
JEDEC standard PLD design software packages. Boolean anc:flor staIB equation entry is
acceplBd.
PLSl531A logic designs can also begeneralBd
using the program table entry format detailed
on the following page. This program table entry
format is supporlBd by the Signetics AMAZE
PLD design software (PTP module). AMAZE is
available free of charge to qualified users.
S
S-x-l~D-a
I
ACTIVE LEVEL
I
CODE
I
I(~,:=:mNG) I H I
x!
L
ACTIVE LEVEL
I
~NYERTING)
LOW
D-IJ
CODE
I
I
L
To implement the desired logic functions, the
staIB of each logic variable from logic equations
(I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
AND ARRAY - (I, 8)
~a
1
~a
~a
U
1
I,a
1
liD
P,D
I
~a
~IJ
~a
1
STATE
OR ARRAY - (8)
~a
~IJ
P,D
P,D
STATE
STATE
~a
~IJ
I
STATE
VIRGIN STATE
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at "H" polarity.
--f=>-.
CODE
A
2. All Pn IBrms are disabled.
3. All Pn terms are active on all outputs.
CODE
•
INACTIVE
NOTES:
1. This is the initial unprogrammed staIB of all links.
2. Any gate Pn will be unconditioanllyinhibilBd if both the True and Complementofan input (either
I or B) are left intact.
CAUTION: PLS153ATEST
COLUMNS
The PLS153A incorporaIBs two columns not
shown in the logic block diagram. These columns are used for in-house IBsting of the device in the unprogrammed staIB. These
columns must be disabled prior to using the
PLS 153A in your apprlCation. If you are using a
Signetics-approved programmer, the disabling
is accomplished during the device programming sequence. If these columns are not disabled, abnormal operation is possible.
Furthermore, because of these IBst columns,
the PLS153A cannot be programmed using the
programmer algorithm for the PLS153.
OcIDber 16, 1989
132
Prcduct Specification
Signetics Programmable Logic Devices
PLS153/A
Field-Programmable Logic Arrays (18 x 42 x 10)
FPLA PROGRAM TABLE
POlARITY
I II
LJ
~
f ~
I
~
T
~
~)
I
I I
OR
AND
0 8 8
l-i=----lf-7+6+-5+-4...3+_2f-'++-+-...
:7+_61-5+4+3+-2+--'+-0--1
8(0)
8.1765432.0
!
i
i
1~3~-+-+~~+-~~-+~~4-+-~~-4~
it 1----:-4 -++--I-+-f-f-+-I-+-f---l-4-I-+-+-+-+-+-I
I
I
~ ~ ~j 1---c::---lH-4-+-+--+---1--+-++-i-~~H-+-+-+--I
g~
~ ~
w
1-;7:-iH-+-+-+++++-+--f-f-HI..--J-+-++--I
a: 1-;:-iH-+-+-+++++-+-.J-f-HH-+-+-+--I
8
:ll i! 1-;8~H-+-+-+++++-+-+-HH-'-+-++--I
ffi ~ ~~'-O~~+-+-~~H-4-+-+--+---1-4-++-+-~
fII
~ ~ i~:-:~~+-+-r-~H-4-+-r--+-~-+-;-+-+-~
u
f2
B.
'3
'4
.5
1&
.7
18
'8
20
2.
22
23
24
25
27
30
:
I
~
,
~
:r-r-;
:~rw
~I ~ ~
: !i i
:~--=
,
,
,
:
:
, ':r
PT
De
D8
:I:~I:IIII~~
: :l!l!J
,
,
:
:
_1_ ......... _' ...
.J ... ... ... ...
04
D3
D2
D1
DO
i
...
PIN
I
8 7 6 5 4 3 2 • '8
18
i'
c:
October 16, 1989
133
.7 .8 .5 .4 .3 .2 11 8
'8
18 17
.6 .5 .4 '3 .2 11 8
Signefics
Document No. 853-1285
ECN No.
97081
Date of Issue July 12, 1989
Status
Product Specification
PLUS153B/D
Programmable Logic Arrays
(18 x42 x 10)
Programmable Logic Devices
DESCRIPTION
The PLUS153 PLDs are high speed, combinatorial Programmable Logic Arrays.
The Signetics state-of-the-art Oxide Isolated Bipolar fabrication process is
employed to produce propagation delays
as short as 12ns.
The 2O--pin PLUS 153 devices have a programmable AND array and a programmable OR array. Unlike PAL® devices,
100% product term sharing is supported.
Any of the 32 logic product terms can be
connected to any or all olthe 10 output OR
gates. Most PAL ICs are limited to 7 AND
terms per OR function; the PLUS153 devices can support up to 32 input wide OR
functions.
The polarity of each output is user-programmable as either active-High or
active-Low, thus allowing AND-OR or
AND-NOR logic implementation. This
feature adds an element of design flexibility, particularly when implementing complex decoding functions.
The PLUS 153 devices are user-programmable using one of several commercially
available, industry standard PLD programmers.
FEATURES
• 110 propagation delays (worst case)
PIN CONFIGURATIONS
N Package
- PLUS153B - 15ns max.
vee
- PLUS153D - 12ns max.
IIg
lie
• Functional superset of 16L8 and
most other 20-pln combinatorial
PALdevlcas
87
lie
B.
• Two programmable arrays
B4
- Supports 32 Input wide OR
functions
B3
B2
.8lnputs
GND
• 10 bl-dlrectionall/O
N _ Plastic
• 42 AND gates
A Package
- 32 logic product terms
'2
- 10 direction control terms
"
10 vee
IIg
• Programmable output polarity
- Active-High or Active-Low
• Security fuse
• 3-State outputs
lie GND B, a,
• Power dissipation: 750mW (typ.)
83
A • Plastic Leaded Chip Carrier
• TTL Compatible
APPLICATIONS
• Random logic
• Code converters
• FauH detectors
• Function generators
• Address mapping
• MuHiplexlng
®PAL is a registered trademark of Monolithic Memorkts. Inc., a wholly OYIfled subsidiary of Advanced Mm Devices Corporation.
PHILIPS
134
Product Specification
Signetics Programmable Logic Devices
Programmable Logic Arrays
(18 x 42 x 10)
PLUS1538/0
LOGIC DIAGRAM
----__
31 ••••• _24 23_ •••• _1615_ ••••• 8 7 ••••••
oXo ...
NOTES:
t. AU programmed 'AND' gate1ocallons are pulled 10 logic "t".
2. All programmod 'OR' gate locations are pulled 10 logic -0".
3. .;:_' Programmable connection.
July 12, 1989
135
__ (CONTROL TERMS) _
Product Specification
Signetic:s Programmable Logic Devices
Programmable Logic Arrays
(18 x 42 x 10)
PLUS153B/D
FUNCTIONAL DIAGRAM
>------...1....0110
ORDERING INFORMATION
DESCRIPTION
THERMAL RATINGS
TEMPERATURE
"",(MAX)
ORDER CODE
2O-Pin Plastic DIP 3OOmil--wide
15ns
PLUSl53BN
Maximum junction
150°C
2O-Pin Plastic DIP 3OOmil-wide
12ns
PLUSl53DN
Maximum ambient
75°C
2O-Pin Plastic Leaded Chip Carrier
15ns
PLUSl53BA
75°C
2O-Pin Plastic Leaded Chip Carrier
12n8
PLUSl53DA
Allowable thermal rise
ambient to junction
ABSOLUTE MAXIMUM RATlNGS1
RATING
SYMBOL
PARAMETER
Max
UNIT
+7
Vee
Input voltage
+5.5
Vee
VOUT
Output voltage
+5.5
Vee
'IN
Input currents
+30
mA
+100
mA
0
+75
OC
-05
+150
Vex;
Supply wllage
Vin
lOUT
Output currents
TA
Operating lree-iIir 1emperature range
Storage 1emperature range
Min
-30
TSTG
°C
NOTES:
1. Stresses above those listed may cause maHunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
July 12, 1989
136
The PLUS153 devices are also processed to
military requirements for operation over the
military 1emperature range. For specifications
and ordering information consult the Signetics
Military Data Book.
Product Specification
Signetics Programmable Logic Devices
Programmable logic Arrays
(18 x 42 x 10)
.
PlUS1538/0
DC ELECTRICAL CHARACTERISTICS oOc
SYMBOL
PARAMETER
Input voltage:!
~ TA ~ +75°C, 4.75 ~ Vee ~ 5.25V
I
i
VL
Low
Vee~
VIH
High
Vee ~ Max
Vc
Clamp
Typl
Min
I
J
LIMITS
TEST CONDITIONS
Max
UNIT
0.8
V
Min
V
2.0
Vee ~ Min, liN ~ -12mA
~.8
-1.2
V
0.5
V
Output voltage
Vee~
VOH
Min
IOL ~ 15mA
Low'
HighS
VOL
IOH~-2mA
2.4
V
Input currenti'
Vee ~ Max
Ill.
Low
IIH
High
40
IlA
IlA
VOUT ~ 5.SV
80
IlA
VOUT ~ 0.45V
-140
VIN
~
-100
0.45V
VIN ~ Vee
Output current
Vee ~ Max
Hi-Z stateS
IO{OFF)
los
Short circuit3, s. 6
VOUT
lee
Vee supply current1
Vee ~ Max
Input
V IN
~
2.0V
8
pF
110
VB
~
2.0V
15
pF
~
OV
-15
-70
mA
200
mA
150
Capacitance
Vee
C IN
CB
~
5V
NOTES:
1. All typical values are at V ee ~ 5V, TA ~ +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with inputs 10 - 12 ~ OV, inputs 13 - Is ~ 4.SV, inputs 17 ~ 4.5V and 16 ~ 10V. For outputs
same conditions except 17 ~ Ov.
5. Same conditions as Note 4 except 17 ~ + 10V.
6. Duration of short circuit should not exceed 1 second.
7. lee is measured with inputs 10 -17 and So - Bg ~ OV.
8. Leakage values are a combination of input and output leakage.
9. III and IIH limits are for dedicated inputs only (10 -17)'
AC ELECTRICAL CHARACTERISTICS oOc ~ TA ~ +75°C,
4.75V ~ Vee ~ 5.2SV,
So -
B4 and for outputs Bs - B9 apply the
R, = 470Q, R2 = 11<0
UMITS
SYMBOL
PARAMETER
FROM
TO
CONDITION
!PD
toE
toD
PLUS153B
TEST
Min
UNIT
PLUS153D
Typ
Max
Min
Typ
Max
Propagation Delay 2
Input +/-
Output +/-
CL = 30pF
11
15
10
12
Output Enable
Input +/-
Output-
CL = 30pF
11
15
10
12
ns
Output Disable'
Input +/-
Output +
CL = 5pF
11
15
10
12
ns
NOTES:
1. Measured at VT = VOL + 0.5V.
2. Measured with all inputs and outputs switching simultaneously.
July 12, 1989
137
ns
$ignatics Programmable Logic Devices
Product Specification
Programmable logic Arrays
PlUS153B/D
(18 x 42 x 10)
VOLTAGE WAVEFORMS
TEST LOAD CIRCUIT
-
yvcc
<>-rI
I
o-l-
<>--r-~
10
I
I
I
17
OUT
Bw
GND
~
MEASUREMENTS:
Input Pulses
TIMING DEFINITIONS
SYMBOL
tpo
Propagation delay between
input and output.
100
Delay between input change
and when output is off (Hi-Z
or High).
toe
Delay between input change
and when output reflects
specified output level.
July 12, 1989
TIMING DIAGRAM
PARAMETER
138
Bvt-TI
I
BZ
BX
AN cifcutl: de{ays are measured at the + 1.5V level
of l'1luts and outputs, unless ctherwlse specified.
¥rR,
1-1-
RZ,:,
AND JIG
CAPACITANCE
J
CL
Product Specification
Signetics Programmable Logic Devices
Programmable Logic Arrays
(18x42x10)
LOGIC PROGRAMMING
PLUS1538/D
OUTPUT POLARITY - (B)
PLUSt 53 logic designs can be generated
using Signetics AMAZE PLD design software
or one of several other commercially available,
JEDEC standard PLD design software packages. Boolean equation entry is accepted.
PLUSI53 logic designs can also be generated
using the program table entry format detailed
on the following pages. This program table
entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
users.
'ro-' 'ro-'
To implement the desired logic functions, the
state of each logic variable from logic equations
(I, S, 0, P, etc.) is assigned a symbol. Thesymbois for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
I,B1 'B 1 'B
AND ARRAY - (I, B)
~B
1 ~B
~B
~B
1~B
P,D
I
1
~B
P,D
P,D
STATE
STATE
~B
~B
STATE
OR ARRAY - (B)
1
r,B
P,D
STATE
DON'TeARE
VIRGIN STATE
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at "W polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.
CODE
PnSTATUS
CODE
A
INAClIVE
•
NOTES:
1. This is the initial unprogrammed state of all links.
2. Any gate Pn will be unconditionally inhibited if both the true and complement of an input (either
I or S) are left intact.
July 12, 1989
139
Signetics Programmable Logic Devices
Product Specification
Programmable Logic Arrays
(18 x 42 x 10)
PLUS1538/0
PLA PROGRAM TABLE
POLARITY
iJ J
II II
8(0)
7 6
41 2 O 9 8
5
2
I-l-=---1f-+ +'+-...-'t--f-'++ +-+-7t--f-5- 1B(1f-4-t-'+
)
+-'+0-;
~
Iil
~
d1-::-1HH-t-t-+++++-+-t-t--HH-+-+-;
~ 1-5:-1H-++-+-+-t-HH-+-+-++-+-HH--l
~ j
1876543210
I
IZ:
~
::E
::Ec(i=::EZ~
I----:.-=-o+++-t-f-t--H-f-t-t++++-+-t-H
11
eQWe~ClI----:;;-t-+-+-+-+-+-t-H--+-+-t-++-T-H-t--1
~
:;
()
Q.
~ ~
en ()
,
!
!
6
::~2~
7
W W Q _ 0 ~ I-::--1HH-t-+-+++++-+-t-t--HH-+-+-l
~zOcenlll~
~ 1ri ~ ffi III 1-~::--1HH-t--+-+++++--t-t-t--HH-+-+-;
•
ffi :ll !3 ffi
I I I
OR
AND
T
e ~ I----:;=-:++-+-+-t-HH-f-t--t-+++-t-+-t-H
I-'
Q.
.4
,,
:
i
i
I
,
20
,
I
2.
!
.5
I
.6
17
18
22
23
24
25
-.l
J
26
,
27
I
26
·:
I
..
::
~
r--r;-,
I
~
_
,
De
I
~ J= '
I
II=CJlla~
'u:l"~9
:
:~~:
·
·
..
_I _____ I_J ____
I
I
DO
D3
D2
01
DO
8
7
6
5
4
3
2
•
11.8 17 .6 .5 .4 '3 '2 11
oJ
Q'
~:
··
··
··
·
July 12.1989
,
D6
PIN
•
i
i
D7
D6
o
,
!
140
•
••• 8 17 .6 .5 .4 .3 .2 11
•
Signetics
PLUS153-10
Document No.
ECN No.
Date of Issue
November 1989
Status
Preliminary Specification
p~c 9 rammab!e
Lonic Devices
Programmable Logic Array
(18 x 42 x 10)
PIN CONFIGURATIONS
DESCRIPTION
FEATURES
The PLUS153-10 PLD is a high speed,
combinatorial Programmable Logic Array.
The Signetics state-of-the-art Oxide
Isolated Bipolar fabrication process is
employed to produce propagation delays
as short as IOns.
• I/O propagation delays (worst case)
• Functional superset of 16L8 and
most other 20-pin combinatorial
PAL devices
The 20-pin PLUS153 device has a programmable AND array and a program-
• Two programmable arrays
mable OR array. Unlike PAL® devices,
100% product term sharing is supported.
Any of the 32 logic product terms can be
connected to any or all of the 1OoutputOR
gates. Most PAL ICs are limited to 7 AND
terms per OR function; the PLUSI53-1 0
can support up to 32 input wide OR
functions.
The polarity of each output is userprogrammable as either active-High or
active-Low, thus allowing AND-OR or
AND-NOR logic implementation. This
feature adds an element of design flexibility, particularly when implementing complex decoding functions.
The PLUS 153-10 device is user-programmable using one of several commercially available, industry standard PLD
programmers.
N Package
- PLUS153-10 -10ns max.
vee
B.
B.
B7
B6
Bs
- Supports 32 input wide OR
functions
B4
B3
.8 inputs
B2
GND
.10 bi-directionall/O
N = Plastic
• 42 AND gates
A Package
- 32 logic product terms
12
- 10 direction control terms
1,
10 Vee Bg
• Programmable output polarity
- Active-High or Active-Low
• Security fuse
• 3-State outputs
• Power dissipation: 750mW (typ.)
A = Plastic Leaded Chip Carrier
• TTL Compatible
APPLICATIONS
• Random logic
• Code converters
• Fault detectors
• Function generators
• Address mapping
• Multiplexing
@PAL is a registered trademark of Monolithic Merrories, Inc .• a wholly owned subsidiary of Advanced Micro Devices Corporation.
PHILIPS
141
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Logic Array
(18x42x10)
PLUS153-10
LOGIC DIAGRAM
31 • • • • • _2423_ • • • • -1615 • • • • • • 8
NOTES:
1. All programmed 'AND' gate locations are pulled to lo,gie "1",
2. AU programmed 'OR' gate locaHons are pulled to logic "0",
3. ,,!.-: Programmable connection.
October 1989
142
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Logic Array
PLUS153-10
(18x42x10)
FUNCTIONAL DIAGRAM
P 1
o.
Po
5o--+----'----+--I
~'>_-----~-Ol!o
=
THERMAL RATINGS
ORDERING INFORMATION
DESCRIPTION
tpo (MAX)
ORDER CODE
TEMPERATURE
20-Pin Plastic DIP 300m ii-wide
IOns
PLUSI53-10N
Maximum junction
150°C
20-Pin Plastic Leaded Chip Carrier
10ns
PLUS153-10A
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
ABSOLUTE MAXIMUM RATINGS1
RATING
SYMBOL
PARAMETER
Min
Max
UNIT
+7
Voc
Vee
Supply voltage
Vln
Input voltage
+5.5
Voc
VOUT
Output voltage
+5.5
Voc
liN
Input currents
lOUT
Output currents
TA
Operating free-air temperature range
Tsm
Storage temperature range
-30
+30
rnA
+100
rnA
0
+75
°C
-<;5
+150
°C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied,
October 1989
143
The PLUS153 devices are also processed to
military requirements for operation over the
military temperature range. For specifications
and ordering information consult the Signetics
Military Data Book.
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Logic Array
PLUS153-10
(18 x 42 x 10)
DC ELECTRICAL CHARACTERISTICS o°C <
- +75°C, 4.75 -< Vee <
- TA <
- 5.25V
LIMITS
SYMBOL
Min
TEST CONDITIONS
PARAMETER
Typ'
Max
UNIT
0.8
V
Input voltage2
V IL
Low
Vee = Min
V IH
High
Vee = Max
V'C
Clamp
2.0
V
-{l.8
Vee = Min, liN =-12mA
-1.2
V
0.5
V
Output voltage
Vee = Min
Low4
HighS
VOL
VOH
IOL= 15mA
2.4
10H =-2mA
V
Input currenti'
Vee = Max
IlL
Low
VIN =0.45V
-100
pA
IIH
High
VIN = Vee
40
pA
VOUT= 5.5V
80
pA
VOUT = 0.45V
-140
Output current
Vee = Max
Hi-Z stateS
lo(oFF)
los
Short circuit3. 5. 6
VOUT=OV
Icc
Vee supply current7
Vee = Max
Input
VIN = 2.0V
VB = 2.0V
-15
150
-70
mA
200
mA
Capacitance
Vee =5V
CIN
CB
110
8
NOTES:
1. All typical values are at Vee = 5V, TA = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with inputs 10 -12 = OV, inputs 13 - 15 = 4.5V, inputs 17 = 4.5V and 16 = 10V. For outputs
same conditions except 17 = OV.
5. Same conditions as Note 4 except 17 = + 1OV.
6. Duration of short circuit should not exceed 1 second.
7. lee is measured with inputs 10 - 17 and So - B9 = OV.
8. Leakage values are a combination of input and output leakage.
9. III and IIH limits are for dedicated inputs only (10 -17)'
AC ELECTRICAL CHARACTERISTICS Ooc:s; TA:S; +75°C, 4.75V:S; Vee:S; 5.25V,
So - B4 and for outputs Bs - B9 apply the
Rl = 4700, R2 = lkO
LIMITS
TEST
SYMBOL
PARAMETER
pF
pF
15
FROM
TO
CONDITION
Typ
Max
UNIT
tpo
Propagation Delay2
Input +/-
Output +1-
CL = 30pF
8
10
ns
toE
Output Enable
Input +!-
Output-
CL = 30pF
8
10
ns
too
Output Disable 1
Input+!-
Output +
CL = 5pF
8
10
ns
NOTES:
1. Measured at VT = VOL + 0.5V.
2. Measured with all inputs and outputs switching simultaneously.
October 1989
144
Min
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Logic Array
(18x42x10)
VOLTAGE WAVEFORMS
PLUS153-10
TEST LOAD CIRCUIT
1. vcc
J:fi
.5V
0,--10
I
I
o-l-
R,
1
1
117
BvjrOUT
~BW
o--l.--
BZ
BX
GND
MEASUREMENTS:
All circuit delays are measured at the + 1.5V level
of Inputs and outputs, unless otherwise specilied.
Input Pulses
TIMING DEFINITIONS
SYMBOL
tpD
Propagation delay between
input and output.
too
Delay between input change
and when output is off (Hi-Z
or High).
tOE
Delay between input change
and when output reflects
specified output level.
October 1989
TIMING DIAGRAM
PARAMETER
145
I
I
l-L--
R2 -::
NCLUDESSCOPE
AND JIG
CAPACITANCE
J
CL
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Logic Array
(18x42x10)
PLUS153--10
OUTPUT POLARITY - (8)
LOGIC PROGRAMMING
PLUSI53-10 logic designs can be generated
using Signetics AMAZE PLD design software
or one of several other commercially available,
JEDEC standard PLD design software packages. Boolean equation entry is accepted.
.~.
PLUS153-10 logic designs can also be generated using the program table entry format detailed on the following pages. This program
table entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
users.
I
ACTIVE LEVEL
I
HIGH'
(NO~NVERTlNG)
I
I
CODE
H
L ACTIVE lEVEL I
I
I
I
(INV~~~NG)
CODE
I
J
I
To implement the desired logic functions, the
state of each logic variable from logic equations
(1,8,0, P, etc.) is assigned a symbol. Thesymbois for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
1
1
'
8
11,8
1
'
8
1
AND ARRAY - (I, 8)
~B
I,B
I,B
I, 1J
I, 1J
P,D
~STATE
~CTlVE,,2
I
P,D
CODE
0
I
I
STATE
I,B
I
CODE
H
ACTIVE'
I
STATE
I
I,ll'
I
CODE
l
I
.
I
STATE
DON'T CARE
P,D
I
CODE
-
I
I
I
CODE
A
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at "H" polarity.
~.
I
I
I
I
Pn STATUS
INACTIVE
I
I
CODE
•
2. All P n terms are disabled.
3. All Pn terms are active on all outputs.
I
I
NOTES:
I, This is the initial unprogrammed state of all links.
2, Any gate Pn will be unconditionally inhibited if both the true and complement of an input (either
I or 8) are left intact.
October 1989
I, 1J
VIRGIN STATE
+=>-.
PnSTATUS
~~I'B
P,D
OR ARRAY - (8)
I
I
I,B
I, 1J
146
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Logic Array
PLUS153-10
(18x42x10)
PLA PROGRAM TABLE
POLARITY
I
I I
;'
~,
i"J ~I~:~~7~6~5~4~3~2~1+-0i-'+-.T-7t-6t-5t-4~3-r_2r'~0~
T
~
Cl f!.
w a:
~ ~
g
~
d1-------,5,---f-+-+---+--f,-+-+---I-+-+-+-,
~:~~~~~-1-1-1~-+~-+-+-+~-r-r~~
--I--I-+-+-,--+--1-+-1
a:
j ~6~~~~-1!~~-4-t-+-T-!t-t-t-r-!r-~~
w
B(O)
'87654(3210
!
i
i
I
,I
!il
~ ~ ~g 12 +~~~-;''-!-4-4-t-+-T'-+-+-+-i-'+++~
[l
~
g:
I
~7~~~~-1:H-1-1~-+--+-+-+-+-r-:t-t--t-I
:::E a:..J
•
i
w ~ ~.~t--~~-1iH-1-1~-+-+i+-+-+-f-it-t--t-I
a:
I- ~'-0+-+--+-+--1i'-!-1'-!~-+--l-I+-+-+-J-,t-t--t-I
w ::::l :::E 1--:::-~~~-l~-4-4-t-+-+-+-+-+-+-r-r-r~
:::E Z
1--:'-:-'
~
I
OR
AND
~'-:-3+-+--+-+--t--+-+-+--t-+--t-+-+-+-r-t-t-t-I
!
i
i
14
15
16
J
l '
I
17
1.
I
I
19
20
21
22
23
24
25
26
27
I
I
!
I
I
!!
29
I
I
!
!
,
i
i
,
J
i
I
!
:
!
I
i
i
i
I
I
i
!
!
!
!
i
i
I
i i i
I
I
I
I
I
I
2.
i
,
!
30
31
i
I
!
I
D8
DB
07
05
!
D4
_1 _ _ _ _
.1 •
.J _ _ _ _
03
02
01
c'
~:
o
::I:
-I
:
:
i
i
I
i
i
I
I
DO
PIN
I
!
I
D6
8
7
6
5
I
4
3
2
1
:
i
i
I
I
19 18 17 16 15 14 13 12 11
I
w
a:
...~
~:~ ~
October 1989
I
!
147
9
19 18 17 16 15 14 13 12 11
9
PlS173
Signetics
Field-Programmable Logic
Array (22 X 42 X 10)
Signetics Programmable Logic
Product Specification
Application Specific Products
• Series 24
DESCRIPTION
FEATURES
The PLS173 is a two-level logic element
consisting of 42 AND gates and 10 OR
gates with fusible link connections for
programming I/O polarity and direction.
•
•
•
•
•
•
•
All AND gates are linked to 12 inputs (I)
and 10 bidirectional I/O lines (8). These
yield variable I/O gate configurations via
10 direction control gates (D), ranging
from 22 inputs to 10 outputs.
On chip T /C buffers cQuQle either True
(I, 8) or Complement (I, 8) input polarities to all AND gates, whose outputs can
be optionally linked to all OR gates.
Their output polarity, in turn, is individually programmable through a set of EX-OR
gates for implementing AND/OR or
AND/NOR logic functions.
The PLS173 is field programmable, enabling the user to quickly generate custom patterns using standard programming equipment.
Order codes for this device are contained in the pages following.
•
•
•
•
•
PIN CONFIGURATIONS
Field-Programmable (Ni-Cr links)
12 inputs
42 AND gates
10 OR gates
10 bidirectional 1/0 lines
Active-High or -Low outputs
42 product terms:
- 32 logiC terms
- 10 control terms
1/0 propagation delay: 30ns (max.)
Input loading: -100iJA (max.)
Power dissipation: 750mW (typ.)
3-State outputs
TTL compatible
APPLICATIONS
•
•
•
•
•
•
N Package
N = Plastic
Random logic
Code converters
Fault detectors
Function generators
Address mapping
Multiplexing
A Package
FUNCTIONAL DIAGRAM
POI
Po
DO
'0
~--------------+---------+---+H".~
'"
NOTE:
A = Plastic Leaded Chip Carrier
LOGIC FUNCTION
·o------t--------------r---------+------~~
TYPICAL PRODUCT TERM:
Pn=A-ii-C'D- ...
TYPICAL LOGIC FUNCTION:
AT OUTPUT POLARITY == H
Z = PO + P1 + P2 ...
•• ------+-------------~---------+------~N
AT OUTPUT POLARITY == L
Z=PO+P1 +P2+ .. .
Z=Pi)-p,-P2· .. .
>4------f>--~--~oD·.
so------t------L-------+~
May 11, 1988
NOTES:
1. For each of the 10 outputs, either function Z
(Active·High) or Z (Active-LOW) is available, but not
both. The desired output polarity is programmed
via the EX-OR gates.
2. Z, A, S, C, etc. are user defined connections to
fixed inputs (I), and bidirectional pins (8).
>f:>-------------~_o·o
148
853-0324 93253
Product Specification
Signetics Application Specific Products. Series 24
PLS173
Field-Programmable Logic Array (22 X 42 X 10)
FPLA LOGIC DIAGRAM
"
"
'.,
'"
B,
B.
B,
B,
B,
B.
B,
B,
B,
B,
31······2423·.··.·1615······87······0
NOTES,
1. AU programmed "AND" gate locations are pulled to logic "1".
2. All programmed "OR" gate locations are pulled to logic "0".
3.
Programmable connection
May 11, 1988
149
Product Specification
Signetics Application Specific Products. Series 24
PLS173
Field-Programmable Logic Array (22 x 42 x 10)
THERMAL RATINGS
ORDERING INFORMATION
TEMPERATURE
ORDER CODE
DESCRIPTION
24-Pin Plastic DIP
300mil-wide
PLS173N
28-Pin Plastic Leaded
Chip Carrier
PLS173A
Maximum junction
150°C
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
ABSOLUTE MAXIMUM RATINGS1
RATING
SYMBOL
PARAMETER
Min
Max
UNIT
+7
Vrx;
Vee
Supply voltage
Vln
Input voltage
+5.5
Vrx;
V OUT
Output voltage
+5.5
Vrx;
liN
Input currents
+30
mA
louT
Output currents
+100
mA
TA
Operating free-air temperature range
a
+75
TSTG
Storage temperature range
--£5
+150
°c
°c
--30
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.
DC ELECTRICAL CHARACTERISTICS aOc <
- TA <
- +75°C
475 <
- 5 25V
- Vee <
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Vee = Min
Vee = Max
Vee = Min. liN =-12mA
2.0
Typl
Max
UNIT
O.S
V
V
V
Input vOltage2
Vil
VIH
Vc
Low
High
Cl amp 2.3
-D.S
-1.2
Output voltage
VOL
VOH
Low. 4
High 2 . 5
Vee = Min
10l = 15mA
10H =-2mA
0.5
V
V
2.4
Input current 'O
Vee = Max
III
Low
VIN = 0.45V
-100
IIH
High
VIN = Vee
40
!JA
!JA
VOUT = 5.5V
SO
!JA
VOUT = 0.45V
-140
Output current
Vee = Max
10(oFF)
Hi-Z state g
los
Short circuit 3. 5. 6
VOUT = OV
Icc
Vee supply current?
Vee = Max
liN
Input
V IN = 2.0V
S
pF
Ca
1/0
Va = 2.0V
15
pF
-15
150
-70
mA
170
mA
Capacitance
Vee =5V
Notes on following page.
May 11.1988
150
Product Specification
Signetics Application Specific Products. Series 24
PLS173
Field-Programmable Logic Array (22 x 42 x 10)
AC ELECTRICAL CHARACTERISTICS oOc :S;TA:S; +7SoC, 4.7S:S;V cc :S;S.2SV, R, = 4700, R2 = lkO
,
--,._--
I
LIMITS
TEST
FROM
TO
CONDITION
Typ
Max
UNIT
!Po
Propagation delay
Input±
Output±
CL = 30pF
20
30
ns
toE
Output enable
Input±
Output-
C L = 30pF
20
30
ns
Output disables
Input±
Output +
= SpF
20
30
ns
SYMBOL
100
PARAMETER
CL
NOTES:
1. All typical values are at Vee = SV, T A = +2SoC.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with inputs VIL applied to 111 , Pins I-S = OV, Pins 6-10 = 4.SV, Pin 11 = OV and Pin 13
S. Same conditions as Note 4 except Pin 11 = + 10V.
6. Duration of short circuit should not exceed 1 second.
7. Icc is measured with 10 and I, = OV, and 12 -111 and Be -13g = 4.SV Part in Virgin State.
S. Measured at VT = VOL + O.SV
9. Leakage values are a combination of input and output leakage.
10. IlL and IIH limits are for dedicated inputs only (Io -I,,).
VOLTAGE WAVEFORM
Min
I
= 10V
TEST LOAD CIRCUIT
1 Vcc
+5V
<>--rI
I
o--L--
<>--r-
o--L-
10
I
I
I
111
OUT
Bx
GND
~
Input Pulses
TIMING DEFINITIONS
SYMBOL
!Po
Propagation delay between
input and output.
100
Delay between input change
and when output is off (Hi-Z
or High).
toe
Delay between input change
and when output reflects
specified output level.
May 11,1988
TIMING DIAGRAM
PARAMETER
lSI
BY~
I
I
BZ~
BW
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of irputs and outputs. unless Dlherwise specified.
J:D"~AND JIG
R,
R2=
CAPACITANCE
J
CL
Product Specification
Signetics Application Specific Products. Series 24
PLS173
Field-Programmable Logic Array (22 x 42 x 10)
LOGIC PROGRAMMING
OUTPUT POLARITY - (8)
PLS173 logic designs can be generated using
Signetics AMAZE PLD design software or one
of several other commercially available,
JEDEC standard PLD design software packages. Boolean andlor state equation entry is
accepted.
.~.
PLS173 logic designs can also be generated
using the program table entry format detailed
on the following pages. This program table
entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
I
l
ACTIVE lEVEL
HIGHl
(NON-lNVERTlNG)
I
I
CODE
I
H
I
ACTIVE lEVEL
lOW
(INVERTING)
I
I
users.
To implement the desired logic functions, the
state of each logic variable from logic equations
(I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
1
1
1
11,8
1
'
8
1
1 1,8
AND ARRAY - (I, 8)
I,B
I,B
I, B
'9
r,B
P,D
i
I
STATE
INAcnVE 1,2
I
I
I, B
r,B
r,B
P,D
CODE
a
I
I
I
STATE
I
CODE
H
P,D
I I
STATE
I,B
I
OR ARRAY - (8)
I
PnSTATUS
ACTIVE
l
P,D
I I
STATE
DON'T CARE
I~
J
I
CODE
A
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at "H" polarity.
-fu-.
I
I
I
I
I
I
Pn STATUS
INACTIVE
CODE
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.
I
I
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused
(inactive) AND gates Pn, On.
2. Any gate Pn, Dn will be unconditionally inhibited if both the True and Complement of any input
(I, B) are left intact.
May 11,1988
CODE
VIRGIN STATE
-+D--.
I
'8
r,B
152
Signetics Application Specific Products • Series 24
Product Specification
Field-Programmable Logic Array (22 X 42 X 10)
PLS173
FPLA PROGRAM TABLE
II I I I I I I I
...,
I
~
~ ~---------------------r---------~I-l-------i
: ~l~l~~~'~'~'~'~'~'~l,~,~lrO~'~'~I,~,~,~,~,~,~,rO~
;
!
1
J
:
,R
• '1
1
•
I
I
4
:
!
!
w
a:
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10
...
11
:
II
.:
"
•
til
"
II
.
....
.
i
II
II
May 11, 1988
:
:
:
:
:
:
:
:
:
.
.
.:
:
:
:
:
:
:
:
:
.:
:
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153
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2
1
It
Signetics
Document No. 853-1298
ECN No.
97080
Date of Issue July 12, 1989
Status
Product Specification
PLUS1738/D
Programmable Logic Arrays
(22 x 42 x 10)
Programmable Logic Devices
PIN CONFIGURATIONS
DESCRIPTION
FEATURES
The PLUS173 PLDs are high speed, combinatorial Programmable Logic Arrays.
The Signetics state-of-the-art Oxide Isolated Bipolar fabrication process is
employed to produce propagation delays
as short as 12ns.
- 1/0 propagation delays (worst case)
The 24-pin PLUS 173 devices have a programmable AND array and a programmable OR array. Unlike PAL® devices,
100% product term sharing is supported.
Any of the 32 logic product terms can be
connected to any or all of the 10 output OR
gates. Most PAL ICs are limited to 7 AND
terms per OR function; the PLUS173 devices can support up to 32 input wide OR
functions.
The polarity of each output is userprogrammable as either active-High or
active-Low, thus allowing AND-OR or
AND-NOR logic implementation. This
feature adds an element of design flexibility, particularly when implementing complex decoding functions.
The PLUS173devices are user-programmable using one 01 several commercially
available, industry standard PLD programmers.
N Package
- PLUS173B -15ns max.
- PLUS173D - 12ns max.
- Functional superset of 20L10 and
most other 24-pin combinatorial
PAL devices
- Two programmable arrays
- Supports 32 input wide OR functions
-12 inputs
.10 bi-direclionalllO
• 42 AND gates
- 32 logic product terms
- 10 direction control terms
• Programmable output polarity
- Active-High or Active-Low
N = Plastic
A Package
13
12
11
10 vee
B9 Ba
• Security fuse
• 3-State outputs
• Power dissipation: 750mW (typ.)
• TTL Compatible
APPLICATIONS
• Random logic
• Code converters
• Fault detectors
A .. Plastic leaded Chip Carrier
• Function generators
• Address mapping
- Multiplexing
@PALisaregisteredtrademarkof Monolithic Memories. Inc., a wholly owried subsidiary of Advanced Micro Devices Corporation.
PHILIPS
154
Product Specification
Signetics Programmable Logic Devices
Programmable Logic Arrays
(22 x 42 x 10)
PLUS173B/O
LOGIC DIAGRAM
'.
'"
B.
31 • • • • • • 2423 • • • • • • 1615 • • • • • • 8
NOTES,
1. All programmed 'AND' gate locations are pulled to
log~"l ".
2. All programmed 'OR' gate locations are pulled to logic "0".
3.
Programmable connection.
July 12, 1989
155
Product Specification
Signetics Programmable Logic Devices
Programmable Logic Arrays
(22 x 42 x 10)
PLUS1738/0
FUNCTIONAL DIAGRAM
P,
D9
Po
10
@
>-----------~_O~
ORDERING INFORMATION
DESCRIPTION
THERMAL RATINGS
TEMPERATURE
tpD(MAX)
ORDER CODE
24-Pin Plastic DIP 300m ii-wide
15ns
PLUS173BN
Maximum junction
150°C
24-Pin Plastic DIP 300m ii-wide
12ns
PLUS173DN
Maximum ambient
75°C
26-Pin Plastic Leaded Chip Carrier
15ns
PLUS173BA
75°C
26-Pin Plastic Leaded Chip Carrier
12ns
PLUS173DA
Allowable thermal rise
ambient to junction
ABSOLUTE MAXIMUM RATINGSl
RATING
SYMBOL
PARAMETER
Max
UNIT
+7
Vrx:,
Input voltage
+5.5
Vrx:,
Your
Output voltage
+5.5
Vrx:,
liN
Input currents
+30
mA
lOUT
Output currents
+100
mA
TA
Operating free-ilir temperature range
0
+75
°C
TSTG
Storage temperature range
-65
+150
°C
Vee
Supply voltage
Vln
Min
-30
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
July 12, 1989
156
Product Specification
Signetics Programmable Logic Devices
Programmable Logic Arrays
(22 x 42 x 10)
PLUS1738ID
DC ELECTRICAL CHARACTERISTICS o°c
SYMBOL
I
PARAMETER
~ TA ~ +75 0 C, 4.75 ~ Vee ~ 5.25V
""
'-
I
I
TEST CONDITIONS
Typ1.
Min
J
Max
UNIT
0.8
V
-1.2
V
0.5
V
Input voltage'
V,L
Low
Vee
~
Min
V,H
High
Vee
~
Max
V'C
Clamp
~
Vee
Min, liN
~
V
2.0
--D.8
-12mA
Output voltage'
~
Vee
Low'
High 5
VOL
VOH
Min
10L
~
15mA
10H
~
-2mA
2,4
V
Input current"
Vee ~ Max
III
Low
I'H
High
V,N
~
-100
~
40
~
5.5V
80
~
0,45V
-140
0,45V
V,N ~ Vee
Output current
Vee ~ Max
Hi-Z state B
10(OFF)
~
VOUT
~
VOUT
los
Short circuit 3 , 5, 6
VOUT
lee
Vee supply current7
Vee
Input
V ,N
~
2.0V
8
pF
I/O
VB
~
2.0V
15
pF
~
~
OV
-15
150
Max
-70
rnA
200
rnA
Capacitance
Vee ~ 5V
liN
Cs
NOTES:
1. All typical values are at Vee ~ 5V, TA ~ +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with inputs 10 -14 ~ OV, inputs 15 -19 ~ 4.5V, 1" ~ 4.5V and 110 ~ lOV For outputs
conditions except 1'1 ~ OV.
5. Same conditions as Note 4 except input 1'1 ~ + 10V
6. Duration of short circuit should not exceed 1 second.
7. lee is measured with inputs 10 -111 and Bo - B9 ~ OV Part in Virgin State.
8. Leakage values are a combination of input and output leakage.
9. I,L and I'H limits are for dedicated inputs only (10 - 111)'
AC ELECTRICAL CHARACTERISTICS
So -
B4 and for outputs B5 - B9 apply the same
O°C ~ TA~ +75°C, 4.75~ Vee~ 5.25V, Rl ~ 470Q, R2 ~ 1kQ
LIMITS
SYMBOL
PARAMETER
FROM
TEST
TO
CONDITION
PLUS173D
PLUS173B
Min
Typ
Max
Min
UNIT
Typ
Max
tpD
Propagation Delay2
Input +/-
Output +/-
30pF
11
15
10
12
ns
teE
Output Enable
Input +/-
Output-
CL ~ 30pF
11
15
10
12
ns
teD
Output Disable 1
Input +1-
Output +
CL
11
15
10
12
ns
CL
~
~
5pF
NOTES:
1. Measured at VT ~ VOL + O.5V
2. Measured with all inputs and outputs switching simultaneously.
July 12, 1989
157
Signetics Programmable Logic Devices
Product Specification
Programmable Logic Arrays
(22 x 42 x 10)
VOLTAGE WAVEFORM
PLUS1738/D
TEST LOAD CIRCUIT
1
Vcc
.5V
<>--rI
I
o--l---.-.
~
o--l--
10
I
I
I
I"
BYT
OUT
BZ~
BW
BX
GNO
~
MEASUREMENTS,
Input Pulses
TIMING DEFINITIONS
SYMBOL
Propagation delay between
input and output.
too
Delay between input change
and when output is off (Hi-Z
or High).
toE
Delay between input change
and when output reflects
specified output level.
July 12, 1989
TIMING DIAGRAM
PARAMETER
tpo
I
I
All circuit delays are measured at the + 1.5V level
of inputs and outputs, unless otherwise specified.
158
J:n"~'-'
R1
R2
AND JIG
CAPACITANCE
r
Cl
Product Specification
Signetics Programmable Logic Devices
Programmable Logic Arrays
(22 x 42 x 10)
PLUS1738/0
OUTPUT POLARITY - (6)
LOGIC PROGRAMMING
PLUS173 logic designs can be generated
using Signetics AMAZE PLD design software
or one of several other commercially available,
JEDEC standard PLD design software packages. Boolean equation entry is accepted.
.~.
.~.
PLUS173 logic designs can also be generated
using the program table entry format detailed
on the following pages. This program table
entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
users.
To implement the desired logic functions, the
state of each logic variable from logic equations
(1,8,0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
1
1
'
9
11,9
1
'9
1
AND ARRAY - (I, 6)
1,8
I,B
I,B
I,B
~B
P.D
I
STATE
INAcnvE',2
I
I,B
P,D
COOE
I
I
0
STATE
I, B
I
STATE
I
I
I,B
I
OR ARRAY - (6)
PnSTATUS
ACTIVE
CODE
L
I
P,D
~ATE
~CARE
I
CODE
- I
j'-D-.
CODE
I
A
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at "H" polarity.
I
I
I
I
I
Pn STATUS
INAcnVE
CODE
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.
I
I
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused
(inactive) AND gates Pn, On.
2. Any gate P n, On will be unconditionally inhibited if both the true and complement of any input
(I, 8) are left intact.
July 12, 1989
I,B
VIRGIN STATE
-fo-.
I
I
~11'B
P,D
CODE
H
I,B
159
Signetics Programmable Logic Devices
Product Specilication
Programmable Logic Arrays
(22 x 42 x 10)
PLUS1738/0
PLA PROGRAM TABLE
POLARITY
I I
M
I
8
7
6
5
B(O)
4
•
2
1
0
9
8i 7
i
~
w
:::Ii
10
~
en
a:
11
0(
:::Ii
8a:
:::l
o
n.
1
0
i
i
i
I
j!
a:
2
6
W
..J
z
4i'
~
ID
0(
5
i
I
I
-'I
5
6
H-!H-t--H!t--I"-t--t-t
i
w
J
9
!
~ •
J •
w
:::Ii
6543210
I I
OR
B(I)
11109817
o
a:
I I
AND
T
E
R
j
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I
J.
I
I
i
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!
12
~
,."
~
15
i
16
I
17
I
18
!
!
20
i
I
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22
2.
J
:
19
21
!
I
:
I
I
I
I
I
I
J
:
i
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I
I
!
~
rT~~-r~-i~~H
rT~l-r~-J~~H
~-rIT-~-r1T-r+~
~-I!r+~+;!-r~H
r+;!-r~-r+!~H
:
24
i
25
26
27
!
!
28
29
, ~ , ':!:
i
:¢-rw-:~:i-'
I
~'~~'i'
~
I
()
~ ~
10 I
:r-r;-:
: L-L-: :,
I
,
,0
I
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a9
:!
:,
:J;:
_, _____ ,_J ____
:
0'
~:
!i111III~I
D6
D57
0%'-1
I
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D2
01
PiN
I
13 11 10
9
I
8
7
6
5
4
3
2
1
I
,
July 12, 1989
I
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04
03
00
~
rT r
i
160
23 22 21 20 19 18 17 16 15 14
23 22 21
20 19 18 17 16 15 14
Signetics
PLU8173-10
Document No.
ECN No.
Date of Issue October 1989
Status
Preliminary Specification
Programmable Logic Array
(22 x 42 x 10)
Programmable Logic Devices
DESCRIPTION
The PLUS173-10 PLD is a high speed,
combinatorial Programmable Log ic Array.
The Signetics state----~~~~-+4---~~~,ollit
lis
a..
83
NOTES:
1. AM programmed 'AND' gatoloca1lons are pulled 10 logic "I".
2. All programmed 'OR' galO locations are pulled 10 logic "0".
3•. {II Programmable connection.
October 1989
162
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Logic Array
(22 x 42 x 10)
PLUS173-10
FUNCTIONAL DIAGRAM
Do
50--+----'----+-1
De
> - - - - - -......-<>110
=
ORDERING INFORMATION
DESCRIPTION
THERMAL RATINGS
TEMPERATURE
tpD(MAX)
ORDER CODE
24-Pin Plastic DIP 300mil-wide
10ns
PLUS173-10N
Maximum junction
150°C
28-Pin Plastic Leaded Chip Carrier
10ns
PLUS173-10A
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
ABSOLUTE MAXIMUM RATINGS1
RATING
SYMBOL
PARAMETER
Vee
Vh
Voor
Output voltage
lIN
Input currents
lOUT
Output currents
Til.
Operating free-air temperature range
Min
Supply voltage
Input voltage
Max
UNIT
+7
+5.5
Voc.
Voc.
Voc.
+5.5
-30
0
+30
mA
+100
mA
+75
·C
Storage temperature range
·C
~5
+150
TSTG
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other oondition above those indicated in the operational and programming specification of the device is not implied.
October 1989
163
Signetics Programmable Logic Devices
Preliminary Specification
Programmable Logic Array
PLUS173-10
(22 x 42 x 10)
DC ELECTRICAL CHARACTERISTICS o°c ~ TA ~ +75°C, 4. 75 ~ Vee ~ 5.25V
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typl
Max
UNIT
0.8
V
Input voltage2
V il
Low
Vee = Min
V IH
High
Vee = Max
Vc
Clamp
2.0
V
--{).8
Vee = Min, liN = -12mA
-1.2
V
Output voltage'
Vee = Min
Low"
HighS
VOL
VOH
0.5
10l = 15mA
2.4
10H =-2mA
V
V
Input current"
Vee = Max
III
Low
VIN = 0.45V
-100
IIH
High
VIN = Vee
40
IJA
IJA
VOUT = 5.5V
80
IJA
VOUT = 0.45V
-140
Output current
Vee = Max
Hi-Z stateS
10(OFF)
los
Short circuit 3, 5, 6
VOUT = OV
lee
Vee supply current?
Vee = Max
Input
I/O
VIN = 2.0V
VB = 2.0V
-15
150
-70
mA
200
mA
Capacitance
Vec = 5V
lIN
CB
8
15
NOTES:
1. All typical values are at Vec = 5V, TA = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with inputs 10 -14 = OV, inputs 15 -19 = 4.5V, I" = 4.5V and 110 = 10V. For outputs
conditions except I" = Ov.
5. Same conditions as Note 4 except input 1" = + 10V.
6. Duration of short circuit should not exceed 1 second.
7. Icc is measured with inputs 10 -111 and So - B9 = Ov. Part in Virgin State.
8. Leakage values are a combination of input and output leakage.
9. III and IIH limits are for dedicated inputs only (10 -I,,).
AC ELECTRICAL CHARACTERISTICS o°c ~ TA ~ +75°C, 4.75 ~ Vce ~ 5.25V,
So -
B4 and for outputs B5 - Bg apply the same
R, = 470Q, R2 = lkQ
TEST
SYMBOL
PARAMETER
pF
pF
FROM
TO
CONDITION
LIMITS
Typ
Max
UNIT
!Po
Propagation Delay2
Input +/-
Output+/-
Cl = 30pF
8
10
ns
toE
Output Enable
Input +/-
Output-
Cl = 30pF
8
10
ns
100
Output Disable 1
Input +/-
Output +
Cl = 5pF
8
10
ns
NOTES:
1. Measured at V T = VOL + 0.5V.
2. Measured with all inputs and outputs switching simultaneously.
October 1989
164
Min
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Logic Array
(22 x 42 x 10)
VOLTAGE WAVEFORM
PLUS173-10
TEST LOAD CIRCUIT
~ vcc
J:D
.5V
0--,----- 10
I
I
I
:
o-l----
I"
Rl
ByT
I
I
DUT
BZ
GND
MEASUREMENTS:
All circuit delays are measured at the + 1.SV level
of inputs and outputs, unless otherwise specified.
Input Pulses
TIMING DEFINITIONS
SYMBOL
tpD
Propagation delay between
input and output.
taD
Delay between input change
and when output is off (Hi-Z
or High).
taE
Delay between input change
and when output reflects
specified output level.
October 1989
TIMING DIAGRAM
PARAMETER
165
f-L--
R2
=
NCLUDES SCOPE
AND JIG
CAPACITANCE
I
CL
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Logic Array
(22x42x10)
PLUS173-10
OUTPUT POLARITY - (B)
LOGIC PROGRAMMING
PLUS173-10 logic designs can be generated
using Signetics AMAZE PLD design software
or one of several other commercially available.
JEDEC standard PLD design software packages. Boolean equation entry is accepted.
.~.
,~.
PLUS173-10 logic designs can also be generated using the program table entry format detailed on the following pages. This program
table entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
AC11VE LEVEL
I ..
GH'
NON-INVER11NG)
CODE
I
H
ACT)VE LEVEL
I
I
LOW
()NVER11NG)
I
CODE
I
I
users.
To implement the desired logic functions. the
state of each logic variable from logic equations
(I. B. O. p. etc.) is assigned a symbol. Thesymbois for TRUE. COMPLEMENT. INACTIVE.
PRESET. etc.• are defined below.
AND ARRAY - (I, B)
I,B
1
~B
~B
r,B
I,B
r,B
11.B
P.D
I
I
STATE
INAC11VE',2
I
I
1B
r,B
•
1
P,D
CODE
0
I
I
I,B
1B
1
P.D
STATE
STATE
I.B
r.B
OR ARRAY - (B)
r.B
•
P.D
STATE
DON'TCARE
VIRGIN STATE
A factory shipped virgin device contains all
fusible links intact. such that:
1. All outputs are at "H" polarity.
2. All Pn terms are disabled.
3. All Pn terms are active on all outputs.
I
I
Pn STATUS
ACTIVE
I
I
CODE
A
I
I
I
I
I
I
Pn STATUS
INAC11VE
CODE
•
I
I
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused
(inactive) AND gates Pn. On.
2. Any gate Pn. On will be unconditionally inhibited if both the true and complement of any input
(I. B) are left intact.
October 1989
166
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Logic Array
PLUS173-10
(22 x 42 x 10)
PLA PROGRAM TABLE
POLARITY
I I I
E
I
6543210
I
11(1)
8(0)
.876543210
.876543210
R
M11l0t.7
I I I
OR
AND
T
w
~
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d
I
j
w
W
....I
:E
I
!
!
;
II:
aI
~
;!
II:
W
:E
10
II:
11
II:
13
'"
8
:E
~o
II.
!
12
!
!
14
15
16
17
!
18
19
20
21
i
22
I
23
24
25
26
27
29
30
D9
: I
:-:;r;I_
rw
w >
0:, ()~ {;l!
0::'
I
~
,
:~c.=.
:
_I _ _ _ _ _
DB
,
,
D3
::
D2
'_J ____
01
'0'
:u:
!:
9
J
I
tlID]....
5 ~
I
I
I
!
D5
D4
DO
PIN
,
Q'
~:
13 11 10
it
8
7
6
5
4
3
2
1
-'
o :c
..J
I
,
October 1989
167
23 22 21 20 19 18 17 16 15 14
23 22 21 2.0 11 18 17 16 15 14
PLHS473
Signetics
Field-Programmable logic
Array (20 X 24 X 11)
Signetics Programmable logic
Product Specification
Application Specific Products
• Series 24
DESCRIPTION
I/O configuration of all 9 bidirectional
pins.
The PLHS473 is a two level logic device
consisting of 24 AND gates and 22 OR
gates with fusible link connections for
programming I/O polarity and direction.
The Signetics state of the art OxideIsolated Bipolar process is used to produce performance not yet achieved in
devices of this complexity.
PIN CONFIGURATIONS
N Package
The PLHS473 contains two new features of significance. A code verification
lock has been incorporated to improve
user security. The addition of three test
columns and one test row enables the
user to test the device in an unprogrammed state.
All AND gates are linked to 11 input pins,
9 bidirectional I/O pins, and 2 dedicated
output pins. The bidirectional pins are
controlled via the OR array. Using these
features, the PLHS473 can be configured with up to 20 inputs and as many as
11 outputs.
B,
B5
The PLHS473 is field programmable using Vertical Avalanche Migration Programmed (VAMPTM) fuses to program
the cells. This enables the generation of
custom logic patterns using standard
programming equipment.
0.
B,
B,
B,
Order codes are listed in the Ordering
Information Table.
The AND array input buffers provide
both the True and Complement of the
inputs (Ix) and the bidirectional signals
(Bx) as programmable connections to
the AND gates. All 24 AND gates can
then be optionally linked to all 22 OR
gates (a feature known as Product Term
sharing not found in PAL @ device architectures or most macrocell architectures). The OR array drives 11 output
buffers which can be programmed as
active-High for AND-OR functions or
active-Low for AND-NOR functions. In
addition, the I/O configuration of each
bidirectional pin is individually controlled
by a sum-of-products (AND-OR) function
which may also contain any of the 24
AND gate outputs. This allows dynamic
B,
FEATURES
• Field-Programmable
• 11 dedicated inputs
• 2 dedicated outputs
• 9 bidirectional I/O lines
• 24 product terms
.22 OR gates
• I/O direction decoded in OR array
• Output Enable decoded in OR
array
• Security fuse
• I/O propagation delay: 22ns (max.)
A Package
FUNCTIONAL DIAGRAM
HIe
o~
23
~
'-~
li
.J
I----
~
;::
fJLj;,)----- ~ h
fJu
..fS- ,.1.-
011
06
85
86
Hie
•
•
•
•
•
------------
:g--~7
84
.,
)
i
Input loading: -100}1A (max.)
Power dissipation: 700mW (typ.)
Security fuse
Testable in unprogrammed state
Programmable as 3-State or
Open-Collector outputs
• TTL compatible
• Programmable output polarity
APPLICATIONS
·0
~
-
•
•
•
•
•
•
Random logic
Code converters
Fault detectors
Function generators
Address mapping
Multiplexing
PAL is a trademark of Monolithic Memories, Inc., a wholly owned subsidary of Advanced Micro Devices, Inc.
May 11, 1988
168
853-0019 93254
Product Specification
Signetics Application Specific Products - Series 24
Field-Programmable Logic Array (20
x
24 X 11)
PLHS473
FPLA LOGIC DIAGRAM
B,
B,
B.
B5
B,
B3
B,
B,
,.
,.
13 Bo
NOTES:
1. All unprogrammed or virgin "AND" gate locations are pulled to logic "1".
2. All unprogrammed or virgin "OR" gate locations are pulled to logic "0".
3.
Programmable connection.
May 11, 1988
169
0.
OA
Signetics Application Specific Products - Series 24
Product Specification
Field-Programmable Logic Array (20 X 24 X 11)
ORDERING INFORMATION
DESCRIPTION
PLHS473
THERMAL RATINGS
ORDER CODE
24-pin Plastic DIP
300mil-wide
PLHS473N
28-pin Plastic Leaded
Chip Carrier
PLHS473A
TEMPERATURE
ABSOLUTE MAXIMUM RATINGS'
SYMBOL
150°C
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
LOGIC FUNCTION
PARAMETER
RATINGS
UNIT
+7
Voe
+5.5
Voc
Vee
Supply voltage
VIN
Input voltage
VOUT
Output voltage
+5.5
Voe
liN
Input currents
-30 to +30
mA
+100
mA
lOUT
Output currents
TA
Operating free-air temperature range
TSTG
Storage temperature range
o to
+ 75
°C
-65 to + 150
°C
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress
rating only. Functional operation at these or any other conditions above those indicated in the operational
and programming specification of the device is not implied.
DC ELECTRICAL CHARACTERISTICS
Maximum junction
TYPICAL PRODUCT TERM:
Pn=A'B'C'D' ...
TYPICAL LOGIC FUNCTION:
AT OUTPUT POLARITY = H
Z::;: PO + P1 + P2 . . .
AT OUTPUT POLARITY::;: L
Z PO + Pl + P2 + ...
Z=PQ·Pi·j)2· .
NOTES:
1. For each of the 11 outputs, either function Z
(Active-High) or Z (Active-Low) is available, but not
both. The desired output polarity is programmed
via the Ex-OR gates.
2. Z, A, B, C, etc. are user defined connections to
fixed inputs (I), fixed output pins (0) and
bidirectional pins (B).
0°C--'--
110
<>-;I
·w
o-!--
Bx
-¥,~.AND JIG
CAPACITANCE
By - - . - - -
OUT
I
I
I
I
Bz - - ' - - -
GND
Rl
Oxr--
R2
I
Cl
":"":"
-:!:-
MEASUREMENTS:
AU circuit delays are measured at the + 1.5V level
of inputs and outputs, unless othelWise specified.
TC02001S
Input Pulses
TIMING DEFINITIONS
SYMBOL
TIMING DIAGRAM
PARAMETER
I,B
tpD
Propagation delay between
input and output.
tOD
Delay between input change
and when output is off (Hi-Z
or High).
tOE
Delay between input change
and when output reflects
specified output level.
May 11, 1988
~...,,_v_____j)l(I.5V
~.3V
I.SV
OV
B
171
Product Specification
Signetics Application Specific Products - Series 24
PLHS473
Field-Programmable Logic Array (20 X 24 X 11)
OUTPUT POLARITY - (0, 8)
LOGIC PROGRAMMING
PLHS473 logic designs can be generated
using Signetics' AMAZE PLD design software
or one of several other commercially available, JEDEC standard PLD design software
packages. Boolean and/or state equation
entry is accepted.
S~D--x~ .
O,B
I
I
PLHS473 logic designs can also be generated using the program table entry format
detailed on the following pages. This program
table entry format is supported by the
Signetics' AMAZE PLD design software (PTP
module). AMAZE is available free of charge
to qualified users.
ACTIVE LEVEL
HIGH
(NON-INVERTING)
I
I
CODE
H
I
I
I
I
ACTIVE LEVEL
LOW'
(INVERTING)
I
I
CODE
L
1
I
To implement the desired logic functions, the
state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol.
The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.
" AND" ARRAY - (I, 8)
I,B
4" 4 4" 4"
I,B
__
I,B
I,B
I,il
__
I,B
I,B
__
I,B
u
P
P
I
I
STATE
~ON'T CARE'
I
I
CODE
-
I
I
I
I
TC02600S
STATE
INACTlve 2
L
CODE
a
I
I
I
I, B
I
TC02630S
INACTIVE 1
I
CODE
•
I
J
Pn STATUS
ACTIVE
NOTES:
1. This is the initial unprogrammed state of all links. All unused Pn and Dn terms must be programmed as
INACTIVE.
2. Any gate Pn will be unconditionally inhibited if the True and Complement of either input (lor B) are both
programmed for a connection.
May 11, 1988
I
i, B
I
c:oe
I
TC0262C1S
VIRGIN STATE
fo-S
Po STATUS
C~DE I
STATE
TC02610S
OR ARRAY - (0, 8)
I
P
P
STATE
172
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at "L" polarity.
2. All Pn terms are enabled in the AND
array. (Don't Cares)
3. All Pn terms are inactive in the OR array.
"TI
f
on
"CI
r
:P
a;'
a::
"CI
~
::II
I
-a
0
I
OR
----------+---------I
AND
CUSTOMER NAME
PURCHASE ORDER #
SIGNETlCS DEVICE #
INACTIVE
CF(XXXX)
CUSTOMER SYMBOLIZED PART #
TOTAL NUMBER OF PARTS
REV _ _ _ DATE
PROGRAM TABLE #
M
I
10
0
8
7
•
• •
3
2
1
0
•
7
I.
• •• •
1
•
r
m
0"
(POl)
CD'
POlAIIITY
r-
I I I I I
I I I
0
OR
~
M
III
1---------I~
Il
ill
3
3D)
~
CONTROl.
lOW
CQ
!i:
8(0)
T
2
1
2
3
E
B
0
1
2
3
D
A
•
7
••••
1
•
B
CQ
8(0)
0
2
A
8
7
•
5
•
3
•
1
(i'
0
•
•
N
10
~
11
X
,.,.
2.
21
22
23
2D
21
22
23
PIN
~
CW
~!
8
7
• •
4
3
2
1
23
22
21
20
17
16
15
14
n
!if
•
en
~.
CD
VI
...
N
''""''""
17
9
~
&
c::
-
14
10
i!'
X
I.,."
11
en
~.
N
C
12
17
18
ig
-
7
8
,.,.
,.
>
"'2.
D)
••
10
11
12
13
14
VI
'<
•
7
8
g."
......l>
•
•
5
(;j
tNAcnYE
I.B(II I
I
I
I
B(II
4
)H
Il
DON'T CARE j-
AND
T
E
R
1.8
i,a
::II
:P
~
....--------I
I
I
I
10
a
G')
~
,. ,.
13
H
22
21
2D
17 "
,.
14
13
NOTES:
~.
=1'~'~~n1':' ~~~':,,':'!'xl"
; ~ ~~-'.::l'': ~;.u~I~';u.. (B. 0) In tho
4. n:ll!:l~Ud ..me In tho AND array
mull be programmed .. INACTiVe.
~
!l
::::t
f
r-
en
:!:j
w
,--
~
-a
Q.
go·
"
Signefics
PLHS473S
Document No.
ECN No.
Date of Issue October 1989
Status
Preliminary Specification
Programmable Logic Array
(20 x 24 x 11)
Programmable Logic Devices
DESCRIPTION
The PLHS473S is a two level logic device
consisting of 24 AND gates and 22 OR
gates with fusible link connections for
programming 1/0 polarity and direction.
The Signetics state-of-the-art OxideIsolated Bipolar process is used to produce performance not yet achieved in
devices of this complexity.
The PLHS473 has an enhanced drive
capability of 24mA .. This, coupled with the
fact that it can drive both 30pF and 200pF
loads, allows it to be directly connected to
an external bus.
All AND gates are linked to 11 input pins,
9 bidirectional 110 pins, and 2 dedicated
output pins. The bidirectional pins are
controlled via the OR array. Using these
features, the PLHS473S can be configured with up to 20 inputs and as many
as 11 outputs.
The AND array input buffers provide both
the True and Complement of the inputs
(Ix) and the bidirectional signals (Bx) as
programmable connections to the AND
gates. All 24 AND gates can then be
optionally linked to all 22 OR gates (a
feature known as Product Term sharing,
not found in PALs® or most macrocell architectures). The OR array drives 11 output buffers which can be programmed as
Active-High for AND-OR functions or
Active-Low for AND-NOR functions. In
addition, the 1/0 configuration of each bidirectional pin is incfividually controlled by
sum--
ORDERING INFORMATION
DESCRIPTION
THERMAL RATINGS
ORDER CODE
24-pin Plastic DIP;
(300mil-wide)
PLHS473SN
28--Pin Plastic Leaded Chip Carrier
(450mil-wide)
PLHS473SA
TEMPERATURE
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
°A
Maximum junction
150°C
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
LOGIC FUNCTION
RATINGS
UNIT
+7
VDC
TYPICAL PRODUCT TERM:
Pn=A·9·C·O· ••.
Vee
VIN
Supply voltage
Input voltage
+5.5
VDC
VOUT
Output voltage
+5.5
VDC
liN
Input currents
-30 to +30
mA
AT OUTPUT POlARITY = l
lOUT
Output currents
+100
mA
Z:PIJ+Pl+PZ+ ...
Z = Pli .",. ~ ...•
TA
Operating temperature range
o to +75
°c
TSTG
Storage temperature range
-B5 to + 150
°c
NOTES:
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
October 1989
176
TYPICAL lOGIC FUNCTION:
AT OUTPUT POlARITY = H
Z=PO+Pl+P2 ...
1. Foreach aftha 11 outputs,eitherfunction Z (ActiveHigh) or Z (Active-Low) is available, but not both.
The desired output polarity is programmed via the
2. i~t'8~ 8~!~:are
Usef defined connections to fixed
inputs (I), fixed output pins (0) and bidirectional pins
(B).
Signetics Programmable Logic Devices
Preliminary Specification
PLHS473S
Programmable Logic Array (20 x 24 x 11)
.
DC ELECTRICAL CHARACTERISTICS o°c -< TA -< +75 0 C, 4.75 -< Vee -<
SYMBOL
I
PARAMETER
5.25V
I
TEST CONDITIONS
Typl
I
I
LIMITS
Min
Max
UNIT
Input vollage2
~MIN
V IL
Low
Vee
V IH
High
Clamp 3
Vee ~ MAX
Vc
08
2.0
Vee ~ MIN, liN ~-12mA
V
V
-0.8
-1.2
V
Output voltage2
Vee ~ MIN
VOL
V OH
Low'
High5
10L
~
0.5
24mA
10H ~-2mA
V
V
2.4
Input current
Vee ~ MAX
~
IlL
Low
VIN
IIH
High
VIN ~ 5.5V
-100
OA5V
40
J.lA
J.lA
Output current
Vee~ MAX
VOUT
~
5.5V
40
OA5V
-100
10(OFF)
Hi-Z state 9
los
Short circuit 3, 5.6
VOUT
lee
Vee supply current'
Vee~ MAX
VOUT
~
~
0.5V
-15
J.lA
J.lA
-70
rnA
140
155
rnA
8
15
pF
10
15
pF
Capacitance
Vee ~ 5V
liN
CB
Input
I/O
VIN ~ 2.0V
VB ~ 2.0V
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
All typical values are at Vee ~ 5V. TA ~ +25°C.
All voltage values are with respect to network ground terminal.
Test one at a time.
Measured with inputs 0 - 4 ~ OV, inputs 5, 7 ~ 4.5V, and inputs 6, 8 - 10 + 10V.
Same conditions a Note 4 exoept input 8 ~ 4.5V
Duration of short circuit should not exceed 1 second.
Icc is measured with all inputs and bidirectional pins at 4.5V. Part in Virgin State
Measured at VT ~ VOL + 0.5V
Leakage values are a combination of input and output leakage.
October 1989
177
Signetics Programmable Logic Devices
Preliminary Specification
PLHS473S
Programmable Logic Array (20 x 24 x 11)
AC ELECTRICAL CHARACTERISTICS O°C ---r-I
I
o--L---.
<>-r-
o-l.--
10
I
By
110
BX
GND
MEASUREMENTS:
-:}
Input Pulses
TIMING DEFINITIONS
SYMBOL
PARAMETER
!Po
Propagation delay between
input and output.
100
IoE
October 1989
Ii
I
BZ
f-1.-
Ox
f--
Bw
All circuit delays are measured at the +'.5V Jevel of
Inputs and outputs. unless otherwise specified.
TIMING DIAGRAM
Delay between input change
and when output is off (Hi-Z
or High).
Delay between input change
and when output reflects
specified output level
178
J:D'""="
R,
I
I
R2
AND JIG
CAPACITANCE
I
":"":"
CL
Preliminary Specification
Signetics Programmable Logic Devices
PLHS473S
Programmable Logic Array (20 x 24 x 11)
OUTPUT POLARITY - (0, B)
LOGIC PROGRAMMING
The PLA can be programmed 0Y' Iileans of
Logic programming equipment.
,~
With Logic programming the AN D/ORlEx-OR
gate input connections necessary to implement
the desired logic function are coded direcrty
from logic equations using the Program Table
on the following page.
I
In this table, the logic state of variables I, P and
B, associated with each Sum Term S is assigned a symbol which results in the proper fusing pattern of corresponding links, defined as
follows.
ACTIVE LEVEL
I
COOE
I(NON~~~:RTlNG) I
H
I
I
I
I
I
ACTIVE LEVEL
LOW'
(INVERTING)
..
I
CODE
J
J
"
"
'
,
8
1"8
1
8
1
1
"AND" ARRAY - (I, B)
I,B
1,8
~B
~B
p
I
I,B
~B
r,B
p
I
I
STATE
STATE
INACTIVE 2
B
p
CODE
I
r,B
0
I
p
STATE
STATE
I,B
r,B
"OR" ARRAY - (0, B)
VIRGIN STATE
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at "L" polarity.
2. All Pn terms are enabled. (Don't Cares.)
3. All P n terms are inactive on all outputs.
L
I
PnSTATUS
INACTIVE'
I
I
COOE
•
J
I
Pn STATUS
CODE
ACTIVE
A
NOTES:
1. This is the initial unprogrammed state of all links.
2. Any gate Pn will be unconditionally inhibited if the true and complement of either input (lor B)
are both programmed for a connection.
October 1989
179
"~
0"
~
~
lE
'"
1I
0
CC
C)
D)
1I
AND
SIGNETICS DEVICE #
CF(XXXX)
CUSTOMER SYMBOLIZED PART #
TOTAL NUMBER OF PARTS
M
10
•
8
7
B(I)
• •
4
•
2
1
•
8
7
• •
4
3
2
1
•
1
2
3
M
~BP)
~
INActrIE
r
•
m
I~--------CONTROl.
1---------l~
(POl)
LDW
I I
I
B
A
8
7
• ••
2
1
•
I.•
8
..
!a
c)"
"l)
.8iil
3
3
II>
S!:
li>
CD
.8o·
0
CC
..
r-
~
~.
~
B
A
8
T
•
5
•
D)
B(O)
3
•
1
•
'<
I \.)
0
X
I\.)
~
......
X
-
7
I.•
11
e-
::0
»
I 1
I I
0
3
3
3D)
IC
~
D
E
~
n"
POlAIIT't
IL
4
T
8
11
12
12
13
13
,."
,.
,.
,.,.
20
21
20
21
22
23
,.
14
15
17
17
18
'2
..
I
III
OR
•
••
••
••
Il
~
••
PIN
i,1
I
I
;
1
•
~
IH
i:
B(O)
T
I
•
I.
I, B
I
I
I
AND
T
INAcnVE
DON'T CARE 1-
REV _ _ _ DATE
PROGRAM TABLE #
R
OR
I
PURCHASE ORDER #
E
>
I
----------+---------I
CUSTOMER NAME
{ll
"tI
~
11
I. •
8
7
• •
4
3
2
1
23
22
21
20
17
,.
15
14
1. ,.
13
23
..
21
..
17 "
,.
14
13
NOTES:
1, The FPLA 10 8h\lpod with all nnks OIJen,
!!l
2. UnUled I and B bill in the AND array exist
cw
IE"
~~
3.
~ ~~-'n:::'~ !,rg~I=Uts (B, 0) In tho
virgin atate.
4. Unused product termaln the AND array
mull be pn>grammod u INACTIVE.
"tJ
~
"tI
r-
::I:
3'
:r
~
f
~
......
en r.
Co)
PLS100jPLS101
Signetics
Field-Programmable Logic
Array (16 X 48 X 8)
Signetics Programmable Logic
Product Specification
Application Specific Products
• Series 28
DESCRIPTION
FEATURES
The PLS100 (3-state) and PLS101
(Open Collector) are bipolar, fuse Programmable Logic Arrays (FPLAs). Each
device utilizes the standard AND/OR/
Invert architecture to directly implement
custom sum of product logic equations.
•
•
•
•
Each device consists of 16 dedicated
inputs and 8 dedicated outputs. Each
output is capable of being actively controlled by any or all of the 48 product
terms. The True, Complement, or Don't
Care condition of each of the 16 inputs
can be ANDed together to comprise one
P-term. All 48 P-terms can be selectively
ORed to each output.
The PLS100 and PLS101 are fully TTL
compatible, and chip enable control for
expansion of input variables and output
inhibit. They feature either Open Collector or 3-state outputs for ease of expansion of product terms and application in
bus-organized systems.
Order codes are listed in the Ordering
Information Table.
•
•
•
•
•
•
PIN CONFIGURATIONS
Field-Programmable (Ni-Cr link)
Input variables: 16
Output functions: 8
Product terms: 48
1/0 propagation delay: 50ns
(max.)
Power dissipation: 600mW (typ.)
Input loading: -100MA (max.)
Chip Enable input
Output option:
- PLS 100: 3-State
- PLS101: Open-Collector
Output disable function:
- 3-State: Hi-Z
- Open-Collector: High
N Package
I.
I.
'10
'11
"2
'13
'14
'15
CRT display systems
Code conversion
Peripheral controllers
Function generators
Look-up and decision tables
Microprogramming
Address mapping
Character generators
Data security encoders
Fault detectors
Frequency synthesizers
16-bit to 8-bit bus interface
Random logic replacement
CE
FS
F,
F,
F2
FO
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
F7
GND
F3
COO42S4S
t
Fuse Enable Pin: It is recommended that thiS pin
either be left open or connected to ground dUring
normal operation.
A Package
FUNCTIONAL DIAGRAM
~-+-t-----:+-;~ TVPlCALCONNECTIOH
'15
114
'13
112
111
110
TOP VIEW
May 11, 1988
181
853-0308 93256
Product Specification
Signetics Application Specific Products • Series 28
Field-Programmable Logic
Array (16 X 48 X 8)
PLS100/PLS101
FPLA LOGIC DIAGRAM
NOTES:
1. All AND gate inputs with a blown link float to a logic "1",
2. AilOR gate inputs with a blOWn fuse float to logic "0".
3. $ Programmable connection.
May 11, 1988
182
Product Specification
Signetics Application Specific Products • Series 28
Field-Programmable Logic
Array (16 X 48 X 8)
PLS100/PLS101
ORDERING INFORMATION
I
DESCRIPTION
TRI-STATE
I
OPEN-COLLECTOR
28-pin Plastic DIP 600mil-wide
PLS100N
PLS101N
28-pin Plastic Leaded Chip Carrier
PLS100A
PLS101A
I
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
The PLS 100 device is also processed to
military requirements for operation over the
military temperature range. For specilications
and ordering information consult the
Signetics Military Data Book.
THERMAL RATINGS
PARAMETER
RATINGS
TEMPERATURE
150°C
Vee
Supply voltage
VDe
Maximum junction
Y'N
Input voltage
+5.5
VDe
Maximum ambient
75°C
Vo
Output voltage
+5.5
VDe
liN
Input current
±30
mA
Allowable thermal rise
ambient to junction
75°C
+100
mA
lOUT
Output current
TA
Operating temperature range
TSTG
Storage temperature range
+7
UNIT
a to
+75
°C
-65 to + 150
°C
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress
rating only. Functional operation at these or any other conditions above those indicated in the operational
and programming specification of the device is not implied.
DC ELECTRICAL CHARACTERISTICS
O°C <; TA <; + 75°C, 4.75V <; Vec <; 5.25V
LIMITS
SYMBOL
PARAMETER
UNIT
TEST CONDITION
Typ1
Max
-0.8
0.8
-1.2
V
V
V
0.35
0.45
V
V
<1
-10
25
-100
/lA
/lA
1
-1
40
-40
-70
/lA
mA
= Max
120
170
mA
= High, Vee = 5.0V
Y'N = 2.0V
VOUT = 2.0V
8
17
Min
Input voltage 2
V,H
V,L
Vie
High
Low
Cl amp2.3
Vce = Max
Vee = Min
Vee = Min, liN = -12mA
2
Output voltage 2
VOH
VOL
Vce = Min
10H = -2mA
10L = 9.6mA
High (PLS100)4
Low5
2.4
Input current
I'H
I'L
Y'N = 5.5V
Y'N = 0.45V
High
Low
Output current
10(OFF)
Hi-Z state (PLS100)
los
Short circuit (PLS100)3. 6
lee
Vce supply current'
Vee = Max
VOUT = 5.5V
VOUT = 0.45V
CE = Low, VOUT = OV
CE
= High,
Vee
-15
Capacitance
CE
C'N
COUT
Input
Output
Notes on following page.
May 11, 1988
183
pF
pF
Signetics Application Specific Products • Series 28
Product Specification
Field-Programmable Logic
Array (16 X 48 X 8)
AC ELECTRICAL CHARACTERISTICS R,
SYMBOL
I
PARAMETER
PLS100jPLS101
~ 470>1, R2 ~ 1k>l, CL ~ 30pF, DoC';; TA ,;;
I
TO
I
FROM
+ 75°C, 4.75V';; Vcc';; 5.25V
I
I
I
I
UNIT
50
l
ns
I
30
I
ns
I
30
I
ns
LIMITS
Min
I
Typ'
I
Max
35
I
15
15
Propagation delay
tpD
tCE
I
I
Input
Chip enable
I
Output
J
Output
I
Output
I
J
Chip enable
I
I
I
I
Chip enable
I
I
Input
I
Disable time
tCD
I
Chip disable
NOTES:
1. All values are at Vee = 5V, TA = + 25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one pin at a time.
4. Measured with V IL applied to CE and a logic high stored.
5. Measured with a programmed logic condition for which the output test is at a low logic level. Output sink current is applied through a resistor to Vee6. Duration of short circuit should not exceed 1 second.
7. Icc is measured with the chip enable input grounded, all other inputs at 4.5V and the outputs open.
May 11,1988
184
Signetics Application Specific Products • Series 28
Product Specification
Field-Programmable Logic
Array (16 X 48 X 8)
PLS100jPLS101
OUTPUT POLARITY - (F)
LOGIC PROGRAMMING
PLS100/PLS101 logic designs can be gener-
ated using Signetics' AMAZE PLD design
software or one of several other commercially
available, JEDEC standard PLD design software packages. Boolean and lor state equation entry is accepted.
PLStOO/PLStOt logic designs can also be
generated using the program table entry format detailed on the following pages. This
program table entry format is supported by
the Signetics' AMAZE PLD design software
(PTP module). AMAZE is available free of
charge to qualified users.
To implement the desired logic functions, the
state of each logic variable from logic equations (I, B, 0, P, etc.) is assigned a symbol.
The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below.
" AND" ARRAY - (I)
I
I
"OR" ARRAY - (F)
fo-s
I
I
Po STATUS
ACTIVE'
I
I
CODE
A
I
I
I
I
Po STATUS
INACTIVE
I
I
CODE
•
I
I
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive)
AND gates Pn.
2. Any gate Pn will be unconditionally inhibited if anyone of its (I) link pairs is left intact.
May 11, 1988
185
Signetics Application Specific Products • Series 28
Product Specification
Field-Programmable Logic
Array (16 X 48 X 8)
PLS100jPLS101
VOLTAGE WAVEFORMS
TEST LOAD CIRCUITS
.3'OV-~--90%
I
I
I
I
I
FOr,OUT
,,
F,~
0 - - '15
0--
OV
+5.
I
I
~J
R2
cr
-1sn.L. . Jsn.C
----L-JL
10%
Vee
0 - - I()
GND
.3'OV~
90%
ov
CL
-=-
~
'f
(INCLUD£S
SCOPE AND JIG
CAPACITANCE)
10%
-Jsns
MEASUREMENTS:
All circuit delays are measured at the + 1,5V level
of inputs and outputs, unless otherwise specified.
TCOI661S
TCG1651S
~5n5l-
Input Pulses
TIMING DEFINITIONS
TIMING DIAGRAM
, - - - - - - - - - - - - - - - - - +3.0V
SYMBOL
tCE
tCD
Delay between when Chip
Enable becomes High and
Data Output is in off state
(Hi-Z or High).
tpD
Delay between beginning of
valid Input (with Chip Enable
Low) and when Data Output
becomes valid.
' - - - - - - - - - - - - - - - - - - - - OV
+3.0V
OV
PARAMETER
Delay between beginning of
Chip Enable low (with Input
valid) and when Data Output
becomes valid.
VOH
VOL
Read Cycle
VIRGIN STATE
The PLS100/101 virgin devices are factory
shipped in an unprogrammed state, with all
fuses intact, such that:
1. All Pn terms are disabled (inactive), in the
AND array.
2.
3.
May 11, 1988
186
All Pn terms are active in the OR array.
All outputs are active-High.
;;::
"11
~
-~
to
CD
CD
">
PROGAM TABLE ENTRIES
CUSTOMER NAME
INPUT VARIABLE
PURCHASE ORDER #
-SIGNETICS DEVICE # _ _ _ _ ~ (XXl2
~
'"
~
~
t;~
~~
~o
"'''' ....'" '"0> "''''
'" ~
.. co
~ ~
I
I
for
1m
L
I
I
unused
Don't Care
-
Prod. Term
Present in F p
(dash)
mputs
"''''0 ..
'" '"co ....'" '"0>
~
OUTPUT FUNCTION
of
"''''
'" ~
Prod. Term Not
Active
High
Present in Fp
I
A
OUTPUT ACTIVE LEVEL
• (period)
I
H
L
>
NOTES
,. Entries independent of output polarity
2 Enter (A) for unused outputs of used P-terms
,. Polarity programmed once only
2_ Enter (H) for all unused outputs
~~ ~~ .. co
~
~
.... 0>
"'~
'" '"
~o
.. co
.... 0>'"
~'"
'"
~
o
~~
-'
"'~
I
~~
o~
.... 1
'"
O>...J
~
"'I
'"
~...J
0>
....
",I
~I
"j
~
, < ,Q.
tl
a
-0
~
~o
'"0--
xa
::>
00(Q
~3
003
xo
000-
-CD
r-
i
(J)
=t
o
(Q
!
('5"
I
8is
en
-g
o0;;
0-
"8.
c
&
•
U)
m
ffi'
"
:
00
Z
"-i
c
l>
zC
i:
1
0
0>1
'"
~
'"
"'Ig
~
~
'"
~
0>
~
....
~
co
1'T1
",::>
..J
..
~
>
ID
r
I
"'~
'"
o
-I
"'~ T
COl
~
3:
~l:Jm-l
'"
co
:0
NOTES
used
.....J
~
:0
Low
0> '"
....
"
oC)
Active
(J)
»:I!
.... CD
I -i
~
'" ~
"'I~
LJ
1 I
r"1
1--l(3
0 1 I r-
::cr"1?:i
I--l =i
I 1-<
,,- r"'1
~
~
01
1-...1
Ll_
-0
r-
en
.....
0
0
..........
aQ"
c
'l
en
-0
D
en
0
r-
.....
0
.....
(J)
~
8-
is
::>
Signetics
Programmable Logic Devices
Section 5
Programmable Logic
Sequencer Device
Data Sheets
INDEX
Series 20
PLS155
PLS157
PLS159A
Series 24
PLS167/A
PLS168/A
PLS179
PLC42VA12
Series 28
PLC415-16
PLS105/A
PLUS105-40
Programmable Logic Sequencer (16 x 45 x 12); 14MHz .... 191
Programmable Logic Sequencer (16 x 45 x 12); 14MHz .... 202
Programmable Logic Sequencer (16 x 45 x 12); 18MHz .... 213
Programmable Logic Sequencers (14 x 48 x 6); 14, 20MHz .. 223
Programmable Logic Sequencers (12 x 48 x 8); 14, 20MHz .. 234
Programmable Logic Sequencer (20 x 45 x 12); 18MHz .... 245
CMOS Programmable Logic Sequencer
(42 x 105 x 12); 25MHz .............................. 256
Programmable Logic Sequencer (17 x 68 x 8); 16MHz ..... 275
Programmable Logic Sequencers (16 x 48 x 8); 14, 20MHz .. 294
Programmable Logic Sequencer (16 x 48 x 8); 40MHz ..... 305
PLUS105-55
Programmable Logic Sequencer (16 x 48 x 8); 55MHz ..... 317
PLUS405-37/-45
PLUS405-55
Programmable Logic Sequencers (16 x 64 x 8); 37, 45MHz .. 329
Programmable Logic Sequencer (16 x 64 x 8); 55MHz ..... 344
Signefics
Document No. 853-0317
ECN No.
93255
Date of Issue
May 11, 1988
Status
Product Specification
I-
,,
t'rogrammaOl~
__ ,"_.
PLS155
Field-Programmable Logic
Sequencer (16 x 45 x 12)
n_.":~~~
Luyll,; Ut:=VI(...t:;:';:)
DESCRIPTION
The PLS155 is a 3-State output, registered logic element combining ANDIOR
gate arrays with clocked J-K flip-flops.
These J-K flip-flops are dynamically convertible to D--type via a "fold-back" inverting buffer and control gate Fc. ~ features
4 registered 1/0 outputs (F) in conjunction
with 8 bidirectional 1/0 lines (8). These
yield variable 1/0 gate and register configurations via control gates (0, L) ranging
from 16 inputs to 12 outputs.
The ANDIOR arrays consist of 32 logic
AND gates, 13 control AND gates, and 21
OR gates with fusible link connections for
programming 1/0 polarity and direction. All
AND gates are linked to 4 inputs (I), bidirectional 1/0 lines (8), internal flip-flop
outputs (a), and Complement Array output (C). The Complement Array consists
of a NOR gate optionally linked to all AND
gates for generating and propagating
complementary AND terms.
PIN CONFIGURATIONS
FEATURES
• 'MAX
= 14MHz
N Package
- 18.2MHz clock rate
vee
• Field-Programmable (Ni-Cr link)
87
• 4 dedicated inputs
86
• 13 control gates
F3
• 32 AND gates
F2
.21 OR gates
F,
Fa
• 45 product terms:
- 32 logic terms
- 13 control terms
85
8.
GND
• 8 bidirectional 1/0 lines
• 4 bidirectional registers
A Package
• J-K, T, or D-type flip-flops
• Asynchronous Preset/Reset
I,
10 eK vee 87
• Complement Array
• Active-High or -Low outputs
• Programmable UE control
• Positive edge-triggered clock
• Input loading:
-100~
(max.)
• Power dissipation: 750mW (typ.)
83 GND UE B4 85
• TIL compatible
• 3-State outputs
APPLICATIONS
• Random sequential logic
• Synchronous up/down counters
• Shift registers
• Bidirectional data buffers
• Timing 'unction generators
• System controllerslsynchronizers
• Priority encoder/registers
PHILIPS
191
Product Specification
Signetics Programmable Logic Devices
PLS155
Field-Programmable Logic Sequencer (16 x 45 x 12)
FUNCTIONAL DIAGRAM
(CONTROl TERMS)
(LOGIC TERMS)
L
•
E
.
0
>
OE
-
i
b
:>
Ii
b
~
_~t-Q
~I--
II
-C
1::
...
c
s
x
-=
B
D-
- - - - ---; - - -
---0
R
P
I
I
p
1
M
T31
To
May 11, 1988
Q
F
(n)
CK
K
"7
FC
On-chip TIC buffers couple either True (I, 8, 0)
or Complement (1, g, Q, C) input polarities to all
AN D gates, whose outputs can be optionally
linked to all OR gates. Any of the 32 AND gates
can drive bidirectional 110 lines (8), whose
output polarity is individually programmable
through aset of Ex-OR gates for implementing
AND-OR or AND-NOR logic functions. Similarly, any of the AND gates can drive the J-K
--~
R
J
inputs of all flip-flops. The Asynchronous Preset and Reset lines (P, R), are driven from the
OR matrix.
All flip-flops are positive edge--triggered and
can be used as input, output or 110 (for interfacing with a bidirectional data bus) in conjunction
with load control gates (L), steering inputs (I),
192
(8), (0) and programmable output select lines
(E).
The PLS155 is field programmable, enabling
the user to quickly generate custom patterns
using standard programming equipment.
Order codes are listed in the Ordering Information Table.
Product Specification
Signetics Programmable Logic Devices
PLS155
Field-Programmable Logic Sequencer (16 x 45 x 12)
FPLS LOGIC DIAGRAM
10
B,
B,
B,
Bo
F,
FO
CK
NOTES:
1 All OR gate inputs with a blown link float to
2 All other gates and control Inputs with a blown
3. ,~
WIRE-OR.
Programmable connection.
May 11, 1988
"0"
float to logic" 1"
193
'-....:t--DJ
CK
Product Specification
Signetics Programmable Logic Devices
PLS155
Field-Programmable Logic Sequencer (16 x 45 x 12)
FLIP-FLOP TRUTH TABLE
VIRGIN STATE
The factory shipped virgin device contains all
fusible links intact, such that:
1. DE is always enabled.
OE'
L
L
L
L
L
L
L
H
H
H
H
+10V
X
wise programmed to J-K only or J-K or D
(controlled).
5. All B pins are inputs and all F pins are
outputs unless otherwise programmed.
LOGIC FUNCTION
0
X
J( • lJ·
1 1 lot, 1
0
+,
X
X
L
4. All flip-flops are in D-mode unless other-
PRESENT STATE
c ....
NEXTSTATE
PRJ
K Q
F
HI-Z
L
L
3. All transition terms are disabled.
STATE REGISTER
CK
H
2. Preset and Reset are always disabled.
10: 1:21 ~t~ 1~R
L
X
X
H
L
L X
H X
X H
X L
L
H
i
i
i
i
i
i
i
i
L
L
L
L
L
L Q
0
L
H
L
L
H
L
H
L
H
L
L
L
H
H
0
Q
L
L
L
H
L
W
L
L
H
L
H
L'
X X L
H
L
W'
X X H
L
H
LU
NOTES:
1. Positive Logic:
J-K=To+T,+T2 .................. T3l
Tn ='C'··(l o ·I , ·1 2 ... )·(QO·Q, .. ·),(Bo
. B,· ... )
SET~:Jo=(Oa' ~ ·o,·~) .J(.
lJ'
c ...
Ko =0
RESETQ1:J,
2.
i
denotes transition from Low to High level.
3. X = Don't care
4. '= Forced at Fn pin for loading the J-K flip-
=0
K, = (03'
~
. 0, .
~)
. J(. lJ . c ...
HOLD 02: J2 .0
K2' O
TOGGlEOa: J3=(0a'~' 0, ·~)·X ·lJ· C ...
K3=(0a'll2' 0, ·Oo)·X· IJ· C ...
NOTE:
Similar logic functions are applicable for D
and T mode flip-flops.
flop in the Input mode. The load control
term, Ln mustbeenabled(HIGH)andthe pterms that are connected to the associated
flip-flop must be forced LOW (disabled)
during Preload.
5. At P = R = H, Q = H. The final state of Q
depends on Which is released first.
6. " = Forced at Fn pin to load J-K flip-flop
independent of program code (Diagnostic
mode), 3-State B outputs.
THERMAL RATINGS
ORDERING INFORMATION
TEMPERATURE
ORDER CODE
DESCRfPTION
20-Pin Plastic DIP (300mil-wide)
PLS155N
Maximum junction
150°C
20-Pin Plastic Leaded Chip Carrier
PLS155A
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
ABSOLUTE MAXIMUM RATINGSl
RATINGS
SYMBOL
PARAMETER
Max
UNIT
+7
Vrx;
Input voltage
+5.5
Vrx;
VOUT
Output voltage
+5.5
Vrx;
liN
Input currents
+30
rnA
lOUT
Output currents
+100
rnA
TA
Operating temperature range
0
+75
°C
TSTG
Storage temperature range
~5
+150
°C
Vee
Supply voltage
VIN
Min
-30
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
May 11, 1988
194
Signetics Programmable Logic Devices
Product Specification
PLS155
Field-Programmable Logic Sequencer (16 x 45 x 12)
DC ELECTRICAL CHARACTERISTICS ooc ~ TA ~ +75°C, 4.75V ~ Vee ~ 5.25V
,
SYMBOL
PARAMETER
I
TEST CONDITION
Min
Vee = Max
Vee = Min
Vee = Min,llN =-12mA
2.0
I
J
UMITS
Typ1
Max
UNIT
-Q.8
0.8
-1.2
V
V
V
0.35
0.5
V
V
Input voilage2
VIH
VII.
V-c
High
Low
Clamp
Output voltagr
VOH
VOL
High
Low
Vee = Min
IOH=-2mA
IOl= 10mA
2.4
Input currents
Vee = Max
IIH
High
VIN = 5.5V
<1
80
~
III
Low
VIN =0.45V
-10
-100
~
~
Output current
Vee = Max
IO(OFF)
Hi-Z states, 6
VOUT = 5.5V
1
80
VOUT = 0.45V
-1
-140
~
-70
mA
190
mA
los
Short circuit3• 7
VOUT =OV
lee
Vee supply current4
Vee = Max
150
Vee = 5.0V
V IN =2.0V
VOUT= 2.0V
8
15
-15
Capacitance
CIN
COUT
NOTES:
Input
Output
1. All typical values are at Vee = 5V, TA = +25°C.
2.
3.
4.
5.
S.
7.
All voltage values are with respect to network ground terminal.
Test one at a time.
lee is measured with the OE input grounded, all other inputs at 4.5V and the outputs open.
Leakage values are a combination of input and output leakage.
Measured with V IH applied to OE.
Duration of short circuit should not exceed 1 second.
May 11, 1988
195
pF
pF
Product Specification
Signetics Programmable Logic Devices
PLS155
Field-Programmable Logic Sequencer (16 x 45 x 12)
AC ELECTRICAL CHARACTERISTICS oOC ~ TA ~ +75°C, 4.75V ~ Vee ~ 5.25V,
Rl =4700, R2 = lkll
UMITS
SYMBOL
PARAMETER
FROM
TO
TEST CONDITION
Min
Typl
Max
UNIT
Pulse width
!eKH
CIock2 High
CK+
CK-
Cl = 30pF
25
20
ns
!eKl
Clock Low
CK-
CK+
Cl = 30pF
30
20
ns
!eKP
Period
CK+
CK+
Cl=3OpF
70
50
ns
tpRH
Preset/Reset pulse
(I,B)-
(I,B) +
Cl = 30pF
40
30
ns
tlSl
Input
(I,B)±
CK+
C l =3OpF
40
30
ns
tlS2
Input(through Fn)
F±
CK+
C l =30pF
20
10
ns
tlS3
Input (through
Complement Array)4
(I,B)±
CK+
C l =30pF
65
40
ns
t/Hl
Input
(I,B)±
CK+
Cl = 30pF
0
-10
ns
t/H2
Input
F±
CK+
Cl = 30pF
15
10
ns
CK+
F±
Cl =30pF
25
30
ns
Setuptime5
Hold time
Propagation delay.
!eKO
Clock
IoEl
Output enable
01:-
F-
Cl = 30pF
20
30
ns
1001
Output disable3
OE+
F+
Cl = 5pF
20
30
ns
tpo
Output
(I,B)±
B±
C l = 30pF
40
50
ns
IoE2
Output enable
(I ,B) +
B±
Cl = 30pF
35
55
ns
1002
Output disable3
(I,B)-
B+
C l = 5pF
30
35
ns
tpRO
Preset/Reset
(I,B) +
F±
C l = 30pF
50
55
ns
NOTES:
1. All typical values are at Voc = 5V, T A = +250 C.
2. To prevent spurious clocking, clock rise time (10% - 90%) oS: 10ns.
3. Measured at VT = VOl + 0.5V.
4. When using the Complement Array IcKP = 95ns (min).
5. Limits are guaranteed with 12 product terms maximum connected to each sum term line.
6. For test circuits, waveforms and timing diagrams see the following pages.
VOLTAGE WAVEFORMS
TEST LOAD CIRCUIT
Vcc
?
!T--
Ioo--rI
I
In
o--l--
OUT
FO
~Fn
BXo-LCKe>--
GNO
-t
MEASUREMENTS:
AR circuit delays are measured at the + 1.5V level
of lf1luts and outputs. unless OI:herwise specified.
Input Pulses
196
JB~Rl
~BZ
!T--
BW<>-r--
May 11,1988
..sV
By
I
I
I----<> OE
R2-=
ANOJIG
CAPACITANCE
J
Cl
Signetics Programmable Logic Devices
Product Specification
Field-Programmable logic Sequencer (16 x 45 x 12)
TIMING DIAGRAMS
PlS155
TIMING DEFINITIONS
..
, n
I SYMBO'L I P' RAMETE"
.:IV
I,B
!eKH
Width of input clock pulse.
!eKL
Interval between clock pulses.
tCKP
Clock period.
tpRH
Width of preset input pulse.
t'S1
Required delay between
beginning of valid input and
positive transition of clock .
t'52
Required delay between
beginning of valid input forced
at flip-flop output pins, and
positive transition of clock.
t'H1
Required delay between
positive transition of clock and
end of valid input data.
t'H2
Required delay between
positive transition of clock and
end of valid input data forced
at flip-flop output pins.
!eKD
Delay between positive
transition of clock and when
outputs become valid (with
O'ELow).
toE1
Delay between beginning of
Output Enable Low and when
outputs become valid.
toD1
Delay between beginning of
Output Enable High and
when outputs are in the
OFF-State.
tpD
Propagation delay between
combinational inputs and
outputs.
toE2
Delay between predefined
Output Enable High, and
when combinational outputs
become valid.
toD2
Delay between predefined
Output Enable Low and when
combinational outputs are in
the OFF-State.
tpRD
Delay between positive
transition of predefined
Preset/Reset input, and
when flip-flop outputs
become valid.
(INPUTS)
OV
.:IV
CK
1.SY
OV
VOH
F
(OUTPUTS)
VOL
.:IV
OV
Flip-Flop Outputs
~---------------------------------------------.:IV
(INPU~:,.., ~1""._v_ _ _ _tp~
______
" _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV
(OUTPUT:
~ r---------~~
~.5V
if
VT
.f=~
k~~~~~~~~~~~~~-_~~10v
,L~'~
E
VOL
::v
Gate Outputs
May 11. 1988
197
Product Specification
Signetics Programmable Logic Devices
Field-Programmable Logic Sequencer (16 x 45 x 12)
TIMING DIAGRAMS (Continued)
,
I.B
(INPUTS)
J
+3V
1.SV
OV
+3V
t
CK
Onl MIN .....
I
-PRESET RESET
-)
,-'ISI
1.SV
I
--_.
OV
'eKO.
-r3V
1.5V
~'PRH - - -
(I, BIN PUTS)
+
1.SV
.... _------ ----(PRESET)
a
(RESET)
OV
'.X,... -----
--- -
.....
--'PRO ----
V
F
J~
(OUTPUTS)
,..----
(RESET)
1.SV
'-----
1511- (PRESET)
• The leading edge of preset/reset must occur only when the input clock is "low", and must remain "high" as long as
required to override clock The falling edge of preset/reset can never go "low' when the input clock is "high".
Asynchronous Preset/Reset
,-------------------------------~.,_------+3V
I,B
(LOAD SELECT)
1.5V
'.51,1
~-------------------------------'I\.------ov
r-----------------~--------------t-------+3V
OE
1.5V
~------------~------oV
j'---------
---------'1I
I
--+---------~Ir-------~ .---+-------+31,1 VOH
F
(INPUTS)
--t-------------~------------JI'---~-------oV VOL
-----1_
J
1001
• +31,1
CK
a
Flip-Flop Input Mode
May 11, 1988
198
PLS155
Product Specification
Signetics Programmable Logic Devices
PLS155
Field-Programmable Logic Sequencer (16 x 45 x 12)
LOGIC PROGRAMMING
PLSI55 logic designs can be generated using
Signetics AMAZE PLD design software or one
of several other commercially available,
JEDEC standard PLD design software packages. Boolean andior state equation entry is
accepted.
PLSI55 logic designs can also be generated
using the program table entry format detailed
on the following pages. This program table
entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
users.
"AND" ARRAY - (I), (B), (Qp)
I,B,O
..
~
___
I,B,O
~~o
'
~
STATE
INACTlVE',2
I
I
CODE
0
I
I
~~o
'
~'.'
___
I
STATE
I,B,O
I
~'
I
I
STATE
I,B,O
I,~O
(T,
CODE
I
L
I
..
___
(T, FC, L. P, R, D)"
CODE
H
I,~O
I,~O
I,B,O
(T, FC, L. P, R, D)"
(T, FC, L, P, R, D)"
I
I
..
___
To implement the desired logic functions, the
state of each logic variable from logic equations
(I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
I
STATE
DON'TCARE
Fe, L, P, R, D)"
I
CODE
-
I
"COMPLEMENT" ARRAY - (C)
c:t: c:t: c:t: c:t:
(Tn' FC)
I
ACTION
I
INACTIVE', 3, S
I
I
o
I
I
I
I
ACTION
GENERATES
1
I
CODE
A
l
I
I
I
"OR" ARRAY - (F-F CONTROL MODE)
I
I
ACTION
(CO-:tn:.&D)
I
CODE
I
A
I
1
ACTION
CODE
•
Notes on follOWing page.
May 11,1988
(T.. FC)
(T.. FC)
(T.. FC)
CODE
199
ACTION
PROPAGATE
I CODE I
I • I
I
I
ACTION
TRANSPARENT
I CODE I
I - I
Product Specification
Signetics Programmable Logic Devices
PLS155
Field-Programmable Logic Sequencer (16 x 45 x 12)
"OR" ARRAY - (an = D-Type)
Tn
Tn
Q
Q
"OR" ARRAY - (an = J-K TYpe)
Q
Q
Q
Q
ACTION
CODE
ACTION
CODE
ACTION
TOGGLE
o
SET
H
RESET
"OR" ARRAY - (5 or B), (P), (Rl
CODE
ACTION
CODe
HOLD
"EX-OR" ARRAY - (B)
-L-r>-P,
R,S -L-r>-P.R,S
I '--'
I '--'
(ORB)
(ORB)
I
I
Tn STATUS
I
I
I
CODE
AcnVE'
INACTIVE
CODE
POLARITY
Tn STATUS
I • I
POLARITY
CODE
HGH
H
LOW
"0£" ARRAY - (El
~D-t>* ~~t= ~D-t>* ~~
En
I
I
ACnoN
IDLE"-
I
I
CODE
o
En
I
I
I
ACTION
CONTROL
I
CODE
A
En
En
I I
ACTION
ENABLe"
I
CODE
•
I
I
I
ACTION
DISABLE
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (T. Fe. L. p. R. D)n will be unconditionally inhibited if both of the I. B. or Q links are left intact.
3. To prevent oscillations. this state is not allowed for C link pairs coupled to active gates Tn. Fe.
4. En = 0 and En = • are logically equivalent states. since both cause Fn outputs to be unconditionally enabled.
5. These states are not allOWed for control gates (L. p. R. D)n due to their lack of "OR" array links.
May 11.1988
200
I CODE I
I - I
Signetics Programmable Logic Devices
Product Specification
Field-Programmable Logic Sequencer (16 x 45 x 12)
PLS155
FPLS PROGRAM TABLE
!
-------t----!
AND
0"
INACTIVE
L 8.
ACTIVE
a
H
I
1,8(1),
~,~,,'","'0--+,-1
I
a (p)
OON'T CARE
A
P.(~.:~~I' I
INACTIVE.
I
I
I
I
I r,"'O"'GG:C,"',""0::-1
INA-CTIvE
Gt:.NER.l.TE
c
1
SET
PROPAGATE
I 1-."',"",,=,-+-,--1
TRANSPARENT _
1
HOLO
T
E
R
en
9
M
rw
(,:ONTROL
1
(0 ;JIKI
I
jlK 0' 0
IA
(C{lfllroUOId2.l
HIGH
H
LOW
L
flf MODE
-
-
-
~ ~O;;eSF?L:; 5~,;pped wi:h ~!! !ink:': iro1act. Tr.I)S;!.bac:k· I
Ii;
I
IDLE
1
0
CONTROL
A
ENABLE
1.
DISABLE
-
EA B:
I
I
ground of entries corresponding to states of virgin
links exists in the table, shown BLANK for clarity
2 Program unused C, I, B, and Q bits in the AND array as
(-). Program unused Q, B, P, and R bits in the OR
array as (-) or (Al, as applicable
3 Unused Terms can be left blank
4 Q (P) and Q (N) are respectively the present and next
.-----~.J....,
1_:-,s",tart.::;eS~O::.:.;1flip-flops 0
I
I
fa
Flf MOOE
fA
AND
O{N)
O{P)
B(I)
C
1
US
2
>-
3210765432103210
•
0
W
5
rw
6
It
....J
r-
7
it
8
Cl-
a::
::E
0
{)
9
0
W
III
L.U
N
0
10
:J
0
::E 0
r-
11
12
III
Z
0
13
,.
>W
Cf)
> Cf)
0
a::
W
Cl- X w {) rZ
w
Cf) X
::E
L.U
I X 0r- a::
::E
W
~
a::
~
LI-
{)
if)
:J
()
15
16
17
::E
~ 0
0
18
()
19
20
21
I
L.U
«r0
22
23
2.
25
26
I
>
W
a::
27
28
29
30
31
en
ra::
It It
it
Fe
t--',-+-+-+--hH-+-+-+-HH-+-+-+-HHr':""-LB
~
It
L.U
w a::
W () 0
::E 0 ;; a:: W
....J
« a:: w w III
Z 0
0 III ~
a:: W if) ::E
w Cf)
:J ::E
z «
::E « ()
~ ....J a::
:r:
0 ()
w
(!)
rCf) a:: z
~
0
:J :J (!) 0 a::
Uj
()
Cl-
Ll-
r-
Cl-
LA
07
06
05
o.
03
02
01
00
PtN
May 11, 1988
5
4
3
2 19 18 13 12
l
j
POLARITY
I 1
1 I
J
9
8
1
201
6
17 16 15 14
B(O)
3210BABA76543210
3
III
I
I
OR
0
Z
(!)
I-
I
- -I -,"---:-"_-----.--,-,.- - -
Signetics
Document No. 853-0318
ECN No.
93255
Date of Issue
May 11,1988
Status
Product Specification
PLS157
Field-Programmable Logic
Sequencer (16 x 45 x 12)
Programmable Logic Devices
DESCRIPTION
FEATURES
The PLS157 is a 3-State output, registered logic element combining ANDIOR
gate arrays w~h clock8d J-K flip-flops.
These J-K flip-flops are dynamically convertible to D-type via a "fold-back" inverting buffer and control gate Fc. It features
6 registered 110 outputs (F) in conjunction
w~h 6 bidirectional 110 lines (B). These
yield variable I/O gate and register configurations via control gates (D, L) ranging
from 16 inputs to 12 outputs.
• f MAX = 14MHz
The AND/OR arrays consist of 32 logic
AND gates, 13 control AND gates, and 21
OR gates w~h fusible link connections for
programming I/O polarity and direction. All
AND gates are linked to 4 inputs (I), bidirectional I/O lines (B), internal flip-flop
outputs (Q), and Complement Array output (C). The Complement Array consists
of a NOR gate optionally linked to all AND
gates for generating and propagating
complementary AND terms.
PIN CONFIGURATIONS
N Package
- 18.2MHz clock rate
• Field-Programmable (NI-Cr link)
• 4 dedicated Inputs
.13 control gates
• 32 AND gates
.21 OR gates
• 45 product terms:
- 32 logic terms
- 13 control terms
.6 bidirectional 110 lines
.6 bidirectional registers
A Package
• J-K, T, or D-type flip-flops
• 3-State outputs
• Asynchronous Preset/Reset
• Complement Array
• Active-High or -Low outputs
• Programmable UE control
• Positive edge-triggered clock
• Input loading: -100!J.A (max.)
• Power dissipation: 750mW (typ.)
• TTL compatible
APPLICATIONS
• Random sequential logic
• Synchronous up/down counters
• Shift registers
• Bidirectional data buffers
• Timing function generators
• System controllers/synchronizers
• Priority encoder/registers
PHILIPS
202
Product Specification
Signetics Programmable Logic Devices
Field-Programmable Logic Sequencer (16 x 45 x 12)
FUNCTIONAL DIAGRAM
(LOGIC TERMS)
(CONTROL TERMS)
R
On-<:hip TIC buffers couple either True (I, 8, Q)
or Complement (T, B, 0, C) input polarities to all
AN D gates, whose outputs can be optionally
linked to all OR gates. Any of the 32 AND gates
drives bidirectional 1/0 lines (8), whose output
polarity is individually programmable through a
set of Ex-OR gates for implementing AND-OR
or AN D-NOR logic functions. Similarly, any of
the 32 AND gates can drive the J-K inputs of
all flip-flops. The Asynchronous Preset and
Reset lines (P, R), are driven from the ANSD
array for 4 of the 8 registers. The Preset and
Reset lines (P, R) controlling the lower four registers are driven from the OR matrix.
May 11, 1988
L
L
All flip-flops are positive edge-triggered and
can be used as input, output or 1/0 (for interfacing with a bidirectional data bus) in conjunction
with load control gates (L), steering inputs (I),
(8), (Q) and programmable output select lines
(E).
The PLS157 is field programmable, enabling
the user to quickly generate custom patterns
using standard programming equipment.
Order codes are listed in the Ordering Information Table.
203
PLS157
Signetics Programmable Logic Devices
Product Specification
Field-Programmable Logic Sequencer (16 x 45 x 1!Q)
FPLS LOGIC DIAGRAM
NOTES:
1. All OR gate inputs with a blown link float to logic "0"
2. All other gates and control inputs with a blown link float to logic" 1"
3. $ denotes WIRE-OR
4.
Programmable connection.
May 11,1988
204
PLS157
Product Specification
Signetics Programmable Logic Devices
PLS157
Field-Programmable Logic Sequencer (16 x 45 x 12)
VIRGIN STATE
FLIP-FLOP TRUTH TABLE
The factorj shipped virgin device contains all
fusible links intact, such that:
1. Of is always enabled.
UE
2. Preset and Reset are always disabled.
3. All transition terms are disabled.
lot, 1
H
L
L X
H X
i
i
i
i
i
i
i
i
L
L
L
L
L
L
L
L
H
L
H
L
L
L
H
H
0
a
W
L
L
L
L
H
H
H
H
+10V
X
X
J(" •
Sn + ,
B • C ••••
NEXT STATE
F
X
X
L
LOGIC FUNCTION
STATE REGISTER
K Q
X
X
L
5. All 8 pins are inputs and all F pins are
outputs unless otherwise programmed.
PRESENT STATE
P R J
L
L
L
wise programmed to J-K only or J-K or D
(controlled).
1 0 10
CK
Hi-Z
L
4. All flip-flops are in D-mode unless other-
1~ 1:21 ~t~ 1 6 R
L
H
X H
X L
L
H
L
a
0
H
L
H
L
L
L
H
L
L
L
H
L
H
L·
X
X L
H
L
W·
X
X H
L
H
L· •
NOTES:
1. Positive Logic:
J-K=To+T, +T 2 .••.....•......••• T 3 ,
Tn=~·(lo·I,·12 ••. ) .(00 , 0, ... ). (80
·8,· ... )
SET .•. B' C .. .
NOTE:
Similar logic functions are applicable for D
and T mode flip-flops.
2.
i
denotes transition from Low to High level.
3. X = Don't care
4. • = Forced at Fn pin for loading the J-K flipflop in the Input mode. The load control
term, Ln mustbeenabled(HIGH) and the pterms that are connected to the associated
flip-flop must be forced LOW (disabled)
during Preload.
5. At P = R = H,
= H. The final state of
depends on which is released first.
6. •• = Forced at Fn pin to load J-K flip-flop
independent of program code (Diagnostic
mode), 3-State 8 outputs.
a
a
ORDERING INFORMATION
THERMAL RATINGS
DESCRIPTION
TEMPERATURE
ORDER CODE
20-Pin Plastic DIP (300mil-wide)
PLS157N
Maximum junction
150°C
20-Pin Plastic Leaded Chip Carrier
PLS157A
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
ABSOLUTE MAXIMUM RATINGS1
RATINGS
SYMBOL
PARAMETER
Max
UNIT
+7
Voc
Input voltage
+5.5
Voc
VOUT
Output voltage
+5.5
Voc
liN
Input currents
+30
rnA
lOUT
Output currents
+100
rnA
TA
Operating temperature range
0
+75
DC
Tsm
Storage temperature range
-65
+150
DC
Vee
Supply voltage
VIN
Min
-30
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
May 11,1988
205
Signetics Programmable Logic Devices
Product SpecifICation
PLS157
Field-Programmable Logic Sequencer (16 x 45 x 12)
DC ELECTRICAL CHARACTERISTICS oOc S; TA S; +75°C, 4.75V S; Vee S; 5.25V
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
Min
Vee = Max
Vee = Min
Vce=Min,IIN=-12mA
2.0
Typ'
Max
UNIT
-0.8
0.8
-1.2
V
V
V
0.35
0.5
V
V
Input voltage2
V/H
VI.
V-c
High
Low
Clamp
Output voltage2
VOH
VOL
High
Low
Vee = Min
IOH=-2mA
IOl= lOrnA
2.4
Input current
IIH
High
VIN = S.SV
<1
80
Ill.
Low
V IN =0.4SV
-10
-100
J.IA
J.IA
Output current
Vee = Max
IO(OFF)
Hi-Z states, 6
VOUT= 5.SV
1
80
VOUT = O.4SV
-1
-140
los
Short circuit3• 7
VOUT =OV
lee
Vee supply current"'
Vee = Max
150
Vee = S.OV
VIN = 2.0V
VOUT = 2.0V
8
15
-15
J.IA
J.IA
-70
rnA
190
rnA
Capacitance
C IN
COUT
Input
Output
NOTES:
1.
2.
3.
4.
5.
6.
7.
All typical values are at Vec = SV, TA = +2SoC.
All voltage values are with respect to network ground terminal.
Test one at a time.
Icc is measured with the OE input grounded, all other inputs at 4.SV and the outputs open.
Leakage values are a combination of input and output leakage.
Measured with VIH applied to OE.
Duration of short circuit should not exceed 1 second.
May 11, 1988
206
pF
pF
Signetics Programmable Logic Devices
Product Specification
PLS157
Field-Programmable Logic Sequencer (16 x 45 x 12)
AC ELECTRICAL CHARACTERISTICS o°c ~ TA ~ +75°C, 4.75V ~ Vee ~ 5.25V, R1
i
SYMBOL
I
PARAMETER
Pulse width
I
~470Q, R2 ~ 11<0
I
FROM
I
TO
I
I
TEST CONDITION
Typ'
I
I
UMITS
Min
Max
UNIT
!eKH
Clock2 High
CK+
CK-
CL ~ 30pF
25
20
ns
!eKL
Clock Low
CK-
CK+
CL ~ 30pF
30
20
ns
!eKP
Period
CK+
CK+
CL ~ 30pF
70
50
ns
tpAH
PreseVReset pulse
(I,B)-
(I,B) +
CL ~ 30pF
40
30
ns
tiSl
Input
(I,B)±
CK+
CL
30pF
40
30
ns
tiS2
Input (through Fn)
F±
CK+
CL ~ 30pF
20
10
ns
tiS3
Input (through
Complement Array)'
(I,B)±
CK+
CL ~ 30pF
65
40
ns
tiHI
Input
(I,B)±
CK+
CL ~ 30pF
0
-10
ns
tiH2
Input
F±
CK+
CL ~ 30pF
15
10
ns
Setuptime5
~
Hold time
Propagation delays
!eKO
Clock
CK+
F±
CL ~ 30pF
25
toE I
Output enable
OE-
F-
CL ~ 30pF
tODI
Output disable3
LiE +
F+
CL ~ 5pF
tpD
Output
(I,B)±
B±
tOE2
Output enable
(I,B) +
B±
tOD2
Output disable 3
(I,B)-
tpAO
PreseVReset
(I,B) +
30
ns
20
30
ns
20
30
ns
CL ~ 30pF
40
50
ns
CL ~ 30pF
35
55
ns
B+
CL ~ 5pF
30
35
ns
F±
CL ~ 30pF
50
55
ns
NOTES:
1. All typical values are at Vee ~ 5V, TA ~ +25°C.
2. To prevent spurious clocking, clock rise time (10% - 90%),; 10ns.
3. Measured at VT ~ VOL + 0.5Y.
4. When using the Complement Array tcKP ~ 95ns (min).
5. limits are guaranteed with 12 product terms maximum connected to each sum term line.
6. For test circuits, waveforms and timing diagrams see the following pages.
VOLTAGE WAVEFORMS
TEST LOAD CIRCUIT
Vcc
10 0--,-I
By
o--l-
BZ
BWo--r--
FO
BXo--i---
Fn
CKe----
GND
'::"
MEASUREMENTS:
All circuit delays are measured at the + 1.5V level
of inputs and outputs, unless otherwise specified.
Input Pulses
May 11, 1988
J:TI~~R,
I
In
+5V
207
OE
R2,::"
AND JIG
CAPACITANCE
J
CL
Signetics Programmable Logic Devices
Product Specification
Field-Programmable Logic Sequencer (16 x 45 x 12)
TIMING DIAGRAMS
PLS157
TIMING DEFINITIONS
SYMBOL
!eKH
+3V
I.B
!eKL
Interval between clock pulses.
tCKP
Clock period.
tpRH
Width of preset input pulse.
t'Sl
Required delay between
beginning of valid input and
positive transition of clock.
t,S2
Required delay between
beginning of valid input forced
at flip-flop output pins. and
positive transition of clock.
t'Hl
Required delay between
positive transition of clock and
end of valid input data.
t'H2
Required delay between
positive transition of clock and
end of valid input data forced
at flip-flop output pins.
!eKO
Delay between positive
transition of clock and when
outputs become valid (with
DE Low).
tOEl
Delay between beginning of
Output Enable Low and when
outputs become valid.
tOOl
Delay between beginning of
Output Enable High and
when outputs are in the
OFF-State.
tpo
Propagation delay between
combinational inputs and
outputs.
tOE2
Delay between predefined
Output Enable High. and
when combinational outputs
become valid.
t002
Delay between predefined
Output Enable Low and when
combinational outputs are in
the OFF-State.
tpRO
Delay between positive
transition of predefined
PreseUReset input. and
when flip-flop outputs
become valid.
(INPUTS)
OV
+3V
CK
1.5V
OV
VOH
F
(OUTPUTS)
VOL
PARAMETER
Width of input clock pulse.
+3V
OV
Flip-f'lop Outputs
~~-------------------------------------------------+3V
(INPU~: l:l-.S-V-------I-~-D-------.-,_________________________
oJ
(OUTPUTS)
B
f,-0:
:.sv
r---------F
toE2
(OUT~U;---------""
ENABLE) ___________..1.
_
f.:i
.
~
toD2~
OV
VOO
VOl
3V
o+v
_
Gate Outputs
May 11. 1988
208
Signetics Programmable Logic Devices
Product Specification
Field-Programmable Logic Sequencer (16 x 45 x 12)
TIMING DIAGRAMS (Continued)
+3V
~ 15V
I,B
(INPUTS)
OV
-i
\
eK
On. MIN,-l
+3V
1.5V
l-
I- IIS1~ 'eKo'-
If 1.5V
i'.'.5V
----
OV
+3V
·PRESET RESET
~lpRH _ _
(I, BIN PUTS)
.... ------- -----
----'.~.....
-- --
(PRESET)
a
(RESET)
I-- 1 PRO
---II.
~15V
F
(OUTPUTS)
OV
,..----
\._---
(RESET)
VOH
'.5V
(PRESET)
VOL
• The leading edge of preset/reset must occur only when the input clock is "low", and must remain "high" as long as
required to override clock. The falling edge of preset/reset can never go "low" when the input clock is "high"
Asynchronous Preset/Reset
+3V
I,B
(LOAD SELECT)
1.5V
1.5V
OV
+3V
OE
1.5V
OV
i-----------------'1I
I
---t------------~Ir-----------~
(INPUTS)
(FORCED DIN)
--t------------' 1'------------'
r - - - t - - - - - - - + 3 V VOH
1.5V
"'---+-------OV VOL
• +3V
eK
a
Flip-Flop Input Mode
May 11, 1988
209
PLS157
Signetics Programmable Logic Devices
Product Specification
PLS157
Field-Programmable Logic Sequencer (16 x 45 x 12)
LOGIC PROGRAMMING
PLS157 logic designs can be generated using
Signetics AMAZE PLD design software or one
of several other commercially available,
JEDEC standard PLD design software packages. Boolean andlor state equation entry is
accepted.
PLS157 logic designs can also be generated
using the program table entry format detailed
on the following pages. This program table
entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
users.
To implement the desired logic functions, the
state of each logic variable from logic equations
(I, B, O,P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
"AND" ARRAY - (I), (B), (Qp)
L~O
~'" ~'" ~'" ~
___
I,B,O
___
L~O
(T, FC, L, P, R, Din
I
I
STATE
INACTIVE',2
I
I
CODE
0
I
I
___
I,B,O
L~O
I,~O
(T, FC, 1., P, R, Din
I
STATE
I,B,O
I
COOE
H
I,~O
I
I
H,Q
I
CODE
L
I
I
I
STATE
DON'TCARE
I COOE I
I - I
"COMPLEMENT" ARRAY - (C)
4: 4: 4: 4:
I
I
INACTIVE', 3, S
I
CODE
I
o
(T.. FC)
(T.. FC)
(Tn' Fe)
ACTION
I
I
I
I
ACTION
I
COOE
GENERATES
I
A
I
I
I
I
"OR" ARRAY - (F-F CONTROL MODE)
I
ACTION
I
CODE
I (CO";tR~&D) I
A
I
1
ACTION
COOE
•
Notes on following page.
May 11, 1988
210
ACTION
PROPAGATE
I CODE I
I • I
'
(T, Fc, 1., P, R, Din
(T, FC, 1., P, R, D)n
STATE
..
1,8,Q
(T.. FC)
I
I
ACTION
TRANSPARENT
I COOE 1
I - I
Product Specification
Signetics Programmable Logic Devices
PLS157
Field-Programmable Logic Sequencer (16 x 45 x 12)
"OR" ARRAY - (an = D-Type)
Tn
Q
Q
"OR" ARRAY - (an = J-K Type)
Q
Q
ACTION
CODE
ACTION
CODE
ACTION
SET
H
RESET
L
HOLD
"OR" ARRAY - (5 or 8), (P), (R)
~P'R'S
I
L
Tn STATUS
I
CODE
I
I
ACTIVE'
I
A
I
I
I
(ORB)
CODE
"EX-OR" ARRAY - (8)
~P'R'S
I
L-/
Q
Q
(ORB)
L-/
Tn STATUS
INACTIVE
I CODE I
I • I
CODE
POLARITY
POLARITY
CODE
HIGH
H
LOW
"OE" ARRAY - (E)
"D-----t># "D-t>#
ACTION
IDlE 1,4
I
CODE
J
0
I
I
CODE
ACTION
I
CONTROL
I
A
"~
En
En
En
I
I
"D~
I
I
ACTION
I
ENABLE4
I
En
I
I
ACTION
I • I
I
DISABLE
CODE
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (T, Fe, L, P, R, D)n will be unconditionally inhibited if both of the I, B, or Q links are left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn, Fe.
4. En = 0 and En = • are logically equivalent states, since both cause Fn outputs to be unconditionally enabled.
5. These states are not allowed for control gates (L, P, R, D)n due to their lack of "OR" array links.
May 11,1988
211
I CODE I
I - I
Product Specification
Signetics Programmable Logic Devices
PlS157
Field-Programmable logic Sequencer (16 x 45 x 12)
FPLS PROGRAM TABLE
_ _ ~N~ _ _
INACTIVE
0
1.8, Q
H
F·8.0
1.8(1).
'I
DON'T CARE
-
INACTIVE
0
GENERATE
---t ___ ~R_
QlP}
-I
PROPAGATE
ACTIVE
I
INACTIVE
I
I
I
I
A
L
I
C
I
I
TRANSPARENT
A
-
i- ------------1 '
CONTROL
_
I
I
P, R. B (OJ,
-
10;01
1
-
",'
It::"~;O~led) A
I'"
HI
,
RESET
(0
= JIl(l
HIGH
I
'ow
A
I
I
-
EA, B
H
,
IPOL,)
I
I
I
I
I'
states of Illp-flops Q
E,
FIF MODE
I
I
I
I
EA
I
I
I
..
3
2
1
0
•
5
3
I T1
OR
8(1)
I
C
PO'A.RITY
I
AND
T
E
R
\,2
0
CONTROL
DISABLE
I
1
-
HOLD
IDLE
ENABLE
I
0
TOGGLE
I
(f)
FIF MODE
I
NOTES
The FPLS IS shipped with alllmks intact. Thusa background of entries corresponding to states of vIrgm
links exists In the table, shown BLANK for clarity
2 Program unused C, I, S, and Q bits in the AND arr ayas
(-) Program unused a, B, P, and A bits m th • OR
array as (-) or (A), as applicable
3 Unused Terms can De lel! blank
a (Pi and Q IN) are respectively the present and next
Q(N)
O(P)
2
1
0
5
•
3
2
1
0
•
5
3
2
1
0
P
R
A
A
8(0)
•
5
3
0
f-
UJ
1
Cl
2
Z
Ui
3
>(IJ
•s
Cl
UJ
+
6
f-
UJ
...J
tlo
:E
a:
Cl.
7
ct
9
10
Cl
UJ
UJ
(IJ
"
N
af-
::J
z
a(IJ
i=
>(f)
:E
0
a:
aCl.
12
Cl
,.
>
15
13
UJ
a: W
<.)
(f)
fUJ
X :E
UJ z
x
UJ
a:
x
a
:E
f- UJ :E
f(f)
~
u.
<.)
(J)
~
<.)
+-
•
f-
a<.)
~
Cl
:E
a<.)
-1
,.
,.,.
I
~
Cl
I
I
+-
I
I
I
I
I
21
UJ
-j
I
17
20
I
I- - --
!
--
22
23
2.
I
I
25
--
2.
I
>
UJ
a:
I
27
2.
I
2.
30
........
31
(f)
Fe
f-
p.
a:
tlo tlo
UJ
ct
LU
a
:E ~
(J)
~ :E
\,2 z «
05
...J
02
LU
a
:E Cl ~ a:
«
a: LU UJ
Z
(IJ
a:
UJ
(f)
af-
J: fLU
~ Z
(f)
~
<.)
«
~
Cl.
UJ
...J
Cl
Ui
~
~
-I-
LA
a:
8a:
Cl.
t---
04
03
01
00
PIN
May 11,1988
.-~
I--l- -t- t- --
L8
(IJ
Cl
UJ
:E
R8
u. tlo
a:
5
4
3
2
"
121 •
•
7
•
,.
--~
171,.
212
15 14 13
--
--
I
2
1
0
Signetics
PLS159A
Document No. 853-1159
ECN No.
93255
Date of Issue
May11,1988
Status
Product Specification
I Programmable Logic Devices
Field-Programmable Logic
Sequencer (16 x 45 x 12)
I
PIN CONFIGURATIONS
DESCRIPTION
FEATURES
The PLS159A is a 3-State output, registered logic element combining AND/OR
gate arrays with clocked J-K flip-flops.
These J-K fli~lops are dynamically
convertible to D-type via a ''1old-back"
inverting buffer and control gate Fc. It features 8 registered I/O outputs (F) in conjunction with 4 bidirectional I/O lines (8).
These yield variable I/O gate and register
configurations via control gates (D, L)
ranging from 16 inputs to 12 outputs.
• High-speed version of PLS159
The AND/OR arrays consist of 32 logic
AND gates, 13 control AND gates, and 21
OR gates with fusible link connections for
programming I/O polarity and direction. All
AND gates are linked to 4 inputs (I), bidirectional I/O lines (8), internal flip-flop
outputs (Q), and Complement Array output eC). The Complement Array consists
of a NOR gate optionally linked to all AND
gates for generating and propagating
complementary AND terms.
N Package
=
• f MAX 18MHz
- 25MHz clock rate
• Field-Programmable (NI-Cr link)
.4 dedicated inputs
• 13 control gates
• 32 AND gates
.21 OR gates
• 45 product terms:
- 32 logic terms
- 13 control terms
• 4 bidirectional I/O lines
A Package
• 8 bidirectional registers
• J-K, T, or D-type flip-flops
•
Power~n reset feature on all
flip-flops (Fn 1)
=
• Asynchronous Preset/Reset
• Complement Array
• Active-High or -Low outputs
• Programmable DE control
• Positive edge-triggered clock
• Input loading:
-100~
(max.)
APPLICATIONS
• Power dissipation: 750mW (typ.)
• Random sequential logic
• TTL compatible
• Synchronous up/down counters
• 3-State outputs
• Shift registers
• Bidirectional data buffers
• Timing function generators
• System controllers/synchronizers
• Priority encoder/registers
PHILIPS
213
Product Specification
Signetics Programmable Logic Devices
PlS159A
Field-Programmable logic Sequencer (16 x 45 x 12)
FUNCTIONAL DIAGRAM
(LOGIC TERMS)
LOGIC FUNCTION
(CONTROL TERMS)
I, I I, J: I ~R
03
Q2
0'
QQ
0
tti==t=t=====t=tt=t.
STATE REGISTER
b
I 1 lot, I
b
0
0
SET C\J:Jo=
(Oa .
Ko=o
PRESENT STATE
X·1J·
8,,+1
0.'
c· ...
NEXT STATE
a, . 00)' X .1J. c ...
RESETO,:J, =0
Kp (03'0.' 0, .~) ·X·1J· C ...
HOlD 02: J2 = 0
K2 = 0
TOGGLE
Oa:
J3
=(Oa' 02' 0,
.~). X
.1J. C .. .
K3 =(03' 0.' 0, .~). X·1J·
c .. .
NOTE:
Similar logic functions are applicable for D
and T mode flip-flops.
On-<:hip TIC buffers couple either True (1,8, a)
or Complement (T, g, 0, C) input polarities to all
AN D gates, whose outputs can be optionally
linked to all OR gates. Any of the 32 AND gates
can drive bidirectional 1/0 lines (8), whose output polarity is individually programmable
through a set of Ex-OR gates for implementing
AND-OR or AND-NOR logic functions. Similarly, any of the 32 AND gates can drive the J-K
inputs of all flip-flops. There are 4 AN D gates
for the Asynchronous Preset'Reset functions.
All flip-flops are positive edge-triggered and
can be used as input, output or 1/0 (for interfacing with a bidirectional data bus) in conjunction
with load control gates (L), steering inputs (I),
(8), (a) and programmable output select lines
(E).
The PLS 159A is field-programmable, enabling
the user to quickly generate custom patterns
using standard programming equipment.
FLIP-FLOP TRUTH TABLE
OE
L
CK
P
R
J
a
K
L
X
X
L
X X X L
H
L
L
X
X
X
X
H
L
L X X H
H X X L
L
H
L
L
i
i
i
L
i
L
i
H
i
H
X i
x i
L
L
L
L
a
0
L
L
L
L
H
L
H
L
L
H
L
H
L
L
L
H
H
0
a
L
L
L
H
L
W
L
L
H
L
H
L·
x
x
X L H L
W·
X H
L· •
L
L
H
H
+10V
The programming voltage required to program
the PLS159A is higher (17.5V) than that required to program the PLS159 (14.5V). Consequently, the PLS159 programming algorithm
will not program the PLS 159A. Please exercise
caution when accessing programmer device
codes to insure that the correct algorithm is
used.
Hi~
H
L
CAUTION: PLS159A
PROGRAMMING ALGORITHM
F
L
H
NOTES:
1. Positive Logic:
J-K=To+ T, + T 2 .................. T3 ,
Tn=C· (10 ,1, .1 2 ... ). (0 0 ,
(80
a, ... ).
VIRGIN STATE
The factory shipped virgin device contains all
fusible links intact, such that:
1.
is always enabled.
or
2. Preset and Reset are always disabled.
3. All transition terms are disabled.
4. All flip-flops are in D-mode unless otherwise programmed to J-K only or J-K or D
(controlled).
5. All 8 pins are inputs and all F pins are
·8,· ... )
2. i denotes transition from Low to High level.
3. X = Don't care
4 . • = Forced at Fn pin for loading the J-K flipflop in the Input mode. The load control
term, Ln must be enabled (HIGH) and the pterms that are connected to the associated
flip-flop must be forced LOW (disabled)
during Preload.
5. At P = R = H,
= H. The final state of
depends on which is released first.
6. •• = Forced at Fn pin to load J-K flip-flop
independent of program code (Diagnostic
mode), 3-State 8 outputs.
a
a
outputs unless otherwise programmed.
May 11, 1988
214
Product Specification
Signetics Programmable Logic Devices
PLS159A
Field-Programmable Logic Sequencer (16 x 45 x 12)
FPLS LOGIC DIAGRAM
"
"
.,
~--+-------------------~~~~FO
CK
NOTES:
1. All OR gate inputs with a blown link float to logic "0",
2. All other gates and control inputs with a blown link float to logic "1".
3, aJ denotes WIRE·OR.
4.
it Programmable connection.
May 11,1988
215
<>---+------ill CK
Signetics Programmable Logic Devices
Product Specification
Field-Programmable Logic Sequencer (16 x 45 x 12)
ORDERING INFORMATION
PLS159A
THERMAL RATINGS
DESCRIPTION
TEMPERATURE
ORDER CODE
20--Pin Plastic DIP (300mil-wide)
PLS159AN
Maximum junction
lSOoC
20--Pin Plastic Leaded Chip Carrier
PLS159AA
Maximum ambient
7SoC
Allowable thermal rise
ambient to junction
75°C
ABSOLUTE MAXIMUM RATINGS1
RATINGS
SYMBOL
PARAMETER
Max
UNIT
+7
VDC
Input voltage
+5.5
VDC
VOUT
Output voltage
+5.5
VDC
liN
Input currents
+30
rnA
lOUT
Output currents
+100
rnA
TA
Operating temperature range
TSTG
Storage temperature range
Vee
Supply voltage
VIN
Min
--30
0
+75
°C
-65
+150
°C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
DC ELECTRICAL CHARACTERISTICS
O°C
:s; TA:S; +75°C, 4.75V:S; Vee:S; 5.25V
UMITS
SYMBOL
PARAMETER
TEST CONDITION
Min
Vce = Max
Vee = Min
Vee = Min, liN =-12mA
2.0
Vee = Min, IOH = -2mA
IOl = 10mA
2.4
Typ'
Max
UNIT
-0.8
0.8
-1.2
V
V
V
0.35
0.5
V
V
Input voltage2
VH-j
V IL
V<:;
High
Low
Clamp
Output voltage2
V OH
VOL
High
Low
Input current
IIH
High
Vee = Max, VIN = 5.5V
<1
80
~
III
Low
VIN = 0.45V
-10
-100
~
Output current
IO(OFF)
Hi-Z state 4, 7
Vee = Max, VOUT = 5.5V
1
80
~
VOUT = 0.45V
-1
-140
-70
~
mA
190
mA
los
Short circuit3 . 5
VOUT = OV
Icc
Vee supply current'l
Vee = Max
150
Vee = 5.0V, VIN = 2.0V
VOUT = 2.0V
8
15
-15
Capacitance
CIN
COUT
Input
Output
NOTES:
1.
2.
3.
4.
All typical values are at Vee = 5V, TA = +25°C.
All voltage values are with respect to network ground terminal.
Test one at a time.
Measured with V IH applied to OE.
5. Duration of short circuit should not exceed 1 second.
6. lee is measured with the OE input grounded, all other inputs at 4.5V and the outputs open.
7. Leakage values are a combination of input and output leakage.
May 11, 1988
216
pF
pF
Product Specification
Signetics Programmable Logic Devices
PLS159A
Field-Programmable Logic Sequencer (16 x 45 x 12)
.
AC ELECTRICAL CHARACTERISTICS o°c ~TA ~ +75°C, 4.75V~ Vee~ 5.25V,
~
SYMBOL
PARAMETER
FROM
R, =470Q, R2 = lkQ
I
I
U;JiiTS
TO
TEST CONDITION
Min
Typ'
Max
I
UNIT
Pulse width
!eKH
Clock2 High
CK+
CK~
CL = 30pF
20
15
ns
!eKL
Clock Low
CK~
CK+
CL = 30pF
20
15
ns
!eKP
Period
CK+
CK+
C L = 30pF
55
45
ns
tpRH
Preset/Reset pulse
(I,B)-
(I,B) +
CL = 30pF
35
30
ns
tIS,
Input
(I,B)±
CK+
CL = 30pF
35
30
ns
tlS2
Input (through Fn)
F±
CK+
CL = 30pF
15
10
ns
tlS3
Input (through
Complement Array)4
(I,B)±
CK+
CL = 30pF
55
45
ns
t,H'
Input
(I,B)±
CK+
CL = 30pF
0
-5
ns
tlH2
Input (through Fn)
F±
CK+
CL = 30pF
15
10
ns
Setup timeS
Hold time
Propagation delay
!eKO
Clock
CK+
F±
CL = 30pF
15
20
ns
tOE'
Output enable
OE-
F~
C L = 30pF
20
30
ns
OE+
F+
C L = 5pF
20
30
ns
B±
CL = 30pF
25
35
ns
CL = 30pF
20
30
ns
too,
Output disable3
tpo
Output
toE2
Output enable
(I,B) +
B±
to02
Output disable 3
(I,B)-
B+
CL = 5pF
20
30
ns
tpRO
Preset/Reset
(I ,B) +
F±
CL = 30pF
35
45
ns
IpPR
Power-<>n/preset
Vee +
F-
CL = 30pF
0
10
ns
(I,B)±
NOTES:
1. All typical values are at Vee = 5V, TA = +25°C.
2. To prevent spurious clocking, clock rise time (10% - 90%) ~ IOns.
3. Measured at VT = VOL + 0.5V.
4. When using the Complement Array !eKP = 75ns (min).
5. Limits are guaranteed with 12 product terms maximum connected to each sum term line.
VOLTAGE WAVEFORMS
TEST LOAD CIRCUIT
Vcc
10
<>--r-
By
I
I
BZ
BWO--Y--
FO
o--l----
Fn
BX
CKe>-----
GND
-=
MEASUREMENTS:
AH circuit delays are measured at the + 1.5V level
of irputs and outputs. unless OIherwise specified.
Input Pulses
May 11,1988
~w.a~.
R,
o---l---
In
.5V
217
or:
R2
AND JIG
CAPACITANCE
I
CL
Signaties Programmable Logic Devices
Product Specification
Field-Programmable Logic Sequencer (16 x 45 x 12)
PLS159A
TIMING DEFINITIONS
TIMING DIAGRAMS
SYMBOL
.:JV
PARAMETER
I,B
(INPUTS)
OV
tCKH
Width of input clock pulse.
tCKL
Interval between clock pulses.
.:JV
1.5V
CK
OV
tCKP
Clock period.
tpRH
Width of preset input pulse.
tlSl
Required delay between
beginning of valid input and
positive transition of clock.
tlS2
Required delay between
beginning of valid input forced
at flip-flop output pins, and
positive transition of clock.
tlHl
Required delay between
positive transition of clock and
end of valid input data.
tlH2
Required delay between
positive transition of clock and
end of valid input data forced
at flip-flop output pins.
!eKO
Delay between positive
transition of clock and when
outputs become valid (with
OELow).
tOEl
Delay between beginning of
Output Enable Low and when
outputs become valid.
t001
Delay between beginning of
Output Enable High and
when outputs are in the
OFF-State.
tpPR
Delay between Vee (after
power--<>n) and when flip-flop
outputs become preset at "1"
(internal Q outputs at "0").
tpD
Propagation delay between
combinational inputs and
outputs.
tOE2
Delay between predefined
Output Enable High, and
when combinational outputs
become valid.
1002
Delay between predefined
Output Enable Low and when
combinational outputs are in
the OFF-State.
tpRO
Delay between positive
transition of predefined
PresetiReset input, and
when flip-flop outputs
become valid.
VOH
F
(OUTPUTS)
- - VOL
.:JV
OV
Flip-Hop Outputs
+3V
~
(INPU~~
~
r---------F
f-- i--
t:-~
B
--
_-..-:r__
1.5V
(OUTPUTS)
toe.
too. -
-----------
1,8
~~T:~i _ _ _ _ _ _..J
ov
VOH
VOl
~-----------------+3V
. 1 . 5 V · · · .1.5V
OV
Gate Outputs
--------------------------------------------+5V
Vcc
~
4.5V
------------___________________________________ ov
tpPR
VOH
F
(OUTPUTS)
' - - - - - - - - - - VO\.
,.._ _ _ _ _ _ _ _ _ _ .3V
I,B
(INPUTS)
' -_ _ _ _ _ _ _ _ OV
,.._ _ _ _ .3V
1.5V
CK---------+-------'
' - _ _J
+----
Power-On Reset
May II, 1988
218
OV
Product Specification
Signetics Programmable Logic Devices
Field-Programmable Logic Sequencer (16 x 45 x 12)
TIMING DIAGRAMS (Continued)
+av
I,B
(INPUTS)
oV
+3V
CK
OV
+3V
PRESET/RESET
ov
(I, B INPUTS)
(PRESET)
Q
VOH
F
(OUTPUTS)
~
-------------'
(PRESET)
VOl
• Preset and Reset functions override Clock. However, F outputs may glitch with the first positive Clock Edge jf TIS1
cannot be guaranteed by the user.
Asynchronous Preset/Reset
+3V
I,B
1.5V
(LOAD SELECT)
-"I'.....---------------JI
1.5V
OV
+3V
OE
1.5V
,---------
OV
-,,
,-_.
--------·'1I
-+------.. . :,-------.. r--+---
F
+3V VOH
(INPUTS)
OV
• +3V
CK
~t1H1
Flip-Flop Input Mode
May 11, 1988
219
VOL
PLS159A
Product Specification
Signetics Programmable Logic Devices
PLS159A
Field-Programmable Logic Sequencer (16 x 45 x 12)
LOGIC PROGRAMMING
PLS 159A logic designs can be generated using
Signetics AMAZE PLD design software or one
of several other commercially available,
JEDEC standard PLD design software packages. Boolean and/or state equation entry is
accepted.
PLS159A logic designs can also be generated
using the program table entry format detailed
on the following pages. This program table
entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
users.
To implement the desired logic functions, the
state of each logic variable from logicequations
(I, B, 0, P, etc.) is assigned a symbol. Thesymbois for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
"AND" ARRAY - (I) , (8) , (ap)
I, B, Q
~
..
~B,Q
'
I,B,a
~'"
___
I,B,Q
(T, FC, l, P, R, Din
1
1
STATE
1
CODE
1
INAcnVE 1,2
I
0
I
~B,Q
~
(T, FC, l, P, R, Din
I
I,B,Q
I
H
~B,Q
'
~-*¢'"
___
I,B,Q
(T, FC, l, P, R, Din
CODE
STATE
.
___
I,B,Q
I
I
I,B,a
(T, FC, l, P, R, Din
CODE
STATE
I
I
l
1
STATE
I
DON'T CARE
I CODE I
I - I
"COMPLEMENT" ARRAY - (C)
~: ~: ~: [:=~:
(Tn,FC)
1
1
ACTION
INACTIVE', 3, 5
1
1
(1'", FC)
CODE
1
o
1
1
r
ACTION
GENERATE5
-I
I
CODE
A
I
"OR" ARRAY - (F-F CONTROL MODE)
FC
May 11,1988
1
ACTION
1
CODE
1
L
PROPAGATE
1
•
1
"OR" ARRAY - (an
1
1
ACTION
TRANSPARENT
1
CODE
I - l
1
=OoType)
FC
Q
Notes on following page.
(T", Fe)
(T", FC)
-I
Q
Q
CAUTION:
THE PLS159A Programming Algorithm is different from the PLS159.
220
Product Specification
Signetics Programmable Logic Devices
PLS159A
Field-Programmable Logic Sequencer (16 x 45 x 12)
"OR" ARRAY - (an
= J-K Type)
i
I
Tn
Q
Q
Q
Q
ACTION
CODE
ACTION
SET
H
RESET
"OR" ARRAY - (5 or B)
CODE
CODE
ACTION
HOLD
"EX-OR" ARRAY - (B)
-t-v-S'B
I
I
Tn STATUS
ACTIVE'
I
I
CODE
A
I
I
I
I
Tn STATUS
INACTIVE
I CODE I
I • I
I
I
POLARITY
I
LOW'
POLARITY
CODE
HIGH
H
I
"OE" ARRAY - (E)
oc~
L
I
IDLE',4
I
I
CODE
o
I
I
CODE
ACTION
I
CONTROL
I
A
En
En
En
En
ACTION
OC~* OC~*
OCD.~
I
I
I
ACTION
ENABLE4
I
I
.
CODE
I
I
I
I
ACTION
DISABLE
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate Cr. Fe, L, P, R, D)n will be unconditionally inhibited if both of the I, B, or Q links are left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn, Fe.
4. En = 0 and En = • are logically equivalent states, since both cause Fn outputs to be unconditionally enabled.
5. These states are not allowed for control gates (L, P, R, D)n due to their lack of "OR" array links.
May 11,1988
221
J
CODE
J
I - I
Signeties Programmable Logic Devices
Product Specification
PLS159A
Field-Programmable Logic Sequencer (16 x 45 x 12)
FPLS PROGRAM TABLE
- - _A!p _ _ _
INACTIVE
1.8,0
H
T. i. Q
I L
Q (PI
I
I
C
I
I
I
1,8(1).
DON'T CARE
LINACTIVE
10
GENERATE
-j- _ _
I
10
IA
;:::::::,..T :
ACTIVE
..,5?R_ _ _
A
INACTIVE.
(0:0)
0
H
I I JIK
I
I
I
I
I
TOGGLE
SET
-+- ____ ...E0!:!.!~L -
P. fI, 8 <0).
(O=-JIK)
: ::::1 LJ
-
-
I~~~II~;o?ed)
FIFMOOE
1,4,
I_IDLE
OJ
CONTROL
A
ENABLE.
I
-1
HIGH
H
lOW
l
I DISABLE
(POlo)
--
EA. 8
J
I
I
I
NOTES
1 The FPlS IS shipped With all links Intact. Thus a back·
ground 01 entnes corresponding to states of Virgin
links eXists ,n the table, shown BLANK for clarity
2 Program unused C, I, e, and bits In the AND array as
(-1_ Program unused D. S, p. and R bits ,n the OR
array as (-) or (Al. as a~pllcable
3 UriuMd Terms can be leI I blanl<.
a
4 Q {PJ and Q (N) are respectillely the present ano ne~1
I_-r:";":.:."::...O::...f.;;":.:.'O.;;"".:;oP:.:'..:O:,-_ _ _ _.-_ _ _-t
...-_ _ _ _ _ _ _....
Fir MODE
I
I
Ea
fA:
C
M
a{N)
DIP)
8(1)
3210321071543210
a{o)
7654321Q3210
0
Z
(!)
1
1i5
2
!Xl
>-
3
Q
4
W
t-
5
W
...J
[l.
#
t-
8
~
8
a:
::.i
0
()
7
•
Q
W
W
~
!Xl
0
10
...J
tZ
O
:::!:
11
!Xl
0
i=
a:
0[l.
12
Q
>- w
oo
>
a: W oo
tw () z
X ::.i
w W
oo X
a:
X
0
I
t- W ::.i
t- ~ oo
::.i
LL :::> ~ 0
()
()
Q
()
13
14
IS
18
17
18
19
20
21
I
W
~
Q
22
23
24
25
28
I
>
W
a:
27
28
2.
30
oo
31
a:
....
# # ~
W
::.i
..:
Z
a:
W
::.i
0
a: w 0LL
W
Q
a:
a: ~
w w
0 Q !Xl
w oo ::.i
:::>
oo ()
..: i= z
J:
...J
W
t- () z
oo
a: (!)
:::> :::>
()
[l.
#
Ra
w
La
!Xl
PA
...J
j5
::.i
a:
..:
g 8a:
1i5 t-
[l.
RA
LA
D3
02
01
00
PIN
May 11, 1988
-,...
Fe
t-
5
4
3
2
9
8
7
6
jOt Aj'TY
(OR)
AND
E
R
~
W
-
I
T
oo
-
•
19 18
222
17 16 15 14 13 12
-
Signefics
PLS167/A
Document No. 853-0314
ECN No.
97885
Date of Issue October 16,1989
Status
Product Specification
Field-Programmable Logic
Sequencers (14 x 48 x 6)
.,
.
~rogrammaole LOglt: U~VII".;~::'
I-
~
-.'"
PIN CONFIGURATIONS
DESCRIPTION
FEATURES
The PLS167 and PLS167A are bipolar,
Programmable Logic State machines of
the Mealy type. The Field-Programmable
Logic Sequencers (FPLS) contain logic
AND/OR gate arrays with user programmable connections which control the inputs of on--<:hip State and Output
Registers. These consist respectively of 8
Op, and 4 OF edge-triggered, clocked SIR
flip-flops, with an asynchronous Preset
Option.
• f MAX
All flip-flops are unconditionally preset to
"1" during power turn-{)n.
• 2-bit shared State/Output Register
The AND array combines 14 external
inputs, 10--13, with 8 internal inputs, P0--7 , fed
back from the State Register to form up to
48 transition terms (AND terms). In addition, Po and P, of the internal State Register are brought off--<:hipto allow extending
the Output Register to 6 bits, if so desired.
All transition terms can include True,
False, or Don't Care states of the controlling variables, and are merged in the OR
array to issue next-state and next--output
commands to their respective registers on
the Low-to-High transition of the Clock
pulse.
Both True and Complement transition
terms can be generated by optional use of
the internal variable (C) from the Complement Array. Also, if desired, the Preset
input can be converted to output-enable
function, as an additional user programmable option.
Order codes are listed in the Ordering
Information Table.
=13.9MHz - PLS167
N Package
20MHz - PLS167 A
- 20MHz clock rate - PLS167
25MHz clock rate - PLS167A
Vee
17
• Fleld-Programmable (Ni-Cr link)
18
• 14 True/Complement buffered
inputs
I•
• 48 programmable AND gates
I"
• 25 programmable OR gates
1'2
• 8-bit State Register
113
I'D
PRiOE
• 4-bit Output Register
• Transition Complement Array
GND
• Programmable Asynchronous
Preset/Output Enable
A Package
• Positive edge-triggered clock
• Power--on preset to logic "1" of all
registers
14
15
16 eK Vee 17
18
• Automatic logic "HOLD" state via
SIR flip-flops
• On--<:hip Test Array
• Power: 600mW (typ.)
• TTL compatible
• 3-State outputs
• Single +5V supply
• 24-pln DIP 300mil-wide
APPLICATIONS
• Interface protocols
• Sequence detectors
• Peripheral controllers
• Timing generators
• Sequential circuits
• Security locking systems
PHILIPS
223
Product Specification
Signetics Programmable Logic Devices
PLS167/A
Field-Programmable Logic Sequencers (14 x 48 x 6)
FUNCTIONAL DIAGRAM
1.1--"":-+-------+
PRiOE
PIN DESCRIPTION
POLARITY
PIN NO.
SYMBOL
1
CK
Clock: The Clock input to the State and Output Registers. A Low-tn) and negative
transition of clock preceding
first reliable clock pulse.
tpRS
Required delay between
negative transition of
asynchronous Preset and
negative transition of clock
preceding first reliable clock
pulse.
t'H
Required delay between
positive transition of clock and
end of valid input data.
leKO
Delay between positive
transition of clock and when
outputs become valid (with
PRI'OELow).
tOE
Delay between beginning of
Output Enable Low and when
outputs become valid.
too
Delay between beginning of
Output Enable High and
when outputs are in the
OFF-State.
tSRE
Delay between input 10
transition to Diagnostic mode
and when the outputs reflect
the contents of the State
Register.
tSRD
Delay between input 10
transition to Logic mode and
when the outputs reflect the
contents of the Output
Register.
tpR
Delay between positive
transition of Preset and when
outputs become valid at "1".
tpPR
Delay between Vee (after
power-on) and when outputs
become preset at "1".
tpRH
Width of preset input pulse.
f MAX
Maximum clock frequency.
1.5V
ov
VOH
VOl
+3V
OV
Flip-Flop Outputs
10-
13
ClK
y
.l'!\15V
---
-I~,.~
~'eKaJ ~---
'.5V~.;'-------~'
C'PR...!
l--'eKH
leKL
-ov
+3V
OV
vaH
VOL
t 'pRS
PR~-'·5V--
+3V
ov
l...-'pRH-I
Asynchronous Preset
+5V
OV
1.5V
(Fn = 1)
VOL
+3V
eLK - -
OV
--------
+3V
I~~
_______________________J
,--------~-------'ii'------
Power-On Preset
October 16, 1989
229
OV
PARAMETFR
...
.. --. -_.'
Width of input clock pulse.
Product Specification
Signetics Programmable Logic Devices
PLS167/A
Field-Programmable Logic Sequencers (14 x 48 x 6)
TIMING DIAGRAMS (Continued)
I
~~--------------------------------------------."A
1.5V
+3V
------------------------------------------------------------ ~
, , - - _ - - - - - +10V
I~-------
+3V
....-----OV
,.----~~.-------+_-------
+3V
-+_______ ov
1"-_ _ _ _
CLK --+--------'1
INTERNAL -
- - - - - - - - VOH
STATE REG.
OUTP~;
v""
_-+________-+___
oe- -----------------------------------------------------------OV
Diagnostic Output Mode
SPEED VS. "OR" LOADING
The maximum frequency at which the PLS
can be clocked while operating in sequential
mode is given by:
eo
..
.
(1IfMAX) = Icv = tIS + IcKO
This frequency depends on the number of
transition terms Tn used. Having all 48 terms
connected in the AND array does not appreciably impact performance; but the number
of terms connected to each OR line affects
tIS, due to capacitive loading. The effect of
this loading can be seen in Figure 1, showing
the variation of tlSl with the number of terms
connected per OR.
The PLS167 AC electrical characteristics
contain three limits for the parameters tlSl
and tlS2 (refer to Figure 1). The first, tiS1A is
guaranteed for a device with 48 terms connected to any OR line. tlSl Bis guaranteed for
a device with 32 terms connected to any OR
line. And tlS1C is guranteed for a device with
24 terms conntected to any OR line.
The three other entries in the AC table, tIS2A,
B, and C are corresponding 48, 32, and 24
term limits when using the on-chip ComplementArray.
The PLS167A AC electrical characteristics
contain two limits forthe parameters tlSl and
tlS2 (refer to Figure 2). The first, tiS1A is guaranteed for a device with 24 terms connected
to any OR line. ~SIB is guaranteed for a device with 16 terms connected to any OR line.
October 16, 1989
_~
30
'"
~
11I1 B ,
""C,V
V
./
V
10
8
0
"
32
24
TERMS CONNECTED/OR
. .
OPOl261S
Figure 1. PLSI67tISl vs.
TermslOR Connected
Ol
..
1/
.
A
1181 "
2
_i
""
..
30
8
,
j,....- V
1/
1/
0
8
"
24
32
TEAMS CONNECTED/OR
..
OP01251S
Figure 2, PLS167A ItSl vs.
TermslOR Connected
230
The worst case of tiS for a given application
can be determined by identifying the OR line
with the maximum number ofTnconnections.
This can be done by referring to the interconnect pattern in the PLS logic diagram, typicalIy illustrated in Figure 3, or by counting the
maximum number of "H" o,"L" entries in one
of the columns of the device Program Table .
This number plotted on the curve in Figure 1
or 2 will yield the worst case tiS and, by implication, the maximum clocking frequency for
reliable operation.
Note that for maximum speed all UNUSED
transition terms should be disconnected from
the OR array.
TRANSITION TEAMI T"
10
0
The two other entries in the AC table, tlS2 A
and B are corresponding 24 and 16 term limits when using the on-chip Complement
Array.
-@flltlfgj..
....
'--~'
'K'
AF01810S
Figure 3. Typical OR Array
Interconnect Pattern
Product Specification
Signetics Programmable Logic Devices
PLS167/A
Field-Programmable Logic Sequencers (14 x 48 x 6)
LOGIC PROGRAMMING
PRESET/UE OPTION - (PIE)
PLS167/A iogic designs (;8.(1 be 'dtllt::tcUtU
using Signetics AMAZE P LD design software
or one of several other commercially available,
JEDEC standard PLD design software packages. Boolean andlor state equation entry is
accepted.
~
PLS167/A logic designs can also be generated
using the program table entry format detailed
on the following pages. This program table
entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
users.
To implement the desired logic functions, the
state of each logic variable from logic equations
(I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
p=o
E=l
(ALWAYS
-=
~
IOE
RiOE
(PRESET
E
DISABLED)
ENABLED)
OPTION
CODE
PRESET 1
H
OPnoN
CODE
PROGRAMMING:
The PS 167/A has a power-up preset feature. This feature insures that the device will power-up
in a known state with all register elements (State and Output Register) at logic High (H). When
programming the device it is important to realize this is the initial state of the device. You must
provide a next state jump if you do not wish to use all Highs (H) as the present state.
;
,
p
1;'
p
1;'
p
1;'
p
1
"AND" ARRAY - (I), (P)
I,P
I,P
~P
r,p
Tn
I
l
STATE
INACTIVE', 2
I
I
I,P
r,p
r,p
Tn
CODE
I
STATE
0
I
I, P
r,p
Tn
Tn
STATE
STATE
I,P
DON'T CARE
"OR" ARRAY - (N), (F)
Tn
"tW' "tgo-' tgo-' "tgo-'
n,f
R
n;l
I
I
ACTION
INACTIVE 1,3
I
I
R
n;l
CODE
0
I
I
I
ACTION
SET
I
R
n;l
CODE
H
I
I
ACTION
RESET
I
R
n,1
CODE
L
I I
ACTION
NO CHANGE
I
CODE
-
I
"COMPLEMENT" ARRAY - (C)
0.: 0.: 0.: 0.:
Tn
I
l
ACTION
INACTIVE',4
I
I
CODE
0
Tn
I
I
I
I
ACTION
GENERATE
I
I
CODE
A
Tn
Tn
I
I
I
I
ACTION
PROPAGATE
I
I
CODE
•
I
I
I
I
ACTION
TRANSPARENT
I
I
CODE
-
J
I
NOTES:
1. This is the initial unprogrammed state of all links.
2. Any gate Tn will be unconditionally inhibited if both the true and complement of any input (I, P) are left intact.
3. To prevent simultaneous Set and Reset flip-flop commands, this state is not allowed for Nand F link pairs coupled to active gates Tn (see
flip-flop truth tables).
4. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn.
October 16,1989
231
Product Specification
Signetics Programmable Logic Devices
PLS167/A
Field-Programmable Logic Sequencers (14 x 48 x 6)
FPLS PROGRAM TABLE
PI!OGAAU TABLE ENTRIES
AND
INACTIVE
PIJRCIiASE ORDER "
CF(XXXX)
SlGNETICS DEVICE "
CUSTOMER SYMBOUZED PART "
GENERATE
: 0
0 A
PROPAGATE
I
.
0
0
Cn
TRANSPARENT I -
INACTIVE
o0
I, P
oH
REV
V
oL
DATE
DONTCARE 0 -
0
1
H'·
3
I
..
R
c:" 1
3
2
1
-I
0
SET
oH
RESET
o L
1
1
NO CHANGE I -
g- 81, - - 'Ti
••
·
r-----------------r------------------
1
11
•
"IS
21
22
I
I
I
I
28
27
•
•
•
29
I
•
I
•
I
··
•
48
•
•I
47
I
39
40
41
4
43
44
I
45
PIN
NO.
1
r
1
8
(;
OUTPUT (Fr)
"3 ;r,-rO•
I
I
•
I
2
0
2
1
2
2
I
·•••
2
3 2
I
I
.
·
I
1
9
L-
5" ;; "3 .Ii
·
I
I
0
·
38
------------- '7...
I
I
30
34
3S
36
37
0
NEXT STATE INs)
,
••
I
REMARKS
I
31
32
33
PIE
PRESET
H
l5i!
0 L
·
-.
•I
••
•
•
!I
I
•
I
I
~.
I
·
4
2S
-.-
~
I
T
I
I
.1. .. ,.
•
·•
·
•
23
..
~
I
·
16
17
18
19
0 "7 "6
I
•
I
I
I
12
13
. ,.
I
I
··
5
OPTION
0
"",Po
OR
PRESENT STATE (Ps)
I
6
7
8
No, F,
OPTION (PIE)
INPUT(IMl
•
•
o0
0
1
,
AND
-
INAC"IlVE
0
TOTAL NUMBER OF PARTS
PROGRAM TA8L£ "
T
E
OR
I
-------------------T-----------------0
CUSTOMER _
3
4
5
I
,
•
·
·
•
I
6
7
8
I
1
1
1
5
4
3
1
1
1
0
..
~~
!~
>
NOTES:
1. The FPlS is shipped with all links initially intact. Thus, a background of "0" for all Terms, and an "H" for the PIE option, exits in the table, shown BLANK instead for clarity.
2. Unused en, 1m, and Ps bits are normally programmed Don't Care (-).
3 Unused Transition Terms can be left for future code modification or programmed as (-) for maximum speed.
4. Letters in variable fields are used as identifiers by logic type programmers.
October 16,1989
232
9
Signetics Programmable Logic Devices
Product Specification
PLS167/A
Field-Programmable Logic Sequencers (14 x 48 x 6)
[.
TEST ARRAY
The FPLS may be subjected to AC and DC
parametric tests prior to programming via an
on-chip test array.
The array consists of test transition terms 48
and 49, factory programmed as shown below.
Testing is accomplished by clocking the FPLS
and applying the proper input sequence to
10-13 as shown in the test circuit timing diagram.
F,
State Diagram
FP LS Under Test
H
OPTlON (PIE)
T
E
R
.
C
48
4"
,,-, -
OR
AND
PRESENT STATE (Ps)
INPUT (1m)
3
2
1
1
0
A
H
H
H
H
H
•
L
L
L
L
LjLjLjLjLjLjLjLjLjL
H
H
H
H
H
H
H
H
H
OUTPUT (Fr)
NEXT STATE (Ns)
9FFTSlsFFFFT'O 11T·TsFFFTtT'O
-71•
5
4
3
2
iTo
3
2
1
0
H
L
L
L
L
L
L
L
L
L
L
L
L
LjLjLjLjLLLlL1L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Test Array Program
+5V
Vee
OV
CK
Both terms 48 and 49 must be deleted during
user programming to avoid interfering with the
desired logic function. This is accomplished
automatically by any of Signetics' qualified
programming equipment.
10-13
:--1 -----,
Fool
3V
1.5V
REGISTER~
STATE
OV
\. _ _ _ _ _ _ _ _ _ _ _ _
J
r---
HIGH
LOW
Test Circuit Timing Diagram
OPTION (PIE)
M
C
48
4"
•
-1 -1
1
-1
3
2
1
0
9TaFT.TsT4T3T 2liTii ,-161s14T,T'211T'O
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
-
PRESENT STATE (Ps)
INPUT (1m)
Test Array Deleted
October 16, 1989
H
OR
AND
T
E
R
233
NEXT STATE (Na)
OUTPUT (Fr)
7.J6JIEI31XElO ,TjE1'O
Signetics
Document No. 853-0322
ECNNo.
97853
Date of Issue October 11, 1989
Status
Product Specification
PLS168/A
Field-Programmable Logic
Sequencers (12 x 48 x 8)
Programmable Logic Devices
DESCRIPTION
FEATURES
The PLS168 and tje PLS168A are bipolar,
Programmable Logic State machines of
the Mealy type. They contain logic AND/
OR gate arrays with user programmable
connections which control the inputs of
on-<:hip State and Output Registers.
These consist respectively of 10 Qp, and
4 QF edge-triggered, clocked SIR flipflops, with an Asynchronous Preset Option.
• f MAx
PIN CONFIGURATIONS
=13_9MHz -
PLS168
20MHz - PLS168A
- 20MHz clock rate - PLS168
25MHz clock rate - PLS168A
N Package
vee
I.
• Field-Programmable (Ni-Cr link)
17
• 12 True/Complement buffered
inputs
I.
18
• 48 programmable AND gates
110
• 29 programmable OR gates
I"
All flip-flops are unconditionally preset to
"1" during power turn-111011\11101 :Hlw I... IHlH1H
L L IL:LILILIL L I. L L LTLI1.II.~LTI. TL L II. IL
0
48
NEXT STATE (Ns)
(px)
,
J
2
,
0
I.IL.II.ILII.IL 1.11.11.11. LILII.II.
~ HIHI\o\ H H \0\ tilH h·1 HhtlHIH
Test Array Program
'5V
OV
Both terms 48 and 49 must be deleted during
user programming to avoid interfering with the
desired logic function, This is accomplished
automatically by any of Signetics' qualified
programming equipment
CK
10-11
tpPR
t=
;J
15v'r"'-----".
Fo-,
~
STATE
::
r---
- - - - - "'\
REGISTER
HIGH
\.. _ _ _ _ _ _ _ _ _ _ _ _ - '
LOW
Test Circuit Timing Diagram
OPTION (P E)
AND
r
H
OR
T
E
R
M
Co
48
-IH
49
• L.
r;-r;,
0
PRESENT STATE (Ps)
INPUT (1m)
T
OuTPUT (Fn
(Px)
IPxj
"'I'" 151' 1 31'1' 10 'T'l'T6-';T'T3 'I' (0
H HIH.HIHIH IN!HIHIHIH HIHIHIH!IIIHIH IIIHlu
1. L I.!l. 1.11. 11.:1. 11.11.1'- 1.11.11.11. LILlI. 1..11.JI.
Test Array Deleted
October 11,1989
REMARKS
NEXT STATE (Ns)
244
,(, (, ( 6I sf '1 3I ' ( , 10 31'1' (0
- 1- 1- 1- 1-1- : -1-(- 1- -1-1-1
- - - - - -:-1-1-1- -1-1-1-
Signefics
Document No. 853-0862
ECN No.
93255
Date of Issue
Mayll,1988
Status
Product Specification
PLS179
Field-Programmable Logic
Sequencer (20 x 45 x 12)
I Programmable LogiC uevlces
~
DESCRIPTION
FEATURES
The PLS179 is a 3-State output, registered logic element combining ANDIOR
gate arrays with clocked J-K flip-flops.
These J-K flip-flops are dynam ically convertible to D-type via a '10Idback" inverting buffer and control gate Fc. It features
8 registered 1/0 outputs (F) in conjunction
with 4 bidirectional 1/0 lines (8). There are
8 dedicated inputs. These yield variable
1/0 gate and register configurations via
control gates (D, L) ranging from 20 inputs
to 12 outputs.
• f MAx
The ANDIOR arrays consist of 32 logic
AN 0 gates, 13 control AND gates, and 21
OR gates with fusible link connections for
programming 1/0 polarity and direction. All
AND gates are linked to 8 inputs (I), bidirectional 1/0 lines (8), internal flip-flop
outputs (Q), and Complement Array output (e). The Complement Array consists
of a NOR gate optionally linked to all AND
gates for generating and propagating
complementary AND terms.
PIN CONFIGURATIONS
=18.2MHz
N Package
- 25MHz clock rate
vcc
• Field-Programmable (Ni-Cr link)
B3
• 8 dedicated inputs
F7
• 13 control gates
F6
• 32 AND gates
FS
.21 OR gates
F4
• 45 product terms:
- 32 logic terms
- 13 control terms
F3
.4 bidirectional I/O lines
• 8 bidirectional registers
F2
F,
Fo
Bo
B•
O£
GNO
• J/K, T, or D-type flip-flops
• Asynchronous Preset/Reset
• Complement Array
A Package
12
I,
10
ClK VCCB3 F7
• Active-High or -Low outputs
NIC
• Programmable OE control
F6
• Positive edge-triggered clock
FS
• Power-on reset on flip-flop
(Fn "1")
=
F4
F3
• Input loading: -1001JA (max.)
F.
• Power dissipation: 750mW (typ.)
NIC
• TIL compatible
• 3-State outputs
Do
Fo
F,
APPLICATIONS
• Random sequential logic
• Synchronous up/down counters
• Sh ift reg isters
• Bidirectional data buffers
• Timing function generators
• System controllers/synchronizers
., Priority encoder/registers
PHILIPS
245
Product Specification
Signetics Programmable Logic Devices
PLS179
Field-Programmable Logic Sequencer (20 x 45 x 12)
FUNCTIONAL DIAGRAM
(LOGIC TERMS)
(CONTROL TERMS)
P
R
L
D
E
CK
On-·J{·1J·C ..
.
a
NOTE:
Similar logic functions are applicable for D
and T mode flip-flops.
a
THERMAL RATINGS
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE
ORDER CODE
150°C
24-Pin Plastic DIP (300mil-wide)
PLS179N
Maximum junction
28-Pin Plastic Leaded Chip Carrier
PLS179A
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
ABSOLUTE MAXIMUM RATINGSI
RATINGS
SYMBOL
PARAMETER
Max
UNIT
+7
VDC
Input voltage
+5.5
VDC
VOUT
Output voltage
+5.5
VDC
liN
Input currents
+30
mA
lOUT
Output currents
+100
mA
TA
Operating temperature range
0
+75
°C
TSTG
Storage temperature range
-65
+150
°C
Vee
Supply voltage
VIN
Min
-30
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming. specification of the device is not implied.
May 11, 1988
248
Product Specification
Signetics Programmable Logic Devices
PLS179
Field-Programmable Logic Sequencer (20 x 45 x 12)
DC ELECTRICAL CHARACTERISTICS OoC!> TA!> +75°C, 4.75V!> Vee!> 5.25V
UMITS
SYMBOL
PARAMETER
TEST CONDITION
Min
Vee = Max
Vee = Min
Vee = Min,IIN =-12mA
2.0
Vee = Min, IOH = -2mA
IOL = 10mA
2.4
Typ'
Max
UNIT
-Q.8
0.8
-1.2
V
V
V
0.35
0.5
V
V
Input voltage 2
VIH
V IL
V'C
High
Low
Clamp
Output voltage2
VOH
VOL
High
LowS
Input current
IIH
High
Vee = Max, V IN = 5.5V
<1
40
II.
Low
VIN =0.45V
-10
-100
Vee = Max, VOUT = 5.5V
1
!lA
!lA
Output current
lo(oFF)
Hi-Z state4, 7
-140
!lA
!lA
-70
mA
210
mA
80
VOUT= 0.45V
los
Short circuit3, 5
VOUT = OV
lee
Vee supply currents
Vee = Max
150
Vee = 5.0V, V IN = 2.0V
VOUT = 2.0V
8
15
-15
Capacitance
C IN
COUT
Input
Output
pF
pF
NOTES:
1.
2.
3.
4.
5.
S.
7.
All typical values are at Vee = 5V, TA = +25°C.
All voltage values are with respect to network ground terminal.
Test one at a time.
Measured with VIH applied to OE.
Duration of short circuit should not exceed 1 second.
lee is measured with the OE input grounded, all other inputs at 4.5V and the outputs open.
Leakage values are a combination of input and output leakage.
VOLTAGE WAVEFORMS
TEST LOAD CIRCUIT
vcc
By
+5V
~
NCLUDESSCOPE
R,
BZ
Fa
Fn
CKe------
'-----r----'
MEASUREMENTS:
All circuit delays are measured at the + 1.5V level
of inputs and outputs, unless otherwise specified.
Input Pulses
May 11, 1988
249
R2,::,
AND JIG
CAPACITANCE
J
CL
Product Specification
Signeties Programmable Logic Devices
PLS179
Field-Programmable Logic Sequencer (20 x 45 x 12)
AC ELECTRICAL CHARACTERISTICS R, = 4700,
SYMBOL
PARAMETER
R2
= 1kO, CL = 30pF, OoC -< TA -< +75°C, 4.7SoCV -< Vec -< 5.25V
FROM
TO
UNIT
LIMITS
TEST
CONDITION
Min 5
Typl
Max
Pulse width 3
!eKH
Clock2 High
CK+
CK-
CL = 30pF
20
15
ns
tCKL
Clock Low
CK-
CK+
CL = 30pF
20
15
ns
tCKP
Period
CK+
CK +
C L = 30pF
55
45
ns
tpRH
PresetiReset pulse
(I, B)-
(I, B) +
CL = 30pF
35
30
ns
tlSl
Input
(I, B)±
CK+
CL = 30pF
35
30
ns
tlS2
Input (through Fn)
F±
CK+
CL = 30pF
15
10
ns
!1S3
Input (through Complement Array)4
(I, B)±
CK+
CL = 30pF
55
45
ns
t'H'
Input
(I, B)±
CK +
CL = 30pF
0
-5
ns
t'H2
Input (through Fn)
F±
CK+
CL = 30pF
15
10
ns
Setup time
Hold time
Propagation delay
!eKO
Clock
CK±
F±
CL = 30pF
15
20
ns
tOE'
Output enable
lJE-
F-
CL = 30pF
20
30
ns
tOOl
Output disable3
or: +
F+
C L = 5pF
20
30
ns
tpo
Output
(I, B)±
B±
CL = 30pF
25
35
ns
IoE2
Output enable
(I, B) +
B±
CL = 30pF
20
30
ns
tOD2
Output disable3
(I, B)-
B+
C L = 5pF
20
30
ns
tpRo
PresetiReset
(I, B) +
F±
CL = 30pF
35
45
ns
F-
CL = 30pF
10
ns
tpPR
Power--{)n preset
Vcc +
NOTES:
All typical values are at Vcc = 5V, TA = +25°C.
To prevent spurious clocking, clock rise time (10% - 90%)" 10ns.
Measured at VT = VOL + 0.5V.
When using the Complement Array !eKP = 75ns (min).
5. Limits are guaranteed with 12 product terms maximum connected to each sum term line.
1.
2.
3.
4.
May 11, 1988
250
0
Product Specification
Signetics Programmable Logic Devices
PLS179
Field-Programmable Logic Sequencer (20 x 45 x 12)
I"
TIMING DIAGRAMS
TIMING DEFINITIONS
SYMBOL
+3V
I,B
(INPUTS)
OV
PARAMETER
!eKH
Width of input clock pulse.
!eKL
Interval between clock pulses.
!eKP
Clock period.
+3V
CK
1.5Y
OV
tpRH
Width of preset input pulse.
tlSI
Required delay between
beginning of valid input and
positive transition of clock.
t'S2
Required delay between
beginning of valid input forced
at flip-flop output pins, and
positive transition of clock.
t'HI
Required delay between
positive transition of clock and
end of valid input data.
t'H2
Required delay between
positive transition of clock and
end of valid input data forced
at flip-flop output pins.
!eKO
Delay between positive
transition of ciock and when
outputs become valid (with
OELow).
toEI
Delay between beginning of
Output Enable Low and when
outputs become valid.
toDI
Delay between beginning of
Output Enable High and
when outputs are in the
OFF-State.
tpPR
Delay between Vcc (after
power-on) and when flip-flop
outputs become preset at "1"
(internal Q outputs at "0").
tpD
Propagation delay between
combinational inputs and
outputs.
toE2
Delay between predefined
Output Enable High, and
when combinational Outputs
become valid.
tOO2
Delay between predefined
Output Enable Low and when
combinational Outputs are in
the OFF-State.
tpRO
Delay between positive
transition of predefined
Preset/Reset input, and when
flip-flop outputs become
valid.
VOH
F
(OUTPUTS)
VOL
+3V
OE
ov
Flip-Flop Outputs
~----------------------------------______________ +3V
(INPU~~
....I
~------.-,--~-------------------------
1:1_.S_v________Ip____
,.~~
OV
~y-------~::
~~~i~---------:E-
:
f:-~
Gate Outputs
~-----------------------------------------------------~V
vee
~
'.SV
----------------------------------------------
OV
tPPR
F
(OUTPUTS)
'-------------------VOL
,-__________________ +3V
I,B
(INPUTS)
' -__________________ OV
----------'
_ - - - - - - - +3V
1.SV
CK---------+______--'
'------'·t--------OV
Power-On Reset
May 11,1988
251
Product Specification
Signetics Programmable Logic Devices
Field-Programmable Logic Sequencer (20 x 45 x 12)
TIMING DIAGRAMS (Continued)
I,B
(INPUTS)
OV
+3V
CK
OV
+3V
PRESET/RESET
OV
(I, B INPUTS)
Q
r--(RESET)--'
F
(OUTPUTS)
-------------'
1.5V
(PRESET)
• Preset and Reset functions override Clock. However, F outputs may gl~ch w~h the first positive Clock. Edge if T'Sl
cannot be guaranteed by the user.
Asynchronous Preset/Reset
+3V
1,8
1.5V
(LOAD SELECT)
1.SV
-'I'----------------Jj1.....- - ov
+3V
1.5V
OV
-\
\
F
(INPUTS)
\
-_.
+3V VOl<
-+-------'
OV VOL
• +3V
CK
/---=----
Q
~-_
~
\_----(O'N)
Flip-FlOp Input Mode
May 11,1988
252
PLS179
Product Specification
Signetics Programmable Logic Devices
PLS179
Field-Programmable Logic Sequencer (20 x 45 x 12)
LOGIC PROGRAMMING
PLS 179 logic designs can be generated using
Signetics AMAZE PLD design software or one
of several other commercially available,
JEDEC standard PLD design software packages. Boolean and/or state equation entry is
accepted.
PLS179 logic designs can also be generated
using the program table entry format detailed
0(1 tJl...u
:: following pages. This program table
entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
users.
To implement the desired logic func~ons, the
state of each logic variable from logic equations
{!, B, 0, P, etc.) is assignAd a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
"AND" ARRAY - (I), (B), (Op)
I,B,O
~'.,
___
I, B,O
1'"
(T, FC, L, P, R, Din
L
I
STATE
INACTIVE',2
I
I
CODE
0
I
I
___
I, B, a
~~o
~~o
~~ ___
..o
I
I,B,O
COOE
I
H
o~¢'"
___
-I,B,O
(T, FC, L, II R, Din
(T, FC, L, P, R, Din
(T, Fe. L, II R, Din
STATE
~~o
I,B,O
I
I
1,8,0
I
I
CODE
STATE
I
L
I
STATE
DON'T CARE
I CODE I
I - I
"COMPLEMENT" ARRAY - (C)
4:
C:~: G~l:
(Tn.FC)
I
ACTION
I
(T .. Fc)
CODE
L INACTIVE'. 3, S I
o
-1
I
I
I
ACTION
GENERATES
I
I
COOE
I
I
I
A
"OR" ARRAY - (F-F CONTROL MODE)
I
ACTION
J-KORD
(CONTROLLED)
I
I
CODE
A
1
I
ACTION
I
J-K
PROPAGATE
(T.. FC)
I CODE I
I • I
I
I
ACTION
TRANSPARENT
I COOE I
I - I
=D-Type)
Tn
a
COOE
•
Notes on following page.
May 11.1988
ACTION
"OR" ARRAY - (an
joo°ioo°
I
C~~:
(T.. FC)
253
a
Product Specification
Signetics Programmable Logic Devices
PLS179
Field-Programmable Logic Sequencer (20 x 45 x 12)
"AND" ARRAY - (ON
=J-K Type)
Q
ACTION
CODE
ACTION
SET
H
HOLD
"OR" ARRAY - (5 or B)
~P'R'S
I '---'
I
I
I
(OR 0)
ACnVe 2
I
CODE
J
A
CODE
"EX-OR" ARRAY - (B)
~P'R'S
I '---'
Tn STATUS
Q
Q
Q
I
I
(OR 0)
I
I
Tn STATUS
INACTIVE
I
POLARITY
I
I
I
I
CODE
L
I
I
POLARITY
CODE
HIGH
H
"OE" ARRAY - (E)
~[}--t>* ~~4= oco~
En
En
I
I
ACTION
IDLE','
I
I
CODE
0
I
I
l
I
ACTION
CONTROL
I
I
CODE
A
",[}~ t>~f
En
En
I
I
I
I
ACTION
ENABLE'
I CODE I
I • I
I
I
ACTION
I
CODE
DISABLE
I
-
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate Cr. Fe, L, P, R, D)n will be unconditionally inhibited if anyone of the I, B, or Q link pairs are left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn, Fe.
a
4. En = and En = • are logically equivalent states, since both cause Fn outputs to be unconditionally enabled.
5. These states are not allowed for control gates (L, P, R, D)n due to their lack of "OR" array links.
May 11,1988
254
I
I
Product Specification
Signetics Programmable Logic Devices
PLS179
Field-Programmable Logic Sequencer (20 x 45 x 12)
FPLS PROGRAM TABLE
---~---+---~----T------~------{
IIACTIVE !AI P, R, 8 (0) I
~ 8,(1),: INACTIVE. (0 = D) I J/K
• FIF IDLE
•
L O(P) I
: JIK .. D
IAI. ~ICONTRO<. A
I
I (COOITRO'-LED)
ENABLE·
I
I
H
IIACTIV£
~ 8, 0
';11,11
•
DON'TCAR£
-
r~n
.-•
INACTM!
GENERATE
_TE
A C )I
I
i
SEf
RESET
HOLD
H
L
(0 = JIK)
-
T
E
R
"•
C/)
U
i=
C
7
I
II
I LOW
I
H_ lHI
,
•••
3
EA,8 :
~A8U-
(POL-)
L
NOlES
1. The FPLS ie Ihipped with . . linkS inlllCt. Thus
• bIckground of entrin ~ to
..... of virgin links ...... in the .....,
I
I
3. UnUMd T..... c.n be ........
'.O(p)_O(N) ...
.... _
aI ftIp4Iopo Q.
_>O/y"'_ ...
Z
(!l
iii
DR)
•
O(P)
3
1
•
4
3
2 23 14 11 10 22 21 20 19 ,. 1716 15
7 •
••
•
2
2
1
•
••
•
•
~
C
W
I-
,.
Il.
!r
8w
C
~
:t
7
,.
~
n
12
13
W
m
N
,.
~
~
z
m
:t
fr xx
::;:
a
~
c
>
w
en >
ex: iii en
w
U
W
I-
Z
w
en x a ex: :t
J: 1:5- IW ::;:
en !(
U. ~
a
u U c U
I-
,."
....
17
20
21
22
23
I ....
2'
25
27
W
!(
C
I
>
w
ex:
..
30
31
Fe
Po
R.
La
p.
RA
en
W
ex:
::;: cW
«
z aex:
ex: w
w en
:t
~
::l
u
May 11,1988
I-
ex:
~
w u.
U a w
ex: ....I
'>
w w m
m ~
c ::;:
en ~ ::;:
,. ,.
,.
LA
00
D2
D1
DO
PIN
•
8
7
••
\.1 z
« I~
W ....I (!l
:I:
~
~
Il.
Z
(!l ~ a
ex:
iii ~ Il.
255
POLA RITY
EA
E8
1
2
3
W
--
2. ProgIwn unu.-:l C, .... Mel 0 bits in 1M AND
....., .. (-I. Progqrn unUlild Q. 8, A. ... p
bit, in the OR 1mY" (-) Of (AI...
F/FMODE
ANO
8(Q
3 2 1
-
8L.ANlCtorc~
I
7
O(N)
3
•••
2
1
•
3
8(0)
2 1
•
Signefics
PLC42VA12
Document No.
ECN No.
Date of Issue January 1989
Status
Prelim inary Specification
CMOS Programmable Logic
Sequencer (42 x 105 x 12)
Programmable Logic Devices
PIN CONFIGURATIONS
DESCRIPTION
FEATURES
The new PLC42VA 12 CMOS PLD from
Signetics exhibits a unique combination of
the two architectural concepts that revolutionized the PLD marketplace.
• High-speed EPROM-based CMOS
Multi-Function PLD
- Super set of 22V10, 32VX10 and
20RA10 PAL® ICs
The Signetics unique Output Macro Cell
(OMe) embodies all the advantages and
none of the disadvantages associated
with the "V" type Output Macro Cell
devices. This new design, combined with
added functionality of two programmable
arrays, represents a significant advancement in the configurability and efficiency of
multi-function PLDs.
The most significant improvement in the
Output Macro Cell structure is the implementation of the register bypass function.
Any of the 10 J-KlD registers can be individually bypassed, thus creating a combinatorialllO path from the AND array to the
output pin. Unlike other "V" type devices,
the register in the PLC42VA 12 Macro Cell
remains fully functional as a buried register. Both the combinatorial 110 and buried
register have separate input paths (from
the AND array). In most V-type architectures, the register is lost as a resource
when the cell is configured as a combinatorial 1/0. This feature provides the capability to operate the buried register
independently from the combinatorial 110.
FA and N Packages
• Two fully programmable arrays
eliminate "P-term Depletion"
- Up to 64 P-terms per OR function
• Improved Output Macro Cell
Structure
-Individually programmable as:
* Registered Output
* Registered Input
* Combinatorial 1/0 with Buried
Register
- Bypassed Registers are 100%
functional with separate input
and feedback paths
-Individual Output Enable control
functions
* From pin or AND array
N." Plastic
FA", Ceramic with Quartz Window
• Eleven clock sources
• Register Preload and Diagnostic
Test Mode Features
A Package
• Security fuse
12
101
CLKNlC Vce Mg Ma
APPLICATIONS
M7
• Mealy or Moore State Machines
- Synchronous
- Asynchronous
MS
• Multiple, independent State
Machines
M&
Nle
M.!
M3
17
• 10-bit ripple cascade
• Sequence recognition
• Bus Protocol generation
• Industrial control
M2
Do
A = Plastic
B, GND HIC Igi
Me
M,
ot
leaded Chip Carrier
• AID Scanning
PAL is a registered trademark of Monolithic Memories, fnc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
PHILIPS
256
Signetics Programmable Logic Devices
Preliminary Specification
CMOS Programmable Logic
Sequencer (42 x 105 x 12)
PLC42VA12
FUNCTIONAL DIAGRAM
P63 • ••
Po
C
Rn
n
DBn
CKn
IgiO'E
{]
11-18
">
-- - ~
<
XB
~
!nICK
-tJ
~r----c
--l
;>
$
...
X2
X2
XB
XB
X2
X2
X2
lit
X2
XB
X2
X2
CON ROL
~
EJt7
XB
-~
J
C
K
.......
~
XB
Q
OMC
~
>-
X2
L-C~
POLARIT!:-
J'
xi"
r-
-0
V
1
M,-
Nil
l!
C:TRO
EJt7
X2
]
'p-R
J
c"
K
'J
~ I L~>Q
OMC
~C~
POLARIT~LV
POLARIT~~
January 1989
257
n=
+-
X2
':"
~Ma
-
J'>-.l
I
-B,
Signetics Programmable Logic Devices
Preliminary Specification
CMOS Programmable Logic
Sequencer (42 x 105 x 12)
PLC42VA12
LOGIC DIAGRAM
NOTE:
;F; Programmable Connection
January 1989
258
Signetics Programmable Logic Devices
Preliminary Specification
CMOS Programmable logic
Sequencer (42 x 105 x 12)
PlC42VA12
LOGIC DIAGRAM (Continued)
---r___ - - -
8]00
PLC42VA12
January 1989
259
Preliminary Specification
Signetics Programmable Logic Devices
CMOS Programmable Logic
Sequencer (42 x 105 x 12)
PLC42VA12
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
24-Pin Ceramic Dualln-Line with window,
Reprogrammable (300mil-wide)
PLC42VA 12FA
24-Pin Plastic Dual In-Line,
One Time Programmable (300mil-wide)
PLC42VA12N
28--Pin Plastic Leaded Chip Carrier,
One TIme Programmable (450mil-wide)
PLC42VAI2A
ABSOLUTE MAXIMUM RATINGS!
SYMBOL
PARAMETER
THERMAL RATINGS
TEMPERATURE
RATINGS
UNIT
-0.510 +7
Voc
Maximum junction
150°C
Vcc
Supply voltage
VIN
Input voltage
-0.5 to Vee +0.5
Voc
Maximum ambient
75°C
VOUT
Output voltage
-0.5 to Vee +0.5
Voc
75°C
liN
Input currents
Allowable thermal rise
ambient 10 junction
-10 to +10
rnA
lOUT
Output currents
+24
rnA
TA
Operating temperature range
TSTG
Storage temperature range
o to +75
°C
~51o+150
°c
NOTE:
1. Stresses above those listed may cause malfunction or perrnanentdamage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.
AC TEST CONDITIONS
41
VOLTAGE WAVEFORMS
+5V
FROM OUTPUT
(BX, FX)
UNDER TEST
1
R2
TEST POINT
CL"
"CL INCLUDES JIG AND PROBE TOTAL
CAPACITANCE
MEASUREMENTS:
All cifcun delays are measured at the + 1.5V level of inputs and outputs, unleu otherwise specified.
Tesl Load CirculI
January 1989
Inpul Pulses
260
Preliminary Specification
Signetics Programmable Logic Devices
CMOS Programmable Logic
Sequencer (42 x 105 x 12)
PLC42VA12
DC ELECTRICAL CHARACTERISTICS oOC -< TA < +75°C, 4.75V .s Vee.s 5.25V
-
UMITS
SYMBOL
PARAMETER
TEST CONDITION
Min
Typ'
Max
UNIT
Input voltage:!
VIL
Low
Vee = Min
-0.3
0.8
V
VIH
High
Vee = Max
2.0
Vee + 0.3
V
0.5
V
Output voltage:!
VOL
Low
Vee = Min
IOL = 16mA
VOH
High
IOH=~·2mA
V
2.4
Input current
IlL
Low
IIH
High
VIN=GND
-10
IJA
VIN = Vee
10
IJA
Output current
VOUT= Vee
10
VOUT= GND
-10
IJA
IJA
VOUT= GND
-130
mA
lOUT = OmA, f = 15MHz5, Vee = Max
90
mA
Hi--Z state
IO(OFF)
los
Short-circuit3· 6
lee
Vee supply current (Active)4
Capacitance
CI
Input
Vee =5V
VIN = 2.0V
12
pF
Ca
I/O
Va =2.0V
15
pF
NOTES:
1. All typical values are at Vee = 5V. TA = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Duration of short-circuit should not exceed one second. Test one at a time.
4. Tested with TIL input levels: VIL = 0.45V, VIH = 2.4V. Measured with all inputs and outputs switching.
5. Refer to Figure I, ~Iee vs Frequency (worst case). (Referenced from 15MHz)
6. Refer to Figure 2 for ~tpD vs output capacitance loading.
+.0
/
V
/
/
/
L
V
",
/
V
-. /
15
20
25
-2
30
I(MHz)
o
/
20
40
60
60
.00 .20 .40 .60 .80 20D
OUTPUT CAPACITANCE LOADING (pF)
Figure 2. ~tpD vs Output
Capacitance Loading (Typical)
Figure 1. Mcc vs Frequency
(Worst Case) (Referenced from 15MHz)
January 1989
/
/v
-.0 /
10
V
261
Preliminary Specification
Signetics Programmable Logic Devices
CMOS Programmable Logic
Sequencer (42 x 105 x 12)
PLC42VA12
AC ELECTRICAL CHARACTERISTICS O°C -< TA -< +75°C, 4.75V -< Vee < 5.25V;
-
R,
=238Q, R2 = 170Q
PLC42VA12
SYMBOL
PARAMETER
FROM
TO
TEST"
CONDITION
(C l (pF»
Min
Typl
Max
UNIT
Sel-upTime
tlSl
Input; dedicated clock
(I, B, M) +/-
CK+
50
25
ns
tlS2
Input; P-term clock
(I, B, M) +/-
(I, B, M) +/-
50
15
ns
tlS3
Preload; dedicated clock
(M) +/-
CK+
50
10
ns
tlS4
Preload; P-Ierm clock
(M) +/-
(I, B, M) +/-
50
0
ns
tlS5
Input through complement array;
dedicated clock
(I, B, M) +/-
CK+
50
50
ns
tlS6
Input through complement array;
P-term clock
(I, B, M) +/-
(I, B, M) +/-
50
40
ns
(I, B, M) +/-
(I, B, M) +/-
50
35
ns
CK+
(M)+/-
50
15
ns
Propagation Delay
tpo
Propagation Delay
tCKOl
Clock to Output; Dedicated clock
tCK02
Clock to output; P-term clock
(I, B, M) +/-
(M) +/-
50
30
ns
IcKPl
Registered operating period;
Dedicated clock
(tlSl + !eK01)
(I, B, M) +/-
(M) +/-
50
40
ns
tCKP2
Registered operating period;
P-term clock (tlS2 + !eK02)
(I, B, M) +/-
(M) +/-
50
45
ns
IcKP3
Register preload operating period;
dedicated clock
(tlS3 + !eK01)
(M) +/-
(M)+/-
50
25
ns
tCKP4
Register preload operating period;
P-term clock
(t1S4 + !eK02)
(M) +/-
(M) +/-
50
30
ns
tCKP5
Registered operating period with
complement array; dedicated
clock (tls5 + !eK01)
(I, B, M) +/-
(M) +/-
50
65
ns
!eKP6
Registered operating period with
complement array; P-term clock
(tlS6 + !eK02)
(I, B, M) +/-
(M)+/-
50
70
ns
tOEl
Output Enable; from fOE pin
/OE-
(M) +/-
50
20
ns
IoE2
Output Enable; from P- term
(I, B, M) +/-
(B, M) +/-
50
30
ns
/OE+
Outputs
disabled
5
20
ns
5
30
ns
tOOl
Output Disable; from fOE pin
tOD2
Output Disable; from P-term
(I, B, M) +/-
Outputs
disabled
tpRo
Preset to Output
(I, B, M) +/-
(M) +/-
50
30
ns
tpPR
Power--t-----------~\r~>-----~·I
OMC CONFIGURATION
CODE
OMC CONAGURATION
COMBINATORIAL OUTPUT
WITH BURIED REGISTER
(0 orJK)
REGISTERED OUTPUT
(0 or JK)
OMC Configuration Options
Each OMC can be configured as a Registered
Output with feedback, a Registered Input or a
Combinatorial 1/0 with Buried Register. Dedicated Input and dedicated 1/0 configurations are
also possible.
OMC CONAGURAllON
CODE
REGISTERED INPUT
Aor .S
LOAD CONTROL P-TERM
When the Combinatorial 110 option is selected,
(the Register Bypass option), the Buried Register remains 100% functional, with its own inputs
from the AN D array and a separate feedback
path. This unique feature is ideal for designing
any type of state machine; synchronous Mealytypes that require both Buried and Output
Registers, or asynchronous Mealy-types that
require buried registers and combinatorial output functions. Both synchronous and asynchronous Moore-type state machines can also be
easily accomodated with the flexible OMC
structure.
Notes on page 270.
January 1989
267
Note that an OMC can be configured as either
a Combinatorial 1/0 (with Buried Register) or a
Registered Output with feedback and it can still
be used as a Registered Input. By disabling the
outputs via any OE control function, the M pin
can be used as an input. When the Load
Control P-term is asserted HIGH, the register
is pre loaded from the M pin(s). When the Lc
P-term is Active-Low and the output is
enabled, the OMC will again function as configured (either a combinatorial 110 or a registered output with feedback). This feature is
suited for synchronizing input signals prior to
commencing a state sequence.
Preliminary Specification
Signetics Programmable Logic Devices
CMOS Programmable Logic
Sequencer (42 x 105 x 12)
PLC42VA12
Output Enable Control Options
OUTPUT CONTROL OPTIONS
Similar to the Clock Options, the Output Enable Control for each OMC can be connected
either to an external source (Ig/OE, pin 13) or
controlled from the AND array (P-terms DMn).
Each Output can also be permanently enabled.
OE
M
Output Enable control for the two bi---
-D--D-- -I>
...."-
~
J
Q
K
ft
Programmable connection.
October 16,1989
279
PLC415-16
Product Specification
Signetics Programmable Logic Devices
CMOS Programmable logic Sequencer
(17 x 68 x 8)
PlC415-16
DETAILS FOR PLC415-16 LOGIC DIAGRAM
TO OUTPUT
PINS
FROM OE PIN 19
OR PTERM OEA (Ft>-3)
OR OEB (F4-7)
I.
FROM INIT PIN
OR PTERM INA (P(h'l)
OR INB (P4-7)
FROMINIT PiN 19
OR PTERM INA (FIJ-.3l
OR INB (F4-7)
FROM elK1
ORCLK2
Detail A
State Registers Po - P7
TOINIT.
UNES
Detail B
Output Registers Fo - F7
'---.--L::;:.....--4----2!!!!!~----....._4:J
1,6
OElfNlT/PD!l16
(PIN 19)
TOAND-=~~~t-_ _ _ _ _ _ _ _ _ _ _ _~
ARRAY -
Detail C
Pin 19 Options: 01:, Initialization, Power Down and Input 16
FROM
AND ARRAY
P4-7 AND
F4-71N1T
P(h'l AND
F(h'lINiT
Detail D
Internal and External Initialization
October 16, 1989
FROM elKl
ORCLK2
280
Product Specification
Signetics Programmable Logic Devices
CMOS Programmable Logic Sequencer
(17x68x8)
PLC415-16
DETAILS FOR PLC415-16 LOGIC DIAGRAM (Continued)
OEB
OEA
INB
INA
P63
P62. • • P2
P1
PO
-----------------.I----------------~/
TOORARRAY
Complement Array Detail
The Complement Array is a special sequencer
feature that is often used for detecting illegal
states. Itis also ideal for generating IF-THENELSE logic statements with a minimum number
of product terms.
The concept is deceptively simple. If you subscribe to the theory that the expressions
(/A -/9 - IC) and ~) are equivalent,
you will begin to see the value ofthis single term
NOR array.
The Complement Array is a single OR gate with
inputs from the AND array. The output of the
October 16, 1989
Complement Array is invened and fed back to
the AND array (NOR). The output of the array
will be Low if anyone or more ofthe AND terms
connected to it are active (High). I!, however, all
the connected terms are inactive (Low), which
is a classic unknown state, the oulput of the
Complement Array will be High.
Consider the Product Terms A, 9 and 0 that
represent defined states. They are also connected to the input of the Complement Array.
When the condition (not A and not 9 and not D)
exists, the Complement Array will detect this
and propagate an Active-High signal to the
281
AND array. This signal can be connected to
Product Term E, which could be used in tum to
resetthe state machine to a known state. Without the Complement Array, one would have to
generate product terms for all unknown or illegal states. With very complex state machines,
this approach can be prohibitive, both in terms
of time and wasted resources.
Note that the PLC415-16 has 2 Complement
Arrays which allow the user to design 2 independentComplementfunctions. This is particularly useful i! 2 independent state machines
have been implemented on one device.
Product Specification
Signetics Programmable Logic Devices
CMOS Programmable Logic Sequencer
(17 x 68 x 8)
PLC415-16
ORDERING INFORMATION
OPERATING
FREQUENCY
ORDER CODE
28-Pin Ceramic DIP with window;
Reprogrammable (600mil-wide)
fMAX= 16MHz
PLC415-16FA
28-Pin Plastic DIP;
One-lime Programmable (600mil-wide)
fMAX= 16MHz
PLC415-16N
28-Pin Plastic Leaded Chip Carrier;
One-lime Programmable (450mil-wide)
fMAX= 16MHz
PLC415-16A
DESCRIPTION
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
RATINGS
UNIT
+7
Voc
Vee
Supply voltage
VIN
Input voltage
+5.5
Voc
VOUT
Output voltage
+5.5
Voc
liN
Input currents
~Oto+30
mA
lOUT
Output currents
+100
mA
TA
Operating tamperature range
o to +75
TSTG
Storage tamperature range
°c
°c
-65 to +150
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicatad in the operational and programming specification of the device is not implied.
October 16, 1989
282
Product Specification
Signetics Programmable Logic Devices
CMOS Programmable Logic Sequencer
(17x68x8)
PLC415-16
DC ELECTRICAL CHARACTERISTICS O°C.,; T A .,; +75°C, 4.75.,; Vee.,; 5.25V
SYMBOL
I
Input voltage 2
_...... -
IIUIT~
I
I
PARAMETER
TEST CONDITION
V IL
Low
Vcc~
V IH
High
Vee~ MAX
Min
MIN
Typl
J
Max
UNIT
-0.3
0.8
V
2.0
Vee + 0.3
V
0.5
V
Output vOltage2
VOL
Low
V OH
High
Vee ~ MIN
IOL ~ 16mA
10H
~-3.2mA
V
2.4
Input current
IlL
Low
VIN ~ GND
-10
~
IIH
High
VIN ~ Vee
10
~
VOUT ~ Vee
VOUT~ GND
10
-10
~
~
~
-130
mA
Output current
10(OFF)
Hi-Z state
los
Short-circuit 3, 6
leesB
Vee supply current with PD
asserted?
Icc
Vee supply current Active
VOUT
GND
Vee ~ MAX
VIN ~ 0 or Vee
I
lOUT ~ OmA
4, 5
Vee~
(TTL or CMOS Inputs)
atl
I
MAX
50
~
atl~
100
~
lMHz
55
mA
MAX
80
mA
Capacitance
CI
Input
Vee ~ 5V
VIN = 2.OV
CB
1/0
VB
~
2.OV
12
pF
15
pF
NOTES:
1.
2.
3.
4.
5.
All typical values are at Vee ~ 5V. TA ~ +25°C.
All voltage values are with respect to network ground terminal.
Duration 01 short-circuit should not exceed one second. Test one at a time.
Tested with TTL input levels: VIL ~ 0.45V, VIH ~ 2.4V. Measured with all inputs and outputs switching.
Reier to Figure 1, Icc vs Frequency (worst case).
6. Reier to Figure 2 lor ,',.tpo vs output capacitance loading.
7. The outputs are automatically 3-Stated when the device is in the Power Down mode. To achieve the lowest possible current, the inputs and
clocks should be at CMOS static levels.
80
70
60
V V
......
7
V V
6
50
"..9
.,.,-
5
4
i
§. 40
'0
./
3
,,/'"
~ 2
(,)
-r- 10
I
I
I
I
.,..l.....
FO
DUT
F7
ov
T
1-
R2
=
"5
0 - - CK
-~
..sV
VCC
INlTiOE ----0
GND
~
I
~ L~ tFJ ~O%
2.5no
2.5no
2.5no
2.5".
cL
(INCLUDES
SCOPE AND JIG
CAPACITANCE)
MEASUREMENTS:
All circuit delays are IT'I98.Sured at the + 1.SV level of
inputs and outputs, unless otherwise specHied.
Input Pulses
LOGIC PROGRAMMING
PLC415-16 logic designs can be generated
using Signetics AMAZE design software or
several other commercially available, JEDEC
standard PLD design software packages.
Boolean andlor state equation entry format is
accepted. Schematic capture entry formats are
also supported.
PLC415-16 logic designs can also be generated using the program table format detailed on
the following page(s). This Program Table
Entry format (PTE) is supported by the
Signetics AMAZE PLD design software.
AMAZE is available free of charge to qualified
users.
To implement the desired logic functions, each
logic variable (I, B, P, S, T, etc.) from the logic
equations if assigned a symbol. TRUE,
COMPLEMENT, PRESET, RESET, OUTPUT
ENABLE,INACTIVE, etc., symbols are defined
below.
INITIALIZATION (PRESET/RESET)11 OPTION - (P/R)
ACTION
CODE
H
i
"
'
p
1i
'
P
1
p
1
"AND" ARRAY - (I), (P)
~P
I,P
I,P
r, Ii
Tn
STATE
Tn
1~p
r, Ii
Tn'
STATE
STATE
I,P
i,p
Notes are on page 291.
October 16,1989
I,P
r, Ii
~ Ii
289
Tn
I
STATE
Signeties Programmable Logic Devices
Product Specification
CMOS Programmable Logic Sequencer
PLC415-16
(17x68x8)
LOGIC PROGRAMMING (Continued)
PIN 19 FUNCTION: POWER DOWN, INIiTALIZATION, UE, OR INPUT
Power Down Mode
P-Term Initialization Control
FROM AND ARRAY
~IITiOE FUSE)
(PO FUSE)
~-,-
F~~~
~~~.~~
-..1
FROM PIN 19
"="
INiT DISABLED
FROM PIN 19
":'
-
TO REGISTERS
PIN 19
INTERNAL INiT FUSE
116 DISABLED
I
I
POWER DOWN FUSE
PIN 19 AS POWER DOWN
I EXTERNAL INiTiOE FUSE
I EXTERNAL IIiTiOE DISABLED
I
I
I
I
CODE
~
CODE
L
':'
l
I
I
I
I
INTERNAL lilT FUSES
I
P-TERMIIiT CONTROL
II
External Initialization Control
(PD FUSE)
II
CODE
H7,8
CODE
HORL
I
I
J
J
FROM AND ARRAY
FR~A~~~
~-5=M~
-.
I
I
P-Term OE Control
OIiTiOE FUSE)
~-~~
FROM PIN 18
lilT CONTROL
FROM PIN 19
POWER DOWN FUSE
POWER DOWN ENABLED OR
DISABLED
INiT DISABLED
FROM PIN 19
PIN 19
CONTROL
116 DISABLED
INTERNAL OE FUSE
':'
I
I
I
I
I
PDFUSE
POWER DOWN DISABLED
EXTERNAL IIiTiOE FUSE
PIN 19 AS EXTERNAL INiT
INTERNAL INiT FUSES
P-TERMINIT ACTIVE OR
INACTIVE
I
CODE
I
I
CODE
I
CODE
Ll
Ll
I
I
I
I
P-TERM OE CONTROL
I
H"o
I
I
POWER DOWN FUSE
I
CODE
I
,aI
HORL7
(INITiOE FUSE)
F~A~:t;~
~:~M_
FROM PIN 19
"="
INiT DISABLED
FROM PIN 19
116 DISABLED
':"
PIN 19
-..1
PDFUSE
I
I
CODE
POWER DOWN DISABLED
I
EXTERIIAL INiTiOE FUSE
I
CODE
I
L
PIN 19 AS EXTERNAL OE
I
H
I
INTERNAL INiT FUSES
I
CODE
I
P-TERM OE ACTIVE OR
INACTIVE
I
I
I
I
I
,al
HORL7
Notes are on page 291 ,
October 16, 1989
~
I
I
External Output Enable Control
(PO FUSE)
OE DISABLED
FROM PIN 18
290
INTERNAL OE FUSES
POWER DOWN ENABLED OR
DISABLED
I
CODE
HORL
J
I
J
I
Signetics Programmable Logic Devices
Product Specification
CMOS Programmable Logic Sequencer
(17x68x8)
PLC415-16
LOGIC PROGRAMMING (Continued)
"OR" ARRAY - J-K FUNCTION - (N), (F)
"'±g[J "'±g[J "'±g[J "'±g[J
lO'
I
lO'
K
ACTION
I
TOGGLE 2
CODE
0
I I
lO'
K
ACTION
I
SET
CODE
H
I
I
N;""F
K
ACTION
RESET
I
CODE
L
I
I
K
ACTION
DON'TCARE
I
CODE
-
I
"COMPLEMENT" ARRAY - (C)
Gl: Gl: Gl: Gl:
Tn
I
L
ACTION
INACTIVE', 3
I
0
Tn
Tn
CODE
I
I
ACTION
GENERATE
I
CODE
A
I
I
I
ACTION
PROPAGATE
J
I
CODE
•
Tn
J
I
CODE
ACTION
I
TRANSPARENT
I
-
J
CLOCK OPTION - (CLK1/CLK2)
CLK2
CLK2
CLK'
CLK,
OPTION
CLK, ONLY'
CODE
I
OPTION
CODE
H
NOTES:
1. This is the initial unprogrammed state of all links.
2. Any gate Tn will be unconditionally inhibited if anyone of its I or P link pairs is left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn.
4. These states are not allowed when using PRESET/RESET option.
5. Input buffer 15 must be deleted from the AND array (Le., all fuse locations "Don't Care") when using second clock option.
6. When using Power Down feature, INPUT 16 is automatically disabled via the design software.
7. If the internal (P-term) control fuse for IN IT andlor OE is programmed as Active High, the associated External Control function will be permanently disabled, regardless of the state of the ExternallNITIOE fuse.
8. One internal control fuse exists for each group of 8 registers. Po _ 3 and Fo _ 3 are banked together in one group, as are p. _ 7 and F. _ 7·
Control can be split between the INIT/OE pin (Pin 19) and P-terms INA, INB, OEA and OEB.
9. The PLC415-16 also has a power-up preset feature. This feature insures that the device will power-up in a known state with all register
elements (State and Output Register) at a logic High (H). When programming the device it is important to realize this is the initial state of the
devige. You must provide a next state jump if you do not wish to use all Highs (H) as the present state.
1O. L = cell unprogrammed.
H = cell programmed.
11. Inputs 10, 11 and 12 (pins 25, 24, & 23) can be used for supervoltage diagnostic mode tests. It is recommended that these inputs D.Ql be
connected to product terms INA, INB, OEA or OEB if you intend to make use of the diagnostic modes due to the fact that the patterns
associated with the internallNIT and OE control product terms may interfere with the diagnostic mode data loading and reading.
October 16, 1989
291
Product Specification
Signetics Programmable Logic Devices
CMOS Programmable Logic Sequencer
(17x68x8)
PLC415-16
PROGRAM TABLE
AND
(1m, Po)
INACTIVE
0
H
I,P
I,P
L
DON'T CARE
INACTIVE
GENERATE
PROPAGATE
TRANSPARENT
OPTIONS
OR (Ns, Fn)
(Cn)
0
A
TOGGLE
SET
•
RESET
0
EXTERNAL INIT
H
EXTERNAL OE
POWER DOWN
H
INITIALIZATION
H
ENABLED
PRESET
POWER DOWN
NO CHANGE
INITfOE
ENABLED
INTERNAL
INIT/OE
H
RESET
DISABLED
INTERNAL
NOINIT
INDETERMINATE 0
H
CLOCK 1 ONLY
L
CLOCK 1 AND 2
I HI
DISABLED
INITIALIZATION
DR
AND
INPUT (1m)
:~:::# C1 CO 116115114113112111 110 19
PRESENT STATE (Ps)
18 17 16 15 14 13 12
11
10 P7 P6 P5 P4 P3 P2 P1 PO
NEXT STATE INs)
OUTPUT IFn)
N7 N6 N5 N4 N3 N2 N1 NO F7 F6 F5 F4 F3 F2 Fl FO
o
"
11
12
13
14
15
,.
17
18
19
,.
W
::;
«Z
Z
I()
W
....,
cr:
a.
0
0
W
Cii
!;;: ;;;
W
0
a:
21
22
23
24
25
26
27
28
2'
30
31
32
33
34
35
3.
37
38
39
40
41
42
43
44
45
46
47
46
4.
50
51
52
53
54
W
"" ""a:
a:
I-
::;
I-
a:
if. if.a:
«
z
W
CfJ
::;
0
U
'::::>
'NA
A
Z
ICfJ
Cii
U
PIN NO.
.'N
"
20
2122 2324 25 26 272
3
4
5
•
7
0
10 11 12 13 1516 17 18
9
LABELS
NOTES:
In the unprogrammed state all cells are conducting. Thus, the program table for an unprogrammed device would contain "0"8 for all product terms (Inactive) and
Inhlafization states (indeterminate). The default or u~rogranmed state of all other options Is "l-,
2. Unused Cn, 1m and Ps cells are normally programmed as Don' Care (-).
3. Unused product terms can be left blank (Inactive) for future code modification.
1~
October 16, 1989
292
Signetics Programmable Logic Devices
Product Specification
CMOS Programmable Logic Sequencer
(17x68x8)
PLC415-16
,-
ERASURE CHARACTERISTICS
(For Quartz Window Packages
Only)
The erasure characteristics of the PLC415
Series devices are such that erasure begins to
occur upon exposure to light with wavelengths
shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps has wavelengths in
the3000-400oA range. Data shows that constant exposure to room level fluorescent
lighting could erase a typical PLC415 in
approximately three years, while it would take
October 16, 1989
approximately one week to cause erasure
when exposed to direct sunlight. If the PLC415
is to be exposed to these types of lighting conditions for extended periods of time, opaque
labels should be placed over the window to
prevent unintentional erasure.
The recommended erasure procedure for the
PLC415 is exposure to shortwave ultraviolet
light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UVintensity X exposure time) for erasure should be a
minimum of 15Wsec/cm2. The erasure time
with this dosage is approximately 30 to 35
293
minutes using an ultraviolet lamp with a
12,OOO~W/cm2 power rating. The device
shouk{be placed within one inch of the lamp
tubes during erasure. The maximum integrated
dose a CMOS EPLD can be exposed to without
damage is 7258Wsec/crn 2 (1 week @
12000~W/cm2), Exposure of these CMOS
EPLDs to high intensity UV light for longer
periods may cause permanent damage.
The maximum number of guaranteed erasel
write cycles is 50. Data retention exceeds 20
years.
Signetics
Document No. 853-0310
ECN No.
97888
Date of Issue October 16, 1989
Status
Product Specification
PLS105/A
Field-Programmable Logic
Sequencers (16 x 48 x 8)
Programmable Logic Devices
DESCRIPTION
The PLS 105and the PLS1 OSA are bipolar
Programmable Logic State machines of
the Mealy type. They contain logic ANDOR gate arrays with user programmable
connections which control the inputs of
on-chip State and Output Registers.
These consist respectively of 6 Op, and 8
OF edge-triggered, clocked SIR flip-flops,
w~h an Asynchronous Preset option. all
flip-flops are uncond~ionally preset to "1"
during power turn on.
The AND array combines 16 external inputs 10 -1 15 w~h six internal inputs PO- 5,
which are fed back from the State Registers to form up to 48 transition terms (AND
terms). All transition terms can include
True, False, or Don't Care stales of the
controlling variables, and are merged in
the OR array to issue next-state and
next-outputcommandsto their respective
registers on the Low-te-High transition of
the Clock pulse. Both True and Complement trans~ion terms can be generated by
optional use of the internal input variable
(C) from the Complement Array. Also, if
desired, the Preset input can be converted
to Output FrlciDIe function, as an additional
user-programmable option.
Order codes are listed in the Ordering
Information Table.
PIN CONFIGURATIONS
FEATURES
• PLS105 f MAx =13.9MHz
- 20MHz clock rate
N Package
• PLS105A fMAX =20MHz
- 25MHz clock rate
• Field-Programmable (NI-Cr link)
.16 Input variables
• 8 output functions
• 48 transition terms
• 6-bit State Register
• S-bit Output Register
• Transition complement array
• Positive edge-triggered clocked
flip-flops
• Programmable Asynchronous
Preset or Output Enable
• Power-on preset to all "1" of
Internal registers
• Power dissipation: 600mW (typ.)
A Package
• TTL compatible
• Single +5V supply
• 3-State outputs
APPLICATIONS
• Interface protocols
• Sequence detectors
• Peripheral controllers
• Timing generators
• Sequential circuits
• Elevator controllers
• Security locking systems
• Counters
• Shift registers
PHILIPS
294
Product Specification
Signetics Programmable Logic Devices
Field-Programmable logic Sequencers (16 x 48 x 8)
PlS10S/A
FUNCTIONAL DIAGRAM
LOGIC TEAMS
'M
PRRiE
T 47 - - - - - - - - -
To
CK
PIN DESCRIPTION
PIN NO,
SYMBOL
1
CK
Clock: The Clock input to the State and Output Registers. A Low-ta-High transition on
this line is necessary to update the contents of both registers.
Active-High
2-8
20-27
1,-1,5
Logic Inputs: The 15 external inputs to the AND array used to program jump conditions
between machine states, as determined by a given logic sequence.
Active-High/Low
9
10
Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when
exercised with standard TTL levels. When 10 is held at + 1OV, device outputs Fo _ 5 reflect
the contents of State Register bits Po - 5. The contents each Output Register remains
unaltered.
Active-High/Low
10-13
15-18
FO-7
19
PRiOE
October 16, 1989
NAME AND FUNCTION
Logic/Diagnostic Outputs: Eight device outputs which normally reflect the contents of
Output Register bits 0 0-7, when enabled. When 10 is held at + 10V, FO-5 =(P0-5), and
F6,7 = Logic "1".
POLARITY
Active-High
Preset or Output 'Eii3IiIe Input: A user programmable function:
• Preset: Provides an Asynchronous Preset to logic "1" of all State and Output Register
bits. Preset overrides Clock, and when held High, clocking is inhibited and Fo _ 7 are High.
Normal clocking resumes with the first full clock pulse following a High-ta-Low clock transition, after Preset goes Low.
Active-High (H)
• Output 'Eii3IiIe: Provides an Output Enable function to all output buffers Fo _ 7 from the
Output Register.
Active-Low (L)
295
Product Specification
Signetics Programmable Logic Devices
Field-Programmable Logic Sequencers (16 x 48 x 8)
PLS10S/A
FPLS LOGIC DIAGRAM
'0
F,
-o+fSa1-+---<>-ho "
CK
NOTES:
1. All AND gate inputs with a blown link float to a logic" 1"
2. All OR gate inputs with a blown fuse float to logic "0".
3. ~
Programmable connection
October 16, 1989
296
Product Specification
Signetics Programmable Logic Devices
PLS10S/A
Field-Programmable Logic Sequencers (16 x 48 x 8)
TRUTH TABLE 1, 2, 3, 4, 5, 6
LOGIC FUNCTION
,
Vcc
PR
.
.
OE
H
L
L
i
X
F
10
CK
S
R
Q p1F
X
X
X
X
X
X
H
H
+10V
X
X
X
an
an
(OP)n
(OF)n
X
X
X
X
X
X
X
X
X
an
an
an
(OP)n
(OF)n
L
L
an
(OF)n
L
H
L
L
H
L
H
H
H
H
IND.
IND.
X
X
H
X
+SV
I
I
I
OPTION
H
L
L
+10V
L
X
L
X
L
X
L
X
t
i
i
i
X
X
X
X
Hi-Z
NOTES:
1. Positive Logic:
S/R=To +T,+T2 +.
+T47
Tn = C(lo 1,1 2 , .. ) (PO P, ... P5)
2. Either Preset (Active-High) or Output Ena1ll8 (Active-Low) are available, but not both. The
desired function is a user-programmable option.
3. i denotes transition from Low-to--High level.
4. R = S = High is an illegal input condition.
S. ·=HorLor+10V.
6. X = Don't Care (,;S.SV).
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
2B-Pin Plastic DIP (600mil-wide)
PLS105N, PLS105AN
2B-Pin Plastic Leaded Chip Carrier
PLS105A,PLS10SAA
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
Min
7SoC
Allowable thermal rise
ambient to junction
75 D C
Output voltage
+S.5
VDC
TSTG
-30
+30
mA
+100
mA
0
+75
DC
-{i5
+1S0
DC
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
October 16, 1989
VIRGIN STATE
The factory shipped virgin device contains all
fusible links intact, such that:
1. pRIDE option is setto PRo Thus, all outputs
will be at"1 ", as preset by initial power-up
procedure.
2. All transition terms are disabled (0).
3. All SIR fliiTflop inputs are disabled (0).
4. The device can be clocked via a Test
Array pre-programmed with a standard
test pattern.
NOTE: The Test Array pattern MUST be
deleted before incorporating a user program. This is accomplished automatically
by any Signetics qualified programming
eqUipment.
Maximum ambient
VOUT
Storage temperature range
c ...
VDC
VDC
Operating temperature range
Rp102' 0, '(0) ·]i·IJ·
+7
+S.S
TA
RESET Q1: 51 = 0
TEMPERATURE
Input voltage
Input currents
=102 . 0, '(0) ·]i·IJ· C ...
Ro= 0
Maximum junction
VIN
Output currents
SET Oo'So
NEXT STATE
UNIT
Supply voltage
liN
0
Max
Vee
lOUT
I lot, I s,,+,
PRESENT STATE
X· B· C· •..
THERMAL RATINGS
RATINGS
SYMBOL
I~21 ~' § I ~R
STATE REGISTER
297
150 D C
Product Specification
Signetics Programmable Logic Devices
PLS10S/A
Field-Programmable Logic Sequencers (16 x 48 x 8)
DC ELECTRICAL CHARACTERISTICS
DOC $ TA $ +75°C, 4.75V $ Vee $ 5.25V
LIMITS
PARAMETER
SYMBOL
TEST CONDITION
Min
Vcc = Max
Vee = Min
Vee = Min, liN = -12mA
2.0
Typl
Max
UNIT
-0.8
0.8
-1.2
V
V
V
0.35
0.45
V
V
Input voltage2
VIH
VIL
Vc
High
Low
Clamp3
Output voltage2
VOH
VOL
High4
LowS
Vee = Min
IOH =-2mA
IOL = 9.6mA
2.4
Input current
IIH
High
VIN = 5.5V
<1
25
IlL
Low
VIN = 0.45V
-10
-100
IlL
Low (CK input)
VIN = 0.45V
-50
-250
iJ.A
iJ.A
iJ.A
Output current
Vee = Max
IO(OFF)
Hi-Z stateS
VOUT = 5.5V
1
40
VOUT = 0.45V
-1
-40
iJ.A
iJ.A
-70
mA
180
mA
los
Short circuit3 , 7
VOUT = OV
Icc
Vee supply currentS
Vee = Max
120
Vee = 5.0V
VIN = 2.0V
VOUT = 2.0V
10
-15
Capacitance6
CIN
COUT
Input
Output
8
pF
pF
NOTES:
1.
2,
3.
4.
5.
All typical values are at Vee = 5V, TA = +25°C.
All voltage values are with respect to network ground terminal.
Test one at a time.
Measured with VIL applied to OE and a logic high stored, or with VIH applied to PRo
Measured with a programmed logic condition for which the output is at a low logic level, and VIL applied to PRIOE Output sink current is
supplied through a resistor to Vee.
6. Measured with VIH applied to PRIOE.
7. Duration of short circuit should not exceed 1 second.
8. Icc is measured with the PRIOE input grounded, all other inputs at 4.5V and the outputs open.
October 16, 1989
298
Product Specification
Signetics Programmable Logic Devices
PLS10S/A
Field-Programmable Logic Sequencers (16 x 48 x 8)
AC ELECTRICAL CHARACTERISTICS R, = 4700 R2 = 1kO, CL =30pF, OoC -< TA -< +75°C, 4.75V -
--~:lf
CL
(INCLUDES
SCOPE AND JIG
CAPACITANCE)
MEASUREMENTS:
All circuit delays are measured at the + 1.5V level of
ifl)uts and outputs, unless otherwise specified.
Input Pulses
October 16, 1989
299
Product Specification
Signetics Programmable Logic Devices
PLS105/A
Field-Programmable Logic Sequencers (16 x 48 x 8)
TIMING DIAGRAMS
TIMING DEFINITIONS
SYMBOL
PARAMETER
+3V
10-,5
tCKH
OV
+3V
elK
tCKL
Interval between clock pulses.
tCKP'
Clock period -- when not
using Complement array.
tiS'
Required delay between
beginning of valid input and
positive transition of clock.
tcKP2
Clock period - when using
Complement array.
tlS2
Required delay between
beginning of valid input and
positive transition of Clock,
when using optional
Complement Array (two
passes necessary through the
AND array).
tvs
Required delay between Vcc
(after power-<>n) and negative
transition of Clock preceding
first reliable clock pulse.
tpAS
Required delay between
negative transition of
Asynchronous Preset and
negative transition of Clock
preceding first reliable clock
pulse.
tlH
Required delay between
positive transition of Clock
and end of valid input data.
tcKO
Delay between positive
transition of clock and when
outputs become valid (with
PRIOELow).
tOE
Delay between beginning of
Output Enable Low and when
outputs become valid.
taD
Delay between beginning of
Output Enable High and
when outputs are in the
OFF-State.
tSAE
Delay between input 10
transition to Diagnostic mode
and when the outputs reflect
the contents of the State
Register
tSRD
Delay between input 10
transition to Logic mode and
when the outputs reflect the
contents of the Output
Register.
tpR
Delay between positive
transition of Preset and when
outputs become valid at "1".
IpPR
Delay between Vee (after
power-on) and when outputs
become preset at "1-.
tpRH
Width of preset input pulse.
fMAX
Maximum clock frequency.
1,5V
-+-----'
oV
VOH
F0-7
VOL
+3V
oV
Sequential Mode
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ +3V
'0.,5 ~_'_.5_V________
OV
Asynchronous Preset
r---------------------------------- .5V
Vee
~_4_.5_V
____________________________________________
i-'PPR-I
F07
aI
'5V\ -I~'::I-- VOH
[F n l=l
.'5V
~
1
OV
~I"ICKO"
\
.
VOL
I CKP ________
,,~
II______ ~5~/1-.eKH-11'5v
1'5v
Width of input clock pulse.
clK _ _
.•
t vS
..
'_.5_V-'X
10-15 _ _ _ _ _ _ _ _ _ _ _
~ "s
E
-I-',H-I
I
Power-On Preset
October 16, 1989
300
::V
Product Specification
Signetics Programmable Logic Devices
PLS105/A
Field-Programmable Logic Sequencers (16 x 48 x 8)
I'
I
TIMING DIAGRAMS (Continued)
1.-.5
--v
+3V
OV
-A...._.5_V_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
r---- ---"\.-------
'0
=:}_--------1'.,.
.
-I
5V
I
-...:-----'1
'IH
J
+ .OV
"\ 8.0V
."'\------ +3V
'.5V
_
1
'. . . .-----
OV
J)'-----+------
r-"--'--:-'------.!...------
'.5V
+3V
'.5V
I
~::TEE:~~ --I--;sl--I--X-I----;N~- --1--------eLK
1-
B.OY
,'S - - - , - 'CKH
0-5 - - - - - - - - - - -
:
FO_ 5
Oe
I
(Fnl
:
OV
I
VOH
I -------------------
••5V*
t-'cKo~1
VOL
~E~ EE:·~H
VOL
-1--------------------
OV
Diagnostic Mode
SPEED VS "OR" LOADING
.
The maximum frequency at which the PLS
can be clocked while operating in sequential
mode is given by:
(lIfMAX) = ley = tIS + IeKO
This frequency depends on the number of
transition terms Tn used. Having all 48 terms
connected in the AND array does not appreciably impact performance; but the number
of terms connected to each OR line affects
tIS, due to capacitive loading. The effect of
this loading can be seen in Figure 1, showing
the variation of t'Sl with the number of terms
connected per OR.
The PLS105 AC electrical characteristics
contain three limits for the parameters t'Sl
and tlS2 (refer to Figure 1). The first, t'S1A is
guaranteed for a device with 48 terms eonnected to any OR line. tlS1B is guaranteed for
a device with 32 terms connected to any OR
line. And tiS lC is guranteed for a device with
24 terms conntected to any OR line.
The three other entries in the AC table, t'S2 A,
B, and C are corresponding 48, 32, and 24
term limits when using the on-chip ComplementArray.
The PLS105A AC electrical characteristics
contain two limits for the parameters t'Sl and
tlS2 (refer to Figure 2). The first, ~SlA is guaranteed for a device with 24 terms connected
to any OR line. t'S1B is guaranteed for a device with 16 terms connected to any OR line.
October 16, 1989
•
~
~
..
..
30
IIS1 C ,
y
""."
,/
~
./
20
10
•
0
16
"
24
TERMS CONNECTED/OR
.. ..
OP01261S
Figure 1. PLS105 tiS' vs.
Terms/OR Connected
..
.
.
"S1B~
!
_is
30
20
k-'" V
1/
/
0
•
2.
18
32
TERMS CONNECTED/OR
..
0P012S1S
Figure 2. PLS1D5A 1is. vs.
Terms/OR Connected
301
This number plotted on the curve in Figure 1
or 2 will yield the worst case tiS and, by implication, the maximum clocking frequency for
reliable operation.
TlIANSlTION TEAMS Tn
10
0
The worst case of tiS for a given application
can be determined by identifying the OR line
with the maximum number ofT nconnections.
This can be done by referring to the interconnectpattern in the PLS logic diagram, typicalIy illustrated in Figure 3, or by counting the
maximum number of "H" or"L" entries in one
of the columns of the device Program Table .
Note that for maximum speed all UNUSED
transition terms should be disconnectedfrom
the OR array.
/
QS1 A ,
The two other entries in the AC table, t'S2 A
and B are corresponding 24 and 16 term
limits when using the on-chip Complement
Array.
-tfltttfgj",
'K'
AF01610S
Figure 3. Typical OR Array
Interconnect Pattern
Product Specification
Signetics Programmable Logic Devices
PlS105/A
Field-Programmable logic Sequencers (16 x 48 x 8)
PRESET/OE OPTION - (PIE)
LOGIC PROGRAMMING
PLS10S/A logic designs can be generated
using Signetics AMAZE PLD design software
or one of several other commercially available,
JEDEC standard PLD design software packages. Boolean and/or state equation entry is
accepted.
PLS1 aSIA logic designs can also be generated
using the program table entry format detailed
on the following pages. This program table
entry format is supported by the Signetics
AMAZE PLD design software (PTP module).
AMAZE is available free of charge to qualified
users.
To implement the desired logic functions, the
state of each logic variable from logic equations
(I, B, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE,
PRESET, etc., are defined below.
.oE
~
RIOE
~
P=D
(PRESET
DISABLED)
E=1
(ALWAYS
-=-
ENABLED)
E
=
OPTION
CODE
OPTION
PRESET 1
H
OE
CODE
PROGRAMMING:
The PLS 1aSIA has a power-up preset feature. This feature insures that the device will power-up
in a known state with all register elements (State and Output Register) at logic High (H). When
programming the device it is important to realize this is the initial state of the device. You must
provide a next state jump if you do not wish to use all Highs (H) as the present state.
i l'p i;'p i;'p il'p
"AND" ARRAY - (I), (P)
I,P
~P
I,P
r,p
Tn
L
I
STATE
INACTIVE',2
I
I
I,P
r,p
r,p
Tn
r,p
Tn
Tn
CODE
STATE
STATE
STATE
0
I, P
l,p
DON'T CARE
"OR" ARRAY - (N), (F)
"±gu' "±gu' ±gu' "±gu'
n, f
ii;l
I
I
ii;l
R
ACTION
INACTIVE',3
L
I
CODE
0
I
I
I
ACTION
SET
I
R
il,l
R
CODE
H
I
I
ACTION
RESET
I
ii;l
CODE
L
I
I
R
ACTION
NO CHANGE
I
CODE
-
I
"COMPLEMENT" ARRAY - (C)
Gl: Gl: Gl: Gl:
Tn
I
I
ACTION
INACTIVE', 4
I
I
CODE
0
I
I
I
I
GENERATE
I
I
CODe
A
Tn
Tn
Tn
ACTION
I
I
I
I
ACTION
PROPAGATE
I
I
CODE
•
I
I
I
I
ACTION
TRANSPARENT
I
I
CODE
-
I
I
NOTES:
1. This is the initial unprogrammed state of all links.
2. Any gate Tn will be unconditionally inhibited if both the true and complement of any input (lor P) are left intact.
3. To prevent simultaneous Set and Reset flip-flop commands, this state is not allowed for Nand F link pairs coupled to active gates Tn (see
flip-flop truth tables).
4. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn.
October 16,1989
302
Signetics Programmable Logic Devices
Product Specification
PLS10S/A
Field-Programmable Logic Sequencers (16 x 48 x 8)
PROGRAM TABLE ENTRIES
FPLS PROGRAM TABLE
i
CUSTOMER NAME
:
1
PROPAGATE
1
TRANSPARENT
TOTAL NUMBER OF PARTS
INACTIVE
1 •
I, P
1 H
REV
f,p
I L
DATE
DON'T CARE
I
PROGRAM TABLE
1
INACTIVE
I
A
GENERATE
CF (XXXX)
SIGNETICS DEVICE 1/
CUSTOMER SYMBOLIZED PART 1/
.
________A...:"!.f!_______ -+- _______O!,_______
INACTIVE
PURCHASE ORDER 1/
Cn
•
1
1
1
1
-
Cn
-, -, -,
•,
~r~
•
•
3
..
0
•
•
8
G
•
•
•
•
•
•
•
·••
·
1
11
12
13
1<4
15
1
17
1
1
20
21
2
23
4
25
••
Na.Fr
-
, - - - - --OPTION- - - - - 1m. Ps
,r-----------------
I PRESET, H I
I DE , L I
1
1
1
_
PIE
0
• ,"""-.
REMARKS
~-----
NEXT STATE (N&)
• , -3
2 r,--O-
OUTPUT(Fr)
,r.
.. -4T3
·•••
, --
2
0
-.-
•••
•
·
;
·
,
I
~,
I
28
·
27
29
3lL
-t
31
+
•
•
•
~
35
36
37
i-
I
I
I
·
· :t::1=
I
-'IlL
~
9
40
<41
4
-l-
45
47
PIN
NO.
2
0
,
2
2
2
2
3
·,
2
:
•• ,
2
2
2
3
I
-t---t
\"
,
I
I
+-+
·
2
, ••,
,-
--t
0
6
I
I
I
1
7 j 8
I
w
~Z
>
•
, ,, , , , 'i'
2 3 •
i
•
8
~:I!
-«
I
t-
I
I
I
I
·
43
<44
•
•
'4
•
I
I
I
I
-+
r-
I
I
I
·
~
W
..J
.ra, 21'-
·
·
3
<4
5
8
7
I l
OR
PRESENT STATE (Ps)
8T,
IH
RESET
OPTION (PIE)
INPUT (1m)
;-
SET
NO CHANGE
AND
T
E
R
M
I
1 •
I
III
NOTES:
1. The FPLS is shipped with all links initially intact. Thus, a background of "0" for all Terms, and an "H" for the PIE option, exits in the table, shown BLANK instead for clarity.
2. Unsed Cn, 1m, and Ps bits are normally programmed Don't Care (-).
3. Unused Transition Terms can be left blank for future code modification, or programmed as (-) for maximum speed.
4. letters in variable fields are used as identifiers by logic type programmers.
October 16, 1989
303
Product Specification
Signetics Programmable Logic Devices
PLS10S/A
Field-Programmable Logic Sequencers (16 x 48 x 8)
TEST ARRAY
The FPLS may be subjected to AC and DC
parametric tests prior to programming via an
on-chip test array.
The array consists of test transition terms 48
and 49, factory programmed as shown below.
Testing is accomplished by clocking the FPLS
and applying the proper input sequence to
10 - 15 as shown in the test circuit timing diagram.
F,
GNO
State Diagram
FPLS Under Test
TEST ARRAY PROGRAM
T
E
I
INPUT (1m)
: I
c
48
A
49
OPTION (PiE)
Lr-__,-____________________~A~N~O~__________~~~~------4
.I
•
-:-
NEXT STATE (Na)
J:-; :- ~ ;1-.-r~T;;T5-r~T3-r2FTo- ;T~-r~T2-r~loIII
l
l
l
III
l
l
l
l
l
l
l
l
l
OUTPUT(F"
-;1~T3r2Fr~ -7-r~T5-T~T;T;-r;T;;l
l
I"
OR
PRESENT STATE (Ps)
l I l l l Il Il
l
l
l
HI HI HI H
l
l
l
l
l
lllllllil
H
H
"
H
H
H
H
"
H
H
Test Array Program
+5V
Vee
OV
CK
Both terms 48 and 49 must be deleted during
user programming to avoid interfering with the
desired logic function. This is accomplished
automatically by any of Signetics' qualified
programming equipment.
10 •15
FO_7
:--1 - - -"'\
REGISTER~
STATE
3V
1.5V
ov
'- _ _ _ _ _ _ _ _ _ _ _ _
J
r---
Test Circuit Timing Diagram
TEST ARRAY DELETED
OPTION (P'E)
AND
T
E
R
M
••
••
C
•
--1 --1
1
-
5• 3
H
2
1
0
H
H
H
L
L
L
"l
"
L
L
1
--
-
1
1
OR
INPUT(lm)
PRESENT STATE (Pa)
.-T8T;-T~T'--r;T;T;T~-r~ -5-r~T3-T;T;To
H
H
L
LILIL/LILIL
L
t l L J L I l l L IL IL IL
H
H
Test Array Deleted
October 16,1989
H
HIHIHIHIH IH IH IH IH IH
304
H
NEXT STATE (Na)
OUTPUT(F~
HIGH
LOW
Signefics
PLUS105-40
Document No. 853-1351
ECN No.
97355
Date of Issue
August 11, 1989
Status
Product Specification
, Programmable Logic Devices
Field-Programmable Logic
Sequencer (16 x 48 x 8)
PIN CONFIGURATIONS
DESCRIPTION
FEATURES
The PLUS105-40 is a bipolar programmable state machine of the Mealy type.
Both the AND and the OR array are userprogrammable. AI148 AND gates are connected to the 16 external dedicated inputs
(10-115) and to the feedback paths of the 6
buried State Registers (Opo-Ops). Because the OR array is programmable, any
one or all of the 48 transition terms can be
connected to any or all of the State and
Output Registers.
• Functionally equivalent to, but
faster than TI1 05SC and
AmPLS105-37
All state transition terms can include True,
False and Don't Care states of the controlling state variables. A Complement Transition Array supports complex IF THEN
ELSE state transitions with a single productterm.
• 48 transition terms
All buried State and Output registers are
edge-triggered S-R flip-flops. Asynchronous Preset/Output Enable functions are
available.
To facilitate testing of state machine designs, diagnostic mode features for register preset and buried state register
observability have been incorporated into
the PLUS1 05-40 device architecture.
Ordering codes are listed in the Ordering
Information Table.
N Packages
• 300 and 600mil-wide Plastic DIP
paCkages
• 50MHz clock rate
- 40MHz operating frequency
• Field-Programmable (TiW link)
• 16 input variables
• 8 output functions
• 6-bit State Register
• 8-bit Output Register
• Transition complement array
• Positive edge-triggered clocked
flip-flops
• Security fuse
• Programmable Asynchronous
Preset or Output Enable
N '" 600mil-wlde
N3 ,",300mB-wide
A Package
• Power-on preset to all "1" of
internal registers
15
16
17 ClK Vcc
Is
I.
• Power diSSipation: 800mW (typ.)
• TIL compatible
• Single +5V supply
• 3-State outputs
APPLICATIONS
• Interface protocols
• Sequence detectors
• Peripheral controllers
• Timing generators
• Sequential circuits
• Elevator controllers
• Security Locking systems
• Counters
• Shift registers
PHILIPS
305
Signetics Programmable Logic Devices
Product Specification
PLUS105-40
Field-Programmable Logic Sequencer (16 x 48 x 8)
FUNCTIONAL DIAGRAM
10
PRlO£
CK
1 4 7 - - - - - - - - - - To
PIN DESCRIPTION
PIN NO.
SYMBOL
1
CK
Clock: The Clock input to the State and Output Registers. A Low-to·High transition on this line
is necessary to update the contents of both registers.
ActiveHigh (H)
2-9,26,27
20-22
10 - Ig,
1'3 - l,s
Logic Inputs: The 13 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence. True and complement signals
are generated via use of "H" and "L".
Active-High/
Low (H/L)
23
1,2
Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when exercising standard TTL levels. When 1,2 is held at + 10V, device outputs Fa - F5 reflect the contents of
Stale Register bits Po - Ps. The contents of each Output Register remains unaltered.
Active-High/
Low (H/L)
24
1"
logic/Diagnostic Inputs: A 15th external logic input to the AND array, as above, when exercising standard TTL levels. When 111 is held at + 10V, device outputs Fa - Fs become direct inputs
for State Register bits Po - Ps; a Low-to-High transition on the appropriate clock line loads the
values on pins Fa - Fs into the State Register bits Po - Ps. The contents of each Output Register
remains unaltered.
Active-High/
Low (H/L)
25
1'0
logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when exerdsing standard TTL levels. When 110 is held at + 10V, device outputs Fa - F7 become direct inputs
for Output Register bits 00 - 07; a Low-to-High transition on the appropriate clock line loads the
values on pins Fo - F7 into the Output Register bits 0 0 - 07. The contents of each State Register
remains unaltered.
Active-High/
Low (H/L)
10-13
15-18
Fa - F7
logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which normally
reflect the contents of Output Register bits 00 - 0 7, when enabled. When 1'2 is held at + 10V, Fa
- Fs = (Po - Ps). When 111 is held at +10V, Fa - Fs become inputs to State Register bits Po - Ps.
When 110 is held at +1OV, Fa - F7 become inputs to Output Register bits 0 0 - 07.
ActiveHigh (H)
19
PR!OE
Preset or Output Enable Input:
A user programmable function:
August 11,1989
NAME AND FUNCTION
POLARITY
• Preset: Provides an asynchronous preset to logic" 1" of all State and Output Register bits.
PR overrides Clock, and when held High, clocking is inhibited and Fa - F7 are High. Normal
clocking resumes with the first full clock pulse following a High-to-Low clock transition, after the
Preset signal goes low. See timing definitions.
ActiveHigh (H)
• Output Enable: Provides an output enable function to buffers Fo - F7 from the Output
Registers.
ActiveLow (L)
306
Product Specification
Signetics Programmable Logic Devices
PLUS105--40
Field-Programmable Logic Sequencer (16 x 48 x 8)
TRUTH TABLE 1, 2, 3, 4, 5, 6, 7
Vee
.
I"
I,.
CK
S
R
Op
OF
F
*
*
X
X
X
H
H
OF
L
+IOV
X
X
X
X
Op
L
L
X
X
Op
H
H
X
X
L
OF
L
X
X
H
OF
OF
OF
H
Op
OF
Hi-Z
1'0
L
+IOV
X
X
L
X
+IOV
X
L
X
+IOV
X
i
i
i
i
L
X
X
+IOV
X
X
X
L
X
X
X
X
X
X
Op
Op
H
X
X
*
X
X
X
Op
X
+IOV
X
X
X
Op
L
L
+IOV
X
X
X
X
Op
H
H
X
X
+IOV
X
X
X
L
OF
L
X
X
+IOV
X
i
i
i
i
X
X
X
X
H
L
X
X
+IOV
X
X
X
X
X
X
X
X
X
OF
OF
OF
Op
L
Op
Op
L
X
X
X
L
L
Op
OF
OF
L
X
X
X
L
H
L
L
L
+5V
i
OPTION
OE
H
PR
X
L
X
X
X
L
X
X
X
i
i
i
i
X
X
X
X
X
OF
H
OF
H
L
H
H
H
H
H
IND.
IND.
IND.
X
X
H
H
NOTES:
I. Positive Logic:
S/R(orJ/K)=To+T, +T2 + ... T4B
Tn = (Co, C,) (10, 1,,12, ... ) (PO, P" ... P5)
2. Either Preset (Active - High) or OUtput Enable (Active - Low) are available, but not both. The desired function is a user-programmable option.
3. i denotes transition from Low-to-High level.
4. * = HorLor+IOV
5. X = Don't Care (~5.5V)
6. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-stated and the indicated levels on
the output pins are forced by the user.
7. IND. = Indeterminent
VIRGIN STATE
A factory-shipped virgin device contains all fusible links intact, such that:
I. PRIOE option is set to PR. Note that even
if the PR function is not used, all registers
are preset to "I" by the power-up procedure.
2. All transition terms are disabled (0).
3. All SIR flip-flop inputs are disabled (0).
4. The device can be clocked via a Test Array
preprogrammed with a standard test pattern. NOTE: The Test Array pattern must
be deleted before incorporating a user
program.
August1l, 1989
307
Product Specification
Signetics Programmable Logic Devices
Field-Programmable Logic Sequencer (16 x 48 x 8)
FPLS LOGIC DIAGRAM
NOTES:
with a blown link lIoal to a
a blown fuse float to logic
August 11, 1989
"1"
308
PLUS10~O
Product Specification
Signetics Programmable Logic Devices
PLUS105-40
Field-Programmable Logic Sequencer (16 x 48 x 8)
ORDERING INFORMATION
..- ..
DE«',...nl"T!ON
-" ••::n... n r I I
LOGIC FUNCTION
-
ODnE"COD"
28-pin Plastic Dual-In-Line, 6oomil-wide
PLUS10S-40N
28-pin Plastic Dual-In-Line, 3OOmil-wide
PLUS10S-40N3
28-pin Plastic Leaded Chip Carrier, 450mil-square
PLUS 1OS-40A
Typical State Transition:
I
~ I~\~ I
2 R PRESENT STATE
JI:. II'
STATE REGISTER
THERMAL RATINGS
I0
lot, I
Sn+'
c· ...
NEXT STATE
TEMPERATURE
Maximum junction
150°C
SETOO'So= (02'
RO =0
Maximum ambient
75°C
RESET Q1: 51
Allowable thermal rise ambient to junction
75°C
=0
=
HOLD 02' S2 0
R2 =0
RATINGS
PARAMETER
Max
UNIT
+7
VDC
Input voltage
+5.5
VDC
V OUT
Output voltage
+5.5
VDC
liN
Input currents
+30
mA
lOUT
Output currents
+100
mA
TA
Operating temperature range
0
+75
°c
tSTG
Storage temperature range
-65
+150
°c
Vee
Supply voltage
V IN
Min
-30
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.
August 11, 1989
309
'I1' CoO.
R, = (02' 0, . 00)' J\. II' CoO.
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
O,·~)·J\
Product Specification
Signetics Programmable Logic Devices
PLUS105-40
Field-Programmable Logic Sequencer (16 x 48 x 8)
DC ELECTRICAL CHARACTERISTICS
O°C:5: T A :5: 75°C, 4.75V :5: Vee :5: 5.25V
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
Min
Vee = Max
Vee = Min
Vee = Min, liN = -12mA
2.0
Typl
Max
UNIT
0.8
Input voltage 2
V IH
V IL
Vie
High
Low
Clamp3
-0.8
-1.2
V
V
V
0.35
0.45
V
V
Output voJtage2
VOH
VOL
High
Low
Vee = Min
10H =-2mA
10L =9.6mA
2.4
Input current
Vee = Max
IIH
High
VIN = Vee
<1
25
IlL
Low
VIN = 0.45V
-20
-250
J.IA
J.IA
Output current
Vee = Max
10(OFF}
Hi-Z state
-70
J.IA
J.IA
J.IA
200
mA
VOUT = 5.5V
1
40
VOUT = 0.45V
-1
-40
los
Short circuit!, 4
VOUT = OV
lee
Vee supply currents
Vee = Max
160
Vee =5.0V
VIN = 2.0V
VOUT = 2.0V
10
-15
Capacitance
CIN
COUT
Input
Output
NOTES:
1.
2.
3.
4.
5.
All typical values are at Vee = 5V, TA = +25°C.
All voltage values are with respect to network ground terminal.
Test one at a time.
Duration 01 short circuit should not exceed 1 second.
lee is measured with the PRIDE input grounded, all other inputs at 4.5V and the outputs open.
August 11, 1989
310
8
pF
pF
Product Specification
Signetics Programmable Logic Devices
PLUS105-40
Field-Programmable Logic Sequencer (16 x 48 x 8)
AC ELECTRICAL CHARACTERISTICS R,
SYMBOL
= 470Q, R2 = 1kQ, Cl = 30pF, O°C $ TA $ +75°C, 4.75V $ Vcc $ 5.25V
..
i
I
PARAMETER
I
I
~
i
~
TO
Min
Typl
CK+
CK-
CKCK+
10
10
8
8
ns
ns
FROM
Max
UNIT
Pulse Width
IeKH
IeKL
Clock High
Clock Low
IeKP1
Period (without Complement Array)
Input±
Output±
25
20
ns
IeKP2
tpRH
Period (with Complement Array)
Preset pulse
Input±
PR+
Output±
PR-
35
15
28
8
ns
ns
tlS1
Input
Input±
CK+
15
12
ns
tlS2
tvs
tpRS
iNVCK
Input (through Complement Array)
Power-on preset
Clock resume (after preset)
Clock lockout (before preset)
Input±
Vcc +
PRCK-
CK+
CKCKPR-
25
0
0
15
20
-10
-5
5
ns
ns
ns
ns
CK+
Input ±
5
-10
ns
CK+
OEOE+
PR +
Vcc+
Output±
OutputOutput +
Output +
Output +
Without Complement Array
Input±
Output±
40.0
50.0
MHz
With Complement Array
Clock period
Input±
CK+
Output±
CK+
28.5
50.0
35.7
62.5
MHz
MHz
Setup Time
Hold Time
tlH
Input
Propagation Delay 3
IeKO
toE
too
IpR
tpPR
Clock
Output enable
Output disable 2
Preset
Power-on preset
8
8
8
15
0
10
10
10
20
10
ns
ns
ns
ns
ns
Frequency of Operation
fMAX
fMAX
fClK
NOTES:
1. All typical values are at Vee = 5V, TA = +25°C.
2. Cl = 5pF; VT = VOL +0.5V.
3. Propagation delays measured with all outputs switching.
August 11, 1989
311
Product Specification
Signetics Programmable Logic Devices
PLUS105-40
Field-Programmable Logic Sequencer (16 x 48 x 8)
TIMING DIAGRAMS
+3V
OV
+3V
I.SV
OV
VOH
VOL
+3V
OV
tOE
Sequential Mode
+3V
OV
+3V
I.SV
ClK
OV
tcKl
VOH
Fo_1?
1.SV
VOL
+3V
PR
I.SV
I.SV
OV
Asynchronous Preset
,-------------__________________________
Vee
~V
4.5V
-J~--------------------------------------- OV
. . . . -----
~~~~_.h..-----------Fo - F7
[Fnl =1
I.SV
VOH
[Fn + 1]
' - - - - - - VOL
eLK
I.Sv-j
-----..J~tcK
OV
tvs
Power-On Preset
August 11. 1989
312
Product Specification
Signetics Programmable Logic Devices
PLUS105--40
Field-Programmable Logic Sequencer (16 x 48 x 8)
TIMING DIAGRAMS (Continued)
Y=
+'UV
S.DV
110
-----I
+3V
OV
tRJH
17"''''''''''''~''7~'''''-r,...,'''''''''
Fa _ F7
, _____....J._""'; - .........-...........
7'1
(INPUTSI LL.L.c...t.;.L.L.c...t.;.L.L.c...t.;.L.LJ ' -_ _ _ _ _...,-_..J ":....L.L.c...t.:....L.L.'"
+3V
ov
+3V
ClK
I'----ov
-'S--...j.~
(~~fn~i) ~~~~
Diagnostic Mode-Output Register Input Jam
Y=
+'OV
s.ov
I"
-----I
+3V
oV
tRJH
Fo_ FS
"""""''''''''''''''''''"'7'"''''''''''"'7'"'''''''"7\
~-----....I..-,"",
+3V
(INPUTSI 1L.c...t.;.L.L.c...t.;.L.L.c...t.;.L.L.<.U ' -_ _ _ _ _...,-_..J "-"-"-<:....L-"-"-<:'" OV
+3V
ClK
(
's --..j..~
'----OV
tcKH
7~D:I----VOH
po-ps)
STATE
~LL
REG.
----- VOL
tcKO
Diagnostic Mode-State Register Input Jam
TIMING DEFINITIONS
SYMBOL
tcKH
PARAMETER
Width of input clock pulse
tcKL
Interval between clock pulses.
tcKP2
Operating period - when using Complement Array.
tiS'
Required delay between beginning of valid input and positive
transition of Clock.
tlS2
Required delay between beginning of valid Input and positive
transition of Clock, when using
optional Complement Array
(two passes necessary through
the AND Array).
SYMBOL
PARAMETER
tlH
Required delay between positive transition of Clock and end
of valid Input data.
tCKo
Delay between positive transition of Clock and when Outputs become valid (with PR!O"E
Low).
tOE
Delay between beginning of
Output Enable Low and when
Outputs become valid.
too
Delay between beginning of
Output Enable High and when
Outputs are in the OFF-state.
tvs
Required delay between Vcc
(after power-on) and negative
transition of Clock preceding
first reliable clock pulse.
tSRE
Delay between input 1'2 transition to Diagnostic Mode and
when the Outputs reflect the
contents of the State Register.
tpRs
Required delay between negative transition of Asynchronous
Preset and the first positive
transition of Clock.
tSRO
Delay between input 1'2 transition to Logic mode and when
the Outputs reflect the contents of the Output Register.
August 11, 1989
313
SYMBOL
PARAMETER
tcKP'
Operating period - without the
Complement Array.
tpR
Delay between positive transition of Preset and when Outputs become valid at "1".
tpPR
Delay between Vcc (after)
power-on) and when Outputs
become preset at "1".
tpRH
Width of preset input pulse.
fMAX
Min. guaranteed operating frequency.
tNVCK
Required delay between the
negative transition of the clock
and the negative transition olthe
Asynchronous PRESET to
guarantee that the clock edge is
not detected as a valid negative
transition.
Product Specification
Signetics Programmable Logic Devices
PLUS105-40
Field-Programmable Logic Sequencer (16 x 48 x 8)
TIMING DIAGRAMS (Continued)
10- 111,
1'3- I
'S_..JI'-_____________________
+3V
OV
+1DY
+3V
1'2
_JI'_ _ _ _ _JI
OV
+3V
ClK
OV
INTERNAL
STATE REG.--
VOH
--r- 10
I
FoT
I
I
I
I
o-l--
OUT
F7
l
1'5
0 - - CK
PRIOE - - 0
GNO
J:n
R2
Cl
": " J ~~~:~O~G
CAPACITANCE)
2.5...
~
2.5na
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs. unless otherwise specified.
Input Pulses
LOGIC PROGRAMMING
PLUS105-40 logic designs can be generated
using Signetics AMAZE pLD design software
or one of several other commercially available.
JEDEC standard PLD design software packages. Boolean andlor state equation entry is
accepted.
PLUS1 05-40 logic designs can also be generated using the program table entry format detailed on the following pages. This program
table entry format is supported by the Sig netics
AMAZE PLD design software (PTE module).
AMAZE is available free of charge to qualified
users.
August 11.1989
To implement the desired logic functions, the
state of each logic variable from logic equations
(I, S, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE,
PRESET. etc., are defined below.
PROGRAMMING THE
PLUS 105·40
The PLUS105-40 has a power-up preset feature. This feature insures that the device will
power-up in a known state with all register elements (state and output register) at a logic High
(H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you
do not wish to use all Highs (H) as the present
state.
314
Signetics Programmable Logic Devices
Product Specification
PLUS105-40
Field-Programmable Logic Sequencer (16 x 48 x 8)
PRESET/OE OPTION - (P/E)
p~--V~~j
~
"RIOl::
E=1
(ALWAYS
ENABLED)
-=OPTION
..
P =0
(pRESET
DISABLED)
CODE
OPTION
E
CODE
H
i
1i
'
P
1
1
1
"AND" ARRAY - (I), (P)
I, P
I, P
I. P
i,p
'p
Tn
I, P
i
i,p
i
I,p
'p
Tn
Tn
I
STATE
I
CODE
I
STATE
STATE
STATE
I
iNACTIVE " 2
I
0
I
I,P
1, P
DON'T CARE
I,p
'p
Tn
"OR" ARRAY - (N), (F)
"fgU-' .'fgU-' "fgU-' "fgU-'
R
il,l
I
ACTION
I
INACTIVE " 3
I
I
R
il,1
CODE
0
I
I
I
ACTION
SET
I
CODE
H
n;l
I
I
n;l
R
ACTION
RESET
I
CODE
L
I
I
R
ACTION
NO CHANGE
CODE
I -
I
"COMPLEMENT" ARRAY· (C)
~: ~: ~: ~:
Tn
I
I
ACTION
INACTlVE ' ,4
I
I
CODE
0
Tn
I
I
I
ACTION
GENERATE
I
CODE
A
Tn
Tn
I
I
I
ACTION
PROPAGATE
I
I
CODE
•
I
I
I
I
ACTION
TRANSPARENT
I
I
CODE
-
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates Tn'
2. Any gate Tn will be unconditionally inhibited if both the true and complement fuses of any input (I,P) are left intact.
3. To prevent simultaneous Set and Reset flip-flop commands, this state is not allowed for Nand F link pairs coupled to active gates Tn (see
flip-flop truth tables).
4. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn.
August 11, 1989
315
I
I
Signetics Programmable Logic Devices
Product Specification
PLUS105-40
Field-Programmable Logic Sequencer (16 x 48 x 8)
FPLS PROGRAM TABLE
PROGRAM TABLE ENTRIES
________A_Np_______
CUSTOMER NAME
PURCHASE ORDER
* ___________
SIGNETICS DEVICE *
CF (XXXX)
INACTIVE
: 0
GENERATE
PROPAGATE
CUSTOMER SYMBOLIZED PART # _ _ _ _ _ __
+ ______ ..P!I______ _
:
A
Cn
I.
TRANSPARENT 1 _
TOTAL NUMBER OF PARTS _ _ _ _ _ _.____
PROGRAMTABLE _ _ _ _ _ _ _ _ _ _.__
REV
DATE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
INACTIVE
I (]
I,P
I H
r. P
I L
DON'T CARE
I _
E
A
M
Q
0'
-.
I
iT 10
I l
Na,Fr
~
- - - - --O-PTIOi\i- - - - - -
r-----------------
1m. 'a
I
I PAESET , H I
: I OE , L I
PIE
OA
PRESENT STATE (Ps)
REMARKS
NEXT STATE (Ha)
-4
-2"
OUTPUT(Fr)
5 -4T 3~2-'--'--'--0--1
·
·
·
·
·
·
I
2
3
4
6
6
7
8
RESET
OPTION (PIE)
INPUT (1m)
Cn -5,-T-.,
) I I, 211
II "
I 0
I H
NO CHANGE : -
AND
T
INACTlVE
SET
6
S -4---.3 2
~,- 0
5
4 r3"T
2 r1
0
5
3
1:'-0-t-:,T:
ST
I
I
I
I
9
1
11
12
13
14
16
18 '
17
1
1
20
21
2
23
27
28
29
lIt
~
34
35
36
37
I
I
I
L
·
·
·
·••
I
I
I
·
I
·
•
•
•
•
·
·•
·
.
I
I
I
I
9
40
41
42..
I
I
I
-
L
43
44
46
48
47
PIN
NO.
.
·,
__
.
,,
o ,
I
1 1 1 1 1 1
235878
I
NOTES:
1. The FPLS is shipped with all links initially intact. Thus, a background of "0" for all Terms, and an "H" for the PIE option, exists in the table,
shown BLANK instead for clarity.
2. Unused C n, 1m , and Ps bits are normally programmed Don't Care (-).
3. Unused Transition Terms can be left blank for future code modification, or programmed as (-) for maximum speed.
4. Letters in variable fields are used as identifiers by logic type programmers.
August 11, 1989
316
Signetics
PLUS105-55
Document No.
ECN No.
Date of Issue November 1989
Status
Preliminary Specification
Field-Programmable Logic
Sequencer (16 x 48 x 8)
I.
Programmable Logic Devices
PIN CONFIGURATIONS
DESCRIPTION
FEATURES
The PLUS105-55 is a bipolar programmable state machine of the Mealy type.
Both the AND and the OR array are userprogrammable. All 48 AND gates are connected to the 16 external dedicated inputs
(10-1'5) and to the feedback paths of the 6
buried State Registers (Qpo-Qps). Because the OR array is programmable, any
one or all of the 48 transition terms can be
connected to any or all of the State and
Output Registers.
• Functionally equivalent to, but
faster than Tl1 05Be and
AmPLS105-37
All state transition terms can include True,
False and Don't Care states of the controlling state variables. A Complement Transition Array supports complex IF THEN
ELSE state transitions with a single productterm.
• 48 transition terms
All buried State and Output registers are
edge-triggered S-R flip-flops. Asynchronous Preset/Output Enable functions are
available.
To facilitate testing of state machine designs, diagnostic mode features for register preset and buried state register
observability have been incorporated into
the PLUS105-55 device architecture.
Ordering codes are listed in the Ordering
Information Table.
N Packages
• 62.5MHz clock rate
- 55MHz operating frequency
• Available in 300 and 600mil-wide
Plastic DIP packages
• Field-Programmable (TiW link)
• 16 input variables
• 8 output functions
• 6-bit State Register
• 8-bit Output Register
• Transition complement array
• Positive edge-triggered clocked
flip-flops
• Security fuse
N .. 6OOmil-wide
• Programmable Asynchronous
Preset or Output Enable
N3 .. 3OOmil-wide
A Package
• Power-on preset to all "1" of
Internal registers
• Power dissipation: 800mW (typ.)
15
16
17 CLK Vee
Is
19
• TTL compatible
• Single +5V supply
• 3-State outputs
APPLICATIONS
• Interface protocols
• Sequence detectors
• Peripheral controllers
• Timing generators
• Sequential circuits
• Elevator controllers
• Security Locking systems
• Counters
• Sh ift reg isters
PHILIPS
317
Signetics Programmable Logic Devices
Preliminary Specification
Field-Programmable Logic Sequencer (16 x 48 x 8)
PLUS105-55
FUNCTIONAL DIAGRAM
>--+----------+-c
PRillE
~-+-----------------+_c
T 4 7 - - - - - - - - - - To
CK
PIN DESCRIPTION
PIN NO.
SYMBOL
1
CK
Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this
line is necessary to update the contents of both registers.
ActiveHigh (H)
2-9,26,27
20-22
10 -19,
113 - 11S
Logic Inputs: The 13 external inputs to the AND array used to program jump conditions
between machine states, as determined by a given logic sequence. True and complement
signals are generated via use of "H" and "L".
Active-Hight
Low (H/L)
23
112
Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when exercising standard TTL levels. When 112 is held at + 10V, device outputs Fa - Fs reflect the contents of State Register bits Po - Ps. The contents of each Output Register remains unaltered.
Active-Highl
Low (H/L)
24
111
Logic/Diagnostic Inputs: A 15th external logic input to the AND array, as above, when
exercising standard TTLIevels. When 111 is held at + 10V, device outputs Fa - Fs become
direct inputs for State Register bits Po - Ps ; a Low-ta-High transition on the appropriate clock
line loads the values on pins Fa - Fs into the State Register bits Po - Ps. The contents of each
Output Register remains unaltered.
Active-Highl
Low (H/L)
25
110
LogiC/Diagnostic Input: A 16th external logic input to the AND array, as above, when exercising standard TTL levels. When 110 is held at +10V, device outputs Fa - F7 become direct
inputs for Output Register bits 0 0 - 0 7; a Low-to-High transition on the appropriate clock line
loads the values on pins Fa - F7 into the Output Register bits 0 0 - ~. The contents of each
State Register remains unaltered.
Active-Hight
Low (H/L)
10-13
15-18
Fo- F7
Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which normally reflect the contents of Output Register bits 0 0 - 0 7, when enabled. When 112 is held at
+ 10V, Fo - Fs = (Po - Ps). When 111 is held at + 10V, Fo - Fs become inputs to State Register
bits Po - Ps. When 110 is held at + 10V, Fo - F7 become inputs to Output Register bits 00 -~.
ActiveHigh (H)
19
PRiOE
Preset or OUtput Enable Input:
A user programmable function:
November 1989
NAME AND FUNCTION
POLARITY
• Preset: Provides an asynchronous preset to logic" 1" of all State and Output Register
bits. PR overrides Clock, and when held High, clocking is inhibited and Fo - F7 are High.
Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after the Preset signal goes Low. See timing definitions.
ActiveHigh (H)
• Output Enable: Provides an output enable function to buffers Fo - F7 from the Output
Registers.
ActiveLow(L)
318
Signetics Programmable Logic Devices
Preliminary Specification
PLUS105-55
Field-Programmable Logic Sequencer (16 x 48 x 8)
TRUTH TABLE 1, 2, 3, 4, 5, 6, 7
I
Vcc
.
1,2
.
CK
OF
F
x
x
X
H
H
OF
X
X
x
x
x
X
Op
L
L
X
Op
H
H
X
L
OF
L
X
i
i
i
i
x
X
H
+10V
X
X
X
X
X
OF
OF
OF
Op
X
Op
Op
OF
Hi-Z
H
.
L
+10V
L
+10V
X
X
L
X
+10V
X
L
X
+10V
L
X
X
L
X
X
+5V
i
I
OPTiON
PR
X
OE
1'0
I"
H
X
X
.
X
+10V
X
X
X
+10V
X
X
X
X
+10V
X
X
X
+10V
X
S
R
Op
H
OF
X
X
X
Op
x
X
Op
L
L
x
x
X
Op
H
H
X
L
OF
L
X
i
i
i
i
x
X
H
H
Op
OF
L
X
X
+10V
X
X
X
L
X
X
X
X
X
X
Op
Op
OF
OF
OF
L
X
X
L
Op
OF
X
X
L
X
X
L
X
X
x
x
i
i
i
i
L
L
x
x
x
x
x
x
x
OF
L
H
L
L
L
H
L
H
H
H
H
H
IND.
IND.
IND.
x
X
H
H
NOTES:
1. Positive Logic:
= To +T, +T2 + ... T48
Tn = (Co, C,) (10, I" 12 , ... ) (Po, P" ... Ps)
2. Either Preset (Active - High) or Output Enable (Active - Low) are available, but not both. The desired function is a user-programmable option.
SIR (orJ/K)
3.
i
denotes transition from Low-to-High level.
= HorLor+10V
5. X = Don't Care (~5.5V)
4.'
6. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-stated and the indicated levels on
the output pins are forced by the user.
7. IND. = Indeterminent
VIRGIN STATE
A factory-shipped virgin device contains all fusible links intact, such that:
1. PRICE option is set to PRo Note that even
if the PR function is not used, all registers
are preset to "1" by the power-up procedure.
2 All transition terms are disabled (0).
3. All SIR flip-flop inputs are disabled (0).
4. The device can be clocked via a Test Array
preprogrammed with a standard test pattern. NOTE: The Test Array pattern must
be deleted before incorporating a user
program.
November 1989
319
Preliminary Specification
Signetics Programmable Logic Devices
Field-Programmable logic Sequencer (16 x 48 x 8)
FPLS LOGIC DIAGRAM
November 1989
320
PlUS10S-55
Signetics Programmable Logic Devices
Preliminary Specification
Field-Programmable Logic Sequencer (16 x 48 x 8)
PLUS105-55
ORDERING INFORMATION
I
LOGIC FUNCTION
i
i
DESCRIPTION
ORDER CODE
28-pin Plastic Dual-In-Line, 6oomil-wide
PLUS105-SSN
28-pin Plastic Dual-In-Line, 3OOmil-wide
PLUS 105-55N3
PLUS105-55A
28-pin Plastic Leaded Chip Carrier, 450mil-square
Typical Slale Transition:
I: I~\~ I ~R
STATE REGISTER
I lot, I s,,+,
THERMAL RATINGS
0
PRESENT STATE
J( • B • C ••••
NEXT STATE
TEMPERATURE
SET 00:
150°C
Maximum junction
So= 10:1·0,
.~). J(.
B· C •.•
RO= 0
Maximum ambient
75°C
Allowable thermal rise ambient to junction
75°C
RESET Q1: 51
=0
R, =102.0,.00) .J\". B· C ...
HOLD 02: ~. 0
R2= a
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
RATINGS
Min
UNIT
Max
Vee
Supply voltage
+7
Voc
Y,N
Input voltage
+5.5
Voc
VOUT
Output voltage
+5.5
Vee
liN
Input currents
+30
mA
lOUT
Output currents
TA
Operating temperature range
tSTG
Storage temperature range
-30
+100
mA
0
+75
°c
-65
+150
°c
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
November 1989
321
Preliminary Specification
Signetics Programmable Logic Devices
PLUS105-55
Field-Programmable Logic Sequencer (16 x 48 x 8)
DC ELECTRICAL CHARACTERISTICS oOC ~
TA ~ 75°C, 4.75V ~ Vee ~ 5.25V
LIMITS
PARAMETER
SYMBOL
TEST CONDITION
Min
Vee: Max
Vee: Min
Vee: Min, liN: -12mA
2.0
Typ'
Max
UNIT
--{).8
0.8
-1.2
V
V
V
0.35
0.45
V
V
Input voltage2
V,H
V ,L
Vie
High
Low
Clamp 3
Output voltage2
VOH
VOL
High
Low
Vee: Min
10H :-2mA
10L: 9.6mA
2.4
Input current
Vee: Max
I'H
High
Y,N : Vee
<1
25
I,L
Low
V,N : 0.45V
-20
-250
IlA
IlA
Output current
Vee: Max
10(oFF)
Hi-Z state
-70
IlA
IlA
IlA
200
rnA
VOUT : 5.5V
1
40
VOUT : 0.45V
-1
-40
los
Short circuit3 , 4
VOUT: OV
lee
Vee supply currentS
Vee: Max
160
Vee: 5.0V
V,N: 2.0V
VOUT : 2.0V
8
10
-5
Capacitance
C'N
COUT
NOTES:
Input
Output
1. All typical values are at Vee: 5V, TA: +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Duration of short circuit should not exceed 1 second.
S. lee is measured with the PR/OE input grounded, all other inputs at 4.5V and the outputs open.
November 1989
322
pF
pF
Signetics Programmable Logic Devices
Preliminary Specification
Field-Programmable logic Sequencer (16 x 48 x 8)
PlUS105-55
CHARACTERISTICS R, = 4700, R2 = lkO, Cl = 30pF. OoC $
,AC ELECTRICAL
,
,
,
TA $ +75°C. 4.75V$ Vcc $5.25V
,
,
,
UMITS
SYMBOL
PARAMETER
FROM
TO
Min
CK+
CK-
CKCK+
8
8
ns
ns
Typ'
Max
UNIT
Pulse Width
tCKl
Clock High
Clock Low
tCKP'
Period (without Complement Array)
Input±
Output±
18
ns
tCKP2
tpRH
Period (with Complement Array)
Preset pulse
Input±
PR+
Output±
PR-
28
10
ns
ns
tIS'
Input
Input±
CK +
10
ns
t'S2
tvs
tpRS
tNVCK
Input (through Complement Array)
Power-on preset
Clock resume (after preset)
Clock lockout (before preset)
Input±
Vcc +
PRCK-
CK+
CKCKPR-
20
0
0
12
ns
ns
ns
ns
CK+
Input ±
5
ns
CK+
OEOE+
PR +
Vcc+
Output±
OutputOutput +
Output +
Output +
Without Complement Array
Input±
Output ±
55.0
MHz
With Complement Array
Clock period
Input±
CK+
Output ±
CK+
35.7
62.5
MHz
MHz
tcKH
Setup Time
Hold Time
tlH
Input
Propagation Delay
tCKO
tOE
too
tpR
tpPR
Clock
Output enable
Output disable2
Preset
Power-on preset
8
8
8
15
10
ns
ns
ns
ns
ns
Frequency of Operation
fMAX
fMAX
fClK
NOTES:
1. All typical values are at VCC = 5V. T A = +25°C.
2. Cl = 5pF; VT = Val + 0.5V.
3. Propagation delays measured with all outputs switching.
November 1989
323
Preliminary Specification
Signetics Programmable Logic Devices
PLUS105-55
Field-Programmable Logic Sequencer (16 x 48 x 8)
TIMING DIAGRAMS
.3V
OV
.3V
1.SV
ov
VOH
VOL
.3V
OV
toE
Sequential Mode
______________________________________________________________ ~V
__________________________________________________________________ OV
1.SV
ClK
'----------- OV
-------......
~+---------------------__.. ~------------- VOH
1.SV
_______...J 'I........L-_____________________.J ' - - - - - - - - - - VOL
PR
1.5V
1.SV
~~~~~~~--------------------------------w
Asynchronous Preset
.5V
OV
IFnl
1.SV
VOH
=,
[Fn + 1]
VOL
.3V
ClK
'o5V-!-
~-----'l__tcK
OV
i+-----lys----.1
~
~:v
~s =±= ~H::'.j '-tcKP
10- 1'5
____________________________' _ o 5 V T
Power-On Preset
November 1989
324
3V
Preliminary Specification
Signetics Programmable Logic Devices
PLUS105--55
Field-Programmable Logic Sequencer (16 x 48 x 8)
TIMING DIAGRAMS (Continued)
§
+10V
8.0V
+3V
ov
tRJH
Fo_ F7
"""''7"':'1'""77''''7"':'1'""77''''''-::''77'''7'- , - - - - - - - ' - " " '
+3V
(INPUTS) L.L..L..L..<'-L..L..L..<'-L..L..'-"'-'.D '- _ _ _ _ _-,-_.1 '-c.J.:.LLJ.:....£..LJ OV
CLK
I"-_ _ _ OV
-~S---f.~
(~i~~f) ~~~~'p&=~I~]:::
~h~:j"Diagnostic Mode-Output Register Input Jam
§
+lOV
B.OV
+3V
ov
tRJH
Fa _ FS
.,...,'I'""7'"7''7"':'I'""7'"7''7"':'I'""77''''7"':n.I,..-----.....- ' " '
+3V
(INPUTS) LL.L...c.J.;.L.L...c.J.;.L.L,oc.J.-LUI '-_"";" _ _""';;';""'_J ,,:....£..L..c.J.:.L~
OV
CLK
-~S~~+--
(~;:i.~)~~~~
Diagnostic Mode-State Register Input Jam
TIMING DEFINITIONS
SYMBOL
tcKH
PARAMETER
Width of input dock pulse.
tcKL
Interval between clock pulses.
!eKP2
Operating period - when
using Complement Array.
tlS1
Required delay between
beginning of valid input and
positive transition of Clock.
tlS2
Required delay between
beginning of valid Input and
positive transition of Clock,
when using optional Complement Array (two passes necessary through the AND
Array).
tvs
Required delay between Vcc
(after power-on) and negative
transition of Clock preceding
first reliable clock pulse.
IpRS
Required delay between
negative transition of Asynchronous Preset and the first
positive transition of Clock.
November 1989
SYMBOL
tlH
tCKO
tOE
too
PARAMETER
Required delay between positive transition of Clock and
end of valid Input data.
Delay between positive transition of Clock and when OutbE}s become valid (with P RI
Low).
Delay between beginning of
Output Enable Low and when
Outputs become valid.
Delay between beginning of
Output Enable High and when
Outputs are in the OFF-state.
tSRE
Delay between input 1'2 transition to Diagnostic Mode and
when the Outputs reflect the
contents of the State Register.
tSRD
Delay between input 1,2 transition to Logic mode and
when the Outputs reflect the
contents of the Output Register.
325
SYMBOL
PARAMETER
tCKP1
Operating period - without
the Complement Array.
tpR
Delay between positive transition of Preset and when Outputs become valid at "1".
tpPR
Delay between Vcc (after)
power-on) and when Outputs
become preset at "1".
tpRH
Width of preset input pulse.
fMAX
Min. guaranteed operating
frequency.
tNVCK
Required delay between the
negative transition of the clock
and the negative transition of
the Asynchronous PRESET to
guarantee that the clock edge
is not detected as a valid negative transition.
Preliminary Specification
Signetics Programmable Logic Devices
PLUS105-55
Field-Programmable Logic Sequencer (16 x 48 x 8)
TIMING DIAGRAMS (Continued)
,'r----------------------
1o- 111.-.....
113 -I,5_-"I'\,_'·5_V_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
ov
+10V
+3V
OV
ClK
i~!i:~~~.-00-05--
~--~---------------------------------------
OV
Diagnostic Mode-Slale Register Outputs
TEST LOAD CIRCUITS
VOLTAGE WAVEFORMS
y
+5V
VCC
<>--r
10
I
I
I
FoI!"I
o-L-
I
OUT
I
F7~
"5
0 - - - CK
PR/~
GND
f---<>
~
Cl
(INCLUDES
SCOPE AND JIG
CAPACITANCE)
2._
2.500
MEASUREMENTS:
All circu~ delays are measured at the + 1.5V level of
inputs and outputs, unless otherwise specified.
-=l::-
Input Pulses
LOGIC PROGRAMMING
PLUS105-55 logic designs can be generated
using Signetics AMAZE PLD design software
or one of several other commercially available.
JEDEC standard PLD design software packages. Boolean andlor state equation entry is
accepted.
PLUS1 05-55 logic designs can also be generated using the program table entry format detailed on the following pages. This program
table entry format is supported by the Signetics
AMAZE PLD design software (PTE module).
AMAZE is available free of charge to qualified
users.
November 1989
To implement the desired logic functions. the
state of each logic variable from logic equations
(I, S, 0, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT. INACTIVE,
PRESET. etc., are defined below.
PROGRAMMING THE
PLUS 105-55
The PLUS105-55 has a power-up preset feature. This feature insures that the device will
power-up in a known state with all register elements (state and output register) at a logic High
(H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you
do not wish to use all Highs (H) as the present
state.
326
Preliminary Specification
Signetics Programmable Logic Devices
PLUS105-55
Field-Programmable Logic Sequencer (16 x 48 x 8)
PRESET/OE OPTION - (PIE)
R!OE
~
iOE
P
~
P=O
(PRESET
DISABLED)
E=1
(ALWAYS
-=
ENABLED)
OPTION
CODE
PRESET 1
H
E
-=
OPTION
CODE
"AND" ARRAY - (I), (P)
I,P
~P
i'P
i,p
I,P
ii'P
Lp
I,P
ii'P
i,p
ii'P
I,p
i
Tn
Tn
STATE
"OR" ARRAY - (N), (F)
"tgD0
Tn
i\f
I
I
R
I
ACTION
I
INACTIVE',3
CODE
0
I
I
Tn
Tn
STATE
STATE
STATE
I, P
j, P
DON'T CARE
"two "two two
n,f
R
n,1
I
ACTION
SET
I
CODE
H
R
n,1
I
I
ACTION
RESET
I
CODE
L
i\f
I
I
ACTION
NO CHANGE
I
CODE
-
I
"COMPLEMENT" ARRAY - (C)
Gl: Gl: Gl: Gl:
Tn
I
ACTION
INACTIVE','
.
I
I
CODE
0
Tn
Tn
I
I
I
ACTION
GENERATE
I
CODE
A
I
I
I
ACTION
PROPAGATE
CODE
I
•
Tn
I
I
I
I
ACTION
TRANSPARENT
I
CODE
-
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates Tn.
2. Any gate Tn will be unconditionally inhibited if both the true and complement fuses of any input (I,P) are left intact.
3. To prevent simultaneous Set and Reset flip-flop commands, this state is not allowed for Nand F link pairs coupled to active gates Tn (see
flip-flop truth tables).
4. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn.
November 1989
327
I
Signetics Programmable Logic Devices
Preliminary Specification
Field-Programmable logic Sequencer (16 x 48 x 8)
PlUS105-55
FPLS PROGRAM TABLE
PROGRAM TABLE ENTRIES
________A_N'p_______
CUSTOMER NAME
PURCHASE ORDER _
tNACTIVE
PROPAGATE
CUSTOMER SYMBOLIZED PART 1/
PROGRAM TABLE
•
INACTIVE
,
I, P
I H
DON'TeARE
I
rr,r-~L
-
DATE
Im,P,
SET
I
RESET
I l
I
NO
r -
-
"
, -,
Cn
M
, •
IFf' , . -.r, . .I
2
1
0
,•
-O-PTIOt,j-- - - - -
,I IPRUET!HI
i5l
I
PIE
'l
OR
~<4~3
"2'-,-
0
•
•
-'--
--
OPTION (PtE)
PRESENT STATE (P,)
INPUT(lm)
3
-
.... F,
CHANGE : -,
r-----------------
AND
T
E
H
I
I
,
0
I 0
INACTIVE
I
Cn
-
TRANSPARENT
TOTAL NUMBER OF PARTS
REV
I
+ ______ 2.!1_______
I
0
A
GENERATE
CF (XXXX)
SIGNETICS DEVICE.
:
,
.',',,','0
REMARKS
-~-----
NEXT STATE (Nil'
,
'54"2
OUTPU1(Ff')
0
7
5
, -rr
••
•
2
3
r,-c.
L.
e
8
11
·
1
17
-.-- f--r--- r-
•••
•,
•
•
12
,3
14
••
+
·
~.
·•
2'
2
23
•
•
•
•
26
9
1
•
•
•
•
38
,
·
·••
27
6
37
·•
•
,
·•
o
t-
-"-
I
·••
,
,
••
•
·
4
41
,
43
44
4
47
PIN
NO
,,
2
0
2
2
UJ
-'UJ
~::I!
-<
~z
>
2
3
·
2
4
2: 2
51 •
2
7
2
J
4
5
7
9
I
1
2
3
0
I
I I
, ,
1
• •
1
,
• I
•",I·
•
7
I I
I
II
!
NOTES:
1. The FPLS is shipped with all links initially intact. Thus, a background of "0" for all Terms, and an "H" for the PIE option, exists in the table,
shown BLANK instead for clarity.
2. Unused C n, 1m, and Ps bits are normally programmed Don't Care (-j.
3. Unused Transition Terms can be left blank for future code modification, or programmed as (-) for maximum speed.
4. Letters in variable fields are used as identifiers by logic type programmers.
November 1989
328
Signetics
PLUS405-37/-45
Document No. 853-1280
ECN No.
97039
Date of Issue
July 7, 1989
Status
Product Specification
Field-Programmable Logic
Sequencers (16 x 64 x 8)
I Programmable Logic Devices
I
DESCRIPTION
PIN CONFIGURATIONS
FEATURES
The PLUS405 devices are bipolar, programmable state machines of the Mealy type. Both
the AND and the OR array are user--programmabie. All 64 AND gates are connected to the
16 external dedicated inputs (1 0 -1,5) and to the
feedback paths of the 8 on-chip State Registers (Opo - OP?). Two complement arrays support complex IF-THEN-ELSE state transitions
with a single product term (input variables Co,
C,).
N Package
• 50 and 58.8MHz minimum guaranteed
clock rates
vce
• 37 and 45MHz minimum guaranteed
operating frequencies (1/(t,s 1 + tCK01)
I.
I.
• Functional superset of PLS105/105A
• Field-programmable (Ti-W fusible link)
',0
.16 input variables
'"
112
• 8 output functions
All state transition terms can include True,
False and Don't Care states of the controlling
state variables. All AND gates are merged into
the programmable OR array to issue the nextstate and next-''''''8' c ...
5. Clock 2 is inactive.
July 7,1989
331
Product Specification
Signetics Programmable Logic Devices
Field-Programmable Logic
Sequencers (16 x 64 x 8)
PLUS405-37/-45
FUNCTIONAL DIAGRAM
Po
W~~T~~i'/ClK
=
July 7,1989
332
1111110£
Signetics Programmable Logic Devices
Product Specification
Field-Programmable Logic
Sequencers (16 x 64 x 8)
PLUS405-37/-45
LOGIC DIAGRAM
p~T_AI!-~
...... _ ...........
... ......
NOTE:
1$ Denotes a programmable fuse location.
July 7,1989
333
,
Jl!IT,LO!: ~
P-roduct Specification
Signetics Programmable Logic Devices
Field-Programmable Logic
Sequencers (16 x 64 x 8)
PLUS405-37/-45
DETAILS FOR REGISTERS FOR PLUS405
r .................................................. .. ;;.;;~~ ..
r---------------------------------~
~
TO AND
ARRAY
STATE REGISTERS
=
S orJ
.---------l--'18 INTIOE
P
··
•
~---------------------------------
DelaiiA
DelailB
,----------------------------------
,----------------------------------
TOINITUNE
OUTPUT REGISTERS
SurJ
~sfCl.K)
.
I
FROM
PlN1CLK
=
~--------------------------------DelallD
~--------------------------------Detail C
July 7,1989
..rl_~~_
• FROM PIN 4
Q~----l--I
334
Product Specification
Signetics Programmable Logic Devices
Field-Programmable Logic
Sequencers (16 x 64 x 8)
PLUS405-37/-45
ORDERING INFORMATION
OPERATING
FREQUENCY
DESCRIPTION
28-Pin Plastic DIP (6oomil-wide)
ORDER CODE
45MHz (tiS' + !eKO')
PLUS40!>-45N
28-Pin Plastic DIP (6oomil-wide)
37M Hz (tiS' + !eKO,)
PLUS405-37N
28-Pin Plastic Leaded Chip Carrier
45MHz (tiS' + !eKO')
PLUS40!>-45A
37MHz (tiS' + !eKO')
PLUS405-37A
28-Pin Plastic Leaded Chip Carrier
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
Vee
Supply voltage
V IN
Input voltage
VOUT
Output voltage
liN
Input currents
lOUT
Output currents
TA
Operating temperature range
TSTG
Storage temperature range
RATINGS
UNIT
+7
Voc
+5.5
Voc
+5.5
Voc
~Oto
+30
rnA
+100
rnA
o to +75
°c
----r-
10
I
I
I
I
o--l---
Fo~
I
I
F71-l-
DUT
Rz
1'5
0 - - CK
=~
..sv
Vee
INlTttlE
GND
!----o
OV
~ L~
tFJ
2.5110
CL
ONCLUDES
SCOPE AND JIG
CAPACITANCE)
iL-
~-Jt
2.5110
~
~~
2.5110
2.5110
MEASUREMENTS:
AU circuit delays are measured at the + 1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
LOGIC PROGRAMMING
INITIALlZATIONiOE OPTION - (INITiOE)
PLUS405 Logic designs can be generated
using Signetics AMAZE design software or
several other commercially available, JEDEC
standard PLD design software packages.
Boolean and/or state equation entry format is
accepted.
PLUS40510gic designs can also be generated
using the program table format detailed on the
following page(s). This Program Table Entry
format (PTE) is supported by the Signetics
AMAZE PLD design software. AMAZE is available free of charge to qualified users.
To implement the desired logic functions, each
logic variable (I, B, P, S, T, etc.) from the logic
equations is assigned a symbol. TRUE,
COMPLEMENT, PRESET, RESET, OUTPUT
ENABLE, INACTIVE, etc., symbols are defined
below.
f«=
IIIT---O
I
IIT/OE
LY--E=,
OPTION
INITIAUZATlON'
I
(ALWAYS
ENABLED)
CODE
I
INIT=O
~
E
(INITIAUZATION
DISABLED)
OPTION
"::"
CODE
L
H
PROGRAMMING THE PLUS405:
The PLUS405 has a power-up preset feature. This feature insures that the device will power-up
in a known state with all register elements (State and Output Register) at logic High (H). When
programming the device it is important t1trsalize this is the initial state of the device. You must
provide a next state jump if you do not wish to use all Highs (H) as the present state.
PRESET/RESET OPTION - (P/R)
July 7,1989
ACTION
CODE
PRESET
H
RESET
341
INDETERMINATE4
Signetics Programmable Logic Devices
Product Specification
Field-Programmable Logic
Sequencers (16 x 64 x 8)
PLUS405-37/-45
i
i
'
p
1i
'
P
1
'p
1
"AND" ARRAY - (I), (P)
~P
I,P
~p
r,p
r,p
Tn
I,P
Tn
1~p
r,p
i;ii
Tn
Tn
STATE
STATE
STATE
STATE
INACTlVE',2
I,P
i, P
DON'TCARE
"OR" ARRAY - J-K FUNCTION - (N), (F)
"±g[J "±g[J "±g[J "±g[J
Jir,F
I
Jir,F
K
ACTION
I
TOGGLE6
CODE
0
I I
Jir,F
K
ACTION
SET
I
CODE
H
I
I
Jir,F
K
ACTION
RESET
I
CODE
l
I I
K
ACTION
NO CHANGE
I
CODE
-
I
"COMPLEMENT" ARRAY - (C)
G1: G1: G1: G1:
Tn
I
ACTION
INACTlVE',3
I
CODE
0
I I
GENERATE
I
CODE
A
Tn
Tn
Tn
ACTION
I I
ACTION
PROPAGATE
I
CODE
•
I
I
I
ACTION
TRANSPARENT
CLOCK OPTION - (CLK1/CLK2)
ClK2
ClK2
ClK,
ClK'
OPTION
CLK, ONLY'
CODE
I
OPTION
CODE
H
NOTES:
1. This is the initial unprogrammed state of all links.
2. Any gate Tn will be unconditionally inhibited if anyone of its I or P link pairs is left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn.
4. These states are not allowed when using PRESET/RESET option.
5. Input buffer 15 must be deleted from the AND array (i.e., all fuse locations "Don't Care") when using second dock option.
6. A single product term cannot drive more than 8 registers by itself when used in TOGGLE mode.
July 7,1989
342
I
I
CODE
-
I
I
Signetics Programmable Logic Devices
Product Specification
Field-Programmable Logic
Sequencers (16 x 64 x 8)
PLUS405-37/-45
PLUS405 PROGRAM TABLE
AND
c- _________________
- - - - - _ _ _ _ 1I
INACTIVE
0
~,P
Him, Ps
I, P
DON'T CARE
l
-
I
OPTIONS
'
_____ OR
--- - - - -1------------I
'iNACTIVE 6R-r;
I
FW"NlT
I
H
r----=O----r,;
TOGGLE
I INiTIOE
__~_~~..A
Cn
I SET
H
No, Fr
I ~ ____l_
PROPAGATE.
I RESET
L
I I eLK, ONLY
L I elK1I
TRANSPARENT i - I r-----c--cI
I NO CHANGE
I I ClK, AND 2
H I ClK2
INACTIVE
I
I 0
r-,---,--,l~ITIALIZATIONI )lJ'TPlJTEli=
CLOCK
'12
I
I
I
I
~~r_----------------A~N~D~----_,r_-------------
;~::y
,
INPUT (1m)
R
NEXT STATE (No)
PRESENT STATE (Ps)
Cl CO 115 114 113112 111 110 19 18 17 16 15 14 13 12 11
10 P7 P6 P5 P4 P3 P2 Pl PO
OUTPUT (Fr)
IN? N NSIN4IN:1 N "' NO F7 F6
F4
Fl Rl
f-
2
4
5
l-8
9
,
W
~
1-
1--1-1-1--
11
0
12
f-+-
1
4
-
6
7
W
--'
CO
2Q
~
22
C!)
25
«
a:
1--
1-
--
,
c-
--lI-I--f--
0
>
W
a:
a: a..
1
--
-t
I--
"
~
-
i-Ij--f--- -1-1-1---
1-1--1---
-+
1---
-t--
I--
--l--
--
26
29
29
32
33
34
~C+_+_t_++__1-L--+--t-t___i__-f_+-+-1
-
J
40
-- -lI--
42
4
I-
38
_~9
X
X
X
~
LL
:tl:
01
0
« :; >a:
0 a:
~
~
0 ii5 0
-+- -
-±-t-
-~-
-
45
- c--
)-
a:
~
-
T
4
48
4.
0
W
N
=II:
W
W
~
Z
W
~
:J
0
CO
~
W
Cl
(/)
f=
:::>
Z
C!)
56
57
(/)
W
~
W
(/)
52
53
(/)
:::>
60
61
63
PIN NO,
2
2
~n
UJ
2 3 4 5 6 789
PIN
LABELS
NOTES:
1. The FPLS Is shiwed with aJl1inks initially intact. Thus. a background of -0" for at! Terms. and an
~Hn
for the INIE and H lor the clock option, exists in the table. shown BLANK instead
forciarity.
2.
3.
Unused en 1m, and Ps bits are normally programmed Don't Care (-).
Unused Transition Tarrns can be left blank for future code modification,
July 7,1989
Of
programmed as (-) for maximum speed.
343
Signetics
PLUS405-55
Document No.
ECN No.
Date of Issue
October 1989
Status
Preliminary Specification
Field-Programmable Logic
Sequencer (16 x 64 x 8)
Programmable Logic Devices
DESCRIPTION
The PLUS405-55 device is a bipolar, program·
mabie state machine of the Mealy type. Both
the AND and the OR array are user-program·
mabie. All 64 AND gates are connected to the
16 external dedicated inputs (10-1,5) and to the
feedback paths of the 8 on·-chip State Regis·
ters (Opo - OP7)' Two complement arrays
support complex IF-THEN-·ELSE state transi·
tions with a single product term (input variables
Co, C , ).
All state transition terms can include True,
False and Don't Care states of the controlling
state variables. All AND gates are merged into
the programmable OR array to issue the nextstate and next-<>utput commands to their reo
spective registers. Because the OR array is
programmable, anyone or all of the 64 transi·
tion terms can be connected to any or all of the
State and Output Registers.
All state (Opo - 0P7) and output (OFO - OF7)
registers are edge-triggered, clocked J-K flipflops, with Asynchronous Preset and Reset
options. The PLUS405 architecture provides
the added flexibility of the J-K toggle function
which is indeterminate on 8-R flip-flops. Each
register may be individually programmed such
that a specific Preset-Reset pattern is initial·
ized when the initialization pin is raised to a logic
level "1 ". This feature allows the state machine
to be asynchronously initialized to known
internal state and output conditions prior to
proceeding through a sequence of state transi·
tions. Upon power-up, all registers are
unconditionally preset to "1 ". If desired, the
initialization input pin (INIT)can be converted to
an Output Enable (GE) function as an additional
user-programmable feature.
Availability of two user-programmable clocks
allows the user to design two independently
clocked state machine functions consisting of
four state and four output bits each.
Order codes are listed in the Ordering
Information Table.
PIN CONFIGURATIONS
FEATURES
N Package
• 62.5MHz minimum guaranteed clock
rate
vcc
• 55MHz minimum guaranteed operating
frequency (11(tI81 + ICK01)
I.
I.
• Functional superset of PLS1051105A
1, 0
• Field-programmable (Ti-W fusible link)
111
• 16 input variables
112
• 8 output functions
1,3
• 64 transition terms
114
• 8-bit State Register
115
• 8-bit Output Register
INIT/lYE
• 2 transition Complement Arrays
Fo
• Multiple clocks
F,
F2
• Programmable Asynchronous
Initialization or Output E1iillIe
• Power-on preset of all registers to "1"
• "On-chip" diagnostic lest mode
features for access to state and output
registers
F3
N = Plastic
A Package
17
CLK Vce Is
19
• 950mW power dissipation (typ.)
1,0
• TIL compatible
111
• J~ or 8-R flip-flop functions
112
• Automatic "Hold" states
,,.
'13
• 3~tale outputs
115
INiT/UE
APPLICATIONS
• Interface protocols
• Sequence detectors
FS F4 GND F3
F2 Fl
FO
A"" Plastic Leaded Chip Carrier
• Peripheral controllers
• Timing generators
• Sequential circuits
• Elevalor conlollers
• Security locking systems
• Counters
• Shift registers
PHILIPS
344
Signetics Programmable Logic Devices
Preliminary Specification
Field-Programmable
Logic Sequencer (16 x 64 x 8)
PLUS405-55
PIN DESCRIPTION
!'INNO.
SYMBOL
NAME AND FUNCTION
POLAR!TY
I
CLKI
Clock: The Clock input to the State and Output Registers. A Low-to-High transition on
this line is necessary to update the contents of both registers. Pin I only clocks Po _ 3 and
Fo _ 3 if Pin 4 is also being used as a clock.
Active-High (H)
2,3,5-9,
26-27
20-22
10 -14,17 16
18 -l g '
Logic Inputs: The 12 extemal inputs to the AND array used to program jump conditions
between machine states, as determined by a given logic sequence. True and complement
signals are generated via use of "Wand "L ".
Active-High/Low
(H/L)
4
CLK2
1'3 -1,5
Logic Inpul/Clock: A user programmable function:
• Logic Input: A 13th extemallogic input to the AND array, as above.
Active-High/Low
(H/L)
• Clock: A 2nd clock for the State Registers P4 - 7 and Output Registers F4 _ 7, as above.
Note that input buffer 15 must be deleted from the AND array (Le., all fuse locations "Don't
Care") when using Pin 4 as a Clock.
Active-High (H)
23
1'2
Logic/Diagnostic Input: A 14th extemallogic input to the AND array, as above, when
exercising standard TIL or CMOS levels. When 1,2 is held at + IOV, device outputs Fo - F7
reflect the contents of State Register bits Po - P7. The contents of each Output Register
remains unaltered.
Active-High/Low
(H/L)
24
111
logic/Diagnostic Input: A 15th extemallogic input to the AND array, as above, when
exercising standard TIL levels. When I" is held at +IOV, device outputs Fa - F7 become
direct inputs for State Register bits Po - P7; a Low-to-High transition on the appropriate
clock line loads the values on pins Fo - F7 into the State Register bits Po - P7. The
contents of each Output Register remains unaltered.
Active-High/Low
(H/L)
25
110
logic/Diagnostic Input: A 16th extemallogic input to the AND array, as above, when
exercising standard TIL levels. When 110 is held at +IOV, device outputs Fo - F7 become
direct inputs for Output Register bits 0 0 -~; a Low-to-High transition on the appropriate
clock line loads the values on pins Fo - F7 into the Output Register bits 0 0 - 0 7, The
contents of each State Register remains unaltered.
Active-High/Low
(H/L)
10-13
15-18
Fo- F7
Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which
normally reflect the contents of Output Register Bits 0 0 - 0 7, when enabled. When 1,2 is
held at +IOV, Fo- F7 = (po- P7). When 111 is held at +IOV, Fo- F7 become inputs to State
Register bits Po - P7. When 110 is held at + IOV, Fo - F7 become inputs to Output Register
bits 0 0 -07,
Active-High (H)
19
INIT/OE
Initialization or Output Enable Input: A user programmable function:
October 1989
• Initialization: Provides an asynchronous preset to logic "I" or reset to logic "0" of all
State and Output Register bits, determined individually for each register bit through user
programming. IN IT overrides Clock, and when held High, clocking is inhibited and Fo - F7
and Po - P7 are in their initialization slate. Normal clocking resumes with the first full clock
pulse following a High-to-Low clock transition, after INIT goes Low. See timing definition
for INvcK and tVCK.
Active-High (H)
• Output Enable: Provides an output enable function to buffers Fo - F7 from the Output
Registers.
Active-Low (L)
345
Signetics Programmable Logic Devices
Preliminary Specification
Field-Programmable
logic Sequencer (16 x 64 x 8)
PlUS405-55
TRUTH TABLE 1, 2, 3, 4, 5, 6, 7
OPTION
Vcc
.
111
.
.1,2
.
CK
J
K
Qp
QF
F
H
x
H/L
OF
X
X
X
X
i
i
i
i
Op
Op
L
L
H
H
L
OF
L
H
X
.
X
X
X
X
X
X
~
~
~
H
+10V
Op
OF
Hi-Z
i
i
i
i
x
x
x
x
Op
Op
Op
~
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H/L
X
X
x
x
x
x
x
~
i
i
i
i
L
L
Op
OF
OF
OF
~
OF
L
H
L
L
L
H
L
H
H
H
H
H
ap
X
H
OF
_Ii
OF
x
INIT
O"E
L
+10V
L
+10V
L
X
X
X
X
X
L
L
L
H
X
X
X
X
+5V
+10V
+10V
X
X
X
X
X
+10V
X
X
+10V
L
X
X
X
X
X
X
X
X
x
x
x
x
x
x
x
x
L
L
L
x
+10V
+10V
X
X
X
X
L
L
i
1'0
+10V
X
x
Op
~
H
Op
L
L
H
H
L
H
Op
~
OF
NOTES:
1. Positive Logic:
SIR (orJ/K) = To + T, + T2 + ... T63
Tn = (Co, C,)(lo, I.. 12, ...) (Po, P" ... P7)
2. Either Initialization (Active-High) or Output Enalire (Active-Low) are available, but not both. The desired function is a user-programmable
option.
3. i denotes transition from Low-Io-High level.
4.• = H orLor+10V
5. X = Don't Care (,;;5.5V)
6. H/L implies that either aHigh or a Low can occur, depending upon user-programmed selection (each State and Output Register individually
programmable).
7. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels
on the output pins are forced by the user.
VIRGIN STATE
A factory-shipped virgin device contains all
fusible links intact, such that:
1. INITIOE is set to INIT. In order to use the
INIT function, the user must select either
the PRESET or the RESET option for each
flip-flop. Note that regardless of the userprogrammed initialization, or even if the
INIT function is not used, aU registers are
preset to '1" by the power-up procedure.
lOGIC FUNCTION
Typical State Transition:
I~ I~\~ I ~R
STATE REGISTER
10 10
1'
PRESENT STATE
lI' B'
I
s,,+,
c· ...
NEXT STATE
2. All transition terms are inactive (0).
3. All SIR (or J/K) flip-flop inputs are disabled
(0).
4. The device can be clocked via a Test
Array preprogrammed with a standard test
pattern.
5. Clock 2 is inactive.
October 1989
SET --r
o--L.
--~:i'-±I
'0
FO~
I
I
I
I
I
I
OUT
F7
LL-
R2
0---- CK
INiT/lYE
GND
CL
(INCLUDES
SCOPE AND JIG
CAPACITANCE)
-=
1'5
r---o
2._
-:5-
2.5na
MEASUREMENTS:
All circuk delays are measured at the + 1.SV level of
inputs and outputs. unless otherwise specified.
Input Pulses
LOGIC PROGRAMMING
INITIALIZATION/OE OPTION - (INIT/OE)
PLUS405 Logic designs can be generated
using Signetics AMAZE design software or
several other commercially available, JEDEC
standard PLD design software packages.
Boolean and/or state equation entry format is
accepted.
PLUS405 logic designs can also be generated
using the program table format detailed on the
following page(s). This Program Table Entry
format (PTE) is supported by the Signetics
AMAZE PLD design software. AMAZE is available free of charge to qualified users.
To implement the desired logic functions, each
fogic variable (I, B, P, S, T, etc.) from the logic
equations is assigned a symbol. TRUE,
COMPLEMENT, PRESET, RESET, OUTPUT
ENABLE, INACTIVE, etc., symbols are defined
below.
~
INiT
E=1
_
-
I
I
OPTION
INITIAUZATION'
(ALWAYS
ENABLED)
I
I
CODE
H
I
I
mIT.o
~
E
(INITIAUZATION
DISABLED)
OPTION
-=
CODE
PROGRAMMING THE PLUS405:
The PLUS405 has a power-up presetfeature. This feature insures thatthe device will power-up
in a known state with all register elements (State and Output Register) at logic High (H). When
programming the device it is important to realize this is the initial state of the device. You must
provide a next state jump if you do not wish to use all Highs (H) as the present state.
PRESET/RESET OPTION - (P/R)
October 1989
NlT!OE
N1T!OE
ACTION
CODE
PRESET
H
RESET
356
Signetics Programmable Logic Devices
Preliminary Specification
Field-Programmable
Logic Sequencer (16 x 64 x 8)
PLUS405-55
l
'
p
il'p
ii'
P
i'p
i
"AND" ARRAY - (I), (P)
I,P
I,P
_
r,p:
Tn
I
I
STATE
I,P
_
I,p
Tn
CODE
o
I
I
I,P
_
"P
I,p
Tn
STATE
CODE
STATE
I,P
H
i, P
Tn
CODE
STATE
CODE
DON'TCARE
"OR" ARRAY - J-K FUNCTION - (N), (F)
"fg[] "fg[] "fg[] "fg[]
R;'F
I
R;'F
K
ACTION
I
TOGGLE6
CODE
0
I I
R;'F
K
ACTION
I
SET
CODE
H
I
I
R;'F
K
ACTION
RESET
I
CODE
L
I
I
K
ACTION
NO CHANGE
I
CODE
-
I
"COMPLEMENT" ARRAY - (C)
G1: G1: G1: G1:
Tn
I
ACTION
INACTlVe 1,3
I
CODE
0
Tn
I I
ACTION
GENERATE
I
CODE
A
Tn
Tn
I I
ACTION
PROPAGATE
I
CODE
•
I I
ACTION
TlIANSPARENT
CLOCK OPTION - (CLK1/CLK2)
CLK2
CLK2
CLKt
CLKt
OPTION
CODE
CLKt ONLy2
L
I
OPTION
CODE
H
NOTES:
1. This is the initial unprogrammed state of all links.
2. Any gate Tn will be unconditionally inhibited if anyone of its I or P link pairs is left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn.
4. These states are not allowed when using PRESET/RESET option.
5. Input buffer Is must be deleted from the AND array (i.e., all fuse locations "Don't Care") when using second clock option.
6. A single product term cannot drive more than 8 registers by itself when used in TOGGLE mode.
October 1989
357
I
CODE
-
I
Signetics Programmable Logic Devices
Preliminary Specification
Field-Programmable
Logic Sequencer (16 x 64 x 8)
PLUS405-55
PLUS405 PROGRAM TABLE
r-----------~A~N~D~--------------r-I----~O~R~-----.-I--~O~P=T~IO~N7.S~---,
~----------------------I----------I----------INACTIVE
0
I, P
H
INACTIVE
1m, Po
I ~1~lm1E OR
!0
GENERATE
A
I, P
l
PROPAGATE.
DON'T CARE
-
TRANSPARENyt -
Cn
SET
I
RESET
l
NO CHANGE
-
i
i IINIT
!0
I
H
No, Fr
I H IINITIOE
Il
I
UE
Il
CLKI ONLY
il
CLKI AND.
~l J
ClK1I
~ HJ CLK2
INiTlALlZATI
CLOCK 112
R
AND
COMPo
ARRAY
INPUT (1m)
PRESENT STATE (Po)
NEXT STATE (No)
7LN1 N5 NO N3lH1 NI NI
OUTPUT (Fr)
F6lfil.!'!l.HLlll
I
'1
~
•3
5
6
UJ
!;i:
o
"
13
14
1
16
UJ
1
1
-'
ro
19
20
~
1
::2;
«a::
23
G
>
0
UJ
a::
a:: Q.
0;
28
30
33
34
35
38
39
.
1
4.
xx
x
"*'
~
I-
()
ct
u.
a::
0
=1:1:
W
::2;
UJ
()
~
en
::J
()
i=
ro
55
:J
0
::2;
~
en
Ci5
()
UJ
so
51
5.
Z
G
46
47
UJ
N
::2;
:> >«z w
en
0
a:: en a::
UJ ()
UJ
::2;
44
45
::J
59
59
61
62
63
PIN NO.
~.~ I ~ I ~ i : I ~ I ~ I ~
•
3
4 5
6 7 8
9
1 1 1 1 1
PIN
LABELS
NOTES:
1.
The FPlS is shJwed wfth all links Initially intact. Thus. a background of "0" for all Terms, and an ~H" for the INiE and H for the clock or:fion. exists in the table. shown BLANK Instead
for clarity.
2.
Unused en 1m, and
3.
Ps bits are normally programmed Don't Care (-).
Unused Transition Terms can be left blank tor future code modification, or programmed as (-) for maximum speed.
October 1989
358
1
Signetics
Section 6
Programmable Macro Logic
Data Sheets
Programmable Logic Devices
INDEX
PLHS501
PLHS502
PLHS601
PML2552
Programmable
Programmable
Programmable
Programmable
Macro
Macro
Macro
Macro
Logic. _.........................
Logic ...........................
Logic ...........................
Logic ...........................
361
372
384
395
1-
Signetics
PLHS501
Document No. 853-1207
ECN No.
98069
Date of Issue
November 10, 1989
Status
Product Specification
Programmable Macro Logic
PMLTM
II
I Programmable Logic nevices
I
FEATURES
STRUCTURE
DESCRIPTION
• Programmable Macro Logic device
• NAND gate based architecture
- 72 foldback NAND terms
The PLHS501 is a high-density Bipolar
Programmable Macro Logic device. PML
incorporates a programmable NAND
structure. The NAND architecture is an
efficient method for implementing any
logic function. The SNAP software development system provides a user friendly
environment for design entry. SNAP
eliminates the need for a detailed
understanding of the PLHS501 architecture and makes it transparent to the user.
PLHS501 is also supported on the
Signetics AMAZE software development
system.
• Full connectivity
• TTL compatible
• SNAP development system
- Supports third-party schematic
entry formats
- Macro library
- Versatile nellist format for design
portability
- Logic, timing, and fault
simulation
• AMAZE development system:
- Supports third-party schematic
entry formats
- Boolean equation entry
- Logic, timing, and fault
simulation
• Delay per internal NAND
function = 6.5ns (typ)
• Testable in unprogrammed state
• Security fuse allows protection of
proprietary designs
• 104 Input-wide logic terms
.44 additional logic terms
• 24 dedicated inputs (10 -Id
• 8 bidirectionalllOs with individual
3-State enable:
- 4 active-High (B4 - B 7 )
- 4 active-Low ('8'0 - 8 3)
• 16 dedicated outputs:
- 4 active-High outputs
0 0 , 0, with common 3-State
enable
O2, 0 3 with common 3-State
enable
- 4 active-Low outputs:
'04, 'Os with common 3-State
enable
'06, '07 with common 3-State
enable
- 8 Exclusive-OR outputs:
Xo - X3 with common 3-State
enable
~ - X7 with common 3-State
enable
The PLHS501 is ideal for a wide range of
microprocessor support functions, including bus interface and control applications.
PML is a trademark of Philips Components-S;gnetics
PHILIPS
361
Product Specification
Signetics Programmable Logic Devices
PLHS501
Programmable Macro Logic
PIN CONFIGURATION
A Package
(52-pln PLCC)
ARCHITECTURE
The core of the PLHS501 is a programmable
fuse array of 72 NAND gates. The output of
each gate folds back upon itself and all other
NAND gates. In this manner, full connectivity of
all logic functions is achieved in the PLHS501.
Any logic function can be created within the
core of the device without wasting valuable I/O
pins. Furthermore, a speed advantage is acquired by implementing multi--levellogicwithin
a fast internal core without incurring any delays
from the 1/0 buffers.
DESIGN DEVELOPMENT TOOLS
The SNAP Software Development System provides the necessary tools for designing with
PML. SNAP provides the following:
SNAP operates on an IBM® PC/XT, PC/AT,
PS/2, or any compatible system with DOS 2.1
or higher. The minimum system configuration
for SNAP is 640K bytes of RAM and a hard disk.
SNAP provides primitive PML function libraries
for third-party schematic design packages.
Custom macro function libraries can be defined
in schematic or equation form.
After the completion of a design, the software
compiles the design for syntax and completeness. Complete simulation can be carried out
using the different simulation tools available.
The programming data is generated in JEDEC
format. Using the Device Programmer Interface (DPI) module of SNAP, the JEDEC fusemap is sent from the host computer to the
device programmer.
• Schematic entry netlist generation from thirdparty schematic design packages such as
AMAZE
The AMAZE PLD Design Software development system also supports the PLHS50 1.
AMAZE provides the following capabilities for
the PLHS501:
• Schematic entry nellist conversion from
third-party schematic software
• Boolean equation entry
• Logic and timing simulation
• Automatic test vector generation
AMAZE operates on an IBM PC/XT, PC/AT,
PS/2, or any compatible system with DOS 2.0
or higher. The minimum system configuration
for AMAZE is 640K bytes of RAM and a hard
disk.
AMAZE compiles the design after completion
for syntax and completeness. Programming
data is generated in JEDEC format.
OrCAD/SDT IJlTM and FutureNet™
• Macro library for standard PLHS50 1
functions and user defined functions
DESIGN SECURITY
The PLHS501 has a programmable security
fuse that controls the access to the data
programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or
retrieved.
• Boolean equation entry
• State equation entry
• Syntax and design entry checking
• Simulator includes logic simulation, fault
simulation and timing simulation.
FutureNet is a trademark of FutureNet Corporation.
OrCAOJSDT is a trademark of DreAD, Inc.
IBM is a registered trademark of International Business Machines Corporation.
November 10, 1989
362
Signetics Programmable Logic Devices
Product Specification
Programmable Macro Logic
PLHS501
PLHS501 FUNCTIONAL BLOCK DIAGRAM
24
DEDICATED
INPUTS
I
N
T
E
R
C
NAND
ARRAY
o
N
N
E
C
T
16
DEDICATED
OUTPUTS
8
BIDIRECTIONAL
IIOS
November 10,1989
363
Signetics Programmable Logic Devices
Product Specification
PLHS501
Programmable Macro Logic
FUNCTIONAL DIAGRAM
,V®
0
7'
" ""
10
.>
!
123
;;~
0.
x2
x2
....
November 10.1989
364
x2
0,.
0 ••
Os.
Product Specification
Signetics Programmable Logic Devices
PLHS501
Programmable Macro Logic
ORDERING INFORMATION
ORDER CODE
DESCRiPTiON
52-Pin Plastic Leadec Chip Carrier
PLHS501A
ABSOLUTE MAXIMUM RATlNGS1
RATINGS
SYMBOL
Max
UNIT
+7
Vrx;
Input voltage
+5.5
Vrx;
VOUT
Output voltage
+5.5
Vrx;
liN
Input currents
lOUT
Output currents
TA
Operating temperature range
TSTG
Storage temperature range
PARAMETER
Vee
Supply voltage
VIN
Min
+30
mA
+100
mA
0
+75
°c
-B5
+150
°c
-30
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other oondition above those indicated in the operational and programming specification of the device is not implied.
THERMAL RATINGS
VIRGIN STATE
TEMPERATURE
Maximum junction
150°C
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
A factory shipped virgin device contains all fusible links open, such that:
1. All product terms are enabled.
2. All bidirectional (8) pins are outputs.
3. All outputs are enabled.
75°C
4. All outputs are active-High except
"So - Bo (fusible 1/0) and 0 4 are active-Low.
November 10, 1989
365
0 7 which
Product Specification
Signetics Programmable Logic Devices
PLHS501
Programmable Macro Logic
DC ELECTRICAL CHARACTERISTICS DOC -< TA -< +75°C, 4.75V oS; Vee -< 5.25V
UMITS
SYMBOL
PARAMETER
TEST CONDITION
Min
Vce = Min
Vee = Max
Vee = Min, liN =-12mA
2.0
Typ'
Max
UNIT
O.B
V
V
V
Input voltage2
Low
High
Cl amp 2.3
VIL
VIH
Vr:;
-{l.B
-1.2
Output voltage
Vee = Min
10L = 10mA
10H =-2mA
Low·'
High 2,5
VOL
VOH
0.45
V
V
2.4
Input current
Vee = Max
IlL
Low
VIN = 0.45V
-100
~
IIH
High
VIN = 5.5V
40
~
BO
-140
-70
~
mA
295
mA
Output current
Vee = Max
10(OFF)
Hi-Z state 9
los
Short circuit3 . 5, 6
Icc
Vee supply currenti'
VOUT = 5.5V
VOUT = 0.45V
VOUT = OV
-15
225
Vee = Max
Capacitance
Vee = 5V
Input
CIN
8
VIN = 2.0V
CB
110
15
VOUT = 2.0V
NOTES:
1. All typical values are at Vee = 5V, TA = +2SoC.
2. All voltage values are with respect to network ground terminaL
3. Test one at a time.
4. For Pins 15 - 19, 21 - 27 and 37 - 40, VOL is measured with Pins 5 and 41 = 8,75V, Pin 43 = OV and Pins 42 and 44 = 4.5V.
For Pins 28 - 33 and 35 - 36, VOL is measured under same conditions EXCEPT Pin 44 = OV.
5. VOH is measured with Pins 5 and 41 = 8.75V, Pins 42 and 43 = 4.5V and Pin 44 = OV.
6. Duration of short circuit should not exceed 1 second.
7. Icc is measured with all dedicated inputs at OV and bidirectional and output pins open.
8. Measured at VT = VOL + 0.5V.
9. Leakage values are a combination of input and output leakage.
TEST LOAD CIRCUITS
VOLTAGE WAVEFORMS
~.~
? vec
+sv
~ 10
I
I
o--l---
<>-ro-L-..
T J:n"~-'
AND JIG
I
I
I
,,"~O"~'
By
I,.
BW
Bz
Ox
BX
GNO
..-l-
-
R2
I
Cl
-=-=
ov
~ LtR tFJ C
2.508
2.Sna
~:~
2.5ns
~
2.5na
MEASUREMENTS:
All circuit delays are measured at the +1.SV level
of inputs and outputs, unless otherwise specified.
Input Pulses
November 10, 1989
pF
pF
366
Product Specification
Signetics Programmable Logic Devices
PLHS501
Programmable Macro Logic
SNAP RESOURCE SUMMARY DESIGNATIONS
11
1.1 . . . .
.. .
~
0
~~;I
123
2
ul: 16 p-terms on X or Y.
NAND Output Buffer with 3-State Control
(TOU501)
~
Tri-Clrl
In--D~orn
PARAMETER
SYMBOL
To
(Output)
From
(Input)
IpHL
lpLH
Out
Out
In
In
taE
taD
Out
Out
Tri-Ctrl
Tri-Ctrl
LIMITS
UNIT
Min
Typ
Max
8.5
8.5
14.0
14.0
17.5
16
ns
ns
8.5
8.5
15
12.5
18.5
17.0
ns
ns
Output Pins: 24 - 27.
Internal Foldback NAND
(FBNAND)
Input
D
Output
LIMITS
SYMBOL
Min
Typ
Max
UNIT
LltpHL
0.05
0.1
0.15
nsip-term
LltpLH
-0.0
-0.05
-0.1
nsip-term
PARAMETER
LIMITS
SYMBOL
To
(Outpul)
From
(Input)
Min
Typ
Max
lpHL
lpLH
Out
Any
4.0
5.5
4.5
6.5
6.8
8
UNIT
NOTES
ns
ns
With 0 p-terms load
Maximum internal loading of 16 terms.
1. Limits are guaranteed with Internal feedback buffers simultaneously sWitching cumulative max,mum of eight outputs.
November 10, 1989
368
Signetics Programmable Logic Devices
Product Specification
Programmable Macro Logic
PLHSS01
MACRO CELL SPECIFICATIONS (Continued) T A ~ O°c to +75°C, 4.75V s Vce s 5.25V, CL ~ 30pF, R2 ~ 10000., R, ~ 4700.
(SNAP Resource Summarv DesiQnations in Parantheses)
AND Output Buffer with 3-State Control
(NOU50l)
Tri--Ctr1
------1
In
Out
PARAMETE,R
LIMITS
--
SYMBOL
To
(Output)
From
(Input)
Min
Typ
Max
\PHL
\PLH
Output
Output
In
In
8.0
8.0
11
11
13
13
ns
ns
taE
taD
Out
Out
Tri-Ctrl
Tri-Ctrt
8.5
8.5
15
12.5
18.5
17.0
ns
ns
UNIT
Bidirectional and Output Pins: 19, 21, 22, 23, 15 -18.
NAND Output Buffer
(OUTS011
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
Min
Typ
Max
\PHL
\PLH
Out
Out
In
In
8.5
8.5
14
14
17.5
16.0
UNIT
ns
ns
Bidirectional Pins: 37 - 40.
Ex-OR Output Buffer
(EX0501)
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
Min
Typ
Max
\PHL
\PLH
Out
Out
AorB
AorB
8.5
8.5
14
14
17.5
16.0
ns
ns
taE
taD
Out
Out
Tri-Ctrl
Tri-Ctrt
8.5
8.5
15
12.5
18.5
17.0
ns
ns
Ex-OR OUtput Pins: 28 - 33.
November 10,1989
369
UNIT
Product Specification
Signetics Programmable Logic Devices
PLHS501
Programmable Macro Logic
PLHS501 GATE AND SPEED ESTIMATE TABLE
FUNCTION
INTERNAL NAND
EQUVALENT
TYPICAL tpo
1
1
1
1
6.5ns
6.5ns
6.5ns
6.5ns
For
For
For
For
8
16
32
l1ns
llns
l1ns
Inverted inputs available
Inverted inputs available
Inverted inputs available (24 chip outputs only)
15
32
41
llns
llns
llns
Inverted inputs, 2 logic levels
Inverted inputs, 2 logic levels
Inverted inputs, 2 logic levels, factored solution.
5
9
17
28
llns
llns
llns
llns
Inverted inputs available
COMMENTS
f MAX
Gales
NANOs
ANDs
NORs
ORs
1 to 32 input variables
1 to 32 input variables
1 1032 input variables
1 to 32 input variables
Decoders
3-to-8
4-10-16
5-lo~2
Encoders
8-to~
16-t<>-4
32-t0.-5
Multiplexers
4-to--l
8-to-l
16-10--1
27-to--l
Can address only 27 external inputs - more if internal
Flip-Hops
D-type Flip-Flop
T-type Flip-Flop
J-K-type Flip-Flop
30MHz
30M Hz
30MHz
6
6
10
With asynchronous S--R
With asynchronous S--R
With asynchronous S--R
Adders
8-bit
45
15.5ns
72
llns
Full carry-lookahead (four levels of logic)
Barrel Shifters
8-bit
2 levels of logic
Latches
D-Iatch
November 10, 1989
2 levels of logic with one shared gate
3
370
Product Specification
Signetics Programmable Logic Devices
PlHS501
Programmable Macro logic
APPLICATIONS
MASTER
SLAVt
r-------------'r-------,
II
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
II
II
II
II
1\
II
1\
1\
II
1\
II
1\
1\
1\
1\
1\
1\
_JL
I
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_J
LOTIO
NUB US
<~~====~~~~~~
Simplified NuBus™ Diagram (10MHz Operating Frequency)
1::::::::::1----
-ADL
-CDSETUP
-MI-IO
-S1
-SO
-A2
-AI
t.,:.~=-j---
DlR
7-BIT
LATCH
-Ml
,--+--1
r=====I==:j C==:>
-CMD-------~
! d~~=======/I
ly--=--...J
CHRESET
POS
BYTE
POS
BYTe
o
Block Diagram of Basic POS Implementation In PLHSS01
NuBus is a trademark ci Texas Instruments, Inc.
November 10, 1989
BUFEN
371
POS
BYTE 2
DATA OUTPUT
Signetics
Document No. 853-1405
ECN No.
98070
Date of Issue November 10, 1989
Status
Product Specification
PLHS502
Programmable Macro Logic
PMLTM
Programmable Logic Devices
FEATURES
STRUCTURE
DESCRIPTION
• Programmable Macro Logic
• NAND gate based architecture
- 64 fold back NAND terms
The Signetics PML family of PLDs
provides the capability to create fast and
cost effective solutions for a number of
microprocessor interface and control
applications. PML incorporates the
unique feature of a programmable NAND
structure as the basis of its architecture.
• Full connectivity
• Delay per Internal NAND
function 6.5ns
=
=
• Clock frequency 40MHz
Operating frequency 33M Hz
=
• SNAP development system eases
design
- Supports third-party schematic
entry formats
- Macro library
- Versatile nellist format for design
portability
- Logic, timing, and fault simulation
• TIL compatible
• Security fuse allows protection of
proprietary designs
• Testable In unprogrammed state
.80 additional logic terms
.128 Inputs per logic term
• 20 dedicated inputs
• 4 programmable Input/clock Inputs
• 8 Independent clocks
- 4 from input/clock pins
- 4 from NAND array
• 8 bldirectionalllOs
• 16 dedicated outputs
- 8 active-High outputs
- 4 outputs with programmable
polarity
- 4 3-State outputs with programmable polarity and independent
3-State control
• 16 burled flip- flops
- 8 D type
- 8 S-R type
The PLHSS02 is a high-density Bipolar
Programmable Macro Logic Device. The
folded NAND array combined with embedded I/O flip-flops allows for both timing control, wide decoders, multiplexers,
and system input and output bus latches
to be combined onto one device.
APPLICATIONS
• VRAM controllers
• DRAMISRAM controllers
• Multiple state machines
• Timing control
• Error detection/correction
PML is a trademark of Philips Components-$ignetics
PHILIPS
372
Product Specification
Signetics Programmable Logic Devices
Programmable Macro Logic
PLHS502
PIN CONFIGURATION
A Package (68-Pln PLCC)
GNIle
11.
14
13
12
11
VCCS
VCCI
10
015
VCC2
GND2
VCC6
GND6
IBI
013
IB2
012
IB3
N.C.
IB4
On
GND10
010
ARCHITECTURE
The core of the PLHS502 is a programmable
fuse array of64 NAND gates and 16 buried flipflops. The output of each gate and Hip-flop folds
back upon itself and all other NAND gates and
flip-flops. In this manner, full connectivity of all
logic functions is achieved in the PLHS502.
Any logic function can be created within the
core of the device without wasting valuable I/O
pins. Furthermore, a speed advantage is acquired by implementing multi-levellogic within
a fast internal core without incurring any delays
from the I/O buffers.
Buried Flip-Flops
The 16 buried flip-flops can be connected to the
input or output structures through the NAND
array. Intricate state machine designs can be
implemented within the core without any
unnecessary delays from the input or output
buffers. Each flip-flop can be realized as an
input or output register with no constraints.
The Clock Array
There are a combination of 26 possible inputs
to the 'Clock Array':
- 2 are direc~y from the input pins fed
through an inverting buffer.
- 4 inputs with programmable polarity direc~y
from the input pins.
• Boolean equation entry
- 4 inputs from 4 individual NAND terms.
• State equation entry
- 16 inputs from the '0' outputs of the flipflops.
• Syntax and design entry checking
The wide selection of clocking options offers
the user the capacity to create custom and
independent clock functions for the flip-Hops.
This together with the full connectivity of the
device, offers the capability to implement a variety of synchronous and asynchronous state
machines. Another possible application is
implementing multi-phase designs such as
pipe-lined processing.
DESIGN DEVELOPMENT TOOLS
The SNAP Software DevelopmentSystem provides the necessary tools for designing with
PML. SNAP provides the following:
• Schematic entry netlistgeneration from thirdparty schematic design packages such as
OrCADISDT'"M and FutureNet™
• Macro library for standard PLHS502 functions and user defined functions
FutureNEil is a trademark of FuturaNet Corporation.
OrCAD/SOT 16 a trademark of OrCAD. Inc.
IBM 1& a registered trademark oIlnlernalional Business Machines COrporation.
November 10, 1989
373
• Simulator includes logic simulation, fault simulation, and timing simulation.
SNAP operates on an IBM® PCIXT, PC/AT,
PS/2, or any compatible system with DOS 2.1
or higher. A minimum of 640K bytes of RAM is
required together with a hard disk.
SNAP provides primitive PML function libraries
for third party schematic design packages.
Custom macro function libraries can be defined
in schematic or equation form.
After the completion of a design, the software
compiles the design for syntax and completeness. Complete simulation can be carried out
using the different simulation tools available.
The programming data is generated in JEDEC
format. Using the Device Programmer Interface (DPI) module of SNAP, the JEDEC fusemap is sent from the host computer to the
device programmer.
Product Specification
Signetics Programmable Logic Devices
Programmable Macro logic
PlHS502
DESIGN SECURITY
The PLHSS02 has a programmable security
fuse that controls the access to the data
programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or
retrieved.
PLHS502 FUNCTIONAL BLOCK DIAGRAM
24
DEDICATED
INPUTS
A
B
[Q
I
N
T
E
R
C
NAND
ARRAY
(X 64)
0
N
N
E
C
T
E
16
DEDICATED
OUTPUTS
8
C
DFUP-FLOPS
WITH
INDEPENDENT
CLOCKS
F
8
BIDIRECTIONAL
uos
8
D
November 10, 1989
S-RFLIp...
FLOPS WITH
INDEPENDENT
CLOCKS
374
Product Specification
Signetics Programmable Logic Devices
PLHS502
Programmable Macro Logic
,
I
/"
FUNCTIONAL DIAGRAM
A
1o- l
lD
63
1
62
0
'"
x"
.~Ix2
I..,tCll(.l.1ICLK ~
:>
1••IClK, I.:YCLK
~9.,9Y
..,
x8
x8)lx8
Jl Jl Xll~~~r~
x8
x8
x8
I
.II~
~,:;p
If'''4
~+
,
4'0'"0
8
i1
t.
l
1
il
~
j
lH-~R
r-;-o
8
(8
D
8
Q~
R
~LR
8
I
~O8-011
I
\
l
(8)
C
,
~OI'-OI5
.".
(x4)
,
1
!
11Io-IB7
....
(x4)
.....
v
(x8)
00-<>7
F
L.. 1
t!!~..,J~J
t.;
....
TEST LOAD CIRCUITS
VOLTAGE WAVEFORMS
JVCC
By
T
<>-r- Bw
BZ
....l...-
BX
Ox
<>-rI
I
o-l-
o-l-
10
I
I
I
J:DW_.sV
AND JIG
,~"~,
110
GND
I
R.
-
':"
Cl
':"
~
TA=
o·c to +75·C. 4.75s Vccs5.25V. Rl
November 10.1989
~~
W
-J
L. .J c
2.5no
2.5...
:-j\ 'iL..&no
..&no
MEASUREMENTS:
All circuit delays are measured at the + l.5V level of
ill'uts and outputs, unieoo otherwise specllied.
=
470il. ~= looOil. CL =30pF
375
InputPul...
Product Specification
Signetics Programmable logic Devices
PLHS502
Programmable Macro Logic
THERMAL RATINGS
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
68-Pin Plastic leaded Chip Carrier
TEMPERATURE
PlHSS02A
ABSOLUTE MAXIMUM RATINGSl
RATINGS
SYMBOL
PARAMETER
Vee
Supply voltage
VIN
Input voltage
Your
Output voltage
liN
Input currents
lour
Output currents
TA
Operating temperature range
TSTG
Storage temperature range
Min
--30
Maximum junction
1SOoC
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
75°C
Max
UNIT
+7
Vrx;
+5.5
Vrx;
+5.5
Vrx;
1. All bidirectional (8) pins are outputs.
+30
rnA
2. All outputs are enabled.
3. All outputs are active-low except
0 0 - 07, which are active-High.
+100
rnA
0
+75
°c
-65
+150
°c
VIRGIN STATE
A factory shipped virgin device contains all
fusible links open, such that:
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
DC ELECTRICAL CHARACTERISTICS oOc -< TA < +75°C, 4.75V s
-
-
vee < 5.25V
UMITS
SYMBOL
PARAMETER
TEST CONDITION
Min
Vee = Min
Vee = Max
Vee = Min, liN = -12mA
2.0
Typl
Max
UNIT
0.8
V
V
V
Input voltage:!
Vil
V IH
V-c
low
High
Clamp2
-0.8
-1.2
Output voltage
VOL
VOH
low2
High2
Vee = Min
IOl = 10mA
IOH=-2mA
0.45
2.4
I
I
V
V
Input current
Vee = Max
III
low
VIN =0.45V
-100
IIH
High
VIN =5.5V
40
J..IA
J..IA
Output current
Vee = Max
IO(OFF)
Hi-Z state
los
Short circuit
Vour=OV
lee
Vee supply current
Vee = Max
Vour=5.5V
Vour=0.45V
-15
80
-140
-70
rnA
400
rnA
J..IA
Capacitance
CIN
CB
Input
110
Vee=5V
VIN = 2.0V
Vour= 2.0V
NOTES:
1. All typical values are at Vee = 5V, TA = +25°C.
2. All voltage values are with respect to network ground terminal.
November 10, 1989
376
8
15
pF
pF
Product Specification
Signetics Programmable Logic Devices
PLHS502
Programmable Macro Logic
MACRO CELL A.C. SPECIFICATIONS (SNAP Resource Summary Designations in Parenlheses)
Input Buffer
(DIN502, CDIN502, BDIN502
NIN502, CNIN502, BNIN502)
I~~
SYMBOL
Min
Typ
Max
UNIT
~lHl
0.05
0.1
0.15
nslp-term
~ILH
-0.02
-0.05
-0.08
nslp-term
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
IHl
ILH
X
X
I
I
IHl
ILH
V
V
UNIT
NOTES
6
6.5
ns
ns
With 0 p-term load
3.5
4
ns
ns
With 0 p-term load
Min
Typ
Max
4
4.5
5
5.5
2
3.5
3
3.5
Input Pins: 1, 2, 4-i!, 10, 11, 13, 14,17,18,53,56-59,61,62,64-66,68.
Bidirectional Pins: 19, 22-25, 27, 28, 30.
Limit of 16 NAND terms for Input Buffer (X and V) and Internal Foldback NAND (V).
NAND Output Buffer with 3-8t8te Control
(TOU502)
~
T,I-Clrl
In-D~om
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
Min
Typ
Max
IpHl
IplH
Out
Out
In
In
8.5
9
9
10
13.5
14
ns
ns
toE
toD
Out
Out
Tri-Ctrl
Tri-Ctrl
10
8
12
10
18.5
16
ns
ns
UNIT
Bidirectional and Output Pins: 19, 22-25, 27, 28, 30.
Internal Foldback NAND
(FBNAND)
D
x
y
SYMBOL
Min
Typ
Max
UNIT
~IpHl
0.05
0.1
0.15
nsip-term
~lplH
-0.02
-0.05
-0.08
nslp-term
PARAMETER
SYMBOL
To
(Output)
From
(Input)
IpHl
V
X
IplH
V
X
LIMITS
Min
UNIT
NOTES
5.5
ns
Wilh 0 p-term load
8
ns
Wilh 0 p-term load
Typ
Max
4.0
5.0
5.5
6.5
Limit of 16 NAND terms for Input Buffer (X and V) and Intemal Foldback NAND (Y).
November 10,1989
377
Product Specification
Signetics Programmable Logic Devices
PLHS502
Programmable Macro Logic
MACRO CELL A.C. SPECIFICATIONS (Continued) (SNAP Resource Summary Designations in Parentheses)
3-State Output with Programmable Polarity
(TEXOS02)
T~
D>------,
· [ >-=----1 ~6-0
PARAMETER
LIMITS
UNIT
SYMBOL
To
(Output)
From
(Input)
Min
Typ
Max
IpHL
IpLH
Out
Out
In
In
9
10
10
12
19
19
ns
ns
toe
100
Out
Out
Tri-Ctrl
Tri-Ctrl
10
8
12
10
18.5
16
ns
ns
Output Pins: 47, 48, 51, 52.
Output with Programmable Polarity
(EX0502)
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
Min
Typ
Max
IpHL
IpLH
Out
Out
In
In
9
10
10
12
19
19
UNIT
ns
ns
Output Pins: 41, 42, 44, 45.
Output Buffer
(NOU502)
~Out
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
Min
Typ
Max
IpHL
IpLH
Out
Out
In
In
8
9
9
10
14
13.5
Output Pins: 31, 32, 34-36, 38-40.
November 10,1989
378
UNIT
ns
ns
Product Specification
Signetics Programmable Logic Devices
PLHS502
Programmable Macro Logic
o FLIP-FLOP (SNAP Resource Summary Designation = DFF502)
INPUTS
OUTPUTS
~~~
CLR
CK
D
a
0
H
X
X
L
H
L
L
X
ao
00
L
i
i
H
L
H
L
Q
f--
Q
I---
Q
f--
Q
f--
Q
f--
Q
f--
D
CK
I
CLR
twCK1, IpCKl
L
H
L
NOTE:
o, o represent previous stable condition of
a a
a, a.
~~
UMITS
SYMBOL
Min
Typ
Max
_~D CK
UNIT
fCKl
33
37
40
MHz
fCK2
37
40
43.5
MHz
fcK3x
33
37
40
MHz
fCK3Y
37
40
43.5
MHz
tWCKl
15
10
8
ns
Ip CKl
30
27
25
ns
tw CK2, tw CK3Y
10
9
8
ns
Ip CK2, Ip CK3Y
27
25
23
ns
tWCK3X
10
9
8
ns
Ip CK3X
T
CLR
twCK2, IpCK2
~
r:::
..
D
CK
I
CLR
twCK3, 'PCK3
30
27
25
ns
tSETUP U
7
5.5
3
ns
tHOLD U
8.5
4.5
1
ns
SYMBOL
Min
Typ
Max
NOTES
tWCLR High
10
9
8
ns
D.tsETuP
-0.02
-0.05
-0.1
nslFO of CKI ,2,3
UMITS
UMITS
SYMBOL
FROM
(INPUT)
tpLH
CKI
IpHL
CKI
lpLH
CK2
tpHL
CK2
lpLH
CK3X
tpHL
CK3X
IpLH
CK3Y
lpHL
CK3Y
IpLH
lpHL
November 10, 1989
CLR
CLR
TO
(OUTPUT)
a,a
a,a
a,a
a,a
a,a
a,a
a,a
a,a
a,a
a,a
NOTES:
UNIT
1. Setup and Hold times are with reference to rising edge of
CK1, CK2, and CK3.
Min
Typ
Max
16.5
20
25
17.5
20.5
24.5
ns
12
14
16.5
ns
13
15
16
ns
14
16
19.5
ns
15
16
19
ns
SYMBOL
Min
Typ
Max
NOTES
12
14
16.5
ns
D.tpHLK
0.05
0.1
0.15
nslFO of CKI ,2,3
13
15
16
ns
D.tpLHK
0.05
0.1
0.15
11
12
15
15
20
19.5
ns
ns
ns
379
2. Limit of 16 Logic terms load on
a and a.
UMITS
D.tpLHO
D.tpHLO
-0.02
0.05
-0.5
0.1
-0.08
0.15
nslFO of CK1,2,3
nslp-term load on
a,a
nslp-term load on
a,a
Product Specification
Signetics Programmable Logic Devices
PLHS502
Programmable Macro Logic
S-R FLIP-FLOP
(SNAP Resource Summary Designation
INPUTS
OUTPUTS
g
11
0
Q
CLR
CK
H
X
X
X
L
H
L
L
X
X
00
00
L
H
t
t
t
t
L
L
L
L
= RSF502)
H
L
L
H
H
L
H
H
00
00
L
L
Not allowed
---E~
33
fCK2
fCK3X
CK
~
0-
Typ
Max
UNfT
37
40
MHz
37
40
43.5
MHz
33
37
40
MHz
fCK3Y
37
40
43.5
MHz
twcK1
15
10
8
ns
IpCK1
30
27
25
ns
ns
tWCK2
10
9
8
Ip CK2
27
25
23
ns
tWCK3X
10
9
8
ns
Ip CK3X
30
27
25
ns
tWCK3Y
10
9
8
ns
Ip CK3Y
ns
Q r--
S
---E~
LIMITS
fCK1
~
R
Q-
CILA
00, 00 represent previous stable condition of 0, O.
Min
S
'WCK1, 'PcK1
NOTE:
SYMBOL
~
CK
~
or--
R
cllR
'WCK2, tpCK2
I
.~~s
Q
~:=. r;=',~
I--
01-cllR
'WCK3, tpCK3
27
25
23
tSETUP S, R
7
5.5
3
ns
tHoLDS, R
8.5
4.5
1
ns
SYMBOL
Min
Typ
Max
NOTES
ns
~tsETUP
-{l.02
-{l.05
-{l.1
ns/FO of CKI ,2,3
10
tWCLR High
9
8
LIMITS
LIMITS
NOTES:
SYMBOL
FROM
(IN PUn
TO
(OUTPUn
Min
Typ
Max
IpLH
CKI
0,0
16.5
20
25
ns
IpHL
CKI
0,0
17.5
20.5
24.5
ns
IpLH
CK2
0,0
12
14
16.5
ns
IpHL
CK2
0,0
13
15
16
ns
tpLH
CK3X
0,0
14
16
19.5
ns
IpHL
CK3X
15
17
19
ns
SYMBOL
tpLH
CK3Y
IpHL
CK3Y
a,o
a,o
a,O
IpLH
CLR
a
tpHL
November 10, 1989
CLR
a
UNIT
1. Setup and Hold times are with reference to rising edge of
CK1, CK2, and CK3.
2. Limit of 16 Logic terms load on
a and O.
LIMITS
Min
Typ
Max
NOTES
0.1
0.15
ns/FO of CKI ,2,3
12
14
16.5
ns
~IpHLK
0.05
13
15
16
ns
~tpLHK
0.05
0.1
0.15
11
15
20
ns
~tpLHQ
-{l.02
-{l.5
-{l.08
12
15
19.5
ns
380
~IpHLQ
0.05
0.1
0.15
nsiFO of CKI ,2,3
ns/p-term load on
0,0
ns/p-term load on
0,0
Signetics Programmable Logic Devices
Product Specification
PLHS502
Programmable Macro Logic
I'
SNAP RESOURCE SUMMARY DESIGNATIONS
8
:sa. . . . +H:-+-~
DUb~;l~t···;·····;n···~~~i~~~jg~~F=~
.••.. •••.•.•••.••• :>
November 10, 1989
381
Product Specification
Signetics Programmable Logic Devices
PLHS502
Programmable Macro Logic
PLHS502 GATE AND SPEED ESTIMATE TABLE
FUNCTION
INTERNAL NAND
EQUVALENT
TYPICALtPD
1
1
1
1
6.5ns
6.5ns
6.5ns
6.5ns
COMMENTS
fMAl(
Gates
NANDs
ANDs
NORs
ORs
For 1 to 32--pin input variables
Additional internal inputs can be used as needed
Additional internal inputs can be used as needed
Additional internal inputs can be used as needed
Macro Flip-Flops
N/A
D-Type Flip-Flop
SR-Type Flip-Flop
N/A
40MHz
40MHz
Total budget = 8
Total budget = 8
35MHz
35MHz
35MHz
With
With
With
With
With
Gate Implemented Flip-Flops
D-Type Flip-Flop
T-Type Flip-Flop
J-K-Type Flip-Flop
Transparent-D Latch
8-R Latch
6
6
10
4
2
N/A
N/A
asynchronous 8-R
asynchronous 8-R
asynchronous 8-R
asynchronous 8-R
asynchronous 8-R
Decoders
3-to-8
4-10-16
5-t0-32
8
16
32
11.5ns
11.5ns
11.5ns
Inverted inputs available
Inverted inputs available
Inverted inputs available (24 chip outputs only)
15
32
41
11.5ns
11.5ns
11.5ns
Inverted inputs, 2 logic levels
Inverted inputs, 2 logic levels
Inverted inputs, 2 logic levels
5
9
17
28
11.5ns
11.5ns
11.5ns
11.5ns
Inverted inputs available
Inverted inputs available
Inverted inputs available
Can address only 27 external inputs - more if internal
only. This disallows clock inputs to flip-flop.
Encoders
8-t0-3
16-t0-4
32-1c>-5
Multiplexers
4-10-1
8-10-1
16-to-l
27-to-l
.
.
PLHS502 Rough Resource Budget = 64 NANDs, 8 D, 8 SR, 24 Inputs, 16 outputs, 8 bldlrectlonals .
APPLICATIONS
PARALLEL DATA OUT
t t t t t t t t
1111:11)'
I
SERIAL DATA IN
RECEIVE CLOCK
TRANSMIT CLOCK
3-81T COUNTER
:
rl I I I I I I ,
I lllllllf
LOAD/sIIFT
J
•
PARALLEL DATA IN
40MHz Synchronous RecelverlTransmltter
November 10,1989
382
SERIAL DATA OUT
Product Specification
Signetics Programmable Logic Dovices
PLHS502
Programmable Macro Logic
APPLICATIONS (Continued)
CLOCK A
--+---t>
HTB
CLOCK B
--+---t>
HTC
CLOCK C
--+---1>
HTD
CLOCK D
--+-4>
DATA 4
DATA 3
DATA 2
DATA 1
4 X 4 Content Addressable Memory (Address valid to Hit Time
November 10, 1989
383
= 2Ons)
Signefics
PLHS601
Document No.
ECN No.
Date of Issue November 1989
Status
Preliminary Specification
Programmable Macro Logic
PMLTM
Programmable Logic Devices
FEATURES
DESCRIPTION
APPLICATIONS
• Programmable Macro Logic
The Signetics Programmable Macro Logic (PML) family of PLDs provides the capability to create fast and cost effective
solutions for general purpose logic integration, microprocessor bus interface and
control applications. PML incorporates
folded NAND gates as the core of its architecture. With this architecture, multiple
levels of logic can be realized within the
device without wasting valuable 1/0 pins.
Furthermore, full connectivity is established among the different macros within
the device, which in turn eliminates the
route and place restrictions associated
with high density programmable gate
arrays.
• General purpose logic integration
and microprocessor support logic
• TTL compatible
• SNAP development system
- Supports third-party schematic
entry formats
- Macro library
- Versatile nellist format for design
portability
- Logic, timing, and fault
simulation
• Delay per Internal NAND function
4.5ns (typ)
• Security fuse for copy protection
STRUCTURE
• 86 fold back terms
- 7810ldback NAND terms
- 8 fold back Exclusive-OR terms
• 64 additional logic terms
• 28 dedicated inputs
• 12 bidirectional pins with ActiveHigh output and independent
3-State control
=
The PLHS601 is a high-density bipolar
PML device. The high number of 1/0 pins
and the folded NAND architecture makes
this device ideal in a wide range of bus interface and control logic applications. The
PLHS601 is a powerful solution to eliminate wait states and create cost-effective
microprocessor support circuitry.
• PAL ® and glue logic replacement
• High speed and wide address
decoders
• Wide multiplexers and decoders
• Bus arbitration functions
ARCHITECTURE
The core of the PLHS601 is a programmable fuse array of 78 folded NAND gates
and 8 folded Exclusive-OR gates. The
output of each gate folds back upon itse~
and all other gates. In this manner, full
connectivity of all logic functions is
achieved. Any logic functions can be implemented within the core of the device
without wasting valuable 1/0 pins. Furthermore, a speed advantage is achieved by
creating multiple levels of logic within the
folded core without incurring any delays
from the 1/0 buffers.
.12 dedicated Active-High outputs
with Independent a-state control
PML is a trademark of Philips Components-Signetics.
®PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
PHILIPS
384
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Macro Logic
PLHS601
i
I
PIN CONFIGURATION
A Package (68-Pin PLCC)
N
~ ~ ~ ~ ~ ~
•
M
N
~
_
~
2
GND10
121
GND2
16
15
1
14
13
12
GND3
1
VeC4
11
10
VCC2
GN09
eo
010
B1
09
B.
B3
B4
GND4
06
~ ~ ~ ~ ~ ~ ~ ~
~
~
m8
9> 0
DESIGN DEVELOPMENT TOOLS
The SNAP Software Development System provides the necessary tools for designing with
PML. SNAP provides the following:
• Schematic entry netlist generation from thirdparty schematic design packages such as
DrCAD/SDT IIITM and FutureNet™
• Macro library for standard PLHS601 functions and user defined functions
• Syntax and design entry checking
• Simulator includes logic simulation, fault simulation, automatic test vector generation,
and timing simulation.
SNAP operates on an IBM® PC/XT, PC/AT,
PS/2, or any compatible system with DDS 2.1
or higher. The minimum system configuration
for SNAP is 640K bytes of RAM and a hard disk.
• Boolean equation entry
• State equation entry
SNAP provides primitive PML function libraries
for third-party schematic design packages.
FutureNet is a trademark of FutureNet Corporation.
DrCAD/SOT is a trademark of Dr€AD, Inc.
IBM is a registered trademark of International Business Machines Corporation.
November 1989
385
Custom macro function libraries can be defined
in schematic or equation form.
After the completion of a design, the software
compiles the design for syntax and completeness. Complete simulation can be carried out
using the different simulation tools available.
The programming data is generated in JEDEC
format. Using the Device Programmer Interface (DPI) module of SNAP, the JEDEC fusemap is sent from the host computer to the
device programmer.
Preliminary Specification
Signetics Programmable Logic Devices
PlHS601
Programmable Macro logic
FUNCTIONAL DIAGRAM
ro-
INPUT
BUFFERS
78
8
NAND
TERMS
EX-OO
TERMS
OUTPUT
TERMS
D- H'>
. .
D- H'>
INPUT
BUFFERS
I......-
30
mA
+100
mA
0
+75
°c
--65
+150
°c
--{30
NOTE:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
THERMAL RATINGS
VIRGIN STATE
TEMPERATURE
Maximum junction
150°C
Maximum ambient
75°C
Allowable thermal rise
ambient to junction
November 1989
A factory shipped virgin device contains all fusible links open, such that:
1. All product terms are enabled.
2. All bidirectional (8) pins are outputs.
3. All outputs are enabled.
75°C
4. All outputs are Active-HIGH.
388
Preliminary Specification
Signetics Programmable Logic Devices
PLHS601
Programmable Macro Logic
DC ELECTRICAL CHARACTERISTICS oOC -< TA -< +75°C, 4.75V -< Vee -< 5.25V
,
SYMBOL
PARAMETER
TEST CONDITION
Min
Vee = Min
Vee = Max
Vee = Min, liN =-12mA
2.0
Typl
,
I
LIMITS
Max
UNIT
0.8
V
V
V
Input voltage'
V ,L
V,H
Vc
Low
High
Clamp 2,3
-0.8
-1.2
Output voltage
Vee = Min
10l = lOrnA
10H =-2mA
Low 2
High2
Val
V OH
0.45
V
V
JlA
JlA
2.4
Input current
Vee = Max
I,l
Low
Y,N = 0.45V
-100
I'H
High
Y,N = 5.5V
40
Output current
Vee = Max
10(oFF)
Hi-Z stateS
los
Short circuit3 , 4
VOUT = OV
Icc
Vee supply current5
Vee = Max
VOUT = 5.5V
VOUT = 0.45V
-15
80
-140
JlA
-70
rnA
340
rnA
Capacitance
Vee = 5V
Y,N = 2.0V
VOUT = 2.0V
Input
I/O
C,N
Cs
8
pF
pF
15
NOTES:
1. AI! typical values are at Vee = 5V, TA = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Duration of short circuit should not exceed 1 second.
5. Icc is measured with all dedicated inputs at OV and bidirectional and output pins open.
S. Leakage values are a combination of input and output leakages.
TEST LOAD CIRCUITS
VOLTAGE WAVEFORMS
~ vcc
T ~"."
". ...'
.sv
0,-- 10
I
I
o-L-
<>---r---
o--l----
AND JIG
I
I
I
By
'.7
BW
BZ
Ox
BX
GND
-,,~
---L-
-
I
R.
':"
CL
-~
ov
-J
LIR IFJ ~~
2.Sna
2.5na
~:~
':"
2-_
~
2-_
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of Inputs and outputs, unless otherwise specified.
Input Pulses
November 1989
389
Preliminary Specification
Signetics Programmable Logic Devices
PLHS601
Programmable Macro Logic
SNAP RESOURCE SUMMARY DESIGNATIONS
_
7.
INPUT
NAND
BUFFERS
ITERIIS
EX-OR
•
OUTPUT
TERIIS
TERIIS
~[}-;~>~~--~-+~-+~+-+-4----4--~
"b ~ .+-~
+--f--I--+-I--I-+--+---+-+-
INPUT
BUFFERS
~
~
'2
78
OUTPUT
BUFFERS
November 1989
390
Preliminary Specification
Signetics Programmable Logic Devices
PLHS601
Programmable Macro Logic
MACRO CELL SPECIFICATIONS TA = o°c to +75°C, 4.75V S Vee s 5.25V, CL = 3OpF,
R2 = 10000, R,
(SNAP Resource Summari Designations in Parentheses)
= 4700
Input Buffer
(DIN601, NIN601)
LIMITS
SYMBOL
Min
Typ
Max
UNIT
!;IHL
0.05
0.1
0.15
nslp-term
!;ILH
--{).02
--{).05
--{).08
nslp-term
PARAMETER
LIMITS
UNIT
NOTES
6
6.5
ns
ns
With 0 p-terms load
3.5
4
ns
ns
With 0 p-terms load
SYMBOL
To
(Output)
From
(Input)
Min
Typ
Max
IpHL
IpLH
X
X
I
I
4
4.5
5
5.5
IpHL
IpLH
y
2
3.5
3
3.5
Y
Input Pins: 1 -2,4 -8,10-11,13 -15,17 -19, 52 -53, 55 -59,61 -62,64- 66, 68.
Bidirectional Pins: 21 - 25,27 - 28, 30 - 32,34 - 35.
Maximum internal fan-out: 16 p-terms on X or Y.
Internal Foldback NAND
(FBNAND)
LIMITS
SYMBOL
Min
Typ
Max
UNIT
!;tPHL
0.05
0.07
0.1
nslp-Ienm
!;lpLH
--{).02
--{).05
--{).08
ns/p-Ienm
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
Min
Typ
Max
IpHL
IpLH
Oul
Any
2.0
3.7
2.7
4.5
4
6
Maximum internal loading of 16 terms.
November 1989
391
UNIT
NOTES
ns
ns
With 0 p-tenms load
Signetics Programmable Logic Devices
Preliminary Specification
Programmable Macro Logic
PLHS601
MACRO CELL SPECIFICATIONS (Continued) TA = oOc to +75°C, 4.75V sVccs5.25V, cL = 30pF, R2 = 1()()()Q, R, =4700
(SNAP Resource Summary Designations in Parentheses)
Non-lnvertlng Output Buffer with
(NOU601)
PARAMETER
SYMBOL
1'0
~tate
Control
LIMITS
(Output)
From
(Input)
Min
Typ
Max
tpHL
tpLH
Output
Output
In
In
8
9
9
10
11.5
13.5
ns
ns
toe
IoD
Out
Out
Tri-Ctrl
Tri-Ctrl
10
8
11.5
9.5
13.5
11.5
ns
ns
UNIT
Bidirectional and Output Pins: 19, 21, 22, 23, 15 -18.
Internal Ex-OR Feedback Terms
(EX0601)
:=8:=----
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
68-pin Plastic Leaded Chip Carrier
High-Speed
PML2552AA
68-pin Ceramic Leaded Chip Carrierwith quartz window
High-Speed
PML2552ALA
68-pin Plastic Leaded Chip Carrier
Standard
PML2552A
68-pin Ceramic Leaded Chip Carrier with quartz window
Standard
PML2552LA
November 1989
396
:! c"
ril g
Preliminary Specification
Signetics Programmable Logic Devices
PML2552
Programmable Macro Logic
FUNCTIONAL BLOCK DIAGRAM
16
INPUT
DFLIP-FLOPS
&
13 DEDICATED
INPUTS
A
~
I
N
T
E
R
C
FOLDED
NAND
ARRAY
0
N
N
E
C
T
B
10
JK FLIP-FLOPS
WITH
COMMON
CLK
c
'-------'
10
JK FLIP-FLOPS
WITH
DISTINCT
CLKS
D
Figure 1
November 1989
397
Preliminary Specification
Signetics Programmable Logic Devices
PML2552
Programmable Macro Logic
LOGIC DIAGRAM
F
I
~
8
A
r
B~
8
IIOA
o (8)a
1
CKA
8
IIDB
-C
~
I/CKB/eKe
1
'>
9
9
2
3
3
>
8
"
8
~~
8
I
lICK
1
3
lj ~"
8
10
10
J
K
CL (10)
CK2
Q
a
20
~
~ c&c~'
K
CKl
Q
J
(10) PR
a
o
0 BFB(G-7)
(8)
(8)
:.-0
~
-=
,.
E
Oii
0-=
BFB(8-15)
)
20
1/00-1/07
(SCAN OUT)
s"
10
8
B
1108-11015
(SCAN OUT)
Q
BFA(8-15 _
1
8
I
10
KEl
(SCAN CLOCK)
10
1
KE2
8
~~
8
'~
4
I
November 1989
398
-~
SCi
00
I
Signetics Programmable Logic Devices
Preliminary Specification
PML2552
Programmable Macro Logic
I..•
DESCRIPTION
ARCHITECTURE
Thp. Signetics PML family of PLDs provides
"instant gate array" capabilities for general
purpose logic integration applications. The
PML2552 is the first high density CMOS-PML
product. Fabricated with the Signetics highperformance EPROM process, it is an ideal
way to reduce N RE costs, inventory problems
and quality concerns. The PML2552 incorpo~
rates the PML folded NAND array architecture
which provides 100% connectivity to eliminate
routing restrictions. What distinguishes the
PML2552 from the "classic" PLD architectures
is its flexibility and the potent flip-flop building
blocks. The device utilizes a folded NAND
architecture, which enables the designer to im~
plement multiple levels of logic on a single chip.
The PML2552 eliminates the NRE costs, risks,
and hard to use design tools associated with
semicustom and full custom approaches. It
allows the system designer to manage reliable
functionality, in less time and space plus a fast~
er time to market. The PML2552 is ideal in to~
days instrumentation, industrial control, EISA,
NuBus™, bus interface and dense state
machine applications in conjunction with the
state-of-the-art CMOS processors. It is capa~
ble of replacing large amounts of TIL, SSI and
MSI logic and literally allows the designer to
build a system on the chip.
The core of the PML2552 is a programmable
NAND array of 96 NAND gates and 20 buried
JKFFs. The output of each NAND gate folds
back upon itself and all other NAND gates and
flip-flops. The '0' and '0" output of each flipflop also folds back in the same manner. Thus,
total connectivity of all logic functions is
achieved in the PML2552. Any logic function
can be created within the core without wasting
valuable I/0pins. Furthermore, aspeedadvan~
tage is acquired by implementing multi-level
logic within a fast internal core without incurring
any delays from the 1/0 buffers. Figure 1 shows
the functional block diagram of the PML2552.
The SNAP development software gives easy
access to the density and flexibility of the
PML2552 through a variety of design entry for~
mats, including schematic, logic equations, and
state equations in
any combination.
Macro Cells
There are 16 bypassable DFFs on the input to
the NAND array. These flip-flops are splitin two
banks of 8 (Bank A and Bank B). Each bank of
flip-flops has a common clock. In the unpro~
grammed state of the device the flip-flops are
active. In order to bypass any DFF, its respec~
tive bypass fuse (BFAx) must be programmed.
The 161/0 pins (100 -10'5) and their respective
D flip-flop macros can be used in anyone olthe
following configurations:
1. As combinatorial input(s).
Each of the 16 3--State outputs can be indi~
vidually disabled by the associated NAND
term and the pin is used as an inverting or
non-inverting input.
2. As registered DFF outputs.
These DFFs are split into two banks of 8,
and each bank is clocked separately. The
bypass fuse BFBx (see PML2552 Logic
Diagram) is used to bypass anyone of these
D FFs. The flip-flops are all active in an un~
programmed device.
NuBu8 Is a trademaric. d Texas Instruments, Inc.
November 1989
399
3. As combinatorial outputs.
By programming the bypass (BFBx) fuse of
anyone of ihe DFFs. the flip-flop(s) is by~
passed. The 1/0 pin can then be used as a
combinatorial output.
4. As Internal fold back DFFs or foldback
NAND gates.
When the 1/0 pin is used as an input, the
output macro can be used as an internal
DFF or a foldback NAN D term. If the bypass
fuse is programmed, the macro will actas a
foldback NAND term. Otherwise itwill act as
an internal OFF.
The 8 bidirectional pins (80-B7) can be used as
either combinatorial inputs or outputs with pro~
grammable polarity. The outputs are inverting
in the unprogrammed state. In order to make
the outputs non-inverting, fuse BFC x (See
Logic Diagram) must be programmed.
The NAND signal labeled '00' (OutputDisable)
shown on the PML2552 logic diagram is used
for the Power Down mode operation. This sig~
nal disables the outputs when the device enters
the Power Down mode and SCI is high.
Clock Array
The 20 buried JKFFs can be clocked through
the 'Clock Array'. The Clock Array consists of
11 NAND terms. Ten of these terms are con~
nected to the clock inputs of the Bank A flipflops that can be clocked individually. One
NAND gate is connected to Bank B flip-flops
that have a common clock. There are 18 inputs
to the clock array. Four come directly from the
input pins (with programmable polarity), 4
inputs are from 4 NAND gates connected
directly to the folded NAND array. 10 inputs are
from the 0 outputs of the JKFFs with clear.
I
Preliminary Specification
Signetics Programmable Logic Devices
Programmable Macro Logic
SCAN TEST FEATURE
With the rise in the ratio of devices on a chip to
the number of I/O pins, Design For Testability
is becoming an essential factor in logic design
methodology. The PML2552 incorporates a
variable length scan test feature which permits
access to the internal flip-flop nodes without requiring a separate external 110 pin for each
node accessed. Figure 2 (Scan Mode Operation) shows how a scan chain is implemented
through the 20 buried JKFFs and 16 output
DFFs. Two dedicated pins, SCI (Scan In) and
SCM (Scan Mode), are used to operate the
scan test. The SCM pin is used to putthe circuit
in scan mode. When this pin is brought to a logic
"1", the circuit enters the scan mode. In this
PML2552
mode it is possible to shift an arbitrary test pattern into the flip-flops. The SCI pin is used to input the pattern. The inverted outputs of
flip-flops DO - D 15 are observable on pins 1/00
-1/015.
The following are features and characteristics
of the device when in Scan Mode:
1. CKEI is the common scan-dock for all the
flip-flops when in scan mode. CKE 1 overrides all clock resources of normal operational mode.
2. ThePreset(PR)and Clear(CL)functionsof
the flip-flops are disabled.
3. Scan overrides the bypass fuse of the flipflops. This means that all the bypassable
DFF s remain intact during scan operation
even though they may have been bypassed
during normal operation.
4. To observe the SCAN data, the output buffers must be enabled by the Output Enable
(tri--<:trl) terms.
5. The outputs of the flip-flops are complemented on pins 1/00 - 1/015.
6. All external inputs to flip-flops in the scan
chain are disabled when the device enters
the scan mode.
7. Blowing the security fuse does not disable
the Scan Test feature.
SCAN MODE OPERATION
SCOUT
11015
1/00 1/014
1/01
1/013
1/02 1/012
1/03
1/011
(COMMON CLOCK (CKE1) FOR ALL FLIP-FLOPS WHEN IN SCAN MODE)
Figure 2
November 1989
400
1/04
1/010
1/05
1/09
1/06
1/00
1107
Signetics Programmable Logic Devices
Preliminary Specification
Programmable Macro Logic
Scan Test Strategy
The scan test pattern is design dependent and
the user must make considerations for Design
For Testability (DFT) during the initial stages of
the design. A typical test sequence is to preload (i.e., enter a state); revertto normal operation (i.e., activate the next state transition); go
back to scan mode to check the result. Note that
the scan test feature available in the PML2552
is a variable length scan chain. The DATA
entered at SCI (JKCL9) can be accessed anywhere between 21 clock cycles (at 1100) to 36
clock cycles (at 11015). For the strategy
discussed here, DATA is read out after 36
clocks at 11015 (i.e., D15). The following operation sequence suggests a possible scan test
method.
PML2552
5. To read result of the state transition, re-€nter scan and apply the scan clock (CKE 1).
The result of the state transition in JKCL9
will be available at SCOUT (11015) after 36
clocks. The results can be stored in a user
defined test memory buffer in inverted logic
representation.
6. As the results are being read and stored,
new 'Test Data' can be entered via SCI.
7. Repeat for all test patterns of interest.
8. Figure 3 (FLOW_CHART) depicts a flow
chart version of the test sequence.
A conservative test policy demands proof that
the test facility is working. Thus, to prove Scan
Chain holds and maintains correct data:
a. Fill chain with several patterns (for example, all ones and all zeros).
b. Retrieve same patterns.
The user is responsible for managing an
external test memory buffer for applied vectors
and results, as part of the test equipment.
1. Parallel readout of 1/00 -1/015 is possible,
but assume only 11015 is used for this
strategy.
2. The first DATA entered at SCI (or JKCL9)
will be the content of D 15 after 36 clocks.
This DATA will be inverted at the output pin
1/015 (i.e., SCOUT). The last DATA entering the scan chain will be the content of
JKCL9. Thus, the scan chain resembles a
first-in-first--r- IA
I
I
o-L~
o--l--
rr J:D~AND JIG
R,
I
I
II
By
B
I
BW
BZ
Ox
BX
GND
W--
r--
R2
CAPACITANCE
I
CL
=-=
-=!:NOTE:
Test load R1 = 75012, R2 = 44212, C L = 30pF (C L = SpF for Output Disable)
OoC s TA S +7SoC, 4.7SV s Vee S 5.25V
November 1989
404
MEASUREMENTS:
All circuit delays are measured at the ... 1.5V level of
inputs and outputs. unless otherwise specified.
Input Pulses
Preliminary Specification
Signetics Programmable Logic Devices
PML2552
Programmable Macro Logic
MACRO CELL AC SPECIFICATIONS Min: ooe, 5.25V; Typ: 27°e, 5.0V; Max: 75°e, 4.75V
(SNAP Resource Summary Designations in Parentheses)
Input Buffer
(DIN552, NIN552, BDIN55, BNIN552
CDIN552, CNIN552, CKDIN552, CKNIN552)
I~
PARAMETER
SYMBOL
UMITS
STANDARD
UNIT
To
From
(Output)
(Input)
Min
Typ
Max
Min
Typ
Max
tpHL
tpLH
X
X
I
I
3
3
6
6
10
10
3.5
3.5
6
6
10
10
ns
ns
tpHL
tpLH
y
Y
I
I
3
3
6
6
10
10
3.5
3.5
6
6
10
10
ns
ns
HIGH-SPEED
Input Pins: 8-14,16,17,20,22-24.
Bidirectional Pins: 1-3,5-7,46-48, 5C"'_ _ _
~
___
"~_~~_,~
tSCMS
Scan Mode (SCM) Setup time
tSCMH
Scan Mode (SCM) Hold time
tIS
Data Input (SCI) Setup time
tlH
Data Input (SCI) Hold time
!eKO
Clock to Output (110) delay
!eKH
Clock High
Max
UNIT
Standard
Min
Max
___
-
_.
15
15
ns
25
30
ns
5
5
ns
5
5
,~~~----.-.-=--=-.-~-
-
ns
~"~~~--.~-
30
..-
40
ns
-----~---~~~,~"~"----~
10
15
ns
10
15
ns
40
50
ns
30
35
~"~.--~
!eKL
Clock Low
-,,------_.
-~-=~-~,---.--.~~-~-,
Power down, power up2
...
I,
Inpul (i, bypassed IIDA, IIDB, 110, 8) selup time before power down
t2
Inpul hold time
t3
Power Up recovery time
t..
Output hold time
ts
Input selup time before Power Up
toE
SCI to Output Enable time 3
---.-----~~~---
ns
.~"
60
._.
-----.
70
ns
0
0
ns
20
25
ns
40
50
ns
40
50
ns
70
80
ns
10
15
ns
40
50
ns
--~=~-
too
SCI to Output Disable time3
Ie
Power Down setup time
t7
Power Up to Output valid
..-
..
10
..
15
ns
Power-on reset
tpPR,
Power-<:>n reset output register (0 = 0) to output (110) delay
tpPR2
Power-<:>n reset input register (0 = 0), buried JK Flip-Flop (Q
to output (8, bypassed 110) delay
= 0)
NOTE:
1. SCM recovery time is 50ns after SCM operation. SOns after SCM operation, normal operations can be resumed.
2. Timings are measured without foldbacks.
3. Transistion is measured at steady state High level (--5oomV) or steady state Low level (+5OOmV) on the output from 1.5V level on the input
with specified test load (R,
November 1989
= 750n, R2 = 442n, CL = 5pF). This parameter is sampled and not 100% tested.
410
Preliminary Specification
Signetics Programmable Logic Devices
PML2552
Programmable Macro Logic
TIMING DIAGRAMS
.
~rI1-5-V---------------------------------------~--~'1.55VV+3V
SCM
-I--
'SCMS
lSCMH
---I ~
------"'
OV
+3V
SCI
oV
eKE1
OV
--------+-, ,---------------+--,
,-----------VOH
110
'------------VOL
Scan Mode Operation
r----------
I, BYPASSED IIDA, IIDB, 110, B
+3V
1.5V
"----------- OV
+3V
PO
B,IIO
OV
Power Down, Power Up
Input (old) Ready Before Power Up
November 1989
411
Preliminary Specification
Signetics Programmable Logic Devices
PML2552
Programmable Macro Logic
TIMING DIAGRAMS (Continued)
,.~--~.,~,
=:x ""
rJ.:
PO
+3V
'~I.~_.5_V
_ _ _ __
OV
~""~~~
----i---'~ I
+3V
~-~-tP~
OV
VOH
B,IIO
1.5
I
t6
SCI
r
1.5V
. I IMPEDANCE I
r
tolt"j
VOL
tOEi
+3V
~1.5V
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
_ _ _ _ _ _- J
OV
Power Down, Power Up
Input (new) Ready After Power Up
I. BYPASSED IIDA, IIDB, 1/0, B
,..-_ _ _-+-_
_..r-
OV
13
+3V
PO
OV
VOH
B,IIO
VOL
SCI
OV
Power Down, Power Up
Input (new) Ready Before Power Up
____________________ +5V
~4.5V
3.0V
Vce
110
~
+-tpPRI~--~
"~-'-.5-V------------
-
tpPR2
B,IIO
=1
~1'-'.-5V-----------
Power-On Reset
November 1989
412
OV
VOH
VOL
VOH
Preliminary Specification
Signetics Programmable Logic Devices
PML2552
Programmable Macro Logic
SNAP RESOURCE SUMMARY DESIGNATIONS
~.. ····tiW~lij;z
00
~XO~2
cb __
I BF:
X
---I--t--t------I--+--I---+-+--t--+--+-+-
Q 1---11
IIDA>--"7'---I D
'liOl¥~
CKA.>----'>'--t> (8)
O~_I_-_I_-~-~----_I_-+--+-+-~~_+-_+-_4--~
I ............. .
BFAX
-=
-t--t--t__-t__----t-_+-~t___+-_I_-_t_-+--.Ji!~m~~
-+--+---I---I-----+--+--+--t---t--t--+----':::.~~~~.::
IIDB
1/08-1/015
1/00-1/07
lICKs/eKe
·~$$if---_t_-_t_----~-t__-_t_~~~-_I_-+-~-_+--
9~~ff----t---t-----~-f----/-~f--~--I--+-~--+--
..... ,.1................
··.~m"··.-I·f----/---/-----If---It---t--t-~--+--_I_-+--+-
·iiiiim+--j--+----II---I---l-+-+---l--+--+--+-
....:::>(::::::::::::::.,
IICKII)--/-*-,7L---"l
~Mtl--+--+-----f---f---+-~~-+---I--+-~--+--
• • p~~•
f~m··'0
1010
8
8
~
K
J
o
Q
CL (10)
204i(CUQ
.................................
CK2
CKE2
10
November 1989
413
Signetics
Section 7
Military Selection Guide
Programmable logic Devices
INDEX
Military Selection Guide ...................... , ..................... 417
Signetics
Military Selection Guide
I'
Programmable Logic Devices
Part Number
Device
Description
Package
Description
PLHS 18P8/BRA
PLHS 18P8/BSA
PLHS501 IBXA
PLS159A
PLUS16L8/BRA
PAL
PAL
GATE ARRAY
PLS
PAL
PLUS 16LB/BSA
PLUS 16L8/B2A
PLUS 16R8/BRA
PLUS16R8/BSA
PLUSI6R8/B2A
Standard
MIL-Drawlng
MIL-Drawlng
J8**
JS**
20DIP3
20FLAT
64DIP9
20DIP3
20DIP3
NA
NA
NA
NA
NA
NA
NA
NA
5962~72801SA
PAL
PAL
PAL
PAL
PAL
20FLAT
20LLCC
20DIP3
20FLAT
20LLCC
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
5962~515509SA
PLUS20LB/BLA
PLUS20LBIIBKA
PLUS20L8/B3A
PLUS20R8/BLA
PLUS20R8JBKA
PAL
PAL
PAL
PAL
PAL
24DIP3
24FLAT
28LLCC
24DIP3
24FLAT
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
5962~767105LA
PLUS20R8/B3A
PLUS405/BXA
PLUS405JBYA
PLUS405/B3A
PLS167/BLA
PAL
PLS
PLS
PLS
PLS
28LLCC
28DIP6
28FLAT
28LLCC
24DIP3
NA
NA
NA
NA
NA
NA
NA
NA
5962~7671 063A
PLS168/BLA
PLS173/BLA
PLS179/BLA
PLHS473
82S100/BXA
PLS
PLA
PLS
PLA
PLA
24DIP3
24DIP3
24DIP3
24DIP3
28DIP6
50202
NA
NA
NA
NA
A
NA
NA
NA
82S100/BYA
82S100/B3A
82S101/BXA
82S101/BYA
82S101/B3A
PLA
PLA
PLA
PLA
PLA
28FLAT
28LLCC
28DIP6
28FLAT
28LLCC
50202
50202
50201
50201
50201
NA
NA
A
NA
NA
NA
NA
NA
NA
NA
82S105/BXA
82S105JBYA
82S105/B3A
82S153A1BRA
82S153A1BSA
PLS
PLS
PLS
PLA
PLA
28DIP6
28FLAT
28LLCC
20DIP3
20FLAT
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
M385101
5962~72801RA
417
PLANNED
PLANNED
5962~515509RA
5962~5155092A
5962~51551 ORA
5962~515510SA
5962~5155102A
5962~767105KA
5962~7671053A
5962~7671 06LA
5962~7671 06KA
PLANNED
PLANNED
PLANNED
PLANNED
PLANNED
5962~850402LA
82S153A/B2A
PLA
20LLCC
NA
NA
• Not available as a Class B standard product. See M3851 0 and/or Military Drawing columns for availability
•• A; available, NA; not available, IP ; in prooess, call for availability.
January 1990
Status··
5962~850701LA
PLANNED
5962~670901XA
A
A
NA
A
A
A
A
A
A
A
A
A
A
A
A
NA
NA
NA
NA
NA
A
A
NA
5962~768201SA
A
A
A
A
A
5962~7682012A
A
5962~670901 YA
5962~6709013A
5962~768201
RA
Signetics
Section 8
Development Software
I
I
I·
I
Programmable Logic Devices
INDEX
AMAZE - Automatic Map and Zap Equations Design Software .............
SNAP - Synthesis Netlist Analysis and Program Software .................
SNAP Data Sheet ................................................
Device Programmer Reference Guide .................................
421
425
427
429
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Signefics
AMAZE
Programmable Logic
Development Software
Programmable Logic Devices
SOFTWARE SUPPORT FOR
USER PROGRAMMABLE LOGIC
Computer Aided Design (CAD) support is
becoming necessary to address the timeconsuming details required by the more
complex programmable logic devices
available today. The design effort can include the manipulation of Boolean equation, truth tables, state diagrams,
flowcharts etc., to create the binary fuse
map required to program such devices.
For many years, design engineers have
used programmable read-only memories
(PROMs) to replace conventional logic.
The architecture of the PROM can be described as a programmable logic device
containing a fixed AND array followed by
a programmable OR array. The fixed
structure of the PROM requires a full
assignment of output words to be programmed for every input combination.
Therefore, little use can be made of
programmable logic software programs
for logic minimization or other compiling
efforts when using PROMs.
Signetics Programmable Logic Devices
are the most advanced approach to solving the inherent limitations of PROMs.
Their architecture consists of a programmable AND array, followed by a programmable OR array - with the addition
of a programmable invert function for
flexible output control.
November 1989
A Signetics PLD device can implement
any set of Boolean expressions, provided
that they are first put into the standard sum
oftheproducts form. The 10gicaiANDs are
implemented at the first gate level of the
programmable logic device and the logical
ORs are implemented by the second gate
level within the PLD. The only limitations
on the expressions are those imposed by
the numberof inputs, outputs, and internal
product terms provided by the particular
PLD circuit selected. The efficiency of implementing the set of equations can be
increased significantly by applying DeMorgan's theorem, and utilizing the programmable invert function on each output.
If there seems to be too few product terms
to handle a relatively large equation set,
one of several minimization methods can
be pursued.
The probability of reducing such equations to manageable size is enhanced
through the flexibility of shared AND terms
for each output function, the accessibility
of all AND terms to each output, and having a programmable invert function on
each output. All of these features can be
utilized by applying the manual manipulation of Venn Diagrams or Karnaugh Maps.
However, the time and effort to accomplish these tasks as well as document the
effort for procurement specification purposes increase the need and desire to
421
have software programs to automatically
perform such manipulations.
Many types of software programs are being developed to provide this assistance
for operation on a wide range of computer
hardware. This list of software is expanding rapidly, consisting of both Signetics
generated software and some independent software houses' contributions.
This discussion is intended to outline the
Signetics developed software program
called AMAZE (Automatic Map And Zap
Equation Entry). The AMAZE software
program currently consists of five modules, BLAST ('Boolean Logic And State
Transfer' entry program), PTP ('PAL To
PLD' conversion program), DPI ('Device
Programmer Interface' program), PLD
SIM (,PLD Simulator' program) and the
PTE ('Program Table Editor' program).
Other modules will be added when product developments require additional software tools.
It must be noted that the AMAZE program
is not by any means the total extent of software available for use in designing with
PLD (Programmable Logic Devices).
Several other commercially available PLD
Design Software packages support
Signetics' PLD product line. Please contact your local Signetics representative for
the latest word on the most currently available software.
Signetics Programmable Logic Devices
AMAZE
Programmable Logic Development Software
AMAZE Version 1.8
Description
The AMAZE software program Automatic Map
And Zap Equation Entry software, consists of
the following five modules:
• BLAST ('Boolean Logic And State
Transfer' entry program)
• PTE ('Program Table Editor')
Equipment Requirements (for
Version 1.8)
• Platform 1: IBM-PC, XT, AT, PS-2 and
compatibles
- Memory: Minimum of 640K bytes
- Operating system: PC-DOS version
2.1 or higher
- Disk Drive: One hard disk drive and
one double sided floppy disk drive
• PTP (,PAL To PLD' conversion program)
• DPI ('Device Programmer Interface'
program)
• PLD SIM ('PLD Simulator' program)
Each module performs specific tasks as outlined in the following section.
Features
• Muttiple modules allowing expansion
for future requirements
Products Supported
AMAZE Version 1.8 supports the following
products:
20-Pin PLDs
PHD16N8
PLC18V8Z11
PLHS16L8A1B
PLHS18P8A1B
PLS153
PLS153A
PLUS153B
PLUS153D
PLUS16L8
PLUS16R4
PLUS16R6
PLUS16R8
PLS155
PLS157
PLS159A
24-Pin PLDs
PLC42VA12
PLHS473
PLS167
PLS167A
PLS168
PLS168A
PLS173
PLS179
PLUS20L8
PLUS20R4
PLUS20R6
PLUS20R8
PLUS173B
PLUS173D
1OH20EV8I1 0020EV8
• Each module designed to be user
friendly
• Both HELP and ERROR messages
• Document printout: Header. Pin
diagram, Boolean equation and Fuse
map
• Interface with most commercial
programmers
• SIMULATOR programs provide
applications assistance and Automatic
Test Vector Generation
28-Pin PLDs
PLC415
PLS100
PLS101
PLS105/A
PLUS105-40
PLUS405
52-Pin PLDs
PLHS501
November 1989
422
Signetics Programmable Logic Devices
AMAZE
Programmable Logic Development Software
BLAST
PTE
Booiean logic And State Transfer program is
a menu driven software package that supports
the engineer in implementing logic designs into
Signetics Programmable Logic Devices. It
checks design data and automatically compiles
a program table from Boolean and State Machine equations. Data from the program table
is then used to produce a Standard File which
contains the fusing codes in a form acceptable
to all the AMAZE modules (i.e., PLD--SIM and
DPI).
Program Tab!e Entry is an interactive editor
which allows the logic designer to enter data
into AMAZE in the form of SIGNETICS
APPROVED PROGRAM TABLES. Each
Signetics PLD data sheet has the program
table format which applies to that device. In
addition, PTE can be used to document completed designs and to make changes in logic
functions which have been previously defined
in the BLAST module.
BLAST reports the logic and syntax errors, and
lists the equations in a Sum of Products form,
which can help the userto minimize the entered
logic equations. It will automatically partition
State machine designs into specified devices,
and then delete redundant terms during compilation.
PROGRAM TABLE EDITOR
FEATURES
BLAST also provides the capability of modifying a current logic set programmed into a device by overlaying new data onto unused fuses.
• On-line editor provides automatic
cursor control and prevents syntax
errors
• Allows easy creation and editing of new
and existing PLD designs
• Truth-table representation of PLD
fusemap in High.lLow format
• On-line help screen and print facility
BOOLEAN LOGIC AND STATE
TRANSFER FEATURES
• User friendly interactive pin list editor
• Boolean equation or state vector entry
• Schematic entry (with external
schematic capture package)**
• Operates on standard PLD fusemap
files
PTP
PAL To PLD is a conversion program to allow
easy transfer of the various PAL 20- and
24-pin circuits to the Signetics PLD 20- and
24-pin series devices.
• Supports all Signetics PLDs and PLEs
PTP can automatically upload the PAL pattem
from a Commerical programmer, convert the
pattern into a PLD pattern, and then download
the PLD pattern into the programmer. The PAL
pattern and it's corresponding PLD pattern are
documented, and the PLD pattern can be
directed to other AMAZE modules.
• User definable device flies for support
of PALs and other PLD devices
PTP can also convert the PAL fuse file in a
HEXPLOT formal.
• On-line error checking, minimization,
and design overlay
• Capable of partitioning single designs
into multiple PLDs
(~AMAZE acoepts TTL schematics gonorale-- B iii 08
D
v
'---
A"
LO R CK
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ac
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Application Note
Signetics Application Specific Products
AN7
Single Chip Multiprocessor Arbiter
Table 1. FPLS Program Table for Priority Arbiter
tRANSITION TERM
No.
i i i
5
0
1
2
3
4
5
7
8
4
3
INPUT VARIABLE (1m)
1
2
- - - -
1
1
-
-
-
1
0
.
,..
15
1.
17
-
L
-
-
-L
L
H
L
H
L
H
H
--L
L H
H H
H H
L
L H
H H
H H
H H
L
H
H
H
H L
L H H
H H H
H H H
-
30
31
32
34
35
-
-
L
H
-
:It
33
--
-
20
21
22
23
24
25
28
27
28
5-r-.- 3- -2
-
,.
ii i i
3
2
1
"0
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
- - - - -- - - -- - -- - - - - L HL
•
10
11
12
13
i i 7 i
H
H
H
H
H
L
H
H
H
H
PRESENT STATE (Po
L
H
H
H
H
L
L
L
H
L
L
H
L
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
-
H
-
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
"" """"
H
- --
.---.-
OUTPUT TERM
-
H
H
H
H
H
H
H
H
H
H
H
H
""
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
L
H
H
H
"
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
NEXT STATE (No)
-5 --4 -3 -2
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
"
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
""
H
L
L
L
H
L
L
L
H
H
H
H
-
1
OUTPUT FUIICTlON ('n)
- -7 -8 5
0
H
H
H
L H H
H H H
L H H
H
H
L
H
L "I"
H H H H
H L H H
H L H H
H L
H H H H
H L H H
L
H
H H H H
H L H H
H L H H
H H H H
H L H H
H L H
L
H
H L
H
H H H H
H H H H
H H
H L
L H
H L H H
L H H H
L L H H
H H H
H H H H
H H
H H
H H
-
•
H H
H H
H H
H
L
H H
H H
H H
H L
H H
H H
H H
H L
H H
H
H H
H L
H H
H H
H H
L
-2 -1 -0
""
L
H
"" "" """
" " "
""" " " "" " " "
"" " " "
" "
"
H
H
H
H
H
3"
H H H
H H L
H L
L
H
H
L
H L H
L H
H H H
H
H
H L
L H H
H
H
H
L
H
H
H
H
H
H
H
H
L
"
"""
" "
H
H
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
-
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H H
H H H
H H H
H H
H H H
H H H
H H H
H H H
H H H
H H H
H
L
H
H
L
H
June 1988
10 lei IdllI~ Id'id' lei
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H
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H
H
H
H
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38
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Application Note
Signetics Application Specific Products
AN7
Single Chip Multiprocessor Arbiter
******************** ARBITERS ********************
@DEVICE SELECTION
ARBITERB/B2Sl05
@STATE VECTORS
[ FF5, FF4, FF3, FF2, FF1, FFO J
wo
WI
W2
= 03Fh
03Eh;
03Dh;
W3
= 03Ch ;
W4
W04
GAO
GAl
GA2
GA3
GA4
GBO
GBI
GB2
03Bh;
I ll---b
06h
07h
OEh
OFh
16h;
100---b
110---b
IOO---b
@INPUT VECTORS
@OUTPUT VECTORS
[OB2, OB1, OBO, OA4, OA3, OA2, OA1, OAOJ
OAO'
OAI'
FEh
FDh
QA2'
FBh
OA3'
F7h
OA4'
EFh
OBO'
DFh
OBI' = 8Fh
082'
7Fh
NOGRANT' = FFh
@TRANSITIONS
WHILE CWO]
CASE
[/RAOl " [GAO] WITH [OAO' l
[/RAI * RAO] " [GAll WITH [OAI'l
[/RA2 * RAI * RAOl " [GA2] WITH (OA2' l
(/RA3 * RA2 * RAI * RAOl I I (GA3l WITH (OA3'l
(/RA4 * RA3 * RA2 * RAI * RAOl " (GA4l WITH (OA4']
ENDCASE
WHILE (WIl
CASE
[/RAll ,. (GAll WITH [OAI'l
[/RA2 * RAI] " (GA2l WITH (OA2']
[/RA3 * RA2 * RAIl"
[GA3l WITH [OA3'l
[/RA4 * RA3 * RA2 * RAIl" [GA4l WITH [OA4'l
[/RAO * RA4 * RA3 * RA2 * RAIl,. [GAOl WITH (OAO'l
ENDCASE
a. Arbiter State Equations
Figure 7
June 1988
442
Signetics Application Specific Products
Application Note
AN7
Single Chip Multiprocessor Arbiter
WHILE [W2)
CASE
(/RA2J :: [GA2J
[/RA3 * RA2J :;
WITH [QA2']
[GA3J WITH CQA.3']
[/RA4 " RA3 " RA2)
II
[GA4) WITH [QA4']
(/RAO
*
RA4
*
RA3
*
RA2J ::
(IRA!
*
RAO
*
RA4
*
RA3 .. RA2J
[GAO] WITH (QAO']
::
[GAl J WITH
[QA1' J
ENDCASE
WHILE (W3]
CASE
[/RA3]
C/RA4
[/RAO
*
*
II
[GA3] WITH lQA3')
RA3J ::
RA4
*
[GA4J WITH CQA4']
RA3J
::
[GAO]
[fRAI " RAO " RA4 " RA3)
[/RA2
*
RAt
*
RAO
*
II
*
RA4
WITH [DAO')
[GAl) WITH (QAI')
RA3J
::
[GA2J
WITH (QA2' )
ENDCASE
WHILE (W4)
CASE
[fRA4) II
[/RAO
*
(GA4) WITH (QA4')
RA4J
::
[GAO] WITH [QAO')
(/RAI " RAO " RA4) I I [GAl) WITH (QAI']
[/RA2 * RAl * RAO * RA4J :: CGA2J WITH (QA2')
[!RA3
*
RA2., RA1
*RA1
*
RA4]'::
[GA3J WITH [QA3')
ENDCASE
WHILE (W041
CASE
[/RBO
[/RBt
l/RB2
ENDCASE
*
*
RA4
RBO
* RA3 * RA2 * RAl * RAO] :: [GBO] WITH [080']
*
RA4
*
RA~.
*
RA2
*
RA1
*
RAO]
::
(G81J
WHILE (GAO]
IF [RAO] THEN [WI] WITH lNOGRANT')
WHILE (GAl)
IF (RAI) THEN CW2] WITH lNOGRANT
J
WHILE (GA2]
IF [RA21 THEN (W3] WITH lNDGRANT']
WHILE [GA3]
IF [RA3] THEN [W4] WITH (NOGRANT'
WHILE [6A4]
IF [RA41 THEN CWO] WITH (NOGRANT'
WHILE [GBO]
IF (RBO) THEN [GBI] WITH (NDGRANT')
WHILE (GBI]
IF [RBI] THEN [692] WITH [NOGRANT'
WHILE [GB2J
IF (RB2] THEN (GBO] WITH [NOGRANT']
a, Arbiter State Equations (Continued)
Figure 7 (Continued)
June 1988
WITH [QBt']
* RB! .. RBO * RA4 * RA3 * RA2 * RA1 * RAO] :: [6B2] WITH [082']
443
Application Note
Signetics Application SpecWic Products
AN7
Single Chip Multiprocessor Arbiter
********************
ARBITERB
4t##=It##ft:####fUt######## p I
LABEL
CLOCK
RB2
RBI
RBO
RA4
RA3
RA2
RA.
RAO
OB2
DB.
OBO
OA4
**
**
GND
**
**
**
**
**
**
**
**
**
**
**
.*
N
L
********************
I S T #ftft ........ #.##.# •••••• _
LABEL
**
+5V **vee
I
**N/C
I
**N/C
**N/C
**N/C
**N/C
**N/C
I
**N/C
I
**N/C
PR
**PRESET
**OAO
0
0
**OAl
0
**OA2
FNC **PIN --------- PIN** FNC
CK
I
I
I
I
0
1-1
2-1
3-1
4-\
**
**
**
**
**
**
\-28
\-27
1-26
B
2
S
5-1
6-1
7-1
•
8-1
0
5
9-1
10-1
11-\
0
12-\
13-\
0
0
OV
14--1
\-25
**
**
**
**
\-24 ...*
1-23 **
\-22
1-21
\-20
\-19
\-18
I ~·17
1-16
1-'5
**
**
**
**
**
..
*.
**
a
**OA3
b. Arbiter Pin List
********************
@DEVICE TYPE
ARBITERS
********************
825105
@DRAWING
************
MULTI -PROCESSOR BUS ARB I TOR
@REV!SION
************
@DATE
ARBITERB REV. 0
************
JULY 26, 1985
@SYMBOL
************
@COMPANY
******H****
@NAME
********H**
@DESCRIPTION
@INTERNAL SR
ARI:rITERB
SIGNE lIes
DAVID k. WONG
FUr' FLOP LABELS
FFO FFl FF2 FF3 FF4 FF5
@CfJMMON F'I"UlJUCT TERM
@C[JMPLEMENT ARRAY
@LOGIC EI,1,UATION
c. Arbiter Boolean Equations
Figure 7 (Continued)
June 1988
444
Signetics Application Specific Products
Application Note
AN7
Single Chip Multiprocessor Arbiter
Table 2. Arbiter Program Table
******************** ARBITERS ********************
************ DAVID K. WONG
************ JULV 26, 1985
Rev/I. D.
- ************ ARBITERS REV. 0
Cust/Project Date
825105
OPTION PIE
T
E
R
INPUT VARIABLE
! PRESENT ST ! NEXT ST
OUTPUT
M e l 1 1 1 1 1 -----------------------------------------------------------_ 5_4_3 _2 .. 1_0_9_8_7._6_5_4_3_2_1_0! 5_ 4_.3_2_1_0! 5_.4_3_2_1_0! 7 _6_5_.4_3 __ 2_1_0!
o A - - -,
, - - , - - - L!H H,H H H H!L L,L H H L!H H H H,H H H L!
1 A - - - - , - - - - , - - - -,- - L H!H H,H H H H!L L,L H H H!H H H H,H H L H!
2
3
4
5
6
"7
B
9
10
11
12
13
14
15
16
A
A
A
A
A
A
A
A
A
A
-
-
-
-,-,-,-,-,-,-,-',-,-,-
-
...,
-
-,-,-,-,-,-,-,-,-,-,-
-
-
A -
-
-
-,- -
-
-,- -
-
A -
-
-
-,- -
-
-,- -
-
A A -
-
-
-,'- - - - , - -,- - - -,-
-
A -
-
-
-,-- -
-
-,-- -
-
17 A 18 A -
-
- -,- - , - .- -
-,- -,- -
-
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
A
A
A
A - A - A --
A - A -
-
-
-
A -
°
(I
0
0
0
0
0
°° °
-
-,- -
-
-,-
-
H
L.
L
H
H
H
H
H,H
L,H,H,H,H,L
L H,H
_.,- L H H,H
H H -
L
L
H
L
H
H
H
H!H H,H H
H!H H,H H
H~H H,H H
-!H H,H H
-!H H,H H
-!H H,H H
-!H H,H H
L!H H,H H
-!H H,H H
-!H H,H H
-!H H,H H
L!H H,H H
H!H H,H H
-!H H,H H
-!H H,H H
LIH H,H H
H'H H,H H
H H H,H H
- H H,H L
L H H,H l.
H H H,H L
H H H,H L
- H H,H L
H H H,H -
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
-
H!L
H!L
H!L
L!L
L!L
L!L
L!L
L!L
H!L
H!L
H!L
H!L
H!L
L!L
Lil.
L'L
L L
L. L
H L
H L
H L
H L
H L
- H
L,H
L,H
H,L
L,L
L,H
L,H
H,L
L,L
L,H
L,H
H,L
L,L
L,L
L,H
ti,L
L.L
L.L
L,H
H,L
L,L
L,L
L,H
L,H
L,H
H
H
H
H
H
H
H
H
H.
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-
'-,- -
-
-,-
-,- -,-,- ,
-
-,- ,H
-.H H,- -
H
--
-,- -
-
-,- -
H -,- -. -
,
-,0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
-,- H - --,H - 0 0,0 0 0
0 0,0 0 0
0 0,0 0 (I
0,0
0
0 0,0
0
0 0,0 0 (I
0 0,0 (I
0,0 0 0
0 0,0 0 0
0 0,0 (I 0
(I 0,0 0 0
0 0,0 0 (I
A A A 0 0
(I 0
0
0 0
0 0
0
0
0 0
0 0
0 0
0 0
0 0
-,- '-,-
-,- - -,- - -,- - - -,- - - , - - .-
H,H
-,L
L.H
H,H
H,H
H
H
H
L
H
H
H
H
-
- -,.- - , - - -,- - - , - .-
_. -
- - _.
-
L
H
H
L
H
H
H
L
H
H H H H,li
H H,L - H H H H,H
H L,L H L L,L H H L H H,t-! H H
A A
A
A
A
-,- -,- -,-- -,-,-- -
-,-,L
L,H
-,-,-,L
L,H
H,H
-,-,L
L,H
H,H
0
0
0
0
0
0
0
°°
(I
0
0 0
0 0
(I 0
0
0
0
°°
0
0
(I
0
0
°
0
0
°
-,L H H H,H
°°
-
°
- , - -. -
-
-
-,- - - 0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0 0 0
0 0 (1
0 0 0
0 (I 0
0 0
0 0 0
0 (I (I
0 (I 0
0
0
0 0
0 0 0
0 0 0
°
L L,L
L. L,H
L L,H
L H,L
H L,H
H H,L
H L,L
0 0,0
0 0,0
0 0,0
0 0,0
0 0,0
(I 0,0
0 0,0
0 0,0
0 0,0
0,0
0 0,0
0 0,0
°° °
H
H
H
H
_.
0
0
0
H
H
H
H
0
H
L
H
L
.0
0
0 0
I) 0
0 0 0
0
0 0 0
(I 0 (I
0 0 0
0 (I 0
0
0
0
0
°
°
°°
H
H
H
H
H
H
H
0
0
':..
°
0
0
(I
0
(I
°° °
(I
0
H,H
H,H
H,H
H,H
H,L
L,L
L.H
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
H
H
L
H
0
0
0
0
0
0
L
L
H
H
_.
0
0
0
°
(I
L!H
H!H
L!H
H!H
L!H
H!H
L!H
L!H
L!H
H!H
L!H
L!H
H!H
H!H
L'H
L!H
H!H
L.~H
LIH
L!H
H!H
LIH
H H
- H
- H
- L
L H
H H
L H
H H
H H
- H
- H
- H
0 (l
0 0
0 (I
0 0
(I 0
0 0
0 0
0
0
0
(I 0
0 0 (I (I
0 0 0 (I
0
0 0
0 (I
0
°
°
°°
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H,H
H,L
L,H
H,H
H,H
H,L
L,H
H,H
H,H
H,L
L,H
H,H
H,H
H,L
L,H
H,H
H,H
H,H
L,H
H.H
H,H
H,H
H,L
H,H
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
L H H,H H
H H H,H H
H H H,H H
H H H,H H
H H H,H H
H H H,H H
H H H,H H
H H H,H H
H H H,H H
H H H,H H
i) 0 0,0 0
(I (I 0,0 0
0
0,0 0
0 0,0 0
0
0,0
(I 0,0 0
0 0 0,0 0
0 0 0,0 0
0 0 0,0
0 0 0,0 (I
0 0 0,0 0
0 (I 0,0 (I
°
°°
°
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H~
H!
H!
L!
H!
H!
H!
L!
H!
HI
H!
L!
H!
H'
H~
L!
H!
H!
H~
H!
H H~
H H!
H H!
H H!
H
H
H
H
H
H
0
0
0
0
°°
°
H!
H!
H!
H!
0
0
0
(I
0
0
0
HI
H!
H!
H!
H!
H!
o!
O!
O!
O!
O!
O!
O!
O!
O!
O!
O!
O!
NNNNNNNNRRRRRRRRFFFFFFFFFFFFOOOOOOOO
/////i//BBBAAAAAFFFFFFFFFFFFB~BAAAAA
CCCCCCCC2104321054321054321021043210
June 1988
445
Signetics Application Specific Products
Application Note
AN7
Single Chip Multiprocessor Arbiter
SUMMARY
Table 3. Design Alternatives for the Priority Arbiter
As can be seen from the circuit diagrams. the
FPLS can offer significant advantages over
discrete MSI arrays in the design of state
machines. The tradeoff in both design alternatives for the Priority Arbiter is shown in
Table 2. Clearly. the FPLS approach uses
fewer parts. with savings in PC board space
and power requirements.
REFERENCES
1.
PARAMETER
Parts count
PCB space
Power
Voltage
2.
W.W. Plumber: "Asynchronous Arbiters";
IEEE Transactions on Computers. January 1972. pp. 37 - 42.
3.
June 1988
R.C. Pearce. J.A. Field. and W.O. Little:
"Asynchronous Arbiter Module"; IEEE
Transactions on Computers. September
1975. pp. 931 - 933.
K. Soe Hojberg: "An Asynchronous Arbiter Resolves Resource Allocation Con-
446
F.P.L.S.
PROM/LATCH
1 IC
.84 in 2
.65W
+5V
""19IC's
7.92 in 2
2.85W
+5V
4.
!licts on a Random Priority Basis"; Computer Design. August 1977. pp.
120-123.
K. Soe Hojberg: "One-Step Programmable Arbiter for Multiprocessors"; Computer Design. April 1978. pp. 154 - 158.
ANa
Signefics
Introduction To Signetics
Programmable Logic
Application Note
Application Specific Products
Author: K. A. H. Noach
INTRODUCTION
Custom logic is expensive - too expensive if
your production run is short. 'Random logic' is
cheaper but occupies more sockets and
board space. Signetics Programmable Logic
bridges the gap. Using PLD, you can configure an off-the-shelf chip to perform just the
logic functions you need. Design and development times are much shorter, and risk
much lower than for custom logic. Connections are fewer than for random logic, and, for
all but the simplest functions, propagation
delay is usually shorter. Yet another advantage that PLD has over custom logic is that it
allows you to redesign the functions without
redesigning the chip - giving you an invaluable margin not only for cut-and-try during
system development, but also for later revision of system design. You're not tied down
by the need to recover capital invested in a
custom Chip.
A PLD chip is an array of logic elements - gates, inverters, and flip-flops, for
instance. In the virgin state, everything is
connected to everything else by nichrome
fuses, and although the chip has the capacity
to perform an extensive variety of logic functions, It doesn't have the ability to. What gives
it that is programming: selectively blowing
undesired fuses so that those that remain
provide the interconnections necessary for
the required functions.
Signetics Series 20 PLD, named for the
number of pins, supplements the well-known
Series 28. The package is smaller - little
more than a third the size, in fact - but the
improved architecture, with user-programmable shared 1/0. compensates for the fewer
pins. The series comprises the following
members, in order of increasing complexity:
• PLS151 - field-programmable gate
array
• PLS153 - field-programmable logic
array
June 1988
• PLS 155 - field-programmable logic
sequencer
• PLS 157 - field-programmable logic
sequencer
• PLS 159 - field-programmable logic
sequencer
Entry to all the devices is via a product matrix,
an array of input and shared 1/0 lines fuseconnected to the multiple inputs of an array of
AND gates (see Figures 1, 2 and 5). To
exploit the capacity of any device, it is important to make the most economical use of the
AND gates it has available. Application of de
Morgan's theorem can help in this. For
exam~
pie, inputs for the function
F=A+B+C+D
would occupy four of the AND gates of the
product matrix. However, the same function
rewritten as
F=ABc15
would occupy only one. Moreover, the second function could be done on the simplest of
the Series 20 devices (and leave eleven
gates over for other functions), whereas the
first could not. The fact that all inputs of the
Series 20 devices, including the shared ones,
incorporate double buffers that make the true
and complement forms of all input variables
equally accessible, greatly facilitates the use
of de Morgan's theorem for logic minimiza-
tion.
To convert the minimized logic equations to
the pattern of fuses to be blown, you can use
either a programming sheet (see e.g. Table 1)
or Boolean equation program-entry software
that lets you enter the equations via the
keyboard of a terminal. The direct programmability of logic equations makes system
design with PLD simple and sure. Functional
changes can be made by replacing one PLD
chip by another differently programmed. In
many cases you can even remove the original
one, reprogram it on the spot, and re-insert it.
Programming machines qualified for the Se-
447
ries 20 are at present available from DATA II
0, KONTRON, and STAG.
FPGA PLS151
The field-programmable gate array is the
simplest of the Series 20 PLD devices; Figure
1 shows the functional diagram. The array
can accept up to 18 inputs. There are six
dedicated input pins (A) and twelve (A') that
can be programmed as inputs, outputs, or
bidirectional 1/0. All input variables, whether
on dedicated or programmed input pins, are
available in both true and complement form in
the product matrix (B), and both forms are
buffered: either form can drive all 12 product
lines if required. In the virgin state, all the
input variables and their complements are
connected to all the product lines via a diode
and a fuse (C), and the product matrix is
effectively inoperative. To enable it to generate the required functions, unrequired connections between individual input lines and
product lines are severed by blowing the
connecting fuses_
At the output of the product matrix are 12
NAND gates, each with 36 inputs to accommodate the 18 possible input variables and
their complements. Each of the product terms
is normally active-Low, but a unique feature of
Signetics PLD is that any or all of them can be
independently programmed active-High. This
is done by means of an array of exclusive-OR
gates (D) at the NAND-gate outputs; when
the fuse that grounds the second input of
each OR gate is blown, the output of that
gate is inverted.
The product matrix and exclusive OR-gate
connections shown in Figure 1 illustrate the
flexibility conferred by having buffered complements of all input variables internally available, together with independently programmable output polarities. Output B , shown
"
with its exclusive OR-gate fuse intact, is
programmed
l311 = lol1lS
Signetics Application Specific Products
Application Note
Introduction To Signetics Programmable Logic
LOGIC GATES G
AN8
CONTROL
GATES
02
10
0,
00
@
c
shared
ilOpins
.,
.,
·7
83
L-----------------~~~+tt_;,~, .,
~--------~rH~+trrtr~7
~----------~~+trrrrr_~8
"-------------~~+trrtr~9
"----------------~~+trrr_~11
L---------------------------~~ittt_i'~·.
L-------------------------------~~H1,_~14
L----------------------------~~~~~15
L----------------------------------4rrr_~l~
86
87
••
S,
L--------------------------------------------------------*tt-t'~7
L------------------------------------------------------------*r-t'~8 .~
1
I
I
8 11
~
~~Je~lcated
rnputs;.A', programmable 1/0. 8, prod.uci (NAND) matrix With fused connections
each of the vertical lines In the matrix represents 36 inputs to the terminating NAND
F, fuse-programmable control matrix. Square dots (.) represent
gated. D, exclusive-OR array With Inputs grounded via fuses for polarity control E,
permanent conneclJons; round dots (e) Intact fuse connections Connected as
the array IS programmed for the functions 8'1 '" 10 11 is and 810 '"
f;" is.
r;;
Figure 1. Field-Programmable Gale Array PLS151A
-----------------------------------------------------------------~
June 1988
448
Signetics Application Specific Products
Application Note
AN8
Introduction To Signetics Programmable Logic
CONTROL TERMS
LOGIC TERMS P
NOTE:
A to F, as In Figure 1. G, sum (OR) matrix. Connected as shown, the array is programmed as a single-bit adder with Carry Enable.
Figure 2. Field-Programmable Logic Array PLS 153
At the same time, and without using any
additional inputs, output BlO (fuse blown) is
programmed
B'0~TQi1i5
Each of the exclusive-OR gates drives a
three-state output buffer. In the virgin state all
the buffers (E) are disabled and therefore in
the high-impedance state. The function of the
programmable I/O pins (A') is ,then deter·
mined by the I/O control matrix (F). The three
AND gates at the control-matrix output are
June 1988
Active-High, and when one of them is in the
High state, the four output buffers it controls
are enabled; the corresponding I/O pins then
act as outputs. conversely, when a controlmatrix AND-gate output is Low and the control fuse for the corresponding Tri-state buffer
is intact, the pins controlled by that gate act
as inputs. Thus, these pins can be programmed in groups of up to four to act as
inputs or outputs according to the state of
selected input variables. If required, any of
the programmable I/O pins can be made a
449
dedicated output by blowing the control fuse
of the output buffer associated with it.
The speed of the FPGA compares favorably
with TTL, although its propagation delay is
longer than the individual gate delay of TTL.
When the number of inputs required is large,
however, the FPGA more than makes up for
this. When more than eight inputs are required, for example, the FPGA has a distinct
advantage. Then, the overall propagation de-
Application Note
Signetics Application Specific Products
Introduction To Signetics Programmable Logic
lay of TTL often amounts to two or three gate
delays, but that of the FPGA to only one.
AN8
FULL ADDER
A
FPLA PLS153
Architecture
With two levels of logic embodied in a product
matrix terminating in 32 AND gates coupled
to a ten-output OR matrix (Figure 2), the
FPLA is a step up in complexity from the
FPGA. Again, there is provision for 18 input
variables, internally complemented and buffered, but here divided between eight dedicated input pins and ten individually programmable 1/0 pins. As before, exclusive-OR gates
grounded by fuses provide output polarity
control, and any of the programmable 1/0
pins can be made a dedicated output by
blowing the control fuse of the output buffer
associated with it.
Co
Programming
Figure 3. Single-Bit Full Adder in TTL (e.g. 74LS80)
When the required functions have been defined, corresponding programming instructions are entered in a programming table, the
layout of which reflects the FPLA architecture. (A Signetics computer program named
AMAZE, which accepts 600lean equations as
input and generates an FPLA programming
table as output, is also available.) The programming machine blows the FPLA fuses in
the pattern prescribed by the table.
As an illustration of FPLA programming, consider a full adder. Figure 3 shows a TTL
version (74LS80) and the corresponding logic
equations. Note that the feedback of Cn + ,
introduces a second propagation delay. In the
FPLA this is eliminated by redefining ~ in
terms of A, 6, and Cn , as shown in Figure 4,
and using the right side of the equation for
Cn + , instead of the term itself. At first glance
this would appear to require a minimum of
three product terms for Cn
plus four for ~,
or a total of seven. The Karnaugh maps,
however, show considerable overlap between
the two functions: the map for Cn
differs
from that for ~ only by having A 6 Cn instead
of ABC;;. Rewriting the equation for C n + , to
introduce ABC;; and eliminate A 6 Cn,
+,
+,
Gn
+, = ABC;; + A 6 C;;
+
A B Cn + A B Co
increases the number of product terms by
one, but now Cn + , and ~ have three terms in
common. Therefore, since the FPLA allows
multiple use of productterms, it is sufficient to
program each of the common terms only
once; thus, the original seven product terms
are effectively reduced to five.
To fill in the programming table (Table 1), first
allocate inputs and outputs.
}crl1
Coi' -.--A
Cn +
I
= ACn +
1+
Ben 'I-
1+
cnc n +
'" ABCn + ABCn + ABc n
1 + ABC n
+ ABC n
=AB+ACn+BCn
= ABCn + ABC n + ABCn + ABCn
Figure 4. Karnaugh Maps and Logic Equations for the Full Adder
of Figure 3, Illustrating how the Equations are Reduced for
the FPLA Implementation Shown in Figure 2 and Table 1
Inputs: A
6
Cn
= 10
= I,
= 12
Outputs:
Cn + , = 6 7
!
= 68
~
= 69
Next, enter the product terms of ~ in the
product-matrix (AND) part of the table, using
H to indicate a true input and L a false one.
• Term 0 .is A B Co: mark H, L, L in
columns 10, I" 12 of row 0
• Term 1 is A B Co: mark L, H, L in
columns 10, I" 12 of row 1
• Term 2 is A B Cn: mark L, L, H in
columns 10, I" 12 of row 2
• Term 3 is A 6 Cn: mark H, H, H in
columns 10, I" 12 of row 3.
Fill the rest of rows 0, 1, 2, and 3 with dashes
to indicate that all other inputs are to be
disconnected from Terms 0, 1, 2, and 3 (fuses
blown).
The product terms of ~ must be added to
form the sum-of-products required at output
June 1988
ABC n
1 =AC n +BCn +AB
450
6 9 , Indicate the required addition by putting
an A (for Attached, i.e. fuse unblown) in the
Term 0, 1, 2, and 3 spaces of column 6(0)9;
Term 4 is not required for ~, so put a dot in
the Term 4 space to indicate that it is to be
disconnected (fuse blown). To indicate that
the output is to be Active-High, put an H in the
polarity square above the 6(0)9 column. Finally, fill row D9 with dashes to indicate that
all fuses on line D9 of the control matnx are to
be blown and 69 is to be a dedicated output.
This completes the programming of ~.
The! output on 68 is programmed in just the
same way, except that the polarity square
above the 6(0)8 column is marked L to
indicate Active-Low. (Note that in the FPLA,
the ~ and! outputs change simultaneously,
because all output signals traverse the exclusive-OR array (D), whether they are ActiveHigh or Active-Low. In the TTL full adder
shown in Figure 3, the output inverter delays
the change of ~ with respect to !.)
Signetics Application Specific Products
Application Note
ANa
Introduction To Signetics Programmable Logic
Table 1. FPLA Programming Table Filled In for the Full Adder of Figure 2
POLARITY
H L L
~
;
~
:i
§I
III
-U
!mJ
i5
;i~
~..:~
:E
C
II:
Z
III
--
CI
0
II:
II.
: --7
~ :t~ ~
9 -
tiS
~
S
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
26
29
30
31
D9
08
D7
06
05
04
03
D2
01
00
. '::.
w
"'w
~~
II:z
~
June 1988
AND
6
5
I
4
3
9
2
1
0
L
L
H L
L
-- - -- -- -- LH LH
-- --- -- L L
H H
H
L
8
7
6
B(I)
5 4 3 2 1 0
- -- -- -- -- -- - - -- - -- - - - - - - - - - - - --
-- -- -- - H- - - - - - - - - - - - ---- ---- -
8
7
6
5
4
3
2
A
B
L
E
I
~
+
IUc
451
.. .
=~J
1 19 18 17 16 15 14 13 12 11 9
~ Cn B A I
OR
B(O)
9 8 7 6 5 4
A A A
A A A
AAA
A A
A
3
2
1
0
Signetics Application Specific Products
Application Note
ANa
Introduction To Signetics Programmable Logic
The output Cn + 1 on 87 contains three of the
same terms as ~, plus the term ABC;;. Only
this last term needs to be additionally programmed in the product matrix: mark L, L, L in
columns 10, 11, 12 of the Term 4 row. Indicate
the addition
A B C;;+A 8 C;; +A B Cn+A B C;;
by putting an A in rows 0, 1, 2, and 4 of
column 8(0)], and show that Term 3 (A 8 Cn)
is not required by putting a dot in the Term 3
row to indicate disconnection (fuse blown).
Put an L in the 8(0)] polarity square to
indicate Active-Low.
Identifying 8 7 as a dedicated output by indicating that all the fuses to control term D7 are
to be blown, would now complete the programming of the full adder. However, a useful
supplementary feature would be a Carry Enable function to keep the 8 7 output buffer in
the high-impedance state except when the
enable input 13 is true. The output buffer is
enabled when both the fuses of a control
term are blown, or when one is blown and the
term that controls the output buffer is true.
Thus, a Carry Enable can be provided via the
13 input by leaving intact the fuse for ActiveHigh operation of the enable signal to control
term D7. To indicate this, put an H in the 13
column of row D7 and fill the rest of the row
with dashes.
The full adder with output Carry Enable uses
only four of the eight dedicated inputs, three
of the ten programmable I/O pins, and five of
the 32 AND gates. The remaining capacity
can be used for programming other functions
which may, if required, also make use of
AND-gate outputs already programmed for
the full adder.
All fuses not indicated as blown in the programming table are normally left intact to
preserve capacity for later program revisions
or the addition of supplementary functions. If
it is essential to minimize propagation delay,
however, the finalized program should include
instructions for blowing all unused fuses to
minimize load capacitance.
FPLS PLS155 - PLS157 - PLS159
Architecture
The FPLS (Figure 5) is the most complex of
the Series 20 PLD devices. Like the FPLA, it
has a 32-term product matrix followed by an
OR matrix. In the FPLS, however, the OR
matrix is larger and comprises three distinct
parts, with architecture differing in detail from
type to type. In the PLS155, for instance, the
first part consists of eight 32-input gates
coupled, like those of the FPLA, to an outputpolarity-controlling exclusive-OR array. The
June 1988
second consists of twelve additional gates
which control four flip-flops. These are what
give the FPLS its sequential character, enabling it to dictate its next state as a function
of its present state. The third part is the
deceptively simple Complement Array (I in
Figure 5): a single OR gate with its output
inverted and fed back into the product matrix.
This enables a chosen sum-of-products to
become a common factor of any or all the
product terms and makes it possible to work
factored sum-of-products equations. it is also
useful for handshaking control when interfac~
ing with a processor and for altering the
sequence of a state machine without resorting to a large number of product terms.
PLS155 has four dedicated inputs and eight
programmable I/O pins that can be allocated
in the same way as in the FPLA. It also has
four shared I/O pins (L) whereby the flip-flops
can be interfaced with a bidirectional data
bus. Two product terms, LA and LB in the
control matrix F, control the loading of the
flip-flops, in pairs, synchronized with the
clock.
Figure 6 shows the architecture of the flip-flop
circuitry in the PLSI55. The flip-flops are
positive-edge-triggered and can be dynamically changed to J-K, T, or D types according
to the requirements of the function being
performed; this considerably lessens the demands on the logic. The Tri-state inverter
between the J and K inputs governs the
mode of operation, under the control of the
product term F:
• When the inverter is in the highimpedance state, the flip-flop is a J-K
type, or a T type when J = K.
• When the inverter is active, K = J and
the flip-flop is a D type; the K input
must then be disconnected from the
OR matrix.
All the product terms from the product matrix
(Toto T31 in Figure 5) ·are fuse-connected to
the J and K input OR gates. if both fuses of
anyone product term are left intact, J = K
and the flip-flop is a T type.
The flip-flops of the PLS155 have asynchronous Preset and Reset controlled by terms in
the OR matrix that take priority over the clock.
Their three-state output buffers can be controlled from the enable pin OE or permanently
enabled or disabled by blowing fuses or
leaving them intact in the enable array (K in
Figure 5).
The PLS157 and PLS159 sequencers have,
Ulspectively, six and eight flip-flops. The architecture differs in detail but is similar in
principle to that of PLS 155.
452
Programming
The FPLS is programmed in much the same
way as the FPLA, using a table to instruct the
machine that blows the undesired fuses. It is
not necessary to work with a circuit diagram;
in fact, it is even undesirable to do so, since
applying the necessary logic reduction techniques would in most cases make the diagram difficult to read and more a hindrance
than a help. An example of how to program
the FPLS as a universal counter/shift-register
is given in the Appendix.
DEVELOPMENT AND
PRODUCTION ECONOMY WITH
PLD
Underlying the design philosophy of the
Signetics Series 20 PLD is the concept of
programmable arrays whose architecture emulates logic equation formats rather than
mere aggregations of gates. The unique combination of features which support this philosophy includes:
• double-buffered true and complement
inputs
• programmable-polarity outputs
• programmable I/O for internal feedback
and maximum freedom in allocating
inputs and outputs
• truth-table programming format
These features are common to all the PLD
devices. In the field-programmable logic sequencers they are further supported by:
• flip-flops with dynamically alterable
operating modes
• a complement array for simplified
handshaking control
From the development engineer's point of
view an important advantage of PLD is that it
eliminates breadboarding. Once the functions
required in terms of minimized logic equations
are worked out, a PLD can be programmed
accordingly. Once programmed, it will perforrn those functions.
Loading the instructions into the programming machine usually takes no more than a
couple of hours; after that, the machine can
program the devices at a rate of 100 an hour.
Moreover, since any PLD can be programmed in many different ways, PLD has
considerable potential for simplifying purchasing and stock control. One type of device
can be programmed to perform a diversity of
tasks for which it would otherwise be necessary to purchase and stock many different
devices.
Series 20 PLD is second-sourced by Harris
Semiconductor.
Application Note
Signetlcs Application Specific Products
Introduction To Signetics Programmable Logic
NOTE:
A to G, As In Figure 2. H, Flip-Flops And Bus-Load Buffer. J. Clock Input K, Output-Buffer Enable. L, Tn-state Flip-Flop Output Buffers
Figure 5. Field-Programmable Logic Sequencer PLS 155
June 1988
453
AN8
Application Note
Signetics Application Specific Products
ANa
Introduction To Signetics Programmable logic
o.E.
•
-h
ii
b
;;
c
C
a
a
ft-.....
J
_I
J 1 I~
R
p
I)
I ....
I ::.
--
J
I
K
I .... 1
-
•
Q
H
1
F,
a
J
(n)
I
-1
-1
I
-e-
From Figure A-1 it is evident that you should
choose J-K or T flip-flops for the counter
mode and D flip-flops for the shift mode, for
you then require only one product term per
flip-flop per mode. Table A-4 summarizes the
number of product terms per mode the various types of flip-flops would require.
C
.....
K
L.......--
I--CK
,..---.,
I
I
I
I
I
I
I
I (n + 1) I
I
I
I
~---'"
denotes wire-OR
denotes fixed connection
Figure 6. Architecture of the PLS 155 Flip-Flop Circuitry
APPENDIX
Programming an FPLS as a
CounterIShift-Register
Objective: to program a PLS155 FPLS as a
count-up, count-down, shift-right, shift-left
machine governed by three control
terms-COUNT/SHIFT, RIGHT/UP, LEFT/
DOWN. Direct implementation would result in
a machine with 64 state transitions (see Table
A-1), which is beyond the scope of the
PLS155 or even the 26-pin PLS105. Logic
reduction is therefore necessary.
As there are only four feedback variables (D,
C, B, A), you can do the reduction by hand,
one mode at a time; the control terms need
not be included till the summary equations
are written. Using the transition mapping
method suggested here, you can examine the
excitation equations for all types of flip-flops
June 1966
n
(R-S, J-K, D,
and choose those types that
will perform the required functions using the
fewest product terms. Table A-2 summarizes
the rules for flip-flop implementation using
transition maps; the transition symbols used
in the table mean:
PRESENT
STATE
NEXT
STATE
0
0
1
1
0
1
0
1
TRANSITION
SYMBOL
0
a
(3
1
Using these symbols, construct Table A-3
from Table A-1 to enable you to examine the
excitation equations for all types of flip-flops.
Proceeding one mode at a time, transfer the
state conditions from Table A-3 to Karnaugh
maps, as in Figure A-1. Following the rules in
454
Table A-2, derive the excitation equations for
the different types of flip-flops (the examples
shown in Figure A-1 omit the T type because
it is the same as the J-K type when J = K). In
deciding which types of flip-flop to use, remember that logic minimization with PLD is
different from logic minimization with 'random
logic': with random logic you seek to reduce
the number of standard packages required;
with PLD you seek to reduce the number of
product terms.
Table A-5 shows the completed programming
table for the counter/shift-register. The programming of Terms 0 to 15 reflects the flipflop excitation equations and illustrates the
value of being able to switch the flip-flops
dynamically from one type of operation to
another. Terms 16, 17 and 16, respectively,
provide for INITIALIZE, asynchronous RESET, and STOP functions.
The programming of the two additional inputs
HALT and BUSY illustrates the value of the
complementary, which is made active when
HALT and BUS'i" are Low (A in the Complement square of Term 16) and propagated into
all the other terms (dot in the Complement
squares of Terms 0 to 17). This means that
unless the HALT and BUSY inputs are High,
none of the product terms will be true and the
state of the machine will not change. If the
Complement Array were not used, twice the
number of product terms would be required,
even if one of the additional inputs were
omitted.
As it is, the design uses only 19 of the 32
product terms available, so there is ample
capacity for extending its capabilities. For
example, the shift-left function can be augmented by a binary multiplication capability,
using a D type flip-flop to make it shift one,
two, or three places according to the state of
two extra inputs, X and Y. Table A-6 shows
the revised programming table. The binary
multiplication function occupies nine additional product terms.
ACKNOWLEDGEMENT
Electronic Components and Applications; Vol.
4, No.2, February 1962. Reprinted with the
permission of PHILIPS.
Signetics Application Specific Products
Application Note
AN8
Introduction To Signetics Programmable Logic
Table A-1. Present-StateINext-State Table for Counter/Shift-Register
STATE
NO.
a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NEXT STATE
PRESENT
STATE
D
a
0
0
a
a
a
a
a
1
1
1
1
1
1
1
1
C
a
a
a
1
1
1
1
a
B
a
a
1
1
a
a
1
1
a
0
0
a
a
1
1
1
1
1
1
a
a
1
1
0
Count Down
A
a
1
a
1
a
1
a
1
a
1
a
1
a
1
a
1
D
1
a
C
1
a
0
0
a
a
a
a
a
a
1
1
1
1
1
1
1
a
CONTROL TERMS
COUNT /SHIFT
RIGHT/UP
LEFT/DOWN
0
1
1
1
1
a
a
a
a
1
1
1
B
1
a
a
1
1
a
a
1
1
a
a
1
1
a
a
1
Count Up
A
D
a
a
a
a
a
a
a
1
1
1
1
1
1
1
1
a
1
a
1
0
1
a
1
a
1
a
1
a
1
a
1
a
C
a
a
a
1
1
1
1
a
a
0
a
1
1
1
1
a
B
a
1
1
a
a
1
1
a
a
1
1
a
a
1
1
a
Shift Left
A
D
a
1
0
0
1
a
1
a
1
a
1
a
1
a
a
1
1
1
1
0
a
a
a
1
1
1
1
0
1
a
1
0
1
1
a
1
a
1
a
a
1
C
a
a
1
1
a
a
1
1
a
a
1
1
a
a
1
1
B
a
1
0
1
a
1
a
1
a
1
a
1
a
1
a
1
Shift Right
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D
C
0
0
1
a
1
a
1
a
1
a
1
a
1
a
1
0
1
a
0
a
a
a
a
a
1
1
1
1
1
1
1
1
a
1
a
Table A-2. Rules for Flip-Flop Implementation Using Transition Maps
FLIP-FLOP
TYPE
R·S
D
T
J·K
June 1988
INPUT
MUST
INCLUDE
MUST
EXCLUDE
S
R
D
a
~
a,1
a,1
T
a,~
J
K
a
~
455
M
~,a
0,1
a
1
REDUNDANT
1,x
a,x
x
x
1,~,x
a,a,x
B
a
a
a
a
1
1
1
1
a
a
a
a
1
1
1
1
A
0
a
1
1
a
a
1
1
a
a
1
1
a
a
1
1
Signetics Application Specific Products
Application Note
Introduction To Signefics Programmable logic
AN8
Table A-3. Transition Table for Counter/Shift-Register
STATE
NO.
TRANSITION
PRESENT
STATE
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Count Down
Count Up
B
A
0
C
B
A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
a
a
a
a
0
0
0
0
0
0
0
(J
1
1
1
1
1
1
1
0
0
0
(J
1
1
1
0
(J
1
a
a
a
0
(J
1
a
0
0
0
0
0
0
0
0
(J
a
a
a
a
0
0
0
(J
1
1
1
0
(J
1
a
a
a
0
(J
1
(J
1
1
1
1
1
1
1
(J
(J
(J
(J
(J
(J
a
(J
C
0
0
0
a
1
1
1
(J
0
0
0
a
1
1
1
(J
Shift Left
B
A
0
a
a
(J
1
(J
0
a
(J
a
a
(J
1
(J
0
a
(J
a
a
(J
1
(J
0
a
a
(J
1
(J
a
0
0
0
0
0
C
0
0
a
a
a
a
(J
(J
1
1
0
0
a
a
(J
(J
(J
(J
1
1
1
1
(J
a
(J
a
a
(J
(J
1
1
Shift Right
B
A
0
0
(J
0
(J
0
(J
0
(J
a
(J
1
0
a
(J
1
0
a
a
1
a
(J
1
0
a
a
1
(J
1
a
1
1
0
0
C
0
0
0
0
(J
(J
(J
(J
a
0
a
0
a
0
a
a
a
a
a
(J
1
(J
1
(J
1
(J
1
1
1
1
1
B
A
0
0
(J
(J
0
(J
a
a
1
1
0
0
(J
(J
a
a
1
1
Table A-4. Number of Product Terms Required for Counter/Shift-Register
Flip-Flop Excitation
FLIP-FLOP
TYPE
SR only
JK only
o only
FPLS
COUNT
UP
COUNT
DOWN
SHIFT
RIGHT
SHIFT
LEFT
8
4
10
4(J-K)
8
4
10
4(J-K)
8
8
4
4(0)
8
8
4
4(0)
@
®
i
K
D
o
@
ABCD
A
ABC
loB
loB
ABCD
ABC
ABC
K
,
A,B+A.
ABC+iC+AC
ABCD+ cD+iD+ AD
D
A
,
AB
AB
A
A
A
@
@
A
lB
ABC
ABCD
A
liB
ABC
i
lB
AieD
ABC
A
AB+A8
A:8C+AC+8C
AiCD+CD+AD+BD
i8
ABC
SHIFT LEFT
SHIFT RIGHT
@
®
0
@
-
@
®
@
-
A
0
®
AeC
A
®
32
24
28
16
COUNTDOWN
COUNT UP
o
TOTAL
A
B
C
D
i
C
Ii
B
C
D
A
A
A
i
c
S
A
J
Ii
A
K
B
C
0
A
D
D
A
Ii
i
0
A
B
B
B
D
D
A
i
A
B
Figure A-1 Karnaugh Maps and Flip-Flop Excitation Functions for the CounterIShift-Register
June 1988
456
C
C
C
C
C
a
1
0
(J
a
1
0
{3
a
1
0
(J
a
1
Application Note
Signetics Application Specific Products
Introduction To Signetics Programmable Logic
AN8
Table A-5. PLS155 FPLS Programming Table for the Counter/Shift-Register
• F/FTYPE
E.-AIEA"A,
rHAArA:
AIAIAIA.l
AND
~ C
B(I)
alP)
M
3210765432103210
OoI.HI.HI.I\
----
POLARITY
II
T
w.mlI i rn~ ~.....:+o~L=+!H::+;L:.+!II!.J.!L:"+'~I'+!C~O~I~~'-+~~~~~'-I
I ~~
~
~
~~
.-
%~I
2 0 L H L H L
0 0 IN' til 3 0 LHLHLI'40LLHHL
5 oLLHHL
CUT-
~
~
L
LLL
1-1
OR
a(N)
P
321
0
-
0
B(O)
B A B A 7 6
5 4
3
o -
2
1 0
-
-
- 0
--A
o -
-
-
- 0
- 0
0 -
-
-
- A
- A
-A
H
n
i
S IF"
- -LEFT____
- - - SH F T - -
-
-
-
- H
H
-\1-- - H -
H -
-
-
~14~~0+LF+~L~H~I.i7L~~--pR~lr'~~--+-+-t~H+-+-+-u~
~
16
17
0
L L
0
H
\I I.
L
- - - -
L - INITI
L ZE -
-
-
-
-
-
-
H
H -
-
L
I.
H
-
A
A -
19
20
21
22
23
24
25
26
27
28
29
30
31
I. a
LA
07
06
~
00000000000000000
0
01000 00 0 0 000 0 00 00
00000000000000000
543219181312987617161514
A
c
p
rI
~
June 1988
457
A
-
A
-
A
- A
- A
- -L L
18 A
~----L------------
-
-
14 -
"
o----H-RES T-I. L
S TO P -
- A
H -
- H -
-
A
- A
0------
9 0 L II L I. L
100LHLLL
o~
110LHI.LL
2: ~_ 12 0 L L \I L I.
~ 2 13 0 L L \I I. I.
A
A
TT
"
A
Signetics Application Specific Products
Application Note
ANa
Introduction To Signetics Programmable logic
Table A-6. Modified PLS155 FPLS Programming Table for the Counter/Shift-Register With the Addition of a
Binary Multiplier
F/FTYPE
AlA 1.11.
T
~I ~
E ~~
~
E
R
M
C
0
0
0
··
·
·
~~ ·
lI:!
";0
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~
~
e.~
4
7
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QC
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e.
~ii'
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"'6 ~
~
.
0%..,11
a
!~~
oi$z
~
w
~
~oo
!:~~
~
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0
··
··
·
0
0
·
0
0
·
AND
8 I)
2 1 0 7 6
IL. H L. H
L H ~ H
I- /01 I- It j..
I- H l- N I- L L H H L
L I.. H,H L 3
... --
L.
ti,t/
L
I..
H,H
L. -
/I I.. L l- -
H L I. I. It L I- L
H l- I. II. I{ I. L I. I- H L L. lI- H I- L Il- I! l- I- L
L If I. I.. lI. I! L l L
-
-
l- N
I. I- I.
L t. I-
·
0
L. L.
0
L /.. H
0
L
L
I..
'-
fI
H
H
• If
IA
l
t.
L
L.
I.
-
l
II
-
4 3
1 0
3
2
----
L.. II
1/ I..
Ii H
/..
H
H L
II H
l-
1
-
IL
L
L L
L-
-
H
H
-
-
-
-
-
H
H -
N
II
II
II
3
2
-
0
II
0-
- - II
II
-
- -
-
-
7
6
II
-
II
-.it
Ii
fI -
II
II
-
-
H
- -
-
-
-IH
-
-
-
- -
31
Fe
-
I- -
-
-
-
-
-
-
JL"
LA
Itr7
0 000 0 0 0 0 0 000 0000
000 0 000000000000
0010100000000000000
0
0 0 0 0 0 0 0 0 0 0 0 0 0 (;) 0 t:>
00000000000000000
0
1 0• •
~
I D.
~
O2
0,
Do
-
-
543
June 1988
- - - l2 ~ ma
~
9
87617161514
458
1 0
-
A
- - -
A
A
A
A
--
-~
A
- -- - - --
A
A
A
A
A
- - -
2
A
A
A
A
- A
A
A
A
II
-
3
- AA
- ---
-
u
H
4
- A
f(
H
5
o -
-
I!
A
- o-
-
II
P
8 A 8
II II -
Ii
II
0
0
0
0-
-
1
80)
0-
-
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II -H
H -
-
- - - - - -L.
0
-~ H~
II L
II H
L H
II ~
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L.
ON)
OP)
2
H
-
POLARITY
OR
-
L
L
IIL
L
L It
0
5
l"a=AI"A ~
A IAIA IAI
IJ
-~
AN11
Signetics
PLD Programmable
Retriggerable One-Shot
Application Note
Application Specific Products
Author: David Wong
ments of the input to FF will give the correct
number of counts as counting from the input
down to 00.
FEATURES
• Programmable pulse-width/delay
• Maximum 256 clock cycles
• Asynchronous TRIGGER input
• Active-High and Active-Low outputs
• Asynchronous RESET
• 20-pin package
THEORY OF OPERATION
The one-shot consists of an FPLS PLS159
and an external clock which may be part of
the system in which this one-shot is to work.
As shown in Figure 1 and Table 1 the FPLS is
configured to have a latch and an eight-bit
binary up counter which is presettable by
input data to any number less than 256. Since
the input data is inverted before it is loaded
into the registers, counting from the com ple-
Pulse-width/delay inputs may be the outputs
of another device or switches. When /RESET
goes Low, flip-flops are set to all l' s (terms
PB and PAl. At the rising edge of the next
clock, data is latched into the registers (terms
LB and LA). When /TRIG goes Low, it is
latched into the input latch formed by term #
0, 1, 2 and 13. The output 0 1 of the latch
goes High and O 2 goes Low which enables
the 6-bit counting cycle. The 01 and /0 1 will
maintain their output levels until the end of
the counting cycle at which time the counter
reaches the count FF, resets the latch by
term # 13, and sets O 2 High. At the rising
edge of the next clock, terms LA and LB
cause data to be loaded again into the
registers, and the device is ready for another
/TRIG input. The output wave-forms are illustrated in Figure 2.
If the /TRIG pulse-width is longer than the
desired pulse-width of the one-shot, the device will react as mentioned above, and at the
end of the count cycle new data will be
loaded, another count cycle begins while the
outputs remain set by the /TRIG input without
changing throughout the change-over of one
count cycle to another. 0 1 ., on the other
hand, will go Low for one clock period at the
change-over. As long as the /TRIG is Low,
0 1• will continue to pulse Low for one clock
period at the change-over of one count cycle
to another. The output O 2 will pulse High for
one clock cycle at the change-over. Figure 2
illustrates output wave-forms for both cases.
Tbe output wave-forms are as illustrated in
Figure 2.
The one-shot is implemented by programming the PLS159 as shown in Table 1. The
logic representation of the program is shown
in Figure 3.
0,
TRIG
>-____~==~:>~---+--~=-------------~
0',
0,.
COUNT
F,
a.
F,
F,
a,
a,
a,
a,
a,
F.
a.
F,
INPUT
F,
F.
F,
SYSTEM elK
RESET
>----------------'
>-----------------Figure 1. Programmable Retrlggerable One-Shot
November 1966
459
0,
Signetics Application Specific Products
Application Note
PLD Programmable Retriggerable One-Shot
AN11
Table 1. PLS159 FPLS Program Table
PROGRAMMABLE RETRIGGERABLE ONE·SHOT
FF MODE
I
IAIAIAIAIA A
T
E
R
E.
REMARK
..
B(I)
-
3
L
2
1
-
0
3
2
1
7
••
4
3
1
7
0
t..ArtH
••
4
3
8(0)
2
1
0
H
H
• -
•-
11
-
2
1
0
•
A
·• ·
· ·
···• ··· ·• ··
··
•·
• ·
·
•
·• • ··• ··
· ·•
·
A
-
-
H
-
H
3
II
H
H
H-.l H
REMARK
Q{N)
2
L
(DR)
Q(P)
0
POLARITY
-.lL
AND
C
I
E.
A A
60
~
6',
II
A
-
1-\
1-\
1-\
H
k
H
-
H
\-i
H
~
1-\
H
H
-
COUNT Gyc..i...£
-
K
~
H
0
0
0
H H H
H H H H
"
0
0
H K H
0
H K It 1-\ H K
Ii H H \-i 1-\ H H
0
0-
12
H H
13
K H H Ii H H
A
LI\Tc.+i
14
,."
P,
17
18
"
20
21
22
23
2.
2.
26
27
28
29
30
31
2
Fe
3
p.
•
•
•
7
8
•
-
R.
L.
p.
SoT &~ 7])
L
H Ii H H H H f+ H UFtO
L
G1:L H L(i-Ij
D~ AT N6r::r
U::.
'56T Gl. TV 62. ~ ("(( G-H
R.
H H H 1+ H H H
L.
K
uA1> OArA IInlErr'-/(
03
0
D'
1
01
•
00
-
PIN
••
N
A
.. f?'"
s
E
'-
3
~
VI
~
'-
2
•
....--1r-- Q
}o--+--o
Figure L RS Latch
Do
10
80
8,
Figure 2. RS Latch
June 1988
464
Application Note
Signetics Application Specific Products
AN14
Latches and Flip-Flops With PLS153
Table 1. PLS153/153A Programming Table
POLARITY
CODE NO.
II I I I I I I LlL
T
AI ID
OR
E
B(O)
Bill
I
R
9 817 6 5 413 2 1 0 REMARKS 9 817 6 5 413 2 1 0
M 7 6 5 413 2 1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
09
08
07
06
05
04
03
02
01
- - -- - -- - - -:
. . .. .• .• .•
o
----- -- -- --- -:
- H
H
• •
••••
- H- - H
I
REMARKS
• A Gl-=/(1/..· is)
A • 1Ci=/(s.O,>
.
I
I
I
~
I
I
I
I
I
:
I
~
I
.
I
:
.
:
I
I
I
I
I
~
,
I
I
.:
:
~
- --- - - - - -- --- ----- ---- ----- - --- -
-~DO
PN 876 5 4 3 2 1 19 18117 1615 1413 1211 9
I
I
I
I
I
I
I
I
I
I
1.--: ......
II~_ e0
a:
c(
:il
June 1988
I
I I I I I I
I I I I I I
I I I I I I
1918 1716 1514 1312 11 9
II)
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a:
I I I I I I I I I
I I I I I I I I I
I I I I I I I I I
I
:
I I I I I I I
I I I I I I
I I I
I I I
I I I
I I I
I
I
I
I
I
:
,T'J'
I
I
I
I
I
I
I
I
9101
'81:)
'-'
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465
M
Lt)
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en
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Application Note
Signetics Application Specific Products
AN14
latches and Flip-Flops With PlS153
ANOTHER SIMPLE R-S LATCH
Another way to implement a simple latch is
shown in Figure 3, in which two NOR functions are cross-coupled to form a latch.
As with the previous example, we first define
the input and output pins. For this example,
we use 12 for the R input, 13 for the S input, 82
for the Q output, and 8 3 for the Q output. We
program 8 2 and 8 3 to have inverted outputs
by programming POLARITY of 82 and 8 3
Low, as shown in Table 2. Terms 6 and 7 are
ORad together by 8(0)2, rows 6 and 7. In the
same manner 8(Ola ORs Terms 8 and 9. The
programmed table of this design may be
represented as shown in Figure 4.
Since each AND-term of the PLS153 can
accommodate up to 18 inputs (true or inverting inputs of eight from 10 to 17 and ten from
80 to 89), and each OR circuit can be
connected to up to thirty-two AND-terms, we
can add additional features such as those
shown in Figure 5.
Figure 3. RS Latch
••
The programming of this design is left to the
reader as an exercise.
.,
Figure 4. RS Latch
.•
• ••
•• •
•
As---.....~
R
Q
·•• ·••
So
8,
Figure 5. RS Latch
June 1988
466
Application Note
Signetics Application Specific Products
AN14
Latches and Flip-Flops With PLS153
Table 2. PLS153/153A Programming Table
CODE NO.
June 1988
467
Signetics Application Specific Products
Application Note
latches and Flip-Flops With PlS153
AN14
O-LATCH
A simple D-Iatch can be constructed with an
PLS153 as shown in FigureS.
This circuit may be easily programmed into
the PLS153 as shown in Table 3. The program may, in turn, be represented as shown
in Figure 7.
IS
This circuit may be expanded to have multiple
D-Iatches using the same latch enable (LE).
I.
Figure 7_ D-Latch
Figure 6. 0 Latch
R-S FLIP-FLOP
Two R-S latches may be combined to form a
master-save flip-flop that is triggered at the
rising-edge of the clock (or the falling-edge of
the clock, if the designer so desires). Figure 8
shows a combination of two sets of crosscoupled NOR gates concatenated to form the
flip-flop. The implementation of this circuit
using PLS153 is as illustrated in Table 4 and
Figure 9.
s ----+---1
a
CK
Figure 8_ RS Flip-Flop
82
Q
8,
Q
~ -I::>-+--IL:J
CK
Figure 9_ RS Flip-Flop
June 1988
468
Application Note
Signetics Application SpeCific Products
AN14
Latches and Flip-Flops With PLS153
Table 3. PLS153/153A Programming Table
CODE NO.
M
LO
0r-
en
..J
a.
June 1988
469
Application Note
Signetics Application Specific Products
latches and Flip-Flops With PlS153
AN14
Table 4. PLS153/153A Programming Table
POLARITY
CODE NO.
T
~D
~
~
~I
I
M 7 6 5 4 3 2 1 0 9 817 6 5 413. 2
o - --- -
L -
lot -
-
- -
- -' -
-
1 - - - - - - - - - _.: - - - -' - 2
- - - -
3
- - - -! - \.. H -
- -
4'
5 - - 6 ___
7 - - 8 - - -
9
10
11
12
.13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
- -
- - - - -
- -
- - H - - -: _ - __ -~- - - - -! - H - - -
:
~
.
-' - -
8/0)
1 0 REMARKS 9 817 6 5 413 2 1 0 REMARKS
- - lie.. ~
• • • • • • • • • A /(~. e.J(. t ~~
H - &.
• ••• • • • • • ·IA
- H &0
• . : . • • • • • A • ~/(s. CI(. t a.. ')
- - - -'- - - -
l!.K'S
• . ' . • • .: .. • A •
-
"5
e,,·
•• :•••• '. A.·
A··
•
-
-
-
-' - II
-:- -
H
-
H
:
H eK· &.
- a..
St
• • :. • • •
•
.i. • • .iA • • • /(8,·/!.I(-tS.
...
,
• • :. • • • A • • •
:
, :
,
·,
··
.
~/(a.. ~ t S'
•
·•
·
··
:
:
:•
:
·
i
:
30
31
09
08
07
06
05
I ITITI I
II I
I I
I I I I I
I I I I I
I I I I
I I I I
I I I I
I I II
I I I I I I I I I
i
04
I I II I I I I I I I
I I I I I I I I I I I
01------------------
I
DO - - - - - - - - - - - - - - - - - -
<
w
a:
June 1988
. .
11
I
I
I
I
I
I
I
I
I
C"')
Lt)
,..
en
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a..
toto
II
I
19 18 17 16 15 14 13 12 11 9
PN 8 7 6 5 4 3 2 1 19 1817 16 15 14 13 12 11 9
en
:E
I
I
I
I
I
11111111111
03 - - - -: - - - - - - - - - - - - - 02-------- ----------
::.::
a:
I
I
I
I
I
....
0
ell<1 '" '"
470
Signetics Application Specific Products
Application Note
Latches and Flip-Flops With PLS153
D FLIP-FLOP
An edge-triggered master-slave D flip-flop
may be constructed with two D-Iatches In the
manner shown in Figure 10.
AN14
An PLS153 may be programmed as shown in
Figure 11 to implement the D flip-flop which is
equivalent to the circuit shown in Table 5 in
the PLS153 logic representation.
Figure 10. 0 Flip-Flop
.
OK
Figure 11. 0 Flip-Flop
~------------------------------------------~~----------------------------------~
June 1988
471
Application Note
Signetics Application Specific Products
AN14
Latches and Flip-Flops With PLS153
Table 5. PLS153/153A Programming Table
C")
It)
,....
en
..J
Q.
June 1988
472
Signetics Application Specific Products
Application Note
Latches and Flip-Flops With PLS153
AN14
APPENDIX A
"
"
"
"
"
"
"
'.
'"
'"
B,
B,
B,
B,
B,
B.
B,
B,
B,
Bo
31 . . . . . . . 24
23 ..... • • • 16
15 ..........
a
7 ........... 0
NOTES:
1 All programmed "AND" gate locations are pulled to logic "1"
2. All programmed "OR" gate locations are pulled to logic "0"
3. :iN Programmable connection
Figure A-1. FPLA Logic Diagram
June 1988
473
Application Note
Signetics Application Specific Products
latches and Flip-Flops With PlS153
AN14
Appendix B. PLS153/153A Programming Table
POLARITY
CODE NO.
rllH HIHILILILIHIHlrI
T
OR
AI
~~--~I----~~--~B~I)~--~
~~
M 76 5 413 2 1 0 9 817 6 5 413 2 1 0 REMARKS 9 8-r7 6 5 4 3 2 1 0 REMARKS
o Ii ... H H - - - - - - - - - A·a·(!.·J) A.: • • A • • • • • 1~)(::A·~·I!·l>
-:, - -
:
2
3
~
41.I.LL-----
,
,
:
----
:
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
:
•
i
•
• •
• •
·.
:
,
,
i
:
;
:
i
:
i
i
:
:
30
:
,
31
D9
08
07
06
05
04
03
• •
:
5
6
7
8
9 - H L -: - - - - - - - - - - - - 10 - H - L - - - - - -:- - - • - - - 11 - - L L - - - - - - ~- - - - - - - -
:
- - - - - - - - - - - - - - - - - - - - - - - - - - -:- - - - - - - - - - - - - - - - - - - - - - - - -
I ITITI I I I I I I I
I I i II I I I I I I I
- - - - - - - - - - - - - • - - -
11111111111
I I I I I I I II I I
- - -
02
01
DO
- - - - - - - -
I
- -:- -'.
I
I I I
I I
I I
I I
11111111111
I I II I I I II I I
I I I I I I I I I I I
!
!
I
PN 8 7 6 5 4 3 2 1 1918~7 16 1514 1312 11 9
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19 18 1716 15 14 13 12 11 9
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(W)
Lt')
..-
tJ)
..J
c..
June 1988
474
Signetics Application Specific Products
Application Note
,",atches and Flip-Flops With PlS153
AN14
APPENDIX C
R-S LATCH (Cross-Coupled NuRj
See Figures 3 and 4 and Table 2
R~S
LATCH (Cross-Coupled NAND)
See Figures 1 and 2 and Table 1
SPIN 1
R Pin 3
R PIN 2
SPIN 4
Q PIN 12
Q PIN 9
Q PIN 13
Q PIN 11
D-LATCH
See Figures 6 and 7 and Table 3
Typical set-up time e; Ons
Typical hold time e; 0 - 5ns
Typical propagation delay e; 20ns
D PIN 6
LE PIN 7
Q PIN 14
EDGE-TRIGGERED R-S Flip-Flop
See Figures 8 and 9 and Table 4
EDGE-TRIGGERED D Flip-FlopSee Figures 10 and 11 and Table 5
R PIN 1
o PIN
SPin 2
CLOCK PIN 5
4
CLOCK PIN 3
Q PIN 15
Q PIN 13
NOTE: Timing requirements/performances are the
same as the R·S latches
NOTE: Timing requirements/performances are the
same as the O-Iatch
Figure C-l. Timing Photos
June 1988
475
Signefics
AN15
PLS159 Primer
Application Note
Application Specific Products
INTRODUCTION
The PLS159 is a field programmable logic
sequencer which consists of four dedicated
inputs, four bidirectional I/O's, eight flip-flops,
thirty two 16-input AND gates, twenty 32-input
OR gates, and a complement array. Each flipflop has a bidirectional I/O and may be
individually programmed as J-K or D flip-flop,
or switch between the two types dynamically.
The flip-flops will accept data from the internal logic array or from the bidirectional I/O, or
they may be set or reset asynchronously from
the AND array. The output polarity of the four
bidirectional I/O's are programmable and the
direction is controlled by the AND array.
Figure 1 is the logic diagram of PLSI59.
PROGRAMMING THE PLS159
The programming table IS shown in Table 1
where there is a place for everything that is
June 1988
shown in Figure 1. The program table is
basically divided into two main sections. The
left hand side of the table, section A, represents the input side of the AND gates, while
the right hand side, section B, represents the
OR gates sections which includes the flipflops and the combinatorial outputs B(O) to
B(3). The flip-flops modes are defined in
section C and the output polarities of the
combinatorial outputs are defined in section
E. The programming symbols are detailed in
Figure 2.
As shown in Table 1, the programming table
is very similar to a truth table. Each column in
section A represents an input to the 32 AND
gates, and each row represents an AND gate
connecting to 17 inputs. Columns 10 to 13
represent the 4 dedicated inputs, 10 to 13 .
Columns B(I)o to B(lb represent the inputs of
the 4 bidirectional I/O, Bo to B3. Columns
476
O(P)o to O(P!? represent the feedback, Fo to
F l , from the flip-flops (the present state).
Column "C" represents the complement array.
As shown in Figure 1, the outputs of the AND
gates are connected to an array of OR gates
which, in turn, are connected to either flipw
flops or output circuits. Columns O(N)o to
O(N!? represent the next state which the flipflops will be in. Columns B(O)o to B(Ob
represent the combinatorial outputs Bo to B3.
Each row represents an AND gate with 17
inputs each of which may be true and/or
complement and is, therefore, a perfect decoder. Referring to the programming symbols
In Figure 2, to implement the equation
z
~
A • B • C • D,
all one has to do is to enter one line as shown
in Table 2, term-a.
Signetics Application Specific Products
Application Note
PlS159 Primer
AN15
I
r-
"
"
"
"
B,
B,
Q~---r------------------~~~14WF,
jt---+-------------------~~--rfiilF,
Qr---r--------------------~~~'2IF,
CK~CK
NOTES,
1. All OR gate inputs with a blown link float to logic "0".
2. All other gates and control inputs with a blown link float to logic "1".
3 .. " denotes WIRE-OR.
Figure 1. FPLS Logic Diagram
June 1988
471
Signetics Application Specific Products
Application Note
PlS159 Primer
AN15
Table 1. FPLS Program Table
CODE N0'5
FenoN
T
E
R
M
I
C 3 2 1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Fe
PS
RS
LB
PA
RA
LA
03
02
01
DO
PIN
c { .1L
FF MODE
I I
AND
S I)
o
3 2 1
o
~SEC1",/)N ,.
(OR)
Q(P)
7 6 5 4
~'r-
Q(N)
REMARKS
765 4
3 2 1 0
B(O)
3 2 1 0
o
3 2 1
-
J
POLARITY:
SEcTIoN D
REMARKS
~~
.
~..P
e:;<,.,0
"Q
C
V:J~
I
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5 4 3 2 9 8 7 6 1918 1716 1514 1312
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1918 1716 1514 13 12 9 8 7 6
en
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II)
....
en
...I
"..:cr
~
w
Q.
cr
June 1988
EA
ES
I
478
Application Note
Signetics Application Specific Products
PLS159 Primer
AN15
The FPLS calt be programmed by means
of LogiC Programming equipment.
With Logic programming, the AND/OR-EXOR input connections necessary to imple-
men! the desired logir. function are coded
directly from the State Diagram using the
Program Tables on the following pages.
In these Tables, the logic state or action of
all I/O, control, and state variables is assigned a symbol which results in the proper
fUSing pattern of corresponding links defined as follows:
1" 1'" 1'" 1'"
1,8.0
i,
(T.
I
fe.
B. a
I, B,
a
I, Ii,
L, P, R, O)n
I, B,O
a
___
1,8,0
CODE
INACTIVE 1,2
I o I
I
Ic:' I
STATE
I, B.a
Looooeos
~
I
(T, Fe_ L. P. R. DIn
IC~'I
STATE
1.8, a
CODE
STATE
I
I - I
DON'T CARE
LOOO1'OS
LDOO100S
LDOOO90S
__
I. B,a
(T. Fe_ L. P. R. Oln
(T, Fe_ L. P. R. DIn
STATE
I, 8,0
"AND" ARRAY-(l), (B), (Qp)
0: 0: 0: 0:
I
INACTIVE 1,3,5
I
GOOE
0
(In_ Fe)
(Tn' Fe)
(Tn· Fel
ACTION
I
ACTION
I
ACTION
CODE
GENERATES
LDOO120S
I
A
I
I
(T n' Fe)
CODE
ACTION
I • I
PROPAGATE
LOOO130S
I
TRANSPARENT
CODE
I - I
lOOO150S
LDOO140S
"COMPLEMENT" ARRAY -(C)
cr cr
(On Ln Pn Rn)
ACTION
I
PROPAGATE
Fe
~. ~.
(On In Pn Rnl
CODe
I • I
Fe
I
ACTION
CODE
TRANSPARENT
I - I
I
ACTION
I
icd~"'T~Ol~ED)
I
LDO{l170S
LDOQ160S
COOE
A
I
I
ACTION
J·K
lDOOl80S
"COMPLEMENT" ARRAY (cont.)
"OR" ARRAY-(MODE)
,---------------,---------------,
a
a
"OR" ARRAY-(QN=D-Type)
Figure 2
June 1988
I
479
I I
CO.DE
LDOO190S
Signetics Application Specific Products
Application Note
PLS159 Primer
AN15
a
ACTION
CODE
ACTION
SET
H
HOLD
"OR" ARRAY - (On
+r>I
+r>-
p, R, 5
(OR B)
Tn STATUS
CODE
ACTIVE
I A I
Tn STATUS
I
=J-K Type)
s7Do- S-rC>o--B
B
P. R. S
(OA B)
-=-
I
lOW
CODE
I
I
l
I
POLARITY
I
HIGH
1.0002805
lOOO27QS
LDOO260S
--=
POLARITY
CODE
I • I
INACTIVE
I
C~DE
I CODEI
I
H
I
lOOO2g0S
"EX-OR" ARRAY-(B)
"OR" ARRAY - (5 or B), (Pl, (R)
~~ ~~ o.~ ~~
En
I
ACTION
CODE
IDlE4
I o I
LDOO300S
En
En
L
I
ACTION
CONTROL
1 CODE J
I
A
l
I
I
ACTION
ENABLE4
lDOO310S
En
LCOOEJ
I • I
I
ACTION
CODE
DISABLE
I - I
1000320'3
"OE" ARRAY-(E)
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates.
2. Any gate (T, Fe, L, P, R, D)n will be unconditionally inhibited if anyone of the I, S, or Q link pairs is left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn, Fe.
4. En = 0 and En = • are logically equivalent states, since both cause Fn outputs to be unconditionally enabled.
5. These states are not allowed for control gates (L, P, R, D)n due to their lack of "OR" array links.
Figure 2 (continued)
June 1988
480
Ll)OO330S
Signetlcs Application Specific Products
Application Note
PLS159 Primer
AN15
Table 2. FPLS Program Table
I
I
CODENa.
T
E
R
M
C
0
1
2
3
4
5
6
FF MODE
I
AND
B I)
I
3 2 1 0 3 2 1 0
-
H
-
Lft L - -
alP)
7 6 5 4
8
9 10 11
12
13
14
(.j L -
- -
--
- - - - - - - - --
- - - - -
- - - -
- - j.( L- -
H1H11-I
JH
-
-
-
- - -
- - - - -
ON
REMARKS
3 2 1 0
-
- -
- - -
-
··
- - - - ··
- /Afd$,/C
- -
-
- - - - --- -
'tI.\fl
3 2 1 0
- - - - - - -
A".Bf("P -
-
- -- - -- - - - - -
• A 2-MS..c ... D
A • T,/Ao·S;tIC
··
· ··
· .• ·•
• A
'/.. I
AA ~
DO 00 00 boA-A
f - - -- - - - -A
- A1
a:
D:/Atio/(3¥JC.
A
T:Q,"'Q.
03
02
01
DO
lE
~:A"'IC
A
-
- - 10
- 00- -
RB
LB
PA
RA
LA
PIN
+/6*/£
L
-
--
31
- - --
J=AjI(C
.. .- .. - .... ..
-
/A;f..IBttIC
REMARKS
BO
3 2 1 0
- - - - - - - H
- - - - -- - H
- - - - --
FC
PB
1 1 1
-
-
- - - - - - - - - - - -- -
POLA RITY
•
(OR)
_9N
- - - - A*C
- - - - 16*/,;.
-
-
EA
7 6 5 4 3 2 1 0
3 2 1 0 3 2 1 0 7 6 5 4 3 2 1 0
0 - H- H-- 1 - - L- L- 2
L
3
fI
4
5
l L L 6 - -H 7
8 - L L 1....- - 9 - - - - ff
10
11 - - - - - 12 - - - - - -13 - -- - 14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
-
EB
IA
I-I' 01
Q.
A B C.D
484
Signetics Application Specific Products
Application Note
PLS159 Primer
AN15
A D flip-flop may be implemented by first
entering an "A" in FIF MODE. Then enter
"0" in the row Fe, which will unconditionally
enable the tri-state inverter between the J
and K inputs. The following logic equation
may be implemented as shown in Table 4,
term 5
rY'""\
00
01' D = IA • IB • IC + E.
Notice that the entries in term 5, columns
O(N)e to 7 are "A" and "." instead of "H"
and "L" as in the case of J/K flip-flops. The
entry "A" will cause the fuse connecting to
the "K" input to be disconnected and the "J"
fuse to be intact. Whereas the entry"." will
cause both fuses to be disconnected. This
feature enables the user to quickly recognize
the mode in which the flip-flops are operating
without having to go through the control
terms. Some commercially available device
programmers in the market may not have the
software capability to implement this feature,
in which case an "H" and a "-" may be used
in place of "A" and "." respectively as shown
in Table 4, terms 8 and 9.
Of course, the term Fc may have inputs
instead of zeros and dashes, in which case
the flip-flop modes are controlled dynamically.
When both the J and K inputs are "1' s", the
flip-flop will toggle. A simple 3-bit counter may
be implemented using only AND terms as
shown in Table 4 terms 11, 12 and 13. The
logic equations for the three flip-flops are as
the following:
(05 toggles unconditionally)
°5: T =1;
(06 toggles when 05 = 1)
06: T =05;
07: T=05'06: (0 7 toggles when 05 •
0 6 = 1)
The above equations represent an octal upcounter. However, since the outputs of the
flip-flops are inverted, the counting sequence
of the outputs is that of a down-counter.
The flip-flops may be asynchronously set and
reset by the Control AND terms PA/PB and
June 1988
C'/D:X
Figure 3
RAIRB respectively. As shown in Figure 1,
PA and RA controls flip-flops Fe to F3, while
PB and RB control F4 to F7·
In order to save the number of input pins, the
eight flip-flops may be synchronously loaded
directly from their own output pins. To use
this feature, EA andlor EB must be programmed "A" or "-" so that the output
buffers may be disabled before loading. As
shown in Figure 1, every flip-flop has an ORI
NOR gate the input of which is directly
connected to the output pin and the outputs
of the OR/NOR are connected to the K and J
inputs respectively. This OR/NOR gate inverts the input and feeds it to the flip-flop in a
"wire-OR" fashion. Therefore, when loading
data directly into the flip-flops from the output
pins, caution must be exercised to insure that
the inputs from the OR array does not interfere with the data being loaded. For example,
if the data being loaded is a "1 " on the output
485
pin, the J input will be a "0" and the K input
will be a "1". If, at the same time, a "1" is
present at the J-input from the OR array, the
flip-flop will see" l' s" in both J and K inputs.
It will toggle as a result. The OR/NOR gates
are enabled by the Control AND terms LA
and LB. LA controls flip-flops Fo to F3 and LB
controls F4 to F7.
All Control AND terms function and are programmed in the same manner as the other
AND terms. The only difference is that the
Control AND terms are not connected to the
OR array.
The outputs of the flip-flops may be fed back
into the AND array as the present state, O(P).
The output of the AND array into the OR array
and the inputs to the flip-flops is the nex1
state, Q(N). As an example, Figure 3 is a
state machine implemented in a PLS159 as
shown in Table 5, terms 0 to 6.
Application Note
Signetics Application Specific Products
PLS159 Primer
AN15
Table 5. FPLS Program Table
I
CODE NO.
IT
FFMOOE
o.
AND
~
H HIHII-/
(OR)
I
S(I)
Q(P)
M C 3210321076543210
O_H~ _ _ _ _ _ _ L L L L L L L L
REMARKSI-=-I"'::"1-::'T..;:QTN=:)"""'''''''''~-::T;S;'::(0:T::-i
--11
L . - - - - LLLL.L.LH
REMARKS
765432103210
LLLLL.LLH.··A
1 ---HL---_LLLLLLLfi
2 - - - - - - - - - L L . L . H LL.Lff
3
4 -lfL------LLLL.LLLL
5 - --fi - - - -- L L L L L L H L
6 7
POLARITY
ES
-1-1-1- .1'
LLL.HLLL.ff.A • •
LLj.j LH LH LA
·A
A
•
ILLLLL.L.lilILLLLLLLi-i
L L LL LL L H
L
•
A A
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FC
PB
RB
LB
PA
RA
LA
03
02
01
DO
PIN
'"'"a:
:E
'"
w
a:
June 1988
I-
-
1
,-~,
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191817161514 13 12 9 8 7 6
5 4 3 2 9 8 7 6 1918 1716 1514 1312
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tJ)
AB CO
W'l. yz
486
..J
0.
Signetics
AN18
Schmitt Trigger Using PLS153
and PLS159
Application Note
Application Specific Products
INTRODUCTION
One of the many features of the PLS 153 to
159 series is the availability of individually
controlled Tri-state 110 pins. Taking advantage of this feature, a Schmitt trigger may be
constructed using one input pin, two bidirectional 110 pins and additional components of
three resistors. The two threshold voltages,
as well as the hysterisis, are determined by
the values of the three resistors and the
parameters of the PLS153/159 device, which
are 1) input threshold voltage, VTH, 2) High
output voltage, VOH, and 3) Low output voltage, VOL. The circuit may be simplified if
Schmitt function is needed only on Low going
High or High going Low, and if the hysterisis
and threshold voltages are not important.
DESCRIPTION
A simplified block diagram of a non-inverting
Schmitt trigger is shown in Figure 1 where R"
R2, and R" R3, form two pairs of voltage
dividers one of which get into action at input
voltage direction of High going Low and the
other Low going High. Assuming that input
voltage starts at zero volt, the output voltage
is therefore at VOL which causes O2 to pull R3
towards ground. As the input voltage increases, only a fraction of the voltage is
impressed upon the input buffer due to the
dividing network R, and R3. As soon as the
input voltage reaches a point where V, = VTH
(VTH = 1.38V typical), the output switches to
VOH which, in turn, turns off O2 and turns on
0,. V, will jump to a value greater than VTH
and 0, then pulls the input pin, through R2,
towards VOH, which in turn locks the output to
a High state even if the input voltage fluctuates, as long as it does not fluctuate outside
of the designed hysterisis. When the input
voltage goes from a High to a Low, the
Schmitt function repeats itself except that 0,
and 02 reverse their roles.
The triggering voltages, VH (Low going High)
and VL (High going Low) are:
VH = VTH [(R, + R3)/R3J - VOL (R,/R3);
VL = VTH [(R, + R2)/R 2J - VO H (R,/R2);
where, at room temperature, Vee = 5.0V,
IOH/lOL < 1rnA. VTH is the threshold voltage
of the device, typically 1.38V; VOL is the
output Low voltage of the device, typically
O.36V at IloL I < 1rnA; VOH is the output
High voltage of the device, typically 3.8V at
IIOH I < 1mA.
The implementation of Figure 1 using
PLS153/153A is as shown in Table 1, and
Figure 2a. A scope photo of the operation of
the circuit is shown in the Appendix. The
implementation using PLS 159 is shown in
Table 2 and Figure 2b. In Tables 1 & 2, V, is
the input pin, Vo is the output pin, V2 is the
output which pulls down V, and V3 is the
output pin that pulls up V,. The Schmitt
output is available at pin 80 for external use,
and is available internally at the input buffers
of 10 and 8(1)0. However, there is a propagation delay between the two signals from the 10
buffer and the 8(1)0 buffer.
An inverting Schmitt triggered buffer may be
constructed using the same principle. A simple block diagram of such inverter is shown in
Figure 3a. The circuit is implemented using
H/L programming table as shown in Table 3
for PLS153 and Table 4 for PLS159. Table 3
is also represented in logic symbols in Figure
3b. If the voltage levels (VL and VH) and the
hysterisis are not critical, one 110 pin may be
used to pull the input pin High and Low.
Therefore one 110 pin and a resistor may be
saved. The drawback is that the range of VH
and VL is quite limited. The circuit is as shown
in Figure 4.
If Schmitt function is needed only in one
direction, one of the resistor I output circuit
may be eliminated. The circuit is as shown in
Figure 5.
+Vcc
....
a, ......
.A
......
II,
II,
INPUT
v,
.....
.....
OUTPUT
Ra
"
J
S
oj>
II
.A
.......
V,N
BOO17()!)~
Figure 1. Simplified Block Diagram of a Schmitt Trigger
June 1988
487
!
i··
I
Signetics Application Specific Products
Application Note
Schmitt Trigger Using PLS153 and PLS159
AN18
Table I. PLS153/153A Programming Table
CODE NO.
POLARITY
I I I ILIMI hlhllM
i
OR
AI
~~
I
15(0
M 765 413 2 1 0 9 817 6 5 413 2 1 0 REMARKS 9 8 76 5 4132 1 0 REMARKS
o - - - -;- - - H - - - - - -i- - - ~
• • A 1ItII-1Nr"-~
~
1 00 00;00 0 0 000 0 00:0 0 010
2 - - - -:- - - - - - - -~- - - 3
4
: :
: :
5
6 oooo!oooooooooo.oooo
7
;
~:
8
9
•
i
:!
:
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
:
•
' :
AA
i
1I!lUI$ t .....
i
a(o).f.
:
i
.:
::
.
:
I
i
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:
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:
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:
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D4
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~
:
,
I
I I I I I I I
II I II I I I I I I
I I I I I I I I I I I
11111111111
I I I I I I I I I I I
I II I II I I I I I
I I II I I I I I I I
I I I I I I I I I I I
I
D7
D6
OS
:
··
,T'J'
i
D8
:
·•
:
29
30
31
D9
•
.!.
- - -i- - - - - - - H
D1 - - - -,- - - - - -i· - - -i- L
00
--!--------- ----
I
~8]654321~187~~W~12119
I
I I
I I
I
I I
I
1918171615141312119
NOTE:
Schmitt trigger output may be obtained from both 10 and 8(1)0 to drive the AND-ARRAY.
June 1988
.
i
:.:-=-
:
·
.!
:
.IA. OIJrPIn"V...
IA • • /IlJTPIIr If....
488
I
v..
Signetics Application Specific Products
Application Note
Schmitt Trigger Using PLS153 and PLS159
INPUT
PLS1531153A
TO OTHER AND TERMS
a. Using PLS153/153A
b. Using PLS159
Figure 2. Schmitt Trigger
June 1988
489
AN18
Application Note
Signetics Application Specific Products
Schmitt Trigger Using PLS153 and PLS159
AN18
Table 2. PLS159 FPLS Programming Table
I
FFMOOE
I I I I I \I I
CODE NO.
EB
I POLARITY
EA
I
I IMIHIH
AND
. (OR}
~ C
I
B I)
QP)
REMARKS~~~Q~·~~~~~~BO~~
M
3210321076543210
765432103210
T
0----"-----------1
2
- - - - - - - -
0 0 0 0 0 0 ., 0 0 0 0 0 «>:0 I 0 «> 0
• • • A ""·IN'I·IIIFR
- - - - - - - - •• A.
-
- - - - - -
REMARKS
-
0CITM"\f0l.
• A • • ',,",,",VoM
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26·
27
28
29
30
31
Fe
PB
I
,-I"""
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
I
I
PA
---
I
I
I
LA
I
I
I
I
I
03
02
01
I
I
I
I
RA
I I I I
I
I
I
LB
RB
I
I
I
I
H-
I
I
I
I
L.-
I
I
I
I
I
I
, -,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DO
PIN
5 4 3 2 9 8 7 6 19181716 15141312
1918 1716 1514 1312 9 876
I
0)
it)
Ui
-I
>
0..
June 1988
490
Signetics Application Specific Products
Application Note
AN18
Schmitt Trigger Using PLS153 and PLS159
+vcc
INPUT
---"'vv-+-----e><>---+--- OUTPUT
a. Simplified Block Diagram
PLS159
INPUT
10 OTHER AND TERMS
b. Using PLS159
Figure 3. Inverting Schmitt Trigger
June 1988
491
LL
S/gnetics Application Specific Products
Application Note
Schmitt Trigger Using PLS153 and PLS159
AN18
Table 3. PLS153/153A Programming Table
POLARITY
CODE NO.
I I I I I I ILILIL
AI D
i
OR
I
~
~~
M 7 6 5 413 2 1 0 9 817 6 5 4 3 2 1 0 REMARKS 9 817 6 5 4 3 2 1 0
- ~ - - - - - It - - ! - - - - - - - 1 000000000000000000
2
3
--
4
5
6
7
8
9
10
- - - - - -!- - - - i - !:
:!
:
,
:
:
!
:
:
:
i
11
12
13
:
:
:
:
14
15
:
17
18
19
20
:,
21
22
23
24
25
26
27
0
i !
i:
:
i
i
:
:
:
:
i
:
:
:
:,
:
:
:
:
i
:
:
i
:
,
:
:
:
:
:,
:
i
i
,
,
28
,
29
30
31
D9
D8
D7
i
i
:
i
i
:
:
:
i
:
i
I ITITI I I I I I I I
I "I I I I I I I I
D6
D5
I
I
i
- - - -
- - - - - ~ - -
- - - -
-'-
_
It
I
I
- - -
-!- L
-!- - ~81654321~18U18~14~12119
June 1988
I I I I I
I I I I
I I I I I I I II I I
IIlIlIrllll
I I II I I I II I I
:
D2 - - - -
I
11111111111
D4
D3
D1
DO
- -
:
:
REMARKS
: ! •• lit. lIN. aUF,..,ll
: . oAoO/lTPUrV...
: ! A. 0IIf1VF' 'IN::
:
i
:!
o
I
I
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I I I I I
I I I I
I I I I
191817161514131211 9
492
Signetics Application Specific Products
Application Note
Schmitt Trigger Using PlS153 and PlS159
AN18
Table 4. PLS159 FPLS Program Table
I
I
COOENO.
I I I I
I
I
Es
FFMOOE
I
,
IPOLARITY
I If.! wi\..
EA
AND
(OR)
Q(P)
I
ON)
80)
REMARKS
REMARKS
BII
C
II
3 2 1 0 3 2 1 0 7 6 5 4 321 0
7 6 5 4 3 2 1 0 3 2 1 0
0
• A my. BUFFER.
III
__ 0
1 0 o 0 00 o 0 o 0 DO o 0 DO o 0
• A • OIITNr'V...
2
A
° DI1I'III1r VO..
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
T
E
R
- - - - -- -- - - - - -- - - - - - - - -- - - -- - - - --
Fe
I
,- r-
PB
I
I
I
I
I
I
I
I
I
I
I
I
I
RB
LB
PA
RA
LA
03
02 01
- - - -- L. - -- - - - - '" - - - - 00- - - - -- -- -5 4 3 2 9 8 7 6 1918 1716 1514 1312
PIN
~
:Ill
->
I
I
I
I
I
I
I
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I
I
I
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,- -,
I I I I
I
I
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I
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I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I
0')
Il)
,...
en
...J
~-:~
Q.
w
a:
June 1988
I
I
I
.
1918 1716 1514 1312 9 8 7 6
til
a:
c(
..
-- -- -- - - - -- - - -- - -- --
493
Application Note
Signetics Application Specific Products
Schmitt Trigger Using PlS153 and PlS159
AN18
INPIIT~OIlTPIIT
4-J
VL =O.78V, VH =1.6V
Figure 4. Schmitt Trigger Using One I/O Pin
a. High Going Low Direction
INPUT~OUTPIIT
~
b. Low Going High Direction
Figure 5. Schmitt Trigger
APPENDIX A
r)utput
Input
NOTE:
R1 = 3.9kS}, R2 = 10.Bkrl, R3 = 2.0kSl, Vee = 5.0V, Ambient temperature
~
25°C
Figure A·1. A Non·lnverting Schmitt Triggered Buffer
June 1988
494
Signetics
AN21
9-Bit Parity Generator/Checker
With 825153/ 153A
Application Note
Application Specific Products
INTRODUCTION
This application note presents the design of a
panty generator using Signetics PLD, 82S153
or 82S153A, which enables the designers to
customize their circuits in the form of "sumat-products". The PLA architecture and the
lObi-directional 110's make it possible to
implement the 9-bit parity generatorlchecker
in one chip without any external wiring between pins. A logic diagram of the device ;s
shown in Appendix A.
The panty at an 8-bit word is generated by
counting the number at "1' s" in the word. It
the number is odd, the word has odd parity. It
the number is even, the word has even parity.
Thus, a parity generator designed tor even
parity, tor example, will generate a "0" it the
parity is even, or a "1" If parity is odd.
Conversely, an odd parity generator will generate a "0" if the parity at the word is odd, or
a "1" it the parity is even. This bit is then
concatinated to the word making it 9-blts
June 1988
long. When the word is used elsewhere, its
parity may be checked for correctness.
FEATURES
• Generates even and odd parities
(SUM E and SUMo)
• SUME = "1" for even parity, "0" for
odd parity
• SUMo = "1" for odd parity, "0" for
even parity
• Generate parity or check for parity
errors
• Cascaded to expand word length
DESCRIPTION
The most straight torward way of implementIng the parity generator I checker is to take the
9-input truth table (8 inputs tor the 8-bit word,
and 1 input for cascading the previous stage)
and put it in a 256 X 4 PROM. Since there
are 2 9 combinations and halt at them is odd,
495
the other halt is even, the circuit will take 256
terms. An alternative is to divide the 9-bits
into 3 groups at 3-bits as shown in Figure 1. It
the sum at the 3-bits is odd, then the intermediate output SUI, or SU2, or SU3 equals 1.
Otherwise it equals O. The intermediate results are grouped together and SUMo becomes "1" it the sum is odd, otherwise
SUMo equals "0". The circuit is implemented
using AMAZE as shown in Figure 3. SU 1 is an
intermediate output for inputs 10, I, and 12, In
the same manner, SU2 and SU3 are intermediate outputs for 13, 14, Is and 16, 17, Is. The
design uses up 16 product terms and 5
control terms leaving 16 product terms and 4
bi-directional 110's to implement other logic
designs.
The design is tested by using the logic
simulator provided by AMAZE. The input test
vector is chosen to exhaustively test tor all 8
input combinations at all 4 sections at the
circuit.
Application Note
Signetics Application Specific Products
AN21
9-Bit Parity Generator/Checker With 82S153/153A
10-
~
1112-
-
13SU2
14-
SUMo
-
15-
SUMe
16-
~
1718-
80016705
10
I,
12
SUl
13
14
Is
SU2
16
17
18
SU3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
1
1
SUl
SU2
sua
SUMo
SUMe
0
0
0
0
0
1
0
1
0
1
0
1
0
1
a
a
1
1
0
0
1
1
a
1
1
1
1
0
0
1
--1
0
1
0
1
1
0
1
a
1
0
0
1
Figure 1. Block Diagram of 9-Bil Parity Generator/Checker
******************** PARGEN ********************
#####################
LABEL
10
11
12
13
14
15
16
17
18
GND
P I N
L I S T
**
**
1
OV
**
9-:
** 10-:
FNC **
LABEL
+5V **VCC
10
**SUME
** 0
:-18
**SUMO
**
:-17
** BB **N/C
:-16
**N/C
**
:-15
** BB **N/C
:-14
**N/C
**
:-13
**SU3
** 0
:-12 ** 0
**SU2
:-11 ** 0
**SUI
:-19
8
2
s
1
5
-'
---------
Figure 2. Pin List
June 1988
#####################
PIN**
---------:-20
** FNC **PIN
** I
** 1-:
** I
** 2-1
** 1
** 3-\
** 1
** 4-:
5-:
** 1
** 6-:
** I
**
** 1
** 7-:
** 1
** 8-:
496
**
TBOO590S
Signetics Application Specific Products
Application Note
9-Bit Parity Generator/Checker With 82S153/153A
********************
********************
PARGEN
@DEVICE TYPE
825153
@ORAWING
******************************* PARITY GENERATOR/CHECKER
@REVISION
*******************************
REV. -
@DATE
******************************* xx/xx/xxxx
@SVMBOL
******************************* FILE 1D: PARGEN
@COMPANY
******************************* SIGNETICS
@NAME
@DESCRIPTION
*********************************************************************
This circuit is a 9-bit parity generator/checker commonly used
for error detection in high speed data transmission/retrieval.
The odd parity output (SUMO) is high when the sum of the data
bits is odd. Otherwise it is low.
The even parity output (SUME) is high when the sum of the data
bits is even. It is low otherwise.
*
*********************************************************************
@COMMON PRODUCT TERM
@I/O DIRECTION
*********************************************************************
SU1, SU2 and SU3 are outputs which are defined in the PIN LIST
and therefoFe they don't need to be defined here again.
*********************~***********************************************
@OUTPUT POLARITY
~********************************************************************
The output polarit'ies of
PIN LIST.
different OLttPLtts are defined in the
They don't have to be defined again hen~.
*********************************************************************
@LOGIC EQUATION
*******iI·**.;!·**********~·**ii·********************************************
*
SU1, SU2, and SU3 are intermediate terms
**********iI'**********************************************************
TRUTH TABLE
INPUTS
12
SU2
17
14
11
0
(I
0
0
SU3
18
15
OUTPUTS
SUI
16
I3
SUMO
SU3
SU2
SUI
10
0
SUME == ISUMO
0
o
(>
o
0
0
0
0
0
0
I)
I
(I
0
(I
o
I
SUI
112
SU2
12
115
15
=
SU3
SUMO
118
18
*
*
*
*
III
111
114
114
"
"
117
117
15U1
SUI
SUME
"
"
I (fSU!
SUI
*
"
"
"
"*
ISU2
15U2
"
"
10 + 112
110 +
12
13 + 115
113 +
15
16 + 118
116 +
18
"
"
ISU2
ISU2
*
*
*
"
"
"
11
11
14
14
17
17
SU3 + ISUI
ISU3 + SUI
"
"
*
*
*
*
110 +
*
116 +
16
10;
113 +
13
*
"
"
SU3 + ISU!
ISU3 + SUI
SU2
5U2
"
"
"
"
SU2
SU2
ISU3 +
SU3 ;
"
"
ISU3 +
5U3> ;
Figure 3. AMAZE Implementation of the Parity Generator/Checker Circuit
June 1988
497
AN21
Signetics Application Specific Products
Application Note
9-Bit Parity Generator/Checker With 82S153/153A
AN21
Table 1. Programming Table
********************
Cust/Prcject
Date
Revii. D.
PARGEN
********************
*******************************
*******************************
825153
xx/xx/xxxx
REV. -
POLARITY
T
!L:H:H:H:H:H:H:H:H:H!
!-------------------------------------------------------M !-------------------------------------------------______ _
! 7_.6 __ 5_ 4_3_2_1_0' 9 _8_·'_6_5 __ 4_3_2_1_0' 9 _8_7 _6_5_ 4_3_2_1_0!
E
R
B(i)
1!-
-,-LLH!--,-,-LHL!--,-
0'-
B(o)
-,-,-
-,
.,AAAA,.
-! . . ,AAAA,.
AA!
AA'
,A A A A,.
A A!
2!-
- -,- H L L!- -,- -
-,-
-~.
3!4!-
,
H H H!- -,L L,H
-!- -,-
-,-,-
-! • • ,A A A A,.
A A!
- ' . ,A A A A,. A
A'
5!-
L H,L
-,-
_I
_1-
-,-
-
.,A A A A,.
A
A!
6!H L,L
- -!- -,-,-! • • ,A A A A,. A
A!
7!--HH,H---'--,--,-!
.,AAAA,.A
A!
8!L H - -,- -!- -,-,L! • . ,A A A A,A
A!
9!H L
-,-,- -,-,L! . • ,A A A A,A
A!
10!L L - -,-,- -,-,H! . . ,A A A A,A
A!
11!HH-'-,-!---,-,
-H! . . ,AAAA,A
A!
12!- -,-,- - - -,H L L -!A A,A A A A,.
A!
13!- -,-,- -,- -,L H L -!A A,A A A A,.
A!
14!-,-,,- -,-' ·-,L L H -!A A,A A A A,.
A!
15!-,
,--,HHH-!AA,AAAA,.
A!
16!0 0
0,0 0 0 0'0 0,0 0 0 0,0 0 0 O!A A,A A A A,A A A A!
17~O 0 0 0,0 0 0 O!O 0,0 0 0 0,0 0 0 O!A A,A A A A,A A A A!
°
18!O 0 0 0,0 0 0 O!O 0,0 0 0 0,0 0 0 O!A A,A A A A,A A A A!
19!O 0 0 0,0 0 0 ()!O 0,0 0 0 0,0 0 0 O!A A,A A A A,A A A A!
20!O 0 0 0,0 0 0 O!O 0,0 0 0 0,0 0 0 O!A A,A A A A,A A A A!
21!O 0 0 0,0 0 0 O!O 0,0 0 0 0,0 0 0 O!A A,A A A A,A A A A!
22!O 0 0 0,0 0 0 O!O 0,0 0 0 0,0 0 0 O!A A,A A A A,A A A A!
23!O
24!0
25!O
26!0
27!0
28!0
29!O
30!0
31!O
D9!D8!D7!
D6!O
0
0
0
0
0
0
0
0
0
° ()
0 0,0 0 0
0 0,0 0 0
0 0.0 0 0
0,0 0 0
0 0,0 0
0 0,0 0 0
0 0,0 0 0
0 0,0 0 0
0 0,0 0 0
-,-
°
°
,
0 0,0
o 0 0,0
D5!O (I 0 0,0
D4!O 0 0 0,0
D3!-,D2!-,-
o
o
o
o
O!O
O!O
O!O
O!O
O!O
O!O
O!O
O!O
O!O
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0,0
0 0 0,0
0,0
0 0 0,0
0 0 0,0
0 0 0,0
0 0 0,0
0 0 0,0
0 0 0,0
00 0,0
_1-
_,_
-
-!-,
0
0
0
0
O!O
O!O
O!O
O!O
-!-
0,0
0,0
0,0
0,0
-,-,-
0 0
0
0 0
0'0
0 0
0 0
0 0
0
0 0
O!A A,A A
O!A A,A A
O~A A,A A
O!A A,A A
O!A A,A A
O!A A,A A
O!A A,A A
O!A A,A A
O!A A,A A
_,_
_1
,
°
-!
°°
°
°
0 0 0,0
0
0 0 0,0 0 0
0
0,0 0 0
0 0 0,0 0 0
O!
O!
O!
O!
-,-
-,
°
-,-
A A,A
A A,A
A A,A
A A,A
A A,A
A A,A
A A,A
A A,A
A A,A
A A
A A
A A
A A
A A
A A
A A
A A
A A
A!
A!
A!
A!
A!
A!
A!
A!
A!
-!
D1! ,
"
DO!O 0 0 0,0 0 0 O!O 0,0 0 0 0,0 0 0 O!
I
I
I
765 4 3 2
June 1988
5 S N N N N S S S I S 5 N N N N 5 5 S I
I I / / U U U 8 U U I I I / U U U 8
o U U
MMC C C C 3 2 1
M MC C C C 3 2 1
E 0
E 0
498
Signetics Application Specific Products
Application Note
9-Bit Parity Generator/Checker With 82S153/153A
AN21
*K****~*********************************************** **************~
*
"
*
This is a test pattern for the 9-bit
Cit"Clwtit.
The simulato''''' wi 11
Lise
this
parity
geYlet~ator/chec~er
fi Ie as Bn
lnput to
*
simulate the logical function.
*********************************************************************
55
UU
555
"11111111 MMBBBBUUUI
"7E.543210 E07554321B
LLLLLLLL IIIIIIIIIL
HLHHLHLL IIIIII/i/H
LHHLLHHL /11/IIIIIH
HHLHLLHL IIIIIIIIIL
LLHLHHLH IIIIIIIIIH
HLLHHLLH IIIIIIIIIL
LHLLHLHH IIIIIIIIIL
HHHHHHHH IIIIIIIIIH
QUIT
EXPECTED
OUTPUTS
BIlBBB
9B321
"HLLLL
"LHLLH
"LHLHL
"HLLHH
"LHHLL
"HLHLH
"HLHHL
"LHHHH
a. Input Pattern PARGEN.TST
825153
A:pargen.STD
This file is the result of logic simulatIon of the parity qenerator/checker
" circuit. The inputs are read from input file PARGEN.TST
INPUTS (;B(1/0);)
" 76543210 9876543210
TRACE TERMS
00000000
10110100
01100110
11010010
HL •... LLLO
LH .•.• LLHI
LH .... LHLI
HL •... LHHO
(~101101 LH ..•. HLLI
10011001 HL .... HLHO
01001011 HL .... HHLO
11111111 LH ...• HHHI
001 I I 10001
0011110001
1/0 CONTRUL LINES
DESIGNATED 1/0 USAGE
ACTUAL 1/0 USAGE
" PIN LIST .•.
I.
08 07 06 05 04 03 02 01
19 18 17 16 15 14 13 12 11 09
b. Output File From SIMULATOR
Figure 4. Test Vectors
June 1988
499
Application Note
Signetics Application Specific Products
9-Bit Parity Generator/Checker With 82S153/153A
AN21
APPENDIX A
"
"
'.
"
'.
"
'.
'.
'"
'"
s,
s,
s,
s,
s,
".
s,
s,
s,
s,
31 • • • • • • 24
23 • • • • • • 16
15 • • • • • • 8
7 •••••• 0
NOTES,
1. All programmed" AND" gale locations are pulled to logic" 1"
2. All programmed 'OR" gate locations are pulled to logic "0'
3. o~ Programmable connection.
Figure A-1. FPLA Logic Diagram
June 1988
500
Signetics
AN23
PLS168/168A Primer
Application Note
Application Specific Products
INTRODUCTION
THE PLS168/168A is a bipolar Field-Programmable Logic Sequencer as shown in
Figure 1, which consists of 12 inputs, a 48
product term PLA and 14 R/S flip-flops. Out
of the 14 flip-flops, six are buried State
Registers (P 4 - Pg), four Output Registers
(Fa - F3), and four Dual-purpose Registers
(Po - P3 ), which may be used as Output or
State Registers. All flip-flops are positive
edge-triggered. They are preset to "1" at
power-up, or may be asynchronously set to
"1" by an optional PR/OE pin, which may be
programmed either as a preset pin or as an
Output Enable pin. Additional features includes the Complement Array and diagnostics features.
ARCHITECTURE
As shown in Figure 2, the device is organized
as a decoding AND-OR network which drives
a set of registers some of which, in turn,
feedbacks to the AND/OR decoder while the
rest serve as outputs. Outputs Po to P3 may
be programmed to feedback to the AND/OR
decoder as State Registers and, at the same
time, used as outputs. The user now can
design a 10-bit state machine without external wiring. The AND/OR array is the classical
PLA structure in which the outputs of all the
AND gates can be programmed to drive all
June 1988
the OR gates. The schematic diagram of the
AND-OR array is shown in Figure 3. This
structure provides the user a very structured
design methodology which can be automated
by CAD tools, such as Signetics AMAZE
software package. The output of the PLA is in
the form of sum-of-products which, together
with the RS flip-flops, is the ideal structure for
implementation of state machines. (Refer to
Appendix A for a brief description of synchronous finite state machines.)
Design Tools
A direct approach to Implement a design
using the PLS168/168A is the H/L table
supplied in the data sheet as shown in Table
1. The table is organized according to input
and output of the PLA decoding network. The
lefthand side of the table represent the inputs
to the AND-array, which includes input from
input pins and present state information from
the feedback buffers which feedback the
contents of the State Register. The righthand
Side of the table represents the output of the
OR-array, which drives the State and Output
Registers as the next state and output Each
column in the lefthand side of the table
represents an input buffer, which may be
inverting, non-inverting, disconnected or unprogrammed. Each column in the righthand
side of the table represents a pair of outputs
to the flip-flops, which may be set, reset,
501
disconnected, or unprogrammed. The programming symbols are H, L, -, and O. (See
Figure 4 for details.) For inputs buffers, "H"
means that the non-inverting buffer is con-
nected, "L" means that the inverting buffer is
connected, "-" means that both inverting
and non-inverting buffers are disconnected,
and "0" means that both inverting and noninverting buffers are connected which causes
that particular AND-term to be unconditionally
Low. On the output side of the table, "H"
means that the particular AND-term IS connected to the OR-term on the" S" input of the
particular flip-flop, "L" means that the ANDterm is connected to the lOR" side, "-"
means that the AND-term is not connected to
the flip-flop at all, and "0" means that the
AND-term is connected to both the" S" and
"R" sides. More details of the symbols and
their meanings are shown in Appendix B.
Each row in the table represents an ANDterm. There are 48 AND-terms in the device.
Therefore, there are 48 rows in the table. An
example of implementing a transition from
one state to another is shown in Figure 4a.
The state diagram can be implemented by the
PLS168 as shown in Figure 4b. The state
diagram is translated into H/L format as
shown in Figure 4c. The first column on the
lefthand side of the table is for the Complement Array which will be discussed in detail in
the next section.
Application Note
Signetics Application Specific Products
AN23
PLS168j168A Primer
NOTES:
1. All programmed "AND" gate locations are pulled to logic "1".
2. All programmed "OR" gate locations are pulled to logic "0".
3. $I Programmable connection.
Figure 1. Logic Diagram of PLS168/168A
June 1988
502
Signetics Application Specific Products
Application Note
PLS168/168A Primer
AN23
Table 1. PLS168/168A Programming Table
CUSTOME" NAYE
PURCHASE ORDER ff
CF (XXXX}
SlGNEnCS DEVICE.
CUSTOMER SYMBOLIZED PART.
'.
TOTAL NUII8ER OF PARTS'
O.lOON
PROGRAM TABLE.
1. 0 , .
"EV
DATE
..;
·,
IG" r
PR. .
~:;tt
''
:
:
·
..·
:
:
:
:
i
i
i
----:
:
..i.
:
22
...L
..i.
----
:
i
;
:
i
...L
-------:
----
_1
----:
:
:
...L
i
----
:
30
:
i
.
..
.,"
-"...
----
"
--=-
.
PON
NO.
:
:
i:i:l: I: I:
1:1: : I: I~ .; I'"
:1' 1'1- j'I'I'
IYA:!:'~"
June 1988
"'"
i
.
..
..
O-"T
I
i
:
:
:
"
"
"
"
"
"
"
"
,."
"
0.
NEXT :::~"N"
;
-'-
"..
..
OPT'ON,P"
..i.
..i.
~
.
.......
~
....f.
'-E
,•
"
"
"
"
"
"
-"
"
~
503
Signetics Application Specific Products
Application Note
PLS168j168A Primer
AN23
I
12 INPUTS
rry
OUTPUT
REGISTER~
t:=:!>
I
10 REGISTER
STATE F=1l
FEEDBACK IL_~
L_========:R:E:G:IST:E:R:S=::.J::JI
D
Figure 2. The Architecture of PlS168/168A
June 1988
504
Signetics Application Specific Products
Application Note
AN23
PLS168/168A Primer
\
,--
Vee
Vee
AND-GATE
I
Ni-C'FUSE"l
I
I
I
,.....-----if--_- vee
----_
I
-----
I
TOOTHER
AND-GATES
TOOTHER
AND-GATES
---+-I-4~---+--~I---;~;~} =~
I
IL ____ _
OR·GATE
-------=IJ
Figure 3. Schematic Diagram of AND-OR Array
June 1988
505
Signetics Application Specific Products
Application Note
PLS168/168A Primer
AN23
L L:L L H L:L L:L L H L:-
08 A L H L H:10 •
-
L HL L
L HL H
L HHH
-
11
PIN1122:22
NO. 8 8 0 1: 2 3 2 3 4 5 6 7
1
6
1
3
1
0 9 8
N
A
~ i ~ ~l:
~~
c. PLS168 Programming Table
Figure 7. Applications of Complement Array
June 1988
509
_"Q
(l.
<=B =)
11
109876543210 9876543210
000000000000
010000000000
100000000000
110000000000
000100000000
001000000000
00 II 00000000
000001000000
000010000000
000011000000
000000010000
000000100000
000000110000
000000000100
000000001000
00000000 II 00
TRACE TERMS
OOOOLHOOOO
OOOOHLOOOO
OOOOHLOOOO
OOOOLHOOOO
OOOOHLOOOO
OOOOHLOOOO
OOOOLHOOOO
OOOOHLOOOO
OOOOHLOOOO
OOOOLHOOOO
OOOOHLOOOO
OOOOHLOOOO
OOOOLHOOOO
OOOOHLOOOO
OOOOHLOOOO
OOOOLHOOOO
000000000001 OOOOHLOOOQ
000000000010
000000000011
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
OOOOHLOOOO
OOOOLHOOOO
OIOOHLOOOO
1000HLOOOO
1100LHOOOO
000 1 HLoaoo
OOlOHLOOOO
OOIILHOOOO
000000000000 OOQOHLOIOO
000000000000
000000000000
000000000000
000000000000
000000000000
OOOOHLlOOO
0000LH1100
OOOOHLOOOI
OOOOHLOOIO
0000LHOOl1
------------ ---------IIIIOOIIII
I/O CONTROL LINES
DESIGNATED 110 USAGE
1111001111
ACTUAL 110 USAGE
.. PINLlST ...
13 II 10 09 08 07 06 05 04 03 02 pI
.. 23 22 21 20 19 18 17 16 15 14
d. Test Vectors Generated by AMAZE After Logic Simulation
Figure 2 (Continued)
June 1988
517
AN24
Signetics Application Specific Products
Application Note
PlS173 as a 10-Bit Comparator, 74lS460
AN24
********************
AN24 173 **************.*****
••••••••••• ~ •••••• DAVID WONG
Cust/Project Date
Rev/I. D.
•••••••••••••••••• OCT-14-B5
- •••••••••••••••••• REV-O
829173
POLARITY
!H:H:H:H:H: L: H:H:H:H!
! ---------------------------------------------------------------R !
SCi)
BCD)
M ! 1 1 -----------------------------------------------------------___ ! 1_0_9_8_7_6_5_4_3_2_1_0!9_B_7 _6_5_ 4_3_2_1_0! 9_8]_6_5_4_3_2_1_0!
O!----,----,--LH!--,----,----!.
AA,.
!
1!- - - -:-,- - - -,- - H L!- -,- - - -,- - - -!.
A At_
2!- - - -,- - - -,L H - -!- -,- - - -,- - - -!.
A At.
3!- - - -,- - - -,H l - -!- -,- - - -,- - - -!.
A At.
4!- - - -,- - L H,- - - -!- -,- - - -,- - - -!.
A A,.
5!- -,- - H L,- - - -!- -,- - - -,- - - -!.
A A,.
6!- - - -,L H - -,- - - -!- -,- - - -,- - - -!.
A A,.
7!- - - -,H L - -,- - - -!- -,- - - -,- - - -!.
A A,.
8!- - L H,- - - -,- - - -!- -,- - - -,- - - _ I .
A A,.
9!- - H L,- - - -,- - - -!- -,- - - -,- - - -!.
A A,.
10!L H - -,- - - -,- - - -!- -,- - - -,- - - -!.
A A,.
l1!H L - -,- - - -,- - - -!- -,- - - -,- - - -!.
A A,.
12!- - - -,- - - -,- - - -!- -,- - - -,- - H L!.
A A,.
13!- - - -,- - - -,- _1- - , - -,- L H!.
A A,.
14!- - - -,- - - -,- - - -!- -,- - - -,L H - -!.
A A,.
15!- - - -,- - - -,- - - -!- -,- - - -,H L - -!.
A A,.
16 ' - - - -,- - - -,- - - -!- -,L H - -,- - - -!.
A A,.
17!- - - -,- - - -,- - - -!- -,H L - -,- - - _ I .
A A,.
18 ' - - - -,- - - -,- - - -!L H,- - - -,- - - -!.
A A,.
19!- - - -,- - - -,- - - -IH L,- - - -,- - - -!.
A A,.
20'- - - -,- - - _,_ - - _ 1 - _ , _ _ _ _ , _ _ _ _ !.
21!22!23!24!25!26!27!28!29!30 ' 31 ' D9!0
0
D8~0 0
D7!0 0
D6~0 0
D5!- -
0
0
0
0
-
-,-,-,-,-,-,-,-,-,-,_,_
0.0
0,0
0,0
0,0
-,-
0
0
0
0
-
D4!D3 ' O
D2!0
D1!0
DO!O
0
0
0
0
-,0,0
0,0
0,0
0,0
- - -,- - 0
0
0 0 0,0 0 0
0 0 0,0 0 0
0
0
0
0
0
0
-,-,-,-,-,-,-,-,-,-,_,_
0,0
0,0
0,0
a 0,0
- _,_
°
0
0
0
0
-
°0 °0 0,0
0
0,0 0
- -!- -,- - - -,- - - -!.
- _1- _, _ _ _ _ , _ _ _ _ I.
0
0
0
0
-
-1-
_, _ _ _ _ , _ _ _ _ I.
-1-
_, _ _ _ _ , _ _ _ _ I.
-!- -,- - - -.- - - -!.
-!- -,- - - -,- - - -!.
-!- -,- - - -,- - - -!.
_1-
_, _ _ _ _ , _ _ _ _
~.
-!- -,- - - -,- - - -!.
-!- -.- - - -,- - - -~.
_ 1 - _ , _ _ _ _ , _ _ _ _ !.
O!O
O!O
O!O
0 10
0,0
0,0
0,0
0,0
00
0 0
0 a
0
_1-
_, _ _ _ _ , _ _ _ _
-!O!O
O!O
O!O
O!O
-,0,0
0,0
0,0
0,0
°
0,0
0,0
0,0
0,0
0 0 01
0 0 O!
0
O~
0
0'
!
°°
- -,- __
-~
0 0
°00 000 0,0
0,0 0 0
0,0 0 0
O~
-
O!
O!
0 0 0,0 0 0 O!
BABABABABABABABANEBABABABANEBABA
5544332211009988EQ77669988EQ7766
Figure 3. Program Table of 10·Bit Comparator with All Unused Terms Deleted
June 1988
518
Signetics Application Specific Products
Application Note
PlS173 as a 10-Bit Comparator, 74lS460
AN24
APPENDIX A
FPLA LOGIC DIAGRAM FOR PLS173
,----------------~~.----------------------------,
__ --,. (CONTROL TERMS\______.
B,
B.
31··.· •• 2423··· .. · · 1 6 1 5 · · · · · · 8 1 · · · · · · 0
NOTES:
1 All programmed" AND" gate locations are
All programmed "OR" gate locations are
Programmable connection
June 1988
to logic '1
to logic
519
Signetics
AN26
PLHS18P8A Primer
Application Note
Application Specific Products
FEATURES
• 100% functional replacement for all
20-pin PALs
• I/O propagation delay: 20ns (max)
• Security fuse lock
• 10 inputs
• 8 bidirectional I/O lines
• Tri-state outputs have programmable
polarity
• Architecture: 8 groups of nine AND
gates. Total of 72 product terms
• Software support on Signetics
AMAZE
• Complete TTL compatibility
• Each bidirectional I/O has individually
controllable output enable
ARCHITECTURE
The PLHS1BPBA is an oxide-isolated. bipolar
field-programmable logic array. This device is
configured as a decoding two-level AND-OR
(sum of products) structure. The PLHS1BP8A
block diagram is shown in Figure 1. All the
AND gates are linked to ·ten inputs (10 - 19)
and eight bidirectional 1/0 lines (B(o) - B(7)).
These links can he made via the on-chip
true/complement buffers. The 72 AND gates
are configured in 8 groups which contain 9
AND gates each. In every group. eight AND
gates are used for user-defined logic functions and the ninth AND gate is used as a tristate output enable control. This gives the
user capability to control the output enable by
means of a product term. The outputs of the
eight logical product terms are ORed together
(see Figure 1). The output polarity of each OR
gate is individually programmable via an Exclusive-OR gate. The user has a choice of
Active-Low or Active-High on each of the
eight outputs. Figure 2 shows the logic dia·
gram of the PLHSI8P8A.
HOW A DEVICE IS
PROGRAMMED
There are three main programmable sections
on the PLHSI8P8A:
A. The AND array.
B. The output polarity.
C. The security fuse.
A. The AND Array - The AND array fuses
are back-to-back diode pairs which act as
open connections in a virgin device. These
open connections are configured as 'Don't
Cares' C- ') in an unprogrammed device. The
open connections are pulled to a logic High
(' 1') (see Figure 3). Consequently, all unprogrammed AND locations are pulled to a logic
High C1') state. This means that in an unprogrammed device, all the product terms are
active. During fusing, current is avalanched
across individual diode pairs. This essentially
short circuits the diode and provides a connection for the associated product term. Figure 3 shows how a typical connection is made
to the AND array (see Appendix B for a
description of the vertical fuses).
The inputs to the AND array consist of 10
dedicated inputs (10 - 19) and 8 bidirectional
II0s (B(O) - 8(7». Initially, all these inputs are
configured as 'Don't Cares' C - '). These
inputs can be connected to the AND array
through an inverting or non-inverting buffer.
The AND gate can be connected to the
inverting buffer by programming the inverting
fuse. Similarly, a connection can be made to
the non-inverting buffer by programming the
non-inverting fuse. Disabling an AND term is
achieved by implementing a logical Low CO')
on the output of the specified AND gate.
When both fuses of an input (e.g. 10 and lO)
are programmed, both the inverting and noninverting buffers are connected to the inputs
of the AND gate. To achieve this a '0' should
be entered on the program table under the
specified input. This will in turn create a
logical Low CO') on the output. To avoid any
glitches on the output, it is a good practice to
program all Inputs to force a logical Low CO').
In each block of nine AND gates, one gate is
used as an output enable control for the tristate output (Terms 0, 9, 18, 27, 36, 45, 54,
63, designated as D on Table 2). The remaining eight gates are connected to a fixed OR
gate. Since in the unprogrammed state the
outputs of all the AND gates are at logic High
C1'), the output of the OR gate also acquires
a logic High state. Therefore the user is
responsible for deactivating any unwanted
product terms. This is done by creating a logic
Low CO') on the outputs of the unwanted
product terms as previously explained. Moreover, the output buffer is always enabled
since the product term controlling the tri-state
output buffer also has a logic High state. If
any of the bidirectional pins are to be defined
as inputs, the product term controlling the
specified bidirectional pin must be disabled.
The bidirectional pin can also be configured
as a dynamic I/O by defining the required
logic for the output-enable-control product
term.
The actual programming of the PLHS1BPBA
is carried out according to JEDEC ' standards
and the specific programming algorithm developed for the part.
According to JEDEC standards on data preparation for the PLD programmer, a "1" specifies a high Impedance for the specified fuse
and "0" a low impedance for the designated
fuse.
For the AND array, the programming algorithm leaves the fuse intact (open-circuited)
when a JEDEC "1" is specified. Consequently, a JEDEC "0" programs and short circuits
the specified fuse. The programming algorithm is different for the output polarity and
will be explained in the next paragraph on
Special Conditions for the Output Polarity.
B. Special Conditions For The Output Polarity - In an unprogrammed device, all the
output polarities are configured as inverting
buffers. In this state, the device will have logic
Low on all its outputs. The outputs of the
PLHS18P8A are configured as tri-state buffers. The two inputs of each Ex-OR gate are
connected as follows: one input is connected
to the output of the fixed OR gate. The
second input is a connection to ground (logic
Low) through a fUSible link.
As mentioned earlier, an unprogrammed fuse
acts as an open connection which is pulled to
a logic High. Therefore the output of the ExOR gate acts as an inverting buffer. When the
fuse is programmed, there is a connection
between ground (logic Low) and the input of
the Ex-OR gate. This will cause the Ex-OR
gate to act as a non-inverting buffer
1. For more information on standard data transfer format between the data preparation system and PLD programmer, refer to JEDEC Council publications.
June 1988
520
Solid State Engineering
Signetics Application Specific Products
Application Note
PlHS18P8A Primer
AN26
+-__________
~~OL~____
~
TERM
I/O
110
I/O
110
INPUTS
1/0
110
110
AND ARRAY
Figure 1. Block Diagram of the PLHS18P8A
June 1988
521
Application Note
Signetics Application Specific Products
AN26
PLHS18P8A Primer
,--------------------------
...
"
a,
"
8,
~
U>
I
J4
i!!
t;
"c0
.,
0:
0-
"
1. All unprogrammed or virgin "AND" gate locations are pulled to
2. All unprogrammed or virgin "OR" gate locations are pulled to
3. .f.t Programmable corrections.
NOTES,
Figure 2.
June 1988
"1"
'"1"
logic Diagram of the
522
PLHS1!!'!~
________
~~"O'"''
Signetics Application SpeCific Products
Application Note
PLHS18P8A Primer
AN26
The procedure for programming this fuse
depends on the programmer manufacturer
and is explained in the manufacturer's operations manual.
-"<:c-i-......-
I(n) _ _ _
I(n)--
DESIGN TOOLS FOR THE
PLHS18P8A
a. Unprogrammed Connection
b. Programmed. The Non-Inverting Buffer
is Connected to the AND Gate
Figure 3. How a Fuse is Programmed
Many CAD tools such as Signetics' AMAZE
software 2 are available to implement designs
using the PLHSI8P8A. The AMAZE software
enables the user to enter the design in the
form of Boolean equations or via the program
table shown in Table 2. This program table is
a one-to-one map of all the programmable
links of Figure 2. The following explains the
implementation of designs uSing the program
table. Also, an example on using the Boolean
Logic Entry program of the AMAZE software
is given.
Using PTE (Program Table Entry) - Assume that Z is a typical logic function with the
following equation:
DFUSE
U
U
P
P
AND/OR
INPUT
OUTPUT
0
I
I
0
0
0
I
I
<=>
Z
PO
~
A • IB
C
-t>o--
P1
~
1A • B
ID
-t>-
The program table in Table 2 is used to
implement this equation. Table 3 shows the
implementation of the logic function uSing the
PTE. The first group of AND terms is used to
implement this function. B(7) is used for the
output, 10, 11, and 12 as inputs.
P = PROGRAMMED
U = UNPROGRAMMED
Table 1. Programming Algorithm
1 - High impedance
0- Low impedance
PO + P1
OUTPUT
POLARITY
Figure 4. Output Polarity Definition
JEDEC SPECIFICATION
~
Where PO and P1 are product terms with the
following equations:
AND ARRAY FUSE
PROGRAMMING
ALGORITHM
OUTPUT POLARITY FUSE
PROGRAMMING
ALGORITHM
Fuse unprogrammed
(open circuit)
Fuse programmed
Fuse programmed
Fuse unprogrammed
(short circuit)
(open circuit)
(short circuit)
Figure 4 shows the definition of the output
polarity for the PLHS18P8A. As can be seen.
the output configuration of the PLHS18P8A is
equivalent to an Ex-OR gate.
into consideration when designing With the
PLHS18P8A. Table 1 shows the resulting
programming algorithm from the JEDEC
specification.
The programming algorithm for the output
polarity section of the PLHS 18P8A is different
from that of the AND array. For the output
polarity a JEDEC "1" (high impedance) programs (short circuits) the Ex-OR gate fuse,
whereas a "0" (low impedance) leaves the
fuse intact (open circuit).
C. The Security Fuse - Programming equipment used to program the PLHS18P8A are
capable of determining the logic pattern
stored in this device (see Appendix A). The
security fuse can be blown to disable the
programmer from reading the pattern in a
programmed device. This feature adds a
measure of protection for proprietary designs.
The programming specifications are transpar·
ent to the user and do not need to be taken
- Term 0 is the direction control term. It is
the tri-state output enable control term.
Since Z is configured as an output, leaving
Term 0 in its unprogrammed state causes
the output to be unconditionally enabled.
- Term 1 is the P-term labeled PO, where
N IB'C is designated by HLH in columns
10, 11, and 12.
- Term 2 is the P-term labeled P1, where
1NB' 10 is designated by LHL in columns
10, 11, and 12.
- Terms 3, 4, 5, 6, 7. At least one input (or
all the inputs) must be set to zero to
disconnect these terms from the OR gate.
- The output polarity for B(7) is H, and this is
entered in the 'Polarity' section.
Using BLAST (Boolean Logic And State
Transfer) - The BLAST module in AMAZE
can be used to implement the above equation. Figures 5 and 6 show the pin list and
logiC equation formal. Table 4 is the program
table generated from these equations.
2. Refer to Signetics Programmable Logic Data Manual for a complete description of the AMAZE programmable logic development software,
June 1988
523
Application Note
Signetics Application Specific Products
AN26
PlHS18P8A Primer
POLARITY
~
~
__________________~A=N=O~r-________________~
R
OR (FIXED)
B(O)
B(I)
M987654
0765421
6
5
4
2
1
10
11
12
13
14
15
16
17
18
,I tll
01 J:
I "
I '"
+
I
I
~i
------------J-~-+~
••
--~~~D------------------~~.o
--~~~--------------------~o.
NOTES:
1. All unprogrammed or virgin "AND" gate locations are pulled to logic "1",
2. All unprogrammed or virgin "OR" gate locations are pulled to logic "0".
3.
it Programmable connections.
Figure 1. PLHS473 Logic Diagram
June 1988
530
Signetics Application Specific Products
Application Note
PlHS473 Primer
AN27
HIGH. An example is shown in Table 2. term
o where pins OA. Os 8(0)8 are programmed
as dedicated outputs. The input section of
term 0 is entirely "dashed out" (this is actually its unprogrammed state) which causes the
AND term to be unconditionally HIGH. OR
terms EA. Es. and 08 are connected to
product term 0 by the "A" entries in their
respective squares. The rest of the 0 section
and the 8(0) section are "dotted out" (left
unconnected) since we are not concerned
with them for the moment. If more outputs are
needed later on. their corresponding squares
may be changed to "As" from "dots" as the
need arises.
OUTPUT =
I(SUM·Of.PROOUC1)
Figure 2. Emulation of Open-Collector Output
Notice that as shown in Figure 1. all fuses in
their unprogrammed state are normally opencircuited. This means that all product terms
are initially disconnected to the OR array. all
OR gates are initially at a logic LOW. and all
output pins are initially in High-Z state. Therefore. if anys of the outputs are to be enabled.
its controlling OR term must be set to a logic
Table 1. PLHS473 Programming Table
----------+---------I
AND
CUSTOMER NAME
PURCHASE ORDER #
SIGNETICS DEVICE #
10
0
1
• •
7
,
3
2
1
0
Il
IA
IINACTIVE
I.
8(0)
1----------I
1
CONTROL
f---------HI
: IHIGH
I
SECTION E ' "
. I,POL)
POLARITY
Il
IlOW
ILl
OR
E
B(I)
4
H I,B(I)
,I
•
7
6
5
4
R
3
2
1
0
M
0
1
2
3
4
2
3
4
5
,
•
0
E
•
A
•
7
6
5
4
B (0)
0
3
2
1
0
•
A
•
7
6
5
4
3
2
1
0
,
•
5
7
7
~
!--iT
f-T,-
SECTION A
-~tr,;-t-If,-
SECTION B
f-T,-
SECTION 0
SECTIONC
~
-r-w-
To
15
15
"
16
17
17
18
18
19
19
20
-
20
21
21
22
22
23
PIN
I
OR
!AcnvE
T
1
5
I••
:
DON'T CARE 1-
AND
T
M
10
i, B
TOTAL NUMBER OF PARTS
PROGRAM TABLE # _ _ _ _ REV _ _ _ DATE
E
R
INACTIVE
CF(XXXX)
CUSTOMER SYMBOLIZED PART #
I
11
10
••
7
,
23
5
4
3
2
1
23
22
21
20
17
16
15
14
13
19
Notes
i;
~~
June 1988
1. The FPLA Is shipped with all links open.
2. Unused I and B bits in the AND array exist
Don't ear. I-) in the virgin state.
3. All p·tenns are Inactive on all outputs (B, 0) in the
virgin array.
4. Unused product terms can be left blank.
.s
531
18
23
22
21
20
17
18
15
I.
13
Signetics Application Specific Products
Application Note
PLHS473 Primer
AN27
OUTPUT POLARITY - (0, B)
S~D-o'l!
I
ACTIVE LEVEL
L
COOE
I
I
L
I
L
I
LOW'
ACTIVE LEVEL
HIGH
I CODE
I
IHI
AND ARRAY - (I, B)
I,B
4" 4" 4" 4"
I,B
CODE
DON'T CAREl
-
I
L
STATE
INACTIVE 2
!
!
I
0
I
I
STATE
I, B
TC02630S
I
INACTIVE'
I
CODE
I
•
I
E
P n STATUS
ACTIVE '
NOTES:
1. This is the initial unprogrammed state of all link pairs.
2. Any gate Pn will be unconditionally inhibited if anyone of its (I, 8) link pairs is programmed for a
connection.
INPU"f.1-INPUf.2
O·C - (INPUT·'·INPUT-2) +(INPUT·3·INPUT·4)
Figure 3. Emulation of Open-Collector Output
June 1988
I
C~DE I
STATE
I
1.8
I
COLDE
I
TC02620S
VIRGIN STATE
f-D-s
Po STATUS
P
TC02610S
OR ARRAY - (0, B)
I
1,8
P
CODE
TC02600S
__
I,B
P
P
STATE
I,B
I,B
I,B
1,8
532
A factor shipped virgin device contains all
fusible links.
1.
2.
3.
All output at "L" polarity.
All P n terms are enable.
All P n terms are active on all outputs.
Signetics Application Specific Products
Application Note
PLHS473 Primer
AN27
Once we have determined the outputs, we
OUT-1
~
can proceed with defining the logic funGtion!=>
As an example, the logic function
OUT-O
~
(INPUT-1 '/INPUT-2) +
(INPUT-3 • INPUT-4)
tion. Notice that the B(O) of O-C is programmed as a "dot" in both terms 12 and 13,
which, together with the polarity control,
causes it to be unconditionally Low, since a
disconnected OR term is unconditionally Low.
The intersections of column D7 and terms 12
and 13 are programmed "A" so that the tristate output buffer of B(Oh is enabled at
input conditions (INPUT-1 • INPUT-2) ~ 1 or
(INPUT-3 ' INPUT-4) ~ 1. Terms 10 and 11
may be represented as shown in Figure 3.
The logic function
INPUT-1' /INPUT-2
OUT-2
is shown in Table 2, term #2 where in the
column labeled "INPUT-1", an "H" is entered to represent a connection of the noninverting input buffer of INPUT-1 and the AND
term 2. In the column labelled "INPUT-2", an
"L" is entered to represent the connection of
the inverting input buffer of INPUT-1 and the
AND term 2. On the output side of the table,
OB in term 0 is programmed "A" to make a
connection between term 2 and the OR term
which is connected to the output pin 0B: The
output polarity of OB is arbitrarily set to
Active-High by programming an "H" in the
Os column of the polarity section.
A sum of several product terms (AND-OR) is
implemented by connecting multiple AND
terms to the same OR term. An example is
shown in Table 2, terms 4 and 5, which
implement the logic function
~
/«INPUT-1 ' INPUT-2) +
(INPUT-3 • INPUT-4))
is shown in terms 9 and 1O. The output is
Active-Low as programmed "L" in the polarity section of OUT-2. As a rule, the AND
function is implemented in a row, whereas the
OR function is implemented in a column.
Since the AND portions of terms 2 and 4 are
the same, they may be combined as shown in
term 7, which saves a duplicated term.
Signetics produces a software package,
AMAZE, as a design tool which assists implementation of logic design and documentation.
For further information on AMAZE software,
refer to the AMAZE User's Manual. Two
simple circuits shown as examples are implemented using AMAZE. The first circuit is a
simple cross-coupled RS latch. The second
circuit is a multiplexer/demultiplexer which
multiplexes four inputs to one output or demultiplexes one input into four outputs. Both
circuits are put into the same PLHS473 device.
Table 2 terms 12 and 13 together emulate an
open-collector output as an example. The
logic equation
O-C~
/«INPUT-1 • INPUT-2) +
(INPUT-3 • INPUT-4))
is implemented by first programming O-C
Active-High in the polarity section. Terms 12
and 13 implement the sum of product func-
Table 2. Examples of Programming PLHS473
AND
I
OR
IACTIVE !AI.(OI
IINACTIVe
----------+-----------
CUSTOMERNAME _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
INACTIVE
10
i
I
I, B
IH
L..---------
PURCHASE ORDER # __________________________
SlGNETlCS DEVICE # _________ CF (XXXX), __________
CUSTOMER SYMBOLIZED PART # __________________
1-.1'
1-----+-11,8(1)
I..... ________
CONTROl
T, B
IL
_
TOTAL NUMBER OF PARTS ______________________
DON'T CAREI-
PROGRAM TABLE # _______ REV _____ DATE _______
II
1
I
HIGH
I H (POL)
LOW
I L
II
r
~---__;=:;;;;;;_-----,
POlARITY
RilL
~ ~----~-__---A~N~D-r----~.~(II---~
:
B(O)
r,~O~.~8~7~.~5~4~~3~2~~~~.~7~.~5~.~3~~2~'~O
SA876543210BA8785432
o
,
If
L
-
A A A •
. '."
'"
2
1/ H 1/ L
•
10
"
H
12
13
II II
-
_
." .
"
11
II
II H _
_
13
•
•
•
11 •
"
"
""
"
"
20
"
"
22
20
22
23
PIN
23
11
10
9- 8
7
6
5
4
3
2
1
23
22
21
20
17
16
15
14
13
......
1. The FPLA .. shipped with all ling open.
2. UI'IUSfId I and B bits In the ANOarravexllt ••
Don't ear. (-) In the virgin stllte.
3. All P-tenns are lnectlve on aM 0UIPUt. (8, 0) In the
vkgln array.
4. Unused product term. ClI" be kft blank.
June 1988
533
18182322
2120
111815
1413
Application Note
Signetics Application Specific Products
PlHS473 Primer
AN27
File Nille : 473PRlI'tE
Dat.: 9/4It986
Tilt I 15153:28
111111111111111111111 PIN
LIS T 11111111""'""1111
..
...
....
..
ffFNCnPIN---------PINnFNCff
LABEL
1-2-4 ft +5V uVCC
I-:
"I
2-:
:-23n/0 1t9
"I
l-nu /0 HONOT
"I It 3-:
Itl It H
:-21 niB uNle
..r
5-:
1-20ftS
"I
H9ffO uN/e
H
"I
1-18UO uN/e
7-:
"I
Itl
8-:
:-17
/8 uN/e
9-: 3 1-16 tt B ltD
Itl
LABEL
IS
Ii
NIC
NIC
NIC
NIC
NIC
NIC
SO
51
Dli
6ND
**
"10-:
:-15tt8
toe
" I ttlH
nOV fi12-:
1-141+8
ItB
itA
Itl
:-131'8
Figure 4. Pin List
File Nille I -473PRlftE
Dat.
Tite
I
I
11411986
15:54114
IDEYICE TYPE
PLiS413
IIIftANIN6
IREYISION
IDATE
ISYMBOL
File nite
473PRHtE
s
tCO/IPANY
INAME
IDESCRIPTlON
ICOMMON PRODUCT TERN
1110 DIRECTION
"Th, I/O DIRECTION definition is optionil, ind lay be d,hulted
to the PIN LIST unless it is bidirectional and is controlled bv
i IDlJic equ.tion, •
"tttUttttftftttfftff
D8 = 1;
110 DEFINITION FOR RIS LATCH
ftiUtttlttfttfftl •
• Each output lUst be defined s.p-erilel y by i ls otIn
10lJie equiUon.·
D7-1 ;
·t.I.....UUUl
110 DEFINITtOtt FOfI ItUXlDEIWX CIRCUIT
ttttlifflfllttl •
D3 = DIR; • "hen DIR = I,ll, 82, 81, 80 beeot! outputs. Dih flailS
fro. F to A, II, C, D••
D2-DIR;
D1 • UIR j
DO-DIRI
D5
s
IDIR I • "hen DIR = 0, 85 becOies IR output, output buHers
of 80 to 83 ire dlubled. Data flOWi fro. A. 8, C,
Dt.F ••
Figure 5. Boolean Equations
June 1988
534
Signetics Application Specific Products
Application Note
PLHS473 Primer
AN27
~aUTPUT
PCLAR!H
The definition of output polanty
the fIN llS]' •
IS
optional and .. y be defaulted
............... POLARITY DEflN1110N fOR RIS LATCH ........... ..
Outputs WIth the sa.e polarity .ay b. deflned
In the sa.e equation. Since the outputs Q and
ONOT are defined" aetlye LON, thIS equatIon
c.auses the ~OR to function as an inverter.
18. X7 ' I ;
M
....... ," POLARITY DEflN1110N fOR NUX/DENUX CIRCUIT ......... ..
X5. 13, X2, XI, If) , 0 :
Outputs BO, 81, 82, B3, 85 are active
HISH, "
@LOGIC EQUmON
UUHtfHUftitU
HWATlONS FOR RIS LATCH
, / i /5 • QNuT ) ;
QNOT ' I ( IR •
tttftttttUtttttHHH
The equatIon .ust used It,e foraat
output, I ( ...... ); sinc. output
Q IS defined as act"e LON ••
Q ) :
" ............ EQUATIONS fOR NUXIDENUI CIRCUll .......
f ' ( A • ISO •
( 8' SO.
! C • ISO'
( 0 t SO t
lSI I '
151) +
51 I ,
51 )
A ' ( f • ISO , 151
B ' ! f t SO, 151 )
C ' If. ISO' 51 )
D ' i f ' SO, 5I
Figure 5. Boolean Equations (Continued)
June 1988
535
tt." ...... .
Signetics Application Specific Products
Application Note
AN27
PLHS473 Primer
...
File Na.e : 473PRIME
Date: 9/4/1986
·1
fl .. : 15:56:24
Cust/Proj.ct
Oat.
Rev/!' D.
, POLARITY'
PLHS473
T
!LLLLLHLHHHH'
E ,---------------------------------------------R'
Bill 'E
!O 810)
M '19876543210' ii76543210' BA87 654321 O! 8A87654321 0'
___ I 0------ ____ 1. ________ ___________ I ______ • ____ I
~
0' ----------H' -H-------, AA •• A. A•••• 'AHA. A. A.... '
I' ------ --'-H- 'H-------- 'AA •. A.A ..•• 'AA. AA. A.... '
2' -LL -------- ,--------H' AA •• A. A••.• 'AA .• AM •••• '
3' -LH-------- ,-------H-' AA .. A. A..... AA •• AHA .... '
4' -HL --------, ------H--' AA .. A. A•••• 'AA •. AM •.•. '
5'-HH--------'-----H---'AA .. A.A .... 'AA •• AAA .•.• '
6' -LL --------, ---H-----' AA •• A. A•••• 'AA .• A.A ••• A'
7'-LH--------'---H-----'AA .. A.A .... 'AA .. A.A .. A.'
8'-HL--------'---H-----'AA .. A.A •••• 'M .. A.A.A •• '
9' -HH--------' ---N-----' AA .. A. A•.•. 'AA .. A. AA •.. '
10' -----------, ---------, AHAAA. A.... 'AA .• A. A•••• '
II 'N----------, ---------, AA •• A. AHAAA 'AA •. A.A •••• '
12!L----------'---------'AA •• AM •••• 'AA •• A.A •.•. '
13! -----------1--------- ~ . , .. , . , .... ! •••••••••• , I
14 I -----------1--------- ~ ...... , .... ! • , ••••••••• I
IS!-----------!---------i ..... " .. " ! •••••• , ••• , I
161-----------! _________ I, •••• , •• , •• !, ....... , .. !
171-----------! _________ ! •. , •••• , •.• I,., ...•. ,.,!
lS!-----------I---------I .... ,., .... ! ••• " ••• , •. I
19! -----------! ---------! .. " ..•.... I . , .
I
20! ___________ I . ________ I ••••••••••• ! ..•.••.•.. I!
I
21 !--------.--! --------- ! ...........
•••••••
I ............ I
22!-----------'---------', ..... , ... ,! .......... , !
231-----------! _________ 1,., •••••••• !, .••.• , ...• !
DSSHNNNNN/I QQNFNDCBA
I!OIIlIlIRS NI I
__
1
R
ccccce
ec
OC C
FigUr~
NNQQNFNDCBA
/I NI I
6. Program Table
OC C
T
--~---
June 1988
536
Signetics
AN28
High-Speed 12-Bit Tracking AID
Converter Using PlS179
Application Note
Application Specific Products
INTRODUCTION
keep the input to the ADC from changing. The
DONE output may be used to control the
sample-and-hold if needed.
The general technique underlying the operation of this A/ D converter is illustrated by the
fuctional block diagram in Figure 1. The
system consists of a D/ A converter, a comparator circuit, and digital logic circuitry. The
digital logic circuitry outputs a digital vaue
which is converted to analog by the D/ A
The SAR keeps shifting to the right until the
digital output is less than the input. When the
output is less than the input, the SAR adds
one bit to the next MSB while keeping all the
higher order bits unchanged. For example, if
the current output is 0001 0000 0000 and the
output is less than the input, the SAR adds
one bit to the right at the next clock. The
output becomes 0001 1000 0000. The output
is again compared to the input. If the addition
of that one bit is too mUCh, it will be shifted to
the right until the output becomes less than
the input. When that happens, that SAR will
again add one bit to the right. The algorithm
of the SAR may be summarized as the
following: If the output is greater than the
input, shift to the right; otherwise add one bit
to the right. This process continues until all 12
bits have been operated on. The last bit (Bit
0) is always changed from a to 1, which is
used as the condition to set DONE to 1
which, in turn, sets open-collector output,
/DONE_OC, to O.
This paper discusses only the digital circuit
which contains the SAR and the Up/Down
Counter. The analog circuits are not within
the scope of this paper.
converter.
SAR
The comparator senses when the output is
greater or less than the input and causes the
digital circuit to decrement or increment its
digital output respectively. The initial conversion is completed in 13 clock cycles. If
tracking mode is used, the A/D converter
then tracks the input voltage as it changes by
incrementing or decrementing l-LSB per
clock. The tracking function makes it possible
to make an A/D conversion in one clock
cycle if the input changes less than the value
of l-LSB per clock period. The conversion
may be halted and the digital output, as well
as the converted analog output from DAC, will
hold their output constant indefinitely. This
feature works well as sample-and-hold since
its output voltage will not decay over time
whereas the output of an analog sample/hold
will decay due to charge leakages.
Two PLS179s are connected together to form
a 12-bit shift register and up/down counter.
The schematic diagram of the A/D converter
is shown in Figure 2. U2 contains bits a to 4
and Ul contains Bits 5 to 11. Interconnects
are made as shown in the diagram. The
digital output to the DAC is in natural binary
format (e.g. 0000 0000 0000 equal zero, and
1111 1111 1111 is full scale or 4095). After
theiST input becomes 0, at the rising edge of
the next clock, the SAR is initialized to halfscale (1000 0000 0000) and the DONE flipflop is reset to output 0 which causes the
open-collector output /DONE_OC to become
high impedance. The digital output is converted by the DAC and is compared to the analog
input voltage by the comparator. If the digital
output is greater than the analog input, the
SAR shifts the 1 to next MSB on the right.
The content of the SAR becomes (0100 0000
0000). If the digital output is still greater than
the input, the SAR shifts right one bit again.
The content of the SAR then becomes (0010
0000 0000). The shifting of 1 to the next MSB
in equivalent to reducing by half the value of
the bit under consideration. If the output is
still too large, the SAR reduces it by half
again by shifting to the right one more time.
In order to avoid the violation of setup time by
the output of the comparator, its output is
latched. There is a built-in 2-phase clock in
U2 which may be used to drive the logic
circuitry and the latch of the comparator (see
Signetics NE5105 data sheet for details on
output latches of voltage comparators).
The analog input voltage may be sampled
and held by an analog sample/hold circuit to
ST----I
TRACK---......~
HOLD---_-I
12·BIT SAR
AND
UP/DOWN COUNTER
UP/DOWN COUNTER
After DONE becomes 1, if /ST and /HOLD
are 1 and /TRACK is 0, the SAR turns into a
12-bit up/down counter. If the analog input
voltage increases, the counter will increment
by 1 at every clock until it matches the input.
If the input decreases, the counter will decrement by 1. When /HOLD becomes 0, the
counter is inhibited and the output is held
indefinitely. The counters consist of 12 toggle
flip-flops and 2 p-terms per flip-flop for directional control. The counter will operate only
1-----0..
DONE
I - - -......~
DONE_OC
I------t~ CLOCK 1
1 - - -__
ANALOG INPUT
, -_ _ _......,/
12~BIT
CLOCK 2
DATA OUTPUT
Figure 1. Functional Block Diagram of 12-Bil High-Speed A/D Converter
June 1988
537
Application Note
Signetics Application Specific Products
AN28
High-Speed 12-Bit Tracking AID Converter Using PlS179
TK
D
1
V
:!
START
1
,
R
+Vcc
22
I:
!;g-
PL$179
18
17
16
15
6
7
8
9
10
i.-.!
r---.!
I
V
10
'~c
l'
CLOCK 2
11
21
HLO
CLOCK 1
PLS179
2
5
,
6
,!-
20
19
18
17
16
15
11
Ul
U2
23
T
DONE-OC
DONE
MSS
12-81 T
DIGI TAL
OUTPUT
J
LATCH ENABLE
,( CLOCK 1
/.-~
LSS
COMPARATOR
LSB
MSS
12-BITDAC
V,N (ANALOG INPUT)
Figure 2. Schematic Diagram of 12-Bit High-Speed AID Converter
June 1988
538
Signetics Application Specific Products
Application Note
High-Speed 12-Bit Tracking AID Converter Using PLS179
after the approximation cycle is completed
and DONE is 1.
Since the 1ST and IHOLD inputs may be
asynchronous with the clock, in order to
minimize the possibilities of having a metastable condition from happening, these inputs
close-up are latched by flip-flops 1ST ART of
Ul and IHLD of U2 respectively. Once they
are latched, subsequent operation begins at
the rISing-edge of the next clock. The output
of the comparator may be latched to prevent
setup time violation. (Signetics NE5105 is a
high-speed comparator with an output latch.
External latch may be used with other comparators.)
CLOCKS
U2 generates an optional 2-phase clock
which may be used to control the latch of the
comparator. The two clocks are basically
180 0 out of phase and CLOCK2 has an
additional 25ns propagation delay behind
CLOCKI. CLOCK2 is used to drive the clockinputs of the PLS179 devices.
The clock frequency is controlled by Rand C.
Those who want to use the built-in clock
CLOCK 1
-l
r
uS
DONE AND IDONE_OC
The output DONE is reset to 0 when 1ST is O.
It remains 0 until the approximation cycle is
completed. After the least significant bit becomes 1, the DONE bit becomes 1 at the next
clock. It remains 1 until it is reset again by
Input 1ST.
The IDONE_OC output is configured to emulate an open-collector output. The output is
programmed to have a logic O. When DONE
is 0, the Tri-state output buffer is set to Hi-Z
condition. As soon as DONE equals 1, the Tristate buffer is enabled and IDONE_OC becomes o.
In the initial phase of AID conversion, 13
clock cycles are required. It is essentral that
the input voltage to the comparator remains
unchanged while the SAR is converting. It
may be necessary to have a samplelhold at
the front end. The DONE output may be used
to control the analog samplelhold circuit.
INPUT LATCHES
Flip-flop ISTART and 2 p-terms in Ul are
configured as a non-inverting D flip-flop. The
input, 1ST, and the output ISTART have the
same polaritres. Flip-flop IHLD and 2 p-terms
in U2 also form a non-inverting D flip-flop. The
output IHLD and the input IHOLD have the
same polarities.
AMAZE INPLEMENTATION
The implementation of the logic cirCUit using
AMAZE is as shown in the appendices. The
SAR circuit is first designed as a state machine (file name: ADCS.SEE). It is then partitioned into two PLS179s after proper pin
assignments are made. Then the upldown
counter, input latches, 2-phase clocks and
the open-collector output, are implemented
by using Boolean equations in their respective .BEE files (file names: ADCB1.BEE and
ADCB2.BEE) in AMAZE. The files are then
assembled to produce the fuse-maps of
PLS179 (ADCB1.STD and ADCB2.STD).
tpD $ 25n.
CLOCK 2
: Iw
-..
I
I
BITS 0-11
should experiment with RC time constants for
the best value. It is recommended that the
less than 1000pF to,
capacitance shouid
best results (see Ap Note AN13 for more
detail).
AN28
~ 1 CLOCK PERIOD
:
I
I
I
I
SUCCESSIVE APPROXIMATION
I
I
I
I
DATA VALID
I
I
DONE
I
I
i50NE~OC
lilt'
1'--1_ _ __
Figure 3. Timing Diagram of Successive Approximation Cycle
June 1988
539
Signetics Application Specific Products
Application Note
High-Speed 12-Bit Tracking AID Converter Using PlS 179
APPENDIX A: STATE EQUATIONS OF SAR
File Name:
ADeS
Date: 10/21/1986
Time:
11:2:14
@OEVICr=: SELECTION
ADCB I/PLS 1 79
ADCB2/PLS 1 79
@STATE VECTORS
[ ISTART, BIT11, BITIO, BIT9, BIT8, BIT7, BIT6, BIT5.
BITl, BITO, DONE]
INIT
HALFSCALE.
ST2048
8T1024
ST512
(I
----
----
-
- 1000 0000
1 1000 0000
-100 0000
--10 0000
0000
0000
0000
0000
0
0
0
0
8T256
ST128
8T64
8T32
8T16
STS
ST4
8T2
STl
----
"START CONVERSION PROCESS"
"SET SAR TO HALF SCALE"
"PRESENT STATE = 2048 (HALF SCALE)"
---1 0000 0000 0 b
---- 1000 0000 0 b
----------------
-100
--10
---1
----------
1 ----
ADI024
AD512
AD256
AD128
-
-1--
-
--1---1
AD64
-
AD32
AD16
ADS
AD4
AD2
ADl
END
SHI024
SH512
SH256
SH128
SH64
SH32
SH16
SHS
SH4
SH2
SHl
SHO
b
b
b
b
b
BIT4, BIT3, BIT2,
-
1--- - - - -1---1---1
-------------
01--01--01
---0 1--01--01--01
---0
0000 0 b
0000 0 b
0000 0 b
1000 0 b
-100 0 b
--10 0 b
---lOb
---------1---1---1---1
-
b
b
-
b
-
b
b
b
b
b
- b
- b
- b
1 b
-
b
-
b
b
---- ---- ---- -
b
b
b
1
b
b
b
1--01--01--01
---0
"ADD 1 BIT TO THE RIGHT"
"SHIFT ONE BIT TO THE RIGHT"
b
b
b
@INPUT VECTORS
[
COMPARE]
GREATER"" 1 b ;
LESS
= 0 b;
"IF DIGITAL OUTPUT IS GREATER THAN ANALOG INPUT.
"IF DIGITAL OUTPUT IS LESS THAN ANALOG INPUT ~ ••
@OUTPUT VECTORS
June 1988
540
~."
AN28
Signetics Application Specific Products
Application Note
High-Speed 12-Bit Tracking AID Converter Using PLS179
APPENDIX A: STATE EQUATIONS OF SAR (Continued)
~lAANSITIONS
WHILE [
INIT ]
IF [] THEN [ HALFSCALE]
WHILE [
5T2048 ]
"INITIALIZE REGISTER TO HALF SCALE"
IF [ GREATER] THEN [ SHI024 ]
IF [ LESS) THEN [ ADI024]
WHILE
WHILE
WHILE
WHILE
WHILE
WHILE
WHILE
WHILE
WHILE
WHILE
WHILE
June 1988
[
5T1024 ]
IF [ GREATER ] THEN [ SH512 ]
IF [ LESS J THEN [ AD512 ]
[ 5T512 ]
IF [ GREATER ] THEN [ SH256 ]
IF [ LESS ] THEN [ AD256 ]
[ 8T256 )
IF [ GREATER ] THEN [ SH128 ]
IF [ LESS ] THEN [ AD128 )
[ 5T128 ]
IF [ GREATER] THEN [ SH64 ]
IF [ LESS ) THEN [ AD64 )
[ 8T64 )
IF [ GREATER ] THEN [ SH32 ]
IF [ LESS ] THEN [ AD32 ]
[ 5T32 ]
IF [ GREATER ] THEN [ SH16 ]
IF [ LESS ) THEN [ AD16 ]
[ 8T16 J
IF [ GREATER] THEN [ SHe]
IF ( LESS ] THEN ( ADS ]
[ STa )
IF [ GREATER) THEN [ SH4 ]
IF [ LESS ) THEN ( AD4 )
[ ST4 ]
IF [ GREATER ] THEN [ SH2 ]
IF [ LESS ) THEN [ AD2 )
[ ST2 )
IF [ GREATER ] THEN [ SHl ]
IF ( LESS) THEN [ ADi )
( STl )
IF [ GREATER ] THEN [ SHO ]
IF [) THEN [END)
541
IF GREATER THAN, SHIFT 1 BIT"
"IF LESS THAN, ADD 1 BIT"
H
AN28
Signetics Application Specific Products
Application Note
High-Speed 12-Bit Tracking AID Converter Using PlS179
APPENDIX B: PIN LISTS
Fil e Name : ADC82
Date: 10/21/1986
Time: 10:58126
**...*......# •••UUUUUUUt
LABEL
CLOCK
/START
COMPARE
**
**
PIN
L I S T . . . . . . . . . . . . . . . . . . . . . . ..
---------
FNC **PIN
1-;
CK
:-23
1-22
3-:
tHOLD
ITRACK
4-1
p
5-;
L
S
I
6-:
BITS
7-'
N/C
N/C
N/C
RC
I
I
IB
CLOCK 1
GND
0
OV
**
**
**
**
PIN** FNC
:-24
2-'
I
a-;
7
9-\
10-:
9
;-21
1-20
1-19
:-18
\-17
\-16
'-15
:-14
:-13
11-\
12-:
**
**
**
**
**
**
**
**
**
**
**
**
**
LABEL
+5V
**vee
IB
**/DONE - DC
**N/C
B
0
0
0
0
0
0
0
10
**/HLD
**BIT4
**BIT3
**BIT2
**BITt
**BITO
**DONE
**CLOCK2
IDE **N/C
File Name: ADCBl
Date: 10/21/1986
Time:
10:53:7
••••••••••••••••••••• P I N
LABEL
CLOCK
1ST
COMPARE
IHLD
ITRACK
BIT4
BIT3
B1T2
BITI
BlTO
DONE
GND
June 1988
**
**
L I S T . . . . . . . . . . . . . . . . . . . . ..
---------
FNC **PIN
CK
1-:
I
I
3-1
4-1
I
I
5-:
I
6-:
I
7-:
I
8-:
I
9-:
I
10- :
I
11-:
OV
12-:
PIN** FNC
:-24
2-'
:-23
:-22
P
L
S
I
7
9
542
:-21
:-20
;-19
:-18
:-17
:-16
:-15
:-14
:-13
**
**
**
**
**
**
**
**
**
**
**
**
LABEL
+5V
**vee
IB
0
0
0
0
**N/C
**/START
**BIT11
**BIT10
**BIT9
0
**BIT8
0
**BIT7
0
**BIT6
0
**BlT5
IS **N/C
IDE "*N/C
AN28
Signetics Application Specific Products
Application Note
High-Speed 12-Bit Tracking AjD Converter Using PLS179
APPENDIX
c:
AN28
BOOLEAN EQUATIONS OF UP/DOWN COUNTER AND INPUT LATCH
File Name , ADCBl
D.te : 10/21/198b
Ti_ , 10:54,4S
.DEVICE TYPE
PLS179
.DRAWING
IIREVISION
.DATE
.SYMBOL
FILE NAME
ADCBl
@COI'IPAblY
@NAME
@DESCRIPTION
@COMMON PRODUCT TERM
@COMPLEMENT ARRAY
@I/O DIRECTION
@OUTPUT POLARITY
@FLIP FLOP CONTROL
Fe
=
1 ;
"SET ALL FLIP FLOP TO BE J/K"
@OUTPUT ENABLE
@REGISTER LOAD
@ASYNCHRONOUS PRESETIRESET
@FLIP FLOP MODE
@LOGIC EQUATION
"NON-INVERTING INPUT LATCH: ISTART
1ST "
START : J = ST;
K = 1ST ;
"UP/DOWN COUNTER ROUTINE"
IBITS : T = /START * TRACK * DONE * /HLD * COMPARE * IBITO * IBITt
IBIT2 * IBIT3 * IBIT4 +
1ST ART * TRACK * DONE * IHLD * ICOMPARE * BITO * BITt
BIT2 * BIT3 * BIT4 ;
IBITb
T
ISTART * TRACK * DONE * IHLD * COMPARE * IBITO * IBITt
IBIT2 * IBIT3 * IBIT4 * IBITS +
ISTART * TRACK * DONE * IHLD * ICOMPARE * BITO * BITt
BIT2 * BIT3 * BIT4 * BITS;
IBIT7
T
ISTART * TRACK * DONE * IHLD * COMPARE *
IBITO * IBITI * IBIT2 * IBIT3 * IBIT4 * IBITS * /BITb +
ISTART * TRACK * DONE * IHLD * ICOMPARE *
BITO * BITt * BIT2 * BIT3 * BIT4 * BITS * BITb ;
IBITS
T - ISTART * TRACK * DONE * IHLD * COMPARE * IBITO * IBITt
IBIT2 * IBIT3 * IBIT4 * IBITS * IBITb * /BIT7 +
ISTART * TRACK * DONE * IHLD * ICOMPARE * BITO * BITt
IBIT9
IBITtO
T
BIT2 * BIT3 * BIT4
1ST ART * TRACK * DONE
181T2 * IBIT3 * 18IT4
ISTART * TRACK * DONE
BIT2 * BIT3 * BIT4
T - ISTART * TRACK * DONE
IBIT2 * IBIT3 * IBIT4
IBIT9 +
ISTART * TRACK * DONE
BIT2 * BIT3 * BIT4
BIT9 ;
IBIT11 , T - ISTART * TRACK * DONE
IBIT2 * IBIT3 * IBIT4
IBIT9 *
IBITI0 +
ISTART * TRACK * DONE
BIT2 * BIT3 * BIT4
BIT9 * BITtO ;
June 1988
543
*
*
*
*
*
*
*
BITS * BITb * BIT7 I
IHLD * COMPARE * ISITO * IBITt
IBITS * IBITb * IBIT7 * IBITS +
IHLD * ICOMPARE * BITO * BITt
*
**
BITS * BITb * BIT7 * BITS;
IHLD * COMPARE * IBITO * IBITI
IBITS * IBITb * IBIT7 * IBITS *
*
*
IHLD
*
*
*
*
*
*
*
*
*
*
BITS
ICOMPARE
*
BITb
*
*
BITO
BIT7
*
*
BITt
BITS
*
BITO * BITt
BIT7 * BITS
*
*
IHLD * COMPARE * IBITO * IBITI
IBITS * IBITb * IBIT7 * IBITS *
IHLD * ICOMPARE
BITS * BITb *
*
*
*
*
Signeties Application Specific Products
Application Note
High-Speed 12-Bit Tracking AID Converter Using PLS179
APPENDIX
c:
AN28
BOOLEAN EQUATIONS OF UP/DOWN COUNTER AND INPUT LATCH (Continued)
Fi Ie Name
I
ADCB2
Date I 10/21/1986
Time: 10:58:56
@DEVICE TYPE
PLS179
.DRAWING
.REVISION
@DATE
@SYM80L
FILE NAME
ADCB2
@COMPANY
@NAME
@DESCRIPTION
@COMHON PRODUCT TERM
@COMPLEMENT ARRAY
DIRECTION
DO = Re ;
"Re OSCILLATOR"
03 "'" DONE ;
"ENABLE tDONE_DC TO OUTPUT A LOGIC LOW~"
@OUTPUT POLAR I TV
@FLIP FLOP CONTROL
Fe = 1 ;
@OUTPUT ENABLE
@REGISTER LOAD
@ASVNCHRONOUS PRESET IRESET
@FLIP FLOP MODE
"1'10, 1'11, 1'12, 1'13, M4, MS -= 1 ;
SET FO - F5 TO J/K FLIP FLOPS."
@I/Q
@LOGIC EpllATlON
I'NON-INVERTING INPUT LATCH:
HLD
:J=
HOLD;
IHLD = /HOLD "
K = tHOLD ;
"UP/DOWN COUNTER ROUTINE"
T
1ST ART
TRACK
IBITl
T
1ST ART
TRACK
ISTART
TRACK
IBIT2
T
ISTART
TRACK
ISTART
TRACK
IBIT3
T
ISTART
TRACK
*
*
*
IBITO
..
,
,
8IT2
*
BIT2
*
IBIT4
,
IDONE_OC
T
*
*
*
*
*
*
IHLD
IHLD
IHLD
IHLD
IHLD
IHLD
DONE
IHLD
DONE
*
*
DONE
*
*
*
TRACK
ISTART
*
TRACK
*
*
BIT3 +
ISTART
*
TRACK
*
ICOMPARE
COMPARE
ICOMPARE
COMPARE
ICOMPARE
IHLD
*
*
*
*
*
*
*
ICOMPARE
*
*
*
*
*
*
*
IHLD
*
COMPARE
*
COMPARE
BITO +
IBITO ;
BITO * BITl +
IBITO * IBITl ;
BITl
BITO *
IBITl
BITO
*
*
IBITO
*
IBITl
IBITO
IBIT3 ;
/( 1 )
"RC OSCILLATOR"
RC
1(1)
CLOCK!
RC ;
-= I ( CLOCK1 )
CLOCK2
June 1988
DONE
DONE
DONE
DONE
DONE
DONE
ISTART
BIT2 +
BIT2
*
*
*
*
*
*
"BUILT-IN DELAY OF 1 tPD"
544
BITl
·
·
•
I
•
I
Signetics Application Specific Products
Application Note
High-Speed 12-Bit Tracking A/D Converter Using PLS179
AN28
APPENDIX D: U1 ADCB1 FUSE MAP
File Name: ADCBl
Date: 10/21/1986
Time : 10:56:5
Cust/Project Date
Rev/I. D.
E(b)=
F/F TYPE
PLS179
E(a) =
POLARTY
T '
i\;-i\;-i\;-i\;-i\;-i\;-i\;-i\ 0
0
L:L:L:L
E ,------------------------------------------------------------------
R
!
! BU)
!
GHp)
Q(n)!
SCo)
M!C!----------------------------------------------------------------
___ !_!7_b_5_4_3_2_1_0!3_2_1_0!7_b_5_4_3_2_1_0!7_6_5_4_3_2_1_0! 3_2_1_0 !
O!A!- - - -,- - - L!- - - _ 1 - - - - , - - - -!H - - -,- - - -!A A A AI
l!A!,
- H!- - - _ 1 -,- -!L - - -,- - - -!A A A A!
2!A!L
3!A!H
4!A!L
5!A!H
6!A!L
7!A!H
8!A!L
9!A!H
10!A!L
11!A!H
12!A!L
13!A!H
14!A!L
15!A!H
Ib!A!17!A!L
18!A!L
19!A!L
20!A!L
21!A!L
22!A!L
23!A!L
24!A!L
25!A!L
2b!A!L
27!A!L
28!A!L
29!A!L
30!0!0
31!0!0
Fc!A!Pb!.!O
Rb!.!O
Lb!.!O
Pa!.!O
Ra!. !O
La! .. !O
D3!.!0
D2!.!0
Dl!.!O
DO!.!O
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L L
H
L
H
L
H
L
L
L
L
L
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L,L H H _ 1 - - H L!L - - -,- - - _ 1 - - - - , H,L H L _ 1 - - H H!L
-,- - - _ 1 -,L,L H H _ 1 - - H L!L
-,- - - H~-,H~L H L _ 1 - H H~L
-,- - - L!-,L,L H H
- H L~L
-,- - H H!-,H,L H L _ 1 - - H H!L
-,- - L L!,
L,L H H _ 1 - - H L!L - - -,- H H H!- - - -,0
H,L H L _ 1 - - H H!L
, L L L!-,0
L,L H H _ 1 - - H L!L - - -,H H H H!- - - 0,H,L H L _ 1 - - H H!L - - -,L L L L!- - - 0,L,L H H _ 1 - - H L!L
H,H H H H!- - 0 -,H,L H L _ 1 - - H H!L - - L,L L L L!- - 0 -,L,L H H _ 1 - - H L!L - H H,H H H H!- 0 H,L H L _ 1 - - H H!L - L L,L L L L!- 0 - ,
,
- _ 1 - - - -!H ,
- _ 1 - L H H,H
L,- - H _ 1 - - L L!L L H H,H H H H!- H L -,L,- - L _ 1 - - L L!L L H H,H H H H!- - L ,
L,- - H _.- - L L!L - L H,H H H H!- - H L,L,- - L _ 1 - - L L!L - L H,H H H H!- - - L,L,- - H _.- - L L!L - - L,H H H H!- - - H,L
L,- - L _ 1 - - L L!L - - L,H H H H!-,L
L,- - H _ 1 - - L L!L - - -,L H H H!- - - -,H
L,- - L _ 1 - - L L!L - - -,L H H H!- ~
L,- - H _ 1 - - L L!L - - -~- L H H!-,L,- - L _ 1 - - L L!L - - -,- L H H!- - - -,L,- - H _ 1 - - L L!L - - -,- - L H!- - - -,L,- - L _ 1 - - L L!L
-,- - L H!- - - -,L,- - H _ 1 - - L L!L
, - - L!- ,
0,0 0 0 ~!O 0 0 O!O 0 0 0,0 0 0 O!O 0 0 0,0
0,0 0 0 O!O 0 0 O!O 0 0 0,0 0 0 O!O 0 0 0,0
L
L
L
L
L
L
L
0 0
0 0
,
0 0 0,0
0 0 0,0
0 0 0,0
0 0 0,0
0 0 0,0
0 0 0,0
0 0 0,0
0 0 0,0
0 0 0,0
0 0 0,0
B B B B /
o
,
o
o
o
o
o
o
o
o
0 0'0 0 0 O!O 00 0,0
0,0
0 O!O 0 0 O!O 0 0 0,0
0 O!O 0 0 O!O 00 0,0
0 O!O 0 0 O!O 00 0,0
0 O!O 0 0 O!O 00 0,0
0 O!O 0 0 O!O 00 0,0
0 O!O 0 0 O!O 00 0,0
0 O!O 0 0 O!O 00 0,0
0 O!O 0 0 O!O 0 0 0,0
1
C
o 0 O!O 0 0 O!O 00
1 1·1 I·T·H
1
o·s
-
-
-
-
0
Q
-
0
0
-
- - H H
- - L
L
H
0
0
L
L
H
0
0
O!A A A
O!A A A
-~A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
H!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
-!A A A
L!A A A
L!A A A
H!A A A
O!A A A
O!A A A
A!
A!
A~
AI
AI
AI
AI
A!
A!
AI
A!
A'
A!
A!
A!
A~
A!
A!
A!
A!
A!
A!
A!
A!
A!
A!
A!
A!
A!
A!
0 0 O!
0 0 O!
0 0 O!
0 0 O!
0 0 O!
0
0
0
0
0
°0 O!O!
0 O!
0 O!
0 O!
N N D B / B B B B B B BIB BBBBBBNNDB
1 rU·l
srITTlrl·S·I I r:r
1 T
I·"'-ro
1
T T T T R L H Tee N T T T T T T T T T T T T T T T T Tee N T
EO
1234ADP
EO A l l 9 8 7 6 5 A 1 198765
C
A
RIO
R 1
K
R
T
T
E
June 1988
545
o
Application Note
Signetics Application Specific Products
High-Speed 12-Bit Tracking AjD Converter Using PLS179
AN28
APPENDIX D: U2 ADCB2 FUSE MAP (Continued)
File Name = ADCB2
Date , 10/21/1986
Tillie:
11:0:7
Cust/Pr-oject Date
Rev/I. D.
PLS179
T
E
~
F/F TYPE
E(b)=
E(a) =
POLARTY
--------------- 0
0
LoL,H,L
!--------------------------------------___________________________
_
'A,A,A,A,A,A,A,A
!
! !
! B---1-
.-
-
-- .-
1---I--
(x4)
----~s_o
----
-------
- -
.- . -
-72
- - .- .....
Figure 3. PLHS501 Logic Diagram
June 1988
I/O
549
Signetics Application Specific Products
Application Note
PlHSS01 Programmable Macro logic Primer
AN29
Figure 5 illustrates how' RS' and 'D' latches
are implemented in the PLHS501.
Another eminent application of the PLHS501
is in generating asynchronous state machines.
.,
0,
The blend of internal feedback paths together
with the abundant number of gates makes
this device suitable for designing asynchronous state machines which employ propagation delays of feedback paths as memory
elements as shown in Figure 6. (See Reference 2.)
0,
TOP VIEW
Figure 4. PLHSS01 Pin Assignments
s-++-R-++-INPUT
D--S~a--DOUTPUT
INPUT D - -
R~a--DOUTPUT
0-++-----'
a. RS Latch
D---------~~~---
B-+++-+------'
INPUTo-- 0 - - - - -.....--rl~--==~
a
INPUTD--
LE
---t:~===--------.:J
-++-Hf-----'
c-+++-+------'
A-+++-+--__--'
b. D Latch
Figure 5. RIS and D Latch Implementation with PML
June 1988
550
Signetics Application Specific Products
Application Note
PLHS501 Programmable Macro Logic Primer
,
INPUT 0
INPUTn
PRES ENT
S TATE
graphs briefly explain the implementation of
PML in the AMAZE structure.
I
•
•
OUTPUT 0
•
•
·
..
~
·
COMBINATIONAL
LOGIC
OUTPUTm
3. Schematic To Boolean Converter (STBC) .
1. BEE accepts user defined logic in the form
of boolean equations and produces an
AMAZE standard fuse file. The boolean notation in BEE will account for the following PML
features.
~
NE XTSTATE
yp
Yp
PROPAGATION DELAY
Figure 6. Model of Asynchronous State Machines Using Propagation
Delays 01 the Feedback Path as Memory Elements
PML DEVELOPMENT
SOFTWARE
Programmable logic development software
has become an integral part of the PLD
design process. Without software tools PLDs
become perplexing devices which are inconvenient to use. Development software enables the user to take full advantage of the
programmable logic's resources. The complexity of the PML devices makes software an
indispensable element in the design process.
The AMAZE PLD design software, as noted in
Reference 3, has been developed for
Signetics programmable logic devices. PML
1. Boolean Equation Entry (BEE).
2. State Equation Entry (SEE).
···
PROPAGATION DELAY
BLAST
The basic elements of BLAST are:
f------
r-;-
AN29
design and development will be fully supported by AMAZE. Figure 7 shows the AMAZE
configuration for supporting PML. The structure of the software is based on the following
modules:
.BLAST (Boolean Logic And State Transfer entry)
DPI
(Device Programmer Interface)
.SIM
(PLD functional SIMulator)
.PI
(PML Integrator)
The foundation for the above modules is an
AMAZE standard fuse file (STO). The STO file
is the common means of communication
between all the modules. The following para-
LOGIC
SIMULATOR
a. The single array architecture provides an
option to specify the number of logic (gate)
levels that accommodate a specified function.
The number of gate levels dictate the delay
between the inputs and outputs. The number
of logic levels for each function can be
specified using the following notation:
LABEL [ number of logic levels 1 = equation;
where LABEL is the user designated name of
the output pin.
b. Some outputs have more than one gate
associated with them (for example registered
or EXOR outputs). The input SIDE of these
outputs can be specifically defined. For example:
Pin Label: R
= eqn;
S = eqn;
c. User definable CLOCK Logic (e.g. as in the
PLHS502) can be specified.
d. For PML devices the Sum-of-Products
(SOP) can be defined as common terms.
BOOLEAN EQUATION
ENTRY
PML
STATE EQUATION
ENTRY
INTEGRATOR
DEVICE PROGRAMMER
INTERFACE
SCHEMATIC TO
BOOLEAN CONVERTER
BLAST
Figure 7. AMAZE Configuration for PML
June 1988
551
Signetics Application Specific Products
Application Note
PLHS501 Programmable Macro Logic Primer
2. SEE accepts state machine definitions and
produces the AMAZE standard fuse file. Particularly, SEE will include asynchronous state
machine implementations utilizing the
PLHS501.
3. STBC converst schematic netlists produced by CAD systems such as Futurenet™,
Daisy, and Mentor into an AMAZE BEE file.
STBC will fully embody the PML in the following manner:
a. De Morgan's theorem is applied to produce
equations in SOP form. All the functions in
SOP form are then converted into their
NAND- NAND equivalent.
b. The converter will determine the polarity
and the number of levels in each equation
and will automatically determine the correct
output polarity.
PI
The PML Integrator is a conversion that
transforms various PAL ™ or PLD circuits into
a PML device. It will automatically fit multiple
PAL™ /PLD devices into a single PML. It is
capable of automatically receiving patterns
from a commercial device programmer and
downloading it back to the programmer after
the PML transformation. The implementation
of an 'Integrator' will allow the automatic
conversion of numerous PALrM/PLDs into a
single PML device.
AMAZE will not be the total extent of development software available for the PML devices. The task of implementing PML design
software is already underway by a number of
different vendors of CAD software.
PLHS501 DESIGN EXAMPLE
DPI
Device Programmer Interface provides the
interface between the AMAZE standard fuse
file and a commercial programmer. It allows
the transmission of data to and from the
device programmer.
SIM
The functional simulator uses the AMAZE
standard fuse file in the following manner:
a. An event driven simulator will assess the
delays within the PML in order to properly
simulate the pattern.
b. Automatically generates test vectors for
the pattern simulation.
June 1988
The following example intends to manifest
the capabilities of the PLHS501. Figure 8
shows a system formed with TTL logic. The
system requirements make it imperative only
to use discrete asynchronous latches. Thus,
none of the 7 latches in the system can be
directly replaced by registers. The system
diagram is drafted using Futurenet™ DASH-2
Schematic Designer. The system is partitioned into two PLS173s and one PLS153. In
order to convert the system into its targeted
PLD's, the PINLIST (see Figures 9a-9c) has
to be defined. Using the AMAZE PIN-LIST
editor, the specified PLD's are labeled with
the same labels as those on the system
schematic (Figure 8). After the declariltion of
labels, AMAZE automatically converts the
system to the designated PLDs. The AMAZE
552
AN29
generated boolean equation files are shown
in Figures 9a, 9b, and 9c. Figure 10 shows
the overall system implemented with PLDs.
The logic condensation capabilities of PML
makes it feasible to replace the whole system
by a single PLHS501 (Figure 11). The
PLHS501 in this design will still have ample
space for any future additions.
The above example demonstrates only part
of the PLHS501 capabilities. The introduction
of PM L devices and their immense logic
power will pave the way for a new generation
of efficient and elegant systems.
REFERENCES
1. Cavlan, Napoleone 1985. "Third Generation PLD Architecture Breaks AND-OR Bottleneck", WESCON 1985 Conference Proceedings.
2. Wong, David K. "Third Generation PLS
Architecture and its Applications", Electro
1986 Conference Proceedings.
3. "1986 PLD Data Manual", Signetics Corporation.
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Application Note
Signetics Application Specific Products
PlHS501 Programmable Macro logic Primer
AN29
File l>Jame : PARTI
12/10/1986
Date
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June 1988
555
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Signetics Application Specific Products
Application Note
PLHS501 Programmable Macro Logic Primer
AN29
File Nama: PART?
Date
12/10/1986
Time
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June 1988
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557
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Application Note
Signetics Application Specific Products
PLHS501 Programmable Macro Logic Primer
AN29
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June 1988
560
Signetics Application Specific Products
Application Note
PlHS501 Programmable Macro logic Primer
AN29
I
l
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June 1988
561
Designing with Programmable
Macro Logic
Signetics
Application Specific Products
The obvious extensions to additional combi-
INTRODUCTION TO PMl
DESIGN CONCEPTS
Programmable Macro Logic, an extension of
the Programmable Logic Array (PLA) concept
combines a programming or fuse array with
an array of wide input NAND gates wherein
each gate folds back upon itself and all other
such NAND gates. This is called a foldback
NAND structure and its basic elements have
been outlined previously (Cavlan " Wong2 ,
Gheissari and Safari3 ).
The choice of an internal NAND logic cell is
appropriate because the cell is functionally
complete, requiring but a single cell type to
generate any Boolean function. A cell within
the PLHS501 may be configured to accommodate from one to 32 inputs from the
outside world, and up to 72 inputs from within
the chip. Because the user can select either
direct or inverted input variables, and either a
direct or complemented output, the NAND
function can generate, with a single pass
through the programming array, the basic four
logic functions of AND, OR, NAND, NOR. All
these basic functions, can be extremely wide,
of course (see Figure 1.1). This convenient
structure allows efficient exploitation of all
widely used minimization techniques (Karnaugh Maps, Quine-McCluskey, Boolean Algebra, etc.).
A
IA~
national functions for decoding, multiplexing
and general Boolean functions is straightforward. Adding feedback to the system expands the range of realizeable functions to
include sequential as well as combinational
functions. Figure 1.2 illustrates the basic
arrangement of the PLHS501. Because of the
large number of inputs each NAND gate has
available, logic functions that require several
levels of conventional 4 or 8 input gates may
be able to be reduced to 1 or 2 levels.
However, it is important to realize that unlike
AND-OR PLD architectures, more than 2
levels of logic may be implemented in the
PLHS501 without wasting output or input
pins. Up to 72 levels of logic may be implemented due to each of the 72 foldback NAND
gates.
So far, the concept of a "macro" is still not
evident. Two ways for the generation of a
macro exist - namely, hard and soft. Borrowing from the concept in computer programming wherein a section of code (called a
macro) is repeated every time its use is
required, we can establish subfunctions
which can be repeated each time required.
The user defined or soft macro can be one
which will generate a function by fused interconnect. When a fixed design function is
provided, it is a hard macro. This may be an
optimized structure like a flip-flop or an adder,
__.z
~~
B,
(OR)
'Z'.
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,
A
z
:
I
INI'\JT
IIECTION
(NOR)
p----t>;_
:
(AND)
I
NAND_Y
OUTPUT
semON
Figure 1.1 PML Basic Functions
June 1988
Optimizing combinational functions in PML
consists largely in making choices and tradeoffs. For single output logic functions, the
choice is obvious from the truth table. If a
particular function's truth table has fewer
entries that are logical zeroes than logical
ones, product of sums should be chosen and
the appropriate OR-AND structure generated.
Otherwise, the usual sum of products should
be chosen, minimizing as usual, before dropping into the two level AND-OR structure
(using the NAND-NAND realization). Combining the availability of inversion at the input
and output of the chip, the NAND-NAND
structure can perform either the OR-AND or
the AND-OR rendition of a function with equal
ease, using precisely the same number of
logic levels. The designer needs only to
choose the optimal rendition to suit his needs
(see Table 1.1). Truth tables with 50% ones
can use either version at the designers whim
unless other uses arise.
PERFORMANCE
:p--t>;-+Z
'Z"
When a user function for a particular use is
isolated, defined and repetition of the function
is required, special software constructs are
provided which will allow it to be defined as a
soft macro and effiCiently replicated. For
higher performance and functional density, an
array of choices which contain optimized
functions or hard macros will be offered in
successor chips. In particular, the PLHS502
(described in Section 4) will include an array
of flip-flops for high performance state machine design.
(NAND)
B ,
z'
rzVi=
or some other function which is generated on
the foundation, by the manufacturer. Soft
macros are seldom optimized or precisely
consistent, but hard macros are both optimized and unalterable.
562
The PLHS501 (Figure 1.2) is a high speed,
oxide isolated, vertically fused PML device
containing 72 internal NAND functions which
are combined with 24 dedicated inputs, 8
bidirectionals and 16 dedicated outputs. A
large collection of applications, both combinational and sequential, may be configured
using this part which looks roughly like a
small, user definable gate array. For the sake
of clarity, worst case passing a signal from an
input, making one pass through the NAND
array (output terms) and exiting an output
takes around 25 nanoseconds with each
incremental pass through the NAND foldback
array taking about 8 nanoseconds.
Signetics Application Specific Products
Designing with Programmable Macro logic
TABLE 1.1 EXAMPLE DEMONSTRATION
F1 (A, B, C) =ABC + ABC- + ABC- + ABC + ABC
\ AB
ABC
11
C\
00
01
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
10
0
I
I
0
0
11
0
0
I
I
I
The optimal choice would be to generate
the zero entries.
0
II we group on the one entries we shall get: F1 = AB-
+ BC + BC
gct ••
L
-J
INPUTS
B
c
L-J
NAND ARRAY
L
-J
OUTPUT
II we group on the zero entries we get instead: F 1
=(B + C) (A + B + C)
F1 (A.B.O
L
-J
OUTPUT
June 1988
563
Signetics Application Specific Products
Designing with Programmable Macro logic
Input
BUTfers
10
-;:::-
D--i
··· ···
72
Output
NAND
terMS
terMS
83-L2
-
Input
B~rs
[-
'~>-
"Lf
Output
Buffers
June 1988
564
rO/
1-0
BO-3
-Ds lO-7
H1>- f--ox
l'
Figure 1.2 PlHS501 logic Diagram
4
4
0- 7
.....
~O 0-3
-G 04-7
Signetics Application Specific Products
Designing with Programmable Macro Logic
The data sheet first lists some maximum
J,JI upagation delays from an input, through a
NAND output term and out through various
output gates. Secondly, it lists maximum
propagation delays from an input, through a
NAND foldback term, through a NAND output
term and out through the different output
gates.
It is intriguing that subtracting one from the
other yields a N.AND foldback gate delay of 5
to 6ns when the worst case gate delay of an
internal foldback gate is listed as 8ns. This is
due to the fact that a gate has less of a delay
when it's output is falling (tPHL) than when
it's output is rising (tPLH). When passing a
signal through two NAND gates one gate will
have less of a delay than the other, and since
the individual rise and fall delays are not
specified, this causes the apparent discrepancy between the two delays.
Figure 1.3, Figure 1.4, Figure 1.5 and Figure
1.6 show graphically the timing paths listed in
the PLHS501 data sheet.
PLHS501 TIMING
tpd3
A
Input
Buffers
10
r---
D-H;>
··· ···
'-i;>
Ft-
72
Output
NANO
terns
terMS
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QQ
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4
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Output
Buffers
NOTES:
tpd3 = 22ns maximum.
Input Buffer + 1 NAND gate + Output Buffer (0, /0,8).
Figure 1.3 tpd3 -22ns Maximum
June 1988
565
,...,
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~O 0-3
,.:,
tpd3
04-7
Signetics Application Specific Products
Designing with Programmable Macro logic
PLHS501 TIMING (Continued)
Buffers
Ie
---:--
0:--1
· ···
·R;--i
-
72
Output
NRND
terMS
t.",P'\
.?
Input
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/
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":
~
72
QQ
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J)
)-
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11
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1f
-D 04-7
Output
Buffers
NOTES,
tpo4 = 30ns maximum.
Input Buffer + 2 NAND gate + XOR gate + Output Buffer.
Figure 1.4 tpo4 -30ns Maximum
June 1988
566
I.j.
.....
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Signetics Application Specific Products
Designing with Programmable Macro Logic
PLHS501 TIMING (Continued)
tpol
f
'
, > , , , > > , , ) ) , >
Input
BuFfers ,..---.....,
10
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...------------t,f------.
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D-H';>'
··
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/
72
Output
NRNO
terMS
tar"1"'16
~+;-+--;-4+_+--r__r--r-_r--r_"/rr--r-~
~--~~?~+-+--+-++-+-~~~~---r--+-~~./~-+--1-
Input
B;:!!!rs
'---
1<; ~
'r
IS.J
72
"t.("
-Do 0-3
~
If
Output
Buffers
NOTES,
tpc 1 "" 25ns maximum.
Input Buffer + 1 NAND gate + XOR gate + Output Buffer.
Figure 1,5 tpo1 -25ns Maximum
June 1988
567
~
04-7
Signetics Application Specific Products
Designing with Programmable Macro Logic
PLHS501 TIMING INTERNAL
t
Input
Buffers
10
-
D---i
··· ···
8;---i
-
72
NAND
te,. ..
;;>
I'D
,
,
,
,
,
,
,
,
7
Output
terMS
Input
Buffers
,
,
,...--
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,
,
t
PO
7
~
72
,
t+-
:-
'--
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~/
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-tr i-Do
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L.f
BO-3
~
0-7
0-3
04-7
Output
Buffers
NOTE:
tpo 7 = ens maximum.
L-_____________________________________________________________
Figure 1.6 tpD7 -8ns Maximum
June 1988
568
~
Signetics Application Specific Products
Designing with Programmable Macro Logic
NAND GATE FLIP-FLOPS
Various types of f!!p-f!ops and latches may be
constructed using the NAND gate building
blocks of the PLHS501. A typical 7474 type of
edge-triggered D flip-flop requires 6 NAND
gates as shown in Figure 1.7.
No additional gates are required to implement
asynchronous set and reset functions to the
flip-flop. The equations necessary for AMAZE
to implement the D flip-flop are shown in
Figure 1.8. However, please note that the
equations of Figure 1.8 define a D flip-flop
configured as a divide by 2 (i.e., ON is
connected to the data input) whereas Figure
1.7 shows a general case. Also note that flipflops with some additional features may be
constructed without using more than the six
NAND gates. This is possible because of the
large number of inputs associated with each
NAND gate. For instance, a flip- flop may be
required to have a clock gated by one or
more signals. Using the PLHS501, it may be
implemented by adding additional input signal
names to NAND gate equations of gates # 2
and #3 of Figure 1.7. If the data input is to
the AND of several signals, extra inputs to
NAND gate #4 may be used. Or if additional
set or reset lines are required, they may be
added simply by using more of the inputs of
each NAND gate connected to the main set
or reset.
Figure 1.10 shows two simulations of the
same flip-flop. The first one is at a little less
than maximum frequency, for clarity in following the waveforms, and the second is at the
maximum toggling frequency. For these simulations each NAND gate has a maximum tpHL
or tpLH of 8nsec (which is the gate delay of a
NAND gate in the PLHS501's fold back array).
First of all, it can be seen from these simulations that for proper simulation or testing of
such a device a set or reset input is mandatory. Both 0 and ON outputs are unknown no
matter what the inputs do, until they are put
into a known state by either a set or reset
input. Secondly, various timing parameters
such as propagation delay, as well as setup
and hold times may be determined. For the
generai case, referring to Fiyui'e 1.7.
Tsetup ~ tpd4 + tpd1, Thold ~ tpd3 +
tpd4 and Clock to 0 = tpd3 + tpd6 + tpd5.
Therefore, performance of the flip-flop depends a great deal on which gates in the
PLHS501 are used, either NAND gates in the
fold back array or output NAND gates, connected to bidirectional pins. As a test of the
simulation, a D flip-flop connected as a divide
by 2 was constructed using only the foldback
NAND terms (see Figure 1.8). An output
NAND term was used to invert the ON output
and drive an output buffer. The only inputs
were the clock and a reset. The data input to
the flop was driven internally by the ON
output. According to the simulation, it was
possible to drive the clock at a frequency of
25Mhz and this small circuit also functioned
at that frequency.
t>--.......-r'lQ
"'-""""1
J
RESETNI[)----HH~~~--------~
CL0 CKD--f~--I
ORTRD--------I~~
Figure 1.7 Edge Triggered 0 Flip-Flop
June 1988
569
Signetics Application Specific Products
Designing with Programmable Macro logic
II##UII#H#### PIN
Left
LABEL
vec
N/C
N/C
N/C
N/C
CLl<
RST
N/C
N/C
N/C
N/C
N/C
GND
LIS T ######I####IIU
Right
LABEL
FNC **PIN
PIN** FNC *'"
1-46 ** TSV **VCC
+5V
8-1
9-1
1-45
**N/C
I
10-1
1-44
**N/C
*' I
P
1-43
I
I
11-1
* "'N/C
L
1-42 •• I
**N/C
I
12-1
1-41
I
13-1
H
**N/C
1-40 ** /0 **N/C
14-1
S
1'-39 ** /0 **N/C
15-1
5
1-38 ** /0 **N/C
16-1
1-37
17-1
I
** /0 **00
•• I
**NjC
18-1
1-36 •• 0
•• 0
1-35 *'0
19-1
**N/C
20-1 _ _ _ 1-34 **,ov 1r*GND
OV
..
..
....
..
File Name: Iflop
Date: 12/3/1987
Time: 10:1:22
@DEVlCE TYPE PLHS501
@DRAWING
@REVlSION
@DATE
@SYMBOL
@COMPANY
@NAME
@DESCRIPTION
Single D flip-flop connected as
divide·-by-two for test
@INTERNAL NODE
CSNO.CRNO.CQO.CQNO;
@COMMON PRODUCT TERM
@I10 DIRECTION
@I10 STEERING
@LOGIC EQUATION
00 - I(CQNO);
CSNO - I(CLK'RST*(/(CSNO'(/[CQNO'RST*CRNO]))));
CRNO = I(CSNO'CLK'(I[CQNO'RST'CRNO]));
CQO = I(CSNO'CQNO);
CQNO = I(CRNO'CQO'RST);
Figure 1.8 PLHS501 Test Flip-Flop
PLHS501
77 66 666666 6 65 555555 55 54 4 4 4 4 4 4 4 4 4 3 3 3 33 3 33 3 3 22222 222 221111111111 000 0000 000
1098765432109876543210987654321098765432109876543210 98 7 654 3 21 0 9 8 7 6 54 3 21 0
I IIII II II I I II II IIII11! IIBBBBBBBB
22221111111111 00 0 00 0 0000 00 0 0 00 0 0
32109876543210987654321076543210
Col for
... '"
, •••••.•••••. '"
IB 0
..•• , . . . . . • • . • , •.....•••.•• , ' .•••••..••..•••••. A .•
HH------------------------------
Col for
••••••••••••••••••••••.• , .•••••••••••• '"
-H------------------------------
P 0
• • • • • • • • • • . . . . . . . . . . • . ' , .•. A •••
Col for
P1
••••••••••••••••.••.•.••.••.•.•••••..•••••••••..••.••••••.•...•.••• A .•• A
H-------------------------------
Col for
P 2
•••••.••••••.•.••••..•••••..•••••..•••••••••••.•.••••••.••••••.... A ••. A.
------------------------------
Col for
P 3
•••••..••••••••••••••••••••••••••...•••••••.•.•••••.••.•..•••..•••• A .•• A
H--------------------------
Col for
P 4
.••••..•.••..•.•.....•••..•....•.•.•........... , . . • . . . . . . . . . . . . • . . . . . AA.
------------------------------
Col for
P 5
•••••••••.•••••••••••••••.••••••••••••••••••••• " " "
•••••••••••••••• A.A
Figure 1.9 Partial PLHS501 Fusemap Showing Test Flip-Flop Fusing
~-------------------
June 1988
570
Signetics Application Specific Products
Designing with Programmable Macro Logic
IIlB.!:)
lIa.G
I--'
I--'
I--'
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
28.0
+
+
+
RESE1N
CLOCK
+
+
+
+
+
+
+
+
+
+
5N
+
+
+
+
r - AN
+
+
+
+
+
+
+
+ L..-C
+
CN
+
+
+
+
+
40.0
60.0
BO.O
l08.8
120.0
Figure 1.10 Waveforms of Test Flip-Flop
June 1988
+
571
DATA
'.0.8
OA
L
ON
160. a
Signetics
Designing with Programmable
Macro Logic
Application Specific Products
FUNCTIONAL FIT
In the late 1960's and early 1970's designers
used SSI, MSI and small amounts of early LSI
to generate logic solutions. Frustrated by the
lack of wide input gates to accommodate a lot
of product terms for two level solutions, they
turned toward the budding ROM and PROM
products. These devices relied on literally
realizing a function by generating its truth
table in silicon. The logic function had to have
each logical one and zero realized distinctly
as an entry for a particular combination of
input variables, usually supplied on the address lines of the memory. Observing that
many such truth tables were dense in ones or
zeroes and sparse in the remainder, a cadre
of initial manufacturers emerged with focus
on supplying a programmable product with a
few "AND gates and OR gates which were
versatile enough to compete against the
ROM/PROM parts. The gimmick supplied by
these PLA manufacturers was to illustrate the
functional equivalency of the PLA to the
PROM by comparing the number of product
terms (to be shortened to "p-terms") the PLA
supplied and comparing this to the width and
depth of available PROMs. P-terms became
the "currency" of the PLA world and a
designer only had to assess the equivalent
number of Boolean product terms required by
his function to determine whether a particular
PLA was a suitable candidate for his design.
Almost in parallel, gate arrays became available. These provided an array of identical,
fixed input gates (usually two input NANDs or
NORs). These were generated in a regular
fashion on a substrate which had a fixed
inputloutput pin arrangement. Also recognizing that all logic functions could be built from
the appropriate two input gates, when interconnected correctly, manufacturers offered
these devices to customers who required
increased density.
June 1988
The designer's responsibility was to generate
what would ultimately be a metal interconnect
pattern of his design. Special tools were
required to allow an untrained system designer to do this successfully. Flip-flops, decoders, registers, adders, etc., could all be generated from the low level gate building blocks.
The currency of gate arrays became known
as gate equivalent functions. That is, with a
limited number of available gates on a substrate, the user needed to know precisely
how many gates were used up, on a function
by function basis, to generate each piece of
his design. A D flip-flop requires about six
gates, a D latch four, a 3 to 8 decoder takes
about 14 gates and so forth. This allowed
estimation regarding whether the function
could conceivably be fit onto a particular
substrate or not. Manufacturers had to offer
multiple foundations so that a designer could
be assured that his design would result in a
working I.C.
The classic method of estimating whether a
logic function would fit into a PLA was to
determine the number of 1/0 pads required
and the number of product terms required to
generate the logical function, then select the
PLA. For a gate array, the required measure
included the 1/0 pad arrangement but substituted the number of available gates to generate the logical function (usually by table
lookup). In an attempt to reconcile the two
measures, Hartman 4 has evolved a formula
for his product line. A calculation using this
method and developing an appropriate "exchange rate" is shown in Table 2.1 for the
PLHS501 and PLHS502. An alternate method
of generating an estimate is to consider the
gate equivalent of generating, say for the
PLHS501, a gate equivalent of the part in an
optimistic functional configuration (72 occurrences of a 32 input NAND gate). Figure 2.1
572
shows how this will result in over 2000
equivalent gates. Conversely, by stacking the
NAND gates into D flip-flops, its least efficient
function, the PLHS501 will have a gate equivalent of only about 100 gates.
The most rational method of assessing fit is
to isolate functions and identify the correct
configuration in terms of gates, to allow direct
tally of the gates used, to generate the
proposed configuration. Table 2.2 may assist
in doing this analysis. Note that all basic
gates require precisely one gate to generate
the function. Also note the occurrence of
functions in the table which could never be
generated as standard I.C.'s previously. The
procedure is to tally the design against a total
budget of 72 multiple input NAND gates.
Table 2.2 is illustrative only, and should by no
means be taken as complete. It may be
simply expanded by designing the proposed
function with disregard to the usual restrictions on the number of inputs to a gate,
realize the function as one, two, three, or
more levels of interconnected logic and count
the number of gate ocurrences required.
Special software has been provided to allow
pyramided logic structures to be generated
under the designer's control. These structures may, however, be no deeper than 72
levels for the PLHS501. Functions should be
generated in accord with the guidelines mentioned before, for selecting an optimal 2 level
logical solution.
It is an interesting observation that manufacturers of gate arrays and standard cell products which offer embedded PROMS, ROMS
or RAMS have not successfully described
these embedded functions in terms of equivalent gates, but rather resort to other means
(such as divulging their relative area with
respect to the area of a basic gate). There is,
as yet, no standard in this arena.
Signetics Application Specific Products
Designing with Programmable Macro Logic
TABLE 2.1 EQUIVALENCY RATIO
Hartman's method is based on a CMOS gate array equivalency wherein 4
transistors constitute a 2 input NAND or NOR gate, equal to one gate. Thus, his
"exchange rate" is as follows:
E.R.
~
4 X
+9 X
+7 X
+ (15
# inputs
# FFs
# 3-State outputs
to 30) X # OR outputs from the AND/OR array.
For the PLHS501: (using CMOS numbers which !TIID' be inappropriate)
E.R.
~
4 X 32
+9 X 0
+ 7 X 24
+ (15 to 30) X 50% of 72 feedbacks
~
836 to 1376 gates
For the PLHS502:
E.R.
~
4 X 32
+9 X 16
+ 7 X 12
+ (15 to 30) X 50% of 64 feedback
~
962 to 1502 gates
Being for two bipolar I.C.'s, in this case, the method may be inappropriate, but
may be taken as an estimating procedure.
QHI.IKlMNOP
NOTE:
Double this and add one for a 32 Input NAND.
Figure 2.1 16 Input NAND Formed from 2 Input Gates
June 1988
573
Signetics Application Specific Products
Designing with Programmable Macro Logic
TABLE 2.2 PLHS501 GATE COUNT EQUIVALENTS
FUNCTION
PLHSS01 INTERNAL
NAND EQUIVALENT
COMMENTS
Gales
NANOs
ANDs
NORs
ORs
1
1
1
1
For
For
For
For
1
1
1
1
to
to
to
to
32
32
32
32
input
input
input
input
variables.
variables.
variables.
variables.
3 to 8
4 to 16
8
16
5 to 32
32
Inverted inputs available.
Inverted inputs available.
Inverted inputs available (24 chip
outputs only).
Decoders
Encoders
8 to 3
16 to 4
15
32
32 to 5
41
Inverted
Inverted
Inverted
factored
inputs, 2 logic levels.
inputs, 2 logic levels.
inputs, 2 logic levels,
solution.
Multiplexers
4 to 1
8 to 1
16 to 1
5
9
17
Inverted inputs available.
27 to 1
28
Can address only 27 external
inputs - more if internal.
6
6
8
With asynch S·R
With asynch S·R
With asynch S·R
45
Full carry look-ahead (four levels of
logic)
72
2 levels of logic
Flip-Flops
D-FF
T-FF
J-K-FF
Adders
8-bit
Barrel Shifters
8-bit
June 1988
574
Designing with Programmable
Macro Logic
Signetics
Application Specific Products
DESIGN EXAMPLES
coprocessor like functions as well as home-
Most designers tend to view a PLD as a
mechanism for collecting logical glue within a
system. That is, those pieces which tie together the larger LSI microprocessors, controllers, RAMs, ROMs, UART s, etc. However,
there is a tendency of viewing a gate array as
an entire system on a chip. PML based
products will fit well in either casting as will be
demonstrated by a series of small but
straightforward examples. For starters, we
shall examine how the fusing process embeds functions, progress to glue-like decoding operations and finally demonstrate some
made "standard products".
The method of associating gates within the
NAND foldback structure is depicted in Figure
3.1 wherein a simple three to eight decoder is
fused into the array. The corresponding inputs are on the left and outputs at the top.
This figure shows inputs and their inverse
formed in the array resulting in a solution that
requires 6 inverting NANDs that would probably be best generated at the input receivers.
Hence, this diagram could be trimmed by six
gates, down to eight to achieve the function.
Figure 3.2 shows two consecutive D-flip-flop
fUSing images. Note that asynchronous sets
and resets may be achieved for free, in this
version. In both Figures 3.1 and 3.2 the gates
are numbered in a one-to-one arrangement.
As well, the accompanying equations are in
the format used by Signetics AMAZE design
software. For clarity, consider the gate labeled 2A in Figure 3.1. Schematically, this is
shown as a 3 input NAND. However, in the
fused depiction, it combines from three intermediate output pOints with the dot intersect
designation. Hence, all gates are drawn as
single input NANDs whose inputs span the
complete NAND gate fold back structure.
1 OF 8 DECODER/DEMULTlPLEXER
EN
,.ll.
V
8
I
E
~
18
~ T1
eNN
,~NN
CN
::t.V>- 12
~r--l
RN
7651.\3210
~ 1S
"; 8 AN
3
:::;-~NN
fUJ'""'16
:::; 1 r"
AN
....
7
18
14
AN",
9
'9"
'::::::'
=UJ- 13
~
CNN
S
11
'IT
'i3'
:::.-'
14
~
'6'
17
NN
'5""'
4
0)LOGIC EQUATION
AN
=
fA;
BN
=
18;
eN
=
~
-ID--!D-
Ie;
ANN
=
BNN
= IBN;
IAN;
CNN
=
EN
leN;
E = lEN;
YO=/ (AN*BN*CN*E);
Y1
= /
Y2
=
I AN '" BNN • eN • E);
Y3
=
I ANN' BNN '" eN • E);
-lJ?i
r§;l
ANN' BN • eN • E);
Y4=/ AN'BN*CNN*E);
Y5
= /
ANN' BN • CNN • E);
Y6
= /
AN' BNN • CNN • E);
Y7 = I ANN'" BNN • CNN '" E);
Figure 3.1 Decoder Implementation in NAND Foldback Structure
June 1988
575
Signetics Application Specific Products
Designing with Programmable Macro logic
TWO EDGE-TRIGGERED FLIP-FLOPS
ON2
02 ON201
@LOGIC EQUATION
DA1 = / (DN1 .. SN1);
SN1 = I (DA" CLOCK1)
lela CK>
6A
DN1 = I (DATA1 '" RN1);
'6B'
01 = I (SN1 '" QN1);
4A
(AN1 • 01);
46
DA2 = I (DN2 '" SN2);
SN2
= I
..--..
..--..
lelO CK!
RN1 = / (SN1 ... CLOCK1 ... ON1);
ON1~/
ONI
(DA2" ClOCK2)
OAT A2
5A
58
RN2 = I (SN2" CLOCK2 .. DN2);
DN2 = I (DATA2" RN2);
3A
Q2 = I (SN2" QN1);
-®--®---liD--
QN2 = / (RN2" Q2);
ORT RI
~
Figure 3.2 Two Flip·Flops Implemented in the NAND Foldback Structure
One straightforward example of using a
PLHS501 is shown in Figure 3.3. Here, the
device is configured to accept the 23 upper
address lines generated by a 68000 micro·
processor. By selecting the direct and com·
plemented variables, at least 16 distinct address selections can be made using only the
dedicated outputs. The designer can combine
additional VME bus strobes, or other control
signals to qualify the decode or, define 8
additional outputs for expanded selection. As
well, the designer could transform the bidirec·
tionals to inputs and decode over a 32 bit
June 1988
space, selecting combinations off of a 32 bit
wide address bus. Because this simple level
of design requires only NAND output terms
plus 4 NAND gates in the foldback array (for
inversion of signals connected to 03.00),
there may be as many as 68 remaining gates
to accomplish additional handshaking or logi·
cal operations on the input variables.
A2S
sao
SELl
68000
At
SELl5
AS
Figure 3.3 68000 Microprocessor
Address Decode
576
Signetics Application Specific Products
Designing with Programmable Macro Logic
148
Al
A2
A3
A4
AS
;
0-"
i
,
j
A6
A7
~
87
ou t 7
86out6
65 outS
84 Qull!
83 Qut3
82out2
61 Dull
BO QutO
Figure 3.4 8-Bit Barrel Shifter Implemented with the PLHS501
An eight bit barrel shifter exploits most of the
PLHS501 as depicted in Figure 3.4. This
implementation utilizes all 72 internal foldback NANOs in a relatively brute force configuration as well as 8 output NANOs to generate transparent latched and shifted results.
The shift position here is generated by the
shift 0, shift 1 and shift 2 inputs which are
distinguished and selected from the input
cells. Variations on this idea of data manipulation could include direct passing data, mirror
June 1988
imaged data (bit reversal) or byte swapping to
name a few.
Part of an eight bit, look-ahead parallel adder
is shown in Figure 3.5. Gates necessary to
form the level-O generate and propagate, as
well as the XOR output gates generating the
resulting sum are not shown. The reader
should be aware that this solution exploits
four layers of pyramided gates and only
utilizes a total of about 58 gates. Additional
sn
comparison or Boolean operations could still
be generated with remaining NAND functions
to achieve additional arithmetic operations.
This application should make the reader
aware of a new class of applications achieveable with third generation PLDs - user defineable I/O coprocessors. The approach of
increasing microprocessor performance by
designing dedicated task coprocessors is
now within the grasp of user defineable single
chip solutions.
Signetics Application Specific Products
Designing with Programmable Macro logic
P8
G1
P8
P1
G6
G2
P8
P1
PS
GS
G2
I
;;:~C5
CB
IGS
P6
GS
Cl
Gil
P5
P6
C6
Pl 1
PS
PS
co
---C2
IG6 - - - - - - '
P7
G6
P7
P6
GS
G2
P3
C7
P2
,---..... >-___ C3
E~
P3
P2
Gl
IG3-----'
IG1------'
P7
P8
PS
~~I
P~
G3
P~
P3
G2
P~
P3
P2
CI
IG~ - - - - - - '
~~~
P2~-------
IPl l
PI
Figure 3.5 Partial NAND Gate Equivalence of the 8-Blt Look-Ahead Adder
June 1988
578
An example of one of the least efficient
structures realizeable on the PLHS501 is
shown in Figure 3.6. Here, a cascade of 12 Dflip-flops are formed into a toggle chain that
uses all available NAND gates in the main
logic array. In the PLHS501 simple cross
coupled latches or transparent D latches are
preferred over edge triggered flip flops simply
because they conserve NAND gates. Applications for structures like this include timing
generators, rate multiplication, etc. Additional
. output gates exist on the output terms as
shown in Figure 1.2, which could gate the
output in multiple state petection configurations. As well, rearranging Figure 3.6 as a
12-bit shifter, picking off stales at the output
terms could result in a general purpose sequence recognizer capable of recognizing
binary string sequences. These strings could
be up to 13 bits long (in a Mealy configuration) and 24 distinct sequences could be
sensed and detected.
Signetics Application Specific Products
Designing with Programmable Macro logic
::r
'"
C\J
o
111
o
Cl
o
eLK
RSTC>----~---------i----------+_--------_r--------~~--------~
N
o
o
'"o
C1
CD
o
o
Figure 3.6 12-81t Ripple Counter
Figure 3.7 shows a 32 to 5 - bit priority
encoder. This sort of device could generate
encoded vector interrupts for 32 contending
devices. 01 particular interest is the fact that
ordinary encoders are not this wide. The
designer is, of course, not constrained to
generating combinational functions in even
powers of two. Thus, the PLHS501 can easily
perform customized functions like a 5 to 27
decoder or a 14 to 4 encoder or, even an 18
to 7 multiplexor. For the sake of optimization,
the designer is encouraged to implement
precisely the function he needs, no more and
no less!
131
IB
The design examples given are illustrative of
some typical operations used in ordinary
systems. In each case, the example could be
thought of as simply an "off the shelf"
standard solution to an every day problem
(I.e., a de facto standard product).
.-=iL:)--!>'" R4N
--H-H-------~r_~EON
GSN
Input
Buffers
NAND
ArroW
Output
Tarl"lS
Figure 3.7 Encoder
June 1988
579
r-
o
Designing with Programmable
Macro logic
Signetics
Application Specific Products
SUCCESSOR ARCHITECTURES
inputs and 8 bidirectionals can be configured
The design examples described and Table
2.2 illustrate the combinational power
and the sequential limitations of the
PLHS501 - Signetics first PML entry. Clearly.
the next family members must address the
flip-flop issue, and they do. The PLHS502
(Figure 4.1) shows a similar NAND function
array of 64 gates with the vital addition of 8
buried D-flip-flops and 8 buried S - R flipflops. Again, 16 pins are devoted to dedicated
outputs, 20 straight inputs, 4 clock or general
to expand input or output capabilities. Slated
to operate in the middle 30MHz clocking
range, this part greatly expands the sequencer capability beyond the initial PLHS501. The
PLHS502 application range will include state
machines like CRC generation/detection,
Bus handshakers, LAN handshaking, arithmetic coprocessors, single chip systems and
a complete bevy of general sequencer operations such as sequence generation and detection. It should be emphasized that the
64 NAND
Terl'ls
npu t
Buffers
8
S~R
B O-Type
Flip-Flops
NAND array is fully connected and circumvents limitations on connectivity as found in
other PLD products.
Almost simultaneous with the arrival of the
PLHS502 (a bipolar part) will be the first
CMOS PML entry. Expanding on the functional capabilities of the PLHS502, the CMOS
part will ofler 52 flip-flops in a variety of
natural configurations with a NAND array near
200 gates. Due to complexity and density, the
part will combine a distinctive power-save
option and the benefits of scan-design.
Output
F l1p-F lops
TerMS
18
119
J20
121
122
123
_.
I~ J
""L -
1 )1
,.~
1 )1
...
,.~
.
'1
1 1
~ ... Lfj
"
J
I
.
"
t~'"
.-
..
08- 0 11
00- 0 7
Ou tpu t
Buffer
8
•••
15
Figure 4.1 PlHS502 Diagram
June 1988
580
80-/8 7
012-°15
Signetics
Designing with Programmable
Macro logic
Application Specific Products
SUPPORT ISSUES
The current PML architecture, the PLHS501,
is adequately supported by Signetics AMAZE
software. Offered free to qualified users,
AMAZE can generate the required design
files, fusemaps and simulations within the
appropriate modules of AMAZE. From a simple menu driven environment on an IBM
personal computer (or compatible under MS/
DOS), the user can generate a design with
logic equations, state equations or schematic
entry (using FutureNet Dash or ORCAD SDT
software). Once the design is entered, the
user must "assemble" it prior to fusing the
PML product. If required, the user may simulate the assembled file to determine the
accuracy and functional operation of his design. Iteration between design entry, assembly and simulation may be required, depending on the users expectations and the completeness of design. Automatic test vector
generation is a simulation option. Currently,
June 1988
the designer may fuse his design using either
a DATA I/O Unisite programmer, a Stag
ZL - 30A or a STREBOR fusing system with
corresponding configuration modules.
The AMAZE product is fully contained and
complete except for the schematic capture
program. Although it is used for the complete
line of Signetics PLD products (PLAs, Sequencers and PROMs), it has undergone
additional modification to support special features required by the nature of the PML
products. These include the following:
• Internal Nodes - the ability to define and
refer to nodes completely within the array
and isolated from direct contact with the
device I/O pins.
• Bracket Freezing - the ability to tag (with
square brackets) a Boolean subfunction
which is not to be optimized by the AMAZE
assembler but is to be realized within the
design explicitly as described by equation.
581
Both features are key to the AMAZE approach to macro generation. In particular,
"bracket freezing" allows the designer to
make tradeoffs between wide and shallow
combinational paths and long, narrow combinational paths.
In the current rendition of AMAZE, automatic
placement and interconnect of the fused
Boolean functions is the recommended approach. Should the user decide to intervene,
a special fuse table editor exists for manual
alteration of the design file. This is not the
recommended approach, but it also serves as
a diagnostic tool to review deSign placement
and interconnect.
Future directions for software support include
enhanced simulation, exhaustive automatic
Boolean optimization, the development of a
full library of macros, automatic design partitioning and a wide assortment of bells and
whistles.
Signetics
Designing with Programmable
Macro logic
Application Specific Products
PLHS501 EXAMPLES USING
AMAZE REVISION 1.6
• Simple gate implementations
• B-bit barrel shifter
• 12-bit comparator with dual 1 of B
decoders
• B-bit carry look-ahead adder
• 32 to 5 priority encoder
• B-bit shift register with 3-bit counter
and sequence detector
• 4-blt synchronous counter
Following are six example applications for the
PLHS501 using AMAZE Rev. 1.6. They
should not be viewed as showing all possible
capabilities of the device. They have been
designed to demonstrate some of the
PLHS501 features, syntax of AMAZE, and to
give the reader some ideas for possible circuit
implementations.
Note that these examples were written using
AMAZE Rev. 1.6. Although Signetics will try
to keep succeeding versions of AMAZE compatible, it may be necessary to change some
syntax rules. Therefore, please refer to your
AMAZE manual for any notes on differences,
if using a revision later than Rev. 1.6.
SIMPLE GATE
IMPLEMENTATIONS
File Name
L I S T IIIIUIIUU
#UIIUUIII PIN
Right
Left
PIN"'''' FNC ....
FNC uPIN
+5V
8-1
9-1
I
LABEL
VCC
A
** 10-1
B
C
•• I
•• I
I
0
•• 0
•• 0
D
N/C
N/C
F2
F4
F6
N/C
F20
GND
B
•• 0
ov
Bottom
LABEL
F40
F60
N/C
FlO
F30
F50
N/C
FlX
F2X
F3X
F4X
F5X
F6X
In this example six functions were implemented for each of the three major types of
output structures. The six functions are ANDI
OR, AOI, NAND, AND, OR and NOR. A
requirement for the ANDIOR and AOI gates
was to use only two gates each from the
fold back array and to combine these product
terms in one NAND output gate. To achieve
this result, it was necessary for the 16 and 10
outputs to write equations using internal
nodes and brackets around the equation.
Refer to Figures 6.1 and 6.2.
ll-I
12-1
13-1
14-1
15-1
16-\
17-1
18-\
19-\
20-\
L
H
S
0
1
+5V
1-46
1-45 *" I
1-44
I
1-43 '/<"If
1-42
\-41 •• I
\-40 ** /0
\-39 •• /0
\-38 "'* /0
1-37 *'" /0
\-36 •• 0
\-35
0
OV
1-34
582
LABEL
"'vee
"N/C
"'*N/C
'**N/C
UNjC
**N/C
**Fl
"'*F3
"'*FS
**N/C
"""N/C
**F7X
"'*GND
Top
** FNC **PIN
•• 0
21-\
22-1
**0
23-1
**0
24-\
** /0
25-1
** /0
26-1
** /0
27-1
** /0
28-\
"0
29-1
0
30-1
0
31-\
0
32-\
** 0
33-\
"0
P
L
H
S
5
0
1
PIN"'*
1- 7 **
1- 6 ..
\- 5
\- 4
1- 3 **
1- 2 ..
\- 1 **
I-52 ..
I-51
I-50
\-49
\-48
1-47 **
Figure 6_ 1 Gates Pin List
For the simulation (Figures 6.3 and 6.4) a
binary count of 0 through 15 hex was applied
to the input D-A. Each output of the log file
was checked against anticipated and other
device outputs of the same function for correct operation.
June 1988
GATES
9/15/1987
Time: 9,30,16
Date
LABEL
FNC
**N/C
I
I
**N/C
*"'N/C
**N/C
I
I
I
I
**N/C
*"'N/C
**N/C
"'*N/C
**N/C
**N/C
*"'NjC
**N/C
I
"'*N/C
Signetics Application Specific Products
Designing with Programmable Macro Logic
File Name : GATES
lJate :
9/15/1987
Time, 9,30,35
.. AND-OR using XOR output"
flx - (a*b)+(c*d);
.. AND-OR-INVERT using XOR output"
f2x - /[(a-b) + (c'd)];
@DEVICE TYPE
PLHS501
@DRAWING
@REVISION
@DATE
@SYMBOL
@:OMPANY
.. NAND using XOR output"
I( a*b*c*d) ;
.. AND using XOR output"
f4x .. a*b*c*d;
"OR using XOR output"
fSx - /(/a*/b*/c*/d) j
f3x ..
@NAME
@DESCRIPTION
"NOR using XOR output"
Various single and two level gate implementations using
f6x .. /a" Ib* Ie· /d;
different output structures
"XOR using XOR output"
f7x : xrl .. aj
xr2 .. hi
@INTERNAL NODE
@:OMMON PRODUCT TERM
@I/O DIRECTION
@I/O STEERING
@LOGIC EQUATION
"AND-OR using
/B
"ANn-OR using /0 output"
flo - /U[a'b) • /[c'd)
;
.. AND-OR-INVERT using 0 output"
f20" /((a*b) + (c-d)];
"NAND using /0 output"
f30 .. /(a*b"'c*d) i
output"
fl - /U[aob) - /[c-d)
;
-AND-OR-INVERT using B output"
.. AND
£2 - /[ (aOb) + (cOd»);
"NAND using
/B
f3 - /(a*b*c*d);
"AND using B output-
"NOR
f4 - a*b*c*d;
"OR using
/B
using 0 output-
f60 - /a*/b*/c*/d;
output"
f5 - /Uaojbo/c'/d)
using 0 output"
£40 .. a*b*c*d;
.. OR using /0 output"
f50 .. /(/a*/b*/c*/d);
output"
i
"NOR using B output"
f6 - /a*/b*/c*/d;
Figure 6.2 Gates Boolean Equations
Simulation input file for GATES
<-------- INPUTS-------- > < B
1
/B
>
222211111111111
321098765432109876543210 76543210
DCBA
A is MSB, D is LSB
HHULLHHHHHHHHHHHHHHHHHH
HHHLLLHHHHHHHHHHHHHHHHHH
HHLHLLHHHHHHHHHHHHHHHHHH
HHHHLLHHHHHHHHHHHHHHHHHH
HHLLHLHHHHHHHHHHHHHHHHHH
HHHLHLHHHHHHHHHHHHHHHHHH
HHLHHLHHHHHHHHHHHHHHHHHH
HHHHHLHHHHHHHHHHHHHHHHHH
HHLLLHHHHHHHHHHHHHHHHHHH
HHHLLHHHHHHHHHHHHHHHHHHH
HHLHLHHHHHHHHHHHHHHHHHHH
HHHHLHHHHHHHHHHHHHHHHHHH
HHLLHHHHHHHHHHHHHHHHHHHH
HHHLHHHHHHHHHHHHHHHHHHHH
HHLHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHH
---------------------------------------------------------------------------------------------------------------
.. Input all 0' s A-D"
.. Input count 1"
"Through •••
·Count 15 hex"
QUIT
Figure 6.3 Gates Simulation Input File
June 1988
583
Signetics Application Specific Products
Designing with Programmable Macro Logic
PLHS501
GATES
Time - 13,59,42 Date - 9/14/1987
<-------- INPUTS-------- > <
> < XOR > < /0,0 >
222211111111111
321098765432109876543210 76543210 76543210 76543210
110000111111111111111111
111000111111111111111111
110100111111111111111111
111100111111111111111111
110010111111111111111111
111010111111111111111111
110110111111111111111111
111110111111111111111111
110001111111111111111111
111001111111111111111111
110101111111111111111111
111101111111111111111111
110011111111111111111111
111011111111111111111111
110111111111111111111111
111111111111111111111111
B, /B
HHLHLHLL
HLLHLHHL
HLLHLHHL
HLLLHHHL
HLLHLHHL
HLLHLHHL
HLLHLHHL
HLLLHHHL
HLLHLHHL
HLLHLHHL
HLLHLHHL
HLLLHHHL
HLLLHHHL
HLLLHHHL
HLLLHHHL
HLHLHLHL
LLHLLHHL
LLLHLHHL
LLLHLHHL
LLLHLHLH
LHLHLHHL
LHLHLHHL
LHLHLHHL
LHLHLHLH
LHLHLHHL
LHLHLHHL
LHLHLHHL
LHLHLHLH
LLLHLHLH
LLLHLHLH
LLLHLHLH
LLLHHLLH
------------------------ --------
oc:x:x:x:>ooo
OOOOOOOO
TRACE TERMS
LLHLHHLH
LHHLHLLH
LHHLHLLH
LHHHHLLL
LHHLHLLH
LHHLHLLH
LHHLHLLH
LHHHHLLL
LHHLHLLH
LHHLHLLH
LHHLHLLH
LHHHHLLL
LHHHHLLL
LHHHHLLL
LHHHHLLL
LHLHHLHL
I/O CONTROL LINES
DESIGNATED I/O USAGE
ACTUAL I/O USAGE
PINLIST ...
14 13 12 11 10 09 07 06 05 04 03 02 01 52 51 50 49 48 47 45 44 43 42 41
18 17 16 15 40 39 38 37 36 35 33 32 31 30 29 28
27 26 25 24 23 22 21 19 ;
Figure 6.4 Gates Simulation Log File
June 1988
584
Signetics Application Specific Products
Designing with Programmable Macro Logic
8 BIT BARREL SHIFTER
This 8-blt shifter wiii shiH to tile right, data
applied to A? - AO with the result appearing
on OUT? - aUTO. Data may be shifted by 1 to
? places by indicating the desired binary
count on pins SHIFT2 - SHIFTO. Data applied
to the aUTO position for a shift of 1. For a
shift of 0, A? will appear on OUT?
File Name , BRLSHF'l'
Date , 9/15/1987
Time , 9:31:58
L I S T iliililll#ilili#ili##
#111#111111#1 i ililili PIN
Right
Left
LABEL
FNC "'*PIN
+5V ** 8-1
9-1
** I
.. I
10-1
11-1
** I
** I
12-1
13-1
** I
14-1
** I
15-1
0
16-1
0
** 0
17-1
18-1
** 0
19-1
0
20-1
** OV
VCC
A2
A3
Also included is a transparent latch for the
output bits. The input 'COMPLMTO' will invert
all output bits simultaneously and input IOE
will 3-State all outputs.
A4
A5
A6
A7
L4
L5
L6
L7
N/C
GND
P
L
H
PIN"''''
1-46
1-45
1-44 **
1-43 ,.
1-42
1-41
1-40
1-39
1-38
1-37 **
1-36
1-35 **
1-34
LABEL
FNC "'*
+5V 1c*VCC
I
I
I
I
I
/0
/0
/0
/0
0
0
OV
**N/C
**N/C
"'*NjC
**N/C
**N/C
""'LO
"'*Ll
**L2
**L3
**OUT7
**OUT6
**GND
Top
LABEL
"'*AI
"''''AO
**SHIFT2
**SHIFTI
Bottom
LABEL
N/C
N/C
N/C
N/C
N/C
N/C
N/C
OUTO
OUT1
OUT2
OUT3
OUT4
OUT5
**
**
**
**
**
PIN** FNC
FNC **PIN
** 0
** 0
** 0
/0
/0
/0
/0
** 0
** 0
"0
** 0
** 0
** 0
21-1
22-1
23-1
24-1
25-1
26-1
27-1
28-1
29-1
30-1
31-1
32-1
33-1
P
L
H
S
5
1- 7
1- 6
1- 5
1- 4
1- 3
1- 2
1- 1
I-52
I-51
I-50
1-49
1-48
1-47
I
** I
** I
**SHIFTD
**COMPLMTO
**/LE
** I
** I
,. I
"''''IDE
,. I
**N/C
'*N/C
**N/C
**N/C
**NjC
Figure 6.5 Barrel Shilter Pin List
RO
RI
R2
R3
R"
R5
R5
R7
110
111
10!
100
011
010
001
000
5H 1FlO
SH 1FT 1
SH 1FT 2
ILE
P
5,~rP
Fr
IPrF[~~Pr
~~
IJi
~
~.
~
81
3/ & ~
COMPLHTQ
IDE
'J
~
~
au t 7
au lG
0
~
t
0
DU
tS
~
t
au
t4
b
r':
~[]
au t3
au
r':
l2
Figure 6.6 8-Bit Barrel Shifter Schematic
June 1988
585
au t]
4
au
to
Signetics Application Specific Products
Designing with Programmable Macro Logic
File Name : BRLSHFT
Date , 9/15/1987
Time, 9,32,14
@DEVICE TYPE
PLHS501
@DRAWING
@REVISION
@DATE
@SYMBOL
@COMPANY
@NAME
@DESCRIPTION
8 Bit Barrel Shifter
wi th 3-state latched outputs
@INTERNAL NODE
nodI, nod2, nod3 ,nod4 I nodS, nod6, nod7 , nodS;
nod9, nodlO I nodl1, nOO12, nod13 , nod14, nod15, nOO16;
nod17 ,nOO18,nOO19,nOO20, nod21,nod22,nod23 ,nod24;
nod25, nOO26, nod27 ,nod28, nOO29 , noc130 I nod31 , nod32 i
13,12,11,10;
@COMMON PRODUCT TERM
rotC" /shift2 .. /shlftl * /shiftO
rotl .. /shift2 1< /shlftl '" shiftO
rot2 .. /shlft2 '" shiftl '" /shiftO
rot3 .. /shift2 '" shiftl 1< shiftO
rot4"
shift2
'I\"
/shiftl '" /shiftO
rotS" shift2 '" jshiftl '" shiftO
rot6" shift2 1< shiftl '" /shiftO
rot?... shift2 '" shiftl '" shiftO
@I/O DIRECTION
xeD - oe;
xel .. oei
xe2 .. oej
xe3 .. oe;
@I/O STEERING
@LOGIC EQUATION
17 .. l[a7 '" rotO '" lIe +
a6 '" rotl * lIe +
a5 '* rot2 '* lIe +
a4 '* rot3 '* lIe +
a3 '* rot4 '* lIe +
a2 '* rotS * lIe +
a1 * rot6 * lIe +
Figure 6.7 Barrel Shifter Boolean Equations
June 1988
586
Signetics Application Specific Products
Designing with Programmable Macro Logic
aD " rot? 'I< Ile +
le*/171i
'I< rotO 'I< Ile +
a5 'I< rotl " Ile +
a4 " rot2 " Ile +
a3 '" rot3 ... lIe +
a2 '" rot4 '" Ile +
a1 'I< rotS " lIe +
aD " rotS '" lIe +
a7 ,. rot? '" Ile +
le 'I< /16 J i
16 .. /[a6
15 .. /[a5 *" rotO " lIe
a4 * rotl 'I< Ile
a3 " rotZ 'I< Ile
a2 1< rot3 '" lIe
a1 ,. rot4 " lIe
aO " rotS 'I< Ile
a7 " rot6 " Ile
a6 ... rot? " Ile
le .., /15];
+
+
+
+
+
+
+
+
14 .. /[a4 'I< rotO " Ile +
a3 " rotl " Ile +
a2 'I< rot2 " Ile +
a1 " rot3 'I< lIe +
aD " rot4 " Ile +
a7 'I< rotS 'I< lIe +
a6 " rot6 " Ile +
a5 .. rot? " Ile +
Ie */14];
nodI" [a3
nod2 .. [a2
nod3 .. tal
nod4 .. taO
nodS" [a7
nod6 .. [a6
nod? .. [as
nodB - [a4
i3 - [Ie"
" roto
'" rotl
'I<
1<
'I<
Ile]
1<
lIe]
rot2 ;, Ile]
roU .. Ile]
'I<
rot4 .. Ile]
'" rotS .. (le)
rot6 'I< lIe)
,. rot7 ." Ile)
13);
'I<
13 .. /( [fnodl" /nOO2*/nOO3'" /nod4* jnod5*/nod6* /nOO7*/nOO8* /i3] ) ;
Ile]
i
nocilO- fal ;. rot! ;. lIe]
i
nod9 .. (a2 " rotO
'I<
Figure 6.7 Barrel Shifter Boolean Equations (Continued)
June 1988
587
Signetics Application Specific Products
Designing with Programmable Macro Logic
nOO11- [aO 1< rot2 '" Ile];
nOO12- [a7 ... rot3 1< lIe] i
oodl3 .. [a6 ... rot4 *
ood14" [a5 1< rotS *
00015- [a4 1< rot6 *
nOO16- [a3 1< rot? ..
U-[le*12];
lie];
Ile];
lie) i
lIe];
12" I( f/nod9*/nodlO*/nodll*/nod12*/nod13*/nod14*/nod15*/nod16*/i2)
nodl7- [al
nod18 ... laO
00019- [a7
00020'" [a6
00021 .. (a5
nod22- [a4
00023- [a3
nod24- [a2
il .. [le 1<
1<
rotO ... lIe)
1<
rotl " lIe)}
i
i
.. rot2 " lIe] i
.. rot3 1< Ile];
.. rot4 1< Ile] i
1< rotS
" Ile] i
" rot6 1< Ile];
'" rot7 1< Ile];
11] ;
11 .. /( [/nod17*jnodlB*jnod19*jnod20*jnod21*jnod22*/nod23* /nod24 * Jill);
00025- [aD
ood26- [a7
00027- [a6
nod2S" [as
nod29" [a4
nod30" [a3
nod3l- [a2
nod32- (al
iO '" [Ie *
*
1<
*
*
*
*
*
rotO
rotl
rot2
rot3
rot4
rotS
rot6
rot7
*
10 J ,.
* lIe] ;
..
*
*
*
lIe]
i
lie];
lie];
lIe];
* Ile];
* lie);
* lie) i
10'" I( (jnod2S*/nod26*/nod27*/nod28*/nod29*/nod30*/nod3I*/nod32* liD]) ;
out7
Qut6
outS
out4
out3
out2
out!
outO
xrl
xr2
xrl
xr2
xrl
xr2
xrl
xr2
xrl
xr2
xrl
xr2
xrl
-------- 11;
/17 i
complmto;
/16;
complmto;
/15;
complmto;
/14;
complmto;
13;
comp1mtoi
12;
comp1mtoi
xr2 - complrnto;
xrl ... 10;
xr2 ... complrnto;
Figure 6.7 Barrel Shifter Boolean Equations (Continued)
June 1988
588
Signetics Application Specific Products
Designing with Programmable Macro Logic
"
Simulation input for BRLSHFT
>
(-------- INPUTS-------- >
<
Illlllllllllhlhhhhhhhhhh
hhhhhhhhllllhlhhhhhhhhhh
hlhlhlhlllllhlhhhhhhhhhh
lhlhlhlhllllhlhhhhhhhhhh
-----------------------------
B I /B
~ShiftO
- Input 00"
Fr"
AA
55H
Illllllhllllhlhhhhhhhhhh -------- "ShiftO -
lllllllhllhlhlhhhhhhhhhh
lllllllhlhllhlhhhhhhhhhh
lllllllhlhhlhlhhhhhhhhhh
lllllllhhlllhlhhhhhhhhhh
lllllllhhlhlhlhhhhhhhhhh
lllllllhhhllhlhhhhhhhhhh
lllllllhhhhlhlhhhhhhhhhh
Illlhhhhhlllhlhhhhhhhhhh
hlhlhlhlllhlhlhhhhhhhhhh
Illlllllllllhlhhhhhhhhhh
Illllllllllhh!hhhhhhhhhh
Illlhhhhllllhlhhhhhhhhhh
h!hlhlhl!ll!llhhhhhhhhhh
Illllllhllllllhhhhhhhhhh
llllllhlllllllhhhhhhhhhh
lllllhllllllllhhhhhhhhhh
llllhlllllllllhhhhhhhhhh
lllhllllllllllhhhhhhhhhh
llhlllllllllllhhhhhhhhhh
lhllllllllllllhhhhhhhhhh
hlllllll!lllllhhhhhhhhhh
Illlllllllllhlhhhhhhhhhh
llllllllllllhhhhhhhhhhhh
QUIT
Input 01N
-------1
-------------------------------------------------- Shift4 - Input OF-------- Shiftl - Input AA
-------- ·ShiftO - Input DO·
-------- Complement output
-------- "ShiftO - Input OF"
-------- start latch test·
-------- continue ...
-------------------------------------------------- end"
-------- ~un-latch output~
-------- ~ 3-state outputs
H
H
H
H
H
H
H
H
Figure 6.8 Barrel Shifter Simulation Input File
June 1988
589
N
Signetics .Application Specific Products
Designing with Programmable Macro logic
PLHSSOI
BRLSHFT
Time - 14: 12: 36 Date - 9/14/1987
(--------INPUTS--------) < B,/B > < XOR
> < /0,0 >
222211111111111
321098765432109876543210 76543210 76543210 76543210
000000000000101111111111
111111110000101111111111
101010100000101111111111
010101010000101111111111
000000010000101111111111
000000010010101111111111
000000010100101111111111
000000010110101111111111
000000011000101111111111
000000011010101111111111
000000011100101111111111
000000011110101111111111
000011111000101111111111
101010100010101111111111
000000000000101111111111
000000000001101111111111
000011110000101111111111
101010100000001111111111
000000010000001111111111
000000100000001111111111
000001000000001111111111
000010000000001111111111
000100000000001111111111
001000000000001111111111
010000000000001111111111
100000000000001111111111
000000000000101111111111
000000000000111111111111
HHHHLLLL
LLLLHHHH
LHLHLHIJ{
HLHLHLHL
HHHHHILL
HHHHLHU,
HHHHUHL
HHHHLLLH
HHHLLU..L
HHLHLLLL
HLHHLLLL
LHHHLLLL
LLLLLLLL
HLHLHLHL
HHHHLLLL
HHHHULL
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHLLLL
HHHHUll.
00000000
00000000
LLLLLLLL
HHHHHHHH
HLHLHLHL
LHLHLHLH
LLLLLLLH
LLLLLLHL
LLLLLHLL
LLLLHLLL
LLLHLLLL
LLHLLLLL
LHLLLLLL
HLLLLLLL
HHHHILLL
LHLHLHLH
LLLU.J...LL
HHHHHHHH
LLU.HHHH
LLLLHHHH
LLI.LHHHH
LLLLHHHH
LLLLHHHH
LLI.LHHHH
LU..LHHHH
LLI.LHHHH
LLLLHHHH
LLLLHHHH
LLLLLLLL
TRACE TERMS
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
ULLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLI.LHHHH
u.LLHHHH
LLI.LHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LU.LHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
I/O CONTROL LINES
DESIGNATED I/O USAGE
ACTUAL I/O USAGE
PINLIST ...
14 13 12 11 10 09 07 06 05 04 03 02 01 52 51 50 49 48 47 45 44 43 42 41
18 17 16 15 40 39 38 37 36 35 33 32 31 30 29 28
27 26 25 24 23 22 21 19
Figure 6.9 Barrel Shifter Simulation Log File
June 1988
590
Signetics Application Specific Products
Designing with Programmable Macro Logic
12 BIT COMPARATOR WITH
DUAL 1 OF 8 DECODERS
File NCiII1e : 12.BITCMP
Date , 9/15/1987
Time , 9,36,0
L I S T UUIUUIUUUIUU
UUIUUUII'UUUiI PIN
Right
Left
LABEL
VCC
B6
B7
B8
B9
B10
Bll
ENCOIIP
••
••
••
••
••
DCDREN
RW
N/C
wo
GND
FNC **PIN
+5V ** 8-1
I
9-1
I
10-1
I
11-1
I
12-1
I
13-1
I
14-1
15-1
16-1
I
17-1
B
18-1
a
19-1
OV
20-1
PIN*- FNC
+5V
P
L
H
S
5
0
1
Bottom
FNC ""·PIN
LABEL
.'It
WI
W2
W3
W4
W5
W6
W7
RO
R1
R2
R3
R4
R5
•• a
•• a
•• a
** /0
** /0
/0
** /0
'It*
a
a
a
a
•• a
•• a
21-1
22-1
23-1
24-1 . p
25-1
L
26-1
H
27-1
S
28-1
5
29-1
0
30-1
1
31-1
32-1
33-1
1-46
1-45
1-44
1-43
1-42
1-41
1-40
1-39
1-38
1-37
1-36
1-35
1-34
**
lABEL
**vee
••
••
••
••
I
I
I
I
I
**Al
**AO
*'It
/0
**CMPOUT
I
•• I
•• I
•• a
•• a
** ov
**A4
**A)
**A2
**DA2
**DA1
**DAD
**R7
**R6
**GND
Top
PIN"'" FNC
IIII111- 1
I-52
I-51
I-50
1-49
1-48
1-47
I
•• I
•• I
•• I
I
I
I
I
The comparator compares 12 bits on inputs
A11 - AO to inputs B11 - BO when the input
'ENCMP" is High. Output 'CMPOUT will
become active-Low when all 12 bits of the A
input match the B. Selection between the two
decoders is done with input 'R/W'. Only one
output may be active (Low) at a time. Although currently separate functions, the decoder enable may be derived internally from
'CMPOUT freeing 2 bidirectional pins which
together with available foldback NAND terms,
may be used to incorporate a third function.
LABEL
-*S5
*'*B4
**83
AIl_R8~
uB2
**B1
**BO
••
••
••
••
Two functions that are very often associated
with controlling I/O parts are address comparison and address decoding. In this example, both functions are programmed into a
PLHS501 using 52 out of the 72 foldback
NAND terms.
COMPRRE
**All
**A10
/
**A9
**AS
ENCOMP
*"'A7
**A6
•• I
CMPOUT
B11-68
"'*AS
DR2
DRI
DR8
Figure 6.10 12-BIt Comparator Pin Llat
DUAL
W7-WO
1 OF 8
R7-RO
.II-.!
DCOREN
Figure 6,11 12-Blt Comparator with
Dual 1 - 8 Decoders Block Diagram
June 1988
591
Signetlcs Application Specific Products
Designing with Programmable Macro logic
File Name : 12BITCMP
Date , 9/15/1987
Time: 9:36:17
@DEVICE TYPE
PLHS501
@DRAWING
@REVISION
@DATE
@SYMBOL
@COMPANY
@NAME
@DESCRIPTION
l2-bit address comparator and dual 1 of 8 decoders
@INTERNAL NODE
axbO, axbl, axb2, axb3, axb4 I axbS, axb6;
axb7 ,axb8 I axb9 I axblO, axbll i
@COMMON PRODUCT TERM
adO-/da2* Idal* /daO*dcdren;
adl-/da2*/dal* daO*dcdreni
ad2-/da2* dal*/daO*dcdren;
ad3-/da2* dal* daO*dcdreni
ad4- da2*/dal*/daO*dcdreni
adS- da2*/dal* daO*dcdren;
ad6- da2* dal*/daO*dcdreni
ad7- da2'" dal* daO*dcdrenj
@I/O DIRECTION
@I/O STEERING
@LOGIC EQUATION
MI2-Bit Address Comparator
H
axbO .. aO*/bO + /aO*bO;
axbl - al*/bl + /al*bl;
axb2 .. a2*/b2 + ja2*b2i
axb3 "" a3*/b3 + /a3*b3;
axb4 .. a4*/b4 + /a4*b4;
axb5 - as*/bS + /a5*b5;
axb6 .. a6*/b6 + /a6*b6;
axb? .. a7*/b7 + /a7*b7;
axb8 .. a8*/b8 + laS*ba;
axb9 - a9*jb9 + /a9*b9;
axblO - aID*/bIO + laID*bIO;
axbll - all * /bll + lall *bll;
T803180S
cmpout - /(/axbO*/axbl*/axb2*/axb3*/axb4*/axbS*/axb6*/axb7*/axbS*/axb9*
/axbID*/axbll*encomp);
"Dual I of a decoders
-
da2-daO are address inputs
dcdren is an enable input
rw selects which group of S outputs r7-rO or w7-wD
will have the decoded active low output-
-
w7
w6
wS
w4
w3
w2
wI
wO
...
...
...
...
...
...
l(ad7*/rw);
/(ad6*/rw);
l(adS*/rw);
l(ad4*/rw);
l(ad3*/rw);
l(ad2*/rw);
I(adl*/:rw) i
l(adO*/rw);
r7
r6
rS
r4
r3
r2
rl
rO
..
...
...
lead7'"
l(ad6*
leadS*
/(ad4*
lead3*
/(ad2*
leadl'"
l(adD*
rw);
rw);
rw) i
rw) i
rw);
rw);
rw) i
rw);
Figure 6.12 12-Bit Comparator Boolean Equations
June 1988
592
Signetics Application Specific Products
Designing with Programmable Macro Logic
Simulation inputs for 12BITCMP
(--------INPUTS--------)
2222HHHHHHHHHHH
<
B,/B
>
32HL98765432HL98765432HL 765432HL
~disable compH
-LLH-LLL -enable camp"
-LLH-LLL camp AA
-LLH-LLL "camp 55"
-LLH-LLL camp FF"
-LLH-LLL -A not equal 8
IIITUrrrrIITrrrrrIIITII -LLL-LLL
rrfrrTTITITTITIIITTTITTT
HLHLHLHLHLHLHLHLHLHLHLHL
LHLHLHLHLHLHLHLHLHLHLHLH
HHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHLHHHHHHHHHHH
H
H
H
N
IITITITTITITTUTTIIIITTI -LHL-LLL "enable decoder W"
IT IT IT T IT IT T IT T II T IT T IT I
TIITTITTTTTITITTTTTITITI
TTTTT!!!!!!!!!!!!!!!!!!!
I IT T IT
IT II IT T IT T IT I
-HHL-LLL -enable decoder R"
-HHL-LLH "count 1"
-HHL-LHL
2"
IT T IT
-HHL-LHH
3
TTITTTTTITTTTTTITTTIIITJ
-HHL-HLL
4"
TITTTITTIITITIITrTTITTIT
-HHL-HLH
5"
TIIIT!!!!!!!!!!!!!!!!!!!
-HHL-HHL
TIT IT IT II TIT II IT TIT TII II -HHL-HHH
IT II IT IT IT IT T TIT II II IT IT -LHL-HHH
QUIT
H
6"
r
~
enable decoder W
Figure 6.13 12-Bit Comparator Simulation Input File
PLHS501
12BITQI.P
Time"" 15: 0: 58 Date""' 9/14/1987
(--------INPUTS--------) ( B,/E ) (XOR
222211111111111
) ( /0,0)
TRACE TER!>'.5
321098765432109876543210 76543210 76543210 76543210
000000000000000000000000
000000000000000000000000
101010101010101010101010
010101010101010101010101
111111111111111111111111
111111111111011111111111
000000000000000000000000
000000000000000000000000
000000000000000000000000
ODOOOOOOOOOOOOOOOOOOOOOO
000000000000000000000000
000000000000000000000000
000000000000000000000000
000000000000000000000000
000000000000000000000000
000000000000000000000000
HOOOHOOO
HOOILOOO
ROOILOOO
ROOILOOO
HOOILOOO
HOOIHOOO
HOI0HOOO
H110HOOO
HI10H001
HII0H010
HIIOH011
HI10HI00
HI10HI01
HI10HI10
Hl10Hl11
HOIOHlll
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHL
HHHHHHLH
HHHHHLHH
HHHHLHHH
HHHLHHHH
HHLHHHHH
HLHHHHHH
LHHHHHHH
HHHHHHHH
------------------------ -------OlllOlII
OIIlOHI
HHHHRHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHL
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
HHHHHHHH
LHHHHHHH
I/O CONTROL LINES
DESIGNATED I/O USAGE
ACTUAL I/O USAGE
PINLIST ..
14 13 12 11 10 09 07 06 05 04 03 02 01 52 51 SO 49 48 47 45 44 43 42 41
18 17 16 15 40 39 38 37 36 35 33 32 31 30 29 28
27 26 25 24 23 22 21 19
Figure 6.14 12-Bit Comparator Simulation Log File
June 1988
593
Signetics Application Specific Products
Designing with Programmable Macro logic
8-BIT CARRY LOOK-AHEAD
ADDER
This function may be used as part of an ALU
design or simply to off-load a microprocessor.
Figure 6.16 is a block diagram showing the
individual components needed for each bit.
A carry input (CO) is provided along with a
carry output (C8). The result of an addition
between the inputs A7 - AO and 87 - 80 occurs on outputs SUM7 - SUMO.
File Name , 8BITADDR
Date
9/15/1987
Time , 9,37,21
,
# # # I # # I # II # II IIII1111 PIN
L I S T #1###1111111111111111
Left
LABEL
VCC
A2
A3
M
AS
A6
A7
N/C
N/C
N/C
N/C
C8
Right
FNC **PIN
** 8-1
9-1
10-1
11-1
12-1
•• r
13-1
14-1
15-1
•• B
16-1
•• B
17-1
B
18-1
0
19-1
ov
20-1
+5V
GND
P
L
H
PIN"'''' FNC
1-46
+5v
1-45
r
1-44
r
1-43
r
1-42
r
1-41
I
1-40
/0
1-39
/0
1-38
/0
1-37
/0
1-36
0
1-35 •• 0
1-34
ov
LABEL
"'*vee
....
"'*N/C
**N/C
**N/C
*"'N/C
..
**N/C
**N/C
**N/C
**N/C
*"'N/C
* "'SUM?
**SUM6
**GND
Bottom
LABEL
Top
F~C
•• 0
•• 0
•• 0
N/C
N/C
N/C
N/C
N/C
N/C
N/C
** /0
** /0
10
•• /0
•• 0
SUMO
SUM1
SUM2
SUM3
SUM4
0
0
•• 0
•• 0
•• 0
SUMS
*"'PIN
21-1
22-1
23-1
24-1
25-1
26-1
27-1
28-1
29-1
30-1
31-1
32-1
33-1
PIN"'''' FNC
P
L
1- 7
1- 6
1- 5
1- 4
111- 1
I-52
I-51
I-50
1-49
1--48
1-47
....
r
r
r
LABEL
"''''AI
'""'AD
*"B7
**B6
..
r
....
..
r
r
r
**B5
**B4
**B3
**B2
"'"B1
**BO
""CO
**N/C
**N/C
Figure 6.15 8-Bil Adder Pin Lisl
NOTES,
G1' "" G4 + P4· G3 + P4· P3'" G2 + P4 '" P3· P2 '" G1;
P1' = P4· P3'" P2'" Pl
G2' "" G8 + PB· G7 + P8 '" P7 '" G6 + PS'" P7· PS* G5;
P2' = PS* P7*PS*PS
C1 = G1 +- P1 '" co.
C2=G2+P2*G1 +P2*P1 * eo;
C3 =G3 + P3 *G2 + P3 '" P2*G1 + P3* P2· P1 • co:
C4 =G1' +P1' "eo;
CS = G5 + P5 '" G1' + P5 '" P1'" co;
C6 = G6 + P6 '" G5 -+ P6" P5 '" G1' + P6 '" P5 '" P1' '" co;
C7 = G7 + Pl'" G6 + P7 '" P6 '" G5 + P7 '" P6" P5 '" G1' + P7" P6 '" P5 '" Pl' '"
CB = G2' + P2'" G1' + P2' '" P1'" co;
co;
Figure 6.16 8-Bil Carry Look-Ahead Adder Block Diagram and Equations
--------------------~
June 1988
594
Signetics Application Specific Products
Designing with Programmable Macro Logic
File Name : 8BITAl)DR
Date , 9/15/1987
Time, 9,37,36
p6 - /Ua5'/b5);
g6 - /gn6;
@DEVICE TYPE
PLHS501
gn7 - /(a6'b6);
p7 - /Ua6'/b6);
g7 - /gn7;
@DRAWING
@REVISION
@DATE
@SYMBOL
gnS - /(a7'b7);
p8 - /Ua7'/b7);
gB .. /9nS;
@COMPANY
@NAME
@DESCRIPTION
8 B1 t Carry Look-Ahead Adder
@INTERNAL NODE
"level-l fUnctions"
g8, 91, 92, 93, 94, 95, 96, 97;
pS, pl., p2, p3, p4, pS, p6, p7;
gn8 ,gn1,9n2,9n3,9n4 ,9n5,9n6 ,gn7;
c1,c2,c3,c4,c5,c6,07 i
9 1_ 1 ,9 2_ 1 ;
91_1 .. g4 + p4*g3 + p4*p3*g2 + p4*p3*p2*gl.;
92_1 .. 98 + p8*g? + pB*p7"'g6 + p8*p7*p6*g5;
.. carry information"
c1 .. 91 + pl*cO;
c2 .. 92 + p2"'gl + p2*pl*cO,.
c3 .. 93 + p3*g2 + p3*p2*gl + p3*p2*pl.*cO;
c4 .. g1_1 + p4*p3*p2*pl*cOi
c5 .. 95 + pS*gl_l + p5*p4*p3*p2*pl*cO;
c6 .. g6 + p6 11 g5 + p6*p5*91_1 + p61rp5"'p4wp3"'p2"'pl"'cO;
c7 - g7 + p7"'g6 + p7"'p6"'g5 + p7*p6*p5*gl_1 +
p7 *p6 wp5*p4 *p3 1rp2*pl *cO;
c8 - g2_1 + p8*p7*p6*p5 1r gl_l + p8 wp7*p6*pS1rp4*p3*p2.pl'/1'cO I
@COMMON PRODUCT TERM
@I/O DIRECTION
@I/O STEERING
@LOGIC EQUATION
Mlevel-O functions"
gn1 - /(aO'bO);
p1 - /UaO'/bO);
gl - /gn1;
"addition functions"
sumO
xrl - cO;
xr2 - pI * gnl;
sum1
xrl - e1;
xr2 - p2 '/I' gn2;
sum2
xr1 ... e2;
gn3;
xr2 - p3
sum3
xr1 - c3;
xr2 - p4 , gn4;
sum4
xr1 - c4;
xr2 - pS
gn5;
sum5
xxI - e5;
xr2 - p6 '/I' gn6;
sum6
xrl - c6i
xr2 - p7 * gn7;
sum7
xrl - c7;
xr2 ... p8 * gn8;
gn2 - /(alOb1);
p2 - /ualO/b1);
g2 - /gn2;
,
gn3 - /(a2'b2);
p3 - /Ua2'/b2);
93 - /9'n3;
.
gn4 - /(a3*b3);
1>4 -
/Ua3'/b3);
g4 - /gn4;
gn5 - /(a4'b4);
p5 - /Ua4'/b4);
g5 - /gn5;
9n6 .. /(a5*b5) ..
Figure 6.17 8-Blt Adder Boolean Equations (Continued)
Figure 6.17 8-Blt Adder Boolean
Equations
8 Bit Adder Simulation input
<-------- INPUTS-------- > < B I IB >
2222HHHHHHHHHH1
321098765432109876543210 76543210
IT IT
IT IT I I IT T r:r IT HHHHHHH
HHHHHHHLLLLLLLLHLHHHHHHH
HHHHHHHU.I..LI.J...LHLLHHHHHHH
LHHHHHHHu..LLLLLLHHHHHHHH
-----------------------------
.. 0
.. 0
"I
.. 0
+ 0"
+ FF"
+ FF"
+ 7F + CARRY IN"
HLHLHLHLLHLHLHLHLHHHHHHH -------- • AA + 55·
HLHLHLHLLHLHLHLHHHHHHHHH -------- • AA + 55 + CARRY IN"
LLHHHHHHLJ..LHHHHHLHHHHHHH -------- "3F + IF"
QUIT
Figure 6.18 8-Bit Adder Simulation Input File
June 1988
595
Signetics Application Specific Products
Designing with Programmable Macro logic
PLHS501
8BITADDR
Time - 15,41,33 Date - 9/14/1987
(--------INPUTS--------) ( B,/B ) (XOR
>(
/0,0)
TRACE TERMS
222211111111111
321098765432109876543210 76543210 76543210 76543210
000000000000000001111111 HHHHLLLL LLLLLLLL LLLLHHHL
111111100000000101111111 HHHHLLLL HHHHHHHH LLLUlHHL
111111100000001001111111
011111110000000011111111
101010100101010101111111
101010100101010111111111
001111110001111101111111
HHHHLLLL
HHHHLLLL
HHHHLLLL
HHHHLLLL
HHHHLLLL
LLLLLLLL
HLLLLLLL
HHHHHHHH
LLLLLLLL
LHLHHHHL
------------------------ -------OOOOOOOO
OOOOOOOO
LLLLHHHH
LLLLHHHL
LLLLHHHL
LLLLHHHH
LLLLHHHL
I/O CONTROL LINES
DESIGNATED I/O USAGE
ACTUAL I/O USAGE
PINLIST ...
14 13 12 11 10 09 07 06 05 04 03 02 01 52 51 50 49 48 47 45 44 43 42 41
18 17 16 15 40 39 38 37 36 35 33 32 31 30 29 28
27 26 25 24 23 22 21 19
Figure 6.19 8-Bit Adder Simulation log File
June 1988
596
Signetics Application Specific Products
Designing with Programmable Macro Logic
32- to 5-BIT PRIORITY
,
ENCODER
File Name
ENCODER
Date: 9/15/1987
Time: 9,38,43
# ## #lU# 1## #111111111 PIN
L I S T 111111111111111111##1
Left
LABEL
VCC
!l8N
!l9N
I20N
I21N
122N
Right
FNC **PIN
+5V ** 8-1
I
H
I23N
I24N
I25N
I26N
127N
N/C
GND
"
"
"
I
I
I
"
1
1
0
OV
10-1
11-1
12-1
13-1
14-1
15-1
16-1
17-1
18-1
19-1
20-1
L
H
S
5
PIN**
1-46
1-45
1-44 "
1-43
1-42
1-41 "
1-40 "
1-39 "
1-38 "
1-37
1-36
1-35
1-34
FNC
LABEL
+5v 1<-I < XOR
>(
/0,0
>
TRACE TERMS
32109876543210987654:3210 76543210 76543210 76543210
111111111111111111111111
111111111111111111111111
111111111111111111111110
111111111111111111111111
111111111111111111111111
111111111111111111111111
111111111111111111111111
111111111111111111111111
111111111111111111111111
111111111111111111111111
011111111111111111111111
101111111111111111111111
11011111111111111111111l
111011111111111111111111
111101111111111111111111
111110111111111111111111
111111011111111111111111
111111101111121111111111
111111110111111111111111
111111111011111111111111
111111111101111111111111
111111111110111111111111
111111111111011111111111
111111111111101111111111
111111111111110111111111
111111111111111011111111
111111111111111101111111
111111111111111110111111
111111111111111111011111
111111111111111111101111
111111111111111111110111
111111111111111111111011
111111111111111111111101
111111111111111111111110
111111111111111111111111
000000000000000000000000
111011101111011110111011
11111111
11110111
11111111
11111011
11111101
11111110
01111111
10111111
11011111
11101111
11111111
11111111
11111111
12111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
11111111
00000000
11101101
-----------------------II II II II
IIIIIIII
LHHHHHLH
LLLLLL1IL
LHHHHHHL
LLLLLHHL
LLLLHLHL
LLLLHHHL
LLLHLLHL
LLLHLHHL
LLLHHLHL
LLLHHHHL
LLHLLLHL
LLHLLHHL
LLHLHLHL
LLHLHHHL
LLHHLLHL
LLHHLHHL
LLHHHLHL
LLHHHHHL
LHLLLLHL
LHLLLHHL
LHLLHLHL
LHU,HHHL
LHLHLLHL
LHLHLHHL
LHLHHLHL
LHLHHHHL
LHHLLLHL
LHHLLHHL
LHHLHLHL
LHHLHHHL
LHHHLLHL
LHHHLHHL
LHHHHLHL
LHHHHHHL
LHHHHHLH
LLLLLLHL
LLLLHLHL
LILLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
UJ..,LHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
u..r...LHHHH
LLLLHHHH
l.LLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
I/O CONTROL LINES
DESIGNATED I/O USAGE
ACTUAL I/O USAGE
PINLIST ...
14 13 12 11 10 09 07 06 05 04 03 02 01 52 51 SO 49 48 47 45 44 43 42 41
18 17 16 15 40 39 36 37 36 35 33 32 31 30 29 28
27 26 25 24 23 22 21 19
Figure 6.24 Encoder Simulation Log File
June 1988
601
Signetics Application Specific Products
Designing with Programmable Macro Logic
8-BIT SHIFT REGISTER WITH
SEQUENCE DETECTOR
File Name : BBTSHFT
This example demonstrates an application
using D type edge-triggered flip-flops. Six
NAND gates are used for each flip-flop (Figure 3.2). Note that to add an asynchronous
reset andlor set to any flip·flop requires no
additional gates. Also, every flip-flop must
have a reset or set line to initialize it. Without
being initialized, the simulator will not be able
to determine the output states as it could
power-up in either a set or reset condition. An
uninitialized flip-flop will cause AMAZE 1.6 to
display a message indicating the outputs are
not stabilized within a certain time period.
Date: 9/15/1987
Time: 9,41,16
L I S T ###1#1111#1##########
##1#1##1#####1 # #####1 PIN
Left
*'
N/C
N/e
N/C
H
I
•• I
10-1
H-I
DATA
*' I
.. I
0
0
0
0
*' 0
eLK.
RST
DETl
DETIN
DE'l'2
As can be seen from the block diagram
(Figure 6.26) this design consists of an 8-bit
shift register, 3-bit ripple counter and 2 flipflops that are set only upon detection of
specific patterns. The patterns are read from
the 0 and ON outputs of the shift register.
Since the input to the second flip-flop has the
output of the first flip-flop as a product term,
detection of the first pattern is a requirement
for the detection of the second.
PIN"''' FNC **
FNC "''''PIN
+5V 'It,.
8-1
LABEL
vee
DET2N
N/C
ov
GND
12-1
13-1
14,-1
15-1
l6-1
17-1
18-1
19-1
20-1
L
H
+5V
1-46
I
1-45
I
1-44
1-43 •• I
1-42
I
1-41
I
1-40
/0
1-39
/0
1-38
/0
1-37
/0
1-36
0
1-35 **0
1-34
ov
.*
**N/C
* "'N/C
**N/C
*"'N/C
**N/C
"N/e
"'''-CQ2
""'COl
**CQO
**07
**06
**GND
Top
Bottom
21-1
22-1
23-1
24-1
25-1
26-1
27-1
28-1
29-1
30-1
31-1
32-1
33-1
0
**0
0
/0
/0
/0
/0
**0
*' 0
0
0
*' 0
**0
N/C
N/C
N/C
N/e
N/e
N/C
N/e
00
01
02
03
04
05
PIN"''"' FNC
FNC **PIN
LABEL
L
H
1- 7
1- 6
1- 5
1- 4
1- 3
1- 2
1- 1
I-52
I-51
I-50
1-49
1-48
1-47
** I
** I
*' I
•• I
.*
.*
I
.. I
I
LABEL
**N/C
**N/C
**N/C
**N/e
**N/e
**N/C
**N/C
**N/C
**N/C
"'*N/C
*1 < /0,0 >
TRACE TERMS
321098765432109876543210 76543210 76543210 76543210
000111111111111111111111
010111111111111111111111
001111111111111111111111
100111111111111111111111
110111111111111111111111
101111111111111111111111
111111111111111111111111
100111111111111111111111
110111111111111111111111
101111111111111111111111
111111111111111111111111
100111111111111111111111
110111111111111111111111
101111111111111111111111
111111111111111111111111
100111111111111111111111
110111111111111111111111
101111111111111111111111
111111111111111111111111
101111111111111111111111
111111111111111111111111
100111111111111111111111
110111111111111111111111
1011111111111l11l1111111
111111111111111111111111
100111111111111111111111
110111111111111111111111
101111111111111111111111
111111111111111111111111
100111111111111111111111
110111111111111111111111
101111111111111111111111
111111111111111111111111
100111111111111111111111
110111111111111111111111
100111111111111111111111
110111111111111111111111
011111111111111111111111
HLHLLLlL
HLHLLLlL
HLHlLLLL
HLHLLLLL
HLHLI...LLH
HLHLJLLH
HLHLLLHL
HLHLLLHL
HLHLLLHH
HLHLLLHH
HLH1..1.H1.L
HLHLLHLL
HLl-lLLHLH
HLHLLHLH
HLHLLHHL
HLHLLHHL
HLHLLHHH
HLHLLHHH
HLLHLLLL
HU,HLLlL
HLLHLLLH
HLLHLLLH
HLLHLLHL
HU,HLLHL
HLLHLLHH
HLLHLLHH
HLLHLHLL
HLLHLHLL
HLLHLHLH
HILHLHLH
HLLHLHHL
HLLHLHHL
HLLHLHHH
HLLHLHHH
LHHLLLLL
LHHLLLLL
LHHLLLLH
HLHLLLLL
00000000
OOOOOOOO
LLLLLLLL
LLLLLLLL
LLLILLLL
lLLLLLLL
LLILLLLL
!.LLILLLL
llJ.J..J.L.LH
L..LLLLLLH
ILULLHL
LLLLLLHL
LLLLLHLH
LLLLLHLH
LlJLHLHL
LLLLHLHL
LLLHLHLH
LLLHLHLH
LLHLHLHL
LLHLHLHL
LHLHLHLH
LHLHLHLH
HLHLHLHH
HLHLHLHH
LHLHLHHL
LHLHLHHL
HLHLHHLH
HLHLHHLH
LHLHHLHL
LHLHHLHL
HLHHLHLH
HLHHLHLH
LHHLHLHL
LHHLHLHL
HHLHLHLH
HHLHLHIJj
HLHLHLHL
HLHLHLHL
LHLHLHU,
LIJ.J:..LLLL
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LILLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
u...LLHHHH
llUHHHH
LLLLHHHH
LLLLHHHH
LILLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
I..J...LLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LU.LHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
LLLLHHHH
lLLLHHHH
LLLLHHHH
LLLLHHHH
UJ...LHHHH
I/O CONTROL LINES
DESIGNATED I/O USAGE
ACTUAL I/O USAGE
PINLIST ...
14 13 12 11 10 09 07 06 05 04 03 02 01 52 51 50 49 48 47 45 44 43 42 41
18 17 16 15 40 39 38 37 36 35 33 32 31 30 29 28
27 26 25 24 23 22 21 19
Figure 6.30 a-Bit Shifter Simulation Log File
June 1988
607
Signetics Application Specific Products
Designing with Programmable Macro logic
4·BIT SYNCHRONOUS
COUNTER
This counter produces a binary count on
outputs Count3 - CountO. Note the required
reset (RST) input to initialize all of the flipflops. The inputs for each flip-flop were first
determined by drawing the desired output
waveforms. Next, Karnaugh rnaps were used
to reduce the number of terms and determine
the logic equations for the input to each flipflop. This technique could be used to construct a counter whose outputs produce some
count other than binary.
The simulation only consists of a reset, followed by a number of clocks to count from 0
through 15 and back to o.
File Name : 4BTCOUNT
Date : 9/15/1987
Time: 9,57,5
#1#1#1#1# 1####1###### PIN
N/C
N/C
N/C
PIN"'*" FNC 1<*
FNC **PIN
+5V
I
I
.* I
.* I
VCC
CLK
RST
N/C
LIS T ##########1######1##1
Right
Left
LABEL
8-1
9-1
10-1
11-1
12-1
13-1
14- (
a
COUNTO
a
COUNT1
COUNT2
COUNT3
TC
0
.* 0
GND
**
0
QV
L
H
S
15-1
16-1
17-1
18-1
19-1
20-1
Bottom
LABEL
** FNC **PIN
21-1
N/C
** 0
22-1
**0
N/C
23-1
N/C
** 0
24-1
N/C
** 10
25-1
N/C
** /0
26-1
N/C
** /0
27-1
N/C
** /0
28-1
0
N/C
0
29-1
N/C
30-1
N/C
0
31-1
N/C
** 0
32-1
*. 0
N/C
33-1
**0
N/C
1-46
+5v
I
1-45
1-44
1-43
1-42 *. I
1-41
I
1-40
10
1-39
10
1-38
10
1-37
10
0
1-36
1-35 ** 0
1-34
OV
**N/C
**N/C
**N/C
**N/C
**N/C
'**N/C
**N/C
**N/C
**NjC
**N/C
**GND
TOp
LABEL
PIN"'* FNC
P
L
H
1- 7
1- 6
1- 5
111- 2
1- 1
I-52
I-51
I-so
1-49
1-48
1-47
I
I
**N/C
**N/C
**N/C
**N/C
**NjC
**N/C
** I
** I
** I
**
**
I
I
**NjC
**N/C
**N/C
**N/C
**NjC
**N/C
**N/C
Figure 6.31 4-Bit Counter Pin List
June 1988
608
LABEL
**VCC
**N/c
Signetics Application Specific Products
Designing with Programmable Macro Logic
File Name : 4BTCOUNT
Date: 9/15/1987
Time: 9:57:28
@DEVICE TYPE
PLYSSOI
@DRAWING
@REVISION
@DATE
@SYMBOL
@CO!-f.PANY
@NAY'"
@DESCRIPTION
4 bit synchronous counter
@INTERNAL NODE
datal, data2, data3 i
csnD, crnD, eqO I cqnO i
esol, crnLcql ,egnl i
csn2, crn2 ,cq2 ,cqn2 i
esn3 ,ern3, cq3 ,egoJ i
@COMMON PRODUCT TER.'1
@I/O DIRECTION
@I/O STEERING
@LOGIC EQUATION
NINPUTS FOR EACH FLIP-FLOp·
DATAl DATA2 DATAJ -
[(CQI-CQNO}+(CQNI-CQO)];
[CCQO*CQl*CQN2)+(CQNO*CQ2)+(CQNl*CQ2)] i
[(CQN2*CQ3)+(CQNO*CQ3)+(CQO*CQl*CQ2*CQN3)+(CQNl*CQ3)] i
"4 D-·TYPE FLIP FLOPS CONNECTED AS A SYNCHRONOUS COUNTER"
CSND
eRNO
CQO
CQND
- /(CLK*RST*(/(CSNO*(/[CQNO*RST*CRNO]»»
/(CSNO*CLK* (/(CQNO*RST*CRNO] » i
- /(CSNO-CQNO);
"" /(CRNO*CQO*RST) i
i
=
CSNl
CRNI
CQI
CONl
=
»» ;
CSN2
CRN2
CQ2
CQN2
..
-
/(CLK*RST* (/(CSN2* (/[DATA2*RST*CRN2) ») ) i
/(CSN2*CLK* (/ [DATA2*RST*CRN2] ) ) i
/(CSN2-CQN2);
/(CRN2*CQ2*RST);
/(CLK*RST* (/(CSNl* (/ [DATA1*RST*CRNl]
- /(CSNl>CLK-(/[DATAI'RST-CRNI]));
- /(CSNI-CQNI);
- /(CRNl*C01*RST) i
CSN3CRN3 CQ3 CQN3 -
/{ CLK*RST'" (/{CSN3* (/[DATA3*RST*CRN3]
/(CSN3*CLK"'(/[DATA3*RST*CRN3]»;
/(CSN3-CQN3);
/(CRN3*CQ3*RST) i
»»;
"Connection to output pinscountO-cqO;
countl-cql;
count2-cq2 ;
count3-cq3 ;
-TERMINAL COUNT PIW
TC-(CQO*CQ1*CQ2*CQ3) ;
Figure 6.32 4-Bit Counter Boolean Equations
June 1988
609
Signetics Application Specific Products
Designing with Programmable Macro Logic
4 Bit Synchronous Counter Simulation Input
HHHHLLHHHHHHHHHHHHHHHHHH --------
HRESET~
HHHHHLHHHHHHHHHHHHHHHHHH -------HHHHHHHHHHHHHHHHHHHHHHHH --------
H
COUNTl ~
HHHHHLHHHHHHHHHHHHHHHHHH -------HHHHHHHHHHHHHHHHHHHHHHHH -------- .. COUNT2"
HHHHHLHHHHHHHHHHHHHHHHHH -------HHHHHHHHHHHHHHHHHHHHHHHH -------- .. COUNT3"
HHHHHLHHHHHHHHHHHHHHHHHH --------
HHHHHHHHHHHHHHHHHHHHHHHH -------- .. COUNT4 ..
HHHHHLHHHHHHHHHHHHHHHHHH -------HHHHHHHHHHHHHHHHHHHHHHHH -------- .. COUNTS"
HHHHHLHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHH
HHHHHLHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHH
HHHHHLHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHH
HHHHHLHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHH
HHHHHLHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHH
----------- ~--- .. COUNT6"
--------------- ~ COUNT? ~
--------------- ~ COUNTS ~
--------------- ~ COUNT9~
--------------- ~ COUNTIO
HHHHHLHHHHHHHHHHHHHHHHHH -------HHHHHHHHHHHHHHHHHHHHHHHH --------
~COUNTll
U
U
HHHHHLHHHHHHHHHHHHHHHHHH -------HHHHHHHHHHHHHHHHHHHHHHHH -------HHHHHLHHHHHHHHHHHHHHHHHH --------
~ COUNT12-
HHHHHHHHHHHHHHHHHHHHHHHH --------
~ COUNT13-
HHRHHLHHHHHHHHHHHHHHHHHH -------HHHHHHHHHHHHHHHHHHHHHHHH --------
W
COUNT14
~
HRHHHLHHHHHHHHHHHHHHHHHH -------HHHHHHHHHHHHHHHHHHHHHHHH -------- "COUNTlSHHHHHLHHHHHHHHHHHHHHHHHH -------HHHHHHHHHHHHHHHHHHHHHHHH -------- - COUNTO"
QUIT
Figure 6.33 4-Bit Counter Simulation Input File
June 1988
610
Signetics Application Specific Products
Designing with Programmable Macro logic
PLHS501
1BTCOUNT
Time - 16: 57: 51 Date - 9/14/19R7
(--------INPUTS--------) ( BilE> < XOR > < /0,0 >
222211111111111
321096765432109676543210 76543210 76543210 76543210
111100111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
111110111111111111111111
111111111111111111111111
LLLLLLLL
LLLLLLLL
LLLHLLLL
LLLHLLLL
LLHLLLLL
LLHLLLLL
LLHHLLLL
LLHHLLLL
LHLLLLLL
LHLLLLLL
LHLHLLLL
LHLHLLLL
LHHLLLLL
LHHLLLLL
LHHHLLLL
LHHHLLLL
HLLLLLLL
HLLLLLLL
HLLHLLLL
HLLHLLLL
HLHLLLLL
HLHLLLLL
HLHHLLLL
HLHHLLLL
HHLLLLLL
HHLLLLLL
HHLHLLLL
HHLHLLLL
HHHLLLLL
HHHLLLLL
HHHHLLLL
HHHHLLLL
LLLLLLLL
------------------------ -------OOOOOOOO
OOOOOOOO
LLLLLLLL
u.u..r...u.L
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLU.LLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
=
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
LLLLLLLL
TRACE TERMS
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
ILLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHL
LLLLHHHH
LLLLHHHH
LLLLHHHL
I/O CONTROL LINES
DESIGNATED I/O USAGE
ACTUAL I/O USAGE
PINLIST ...
14 13 12 11 10 09 07 06 05 04 03 02 01 52 51 50 49 46 47 45 44 43 42 41
18 17 16 15 40 39 38 37 36 35 33 32 31 30 29 28
27 26 25 24 23 22 21 19
Figure 6.34 4-Bit Counter Simulation Log File
Bibliography
1. Cavalan, N., 1984, Third Generation PLD Architecture Breaks AND-OR Bottlenecks.
Proceedings of WESCON.
2. Wong, D., 1985, New Developments in Programmable Logic Devices. MIDCON Session 19. Chicago
3. Gheissari, A and Safari, B., 1987, High Speed, High Complexity PLDs and Applications.
ELECTRO-87 Session 35.
4. Hartman, Robert, May 1984, Estimating Gate Complexity of Programmable Logic Devices. VLSI Design. PP 100 - 103
5. Minnick, R.C., Dec. 1964, Cutpoint Cellular Logic, I.E.E.E. Transactions on Electronic Computers, PP 685 - 698.
6. Minnick, R.C., 1965, Cobweb Cellular Arrays, Proceedings of the Fall Joint Computer Conference, PP 327-341. Las Vegas, NV.
7. Canaday, R., 1965, Two-Dimensional Iterative Logic, Proceedings of the Fall Joint Computer Conference, PP 343 - 353. Las Vegas,
NV.
8. Gardner, P.L., Dec. 1970, Functional Memory and Its Microprogramming Implications, Technical Report TR.12. 091, IBM United
Kingdom Laboratories Limited. Hursley Park, Winchester Hampshire.
9. Roth Jr., C.H. Fundamentals of Logic Design, Second Edition, West Publishing Co., 1979, PP: 136.144. SI. Paul, MN.
June 1988'
611
Signefics
PLHS501
Application Notes
Vol. 2
Programmable Logic Devices
INTRODUCTION
This document is written assuming the
reader is familiar with Signetics PLHS501.
As well, we shall assume familiarity with
the predecessor document "Designing
with PML" and some exposure to
Signetics AMAZE software. The goal of
this document (i.e., Vol. 2) is to expand on
the original ideas and present some cookbook solutions to some useful design
problems. Vol. 2 also reflects nearly a year
of experience through the multitude of
design-ins achieved with the PLHS501.
In fact, several of the design solutions
April 1989
presented here were contributions from
our customers through our field applications organization. Designs we have encountered fell into a couple of interesting
categories. First, many users view the part
as a natural step in eliminating extraneous
board "glue" (10 or more chips) or eliminating multiple programmable array logic
devices (usually 3 to 5 units). Others
recognized the PLHS501 capabilities of
extremely wide logic functions and still
others chose to invent their own solutions
to standard bus interfaces. Commercially
available bus interfaces often "miss the
612
mark" and creative designers wish to implement exactly the functions they need in
a concise, effective manner. To date, we
have seen PLHS501 interfaces to the
VME Bus II, FAST Bus, NuBus, GPIB and
the IBM Micro Channel for the PS/2
system.
Before presenting these solutions however, it is appropriate to review the PML
basics and expand on a number of issues
which have been found to be important but
which were previously treated lightly.
Signetics
PLHS501
Application Notes
Vol. 2
Programmable Logic Devices
PLHS501 REVIEW
The PLHS501 is a 52-Pin, bipolar programmable logic device with a very powerful architecture. Unlike classic AND/OR
based architectures, its basic building
block is the NAND function which is configured in a foldback programming array.
By cascading successive NAND functions
through the array, both combinational and
sequential structures may be obtained.
ThePLHS501 has 24 dedicated inputs, 16
outputs (with several varieties) and eight
bidirectional pins. The internal NANOs
may be cascaded to any depth needed, to
achieve effective solutions using logic
structures such as muxes, decoders and
flip-flops without going off chip and wasting I/O pins to achieve cascading. To use
the PLHS501 effectively, the designer
should attempt to fold in function and
UM~~
remain within the chip as much as possible before exiting.
Figure 2-1 shows the PLHS501 architecture and illustrates several of the timing
paths for internal signals to give the designer a feeling for maximum time delay
within the part. These numbers are worst
case maximums, regardless of switching
directions, so the user may be assured
that in general, the PLHS501 will be faster
than these numbers.
The shorthand notation of Figure 2-1
hides something with which many designers have been impressed in the PLHS501,
the wide input NAND gates. Figure 2-2
shows just how wide the internal NANOs
are, from a logical viewpoint. Each NAND
can accommodate upt032 external inputs
and 72 internal inputs. Hence the part is
ideal for wide decoding of 32-bit address
and data busses. With 72 copies of the
wide NAND, the PLHS501 is often compared against low-end gate arrays. While
flatter4ing, this gives no usable method to
determine the degree to which functions
can be fit into the device. As a rule of
thumb, the PLHS501 can accommodate
three or more PLA devices and usually
four to five PAL® devices.
For any particular design, the user should
refer to Table 2-1 and evaluate his/her design incrementally, tallying against a 72
gate budget. This is a ballpark estimation
against the NAND capacity of the core of
the part. The clever designer will find additional function by correctly exploiting the
output logic.
_________________________ ,
I
22M (MAX) - - - - - - - - - - - - - - - - ,
I
I
i
OUTPUT
TERMS
Figure 2-1. PLHS501 Logic Diagram
PAL is a registered trademark of Monolithic Memories. Inc .. a wholly owned subsidiary of Advanced Micro Devices, Inc.
April 1989
613
-
INPUT
BUFf1:RS
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
Table 2-1. PLHS501 Gate Count Equivalents
FUNCTION
Gates:
NANOs
ANDs
NORs
ORs
INTERNAL
NAND
EQUIVALENT
1
1
1
1
COMMENTS
For
For
For
For
1 to
1 to
1 to
1 to
32
32
32
32
input variables
input variables
input variables
input variables
Decoders
3-to-8
4-to-16
5-to-32
8
16
32
Inverted inputs available
Inverted inputs available
Inverted inputs available (24 chip outputs
only)
Encoders
8-to-3
16-t0-4
32-t0-5
15
32
41
Inverted inputs, 2 logic levels
Inverted inputs, 2 logic levels
Inverted inputs, 2 logic levels, factored
solution.
Multiplexers
4-to-1
8-to-1
16-10-1
27-10-1
5
9
17
28
Inverted inputs available
Inverted inputs available
Inverted inputs available
Can address only 27 external inputs - more if
internal
Flip-Hops
D-type Flip-Flop
T-type Flip-Flop
J-K-type Flip-Flop
Transparent-D Latch
S-R Latch
6
6
10
4
2
With
With
With
With
With
Adders
8-bit
45
Full carry-Iookahead (four levels of logic)
Barrel Shifters
8-bit
72
2 levels of logic
April 1989
asynchronous S-R
asynchronous S-R
asynchronous S-R
asynchronous S-R
asynchronous S-R
Figure 2-2. An Internal NAND
Logic Equivalent
614
Signefics
PLHS501
Application Notes
Vol. 2
Programmable Logic Devices
FLIP-FLOP BASICS
Most designers view flip-flops as black
boxes with data inputs and outputs as well
as additional control inputs. Some flipflops are designed as primitive transistor
structures, but in the past, gate array designers used their elementary building
block, the NAND gate, to make flip-flops.
Because the PLHS501 is also largely
structured from NANOs, we can draw
upon years of well known NAND-based
flip-flop designs to readily implement flipflops within the PLHS501.
Figures 3-1,3-2,3-3 and 3-4 give single
sheet summaries of several flip-flop configurations. It should be noted that the
transparent latch is recommended for
data capturing, but not for state machines
due to potential glitching. The edge triggered O-type is a convenient building
block. Although external gates are saved
with the J-·K structure, it is at the expense
of additional NANOs within the J-K flipflop itself.
Notation
The delay of a NAND gate is most often
designated as tpLH or tpHL, indicating that
the gate output makes a High-to-Low
(tpHLl or Low-to-High (tpLH) transition. For
the flip-flops' transition, the High-to-Low
10 is DO and the Low-to-High 10 is 01.
This also holds true for structures fully
contained within the foldback core, because input and output time delays will
differ and change the performance. Knowing the basic concepts, the designer can
expand these structures to include I/O
pins and generate flip-flops wrapped
around the part - but, he must derate his
parameters accordingly to reflect the
slower paths.
Because it will be lengthy to explain all of
the flip-flop configurations given, we will
show only one in some detail. The interested reader can verify the rest by manual
analysis or by digital simulation. The Table
3-1 gives the typical and worst case values for an internal foldback NAND gate.
The single O-Iatch with enable ActiveHIGH can be described in terms of the
propagation delay formula given in Figure
3-1. For instance, the first propagation is
for 0 to a, where the a output transitions
from High-to-Low (i.e., tpoo). To do this,
assumeO is high so the/O term is Low. To
switch the state, /0 must be flipped first.
Hence, the logic variable enters G2, then
passes through G7, G4 and finally G3.
This presents four transitions, two from
Low-to-High (G2 and G4 outputs) and
two from High-to-Low (Gl and G3 outputs). Hence, the formula reflects
2(dl &dO} which, using Table 3-1, gives
2(8+6.5}=29ns.
This is the worst case value, using typicals
will give a value of 2(5.5+6.5}=24ns.
Switching in the other direction is a little
different. Assuming tPD , goes from 0=0 to
Table 3-1. Internal Fold Back NAND Gate
D
INPUT
OUTPUT
LIMITS
PARAMETER
SYMBOL
tpHL
tpLH
April 1989
TO
(OUTPUT)
FROM
(INPUT)
ANY
Min
Max
5.5
6.5
6.5
8.0
615
UNIT
ns
0=1, the /0 signal must be initially 1.
Hence, G3 is armed for immediate transition. Hence, the time delay is simply traversing G2 and G3. One of them will go
High-to-Low (G2) and the other Low-toHigh (G3). The formula reflects the sum of
the two transitions: tPD' =dl+dO. Fromthe
table, this is 14.5ns (worst case) or 12ns
(typical). The rest of the formula must be
similarly analyzed, but the method is
straightforward.
Flip-Flop Merging
Figure 3-5(A} shows the positive edge
triggered 0 flip-flop structure. By putting
a two-level AN~/OR structure in front of
the data input, the 0 flip-flop can be
steered from state to state.
Figure 3-5(B} shows such an input structure realized from a two-level NAND gate
section.
Figure 3-5(C} shows this "AND-OR"
structure rolled inside of the flip-flop. The
gating was merged with the flip-flop inwards to make a faster, composite function. Whereas this may appear as a trick
to the uninitiated, this degree of flexibility
allowed gate array designers to merge a
multitude of logic into a fixed foundation.
For highest efficiency, similar thinking allows the designer to break up decoders
and multiplexers into their building blocks
and generate only the pieces needed.
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
Propagation Delay Formulas:
Logic Symbol
~:
:t
t
QI!
2(D)j
3
FROM
TO
D
a
D
0
E
a
E
0
FORMULAS
tpoo - dl+dO x 2
tpDt '" dl+dO
-ETOOtpDO
".~
G1
3(0)
G4
4(0)
Function (Truth) Table
E
0
{)
0
:i-
1
0
0
1
1
1
1
0
X
0
n-1
0
n 1
0
0
~
0
DATA ENABLED
rE:01
~
o=uI
and "0"; the "0" output follows the data as
long as E is High. One setup time before the
High-to-law transition of E. 0 is stored in
the latch; the latched outputs remain stable
as long as E is Low.
On-I" state before High-·to-LO'N transition
01 E.
7.
X = don't care.
Figure 3-1. Single D-Latch (Enable Active-HIGH)
April 1989
a
E
0
D (SETUP TIME)
D (HOLD TIME)
E-C};
0
616
a
a-
E
ENABLE PULSE WIDTH
~
0
NOTE:
1. Spi~s can occur on U during the propagation de~y of E to a.
NOTES:
5. When input Enable (E) is High, data enters
the latch at "0" and appears at outputs "a"
6.
D
0
0
G3
E-
DATA LATCHED
D
tpDl~
Timing Waveforms:
1 (E)
aa
ENABLE PULSE
OPERATING MODE
D
0
HDLD TIME
NAND Gate Diagram
a
E
This part is functionally simlar to the 7475.
SETUP TIME
TO
D
tp01 '" 2xdl + dO
tPDO - dl + 2XdQ
NOTE:
4(0)
tpllO~
FROM
E
tpDI '" dl+dO
.. dl + 2XdO
_0
1 (E)
PARAMETER
tpDO '" dl + 2XdO
tpDl '" dl+dO
tpoo .. d1 + 2XdO
(0)
Propagation Delays:
rE=OI
DELAYinne
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
,Propagation Delays·I
Propagation Delay Formulas:
Loaic Symbol
~-.
FROM
TO
C
0
tPDO~
IpO "" 2xd 1+dO
QR
2(D) = + D
3 (C)
t
L._C_P
__
_
0...J
tpoo
a
C
6(0)
NOTE,
This part is functionally similar to the 74LS74.
= 2xd1+2xdO
IPOl ~ 2xd1+dO
t PD1
tpoo" 2 (d1+dO)
5(0)
o (SETUP TIME)
- ISL2 dO
o (HOLD TIME)
.. ISL 1 dl+dO
CLOCK PULSE WIDTH
.. 2xdO+d1
NAND Gate Diagram
I
i
FROM TO
DELAY in ns
PARAMETER
FORMULAS
f
C
0
C
a
C
0
C
a
o (SETUP TIME)
o (HOLD TIME)
ns MIN
ENABLE PULSE WIDTH
ns MIN
ns MIN
Timing Waveforms:
CL
CLOCK
WIDTH
SETUP HOLD
5(0)
D
2 (D) _ _ _rc;;")'~-l--=!
6(0)
O-----+-......J
u-----+---,
CTOO
1 (C) _ _ _-j
NOTE:
1. Spikes can occur on
a during the propagation delay 01 C to a.
Function (Truth) Table
c
0
°n+1
'On +1
~
0
0
1
~
1
1
0
NOTES,
L Data is transferred to the outputs on the
negative--going edge of the cock.
2. Q n + 1 '" state after High-la-Low transition
afC.
Figure 3-2. D Flip-Flop (Negative Edge-Triggered)
April 1989
617
I
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
Propagation Delay Formulas'
Logie Symbol
FROM
~'"
FORMULAS
tpOt .. 2d1+dO
Q
C
tpoo =
2(dl+dO)
tPOt
2dl+dO
=
Propagation Delays:
PARAMETER
tPD1
f
tPDO~
ep
R
6(0)
TO
C
C
R
Q
0
Q
tpOD - dl+dO
D (SETUP TIME)
ns Min
R
0
'pDI' dl
D (HOLD TIME)
ns Min
MINIMUM
CLOCK WIDTH
ns
MINIMUM
RWIDTH
ns
• dO
D (HOLD TIME)
'" dl + dO
NOTE:
CL WIDTH (HIGH)
",d1+2dO
This part is functionally simitar to the 74LS74.
RESET WIDTH (LOW)
R->Q
DELAY in ns
0
0
0
0
0
C
C
D (SETUP TIME)
0
FROM
R
'pDI .2(dl+dO)
2 ( 0 ) H O 5(0)
l(e)
TO
C
R
NAND Gate Diagram
4(R) _ _
;:=====+====::::;~
5(0)
2(0) _ _ _- ' " - ,
6(0)
1:>--<--1---1
1(C)
Function (Truth) Table
C
\..
\..
\..
\..
,.
TIming Waveforms:
0
On+1
°n+1
0
0
I
,
,
0
0
0
,
,
,
0
Cl
o
0-+-.,
RTOO
NOTES:
Data Is transf8(red to the outputs on the
negativ9--9oing edge of the clock; reset
~R"
R
2.
(Active-LOW) Is asynchronous and
independent 01
On+l '" state after High-to-LC1vV transition
3.
otC.
X _ don't care.
0-----+-......
0-----+---., CTOO
Figure 3-3. D Flip-Flop with Reset
April 1989
618
RTOO
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
Propagation Delay Formulas:
$
Logic Symbol
a
TO
FORMULAS
C
Q,a
tpOD .. 3dO+2d 1
S
a
a
tpOl .. 3(dl+dO)
CP
K ROO
R
.ua (a)
S
tpOt .. dl
a
R
J
0
tPoo~
tpOD" dl+dO
7(0)
a
S
S
a
Q
R
Q
C
f
S
R
a
J-K SETUP TIME
0
J-K HQLO TIME
2 Min
J-K HQlD TIME
• dO
--_._-
S.R (MIN)
.. dl + dO
MINIMUM
16
Function (Truth) Table
C
2 {J)-----I
6 (0]
1 (eL)
7 (0]
3 (K)-----l
U
U
Timing Waveforms:
J
K
S
R
On+l
On+l
0
0
1
1
Qn
On
1
0
1
1
1
0
0
1
1
1
0
1
1
1
1
1
Q
a
C
J
K
S
R
Q
°
X
X
X
1
0
0
1
X
X
X
0
1
1
0
U
U
5(R)-----========i=======================1-----~
NOTES:
1. Master/slave data is pulse-triggered and
enters the J-K flip-flop when the clock (C)
S
goes Low; tile entered data is transferred
to the outputs on the positive going edge
of "eN. Set (S) and Reset (Al inputs are
R-+------,
asynchronous, independent signals and,
when either is Active-lOW, the J-K and C
J-K
inputs are overridden.
2.
-+--1
0 -_ _ _
0-----+.....,
nil
20
PULSE WIDTH
MINIMUM PULSE
WIDTH S&R (lQW)
= (dl+dO)
UtLAY In
a
Q&a
Q
0
.(S)----~=======+=======================i----,
3.
a
0-+----,
Figure 3-4, J-K Flip-Flop with Set and Reset
April 1989
Q&a
J-K SETUP TIME
NAND Gate Diagram
c
10
C
tpOD .. 2(d 1+dO)
PULSE WIDTH C (MIN)
NOTE:
This part is functionally similar to the 74LS109.
FROM
R
tPD1
IfC·l
5
CP
K
R
I
PARAMETER
tPOt '" dl
ItC .. O
QB
2
1
3
5
Propagation Delays:
FROM
619
Qn+ 1 .. next state of Q.
X", don't care.
I
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
p--.---L":>
RESET" C>--H~-""?~--
A
B
C
D
Figure 3-S(A). Positive Edge Triggered
D-Fllp-Flop with Reset and Set
SETH
Figure 3-6(8). As in (A), with Input AND-OR Function
L::---.---:-----,
Q
CLOCK,--~ II l i T
RESET"
L::-tt1H--;?--=-,
Figure 3-6(C). As Above, with Integral AND-OR Input Function
Figure 3-6. Flip-Flop Merging
April 1989
620
Q
Signetics
PLHS501
Application Notes
Vol. 2
Programmable Logic Devices
VME Bus EXAMPLES
Omnlbyte VSBC20 Mailbox
Interrupt Structure
One of the more popular uses for the
PLHS501 is interfacing with 32-bit microprocessors. This section illustrates some
of the ways the part has been used with
the popular VME Bus. The Omnibyte
Corporation manufactures many VME
Bus products (as well as others) and was
kind enough to release a portion of their
VSBC20 board design as an example of
using the PLHS501 in a very flexible, user
configurable interrupt generation device.
The VSBC20 employs two PLHS501
parts, as shown in Figure 4-1. One device
is used largely as an address decoder, the
other, which is the object of this Section, is
the configurable interrupt generator. The
target microprocessor here is a 25MHz
68020 and the application is interrupt generation. The explanation is in the words of
Glenn Case, the designer:
"Following the design philosophy of giving
the user as much flexibility as possible, the
local interrupt structure of the VSBC20 is
implemented in a PLD. It is impossible to
"optimize" the assignment of the local
interrupts to the interrupt levels olthe processor since they are application specific.
One system may want the Serial I/O and
Parallel I/O to have higher levels than the
Omnimodule Interrupts while yet another,
using a SCSI Omnimodule, may want it to
have higher level interrupts. Arbitrarily
assigning and hard wiring these levels
would unnecessarily constrain the use of
the VSBC20 for any given application. By
using the Signetics PLHS501, the entire
logic to implement the interrupt structure
fits into one PLD. Furthermore, the
AMAZE software to program the part is
available free from Signetics. The
PLHS501 can be reprogrammed until the
unused feedback gates are all used. So,
the user can get the software free and
change the interrupt levels a couple of
times before having to replace the
PLHS501 with a new part. This appendix
describes how the PLHS501 is used and
how to change the interrupt levels.
There are a total of 17 possible interrupt
sources to the processor on the VSBC20.
There are up to seven possible VMEbus
interrupts, nine possible local interrupts,
and a Front Panel Non-Maskable
interrupt. The local interrupts include:
ACFAIL*, SYSFAIL*, parity error, mailbox
interrupt, two Omnimodule interrupts, 24
bit timer interrupt, Parallel I/O, and Serial
ACFAIL*,
I/O interrupts. Although
SYSFAIL* and mailbox interrupts are
generated by VMEbus, they are referred
to as local interrupts because they are acknowledged locally. That is, no VMEbus
lACK cycle takes place. The local
interrupts are latched during an lACK
cycle to '1reeze"the state of the interrupts.
This allows the correct acknowledgement
of the interrupts. The ACFAIL*, SYSFAIL*
and Front Panel Non-Maskable Interrupt
are assigned to Level 7. The Front Panel
NMI has the highest priority followed by
ACFAIL *, parity error, and SYSFAIL *. The
front Panel interrupt is acknowledged by
an autovectorwhile the other three generate a vector that is encoded as described
in the Error Interrupt Vector CSR. The
local interrupts for the mailbox interrupt,
Omnimodule Interrupt 0, Omnimodule
Interrupt I, 24 bit timer interrupt, Parallel
I/O Interrupt, and Serial I/O Interrupt have
been assigned by the usertothe level best
suited for the user's application. The mailbox interrupt uses the auto vector while
the others provide interrupt acknowledge
vectors. However, these may also be
changed to generate autovectors. For example, if a unique Omnimodule is designed by the user and there is not enough
room to provide an interrupt vector on the
module, the PLD can be changed to issue
an autovector instead of generating an
lACK cycle to the Omnimodule. ~ is also
possible to have two interrupts share the
same level, although this seems unnecessary, since there are enough available
interrupt levels.
The following examples illustrate how
easy it is to change the local interrupt
levels:
EXAMPLE 1:
Put the Pl0 interrupt in level 4 and the Omnimodule 0 interring on level 2.
LIRQ4 ~ /LIRQPIO;
LIRQ2 ~ /LIRQOOM;
IACKOOM ~ /1/LIRQOM*/A3*A2*/Al*//IACK*/BAS);
IACKPIIO ~ /1/LIRQPIO*A3*/A2*/Al*/IACK*/BAS);
1->
1->
<-I
<-I
change these
equations to
EXAMPLE 2:
Make both the Omnimodule Interrupt Autovectored instead of bus-vectored. (LITROOOM uses level 4 and LlROIOM uses level 5.)
AUTOVECTOR
+
+
+
+
IACKIOM
IACKOOM
April 1989
~
~
/(0);
/(0);
[/FPNMIRQ*A3*A2*Al*/IACK*/BAS*RESET]
[/LIRQMBOX*A2*A2*/Al*/IACK*/BAS*RESET]
[/LIRQOOM*A3*/A2*/Al*/IACK*/BAS*RESET]
[/LIRQIOM*A3*/A2*Al*/IACK*/BAS*RESET]
[autovector*
/BAS*RESET];
<-<--
change
equation
621
<-- ADD
<-- ADD
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
A'
A10
An
A12
A13
A1.
A15
A16
A17
A18
.,
10
OIl
37
AS
•2
11
lIT
38
A•
43
44
.5
47
48
12
B2
II!f
3.
40
A7
15
,.
ROMSZO
17
18
EAG'
PlHS501
13
14
17
B4
B5
B6
B7
50
18
00
••
15
16
AS
ROMSZ1
CPUSPACE'
~S68XXX
51
I.
01
52
1
110
02
A20
In
03
22
23
lACK
IOSPACE
A21
2
112
~
24
CSFPC'
A22
3
113
25
CSCSW
2•
CS68230*
5
11'
115
m;
00
m
27
CS6888,·
CSROM'
M.
•
A23
A24
A25
6
116
XO
28
A26
7
117
X1
29
CSIOMODULE'
118
X2
lOS PACE'
•
A27
A28
10
X3
A2.
n
11'
120
30
31
X.
32
CSMBX'
A30
12
121
X5
33
CSBBITTO
A31
13
122
X6
35
CSCSROAMBX'
123
X7
I
Un
OFFBRD'
~
STROBE'
ADDRESS DECODER
25MHzCLOCK
I
ADDRESS
A3l-AD
PLHS501
lACK
41
10
OIl
37
BAS'
.2
11
lIT
38 N/e
A3
43
12
B2
A2
44
45
13
m
14
15
A1
MASK BITS {
'~~l
LATe HED INTERRUPTS
-"'-""'j
INTERRUPTS
~
40
IACKP
,.
15
BRDFAIL'
17
18
FPNMIIN'
PERRM
47
SYSFW
48
I.
ACFM
4.
17
B4
B5
B6
B7
LSYSF~
18
{)()
I.
01
LACFAIL'
52
110
lIROPE'
1
In
02
03
23
IACKMBX'
lIROMBX'
2
112
~
2.
IACKoOM'
3
113
05
Oil
25
IACK10M*
114
2.
IACKTMA'
115
m
27
IACKPIO'
116
XO
28
02.
117
X1
2.
025
118
IACKSIO'
10
11.
X2
X3
30
VIR02'
•
•
•
31
OFFBROIACK'
VIR03'
11
12
13
120
X,
32
AUTOVEC'
VIR04'
VIRQ5*
121
XS
33
IPLO'
122
X.
35
IPL,·
VIRQ6'
14
123
X7
3.
IPL2'
lIR01OM'
lIROOOM'*
lIROTMW
lIROPlO"
lIROSIO'
VIRa1·
MA
FPNMIRO'
5
7
RESET"
68020
RESET
V1ROr
~
~DSACKO*
=
02.
025
AVEC
fPl]J
II'[f
JP[2
U8
VIR07'
INTERRUPT CONTROlLER
Figure 4-1. Portion of Omnibyte VSBC20 Highlighting PLHS501 Usage
April 1989
622
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
File Name : vsbc20is
Date
9/13/1988
Time :
9: 4: 2
LIS T #####################
##################### PIN
Right
LABEL
Left
LABEL
FNC **PIN
+5V
8-1
I
9-1
10-1
VCC
VIRQ1
VIRQ2
VIRQ3
VTRQ4
VIRQ5
VIRQ6
BRDFAIL
RESET
FPNMIIN
VIRQ7
N/C
GND
ll-I
**
**
I
I
o
ov
12-1
13-1
14-1
15-1
16-1
17- I
18- I
19-1
20-1
PIN** FNC
P
L
H
1-46
1-45
1-44
1-43
1-42
1-4l
1-40
1-39
1-38
1-37
1-36
1-35
1-34
+SV
**vee
I
**Al
**A2
**A3
**BAS
**
I
**lACK
/0
/0
/0
/0
**IACKF
**N/C
**N/C
**N/C
**IPL2
0
0
/0
**IPLl
**GND
Bottom
LABEL
N/C
DSACKO
N/C
IACKOOM
IACK10M
IACKTMR
IACKPIO
024
025
IACKSIO
OFFBRDIACK
AUT aVEC
IPLO
Top
FNC **PIN
a
21-1
a
22-1
a
23-1
/0
24-1
/0
25-1
/0
26- I
/0
27-1
28-1
a
a
29- I
o
30-1
a
31-1
a
32-1
a
33-1
P
L
H
S
5
PIN** FNC
1I
IIIIII- 1
I-52
I-51
I-50
1-49
1-48
1-47
LABEL
**LIRQSIO
**LIRQPIO
**LIRQTMR
**LIRQOOM
**LIRQ10M
**LIRQMBX
**LIRQPE
**LACFAIL
**LSYSFAIL
**N/C
**ACFM
**SYSFM
**PRRM
Figure 4-2. PLHS501 Pinlist for VSBC20 Interrupt Structure
@DEVICE TYPE
PLHS501
@DRAWING
1155
@REVISION A
@DATE
9-9-88
@SYMBOL
@COMPANY
OMNIBYTE CORP.
@NAME
GLENN CASE
@DESCRIPTION
VSBC20 INTERRUPT STRUCTURE PLD
@INTERNAL NODE
LIRQ7 ALLIRQ7 AHIACKF AHFPNMIRQ AUTO VECTOR FPNMIRQ
@COMMON
LIRQ6
LIRQ5
LIRQ4
LIRQ3
LIRQ2
LIRQ1
PRODUCT TERM
/LIRQMBX;
/LIRQ10M;
/LIRQOOM;
/LIRQTMR;
/LIRQPIO;
/LIRQSIO;
"LIRQ6 goes high when LIRQMBX goes low"
Figure 4-3. VSCB201S .BEE File (begins)
April 1989
623
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
@I/O DIRECTION
DB4
0;
DB5
O·
DB6
o·
DB7
O·
XED
/lACKF;
1;
XEl
XE2
1;
XE3
1;
OEI
IIACKF;
OE2
1;
OE3
1·
@I/O STEERING
@LOGIC EQUATION
LIRQ7
[/LACFAIL * ACFM]
" [/LYSFAIL * SYSFM
+ [/LIRQPE * PERRM];
ALLIRQ7
I[/[/LACFAIL * ACFM]
+ I[/LSYSFAIL * SYSFM * BRDFAIL]
+ I[/LIRQPE * PERRM]];
AHFPNMIRQ
+
+
+
+
+
+
FPNMIRQ
IPLO:
"LIRQ7 goes high when"
* BROFAIL)
[ IFPNMIIN
[AHFPNMIRQ
[AHFPNMIRQ
[AHFPNMTRQ
[AHFPNMIRQ
[AHFPNMIRQ
[AHFPNMIRQ
*/lACK
* RESET]
*/IACK * RESET]
*IACK * BAS * RESET]
*IACK * IBAS * IAI * RESET]
*IACK * IBAS
*IACK * /BAS
*IACK * IBAS
* IA2 * RESET]
* IA3 * RESET]
* A3 * A2 * Al * IAUTOVECTOR * RESET];
I (AHFPNMIRQ) ;
~
IVIRQ7
+ LIRQ7
+ IFPNMIRQ
+ ILIRQ7 * ILIRQ6
+ ILIRQ7 * ILIRQ6
+ ILIRQ7 * ILIRQ6
+ ILIRQ7 * ILIRQ6
+ ILIRQ7 * ILIRQ6
XRl~
* VIRQ7 * VIRQ6 *
* VIRQ7 * VIRQ6 *
* ILIRQ5 * ILIRQ4
* ILIRQ5 * ILIRQ4
* ILIRQ5 * ILIRQ4
LIRQ5
IVIRQ5
* VIRQ7 * VIRQ6
* VIRQ7 * VIRQ6
* VIRQ5 * VIRQ4 * LIRQ3
* VIRQ5 * VIRQ4 * IVIRQ3
* ILIRQ3 * ILIRQ2 * VIRQ7 * VIRQ6 * VIRQ5 * VIRQ4 *
VIRQ3
* VIRQ2 * LIRQl
+ ILIRQ7 * ILIRQ6 * ILIRQ5 * ILIRQ4 * ILIRQ3 * ILIRQ2 * VIRQ7 * VIRQ6 * VIRQ5 * VIRQ4 *
VIRQ3
* VIRQ2
XR2
~
*
IIRQl;
1;
IPLl: XRl
+
IVIRQ7
LIRQ7
+ IFPNMIRQ
+ ILIRQ7 * VIRQ7 * LIRQ6
+ ILIRQ7 * VIRQ7 * IVIRQ6
+ ILIRQ7 * ILIRQ6 * ILIRQ5 * ILIRQ4 * VIRQ7 * VIRQ6 * VIRQ5 * VIRQ4 * LIRQ3
+ ILIRQ7 * ILIRQ6 * ILTRQ5 * ILIRQ4 * VIRQ7 * VIRQ6 * VIRQ5 * VIRQ4 * IVIRQ3
+ ILIRQ7 * ILIRQ6 * ILIRQ5 * ILIRQ4 * ILIRQ3 * VIRQ7 * VIRQ6 * VIRQ5 * VIRQ4 * IVIRQ3
* LIRQ2
+ ILIRQ7 * ILIRQ6 * ILIRQ5 * ILIRQ4 * ILIRQ3 * VIRQ7 * VIRQ6 * VIRQ5 * VIRQ4 * IVIRQ3
* IVIRQ2;
XR2
1;
Figure 4-3. VSCB20lS .BEE File (continued)
April 1989
624
Signetics Programmable Logic Devices
PlHS501
Application Notes Vol. 2
TLP2: XRl
+
+
+
+
+
+
+
XR2
~
IVIRQ7
LIRQ7
IFPNMIRQ
ILIRQ7 *
ILIRQ7 *
ILIRQ7 *
ILIRQ7 *
ILIRQ7 *
ILIRQ7 *
* lACK * IBAS]
[A3 * A2 * Al * FPNMIRQ * ILSYSFAIL * lACK * IBAS]
[A3 * A2 * Al * FPNMIRQ * ILIRQPE
* lACK * IBAS]);
1([A3 * A2 * Al * FPNMIRQ * ILACFAIL
OFFBROIACK: XRl
+
+
+
+
+
+
~
ILIRQ7 * A3 * A2 * Al *
ILIRQ6 * A3 * A2 * IAI *
ILIRQ5 * A3 * IA2 * Al *
ILIRQ4 * A3 * IA2 * IAI *
ILIRQ3 * IA3 * A2 * Al *
ILIRQ2 * IA3 * A2 * IAI *
ILIRQI * IA3 * IA2 * Al *
024: XRl
ILACFAIL
IBAS
IBAS
IBAS
IBAS
IBAS
IBAS;
*
ACFM
* PERRM;
1;
D25 : XRl
+
+
~
*
lACK *
lACK *
rACK *
lACK *
IACK
AUTOVECTOR;
+ ILIRQPE
XR2
* IBAS * FPNMIRQ * IAUTOVECTOR
*
[/FPNMIRQ * A3 * A2 * Al * lACK * IBAS * RESET]
+ [/LIRQMBX * A3 * A2 * IAI * lACK * IBAS * RESET]
+ [ AUTOVECTOR
* IBAS * RESET];
AUTOVEC; XRl
XR2 ~ 1;
~
lACK
lACK
1;
AUTOVECTOR
XR2
VIRQ6 * LIRQ5
VIRQ6 * IVIRQ5
VIRQ7 * VIRQ6 * VIRQ5 * LIRQ4
VIRQ7 * VIRQ6 * VIRQ5 * IVIRQ4;
1;
IACKF
XR2
VIRQ7 * LIRQ6
VIRQ7 * IVIRQ6
ILIRQ6 * VIRQ7 *
ILIRQ6 * VIRQ7 *
ILIRQ6 * ILIRQ5 *
ILIRQ6 * ILIRQ5 *
ILACFAIL
LIRQPE
*
ACFM
PERRM
IPERRM
* ILSYSFAIL * SYSFM
* ILSYSFAIL * SYSFM;
1;
lACK 10M
I (/LIRQI0M *
A3
* IA2 *
IACKOOM
/(/LIRQOOM
*
A3
* /A2 * IAI * lACK * IBAS) ;
IACKTMR
I (/LIRQTMR * IA3 *
A2
*
IACKPIO
I (/LIRQPIO * IA3 *
A2
* /Al * lACK * IBAS);
IACKSIO
I (/LIRQSIO * IA3 * IA2 *
DSACKO
~
Al * lACK
Al
* IBAS) ;
* IACK * IBAS) ;
Al * lACK * IBAS);
BAS;
Figure 4-3. VSCB20lS .BEE File (end)
April 1989
625
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
The idea for this VMEbus EPROM board came
from WIRELESS WORLD CIRCUIT IDEAS,
January, 1988. The implementation was done
by a Philips' FAE, John McNally.
The circuit· drawing was entered onto a PC
using FutureNet DASH, a schematic capture
package (Figures 4-4, 4-5, and ~). It was
then converted to logic equations using
AMAZE (Figure 4..g) and then assembled into
a PLHS501.
The board contains two banks of EPROMs.
Each bank consists of either two 27128s or two
27256s; each of which can be enabled by comparing the address location fa the board.
Decoding three other address bits selects
which of the banks is accessed. A 4-bit shift
register combined with four jumpers provide
wail states.
This application, which needs eight ICs, used
forty-four of the available seventy-two NA ND
Foldback Terms and forth of the available fiftytwo pins. As the PLHS501 contains no registers, an edge-triggered D-type flip-flop was
designed using NAND gates and this is used as
a soft macro in order to implement the shift
register function (Figure ~).
VME Bus EPROM Interface
As suggested in the original article, the circuit
could be expanded to access up to eight ROM
banks (Figure 4--8). This was achieved by editing the logic equation file and adding extra
equations (Figure 4..g). Modifying the drawing,
although fairly easy to do, was not considered
necessary as the object was to design with
PML and not TIL. The expanded circuit would
require another three TIL IC packages, brining
the total to eleven. The number of foldback
terms increased to fifty-five, with the number of
pins rising to fifty. Figure 4-1 0 shows the pinout
of both versions.
740
ENADO
1 """,2
~~
lAS
Gl
A19
A16
1
~
o-!--
",3
ENOATLO
G2
A22
521
A21
1 7432
7404
~2
2
I
1 7432
3
3
2J
Gs
G4
G3
ENDATHI
/
IR-W
~MO
.Ii
~
C t+<
~
6
~
2J
523
A23
522
16
15
14
13
12
11
---...-
1 7432
GND
GND
17
_2.....
~p--
IMASEL
19
~
~
~
vcc
,.
1
~
~~
~
~
f-2-<
1 Jj!,2
ROMI
~
~
~
10
NC
~3
~
1 7432
IROM1LO
1~
2
V
Ii2
I
3
IROM1LO
3
IROM1H1
G7
G6
IROM1H1
3
1 7432
>J
G9
G6
IDSO
10S1
IDTACK
R-WN
~~
~
~
..--L
rTa---oo
12
11
10
~
~
6
7
CKBMZ
2
~
01
02
03
WAlT
7402
1
3
Gl0
1 7400
",,-3
2
'G;;"
Gl0
(SOURCE: WIRELESS WORLD, JAN. 1988, CIRCUIT IDEAS)
•
Figure 4-4. VME - EPROM Interface
April 1989
626
1
1
~2
G12
DTAK
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
o
PN
ON
CK
o
Figure 4-5. Edge-Triggered 0 Flip-Flop (DFFS)
7404
EL 1
SET
G1
OFFS
GNO
PN
0
CLBMZ
CK
FF'
OFFS
a
ao
ON
RN
ONO
ROO
SN
SOO
ON
000
OFFS
a
PN
0
ON
RN
SN
CK
ON
01
~,
RO,
SO,
DO'
FF2
PN
0
CK
FF3
Figure 4-6. 4-8il Shifter (7495)
April 19S9
627
OFFS
a
02
ON
RN
SH
ON
ON2
PH
R02
So.
002
a
CK
ON
RN
SN
ON
FF4
03
0N3
R03
SOl
003
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
2 ROM BANKs AS ORIGINAL CIRCUIT.
REPLACES 8 PACKAGEs - UsES 46 FOLDBACK TERMS
517
lAS
518
511
520
521
522
523
A16
A17
A18
A19
A20
5
1 7 16
4
3
2
1 52 51 50
491 48 147
VCC
A21
A22
A23
8
9
10
11
IDSO
12
1051
13
R-WN
14
15
Ql
16
Q2
17
Q3
18
IROMOLO 19
GND
20
46
45
44
PLHS501
43
42
41
40
ao
39
38
37
36
35
34
VMEEXP
121 122 23 24 25 26 27 28 29 30 31132133
IROMOHI
IROM1LO
IROM1HI
NIC
NIC
NlC
VCC
WAIT
NlC
CKBMZ
NlC
NlC
IR-W
DTAK
IDTACK
IMASEL
NlC
NlC
GND
NlC
NIC
NlC
ENDATH
ENDATLO
ENADD
NlC
EXPANDED TO 8 ROM BANKS
REPLACES 11 PACKAGES - USEs 55 FOLDBACK TERMS
517
lAS
A16
A17
A18
A19
A20
vee
A21
A22
A23
IDSO
1051
R-WN
REG
ENADD
ENOATLO
ENDATHI
!ROMOLO
GND
IROMOHI
IROM1LO
IROM1H1
IROM2LO
!ROM2H
IROM3LO
518
519
520
521
522
523
1 7 16
5
8
9
10
11
12
13
14
15
16
17
18
19
20
4
3
2
1 52 51 50 49148147
46
45
PLHS501
FULLEXP
121 122
23 24 25 26 27 28 29 30 31132133
Figure 4-7. VMEEXP and FULLEXP
April 1989
VCC
W2
Wl
43
CKBMZ
42
NlC
NlC
41
IR-W
40
DTAK
39
IDTACK
38
37
IMAsEL
36 fROM7H1
35 IROM7LO
GND
34
44
628
!ROM6H
IROM6LO
IROM5H1
IROM5LO
IROM4H
IROM4LO
IROM3Hi
Signe!ics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
File Name : VMEEXP
Date
2/13/1988
Time: 10:23:5
##################### PIN
LIS T #####################
Right
Left
LABEL
FNC **PIN
+5V
8-1
vee
A21
A22
A23
/DSO
/DS1
R-WN
** 0
QO
Q1
Q2
Q3
o
/ROMOLO
GND
OV
9-1
10-1
11-1
12-1
13-1
14-1
15-1
l6-1
17-1
18-1
19-1
20-1
P
L
H
S
5
PIN**
1-46
1-45 **
1-44 **
1-43
1-42
1-41
1-40
1-39
1-38
1-37
1-36
1-35
1-34
FNC
I
I
I
/0
/0
/0
/0
**N/C
OV
**GND
Top
FNC **PIN
o
21-1
o
22-1
o
23-1
/0
24-1
/0
25- I
/0
26-1
/0
27-1
o
28- I
o
29-1
o
30-1
** 0
31-1
o
32-1
o
P
L
H
S
5
33-1
PIN** FNC
1I
IIIIIII-52
I-51
I-50
1-49
1-48
1-47
Figure 4--3. VMEEXP PLHSS01 Pinlis!
April 1989
**WAIT
**N/C
**CKBMZ
**N/C
**N/C
**/R-W
**DTAK
**/DTACK
** /MASEL
**N/C
o
Bottom
LABEL
/ROMOHI
/ROM1LO
/ROM1HI
N/e
N/e
N/e
N/e
ENADD
ENDATLO
ENDATHI
N/e
N/e
N/e
LABEL
+SV **vcc
629
LABEL
**A20
**A19
**A18
**A17
**A16
**/AS
**517
**S18
**519
**520
**521
**522
**523
Signetics Programmable Logic Devices
PlHS501
Application Notes Vol. 2
File Name: VMEEXP
Date:
Time:
211311988
10:23:41
@DEVICE TYPE
PLHS501
@DRAWING
VMEEXP.DWG
@REVISION
@DATE
2112/1988
@SYMBOL
@COMPANY
@NAME
VMEEXP
@DESCRIPTION
@INTERNAL NODE
R03 S03 D03 R02 S02
D02 QO ROI SOl DOl
ROO SOO DOO
@I/O DIRECTION
DB5
1
DB6
DB7
OEO
DEI
@I/O STEERING
@LOGIC EQUATION
(/((//MASEL)*S03*CK8MZ*D03))
R03
S03
(/(CKBMZ*(/(S03*D03*(//MASEL)))))
D03
(/ (Q2*R03)) ;
R02
(/ ((/ /MASEL) *S02*CKBMZ*D02)) ;
S02
(/(CKBMZ*(/(S02*D02(//MASEL)))))
D02
(/ (Q1 *R02)) ;
R01
(/ ( (/ /MASEL) *SOI *CKBMZ *DOl)) ;
SOl
(/(CKBMZ*(/(SOl*D01(//MASEL)))))
DOl
(/(QO*R01));
ROO
(/ ((/ /MASEL) *SOO*CKBMZ*DOO)) ;
SOO
(/(CKBMZ*(/(SOO*DOO*(//MASEL)))))
DOO
(/(Q*ROO));
/ROMOLO
(/DSO+(/(/A16*/0*1*//MASEL)))
/ROMOHI
(/DSl+(/(/A16*/0*1*//MASEL)))
/ROM1LO
(/DSO+(/(A16*/0*1*//MASEL)))
/ROM1HI
(/DS1+(/(A16*/0*1*//MASEL)))
QO
(/ ((/ (ROO*QO)) *SOO* (/ /MASEL)))
Ql
(/ ((/ (R01 *Ql)) *SOI * (/ /MASEL)))
Q2
(/ ((/ (R02*Q2)) *S02* (/ /MASEL)))
Q3
(/ ((/ (R03*Q3)) *S03* (/ /MASEL)))
/MASEL ~ /(/(/[/((A17*S17+/A17*/S17)*(A18*S18+/A18*/S18)*(A19*S19+
/A19*/S19)* (A20*S20+/A20*/S20) *(A21*S2l+/S21*/S21) *
(A22*S22+/A22*/S22)*(A23*S23+/A23*/S23)*//A5)]))
/DTACK
/((/(/MASEL+WAIT))*R-WN)
DTACK
/(/DTACK)
/R-W ~ / (R-WN) ;
ENADD ~ (/ /A5) ;
ENDATLO
((/R-W+/MASEL)+/DSO)
ENDATHI
(/DS1+(/R-W+/MASEL))
Figure 4-9. VMEEXP PLHS501 .BEE File
April 1989
630
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
File
Name
Date
:
FULLEXP
2/1311988
Time : 10:11:28
##################### P I N
L I S T #####################
Left
LABEL
vee
A21
A22
A23
/OSO
/OSl
R-WN
REG
ENADO
ENDATLO
ENDATHI
/ROMDLO
GNO
FNe **PIN
+5V ** 8-1
I
9- I
10-1
11-1
12-1
** I
13-1
14-1
15-1
** 0
16-1
** 0
0
17- I
0
18-1
0
19-1
ov
20-1
PIN** FNC
p
L
H
1-46
1-45
1-44
1-43
1-42
1-41
1-40
1-39
1-38
1-37
1-36
1-35
1-34
+5V **VCC
**WO
I
**Wl
**CKBMZ
I
/0
/0
/0
/0
0
0
ov
FNC **PIN
0
21-1
0
22-1
0
23-1
/0
24-1
/0
25-1
/0
26- I
/0
27-1
0
28-1
0
29-1
0
30-1
0
31-1
0
32-1
0
33-1
**/MASEL
**ROM7HI
**ROM7LO
**GND
PIN** FNe
p
L
H
I111111i-52
I-51
I-50
1-49
1-48
1-47
I
Figure 4-10. FULLEXP Pin lis!
April 1989
**N/C
**N/C
**/R-W
**DTAK
**/DTACK
Top
Bottom
LABEL
/ROMOHI
/ROM1LO
/ROM1HI
/ROMlLO
/ROM1HI
/ROM3LO
/ROM3HI
/ROM4LO
/ROM4HI
/ROM5LO
/ROM5HI
/ROM6LO
/ROM6HI
Right
LABEL
631
LABEL
**A20
**A19
**A18
**A17
**A16
**/AS
**517
**518
**519
**520
**521
**522
**523
Signetics Programmable Logic Devices
PlHS501
Application Notes Vol. 2
File Name: FULLEXP
Date:
2/13/1988
Time:
10:11:30
@DEVICE TYPE
PLHS501
@DRAWING
VMEEXP.DWG
@REVISION
@DATE
2/12/19B8
@SYMBOL
@COMPANY
@NAME
VMEEXP
@DESCRIPTION
@INTERNAL NODE
R03 S03 003 R02 S02
D02 R01 SOl DOl ROO
SOO DOO
QO Q1 Q2 Q3
@I!O DIRECTION
DB4
1
DBS
1
DB6
DB7
OEO
OE1
OE2
OE3
XEO
XE1
XE2
XE3
@STEERING
SO
Q
Sl
Q
S2
Q
S3
Q
Figure 4-11. FULLEXP PLHS501
.BEEFile
April 1989
@LOGIC EQUATION
R03
(/ ((/ /MASEL) *S03*CKBMZ*D03))
S03
(/(CKBMZ*(/(S03*D03*(//MASEL)))))
D03
(/(Q2*R03));
(/
((/ /MASEL) *S02*CKBMZ*D02)) ;
R02
(/(CKBMX*(/S02*D02*(//MASEL)))))
S02
D02
(/(Ql*R02)) ;
(/ ((/ /MASEL) *SOI*CKBMZ*DOl)) ;
ROl
(/ (CKBMZ* (/ (SOI*D01* (/ /MASEL)))))
SOl
(/ (QO*ROI)) ;
001
(/ ((/ /MASEL) *SOO*CKBMZ*DOO)) ;
ROO
(/ (CKBMZ* (/SOO*DOO* (/ /MASELI))))
SOD
(/(Q*ROO)) ;
DOD
(/DSO+/(/A16*/A17*/A18*//MASEL))
/ROMOLO
(/DSl+/(/A16*/A17*/A18*//MASEL))
/ROMOHI
(/OSO+/ (A16+/A17*/A1B*/ /MASEL)) ;
/ROMILO
(/DS1+/(A16*/A17*/A18*//MASEL)) ;
/ROM1HI
/(/(/DSO+/(/A16*A17*/A18*//MASEL)))
/ROM2LO
/(/(/DSl+/(/A16*A17*/A18*//MASEL)))
/ROM2HI
/ROM3LO ~ /(/(/DSOt/(A16*A17*/AI8*//MASEL)))
/(/(/DSl*/(A16*A17*/A18*//MASEL)))
/ROM3HI
(/050+/ (A16*/A17*A18*/ /MASEL)) ;
/ROM4LO
(/DSl+/(A16*/A17*/A18*//MASEL)) ;
/ROM4HI
/ROMSLO
(/SAO+/ (A16*/A17 (A18*/ /MA5EL) I ;
(/051+/ (A16*/A17*A18*/ /MASEL)) ;
/ROMSHI
(/OSO+/(A16*A17*A18*//MASEL))
/ROM6LO
(/DS1+/(A16*AI7*A18*//MASEL))
/ROM6HI
/ROM7LO
(/DSO+/ (A16*A17*A18*/ /MASEL))
/ROM7HI
(/051+/ (A16*A17*AI8* / /MASEL))
ENADD
(//AS) ;
ENDATLO
((/R-W+/MASEL) +/050) ;
(/OS1+ (/R-W+/MASEL)) ;
ENDATHI
00
/((/(ROO*QO))*SOO*(//MASEL))
01
/ ((/ (R01 *oJ) ) *SOI * (/ /MASEL))
02
/ ((/ (R02*Q2)) *502* (/ /MASEL))
Q3
/((/(R03*Q3))*S03*(//MA5EL))
/MASEL ~ /(/([/((A17*S17+/A17*/A17*/S17*(A1B*S18+/A18*/S18)
*(A19*S19+/A19*/S19)*(A20*S20+/A20*/S20)*(A2l*S2l
+/A2l*/S21)*(A22*S22+/A22*/S22)*(A23**S23
+(A23*S23)*//AS)])) ;
/ ( (/ (/MASEL+ / ( (/00 *WO * /W1) + (/Ql *wo * /Wl) + (/Q2 * /WO *1'1l)
/DTACK
+ (/Q3*WO*Wl)))) *R-WN)
DTAK
/ (DTACK)
/R--W ~ / (R-WN) ;
REG ~ QO*Q1*Q2*Q3
Figure 4-11. FULLEXP PLHS501 .BEE File (Continued)
632
Signetics
PLHS501
Application Notes
Vol. 2
Programmable Logic Devices
MICRO CHANNEL INTERFACE
IBM's new Micro Channel Architecture
(MCA) bus implements new features not
found on the XT/ATbus. One new requirement for adapter designers is that of Programmable Option Select (paS) circuitry.
It allows system software to configure
each adapter card upon power on, thereby
eliminating option select switches or
jumpers on the main logic board and on
adapter cards.
Each adapter card slot has its own unique
-COSETUP signal routed to it. This allows
the CPU to interrogate each card individually upon power up. By activating a card's
-COSETUP line along with appropriate
address and control lines two unique 8 bit
10 numbers arefirsl read from the adapter.
Based upon the 10 number, the system
then writes into the card's option latches
configuration information that has been
stored in the system's CMOS RAM. The
CPU also activates pas latch address
102h bit 0, which is designated as a card
enable bit.
If a new card is added to the system, an
auto-configuration utility will be invoked.
Each adapter card has associated with it
a standardized Adapter Description File
with filename of @XXXX.ADF, where
XXX X is the hex 10 number of the card.
April 1989
The configuration utility prompts the user
according to the text provided in the .AOF
file and updates the card's latches and the
system's CMOS RAM.
provided for by circuitry within the
PLHS501. The external transceiver may
also be used by other devices on the
adapter card.
IBM reserves 8 add resses for byte-wide
pas latches, however, depending on the
card's function, not all addresses need to
be used. In addition, of those addresses
that are used, only the bits used need to be
latched. The first two addresses which are
reserved for reading the 10 bytes, and bit
oof the third address, which is defined as
a card enable bit, are mandatory. Some of
the remaining bits of the third address are
suggested by IBM to be used as inputs to
an I/O or memory address comparator to
provide for alternate card addresses.
Many adapter cards will not use more than
these three pas locations.
In this application, edge-triggered registers are not required and therefore should
not be used, as transparent latches use
fewer NAND gates to implement. Figure 5-2 shows the various latch circuits
described by the AMAZE equations. pas
byte 2 was made using four of the /B
device pins and four of the B pins. Notice
however, from Figure 5-2(B) that the bits
on the /B pins used the complement of the
input pin, thereby implementing a noninverting latch. Also, all 8 bits of this byte
were brought to output pins. If some of the
bits are not used by external circuitry, then
the specific bit latch may not be needed or
may be constructed entirely from foldback
NAND gates freeing additional pins.
The following example describes an implementation of pas circuitry realized in
a PLHS501. It uses only 56 of the possible
72 internal foldback NANO gates and only
a portion of the device pins, allowing additional circuitry to ba added. Figure 5-1
shows a block diagram of the circuit, and
Figures 5-3 and 5-4 are the AMAZE files.
Pins labeled 000-070 must be connected externally to pins 001-071. They
also must be connected through a 74F245
transceivertothe Micro Channel. External
transceiver direction and enable control is
633
An external F521 may be added to provide
for I/O address decoding. As the MCA bus
requires all16 bits of the 110 address to be
decoded, 8 bits may be assigned to the
F521 and 8 bits to the 501. Bit fields
decoded in the 501 may be done so in
conjunction with bits from pas byte 2 to
provide for alternate I/O addressing. Additionally, some of the available 501 outputs
may be used as device enables for other
devices on the card.
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
1:::;;::;:;\----
-ADL
BUFEN
L,..:::':;=-J--- DlR
-CDSETUP
-Mi-lO
-$.
-SO
-A2
7-81T
LATCH
-A.
-AIJ
BYTE
~======:t~ c::==== ) DATA
POS 2
OUTPUT
r--+--i I-CMD-------~
CHRESET
OCTAL
POS
1-;:t:=::JI
I-
MULTIPLEXER
3 to •
BYTE
•
CARD
I.D.
POS
BYTE
o
Figure 5-1. Block Diagram of Basic POS Implementation in PLHS501
D4I
SETUP
(SETUP)
/U
ADL
(INTERNAL NODE)
(A) Control Signal Input Latch (1 of 7)
(B) Data Latch of Bits 4 - 7
DOl
LO
(C) Data Latch of Bits 0 - 3
Figure 5-2. Latches Used In MCA Interface
April 1989
634
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
Fi!e
Date
Time
, MCPOSREG
5/31/1988
: 11:50:2
N?mp
##################### p I N
L I S T #####################
Right
LABEL
Left
LABEL
FNC **PIN
+5V
8-1
I
9-1
10-1
11-1
12-1
13-1
14-1
0
15-1
0
l6-1
0
17-1
0
18-1
0
19-1
OV
20-1
VCC
N/C
N/C
N/C
N/C
N/C
N/C
/L4
/L5
/L6
/L7
N/C
GNO
PIN** FNC
L
H
S
5
+5V **VCC
1-46
1-45
1-44
1-43
1-42
1-4l
1-40
1-39
1-38
1-37
1-36
1-35
1-34
I
I
I
/0
/0
/0
/0
0
0
/0
**D41
**031
**021
**011
**001
**L3
* *L2
**Ll
**LO
**D70
**060
**GND
Top
Bottom
LABEL
BUFEN
N/C
N/C
lOWE
N/C
N/C
N/C
000
010
020
030
040
050
FNC **PIN
0
21-1
0
22-1
0
23-1
/0
24-1
/0
25-1
/0
26- I
/0
27-1
0
28-1
29-1
0
0
30-1
0
31-1
0
32-1
0
33-1
PIN** FNC
p
L
H
s
5
0
11II11- 2
I- I
I-52
I-51
I-50
1-49
1-48
1-47
**
**
I
I
I
I
LABEL
**551
**550
**SETUP
**CMD
**A2
**Al
**AO
**MIO
**ADL
**RST
**D71
**D61
**051
Figure 5-3. PLHSS01 MCPOSREG Pinlis!
April 1989
635
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
File Name: MCPOSREG
Date:
5/31/1988
Time:
11: 50: 17
@DEVICE TYPE
PLHS501
@DRAWING
@REVISION
@DATE
@SYMBOL
@COMPANY
@NAME
@DESCRIPTION
Basic Programmable Option Select circuitry
for a Micro Channel Adaptor card
@INTERNAL NODE
/setupl,/miol,aOl,al1,/a21,ssOl,ss11;
len,outen,/iow;
@COMMON PRODUCT TERM
readO
(setupl*/ssll*ssOl*miol*/cmd*a21*/al1*/aOl);
readl
(setupl*/ss11*ssOl*miol*/cmd*a21*/all* aOl);
read2
(setupl*/ss11*sslO*miol*/cmd*a21* all*/aOl);
NOTE: In the above equations, setupl, miol and a21 all should be
preceded by a slash (/). The slash was omitted to correct for
a mapping error in AMAZE 1.65 when using active low internal node
definitions in common product terms.
b7h
b6h
b5h
b4h
b3h
b2h
blh
bah
0;
1;
1;
1;
1;
1;
1;
0;
" Define high 10 byte "
(POS byte #1)
7E hex
b7l
" Define low 10 byte "
1;
b61
1;
(POS byte #0)
b51
1;
FF hex
1;
b41
b31
1;
b21
1;
bIl
1;
bOI
1;
@I!O DIRECTION
~3-state output control of d7o-dOo"
xeD
(/setupl*/ssl1*ssOl*/miol*/cmd*a21*outen);
xel
(/setupl*/ssl1*ssOl*/miol*/cmd*a21*outen);
xe2
(/setupl*/ssll*ssOl*/miol*/cmd*a21*outen);
xe3
(/setupl*/ssll*ssOl*/miol*/cmd*a21*outen);
@I!O STEERING
Figure 5-4. PLHS501 MCPOSREG .BEE File (begins)
April 1989
636
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
@LOGIC EQUATION
" 7-Bit Input Latch for Control Signals "
Isetup1
fmoi!
ssll
5s01
la21
all
a01
Isetup*/ad1 + /setupl*adl;
+ fmio! *adl;
*adl;
+ 5511
*adl;
+ 5s01
*adl;
+ la21
*adl;
+ all
+ a01
*adl;
fmio */ad1
ssl */ad1
ssO */ad1
la2 */ad1
a1
*/ad1
aO
*/ad1
" Option Select Octal Data Latch (POS byte #2)
" 10 is to be used as a card enable signal"
len
"
I [/setup1*/ss01*ssll*/mio1*/cmd*/a21*a11*/aOl]; "write to latch"
1[/d7i * en]
1[/d6i * en]
1[/d5i * en]
I [/d4i * en]
1(/[ d3i * en
I (I[ d2i * en
I (I [ dli * en
I (I[ dOi * en
/17
/16
/15
114
13
12
11
10
*
*
*
*
*
*
*
*
1[17 * len]
1[16 * len]
1[15 * len]
* len]
1[14
Irst]
Irst]
Irst]
Irst]
*
*
*
*
1[13
1[12
1[11
1[10
*
*
*
*
*
*
*
*
[/rst] ;
[/rst] ;
[/rst];
[/rst] ;
len * Irst])
len * Irst])
len * Irst])
len * Irst])
;
;
;
;
\\ Octal 3 to 1 Multiplexer"
\\ This miltiplexer selects between reading
POS[O], POS[l] or POS[2] onto the data bus"
d70
(b7h*readl + b71*readO + 117*read2);
d60
(b6h*read1 + b61*readO + {16*read2);
d50
(b5h*readl + b51*readO + 115*read2);
d40
(b4h*readl + b41*readO + /14*read2);
d30
(b3h*readl + b31*readO + 13*read2);
d20
(b2h*readl + b21*readO + 12*.read2);
dl0
(b1h*readl + bl1*readO + 11*read2);
dOo
(bOh*readl + bOl*readO + 10*read2);
"3-State output control for d7o-dOo:
outen =/[all*aOl];
"External F245 transceiver control"
iowb
/iow
bufen
1(/a21 * Isetupl * miol * ss11 * IssOl);
1(/a21 * Isetupl * miol * ss11 * IssOl);
cmd * liow;
Figure 5-4. PLHS501 MCPOSREG .BEE File (end)
April 1989
637
Signetics
PLHS501
Application Notes
Vol. 2
Programmable Logic Devices
NuBus INTERFACE
In Apple Computer's book" "Designing
Cards and Drivers for Macintosh " and
Macintosh SE", an application was described for interfacing an 8-bit I/O controller to the NuBus. The controller used was
a SCSI controller of the type used on the
main Macintosh logic board. Seven
devices (three of which were PAL architecture) were used as control circuitry
interfacing the SCSI controller and two
RAM chips to the bus.
This example of using the PlHS501
shows a method of interfacing the same
SCSI controller and RAM chips to the
NuBus using only three parts. The adapter
card schematic is shown in Figure 6-2 and
the AMAZE listing is in Figure 6-6.
Although the AMAZE listing may seem
confusing at first glance, the circuitry
fused into the PlHS501 can be broken
down into small blocks of latches, flipflops, and schematically in Figures 6-4
and 6-5. Circuit timing is shown in Figure 6-3.
Referring to Figure 6-4 and Figure 6-5,
the circuitry starts a transaction by first
detecting a valid address in either the slot
or super slot range. The detection is accomplished by two wide-input NAND
gates, and controlled by the IClK signal.
Following each NAND gate is an S-R
latch to hold the signal until near the end
olthe cycle. The two S-R latch signals are
combined into one signal named STO
such that if either NAN D gate output was
low, then some delay time after the rising
edge of IClK, STO will go low. The next
MASTER
rising edge of IClK will cause signal ST1
to go low. This sets signal DE210w, which
is an input to an external flip-flop to cause
ST2 to go low at the next rising IClK edge
terminating the cycle. An external flip-flop
was necessary to achieve a high-speed
IClK to !lOR and lACK transition. Also, an
external FI25 buffer was added to meed
the soon to be approved IEEE P1196
specrrication requirement of 60mA 10l for
signal INMRQ and 24mA 10L for signals
ITMOITM1 and lACK. Figure 6-5(B)
shows an easily implemented latch which
controls interrupts generated by the SCSI
controller passing onto the bus. Upon
IRESETthe latch is put into a known state.
Under software control, by writing to a
decoded address, the latch may be set or
reset, thereby gating or blocking the interrupt signals.
SLAVE
r-------------'r-------,
OTiO
NUBUS
Figure 6-1. Simplified NuBuS™ Diagram
• Designing Cards and Drivers for Macintosh" and Macintosh SE, Adcison-Wesley Publishing Company. Inc. 1987.
April 1989
638
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
74~2S
mMRa~~----------------------------------------~~~------------------------------------~------<;1J----1
~MO
;1~
r--:
~
IACKc::>----------------------------------------~r+-------~~~+--1
ISTART
,-...c=>---------1H-+t-t+----+--1>-I>=Ola
IR~~~t=S
ill1
nD3~
nD2r-:
~~B
I
PU
~~~~ d~~~~~~
- WI- -
IA031 --
4 ~1'20~--_q_----------j 07
IA030
IIAAD
D2928 : : :
5
6 AS
IA025 ==::
IAD24:::
Al
81 14
01
11 AD
BO 13
00
A6
os!!: ~
86 19
OS 1.
OS
B4 17
F~~;:=:==~7~A4
;:g~ ::::;
::~:~ :~
10
--r
~
GND ----t CAB COA
GND
GND
SAO SOA ~ GND
nORI
GAO GOA 1]21
--+
04
g:
PLHS501
INMREa.f-:::====4==;==::t~_
RESETO
~
IRESETBI-
ISTO I----------t-fj----j
0 a 1--;------ nOR
~ DROf----- ORO
IRa f____ IRa
74F74
0
IADCLK--,-l/_A~~~C:!!tL~~--~~L~~~!!;~~~~~W~R~f----==-·m°;AwMcs-------'
'" '" '"
IRAMCS
)1)
~
I
=<
IIAAD
04
;~~h
I
IA019
•
IADI8~
:
~ fRAMeS
6264CS2 f=--- PU
18
IT----
16
~
44
1~::
Al
AO
~ IEDP
IDACK--¥. IDACK
ICS ----To ICS
ISEL
IBSY
07
L'
05
06
l:::===~2~1~
~===~2!s~A9
l'
!~
24
A10
A11
~f.17~~~~~
BB4S 17
a
A3
~E==!====~98A2
:~h:~
10 ~
B11e:!l:t===~
BOle
WE
15
fF-- now
nOR
g~~ ~
~ :t?MCS
OE
6264f2764
--t
Figure 6-2. Adapter Card Schematic
639
HAl
~AO
32
40
50
46
ICNO
42
IMSG~ 48
r,g-----
IREa
F-,",-
IRESET
F!--- IRESETO
GND
16
g~ ~~
04
sKxs
~::f----------"'J
r,t----- :
r,r-IATN r,sIRST l i t nNO r,a-------lACK
:g:~ ~g~
~A2
:·'---------c2.;~rl A12
ADCLK----t CAO CBA~GND
PU~
SAB SOA rr,- GND
L--'- GAO GOA F- PU
~
April 1989
E
ORa--¥a ORa
IRa ---'" IRa
A7Ei7'-'~~9~==i~===3:a~~
R!,M ~~ltil~====J
B6 ~,.
7 A4 PROM
27
6 A6
7 AA4S
11
~
OE ~ now
nOR
WE
CSl
~: ~
VCC lOOP
~~ ~ :~
8====j~~:~:!" ~:~
~
~5 i ~
'~
~====!!~
~~
.Kxa g~ ~'~1~t:===:::L~===~404 go SC~ ~:2 i 8
t
SASRAMOOI-"
I~CTRR/D~~_2:
IAD1Sc::>--------;4H'A7"'B7 ~
IAD14?=<
~ AA6S 0056 18
7 A4
B4 17
IAD11
: A3
B3Hi:~;------'
IAD101-<
10 AA~
:~1$.14!===~
IAD9~
11 AD
BOLI'.!!13'---_ ___'
IA08~
•
~ :~
34
26
10'"
1"
GND
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
{ClK
/START
AClK
T~--,~~----l~~----~----~I
/SLOT/sUPER - - - -......J
STO
----------l
ST.
-----4-----l
ST2-----4----~----_l
{ACK
----------I------f------i...
nOR
--------1..
now
----------l
Figure 6-3. Timing Diagram
D4---~
D7-----I
START - - - - - 1
{ACK-----1
ClK-----1
{RESET - - - - - I
/SLT
»-~o-'- STO
{elK
D-lATCH WITH INTEGRAL AND GATE INPUT
(DELAY INPUT UNTIL RISING EDGE OF IClK)
START - - - - - 1
{ACK-----1
elK:::====~
/SUP
{RESET
Figure 6-4. Decoding and Latch Circuitry
April 1989
640
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
ISlO
,RESET
IHESET
IRESET
ISLOT
ICLK
ISTO
ISUPER
leLK
/sLT
TMll
TMI
AD/elK
ISLT
ISUP
IRESET
ISTO~STl
ICLK-LJ
(A) Four Internal Flip-Flops Constructed from NAND Gates.
""""'Jr------r'b-....JI.'!N:!'TE~N~___;
Slot*'OW*SetAddr - - -. .
Slot*'QW-ReaetAddr
AND-OR FUNCTIONS
DRG-+--~~L_~
--II~\:r-------'=l
IRQ ----'~L_~
IRESET
(8) Interrupt Enable Control Latch
Internal Flip-Flops and Latches
Figure 6-5. Internal Flip-Flops and Latches
April 1989
641
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
##################### P I N
LIS T #####################
Left
LABEL
VCC
/ID2
/ID3
DRQ
IRQ
ST2
N/C
N/C
N/C
N/C
N/C
N/C
GND
FNC **PIN
+5V
8-1
I
9-[
10-[
PIN** FNC
12-1
P
L
13-[
H
14-[
15-[
16-[
S
5
1l-[
**
0
0
** 0
0
0
OV
17-[
18-[
19-[
20-[
+5V
1-46
[-45
I
[-44
[-43
[-42 **
[-41
I
[-40
/0
[-39
/0
[-38
/0
[-37
/0
[-36
0
[-35
0
[-34
/0
N/C
N/C
ACLK
/ROMCS
/RAMCS
N/C
/NMRQ
DE2
/RESET
/SCSI
/DACK
/IORR
/IOW
FNC **PIN
0
21-[
0
22-[
0
23-[
/0
24-[
/0
25-[
/0
26-1
27-[
/0
0
28-[
0
29-[
0
30-[
** 0
** 31-[
0
32-[
** 0
33-[
**5TO
**N/C
**N/C
**N/C
**N/C
**N/C
**GND
P
L
H
S
[[- 5
[[- 3
[- 2
[[.-52
[-51
[-50
[-49
[-48
[-47 **
**/IDO
**/RESET
**/TM1
**/ACK
**/START
DecodeR
(dO*idO+/dO*/idO);
(dl*idl+/dl*/idl);
~Address
Figure !Hi. AMAZE Usting (begins)
642
LABEL
**/ID1
slotn,supern;
@COMMON PRODUCT TERM
@I/O DIRECTION
@I/O STEERING
@LOGIC EQUATION
April 1989
**AIB
**A9
[-
setad,rstad,inten:
~
**DO
**A19
PIN** FNC
@DEVICE TYPE
PLHSS01
@DRAWING
@REVISION
@DATE
@SYMBOL
@COMPANY
@NAMB
@DESCRIPTION
SCSI-NuBus Interface
@INTERNAL NODE
/sl,/sp,/SLOT,/SUPER;
snl,sn2,rnl,rn2;
sn3,rn3,stl;
sn4,rn4,tmll,tmlln;
CMP3a,CMP2a,CMPla,CMPOa;
CMP3b,CMP2b,CMP1b,CMPDb;
/slt,/sup,stln,adclk:
cmpOa
cmp1a
**VCC
**D1
Top
Bottom
LABEL
Right
LABEL
**/CLK
**D7
**D6
**D5
**D4
**03
**D2
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
cmp2a
cmp3a
cmpOb
emplb
cmp2b
cmp3b
(d2*id2+/d2*/id21;
(d3*id3,/d3*/id31;
(d4*idO+/d4*/idOI;
(d5*idl+/d5*/idll;
(d6*id2+/d6*/id21;
(d7*id3+/d7*/id31;
lsI
/(d7*d6*d4*cmpDa*cmpld*cmp2a*cmp3a*start*/ack*clk);
/(cmpOb*cmplb*cmp2b*cmp3b*start*/ack*clk);
"latch slot signal"
/slt ~ /llreset*st2*/I/sl*/slt]l;
"latch super signal"
Isup = /(/reset*st2*/[/sp*/sup]);
"Let /slt or Isup through only
until after the rising edge
of / elk"
stO
/ (/ [/slt*/sup*clk] * / [stO*clkJ * / [/slt*/sup*stO]
"Slot signal D-type Flip-Flop"
/sp
snl
* /reset);
/(/clk*slt*(/[snl*/reset*/super*(/[stO*rnl*/slt])]));
eni
/ IIclk*sni* II IstO*rni*/slt] II;
Islot = /(/reset*/super*snl*slotn);
slotn = f{//slot*rnl*/sltl;
"Super signal D-type Flip-Flop"
sn2 = I (/clk*/sup* (/ [sn2*/reset*/slot* (/ [stO*rn2*/sup])]));
rn2 ~ / IIcik*sn2* II IstO*rn2*/sup] 1 I;
/super = /(/reset*/slot*sn2*supern);
supern = /(/super*rn2*/sup);
~State 1 D-type Flip-Flop"
sn3
/ (/elk* II Isn3*/reset* II IstO*rn3] I] 1 I;
rn3
/(/clk*sn3*(/lstO*rn3]11;
stl
/(/reset*sn3*stln);
stin~ / Isti*rn3];
"output to external flop"
de2 ~ /(stin * st21;
~address latch clock"
adclk = clk*stO*stl;
aclk = clk*stO*stl;
~latch tml signal for r/w info"
sn4 ~ /(adcik*/reset*(/lsn4*(/I/tmi*rn4*/reset]I]II;
rn4 = /(adclk*sn4*(/[/tml*rn4*/reset]));
tmll = /(sn4*tmlln);
tmlln= / (rn4*/reset*tmll);
tmll ->
tmlln -)
read,
read,
write
write
"straight decode stuff"
/iorr
/(/stO*tmil
/iow
/(/tmiln*stO
/scsi
/(slotn*/a19*/a18*/a9
/dack
/(slotn*/al9*/al8* a9
/ramcs= /(slotn* al9* al8
/ramcs= /(supern
/resetb= /reset;
"interrupt control latch"
set ad
/(tmlln*/stO*slotn* al9*/al8* a9);
rstad
/(tmlln*/stO*slotn* a19*/al8*/a9);
inten
/(setad*(/[inten*rstad*/reset]));
/nmrq
/(inten*drq+inten*irq) ;
*
*
*
*
*
*
/reset);
/reset);
/reset);
/reset);
/reset);
/reset);
Figure 6-6. AMAZE Listing (end)
April 1989
643
SigneHcs
PLHS501
Application Notes
Vol. 2
Programmable Logic Devices
NUGGETS
of the inputs. It would seem that there
must be some "best" way to generate and
detect parity. Recall thatthe PLHS501 can
generate both deep logic functions (lots of
levels) and wide logic functions (lots of
inputs). The best solution would require
the fewest gates and the fewest number of
logic levels. Let's review the basics. first.
Table 7-1 (A) shows the parity function for
two variables and Table 7-1(8) shows it
for three variables. The Ex-OR function
generates even parity.
Much current focus for microprocessor
design is on the address bus. Typically,
most designers assume the processor will
handle the data manipulation and the data
bus is assumed to be a straight, clean path
to and from the memory. Data transformations may be accomplished for specific
purposes when the application requires it.
For instance, a classic transformation
from the early 70's was the bit reversal required to address operands for a Fast
Fourier Transformation. When designers
implemented bit reversal as a separate
hardware process, the whole system improved. Likewise for hardware multipliers.
cannot support 8 (27+1_129). Hence. it is
appropriate to seek a cascaded solution.
hopefully taking advantage of the available output Ex-OR functions. Let's solve
a 16 input Ex-OR function, by subpartitioning. First, consider Figure 7-1 (A)
where two literals are Exclusive-ORed to
generate an intermediate Ex-OR function. This requires available complementary inputs and generates even parity in
two levels. Figure 7-1 (8) also does this
(by factoring), requiring 3 gate levels. but
does not require complementary inputs.
It is noticeable that there are precisely
50% logical 1 entries in the truth tables.
This yields the famous checkerboard
Karnaugh Maps. With a checkerboard Kmap. no simplification of Ex-OR functions
is possible by Boolean simplification. The
two variable Ex-OR has two ones (implying 3 gates to generate). the 3 variable has
four ones (implying 5 gates to generate).
In general. 20-1+1 product terms could
generate Ex-OR functions in two levels of
NAND gates (assuming complementary
input variables exist). You must have an
unlimited number of gate inputs for this to
hold.
Also, a hidden ''transformation" is the
appending of parity and the calculation of
E.C.C. polynomials. Clearly, when the deSigner recognizes that significant performance improvement can be achieved by
realizing the payoff attainable with a special purpose hardware device, he should
design it. For example. let's consider
parity generation:
Data Bus Parity
The PLHS501 can span 32 bits of input
data. It has four output Ex-OR gates, and
the ability to generate literally any function
Assuming inputs must get into the
PLHS501 through the pin receivers, it is
best to generate as wide of an initial
Ex-OR as possible. so a structure like
Figure 7-1 (A) expanded is appropriate.
Figure 7-1 shows a 2-level 4 input
Ex-OR function which may be viewed as
a building block. This structure may be
repeated four times. across four sets of
four input bits generating partial intermediate parity values which may then be
treated through two boxes similar to Figure 7-1 (8). These outputs are finally combined through an output Ex-OR at a
PLHS501 output pin. Figure 7-3 shows
the complete solution which requires 44
NANOs plus one Ex-OR.
The PLHS501 could do this for 7 input
variables in two levels (Z;+ 1=65), but
A
B
A$B
A
B
0
0
0
0
1
1
0
0
0
0
0
0
0
t
0
1
0
0
1
Table 7-1 (A).
C
0
1
0
1
0
1
0
Table 7-1 (B).
Table 7-1. Even Parity Functions
April 1989
644
A$B
0
1
1
0
1
0
0
Signelics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
. . - - INPUTS
-I"
2LEVELS
---i
~:JOo-W$'
Figure 7-1(A).
Figure 7-1(B).
Figure 7-1. Complementary Input Levels
J[
B
C
D
!
~D
A~;
B~:
c~~
D~:
A
~
D
J[
B
C
D
•
C
D
Ic
D
A
B
I~
C
D
AE9BE9cE9D
4-lNPUT EX-OR SYMBOl.
Figure 7-2. Four Vsrlable Ex-ORs
April 1989
645
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
11
A
12
B
13
C
14
D
15
A
Ie
17
Ie
B
II
A
C
RG. 7-2
RG. 7-2
L
I
RG. 7-1(B)
D
110
B
111
112
C
113
A
RG. 7-2
D
11.
B
115
C
116
D
AG.7-2
L
I
AG. 7-1(B)
==:
~~N~l!!:is + 1Ex-oR.
Figure 7-3. 16 Input Even Parity Generation
April 1989
646
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
Two examples follow which were supplied by
one of our European Sales Engineers, Nils
Lindgren. The first, called "paritet", calculates
even and odd parity for 24 input literals. Several
output options are available and the design
uses a cascade with a different partitioning than
just previously discussed.
relatively long design equation into Signetics
AMAZE.
The second example "compare" implements, a
16--bit comparator over 32 input bits. The design generates outputs for conditions representing the classic "EQUAL", "AGTB" (A>B)
and BGTA (B>A). The long, triangularized
equation for T 42 suggests that Nils found a
clever editing approach to accurately enter a
File Name : PAR1TET
Date
5/31/1988
Time : 10:26:22
##################### P I N
L I 5 T #####################
Left
FNC **PIN
LABEL
VCC
+5V
A
I
B
c
I
0
E
F
N/C
N/C
N/C
N/C
N/C
GND
I
I
B
B
B
B
0
ov
8-1
9-1
10-1
ll-I
12-1
13-1
14-1
15-1
16-1
17-1
18-1
19- I
20-1
P
L
H
S
5
PIN**
1-46
1-45
1-44
1-43
1-42
1-41
1-40
1-39
1-38
1-37
1-36
1-35
1-34
FNC
Right
LABEL
+5V **VCC
I
I
I
I
/0
/0
/0
a
**K
**J
**1
**H
**G
**N/c
**N/C
**N/C
**OEN
0
**N/C
**N/C
ov
**GND
Bottom
LABEL
N/C
N/C
ODD_OC
ODD
EVEN
EVEN OC
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Top
FNC **PIN
0
21-1
0
0
/0
/0
/0
/0
0
0
0
0
0
0
22-1
23-1
24-1
25-1
** 26-1
27-1
28-1
29-1
30-1
31-1
32-1
33-1
p
L
H
s
5
PIN** FNC
**y
I
1- 7
**X
1- 6
**V
1- 5 **
**U
1**T
1**5
1**R
I- I
I-52
**0
**p
I-51
**0
I-50
**N
1-49
**M
1-48
1-47
**L
Figure 7-4_ PARITET PLHSS01 PlnUsl
April 1989
647
LABEL
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
File Name : PARITET
@DEVICE TYPE
PLHSS01
@DRAWING
@REVISION
@DATE
1988
@SYMBOL
@COMPANY
Philips
@NAME
Nils Lindgren
@DESCRIPTION
24 bit parity circuit
@INTERNAL NODE
JO J1 J2 J3 J4 JS J6 J7 JS J9 TO T1 T2 T3
@COMMON PRODUCT TERM
@I/O DIRECTION
OE1=T2*T3*/OEN;
OE2=/OEN;
OE3=TO*T1*/OEN;
@I/O STEERING
@LOGIC EQUATION
"FIRST LEVEL: 'EVEN' FROM GROUPS OF THREE INPUTS·
JO=/A*/B*/C + /A*B*C + A*/B*C + A*B*/C;
J1=/D*/E*/F + /D*E*F + D*/E*F + D*E*/F;
J2=/G*/H*/I + /G*H*I + G*/H*I + G*H*/I;
J3=/J*/K*/L + /J*K*L + J*/K*L + J*K*/L;
J4=/M*/N*/O + /M*N*O + M*/N*O + M*N*/O;
J5=/P*/Q*/R + /P*Q*R + P*/Q*R + P*Q*/R;
J6=/S*/T*/U + /S*T*U + S*/T*U + S*T*/U;
J7=/V*/X*/Y + /V*X*y + V*/X*y + V*X*/Y;
"SECOND LEVEL: 'EVEN' FROM FOUR GROUPS AT A TIMEN
JS=/JO*/J1*/J2*/J3 + /JO*/J1*J2*J3 + JO*J1*/J1*/J3 +
+ JO*/J1*/J2*J3 + /JO*J1*/J2*J3 + JO*/J1*J2*/J3 +
J9=/J4*/JS*/J6*/J7 + /J4*/JS*J6*J7 + J4*JS*/J6*/J7 +
+ J4*/JS*/J6*J7 + /J4*JS*/J6*J7 + J4*/JS*J6*/J7 +
TO=/(JS*J9);
T1=/(/JS*/J9);
T2=/(JS*/J9);
T3=/ (/J8*J9);
ODD=/(T2*T3);
EVEN=/(TO*T1);
ODD_OC=O;
EVEN_OC=/(l);
/JO*J1*J2*J3
JO*J1*J2*J3;
/J4*JS*J6*J7
J4*JS*J6*J7;
Figure 7-5. PARITET PLHS501 .BEE File
April 1989
648
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
File Name : compare
Date
5/31/1988
Time : 10:25:29
##################### P I N
L I S T #####################
Left
LABEL
vee
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
N/e
GND
FNe **PIN
+5V
8-1
I
9-1
10-1
ll-I
12-1
13-1
**
14-1
15-1
16-1
17-1
18-1
0
19- I
OV
20-1
P
L
H
S
5
PIN**
1-46
1-45
1-44 **
1-43
1-42
1-41
1-40
1-39
1-38
1-37
1-36
1-35
1-34
Right
FNe
LABEL
+5V **vcc
I
**BO
**AF
**AE
**AD
**AC
**AB
**AA
0
0
OV
**N/C
"!{*N/c
**GND
Top
Bottom
LABEL
EQUAL
AGTB
BGTA
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/e
**B2
**B1
FNe **PIN
0
210
220
2324/0
25/0
** 26/0
/0
270
280
290
300
310
320
33-
PIN** FNC
P
L
H
S
5
0
1111-
111I-52
I-51
I-50
1-49
1-48
1-47
LABEL
**BF
**BE
**BO
**BC
**BB
**BA
**B9
**B8
**B7
**B6
**B5
**B4
**B3
Figure 7~. PLHSS01 Plnlisl for 16-811 Comparator
File Name : compare
Date
5/31/1988
Time: 10:25:43
@DEVICE TYPE
PLHS501
@DRAWING
@REVISION
@DATE
@SYMBOL
@eOMPANY
PHILIPS
@NAME
NILS LINDGREN
@DESCRIPTION
16 BIT COMPARATOR WITH THREE OUTPUTS:
EQUAL,AGTB (A>B) , AND BGTA (B>A)
Figure 7-7. Compare PLHS501 .BEE File (begins)
April 1989
649
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
@INTERNAL NODE
Tl T2 T3 T4 T5
T9 TlD Tll Tl2 T13
T17 Tl8 Tl9 T20 T2l
T25 T26 T27 T28 T29
T4l T42
@COMMON PRODUCT TERM
@I/O DIRECTION
@I/O STEERING
@LOGIC EQUATION
Tl~/(AF*/BF);
T3~/
(AE*/BE);
T5~/(AD*/BD);
T7~/(AC*/BC);
(AB*/BB);
(AA*/BA);
T13~/ (A9* /B9);
T9~/
Tll~/
Tl5~/(A8*/B8);
Tl7~/(A7*/B7);
Tl9~/
T21~/
T23~/
T25~/
(A6*/B6);
(A5*/B5);
(M * /M) ;
(A3*/B3);
T27~/(A2*/B2);
;
(AD*/BO);
T29~/(Al*/B2)
T3l~/
T6
Tl4
T22
T3D
T7
Tl5
T23
T3l
T8
T16
T24
T32
(/AF*BF);
(/AE*BE);
T6~/ (/AD*BD);
T8~/ (/AC*BC) ;
TlD~/ (/AB*BB);
Tl2~/ (/AA*BA);
Tl4"~/ (/A9*B9);
Tl6~/ (/A8*B8);
Tl8~/ (/A7*B7);
T2D~/ (/A6*B6);
T22~/ (/A5*B5);
T24~/ (/M*B4);
T26~/ (/A3*B3);
T28~/ (/A2*B2);
T30~/ (/Al*Bl);
T32~/ (/AO*BO) ;
T2~/
T4~/
T4l~Tl*T2*T3*T4*T5*T6*T7*T8*T9*TlO*Tll*Tl2*Tl3*Tl4*Tl5*Tl6*Tl7*
T42~
Tl8*Tl9*T20*T2l*T22*T23*T24*T25*T26*T27*T28*T29*T3D*T3l*T32;
ITl +
/T3*T2+
/T5*T4*T2+
/T7*T6*T4*T2+
IT9*'J'8*T6*T4 *T2-+
/T11*T10*T8*T6*T4*T2+
/Tl3*Tl2*TlO*T8*T6*T4*T2+
/Tl5*Tl4*Tl2*TlO*T8*T6*T4*T2+
/Tl7*Tl6*Tl4*Tl2*TlO*T8*T6*T4*T2+
/Tl9*Tl8*Tl6*Tl4*Tl2*TlO*T8*T6*T4*T2+
/T2l*T20*Tl8*Tl6*Tl4*Tl2*TlO*T8*T6*T4*T2+
/T23*T22*T20*Tl8*Tl6*Tl4*Tl2*TlO*T8*T6*T4*T2+
/T25*T24*T22*T20*Tl8*Tl6*Tl4*Tl2*TlO*T8*T6*T4*T2+
/T27*T26*T24*T22*T20*T18*T16*T14*T12*T10*T8*T6*T4*T2+
/T29*T28*T26*T24*T22*T20*T18*T16*T14*T12*T10*T8*T6*T4*T2+
/T3l*T30*T28*T26*T24*T22*T20*Tl8*Tl6*Tl4*T12*TlO*T8*T6*T4*T2;
EQUAL~T4l;
AGTB~T42;
BGTA~/(T41+T42)
;
Figure 7-7. Compare PLHS501 .BEE File (end)
April 1989
650
Signetics Programmable Logic Devices
PLHS501
Application Notes Vol. 2
Data Bus Operations
The following is basically an academic
example, posed for the sake of illustration. Suppose some special data bus operations are
desirable. For the purpose of illustration, let's
label the microprocessor bus output side as
ODATO-ODAT15 and the output of our
PLHS501 as 00-015. Basically, the microprocessor will output straight data and the
PLHS501 will alter it according to some plan.
We will replicate multiple identical cells, but
they need not be identical in practice. Table 7-2
shows the operations to be done (justaboutany
could be chosen, provided they meet the gate
budget).
Table 7-2. Data Operations
12
1,
DouT
0
0
ODATI (pass)
0
1
ODATI (complement)
1
0
SWITCH
1
1
DOUBLE SHIFT
April 1989
ODAn
n:
nt
IDDAn
n2
11
DouT
oDAn.N
nl
12
n2
nt
ODAl1+2
Figure 7~. Basic Cell Structure
It may be observed that in one mode, the data
passes direcUy, it complements in another,
switches bits in another and rotates right in the
last Four input gates per bitare required to map
the bits, and one output gate. Clearly, the
straight PLHS501 NAND outputs can be judiciously used, but care must be taken when using other output functions. A 16--bit data bus
requires 16 cell configuration where each cell
is essentially identical to Figure 7~, but its internal structure may be altered to account for
the particular output pins logic function.
651
Signetics
PLHS502
Application Notes
Vol. 1
Programmable Logic Devices
INTRODUCTION
Certain design techniques are used
repeatedly by nearly all digital systems
designers. If these useful building blocks
occur w~h enough volume production,
they become special purpose contenders
for silicon manufacturers to justify rendering as standard products. Some building
blocks, however, are never viewed as
likely candidates because the performance requirements may be too high, the
volumes not high enough, or it never occurred to marketeers that these subsystems would be valuable. System
designers could fashion solutions to these
building blocks from glue logic or PLDs
and sometimes small gate arrays. Several
typical building blocks will be illustrated
here - including a 4-byte datapipe, a
small content addressable memory
(CAM), a system resource scoreboard
and a synchronous receiverltransmitter.
The generation of each building block will
be demonstrated w~h a Signetics
PLHS502 (Figure 1-1). This device is rendered in the Programmable Macro Logic
August 1989
(PML) architecture which deftly bridges
the gap between gate arrays and ordinary
PLDs.
Designed w~h a high-speed bipolar
process, the PLHS502 combines 64
extremely wide fold back NAND gates with
two types of internal flip-flops. The
PLHS502 provides 8 internal D flip-flops
and 8 internal S-R flip-flops. Each flipflop can toggle in excess of 50MHz.
These flip-flops are called "hard macro'
flip-flops. Unique among such programmable devices, each flip-flop has completely independent clocking. This allows
e~her external clocking (from four different pins) or internally derived clocking
events. Ripple and synchronous controllers may be freely mixed. It should be
remembered that additional flip-flops and
specially custom designed flip-flops may
be configured from the NAND array. Clock
independence is a requirement for generating distinct internal sequencers and
controllers. Additionally, itshould be noted
that the flip-flop Q outputs cross the clock
652
fusing array, but 0" outputs do not. The
PLHS502 is packaged in a 68-pin PLCC.
This application note consists of several
sections. The next section briefly describes Signetics SNAP software package for implementing PML designs.
Section 3 describes the basic process for
estimating whether a design will fit into a
PLHS502. In Section 4, some guidelines
for designing synchronous state machines are given with focus on efficient
counter and shifter design. Specific examples are included which may be easily
mimiced for successful state machine design. Additional guidelines are then provided in Section 5, for optimizing a design
before it is implemented with SNAP.
These guidelines will help guarantee that
SNAP implements the function preCisely
as needed. In Section 6, some larger examples are provided which iIIustratesome
interesting and unique capabilities of the
PLHS502. Section 7 details a procedure
for merging logic functions into flip-flops
for faster, more efficient structures.
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
9"
.
""
J~i~'
~~
....
.
1\ K~
.......
5i
.
~
:gr-
~
r--
d
···
···
...
~~ ...
~··
...
gt1
a:5(J
~
.
~
.. ...
~
II!w
......::>
:!!
Agure 1-1.
August 1989
..
PLHS502 logic Diagram
653
···
~~.
Signetics
PLHS502
Application Notes
Vol. 1
Programmable Logic Devices
DEVELOPMENT SUPPORT
Because the architecture encourages
deep functional nesting, a new support
tool has been developed. Synthesis, Netlist, Analysis and Program (SNAP) software defines a gate array type
development environment. SNAP permits several forms of design capture
(schematic, Boolean equations, state
equations, etc.), a gate array simulator
with back annotation, waveform display
and a complete fault analyzer and final
fusemap compilation and model extraction. SNAP comes with a library of cells,
and designs may be captured independently of the ultimate device that will implement the design. This permits the
designer to migrate his design among a
family of PML devices just as gate array
designs can be moved to larger foundations when they do not route on smaller
ones. Figure 2-1 shows the SNAP user
interface "Shell" which dictates one sequence of operations to complete a design. Other sequences may be used.
The top portion of the shell depicts the
paths available for design entry. Any de-
sign may be implemented in anyone or a
blend of all methods. For instance, a shift
register might best be described schematically but a decoder by logic equations.
These may be united with a multiplexor
described by a text nellist as well. Ultimately, each form of input will be transformed to a function nellist and passed
either to the simulation section or to the
compiler section. Waveform entry is for
simulation stimuli.
The simulator portion of SNAP is a
5-State gate array simulator with full timing information, setup and hold time
checking, toggle and fault grade analysis
and the ability to display in a wide range of
formats, any set of nodes within the design. This permits a designer to zoom in
with a synthetic logic state analyzer and
view the behavior of any point in the design. Simulations can occur with unit delays, estimations or exact delays. The
sequence of operations depicted in Figure
2':'1 is entirely arbitrary, as many other
paths exist.
It should be noted that the output of the
FutureNeI and DASH are trademarks of DATA va
August 1989
654
"merger" block represents the composite
design, but as yet is not associated to a
PML device. This occurs in the compiler
portion wherein association to the device
occurs and a fusemap is compiled. This is
analogous to placement and routing in a
gate array environment. Because of the
interconnectibility of PML, this is not difficult. Once compiled, the exact assignment of pins, gates and flip-flops is
known, so timing parameters may be
associated and a new simulation model
generated with exact detailed timing embedded. The design may be simulated
very accurately at this point, and if correct,
a part should be programmed.
To facilitate future migration to workstations, SNAP has been written largely in
c. The internal design representation is
EDIF (Electronic Design Interchange Format) compatible which permits straightforward porting to many commercially
viable environments. SNAP currently utilizes OrCAD for schematic entry with
eminent availability of FutureNet Tht
DASH.
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
I
WAV~rMS
l
NETWAVE
I
I
BOOLEAN
ScCAPTURE
I
=I=
EDITOR
I
I
••
l
I
NETCONV
~
STATECONV
I
I
MERGER
I
TESTVECTOR
~
'--_Sl_MI'_RT_---II-i
PLOT
~
I
SlMFLT
I
Figure 2-1. SNAP Shell Design
August 1989
655
DPI
I
Signefics
PLHS502
Application Notes
Vol. 1
Programmable Logic Devices
CAPACITY AND PARTITIONING
CONSIDERATIONS
One of the dominant attributes of PML
architecture is its complete interconnectibility. Anyfunction-NAND, flip-flop, input
and output structures, can be connected
to any other. PML devices do not exhibit
the restricted interconnect bottleneck like
other programmable gate arrays. If there
is capacity within the part for a function, it
can be connected withoutthe sad surprise
ending of "nonroutability". Estimation for
design fit is simply a matteroftallyingfunction usage against a fixed set of resources
using a table lookup. An elementary table
of typical useful functions is provided in
Table 3-1. Clearly Table 3-1 shows only
a few of the typical functions achievable
and their relative "expense" from the total
function budget. As with gate arrays, the
designer needs only to implement the
portion of his chosen function that is to be
actually used.
Fortunately, if the designer is using SNAP,
all unused functions will be automatically
eliminated. This is done by nellist analysis
where SNAP observes an output within
your circuit which is unconnected. It
eliminates the unconnected gate and
reanalyzes to see if there are more unconnected gates in the design. The procedure
iterates until there are no more unconnected gates. When estimating whether a
function will fit or not, the values in Table
3-1, if used without modification, should
result in a high gate count. So, to more accurately assess fit, they should be derated
to account for automatic nellist trimming.
As well, the estimator should consider logic functions which can be obtained for
'1ree" from input buffers and output functions. Guidelines, provided in Section 5,
will illustrate this process.
TABLE 3-1. PLHS502 GATE EQUIVALENT TABLE
FUNCTtON
INTERNAL
NAND
EQUIVALENT
COMMENTS
Gates:
NANOs
ANDs
NORs
ORs
For 1 to 32-pin input variables
Add'i internal inputs can be used as needed
Add'i internal inputs can be used as needed
Add'l internal inputs can be used as needed
Gate Macro Flip-Flops:
D-FF
SR-FF
N/A
N/A
Total Budget ~ 8
Total Budget ~ 8
D-FF
T-FF
J-K-FF
Tran sparent-D Latch
S-R Latch
6
6
10
4
With async S-R
With async S-R
With async S-R
With async S-R
With async S-R
3 t08
4 to 16
5 to 32
8
16
32
Inverted inputs available
Inverted inputs available
Inverted inputs available
(24 chip outputs only)
8103
16 t04
32 t05
15
32
41
Inverted inputs, 2 logic levels
Inverted inputs, 2 logic levels
Inverted inputs, 2 logic levels
4 to 1
8 to 1
16 to 1
2710 1
5
9
17
28
Gate Implemented Flip-Flops:
2
Decoders:
Encoders:
Multiplexors:
Inverted inputs available
Inverted inputs available
Inverted inputs available
Can address only 27 externally inputs - more if internal only.
This disallows clock inputs to flip-flop.
PLHS502 Rough Resource Budget ~ 64 NANOs, 8 D, 8 SR, 24 inputs, 16 outputs, 8 bidirect.
August 1989
656
Signetics
PLHS502
Application Notes
Vol. 1
Programmable Logic Devices
STATE MACHINE DESIGN
Synchronous state machines can be classified in roughly three practical categories
- sequence generators, sequence detectors and controllers. These can also be
subcategorized as Mealy, Moore, finite
state, linear, etc. A very large application
market is covered, by considering the basic design of counters and shifters because a counter (with possible decoding)
can be viewed as a generalized sequence
generator and a shifter (with decoding)
can be viewed as a sequence detector. A
couple of small examples should illustrate
the basic principles of flip-flop selection,
picking optimal solutions and trading off
hard macro and soft macro functions.
First, a few small counters will be dis-
cussed in detail from a logic viewpoint.
Then, small shifters will be shown. These
basic designs are extendible so that a
designer can recognize the patterns to
make the counters and shifters bigger if
necessary. In the next section, some general guidelines forgetting "smaller, tighter"
designs will be given.
Counter Design Notes
A straightforward 3-bit up/down counter
transition table is depicted in Figure
4-1 (a). The state variables are designated A, B, C and the direction control is
U. Up counting occurs when U = 1 and
down counting occurs when U = O. Figure
4-1 (b) shows four variable maps with the
next state transitions at the current state
P.S.
B
C
0
0
0
0
1
1
a
a
0
1
1
1
1
U
A
0
1
a
a
1
1
1
0
B
1
0
1
0
1
a
a a
a 1
a 1
1 a
1 a
1
1
1
We will not initially be interested in the full
design details but rather, only on the number of product terms and sum terms for
each solution. Figure 4-2(b) shows the
K-map loops for a D flip-flop solution.
Figure 4-2(a) shows the required transitions used to generate the three maps in
Figure 4-2(b). There are 9 loops forthe A
and B variables requiring 9 product terms
and 2 sum terms for driving the A and B
flip-flops. The C flip-flop requires no additionallogic. Note the "SUM"terms are free
on PLHS502 D flip-flops because of the
embedded NANDs.
N.S.
N.S.
A
and input intersections. These transitions
will be useful in reference to Figures 4-2,
4-3 and 4-4 where the design is cast onto
D, S-R and J-K flip-flop solutions.
0
C
U
A
1
0
1
a
a
0
a
1
1
1
1
1
a
1
a
a
B
0
1
1
a
a
1
1
0
1
C
1
0
1
0
1
a
1
a
COUNTER STATE TABLE
(a)
AB
CU
AB
AB
CU
CU
00
01
11
10
00
01
11
10
00
01
11
10
00
0-->1
0-->0
1-->1
1-->0
00
0-->1
1-->0
1-->0
0-->1
00
0-->1
0-->1
0-->1
0-->1
01
0-->0
0-->0
1-->1
1-->1
01
0-->0 1-->1
1-->1
0-->0
01
0-->1
0-->1
0-->1
0-->1
11
O-~O
0-->1
1-->0
1-->1
11
0-->1
1-->0
1-->0
0-->1
11
1-->0
1-->0
1-->0
1-->0
10
0-->0
0-->0
1-->1
1-->1
10
0-->0 1-->1
1-->1
0-->0
10
1-->0
1-->0
1-->0
1-->0
A
TRANSITIONS
B
TRANSITIONS
(b)
Figure 4-1. 3-Blt UfD Counter Definition
August 1989
657
C
TRANSITIONS
Signetics Programmable Logic Devices
PlHSS02 Application Notes
Vol. 1
O~O
D=O
O~l
D=l
1~0
D=O
1~1
D=l
(a)
AB
AB
AB
CU
A
.-----,
C)
0
0
0
'1
0
1
'1
CU
CU
r
'----"
0
c[
0
CD
0
0
1
1
1
~1
1
1
0
0
0
0
0
0
0
0
0
'----'
1
'----'
B
DA
DB
DA takes 5 P-Terms
DB takes 4 P-Terms
DC takes 0 P-Terms
3 Variables, 8 States and 9 P-Terms and 2 S Terms
(b)
Figure 4-2. K-Map Loops Using D-FFs
August 1989
1)
1
658
DC
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
0-70
S: 0
R: X
0-71
1
1-70
1-71
X
0
0
1
0
(a)
AB
AB
AB
cu
cu
cu
C)
0
X
0
C)
0
0
B
0
0
X
X
0
(X
X
0
0
CD
0
X
C)
0
0
0
0
X
X
0
X
X
SA
it
1
1~1
1
1
0
B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1(1
1
1
1
1
SB
AB
SC
AB
CU
AB
CU
0
X
0
C)
X
X
0
0
RA
CU
0
(1
1
0
X
0
0
X
RB
RC
X
0
C)
0
0
(1
1
0
X
X
0
0
X
0
0
X
SA
SA
SB
RB
SC
RC
2P
2P
2P
2P
0
1S
1S
1S
1S
0
....Q
....Q
8P
4S
P
S
= Product Terms
= Sum Terms
(b)
Figure 4--3. K-Map Loops Using 8-R-FFs
August 1989
~
1
659
1~1
~
1)
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
o~o
J:
K:
0~1
1~0
1~1
0
1
X
X
X
X
1
0
(a)
AS
AS
CU
AS
CU
(15
0
0
X
[0_
0
X
X
JA
CU
( 1
X
X
1 )
0
X
X
0
JS
1
1
1
1
1
JC
X)
X
( 1
X
X
1 )
X
X
X
X
0
0
X
X
0
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
AS
AS
CU
(X5
X
0
r0.
X
X
0
0
KA
CU
(X
1
1
X)
X
0
0
X
KS
KA
1
(1
AS
JS
KS
JC
JC
1
0
CU
JA
1
X
eX
X
X
2P
OP
2P
OP
OP
QE
4P
KC
1)
0
(X
1
1
X)
1
1
1
1
0
0
X
0
0
X
1
1
1
1
IS
OS
IS
OS
OS
P = Product Terms
S = Sum Terms
llS
2S
(b)
Figure 4-4. K-Map Loops Using J-K-FFs
Figure 4-3 shows the same design implemented with S-R flip-flops. Figure 4-3 (a) shows
the required S-R transitions and Figure 4-3(b)
maps them onto the corresponding state variable maps. Tallying the loops, we find a total of
8 product terms and 4 sum terms. Again, the
sum terms are free.
Figure 4-4 shows the design again on J-K flip-
August 1989
flops. Figure 4-4(a) shows the transitions and
Figure 4-4(b) the K-map loops. Again tallying
yields 4 product terms and 4 sum terms. The C
variable is realized by J = K = 1 using no product
terms, or sum terms.
From standard logic design we know that 0 flipflops will increase product terms (no don't care
transitions), 8-R flip-flops are less dramatic
660
and J-Ks increase product terms the least (i.e.,
maximum don't cares).
However, the PLHSS02 has no J-K flip-flops.
For simple toggling, the 0 flip-flop requires no
additional circuitry and is the smallest (usually
fastest) implementation. So, Os should always
be assigned for the least significant bit.
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
v
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Q
0
1
0
1
0
1
0
1
QT
JK
00
Q
0
1
0
0
1
1
1
0
01
11
10
o
Q
CLOCK
1--+---.--
o
K
Figure 4-5. J-K Flip-Flop Derived from a D
If required, J-K flip-flops can be constructed
from 0 flip-flops by utilizing the structure
shown in Figure 4-5, as a substitution. The sum
term is taken from the NAND physically connected to the 0 flip-flop and the K input may be
derivable from either an input inverter or a 0
from a flip-flop. Therewill be a penalty for using
this structure from a speed point, but it may
save gates if used judiciously.
each. So, the 3--bit up/down counter will
require:
Flip-flops:
3x6= 18
This example assumes the designer is implementing the counter with the internal hard macro flip-flops. If the design is being generated
from the NAND array only, it should be noted
that the payoff will be interestingly different.
The D flip-flop requires 6 NAN Ds and the J-K
flip-flop will require 10 NANOs. In this version,
the sum terms cost an additional NAND gate
The same design built from J-Ks configured
from NANOs will require:
Flip-flops:
3 x 10 = 30
August 1989
Sum terms
2
Prod. terms
Jt
Total
= 29
Sum terms
3
Prod. terms
A
Total
661
37
gates
gates
The all 0 version looks pretty good at this point
from a total gate count view. Let's take a closer
look at the 0 flip-flop solution:
Figure 4--6 shows the 0 flip-flop solution with
all prime implicants looped and the corresponding transition equations are below. This is implemented in Figure 4-7 using conventional 0
flip-flops in the PLHS502. An alternate solution
would be to substitute the 6 NAND 0 flip-flop
for each O-box in Figure 4-7, but a better (only
25gates!) solution can be achieved by merging
the logic gates on the input of the flip-flops right
into the NAND flip-flop structure as shown in
Figure 4-8. This technique was described in
PLHS501 Applications Notes Volume 2.
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
AB
AB
AB
CU
.....--..
rABCU
(0
a
a
a
1
1
-'
c[
a
a
Jl:BCtf
CU
A
\D
a
1
'-----'
B
A
.....--..
'1'
]
U
1
c[
1
'-ACO
BCD
f,\
1
1
1~1
1
1
0
a
a
a
a
a
a
a
a
1(1
ABu
'-------'
B
DA
DA
DB
DC
CU
ABC"
a
'---'
Va
A
DC
DB
Jl:BCU + ABCU + ABC" + ABU + ACO
BC"U + BC"U + BCU + BCD
C"
Flgure~.
0 Flip-f'lop Equations for 3-Bit Counter
CLOCK-------------4~--------------------------~~----------------,
SETN----_+--~~----------------------_+--~~------------t___.
B
A
A
B
C
A
B
U
A
C
lJ
RESaN----~----------------------------~----------------~
TOTAL COST = 3 D-FFS
+ 9 GATES
Figure 4-7. 3-8it Solution using PLHSSa2 0 Flip-Flops
August 1989
662
c
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
SETN:>-t----------.------------------.---------,-------------t--------------,
NC
~~J
Figure 4--a. 3-Bit Solution With Merged NAND Flip-Flop
August 1989
663
Signetics Programmable Logic Devices
PlHS502 Application Notes
Vol. 1
A couple of final notes on counter design. The
basic structure for a simple up counteris shown
in Figure 4-9. This one uses a D flip-flop least
significant bit and a generic format for high
order bits, as shown. Note that only 2 product
terms per bit are needed.
Down counters can be treated similarly. Fairly
general sequence generators can be configured from counters by simply adding a
combinational decoder, as needed. One final
counter example is shown in Figure 4-10
wherein a 10-bit counter is defined using the
SNAP Boolean equation formal. Note that the
logic equations follow the format described in
ALL LOWER
QOUTPUTS
5
Q
ALL LOWER
Q OUTPUTS
R
Q
QOUTPUTS
LOWER THAN
THIS CElL
S
Q
R
Q
Figure 4-9. All resets are shared as well as all
clocks. This design would require eight hard
macro S-R flip-flops, one hard macro D flipflop and one additional S-R flip-flop which
SNAP would automatically configure from a
hard macro D flip-flop.
MosT
SIGNIACANT
BIT
CLOCK
INTERMEDIATE
BIT
CLOCK
QOUTPUTS
LOWER THAN
THIS CELL
LEAST
SIGNIFICANT
Q
CLOCK
0
NOTE: Asynchronous reset is nol shown.
Figure 4-9. Up Counter Structure
August 1989
664
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
@PINLIST
CLOCK I; RESET I;
A
E
0;
0;
0;
B
F
L
0;
0;
0;
C
G
0;
D
O·
O·
H
0;
@LOGIC EQUATIONS
A.D
B.S
B.R
/A;
/B*A;
B*A;
C.S
C.R
D.S
D.R
E.S
E.R
F.S
F.R
G.S
G.R
H.S
H.R
1.S
T.R
L.S
L.R
A.RST
B .RST
/C*A*B;
C*A*B;
/D*A*B*C;
D*A*B*C;
/E*A*B*C*D;
E*A*B*C*D;
/F*A*B*C*D*E;
F*A*B*C*D*E;
/G*A*B*C*D*E*F;
G*A*B*C*D*E*F;
/H*A*B*C*D*E*F*G;
H*A*B*C*D*E*F*G;
/I*A*B*C*D*E*F*G*H;
I*A*B*C*D*E*F*G*H;
/L*A*B*C*D*E*F*G*H*I;
L*A*B*C*D*E*F*G*H*I;
/RESET;
/RESET;
/RESET;
/RESET;
/RESET;
/RESET;
/RESET;
/RESET;
/RESET;
/RESET;
CLOCK;
CLOCK;
CLOCK;
CLOCK;
CLOCK;
CLOCK;
CLOCK;
CLOCK
CLOCK
CLOCK
~
~
C.RST~
D.RST~
E. RST
F.RST
~
~
G.RST~
H.RST~
LRST
~
L.RST~
A.CLK~
B. CLK
C.CLK
D. CLK
E. CLK
F. CLK
G. CLK
H. CLK
I. CLK
L. CLK
~
~
~
~
~
~
~
~
~
Figure 4-10. 10--Bit Up Counter -
August 1989
665
SNAP Style
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
a
Shifter Design Notes
By recognizing the availability of the output,
if it is used instead, the design procedure
remains "nose to tail" substituting 0" for Q into
the NAND (using only one input). Should a fancier shifter be required (see the Synchronous
ReceiverlTransmitter design at the end), the
designer may choose to even implement soft
macro "merged" shifter flip-flops.
Efficient shifter design is critical to achieve the
fastest, most economical PLHS502 sequence
recognizers. For ideal shifters, no additional
gates should be required if the designer correctly exploits the hard macro flip-flops for the
part. Normally, one views a shifter as an input
to D, Q to D, Q to D, etc., like circus elephants
walking nose to tail. But, the PLHS502 D flipflop has an embedded NAND gate which, for
this type afdesign, appears to "getin the way"
The maximum internal "all shifter" capacity of
the PLHS502is 26 bits, assuming conventional
structure flip-·flops. If one were to design a
schematic with 26 D flip-flop cells in cascade,
SNAP would configure the first 8 from the hard
macro Ds, the next 8 from the hard macro S-Rs
and the last 10 from the NAN D array.
An example illustrating a non schematic captured 3-bit shifter follows. Figure 4-11 illustratesits' state diagram, Figure4-12 shows the
state equation solution and Figure 4-13 shows
the very compact Boolean equation solution.
o
RESEl:...
o
o
o
Figure 4-11. 3-Bit Shift Register Slate Diagram
August 1989
666
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
@PINLIST
QA
0;
RESET I;
0;
OB
DATA
I;
OC 0;
@INPUT VECTORS
Il
DATA;
10
/DATA;
@OUTPUT VECTORS
@STATE VECTORS
lOA, OB, OC] ;
so
000
B;
51
001
B;
52
010
B;
53
011 B;
54
100 B;
55
101 B;
56
110 B;
57
111 B;
@TRAN5ITION5
WHILE [ ]
IF RE5ET THEN [50]
WHILE [50]
IF
Il
THEN [54]
IF
10
THEN [50]
WHILE
[51]
IF
Il
THEN [55]
IF
10
THEN [50]
WHILE [52]
IF
11
THEN [55]
IF
10
THEN [51]
WHILE [53]
IF
Il
THEN [55]
IF
10
THEN [51]
WHILE [54]
IF
11
THEN [56]
IF
10
THEN [52]
WHILE [55]
IF
11
THEN [56]
IF
10
THEN [52]
WHILE [56]
IF
11
THEN [57]
IF
10
THEN [53]
WHILE [57]
IF
Il
THEN [57]
IF
10
THEN [53]
CLOCKIi
@PINLI5T
CLOCKI;
DATA
I;
RE5ET I;
OA
0;
OB
0;
QC
0;
@LOGIC EQUATION5
OA.D = DATA;
QB.D
QA;
QB;
OC.D
QA.R5T
RESET;
QB.RST
RESET;
QC.RST
RESET;
QA.CLK
CLOCK;
QB/CLK
CLOCK;
QC.CLK
CLOCK;
Figure 4-13. 3-8lt ShlfterBoolean Solution
Figure 4-12. 3-Bit ShlfterState Equations
August 1989
667
Signefics
PLHS502
Application Notes
Vol. 1
Programmable Logic Devices
ADDITIONAL DESIGN
GUIDELINES
The following guideline summary is by
no means complete. Rather, it is a list
of straightforward substitutions which the
designer can make to help guarantee that
the design fits. The basic approach is to
build the design using the basic building
blocks of the architecture. For the
PLHSS02 this means using NAND gates,
D flip-flops and S-R flip-flops. To make
this clear, we will enumerate and illustrate
good basic design substitutions.
1. Use NAND gates whenever possible.
2. Use S-R flip-flops for counters over 4
bits long.
3. Use D flip-flops (if possible) for the
August 1989
least significant counter b~.
4. If possible eliminate NOR functions by
converting to AND w~h complemented
input (use 0 on flip-flops and available
input complements).
leaves the device. So, assign complemented, buffered outputs accordingly. Exclusiv&-OR/parity controlled
outputs are slower, so assign them accordingly.
S. AND gates which feed NAND gates
can be replaced by wider NAND gates
(exploit NAND width).
9. Build toggle chains out of D flip-flops,
then S-R flip-flops, to conserve NAND
gates.
6. Eliminate all extra inversions by exploiting input complements and flipflop IQ outputs.
10.The NAND-feeding D-FF structure
may be thought of as an AND-feeding
D-FF with Q and 0 reversed.
7. If you exceed your flip-flop budget of
hard flip-flops, put the most complex
flip-flop configurations into soft macros (see Section 6). Fold the gating
function into the flip-flop.
11. For very large counters, converting DFFs to J-K FFs may be appropriate. H
necessary, then do so.
8. Careful output pin assignment can result in a free logic function as the signal
668
12.Efficient methods for implementing
Exciusive-ORfunctions are described
in PLHSSOI Applications Notes Volume2.
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
,..
(b)
(a)
1.
=D--~
GET AT OUTPUT
PIN
GET FROM PIN INPUTS
OR FF-Oo
(c)
PIN INPUTS
ORO.
4.
3.
OUTPUT PIN OR
NEXT NAND
See 1(c)
5.
6.
(b)
(a)
~[Jr
10.
11.
{]=
o
CLOCK
K
II
-
Figure 5-1.
August 1989
PLHS502 Guidelines
669
Signetics
PLHS502
Application Notes
Vol. 1
Programmable Logic Devices
ADDITIONAL PLHS502
APPLICATIONS
These examples illustrate various applications the PLHS502 is capable of, which
are quite interesting.
Byte Data Pipe
A common system building block is the
byte data pipe illustrated in Figure 6-1.
This elementary structure illustrates a parallel cascade of octal registers where
each tier is independently clocked. Data
arrives at the input pins and is clocked in
by clock A. After settling, this is clocked
into the second tier by clock B, the thirdtier
by clock e and the output tier by clock D.
August 1989
The two center registers are generated
from NAND gate transparent latches comprised of three gates. This classic threegate latch has a static hazard in the ones,
but careful timing and masking the input
and output logical image to the outside
world, with edge triggered registers, essentially eliminates this evidence. This
consumes 48 olthe 64 gates budget in the
PLHS502. The remaining gates may now
be used as needed to configure this data
path for a more specific applications such
as:
a. A distributed decoder as in a RiSe
pipeline. Each remaining gates can de-
670
tect 32-bit internal state combinations
(expanded to 40 bits if simu~aneous
examination of the input pins is desired).
b. A 4-byte queue for interprocessor and
processor to bus communications and
synchronization.
c. A 3-, 4-, or 5-byte sequence detector
for byte oriented protocols.
Clearly, one of the internal register tiers could
be freed up or the arrangement altered to have
a three pOSition data pipe and a group of S-R
registers to implement a bus handshaker or internal counters for a queue pointer, etc.
Signelics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
CLOCK 0
CLOCKC
CLOCKB
CLOCK A
011
001
002
012
003
013
004
014
005
Dl5
006
016
007
Dl7
008
Dl8
EDGE TRIGGERED
_FUP-FLOPS
TRANSPARENT LATCHES
Figure 6-1. A Byte Data Pipe
August 1989
671
EDGE TRIGGERED
DFUP~LOPS
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
Custom CAMS
Another common block used in memory and
I/O systems today is the content addressable
memory (CAM), illustrated in Figure 6~2.
These are used for associative searching and
often implement the TAG structure orVALID bit
structure for the translation lookaside buffer in
a cache system. CAMs more closely resemble
a small register array where each cell has an independentdala compare operation with a global polling mechanism. This example illustrates
the PLHS502's ability to realize a small, relatively fast 4X4 CAM. In this example, the 16
register cells are made with the D flip-flop and
the S-R flip-flops configured as Ds. Each flip~
flop output i s compared to a corresponding data
input with a coincidence function which is
generated from three NANDs. Groups of four
comparators are then ANDed together to generate the HIT signals indicating the presence of
a 4--bit item. If speed and gate economy are
required, the composite compare tunction can
be generated, exploiting wide gates rather than
deep cascades.
The CAM operation is simple. The CAM must
first be loaded, with four bits in each tier. Loading was chosen to be 4~bit parallel with independenlclocking. This allows "one transaction"
replacement and is the most flexible approach
for implementing arbitrary updating policies.
Once it is loaded, the 4-bit data is applied on
the same lines (this could easily be changed to
four different lines). When a value is applied, a
"H IT" is generated if the current value matches
one of the stored 4-bit items. How the "HIT" is
used by the outside system is system dependent. If a value is applied and there is no "H IT,"
there is no response. Again, there are a number
of remaining internal NAND gates as well as
most of the gates tied to the I/O pins to perform
additional tasks and adapt the behavior of this
building block.
This is a very efficient structure to implement a
direct mapped cache, where four l-megaword
regions could create the logical image of a
16--megaword region. The time from valid
address to valid "HIT" is about 20 nanoseconds
-max.
HIT A
CLOCK A
HITS
CLOCKB
HlTC
ClOCKC
HIT 0
CLOCK 0
DATA 4
DATA 3
DATA 2
Figure 6--2. 4X4 CAM
August 1989
672
DATAl
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
System Scoreboard
High digital system throughput may be
achieved by allowing high-speed processors
to run independen~y at their own rate. Hence,
operation speed is only limited when data or
function dependencies occur. This requires a
special sort of synchronization mechanism to
allow independent processes to realign when
necessary. A classic solution to this is the
Scoreboard concept, illustrated in Figure 6-3.
In essence, this is an overall system register
with independent status bits assigned to specific functional units and data registers. The idea
is an old one, but has recently resurfaced since
modern Rise designers have begun resurrecting highly parallel else architectured artifacts.
version 1) and leaves 5 bi---~t-:;,-L----,
CLOCK
D
RESETn
DATA
• -
c:=>---tt!-t
c:=>----L.:.r
b-
MULTIPLEXED 0
ON
A 6 NAND GATE IJ.-FF
a
a
ON
ON
LOAD/SHIFT
PIN
--I'>r---++--I
-----T3
T2
d _ MULTIPLEXED O-FF WITH
AND/OR MERGED INTO FF DESIGN
c - ALL GATE MULTIPLEXED IJ.-FF
Figure 6--6. Custom Flip-Flop Metamorphosis
August 1989
676
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
~
.---2
CLOCK
3
NA3
1
U2
1
U5
SRFF
2
";;;V
1 ~6
4
I-~
3
U11
4
1
2
2
3
o;;.v
NA3
o
S
51
01
CP
C
L
A
A
ON
~
o
51
14
CLA
S=o
1
U12
SRFF
3
1,.!;,"
2
";;;V
NA2
U4
3
l~B
2J
1
2
2
3
";';.v
NA2
S
02
CP
C
L
A
A
-6
ON
J4
U13
1
U9
SRFF
2
";;;V
~102
I
1
S
2
3
CP
C
A
5
0
L
A
ON
";"NV
14
l
Figure 6-7. 3-Bit Counter Schematic
U1
Figure 6--a. Final Merged D Flip-Flop Schematic
AugUSII989
677
03
»
c:
2-
<0
:J
CD
c:
!!i
~.
:g
"U
<0
c8
~
3
gj.
C5"
b
<0
(I"
U1
~
LODSHF~
IN
g"
~
1
CLOCK
U2
2
CLOCK
a
RESET
RESET
I-- r--
QPREV
~
CLOCK
I
PDIN2
~
LFLOPCELL
a
RESET
~
DATIN
LOAD
ON
SHIFT
QPREV
PDIN1
'"
~FLOPCELL
FLOPCELl
NIN
I-- I--
DATIN
LOAD
ON
SHIFT
QPREV
'--
CLOCK
RESET
a
-
RESET
DATIN
I-'--
LOAD
SHIFT
QPREV
_
l!:FLOPCELL
CLOCK 0<_
DATIN
-
ON
LOAD
SHIFT
QPREV
ON
~
'"
"'C
"'C
o·
a
ci"
:::J
~~
Figure 6-9" Transmitter Schematic
:-(i)
.... en
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
!..
PDOUT1
PDOUT2
PDOUT3
SDOUTR
PDQUT4
CLOCKR
RESETR
PDOUTB
Figure 6-10. Receiver Schematic
Augusl1989
679
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
Simulation Control File for Flopcell
Strategy
1. Reset issued initially
Define a repetitive clock @ 10MHz
2.
3.
Load a logical one
4.
Switch mode to shift, and shift in a logical zero
5.
Load a logical zero
6. Switch mode to shift, and shift in a logical one
7.
Issue another reset
S 1(20,40,450,470)reset
S 0(50,100,etc.)clock
S 0(45, 70,245,270)lod shf
S O(45,90)datin
S O(345,370)q prey
P reset,clock,lod shift,datin,q prev,q
SU Time~500
-F
_, J ____ '- ___ 1 ___ J ____ I- ___ 1 ____ 1 ___ L ___ -L ___ -L ___ L ___
~
___ L __
RESET
CLOCK
LOOSHF
DATIN
QPREV
~~
______
~n~
_____________
~~----------------------
________________________
~IlL
________
Q
-' 1 - - - T - - - r - - - 1 - - - T - - - r - - - - r - - - 1 - - - TIME
o
~
~
~
§
*
~
~
r - - - T - - -r ---1- - - - - ~
Figure 6-11. SNAP Simulation of the Merged Fllp-f'lop
August 1989
680
~
~
~
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
DELAV.",0n8
RESETR
H
MARKER
= One
SEC/DlV=lOQna
LJ
ClKR
n
SDiN
RESETT
H
n
n
n
IJ
ClKT
n
-----.fl
lODSHF
PDlN1
PDlN2
PDINS
l
PDlN6
l
100
300
500
700
900
1100
F1: HELP, F9: MENU, FlO: EXIT
DELAY
POIN3
H
PDIN4
H
PDIN7
H
POINe
H
= Ona
MARKER = One
SECfDIV=l00na
U
--.J
--.J
QPREV
ClR
SDOUT
U
PDOUT1
U
PDOUT2
U
PDOUT3
100
300
700
500
Figure 6-12. RECTRAN.SCL Waveforms
August 1989
681
900
1100
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
DELAY. One
RESETT
H
MARKER
= One
SEC/DN=100M
11
CLKT
---.n______________________________________
LODSHF
~n~
______
POIN.
PDIN2
PDIN3
H
PDIN4
H
PDINS
PDIN6
PDIN7
H
.00
300
500
700
900
1100
Fl: HELP, F9: MENU, FlO: EXIT
DELAY
=Ons
MARKER
=Ona
SECtDIV=l00ns.
PDINS
SDOUT
UUJ
Ul
SDIN
RESETR
u
J
QPREV
H
---1l~__~r-l~__~r_l~__~r_lL________________
lJ
ClKR
PDOUTl
PDOUT2
UU
Ul
PDOUT3
UU
Ul
PDOUT4
UU
Ul
100
300
700
500
Figure 6-13. Partial RECTRAN.RES File
August 1989
682
900
1100
Signelics Programmable Logic Devices
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
DELAY
PDOUT6
U
= Dna
MARKER
= Ono
r--LJI
UU
UL
PDOUT7
U
SEC/DlY=l00na
~
UU
UL
UU
PDOUT8
1\
UL
Q1
U
02
U
Q3
U
Q4
U
Q5
U
06
U
'OCHK
U
r
L
U
U
UU
UL
100
300
700
500
Figure 6-15. Final RECTRAN.RES File
S
1(20,40,1000)RESETR
0(50,100,ETC)CLKR
0(100,150,300,350,500,550,700,750)SDIN
S
1 (20, 40,1000) resetT
S
0(50,100,etc)clkT
S
0(45,70,1025,1050)lodshf
S
0(1000)pdin1,pdin2,pdin5,pdin6
S
1(100)pdin3,pdin4,pdin7,pdin8
S
0(20)CLR
* S 1(2000)VCC
p resetT,clKT,lodshf,pdinl,pdin2,pdin3,pdin4,pfin5,pdin6
# ,pdin7,pdin8,qprev,sdout,SDIN,RESETR,CLKR,PDOUT1,
# PDOUT2,PDOUT3,PDOUT4,PDOUT5,PDOUT6,PDOUT7,PDOUT8,
# Q1,Q2,Q3,Q4,Q5,Q6
PCO
sutime=2000
f
Figure 6-16. RECTRAN.sCL Text
August 1989
684
900
1100
F1, HELP, F9, MENU, flO, EXIT
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
* Date:
Output of Netgene
5/ 3/1989
Version 1.0
Time:
18:36:25
*~***********************************************************
* Input File Name
RECTRAN.EDF
* Netlist File
RECTRAN. MAC
*************************************************************
MACRO
RECTRAN SCH I (CLKR, CLKT, CLR, LODSHF, PDINl, PDIN2, PDIN3, PDIN4,
PDIN 5, PDIN6, PO IN7, PD IN8, QPREV, RESE TR, RESETT, SDIN) 0 (PDOUTl,
PDOUT2,PDOUT3,PDOUT4,PDOUT5,POOUT6,PDOUT7,PDOUT8,Ql,Q2,
Q3,Q4,Q5,Q6,SDOUT)
CELL_ REC _ 0 _ 0 REC I (CLKR, RESETR, SDIN) 0 (POOUTl, PDOUT2, POOUT3,
# PDOUT4,PDOUT5,PDOUT6,PDOUT7,PDOUT8)
BLKOI TRANS I(CLKT,LODSHF,PDINl,PDIN2,PDIN3,PDIN4,PDIN5,
# PDIN6,PDIN7,PDIN8,QPREV,RESETT) O(SDOUT)
BLK02 COUNTER3 I (CLKR,CLR) 0(Ql,Q2,Q3)
BLK03 COUTNER3 I (CLKT,CLR) 0(Q4,Q5,Q6)
MEND
Figure 6-17. High-Level RECTRAN Macro File
***********************************************
Output of Netgene
Version 1.0
5/ 2/1989
Time: 13:35:45 *
***********************************************
* Input File Name
REC.EDF
* Netlist File
REC.MAC
***********************************************
* Date:
MACRO
REC_SCH I (CLOCKR,RESETR,SDOUTR) O(PDOUTl,PDOUT2,PDOUT3,
PDOUT4,PDOUT5,PDOUT6,PDOUT7,PDOUT8)
Ul
U2
U3
U4
U5
U6
U7
U8
DFFR
DFFR
DFFR
DFFR
DFFR
DFFR
DFFR
DFFR
I (SDOUTR,CLOCKR,RESETR)
I (PDOUTl,CLOCKR,RESETR)
I (PDOUT2,CLOCKR,RESETR)
I (PDOUT3,CLOCKR,RESETR)
I (PDOUT7,CLOCKR,RESETR)
I (PDOUT6,CLOCKR,RESETR)
I (PDOUT5,CLOCKR,RESETR)
I (PDOUT4,CLOCKR,RESETR)
o (PDOUTl, DMOl)
O(PDOUT2,DM02)
o (PDOUT3, DM03)
o (PDOUT4, DM04)
o (PDOUT8, DM05)
o (PDOUT7, DM06)
o (PDOUT6, DM07)
o (PDOUT5, DM08)
MEND
Figure 6-18. Receiver Macro File
August 1989
685
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
***********************************************
*
*
Date:
Output of Netgene
1/ 5/1989
version 1.0
Time:
13:37:13
*
*
***********************************************
*
*
*
*
*
*
*
************************************************
*
Input File Name
Netlist File
TRANS.EDF
TRANS.MAC
MACRO
*
Z TRANS_SCH I (CLOCK, LODSHF,PDIN1,PDIN2,PDIN3,PDIN4,PDIN5,
# PDIN6,PDIN7,PDIN8,QPREV,RESET) o (SDOUT)
*
U1 IN I (LODSHF) O(SN01)
U2 NIN I(LODSHF) O(SN09)
BLK01 FLOPCELL I(CLOCK,PDIN1,SN01,QPREV,RESET,SN09)
# DM01)
BLK02 FLOPCELL I(CLOCK,PDIN2,SN01,SN02,RESET,SN09)
# DM02)
BLK03 FLOPCELL I (CLOCK,PDIN3,SN01,SN03,RESET,SN09)
# DM03)
BLK04 FLOPCELL I(CLOCK,PDIN4,SN01,SN04,RESET,SN09)
# DM04)
BLK05 FLOPCELL I(CLOCK,PDIN8,SN01,SN08,RESET,SN09)
# DM05)
BLK06 FLOPCELL I (CLOCK,PDIN7,SNOl,SN07,RESET,SN09)
# DM06)
BLK07 FLOPCELL I(CLOCK,PDIN6,SN01,SN06,RESET,SN09)
# DM07)
BLK08 FLOPCELL I (CLOCK,PDIN5,SN01,SN05,RESET,SN09)
# DM08)
O(SN02,
O(SN03,
O(SN04,
O(SN05,
o (SDOUT,
O(SN08,
O(SN07,
O(SN06,
*
MEND
*
Figure 6-19. Transmitter Macro File
August 1989
686
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
************************AAAl*******************
*
Version 1.0
Output of Netgene
*
Time:
13:34:36 *
Date:
1/ 5/1989
***********************************************
*
*
*
*
*
*
*
*************************************************
Input File Name
Net1ist File
FLOPCELL.EDF
FLOPCELL.MAC
*
MACRO
*
Z FLOPCELL SCH I (CLOCK,DATIN,LOAD,QPREV,RESET,SHIFT) O(Q,
# QN)
*
U1
U2
U3
U4
US
U6
U7
NA3
NA3
NA4
NA4
NA4
NA2
NA3
I(SN05,SN01,SN03) O(SN02)
I (SN02,RESET,CLOCK) O(SN03)
I(SN03,CLOCK,SNOS,SN01) o (SN04)
I (RESET,SN04,LOAD,DATIN) O(SNOS)
I (RESET,SN04,SHIFT,QPREV) O(SN01)
I(SN03,QN) O(Q)
I (Q,RESET, SN04) O(QN)
*
MEND
*
Figure 6-20. Flopcell Macro File
August 1989
687
Signetics Programmable Logic Devices
PlHS502 Application Notes
Vol. 1
***********************************************
Output of Netgene
version 1.0
*
* Date: 1/ 5/1989
Time:
13:42:14 *
***********************************************
*
** Input File Name
* Netlist File
*
COUNTER3.EDF
COUNTER3.MAC
*
*
*************************************************
*
MACRO
*
Z COUNTER3 SCH I (CLOCK,CLR) O(Q1,Q2,Q3)
*
U1 NA3 I(SN03,Q2,Q3) O(SN01)
U2 NA3 I(Q1,Q2,Q3) o (SN04)
u3 NA2 I(SN09,Q3) O(SN06)
U4 NA2 I(Q2,Q3) O(SN1O)
U5 INV I(SN01) O(SN02)
U6 INV I (SN04) o (SN05)
U7 INV I (SN06) O(SN07)
U8 INV I(SN1O) O(SN08)
u9 INV I (Q3) O(SNll)
U10 INV I(SN12) o (SN13)
U11 SRFF I (SN02,SN05,CLOCK,CLR) O(Q1,SN03)
U12 SRFF I(SN07,SN08,CLOCK,CLR) O(Q2,SN09)
U13 SRFF I (SNl1,SN13,CLOCK,CLR) O(Q3,SN12)
*
MEND
*
Figure 6-21. 3-Bit Counter Macro File
August 1989
688
Signetics
PLHS502
Application Notes
Vol. 1
Programmable Logic Devices
ADVANCED FLIP-FLOP MERGING
Folding logic functions directly into the
workings of a flip-flop has a unique payoff with PML. (As illustrated in Sections 4
and 6). Since the basic approach may be
extended to other flip-flop structures, this
technique may be used more "generally".
The figures provided in this section illustrate examples of simple and complicated
structures.
Consider the D-Iatch in Figure 7-1:
OATA--..r"_
ENABL.-,-""I..._
Figure 7-1_ D-Latch
Hthe data input point is driven from a twolevel logic function as shown in Figure
7-2(a), the gate count is six with one inverter. The input signals pass through two
logic layers before entering the latch, then
throug h two more to reach the Q output.
From Figure 7-2(a), note that the data input to gate G4 is driven High from the G3
output when either G1 Dr G2 (or both) is
driven Low. Also, note that when Data is
High, and Enable is High, the output of G4
will be Low. Under these conditions, the
outputs of G1 or G2 are driven in a direction similar to the output of G3 and G4. By
eliminating G3 and G4 and substituting
G1 and G2 where G4 was, some gate and
speed saving is gained as shown in Figure 7-2(b). Note that the Enable signal
has to be reinserted carefully. This permits
a faster, cheaper, and more efficient
merged latch. This is the simplest structure and the reader is encouraged to prove
w
the operation by simulation or construction. The general approach is a simple
expansion of these steps.
1. Isolate the positive asserted flip-flop
input.
2. Isolate the two--level ANDIOR driving
function.
3. Eliminate the NAND gate in step 1
but preserve inputs and outputs.
4. Eliminate the second-level NAND
from step 2, but preserve inputs in
the step 2 ANDIOR structure.
5. Place the corresponding intermediate
outputs to replace the eliminated flipflop input gates output.
6. Place any inputs which fed the flipflop input gate onto the new input
points from step 5 (Le., the input
points of the step 2 ANDIOR structure).
W_--Ir--...
x
x
Y_--Ir--...
Y
z
a
Z
ENABLE
(a)
(b)
Figure 7-2. D-Latch with Driving Logic
August 1989
689
Signetics Programmable Logic Devices
PLHS502 Application Notes
Vol. 1
Let's illustrate the procedure by applying it to a
more complicated flip-flop -the dreaded J-KI
Figure 7-'3 depicts a J-K with a two-levellogic
function tied to J and a different function tied
to K. J gets the sum of three product terms and
K gets the sum of two.
s
6(0)
CLK
K
A
Figure 7-3. J-K with Gating
Because the inputs to gates A, B, C, D, E will
be maintained, we don't care what they are.
From the recipe:
Step 1.
Isolate the positive asserted flip-flop
input.
For J this is gate G2.
For K this is gate G3.
Step 2.
Isolate the two-level ANDIOR driving function.
(see function 1 and 2)
Step 3.
Eliminate the NAND inputs in step 1
but preserve inputs and outputs.
(Figure 7--4(a))
Step 4.
Eliminate the second-level NAND
from step 2.
(Figure 7--4(a))
FUNCTION 1
STEP 3
s~~~========~~
6(0)
CLI<
K
FUNCTION 2
Figure 7-4(a). A Merged J-K Flip-Flop
It is hoped that the reader can, in general, avoid
the use of the J - K structures built from gates
as shown due to their inefficiency of gate
usage. There is also a potential timing liability
August 1989
in thatthe clock path G lto GA is faster than the
data input paths and creates a possible race.
However, this example serves to illustrate that
690
a merging process can be applied systematically, with success, to even relatively complicated structures.
Signefics
Programmable Logic Design
and
Application Notes
Programmable Logic Devices
Today's engineer is constantly striving to
consolidate higher complexity and more
feature-intensive circuits into designs
without sacrificing flexibility. In a competitive marketplace, designs need to be
brought to market quickly. The Signetics
solution is to provide high-performance
Programmable Logic Devices (PLDs) that
can be quickly and easily integrated into
system designs.
In using this manual, some familiarity with
PLDs is helpful. In addition, we recommend the recently published text books,
Programmable Logic Devices, by Geoff
Bostock (McGraw-Hili, copyright 1988),
and Programmable Designer's Guide by
Roger Alford (Howard W. Sams & Co.,
copyright 1989).
This document provides complete,
straightforward application examples.
The first three sections describe Signetics
PLDs. Sections fourthrough eight provide
application examples. Most applications
are accompanied by one or two pages of
text. Some also include a circuit or block
diagram and an AMAZE design file listing
to implement that application. To save
time, the files are available on diskette or
by accessing the Signetics toll-free bulletin board: (800) 451-6644.
AMAZE SOFTWARE
Design, simulation and device-programming support for all Signetics PLD families
is provided by Signetics AMAZE PLD
design software. AMAZE, which supports
many of Signetics programmable products, includes Boolean logic and direct
state-equation entry. Functional and AC
timing simulation models and an automatic test vector generator are included in
the AMAZE PLD design package. The
software runs with MS-DOS 2.0 or newer
operating systems and is available free of
charge to qualified users. Schematic capture capability is available in conjunction
with Data I/O's FutureNet Dash System
and the OrCad Systems Corporation
OrCAD/SDT"" schematic capture software packages.
The Signetics families of PLDs are also
supported by Data I/O®'s design software
package, ABELTM, and the P-CAD and
CUPL'" design software.
Automatic Map and Zap Equation Entry
(AMAZE) software designed by Signetics
will interface with most commercial programmers.
AMAZE consists of five modules:
• BLAST (Boolean Logic and State
Transfer entry program)
• PTE (Program Table Editor)
• PTP (PAL to PLD conversion program)
ACKNOWLEDGEMENTS
In appreciation for their contributions:
Dimitrious Douros
Mike Gershowitz
Ali Gheissari
Jim Green
Neil Kellet
Jerry Liebler
Bob Lundeberg
John McNalley
Tony Parisi
August 1989
• DPI (Device Programmer Interface
program)
• PLD SIM (PLD Simulator program)
The software modules allow expansion
for future requirements. They are user
friendly with both HELP and ERROR messages. Simulator programs provide applications assistance and automatic test
vector generation.
Equipment requirements, products supported and details of product modules are
contained in the AMAZE design software
manual.
691
AMAZE is available at no charge by
request to the Signetics factory.
Additional design support is usually available with the commercially available packages ABEL, CUPL PLDesigner, LOG/iC,
etc. Programming support is always
available through DATA I/O, STAG Microsystems, and several other programmers.
PRODUCT SECTION
INTRODUCTION
Signetics manufactures a wide range of
PLDs and Programmable Logic Sequencers. In the area of PLDs, there are two
basic architectures: Programmable Logic
Arrays (PLAs) and Programmable Array
Logic (PAL ®).
The PLA architecture consists of two
interconnectable arrays with programmable connections between the input pins
and a group of AND gates. Another programmable array exists between the AND
gate outputs and the inputs to a group of
OR--gates. Complete freedom of interconnection is possible with this arrangement.
PAL-type deVices, on the other hand,
provide programmable interconnection
between the input pins and the AN D
gates, but the outputs of the AND gates
are tied to specific OR gates, then finally
routed to output pins. By eliminating the
programmability between the AND-OR
area, some speed savings are achieved at
the expense of interconnect freedom.
Signetics Programmable Logic Sequencers combine the versatility of the PLA with
flip-flops to achieve powerful state machines in a variety of user configurations.
This section is designed to familiarize
design engineers with the Signetics lines
of PLAs, PALs, and Sequencers available,
and acquaint them with their general capabilities and features. Each architecture
is briefly showcased in an initial rendering
with a short capsule description of the
part. The serious reader should consult
the data sheet sections of this PLD Data
Handbook for full electrical details on any
part.
SigneHcs
Programmable Logic Design
and
Application Notes
Programmable Logic Devices
PLADEVICES
Signetics PLAs are particularly useful in
the design of wide address decoders and
random logic replacement. The primary
advantage Signetics brings to these applications with their PLA devices is product
term sharing, which is made possible via
the two programmable arrays. The familiar PAL architecture supports a programmable AND array, followed by a fixed OR
array. Better than 90% of the PAL devices
that are available today are limited to 7
input wide gates. When pursuing a solution to a complex address decoding
scheme, this restriction is prohibitive. The
Signetics PLAdevices support 100% of all
product terms. Once a term is created, it
can be shared with any or all of the output
functions. No duplication of resources is
incurred. The popular PLXX153 family
support 32-input wide OR gates which
are ideal for memory 110 decoders. The
addition of programmable output polarity
also enhances design efficiency and logic
minimization.
The 2 programmable array concept dominates the Signetics PLD product line. With
the exception of the PAL-type devices
which have been geared for ulitmate performance, all Signetics PLDs have been
architected with efficient and flexible PLA
structures. With the largest breadth programmable product line in the industry,
Signetics believes the designer can truly
fill his requirements from the several product lines-PLA, PAL, and PLS. PLA
device descriptions follow.
Signetics PLUS153D
Figure 1-1 depicts the Signetics
PLUS153D. This bipolar PLA is pin and
functionally equivalent to all other
August 1989
Signetics 153 1ype PLAs (i.e., the
PLS153, PLC153, PLHS153), but requires no more than 12 nanoseconds to
generate a stable output.
The PLUS153D has eight dedicated
inputs and 10 bidirectional pins. The bidirectional pins may be adapted to suit the
user's specific needs. 2Q-pin DIP or
PLCC packages are available.
The output structure of the PLUS153D
includes programmable polarity control on
each output. Either active HIGH (noninverting) or active LOW (inverting) outputs are configurable via the EX-OR gate
associated with each 110. Individual
3-State control of the 110 is also supported
with the ten direction control AND terms
(D1-D9).
Other benefits to the PLUSl53D include
full pin compatibili1y with most 2Q-pin
combinational PAL® parts. The natural
product term sharing capabilities of the
PLA architecture yield complete freedom
of configuration should the engineer implement a particularly creative decode
configuration.
Signetics PLUS173D
Figure 1-2 depicts the Signetics
PLUS173D. This bipolar PLA is functionally equivalent to the Signetics PLS173.
The 24-pin PLUS173 has four more input
pins than the PLUS153. The user may
adapt the bidirectional pins to suit particular decoding needs, but the propagation
delay time is still no more than 12 nanoseconds from stabilized input to stable
output.
By having more inputs than the 153 part,
the 173 can either resolve more input lines
692
orgenerate more outputs functions for the
same number of inputs. Distinct 3-State
control over each output may be useful for
controlling chip enables where contention
(i.e., multiple access) may exist.
For speed and input width, the PLUS 173D
is probably the best single PLA available
today for both memory and I/O decoding.
Combining the 12 nanosecond tpo with the
distinguishable range of 12 to 21 inputs,
the designer can easily decode say 16
input addresses as well as readlwrite
qualifiers or encoded status signals. Output polarity control (active-High or activeLow) is achieved by programming the
Exclusive-OR gate associated with each
output.
The flexibili1y achieved with a PLA structure can be quickly appreciated by the
designer who has experienced the frustration of the dedicated "OR" structures in
PAL ICs. Currently, the only time penalty
for the freedom granted by a PLA is a few
nanoseconds!
The PLHS473
The PLHS473 devices are 24-pin PLAs.
Each has 24productterms, 11 inputs, 9bidirectional pins and 2 dedicated outputs.
Each output and bidirectional pin is independently tri-stateable from the OR array.
Unlike the traditional PLA, the 3-State
control of the 473 devices is accomplished
with an OR function. This feature supports
more complex (sum of products) logical
control of the outputs. Output polarity is
programmable (active-High or Low) via
the 11 EX-OR gates that precede the output pins.
The PLHS473 is TTL compatible, with a
worst-case propagation of 22ns.
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Figure 1-1. Signetics PLUS153D
August 1989
693
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Figure 1-2. Signelics PLUS173D
Augusl1989
694
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
86
8,
8,
8,
--~~g6----------------~~~
8,
~~_
80
_---J-@
--~~~6--------------------~o.
--~~~C--------------------~OA
23 • •
•
• •
• 16
15. • •
•
•
• 8
7·..... 0
Figure 1-3. PLHS473 Architecture
August 1989
695
Signetics
Programmable Logic Design
and
Application Notes
Programmable Logic Devices
PAL ®. TYPE DEVICES
Signetics provides state-of-the-art industry standard PAL devices, both bipolar and
CMOS. The range of offers spans the entire gamut of performance options; zerostandby power generic devices specified
over the commercial, industrial and militarytemperature ranges, orthe ultimate in
high speed, an EeL compatible 20EV8
device. Almost every option in between is
also offered.
The PAL architecture consists of a programmable AND array, followed by a fixed
OR array. The somewhat rigid architecture lends itseH to less complex, narrower
logic functions. There are three basic
PAL-type device configurations. The
XXL8 devices are strictly combinatorial.
The XXRX series offers a range of
registered and combinatorial outputs.
August 1989
The XXV8 series is considered to be generic in nature, in that the output macros
are variable (hencethe"V") ascombinatorial or registered. Most frequent applications include counters and shifters (the RX
series), and small decoders and multiplexers (the L8 series).
Industry standard software can be used
with Signetics PAL-type devices. Full
support is also provided via the Signetics
AMAZE Design software.
The Signetics PAL-type device descriptions follow. The line is being expanded
continuously. If you don't find the device
you need for your circuit, please contact
Signetics toll-free at (800)227-1817,
Extension 900.
696
Signetics PLHS18P8B
Figure 2-1 depicts the Signetics
PLHS18P8B which is a bipolar, PAL-type
device. The propagation delay time will be
15 nanoseconds maximum from stable
inputs to stable outputs. The part has 10
inputs, eight bidirectional pins, and 72
product terms. Due to the programmable
output polarity, the PLHS18P8B can functionally replace 13 other standard PAL devices. Being pin compatible to all 20-pin
combinational PALs increases the parts'
versatility considerably. The PLHS18P8B
can sink 10L = 24mA (max).
Output polarity control for this PAL-type
part is achieved identically to the procedure for the PLUS153D and PLUSI73D.
The PLHS18P8B is ideal for address and
I/O decode for moderately fast microprocessors from both a speed and current
drive capability.
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
10
a,
a,
I,
a,
I,
a,
I,
B,
I,
a,
I,
a,
I,
·0
I,
I,
Figure 2-1. Signetics PLHS18P8B
August 1989
697
Signetics Programmable Logic Devices
Programmable logic Design
and Application Notes
The PLUS16LBD and-7
The PLUS16L8D and -7 PAL-type devices are
functionally identical to other commercially
available 16L8 PAL ICs. Figure 2-2 shows an
extremely simplified version. Less flexible than
a PLA, the PLUS16L8D/-7provides raw speed
and current drive so important fordriving SRAM
arrays on RISC processors or the control/data
lines on rapid bus structures. The PLUS16L8D
has a worst-<:ase propagation delay of 10ns.
The worst-<:ase TPO of the -7 is 7.Sns. 24mA
output drive is guaranteed.
The PLUS16L8D/-7 have seven productterms
per OR function and one per 3-State control.
Six of the eight outputs can be configured as
inputs or outputs. The PLUS16L8D/-7 are
available in 20-pin plastic DIL or 20-pin PLCC
packages.
PLUS16L8D
20
I.
I,
0.,
12
8.
13
B5
AND
OR
ARRAY
10
Bo
15
B3
I.
B2
17
8,
18
00
GND
Ig
Figure 2-2. PLUS16L8 (D and -7)
Augus! 1989
Vec
698
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
The PLUS16R8D and-7
PLUS16R8D
The PLUS16R8D and-7, like the PLUS16L8D
and -7 is identical to other manufacturers' registered PAL devices. The parts have eight
inputs, eight outputs, and eight D-flip-flops.
Each flip-flop feeds an output pin through a
3-State buffer. The output of each D-flip-flop,
0, is also fed back to the AND array. Each output is capable of driving 24mA 10L max, with all
ouputs simultaneously asserted.
'--/
20
vee
D7
D.
The PLUS16R8D has a worst-<:ase propagation delay of IOns. The worst-ease tpo of the-7
is 7.5ns. The PLUS16R8D and-7 are available
in 2O--pin plastic DIP and 20--pin PLCC.
DS
D4
D3
D,
D,
00
OE
Figure 2-3. PLUS16R8 (0 and-7)
August 1989
699
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
The PLUS20LSD and -7
PlUS20lBD
The PLUS20L8D and -7 devices have 14
inputs, two dedicated outputs and six bidirectionals. The tpo are 1Ons max and 7.5ns max,
respectively. The 24mA of output low current of
these devices can drive capacitive address line
inputs and pc-board traces through long
layouts. This makes the particularly suitable for
driving SRAM, video DRAM, and FAST dynamic RAM arrays in 32-bit microprocessor
environments.
vec
113
07
Bs
Identical to other commercially available 20L8
PAL devices, the PLUS20L8D and -7 have 56
functional product terms which are hard-wired
to eight OR gates. Each OR gate drives an
Active-Low output. The tri-state control of
each output is from a dedicated AN D product
term.
B5
B,
B3
The worst-<:ase propagation delays for the
PLUS20L8D and 20L8--7 are 10ns and 7.5ns,
respectively.
B2
B,
00
"2
'11
Figure 2-4, PLUS20L8 (D and -7)
August 1989
700
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
PLUS20RaD
Figure 2-5. PLUS20R8 (0 and-7)
The PLUS20R8D and-7
The PLC18V8Z
The PLUS20R8D and -7 are 24-pin versions
of the 16R8 PAL device. With propagation
delays of 1Ons and 7.5ns max, the parts deliver
24mA of output low current drive. Eight D-flipflops share a common clock and output enable
line. The output of each flip-flop is dedicated to
a separate output pin and is also fed back to the
AND array.
The PLC18V8Z is a multi-function, generic
PAL-type device. It is pin-compatiblewith, and
can replace 22 different 20-pin registered and
combinatorial PAL devices. To accomplish this.
the conventional 'single function' output pin has
been replaced by a configurable Output Macro
Cell. Each Macro Cell contains a D-flip-flop or
a combinatorial 1/0 path. Output polarity and
tri-state control functions are also individually
configurable. Each OMC is fed by nine AND
The PLUS20R8D and -7 are available in
24-pin plastic OIL and 28-pin PLCC.
August 1989
701
product terms, which are hard-wired in the
classic PAL fashion.
One of the key features of the part is its ability
to sink 24 milliamps IQL, compatible with other
bipolar PALdevices-yetstili comply with internal CMOS circuitry. The UV erasable version is
available in 20-pin ceramic OIL with a quartz
window.
Signetics Programmable Logic Devices
Programmable logic Design
and Application Notes
Figure 2-6. PLC18V8Z Architecture
August 1989
702
Signefics
Programmable Logic Design
and
Application Notes
Programmable Logic Devices
SEQUENCER DEVICES
Introduction
Ten years ago, in their search for a
straightforward solution to complex sequential problems, Signetics originated
Programmable
Logic
Sequencers.
Signetics Programmable Sequencers
represent a product line which combines
the versatility of two programmable arrays
(PLA concept) with flip-flops, to achieve
powerful state machine architectures.
Each arrangement or "architecture" offers
a variation of the basic concept which
combines two programmable logic arrays
with some flip-flops, in an undedicated
fashion. The PLA product terms are IlQ1
specifically dedicated to any particular
flip-flop. All, none, or any mix in between
may be connected to any flip-flop the
designer chooses. The PLA structure
therefore supports 100% product termsharing as well as very wide OR functions
preced ing the flip-flops.
Signetics line of Programmable Logic
Sequencers has been further customized
to accommodate specific types of state
machine designs. Some have both registered and combinatorial outputs, specifically for synchronous and asynchronous
Moore-type state machines. Others have
state or buried registers, as well as output
registers. These devices (PLUS105,
PLC42VA12 and PLUS405) are ideal for
synchronous Mealy-type applications.
August 1989
J-K and S-R register functions are another benefit. The logic functions provided by
these types of registers far exceed the
capability of a D--type register. The functionality of the J-K allows the designer to
optimize the logic used in generating state
transitions. Ninety percent of PAL devices
have D-type registers. All the sequencers
are equipped with three state options for
bussing operations, JK or SR flip-flops
and some form of register Preset/Reset
functions.
Finally, all PLS devices have a Transition
Complement Array. This asynchronous
feedback path, from the OR array to the
AND array, generates "complement"transition functions using a single term. Virtually hidden in between the AND array and
the OR array is the Complement Array.
This single NOR gate is not necessarily
"an array," however the inputs and outputs
of this complement gate span the entire
AND array. The input(s) to the Complement Array can be any of the product
terms from the AND array. The output of
the Complement Array will bethe 'complement' of the product term input. If several
product terms are connected to the Complement Array, their respective complements can also be generated. The output
olthe Complement Array is fed back to the
AND array, whereby it can be logically
gated through another AND gate and
finally propagated to the OR array. The
significance being that the complement
703
state of several product terms can be
generated using one additional AND product term. For example, if an efficient
method of sensing that no inputs were asserted was needed, the designer could
connect the output of appropriate AND
gates to the complement NOR gate. The
outputofthe NOR gate could then be used
to condition and then set or reset a flip-flop
accordingly. As well, he could detect a particular state variable combination and
force a transition to a new state, independent of the inputs. Or he could combine
input signals and state (AND) terms to
generate a new composite term. In any of
these applications, the ComplementArray
greatly reduces the number of statetransition terms required.
In orderto present the material in the most
concise fashion, a brief state equation
tutorial is presented first. The PLUS 105
description immediately follows. In this
capsule description, the level of detail is
expanded, so read it first for basic understanding. Each additional presentation
will be done with regard to the fundamentals described for the PLUS105. Figure
3-3 shows the detailed drawing of the
PLUS105 in full detail. Figure 3-4 shows a
compressed rendition of the same diagram so that the reader can understand
the diagram notation. The compressed
shorthand version will be used for the rest
of the sequencers.
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
While
OJ
[UJ
[/OJ
THEN
THEN
[STATE
[STATE
1J
3J
1J
[UJ
[/OJ
THEN
THEN
[STATE
[STATE
2J
OJ
IF
IF
2J
[UJ
[/OJ
THEN
THEN
[STATE
[STATE
3J
1J
[STATE
3J
THEN
THEN
[STATE
[STATE
OJ
2J
[STATE
IF
IF
While
[STATE
IF
IF
While
[STATE
When
IF
IF
Figure 3-1. Up-Down Counter
State Diagram
[UJ
I/OJ
Figure 3-2. STATE EQUATIONS to Implement Up-Down Counter
State Equation Tutorial
The PLUS105
STATE equation entry is a convenient way to
describe elementary sequential machines in a
manner which is directly related to a state diagram of the machine. The basic commands are
few, but can be combined in a powerful fashion.
Figure3-1 showsa4 state up-down counter for
a machine with an U(up)/D(down) input line.
Figure 3-2 shows the state equation syntax to
implement Figure 3-1.
This part (Figure 3-3) has sixteen logic inputs
and eight outputs. It also has eight S-R flipflops tied directly to those output pins through
3--State buffers (common control from pin 19).
The user may select pin 19 to be an Output
Enable signal or an asynchronous preset (PR)
signal which is common to all flip-flops. Embedded into the device are 48 AND gates. All
flip-flops are S-R type with an OR gate on both
Sand R. Thedesignermay choose any number
of product terms and connect them with any OR
gate. The product terms can also be shared
across any OR gate, as needed. Six of the 14
flip-flops are termed "buried registers" as their
outputs are fed back to the AND array, regenerating both the 0 and /0 state variables. There
is no direct connection to an output. Both the
input signals and the state variables 0 and /0
are fed to the AN D array through buffers which
provided the TRUE (or noninverted) and Complement (inverted) renditions of the variable.
This is critical for the efficient use of the AN D
array. The designer has all state and input
variables necessary to generate any state
transition signal to set andlor reset commands
to the flip-flops. Because 01 this AND/OR arrangement, combined with complete freedom
of configuration, all sequential design optimization methods are applicable.
The basic meaning can be summarized in the
following way. Simply, ''while in state X" if input
"Y" occurs, "transverse to state Z". This is a
Moore machine model. Mealy may be accommodated by addition of the "with" operation
which designates an output variable being
associated as shown below:
A.) While
IF
[CURRENT STATE]
with [OUTPUT VARIABLE]
[INPUT VARIABLE]
then [NEXT STATE]
or
B.) While
IF
[CURRENT STATE]
[INPUT VARIABLE]
then [NEXT STATE]
with [OUTPUT VARIABLE]
If a latched output variable is desired, the addition of a prime notion (I) to the right of the output
variable is required.
The designer must assign the binary values of
choice to specific states for a state equation
function to be implemented. The Signetics
AMAZE manual details state equation solutions with more examples, but the advantage of
state equations is that the designer can be less
involved with the internal structure 01 the
sequencer than required by other methods.
August 1989
There are many other feature capabilities
suitable for creative usage. For example, it is
common practice to use the 48 product terms
with the 6-bit buried register, treating the output
8-bitregister as an intermediate,loadable data
register only. This provides a very good bus
"pipeline" lor the ;nternal 6-bit machine.
However, other logic options can be accomplished by combining internal state inlormation
(present state) with current input information,
generating a next state which is different from
the current internal state.
704
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Figure 3-3. PLUS10S
August 1989
705
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
10
I--+---------+_ c
T 4 7 - - - - - - - - - - To
~~--~<~_[]CK
Figure 3-4. Compressed Drawing of PLUS 105
August 1989
706
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
The PLSI55, 157, and 159A constitute a three
part family of 2O--pin sequencers that are well
suited for high speed handshakers, counters,
shift registers, pattern detectors and sequence
generators. Additional applications include
testability enhancement, demonstrated in the
application examples of signature analysis and
pseudo random number generation. The three
devices are very similar in architecture. All have
a total of 12 possible outputs. The difference is
the ratio of combinational 110 to registered outputs available.
four registered outputs. All of the state variables and combinational variables are presented to the output pins by way of 3-Slate
inverting buffers. The combinational and state
variable outputs are fully connected (fed back)
back to the AND array in both the True and
Complemented form of the variable. The product includes a special feature that allows the
user to configure the flip-flops as either J-K or
D flip-flops on an individual basis. A Register
Preload feature is supported via two product
terms (La, Lb) which permit "back loading" of
data into the flip-flops, directly from the output
pins. The part can now be easily forced into any
known state by enabling La, Lb, applying data
at the outputs (previously "3-Stated"), and
applying a clock pulse. Register Preset and
The PLS155
The PLS155 is a sequencer providing four J-K
flip-flops with a PLA having 32 logic product
terms and 13 control product terms. Eight combinational 110 are available in addition to the
(LOGIC TERMS)
(CONTROL TERMS)
L
0
.
Reset functions are controlled in 2 banks of 2
registers each. Note that control product terms
are from the OR array.
The outputs of all variables are 3-State controlled by a unique partition. Pin 11 provides an
Output Enable input (OE) which can be
asserted with the EA and EB control product
terms. EA controls the flip-flops FO and Fl, and
EB controls F2 and F3. Each combinational
output term has a distinct 3-State control term
(DO - 07) originating from the AND array of the
PLA. Each combinational output variable can
be programmed as inverting (active LOW) or
non-inverting (active HIGH) by way of the
output polarity EX-OR gate associated with
each 110 pin.
E
Ii
b
b
Ii
R----+----4---+r-4
p--~----+-_tr-;
Q---t---- CK
I
I
T31
TO
Fd
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _4 _
_ _ _ _ _ JI
Copies
Figure 3-5, PLS155 Architecture
August 1989
707
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
The PLS157
This sequencer features all the attributes of the
aforementioned PLSI55, however, two flipflops have been added, at the expense of two
of the combinational outputs. Pins 13 and 18 on
the PLS157 are flip-flop driven, where the same
pins on the PLS155 are combinatorial, driven
from the PLA. Again, all variables (input,
output, or state variables) fully connectoverthe
PLA portion with both True and complemented
versions supplied. The number of product
terms, the Complement array, Output Enable,
3-State configurations, Register Preload, etc.,
track the PLS155 part. As with the PLSI55,
distinct dock input on pin 1 is provided for
synchronous operation. Register Preset and
Reset are available in 2 banks. Pin F4 and F5
are controlled from the AN D array (product
Terms P B and RB). The remaining 4 registers,
Fa - F3 , are controlled by the sum terms (from
(LOGIC TERMSI
P
(CONTROL TERMSI
R
L
L
D
Figure 3-6. PLS157 Architecture
August 1989
708
the OR array) PA and RA .
Designs requiring more than 16 states but less
than or equal to 64 states are solid candidates
for realization with the PLSI57. Itcan beconfigured as a Moore machine for counter and
shifter designs from the flip-flop outputs, or as
high speed pulse generators or sequence
detectors with the combinational outputs.
Mixed solutions are also possible.
E
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
The PLS159A
By extending the PLS157 arrangement even
further, the PLS 159A can be derived. Again,
maintaining identical input, product terms,
Complement array and similar 3-State partitioning, the PLS159A also resides in a 2O-pin
package. The expansion to dual4-bit banks of
flip-flops, at the expense of 2 combinational
well as the bus oriented system. For enhanced
performance, the flip-flop outputs are inverted.
To provide positive outputs ior shifters and
counters, the input variables and state feedback variables can be selectively inverted
through an input receiver or the feedback path
through the AND gate array.
outputs, enhances the number of available
internaf states while maintaining product term
and pin compatibility. Note that all registers are
controlled from the AND array in 2 groups of
four.
The PLS159A is an llkIlIlQll!1. It readily enters
the environment of the S-bit data operand as
(LOGIC TERMS)
(CONTROL TERMS)
E
OE
•i
b
b
6
B
F
'>--&-Q>-t-l K
TO
-0
F7
t.::=+::...JT~D
FO
CK~~~==========~
Figure 3-11. PLUS405
August 1989
713
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
The Future is Here Now.
Recent architectural extensions are currently
available from Philips Components-Signetics.
These include the PLC415 and PLC42VA12.
These new "Super Sequencers" are available
now for high-end new designs. Please check
the data sheet section of this handbook for
more information.
August 1989
714
Signetics
Programmable Logic Design
and
Application Notes
Programmable Logic Devices
APPLICATION SECTION
INTRODUCTION
This section provides examples of the
wide ranging applications for Signetics
PLD products. In microprocessors, for example, PLDs can solve complex interfacing problems. Theirwide input gates make
them ideal for microprocessor decoding,
memory and I/O functions.
Communication is another key area
where PLDs can solve difficult problems.
Here PLDs simplify the process of developing products to an emerging standard.
Signetics has provided a series of examples to show PLDs make it possible to
change a design the same instant the
standard changes. The examples contain
a range of applications from whole
protocols and simple scramblers to a customizable speech synthesis system.
Other examples in this section illustrate
applications in home security and instrumentation.
The applications in this section are designed to show how Signetics PLDs can
solve many classic design problems.
However, it is important to note that each
example exploits only one of the many facets of the product.
Introduction
Architectural bottlenecks have migrated
from one point to another within a system
throughout the history of computer design. Currently, processor speeds and
memory cycles have become so tightly
designed 1hat little margin exists should
any incompatibility arise between them.
Driven for both speed and pin compatibility, DRAM manufacturers have added additional modes to their designs such as the
nibble and page modes. Processor designers have resurrected the multiple bus
Harvard architectures, as evident in some
of the commercially available RISC chips.
And, by using small block read ahead
caches, the processors hide slower
DRAM accesses typically by bursting as
many as four words in a read cycle. Attempting to match the DRAM to the processor, or perform parity or ECC at full
speed (Le., no wait states) requires a fine
balance of time budgeting, cost tradeoff
and impedance matching among other issues. Performihg all of these functions
has resu~ed in an address decode time
between 10 and 20 nanoseconds, depending on the required set of tradeoffs.
For example, a tight 80386 memory cycle
atfullspeed may require 10 nanoseconds,
which could be accomplished with a Dspeed PLD, or with a fast PROM. Less
than 1Ons is desirable, so 7.5ns PAL-type
devices will help. The new PHD16N8 and
PHD48N22 are ideal.
System Partitioning
MICROPROCESSOR
INTERFACING WITH SIGNETICS
PLDS
Microprocessor interfacing is the art of
connecting the attributes of a microprocessor, very skillfully to its surrounding environment. They must lineup carefully and
match the appropriate timing, address
and data signals to achieve an effective interaction. This section illustrates multiple
interfacing examples.
August 1989
Currently, most 32-bit processors generate an address capable of logically spanning four gigabytes. This is accomplished
with 32 bits of distinct address lines. Available memories occupy much less (i.e., 1
megabit or less). A 1 megabit DRAM requires twenty bits of address, so selecting
across twelve bit fields may be appropriate. Single module selection (or common
address banks) could be accomplished
with any logic device which can decode
(i.e., generate a select condition) over the
715
12 high order address bits. Many contenders exist for this reason. The classic solution would be the 74S133 (!PD = 4ns) 13
input NAND gates with an additional
74S04 inverter to decode. Total decode
time is at least eight nanoseconds. Depending on the cycle requirements, this
may be required, but typically is not. A
more efficient method is simply a PLD
which combines the wide logic gate with
''free" input inverters where required.
Additional select qualifiers may be needed to distinguish the precise assertion
time of the select signal. The total number
of decoding inputs will exceed the applied
address signals.
Given the memory choices selected, the
designer must choose a decoding device
which meets his criteria. A typical system
would have a mix of PROM (system functions), STATIC RAM (no wait memory or
cache), DRAM (slower bulk store) or dual
port memory (video RAM or shared store).
Each will have differenttiming constraints.
Most systems today will have much less
than the four gigabytes they can address,
but for software expansion reasons (or
other system considerations) the memory
may not run contiguously and small
patches might be spread over the entire
range. tt will be important to decode precisely to known regions and avoid accidental reference to nonexistent regions.
In selecting a decode device, assuming
one is required, several considerations
become key. Should the software allow it,
or the performance require it, the fastest
decode is by distinct selection via direct
connection to high order address lines. In
today's organizations this will be the fastest, most fragmented memory space.
Electrical drive pitfalls can exist here.
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Tight layout of the board is also important so
that precious, paid for nanoseconds are not
given up to long PC connect lines, inputcapacitance and voltage reflections. Many of the
Signetics candidates illustrated in this discussion are limited to speed applications requiring
no more than 16mA output drive. They may be
inappropriate for extremely dense RAM arrays
with long pc-trace interconnects. For simple,
fast decode purpcses, the D-speed PAl-lYpe
devices are good, with a logical choice being
the 7.5ns PALICs. The new PHD family of parts
is even better.
Some straight forward decoding examples
follow with criteria for selecting specific
Signetics PlD products for decode. These examples exploit only one of many facets offered
by these products. Other examples illustrate
(Data 0-7), lMDF (Data 8-15), UMD (Data
18-23), or UUD (Data 24~1). All subfieldscan
be simultaneously asserted as dictated from
decoding the size control lines (SIZO, SIZ1) in
conjunction with the low order address lines
(AO,Al).
the use of Signetics PlDs for customized interrupt handling and a most extensive example
shows a powerful solution to a SCSI bus inter-
face.
Bus Size Decoding for the 68020
-PLUS18P8B
Because the solution requires no product term
sharing and is intensive on neither input nor
output pins, a simple fast PAL device is the best
choice-the PlHS18P8B is designated. The
basic operation is to decode the input lines to
indicate whether the bus should have 8, 16, or
32 bits driven onto it These signals are
supplied to a device external to the microprocessor which then asserts the corresponding
data. Figure 4-2 shows an appropriate pinlist
under AMAZE with Figure 4-2 showing the logic
equation file.
Address decode for this class of processor is
shown in successive sections (Le., 68030 and
80386). This example depicts a slightly
different problem--"data bus sizing" which is
accomplished by decoding the address and
control signals replicated in the logic diagram in
Figure 4-1. Basically the 68020 device will
strobe data onto the 32--bit databus in byte
oriented subfields of the large word. Sixteen bit
ports can receive either the upper or lower 16
data lines. Other ports can respond to llD
UUD
UMD
~
•
UD
UD
LD
~--I
I ...
AI
SlZD
SlZI
UUD
....
r ........
r ........
UMD
LMD
UD
UD
LD
I ....
...
Figure 4--1. 68020 Bus Sizing logic
August 1989
716
LMD
=
=
=
=
=
=
UpperUpper Data (32-Bi1 Port)
Upper IIcIdIe Data (32-811 Port)
Lower IIidcIe Data (32-1Ii1 Port)
LowerLo wer Data (32-Bil Port)
UpperD.ta (16-811 Port)
Lower Data ( I _ ' Port)
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
File Name
BYTESEL
4/31/1988
Date
@DEVICE
PLHS18P8
@DRAWING
@REVISION
@OATE
@SYMBOL
@COMPANY
@NAME
@OESCRIPTION
@PINLIST
~<--------FUNCTION-------->
<--REFERENCE-->"
"PINLABEL PIN # PIN FCT
PIN ID OE CTRL"
AD
1
I
10
11
Al
SIZO
12
SIZI
I
13
N/C
14
I
N/C
15
N/C
16
I7
N/C
I
18
N/C
GND
10
ov
GNO
N/C
19
11
I
DO
12
/B
BO
N/C
N/C
13
/B
01
Bl
LO
14
0
B2
02
03
UD
15
0
B3
LLO
16
0
B4
04
LMD
17
0
BS
05
UMD
18
0
B6
06
07
UUD
19
0
B7
+SV
VCC
20
VCC
@COMMON PRODUCT TERM
~CPT label = (expression)"
@I/O DIRECTION
@LOGIC EQUATION
UUO~ /AO*/Al ;
UMO~ /SIZO*A1tAl*AO+SIZ1*/Al ;
LMO~ /AO*Al+/Al*/SIZl*/SIZO+SIZl*SIZD*/Al+/SIZO*/Al*A
LLO= AO*SIZD*SIZ1TSIZO*/SIZ1+AO*Al+Al*SIZl
UO ~ /AO ;
LD = AO+SIZl+/SIZO ;
Figure 4-2. BYTESEL Design File
Interfacing to SPARePLUS20L8-7
The SPARC™ processor is a modern RISC device configured from a popular CMOS gate
array. Architectural details can be found in data
sheets and literature. Supporting a full 32 bitaddress decode at full speed requires a 60 nanosecond instruction or data cycle. We will
consider a SOns part although a 30ns one is
available. Figure 4-3 shows the pin definition
and Figure 4-4 the basic timing. The address is
driven out in two phases (low and high) and the
data must be present 54 nanoseconds after the
rising edge of clock 1. To meet the access time
will require an SRAM of less than 60ns. In fact,
the address generation requires 30ns from
when the low address is valid to when the high
August 1989
address is valid. This is almost untenable and
most designs will rely on the high order address
lines seldom changing with respect to the low
order ones. Therefore, assuming the high order
lines are static and basing address calculations
on the low order transitions seems reasonable.
Detecting a change from one "segment" to
another in the high lines can key a "wait" condition when addresses make big jumps. By JlQ1
doing this, will force a very expensive SRAM
solution if zero waits are required. Assuming
zero wait states are desired, this will require a
memory less than 20ns access, if the fastest
(7.5ns) PLD is chosen. By virtue of its restricted
width and even more restricted speed option for
a zero wait state solution. the PLUS20L8-7 is
the only contender. This restricts the SPARC
717
address space to 32 independent modules.
The low order address lines must be latched
within the RAM or externally.
Full performance can be achieved for 32, 64Kbit static RAMs comprising '/z-mega word
store at full speed. By allowing a single wait
state, the options open enormously to include
a full spectrum of SRAMs, PROMs, even
DRAMs with any of the other decode devices.
Figure 4-5 shows four such modules selecting
off of Al17-AH21 address lines into 16K y
4-bit, 35ns SRAMs. This populates the entire
lower two megaword space with high performance static RAM. The high order address lines
(AH22-AH31) can select other such modules
for expansion purposes.
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Von
~,,~.
GND
eLK
:on
}
AH31-AH16
ADDRESS
BUS
AS17-AS10
D31-DO
FEXe
Fee
RD
FCCV
DFETCH
F1'
} '"'C'CLe
DEFINITION
SIZE
FXACK
FLUSH
DATA
BUS
=
WE
mom
COPROCESSOR
INTERFACE
}
MB86900
FEND
FADR
LOCK
FINS
lIDS
=
=
=
BUS CYCLE
CONTROLS
W!Dm
SROID
1lROill
IRL
RESET
TC
MEXC
=
Figure 4-3. SPARe Pin Definition
August 1989
718
} '''ERR"''
& SYSTEM CONTROLS
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
1 4 - - - buns min _ _-i_~1
CLK1
CLK2
AL
AH
ASI
031-00
NOTE:
All times with respect to elKl rising edge
AL '" low order addresses
AH .. high order addresses
031-00 _ Data
ASI. address strobes
Move
Figure 4-4. SPARe Instruction Felch Timing
August 1989
719
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Figure 4-5. 1/2MEG SPARC SPACE
AugUSI1989
720
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
The 80386 Pipeline Decoder PLUS153D
For example, select a mix of memory that will
be located in small addressing chunk segments
within the lower 16 megabytes of the 80386 four
gigabyte address space. See Figure 4-6.
This decoding method will impact the memory
addressing, but in a different way. The 80386
supports a mode whereby a next address can
be asserted early (1 clock cycle) if the user
asserts the NA# pin. The interleaved slower
memory may be sued by getting the nest
ClK2
2X CLOCK {
address earlier than normal to trigger an early
memorv cvcle. Because we will be driving a
single ~ig~al, NA#, a PLUS153 can be configured with eight inputs and nine of the bidirectionals configured as inputs (i.e., 17 inputs, one
output). By decoding addresses 31-17with the
status signal M asserted high and ADS#
asserted low, an NA#wili assert early to initiate
a pipe lined early transfer with a slower RAM.
This approach allows designers to tune their
specific memory speeds to the processor,
ADDRESS BUS,)
BE3#
32-BlT{ 00-D31< DATA PLUS
DATA
BE2#
BEO#
W/R'
..
NS. . .
READY....
MI1O#
PROCESSOR
HOLD
NMI :
TS{
BYTE
}
ENABLES
}
COPROCESSOR SIGNALING
RESET:
r
}
POWER CONNECTKlNS
~
~
lOCK. . .
r
...
HlDA ...
INTR ...
lNTERRUP
DiG.
80386
BS16# :::
~
32-BIT
ADDRESS
}
r
r-
BUS
ARBITRAT ION{
..
:
~
~
BE1#
...
Fiaure 4-10 shows NA# qenerated for a pipelin-;'d address located in the lowest 128K of the
address space. In Figure 4-11, the PLUS153D
is shown as a single 17-input NAND function,
most of the remaining portion of the part is unused. The address strobe and M signals are
includedto correctly qualify the address and not
generate glitches into the NA# pin. Unless the
p.c. board is poorly designed, the output drive
of the PLUS 153D will be adequate to drive the
NA# pin and any additional PC-metal. Figure
4-12 shows the AMAZE equation to decode.
"
:"
BUS
CONTROL
according to timing needs.
PEREa
I~
BUSY#
~
I....
ERROR.
...
I~
v"
GND
I'"
Figure 4-7, Functional Signal Groups
1023
Figure 4-7 illustrates the 80386 signal groups.
1022
Figure 4-8 illustrates various bus cycles with no
wait states, and no pipelining.
•••
Figure 4-9 illustrates bus cycles with and without pipelining.
Figure 4-10 illustrates the CLK2 time spans.
1S
1 MEG Chunk
14
1 MEG Chunk
••
Figure 4-11 illustrates the NA# pin lis!.
Figure 4-12 illustrates the .BEE file for NA#
generation.
•••
GIGABYTE 0
••
1 MEG Chunk
1 MEG Chunk
1 MEG Chunk
1 MEG Chunk
Figure 4~. A Typical Address Space
August 1989
721
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
CLK2 [
(82384 CLK)[
BEO-BE3# [
A2-A31.
Ml1 0#. D/C#
W/R# [
ADS# [
NA# [
BS16# [
READY# [
LOCK# [
00--031 [
IDLE STATES ARE SHOWN HERE FOR DIAGRAM VARIETY ONLY.
WRITE CYCLES ARE NOT ALWAYS FOLLOWED BY AN IDLE STATE.
AN ACTIVE BUS CYCLE CAN IMMEDIATELY FOLLOW THE WRITE CYCLE.
Figure 4·8. Various Bus Cycles and Idle States with
Non-Pipeline Address
August 1989
722
Signetics Programmable logic Devices
Programmable Logic Design
and Application Notes
I r'\1
.-
IDLE
CYCLE 2
IULC
NON-PIPELINED
(READ)
ClK2 [
(82384 ClK) [
BEO-BE3# [
A2-A31.
Mll0#.DIC#
WIR# [
ADS# [
NA# [
BSI6# [
READY# [
lOCK# [
DO-D31 [
Figure 4-9. Mixed PipelinedlNon-Pipelined Signals
PIPEUNED REGION IN LOWEST 128K
1S(AD31:
~
:
AD17
16 (HIGH)
7:J::>----
PLUS1
h
NAI
18
M-
17 (HIGH) AD .....- - . . . J
NA#
=IAD31.JAD30·/AD29 ... /AD17.M.ADS# ;
Figure 4-10. Pipelined Region NA# Generator
August 1989
723
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
File Name : NA 386
Date
5/16/1988
Time : 16:37:58
####################
LABEL
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
GND
FNC**
OV
P I N
L I S T
PIN - ---- ------p IN **
1-1
1-20
2- I
P
1-19
L
3-1
1-18
4-1
U
1-17
5-1
S
1-16
6-1
1-15
7-1
1-14
8-1
1--13
9- I
1-12
10-1
1-11
####################
FNC
+5V
I
LABEL
VCC
AD22
AD21
AD20
AD19
AD18
AD 17
M
lADS
10
INA
----------Figure 4-11. Pinlis! NA_386
File Name : NA 386
Date
5/16/88
Time: 16:38:8
@DEVICE TYPE
PLUS153
@DRAWING
@REVISION
@DATE
@SYMBOL
@COMPANY
@NAME
INA386
@DESCRIPTION
THIS DESIGN DRIVES THE NA# SIGNAL LOW WHEN ASSERTED ON AN
80386 PROCESSOR FOR A MEMORY REGION SPANNING THAT DECODED
BY THE EQUATION CONTAINED HEREIN.
@COMMON PRODUCT TERM
@I/O DIRECTION
@LOGIC EQUATION
INA:/I/AD31*/AD30*/AD29*/AD28*/AD27*/AD26*/AD25*/AD24*IAD23
*/AD22*/AD21*/AD20*/AD19*/AD18*/AD17*/ADS*M);
Figure 4-12. NA_386 .BEE File
August 1989
724
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
68030 Address DecodingPLUS173D
Although designers generally try to optimize
every nanosecond of microprocessor performance, it is typically not necessary for the CPU
to always operate at full speed. Operating the
CPU, when acceptable, at a slower speed can
bring about a more economical and compact
system. This is due to higher costs associated
with fast memory and greater board area usage
of very wide memory configurations.
200ns B-bit EPROM and fast 35ns 32-bit RAM
to a 68030. A PlUS173D was chosen for its
high speed and large number of inputs and
outputs. Figure 4-14 shows the AMAZE pinlist
and Boolean equations for the device. The
EPROM occupies memory space 0--32K while
the RAM occupies addresses 64K-128K. However, please note that because not all of the
upper memory address bits were decoded, the
memory arrays will also appear at other
addresses.
Some software routines in which slower performance may be acceptable a.re durina Dower
up initialization, diagnostic routines, or p~ssibly
some exception processing routines. Where
speed is not critical, an 8-bit bus is the most
economical and compact because of readily
available byte wide memory components and
buffers. The 68030 is easily interfaced to 8, 16,
or 32-bit ports because it dynamically interprets the port size of the addressed device during each bus cycle. Figure 4-13 shows an
example of interfacing both a relatively slow
AO- A14
,J;
+
27C256
,.--,
L
00
DO
F174
,..--t>
MR
03
32Kx8
EPROM
:J
r
EN
Q
0
IX
0-
I,
>---[><>--1--117 82
r--[><>--1--I1161 8,
IS
00
0123
4567
a i10ll
121l1.,5 "n1819 20212223 24252627 21293031 32333U53637383e
INPUTS (0-39)
August 1989
728
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
(
"
INST. BUS
"'oJ
29000
I
I
I
,..
....
A31
SIGNETICS
20L8D
A16
AO-AI5 I\,.
~
...
,;
1
1
t-
E
-
r-
tt-
16Kx 4
SRAM
rr-
V
Figure 4-17. High Speed Burst Mode Configuration
Consider, for example, the configuration
depicted in Figure 4-17 with Motorola MCM
6288 SRAMs. As depicted, there are eight
modules forming a 16K word space. The 29000
is targeted to drive SOpf according to the data
manual at full speed (25MHz clock). How much
additional time delaywill be attributed to the bus
and RAM loading?
For the chosen RAM configuration Cin = 8 (5pf)
= 4Opf. We will have to ~ some values for
p.c. wiring. One common one today is about
2Opflft. Placing our RAM on the same board,
August 1989
near the processor should require about a foot
of trace/address line. The average CL = (40 +
20) pf. This is just beyond the 10ns specified for
testing the 2OL8 (i.e., 50pf), however, if we
ignore it, the extra loading will not significantly
impact this small system.
To include it would incur additional assumptions about the pull up and pull down resistance
of the 20L8 (these values are typically between
5 and 20 ohms), but are not strictly specified.
The result is that we are within 2 nanoseconds
of time delay by ignoring the capacitance.
729
Tdelay (2018)
Tdelay (RAM access)
Tdelay (29000)
= 10ns (MAX)
= 25ns (MAX)
= 5ns (MAX)
40ns (MAX)
Adding anything into the data path or a poor
circuit layout can take the design out of spec.,
but by these assumptions, is can succeed.
Design slack may be generated simply by inserting the 20LS-7 and one gets 2.5ns of free
time margin.
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Interrupt Handler -
PLS179
In the 1970's I. C. manufacturers made the error
of introducing microprocessor chips without
having family support chips available. Often,
months or years passed before relatively
simple family additions arrived. later, a similar
situation arose when bus s1andards, LAN standards, and disk standards failed to settle down
for system designers to get sufficient market
lead without LSI solutions. PLDs could have
helped much here! As an example of designing
a microprocessor family part, consider Figure
4-18, which depicts an interrupt handler. In particular, note that interrupt inputs will be latched
into an 8-bit register. This in tum will be
encoded to a 3-bit vector which may be appre>priately enabled and applied to the microbus.
Figure 4-18 shows the eight flip-flops as having
J-K and 10 inputs which will be generated with
a PLSl79 by switching the flip-Hop control.
Appropriate control signals for the various
transactions might be as follows:
1. CLOCK - the system synchronous time
base.
2. Interrupt Enable - when asserted high
from the microprocessor, allows interrupts
to be generated to the microprocessor.
3. Interrupt - a strobe or level defined to indicate a pending interrupt and a valid
encoded vector.
August 1989
4. Interrupt Acknowledge - a response
signal from the microprocessor which may
be used to enable the 3-bit vector onto
the bus. As well, it may initiate clearing
the currently asserted interrupt latch.
5. IINTO-IINT7 - eight possible interrupt request signals which must be asserted low
and held there until service for that device
has occurred.
6. Reset - this is a system override signal
which will clear all Hip-flops during initial
operation.
Basic Operation
Initially, the part should be reset by asserting
the RESET pin high, asynchronously. Then,
when interrupts are enabled, the ID-inputs to
the 8 flip-flops will be synchronously scanning
for interrupt inputs (asserted low). This will put
a nonzero value into the eight bit register which
will generate an interrupt output, combinationally through the Complement array. In parallel,
a ~bit encoded vector will be applied on the
VECO, VEC1, VEC21ines. Asserted high logic
will be assumed for the vector. Presumably, a
microprocessor will interrupt this, transfer control to a service routine and clear the interrupt.
The clear will be accomplished by disabling
interrupts and strobing the vector value back
730
into the PLS179, using the lACK signal. Disabling the interrupts will put the registers into J-K
mode. J is tied to zero and K is decoded from
the specifically strobed vector. Therefore, synchronous clear of the high priority bit is done.
Interrupts are then re--enabled and the process
continues.
The PLS179 solution offers room for user alteration. For example, the lACK condition could
be redefined as a combination of the ZOO 10REO and M1 signals, or any specific splitting of
internal signals could be easily done. The
design could fitintoa PLS159A, but there would
be less room for variation for specifIC users exact needs. Figure 4-20 shows the pinlist for the
handler. Figure 4-21 gives the corresponding
design file. A simulation Rulertemplate is given
in Figure 4-22, and Figure 4-23 shows a simulation log file for some example interrupt transactions. In Figure 4-23, the simulation begins
by asserting RESET followed by successive
assertion of each interrupt bit to demonstrate
the vector encoding. The second half begins
with all eight interrupts asserted simultaneously and each is cleared successively in descending priority. IINTO is the highest priority. The
interrupt is actually asserted through the
PLSl79 Complement array behaving as a
simple NOR gate.
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
IINm
R6ET __________- ,
INTENA [make D FFSJ
ANTENA [make J-K FFS]
ANTO
I I no
----J
I'
nNTI
no
n,
nNT2
nNT3
--------i
INT
nNT4
KLEARO
nNTS
n,
n.
13
00
nNT6
VO
n,
n.
n3
nNT7
liNn
I.
00
14
KLEAR,
00
n.
n.·
n'
nNT2
ANT.
KLEAR2
E
nNT3
N
ANT3
VECO
ns
0
VEC1
D
16
00
ANT4
VEC.
R
KLEAR4
A.
A.
U
M
C
KLEAR3
v.
M
IS
00
n,
n.
n3
M
ns
0
n6
nNTS
17
ANTS
Figure 4-19. Encoder Logic Diagram
KLEARS
nNT6
KLEARO
ANT6
KLEAR6
D
KLEAR.
C
KLEAR3
0
ANT7
KlEAR4
1J
KLEAR7
K
341
KLEAR,
KLEARS
E
0
D
E
R
KLEAR6
KLEAR7
LA
=La =INTENA.nNT
Figure 4-18. Interrupt Handler
August 1989
731
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@DEVICE TYPE
PLS179
@DRAWING
@REVISION
@DATE
@SYMBOL
@COMPANY
JOE USER
@NAME
GENERIC INTERRUPT VECTOR GENERATOR
@DESCRIPTION
@PINLIST
~<--------FUNCTION-------->
"PINLABEL
CLOCK
ENA
RESET
lACK
N/C
NIC
N/c
NIC
NIC
INTERUPT
VECO
GND
aTE
VEC1
IINTO
/INT1
IINT2
/INT3
/INT4
/INTS
/INT6
/INT7
VEC2
VCC
PIN #
1
PIN_FCT
CK
I
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
<--REFERENCE-->"
OE CTRL"
PIN ID
CLK
10
11
12
13
B
B
OV
14
IS
I6
17
BO
B1
GND
IOE
IOE
B
IB
IB
IB
IB
IB
IB
IB
IB
B2
FO
F1
F2
F3
F4
F5
F6
F7
B3
+SV
vce
DO
D1
D2
EA
EA
EA
EA
EB
EB
EB
EB
D3
Figure 4-20. Interrupt Pin Ust
August 1989
732
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@COMMON PRODUCT TERM
/INTO*/INTl*/INT2*INT3
CPT2~
/INTO*/INTl*/INT2*/INT3*/INT4*INTS
CPT3~
/INTO*/INTl*/INT2*/INT3*/INT4*/INTS*INT6
CPT4~
/INTO*/INTl*/INT2*/INT3*/INT4*/INTS*/INT6*INT7
KLEARO
~/VEC*/VECl*/VECO*IACK; "DECODE VECTOR 0"
KLEARI
~/VEC2*/VECl*VECO*IACK; "DECODE VECTOR 1"
KLEAR2
~/VEC2*VECl*/VECO*IACK; "DECODE VECTOR 2"
~/VEC2*VECl*VECO*IACK; "DECODE VECTOR 3"
KLEAR3
KLEAR4
~VEC2*/VECl*/VECO*IACK; "DECODE VECTOR 4"
KLEARS
~VEC2*/VECl*VECO*IACK; "DECODE VECTOR 5"
KLEAR6
~VEC2*VECl*/VECO*IACK; "DECODE VECTOR 6"
KLEAR7
~VEC2*VECl*VECO*IACK; "DECODE VECTOR 7"
@COMPLEMENT ARRAY
/C ~ /(INTO + INTI + INT2 + INT3 + INT4 + INTS + INT6 + INT7);
@I/O DIRECTION
D3
ENA;
02
ENA;
01
ENA;
DO
ENA;
@FLIP FLOP CONTROL
FC ~ /ENA;
@OUTPUT ENABLE
CPTl~
EA~OTE;
EB~OTE;
II
@INPUTS
13 lOTE
RESET
2 INTENABLE
22
21
20
19
18
17
16
15
/INT7
/INT6
/INTS
/INT4
/INT3
/INT2
/INTI
/INTO
4 lACK
23 VEC2
14 VECI
11 VECO
@OUTPUTS
10 INTERRUPT
23 VEC2
14 VECI
11 VECO
@REGISTER LOAD
LA~ENA;
LB~ENA;
@ASYNCHRONOUS PRESET/RESET
RA
RESET;
RB
RESET;
PA
0;
PB
0;
@FLIP FLOP MODE
MO,Ml,M2,M3,M4,MS,M6,M7
1;
@LOGIC EQUATION
VECO
(/INTO*INTI + CPTI + CPT2 + CPT4);
VECI ~ (/INTO*/INTl*INT2 + CPTI + CPT3 +CPT4);
VEC2 ~ (/INTO * /INTI * /INT2 */INT3*INT4 + CPT2 + CPT3 + CPT4);
INTERRUPT ~ (/C);
INTO:
J~O;
K~KLEARO;
INTI:
J~O;
K~KLEARl;
INT2;
J~O;
K~KLEAR2;
INT3:
J~O;
K~KLEAR3;
INT4:
J~O;
K~KLEAR4;
INTS:
J~O;
K~KLEARS;
INT6:
J~O;
K~KLEAR6;
INT7:
J~O;
K~KLEAR7;
Figure 4·21. Interrupt Design File
August 1989
733
22
21
20
19
18
17
16
15
/INT7
/INT6
/INTS
/INT4
/INT3
/INT2
/INTI
/INTO
Figure 4·22. Interrupt Ruler File
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
PLS179 INTERRUP
C
L
INP
Time
I/O
14:53:31
<~PREV~>
Date
~
8/5/1987
<~NEXT~>
<~FOUT~>
K E 76543210
3210
76543210
76543210
76543210
C
C
C
C
C
C
C
C
C
LLLH
LLLLLLLL
LLLLLLLL
LLLLLLLL
HLLLLLLL
LHLLLLLL
LLHLLLLL
LLLHLLLL
LLLLHLLL
LLLLLHLL
LLLLLLHL
LLLLLLLH
HHHHHHHH
HHHHHHHL
HHHHHHLL
HHHHHLLL
HHHHLLLL
HHHLLLLL
HHLLLLLL
HLLLLLLL
LLLLLLLL
LLLLLLLL
HLLLLLLL
LHLLLLLL
LLHLLLLL
LLLHLLLL
LLLLHLLL
LLLLLHLL
LLLLLLHL
LLLLLLLH
HHHHHHHH
HHHHHHHL
HHHHHHLL
HHHHHLLL
HHHHLLLL
HHHLLLLL
HHLLLLLL
HLLLLLLL
LLLLLLLL
NNNNNNNN
HHHHHHHH
C
C
C
C
C
C
C
C
C
C
TRACE TERMS
a
0 11111111
11111010
11111001
11111001
1 11111001
1 11111001
1 11111001
11111001
11111001
11111001
11111001
11111100
11111100
11111100
11111100
11111100
11111100
11111100
11111100
HHHL
HHLL
HLHL
HLLL
LHHL
LHLL
LLHL
LLLL
LLLL
000.
OOL
010.
011.
100.
10l.
110.
l1l.
-------X
BBBB
BBBO
LLLLLLLH
LLLLLLHH
LLLLLHHH
LLLLHHHH
LLLHHHHH
LLHHHHHH
LHHHHHHH
HHHHHHHH
I/O CONTROL LINES
DESIGNATED I/O USAGE
ACTUAL I/O USAGE
PINLIST ...
01 13 09 08 07 06 05 04 03 02 23 14 11 10
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
22 21 20 19 18 17 16 15
Figure 4-23. Interrupt Simulation Log File
August 1989
734
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
SCSI TARGET INTERFACE PLUS105 AND PLUS153B
Overview
Thisapplication provides acomplete solution to
the SCSI Target Interface. As well, it includes
a detailed rendering of the PLUS 105 controlling
transaction with a complete state equation
solution.
Introduction
From its first introduction, the SCSI Bus (known
as SASI in its initial days), has gained wide
acceptance as a small computer peripheral
bus. As the performance capabilities of mass
storage peripheral devices increased, other
bus specifications came into being to handle
the increased performance requirements. Interfaces such as the High Speed SCSI, ESDI,
and proposed bytelword wide bus for high
performance mass storage devices (to replace
the de facto standard SMD Interface) are gaining acceptance. Though different from each
other, they present the system designer with
surprisingly similar handshake requirements
for the transfer of command, status, data and
other information among hosts andlor targets
connected to the bus.
In recent years severallC manufacturers have
introduced single-chip controllers for the SCSI
Bus, but none yet for the new proposed buses.
The purpose of this application note is to use
the SCSI Bus, known to most designers, as the
vehicle to demonstrate the ease with which
such buses can be handled by high performance, low cost programmable sequencers. The
design described is based on the PLUS105 (or
the higher performance PLUS405).
High performance programmable sequencers
using the architecture exemplified in the
PLUS105 have been available since Signetics
invented and introduced the PLS105 in 1980.
Functional Description
The SCSI Interface described in this document
is a Full Target Implementation that includes
the following features:
-
Arbitration Capability
Reselect Capability
Software Programmable Target I.D.
Full DMA Interface
Interrupt Generator
The Reselect and Arbitration capabilities
enable the implementation of an efficient, intel-
ligent target controiier. Once a command is
received, the target can disconnect from the
SCSI Bus, execute the command and reconnect to the SCSI when data or status needs to
be transferred to the requester. This reduces
the amount of idle time on the bus; it also
enables the target to receive multiple commands and execute them in the most efficient
manner.
The software programmable Target I.D. allows
the same design to be used for multiple targets
sharing the same SCSI Bus. The DMA Interface is based on a straight-forward DMA
RequestiDMA Acknowledge Handshake protocol, enables fast data transfers without undue
burden on the local intelligence.
An open collector, active low interrupt is
provided to request service by the local intelligence at the completion of transfers or in the
event of errors.
Programmer's Interface
The SCSI Port is operated through the use of
five independ8ntly addressed registers:
STATUS, COMMAND, TARGET ID, DATA IN,
DATA OUT.
ADDRESS
REGISTER
ACCESS MODE
Base + 0
Base + 0
Base + 1
Base + 2
Base + 2
STATUS
COMMAND
TARGETID
DATA IN
DATA OUT
Read only
Write only
Write only
Read only
Write only
The 5 registers are 8 bits wide with bit definitions as described below:
IROE
-
SET to enable the generation of interrupts from the Port.
PORTE
-
SET to enable operation of the SCSI Port. Negation of this signal is required to clear the interrupt generated
at the completion of every command.
DMAE
SET to enable the DMA Interface of the SCSI Port.
CTLE
Defines the direction of transfers on the SCSI Bus
o : From SCSI to TARGET
1 : From TARGET to SCSI
MESG
-
CTRL
SET for MESSAGE Transfers on the SCSI Bus
Defines the type of transfer on the SCSI Bus
o : DATA Transfer
1 : COMMAND or STATUS Transfer
SFC
August 1989
-
Two bit Function Code:
o 0 - Disconnect
o 1 - Transfer
- Reselect
10
11
- Arbitrate
735
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
CMPL
Function Completed. This signal gated with BIT 7 (I ROE) of the Command Register generates an Interrupt to
the local intelligence.
PARE
Parity Error. The source of the error can be determined from the state of BIT 4 (CTLS) in the COMMAND
Register:
CTLS=O - Error on SCSI Bus
CTLS= 1 - Error in local memory
SRST
-
Status of RESET signal on SCSI Bus
ATTN
-
Status of ATTENTION signal on SCSI Bus
SLCT
-
Status of SELECT signal on SCSI Bus
BUSY
-
Status of BUSY signal on SCSI Bus
ARBT
-
ASSERTED to indicated that the controller has won Arbitration and is in control of the SCSI Bus.
SLCD
-
SELECTED. If both SLCD and SLCT are ASSERTED, the controller is being selected by another device on
the SCSI Bus.
TARGET 10 REGISTER
not
7
TID
6
-
used
5
TID
4
3
2
o
Three bit code that defines the Target 1.0.
Port Operation
As described in the previous section, the port
can execute 4 commands:
Arbitrate, Reselect, Transfer and Disconnect.
Arbitrate
The port monitors the SCSI Bus for the "bus free" state. When the bus is free, the port starts the Arbitration
sequence to gain bus mastership. If arbitration is won, the port will generate an interrupt with the appropriate
status in the STATUS Register. If arbitration is lost, the port returns to the monitoring of the SCSI Bus.
Reselect
The port transfers the desired ID Byte from local memory (through DMA) to the SCSI Bus and waits for the
appropriate response from the desired controller. When the desired controller responds, the Port generates
an interrupt with the appropriate status in the STATUS Register.
Transfer
The port transfers data between local memory and the selected controller on the SCSI Bus until the DMA
Termination Signal (DMACNTO) is asserted. At completion, the port generates an interrupt with the proper
status in the STATUS Register.
Disconnect
The port relinquishes Bus mastership. This results in the "bus free" state allowing other controllers to use
the SCSI Bus. This is also the IDLE state for the Port. The port should be programmed for this state when
there is no SCSI work in progress.
August 1989
736
Signedcs Programmable Logic Devices
Programmable Logic Design
and Application Notes
Arbitration Software Sequence
PROC (arbitrate)
negate DMAE. PORTE
set SFC to ARBITRATE; assert PORTE
---wait for completion - - negate PORTE
IF port won arbitration
THEN exit with normal status
ELSE DO
IFSRST
THEN exit with RESET status
ELSE DO
set-up single byte DMA transfer
negate CTLS; assert DMAE. PORTE
- - - w a i t for completion - - negate DMAE. PORTE
exit with Port Selected status
END
END
END
RESELECT Software Sequence
PROC (reselect)
negate DMAE. PORTE
place reselectlD byte in local memory
set-up single byte DMA transfer
set SFC to RESELECT; assert DMAE. PORTE
---wait for completion - - negate DMAE. PORTE
IF good completion
THEN exit with normal status
ELSE IFSRST
THEN exit with reset status
ELSE exit with error status
END
TRANSFER Software Sequence
PROC (transfer)
negate DMAE. PORTE
set-up DMA controller
set SFC to TRANSFER; set-up CTRL. CTLS. MESG; assert DMAE. PORTE
- - - wait for completion - - negate DMAE. PORTE
IF good completion
THEN exit with normal status
ELSE IFSRST
THEN exit with reset status
ELSE exit with error status
DISCONNECT Software Sequence
PROC (disconnect)
negate DMAE. PORTE
set SFC to DISCONNECT; assert PORTE
---wait for completion - - negate PORTE
exit with normal status
END
August 1989
737
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Hardware Description
The SCSI Interface described in this document
is implemented using three Programmable
Logic Devices and a hand-full of FAST SSIIOctals. Referring to the schematic in Figure 4-30
(page 4-46), the functions of the different components are as follows:
U6 - (74F244) Port STATUS Register
U7 -
(74F273) Port COMMAND Register
Ul -
(74F374) DATA OUT Register
U2 -
(74F374) DATA IN Register
US -
(74F273)
U4 -
(74145) Asserts proper signal on SCSI bus during Arbitration.
U5 -
(PLUSI53B): RegisterDecode
: 3-bit TARGET 10 Register.
U3 -
(PLUS153B) :Parity Generator/Checker
:Arbitration Win Detection
:Port Selectad Detection
U9 -
(PLUS105) : Executes all commands
: Controls handshake with DMA controller
: Controls REOIACK Handshake with SCSI Bus
: Detacts "bus free" state
: Implements 'arbitration delay"
: SCSI Bus signafs Synchronization
: Partial Status Latch
74F38's -
High Current, Open Collector Drivers for SCSI Bus
74F14's-
Schmitt Trigger Input Receivers for SCSI Bus
NOTES:
1. The interface requires an SMHz Clock. The throughput of the interface can be increased by operating this circuit at 24MHz by using the
PLUS405.
2. The interface is initialized by an active low signal: /sYSRESET
3. The DMA Interface consists of four signafs:
DMAENBL
Software controlled DMA Enable
DMAREQ
asserted by the port (PLS105A) for each byte transfer
/DMACYCLE asserted by DMA controller as a response to DMAREQ
/DMACNTO asserted when the DMA transfer count reaches 0
4. The processor (local intelligence) interface consists of 5 signals
A1,AO
/SYSSEL
/SYSREAD IINTERRUPT-
August 1989
The two least significant address bits
A block decode signaf for the SCSI Port
Active low, READ signaf
O-READ
1-WRITE
Active low, Open collector Interrupt
738
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@DF.VICF. TYPE
PLUS 105
@DRAWING
@REVISION
@DATE
@SYMBOL
@COMPANY
@NAME
@DESCRIPTION
DNW-SIG-105
A
11-29-87
U9
SIGNETICS
DIMITRIOUS DOUROS
SCSI CONTROLLER
@PINLIST
~<--------FUNCTION-------->
"PINLABEL
8MHZ
IDMACNTO
PORTENB
SELECTED
WON ARB
BBUSY
BSELECT
BACK
BRESET
CBUSY
CSELECT
REQUEST
IARBITRATE
GND
SFCMPL
SPARERR
SDRVENB
DMAREQ
LOW
ICBUSY
ICSELECT
IREQUEST
PARERROR
CTLSCSI
SFC1
SFCO
IDMACYCLE
VCC
PIN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN FCT
CK
I
<--REFERENCE-->"
PIN ID
OE CTRL"
CLK
17
16
IS
14
I3
a
0
0
0
OV
0
0
0
0
IDE
+5V
12
11
10
F7
F6
F5
F4
GND
F3
F2
F1
FO
PR/OE
115
114
113
112
III
110
19
18
VCC
IOE
IOE
IDE
IDE
IDE
IDE
IOE
IOE
Figure 4-24. PLUS105 SCSLCTL PinUst
August 1989
739
Signelics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@INTERNAL SR FLIP FLOP LABELS
QO Q1 Q2 Q3 Q4 Q5
@COMMON PRODUCT TERM
@COMPLEMENT ARRAY
@LOGIC EQUATION
@DEVICE SELECTION
SCSI_CTL/PLS105
@INPUT VECTORS
[PORTENB,SFC1,SFCO]
"COMMAND CODE DEFINITIONS"
DISCONNECT
DATA XFER
RESELECT
ARB COMMAND
100B;
101B;
110B;
111B;
@OUTPUT VECTORS
[CBUSY,CSELECT,REQUEST,/ARBITRATE,SFCMPL,SPARERR,
SDRVENB,DMAREQ]
"DISCONNECT STATE OUTPUTS"
00011000B;
"POWER-UP STATE OUTPUTS"
POWER UP OUT' ~ 00010000B;
@STATE vECTORS
[Q5,Q4,Q3,Q2,Q1,QO]
"INITIALIZATION, IDLE, AND DON'T CARE STATES"
POWER_UP
IDLE~ lFH;
ANY STATE
3FH;
------B;
"PORT SELECTED RESPONSE STATES"
SELECTED 1
SELECTED_2
SELECTED_3
SELECTED_4
3CH;
l8H;
19H;
lAH;
"RESELECT STATE SEQUENCE"
RESELECT_l
RESELECT_2
RESELECT_3
RESELECT_4
RESELECT_5
RESELECT_6
10H;
llH;
12H;
l3H;
3BH;
33H;
Figure 4-2S.1 PLUS10S SCSI CTL .SEE File (continued)
AuguSl1989
740
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
~~_~BITRATION
ARBITRATE 1
ARBITRATE 2
ARB DELAY GO
ARB DELAY IP
ARB_DELAY_QU
STATE SEQUENCE"
=
DOH;
= OFH;
20H;
10----B;
2EH;
TRANSFER SEQUENCE"
~DATA
DATA_XFER_l
DATA XFER 2
DATA XFER 3
DATA XFER 4
DATA XFER S
DATA XFER SL
~EVENT
14H;
ISH;
16H;
17H;
34H;
lAH;
COMPLETION SEQUENCE"
COMPLETE 1
COMPLETE 2
lCH;
lEH;
@TRANSITIONS
------------ POWER-UP RESET RESPONSE --------------WHILE
IF
[POWER_UP]
[J
THEN [IDLE] WITH [POWER_UP_OUT']
------------ SCSI BUS RESET RESPONSE --------------WHILE
IF
[ANY_STATE]
[BRESET]
THEN [COMPLETE_I] WITR [DISCNCT_OUT']
WHILE
IF
[IDLE]
[/BRESET*DISCONNECT*ICBUSY]
THEN [COMPLETE_I] WITH [DISCNCT_OUT']
------------ DISCONNECT SEQUENCE ---------------
Figure 4-25.2 PLUS105 SCSI ell .SEE File (continued)
August 1969
741
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
RESELECT SEQUENCE
WHILE
IF
[IDLE]
[/BRESET*/BSELECT*/BBUSY*RESELECT*ICBUSY*ICSELECT]
THEN [RESELECT 1] WITH [CBUSY' ,CSELECT' ,SDRVENB' ,DMAREQ']
WHILE
IF
[RESELECT_I]
[/BRESET*DMACYCLE]
THEN [RESELECT_2] WITH [/DMAREQ']
WHILE
IF
[RESELECT _ 2]
[/BRESET]
THEN [RESELECT 3]
WHILE
IF
[RESELECT 3]
[/BRESET]
THEN [RESELECT 4]
WHILE
IF
[RESELECT_4]
[/BRESET*ICBUSY]
THEN [RESELECT_5]
WHILE
IF
[RESELECT_5]
[ /BRESET*ICBUSY]
THEN [RESELECT 5] WITH [/CBUSY']
[/BRESET*/ICBU5Y]
THEN [RESELECT_6]
IF
WHILE
IF
[RESELECT_6]
[/BRESET*/ICBUSY*BBUSY]
THEN [COMPLETE_I] WITH [CBUSY' ,/CSELECT' ,SFCMPL']
"------------ PORT SELECTED RESPONSE
WHILE
IF
[IDLE]
[/BRESET*PROTENB*/ICBUSY*/ICSELECT*/BBUSY*BSELECT*SELECTED*/PARERROR]
THEN
[SELECTED 1] WITH [SFCMPL' ,DMAREQ']
WHILE
IF
[SELECTED 1]
[/BRESET*/PORTENB*DMACYCLE]
THEN [SELECTED_2] WITH [CBUSY' ,/SFCMPL' ,SDRVENB' ,/DMAREQ']
WHILE
IF
[SELECTED_2]
[/BRESET]
THEN [SELECTED 3]
WHILE
IF
[SELECTED 3]
[/BRESET]
THEN [SELECTED 4] WITH [SFCMPL']
WHILE
IF
[SELECTED _ 4]
[ /BRESET*PORTENB]
THEN [COMPLETE_I]
Figure 4-25.3 PLUS105 SCSI CTl.SEE File (continued)
August 1989
742
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
ARBITRATION SEQUENCE
WHILE
IF
[IDLEJ
[/BRESET*ARB~COMMAND*/ICBUSY*/BBUSY*/BSELECTJ
THEN [ARBITRATE 1J
WHILE
IF
IF
WHILE
IF
IF
IF
IF
IF
IF
IF
IF
WHILE
IF
[ARBITRATE~lJ
[/BRESET*(BBUSY+BSELECT)J
THEN [IDLEJ
[/BRESET*/BBUSY*/BSELECTJ
THEN [ARB~DELAY~GOJ WITH [CBUSY' ,ARBITRATE' ,SDRVENB'J
[ARB DELAY IPJ
[/BRESET*Q·OJ
THEN [/QOJ
[/BRESET*/QOJ
THEN [QOJ
[/BRESET*Q1*QOJ
THEN [/Q1J
[/BRESET* /Q1 *QO J
THEN [Q1J
[/BRESET*Q2*Q1*QOJ
THEN [/Q2 J
[BRESET*/Q2*Q1*QOJ
THEN [Q2J
[/BRESET*/Q3*Q2*Q1*QOJ
THEN [Q3J
[/BRESET*ARB DELAY QUJ
THEN [ARBITRATE 2J~
[ARBITRATE~2J
[/BRESET*/BSELECT*WONARBJ
THEN [COMPLETE~lJ WITH [CSELECT' ,/ARBITRATE' ,SFCMPL'J
[/BRESET*BSELECTJ
THEN [IDLEJ WITH [/CBUSY' ,/ARBITRATE' ,/SDRVENB' J
IF
---------------- DATA TRANSFER SEQUENCE --------------WHILE
IF
[IDLEJ
[/BRESET*ICBUSY*/ICSELECT*DATA XFER*CTLSCSIJ
THEN [DATA~XFER~lJ WITH [REQUEST'J
[/BRESET*ICBUSY*/ICSELECT*DATA XFER*/CTLSCSIJ
THEN [DATA~XFER-1J WITH IDMAREQ'J
IF
WHILE
IF
IF
WHILE
IF
WHILE
IF
[DATA~XFER 1J
[BRESET*PROTENB*IREQUEST*BACK]
THEN [DATA~XFER~lJ WITH [DMAREQ'J
[/BRESET*PORTENB*DMACYCLEJ
THEN [DATA~XFER~2J WITH [/DMAREQ'J
[DATA~XFER~2J
[/BRESETJ
THEN [DATA~XFER~3J
[DATA~XFER 3J
[/BRESETJ
THEN [DATA~XFER 4J
Figure 4-25.4 PLUS105 SCSI CTL .SEE File (continued)
August 1989
743
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
WHILE
IF
IF
IF
IF
IF
WHILE
IF
[DATA XFER 4]
[/BRESET*PORTENB*/PARERROR*DMACNTO*/CTLSCSI]
THEN [COMPLETE 1] WITH [SFCMPL']
[/BRESET*PORTENB*/PARERROR*SMACNTO*CTLSCSI]
THEN [DATA_XFER_5] WITH [REQUEST']
[/BRESET*PORTENB*/PARERROR*/SMACNTO]
THEN [DATA XFER 1] WITH [REQUEST']
[/BRESET*/PORTENB]
THEN [DATA_XFER_SL] WITH [SFCMPL']
[/BRESET*PORTENB*PARERROR]
THEN [COMPLETE_I] WITH [SFCMPL' ,SPARERR']
[DATA XFER 5]
[/BRESET*IREQUEST*BACK]
THEN [COMPLETE_I] WITH [SFCMPL']
COMMAND COMPLETION SEQUENCE
WHILE
IF
[COMPLETE_l]
[/BRESET*/PORTENB]
THEN [COMPLETE_2] WITH [/SFCMPL' ,/SPARERR']
WHILE
IF
[COMPLETE_2]
[/BRESET*PORTENB]
THEN [IDLE]
WHILE
IF
[IDLE]
[/BRESET*/BSELECT*/ICBUSY*/SFCl*/SFCO]
THEN [IDLE]
Figure 4-25.5 PlUS105 SCSI CTl.SEE File (end)
Augusl1989
744
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
r
GDEVICE TYPE
PLUS1S3
@DRAWING . . . . . . . . . . . . . . . S IG APN88 02
@REVISION . . . . . . . . . . . . . . A
@DATE . . . . . . . . . . . . . . . . . . 8-8-88
@SYMBOL . . . . . . . . . . . . . . . . U3
@COMPANY . . . . . . . . . . . . . . . SIGNETICS
@NAME . . . . . . . . . . . . . . . . . . ASP APPLICATIONS GROUP
@DESCRIPTION . . . . . . . . . . . CSI TARGET CONTROLLER. ARBITRATION/SELECTION LOGIC
@PINLIST
"<--------FUNCTION-------->
"PINLABEL PIN # PIN FCT
SDO
1
I
SD1
SD2
SD3
SD4
SDS
SD6
SD7
8
PARI
9
0
GND
10
OV
PAR2
11
0
IDO
12
ID1
13
ID2
14
A-WONARB
15
0
A-SELECTED 16
0
PARERROR
17
0
GEN-PAR
18
0
REC-PAR
19
VCC
20
+SV
<--REFERENCE-->"
PIN ID
OE CTRL"
10
I1
12
13
14
IS
16
I7
BO
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
VCC
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
Figure 4·26. PLUS153 SCSI ARB Plnllsl
August 1989
745
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@COMMON PRODUCT TERM
MAX-1O-MATCH ~ 101 * 101 * 102 * S07
@I!O DIRECTION
@LOGIC EQUATION
A-SELECTED
* /ID2
100
* II01
* SDl
+ /IDO
ID1
* /ID2
* S02
101
* /ID2
* SD3
+ IDO
* II01
102
* S04
+ /IDO
* 505
ID2
+ IDO
* II01
101
102
* S06
+ lIDO
MAX-IO-MATCH
+
A-WONARB
IDO
* /ID1
* II02
* /502
* /503
* /504
* SOl
/507
+ /IDO
ID1
* /102
* /503
* /504
S02
* /505
ID1
503
* /S04
* /S05
* /SD6
* /102
+ IDO
* II01
* /505
* /506
* /507
102
S04
+ IIOO
* /506
* II01
102
505
* /507
+ IDO
101
102
506
* /S07
+ lIDO
MAX-1O-MATCH
" PARITY GENERATOR ( PARI AND PAR2 ARE PARTIAL TERMS) . "
PARI
SOD
* /501
* /S02
+ /500
501
* /502
* /SOl
+ /SOO
S02
SOl
S02
+ SOD
PAR2
* /505
503
* /S04
504
+ /503
* /sos
* /504
+ /503
sos
S04
SOS
+ S03
GEN-PAR
PARI
* PAR2 * /S06 * /507
+ PARI
*/PAR2
506
* /507
+ PARI
* /PAR2
* /506
507
+ PARI
506
507
* PAR2
+ /PAR1 */PAR2
* /506
* /507
+ /PAR1 * PAR2
506
* /S07
+ /PARI * PAR2
* /S06
507
506
507
+ /PAR1 */PAR2
"PARITY ERROR GENERATOR. ERROR FLAGGED IF RECEIVED PARITY IS DIFFERENT
FROM CALCULATED PARITY."
PARERROR ~ /GEN-PAR * REC-PAR
+ GEN-PAR * /REC-PAR ;
Figure 4-27. PLUS153 SCSI_ARB .BEE File
August 1989
746
* /S05
* /S06 *
* /506
* /507
* /507
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@DEVICE TYPE
PLUSlS3
@DRAWING . . . . . . . . . . . . . . . SIG_APN88_ 02
@REVISION ...........•.. A
@DATE . . . . . . . . . . . . . . . . . . 8-8-88
@SYMBOL ...........•.... US
@COMPANY .........••.•.. SIGNETICS
@NAME .................. ASP APPLICATIONS GROUP
@DESCRIPTION .......•... SCSI TARGET CONTROLLER. REGISTER CONTROL LOGIC
@PINLIST
"<--------FUNCTION-------->
~PINLABEL
PIN # PIN FCT
/DMACYCLE
1
AO
2
Al
/SYSREAD
/SYSSEL
5
DBO
6
DBI
DB2
SDRVENB
I
GND
10
OV
CTLSCSI
11
I
/WRCTRL
12
/0
/RDSTAT
13
/0
/ROOATA
14
/0
IDO
15
0
101
16
0
102
17
0
BUFENBL
18
0
/WROATA
19
/0
VCC
+SV
20
<--REFERENCE-->"
PIN_ID
OE_CTRL"
10
11
12
13
14
IS
16
I7
BO
GND
Bl
B2
B3
B4
BS
B6
B7
B8
B9
VCC
DO
01
D2
D3
04
DS
06
07
D8
09
Figure 4·28. PLUS153 SCSI_DCD Pinlisl
August 1989
747
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@COMMON PRODUCT TERM
@I/O DIRECTION
@LOGIC EQUATION
BUFENBL = SDRVENB
SCSI CONTROLLER REGISTER MAP
IDMACYCLE
CTLSCSI
ISYSSEL
ISYSREAD
Al
AO
H
H
H
H
H
H
L
L
X
X
X
X
X
X
L
L
L
L
L
L
L
H
L
H
L
H
0
0
0
L
H
X
X
X
X
0
0
1
1
X
X
X
X
0
1
1
X
X
FUNCTION
READ STATUS REG.
WRITE CONTROL REG.
DATA BUFFER
- READ
- WRITE
-- NOT VALID -SET TARGET ID
DMA : SCSI -> SYSTEM
DMA : SYSTEM -> SCSI
IRDSTAT
IDMACYCLE * SYSSEL * lAO * IAl * SYSREAD ) ;
IWRCTRL
IDMACYCLE * SYSSEL • lAO * IAl * ISYSREAD ) ;
IRDDATA
IDMACYCLE * SYSSEL * AD * IAl • SYSREAD
+ DMACYCLE * ICTLSCSI ) ;
IWRDATA
I
( IDMACYCLE • SYSSEL • AD ·/Al • ISYSREAD
+ DMACYCLE • CTLSCSI )
IDO-2 ARE THE TARGET ID CODE. THE ID REGISTER IS IMPLEMENTED
IN THE PLUSl53 BY SUPPLYING A SET TERM ( WITH DBO-2 ) AND A
HOLD TERM ( WITH IDO-2 ).
IDO
+ I (
IDl
+ I (
ID2
+ / (
IDMACYCLE
IDMACYCLE
IDMACYCLE
/DMACYCLE
IDMACYCLE
IDMACYCLE
• SYSSEL
• SYSSEL
* SYSSEL
• SYSSEL
* SYSSEL
* SYSSEL
* Al
* ISYSREAD
* DBO
* Al
* Al
* ISYSREAD
* ISYSREAD
*
•
•
•
•
* Al
* ISYSREAD
* Al
* Al
* ISYSREAD
• ISYSREAD
IDO
DBl
IDl
DB2
ID2
Figure 4-29. PLUS153 SCSI_OCD .BEE File
August 1989
748
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
·~ill·~i~'~; s·~
:::
'"
0
:::Ii
~;: ~.., ~~'" ~~,., ~
;!:
!l! ~
1!
'" ~
I!:
1!
... '"
.... '"
I
@o.ll.
-
• • •
Figure 4-30. SCSI Targellnlerface
August 1989
749
Signefics
Programmable Logic Design
and
Application Notes
Programmable Logic Devices
COMMUNICATIONS USING PLDs
PLD devices are particularly appropriate
for digital communications. High speed
sequencers form a natural means of
handshaking and protocol checking,
where PLAs and PALs can decode parallel header information. But, PLDs fill a
need for digital communications-that of
the emerging "standard". Once an initial
specification for a communication protocol is agreed upon, the manufacturers
may generate product to meet the current
specification. This will probably not embody the final specification, but will closely
resemble it. Unfortunately, the penalty for
having to redesign a gate array is relatively high should a communication protocol
be implemented in one and require
change. A PLD solution is an ideal embodiment for a product designed to implement an emerging standard because it
can be changed when the "standard"
changes.
This section covers several examples of
data communication designs from whole
protocols to simple scramblers-along
with a customizable speech synthesis
system using the Philips PCF8200.
Ds
(out)
DsX-B + DsX-7
Ds = D; + DSX_6 + DSX_7
D; = Ds (1 + X_6 + D X_7
Figure 5-1. CCITT V.27 Scrambler
August 1989
750
The CCITT V.27 Scrambler PLC18V8Z
The Radio Shack publication "Understanding Data Communications" contains
a brief description of the CCITI V.27
recommended scrambler for use with
4800bps modems. The logic diagram for
this circuit is aserialcascadeof Dflip-flops
with Exclusive-OR gates tapped in and
out of the data stream. This class of
machines implements transformations
based upon Galois polynomials which are
often described by linear sequential machines (i.e., D-FFs and EX-OR gates).
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Pile NJ.mc:
CCI'!'T V. 27 Scra.mbler
Date:
Time:
10/31/1988
16:17:41
@DEVICE TYPE
PLC18V8Z
@DRAWING
@REVISlON
@DATE
@SYMBOL
@COMPANY
@NAME
@DESCRIPTION
@PINLIST
-c--------FUNCTION-------->
-PINLABEL PIN #
PIN FCT
CLOCK
1
CLK
DIN
I
N/C
N/C
N/C
5
N/C
6
N/C
7
N/C
8
N/C
9
GND
10
OV
ENA
11
fOE
Xl
12
0
X2
13
D
X3
14
D
X4
15
D
X5
16
D
X6
17
D
X7
18
0
DOUT
19
B
VCC
20
+5V
<--REFERENCE-->"
PIN ID
IO/CLK
OE CTRL"
11
12
13
14
15
16
I7
18
GND
19//0E
BO
Bl
B2
B3
B4
B5
B6
B7
VCC
DO
01
D2
D3
D4
D5
D6
07
@COMMON PRODUCT TERM -CPT LABEL ~ (expression)"
@I/O DIRECTION
07 ~ 1 ;
@LOGIC EQUATION
DOOT
X7*/X6*/DIN + /X7*X6*/DIN + X7*X6*DIN + /X7*/X6*DIN
Xl: D
DOOT
X2: D
Xl
X3: 0
X2
X4 : D
X3
X5: D
X4
X6: 0
X5
X7: 0
X6
Figure 5·2. V.27 Scrambler
August 1989
751
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
A Novel Speech Synthesizer PLS159A
The goal of this design was to build a small
board capable of transmitting a variety of verbaI
messages in conjunction with the Philips
PCF8200 speech synthesis part. Judicious
partitioning resulted in a PLS159A acting as a
controller, an HC4040 counter addressing an
EPROM and an EPROM which provides binary
data to the PCF8200.
The PLS159A transacts with the PCF8200
(Busy, etc.) and controls pulsing to the
HC4040. Upon asserting the pushbutton, the
cycle begins and proceeds to advance the
HC4040 in increments 3FF (HEX) consecutive
addresses. Figure 5-6 shows the system in full
detail. The ultimate signal comes from the
6200, and drives an o~mp which delivers the
final signal to the speaker. Various R~ combinations implement filtering and a simple pot
provides the level control.
Programming the EPROM was accomplished
by capturing short messages on audio tape,
downloading to a Philips PCF8200 development system which analyzes and compresses
the data for efficient storage. The result is an
EPROM file which needs 3FF HEX addresses
to store about 10sec of speech.
Figure 5-9 shows the AMAZE state equation
entry file for the PLS159A which handshakes
with the 8200 and 4040 parts.
@DEVICE TYPE
PLS159
@DRAWING
. . . . . . . . . . . . . . . . . . . . . . PLD CONTROLLER FOR PCF8200 SPEECH SYNTHESIZER
@REVISION
....•••.•••••...•••... B
@DATE
. . . . . . . . . . . . . . . . . . . . . . 9/07/88
@SYMBOL
. . . . . . . . . . . . . . . . . . . . . . PLSI59
@COMPANY
. . . . . . . . . . . . . . . . . . . . . . SIGNETICS CORPORATION
@NAME
@DESCRIPTION
This circuit will perform most functions required to achieve a minimum
configuration PCF8200 speech synthesizer system.
REV-A **Original design modified to work in existing ASP demo board. ***
REV-B **Fixed SEE/BEE file to eliminate random quits during utterances
l)Gray code for sequencer.
2)Input latch added on REQ signal from PCF8200 for
synchronization
FUNCTIONS PERFORMED:
1.System Oscillator for sequencer controller
2.Byte update control via EPROM to PCF8200
@PINLIST
"<---------FUNCTION---------> <--REFERENCE-->"
"PINLABEL
PIN # PIN FCT
PIN 10
OE CTRL"
6_MHZ IN
1
CK
CK
REQ
I
10
BUSY
Il
END ADRS
12
N/C
I
13
R C
/B
BO
DO
6 MHZ - OUT
0
Bl
01
START_REQ
I
B2
02
N/C
/B
B3
03
GND
10
OV
GND
N/C
11
JOE
JOE
SVO
12
/0
FO
EA
SVI
13
/0
Fl
EA
SV2
14
/0
F2
EA
N/C
IS
/B
F3
EA
REQLATCH
16
/0
F4
EB
RESET
17
10
F5
EB
COUNT
18
/0
F6
EB
WRITE
19
/0
F7
EB
VCC
+SV
20
VCC
Figure 5·3. PLS159A SPEECHB Pinlisl
August 1989
752
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
I I
@COHHON PRODUCT TERM
@nRVTCE SELECTION
SPEECHB/PLS159
@COMPLEMENT ARRAY
@I!O DIRECTION
DO ~ 6_MHZ_OUT;
@FLIP FLOP CONTROL
FC ~ 1;
"REVISION-B"
@STATE VECTORS
[SV2
SV1
SVO]
@OUTPUT ENABLE
EA ~ 0 ;
EB ~ 0 ;
@REGISTER LOAD
SO
Sl
S2
S3
S4
S5
S6
@A5YNCHRONOU5 PRESET/RESET
@FLIP FLOP MODE
@LOGIC EQUATION
**
OSCILLATOR SECTION
II
6_MHZ_OUT ~ R_C;
R_C ~ /(1)
"LATCH FOR SYNCHRONIZATION
OF PLD AND SPEECH CHIP
CLOCKS"
"CAPTURE OF REQ SIGNAL FROM
PCF8200"
/REQLATCH
K
J
/REQ;
REQ;
Figure 5-4. PLS159A SPEECHB
.BEEFile
000 B'
all B;
101 B'
110 B'
100 B;
010 B'
111 B'
@INPUT VECTORS
@OUTPUT VECTORS
@TRANSITIONS
"Initialization at powerup"
WHILE
WHILE
SO
IF
S6
IF
THEN
Sl
WITH
/RESET', WRITE', COUNT']
THEN
51
WITH
/RESET', WRITE', COUNT']
"Wait for Start switch to be depressed"
WHILE
51 ]
IF [/START_REQ
*
/BUSY] THEN [ S2 ] WITH [/WRITE']
WHILE [ S2
IF
] THEN [ S3 ] WITH [ WRITE' , COUNT']
WHILE [ S3
IF
] THEN [ S4 ] WITH [/COUNT']
WHILE [ S4
IF [REQLATCH] THEN [ S5 ] WITH [/WRITE' ,COUNT']
IF [END_ADRS + /BUSY] THEN [ S6 ] WITH [RESET']
WHILE [ S5 ]
IF [/REQLATCH] THEN [ S3 ] WITH [ WRITE']
Figure 5-5. PLS159A SPEECHB .SEE File
August 1989
753
»
c:
D)'tI ~
~"" illga.
a,0
'"2lc:
l>~
~
'"
"'CD)
"'C3
=3
PLS159A
gD)
~.C"
"CLK01\i
02
RST03
04
OU1
0
05
K
10K
"t
j
OS
09
010
011
"
lir
c:
31 10
~~~~~TI11==========+=======:J
15
14
o
012
iil
S
C
'"f!>
!fJ
~
!
R14¥.'
4 ZK
R6
lK
Yl
6MHz
4.7K
VI
'<
:;.
"
~.
II>
+5V
+5V
~
iD
3
RS
lOOK
lK
-=1
BTl
4 .SV
o
S
C
@}
1D
.8
Zb
o
-
oce
_.
g~14
~
3
0~(I)
+5V
U4
74HCT4040
"C
.8
(1)(')
U)c
(I)
U)
ce'
~
('i.
~
&f
'"
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
CCITT Forward CRC PolynomIal PLUS405
This application illustrates the use of Signetics
PLUS405 in a high speed data communication
application. Typically, larger polynomial encoders permit error checking over larger data
streams than smaller ones. This design implements a sixteenth order polynomial and the figures that follow show the logic equations to
implement it.
File Name : ere gen
Date
10/30/1987
Time: 11:10:56
####################
LABEL
CLK
N/C
N/C
o
N/C
XIl3
XIl4
XIl5
XIl6
X016
X015
X014
X013
GND
**
PIN
LIS T
FNC **PIN----------- PIN
CK ** 1-1
1-28
2-1
1-27
3-1
1-26
4-1
P
1-25
5-1
L
1-24
6-1
U
1-23
I
7-1
S
1-22
I
** 8- I
4
1-21
** 9-1
0
1-20
** 10-1
5
1-19
0
o ** 11-1
1-18
o
12-1
1-17
o ** 13-1
1-16
OV
14-1
1-15
File Name : ere gen
Date
10/30/1987
Time: 11:11:2
@DEVICE TYPE
PLUS405
@DRAWING
@REVISION
@DATE
@SYMBOL
@COMPANY
@NAME
@DESCRIPTION
This design implements the eRe-celTT forward polynomial with a PLUS405.
eRe-ceITT
GF(X)
~
forward polynomial is
I + X'5 + X'12 + X'16
NOTE: Since this polynomial requires a 16-bit shift register together
with an array of exclusive-OR's the contents of the 8 output flip-flops
must be fed back into the array via the input pins of the PLUS405.
Bits 1 to 8 are formed with the 8-bit internal register while the
remaining B-bits are made out of the 8-bit output register the outputs
of which are externally fed back to inputs XI9 through XI16.
@INTERNAL FLIP FLOP LABELS
Xl, X2, X3, X4, XS, X6, X7, X8
@COMMON PRODUCT TERM
@COMPLEMENT ARRAY
@BURIED REGISTER CLOCK
@INIT/OE
RESET ~
RO, R1, R2, R3, R4, R5, R6, R7,
RB, R9, RIO, R11, R12, R13, R14, R15 ;
Figure 5-8. PLUS405 Design File
August 1989
755
LABEL
VCC
I
G
**
Figure 5·7. PLUS405 PinUst
The
FNC
+5V
INT
o
o
o
o
N/C
N/C
N/C
XIl2
XIll
XIlO
XI9
RESET
X09
X010
X011
X012
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@LOGIC EQUATION
u
*************************************************************
Xl : INPUT ~ (D XOR XIl6) * G
~ (/D * XIl6 * G) + ( D * /XIl6 * G); "*
*************************************************************
Xl : J
K
X2
J
K
X3
J
K
X4
J
K
X5
J
K
~
(D * /XIl6 * G)
/G + (D * XIl6)
+ (/D * XI16 * G)
+ (/D * /XIl6)
Xl
/XI
X2
/X2
X3
/X3
X4
/X4
*************************************************************
X6 : INPUT ~ X5 XOR (( D XOR XIl6 ) * G ) ; "
*************************************************************
X6 : J
K
X'I
J
K
X8
J
K
X09 :J
K
XOIO:J
K
XOll :J
K
(/G * X5) + (/D * X5 * XIl6) + (D * X5 * XIl6)
(G * D * /X5 * /XIl6) + (G * /D * /X5 * XIl6) ;
(/G * /X5) + (D * /X5 * XII6) + (/D * /X5 * /XII6)
(G * D * X5 * /XIl6) + (G * /D * X5 * XIl6) ;
+
X6
/X6
X7
/X7
X8
/X8
XI9
/XI9
XIlO
/XIIO
XOI2:J
XIlI
/XIlI
*************************************************************
Xl3 : INPUT ~ Xl2 XOR (( D XOR XIl6 ) * G ) ; "
*************************************************************
K
u
XOl3
:
J
K
XOl4
J
K
XOl5
J
K
XOl6
J
K
(/G * XII2) + (/D * XII2 * XII6)
(G * D * /XIl2 * /XII6) + (G */D
(/G * XII2) + (D * /XII2 * XII6)
(G * D * XIl2 * /XIl6) + (G * /D
+
*
+
*
(D * XIl2 * XIl6)
+
/XIl2 * XIl6) ;
(/D * /XII2 * /XII6)+
XIl2 * XIl6) ;
XII3
/XIl3;
XIl4 ;
/XIl4;
XIl5 ;
/XII5;
Figure 5-9 PLUS405 logic Equations
August 1989
756
Signetics
Programmable Logic Design
and
Application Notes
Programmable Logic Devices
INSTRUMENTATION
Instrumentation typically involves the
measurement and often the display of
physical world parameters. Digital systems are particularly effective in this area
and as usual, are largely limited only by
the designer's imagination. This section
describes three distinct examples of instrumentation provided from customer interaction.
The lastdesign involves implementing the
sweep circuitry for an oscilloscope. This
can be extended and modified for similar
designs.
Another example is a pulse width monitor
which can be used in controlling power
pulses, radio strength or radar/sonar timing measurements.
The first example shows several parts being used to make a plethysmographic
monitor (i.e., heart rate). This has straightforward medical and health applications.
The beauty of PLD solutions to these
problems is simple -they are readily modifiable for adaption for another end use.
The oscilloscope circuit could be altered
for a laser light show. The pulse width
monitor could pick up a timing pulse from
Figure 6·1. Heart Beat Monitor System Diagram
August 1989
757
a disk and the plethysmographic system
could be configured for animals rather
than humans.
Heart Beat Monitor - PLS159A,
PLS168A and PLS153
PLDs can be used as powerful building
blocks in implementing the digital portion
of a low cost portable heart beat monitor.
This monitor is capable of displaying the
heart beat in pulses per minute. Figure 6-1
shows the system block diagram. The digital portion is inside the dashed lines.
Signetics Programmable Logic Devices
Programmable logic Design
and Application Notes
Operation
A transducer generates the heart beat pulses
which are amplified and filtered. A level detector (one-shot) converts the amplified signals to
TTL level signals. A 15 second timer is used to
count the number of pulses in fifteen seconds.
The number is multiplied by four to approximate
the number of pulses in sixty seconds. A binary
to BCD converter is used to display the result.
A start switch resets the system and initiates
the count.
techniques include optical plethysmography,
ultrasonic flow measurement, piezoelectric
pickup of peripheral arterial pulse, Korotkofl
sounds, and recording the ECG.
filter with a gain of 20, and a frequency response of 1-200 Hz. Figure 6-3 shows the circuit diagram of the amplifier/filter stage.
Light plethysmography is used as the transducerin this design. The Tektronix light plethysmograph (Figure 6-2), operates by measuring the
reflectance of skin to red light. As blood flows
into the skin's capillary bed with each heart
beat, the reflectance changes and this change
is amplified and observed.
The amplified signal is fed through the 'Level
Detector' stage to create a square wave. A
Schmilt-Trigger is used to generate the square
wave. Application Note 18 in the Signetics PLD
Data Manual explains the implementation of
the Schmitt-Trigger in detail. A P LS153 is used
to create the Schmitt Trigger. The PLS153 also
holds the glue logic and other functions for the
system explained further in this article (see Figure6-4).
Transducer
There are several techniques to monitor the
blood flow in the peripheral system. These
r----------,
I
I
I
PHOTb
RESISTOR
i~
I
I
I
I
I
I
iI
I
Amplifier/Filter
Signetics SA 741 OP--amp is used as bandpass
Level Detector PLS153
TO AMPLIFIER!
FILTER SECTION
O.28/J.F
lOOK
r---JVIII.----l
400 OHM
~'7
LED
311lF
~I~--+-~
I
!
L----------.:L-=
i
1-
=
BLACK SHIELD
Figure 6·2. Tektronix Plethysmograph as Transducer
Figure 6·3. Amplifier/Filter Slage
~
K
HEART_BT_IN
HEART_BT_OUT
16K
Figure 6-4. SCHMITT-TRIGGER Diagram
August 1989
n.2BK
10KOHM
758
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@DEVICE TYPE
PLS153
@DRAWING
@REVISION
@DATE
@SYMBOL
@COMPANY
@NAME
@DESCRIPTION
@PINLIST
"(---------FUNCTION--------->
"PINLABEL
PIN #
PIN FCT
SET
1
I
RST
2
HEART BT IN
3
15 SEC
N/C
N/C
N/C
N/C
8
N/C
9
B
GND
10
OV
RESET
11
0
NTRESET
12
0
NO_HRT_BT
13
0
HEART BT OUT 14
0
BT IN_15_SEC 15
0
N/C
16
B
N/C
17
B
N/C
18
B
N/C
19
B
VCC
+5V
20
~II
15 SEC TIMER
(PLS168A)
CLOCK INPUT
330 ohms
Figure 6-7. Clock Input for the PLS168
(--REFERENCE-->"
PIN ID OE CTRL"
10
Il
12
13
14
IS
16
I
/
/
'"
I
I
I7
BO
GND
Bl
B2
B3
B4
B5
B6
B7
B8
B9
VCC
I
,,"---- .....
I
I
\
\
DO
Dl
D2
D3
D4
D5
D6
D7
D8
D9
\
\
,
',....""-
STlIRT/COUNT_END
--
..-'
Figure 6-8. State Transition Diagram
Figure 6-5. HTBT_153 Plnlist
@COMMON PRODUCT TERM
@I/O DIRECTION
@LOGIC EQUATION
"Level Detector (Schmitt Trigger)"
HEART BT OUT
HEART_BT_IN;
"Debouncer"
RESET
/SET + /NTRESET;
NTRESET
/RESET + /RST;
"15 Second Timer ANDed with the output of the
Level Detector"
BT IN 15 SEC
15_SEC * HEART_BT_OUT;
1.OK
OUT
1.OK
+5V
Figure 6-6. HTBT_153 .BEE File
Fifteen Second Timer
To create a fifteen second timer, a counter can
be constructed with the PLS 16BA such that the
number of counts is equivalent to 15 seconds.
To achieve this, the 60Hz signal from the power
line is passed through a transformer and a halfwave rectifier to create the clock input to the
PLSI68A (see Figure 6-7).
The number of counts needed to create the 15
August 1989
Figure 6-9. Circuit Diagram of Debouncer
second time interval is calculated in the following manner:
15 seconds = 15 X 60 (cycles/seconds) = 900
where '60' is the 60Hz clock input to the
PLSl66A.
Figure 6-8 shows the state transition diagram
759
for the counter. Figure 6-10 is the timing diagram to generate the number of pulses in 15 seconds.
The reset switch is used to initiate the count
This switch is debounced using the PLS153 of
Figure 6-4. Figure 6-9 shows the circuit diagram of the debouncer. The design equations
for the debouncer are shown as part of the design equation files of Figure 6.s.
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
If n = number of registers with feedback, then
an n-bit counter can be created with any of
Signetics sequencers using only n+ 1 terms.
CLOCK
60Hz
START /
COUNT_END
HEART
BEAT
PULSE
Table 6-1 shows the implementation of the 15
second timer in the PLS168A. Input variable 10
is the in put from the reset switch and' 15 _ SE C'
is the Count_End signal. At the 900th count
(terms 12 & 13; HHHLLLLHLL), output'Q' goes
to a logic low, indicating that the end of the
count has been reached.
'/
~I
JlJUlJLJ1
n n n U n l,t
INPUTTO
PULSE
----.J U U
COUNTER
~I...___
NUMBER OF PULSES
IN 15 SECONDS
Figure 6-10. PLS168 Timing Diagram
Cust/Project
Rev/I. D.
PLS168A
-15 Second Timer with Reset
T
E
OPTION PIE
!
!L!
!----~------------------------------------------------------------------
! !
INPUT VARIABLE
PRESENT STATE
NEXT STATE
!OUTPUT !
M !e!l 1 -------------------------------------------------------------------! !1 a 987 6 5 4 3 2 1 0!9 8 7 6 5 432 1 a!
!3 2 1 a!
01. !-,- - - -,- - - H!- -,-,- - - L!
!- H'
11.!- - - -,- - - -,- - - H!
-,-,- - L H! -- - - - - - H!
H L!21.)-,- - - -,- - - H!- -,- H L L! -,- L H H!- - - H!
3!.1- - - -,- - - -,- - - H!- -,- - - -,L H H H!- H!
- -,H L L L!
4! • ! -, - - - -, - - - H! - -, - - - L, H H H H!- - - - - H,L L L L1- - - H!
5! . ! -, - - - -, - - - H! - -, - - L H, H H H H!- - - - H L,L L L L!H'
6!.!-,----,H!- - - L H H,H H H H!- - - H L L,L L L L!H!
7!.!- , - - - H ! - -,L H H H,H H H H!- -,H L L L,L L L L!H!
8!.1-,- , - - - H ! - L,H H H 11, H H H H!- H,L L L L,L L L L1H!
91.!- - - -,- - - -,- - - HIL H,H H H H,B H H H!H L,L L L L,L L L L!- - - H!
101.!- , - - - - , - - - H I H H,H H H H,H H H H!L L,L L L L,L L L L1- - - H!
11! . !- - - -,- - - -,- - - Ll- -,- - - -,- -1L L,L L L L,L L L L1H!
12 !A!- - - -,- - - -,- - - LIH H,H L L L,L H L L1L L,L - - -,- L - -,- - - H!
-,- - - -,13!A! - H!H H,H L L L,L H L L!H H,H L L L,L H L L!- - - L!
14! !
15! !
16! !
17! !
18! !
R
191
20!
1
!
,
" ,
*****************************************************************************
43!A!
44!A!
45!A!
46 !A!
47!A!
R
E
~
S
E
T
E
C
Table 6-1. PLS168A Program Table
August 1989
760
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Each line (or term) in Table 6-1 is part of the
-_..._.:.:TO::.;CLOCK
OSCILLATOR
RESET
LOAD
IL
_ _L-------------
2
1
021
2
5
2
2
6
(TIME)
(DETECT POINTS)
00
SIG * SIGINDLY * lAIN
10 US
I(SIGIN)* CNT
(MODE) (ST)
QQQQQQQ
Q
1198765
43210
Q
Q
Q
Q
(Fl FO P9 P8 P7 P6 P5 P4 P3 P2 Pl PO)
START
P
LLLLLLLLL
L
L
L
~
25
TEsT
P
LLLLLLLHH
L
L
H
256
ALARM
P
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
L
L
L
H
L
L
105 US
(SIGIN)
*
CNT
~
155 US
(SIGIN)
* CNT
~
388
ALARM
P
L
208 US
(SIGIN) * CNT
~
520
ALARM
P
LLHLLLLLHLLL
261 US
(SIGIN) * CNT
~
653
ALARM
P
L
L
H
L
H
L
L
L
H
H
L
H
314 US
(SIGIN)
* CNT
~
785
ALARM
P
L
L
H
H
L
L
L
H
L
L
L
H
367 US
(SIGIN) * CNT
~
918
ALARM
P
L
L
H
H
H
L
L
H
L
H
H
L
420 US
(SIGIN)
*
CNT
~
1050
ALARM
P
LHLLLLL
H
L
H
L
473 US
(SIGIN)
* CNT
~
1182
ALARM
P
LHLLHLLHH
H
H
L
526 US
(SIGIN)
* CNT
~
1315
ALARM
P
L
L
L
L
H
H
579
us
(SIGIN)
* CNT
~
1448
ALARM
P
LHLHHLHLH
L
L
L
H
L
H
L
H
L
632
us
(SIGIN)
* CNT
~
1580
ALARM
P
L
H
H
L
L
L
H
L
H
H
L
L
685
us
(SIGIN)
* CNT
~
1712
ALARM
P
L
H
H
L
H
L
H
H
L
L
L
L
738
us
(SIGIN)
* CNT
~
1845
ALARM
P
L
H
H
H
L
L
H
H
L
H
L
H
791 Us
(SIGIN)
* CNT
~
1978
ALARM
P
L
H
H
H
H
L
H
H
H
L
H
L
us
(SIGIN)
* CNT
~
2110
ALARM
P
H
L
L
L
L
L
H
H
H
H
H
L
897 Us
(SIGIN)
* CNT
~
2243
ALARM
P
H
L
L
L
H
H
L
L
L
L
H
L
955 Us
(NORMAL)* CNT
NORMAL
P
H
L
L
H
H
L
H
L
L
L
H
H
844
~
2387
-------------------END NORMAL SIGNAL MODE CHECK AND TIME OUT---------------
Figure 6-14.2 PLS168/BCA TRFDECT .BEE File (continued)
August 1989
765
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
----------------------------BEGIN TEST MODE CHECK-------------------------1.578 MS
JUMP
TEST
N
HHHHLHH
L
H
L
L
H
1.582 MS
(SIGIN)
* CNT = 3957
ALARM
P
H
H
H
H
L
H
H
H
L
H
L
H
1.588 MS
(SIGIN)
*
ALARM
P
H
H
H
H
H
L
L
L
L
L
H
L
1.592 MS
(SIGIN)
*
H
L
1.597 MS
(SIGIN)
H
L
1. 602 MS
(SIGIN)
1. 607 MS
(SIGIN)
* CNT
1. 612 MS
(SIGIN)
1. 617 MS
CNT
=
3945
CNT
~
CNT
=
3982
ALARM
P
HHHHHLLLH
H
* CNT
=
3994
ALARM
P
H
H
H
H
H
L
L
H
L
* CNT
=
4006
ALARM
H
H
H
H
H
L
H
L
L
H
H
L
4019
ALARM
P
HHHHHLH
H
L
L
H
H
* CNT = 4032
ALARM
P
HHHHHHLLLLLL
ALARM
P
HHHHHHL
H
=
3970
(SIGIN)
* CNT =
1. 622 MS
(SIGIN)
*
4057
ALARM
1. 627 MS
(SIGIN)
* CNT = 4069
1. 632 MS
(SIGIN)
1.636 MS
(SIGIN)
H
L
H
H
L
L
P
H
L
H
H
L
L
H
ALARM
P
HHHHHHH
L
L
H
L
H
* CNT = 4082
ALARM
P
H
H
H
H
H
H
H
H
L
L
H
L
*
ALARM
P
H
H
H
H
H
H
H
H
H
L
H
L
CNT
CNT
=
=
4044
4090
H
H
H
H
----------------------------END TEST MODE CHECK---------------------------IF THE (SIGIN) INPUT IS NEGATED BEFORE THE ELAPSED TIME OF 105 US THE COUNTER CONTINUES TO COUNT
UNTIL THE ELAPSED TIME OF 955 MS. AT THIS POINT THE COUNTER AGAIN RESETS ITSELF UNTIL THE NEXT
(SIGIN) INPUT REQUEST.
DURING TEST MODE, THE SEQUENCER SAMPLES THE SIGIN PULSE AT A REPETITION RATE OF 72 US. WITH A
PULSE WIDTH OF 6.5 US. THE TIME OUT FOR AN ALARM DETECT IS BASED ON SAMPLE A CHECK ONCE EVERY
US, APTER THE 10 US SAMPLE FOR SIGIN NEGATION.
END
Figure 6-14.3 PLS168/BCA TRFDECT .BEE File (end)
August 1989
766
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@PINLIST
"C---------FUNCTION--------->
"PINLABEL
PIN #
PIN FeT
e~
1
cr
SIGIN
N/e
SIGDLYIN
AIN
IA1
lAO
FAD
o
FA1
o
SIGDLYOUT
10
o
ALARM
o
11
GND
12
OV
N/C
13
o
N/c
14
o
N/C
15
o
N/C
16
o
IDE
17
PR
N/e
18
N/e
19
N/C
20
N/C
21
N/C
22
N/C
23
vee
24
+5V
<--REFERENCE-->~
PIN 10
CK
IS
14
DE CTRL"
13
12
11
10
FO
F1
F2
F3
GND
PO
PI
P2
P3
IDE
IDE
IDE
IDE
IDE
IDE
IDE
IDE
PRIIOE
III
no
19
18
17
16
vee
Figure 6-15. PLS168iBCA TRFDECT Pinlist
File Name : TRFDECT
Date
9/14/1988
Time: 13:24:44
Cust/Project
Date
- 4/4/1988
RevlI. D.
PLS168
OPTION PiE
!L!
T
!
E
!--------------------------------------------------------------------------
!OUTPUT !
! !
INPUT VARIABLE
PRESENT STATE
NEXT STATE
M !C!1 1 -------------------------------------------------------------------! !1- 0- 9- 8 - 7- 6- 5- 4- 3 - 2- 1 - O!9 - 8- 7- 6- 5- 4- 3- 2 - 1 - 0!9 - 8- 7 - 6- 5 - 4- 3 - 2 - 1 - 0!3 2 1 O!
OfA!- - - -,- - H -,L L - -!- -,- - - -,- - - -!L L,L L L L,L L L L!- H - -!
-,- - - -,H - - -!- -,- - - -,- - - L!- -,- - - -,l! . !H!- - - -!
2!.!- - - -,- - - -,H - - -!- -,- - - -,- - L Hl- -,- - - -,- - H L!- - - -!
3!.!- - - -,- - - -,H - - -!- -,- - - -,- L H H!- -,- - - -,- H L L!- - - -!
4!.!-,- - - -,H - - -!- -,- - - -,L H H H!- -,- - - -,H L L L!- - - -!
5!.!- - - -,- - - -,H - - -!- -,- - - L,H H H H!- -,- - - H,L L L L!- - - -!
6! • ! - - - -, - - - -, H - - -! - -, - - L H, H H H H! - -, - - H L, L L L L! - - - -!
7!.!- - - -,- - - -,H - - -!- -,- L H H,H H H H!- -,- H L L,L L L L!- -!
8! • ! - - - -, - - - -, H
-! - -, L H H H, H H H H! - -, H L L L, L L L L! - - - -!
9! • ! - - - -, - - - -, H - - - 1 - L, H H H H, H H H H! - H, L L L L, L L L L! - - - -!
10!.!- - - -,- - - -,H - - -!L H,H H H H,H H H H!H L,L L L L,L L L L!- - - -)
11!.!- - - -,~ - - -,H - - L!H H,H H H H,H H H H1L L,L L L L,L L L L!- - - H!
12!.!- - - -,-,H - L H1H H,H H H H,H H H H!L L,L L L L,L L L L!- - H L!
13!.!
-,- - - -,H - H H!H H,H H H H,H H H H!L L,L L L L,L L L 1!L L L L!
_1 _ _ _ _ 1
- -!- -,- - - -,14! . ! - - - -,-,- -,- - - -,-
R
Table 6-3.1 Transmitter Fault Detector Program Table (continued)
August 1989
767
Signetics Programmable logic Devices
Programmable Logic Design
and Application Notes
15!A!16!A!17!Al18!A!19!Al201AI21!A!22!A!23!A!24!Al25!A!26!Al27!A!28!A!29!A!30!Al31!AI321A!33!A!34!A!35!A!36!A!37IA!38!A!39!A!40!A!411A!42!A!43!A!44!A!45!AI461-!47!-!-
-
-
- - - -
-
-
-
-
-
-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-
-
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-
-,H L
-,H L
-,H H
-,H L
-,H L
-,H L
-fH L
-fH L
-,H L
-,H L
-fH L
-fH L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,H L
-,- -,- -
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
-
L!L
L!L
L!H
L!L
L!L
L!L
L!H
L!H
L!H
L1H
HIL
H!L
H!L
HIL
HIH
H!H
HIH
HIH
L!L
L!L
L!L
H!H
H!H
HIH
HIH
HIH
HIH
HIH
HIH
HIll
H!H
-!-
!- -,-
-
N N N N N N S N
A I
/
I A A
/
/ /
/
/ I /
L,H
H,H
L,L
L,H
L,L
H,H
L,L
L,H
HfL
H,H
L,L
L,H
H,L
H,H
L,L
L,H
H,L
H,H
L,L
H,L
H,L
H,L
H,H
H,H
H,H
H,H
H,H
H,H
H,H
lI,H
H,H
-,-
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
L
H
H
H
H
-
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
H
H
L
L
L
H
H
L
L
L
H
-
H,H
H,L
L,L
L,L
H,H
L,L
L,H
L,H
H,L
H/L
H,H
H,H
L,L
L,H
L,H
H,L
H,L
H,H
H,H
H,L
H,H
H,L
L,L
L,H
H,H
L,L
H,L
L,L
L,H
H,H
L,L
-,-, -
I
H
L
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
H
H
H
L
1
L
L
-
HiL H,L L L
H!L L,L L L
L!L L,L L L
L1L H,L L L
HlH HfL H H
L!L H,L L L
L!L H,L L L
H!L H,L L L
HIL H,L L L
L!L H,L L L
L!L H,L L L
L1L H,L L L
HIL H,L L L
L!L H,L L L
L!L H,L L L
L!L H,L L L
HIL H,L L L
L!L H,L L L
LIL H,L L L
HIL H,L L L
HIL H,L L L
H!L H,L L L
L!L H,L L L
LIL H,L L L
L!L H,L L L
LIL H,L L L
H!L H,L L L
L!L H,L L L
L!L H,L L L
H!L H,L L L
H!L H,L L L
-!- -,-
N N N N
/ /
C C C C C C G C G N 1
I
D
N
H
L
H
L
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
L
L
H
L
H
L
H
L
L
H
L
H
-
/ /
C C C C
L,L
L,L
L,L
L,L
L,H
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
L,L
1,1
L,L
L,L
-,-, -
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L L1H - L L!
L L!L L L L!
L L!L L L L!
L L!H - L L!
L H!- - H HI
L L!H - L L!
L L!H - L L!
L L!H - L L!
L LlH - L L!
L L!H - L L!
L L!H - L L!
L L!H - L L!
L LIH - L L!
L L!H - L Ll
L L!H - L L!
L LIH - L L!
L LIH - L L!
L LIH - L L!
L L!H - L Ll
L LIH - L L!
L L!H - L Ll
L L!H - L L!
L L'H - L L!
L L'H - L LI
L L'H - L LI
L L!H - L L!
L L!H - L L!
L LIH - L Ll
L LIH - L 1!
L L!H - L Ll
L L!H - L L!
--!----!
- -J- - - -J
NNNNASFF
/ / / / L
A A
CCCCAGIO
R D
L
M L
Y
Y
a
u
N
Table 6-3.2 Transmitter Fault Detector Program Table (end)
August 1989
768
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Scope Trace Sweep Circuit PLS153 and PLS155
Jerry Uebler submitted this spectrum analyzer
sweep circuit design.
@DEVICE TYPE
PLS153
@DRAWING
1
@REVISION
1
@DATE
1-27-88
@SYMBOL
@COMPANY
Tektronix Inc.
@NAME
sweep logic
@DESCRIPTION
This chip forms the sweep logic circuit for the 2710
spectrum analyzer.
@PINLIST
"<---------FUNCTION---------) <--REFERENCE-->H
'PINLABEL
PIN #
PIN FCT
PIN 10
OE CTRL H
EOSWP1
I
10
TRIGIN
2
11
SLOPE
3
12
AUTOTRIG13
SSTRIG
5
14
SINGLSWP
6
IS
MANSWP16
SGDIS
I
17
HOLDOFF
B
BO
DO
GND
10
OV
GND
RSFFI2
11
0
Bl
Dl
RSFF11
12
0
B2
D2
SGDFFI
13
0
B3
D3
SSFOOO
14
0
B4
04
SSOFFI
15
0
B5
05
STIN
16
I
B6
06
STOUT
17
0
B7
D7
SWPGATE18
B
B8
08
SWPGATEO
19
0
B9
D9
vce
20
+5V
vce
Figure 6-16. PLS153 SWP PlnUsl
August 1989
769
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
@COMMON PRODUCT TERM
SWPTRIG~/(EOSWP)+/((STOUT*/STIN)+/AUTOTRIG-)+/SSDFFO+/RSFFI2;
@I10 DIRECTION
DO~RSFFI2;
D8~/SWPGATE*/SGDIS;
@LOGIC EQUATION
RSFFI2~(EOSWP-
)*/RSFFIl;
RSFFll~/HOLDOFF*/RSFFI2;
SWPGATE ~ SGDFFI*/SWPTRIG + /MANSWP- + SWPGATE*(EOSWP- )*SWPTRIG;
SWPGATE- ~O;
SGDFFI~ SWPTRIG+/MANSWP-+(/SWPTRIG*(EOSWP- )*SGDFFI);
HOLD OFF ~ 0;
STOUT~((TRIGIN*/SLOPE)+(/TRIGIN*SLOPE));
SSDFFO~
SSDFFI~
SSDFFI*SSTRIG+/SINGLSWP+(EOSWP- )*/SSTRIG*SSDFFO;
/SSTRIG+/SINGLSWP+(EOSWP- )*SSTRIG*SSDFFI;
Figure 6·17. PLS153 SWP .BEE File
@DEVICE TYPE
PLS155
@DRAWING
@REVISION
@DATE
@SYMBOL
@COMPANY
@NAME
@DESCRIPTION
@PINLIST
"c---------FUNCTION---------> C--REFERENCE-->"
"PINLABEL
PIN #
OE CTRL"
PIN FCT
PIN ID
HCLOCK
1
CK
CK
VSYNC
2
10
ENDVSWP
3
11
VIDMON
4
12
TC5
I
13
VIDMaN6
BO
DO
a
PEa
Bl
Dl
VMTST
B2
D2
FMVIDB3
D3
GND
10
OV
GND
N/C
11
/OE
/OE
SWPGATE
12
B
B4
D4
BLANK
13
0
D5
B5
QBAR
14
/0
FO
EA
STO
15
/0
Fl
EA
STI
16
/0
EB
F2
TRIGGER
/0
17
F3
EB
HsaUT
18
a
D6
B6
HSIN
19
B7
D7
VCC
+5V
20
VCC
Figure 6-18. PLS155 SWP3 Pinlisl
August 1989
770
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
I
~,
I
II
@COMMON PRODUCT 'rJ
"PINLABEL
CLK
OIR
N/C
N/C
N/C
2PHA
2PHB
2PHC
2PHO
GNO
N/C
IPHA
IPHB
lQ
2Q
N/C
N/C
IPHC
IPHO
VCC
PIN # PIN_FCT
1
CK
2
I
0
0
0
0
10
11
12
OV
fOE
0
13
a
14
IS
16
17
18
19
20
/0
/0
/B
/B
0
a
+SV
<--REFERENCE-->"
PIN 10
OE~CTRL"
CK
10
11
12
13
BO
DO
Bl
01
B2
02
B3
03
GNO
/OE
B4
04
BS
05
FO
EA
Fl
EA
F2
EB
F3
EB
B6
06
B7
07
VCC
Figure 7·2. PLS155 STEP Pinlisl
August 1989
773
Signetics Programmable logic Devices
Programmable Logic Design
and Application Notes
@COMMON PRODUCT TERM
@COMPLEMENT ARRAY
@I/O DIRECTION
dO-I;
dl~l;
d2~1;
d3~1;
d4~1;
d5~1;
d6~1;
d7~1;
@FLIP FLOP CONTROL
@OUTPUT ENABLE
ea==O;
@REGISTER LOAD
la ~O;
@ASYNCHRONOUS PRESET/RESET
ra~/I;
@FLIP FLOP MODE
rnl
~
1; rnO
@LOGIC
Iphd
Iphc ~
Iphb ~
Ipha
2phd
2phc
2phb
2pha
12q:j
k
/lq:j
k
~
1;
EQUATION
lq*2q;
2q* /lq;
/2q*/lq;
/2q* /lq;
(lq*2q)*(2q+lq)+(/lq+/2q)*(/2q*/lq)
(2q*/lq)*(/lq+/2q)+(/2q+lq)*(lq*2q)
(/2q*lq) *(/2q+lq)+(2q+/lq) *(2q*/lq)
(/2q*/lq) *(2q+/lq) +(2q+lq) * (/2q*lq)
Idir*/lq+lq*dir;
Idir*/lq+lq*dir;
1;
1;
Figure 7·3. PLS155 STEP .BEE File
U48
7 7473
J
0
9
5
J
10
0
12
elK
0- 13
2
~JL.-/7488-,-3_~ 2PHA
6
8
Figure 7-4. Stepper Motor logic Diagram
August 1989
774
20
Signeties Programmable Logie Devices
Programmable Logic Design
and Application Notes
File Name : STEP
Date : 9/14/1988
ReV/I. D.
PLS155
!FF TYPE! EB EA !
POLARITY
!-------!-------1-----------------------1
!H:H:H:H:H:H:H:H!
!A:A:.:.10
T
E
!------------------------------------------------------------------
I Q (p)
I Q (n)
! P ! R !
B(O)
! !
B (I)
M !Cl---------------------------------------!B!A1B!Al---------------1
R
---! ! 3 2 1
O!A!- - l!A!21A!-
O! 7 6 5 4 3 2 1 O! 3 2 1 O! 3 2 1 O!.
-1- -,- - - -!- - L L10 0 - -1.
-!----,----!--LH100--!.
-1-,- - -, - - 3 !A!- - - -!4 !Al- - - -!- - - -,- - -,- - 51A!6!Al-
-1- -
-
-,- -
-
-1- - H L ! O Q - - !
-!- - H HlD 0 - -1
-!- - - H!O 00 -!
-!- - - L!O 0 a -!.
-1-
-
-
-10
a -
01.
.!.
• 17 6 5 4 3 2 1 O!
.!A
.,A A
.!
.!.A
AA.!
.!.
A
A A!
A,A
.! .
.! .
.! .
.1.
A!
7!A!O a 0 010 0 0 0,0 0 0 010 0 0 010 0 0 OlA A A A!A A A A,A A A A!
**********************************************************************
**********************************************************************
31!0!0 a a O!O 0,0 0 a O!O 0,0 a 0 O!O a a a!A A A A!A A A A,A A A A!
Fc!a!O a a O!O 0,0 0 a O!O 0,0 0 0 a!
Lb!.!O 0 a O!O 0,0 a a O!O 0,0 a a O!
La!.!O a 0 O!O 0,0 a 0 O!O 0,0 0 0 a!
D7!-!-1- -,- - - -to 0,0 0 0 O!
D6!.!- - - -!- -,- - - -!- -,- - - - !
05!-!- - - -!- -,- - - -!- -,- - - -!
D4!.!- - - - ! - -,- - - - ! - -,- 03!-!- - - -1- -,- - - -!- -,- - - -!
02!-!- - - -!- -,-!- -, - !
D1!-1- - - - ! - -,- - - - ! - -,- - 001.!- - - -!- -,- - - -!- -,-
-,
NNND
/ / I
NN21NN21
P P P P P P P P / / Q Q /
CCCRHHHHHHHHCC
DCBADCBA
/ Q Q
CC
P P P P P P P P
H H H H H H H H
DCBADCBA
Table 7·1. STEPPER CONTROL Program Table
+20V
vee
R1
R4700HMS
D1
DIODE
R2
R560HMS
~
DIODE
01
NPN
DIODE
NOTES:
D1. D2 ARE 1N4001
01 IS A 2N2222
0215 A 2N30SS
D31SABY127
Figure 7·5. STEPPER CONTROL Power Buffer
August 1989
775
Programmable Logic Design
and
Application Notes
Signetics
Programmable Logic Devices
SECURITY SYSTEMS Nell Kellet
A Programmable Alarm System PLS168
Security systems are typified by some
sensing circuit (perceiving intrusion, fire,
etc.) and some basic activation circuit.
Simple logic or complex sequences may
be used with the sensors orthe alarm generation circuits. Two of the following solutions utilize the innate capability of CMOS
EPLDs to work well with RC timing circuits
in generating time delays and relaxation
oscillators.
This design illustrates an expansion of the
design using additional PLS153 devices
which were deleted in this version for
brevity.
A basic alarm controller can be considered as a black box with several inputs
and several outputs (Figure 8-1). Some inputs are used for detection and others for
CLOCK
ARM
CON-{
TROL
INPUTS
RESET
RRE
PREATAK
TIMED 1
TIMED 2
DETECT
INPUTS
ALARM 1
ALARM 2
ALARM 3
SOUNDER
ALARM
BEACON
}
CONTROLLER
r---.
0
0
f------'
}
ALARM 3
Figure 8·1. Basic Alarm Controller
August 1989
ALARM
OUTPUTS
776
STATUS
INDICATOR
control. Detect inputs are driven from a variety of alarm transducers such as reed
switches, smoke detectors, pressure
mats, etc. An ARMinput switches the system into a state which allows detection of
the various alarm conditions and a RESETinput is used to reset the system after
an alarm has been triggered and dealt with
oron re-entering the protected area. Outputs from the system include a sounder, a
beacon and status indicators.
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
_I'~atakl
~N1JlI.
sounder ---(~
ST._ N.U.L
.L. "\..
arm.reseV
~ arm.lIr9.perata
sounaer
fire/
sounaer
arm.reseVsoun
r-04---- fire/sounde'------------(
~:~resev
~nder
~~~~:E~::::::;t== alarm
1·lIr9/sounaer
alarm 2·lIr9/sounaer
...
alarm 3·lIr9/sounaer
======::::!(--~--
TOST_NULL
I
arm.rese~
sounder
TOST_NULL
TOST NULL
Figure 8-2. State Diagram for the Alarm Controller
Detect inputs can be divided into timed, untimed, lire and personal attack inputs. Timed
circuits allow entry/exit delay circuits for front
and rear doors, to delay operation of the alarm
for approximately 16 seconds. Untimed circuits
cause the alarm to operate immediately when
an alarm condition occurs. These would be
used to protect unusual means of entry, such as
windows. Both the timed and untimed circuits
should operate only if the system is armed.
Figure 8-2 the controller can be in one of six
possible states. Examine the transitions from
ST_NULL as an example. If a personal attack
orfireconditionoccurswhile in this state, a transition to ST_1 takes place as indicated by the
arrows on the diagram. Also at this time the
sounder and beacon are activated, thus giving
the alarm. If the fire and personal attack conditions have not occurred and the ARMSWITCH
is set, then a transition to ST_ takes place.
The personal attack circuit is a special case untimed circuit and should operate only when the
system is disarmed. The fire-detect circuit is
again a special case untimed circuit and should
operate regardless of whether the system is
armed or not
Similarly, other arrows on the state diagram
represent transitions between other states
when specified input conditions occur. Output
parameters are shown to the right of the slash
line. Where there are no output parameters
specified in a transition term, this indicates that
no output changes are desired during this transition. Thatis, an output will hold its present value until told to change.
Outputs from the controller drive an external
sounder and beacon. Alter 128 seconds, the
sounder should turn off if the alarm has been
triggered by either a timed or general untimed
circuit However, when a fire or personal attack
triggers the system, the sounder should not
turn off until the system is reset and the alarm
condition removed.
State Machine Implementation
This design is best implemented as a state machine. The state diagram is derived from the
vorbal system description. Please note from
August 1989
a
PLD Implementation
Having defined the desired system operation it
is now time to select the required device to implement the desired system function from the
PLD Data Manual. In this case, the device selected is the PLS 168. Figure 8-3 shows the pinning information for the alarm controller. A
1O-bit counter within the controller produces
the entry/exit and sounder turn-<>ffdelays since
this makes more efficient use of the PLD facili-
777
ties than implementing the delays as part of the
state machine. This counter uses seven internal registers with feedback and three without
For those registers without feedback, external
wiring feeds their outputs back into the device
to complete the 20-bit counter. Pins five to ten
are used for this purpose. OutputT7 also forms
part of the counter.
Three other registers form the state registers
and are labeled SRO, SR 1 and BEACON. State
vectors for these registers have to be chosen
with care to ensure thatthe beacon output isactivated at the correct time. Other inputs and outputs are as already discussed. Note that the
PRiOE pin isnot used. This pin must be tied to
ground in the final circuit
Once the pin information has been entered, any
Boolean equations desired can be defined using the Boolean equation entry (.BEE) file of
AMAZE. List 1 shows the .BEE file for the alarm
controlier. Any internal registers used in either
the Boolean equation or state equation entry
file are given names in this file, in this case 1 to
16. Equations for the 10-bit counter are entered after the title line @LOGIC EQUATION,
using registers t1 to t1Oin. Register SRO halts
and clears the counter while the controlier is in
certain states. This needs to be considered
when defining the state vectors.
Signetics Programmable logic Devices
Programmable Logic Design
and Application Notes
State Equation Entry
The state equation enlly (.SEE) file of AMAZE
uses a state-transition language, parameters
of which are taken directly from the state diagram. Information is entared into this file in a
free format. The only points to remember are
that the square brackets should be used
throughout to define the state registers and
transitions, semicolons should be used to mark
the end of vector definition and apostrophes
should be used to indicate a registered output.
State vectors can be defined in the state equation enlly file as shown in Ust 2. State vectors
are simply a means of labeling an arrangement
of state registers which can be used later to define state transitions. Becausewe are using the
BEACON output register as a state registar
also and SAO is being used to halt and clear the
1O-bitcounter, particular care must be taken in
defining the state vectors in this instance.
From the state diagram,thecountarmustbegin
counting during states ST_O, ST_2and ST_3
and it must be cleared during states ST_1,
ST 4 and ST NUll. State ST_NULL represents the po~r-op state of the PLS168 in
which all register outputs are at logic one. Thus
the inactive state of the counter is defined as
being when SRO is at logic one, therefore, SRO
must be at this level during states ST.., 1 and
ST 4and at logic zero during other states. The
ala-;m beacon is considered to be active by an
active--low signal and must be activated during
states ST_3 and ST_4. Register SRI must
therefore be chosen to ensure mutual exclusiv-
ity between state vectors. Input and output ~
tors can be defined in the same manner In
terms of input and output label names. In this
case, however,the label names are used direedy. State transitions can now be derived direcdy from the state diagram. This is done using
a Pascal...Jike state transition language and can
clearly be seen in Table 8-1. Note that multiple
IF statements can be implemented as such or
as CASE statements as shown. Enlly/exit and
sounder tum-off delay times are represented
as a decoding of the lO-bit counter states.
Thus to get the desired 16 second enlly/exit
delay. t7 must be decoded and to achieve the
128 second sounder tum-off delay nOin must
be decoded.
STATE MACHINE AND TIMER FOR BURGLAR ALARM
@INTERNAL SR FLIP FLOP LABELS
t6 t5 t4 t3 t2 tl
@LOGIC EQUATION
tl: s
/tl*/srO ;
r
tl*/srO
+ srO
t2 s
tl*/t2*/srO
r
tl* t2*/srO
+ srO
t3 s
tl* t2*/t3*/srO
r = tl* t2* t3*/srO
srO
+
t4 s
tl* t2* t3*/t4*/srO
r = tl* t2* t3* t4*/srO
+ srO
tS s
t1* t2* t3* t4*/t5*/srO
r
tl* t2* t3* t4* t5*/srO
+ srO
t6 s
t1* t2* t3* t4* t5 * /t 6* / srO
r
tl* t2* t3* t4* t5* t6*/srO
+ srO
t7 s
tl* t2* t3* t4* t5* t6*/t7*/srO
r ~ t1* t2* t3* t4* t5* t6* t7*/srO
+ srO
t8 s = t1* t2* t3* t4* t5* t6* t7*/t8*/srO
r
t1* t2* t3* t4* t5* t6* t7* t8*/srO
+ srO
t9 s = tl* t2* t3* t4* t5* t6* t7* t8*/t9*/srO
r ~ t1* t2* t3* t4* t5* t6* t7* t8* t9*/srO
+ srO
s
tlO
tl* t2* t3* t4* t5* t6* t7* t8* t9*/tlO*/srO
r
tl* t2* t3* t4* t5* t6* t7* t8* t9* tlO*/srO
+ srO
~
~
~
~
~
~
~
~
~
~
~
~
(Can be used lat"er to define state equations)
Table 8-1. Logic Equations
August 1989
778
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
I
I
1
I
1--,
1
PLS168
,.........._ _ _----'.,1
CK
""""'''''-----''-1
1
I
I
+5V t-<-'''------''-'....
1
-L...jl
.J...LJUILL._ _ _
.J...LJL.I..---_ _-C...! 0
......_ _ _ _-02..1 0
..u;)._ _ _ _-=-I 0
PR
.................'"'--_--'-"--1 0
...........---J..<....j
1-'-'-----"-........
0 .......'--_ _ _.LlI>J
0 .......'--_ _-..;~
0 !-'""'--_ _........J..L
0 1-'-'"'--_--'-..............
OV
Figure 8·3. Pinning Information for the Alarm Controller
--~-----1~----~-----------------------t--------~---+V
HC132
1K
1K
PLS168
Clock
Beacon
13
Sounder 11
3300
Arm
Reset
Peratak
Fire
T8in
T9in
T10in
T10
T9
T8
1K
Figure 8-4. Alarm System based on the PLS168
With the system fully defined, simply assemble
the design information -during the AMAZE
assembler to produce the fuse pattern for the
desired device, Should any design changes
meed to be made to a device, the fuse pattern
may be modified directly using the program
table editor of AMAZE, However, taking this
August 1989
action is not recommended since Boolean
equation and state equation files are notaltered
correspondingly.
Functioning 01 the device can be verified with
the AMAZE simulator, which can also be used
779
to check A,C, timings before downloading the
pattern to a device programmer, such as Stag
ZL30A or Data 1/0 29B, to program the device.
Test vectors are produced either automatically
or interactively by the simulator.
Signetics Programmable Logic Devices
Programmable Logic Design
and Application Notes
Programmability
The PLS 168 device could now be used as the
controller of an alarm system. As it stands, the
device assumes that all the alarm inputs indicate an alarm condition when in the high state,
logic one, and that the alarms are activated
when the alarm outputs are active low (i.e., at
logic zero).
Should an alarm input transducer be used
which indicates an alarm condition as a low
state, this can be catered for by altering the
.SEE file. For example, consider a smoke detector which outputs logic zero on detection of
an alarm condition and assume that this transducer is driving the "fire" input of the device. By
changing all references to 'fire' in the .SEE file
to '/fire' and all instances of '/fire' to 'fire' then
the activation of the alarms will occur when Iog-
System Implementation
sounder tulTH)lI delays. These delays can be
modified either by changing the external oscillator circuit or by decoding a different internal
counter state. For example, to increase the entry/exit delay change all references to t7 in the
.SEE file to lB. Both normally-<:Iosed and normally-open loop implementations are shown.
Due to the distances involved in an alarm system, the open-loop configuration may cause
problems, being driven by the positive supply.
to avoid this problem, input-.='-"":"'='-"""--:--::\7.77)
J L ' 0 2 3 (.58)-AAITI EID@f.Q1O (.254)
.015 (.38)
853~05B4
@I
81594
January 1990
790
NOTES:
1. Controlling dimension: inches. Millimeters are shown in
parentheses.
2. Dimensions and tolerancing per ANSI Y14.5M - 1982.
3. "T", "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal fine, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #20 when viewed from the top.
Signetics Programmable Logic Devices
Package Outlines
24-PIN CERAMIC DUAL-IN-LiNE WITH QUARTZ WINDOW
II-~~~
.030 (.76)
NuTES:
1
J L 0 2 3 (.58)-i+t Tt EtO@j.010 (.254)
.015 (.38)
1. Controlling dimension: inches. Millimeters are shown in
parentheses.
2. Dimensions and tolsrancing per ANSI Y14.5M - 1982.
3. "T", "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #20 when viewed from the top .
.035 (.89)
jr
'02:JL('61i
It
~15 (.38)
@t
.010 (25)
Li
-j
.300ssc
(7.62)
(NOTE 4)
.395 (lo.oS)
.SOO (7.62)
853-0586 84000
28-PIN CERAMIC DUAL-IN-LiNE WITH QUARTZ WINDOW
NOTES:
1. Controlling dimension: inches. Millimeters afe shown in
parentheses.
2. Dimensions and tolerancing per ANSI Y14.5M - 1982.
3 "T", "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #24 when viewed from the top .
.598 (15.19)
=-"==;__
~==,""",""'''''''=-=,",7<:''''-=""",,"",,"7<==,"",,,"~--=rS06)
l.-,. 'M' =
.o.~_-rJ
________ 1'~5(S7.72)-------------J
'if 'if 'if 'if 'if I
1.440 (36.58)
l~::::: ~I
m------
,
.
225 (572) mal(
I~
~'19)
~
125,(318)
JL""-"! "~""
.015 (.38)
-!Ii' I,
~
I-
""'
"'
.600 (15.24) sse
(NOTE 4)
.695 (17.65)
.600 (15.24)
853-0589 84000
January 1990
. 620 (15.75)=1
590 (14.99)
(NOTE 4)
145 IS 68)
791
Signetics Programmable Logic Devices
Package Outlines
CERAMIC LEADED CHIP CARRIER WITH QUARTZ WINDOW
TYPICAL 8 J N9JC VALUES (oCiWJ
NO. OF LEADS
PACKAGE CODE
DESCRIPTION
Average 8 JA
Average 8 JC
68
LA
965mil-wide
55
25
68-PIN CERAMIC LEADED CHIP CARRIER WITH QUARTZ WINDOW
r----~~SQ.
1~""Ii(24.5118Q'
1 I '''(23)5)~
:l5 ("'4)
0
.15 CUI, 45 X
~
t.
.1
'I •
-
,•
I
..
..osa
(1.27) TYP.
asc
I
I
NOTES:
1. Controlling dimensions: inches. Millimeters are shown in
parenthesis.
2. Dimension and toleracing per ANSI Y14.5M·1982.
.810(20.57)
i
;;m'l1!!!lJll1lmm!Illlm1i;'?'"
3. When a window lid is used, the overall package
thickness must increase by a minimum of .010 inch
(O.25mm) and a maximum of .040 inch (1.020mm).
.025 (U4) MIN.
.. ~ r ....
..
I
-~--I--I-
,
d
r
r.790(20.071
I
"1-/
•
-
"'11r - .DaliI2"S)
.085 (1.65)
-----j
r m..
.086 (2.18)
(,.88j
LSI 853·1240 95007
January 1990
792
Signetics Programmable Logic Devices
Package Outlines
PLASTIC DIP
1. Package dimensions conform to JEDEC
specification MS-001--AA for standard
Plastic Duallnline (DIP) package.
2. Controlling dimensions are given in inches
with dimensions in millimeters, mm, contained in parentheses.
3. Dimensions and tolerancing per ANSI
Y14.5M - 1982.
4. "T", "D" and "E" are reference datums on the
molded body and do not include mold flash
or protrusions. Mold flash ·or protrusions
shall not exceed 0.01 inch (0.25mm) on any
side.
5. These dimensions measured with the leads
voltage drop of a calibrated diode to measure the change in junction temperature
due to a known power application. Testconditions for these values are:
constrained to be perpendicular to plane T.
6. Pin numbers start with pin #1 and continue
counterclockwise when viewed from the
top.
Test Ambient-Still Air
7. Lead material: Olin 194 (Copper Alloy) or
equivalent, solder dipped.
Test Fixture--
9JA-
TeXlcol ZIF socket
with 0.04" stand-
off
8. Body material: Plastic (Epoxy).
9JC- Water cooled heat
9. Thermal resistance values are determined
by Temperature Sensitive Parameter (TSP)
method. This method uses the forward
sink
PLASTIC DUAL"IN-L1NE PACKAGES
TYPICAL 9JA/9 JC VALUES (0C/W)
NO, OF LEADS
PACKAGE CODE
DESCRIPTION
20
N
Cu. Lead Frame
300mil-wide
63
27
24
N
Cu. Lead Frame
300mil-wide
56
26
28
N
Cu. Lead Frame
600mil-wide
46
18
28
N3
Cu. Lead Frame
300mil-wide
53
24
Average
9JA
Average
9JC
20-PIN PLASTIC DUAL-IN-L1NE (N PACKAGE)
o
.004
NOTES,
.10
1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEOEC specification
MS-001-AE for standard dual in-tine (DIP) package .300
inch row spacing (PLASTIC) 20 leads (issue B. 7/85)
3. Dimensions and tolerancing per ANSI Y14. 5M-1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin #20 when viewed from the top .
. 100 (2.54)
ssc
F-DO~--~~-------- 1.0~(U.6~
1.045 (U.54)
.064 (1.63)
.045 (1.14)
~-------------------,~
.160 (4.06)
PLANE
~
JL022
(.56)
.017 (.43)
.035 (.89)
.020 (.51)
.120 (3.05)
1+1T1EloOOl. .o10 (.25) 81
.010 (.25 )
853·0408 B1234
January 1990
.015 (.38)
793
~ij
--ILfl
5i)
BSC
.300 (7.62)
(NOTE 5)
.395 (10.03)
.300 ( 7.62)
Signetics Programmable Logic Devices
Package Outlines
24-PIN PLASTIC DUAL-IN-LiNE (N PACKAGE)
, 'NOTES
1. Controlling dimension: inches. Melnc are shown in
parenthesis.
Package dimensions conform to JEDEC specification
MS-001-AF for standard dual in-line (DIP) package .300 inch
row spacing (plastic) 24 leads (issue B, 7;85)
3 Dimension and lolerancing per ANSI Y14. 5M-1982
4. r: ''0': AND "E" are reference datums on the molded body
and do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010 inch (.2Smm) on any Side
5 These dimensions measured with the leads constrained to be
perpendicular to plane T
6 Pin numbers start with pin #1 and continue counterclockwise
to pin #24 when viewed from the top
2
"
a~'~(4'70)
.~
I-T-]-SEATING
PLANE
18
3 221(7.62)
.300
•.
(NOTE 5)
A
t"
1
~'-
,.160(4.06)
Jl
.138(3.51)
~:::
®~~~V~.;j ~
,120 (3.05)
56
.02.2,
lEI-'- ___
0 '"
.017(.43)1 I"'IT
WL ____
w.
)b
C··
.045 (1.14)
1.01.
(.25) r9.1
------
.015 (.38)
.010 (.25)
.'
,;\
0. 155 (3.94)
B~]"
.14513.68)
.300 (7.62)
NOTE 5
.395 (10.03)
.300 ( 7.62)
28-PIN PLASTIC DUAL-IN-LiNE (N PACKAGE)
l.tD®!
.004 (.10j
I
NOTES,
1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS·Oll·AB for standard dual in·line (DIP) package .600
inch row spacing (PLASTIC) 28 leads (issue B. 7/85)
3. Dimensions and tOlerancing per ANSI Y14. 5M·1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin #28 when viewed from the top .
.560 (14.22)
~
.155 (3.&4)
.145(3.68)
'04511'~4)
ii
~
.138 (3.51)
:: ~::!
.120 (3.05)
1+ITIEIDll>! .010 C.2$)
OIJ I
~
.010 (.25)
853·0413 84099
January 1990
794
\\
1--.800 (15.24) BSC------l
(NOTE 5)
~
.600 (15.24)
I
Signeties Programmable Logie Devices
Package Outlines
28-PIN PLASTIC DUAL-IN-LiNE (N3 PACKAGE)
NOTES:
1. Controlling dimensions: inches, Metnc are
shown in parentheses
2 Dimensions are tolerancing per ANSI
1 1D ® 1·004 (.10) 1
YI4.5M-1982
"T", "0", and "E" are reference datums on the
molded body and do not include mold-flash
or protrusions which shall nol exooed .010
Inch (.25 mm) on any side
4 These dimensions measured with the leads
constrained to be perpendicular to plane "T"
5 Pin numbers start with #1 and continue
counterclockwise to pin #28 when viewed
from the lop
3
--------~:~ :~~::--------I
.320 (8.13)
300(7.621
(NOTE 5)
f
.045 (1.14)
020 ( 51)
.OI51~
010 (25) _ _ _ _
853-0864 89398
January 1990
A(~j'
300
fl62)
sse
(NOTE 5)
J"
.395 (1.0031
300 ( 762)
NOl
795
Signefics
Programmable Logic Devices
Section 11
Sales Offices,
Representatives &
Distributors
Sales Offices,
Representatives &
Distributors
Signefics
Programmable Logic Devices
SIGNETICS
HEADQUARTERS
Toms River
Phone: (201) 505-1200
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, CA 94088-3409
Phone: (408) 991-2000
NEW YORK
Wa~~lngers Falls
one: (914) 297-4074
ALABAMA
Huntsville
Phone: (205) 830-4001
ARIZONA
Phoenix
Phone: (602) 968-5777
CALIFORNIA
Calabasas
Phone: (818) 880-6304
Irvine
Phone: (714) 833-8980
(714) 752-2780
Los Angeles
Phone: (213) 670-1101
NORTH CAROLINA
Raleigh
Phone: (919) 781-1900
OHIO
Columbus
Phone: (614) 888-7143
Da~ton
hone: (513) 294-7340
OREGON
Beaverton
Phone: (503) 627-0110
PENNSYLVANIA
Plymouth Meetln~
Phone: (215) 8 5-4404
FLORIDA
Oviedo
Conley and Assoc., Inc.
Phone: (407) 365-3283
OHIO
Centerville
Bear Marketing, Inc.
Phone: (513) 436-206t
ILLINOIS
Hoffman Estates
Micro-Tex. Inc.
Phone: (708) 382-3001
Richfield
Bear Marketing, Inc.
Phone: (216) 659-3131
INDIANA
Indianapolis
Mohrfield Marketing, Inc.
Phone: (317) 546-6969
IOWA
Cedar Rapids
J.R. Sales
Phone: (319) 393-2232
MARYLAND
Columbia
Third Wave Solutions, Inc.
Phone: (301) 290-5990
TENNESSEE
Greeneville
Phone: (615) 639-0251
MINNESOTA
Eden Prairie
High Technology Sales
Phone: (612) 944-7274
Sunnyvale
Phone: (408) 991-3737
TEXAS
Austin
Phone: (512) 339-9944
COLORADO
Aurora
Phone: (303) 751-5011
Houston
Phone: (713) 668-1989
MISSOURI
Bridgeton
Centech, Inc.
Phone: (314) 291-4230
San Diego
Phone: (619) 560-0242
GEORGIA
Atlanta
Phone: (404) 594-1392
ILLINOIS
Itasca
Phone: (312) 250-0050
Richardson
Phone: (214) 644-3500
CANADA
SIGNETICS CANADA, LTD.
Etobicoke, Ontario
Phone: (416) 626-6676
INDIANA
Kokomo
Phone: (317) 459-5355
Nepean, Ontario
Phone: (613) 225-5467
MASSACHUSETTS
Westford
Phone: (508) 692-6211
REPRESENTATIVES
MICHIGAN
Farmington Hills
Phone: (313) 553-6070
NEW JERSEY
parSlppanr:
Phone: 201) 334-4405
December 1989
Raytown
Centech, Inc.
Phone: (816) 358-8100
NEW MEXICO
Albuquerque
F.P. Sales
Phone: (505) 345-5553
NEW YORK
Ithaca
Bob Dean, Inc.
Phone: (607) 257-1111
OREGON
Beaverton
Western Technical Sales
Phone: (503) 644-8860
PENNSYLVANIA
Pittsbur~h
Bear arketin~, Inc.
Phone: (412) 31-2002
Hatboro
Delta Technical Sales, Inc.
Phone: (215) 975-0600
UTAH
Salt Lake City
Electrodyne
Phone: (801) 264-8050
WASHINGTON
Bellevue
Western Technical Sales
Phone: (206) 641-3900
Spokane
Western Technical Sales
Phone: (509) 922-7600
WISCONSIN
Waukesha
Micro-Tex, Inc.
Phone: (414) 542-5352
CANADA
Burnaby, B.C.
Tech-Trek, Ltd.
Phone: (604) 439-1373
Misslssauga, Ontario
Tech-Trek, Ltd.
Phone: (416) 238-0366
Ne~ean, Ontario
ARIZONA
Scottsdale
Thom Luke Sales, Inc.
Phone: (602) 941-1901
Rockville Centre
S-J Associates
Phone: (516) 536-4242
Wa~ln8ers Falls
bean, Inc.
Phone: (914) 297-6406
Ville SI. Laurent, Quebec
Tech-Trek, Ltd.
Phone: (514) 337-7540
CALIFORNIA
Folsom
Webster Associates
Phone: (916) 989-0843
NORTH CAROLINA
Smithfield
ADI
Phone: (919) 934-8136
PUERTO RICO
Santurce
Mectronics Sales, Inc.
Phone: (809) 728-3280
799
ech-Trek, Ltd.
Phone: (613) 225-5161
Signetics Programmable logic Devices
Sales Offices, Representatives & Distributors
DISTRIBUTORS
Contact one of our
local distributors:
Anthem Electronics
Falcon Electronics, Inc.
Gerber Electronics
Hamilton/Avnet Electronics
Marshall Industries
Schweber Electronics
Wyle/LEMG
Zentronics, Ltd.
FOR SIGNETICS
PRODUCTS
WORLDWIDE:
ARGENTINA
Philips Argentina S.A.
Buenos Aires
Phone: 54-1-541-4261
AUSTRALIA
DENMARK
Philips Components AIS
Copenhagen S
Phone: 45-1-54-11-33
FINLAND
SPAIN
FRANCE
MALAYSIA
SWEDEN
R.T.C. Compelec
Issy-Ies-Moulineaux
Cedex
Phone: 33-1-40-93-80-00
Philips Malaysia SON
Bernhad
Kuala lumpur
Phone: 60-3-734-5511
Philips Components A.B.
Stockholm
Phone: 46-8-782-1 0-00
GERMANY
MEXICO
Valvo
Hamburg
Phone: 49-40-3-296-0
Philips Components
Guadalajara, Jal
Phone: 52-36-52-27-70
GREECE
Philips S.A. Hellenique
Athens
Phone: 30-1-4894-339
AUSTRIA
INDIA
BELGIUM
BRAZIL
Philips 00 Brasil, Llda.
Sao Paulo
Phone: 55-11-211-2600
CHILE
Philips Chilena S.A.
Santiago
Phone: 56-02-077-3816
CHINA,
PEOPLES REPUBLIC OF
Philips Hong Kong, LId.
Kwai Chung, Kowloon
Phone: 852-0-424-5121
COLUMBIA
Iprelenso, Llda.
Bogota
Phone: 57-1-2497624
December 1989
SA Philips (PTY), Ltd.
Randburg
Phone: 27-11-889-3911
Philips Industries, Ltd.
Seoul
Phone: 82-2-794-5011
/2/3/4/5
HONG KONG
S.A. MBlE Components
Brussels
Phone: 32-2-525-61-11
KOREA
SOUTH AFRICA
Oy Philips Ab
Espoo
Phone: 358-0-502-61
Philips Electronic
Components & Mat'! LId.
Artarmon, N.S.W.
Phone: 61-2-439-3322
Osterrlchlsche Philips
Wien
Phone: 43-222-60-1 01-820
Philips Components Japan
Tokyo
Phone: 81-3-740-5028
Philips Hong Kong, ltd.
Kwai Chung, Kowloon
Phone: 852-0-424-5121
Pelco Electronics
& Elect. Ltd,
Bombay
Phone: 91-22-493-0311
INDONESIA
P,T. Philir.s.Ralin
Electron cs
Jakarta Selatan
Phone: 62-21-517-795
IRELAND
Philips Electrical Ltd.
Dublin
Phone: 353-1-69-33-55
ISRAEL
Rapac Electronics, Ltd.
Tel Aviv
Phone: 972-3-477115
ITALY
Philips S.p.A.
Milano
Phone: 38-2-67-52-1
JAPAN
Philips Components Japan
Osaka-Shl
Phone: 81-6-389-7722
Mexico, D.F.
Phone: 52-721-64-984
NETHERLANDS
Philips Nederland
Eindhoven
Phone: 31-40-783-749
NEW ZEALAND
Philips New Zealand LId.
Auckland
Phone: 64-9-605-914
NORWAY
Norsk AlS Philips
Oslo
Phone: 47-2-68-02-00
PERU
Cadesa
San Isidro
Phone: 51-14-707-080
PHILIPPINES
Philips Industrial Dev., Inc.
Makati Metro Manila
Phone: 63-2-810-01-61
PORTUGAL
Philips Portuguesa SA
Lisbon
Phone: 351-1-68-31-21
SINGAPORE
Philips Singapore
Pte., LId.
Singapore
Phone: 65-350-2000
800
Copresa S.A.
Barcelona
Phone: 34-3-301-63-12
SWITZERLAND
Philips Components A.G.
Zuerich
Phone: 41-1-488-2211
TAIWAN
Philips Taiwan, Ltd.
Taipei
Phone: 886-2-509-7666
THAILAND
Philips Electrical Co.
of Thailand LId.
Bangkok
Phone: 66-2-223-63309
TURKEY
Turk Philips
Tlcaret A.S.
Istanbul
Phone: 90-1-179-27-70
UNITED KINGDOM
Philips Components
london
Phone: 44-1-580-6633
UNITED STATES
Signetics
Sunnyvale, California
Phone: (408) 991-2000
URUGUAY
Luzllectron S.A.
Montevideo
Phone: 598-91-56-41/
42143/44
VENEZUELA
Magnetica S.A.
Caracas
Phone: 58-2-241-7509
11128189
Philips Components -
a worldwide Group of Companies
Al'gentin..: PHILIPS ARGENTINA S.A. Div. Components, Vedis
3892, 1430 BUENOS AIRES. Tel. (01) 541 -7'''' to 77"7.
Auat,.I.: PHILIPS COMPONENTS PTY Ltd . 11 Waltham Street.
ARTARMON, N.S.w. 2064, TEL. (02) 4393322.
Au_: OSTERREICHISCHE PHILIPS INDUSTRIE G.m .b.H., UB
Bauelemente, Triester Str. 64. 1101 WIEN. Tel. (0222) 60 101-820.
"Igium: N.V. PHILIPS PROF. SYSTEMS-Components Div., 80
Rue Des Deux Gares, 8 - 1070 BRUXELLES, Tel . (02) 5256111 .
....zll: CONSTANTA-IBRAPE; (Active Devices) : Av. Brigadeiro
Faria Uma, 1135-SAO PAULO-SP, Tel. 10'1' 21 ' -2600.
Portupl: PHILlPS .PORTUGESAS .A .R.L.,.Av. Eng. Duarte
Pacheeo 6, iOO9l1SBOACodex, Tel. (019) 683121 .
Sinppore: PHILIPS PROJECT DEV. (Singapore) PTE LTD.,
Components Div ., Lorong 1, Toa Payoh, SINGAPORE 1231 ,
Tel. 3502000 .
Sp.in: PHILIPS Components, Balmes 22, 08007 BARCELONA,
Tel. (03) 3016312.
Sw....n: PHILIPS Components, A .B., Tegeluddsvagen 1, S-11584
STOCKHOLM , Tel. (0)8-7821000.
Switz.....nd: PHILIPS A .G., Components Dept., Allmendstrasse
140-142, CH-8027 ZURICH, Tel. (01) 4882211.
Taiwan: PHILIPS TAIWAN LTD., 150 Tun Hua North Road, P.O.
Box 22918, TAIPEI, Taiwan, Tel. (02) 7120500.
TluIi"nd: PHILIPS ELECTRICAL CO. OF THAILAND LTO. , 283
Silom Road , P.O. Box961 , BANGKOK, Tel. (02) 233-6330-9.
Turkey: TURK PHILIPS TICARET AS., Philips Components,
Talatpasa Cad, No. 5, 80640 LEVENT/ISTANBUL,
Tel. (01) 1792770.
United Kingdom: PHILIPS COMPONENTS LTD ., Mullard House,
Torrington Place , LONDON WCle 7HD, Tel. (0115806633.
United Stet. .: IC Products:
CONSTANTA IBRAPE; (Passive Devices & Materials): Av.
Francisco Monteiro, 702 - RIBEIRAO PIRES·SP.
Tel. 1011 ) 459-8211 .
c.uda: For Ie Products Refer to United States
Chile: PHILIPS CHILENA S.A., Av. Santa Maria 0760. SANTIAGO,
Tel. (02) 773816.
Colombia: IND. PHILIPS DE COLOMBIA S.A., c/o IPRELENSO
LTO., C,a. 21 , No 56-17 BOGOTA, D.E., Tel. (01) 2497624.
Denmerk: PHILIPS COMPONENTS AIS. Prags Boulevard BO,
PB1919, DK-23oo COPENHAGEN S, Tel. 01 -54113.
Finland: PHILIPS COMPONENTS, Sinikaliontie 3, SF-2630 ESPOO
HELSINKI 10, Tel. 358-0-50261 .
Fr.nce: RTC-COMPELEC, 117 Quai du President Roosevelt, 92134
ISSY-LES-MOULINEAUX Cedex, Tel. (01) 40938000.
GennIIny (Fed. Republic): VALVO, UB Baulementeder Philips
G.m.b.H., Valvo Haus, Burchardstrasse 19, 0 ·2 HAMBURG 1.
Tel. (040) 3296-0.
Greece: PHILIPS HELLENIQUE S.A., Components Division , No. 15,
25th March Street, GR 17178 TAVROS,
Tel. (01) 4894339/ 4894911 .
Hong Kong: PHILIPS HONG KONG LTD., Components Div ., 15/F
Philips Ind. Bldg ., 24·28 Kung Yip St., KWAI CHUNG,
Tel. (0)-245121 .
India: PEICO ELECTRONICS & ELECTR)CALS LTO., Components
Dept., Band Box Building, 254-0 Dr. Annie Besant Rd ., BOMBAY
- 400025, Tel. (022) 492021 114930590.
Indonea..: P.T. PHILlPS-RALIN ELECTRONICS, Components Div.,
Setiabudi II Building , 6th FI., Jalan H.R. Rasuna Said (P.O. Box
223/KBYI Kuningan, JAKARTA 12910, Tel. (021) 517995.
......nd: PHILIPS ELECTRONICS (IRELAND) LTD., Componen ts
Division, Newstead, Clongskeagh, DUBLIN 14, Tel. (01) 693355.
tt.1y: PHILIPS S.p.A ., Philips Components, Piazza IV Novembre 3,
1-20124 MILANO, Tel. (02) 67521 .
~~n: NIHON PHILIPS CORP., Shuwa Sinagawa Bldg., 26--33
Takanawa 3-chome, Minato-ku, TOKYO (l08), Tel. (03) 448·5611 .
(IC Products) SIGNETICS JAPAN LTD., 8-7 Sanbancho
Chiyoda-ku, TOKYO 102, Tel . (03) 230-1521 .
K ..... (Republic of): PHILIPS ELECTRONICS IKOREA) LTO.,
Elcoma Div., Philips House, 260·199 Itaewon-dong, Yongsan-ku,
SEOUL, Tel. (02) 794-5011 .
M ...y " : PHLIPS MALAYSIA SON BHD, Components Div. 3Jalan
SS1512ASUBANG, 47500 PETALING JAYA, Tel. (02) 7345511 .
M •• ico: ELECTRONICA, S.A. deC.V., Carr. Mexico-Toluca km .
62.5, TOLUCA, Edo. de Mexico 50140,
Tel. Toluca 91 (721) 613-00.
Neth........: PHILIPS NEDERLAND, Marktgroep Philips
Components, Postbus 90050, 5600 PB EINDHOVEN ,
Tel. (040) 783749.
New
nd: PHILIPS NEW ZEALAND LTD., Components
Division, 110 Mt. Eden Road, C.P.O. Box 1041 , AUCKLAND,
Tel. (09) 605-914.
Norw.y: NORSK A/S PHILIPS, Philips Components, Box 1,
Manglerud 0612, OSLO, Tel. (02) 680200.
P.kiaun: PHILIPS ELECTRICAL CO. OF PAKISTAN LTD>, Philips
Markaz, M .A . Jinnah Rd ., KARACHI-3, Tel . (021) 725772 .
Pwu: CADESA, Av. Pardoy Aliaga No. 695, 6th Floor, San Isidro,
LIMA 27, TeI.I014P07080.
Philippi ....: PHILIPS INDUSTRIAL DEV. INC., 22-«) Pasong Tamo,
P.O. Box911 , Makati Comm . Centre, MAKATI-RIZAL3116,
Tel . (02) 868951 to 59.
The information presented in this document does not form part of
any quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be accepted
by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent - or
industrial or intellectual property rights.
11/ 16/89
98-7001 -230
e Copyright 1989 NAPe
PHIUPS COMPONENTS-SIGNETICS
811 East ArquesAvenue
Sunnyvale, CA 94088·3409
Tel. (408) 991 -2000
Discrete Semiconductors. Passive Components,
Materials, and Professional Components:
PHIUPS COMPONENTS-DISCRETE
PRODUCTS DIVISION
2001 West Blue Heron Boulevard
Riviera Beach, FL. 33404
Tel. (305) 881 -3200
Color Picture Tubes - Monochrome and Color
Display Tubes:
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P.O. Box 963
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Tel. (313) 996-9400
UrugUlly: LUZILECTRON S.A ., Avda Uruguay 1287, P.O. Box 907 ,
MONTEVIDEO, Tel. (02) 985395.
V ..........: IND. VENEZOLANAS PHILIPS S.A. , c/o MAGNETICA
S.A ., Calle 6, Ed Las Tres Jotas, App. Post. 78117, CARACAS,
Tel. (02) 2393931 .
For all other countri. . apply to: Philips Components Division,
International Business Relations, P.O. Box 218, 5600 MD
EINDHOVEN , The Netherlands, Telex 35000 phtcnl
AS67
e Philips Export B.V. 1989
z....
All Rights are reserved. Reproduction in whole or in part is
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I
PHILIPS
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