1990_Silicon_General_Product_Catalog 1990 Silicon General Product Catalog
User Manual: 1990_Silicon_General_Product_Catalog
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SILI[ON
GENERAL
Product
. Catalog
SILI[ON
GENERAL
1990/1991
Solutions for Data Conversion and Power Management
INTRODUCTION
SILICON
GENERAL
r
THE SILICON GENERAL COMMITMENT
Silicon General Semiconductors has been recognized for many years as a leading supplier of
linear power management IC's, providing proprietary semiconductors for regulators, pulse
width modulators, servo and other drivers, read/write circuitry, and operational amplifiers. Our
roots in power IC technology have led us naturally into the interface area, and CMOS now plays
an important role in our product strategy, along with our historically recognized bipolar
capability. Our CMOS products, while not represented in this catalog, serve a variety of
interface applications and are available on a custom basis.
Silicon General believes a focused product and marketing strategy is best for our chosen
marketing base, as well as our customers. We concentrate our resources on serving
applications in the Military, Radiation Hard, Industrial Power Supplies, Computer Storage, and
Automotive markets. This focused strategy has allowed us to become the leading supplier to
our customers in some of these areas, and we continue to increase our penetration in the
others.
Silicon General has been certified by DESC to manufacture microcircuits in conformance with
MIL-M-38510, Class B. Certification has also been extended to manufacture devices to MILS-19500, JAN, JANTX, and JANTXV. Several devices have been qualified with a growing list
of QPL items planned in the future. Many OEM customers have approved Silicon General to
manufacture and process devices to their demanding Class S requirements.
We are committed to providing quality products to our customers, on schedule. All our products,
whether industrial or military, are processed in the same qualified bipolar fabrication facility. Fab
equipment includes the use of projection aligners, dry etch equipment, and ion implantation.
Statistical process control is in place and used in daily operations.
Silicon General's offshore and US assembly capability, in combination with one of the broadest
package offerings in the industry, provides further flexibility in satisfying the needs of our
customers.
We are also committed to providing better technical solutions to your applications problems,
and particularly endeavor to provide custom capability wherever practical. Design, product, and
applications engineering teams are available in more than one geographical area.
Silicon General supplies the leaders in each of our chosen market areas, and we pride
ourselves in this regard. We are a team dedicated to meeting our commitments, and we are a
company who values partnership relations with its customers.
We thank you for considering Silicon General as a supplier to your company.
sjg,n~
ell ~r'AI'--------"
c~~mpson
Charles
President
December 1989
GENERAL NOTES
SILICON
GENERAL
PRODUCT STATUS DEFINITIONS
The following definitions are used in this catalog to describe the current product production status. Silicon
General reserves the right to make changes without further notice to any product to improve reliability, function
or design.
Future Product Release Product is either currently under design or in the conceptual stage, and characteristics are for information only .
.Advanced Data Sheet Product design has been completed and parameters are under evaluation. Data described are
design goals, and final device specifications are subject to change.
(No Definition Noted) Product is in full production.
IDENTIFICATION OF OFF-SHORE ASSEMBLY LOCATIONS
Silicon General utilizes several off-shore locations to perform assembly and environmental screening
operations. This assembly site is identified on the device or unit packaging label according to the following
codes:
~
Preferred
Abbreviations
Limited Space
Abbreviations
Korea
Philippines
Thailand
U.S.A.
KOR
PHIL
THAI
USA
A
SorT
B
G
THUMB INDEX
SILICON
GENERAL
TABLE OF CONTENTS
I •
PART NUMBER INFORMATION
I •
GENERAL INFORMATION
I •
POWER SUPPLY CIRCUITS
I
MOTION CONTROL CIRCUITS
I •
POWER DRIVER AND INTERFACE CIRCUITS
II
I.
OPERATION AMPLIFIERS AND COMPARATORS
I •
CORE MEMORY CIRCUITS
I •
AUTOMOTIVE CIRCUITS
I •
OTHER CIRCUITS
I
PACKAGE INFORMATION
I •
APPLICATION INFORMATION
I
SALES OFFICES
I
II
II
II
THUMB INDEX
SILICON
GENERAL
TABLE OF CONTENTS
I
PART NUMBER INFORMATION
I
GENERAL INFORMATION
I
POWER SUPPLY C~RCUITS
I
81
MOTION CONTROL CIRCUITS
I
III
POWER DRIVER AND INTERFACE CIRCUITS
I
81
OPERATiON AMPLIFiERS AND COMPARATORS
I
III
CORE MEMORY CIRCUITS
I
Ell
AUTOMOTIVE CIRCUITS
I
III
OTHER CIRCUITS
I
III
PACKAGE INFORMATION
I
III
APPLICATION INFORMATION
I
lEI I
SALES OFFICES
I
I
.1
&1
III
1-1
•
TABLE OF CONTENTS
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS,
Section· Page
SECTION 1 • TABLE OF CONTENTS
1-2
SECTION 2 • PART NUMBER INFORMATION
Product Selection Guide
Numerical Selection Guide
Product Cross Reference Guide
Package Cross Reference Guide
Product Identification
Linear Integrated Circuits
Power Hybrid Circuits
2-2
2-4
2 - 10
2 - 12
2 - 14
2 - 15
,I
SECTION 3 • GENERAL INFORMATION,
Quality Assurance
Screening Procedures for Linear I.C.
Screening Procedure for Power Hybrid
,Screening Procedure for Diode Arrays
Q.C.1. Class S, MIL-M-38510
Q.C.I. Class B, MIL-M-38510
Q.C.1. JAN, JANTX, JANTXV MIL-S-19500
Capabilities
Military Product, MIL-M-38510 and MIL-S-19500
Custom Circuits
Radiation Hardening
3-2
, 3-3
'3-4
3-5
3-7
3 - 10
3 - 13
3 - 16
3 - 17
3 - 20
SECTION 4 • POWER SUPPLY CIRCUITS
Selection Guide
Data Sheets
4-2
4-7
SECTION 5 • MOTION CONTROL CIRCUITS
5-2
5-3
Selection' Guide
Data Sheets
SECTION 6 • POWER DRIVERS & INTERFACE CIRCUITS
Selection Guide
Data Sheets
6-2
6-5
SECTION 7 • OPERATIONAL AMPLIFIERS & COMPARATORS
7-2
7-5
Selection Guide
Data Sheets
January 1990
1 -2
TABLE OF CONTENTS
Section - Page
SECTION 8 - CORE MEMORY CIRCUITS
Selection Guide
Data Sheets
8-2
8-7
SECTION 9 - AUTOMOTIVE CIRCUITS
9-2
Selection Guide
Data Sheets
9-3
SECTION 10 - OTHER CIRCUITS
10 - 2
10 - 5
Selection Guide
Data Sheets
SECTION 11 - PACKAGE INFORMATION
Thermal I Power Ratings
Mechanical Dimensions
11 - 2
11 - 3
SECTION 12 - APPLICATION INFORMATION
12 - 2
12 - 3
Listing of Application Notes
Application Notes
SECTION 13 - SALES OFFICES
Domestic Sales Representative
Domestic Distributors
International Offices
1-3
13 - 2
13 - 5
13 - 8
1-4
THUMB INDEX
SILICON
GENERAL
_I
TABLE OF CONTENTS
I
PART NUMBER INFORMATION
I
III
GENERAL INFORMATION
I
III
POWER SUPPLY CIRCUITS
I
III
MOTION CONTROL CIRCUITS
I
III
POWER DRIVER AND INTERFACE CIRCUITS
I
81
OPERATION AMPLIFIERS AND COMPARATORS
I
III
CORE MEMORY CIRCUITS
I
III
AUTOMOTIVE CIRCUITS
I
III
OTHER CIRCUITS
I
III
PACKAGE INFORMATION
I
III
APPLICATION INFORMATION
I
III
SALES OFFICES
I
I
2-1
•
PRODUCT SELECTION GUIDE
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
POWER. SUPPLY CIRCUITS
Dual Tracking Fixed
SWITCHING REGULATOR CONTROL I.C.'s
SG1526/252613526
SG 1526B125268/35268
SG1527Al2527Al3527A
SG1529/252913529
SG1840/284013840
Current Mode PWM's
SG1528/252813528
SG1530/253013530
SG182512825/3825
SG18421284213842
SG18431284313843
SG1844/2844/3844
SG1845/284513845
SG1846/2846/3846
SGl847/2847/3847
4- 83
4 - 89
4 - 93
4-101
4-111
4 - 93
4-125
4 -183
4-121
4-121
4-175
4-191
4-191
4-201
4-201
4-209
4- 209
POWER SUPPLY SUPPORT FUNCTIONS
Protection Circuits
SG15421254213542
SG154312543/3543
SG154412544/3544
SG1548/2548/3548
SG1549/2549/3549
SG3523A13423A
SG352313423
Magnetic Amplifier Controllers
SG1557/255713557
SG1559/255913559
SG1560/2560/3560
4-141
4-147
4-153
4-157
4-161
4-219
4-219
4-165
4-165
4-165
Off Line Start-Up Controller
SGl540/2540/3540
4-135
VOLTAGE REGULATORS
Positive Adjustable
SG1051205/3051305A
SGl17/2171317
SGl17A1217A1317A
SGl17HV/217HVl317HV
SGl17AHV/217AHV/317AHV
SG1381238/338
SG138A1238A1338A
SG150/250/350
SG 150Al250Al350A
SG7231723C
SG15321253213532
SG104l2041304
SG140Al340A-5
SG140/340-6
SG140/340-8
SG1401340-12
SG140Al340A-12
SG1401340-15
SG140Al340A-15
SG140/340-18
SG140/340-20
SG780517805C17805A17805AC
SG7806l7806C17806A17806AC
SG7808l7808C17808A17808AC
SG781217812C/7812A17812AC
SG781517815C17815A17815AC
SG781817818CI7818A17818AC
SG782017.820C17820Al7820AC
SG782417824C/7824A17824AC
4-15
4-53
4- 53
4- 53
4-53
4-53
4-53
4-53
4-53
4-53
4-53
4-223
4-223
4-223
4-223
4-223
4-223
4-223
4-223
Negative Fixed Voltage
SG120/320-5
SG120Ai320A-5
SG120/320-5.2
SG120/320-8
SG120/320-12
SG120Al320A-12
SG120/320-15
SG120Al320A-15
SG1201320-18
SG120/320-20
SG790517905C17905A17905AC
SG7905.217905.2C
SG7905.2A17905.2AC
SG790817908C17908A17908AC
SG791217912C17912A17912AC
SG791517915C17915A17915AC
SG791817918C17918A17918AC
SG79201792OC17920Al7920AC
4-31
4-31
4 -31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4 -235
4-235
4-235
4-235
4 -235
·4-235
4-235
9-3
9-7
9-11
SG29055/29055A
4 -11
4-19
4 -19
4 -27
4-27
4-45
4-45
4- 63
4-63
4-69
4-129
4-7
4-39
4-39
SG29085/29085A
SG29125/29125A
Voltage Reference Circuits
SG103-1.8
SG103-2,0
SG103-2.2
SG103-2.4
SG103-2.7
SG103-3.0
SG103-3.3
SG103-3.6
SG103-3.9
SG103-4.3
SG103-4.7
SG103-5.1
SG103-5.6
SG1503/2503/3503
Dual Tracking Adjustable
SG1502l2502l3502
SG10912091309
SG140/340-5
Low Dropout Regulators
Negative Adjustable
SG137/2371337
SG 137Al237Al337A
4-73
4-171
Positive Fixed Voltage
Voltage Mode PWM's
SG15241252413524
SG 1524B125248/35248
SG1525A12525A13525A
SWITCHING REGULATOR OUTPUT STAGE
SG1501 Al2501A13501 Al4501
SG156811468
4 -79
January 1990
2-2
10- 9
10- 9
10 - 9
10 - 9
10-9
10-9
10-9
10-9
10 -9
10 -9
10 -9
10-9
10 - 9
10-35
SM600/601/602
SM610/611/612
SM625/6261627
SM635/636/637
SM645/646/647
SM655/656/657
SM660/661 1662
SM670/671 1672
4-247
4-247
4- 251
4-251
4-255
4-255
4-259
4- 259
MOTION CONTROL CIRCUITS
DC MOTOR PWM's
SG1731/2731/3731
5-9
STEPPER MOTOR DRIVER
SG3718
5 -29
MOTOR DRIVERS
High Current Motor Drivers
SGl173/2173/3173
SG1635/3635, SG1635A1363.5A .
SG1650/3650
SG3645
SG3663
SG3172
5-3
5-3
5 -15
5 -19
Medium Current Motor Drivers
·SG2001/2011/2021
SG200212012/2022
SG2003/201312023
SG2004/2014/2024
SG2005/201512025
SG2064/2065
. SG2066/2067
SG2068/2069
SG2070/2071
SG2074/2075
SG2076/2077
SG2801/2811/2821
SG28021281212822
SG28031281312823
SG2804/2814/2824
SG2805/2815
SG3272
6 -43
6 -43
6 -43
6-43
6-43
6 - 51
6 - 51
6-51
6-51
6-51
6- 51
6-57
6-57
6-57
6- 57
6 -57
7-41
Dual Hammer Drivers
SG3700
5-25
PRODUCT SELECTION GUIDE
POWER DRIVERS AND
INTERFACE CIRCUITS
POWER MOSFET DRIVERS
SG 1626/2626/3626
SG 1644/2644/3644
6-17
6-35
SG55463175463
SG55464175464
SG55470/754 70
SG55471175471
SG554 721754 72
SG55473/75473
SG55474175474
6 - 85
6 - 89
6-73
6 -77
6 - 81
6 - 85
6 - 89
AUTOMOTIVE CIRCUITS
LOW DROPOUT DUAL
VOLTAGE REGULATORS
9-3
9-7
9 -11
SG29055/29055A
SG29085/29085A
SG29125/29125A
Quad Peripheral Drivers
HIGH CURRENT DRIVERS
6-5
SG508
OTHER LINEAR CIRCUITS
Output Drivers
SG1627/2627/3627
6 - 25
Switch Drivers
SG 1629/2629/3629
6 -31
Quad Power Drivers
SG3645
5 -15
Dual Hammer Drivers
SG3700
5 - 25
Half Bridge Driver
SG1635/3635, SG1635A13635A
SG 1650/3650
5-3
5-3
Dual Solenoid Driver
SG3663
5 -19
6- 65
6 - 69
SG541
GENERAL PURPOSE
Compensated
7-11
7-25
SG107/207/307
SG7411741C
Uncompensated
7-5
7-9
SG101A1201A
SG2101A
7- 21
7- 33
7-15
7-19
SG111/211/311
SG2111
6-9
6 -13
SG1173/2173/3173
SG3172
SG3272
SG510A4/SG510AR4
10-13
VOLTAGE COMPARATORS
7 -15
7-19
SGlll/211/311
SG2111
WIDE BAND VIDEO AMPLIFIERS
High Voltage Compensated
SG143/343
SG1536/1436
10 -19
READIWRITE AMPLIFIER
Power Operational Amplifiers
Line Drivers / Receivers
SG1488
SG1489/1489A
DISK DRIVE
Comparators
Quad PIN Diode Driver
SG5792
SG5793
OPERATIONAL AMPLIFIERS
AND COMPARATORS
7- 29
7-37
7-41
SG040
SG1401/2401/3401
10-5
10 - 25
MULTIPLIERS
SG140212402/3402
SG1595/1495
10 - 31
10-39
MODULATOR/DEMODULATOR
SG1596/1496'
10 -45
Darlington Array Drivers
SG2001/2011/2021
SG20021201212022
SG2003/2013/2023
SG2004/2014/2024
SG2005/2015/2025
SG2801/2811/2821
SG280212812/2822
SG2803/2813/2823
SG2804/2814/2824
SG2805/2815
6 - 43
6 -43
6 -43
6 - 43
6- 43
6 - 57
6 - 57
6- 57
6 - 57
6 - 57
Quad Darlington Array Drivers
SG2064/2065
SG2066/2067
SG2068/2069
SG2070/2071
SG2074/2075
SG2076/2077
6- 51
6- 51
6-51
6- 51
6-51
6-51
Dual Peripheral Drivers
SG55450B175450B
SG55451 B175451 B
SG55452B175452B
SG55453B175453B
SG55454B175454B
SG55460175460
SG55461 175461
SG55462175462
6-73
6-77
6- 81
6- 85
6-89
6-73
6-77
6-81
CORE MEMORY CIRCUITS
VOLTAGE REFERENCE CIRCUITS
SENSE AMPLIFIERS
SG5524
SG5534
SG55234/55234A
SG55236/55236A
8-11
8 - 25
8- 25
8- 29
MEMORY DRIVERS
SG55325175325
SG55326/75326
SG55327175327
8 - 37
8 -41
8 - 45
DIODE ARRAYS
8 -15
8 -15
8 -15
8-15
8-15
8 -15
8 - 21
SG5768/5768A
SG5770/5770A
SG5772/5772A
SG5774/5774A
SG25768
SG6496
SG6100/6101
BRIDGE CIRCUITS
8-7
SG3212
2-3
SG103-1.8
SG103-2.0
SG103-2.2
SG103-2.4
SG103-2.7
SG103-3.0
SG103-3.3
SG103-3.6
SG1 03-3.9 ,
SG103-4.3
SG103-4.7
SG103-5.1
SG103-5.6
SG1503/2503/3503
10-9
10 - 9
10 - 9
10-9
10 - 9
10 - 9
10-9
10 - 9
10 - 9
10- 9
10 -9
10- 9
10-9
10-35
TRANSISTOR ARRAYS
SG3049
SG3183
SG3821 13046/3086
10-51
10- 55
10 - 59
•
SILICON
NUMERICAL PRODUCT SELECTION GUIDE
GENERAL
LINEAR INTEGRATED CIRCUITS
DevIce Type
DescrIption
SG040
SGl01A
SG103-1.8
00103-2.0
SG103-2.2
00103-2.4
00103-2.7
SGi03-3.0
SGi03-3.3
SG103-3.6
SG103-3.9
SGl03-4.3
SG103-4.7
SG103-S.1
SGi03-5.6
SG104
SG10S
00107
SG109
SG111
SG117
SG117A
OO117HV
SG117AHV
SG12D-S
SG120A-5
SG120-S.2
SG12D-8
SGl2D-12
SGl20A-12
SG120-15
SG120A-1S
SG120-18 .
SG120-20
S<3137
SG137A
SG138
SG138A
SGl4D-S
SG140A-.S
SGl4D-6
SG14Q-8
SG140-12
SGl40A-12
SG140-15
SG140A-15
SGl40-18
SG14D-24
SG143
SGl50
SG150A
SG201A
SG203-1.8
SG203,2.0
SG203-2.2
SG203-2,4
Two Channel Video Amplifier
Uncompensated Operational-Amplifier
Voltage Reference 1.8V
Voltage Reference 2.0V
Voltage Reference 2.2V
Voltage Reference 2.4V
Voltage Reference 2.7V
Voltage Reference 3.0V
Voltage Reference 3.3V
Voltage Reference 3.6V
Voltage Reference 3.9V
Voltage Reference 4.3V
Voltage Reference 4.7V
Voltage Reference 5.W
Voltage Reference 5.6V
Neg. Adjustable Voltage Regulator
Pos. Adjustable Voltage Regulator
Compensated Operational Amplifier
Pos. Fixed Voltage Regulator 5.0V
Voltage Comparator
Pos. Adjustable Voltage Regulator
Pos. Adjustable Voltage Regulator
Pos. Adjustable High Voltage Regulator
Pos. Adjustable High Voltage Regulator
Neg. Fixed Voltage Regulator 5.0V
Neg. Fixed Voltage Regulator 5.0V
Neg. Fixed Voltage Regulator 5.2V
Neg. Fixed Voltage Regulator B.OV
Neg. Fixed Voltage Regulator 12V
Neg. Fixed Voltage Regulator 12V
Neg. Fixed Voltage Regulator 15V
Neg. Fixed Voltage Regulator 15V
Neg. Fixed Voltage Regulator 1BV
Neg. Fixed Voltage Regulator 20V
1.5A Neg. Adjustable Regulator
1.5A Neg. Adjustable Regulator
SA Pos. Adjustable Regulator
5A Pos. Adjustable Regulator
Pos. Fixed Voltage Regulator 5.0V
Pos. Fixed Voltage Regulator 5.0V
Pos. Fixed Voltage Regulator 6.0V
Pos. Fixed Voltage Regulator B.OV
Pos. Fixed Voltage Regulator 12V
Pos. Fixed Voltage Regulator 12V
Pos. Fixed Voltage Regulator 15V
Pos. Fixed Voltage Regulator 15V
Pos. Fixed Voltage Regulator 1BV
Pos. Fixed Voltage Regulator 24V
High Voltage Operational Amplifier
3A Positive Adjustable Regulator
3A Positive Adjustable Regulator
Uncompensated Operational Amplifier
Voltage Reference 1.BV
Voltage Reference 2.0V
Voltage Reference 2.2V
Voltage Reference 2.4V
Page No.
Device Type
Description
10-5
7-5
10-9
10-9
10-9
10-9
10-9
10-9
10- 9
10- 9
10-9
10 - 9
10- 9
10- 9
10 - 9
4-7
4-11
7-11
4-15
7-15
4-19
4-19
4-27
4-27
4-31
4-31
4-31
4-31
4 - 31
4-31
4-31
4 - 31
4-31
4-31
4-39
4 - 39
4-45
4-45
4-53
4-53
4-53
4-53
4- 53
4 -53
4-53
4-53
4-53
4-53
7-21
4-63
4 - 63
7-5
10- 9
10-9
10-9
10- 9
SG203-2.7
SG203-3.0
SG203-3.3
SG203-3.&
SG203-3.9
SG203-4.3
SG203-4.7
SG203-S.1
SG203-S.6
SG204
SG20S
SG207
SG211
SG217
SG217A
SG217HV
SG217AHV
SG237
SG237A
SG238
SG238A
SG250
SG250A
SG301A
SG303-1.8
SG303-2.0
SG303-2.2
SG303-2.4
SOO03-2.7
SG303-3.0
SG303-3.3
SG303-3.&
SOO03-3.9
SG303-4.3
SOO03-4.7
SG303-5.1
SG303-S.6
SG304
SG30S
SG305A
SG307
SG309
SG311
SG317
SG317A
SG317HV
SG317AHV.
SG320-5
SG320A-5
SG320-5.2
SG320-8
SG32D-12
SG320A-12
SG32O-15
SG32OA-15
SG32o-18
Voltage
Voltage
Voltage
Voltage
Voltage
January 1990
2-4
Reference 2.7V
Reference 3.0V
Reference 3.3V
Reference 3.6V
Reference 3.9V
Vo~age Reference 4.3V
Voltage Reference 4.7V
Voltage Reference S.1 V
Voltage Reference 5.6V
Neg. Adjustable Voltage Regulator
Pos. Adjustable Voltage Regulator
Compensated Operational Amplifier
Voltage Comparator
Pos. Adjustable Voltage Regulator
Pos. Adjustable Voltage Regulator
Pos. Adjustable High Voltage Regulator
Pos. Adjustable High Voltage Regulator
1.5A Neg. Adjustable Voltage Regulator
1.5A Neg. Adjustable Voltage Regulator
SA Pos. Adjustable Regulator
SA Pos. Adjustable Regulator
3A Positive Adjustable Regulator
3A Positive Adjustable Regulator
Uncompensated Operational Amplifier
Voltage Reference 1.BV
Voltage Reference 2.0V
Voltage Reference 2.2V
Voltage Reference 2,4V
Voltage Reference 2.7V
Voltage Reference 3.0V
Voltage Reference 3.3V
Voltage Reference 3.6V
Voltage Reference 3.9V
Voltage Reference 4.3V
Voltage Reference 4.7V
Voltage Reference 5.1 V
Voltage Reference 5.6V
Neg. Adjustable Voltage Regulator
Pos. Adjustable Voltage Regulator
Pos. Adjustable Voltage Regulator
Compensated Operational Amplifier
Pos. Fixed Voltage Regulator 5.0V
Voltage Comparator
Pos. Adjustable Voltage Regulator
Pos. Adjustable Voltage Regulator
Pos. Adjustable High Voltage Regulator
Pos. Adjustable High Voltage Regulator
Neg. Fixed Voltage Regulator 5.0V
Neg. Fixed Voltage Regulator 5.0V
Neg. Fixed Voltage Regulator 5.2V
Neg. Fixed Voltage Regulator B.OV
Neg. Fixed Voltage Regulator 12V
Neg. Fixed Voltage Regulator 12V
Neg. Fixed Voltage Regulator 15V
Neg. Fixed Voltage Regulator 15V
Neg. Fixed Voltage Regulator 1BV
Page No.
10-9
10-9
10-9
10-9
10-9
10-9
10-9
10-9
10 -9
4-7
4-11
7-11
7-15
4-19
4 -19
4-27
4-27
4-39
4-39
4-45
4-45
4-63
4- 63
7-5
10- 9
10-9
10- 9
10 - 9
10-9
10-9
10 -9
10-9
10-9
10 - 9
10-9
10-9
10- 9
4-7
4-11
4-11
7-11
4-15
7-15
I
4-19
4-19
4-27
4-27
4- 31
4- 31
4- 31
4 -31
4-31
4-31
4-31
4-31
4- 31
NUMERICAL PRODUCT SELECTION GUIDE
Device Type
Description
SG320-20
SG337
SG337A
SG338
SG338A
SG340·5
SG340A-5
SG340·6
SG340-8
SG340-12
SG340A-12
SG340-15
SG340A-15
SG340-18
SG340-24
SG343
SG350
SG350A
SG508
SG510A4
SG510AR4
SG541
SG723
SG723C
SG741
SG741C
SG1173
SGI401
SGI402
SG1436
SGI468
SGI488
SG1489
SG1489A
SG1495
SG1496
SG1501A
SG1502
SG1503
SG1524
SG1524B
SGI525A
SG1526
SG1526B
SG1527A
SG1528
SG1529
SG1530
SGI532
SGI536
SGI540
SGI542
SGI543
SGI544
SG1548
SGI549
Neg. Fixed Voltage Regulator 20V
1.5A Negative Adjustable Regulator
1.5A Negative Adjustable Regulator
5A Positive Adjustable Regulator
5A Positive Adjustable Regulator
Pos. Fixed Voltage Regulator 5.0V
Pos. Fixed Voltage Regulator 5.0V
Pos. Fixed Voltage Regulator 6.0V
Pos. Fixed Voltage Regulator 8.0V
Pos. Fixed Voltage Regulator 12V
Pos. Fixed Voltage Regulator 12V
Pos. Fixed Voltage Regulator 15V
Pos. Fixed Voltage Regulator 15V
Pos. Fixed Voltage Regulator 18V
Pos. Fixed Voltage Regulator 24V
High Voltage Operational Amplifier
3A Positive Adjustable Regulator
3A Positive Adjustable Regulator
Quad - NAND Driver
ReadlWrite Amplifier
ReadlWrite Amplifier
Read Data Processor
Precision Pos. Adjustable Voltage Regulator
Precision Pos. Adjustable Voltage Regulator
Compensated Operational Amplifier
Compensated Operational Amplifier
3.5A Power Operational Amplifier
High Frequency Video Amplifier
Variable Gain, Wideband Amplifier/Multiplier
High Voltage Operational Amplifier
Fixed Dual Voltage Tracking Regulator
Quad RS-232C line Driver
Quad RS-232C Line Receiver
Quad RS-232C Line Receiver
4 - Quadrant Multiplier
Balanced Modulator/Demodulator
Fixed Dual Voltage Tracking Regulator
Adjustable Dual Voltage Tracking Regulator
Precision 2.5V Reference
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
High Speed Current Mode PWM
Voltage Mode Pulse Width Modulator
High Speed Current Mode PWM
Precision Pos. Adjustable Voltage Regulator
High Voltage Operational Amplifier
Off - Line Start-Up Controller
Voltage Sensing Circuit
Power Supply Output Supervisory Circuit
Low Voltage Supervisory Circuit
Quad Power Fault Monitor
Current Sense Latch
Device Type
Description
SG1557
SG1559
SG1560
SG1568
SG1595
SG1596
SG1626
SG1627
SG1629
SGI635
SG1635A
SG1644
SG1650
SG1731
SG1825
SG1840
SGI842
SGI843
SGI844
SGI845
SG1846
SG1847
SG2001
SG2002
SG2003
SG2004
SG2005
SG2011
SG2012
SG2013
SG2014
SG2015
SG2021
SG2022
SG2023
SG2024
SG2025
SG2064
SG2065
SG2066
SG2067
SG2068
SG2069
SG2070
SG2071
SG2074
SG2075
SG2076
SG2077
SG2101A
SG2111
SG2172
SG2173
SG2401
SG2402
SG2501A
Magnetic Amplilier Controller
Magnetic Amplifier Controller
Magnetic Amplifier Controller
Fixed Dual Voltage Tracking Regulator
4 - Quadrant Multiplier
Balanced Modulator/Demodulator
Dual High Speed MOSFET Driver
Dual High Current Output Driver
High Current Floating Switch Driver
2A Half - Bridge Driver
2A Half - Bridge Driver
Dual HigH Speed MOSFET Driver
2A Hall - Bridge Driver
DC Motor Pulse Width Modulator
High Speed Current Mode PWM
Programmable, Off-Line PWM Controller
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width. Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
High Voltage, Medium Current Driver Array
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Quad 1.5A Darlington Switches
Dual Uncompensated Operational Amplifier
Dual Voltage Comparator
3.0A Power Operational Amplifier
3.5A Power Operational Amplifier
High Frequency Video Amplifier
Variable Gain Wideband Amplifier/Multiplier
Fixed Dual Voltage Tracking Regulator
Page No.
4· 31
4-39
4-39
4· 45
4 ·45
4-53
4· 53
4-53
4· 53
4-53
4· 53
4· 53
4 ·53
4- 53
4- 53
7 - 21
4- 63
4- 63
6-5
10-13
10 -13
10-19
4-69
4-69
7- 25
7-25
7- 29
10- 25
10 -31
7- 33
4 -171
6-9
6-13
6-13
10-39
10 -45
4-73
4-79
10-35
4- 83
4- 89
4- 93
4-101
4 -111
4-93
4-121
4 -125
4-121
4 -129
7-33
4-135
4-141
4-147
4-153
4 -157
4-161
2-5
Page No.
4-165
4·165
4·165
4 ·171
10- 39
10-45
6-17
6- 25
6-31
5·3
5·3
6-35
5-3
5-9
4-175
4-183
4-191
4-191
4-201
4- 201
4-209
4-209
6-43
6 - 43
6-43
6-43
6 -43
6-43
6-43
6 -43
6-43
6-43
6 - 43
6-43
6 -43
6 -43
6 -43
6 - 51
6-51
6 -51
6 - 51'
6 -51
6 -51
6 -51
6-51
6 -51
6 - 51
6-51
6-51
7-9
7 -19
7 -41
7 -29
10-25
10 - 31
4 -73
•
NUMERICAL PRODUCT SELECTION GUIDE
Device Type
SG2502
SG2503
SG2524
SG2524B
SG2525A
SG2526
SG2526B
SG2527A
SG2526
SG2529
SG2530
SG2532
SG2540
SG2542
SG2543
SG2544
SG2548
SG2549
SG2557
SG2559
SG2560
SG2626
SG2644
SG2731
SG2601
SG2602
SG2803
SG2804
SG2605
SG2811
SG2812
SG2813
SG2814
SG2815
SG2821
SG2822
SG2823
SG2824
SG2825
SG2840
SG2842
SG2843
SG2844
SG2845
SG2846
SG2847
·SG3045
SG3046
SG3049
SG3086
SG3172
SG3173
SG3183
SG3212
SG3272
SG3401
Description
Adjustable Dual Voltage Tracking Regulator
Precision 2.5V Reference
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Vottage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
High Speed Current Mode PWM
Voltage Mode Pulse Width Modulator
High Speed Current Mode PWM
Precision Pos. Adjustable Voltage Regulator
Off-Line Start-Up Controller
Voltage Sensing Circuit
Power Supply Output Supervisory Circuit
Low Voltage Supervisory Circuit
Quad Power Fault Monitor
Current Sense Latch
Magnetic Amplifier Controller
MagnetiC Amplifier Controller
Magnetic Amplifier Controller
Dual High Speed MOSFET Driver
Dual High Speed MOSFET Driver
DC Motor Pulse Width Modulator
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Voltage Medium Current Driver Array
High Speed Current Mode PWM
Programmable. Off-Line PWM Controller
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Matched NPN Transistor Arrays
Matched NPN Transistor Arrays
Dual High Frequency Operational Amplifier
Matched NPN Transistor Arrays
3.0A Power Operational Amplifier
3.5A Power Operational Amplifier
High Current NPN Transistor Array
Dual Diode Bridge
Dual Power Operational Amplifier
High Frequency Video Amplifier
.PagaNo.
4 - 79
10-35
4 - 83
4-89
4-93
4- 101
4 - 111
4- 93
4 - 121
4 - 125
4 - 121
4- 129
4 - 135
4- 141
4 - 147
4- 153
4- 157
4- 161
4- 165
4 - 165
4- 165
6- 17
6-35
5-9
6-57
6-57
6-57
6 - 57
6 - 57
6- 57
6-57
6 - 57
6- 57
6- 57
6- 57
6-57
6-57
6-57
4- 175
4- 183
4 - 191
4- 191
4 -201
4-201
4-209
4-209
la-59
10 - 59
10 - 51
10-59
7- 37
7- 29
10 - 55
8-7
7-41
10 - 25
Device Type
SG3402
SG3423
SG3423A
SG3501A
SG3502
SG3503
SG3523
SG3523A
SG3524
SG3524B
SG3525A
SG3526
SG3526B
SG3527A
SG3528
SG3529
SG3530
SG3532
SG3540
SG3542
SG3543
SG3544
SG3548
SG3549
SG3557
SG3559
SG3560
SG3626
SG3627
SG3629
SG3635
SG3635A
SG3644
SG3545
SG3650
SG3663
SG3700
SG3718
SG3731
SG3821
SG3825
SG3840
SG3842
SG3843
SG3844
SG3845
. SG3846
SG3847
SG4501
SG5524
SG5534
SG5768
SG5768A
SG5770 .
SG5770A
SG5772
2-6
Description
. Page No.
Variable Gain Wideband Amplifier/Multiplier
Voltage Sensing Circuit
Voltage Sensing Circuit
Fixed Dual Voltage Tracking Regulator
Adjustable Dual Vottage Tracking Regulator
Precision 2.5V Reference
Voltage Sensing Circuit
Voltage Sensing Circuit
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
Voltage Mode Pulse Width Modulator
High Speed Current Mode PWM
Voltage Mode Pulse Width Modulator
High Speed Current Mode PWM
Precision Pos. Adjustable Voltage Regulator
Off-Line Start-Up Controller
Voltage Sensing Circuit
Power Supply Output Supervisory Circuit
Low Voltage Supervisory Circuit
Quad Power Fault Monitor
Current Sense Latch
Magnetic Amplifier Controller
MagnetiC Amplifier Controller
Magnetic Amplifier Controller
Dual High Speed MOSFET Driver
Dual High Current Output Driver
High Current Floating Switch Driver
2A Half Bridge Driver
2A Half Bridge Driver
Dual High Speed MOSFET Driver
Quad 2.5A Power Driver
2A Half Bridge Driver
Dual Solenoid / Motor Driver
Dual Hammer Driver
High Current Stepper Motor Driver
DC Motor Pulse Width Modulator
Matched NPN Transistor Arrays
High Speed Current Mode PWM
Programmable Off-Line PWM Controller
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Current Mode Pulse Width Modulator
Fixed Voltage Dual Tracking Regulator
Dual Sense Amplifier
Dual Sense Amplifier
Diode Array Circuits
Diode Array Circuits
Diode Array Circuits
Diode Array Circuits
Diode Array Circuits
to-31
4-219
4-219
4 - 73
4- 79
10 -35
4-219
4-219
4- 83
4-89
4- 93
4 - 101
4- 111
4-93
4- 121
4 - 125
4- 121
4 - 129
4- 135
4- I'll
4 - 147
4- 153
4 - 157
4 - 161
4 - 165
4- 165
4-165
6 - 17
6-25
6 - 31
5-3
5-3
6-35
5- 15
5-3
5- 19
5-25
5 -29.
5-9
10 - 53
4- 175
4- 183
4 - 191
4- 191
4-201
4-201
4-209
4-209
4- 73
8- 11
B -25
8 - 15
B- 15
8 - 15
8- 15
8- 15
NUMERICAL PRODUCT SELECTION GUIDE
DevlceType
Description
SG5772A
SG5774
SG5774A
SG5792
SG5793
SG6100
SG6101
SG6496
SG780S
SG7805C
SG780SA
SG7805AC
SG7806
SG7806C
SG7806A
SG7806AC
SG7808
SG7808C
SG7808A
SG7808AC
SG7812
SG7812C
SG7812A
SG7812AC
SG7815
SG7815C
SG7815A
SG7815AC
SG7818
SG7818C
SG7818A
SG7818AC
SG7820
SG7820C
SG7820A
SG7820AC
SG7824
SG7824C
SG7824A
SG7824AC
SG7905
SG7905C
SG7905A
SG7905AC
SG7905.2
SG7905.2C
SG7905.2A
SG7905.2AC
SG7908
SG790BC
SG7908A
SG7908AC
SG7912
SG7912C
SG7912A
SG7912AC
Diode Array Circuits
Diode Array Circuits
Diode Array Circuits
Quad PIN Diode Driver
Quad PIN Diode Driver
Diode Array Circuits
Diode Array Circuits
Diode Array Circuits
Pos. Fixed Voltage Regulator S.OV
Pos. Fixed Voltage Regulator 5.0V
Pos. Fixed Voltage Regulator 5.0V
Pos. Fixed Voltage Regulator 5.0V
Pos. Fixed Voltage Regulator 6.0V
Pos. Fixed Voltage Regulator 6.0V
Pos. Fixed Voltage Regulator 6.0V
Pos. Fixed Voltage Regulator 6.0V
Pos. Fixed Voltage Regulator 8.0V
Pos. Fixed Voltage Regulator 8.0V
Pos. Fixed Voltage Regulator 8.0V
Pos. Fixed Voltage Regulator 8.0V
Pos. Fixed Voltage Regulator 12V
Pos. Fixed Voltage Regulator 12V
Pos. Fixed Voltage Regulator 12V
Pos. Fixed Voltage Regulator 12V
Pos. Fixed Voltage Regulator 15V
Pos. Fixed Voltage Regulator 15V
Pos. Fixed Voltage Regulator 15V
Pos. Fixed Voltage Regulator 15V
Pos. Fixed Voltage Regulator 18V
Pos. Fixed Voltage Regulator 18V
Pos. Fixed Voltage Regulator 18V
Pos. Fixed Voltage Regulator 18V
Pos. Fixed Voltage Regulator 20V
Pos. Fixed Voltage Regulator 20V
Pos. Fixed Voltage Regulator 20V
Pos. Fixed Voltage Regulator 20V
Pos. Fixed Voltage Regulator 24V
Pos. Fixed Voltage Regulator 24V
Pos. Fixed Voltage Regulator 24V
Pos. Fixed Voltage Regulator 24V
Neg. Fixed Voltage Regulator 5.0V
Neg. Fixed Voltage Regulator 5.0V
Neg. Fixed Voltage Regulator 5.0V
Neg. Fixed Voltage Regulator 5.0V
Neg. Fixed Voltage Regulator 5.2V
Neg. Fixed Voltage Regulator 5.2V
Neg. Fixed Voltage Regulator 5.2V
Neg. Fixed Voltage Regulator 5.2V
Neg. Fixed Voltage Regulator 8.0V
Neg. Fixed Voltage Regulator 8.0V
Neg. Fixed Voltage Regulator B.OV
Neg. Fixed Voltage Regulator 8.0V
Neg. Fixed Voltage Regulator 12V
Neg. Fixed Voltage Regulator 12V
Neg. Fixed Voltage Regulator 12V
Neg. Fixed Voltage Regulator 12V
Page No.
8-15
8-15
8 -15
6-65
6 - 69
8-21
8-21
8-15
4 -223
4- 223
4 - 223
4- 223
4 -223
4-223
4 -223
4- 223
4 -223
4-223
4 -223
4-223
4 -223
4- 223
4 -223
4-223
4 -223
4-223
4- 223
4 -223
4- 223
4 -223
4 - 223
4 -223
4 -223
4-223
4 -223
4-223
4 -223
4-223
4 -223
4-2'23
4 -235
4-235
4 -235
4-235
4-235
4-235
4-235
4-235
4- 235
4-235
4- 235
4- 235
4-235
4- 235
4 -235
4- 235
2-7
Device Type
Description
SG7915
SG7915C
SG7915A
SG7915AC
SG7918
SG7918C
SG7918A
SG7918AC
SG7920
SG7920C
SG7920A
SG7920AC
SG2S768
SG2S770
SG2905S
SG290S5A
SG29085
SG29085A
SG29125
SG29125A
SG55234
SG55234A
SG55236
SG55236A
SG55325
SG55326
SG55327
SG554508
SG554518
SG554528
SG554538
SG554548
SG55460
SG55461
SG55462
SG55463
SG55464
SG55470
SG55471
SG55472
SG55473
SG55474
SG75325
SG75326
SG75327
SG754508
SG754518
SG754528
SG754538
SG754548
SG75460
SG75461
SG75462
SG75463
SG75464
SG75470
Neg. Fixed Voltage Regulator 15V
Neg. Fixed Voltage Regulator 15V
Neg. Fixed Voltage Regulator 15V
Neg. Fixed Voltage Regulator 15V
Neg. Fixed Voltage Regulator 18V
Neg. Fixed Voltage Regulator 18V
Neg. Fixed Voltage Regulator 18V
Neg. Fixed Voltage Regulator 18V
Neg. Fixed Voltage Regulator 20V
Neg. Fixed Voltage Regulator 20V
Neg. Fixed Voltage Regulator 20V
Neg. Fixed Voltage Regulator 20V
Diode Array Circuits
Diode Array Circuits
Low Dropout Dual Regulator 5V, 5V
Low Dropout Dual Regulator 5V, SV
Low Dropout Dual Regulator 8.2V, SV
Low Dropout Dual Regulator 8.2V, 5V
Low Dropout Dual Regulator 12V, 5V
Low Dropout Dual Regulator 12V, 5V
Dual Sense Amplifier
Dual Sense Amplifier
Dual Sense Amplifier! Data Registers
Dual Sense Amplifier! Data Registers
Dual Source! Dual Sink Memory Driver
Quad Sink Memory Driver
Quad Source Memory Driver
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - NAND Driver
Dual Peripheral Positive - OR Driver
Dual Peripheral Positive - NOR Driver
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - NAND Driver
Dual Peripheral Positive - OR Driver
Dual Peripheral Positive - NOR Driver
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - NAND Driver
Dual Peripheral Positive - OR Driver
Dual Peripheral Positive - NOR Driver
Memory Driver
Memory Driver
Quad Source Memory Driver
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - NAND Driver
Dual Peripheral Positive - OR Driver
Dual Peripheral Positive - NOR Driver
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - NAND Driver
Dual Peripheral Positive - OR Driver
Dual Peripheral Positive - NOR Driver
Dual Peripheral Positive - AND Driver
Page No.
4- 235
4-235
4- 235
4-235
4 - 235
4-235
4 - 235
4-235
4 -235
4-235
4-235
4-235
8-15
8-15
9-3
9-3
9-7
9 -7
9-11
9-11
8-25
8-25
8-29
8-29
8-37
8-41
8-45
6-73
6-77
6-81
6-85
6- 89
6-73
6-77
6-81
6-85
6-89
6-73
6-77
6-81
6-85
6-89
8-37
8-41
8-45
6-73
6-77
6-81
6-85
6-89
6-73
6-77
6-81
6-85
6-89
6-73
•
NUMERICAL PRODUCT SELECTION GUIDE
Device Type
Description
SG75471
SG75472
SG75473
SG75474
SM600
SM601
SM602
SM610
SM6ll
SM612
SM625
SM626
SM627
SM635
SM636
SM637
SM645
SM646
SM647
SM655
SM656
SM657
SM660
SM661
SM662
SM670
SM671
SM672
Dual Peripheral Positive - AND Driver
Dual Peripheral Positive - NAND Driver
Dual Peripheral Positive - OR Driver
Dual Peripheral Positive - NOR Driver
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
Switching Regulator Power Output Stages
PagaNo.
Device Type
6 -77
6 - 81
6 - 85
6- 89
4-247
4 - 247
4-247
4- 247
4- 247
4- 247
4- 251
4-251
4 -251
4- 251
4 - 251
4- 251
4- 255
4 - 255
4- 255
4- 255
4- 255
4- 255
4 -259
4- 259
4-259
4- 259
4- 259
4- 259
2-8
DescrIption
PagaNo.
•
2-9
CROSS REFERENCE GUIDE
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
PIN
SGREPLACE PIN
CHERRY
CH1526
CS365
CS1524
SG1526
SG3172
SG1524
SG1524B
SG1525A
SG1527A
SG1842
SGl843
SG2524
SG2525A
SG2526
SG2527A
SG3718
CS1524A
CS1525A
CS1527A
CSl842
CSl843
CS2524
CS2525A
C52526
CS2527A
CS3717A
LINEAR TECH
LM101A
LM107
LMlll
LMl17
LMl17A
LM123
LM137
LM138
LM150
LM301A
LM307A
LM311
LM317
LM317A
LM323
LM337
LM338
LM350
LT123A
LT137A
LT13BA
LT150A
LT1524
LT1525A
LT1526
LT1527A
LTl842
LT1843
LT2524
LT2524A
LT2526
LT323A
LT337A
LT338A
LT350A
LT3524
LT3525A
LT3526
LT3527A
SG1524
SG1525A
SG1527A
SG2524
SG3524
SG3525A
SG3527A
UC1B46
UCl847
UC3B46
UC3B47
SG101A
SG107
SGlll
SGl17
SGl17A
SG123
SG137
SG138
SG150
SG301A
SG307
SG311
SG317
SG317A
SG323
SG337
SG336
SG350
SG123A
SG137A
SG138A
SG150A
SG1524
SG1525A
SG1526
SG1527A
SGl842
SGl843
SG2524
SG2524B
SG2526
SG323A
SG337A
SG338A
SG350A
SG3524
SG3525A
SG3525
SG3527A
SG1524
SG1525A
SG1527A
SG2524
SG3524
SG3525A
SG3527A
SGl846
SGl847
SG3B46
SG3B47
MOTOROLA
LM101A
LM109
LMlll
LMl17
LM123
LM124
LM137
LM140-12
SG101A
SG109
SGlll
SGl17
SG123
SG124
SG137
SG14Q-12
LMl40-15
LMl40-18
LM140-24
LMl50
LM201
LM201A
LM204
LM205
LM208
LM211
LM217
LM223
LM224
LM237
LM250
LM301A
LM305
LM309
LM311
LM317
LM323
LM337
LM340-05
LM340-12
LM340-15
LM340-18
LM340-20
LM340-24
LM350
LM350-o8
MADl103C
MADll03F
MADll03P
MAOll04C
MAOll04F
MAOll04P
MAOll08C
MAOll08F
MAOll0BP
MC1403
MC1411
MC1412
MC1413
MC1416
MC1436
MC1468
MC14B9A
MC1495
MC1496
MC1503
MC1536
MC1568
MC1595
MC1596
MC1723
MC1741
MC1741S
MC174B
MC7805
MC7B05A
MC7B05AC
MC7B05C
MC7BOB
MC7B06A
MC7B06AC
MC7B06C
MC7808
MC7BOBA
MC7BOBC
MC7812
MC7812A
MC7B12AC
MC7Bl2C
MC7815
MC7815A
MC7B15AC
MC7B15C
MC7B20
SGREPLACE PIN
SG14Q-15
SG14Q-18
SG140-24
SG150
SG201
SG201A
SG204
SG205
SG209
SG211
SG217
SG223
SG224
SG237
SG250
SG301A
SG305
SG309
SG311
SG317
SG323
SG337
SG34Q-05
SG340-12
SG34Q-15
SG340-18
SG340-20
SG340-24
SG350
SG340-08
SG5772J
SG5772F
SG5772N
SG5774J
SG5774F
SG5774N
SG6101J
SG6101F
SG6101N
SG3503
SG2001
SG2002
SG2003
SG2004
SGl436
SG1468
SGl489A
SG1495
SG1496
SG1503
SGl536
SG156B
SG1595
SG1596
SG723
SG741
SG741C
SG201
SG7805
SG7805A
SG7805AC
SG7B05C
SG7B06
SG7806A
SG7806AC
SG7B06C
SG7808
SG780BA
SG7BOBC
SG7812
SG7812A
SG7B12AC
SG7812C
SG7815
SG7B15A
SG7B15AC
SG7815C
SG7B20
SGREPLACE PIN
MC7820A
MC7820AC
MC7820C
MC7824
MC7824A
MC7824AC
MC7824C
MC7905
MC7905A
MC7905AC
MC7905C
MC7905_2
MC7905.2A
MC7905.2AC
MC7905.2C
MC7908
MC7908A
MC7908AC
MC7908C
MC7912
MC7912A
MC7912AC
MC7912C
MC7915
MC7915A
MC7915AC
MC7915C
MC7918
MC7918A
MC7918AC
MC7918C
MC7920
MC7920A
MC7920AC
MC7920C
SG1525A
SG1526
SG1527A
SG2525A
SG2526
SG2527A
SG3525A
SG3526
ULN2003
ULN2004
ULN2084
ULN2065
ULN2066
ULN2067
ULN2068
ULN2069
ULN2074
SG7820A
SG7820AC
SG7820C
SG7824
SG7824A
SG7824AC
SG7824C
SG7905
SG7905A
SG7905AC
SG790SC
SG7905_2
SG7905.2A
SG7905.2AC
SG7905.2C
SG7908
SG7908A
SG7908AC
SG7908C
SG7912
SG7912A
SG7912AC
SG7912C
SG7915
SG7915A
SG7915AC
SG7915C
SG7918
SG7918A
SG7918AC
SG7918C
SG7920
SG7920A
SG7920AC
SG7920C
SG1525A
SG1526
SG1527A
SG2525A
SG2526
SG2527A
SG3525A
SG3526
SG2003C
SG2004C
SG2064
SG2065
SG2066
SG2067
SG2068
SG2069
SG2074
NATIONAL
OS55325
0555451
OS55452
OS55453
0555454
OS55461
OS55462
OS55463
OS55464
DS55470
OS55471
FSA1410M
FSA1411M
FSA2002M
FSA2003M
FSA2500M
FSA2501M
FSA2501P
FSA2503M
FSA2503P
FSA2504M
FSA2509M
FSA2509P
SG55325
SG55451
SG55452
SG55453
SG55454
SG55461
SG55462
SG55463
SG55464
SG55470
SG55471
SG5770T
SG5768T
SG576BF
SG5770F
SG5772F
SG5772J
SG5772N
SG5774J
SG5774N
SG5774F
SG5774AJ
SG5774AN
April 1990
2 -10
FSA251OM
FSA2510P
FSA2563M
FSA2563P
FSA2564M
FSA2564P
FSA2565M
FSA2566M
FSA2619M
FSA2619P
FSA2620M
FSA2620P
FSA2621M
FSA2719M
FSA2719P
FSA2720M
FSA2720P
FSA2721M
LM103-1.8
LM103-2.7
LM103-4.8
LM104A
LM105A
LM109
LMl17
LM120-05
LM120-oa
LM120-12
LM120-15
LM120-18
LM120-20
LM12Q-5.2
LM123
LM137
LM138
LM140-05
LM140-06
LM140-0B
LM140-12
LM140-15
LM140-1B
LM140-20
LM143
LM150
LM1524
LM204
LM205
LM207
LM209
LM217
LM220-05
LM220-08
SGREPLACE PIN
SG5772AJ
SG5772AN
SG5768AJ
SG5768AN
SG5770AJ
SG5770AN
SG25768J
SG25770J
SG6101AJ
SG6101AN
SG6100AJ
SG6100AN
SG6100AF
SG6101J
SG6101N
SG6100J
SG6100N
SG6100F
SG103-1.8
SG103-2.7
SG103-4.8
SG104
SG105
SG109
SGl17
SG120-o5
SG120-o8
SG120-12
SG120-15
SG120-18
SG120-20
SG120-5.2
SGl23
SG137
SG138
SGl40-05
SG140-06
SG140-0B
SG14Q-12
SG140-15
SG140-18
SG140-20
SGl43
SGl50
SG1524
SG204
SG205
SG207
SG209
SG217
SG220-05
SG22Q-08
LM220·12
SG220-12
LM220-15
LM220-5.2
LM237
LM238
LM23BA
LM240-05
LM240-06
LM240-0B
LM240-12
LM240-15
LM240-18
LM250
LM250A
LM2524
LM304
LM305
LM305A
LM309
LM317
LM320-05
LM320-oB
LM32Q-12
LM32Q-15
LM32Q-1B
LM320-20
SG220-15
SG220-5.2
SG237
SG238
SG238A
SG240-05
SG240-06
SG24Q-OB
SG240-12
SG240-15
SG240-18
SG250
SG250A
SG2524
SG304
SG305
SG305A
SG309
SG317
SG320-05
SG320-OB
SG320-12
SG320-15
SG320-1B
SG320-20
LM320-5_2
LM323
LM337
LM338
LM34Q-05
LM340-08
LM340-12
LM34Q-15
LM340-18
LM340-20
LM343
LM350
LM3524
LM723
LM723C
LM2935
LM2985
MADll05
MADll06
MADll07
MADll09
UA101A
UA105
UA109
UAlll
UAl17
UA124
UA1489
UA1489A
UA1524
UA201
UA209
UA224
UA238
UA2524
UA301A
UA305
UA305A
UA30B6
UA309
UA311
UA317
UA324
UA338
UA350
UA3524
UAS5450
UA55452
UA55462
UA75450
UA75451
UA75452
UA75453
UA75461
UA75462
UA7805-C
UA7B05-C2
UA7805-M
UA7806-C
UA7B06-C2
UA7806-M
UA78OB-C
UA78OB-C2
UA780B-M
UA7812-C
UA7B12-C2
UA7812-M
UA7B15-C
UA7B15-C2
UA7815-M
UA7620-C
UA7B20-C2
UA7820-M
UA7B24-C
UA7824-C2
UA7B24-M
UA7905-C
UA7905-M
SGREPLACE
SG320-5_2
SG323
SG337
SG338
SG340-05
SG340-08
SG340-12
SG340-15
SG340-18
SG340-20
SG343
SG350
SG3524
SG723
SG723C
SG29055
SG29085
SG5768
SG5770
SG5774
SG61 00
SG101A
SG105
SG109
SGlll
SGl17
SG124
SGl488
SGl489A
SG1524
SG201
SG209
SG224
SG238
SG2524
SG301A
SG305
SG305A
SG3B21
SG309
SG311
SG317
SG324
SG33B
SG350
SG3524
SG55450B
SG55452B
SG55462
SG75450B
SG75451B
SG75452B
SG75453B
SG75461
SG75462
SG7805C
SG7805AC
SG7805
SG7806C
SG7806AC
SG7B06
SG780BC
SG780BAC
SG7BOB
SG7B12C
SG7B12AC
SG7812
SG7815C
SG7815AC
SG7B15
SG7820C
SG7B20AC
SG7B20
SG7824C
SG7B24AC
SG7624
SG7905C
SG7905
CROSS REFERENCE GUIDE
PIN
SG REPLACE
NATIONAL
UA7908-C
UA7908-M
UA79l2-C
UA79l2-M
UA79l5-C
UA79l5-M
UA796
UA9665
UA9666
UA9667
lN5768
lN5770
lN5772
SG7908C
SG7908
SG79l2C
SG7912
SG79l5C
SG7915
SG1596
SG2001
SG2002
SG2003
lN5768
lN5770
1NSn2
SGS
l165
l20l
l202
l203
l204
l272
l60l
l602
l603
l604
l2722
l2726
l7805
l7805C
l7806
l7806C
l7808
l7808A
l78l2
l78l2C
l78l5
l78l5C
l7820
l7820C
l7824
l7824C
l7905
l7905C
l7905.2
l7905.2C
l7908
l7908C
l79l2
l79l2C
L7915
L79l5C
L79l8
L79l8C
L7920
L7920C
LM123
LM2l7
LM223
LM3l7
LM323
LM324
LM324A
LM723
lM74l
LM741C
lS101A
lS204
UlN2001A
UlN2002A
UlN2003A
UlN2004A
UlN2064B
UlN2065B
UlN2066B
UlN2067B
SG3l73
SG2021C
SG2022C
SG2023C
SG2024C
SG3272
SG2821
SG2822
SG2823
SG2824
SG3272
SG3272
SG7805
SG7805C
SG7806
SG7806C
SG7808
SG7808C
SG7812
SG78l2C
SG7815
SG78l5C
SG7820
SG7820C
SG7824
SG7824C
SG7905
SG7905C
SG7905.2
SG7905.2C
SG7908
SG7908C
SG7912
SG79l2C
SG7915
SG79l5C
SG7918
SG79l8C
SG7920
SG7920C
SGl23
SG2l7
SG223
SG3l7
SG323
SG324
SG324A
SG723
SG741
SG741C
SG101A
SG204
SG2001C
SG2002C
SG2003C
SG20D4C
SG2064
SG2065
SG2066
SG2067
PIN
SG REPLACE
UlN2068B
UlN2069B
UlN2070B
UlN2071B
UlN20748
UlN2075B
ULN2076B
UlN2077B
UlN2801A
UlN2802A
UlN2803A
UlN2804A
SG2068
SG2069
SG2070
SG2071
SG2074
SG2075
SG2076
SG2077
SG2801
SG2802
SG2803
SG2804
SPRAGUE
UDN2935
UlN200l
UlN2002
UlN2003
UlN2004
UlN20ll
UlN20l2
UlN20l3
UlN20l4
UlN202l
ULN2022
UlN2023
UlN2024
UlN2045
UlN2064
UlN2065
UlN2066
UlN2067
UlN2068
UlN2069
UlN2070
UlN207l
UlN2074
UlN2075
UlN2076
UlN2077
UlN375l
ULN8l24
UlN8l25A
ULN8l26
UlN8l27A
UlQ8l24
UlQ8l25A
UlQ8l26
UlQ8l27A
UlS200l
UlS2002
SG3635
SG2001C
SG2002C
SG2003C
SG2004C
SG20llC
SG20l2C
SG20l3C
SG20l4C
SG2021C
SG2022C
SG2023C
SG2024C
SG3821
SG2064
SG2065
SG2066
SG2067
SG2068
SG2069
SG2070
SG2071
SG2074
SG2075
SG2076
SG2077
SG3l73
SG3524
SG3525A
SG3526
SG3527A
SG2524
SG2525A
SG2526
SG2527A
SG2001
SG2002
PIN
SGREPLACE
TEXAS INSTRUMENTS
TlO40
lMl01A
lMl07
lMlll
lM137
lM207
lM2ll
lM2l7
lM237
SGl524
SG2524
SN55189
SN55l89A
SN75064
SN75065
SN75066
SN75067
SN75068
SN75069
SN75074
SN75075
SN75188
SN75189
SN75l89A
SN75234
SN7524
SN75325
SN75326
SN75327
SN75430
SN75431
SN75432
SN75433
SN75434
SN75450B
SN75451B
SN75452B
SN75453B
SN75454B
SN75460
SN75461
SN75462
SN75463
SN75464
SN75470
SN75471
SN75472
SN75473
SN75474
SNJ55188
SG040
SG101A
SG107
SGlll
SG137
SG207
SG2ll
SG2l7
SG237
SG1524
SG2524
SG1468
SG1489A
SG2064
SG2065
SG2066
SG2067
SG2068
SG2069
SG2074
SG2075
SG75188
SG1468
SG1489A
SG75234
SG7524
SG75325
SG75326
SG75327
SG75430
SG75431
SG75432
SG75433
SG75434
SG75450B
SG75451B
SG75452B
SG75453B
SG75454B
SG75460
SG75461
SG75462
SG75463
SG75484
SG75470
SG75471
SG75472
SG75473
SG75474
SG1488
PIN
Tl1l7
Tl1525A
Tl1527A
Tl2525A
Tl2527A
SGREPLACE
SGl17
SG1525A
SG1527A
SG2525A
SG2527A
UNITRODE
PIC600
PIC601
PIC602
PIC6l0
PIC6ll
PIC6l2
PIC625
PIC626
PIC627
PIC635
PIC636
PIC637
PIC645
PIC646
PIC647
PIC655
PIC656
PIC657
PIC7501
PIC7502
PIC7503
PIC7504
PIC7505
PIC7506
PIC7507
PIC7508
PIC7509
PIC7510
PIC75ll
PIC7512
PIC7513
PIC7514
PIC7515
PIC7516
PIC7517
PIC7518
PIC7519
PIC7520
PIC7521
PIC7522
PIC7523
PIC7524
PIC7525
PIC7526
SM600
SM601
SM602
SM6l0
SM6ll
SM6l2
SM625
SM626
SM627
SM635
SM636
SM637
SM645
SM646
SM647
SM655
SM656
SM657
SM600B
SM601B
SM602B
SM6l0B
SM6llB
SM6l2B
SM625B
SM626B
SM627B
SM635B
SM636B
SM637B
SM645B
SM646B
SM647B
SM655B
SM656B
SM657B
SM600A
SM601A
SM602A
SM6l0A
SM6llA
SM6l2A
SM625A
SM626A
ULS2003
SG2003
SNJ55189
SG14B9
PIC7527
SM627A
ULS2004
UlS20ll
ULS2012
ULS2013
UlS20l4
ULS2021
ULS2022
ULS2023
UlS2024
UlS280l
ULS2802
ULS2803
UlS2803
UlS2804
UlS28ll
UlS28l2
ULS2814
UlS282l
UlS2822
UlS2823
UlS2824
UlS8l24
UlS8l25A
UlS8l26H
UlS8l27A
SG2004
SG20ll
SG2012
SG2013
SG2014
SG2021
SG2022
SG2023
SG2024
SG2801A
SG2802A
SG2803A
SG28l3A
SG2804A
SG28llA
SG28l2A
SG28l4A
SG2821A
SG2822A
SG2823A
SG2824A
SGl524
SG1525A
SG1526
SG1527A
SNJ55l89A
SNJ55234
SNJ55234
SNJ55236
SNJ55236
SNJ5524
SNJ55325
SNJ55326
SNJ5534
SNJ55450B
SNJ55451B
SNJ55452B
SNJ55453B
SNJ55454B
SNJ55460
SNJ55461
SNJ55462
SNJ55463
SNJ55464
SNJ55470
SNJ55471
SNJ55472
SNJ55473
SNJ55474
Tl1ll
SG1489A
SG55234
SG55234A
SG55236
SG55236A
SG5524
SG55325
SG55326
SG5534
SG55450B
SG55451B
SG55452B
SG55453B
SG55454B
SG55460
SG55461
SG55462
SG55463
SG55464
SG55470
SG55471
SG55472
SG55473
SG55474
SGlll
PIC7528
PIC7529
PIC7530
PIC7531
PIC7532
PIC7533
PIC7534
PIC7535
PIC7535
UCl17
UC120-05
UC120-l2
UC120-l5
UC137
UC140-05
UC140-l2
UC140-l5
UC150
UC1524
UC1524A
UC1525A
UC1526
UC1526A
UC1527A
UC1543
SM635A
SM636A
SM637A
SM645A
SM646A
SM647A
SM655A
SM656A
SM657A
SGl17
SG120-05
SG120-l2
SG120-l5
SG137
SG140-05
SG14D-12
SG140-l5
SG150
2 -11
SG1524
SG1524B
SG1525A
SG1526
SG1526B
SG1527A
SG1543
PIN
UC1825
UC1544
UCl840
UC1842
UCl843
UC1844
UCl845
UC1846
UCl847
UC2l7
UC237
UC250
UC2524
UC2524A
UC2525A
UC2526
UC2526A
UC2527A
UC2540
UC2543
UC2544
UC2825
UC2840
UC2842
UC2843
UC2844
UC2845
UC2846
UC2847
UC3l7
UC320-05
UC320-l2
UC320-l5
UC337
UC340-05
UC340-l2
UC340-l5
UC350
UC3524
UC3525A
UC3526
UC3526A
UC3527A
UC3543
UC3544
UC3717
UC3825
UC3840
UC3842
UC3843
UC3844
UC3845
SGREPLACE
SG1825
SGl544
SG1840
SGl842
SG1843
SGl844
SG1845
SGl846
SG1847
SG2l7
SG237
SG250
SG2524
SG2524B
SG2525A
SG2526
SG2526B
SG2527A
SG2540
SG2543
SG2544
SG2825
SG2840
SG2842
SG2843
SG2844
SG3845
SG2846
SG2847
SG3l7
SG320-05
SG320-l2
SG320-l5
SG337
SG340-05
SG340-l2
SG340-l5
SG350
SG3524
SG3525A
SG3526
SG3526B
SG3527A
SG3543
SG3544
SG3718
SG3825
SG3840
SG3842
SG3843
SG3844
SG3845
UC3846
SG3B46
UC3847
UC7805
UC7805A
UC7805AC
UC7805C
UC7812
UC78l2A
UC78l2AC
UC78l2C
UC7815
UC78l5A
UC78l5AC
UC78l5C
UC7905
UC7905A
UC7905AC
UC7905C
UC7912
UC79l2A
UC79l2AC
UC79l2C
UC7915
UC79l5A
UC79l5AC
UC79l5C
SG3847
SG7805
SG7805A
SG7805AC
SG7805C
SG7812
SG78l2A
SG78l2AC
SG78l2C
SG7815
SG78l5A
SG78l5AC
SG78l5C
SG7905
SG7905A
SG7905AC
SG7905C
SG7912
SG79l2A
SG79l2AC
SG79l2C
SG7915
SG79l5A
SG79l5AC
SG79l5C
•
INDUSTRY PACKAGE CROSS·REFERENCE
SILICON·
GENERAL
Cherry
Silicon
General·
Linear
Tech
Motorola
NSC
Signetics
Sprague
Texas
Instruments
Unitrode
PLASTIC DUAL-IN-LINE (DIP)
•
.~
~.
~
•
.#
,
I
,
,
..
8-Pin
M
N
N8
P1
N
M
P
N
14,16,18,20,22,
&24-Pin
N
N
N
P2
N
A
N
N
16 - Pin (Batwing)
W
24 & 28 - Pin
(Wide)
N
N
B
N
A
NF
PLASTIC SMALL OUTLINE (8.0.I.C.)
OM
S
D
M
D
L
D
D
S
D
M
D
L
D
16,18, & 20 - Pin
OW
S
D
WN
DW
LW
20 - Pin (Batwing)
DWW
8-Pin
14&16-Pin
D
D
LB
PLASTIC (POWSR)
3&5-Pin
(TO-220)
P
T
3 - Pin (TO-247j
V
P
12 - Pin (SIP)
S
12 - Pin (SIP)
ST
T
T
U
Z
W
December 1989
2 -12
KC
T
INDUSTRY PACKAGE CROSS-REFERENCE
Silicon
General
Cherry
Linear
Tech
Motorola
NSC
Signetics
Sprague
Texas
Instruments
Unltrode
EP
FN
Q
JG
J
R
J
J
H
JD
PLASTIC LEADED CHIP CARRIER
•
•.-
20 & 28 - Pin
(PLCC)
V
Q
CERAMIC ,,11.111 .IN. I INJ:
Cf!~..M;~
Y
J
J8
U
J
FE
14,16 (TO-116),
& 18- Pin
J
J
J
L
J
F
H
0
L
0
J
SIDE BRAZED (DIP)
~
I
8- Pin
14,16, & 18 - Pin
CERAMIC FLAT PACK I
~~.
10,16, & 20 - Pin
F
~
14- Pin
24 - Pin
I.
F
U,W
F
F
W
F
F
W
.."'n......... J:anl J:~C:; CHIP CARRIER
<>
20 - Pin (LCC)
L
L
3 (TO-39), 8 (TO-99),
10 (TO-96, TO-l00!, &
12 (TO-l0l) - Pin
T
H
3 - Pin (TO-3)
K
K
3,5, & 9 - Pin
(TO-66)
R
E
G
G,H
H
H
K
K
EK
FK
L
METAL CANS
fTf
~
~
R
"e"Me II~ TO·257
~
3 - Pin
G,IG
2 -13
H
V
K
•
PRODUCT IDENTIFICATION
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
LINEAR INTEGRATED CIRCUITS
xx
xxxxx xx
SG
SG
55325
7805
,--S,M-,-_64..,5r--- _
xxx xxxxx
J
- Example
8838
- Example
R
_ ~ ,..--'-- ;-- - Example
AC
-
r---------------------~-
PRODUCT
(SPS No.) - 4 or 5 digit in-house number for
Spec. Control Drawings
883 - MIL-STO-883
Class B
Class S
JAN - MIL-M-38510 (Integrated Circuits)
SMO - Standardized Military Drawing
(OESC)
JAN - MIL-S-19500 (Oescrete
Components)
~
See data sheets or price" sheet for
individual descriptions and temperature
ranges.
ELECTRICAL GRADES
PROCESSING LEVEL
(optional)
SG - Linear Integrated Circuit
SM - Thick Film Hybrid (See next page)
GENERIC PART NUMBER
~------------------------~
-
~----------------------------~
PACKAGE OPTIONS
M - 8 PIN OIL Plastic
N - 14,16,18,20,22,24,28,40 PIN OIL Plastic
W - 16 PIN Batwing OIL Plastic
o - 14,16, PIN OIL S.O.l.C. Plastic
OM - 8 PIN OIL S.O.l.C. Plastic
OW - 16,18,20 PIN OIL S.O.I.C. Plastic (wide body)
OWW - 20 PIN Batwing OIL S.O.I.C. Plastic
P - 3, 5 PIN TO-220 Plastic
V - 3 PIN TO-247 SIP Plastic
S - 12 PIN SIP Plastic
ST - 12 PIN SIP Plastic (Metal Tab)
Q - 20, 28 PIN Leaded Chip Carrier - Plastic (PLCC)
Y - 8 PIN OIL Ceramic
J - 14,16,18 PIN OIL Ceramic
H - 14,16,18 PIN OIL Ceramic Side Brazed
F - 10,14,16,20,24 PIN OIL Ceramic (CERPAC)
L - 20 PIN Leadless Chip Carrier - Ceramic (LCC)
Z - 2 PIN TO-46 Metal Can
Z - 3 PIN TO-52 Metal Can
T - 3,8,10,12 PIN TO-5 Metal Can
K - 3, 4 PIN TO-3 Metal Can
R - 3,4, 5, 9 PIN TO-66 Metal Can
G - 3, 5 PIN TO-257 (non-isolated hermetic TO-220)
IG - 3, 5 PIN TO-257 (isolated hermetic TO-220)
I
(optional)
A or B - Improved Performance
C - Commercial Temp Range
December 1989
2-14
PRODUCT IDENTIFICATION
SILICON
GENERAL
POWER HYBRID CIRCUITS
LINEAR INTEGRATED CIRCUITS
SM
SM
SM
SM
-
xxx xx x x
-
600
625
645
HR
HR
r-'--
XXXXX
R
R
1
- Example
- Example
K 12345 - Example
- ,---
PRODUCT
SM - Thick Film Hybrid
SPECIAL SCREENING
4 Dr 5 digit in - house number for
Spec. Control Drawings.
I
GENERIC PART NUMBER
PACKAGE DESIGNATOR
See data sheets or price sheet for
individual
descriptions
and
temperature ranges.
R - Metal Can TO-66
K - Metal Can TO-3
I
PARTICLE CONTROL
(Available only with HR construction)
(blank) - Standard
1 - PIND Test
2 - Conformal Coating
CONSTRUCTION I SCREENING
(blank) - Commercial construction, no burn-in
HR - High reliability construction, Burn-in
HTRB 160 Hours
December 1988
2- 15
•
2 -16
THUMB INDEX
SILICON
GENERAL
IIi
III
I
III
III
III
TABLE OF CONTENTS
PART NUMBER INFORMATION
GENERAL INFORMATION
POWER SUPPLY CIRCUITS
MOTION CONTROL CIRCUITS
POWER DRIVER AND
81
81
III
III
.1
~NTERFACE
CIRCUITS
OPERATION AMPLIFIERS AND COMPARATORS
CORE MEMORY CIRCUITS
AUTOMOTIVE CIRCUITS
OTHER CIRCUITS
PACKAGE INFORMATION
ml
APPLICATION INFORMATION
131
SALES OFFICES
3-1
I
I
I
I
I
I
I
I
I
I
I
I
I
•
QUALITY ASSURANCE
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
From its beginning in 1969, Silicon General has been committed to excellence in the
manufacture of Linear Integrated Circuits.
Over the years, innovative design and the dedication to high quality manufacturing principles
has seen the product line expand in scope and grow in customer acceptance.
Silicon General is committed to the concept that the ultimate quality of a device is determined
by the company's exacting design and manufactuing process controls. The'Statistical
Process Control program (SPC) at Silicon General is in effect and has a high management
directive to continue to improve. Our dedication to a zero defects program, through process
control, has largely been realized through the Total Quality Management concept currently
in place.
We understand that satisfaction to the customer is achieved by delivering a high quality
product on time. Silicon General assures this through close customer working relationships
and a dedication to personal service.
QUALITY ASSURANCE MANAGER
November 1988
3-2
QUALITY ASSURANCE
SILICON
GENERAL
SCREENING PROCEDURES
FOR LINEAR INTEGRATED CIRCUITS
LINEAR INTEGRATED CIRCUITS
Silicon General manufactures hermetic products to the three standard levels of quality assurance
processing outlined below. In addition, the company's unique flexibility allows ready accommodations
to special customer requirements. The following Class S and Class B screening procedures are in
compliance to MIL-M-38510 and all methods are as detailed in MIL-STD-883.
Screen
MIL·M·3B510, Class S
Method
Reqm't
MIL·M-38510, Class B
Method
Reqm't
Standard Product
Method
Reqm't
Wafer Lot Acceptance
5007
Sample
N/A
N/A
Non-Destructive Bond Pull
2023
100%
N/A
N/A
Internal Visual (Pre-Cap)
2010, Condition A
100%
2010, Condition B
100%
Commercial Visual
100%
Stabilization Bake
100B, Condition C
24 Hours @ lS0°C
100%
100B, Condition C
24 Hours @ lS0°C
100%
100B, Condition C
24 Hours@ lS0°C
Optional
Temperature Cycling
1010, Condition C
10 Cycles,
-65°C to +lS0°C
100%
1010, Condition C
10 Cycles,
-65°C to +150°C
100%
1010, Condition C
10 Cycles,
·6SoC to +150°C
Optional
Constant Acceleration
2001, Applicable
100%
Condition per Package Type
2001, Applicable
100%
Condition per Package Type
2001, Applicable
Optional
Condition per Package Type
Particle Impact Noise Detection (PIND)
2020, Condition A
N/A
N/A
Hermeticity (Seal)
a) Fine Leak
b) Gross Leak
1014, Condition B
S x 1O~ atm-cc/sec
1014, Condition Cl
100%
100%
1014, Condition B
S x 10" atm-cc/sec
1014, Condition Cl
100%
100%
1014, Condition B
S x 10-' atm-cc/sec
1014, Condition Cl
Sample
Sample
Pre-Bum-In Electrical Test
Per Applicable Device Spec.
Unit Serialization as required
Per Applicable Device Spec.
Per Applicable Device Spec.
Burn-in Test
101S, Dynamic
100%
240 Hours@ 125°C Minimum
(Note: An additional 72 Hrs
HTRB burn-in and interim
electrical test as required)
1015, Static or
100%
Dynamic
160 Hours@ 125°C Minimum
or equivalent
N/A
Final Electrical Test
a)DC@2S0C
b) DC@ Max. and Min. Rated Temp.
c) Dynamic @2SoC
d) Functional @2SoC
Per Applicable Device Spec.
100%
100%
100%
100%
Per Applicable Device Spec.
100%
100%
100%
100%
Per Applicable Device Spec.
100%
Sample
100%
100%
1014, Condition B
S x 1O~ atm-cc/sec
1014, Condition Cl
100%
N/A
N/A
100%
N/A
N/A
Method 2012
100%
N/A
N/A
External Visual
Method 2009
100%
Quality Conformance Testing
Group A
SOOS
DC, AC Parameters
Hermetlcity (Seal)
a) Flne Leak
b) Gross Leak
Radiography
Groups B, C (Class B only), 0
SOOS Paragraph
+2SoC
+12SoC
-SsoC
3.S
January 1990
3-3
Method 2009
SOOS
DC, AC Parameters
SOOS Paragraph
100%
+2SoC
+12SoC
-SsoC
3.S
Method 2009
100%
DC, AC Parameters
+25°C
•
QUALITY ASSURANCE
SILI[ON
GENERAL
LINEAR INTEGRATED CIRCUITS
SCREENING PROCEDURES FOR
HIGH RELIABILITY POWER HYBRID CIRCUITS
Screen
Method· MIL-sTD-883
Internal Visual (Pre~Cap)
2017, Condition B
100%
Conformal Coating
SG Internal Spec.
(optional)
StabiDzatlon Bake
1008, Condition C
24 Hours @ 150°C
100%
Temperature Cycling
1010, Condition C
10 Cycles, -65°C to +150°C
100%
Constant Acceleretion
2001, Condition B
20,000 g, V, orientation (R - Pkg.)
5,000 g, V, orientation (K - Pkg.)
100%
Particle Impact Noise Detection (PINO)
2020, Condition B
(optional)
1014, Condition B
S x 10" atm-cc/sec
1014, Condition Cl
100%
Hermetfcity (Seal)
a) Fine Leak
b) Gross Leak
Requirement
Comments
Per Applicable Device Specification
100%
Functional Test
100%
Per Applicable Device Specification
Pre-Burn-In Electrical Test
Per Applicable Device Specification
100%
Unit Serialization as required
Bum-in Test
101S, Static Condition A (HTRB)
160 Hours
100%
Consult Factory for Other Screening
Procedures
Final Electrical Test
a)OC@2SOC
b) DC @ Max. and Min. Rated Temp.
c), Dynamic@25°C
d) Functional @2SoC
e)AC@2SOC
Per Applicable Device Specification
Hermelicity (Seal)
a) Fine Leak
100%
100%
100%
100%
100%
1014, Condition B
5 x 10" atm-cc/sec
1014, Condition Cl
100%
External Visual
Method 2009
100%
Quality Conformance Tes~ng
Group A
S008
DC, AC Parameters
b) Gross Leak
Groups B, C, 0
100%
+25°C
+125°C
-S5°C
Sample Testing
December 1988
3-4
Subgroups 1, 4, 7, 9,
Subgroups 2, 8, 10
Subgroups 3, 8, 11
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
QUALITY ASSURANCE
JANTX & JANTXV SCREENING PROCEDURES
FOR MIL-S-19500/474 DIODE ARRAYS
Screen
Method - MIL-STD-750
Requirement
Internal Visual (Pre-Cap)
MIL-STO-883
Method 2010 Condo B
Stabilization Bake
1032
24 Hours @ 200'C
100%
Temperature Cycling
1051
20 Cycles, -65'C to +175'C
100%
Constant Acceleration
2006
20,000 g, Y, orientation
100%
Hermeticity (Seal)
a) Fine Leak
1071
JANTXVonly
Specified in MIL-S-19500/474
•
100%
b) Gross Leak
100%
Pre-Bum-in Electrical Test
Per Applicable Device Specification
100%
Burn-in Test
1038
72 Hours @ 150'C
100%
Final Electrical Test
a)DC@25'C
b) DC@ Max. and Min. Rated Temp.
c) Delta Measurements
Per Applicable Device Specification
Quality Conformance Testing
Group A
External Visual
DC, AC Parameters
GroupsB&C
Comments
As specified in MIL-S-19500/474
100%
100%
100%
+25'C
+150'C
-55'C
Sample Testing
January 1990
3-5
Subgroup 1
Subgroups 2, 4, 6, 7
Subgroup 3
Subgroup 3
3-6
QUALITY CONFORMANCE
SILICON
GENERAL
CLASS S MIL-M-38S10 Q.C.I.
LINEAR INTEGRATED CIRCUITS
QUALITY CONFORMANCE INSPECTION (Q.C.I.)
The following Group Band D tests are performed on a periodic basis or when specified by the customer.
This testing is in compliance to MIL-M-38510 as detailed in MIL-STD-883, Method 5005.
•
Samples Taken Periodically
From Production Lots
Group A Testing Each Lot
I
I
Group B
Construction and Die
Related Tests
Group D
Package Tests
December 1988
3-7
CLASS S MIL-M-38510 Q.C.I.
Group B
GROUPS
Construction and Die
Related Tests
Delta Computations
are optional
3-8
CLASS S MIL-M-38510 Q.C.1.
Group 0
•
3-9
QUALITY CONFORMANCE
SILICON
GENERAL
CLASS B MIL-M-38510 Q.C.I.
LINEAR INTEGRATED CIRCUITS
QUALITY CONFORMANCE INSPECTION (Q.C.I.)
The following Group B. C and D tests are performed on a periodic basis or when specified by the
customer. This testing is in compliance to MIL-M-38510 as detailed in MIL-STD-883, Method 5005.
Samples Taken Periodically
From Production Lots
Group A Testing Each Lot
I
I
Group B
Construction Tests
GroupC
Die-Related Tests
September 1989
3 -10
Group b
Package Tests
CLASS B MIL-M-38510 Q.C.I.
Groups Band C
Resistance to
Solvents
Method 2015
GROUPS
GROUPC
Construction Tests
Die-Related Tests
Subgroup 3
3 Units Min.
No Failures
n+5Units
Solderability
Method 2003
3 Units Min., 22 Leads
Subgroup 1
LTPD.5
Bond Strength
Method 2011
4 Units, 15 Wires
Read and Record
Electrical Test
Operating Life Test
1OOOHrs. @ 125°C
or Equivalent
Method 1005
168 Hours
Read and Record
Electrical Test
504 Hours
Read and Record
Electrical Test
1000 Hours
Read and Record
Electrical Test
Read and Record
Electrical Test
Delta Computation·
Delta Computations
are optional
3 -11
•
CLASS B MIL-M-38510 Q.C.I.
Group D
3 -12
QUALITY CONFORMANCE
SILICON
GENERAL
JAN, JANTX, JANTXV MIL-S-19500 Q.C.1.
LINEAR INTEGRATED CIRCUITS
QUALITY CONFORMANCE INSPECTION
The following Group Band C tests are performed on a periodic basis or when specified by the customer.
This testing is in compliance to MIL-S-19500 Class B quality is shown below.
•
Samples Taken Periodically
From Production Lots
Group A Testing Each Lot
I
1
Group B
Construction and Die
Related Tests
Group C
Die Related and Package Tests
December 1988
3-13
JAN, JANTX, JANTXV MIL-S-19500 Q.C.I.
Group B
When specifically
required
3-14
JAN, JANTX, JANTXV MIL-S-19500 Q.C.I.
Group C
•
3-15
CAPABILITIES
SILICON
GENERAL
MILITARY PRODUCTS
LINEAR INTEGRATED CIRCUITS
PROCESS CAPABLILITIES
Silicon General offers a variety of design, test and processing capabilities that specialize in meeting the specific requirements of the
military customer.
This commitment to the military marketplace has led Silicon General to staff and operate a fully certified MIL-M-38510 as well as
MIL+19500 facility. This unique combination encompassing both discrete and microcircuit components solutions has proven valuable in solving the miitary customers needs.
The JAM market has become a vital part of our business and Silicon General has introduced a broad offering of components to support
it. In addition to our current list of QPL devices we have developed an extensive list of products scheduled for future JAN qualification.
These products will help to support the military's thrust for product standardization. Silicon General believes that this understanding
of severe environment components has improved the quality of our entire product offering.
SILICON GENERAL SPECIFICATION PROGRAMS
• MIL-M-38510 - JAN
• MIL-S-19500 - JAN, TX, TXV
• DESC Drawings
• MIL - STD - 883
• MIL - STD - 750
• Source Control Drawings
ADDITIONAL - HIGH RELIABILITY OPTIONS
In addition to the process capabilities required by our military certification, we also offer the following process options for our space level
and Ultra-High Reliability applications.
•
•
•
•
•
•
PIND Testing
X- Ray
Radiation Testing
SEM Analysis and Wafer Lot Acceptance
Customer Source Inspection Program
Custom Data Capability
This combination of small company customer service philosophy with large company capability has enabled Silicon General to become
a key supplier in a broad range of High Reliability programs.
Contact Silicon General for a current listing of our JAN QPL and DESC DWG qualifications.
December 1988
3 -16
CAPABILITIES
SILICON
GENERAL
CUSTOM AND SEMI-CUSTOM
INTEGRATED CIRCUITS
LINEAR INTEGRATED CIRCUITS
INTRODUCTION
Silicon General offers a wide range of full custom and semi-custom
integrated circuits processed in a MIL-M-38S10 and MIL-S-19S00
certified facility.
CUSTOM CIRCUIT TECHNOLOGY
Full custom ICs are unique circuit topologies defined by the end
user. By contrast, semi-custom ICs are circuit modifications and
extrapolations of existing Silicon General devices. This might be
as simple as unique electrical test programs or special packaging
or as extensive as actually altering the original circuit design.
Silicon General has several circuit technologies to chose from in
the design of a custom or semi-custom I.C. This choice can be
defined by the end user or recommended by Silicon General.
These technologies are shown in Table 1.
TABLE 1 - CUSTOM CIRCUIT TECHNOLOGIES
Bipolar
0 Hybrids
o Gold - doped Bipolar • Silicon - on - Insulator
• CMOS
o
CUSTOM CIRCUIT CAPABILITY
The important characteristics for each of the technologies mentioned above in Table 1 are listed in the following section. These
characteristics provide only a baseline as new'processing mod-
ules ani continually being developed. Please consult the factory
for the latest innovations being made.
Bipolar
The details in Table 2 show the characteristics of the various
junction isolated bipolar processes used at Silicon General.
TABLE 2 - BIPOLAR PROCESS CAPABILITIES
Process
FT
12V
lGHz
20V
600MHz
40V
400MHz
60V
2S0MHz
Discrete
N/A
Min.
HFE
Min.
VCBO
Min.
VCEO
Current
Rating
Double
Layer Metal
Schottky
Gold
Doping
Implant
Resistor
Polysilicon
Resistor
SO
SO
SO
SO
SO
2SV
40V
60V
80V
lS0V
14V
20V
40V
60V
100V
100mA
SA
SA
SA
30A
Yes
Yes
Yes
No
No
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
N/A
No
Yes
Yes
Yes
N/A
Along with the broad bipolar processing capabilities, Silicon
General offers proven building blocks with extensive reliability
histories and known levels of operational performance. These
blocks can be used as is or modified to accomodate an end users
needs. Table 3 details the building blocks used extensively on
Silicon General standard and custom/semi-custom circuits.
TABLE 3 - IC BUILDING BLOCKS
• Pulse Width Modulation techniques for switching power
supplies and motor control applications
., Bandgap voltage references (tolerance < 1%)
• Oscillators
• Low dropout output stages (e.g. dropout <1V at 7S0mA)
• Various comparators and op-amps
• Full Logic
- Gates, Flip Flops, Schmitt Triggers etc.
- TTL, Schottky TTL, EFL, ECL, J2L
- Gate Delays ~ 3nsec
• Discrete Transistor / Diode Arrays
• High Current, High Voltage Power Stages
December 1988
3-17
•
CUSTOM AND SEMI-CUSTOM Ie's
CUSTOM CIRCUIT CAPABILITY (continued)
CMOS
Silicon General' has in-house capability to develop Standard Cell
or full custom CMOS I.C.'s. These I.C.'s are then processed at
qualified outside foundries. This CMOS capability combined with
the broad bipolar background enable Silicon General to aid in the
partitioning of many end users applications. Current CMOS
capabilities are listed in Table 4.
TABLE 4 - CMOS CAPABILITIES
• Geometries from 2.0)lmto 1.2)lm
• Standard Cell Library tnat includes:
- 7400 SSIIMSI Logic Family
- Static RAM to 64K
, • CAD tools available:
- Auto Place and Route (Standard Cell and Block)
- Schematic Capture
- Schematic Simulation
- Layout vs. Schematic Checking (LVSf
- Design Rule Checking (DRC)
- Electrical Rule Checking (ERC)
Hybrid
A long history exists in the design and manufacture of thick film
hybrids forthe military, automotive, and commercial markets. For
those applications where a single monolithic approach is not
attainable Silicon General can combine a standard, custom or
semi-custom I.C. with other components into a cost-effective,
size efficient hybrid. Current thick film hybrid capabilities are
listed in Table 5.
TABLE 5 - HYBRID CAPABILITIES
• Surface Mount or Chip and Wire technologies
• Custom Hybrid Packaging for both low and high power
applications
'
• Full Military Processing
• Laser trimmed resistors:
- 0.5% absolute value
- 0.2% matching
• Conformal Coating
Silicon on Insulator (501)
Currently under development is a proprietary state of the art SOl
process designed specifically to improve the radiation hardening
capability of Military I.C.'s produced at Silicon General. First
product introduction will occur in 1989. The details of this process
are shown on page 3-18. Target characteristics are listed in Table
6.
TABLE 6 - SOl CHARACTERISTICS
• Transistor isolation to 750V
• Minimum VeBO = 130V, VCEO = 80V
• Maximum Current Rating to 5A
• 'Dual Layer metal, Schottky, and gold doping capability
• 'FT'upto 6GHz
• Implant and Polysilicon resistors
PACKAGING ALTERNATIVES
Packaging alternatives are presented in Table 7. These range
from the more common DIP to newer packages like the hermetic
TO-220 and full custom packages. Trade-offs can be made concerning power handling capability, size, hermeticity and cost. The
8J~ and 8 JA values and package dimensions are given for most of
these packages in Section 11 of this catalog. Silicon General
product engineers are well equipped to assist in selecting the best
package for your particular requirements.
TABLE 7 - PACKAGING ALTERNATIVES
• Ceramic and plastic dual in line
• Ceramic and plastic leadless and leaded chip carriers
(.I-lead available)
• Ceramic flatpacks
• Plastic S.O.I.C.
•
•
•
•
3 -18
Metal Can (TO-3, TO-5, TO-39, TO-46, TO-52, TO-66, TO-99)
Hermetic TO-220 and plastic TO-220 outline package
Power SIP
,Custom hermetic and plastic packages
CUSTOM AND SEMI-CUSTOM IC's
CUSTOM CIRCUIT PROCESSING LEVELS
Silicon General's custom circuit experience is extensive. We
have produced custom ICs for some of the most demanding environments, both military and commercial. Our custom circuits
can be found on satellites, radar systems, gyroscopes, automobiles, missile systems, disc drives and catalog power supplies.
Table 8 contains a partial list of the processing levels available for
custom circuits. This flexibility in processing combined with a MILM-38510, MIL-S-19500 approved facility results in a custom
circuit supplier able to handle virtually all special program and
end-user requirements.
TABLE 8 - CUSTOM CIRCUIT PROCESSING LEVELS
• MIL - STD - 883
Class B
Class S
• MIL-STD-750
JAN
JANTX
JANTXV
• Die processing; MIL - STD - 883, Level B, Level S
•
•
•
•
•
•
•
Military (-55°C to 125°C)
Automotive (-40°C to 125°C)
Industrial (-25°C to 85°C)
Commercial (O°C to 70°C)
Extended temperature range
Wafer traceability, wafer lot acceptance, SEM
Special processing (end user defined)
CONCLUSION
Silicon General is committed to building long-term customer relationships. To be a valued supplier; we must provide, on
time, a quality product, which meets not only the customer specification but the device application as well. Our military
certified facility and production capability, both military and commercial, define Silicon General as a custom IC supplier
able to support virtually any end-user requirement.
Silicon General has the production resources, technical expertise and commitment to quality to provide a TOTAL
SERVICE (end-user defined) custom integrated circuit program.
.
3 -19
•
CAPABILITIES
SILICON
GENERAL
RADIATION HARDENED
INTEGRATED CIRCUITS
LINEAR INTEGRATEO CIRCUITS
INTRODUCTION
After successfully participating in most of the strategic military and
space programs of the last two decades, Silicon General is
focusing its efforts in these areas by forming a division that will
design and produce RADIATION HARDENED linear integrated
circuits. The RAD HARD IC TECHNOLOGIES Division, in
conjunction with Silicon General's established Level "S" and
custom processing programs, will be able to better serve the
needs of today's demanding space and military programs by
providing radiation hardened custom and standard linear ICs.
RAD HARD TECHNOLOGY
The RAD HARD Ie TECHNOLOGIES Division begins the design
of a radiation hardened device by studying the customer's radiation and electrical performahce requirements to determine required device geometries and radiation hardening techniques.
Circuit simulations are used to verify device performance; prototypes are provided to the customer to verify system performance.
In this way Silicon General reduces the risk of a radiation or
electrical specification issue when the final product is delivered.
Manyfactors are considered butthe major areas of concern when
designing a device for specific radiation performance are the
device electrical design, circuit layout and fabrication processes.
Listed below are some olthe techniques used by Silicon General.
DESIGN / LAYOUT CONSIDERATIONS
• Beta degradation tolerant electrical design ensures the system designer worst case electrical specification after the radiation
event.
• Photocurrent compensation is used to minimize the circuit upset during a radiation event.
• In junction isolated devices, NPN and PNP transistors are spaced for maximum radiation tolerance.
FABRICATION PROCESSES
• The key fabrication process used at Silicon General for radiation hardening is a propretary process called T1SER (See figure
t). The acronym stands for Trench Isolated Selective Epi Regrowth. It is a Silicon On Insulator process that offers many
advantages over older isolation techniques, such as Dielectric Isolation. T1SER is used in any circuit design requiring low
photo current generation or latch-up free operating during a Gamma Dot event.
Si Wafer
Figure 1. NPN Transistor
• Buried zener references are used instead of surface zeners to minimize the effect of surface charge build-up.
• Other fabrication processes, such as Sub metal Nitride Passivation, Double diffused PNP transistors, and Oxide Isolated
resistors, are also used.
In addition to custom radiation hardened designs, Silicon General plans to introduce a line of rad hard "industry standard" linear devices,
e.g., LM117, LM137, ...
Please call Silicon General or your local Silicon General representative for more information.
January 1990
3 - 20
THUMB INDEX
SILICON
GENERAL
.1
III
81
I
81
III
81
III
III
III
III
III
III
TABLE OF CONTENTS
PART NUMBER INFORMATION
GENERAL INFORMATION
POWER SUPPLY CIRCUITS
MOTION CONTROL CIRCUITS
POWER DRIVER AND INTERFACE CIRCUITS
OPERATION AMPLIFIERS AND COMPARATORS
CORE MEMORY CIRCUITS .
AUTOMOTIVE CIRCUITS
OTHER CIRCUITS
PACKAGE INFORMATION
APPLICATION INFORMATION
SALES OFFICES
4-1
I
I
I
I II
I
I
I
I
I
I
I
I
I
SELECTION GUIDE
POWER SUPPLY CIRCUITS
SILICON
GENERAL
SWITCHING REGULATOR CONTROL IC's
LINEAR INTEGRATED CIRCUITS
I
PERFORMANCE CHARACTERISTICS
DEVICE TYPE.
Voltage Mode PWM
.
SK31527A12527At.3527A
·
· ··• ·
·• •• ·• ·• ·•
SG152612526J3526
•
•
•
•
••
SG1526B125268V3526B
•
•
•
•
••
SG15241252413524
SK31524BV25248V3524B
SG1525A12525At3525A
40V
300KHz. 2
·
500KHz. 2
•
100mA
60V
<50%
J, N, 0, F, L
•
<50%
J, N, OW, F, L
<50%
J, N, OW, F, L
<50%
J.. N, OW, F, L
<50%
J, N, OW, F, L
<50%
J,N,OW
• N/A • <100%
J,N,OW
200mA
35V
500KHz
2
400KHz
2
• • •
• • •
• • • •
550KHz
2
• • • •
0.4A
35V
0.4A
35V
O.4A
SG1529/252913529
SG1840/284013840
·• ·
······
•
•
60V
• 500KHz. 2
200mA
30V
• 500KHz. 1
·
•
400mA
Current Mode PWM
SG1528J252813528
SG153012530/3530
SK318251282513825
• • • • •
• • • • •
• • • • • •
22V
•
3M Hz
1
•
2MHz
2
3A
30V
• • N/A •
•
• •
• • • • •
<50%
<100%
<50%
J, N, OW, F,L, Q
•
• N/A •
•
•
•
•
•
•
•
•
•
• • • •
• • • •
<100%
J, N, Y, M, 0, F, L
<50%
J, N, Y, M, 0
<50%
J, N, OW, F, L
J,N,OW
1.5A
SK318421284213842
SG184312843J38.43
SG18441284413844
SG1845/2845J3845
SG184612846Js84Ei
SG18471284713847
•
•
•
• • •
• • •
• • •
•
• • • •
• • • • • •
· ··
··
30V
• 500KHz
1A
•
•
•
40V
500mA
• 500KHz
•
November 1988
4-2
1
2
SELECTION GUIDE
POWER SUPPLY CIRCUITS
SILICON
GENERAL
POWER SUPPLY SUPPORT FUNCTIONS
LINEAR INTEGRATED CIRCUITS
Device Type
SG1540/2540/3540
Description
Key Features
Packages
011- line start up controller.
•
•
•
•
•
Eliminates bulky 50/60Hz transformer.
Minimizes high voltage bleeder current.
Usable with primary or secondary PWM conto\'
Programmable start up voltage.
Programmable over voltage latch.
Y,M, DW, F
Power factor controller
•
•
•
•
•
•
Micro-power start-up mode
Low operating current consumption
Internal 5% reference
Totem pole output stage
Automatic current limiting of Boost stage
8-pin DIP plastic package
Over/under voltage
• Operation from 4.5V to 40V
• Useful for either over- or under-voltage sensing
Minimizes the cost and
complexity of auxiliary
power supply.
SG3561
SG15421254213542
protection circuit
•
•
•
•
•
•
SG3523N3523
SG3423N3423
Over voltage protection
circuit
SG1543/2543/3543
SG1544/2544/3544
Power supply supervisory
circuit. Monitors and controis power supply output.
J, N, D, F
Built-in input hysterisis
Zero to 35V sensing capability
Programmable time delay
SCR "Crowbar" drive of 200mA
Remote activation capability
2.6V 1% reference available
• Operation from 4.5V to 40V
• Highly accurate sensing threshold
•
•
•
•
Y,M
Y,M
Built-in input hysteresis
Programmable time delay
SCR 'Crowbar" drive of 200mA
Remote activation capability
• Over-voltage, under-voltage, and current sensing circuits are all included
• Programmable time delays
• Internal 1% accurate reference available
J, N, DW,
F,L
• Open collector outputs
• Remote activation capability
• SCR 'Crowbar" drive of 300mA
• Optional over voltage latch
• Uncommited comparator
• Inputs for low voltage sensing (SG1544 series only)
SG154812548/3548
Quad power fault monitor.
Monitors and controls four
power supply outputs.
• Over-voltage and under-voltage sensing on four power supply outputs
• Programmable time delay
• Internal 1% accurate reference available
• Open collector outputs.
• Adjustable fault window
• On-chip inverting op-amp for negative voltage
• Additional input for AC line monitoring
December 1989
4-3
J, N, DW, L
•
SELECTION GUIDE
POWER SUPPLY CIRCUITS
POWER SUPPLY SUPPORT FUNCTIONS
Device Type
Description
Key Features
SG15491254912549
Current sense latch. Monitors power supply output
current.
•
•
•
•
•
SG1557/255713557
SG1559/255913559
SG1560/2560/3560
Low cost MAG-AMP controller. Controller for magnetic amplifiers or secondary side control applications.
• Lower cost than combined comparable discrete parts
• Two independent op-amps (1557/59 series)
• Two uncommited open collector comparators (1557/59 series)
• ±2% voltage reference over line, load and temperature
• Low input voltage operation
• 13V zener for pre-regulating +V'N (1557/59 series)
• Intemall OOmV offset voltage built in one olthe comparators (1559 series only)
SG1626/262613626
SG1644/2644/3644
SG1627/2627/3627
SG1629/2629/3629
High speed driver (Inv.)
High speed driver (N.I.)
Dual uncommited output
driver
Bipolar driver
SG103/203/303 SG15031250313503
Voltage reference
Voltage reference
"
Packages
Current sense latching circuitry
Separate terminals for high and low common mode input sensing
Automatic reset from PWM clock
Complementary outputs available
Low propagation delays (180ns)
SEE POWER DRIVER AND INTERFACE SECTION
SEE OTHER LINEAR CIRCUITS SECTION
4-4
Y,M
J, N, Y,M,
DW
SELECTION GUIDE
POWER SUPPLY CIRCUITS
S~L~CON
GENERAL
I'
VOLTAGE REGULATORS
LINEAR INTEGRATED CIRCUITS
PERFORMANCE CHARACTERISTICS
Device Type
Output
Current
Polarity
SG138!138A
5A
Positive
SG150
3A
Positive
1.5A
Positive
SG117!117A
SG117HV!117AHV
SG140
Positive
SG7800
SG109
Positive
SG137!137A
Negative
SG137HV
Negative
SG790017900A
Max. Input
Low
Dropout
Voltage
·
·•
·
·
·
0.75A
SG29125!125A'
Positive
0
Positive
•
Positive
0.5A
Positive
·
SG117Hv/117AHV
Output
Voltage (V)
Package
35V
1.2Vto38V
K(TO-3)
35V
1.2Vto 33V
K (TO-3), P (TO-220)
35V
1.2Vto 37V
K (TO-3), R (TO-66),
60V
1.2Vto 57V
P (TO-220),
35V
5,6,8,12,15,
G (Hermetic TO-220).
18,20,24
IG (Hermetic TO-220)
35V
5V
35V
-1.2V to -37V
60V
-1.2V to -57V
35V
-5, -5.2, -8, -12,
-15 -18, -20
0
SG29085!85A'
SG117!117A
·•
·
Adjustable Dual
0
SG120
SG29055!55A'
Fixed
•
•
·
•
· .
0
0
26V
5V,5V
26V
8V,5V
26V
12V,5V
35V
1.2Vto 37V
60V
1.2Vto 57V
5,6,8,12,15,
SG780017800A
Positive
0
35V
SG109
Positive
•
35V
5V
SG137!137A
Negative
35V
-1.2V to -37V
P (TO-220)
T (TO-39)
18,20,24
0
SG137HV
SG120
Negative
SG790017900A
SG1532
0.1A
SG723
Positive
Positive
SG1501A
Negative!
Positive
0
·
·
Negative!
SG1502
Positive
SG1568
Positive!
·
60V
-1.2V to -57V
35V
-5, -5.2, -8, -12,
-15, -18, -20
•
•
·
· ·
•
0
2Vto 38V
50V
2Vto 38V
±35V
±15V
±30V
±10Vto±28V
±30V
±15V
J, N, T
50V
4.5Vt040V
J, N, T
-50V
-O.015V to -40V
Negative
SG105
O.02A
SG104
Positive
Negative
J, N, T
50V
J, N,
(TO-96)
T (TO-100)
J, N
(TO-100)
R (TO-66)
•
•
• See Automotive Section
December 1989
4-5
(TO-99)
T (TO-100)
•
SELECTION GUIDE
POWER SUPPLY CIRCUITS
SILICON
GENERAL
SWITCHING REGULATOR OUTPUT STAGE
LINEAR INTEGRATED CIRCUITS
PERFORMANCE CHARACTERISTICS
Device _OUtput
current,
Type.,'
-':"" .
SM645
20.6; -
"
Polarity
Positive
Input/Output Rlaenme(ns) Fall nme (ns)
On-State Voltage
VoltageM
Voltage
Current
Current
Diode
Trell8latcii'.
:'
Volta"e
60
60
150
175
300
60
175
300
300
60
150
175
300
Packages
1.5V@7A 1.25V@7A
K(TO-S)
1.5V@7A 1.25V@7A
R (T0-66)
. " .
~'
SM646
'
80
SM647
100
Negative
SM655
60
SM656
80
SM657
100
,"
SM625
,
~15A
Positive
60
~'
Isolated
~; ';
"
80
SM626
;,: '.~
"
100
SMe27•• : " it
SM635
)~" ( ~ ~
.
"
Negative
... ..
SM636
60
60
175
300
300
60
150
175
300
80
100
SM637
SM660
1M
Positive
60
1,5V@5A 1.25V@5A
R (TO-66)
Isolated
SM661
80
SM662
100
Negative
SM670
60
SM671
80
SM672 ,
100
'SA
SM600
Positive
60
60
175
300
300
50
75
75
150
,.
:
SM601
80
100
SM602
Negative
60
50
75
"
SM611
80
, '
100
SM612
1.0V@2A
R (TO-66)
Isolated
.
SM61 0
1.5V@2A
0
November 1988
4-6
75
150
SGI041SG2041SG304
SILICON
GENERAL
NEGATIVE VOLTAGE REGULATOR
LINEAR INTEGRATEO CIRCUITS
DESCRIPTION
FEATURES
This circuit is a negative voltage regulator designed for both linear and switching applications. It is a complement olthe SGt 00/200/300, SGt 05/205/305 and
SG723!723e intended for systems requiring regulated negative voltages having a common ground with the unregulated supply. With an input voltage rating
of up to 50 volts, this device will deliver load currents to 25 milliamps. Adding
external transistors will increase the current capability to greater than t Oamps
and further improve regulation.
• Output voltage adjustable from 15mV to
40V
• lmV regulation no load to full load
• O.OI%IV lin regulation
• 1% maximum temperature variation
The SGt 04 will operate overthefull military ambienttemperature range of -55°e
to +t25°e. The SG204 operates over the temperature range of -25°e to 85°e
while the SG304 is designed for commercial applications of ooe to 70 oe.
• Available to MIL·STD·883B
• SG level "S" processing available
HIGH RELIABILITY FEATURES· SG104
BLOCK DIAGRAM
,
ADJUSl'MENT
GROUND
R'2
'5K
R'3
'5K
REGULATED OUTPUT
R,.
'K
BOOSTER OUTPUT
a,
R2
7.BK
'--......---<~-+--+---+--+-...........::
CURRENT UM'T
R7
2.2K
-j-_+_......__--'.. '-:.:::.:...__.,..--"
L-._ _ _ _ _ _ _
C2
15pF
REFERENCE
REFERENCE
SUPPLY
COMPENSAliON
April 1990
4-7
UNREGULATED 'NPUT
•
SG104/SG204/SG304
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage
SG104, SG204 ................................................................
SG304 ..............................................................................
Input - Output Voltage Differential
SG104, SG204 ................................................................
SG304 .............................................................................
Operating Junction Temperature
Hermetic (T-Package) .................................................. 1S0°C
Power Dissipation ........................................................ SOOmW
Storage Temperature Range ............................ -6SoC to 1S0°C
Lead Temperature (Soldering, 10 seconds) .................... 300°C
SOV
40V
SOV
40V
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL DERATING CURVES
10.0
2.'
2.0
•.0
~
~
~
I
~
~
c
~
~
I.'
I
1.0'-
~
ill
is
N'o..
.....
0
2.
.0
75
4.0
~
~~
D.•
0
6.0
"
~tia...."
I~
~
2.0
"-'-
100
12.
150
I"
0
17.
0
2.
'0
75
100
"-
12.
,.0
175
AMBIENT TEMPERATURE - "C
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage
SG104, SG204 ....................................................... 8V to 48V
SG304 .................................................................... 8V to 38V
Input - Output Voltage Differential
SG104, SG204 ....................................................... 4V to 47V
SG304 .................................................................... 4V to 37V
Operating Ambient Temperature Range
SG104 ........................................................... -SsoC to 12SoC
SG204 ............................................................. -2SoC to 8SoC
SG304 ................................................................ O°C to 70°C
Note 2: Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SGI 04 wHh -55°C :s; T.:s; 125°C, SG204 with -55°C
:s; T.:s; 125°C, SG304 with -55°C:s; T.:s; 70°C. Temperature drift effects must be taken into account separately when the unit is operating under conditions
of high dissipation. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambienttemperature.)
Parameter
Input VoltaQe.Range
Output Voltage Range
Outpuf-lnput'Voltage
Differential (Note 2)
Load'Aeg~l~ori (Note 3)
Line Regulation (Note 4)..
Ripple Rej~ron '
Test Conditions
SG104/204
SG304
Units
Min. Typ. Max. Min. Typ. Max.
,,-8 -40
V
-8
-40
V
O.Q1S -30
0.03!:
V
2.0
50 2.0
40
O.S
V
SO 0.5
40
1 '5
1
5 mV
0.OS6 0.1
0.OS6 0.1
%
-so
,.
·lo .. 20mA
, 10= SmA.. ,
.~ ,OS 10S20mA,
-150
VOUT S -SV, aVIN = 0.1 VIN .
,,":,"r'O'.
>,
CPIN1 •PIN9 = 1OitF, f .. 120Hz
t
VIN < -1SV
Rsc
-7V~VIN~-1SV
Note 2. When external booster transistors are used, the minimum output- Note 4.
Input voltage differential is increased, in the worst case, byapproximately 1 volt.
Note 3. The output currents given, as well as the load regulation, can be
increased by the addition of external transistors. The improvement
factor will be roughly equal to the composite current gain of the
added transistors.
4-8
0.2
O.S
O.S
1.0
0.2
O.S
O.S
1.0
mVN
mVN
With zero output, the DC line regulation is determined from the
ripple rejection. Hence, with output voltages between 0 volts and
-5volts, a DC output variation, determined from the ripple rejection, must be added to find the worst-case line regulation.
SG104/SG204/SG304
ELECTRICAL SPECIFICATIONS (continued)
Parameter
SG104/204
SG304
Units
Min. Typ. Max. Min. Typ. Max.
1.8 2.0 2.2 1.8 2.0 2.2 VlKn
%
0.3 1.0
0.3 1.0
Test Conditions
Output Voltage Scale Factor
Temperature Stability
Output Noise Voltage
Standby Current Drain
Long Term Stability
RplN2 _PIN3 = 2.4k
Vo ::,;-1V
10Hz::'; f::,; 10KHz
Va::'; -5V, CpIN1-PIN9 = 0
CpIN1 • PIN9 = 1O~F
IL = 5mA, Va = 0
Vo= ·30V
Vo= ·40V
Vo ::,;·1V
0.007
15
1.7 2.5
3.6
0.1
0.007
15
1.7 2.5
3.6 5.0
5.0
1.0
0.1
1.0
%
~V
mA
mA
mA
%
APPLICATION CIRCUITS
--'--~---~--~r-- GND
Cl
4.7p.F
\---+--
VOUT :::::;
\---,-+--,--VOUT -
~
Rl
Rl
2.4K
2.4K
1~
V,N
12V
R3 0.2
---+------+-------'
GND~---'
FIGURE 1-BASIC NEGATIVE REGULATOR CIRCUIT
VIN;!!;-14V
FIGURE 1- HIGH CURRENT REGULATOR CIRCUIT
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
10·PIN TO·100 METAL CAN
T-PACKAGE
SG104T/883B
SG104T
SG204T
SG304T
Ambient
Temperature Range
·55°C to 125°C
·55°C to 125°C
·25°C to 85°C
O°C to 70·C
Connection Diagram
N.C.
ADJ.
GROUND
CD @)®
REFERENCE ®
® ~~*~~TED
REFERENCE ®
®
BOOSTER
SUPPLY
COMPENSATION @ ® ® CURRENT LIMIT
UNREGULATED
INPUT
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grave, CA 92641 • (714) 898·8121 • TWX: 910-596·1804. FAX: (714) 893-2570
4·9
•
4 -10
SGlOSISG20SISG30SISG30SA
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
POSITIVE VOLTAGE REGULATOR
DESCRIPTION
FEATURES
This circuit is a positive voltage regulator designed for both linear and switching
applications. Inherent component tracking of the monolithic integrated circuit
process provides a high degree of stability and accuracy in addition to fast
response to both line and load transients. With an input voltage rating of up to
SOY, this device will deliver load currents of 20mA (4SmA with 30SA). Adding
external transistors will increase the current capability to greater than 10amps
and further improve regulation.
• Output voltage adjustable from 4.SV to
40V
• Load regulation better than 0.01%/mA
• Line regulation better than 0.06%N
• Ripple rejection of 0.01%N
• 1.0% maximum temperature variation
HIGH RELIABILITY FEATURES - SG10S
• Available to MIL-STO-883B
• SG level "S" processing available
BLOCK DIAGRAM
UNREGULA TED
INPUT
BOOSTER
OUTPUT
CURRENT
LIMIT
REGULATED
OUTPUT
COMPENSA TION
SHUTDOWN
FEEDBACK
REFERENCE
BYPASS
GROUND
April 1990
4 -11
SG10SISG20SISG30SISG30SA
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage
SG10S ............................................................................ SOV
SG20S ............................................................................ SOV
SG30S .............................................. ;............................. 40V
SG30SA .......................................................................... SOV
Storage Temperature Range .........................•.. -6SoC to lS0°C
Lead Temperature (Soldering, 10 seconds) .................... 300°C
Note 1. Values beyond which damage may occur.
Input - Output Voltage Differential
SG10S .............................................................................. 30V
SG20S .............................................................•................ 30V
SG30S .............................................................................. 30V
SG30SA ....................................................................:....... 30V
Operating Junction Temperatures
Hermetic (T, J, F, V-Packages) .................................. lS0°C
Plastic (N-Packages) .................................................... lS0°C
THERMAL DERATING CURVES
~
i
~
is
~
~
I
I
175
175
AMBIENT TEMPERATURE - "C
CASE TEMPERATURE -
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
'C
MAXIMUM POWER DISSIPATION VB CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage
SG10S, SG20S, SG30SA ................................... 1OV to 48V
SG30S .............................................................. 1OV to 38V
Input - Output Voltage Differential
SG10S, SG20S, SG30S, SG30SA ....................... SV to 28V
Note 2: Range over which the device is functional.
Operating Ambient Temperature Range
SG10S .......................................................
-SSOCto12SoC
SG20S .............................................. ...........
-2SoC to 8SoC
SG30S, SG30SA ...... ........................................ O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1 05 with -55°C S; T. S; 125°C, SG205 with -25°C
S;T. S; 85°C, and SG305 with O°C S;T. S; 70°C. Temperature drift effects must be taken into account separately when the unit is operating under conditions
of high dissipation. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambienttemperature.)
Parameter
Input Voltage Range
Output Voltage Range
Input/Output Differential
Load Regulation (Note 4)
Une Regulation
Ripple Feed
Temperature Stability (Note 3)
Output Noise Voltage
Feedback Sense Voltage
Standby Current Drain
Load Current
Long Term Stability (Note 3)
SG105/205
Test Conditions
Il < 12mA, Rsc
VIN - VOUT s; 5V
VIN - VOUT > SV
= 100
CREF = 10~F, f = 120Hz
1.0Hz S; f S; 10KHz, CREF =0
Min. Typ. Max. Min.
8.S
SO 8.0
4.S
40 4.S
3.0
30 3.0
0.1
0.06
0.03
0.01
1.0
O.OOS
1.5S 1.7 1.8S 1.SS
2.0
0
0
0.1
1.0
Note 3. This test is guaranteed but not tested.
Note 4. Applies for constant junction temperature.
4 -12
SG305
Typ. Max.
40
30
30
0.1
0.06
0.03
0.01
1.0
O.OOS
1.7 1.85
2.0
0.1
1.0
SG305A
Units
Min. Typ. Max.
V
8.S
SO
V
4.S
40
V
3.0
30
%
0.2
0.06 %N
0.03 %N
%N
0.003
%
1.0
O.OOS
%
V
1.5S
1.8S
rnA
2.0
rnA
0
%
0.1 1.0
SGIOSISG20SISG30SISG30SA
CHARACTERISTIC CURVES (continued)
40
RsC""100
"
1"\ ....... ~
\
\ ............
'I
(5 -0.2
~
~
w
\
-0.4
TA=1251b\
~ -0.6
\
\
\
\
=>
is
-O.B
-0.1
o
10
E
'2
TA.. -55a:::
~
3.0
tJ
2.8
z
~
~
a
>--
\
"
4
40
5
6 7 B
FIGURE 1.
LOAD REGULATION
10 12
is
.....
15 20
Rsc=lon
:;E
S'
~
12
""" ~ ~ I--..r-
:>
>--
=>
"-
z
ia
'L=20mA
'L .. 1OmA
I"'--
2530
""IER
1.1
./
1.0
.t~....... "
0.9
0
25
50
75 100 125 150
1"+ EIJED
S'
E
25
50
75 100 125 150
I
I.
0
"'
~
-J125
TA=25OC
1
1\-_ .....
u"' ,
F
-40
V
VOUT"'10Y
--CL"'O
- - - - CL =lp.F
w
RSC=100
A\jN=5V11lour=19mA
~ +400
~
0
:>
>--
COAil
rf........
~
is
l~"· ~..
r
-400
0.8
20
10
AMBIENT TEMPERATURE-( "c)
FIGURE 4.
DROPOUT VOLTAGE
a
-75 -50 -25
FIGURE 3.
CURRENT LlMITNG
;~HJ
.....
........
AMBIENT TEMPERATURE-(Oc)
~
IL=TA
11
-75 -50 -25
10
o
40
RsC=151l""-
+40
~
~
- ----""",~"100
~=.::.
0;
1.2
VQU!..IOV
~
>--
......
FIGURE 2.
OPTIMUM DIVIDER RESISTOR VALUES
13
0
20
OUTPUT VOL TAGE-(V)
LOAD CURRENT-(mA)
J
i"
13
2.'
2.0
30
...... ......
~
2.6
2.2
20
30
i "- ....
r- r--
Rl=(l "K)VoUT
'I
"\
\
\
\
...........
:;-
Rl/~=2K
3.2
TA-25'c\
\
~
iO
3.4
~~
30
40
50
10
20
30
INPUT VOLTAGE-(V)
FIGURE 6.
TRANSIENT RESPONSE
FIGURES.
STANDBY CURRENT DRAIN
APPLICATION CIRCUITS
REGULATED
OUTPUT
REGULATED
OUTPUT
FERRITE
CORE
Rl
Rl
Cl
47pF
INPUT
+ C2
VOLTAGE
ADJUST
4.7~F
UNREGULATED
INPUT
-+--.......---'<:~
----,
R2
~CREF
GROUND
FIGURE 7 - REGULATOR CONNECTED FOR 2 AMP OUTPUT
GROUND
TO.l"F
I
FIGURE 8 • BASIC REGULATOR CIRCUIT
4-13
R2
•
SGIOS/SG20S/SG30S/SG30SA
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
Ambient
Temperature Range
8·PIN CERAMIC DIP
y. PACKAGE
SG105Y/BB3B
SG105Y
SG205Y
SG305Y
SG305AY
·55°e to 125°C
-55°C to 125°C
-25°C to B5°e
OOeto 70°C
ooe to 70°C
14·PIN CERAMIC DIP
J-PACKAGE
SG105J/BB3B
SG105J
SG205J
SG305J
SG305AJ
-55°C to 125°C
-55°C to 125°C
-25°C to B5°e
OOeto 70°C
OOeto 70°C
14-PIN PLASTIC DIP
N-PACKAGE
SG205N
SG305N
SG305AN
-25°C to B5°C
ooe to 70°C
OOeto 70°C
10·PIN CERAMIC
FLATPACK
F·PACKAGE
SG105F/BB3B
SG105F
-55°C to 125°C
-55°C to 125°C
8·PIN TO-99 METAL CAN
T-PACKAGE
SG105T/BB3B
SG105T
SG205T
SG305T
SG305AT
-55°C to 125°C
-55°C to 125°C
-25°C to B5°e
OOeto 70°C
OOeto 70°C
0
Connection Diagram
CURRENT LIMIT
BOOSTER OUTPUT
UNREGULATED OUTPUT
'
GND
N.C.
N.C.
BOOSTER OUTPUT
UNREGULATED INPUT
GND
N.C.
REFERENCE BYPASS
2
3
4
REGULATED OUTUT
COMPENSATION
FEEDBACK
REFERENCE BYPASS
7
6
5
[~P N.C.
[ 2
[ 3
[ 4
[ 5
[6
P N.C.
P CURRENT LIMIT
P REGULATED OUTPUT
P COMPENSATION
13
12
11
10
9p
N.C.
[~p FEEDBACK
2'
N.C.
BOOSTER OUTPUT
2
UNREGULATED OUTPUT =
3
GND=4
REFERENCE BYPASS =
5
10
f:=::J
N.C.
1=== CURRENT LIMIT
9
81===
7!==J
6
t::=
REG. OUTPUT
COMPENSATION
FEEDBACK
REGULATED
OUTPUT
CURRENT LIMIT
CD ® ® ~~.f~~TIONI
® FEEDBACK
®
UNREGULATED INPUT ® @) ® REFERENCE BYPASS
BOOSTER OUTPUT
GROUIND
& CASE
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898·8121. TWX: 910-596·1804. FAX: (714) 893-2570
4-14
SG109/SG309
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
5 -VOLT FIXED VOLTAGE REGULATORS
DESCRIPTION
FEATURES
The SG109/SG309 is a completely self-contained 5V regulator.
Designed to provide local regualtion at currents up to 1A for digital
logic cards, this device is available in the hermetic TO-3, TO-66, TO39 and hermetic and plastic TO-220.
•
•
•
•
•
•
A major feature of the SG109's design is its built-in protective
features which make it essentially blowout proof. These consist of
both current limiting to control the peak currents and thermal
shutdown to protect against excessive power dissipation. With the
only added component being a possible need for an input bypass
capacitor, this regulator becomes extremely easy to apply. Utilizing
an improved Bandgap reference design, problems have been
eliminated that are normally associated with the zener diode
references, such as drift in output voltage and large changes in the
line and load regulation.
Fully compatible with TTL and DTL
Output current in excess of 1A
Internal thermal overload protection
No additional external components
Bandgap reference voltage
Foldback current limiting
HIGH RELIABILITY FEATURES-SG109
•
•
•
•
Available to MIL-STD-883
MIL - M3851 0 110701 BXA - JAN109T
Radiation data available
SG level "S" processing available
•
SCHEMATIC
R'B
L - - _ _ > M - - -.....-Ql2
Your
Vos
April 1990
4 -15
SG1091SG309
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage ..............................•....................................... 35V
Power Dissipation .......................................... Internally Limited
Storage Temperature Range ............................. -65°C to 150°C
Operating Junction Temperature
Hermetic (K, R, T, G, IG-Packages) .................•.......... 150°C
Lead Temperature (Soldering, 10 Seconds) ................ 300°C
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL DERATING CURVES
'.O....--,.---,---r--,---r--"T"---'
~
~
~
~
~
ill
ill
c 2.0[--1-----;
"
i
20
i
'0
°OL-~-~-~-~-~~-~
0
17'
17'
0
AMBIENT TEMPERATURE - "c
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage Range .............................................. 7.0V to 25V
Operating Junction Temperature Range
SGl 09 ............................................................ -55°C to 150°C
SG309 ..............................................•............... O°C to 125°C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SGI 09 with -55·C ~ T. ~ IS0·C, SG309 with O·C
~T. ~ 125°C, and for V,N = 10V, lOUT = SOOmA (K, R, G, and IG -Power Packages-) and lOUT = 1OOmA (T-package). Low duty cycle pulse testing techniques
are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Output Voltage
Line Regulation
Load Regulation
Total Output Voltage Tolerance
Quiescent Current
Quiescent Cur.rent Change
Output Noise Voltage
Long Term Stability
Ripple Rejection
Test Conditions
TA = 25°C
VIN = 7.1V to 25V, TA = 25°C
TA = 25°C
Power Pkgs: lOUT = 5mA to 1.5A
T-package: lOUT =5mA to 500mA
VIN= 7.4V to 25V
Power Pkgs: lOUT '7 5mA to 1.0A,
P s20W
T-package: IOUT=5mA to 200mA, P s20W
VIN = 7.4V to 25V
With Line: VIN = 7.4V to 25V
With Load: Power Pkgs: lOUT = 5mA to 1.0A
T"package: lOUT =SmA to 200mA
f = 10Hz to 100KHz, TA = 25°C
TA = 25°C
SG109
SG309
Min. Typ. Max. Min. Typ. Max.
4.7 5.05 5.3
4.8 5.05 5.2
4.0
50
4.0
50
4.6
4.6
4-16
V
mV
15
15
100
50
15
15
100
50
mV
mV
5.0
5.0
5.4
5.4
10
0.5
0.8
0.8
4.75 5.00 5.25
4175 5.00 5.25
10
0.5
0.8
0.8
40
20
50
V
V
rnA
rnA
mA
rnA
Il V
mV
dB
40
10
50
Units
SG1091SG309
APPLICATION CIRCUITS
INPUT - - - - . - - ' j
f"--.-- OUTPUT
f"----.-- OUTPUT
R1
3000
1%
INPUT - - - - . - - ' j
'----~
* REQUIRED
*.
IF REGULATOR IS AN APPRECIABLE
DISTANCE FROM POWER SUPPLY FILTER
ALTHOUGH NO OUTPUT CAPACITOR IS NEEDED
FOR STABILITY IT DOES IMPROVE TRANSIENT
RESPONSE.
FIGURE 2 - ADJUSTABLE OUTPUT REGULATOR
FIGURE 1 - FIXED 5V REGULATOR
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
3-TERMINAL TO-3
METAL CAN
K-PACKAGE
Part No.
SG109KJ883B
SG109K
SG309K
(See Notes Below)
Ambient
Temperature Range
II
Connection Diagram
-55°C to 125°C
-55°C to 125°C
to 70°C
v'~
ooe
~.'"'""
VOUT
3-TERMINAL TO-66
METAL CAN
R-PACKAGE
SG109R!883B
SG109R
SG309R
-55°C to 125°C
-55°C to 125°C
to 70°C
v"
ooe
CD
0
0
2
CASE IS GROUND
v""
3-PIN HERMETIC TO-257
G-PACKAGE (Non-Isolated)
SG109G!883B
SG109G
-55°C to 125°C
-55°C to 125°C
3-PIN HERMETIC TO-257
IG-PACKAGE (Isolated)
SG1091G/883B
SG1091G
-55°C to 125°C
-55°C to 125°C
3-PIN TO-39 METAL CAN
T-PACKAGE
SG109T/883B
SG109T
SG309T
-55°C to 125°C
-55°C to 125°C
to 70°C
TAB
IS
GROUND 1
0
ooe
1
:
I
'.cQ
v""
Note 1_ Contact factory for JAN and DESC product availability_
2_ All parts are viewed from the top_
Silicon General •
~RoUND
v"
® ®
GROUND
3_ Product is also available in leadless chip carrier (LCC) and hermetic flat pack (F)_
Contact factory for price and availability_
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 .1WX: 910-596-1804. FAX: (714) 893-2570
4-17
4 -18
SGl17AISG217AISG317A
SGl171SG2171SG317
SILICON
GENERAL
1.5 AMP THREE TERMINAL
ADJUSTABLE VOLTAGE REGULATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SGl17A Series are 3-terminal positive adjustable voltage
regulators which offer improved performance over the original 117
design. A major feature of the SGl17A is reference voltage
tolerance guaranteed within ± 1%, allowing an overall power supply
tolerance to be better than 3% using inexpensive 1% resistors. Line
and load regulation performance has been improved as well.
Additionally, the SGl17A reference voltage is guaranteed not to
exceed 2% when operating over the full load, line and power
dissipation conditions. The SG1.17A adjustable regulators offer an
improved solution for all positive voltage regulator requirements with
load currents up to 1.5A.
• 1% output voltage tolerance
• 0.01%N line regulation
• 0.3% load regulation
• Min. 1.5A output current
• Available in hermetic TO·220
HIGH RELIABILITY FEATURES·SG117A1SG117
•
•
•
•
Available to MIL·5TD·883 and DE5C 5MD
MIL·M38510/11704BVA· JAN117K
MIL·M3851 0111704BXA • JAN117T
5G level "5" processing available
II
SCHEMATIC DIAGRAM
022'J/--r-W---i:!i:
""""--1--+-002.
D~D
~
HI
DI
6.JV
P
'--!--+-+--iI---I--!--t:§02.
X7--K-
}-' METAL TRII,I
XlI-''~.
--r DIFFERENCES OCCUR BETWEEN
Q26,R28.R;,S
April 1990
4 ·19
~e,7Il"K.
O.154(tr
SGl17AISGl17 SERIES
ABSOLUTE MAXIMUM RATINGS (Note 1)
,
,(
Power Dissipation ........................................... Internally Limited
Input to Output Voltage Differential ..........•.. ,.................... 40V
Storage Temperature Range ............................. -6S·C to 1S0·C
Note 1. Exceeding these ratings could cause damage to the device.
Operating Junction Temperature
Hermetic (K. R. T. F. L. G. IG-Packages) ...................,.1S0·C
Lead Temperature (Soldering. 10 Seconds) ................ 300·C
THERMAL DERATING CURVES
5,• .---r-----,---r---,---,--..,..----,
~
~
~
I
~
3,.
~
~
~
~
~
i:i
is 2.0
a
i
I
20
25
50
75
'00
'25
150
'75
AMBIENT TO.4PERATURE - 'C
CASE TEMPERATURE - 'C
MAXIMUM POWER OISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2 & 3)
Input Voltage Range ..............................
(Vour + 3.SV) to 37V
Operating Junction Temperature Range
SG117A1SG117 ......................................... -SS·C to 1S0·C
SG217A1SG217 ......................................... -2S·C to 1S0·C
SG317A1SG317 .......................................... .. O·Cto 12S·C
Note 2. Range over which the device is functional.
Note 3. These ratings are applicable for junction temperatures of less than IS0·C.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified. these specifications apply over full operating ambient temperatures for SG117AlSG 117 with -SS'C ~ T. ~ 12S'C. SG217AI
SG 317A1SG317withO'C~TA~12S'C. V"-Vo,,,=S.OV. and for loorr=SOOmA (K. R. Gand IG). and loorr= 100mA(T.
F and L packages). Although power dissipation is intemally limited. these specifications are applicable for power dissipations of 2W for the T. F. and
L packages. and 20W for the K. R. G. and IG packages. 1MAl( is I.SA for the K. R. G. and IG packages and SOOmA forthe T. F. and L packages. Low
duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
SG217with-2S'C~TA~ IS0'C.
Parameter
Test Conditions
Reference Voltage
Line Regulation (Note 4)
'"
.. ,
'Load Regulation (Note 4)
Thermal Regulaiion (Note S)
. Ripple Rejection
Adjust Pin Current
Adjust Pin Current Change'
lour =10mA TA =25·C
3V S (V'N - Vour) s 40V. P s' PMAX'
~ 10mA ~ lour ~,IUAX ,
, '
3V S (V,N - Vour)S 40V. IL = 10mA
'TA ;'25"C .
' "
TA=TMlNtoTw,x
1OmA ~ lour ~ 1MAl(
Vour.S; SV. TA.=: 2S·C
Vour?! 5V. TA ':' 25·C
VQUTSSV
,
Vwr?! 5V ...
TA = 2S·C. 20ms pulse
Vour ="10V. f :='120Hi
CADJ := 1J.1.F. TA = 2S·C
CADJ =JOJ1F
SG117A1SG217A
SG117/SG217
Min. Typ. Max. Min. Typ. Max.
1.238 1.250 1.262
1.225 1.250 1.270 1.20 1.25 1.30
0.005 Q.Of
0.01 0.02
4-20
0.01' '0.02
0.02 O.OS
1S
S
0:1
0.3
20
SO
0.3
1
.- 0.002 0.02
S
0.1
20
o:a
0.03
65
66
,8'0
SO
,10mA ~ lour ~ fMAl(' 2.5V ~ (Y,N - Vourf~ 40V
I,
66
100
1.1.2' . 5
65
80
SO
1S
Units
V
V
%IV
%IV
mV
0'.3
-%
SO
1
0.07
mV
%
%/W
100
',0.2" ',5
dB
dB
Il A
IJA
~
SG117AISG117 SERIES
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Minimum Load Current
Current Limit
Temperature Stability (Note 5)
Long Term Stability (Note 5)
RMS Output Noise (% of VOUT)
Parameter
Reference Voltage
Line Regulation (Note 4)
Load Regulation (Note 4)
Thermal Regulation (Note 5)
Ripple Rejection
Adjust Pin Current
Adjust Pin Current Change
Minimum Load Current
Current Limit
Temperature Stability (Note 5)
Long Term Stability (Note 5)
RMS Output Noise (% of Vour)
Test Conditions
(V'N - VOtlT) = 40V
(V'N - VOUT) ~ 15V
K, P, R, G, IG Packages
T, L, F Package
(V'N - VOtlT) = 40V, TJ = 25°C
K, P, R, G, IG Packages
T, L, F Packages
SG117AlSG217A
SG117/SG217
Min. Typ. Max. Min. Typ. Max.
5
3.5
5
3.5
10tlT = 10mA TA = 25°C
3V ~ (V'N - Vour) ~ 40V, P ~ PMAX '
10mA ~ lour ~ IMAX
3V ~ (V'N - Vour) ~ 40V, IL = 10mA
TA = 25°C
TA = TM'N to TMAX
1OmA ~ lOUT ~ 1MAl(
VOUT~ 5V, TA = 25°C
VOUT "= 5V, TA = 25°C
VOUT~ 5V
VOUT "= 5V
TA= 25°C, 20ms pulse
Vour = 10V, f =120Hz
CADJ = 1flF, TA = 25°C
CADJ = 10flF
TA = 25°C
1OmA ~ lOUT ~ IMAX , 2.5V ~ (V'N - V0tlT) ~ 40V
(V'N - VOUT) = 40V
(V'N - VOtlT) ~ 15V
K, P, R, G, IG Packages
T, L, F Packages
(V'N - Vour) = 40V, TJ = 25°C
K, P, R, G, IG Packages
T, L, F Packages
TA = 125°C
TA= 25°C, 1OHz ~ f ~ 10KHz (Note 5)
mA
1.5
0.5
2.2
0.8
1.5
0.5
2.2
0.8
A
A
0.3
0.15
0.4
0.2
1
0.3
0.001
0.3
0.15
0.4
0.2
1
0.3
0.001
A
A
%
%
%
TA = 125°C, 1000 Hours
TA = 25°C, 10Hz ~f ~ 10 KHz (Note 5)
Test Conditions
Units
2
1
1
SG317A
SG317
Min. Typ. Max. Min. Typ. Max.
1.238 1.250 1.262
1.225 1.250 1.270 1.20 1.25
66
Units
V
1.30
V
0.005 0.01
0.01 0.02
0.01
0.02
0.04
0.07
%N
%N
5
25
0.1
0.5
20
50
0.3
1
0.002 0.02
5
0.1
20
0.3
0.03
25
0.5
70
1.5
0.07
mV
%
mV
%
%/w
100
5
10
dB
dB
IJA
IJA
mA
65
80
50
0.2
3.5
66
100
5
10
65
80
50
0.2
3.5
1.5
0.5
2.2
0.8
1.5
0.5
2.2
0.8
A
A
0.15
.075
0.4
0.2
1
0.3
0.001
0.15
.075
0.4
0.2
1
0.3
0.001
A
A
%
%
%
2
1 ..
1
Note 4. Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to heating
effects are covered under the specification for thermal regulation.
Note 5. These parameters, although guaranteed, are not tested in production.
4-21
SGl17AISGl17 SERIES
CHARACTERISTIC CURVES
0.2
60
...
"
'(
...... ...... ......
~
tJ
r= =\-2
l .. a.SA
z
a
F
-< -0.2
"\~
IL.. ,SA
-0.4
;!:
g -0.6
i~
--
",....;;
"1N"'15V
VOUT""10r
o
-1.0
-75-50-250
25
~
o
75100125150
TEMPERATURE-("c)
40
20
45
~-<
40
~
'~ ~
-O.B
i:'i
FIGURE 2.
OUTPUT CURRENT VS. INPUT/OUTPUT
DIFFERENTIAL
3.0
F
I
1.250
tJ
"'"
;!:
5
> 1.240
2.0
w
u
0-
=>
r--..
~
~~
~
~
3.0
i:'i
~
1\
1.230
0Z
w
u
~
5
'--'--'-_'--'---'---'_.1--'-''''''
a
25
50
1.220
2.5
2.0
...... ,....
r-=
~
1.5
1.0
~
r
~
~.
I'rJ=150'\:
TJ=j''\:
100
-
CADJJo¢="
....
80
.........
60
40
./
ID
I'--
50
~
I
Cp.oJ"o
15F
~
~~568~r5V
~
60
25
OUTPUT VOLTAGE-(V)
FIGURE 7.
RIPPLE REJECTION VS. OUTPUT VOLTAGE
30
35
100
~
"
~
1
10
~
\
:\ I~
r""OV
o
20
15F
I~
TJ=2sDc
15
'(
~_15V
20
10
80
ill
\
IL SOOmA
lK
10K
FREQUENCY-(Hz)
FIGURES.
RIPPLE REJECTION VS. FREQUENCY
4-22
20
30
40
100
~J""~
40
10
FIGURE 6.
QUISCENT CURRENT VS. INPUTIOUTPUT
DIFFERENTIAL
1
-.....
0:
20
o
o
INPUT/OUTPUT DIFFERENTIAL-(V)
1/.......- ~CADJ"O I'\.
Ii:
~;2~~
o
o
75 100 125 150
FIGURES.
REFERENCE VOLTAGE VS. TEMPERATURE
100
80
25
TEMPERA TURE-("c)
FIGURE 4.
INPUTIOUTPUT DIFFERENTIAL VS. TEMPERATURE
ill
a
'-75 -50 -25
75 100 125 150
TEMPERATURE-("c)
~0:
,,;
., ~
TJ=-55~
0.5
-75 -50 -25
~
'"
;r
0
1.0
F
3.5
u
i:'i
1.5
-<
E
~
;;
'(
z
a
75 100 125 150
4.0
~
2.5
:;
~.
50
4.5
1.260
i:'i
ffi
It·
is
25
FIGURE 3.
ADJUSTMENT CURRENT VS. TEMPERATURE
$"
J
a
TEMPERATURE-("c)
INPUT/OUTPUT DIFFERENTIAL-(V)
FIGURE 1.
OUTPUT VOLTAGE DEVIATION VS. TEMPERATURE
...-I- ~
V
35
-75 -50 -25
60
V-
I"
V
0-
TJ .. -55~
=>
./
50
u
\ ~ro,j,,..,J_-'-I'' '_+--1
~ ~ a t-""",I\>jo..:q,..-O,.'' ;C;;;'';:.J-_O+-I\'-;:,'-Jo-+--I
/
100
I
ij
:[
~:;;
>-
:0
i!o
:0
0
CAOJaO/
10- 1
1O-~
-
1.0
w
/
i!oo=>
~O.5 I--l--i--t--+-t-....
VH-+--l
vOUT""ov
-1.0
../
~_-1.5
/CADJ"'O,w
~G
5 ~ 1.0
>"
~~
;;; u
0.5
'L-SOmA t-+-I-+--lf-i-i-l---l
TJ .. 25't
1--t--I-+-+-j--I-4-1---l
I-+-+-+-+-I-+--+-I--j
I-+--+-+-+-i-+-+-I--j
a 1...L...l_L...l.......JL............._ _ooI
10
10
J
r-,---,---,--.,--r---,--.,--r---r
2
I--I--I--I--I---I---""'"..-+-I--i
~~ 11-+--+-+q,::-:.J-."'c,-I,IJ_"'o-tf-\t-+--I
g is a t-.,......;r-+-+_I_I-F..
""t-+--i
~~
-1
15"
-2
1--I~+-.-.,f--.pq,""""'P-,C::;'r'Jc-'lOt"''''-+_+--I
1--11+
'Il--+-I-+--t--;:b..t-l
\J
\1N'"'sv
-Jt-+~-I-t-+-il--r-~~~~X-
'< 1.5 F-+,-r+_+-+____+-T:.;.J.-=2::,5'ct---f
~ ~ 1.0 t-+lH-t-+-iI--t\-t-t--l
g
'-t--+--I
a~ 0.5a 1-..,1I1-:--I--+-t-+--f+
_ ....- ' _.........J...---JL-..J...\.
_ _ _ __
10
40
20
JO
40
TIME-(p.,)
FREOUENCY-(Hz)
FIGURE 10.
OUTPUT IMPEDANCE VS. FEaUENCY
JO
20
w
FIGURE 11.
LINE TRANSIENT RESPONSE
r---'---~----r---'----'
1.5
FIGURE 12.
LOAD TRANSIENT RESPONSE
r--r---,---,--.,--r---r--r-"'T'"-'
1.5
r-,-.....,..--,-,.,--r---r--,.--r--,
1 r--1--+--1r-+--r--1,"'~--r-~
~ ~ 0.5 r-+-I-+:-q,,,,,_,T-.-=c,.-I,f-J_",,~I"'~-."""'-+--I
ga 01-~--lr-+-+-":1-...p:~L...+--I
g
~
r!i
~- r:- q,-,!r, C;'J-'''''
~ ~O.5 t--H,-f,,-p-:.q::.'-'ir-T'-I-t--l
:[
8
go
"-
:;;
f-
~
15
0.01
w
<>-
~-1
ow
0.001
0.5
I-+-I-t-+-i-i+-+-t--l
~U
0
1...L...l_L...l..L.....L............._ _ooI
:0",
,.
' I-+-+-+-+_I_I+--+-I--j
>"~
I-
0.0001 ' - _ - ' -_ _L-_-'-_---JL-_-'
10
100
10K
100K
1M
-1 I--t--+--j---t-+~~t-+-I
10
FREOUENCY-(HZ)
FIGURE 13.
OUTPUT IMPEDANCE VS. FREaUENCV
20
30
40
TIME-(p.,)
, ,
, ,
, ,
11
~
8
tJ
9
~>
>-
4
S
J
:0
0
2XRESISlTORS
7
6
5
2
1
'XRESISITOR:f
2" RESISITORSI
--r l
P
".
,,,
I'iY
3
II
JcJ,U~
RE:SISITO~S
, J,
, ,
P
a
4
6
I
a
a ___- ' _.........J..._L-..J...\.
...._ _...
10
20
FIGURE 15.
LOAD TRANSIENT RESPONSE
12
10
I--HU~--+-+--I--~~~~15~V-+--I
TIME-v,.,)
FIGURE 14.
LINE TRANSIENT RESPONSE
g
-1
-1.5 1-+-I-+-+-,I--I~~ro~g~IOOmA
TJ=25"C
<: 1.5 1-+-r+-+-+-_I+---t-r--1
~ 1.0 1-+l'H-+-+-,I--t\-I-+--l
g ~ 0.5 I---ff'-I-+-+-il--I:+
'-1-4--1
10
20
OUTPUT VOLTAGE
FIGURE 16.
OUTPUT VOLTAGE ERROR
4-23
40
100
JO
40
a
SGl17AISGl17 SERIES
APPLICATION INFORMATION
GENERAL
The SG117A develops a 1.25V reference voltage between the
output and ,ihe adjustable terminal (see Figure 1). By placing a
resistor, R, between these two terminals, a constant current is
caused to flow through R, and down through R2 to set the overall
output voltage, Normally this current is the specified minimum
load current of 5mA or 10mA.
VIN
--.--1
For convenience, a table of standard 1% resistor values is shown
below.
1----,,--...-- V au T
I
FIGURE 17· BASIC REGULATOR CIRCUIT
Because IADJ is very small and constant when compared with the
current through R" it represents a small error and can usually be
ignored.
Table of Y2% and 1% Standard Resistance Values
1.00
1.02
1.05
1.07
1.10
1.13
1.15
1.18
1.21
1.24
1.27
1.30
1.33
1.37
1.40
1.43
1.47
1.50
1.54
1.58
1.62
1.65
1.69
J.74
1.78
1.82
1.87
1.91
1.96
2.00
2.05
2.10
2.15
2.21
2.2!)
2.32
2.37
2.43
2.49
2.55
2.61
2.67
2.74
2.80
2.87
2.94
.3.01
3.09
3.16
3.24
3.32
3.40
3.48
3.57.
3.65
3.74
3.83
3.92
4.02
4.12
4.22
4.32
4.42
4.53
4.64
4.75
4.87
4.99
5.11
5.23
5.36
5.49
5.62
5.76
5.90
6.04
6.19
6.34
6.49
6.65
6.81
6.98
7.15
7.32
7.50
7.68
7.87
8.06
8.25
8.45
8.66
8.87
9.09
9.31
9.53
9.76
. Standard Resistance Values are obtained from the Decade
Table by multiplying by multiples of 1O. As an example:1.21 can
represent 1.210, 12.10, 121(1, 1.21Knetc.
Rp
It is easily seen from thE! above equation, that even if the resistors
were of exact value, the accuracy of the output is limited by the
accuracy of VREF' Earlier adjustable regulators had a reference
tolerance of ±4%. This tolerance is dangerously close to the ±5%
supply tolerance required in many logic and analog systems.
Further, many 1% resistors can drift 0.01 %°C adding another 1%
to the output voltage tolerance.
PARASITlC
LINE RESISTANCE
CONNECT
R, TO CASE
R,
R2
For example, using 2% resistors and ±4% tolerance for VREF,
calculations will show that the expected range of a 5V regulator
design would be 4.66V S VOUT S 5.36V or approximately ±7%. If
the same example were used for a 15V regulator, the expected
tolerance would be ±8%. With these results most applications
require some method of trimming, usually a trim pot. This solution
is expensive and not conducive to volume production.
L
TO LOAD
FIGURE '8 - CONNECTIONS FOR BEST LOAD REGULATION
f--.--~- VOUT
One of the enhancements of Silicon General's adjustable regulators over existing devices is tightened initial tolerance. This allows
relatively inexpensive 1%or 2% film resistors to be used for R, and
R2 while setting output voltage within an acceptable tolerance
range.
With aguaranteed 1% reference, a5V power supply deSign, using
±2% resistors, would have a worse case manufacturing tolerance
of ±4%. If 1% resistors were used, the tolerance would drop to
±2.5%. A plot of the worst case output voltage tolerance as a
function of resistor tolerance is shown on the front page.
CONNECT R2
t
Optional-improves transient
response
*
Needed if device is for from
#
Needed if load current is
mechanically switched
VOUT =1.25V
filter capacitors
FIGURE '9 ·'.2V-25V ADJUSTABLE REGULATOR
4-24
(1+~)
SGl17AISGl17 SERIES
APPLICATION INFORMATION (continued)
BYPASS CAPACITORS
Input bypassing using a 11lF tantalum or 251lF electrolytic is
recommended when the input filter capacitors are more than 5
inches from the device. A 0.11lF bypass capacitor on the ADJUST
pin is required if the load current varies by more than 1Alllsec.
Improved ripple rejection (BOd B) can be accomplished by adding
a 1OIlF capacitor from the adjust pin to ground. For improved AC
transient response and to prevent the possibility of oscillation due
to unknown reactive load, a 11lF capacitor is also recommended
althe output. Because oftheir low impedance at high frequencies,
the best type of capacitor to use is solid tantalum.
5V
VOUT
12111
38311
FIGURE 22 - 5V REGULATOR WITH SHUT DOWN
+24V
7.:;4<)0_6________t -__"'SE=,L.ECT C FOR DESIRED RISE TIME
RETURN
_ ______________-=====::~~::======7_RET
3K
2%
FIGURE 20 - REMOTE SENSING
FIGURE 23 - 21V PROGRAMMING SUPPLY FOR UV PROM/EEPROM
f-~-----5V
R,
TO Vpp
1210
READ
WRITE
R2
3830
BYTE
t~:I's
*Cl Improves Ripple Rejection.
Xc
should be small compared to R2'
Vpp
DE
OV
5V
2490
1%
5V
12V
21V
21V
7500
1%
READ
39K
~
FIGURE 2' - IMPROVING RIPPLE REJECTION
3.24K
1%
TO DE
BYTE ERASE
LOAD REGULATION
Because the SG117A is a three-terminal device, it is not possible
to provide true remote load sensing. Load regulation will be
limited by the resistance of the wire connecting the regulatorto the
load. For the data sheet specification, regulation is measured at
the bottom of the package. Negative side sensing is a true Kelvin
connection, with the bottom of the output divider returned to the
negative side of the load. Although it may not be immediately
obvious, best load regulation is obtained when the top of the
divider is connected directly to the case, not to the load. This is
illustrated in Figure 1B. If R, were connected to the load, the
effective resistance between the regulator and the load would be
RpX (
R2~.R,
) ,Rp = Parasitic Line Resistance.
I
Connected as shown, Rp is not multiplied by the divider ratio. Rp
is about 0.0040 per foot using 16 gauge wire. This translates to
4mV/ft. at 1A load current, so it is important to keep the positive
lead between regulator and load as short as possible.
18K
----.I
ALL GATES 7407
CHIP ERASE
lOOK
FIGURE 24 - 2816 EEPROM SUPPLY PROGRAMMER FOR READIWRITE CONTROL
10K
THERMALLY
COUPLED
5011
+
LOAD ON BATTERY
":200!'A WHEN NOT
CHARGING
-"--12V
SOK
FIGURE 25 - TEMPERATURE COMPENSATED LEAD ACID BATTERY CHARGER
4-25
•
SGl17AISGl17 SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
3-TERMINAL TO-3
METAL CAN
K-PACKAGE
Part No.
Ambient
Temperature Range
Connection Diagram
SG117AKl883B
SG117AK
SG217AK
SG317AK
SG117K1883B
SG117K
SG217K
SG317K
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
QOC to 7QoC
-55°C to 125°C .
-55°C to 125°C
-25°C to 85°C
QOC to 70°C
SG117AR/883B
SG117AR
SG217AR
SG317AR
SG117R/883B
SG117R
SG217R
SG317R
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
QOC to 70°C
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
O°Cto 7QoC
SG117AT/883B
SG117AT
SG217AT
SG317AT
SG117T/883B
SG117T
SG217T
SG317T
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
QOCto 7QoC
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
O°Cto 7QoC
3-PIN HERMETIC TO-257
G-PACKAGE (Non-Isolated)
SG117AGl883B
SG117AG
SG117G/883B
SG117G
-55°C to
-55°C to
-55°C to
-55°C to
3-PIN HERMETIC TO-257
IG-PACKAGE (Isolated)
SG117AIG/883B
SG117AIG
SG117IG/883B
SG1171G
-55°C to 125°C
-55°C to 125°C
-55°C to 125°C
-55°C to 125°C
10-PIN CERAMIC
FLAT PACK
F-PACKAGE
SG117AF/883B
SG117AF
SG117F/883B
SG117F
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
(NOle3)
SG117AU883B
SG117AL
SG117U883B
SG117L
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
(Note 4)
3-TERMINAL TO-66
METAL CAN
R-PACKAGE
3-PIN TO-39 METAL CAN
T-PACKAGE
20-PIN CERAMIC (LCC)
LEADLESS CHIP CARRIER
L-PACKAGE
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
Silicon General •
ADJUSTMENT
~'"'v.
ADJUSTMENT
~
'.(Q
CASE IS v"'"
2
v"
® ®
ADJUST
v"'"
125°C
125°C
125°C
125°C
0
1
N.C.
N.C.
N.C.
VOIJT
I
1
:
2'
==
r==
10
9
2
F=
ADJUST
I==v.
•I===:J
~N.c
•i::=
3
V•
. 7
4
v"",=.
1. SENSE
2.·N.C.
3. N.C.
4. N.C.
•
5. VIM
6
6: N.C.
7
7. N.C.
•
8. N.C.
9. N.C.
10. ADJUST
~~UST
.
N.C.
3212019
'0"
n
.
16
,.
1.
9 10 11 1213
11.
12.
13.
14.
15.
16.
17.
18.
19.
N.C.·
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C:
N.C.
20. VOUT
3. Both inputs and outputs must be externally connected together at the device
terminals.
.
4. For normal operation the SENSE pin must be externally connected to the load.
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4-26
SGl17AHVISG217AHVISG317AHV
SGl17HVISG217HVISG317HV
SILICON
GENERAL
1.5 AMP THREE TERMINAL
ADJUSTABLE VOLTAGE REGULATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG117AHV Series are 3-terminal positive adjustable voltage regulators
which offer improved performance over earlier devices. A major feature of the
SG117AHV is the output voltage tolerance is guaranteed at a maximum of ± 1%,
allowing an overall power supply tolerance to be better than 3 % using inexpensive 1 % resistors. Line and load regulation performance has been improved as
well. Additionally, the SG117AHV reference voltage is guaranteed not to exceed
2% when operating over the full load, line and power dissipation conditions. The
SG117AHV adjustable regulators offer an improved solution for all positive voltage
regulator requirements with load currents up to 1.5 amps.
•
•
•
•
•
For application information and characteristic curves see SG117A/117 data sheet.
1 % output voltage tolerance
0.01%IV line regulation
0.3% load regulation
Min. 1.5A output current
Available In hermetic TO·220
HIGH RELIABILITY FEATURES
·SG117AHV/SG117HV
• Available to MIL-STD·883
• SG level "S" processing available
SCHEMATIC DIAGRAM
r---~--~------~---r----~--~--------------~-----r--~---r---r-'--4-~+~N
Q'*""-+-+!!.!"lI"P'----+
<:SA
D'
6.JV
X7-"K"
}-- METAL TRlY
X8-"l"
"K" _.,. DlFTERENCES OCOJR BETWEEN
Q26,R26.RJa
April 1990
4-27
a
SGl17AHV/SGl17HV SERIES
ABSOLUTE MAXIMUM RATINGS (Notel)
Power Dissipation ........................................... Internally Limited
Input to Output Voltage Differential.......................... ......... 60V
Storage Temperature Range ............................ -65°C to 150°C
Note 1. Exceeding these ratings could cause damage to the device.
Operating Junction Temperature
Hermetic (K, R, T, F, L, G, IG-Packages) ..................... 150°C
Lead Temperature (Soldering, 10 Seconds) ................ 300°C
THERMAL DERATING CURVES
5.0.---r---r---r--r---,---r---.
I"
i
~
;"
l\
.~
~
2.0
"
i
20
i
25
S 60V
IJA
4-28
SGl17AHV/SG117HV SERIES
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Minimum Load Current
Current Limit
Temperature Stability (Note 5)
Long Term Stability (Note 5)
RMS Output Noise (% of VOUT)
Test Conditions
(VIN - VOUT) = 60V
(VIN - VOUT) s 15V
K, P, R, G, IG Packages
T, L, F Package
(VIN - VOUT) = 60V, TJ = 25°C
K, P, R, G, IG Packages
T, L, F Packages
Line Regulation ( Note 4)
Load Regulation ( Note 4)
1.5
0.5
Test Conditions
lOUT = lOrnA TA - 25°C
3V S (V IN - VOUT) s 60V, P S PMAX '
lOrnA S lOUT ~ IMAX
3V ~ (VIN - VOUT) ~ 60V, IL = 10mA
TA = 25°C
TA = TMIN to TMAX
1OmA ~ lOUT ~ IMAX
VOUT~ 5V, TA = 25°C
Vour?:. 5V, TA = 25°C
Adjust Pin Current
Adjust Pin Current Change
Minimum Load Current
Current Limit
Temperature Stability (Note 5)
Long Term Stability (Note 5)
RMS Output Noise (% of VOUT)
Vour?:. 5V
TA = 25°C, 20ms pulse
Vour= 10V,f=120Hz
CADJ = l11F, TA = 25°C
CAOJ = 10l1F
TA = 25°C
1OmA ~ lOUT ~ IMAX , 2.5V ~ (V IN - VOUT) ~ 60V
(VIN - VOUT) = 60V
(VIN - VOUT) ~ 15V
K, P, R. G. IG Packages
T, L, F Packages
(VIN - VOUT) = 60V, TJ = 25°C
K, P, R, G, IG Packages
T, L, F Packages
TA = 125°C
TA = 25°C, 1OHz ~ f ~ 10KHz (Note 5)
1.5
0.5
2
1
Units
rnA
2.2
0.8
A
A
0.1
0.03
1
0.3
0.001
A
A
%
%
%
1
SG317AHV
SG317HV
Min. Typ.· Max. Min. Typ. Max.
1.238 1.250 1.262
Units
V
1.225 1.250 1.270 1.20
1.25
1.30
V
0.005 0.Q1
0.Q1 0.02
0.01
0.02
0.04
0.07
%N
%N
5
25
0.1
0.5
20
50
0.3
1
0.002 0.02
5
0.1
20
0.3
0.04
25
0.5
70
1.5
0.07
mV
%
mV
%
%/W
100
5
12
dB
dB
jJA
jJA
rnA
VOUT~5V
Thermal Regulation (Note 5)
Ripple Rejection
2.2
0.8
0.1
0.03
1
0.3
0.001
TA = 125°C, 1000 Hours
TA = 25°C, 10Hz sf s 10 KHz (Note 5)
Parameter
Reference Voltage
SG117AHVI
SG117HVI
SG217HV
SG217AHV
Min. Typ. Max. Min. Typ. Max.
7
3.5
7
3.5
66
1.5
0.5
65
80
50
0.2
3.5
65
66
100
5
12
2.2
0.8
0.1
0.03
1
0.3
0.001
50
0.2
3.5
1.5
0.5
2
1
80
2.2
0.8
A
A
0.4
0.03
1
0.3
0.001
A
A
%
%
%
1
Note 4. Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to heating
effects are covered under the specification for thermal regulation.
Note 5. These parameters, although guaranteed. are not tested in production.
4-29
•
SGl17AHVISGl17HV SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
3·TERMINAL TO·3
METAL CAN
K·PACKAGE
3·TERMINAL TO-66
METAL CAN
R-PACKAGE
3-PIN TO-39 METAL CAN
T-PACKAGE
Part No.
Ambient
Temperature Range
SG117AHVKl883B
SG117AHVK
SG217AHVK
SG317AHVK
SG117HVKl883B
SG117HVK
SG217HVK
SG317HVK
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
O°Cto 70°C
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
O°C to 70°C
SG117AHVRl883B
SG117AHVR
SG21'7AHVR
SG317AHVR
SG117HVRl883B
SG117HVR
SG217HVR
SG317HVR
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
O°Cto 70°C
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
O°C to 70°C
SG117AHVT/883B
SG117AHVT
SG217AHVT
SG317AHVT
SG117HVT/883B
SG117HVT
SG217HVT
SG317HVT
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
O°Cto 70°C
-55°C to 125C
-55°C to 125°C
-25°C to 85C
O°C to 70°C
Connection Diagram
ADJUSTMENT
~"'~
v.
ADJUSTMENT
CASE IS v""
'.cQ
ADJUST
SG117AHVGl883B
SG117AHVG
SG117HVG/883B
SG117HVG
-55°C to
-55°C to
-55°C to
-55°C to
3-PIN HERMETIC TO-257
IG-PACKAGE (Isolated)
SG117AHVIG/883B
SG117AHVIG
SG117HVIG/883B
SG117HVIG
-55°C to 125°C
-55°C to 125°C
-55°C to 125°C
-55°C to 125°C
10-PIN CERAMIC
FLAT PACK
F-PACKAGE
SG117AHVF/883B
SG117AHVF
SG117HVF/883B
SG117HVF
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
(Nolo 3)
SG117AHVU883B
SG117AHVL
SG117HVU883B
SG117HVL
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
(Nolo 4) 1. SENSE
2. N.C.
3. N.C.
4. N.C.
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
Silicon General •
0
2
v"
3-PIN HERMETIC TO-257
G-PACKAGE (Non-Isolated)
20-PIN CERAMIC (LCC)
LEADLESS CHIP CARRIER
L- PACKAGE
I(J
o
a
"
IA
1
2
.3
5
6
-V'N -
4
(v)
7
8
9
40
t'-
30
SOOmA LOAD, 25°C
SG7905
20
10
o
10
10
100
lK
10K
100K
FREQUENCY-(HZ)
FIGURE 7.
DROP.OUT CHARACTERISTICS
FIGURES.
RIPPLE REJECTION VS. FREQUENCY
APPLICATIONS
C2
1.0I'F
f-----+--
C2
1.01'F
OUTPUT
f-=--....- -....- OUTPUT
FIGURE 10 - CIRCUIT FOR INCREASING OUTPUT VOLTAGE
FIGURE 9 - FIXED OUTPUT REGULATOR
NOTE: 1. Cl is required only if regulator is separated from rectifier
filter.
2. Both Cl and C2 should be low E.S.R. types such as solid
tantalum. If aluminum electrolitics are used, at least 10 times
values shown should be selected.
3. If large output capacities are used, the' regulators must be
protected from momentary input shorts. A high current diode
NOTE: C3 optional for improved transient response and ripple rajec-
4-33
R,+R,
Vour = V (REGULATOR)-R-,-
R = V(REG)
, ISmA
-S.OV & -S.2V NEGATIVE REGULATOR
SG120/SG320
ELECTRICAL SPECIFICATIONS (Note I)
SG120-0S/SG320-0S
(Unless otherwise specified, these specifications apply over full operating ambient temperatures for SG120-0S with -SS·C S T. S ISO·C, SG320-0S with
O·C S T. S; 12S·C, and V,N = -IOV, 10 = SmA, C'N = 211F, Caur = I.OI1F. Low duty cycle pulse testing techniques are used which maintains junction and
case temperature equal to the ambient temperature.)
Parameter
Output Voltage
Line Regulation (Note I)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ =25'C
Y'N = -7V to -25V, TJ = 25'C
Power Pkgs: 10 = 5mA to 1.5A, TJ = 25°C
T: Pkg: 10 = 5mA to 500mA, TJ = 25°C
VIN = -7.5Vto -25V
Power Pkgs: 10 = 5mA to 1.5A, P s 20W
T - Pkg: 10 = 5mA to 500mA, P s 2W
Y'N = -7V to -25V
With Line: VIN = -7V to -25V. TJ = 25°C
With Load: TJ = 25°C
Power Pkgs: 10 - SmA to I.SA
T - Pkg: 10 = 5mA to 500mA
AVo=100mV, TJ =25°C
Power Pkgs: 10 = 1.0A. T - Pkg: 10 = 500mA
Power Pkgs: TJ = 25°C
.
T - Pkg: TJ = 25°C
Power Pkgs: VIN = -35V, TJ =25°C
T - Pkg: Y'N = -35V, TJ = 25°C
AVIN = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. atTJ =125°C
10=5mA
SG120-0S
SG320-0S
Min. Typ. Max. Min. Typ. Max.
-4.9 -5.0 -5.1 -4.8 -5.0 -5.2
10
10
25
40
75
60 100
50
30
30
50
50
-4.8
-4.8
-5.0
-5.0
-5.2 -4.75 -5.00 -5.25
-S.2 -4.75 -5.00 -5.25
2
2
0.4
0.4
1.1
2.3
3.3
1.4
1.2
0.6
25
20
175
1.1
2.3
3.3
1.4
1.2
0.6
25
20
175
80
V
A
A
A
A
dB
IlVN
mV
°C
1.5
80
V
V
mA
mA
mA
mA
54
54
V
mV
mV
mV
0.4
0.4
0.4
0.4
1.5
0.5
Units
SGI20-S.21SG320-S.2
(Unless otherwise specified, these specifications apply overfull operating ambient temperatures for SGI20·S.2 with -SS·C S T. S ISO·C, SG320·S.2 with
O°C S T. S 12S·C, and V,N = -IOV, 10 = SmA, C'N = 211F, COUT = I.OI1F. Low duty cycle pulse testing techniques are used which maintains junction and
case temperature equal to the ambient temperature.)
Parameter
Test Conditions
TJ =25°C
Y'N = -7.2V to -25V, TJ = 25°C
Power Pkgs: 10 = 5mA to 1.5A, TJ = 25°C
T - Pkg: 10 = 5mA to 500mA, TJ = 25°C
V,N = -7.7V to -25V
Total Output Voltage
Tolerance
Power Pkgs: 10 = 5mA to 1.5A, P s 20W
T - Pkg: 10 = ,5mA to 500mA, P s 2W
Quiescent Current
Y'N = -7.2V to -25V
Quiescent Current Change
With Line: VIN .. -7.2Vto -25V, TJ = 25°C
With Load: TJ = 25°C
.,
Power Pkgs: 10 = 5mA to 1.5A
T - Pkg: 10 = 5mA to 500mA
Dropout Voltage
. AVo =100mV, TJ = 25°C
Power Pkgs: 10 = 1.5A, T - Pkg: 10 = 500mA
Peak Output Current
Power Pkgs: TJ = 25°C
..
T - Pkg: TJ = 25°C
Short Circuit Current
Power Pkgs: Y,N = ·35V, TJ = 25°C
T - Pkg: Y'N = -35V, TJ = 25°C
Ripple Rejection
AVIN = 10V, f = 120Hz, TJ = 25°C
Output Noise Voltage (rms) f = 10Hz to 100KHz (Note 2)
Long Term Stability
1000hrs. at TJ .. 125°C
Thermal Shutdown
10=5mA
Output Voltage
Line Regulation (Note I)
Load Regulation (Note 1)
SGI20-5.2
SG320-S.2
Units
Min. Typ. Max. Min. Typ. Max.
-5.4·
-5.0
-5.2
-5.1 -5.2 -5.3
V
15
10
40
mV
25
60
100
mV
50
75
30
30
50
mV
50
-5.0
-5.0
1.1
1.5
0.5
-5.4 -4.95 -5.20 -5.45
-5.4 -4.95 -5.20 -5.45
2
2
0.4
0.4
V
V
mA
mA
0.4
0.4
0.4
0.4
mA
mA
1.1
2.3
3;3
1.4
1.2
0.6
25
20
175
80
V
A
A
A
A
dB
IlVN
mV
°C
2.3
3.3
1.4
1.2
0.6
1.5
0.5
54
54
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4-34
-5.2
-5.2
25
20
175
80
-8V & -12V NEGATIVE REGULATOR
SG120/SG320
ELECTRICAL SPECIFICATIONS (Note 1)
SGI20-0S/SG320-0S
(Unless otherwise specified, these specifications apply over full operating ambienttemperatures for SG120-08 with -55'C,;; T.,;; 150'C, SG320-08 with
O'C ';;T.,;; 125'C, and V,N =-14V, 10 =5mA, C'N =1.01lF, COUT =1.0IlF. Low duty cycle pulse testing techniques are used which maintains junction and
case temperature equal to the ambient temperature.)
SG320-S
SGI20-S
Parameter
Test Conditions
Units
Min_ Typ, Max, MIn_ Typ, Max_
TJ = 2SoC
Output Voltage
-7.S -S.O -S.2 -7.7 -S.O -S.3
V
V1N = -10.SV to -2SV, TJ = 2SoC
Line Regulation (Note 1)
10
10
2S
40
mV
Power Pkgs: 10 = SmA to I.SA, TJ = 2SoC
Load Regulation (Note 1)
20
100
mV
20
80
T - Pkg: 10 = SmA to SOOmA, TJ = 2SoC
10
40
mV
10
2S
Total Output Voltage
V1N = '1 O.SV to -2SV
Power Pkgs: 10 = SmA to I.SA, P :;; 20W
Tolerance
-7.6S -8.00 -8.3S -7.6 -8.0 -8.4
V
T - Pkg: 10 = SmA to SOOmA, P :;; 2W
-7.6S -8.00 -8.3S -7.6 -8.0 -S.4
V
V1N = -10.SVto -2SV
2
mA
Quiescent Current
2
With Line: V1N = -10.SV to -2SV, TJ = 2SoC
Quiescent Current Change
mA
0.4
0.4
With Load: TJ = 2SoC
Power Pkgs: 10 = SmA to I.SA
mA
0.4
0.4
T - Pkg: 10 = SmA to SOOmA
0.4
mA
0.4
!!No = 100mV, TJ = 2SoC
Dropout Voltage
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = SOOmA
1.1
2.3
V
1.1
2.3
PoWer Pkgs: TJ = 2SoC
Peak Output Current
I.S
I.S
3.3
A
3.3
T - Pkg: TJ = 2SoC
1.4
O.S
1.4
A
O.S
Power Pkgs: V1N = -3SV, TJ = 2SoC
Short Circuit Current
1.2
A
1.2
T - Pkg: V1N = -3SV, TJ = 2SoC
0.6
0.6
A
tN1N = 10V, f = 120Hz, TJ = 2SoC
Ripple Rejection
54
dB
S4
2S
80
Output Noise Voltage (rms) f = 10Hz to 100KHz (Note 2)
2S
80
IlV/V
1000hrs. at TJ = 12SoC
Long Term Stability
32
32
mV
Thermal Shutdown
17S
10= SmA
17S
°C
SGI20-121SG320-12
(Unless otherwise specified, these specifications apply over full operating ambienttemperatures for SG120-12 with -55°C,;; T. ,;; 150'C, SG320-12 with
O'C,;; T.,;; 125'C, and V,N =-17V, 10 =5mA, C'N =2.0IlF, COUT = 1.0IlF. Low duty cycle pulse testing techniques are used which maintains junction and
case temperature equal to the ambient temperature.)
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage'(rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ =2SoC
V1N = -14V to -32V, TJ = 2SoC
Power Pkgs: 10 = SmA to 1.0A, TJ = 2SoC
T - Pkg: 10 = SmA to SOOmA, TJ = 2SoC
V1N = -14.5V to -32V
Power Pkgs: 10 = SmA to 1.0A, P :;; 20W
T - Pkg: 10 = 5mA to SOOmA, P :;; 2W
V1N = -14V to -32V
With Line: V1N = -14V to -32V, TJ = 2SoC
With Load: TJ = 25°C
Power Pkgs: 10 =5mA to 1.0A
T - Pkg: 10 = SmA to SOOmA
IlVo = 100mV, TJ =25°C
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = SOOmA
Power Pkgs: TJ = 2SoC
T - Pkg: TJ = 25°C
Power Pkgs: V1N = -35V, TJ = 25°C
T - Pkg: V1N = -3SV, TJ = 2SoC
IlV1N = 10V, f =120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 125°C
10= SmA
SG120-12
SG320-12
Min. Typ. Max. Min. Typ. Max.
-11.7 -12.0 -12.3 -11.6 -12.0 -12.4
4
20
4
10
30
SO
30
SO
10
10
40
2S
-11.S -12.0 -12.S -11.4 -12.0 -12.4
-11.5 -12.0 -12.5 -11.4 -12.0 -12.4
2
4
2
4
0.4
0.4
1.1
56
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4-3S
2S
48
17S
2.3
1.5
3.3
1.4 O.S
1.2 .
0.6
56
80
V
mV
mV
mV
V
V
mA
mA
0.4
0.4
mA
mA
1.1
2.3
3.3
1.4
1.2
0.6
25
4S
175
80
V
A
A
A
A
dB
IlV/V
mV
°C
0.4
0.4
I.S
O.S
UnIts
•
SG120lSG320
-15V & -18V NEGATIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
SG120-15/SG320-15
(Unless otherwise specified, these specifications apply overfull operating ambient temperatures for SG120-15 with -55°C ST. S150°C, SG320-15 with
O°C ST. S125°C, and V,N = -20V, 10 = 5mA, C'N = 2.011F, COUT = 1.0I1F. Low duty cycle pulse testing techniques are used which maintains junction and
case temperature equal to the ambient temperature.)
SG120-15
SG320-15
Parameter
Units
Test Conditions
Min. Typ. Max. Min. Typ. Max.
TJ =25°C
-14.7 -15.0 -15.3 -14.6 ·15.0 ·15.4
V
Output Voltage
Line Regulation (Note 1)
VIN = -17V to -35V, TJ = 25°C
5
20
mV
5
10
Load Regulation (Note 1)
Power Pkgs: 10 = 5mA to 1.0A, TJ = 25°C
30
80
mV
30
80
T - Pkg: 10 = 5mA to 500mA, TJ = 25°C
10
40
10
mV
25
Total Output Voltage
VJN - ·17.5V to -35V
Tolerance
Power Pkgs: 10 = 5mA to 1.0A, P :5 20W
-14.5 -15.0 -15.5 -14.4 -15.0 -15.6
V
. T • Pkg: 10 = 5mA to 500mA, P :5 2W
-14.5 ·15.0 -15.5 ·14.4 ·15.0 ·15.6
V
VIN = -17V to -35V
2
4
Quiescent Current
rnA
2
4
Quiescent Current Change With Line: VJN = -17V to ·35V, TJ = 25°C
0.4
rnA
0.4
With Load: TJ = 25°C
Power Pkgs: 10 = SmA to 1.0A
rnA
0.4
0.4
0.4
T - Pkg: 10 = 5mA to 500mA
rnA
0.4
Dropout Voltage
/lVo =100mV, TJ =25°C
Power Pkgs: 10 =1.0A, T - Pkg: 10 = 500mA
1.1
2.3
1.1
2.3
V
Power Pkgs: TJ = 2SoC
1.5
Peak Output Current
'3.3
3.3
A
I.S
T· Pkg: TJ = 25°C
0.5
1.4
A
0.5
1.4
Power Pkgs: VIN = -3SV, TJ =2SoC
1.2
Short Circuit Current
1.2
A
T - Pkg: VIN = -35V, TJ = 25°C
0.6
A
0.6
/lVIN = 10V, f =120Hz, TJ '= 2SoC
Ripple Rejection
S6
S6
dB
25 . 80
Output Noise Voltage (rms) f =10Hz to 100KHz (Note 2)
25
80
IlVN
1000hrs. at TJ = 12SoC
Long Term Stability
60
.mV
60
Thermal Shutdown
175
10 = 5mA
175
°C
SG120-18/SG320-18
(Unless otherwise specified, these specifications apply over full operating ambient temperatures for SG120-18 with -55°C ST. S150°C, SG320-18 with
O°C ST. S125°C, and V,N = -27V, 10= 5mA, C'N = 2.011F, COUT = 1.011F. Low duty cycle pulse testing techniques are used which maintains junction and
. case temperature equal to the ambient temperature.)
Parameter
Test Conditions
TJ =25°C
VIN = ·21 V to -33V, TJ = 25°C
Power Pkgs: 10 =SmA to 1.0A, TJ = 25°C
T - Pkg: 10 =5mA to 500mA, TJ =25°C
Total Output Voltage
VIN =·22V to -33V
Tolerance
Power Pkgs: 10 = 5mA to 1.0A, P :5 20W
T • Pkg: 10 =5mA to SOOmA, P :5 2W .
Quiescent Current
VIN =-21V to -33V
Quiescent Current Change With Line: VJN =·21V to ·33V, TJ =25°C
With Load: TJ =25°C
Power Pkgs: 10 = 5mA to 1.0A
T - Pkg: 10 = 5mA to 500mA
Dropout Voltage
/lVo = 100mV, TJ =25°C
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = 500mA
Power Pkgs: TJ = 2SoC
Peak OutpUt Current
T - Pkg: TJ = 25°C
Short Circuit Current
Power Pkgs: VIN =-35V, TJ = 25'C
T - Pkg: VIN = -35V, TJ = 25°C
.Ripple Rejection
/lVIN =10V,f =120Hz, TJ =25°C
Output Noise Voltage (rms) . f = 10Hz to 100KHz (Note 2)
LOng Term Stability
1000hrs. atTJ =125°C
Thermal Shutdown
10=5mA
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
SG320-18
SG120-18
Min. Typ. Max. Min. Typ. Max.
-17.6 -18.0 ·18.4 ·17.4 ·18.0 ·18.6
5
5
20
10
30
30
80
80
10
10
40
25
-17.4 -18.0 '18.6 -17.1 -18.0 -18.9
~17.4 ·18.0 ·18.6 -17.1 -18.0 -18.9
2
4
2
4
0.4
0.4
0.4
0.4
1.1
I.S
0.5
4-36
1.1
1.5
0.5
56
56
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
2.3
3.3
1.4
1.2
0.6
25
.72
175
"
80
72
175
Units
V
mV
mV
mV
V
V
rnA
·mA
0.4
0.4
rnA
rnA
2.3
3.3
1.4
1.2
0.6
V
A
A
A
A
dB
IlVN
mV
°C
SG120/SG320
-20V NEGATIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
SG120-20/SG320-20
(Unless otherwise specified, these specifications apply over full operating ambient temperatures for SG120-20 with -55°C :s; T.:s; 150°C, SG320-20 with
O°C :S;T.:S; 125°C, and V,N = -29V, 10 = 5mA, C'N = 2.011F, COUT = 1.0I1F. Low duty cycle pulse testing techniques are used which maintains junction and
case temperature equal to the ambient temperature )
SG120-20
SG320-20
Parameter
Units
Test Conditions
Min. Typ. Max. Min. Typ. Max.
Output Voltage
V
TJ = 25°C
-19.5 -20.0 -20.5 -19.2 -20.0 -20.8
Line Regulation (Note 1)
VIN =-23V to -35V. TJ =25°C
5
20
mV
5
10
Load Regulation (Note 1)
Power Pkgs: 10 =SmA to 1.0A. TJ =25°C
mV
30
30
80
80
T - Pkg: 10 =5mA to 500mA. TJ =25°C
10
25
mV
10
25
Total Output Voltage
VIN = -24V to -35V
Tolerance
Power Pkgs: 10 = 5mA to 1.0A. P ~ 20W
V
-19.3 -20.0 -20.7 -19.0 -20.0 -21.0
T - Pkg: 10 =5mA to 500mA, P ~ 2W
V
-19.3 -20.0 -20.7 -19.0 -20.0 -21.0
Quiescent Current
2
VIN =-23V to -35V
2
4
mA
4
Quiescent Current Change
With Line: VIN =-23V to -35V. TJ =25°C
0.4
mA
0.4
With Load: TJ =25°C
Power Pkgs: 10 =5mA to 1.0A
0.4
mA
0.4
T - Pkg: 10 = 5mA to 500mA
0.4
mA
0.4
Dropout Voltage
AVo = 100mV. TJ =25°C
Power Pkgs: 10 = 1.0A. T - Pkg: 10 =500mA
1.1
1.1
2.3
V
2.3
Peak Output Current
Power Pkgs: TJ =25°C
1.5
1.5
3.3
A
3.3
T - Pkg: TJ = 25°C
0.5
1.4
0.5
1.4
A
A
Short Circuit Current
Power Pkgs: VIN =-35V. TJ =25°C
1.2
1.2
A
T - Pkg: VIN =-35V. TJ =25°C
0.6
0.6
Ripple Rejection
AVIN =10V, f = 120Hz, TJ =25°C
56
dB
56
Output Noise Voltage (rms) f = 10Hz to 100KHz (Note 2)
25
80
25
80
IlVN
1000hrs. at TJ =125°C
Long Term Stability
80
mV
80
Thermal Shutdown
175
175
°C
10=5mA
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4-37
•
8G12018G320
NEGATIVE REGULATOR
<
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
3·TERMINAL TO-3
METAL CAN
K-PACKAGE
Part No.
SG120-XXKl883B
SG120-XXK
SG320-XXK
(See Notes Below)
Ambient
Temperature Range
Connection Diagram
-55°C to 125°C
-55°C to 125°C
O°Cto 70°C
GROUND
~.,.
v"'"
3-TERMINAL TO-56
METAL CAN
R-PACKAGE
SG120-XXA/883B
SG120-XXR
SG320-XXR
-55°C to 125°C
-55°C to 125°C
O°C to 70°C
GROUND
....
0
I I
I SU3~A
~
:::>
0....
:::>
Yi'i
2% RESISTORS
1% RESISTORS
po
4
6
10
20
OUTPUT VOLTAGE
April 1990
4-39
40
100
•
SG137AISG137 SERIES
ABSOLUTE MAXIMUM RATINGS (Note I)
Power Dissipation ........................................... Internally Limited
Input to Output Voltage Differential.................................. 40V
Storage Temperature Range ............................ -65°C to 150°C
Note 1. Exceeding these ratings could cause damage to the device.
Operating Junction Temperature
Hermetic (K, R, T, L, G, IG-Packages) ......................... 150°C
Lead Temperature (Soldering, 10 Seconds) ................ 300°C
THERMAL DERATING CURVES
5.0 r--r-~--r--,-.,.---r--..,.----.
~,
~
30
~
~
~
~
~
ii
"
~
2.0
i
20
175
AMBIENT TEMPERATURE -
-c
CASE TEMPERATURE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2 & 3)
Input Voltage Range ............................... -(VOUT + 3.5V) to -36V
Operating Junction Temperature Range
SG137NSG137 ............................................. -55°C to 150°C
SG237NSG237 ............................................. -25°C to 150°C
SG337NSG337 ................................................ O°C to 125°C
Note 2. Range over which the device is functional.
Note 3. These ratings are applicable for junction temperatures of less than 135°C.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified. these specifications apply over full operating ambienttemperatures for SG137A1SG137 with -55°C ST. S 150°C, SG237A1
SG237 with -25°C sT. S 150°C, SG337A1SG337 with O°C ST. S 125°C, IV'N - Vourl = 5.0V, and for lour = 500mA (K, R, G, and IG power packages) and
lOUT = 100mA (T, F. and L packages). Although power dissipation is internally limited. these specifications are applicable for power dissipations of 2W
for the T, F and L packages, and 20W for the K, R, G, and IG packages. 'MAl( is 1.5A for the K, R, G, and IG packages and O.5Afor the T, F and L packages.
Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
SG137A1SG237A
SG137/SG237
Parameter
Test Conditions
Units
Min. Typ. Max. Min. Typ. Max.
Reference Voltage
1.238
-1.250
1.262 1.225 1.250 -1.275
V
lOUT = 10mA, TA = 25°C
1.220 -1.250 -1.280 1.200 -1.250 -1.300
V
3V:s; IV'N - VouTI S 40V, 1OmA:s; lOUT :s; IMAX
Line Regulation (Note 4)
3V :iqV,N - VoUTI:S; 40V, 10UT:S; IMAX
0.005 0.01
0.01 0.02
TA = 25°C
%N
Load Regulation (Note 4)
1OmA :s; lOUT ::; IMAX
5
25
15
mV
25
IVOUTI:S; 5V, TA = 25°C
0.1
0.5
0.3
0.5
%
IVOUTI~ 5V, TA = 25°C
10
50
20
mV
50
IVOUTI:S;5V
0.2
1.0
0.3
%
1.0
IVOUTI~ 5V
Thermal Regulation (Note 5)
TA= 25°C, 10ms pulse
0.002 0.02
0.002 0.02 %/W
Ripple Rejection
VOUT = -10V, f =120Hz
60
66
60
dB
CADJ = 0, TA =.25°C
70
80
66
77
dB
CADJ = IOIlF
Adjust Pin Current
65
100
65
100
TA = 25°C
IJA
Adjust Pin Current Change
1.0
2
5
5
3V::; IV,N - VOUTI :s; 40V
IJA
0.2
0.5
2
10mA :s; lOUT :s; IMAX
5
IJA
4-40
SG137AISG137 SERIES
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Minimum Load Current
Current Limit
Temperature Stability (Note 5)
Long Term Stability (Note 5)
RMS Output Noise (% 01 VOIlT)
Parameter
Reference Voltage
Line Regulation (Note 4)
Load Regulation (Note 4)
Thermal Regulation (Note 5)
Ripple Rejection
Adjust Pin Current
Adjust Pin Current Change
Minimum Load Current
Current Limit
Temperature Stability (Note 5)
Long Term Stability (Note 5)
RMS Output Noise (% 01 Your)
Test Conditions
IV,N - Vourl ::;; 40V
W'N - Vourl::;; 10V
IV,N - VoUTI::;; 15V
K, P, R, G,IG Packages
T, L, Packages
IV,N - Vourl ::;; 40V, TJ = 25°C
K, P, R, G,IG Packages
T, L, Packages
SG137AlSG237 A
SG137/SG237
Min. Typ. Max. Min. Typ. Max.
5.0
2.5
2.5
5.0
1.2
3
1.2 3.0
1.5
0.5
2.2
0.8
3.2
1.5
1.5
0.5
0.24
0.15
0.4
0.25
0.6
0.3
0.003
1.0
0.5
1.5
1.0
0.24
0.15
TA = 125°C, 1000 Hours
TA = 25°C,10Hz::;;f::;; 10 KHz (Note 5)
Test Conditions
lOUT = 10mA, TA = 25°C
3V ::;; IV,N - Vourl ~ 40V, 1OmA ::;; lour::;; IMAX
3V ::;; IV,N - Vourl::;; 40V, lour::;; 1MAl(
TA = 25°C
1OmA ~ lOUT ::;; 1MAl(
IVourl~ 5V, TA = 25°C
IVourl~ 5V, TA = 25°C
IVour l::;;5V
IVOUTI~ 5V
TA= 25°C, 10ms pulse
Your = -10V, 1 =120Hz
CADJ = 0, TA = 25°C
CAOJ = lOIlF
TA = 25°C
3V::;; IV,N - Vourl::;; 40V
1OmA ~ lOUT ~ IMAX
IV,N - VOUTI ::;; 40V
IV,N - Vourl::;; 10V
IV,N - Vourl::;; 15V
K, P, R, G, IG-Packages
T, L-Packages
IV,N - Vourl::;; 40V, TJ = 25°C
K, P, R, G,IG- Packages
T, L·Packages
TA = 125°C, 1000hr
T~ = 25°C, 10Hz::;; f ::;; 10KHz (Note 5)
Units
mA
mA
A
A
2.2
0.8
0.4
0.25
0.6·
0.3
1.0
0.003
A
A
%
%
%
SG337A
SG337
Units
Min. Typ. Max. Min. Typ. Max.
V
1.238 -1.250 -1.262 1.213 -1.250 -1.287
1.220 -1.250 -1.280 1.200 -1.250 -1.300
V
0.005 0.01
0.01
0.04
%/V
5
25
0.1
0.5
10
50
0.2
1.0
0.002 0.02
15
50
0.3
1.0
20
70
0.3
1,5
0.003 0.04
mV
%
mV
%
%IW
66
80
65
1.0
0.2
2.5
1.2
100
5
2
5
3
1.5
0.5
2.2
0.8
3.5
1.5
1.5
0.5
2.2
0.8
A
A
0.24
0.15
0.5
0.25
0.6
0.3
0.003
1.0
0.5
1.5
1.0
0.15
0.10
0.4
0.17
0.6
0.3
0.003
A
A
%
%
%
60
70
66
60
77
65
2
0.5
2.5
1
100
5
5
10
6
1.0
dB
dB
jJA
jJA
jJA
mA
mA
Note 4. Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to heating
effects are covered under the specification for thermal regulation.
Note 5. These parameters, although guaranteed, are not tested in production.
4 - 41
•
SG137AISG137 SERIES
CHARACTERISTIC CURVES
3.0
E
"-
'z"
~
1.27
1.6
2.2
l - I-
~
=>
1.8
=>
~
.'.
l.-"
0
=>
"~
1.4 ~
1.oL,...-~
"~,,or:.
~
~l" 'j,'J0C~
~o '/
..
E
'"
~
.,
1.4
1.26
-
t!
w
u
1.25
~
~l:P
~
. . .n
1.24
1.2
0.8
1.6
2.0
0
50
25
0.2
.,
t!
~
~
~
~
a
---
I- ""'
r--."
0
-0.2
"10
5
3:
I-
~
-0.4
0.4
~
=>
I"
0.4
1.2
0.8
2
~
~
\. .
.
,
\~
T
PACKAGED
DEVICE
\
"
~
'~
r-~
10
20
20
30
.
75
z
70
'"u'"=>
65
w
40
!'.
~
~
V
-
~
-,
~
~
15
~
-.
~
F'== :.::=
30
40
INPUT -OUTPUT DIFFERENTIAL (V)
FIGURE 4.•
OUTPUT VOLTAGE DEVIATION
VS. OUTPUT CURRENT
10
80
P AND K
0
OUTPUT CURRENT (A)
IFfII
FIGURE 3.
CURRENT VS. INPUT/OUTPUT DIFFERENTIAL
PACKAGED
DEVICES
"
2.0
"
.. 25°C
INPUT -OUTPUT DIFFERENTIAL (V)
::.::.. ~
0
1.6
~...... ~
-1500~.::.r
---,..
0
TJ .. 25 C
0
0
0.6
Tj
_ ... - - TJ .. _55°C
- - TJ-150oC
--
z
r
0.8
75 100 125 150
FIGURE 2.
REFERENCE VOLTAGE VS. TEMPERATURE
0.4
0
~
a
~},
1.0
TEMPERATURE (OC)
3
"
~
0
-75 -50 25
FIGURE ,.
INPUT/oUTPUT DIFFERENTIAL
VS. OUTPUT CURRENT
«
~
oS
.j
1.2
0.2
OUTPUT CURRENT (A)
0
<'
1.23
0.4
0
g
,~
J .. _55°C
2.6
C
I"
1.8
FIGURE 5.
INPUT/oUTPUT DIFFERENTIAL
VS. OUTPUT CURRENT
60
55
50
-75 -50 -25
0
25
50
75 100 125 150
TEMPtRATURE COC)
FIGURES.
ADJUSTMENT CURRENT VS. TEMPERATURE
.. The SG137A has load regulation compensation which
makes the typical unit read close to zero. This band
represents the typical production spread.
APPLICATION INFORMATION
OUTPUT VOLTAGE
The output voltage is determined by two external resistors, R, &
R2(see Figure 7).
• C,
,~
''''''
;;,
.2
+
-I"OJ
! ., 'F ;J.
I
R2=
,"EF
AoJ
-VIN-YVIN
SG1.37A
VlJ(n
FIGURE 7
The exact formula for the output voltage is:
Vour = VREF (
R2+R,.
) + IADJ (R2)
R,
Where: VREF =Reference Voltage, IADJ = Adjustment Pin Current.
In most applications, the second term is small enough to be
ignored, typically about 0.5% of VOUT' In more critical applications,
the exact formula should be used, with IADJ equal to 65JJA. Solving
for R2 yields:
-VOUT
V01If - VREF
~+I
R,
ADJ
Smaller values of R, and R2 will reduce the influence of IADJ on the
output voltage, but the no-load current drain on the regulator will
be increased. Typical values for R, are between 1oon and 300n,
giving 12.5 mA and 4.2mA no-load current respectively. There is
an additional consideration in selecting R, the minimum load
current specification olthe regulator. The operating current oltha
4-42
SG137AISG137 SERIES
APPLICATION INFORMATION (continued)
SG137A flows from input to output. If this current is not absorbed
by the load, the output olthe regulator will rise above the regulated
value. The current drawn by R, and R2 is normally high enough
to absorb the current, but care must be taken in no-load situations
where R, and R2 have high values. The maximum value for the
operating current, which must be absorbed, is 5mA for the
SG137A, If input-output voltage differential is less than 10V, the
operating current that must be absorbed drops to 3mA.
EXAMPLES:
1. A precision 10V regulator to supply up to lAmp load current.
a. Select R, = 1000 to minimize effect of I.OJ
b.
CI I
VaUT - VREF
10V -1.25V
acu ate R, (VRE,!R,) + IADJ (1.25V/l000) + 6511A = 7040
2. A 15V regulator to run off batteries and supply 50mA.
V,N MAX=25V
a. To minimize battery drain, select R, as high as possible
- 1.25V
-4170
R,3mA , use4040, 1°'•
TYPICAL APPLICATIONS
The outp,ut stability, load regulation, line regulation, thermal
regulation, temperature drift, long term drift, and noise, can be
improved by a factor of 6.6 over the standard regulator configuration. This assumes a zener whose drift and noise is considerably
better than the regulator itself. The LM3298 has 20PPM/oC
maximum drift and about 10 times lower noise than the regulator.
.,
CJ
'''
C'
",
saUD
.,
TANTALUM
1200
-VIN
In the application shown Figure 8, regulators #2 to #N will track
regulator #1 to within ±24mV initially, and to ±60mVover all load,
line, and temperature conditions. If any regulator output is shorted
to ground, all other outputs will drop to -2V. Load regulation of
regulators #2 to #N will be improved by Vou!1.25V compared to
a standard regulator, so regulator #1 should be the one which has
the lowest load current.
--+-----1
I - - I - - - j......-
......-
1--1--')>---......-
-VotJT
-VOOT2
I
I
I
~J r----JJ~~~~~:~,:r-J
L...........
' ---iIVIN
SRG~J~~
Vouri-:-
01+
tci:o
l ____...._T_A.NT~~~TIN
.......
II.. _________ .JI
7V
lM329B
FIGURE 8 • MULTIPLE TRACKING REGULATORS
R2"
+
~citD
TANTALUM
Rl
lK
1%
1 " - - - - - - -......"R2 =
9.0:~U~O-,
-VOUT
k-----.,.--r---
+VOUT
1'-----+--1--
-VOUT
-9080
FIGURE 9· HIGH STABILITY REGULATOR
'2
5K
,---t--;'"
R'
I
H -
V,N
SG337A
5K
+ Cl
1~
1,..-
AOJ
SOUD
TANTALUM
VOUT
Rs
-;-
(+)
I "" 65JJA
+ 1.~~V
(0.80 S Rs S 2500)
·"R1 or RS may be trimmed 51ightly to improve tracking
FIGURE 11 • DUAL TRACKING SUPPLY %1.25V 10 ±2.0V
FIGURE 10· CURRENT REGULATOR
4-43
•
SG137AISG137 SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
3·TERMINAL TO-3
METAL CAN
K-PACKAGE
Part No.
Ambient
Temperature Range
SG137AK/883B
SG137AK
SG237AK
SG337AK
SG137K/883B
SG137K
SG237K
SG337K
-55°e to 125°e
-55°e to 125°C
-25°C to 85°C
ooe to 70e
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
ooe to 70°C
SG137AR/883B
SG137AR
SG237AR
SG337AR
SG137R!883B
SG137R
SG237R
SG337R
-55°C to
-55°C to
-25°C to
ooe to
-55°e to
-55°C to
-25°e to
ooe to
SG137AT/883B
SG137AT
SG237AT
SG337AT
SG137T1883B
SG137T
SG237T
SG337T
-55°e to 125°e
-55°e to 125°e
-25°e to 85°e
ooe to 70 0 e
-55°e to 125°e
-55°e to 125°e
-25°e to 85°C
ooe to 70 0 e
3-PIN HERMETIC TO-257
G-PACKAGE (Non-Isolated)
SG137AG/883B
SG137AG
SG137G/883B
SG137G
-55°e to
-55°e to
-55°e to
-55°e to
125°e
125°e
125°e
125°e
3-PIN HERMETIC TO-257
IG-PACKAGE (Isolated)
SG137AIG/883B
SG137AIG
SG1371G/883B
SG1371G
-55°e
-55°C
-55°C
-55°e
to
to
to
to
125°e
125°e
125°e
125°e
20-PIN CERAMIC (LCC)
LEAD LESS CHIP CARRIER
L- PACKAGE
SG137AU883B
SG137AL
SG137U883B
SG137L
-55°e to
-55°C to
-55°e to
-55°e to
125°e
125°e
125°e
125°e
3-TERMINAL TO-66
METAL CAN
R-PACKAGE
3-PIN TO-39 METAL CAN
T-PACKAGE
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
Silicon General •
Connection Diagram
ADJUSTMENT
1
0
0
®
CASE ISV1N
VOUT
125°C
125°e
85°e
70 0 e
125°C
125°C
85°e
70 0 e
ADJUSTMENT
CD
0
0
®
CASE IS
VIN
Voo,
="~'~cQ
vo",
IV
®
v"
VOUT
0
1
I
1
(No1e4)
3
1. VOUT
2. Vour
3.
4.
5.
6.
7.
8.
9.
10.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
:
2
1
~'DJUST
20 19
'0"
,
17
6'
16
7
,
15
14
9
10 11
12 13
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
VIN
N.C.
N.C.
N.C.
N.C.
ADJUST
N.C.
N.C.
N.C.
N.C.
3. Product is also available in flatpack. Consult factory for price and delivery.
4. Both outputs must be externally connected together at the device terminals.
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
4-44
SG138AISG238AISG338A
SG1381SG2381SG338
SILICON
GENERAL
5 AMP POSITIVE ADJUSTABLE
VOLTAGE REGLATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG138A series are 3-terminal positive adjustable voltage regulators capable
of supplying in excess of 5A over a 1.25V to 32V output voltage range. These
regulators are exceptionally easy to use, requiring only two external resistors to
program the output voltage. In addition, a major feature of the "A" version device
is the initial output voltage tolerance which is guaranteed to be within ±1 % at room
temperature. Over full operating conditions, including load, line, and power dissipation, the reference is guaranteed not to very more than 2%.
• Guaranteed 5A output current
• Guaranteed 1% output voltage tolerance
• Guaranteed 0.3 % load regulation
• Guaranteed 0.01% line regulation
• Low TC internal current limit
• Thermal overload protection
• Improved output transistor safe operating area compensation
• Output adjustable from 1.25V to 32V
• Paralleling regulators for higher
output current
A novel characteristic of the SG138A series is its new current limit circuitry, which
allows transient load currents of up to 12A to be safely delivered to the load without
additional protection schemes.
The SG138A is an improved version of the popular LM138, and utilizes advanced
circuit design, device layout, and processing techniques in order to provide
superior performance and reliability.
HIGH RELIABILITY FEATURES
-SG138A1SG138
• Available to MIL-STD-883
• SG level "S" processing available
SCHEMATIC
April 1990
4 - 45
•
SG138AISG138 SERIES
ABSOLUTE MAXIMUM RATINGS (Note 1)
Power Dissipation ........................................... Internally Limited
Input to Output Voltage Differential ................................... 35V
Storage Temperature Range ............................ -65°C to 150°C
Note 1. Exceeding these ratings could cause damage to the device.
Operating Junction Temperature
Hermetic (K, G, IG-Packages) ...................................... 150°C
Lead Temperature (Soldering, 10 Seconds) ................... 300°C
THERMAL DERATING CURVES
~~
'.0
4.0
"
i "+~
i
,
30
~
~
"-..,,;
is
,
4""
IJ..~
c~
~~
~
~~~
2.0
~
:.?.,.~
1.0
0
~
c
i5
2.
50
7.
~
100
.~~~
'0
r",
"
1.250
-<
50
r--;r-~--r--;r--,
0.1
~
r-
i-"""
l--" l--"
;;;
....
0.01
"10
5
1.230
25
75 100 125 150
a
~O-25
TEMPERATURE-("c)
~
~
75
0.001
t__--t"~-t__-_T.,___;:::__t__--j
0.0001 '--~--'--~--'--""
10K
100K
1M
10
100
1K
1001251~
TEMPERATURE-("c)
FIGURE 4.
ADJUSTMENT CURRENT VS. TEMPERATURE
FREQUENCV-(Hz)
FIGURES.
TEMPERATURE STABILIlY
FIGURE 6.
OUTPUT IMPEDANCE VS. FREQUENCY
100
100
cADJJO,uF
TJoa,;O'\::
TJ=25~
~~
V. I-'"
~ ~ k·si'c
V
~~ lo
o
~
>=
~
60
'"
15
20
25
30
35
FIGURE 7.
MINIMUM OPERATING CURRENT VS.INPUTOUTPUT DIFFERENTIAL
40
.,
~
CAO)O
5<=
~
~
''IN- VOUr=5V
'"
f=120Hz
TJ·'T
o
IL:
-
~ADJ"10¢'"
CADJ""O
60
40
a.
lour-SOOmA
20
80
w
1'-1"'"
40
a.
o
10
...
80
!
~
V
INPUT-OUTPUT DIFFERENTlAL-(V)
75100125150
I
tJ
z
~ 1.240
a
-50 -25
~
FIGURE 3.
DROPOUT VOLTAGE VS. TEMPERATURE
J,.260
~
I
35
25
TEMPERATURE-("c)
10
tJ
40
~
a
~O-25
75100125150
;;-
I-"
1/
V
<.>
~"l
25
FIGURE 2.
LOAD REGULATION VS. TEMPERATURE
i.-"" I '
"<
IOUr-JA
:r,:-l"- t- r----
TEMPERATURE-("c)
1.270
60
c:t:
~
5V
~O-25
65
~
~
I---' r---
IOUT=5"
YOUr- lOV
PRELOAD= Om'
100
FIGURE t.
OUTPUT VOLTAGE ERROR VS. OUTPUT VOLTAGE
55
......
-0.2
. OUTPUT VOLTAGE-(V)
!-
g~
\1N"" VOUT'"20V
~<
:OI
\1.r Vour- 3OY
10
'00
I
~,
oz
I.....~
>0
!;(
~~
-,
:00
0
-2
<-
-3
g:~
I---n,V':::U;OF"lOiVv.L-+-+eo=UTori.o;\-f--+--l
f----t;~"'c~T';t,~i~"'mt-'--+f--tc"'A"'OJt'.O'-f--t---l
-1.5
'IN=l:>V
Vout=10V
i
1.0
'-
13
0.5
10
20
30
'iI
g
40
1\
\.
20
'0
TIME-(us)
TIME-(ms)
FIGURE 13.
CURRENT LIMIT VS. PERIOD
~E
a.U
~
0
0.1
I
w
1--11'-~+--t-'l.-.--1",f-F'-Cl-f_'-O",-t---I-+--l
~~
i"iiiWF'i
FIGURE 12.
CURRENT LIMIT VS. PERIOD
0 f--+-+--+--+--+-+--t--+---1
,,<
"'
13
30
FIGURE 11.
CURRENT LIMIT VS. INPUT· OUTPUT DIFFERENTIAL
PRELOAD
-
20
10
INPUT-OUTPUT DIFFERENTIAL-{V)
FIGURE 10.
RIPPLE REJECTION
'2
\o\N'" 0
···.~I
0
'0
OUTPUT CURRENT-(A)
'4
0=1
- •• PREL~AD .. O
f-120Hz
40 '-"='-'-'...J..J-U.L.I..-__-'-.......L..l..J...J..L.U
RELOAO .. O
f, .'
i
50
r-rTrT'TTTTr111--nl-rrrrrn---.--rrmm
'2 ~~d+~--~+t~--~tH~
TCAS[-2SOc
PRELOAO=;j"
"' •••
<-
14
DC CURRENT LIMIT
30
TlME-(us)
FIGURE 14.
LINE TRANSIENT RESPONSE VS. PERIOD
FIGURE 15.
LOAD TRANSIENT RESPONSE VS. PERIOD
APPLICATION INFORMATION
GENERAL
The SG138A develops a 1.25V referenCe voltage between the
output and the adjustable terminal (see Figure 1). By placing a resistor, R1, between these two terminals, a constant current is
caused to flow through R1 and down through R2 to set the overall output voltage. Normally this current is the specified minimum
load current of 5mA or 10mA. Because IADJ is very small and constant when compared with the current through R1, it represents a
small error and can usually be ignored. It is easily seen from the
output voltage equation, that even if the resistors were of exact
value, the accuracy olthe output is limited by the accuracy of VREF.
Earlier adjustable regulators had a reference tolerance of ±4%
which is dangerously close to the ±5% supply tolerance required
in many logic and analog systems. Further, even 1% resistors can
drift 0.01 %I'C, adding additional error to the output voltage tolerance.
4-49
SG338A
VINr-
J
,
OUT 1-----.....----- VOUT
IN
ADJ.
VREF
Lh
IADJ
R,
t
R2
5D JJ.A
VOUT~
VREF (1+
:~ )+1
ADJ R2
FIGURE'6· BASIC ADJUSTABLE REGULATOR
40
SG138AISG138 SERIES
APPLICATION INFORMATION
(continued)
For example, using 2% resistors and ±4% tolerance for V REF' calculations will show that the expected range of a 5V regulator
design would be 4.66V ~ VOUT ~ 5.36V or approximately ±7%. If
the same example were used for a 15V regulator, the expected tolerance would be ±8%. With these results most applications required some method of trimming, usually a trim pot. This solution
is both expensive and not conducive to volume production
One of the enhancements of Silicon General's adjustable regulators over existing devices is the tightened initial tolerance of V REF'
This allows relatively inexpensive 1% or 2% film resistors to be
used to Rl and R2 to set the output voltage within an acceptable
tolerance.
PROTECTION DIODES
The SG 138N338A do not require a protection diode from the adjustment terminal to the output (see FigureI7). Improved internal
circuitry eliminates the need for this diode when the adjustment
pin is bypassed with a capacitor to improve ripple rejection. If a
very large output capacitor is used, such as a IOOIlF shown in
Figure 2, the regulator could be damaged or destroyed if the input
is accidentally shorted to ground or crowbarred, due to the output
capacitor discharging into the output terminal of the regulator. To
prevent this, a diode Dl as shown, is recommended to safely
discharge the capacitor.
~
With a guaranteed 1% reference, a 5V power supply design, using
±2% resistors, would have a worst case manufacturing tolerance
of ±4%. If 1% resistors are used, the tolerance will drop to ±2.5%.
A plot of the worst case output voltage tolerance as a function of
resistor tolerance is shown on the front page.
VIN
01
IN4002
SG338A
IN
OUTI---t--t--r-VOUT
iI~.
t--l--+----"Ii
R,
ADJ
7
10,£ :::kr(CADJ
R,
For convenience, a table of standard 1% resistor values is shown
below.
1.47
1.50
1.54
1.58
1.62
1.65
1.69
1.74
1.78
1.82
1.87
1.91
1.96
2.00
2.05
2.10
2.15
2.21
2.26
2.32
2.37
2.43
2.49
2.55
2.61
2.67
2.74
2.80
2.87
2.94
3.01
3.09
3.16
3.24
3.32
3.40
3.48
3.57
3.65
3.74
3.83
3.92
4.02
4.12
4.22
4.32
4.42
4.53
4.64
4.75
4.87
4.99
5.11
5.23
5.36
5.49
5.62
5.76
5.90
6.04
6.19
6.34
6.49
6.65
CoUT
NOT NEEDED
FIGURE 17 - REMOVING PROTECTION DIODE
Table of Yz% and 1% Standard Resistance Values
1.00
1.02
1.05
1.07
1.10
1.13
1.15
1.18
1.21
1.24
1.27
1.30
1.33
1.37
1.40
1.43
100",
LOAD REGULATION
6.81
6.98
7.15
7.32
7.50
7.68
7.87
8.06
8.25
8.45
8.66
8.87
9.09
9.31
9.53
9.76
Because the SG138A is a three-terminal device, it is not possible
to provide true remote load sensing. Load regulation will be limited by the resistance of the wire connecting the regulator to the
load. The data sheet specification for load regulation is measured
at the bottom of the package. Negative side sensing is a true
Kelvin connection, with the bottom of the output divider returned
to the negative side of the load. Although it may not be immediately obvious, best load regulation is obtained when the top of the
resistor divider, (Rl), is connected directly to the case not to the
load. This is illustrated in Figure 18. If Rl were connected to the
load, the effective resistance between the regulator and the load
would be
Rp X ( R2 ~1 Rl ) ,Rp = Parasitic Line Resistance.
Connected as shown, Rp is not multiplied by the divider ratio. Rp
is about 0.004Q per foot using 16 gauge wire. This translates to
4mV/ft at lA load current, so it is important to keep the positive
lead between regulator and load as short as possible, and use
large wire or PC board traces.
Standard Resistance Values are obtained from the Decade
Table by multiplying by multiples of 10. As an example:l.21 can
represent 1.2Hl, 12.10, 121 n, 1.21 Kn etc.
BYPASS CAPACITORS
Rp
Input bypassing using a IIlF tantalum or 251lF electrolytic is
recommended when the input filter capacitors are more than 5
inches from the device. Improved ripple rejection (80dB) can be
accomplished by adding a 1OIlF capacitor from the adjust pin to
ground. Increasing the size of the capacitor to 20llF will help
ripple rejection at low output voltage since the reactance of this
capacitor should be small compared to the voltage setting resistor, R2. For improved AC transient response and to prevent the
possibility of oscillation due to unknown reactive load, a IIlF
capacitor is also recommended althe output. Because oftheir low
impedance at high frequencies, the best type of capacitor to use
is solid tantalum.
4-50
SG338A
PARASITIC
LINE RESISTANCE
Your I,
ADJ.
I
~
.
~
~.~
CONNECT
R, TO CASE
I
FIGURE 18 - CONNECTIONS FOR BEST LOAD REGULATION
SG138AISG138 SERIES
TYPICAL APPLICATIONS
SG338A
l--o"'.OV,l.-o----.-- ~vamps
VOUTI-----.----- 5V
1210
1%
ADJ.
0,0160
3650
1%
1210
'----+--+ ,%
• Needed II device is far from
filter capacitor
··Optional·lmprovestransient
3650
17.
• this circuit will not work
with LM version devices.
response
··CUtl'8ntsharingreslslors
degrade regulatlonto 1%
FIGURE 19· PARALLEL REGULATORS FOR
HIGHER CURRENT
FIGURE 20· 1.2V· 25V ADJUSTABLE REGULATOR
SG338A
VOUT/----.----- 5V
V,N
FIGURE 21 • 5V REGULATOR WITH SHUT DOWN
1SV
SG338A
IN
SG338A
12V
SA
OUTI---t---.,
Y,N
VOUT
1.2K
ADJ.
ADJ .
•
C~
Improves ripple rejection
~
should
be small compared to ~
FIGURE 22 • IMPROVING RIPPLE REJECTION
FIGURE 23· AUTOMATIC LIGHT CONTROL
FIGURE 24· PROTECTED HIGH CURRENT
LAMP DRIVER
SG338A
'5V
VOUTI-----,----,
~-------'''-- ~ 12'1
FIGURE 25 • LAMP FLASHER
FIGURE 26 • REMOTE SENSING
4·51
FIGURE 27· TEMPERATURE COMPENSATED
LEAD ACID BATTERY CHARGER
SG138AISG138 SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
3·PIN METAL CAN
K-PACKAGE
Part No.
Ambient
Temperature Range
SG138AKl883B
SG138AK
SG238AK
SG338AK
SG138K1883B
SG138K
SG238K
SG338K
-55°C to
-55°C to
-25°C to
O°C to
-55°C to
-55°C to
-25°C to
O°C to
150°C
150°C
150°C
125°C
150°C
150°C
150°C
125°C
3-PIN HERMETIC TO-257
G-PACKAGE (non-Isolated)
SG138AG/883B
SG138AG
SG138G/883B
SG138G
-55°C to
-55°C to
-55°C to
-55°C to
150°C
150°C
150°C
150°C
3-PIN HERMETIC TO-257
IG-PACKAGE (Isolated)
SG138AIG/883B
SG138AIG
SG1381G/883B
SG1381G
-55°C to
-55°C to
-55°C to
-55°C to
150°C
150°C
150°C
150°C
Connection Diagram
0
'·0
0
ADJUSTMENT
CASE IS OUTPUT
: 2
0
1
1
1
v"
~ ~~~UST
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4-52
SG140AISG340A
SG140lSG340
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
POSITIVE FIXED VOLTAGE REGULATOR
DESCRIPTION
FEATURES
The SG140A/140 series -of positive regulators offer self contained, fixed-voltage
capability with Up to 1.5A of load current and input voltage up to 50V (SG140A series
only).
• Output voltage set Internally to
±1.5% on SG140A
• Input voltage reange to 50V max. on
SG140A
• Two volt Input-output differential
• Bandgap reference voltage
• Excellent line and load regulation
• Foldback current limiting
• Thermal overload protection
• Voltages available - 5V, 6V, 8V,
12V,15V,18V,24V
These units feature a unique on-chip trimming system to set the output voltages to
within ±1.5% of nominal on the SG140A series, ±2.0% on the SG140 series, and ±4.0%
on the SG340 series. The SG140A versions also offer much improved line and load
regulation characteristics. Utilizing an improved Bandgap reference design, problems
have been eliminated that are normally associated with the Zener Diode references,
such as drift in output voltage and large changes in the line and load regulation.
All protective features ofthermal shutdown, current limiting, and safe-area control have
been designed into these units and since these regulators require only a small output
capacitor for satisfactory performance, ease of application is assured.
HIGH RELIABILITY FEATURES
- SG140Al140
Although designed as fixed-voltage regulators, the output voltage can be increased
through the use of a simple voltage divider. The low quiescent drain current of the
device insures good regulation when this method is used.
• Available to MIL-STD - 883
• Radiation data available
• SG level "5" processing available
Product is available in hermetically sealed TO-220 (both isolated and non-isolated),
TO-3 and TO-66 power packages.
SCHEMATIC DIAGRAM
R18
'---~w-..---~-@2
VOUT
Vos
April 1990
4-53
•
POSITIVE REGULATOR
SG140AISG140 SERIES
ABSOLUTE MAXIMUM RATINGS (Note 1)
Device
Input Voltage
Input Voltage Differential
Output Voltage
Input Voltage
(transient) (Note 3)
(Output shorted to ground)
5V
35V
.50V
35V
35V
50V
35V
6V
av
35V
50V
35V
12V
35V
50V
35V
15V
35V
50V
35V
laV
35V
50V
35V
24V
40V
50V
35V
Operating Junction Temperature
Storage Temperature Range ............................ -65·C to 150·C
Hermetic (K, R, G, IG - Packages) ............................... 150·C
Lead Temperature (Soldering, 10 Seconds) ................... 300·C
Note 1. Values beyond which damage may occur.
THERMAL DERATING CURVES
50~
5.0
4.0
~
~
I
3.0
~
\.
IcRL'NLlJ
~~
i
I
~
"''\;
~~
~o
i
~,,~
""
~.,.~ :'<0
~
1.0
a
~
a
25
30
~~
~ tf-~1%;
is
...
r~
~~
is 2.0
o~~~
~~ ~
. ."
~
o~~
"t>
40
~
50
75
'00
,
'25
'50
~
i
~'~.l~~~
.1".0/",
~~CI
20
~~
I~
•a
175
~
,,~'\,
'0
AMBIENT TEMPERATURE - "C
,J>~
9g", ~.,.-?
25
50
75
'00
MAXIMUM POWER DISSIPATION VB AMBIENT TEMPERATURE
"
'25
CASE TEt.4PERA TURE - "C
'50
175
MAXIMUM POWER DISSIPATION VB CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Operating Junction Temperature Range:
SG140N140 .................................................. -55·C to 150·C
SG340N340 ..................................................... O·C to 125·C
Note 2. Range over which the device is functional.
CHARACTERISTIC CURVES
,
'\ \
I--
2
~
Ii
"
u
P Pkg. Only)
Note 3. Operation at high input voltages is dependent upon load current. When
load current is less than SmA, output will rise out of regulation as inputoiutput differential icreases beyond 30V. Note also from Figure 1, that
maximum load current is reduced at high voltages. The SOV input
rating of the SG140A series refers to ability to withstnd high line or
transient conditions without damage. Since the regulato~s maximum
current capability is reduced, the output may fall out of regulation at
high input voltages under nominal loading.
1
'\ r V'~'\t.
v~
:Y~~d'~d'o
is'o
('
C' '\.
I--
~
5
I(
t.vo=200mV
..... '\
~
iii
G, lG, K. R.
:--
3
1
-'i:"'\. :-..... i\.
0
a
'0
20
30
"
40
50
INPUT-OUTPUT VOLTAGE DIFFERENTIAL - (V)
FIGURE 1.
PEAK OUTPUT CURRENT
vs. INPUT· OUTPUT DIFFERENTIAL
4-54
POSITIVE REGULATOR
SG140AISG140 SERIES
CHARACTERISTIC CURVES (continued)
3
~
r--
I
t!
~>
2
r
<5
~
1
...'I
""" 5G7805/140-5
60
JyV/
,.
0.2
70
///
~
r 7l~
r,.....- "-V
."
, /"
~ 5G7815/140-15
50
40
0
""
~
~
G, IG, K, R, &; P Pkg. Only
6VO=200mV
30
,~
~~ ~~;~i~v +;'V3V
b=IOOmA
5G7824/140-24
TJ .. 2S"C
20
"
10
0
.,"
-0.2
t!
-0.4
§;:
-0.6
~
IL a 1S,\
=>
I"
-0.8
<5
\
1
2
3
10
100
LOAD CURRENT - (A)
1K
10K
lOOK
"1N=15V
VOUT=I~r
-1.0
-75 -50 -25
1M
a
25
50
75 100 125 150
TEMPERATURE-( "c)
FREQUENCY - (Hz)
FIGURE 2.
MINIMUM INPUT • OUTPUT VOLTAGE
VS. LOAD CURRENT
I'i'..
~
~
~
0
0
r--. ~~ t-...
0
\&.
I
z
'L
0
z
'"
FIGURE 4.
TEMPERATURE COEFFICIENT OF OUTPUT VOLTAGE
FIGURE 3.
RIPPLE REJECTION VS. FREQUENCY
APPLICATIONS
INPUT ~
11 SG7800/140 12
O.33~F =F
I
••
I
3
1
~
~ OUTPUT
TO.'~F'
' ' 't
~
• INCREASING VALUE OF OUTPUT CAPACITOR
IMPROVES SYSTEM TRANSIENT RESPONSE
..
1
INPUT
REQUIRED ONLY IF REGULA TOR IS LOCATED
AN APPRECIABLE DISTANCE FROM POWER
SUPPLY FILTER
FIGURE 5 • FIXED OUITPUT REGULATOR
SG7800/140
v1x
r
31
C
\()=Vxx
1
2
~ OUTPUT
Rl
TO.'~F
'Q
(1+ ~~) + bR2
~
R2
"7
FIGURE 6· CIRCUIT FOR INCREASING OUITPUT VOLTAGE
Rsc
INPUT ()
R1
30
~, ~
2N4398
1 SG7805/140
INPUT
2N6124
1 1SG7BOO/140
1
O.33,u F f
l'
12
1
-V OUTPUT
fO. 1/JF
-,!:-
0.33"'
r
3
I
1KO
-=-
FIGURE 7· HIGH OUTPUT CIRRENT, SHORT CIRCUIT PROTECTED
12
r"\
I
~
101"'
10K
FIGURE 8· ADJUTABLE OUITPUT REGULATOR, 7V to 30V
4- 55
OUTPUT
SG140AISG140 SERIES
S.OV POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
SG140A· 5/SG340A· 5
(Unless otherwise specified. these specifications apply over full operating ambient temperatures for SG140A-05 with -55°C ~ T. ~ 150°C. SG340A-05
with O°C ~T. ~ 125°C. and V,N = 10V.10 = 1.0A. C'N = O. 33~F. COUT = 0.1J1F and are applicable for the K. R. G. and IG - Power package - only. Lowduty
cycle pulse testing techniques are used which maintains junction and case temperature equal to the ambient temperature.)
SG140A·5
SG340A·5
. Parameter
Test Conditions
Units
Min. Typ. Max. Min. Typ. Max.
4.9
5.0
Output Voltage
10 = SmA to 1.0A. TJ = 25°C
4.9 5.0 5.1
5.1
V
Line Regulation (Note 1)
VIN = 7.5V to 20V. 10 = 500mA
10
mV
10
VIN = 7.5V to 20V. TJ = 25°C
10
mV
3
10
3
VIN = 7.5V to 20V
12
mV
12
VIN = SV to 12V. TJ .. 25°C
4
mV
4
Load Regulation (Note 1)
25
10 = 5mA to 1.0A
25
mV
10 = 5mA to 1.5A. TJ = 25°C
25
mV
10
25
10
15
10 = 250mA to 750mA. TJ = 25°C
mV
15
Total Output Voltage
VIN = 7.5V to 20V.lo = 5mA to 1.0A. P s15W
4.B
Tolerance
4.S 5.0
5.0
5.2
V
5.2
Over Temperature Range
Quiescent Current
6.5 mA
6.5
TJ = 25°C
mA
6
6
Quiescent Current Change
With Line: VIN = 7.5V to 2SV.lo = SOOmA
O.B rnA
O.S
VIN = 7.SV to 20V. 10 = lA. TJ = 25°C
O.S mA
O.B
With Load: 10 = SmA to 1.0A
0.5
O.S mA
2
Dropout Voltage
eNo = 100mV. 10 = lA. TJ = 25°C
2
2.5
2.5
V
Peak Output Current
TJ = 25°C
2.4
A
2.4
TJ = 25°C
2.1
Short Circuit Current
2.1
A
AV1N .. 10V. f .. 120Hz. TJ = 25°C
68
Ripple Rejection
dB
68
40 Jl.VN
Output Noise Voltage (rms) f = 10Hz to 100KHz (Note 2)
40
1000hrs. at TJ = 12SoC
20
Long Term Stability
20
mV
Thermal Shutdown
175
175
10= 5mA
°C
SG140· 5/SG340· 5
(Unless otherwise specified. these specifications apply over full operating ambient temperatures for SG 140-05 with -55°C ~ T. ~ 150°C. SG340-05 with
O°C ~ T. ~ 125°C. and V,N = 10V. 10 = 500mA. C'N = O. 33~F. COUT = O.I~F and are applicable for the K. R. G. and IG - Power package - only. Low duty
cycle pulse testing techniques are used which maintains junction and case temperature equal to the ambient temperature.)
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
10 = SmA to 1.0A. TJ = 2SoC
VIN = BV to 20V
VIN = 7V to 2SV. TJ = 25°C
VIN = BV to 12V. 10 = 1.0A
VIN = 7.3V to 20V. 10 = 1.0A. TJ = 25°C
10 = 5mA to 1.0A
10 = SmA to 1.5A. TJ = 25°C
10 = 250mA to 750mA. TJ = 25°C
VIN = BV to 20V. 10 = 5mA to 1.0A. P S15W
10= 1.0A
TJ = 25°C
With Line: VIN = 8V to 25V
VIN = SV to 20V. 10 = lA. TJ = 25°C
With Load: 10 " 5mA to 1.0A
AVo = 100mV.lo= lA. TJ = 25°C
TJ =2SoC
TJ = 25°C
AVIN .10V. f = 120Hz. TJ " 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 125°C
In = 5mA
SG140·5
SG340·5
Units
Min. Typ. Max. Min. Typ. Max.
5.0
S.2
V
4.8
4.8 5.0
5.2
50
mV
50
mV
50
50
25
mV
25
SO
mV
50
50
mV
50
50
mV
50
25
25
mV
4.75 5.00
2
2.4
2.1
4.75 5.00
2
2.4
2.1
5.25
8.5
B
1.0
1.0
0.5
2.5
62
68
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4-56
5.25
7
6
O.S
O.B
0.5
2.5
40
20
175
40
20
175
V
mA
mA
mA
mA
mA
V
A
A
dB
Jl.VN
mV
°C
SG140AISG140 SERIES
6.0V & 8.0V POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
SG140 - 6/SG340 - 6
(Untess otherwise specified, these specifications apply over full operating ambient temperatures for SG140-06 with -55°C S; TA S; 150°C, SG340-06 with
O°C S;TAS; 125°C, and V,N = l1V, 10 = 500mA, C'N = O. 3311F, COUT = O.II1F and are applicable for the K, R, G, and IG - Power package - only. Low duty
cycle pulse testing techniques are used which maintains junction and case temperature equal to the ambient temperature.)
SG140 - 6
SG340-6
Parameter
Units
Test Conditions
Min_ Typ. Max. Min. Typ. Max.
Output Voltage
10 = 5mA to I.OA, TJ = 25°C
5.75 6.00 6.25 5.75 6.00 6.25
V
Line Regulation (Note 1)
mV
60
60
V'N = 9Vto 21V
VIN = 8V to 25V, TJ = 25°C
mV
60
60
mV
30
V'N = 9V to 13V,lo= 1.0 A
30
V'N = 8.3V to 21 V, 10= 1.0 A, TJ = 25°C
60
60
mV
Load Regulation (Note 1)
10 = 5mA to 1.0A
60
mV
60
10 = 5mA to 1.5A, TJ = 25°C
mV
60
60
10 = 250m A to 750mA, TJ = 25°C
30
mV
30
Total Output Voltage
V'N = 9V to 21V, 10 = 5mA to 1.0A, P s; 15W
5.7
6.0
6.3
Tolerance
6.0
6.3
V
5.7
Quiescent Current
10= 1.0 A
7
8.5
mA
TJ = 25°C
6
8
mA
Quiescent Current Change
With Line: V'N = 9V to 25V
0.8
1.0
mA
V'N = 9V to 21V, 10 = lA, TJ = 25°C
1.0
mA
0.8
With Load: 10 = 5mA to I.OA
0.5
0.5
mA
Dropout Voltage
tJ.Vo = 100mV, 10 = lA, TJ = 25°C
2
2.5
V
2
2.5
2.4
2.4
A
Peak Output Current
TJ = 25°C
2.1
Short Circuit Current
TJ = 25°C
A
2.1
Ripple Rejection
tJ.V'N = 10V, f = 120Hz, TJ = 25°C
59
dB
65
Output Noise Voltage (rms) f = 10Hz to 100KHz (Note 2)
40 I1VN
40
24
Long Term Stability
1000hrs. at TJ = 125°C
24
mV
175
Thermal Shutdown
10= 5mA
175
°C
SG140 - 8/SG340 - 8
(Unless otherwise specified, these specifications apply over full operating ambient temperatures for SG140-08 with -55°C S; TA S; 150°C, SG340-08 with
O°C S;TAS; 125°C, and V,N = 14V, 10 = 500mA, C'N = .0. 3311F, COUT = O.II1F and are applicable for the K, R, G, and IG - Power package - only. Low duty
cycle pulse testing techniques are used which maintains junction and case temperature equal to the ambient temperature.)
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
10 =5mA to 1.0A, TJ = 25°C
V'N = llV to 23V
V'N = 10.5V to 25V, TJ =25°C
V'N = l1V to 17V, 10 = 1.0A
V'N = 10.5V to 23V, 10 = I.OA, TJ =25°C
10 = 5mA to 1.0A
10 = 5mA to 1.5A, TJ =25°C
10 = 250mA to 750mA, TJ = 25°C
V'N = 11.5V to 23V, 10 = 5mA to 1.0A, P s; 15W
10 = 1.0A
TJ =25°C
With Line: V'N =11.5V to 25V
V'N = 11.5V to 23V, 10 = lA, TJ =25°C
With Load: 10 =5mA to I.OA
tJ.Vo = 100mV, 10 = lA, TJ =25°C
TJ = 25°C
TJ =25°C
tJ.V'N = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. atTJ = 125°C
In =5mA
SG140 - 8
SG340-8
Units
Min. Typ. Max. Min. Typ. Max.
7.7
8.0
7.7. 8.0
8.3
8.3
V
80
mV
80
mV
80
80
40
mV
40
80
mV
80
mV
80
80
80
mV
80
40
mV
40
7.6
2
2.4
2.1
8.4
7
6
0.8
0.8
0.5
2.5
62
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4-57
8.0
7.6
8.0
2
2.4
2.1
8.4
8.5
8
1.0
1.0
0.5
2.5
56
40
40
32
175
32
175
V
mA
mA
mA
mA
mA
V
A
A
dB
I1VN
mV
°C
SG140AISG140 SERIES
12V POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
SG140 A -12/SG~OA -12
(Unless otherwise specified, these specifications apply over full operating ambient temperatures for SG140A -12 with -55°C STA S 150°C, SG340A-12
with O°C ST. S 125°C, and V,N =19V,10 =1.0A, C'N =O. 33I1F, COUT =O.II1F and are applicable for the K, R, G, and IG - Power package - only. Lowduty
cycle pulse testing techniques are used which maintains junction and case temperature equal to the ambient temperature.)
Parameter
Output yoltage
Line ~egulation (Note 1)
"
Load ReQulation (Note 1)
1:otafOutput Voltage.
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
long Term StaDility
.
Thermal Shutdown
Test Conditions
10 =SmA to 1.0A. TJ = 25°C
V'r-! = 14.8Vto 27V.lo =SOOmA
VIN = 14.SV to 27V. TJ = 2SoC
V'r-! = 16V to 22V
VIN= 16Vto 22V. TJ = 25°C
10 =SmA to 1.0A
,10 = SmA to I.SA. TJ = 25°C
10 =250mA to 750mA. TJ =25°C
V,N = 14.8Vto 27V.lo =5mA to 1.0A. P s 15W
Over Temperature Range
TJ =25°C
With Line: V'N = ISV to 30V. 10 = 500mA
V,N = 14.8V to 27V. 10 = lA. TJ =25°C
With Load: 10 = SmA to 1.0A
INo = 100mV. 10 = lA. TJ =25°C
TJ =2SoC
TJ = 25°C
!N'M = 10V. f = 120Hz. TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 12SoC
10 = 5mA
SG140A -12
SG340A-12
Min. Typ. Max. Min. Typ. Max.
11.7S 12.00 12.2S 11.7S 12.00 12.2S
18
18
4
4
18
18
30
30
9
9
60
60
32
32
19
19
11.5 12.0 12.5
6.5
6
0.8
0.8
O.S
2
2.5
2.4
2.1
61
40
48
175
11.5
12.0
2
2.4
2.1
175
V
mV
mV
mV
mV
mV
mV
mV
12.5
6.5
6
0.8
0.8
0.5
2.5
V
mA
mA
mA
mA
mA
V
A
A
dB
40
JlVN
61
48
Units
mV
°C
SG140 -121SG340 -12
(Unless otherwise specified, these specifications apply over full operating ambieni temperatures for SG140-12 with -55°C ST. S 150°C, SG340-12 with
O°C ST. S 125°C, and V,N =19V, 10 =500mA, C'N =O. 3311F, COUT =O.II1F and are applicable for the K, R, G, and IG - Power package - only. Low duty
cycle pulse testing techniques are used which maintains junction and case temperature equal to the ambient temperature.)
SG340 -12
SG140-12
Parameter
Test Conditions
Units
Min. Typ. Max. Min. Typ. Max.
10 .. 5mA to 1.0A. TJ = 25°C
V
Output Voltage
11.5 12.0 12.5 11.5 12.0 12.5
Line Regulation (Note 1)
V,N =15V to 27V
120 mV
120
'120
VIN = 14.SV to 30V. TJ =2SoC
120 mV
V,N = 16V to 22V. 10 = 1.0A
60
mV
60
..
V,N = 14_6V to 27V. 10 = 1.0A. TJ = 2SoC
120 mV
120
120 mV
Load. Reg!llation (Note 1)
10 =5mA to 1.0A
120
10 .. SmA to 1.SA. TJ =2SoC
120 mV
120
10 = 250mA to 750mA, TJ =25°C
60
mV
60
ToI8l Output Voltage
Tolerance
11.4 12.0 12.6 11.4 12.0 12.6
V
V'N = 14.5V to 27V. 10 =5mA to 1.0A. P s 15W
Quiescent Current
10 .. 1.0A
8.S mA
7
8
mA
6
TJ =25~C
Quiescent Current Change
With Line: V,M" 15V to 30V
0.8
1.. 0 mA
1.0 mA
0.8
V,N = 14.5V to 27V. 10 = lA, TJ =.25°C
O.S
O.S mA
.With Load: 10 =SmA to 1.0A
Dropout Voltage
INo = 100mV, 10 = lA, TJ = 25°C
2
2
2.5
V
2.5
TJ =2SoC
2.4
Pe8k Output Current
2.4
A
TJ = 25°C
2.1
Short Circuit Current
2.1
A
Ripple Rejection
AV,M =10V. f .. ,120HZ. TJ .. 25°C
S5
dB
61
Output Noise Voltage (rms) f = 10Hz to 100KHz (Note 2)
40 JlVN
40
1000hrs. at TJ = 125°C
mV
Long Term ,S!8bil,lty
48
48
Thermal Shutdown
175
175
10=5mA
°C
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4 - 58
SG140AISG140 SERIES
15V POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
SG140 A -15/SG340A -15
(Unless otherwise specified, these specifications apply over full operating ambient temperatures for SG140A-15 with -55'C ST, S 150'C, SG340A-15
with O'C ST, S125'C, and Y'N =23V, 10 =1,OA, C'N =O. 33~F, COUT =O.1~F and are applicable for the K, R, G, and IG - Power package - only. Lowduty
cycle pulse testing techniques are used which maintains junction and case temperature equal to the ambient temperature.)
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
10 = 5mA to 1.0A, TJ = 25°C
Y'N = 17.9V to 30V, 10 = 500mA
VIN = 17.5V to 30V, TJ = 25°C
Y'N = 20V to 26V
Y'N = 20V to 26V, TJ = 25°C
10 = 5mA to 1.0A
10 = 5mA to 1.5A, TJ = 25°C
10 = 250mA to 750mA, TJ = 25°C
Y'N = 17.9V to 30V, 10 = 5mA to 1.0A, P s; 15W
Over Temperature Range
TJ = 25°C
With Line: Y'N = 17.9V to 30V, 10 = 500mA
Y'N = 17.9V to 30V, 10 = 1A, TJ = 25'C
With Load: 10 = 5mA to 1.0A
AVo = 100mV, 10 = lA, TJ = 25°C
TJ = 25°C
TJ = 25°C
AV,N = 10V, f = 120Hz, TJ =25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 125°C
10= 5mA
SG140A -15
SG340A-15
Units
Min. Typ. Max. Min. Typ. Max.
V
14.7 15.0 15.3 14.7 15.0 15.3
22
mV
22
22
22
mV
30
mV
30
10
mV
10
75
75
mV
35
mV
35
21
mV
21
14.4 15.0
2
2.4
2.1
15.6
6.5
6
0.8
0.8
0.5
2.5
14.4
15.0
2
2.4
2.1
15.6
6.5
6
0.8
0.8
0.5
2.5
60
60
40
40
60
175
60
175
V
mA
mA
mA
mA
mA
V
A
A
dB
Jl.VN
mV
°C
SG140 - 15/SG340 - 15
(Unless otherwise specified, these speCifications apply over full operating ambienttemperatures for SG140-15 with -55'C ST, S 150'C, SG340-15 with
O'C ST, S 125'C, and Y'N = 23V, 10 = 500mA, C'N = O. 33~F, COUT = O.1~F and are applicable for the K, R, G, and IG - Power package - only. Low duty
cycle pulse testing techniques are used which maintains junction and case temperature equal to the ambient temperature.)
SG140 -15
SG340-15
Parameter
Units
Test Conditions
Min, Typ. Max. Min. Typ. Max.
10 = 5mA to 1.0A, TJ =25°C
Output Voltage
14.4 15.0 15.6 14.4 15.0 15.6
V
Line Regulation (Note 1)
150
150 mV
Y'N = 18.5V to 30V
VIN = 17.5V to 30V, TJ =25°C
150 mV
150
75
mV
Y'N = 20V to 26V, 10 = 1.0A
75
150 mV
VIN = 17.7V to 30V, 10 = 1.0A, TJ =25°C
150
Load Regulation (Note 1)
10 = 5mA to 1.0A
150 mV
150
10 = 5mA to 1.5A, TJ =25°C
150 mV
150
10 = 250mA to 750mA, TJ = 25°C
75
mV
75
Total Output Voltage
Tolerance
Y'N = 17.5V to 30V, 10 = 5mA to 1.0A, P S; 15W
14.25 15.00 15.75 14.25 15.00 15.75 V
10 = 1.0A
8.5
mA
Quiescent Current
7
TJ = 25°C
mA
8
6
Quiescent Current Change
With Line: Y'N = 18.5V to 30V
1.0
mA
0.8
1.0
mA
0.8
Y'N = 18.5V to 30V, 10 = lA, TJ = 25°C
With Load: 10 = 5mA to 1.0A
0.5
mA
0.5
Dropout Voltage
2
2.5
AVo = 100mV, 10 = lA, TJ =25°C
2
V
2.5
TJ = 25°C
Peak Output Current
2.4
A
2.4
Short Circuit Current
2.1
A
TJ =25°C
2.1
AV ,N = 10V, f = 120Hz, TJ = 25°C
54
dB
Ripple Rejection
60
Output Noise Voltage (rms) f = 10Hz to 100KHz (Note 2)
40 Jl.VN
40
Long Term Stability
1000hrs. at TJ = 125°C
60
mV
60
Thermal Shutdown
175
10 = 5mA
175
°C
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4 - 59
SG140AISG140 SERIES
18V& 24V POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note I)
SG140 • 18/SG340 ·18
(Unless otherwise specified, these specifications apply over full operating ambienttemperatures for SGI 40-1 8 with -55°C ~ T. ~ 150°C, SG340-18 with
O°C ~ T.~ 125°C, and V,N = 27V, 10 = 500mA, C'N = O. 3311F, COUT = O.II1F and are applicable for the K, R, G, and IG - Power package - only. Low duty
cycle pulse testing techniques are used which maintains junction and case temperature equal to the ambient temperature.)
SG140 ·18
SG340 ·18
Parameter
Units
Test Conditions
Min. Typ. Max. Min. Typ. Max.
Output Voltage
10 = 5mA to 1,OA, TJ = 25°C
17.3 1,8.0 18.7 17.3 18.0 18.7
V
Line Regulation (Note I)
VIN = 21.5V to 33V
180 mV
180
180 mV
VIN " 21V to 33V, TJ =25°C
180
mV
VIN = 24V to 30V, 10 = 1.0A
90
90
VIN = 21V to 30V, 10 " 1.0A, TJ = 25°C
180 mV
180
Load Regulation (Note I)
10 = 5mA to 1.0A
180 mV
180
to = 5mA to 1.5A, TJ = 25°C
180 mV
180
10 = 250mA to 750mA, TJ = 25°C
mV
90
90
Total Output Voltage
Tolerance
VIN = 21V to 33V, 10 = 5mA to 1.0A, Ps 15W
V
17.1 18.0 18.9 17.1 18.0 18.9
Quiescent Current
8.5 mA
10= lA
7
TJ = 25°C
mA
8
6
Quiescent Current Change
1.0 rnA
With Line: VIN = 21 V to 33V
0.8
1.0 mA
VIN = 21V to 33V, 10 = 1A, TJ ~ 25°C
0.8
With Load: 10 = 5mA to 1.0A
0.5 mA
0.5
Dropout Voltage
!:No = 100mV, 10 = lA, TJ = 2SoC
2
2
2.S
V
2.S
Peak Output Current
TJ =25°C
2.4
2.4
A
Short Circuit Current
TJ = 25°C
2.1
2.1
A
Ripple Rejection
I!!.VIN = 10V, f = 120Hz, TJ = 25·C
53
dB
59
Output Noise Voltage (rms) f = 10Hz to 100KHz (Note 2)
40 I!VN
40
Long Term Stability
1000hrs. at TJ = 125·C
mV
72
72
Thermal Shutdown
·C
175
175
10=5mA
SG140 • 24/SG340· 24
(Unless otherwise specified, these specifications apply over full operating ambienttemperatures for SG140-24 with -55°C ~ T. ~ 150°C, SG340-24 with
O°C ~T.~ 125°C, and V,N = 33V, 10 = 500mA, C'N = O. 3311F, COUT = O.II1F and are applicable for the K, R, G, and IG - Power package - only. Low duty
cycle pulse testing techniques are used which maintains junction and case temperature equal to the ambient temperature.)
Parameter
Output Voltage
Line Regulation (Note I)
Load Regulation (Note I)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
10 = 5mA to 1.0A, TJ = 25·C
VIN = 28V to 38V
VIN = 27V to 38V, TJ = 25·C
VIN = 30V to 36V, 10 = 1.0A
VIN =27.1 V to 35V, 10 = 1.0A, TJ =25·C
10 = SmA to 1.0A
10 = 5mA to I.SA, TJ =25°C
10 = 250mA to 7S0mA, TJ = 2SoC
VIN = 27V to 38V, 10 = SmA to 1.0A, Ps ISW
10= 1,.OA
TJ =2S·C
With Line: VIN = 27V to 38V
VIN = 28V to 38V, 10 = lA, TJ = 25°C
With Load: 10 = SmA to 1.0A
I!!.Vo = 100mV, 10 = lA, TJ = 25°C
TJ = 25°C
TJ = 25°C
I!!.VIN = 10V, f = 120Hz, TJ =25°C
f =10Hz to 100KHz (Note 2)
1000hrs, at TJ = 125°C
10 =5mA
SG140·24
SG340·24
Units
Min. Typ. Max. Min. Typ. Max.
23
25
24
24
23
V
25
240 mV
240
240
240 mV
120 mV
120
240 mV
240
240 mV
240
240 mV
240
120 mV
120
22.8 24.0
2
2.4
2.1
22.8
24.0
2
2.4
2.1
25.2
'8.5
8
1.0
1.0
0.5
2.5
50
56
Note I. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4-60
25.2
7
6
0.8
0.8
O.S
2.5
40
40
96
175
96
175
V
mA
mA
mA
mA
mA
V
A
A
dB
I!VN
mV
·C
SG140A/SG140 SERIES
POSITIVE REGULATOR
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
3-TERMINAL TO-3
METAL CAN
K-PACKAGE
Part No.
Ambient
Temperature Range
SG 140A-XXK/BB3B
SG140A-XXK
SG240A-XXK
SG340A-XXK
SG 140-XXK/BB3B
SG140-XXK
SG240-XXK
SG340-XXK
-55°C to 125°C
-55°C to 125°C
-25°C to B5°e
OOeto 70e
-55°C to 125°C
-55°C to 125°C
-25°C to B5°e
OOeto 70°C
SG140A-XXR/BB3B
SG140A-XXR
SG240A-XXR
SG340A-XXR
SG140-XXR/BB3B
SG140-XXR
SG240-XXR
SG340-XXR
-55°C to 125°C
-55°C to 125°C
-25°C to B5°e
ooe to 70°C
-55°C to 125°C
-55°C to 125°C
-25°C to B5°e
ooe to 70°C
SG140A-XXT/BB3B
SG140A-XXT
SG340A-XXT
SG140-XXT/BB3B
SG140-XXT
SG340-XXT
-55°C to 125°C
-55°C to 125°C
ooe to 70°C
-55°C to 125°C
-55°C to 125°C
ooe to 70°C
3-PIN HERMETIC TO-257
G-PACKAGE (Non-Isolated)
SG140A-XXG/BB3B
SG140A-XXG
SG140-XXG/BB3B
SG140-XXG
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
3-PIN HERMETIC TO-257
IG-PACKAGE (Isolated)
SG140A-XXIG/BB3B
SG140A-XXIG
SG140-XXIG/BB3B
SG140-XXIG
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
3-TERMINAL TO-66
METAL CAN
R-PACKAGE
3-PIN TO-39 METAL CAN
T-PACKAGE
Note 1.
2.
3.
4.
Connection Diagram
v"
~.~
vo",
v"
CD
0
0
2
CASE IS GROUND
Vo",
'.cQ
v",,,
Tab is GND
10I
I
~
Gl
GROUND
:
~~UND
v"
Contact factory for JAN and DESC product availability.
All parts are viewed from the top.
"XX" to be replaced by output voltage of specific fixed regulator.
Some products will be available in leadless chip carrier (LCC) and hermetic flat pack (F). Consult factory for price and availability
Silicon General .
11861 Western Avenue· Garden Grove, CA 92841 • (714) 898-8121 • TWX: 910-596-1804· FAX: (714) 893-2570
4 - 61
4 - 62
SG150AISG250AISG350A
SG150lSG250lSG350
SILI[ON
GENERAL
3 AMP POSITIVE ADJUSTABLE REGULATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG150/150A series are adjustable 3-terminal positive voltage regulators
capable of supplying in excess of 3A over a 1.2V to 33V output range. They are
exceptionally easy to use and require only 2 external resistors to set the output
voltage. The SG1501150A series offers full overload protection available only in
IC's. Included on the chip are current limit, thermal overload protection and safe
operating area protection.
•
•
•
•
•
•
•
•
Since the regulator is '110ating" and sees only the input-to-output differential
voltage, supplies of several hundred volts can be regulated as long as the
maximum input to output differential is not exceeded.
Trimmed ±1% reference voltage
Adjustable output down to 1.2V
Guaranteed 3A output current
Line Regulation typically 0.1 %
Guaranteed thermal regulation
Current limit constant with temperature
86 dB ripple rejection
Standard 3-lead transistor package
HIGH RELIABILITY FEATURES
- SG150A I SG150
Supplies needing electronic shutdown can be achieved by clamping the adjustment terminal to ground, which programs the outputto 1.2V where most loads draw
little current. Reference voltage, which is trimmed to be within ±1% at room
temperature, is guaranteed to be within ±2% over all operating conditions for the
"A" version and ±4% for the standard version. They are packaged in the hermetic
TO-3 and TO-220 (Isolated and Non-Isolated).
• Available to MIL-STD-883 AND DESC
SMD
• SG level .. processing available
s..
PRECISION REGULATOR
SG150/150A
+V,N>----i V,N
,
va
+VaUT
~
ADJ.
R1
2400
VREF
I
--
'ADJ
R2
G N D > - - - - - - - - - - - - - t - - - 7 GND
-~
OUTPUT VOLTAGE ERROR
9
"
'(
0:
0
7
:;]
6
§2
4
~
0-
::0
3
0
2
I"
::0
'" R,J"ok sUJd
2::CREJIST~
II
~
:,..
w
5
II
SG350
0:
'-'
II
2~ REJISTO~S
8
V
SG3 50A
~
1:::: RE STO
SG3 50A
~
1
0
1
2
4
6
10
20
OUTPUT VOLTAGE-(V)
April 1990
4-63
40 60
100
•
SG150AISG150 SERIES
ABSOLUTE MAXIMUM RATINGS (Note I)
Power Dissipation ........................................... Internally Limited
Input-Output Voltage Differential ....................................... 35V
Storage Temperature Range ............................. -65°C to 150°C
Note I. Exceeding these ratings could cause damage to the device.
Operating Juntion Temperature
Hermetic (K, G, IG-Packages) ...................................... 150°C
Lead Temperature (Soldering, 10 Seconds) ................. 300°C
THERMAL DERATING CURVES
50~
5.0
40
~,
e
30
~
~
"~~
"
4"
~
i5
"
Q
~
0'.<:,
?J...
+('1::
~
""1'".C'
>0
0
25
50
75
20
~
(u'~1-
1'J.'-9-1-
+!'1'~
~~
(('-)('
~
'
10
~
125
100
<:'0,:
>o~"", ~
~
~
0
i5
e
~s? ~
1.0
.-~~
,
~('~
"0
40
~
~
+
(J'.
';o~
2.0
~
150
~
0
175
0
25
50
75
100
CASE TEMPERATURE -
AMBIENT TEMPERATURE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
\
125
150
175
'C
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage Range ............................................... 3.0V to 30V
Note 2. Range over which the device is functional.
Operation Junction Temperature Range
SG150Al150 .................................................. -55°C to 150°C
SG250Al250 .................................................. -25°C to 150°C
SG350Al350 ................ ................................ ..... O°C to 125°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SGI 50AlSGI 50 with -55°C S;T. S; 150°C, SG250Al
SG250 with -25°C S; T. S; 150°C, SG350AlSG350 with O°C S; T. S; 125°C and Y'N - VOUT = 5V, and lOUT = 1.5A. Specifications are applicable for power
dissipations up to 30W for the K package. Power dissipation is guaranteed at these values up to 15V input-output differential. Above 15V input-output
differential power dissipation is limited by device internal protections circuitry. Low duty cycle pulse testing techniques are used which maintains junction
and case temperature equal to the ambient temperature.)
Parameter
Reference Voltage
Line Regulation
Load Regulation (Note 3)
ThermarRegulation
I ~~ipple Rejection
Adjust Pin~~urient
Adjust Pin Current Change
Minimum LOad Current
Current Limit
Test Conditions
=
=
lOUT 10mA TJ 25°C
3V::; (VIN - VOUT) ::; 35V, P ::; 30W,
10mA::; lOUT::; 3A
3V::; (V IN - VOUT)::; 35V, IL = 10mA,
TA 25°C
10mA::; lOUT::; 3A
VOUT ::; 5V, TA 25°C
VOUT~ 5V, TA = 25°C
VOUT ::;5V
VOUT~ 5V
TA 25°C, 20ms pulse
VOUT = 10V, f =120Hz
CADJ 0
CADJ = 10~F
=
SG150AlSG250A
SG150
Min. Typ. Max. Min. Typ. Max.
1.238 1.250 1.262
1.225 1.250 1.270 1.20 1.25 1.30
0.02 0.05
0.02 0.05
0.005 O.of
0.005 0,01
=
5
15
0.1
0.3
15
50
0.3
1
0.002 0.01
=
=
10mA::; IL::; 3A, 3V::; (VIN - VOUT)::; 35V
(VIN - VOUT) 35V
(VIN - VOUT)::; 10V
(VIN - VOUT) = 30V
66
=
4-64
65
86
50
0.2
3.5
3
0.3
4.5
1
5
15
0.1
0.3
20
50
0.3
1
0.002 0.01
66
100
5
5
3
0.3
65
86
50
0.2
3.5
4.5
1
100
Units
V
V
%N
%N
mV
%
mV
%
O/O/W
dB
dB
~
5
~A
5
mA
A
A
SG150AISG150 SERIES
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Temperature Stability (Note 4)
Long Term Stability (Note 4)
RMS Output Noise (% of VOUT)
TA = 125°C
TA = 25°C, 10Hz ~f ~ 10KHz
Line Regulation
Load Regulation (Note 3)
SG350A
SG350
Min. Typ. Max. Min. Typ. Max.
1.238 1.250 1.262
Test Conditions
Parameter
Reference Voltage
SG150AlSG250A
SG150
Min. Typ. Max. Min. Ty~ Max.
1
2
1
0.3
0.3
0.001
0.001
Test Conditions
lOUT = 10mA TJ = 25°C
3V ~ (VIN - Vour) ~ 3SV, P ~ 30W,
10mA ~ lour ~ 3A
3V ~ (VIN - Vour) ~ 3SV, IL = 10mA
TA =2SoC
10mA ~ lour ~ 3A
VOUT~SV, TA = 25°C
Vour ';;! SV, TA = 2SoC
1.225 1.250 1.270 1.20 1.25 1.30
0.02 O.OS
0.02 0.07
O.OOS 0.01
O.OOS 0.03
5
15
0.1
0.3
1S
50
0.3
1
0.002 0.01
Vour~SV
Thermal Regulation
Ripple Rejection
Adjust Pin Current
Adjust Pin Current Change
Minimum Load Current
Current Limit
Temperature Stability (Note 4)
Long Term Stability (Note 4)
RMS Output Noise (% of Vour)
Vour ';;! SV
TA = 25°C, 20ms pulse
Vour = 10V, f=120Hz
CAOJ = 0
CAOJ = 1Ol1F
6S
86
50
0.2
3.5
4.5
3
1
0.25
1
0.3
0.001
66
10mA ~ IL~ 3A, 3V ~ (VIN - Vour) ~ 35V
(VIN - Vour) = 35V
(VIN - Vour) ~ 10V
(VIN - Vour) = 30V
TA = 125°C
TA = 25°C, 10Hz ~f ~ 10KHz
S
25
0.1
O.S
20
70
0.3
1.S
0.002 0.03
65
86
50
0.2
3.5
4.5
3
1
0.25
1
0.3
0.001
2
1
%
%
%
Units
V
V
%N
%N
mV
%
mV
%
%/W
dB
dB
66
100
5
10
Units
100
5
10
J.lA
J.lA
mA
A
A
%
%
%
Note 3. Regulation is measured at a constant TA• Changes in output due to heating must be taken into account seperately. Pulse testing with low duty
cycle is used.
Note 4. These parameters, although guaranteed are not tested in production.
APPLICATIONS INFORMATION
GENERAL
The SG 150A develops a 1.25V reference voltage between the
output and the adjustable terminal (see Figure 1). By placing a
resistor, R" between these two terminals, a constant current is
caused to flow through R, and down through R2 to set the overall
output voltage. Normally this current is the specified minimum
load current of SmA or 10mA.
Because IADJ is a very small and constant when compared with the
current through R" it represents a small error and can usually be
ignored. It is easily seen from the equation, that even if the
resistors were of exact value, the accuracy olthe output is limited
by the accuracy of VREF' Earlier adjustable regulators had a
reference tolerance of±4% which is dangerously close to the ±S%
supply tolerance required in many logic and analog systems.
Further, even 1% resistors can drift 0.01%IOC, adding additional
error to the output voltage tolerance.
4 - 65
SG150A
VIN
::!:
ADJ.
I-=-
Lh
IADJ
50 J1.A
VOUT = VREF
(1+
,
OUT 1------.--- VOUT
IN
:~)
~
VREF
R1
R2
-2:+IADJ R2
FIGURE' - BASIC ADJUSTABLE REGULATOR
II
SG150AISG150 SERIES
APPLICATIONS INFORMATION
This is illustrated in Figure 2. If R, were connected to the load, the
effective resistance between the regulator and the load would be:
BYPASS CAPACITORS
Input bypassing using a 1J.lF tantalum or 25J.1F electrolytic is
recommended when the input filter capacitors are more than 5
inches from the device. Improved ripple rejection (SOd B) can be
accomplished by adding a 1OJ.lF capaCitor from the adjust pin to
ground. Increasing the size olthe capacitor to 20J.lFwili help ripple
rejection at low output voltage since the reactance of this capacitor should be small compared to the voltage setting resistor, R2•
For improved AC transient response and to prevenUhe possibility
of oscillation due to unknown reactive load, a 1J.lF capacitor is also
recommended at the output. Because of their low impedance at
high frequencies, the best type of capacitor to use is solid
tantalum.
fR + R \
Rp X \~/' Rp = Parasitic Line Resistance.
1
SG350A
Rp
PARASITIC
LINE RESISTANCE
ADJ.
R2
LOAD REGULATION
.1.,--------2,'
Because the SG150A is a three-terminal device, it is not possible
to provide true remote load sensing. Load regulation will be
limited by the resistance olthe wire connecting the regulatorto the
load. The data sheet specification for load regulation is measured
at the bottom of the package. Negative side sensing is a true
Kelvin connection, with the bottom of the output divider returned
to the negative side of the load. Although it may not be immediately obvious, best load regulation is obtained when the top of the
resistor divider (R2) is connected directly to the case, not the load.
~
CONNECT R2
TO LOAD
FIGURE 2· CONNECTIONS FOR BEST LOAD REGULATION
Connected as shown, Rp is not multiplied by the divider ratio. Rp
is about O.004Q per foot using 16 gauge wire. This translates to
4mV/ft. at a 1A load current, so it is important to keep the positive
lead between regulator and load as short as possible, and use
large wire or PC board traces.
TYPICAL APPLICATIONS
I---~-----{) RETURN
3650
1%
250
RETURN
0--------------------------------------'
FIGURE 5· PARAUEl REGULATORS FOR HIGHER CURRENT
(This circuit will not work with LM version devices.)
FIGURE 6· REMOTE SENSING
4- 66
SG150AISG150 SERIES
TYPICAL APPLICATIONS (continued)
I
SG350A
I VIN
I
VOUT
VOUTI
AOJ
~~O
I
lpF
TCl>
f
VOUr=VREF(1+!if)
+
~ 02
•
lpF
TC3.
R2
C2
10pF
•
GNO
.Ii: 01
GND
i
IAO R2 )
~
• No external capacitors are required with the SG150Al150 but in some
application, performance may be improved with added capacitance as follows:
C1. An input capacitor at O.ll1F will protect against problems when high
impedance is present. The device can be more sensitive to input
impedance when output or adjustment capacitors are used.
C2. Bypassing the adjustmentterminal to ground with a 1Ol1F capacitor will
improve the ripple rejection by about 15dB.
C3. A 111F tantalum capacitors on the output will improve transient response and keep the regulator from ringing due to tight capacitive
loading.
In addition to external capacitors, it is sometimes good practice to add
protection diodes 01 and 02 ifthere is a chance that a capacitor may discharge
through the regulator IC.
Oiode 01 protects against C3 with an input short.
Oiode 02 protects against C2 with an output short.
VREF =1.250 ±O.25V
IADJ '" 50pA
FIGURE 7· BASIC REGULATOR WITH CAPACITORS'
FOR INCREASED PERFORMANCE
•
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
3-TERMINAL TO-3
METAL CAN
K-PACKAGE
Part No.
Ambient
Temperature Range
SG150AKlBB3B
SG150AK
SG250AK
SG350AK
SG150KlBB3B
SG150K
SG250K
SG350K
-55°C to 125°C
-55°C to 125°C
-25°C to B5°C
O°Cto 70C
-55°C to 125°C
-55°C to 125°C
-25°C to B5°C
O°Cto 70°C
3-PIN HERMETIC TO-257
G-PACKAGE (Non-Isolated)
SG150AGlBB3B
SG150AG
SG150G/BB3B
SG150G
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
3-PIN HERMETIC TO-257
IG-PACKAGE (Isolated)
SG150AIG/BB3B
SG150AIG
SG150lG/BB3B
SG150lG
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
Connection Diagram
v"
:
~~UST
Note 1. Contact factory for JAN and OESC product availability.
2. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
4 - 67
4-68
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I
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I
I
SG7231SG723C
SILICON
GENERAL
PRECISION VOLTAGE REGULATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
This monolithic voltage regulator is designed for use with either positive
or negative supplies as a series, shunt, switching, or floating regulator
with currents up to 150mA. Higher current requirements may be
accommodated through the use of external NPN or PNP power
transistors. This device consists of a temperature compensated
reference amplifier, error amplifier, power series pass transistor, current
limit, and remote shutdown circuitry.
•
•
•
•
•
•
•
The SG723 will operate over the full military ambient temperature range
of -55°e to 125°e while the SG723e is designed for commercial
applications of ooe to 70 oe.
HIGH RELIABILITY FEATURES - SG723
•
•
•
•
•
•
Positive or negative supply operation
Series, shunt, switching or floating operation
Low line and load regulation
Output adjustable from 2V to 37V
Output current to 150 mA
Low standby current drain
O.002%/O C average temperature variation
Available to MIL-STD-B83 and DESC SMD
MIL-M38510/10201BHA· JAN 723F
MIL·M38510/10201SIA· JAN 723T
MIL·M3851 011 0201 SCA • JAN723J
Radiation data available
SG level "S" processing available
BLOCK DIAGRAM
Vo
Vz
C.L.
C.S.
+
VOLTAGE
REFERENCE
AMPLIFIER
N.I.
INV
V-
FREQ.
COMP
*
Vc IS INTERNALLY CONNECTED TO VIN FOR T PACKAGE.
April 1990
4-69
•
SG7231SG723C
ABSOLUTE MAXIMUM RATINGS (Note 1)
Pulse (50 ms) Input Voltage from Y'N to V- .......................... 50V
Continuous Input Voltage from Y'N to V- .............................. 40V
Input to Output Voltage Differential................................... 40V
Maximum Output Current ............................................... 150mA
Current from Vz (J-Package only) .................................... 25 mA
Note 1. ' Exceeding these ratings could cause damage to the device.
Current from VRE ................................................................15mA
Operating Junction Temperature
Hermetic (T, J, F, L-Packages) ...................................... 150°C
Storage Temperature Range ............................. -65'C to 150'C
Lead Temperature (Soldering, 10 Seconds) .................... 300'C
THERMAL DERATING CURVES
2,5 r--r----.-----r---.,---.,--~-----,
is
~
~ I::------
E
VOUT= YREF
~
"
"
~
LINE
.--
z
0
l"-
F
~
~
.,.,-
3.0
>0
- 0.1
VIN .. +12V
Vour = +5V
Rsc = 0
tWIN = 3V
1110ur = SOmA
-0.2
z
-
w
~
LINE
IL""O
'"E
+D.1
'"
"'"u
2.0
~
1.0
~
h- "..-
TA"
_~50C
z
F
~50C
-
.....
"'"
VIN .. +12V
1';. -5
TA - J2S 0C
w
";S
,/
~
r--
0
t.VIN '" 3V
AIOUT = 10mA
g
LOAD
~
~
------;
Your ~ +5V
Rsc" O
+10
{\
-
-
V
0
a
10
15
20
25
30
INPUT-OUTPUT DIFFERENTIAL -
35
40
a
-10
10
20
30
INPUT VOLTAGE -
V
FIGURE 4.
REGULATION VS.INPUT.QUTPUTVOLTAGE
REGULATION
FIGURES.
STANDBY CURRENT DRAIN
40
50
10
V
20
TIME -
30
40
ms
FIGURES.
TRANSIENT RESPONSE
APPLICATION INFORMATION
Vc
REGULATED
REGULATED
OUTPUT
VIN
OUTPUT
VREF
N.I.
R,
VR2
RZ
GROUND
GROUND----~~--------------~~
J
VOUT=tREFX R, R2
+R2
FIGURE 8 - BASIC HIGH VOLTAGE REGULATOR
V",,-7VT037V
FIGURE 7 - BASIC LOW VOLTAGE REGULATOR
Vour =2VT07V
4 -71
SG7231SG723C
APPLICATION INFORMATION (continued)
GROUND
VIN
Vc
Your
VIN
Vz
VREF
CL
N.I.
CS
-------,---rVc'""-V;;;;;,
01
2N5001
Rsc
REGULATED
OUTPUT
R,
V-
R2
GROUND
t
+R~
R,
VOUT = VREF x ~
FIGURE 10· NEGATIVE VOLTAGE REGULATOR
FIGURE 9· HIGH CURRENT REGULATOR
EXTERNAL NPN TRANSISTOR I, • 1.0A
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
14-PIN CERAMIC DIP
J- PACKAGE
Part No.
SG723J/883B
SG723J
SG723CJ
Ambient
Temperature Range
Connection Diagram
-55°C to 125°C
-55°C to 125°C
O°Cto 70°C
N.C. [~:::J N.C.
CURRENT LIMIT [ 2
13:::J FREO. COMPENSATION
CURRENT SENSE [ 3
INVERTING INPUT [ 4
NON·INVERTING INPUT [ ,
VREF
[
12:::J V"
" :::J V,
10:::J V""
6
9::J Vz
V·[~:::JN.C.
1O-PIN METAL CAN
T-PACKAGE
SG723T/883B
SG723T
SG723CT
(Notes 3 & 4)
-55°C to 125°C
-55°C to 125°C
O°C to 70°C
CURRENT LIMIT
CD
CURRENT SENSE
INVERTING INPUT
NON·INVERTING
INPUT
@)
®
®
®
VIN
o
V,
0® ®
VREF
FREO. COMPENSATION
®
V""
V·
10-PIN CERAMIC
FLAT PACK
F-PACKAGE
SG723F/883B
SG723F
(No.e3)
-55°C to 125°C
-55°C to 125°C
CURRENT SENSE
INVERTING INPUT
~
c=:::::
NON·INVERTING INPUT =
VREF
1
2
3
r::==
4
V·='
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L-PACKAGE
SG723U883B
SG723L
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
t.
2.
3.
4.
5.
6.
7.
S.
9.
10.
-55°C to 125°C
-55°C to 125°C
FREO. COMP.
CURRENT LIMIT
CURRENT SENSE
N.C.
INVERTING INPUT
N.C.
N.I. INPUT
VREF
N.C.
V·
3 2
10 =
9 =
B
7
CURRENT LIMIT
FREO. COMPo
===:::::J VIN
::=::J Vc
,=Vo",
1 2Q 19
'0"
,
17
7
"
15
,
8
14
9 10 11 12 13
11.
12.
13.
14.
IS.
16.
17.
N.C.
VZ
N.C.
Voor
N.C.
N.C.
N.C.
18. Vc
19. N.C.
20. VIN
Note 3. Vzoutputis not available in T. F-packages.
4. Pin 5 is connected to case.
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
4 -72
SG1501AISG2501AISG3501AISG4501
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
DUAL VOLTAGE TRACKING REGULATOR
DESCRIPTION
FEATURES
This circuit is adual polarity tracking regulator designed to provide
balanced positive and negative output voltages at currents up to
100mA. It is internally set for positive and negative 15 volt outputs
but a single external adjustment can be used to change both
outputs simultaneously from 10 to 23 volts. This device can be
used with input voltages of up to ±35 volts and also has provision
for adjustable current limiting, and utilization at currents in excess
of two amps with the aid of external power transistors. A built-in
sensing circuit monitors junction temperature and shuts down the
regulator above 170°C eliminating the user's need for concern
about power dissipation under short circuit conditions. The
SG1501A will operate over the military ambient temperature
range of -55°C to 125°C, while the SG2501A, SG3501A, and
SG4501 are designed for commercial applications of O°C to 70°C.
o
•
•
•
•
•
•
•
±15V tracking outputs
Output currents to 100mA
Internal thermal shutdown protection
Precision line and load regulation
1% maximum temperature variation
Adjustable current limit
±35V inputs
Output adjustable from ±10V to ±23V
HIGH RELIABILITY FEATURES - SG1501A
~
Available to MIL-STD-SS3
~ SG level "S" processing available
BLOCK DIAGRAM
POSITIVE
OUTPUT
POSITIVE
INPUT
POSITIVE
SENSE
0---.-----,
r - - - - + - - - - - - - + - - { ) POSITIVE
STAB.
f - - - - - - 4 - - - n BALANCE
ADJUST
(not available in T-package)
GND~--~--------------------------~----t---,
-6.2V
+
VOLTAGE
ADJUST
" - - - - - - - - + - - + - - 0 NEGATIVE
STAB.
NEGATIVE o--~---.J
INPUT
NEGATIVE
OUTPUT
NEGATIVE
SENSE
See Application Notes for additional information.
April 1990
4-73
•
SGl50lAISG250lAISG350lAISG4501
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage from V+ to VSG1501A, SG2501A ........................................................ 70V
SG3501A, SG4501 ........................................................... 60V
Maximum Load Current .................................................. 100mA
Note 1. Exceeding these ratings could cause damage to the device.
Operating Junction Temperature
Hermetic (J, T, L - Packages) ....................................... 150°C
Plastic (N - Packages) .................................................. 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
THERMAL DERATING CURVES
2.5
r--r---;---,.--;---r--..,-----,
~
I
3.0
~
~c
2.0
I
'.0 1----1!--+--I--..3jo,~I&---!---1
'75
AI,IBrENT TEMPERATURE -
'C
CASE TEMPERATURE - "C
MAXIMUM POWER OISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage from V+ to VSG1501A, SG2501A ....................................................... 60V
SG3501A, 4501 ............................................................... 50V
Output Current .......................................................... 0 to 50mA
Input - Output Differential (minimum) .................................... 4V
Operating Ambient Temperature Range (TJ)
SG1501A ....................................................... -55°C to 125°C
SG2501A, SG3501A, SG4501 ............................ O°C to 70°C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise stated, these specifications apply for the operating ambient temperature ofTA =25°C, Y'N =±20V, Voor =±15V, IL =0, Asc =on, C, =
C, =O.Ol"F. C, =C, =1.0"F. and VOLTAGE ADJUSTMENT pin open. All specifications apply to both positive and negative sides of the regulator. either
singly or together. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Output Voltage
Input Voltage
Input - Output Differential
Output Voltage Balance
Une Regulation
Load Regulation
OUtput Voltage Range
Input Voltage Range
Ripple Rejeciion
Temperature Stability (Note 3)
Short Circuit Current Umi!
Output Noise Voltage
Positive Standby Current
Negative Standby Current
Long Term Stability
Test Conditions
Rsc = 0, IL = SOmA
VIN = 17V to VMAX '
TA = TMIN to TMAX
IL = OmA to 50mA,
TA = TMIN to TMAX
Voltage adjust circuit
10V Output
f = 120Hz
TA = TMIN to TMAX
Rsc=10n
BW = 100Hz to 10KHz
IL =0
IL = 0
SGl501A12501A
SG3501A
SG4501
Units
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
14.8 15 15.2 14.5 15 15.5 14.25
15.75
V
±35
±30
±30
V
2
2
2
V
50
150
50
300
50
300
mV
4
20
5
30
23
35
10
12
75
0.3
1.0
60
50
2
3
0.1
Note 3. These parameters. although guaranteed. are not tested in production.
4-74
4
5
4
20
5
30
23
30
10
12
75
0.3
60
50
2
3
0.1
1.0
4
20
mV
·5
30
23
30
mV
V
10
12
75
0.3
1.0
60
4
5
50
2
3
0.1
V
dB
4
5
%
rnA
!LV...
rnA
rnA
%/KHr
SG1501AISG2501AISG3501AISG4501
CHARACTERISTIC CURVES
>
I
>
...J
E'
POSITIVE
<:
F
OU~PUT
0:
z
o
i:'
u..
F
<:
t:::J
'"w
'"
;0
...J
t-
3
I':
:::J
~~T~A_~~+~'2~5~OC~~=4~NE~G~A~T'~VE~OU~T~~~"r~'.~.,,~.~
-V
-+-___-l
o
12
NEGATIVE rGULATOR
1----1---+---+---1
o
25
50
LOAD CURRENT -
75
"".,
POSITIVE REGULA TO':"'"
TA == -550C
10 h~"~'::-C-:::-ii~::,20rVO::.:Lc.TS:"""'--+_ _ _
..............:
o
_.~ '"
TA - +2SoC
8
:::J
I':
:::J
TA = 2SoC
Rsc ::: 0
4
15
5
w
§;
5
zW
100
o
25
rnA
75
50
LOAD CURRENT -
FIGURE 1.
LOAD REGULATION
100
rnA
•
FIGURE 2.
REGULATOR DROPOUT VOLTAGE
Ul
W
'"Vi
100
1000
I
tO
CD
<:
80
t-
60
>
E
E
zW
0:
0:
:::J
U
::::::: t"- ........
w
l.>
<:
600
,,--~
"'G~ R~Gu.
~-rOi;>
~
0
>
w
40
Ul
r;-r--... . . .
400
z
'"<:g
'"
'"<:X
'"
800
w
Ul
20
200
.l
:::J
1.
CURRENT LIMIT::: SENSE RVOl TAGE
I
0
0
10
0
15
- 50 - 25
20
INPUT-OUTPUT VOLTAGE DIFFERENTIAL -
I
I
0
25
I SC I
50
75
100 125
JUNCTION TEMPERATURE _DC
V
FIGURE 3.
MAXIMUM CURRENT CAPABILIlY
FIGURE 4.
CURRENT LIMITING CHARACTERISTICS
V'N(+) ~ V'N(-)
4 r-_V~O~U~T_~~±r'~5~V~O~LT~S-1_ _ _
-+___'
<:
<:
41--+-+-+--1-
E
E
-H
t-
t-
Z
W
0:
0:
31---t-+--i7"'-t--+-:,
Z
W
0:
0:
:::J
i3
U
t-
t:::>
:::J
-
Vl
Vi
20
...J
10
Z
'"~x
w
5.0
"~
/
w
'"«
"
I
T
.04
f-
.02
SINGLE EXTERNAL RESIST0'l
:;:
RESISTOR FROM '"
V. ADJ. PIN TO GN
~~~5j. PI~K~O
~
"-
1/
.06
Vl
...J
«
::>
'"J:>-
0
-.02
w
NEG. SENSE
3.0
2.0
-.04
~
V
./
,
..;
,.
~
...-(' ~
SmA OIViDER
= ,;
THERMAL SHIFT
CHANGE IN OUTPUT VOLTAGE
CHANGE IN JUNCTION TEMP
-.06
1.0
B
10
12
14
16
lB
20
22
24
8
0
F
«
:>
w
Cl
-20
10
>
=>
[!:
=>
0
\1.
= ±15
= 100
VOUT
RSC
>
E
POSlllVEIOUlPUT
-10
20
>-
"-
0
0
16
18
~
z
0
F
«
:>
'"Cl
VOLTS
w
IL "" OmA
6VIN = 20 to 23 VOLTS
11
-10
5
120
160
=
RSC "" 100
AI ". 0 to 10 rnA
1\
\...
0
NEG~lIVE
f-
=>
200
II ~
OUllPUT
-5
-10
80
'llME -
240
V
o
40
80
ms
120
TIME -
FIGURES.
LINE TRANSIENT RESPONSE
160
-40
==
c:
I
z
w
-50
u
z
«
~.
w
>>-
«
~y
i'i'.
~
~'"
>-
=>
0..
>-
0.1
=>
0;
0
-70
==.
~
~
lK
10K
INPUT FREQUENCY -
lOOK
.01
100
1M
Y
l~~ ~
w
0..
0..
>-
CL'" 1.0J,lF
1.0
~
./
"'~:
/ i-""
&>
~
0..
;;;
240
FIGURE 10.
LOAD TRANSIENT RESPONSE
ITIII[
0
200
ms
10
«
24
VIN '" ±20 VOLTS
Your
±15 VOLTS
-10
10
>
f=>
0..
NEGAliVE OUlPUT
40
V
-5
0
0
0
F
22
V
.1'
PosmVEI OUlPUT
0
...J
II
0
5
"~
-20
!ll
20
±
10
10
"'"
~
...J
14
FIGURES.
TEMPERATURE COEFFICIENT
OF OUTPUT VOLTAGE
20
z
12
OUTPUT VOLTAGE -
FIGURE 7.
EXTERNAL PARALLEL RESISTOR REQUIRED FOR
VOLTAGES OTHER THAN±15 VOLTS .
>
E
10
± V
OUTPUT VOLTAGE -
lOOK
Hz
II IIIII
1M
SG1501AISG2501AISG3501AISG4501
TYPICAL APPLICATIONS
r--.,-'IM..,---,---+---j---,-- +15V
CJ
.01
IVIN
Out
Sense
Stab I Bol
L___ .PQ.slJ!YE____ J Adj
GROUNO
r----NEGAnvE---l
IVIN
Out
Sense
GND
Volt
Adj
Stob I
~~u~nVE - - - 4 - -2-'N519'-0--+-'0/10.....- - 4 - - - - - - - - - - < - -15V
FIGURE 13· HIGH CURRENT CONFIGURATION. ONE AMP OUTPUT
For full power output, the external transistors must be mounted on adequate heat sinks. Selection of power transistors may be made
on the basis of current and voltage capability with low-frequency devices preferred to minimize the risk of oscillation. In this circuit,
the value of Rsc is selected in order to protect the pass transistors rather than the IC. C1 and C2 are only necessary if high line
impedance is present.
-+__..,
~~~~VE _ _
IV IN
RSC
r'VV\r
E
POSITIVE
is
""'"",;"
F
Iiii;;""",:::"
-
f- ~~
,I
~
0
'1""1
illS
14'/
0.1
"
-70
INPUT FREQUENCY - Hz
± V
FIGURE 4.
STANDBY CURRENT DRAIN
'L - 10mA
CL'" 1 O/-IF
1.0
~
ir
~
25
FIGURE 3.
CURRENT LIMITING CHARACTERISTICS
~
0
0
JUNCTION TEMPERATURE _oC
LOAD CURRENT - mA
FIGURE 2.
REGULATOR DROPOUT VOLTAGE
ro
r-- r-.... .......
-~r--
-50 -25
100
........lise•,0n
lK
I\.
::':
'-'!
j
I
,I.
10K
100K
1M
TEST FREQUENCY - Hz
FIGURES.
RIPPLE REJECTION
FIGURE 6.
OUTPUT IMPEDANCE
TYPICAL APPLICATIONS
POSITIVE
INPUT
POSITIVE
OUTPUT
R3
C3
GND
1.0~F
GROUND
GROUND
-----NffiAn~-----l
CL
SENSE
I
STAB I REF
VOL
ADJ
Rl
C4
R4
1.D~F
R2
NEGATIVE
INPUT
NEGATIVE
OUTPUT
NEGATIVE Vo
~ 6.2(R~tR2).
POSITIVE Vo
~~NEGATIVE
Vo
FIGURE 7· BASIC REGULATOR CIRCUIT
For best temperature performance, the parallel impedance of R1 and R2 should be 6.3K ohm while that of R3 and R4 should be
10K. Increasing the value of C1 and C2 will reduce the frequency response while transient response may be improved by increasing C3 and C4. For very low-noise applications. a 4.71!F capacitorfor CREF may be added. Rsc is selected such that a sense voltage
of 0.6 volts (at TJ = 25°C) is developed at the maximum load current desired.
4 - 81
II
SG15021SG25021SG3502
TYPICAL APPLICATIONS (continued)
POSIllVE
INPUT
I
I
I
!.J....
'1'
GND
I
I
I
GROUND
------NEGAn~-----l
I
I
I
!.J....
CL
SENSE
I
VOL
STAB I REF
ADJ
'1'
NEGATIVE
INPUT
I
I
I
FIGURE 8 - HIGH CURRENT CONFIGURATION
Power transistors should be selected on the basis of current and voltage requirements with low-frequency devices preferred to
minimize the risk of oscillation. Input capacitors (0.1I1F to 1.0I1F) may be required if the circuit is located remote from the power
supply filter. The common-collector configuration here has the advantage of allowing the use of separate collector voltages for the
pass transistors but the common-emitter configuration shown below may also be used. In fact, one configuration on the positive
side and the other on the negative side will allow the use of all NPN or all PNP power transistors.
--r
I
I
GROUND~
I _
I
!.J....
------NEGA~~-----l
..,...
OUT
I
CL SENSE STAB I REF
VOL
ADJ
I
I
I
R2
C1
NE~~~~
_+--_--!,
~~~~~_~_.O~1~_F_ _ _ _~~~~___ ~~~~~
SHORT CIRCUIT CURRENT .,... SENSE VOLTAGE
RSC
.
MAXIMUM LOAD CURRENT
SENSE VOLTAGE+R5(.YQ'
\R61
lit!
RSC
FIGURE 9 - FOLDBACK CURRENT LIMITING
The use of R5 and R6 to provide fold-back current limiting is possible with either common-emitter or common-collector
configurations. The values for R5 and R6 are determined by an iterative solution of the equations shown with the trade-off being
that a greater amount of fold-back requires a larger voltage drop a cross Rsc' Note that in the common-emitter configuration, the
100n base - to emitter resistors must provide a path for the regulator stand-by current and should not be increased in value.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Note Below)
Package
Part No.
14-PIN CERAMIC DIP
J - PACKAGE
14-PIN PLASTIC DIP
N- PACKAGE
..
SG1502J/8838
SG1502J
SG2502J
SG3502J
SG2502N
SG3502N
Ambient
Temperature Range
-55°C to 125°C
-55°C to 125°C
O°C.to 70 0 e
O°Cto 70 0 e
O°C to 70°C
ooe to 70°C
Connection Diagram
GND
BALANCE ADJUST
POSITIVE STAB.
POSITIVE SENSE
+ CURRENT LIMIT
POSITIVE OUTPUT
POSITIVEINPUTV+
[~J VOLTAGE ADJ.
[ 2
[3
[4
[ 5
[ '.
13 ]
12 ]
11 ]
10 ]
9]
REFERENCE BYPASS
NEGATIVE STAB.
NEGATIVE SENSE
- CURRENT LIMIT
NEGATIVE OUTPUT
[~J NEGATIVEINPUTV-
Note 1. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
4-82
SG15241SG25241SG3524
SILI[ON
GENERAL
REGULATING PULSE WIDTH MODULATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
This monolithic integrated circuit contains all the control circuitry for a
regulating power supply inverter or switching regulator. Included in a 16pin dual-in-line package is the voltage reference, error amplifier, oscillator,
pulse width modulator, pulse steering flip-flop, dual alternating output
switches and current limiting and shut-down circuitry. This device can be
used for switching regulators of either polarity, transformer coupled DC to
DC converters, transformerless voltage doublers and polarity converters,
as well as other power applications. The SG1524 is specified for operation
over the full military ambient temperature range of -55°C to +125°C, the
SG2524 for -25°C to +85°C, and the SG3524 is designed for commercial
applications of DOC to +7DoC.
•
•
•
•
•
•
•
•
•
•
•
BV to 40V operation
5V reference
Reference line and load regulation of 0.4%
Reference temperature coefficient < ± 1%
100Hz to 300KHz oscillator range
Excellent external sync capability
Dual 50mA output transistors
Current limit circuitry
Complete PWM power control circuitry
Single ended or push-pull outputs
Total supply current less than 10mA
HIGH RELIABILITY FEATURES - SG1524
•
•
•
•
Available to MIL-STD-883B and DESC SMD
MIL-M-38510/12601BEA - JAN1524J
Radiation data available
SG level "S" processing available
BLOCK DIAGRAM
+5V
+5V
+
INV. INPUT
SENSE
-SENSE
N.!. INPUT
GROUND rl...(SUBSTRATE) \ J ...L
-=-
lk
COMPENSATION
SHUTDOWN
April 1990
See Application Notes for additional information.
4-83
II
SG15241SG25241SG3524
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage (+V IN ) ............................................................ 42V
Collector Voltage ................................................................ 40V
Logic Inputs .......................................................... -0.3V to 5.5V
Current Limit Sense Inputs .................................. -0.3V to 0.3V
Output Current (each transistor) .................................... 100mA
Reference Load Current ..................................................' 50mA
Note 1. Values beyond which damage may occur.
Oscillator Charging Current .............................................. 5mA
Operating Junction Temperature
Hermetic (J, F, L Packages) ........................................ 150°C
Plastic (N, DW Packages) ............................................ 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) .................... 300°C
THERMAL DERATING CURVES
2.5....--....---;---r--,---,-,---,
1.0 I--t---I-'"---"I'"",,,,"""'~M---t---I
175
AMBIENT TEMPERATURE - "C
CASE TEMPERATURE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage (+V IN ) ••••••••••••••••••••••••••••••••••••••••••••••••••• 8V to 40V
Collector Voltage ....................................................... OV to 40V
Error Amp Common Mode Range .......................... 1.8V to 3.4V
Current Limit Sense Common Mode Range ......... -0.3V to 0.3V
Output Current (each transistor) ............................... 0 to 50mA
Reference Load Current ... ........................................ 0 to 20mA
Oscillator Charging Current .................................. 30~ to 2mA
Oscillator Frequency Range ........................... 100Hz to 300KHz
Oscillator Timing Resistor (RT) ••••••••••••••••••••••••• 1.8KO to 100KO
Oscillator Timing Capacitor (CT) •••••••••••••••••••••••••••• 1nF to 1.0!1F
Operating Ambient Temperature Range
SG1524 ......................................................... -55°C to 125°C
SG2524 ........................ ................................... -25°C to 85°C
SG3524 ............................................................... O°C to 700 e
Note 2: Range over which the device is functional and parameter limits are guaranteed.
ELECTRICAL SPECIFICATIONS.
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1524 with -55°e '" T. '" 125°e, SG2524 with
-25°e '" T. '" 85°e, SG3524 with ooe '" T. '" 700 e, and +V'N = 20V. Low duty cycle pulse testing techniques are used which maintains junction and
case temperatures equal to the ambient temperature.)
Parameter
Reference Section (Note 3)
Outpu1 Voltage
Line Regulation
Load Regulation
Temperature Stability (Note 7)
Total OUtpu1 Voltage Range (Note 7)
Short Circuit Current
Test Conditions
SG1524/2524
SG3524
U 't
, Min.' Typ.' Max.' Min. Typ. Max., m s
'.
TJ = 25°C
VIN = 8V to 40V
IL = 0 to.20mA
Over Operating Temperature Range
Over Line, Load and Temperature
V••• = OV
Note 3. IL = OmA
4-84
4.80 5.00 5.20 4.60 5.00 5.40
20
30
50
50
50
50
4.80
5.20 4.60
5.40
25
50 150 25
50 150
V
mV
mV
mV
V
mA
SG15241SG25241SG3524
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Oscillator Section (Note 4)
Initial Accuracy
Test Conditions
SG1524/2524
SG3524
U 't
Typ. Max. I Min. Typ. Max.1 m s
I Min.
TJ = 25°C
36
34
MIN~TJ~ MAX
Voltage Stability
Maximum Frequency
Sawtooth Peak Voltage
Sawtooth Valley Voltage
Clock Amplitude
Clock Pulse Width
Y'N = BV to 40V
RT = 2Kn, CT = 1nF
Y'N = 40V
V ,N = BV
200
3
0.6
3.2
0.3
Error Amplifier Section (Note 5)
Input Offset Voltage
Rs~2Kn
Input Bias Current
Input Offset Current
DC Open Loop Gain
RL 2:1 OMn, T J = 25°C
Output Low Level
V PIN ' - VPIN2 2: 150mV
Output High Level
VPIN' - VPIN' 2:150mV
Common Mode Rejection
VCM = 1.BV to 3.4V
Supply Voltage Rejection
Y'N = BV to 40V
Gain-Bandwidth Product (Note 7)
T =25°C
P.W.M. Comparator (Note 4)
Minimum Duty Cycle
V COMP = 0.5V
Maximum Duty Cycle
Ven",p = 3.6V
Current Limit Amplifier Section (Note 6)
Sense Voltage
T J = 25°C
Input Bias Current
Shutdown Section
Threshold Voltage
T J = 25°C
MIN ~TJ" MAX
Output Section (each transistor)
Collector Leakage Current
VCE =40V
Collector Saturation Voltage
Ic = 50mA
Emitter Output Voltage
IE= 50mA
Collector Voltage Rise Time
Rc= 2Kn
Collector Voltage Fall Time
Rc =2Kn
Power Consumption
Standby Current
V'M =40V
Note 4.
Note 5.
Note 6.
Note 7.
40
0.1
400
1
44
46
1
36
34
200
3
0.6
3.2
0.3
3.B
1.2
1.5
0.5
1
0.1
400
1
0.2
4.2
3.B
0.2
4.2
1
2
45
49
0.5
2
45
49
%
KHz
V
V
V
Ils
3.B
1.2
10
10
2
mV
IlA
IlA
dB
V
V
dB
dB
MHz
190
200
210
200
1BO
0.5
0.2
O.B
1.2
1.B
0.5
0.2
17
0.5
0
%
%
200
220
200
mV
IlA
O.B
1.2
1.B
V
V
50
2
IlA
50
2
V
V
Ils
Ils
17
0.4
0.2
0.4
0.2
7
10
I
7
Fase = 40KHz (RT = 2.9KQ, CT = .01IlF)
VeM = 2.5V
VeM = OV
These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
4 - B5
KHz
KHz
60
0
I
44
46
1
1.5
2
1
5
10
1
72
3.B
70
55
1
40
10
I
mA
•
SG15241SG25241SG3524
APPLICATION NOTES
OSCILLATOR
The oscillator in the SG1524 uses an external resistor RT to
establish a constant charging current into an external capacitor
CT' While this uses more current than a series·connected RC, it
provides a linear ramp voltage at CT which is used as a timedependent reference for the PWM comparator. The charging
current is equal to 3.6V/Rp and should be restricted to between
30~ and 2mA. The equivalent range for RT is 1.8K to lOOK.
Note that for buck regulator topologies, the two outputs can be
wire-ORed for an effective 0-90% duty cycle range. With this
connection, the output frequency is the same as the oscillator
frequency. For push-pull applications, the outputs are used
separately; the flip-flop limits the duty cycle range at each output
to 0-45%, and the effective switching frequency althe transformer
is 1/2 the oscillator frequency.
The range of values for CTalso has limits, as the discharge time
of CTdetermines the pulse width of the oscillator output pulse. The
pulse is used (among other things) as a blanking pulse to both
outputs to insure that there is no possibility of having both outputs
on simultaneously during transitions. This output deadtime relationship is shown in Figure 1. A pulse width below 0.35 microseconds may cause failure of the internal flip-flop to toggle. This
restricts the minimum value of CTto 1OOOpF. (Note: Although the
oscillator output is a convenient oscilloscope sync input, the
probe capacitance will increase the pulse width and decrease the
oscillator frequency slightly.) Obviously, the upper limit to the
pulse width is determined by the modulation range required in the
power supply atthe chosen switching frequency. Practical values
of CTfall between 1OOOpF and O.II1F, although successful 120 Hz
oscillators have been implemented with values up to 511F and a
series surge limit resistor of 100 ohms.
If it is desired to synchronize the SG1524 to an external clock, a
positive pulse may be applied to the clock pin. The oscillator
should be programmed with RT and CTvalues that cause itto freerun at 90% of the external sync frequency. A sync pulse with a
maximum logic 0 of +0.3 volts and a minimum logic 1 of +2.4 volts
applied to Pin 3 will lock the oscillator to the external source. The
minimum sync pulsewidth should be 200 nanoseconds, and the
maximum is determined by the required deadtime. The clock pin
should never be driven more negative than -0.3 volts, nor more
positive than +5.0 volts. The nominal resistance to ground is 3.2K
at the clock pin, ±25% over temperature.
The oscillator frequency is approximately lIRT"CT; where R is in
ohms, C is in microfarads, and the frequency is in Megahertz. For
greater accuracy, the chart in Figure 2 may be used for a wide
range of operating frequencies.
If two or more SG1524s must be synchronized together, program
one master unit with RT and CTfor the desired frequency. Leave
the RT pins on the slaves open, connect the CTpins to the CTof
the master, and connect the clock pins to the clock pin of the
master. Since CTis a high-impedance node, this sync technique
works best when all devices are close together.
100K
f;l
Vl
"I
10~MII~.
SOK
S
Vl
~20K
o
w
::;;
~
2
w
I
I---+-+-+-+-t-H++--+-f-::
w 10K
~
t.s;111!111
"
0.2
.002
.OOS
.01
CT VALUE -
.02
.OS
RI' "',
~q,
=: 5K
'"
'"
'-
'-
2K
'--_-'-_-'--'-.I-!--1..J..J....L._ _-'-_'--J......Jc...J....u..u
.001
~~1~~
1K
SOO
0.1
1K
2K
SK
10K
20K
SOK
100K 200K
OSCILLATOR FREQUENCY - HZ
~F
FIGURE 1 • OUTPUT STAGE DEADTIME VS. C,
FIGURE 2 • OSCILLATOR FREQUENCY VS. R, AND C,
4-86
\.
SOOK
SG15241SG25241SG3524
APPLICATION NOTES (continued)
CURRENT LIMITING
The current limiting circuitry of the SG1524 is shown in Figure 3.
By matching the base-emitter voltages of Q1 and Q2, and assuming a negligible voltage drop across R1:
C.L. Threshold
=VBE(Q1) + I,' R2 - VBE(Q2) =I,' R2
- 200 mV
Although this circuit provides a relatively small threshold with a
negligible temperature coefficient, there are some limitations to its
use because of its simplicity.
The most important of these is the limited common-mode voltage
range: ±0.3 volts around ground. This requires sensing in the
ground or return line of the power supply. Also precautions should
be taken to not turn on the parasitic substrate diode of the
integrated circuit, even under transient conditions. A Schottky
clamp diode at Pin 5 may be required in some configurations to
achieve this.
A second factor to consider is that the response time is relatively
slow. The current limit amplifier is internally compensated by R,
, C,. and Q1, resulting in a roll-off pole at approximately 300 Hz.
A third factor to consider is the bias currentolthe C.L. Sense pins.
A constant current of approximately 150~ flows out of Pin 4, and
a variable current with a range of 0-150IlA flows out of Pin 5. As
a result, the equivalent source impedance seen by the current
sense pins should be less than 50 ohms to keep the threshold
error less than 5%.
Since the gain of this circuit is relatively low (42 dB), there is a
transition region as the current limit amplifier takes over pulse
width control from the error amplifier. For testing purposes,
threshold is defined as the input voltage required to get 25% duty
cycle (+2 volts at the error amplifier output) with the error amplifier
signaling maximum duty cycle.
APPLICA TION NOTE: If the current limit function is not used on
the SG1524, the common-mode voltage range restriction requires both current sense pins to be grounded.
FIGURE 3· CURRENT LIMITING CIRCUITRY OF THE SG'524
In this conventional single-ended regulator circuit, the two outputs
olthe SG1524 are connected in parallel for effective a- 90% dutycycle modulation. The use of an output inductor requires and RC phase compensation network for loop stability.
Push-pull outputs are used in this transformer-coupled DC-DC
regulating converter. Note that the oscillator must be set at twice
the desired output frequency as the SG1524's internal flip-flop
divides the frequency by 2 as it switches the P.W.M. signal from
one outputto the other. Current limiting is done here in the primary
so that the pulse width will be reduced should transformer saturation occur.
4 - 87
II
SG15241SG25241SG3524
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
16-PIN CERAMIC DIP
J- PACKAGE
Part No.
Ambient
Temperature Range
SG1524J/883B
SG1524J
SG2524J
SG3524J
-55°C to
-55°C to
-25°C to
O°C to
16-PIN PLASTIC DIP
N - PACKAGE
SG2524N
SG3524N
-25°C to 85°C
O°C to 70°C
16-PIN NARROW BODY
PLASTIC S.O.I.C.
D- PACKAGE
SG2524D
SG3524D
-25°C to 85°C
O°C to 70°C
Connection Diagram
125°C
125°C
85°C
70°C
INV.INPUT
VREF
N.I.INPUT
+VIN
E,
C,
C,
E,
OSC.OUTPUT
+C.L. SENSE
-C.L. SENSE
R,
C,
SHUTDOWN
COMPENSATION
GROUND
VREF
INV.INPUT
N.I.INPUT
OSC.OUTPUT
+VIN
E,
+C.L. SENSE
·C.L.SENSE
C,
C,
R,
C,
GROUND
16-PIN CERAMIC
FLAT PACK
F-PACKAGE
SG1524F/883B
SG1524F
-55°C to 125°C
-55°C to 125°C
E,
-......,.=-_.::..r-
SHUTDOWN
COMPENSATION
INV. INPUT
VREF
N.!. INPUT
+v~
OSC. OUTPUT
+C.l. SENSE
E,
Co
-C.L.SENSE
C,
~
~
C,
SHUTDOWN
GROUND ~----i-"---_ _-=--~ COMPENSATION
20-PIN CERAMIC
LEAD LESS CHIP CARRIER
L- PACKAGE
SG1524U883B
SG1524L
-55°C to 125°C
-55°C to 125°C
1. N.C.
2. VREF
3. INV. INPUT
4. N.I.INPUT
5. OSC. OUTPUT
6. + C.L. SENSE
7.· C.L. SENSE
8. RT
9. CT
10. GROUND
3
2
,
20 19
'D"
5
6
"
16
7
15
'
14
9
1011
1213
11.COMP
12. SHUTDOWN
13. N.C.
14. EA
15.C...
16. N.C.
17,CB
18. EB
19. N.C.
20. +VIN
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11661 Western Avenue. Garden Grove, CA 92641. (714) 696-6121. TWX: 910-596-1604. FAX: (714) 693-2570
4 - 88
SG1524BISG2524BISG3524B
SILI[ON
GENERAL
REGULATING PULSE WIDTH MODULATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1524B is a pulse width modulator for switching power supplies
which features improved performance over industry standards like the
SG 1524. A direct pin-for-pin replacementforthe earlier device, it combines
advanced processing techniques and circuit design to provide improved
reference accuracy, and extended common mode range at the error
amplifier and current limit inputs. A DC-coupled flip-flop eliminates triggering and glitch problems, and a PWM data latch prevents edge oscillations.
The circuit incorporates true digital shutdown for high speed response,
while an undervoltage lockout circuit prevents spurious outputs when the
supply voltage is too low for stable operation. Full double-pulse suppression logic insures alternating output pulses when the Shutdown pin is used
for pulse-by-pulse current limiting. The SG1524B is specified for operation
over the full military ambient temperature range of -55°C to 125°C. The
SG2524B is characterized for the industrial range of -25°C to 85°C, and the
SG3524B is designed for the commercial range of O°C to 70°C.
•
•
•
•
•
•
•
•
•
•
•
7V to 40V operation
5V reference trimmed to ±1%
100Hz to 400KHz oscillator range
Excellent external sync capability
Dual 1OOmA output transistors
Wide current limit common mode range
DC·coupled toggle flip·flop
PWM data latch
Undervoltage lockout
Full dC!uble-pulse suppression logic
60V output collectors
HIGH RELIABILITY FEATURES
·SG1524B
•
•
•
•
Available to MIL·STD·SS3 and DESC SMD
Scheduled for MIL·M·38510 QPL listing
Radiation data available
SG level "s" processing available
DESCRIPTION
GROUND
0-----+
COLLECTOR A
EMITTER A
COLLECTORB
INVERTING
NON·INVERTING
EMITTERB
+C.LSENSE
-C.L. SENSE
COMPENSATION
SHUTDOWN
April 1990
See Application Notes for additional information.
4-89
•
SG1524BISG2524BISG3524B
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage (+VIN) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 42V
Collector Voltage ................................................................. 60V
Logic Inputs .......................................................... -0.3V to 5.5V
Current Limit Sense Inputs ...................................... -0.3V to VIN
Output Current (each transistor) .................................... 200mA
Reference Load Current :.......:.......................................... 50mA
Note 1. Values beyond which damage may occur.
Oscillator Charging Current ................................................ 5mA
Operating Junction Temperature
Hermetic (J, F, L Packages) ......................................... 150°C
Plastic (N, DW Packages) ............................................ 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) ..................... 300°C
THERMAL DERATING CURVES
2.5
r----.,,----,.---,---r--..,--,.----,
~
~
,
1.5
i!i
Ii
!:i
~
i
1.0
"
I
2.0
i
0.5
0
1.0
0
25
50
75
0
175
AMBIENT TEMPERATURE - "C
0
25
175
CASE TEMPERATURE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage (+VIN) .................................................... 7V to 40V
Collector Voltage ........•...................•........................... OV to 60V
Error Amp Common Mode Range .......................... 2.3V to VREF
Current Limit Sense Common Mode Range ....... OV to VIN -2.5V
Output Current (each transistor) .............................. 0 to 100mA
Reference Load Current ............................................ 0 to 20mA
Oscillator Charging Current ............................... 25!1A to 1.8mA
Oscillator Frequency Range .......................... 100Hz to 400KHz
Oscillator Timing Resistor (RT) ........................... 2KQ to 150KQ
Oscillator Timing Capacitor (CT) •••••••••••••••••••••••••••• 1nF to 0.1 J.lF
Operating Ambient Temperature Range
SG1524B ..•.................................................... -55°C to 125°C
SG2524B ......................................................... -25°C to 85°C
SG3524B ............................................................ O°C to 70°C
Note 2: Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these Sp!lcifications apply over the operating ambienllemperatures for SG1524B with -55'e s T. s 125'e, SG2524B with
-25°C s T. s 05'e, SG3524B with O'C s T. s 70°C, and +V'N = 20V. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
Parameter
Test Conditions
Reference Section (Note 3)
Output.V~ltage
Line Regulation
~~ Ffe"gu!alion: .
Temperature Stability (Note 7)
TJ c 25°C
VIN = 7V to 40V
IL =Oto20mA
Over Operating Temperature Range
OVer Line, Load and Temperature
VREF = OV
Total "Outpu~,(oltage Range
Short Circuit Current
Undervoltage Lockout Section
Threshold Voltage
I
SG1524B/2524B
I Min.J Typ.J Max.
4.95 5.00 5.05 4.90 5.00 5.10
3
20
3 , 30
5
30
5
50
15
15
50
50
4.90
5.10 4.80
5.20
25
50 120 25
50 120
14.3 I 4.5
Note 3. IL = OmA
4 - 90
SG3524B
4.7
Units
Min. Typ. Max.1
I 4.3 I 4.5 I 4.7 I
V
mV
mV
mV
V
mA
V
SG1524BISG2524BISG3524B
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Test Conditions
Oscillator Section (Note 4)
Initial Accuracy
TJ = 25°C
Voltage Stability
V'N = 7V to 40V
Temperature Stability (Note 9)
Over Operating Range
Minimum Frequency
RT = 150Kn, CT= O.lI1F
Maximum Frequency
RT = 2Kn, CT= 470pF
Sawtooth Peak Voltage
V'N = 40V
Sawtooth Valley Voltage
V,N = 7V
Clock Amplitude
Clock Pulse Width
Error Amplifier Section (Note 5)
Input Offset Voltage
Rs S2Kn
Input Bias Current
Input Offset Current
DC Open Loop Gain
RL~10Mn
Output Low Level
ISINK = 100!1A; VpIN1 - VpIN2 ~ 150mV
Output High Level
ISOURCE = IOOI1A; VPIN 2 - VPIN 1 ~ 150mV
Common Mode Rejection
VCM = 2.3V to VREF
Supply Voltage Rejection
V,N = 7V to 40V
Gain-Bandwidth Product (Note 7 )
T = 25°C
P.W.M. Comparator (Note 4)
Minimum Duty Cycle
VCOMP = 0.5V
Maximum Duty Cycle
V~n". = 3.9V
Current Limit Amplifier Section (Note 6)
Sense Voltage
Input Bias Current
Shutdown Input Section
HIGH Input Voltage
HIGH Input Current
VSHUTDOWN = 5.0V
LOW Input Voltage
Output Section (each transistor)
Collector Leakage Current
VcE =60V
Collector Saturation Voltage
Ic = 10mA
Ic= 100mA
Emitter Output Voltage
IE= 10mA
IE= 100mA
Emitter Voltage Rise Time (Note 7) RE = 2Kn, TA = 25°C
Collector Voltage Fall Time
R" = 2Kn, T. = 25°C
Power Consumption
Standby Current
V,. =40V, VRH TOowr.L = 2.0V
Note 4.
Note 5.
Note 6.
Note 7.
SG1524B/2524B
SG3524B
U't
,Min. Typ. Max.' Min. I Typ. Max.' nI s
42
400
0.6
3.0
0.2
60
3.8
70
76
1
45
0.1
1
50
600
3.5
1
4.0
0.5
48
1
2
140
0.5
1
5
5
1
78
0.2
4.2
90
100
2
40
400
3.9
1.2
0.6
3.0
0.2
50
1
2
120
2
1
10
10
1
78
0.2
4.2
90
100
2
60
0.5
3.8
70
76
1
0
45
49
180 200
-3
220
-10
2.0
3.9
1.2
0.5
170 200
-3
0.2
1.0
17.5 19
17
18
0.2
0.1
5
1
0.6
50
0.4
2.0
0.5
0.2
0.1
0.2
1.0
17.5 19
17
18
0.2
0.1
12 ,
I
5
mV
!1A
I1A
dB
V
V
dB
dB
MHz
%
%
230
-10
mV
I1A
1
0.6
V
mA
V
2.0
0.1
KHz
%
%
Hz
KHz
V
V
V
I1S
0
49
45
Fose = 43KHz (RT = 2700n, CT= .OII1F)
VeM = 2.3V to VREF
VeM = OV to 17.5V
These parameters, although guaranteed over the recommended operating conditions, are not tested in production.
4-91
45
0.1
1
50
600
3.5
1
4.0
0.5
50
0.4
2.0
0.5
0.2
!1A
V
V
V
V
I1s
I1S
12 , mA
•
SG1524BISG2524BISG3524B
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
Ambient
Temperature Range
SG1524BJ/883B
SG1524BJ
SG2524BJ
SG3524BJ
·55°e to 125°C
·55°e to 125°C
·25°e to 85°C
ooe to 700 e
16·PIN PLASTIC DIP
N· PACKAGE
SG2524BN
SG3524BN
·25°e to 85°C
ooe to 70°C
16·PIN WIDE BODY
PLASTIC S.O.I.C.
DW·PACKAGE
SG2524BDW
SG3524BDW
·25°e to 85°C
ooe to 70°C
16·PIN CERAMIC DIP
J. PACKAGE
Connection Diagram
v..,
INV.INPUT
N.I.INPUT
OSC.OUTPUT
+C.L.SENSE
·C.l.SENSE
+V.
e.
c,
C,
R,
E,
C,
SHUTDOWN
COMPENSATION
GROUND
vRU
INV.INPUT
N.I.INPUT
OSC. OUTPUT
+C.L. SENSE
.c.L. SENSE
+V.
E,
Ce
C,
R,
E,
C,
SHUTDOWN
"'"-1..L:...._ _~-
GROUND
16·PIN CERAMIC
FLAT PACK
F· PACKAGE
SG1524BF/883B
SG1524BF
·55°e to 125°C
·55°e to 125°e
COMPENSATION
VREF
INV.INPUT
N.I.INPUT
OSC.OUTPUT
+C.L.SENSE
.c.L. SENSE
+VIN
E,
C,
C,
E,
R,
C,
-;-=-__
GROUND _ _
20·PIN CERAMIC
LEADLESS CHIP CARRIER
L· PACKAGE
SG1524BU883B
SG1524BL
·55°e to 125°C
·55°e to 125°C
loN.C.
2. INV. INPUT
3. N.I.INPUT
4. OSC. OUTPUT
5. +C.L. SENSE
S.N.C.
7. .c.L. SENSE
8. R,
9,CT
10. GROUND
~~
'OJ
3
2
1
__
20 19
SHUTDOWN
COMPENSATION
".N.C.
12.COMP
13. SHUTDOWN
.
5
1.1.
17
14. E"
7
15
•
14
15.C"
1S.N.C.
17,CB
18. EB
19,+V1N
9
10 11 12 13
20. VREF
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898·8121 • TWX: 910·596·1804. FAX: (714) 893·2570
4·92
SG1525AISG2525AISG3525A
SG1527AISG2527AISG3527A
SILICON
GENERAL
REGULATING PULSE WIDTH MODULATOR
LINEAR INTEGRATEO CIRCUITS
DESCRIPTION
FEATURES
The SG1525A!1527A series of pulse width modulator integrated circuits are designed to offer improved performance and lower external parts count when used to
implement all types of switching power supplies. The on-chip +5.1 volt reference is
trimmed to ±1% initial accuracy and the input common-mode range of the error
amplifier includes the reference voltage, eliminating external potentiometers and
divider resistors. A Sync input to the oscillator allows multiple units to be slaved
together, or a single unit to be synchronized to an external system clock. A single
resistor between the CT pin and the Discharge pin provides a wide range of deadtime
adjustment. These devices also feature built-in soft-start circuitry with only a timing
capacitor required externally. A Shutdown pin controls both the soft-start circuitry
and the output stages, providing instantaneous turn-off with soft-start recycle for
slow turn-on. These functions are also controlled by an undervoltage lockout which
keeps the outputs off and the soft-start capacitor discharged for input voltages less
than that required for normal operation. Another unique feature of these PWM
circuits is a latch following the comparator. Once a PWM pulse has been terminated
for any reason, the outputs will remain off for the duration of the period. The latch is
reset with each clock pulse. The output stages are totem-pole designs capable of
sourcing or sinking in excess of 200mA. The SG1525A output stage features NOR
logic, giving a LOW output for an OFF state. The SG1527A utilizes OR logic which
results in a HIGH output level when OFF.
•
•
•
•
•
•
•
•
8V to 35V operation
5.1 V reference trimmed to ±1 %
100Hz to 500KHz oscillator range
Separate oscillator sync terminal
Adjustable deadtime control
Internal soft-start
Input undervoltage lockout
Latching P.W.M. to prevent multiple
pulses
• Dual source/sink output drivers
HIGH RELIABILITY FEATURES
- SG1525A, SG1527A
•
•
•
•
•
Available to MIL-STD-883B
MIL-M38510/12602BEA - JAN1525AJ
MIL-M38510/12604BEA - JAN1527AJ
Radiation data available
SG level "s" processing available
BLOCK DIAGRAM
Vc
+VIN
GROUNO
SYNC
RT
CT
OISCHARGE
SG1525A OUTPUT STAGE
COMPENSA1l0N
Vc
INV. INPUT
N.i. INPUT
SOFT-START
SHUTDOWN
5K
5K
SG1527A OUTPUT STAGE
See Application Notes for additional information.
April 1990
4 - 93
SG1525AISG1527A SERIES
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (+V ,N ) .......................................................... 40V
Collector Supply Voltage (Vc) .............................................. 40V
Logic Inputs .......................................................... -0.3V to 5.5V
Analog Inputs .......................................................... -0.3V to V,N
Output Current, Source or Sink ...................................... 500mA
Reference Load Current ................................................... 50mA
Oscillator Charging Current ................................................ 5mA
Operating Junction Temperature Range
Hermetic (J, F, L Packages) ......................................... 150°C
Plastic (N, DW Packages) ........................................... 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) .................... 300°C
Note 1. Values beyond which damage may occur.
THERMAL DERATING CURVES
2.5 , - - , . - - , . - - , . - - , . - - , - - , - - - - ,
~
~
~
~
z
~~
~
~
15
15
j
i
175
175
AMBIENT TEMPERATURE -
·c
CASE TEMPERATURE -
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
·c
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage (+V,N ) .................................................... 8V to 35V
Collector Voltage (Vc) ............................................. 4.5V to 35V
Sink/Source Load Current (steady state) ................ 0 to 100mA
Sink/Source Load Current (peak) ............................ 0 to 400mA
Reference Load Current ............................................ 0 to 20mA
Oscillator Frequency Range .......................... 100Hz to 350KHz
Oscillator Timing Resistor (R T) ••••••••••••••••••••••••••• 2Kn to 150Kn
Deadtime Resistor Range (R D) •••••••••••••••••••••••••••••••• on to 500n
Oscillator Timing Capacitor (CT) ••••••••••••••••••••• 0.0011lF to 0.11lF
Operating Ambient Temperature Range
SG1525A1SG1527 A ...................................... -55°C to 125°C
SG2525A1SG2527A ......................................... -25°C to 85°C
SG3525A1SG3527A ............................................ O°C to 70°C
Note 2: Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1525AJSG1527A with -55°C" TA " 125°C,
SG2525AJSG2527A with -25°C" TA " 85'C, SG3525AJSG3527A with O°C" TA " 70°C, and +V'N = 20V. Low duty cycle pulse testing techniques are
used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Reference Section
Output Voltage
Line Regulation
Load Regulation
Temperature Stability (Note 3)
Total Output Voltage Range (Note 3)
Short Circuit Current
Output Noise Voltage (Note 3)
Long Term Stability (Note 3)
Test Conditions
TJ '" 25°C
V,N '" 8V to 35V
IL = 0 to 20mA
Over Operating Temperature Range
Over Line, Load and Temperature
VREF ", OV, TJ '" 25°C
10Hz ~ f ~ 10KHz, TJ '" 25°C
T '" 125°C
SG1525A12525A
SG3525A
SG1527Al2527 A
SG3527A
Units
I Min. Typ.1 Max. I Min.1 Typ. Max. I
V
5.05 5.10 5.15 5.00 5.10 5.20
mV
10
10
30
30
mV
20
50
20
50
mV
20
50
20
50
V
5.00
5.20 4.95
5.25
rnA
80 100
80 100
40 200
40 200 IlVrms
20
50
20
50 mV/khr
Note 3. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
Note 4. Fosc = 40KHz (1\ = 3.6Kn, Cr = O.Q1!LF, Ro = On)
Note 5. Applies to SG1525AJ2525AJ3525A only, due to polarity of output pulses.
4-94
SG1525AISG1527A SERIES
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Oscillator Section (Note 4)
Initial Accuracy
Voltage Stability
Temperature Stability (Note 3)
Minimum Frequency (Note 3)
Maximum Frequency (Note 3)
Current Mirror
Clock Amplitude
Clock Width
Sync Threshold
Sync Input Current
Error Amplifier Section (Vc" = 5.1 V)
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
Gain-Bandwidth Product (Note 3)
Output Low Level
Output High Level
Common Mode Rejection
Supply Voltage Rejection
P.W.M. Comparator Section
Minimum Duty Cycle
Maximum Duty Cycle
Input Threshold (Note 4)
Test Conditions
SG1525A12525A
SG3525A
SG1527Al2527A
Units
SG3527A
I Min. Typ.IMax.1 Min. Typ. Max. I
37.6
T J = 25°C
V ,N = 8V to 35V
MIN $TJ $ MAX
RT = 150KO, CT = .01 ~F
RT = 2KO, CT = 1nF
IRT= 2mA
350
1.7
3.0
0.3
1.2
T J = 25°C
Sync Voltage = 3.5V
40 42.4 37.6
±0.3 ±1
±3
±6
150
350
2.0 2.2 1.7
3.5
3.0
0.5
1.0 0.3
2.0 2.8 1.2
1.0 2.5
0.5
1
RL ~10MO, T J = 25°C
A., = OdB, TJ = 25°C
60
1
VCM = 1.5V to 5.2V
V ,N = 8V to 35V
3.8
60
50
VCOMP = 0.6V
V COMP = 3.6V
Zero Duty Cycle
Maximum Duty Cycle
5
10
1
75
2
0.2
5.6
75
60
40
±1
±3
2.0
3.5
0.5
2.0
1.0
2
1
60
1
0.5
3.8
60
50
75
2
0.2
5.6
75
60
Input Bias Current
Soft-Start Section
Soft Start Current
VSHUTOOWN = OV
Soft Start Voltage
VSHUTDOWN = 2V
Shutdown Input Current
V~HIJTn()WN = 2.5V
Output Drivers Section (each transistor, V =20V)
Output High Level
ISOURCE = 20mA
ISOURCE = 100mA
Output Low Level
IS INK = 20mA
ISINK = 100mA
Undervoltage Lockout
VCaMP and V ss = High
Collector Leakage (Note 5)
Vc = 35V
Rise Time
CL = 1nF, T J = 25°C
Fall Time
CL = 1nF, T J = 25°C
Shutdown Delay (Note 3)
V~o = 3V, C" = 0, T = 25°C
Total Standby Current
Standby Current
V,N =35V
4 - 95
25
18
17
6
49
0.9
3.3
.05
3.6
2.0
50
0.4
0.4
80
0.6
1.0
45
0.6
19
18
0.2
1.0
7
0.4
2.2
8
100
50
0.2
I
14
25
18
17
200
600
300
0.5
I
20 I
2.2
1.0
2.8
2.5
10
10
1
0.5
0
0
45
0.6
42.4
±2
±6
150
6
49
0.9
3.3
.05
3.6
2.0
50
0.4
0.4
80
0.6
1.0
19
18
0.2
1.0
7
100
50
0.2
14
0.4
2.2
8
200
600
300
0.5
KHz
%
%
Hz
KHz
rnA
V
~s
V
rnA
mV
~A
~
dB
MHz
V
V
dB
dB
%
%
V
V
~
~A
V
rnA
V
V
V
V
V
~A
ns
ns
~s
20 I rnA
SG1525AISG1527A SERIES
OSCILLATOR SECTION
7.4K
2K
RAMP
TO PW'M
14K
a"
0'4
25K
BLANKING
TO OUTPUT
CLOCK
FIGURE 1 • OSCILLATOR SCHEMATIC
200
c
'"
~
~V1
~
500
100
c
I
50
-a
400
S
20
~V1
300
w
200
~
100
~
10
.
""c
'-'
z
i=
dd
1O~~29~
DISCHARGE TIME -
FIGURE 2· OSCILLATOR CHARGE TIME VS. R, AND C,
ms
FIGURE 3· OSCILLATOR DISCHARGE TIME VS. R, AND C,
ERROR AMPLIFIER SECTION
BO
'"
c
I
60
Z
INV.
INPUT
'"
~
'-'
TO PWM
COMPARATOR
N.I.
INPUT
5.BV
300
9
40
w
'-'
20
COMP
;'
§
~
~
g
~
FREQUENCY - H;
FIGURE 4 • ERROR AMPLIFIER
FIGURE 5 • ERROR AMPLIFIER OPEN·LOOP
FREQUENCY RESPONSE
4-96
~
SG1525AISG1527A SERIES
OUTPUT SECTION
VIN = 20'0'
TA.= 25°C
II.
V
~f-~
I'-'~CE
SAT, Vc- VOH
5K
10K
'OK
o
--""
.01
CLOCK
F/F
'Ii' S'NKSr'rL I
,02.03 .05
.1... 1
.10
.2.3
.5
OUTPUT CURRENT, SOURCE OR SINK -
PWM
FIGURE 6 ·OUTPUT CIRCUIT (10 Circuij Shown)
lA
A
FIGURE 7· OUTPUT SATURATION CHARACTERISTICS
•
APPLICATION INFORMATION
+VSUPPLY
+VSUPPLY
II
RETURN
RETURN
0 - - - - - 1 - - - - -.....-
For single-ended supplies, the driver outputs are grounded. The
Vc terminal is switched to ground by the totem-pole source
transistors on alternate oscillator cycles.
In conventional push-pull bipolar designs, forward base drive is
controlled by R, - R3 • Rapid turn-off times for the power devices
are achieved with speed-up capacitors C, and C2 •
+VSUPPLY
+VSUPPLY
c,
II
C2
RETURN ( } - - - + - - - - - - - - - - - + - - - - - '
RETURN
The low source impedance of the output drivers provides rapid
charging of power FET input capacitance while minimizing external components.
Low power transformers can be driven directly by the SG1525A.
Automatic reset occurs during deadtime, when both ends of the
primary winding are switched to ground.
4-97
SG1525AISG1527A SERIES
APPLICATION INFORMATION (continued)
SHUTDOWN OPTIONS
1. Use an external transistor or open-collector comparator to pull
down on the Comp terminal. This will set the PWM latch turning
off both outputs. lithe shutdown signal is momentary, pulse-bypulse protection can be accomplished as the PWM latch will be
reset with each clock pulse.
3. Apply a positive-going signal to the Shutdown terminal. This will
provide most rapid shutdown of the outputs but will not immediately set the PWM latch if there is a Soft-Start capacitor. This
capacitor will discharge but with a current of approximately
twice the charging current.
2. The same results can be accomplished by pulling down on the
Soft-Start terminal with the difference that on this pin, shutdown
will not affect the amplifier compensation network but must
discharge any Soft-Start capacitor.
4. The shutdown terminal can be used to set the PWM latch on a
pulse-by-pulse basis ilthere is no external capacitance on SoftStart terminal. Slow turn-on may still be accomplished by
applying an external capacitor, blocking diode, and charging
resistor to the comp terminal. (See SG1524 Application Note).
SG1525A11527A LAB TEST FIXTURE
r-------------,
1 - - - - - - - - & - - . - - 0 +VIN
JK
o
PIW
5
C
ADJ.
10K
A
I
L
L
A
T
3.6K
o
R
1.5
K
B
I
rtr~D
SOfTSTART
IL
~=
__________
4-98
_ __ J
-=--
SG1525AISG1527A SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
Ambient
Temperature Range
SG1525AJ/883B
SG1525AJ
SG2525AJ
SG3525AJ
SG1527AJ/883B
SG1527AJ
SG2527AJ
SG3527AJ
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
DoC to 70°C
-55°C to 125°C
-55°C to 125°C
-25°C to 85°e
DoC to 70°C
16-PIN PLASTIC DIP
N-PACKAGE
SG2525AN
SG3525AN
SG2527AN
SG3527AN
-25°C to 85°C
DoC to 70 0 e
-25°C to 85°C
DoC to 70°C
16-PIN WIDE BODY
PLASTIC S.O.I.C.
DW-PACKAGE
SG2525ADW
SG3525ADW
SG2527ADW
SG3527ADW
-25°C to
DoC to
-25°C to
DoC to
16-PIN CERAMIC DIP
J-PACKAGE
Connection Diagram
INV.INPUT
N.I.INPUT
SYNC
OSC.OUTPUT
C,
v"'
-tV 1N
OUTPUTB
Vo
GROUND
OUTPUT A
SHUTDOWN
COMPENSATION
R,
DISCHARGE
SOFT-START
85°C
70°C
85°C
70°C
INV.INPUT
N.I.INPUT
SYNC
OSC.OUTPUT
C,
V,,,
+V.
OUTPUTB
Vo
GROUND
OUTPUT A
SHUTDOWN
COMPENSATION
R,
DISCHARGE
SOFT·START
16-PIN CERAMIC
FLAT PACK
F-PACKAGE
20-PIN CERAMIC
LEAD LESS CHIP CARRIER
L-PACKAGE
SG1525AF/883B
SG1525AF
SG1527AF/883B
SG1527AF
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
SG1525AU883B
SG1525AL
SG1527AU883B
SG1527AL
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
INV.INPUT
N.I.INPUT
SYNC
OSC.OUTPUT
C,
R,
DISCHARGE
SOFT-START
v"'
+VIN
OUTPUTB
Vo
GROUND
OUTPUT A
SHUTDOWN
COMPENSATION
3
2
1
20 19
1. N.C.
2. INV. INPUT
3. N.I.INPUT
4. SYNC
5. OSC. OUTPUT
6. N.C.
7,CT
'Dc:
5
17
•
18
7
18
B. R,
•
M
9. DISCHARGE
10. SOFT·START
9
10 11 12 13
11. N.C.
12.COMP
13. SHUTDOWN
14. OUTPUT A
15. GROUND
16. N.C.
17.Vc
lS.0UTPUTB
19,+V1N
20. VREF
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
4 - 99
4 -100
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SG15261SG25261SG3526
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
REGULATING PULSE WIDTH MODULATOR
DESCRIPTION
FEATURES
The SG1526 is a high performance monolithic pulse width modulator
circuit designed for fixed-frequency switching regulators and other power
control applications. Included in an 18-pin dual-in-line package are a
temperature compensated voltage reference, sawtooth oscillator, error
amplifier, pulse width modulator, pulse metering and steering logic, and
two low impedance power drivers. Also included are protective features
such as soft-start and undervoltage lockout, digital current limiting,
double pulse inhibit, a data latch for single pulse metering, adjustable
deadtime, and provision for symmetry correction inputs. For ease of
interface, all digital control ports are TTL and B-series CMOS compatible.
Active LOW logic design allows wired-OR connections for maximum
flexibility. This versatile device can be used to implement single-ended
or push-pull switching regulators of either polarity, both transformerless
and transformer coupled. The SG1526 is characterized for operation
over the full military ambient junction temperature range of -55°C to
+150°C. The SG2526 is characterized for operation from -25°C to
+150°C, and the SG3526 is characterized for operation from O°C to
+125°C.
o
o
o
•
•
•
o
o
o
o
o
o
o
o
8 to 35 volt operation
5V reference trimmed to ±1%
1Hz to 350KHz oscillator range
Dual100mA source/sink outputs
Digital current limiting
Double pulse suppression
Programmable deadtime
Undervoltage lockout
Single pulse metering
Programmable soft-start
Wide current limit common mode range
TTUCMOS compatible logic ports
Symmetry correction capability
Guaranteed 6 unit synchronization
HIGH RELIABILITY FEATURES - SG1526
• Available to MIL-STD-883B and DESC SMD
• Radiation data available
• SG level "S"processlng available
BLOCK DIAGRAM
GROUND
Ro
0----,
RT
OUTPUT A
CT~~_~
CSOFTSTART '-F--c._---'
COMPENSATION 0 - - - - . " , - 4
+ ERROR
-ERROR
OUTPUTB
+c.s.
-c.S.
April 1990
See Application Notes for addition information.
4 -101
•
SG1526/SG2526/SG3526
ABSOLUTE MAXIMUM RATINGS
Input Voltage (V ,N) ............................................................... 40V
Collector Supply Voltage (Vc) ............................................. 40V
Logic Inputs ......................................................... -0.3V to 5.5V
Analog Inputs .. :....................................................... -0.3V to Y'N
Source/Sink Load Current (each output) ........................ 200mA
Reference Load Current ................................................... 50mA
Note I. Exceeding these ratings could cause damage to the device.
Logic Sink Current ............................................................ 15mA
Operating Junction Temperature
Hermetic (J, F, L Packages) ......................................... 150°C
Plastic (N, DW Packages) ............................................ 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
THERMAL DERATING CURVES
•. O.---r----,r----,---,.--,----,..--,
2.' .---.-----,---,.---,.--,----,..--,
is
i
c
2.0
~
1.0 I---+--II---""I.......-+~E"'I.--+---l
°0~--2~.--.~0-~7.-~100-~~~-~,75
m
AMBIENT TEMPERATURE -
·c
CASE TEMPERA1'URE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER OISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage ...................................................•......... 8V to 35V
Collector Supply Voltage ........................................ 4.5V to 35V
Sink/Source Load Current (each output) ................. 0 to 100mA
Reference Load Current ........................................... 0 to 20mA
Oscillator Frequency Range .............................. 1Hz to 350KHz
Oscillator Timing Resistor .................................. 2Kn to 150Kn
Note 2. Range over which the device is functional.
Oscillator Timing Capacitor ..................................... 1nF to 20).lF
Available Deadtime Range at 40KHz ....................... 3% to 50%
Operating Ambient Temperature Range:
SG1526 ......................................................... -55°C to 125°C
SG2526 ......................................•.................... -25°C to 85°C
SG3526 ............................................................... O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SGI526 with -55'e ~ T. ~ 125'e, SG2526 with 25°e ~T. ~ 85°e, SG3526 with Q'e ~ T. ~ lQ'e, and V,N = 15V. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
Parameter
Reference Section (Note 3)
Output Voltage
Line Regulation
Load .Regi.llation
Temperature Stability (Note 9)
Total OutpUt ~oltage Range (Note 9)
Short Circuit Current
Undervoltage Lockout Section
FiE'SET Output Volt,age
RESET Output Voltage
Test Conditions
TJ = 25°C
Y'N = 8to 35V
IL =Oto20mA
Over Operating TJ
Over Recommended Operating Conditions
VRE • = OV
VREF = 3.8V
Vo . . = 4.8V
SG3526
I SG1526/2526 I
I Units
Min. Typ. Max. Min. Typ. Max.
4.95 5.00 5.05 4.90 5.00 5.10
10
10
30
30
10
10
30
50
15 50
15
50
4.90 5.00 5.10 4.85 5.00 5.15
50 125
50 125
2.4
4 -102
0.2
4.8
0.4
2.4
0.2
4.8
0.4
V
mV
mV
mV
V
mA
V
V
SG15261SG25261SG3526
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Test Conditions
Oscillator Section (Note 4)
Initial Accuracy
TJ = 25°C
Voltage Stability
Y'N = 8to 35V
Temperature Stability (Note 9)
Over Operating TJ
Minimum Frequency (Note 9)
RT = 150Kn, CT= 20~F
Maximum Frequency
RT = 2Kn, CT= 1.0nF
Sawtooth Peak Voltage
Y'N = 35V
Sawtooth Valley Voltage
V".• =8V
Error Amplifier Section (Note 5)
Input Offset Voltage
Rs :>2Kn
Input Bias Current
Input Offset Current
DC Open Loop Gain
RL 2: 1OMn, TJ = 25°C
High Output Voltage
VPINt - VPIN2 2: 150mV, ISOURCE = 100~
Low Output Voltage
VPIN2 - VPINt 2: 150mV, ISINK = 1OO~A
Common Mode Rejection
Rs :>2Kn
Supply Voltage Rejection
Y'N = 8V to 35V
PWM Comparator Section (Note 4)
Minimum Duty Cycle
VCOMPENSATION = 0.4V
Maximum Duty Cycle
V
=3.6V
Digital Ports (SYNC, SHUTDOWN, and RESET)
HIGH Output Voltage
ISCURCE = 40~
LOW Output Voltage
'SINK = 3.6mA
HIGH Input Current
V,H = 2.4V
LOW Input Current
V'L = O.4V
Current Limit Comparator Section (Note 6)
Sense Voltage
Rs :> son, TJ = 25°C
Input Bias Current
Soft-Start Section
Error Clamp Voltage
RESET = 0.4V
Cs Charging Current
RESET = 2.4V
Output Drivers (each output) (Note 7)
HIGH Output Voltage
ISCURCE = 20mA
ISOURCE = 100mA
LOW Output Voltage
ISINK =20mA
ISINK = 100mA
Collector Leakage
Vc = 40V
Rise Time
CL = 1000pF
Fall Time
C = 1000pF
Power Consumption Section (Note 8)
Standby Current
SHUTDOWN = 0.4V
Note 3.
Note 4.
Note 5.
Note 6.
I, = OmA
Fosc = 40KHz (RT = 4.12Ka±I%, CT= .01I1F±I%, RD = On)
VCM = 0 to 5.2V
VCM = 0 to 12V
I
SG1526/2526
SG3526
Units
Min. Typ. Max. Min. Typ. Max.
±3
0.5
7
±8
1.0
10
1.0
3.0
1.0
3.5
350
0.5
±3
0.5
5
±8
1.0
10
1.0
3.0
1.0
3.5
350
0.5
5
2
-350 -1000
35 100
72
64
60
3.6 4.2
3.6
0.2 0.4
94
70
70
66
80
66
10
2
-350 -2000
35 200
72
4.2
0.2 0.4
94
80
0
45
2.4
mV
nA
nA
dB
V
V
dB
dB
0
49
45
%
%
49
4
2.4
0.2 0.4
-125 -300
-225 -500
4
0.2 0.4
-125 -300
-225 -500
100
-3
110
-10
100
-3
120
-10
mV
0.1
100
0.4
200
0.1
100
0.4
200
V
~
12.5 13.5
12.5 13.5
12
13
12
13
0.2 0.3
0.2 0.3
2
1.2
2
1.2
50 150
50 150
0.3 0.6
0.3 0.6
0.1 0.2
0.1 0.2
V
V
V
V
~
90
50
I
%
%
%
Hz
KHz
V
V
18
I
30
80
50
I
18
I
30
V
V
~A
~
~
~s
~
I
rnA
Note 7. Vc = 15V
Note 8. Y'N = 35V
Note 9. These parameters, although guaranteed over the recommended operating conditions, are nol tested in production.
4 -103
8G152618G252618G3526
CHARACTERISTIC CURVES
'
T
'0
~ 1>=
mV
SPEC
UMIT
777, ;0
'-'<.C< ~
~P
l
~~
~~
~
J
o
§
10
3
20 30
50
"5
~
IE
U
~
0:
-50450
25
~
70
r-...
60
I'-..
50
30
~
20
10
~o-~
75100125150
FIGURE 1.
REFERENCE VOLTAGE VS. SUPPLY VOLTAGE
FIGURE 2.
REFERENCE TEMPERATURE STABILITY
~
"~
0
255075100125150
JUNCTION TEMPERATURE _(Oe)
JUNCTION TEMPERATURE-(Oe)
SUPPLY VOLTAGE -(v)
-
I-
40
~
~
100
90
80
FIGURE 3.
REFERENCE SHORT CIRCUIT CURRENT
11
I
z
80
60
~
'w"
40
~
20
0:
"15
"'
">15"::>
:I:
.........
1'\
~~'b~~~~:o'~:tK
~
E
i-"""
-2
/
-4
.... ~
1/
V
f'fosc-. IKH'
./
FOSe=40KHz
Rr .. 412KO, CT'" OJ¢", RO on
0:
~
V
-
z
0
"'~
10
-6
V"
(cr-. 01
)
V
s:
0
o
-50 -25
RIPPLE FREQUENCY-(Hz)
FIGURE 4.
REFERENCE RIPPLE REJECTION
'C
i:
20
a
25
50
75 100 125 150
o
2
4
6
FIGURE 5.
OSCILLATOR FREQUENCY TEMPERATURE
STABILITY
8
10 12 14 16 18 20 22
Ro-(O)
JUNCTION TEMPERA TURE-(OC)
FIGURE 6.
OUTPUT DRIVER DEADTIME VS. Ro VALUE
~-1----if-1.f-j~~~.I~7f~~--7f~~--7f-,~~~-,~-,~~~--~-1---t---i
0:
21'
51'
101' 201'
501' 1001' 2001'
5001' 1m
2m
5m
10m 20m 50m
OSCILLATOR PERIOD-Cs)
FIGURE 7.
OSCILLATOR PERIOD VS.
R,- AND CT
4 -104
100m 200m 500m
1
SG1526/SG2526/SG3526
CHARACTERISTIC CURVES (continued)
1 SEC
I' "'
>
n.
4 ~
4 ~~~
1.2
1.0
0.2
~;!
V
50
w
::;
i=
\
1.4
$'
:::'
FIGURE 9.
ERROR AMPLIFIER OPEN LOOP GAIN
VS. FREQUENCY
3
140
~
FREQUENCY-(Hz)
FIGURES.
UNDERVOLTAGE LOCKOUT CHARACTERISTIC
100
100
::;
,
10
60
x
"'
"I"-
~
lO~O~P~
20
REFERENCE VOLTAGE-(V)
20
~
200
is
'-'
;!
~" '=
500
0
z
10
_. .. -
r
~
~
0.5
J
o
1
10
20
50
100
200
10
20
30
40
+Vc SINK CURRENT-(mA)
FIGURE 15.
OUTPUT SUPPLY SATURATION VOLTAGE VS.IS'NK
4 -105
FIGURE 16.
STANDBY CURRENT VS. SUPPLY VOLTAGE
50
SG1526/SG2526/SG3526
APPLICATION INFORMATION
VOLTAGE REFERENCE
The reference regulator of the SG1526 is based on a temperature compensated
zener diode. The circuitry is fully active at supply voltages above +8 volts., and provides up to 20mA of load current to external circuitry at +5.0 volts. In systems
where additional current is required, an external PNP transistor can be used to
boost the available current. Arugged low frequency audio-type transistor should
be used, 'and lead lengths between the PWM and transistor should be as short as
possible to minimize the risk of oscillations. Even so, some types of transistors
may require collector-base capacitance for stability. Up to 1amp of load current
can be obtained with excellent regulation if the device selected maintains high
current gain.
VREF
GND
-------->---~
FIGURE 17,
EXTENDING REFERENCE OUTPUT CURRENT
UNDERVOLTAGELOCKOUT
The undervoltage lockout circuit protects the SG1526 and the power devices it controls from inadequate supply voltage. If +VIN
is too low, the circuit disables the output drivers and holds the RESET pin LOW. This prevents spurious output pulses while
the control circuitry is stabilizing, and holds the soft-start timing capacitor in a discharged state.
The circuit consists of a + 1.2 volt bandgap reference and comparator circuit which
is active when the reference voltage has risen to 3VBE,or 1.8 volts at 25°C. When
. the reference voltage rises to approximately +4.4 volts, the circuit enables the
output drivers and releases the RESET pin, allowing a normal soft-start. The comparator has 200mVof hysteresis to minimize oscillation althe trip point. When +VIN
to the PWM is removed and the reference drops to +4.2 volts, the undervoltage
circuit pulls RESET LOW again. The soft-start capacitor is immediately discharged, and the PWM is ready for another soft-start cycle.
The SG1526 can operate from a +5 volt supply by connecting the VREF pin to the
+VIN pin and maintaining the supply between +4.8 and +5.2 volts.
TO RESET
TO DRIVER A
TO DRIVER B
FIGURE lB,
SIMPLIFIED UNDERVOLTAGE LOCKOUT
SOFT·START CIRCUIT
The soft-start circuit protects the power transistors and rectifier diodes from high
current surges during power supply turn-on. When supply voltage is first applied
to the SG1526, the undervoltage lockout circuit holds RESET LOW with 03. 01
is turned on, which holds the soft-start capacitor voltage at zero. The second
collector of 01 clamps the output error amplifier to ground, guaranteeing zero duty
cycle at the driver outputs. When the supply voltage reaches normal operating
range, RESET will go HIGH. 01 turns off, allowing the internall00~A current
source to charge Cs' 02 clamps the error amplifier output'to 1VBE above the
voltage on Cs' As the soft-start voltage ramps up to +5 volts, the duty cycle of the
PWM linearly increases to whatever value the voltage regulation loop requires for
an error null. Figure 10 gives the timing relationship between Cs and ramp time
to 100% duty cycle.
FIGURE 19,
SOFT·START CIRCUIT SCHEMATIC
DIGITAL CONTROL PORTS
The three digital control ports of the SG1526 are bi-directional. Each pin can drive
TTL and 5 volt CMOS logic directly, up to a fan-out of 10 low-power Schottky gates.
Each pin can also be directly driven by open-collector voltage cpmparators; fanin is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin
is pulled LOW to activate the particular function. Driving SYNC LOW initiates a
discharge cycle in the oscillator. Pulling SHUTDOWN LOW immediately inhibits
all PWM output pulses. Holding RESET LOW discharges the soft-start capacitor.
The logic threshold is +1.1 volts at 25°C. Noise immunity can be gained at the
expense of fan-out with an external 2K pullup resistor to +5 volts.
40K
20K
TO
INTERNAL
LOGIC
FIGURE 20,
DIGITAL CONTROL PORT SCHEMATIC
4-106
SYNC
SHUTDOWN
OR RESET
SG15261SG25261SG3526
APPLICATION INFORMATION (continued)
OSCILLATOR
FIGURE 21 - OSCILLATOR CONNECTIONS AND WAVEFORMS
The oscillator is programmed for frequency and deadtime with three components: RT' CT, and RD- Two waveforms are
generated: a sawtooth waveform at pin 10 for pulse width modulation, and a logic clock at pin 12_ The following procedure is
recommended for choosing timing values:
1_ With RD = on (pin 11 shorted to ground) select values for RT and Cr from Figure 7 to give the desired oscillator period_
Remember that the frequency at each driver output is half the oscillator frequency, and the frequency at the +Vc terminal
is the same as the oscillator frequency_
2_ If more dead time is required, select a larger value of RD using Figure 6 as a guide_ At 40kHz dead time increases by
400nSeC/ohm_
3_ Increasing the dead time will cause the oscillator frequency to decrease slightly_ Go back and decrease the value of Rr
slightly to bring the frequency back to the nominal design value_
The SG1526 can be synchronized to an external logic clock by programming the oscillator to free-run at a frequency 10% slower
than the sync frequency_ A periodic LOW logic pulse approximately 0_5~Sec wide at the SYNC pin will then lock the osciliator
to the external frequency_
Multiple devices can be synchronized together by programming one master unit for the desired frequency, and then sharing
its sawtooth and clock waveforms with the slave units_ All CTterminals are connected to the CTpin of the master, and all SYNC
terminals are likewise connected to the SYNC pin of the master_ Slave RT terminals should not be left open nor should they
be tied to the +5V reference; at least 50K should be connected to each pin_ Slave RD terminals may be either left open or
grounded_
ERROR AMPLIFIER
VREF -w.--+-{
"--..w.......-
POSITIVE
OUTPUT
VOLTAGE
GND
GND
VOUT
~
VREF
(R~~Rz)
R _ ( R1R2 )
3- Rl+R2
FIGURE22B
FIGURE22A
ERROR AMPLIFIER CONNECTIONS
The error amplifier is a transconductance design, with an output impedance of 2 megohms and an effective output capacitance
of 100 pF_ Since all voltage gain takes place althe output pin, the open-loop gain can be shaped with shunt reactance to ground_
For unity gain stability the amplifier requires an additional external 100 pF to ground, resulting in an open-loop pole at 400 Hz_
The input connections to the error amplifier are determined by the polarity of the switching supply output voltage_ For positive
supplies, the common-mode voltage is +5_0 volts and the feedback connections in Figure 22A are used_ With negative
supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the +5_0
volt reference voltage, as shown in Figure 229_
4-107
SG15261SG25261SG3526
APPLICATION INFORMATION (continued)
OUTPUT DRIVERS
The totem-pole output drivers of the SG1526 are designed to source and sink 1OOmA continuously and 200mA peak. Loads
can be driven either from the output pins 13 and 16, or from the +VC pin, as required. Curves for the saturation voltage atthese
outputs as a function of load current are found in Figures 14 and 15.
Since the bottom transistor ofthe totem-pole is allowed to saturate, there is a momentary conduction path from the +Vc terminal
to ground during switching. To limit the resulting current spikes a small resistor in series with pin 14 is always recommended.
The resistor value is determined by the driver supply voltage, and should be chosen for 200mA peak currents, as shown in
Figure 25.
+V SUPPLY
0---;--------,
+15V O-~p--------,
+V SUPPLY
CI
15
RETURN
RETURN
RETURN 0------<-----<-
FIGURE 24.
SINGLE·ENOED CONFIGURATION
FIGURE 23.
PUSH·PULL CONFIGURATION
FIGURE 25.
DRIVING N·CHANNEL POWER MOSFETS
SG1526 LAB TEST FIXTURE
-15V
GND
+15V
+15V
~
~
COMMON MODE
-lVOLTAGE SELECT
33K
Jl
10K
EXTERNAL
SYNC
7500
~--''''''''''''-
TO -ERROR
10K±O.lX
+'eTEST
L---;-aJlMr-- TO
+ERROR
10K±O.'"
4 -108
C.S.
TO
TO
Xl0
+C.S.
-C.S.
C~Tti1JO!1
SENSE
SWEEP
~ '~0!1
100
SG15261SG25261SG3526
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
18-PIN CERAMIC DIP
J-PACKAGE
Part No.
SG1526J/883B
SG1526J
SG2526J
SG3526J
Ambient
Temperature Range
-55°G
-55°e
-25°G
OOG
to 125°G
to 125°e
to 85°e
to 70 0 e
18-PIN PLASTIC DIP
N- PACKAGE
SG2526N
SG3526N
-25°e
OOG
to 85°G
to 70 0 e
18-PIN WIDE BODY
PLASTIC S.O.l.C.
OW-PACKAGE
SG2526DW
SG3526DW
-25°e
OOG
to 85°G
to 70 0 e
Connection Diagram
v,,,
+ERROR [~P
• ERROR [2
17p +VIJj
COMPENSATION [3
16
OUTPUT B
CSOFTSTAJIT [ 4
15
GROUND
RESET [5
• CURRENT SENSE [ .
+ERROR IT
·ERROR IT
COMPENSATION IT
R,IT
to 125°e
to 125°e
18
2
17~ +VIN
,. ~ OUTPUTB
15 ~ GROUND
3
•
•
•
~ SYNC
11~
9
10
2
c::::==
-C.S.
c::::==
c::::==
c::::==
RDEADTIME
I:D c,
+C.S.
c::::==
1
24 23
21 ~ +V/N
22 20 ~ OUTPUT B
19~ GROUND
8 10
15 17 ~ OUTPUT A
6
18~
7
c::::== •
6. RESET
7.-C.S.
8.+C.S.
9. SHUTDOWN
10. R,
3
2
1
20 19
4C~
•
•
1.
17
1.
7
I.
14
10 11 12 13
SYNC
11.Cy
12. RoeADTlME
9
9
+VCOU£CTOR
N.C.
IIII
R,
5,CSOFTSTART
1. ~
11121314
SHUTDOWN
1.N.C.
2.+ERROR
3.-ERROR
4.COMP
N.C.
3
4
5
~
-55°e to 125°e
-55°e to 125°G
VR£F
14~ +VCOlLECTOR
13 ~ OUTPUT A
12
7
N.C.
N.C.
SG1526U883B
SG1526L
FIJ
1
~~::g: ~~~~~~~J.=;=Ll]llLU~u~~~~
~:~.
~_
CQMP
CSOfTST"RT
RESET
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L- PACKAGE
RDEADTIME
0: 4
SHUTDOWN IT
-55°e
-55°e
12
R, [~P C,
CSCFTSTART
SG1526F/883B
SG1526F
VCO\..LECTOR
13
+CURRENT SENSE [ 7
SHUTDOWN [8
RESET IT
- CURRENT SENSE IT
,CURRENT SENSE IT
24-PIN CERAMIC
FLAT PACK
F-PACKAGE
P
P
14 P
P OUTPUT A
P SYNC
11 P
13. SYNC
14. OUTPUT A
15. N.C.
16.+VCOLlECTOIl
17. GROUND
18.0UTPUTB
19. +VIN
20. VReF
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121' TWX: 910-596-1804. FAX: (714) 893-2570
4 -109
4 - 110
SG1526BISG2526BISG3526B
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
REGULATING PULSE WIDTH MODULATOR
DESCRIPTION
FEATURES
The SG1526B is a high-performance pulse width modulator for switching
power supplies which offers improved functional and electrical characteristics over the industry-standard SG1526. A direct pin-for-pin replacement for
the earlier device with all its features, it incorporates the following enhancements: a bandgap reference circuit for improved regulation and drift characteristics, improved undervoltage lockout, lower temperature coefficients on
oscillator frequency and current-sense threshold, tighter tolerance on
softstart time, much faster SHUTDOWN response, improved double-pulse
supperessiDn logic for higher speed operation, and an improved output
driver design with low shoot-through current, and faster rise and fall times.
This versatile device can be used to implement single-ended or push-pull
switching regulators of either polarity, both transformer-less and transformer-coupled. The SG1526B is specified for operation overthe full military
ambient temperature range of -55°C to 150°C. The SG2526B is characterized forthe industrial range of -25°C to 150°C, and the SG3526B is designed
for the commercial range of O°C to 125°C.
o 8 to 35 volt operation
• 5V low drift 1% bandgap reference
o 1 Hz to 500KHz oscillator range
• Dual100mA source/sink
o Digital current limiting
• Double pulse suppression
• Programmable deadtlme
• Improved undervoltage lockout
• Single pulse metering
o Programmable soft-start
o Wide current limit common mode range
o TTWCMOS compatible logic ports
o Symmetry correction capability
o Guaranteed 6 unit synchronization
• Shoot thru currents less than 100mA
o Improved shutdown delay
o Improved rise and fall time
HIGH RELIABILITY FEATURES - SG1526B
•
•
•
•
Available to MIL-STD-883
MIL-M38510/12603BVA - JAN1526BJ
Radiation data available
SG level "S" processing available
BLOCK DIAGRAM
GROUND
RD
RT
o---==:r---'
9----:;:::=l----,
OUTPUT A
cT
CSOFTSTART
COMPENSATION
0---...,...--+
+ ERROR
-ERROR
OUTPUTB
+c.s.
-c.s.
Aprtl1990
4 -111
SG1526BISG2526BISG3526B
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage (V ,N ) ............................................................... 40V
Collector Supply Voltage (Vc) ............................................. 40V
Logic Inputs ......................................................... -0.3V to 5.5V
Analog Inputs .......................................................... -0.3V to V,N
Source/Sink Load Current (each output) ....................... 200mA
Reference Load Current ................................................... 50mA
Logic Sink Current .............................................................15mA
Operating Junction Temperature
Hermetic (J, F, L Packages) ......................................... 150°C
Plastic (N, OW Packages) ............................................ 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL DERATING CURVES
2.5....--,.--r---r---,----,.--,.----,
5.0.---..---r---,----..--,.---,..--,
1.0 I---I----l-~""""-f~"""--+--I
°0~-2~5-~50-~75--,~OO-~~3L-~,~
175
AMBIENT TEMPERATURE - "C
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage ............................................................. 8V to 35V
Collector Supply Voltage ........................................ 4.5V to 35V
Sink/Source Load Current (each output) ................. 0 to 100mA
Reference Load Current ............................................ 0 to 20mA
Oscillator Frequency Range .............................. 1Hz to 500KHz
Oscillator Timing Resistor .................................. 2Kn to 150Kn
Note 2. Range over which the device is functional.
Oscillator Timing Capacitor ................................ 470pF to 20llF
Available Deadtime Range at 40KHz ....................... 5% to 50%
Operating Junction Temperature Range:
SG1526B ....................................................... -55°C to 125°C
SG2526B ......................................................... -25°C to 85°C
SG3526B ............................................................ O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these speCifications apply over the operating ambienttemperatures for SG1526B with -55°C,,; T. ,; 125°C, SG2526B with
-25°C,; T.,; 85°C, SG3526B with ooe ,,; T. ,; 70°C, and V,N = 15V. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
Parameter
Reference Section (Note 3)
Output VoHage
Line Regulation
Load Regulation
Temperature Stability (Note 9)
Total Output Voltage Range (Note 9)
Short Circuit Current
Undervoltalle Lockout Section
RESET'Output Voltage
RESET Output Voltage
Test Conditions
TJ =25°C
V,N = 8to 35V
IL =Oto20mA
Over Operating TJ
I SG1526B/2526B
SG3526B
I Units
Typ. t Max. Min. Typ. Max.1
I Min.
4.95 5.00 5.05 4.90 5.00 5.10
10
7
10
20
10
10 25
20
15
15
50
50
4.90 5.00 5.10 4.85 5.00 5.15
25
50 125 25
50 125
VREF = OV
VREI'=3.8V
VR . . = 4.8V
2.4
4-112
0.2
4.8
0.4
2.4
0.2
4.8
0.4
V
mV
mV
mV
V
mA
V
V
SG1526BISG2526BISG3526B
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Test Conditions
Oscillator Section (Note 4)
Initial Accuracy
TJ = 25°C
Voltage Stability
Y'N = 8to 35V
Temperature Stability (Note S)
Over Operating TJ
Minimum Frequency (Note S)
RT = 150KO, CT= 2Ol-1F
Maximum Frequency
RT = 2Kn, CT= 470pF
Sawtooth Peak Voltage
Y'N = 35V
Sawtooth Valley Voltage
V,N = 8V
SYNC Pulse Width
RL = 2.0KO to VREF
Error Amplifier Section (Note 5)
Input Offset Voltage
Rs:!>2Kn
Input Bias Current
Input Offset Current
DC Open Loop Gain
RL~ 10MO
High Output Voltage
VPINt - VplN2 ~ 150mV, ISOURCE = 100j.1A
Low Output Voltage
VpIN2 - VPINt ~ 150mV, ISINK = 100j.1A
Common Mode Rejection
Rs:!>2Kn
Supply Voltage Rejection
Y'N = 8V to 35V
PWM Comparator Section (Note 4)
Minimum Duty Cycle
VCOMPENSATION = 0.4V
Maximum Duty Cycle
V
-3.6V
Digital Ports (SYNC, SHUTDOWN, and RESET)
HIGH Output Voltage
ISOURCE = 40j.1A
LOW Output Voltage
ISINK = 3.6mA
HIGH Input Current
V,H = 2.4V
LOW Input Current
V,L = 0.4V
(NoteS)
SHUTDOWN Delay to Output
Current Limit Comparator Section (Note 6)
Sense Voltage
Rs:!>500
Input Bias Current
Delav to Outout (Note SL
Soft-Start Section
Error Clamp Voltage
F!:~I=0.4V
Cs Charging Current
RESET = 2.4V
Output Drivers (each output) (Note 7)
HIGH Output Voltage
ISOURCE = 20mA
ISOURCE = 100mA
LOW Output Voltage
ISINK= 20mA
ISINK = 100mA
Collector Leakage
Vc =40V
Rise Time
CL= 1000pF
Fall Time
C = 1000pF
Power Consumption Section (Note B)
Standby Current
SHUTDOWN = 0.4V
Note 3.
Note 4.
Note 5.
Note 6.
/L = OmA
Fesc = 40KHz (RT = 4.12Kn ±1 %, CT = .Q1 ~F ±1 %, Re = On)
VCM = 0 to 5.2V
VCM = 0 to 12V
,SG1526B/2526B,
SG3526B
, Units
, Min.' Typ. Max.' Min. Typ. Max.,
500
2.5
0.5
64
3.6
70
66
±3
0.5
7
±8
1.0
10
1.0
3.0
1.0
1.0
3.5
1.1
2
500
2.5
0.5
5
2
-350 -1000
35 100
72
60
3.6
4.2
0.2 0.4
70
94
66
80
±3
0.5
3
±8
1.0
5
1.0
3.0
1.0
1.0
3.5
1.1
2
0
45
49
%
%
49
2.4
4
0.2 0.4
-125 -200
-225 -360
200
2.4
4
0.2 0.4
-125 -200
-225 -360
200
V
V
j.1A
j.1A
ns
90
100
-3
80
100
-3
120
-10
400
mV
j.1A
ns
0.1
100
0.4.
150
V
I-1A
50
110
-10
400
0.1 0.4.
100 150
50
12.5 13.5
12.5 13.5
12
13
12
13
0.2
0.2 0.3
2
1.2
1.2
50
50 150
0.3
0.3 0.4
0.1
0.1 0.15
I
mV
nA
nA
dB
V
V
dB
dB
10
2
-350 -2000
35 200
72
4.2
0.2 0.4
94
80
0
45
%
%
%
Hz
KHz
V
V
I-1s
18
30 ,
V
V
V
V
j.1A
I-1s
0.3
2
150
0.4
0.15
, 18 , 30
j.1S
I
mA
Note 7. Vc=15V
Note B. Y'N = 35V
Note S. These parameters, a/though guaranteed over the recom·
mended operating conditions, are not tested in production.
4 -113
II
SG1526BISG2526BISG3526B
CHARACTERISTIC CURVES
<'
E
>-E
r15
50
~z
is"
~
>-
25
~
iJ
!5
~
~
~
g -25
1/
~
,/'
.
V
/
/'
>-
'"
~
50
100
100
I'
80
60
~
-50
-50 -25
0
20
-50-25
25 50 75 lOa 125 150
FIGURE 2.
REFERENCE TEMPERATURE STABILITY
~
r--
~
"
40
~
20
w
~
\
~
IL= 0 rnA, CL=
""w
60
~
40
0.
0
20
- r.....
"-
:t?1
"cOMP~
'\
'\
2
z
100pr-:-
W
100
10K
1K
lOOK
10
1M
\
100
lK
10K
lOOK
FIGURES.
UNDER VOLTAGE LOCKOUT
'-""'-T"'T"'T"T""-'-""'--'7"T"'"1
500
I-+--I-I-++---+-¥-'+--,H
200
325
~
'OO~-+--r-+~~-r--+~~~
~
20
0
r
~
./
100
/
/
c
S
17''+-1-1
+
2N2907
~~
~
"
A~
I;
~
~
'"
c~~~:
10
CSOFTSTART (j.F)
FIGURE 7.
SOFTSTART TIME CONSTANT VS. Cs
20
50
Id ~
250
225
200
'---'----'--'-I--'--~'____'_:
I I ___I.1___I.1....w1
0.5
275
F
~~~~u~
LIMIT
10M
FIGURES.
ERROR AMPLIFIER OPEN I.OOP GAIN
VS. FREQUENCY
1.300
u
§
50 ~-+-"""''-j},d.
1M
FREQUENCY (Hz)
REfERENCE VOLTAGE (VOLTS)
1 SEC
g
~
80
~
z
I I I
i
"
25 50 75 100125150
0
FIGURE 4.
REFERENCE RIPPLE REJECTION
~
m
g
0iE
RIPPLE FREQUENCY (Hz)
:::i!
0
0.
10
8
r--.
JUNCTION TEMPERATURE-COC)
"
I~
,WIN - 1 VOLT PK-PK
-
FIGURE 3.
REFERENCE SHORT CIRCUIT
/
80
60
......
~
~
~
i"-~
w
m
is
F
........
40
JUNCTION TEMPERATURE-(OC)
FIGURE 1.
REFERENCE VOLTAGE VS. SUPPLY VOLTAGE
'"
u
'"
10
120
20406080100120140160180
DIFFERENTIAL INPUT VOLTAGE (mV)
FIGURES.
CURRENT LIMIT TRANSFER FUNCTION
4 -114
~
~~ ~
-50 -25
~~
0
~r
lOOmv
Overdrive
25 50 75 100 125 150
JUNCTION TEMPERATURE-(OC)
FIGURE 9.
COMPARATOR INPUT TO DRIVER OUTPUT DELAY
SG1526BISG2526BISG3526B
CHARACTERISTIC CURVES (continued)
10
25
-;;E
100
;r
20
i
15
~z
10
/
/
----
I
u
;0
V
V
RO=OO
....
I
V>
/'
R t =2.7K
./
,,/
J
10
20
30
40
CT= D1.uF
12
1.0
.001
50
rosc=40KHZ
16
20
24
RO-
V>
30
L
/
100
i
S
eo
-2
~
'"
-4
"~
-6
r-
i
20
50
100
FOSC=40KHz
50
FIGURE 14.
SUPPLY CURRENT VS. OUTPUT FREQUENCY
~O~5
FIGURE 15.
SUPPLY CURRENT VS. OUTPUT FREQUENCY
I-
a
25
~
75100125150
FIGURE 16.
OSCILLATOR FREQUENCY
TEMPERATURE STABILITY
"
w
120
!
100
V>
SOURCE
JUNCTION TEMPERATURE-(OC)
300
160
I'~
'"
100
FREQUENCY-(KHz)
A
J::;
~
1000pF
I'
~
~ 140
Ct "" 01~f
RO=OO
/
V V
300
V,N =VC=15V
Rt =4.12K
40
30
III
-
II
Full Duly Cycle
Ct =470pF
Rt =22K-155K
FREQUENCY-(KHZ)
...... ~
,.
2500P}
10
300
FIGURE 13.
SUPPLY CURRENT VS. OUTPUT FREQUENCY
"
II
Y'N ",Vc=28V
50
i3
20
50
j
60
Y'N "'VC~15V
CL=2S00pF Both Outputs
FREQUENCY-(KHz)
~
FIGURE 12.
OUTPUT DRIVER DEADTIME VS. RD VALUE
FIGURE 11.
OUTPUT DRIVER DEADTIME VS. Cr VALUE
FIGURE 10.
STANDBY CURRENT VS. SUPPLY VOLTAGE
~
V
kss; ~ ~ ~
~~ ~ ~ ~:.Y
80
SINK
10
OUTPUT DRIVER LOAD CURRENT-(mAl
FIGURE 17.
OUTPUT DRIVER SATURATION VOLTAGE
4 -115
100
-50 -25
0
25 50 75 100125150
JUNCTION TEMPERATURE-(OC)
FIGURE 18.
SHUTDOWN INPUT TO DRIVER OUTPUT DELAY
SG1526BISG2526BISG3526B
CHARACTERISTIC CURVES (continued)
s
4:
20r--r--~L-~~--~~~~-iq-"~~~f-~~f-~r-~~L-~--;-~---i
0:
5p.
101' 20p.
FIGURE 19.
OSCILLATOR PERIOD VS. RT AND CT
50p. 1001' 200p.
500p. 1m
2m
5m
10m 20m 50m
100m200m 500rn
1
5
OSCILLATOR PERIOD-(.)
APPLICATION INFORMATION
VOLTAGE REFERENCE
The reference regulator of the SG1526B is a "band-gap" type; that is, the precision
+5 volt output is derived from the very predictable base-emitter voltage of an NPN
transistor. Since this is a sub-surface phenomenon, the resulting output exhibits
excellent stability compared to earlier surface-breakdown zener designs.
The reference output is stabilized at input voltages as low as +8 volts, and can
provide up to 20mA of load current to external circuitry. An external PNP transistor
can be used to boost the available current to many hundreds of mAo A rugged lowfrequency audio·type transistor should be used, and lead lengths between the PWM
and transistor should be as short as possible to minimize the risk of oscillation.
UNDERVOLTAGELOCKOUT
The undervoltage lockout circuit protects the SG1526B and the power devices it
controls from inadequate supply voltage. If +V'N is too low, the circuit disables the
output drivers and holds the RESET pin LOW. This prevents spurious output pulses
while the control circuitry is stabilizing, and holds the soft-start timing capacitor in a
discharged state.
The circuit consists of a merged bandgap reference and comparator circuit which is
active when the reference voltage has risen to 2V BE or 1.2 volts at 25°C. When the
reference voltage rises to approximately +4.4 volts, the circuit enables the output
drivers and releases the RESET pin, allowing a normal softstart. The comparator
has 200mV of hysteresis to minimize oscillation at the trip point. When +V'N to the
PWM is removed and the reference drops to +4.2 volts, the undervoltage circuit pulls
RESET LOW again. The soft-start capacitor is immediately discharged, and the
PWM is ready for another soft-start cycle.
The SG1526B can operate from a +5 volt supply regulated to within ±4% by
connecting the VREF pin to the +V'N pin.
SOFT-START CIRCUIT
The soft-start circuit pro!ects the power transistors and rectifier diodes from high
current surges during power supply turn-on. When supply voltage is first applied to
the SG1526B, the undervoltage lockout circuit holds RESET LOW with 03. 01 is
turned on, which holds the soft-start capacitor voltage at zero. The second collector
of 01 clamps the output of the error amplifier to ground, guaranteeing zero duty cycle
at the driver outputs. When the supply voltage reaches normal operating range,
RESET will go HIGH. 01 turns off, allowing the internall00flA current source to
charge Cs. 02 clamps the error amplifier output to 1.0 VBE above the voltage on Cs.
As the soft-start voltage ramps up to +5 volts, the duty cycle of the PWM linearly
increases to whatever value the voltage regulation loop requires for an error null.
Figure 7 gives the timing relationship between Cs ramp time to 100% duty cycle.
4 - 116
'10
GND
FIGURE 20.
EXTENDING REFERENCE OUTPUT CURRENT
TO RESET
TO DRIVER A
TO DRIVER B
FIGURE 21.
SIMPLIFIED UNDERVOLTAGE LOCKOUT
FIGURE 22.
SCFT·START CIRCUIT SCHEMATIC
SG1526BISG2526BISG3526B
APPLICATION INFORMATION (continued)
DIGITAL CONTROL PORTS
The three digital control ports of the SG1526B are bi-directional. Each pin can drive TIL and 5 volt CMOS logic directly,
up to a fan-out of 10 low-power Schottky gates. Each pin can
also be directly driven by open-collector TIL, open-drain
CMOS, and open-collector voltage comparators, fan-in is
equivalent to 1 low-power Schottky gate. Each port is
normally HIGH; the pin is pulled LOW to activate the particular function. Driving SYNC LOW initiates a discharge cycle
in the oscillator. Pulling SHUTDOWN LOW immediately
inhibits all PWM output pulses. Holding RESET LOW discharges the soft-start capacitor. The logic threshold is +1.1
volts at +25°C. Noise immunity can be gained at the expense
of fan-out with an external 2K pull-up resistor to +5 volts.
OSCILLATOR
The oscillator is programmed for frequency and dead time
with three components: RT Cp and RD. Two waveforms are
generated: a sawtooth waveform at pin 10 for pulse width
modulation, and a logic clock at pin 12. The following
procedure is recommended for choosing timing values:
1. With RD = on (pin 11 shorted to ground) select values
for RT and CT from Figure 19 to give the desired
oscillator period. Remember that the frequency at
each driver output is half the oscillator frequency, and
the frequency at the +Vc terminal is the same as the
oscillator frequency.
2. If more dead time is required, select a larger value of
RD using Figure 14 as a guide. At 40 KHz dead time
increases by 300 ns/n.
3. Increasing the dead time will cause the oscillator
frequency to decrease slightly. Go back and decrease the value of RT slightly to bring the frequency
back to the nominal design value.
The SG1526B can be synchronized to an external logic clock
by programming the oscillator to free-run at a frequency 10%
slower than the sync frequency. A periodic LOW logic pulse
approximately 0.5 J.lSeC wide at the SYNC pin will then lock
the oscillator to the external frequency.
ERROR AMPLIFIER
The error amplifier is a transconductance design, with an
output impedance of 2 megohms. Since all voltage gain
takes place at the output pin, the open-loop gain/frequency
characteristics can be controlled with shunt reactance to
ground. When compensated for unity-gain stability with 100
pF, the amplifier has an open-loop pole at 400 Hz.
The input connections to the error amplifier and determined
by the polarity of the switching supply output voltage. For
positive supplies, the common-mode voltage is +5.0 volts
and the feedback connections in Figure 25A are used. With
negative supplies, the common-mode voltage is ground and
the feedback divider is connected between the negative
output and the +5.0 volt reference voltage, as shown in
Figure 25B.
SYNC
TO
INTERNAL
LOGIC
SHUTDOWN
OR RESET
FIGURE 23
DIGITAL CONTROL PORT SCHEMATIC
Multiple devices can be synchronized together by programming one master unit for the desired frequency, and then
sharing its sawtooth and clock waveforms with the slave
units. All CT terminals are connected to the CT pin of the
master, and all SYNC terminals are likewise connected to the
SYNC pin olthe master. Slave RT terminals should not be left
open; at least 50K should be connected from each pin to
ground. Slave RD terminals may be either left open or
grounded.
FIGURE 24.
OSCILLATOR CONNECTIONS ANDD WAVEFORMS
VREf~R3
l'
R2
\
ONo
Your =
R3=
POSITIVE
OUTPUT
VOLTAGE
(~)
R1+R.2
(A)
FIGURE 25.
ERROR AMPLIFIER CONNECTIONS
4 -117
ONo
VREF(R~~R2)
(8)
•
SG1526BISG2526BISG3526B
APPLICATION INFORMATION (continued)
OUTPUT DRIVERS
The totem-pole output drivers of the SG15268 are designed
to source and sink 100mA continuously and 200mA peak.
Loads can be driven either from the output pins 13 and 16, or
SUPPLY o--,---------~
from the +Vc pin, as required. Curves for the saturation
voltage at these outputs as a function of load current are
found· In Figure 17.
+15V
+V SUPPLY
0---,--------,
II
T1
15
RETURN
RETURN 0 - - - - ' - - - " " "
RETURN
FIGURE 28.
DRIVING N-CHANNEL POWER MOSFETS
FIGURE 26.
PUSH·PULL CONFIGURATION
SG1526B LAB TEST FIXTURE
-15V
MIN.
_______
Y20
.J}F"
+15V
+Vc
+15V
GND
MAX.
,01
lOOl
~F j!F
LfJ
TO
33K
Jl
10K
EXTERNAL
SYNC
~OO1~FS::36.
lK
510
7S0n
--1""<'-"',- TO
-ERROR
10K±O.'X
+18TE5T
"----HllJQ--,-- TO +ERROR
10K±O.1%
4 -118
OR EQUIV.
C.S.
TO
TO
Xl0
+C.S.
-C.S.
CD.T~·
~~~~
LJ=-tJ
1
SG1526BISG2526BISG3526B
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
18-PIN CERAMIC DIP
J- PACKAGE
Part No.
SG1526BJ/883B
SG1526BJ
SG2526BJ
SG3526BJ
(See Notes Below)
Ambient
Temperature Range
Connection Diagram
-55°C to 125°C
-55°C to 125°C
-55°C to 125°C
DOC to 7Doe
to 85°C
DOC to 7Doe
18-PIN PLASTIC DIP
N- PACKAGE
SG2526BN
SG3526BN
-25°C
18-PIN WIDE BODY
PLASTIC S.O.I.C.
DW-PACKAGE
SG2526BDW
SG3526BDW
-25°C
+VIN
OUTPUTS
GROUND
CSOFTST"fIT
RESET
- CURRENT SENSE
+ CURRENT SENSE
VCOUECTOR
OUTPUT A
SYNC
ROEAOTIME
C,
to 85°C
DOC to 7Doe
VREF
+ ERROR
-ERROR
COMPENSATION
+ERAOA
VREF
-ERROR
COMPENSATION
+VIN
OUTPUTS
GROUND
C SOFTSTART
RESET
+VcoueCTOR
- CURRENT SENSE
+ CURRENT SENSE
OUTPUT A
SYNC
SHUTDOWN
R,
24-PIN CERAMIC
FLAT PACK
F- PACKAGE
SG1526BF/883B
SG1526BF
-55°C to 125°C
-55°C to 125°C
-ERROR
+ERROR
N.C.
~~_ _~~
~~~~~~~~~~
COMP
+V""
OUTPUT B
CsonSTAAT
RESET
GROUND
·C.5.
+VCOlLECTOR
+ C.S.
OUTPUT A
N.C.
SYNC
~
N.C.
SHUTDOWN
ROEAOTNe
R,
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L- PACKAGE
SG1526BU883B
SG1526BL
-55°C
-55°C
to 125°C
to 125°C
N.C.
v",
N.C.
1. N.C.
2. +ERROR
a.-ERROR
4.COMP
5,C SOFTSTAAT
6. RESET
7.-C.S.
6. + C.5.
9. SHUTDOWN
10.RT
C,
Dc:
3
4
5
•
2
1
20 19
11.CJ
1.
17
16
7
15
•
14
9
10 11 12 13
12. ROEADTlME
la.SYNC
14. OUTPUT A
lS.N.C.
16. +VCOUECTOR
17. GROUND
16. OUTPUTS
19,+V1N
20. VREi'
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
4 -119
•
4 -120
SG15281SG25281SG3528
SG1530lSG2530lSG3530
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
FUTURE PRODUCT RELEASE
HIGH SPEED CURRENT MODE PWM CONTROLLER
DESCRIPTION
FEATURES
The SG1528/30 family of single-ended pulse width modulators are
optimized for high frequency, current mode control of switching power
supply applications. The control architecture also allows its use as a unidirectional motor speed controller. The circuit features internally preset
start-up and run voltage thresholds compatible with power N-channel
MOSFETs. A precision low-drift bandgap reference exhibits excellent
long-term stability. Both the voltage error amp and current amp are
wideband operational amplifiers for high speed performance and maximum applications flexibility. A high peak-currenttotem-pole output driver
permits direct drive of the power switch. The difference between these
two series of controllers is the maximum duty cycle range of the output
stage. The SG1530 family can operate to duty cycles approaching
100%, where they are mainly used in non-isolated DC-DC converters
whereas the 1528 series has a duty cycle range of zero to <50%,
optimized for isolated, primary-side control of switching power supplies.
The SG1528/1530 is specified for operation over the full military ambient
temperature range of -55 D C to 125D C. The SG2528/2530 is characterized for the industrial range of -25D C to 85 D C, and the SG3528/3530 is
designed for the commercial range of ODC to 70 DC.
• Current mode or voltage mode control
• Micropower start-up mode (0.6mA max.)
• ±1% Low-drift reference
• Wideband voltage error amp (6MHz typ.)
• Wideband current differential amp (12MHz typ.)
• Output Frequencies to 2MHz
• Programmable DC Bus O.V. and U.V. sense
• High speed shutdown
• Soft start
• Full fault suppression logic
• 2A peak output current drive
• Output driver rise and fall time less than 30ns
• Ideal for using with SENSFETS
HIGH RELIABILITY FEATURES
- SG1528/SG1530
o Available to MIL-STD-883
• SG level "S" processing available
BLOCK DIAGRAM
V REF
17
S.10V
UNOERVOLTAGE
14
11
4.2V
OVER VOLTAGE
10
"HICCUP' THRESHOLD
E.Aa",
E.A·
V,
13
OUTPUT DRIVER
0.'----1
06----=========;1
POWERGNO
E.A+
C.A+
C.AC.~
SOFT START CAP
16
SYNC
ANALOG
GNO
Note 1. Toggle Flip-Flop used only in 1528 series.
April 1990
4-121
•
SG15281SG1530 SERIES
ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage (VIN ' V0) ...................................................... 22V
Analog Inputs (ERR, CUR, OV, UV) ....................... -0.3V to VIN
Logic Inputs (SYNC) ............................................. -0.3V to 5.5V
Source I Sink Load Current (continuous) ........................... 0.5A
Source I Sink Load Current Peak (200ns) ............................ 3A
Reference Load Current ................................................... 50mA
Soft Start Discharge Current ............................................ 50mA
Sync Output Source Current .............................................. 5mA
Note 2. Values beyond which damage may occur.
Error Amplifier Output Current ............................................ 5mA
Current Sense Amplifier Output Current ............................. 5mA
Oscillator Discharging Current ............................................ 5mA
Operating Junction Temperature
Hermetic (J, F, L Packages) ......................................... 150'C
Plastic (N, OW Packages) ............................................ 150'C
Storage Temperature ........................................ -65'C to 150'C
THERMAL DERATING CURVES
2.5
20
~
11.5
~~
is
1.0
i
5.0
ro...
4.'
"~~'"
~
~
~~
'.O~I.b..
1:5.0
I
"1-t;.6>
it: ~4
<>o::~
0",
'-9-1-
.a
~0
0
0
25
50
75
0<0
~~
'00
125
150
1\
~,
~
I"r,e~~..
~
'I"
I ~.~~~~
~~ ~
,.,
...... ~
a
~('C'C) ~ &r~C'
'5
~
2.0
0
175
AMBIENT TEMPERATURE - "C
0
25
50
75
'00
~
'25
,SO
175
CASE TEMPERATURE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3. Range over which the device is functional.)
Collector Voltage ..................................................... 4.5V to 20V
Supply Voltage Range .............................................. 13V to 20V
Source I Sink Output Current (continuous) ........................ 0.3A
Source I Sink Output Current Peak (200ns) ....................... i .5A
Reference Load Current ............................................ 0 to lOrnA
Oscillator Frequency Range ............................. 1KHz to 1.5MHz
Oscillator Timing Resistor (RT) ................................ 1Kn to TBD
Oscillator Timing Capacitor (CT) ........................ 500pF to O.l!iF
Operating Ambient Temperature Range
SG1528 ......................................................... -55'C to 125'C
SG2528 ........................................................... -25'C to 85'C
SG3528 ............................................................... O'C to 70'C
ELECTRICAL SPECIFICATIONS (Note 4)
(Unless otherwise specified, these specifications apply over the operating ambienllemperatures for SG152BISG1530 with ·55°e S; T. S; 125°e, SG252BI
SG2530 with ·25°e S; T. S; B5°e, SG352B/SG3530 with ooe S; T. S 70oe, and V'N = Vc = 15V (Note 5). Low duty cycle pulse testing techniques are used
which maintains junction and case temperatures equal to the ambient temperature.}
Parameter
Reference Section
Output Voltage
Line Regulation
Load Regulation
Temperature Stability (Note 6)
Total Output Variation
Output Noise Voltage (Note 6)
Long-Term Stablility (Note 6, 7)
Short Circuit Output Current
Oscillator Section (Note 8)
Initial Accuracy
Voltage Stability
Temperature Stability
Minimum Frequency
Maximum Frequency
Ramp Peak Voltage
Test Conditions
TJ =25'C, 10 =lmA
VIN =13V to 20V
Il =1 to lOrnA
Line, Load and Temp
TJ = 25°C, 10Hz < f < 10KHz
TJ =125°C, 1000Hrs
VREF = OV
=
TJ 25°C, CSYNC ::;; 10pF
VIN = 13V to 20V
Over Operating Range
RT =TBD ; Cr = TBD
RT =TBD; CT = TBD
4 -122
SG1528/2528
SG3528
SG1530/2530
SG3530
Units
I Min. Typ.1 Max. I Min. Typ·IMax·1
V
5.05 5.10 5.15 5.05 5.10 5.15
mV
3
15
3
15
2
mV
15
2
15
mV
20
20
40
40
V
5.0
5.2 5.0
5.2
100
100
!iVlrms
mV
5
25
25
5
15
50 100 15
50 100 rnA
0.9
2
1.0
1.1
±O.5
±4 ±8
0.5 1.0
3
3.8
0.9
2
1.1
±O.5
±4 ±8
0.5 1.0
3
3.8
1.0
MHz
%
%
KHz
MHz
V
SG15281SG1530 SERIES
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Test Conditions
Oscillator Section (Note 8)
Ramp Valley Voltage
Ramp Valley to Peak Amplitude
Sync Output High Level
TJ = 25°C, ISYNC = 1mA
Sync Output Low Level
TJ = 25°C, ISYNC = lmA
Sync Input High Level (Note 6)
TJ = 25°C
Sync Input Low Level (Note 6)
TJ = 25°C
Sync Input Current, High & Low
(Note 6)
Sync Output Pulse
CCLK';; 10pF, ISYNC = OmA
Error Amplifier Section (E.A) (Note 9)
Input Offset Voltage
Rs';; 1000, E.AoUT = 2.5V
Input Bias Current
VCM =2.5V
Input Offset Current
VCM = 2.5V
Common Mode Range
Open Loop Gain
VCM = 2.5V, Output Volt. Ito 2.5V, RL = 10K
Unity Gain Bandwidth (Note 6)
AVOL = OdB
Output Voltage Slew Rate (Note 6) See Figure TBD
CMRR
VCM = 1.7V to 7V
PSRR
V,N = 13Vto 20V
Output Sink Current
E.-\'UT = 2V, I1V = 150mV
Output Source Current
E.-\,UT = 2V, I1V = t50mV
Output High Level
RL=10K
R =10K
Output Low Level
Current Sense Amplifier (C.A) Section (Note 10)
Input Offset Voltage
RCM $; 100, C.AaUT = 2.5V, VCM = 1.5V
Input Bias Current
VCM = O.tv
VCM = O.IV
Input Offset Current
Common Mode Range
Open Loop Gain
VCM = 1.5V, Output Voltage 1 to 2.5V, RL = 5K
Unity Gain Bandwidth (Note 6)
AVOL = OdB
Output Voltage Slew Rate (Note 6) See Figure TBD
CMRR
VCM = O.IV to 7V, C.AOUT = 2.5V
PSRR
V,N = 13V to 20V, VCM = 0.1
Output Sink Current
C.AOUT = 2V, VCM = 2.5V, I1V = 75mV
Output Source Current
C'-\'UT = 2V, VCM = 2.5V, I1V = 75mV
Delay to Output (Note 6)
C.AOUT = 0.5V to 2V, E.AoUT = 1.5V
Output High Level
RL =5K
Output Low Level
RL =5K
"Hiccup" Section
Rs';; 100, VCM = 1.7V to 2.5V
Input Offset Voltage
Input Bias Current
C'-\'UT = 2.5V, VHICCUP = 1.7V to 3.5V
Common Mode Range
Delay to Output (Note 6)
C.AnliT = 2.2V, V"'OOII. = 2V, E.AnliT = 2.5V
Overvoltage/Undervoltage Section
Overvoltage Threshold Voltage
IREF = lmA
Overvoitage Hysteresis
IREF = lmA
Undervoltage Threshold Voltage
IREF = lmA
Undervoltage Hysteresis
IREF = lmA
Delay to Output (Note 6)
O.V. = VREF + 0.2V
O.V. Input Bias Current
O.V.lnput= 10V
U.V. Input Bias Current
U.V. Input = 10V
4 -123
SG1528/2528
SG3528
SG1530/2530
SG3530
Units
I Min. Typ. Max. I Min. I Typ. Max. I
2.8
0.9 1.0 1.1 0.9
4.2 4.35 4.5 4.2
3.35 3.55 3.75 3.35
4.25
4.25
3.6
1
2
200 275 350 200
1.7
60
4
5
75
90
0.4
3
2.6
5
15
2.5
7
64
6
10
100
0.7
6
2.8
0.1
2.5
200
0.1
60
8
10
75
90
0.5
5
3.8
0.3
5
500
50
7
64
12
20
100
1.33
10
1.7
60
4
5
75
90
0.4
3
2.6
2.8
1.0 1.1
4.35 4.5
3.55 3.75
1
275
5
15
2.5
7
64
6
10
100
0.7
6
2.8
0.1
2.5
200
0.1
60
8
10
75
90
0.5
5
3.5
0.2
0.4
60
10
10
3.5
650
1.7
5
500
50
7
1.33
10
80
2.7
4.0 4.2 4.4
350 450 550
4.0 4.2 4.4
660 830 1000
550 800
2
6
2
6
3.8
0.3
64
12
20
100
80
2.7
3.6
2
350
3.5
0.2
0.4
60
10
10
3.5
650
1.7
4.0
350
4.0
660
4.2 4.4
450 550
4.2 4.4
830 1000
550 800
2
6
2
6
V
V
V
V
V
V
mA
ns
mV
IlA
!lA
V
dB
MHz
V/IlS
dB
dB
mA
mA
V
V
mV
IlA
!lA
V
dB
MHz
V/IlS
dB
dB
mA
mA
ns
V
V
mV
!lA
V
ns
V
mV
V
mV
ns
!lA
IlA
•
SG15281SG1530 SERIES
ELECTRICAL SPECIFICATIONS (continued)
Parameter
SG1528/2528
SG3528
SG1530/2530
SG3530
Units
I Min. I Typ. Max·IMin. Typ·IMax.
Test Conditions
Output Section
Collector Leakage Current
Output High Level
Output Low Level
Maximum Duty Cycle (Note 8)
Zero Duty Cycle
Rise Time (Note 6)
Fall Time (Note 6)
Bleeding Resistor
Cross Conduction Current (Note 6)
Start Up Section
Start Up Voltage
Start Up Current
Shut Down Voltage
Delay to Output on Shut Down
Soft-Start Section
Soft Start Charging Current
Soft Start Discharge Current
Soft Start Discharge Voltage
Power Consumption Section
Total Supply Current
Standby Current
Vc .. 20V, Output off
ISOURCE = 50mA
'SOURCE = 200mA
ISINK = 50mA
ISINK = 200mA
E.AoUT = 2V, c.Aour = 1.5V
E.Aour = 0.5V, C.Aour = 0.6V
Cl =lnF
Cl =lnF
Tristate Output, V'N = 11 V (Note 6)
C =lnF
0.5
13 13.5
12.5 13.5
0.3 0.5
1
2
45
48
51
0
25
50
20
50
10
60
6
60
0.5
13 13.5
12.5 13.5
0.3
1
45
48
25
20
10
6
0.5
2
51
0
50
50
60
60
mA
V
V
V
V
%
%
ns
ns
Kn
nJ/Hz
16 16.5 15.5 16 16.5
350 600
350 600
11.5 12 12.5 11.5 12 12.5
150 300
150 300
15.5
V,N = Start-Up Threshold
Output Low, V,N = 11 V (Note 6)
35
VSOFTSTAAT = 0.5V, VHICCUP = 4V
VSOFTSTART = l1V, V,N = llV
'DISCHARGE = 30mA
45
55
2
to = 200KHz, Cl = 1000pF
VU.v = 3.5V
Note 4. Performance data described herein represent design goals.
Final device specifications are subject to change.
Note 5. Adjust V,N above the start threshold before setting it to 15V.
Note 6. This parameter, although guaranteed, is not tested In production.
35
30
55
45
30
35
50.
20
35
V
IIA
V
ns
IIA
2
mA
V
50
20
mA
mA
Note 7. This parameter is non-accumulative, and represents the random fluctuation of the reference voltage within some eTTor band
when observed over any 1000 hour period of time.
Note 8. Fosc = 1MHz (AT = TBD ,CT= TBD)
Note 9. C.A - =1.1V, C.A + =1V
Note 10. E.A - = 2.5V, E.A + = 2.4V
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
18-PIN CEAAMIC DIP
J- PACKAGE
18-PIN WIDE BODY
PLASTIC S.O.l.C.
OW-PACKAGE
Part No.
Ambient
Temperature Range
SG1528J/883B
SG1528J
SG2528J
SG3528J
SG1530J/883B
SG1530J
SG2530J
SG3530J
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
O°C to 70°C
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
O°C to 70°C
SG2528DW
SG3528DW
SG2530DW
SG3530DW
-25°C to 85°C
0°Ct070°C
-25°C to 85°C
O°C to 70°C
Notes: 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
Connection Diagram
.C.A + [-,--cr;o
C.A- [2
c.A"."
E.A+
E.A·
E.A"."
P ANALOG GND
17p VREF
[3
lOp
[4
15p
[5
14
[6
SOFT START [7
HICCUP C e
13
SYNC
R,IC,
P UNDERVOlTAGE
P OVERVOlTAGE
12p Vf.I
11
VC
p
POWER GROUND [~P DRIVER OUTPUT
C.A+
C.A·
c.A"."
E.A+
E.A·
E·Ao",
SOFTSTART
HICCUP
POWER GROUND
[[
[[
[[
[[
[[
[[
[[
[[
[[
II
ANALOG GND
1
1.
2
17:JJ VREF
3
16
4
15
5
6
7
•
9
I I SYNC
I I R,iC,
I I UNDERVOlTAGE
13 I I OVERVOlTAGE
12::IJ V1N
11 :IJ Vc
10 I I DRIVER OUTPUT
14
3. Product is also available in leadless chip carrier (LCC) and 24-pin
hermetic flat pack (F). Contact factory for price and availability.
Silicon General • 11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4-124
SG15291SG25291SG3529
SILICON
GENERAL
REGULATING PULSE WIDTH MODULATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1529 series of pulse width modulator integrated circuits are designed to
provide all the operational features of the SG1524B series with the added
advantage of an uncommitted input to the PWM comparator. This allows the
device to be used in Feed-Forward regulation schemes to achieve better line
regulation as well as improved dynamic response. A 5V bandgap reference
trimmed to ±1 % tolerance, an error amplifier, and a current limit comparator with
a high common mode range are included in the I.C.
•
•
•
•
•
•
•
•
•
•
•
•
A DC coupled flip-flop eliminates triggering and glitch problems, and a PWM
data latch prevents edge oscillations. The circuit incorporates true digital
shutdown for high speed response while an undervoltage lockout circuit prevents spurious outputs when the supply voltage is too low for stable operation.
Full double-pulse suppression logic insures alternating output pulses when the
Shutdown pin is used for pulse-by-pulse current limiting. The SG1529 is
specified for operation over the full military ambient temperature range of -55°C
to 125°C. The SG2529 is characterized for the industrial range of -25°C to 85°C
and the SG3529 is designed for the commercial range of O°C to 70°C.
Feed forward capability
7V to 40V operation
5V reference trimmed to ±1%
100Hz to 400KHz oscillator range
Excellent external sync capability
Dual100mA output transistors
Wide current limit common mode range
DC-coupled toggle flip-flop
PWM data latch
Undervoltage lockout
Full double-pulse suppression logic
SOV output collectors
HIGH RELIABILITY FEATURESSG1529
• Available to MIL-STD-883
• SG level "5" processing available
BLOCK DIAGRAM
+VIN
GROUND
RT
COLLECTOR A
CT
F.F.
EMITIER A
COLLECTORS
INVERTING
NON·INVERTING
EMITTERS
+C.l. SENSE
·C.l.SENSE
COMPENSATION
SHUTDOWN
April.1990
4-125
II
SG15291SG25291SG3529
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage (+V ,N) ............................................................. 42V
Collector Voltage ................................................................. 60V
Logic Inputs ......................................................... -0.3V to 5.5V
Current Limit Sense Inputs ..................................... -0.3V to Y'N
Output Current (each transistor) .................................... 200mA
Reference Load Current ................................................... 50mA
Note 1. Values beyond which damage may occur.
Oscillator Charging Current ................................................ 5mA
Operating JI,mction Temperature
Hermetic (J Package) ................................................... 150°C
Plastic (N, DW Packages) ............................................ 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) .................... 300°C
THERMAL DERATING CURVES
2.5 ,...--,..----,---,--.....,.---,----r---,
50,...--r----,---,--.....,.---,----r--,
~
~
~
C 2.0
1---1-----,
i
1.0
1---1----l---+---f~n-+--1
175
AMBIENT TEMPERATURE - "c
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION VB AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION VB CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage (+V,N) ••...•••..•••••...•••..••••.•••••.••••••..••.•..•••• 7V to 40V
Collector Voltage .................... .......................... ......... OV to 60V
Error Amp Common Mode Range .......................... 2.3V to VREF
Current Limit Sense Common Mode Range ....... OV to V,N-2.5V
Output Current (each transistor) .............................. 0 to 100mA
Reference Load Current ............................................ 0 to 20mA
Oscillator Charging Current ............................... 25JlA to 1.8mA
Note 2: Range over which the device is functional.
Oscillator Frequency Range ........................... 1OOHz to 400KHz
Oscillator Timing Resistor (Rr) ........................... 2KQ to 150KQ
Oscillator Timing Capacitor (Cr ) ............................. 1nF to 0.1 JlF
Operating Ambient Temperature Range
SG1529.......................................................... -55°C to 125°C
SG2529..................... ....................................... -25°C to 85°C
SG3529.......... ................. .................................... O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1529 with -55°C';; T. ,;; 125°C, SG2529 with
-25°C,;; T.,;; 85°C, SG3529 with O°C ,;; T. ,;; 70°C, and +V'N = 20V. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
Parameter
Reference Section (Note 3)
Output Voltage
Line ~egulation
Load Regulation
Temperature Stability (Note 7)
Total Output Voltage Range
Short Circuit Current
Undervoltage Lockout Section
Threshold Voltage
Test Conditions
TJ = 25°C
Y'N = 7V to 40V
IL =Oto 20mA
Over Operating Temperature Range
Over Line. Load and Temperature
VREF = OV
SG1529/2529
SG3529
Units
Min. Typ. Max. I Min. I TYP.I Max. I
4.95 5.00 5.05 4.90 5.00 5.10
3
20
3
30
5
30
5
50
15
50
15
50
4.90
5.10 4.80
5.20
25
50 120 25
50 120
4.3
Note 3. IL = OmA
4-126
4.5
4.7 14.3
4.5
4.7
V
mV
mV
mV
V
mA
V
SG15291SG25291SG3529
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Test Conditions
Oscillator Section (Note 4)
Initial Accuracy
TJ = 25°C
Voltage Stability
Y'N = 7V to 40V
Temperature Stability (Note 7)
Over Operating Range
Minimum Frequency
RT= 150Kn, CT= O.lliF
Maximum Frequency
RT = 2Kn, CT= 470pF
Sawtooth Peak Voltage
Y'N = 40V
Sawtooth Valley Voltage
V,N =7V
Clock Amplitude
Clock Pulse Width
Error Amplifier Section (Note 5)
Rs :S;2Kn
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
RL ~ 10Mn
Output Low Level
ISINK = 1001iA; VPIN 1 - VPIN 2 ~ 150mV
Output High Level
ISOURCE = 1001iA; VpIN2 - VplNI ~ 150mV
Common Mode Rejection
VCM = 2.3V to VREF
Supply Voltage Rejection
Y'N = 7V to 40V
Gain-Bandwidth Product (Note 7)
T = 25°C
P.W.M. Comparator (Note 4)
Minimum Duty Cycle
VCOMP = 0.5V (Note 8)
Maximum Duty Cycle
VCaMP = 3.9V (Note 8)
Input Bias Current
V.. = 0.5V to 3.9V
Current Limit Amplifier Section (Note 6)
Sense Voltage
Input Bias Current
Shutdown Input Section (Note 6)
HIGH Input Voltage
HIGH Input Current
VSHUTDOWN = 5.0V
LOW Input Voltage
Output Section (each transistor)
Collector Leakage Current
VcE =60V
Collector Saturation Voltage
Ic= 10mA
Ic= 100mA
Emitter Output Voltage
IE = 10mA
IE= 100mA
Emitter Voltage Rise Time (Note 7) RE = 2Kn, TA = 25°C
Collector Voltage Fall Time
R" = 2Kn, T = 25°C
Power Consumption
Standby Current
Y'N = 40V, V.HIJTnClWN = 2.0V
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
SG1529/2529
SG3529
U ·t
I Min. Typ.IMax. Min. Typ. Max.1 m s
42
45
±O.I
±1
50
400 600
3.5
0.6
I
3.0 4.0
0.2 0.5
0.5
1
60
3.8
70
76
I
78
0.2
4.2
90
100
2
45
49
48
±1
±2
140
3.9
1.2
40
45
±0.1
±1
50
400 600
3.5
0.6
1
3.0 4.0
0.2 0.5
5
5
I
2
1
60
3.8
70
76
1
78
0.2
4.2
90
100
2
45
49
0.5
0
2
180 200 220
-3
-10
170 200
-3
2.0
2.0
0.1
17.5
17
0.2
1.0
19
18
0.2
0.1
1
0.6
50
0.4
2.0
0.5
0.2
0.1
0.2
1.0
17.5 19
17
18
0.2
0.1
5
I 5 I 12 I
I
Fosc = 43KHz (RT = 2700n, CT= .01I1F)
VCM = 2.3V to VR'F
VCM = OV to 17.5V
These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
CT connected to FF.
4-127
50
±1
±2
120
3.9
1.2
10
10
1
0.5
KHz
%
%
Hz
KHz
V
V
V
lis
mV
liA
IiA
dB
V
V
dB
dB
MHz
0
%
%
2
IiA
230
-10
mV
1
0.6
50
0.4
2.0
0.5
0.2
IiA
V
mA
V
IiA
V
V
V
V
liS
!is
12 I mA
II
SG15291SG25291SG3529
APPLICATION CIRCUITS
rSM625
15Vdc
, +220
TO
~F
32Vdc
INPUT
50V
--*
L1
~
iU
T
I
L
'F 27DOpF
0.033
2W
+12V
~
I
+,oo¥
OUTPUT
= .11'1'
0.5 TO SA
LOAD
6.2
1/2 W
I
~
~
GND
10K
;-J'4
161
~
5
4
~r--
'1
10K
8
~22!'i"F
41Ql
.--I -
SG1529
3
3.9K
~I-
~IVN10Kt.4
~
tL
'F
CR,
lN4148
7
6
10
9
2.7K
6.BK
18K
.01 =
~F
:=~}
= =;022
~F
*Ll: OUTPUT INDUCTOR
1
CORE: MICRO METAL n06-26
lURNS: 45 TURNS #18 AWG
'"
FIGURE 1 - 60V STEP DOWN BUCK CONVERTER
The above schematic describes a SOW step down (Buck) converter where feed forward feature is obtained by generating a ramp with
external components R1, C1 and Q1. The slope of the ramp changes with the change in input voltage, which causes the duty cycle
to adjust much faster than the conventional fixed slope ramp method resulting in a better line transient response. Rectifier CR1 is used
to offset the ramp.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
18-PIN CERAMIC DIP
J-PACKAGE
Part No.
SG1529J/883B
S(31529J
SG2529J
SG3529J
Ambient
Temperature Range
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
O°C to 70°C
Connection Diagram
INV. INPUT
N.I.INPUT
asc. OUTPUT
+C.L. SENSE
-C.L. SENSE
[ii""1ap
[2
[3
[4
[5
R,. [ .
18·PIN PLASTIC DIP
N-PACKAGE
SG2529N
SG3529N
-25°C to 85°C
O°C to 70°C
18-PIN WIDE BODY
PLASTIC S.O.I.C.
OW-PACKAGE
SG2529DW
SG3529DW
-25°C to 85°C
O°C to 70°C
<;
[7
N.C.
PV
P +VIN
17
16
15 ]
14 ]
REF
E,
Ca
13] C.
12] E.
11 ] SHUTDOWN
F.F. [ 8
GROUND [~J COMPENSATION
INV. INPUT
N.I.INPUT
OSC. OUTPUT
+C.L. SENSE
,C.L. SENSE
R,
C,
F.F.
GROUND
IT
IT
IT
18
JJ N.C.
2
17
:IJ
3
16::IJ +VN
15 JJ E,
1
4
IT
IT
5
IT
6
IT
IT
7
IT
•
•
VRE.F
14;::0 Ca
13
CA
12:0 EA
11
SHUTDOWN
10
COMPENSATION
f:IJ
PJ
iJJ
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Sjlicon General • 11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4 -128
SG15321SG25321SG3532
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
PRECISION GENERAL-PURPOSE REGULATOR
DESCRIPTION
FEATURES
This monolithic integrated circuit is a versatile, general-purpose voltage
regulator designed as a substantially improved replacement for the popular
SG723 device. The SG1532 series regulators retain all the versatility of the
SG723 but have the added benefits of operation with input voltages as low as
4.5 volts and as high as 50 volts; a low noise, low voltage reference; temperature
compensated, low threshold current limiting; and protective circuits which
include thermal shutdown and independent current limiting of both the reference
and output voltages. A separate remote shutdown terminal is included. In the
duaJ-in-line package an open collector output is available for low input-output
differential applications.
•
•
•
•
•
•
These devices are available in both hermetic 14-pin cerdip and 1O-pin TO-96
packages. In the T-package, these units are interchangeable with the LAS1000 and LAS-11 00 regulators. The SG1532 is rated for operation over the
ambient temperature range of -55°e to 125°e while the SG2532 and SG3532
are intended for industrial applications of ooe to 70oe.
Input voltage range of 4.5V to 50V
2.5V low noise reference
Independent shutdown terminal
Improved line and load regulation
80mV current limit sense voltage
Fully protected including thermal
shutdown
• Useful output current to 150mA
HIGH RELIABILITY FEATURES
-SG1532
• Available to MIL-STD-883
• SG level "s" processing available
BLOCK DIAGRAM
VC*Cr------------------,
VOUT
Vz
CURRENT LIMIT
CURRENT SENSE
N.!. INPUT
INV. INPUT
SHUTDOWN
FREQ. COMP
V-
*
Vc IS INTERNALLY CONNECTED TO VIN FOR T PACKAGE
April 1990
4 -129
II
SG15321SG25321SG3532
ABSOLUTE MAXIMUM RATINGS (Note I)
Pulse (50 ms) Input Voltage from Y'N to V- .......................... 50V
Continuous Input Voltage from Y'N to V-............................... 40V
Input to Output Voltage Differential .................................... 40V
Maximum Ouiput Current .............................................., 250mA
Current from Vz (J, L-Package only) ................................ 100mA
Note 1.. Exceeding these ratings could cause damage to the device.
Current from VREF ............................................................... 25mA
Operating Junction Temperature
Hermetic (T, J, L-Packages) .......................................... l50°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
THERMAL DERATING CURVES
2.5
50l\l\
40~
2.0
~
~
I
15
Ii
~
m
is 1 0
i
~
<
~
~ ~r"o
~
"(10
>C;'l
0
0
25
50
75
"'1
'<74
i
"'~q,~
r
~
~~
125
'00
A~BIENT TE~PERA TURE
-
150
~
(
5
{~)
'.0,1'
05
,.'''~c~
~~
~~
"
~
~
<~ ~
~~
o
'0
"'liI
0
175
0
"C
25
50
75
100
CASE TEMPERAT\JRE -
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
~
125
150
175
"C
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage Range
SG15321SG2532 .................................................... 5V to 45V
SG3532 .................................................................. 5V to 36V
Output Current Range ........................................ 1rnA to 100mA
Note 2. Range over which the device is functional.
Reference Current ............................................................ 5mA
Zener Current (J & L-Packages only) .............................. 20mA
Operating Ambient Temperature Range
SG1532 ........................................................ -55°C to 125°C
SG25321SG3532 ................................................. O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1532 with -55°C ~ T. ~ 125°C, SG2532 with
O°C ~ T. ~ 70·C, SG3532 with O·C ~ T.::; 70·C, Y'N = 1OV, VOUT = 5V, and lour= 1mAo Low duty cycle pulse testing techniques are used which maintains
junction and case temperatures equal to the ambient temperature.)
5G153215G2532
5G3532
Parameter
Test Conditions
Units
Min. Typ. Max. Min. Typ. Max.
Input Voltage Range
4.5
TA = 25°C
50
4.5
40
V
4.7
50
4.7
40
V
Output Voltage Range
2.0
38
2.0
38
V
Max Output Current
175 250
175 250
rnA
Rsc = 0, VOUT = 0, TA = 25°C
V
1.7 2.0
1.7 2.0
lOUT = 100mA, TA = 25°C
Min (V'N - VOu-r)
Reference Voltage
TA=25°C
2.40 2.50 2.60 2.40 2.50 2.60
V
2.65 2.35
2.35
2.65
V
Temperature Stability (Note 4)
0.005 0.Q15
0.005 0.015 %/OC
15
Ref Short Circuit Current
VREF=O, TA=25°C
25
15
25
rnA
Line Regulation (Note 3)
8V SV ,N S 40V
0.005 0.Q1
0.005 0.02
%N
0.Q1 0.02
0.01 0:03 %N
8V S Y'N S 20V, lour = 25mA
Load Regulation (Note 3)
0.002 0.004
0.002 0.004 %/mA
1rnA S lOUT S 25mA
lmA S lour S 100mA
0.002 0.005
0.002 0.005 %/mA
Current Limit Sense Voltage
0.06 0.08 0.10 0.06 0.08 0.10
Rsc = lOOn, VOUT = OV
V
0.40 0.70 1.0 0.40 0.70 1.0
Shutdown Voltage Threshold
V
Shutdown Source Current
100 200 300 100 200 300
itA
"OUT = high
lOUT = lOrnA, (J and L-Packages only)
6.4
7.2
6.0
Zener Voltage
6.0
6.4 7.2
V
Standby Current
V,N = 40V
2.5
3.5
2.5
3.5
rnA
Error Amplifier Offset Voltage
2.0
10
2.0
mV
15
Error Amplifier Input Bias
Current
4.0
15
4.0
20
ItA
4 -130
SG1532/SG2532/SG3532
ELECTRICAL SPECIFICATIONS (continued)
Parameter
SG1532/SG2532
Test Conditions
Min.
66
=
Open Loop Gain
Ripple Rejection
Output Noise
Long Term Stability (Note 4)
Thermal Shutdown
T A 25°C
f = 120Hz, TA = 25°C
10Hz sf s 100KHz, TA
V IN =30V, TA = 125°C
Typ. Max. Min.
68
60
66
50
0.3
1.0
175
=25°C
SG3532
Typ. Max.
68
66
50
1.0
0.3
175
Units
dB
dB
j.1VRMS
%/Khr
°C
Note 3. Applies for constant junction temperature. Temperature drift effects must be taken into account separately when the unit is operating under
conditions of high dissipation.
Note 4. These parameters, although guaranteed, are not tested in production.
CHARACTERISTIC CURVES
VO=5V -'
.,...
-::(
E
.,>
3
w
'"«
:::J
U
TJ= 12S oC
>
...:::J
TJ= 2S oC
>-
-1000PF
-20
/
TJ-25 C
"J
w
a::
f\\ ~
60
'1N=10V
VCF5V
IL=lmA
u
w
-40
...J
Q.
Q.
n:
\ \
0
0
"0
,.,., /
-60
V
-80
100
10
CURRENT LIMIT SENSE VOLTAGE-(mV)
100
lK
10K
FREQUENCY-(Hz)
FIGURE 3.
CURRENT LIMITING
FIGURE 4.
RIPPLE REJECTION
4 ·131
lOOK
1M
II
SG15321SG25321SG3532
CHARACTERISTIC CURVES (continued)
VIN=10V
Vr:r 5V
I
IL=lmA
$'
ID
"0
Iii'
w
'I
z
40
«
'-'
w
180
'-'
20
'"
f--1
230
§;
280
0
'"'-'w
'I
w
~
'-'
z
'"
0
E
'I
z
F
0
w
W
III
+50
0
Q.
0
f--
::>
0
'~N-3y
I
~
5
0
r--~
-50
~N=10V.
Vr:r SV
lL=lmA,
Cc=1000PF
:::~
TJ=2SDC. Rsc:;=O
r-- f\.
LOAD RJSPONSE
l!.IL-l0mA
I
-50
'"
1\
LINE RESPONSE
I
Q.
100
lK
10K
o
1M
lOOK
5
10
15
20
FREQUENCY-(Hz)
FIGURE 5.
FREQUENCY RESPONSE
FIGURE 6.
TRANSIENT RESPONSE
APPLICATION INFORMATION
HIGH (3rP_N_P_ _ _ _ _ _ _ _ _ _,~, +VO
l
·5
'K
.,
+~N - - , - - - - - - - - - - - - - ,
Vc
Vo
~N
Vz
"REF
CL
N'
CS.
.,
lN4002
1.5K
Vc
Vo
~N
Vz
I
I
J
·SC
330n
1.00
7500
+
.,
Co
'00
so
'NV
V-
caMP
·4
750[1
MFa
1000pF
.,
Cc
.,
+
Co
'00
MFa
S10n
GNO
ONO -
-+-----<--+-- ONO
.........- - - - - - - -.....
FIGURE 8 - HIGH CURRENT REGULATOR WITH FOLDBACK
CURRENT LIMITING AND REMOTE SHUTDOWN
FIGURE 7 - 90% EFFICIENT LINEAR REGULATOR
Output Voltage - 5V
Min (VIN,VOUT) a12A ... D.4V
Load Reg D-2A = 20mV
+VO
S10D
500
GNO
·SC
050
Output Voltage = 5V
Max Output Current." SA
Min VIN at No Load = 6.9V
Min VN at SA = S.2V
Max Output Current = 3A
Une Reg 6-30V = 10 mV
Notes:
Line Reg 1D-30V .. 3mV
Load Reg 0-5A = 17mV
Short Circuit Current = 1.SA
Note:
100n surge limiting resistor should be used for output voltages
above BV.
For output voltages above 8V and load currents which allow PNP
basecurrentto be IImltedto25mA, the internal zener may be used,
eliminating the need forUle two external diodes and the divider on
VAEY-'
Rar: can be eliminated if the 200mA current limit on VOUT is
adequate. Overall current limiting Is dependent upon PNP Beta.
For greater accuracy. load currrent may be sensed In the ground
line.
4-132
SG15321SG25321SG3532
APPLICATION INFORMATION
+'N~---------------4~--~,
Vc
'0'0
1--------+
Vc
+VIN
Vo
Vz
'N
'-'REF
C L.
1--------+
CL.
",,,
"sC
cs I-------+-~-+VD
+VD
CS
so.
"
so
-
R,
-
~OOf'F
eND
FIGURE 9 - HIGH EFFICIENCY LOW VOLTAGE REGULATOR
Output Voltage = 5V
Max Output Current'" 9A
Min VIN at SA '" 7.0V
Cc
eND
FIGURE 10 - BASIC LOW CURRENT REGULATOR
Sense Voltage
I
VOUY "
"'~
R
R1 Rz sc
Co .1000 pF
R, "" 11,+R;
VREF~+~)
,
LIne Reg 7-20V .. 10mV
Load Reg 0-5A • 25mV
Constant Current Limiting
•
lour S 100mA
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Part No_
Package
14-PIN CERAMIC DIP
J- PACKAGE
10-PIN METAL CAN
T- PACKAGE
Ambient
Temperature Range
SG1532J/883B
SG1532J
SG2532J
SG3532J
-55°e to 125°e
-55°e to 125°e
ooe to 70 0 e
ooe to 70 De
SG1532T/883B
SG1532T
SG2532T
SG3532T
-55°e to 125°e
-55°e to 125°e
ooe to 70 0 e
ooe to 70 0 e
Connection Diagram
N.C.
CURRENT LIMIT
CURRENT SENSE
INVERTING INPUT
NON-INVERTING INPUT
VAEF
V-
(Notes 3 & 4)
-55°e to 125°e
-55°e to 125°e
Note 1. Contact factory for JAN and DESC product availablity_
2. All packages are viewed from the top.
Silicon
~eneral
•
P
P
P
P
CD
CURRENT SENSE
INVERTING INPUT
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
N.C.
CURRENT LIMIT
CURRENT SENSE
N.C.
INVERTING INPUT
N.C.
N. I. INPUT
VAEF
N.C.
V-
@I
®
FREO. COMPENSATION
®
0
®
®
V"'
SG1532U883B
SG1532L
N.C.
[ 2
13
FREQ. COMPENSATION
[ 3
12
V.
[ 4
11
Ve
[ •
10
Vwe
[89PV'l,
[~P SHUTDOWN
CURRENT LIMIT
NON-INVERTING
INPUT
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L-PACKAGE
[f1""714p
VtH & Vo
SHUTDOWN
0 ®® va"'
v-
3 2
1 20 19
'0"
·
,.
•
17
7
15
•
14
9 10 11 12 13
11.
12.
13.
14.
15.
16.
N.C.
SHUTDOWN
Vz
N.C.
Voor
N.C.
17. Vo
18. VIN
19. N.C.
20. FREQ. COMPo
Note 3_ Vzoutput is not available in T-package_
4_ Pin 5 is connected to case.
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4 -133
4 -134
SG1540/SG2540/SG3540
SILICON
GENERAL
OFF-LINE START-UP CONTROLLER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1540 is an integrated circuit designed to efficiently provide
start-up power from a high-voltage DC bus to a PWM control circuit
in a switching power supply. When used on the primary side, it
reduces start-up current to less than 1rnA and allows any standard
PWM control circuit to be used as a primary-side controller. When
used to power a controller on the secondary side, it efficiently
eliminates the need for a heavy 50/60Hz line transformer with its
associated low frequency magnetic fields.
• Useable with primary and secondary side PWM
controllers
• Mlcropower comparator / switch
- Internal 2.5V bandgap reference
- SOmA power switch
• Squarewave oscillator
- 500Hz to 200KHz operation
- 200mA totem pole outputs
• Eliminates bulky, expensive 50/60 Hz transformer
• Minimizes high voltage bleeder current
• Programmable start-up voltage and hysteresis
• Internal and programmable overvoltage crowbar
latch
• Available in 8 pin DIP, 10 pin flat pack, and 16 pin
widebody sOle
The circuit consists of three sections: a micropower bandgap
comparator/power switch referenced to 2.5 volts which isolates the
start-up capacitor from its load; a high frequency square-wave
oscillator with 200mA totem-pole output for driving an isolation
transformer; and a second bandgap comparator with latching
crowbar to protect against overvoltage faults while starting or
running.
HIGH RELIABILITY FEATURES - SG1540
The SG1540 is specified for operation over the full military ambient
temperature range of -55°C to 125°C. The SG2540 is characterized for the industrial range of -25°C to 85°C, and the SG3540 is
designed for the commercial range of ooe to 70°C.
• Available to MIL-STD - 883
• SG level "s" processing available
BLOCK DIAGRAM
START
}-----I+
HYSTERESIS
DC OUT
42V
OVERVOL TAGE
r-----t+
AC OUT
GROUND
+2.5V
TIMING
See Application Notes for additional information.
April 1990
4 -135
II
SG1540/SG2540/SG3540
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (+V,N) ...................................................... +37V
DC Output Current, Continuous (VOUT) .......................... 100mA
ACOutput Current, Continuous .................................... 200mA
Analog Inputs (Start and Overvoltage) ................ -0.3V to 6.0V
Analog Input Currents (V>8V) .......................................... 10mA
Overvoltage Crowbar Current, Continuous ...................... 50mA
Overvoltage Crowbar Energy (Y2CIJ2) ....•............................... 8mJ
Operating Junction Temperature
Hermetic (Y Package) ................................................ 150°C
Plastic (M, OW Packages) .............................. :........... 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................. 300°C
Note 1. Values beyond which damage may occur.
THERMAL DERATING CURVES
2.5,..--.-------,-,--,---,---r--,
50,..--;.-------,--,--,---,---r----,
2.0
4.01----iI---+--+--+--!---1---1
~
~
~
~
~
I
175
AMBIENT TEMPERA 1\JRE -
CASE TEMPERATURE - "C
'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage Range ................................................ 7V to 35V
DC Output Current, Continuous ......................... ..... 0 to SOmA
AC Output Current, Continuous ............................ 0 to 100 mA
Oscillator Frequency Range .......................... 1KHz to 400KHz
Timing Resistor Range ...................................... 2KQ to 150KQ
Timing Capacitor Range ...................................... 1nF to 20IJF
Operating Ambient Temperature Range
SG1540 .......................................................... -55°C to 125°C
SG2540 ............................................................ -25°C to 85°C
SG3540 ................................................................ O°C to 70°C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1540 with -55°C ~ T. ~ 125°C, SG2540 with
-25°C ~ T. ~ 85°C, SG3540 with O°C ~T. ~ 70°C, and +V'N = 15V. A O.lIlF high frequency bypass capacitor Is recommended on V'N. Low duty cycle
testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Start-up Section
Start Current Icc
Operating Current
Start Threshold
Start Bias Current
Start Clamp Voltage
Hysteresis ON Voltage
DC Output Section
VOUT Voltage
Short Circuit Current
Test Conditions
ISG1540/2540/35401 Units
I Min. Typ. Max. I
VpIN • =Oto5V
IpIN • = lmA
I.'N. = 100IJA
0.2 0.4
0.3 0.6
3
6
2.37 2.50 2.63
1
0.1
7
6
8
0.1
0.2
mA
mA
rnA
V
IJA
V
V
ISOURCE = lOrnA
ISOURCE = 50mA
VOUT=OV
12.5 13.5
12.0 13.0
50 100 225
V
V
rnA
VSTART = 0 to 2.37V
VnMING = +V,N; VOUT Open
Fosc = 50KHz, VOUT and AC OUT Open
4 -136
SG1540/SG2540/SG3540
ELECTRICAL SPECIFICATIONS (continued)
Parameter
ISG1540/2540/35401 Units
Min. Typ. Max.
Test Conditions
Oscillator Section (Note 3)
Initial Accuracy
Voltage Stability
Temperature Stability (Note 4)
Oscillator Minimum Frequency
Oscillator Maximum Frequency
AC Output Section
HIGH Output Voltage
46
TJ = 25°C
+V'N = 12 to 1BV
RT = 17.BK, CT= .06BIlF
T = 470pF
LOW Output Voltage
Squarewave Duty Cycle
AC Output Risetime
AC Output Falltime
Overvoltage Crowbar Section
Overvoltage Threshold
Overvoltage Bias Current
Overvoltage Clamp Voltage
+V,NOvervoltage Threshold
SCR ON Voltage
SCR Holding Current
1\ = 1.5K, C
400
ISOURCE = 20mA
ISOURCE = 100mA
ISINK =20mA
ISINK = 100mA
12.5
12.0
IVIN= 35mA
Vov =0
2.37 2.50 2.63
0.1
1
6
7
B
37
42
44
12
9
0.15 0.35 0.55
V
IlA
V
V
V
mA
Note 3. Fosc = 50KHz, RT = 3.48K CT = 4.7nF unless otherwise specified.
Note 4. These parameters, although guaranteed, are not tested in production.
CHARACTERISTIC CURVES
2.5
TJ-5~
~~
~~
L'
.,
",..
-~
",..
o
o
10
20
TJ=~50C
-
......I -
TJ~I~
30
~
40
--
Rt
50
10
100
lK
10K
Oscillator (Hz)
OUTPUT CURRENT-(mA)
FIGURE 1 • SATURATION VOLTAGE (DC OUT PIN) VS. OUTPUT CURRENT
FIGURE 2· OSCILLATOR FREOUENCY VS. R, AND C,
4 -137
KHz
%
%
KHz
KHz
0.3
2.0
55
0.6
0.2
45
13.5
13.0
0.2
1.2
50
0.3
0.1
54
12
5
1
V
V
V
V
%
Il S
Il S
CL = 1000pF
CL = 1000pF
Vo.v. = 0 to 2.37V
lo.v. = 1mA
50
5
2
lOOK
•
SG1540/SG2540/SG3540
APPLICATION INFORMATION
120/240
f'\.,
300-400VOC
VAC
SO/60HZ
RSTART
120V
SECONDARY
WINDING
C2
200VDC
CST RT
POWER
TRANSISTOR
FIGURE 3 - EFFICIENT PRIMARY SIDE START-UP
PRIMARY SIDE START-UP
When the design goal is efficient start-up for a control PWM referenced to the primary side of the power transformer, the configuration
in Figure 3 is recommended_ An energy storage capacitor CSTART is trickle-charged from the 300-400 Volt DC bus by resistor RSTART"
The value of RSTART is chosen to provide a constant 1mA charging current, allowing the use of a V2 watt resistor. As the voltage on CSTART
ramps up from zero, the only load current is the standby current of the SG1540 and that of the divider network R1-R3. (Connecting the
TIMING pin to +VIN disables the internal power oscillator and forces the circuitry into a micropower standby model. Since the input bias
current at the START pin is 11lA maximum, a divider current of 1OOIlA is adequate).
When the voltage at the START pin reaches +2.5 Volts, the hysteresis transistor turns off, overdriving the START pin. The VOUT pin is
switched to the HIGH state, providing power to the PWM control circuit. As energy flows out of the START capacitor, its voltage decays;
but it remains connected to the PWM circuit until the dropout voltage is reached (VSTART - VHYSTERESIS)' The bootstrap winding on the power
transformer and rectifier diode D5 prevent this from happening_ As the PWM control circuit becomes active, the power transistor begins
to switch, providing operating current to the PWM circuit through the SG1540.
RESISTOR CALCULATIONS
Given that VSTART and VDROPOUT have been chosen, and that the divider current at start-up is 1OOIlA, then the values for R1 through R3
are calculated as follows:
1_ For simplification, let X =
VSTART- 2.5
2.5
2. Then,R1 = 2.5 x 104 • X
R2 = R1N
and Y = VDROPOUT -2.5
2.5
and
R1' R2
R3 = X' R2 _ R1
[1]
[2]
[3]
DESIGN EXAMPLE
Suppose we have a power MOSFET device, and so want to start at +18 volts and drop out at +12 volts.
Then
Therefore
X = 6.20
andY = 3.80
R1 = 2.5 x 104' 6_2 = 155K
R2 = 1.5 x 10 5/3.8 = 39.5K
(Choose 150K)
(Choose 39K)
1.5 x 105 ' 3.9 x 104
R _
3 - 6.2' 3.9 x 104 _1.5 x 105 = 63.7K
(Choose 62K)
4-138
SG1540/SG2540/SG3540
APPLICATIONS INFORMATION (continued)
The voltage waveform at +V'N is shown in Figure 4 with these resistor values and with
before the +15 volt bootstrap winding becomes active.
CSTART
= 31JF. Notice that two tries are required
25
20
2:
w
'"«
./
15
f-
-.J
0
>
10
D-
/
:::0
I
f-
5
'"«
V
./
v"""
1
/
fU1
a
-5
V
/
;I
a
20
40
60
100
80
TIME
120
140
160
180
II
200
(ms)
FIGURE 4 - STARTUP VOLTAGE WAVEFORM
JOO-400VDC
Tp
Cl
200VDC
II
RSTART
II
T2
380K 1/2 WAn
Tp
120V
II
T1
C2
200'vUC
Cs
RT
FIGURE 5 - SECONOARY·SIDE START·UP WITHOUT A LINE TRANSFORMER
4-139
SG1540/SG2540/SG3540
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
8·PIN CERAMIC DIP
V-PACKAGE
Part No.
(See Notes Below)
Ambient
Temperature Range
to 125°C
to 125°C
to 85°C
ooe to 70°C
SG1540Y/883B
SG1540Y
SG2540Y
SG3540Y
-55°C
-55°C
-25°C
8-PIN PLASTIC DIP
M-PACKAGE
SG2540M
SG3540M
-25°C
16-PIN WIDE BODV
PLASTIC S.O.I.C.
OW-PACKAGE
SG2540DW
SG3540DW
-25°C to 85°C
OOeto 70°C
Connection Diagram
START
OVER VOLTAGE
Notes:
SG1540F/883B
SG1540F
7
+VIN
•
AC OUT
TIMING
4
5
GROUND
to 85°C
ooe to 70°C
-55°C
-55°C
to 125°C
to 125°C
DCOUT
2
3
START
N.C.
OVER VOLTAGE
N.C.
HYSTERESIS
N.C.
TIMING
N.C.
10-PIN HERMETIC
FLAT PACK
F-PACKAGE
0
HYSTERESIS
N.C.
START
OVERVOLTAGE
HYSTERESIS
TIMING
DC OUT
N.C.
+VIN
ACOUT
N.C.
GROUND
N.C.
DC OUT
+VIN
ACOUT
GROUND
1. Contact factory for JAN and DESC part availability.
2. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
4 -140
SG15421SG25421SG3542
SILICON
GENERAL
VOLTAGE SENSING CIRCUIT
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
This monolithic integrated circuit provides the control functions necessary to protect
sensitive electronic circuitry from over-voltage transients or the effects of voltage
regulator failure. It is designed for use with an external SeR "crowbar" for immediate shutdown of the power supply, but additionally provides logic level outputs for
regulator turn-off andfor operator or system out-of-tolerance indication.
• Operation from 4.5V to 40V
• Useful for 'either over- or undervoltage sensing
• SenSing threshold accurate to ±2%
• Built-in input hysterisis
• Zero to 35V sensing capability
• Programmable time delay
• SCR "Crowbar" drive of 200mA
• Remote activation capability
• 2.6V 1% reference available
This device contains an accurate, stable 2.6 volt reference which allows the sensing
threshold to be set predictably without the need for potentiometers. Uncommitted
availability of both polarity inputs to the sensing comparator allows a wide flexibility
of use including the ability to sense voltages less than the reference voltage. An
external capacitor can be used to program an accurate time delay between fault
occurrence and crowbar triggering, but this delay may be bypassed by inputing althe
Sense 2 terminal or by using the remote activation capability.
For additional circuit functions, see SG1543 data sheet.
HIGH RELIABILITY FEATURES
-SG1542
• Available to MIL-STD-883B
• SG level "S" processing available
BLOCK DIAGRAM
250J-lA
SCR
TRIGGER
+
ABOVE
LIMIT
WITHIN
LIMIT
COMMON
N.I.
SENSE 1
INV.
SENSE
DELAY
CURRENT
SENSE 2
REMOTE
ACTIVATE
See Application Notes for additional information.
April 1990
4 -141
•
SG15421SG25421SG3542
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (+V,N ).................................................. 40V
Collector Supply Voltage, Vc ............................................... 40V
Sense Voltage (1) ............................................................... +V'N
Sense Voltage (2) .................................:............................ 6.5V
Remote Activation Input Voltage ........................................ 7.0V
SCR Trigger Current (Note 2) ...........................:.............. 300mA
Limit Indicators Output Voltage ........................................... 40V
Limit Indicators Output Sink Current ................................ 50mA
Operating Junction Termperature
Hermetic (J, F Packages) ............................................. 150°C
Plastic (N, D Packages) ............................................... 150°C
Storage Temperature Range ............................. -65°C to 150°C
Note 1. Values beyond which damage may occur.
Note 2. At higher input voltages, a dissipation limiting resistor, RG ' is required. See Figure 1.
THERMAL DERATING CURVES
2.5 ; - - - - , ; - - - ; - . . . . . , . - - - , - - - , - - , - - . ,
6
i
is 2.0
~
1.01-----11----'
175
AMBIENT TEMPERATURE -
-c
CASE TEMPERA'TlJRE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Input Supply Voltage (+V,N ) .................................... 4.7V to 40V
Sense Voltage (1)
Common Mode Input Range ......................... OV to (+V,N ) -3V
Sense Voltage (2) ....................................................... 0 to 5.5V
Reference Load Current ........................................... 0 to 10mA
Indicator Output Voltage ......................................... 4.7V to 40V
Indicator Output Current ............................................ 0 to 10mA
Delay Timing Capacitor (Note 4) .................................... 0 to 11lF
Operating Ambient Temperature Range
SG1542 ......................................................... -55°C to 125°C
SG2542 ........................................................... -25°C to 85°C
SG3542 .............................................................. O°C to 70°C
Note 3. Range over which the device is functional and parameter limits are guaranteed.
Note 4. Larger value capacitor may be used with peak current limiting. See Figure 5.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1542 with -55°C ST. S 125°C, SG2542 with
-25°C,;; T. S 85°C, SG3542 with ooe,;; T.,;; 70°C, and +V'N = 10V. Low duty cycle testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
SG154212542
SG3542
Parameter
Test Conditions
Units
I Mln.1 Typ. Max. I Min. Typ. Max.
Supply Section
Input Voltage Range
4.5
V
40 4.5
TJ =25°C to TMAX
40
4.7
V
40 4.7
40
TMIN to TMAX
Supply Current
mA
+V,. =40V, Outputs open
5
7
5
10
Reference Section
Reference Voltage
V
2.58 2.60 2.62 2.55 2.60 2.65
TJ =25°C
V
2.55
Over Operating Temperature Range
2.65 2.50
2.70
+VIN ,"5t040V
Line Regulation
1
mV
1
5
5
Load Regulation
mV
1
15
1
15
IREF = 0 to 10mA
Short Circuit Current
mA
15 40
15 40
VREF=OV
%/oC
Temperature Stability
0.005
0.005
4 -142
SG15421SG25421SG3542
ELECTRICAL SPECIFICATIONS (continued)
Parameler
SG1542/2542
SG3542
U '1
IMin. Typ·iMax. Min. Typ. Max. I nI s
Tesl Conditions
Comparator Section
Sense 1 Offset Voltage
Input Hysteresis
Sense 1 Common Mode
Sense 1 Bias Current
Sense 2 Threshold
Sense 2 Bias Current
Delay Current
Limit Indicators VSAT
Limit Indicators Leakage
Propagation Delay
-20
SENSE 1 (+) rising, SENSE 1 INV. = 2.6V
0
2S
-20
20
0
(V,N )-3 0
-0.3 -l.S
-0.3
2.S0 2.60 2.70 2.S0 2.60
1.0
10
1.0
200 2S0 3S0 200 250
0.2 O.S
0.2
0.01 1.0
0.01
SOO
SOO
500
SOO
IL = lOrnA
V,ND = 40V
To Ind., TJ = 2SoC
To Trigger, T = 2SoC
SCR Trigger Section
Remote Activation Current
Remote Activation Threshold
Peak Output Current
Peak Output Voltage
Output Off Voltage
Output Current Rise Time
0.8
100
Vc=SV, RG=O, Vo=O
10 = 100mA
+V'N = 40V, RL = 1KO
RL = SOO, TJ = 2SoC
120
1.0
200
220
2.0
600
V,N -2.5 V,N ·1.6
0.8
100
20
0
2S
(V,N )·3
120
1.0
200
-l.S
2.70
10
3S0
O.S
1.0
220
2.0
600
V,N -2.5 V ,N -1.6
0.1
0.1
400
400
CHARACTERISTIC CURVES
c
100
Rc;>
0
'"
~
'"0
75
50
/
i=
0'
:J
i"
;.3
V
03
~
~
"z
1/
I~
25
o
/
o
V
/
I---f---+---+--~
0.1
I---f---+-----,~-___l
.01 I---f---.lf---+--___l
001
V
10
1.0
20
30
COLLECTOR VOLTAGE, Vc -
t--~'-----+---t--___l
.0001 ....._--'-_ _-'-_ _-'-_--'
.001
.01
0.1
1.0
10
40
v
DELAY TIME -
FIGURE 1 • MINIMUM GATE CURRENT LIMITING RESISTANCE
ms
FIGURE 2· ACTIVATION DELAY VS. CAPACITOR VALUE
SIMPLIFIED SCHEMATIC DIAGRAM - FIGURE 3
r--;--1-----..,-+----,r----+--r+-,---r--+---,--I-....,.-.,--------
L,.
--0:3
L. = Indicator selected for max_ current ~ 1OmA @ VTRIP
SCR = Selected for max_ peak current capability
FIGURE 4 - BASIC OVER-VOLTAGE PROTECTION CIRCUIT CONFIGURATION
The 100 ohm resistor limits the peak discharge current into the
SG1542 while the external PNP transistor provides a high
peak-current discharge path for the delay capacitor_
5G1542
DELAY
CDELAY
FIGURE 5 - SURGE LIMIT CIRCUIT FOR LARGE DELAY CAPACITORS
POWER SUPPLY OUTPUT VOLTAGE
LOW-CURRENT BIAS SUPPLY
+VIN
R1
VREF
Sf~fE
R2
Vc
A8V. lMT.
1
Sf!':'fE 1
WTH. LMT.
DELAY
REM. ACT.
SENSE 2
SCR
Rl
CROWBAR
TRIGGER
RG
R2
COM.
GROUND
V TRIP "" 2.6V (
R1+R2)
---"R2
FIGURE 6 - OVER-VOLTAGE SENSING FOR VOLTAGES ABOVE 2.6 VOLTS
+VIN
Vc
VREF
ABV. LMT.
smE 1
Sf!':'fE 1
WTH. lMT.
DELAY
REM. ACT.
SENSE 2
SCR
CROWBAR
TRIGGER
COM.
GROUND
VTRIP
=
2.6V
(Rl:~i)
FIGURE 7 - OVER-VOLTAGE SENSING FOR VOLTAGES lESS THAN 2.6 VOLTS
4-144
86154218625421863542
APPLICATION INFORMATION (continued)
POWER SUPPLY OUTPUT VOLTAGE
NEGATIVE POWER SUPPLY OUTPUT VOLTAGE
BIAS SUPPLY
R1
R2
+VIN
Vc
VREF
A8V. LMT.
smE
R1
Sf~yE 1
TRIGGER
REM. ACT
SENSE 2
Vc
VREF
ABV. LMT.
_
I-------=~---LMT.
smE 1 WTH.
S[~rE 1 TRIGGER
1 WTH, LMT.
DELAY
+YIN
CROWBAR
GROUND
VTRIP
R2
~ -2.6V~:~)
LOW INDICATE
REM. ACT.
DELAY
SCR
COM.
HIGH INDICATE
COM.
SENSE 2
GROUND
FIGURE 9 - UNDER-VOLTAGE SENSING
FIGURE 8 - OVER-VOLTAGE SENSING FOR NEGATIVE OUTPUT VOLTAGES'
• Without a positive bias supply, the basic QVP circuit on page 3 can be used equally well
with either positive or negative voltages.
POWER SUPPLY OUTPUT VOLTAGE
POWER SUPPLY VOLTAGE
BIAS SUPPLY
R1
Z1
+VIN
Vc
+VIN
Vc
VREF
ABV. LMT.
VREF
ABV. LMT.
sm E
WTH. LMT.
smE 1
WTH. LMT.
Sr~yE
TRIGGER
Sr::!yE 1
TRIGGER
DELAY
REM. ACT.
SENSE
COM.
R1
RG
R2
DELAY
SENSE 2
1K
REM. ACT.
COM.
R2
CD
GROUND
GROUND
FIGURE 10 - DELAYED THRESHOLD SENSE PLUS IMMEDIATE TRIP
FOR HIGH OVER-VOLTAGE
FIGURE 11 - OVER-VOLTAGE SENSING WITH MINIMUM TIME DELAY
POWER SUPPLY VOLTAGE
R1
+VIN
Vc
VREF
ABV. LMT.
Sr~yE 1 WTH. LMT.
Sf::!yE 1
DELAY
R2
SENSE 2
10K
1
TRIGGER
J,
1
" " Q1
+VIN
+VIN
ABV. LMT.
ABV. LMT.
REM. ACT.
REM. ACT.
COM.
REM. ACT.
I
COM.
RESET
COM.
1K
1K
~
TO ADDITIONAL
OVP CIRCUITS
I
GROUND
FIGURE 12 - OVER-VOLTAGE LATCH WITH RESET
FIGURE 13 -INTERCONNECTING MULTIPLE SG1542'5
Q1 must provide >2mA for each OVP circuit. With this arrangement, activation of any circuit
will activate all. For a master-slave relationShip, the WITHIN LIMIT terminal of the master may
be directly connected to the REMOTE ACTIVATE terminals of all the slaves.
4-145
SG15421SG25421SG3542
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
Part No.
14-PIN CERAMIC DIP
J - PACKAGE
(See Notes Below)
Ambient
Temperature Range
SG1542J/883B
SG1542J
SG2542J
SG3542J
-55°C to
-55°C to
-25°C to
O°Cto
125°C
125°C
85°C
70°C
14-PIN PLASTIC DIP
N- PACKAGE
SG2542N
SG3542N
-25°C to 85°C
O°Cto 70°C
14-PIN PLASTIC S.O.I.C.
D- PACKAGE
SG2542D
SG3542D
-25°C to 85°C
O°C to 70°C
Connection Diagram
v,
+VIN
DELAY CURRENT
SENSE 2
SENSE 1 N.I.
SENSE 1INV.
N.C.
v,
+VIN
DELAY CURRENT
SENSE 2
SENSE 1 N.I.
SENSE 1INV.
N.C.
14-PIN CERAMIC FLATPACK
F - PACKAGE (Note 3)
SG1542F/883B
SG1542F
-55°C to 125°C
-55°C to 125°C
v,
+VIN
DELAY CURRENT
SENSE 2
SENSE 1 N.I.
SENSE 1 INV.
SCRTRIGGER
v..,
COMMON
ABOVE LIMIT
REMOTE ACT.
WITHIN LIMIT
N.C.
SCRTRIGGER
VREF
COMMON
ABOVE LIMIT
REMOTE ACT.
WITHIN LIMIT
N.C.
SCRTRIGGER
v"'
COMMON
ABOVE LIMIT
REMOTE ACT.
WITHIN LIMIT
N.C. ------,-'--_ _- - ' - r - - - N.C.
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
3. Contact factory for product availability.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4 -146
SG15431SG25431SG3543
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
POWER SUPPLY OUTPUT SUPERVISORY CIRCUIT
DESCRIPTION
FEATURES
This monolithic integrated circuit contains all the functions necessary to monitor and
control the output of a sophisticated power supply system. Over-voltage (O.V.) sensing
with provision to trigger an external SCR "crowbar" shutdown; an under-voltage (U.V.)
circuit which can be used to monitor either the output or to sample the input line voltage;
and a third op amp/comparator usable for current sensing (C.L.) are all included in this
IC, together with an independent, accurate reference generator.
o
o
o
o
Both over and under-voltage sensing circuits can be externally programmed for minimum
time duration offault before triggering. All functions contain open collector outputs which
can be used independently or wire-ORed together; and although the SCR trigger is
directly connected only to the over-voltage sensing circuit, it may be optionally activated
by any of the other outputs, or from an external signal. The O.V. circuit also includes an
optional latch and external reset capability.
o
o
Over-voltage, under-voltage, and
current sensing circuits all
included
Reference voltage trimmed to 1%
accuracy
SCR "Crowbar" drive of 300mA
Programmable time delays
Open-collector outputs and
remote activation capability
Total standby current less than
10mA
HIGH RELIABILITY FEATURES
- SG1543
The current sense circuit may be used with external compensation as a linear amplifier
or as a high gain comparator. Although nominally set for zero input offset, a fixed
threshold may be added with an external resistor. Instead of current limiting, this circuit
may also be used as an additional voltage monitor.
~
~
Available to MIL-STD-883 and
DESCSMD
SG level "S" processing available
The reference generator circuit is internally trimmed to eliminate the need for external
potentiometers and the entire circuit may be powered directly from either the output being
monitored or from a separate bias voltage.
BLOCK DIAGRAM
U.V.
U.V.
SENSE
INDICATE
GROUND
O.V.
SENSE
S.C.R.
TRIGGER
O.V.
INDICATE
INV.
N.I.
ACTIVATE
(GROUND TO ACTIVATE)
OFFSET/COMP
See Application Notes for additional information.
April 1990
4 -147
SG1543/SG2543/SG3543
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (+V,N).................................................. 40V
Sense Inputs ....................................................................... +V'N
SCR Trigger Current (Note 2) .......................................... 300mA
Indicator Output Voltage ...................................................... 40V
Indicator Output Sink Current ........................................•.. 50mA
Operating Junction Temperature
Hermetic (J, F, L Packages) ......................................... 150°C
Plastic (N, OW Packages) ............................................ 150°C
Storage Temperature Range ............................. -65°C to 150°C
Note 1. Values beyond which damage may occur.
Note 2. At higher input voltages, a dissipation limiting resistor, RG ' is required. See Figure 1.
THERMAL DERATING CURVES
2.5...--r-----,---.,----.,---,..--,..-...,
i;
~
~
2.0
i
p.,.~-~~ ,--Pl.:~+--I----1--I
1.0 1--1----1--'<---""""-:"---"'~M---+----1
175
AMBIENT TEMPERATURE - "c
CASE TEMPERATURE -
-c
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Delay Timing Capcitor (Note 4) ...................................... 0 to 111F
Input Supply Voltage (+V ,N) .................................... 4.7V to 40V
Current Limit Common Mode
Operating Ambient Temperature Range
SG1543 ......................................................... -55°C to 125°C
Input Voltage Range ....................................... OV to +V'N -3V
SG2543 ........................................................... -25°C to 85°C
Reference Load Current ........................................... 0 to 10mA
SG3543 .............................................................. O°C to 70°C
Indicator Output Voltage ......................................... 4.7V to 40V
Indicator Output Current ............................................ 0 to 10mA
Note 3: Range over which the device is functional.
Note 4. Larger value capacitor may be used with peak current limiting. See Figure 7.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1543 with -55°C S; TA S; 125°C, SG2543 with
-25°C S; TA S; 85°C, SG3543 with ooe S; TA S; 70°C, and +V'N = 10V. Indicator outputs have 2Kn pull-up resistor. Low duty cycle testing techniques are
used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Test Conditions
Supply Section
InPIJi voltage RangEL
•
~
w
L .;. ~ .,
T J =25°C to TMAl(
4.5
4.7
•
SupPfy Current
Reference Section
Output Volf!lge } f :;
'Une Aeg~!~~ , ,'_ ~
Load Regulation
'Short
Temperature Stability
+V;N = 40V, Outputs open, T';' 25°C
','
CircuifO·urrent ..···
-
..
~
~,,,
..
'"
:
~~
"
"
40
7
40
10
4.5
4.7
40
7
40
10
V
V
mA
V
2.48 2.50 2.52 2.45 2.50 2.55
V
2.55 2.40
2.60
2.45
mV
1
1
5
5
mV
10
1
10
1
mA
12 25
40
12 25
40
%IOC
.005
:005
TJ = 25°C
. ... .,
SG154312543
SG3543
Units
Typ. Max. I Min. Typ. Max.1
I Min.
+V,N =5t030V.
IREF
to 10mA
VREF=OV
=.9
4-148
SG15431SG25431SG3543
ELECTRICAL SPECIFICATIONS (continued)
Parameter
SG3543
SG1543/2543
Units
I Min. Typ.IMax. Min. Typ. Max.
Test Conditions
Comparator Section
Input Threshold (Note 5)
2.45 2.50 2.55 2.40 2.50 2.60
2.40
2.65
2.60 2.35
25
25
0.3 1.0
0.3 1.0
0.2 0.5
0.2 0.5
8
6
8
6
200 250 300 200 250 300
0.2 0.5
0.2 0.5
1.0
.01
1.0
0.1
TJ = 25°C
Input Hysteresis
Input Bias Current
Delay Saturation
Delay High Level
Delay Charging Current
Indicate Saturation
Indicate Leakage
Propagation Delay
Sense input = OV
VD=OV
IL = 10mA
VIND = 40V
Vov. INPUT = 2. 7V, VU.V. INPUT = 2.3V , TJ = 25°C
CD = 0
CD = 11lF
SCR Trigger Section
Peak Output Current
Peak Output Voltage
Output Off Voltage
Remote Activate Current
Remote Activate Voltage
Reset Current
Reset Voltage
Output Current Rise Time
Prop. Delay from REM. ACT. Pin
Prop. Delay fom O.V. INPUT Pin
Current Limit Section
Input Voltage Range
Input Bias Current
Input Offset Voltage
CMRR
AVOL
Output Saturation
Output Leakage
Small Signal Bandwidth
Propagation Delay
400
10
+VIN = 5V, RG = 0, Va = 0
+VIN = 15V, 10 = 100mA
+VIN =40V, RL = 1KO
REM. ACT. pin = Gnd
REM. ACT pin open
RESET pin = Gnd, REM. ACT. = Gnd
RESET pin open, REM. ACT. = Gnd
RL = 500, T J = 25°C, CD = 0
VREM.ACT. = 0.4V
Yo' NPIIT = 2.7V
100
12
400
V'N- 3V 0
1.0
10
120 70
60
72
0.5
1.0
0.3
0
100
70
80
0.2
.01
5
200
80
60
72
100
12
0.1
0.8
6
0.8
6
0
OFFSET/COMP pin open, VCM = OV
OFFSET/COMP pin open, VCM = OV
10kO from OFFSET/COMP pin to Gnd
o $VCM $ 12V, VIN =15V
OFFSET/COMP pin open, VCM = OV
IL = 10mA
VIND = 40V
Av = OdB, TJ =25°C
VOVERDRIVE = 100mV, T =25°C
200
13
0
0.4
2
0.4
2
400
300
500
0.3
0
100
70
80
0.2
.01
5
200
Note 5. Input voltage rising on O.V. Input and falling on U.V. Input.
CHARACTERISTIC CURVES
1.0
.-----r---1----,/~
c
:\"
0.1 1---+--+--~"-----1
150
~
DELAy=25C
~
/
'e
I--------I---"/~
=
.01
10mS/,.F
.001/
5
10
15
20
25
30
35
.0001
.001
40
.01
0.1
1.0
DELAY TIME-(ms}
VIN SUPPLY VOLTAGE-(V)
FIGURE 1.
SeR TRIGGER POWER LIMITING
FIGURE2.
ACTIVATION DELAY VS. CAPACITOR VALUE
4 -149
ns
ms
400
10
200
13
0
0.4
2
0.4
2
400
300
500
10
V
V
mV
IlA
V
V
IlA
V
IlA
400
0.1
0.8
6
0.8
6
V'N 3V
1.0
15
130
0.5
1.0
mA
V
V
mA
V
mA
V
mAillS
ns
ns
V
IlA
mV
mV
dB
dB
V
IlA
MHz
ns
II
SG15431SG25431SG3543
CHARACTERISTIC CURVES (continued)
III I
II II
OVER-VOLTAGE
INPUT
200
$'
E
UNDER-VOlTAGE
INPUT
~
~
g
•
2.46 2.48
~
~
i!'
10
7
5
~
lK
2.50 2.52 2.54
V~~: ~~~---=
"'\
30
20
~
2.50
I'
100
70
50
\.
""\.
.3K 5K 10K
30K SDK JM
"'1
..3M.5M 1M
RT, THRESHOLD SETTING RESISTOR-(O)
SENSE INPUT VOLTAGE-(V)
FIGURE 3.
COMPARATOR INPUT HYSTERESIS
FIGURE 4.
CURRENT LIMIT INPUT THRESHOLD
80
VIN .. 10V
'i
I
m
Z
"
tJ
.~
"'-'tJ
~
>
is
'3
i'5
RL" 2t<1l
~
"(
70
TJ .. 25CC
60
180
'-'
60
~
40
270
20
360
.
i'5
is
0
40~--~~--~----~--~~
100
10k
1k
100k
1M
FREQUENCY-(Hz)
FREQUENCY-(Hz)
FIGURE 6.
CURRENT LIMIT AMPLIFIER FREQUENCY RESPONSE
FIGURES.
CURRENT LIMIT AMPLIFIER GAIN
APPLICATION INFORMATION
SG1543
~II r--+--l
DELAY
CDELAY
6~JUT--------'i r L...J
FIGURE 7 - SURGE LIMIT CIRCUlT FOR LARGE DELAY CAPACITORS
OFf
ON
FIGURE 8 - INPUT LINE MONITOR
The 100 ohm resistor limits the peak discharge current into the
SG1543 while the external PNP transistor provides a high peakcurrent discharge path for the delay capacitor.
4-150
'-'
z
<
~:J:
0
'3
50
f"(
..
SG15431SG25431SG3543
APPLICATION INFORMATION (continued)
The values for the external components are determined as follows:
Current limit input threshold, VTH = 1~00
1
Cs is determined by the current loop dynamics
V +~
V (~
R ;)
Peak current to load, I. =~
Short circuit current, Ise = ~
..
se
2.5 (R +R +R )
Low output voltage limIt, Vo (Low) _
R\R' 6
High output voltage limit, V0 (High) =2.5
(R4~R.+R6)
•
Voltage sensing delay, '" = 10,000 Co
FIGURE 9 • TYPICAL APPLICATION CIRCUIT
R; 5
SCR trigger power limiting resistor, RG >V
•
~LApSPLY=----------'---TO SG139 COMPARATORS
MAIN
POSITIVE
SUPPLY
------------------1
.,
SG1543
I
I
I
I
.2
.3
GROUND
ADDITIONAL
R4
_..-_ _ _ _ _ _
T
1
POSITIVE --tV'vSUPPLY
R5-!-
N~~~~~-------~.~.~-~~
VOLTAGE
~
I
FIGURE 10· SENSING MULTIPLE SUPPLY VOLTAGES
MAIN SUPPLY BUS _ -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,--_
BIAS VOLTAGE - - - - - - - - - - - - ,
r---------I
I
I
I
I
S.C.R.
"CROWBAR"
SUPP~~T~~~ _-_~.....R " S C f I r _ + - - - - - - - - - - - - - - - - - - - -.....~_
FIGURE 11 • OVERCURRENT SHUTDOWN
4 -151
8G1543/8G2543/8G3543
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
16-PIN CERAMIC DIP
J-PACKAGE
Part No.
SG1543J/883B
SGl543J
SG2543J
·SG3543J
Ambient
Temperature Range
-55°C to
-55°C to
-25°C to
DOC to
125°C
125°C
85°C
7Doe
16-PIN PLASTIC DIP
N- PACKAGE
SG2543N
SG3543N
-25°C to 85°C
DOC to 7Doe
16-PIN WIDE BODY
PLASTIC S.O.l.C.
DW-PACKAGE
SG2543DW
SG3543DW
-25°C to 85°C
DOC to 7Doe
16-PIN CERAMIC
FLAT PACK
F- PACKAGE
(Note 3)
SG1543F/883B
SG1543F
-55°C to 125°C
-55°C to 125°C
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L-PACKAGE
(Note 3)
SG1543U883B
SG1543L
-55°C to 125°C
-55°C to 125°C
Connection Diagram
S.C.R. TRIGGER
REMOTE ACTIYATE
RESET
O.Y.INDICATE
O.Y. DELAY
O.Y.INPUT
U.Y.INPUT
U.Y. DELAY
+Y.
VREF
GROUND
C.L.OUTPUT
OFFSET/cOMP
C.L. N.I. INPUT
C.L. INY. INPUT
U.Y. INDICATE
S.C.R. TRIGGER
REMOTE ACTIYATE
RESET
O.Y.INDICATE
O.Y.DELAY
O.Y.INPUT
U.Y.INPUT
U.Y.DELAV
+V'N
VREF
GROUND
C.L.OUTPUT
OFFSET/COMP
C.L. N.I. INPUT
C.L. INY. INPUT
u.v. INDICATE
S.C.A. TRIGGER
REMOTE ACTIYATE
RESET
O.Y. INDICATE
O.Y. DELAY
O.Y.INPUT
U.Y.INPUT
U.Y. DELAY
1. N.C.
2.
SCR TRIGGER
3. REMOTE ACTIVATE 4
4. R E S E T .
5. O.Y. INDICATE
•
6.N.C.
7. O.Y. DELAY
7
B. O.Y. I N P U T .
9. U.Y. INPUT
10. u.v. DELAY
+V'N
VREF
GROUND
C.L.OUTPUT
OFFSET/COMP
C.L. N.I.INPUT
C.L. INY. INPUT
u.v. INDICATE
0'
2 :1: 20 1.
~
,.
17
,.
,.
14
9
10 11 12 13
11.N.C.
12. U.Y.INDICATE
13. C.L. INY. INPUT
14. C.L. N.I.INPUT
15.0FFSET/COMP
16. N.C.
17. C.L. OUTPUT
lB. GROUND
19. VREF
20,+V'N
Note 1. Contect factory for JAN and DESC product aYaiiablity.
2. All packages are viewed from the top.
3. Consult factory for product availability.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4 -152
SG15441SG25441SG3544
SILICON
GENERAL
LOW-VOLTAGE SUPERVISORY CIRCUIT
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
This device was designed to provide all the operational features of the SG1543/
2543/3543 devices but with the added advantage of uncommitted inputs to the
voltage sensing comparators. This allows monitoring of voltage levels less than
2.5 volts by dividing down the internal reference supply.
• Uncommitted comparator inputs for
wide input flexibility
• Common-Mode range from zero to near
supply voltage
• Reference voltage trimmed to 1%
accuracy
• Over-voltage, under-voltage, and current
sensing circuits all included
• SCR "Crowbar" drive of 3DDmA
• Programmable time delays
• Open-collector outputs and remote
activation capability
• Total standby current less than 1DmA
In all other respects, the SG1544 series is identical to the SG1543 series. These
monolithic devices contain all the functions necessary to monitor and control the
output of a sophisticated power supply system. Over-voltage sensing with
provision to trigger an external SCA "crowbar" shutdown; an under-voltage circuit
which can be used to monitor either the output or sample the input line voltage; and
a third op amp/comparator usable for current sensing are all included in this IC,
together with an independent, accurate reference generator.
The voltage-sensing input comparators are identical and can be used with
threshold levels from zero volts to (V'N - 3V). Each has approximately 25mv of
hysteresis which is offset so the switching differential threshold is zero on the noninverting input for rising levels and zero on the inverting input for falling signals. All
other operating characteristics are as described in the SG1543 data sheet and
application note.
HIGH RELIABILITY FEATURES
- SG1544
• Available to MIL-STD-883 and DESC
SMD
• SG level "5" processing available
BLOCK DIAGRAM
INV.
N.I.
INV.
N.!.
S.C.R.
TRIGGER
O.V.
TRIGGER
INV.
N.I.
OFFSET/CaMP
April 1990
See Application Notes for additional information.
4-153
•
SG15441SG25441SG3544
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (+V ,N ) ................................................. 40V
Sense Inputs ....................................................................... +V'N
SCR Trigger Current (Note 2) .......................................... 300mA
Indicator Output Voltage ...................................................... 40V
Indicator Output Sink Current ........................................... SOmA
Operating Junction Temperature
Hermetic (J Package) ................................................... 150°C
Plasitc (N, DW Packages) ............................................ 150°C
Storage Temperature Range ............................ -65°C to 150°C
Note 1. Values beyond which damage may occur.
Note 2. At higher input voltages, a dissipation limiting resistor, RG ' is required. See Figure 1.
THERMAL DERATING CURVES
2.5 , - - , - - , - - , - - , - - , - - , - - - - - ,
~
~
~
~
~~
"~
0
~
<
6
6
~
i
175
175
AMBIENT TEMPERATURE -
CASE TEMPERATURE -
'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
·c
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Input Supply Voltage (+V ,N ) ..................................... 4.7V to 40V
Current Limit Common Mode
Input Voltage Range ........................................ OV to +V'N -3V
Reference Load Current ............................................ 0 to 10mA
Indicator Output Voltage ......................................... 4.7V to 40V
Indicator Output Current ............................................ 0 to 10mA
Delay Timing Capcitor (Note 4) ...................................... 0 to IIlF
Operating Ambient Temperature Range
SG1544 .......................................................... -55°C to 125°C
SG2544 ............................................................ -25°C to 85°C
SG3544 ............................................................... O°C to 70°C
Note 3: Range over which the device is functional.
Note 4. Larger value capacitor may be used with peak current limiting. See Figure 1.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1544 with ·55'e ,; TA ,; 125'e, SG2544 with
-25°C,; TA ,; 85'e, SG3544 with o'e,; TA ,; lO'e, and +V'N = 10V. Indicator outputs have 2kQ pull-up resistors. All electrical ratings and specifications
are tested with the inverting over-voltage input and the non·inverting under-voltage input externally connected to the 2.5V reference. Low duty cycle
testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Supply Section
Input Voltage Range
Supply Current
Reference Section
Output Voltage
Line Regulation
Load Regulation
Short Circuit Current
Temperature Stability
Test Conditions
TJ =25°C to TMAX
4.5
4.7
+V," =40V, Outputs open
TJ
SG1544/2544
SG3544
U ·t
Typ. Max. I Min. Typ. Max. I m s
I Min.
=25°C
7
40
40
10
4.5
4.7
7
40
40
10
2.48 2.50 2.52 2.45 2.50 2.55
2.45
2.55 2.40
2.60
1
5
1
5
1
10
1
10
12
25
40
12
25
40
.005
.005
+V'N =5 to 30V
IREF =0 to 10mA
VREF =OV
4-154
V
V
mA
V
V
mV
mV
mA
%/OC
8G154418G254418G3544
ELECTRICAL SPECIFICATIONS (continued)
Parameter
SG1544/2544
SG3544
U It
Min. Typ. Max. I Min. TYP.I Max. I n s
Test Conditions
Comparator Section
Input Threshold (Note ,5)
TJ = 25°C
Input Hysteresis
Input Bias Current
Delay Saturation
Delay High Level
Delay Charging Current
Indicate Saturation
Indicate Leakage
Propagation Delay
Sense input = OV
Vo=OV
IL = 10mA
V,NO = 40V
VO.V.NI.IN = 2.7V, VU.V.INV.IN = 2.3V, TJ = 25°C
Co=O
Co =l1lF
SCR Trigger Section
Peak Output Current
Peak Output Voltage
Output Off Voltage
Remote Activate Current
Remote Activate Voltage
Reset Current
Reset Voltage
Output Current Rise Time
Prop. Delay from REM. ACT. Pin
Prop. Delay fom O.V. N.I. IN Pin
Current Limit Section
Input Voltage Range
Input Bias Current
Input Offset Voltage
CMRR
AVOL
Output Saturation
Output Leakage
Small Signal Bandwidth
Propagation Delay
2.45 2.50 2.55 2.40 2.50 2.60
2.65
2.40
2.60 2.35
25
25
0.3 1.0
0.3 1.0
0.2 0.5
0.2 0.5
8
6
8
6
200 250 300 200 250 300
0.2 0.5
0.2 0.5
.01 1.0
0.1 1.0
400
10
100 200
12
13
0
0.4
2
0.4
2
400
300
500
+V,N =5V, RG=O, Vo=O
+V'N = 15V, 10 = 100mA
+V'N= 40V, RL = lKn
REM. ACT. pin = Gnd
REM. ACT pin open
RESET pin = Gnd, REM. ACT. = Gnd
RESET pin open, REM. ACT. = Gnd
RL = 50n, TJ = 25°C, Co = 0
VREM,ACT. = O.4V
~.v. N.I. IN~UI = 2.7V
0
OFFSET/COMP pin open, VCM = OV
OFFSET/COMP pin open, VCM = OV
1on from OFFSET/COMP pin to Gnd, TJ = 25°C
0:;; VCM :;; 12V, V,N = 15V
OFFSET/COMP pin open, VCM = OV
IL = 10mA
V,NO = 40V
Av = OdB, TJ = 25°C
VOVERORIVE = 100mV, TJ = 25°C
80
60
72
0.3
0
100
70
80
0.2
.01
5
200
0.1
0.8
6
0.8
6
100 200
12
13
0
0.4
2
0.4
2
400
300
500
V'N3V 0
1.0
10
120 70
60
72
0.5
1.0
0.3
0
100
70
80
0.2
.01
5
200
!1A
V
!1A
ns
ms
400
10
400
V
V
mV
IlA
V
V
400
0.1
0.8
6
0.8
6
V'N3V
1.0
15
130
0.5
1.0
mA
V
V
mA
V
mA
V
mAills
ns
ns
V
!1A
mV
mV
dB
dB
V
!1A
MHz
ns
Note 5. Input voltage rising on O.V. N.I. INPUT and falling on U.V. INV. INPUT.
APPLICATION INFORMATION
SG1544
100 [)
DELAY
CDELAY
T
1
::1-;2907
-
FIGURE 1 • SURGE LIMIT CIRCUIT FOR LARGE DELAY CAPACITORS
The 100 ohm resistor limits the peak discharge current into the SG 1544 while the external PNP transistor provides a high peak-current
discharge path for the delay capacitor.
4 -155
SG15441SG25441SG3544
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
18-PIN CERAMIC DIP
J-PACKAGE
Part No.
Ambient
Temperature Range
SG1544J/883B
SG1544J
SG2544J
SG3544J
-55°e to 125°e
-55°e to 125°e
-25°e to 85°e
ooe to 700 e
18-PIN PLASTIC DIP
N- PACKAGE
SG2544N
SG3544N
-25°e to 85°e
ooe to 700 e
18-PIN WIDE BODY
PLASTIC S.O.I.C.
OW-PACKAGE
SG2544DW
SG3544DW
. -25°e to 85°e
ooe to 70 0 e
Connection Diagram
SCR TRIGGER
[f"1'='1ap
REMOTE ACTIVATE [ 2
RESET
O.V.INDICATE
O.V. DELAY
O.V. N.I.INPUT
O.V.INV.INPUT
U.V. N.I.INPUT
U.V.INV.INPUT
SCR TRIGGER
. REMOTE ACTIVATE
RESET
O.V. INDICATE
O.V. DELAY
O.V. N.I. INPUT
O.V.INV.INPUT
U.V. N.I.INPUT
U.V. INV. INPUT
0:
0:
0:
0:
0:
0:
0:
0:
0:
+V.
PV
16 P GROUND
15 P C.L. OUTPUT
14 P OFFSET I COMP
13 P C.L. N.I. INPUT
12 P C.L.INV.INPUT
17
REF
[3
[4
[5
[6
[7
[.
11
U.V. INDICATE
[~jJ U.V. DELAY
P
FD
1
18
2
3
17~
VPE.F
16
15
14
13
GROUND
C.L. OUTPUT
OFFSET I COMP
C.L. N.I. INPUT .
4
5
6
7
•
•
iTI
iTI
iTI
iTI
12 tTI
11 iTI
10
PJ
+v~
C.L. INV. INPUT
U.V. INDICATE
U.V. DELAY
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4-156
8G154818G254818G3548
SILICON
GENERAL
QUAD POWER FAULT MONITOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1548 is an integrated circuit capable of monitoring up to four
positive DC supply voltages simultaneously for overvoltage and undervoltage fault conditions. An on-chip inverting op amp also allows
monitoring one negative DC voltage. The fault tolerance window is
accurately programmable from ±5% to ±40% using a simple divider
network on the 2.5V reference. A single external capacitor sets the
fault indication delay, eliminating false outputs due to switching noise,
logic transition current spikes, and short-term AC line interruptions. An
additional comparator referenced to 2.5V allows the AC line to be
monitored for undervoltage conditions or for generation of a line clock.
The comparator can also be used for programmable undervoltage
lockout in a switching power supply. Uncommitted collector and
emitter outputs permit both inverting and non-inverting operation.
External availability of the preCision 2.5V reference and open-collector
logic outputs permit expansion to monitor additional voltage using
available open-collector quad comparators.
•
•
•
•
•
•
•
•
•
•
Monitors four DC voltages and the AC line
Precision 2.5V ±1% low-drift reference
Fault tolerance adjustable from ±5% to ±40%
±3% trip threshold tolerance over temperature
Separate 10mA, 40V overvoltage, undervoltage
and AC line fault outputs
Fault delay programmable with a single capacitor
30mV comparator hysteresis to prevent oscillations
On-chip Inverting op amp for negative voltage
Open-collector output logic or expandabillty
Operation from 4.5V to 40V supply
HIGH RELIABILITY FEATURES - SG1548
• Available to MIL-STD-883
• Radiation data available
• SG level "5" processing available
BLOCK DIAGRAM
DELAY
LINE SENSE
COLLECTER
OUTPUT
2.50V
6.5V
EMITTER
OUTPUT
~
FAULT
SENSE 1
SENSE 2
SENSE 3
SENSE 4
INVERTER
OUTPUT
INVERTER
INPUT
ONDER VOL IAGE
:;;J
FAULT
-
+
LOWER
THRESHOLD
Aprll1990
See Application Notes for additional information.
4 -157
S615481S625481S63548
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (+V ,N) .......................................................... 40V
FalJlt Output Collector Voltage ............................................ 40V
Sense Input Voltage Range ........... ...................... -0.3V to 6.0V
Fault Output Sink Current ................................................ 20mA
Line Sense Input Current ................................................. ±1 mA
Inverting Op Amp Input Curreni ........................................ -5mA
Note 1. Values beyond which damage may occur.
THERMAL DERATING CURVES
Inverting Op Amp Output Current ..................................... 25mA
Operating Junction Temperature
Hermetic (J, L Packages) ............................................. 150°C
Plastic (N, DW Packages) ............................................ 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature ........................................................... 300°C
50~
25
2.0
~
~
'"
is
~
~
.i5
10
,,-
~~
"
~
5
~
~4..,
'~
'.
:}.o
;J
(C
~
~
:?
?..,J"~
C'~.o
",(1(1....17.
~
4..,
'''-~
~'\t.o
:;«-0
~Q
1-
iii
"'At1'~cc
05
'\~
,,~
'30~r.,.11~ (~
~-t ~4.o
r-~
~+
•. 0 '
«.0",
r,.
1'<>0)
0
0
25
50
75
100
125
150
0
175
~
~o/I~'
10
0
25
50
75
100
125
150
175
AMBIENT TEMPERATURE - 'C
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage Range
±25% Maximum Fault Window (Nole 3) ............... 4.5V to 35V
±40% Maximum Fault Window ............................ 5.0V to 35V
Lower Threshold Input Range .............................. 1.5V to 2.45V
Fault Tolerance Window Range ........................... ±5% to ±40%
Fault Output Sink Current Range .............................. 0 to 10mA
Note 2. Range over which the device is functional.
Line Sense Output Current Range ............................ 0 to 10mA
Voltage Reference Output Current ............................ 0 to 10mA
Operating Ambient Temperature Range
SG1548 ......................................................... -55°C to 125°C
SG2548 .................................... ....................... -25°C to 85°C
SG3548 ............................................................... O°C to 70°C
Note 3. Limited by inverter amplifier positive swing at -55°e.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1548 with -55°e "
125'e, SG2548 with
-25°e"
85'e, SG3548 with o'e"
70 0 e, and +V'N = 15V. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
SG1548/2548
SG3548
Units
Parameter
Test Conditions
Min. Typ. Max. I Min. Typ. Max. I
Supply Section
Supply Current
4.8 10 I
mA
4.8 10
I +V'N= 40V
Reference Section (Note 4)
Output Voltage
2.475 2.500 2.525 2.475 2.500 2.525 V
TJ = 25°C
2.450
Over Temperature
2.550 2.450
2.550 V
mV
1
Line Regulation
5
1
5
+V'N = 4.5V to 35V
mV
Load Regulation
3
IL = Oto 10mA
10
3
10
Short Circuit Current
10 25
mA
40
10 25
40
VREF=OV
Fault Window Generator Section
Input Bias Current
-0.4 -2.0 I (.IA
VD ," = 1.5V to 2.45V
-0.4 I -2.0 I
I
DC Sense Inputs Section
2.547 2.625 2.704 2.547 2.625 2.704 V
Overvoltage Threshold
VpIN1 = 0.95 X VREF
3.396 3.500 3.606 3.396 3.500 3.606 V
VpIN1 = 0.60 X VREF
Undervoitage Threshold
VPIN1 = 0.95 X VREF
2.304 2.375 2.447 2.304 2.375 2.447 V
1.455 1.500 1.545 1.455 1.500 1.545 V
VpIN1 = 0.60 X VREF
Input Bias Current
±0.6 ±2.0
±0.6 ±2.0 (.IA
VSENSE = 1.5V to 3.5V
dB
Threshold Supply Rejection
60 100
60 100
+V'N = 4.5V to 35V
Note 4. IL = OmA
T."
T. "
T."
4-158
SG15481SG25481SG3548
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Fault Delay Section
Comparator Threshold
Comparator Hysteresis
Delay Charging Current
On Saturation Voltage
OFF Clamp Voltage
Inverting Op Amp Section (Note 5)
Input Offset Voltage
Input Bias Current
Output High Voltage
Output Low Voltage
Large Signal Voltage Gain
Output Source Current
Power Supply Rejection Ratio
AC Line Sense Section
Comparator Threshold
Comparator Hysteresis
Input Bias Current
Collector Leakage Current
Collector Saturation Voltage
Emitter Output Voltage
Diode Clamp Voltage
Test Conditions
SG1548/2548
SG3548
U It
Typ. IMax. I Min. Typ. Max. I n s
IMin.
1.200 1.250 1.300 1.200 1.250 1.300
25
25
32.5 50 67.5 32.5 50 67.5
0.1 0.2
0.1 0.2
+3.2 +3.6
+3.2 +3.6
VplNa = OV
IplNa = OmA
IplN , = OmA
3.2
ISOURCE = 5mA
ISINK = 5mA
Rl = 10K
72
5
72
+V = 4.5V to 35V
2
15
-0.3 -1.0
3.5
1.0 1.9
100
15
25
100
3.2
72
5
72
15
2
-0.3 -1.0
3.5
1.0 1.9
100
25
15
100
2.440 2.500 2.560 2.440 2.500 2.560
25
25
1
2
1
2
10
1
10
1
0.2 0.5
0.2 0.5
13
12
13
12
7.5
7.5 6.0
6.0
-1.0 -0.3
-1.0
-0.3
VPIN5 = Low to High
VpIN5 = 2.5V
VeE =40V
le= 10mA
IE = 10mA
IpIN5 = lmA
IpIN5 = -lmA
Fault Logic Outputs (Each output)
Collector Leakage Current
Ve=40V
Collector Saturation Voltage
10 = 10mA
1
0.2
10
0.5
1
0.2
10
0.5
V
mV
IlA
V
V
mV
IlA
V
V
dB
mA
dB
V
mV
J.!A
J.!A
V
V
V
V
IlA
V
Note 5. +V'N = 4.5V.
APPLICATION INFORMATION
SETTING THE FAULT TOLERANCE WINDOW
MONITORING A NEGATIVE VOLTAGE
The fault tolerance window is set by applying a voltage less than
the +2.50Vreference to the Lower Threshold input (Pin 1). The
voltage is obtained by a resistor divider from the reference (Pin 3)
to ground. If ±5% tolerance is desired, then 95% of the reference
(+2.375V) is applied to Pin 1. If ±40% is wanted, then 60% of the
reference (+ 1.50V) is applied. In the example on the back page,
the tolerance is ±5%. The nominal overvoltage and undervoltage
thresholds are centered about the reference at +2.625V and
+2.375V (+2.500V ±0.125V).
A negative voltage can be converted to a positive one and
simultaneously scaled to +2.50V by using the internal operational
amplifier as an inverter. Only an input resistor and feedback
resistor are required.
SCALING THE MONITORED SUPPLY VOLTAGES
Each positive voltage to be monitored is divided down to +2.50V
with a resistor network and connected to one of the Sense inputs.
Unused Sense inputs should be connected to the reference. This
will not increase the bias current. A variation of the monitored
voltages out of the programmed tolerance range will cause the
appropriate overvoltage or undervoltage fault output to switch
LOW. The effective tolerance on any input may be broadened
with an additional resistor to the voltage reference. The example
on the back page shows a ±10% tolerance on the +5Vsupply
although the SG1548 is programmed for a ±5% tolerance. The
procedure for calculating the resistor value is found in the SG1548
Application Note.
SETTING THE FAULT DELAY
A single capacitor at the Delay pin sets the time an out-oftolerance fault must persist before a fault is actually declared.
This feature allows switching noise on the supplies to be rejected.
The delay time is given by: Delay = 25ms/J.!F .
AC LINE MONITORING
The AC line voltage can be monitored for single-cycle dropouts
with the few components shown in the example. A half-wave
rectifier charges the capacitor on positive line cycles. After the
positive peak and during the negative line cycle the capacitor
discharges from a fixed voltage controlled by the internal Zener
diode. If a positive cycle is missing, the capacitor discharges to
below the +2.5V trip point of the comparator, causing the output
transistor to turn on.
4-159
SG1548/SG2548/SG3548
APPLICATION EXAMPLE
BIAS SUPPLY
"REF
21.5K
SG1548
+24V±20%<>".f0;.'--+--j-{11 SENSE 1
+5V±1 0% C>-'\,'"'I\---1~---4-{
OVER VOL TAGE
+15V±5%O:";ii)'.'--t----{
UNDER VOLTAGE
15K
-15V±5%C>-'\,'"'I\---1~--{
120 VA';;j
II ,.r-l*""V\.--~-~-{5
LINE SENSE
60~
In this example, the SGt548 simultaneously monitors four DC voltages: +5V, +24V, and ±15V. Three different fault tolerances are
programmed: ±5% on the two 15V supplies, ±1 0% on the +5V supply, and ±20% on the +24V supply. The 51lF delay capacitor provides
125 milliseconds of fault delay.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
16·PIN CERAMIC DIP
J·PACKAGE
Part No.
SG1548J/8838
SG1548J
SG2548J
SG3548J
Ambient
Temperature Range
-55°C to
·55°e to
·25°e to
ooe to
125°C
125°C
85°C
70°C
16·PIN PLASTIC DIP
N· PACKAGE
SG2548N
SG3548N
·25°e to 85°C
ooe to 70°C
16·PIN WIDE BODY
PLASTIC S.O.l.C.
DW·PACKAGE
SG2548DW
SG3548DW
-25°C to 85°C
ooe to 70°C
Connection Diagram
LOWER THRESHOLD [-,---v-;o ~ INV. OUTPUT
GROUND [ 2
15
INV. INPUT
P
3
14p SENSE4
+v~ [4
VREF
l3p SENSE3
LINE SENSE
EMITTER OUTPUT
COLLECTOR OUTPUT
DELAY
LOWER THRESHOLD [[
GROUND'[[
VREF IT
[
[ 5
[ •
[ 7
t2
11
10
[L...2P O.V. FAULT
1
,.::0
,
15::0
2
14 ::0
+VIN 0: 4
LINE SENSE
EMITTER OUTPUT
COLLECTOR OUTPUT
DELAY
20·PIN CERAMIC (LCC)
LEADLESS CHIP CARRIER
L·PACKAGE
SG1548U8838
SG1548L
-55°C to 125°C
-55°C to 125°C
1.N.C.
2. LOWER THRESHOLD
3. GROUND
4. VREF
;
5,+V1N
6.N.C.
7. LINE SENSE
8. EMITTER OUTPUT
9. COLLECTOR
OUTPUT
10.DELAY
[[
[[
[[
[[
P SENSE 2
P SENSE 1
P U.V. FAULT
" ::0
t2 ::0
5
•
11
7
10
~
pc
• tr:J
8
,
2
1
INV. OUTPUT
INV. INPUT
SENSE 4
SENSE 3
SENSE 2
SENSE1
u.v. FAULT
O.V. FAULT
20 19
'0"
5
17
•
1.
7
,
8
15
14
9
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
N.C.
o.v. FAULT
U.V. FAULT
SENSE 1
SENSE 2
N.C.
SENSE 3
SENSE 4
INV.INPUT
INV. OUTPUT
10 11 12 13
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898·8121. TWX: 910·596·1804. FAX: (714) 893·2570
4·160
SG15491SG25491SG3549
E
SILICON
GENERAL
CURRENT SENSE LATCH
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
This monolithic integrated circuit is an analog latch device with digital reset. It was specifically designed to provide pulse-by-pulse current limiting for switch-mode power
supply systems, but many other application are also feasible. Its function is to provide
a latching switch action upon sensing an input threshold voltage, with reset accomplished by an external clock signal. This device can be interfaced directly with many
kinds of pulse width modulating control Ie's, including the SG1524, SG1525A and
SG1527A.
• Current sensing with 100mV
threshold
• Common-mode Input at ground or
t040V
• Complementary outputs
• Automatic reset from PWM clock
• 180ns delay
• Interface direct to sG1524,
sG1525A,sG1527A
The input threshold for the latch circuit is 100mV, which can be referenced either to
ground or to a wide-ranging positive voltage. There are high and low-going output
signals available, and both the supply voltage and clock signal can be taken directly
from an associated PWM control chip.
HIGH RELIABILITY FEATURES
• SG1549
With delays in the range of 200 nanoseconds, this latch circuit is ideal for fast reaction
sensing to provide overall current limiting, short circuit protection, or transformer
saturation control.
o Available to MIL-sTD-883
• sG level "5" processing available
o Radiation data available
BLOCK DIAGRAM
+VS
CLOCK
RESET
HI CM +
INPUT
HI
OUTPUT
+
La
La
CM
INPUT
OUTPUT
SCHEMATIC
r---T---------~------~~r---~v,
LO
OUTPUT
See Application Notes for additional information.
April 1990
4-161
•
SG15491SG25491SG3549
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage, Vs ..................................................... 25V
HI CM Input Voltage ............................................................ 40V
LO Output "off" Voltage ....................................................... 40V
LO Output "on" current ..................................................... 25mA
Operating Junction Temperature
Hermetic (V Package) .................................................. 150°C
Plastic (N Package) ...................................................... 150°C
Storage Temperature Range ............................. -65°C to 150°C
Note 1. Values beyond which damage may occur.
THERMAL DERATING CURVES
2.5
5.0
2.0
'.0
~
~
~
I
~
~
c
'I
1.5
~
'0
~
~~6'~
C 2.0
0
0
25
50
75
"~~
~
::t.s~c
~DI,.o) ~
05
r".,
~
I~
r6,"i",
3.0
~
~
~
-"(8....1>/.
1.0
'-. ~
100
125
150
0
175
'
0
25
...
50
:.;r~
~
75
100
"
150
125
175
AMBIENT TEMPERATURE - "c
CASE TEMPERATURE - "C
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Supply Voltage, Vs .................................................... 5.0V
HI CM Input Voltage .................................................. 2V to 40V
LO Output "off" Voltage ............................................. 5V to 40V
LO Output "on" Current ............................................. 0 to 10mA
Reset LO Voltage ..................................................... OV to 0.8V
Note 2. Range over which the device is functional.
Reset HI Voltage .................................................... 2.5V to 5.0V
Operating Ambient Temperature Range
SG1549V ....................................................... -55°C to 125°C
SG2549V or M ................................................. -25°C to 85°C
SG3549V or M .................................................... O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1549 with -55°e s T. s 125°e, SG2549 with
-25°e ST. S 85°e, SG3549 with ooe S T. S lOoe, and V s = 5V. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
Parameter
Supply Section
Supply Current
LO CM Input Section (Note 3)
Threshold Voltage
Input Impedance
HI CM Input Section (Note 3)
Threshold Voltage
Test Conditions
I
SG1549/2549
SG3549
U It
,Min. Typ. Max.' Min. Typ. IMax.' n s
VPIN8 =5V
V. ,NS = 20V
2
10
2
10
5
15
mA
mA
Pin 1 & 2 shorted, TA = 25°C
pin 1 & 2 shorted
VPIN3 = 50mV, TA =25°C
V. ,N • = 50mV
80 100 120 80 100 120
70 100 130 70 100 130
400 500 600 400 500 600
300 500 700 300 500 700
mV
mV
VOM " 2V, Pin 3 open, TA = 25°C
VCM = 40V, Pin 3 open, TA = 25°C
VOM = 2V, Pin 3 open
VCM = 40V, Pin 3 open
V.,N , =V.,N .=40V
80
80
70
70
Input Current
Clock Reset Section
Min. Trigger Voltage
Input Current
V. ,N7 = 4V
Note 3. Input threshold voltages and supply current are directly proportional to supply voltage, Vs .
4 -162
3
15
100 120
100 120
100 130
100 130
200 300
2.0
20
2.5
40
80
80
70
70
100 120
100 120
100 130
100 130
200 300
2.0
20
2.5
40
n
n
mV
mV
mV
mV
!lA
V
!lA
SG15491SG25491SG3549
ELECTRICAL SPECIFICATIONS
(V. = 5V, and over recomended operating temperature, unless otherwise specified.)
Parameter
SG1549/2549
Test Conditions
HI Output Section
Off Voltage
On Voltage
IlL = lmA
LOOutput
Off Leakage
On Voltage
IVI = SmA
=40V
SG3549
U 't
Max.1 m s
I Min.! Typ.! Max. I Min.! Typ.
I
2.8
I 0 I 0.1
3.2
2.8
1.01 1 1.0
.3
0.5
pIN5
0
3.2
0.1
V
V
.01
.3
1.0
0.5
J.lA
V
TYPICAL SWITCHING CHARACTERISTICS (Note 4)
(V. = 5V, TA = 25'C)
Parameter
SG1549 Series
Units
Min. Typ. Max.
ns
150 300
300 600
ns
ns
50 300
180 360
ns
300 900
ns
ns
30
60
Test Conditions
Amplitude =3.0V
RL =47012 to Vs
La CM Amplitude =200mV
La CM Amplitude =200mV, RL
Amplitude =200mV, VCM =5V
La CM Input =200mV
Reset Minimum Pulse Width (Tw1 )
Delay from Reset to La Output (T DIOFF))
La Input Minimum Pulse Width (TW2)
Delay from La Input to La Output (TDIONi)
Delay from HI Input to La Output (TDION)
Delay from HI Output to La Output
=47012 to Vs
Note 4: These parameters, although guaranteed, are not tested in production.
DYNAMIC TEST CIRCUIT
SWITCHING WAVEFORMS
4
PULSE
CEN 2
GEN 1
TRIG
OUTPUT
Y
+VCM
r--r:s" J~
2N2222's
1
B
2
7-
--,
I
HllN:
LO IN :
S1K
"
['
RESET {
DV
LO
eM
+50Y
HI eM
{:~
{ V
,>0
OUTPUT
51
5
LO OUTPUT {
HI
6
"
~--~
GEN 2.
J~E~-'L _______ ~ _____
)
_~ DELAY -
eM - - - -
---- --------
~tw
(GEN 2)
-.2V
o U.T.
0 HI IN
"
3V
OUT
LO
OUTPUT
5V
OV
HI OUTPUT {
GROUND
~~
-~~.N)
_
t
LD eM ~h--tDION)11
LO eM
-u--- rLw
-=
(8FF)
--
IL
APPLICATION NOTES
HIGH LINE SENSING - The SG 1549 will provide current sensing in the
positive supply line in the typical SG1524 single-ended switching regulator application shown in Figure 1. The HI CM sense circuitry can be
used with input voltages between 2 and 40 volts.
A value for Rse is determined by dividing the 100mV input threshold by
the peak current desired. High-frequency noise, or switching transients,
can usually be eliminated by a small capacitor between pins 3 and 4.
Current control may be accomplished by either the HI OUTPUT pin
connected to the SG1524's Shutdown pin, or the La OUTPUT pin
connected directly to the Compensation Terminal. In either case,
activation of the current sense latch will tend to discharge the compensation capacitor, Ce, which may cause slow recovery from pulse limiting.
If this feature is desired, the La OUTPUT pin may be used to discharge
a soft-start network instead of coupling directly to the SG1524. If it is not
desired, the use of a small value of Ce, and perhaps a diode across Re,
will enhance recovery.
4-163
+VIN
'sc
SWITCH
~ ra---L
r------t+
Vs
1 HI eM
2 -
0----J
:0 eM
RES
ou~ i-6---o
"""'\.)VOUT
PMW
CONTROL
~:~F
"I'
[~T:~
COMMON
FIGURE 1 -
HIGH LINE SENSING WITH THE SG1549 IN CONJUNCTION
WITH AN SG1524 PWM CONTROL IC
SG1549/SG2549/SG3549
APPLICATION NOTES (continued)
Another method of introducing the current shutdown signal is shown in
Figure 2 where the SG1524 is used to activate a constant drive current
to the high-current switch, in this case an SM600. The 2N2222 forms a
constant current generator when driven from the SG1524's 5.0 volt
reference through a 1K resistor. This transistor is then switched off by the
LO OUTPUTtransistor in the SG1549, achieving the fastest response to
the output of the regulator.
LOW LINE SENSING • In many types of feed-forward or push-pull
converters, current protection may be provided by sensing in an emitter
resistor referenced to ground on the primary side of an output transformer. The fast-reacting SG1549 can easily sense secondary overload
as reflected back to the primary and, additionally, provide protection from
unbalanced transformer saturation.
When using the LO CM inputs, the HI CM inputs should be shorted
together. While the LO CM inputs may be connected directly across a
sense resistor, Rsc' a small low-pass filter as shown in Figure 3 is often
required to eliminate high frequency transients. It must be remembered
that the 500n input impedance at the LO CM terminals will cause the use
of R1 to increase the effective threshold; however, this also offers the
possibility of an easily adjustable threshold by incorporating a potentiometer at the input.
Coupling the output Signal from the SG1549 to the control chip may be
done in several ways including the use of either the Compensation or
Shutdown pins on the SG1524 as described earlier.
Another convenient way to tie the output of the SG1549 into the PWM
control in higher power applications is by using the SG1627 Dual
Interface Driver and connecting the LO OUTPUT terminal of the Sg1549
directly to the two Non-Inverting inputs ofthe SG1627 as shown in Figure
'"
.'" O-----r-- - - - - - - - - - - ,
See Application Notes for additional information.
April 1990
4 -175
•
SG1825/SG2825/SG3825
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage (V'N and Vc) ................................................... 30V
Analog Inputs:
Error Amplifier and Ramp ................................. -0.3V to 7.0V
Soft Start and ILIM/S.D ....................................... -0.3V to 6.0V
Digital Input (Clock) .............................................. 1.5V to 6.0V
Driver Outputs ................................................ -0.3V to Vc+ 1.5V
Source / Sink Output Current (each output):
Continuous ..................................................................... 0.5A
Pulse, 500ns .................................................................. 2.0A
Soft Start Sink Current ..................................................... 20mA·
Clock Output Current ......................................................... 5mA
Error Amplifier Output Current ........................................... 5mA
Oscillator Charging Current ................ ............................... 5mA
Operating Junction Temperature:
Hermetic (F, J, L Packages) ......................................... 150°C
Plastic (OW, N Packages) ............................................ 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (soldering, 10 seconds) ..................... 300°C
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL DERATING CURVES
2.5
,...--,...---,---,---,----r---r-...,
1.01--j---If-"-""""'I......."..,...30M--+--l
o~-~~-~-~-~~~-~
o
175
25
17S
AMBIENT TEMPERATURE - "c
CASE TEMPERATURE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage Range .............................................. 10V to 30V
Voltage Amp Common Mode Range ...................... 1.5V to 5.5V
Ramp Input Voltage Range ....................................... OV to 5.0V
Current Limit / Shutdown Voltage Range .................. OV to 4.0V
Source / Sink Output Current
Continuous ................................................................. 200mA
Pulse, 500ns .•................................................................. 1.0A
Voltage Reference Output Current ...................... 1 mA to 10mA
Oscillator Frequency Range ............................ 4KHz to 1.5MHz
Oscillator Charging Current .................................. 301lA to 3mA
Oscillator Timing Resistor (RT) •••••••••••••••••••••••••••• 1KO to 100KO
Oscillator Timing Capacitor (CT) •••••••••••••••••••••••• 470pF to .01 ~F
Operating Ambient Temperature Range:
SGI 825 ......................................................... -55°C to 125°C
SG2825 ........•.................................................. -25°C to 85°C
SG3825 ............................................................... O°C to 70°C
Note 2. Range over which the device is functional and parameter limits are guaranteed.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1825 with -55°C ~ T. ~ 125°C, SG2825 with
-25°C ~ T. ~ 85°C, SG3B25 with ooe ~ T. ~ 70°C, and V'N = Vc = 15V. Low duty cycle pulse testing techniques are used which maintains junction
and case temperatures equal to the ambient temperature.)
Parameter
Reference Section
Output Voltage
Line Regulation
Load Regulation
Temperature Stability (Note 3)
Total Output Range (Note 3)
Output Noise Voltage (Note 3)
Long Tenn Stability (Notes 3 & 4)
Short Circuit Current
Test Conditions
TJ = 25°C,IL= lmA
V,N = 10 to 30V
IL=1t010mA
Over Operating Temperature
Over Line, Load, and Temperature
f = 10Hz to 10KHz, IL = OmA
TJ = 125°C, t = 1000hrs
Vooo = OV
4-176
I SG1825/2825 I
SG3825
I Units
I Min. Typ. Max. I Min. Typ. Max.1
5.05 5.10
2
5
0.2
5.00
50
5
-15 -50
V
5.15 5.00 5.10 5.20
mV
20
2
20
mV
20
5
20
0.4
0.2 0.4 mV/oC
V
5.20 4.95
5.25
200
50
~VRMS
mV
25
5
25
-100 -15 -50 -100 mA
SG1825/SG2825/SG3825
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Test Conditions
SG1825/2825 I
SG3825
I Units
IMin. Typ. Max. I Min. Typ. IMax. I
Oscillator Section (Note 5)
Initial Accuracy
TJ = 25 a C, CCLI( s; 10pF
360 400 440 360 400 440 KHz
2
Voltage Stability
0.2
%
2
0.2
Y'N = tOto 30V
8
Temperature Stability (Note 3)
Over Rated Operating Temperature
5
8
%
5
Total Frequency Limits (Note 3)
Over Line and Temperature
460 KHz
340
460 340
4
KHz
Minimum Frequency
RT = 100Kn, CT = .01/lF
4
MHz
Maximum Frequency
1.5
RT = 1Kn, CT= 470pF
1.5
Clock High Level
V
3.9 4.5
3.9 4.5
IClK = -lmA
V
2.3 2.9
Clock Low Level
2.3 2.9
IClK = -lmA
Ramp Peak Voltage
2.6 2.8 3.0 2.6 2.8 3.0
V
Ramp Valley Voltage
0.6 0.9 1.1 0.6 0.9 1.1
V
Valley-to-Peak Amplitude
V
1.6 1.8 2.1 1.6 1.8 2.1
Error Amplifier Section (Note 6)
Input Offset Voltage
15
mV
10
Rs s; 2Kn, VERROR = 2.5V
Input Bias Current
0.6
3
3
0.6
/lA
VERROR = 2.5V
1
Input Offset Current
0.1
1
0.1
/lA
VERROR = 2.5V
DC Open Loop Gain
dB
60
95
60
95
VERROR = 1 to 4V
Common Mode Rejection
dB
75
Over Rated Voltage Range, VERROR = 2.5V
95
75
95
Power Supply Rejection
dB
85 110
85 110
Y'N = 10V to 30V, VERROR = 2.5V
Output Sink Current
1
rnA
2.5
1
2.5
VERROR = IV
Output Source Current
-0.5 -1.3
rnA
-0.5 -1.3
VERROR = 4V
V
Output High Voltage
IERROR = -0.5mA
4.0 4.7 5.0 4.0 4.7 5.0
V
0
0.5 1.0
Output Low Voltage
0
0.5 1.0
IERROR = lmA
Unity Gain Bandwidth (Note 3)
MHz
3
5.5
5.5
3
Avol =OdB
Slew Rate (Note 3)
6
12
12
V//ls
6
Avcl = 1, Vo = 2Vto 4V
PWM Comparator Section (Note 5 & 7)
Ramp Input Bias Current
-5
-1
-5
-1
I!A
0
Minimum Duty Cycle
%
0
VERROR =IV
Maximum Duty Cycle (Note B)
%
85
85
VEAROR =4V
V
Zero Duty Cycle Threshold
1.1 1.25
1.1 1.25
ns
Delay to Driver Output (Note 3)
80 100
VRA ...P =0 to 2V, V.RRnR = 2V
80 100
SoftStart Section
Css Charge Current
3
9
20
3
20
9
VSOFTSTART = 0.5V
I!A
Css Discharge Current
1
1
rnA
V.nFTiITART = 1.0V
Current Limit I Shutdown Section (Note 9)
±10
IUM Input Bias Current
±10
I!A
V
Current Limit Threshold
0.9 1.0 1.1 0.9 1.0 1.1
V
Shutdown Threshold
1.25 1.40 1.55 1.25 1.40 1.55
Delay to Driver Output (Note 3)
ns
80 100
80 100
VSHUTDOWN = OV to 1.2V
Output Drivers (each output)
Output Low Level
V
ISINK =20mA
0.25 0.40
0.25 0.40
V
1.2 2.2
1.2 2.2
ISINK = 200mA
V
13.0 13.5
13.0 13.5
Output High Level
ISOURCE = 20mA
V
12.0 13.0
12.0 13.0
ISOURCE = 200mA
VCStandby Current
150 500
150 500
Vc=30V
I!A
Output Rise / Fall Time (Note 3)
60
ns
C = 1000pF
30
60
30
Undervoltage Lockout Section
Start Threshold Voltage
8.8 9.2 9.6 8.8 9.2 9.6
V
UV Lockout Hysteresis
0.4 0.8 1.2 0.4 0.8 1.2
V
Supply Current Section (Note 5)
Start Up Current
V,N =8V
1.1 2.5
1.1 2.5
rnA
Operating Current
22
33
22
33
rnA
Y'N' , VR, MP , V(I""/S.D.) = OV, VN1 = 1V
Note 3. This parameter is guaranteed by design and process control, but is not 100% tested in production.
Note 4. This parameter is non-accumulative, and represents the random fluctuation of the reference voltage within some error band when observed
over any 1000 hour period of time.
Note B. 100% duty cycle is defined as a pulsewidth equal to one
Note 5. Fosc = 400KHz (RT= 3.65Kn, CT = 1.0nF)
oscillator period.
Note 6. VCM = 1.5Vto 5.5V.
Note 9. V(lu,)SHUTDOWN) = OV to 4.0V, unless otherwise specified.
Note 7. V...P = OV, unless otherwise specified.
4-177
•
SG1825/SG2825/SG3825
CHARACTERISTIC CURVES
2.5
r-r-"T""""T"--,---r-r-.,-,-...,.,,...,
100
>
90
E
2.0
I-+-+r-r-+-+-t-t-+--t+-l
~ 1.5
I-+-+r-r-+-+-t-t-+--t+-l
<{
<{
E
E
I
'"'"i3
}~
~~
LTT V
it
1il
0.5
1-+-+r-r-+-+-t-t-+--tH
70
>-
cP'
15
~
~~
SPEC
~ 1.0
80
u
~
w
'" "'
50
u
40
'"
~
30
15
I-+-+r-r-+-+-t-t-+.....I---l
60
......
...... r-...
20
r--
10
-n-~-~
YIN -
0
~
~
o
n
1001~1~
JUNCTION TEMPERATURE -
VOLTS
FIGURE 1.
-75-50-2502550
'C
FIGURE 2.
REFERENCE TEMPERATURE STABILITY
SUPPLY CURRENT VS. VIN
10
~
10
~
80
0
~
r-.
60
is
CL = O}'F
1< 40
w
u
15
15
5
~
-2
~ -4
~
20
~
~
\
AVIN = IV RMS
IL = 1 rnA
~
CL
CL
~ -6
<{
j
-8
~-10
- -,"
o
100
10
1K
10K
lOOK
-n-~-~
1M
RIPPLE FREQUENCY - HZ
0
~
~
/
/
w
"~
~
0.5
>=>
CL
~ 0.2
o
L
0.1
"r
V
/
.05
n
1001~1~
JUNCTION TEMPERATURE -
FIGURE 4.
REFERENCE RIPPLE REJECTION
/
I
IOSC= 400 KHZ
RT = J65K
CT'"'1QOOpF
i- -
<{
eo
'C
FIGURE 3.
REFERENCE SHORT CIRCUIT CURRENT
100
!g
z
75100125150
JUNCTION TEMPERATURE -
0.5
10
'C
20
50
100
CT VALUE - nF
FIGURES.
OSCILLATOR TEMPERATURE STABILITY
FIGURE 6.
OUTPUT OEAOTIME VS. CT VALUE
100K
'°90 ,.
~,.
.........
50K
(11
:::;
is 20K
'"I
w 10K
:3
~
~ ......
~
5K
c::
",.
.......... .......
--
i'o...
" --
.,.~o PF'
i"""oo
i""'oo..
........
r-..... .......
.........
........
2K
1K
10K
20K
50K
~
r--..
~
I"'-..
r--.......
... r-........
.......
........
......
r-... .....
.....
.............
~r"- to....
100K
t"......
"
4-178
..........
......
......
..........
.........
.......
"-
500K
200K
OSCILLATOR FREQUENCY FIGURE 7.
OSCILLATOR FREQUENCY VS. RT AND CT
~
HZ
I"
1',
r--.
.... i"oo.
1M
'"
2M
SG18251SG28251SG3825
CHARACTERISTIC CURVES
1 sec
100
u
-
0
0
- r---
I 120
>
x
160
~ 140
WOK
FREQUENCY -
1M
20
o
10M 100M
-n-~-e
HZ
0 e
~
n
l001el~
JUNCTION TEMPERA lURE -
·C
CSOFTSTART - "F
FIGURES.
SOFTSTART TIME VS. Cs VALUE
FIGURE 9.
ERROR AMP OPEN LOOP GAIN
200
III
>14.5
160
~ 140
~
- r---
r--- -
VILIL4" 0 TO \ 2 VOLTS
120
-
""do 100
~
o
80
~ 60
"
i!'
<5
>
+VIN .. \Ie = 15 VOLTS
w
~
~
::>
'"
o
~
'"~
0
e
~
n
100
90
90
80
70
I - r---
CL,"1000pF
r----
~
w
"
60
!=
5
0.5
10 20
50 100200 500
/
70
40
~
""
r-- --
I
~
0
o ~~~--~~~--~~~~
-75-~-25
a 2550 75100125150
JUNCTION TEMPERATURE -
·C
FIGURE 14.
OUTPUT RISEIFALL TIME VS. TEMPERATURE
c L = 1000 pF
40
vV
>-
z
~
w
~u
V" II
40
+vIN - Vc = 15 VOLTS
""E
TJ = +2S'C
30
f-"""
~ 20
P
>- 30
10
'.5A
mA
IIIIII
50
~
::>
20
50 100200 500
FIGURE 13.
OUTPUT DRIVER LOW VOLTAGE VS.lsINK
+VIN ... Vc" 15 VOLTS
" ~
FAL~TII"4E
30
10 20
OUTPUT DRIVER SINK CURRENT -
60
60
:J 50
5
15A
mA
II
""
II 1111
80
50
~
"
i'"
w
FIGURE 12.
OUTPUT DRIVER HIGH VOLTAGE VS. 'SOURCE
100
+'0'1/11 "" VC= 15 VOLTS
2
OUTPUT DRIVER SOURCE CURRENT -
"c
FIGURE 11.
'UMIT INPUT TO DRIVER OUTPUT DELAY
"!=
""
~
1
l001el~
JUNCTION TEMPERA lURE -
w
1.0
12
-n-~-e
~
~
::>
~
o
20
o
If
>-
\
13
~12.5
40
/
2.0
~ 1.5
1-13.5
::>
25
I
t5
~
14
~
a
3.0
15
180
fd
FIGURE 10.
RAMP INPUT TO DRIVER OUTPUT DELAY
20
10
10
o
0.1
0.2
10
0.5
LOAD CAPACITANCE -
nF
FIGURE 15.
OUTPUT RISE/FALL TIME VS. LOAD CAPACITANCE
4-179
o
'OK
20K
50K
100K 200K
OUTPUT FREQUENCY -
500K
HZ
FIGURE 16.
SUPPLY CURRENTVS. OUTPUT FREQUENCY
,M
SG18251SG28251SG3825
APPLICATION INFORMATION
HIGH·SPEED LAYOUT AND BYPASSING
The SG1825, like all high-speed circuits, requires extra attention to external conductor and component layout to minimize undesired inductive and capacitive effects. All lead lengths must be as short as possible. The best printed circuit board choice
would be a four-layer design, with the two internal planes supplying power and ground. Signal interconnects should be placed
on the outside, giving a conductor-over-ground-plane (microstrip)
1---.;"";;,,11"'-----.......0 VREF
configuration. A two-sided pc board with one side dedicated as a
ground plane is next best, and requires careful component placeSG1825
Vc 13
ment by a skilled pc designer.
PWR GND 12
Two supply bypass capacitors should be employed: a low-inductance 0.1 IlF ceramic within 0.25 inches of the +V'N pin for high
frequencies, and a 1 to 5 IlF solid tantalum within 0.5 inches of the
Vc pin to provide an energy reservoir for the high peak output
currents. A low-inductance .01 IlF bypass for the reference output
is also recommended.
+V'N
.01pF
=L:::=!====~===l=±:=
FIGURE 17.
HIGH SPEED LAYOUT AND BYPASSING
MICROPOWER STARTUP
Since the SG1825 draws less than 2.5 mA of supply current before
turning on, a low power bleeder resistor from the rectified AC line
supply is all that is required for startup. A start capacitor, Cs' is
charged with the excess currentfrom the bleeder resistor. When the
turn-on threshold voltage is reached, the PWM circuit becomes
active, energizing the power transistors. The additional operating
current required by the PWM is then provided by a bootstrap winding
on the main high-frequency power transformer.
OND
~.:.:..:.:.+-t-'
FIGURE 18.
MICROPOWER STARTUP
. SOFTSTART CIRCUIT
The Softstart pin of the SG1825 is held low when either the chip is in the micropower mode, or when a voltage greater than
+1.4 volts is present at the ILiM/s.o. pin. The maximum positive swing of the voltage error amplifier is clamped to the Softstart
pin voltage, providing a ramp-up of peak charging currents in the power semiconductors at turn-on.
. In some cases, the duration of the Shutdown signal can be too short
to fully discharge the softstart capacitor. The illustrated resistor!
discrete PNP transistor configuration can be used to shorten the
discharge time by a factor of 50 or more. When the internal
discharge transistor in the SG 1825 turns on, current will flow through
surge limit resistor Rl. As the resistor drop approaches 0.6 volts, the
external PNP turns on, providing a low resistance discharge path for
the energy in the softstart capacitor. The capacitor will be rapidly
discharged to +0.7 volts, which corresponds to zero duty cycle in the
pulse width modulator.
SG1825
+
CSOFTSTART
FIGURE 19.
SOFTSTART FAST RESET
FREQUENCY SYNCHRONIZATION
Two or three SG1825 oscillators may be locked together with the
interconnection scheme shown, if the devices are within an inch or
so of each other. A master unit is programmed for desired
frequency with RT and CTas usual. The oscillators in the slave units
are disabled by grounding CT and by connecting RT to VREF" The
logic in the slave units is locked to the clock of the master with the
wire-OR connection shown.
Many SG1825s can be locked to a master system clock by wiring
the oscillators as slave units, and distributing the master clock to
each using a tree-fanout geometry.
4 -180
ax
SG1825
.,........---,
C,
PWR GND 12
ax v....
SG1825
.,.'
C,
PVIft GNO 12
GIlD
FIGURE 20.
OSCILLATOR SYNCHRONIZATION
SG18251SG28251SG3825
APPLICATION INFORMATION
OSCILLATOR
The oscillator frequency is programmed by external timing components RT and CT' A nominal +3.0 volts appears at the RT pin.
The current flowing through RT is mirrored internally with a 1:1 ratio. This causes an identical current to flow out the CTpin,
charging the timing capacitor and generating a linear ramp. When the upper threshold of +2.8 volts is reached, a discharge
network reduces the ramp voltage to +1.0, where a new charge cycle
begins.
SG1825
The Clock output pin is LOW (+2.3 volts) during the charge cycle,
and HIGH (+4.5 volts) during the discharge cycle. The Clock pin is
driven by an NPN emitter follower, and so can be wire-ORed. Each
Clock pin can drive a 1 mA load. Since the internal current-source
pulldown is approximately 400 ~A, the DC fan-out to other SG1825
Clock pins is at least two.
+S.1V
Jl
4
CLOCK
HOY
+2.JV
The type of capacitor selected for CT is very important. At high
frequencies, non-ideal characteristics such as effective series resistance (ESR), effective series inductance (ESL), dielectric loss and
dielectric absorption all affect frequency accuracy and stability. RF
capacitors such as silver mica, glass, polystyrene, or COG ceramics
are recommended. Avoid high-K ceramics, which work best in DC FIGURE 21.
bypass applications.
OSCILLATOR FUNCTIONAL DIAGRAM
•
ERROR AMPLIFIER
The voltage error amplifier is a true operational amplifier with lowimpedance output, and can be gain-stabilized using conventional
feedback techniques. The typical DC open-loop gain is 95 dB, with
a single low-frequency pole at 100 Hz.
The input connections to the error amplifier are determined by the
polarity of the power supply output voltage. For positive supplies,
the common-mode voltage is +5.1 volts and the feedback connections in Figure A are used. With negative outputs, the commonmode voltage is half the reference, and the feedback divider is
connected between the negative output and the +5.1 volt reference
as shown in Figure B.
FIGURE 22.
VOLTAGE AMP CONNECTIONS
OUTPUT DRIVERS
The output drivers are designed to provide up to 1.5 Amps peak
output current. To minimize ringing on the output waveform, which
can be destructive to both the power MOSFET and the PWM chip, the
series inductance seen by the drivers should be as low as possible.
SC1825
I
~fARAOAY SH!ElD
I
I
I
One solution is to keep the distance between the PWM and MOSFET
gate as short as possible, and to use carbon composition series
damping resistors. A Faraday shield to intercept radiated EMI from
the power transistors is usually required with this choice.
.SCHOTTKY Q.At.lP MAY BE REQUIRED
A second approach is to place the MOSFETs some distance from the
PWM chip, and use a series-terminated transmission line to preserve
drive pulse fidelity. This will minimize noise radiated back to the FIGURE 23.
sensitive analog circuitry olthe SG1825. A Faraday shield may also DRIVING SHIELDED CABLE
be required.
If the drivers are connected to an isolation transformer, or if kickback through CGO of the MOSFET is severe, clamp diodes may
be required. 1 Amp peak Schottky diodes will limit undershoot to less than -0.3 volts.
4 -181
SG1825/SG2825/SG3825
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
16-PIN CERAMIC DIP
J - PACKAGE
Part No.
SG1825J/883B
SG1825J
SG2825J
SG3825J
Ambient
Temperature Range
.,
Connection Diagram
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
to
aoe 7aoe
16-PIN PLASTIC DIP
N-PACKAGE
SG2825N
SG3825N
-25°C to 85°C
to
16-PIN WIDE BODY
PLASTIC S.O.l.C.
OW-PACKAGE
SG2825DW
SG3825DW
-25°C to 85°C
to
aoe 7aoe
aoe 7aoe
INV. INPUT
N.I.INPUT
ElA OUTPUT
CLOCK
R,
RAMP
SOFT START
SG1825F/883B
SG1825F
-55°C to 125°C
-55°C to 125°C
P
P
[2
[3
R, [S
14
OUTPUT B
13p Vc
12p PWRGND
CT [6
11
[4
IT
IT
IT
IT
IT
IT
IT
IT
1
2
3
20-PIN PLASTIC
LEADED CHIP CARRIER
0- PACKAGE
(Note 3)
SG1825U883B
SG1825L
SG2825Q
SG3825Q
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
to
aoe 7aoe
P GROUND
•
•7
7. AT
9. RAMP
10. SOFT START
" f:o
p:1
OUTPUT B
13
Vc
+V'N
Fo
PWRGND
f:o
f:o
9.P:J
8
:::::=;;
e,cr
V REF
~
11
I.
OUTPUT A
GROUND
'UM J S.D.
16~VP.E~
c:==::::::
1.N.C.
2. INV. INPUT
3. N.I. INPUT
4. ElA OUTPUT
5. CLOCK
S.N.C.
FIJ
15
12
5
1
INV. INPUT
2
N.I. INPUT
3
ElAOUTPUT =
CLOCK = .
.R,= 5
C,=
RAMP =
7
8
SOFT START =
1.N.C.
2. INV.INPUT
3. N.I.INPUT
4. ElA OUTPUT
5. CLOCK
S.N.C.
7. RT
e'Cr
9. RAMP
10. SOFT START
I".'S.D.
16
15~+V'N
"~ OUTPUTB
t=====?
13
t====:J
3 2
1 20 19
'0"
'0"
S
17
6
,16
7
IS
•
I.
9
10 11
12 13
3 2 1 20 19
S
17
•
7
I.
IS
.
.
•
I.
9
Vc
12~ PWRGND
11 ~ OUTPUT A
1O~ GROUND
9
IUM f S.D.
•
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L-PACKAGE
(Note 3)
P OUTPUT A
RAMP [7
I.
SOFT START [~P
C,
16-PIN CERAMIC
FLAT PACK
F-PACKAGE
(Note 3)
[~P V,,,
15
+V,~
INV. INPUT
N.I. INflUT
ElA OUTPUT
CLOCK
10 11
12 13
".N.C.
12.IL11oI /S.D.
13. GROUND
14. OUTPUT A
15.PWRGND
16. N.C.
17. Vo
1B.OUTPUTB
19,+V'N
20. VRE.F
".N.C.
12.1,,"IS.D.
13. GROUND
14. OUTPUT A
15. PWRGND
1S.N.C.
17.Vc
1B.OUTPUTB
19,+VIj
20. VREF
Note 1. Contact factory for JAN and DESC product availablity..
2. All packages are viewed from the top.
3. Contact factory for package availabiilily
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4-182
SG1840/SG2840/SG3840
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
PROGRAMMABLE, OFF-LINE, PWM CONTROLLER
DESCRIPTION
FEATURES
Although containing most of the features required by all types of switching
power supply controllers, the SG1840 family has been optimized for highlyefficient boot-strapped primary-side operation in forward or flyback power
converters. Two important features for this mode are a starting circuit which
requires little current from the second operation over a wide input voltage
range.
• All control, driving, monitoring, and protection functions included
• High Frequency Initial Accuracy
• Low-current, Off-line start circuit
• Feed-forward line regulation over 4 to 1 input
range
• PWM latch for single pulse per period
• Pulse-by-pulse current limiting plus shutdown for over-current fault
• No start-up or shutdown transients
• Slow turn-on and maximum duty-cycle clamp
• Shutdown upon over- or under-voltage
sensing
• Latch off or continuous retry after fault
• Remote, pulse-commandable start/stop
• PWM output switch usable to 1A peak
current
.1% reference accuracy
• 500kHz operation
.70dB PSRR
• Linear frequency response
In addition to startup and normal regulating PWM functions, these devices
offer a built-in protection from over-voltage, under-voltage, and over-current
fault conditions. This monitoring circuitry contains the added features that any
fault will initiate a complete shutdown with provisions for either latch-off or
automatic restart. In the latch-off mode, the controller may be started and
stopped with external pulsed or steady-state commands.
Other performance features of these devices include a 1% accurate reference, provision for slow-turn-on and duty-cycle limiting, and high-speed
pulse-by-pulse current limiting in addition to current fault shutdown.
The SG1840 PWM output stage includes a latch to insure only a single pulse
per period and is designed to optimize the turn off of an external switching
device by conducting during the "OFF"time with a capability for both high peak
current and low saturation voltage. These devices are available in an 18-pin
dual-in-line plastic or ceramic package.
The SG1840 is characterised for operation over the full military ambient
temperature range or -55°e to 125°e. The SG2840 and SG3840 are
designed for operation from -25°e to 85°e and ooe to 70 oe, respectively.
HIGH RELIABILITY FEATURES-SG1840
• Available to MIL-STD-883
• SG Level "S" processing available
BLOCK DIAGRAM
~N
SENSE
RAMP
YlN SUPPLY
DRIVER
COMP
BIAS
INV INPUT
()----f"-
PWM
OUTPUT
NI INPUT
5.0V REF'
START/UV
GROUND
SLOW START
DUTY CYCLE
CLAMP
RESET
EXT STOP
>---1-"""-
L'-_--'">
CUR UIJIIT
THRESHOLD
CURRENT SENSE
ov
SENSE
April 1990
4 -183
a'
~
,.1
~'",
SG1840/SG2840/SG3840
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (+ V,N )
Voltage Driven ................................................................. 32V
Current Driven (self-limiting) ....................................... 100mA
PWM Output Voltage (Pin 12) ............................................. 40V
PWM Output Current (continuous) ................................. 400mA
PWM Output Peak Energy Discharge ...................... 201-1 Joules
Driver Bias Current (Pin 14) .......................................... -200m A
Reference Output Current (Pin 16) ................................. -SOmA
Slow-start Sink Current (Pin 8) ....................................... 20 mA
Note 1. Values beyond which damage may occur.
+ V,N Sense Current (Pin 11) ............................................ 10mA
Current Limit Inputs (Pins 6 & 7) .......................... -O.SV to S.SV
Comparator Inputs (Pins 2,3,4,S,17,18) .................. -0.3V to V,N
Operating Junction Temperature
Hermetic (J package) .................................................... IS0°C
Plastic (N, DW packages) ............................................. IS0°C
Storage Temperature Range ............................ -6SoC to IS0°C
Lead Temperature (Soldering, 10 Seconds) ................... 300°C
THERMAL DERATING CURVES
2.5
2.0
~,
1.5
is
~
iiiB
1.0
5.0
I'..
"-
~&
§
~
13.0
"- ~'&;~~0~
"t-
~
c"
'~4';'-
iii
6
1-1'?6'
~~"t-
~
0
25
50
75
~
100
125
~" \v
~.~
'~
r;.6"~;jr
2.0
i
" N:~"c
0.5
0
\
4.0
150
i"i"S'-2
.5'0/0
4-~
(' o~
~
1.0
~
0
175
0
AMBIENT TEMPERATURE - 'C
25
50
75
100
CASE TEMPERATURE -
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
~
125
150
175
'C
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage Range .............................................. 8Vto 30V
Error Amp Common Mode Range .......................... I.SV to S.SV
PWM Output Current (continuous) .......................... 0 to 200m A
Driver Bias Output Current ....................................... oto SOmA
Reference Load Current ........................................... 0 to 20mA
+ V,N Sense Current Range ............................... 101-lA to 1.0mA
Ramp Generator Capacitor Range ................... 620pF to O.II-1F
Oscillator Frequency Range ........................... 1OOHz to SOOKHz
Oscillator Timing Resistor (R T) ........................... 1Kf.! to 100Kf.!
Oscillator Timing Capacitor (CT) ....................... 620pF to O.II-1F
Operating Ambient Temperature Range:
SG1840 ......................................................... -SsoC to 12SoC
SG2840 .... ...... ...... .................. ................ ......... -2SoC to 8SoC
SG3840 .... ...... ........................ ................ ............ O°C to 70°C
Note 2. Range over which the device is functional and parameter limits are guaranteed.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1840 with -55°C,; TA ,; 125°C, SG2840 with
-25°C,; TA ,; 85°C, SG3840 with DoC'; TA ,; 70°C, V'N = 20V. RT = 20Kn, C, = O.001I-lF, CR = O.001I-lF, and Current LimitThreshhold = 200mV. Low duty
cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Power Inputs Section
Start-Up Current
Start-Up Current T.C. (Note 3)
Operating Current
Supply OV Clamp
Reference Section
Reference Voltage
Line Regulation
Load Regulation
Temperature Coefficient (Note 3)
Short Circuit Current
Test Conditions
V,N = 30V, Pin 2 = 2.5V, TJ = 25°C
V,N = 30V, Pin 2 = 2.SV
V,N '" 30V. Pin 2 = 3.5V
I'M= 20mA
TJ= 25°C
V,N = 8 to 30V
IL = Ot020mA
Over operating temperature range
Va «= O. T = 25°C
4-184
, SG1840/2840,
SG3840
, Un'ts
, Min. Typ. Max.' Min. Typ. Max.'
I
5
33
4.95
5
-0.1
10
40
7
-0.2
15
4S
5.0
10
10
5.05
IS
20
±0.4
-100
-80
5
33
4.9
mA
%/OC
mA
V
5
-0.1
10
40
7
-0.2
15
48
5.0
10
10
5.1
V
20
mV
30
mV
±0.4 mV/oC
-100 mA
-80
SG1840/SG2840/SG3840
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Oscillator Section
Nominal Frequency
H.F. Initial Accuracy (Note 3)
Voltage Stability
Temperature Coefficient (Note 3)
Maximum Frequency
Ramp Generator Section
Ramp Current, Minimum
Ramp Current, Maximum
Ramp Valley
Ramp Peak
Error Amplifier Section
Input Offset Voltage
Input Bias Current
Input Offset Current
Open Loop Gain
Output Swing (Max. Output :>;
Ramp Peak - 100m V)
CMRR
PSRR
Short Circuit Current
Gain Bandwidth (Note 3)
Slew Rate (Note 3)
PWMSection
Continuous Duty Cycle Range
(other than zero) (Note 3)
Output Saturation
Output Leakage
Comparator Delay (Note 3)
Sequencing Functions Section
Comparator Thresholds
Input Bias Current
StartlUV Hysteresis Current
Input Leakage
Driver Bias Saturation Voltage
Driver Bias Leakage
Slow-Start Saturation
Slow-Start Leakage
Current Control Section
Current Limit Offset
Current Shutdown Offset
Input Bias Current
Common Mode Range (Note 3)
Current Limit Delay (Note 3)
Test Conditions
TJ = 25°C
Rr = 3K!1, Cr = 91 OpF
VIN = Sto 30V
Over operating temperature range
Rr = 2K!1, Cr = 620pF
I SG1840/2840 I
SG3840
I Units
I Min. Typ. Max.1 Min.1 Typ. Max. I
47
270
50
300
0.5
500
-11
-0.9 -0.95
0.3 0.5
3.9 4.2
ISENSE = -1 OIlA
ISENSE = 1.0mA
Clamping Level
VCM = 5.0V
0.5
0.5
Ll.Vo = 1 to 3V
Minimum Total Range
VCM = 1.5to 5.5V
VIN = S to 30V
V COMP = OV
60
0.3
66
70
70
SO
90
-4
2
O.S
T J = 25°C, AVOL = OdB
T = 25°C, AveL = OdB
1
Minimum Total Continuous Range, Ramp
Peak < 4.2V
lour = 20mA
lour = 200mA
Vour = 40V
Pin S to Pin 12
T = 25°C, R = 1kn
5
Pins 2, 3, 4, 5
Pins 3, 4, 5 = OV
Pin 2 = 2.5V
Input V = 20V
IB= -50mA
VB=OV
Is = 2mA
Vs = 4.5V
2.S
150
370
Pin 7= OV
-14
4.5
0.4
2.2
10
500
3.0
-1.0
200
0.1
2
-0.1
0.2
0.1
3.2
-3.0
250
10
3
-10
0.5
2.0
0
400
-2
5
430
-5
3.0
400
KHz
KHz
%
%/OC
-11
-14
-0.9 -0.95
0.3 0.5
3.9 4.2 4.5
llA
rnA
10
5
0.5
mV
3.5
V
2
1
60
0.3
66
70
70
SO
90
-4
2
O.S
5
2.8
150
360
-10
0.2
1.7
0.1
300
0.4
2.2
10
500
3.0
-1.0
200
0.1
2
-0.1
0.2
0.1
3.2
-3.0
250
10
0
400
-2
10
440
-5
3.0
400
-0.4
200
V
V
llA
llA
dB
dB
dB
rnA
MHz
VlllS
95
Note 3. These parameters, although guaranteed over the recommended operating condition, are not 100% tested in production.
4 -185
55
330
1
±.OS
KHz
1
0.2
1.7
0.1
300
50
300
0.5
500
-10
95
200
45
270
5
2
0.5
3.5
-0.4
T = 25°C, Pin 7 to 12, R =11<
53
330
1
±.OS
%
V
V
llA
ns
V
llA
!lA
llA
3
V
-10
0.5
2.0
llA
V
llA
mV
mV
!lA
V
ns
•
SG1840/SG2840/SG3840
CHARACTERISTIC CURVES
220
1,
'"'"
:::l
U
'"inw
'">-w
'">-
--
210
>z
w
200
v
r-....
r-
.......
190
I
lI
I
180
-55 -25
TIMING RESISTOR-(n)
I
I
25
I
50
'"'"
I
75
I
100
JUNCTION TEMPERATURE-(OC)
FIGURE 1.
OSCILLATOR FREQUENCY
FIGURE 2.
STARTIU.V. HYSTERESIS CURRENT VS.
JUNCTION TEMPERATURE
..,.
Q.z
>-0.
"'>- 4.0
0-
.....=~
Cj~
$'
1.0
::;;
>-« 0.1
:::lU
0>
H\
Cs=o
>-~
>-
20V
:::l
$'N
~~
0.0.
OV
2.5
§?
2.0
'"~
00
~z
~a: 6.5
uQ.
I'
w
Cs=D--
-~~=.'~F
- --
0
~Cs=.ii";;F-
H"
a
z
-
---
1.5
1.0
i':::lo
0.5
:::l
!- 0s=.1'"1
es=· 01
~
'">«
'">-
«
:::l
r
2
0
4
5
DELAY TIME-(IlS)
OUTPUT SINK CURRENT-(mA)
FIGURE 3.
SHUTDOWN TIMING
FIGURE 4.
PWM OUTPUT SATURATION VOLTAGE
VS. SINK CURRENT
420
$'
E
I'
g
f--
-
I-
-
415
0
I
'"
W
'"
F
410
>-
:;;
:J
V
>Z
w
'"
0:
405
,., -
-
;I'
:::l
U
I
400
-55 -25
I
I
a
I
25
I
50
75
I
100
JUNCTION TEMPERATURE-(OC)
FIGURES.
CURRENT LIMIT VS. JUNCTION TEMPERATURE
4-186
125
125
SG1840/SG2840/SG3840
SG1840 POWER SEQUENCING FUNCTIONS
E
G
H I J
QRS
I I
I
I I I
I II
D
Note 1. Vcrepresents an analog
of the output voltage generated
by a primary-referenced secondary winding on the power transformer. It is the voltage monitored by the startlUV comparator
and, in most cases, is the supply
voltage, VIN , for the SG1840.
Vc
(Note ,)
Driver
810s
Slow
Start
PWM
Note 2. Although input to External Stop, Pin 4, is shown, results
are the same for any fault input
which sets the Error Latch.
u
(Not;li, - - - - - . . . ,
U
Reset _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....1
I I I
I II
QRS
TIME
EVENT
TIME
EVENT
A
Initial turn·on. Vc rises with light load
Start threshold. Driver Bias Loads Vc
Operating PWM regulates Vc
Stop input sets Error Latch turning off PWM
UV low threshold. Error Latch remains set
Start turns on Driver Bias but Error Latch still set
L
M
N
Return to normal run state
Reset Latch set signal removed
Error Latch set with momentary fault
Error Latch does not reset as Reset Latch is reset
B
C
D
E
F
~}
I
J
K
o
6}
Vc and Driver Bias recycle with no turn-on
Reset Latch set is set with momentary Reset signal
Vc must complete cycle to turn-on
Start and Error Latches reset
Normal start initiated
Return to normal run state
R
S
Vc and Driver Bias continue to cycle
Stop command removed
Error Latch reset at UV low threshold
Start threshold now removes slow-start clamp
T
U
V
OPEN LOOP TEST CIRCUIT
'-"
'-"./
SUPPLY
~
VOLTAGE
~N
'6
~
Rr
20K
Or
.001
--D...
~N
20K
R2
9K
'4
DRIVE 81AS
SENSE
D.U.T.
RT/CT
PWM OUT
'2
GNO
'3
-'..Q. RAMP
I~~~~6R
~ RL ~'K
-=2
3K
R3
SLOW ST.
SG1840
I
Cs'
~
8 Rsf'80K
VREF
9
R,
Roc~ 24K
"5
lOOK
3
4<
--=-
+ .001
1
START/UV
STOP
~o-
OV SENSE
RESET
~o-
COMP
INV
1~r
C/L(-)
NI
C/L(+)
-=-
7
6
'8
VREF
I
l.
O.,
'OK
48K
'OK}
PMW
_
43K
'---<
2K
ADJ
-:
10K
CURRENT SENSE
-=1
UV Foult Voltage
Nominal Frequency = - - = 50KHz
RTC T
Start Voltage
~ 3 (R1+~+R3~+O.2R1~
\
R2+R3 )
~ 3 (R1+~+R3~~
\
12V
OV Foult Voltage
~ 3 (R1+~+R3~~
\
4 -187
BV
R2 +R 3 )
R2+R3 )
TEST
Current Limit
= 200mV
Current Fault Voltage = SOOmV
32V
Duty Cycle
~
50%
II
SG1840/SG2840/SG3840
FUNCTIONAL DESCRIPTION
PWMControl
1. Oscillator
Generates a fixed-frequency internal clock from an external
6
F\ and CT'
Frequency = R
T T
2. Ramp Generator
dv
sense voltage
Develops a linear ramp with a slope defined externally by (it
=
RRCR
CRis normally selected ~ CRand its value will have some effect upon valley voltage.
CRterminal can be used as an input port for current mode control.
3. Error Amplifier
Conventional operational amplifier for closed-loop gain and phase compensation.
Low output impedance; unity-gain stable.
4. Reference Generator
Precision S.OV for internal and external usage to SOmA.
Tracking 3.0V reference for internal usage only with nominal accuracy of ±20/0.
40V clamp zener for chip OV protection. 100mA maximum current.
5. PWM Comparator
Generates output pulse which starts at termination of clock pulse and ends when the ramp input
crosses the lowest of two positive inputs.
6. PWM Latch
Terminates the PWM output pulse when set by inpuis from either the PWM comparator, the pulse-bypulse current limit comparator, or the error latch. Resets with each internal clock pulse.
7. PWM Output Switch
Transistor capable of sinking current to ground which is off during the PWM on-time and turns on to
terminate the power pulse. Current capacity is 400mA saturated with peak capacitance discharge in
excess of one amp.
Sequencing Functions
1. StarVUV Sense
This comparator performs three functionsWith an increasing voltage, it generates a turn-on signal at a start threshold.
With a decreasing voltage, it generates a UV fault signal at a lower level separated by a 200llA
hysteresis current.
At the UV threshold, it also resets the Error Latch if the Reset Latch has been set.
2. Drive Switch
Disables most of the chip to hold internal current consumption low, and Driver Bias OFF, until input
voltage reaches start threshold.
3. Driver Bias
Supplies drive current to external power switch to provide turn-on bias.
4. Slow Start
Clamps low to hold PWM OFF. Upon release, rises with rate controlled by RsCs for slow increase of
output pulse width.
Also used to clamp maximum duty cycle with divider Rs Roc'
5. Start Latch
Keeps low input voltage at initial turn-on from being defined as a UV fault. Sets at start level to
monitor for UV fault.
6. Reset Latch
When reset, this latch insures no reset signal to either Start or Error latches so that first fault will lock
the PWM off.
When set, this latch resets the Start and Error latches at the UV low threshold, allowing a restart.
Protection Functions
1. Error Latch
When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset.
Inputs to Error Latch are:
a. UV low (after turn-on)
b. OV high
c. Stop low
d. Current Sense 400mV over threshold
Error Latch resets at UV threshold if Reset Latch is set.
2. Current Limiting
Differential input comparator terminates individual output pulses each time sense voltage rises above
threshold.
When sense voltage rises to 400mV above threshold, a shutdown signal is sent to Error Latch.
4 -188
SG1840/SG2840/SG3840
SG1840 PROGRAMMABLE PWM CONTROLLER IN A SIMPLIFIED FLYBACK REGULATOR
'.
R,
f
In this application, complete control is maintained on the primary side. Control power is provided by RIN and CIN during start-up, and
by a primary-referenced low voltage winding, N2, for efficient operation after start. The error amplifier loop is closed to regulate the DC
voltage from N2 with other outputs following through their magnetic coupling - a task made even easier with the SG1840's feed-forward
line regulation.
Not shown are protective snubbers or additional interface circuitry which may be required by the choice of the high-voltage switch, Os,
or the application.
SG1840 CONTROLS A HIGH-CURRENT NON-ISOLATED BUCK REGULATOR
'0
VIN - 10-JOY
Although primarily intended for transformer-coupled power systems, the SG1840's advantages of feed-forward for high ripple-rejection,
a fully contained fault monitoring system and remote startlstop capability make it worth considering for other types of regulators. Since
the fault logic within the SG1840 requires recycling the voltage sensed by the StartlUV Comparator to reset the error latch, a need for
automatic restart must be addressed in a manner similar to that shown. In this simple, non-isolated, buck regulator, diode 01 provides
a low-impedence bootstrapped drive power source after start-up is achieved through RIN and CIN • When a fault shutdown terminates
switching action, the loading of 01 and Rd will lower the voltage on pin 2 to effect an automatic re-start attempt which will continuously
recycle until the fault is removed.
4 -189
II
S61840/S62840/S63840
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
Ambient
Temperature Range
18-PIN CERAMIC DIP
J-PACKAGE
SG1840J/883B
SGl840J
SG2840J
SG3840J
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
OOeto 70°C
18-PIN PLASTIC DIP
N- PACKAGE
SG2840N
SG3840N
-25°C to 85°C
OOeto 70°C
18-PIN WIDE BODY
PLASTIC S.O.l.C.
DW-PACKAGE
SG2840DW
SG3840DW
-25°C to 85°C
OOeto 70°C
Connection Diagram
COMPENSATION
START UV
OV SENSE
STOP
RESET
CURRENT THRESHOLD
CURRENT SENSE
SLOW START
RTC T
COMPENSATION
STARTUV
OVSENSE
STOP
RESET
CURRENT THRESHOLD
CURRENT SENSE
SLOW START
IT
IT
IT
IT
IT
IT
IT
IT
R,C, IT
[-,--=-;e J
NON·INV INPUT
INVERTING INPUT
5.0V REF
+VIN SUPPLY
ORIVER BIAS
GROUND
PWM OUTPUT
V" SENSE
[~::::J RAMP
[2
[3
[4
[ 5
[ •
[7
[8
1
2
3
4
5
•7
8
9
17 J
IS:J
15:::J
14:J
13:J
12:J
11:J
18
17
fIl
i=D
,. i=D
NON·INV INPUT
INVERTING INPUT
5.0V REF
15 ~ +Vtt SUPPLY
14
DRIVER BIAS
13
GROUND
12
PWM OUTPUT
11 ~ V1N SENSE
~ RAMP
I.
i=D
i=D
i=D
Note 1. Contact factory for JAN and DESC product availibility.
2. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
4 -190
SG18421284213842
SG18431284313843
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
CURRENT-MODE PWM CONTROLLER
DESCRIPTION
FEATURES
The SG1842/43 family of controllC's provides all the necessary features
to implement off-line fixed frequency, current mode switching power
supplies with a minimum number of external components. Current mode
architecture demonstrates improved line regulation, improved load regulation, pulse-by-pulse current limiting and inherent protection of the
power supply output switch.
o Optimized for off-line control
• Low start-up current «1 mAl
o Automatic feed forward compensation
• Trimmed oscillator discharge current
• Pulse-by-pulse current limiting
• Enhanced load response characteristics
o Under-voltage lockout with 6V hysteresis
(SG1842 only)
• Double pulse suppression
o High current totem pole output (lAmp peak)
• Internally trimmed bandgap reference
• 500 KHz operation
o Undervoltage lockout
SG1842 -16 volts
SG1843 - 8.4 volts
• Low shoot-through current < 75mA over
temperature
The bandgap reference is trimmed tD ±1 % over temperature. Oscillator
discharge current is trimmed to less than ±10%. The SG1842/43 has
under-voltage lockout, current limiting circuitry and start-up current of
less than 1 mAo
The totem pole output is optimized to drive the gate of a power MOSFET.
The output is low in the off state to provide direct interface to an N channel
device.
The SG1842/43 is specified for operation over the full military ambient
temperature range of -55°C to 125°C. The SG2842/43 is specified forthe
industrial range of -25°C to 85°C, and the SG3842/43 is designed for the
commercial range of O°C to 70°C.
HIGH RELIABILITY FEATURES
- SG1842/1843
•
•
•
•
Available to MIL-STD-883 and DESC SMD
Scheduled for MIL-M38510 QPL listing
Radiation data available
SG level "S" processing available
BLOCK DIAGRAM
V REF
S.ov
50mA
OUTPUT
POWER GROUND
- Vccand Vc are internally connected forS pin packages.
- POWER GROUND and GROUND are internally connected for 8 pin packages.
April 1990
See Application Notes for additional information.
4-191
S618421S61843 SERIES
ABSOLUTE MAXIMUM RATINGS (Notes 1 & 2)
Supply Voltage (Icc < 30mA) ................................... Sell-limiting
Error Amp Output Sink Current ......................................... 10mA
Supply Voltage (Low Impedence Source) ........................... 30V
Operating Junction Temperature
Output Current ,(peak) ......................................................... ±1 A
Hermetic (J, y, F - Packages) ....................................... 150°C
Plastic (N, M, D - Packages) ........................................ 150°C
Output Current (continuous) ........................................... 350mA
Storage Temperature Range ............................. -65°C to 150°C
Output Energy (Capacitive Load) ........................................ 511J
Analog Inputs (Pin 2, Pin 3) ................................. -0.3V to 6.3V
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Exceeding these ratings could cause damage to the device.
Note 2. All voltages are with respect to Pin 5. All currents are positive into the specified terminal.
THERMAL DERATING CURVES
2.5 .-----.-------,--'-r----,----,----r----,
'75
AMBIENT TEMPERATURE - 'C
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Supply Voltage Range ......................................................... 30V
Output Current (peak) ........•................................................ ±1A
Output Current (continuous) ,.......................................... 200mA
Analog Inputs (Pin 2, Pin 3) ...................................... OV to 2.6V
Error Amp Output Sink Current .......................................... 5mA
Oscillator Frequency Range ........................... 1OOHz to 500KHz
Note 3. Range over which the device is functional.
Oscillator Timing Resistor (R T) ................... 5200 S RT S 150kQ
Oscillator Timing Capacitor (CT) .................. 1000pF S CT S 111F
Operating Ambient Temperature Range:
SG1842/43 .................................................... -55°C to 125°C
SG2842/43 ............. ......................................... -25°C to 85°C
SG3842/43 .........................................................• O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG18421SG1843 with ·55°e S T. S 125°e, SG28421
SG2843 with -25°e S T. S 85°e, SG38421SG3843 with ooe ST. S 70 oe, Vee = 15V (Note 7), RT = 10Kfl, and e T= 3.3nF. Low duty cycle pulse testing
techniques are used which maintains junction and case temperatures equal to the ambient temperature)
I SG1842/43 I SG2842/43 I SG3842/43 I Units
Parameter
Test Conditions
,Min. Typ. Max., Min. Typ. Max., Min. Typ. Max.,
Reference Section
Output Voltage
4.95 5.00 5.05 4.95 5.00 5.05 4.90 5.00 5.10
TJ =25°C, 10 = 1mA
V
Line Regulation
12V S VIN S 25V
20
6
20
20
6
6
mV
Load Regulation
1 s 10 S20mA
25
6
25
mV
6
25
6
Temp. Stability (Note 4)
0.2 0.4
.02 0.4
0.2 0.4 mV/OC
Total Output Variation (Note 4)
Line, Load, Temp.
4.90
5.10 4.90
5.18
V
5.10 4.82
Output Noise Voltage (Note 4)
10Hz sis 10kHz, TJ =25°C
50
50
50
I1V
Long Term Stability (Note 4)
25
TA =125°C, 1000 Hrs.
5
5
25
5
25
mV
Output Short Circuit
-30 -100 -180 -30 -100 -180 -30 -100 -180 mA
Oscillator Section
Initial Accuracy
TJ =25°C
47
57
47
52
52
57
47
52
57
kHz
Voltage Stability
1
0.2
.02
1
0.2
1
12 SVcc S 25V
%
Temp. Stablilty (Naie 4)
5
5
5
%
TMINSTASTMAX
Amplitude
1.7
1.7
1.7
V
VRT/CT (peak to peak)
Discharge Current
7.8 8.3 8.8 7.5. 8.4 9.3 7.5 8.4 9.3
TJ = 25°C
mA
7.0
9.0 7.2
9.5
9.5 7.2
mA
T..,N sT S T .>v
4 -192
SG18421SG1843 SERIES
ELECTRICAL SPECIFICATIONS (continued)
Parameter
I SG1842/43 I SG2842/43 I SG3842/43 I Units
I Min. Typ. Max. I Min. Typ. Max. I Min. I Typ.1 Max. I
Test Conditions
Error Amp Section
Input Voltage
Input Bias Current
Open Loop Gain (AvoL)
Unity Gain Bandwidth (Note 4)
PSRR
Output Sink Current
Output Source Current
VOUT High
VOUTLow
Current Sense Section
Gain (Notes 5 & 6)
Maximum Input Signal (Note 5)
PSRR (Note 5)
Input Bias Current
Delay to Output (Note 4)
Output Section
Output Low Level
VCOMP = 2.5V
2.45 2.50 2.55 2.45 2.50 2.55 2.42 2.50 2.58
V
-0.3
-0.3 -1
1
-0.3 -2
~
65
65
90
90
65
90
dB
0.7
0.7
1
1
0.7
1
MHz
60
70
60
70
70
dB
60
2
2
6
6
2
6
mA
-0.5 -0.8
-0.5 -0.8
-0.5 -0.8
mA
5
5
6
V
6
5
6
0.7 1.1
0.7 1.1
0.7 1.1
V
12SVCC S25V
VVFa = 2.7V, VCOMP = 1.1 V
VVFB = 2.3V, VCOMP = 5V
VVFa = 2.3V, RL = 15K to gnd
VVFB=2.7V,R = 15KtoVREF
2.85
0.9
VCOMP = 5V
12SVcc S25V
1
13
12
Rise Time
Fall Time
Under-Voltage Lockout Section
Start Threshold (1842)
Min. Operating Voltage (1842)
After Turn On
Start Threshold (1843)
Min. Operating Voltage (1843)
After Turn On
PWMSection
Max. Duty Cycle
Min. Duty Cycle
Power Consumption Section
Start-Up Current
Operating Supply Current
VVFa = V,SENSE = OV
Vcr: Zener Voltage
1",,= 25mA
3.15 2.85
1.1
0.9
3
1
-10
300
70
-2
150
0.1 0.4
1.5 2.2
13.5
13.5
50 150
50 150
13
12
0.1
1.5
13.5
13.5
50
50
70
-2
150
ISINK= 20mA
ISINK = 200mA
ISOURCE = 20mA
ISOURCE = 200mA
TJ = 25°C, CL = 1nF
T = 25°C, C = 1nF
Output High Level
3
0.4
2.2
13
12
150
150
16
10
8.4
7.6
17
11
9.0
8.2
15
9
7.8
7.0
16
10
8.4
7.6
9.0
8.2
14.5
8.5
7.8
7.0
93
95
100
90
95
100
90
0.5
11
34
17
0.5
11
34
1
17
o
1
6. Gain defined as:
Notes: 4. These parameters, although guaranteed, are not 100%
tested in production.
5. Parameter measured at trip point of latch with VVFB = O.
17
11
o
VN
V
-10
300
dB
~
ns
0.1 0.4
1.5 2.2
13.5
13.5
50 150
50 150
V
V
V
V
ns
ns
16
10
8.4
7.6
17.5
11.5
9.0
8.2
V
95
100
%
%
0.5
1
11
17
rnA
mA
V
1
70
-2
150
-10
300
15
9
7.8
7.0
3.15
1.1
3
3.15 2.85
1.1
0.9
V
V
V
o
34
d Veo",
A = ~; 0" V'SENSE" O.BV.
ISENSE
7. Adjust Vee above the start threshold before setting at 15V.
CHARACTERISTIC CURVES
rS'
~
10.0 I---'t
"-t-I---t-++-t--t-l
'"
96
SG1842
1-+----1
"-1-+-+-;;;1;;;;:::1:::-+-1
§?
~
9.2 1---t-++-t-+-I--+-+-1
~ B.B 1-+--+---+--+--+-1-+-+--;
~o
?5
'~"
8.4 1-+--+---+--+--+-1-+-+--;
I\.
V'N = 15V
K -21---t-++-t-1~
'D~UT~YfCY~C~~-~5D~"-l
l~
r\
-4 I---t-++-t--t---'lil-t-+--l
~ -61-+--+---+-+--+-~~t-+---i
8
E -BI-+--+---+-+--+-I--r~\--;
SG1843
B.O
I-+--+---+--+--+_-f-_-+--+-l
~O~5
02550
75
1001251~
JUNCTlON TEMPERATURE-(Oc)
FIGURE 1.
DROPOUT VOLTAGE VS. TEMPERATURE
-10 1---1--+---+-+--+-1--+-+--1
-SO -25
0
25
50
75 100 125 150
JUNCTION TEMPERATURE-(Oe)
FIGURE 2.
OSCILLATOR TEMPERATURE STABILITY
4-193
"'-=-,!.
220 I--+-++-t--t-t-I---t--l
/
200 I--+-++-t--t-t-V-t--l
~ ,BO I-+-+--+---+--+---,j~t-+---i
/
~~ 1601-+-+--+--+'A-1"""-j---r-----i
/vPIN3 -
!
1.1V
~
z
140
'20 1--+--+--+--+-+-1-1--1--1
-50 -25
a
25
50
75 100 125 150
JUNCTION TEMPERATURE-(Oc)
FIGURE 3.
CURRENT SENSE TO OUTPUT DELAY VS. TEMP.
SG18421SG1843 SERIES
CHARACTERISTIC CURVES (continued)
5.02
50
R
~
49
~
4B
§
47
'""
46
:>
S
0
1-0-.
100K~ V
~
11'
50KHz
0.7
~
-<
E
~
"
I~ ~
~
45
lOOK
200K
25
50
I
"-
0.4
'""
0.3
~
~
75 100 125 150
~;0
B
>
~
'""
8.26
/
8.24
8.22
B.20
">
V
16.06
-50 -25
is
"-<
~
"- f',
~! '
0
25
50
I'
1.0
0.5
100
200
.300
w
400
OUTPUT CURRENT-(mA)
FIGURE 10.
OUTPUT SATURATION VOLTAGE VS. OUTPUT
CURRENT AND TEMPERATURE
(SINK TRANSISTOR)
B.D
500
I
25
50
75 100 125 150
I
"f\
"
7.6
~
:"
~
7.4
",.
-
- "-
"\
/
~
0
I
J
7.B
"-<
Ii:
I
~
7.2
-50-250
75 100 125 150
255075100125150
JUNCTION TEMPERATURE-(OC)
FIGURE 9.
OSCILLATOR DISCHARGE CURRENT
VS. TEMPERATURE
1.0
,-,---,--r--=_"
::
1-_+__
/.P/'"
t-_-h.V-;J'/./\:;"k~f-V_-l
I~vt)
u-
1.5
0
FIGURE6.
REFERENCE VOLTAGE VS. TEMPERATURE
FIGURES.
START-UP VOLTAGE THRESHOLD
VS. TEMPERATURE
20
/
-50 -25
I
\
\,
4.98
JUNCTION TEMPERATURE-(OC)
2.5
Vee = 1SV
JUNCTION TEMPERATURE-("c)
SG1842
15.98
75 100 125 150
FIGURE 7.
START-UP VOLTAGE THRESHOLD
VS. TEMPERATURE
g
~
/
JUNCTION TEMPERATURE _(DC)
~;0
I
~ .........
B.2
g
50
4.99
II
-<
E
":,) 16.02
25
~
~
16.00
0
r--.
~
§Z
5.00
255075100125150
~
8.18
">
a
"'- ~
~ 16.04
I
-50 -25
.......
SG1843
/
~
~
V
V
8.28
r
FIGURES.
START-UP CURRENT VS. TEMPERATURE
~
8.30
~O~5
16.08
">
......
5.01
JUNCTION TEMPERA TURE-( DC)
FIGURE 4.
OUTPUT DUTY CYCLE VS. TEMPERATURE
SG1843
">
.........
0.5
JUNCTION TEMPERATURE-(OC)
8.32
~G1B42
0.6
0.2
a
.......
:>
50K
44
-50 -25
.......
,/-'~i--
0.6
/
0.5
0.4
f-------t--f--/+'/.-f+lf-----+-----I
f-------t--hf-jf-,/-A----+___---I
0.3
I---lf--/*V.,...'/r-t--t----l
0.2
'--If-~l+'j+V-l--t--l---J
0.1
I---t-J.-.'./...f-I-'f----+---+--t
1.0
2.0
3.0
4.0
ERROR AMP OUTPUT VOL TAGE-(V)
FIGURE 11.
CURRENT SENSE THRESHOLD VS. ERROR
AMPLIFIER OUTPUT
4-194
">
4.0
~
3.0
~
§Z
z
0
"~
2.0
'"
1.0
F'
5.0
OUTPUT CURRENT-(mA)
FIGURE 12.
OUTPUT SATURATION VOLTAGE VS. OUTPUT
CURRENT AND TEMPERATURE
(SOURCE TRANSISTOR)
SG18421SG1843 SERIES
APPLICATION INFORMATION
OSCILLATOR:
The oscillator of the 1842143 family of PWM's is designed such that many values of RT & CTwill give the same oscillator frequency,
but only one combination will yield a specific duty cycle at a given frequency.
A set offormulas are given to determine the values of Rr & CTfor a given frequency and maximum duty cycle. (Note: These formulas
are less accurate for smaller duty cycles or higher frequencies. This will require trimming of RT or CTto correct for this error.)
GIVEN: Frequency", f
Maximum Duty Cycle", Dm
CALCULATE:
RT = 267
~ 1.76)Yom
-1
(1.0m
Yl)
(1.76)
EXAMPLE:
A Flyback power supply requires a maximum of 45% dutycycle at a switching frequency of 50KHz. What are the values of
RT and CT?
J
(0)
GIVEN: f = 50KHz
Dm = 0.45
m-1
where .3 < Dm < .95
1.86 x Dm
CALCULATE: RT =267
(Il F)
~ 1.76)
/.645 -1
5
J
=6740
(1.76)% -1
fx RT
CT =
1.86 x .45
50000 x 674
...........
"'~ . . . . r-.
For Duty-Cycles above 95% use:
= .0251lF
1000
o!!r,
6801}
"'- ~~
100
N
:I:
e-
~~
'"
>~Q
...........
eT
10
I"-
~
~
~
&D.to
~
,
r'-I"-
>
9\'0
'ei%
'"
'"
~
.001
.002
.005
.01
.02
CT VALUE -
.05
0.1
J1F
FIGURE 14 - OSCILLATOR FREQUENCY VS. R, FOR VARIOUS C,
FIGURE 13 - OSCILLATOR TIMING CIRCUIT
APPLICATION CIRCUITS
......
~ t ' i""'- r--. r'- ..
I
1
~
.
(Note 8)
VN
7('1)
Ql
~
SC1S42!4J
__
's
j
Ql
6(10)
~K
IPK(!.1AX) =
'R~V
5(8)
3(5)
's
FIGURE 15 - CURRENT SENSE SPIKE SUPPRESSION
FIGURE 16 - MOSFET PARASITIC OSCILLATIONS
The RC low pass filter will eliminate the leading edge current
spike caused by parasitics of Power MOSFET.
A resistor (R,) in series with the MOSFET gate will reduce
overshoot & ringing caused by the MOSFET input capacitance
and any inductance in series with the gate drive. (Note: It is very
important to have a low inductance ground path to insure correct
operation ofthe I.C. This can be done by making the ground paths
as short and as wide as possible.)
4 -195
SG18421SG1843 SERIES
APPLICATION CIRCUITS
(continued)
VC+.I~S
~~
vel
.
-R,IR, _
II
Ql
VGS Waveforms
~~
SGl842143
50% DC
:~
3(5)
25% DC
3(5)
I
= V(pin
PK
U-1.4 (!:!e.)
Ns
3 s
FIGURE 17 - BIPOLAR TRANSISTOR DRIVE
FIGURE 18 -ISOLATED MOSFET DRIVE
The 1842143 output stage can provide negative base current
to remove base charge of power transistor (all for faster turn off.
This is accomplished by adding a capacitor (C 1l in parallel with a
resistor (R1l. The resistor (R1l is to limit the base ,current during
turn on.
Current transformers can be used where isolation is required
between PWMand Primary ground. A drive transformer is then
necessary to interface the PWM output with the MOSFET.
8(14)
8(14)
RA
8
4(7)
4
~
SGl842143
555
TIMER
Rs
3
4(7)
M
C -'-
::r
-::-
3(5)
C
IpK =
V
it
Where: 0
an
dV
1=
~ V, ~ 1.0V
1.43 - 0.23 R/R,
1+R/Rz
!"OFTSTART
r,
= -In ~ -
~lc R,R,
VoJ
11
-
f
'F1,+Fr,
1
1.44
=(R+2R)C
5(9)
To other
SGX842143
0.5
h
V,=--"R,T
were:
1 + )'Rz
FIGURE 19 - ADJUSTABLE BUFFERED REDUCTION OF
CLAMP LEVEL WITH SOFT·START
FIGURE 20 - EXTERNAL DUTY CYCLE CLAMP AND
MULTI·UNIT SYNCHRONIZATION
Soft start and adjustable peak current can be done with the
external circuitry shown above.
Precision duty cycle limiting as well as synchronizing several
1842143's is possible with the above circuitry.
4 -196
SG18421SG1843 SERIES
APPLICATION CIRCUITS (continued)
7(11)
SV
2.BV
1.1Vo
2.SV
RT
6(10)
I
2(3)
CT
-=-
Discharge
Current
~
R,
1(1)
Id =8.2mA
RF
RF ;::10K
-=FIGURE 21 - OSCILLATOR CONNECTION
FIGURE 22 - ERROR AMPLIFIER CONNECTION
The oscillator is programmed by the values selected for the timing
components RT and CT' Refer to application information for
calculation of the component values.
Error amplifier is capable of sourcing and sinking current up to
O.SmA.
FIGURE 23 - SLOPE COMPENSATION
Due to inherent instability of current mode converters running above 50% duty cycle, a slope compensation should be added to either
current sense pin or the error amplifier. Figure 23 shows a typical slope compensation technique.
4-197
•
SG18421SG1843 SERIES
APPLICATION CIRCUITS (continued)
[J
,---------~--~~----------------------~--------------()VREF
SG1842/43
4.7K
VCC
0.1!,F
1K ~--~----~----+---~
ERROR AMP
ADJUST
0.1!,F
1K_
}--+----j----~----_o
4.7K
OUTPUT
---1I-________+ ____________--() GROUND
L -________
FIGURE 24 - OPEN LOOP LABORATORY FIXTURE
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and ypass capacitors should
be connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply
an adjustable ramp to pin 3.
T1
4.70 1W
USD735
+
5V
2-5A
16V
Tl: Cailcraft E-4140-b
SG1842
V
F8
COMP
Primary - 97 turns
single AWG 24
V
CC
Secondary - 4 turns
4 parallel AWG 22
OUT
Control -
9 turns
3 parallel AWG 28
3.6KO
100pF
V
REF
O.OlpF
q
CUR
SEN
RT/C T GND
470pF
I
0.850
.OO47pF
ISOLATION
BOUNDRY
SPECIFICATIONS
Input line voltage:
Input frequency:
Switching frequency:
Output power:
Output voltage:
Output current:
Line regulation:
Load regulation:
Efficiency @ 25 Watts,
V'N = 90VAC:
V'N = 130VAC:
Output short-circuit current:
FIGURE 25 - OFF·L1NE FLYBACK REGULATOR
90VAC to 130VAC
50 or 60Hz
40KHz ±10%
25Wmaximum
5V+5%
2t05A
0.01%IV
8%/A*
* This circuit uses a low-cost feedback scheme in which the DC
voltage developed from the primary-side control winding is
sensed by the SG1842 error amplifier. Load regulation is
therefore dependent on the coupling between secondary and
control windings, and on transformer leakage inductance.
70%
65%
2.5Amp average
Note 8. Pin numbers referenced are for 8 pin package and pin numbers in parenthesis are for 14 pin packages.
4-198
SG18421SG1843 SERIES
CONNECTION DIAGRAM & ORDERING INFORMATION (See notes below)
Package
14-PIN CERAMIC DIP
J - PACKAGE
Part No.
SG1842J/883B
SG1842J
SG2842J
SG3842J
SG1843J/883B
SG1843J
SG2843J
SG3843J
Ambient
Temperature Range
-55°e
-55°e
-25°e
ooe
-55°e
-55°e
-25°e
ooe
to
to
to
to
to
to
to
to
Connection Diagram
125°e
125°e
85°e
70 0 e
125°e
125°e
85°e
70 0 e
q1
COMP
N.C.
W
14
VREf
3
13
12
Vee
4
11
VC
6
9
OUTPUT
GROUND
7
8
POWER GND
U
V Fa
N.C.
I"",
N.C.
R!C T
14-PIN PLASTIC DIP
N - PACKAGE
SG2842N
SG3842N
SG2843N
SG3843N
-25°e
ooe
-25°e
ooe
8-PIN CERAMIC DIP
Y- PACKAGE
SG1842Y/883B
SG1842Y
SG2842Y
SG3842Y
SG1843Y/883B
SG1843Y
SG2843Y
SG3843Y
-55°e to
-55°e to
-25°e to
ooe to
-55°e to
-55°e to
-25°e to
ooe to
125°e
125°e
85°e
70 0 e
125°e
125°e
85°e
70 0 e
8-PIN PLASTIC DIP
M - PACKAGE
SG2842M
SG3842M
SG2843M
SG3843M
-25°e
ooe
-25°e
ooe
to
to
to
to
85°e
70 0 e
85°e
70 0 e
14-PIN PLASTIC S.O.I.C.
D- PACKAGE
SG2842D
SG3842D
SG2843D
SG3843D
-25°e
ooe
-25°e
ooe
to
to
to
to
85°e
70 0 e
85°e
70 0 e
to
to
to
to
85°e
70 0 e
85°e
70 0 e
C O M P O V""
V FB
2
7
Vee
ISENSE
3
6
Riel
4
5
OUTPUT
GROUND
COMP IT
N.C. IT
20-PIN CERAMIC
LEAD LESS CHIP CARRIER
L- PACKAGE
SG1842F/883B
SG1842F
SG1843F/883B
SG1843F
SG1842U883B
SG1842L
SG1843U883B
SG1843L
-55°e
-55°e
-55°e
-55°e
-55°e
-55°e
-55°e
-55°e
to
to
to
to
to
to
to
to
125°e
125°e
125°e
125°e
125°e
125°e
125°e
125°e
14PJ VREF
13~ N.C.
1
2
VFa IT
3
N.C. IT
4
IT
N.C. IT
RIC, IT
5
ISENSE
10-PIN CERAMIC
FLAT PACK
F- PACKAGE
N.C.
v
Fa
R/G T
POWERGND
1. N.C.
2.COMP
3. N.C.
4. N.C.
5. VFa
6. N.C.
7.lsENSE
B.N.C.
9. N.C.
10. RIC,
r:::=::::::::
c::::=
=
c::::::
3
Vee
VC
P=l
10fTI
OUTPUT
9fTI GROUND
81=0 POWER GND
6
7
10~VREF
COMP ~ 1
ISENSE
12~
11
9!=====JVcc
2
8~Vc
3
7~ OUTPUT
4
5
6~ GROUND
2
1
20 19
'0"
5
17
6
16
7
8
15
14
910111213
11.N.C.
12. GROUND
13. N.C.
14. N.C.
15. OUTPUT
16. N.C.
17. Vee
1B.N.C.
19. N.C.
20. VREF
Note 1. Contact factory for JAN and DESC product availability.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4 -199
4-200
SG18441284413844
SG18451284513845
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
CURRENT-MODE PWM CONTROLLER
DESCRIPTION
FEATURES
The SG1844/45 family of control IC's provides all the necessary features to
implement off-line fixed frequency, current mode switching power supplies with
a minimum number of external components. Current mode architecture demonstrates improved line regulation, improved load regulation, pulse-by-pulse
current limiting and inherent protection of the power supply output switch.
•
•
•
•
•
•
•
The bandgap reference is trimmed to ±1 % over temperature. Oscillator
discharge current is trimmed to less than ±10%. The SG1844/45 has undervoltage lockout, current limiting circuitry and start-up current of less than 1 mAo
The totem pole output is optimized to drive the gate of a power MOSFET. The
output is low in the off state to provide direct interface to an N channel device.
•
•
•
•
•
Both operate up to a maximum duty cycle range of zero to < 50% due to an
internal toggle flip flop which blanks the output off every other clock cycle.
•
The SG1844/45 is specified for operation overthe full military arnbienttemperature range of -55°C to 125°C. The SG2844/45 is specified for the industrial
range of -25°C to 85°C, and the SG3844/45 is designed for the commercial
range of O°C to 70°C.
Optimized for off-line control
Low start-up current «1mA)
Automatic feed forward compensation
Trimmed oscillator discharge current
Pulse-by-pulse current limiting
Enhanced load response characteristics
Under-voltage lockout with 6V hysteresis (sG1844 only)
Double pulse suppression
High current totem pole output
Internally trimmed bandgap reference
500KHz operation
Undervoltage lockout
sG1844 -16 volts
sG1845 - 8.4 volts
Low shoot-through current < 75mA over
temperature
HIGH RELIABILITY FEATURES
- SG1844/SG1845
o Available to MIL-sTD-883
o sG level "5" processing available
BLOCK DIAGRAM
V REF
5.0V
SOmA
GROUND
OUTPUT
R
V'B
Latch
Current Sense
Comparator
COMP
CURRENT SENSE
POWER GROUND
0>-------------------'
- Vee and Vc are internally connected for 8 pin packages.
- POWER GROUND and GROUND are internally connected for 8 pin packages.
See Application Notes for additional information.
April 1990
4- 201
•
SG18441SG1845 SERIES
ABSOLUTE MAXIMUM RATINGS (Note 1 & 2)
Supply Voltage (Icc < 30mA) ........ :.......................... Self-limiting
Error Amp Output Sink Current ......................................... 1OmA
Supply Voltage (Low Impedence Source) ........................... 30V
Operating Junction Temperature
Output Current (peak) ......................................................... ±1A
Hermetic (J, Y Packages) ............................................. 150°C
Output Current (continuous) ........................................... 350mA
Plastic (N, M, D Packages) ........................................... 150°C
Storage Temperature Range ............................. -65°C to 150°C
Output Energy (Capacitive Load) ........................................ 5~J
Analog Inputs (Pin 2, Pin 3) .................................. -0.3V to 6.3V
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Values beyond which damage may occur.
Note 2. All voltages are with respect to Pin 5. All currents are positive into the specified terminal.
THERMAL DERATING CURVES
2.5
5.0,\
2.0
~
I
~
~
~'"
~
~
I
~~
(' ....Pl'"
0
y
t
2'
.1"01
() (''1
1'("
"
~
~Ij>Oh
-if (6....f:J
'0
100
7'
r-V ,ol-is
~COtl
1.0
12'
150
0
17'
'\
'''71-,o(
~
erOIP)
J
Iv (i'!l': I
Of")
0
) "
PIN
14.0
~4-
. . 'O/"'s.
2.0
i
~,o)
0.'
L
(e~,,,,
~
a
I ~~~~
~ ~'"
D
3.0
~
'.0~~~"'~
o
'\
~
~"
1.51-
~
a
4.0
~~
~
0
2'
'0
"'s.->"
7'
o~
100
~
150
12'
17'
AMBIENT lE).(PERATURE - "c
CASE TEMPERATURE - "C
MAXIMUM POWER OISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage Range ............................................... ......... 30V
Output Current (peak) ........................................................ ±1A
Output Current (continuous) ........................................... 200mA
Analog Inputs (Pin 2, Pin 3) ...................................... OV to 2.6V
Error Amp Output Sink Current .......................................... 5mA
Oscillator Frequency Range .......................... 100Hz to 500KHz
Note 2. Range over which the device is functional.
Oscillator Timing Resistor (RT) ................... 5200 S RT S 150kO
Oscillator Timing Capacitor (CT) .................. 1OOOpF S CT S 1~F
Operating Ambient Temperature Range:
SG1844/45 .................................................... -55°C to 125°C
SG2844/45 ....................................... ............... -25°C to 85°C
SG3844/45 ........................ ................................. O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambienllemperatures for SG1844!SG1845 with -55°C,;; T.,;; 125°C, SG2844!
SG2845 with -25°C';; T.,;; 85°C, SG3844!SG3845 witl) O°C ';;T.,;; 70°C, Vee = 15V (Note 6), R,. = 10KQ, and CT = 3.3nF. Low duty cycle pulse testing
techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Reference Section
Output Voltage
Line Regulation
Load Regulation
Temp. Stability (Note 3)
Total Output Variation (Note 3)
Output Noise Voltage (Note 3)
Long Term Stability (Note 3)
Output Short Circuit
Oscillator Section
Initial Accuracy (Note 7)
Voltage Stability
Temp. Stability (Note 3)
Amplitude
Discharge Current
I SG1844/45 I SG2844/45 I SG3844/45 I Units
I Min. Typ. IMax. IMin. Typ. Max. I Min. ITyp. Max. I
Test Conditions
TJ '" 25°C, 10 ", 1mA
12SVIN S25V
ISIo S20mA
Line, Load, Temp.
10Hz S f S 10kHz, TI = 25°C
TA = 125°C, 1000 Hrs.
TJ =25°C
12V S Vcc S 25V
TMINSTASTMAX
VRTICT (peak to peak)
T ",25°C
MIN < T < TMAX
r
4.95 5.00 5.05 4.95 5.00
20
6
6
25
6
6
.02
0.2 0.4
4.90
5.10 4.90
50
50
25
5
5
-30 -100 -180 -30 -100
47
52
.02
57
1
47
9.1
9.3
7.5
7.2
5
7.8
6.8
4-202
1.7
8.3
52
0.2
5
1.7
8.4
5.05 4.90 5.00 5.10
V
20
20
mV
6
25
6
25
mV
0.4
0.2 0.4 mV/oC
5.10 4.82
5.18
V
50
~V
25
25
mV
5
-180 -30 -100 -180 mA
57
1
47
9.3
9.5
7.5
7.2
52
0.2
5
1.7
8.4
57
1
9.3
9.5
kHz
%
%
V
mA
mA
SG18441SG1845 SERIES
ELECTRICAL SPECIFICATIONS (continued)
Parameter
I
Test Conditions
Error Amp Section
Input Voltage
Input Bias Current
Open Loop Gain (AyOL)
Unity Gain Bandwidth (Note 3)
PSRR
Output Sink Current
Output Source Current
VOUT High
VOUT Low
Current Sense Section
Gain (Notes 4 & 5)
Maximum Input Signal (Note 4)
PSRR (Note 4)
Input Bias Current
Delav to Output (Note 3)
Output Section
Output Low Level
VeoMP
=2.5V
2~Vo~4V
12~Vee~25V
VVFB =2.7V,
VVFB =2.3V,
VVFB =2.3V,
VV.B =2.7V,
VeoMP = 1.1V
VCOMP =5V
RL =15K to gnd
RL = 15K to VR••
VeoMP =5V
12V ~ Vee ~ 25V
SG1844/45 I SG2844/45 I SG3844/45
Units
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
2.45 2.50 2.55 2.45 2.50 2.55 2.42 2.50 2.58
-0.3
-0.3 -1
-0.3 -2
1
65
90
65
90
65
90
0.7
0.7
1
1
0.7
1
60
60
70
70
60
70
2
2
6
6
2
6
-0.5 -0.8
-0.5 -0.8
-0.5 -0.8
5
5
6
6
5
6
0.7 1.1
0.7 1.1
0.7 1.1
V
IlA
dB
MHz
dB
mA
mA
V
V
2.85
0.9
3 3.15 2.85 3 3.15 2.85 3 3.15
1.1 0.9
1
1
1.1 0.9
1
1.1
70
70
70
-2
-2
-10
-10
-2
-10
150 300
150 300
150 300
VN
V
dB
13
12
0.1 0.4
1.5 2.2
13.5
13.5
50 150
50 150
13
12
0.1 0.4
1.5 2.2
13.5
13.5
50 150
50 150
0.1
0.4
1.5 2.2
13.5
13.5
50 150
50 150
V
V
V
V
ns
ns
15
9
7.8
7.0
16
10
8.4
7.6
17
11
9.0
8.2
15
9
7.8
7.0
16
10
8.4
7.6
17
11
9.0
8.2
14.5
8.5
7.8
7.0
16
10
8.4
7.6
17.5
11.5
9.0
8.2
V
V
V
V
46
48
50
0
46
48
50
0
46
48
50
0
%
%
0.5
11
34
1
17
0.5
11
34
1
17
0.5
11
34
1
17
mA
mA
V
ISINK =20mA
ISINK =200mA
'SOURCE =20mA
'SOURCE =200mA
TJ =25°C, CL = lnF
T =25°C, C = 1nF
Output High Level
Rise Time (Note 3)
Fall Time (Note 3)
Under-Voltage Lockout Section
Start Threshold (1844)
Min. Operating Voltage (1844)
After Turn On
Start Threshold (1845)
Min. Ooeratina Valtaae(184~ After Turn On
PWMSecllon
Max. Duty Cycle
Min. Duty Cycle
Power Consumption Section
Start-Up Current
Operating Supply Current
VVFB =V,SENSE =OV
Vee Zener Voltage
Icc =25mA
13
12
I!A
ns
I1V
5. Gain defined as: A = ~; 0:;; VIS'NSO:;; O.BV.
Notes: 3. These parameters, although guaranteed, are not 100%
tested in production.
4. Parameter measured at trip point of latch with VVFS = O.
tl.
VISENSE
6. Adjust Vco above the start threshold before setting at 15V.
7. Output frequency equals one half of oscillator frequency.
CHARACTERISTIC CURVES
.,
S' 10.0
tJ
~
96
""-
SC::1B44
-
§;!
~
92
"~
88
;!5
8.4
;=
"
;r~
1;
ffi
§
0
"Z
1\
N
SG1845
8.0
-50 -25
0
25
--
50
75 100 125 150
JUNCTION TEMPERATURE-CDc)
FIGURE 1.
OROPOUT VOLTAGE VS. TEMPERATURE
~
-2
-4
-6
Y,N .. 15V
I-J+-++-+I~
""'U' -','rcCY""CLt-'=--1'50,,-"-I
r\
1-+-++-+-+--'1.1-+-+--1
1\
f-+-+--+--+-+---i,"",,+-+--i
-Bf-+-+--+--+-+~f-r~\--i
-10
f-+-+--+--+-+----'f-+-+--i
-so
-25
0
25
50
75 100 125 150
JUNCTION TEMPERATURE-COe)
FIGURE 2.
OSCILLATOR TEMPERATURE STABILITY
4- 203
.,-
g
~
>z
w
""a
220
/
200
V
160
Vv
160
140
IN3 .. ,.1V
~ .....
......
120
-50 -25
a
25
50
75 100 125 150
JUNCTION TEMPERATURE-COe)
FIGURE 3.
CURRENT SENSE TO OUTPUT DELAY VS. TEMP.
SG18441SG1845 SERIES
CHARACTERISTIC CURVES (continued)
5.02
0.7
<-E
;r
~
...... .......
~'B44
O.S
.......
0.5
......
::>
'-'
!3
0.4
~
0.3
....
S-
5.01
~
5.00
i'i
4.99
~
.......
r....
w
'-'
~
SG1845
II
k
........
"
I
If
~
8.28
~
....
8.24
~
~
4.98
a
50
75 100 125 150
~
16.04
~
n.
::J
....
"""
16.02
15,ge
~O-25
a
;r
~
SG1844
~
~
a"'
8.2
w
7.8
~
i;l
7.S
"~
,
1\
~
7.4
z
0.4
....z
0.3
a"'"'
0.2
w
0.1
2.5
"
'\
I
a
2550
75
2.0
3.0
S-
4.0
~
'i1
3.0
z
0
F
"'~
;;;
4.0
FIGURE 10.
CURRENT SENSE THRESHOLD VS. ERROR
AMPLIFIER OUTPUT
2.0
~
~
1.5
F
1.0
"'
0.5
'OOl~150
~
IJ 'I
II.
'II
I III
/II
u..
1.0
S-
is
JUNCTION TEMPERATURE-(Oc)
l.rtfh~
ERROR AMP OUTPUT VOLTAGE-(V)
l001251~
FIGURES.
START-UP VOLTAGE THRESHOLD
VS. TEMPERATURE
"'"'
;;;
-50~5
100125100
1//
0.7
-
~
~
1.30
~
'"
1.20
'"
gJ
1.10
..............
.....
3.10 _
~~
'"
1--+---+--+--+-~---+--1
3.00
I--+---+--+--+-~---+---I
U 2.90
1--+---+--~--+-~---+--1
~
Q
268
0.5 1.0 1.5 2.0 2.5 3.0 ::5 5 4.0 4.5 5.0
125
JUNCTION TEMPERATURE - (OC)
~
2.82
2.76
-25
FIGURE 2.
V." SHORT CIRCUIT CURRENT VS. TEMPERATURE
28'
z
;;: 2.78
'"
-55
(OC)
FIGURE 1.
REFERENCE VOLTAGE VS. TEMPERATURE
A~
0~...J._--'-_'-...J._--'-_'--'
125
gJ
-55 ·25
25
JUNCTION
50
75
TEMPERAT~RE
100 125
_ (OC)
FIGURES.
OSCILLATOR VALLEY VOLTAGE VS. TEMPERATURE
4-212
2.80
L----l_--'-__..L._l.......J_--'-_-'
-55 -25
'25
50
75
100 125
JUNCTION TEMPERATURE - (Oc)
FIGURES.
OSCILLATOR PEAK VOLTAGE VS. TEMPERATURE
SG18461SG1847 SERIES
CHARACTERISTIC CURVES
(continued)
220
:;-
.5-
d
~
2.6
2.4
~
14
w
~
i3
I
f!
:'i
""'-
~
w
""
1.2
-25
25
I\.
\
~
50
75
170
\
z
~
I
100
125
160
/
V
-
200
~
1S0
i'0
160
~
140
150
-55
-25
JUNCTION TEMPERATURE - (OC)
25
50
75
100
-
120
-55
125
.....
V
,..- V
-25
JUNCTION TEMPERATURE - (oG)
FIGURE 7.
MINIMUM SCR LATCH CURRENT
/
/
g
IL
'\
/
(10:= ABOVE THRESHOLD)
/
iii
10
-55
180
g
16
/
(10:!( ABOVE THRESHOLD)
I
i'...
2.0
18
z
,;"
22
"
~
190
"IN =15V
25
50
75
100
125
JUNCTION TEMPERATURE - (DC)
FIGURE 9.
SHUTDOWN DELAY TO OUTPUT VS. TEMPERATURE
FIGURES.
CURRENT SENSE DELAY VS. TEMPERATURE
•
50
S'
.5-
t5
~
"z
~
100
z
w
~
~
~
1.50
u
~
~
~
12.0
.5-
1.60
~
~
«
1.40
'"inz
I' r-- r-..
"-
"«
~
1.30
~
ffi
-55
-25
25
50
75
laO
11.0
90
"1"'-.
.......
6.0
50
4.0
-25
~
),L f,& C-
w
z
3.0
0
'i
~V
>=
«
~
2.0
;J,
1.0
o
75
100
2.0
"
1.0
~
z
>=
~
;J,
p-
o
:::::::; ~
p
/.
200
~
,,'
'\ ~ ~"J0c
300
./
~ -:::: ?
,. ...'2.50C
/'
/
-
;
120
iE
u
~
400
OUTPUT CURRENT - (mA)
FIGURE 13.
OUTPUT TRANSISTOR SATURATION VOLTAGE
VS. OUTPUT CURRENT (SOURCE TRANSISTOR)
500
k::: ~ ~
~
100
200
300
400
FIGURE 12.
OUTPUT TRANSISTOR SATURATION VOLTAGE
VS. OUTPUT CURRENT (SINK TRANSISTOR)
2000
Rp.8KCl
40
.5 1aoo
cl'y
t/
I
:;
0'
100
60
Ui' 1900
".......-
140
80
500
OUTPUT CURRENT - (mA)
RT"SKn
160
20
100
/
o '~
o
125
FIGURE 11.
ERROR AMP SINK CURRENT VS. TEMPERATURE
'/
5.0
g
50
0
180
60
?:
4.0
25
-
"~
3.0
JUNCTION TEMPERATURE - (OC)
FIGURE 10.
ERROR AMPLIFIER INPUT OFFSET VOLTAGE
VS. TEMPERATURE
";<:
i'...
70
JUNCTION TEMPERATURE - (OC)
40
w
80
-55
125
?:
-
-55
./
~
~
/
u
~
1700
1600
~C\.;
1500
1400
1300
i-"""
......... I--
V
1200
-25
25
50
75
100
JUNCTION TEMPERATURE - (DC)
FIGURE 14.
SYNC PULSEWIDTH VS. TEMPERATURE
4 - 213
125
-55
-25
25
50
75
100
JUNCTION TEMPERATURE - (DC)
FIGURE 15.
SYNC PULSEWIDTH VS. TEMPERATURE
125
SG18461SG1847 SERIES
CHARACTERISTIC CURVES (continued)
Rr~8K(l
~
Rr-BKO
26.5
I
i
iii0
V
u
z
w
/
[;]
"
[;] 2.75
V
250
-25
0
25
50
75
JUNCTION TEMPERATURE -
100
/
/'
2.65
125
-55
-25
(OC)
a
25
I
43
\!
42
§
4'
.......
CT=OOOl!!F, fq=8KCl
.............
........
I'-.
r-.....
U
/
tr-.....
40
39
38
50
75
JUNCnON TEMPERATURE -
FIGURE 16.
OSCILLATOR FREQUENCY VS. TEMPERATURE
g
44
~
Cf""O.lIJF
~
~
iii0
I-- roo-
-55
--
e'
CT".OOl IJF /
255
45
/
I
>-
26.0
e'
~
:::
~
/
46
2.85
100
125
-55
(OC)
-25
a
25
FIGURE 17.
OSCILLATOR FREQUENCY VS. TEMPERATURE
FIGURE 18.
DllTY CYCLE VS. TEMPERATURE
APPLICATION INFORMATION
lOOK
50K
20K
S
Ii
10K
5K
1/
2K
/
,
~
/1/
/
lK
lOpsec
lOOpsec
lOOOf.lsec
OSCILLA TOR PERIOD (ps)
FIGURE 19· OSCILLATOR FREQUENCY CURVES
..I...'V
11.2V
r~
IR~
t3.7V
SAWTOOTH~
(Pin 8)
osc~
(Pin 10)
-1
1--.
OUTPUT OEAOTIME (TO)
Oscillator frequency is approximated by the formula: fT ~
FIGURE 20 - OSCILLATOR CIRCUIT
4-214
50
75
JUNCTION TEMPERATURE -
~
RrCr
100
(OC)
125
SG18461SG1847 SERIES
APPLICATION INFORMATION (continued)
y:>,5"4---II+
t
O.5mA
Is
~
R
3
+
C
RS
4
7
-=-
COMP
FIGURE 22 - CURRENT SENSE AMPCONNECTIONS
FIGURE 21 - ERROR AMP OUTPUT CONFIGURATION
(Error amplifier can source up to O.5mA)
A small RC filter may be required in some applications to reduce switch
transients. Differential input allows remote, noise free switching.
SG1846
Vc
+-~-.......-o
FIGURE 23 - SINGLE ENDED BOOST CONFIGURATION
4 - 215
VOUT
S618461S61847 SERIES
APPLICATIONS INFORMATION (continued)
SG1846
H1N
YiN
II
BOUT
VOUT
I
-;;-
FIGURE 24 - BUCK CONVERTER WITH CURRENT SENSE WINDING
SG1846
+\\N
FIGURE 25 - PUSH/PULL CONVERTER WITH SLOPE COMPENSATION
4-216
SG18461SG1847 SERIES
APPLICATIONS INFORMATION (continued)
'5
o.sv
Rl CURRENT
,
LIMIT
COMP
R2 VREF
Peak Current (IS) is determined by the formula" IS'" Rl +R2 -0.5
3RS
FIGURE 26 - PULSE BY PULSE CURRENT LIMITING
CURRENT
R,
LIMIT
'ss
.IL 0-'61-"'==-1
FIGURE 27 - SOFT START AND SHUTDOWN/RESTART FUNCTIONS
CURRENT LIMIT
~
./I
O.5:~----V-----'>
SHUTDOWN
ON~'--_ _ _ _
----'n
OFF
L _ _ _ _ _-',
JUl--v < 0_8mA
---.r-
~ >3mA (LATCHED OFF)
1
1
FIGURE 28 - SHUTDOWN WITH AUTO-RESTART
FIGURE 29 - SHUTDOWN WITHOUT AUTO-RESTART (LATCHED)
If VREF < 0_8mA the shutdown latch will commutate
If
1
V
REF
> 3mA the device will latch off
1
when Iss < 0_8mA and a restart cycle will be initiated_
until power is recycled_
4-217
SG18461SG1847 SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Ambient
Temperature Range
Package
Part No.
16-PIN CERAMIC DIP
SG1846J/883B
SG1846J
SG2846J
SG3846J
SG1847J/883B
SG1847J
SG2847J
SG3847J
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
ooe to 70°C
-55°C to 125°C
-55°C to 125°C
-25°C to 85°C
ooe to 70°C
16-PIN PLASTIC DIP
N- PACKAGE
SG2846N
SG3846N
SG2847N
SG3847N
-25°C to 85°C
ooe to 70°C
-25°C to 85°C
ooe to 70°C
16-PIN WIDEBODY
PLASTIC S.O.I.C
OW-PACKAGE
SG2846DW
SG3846DW
SG2847DW
SG3847DW
-25°C to 85°C
ooe to 70°C
-25°C to 85°C
ooe to 70°C
J - PACKAGE
Connection Diagram
C.L.ISOFTSTART
SHUTDOWN
v,.,
+VIN
(-)C.S.
OUTPUTB
(+)C.S.
(+) ERROR AMP
(-) ERROR AMP
COMPENSATION
GROUND
OUTPUT A
SYNC
v,
R,
C,
C.L.ISOFTSTART
SHUTDOWN
v,.,
(-)C.S.
+VIN
OUTPUTB
(+)C.S.
(+) ERROR AMP
(-) ERROR AMP
COMPENSATION
GROUND
OUTPUT A
SYNC
v,
C,----,-'-'-_ _~- R,
16-PIN CERAMIC
FLAT PACK
F - PACKAGE (Note 3)
SG1846F/883B
SG1846F
SG1847F/883B
SG1847F
-55°C
-55°C
-55°C
-55°C
to 125°C
to 125°C
to 125°C
to 125°C
CLISOFTSTART
SHUTDOWN
VAH
+VIN
(.) C.S.
OUTPUT B
(+)C.S.
(+) ERROR AMP
(-) ERROR AMP
COMPENSATION
v,
GROUND
OUTPUT A
SYNC
~---~~--~---- ~
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L - PACKAGE (Note 3)
SG1846U883B
SG1846L
SG1847U883B
SG1847L
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C.
125°C
125°C
1. N.C.
2. C.L.ISOFTSTART
3. VREF
4. (-)C.6.
5. (+)C.S.
6. N.C.
7. (+) ERROR AMP
a. (-) ERROR AMP
9. COMPENSATION
10,CT
Notes:
3
2
1
20 19
11.N.C.
.40" "
12.RT
5
17
"
7
15
•
14
9
10 11 12 13
13. SYNC
14.0UTPUT A
15. GROUND
lS.N.C.
17.,Vc
la.OUTPUTB
19.Vw
20.SHUTDOWN
1. Contact factory for JAN and DESC part availability.
2. All parts are viewed from the top.
3. Consult factory for product availability.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4 - 218
SG3523/SG3423
SG3523A/SG3423A
liiMil
OVER-VOLTAGE SENSING CIRCUIT
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
This monolithic integrated circuit provides the control functions necessary to
protect sensitive electronic circuitry from over-voltage transients or the effects
of voltage regulator failure. It is designed for use with an external SeR "crowbar"
for immediate shutdown of the power supply, but additionally provides logic level
outputs for regulator turn-off and / or operator or system out-of-tolerance
indication.
o Operation from 4.5V to 40V
This device contains an accurate, stable 2.6V reference which allows the
sensing threshold to be set predictably without the need for potentiometers. An
external capacitor can be used to program an accurate time delay between fault
occurence and crowbar triggering, but this delay may be bypassed by inputing
at the Sense 2 terminal or by using the remote activation capability.
HIGH RELIABILITY FEATURES
- SG3523/SG3523A
o
Highly accurate sensing threshold
o Built-in input hysteresis
o Programmable time delay
o
o
~
~
SCR "Crowbar" drive of 200mA
Remote activation capability
Available to MIL-STD-883B
SG level "S" processing available
For additional circuit functions, see SG1542 and SG1543 data sheets.
BLOCK DIAGRAM
2.6V
REF
OUTPUT
INDICATOR
OUTPUT
GROUND
SENSE 1
CURRENT
SOURCE
SENSE 2
See Application Notes for additional information.
April 1990
4 -219
•
SG35231SG34231SG3523AISG3423A
ABSOLUTE MAXIMUM RATINGS (Note I)
Input Supply Voltage (V ,N) ................................................... 40V
Sense Voltage (1) Input Range ..............................................V,N
Sense Voltage (2) Input Range .....................•.................... 6.5V
Reference Load Current ................................................... 10mA
Indicator Output Voltage ..................................................... 40V
Note I. Values beyond which damage may occur.
Indicator Output Current .................................................. SOmA
Operating Junction Temperatures
Hermetic (V-Packages) ................................................ 150°C
Plastic (M-Packages) .................................................. 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) ........•........... 300°C
THERMAL DERATING CURVES
2.5
5.0
20
4.0
I"
I"
~
I
~
iii
c
~
~
1.5
I 3.0
'0 ~
~
f':::
6
~",.
(8...,0",
~s
~C'
I~"'-)
05
0
i I'-. ~
5
0
25
50
75
125
150
...........
~
"'-)
100
2.0
0
175
AMBIENT TEMPERATURE - "c
~
4f (8....pt'"
tJ
l:-4,s"l):
1.0
r~ ~ ~
0
25
50
75
100
125
150
175
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION VB AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION VB CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Indicator Output Current ....................................... OmA to 10mA
Input Supply Voltage (V,N) ...................................... 4.7V to 40V
Delay Timing Capacitor (Note 2) ................................ 0jJ.F to ljJ.F
Sense Voltage (1) Input Range ............................ OV to V,N -3V
Operating Ambient Temperature Range
Sense Voltage (2) Input Range ................................ OV to 5.5V
SG3523/3523A ........•..................................... -55°C to 125°C
Reference Load Current ...................................... OmA to 10mA
SG3423/3423A ................................................... O°C to 70°C
Indicator Output Voltage ........................................ 4.7V to 40V
Note 2. Larger value capacitor may be used with peak current limiting. See Figure I.
Note 3. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG3523JSG3523A with -55°C,;; TA,;; 125°C, SG34231
SG3423A with ooe,;; TA ,;; 70°C, and V,N = IOV. Low duty cycle pulse testing techniques are used which maintains Junction and case temperatures equal
to the ambient temperature.)
8G3523A
8G3423/8G3523
8G3423A
Parameter
Test Conditions
Units
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
V
Supply Voltage Range
4.5
40 4.5
40 4.5
40
TA =25°C to TMAJ(
V
4,7
40 4.7
40 4.7
40
TA = TMIN to TMAX
7
5
7
5
Supply Current
10
mA
5
V
Sense Threshold
2.55 2.60 2.65 2.50 2.60 2.70 2.45 2.60 2.75
TJ = 25°C
V
2.50
2.70 2.45
2.75 2.35
2.85
TA =TUIN to TMAJ(
mV
25
Input Hyteresis
Sense 1 only
25
25
Input Bias Current
-0.3 -1.0
-0.3 -1.0
-0.3
Sense 1
!LA
jJ.A
Sense 2
+5 +10
+5 +10
+5
Delay Current
200 250 350 200 250 350 150 250 350
!LA
Remote Actiyation Input Current
40
40
40
5
5
5
VpIN5 = 2.0V
itA
-120 -250
-120 -250
-120 -250 !LA
VpINs =0.8V
V
Output Voltage
y,.-2.5 y'N-I .6
10= 100mA
y'N-2.5 y'N-I .6
y'N-2.5 y'N-I .6
200
mA
Peilk Output Current
100 200 600 100 200 600
V,N =5V, Vo=OV
0.1
0.1
V
Output Off Voltage
V,N = 40V
0
0
0
V
0.1
0.1
0.1
Indicator Saturation Voltage
IL = -1.6mA
V
0.2 0.5
0.2 0.5
0.4
IL =-10mA
Indicator Leakage
0.1 1_0
0.1 1.0
VpIN6 = 40V
0.1 1.0
!LA
Propagation Delay to Output
TJ = 25°C, Sense 1
1.0
1.0
1.0
jJ.S
0.5
0.5
0.5
TJ = 25°C, Sense 2
jJ.S
mAljJ.s
400
400
Output Current Rise Time
400
TJ = 25°C
4-220
SG35231SG34231SG3523AISG3423A
APPLICATION INFORMATION
J
lOon
The loon resistor limits the peak discharge current into the SG3523
while the external PNP transistor provides a high peak-current
discharge path for the delay capacitor.
SG3523
r---A,>/VAV---1I---{l DELAY
a......_ _ _...
CDELAY.!.""
2N2907
FIGURE 1 • SURGE LIMIT CIRCUIT FOR LARGE DELAY CAPACITORS
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Pac/(age
8-PIN CERAMIC DIP
y- PACKAGE
8-PIN PLASTIC DIP
M-PACKAGE
Part No.
SG3523AY/883B
SG3523AY
SG3523Y/883B
SG3523Y
SG3423AY
SG3423Y
SG3423AM
SG3423M
Ambient
Temperature Range
-55°e
-55°e
-55°e
-55°e
ooe
ooe
to 125°e
to 125°e
to 125°e
to 125°e
to 70 0 e
to 70 0 e
Connection Diagram
+v"
O.
2
7
OUTPUT
GROUND
SENSE 2 ,
•
INDICATOR OUT
5
REMOTE ACT.
SENSE 1
CURRENT SOURCE
4
ooe to 70 0 e
ooe to 70 0 e
Note 1. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4-221
•
4 - 222
SG7800AISG7800AC
SG7800lSG7800C
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
POSITIVE FIXED VOLTAGE REGULATOR
DESCRIPTION
FEATURES
The SG7800NSG7800 series of positive regulators offer self contained, fixedvoltage capability with up to 1.5A of load current and input voltage up to 50V
(SG7800A series only). These units feature a unique on-chip trimming system
to set the output voltages to within ±1.5% of nominal on the SG7800A series,
±2.0% on the SG7800 series, and ±4.0% on the SG7800C/340 series. The
SG7800A versions also offer much improved line and load regulation characteristics. Utilizing an improved Bandgap reference design, problems have been
eliminated that are normally associated with the Zener diode references, such
as drift in output voltage and large changes in the line and load regulation.
• Output voltage set internally to ±1.5% on
sG7800A
• Input voltage range to 50V max. on SG7800A
• Two volt input-output differential
• Excellent line and load regulation
• Foldback current limiting
• Thermal overload protection
• Voltagesavailable-5V, 6V, 8V, 12V, 15V, 18V,
20V,24V
All protective features of thermal shutdown, current limiting, and safe-area
control have been designed into these units and since these regulators require
only a small output capacitor for satisfactory performance, ease of application
is assured.
HIGH RELIABILITY FEATURES
- SG7800A/7800
~
~
Although designed as fixed-voltage regulators, the output voltage can be
increased through the use of a simple voltage divider. The low quiescent drain
current of the device insures good regulation when this method is used.
~
~
~
~
Product is available in hermetically sealed TO-257 (both isolated and nonisolated), TO-3, T039 and TO-66 power packages.
~
~
~
Available to MIL-sTD - 883
MIL-M38510/10702BXA - JAN7805T
MIL-M38510/10703BXA - JAN7812T
MIL-M38510/10704BXA - JAN7815T
MIL-M38510/10706BVA - JAN7805K
MIL·M3851 0/1 0707BVA • JAN7812K
MIL·M38510/10708BVA· JAN7815K
Radiation data available
SG level "5" processing available
SCHEMATIC DIAGRAM
R1B
'-----vv.,.---+---(j;2 Vour
Vos
April 1990
4-223
SG7800AISG7800 SERIES
POSITIVE REGULATOR
ABSOLUTE MAXIMUM RATINGS (Note 1)
Device
Input Voltage
Output Voltage
5V
6V
8V
12V
15V
18V
20V
24V
Input Voltage
(transient) (Note 3)
Input Voltage·Differential
(Output shorted to ground)
50V
50V
50V
50V
50V
50V
50V
50V
35V
35V
35V
35V
35V
35V
35V
35V
35V
35V
35V
35V
35V
35V
35V
40V
Operating Junction Temperature
Hermetic (K, R, T, G, IG - Packages) ........................... 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Values beyond which damage may occur.
THERMAL DERATING CURVES
~
~
is
is
~
~
~
~
~
~
"
"
i
i
175
'75
AMBIENT TEMPERATURE - "c
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Operating Junction Temperature Range:
SG7800 ......................................................... -55°C to 150°C
SG7800C .......................................................... O?C to 125°C
Note 2. Range over which the device is functional.
CHARACTERISTIC CURVES
G, lG, K, R, ,& P Pkg Ollly)
lNo=200mV
'\
1'\
--1\ '\
l
-"
"
v~~\5'0
v~
)<
I,t
~d'o
~~~o
o
o
Note 3. Operation at high input voltages is dependent upon load current. When
load current is less than SmA, output will rise out of regulation as inputoiutput differential icreases beyond 30V. Note also from Figure 1, that
maximum load current is reduced at high voltages. The SOV input
rating of the SG140A series refers to ability to withstnd high line or
transient conditions without damage. Since the regulator's maximum
current capability is reduced, the output may fall out of regulation at
high input voltages under nominal loading.
I
C'"
(l
'1\.r\. r\.
I I\- r\ r\.
10
20
30
40
50
INPUT-OUTPUT VOLTAGE DIFFERENTIAL - (V)
FIGURE 1.
PEAK OUTPUT CURRENT
vs. INPUT· OUTPUT DIFFERENTIAL
4-224
SG7800AISG7800 SERIES
POSITIVE REGULATOR
CHARACTERISTIC CURVES (continued)
?:
-
I
"'"~
60
JyV/
::>
~
V'I:p
~
50
I
is
/'
1
~
m
'r V "
>
>-
..
~SG7805/140-5
"
~4Y
2
0
i
70
/1//
3
~
30
it
20
'j
G, IG, )(, R, & P Pkg. Only
"
l,vo=200mV
40
~~ ~~;~i:v +;~JV
lo"lOOmA
TJ=2SoC
5G7615/140 15
~
~
5G7824)140-24 \
0
1
3
2
r--. ~o:.:.. ......
"- ......
I'-..
~
'l=15A
w -0.4
";0
g -0.6
~
>-
~
~
0
-0.8
ViN=15V
'lour-lOr
-1.0
10
100
LOAD CURRENT - (A)
1K
10K
FREQUENCY -
FIGURE 2.
MINIMUM INPUT - OUTPUT VOLTAGE
VS. LOAD CURRENT
-.
~ -0.2
0
0
0
I
~,
\
10
02
lOOK
-75 -50 -25 0
1M
25
50
75 100 125 150
TEMPERATURE-(OC)
(Hz)
FIGURE 3.
RIPPLE REJECTION VS. FREQUENCY
FIGURE 4.
TEMPERATURE COEFFICIENT OF OUTPUT VOLTAGE
APPLICATIONS
II SG7800/140 12
II
INPUT
O.33pF .. +
[3
OUTPUT
INPUT
+O.,PF.
J• INCREASING VALUE OF OUTPUT CAPACITOR
IMPROVES SYSTEM TRANSIENT RESPONSE
..
"~"'t
REQUIRED ONLY IF REGULA TOR IS LOCATED
AN APPRECIABLE DISTANCE FROM POWER
SUPPLY FILTER
31
~IQ
\b=Vxx(l+
~n+
2
OUTPUT
,I
Vr
Ril
TO.
,PF
R2
b R2
-=-
FIGURE 6 - CIRCUIT FOR INCREASING OUITPUT VOLTAGE
FIGURE 5 - FIXED OUITPUT REGULATOR
INPUT V
I SG7800/140
Rsc
"~
2N4398
11 SG780S/140 12
1
J
3
INPUT
30
2N6124
O.33pF
T
11 SG7800/140 12
1
1
t
~
D
OUTPUT
TO.'"F
033
j
'T
P
1KO
"-' OUTPUT
~"
=;: 0.1p'
10K
~
FIGURE 7 - HIGH OUTPUT CIRRENT, SHORT CIRCUIT PROTECTED
FIGURE 8 - ADJUTABLE OUITPUT REGULATOR, 7V 10 30V
4-225
•
S.OV POSITIVE REGULATOR.
SG7800AISG7800 SERIES
ELECTRICAL SPECIFICATIONS (Note 1)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG7805A1SG7805 with -55°C ,s; T. ,s; 150°C,
SG7805AC/SG7805C with O°C ,s;T.,s; 125°C, VrN = 10V, 10 = 500mA for the K, R, G and IG -Power Packages-, 10 = 1OOmAforthe T package, CrN = O.33jlF,
and COUT = O.1jlF. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambienttemperatire.)
SG7805A1SG7805
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 25°C
VIN = 7.5V to 20V, TJ = 25°C
V1N = 8V to 12V, TJ = 25°C
Power Pkgs: 10 = 5mA to 1.5A, TJ = 25°C
10 = 250mA to 750mA, TJ = 25°C
T - Pkg: 10 = 5mA to 500mA, TJ = 25°C
VIN =8V to 20V
Power Pkgs: 10 = 5mA to 1.0A, P :5 20W
T - Pkg: 10 = 5mA to 500mA, P :5 2W
Over Temperature Range
TJ =2SoC
With Line: V1N = BV to 25V
With Load: 10 = SmA to 1.0A (Power Pkgs.)
10 = 5mA to 500mA (T)
AVo = 100mV, TJ =25°C
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = 500mA
Power Pkgs: V1N = 10V, TJ = 2SoC
T - Pkg: V1N = 10V, TJ = 25°C
Power Pkgs: V1N = 35V, TJ = 25°C
T - Pkg: V1N = 35V, TJ = 25°C
AV1N = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 125°C
10= 5mA
SG7805A
SG7805
Min. Typ_ Max. Min. Typ. Max.
4.92 5.00 5.0B 4.BO 5.00 5.20
5
25
50
5
2
2
12
25
15
15
50
50
5
25
5
25
20
100
5
25
4.B5 5.00
4.85 5.00
4
1.5
O.S
2
2.0
1.0
5.15
5.15
7
6
O.B
0.5
0.5
2.S
3.3
2.0
1.2
0.7
4.65
4.65
5.00
5.00
4
1.5
0.5
2
2.0
1.0
V
V
mA
mA
mA
mA
mA
2.5
3.3
2.0
1.2
0.7
V
A
A
A
A
dB
IlV/V
mV
°C
40
40
20
17S
V
mV
mV
mV
mV
mV
5.35
5.35
7
6
0.8
0.5
0.5
68
68
Units
20
175
SG7805AC/SG7805C
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 25°C
V1N = 7.5V to 20V, TJ = 25°C
V1N = aVto 12V, TJ = 25°C
Power Pkgs: 10 = 5mA to 1.5A, TJ = 25°C
10 = 250mA to 750mA, TJ = 25°C
T - Pkg: 10 = SmA to SOOmA, TJ = 25°C
V1N = 8V to 20V
Power Pkgs: 10 = 5mA to 1.0A, P :5 20W
T - Pkg: 10 = SmA to 500mA, P :5 2W
Over Temperature Range
TJ = 25°C
With Line: V1N = 8V to 25V
With Load: 10 = 5mA to 1.0A (Power Pkgs.)
10 = 5mA to SOOmA (T)
AVo = 100mV, TJ = 25°C
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = 500mA
Power Pkgs: TJ = 25°C
T - Pkg: TJ = 25°C
Power Pkgs: V1N = 3SV, TJ = 25°C
T - Pkg: V1N = 35V, TJ = 25°C
AV1N = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 125°C
10=5mA
SG7aOSAC
SG7805C
Min. Typ. Max. Min. Typ. Max.
4.92 5.00 5.08 4.BO 5.00 S.20
100
5
S
50
2
25
4
50
100
50
10
5
25
50
100
2S
4.85 S.OO
4.85 5.00
4
1.5
0.5
2.5
3.3
2.0
1.2
0.7
4.75
4.75
S.OO
5.00
4
1.5
0.5
2
2.0
1.0
40
20
175
V
V
mA
mA
mA
mA
mA
2.S
3.3
2.0
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
40
20
175
V
mV
mV
mV
mV
mV
5.25
5.25
8.5
B
1.3
0.5
0.5
62
68
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4-226
2
2.0
1.0
5.15
5.15
7
6
1.0
0.5
0.5
Units
SG7800AISG7800 SERIES
6.0V POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG7806NSG7806 with -55°C,;; T. ,;; 150°C,
SG7806AC/SG7806C with O°C,;; T.,;; 125°C, V,N =11V, 10 =500mA for the K, R, G and IG -Power Packages-, 10 =1OOmA forthe T package, C'N =0.33fiF,
and COUT = 0.1 fiF. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperatire.)
SG7806A1SG7806
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 2SoC
VIN = 8.SV to 2SV, TJ = 2SoC
VIN = 9V to 13V, TJ = 2SoC
Power Pkgs: 10 = SmA to 1.SA, TJ = 2SoC
10 = 2S0mA to 7S0mA, TJ = 2SoC
T - Pkg: 10 = SmA to SOOmA, TJ = 2SoC
VIN = 9V to 21V
Power Pkgs: 10 = SmA to 1.0A, P ~ 20W
T - Pkg: 10 = SmA to SOOmA, P ~ 2W
Over Temperature Range
TJ = 2SoC
With Line: VIN = 8V to 25V
With Load: 10 = SmA to 1.0A (Power Pkgs.)
10 = 5mA to 500mA (T)
f.Va= 100mV, TJ =2SoC
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = 500mA
Power Pkgs: TJ = 2SoC
T - Pkg: TJ = 2SoC
Power Pkgs: VIN = 3SV, TJ = 2SoC
T - Pkg: VIN = 35V, TJ = 2SoC
tNIN = 10V, f = 120Hz, TJ = 2SoC
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 12SoC
10 = 5mA
SG7606A
SG7806
Min. Typ. Max. Min. Typ. Max.
S.7S 6.00 6.2S
S.9
6.0
6.1
60
6
6
30
IS
3
30
3
20
20
60
60
6
6
30
30
30
30
S.82 6.00
S.82 6.00
4
I.S
O.S
2
2.0
1.0
6.18
6.18
7
6
0.8
O.S
O.S
2.5
3.3
1.7
1.2
0.7
S.65
S.65
6.00
6.00
4
I.S
O.S
2
2.0
1.0
V
V
mA
mA
mA
mA
mA
2.S
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
40
40
24
175
24
175
V
mV
mV
mV
mV
mV
6.35
6.35
7
6
0.8
O.S
O.S
6S
6S
Units
SG7806AC/SG7806C
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 25°C
VIN = 8.SV to 25V, TJ = 25°C
VIN = 9V to 13V, TJ = 2SoC
Power Pkgs: 10 = 5mA to 1.5A, TJ = 2SoC
10 = 2S0mA to 750mA, TJ = 2SoC
T - Pkg: 10 = 5mA to 500mA, TJ = 25°C
VIN = 9V to 21V
Power Pkgs: 10 = SmA to 1.0A, P ~ 20W
T - Pkg: 10 = 5mA to SOOmA, P ~ 2W
Over Temperature Range
TJ = 2SoC
With Line: VIN = 8V to 2SV
With Load: 10 = 5mA to 1.0A (Power Pkgs.)
10 = SmA to 500mA (T)
f.Va = 100mV, TJ = 2SoC
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = SOOmA
Power Pkgs: TJ = 2SoC
T - Pkg: TJ = 25°C
Power Pkgs: VIN = 35V, TJ = 25°C
T - Pkg: VIN = 35V, TJ = 25°C
f.VIN = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 125°C
10= 5mA
SG7806AC
SG7806C
Min. Typ. Max. Min. Typ. Max.
5.9 6.0
6.1 5.7S 6.00 6.2S
12
6
120
60
6
3
60
30
2S
120
15
60
10
60
S
30
60
30
5.82 6.00
5.82 6.00
4
I.S
0.5
2.5
3.3
1.7
1.2
0.7
5.7
5.7
6.0
6.0
4
I.S
0.5
2
2.0
1.0
V
V
mA
mA
mA
mA
mA
2.5
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
40
40
24
175
24
175
V
mV
mV
mV
mV
mV
6.3
6.3
8.5
8
1.3
O.S
O.S
59
62
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4 - 227
2
2.0
1.0
6.18
6.18
7
6
1.0
O.S
0.5
Units
SG7800AISG7800 SERIES
8.0V POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG7808NSG7808 with -55°C S TA S 150°C,
SG7808AC/SG7808C with O°C S TA S 125°C, V,N = 14V, 10 = 500mAforthe K, R, G and IG -Power Packages-, 10 = 1OOmA forthe T package, C'N = O.33I1F,
and COUT = O.lI1F. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambienttemperatire.)
SG7808A1SG7808
Parameter
Test Conditions
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
TotalOutputvoltage
Tolerance
'.'
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current.
Ripple Rejection
Output Noise Voltage (rms)
Long Tem1 Stability
Thermal Shutdown
TJ =2SoC
VIN = I 0.5V to 25V, TJ =2SoC
VIN = 11V to 17V, TJ = 2SoC
Power Pkgs: 10 = 5mA to 1.5A, TJ = 25°C
10 = 250mA to 750mA, TJ = 2SoC
T - Pkg: 10 = SmA to 500mA, TJ =25°C
VIN = 11.SV to 23V
Power Pkgs: 10 =5mA to I.OA, P ::; 20W
T - Pkg: 10 =SmA to SOOmA, P ::; 2W
Over Temperature Range
TJ =25°C
With Line: VIN =11.5V to 2SV
With Load: 10 =SmA to 1.0A (Power Pkgs.)
10 =SmA,to SOOmA (T)
AVo" 100mV, TJ =2SoC
Power Pkgs: 10 =1.0A, T - Pkg: 10 =500mA
Power Pkgs; TJ = 2SoC
T - Pkg: TJ =25°C
Power Pkgs: VIN =35V, TJ =2SoC
T - Pkg: VIN = 10V, TJ = 25°C
AViN =10V, f =120Hz, TJ .. 2SoC
f =10Hz to 100KHz (Note 2)
1000hrs. atTJ = 125°0
10 =5mA
SG7808A
SG7808
Min. Typ. Max. Min. Typ. Max.
7.88 8.00 8.12 7.7 8.00 8.3
8
80
8
40
4
4
40
20
24
24
70
80
8
8
40
3S
8
40
8
35
7.76 8.00 8.24
7.76 8.00 8.24
7
4
6
0.8
0.5
0.5
1.S
0.5
2
2.0
1.0
2.S
3.3
1.7
1.2
0.7
62
7.6
7.6
8
8
4
1.S
O.S
2
2.0
1.0
V
mV
mV
mV
mV
mV
8.4
8.4
7
6
0.8
O.S
0.5
V
V
mA
mA
mA
mA
mA
2.5
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°0
62
32
175
Units
32
175
SG7808AC/SG7808C
Parameter
Test Conditions
TJ =2SoC
(No~e 1)
VIN =1O.SV to 25V, TJ =25°C
VIN .. l1V to 17V, TJ .. 2s00
Load Regulation (Note 1)
Power Pkgs: 10 =SmA to 1.5A, TJ =2SoC
10 .. 2S0mA to 7S0mA, TJ =2SoC
..
T - Pkg: 10 =SmA to 500mA, TJ =25°C
Total Output Voltage
VIN = 11.5V to 23V
Tolerance
Power Pkgs: 10 = 5mA to 1.0A, P ::; 20W
T - Pkg: 10 .. SmA to SOOmA, P::; 2W
Quiescent Current
Over Temperature Range
TJ = 25°C
Quiescent Current Change
With Line: VIN =11.5V to 25V
With Load: 10 = 5mA to 1.0A (Power Pkgs.)
10 =SmA to SOOmA (T)
. AVo = 100mV, TJ .. 2SoC
.
Dropout Voltage
Power Pkgs: 10 = 1.0A, T - Pkg: 10 =500mA
Power Pkgs: TJ = 2SoC
Peak oUtput Current
T - Pkg: TJ =25°C
Power Pkgs: VIN = 35V, TJ .. 25°C
Short Circuit Current
T - Pkg: VIN = 35V, TJ =25°C
AVIN =10V, f .. 120Hz, TJ =2SoC
Ripple Rejection
Output Noise Voltage (rms) f = 10Hz to 100KHz (Note 2)
Long Tem1 Stability
1000hrs. at TJ =125°C
Thermal Shutdown
lo=5mA
Output Voltage
Line Regulation
SG7808AC
SG7808C
Min. Typ. Max. Min. Typ. Max.
7.88 8.00 8.12 7.7
8.0
8.3
16
160
8
80
4
8
80
40
24
40
160
80
16
80
8
40
16
80
8
40
7.76 8.00 8.24
7.76 8.00 8.24
7
4
6
1.0
O.s
0.5
I.S
0.5
2.5
3.3
1.7
1.2
0.7
62
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4-228
2
2.0
1.0
7.6
7.6
8.0
8.0
4
8.4
8.4
8.5
8
1.0
0.5
0.5
1.5
O.S
2
2.0
1.0
2.5
3.3
1.7
1.2
0.7
S5
40
32
175
40
32
175
Units
V
mV
mV
mV
mV
mV
V
V
mA
mA
mA
mA
mA
V
A
A
A
A
dB
IlVN
mV
°C
SG7800AISG7800 SERIES
12V POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG7812A1SG7812 with -55°C S T. S 150°C,
SG7812AC/SG7812C with O°C ST. S125°C, V,N = 19V, '0= 500mA forthe K, R, G and IG -Power Packages-, 10 = 100mA forthe T package, C'N =O.33I1F,
and COUT = O.1I1F. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambienttemperatire.)
SG7812A1SG7812
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peal{ Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 25°C
VIN = 14.5V to 30V, TJ = 25°C
VIN = 16V to 22V, TJ = 25°C
Power Pkgs: 10 = 5mA to 1.5A, TJ = 25°C
10 = 250mA to 750mA, TJ = 25°C
T - Pkg: 10 = 5mA to 500mA, TJ = 25°C
VIN = 15.5V to 27V
Power Pkgs: 10 = 5mA to 1.0A, P ::; 20W
T - Pkg: 10 = 5mA to 500mA, P ::; 2W
Over Temperature Range
TJ = 25°C
With Line: VIN = 15V to 30V
With Load: 10 = 5mA to 1.0A (Power Pkgs.)
'0 = 5mA to 500mA (T)
!1Vo = 100mV, TJ = 25°C
Power Pkgs: '0 = 1.0A, T - Pkg: '0 = 500mA
Power Pkgs: TJ = 25°C
T - Pkg: TJ = 25°C
Power Pkgs: VIN = 35V, TJ = 25°C
T - Pkg: VIN = 35V, TJ = 25°C
!1VIN = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 125°C
10=5mA
SG7812A
SG7812
Min. Typ. Max. Min. Typ. Max_
11.8 12.0 12.2 11.5 12.0 12.5
12
12
120
60
6
30
6
60
28
120
28
80
10
60
10
40
10
10
40
60
11.7 12.0 12.3
11.7 12.0 12.3
7
4
6
0.8
0.5
0.5
1.5
0.5
2
2.0
1.0
2.5
3.3
1.7
1.2
0.7
11.4
11.4
12.0
12.0
4
1.5
0.5
2
2.0
1.0
V
V
mA
mA
mA
mA
mA
2.5
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
40
40
48
175
48
175
V
mV
mV
mV
mV
mV
12.6
12.6
7
6
0.8
0.5
0.5
61
61
Units
SG7812AC/SG7812C
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ - 25°C
VIN = 14.5V to 30V, TJ = 25°C
VIN = 16V to 22V, TJ = 25°C
Power Pkgs: 10 = 5mA to 1.5A, TJ = 25°C
10 = 250mA to 750mA, TJ = 25°C
T - Pkg: '0 = 5mA to 500mA, TJ = 25°C
VIN = 15.5V to 27V
Power Pkgs: 10 = 5mA to 1.0A, P ::; 20W
T - Pkg: 10 = 5mA to 500mA, P::; 2W
Over Temperature Range
TJ = 25°C
With Line: VIN = 15V to 30V
With Load: 10 = 5mA to 1.0A (Power Pkgs.)
'0 = 5mA to 500mA (T)
/!"vo = 100mV, TJ = 25°C
Power Pkgs: 10 = 1.0A, T - Pkg: '0 = 500mA
Power Pkgs: TJ = 25°C
T - Pkg: TJ = 25°C
Power PI{gs: VIN = 35V, TJ = 25°C
T - Pkg: VIN = 35V, TJ = 25°C
!1VIN = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 125°C
10=5mA
SG7812C
SG7812AC
Min. Typ. Max. Min. Typ. Max.
11.8 12.0 12.2 11.5 12.0 12.5
240 240
12
120
12
120
6
60
240
28
120
80
10
24
120
60
24
120
10
60
11.7 12.0
11.7 12.0
4
1.5
0.5
2.5
3.3
1.7
1.2
0.7
51
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4- 229
2
2.0
1.0
12.3
12.3
7
6
1.0
0.5
0.5
11.4 12.0
11.4 12.0
4
1.5
0.5
2
2.0
1.0
48
175
V
V
mA
mA
mA
mA
mA
2.5
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
40
48
175
V
mV
mV
mV
mV
mV
12.6
12.6
8.5
8
1.0
0.5
0.5
55
40
Units
SG7800AISG7800 SERIES
15V POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG7815NSG7815 with -55°C S T. S 150°C,
SG7815AC/SG7815C with O°C ST. S125°C, V,N = 23V, 10 = 500mA for the K, R, Gand IG -Power Packages-, 10 = 1OOmA forthe T package, C'N = O.3311F,
and COUT = O.lI1F. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambienttemperatire.)
SG7815A1SG7815
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ =25°C
V1N = 17.5V to 30V, TJ =25°C
VIM =20V to 2SV, TJ =25°C
Power Pkgs: 10 =5mA to 1.5A, TJ =25°C
10 =250mA to 750mA, TJ =25°C
T - Pkg: 10 =5mA to 500mA, TJ =25°C
VIN =18.5V to 30V
Power Pkgs: 10 =5mA to 1.0A, P ~ 20W
T - Pkg: 10 =5mA to 500mA, P ~ 2W
Over Temperature Range
TJ =25°C
With Line: VIN =18.5V to 30V
With Load: 10 =5mA to 1.0A (Power Pkgs.)
10 =5mA to 500mA (T)
INo =100mV, TJ =25°C
Power Pkgs: 10 =1.0A, T - Pkg: 10 =500mA
Power Pkgs: TJ =25°C
T - Pkg: TJ =25°C
Power Pkgs: VIN =35V, TJ =25°C
T - Pkg: VIN =35V, TJ =25°C
ININ = 10V, f =120Hz, TJ =25°C
f =10Hz to 100KHz (Note 2)
1000hrs. at TJ =125°C
10=5mA
SG7815A
SG7815
Min. Typ. Max. Min. Typ. Max.
14.8 15.0 15.2 14.4 15.0 15.S
15
15
75
150
8
75
40
8
30
150
30
100
12
75
12
50
12
75
12
50
14.S 15.0 15.4
14.S 15.0 15.4
7
4
6
0.8
0.5
0.5
1.5
0.5
2
2.2
0.9
2.5
3.3
1.7
1.2
0.7
14.3 15.0 15.7
14.3 15.0 15.7
7
4
6
O.B
0.5
0.5
1.5
0.5
2
2.2
0.9
2.5
3.3
1.7
1.2
0.7
60
SO
40
40
SO
175'
60
175
Units
V
mV
niv
mV
mV
mV
V
V
mA
mA
mA
mA
mA
V
A
A
A
A
dB
JlVN·
mV
°C
SG7815AC/SG7815C
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term StabilitY
Thermal Shutdown
Test Conditions
TJ -25°C
VIN = 17.5V to 30V, TJ =25°C
VIN =20V to 2SV, TJ =25°C
Power Pkgs: 10 = 5mA to 1.5A, TJ =25°C
10 =250mA to 750mA, TJ =25°C
T - Pkg: 10 =5mA to 500mA, TJ = 25°C
VIM = 13.5V to 30V
Power Pkgs: 10 = 5mA to 1.0A, P ~ 20W
T - Pkg: 10 - SmA to 500mA, P ~ 2W
Over Temperature Range
TJ =25°C
With Line: VIN = 18.5V to 30V
With Load: 10 =5mA to 1.0A (Power Pkgs.)
10 = 5mA to 500mA (T)
!No =100mV, TJ =25°C
Power Pkgs: 10 = 1.0A, T - Pkg: 10 =500mA
Power Pkgs: TJ =25°C
T - Pkg: TJ =25°C
Power Pkgs: VI/ol =35V, TJ =25°C
T - Pkg: VIN =35V, TJ =25°C
I1VIN =10V, f =120Hz, TJ =25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ .. 125°C
10 = 5mA
SG7815AC
SG7815C
Min. Typ. Max. Min. Typ. Max.
14.8 15.0 15.2 14.4 15.0 15.S
30
15
150
300
15
150
8
75
100 300
30
150
12
30
150
75
12
30
150
75
14.S 15.0 15.4 14.3
14.S 15.0 15.4 14.3
7
4
6
1.0
0.5
0.5
2
1.5
0.5
0.9
2.5
3.3
1.7
1.2
0.7
1.5
0.5
2
2.2
0.9
2.5
3.3
1.7
1.2
0.7
SO
SO
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4-230
2~2
15.0 15.7
15.0 15.7
B.5
4
8
1.0
0.5
0.5
40
SO
175
40
SO
175
Units
V
mV
mV
mV
mV
mV
V
V
mA
rnA
mA
mA
mA
V
A
A
A
A
dB
JlVN
mV
°C
SG780()AISG7800 SERIES
18V POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG7818A1SG7818 with -55'C ,;; TA ,;; 150'C,
SG7818AC/SG7818C with O'C';; TA ,;; 125'C, V,N = 27V, 10 = 500mA for the K, R, G and IG -Power Packages-, 10 = 1OOmA forthe T package, C'N = O.3311F,
and COUT = O.1I'F. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperatire.)
SG7818A1SG7818
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peal{ Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 2SoC
VIN = 21 V to 33V, TJ = 2SoC
VIN = 24V to 30V, TJ = 2SoC
Power Pkgs: 10 = SmA to 1.SA, TJ = 2SoC
10 = 2S0mA to 7S0mA, TJ = 25°C
T - Pkg: 10 = SmA to SOOmA, TJ = 2SoC
VIN = 22V to 33V
Power Pkgs: 10 = SmA to 1.0A, P S; 20W
T - Pkg: 10 = SmA to SOOmA, P S; 2W
Over Temperature Range
TJ = 2SoC
With Line: VIN = 28V to 38V
With Load: 10 = SmA to 1.0A (Power Pkgs.)
10 = SmA to SOOmA (T)
!:l.Vo = 100mV, TJ = 2SoC
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = SOOmA
Power Pkgs: TJ = 2SoC
T - Pkg: TJ = 2SoC
Power Pkgs: VIN = 3SV, TJ = 25°C
T - Pkg: VIN = 3SV, TJ = 2SoC
tWIN = 10V, f = 120Hz, TJ = 2SoC
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 12SoC
10=SmA
SG7818A
SG7818
Min, Typ. Max. Min. Typ. Max.
17.7 18.0 18.3 17.3 18.0 18.7
20
20
90
180
10
10
4S
90
40
40
120
180
15
lS
60
90
lS
lS
60
90
17.S 18.0 18.S
17.5 18.0 18.S
7
4
6
0.8
O.S
O.S
1.S
O.S
2
2.2
0.9
2.S
3.3
1.7
1.2
0.7
17.1
17.1
18.0
18.0
4
1.S
O.S
2
2.2
0.9
V
V
mA
rnA
mA
mA
mA
2.S
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
40
40
72
175
V
mV
mV
mV
mV
mV
18.9
18.9
7
6
0.8
O.S
O.S
S9
S9
Units
72
175
SG7818AC/SG7818C
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peal< Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 2SoC
VIN = 21V to 33V, TJ = 2SoC
VIN = 24V to 30V, TJ = 25°C
Power Pkgs: 10 = 5mA to 1.SA, TJ = 2SoC
10 = 2S0mA to 7S0mA, TJ = 2SoC
T - Pkg: 10 = SmA to SOOmA, TJ = 2SoC
VIN = 22V to 33V
Power Pkgs: 10 = SmA to 1.0A, P S; 20W
T - PI(g: 10 = 5mA to SOOmA, P S; 2W
Over Temperature Range
TJ = 2SoC
With Line: VIN = 28V to 38V
With Load: 10 = SmA to 1.0A (Power Pkgs.)
10 = SmA to SOOmA (T)
I!No = 100mV, TJ = 25°C
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = 500mA
Power Pkgs: TJ = 25°C
T - Pkg: TJ = 25°C
Power Pkgs: VIN = 35V, TJ = 25°C
T - Pkg: VIN = 35V, TJ = 25°C
tWIN = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. aITJ = 125°C
10=5mA
SG7818AC
SG7818C
Min. Typ. Max. Min. Typ. Max.
17.7 18.0 18.3 17.3 18.0 18.7
40
20
360
180
20
10
180
90
40
120 360
180
40
180
lS
90
40
180
lS
90
17.S 18.0 18.S
17.5 18.0 18.5
7
4
6
1.0
0.5
O.S
1.5
0.5
59
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4 - 231
2
2.2
0.9
2.5
3.3
1.7
1.2
0.7
17.1
17.1
18.0
18.0
4
1.5
0.5
2
2.2
0.9
59
72
175
72
175
Units
V
mV
mV
mV
mV
mV
18.9
18.9
8.5
8
1.0
0.5
O.S
V
V
mA
mA
mA
mA
mA
2.5
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
SG7800AISG7800 SERIES
20V POSITIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG7820NSG7820 with -55°C S TA S 150°C,
SG7820AC/SG7820C with O°C S TA S 125°C, V,N =29V, 10 =500mA forthe K, R, G and IG -Power Packages-, 10 =1OOmA for the T package, C'N =O.33~F,
and COUT = 0.1 ~F. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperatire.)
SG7820AlSG7820
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ =2S~C
VIN = 27V to 3SV, TJ = 2SoC
V IN = 26V to 32V, TJ = 2SoC
Power Pkgs: 10 = SmA to 1.SA, TJ = 2SoC
10 = 2S0mA to 7S0mA, TJ = 2SoC
T - Pkg: 10 = SmA to SOOmA, TJ = 2SoC
VIN = 24V to 3SV
Power Pkgs: 10 = SmA to 1.0A, P S 20W
T - Pkg: 10 = SmA to SOOmA, P S 2W
Over Temperature Range
TJ = 2SoC
With Line: VIN = 24V to 3SV
With Load: 10 = SmA to 1.0A (Power Pkgs.)
10 = SmA to SOOmA (T)
INo = 100mV, TJ = 2SoC
Power Pkgs: 10 = 1.0A, T- Pkg: 10 = SOOmA
Power Pkgs: TJ = 2SoC
T - Pkg: TJ = 2SoC
Power Pkgs: VIN = 3SV, TJ = 2SoC
T - Pkg: VIN = 3SV, TJ = 2SoC
ININ = 10V, f = 120Hz, TJ = 2SoC
f = 10Hz to 100KHz (Note 2)
1000hrs. aITJ = 12SoC
10= SmA
SG7820A
SG7820
Min. Typ. Max. Min. Typ. Max.
19.7 20.0 20.3 19.2 20.0 20.8
22
22
100
200
12
SO
12
100
4S
4S
140
200
20
20
70
100
20
20
100
70
19.4 20.0
19.4 20.0
4
1.S
O.S
2
2.2
0.9
20.6
20.6
7
6
0.8
O.S
O.S
2.S
3.3
1.7
1.2
0.7
19.0 20.0
19.0 20.0
4
1.S
O.S
2
2.2
0.9
V
V
mA
mA
mA
mA
mA
2.S
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
40
40
96
17S
96
17S
V
mV
mV
mV
mV
mV
21.0
21.0
7
6
0.8
O.S
O.S
S8
S8
Units
SG7820AC/SG7820C
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output CUrrent
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 2SoC
VIN = 27V to 3SV, TJ = 2SoC
VIN = 26V to 32V, TJ = 2SoC
Power Pkgs: 10 = SmA to 1.SA, TJ = 2SoC
10 = 2S0mA to 7S0mA, TJ = 2SoC
T - Pkg: 10 = SmA to SOOmA, TJ = 2SoC
VIN = 24V to 3SV
Power Pkgs: 10 = SmA to 1.0A, P S 20W
T - Pkg: 10 = 5mA to SOOmA, P :s 2W
Over Temperature Range
TJ =2SoC
With Line: VIN = 24V to 3SV
With Load: 10 = SmA to 1.0A (Power Pkgs.)
10 = SmA to SOOmA (T)
IN0 = 100mV, TJ = 2SoC
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = SOOmAPower Pkgs: TJ = 2SoC
T - Pkg: TJ = 2SoC
Power Pkgs: VIN = 3SV, TJ = 2SoC
T - Pkg: VIN = 3SV, TJ = 2SoC
I:..YIN = 10V, f = 120Hz, TJ = 2SoC
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 12SoC
10=SmA
SG7820AC
SG7820C
Min. Typ. Max. Min. Typ. Max.
19.7 20.0 20.3 19.2 20.0 20.8
22
44 400
200
12
24
200
100
4S
lS0 400
200
20
SO
200
100
20
100
SO
200
19.4 20.0
19.4 20.0
4
1.S
O.S
2.S
3.3
1.7
1.2
0.7
58
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4- 232
2
2.2
0.9
20.6
20.6
7
6
1.0
O.S
O.S
19.0 20.0
19.0 20.0
4
1.S
O.S
2
2.2
0.9
96
17S
V
V
mA
mA
mA
r:nA
mA
2.S
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
40
96
17S
V
mV
mV
mV
mV
mV
21.0
21.0
8.S
8
1.0
O.S
O.S
S8
40
Units
24V POSITIVE REGULATOR
SG7800AISG7800 SERIES
ELECTRICAL SPECIFICATIONS (Note 1)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG7B24NSG7B24 with -55°C :5 T. :5 150°C,
SG7B24AC/SG7B24C with O°C :5T. :5125°C, V,N = 32V, 10 = 500mA for the K, R, G and IG -Power Packages-, 10 = 1OOmA for the T package, C'N = O.3311F,
and COUT = O.1I1F. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperatire.)
SG7824A1SG7824
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 25°C
Y'N = 27V to 38V, TJ = 25°C
Y'N = 30V to 36V, TJ = 25°C
Power Pkgs: '0 = SmA to 1.SA, TJ = 2SoC
10 = 250mA to 7S0mA, TJ = 25°C
T - Pkg: 10 = SmA to 500mA, TJ = 25°C
Y'N = 2SV to 38V
Power Pkgs: 10 = 5mA to 1.0A, P :5 20W
T - Pkg: 10 = SmA to 500mA, P :5 2W
Over Temperature Range
TJ = 25°C
With Line: Y'N = 2SV to 38V
With Load: 10 = 5mA to 1.0A (Power PIIgs.)
'0 = 5mA to 500mA (T)
!N0 = 100mV, TJ = 25°C
Power Pkgs: '0 = 1.0A, T - Pkg: '0 = 500mA
Power PIIgs: TJ = 25°C
T - Pkg: TJ = 25°C
Power Pkgs: Y'N = 35V, TJ = 25°C
T - Pkg: Y'N = 35V, TJ = 25°C
tN ,N = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 125°C
10= 5mA
SG7824A
SG7824
Min. Typ. Max. Min. Typ. Max.
23.6 24.0 24.4 23.0 24.0 25.0
25
120
50
240
28
120
14
60
180 240
SO
160
70
25
120
SO
25
25
120
SO
23.3 24.0
23.3 24.0
4
1.5
0.5
2
2.2
0.9
24.7
24.7
7
6
0.8
0.5
0.5
2.5
3.3
1.7
1.2
0.7
22.S
22.8
24.0
24.0
4
1.5
0.5
2
2.2
0.9
V
V
mA
mA
mA
mA
mA
2.5
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
40
40
96
175
96
17S
V
mV
mV
mV
mV
mV
25.2
25.2
7
6
0.8
0.5
O.S
56
56
Units
SG7824AC/SG7824C
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ - 2SoC
Y'N = 27V to 38V, TJ = 25°C
Y'N = 30V to 36V, TJ = 25°C
Power Pkgs: 10 = 5mA to 1.SA, TJ = 25°C
10 = 250mA to 750mA, TJ = 2SoC
T - Pkg: 10 = 5mA to 500mA, TJ = 2SoC
Y'N = 28V to 3SV
Power Pkgs: '0 = 5mA to 1.0A, P :5 20W
T - Pkg: 10 = 5mA to 500mA, P :5 2W
Over Temperature Range
TJ = 25°C
With Line: Y'N = 2SV to 38V
With Load: 10 = 5mA to 1.0A (Power Pkgs.)
'0 = 5mA to 500mA (T)
tNo = 100mV, TJ = 25°C
Power Pkgs: '0 = 1.0A, T - Pkg: '0 = 500mA
Power Pkgs: TJ = 25°C
T - Pkg: TJ = 25°C
Power Pkgs: Y'N = 35V, TJ = 25°C
T - Pkg: Y'N = 35V, TJ = 25°C
!:N'N = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. atTJ = 125°C
'0= 5mA
SG7824AC
SG7824C
Min. Typ. Max. Min. Typ. Max.
23.6 24.0 24.4 23.0 24.0 2S.0
50
480
25
240
28
240
14
120
180 480
50
240
240
25
70
120
25
25
120
240
23.3 24.0
23.3 24.0
4
1.5
0.7
2.5
3.3
1.7
1.2
0.7
56
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4- 233
2
2.2
0.9
24.7
24.7
7
6
1.0
0.5
0.5
22.8
22.S
24.0
24.0
4
1.5
0.7
2
2.2
0.9
96
175
V
V
mA
mA
mA
mA
mA
2.5
3.3
1.7
1.2
0.7
V
A
A
A
A
dB
IlVN
mV
°C
40
96
175
V
mV
mV
mV
mV
mV
2S.2
25.2
8.5
S
1.0
0.5
0.5
56
40
Units
SG7800AISG7800 SERIES
POSITIVE REGULATOR
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
3-TERMINAL TO-3
METAL CAN
K-PACKAGE
Part No.
SG78XXAKl883B
SG78XXAK
SG78XXAeK
SG78XXKl883B
SG78XXK
SG78XXK
Ambient
Temperature Range
Connection Diagram
-55°C to 125°C
-55°C to 125°C
ooe to 70e
-55°C to 125°C
·55°e to 125°C
ooe to 70°C
0
o
®
.7="
0
CASE IS GROUND
VOUT
3-TERMINAL TO-66
METAL CAN
R-PACKAGE
SG78XXAR/883B
SG78XXAR
SG78XXAeR
SG78XXR/883B
SG78XXR
SG78XXeR
-55°C to 125°C
-55°C to 125°C
ooe to 70°C
-55°C to 125°C
-55°C to 125°C
ooe to 70°C
v"
CD
0
0
®
CASE IS GROUND
vo~
3-PIN TO-39 METAL CAN
T-PACKAGE
3-PIN HERMETIC TO-257
G-PACKAGE (Non-Isolated)
3-PIN HERMETIC TO-257
IG-PACKAGE (Isolated)
Note 1.
2.
3.
4.
SG78XXAT/883B
SG78XXAT
SG78XXAeT
SG78XXT/883B
SG78XXT
SG78XXeT
-55°C to 125°C
-55°C to 125°C
ooe to 70°C
-55°C to 125°C
-55°C to 125°C
ooe to 70°C
SG78XXAG/883B
SG78XXAG
SG78XXG/883B
SG78XXG
-55°C
-55°C
-55°C
-55°C
to
to
to
to
125°C
125°C
125°C
125°C
SG78XXAIG/883B
SG78XXAIG
SG78XXIG/883B
SG78XXIG
-55°C
-55°C
-55°C
-55°C
to
to
to
to
125°C
125°C
125°C
125°C
'·8
® ®
vo~
Tab is GND
10I
GROUND
1
:
I
~~OUND
v"
Contact factory for JAN and DESC product availability.
All parts are viewed from the top.
"XX" to be replaced by output voltage of specific fixed regulator.
Some products will be available in leadless chip carrier (LCC) and hermetic flat pack (F). Consult factory for price and availability
Silicon General.
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
4 - 234
'¥*
SG7900AISG7900AC
SG7900lSG7900C
•
SILICON
GENERAL
LINEAR INTEGRATEO CIRCUITS
NEGATIVE FIXED VOLTAGE REGULATOR
DESCRIPTION
FEATURES
The SG7900AlSG7900 series of negative regulators offer self-contained, fixedvoltage capability with up to 1.5A of load current. With a variety of output voltages
and four package options this regulator series is an optimum complement to the
SG7800AlSG7800, SG140/SG340 line of three terminal regulators.
• Output voltage set internally to ±1.5% on
SG7900A
• Output current to 1.5A
• Excellent line and load regulation
• Foldback current limiting
• Thermal overload protection
• Voltages available: -5V, -5.2V, -8V,
-12V, -15V, -18V, -20V
• Contact factory for other voltage options
These units feature a unique band gap reference which allows the SG7900A
series to be specified with an output voltage tolerance of ±1.5%. The SG7900A
versions also offer much improved line regulation characteristics.
All protective features of thermal shutdown, current limiting, and safe-area control
have been designed into these units and since these regulators require only a
single output capacitor (SG7900 series) or a capacitor and 5mA minimum load
(SG120 series) for satisfactory performance, ease of application is assured.
Although designed as fixed-voltage regulators, the output voltage can be increased through the use of a simple voltage divider. The low quiescent drain
current of the device insures good regulation when this method is used, especially
for the SG120 series.
These devices are available in hermetically sealed TO-257 (both isolated and nonisolated), TO-3, TO-39 and TO-66 power packages.
HIGH RELIABILITY FEATURES
- SG7900A/SG7900
•
•
•
•
•
•
•
•
Available to MIL-STD - 883
MIL-M3851 0/11501 BXA - JAN7905T
MIL-M38510/11505BVA - JAN7905K
MIL-M3851 0/11506BVA - JAN7912K
MIL-M3851 0/11507BVA - JAN7915K
Scheduled for MIL-M-38510 QPL listing
Radiation data available
SG level "S" processing available
SCHEMATIC DIAGRAM
GNO
• WIRE EXISTS IF 120 TYPE DEVICE.
WIRE DOES NOT EXIST IF 7900 TYPE DEVICE.
SELECTABLE BY EMInER OPTION.
April 1990
4-235
•
SG7900AISG7900 SERIES
NEGATIVE REGULATOR
ABSOLUTE MAXIMUM RATINGS (Note 1)
Device
Output Voltage
-5V
-5.2V
-8V
-12V
-15V
-18V
-20V
Input Voltage Differential
(Output shorted to ground)
35V
35V
35V
35V
35V
35V
35V
Input Voltage
-35V
-35V
-35V
-35V
-40V
-40V
-40V
Operating Junction Temperature
Hermetic (K, R, T, G, IG - Packages) ........................... 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Values beyond which damage may occur.
THERMAL DERATING CURVES
175
175
AMBIENT TEMPERATURE - "c
CASE TEMPERATURE -
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
'C
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Operating Junction Temperature Range:
SG7900Al7900 .............................................. -55°C to 150°C
SG7900AC/7900C ............................................ O°C to 125°C
Note 2. Range over which the device is functional.
CHARACTERISTIC CURVES
25
E
20
15
15
"<
0.
gj
0
10
~
V,
3.5 C/W HEAT SINK
\
~ATSlNk
o
o
25
50
75
-
SG7905
-
I\,
\
...- Y
/
500
2:
=>
0
>
v
l-
1\
1\
/
r
~57
V
4.99
\
/
VIN =-lDY, NO LOAD
j'
SG7905
I
O.B
I--
O. 7 0
125
AMBlENT TEMPERATURE -
I-"
r-
I"'-..
100
-;>,.
VIN ;::-lOV
1.2
\.
~
~
"<
S
1.3
\
~
"<-
......
05
"
" " """"
"
0
0
:<
10
20
SG7~05
-
0
-
........
S
V-
V
2
,
~5~
,
SG120-05
" ""... t'-..
.......
........
10
20
30
40
0
10
r--....
........
20
.......
~
f'..
0
0
30
40
-V'N - (V)
-V'N - (V)
FIGURE 4.
SHORTCIRCUIT CURRENT VS. V'N
t'-... ......b,.
"""
0
40
K PKG, TO-3
SG7905K
U
if>
_f-"
~
,
"-
30
- (v)
-V'N
,/
2
.s,
........
........
25~C
NO LOAD. 25°C
"-
"""
-55~e
3
3
T PKG, TO-39
SG7905T
25 be
FIGURES.
SHORT CIRCUIT CURRENT VS. V'N
FIGURES.
QUIESCENT CURRENT VS. V'N
•
70
VIN ",-lOV, 25°C
SG7905
6
60
Z
,
>-
oo
>,
0
'"
r-...
~
5
N~ l~AD
lOn LOAD
4
3
,
N
W
if!J
"'50 LOAD
z
0
i=
,
,
0
0
IA
2
~
~
ii'
VI
3
40
u
~rJ
2
50
r"-
30
SOOmA LOAD, 25°C
SG7905
20
10
0
4
5
6
7
B
9
10
10
100
-V'N - (V)
10K
'K
lOOK
FREQUENCY-(Hz)
FIGURE 7.
DROPOUT CHARACTERISTICS
FIGURE B.
RIPPLE REJECTION VS. FREQUENCY
APPLICATIONS
.t J-
C1
f 2 . 2 1lF
INPUT
3
C2
f 1 . 0 1lF
1
NEGATIVE
REGULA TOR
.t
J1
12
.:l
T
lC1
T 2 . 2 1l F
OUTPUT
INPUT
31
1
C3
R,
<
25 1l F
lC2
T 1 . 0 1l F
11
NEGATIVE
REGULATOR
R2
2
OUTPUT
FIGURE 10 - CIRCUIT FOR INCREASING OUTPUT VOLTAGE
FIGURE 9 • FIXED OUTPUT REGULATOR
NOTE: 1. C1 is required only if regulator is separated from rectifier
NOTE: C3 optional for improved transient response and ripple rejec-
filter.
2. Both C1 and C2 should be low E.S.R. types such as solid
tantalum. If aluminum electrolitics are used, at least 1Otimes
values shown should be selected.
3. If large output capacities are used, the regulators must be
protected from momentary input shorts. A high current diode
4-237
R,+R,
VOUT = V (REGULATOR) -R-,-
R = V(REG)
,
15mA
SG7900AISG7900 SERIES
-S.OV NEGATIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG7905A1SG7905 with -55°C" T. " 150°C,
SG7905AC/SG7905Cwith O°C"T." 125°C, V,N = -10V,l e=500mA for the K, R, G and IG -Power Packages-,Ie = 100niA forthe T package, C'N = 211F,
and COUT = 1.0I1F. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
SG7905A1SG7905
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ =25°C
VIN = -7.SV to -2SV, TJ = 2SoC
VIN =-8V to -12V, TJ =2SoC
Power Pkgs: 10 = SmA to I.SA, TJ = 25°C
10 =2S0mA to 7S0mA, TJ =2SoC
T - Pkg: 10 = SmA to 500mA, TJ =2SoC
VIN =-BV to -20V
Power Pkgs: 10 = 5mA to 1.0A, P :5 20W
T - Pkg: 10 =SmA to SOOmA, P :5 2W
Over Temperature Range
TJ =25°C
with Line: VIN = -BV to -25V
with Load: 10 =SmA to 1.0A (Power Packages)
10 = SmA to SOOmA (T)
aVo =100mV, TJ =2SoC
Power Pkgs: 10 =1.0A, T - Pkg: 10 = SOOinA
Power Pkgs: TJ =2SoC
T - Pkg: TJ = 25°C
Power Pkgs: VIN = -3SV, TJ =2SoC
T - Pkg: VIN = -3SV, TJ = 25°C
!NIN =10V, f =120Hz, TJ =2SoC
f =10Hz to 100KHz (Note 2)
1000hrs. atTJ =12SoC
10=5mA
SG7905A
SG7905
Min. Typ_ Max. Min. Typ. Max_
-4.92 -S.OO -S.OB -4.B -S.O -S.2
2S
3
SO
S
12
1
2S
3
15
75
15
100
1S
1S
2S
25
5
100
S
30
-4.BS -5.00 -S.15 -4.70 -S.OO -5.30
-4.BS -S.OO -S.IS -4.70 -S.OO -S.30
2.5
2.5
2.0
2.0
1.3
1.3
O.S
O.S
0.5
O.S
1.1
I.S
0.5
.2.3
3.3
1.4
1.2
0.6
S4
1.1
2.3
3.3
1.4
1.2
0.6
2S
20
175
80
I.S
0.5
S4
2S
20
17S
80
Units
V
mV
mV
mV
mV
mV
V
V
mA
mA
mA
mA
mA
V
A
A
A
A
dB
IlVN
mV
°C
SG7905AC/SG7905C
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 2SoC
VIN = -7.5V to -25V, TJ = 25°C
VIN =-8V to -12V, TJ = 2SoC
Power Pkgs: 10 = SmA to 1.SA, TJ = 2SoC
10 =250mA to 750mA, TJ =2SoC
T - Pkg: 10 = 5mA to 500mA, TJ = 25°C
VIN .; -BV to -20V
Power Pkgs: 10 = 5mA to 1.0A, P :5 20W
T - Pkg: 10 =SmA to 500mA, P :5 2W
Over Temperature Range
TJ =25°C
with Line: VIN = -8V to -25V
with Load: 10 =SmA to 1.0A (Power Packages)
10 = 5mA to 500mA (T)
aVo =100mV, TJ = 2SoC
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = 500mA
Power Pkgs: TJ 25°C
T - Pkg: TJ = 25°C
Power Pkgs: VIN =-35V, TJ =25°C
T - Pkg: VIN =-35V, TJ =25°C
aV IN = 10V, f = 120Hz, TJ =2SoC
f = 10Hz to 100KHz (Note 2)
1000hrs. atTJ " 125°C
lo=SmA
=
SG7905AC
SG7905C
Min. Typ. Max. Min. Typ. Max.
-4.92 -S.OO -S.OB -4.B -S.O -S.2
3
100
S
40
1
SO
3
2S
15
15
75
100
S
SO
S
50
15
100
5
SO
-4.85 -5.00 -5.15 -4.75 -5.00 -5.25
-4.85 -5.00 -S.IS -4.75 -5.00 -5.25
2.5
3.0
2.0
2.0
1.3
1.3
0.5
0.5
0.5
0.5
1.1
1.5
0.5
1.1
2.3
3.3
1.4
1.2
0.6
25
20
175
80
1.5
0.5
S4
54
Note 1. All regulation tests are made at constant junction temperature with low duty cycle testing.
2. This test is guaranteed but is not tested in production.
4-238
2.3
3.3
1.4
1.2
0.6
25
20
175
80
Units
V
mV
mV
mV
mV
mV
V
V
mA
mA
mA
mA
mA
V
A
A
A
A
dB
IlVN
mV
°C
SG7900AISG7900 SERIES
-5.2 V NEGATIVE REGULATOR
ELECTRICAL SPECIFICATIONS (Note 1)
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG790S.2A1790S.2 with -SsoC S T. S IS0°C,
SG790S.2AC!790S.2C with O°CST. S 12SoC, V,N =-10V,1 0=SOOmA for the K, R, G and IG -Power Packages-, 10= 1OOmA for the T package, C,N = 2j!F,
and COUT = 1.0j!F. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
SG79D5.2A1SG79D5.2
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 25°C
Y'N = -7.7V to -2SV, TJ = 25°C
Y'N = -SV to -12V, TJ = 25°C
Power Pkgs: 10 = 5mA to 1.SA, TJ = 2S0C
10 = 250mA to 750mA, TJ = 25°C
T - Pkg: 10 = 5mA to 500mA, TJ = 2SoC
Y'N = -S.2V to -20V
Power Pkgs: 10 = SmA to 1.0A, P s 20W
T - Pkg: 10 = SmA to 500mA, P s 2W
Over Temperature Range
TJ = 25°C
with Line: Y'N = -S.2V to -2SV
with Load: 10 = 5mA to 1.0A (Power Pacl(8ges)
10 = SmA to 500mA (T)
!:"vo = 100mV, TJ = 25°C
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = SOOmA
Power Pkgs: TJ = 2SOC
T - Pkg: TJ = 25°C
Power Pkgs: Y'N = -35V, TJ = 25°C
T - Pkg: Y'N = -3SV, TJ = 2SoC
!:N'N = 10V, f = 120Hz, TJ = 25°C
f = 10Hz to 100KHz (Note 2)
1000hrs. at TJ = 12SoC
10=SmA
SG79D5.2A
SG79D5.2
Min. Typ. Max. Min. Typ. Max.
-5.12 -5.20 -5.2S -5.0 -5.2 -5.4
5
5
25
50
3
25
3
15
15
1S
7S
100
5
30
5
25
5
100
5
30
-5.05 -5.20 -5.3S -4.90 -S.20 -5.S0
-5.05 -5.20 -S.35 -4.90 -S.20 -5.50
2.S
2.S
2.0
2.0
1.3
1.3
0.5
0.5
O.S
0.5
1.1
1.5
O.S
2.3
3.3
1.4
1.2
0.6
1.1
2.3
3.3
1.4
1.2
0.6
25
24
175
SO
1.S
O.S
54
54
25
24
175
SO
Units
V
mV
mV
mV
mV
mV
V
V
mA
mA
mA
mA
mA
V
A
A
A
A
dB
IlVN
mV
°C
SG79D5.2AC/SG79D5.2C
Parameter
Output Voltage
Line Regulation (Note 1)
Load Regulation (Note 1)
Total Output Voltage
Tolerance
Quiescent Current
Quiescent Current Change
Dropout Voltage
Peak Output Current
Short Circuit Current
Ripple Rejection
Output Noise Voltage (rms)
Long Term Stability
Thermal Shutdown
Test Conditions
TJ = 25°C
Y'N = -7.7V to -25V, TJ = 25°C
V,N =-SVto-12V, TJ =2SoC
Power Pkgs: 10 = 5mA to 1.5A, TJ = 25°C
10 = 250mA to 750mA, TJ = 25°C
T - Pkg: 10 = SmA to SOOmA, TJ = 2SoC
Y'N = -S.2V to -20V
Power Pkgs: 10 = SmA to 1.0A, P s 20W
T - Pkg: 10 = 5mA to 500mA, P s 2W
Over Temperature Range
TJ = 25°C
with Line: Y'N = -S.2V to -20V
with Load: 10 = SmA to 1.0A (Power Packages)
10 = 5mA to 500mA (T)
AVo = 100mV, TJ = 25°C
Power Pkgs: 10 = 1.0A, T - Pkg: 10 = 500mA
Power PI 85%
• Electrically isolated, 4-pin, TO-66 hermetic case
HIGH RELIABILITY FEATURES
t
Available with high reliability processing
FUNCTIONAL DIAGRAM
SM600/SM601/SM602
POSITIVE
OUTPUT
DRIVE
COMMON
SM610/SM611/SM612
NEGATIVE
OUTPUT
DRIVE
April 1990
4-247
COMMON
•
SAl600lSAl6011SAl6021SAl610lSAl6111SAl612
ABSOLUTE MAXIMUM RATINGS (Note 1)
SM600
Input Voltage, V._ 2 ________________________________________
60V
Output Voltage, V'_2 ------------------'--- ___ : ____________ 60V
Drive Input Reverse Voltage, V3_. _______________
SV
Output Current; I, _________________________________________
SA
Drive Current, 13 ___ : ____________________.___________________ -0_2A
SM601
SOV
SOV
SV
SA
-0_2A
Thermal Resistance
Power Switch, OJ _C __________________________________________________ -' 4_0°CIW
Commutating Diode ______________ , ___________________________________ 4_0°CIW
Case to Ambient, 0C_A ____________________________________________ 60_0°CIW
Operating Junction Temperature
Hermetic (R Package) __________________________________________________ lS0°C
Storage Temperature Range _____________________________ -6SoC to 1S0°C
Lead Temperature (Soldering, 10 Seconds) _______ ~ ____________ 300°C
SM610
-60V
-60V
-SV
-SA
0_2A
SM602
100V
100V
SV
SA
-0_2A
SM611
-SOV
-BOV
-SV
-SA
0_2A
SM612
-100V-100V
-SV
-SA
0_2A
Note 1_ Exceeding these ratings could cause damage to the device_
THERMAL DERATING CURVES
.
5.0
50
4.0
40
~
I
3.0
~
;
c
2.0
i
""'
~
I
~
0
25
~
.~
1.0
0
is
50
~ '-
"
100
""-
AI.lB!ENT TEMPERATURE -
125
150
"
~.~~~
20
i
~
75
30~
:'<81-
'-
10
0
175
'C
0
25
50
75
'00
""125
150
"75
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
SM600
SM601
SM602
SM610
Input Voltage, V._ 2 _________________________________________ SOV
70V
90V
-SOV
-SOV
70V
90V
Output Voltage, V, -2 -------------------------------------- SOV
Drive Input Reverse Voltage, V3_. _________________ 3V
-3V
3V
3V
Output Current, I, ___________________________________________ 4A
-4A
4A
4A
Drive Current, 13 ______________________________________________
-O_lA
-O_lA
-O_lA
O_lA
Operating Ambient Temperature Range
____________________________________________________ O°C to 70°C
SM6XXR
SM6XXHRR ____________________________________________ -SsoC to 12SoC
SM611
-70V
-70V
-3V
-4A
O_lA
SM612
-90V
-90V
-3V
-4A
O_lA
Note 2_ Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of TA = 25°C __ Low duty cycle pulse testing techniques
are used which maintains junction and case temperatures equal to the ambient temperature_)
Parameter
On-State Vol~e (Note 3)
Diode ForWard Voltage (Note 3)
Off-state Cjlrrent
Diode Reverse Current
Test Conditions
I. = 2A(-2A), 13 = -20mA (20mA)
I. = SA(-SA), 13 = -20mA (20mA)
I. = 2A{-2A)
I. = SA{-SA)
V4 =Rated input voltage
v. = Rated input voltage, TA =125°C
V, =Rated output voltage
V, = Rated output voltage, TA = 125°C
Note 3_ Pulse test: Duration = 300115, Duty Cycle,;; 2%_
4 -24S
SG600/601/602
5G61 0/611/612
Min. Typ. Max. Min. Typ. Max.
1.0
-1.0 -1.S
1.S
2.S
-2.S -3.S
3.S
O.S
-O.S -1.0
1.0
1_5
-1.0 -1.5
1.0
0.1
10
-0.1
-10
10
-10
1.0
-1.0 -10
10
soo
-500
Units
V
V
V
V
IJA
IJA
IJA
I1A
SAl600ISA1601ISAl602ISAl610ISA1611ISA1612
ELECTRICAL SPECIFICATIONS (continued)
Parameter
I SG600/601/602 I SG610/611/612
I Min. I Typ. I Max. I Min. I Typ. I Max.
Test Conditions
Dynamic Characteristics (See FiQures 1 & 2) (Notes 4 & 5)
Current Delay Time
Current Rise Time
Voltage Rise Time
Voltage Storage Time
Voltage Fall Time
Current Fall Time
Efficiency (Note 5)
20
50
30
450
50
70
85
40
75
50
75
150
20
50
30
450
50
70
85
Units
40
75
50
ns
ns
ns
ns
75
150
ns
ns
%
AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS (Note 6)
~--.----o
VOUT=+5V
RL =2.50
IDRIVE=-20mA
PULSE WIDTH=10,uS
REP. RATE=20KHz
3
1.2KO
+25V
1 IIII I
U
rv OV
U
U
FIGURE 1 - SM600/601/602 SWITCHING SPEED CIRCUIT
./
\
\
,
V4-1
/
\
/
/~
'\
\
\
\
I
I
,/
POWER SWITCH
\
2
7--COMMUTATING DIODE
FIGURE 2 - SM600/601/602 SWITCHING WAVEFORMS
Note 4. In switching an inductive load, the current will lead the voltage on turn-on and lag the voltage on turn-off (see Figure2). Therefore, Voltage Delay
Time (tDV ) " to. + to and Current Storage Time (t,,) " t" + tN _
Note 5. The efficiency is a measure of internal power losses and is equal to Output Power divided by Input Power. The switching speed circuit of Figure
1, in which the efficiency measured, is represenative of typical operating conditions for the SM600 series switching regulators_
Note 6. SM61 0/611/612 Test Circuit and waveforms are identical but of opposite polarity (V'N =-25V, VOUT = -5V, IDR'VE =+20mA).
APPLICATION CIRCUITS
SM60X
SM60X
Va
FIGURE 3 - STEP DOWN (BUCK) CONVERTER
FIGURE 4 - NEGATIVE OUTPUT DOWN/UP (BUCK-BOOST) CONVERTER
4-249
SAl600lSAl6011SAl6021SAl610lSAl6111SAl612
APPLICATION CIRCUITS (continued)
--
SM61X
VIN
I-
+
I
~
r
>
Va
I
n77
PWM
DRIVE
/~
PWM
FEEDBACK
FIGURE 5 - STEP UP (BOOST) CONVERTER
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Note Below)
Package
4-PIN TO-66 METAL CAN
R- PACKAGE
Part No.
Ambient
Temperature Range
SM600R
SM600HRR
SM601R
SM601HRR
SM602R
SM602HRR
O°C to 70°C
-55°C to 125°C
O°C to 70°C
-55°C to 125°C
O°C to 70°C
-55°C to 125°C
SM61 OR
SM610HRR
SM611R
SM611HRR
SM612R
SM612HRR
O°C to 70°C
-55°C to 125°C
O°C to 70°C
-55°C to 125°C
O°C to 70°C
-55°C to 125°C
Connection Diagram
~""'"~'"~
0
COMMON
1
4
23
0
DRIVE
"ffi""'oo~~.'m
O~: 0
COMMON
DRIVE
Note 1. All packages are viewed from the top.
2. Case is electrically isolated.
3. Consult factory for additional screening available.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-6121. TWX: 910-596-1804. FAX: (714) 893-2570
4-250
ee"."",
j4
SA/62SISA1626ISA1627ISA163SISA1636ISAf637
SILICON
GENERAL
SWITCHING REGULATOR
POWER OUTPUT STAGES
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SM625/626/627 and SM635/636/637 series of Power Output
Stages are especially designed to be driven with standard PWM
integrated circuits to form an efficient switching power supply.
The SM625, SM626 and SM627 are optimized for non-isolated
Buck and Buck-Boost application, where SM635, SM636 and
SM637 are best suited for DC-DC Boost type applications as well
as negative output Buck Converters. The hybrid circuit construction utilizes thick film resistors on a beryllia substrate for maximum
thermal conductivity and resultant low thermal impedance. All of
the active elements in the hybrid are fully passivated.
• Equivalent to the Unitrode PIC 625, 626, 627, 635, 636,
637
• 15A current capability
• Designed and characterized for switching regulator
applications such as Buck, Boost, and Buck-Boost
type
• Cost saving design reduces size, improves efficiency,
reduces noise and RFI
• High operating frequency (to> 100KHz) results in
smaller inductor-capacitor filter and improved power
supply response time
• High operating efficiency at 7 A typical performance Rise and fall time", 300ns
Efficiency> 85%
• Electrically isolated, 4-pin, TO-66 hermetic case
HIGH RELIABILITY FEATURES
~
Available with high reliability processing
FUNCTIONAL DIAGRAM
SM625/SM626/SM627
POSITIVE
OUTPUT
2
COMMON
SM635/SM636/SM637
NEGATIVE
INPUT
NEGATIVE
OUTPUT
4)-_-,
DRIVE
April 1990
4 - 251
COMMON
SM6251SM6261SM6271SM6351SM6361SM637
ABSOLUTE MAXIMUM RATINGS (Note 1)
SM625
Input Voltage, V4_2 •••••••••••••••••••••••••••••••••••••••.• 60V
Output Voltage, V,. 2 ••••••••••••••••••••••.••••••••••••••• 60V
Drive Input Reverse Voltage, V3. 4 ................. 5V
Output Current, I, ........................ :................. 15A
Drive Current, 13 ............................................. -O.4A
Thermal Resistance
Power Switch, 6J • c ................................................... 4.0°C/W
Commutating Diode .................................................. 4.0°C/W
Case to Ambient, 6c . A •••••••••••••••••••••••••••••••••••••••••••• 60.0°C/W
Note 1. Exceeding these ratings could cause damage to the device.
SM627
100V
100V
5V
15A
-O.4A
SM626
80V
80V
5V
15A
-O.4A
SM636
-80V
-80V
-5V
-lSA
O.4A
SM635
-60V
-60V
-5V
-15A
O.4A
SM637
-100V
-100V
-5V
-lSA
O.4A
Operating Junction Temperature
Hermetic (R Package) .................................................. lS0°C
Storage Temperature Range ............................. -6SoC to lS0°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
THERMAL DERATING CURVES
5.0
50
4.0
~
~
,
3.0
~
~
~
is
40
"-
2.0
~
~
~
,
"
0
~
6
C'..,~
25
50
75
100
""-
AMBIENT TEMPERA lURE -
125
150
"
~
20
~
.(
1'0...
0
~
~
~~~~
1.0
JO
~
\0
'"
~
c. . 1J
.
10
0
175
-c
0
25
50
75
1'0...
100
"~
125
CASE TEMPERA lURE -
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
150
175
'C
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
SM627
SM625
SM626
SM635
-SOV
Input Voltage, V4_2 ••.•••••••••••••••••••••••••••••••••••••• SOV
70V
90V
Output Voltage, V, -2 •••••••••••••••••••••••••••••••••••••• 50V
70V
90V
-50V
-4V
Drive Input Reverse Voltage, V3_4 ................. 4V
4V
4V
-13A
Output Current, I, .......................................... 13A
13A
13A
-0.3A
Drive Current, 13 ............................................. -0.3A
-0.3A
0.3A
Operating Ambient Temperature Range
SM6XXR .................................................... O°C to 70°C
SM6XXHRR ............................................ -5SoC to 12SoC
Note 2. Range over which the device is functional.
SM636
-70V
-70V
-4V
-13A
0.3A
SM637
-90V
-90V
-4V
-13A
0.3A
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature ofT. = 25'C. Low duty cycle pulse testing techniques
are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
On-State Voltage (Note 3)
Diode ForwardVoltage (Note 3)
Off-State Current
Diode Reverse Current
Test Conditions
14 = 7A(-7A),1 3 =-30mA (30mA)
14 =15A(-15A), 13 = -30mA (30mA)
I. =7A(-7A)
I. = lSA(-15A)
V. = Rated input voltage
V 4 = Rated input voltage, TA = 125°C
V, = Rated output voltage
V, = Rated output voltage, TA = 125°C
Note 3. Pulse test: Duration = 300l1s, Duty Cycle,; 2%.
4- 252
SG625/626/627
SG635/636/637
Min. Typ. Max. Min. Typ. Max.
-1.0 -1.5
1.0
1.5
2.S
3.5
-2.5 -3.S
0.85 1.25
-0.85 -1.25
0.95 1.75
-0.95 -1.75
0.1
-0.1
10
-10
10
-10
-1.0 -10
1.0
10
500
-500
Units
V
V
V
V
jJJ\
I1A
jJJ\
jJJ\
SM62SISM6261SM6271SM63SISM6361SM637
ELECTRICAL SPECIFICATIONS (continued)
Parameter
I SG625/626/627 I SG635/636/637 I Units
I Min. Typ. I Max. I Min. Typ. Max. I
Test Conditions
Dynamic Characteristics (See Figures 1 & 2) (Notes 4 & 5)
Current Delay Time
Current Rise Time
Voltage Rise Time
Voltage Storage Time
Voltage Fall Time
Current Fall Time
Efficiency (Nole 5)
35
65
40
700
70
175
85
60
150
60
175
300
35
65
40
700
100
175
85
60
175
60
300
300
ns
ns
ns
ns
ns
ns
0/0
AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS (Nole 6)
IDRIVE=-30mA
PULSE WIDTH=10/LS
REP. RATE=20KHz
3
6800
+ 25V i
ev OV
I I I I rU
U
U
FIGURE 1 - SM625/626/627 SWITCHING SPEED CIRCUIT
,
/
POWER SWITCH
,
/
/
/-7--
!
12
,,
~,
- COMMUTATING mODE
/
FIGURE 2 - SM625/6261627 SWITCHING WAVEFORMS
Nole 4. In swilching an induclive load, Ihe currenl will lead Ihe vollage on lurn-on and lag the vollage on lurn-off (see Figure 2). Therefore, Vollage Delay
Time (IDV) " I" + t, and Current Storage Time (I,,) "t" + t", .
Nole 5. The efficiency is a measure of inlernal power losses and is equal 10 OUlpul Power divided by Input Power. The swilching speed circuit of Figure
1, in which Ihe efficiency measured, is represenalive of typical operaling conditions for Ihe SM600 series swilching regulalors.
Note 6. SM635/636/637 Test Circuit and waveforms are identical but of opposite polarily (V'N =-25V, VOIJf =-5V, IDR'VE = +30mA).
APPLICATION CIRCUITS
SM62X
SM62X
Vo
FIGURE 4 - NEGATIVE OUTPUT DOWN/UP (BUCK-BOOST) CONVERTER
FIGURE 3 - STEP DOWN (BUCK) CONVERTER
4·253
SM62SISM6261SM6271SM63SISM6361SM637
APPLICATION CIRCUITS (continued)
SM63X
1
PWM .------,
DRIVE
PWM
rr'n
FEEDBACK
FIGURE 5 - STEP UP (BOOST) CONVERTER
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Note Below)
Package
4-PIN TO-66 METAL CAN
R- PACKAGE
Part No.
Ambient
Temperature Range
SM625R
SM625HRR
SM626R
SM626HRR
SM627R
SM627HRR
DOG to 7DoG
-55°G to 125°G
DOG to 7DOG
-55°G to 125°G
DOG to 70 0 G
-55°G to 125°G
SM635R
SM635HRR
SM636R
SM636HRR
SM637R
SM637HRR
DOG to 7DoG
-55°G to 125°G
DOG to 7D'G
-55'G to 125'G
D'G to 7D'G
-55'G to 125'G
Connection Diagram
~"~oo~m'~
o
1
4
2
3
COMMON
0
DRIVE
"~'~~~'"""'"'
o
COMMON
1
4
2
3
0
DRIVE
Note 1. All packages are viewed from the top.
2. Case is electrically isolated.
3. Contact factory for additional screening available.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4-254
Ie
,
SILI[ON
GENERAL
SM6451SM6461SM6471SM6551SM6561SM65T
I
SWITCHING REGULATOR
POWER OUTPUT STAGES
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SM645/646/647 and SM655/656/657 series Df Power Output
Stages are especially designed to be driven with standard PWM
integrated circuits to form an efficient switching power supply.
The SM645, SM646 and SM647 are optimized for non-isolated
Buck and Buck-Boost application, where SM655, SM656 and
SM657 are best suited for DC-DC Boost type applications as well
as negative output Buck Converters. The hybrid circuit construction utilizes thick film resistors on a beryllia substrate for maximum
thermal conductivity and resultant low thermal impedance. All of
the active elements in the hybrid are fully passivated.
o
Equivalent to the Unitrode PIC 645, 646, 647, 655, 656,
657
o 15A current capability
o Cost saving design reduces size, Improves efficiency,
reduces noise and RFI
o High operating frequency (to> 100KHz) results in
smaller Inductor-capacitor filter and Improved power
supply response time
o High operating efficiency at 7A typical performanceRise and fall time < 300ns
Efficiency> 85%
HIGH RELIABILITY FEATURES
~
Available with high reliability processing
FUNCTIONAL DIAGRAM
SM645/SM646/SM647
POS!1lVE
OUTPUT
DRIVE
COMMON
SM655/SM656/SM657
NEGATIVE
OUTPUT
NEGATIVE 4}-- 100KHz) results In
smaller inductor-capacitor filter and improved power
supply response time
• High operating efficiency at 7A typical performanceRise and fall time < 300ns
Efficiency> 85%
• Electrically Isolated, 4-pin, TO-66 hermetic case
HIGH RELIABILITY FEATURES
~
FUNCTIONAL DIAGRAM
Available with high reliability processing
SM660/SM661/SM662
POSITIVE
OUTPUT
DRIVE
COMMON
SM670/SM671/SM672
NEGATIVE
INPUT
NEGATIVE
OUTPUT
DRIVE
Apri11990
4-259
COMMON
•
SAl660lSAl661 ISAl6621SAl670lSAl671 ISAl672
ABSOLUTE MAXIMUM RATINGS (Note t)
SM66D
Input Voltage, V,C2 ...................................,..... 60V
Output Voltage, V'.2 ...................................... 60V
Drive Input Reverse Voltage, V3 ., ••••••••••••••••• SV
Output Current, I, ......................... c•••••••••••••••• lOA
Drive Current, 13 , •••••••••••••••••••••••••••••••••••••••••••• -0.4A
SM661
SOV
SOV
SV
lOA
-0.4A
Thermal Resistance
Power Switch, OJ.c ................................................... 4.0°CIW
Com mutating Diode ......................................,........... 4.0°CIW
Case to Ambient, 0C.A ................:........................... 60,0°CIW
Note 1. Exceeding these ratings could cause damage to the device.
SM662
100V
100V
SV
lOA
-O.4A
SM671
-SOV
-SOV
-SV
-lOA
O.4A
SM67D
-60V
-60V
-SV
-lOA
O.4A
SM672
-100V
-100V
-SV
-lOA
0.4A
Operating Junction Temperature
Hermetic (R Package) .................................................. lS0°C
Storage Temperature Range ............................. -6SoC to lS0°C
Lead Temperature (Soldering, 10 Seconds) ........ :...., ...... 300°C
THERMAL DERATING CURVES
5.0
50
..
4.0
~.
~
~
I
3.0
~
~
"'
ii
i
15 2.0
i
I
0
25
50
\
75
30
ii
~
~~'"l-",
1.0
0
40
~
15
i
~
"100
""-
AMSIENT TEMPERATURE -
20
125
150
""
I~.~~~
:'<~
"-
10
0
175,
-c
0
25
50
75
100
'"
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
"
125
CASE TEMPERATURE - "c
150
175
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
SM662
SM660
SM661
SM660
-SOV
70V
90V
Input Voltage, V'.2 ......................................... SOV
70V
90V
-SOV
Output Voltage, V'.2 ...................................... SOV
Drive Input Reverse Voltage, V3 . , ................. 4V
4V
4V
-4V
-9A
Output Current, I, ..........................................
9A
9A
9A
Drive Current, 13 ............................................. -0.3A
-0.3A
-0.3A
0.3A
Operating Ambient Temperature Range
SM6XXR .................................................... O°C to 70°C
SM6XXHRK ............................................ -SsoC to 12SoC
Note 2. Range over which the device is functional.
SM661
-70V
-70V
-4V
-9A
0.3A
SM662
-90V
-90V
-4V
-9A
0.3A
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of TA = 25°C. Low duty cycle pulse testing techniques
are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Test Conditions
On-State yoltage (Note 3)
1.= SAl-SA), I. = -30mA(30mA)
I, = 10A(-10A), 13 = -30mA(30mA)
Diode Forward Voltage (Note 3) I. = SAl-SA)
I, = 1OA(-lOA)
Off-State Current
V. = Rated input voltage
V,= Rated input voltage, TA = 12SoC
Diode Reverse Current
V, = Rated output voltage
'
V, = Rated output voltage, TA = 12SOC
Note 3. Pulse test: Duration = 300115, Duty Cycle:!: 2%.
4-260
SG660/661 1662
SG670/671 1672
Min. Typ. Max. Min. Typ. Max.
1.0
1.S
-10 -1.5
2.S
3.S
-2.S -3.S
O.SS 1.25
-O.SS -1.25
0.9S 1.7S
-0.9S -1.7S
0.1
10
-0.1
-10
10
-10
1.0
10
-1.0 -10
SOO
-SOO
Units
V
V
V
V
/lA
/lA
/lA
itA
SAl660lSAl6611SAl6621SAl670lSAl6711SAl672
ELECTRICAL SPECIFICATIONS (continued)
Parameter
SG660/661 1662
SG670/671/672
Min. Typ. Max. I Min. I Typ. Max.
Test Conditions
Dynamic Characteristics (See Figures 1 & 2) (Notes 4 & 5)
Current Delay Time
Current Rise Time
Voltage Rise Time
Voltage Storage Time
Voltage Fall Time
Current Fall Time
Efficiency (Note 5)
35
65
40
700
70
175
85
60
150
60
175
300
35
65
40
700
100
175
85
60
175
60
300
300
I
I
Units
ns
ns
ns
ns
ns
ns
%
AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS (Note 6)
~--..--o Vour=+5V
~=1.00
'ORIVE=-30mA
PULSE WIOTH=10!'-S
REP. RATE=20KHz
3
6800
r---l r---l I
U
U
U
+25V I
'V OV
FIGURE 1 • SM66OJ661/662 SWITCHING SPEED CIRCUIT
\
\ V4-1
\
,
../
\
,
/
/
POWER SWITCH
/
/~7-
"-\
\
\
/
/
2
COMMUTATING DIODE
FIGURE 2· SM660/661/662 SWITCHING WAVEFORMS
Note 4. In switching an inductive load, the current will lead the voltage on turn-on and lag the voltage on turn-off (see Figure 2). Therefore, Voltage Delay
Time (tDV) :; td, + t. and Current Storage Time (t,,) :; t" + t, .
Note 5. The efficiency is a measure of internal power losses and is equal to Output Power divided by Input Power. The switching speed circuit of Figure
1, in which the efficiency measured, is represenative of typical operating conditions for the SM600 series switching regulators.
Note 6. SM670/671/672 Test Circuit and waveforms are identical but of opposite polarity (V'N = -25V, VOOT = -5V, 'DR'VE = +30mA).
APPLICATION CIRCUITS
SM66X
SM66X
FIGURE 3 • STEP DOWN (BUCK) CONVERTER
FIGURE 4 • NEGATIVE OUTPUT DOWN/UP (BUCK·BooST) CONVERTER
4 - 261
•
SAl660lSAl6611SAl6621SAl670lSAl6711SAl672
APPLICATION CIRCUITS (continued)
SM67X
1
PWM .-------,
DRIVE
PWM
fin
FEEDBACK
FIGURE 5 - STEP UP (BOOSn CONVERTER
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Note Below)
Package
4-PIN TO-66 METAL CAN
R-PACKAGE
Part No.
Ambient
Temperature Range
SM66DR
SM66DHRR
SM661R
SM661HRR
SM662R
SM662HRR
Doe to 7Doe
-55°e to 125°e
Doe to 7Doe
-55°e to 125°e
Doe to 7Doe
-55°e to 125°e
SM67DR
SM67DHRR
SM671R
SM671HRR
SM672R
SM672HRR
Doe to 7Doe
-55°e to 125°e
Doe to 7Doe
-55°C to 125°C
DOC to 7Doe
-55°C to 125°C
Connection Diagram
~~".~
o : :
COMMON
0
DRIVE
"~_~'~,"'m
o
COMMON
1
4
2
3
0
DRIVE
Note 1. All packages are viewed from the top.
2. Case is electrically isolated.
3. Consult factory for additional screening available.
Silicon General •
11861 Western Avenue. Garden Grove. CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
4-262
rHUMB INDEX
Ij
SILICON
GENERAL
III
TABLE Of CO~TENTS
I
III
PART NUMBER ~NFORMATION
I
III
GlENlIERAl ~lNIfORMAT~ON
I
III
/POWtER Sl)J[PlPlV
C~RCijJJ~l'S
I
M01~OINl
CONTROL C~!RCll.nTS
I
III
/POWER
[)R~VIER
I
III
OIPIERAl'~ON AMIPUf~ERS
III
CORlE MEMORV C~RCijJJ~'fS
I
III
AijJJl'OMOT~VIE C~RCijJJ~TS
I
111
OTHER CIRCIUl~TS
I
III
PACKAGE ~INIFORMAT!ON
I
III
APPlICAT~ON ~NfORMATION
I
III
SALES OFfICES
I
I
AND
5 -1
~NrERfAC[E C~[RCllUTS
AND COMPARATORS
I
•
SELECTION GUIDE
MOTION CONTROL CIRCUITS
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
Device Type
»>
Description
Typ.Application ~
00163513635
SG1635A13635A
SG1650/3650
Half-bridge driver • DC motor drivers
• Stepper motor
drive
003645
Quad power
driver
SG3663
'o(CONTl
Key Features
VC(IIAX) VCC(IIAX)
Pkgs.
R,P
SA
2A
3SV
40V
3SV
40V
•
•
•
•
Single totem-pole output
Internal clamp diodes
BUilt-in thermal protection
TIL input compatibility
• DC motor drivers
• Stepper motor
drive
• Lamp driver
• Relay driver
3.SA
2,SA
60V
40V
•
•
•
•
•
Four open collector outputs
Internal clamp diodes
Thermal shutdown protection
TIL input compatibility
Common enable pin
Dual solenoid
motor driver
• DC motor drivers
• Stepper motor
drive
• Solenoid motor
drive
3.SA
3,OA
SOV
SOV
• Dual uncommited totem pole outputs
• Internal clamp diodes
• Thermal shutdown protection
• Current sense comparator with
variable threshold and hysteresis
• Chop or non-chop load current
control
SG3700
Dual hammer
driver
• DC motor drivers
coil
• Hammer
drive in high
speed printers
1.SA
O,9A
S.2SV
40V
•
•
•
•
Dual open collector outputs
Internal clamp diodes
Thermal shutdown protection
Internal op-amp to regulate output
current
• Adjustable output current control
• Thermal shutdown indicator
• Logic control of input data
N
SG1731/2731/3731
DC motor pulsewidth modulator
• DC motor control 400mA 200mA
• Electronic microstepping of stepper motors
±2SV
(SOV)
±18V
(36V)
• Dual uncommited totem pole outputs
• Maximum frequency to 3S0KHz
• Adjustable deadband operation
• High slew rate op-amp
• Digital SHUTDOWN input
J, N
SG3718
Sepper motor
driver
• Stepper motors
1,SA
1,2A
S.SV
4SV
SG117312173/3173
SOO172
SG3272
Power op-amp
• Linear DC motor
SA'
3A
1,SA
3.SA
2A
lA
SOV
18V
18V
SG200012800 Series
Darlington arrays • Logic to power
interface
• Lamp driver
• Motor driver
O.6A
O.SA
SOV
Quad power
• Relays
Darlington arrays • Solenoids
• DC and stepper
motor driver
• Display driver
1.7SA
SG2064 thru 2077
.,
1.SA
W,
DWW
S,ST
W,
• Full-step, Half-step, Micro-set
capability
DWW,
• Wide range of motor supply voltge
Q
• Built-in fast commutating diodes
• Output stage shoot-through protection
• Thermal shutdown protection
• Low saturation output stage
• Designed for unstabilized motor
supply
SEE OP-AMP SECTION
&
SEE POWER DRIVER
9SV
& INTERFACE SECTION
SOV
&
80V
November 1988
5-2
SEE POWER DRIVER SECTION
SILICON
GENERAL
SG1635AISG3635A
SG16351SG3635
SG1650lSG3650
LINEAR INTEGRATED CIRCUITS
2A, HALF -BRIDGE DRIVER
DESCRIPTION
FEATURES
The SG1635 and SG1650 are monolithic integrated circuits
designed to interface low-level logic signals with high-current,
inductive, or capacitive loads. These devices are particularly adept
at high-speed pulse width modulation for motor drives or Class D
audio amplifiers, and when used in pairs, they can provide full bridge
drive for bi-directional control.
o
o
o
o
o
o
o
With TTL-compatible units, these devices will either source or sink
up to SA of peak current with interlock protection to insure that
source and sink cannot be on simultaneously. Additional protection
is provided by thermal shutdown of the source output if the chip
temperature rises above 160°C. High speed internal commutating
diodes are also included.
Source or sink 5A peak
Half-bridge with Internal diodes
TTL input compatibility
Either dual- or tri-state output
Direct PWM motor drive from microprocessor
Built-in thermal protection
SG3635P replaces UDN2935Z
SG3650P replaces UDN2950Z and SN75605
HIGH RELIABILITY FEATURES
- SG1635A1SG1635/SG1650
• Available to MIL-STD-SS3
o SG level "5" processing available
BLOCK DIAGRAM - SG1635/1635A13635/3635A
Vs
TRUTH TABLE
ENABLE
INPUT
OUTPUT
Enable
0
0
1
1
Pulse
0
1
0
1
Output
High
High
Low
011- HighZ
1 = Open or High
PULSE
INPUT
GND
BLOCK DIAGRAM - SG1650/3650
Vs
TRUTH TABLE
ENABLE
INPUT
OUTPUT
PULSE
INPUT'
Enable
0
0
1
1
Pulse
0
1
0
1
Output
Low
OIl-HighZ
Low
High
1 = Open or High
NOR,;O------£
~------~~
GND
SUBSTRATE
& CASE
See Application Notes for additional information.
Apri11990
5-3
•
S61635AIS63635A, S616351S63635, S61650lS63650
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Vs)
SG1635/SG3635, SG1650/SG3650 .............................. 40V
SG1635A1SG3635A ........................................................ 45V
Input Voltage
Enable and Pulse .............................................................. 7V
Note 1. Values beyond which damage may occur.
Source/Sink Output Current
Contiuous ............................................................................ 3A
Peak .................................................................................... 5A
Operating Junction Temperature
Hermetic (R - Package) ................................................ 150'C
Plastic (P - Package) ...................................... :............. 150'C
Storage Temperature Range .......................... -65'C to 150'C
Lead Temperature (Soldering, 10 Seconds) .................... 300'C
THERMAL DERATING CURVES
5.0
50
'.0
40
~
~
,
30
1;
'" "~~
~,
.~
r--"
1.0
I
1.0
0
~
~ ~~"" ".-,:'<
~Ib..~
~~O)
~1<
0
25
50
75
~~ ~::t.
s'..o~
S'J),
" 0,0,,,,..1
_'l'l'-f(
20
"~
~
"-
'~ ~
100
r.t,
~
~
125
150
~
10
0
175
q;
0
25
50
75
"'"
100
125
150
175
AUB1ENT TEMPERATURE - "c
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage (Vs)
SG1635/SG3635, SG1650/SG3650 ...................... 8Vto 35V
SG1635A1SG3635A ................................................ 8V to 40V
Note 2. Range over which the device is functional.
Source/Sink Output Current
Continuous .......................................................................... 2A
Peak .................................................................................... 3A
Operating Ambient Temperature Range
SG1635/SG1635A, SG1650 .......................... -55'C to 125'C
SG3635/SG3635A, SG3650 .............................. O'C to 70'C
ELECTRICAL SPECIFICATIONS
SG1635/SG1635A and SG3635/SG3635A
(Unless otherwise specified, these specfiications apply overthe operating ambient temperatures for SG1635/SG 1635A with -55'C s T. S 125'C, SG36351
SG3635A with O'C S T. s 70'C, and +Vs = 24V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal
to the ambient temperature.)
SG1635/1635A
SG3635/3635A
Units
Parameter
Test Conditions
I Min. Typ. Max. I
Static Characteristics
Logic 1 Input Voltage
2.0
V
Logic 0 In'put Voltage
0.8
V
200
Input High- C",rrent
. VPin.se ,,; VENABLE .. 4.5V
!1A
-3.2
Input Low Current
mA
VpULSE " VENABLE" OV
..
..
OiJtpiJt 1.iiaI---.---r---(i
.,
.F
FIGURE 3
-15V
>---4--____-0
~~~a~
>--___-@
FIGURE 4
In this simple battery-powered position servo, the control supply
and driver supply are both single-ended positive with respect to
ground.
-10v
A high torque position servo is obtained by buffering the output
drivers to obtain higher output current.
5 -12
SG17311SG27311SG3731
APPLICATION CIRCUITS
+15V
>--.,.--.--{1
+10V
>----r--~_@
-IOV
>--+-+--(9)
01
"'
-15V
>--+--+_-{
lOW Z
AUDIO
INPUT
>-vv.--,--+-\.'
FIGURES
FIGURES
Bi-directional speed control results when the feedback voltage
transducer is a tachometer.
The two-quadrant transfer function of the SG1731 is ideal for
pulse width modulated audio power amplifiers.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Note Below)
Package
IS-PIN CERAMIC DIP
J-PACKAGE
IS-PIN PLASTIC DIP
N- PACKAGE
Part No.
Ambient
Temperature Range
SG1731J/883B
SG1731J
SG2731J
SG3731J
-55°C to
-55°G to
-25°G to
DOG to
SG2731N
SG3731N
-25°G to 85°G
DOG to 65°G
125°G
125°G
85°G
65°G
,
Connection Diagram
+VT
[~P
2V,.
N. I. INPUT
INV. INPUT
ERROR
[2
[3
[4
[5
15
14
13
12
cT
[6
11
2V,· [7
10
P
P
P
P
P
P
+vs
SHUTDOWN
+Vo
OUTPUT A
OUTPUT 8
-Vo
SUBSTRATE
·v, [,""----,-p -v,
Note 1. All packages are viewed from the top.
Note 2. Contact factory for flatpack and leadless chip carrier availability.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
5-13
5 -14
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SG3645
SILICON
GENERAL
II'
QUAD 2.5 AMP POWER DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG3645 is a quad high voltage, high current driver, ideal for driving
stepper motors. Each channel consists of TTL compatible inputs and open
cOllector-Darlington outputs with integral transient suppression diodes. A
common enable is provided to disable or enable all four outputs simultaneously. The output stages are capable of sinking 2.5 Amps with breakdown
voltages in excess of 60 volts. Thermal shutdown is provided to disable the
outputs if excessive die heating occurs. The SG3645 is specified for operation over the ambient temperature range of OOG to 125°C and is available in;
the thermally efficient plastic Batwing package.
•
•
•
•
Peak output currents to 3.5A
Output voltages to 60V
Integral clamp diodes
Common enable pin
• TTL compatible inputs
• Thermal shutdown protection
• Available in 16 pin Batwing DIP and a 20 pin
Batwing SOIC
BLOCK DIAGRAM
DIODE
COMMON
IN 1
OUT 1
OUT 4
ENABLE
2
*
LOGIC
GND
PINS 4, 5, 12, 13
PWR GND
AND SUBSTRATE
TRUTH TABLE
INPUT
ENABLE
OUTPUT
L
L
L
H
H
H
H
ON
OFF
OFF
OFF
L
April 1990
5-15
•
SG3645
ABSOLUTE MAXIMUM RATINGS (Note 1)
Output Voltage .............•.•........................•............................ 70V
Output Current (Each Output)
Continuous (Note 2) ......................................................... 3.0A
Peak (1% Duty Cycle, 'oN = 10ms) ..............................:.. 4.0A
Supply Voltage (Vs) ............................................................. 2SV
Logic Input Voltage ................................................................ 7V
Logic Supply to Substrate Voltage ...................................... 40V
Operating Junction Temperature
Plastic (W, DWW-Package) ........................................... 1SO·C
Storage Temperature Range ............................ -6S·C to 1S0·C
Lead Temperature (Soldering, 10 Seconds) ...................:300·C
Note 1. Exceeding these ratings could cause damage to the device. All currents are positive into the specified terminal.
Note 2. Maximum continuous output current is limited by the thermal resistance of the package·heat sink combination.
THERMAL DERATING CURVES
...
10.0,\
4.0
~,
I'!
~
,
3.0
~
~
~
a
2.0
~
~
(~
25
"
75
100
~+
lo9-461..,
~·10 ~b
"'0~~
2.0
~
125
AMBIENT TEMPERATURE -
~'\
IsIi'~
4.0
~
rl)ji",o."'~
0
r\.
~
i5
("'0.;",;; §<&''''.
1.0
"~'~
'.0
~
~~
i
0
\..
8.0
150
0
175
~
0
.....
0
25
50
75
100
\
125
150
175
CASE TEMPERATURE - "C
'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION VB CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Supply Voltage (Vs) ........................•....................... 4.SV to 20V
Output Voltage .......................................•..............•........•.. 60V
Logic Supply to Substrate Voltage .................................... 2SV
Note 3. Range over which the device is functional.
Output Current (Each Output)
Continuous ........•.......••.................................................. 2.SA
Peak (1% Duty Cycle, tON = 10ms) ................................ 3.SA
Operating Ambient Temperature Range
. SG3645 ............................................................ O·C to 125°C
ELECTRICAL SPECIFICATIONS (Static and Dynamic)
(Unless otherwise specified, these specifications apply for the operating ambient temperatures for SG3645 with ooe ,;; TJ ,;; 125°C and Va =5V. Low
duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.) (Note 4)
Test Conditions
Parameter
Logic 1lnputVo~e (VJ
Logic 0 Input Voltage (VIL)
Supply Curiant '.~ ~
OFF)
. ... .... (Is- ()N)
Input Hig~ purrent _(I~
.
. '.
(IEN(Hj)
Input Low. C:!lrrem.
. (11N(1.J .
(I
)
Output ~furatiQ~. v~Ita!ie('(VSAT)
(Note 5)
:J1s ;
"'.:""",,,"'
Output Leak~~e Curr~nt(!CEX)
.-
.
Diode Forward. Voltage (VF)
(Note 5)
."
VIN =VEN =5V, Vs=20V
VIN =VEN = OV, Vs = 20V
VIN =5V; Vs=20V
VEN = 5V; Vs = 20V
VIN = OV; Vs = 20V
VEN = OV; Vs = 20V
VIN .. Vel = 0.8V; Vs = 4.5V
lOUT = 1.5A
IQUT-2.5A
(Per Truth Table) Vs = 20V; VCEX = 60V
TJ =25°C'
.
. ..
TJ = O°C to 125°C
IF=1.5A
IF = 2.5A
5 -16
Min.
2
SG3645
Typ. Max.
-50
-70
0.8
15
35
10
10
·250
-250
1.2
1.8
1.75
2.65
1.5
1.8
25
250
2.1
2.65
8
21
Units
V
V
mA
mA
jIA
~
~.
~
V
V
~
~
V
V
SG3645
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Test Conditions
Diode Leakage Current (IA)
Input/Enable, Turn-on Delay (tON)
(Note S)
Input/Enable, Turn-off Delay (tOFF )
(NoteS)
Thermal Shutdown (TT~) (Note 6)
Min.
VA = 60V
TJ =25°C
TJ = 125°C
TJ =25°C; Vs = 5V, lOUT = 1.5A,
VOUT =45V, Duty Cycle = 10%
TJ =25°C; Vs = 5V, lOUT = 1.5A,
VOUT =45V, Duty Cycle = 10%
Measured at Junction Temperature
SG3645
Typ. Max.
125
Units
25
250
IlA
500
1500
ns
500
150
1500
ns
°C
IlA
Note 4. Although device performance is guaranteed over the recommended junction temperature range, testing is not performed at the temperature
extremes.
Note 5. These parameters are tested using pulse techniques to minimize device heating.
Note S. These parameters, although guaranteed over the recommended operating conditions, are not tested in production.
CHARACTERISTIC CURVES
30
3.5
25
3.0
INPUT LOW
ENABLE lOW
3:
•
2.5
20
f-
z
f-
w
Z
W
0:
0:
:::J
u
:::J
U
~
a.
a.
2.0
0:
0:
15
1.5
f-
:::J
10
a.
f-
:::J
:::J
1.0
0
(f)
5
o
0.5
o
10
20
SUPPLY VOLTAGE -
10 20 30 40 50 60 70 80 90 100
(V)
(%)
DUTY CYCLE -
FIGURE 1.
SUPPLY CURRENT
FIGURE 2.
RECOMMENDED MAXIMUM PEAK CURRENT
VS. DUTY CYCLE
2.5
1.75
TJ
~ 125'~n
./
2:
2.0
"«
~
1.5
0
>
z
0
F'
TJ ==
1.0
TJ~1~
«
0:
:::J
f-
«
(f)
oOc
2:
:P
w
V
~
"«~
TJ = oOc
0
>
0
0:
TJ
1.0
«
3:
TJ
0:
1.0
=
l~OC
0
NOTE:
THESE TESTS ARE MEASURED
USING ~ULSE TECHNIQUES TO
MINIMIZE DEVICE HEATING.
o
0.5
aOc
~ of~
'"
NOTE:
THESE TESTS ARE I.4EASUREO
USING PULSE TECHNIQUES TO
MINII.4IZE DE\1CE HEATING.
o
TJ:::
v~
w
0.5
o
1.5
1.5
2.0
OUTPUT CURRENT -
2.5
3.0
o
0.5
1.0
1.5
2.0
DIODE CURRENT -
(A)
FIGURE 3.
SATURATION VOLTAGE vs. OUTPUT CURRENT
(A)
FIGURE 4.
DIODE FORWARD VOLTAGE VS. DIODE CURRENT
5-17
2.5
3.0
SG3645
APPLICATION CIRCUITS
+VSS
+VSS
15
15
16
16
IN1
IN1
14
3
14
6
11
IN3
7
10
IN4
IN2
IN2
11
IN3
IN4
I
100JLF
I
100JLF
EN
50V
EN
+
4,5,12,13
n
H
1
H
1
-VEE
50V
lOOI'F
I50V
-::-
NOTE:
WHEN OPERATING USING A
SPLIT SUPPLY, INSURE
THAT THE LOGIC GROUND TO
NEGATIVE SUPPLY DOES NOT
EXCEED 25V.
-::-
FIGURE 5 - POSITIVE SUPPLY
+
FIGURE 6 - SPLIT SUPPLY
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Note Below)
Package
16-PIN PLASTIC BATWING
W-PACKAGE
Part No.
SG3645W
Ambient
Temperature Range
Connection Diagram
Doe to 700 e
INl [
ENABLE [
IN2 [
1
'-.,./ 16
2
3
15
,.
EMITTER I SUBSTRATE [ •
IN3 [ •
•
IN4 [ 7
LOGICGND [ 8
20-PIN PLASTIC
BATWING S_O.I_C.
DWW - PACKAGE
SG3645DWW
Doe to 70 0 e
INl IT
ENABLE IT
IN2 IT
EMITTER I SUBSTRATE [
IN3 IT
IN4 IT
LOGICGND IT
P OUTl
P DIODE COMMON
P OUT2
13 ]
12
11
10
9
EMITTER I SUBSTRATE
J OUT3
J OUT4
J V,
JJ
JJ
1
20
2
19
3
7
,.,.
~r'
8
13
,.
12
11
•
•
•
9
OUTl
DIODE COMMON
EMITTER I SUBSTRATE
,.
!JJ OUT3
!JJ OUT 4
tTI
V,
Note 1. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
5-18
SG3663
SILICON
GENERAL
DUAL SOLENOID / MOTOR DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG3663 is a dual high-voltage, high-current monolithic I.C. recommended fordriving solenoids and stepper motors. Each output stage contains
sink/source drivers rated to ±3.5A peak currents with breakdowns in excess
of 50V. Internal suppression diodes provide protection when switching
inductive loads. The output stage can be configured to drive two separate
loads or a single load in an H-bridge configuration.
o Dual outputs rated at ±3.5A peak current
• Chop or non-chop load current control
• Current sense comparator with variable
threshold and hysteresis
• Internal clamp diodes for transient
suppression
• Single supply operation (8V to SOY)
• Thermal shutdown protection
o Available In two different power SIP's rated
at 9JC < 2°CfW
The SG3663 offers load current control through the implementation of an
internal current sense comparator to control the high side driver. Peak and
average currents are set by controlling the threshold voltage on the sense
comparator. A mode select pin determines if the SG3663 is operating in the
chop or non-chop mode.
The SG3663 is available in two types of power SIP and is rated to junction temperatures of O°C to 125°C.
BLOCK DIAGRAM
•
Vee
SOURCE 1
SOURCE 2
SINK 1
SINK 2
TRUTH TABLE
INPUT
0
0
0
0
1
DC =
Don~
MODE CONTROL
o(Non-chop)
o(Non-chop)
1 (Chop)
1 (Chop)
DC
VSENSE
< VTH 110
> VTH /10
VTH /10
DC
care
April 1990
5 -19
SINK
SOURCE
DRIVER DRIVER
ON
ON
ON
OFF
ON
ON
ON
OFF
OFF
OFF
SG3663
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (VCC) ........................................................... 55V
Operating Junction Temperature ...................................... 150°C
Logic Input Voltage ................................................................ 7V
Storage Temperature Range ............................. -65°C to 150°C
Threshold Input Voltage (VTH ) ............................................... 5V
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Source/Sink Output Current (Each Output):
Continuous ................................................................... ±3.5A
Peak ............................................................................. ±4.4A
Note 1. Exceeding these ratings could cause damage to the device. All currents are positive into the specified terminal.
THERMAL DERATING CURVES
5.0
100
4.0
.0
~
~
~
I
3.0
I
~
~
c
"
2.0
~
1.0
0
0
~
ill
N......'r
25
5
~'I'~~~
50
75
.........
40
",.'r
(''''',0,;
~
I'
100
60
'I'~
~
20
~
125
150
0
175
0
25
50
75
~~
"-
100
"-
125
150
175
CASE TEMPERATURE - 'C
AMBIENT TEMPERATURE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage (Vee) .................................................. SV to SOV
Source/Sink Output Current (Each Output):
Continuous .................................................................... ±3.0A
Peak .............................................................................. ±3.5A
Note 2. Range over which the device is functional.
Threshold Input Voltage (VTH ) ................................ 0.6V to S.OV
Ambient Temperature Range (TA) .......................... O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of T. = 25°C, Vee = 50V, and RSENSE = 0.1 n. Low duty
cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Supply Current
(ICC(ON)
(ICC(OFF)
..
"Logic'~ Iriput Voltage (V&J
Logic 0 Input Voltage (V,l)
Logic 1 Input Current (I'H)
Logic Olnput Current (I,l)
ThreshOld Input Current (ITHH)
Threshold Hysteresis Current (IHYs)
Sour~ Qutput Saturation Voltage
(VSAT) (Note 3)
Sink O~ut Saturation Voltage
(VSAT) (Note 3)
SourcelSlnkleakage Current C1ceJ
Source Diode Forward Voltage (VFl
Test Conditions
V,N " VMOoe " OV, lOUT" OA
V,N =VMODE =2.7V
Input 1Mode Control
Input / Mode Control
V'N =VMOOE =2.4V
V,N = VMODE =O.4V
VTH ';' 0.6V to S.OV, VTH ;:: VSENSE X 10
VTH =0.6V to 5.0V, VTH ;:: VSENSE X 10
V'M = OV, lOUT = -2A
V'N =OV, lOUT =-3.SA
V'N .OV, lOUT. 2A
V,N = OV, lOUT = 3.SA
V,N .2.4V, VSOURCE " OV
V'N =2.4V, VSINK .. SOV
V'N =2.4V, ISOURCE =-2A
V,N =2.4V, ISOURCE" -3.SA
5-20
Min.
SG3663
Typ_ Max_
12
25
12
25
2.0
140
O.S
100
-1.0
-100
200 260
1.85 2.2
2.0
2.6
1.3
1.8
2.1
2.6
100
100
-1.2 -1.6
-1.4 -2.0
Units
mA
mA
V
V
J.IA
mA
J.IA
J.IA
V
V
V
V
J.IA
J.IA
V
V
SG3663
ELECTRICAL SPECIFICATIONS (continued)
Parameter
503663
Test Conditions
Sink Diode Forward Voltage (VF)
Diode Leakage Current (I A)
Output Current Regulation (IAEG)
Propagation Delay (Note 4)
(TplH )
(TpHl)
Min.
V,N =2.4V. ISINK =2A
V,N =2.4V, ISINK =3.5A
V,N =2.4V, VSOUACE =50V
V,N =2.4V, VSOUACE =OV
VTH =2.0V to 3.6V
VTH = 1.0V to 2.0V
VTH =0.6V to 1.0V
SO% V,N to 50% VOUT
lOUT =2A (resistive)
-5
-10
-25
Thermal Shutdown (TTH)
Typ. Max.
1.75 2.2
2.3
2.8
100
100
S
10
2S
2.S
3.0
160
Units
V
V
jlA
j.lA
%
%
%
j.ls
j.ls
°C
Note 3. These parameters are tested using pulse techniques to minimize device heating.
Note 4. These parameters are guaranteed by design but not 100% tested in production.
CHARACTERISTIC CURVES
4
4
S'
S'
I"
w
I"
w
t:l
""o
t-
t:l
3
..J
-----
>
z
>=
0
SOURCE
2
'"""
::;)
t-
""
(f)
1
..........
~~
~
""t-
3
..J
§?
~
0
'"""
2
-
V
l-/
;...... I--'
;::
'"o
....
1
SOURCE
. /~
~
~
0
0
1
0
0
4
3
2
1
2
3
4
FORWARD CURRENT -(A)
OUTPUT CURRENT-(A)
FIGUAE2.
DIODE FORWARD VOLTAGE
VS. FORWARD CURAENT
FIGUAE 1.
OUTPUT SATURATION VOLTAGE
VS. OUTPUT CURRENT
APPLICATION NOTES
1/2 SG3663
~i
r
O.ln
SOURCE 2
SOURCE 1
.r-..
~
SINK 1
SENSE 1
1. When using the SG3663 in an H-bridge configuration, external diodes must be used. These diodes must be high speed
with voltage ratings above 70V and capable of handling SA.
Care should also be taken not to simultaneously turn on both
inputs.
1/2 SG3663
SINK 2
i31
r
2. PC Board layout - The output current is controlled by both the
voltage of the Sense pin and the sense resistor. Because of
the large currents and low resistance, it is critical to have
extremely good PC board layout to reduce parasitic wiring resistances which could add to the sense resistor and reduce the
output current.
SENSE 2
O.ln
-=-
3. Decoupling of the. Vcc supply with a 10j.lF electrolytic is
recommended.
-=FIGURE 3· H·BRIDGE CONFIGURATION
S - 21
•
SG3663
FUNCTIONAL DESCRIPTION
Vcc
NON-CHOP MODE
A logic "0" appli~d to the Mode Control pin will cause the SG3663
to operate in the non-chop mode. If a logic "0" then appears on the
Input pin, both the sink and source transistors will turn-on causing
the load current to rise according to:
Vcc'- VSATf - VSAT2 - L - } -IRsENSE = 0
SOURCE
SINK o-~f----'
t
solving for I(t)
vcc - VSAn - VSAT2 (1 _e -(RlL)t)
I(t) = ---"':.........:!=-'-----'==RSENSE
for l(t=O) = OA
1)
SENSE
This current will rise exponentially until it reaches a peak value
described in Equation 2.
2)
TH /10
IPEAK-_ -V0
-I
FIGURE 4. TYPICAL APPLICATION IN NON·CHOP MODE (Refer to Figures 4 & 5)
'SENSE
The comparator then trips, setting the latch and turning off the
source transistor.
Since the source transistor has been disabled and the coil current
cannot change instantaneously the currentflowwill be through 02
and will exponentially decay per the following:
3)
I(t) = - IpEAK e-(R/L)(t - T)
The load currentwill decay to "0" unless the latch is reset by pulling
the input high and then low again to activate the source driver.
When the input goes high both the sink and source turn off and the
current path is through 02, L, and 01. Figure 5 is a graphical representation of the above discussion.
CHOP MODE (Note: Only one section can be used at one time.)
A logic signal "1" on the Mode Control pin will cause the SG3663
to operate in the chop mode. As in the non-chop mode a logic "0"
on the Input pin will cause the sink and source transistor to turn on
with Equation 4 describing the current in the load.
4)
I(t) = Vee - VSAn - VSAT2 ' (1 ': e-(RlL)I)
RSENSE
Once IpEAK is reached the source transistor turns-off and a current
source (IH~s = +200J,LA) is activated on the threshold pin, This
current source lowers the effective threshold voltage by an
amount determined by a resis)or value RHVS . The load current will
decay until the new threshold is reached 'at which time the source
transistor is activated and the ,threshold 'is restored to its 'original
value by turning off the current source. The output current will rise
again until the original peak value has been reached. This
chopping action will continue until the Input pin' is'taken high
causing the load current to decay to OA. Figure 6 is a graphical
representation of the chop-mode action.
5-22
FIGURE 6 • CHOP MODE (Refer to Figure 4)
SG3663
DESIGN EXAMPLES - CHOP MODE (Refer to Figure 4)
Example 1Desired: 3.0A Peak, 20KHz Chop Frequency
Vee = 50V, L = 2mH, RSENSE = 0.10
Given:
Example 2A voltage divider on the reference supply can be used to
establish the necessary peak and hysterisis current.
Desired:
Given:
3.0A Peak, 10% Hysterisis Current
VREF = 5.0V, RSENSE = 0.10
A'
FIGURE 7.
1)
2)
THRESHOLD INPUT (VrH)
R
(3.0A) x (0.10) = 300mV
VSENSE
VTH
300mV x 10 = 3V
T
1
T, + T2 = 20KHz
V
L..5L
d,
dl1
T,=
FIGURES.
V =
.JJ SA12 - VII>
L
Vee - VSATI - VSAT2
L
50V - 2.0V - 2.0V
2mH
-2.0V-2.0V
2mH
23A1ms
:.T _
dl
= -2.0Alms
dl
3) % HYS -
-
(2~O + 2~) x -10"
RHyS (lpEAK X RSENSE X 10)
VREF - (lpEAK X RSENSE x 10)
2.5KO
= 92mA
R
dl
IpEAK
0.092A
2.5KO (3.0A x 0.10 x 10)
5.0V - (3.0A x 0.10 x 10)
3.75KO
(3%) (3V)
90mV
=
R
5.0V x 10%
2001lA
3%
5)
RHyS X VTH (peak)
VREF - VTH (peak)
dl
----y;:4)
R
23A1ms + 2.0Alms
_1_
20KHz
-
VREF X % Hysterisis
200!1A
L3L
d,
dVTH
200llA
90mV
200llA
4500
5 - 23
•
SG3663
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
12·PIN PLASTIC SIP
ST· PACKAGE
Part No.
SG3663ST
Ambient
Temperature Range
OOeto 70 0 e
Connection Diagram
W
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
GROUND
INI
SENSE 1
SINKI
SOURCE 1
THRESHOLD INPUT
Vee
SOURCE2
SINK2
SENSE2
IN2
MODE CONTROL
~
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
GROUND
IN 1
SENSE 1
SINKI
SOURCE 1
THRESHOLD INPUT
Vee
SOURCE2
SINK2
SENSE2
IN2
MODE CONTROL
00
1
12-PIN PLASTIC SIP
S·PACKAGE
SG3663S
°
12
OOeto 700 e
1
12
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
5-24
..,
SILICON
SG3700
;
GENERAL
DUAL HAMMER DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG3700 is a monolithic integrated circuit that will provide up to
900mA of current to each output. An external sense resistor and an
external reference control voltage is required for programming the
output current to the desired value. On-chip TTL-compatible logic
is provided for timing of the output current pulse duration.
•
•
•
•
•
Output current to 900mA
Output voltage to 40V
Built-in clamp diodes
Thermal protection
Logic control of pulse duration
BLOCK DIAGRAM
~S
16,~----------------------------------------------------~~
CRl
CR3
1
THERMAL
SHUT-DOWN
CIRCUITRY
CR2
H PROT
CR4
HD 2
S2
GND
VCl
XR 2
®--I GND
13;}--------------------------j---------------.J
C2
April 1990
5 -25
SG3700
ABSOLUTE MAXIMUM RATINGS (Note 1)
Driver Supply Voltage (Vss) ................................................ 42V
TIL Supply Voltage (Vcc) .................................................... 7V
TIL Logic Input Voltage With Respect To Ground (V ,N ) .... 5.5V
Output Current, Each Driver ................................................ lA
Control Voltage (VCL) ............................................................ 2V
VHPROT .................................................................................. Vss
Operating Junction Temperature
Plastic (N- Package) .................................................... 15O°C
Storage Temperature Range ............... ........... -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Values beyond which damage may occur.
THERMAL DERATING CURVES
2.5
50
2.0
4.0
~
~
,
1.5
~
~
~
"
~
1.0
,
i
I
"- ~<
~
is
0
25
50
75
~~
100
2.0
~
~<
0
"-
~
':Is-
0.5
'.0
is
"
1.0
"
125
ISO
0
175
0
'"
25
"'fi.,
'.o~
~
I~
0",_
50
7.
100
"-
125
ISO
175
AMBIENT TEMPERATURE - "C
CASE TEMPERAilJRE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Driver Supply Voltage (Vss) ................................................ 40V
TIL Supply Voltage (Veel .................................. 4.75V to 5.25V
Control Voltage (VCL) (On State) .......................... 1.2Vto 1.8V
Control Voltage (VCL) (Off State) .............................. OV to 0.4V
Note 2. Range over which the device is functional.
Output Current, Continuous .......................................... 900mA
Operating Ambient Temperature Range
SG3700 ........................... ........................... ........ O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specfiications apply over the operating ambienttemperatures for SG3700 with O°C S TA S 70°C. Low duty cycle pulse
testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Logic Section
Low Level Input Voltage(V ,L) (All Inputs)
Low Level Input Current (I,L) (All Inputs)
High Level Input Voltage (V,H) (All Inputs)
High Level Input Current (I,H) (All Inputs)
Input Clamp Voltage (V ,K)
Control Section
Control VoHage Input Current (ICL)
Protection Section
HPROT Output Voltage, Low State
(Thermal Shutdown) (VHPROT)
HPROT Leakage to Ground (IHPROT)
HPROT Leakage from V•• (I"PROT)
Test Conditions
I
SG3700
I Units
I Min. Typ.iMax.i
0.8
-1.6
Vcc =5.25V, V,N =0.4V
2.0
Vcc = 5.25V, V,N =2.4V
Vee = 5.25V, VIN = 5.5V
Vcc =4.75V, liN =12mA
Vcc = OV to 1.8V
IHPROT =1.5mA
VHPROT = OV, Vss = 40V
V"PROT = V•• = V"n = 40V, V~~ = 5V
5-26
I
V
mA
V
40
1.0
-1.5
rnA
V
i ·0.2 i -1.0
I ItA
2.0
-100
5
ItA
ItA
ItA
V
8G3700
ELECTRICAL SPECIFICATIONS (continued)
Parameter
SG3700
U 't
I Min. I Typ. I Max. I m s
Test Conditions
Output Section
Output Transistor Saturation Voltage (VCEISAT))
Output Current Low, Off State (lOl)
XRt' XR2 Voltage, On State (VXR)
XR 1, XR2 Voltage, Off State (VXR) (Note 3)
Forward Voltage (CRt' CR2) (VF)
Forward Voltage (CR 3 , CR.) (VF)
Leakage Current (CRt' CR,) (I R)
Supply Section
Total Supply Current (Icc)
1.5
1.0
Ic = 900mA, VCl = 1.2V to 1.8V
Vss = VHO = 40V
Driver on, VCl = 1.2V to 1.8V, TA =25°C
Driver on, VCl = OV
IF= 900mA
IF= 1mA
Vss = 40V, VHO = OV
O.97VCL
50
1
3
3
30
30
Note 3. VXR voltage in off-state shall not exceed specified value when Vee is changed from +5V to av.
SWITCHING WAVEFORM AND TIMING DIAGRAM· FIGURE 1
~
WM &
",,-WLLh~CL.:;;0j'-LLA-_---"-"~CL.'-LLLCL.'--_.L~'-LLLc.c.
--j ill'S MIN
HAMMER DRIVE CURRENT
TYPICAL APPLICATION
TO FAULT DETECTING
CIRCUITRY
VSS
33K
TO "HPROT" PIN ON
All OTHER HAMMER ~----+
DRIVER IC'S
HPROT
r-------------
I
I
I
I
I
TO 2ND
VSS
I
I
I
I
I
~==ir==~=l===:::l
VCl (
CLEAR
DATA
SET
Rx =
5-27
70
SG3700
I
I Min. I Typ. Max.
Test Conditions
Dynamic Characteristics (V•• - 4aV, Rx - 2(1, RH - 32(1, L,. - a and T. - 25°C)
Pulse Width, S & C Inputs (Ip)
See Figure 1
Hammer Drive Current Turn·on Delay (toION))
Hammer Drive Current Turn-off Delay (toIOFF))
Hammer Drive Rise Time (tR)
Hammer Drive Fall Time (IF)
DATA
1.03VCL
450
3.0
1.0
100
Outputs in Off State, Logic Inputs Low
Parameter
VCl
2,00
V
mA
V
mV
V
V
IIA
mA
Units
IJ.S
IJ.S
IlS
Ils
IJ.S
SG3700
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Note Below)
Package
16·PIN PLASTIC DIP
N- PACKAGE
Note:
Part No.
Ambient
Temperature Range
SG3700N
O°C to 70°C
Connection Diagram
HPROT [~::J v"
HD 1 [ 2
15::J HD 2
XR 1 [ 3
14::J XR 2
Vee
[4
13:::J
S1
DATA 1
C1
GND
[5
12::J S2
Va.
[6
11::J DATA 2
[7
,.::J 'C2
['-'------!.::J N.C.
1. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
5 - 28
•
SG3718
SILICON
GENERAL
ADVANCED DATA SHEET
STEPPER MOTOR DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG3718 is a monolithic integrated circuit intended to drive one phase
winding of a bipolar stepper motor with chopper control of the phase current.
o
Pin to pin compatible with all industry
standard 3717s I 3718s
o Full-step, half-step and micro-step
capability
o Bipolar output current up to 1.SA
o Wide range of motor supply voltage 1046V
o Built-in fast recovery commutating diodes
o Current levels selected in steps or varied
continuously
o Output stage shoot-through protection
o Thermal shutdown protection
o Low saturation output stage
o Designed for unstabllized motor supply
Current levels may be selected in three steps by means of two logic inputs which
selects one of the three current comparators. Each comparator is set to a
different threshold level with the divider network off of the reference input. A
monostable programmed by an external RC network sets the current decay time
to control the average current in the winding. A seperate logic input controls the
direction of current flow. The output section features an H-bridge with four fast
recovery com mutating diodes for current recirculation. An external connection
to the lower emitters is available for insertion of a sensing resistor.
The SG3718 is available in 16 pin plastic batwing. 20 pin batwing S.C.I.C. and
28 pin PLCC packages.
BLOCK DIAGRAM (Pin numbers are for plastic batwing W - Pkg only.)
Vee
"M
lOGIC SUPPLY
MOTOR SUPPLY
"M
MOTOR SUPPLY
}---~.3}-------~
OUTPUT STAGES
16
4.5
12.13
GND
COMPARATOR
INPUTS
EMlnERS
TIMING
INPUT
TRUTH TABLE
Input a (I,)
Input 1 (I,)
H
L
H
L
H
H
L
L
Mode
No current
Low current
Medium current
High current
April 1990
5-29
SG3718
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltages
Logic Supply , Vee ..................................................... OV to 7V
Output Supply, VM •••••••••••••••••••••••••••••••••••••••••••••••••• OV to 50V
Input Voltage
Logic Inputs ......................................................... -0.3V to 6V
Analog Input ....................................................... -0.3V to Vee
Reference Input ....................................•............. -0.3V t015V
Input Currents
Logic Inputs ................................................................. -10mA
Analog Inputs ............................................................... -1 OmA
Output Current ................................................................. ±1.5A
Operating Junction Temperature
Plastic (W, DWW, Q Packages) ....................................125°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) .................... 300°C
Note 1. Values beyond which damage may occur. All voltages are measured with respect to ground, and all currents are defined as positive flowing
into the device (unless otherwise specified).
THERMAL DERATING CURVES
5.0,--;---;,..---,---,---,----r---,
10.0 ~-,..---,---,----r---,--....,--,
4.01--1-----11--____1-____1-____1-_+---1
8.0~-~____I-____I-_+-_+-_+---l
I 6.0 p".---t-7.~~
~
is
i
c
Bi
a
2.0
4.0
I
I
2.0 1--1--l--+-~~N--+---1
1.01--1---'-
175
AMBIENT TEMPERATURE - "c
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION VB AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage
Logic Supply, Vcc ............................................... 4.5V to 5.5V
Output Supply, VM ••••••••••••••••••••••••••••••••••••••••••••••••• 1OV to 45V
Output Current ................................................. ,±20mA to ±1.2A
Note 2. Range over which the device is functional.
Logic Input Rise Times ................................................. < 211sec
Logic Input Fall Times ................................................... < 211sec
Operating Ambient Temperature Range
SG3718 .............................................................. O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specfiications apply over the operating ambient temperatures for SG3718 with o·e :s; T. :s; 70·e, 10V < VM < 4SV,
4.SV < Vcc < S.SV, and VR = SV (Refer to the test circuit, Figure 1). Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
Parameter
Test Conditions
Bias Supply
Logic Supply Current, Icc
Total Power Consumption (Note 3)
Total Power Dissipation
1M" 0.5A, f, = 30KHz, VM= 36V
1M = 0.8A, f, = 30KHz, VM = 36V
1M ='1A, f... 30KHz, Vu" 36V
Thermal Shutdown Temperature
Self heating
Logic Inputs
Logic Input Low Voltage
Logic Input High Voltage
Logic
Voltage Input CUrrent.
VI =0.4V
High Voltage Input Current
VI =2.4V
Refenmce Input Current
VR .. SV
Note 3. These parameters, although guaranteed, are not tested in production.
Low
5-30
SG3718
Units
Max. I
IMin. ITyp.
9
30
mA
1.4
2.8
3.1
1.7
3.3
3.8
190
W
150
0.8
2
-400
W
W
°C
V
V
I1A
0.4
20
1.0
I1A
mA
SG3718
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Test Conditions
Comparators
Low Threshold Voltage
Medium Threshold Voltage
High Threshold Voltage
Input Current
Cutoff Time, TOFF
Turn Off Delay, To
Source Diode - Transistor Pair
Saturation Voltage, V SAT
Leakage Current
Diode Forward Voltage, V F
Sink Diode - Transistor Pair
Saturation Voltage, V SAT
Leakage Current
Diode Forward Voltage, V F
SG3718
Units
IMin. Typ. Max.
V R = 5V, 10 = L, I, = H
V R = 5V, 10 = H, I, = L
V R = 5V, 10 = L, I, = L
65
230
390
-20
25
RT = 56KQ, C T = 820pF, V M = 10V, TON> 511sec
TA = 25°C, dVe I dt > 50mV/Ilsec
80
250
420
30
1.05
1.2
1.3
1M = -0.5A, (See Figure 2)
1M = -0.8A
IM= -1A
V M = 40V, 10 = H, I, = H
1M = -0.5A
1M = -0.8A
I =-1A
1.1
1.2
1.3
1.0
1.0
1.2
1M = 0.5A
1M = 0.8A
IM= 1A
V M = 40V, 10 = H, I, = H
IM= 0.5A
1M = 0.8A
IM= 1A
1.1
1.3
1.1
90
270
440
+20
35
2
mV
mV
mV
I1A
I1s
1.2
1.4
1.5
100
1.5
1.45
1.6
V
V
V
IlA
V
V
V
1.2
1.25
1.3
100
1.5
1.7
2.0
V
V
V
IlA
V
V
V
Il s
PIN DESCRIPTION
Pin Name
Description
Pin Name
OUTPUT 8 (80UT)
Output connection (with OUTPUT A). The
output stage is a "H" bridge formed by four
transistors and four diodes suitable for
switching applications.
PULSE TIME (TIMING)
A parallel RC network connected to this pin
sets the OFF time of the lower power transistors. The pulse generator is a monostable triggered by the rising edge of the
output of the comparators (TOFF = 0.69
RTC T)·
SUPPLY VOLTAGE 8
This pin and INPUT 0 are logic inputs which
select the outputs of the three comparators
to set the current level. Current also depends on the sensing resistor and reference voltage. See truth table.
INPUTO (1 0)
See INPUT 1.
COMPARATOR INPUT
(CURRENT)
Input connected to the three comparators.
The voltage across the sense resistor is fed
back to this input through the low pass filter
ReCe' The lower transistor are disabled
when the sense voltage exceeds the reference voltage of the selected comparator.
When this occurs the current decays for a
time set by RTCT , TOFF = 0.69 RTCT .
REFERENCE (V R)
A voltage applied to this pin sets the reference voltage of the three comparators, this
determining the output current (also thus
depending on Rs and the two inputs INPUT
o and INPUT 1).
Supply voltage input for output stage
(VM)
GROUND
Ground connection. This will provide good
heat conduction from die to printed circuit
copper.
LOGIC SUPPLY (Vee)
Supply voltage input for logic circuitry.
PHASE
This TIL-compatible logic input sets the direction of current flow through the load. A
high level causes current to flow from OUTPUT A (source) to OUTPUT 8 (sink). A
schmitt trigger on this input provides good
noise immunity and delay circuit prevents
output stage short circuits during switching.
Description
INPUT1 (I,)
OUTPUT A (AOUT)
See OUTPUT 8 pin.
SENSE RESISTOR
(EMITIERS)
Connection to lower emitters of output
stage for insertion of a current sense resistor.
5- 31
•
SG3718
TEST CIRCUIT & TYPICAL WAVEFORMS
+5V
Vee
LOGIC SUPPLY
SG3718
+5V
OUWUT STAGES
4,5
12.13
GNO
~-------------{~----------------------------~1.~--------------~
TIMING INPUT
EMITTERS
~----~~'K~------~----------------------------~~S
Cc
Rr
Rc
56K
820pF
Or
820pF
FIGURE 1 - SG3718 TEST CIRCUIT (Pin numbers are for plasfic batwing W-pkg only)
(D) VBDUT(Pin 1)::
I-I--------r--------,-t
FIGURE 2 - TYPICAL WAVEFORMS WHEN PHASE INPUT IS LOW
(Pin numbers are for plastic batwing W·pkg only)
5 - 32
"sENSE
1n
SG3718
TYPICAL APPLICATION
+5
+5
+40
AOUT
PHASE A
'1'
7 '1
0'
9 '0
STEPPING MOTOR
8
5G3718
AO 15
Cs
16
BOUT
4.5
12.1.3
10
820pF
+5
+5
+40
AOUT
PHASE B
'1·
7 '1
bB
9 '0
5G3718
AO 15
Cs
16
BOUT
4.5
12,1.3
10
B20pF
•
(Pin numbers are for plastic batwing W-pkg only)
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
16·PIN PLASTIC BAffliNG
W-PACKAGE
Part No.
SG3718W
Ambient
Temperature Range
Connection Diagram
DOC to 7DoC
1
TIMING [
2
1S
v. [ ,
14
GND [ ;
Vee [ 6
I, [ 7
PHASE [ •
20-PIN PLASTIC
BAffliNG S.O.l.C
DWW·PACKAGE
SG3718DWW
DOC to 7DoC
AOUT
Vy
130
GND
11
VR
12
P
1O!J COMP.IN
9P I,
1
20 I I EMITTERS
,
19 I I
Ao",
~:
GND
1,0:
PHASE 0:
1. GROUND
2. GROUND
3. GROUND
4. Viol
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
P
P
EMITTERS
B"", 0:
::[
SG3718Q
O°C to 70°C
P
TIMING 0:
Vee IT
28-PIN PLASTIC LEADED
CHIP CARRIER (PLCC)
Q-PACKAGE
16
B"", [
N.C.
Ao.,
N.C.
EMITTERS
GROUND
BOUT
TIMING
GROUND
GROUND
GROUND
2
4
5
•7
•
T'
14
13:0 VR
9
12 I I COMP.IN
10
11 I I I,
4321282726
'0"
•
24
7
•
9
10
2'
22
21
20
11
19
12 13 14 15 16 17 18
15. GROUND
16. GROUND
17. GROUND
18. Vee
19. I,
20. PHASE
21.10
22. N.C.
23. COMPIN
24. VR
25. N.C.
26. N.C.
27. N.C.
28. GROUND
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 696-6121 .fflX: 910-596-1604. FAX: (714) 693-2570
5-33
5 - 34
I
THUMB INDEX
N
SILICON
GENERAL
-
;
III
III
111
III
III
I
III
I
III
1111
.1
III
III
TABLE Of CONTENTS
PART NUMBER
GENERAL
[POWIE~
~NIFORMATION
~NIFORMAT~OINl
SUPPLY
C~IACU~lrS
MOT~O~
CONTROL
POWER
IDR~VIE[R
C~RCU~lrS
AND
~NTlEIRFACIE
O[P[ERAlr~O~ AMfPUIF~ERS
AND COMPARATORS
CORlE MEMORY C~RCU~TS
AUTOMOT~V[E C~RCU~TS
OTHER
CIIRCU~TS
PACKAGE
~NfORMAT~ON
A[PPUCAT~ON ~NIFORMATION
SALES
OIFIF~CES
6 -1
CIRCUITS
I
I
I
I
I
I
I
I
I
I
I
I
I
•
II
SELECTION GUIDE
POWER DRIVERS & INTERFACE CIRCUITS
SILI[ON
GENERAL
POWER DRIVERS
LINEAR INTEGRATED CIRCUITS
Device Type
Description
Typ. Application
Half-bridge • DC motor drivers
SG1635/2635/3635
SG1635N2635N3635A driver
• Stepper motor
100PKl
100CONl)
VC(MAX)
VCC(MAX)
5A
2A
35V
40V
35V
40V
Key Features
Pkgs.
SEE MOTION CONTROL CIRCUITS
drive
SG2000 Series
Darlington
arrays
• Logic to power
interface
• Lamp driver
• Motor driver
SG2800 Series
Darlington
arrays
• Logic to power
interface
• Lamp driver
• Motor driver
SG2064 thru SG2077
Quad power
Darlington
arrays
• Relays
• Solenoids
• DC and stepping
motors
• Display drivers
SG3645
Quad
driver
SG3663
SG3700
power
Dual solenoid
motor driver
Dual hammer
driver
O.SA
0.5A
50V
95V'
• Seven open collector Dar- J, N, OW,
lington arrays
L
• Internal clamp diodes
• High speed switching
• Closely matched parameters
0.5A
50V
95V'
• Eight open collector Darlington arrays
• Internal clamp diodes
• High speed switching
• Closely matched parameters
J, L
1.75A
1.5A
50V
80V"
• Four open collector Darlington arrays
• Internal clamp diodes
• 1.5V max. saturation at 1.5A
• Low internal parasitics
J,W
• Stepper motor
drive
• DC motor drive
• Lamp driver
• Relay driver
3.5A
2.5A
SOV
• DC motor drivers
• Stepper motor
drive
• Solenoid motor
drive
3.5A
• DC motor drivers
coil
• Hammer
drive in high
speed printers
1.5A
40V
SEE MOTION CONTROL CIRCUITS
3.0A
50V
50V
SEE MOTION CONTROL CIRCUITS
0.9A
5.25V
40V
SEE MOTION CONTROL CIRCUITS
.
..
- SG2021 thru SG2025 only
SG2821 thru SG2824 only
- For SG20S5, 20S7, 20S9, 2071, 2075, 2077 only.
November 1988
6-2
SELECTION GUIDE
POWER DRIVERS & INTERFACE CIRCUITS
SILICON
GENERAL
INTERFACE CIRCUITS
LINEAR INTEGRATED CIRCUITS
DevlceType
Description
Typ. Application
100PKl
IO(CONT)
Vo
Key Features
Pkgs.
SG1488
Quad line-driver
• Data communication interface
10mA
10mA
±12V
• Conformance with specifications of
EIA standard No. RS-232C
• Current limited outputs
• Power-off source impedance 300n
minimum
• Slew rate control with external capacitor
• Inputs compatile with DTL and TTL
logic
J
SG1489/SG1489A
Quad line receiver
• Data communicaton interface
20mA
10mA
10V
• Conformance with specifications of
EIA standard No. RS-232C
• Input resistance -3Kn TO 7Kn
• Input threshold hysteresis built in
• Logic threshold shifting
• Input noise filtering
J
SG16261262613626
SG16441264413644
Dual high speed
driver
• Driving power
MOSFETs
• Driving high capacitive loads
• Low voltage motor drive
3A
0.2A
22V 22V
•
•
•
•
•
•
•
SG1627/2627/3627
Dual high current • Driving bipolar or
output driver
MOSFETs
• Low curren1 DC
motor drive
1A
0.5A
30V 30V
• Dual uncommited totem-pole outputs
• Constant current drive capability
• Inverting and N.!. inputs
• 2V threshold for high noise immunity
• Full cmpatibility with 1524 outputs
J, N
SG1629/2629/3629
Floating switch
driver
2A
0.5A
20V 20V
• Single uncommited outputs
• Self generating positive and negative currents
• Floating operation
• Baker clamp input for non-saturated
switching
• Provisions for source and sink gating
T,R
SG5792
Quad pin diode • Phase shifters
driver
• Attenuators
O.5A
O.3A
50V
6V
• Four independent pin drivers
• Shorted diode protection
• TTL input compatible
J
SG5793
Quad pin diode • Phase shifters
driver
• Attenuators
0.2A
0.1A
-55V
7V
• Four independent pin drivers
• HCMOS compatible
• Output monitor pin for each output
J
Inv. (1626 series)
N.I. (1644 series)
high
• Driving
speed bipolar
power transistors
November 1988
6-3
Vee
Y,M,J,W,
Dual totem pole outputs
T,R
High speed Schottky logic
Frequencies beyong 1MHz
TTL input compatibility
Rise and fall times less than 25ns
Propagation delays less than 20ns
Efficient operation at high frequency
SELECTION GUIDE
POWER DRIVERS & INTERFACE CIRCUITS
SILICON
GENERAL
PERIPHERAL DRIVERS
LINEAR INTEGRATED CIRCUITS
Device Type
SG508
Description
Quad high vollage NAND driver
Typ. Application IO(PK)
o
o
Lamp drivers
Relay driver
O.5A
100CONl)
Vc
Vee
O.25A
100V
7V
Key Features
o
o
o
SG55325
SG55326
SG55327
Memory driver
o
o
o
SG554506I75450B
Dual peripheral
positive AND
driver
o
o
o
SG55460175460
o
o
Core memory
drivers
Relay drivers
Lamp drivers
O.75A
High speed logic
buffers
Relay drivers
Lamp drivers
Memory drivers
Line drivers
O.4A
O_6A
25V
O_3A
35V
7V
Two NAND gates and two
uncommited NPN transistors
o High speed switching
• TIL or DTL compatible diode-clamped inputs
o Can be configured as an
AND gate (common emitter
configuration) or as a NAND
gate (emitter follower configuration)
J, L
7V
o
Two AND gates with open
collector outputs
High speed switching
TIL or DTL compatible diode-clamped inputs
Y,L
Two NAND gates with open
collector outputs
High speed switching
TIL or DTL compatible diode-clamped inputs
Y,L
Two OR gates with open
collector outputs
High speed switching
TIL or DTL compatible diode-clamped inputs
Y, L
Two NOR gates with open
collector outputs
High speed switching
TIL or DTL compatible diode-clamped inputs
Y,L
I40V
SG55461 175461
70V
o
o
o
SG55471 175471
o
o
SG55452BI754528
SG55462175462
Dual peripheral
positive NAND
driver
o
o
o
SG55472175472
o
o
SG5545361754538
SG55463175463
Dual peripheral
positive
OR
driver
o
o
o
SG55473175473
o
o
SG554546175454B
SG55464175464
Dual peripheral
positive NOR
driver
o
o
o
SG55474175474
o
o
H
7V&25V
I-
Dual peripheral
positive AND
driver
Pkgs.
SEE CORE MEMORY CIRCUITS
SG55470175470
SG55451 B175451 B
Four NAND gates with open
collector outputs
Pinning compatible with 541
74 logic series
Inputs compatible with DTU
TIL
High speed logic
buffers
Relay drivers
Lamp drivers
Memory drivers
Line drivers
O.4A
High speed logic
buffers
Relay drivers
Lamp drivers
Memory drivers
Line drivers
O.4A
High speed logic
buffers
Relay drivers
Lamp drivers
Memory drivers
Line drivers
O.4A
High speed logic
buffers
Relay drivers
Lamp drivers
Memory drivers
Line drivers
O.4A
O.3A
30V
o
I35V
o
I70V
.0
O.3A
30V
7V
o
I35V
o
-
o
70V
O.3A
30V
7V
o
35V
o
-
o
70V
O.3A
30V
7V
o
~
35V
o
I-
o
70V
November 1988
6-4
8G508
SILICON
GENERAL
QUAD-NAND DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG508 is a Quad 2-lnput NAND Driver with outputs capable of sustaining
100V breakdown voltage. Each TTL-compatible NAND gate controls a
500mA output sink transistor. This combination of a TTL-<:ompatible gate
with high current output driver allows the designer to interface low-level logic
circuits to power loads. It is also ideal for sense circuit applications.
• Quad drivers with TTL-compatible logic
• 500mA output sink current
• 100V output breakdown voltage
HIGH RELIABILITY FEATURES
-SG508
The high breakdown voltage and current sink capabilities of these devices
make them the perfect choice for driving incandescent lamps, relays and
other peripheral devices.
• Available to MIL-STD-BB3 and DESC SMD
• SG level "S" processing available
The SG508 driver is a direct replacement for the Sprague UHD508 and is
available in the side-brazed hermetic package (H-package). The SG508
Quad NAND driver is characterized for operation overthefull military ambient
temperature range of -55°C to 125°C and can be ordered in custom or other
high-reliability screening flows.
BLOCK DIAGRAM
o
vee
1Y
1A
1B
2Y
2A
2B
3Y
3A
3B
4Y
4A
4B
GND
FUNCTION TABLE (each driver)
A
B
Y
L
L
H (off-state)
L
H
H (off-state)
H
L
H (off-state)
H
H
L(on-state)
H = High Level, L = Low Level
April 1990
6-5
'SGS08
ABSOLUTE MAXIMUM' RATINGS (Note 1)
Supply Voltage (Vee) .................................................... 7.0V DC
Input Voltage ................................................................ 5.5V DC
Output Off-State Voltage ............................................. 100V DC
Output On-State Current ................................................ 500mA
Operating Junction Temperature
.'
Hermetic (H-package) .................................................. 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) ................... 300°C.
Note 1. Exceeding these ratings could cause damage to the device. All currents are' positive into the specified terminal.
THERMAL DERATING CURVES
2.5
50",
2.0
4.0
~
~
~
I
I
~
1
~
1.0
is
I~'b.,
i
~""'"I~
05
0
~
~«'.04V~
~.
0
3.0
25
50
75
100
~" .
~
~
,.5 "
~
"
'\
E
~""~~
~\
2.0
i
10
"
125
150
0
175
0
AMBIENT TEMPERATURE - "c
25
50
75
100
\
125
150
175
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage (Vcel .............................................. 4.5V to 5.5V
Maximum Current Into Any Output (On-State) .............. 250mA
Minimum High Level Input Voltage (V1H) ............................ 2.0V
Maximum Low Level Input Voltage (VIJ ............................ 0.8V
Operating Ambient Temperature Range (T)
SG508 ............................................................ -55°C to 125°C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise stated, these specifications apply over the operating ambient temperatures for SG 508 with -55°C:s; T. :s; 125°C. Low duty cycle
pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Input Current High (IIN(I~
Inpu! Current Low (IIN(O)
Output Reverse Current (10Ff)
Output Voltage Low (VON)
Level Supply Current, High (100(1 )
Level Supply Current, Low (lee(o)1
Propagatfon Delay Time
.
Turn-on (tpo ON)
Turn-off (t;,~OFF)
Test Conditions
Other input = OV
Driven input = 2.4V
Driven input =S.5V
Other input =4.5V, Driven input =0.4V, VfX =5.5V, Vour =100V
Other input =Vcc ' Driven input =0.8V, Vcc =4.5V
Vee =4.5V,.AII inputs =2.0V
-55°C sTA< 25°C,. Output = 150mA
-55°C s TA < 25°C, Output =250mA
TA = 125°C, Output = 150mA .
TA= 125°C, Output = 250mA
TA =25°C, Vee =5.5V, All Inputs =OV
TA =25°C, Vec =5.5V, All Inputs = 5.0V
Vs = 100V, CL = 15pF, Vec = 5.0V, RL = 6700
6-6
Min.
SGSOB
Typ. Max.
Units
40
1000
-800
100
iJA
iJA
0.5
0.7
0.6
O.B
30
106
V
V
V
mA
mA
500
750
ns
ns
IlA
iJA
V
SG508
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
14-PIN SIDE-BRAZED DIP
H - PACKAGE
Part No.
SG508H/883B
SG508H
Ambient
Temperature Range
-55°C
-55°C
to 125°C
to 125°C
Connection Diagram
1A [l1'714p vee
16 [ 2
13 iJ 4A
1Y [ 3
12 P 46
2A[411iJ 4Y
26[51OP3A
2Y[6
SP36
GNO [~iJ 3Y
•
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General.
11861 Western Avenue. Garden Grove, CA 926410 (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
6-7
6-8
SG1488
SILI[ON
GENERAL
QUAD RS-232C LINE DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1488 is a monolithic quad line driver designed to interface data
terminal equipment with data communications equipment in
conformance with specifications of EIA standard No. RS-232C.
•
•
•
•
•
Current limited output 1OmA typical
Power-Off source impedance 3000 minimum
Simple slew rate control with external capacitor
Flexible operating supply range
Compatible with all DTL and TTL logic families
HIGH RELIABILITY FEATURES - SG1488
• Available to MIL-STD·BB3
• SG level "s" processing available
CIRCUIT SCHEMATIC ('/4 Circuit Shown)
V+ 140-----.----------.------.-----,
R
B2K
INPUT 4
r-..O---jI4----t
INPUT 5
0--_---+
t-7_0_r-----''-------.~3N00Io---Qr'\ 6
OUTPUT
;=}36K
GN07~
V
l
I
r
'OK
v- ,
'']
~7K
70
LOGIC DIAGRAM
(1A)
2~3
~
L-/'
~
(1Y)
,(4A) 12
4B) 13
(
~11
o-----L../'
(2A) 4 : D - - - o ( )
(2B) 5
6 2Y
-L
..
~
(4Y)
07 (GND)
-:-
V+
(3A) g : D - - - o
(3B) 10
8 (3Y)
V-
POSITIVE LOGIC: Y=AB
FUNCTION TABLE
INPUTS
A
S
OUTPUT
y
H
L
H
X
X
L
L
H
H
H = high level, L = low level,
X = irrelevant
April 1990
6-9
.
014 (+VCC)
01 (-Vccl
•
SG1488
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ................................................................ ±15V
Input Signal Voltage .................................... -15V::; Y'N ::; 7.0V
Output Signal Voltage ...................................................... ±15V
Operating Junction Temperature
Hermetic (J-Package) .................................................... 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL DERATING CURVES
2.5
50,\
2.0
~
~
I
1.5
is
~
~
~
6
1.0
~
4.0
""
I
~~
~\oq,
0.5
0
~
0
25
50
5
~
100
""'"~,""~~
2.0
~
~
75
'\r\.
3.0
"'
AMBIENT TEMPERATURE -
1.0
"
125
150
0
175
0
25
·c
50
75
"'\
100
125
150
175
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage ................................................................ ±12V
Input Signal Voltage .................................................... V- t05V
Note 2. Range over which the device is functional.
Operating Ambient Temperature Range
SG14BB ................................................................ O°C to 75°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over full operating ambient temperatures for SG14BB with D'G ,,; TA ,,; 75'G, V+ = 9.DV ±1 %, and
V- = -9.DV ±1%. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Static Characteristics
Forward Input Current
Reverse Input Current
Output Voltage High
Output Voltage Low
Test Conditions
V,N =OV
Y'N = 5.0V
Y'N =O.BV, RL =3.0KO,
Y'N = O.BV, RL =3.0KO,
Y'N = 1.9V, RL =3.0KO,
Y'N = 1.9V, RL =3.0KO,
1.0
V+ =9.0V, V- = -9.0V
V+ =13.2V, V- =-13.2V
V+ =9.0V, V- = -9.0V
V+ = 13.2V, V- =-13.2V
Positive Output Short-Circuit Current (Note 3)
Negative Output Short-Circuit Current (Note 3)
Output Resistance (Note 4)
V+ =V- =OV, IVouTI =±2.0V
Positive Supply Current
RL ==
Y'N =O.BV, V+ =9.0V
Y'N = 1.9V, V+ =9.0V
Y'N =O.BV, V+ =12V
Y'N = 1.9V, V+ =12V
Y'N =O.BV, V+ =15V
Y'N = 1.9V, V+ =15V
Negative Supply Current
RL =00
Y'N = O.BV, V- =-9.0V
Y'N =1.9V, V- =-9.0V
Y'N =O.BV, V- =-12V
Y'N =1.9V, V- = -12V
Y'N =O.BV, V- =-15V
Y'N =1.9V, V- =-15V
6 -10
SG14BB
Min. I Typ. I Max.
6.0
9.0
-6.0
-9.0
6.0
-6.0
300
7.0
10.5
-7.0
-10.5
10
-10
4.5
15
5.5
19
-13
-1B
1.6
10
12
-12
I
I
Units
mA
JlA
V
V
V
V
mA
mA
0
6.0
20
7.0
25
12
34
mA
mA
mA
mA
mA
mA
-15
-17
-15
-23
-2.5
mA
mA
mA
mA
mA
mA
SG1488
ELECTRICAL SPECIFICATIONS (continued)
Parameter
I
Test Conditions
Static Characteristics (continued)
Power Dissipation
V+
V+
Dynamic Characteristics (Note 4)
Propagation Delay Time High-Low (TPHL)
Fall Time (TTHL)
Propagation Delay Time Low-High (TPLH)
Rise Time (TTLH)
I Min.
SG1488
Typ. M ax..: Units
=9.0V, V- =-9.0V
=12V, V- = -12V
=3.0KO, C L = 15pF, TA =25°C
=3.0KO, C L = 15pF, TA =25°C
~ =3.0KO, C L = 15pF, TA =25°C
ZL =3.0Ka, C L = 15pF, TA =25°C
150
45
110
55
ZL
ZL
333
576
mW
mW
200
75
175
100
ns
ns
ns
ns
Note 3. Maximum power dissipation may be exceeded if all outputs are shorted simultaneously.
Note 4. These parameters are not tested in production.
TYPICAL APPLICATION
LINE DRIVER
SG1488J
INTERCONNECTING
LINE RECEIVER
SG1489J
CA\E
,-~
,
,.---,
--<
--<
---<
L ___ "J-
})
L ___ "
,
,
,
INTERI
DTL LOGIC INPUT --!---CONNECTING--!--- DTL LOGIC OUTPUT
CABLE
i
i
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
14·PIN CERAMIC DIP
J-PACKAGE
Part No.
SG1488J/8838
SG1488J
Ambient
Temperature Range
O°C to 75°C
O°C to 75°C
Connection Diagram
.V", [f1""Ti4p +v",
P
12p
P
10P
lA [ 2
13
4B
1Y [ 3
4A
2A [ 4
11
4Y
2B [ 5
3B
2Y[6
.p3A
GND [~P 3Y
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898·8121 • TWX: 910·596·1804. FAX: (714) 893·2570
6 - 11
•
SG14891SG1489A
SILICON
GENERAL
•
QUAD RS-232C LINE RECEIVERS
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1489/SG1489A monolithic quad line receivers are designed to
interface data terminal equipment with data communications
equipment in conformance with specifications of EIA Standard
No. RS-232C.
Input resistance 3.DKil to 7.DK!l
Input signal range ±3DV
• Input threshold hysteresis built in
• Response control
• Logic threshold shifting
• Input noise filtering
o
o
HIGH RELIABILITY FEATURES
• SG1489/1489A
• Available to MIL·STD·BB3
• SG level "5" processing available
CIRCUIT SCHEMATIC ('/4 Circuit Shown)
V+
I SG1489AJ I
IRFII SG1489J
10KO
I 2KO I
14
9K
5K
RESPONSE
CONTROL 2
2K
OUTPUT
V ........---{
3
V..A-----l
4K
INPUT
1
I'>t.,
,A
10K
GROUND
L -____~__----~~----~~------~--~
LOGIC DIAGRAM
(IA) 10---/)--03 (IY)
(CONTROL 1) 2
(2A) 4
(CONTROL 2) 5
(3A) 10
(CONTROL 3) 9
a----T
(4A) 13
(CONTROL 4) 12
~6
(4Y)
a----T
(2Y)
V+ - ..0----<0 VCC
a----T
~8
a----T
~11
(3Y)
POSITIVE LOGIC: Y=A
April 1990
6 -13
..,L..r-----o-f----,r---IJ
pF
,"",_~l--'V'''v-.--_+-l_~r.
AC Inpulo-
.~
<;
10%
90%
10r.
500
1~?,
10nSec
3.SV ~ 90%
INPUT
(
"
1
2N2369A
--{>--
e
~
OUTPUT
15V - -
-
-
OUTPUT
ov-~
r;;;90"'X---+->-90X
\
/
10'
t--WHL-
WLH-
-
-
-TTLH
I- TTHL
CHARACTERISTIC CURVES
30
40
"-
c
I
w
30
"
F
z
a
F
~
i"
T A~ 25°C
Freq=200KHz
30
-
g
Duly Cycle = 50"
25
1-_ _-+__
TA" 2SoC
Duty Cycle'" 50"
............ ~TURN-ON DELAY
w
TrLH - RISE TIME
",.
F
g
TTl1L -IFALL TIME
10
20r----r--~~~
____
~~
15~---+---1----I
~f-...
10
15
20
(v)
FIGURE 2.
TRANSITION TIMES VS. SUPPLY VOLTAGE
5
10
15
SUPPLY VOLTAGE -
20
(V)
FIGURE 3.
PROPAGATION DELAY VS. SUPPLY VOLTAGE
6 -19
T-r
"erE: 1960 pF
Freq.200KHz
o L....-L_....1.._...L.._'---L_..J
0
10r--r-L-~~+--+--r~
TpHL - TURN-OFF DELAY
10r----t~----~----_1
SUPPLY VOLTAGE -
I
251--r_+--+_T~~~H-_R,IS_E_n",Er-~
-
Freq = 200KHz
~
I
20
5
f-I-
CL = 1000 pF
CL = 1000 pF
\..
5 -
rot'
+--1--1--1
o L.J.....1.....L..L....i.....l.....L..L....i.....l.....L..L....i...J
-55
-25
25
50
75
AMBIENT TEMPERATURE _
100
(OC)
FIGURE 4.
TRANSITION TIMES VS. AMBIENT TEMPERATURE
125
•
SG16261SG26261SG3626
CHARACTERISTIC CURVES (continued)
100
50
Vee= ,5'0'
g
g
;;:
40
.5.
20
TA" 25DC
Freq = 200KHz
DutyCycle"SO:;
80th Output, Switchinl;!
w
60
>-
!
i
"z
w
">~
80
F
F=
0
F
40
!?1
10
"'
i!:
Vee= 15V
cL. = 1000 pF
Freq = 200KH~
Duty Cycle = 50~
20
o'~~-L~~~~~~~~~
-55
-25
25
50
75
100
AMBIENT TEMPERATURE - (OC)
Vee
15'0'
TA= 250C
D,t Cvele .. 1%
~
V
/
10
100
10000
CAPACITIVE LOAD -
Vee
15'0'
TA.=
Out C Ie =
/~
~
(
OUTPUT CURRENT - (A)
/
25 0 C
,%
70
"'
.§.
/'
0
10K
(A)
CL = 2S00pF
Duty Cycle = 5011:
C'i
80
Channel Crounded
0:
0:
::>
"
i
60
40
20
10K
lOOK
FREQUENCY -
FIGURE ",
SUPPLY CURRENT VS, FREQUENCY
6-20
1M
(Hz)
1M
lOOK
FREQUENCY -
.lnputtoSecond
>-
20
10
TA" 25 0 C
100
30
Ol
140
120
40
'"'"::>
"
~
/
50
z
w
FIGURE 9,
LOW SIDE SATURATION VS, OUTPUT CURRENT
.§.
60
>-
OUTPUT CURRENT -
;;:
10000
(pF)
FIGURE 7,
SUPPLY CURRENT VS. CAPACITANCE LOAD
)'
J
1000
LOAD CAPACITANCE -
(pF)
FIGURE 6,
TRANSITION TIMES VS, CAPACITIVE LOAD
-/'
FIGURES.
HIGH SIDE SATURATION VS, OUTPUT CURRENT
20
0'-----'----'-'-.w..u.u_~__'_~u.Ju.u
1000
125
FIGURE 5,
PROPAGATION DELAY VS, AMBIENT TEMPERATURE
30
FIGURE 10.
SUPPLY CURRENT VS, FREQUENCY
(Hz)
SG1626/SG2626/SG3626
APPLICATION INFORMATION
POWER DISSIPATION
The SG1626, while more energy-efficient than earlier gold-doped
driver IC's, can still dissipate considerable power because of its
high peak current capability at high frequencies. Total power
dissipation in any specific application will be the sum of the DC or
steady-state power dissipation, and the AC dissipation caused by
driving capacitive loads.
The DC power dissipation is given by:
where Icc is a function of the driver state, and hence is duty-cycle
dependent.
The AC power dissipation is proportional to the switching frequency, the load capacitance, and the square of the output
voltage. In most applications, the driver is constantly changing
state, and the AC contribution becomes dominant when the
frequency exceeds 100-200KHz.
tor is an effective combination. For commercial applications, any
low-inductance ceramic disk capacitor teamed with a Sprague
150D or equivalent low ESR capacitor will work well. The capacitors must be located as close as physically possible to the Vcc pin,
with combined lead and pc board trace lengths held to less than
0.5 inches.
GROUNDING CONSIDERATIONS
Since ground is both the reference potential forthe driver logic and
the return path for the high peak output currents of the driver, use
of a low-inductance ground system is essential. A ground plane
is highly recommended for best perforrnance. In dense, high
performance applications a 4-layer pc board works best; the 2
inner planes are dedicated to power and ground distribution, and
signal traces are carried by the outside layers. For cost-sensitive
designs a 2-layer board can be made to work, with one layer
dedicated completely to ground, and the other to power and signal
distribution. A great deal of attention to component layout and
interconnect routing is required for this approach.
LOGIC INTERFACE
The SG1626 driver family is available in a variety of packages to
accommodate a wide range of operating temperatures and power
dissipation requirements. The Absolute Maximums section of the
data sheet includes two graphs to aid the designer in choosing an
appropriate package for his design.
The designer should first determine the actual power dissipation
of the driver by referring to the curves in the data sheet relating
operating current to supply voltage, switching frequency, and
capacitive load. These curves were generated from data taken on
actual devices. The designer can then refer to the Absolute
Maximum Thermal Dissipation curves to choose a package type,
and to determine if heat-sinking is required.
DESIGN EXAMPLE
Given: Two 2500 pF loads must be driven push-pull from a +15
volt supply at 100KHz. This is a commercial application where the
maximum ambient temperature is +50°C, and cost is important.
1. From Figure 11, the average driver current consumption
under these conditions will be 18mA, and the power dissipation
will be 15volts x 18mA, or 270mW.
2. From the Ambient Thermal Characteristic curve, it can be
seen that the M package, which is an 8-pin plastic DIP with a
copper lead frame, has more than enough thermal conductance
from junction to ambient to support operation at an ambient temperature of +50°C. The SG3626M driver would be specified for
this application.
The logic input of the 1626 is designed to accept standard DCcoupled 5 volt logic swings, with no speed-up capacitors required.
"the input signal voltage exceeds 6 volts, the input pin must be
protected against the excessive voltage in the HIGH state. Either
a high speed blocking diode must be used, or a resistive divider
to attenuate the logic swing is necessary.
LAYOUT FOR HIGH SPEED
The SG1626 can generate relatively large voltage excursions with
rise and fall times around 20-30 nanoseconds with light capacitive
loads. A Fourier analysis ofthese time domain signals will indicate
strong energy components at frequencies much higher than the
basic switching frequency. These high frequencies can induce
ringing on an otherwise ideal pulse if sufficient inductance occurs
in the signal path (either the positive signal trace or the ground
return). Overshoot on the rising edge is undesirable because the
excess drive voltage could rupture the gate oxide of a power
MOSFET. Trailing edge undershoot is dangerous because the
negative voltage excursion can forward-bias the parasitic PN
substrate diode of the driver, potentially causing erratic operation
or outright failure.
Ringing can be reduced or eliminated by minimizing signal path
inductance, and by using a damping resistor between the drive
output and the capacitive load. Inductance can be reduced by
keeping trace lengths short, trace widths wide, and by using 20z.
copper if possible. The resistor value for critical damping can be
calculated from:
RD=2~ [2]
SUPPLY BYPASSING
Since the SG1626 can deliver peak currents above 3amps under
some load conditions, adequate supply bypassing is essential for
proper operation. Two capacitors in parallel are recommended to
guarantee low supply impedance over a wide bandwidth: a 0.1 ~F
ceramic disk capacitor for high frequencies, and a 4.7~F solid
tantalum capacitor for energy storage. In military applications, a
CK05 or CK06 ceramic operator with a CSR-13 tantalum capaci-
where L is the total signal line inductance, and CL is the load
capacitance. Values between 10 and 1000hms are usually
sufficient. Inexpensive carbon composition resistors are best
because they have excellent high frequency characteristics.
They should be located as close as possible to the gate terminal
of the power MOSFET.
6 - 21
•
SG1626/SG2626/SG3626
TYPICAL APPLICATIONS
165V
15V
15
• vee
13
11r-~---K--~~~
OUT A
SG3527A
- IN5819
SG3626
14r-~---M--~r--1
IN B
12
GND~--~------~
OUT B
FIGURE 12.
When the SG3626 is driven from a totem-pole source with a peak output greater than 6 volts, a low-current, fast-switching blocking
diode is required at each logic inputfor protection. In this push-pull converter, the inverted logic outputs ofthe 3527A are ideal control
sources for the power driver.
15V
SG3626
11
SG3524B
GND~-----*----~--~--~
FIGURE 13.
In this forward converter circuit, the control capabilities of the SG3524B PWM are combined with the powerful totem-pole drivers
found in the SG3626. This inexpensive configuration results in very fast charge and discharge of the power MOSFET gate
capacitance for efficient swithing.
6-22
SG16261SG26261SG3626
TYPICAL APPLICATIONS (continued)
OUTPUT
115V
AC
Vee !-----t-,
.---1........,4.7,,£ •
OUT A
..-~~+-Ocf--"'N'-I--t--M---t---1 OUT
SG3626
IN5B19
'--...,....-f+-oCf--,,'N'-I--t--M--t--r--1 0UT
OUT B
GND B
FIGURE 14.
In half or full-bridge power supplies, driving the isolation transformers directly from the PWM can cause excessive IC temperatures,
expeciallyabove 100KHz. This circuit uses the high drive capacity of the SG3626 to solve the problem.
15V
---t----------.----_----,
OUTPUT
.----'--_4.7p.F
Vee
VIN
115V
Vc
OUT
SG3626
!--"'-IV',.-.--I
IN
OUT
AC INPUT
SG3847
I--MI'>I'v---ii.,
T
GNO
ERROR SIGNAL
FIGURE 15.
A low-impedance resistive divider network can also be used as the interface between the PWM high-voltage logic output and the
SG3626 power driver. In this 200KHz current mode converter, the SG3847 provides control, while the SG3626 provides high power
drive and minimizes ground spiking in the controllC.
6 - 23
•
SG16261SG26261SG3626
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
14-PIN CERAMIC DIP
J -PACKAGE
8-PIN CERAMIC DIP
V-PACKAGE
Part No_
SG1626JIBB38
SG1626J
SG2626J
SG3626J
SG1626YIBB38
SG1626Y
SG2626Y
SG3626Y
Ambient
Temperature Range
-55°C to
-55°C to
-25°C to
ooe to
-55°e to
-55°e to
-25°C to
OOeto
125°C
125°C
B5°e
70°C
Connection Diagram
N.C. C~::l V'"
N.C. C 2
13::l N.C.
OUTAC3
"::lOUTB
N.C. C 4
11 ::l N.C.
INA C 5
lOp INB
N.C. [ •
• P N.C.
GROUND [L-.B.P N.C.
125°C
125°e
B5°e
70°C
8-PIN PLASTIC DIP
M- PACKAGE
SG2626M
SG3626M
-25°C to B5°e
OOeto 700 e
16-PIN BATWING DIP
W-PACKAGE
SG2626W
SG3626W
-25°C io B5°e
ooe to 70 0 e
N.C. 0 8
INA 2
7
GROUND 3
8
INB 4
5
N.C.
OUT A
V'"
OUTB
N.C. C 1
1. Cl N.C.
15 POUTA
INA[2
N.C. [ 3
14
Vee
GROUND [ 4
13
GROUND
GROUND
5
12
GROUND
N.C. [ ,
11
V"
INB[7
"POUTB
N.C. [-....0.8_ _
• 'CP N.C.
P
P
P
16-PIN WIDE BODV
PLASTIC S.O.I.C.
DW-PACKAGE
SG2626DW
SG3626DW
-25°C to B5°e
OOeto 70°C
1
2
15 ~ OUTA
N.C. IT
3
14 ~ Vee
GROUND
GROUND
N.C.
INB
N.C.
8-PIN TO-99 METAL CAN
T-PACKAGE
SG1626TIBB38
SG1626T
SG2626T
SG3626T
-55°e to
-55°C to
-25°C to
ooe to
125°C
125°e
IT 4
13 ~
IT 5
12 ~
IT ,
11 ~
IT 7
10 ~
IT""""""t.l..::8_ _-,.-,"~-
N.C.
GROUND
GROUND
Vee
OUTB
N.C.
V",
OUTA
B5°e
70°C
18
fIl
N.C. IT
INA IT
1
8
7
N.C. 2
OUTB
,
INA 3
N.C.
5 1NB
4
GND
5-PIN TO-55 METAL CAN
R- PACKAGE
SG1626R/B838
SG1626R
SG2626R
SG3626R
-55°e 10 125°e
-55°e to 125°C
-25°C to B5°e
OOeto 70 0 e
o
V'"
OUTB
INB
0 ®
@\\OUTA
® G:l
o
~NA
CASE IS GROUND
Note: Case and tab are
Internally connected to
substrate ground.
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
6-24
SG1627/SG2627/SG3627
SILICON
GENERAL
DUAL HIGH-CURRENT OUTPUT DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1627 series devices are monolithic, high-speed driver integrated
circuits designed to interface digital control logic with high current loads. Each
device contains two independent drivers which will either source or sink up to
500mA of current. The sink transistor is designed as a saturating switch while
the source transistor can be used either as a switch or as a constant current
generator with external resistor programming.
• Two independent driver circuits
• Outputs will source or sink currents to
500mA
• 300ns response time
• Full compatibility with SG1524 PWM circuit
• Constant current drive capability
• Two volt threshold for high noise Immunity
• Source and sink can be separated for complementary outputs
Each half of this device contains both inverting and non-inverting inputs which
have two volt thresholds for high noise immunity. Either input can be used
alone to switch the output, or one input can be strobed with the other. These
units have been designed to directly interface with the SG1524 Regulating
Pulse Width Modulator Circuit.
These devices are supplied in ceramic 16-pin D.I.L. packages. The SG1627
is specified for operation over a -55°C to +125°C ambient temperature range
while the SG2627 is intended for industrial applications of -25°C to 85°C and
the SG3627 for O°C to 70°C.
HIGH RELIABILITY FEATURES - SG1627
• Available to MIL-STD-883
• SG level "S" processing available
•
SCHEMATIC (one-half of total device shown)
To Side B
To Side B
+vcc
R8
R2
R4
R5
R7
5K
5K
2K
5K
+-1K-1r-_-I:----~-U
~~~~~~or
I~~~i(}---+----r--+--+--~
Non-lnv.
06
Current
H4-<'--------{J Sense/Boost
Input
Sink
01
02
6V
6V
Coli ector
Sink
Emitter
Ground
Substrate
BLOCK DIAGRAM (one-half of total device shown)
C
INV. INPUT
N.I. INPUT
CURRENT
SENSE
GND~
FUNCTION TABLE
NON
INV.
INV.
SINK
SOURCE
LO
OPEN
OPEN
LO
OPEN
LO
OPEN
LO
ON
OFF
ON
ON
OFF
ON
OFF
OFF
See Application Notes for additional information.
April 1990
6-25
SG1627/SG2627/SG3627
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, Vcc
SG1627, 2627 .................................................................. 30V
SG3627 ............................................................................ 20V
Output Collector Voltage
SG1627, 2627 ................................................................. 30V
SG3627 ........................................................................... 20V
Source or Sink Current, DC ............... ;.;00" •••••••••••••••••••••••• 500mA
Peak Current « 2% duty cycle) ............................................. IA
Input Voltage Range .................•........................... -0.3V to 5.5V
Input Current ..................................................................... 10mA
Operating Junction Temperature
Hermetic (J Package) ................................................... 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL DERATING CURVES
2.5
5.01\
2.0
~
~
I
1.5
4.0
~
il
i"
"
~
1.0
~
,
0
25
50
I
~~
'\04
0.5
0
~
75
C
100
~'I>
1.0
"-
125
"""
2.0
i
""
AMBIENT lEMPERATURE -
'\'-
'.0
150
0
175
0
25
50
75
~~
r'\.
100
\
125
150
175
CASE TEIdPERATURE - 'C
'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage, Vcc
SG1627, 2627 ........................................................ 5V to 30V
SG3627 .................................................................. 5V to 20V
Output Collector Voltage
SG1627, 2627 ........................................................ 5V to 30V
SG3627 ..............................................................:.. 5Vto 20V
Source or Sink Current, DC ............................... OmA to 500mA
Note 2. Range over which the device is functional.
Peak Current «2% duty cycle) .......................... OmA to 750mA
Input Voltage ....................•........................................ OV to 5.5V
Input Current ........................................................ OmA to 10mA
Operating Ambient Temperature Range
SGI627........................................................... -55°C to 125°C
SG2627 ........................................................... -25°C to 85°C
SG3627 ............................................................... O°C to 70°C
ELECTRICAL SPECIFICATIONS
. (Unless otherwise specified, these specfiications apply over the operating ambient temperatures for SG1627 with -55°C ST. S125°C, SG2627 with ·25°C
ST. S85°C, SG3627 with DoC ST. S70°C, and Vee = 5V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures
equal to the ambient temperature.)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Input Threshold
Low-Level Input Current
Source Off, Leakage Current
Source On, Collector Saturation
(Source Emitter Grounded, Rsc = 0)
Source On, Emitter Voltage
Sink Off, Leakage Current
Sink On, Collector Saturation
Current Limit Sense Voltage
Sense Voltage Temperature Coefficient
Test Conditions
VIN=OV
Collector V = VMAX
ISOURCE = 50mA
ISOURCE = 300mA
ISOURCE =500mA
ISOURCE =-50mA
Collector V =VMAX
ISINK = 50mA
ISINK =300mA, Vcc =20V
ISINK = 500mA, IBOOST = 25mA
Rsc = lOn, TA =25°C
Rsc = Ion
6-26
SG1627/2627/3627
Min. Typ. Max.
2.8
5.5
1.4
0
2.0
-1.0 -2.0
0.3
1.0
1.1
1.7
1.2
1.9
1.3
Vcc·3V
600
1.0
0.2
0.5
0.5
700
1.8
100
0.4
0.7
900
Units
V
V
V
mA
mA
V
V
V
V
!LA
V
V
V
mV
mVrC
SG16271SG26271SG3627
ELECTRICAL SPECIFICATIONS (continued)
SG1627/2627/3627
Units
Min. Typ. Max.
15
22
rnA
50
73
rnA
80
115
rnA
ns
100
ns
300
Test Conditions
Parameter
Supply Current (both sink transistors on)
Response Time (TRHL)
Response Time (TRLH)
Vcc =5V
Vee = 20V
Vee = 30V (1627/2627 only)
Fig. 12, RL = 240 TA = 25°C
Fig. 12, RL = 240 TA = 25°C
CHARACTERISTIC CURVES
I
100
4
so~rc~
Vee = 5V
>
,
0
~
iE
E
CURRENTS = SOmA
2
-
INPUT
INVERTING
INPUT
50
100
3.5
w
2.5
"~
§:
I
VhfT
TJ = 125°C
vee -\/
F
1.5
~
1.0
100
200
COLLECTOR CURRENT -
1.0
"~
'Oo
60
>~
""-
......;.
1
a
~
a
NON-INlRTIG
.l~
T,."oC
r
.:::::: :::::: ~
3.5
Sl~k ccneolor
80
,
3
r
~
r
10
0.0
II
A
~
6- 0.5V
1
200 ns/divisian
FIGURE B. OUTPUT WAVEFORM
FIGURE 7· TOTEM POLE OUTPUT SWITCH CIRCUIT
6 - 27
-
SG16271SG26271SG3627
APPLICATION CIRCUITS
FIGURE 9
FIGURE 10
Basic 300mA switched drive circuit. II the external output transistor is to
be on when the driving transistor is on, use the inverting input with the noninverting input left open. For opposite phasing, use the non-inverting input
with the inverting input grounded.
Use 01 higher input voltage provides greater drive lor higher sink-transistor
peak current while R2 provides constant source current. R1 helps
minimize power in the SG1627. Although the sink emitter may be
connected to a different ground point Irom pin 5, any voltage differences
between them will directly affect the input threshold level.
Vee
=
+sv
R1
RL
1/2 SG1627r--<>-.j-'O_0-,O SOURCE
RL
SINK
FIGURE 11
FIGURE 12
Additional source current or power handling capability may be added with
the use 01 an external PNP transistor. For optimum performance, a low
storage-time unit should be selected. II current limiting is not required, an
NPN emitter lollower could also be used lor source boost.
Source and sink transistors can be used separately lor complementary
outputs. At low supply voltages the sink current is limited to approximately
100mA, but il current limiting is not required a sink drive boost may be
added with R1. The current in R1 should be .05 times the sink load current
to insure saturation.
+vrN
-!=::::::;:j::::::;:;::=!-__~
1/2 SGI627'r-~~_ _
Other
Helf
SG1627
R,
100
To
NI
Input
FIGURE 14
FIGURE 13
Source and sink transistors can be used separately lor an efficient translonmer driver. Here the source provides constant current drive with
magnetic reset accomplished by a Ilux clamp utilizing the sink transistor.
With the source current sense terminal connected to ground, there will be
a residual collector current 01 approximately 3001iA. II this is objectionable, insert a diode between current sense and ground.
Simultaneous conduction 01 the output switching transistors can be positively prevented by using diodes to cross-couple a gating signal into the
non-inverting inputs. For maximum power handling capability, the source
transistor is driven into saturation with the current limiting provided by R1.
6 - 28
SG1627/SG2627 /SG3627
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
16·PIN CERAMIC DIP
J - PACKAGE
Part No.
SG1627J/883B
SG1627J
SG2627J
SG3627J
Ambient
Temperature Range
·55°C to
-55°C to
-25°C to
DOC to
125°C
125°C
85°C
7DoC
Connection Diagram
SINK C (A) [[1"716]
SINK E (A) [ 2
INV. (A) [ 3
N.I.(A) [ 4
GROUND [ 5
N.I. (6) [6
CURRENT SENSE (A)
" J SOURCE E (A)
14 ]
SOURCE C (A)
13:J
12 ]
11 ]
Vee
INV. (6)
SOURCE C (6)
SINK E (6)
[7
SINK C (6)
~]
10 ]
SOURCE E (6)
CURRENT SENSE (6)
II
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
6 - 29
6 - 30
SG16291SG3629
SILICON
GENERAL
HIGH-CURRENT FLOATING SWITCH DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1629 and SG3629 are monolithic integrated circuits designed to
generate the positive and negative base drive currents (ib1 and ib2) required
for high-speed, high power switching transistors. These units are intended to
interface between the secondary of a drive transformer and the base of an
NPN switching device. Positive drive current can be made constant with an
external programming resistor, or can be clamped with a diode to keep the
switching device out of saturation. Negative turn-off current is derived from
a negative voltage generated in an external capacitor. All operating power is
supplied by the transformer secondary and these devices can be floated at
high levels with respect to ground for off-line, bridge converters.
• Self-generating positive and negative
currents
• Constant source current (I B,) to one amp
• Two amp peak sink current (I B2) to negative
voltage
• Floating operation
• Baker clamp input for non-saturated
switching
• Provisions for source and sink gating
• 100ns response
For medium power applications, these units are available in 1O-pin, TO-1 00
package; while high power capability is offered in a 9-pin, TO-66 case. In
either package, the SG1629 is specified for operation over an ambient
temperature range of -55'C to 125'C while the SG3629 is intended for
industrial applications of 0 to 70'C.
HIGH RELIABILITY FEATURES - SG1629
~ Available to MIL-STD-883
• SG level "5" processing available
SCHEMATIC
D3
+VIN
SOURCE
EMITTER
Q4
R2
1K
D1
SOURCE
CLAMP
CURRENT
SENSE
SINK
DRIVE
SINK
GATE
SINK
COLLECTOR
0R1
10K
Q1
D2
SINK
EMITTER
-VIN
SUBSTRATE
& CASE
See Application Notes for additional information.
April 1990
6 -31
•
SG16291SG3629
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage (+V,N or -V,N ) .................................................. 20V
Collector to Emitter Voltage, Source or Sink ....................... 20V
Source Current ................................................................... 2.0A
Sink Current ....................................................................... 3.OA
Sink Rectifier Current (peak) .............................................. 2.0A
Operating Junction Temperature
Hermetic (T, R Packages) ............................................ 150°C
Storage Temperature Range ............................ -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL DERATING CURVES
5.0
50
4.0
40
S
~
,
3.0
is
~
iii
Ci
i
2.0
"
E
~
,
"~
10~
N.
0
~
:'< ~'b
25
50
75
30,",
10
C~"')
100
AMBIENT TEMPERATURE -
125
150
0
175
"-
20
~
rr~ ~
AttTAL
0
~
-
0
~
~""('I':
.<~
T_(lO-PIN
I
25
"c
50
META~
CAN
75
'"
100
.........
125
150
175
CASE TEMPERATURE - "C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage (+V,N or -V ,N ) .................................................. 15V
Collector to Emitter Voltage, Source or Sink ....................... 15V
Source Current ............................................................. OA to 1A
Sink Current ................................................................. OA to 2A
Sink Rectifier Current (Peak) ....................................... OA to 1A
Operating Ambient Temperature Range
SG1629 .......................................................... -55°C to 125°C
SG3629 ............................................................... O°C to 70°C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specfiications apply over the operating ambient temperatures for SG1629 with -55°C S T. S 125°C, SG3629 with O°C
S TA S 70°C. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Test Conditions
Collector to Emitter Voltage, Source or Sink
Collector to Emitter Leakage, Source or Sink
input Leakage V+ to VInput Leakage V- to V+
Standby Current from Sink Emitter Voltage (Note 3)
Clamp Current
Source Saturation Voltage
VSE=O
VSE = 0, VCE = 15V
Input Voltage =+15V
Input Voltage = -15V
Sink Emitter =-5V, +V'N =-V'N =OV
+V'N = 15V, V clamp = OV
ISOURCE =100mA
ISOURCE = 500mA
ISOURCE = 1A, TA =25°C
Sink Saturation Voltage, Force beta = 100
ISINK = 100mA
ISINK =500mA
ISINK = 1A, TA = 25°C
Sink Current Gain
ISINK = 2A, VCE =3V
Current Limit Sense Voltage
Rsc = 0.7n, TA = 25°C
Sink Rectifier Forward Voltage
IF = 1A. TA =25°C
Sink Gate Output Saturation
Sink Drive = 10mA, Sink Gate liN = 1mA
Source Response
ISOURCE =1A
Sink Response
ISINK = 1A
Note 3. 1KQ from -V'N to Sink Drive and Source Emitter connected to Sink Collector.
6 - 32
SG1629/SG3629
Min. Typ. Max.
20
30
5
100
1
100
2
4
5
10
10
15
20
1.7
1.8
2.0
3
1.2
1.3
1.5
2
300 500
0.55 0.65 0.80
1.0 2.0
0.2
0.4
100
100
Units
V
!1A
!1A
mA
mA
mA
V
V
V
V
V
V
V
V
V
ns
ns
SG16291SG3629
CHARACTERISTIC CURVES
4.0
4.0
>
>
RSC ~ Or!
1
"~
TJ - -5SoC
20
~
f2
c:l
w
30
§;
z
a
FORCE
k'::"
TJ
Ir~
"~
30
TJ=~Y V-
z
a
20
08
12
1.6
~
/
9-
1.0
V-
~ F-"
:;;..r'
TJ
t
TJ -
0
08
12
SINK CURRENT -
1.6
/
~
10V
~
5V
=>
~ ,./'
~
----
~
+lDY
0
0
0.2
0.4
0.6
FORWARD CURRENT -
0.8
II
1K
VIN0--
Ir
.5A
SG1629
,
,
¢l d
9
'SC
O.7n
7
9J~IOUT
5
Your
4
RS
51n
1\
\
A
,
6~
"
II
OA
1.0
J
50mfdI
CI
lA
15
12
V
FIGURE 3.
CONSTANT SOURCE CURRENT
OV
=>
52
9
SOURCE VOLTAGE -
02
1.0
6
3
A
3.0
2.0
J
0
OV
";0
250C
0.5
2.0
5V
z
:>
=1
TJ =1'2S oC
=>
-5SoC
FIGURE 2.
SINK SATURATION
1
TJ
rr
TJ"T'C
0.4
A
25 C
r
1.0
w
u
:;:'"
O~
TJ .. -5SoC
0
20
4.0
>
e
~
RSC=
1.5
0
0.4
FIGURE 1.
SOURCE SATURATION
"'"
1
~
c:l
SOURCE CURRENT -
~
"'
TJ = 25°C
f2
10
0
1
100
§;
2SoiC
0
w
2.0
t, -
1
•
7
200ns/Dlvlsion
FIGURE 4.
RECTIFIER FORWARD VOLTAGE
FIGURE 5.
DYNAMIC RESPONSE WAVEFORM
FIGURE 6.
DYNAMIC RESPONSE TEST CIRCUIT
APPLICATION CIRCUITS
ANTI-SATURA TlON CLAMP
SG1629
¢l j
,OT
'OT
6~IVER ~
20T
"2K
+10V
20T
TO
DRIVER
CORE
2213P 3C8
EI
~
Some SG1629 cirCUit
osobove
01
+vs
yJ
SG1629
'cs
10n
"-- a 7A
2.0A
2"-16583
I
~
+ Cs
20,.,'OV
-§
II
Load
(
-=R8
2N6583
-K
~
R
Cs
=1=
7
FIGURE 7
FIGURE 6
Two SG1629 devices can be combined to form the drive signals for the
power transistors in a 5A, half-bridge switching supply.
A load-dependent drive current may be provided by eliminating the current
sensing resistor and adding the anti-saturation clamp diode D1.
6 - 33
SG16291SG3629
APPLICATION CIRCUITS (continued)
FIGURES
FIGURE 9
Where transformer inductance would normally degrade turn-on current
rise time. the use of the sink gate with a relatively slow external transistor.
Ql. will delay the sink turn-off until after source current has been
A simplified drive system for a half-bridge switched mode converter. A full
bridge drive may be accommodated with four SG1629 drivers and additional current boosting for the SG1627.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
9-PIN METAL CAN
R- PACKAGE
Part No_
SG1629R1883B
SG1629R
SG3629R
Ambient
Temperature Range
Connection Diagram
-55°C to 125°C
-55°C to 125°C
DoC to 70°C
CURRENT SENSE
SOURCE CLAMP
SOURCE EMMITER
10-PIN METAL CAN
T-PACKAGE
SG1629T/883B
SG1629T
SG3629T
-55°C to 125°C
-55°C to 125°C
DoC to 70°C
SINK EMMITER
SINK DRIVE
7
,
-VIN
+VIN
N.C.
.v. lOGIC
7
OND
1
-----
1SV - - - -
OUTPUT
1\
-J"
I~
'0'
ov--'
r
SG1644
+11
90'
INPUT
90:;
90.
1\
/
OUTPUT
ov
'0'
TPLH-
-
-
I-- TTLH
~
I-
TPHL-
-
TTHL
7
CHARACTERISTIC CURVES
50
60
CL'" 1000 pI"
TA.~
I
w
"z
40
30
~
0
""
~
TTHL
20
TTLH
-=-
-
FALL TIME
40
w
"
~
F
20
~
c
I
Tpu<
ruL-OFF DELAY
TURN-ON DELAY
10
5
10
20
'5
SUPPLY VOLTAGE -
(v)
FIGURE 2.
TRANS'TION TIMES VS. SUPPLY VOLTAGE
0
I
5
'0
(V)
FIGURE 3.
PROPAGATION DELAY VS. SUPPLY VOLTAGE
6- 37
"
F
fALL TIME
5
-
'5
F
"~
"
10
Vee: ~~~DPF'
f'req"2DOKHz
5 I - Du1 yCycle"'SO%
o
20
'5
SUPPLY VOLTAGE -
TTHL -
20
w
---r- TpHL -
r!H- JE TlMEI
25
-
freq" 200KHz
Duty Cycle = 50%
"-
30
>-
CL" 1000 pI"
T ,,_ 2SOC
.\
I
RISE TIME
'0
0
50
-;;;-
I
~
F
F
25°C
Freq=20QKHzDuty Cycle = 50%
30
~
-55 -25
I 25I
0
50
75
'00 '25
AMBIENT TEMPERATURE - (OC)
FIGURE 4.
TRANSITION TIMES VS. AMBIENT TEMPERATURE
•
SG1644/SG2644/SG3644
CHARACTERISTIC CURVES (continued)
50
]
0
40 r---.=.~~~t--------f--1
40
40
w
""i5
"iii
w
"">-
g
20
20
20 r----------+~~------~
10
10~~~~--~--------_i
g
T PLH - TURN-ON
o L....l.-l..-'-L....l.-l..-'-L....l.-l...J....JL....l....J
-55
-25
25
50
75
AMBIENT TEMPERATURE -
100
1000
125
CAPACITIVE LOAD -
(DC)
FIGURES.
PROPAGATION DELAY VS. AMBIENT TEMPERATURE
r-----------t------#----4
30
30
10000
1000
(pF)
10000
LOAD CAPACITANCE -
FIGURE 6.
TRANSITION TIMES VS. CAPACITIVE LOAD
(pF)
FIGURE 7.
SUPPLY CURRENT VS. CAPACITANCE LOAD
70
VCC" 15V
TA= 25°C
Out
Cycle = ,,,;
/
-/
V
VCC .. I'5V
/-
TA'" 25°C
Duty Cycle = ,,.
V
/
60
';(
S
>-
/
/
V
/
/
z
w
50
40
go
~
=>
30
~
20
"
10
0
10K
OUTPUT CURRENT - (A)
OUTPUT CURRENT - (A)
FIGURES.
HIGH SIDE SATURATION VS. OUTPUT CURRENT
FIGURE 9.
LOW SIDE SATURATION VS. OUTPUT CURRENT
70
60
';(
.E>-
~
"=>
"
~
50
40
30
20
iil
10
0
10K
lOOK
FREQUENCY - (Hz)
FIGURE 11.
SUPPLY CURRENT VS. FREQUENCY
6-38
1M
1M
lOOK
FREQUENCY -
FIGURE 10.
SUPPLY CURRENT VS. FREQUENCY
(Hz)
SG16441SG26441SG3644
APPLICATION INFORMATION
The SG1644, while more energy-efficient than earlier gold-doped
driver IC's, can still dissipate considerable power because of its
high peak current capability at high frequencies. Total power
dissipation in any specific application will be the sum of the DC or
steady-state power dissipation, and the AC dissipation caused by
driving capacitive loads.
POWER DISSIPATION
tantalum capacitor for energy storage. In military applications, a
CK05 or CK06 ceramic operator with a CSR-13 tantalum capacitor is an effective combination. For commercial applications, any
low-inductance ceramic disk capacitor teamed with a Sprague
150D or equivalent low ESR capacitor will work well. The
capacitors must be located as close as physically possible to the
Vcc pin, with combined lead and pc board trace lengths held to
less than 0.5 inches.
The DC power dissipation is given by:
GROUNDING CONSIDERATIONS
where Icc is a function of the driver state, and hence is duty-cycle
dependent.
The AC power dissipation is proportional to the switching frequency, the load capacitance, and the square of the output
voltage. In most applications, the driver is constantly changing
state, and the AC contribution becomes dominant when the
frequency exceeds 100-200KHz.
The ability of the SG1644 to deliver high peak currents into
capacitive loads can cause undesirable negative transients on the
logic and power grounds. To avoid this, a low inductance ground
path should be considered for each output to return the high peak
currents back to it's own ground point. A ground plane is recommended for best performance. If space for a ground plane is not
available, make the paths as short and as wide as possible. The
logic ground can be returned to the supply bypass capacitor and
be connected at one point to the power grounds.
LOGIC INTERFACE
The SG1644 driver family is available in a variety of packages to
accommodate a wide range of operating temperatures and power
dissipation requirements. The Absolute Maximums section of the
data sheet includes two graphs to aid the designer in choosing an
appropriate package for his design.
.
The designer should first determine the actual power dissipation
of the driver by referring to the curves in the data sheet relating
operating current to supply voltage, switching frequency, and
capacitive load. These curves were generated from data taken on
actual devices. The designer can then refer to the Absolute
Maximum Thermal Dissipation curves to choose a package type,
and to determine if heat-sinking is required.
DESIGN EXAMPLE
Given: Two 2500pF loads mustbe driven push-pull from a +15volt
supply at 100KHz. The application is a commercial one in which
the maximum ambient temperature is +50°C, and cost is important.
1. From Figure 11, the average driver current consumption
under these conditions will be 1BmA, and the power dissipation
will be 15volts x 1BmA, or 270mW.
2. From the ambient thermal characteristic curve, it can be seen
that the M package, which is an B-pin plastic DIP with a copper
lead frame, has more than enough thermal conductance from
junction to ambient to support operation at an ambient temperature of +50°C. The SG36446M driver would be specified for this
application.
SUPPLY BYPASSING
Since the SG1644 can deliver peak currents above 3amps under
some load conditions, adequate supply bypassing is essential for
proper operation. Two capacitors in parallel are recommended to
guarantee low supply impedance over a wide bandwidth: a 0.11lF
ceramic disk capacitor for high frequencies, and a 4.71lF solid
The logic input of the 1644 is designed to accept standard DCcoupled 5 volt logic swings, with no speed-up capacitors required.
If the input signal voltage exceeds 6 volts, the input pin must be
protected againstthe excessive voltage in the HIGH state. Either
a high speed blocking diode must be used, or a resistive divider
to attenuate the logic swing is necessary.
LAYOUT FOR HIGH SPEED
The SG1644 can generate relatively large voltage excursions with
rise and fall times around 20-30 nanoseconds with light capacitive
loads. A Fourier analysis ofthese time domain signals will indicate
strong energy components at frequencies much higher than the
basic switching frequency. These high frequencies can induce
ringing on an otherwise ideal pulse if sufficient inductance occurs
in the signal path (either the positive signal trace or the ground
return). Overshoot on the rising edge is undesirable
because
the excess drive voltage could rupture the gate oxide of a power
MOSFET. Trailing edge undershoot is dangerous because the
negative voltage excursion can forward-bias the parasitic PN
substrate diode of the driver, potentially causing erratic operation
or outright failure.
Ringing can be reduced or eliminated by minimizing signal path
inductance, and by using a damping resistor between the drive
output and the capacitive load. Inductance can be reduced by
keeping trace lengths short, trace widths wide, and by using 20z.
copper if possible. The resistor value for critical damping can be
calculated from:
Ro = 2,roc;. [2]
where L is the total signal line inductance, and CL is the load
capacitance. Values between 10 and 1000hms are usually sufficient. Inexpensive carbon composition resistors are best because they have excellent high frequency characteristics. They
should be located as close as possible to the gate terminal of the
power MOSFET.
6 - 39
SG16441SG26441SG3644
TYPICAL APPLICATIONS
15V
Vce
SG1644
OUT A
SG1524B
GND B
OUT A
GND
GND B
I
LOGIC
I
GND
I
FIGURE 12.
In this push pull converter circuit, the control capailities of the SG1524B PWM are combined with the powerful totem·pole drivers
found in the SG1644 (see SG1626 for example). This inexpensive configuration results in very fast charge and discharge of the
power MOSFET gate capacitance for efficient switching.
15V
Vee
SG1644
VIN
IN A
SG
1525A
-:
OR
IN B
15268
-:
LOGIC
LTD FET #1
LTD FET #2
LTD FET #3
LTD FET #4
GND
GND
-=-
-=-
FIGURE 13.
When the peak current capabilites of PWM's such as 1525A or 15268 are not sufficient to drive high capacitive loads fast enough,SG1644 is one solution to this problem. This combination is especially suited for full bridge applications where high input
capacitance MOSFETs are being used. Diodes 01 and 02 are necessary if the leakage inductance of the drive transformer will
drive the output pins negative.
6·40
SG16441SG26441SG3644
TYPICAL APPLICATIONS (continued)
15V
1/2
Vee
SG1644
FIGURE 14.
A low cost, yet powerful alternative to the single ended converters with parallel MOSFETs is a combination of SG1842 and SG1644
as shown in Figure 16. This combination will also allow a low noise operation by separating the drive and its associated high peak
currents, away from the PWM logic section.
.--c:--I---_- v cc
+
1/2
Vee
SG1644
p
+
IN A
.--v--,C",c-+-_ v cc
OUT
LOGIC
A
+ 1--~----l
~
fe,,obr-
'.Q
C'C)
'.ot71'
~
~l..t
~
-<~
,.
''t)
'1J
e
"
~c1'
Yo:
<
it
""q"~4
S'~C'
20
'"
O~~~
10
O;~
~
r~0
0
0
25
50
75
100
12.
150
0
17.
0
25
50
75
100
~
125
150
17.
AMBIENT TEMPERATURE - "C
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Output Voltage, VCE
SG2000, SG2020 series .................................................. 50V
SG2010 series ................................................................. 95V
Note 2. Range over which the device is functional.
Peak Collector Current, Ic
SG2000, SG2020 series ............................................. 350mA
SG2010 series ............................................................ 500mA
Operating Ambient Temperature Range
SG2000 Series - Hermetic ............................. -55°C to 125°C
SG2000 Series - Plastic ...................................... DoC to 70°C
SELECTION GUIDE
Device
SG2001
Vce Max
50V
Ic Max
500mA
SG2002
SG2003
SG2004
SG2005
SG2011
50V
50V
50V
50V
50V
500mA
500mA
500mA
500mA
600mA
SG2012
50V
600mA
Logic Inputs
General Purpose
PMOS,CMOS
14V-25V PMOS
5VTIL,CMOS
6V-15V CMOS, PMOS
High Output TIL
General Purpose
PMOS, CMOS
14V-25V PMOS
6-44
Device
SG2013
SG2014
SG2015
SG2021
VCE Max
50V
50V
50V
95V
IcMax
600mA
600mA
600mA
500mA
SG2022
SG2023
SG2024
95V
95V
95V
500mA
500mA
500mA
Logic Inputs
5VTIL,CMOS
6V-15VCMOS, PMOS
High Output TIL
General Purpose
PMOS,CMOS
14V-25V PMOS
5VTIL,CMOS
6V-15V CMOS, PMOS
SG2000 SERIES
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply overthe operating ambient temperatures for SG2000 series - Hermetic -with -55°e,;; TA ,;; 125°e
and SG2000 series - Plastic - with ooe,;; TA ,;; 70 oe. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures
equal to the ambient temperature.)
SG2001 thru SG2005
Parameter
Output Leakage Current (lCEX)
Collector - Emitter (VeE(5'1)}
Input Current (IIN(ON))
(I'N(OF3)
Input Voltage (V'N(ON)
Applicable
Devices
All
SG2002
SG2004
All
T.=TMIN
TA=TMIN
T. = TMIN
TA = 25°C
TA = 25°C
TA = 25°C
T. = TMAX
TA=TMAX
TA=TMAX
SG2002
SG2003
SG2004
SG2005
All
SG2002
SG2003
SG2004
SG2005
D-C Forward Current
Transfer Ratio (h FE)
Input Capacitance (C,N) (Note 3)
Turn-On Delay (TPLH)
Turn-Off Delay (TPHL)
Clamp Diode Leakage Current (I R)
Clamp Diode Forward Voltage (VF)
Temp.
SG2001
All
All
All
All
All
Test Conditions
VeE = 50V
VCE = 50V, V,N = 6V
VeE = 50V, V,N = 1V
Ie = 350mA, Is = 85011A
Ie = 200mA, Is = 55011A
Ie = 100mA, Is = 35011A
Ie = 350mA, Is = 50011A
Ie = 200mA, Is = 35011A
Ie = 100mA, Is = 25011A
Ie = 350mA, I. = 50011A
Ie = 200mA, Is = 35011A
Ie = 100mA, Is = 250JlA
V,N = 17V
V,N = 3.85V
V,N = 5V
V,N = 12V
VIN = 3V
Ie = 500JlA
VeE = 2V,Ie = 300mA
VeE = 2V, Ie = 300mA
VeE = 2V, Ie = 200mA
VCE = 2V, Ic = 250mA
VeE = 2V, Ie = 300mA
VCE = 2V, Ic = 200mA
VeE = 2V,Ie = 250mA
VeE = 2V, Ie = 300mA
VeE = 2V, Ie = 125mA
VeE = 2V, Ie = 200mA
VeE = 2V, Ie = 275mA
VCE = 2V, Ic = 350mA
VCE = 2V,Ie = 125mA
VCE = 2V, Ie = 200mA
VeE = 2V,Ic = 275mA
VeE = 2V, Ie = 350mA
VCE = 2V, Ie = 350mA
VeE = 2V, Ie = 350mA
VeE = 2V, Ie = 350mA
VCE = 2V, Ic = 350mA
T.=TMAX
TA=TMIN
TA=TMAX
T.=TMIN
TA = TMIN
TA=TMIN
TA=TMAX
TA=TMAX
TA=TMAX
TA=TMIN
T. =TMIN
TA=TMIN
TA = TMIN
TA=TMAX
TA=TMAX
T.=TMAX
T.=TMAX
TA = TMIN
T.=TMAX
TA=TMIN
TA = 25°C
TA = 25°C
TA = 25°C 0.5 E'N to 0.5 EOUT
TA = 25°C 0.5 E'N to 0.5 EaUT
VR = 50V
IF = 350mA
Note 3. These parameters, although guaranteed, are not tested in production.
6 - 45
Limits
Units
Min. Typ. Max.
100 IIA
500 IIA
500 IIA
V
1.6 1.8
V
1.3 1.5
V
1.1 1.3
V
1.25 1.6
V
1.1 1.3
V
0.9 1.1
V
1.6 1.8
V
1.3 1.5
V
1.1 1.3
480 850 1300 IIA
650 930 1350 JlA
240 350 500 IIA
650 1000 1450 JlA
1180 1500 2400 IIA
25
50
JlA
18
V
13
V
3.3
V
3.6
V
3.9
V
2.4
V
2.7
V
V
3.0
6.0
V
V
8.0
10
V
V
12
5.0
V
V
6.0
7.0
V
V
8.0
V
3.0
2.4
V
500
1000
pF
15 25
250 1000 ns
250 1000 ns
50
IIA
V
1.7 2.0
•
SG2000 SERIES
ELECTRICAL SPECIFICATIONS (continued)
SG2011 thru SG2015
Parameter
Output Leakage Current (I CEX)
Collector ~ Emitter (VCE(SAT))
Input Current (I'N(ON))
(I'N(OFF\)
Input Voltage (V'N(ON)
Applicable
Devices
All
SG2012
SG2014
All
TA =TMIN
TA=TMIN
TA =TMIN
TA = 2SoC
TA = 2SoC
TA = 2SoC
TA=TMAX
TA=TMA)(
TA = TMAX
SG2012
SG2013
SG2014
SG201S
All
SG2012
SG2013
SG2014
SG2015
D-C Forward Current
Transfer Ratio (h FE )
Input Capacitance (C,N ) (Note 3)
Turn-On Delay (TPLH)
Turn-Off Delay (TPHL)
Clamp Diode Leakage Current (IRl
Clamp Diode Forward Voltage (VF)
Temp.
SG2011
All
All
All
All
All
Test Conditions
VCE = SOV
VCE = SOY, Y'N = 6V
VCE = SOY, Y'N = 1V
Ic = SOOmA, 18 = 11 OOIlA
Ic = 3S0mA, 18 = 8S011A
Ic = 200mA, 18 = SSOIlA
Ic = SOOmA, 18 = 60011A
Ic = 3S0mA, 18 = SOOIlA
Ie = 200m A, 18 = 3S0llA
Ic = SOOmA, 18 = 600llA
Ic = 3S0mA, 18 = SOOIlA
Ic = 200mA, 18 = 3S0llA
V'N = 17V
Y'N = 3.8SV
Y'N = SV
Y'N = 12V
Y'N =3V
Ic = 500llA
VCE = 2V, Ic = SOOmA
VCE = 2V, Ic = 500mA
VCE = 2V, Ic = 2S0mA
VCE = 2V, Ic = 300mA
VCE = 2V, Ic =SOOmA
VCE = 2V, Ic = 2S0mA
VCE =2V, Ic = 300mA
VCE = 2V, Ic = SOOmA
VCE 2V, Ie = 27SmA
VCE = 2V, Ic = 350mA
VCE 2V, Ie = SOOmA
VCE = 2V, Ic = 27SmA
VCE = 2V, Ic = 3S0mA
VCE = 2V, Ic = SOOmA
VCE = 2V, Ic = 3S0mA
VeE = 2V, Ic = 500mA
VeE = 2V, Ic = 3!iOmA
VCE = 2V, Ic = SOOmA
VCE = 2V, Ie = SOOmA
VCE = 2V, Ic = 500mA
TA=TMAX
TA=TMIN
TA=TMAX
TA =TM'N
TA = TMIN
TA=TMIN
TA = TMAX
TA=TMA)(
TA=TMA)(
TA = TMIN
TA =TMIN
TA=TM'N
TA=TMA)(
TA=TMA)(
TA = TMAX
TA = TMIN
TA =TMIN
TA=TMAx
TA=TMAX
TA = TM'N
TA = 25°C
TA = 2SoC
TA = 25°C O.S E'N to O.S EOUT
TA = 25°C O.S E'N to O.S EOUT
VR= SOV
IF = 3S0mA
IF = SOOmA
=
=
Note 3. These parameters, although guaranteed, are not tested in production.
6 - 46
Limits
Min. Typ. Max.
100
SOO
500
1.8 2.1
1.6 1.8
1.3 1.S
1.7 1.9
1.25 1.6
1.1 1.3
1.8 2.1
1.6 1.8
1.3 1.5
480 8S0 1300
650 930 1350
240 3S0 SOO
6S0 1000 14S0
1180 lS00 2400
2S
50
23.S
17
3.6
3.9
6.0
2.7
3.0
3.5
10
12
17
7.0
8.0
9.S
3.0
3.S
2.4
2.6
4S0
900
25
lS
250 1000
2S0 1000
50
1.7 2.0
2.S
Units
IIA
IlA
IIA
V
V
V
V
V
V
V
V
V
IlA
IlA
IIA
IlA
IIA
IlA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
pF
ns
ns
IlA
V
V
SG2000 SERIES
ELECTRICAL SPECIFICATIONS (continued)
SG2021 thru SG2025
Parameter
Output Leakage Current (lCEX)
Collector - Emitter (VCEISAT))
Input Current (I'NION»)
(I'NIOFFI)
Input Voltage (V'N(ON)
Applicable
Devices
All
SG2022
SG2024
All
TA = TMIN
TA = TM'N
TA = TM'N
TA = 25°C
TA = 25°C
TA = 25°C
TA=TMAX
TA=TMAX
TA=TMAX
SG2022
SG2023
SG2024
SG2025
All
SG2022
SG2023
SG2024
SG2025
D-C Forward Current
Transfer Ratio (h FE )
Input Capacitance (C'N) (Note 3)
Turn-On Delay (TPLH)
Turn-Off Delay (TPHL)
Clamp Diode Leakage Current (I R)
Clamp Diode Forward Voltage (V F)
Temp.
SG2021
All
All
All
All
All
Test Conditions
VCE = 95V
VCE = 95V, VIN = 6V
VCE = 95V, V'N = 1V
Ic = 350mA, 16 = 850J.lA
Ic = 200mA, 16 = 550J.lA
Ic = 100mA, 16 = 350llA
Ic = 350mA, 16 = 500J.lA
Ic = 200mA, 16 = 350llA
Ic = 100mA, la = 250J.lA
Ie = 350mA, 16 = 500J.lA
Ic = 200mA, 16 = 350J.lA
Ic = 100mA, 16 = 250J.lA
V'N= 17V
V'N= 3.85V
VIN = 5V
VIN = 12V
V'N=3V
Ic= 5OOIlA
VOE = 2V,Io = 300mA
VCE = 2V, Ic = 300mA
VCE = 2V, 10 = 200mA
VOE = 2V, Ic = 250mA
VeE = 2V, Ie = 300mA
VeE = 2V, Ic = 200mA
VCE = 2V, Ic = 250mA
VCE = 2V, Ic = 300mA
VCE = 2V, Ie = 125mA
VCE = 2V, Ie = 200mA
VeE = 2V, Ic = 275mA
VCE = 2V, Ic = 350mA
VCE = 2V, Ie = 125mA
VeE = 2V, Ie = 200mA
VCE = 2V, Ie = 275mA
VCE = 2V, Ic = 350mA
VCE = 2V,Ic = 350mA
VOE = 2V, Ie = 350mA
VeE = 2V, 10 = 350mA
VOE = 2V, 10 = 350mA
TA=TMAX
TA = TMW
TA=TMAX
TA=TM'N
TA = TM'N
TA=TM'N
TA=TMAX
TA=TMAX
TA=TMAX
TA=TM'N
TA = TM'N
TA=TM'N
TA = TM'N
TA=TMAX
TA=TMAX
TA=TMAX
TA=TMAX
TA=TM'N
TA=TMAX
TA=TM'N
TA = 25°C
TA = 25°C
TA = 25°C 0.5 EIN to 0.5 EOUT
TA= 25°C 0.5 E'N to 0.5 EOUT
VR = 95V
IF = 350mA
Note 3. These parameters, although guaranteed, are not tested in production.
6-47
Limits
Units
Min. Typ. Max.
100 J.lA
500 J.lA
500 J.lA
V
1.6 1.8
V
1.3 1.5
V
1.1 1.3
V
1.25 1.6
V
1.1 1.3
V
0.9 1.1
V
1.6 1.8
V
1.3 1.5
V
1.1 1.3
480 850 1300 J.lA
650 930 1350 IlA
240 350 500 J.lA
650 1000 1450 IlA
1180 1500 2400 J.lA
25
50
IlA
18
V
13
V
3.3
V
3.6
V
3.9
V
2.4
V
2.7
V
3.0
V
6.0
V
8.0
V
10
V
12
V
5.0
V
6.0
V
7.0
V
8.0
V
3.0
V
V
2.4
500
1000
25
pF
15
250 1000 ns
250 1000 ns
50
J.lA
V
1.7 2.0
•
SG2000 SERIES
CHARACTERISTIC CURVES
600
<'
.5-
~
:>
u
400
500
/
400
I
I
z
~
u
200
100
o
ia
I
300
0
>=
<'E
o
.4
2001
.8
~
5
1.0 1.2
100
II
o
2
3
4
5
B
9
1.0
V
:>
a.
z
~
MAXIMUM
r
1.5
..".~
a
TYPICAL
>-
1.0
~
16
18
20
22
24
26
I
/ /
I
,
1/
>a.
TYPICAL
0
a
1.0
2.0
0.5
3.0
4.0
5.0
<'
MAXI!UM
E
~
3.0
/
cr
cr
:>
u
>:>
a.
2.0
~
z
1.0
o
/
6.0
7.0
B.O
/'VPICAL
/
V
o
INPUT VOLTAGE
FIGURE 7.
INPUT CHARACTERISTICS - SG200S
"
en
~
I
>-
«
«
E
400
~
>-
~
cr
~
cr
200
i2
u
~
~u
0
u
"~
20
40
60
80
PER CENT DUTY CYCLF.-(%)
FIGURES.
PEAK COLLECTOR CURRENT VS. DUTY CYCLE
6 - 48
I-'
5.0
0'
600
E
i2
u
".. I-"""
TYPICAL
".. I-"'"
./
6.0
7.0
8.0
9.0
FIGURE 6.
INPUT CHARACTERISTICS - SG2004
«
~
/'"
/'"
10
INPUT VOLTAGE-(V)
+
V
..".V
MAXIMUM
1.0
z
~
J
200 250 300 350 400
1.5
:>
INPUT VOL TAGE-(V)
0'
4.0
100 150
<'E
FIGURES.
INPUT CHARACTERISTICS - SG2003
5.0
50
2.0
If
J
INPUT VOLTAGE-(V)
FIGURE 4.
INPUT CHARACTERISTICS - SG2002
a
2.5
/
I 1/
0.5
14
12
1/
:>
o
12
11
If
~
"
0.5
o
10
I
J
FIGURE 3.
OUTPUT CURRENT VS. INPUT CURRENT
E
,/
100
FIGURE 2.
OUTPUT CURRENT VS.INPUT VOLTAGE
<'
./
./
~
5
II
2.0
./
MAXIMUM
200
INPUT CURRENT-("A)
2.0
~
>-
~
I
~OI5,
2.5
1.5
>'-
INPUT VOLTAGE-(V)
2.5
<'E
AL.l TYPES
300
>-
1.4 1.6 1.B
FIGURE 1.
OUTPUT CHARACTERISTICS
~
I
2OI°t,..
a
SATURATION VOLTAGE-(V)
r
-
2003
<'
.5-
200
o
.6
I
2004
\
I
I
>-
I
.2
300
400
I
I
I
100
"~
11
12
SG2000 SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
16-PIN CERAMIC DIP
J-PACKAGE
Ambient
Part No. (Note 3) Temperature Range
SG2XXXJ/8838
SG2XXXJ
Connection Diagram
-55°C to 125°C
-55°C to 125°C
1~
4141-
~
5 ,-
16-PIN PLASTIC DIP
N- PACKAGE
SG2XXXN
DOC to 7DoC
4141-
~
, [ [-;,.,
16-PIN WIDE BODY
PLASTIC S.O.l.C.
DW-PACKAGE
SG2XXXDW
DOC to 7DoC
1
3~
4141-
7~
41-
,~ r-"..
3
1
20
16
~15
~14
13
~12
11
~'0
::J::J9
19
~ I"
,----<
4'1
41-
:->t-
5~
:0
"'-
2
10
::J9
41-
6
-55°C to 125°C
-55°C to 125°C
11
~
41-
5~
SG2XXXL/8838
SG2XXXL
12
4141-
2~
41T
20-PIN CERAMIC
LEAD LESS CHIP CARRIER
L- PACKAGE
14
~13
41-
6
7
15
41-
3 r
4
16
41-
2
41414141-
9
0.
10
11
12
It
1S
17
16
15
14
13
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
3. See selection guide for specific device types.
Silicon General .
11861 Western Avenue· Garden Grove, CA92641 • (714) 898-8121· TWX: 910-596-1804· FAX: (714) 893-2570
6-49
•
6 - 50
SG2064 THRU SG2077
SILICON
GENERAL
QUAD 1.5 AMP DARLINGTON SWITCHES
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
These high-voltage, high-current Darlington arrays are monolithic bipolar devices
especially designed for interfacing low-level control logic and peripheral loads
such as relays, solenoids, DC and stepping motors; multiplexed LED and
incandescent displays; and heaters. The logic inputs are designed to be
compatible with TTL, DTL, LSTTL, CMOS and NMOS logic families. Several of
the arrays include integral clamp diodes for driving inductive loads, and breakdown
voltage ratings to 80 volts are available.
•
•
•
•
Four power drivers per package
1_5 Amp collector currents
80V and 50V BVCEX ratings
Integral clamp diodes for Inductive
loads
• Compatibility with all popular logic
families
• Low Internal parasltlcs
All devices are supplied in a modified 16-lead plastic dual-in-line batwing package.
A copper alloy lead frame with webbing between the central pins provides low
thermal resistance to ambient air, and allows a 2.8 watt total power dissipation
rating within a standard footprint.
HIGH RELIABILITY FEATURES
-SG2069
These devices are direct replacements for ULN-2064B thru ULN-2077B devices.
• Available to MIL·STD·883 and DESC
SMD
BLOCK DIAGRAM
PARTIAL SCHEMATICS
SG2064 thru SG2067
0,
0--------,-*-+---t4---,--------<) 0.
OND
SG2064 thru SG2067
SG2064/2065: R'N = 3500:
SG2066/2067: RIN = 31<0:
7.2K
3K
'I. SCHEMATIC SHOWN
"
C:z o-----~*-+----t4~---____<)c,
SG2068 thru SG2071
--oVs
+Vs
o,o---~-~_M_1-1~,__U~--oo.
SG2068 thru SG2071
eND
eND
eND
"
c,
SG2068/2069:
72K
3K
RIN
= 2.SK, Rs = 9000
SG2070/2071: RIN = 11.6K, As = 3.4Ka
V, SCHEMATIC SHOWN
o----"'--~_M_1-1t-J>------"'----oc,
L -_ _ _ _ _--QK
SG2074/2075: RIN = 3500
SG2076/20n: RIN = 3Ka
SG2074 thru SG2077
V.SCHEMATlCSHOWN
72K
April 1990
6 - 51
•
SG2064 THRU SG2077
ABSOLUTE MAXIMUM RATINGS (Note 1)
Output Current .................................................................. 1.75A
Operating Junction Temperature
Hermetic (H-Packages) .................................................150°C
Plastic (W-Packages) ......................................... ; .......... 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering 10 sec.) ............................ 300°C
Logic Input Voltage ........................................................ (Note 2)
Logic Input Current ........................................................... 25mA
Supply Voltage
SG2068/2069 ............................................................... :... 12V
SG2070/2071 .......... .......... ..... ................................ ......... 22V
Output Voltage ................................................................ (Note 2)
Note 1. Values beyond which damage may occur.
Note 2. See Selection Guide located on last page of this data sheet.
THERMAL DERATING CURVES
~
~
~
~
~
ill
ill
"
"
~
~
175
175
CASE TEt.1PERATURE -
AMBIENT TEMPERATURE - "c
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note
"C
3)
Operating Ambient Temperature Range
SG2069 (Side-Brazed) .................................. -55°C to 125°C
SG2064 thru SG2077 (Batwing) .......................... O°C to 70°C
Peak Output Current ........................................................... 1.5A
Supply Voltage
SG2068/2069 ................................................................... 10V
SG2070/2071 ................................................................... 20V
Note 3. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of TA = 25°C. Low duty cycle pulse testing techniques
are used which maintains junction and case temperatures equal to the ambient temperature.)
SG2064 thru SG2067
Parameter
Output Leakage Current
Applicable
Devices
SG2064/2066
SG2065/2067
Output Sustaining Voltage (NOle 4)
Collector-Emitter Saturation Voltage
Input Current
SG2064/2066
SG2065/2067
All
SG2064/2066
SG2065/2067
SG2064/2065
SG2066/2067
Test Conditions
V CE '" 50V
V CE = 50V, TA =TMAX
V CE = BOV
VCE = BOV, TA = T MAX
Ie = l00mA, V,N = O.4V
Ic = 1OOmA, Y'N = O.4V
Ie '" 500I)'lA, Ie " 625!lA
Ie =750mA, 18 =935!lA
Ie = 1.0A, IB = 1.25mA
Ic = 1.25A, 18 =2.0mA
Ie I.SA, 18 = 2.25mA
Y'N =2.4V
Y'N =3.75V
Y'N =5.0V
Y'N =12V
=
Note 4. These parameters, although guaranteed, are not tested in production.
6 - 52
Limits
Units
Min. Typ. Max.
100 !lA
500
!lA
100 !lA
500
!lA
35
V
50
V
1.1
V
V
1.2
1.3
V
1.4
V
1.5
V
1.4
4.3
mA
mA
3.3
9.6
0.6
1.8
mA
1.7
5.2
mA
SG2064 THRU SG2077
ELECTRICAL SPECIFICATIONS
(continued)
SG2064 thru SG2067
Parameter
Input Voltage
Applicable
Devices
SG2064/2065
SG2066/2067
Turn-On Delay (Note 4)
Turn-Off Delay
Clamp Diode Leakage (Note 4) Current
All
All
SG2064/2066
SG2065/2067
Clamp Diode Forward Voltage
All
Test Conditions
VCE = 2V, Ie = LOA
VeE = 2V, Ie = 1.5A
VeE =2V, le= 1.0A
VeE = 2V, Ie = 1.5A
0.5 E'N to 0.5 EOUT
0.5 E'N to 0.5 EOUT
VA = 50V
VA= 50V, TA=TMAX
VA = 80V
VA = 80V,TA =T MAX
IF = LOA
IF= 1.5A
Limits
Units
Min. Typ. Max.
2.0
V
2.5
V
6.5
V
10
V
1.0
IlS
1.5
Ils
50
IlA
100 IlA
50
IlA
100 IlA
1.75 V
2.0
V
SG2068 thru SG2071
Parameter
Output Leakage Current
Applicable
Devices
SG2068/2070
SG2069/2071
Output Sustaining Voltage (Note 4)
Collector-Emitter Saturation Voltage
SG2068/2070
SG2069/2071
SG2068/2069
SG2069
SG2070/2071
SG2071
Input Current
SG2068/2069
SG2070/2071
Input Voltage
Supply Current
Turn-On Delay (Note 4)
Turn-Off Delay (Note 4)
Clamp Diode Leakage Current
SG2068/2069
SG2070/2071
SG2068/2069
SG2070/2071
All
All
SG2068/2070
SG2069/2071
Clamp Diode Forward Voltage
All
Test Conditions
VeE = 50V
VeE = 50V, TA = TMAX
VeE = 80V
VeE = 80V, TA = TMAX
Ie = 100mA, V,N = O.4V
Ie = 100mA, V,N = O.4V
Ie = 500mA, V,N = 2.75V
Ie = 750mA, V,N = 2.75V
Ie = LOA, V,N = 2.75V
Ie = 1.25A, V,N = 2.75V
Ie = 1.5A, V,N = 2.75V
Ie = 500mA, V,N = 5.0V
Ie = 750mA, V,N = 5.0V
Ie = 1.0A, V,N = 5.0V
Ie = 1.25A, V,N = 5.0V
Ie = 1.5A, V,N = 5.0V
V,N =2.75V
V,N = 3.75V
V,N = 5.0V
V,N = 12V
VeE = 2V, Ie = 1.5A
VeE = 2V, Ie = 1.5A
Ie = 500mA, V,N = 2.4V
Ie = 500mA, V,N = 5.0V
0.5 E'N to 0.5 EOUT
0.5 E'N to 0.5 EOUT
VA = 50V
VA = 50V, TA = TMAX
VA = 80V
VA = 80V, TA = TMAX
IF = LOA
IF = 1.5A
6 - 53
Limits
Units
Min. Typ. Max.
100 IlA
500 IlA
100 IlA
500 IlA
V
35
V
50
1.1
V
1.2
V
1.3
V
1.4
V
1.5
V
1.1
V
1.2
V
1.3
V
V
1.4
1.5
V
550 IlA
1000 IlA
400 IlA
1250 Il A
2.75
V
5.0
V
6.0 mA
4.5 mA
1.0
Ils
1.5
Ils
50
IlA
100 IlA
50
IlA
100 IlA
1.75 V
2.0
V
SG2064 THRU SG2077
ELECTRICAL SPECIFICATIONS (continued)
SG2074 thru SG2077
Applicable
Devices
SG207412076
Parameter
Output Leakage Current
SG207512077
Output Sustaining Voltage (Note 4)
Collector-Emitter Saturation Voltage
SG207412076
SG2075/2077
All
Input Current
SG2074/2076
SG2075/2077
SG2074/2075
SG2076/2077
Input Voltage
SG2074/2075
SG2076/2077
Turn-On Delay (Note 4)
Tum-Off Delay (Note 4)
All
All
limits
Units
Min. Typ. Max.
100 pA
500 pA
100 pA
500 itA
V
35
V
50
1.1
V
1.2
V
1.3
V
1.4
V
V
1.5
4.3 mA
2.0
9.6 mA
4.5
1.8 mA
0.9
5.2 mA
2.75
2.0
V
2.5
V
6.5
V
10
V
1.0 !1S
1.5 !1S
Test Conditions
VeE = 50V
VeE = 50V, TA = TMAJ(
VeE=BOV
VeE = BOV, TA = TMAX
Ie = 100mA, VIN = OAV
Ie = 100mA, VIN = 0.4V
Ie = 500mA, 18 = 625pA
Ie =750mA, 18 =935ltA
Ie = 1.0A, 18 = 1.25mA
Ie = 1.25A, Ie =2.0mA
Ie = 1.5A, Ie = 2.25mA
VIN = 2.4V
VIN = 3.75V
VIN = 5.0V
VIN = 12V
VeE =2V, Ie = 1.0A
VeE = 2V, Ie = 1.5A
VeE = 2V, Ie = 1.0A
VeE = 2V, Ie = 1.5A
0.5 EIN to 0.5 EOUT
0.5 EIN to 0.5 EnllT
CHARACTERISTIC CURVES
14
.,E
i
13
12
I'
..,~."
B
~
~~
6
~
:0
"z
4
2
.,.5-
V
I~g~gl:~~~
10
/
I~ V
~
~~~~~N
r
TH
.......
........ V
!
6
I~g~g~~~~;
4
z
~ ~ »'" ~,' ~"~
~~
I ~.~ ~ ~ ~ ~
~
3
~
"-
.,
5
:0
2~
1
0
~~
~~~~~
~
:""U~
~ P'"'
2.0
2.5
3.0
3.5
4.0
4.5
5.0
6
B
7
9
10
INPUT VOLTAGE-(V)
"
12
r
DEVllE
1.5
~' r\ 1\
~
13
r\ t\.
1.0
'"
G
~
U
u
~
~
0.5
I
~g~D~~Tl~G DRIVERS
-
"1
~
utT
.......
"
.......
..:....
"
'"'-
SIt.1Ul..TA.NEOUSLY
SG2°r41RU
207
0
0
10 20 30 40 50 60 70 80 90 100
OUTY CYCLE-(%)
FIGURE 4.
PEAK ALLOWABLE COLLECTOR CURRENT
VS. DUTY CYCLE AT T, - 70'C
6-54
J. ~
If'
SG2064/66
SG2074/76
1.5
2.5
/
/
0
0.5
1.0
2.0
3.0
FIGURE 3.
MAXIMUM REQUIRED LOGIC INPUT CURRENT
VS. COLLECTOR CURRENT
r f"':':::-..........
r--..
0.5
1.0
INPUT CURRENT-(;uA)
FIGURE 2.
LOGIC INPUT CURRENT VS. INPUT VOLTAGEHIGH LEVEL LOGIC
.,
~
:0
0
5
INPUT VOLTAGE-(V)
FIGURE 1.
LOGIC INPUT CURRENT VS. INPUT VOLTAGE5VLOGIC
~gg~~~~; -:;>
1.5
r
B
u
0
1.5
".-- / _--r
7
V
3.5
SG2064 THRU SG2077
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
16-PIN PLASTIC BATWING
W- PACKAGE
Part No,
SG2064W
SG2065W
SG2066W
SG2067W
(See Notes Below)
Ambient
Temperature Range
ooe to
ooe to
ooe to
ooe to
70 0 e
70 0 e
70 0 e
70 0 e
Connection Diagram
K[ 1
c, [ ,
16P
81
14
15
3
[
"wP
GND [ ;
82
12
6
[
11
C, [ 7
K[ ,
16-PIN PLASTIC BATWING
W- PACKAGE
16-PIN PLASTIC BATWING
W- PACKAGE
16-PIN SIDE-BRAZED DIP
H- PACKAGE
SG2068W
SG2069W
SG2070W
SG2071W
SG2074W
SG2075W
SG2076W
SG2077W
SG2069Hf883B
SG2069H
ooe to
ooe to
ooe to
ooe to
ooe to
ooe to
ooe to
ooe to
70 0 e
70 0 e
70 0 e
70 0 e
70 0 e
70 0 e
70 0 e
70 0 e
1
K[
10
'J
c, [ ,
GND [ 4
5
B, [ 6
N.C. [ 7
C, [ ,
1
E, [ ,
B, [ 3
GND [ 4
5
B, [ 6
E, [ 7
C, [ ,
-55°e to 125°e
-55°e to 125°e
K
P
GND
83
N.C.
9
Pc,
16
Pc,
15
14
B, [ 3
c, [
c,
P N.C.
P B,
P B,
P v,
" WGND
"
11
B,
10 pc,
9 b K
P
\J
16
15
14
Pc,
P E,
P B,
" WGND
"
11 :J B,
10 :J E,
9
:J c,
[r;"='16 pc,
c, [ ,
B, [3
GND [4
GND [5
B2 [ 6
N.C. [7
15p B,
14p V,
13p GND
"P
GND
11 P 8
lOP Cs
3
C,[~j:JK
20-PIN PLASTIC
BATWING S.O.I.C.
DWW - PACKAGE
SG2064DWW
SG2065DWW
SG2066DWW
SG2067DWW
ooe
ooe
ooe
ooe
to
to
to
to
70 0 e
70 0 e
70 0 e
70 0 e
KIT
,1
5
B, IT
C, IT
KIT
ooe to
OOeto
ooe to
ooe to
70 0 e
70 0 e
70 0 e
70 0 e
K IT
c, IT
,
c.
N.C.
13
12
10
11
,1
20
GND
f:IJ
ITI
83
N.C.
P:J
c,
fIJ
c,
fJ:J
, : i l'
19
B,
3
4
B, IT
N.C. IT
C, IT
6 - 55
16
15
14
9
5
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
3. See selection guide for specific device types.
fTI
fJ:J
4
7
SG2068DWW
SG2069DWW
SG2070DWW
SG2071DWW
19
3
6
20-PIN PLASTIC
BATWING S.O.I.C.
DWW - PACKAGE
20
, :I l'
c, IT
16
6
15
,
7
14
9
12~ Cs
10
11
13
GND
f:IJ
83
f:o
K
SG2064 THRU SG2077
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
20-PIN PLASTIC
BATWING S.O.l.C.
DWW - PACKAGE
(continued)
Ambient
Temperature Range
Part No.
SG20740WW
SG20750WW
SG20760WW
SG20770WW
O°Cto 70°C
O°Cto 70°C
O°Clo 70°C
O°Clo 70°C
Connection Diagram
C, II
E, II
,:[
1
20
2
19
3
4
5
•
•
7
e,
II
E, II
C, II
ITI
~
C,
E4
l'
~:
14
13
9
12
10
11
GND
t:o
PJ
B,
E3
tTI c,
SELECTION GUIDE
Device
logic Inputs
SG2064
SG2065
VcExMax
50V
SOV
VCE/SUS Max
35V
50V
VIN Max
15V
15V
SG2066
SG2067
50V
SOV
35V
50V
30V
30V
6V to 15V CMOS and PMOS
SG206S
SG2069
50V
SOV
35V
50V
15V
15V
TTL, OTl, Schottky TTL, 5V CMOS amd NMOS
SG2070
SG2071
50V
SOV
35V
50V
30V
30V
6V to 15V CMOS and PMOS
SG2074
SG2075
50V
SOV
35V
50V
30V
60V
General Purpose
SG2076
SG2077
50V
SOV
35V
50V
30V
60V
6V to 15V CMOS and PMOS
TTL, OTl, Schottky TTL, 5V CMOS and NMOS
/
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
6 - 56
SG2800 SERIES
SILICON
GENERAL
HIGH VOLTAGE MEDIUM
CURRENT DRIVER ARRAYS
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG2800 series integrates eight NPN Darlington pairs with
internal suppression diodes to drive lamps, relays, and solenoids in
many military, aerospace, and industrial applications that require
severe environments. All units feature open collector outputs with
greater than 50V breakdown voltages combined with 500mA current
carrying capabilities. Five different input configurations provide
optimized designs for interfacing with DTL, TTL, PMOS, or CMOS
drive signals. These devices are designed to operate from -55°C to
125°C ambient temperature in a 18-pin dual in-line ceramic (J)
package and 20-pin leadless chip carrier (LCC).
•
•
•
•
•
•
Eight NPN Darlington pairs
Collector currents to 600mA
Output voltages from 50V to 95V
Internal clamping diodes for inductive loads
DTL, TTL, PMOS, or CMOS compatible inputs
Hermetic ceramic package
HIGH RELIABILITY FEATURES
•
•
•
•
•
•
•
•
Available to MIL·STD·883 and DESC SMD
MIL·M3851 0/141 06BVA • JAN2801J
MIL·M3851 0/141 07BVA • JAN2802J
MIL·M38510/14108BVA· JAN2803J
MIL·M38510/14109BVA· JAN2804J
MIL·M38510/14110BVA· JAN2805J
Radiation data available
SG level "S" processing available
•
PARTIAL SCHEMATICS
SG2801/2811/2821
SG2802/2812/2822
I
I
7.2K
+v
SG2803/2813/2823
+v
I
I
3K
L _____ ~--
,--------'I----{
7.2K
3K
L---M---
SG2804/2814/2824
I
I
7.2K
+v
SG2805/2815
+v
I
I
3K
L---M---
7.2K
+v
3K
L---M---
April 1990
6-57
SG2800 SERIES
ABSOLUTE MAXIMUM RATINGS (Note 1)
Output Voltage, VCE
(SG2800, 2810 series) .................................................... SOV
(SG2820 series) .............................................................. 9SV
Input Voltage; VIN
(SG2802,3,4 series) ......................................................... 30V
(SG280S series) ............................................................... 1SV
Continuous Input Current, liN ............................................ 2SmA
Note 1. Values beyond which damage may occur.
Continuous Collector Current, Ic
(SG2800, 2820) .......................................................... SOOmA
(SG2810) ..............................................•..................... 600mA
Operating Junction Temperature
Hermetic (J, L Packages) ............................................. 1S0°C
Storage Temperature Range ............................ -6SoC to 1S0°C
Lead Temperature (Soldering 10 sec.) ............................ 300°C
THERMAL DERATING CURVES
2.5
2.0
~,
1.5
~
~
~
~
is
1.0
~
0.5
0
5.0
i"I...
40 "
"'
.
~
"
'" , ,
~
~~
~
~
"~~-r<
0
25
50
75
is 2.0
~
~
,,,~
'00
(j>~
,~
'.0
~
~
~
~o
~
,
"1\
~~
150
1.0
0
175
0
25
50
75
"~'\
'00
'2'
150
175
CASE T'EMPERATURE - "C
AMBIENT TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Output Voltage, VCE
SG2800, SG2820 series .................................................. SOV
SG281 0 series ................................................................. 9SV
Note 2. Range over which the device is functional.
Peak Collector Current, Ic
SG2800, SG2820 series ............................................. 3S0mA
SG281 0 series ............................................................ SOOmA
Operating Ambient Temperature Range ............ -SSoC to 12SOC
SELECTION GUIDE
Device
SG2801
VCE Max
SOV
IcMax
SOOmA
SG2802
SG2803
SG2804
SG280S
SG2811
SOV
SOV
SOV
SOV
SOV
SOOmA
SOOmA
SOOmA
SOOmA
600mA
SG2812
SOV
600mA
Logic Inputs
General Purpose
PMOS,CMOS
14V-2SV PMOS
SVTTL, CMOS
6V-1SV CMOS, PMOS
High Output TTL
General Purpose
PMOS,CMOS
14V-2SV PMOS
6 - S8
Device
SG2813
SG2814
SG281S
SG2821
VcEMax
SOV
SOV
SOV
9SV
IcMax
600mA
600mA
600mA
SOOmA
SG2822
SG2823
SG2824
9SV
9SV
9SV
SOOmA
SOOmA
SOOmA
Logic Inputs
SVTTL, CMOS
6V-1SV CMOS, PMOS
High Output TTL
General Purpose
PMOS,CMOS
14V-2SV PMOS
SVTTL, CMOS
6V-1SVCMOS, PMOS
SG2800 SERIES
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures of -55°C $ T. $ 125°C. Low duty cycle pulse
testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
SG2801 thru SG2805
Parameter
Output Leakage Current (lCEX)
Collector - Emitter (VCE(SAT)
Input Current (I'N(ON)
(I'N(OFFI)
input Voltage (VIN(ON)
Applicable
Devices
All
SG2802
SG2804
All
TA = TMIN
TA=TMIN
TA = TMIN
TA = 25°C
TA = 25°C
TA = 25°C
TA = TMAX
TA=TMAl(
TA=TMAX
SG2802
SG2803
SG2804
SG2805
All
SG2802
SG2803
SG2804
SG2805
D-C Forward Current
Transfer Ratio (h FE )
Input Capacitance (C IN ) (Note 3)
Turn-On Delay (TPLH)
Turn-Off Delay (TPHL)
Clamp Diode Leakage Current (I R)
Clamp Diode Forward Voltage (V.)
Temp.
SG2801
All
All
All
All
All
Test Conditions
VCE =50V
VCE = 50V, VIN = 6V
VCE = 50V, VIN = lV
Ic = 350mA, Ie = 8501tA
Ic = 200mA, Ie = 5501tA
Ic = 100mA, Ie = 3501tA
Ic = 350mA, Ie = 5001tA
Ic = 200mA, Ie = 3501tA
Ic = 100mA, Ie = 2501tA
Ic = 350mA, Ie = 5001tA
Ie = 200mA, Ie = 3501tA
Ie = 100mA, Ie = 2501tA
VIN = 17V
VIN = 3.85V
VIN =5V
VIN = 12V
VIN =3V
Ic = 500llA
VCE = 2V, Ie = 300mA
VCE = 2V, Ic = 300mA
VeE = 2V, Ie = 200mA
VeE = 2V, Ie = 250mA
VCE = 2V, Ie = 300mA
VCE = 2V, Ie = 200mA
VeE = 2V, Ie = 250mA
VeE = 2V, Ie = 300mA
VeE = 2V, Ic = 125mA
VCE = 2V, Ic = 200mA
VCE = 2V, Ic = 275mA
VCE = 2V, Ic = 350mA
VCE = 2V, Ic = 125mA
VCE = 2V, Ic = 200mA
VCE = 2V, Ic = 275mA
VCE = 2V, Ic = 350mA
VCE = 2V, Ic = 350mA
VCE = 2V, Ic = 350mA
VCE = 2V, Ic = 350mA
VCE = 2V, Ic = 350mA
TA=TMAX
TA = TM'N
TA=TMAX
TA=TMIN
TA =TMIN
TA=TMIN
TA=TMAX
TA=TMAX
TA=TMAX
TA = TMIN
TA = TMIN
TA =TMIN
TA = TMIN
TA=TMAX
TA = TMAX
TA=TMAX
TA=TMAX
TA=TMIN
TA = TMAX
TA = TMIN
TA = 25°C
TA = 25°C
TA = 25°C 0.5 EIN to 0.5 EOUT
TA = 25°C 0.5 EIN to 0.5 EOUT
VR = 50V
I. = 350mA
Note 3. These parameters, although guaranteed, are not tested in production.
6 - 59
Limits
Min. Typ. Max.
100
500
500
1.6 1.8
1.3 1.5
1.1 1.3
1.25 1.6
1.1 1.3
0.9 1.1
1.6 1.8
1.3 1.5
1.1 1.3
480 850 1300
650 930 1350
240 350 500
650 1000 1450
1180 1500 2400
25
50
18
13
3.3
3.6
3.9
2.4
2.7
3.0
6.0
8.0
10
12
5.0
6.0
7.0
8.0
3.0
2.4
500
1000
25
15
250 1000
250 1000
50
1.7 2.0
Units
ItA
IlA
ItA
V
V
V
V
V
V
V
V
V
ItA
ItA
ItA
IlA
ItA
IlA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
pF
ns
ns
IlA
V
•
SG2800 SERIES
ELECTRICAL SPECIFICATIONS (continued)
SG2811 thru SG281S
Parameter
Output Leakage Current (Icex)
Collector - Emitter (VCE(SAT))
Input Current (IIN(ON»)
(I'N(OF3)
Input Voltage (V'N(ON)
Applicable
Devices
All
SG2812
SG2814
All
SG2812
SG2813
SG2814
SG281S
All
SG2812
SG2813
SG2814
SG281S
D-C Forward Current
Transfer Ratio (h FE)
Input Capacitance (C,N ) (Note 3)
Turn-On Delay (TPLH)
Tum-Off Delay (TPHL)
Clamp Diode Leakage Current (IR)
Clamp Diode Forward Voltage (VF)
SG28tl
All
All
All
All
All
Test Conditions
Temp.
VCE =SOV
VCE = SOV, VIN = 6V
VCE = 5OV, VIN = 1V
TA=TMIN Ic = SOOmA, Is = 11 OOIlA
TA=TMIN Ic = 3S0mA, Is = 8S0pA
TA=TMIN Ic = 200mA, Is = SSOIlA
TA =2SoC Ie = SOOmA, Is = 60011A
TA = 2SoC Ic = 3S0mA, Is = SOOIlA
TA =2SoC Ic = 200mA, Is = 3S0pA
TA = TMAX Ic = SOOmA, Is = 60011A
TA=TMAX Ic = 3S0mA, Is = SOOpA
TA = TMAX Ic = 200m A, Is = 3S011A
V,N = 17V
VIN = 3.8SV
VIN=SV
V"' = 12V
V;~=3V
TA = TMAX
TA=TMIN
TA=TMAX
TA=TMIN
TA = TMIN
TA=TuIN
TA = TMAX
TA=TMAX
TA = TMAX
TA=TuIN
TA = TUIN
TA=TuIN
TA = TMAX
TA=TMAX
TA=TMAX
TA=TuIN
TA = TMIN
TA=TMAX
TA=TMAX
TA = TUIN
TA = 2SoC
TA =2SoC
TA = 2SOC
TA = 25°C
Note 3. These parameters. although guaranteed. are not tested in production.
Ic = SOOIlA
VCE = 2V, Ic = SOOmA
VCE = 2V, Ic = SOOmA
VCE = 2V, Ic = 2S0mA
VCE = 2V, Ic = 300mA
VCE = 2V, Ic = SOOmA
VCE = 2V, Ic = 2S0mA
VCE = 2V, Ic = 300mA
VCE = 2V, Ic = SOOmA
VCE = 2V, Ic = 27SmA
VCE = 2V, Ic = 3S0mA
VCE = 2V, Ic = SOOmA
VCE = 2V, Ic = 27SmA
VCE = 2V, Ic = 3S0mA
VCE = 2V, Ic = SOOmA
VCE '= 2V,Ie = 3S0mA
VCE = 2V, Ic = SOOmA
VCE = 2V,Ic = 3S0mA
VCE = 2V, Ic = SOOmA
VCE = 2V,Ic = SOOmA
VCE = 2V, Ic = SOOmA
O.S EIN to O.S EOUT
O.S EIN to O.S EOUT
VR = SOV
IF = 3S0mA
IF= SOOmA
Limits
Min. Typ. Max.
100
SOO
500
1.8 2.1
1.6 1.8
1.3 1.S
1.7 1.9
1.2S 1.6
1.1 1.3
1.8 2.1
1.6 1.8
1.3 1.S
480 8S0 1300
6S0 930 13S0
240 3S0 SOO
6S0 1000 14S0
1180 1S00 2400
2S
so
23.S
17
3.6
3.9
6.0
2.7
3.0
3.S
10
12
17
7.0
8.0
9.S
3.0
3.S
2.4
2.6
450
900
2S
1S
2S0 1000
2S0 1000
SO
1.7 2.0
2.S
Units
pA
llA
pA
V
V
V
V
V
V
V
V
V
pA
IlA
pA
IlA
pA
IlA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
pF
ns
ns
llA
V
V
SG2800 SERIES
ELECTRICAL SPECIFICATIONS (continued)
SG2821 thru SG2824
Parameter
Output Leakage Current (leEx)
Collector - Emitter (VeE(SAT))
Input Current (I'N(ON»)
Applicable
Devices
All
SG2822
SG2824
All
Temp.
TA = TMIN
TA=TMIN
TA=TMIN
TA = 25°C
TA = 25°C
TA = 25°C
TA=TMAX
TA=TMAX
TA=T MAX
SG2822
SG2823
SG2824
All
SG2822
Test Conditions
VeE = 95V
VeE = 95V, V,N = 6V
VeE = 95V, V,N = 1V
Ie = 350mA, Is = 850ltA
Ie = 200mA, Is = 550!1A
Ie = 100mA, Is = 350J.lA
Ie = 350mA, Is = 500!1A
Ie = 200mA, Is = 350J.lA
Ie = 100mA, Is = 250!1A
Ie = 350mA, Is = 500ltA
Ie = 200mA, Ie = 350!1A
Ie = 100mA, Is = 250J.lA
V,N = 17V
V,N = 3.85V
V,N =5V
V,N = 12V
Ie = 500J.lA
VeE = 2V, Ie = 300mA
VeE = 2V, Ie = 300mA
VeE = 2V, Ie = 200mA
Vee = 2V, Ie = 250mA
Vee = 2V, Ie = 300mA
Vee = 2V, Ie = 200mA
Vee = 2V, Ie = 250mA
Vee = 2V, Ie = 300mA
VeE=2V,le= 125mA
Vee = 2V, Ie = 200mA
VeE = 2V, Ie = 275mA
Vee = 2V, Ie = 350mA
Vee = 2V, Ie = 125mA
Vee = 2V, Ie = 200mA
VeE = 2V, Ie = 275mA
Vee = 2V, Ie = 350mA
VeE = 2V, Ie = 350mA
Vee = 2V, Ie = 350mA
TA=TMAX
TA = TMIN
TA=TMAx
SG2823
TA =TMIN
TA=TMIN
TA = TMIN
TA=TMAX
TA=TMA)(
TA=TMA)(
SG2824
TA = TMIN
TA = TMIN
TA =TMIN
TA=TMIN
TA=TMAX
TA = TMAX
TA = TMAX
TA=TMA)(
D-C Forward Current
SG2821
TA = TMIN
Transfer Ratio (h FE)
TA = 25°C
Input Capacitance (C ,N ) (Note 3)
All
TA = 25°C
Turn-On Delay (TPLH)
All
TA = 25°C 0.5 E'N to 0.5 EOUT
Turn-Off Delay (TPHL)
All
TA = 25°C 0.5 E'N to 0.5 EOUT
Clamp Diode Leakage Current (lR)
All
VR= 95V
Clamp Diode Forward Voltage (VF)
All
IF= 350mA
Note 3. These parameters, although guaranteed, are not tested in production.
(I'N(OFFI)
Input Voltage (V'N(ON)
6-61
Limits
Units
Min. Typ. Max.
100 itA
500 itA
500 !1A
V
1.6 1.8
V
1.3 1.5
V
1.1 1.3
V
1.25 1.6
V
1.1 1.3
V
0.9 1.1
V
1.6 1.8
V
1.3 1.5
1.3
V
1.1
480 850 1300 J.lA
650 930 1350 J.lA
240 350 500 !1A
650 1000 1450 !1A
25
50
!1A
18
V
13
V
3.3
V
3.6
V
3.9
V
2.4
V
2.7
V
3.0
V
6.0
V
8.0
V
10
V
12
V
5.0
V
6.0
V
7.0
V
8.0
V
500
1000
25
pF
15
250 1000 ns
250 1000 ns
50
!1A
V
1.7 2.0
•
SG2800 SERIES
CHARACTERISTIC CURVES
400
600
<-E
SOD
;r
400
~
300
~
"z
"
~
"
/
I
0
F=
200
I
100
o
a
<-E
ia
/
.4
.6
.8
300
2
MAXIMUM
~
">-
,Jsr
/
I
o
.3
2
1.0
."
0.5
V
">-
TYPICAL
B
9
10
14
"
16
18
20
22
24
5.0
J
4.0
MAXILM
3.0
I
2.0
VV
12
MAXIMUM
TYPICAL
V
o
INPUT VOLTAGE
FIGURE 7.
INPUT CHARACTERISTICS· SG2B05
o
50
100 150 200 250 300 .350 400
1.5
..s<-,'.
/ L
/
~
=>
//
1.0
,
//
">-=>
TYPICAL
a
1.0
2.0
4.0
5.0
6.0
7.0
B.O
0'
!<
«
«
"'">-I
«
E
400
"
>-
~
a
w
'"
I"
200
~
"'"
20
40
60
80
PER CENT DUTY CYCLE-(%)
FIGUREB.
PEAK COLLECTOR CURRENT VS. DUTY CYCLE
6-62
,., ,.,i-""'"
TYPICAL
100
~
,.,,....
:..,....-r-'"
6.0
7.0
8.0
9.0
FIGURE 6.
INPUT CHARACTERISTICS· SG2B04
0' 600
Ii'
+
'"'"=>
"
'"
I"
"
~
"«
'"
it
./
~
10
INPUT VOLTAGE-(V)
FIGURES.
INPUT CHARACTERISTICS· SG2B03
"
1.0
5.0
INPUT VOLTAGE-(V)
E
MAXIMUM
0.5
3.0
..,I-'
1.5
~
j
0.5
26
2.0
1/
z
/
I
L
2.5
>-
~V
1.0
11
)
/
2.0
Ii'
FIGURE 4.
INPUT CHARACTERISTICS· SG2B02
o
5
o
1/
INPUT VOLTAGE-(V)
'"'"=>
">~
4
100
FIGURE 3.
OUTPUT CURRENT VS. INPUT CURRENT
o
~
I
J
FIGURE 2.
OUTPUT CURRENT VS. INPUT VOLTAGE
;r
~
=>
V"
.,,'
/
12
..s<-,'.
=>
INPUT CURRENT-(IJA)
<-E
/
1.5
Ii'
"
/
200
f=
0
2.5
..s
~
3'">-
INPUT VOLTAGE-(V)
2.5
2.0
ALL TYPES
300
=>
100
o
1.4 1.6 1.B
1.0 1.2
I
;r
280t.,1
200
=>
§
FIGURE,.
OUTPUT CHARACTERISTICS
=>
3
<-E
I
2804
SATURATION VOLTAGE-(V}
<-
-
2.0
>-
I
.2
400
11
12
SG2800 SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
18-PIN CERAMIC DIP
J-PACKAGE
Ambient
Part No. (Note 3) Temperature Range
SG28XXJ/8838
SG28XXJ
Connection Diagram
-55°C to 125°C
-55°C to 125°C
1~
2'3
•
•
6L
7
•
. [ P,
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L-PACKAGE
SG28XXU8838
SG28XXL
-55°C to 125°C
-55°C to 125°C
3
2
_4141414141414141-
1
20
'hl ~
•
•
1B
17
16
I.
"
.J 13
12
11
:::J
I.
I.
T;:,.
'*
'*
'*
r----'
'* L,
.~
.'*
"lp'* 1 /
17
16
'-< I.
7
•
I.
11
12
I.
13
•
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
3. See Selection Guide for specific device types.
Silicon General •
11861 Western Avenue. Garden Grove. CA 92641 • (714) 898-8121 • TWX: 910-596-1804 • FAX: (714) 893-2570
6-63
6 - 64
SG5792
SILICON
ADVANCED DATA SHEET
GENERAL
QUAD PIN DIODE DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
This monolithic multiple high-voltage inverting switch is designed to
interface between low level digital logic and high-voltage PIN
diodes. Each driver stage is self-contained and protected against
diode shorts, requiring only a single resistor for determining diode
forward current. Reverse operation provides high transient switching current capability for fast diode turnoff. Forward operation is
effected when the input is pulled high.
•
•
•
•
•
•
•
Four independent PIN diode drivers
50 volts reverse bias
300mA forward current
Fast diode turnoff
Shorted diode protection
Compatible with most logic families
For 85V or 125V devices contact factory
HIGH RELIABILITY FEATURES - SG5792
o Available to MIL-STD-883
o SG level "S" processing available
BLOCK DIAGRAM
Vee
IN #1
DRIVER #1
OUT #1
~--oVss
Vee
IN #2
OUT #2
INPUT
0 - - - 0 OUTPUT
BITE
IN #3
OUT #3
GROUND
(each driver)
IN #4
DRIVER #4 I---+---
0
<=
'-
25
~
"~
0
~
20
'"
r\.
TA=2Sct
~
1.5
-
r--
0
0
-10
tw=300~
-20
'"
~
"
DUTY CYCLE:;; 2
80
TA=70:;
"JI
1.2
100
;i
:::::: ~
~
.....
TA-2S6C
~\
'TA"'70
is
<=
0.4
~
0.3
TA .. 7oClc
rio
f!
~
u
200
400
FIGURE 3.
BASE-EMITTER VOlTAGE VS. COLLECTOR
VOLTAGE
f't
I~
0.2
~
70100
iW
;i
g
40
COLLECTOR CURRENT-(mA)
COLLECTOR CURRENT -(mA)
~
0.1
~ f9'
~
~,
I-
TA-2S
(0
2.0
~
~
""-~~
~-"
i'-: '\.
r
~
tee)
(8...../:J
0
~~
C
~
0
175
0
'C
'"
25
50
75
100
~
125
'50
175
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Notes 2 & 3)
Operating Ambient Temperature Range
Supply Voltage (Vee)
SG554528, SG55462, SG55472 ....................... 4.5V to 5.5V
SG554528, SG55462, SG55472 ................... -55°C to 125°C
SG754528, SG75462, SG55472 .................... 4. 75V to 5.25V
SG754528, SG75462, SG75472 ........................ O°C to 70°C
Note 2. Range over which device is functional.
Note 3. The substrate (pin 8) must always be at the most-negative device voltage for proper operation.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG55452B/462/472 with -55°e ~ TA ~ 125°e, and
SG75452B/462/472 with aoe ~ TA ~ 7aoe. Typical values are tested at Vee = 5V, and TA = 25°e. Low duty cycle pulse testing techniques are used which
maintains junction and case temperatures equal to the ambient temperature.)
SG554528
SG754528
SG55462
SG75462
Units
Parameter
Test Conditions
SG55472
SG75472
Min_
Typ_ Max.
Min. Typ. Max_
V
High-level Input Voltage (V IH)
2
2
0.8
Low-level Input Voltage (VIL)
V
0.8
V
-1.2 -1.5
Input Clamp Voltage (V,K)
-1.2 -1.5
Vee = MIN,IIN =-12mA
100
High-level Output Current (lOH)
300
Vce = MIN, VIL = 0.8V,
IlA
VOH = 30V SGX5452B
VOH = 35V SGX5462
VOH = 70V SGX5472
0.25 0.5
V
Low-level Output Voltage (VOL)
0.25 0.4
Vee = MIN, VIH = 2.0V, 10L = 100mA
V
0.5 0.8
0.5 0.7
Vce =MIN, V,H " 2.0V, 10L =300mA
1.0
mA
1.0
Input Current at Max Y'N (liN)
Vee = MAX, Y'N =5.5V
40
High-level Input Current (I'H)
40
Vce = MAX, Y'N =2.4V
IlA
-1.0 -1.6
mA
Low-level Input Current (IlL)
-1.0 -1.6
Vee = MAX, VIN = O.4V
Supply Current, Outputs High.
Vee = MAX, Y'N = OV
14
mA
SGX5452B
11
11
14
13
17
mA
SGX5462, SGX5472
13
17
Supply Current, Outputs Low
Vee = MAX,-VIN =5V
71
SGX5452B
56
mA
71
56
SGX5462, SGX5472
61
76
mA
76
61
6 - 82
SG55452BI62172 SERIES
SWITCHING SPECIFICATIONS (Vee = 5V, TA = 25'C)
Parameter
SG55452B
SG55462
SG55472
SG75462
SG75472
SG75452B
Units
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
45
ns
26
35
45
65
65
Test Conditions
Propagation Delay Time, Lowto·High Level Output
Propagation Delay Time, High·
to-Low Level Output
Transition Time, Low-lo-High
Output
Transition Time, High·to·Low
Level Output
High-Level Output Voltage
After Switching
Ie = 200mA, e L = 15pF,
RL = 50n
Ie - 300mA,
Vs = 20V SGX5452B
Vs = 30V SGX5462
Vs = 55V SGX5472
24
35
30
50
30
50
ns
5
8
13
25
13
25
ns
7
12
10
20
10
20
ns
~s·6.5
mV
mV
mV
Vs-10
Vs-18
CONNECTION DIAGRAMS 8. ORDERING INFORMATION (See Notes Below)
Package
8-PIN CERAMIC DIP
Y-PACKAGE
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L- PACKAGE
Part No_
Ambient
Temperature Range
SG55452BY/883B
SG55452BY
SG55462Y/883B
SG55462Y
SG55472Y/883B
SG55472Y
SG75452BY
SG75462Y
SG75472Y
-55°C to 125°C
-55°C to 125'e
-55°C to 125°C
-55°C to 125°C
-55°C to 125°C
-55°C to 125°C
ooe to 70°C
ooe to 70°C
ooe to 70°C
SG55452BU883B
SG55452BL
SG55462U883B
SG55462L
SG55472U883B
SG55472L
-55°C to
-55°C to
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125'e
125°C
125°C
125°C
Connection Diagram
1
"
18 A
2 O7V28
1Y
3
6
2A
GND452Y
1. N.C.
2.1A
3. N.C.
4. N.C.
5.1B
6. N.C.
7.1Y
a. N.C.
9. N.C.
10.GND
3
2
1
20 19
'0"
5
17
".N.C.
12.2Y
13. N.C.
14. N.C.
15.2A
'
16
16. N.C.
7
15
8
14
17.2B
1a.N.C.
19. N.C.
20. Vee
9
10 11
12 13
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
3. Product is also available in flat pack. Consult factory for price and delivery.
Silicon General.
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
6 - 83
•
6 - 84
SG55453BISG554631SG55473
SG75453BISG 754631SG 75473
SILI[ON
GENERAL
DUAL PERIPHERAL POSITIVE-OR DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG554538/SG55463/SG55473 (SG754538/SG75463/SG75473)
series of dual peripheral Positive-OR drivers are a family of versatile
devices designed for use in systems that employ TTL or DTL logic. This
family of drivers are direct replacements for the Texas Instruments
SN554538/63173 (SN754538/63173) series. Diode-clamped inputs simplify circuit design. Typical applications include high-speed logic buffers,
power drivers, relay drivers, MOS drivers, line drivers, and memory drivers.
The SG554538/SG55463/SG55473 drivers are characterized for operation over the full military ambient temperature range of -55°e to 125°e and
the SG754538/SG75463/SG75473 drivers are characterized for operation
from ooe to 70 oe.
•
•
•
•
•
•
EQUIVALENT CIRCUIT SCHEMATIC (each driver)
300mA output current capability
High-voltage output
No output latCh-Up at 20V
High speed switching
TTL or DTL compatible diode-clamped inputs
Standard supply voltages
HIGH RELIABILITY FEATURES
- SG55453B/SG55463/SG55473
o Available to MIL-STD-883
o Scheduled for MIL-M-38510 QPL listing
o SG level "S"processing available
BLOCK DIAGRAM
Positive Logic: Y=A+B
2Y
2A
vee
4KO
1.6KO
4KO
28
1300
GND
1A
A
y
1B
1Y
B--r---~----~------~
L---~----~-------------4--~--~GND
FUNCTION TABLE (each gate)
A
B
V
L
L
L (on-state)
L
H
H (off-state)
H
L
H (off-state)
H
H
H (off-state)
H = High Level, L = Low Level
April 1990
6- 85
SG55453BI63173 SERIES
ABSOLUTE MAXIMUM RATINGS (Note t)
Supply Voltage (Vee) ............................................................. 7V
Input Voltage ...................................................................... 5.5V
Interemitter Voltage ............................................................ 5.5V
Off-state Output Voltage
X5453B Series ................................................................. 30V
X5463 Series ................................................................... 35V
X5473 Series .................................................................... 70V
Note 1. Exceeding these ratings could cause damage to the device.
Output Current .............................................................. 400mA
Continuous Total Dissipation at (or below)
25°C Free-Air Temperature ...................................... 800mW
Operating Junction Temperature
Hermetic (Y, L Packages) ........................................... 150°C
Storage Temperature Range ........................... -65°C to 150°C
Lead Temperature (1/16 inch from case
for soldering 60 sec.) .................................................. 300°C
THERMAL DERATING CURVES
2.5
5.0
2.0
'.0
.
~
~
~
13.0
15
a
~
<
6
"''(
~
~
,
~
~
~s.r-
~
IO~
r (e...,oIA,t
ijI (CO)
CtI?OIt))
05
0
~
,
~
5
~
25
50
75
100
"
~
125
150
0
175
AMBIENT TEMPERATURE - 'C
. ~'"
,~
\r\.
~
I-
1.0
~
0
2.0
'"
(c
~
0
25
50
75
100
CASE TEMPERATURE -
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
'-
125
·c
150
175
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Notes 2 & 3)
Supply Voltage (Vee)
Operating Ambient Temperature Range
SG55453B, SG55463, SG55473 ........................ 4.5V to 5.5V
SG55453B, SG55463, SG55473 .................. -55°C to 125°C
SG75453B, SG75463, SG75473 ........................ DoC to 70°C
SG75453B, SG75463, SG75473 .................... 4.75V to 5.25V
Note 2. Range over which device is functional.
Note 3. The substrate (pin 8) must always be at the most-negative device voltage for proper operation.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG55453B/463/473 with -55°C ST. S 125°C, and
SG75453B/463/473 with DOC ST. S7DoC. Typical values are tested at Vee =5V, and T. =25°C. Low duty cycle pulse testing techniques are used which
maintains junction and case temperatures equal to the ambient temperature.)
SG55453B
SG75453B
SG55463
SG75463
Parameter
Test Conditions
Units
SG55473
SG75473
~.
High-level Input Voltage (V IH )
Low-level Input Voltage (V IL)
Input Clamp Voltage (VIK)
High-level Output Current (lOH)
Low-level Output Voltage (VOL)
Input Current at Max VIN (liN)
High-level Input Current (IIH)
Low-level Input Current (IlL)
Supply Current, Outputs High
Supply Current, Outputs Low
Vee =MIN, liN = -12mA
Vee = MIN, VIH = 2V,
VOH =30V SGX5453B
VOH = 35V SGX5463
VOH = 70V SGX5473
Vee = MIN, VIL = 0.8V, 10L = 100mA
Vee =MIN, VIL = 0.8V,loL = 300mA
Vec = MAX, VIN =5.5V
Vee = MAX, VIN = 2.4V
Vee = MAX, VIN = O.4V
Vee = MAX, VIN = 5V
Vee = MAX, VIN = OV
SGX5453B
SGX5463
SGX5473
6 -86
Min. Typ. Max. Min. Typ. Max.
2
2
0.8
0.8
-1.2 -1.5
-1.2 -1.5
100
300
0.25
0.5
0.25
0.5
-1.0
8
0.5
0.8
1.0
40
-1.6
11
54
58
58
68
76
76
54
-1.0
8
58
58
V
V
V
I1A
0.4
0.7
1.0
40
-1.6
.11
V
V
mA
"68
76
mA
mA
mA
.76
I!A
mA
mA
SG55453BI63173 SERIES
SWITCHING SPECIFICATIONS (Vee = 5V, T. = 25°C)
Parameter
SG55453B
SG55473
SG55463
SG75453B
SG75463
SG75473
Units
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
30
18
25
55
30
55
ns
Test Conditions
Propagation Delay Time, Lowto-High Level Output
Propagation Delay Time, Highto-Low Level Output
Transition Time, Low-to-High
Output
Transition Time, High-to-Low
Level Output
High-Level Output Voltage
After Switching
Ie = 200mA, e L = 15pF,
RL =50n
Ic=300mA,
Vs = 20V SGX5453B
Vs = 30V SGX5463
Vs = 55V SGX5473
16
25
25
40
25
40
ns
5
8
8
20
8
20
ns
7
12
10
20
10
20
ns
mV
mV
mV
tvs-6.5
Vs-10
Vs-18
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
6-PIN CERAMIC DIP
V-PACKAGE
20-PIN CERAMIC
LEAD LESS CHIP CARRIER
L- PACKAGE
Part No.
Ambient
Temperature Range
SG55453BY/883B
SG55453BY
SG55463Y/883B
SG55463Y
SG55473Y/883B
SG55473Y
SG75453BY
SG75463Y
SG75473Y
-55°C to 125°C
-55°e to 125°e
-55°e to 125°e
-55°e to 125°e
-55°e to 125°C
-55°C to 125°e
ooe to 70 0 e
ooe to 70 0 e
DOC to 70 0
SG55453BU883B
SG55453BL
SG55463U883B
SG55463L
SG55473U883B
SG55473L
-55°e to
-55°e to
-55°e to
-55°e to
-55°e to
-55°e to
Connection Diagram
lAO.
V"
18
2
7
28
1Y
3
6
2A
GND452Y
e
125°e
125°e
125°e
125°e
125°e
125°e
1.N.C.
2.1A
a.N.c.
4. N.C.
S.lB
6.N.C.
7.1Y
B.N.C.
9.N.C.
10.GND
•
2
1
20 19
'0"
.
S
17
"
7
IS
•
I.
9
10 11 1213
11. N.C.
12.2Y
la.N.c.
14. N.C.
lS.2A
16. N.C.
17.2B
lB.N.C.
19.N.C.
20. Vee
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
3. Product is also available in flat pack. Consult factory for price and delivery.
Silicon General •
11661 Western Avenue. Garden Grove, CA 92641 • (714) 696-6121 • TWX: 910-596-1804. FAX: (714) 693-2570
6 - 87
6 - 88
SG55454BISG554641SG55474
SG75454BISG754641SG75474
SILICON
GENERAL
DUAL PERIPHERAL POSITIVE-NOR DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG55454B/SG55464/SG55474 (SG75454B/SG75464/SG75474) series of dual peripheral Positive-NOR drivers are a family of versatile devices
designed for use in systems that employ TTL or DTL logic. This family of
drivers are direct replacements for the Texas Instruments SN55454B/641
74 (SN75454B/64174) series. Diode-clamped inputs simplify circuit design.
Typical applications include high-speed logic buffers, power drivers, relay
drivers, MOS drivers, line drivers, and memory drivers. The SG55454BI
SG55464/SG55474 drivers are characterized for operation over the full
military ambient temperature range of -55°e to 125°e and the SG75454BI
SG75464/SG75474 drivers are characterized for operation from ooe to
70 oe.
•
•
•
•
•
•
EQUIVALENT CIRCUIT SCHEMATIC (each driver)
300mA output current capability
High-voltage output
No output latch-up at 20V
High speed switching
TTL or DTL compatible diode-clamped inputs
Standard supply voltages
HIGH RELIABILITY FEATURES
- SG55454B/SG554641 SG55474
• Available to MIL-STD-883
• Scheduled for MIL-M-38510 QPL listing
• SG level "S"processlng available
BLOCK DIAGRAM
Positive Logic: V
-r------'J
2A
,---_,_-----1"--~_,_----1"----
4KO
2KO
=A + B
2Y
Vee
2S
4KO
GND
1A
Y
1So----I
"'--------'--1Y
lKO
L-~--_+-----+_-+-~-~~--GND
FUNCTION TABLE (each gate)
A
B
Y
L
L
H (off-state)
L
H
L (on-state)
H
L
L (on-state)
H
H
L (on-state)
H = High Level, L = Low Level
January 1990
6- 89
SG55454B/64/74 SERIES
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Vee) ............................................................. 7V
Input Voltage ...................................................................... 5.5V
Interemitter Voltage ............................................................ 5.5V
Off-state Output Voltage
X5454B Series ................................................................. 30V
X5464 Series ................................................................... 35V
X5474 Series ...............................................,.................... 70V
Note 1. Exceeding these ratings could cause damage to the device.
Output Current .............................................................. 400mA
Continuous Total Dissipation at (or below)
25°C Free-Air Temperature ...................................... 800mW
Operating Junction Temperature
Hermetic (y, LPackages) ........................................... 150°C
Storage Temperature Range ........................... -65°C to 150°C
Lead Temperature (1/16 inch from case
for soldering 60 sec.) .................................................. 300°C
THERMAL DERATING CURVES
2.5
50
2.0
4.0
~
,
1.5
~
~
5
10
~
I 30
5
~~-
10"
~
~V
50
1.5
iiil
1.0
""
-
~
ia
BIAS
~
'(
SUPPLY VOLTAGE-(±V)
FIGURE 4.
SUPPLY CURRENT VS. SUPPLY VOLTAGE
20
'>c:
TA"'70'\: ,
TA.. 12S't
>-
i"
OFFSET
T
15
'""
15V
l"\A- 2S
V>
0.5
10
\
10
";;;z
10
>-
5
+:l:
........ ~ ::--...
20
ii';;;
0
20
15
..L.
30
15
FIGURE 3.
MINIMUM VOLTAGE GAIN
I
40
T,o\" 25°C
10
SUPPLY VOLTAGE-(±V)
FIGURE 2.
OUTPUT SWING VS. SUPPLY VOLTAGE
2.5
~
......
5
SUPPLY VOLTAGE-(±V)
FIGURE 1.
INPUT VOLTAGE RANGE VS. SUPPLY VOLTAGE
r
V
70'----'--~--~--~--~---J
SUPPLY VOLTAGE -(± V)
<'
E
82
76
0'----l._-'-_..I-_'----l._....1
5
10
15
20
2.0
,..,.,
88
0
-60
I
-20
20
0
60
TEMPERATURE-(OC)
FIGURES.
INPUT CURRENT VS. TEMPERATURE
7-7
100
140
10
0
15
20
OUTPUT CURRENT-(±mA)
FIGURE 6.
CURRENT LIMITING
25
30
SGIOIAISG201AISG301A
CHARACTERISTIC CURVES
120
,
r---r-,---r--r-----r--,,----,
,'~u IIIII Jill
16 r------r---r---r-T,-~2~50~C~
TA~:250C
VS=t.1SV
Vs ±15V
12 I----i~----i~--+_---i
J
\
1\
INPUT
I
L_
~,
~
\
\
OUTPUT
~ -2~-B\M-~~~(~~
1\
I-t--+~
'---i-I-t-H
l-t---i--i
-4
-6~~=1~~~~+-+-~
-8~~+-+-4-~-+-+-4---1~
_20L--L_L-~_~~_-L~
1
10
100
lK
10K
lOOK
1M
10M
1K
10K
FREQUENCY-(Hz)
100K
1M
10M
-10 L-.l-o-,"'0-:':20:-:'30::--C4LO"'5.l-0-6"'0-::':70:-:'80~
FREQUENCY-(Hz)
FIGURE 7.
OPEN LOOP FREQUENCY RESPONSE
FIGURE 9.
VOLTAGE FOLLOWER PULSE RESPONSE
FIGURES.
LARGE SIGNAL FREOUENCY RESPONSE
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
Ambient
Temperature Range
SG101AJ/883B
SG101AJ
SG201AJ
SG301AJ
-55°C
-55°C
-25°C
O°C
14-PIN PLASTIC DIP
N - PACKAGE
SG201AN
SG301AN
-25°C to 85°C
O°C 10 70°C
a-PIN METAL CAN
T-PACKAGE
SG101AT/883B
SG101AT
SG201AT
SG301AT
-55°C
-55°C
-25°C
O°C
14-PIN CERAMIC DIP
J - PACKAGE
to
to
to
to
125°C
125°C
85°C
70°C
10 125°C
to 125°C
to 85°C
to 70°C
Connection Diagram
[r;-=14p
N.C.
N.C. [ 2
13
OFFSET ADJUST [ 3
12
INVERTING INPUT [ 4
NON·INVERTING INPUT [ 5
11
10
v· [
6
9
N.C.
P
P
P v+
P
P
N.C.
COMPENSATION
OUTPUT
OFFSET ADJUST
[~P
N.C.
N.C.
COMPENSATION
OFFSET ADJUST
INVERTING INPUT
NON-INVERTING
INPUT
CD ® ® v+
® OUTPUT
® 8) ® OFFSET ADJUST
®
V·
10-PIN CERAMIC
FLAT PACK
F- PACKAGE
SG1 01 AF/883B
SG101AF
-55°C 10 125°C
-55°C to 125°C
===
c::::::
N.C. ~ 1
OFFSET ADJUST
2
INVERTING INPUT
3
=
=
=
=
N.C.
COMPENSATION
8 ===:::J V+
10
9
NON·INVERTING INPUT
4
7
V· =~_---t.:C5_ _ _
6r=-_
OUTPUT
OFFSET ADJUST
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
7-8
•
SG2101A
SILICON
GENERAL
ADDENDUM TO SG101A DATA SHEET
DUAL OPERATIONAL AMPLIFIERS
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG2101A is a dual version of the SG101A Operational
Amplifier and consists of two independent dice in the same
package.
•
•
•
•
•
Dual Independent SG101A
Offset voltage 3mV maximum over temperature
Input bias current 100nA maximum over temperature
Offset current 20nA maximum over temperature
Guaranteed drift characteristics
o Offsets guaranteed over entire common-mode range
The SG21 01 A is a general-purpose internally compensated
operational amplifier. It has excellent input bias current and drift
characteristics in addition to short circuit protection and is pin
compatible with industry standard operational ampliufiers.
HIGH RELIABILITY FEATURES - SG2101A
~
The SG21 01 A is guaranteed and fully characterized over the
full military ambient temperature range of -55°C to 125°C.
~
~
Available to MIL-STD - 883
MIL - M385l0 Il0l05BEA - JAN2l01AJ
SG level "S" processing available
OPERATING CONDITIONS & ELECTRICAL SPECIFICATIONS
(All information is identical to the SGl 01 A. Consult data sheet for specifics.)
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
16-PIN CERAMIC DIP
J- PACKAGE
Part No.
SG21 01 AJ/BB3B
SG2101AJ
Ambient
Temperature Range
-55°C to 125°C
-55°C to 125°C
Connection Diagram
+Vcc(A)
COMPENSATION (A)
OFFSET ADJUST (A)
• INPUT (A)
+ INPUT (A)
·V",
OFFSET ADJUST (B)
OUTPUT (B)
16-PIN CERAMIC
FLAT PACK
F- PACKAGE
SG21 01 AF/883B
SG2101AF
-55°C to 125°C
-55°C to 125°C
+V'" (A)
COMPo (A)
OFFSET ADJ. (A)
• INPUT (A)
+ INPUT (A)
-Vee
OFFSET ADJ. (B)
(A) OUTPUT
N.C.
(A) OFFSET ADJUST
(B) + INPUT
(B)-INPUT
(B) OFFSET ADJUST
(B) COMPENSATION
(B)+V",
(A) OUTPUT
N.C.
(A) OFFSET ADJ .
(B) + INPUT
(B) - INPUT
(B) OFFSET ADJ.
(B) COMPo
OUTPUT (B)~~--L.::......~~:.y-~~(B) +Vee
Note 1. Contact factory for JAN and DESC product availability.
2. All parts are viewed from the top.
January 1990
7-9
7 -10
8G10718G20718G307
SILICON
GENERAL
OPERATIONAL AMPLIFIER8
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1 07/207/307 is a general purpose internally compensated
operational amplifier. It has excellent input bias current and drift
characteristics in addition to short circuit protection and is pin
compatible with industry standard operational amplifiers.
• Offset voltage 3mV maximum over temperature
• Input current 100nA maximum over temperature
o Offset current 20nA maximum over temperature
• Guaranteed drift characteristics
o Offsets guaranteed over entire common mode
range
The SG107 is guaranteed and fully characterized over the full
military ambient temperature range of -55°C to 125°C while the
SG207 is electrically identical, except its performance is guaranteed from -25°C to 85°C. The 307 is designed for commercial
applications of O°C to 70°C.
HIGH RELIABILITY FEATURES - SG107
• Available to MIL-STD - 883
• SG level "S" processing available
SCHEMATIC DIAGRAM
OFFSET ADJUST
r-----~----~~------------~------------~--_CV+
INVERTING INPUT
O----------+-----+-----f
NON-INVERTING (}----------!----I
INPUT
OUTPUT
R8
1K
L--+~~--+-~----------~------------~--~--~----oV
R4
250
OFFSET
ADJUST
INVERTING INPUT
OUTPUT
NON-INVERTING INPUT
Optional Balancing Circuit
April 1990
7 -11
•
86107186207186307
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Votage
SG107/207 .................................................................... ±22V
SG307 .......................................................................... ±18V
Differential Input Voltage .................................................. ±30V
Input Voltage (Note 2) ...................................................... ±15V
Operating Junction Temperature
Hermetic (T, J, F Packages) ........................................ 150°C
. Plastic (N Package) .................................................... 150°C
Storage Temperature Range ............................ -65°C to 150°C
Output Short Circuit Duration (Note 3) ........................ Indefinite
Lead Temperature (Soldering, 10 Seconds) .................. 300°C
Note 1. Exceeding these ratings could cause damage to the device.
Note 2. For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
Note 3. Continuous short circuit is allowed for case temperatures to 125°C and ambient temperatures to 70°C.
THERMAL. DERATING CURVES
2.5...--...---,---r--,---r--""T'"-'"
1.01--1--'-
175
AMBIENT TEMPERATURE - "c
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION VB CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 4)
Supply Voltage
SG107/207 .......................................................... ±5V to ±20V
SG307 ................................................................ ±5V to ±15V
Note 4. Range over which the device is functional.
Operating Ambient Temperature Range
SG107 ............................................................ -55°C to 125°C
SG207 ............................................................... -25°C to 85°C
SG307 .................................................................. O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise stated, these specifications apply for the operating ambient temperature of TA = 25°C and for ±5V,;; V.';; ±20V. Low duty cycle
pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Input Offset Voltage
Test Conditions
RgS501
~
30
::J
10
10
/
15
0
1\
4
RL = 5KO
20
W
"<:~
40 60 100
0
......
200
/
TA '" +2S o C
"
-=
,
0
/
25
z
10K
-=-
if
30
5
o
400
V
o
±10
FREQUENCY (kHz)
±20
±30
±40
POWER SUPPLY VOLTAGE (Vdc)
FIGURE 1.
POWER BANDWIDTH
FIGURE 2.
PEAK OUTPUT VOLTAGE SWING VS. POWER SUPPLY VOLTAGE
+140
32
0
- "-
+120
~
z
+100
+80
~"
+60
+40
0
>
S
+20
z
w
-20
1.0
10
i'o..
24
tr
tr
::J
u
.~
20
16
I
12
r-
tr
0
I
III
::J
r0
4
0
- 50 -25
25
50
75 100 125
FIGURE 4.
OUTPUT SHORT-CIRCUIT CURRENT VS. TEMPERATURE
120
100
I"
8.0
........ 1-0.
'iD
~
BIAS
80
z
~
2.0
I""'-- .......
o
-
-55 -35 -15
25
45
±28V
100KO
20
OFFSET
5
vee =
Rl =
65
-55 -35 -15
85 105 125
TEMPERATURE (OC)
25
45
65
TEMPERATURE (OC)
FIGURES.
INPUT CURRENT
FIGURE 6.
VOLTAGE GAIN
7 -23
85 105 125
•
SG1431SG343
CHARACTERISTIC CURVES (continued)
5.0
Vl
1.0
:c
2.
'"'"::>
~
r---r--,---r--,---r--,---r--,--,
N
4.0
5
I-
1.5
1.0 I--t--t--t--t--t--t--t--t--l
Z
::>
Vs ::: ±2ay
Vs = ±2BV
o~~~~~~~I~I~
0~~~~~~~1~1~
-55 -35 -15
5
25
45
65
-55 -35 -15
85 105 125
5
25
45
65
85 105 125
TEMPERATURE (DC)
TEMPERATURE (OC)
FIGURE 7.
SUPPLY CURRENT
FIGURES.
UNITY GAIN BANDWIDTH
TYPICAL APPLICATIONS
'2
lOOK
?+28V
~
0-2
SG143
~~?'
VA~
L~7,.
R,
'OK
SG143
SWITCH
6
I
RJ
470
~,1.0~
SAMPLE
COMMAND
6
eOUT
5
0-+-,---"'-1' +
VB~
~
IP"Y',c",oot'c
110K
-2BV
• Dnft due to biaS current
is typically 8mV/s
FIGURE 9· VOLTAGE OFFSET
NULL CIRCUIT
FIGURE 11 • LOW·DRIFT SAMPLE AND HOLD
FIGURE 10· DIFFERENTIAL AMPLIFIER WITH ±20V
COMMON·MODE INPUT VOLTAGE RANGE
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
8-PIN METAL CAN
T·PACKAGE
Part No.
SG143T/883B
SG143T
SG343T
Ambient
Temperature Range
-55°e to 125°e
-55°e to 125°e
ooe to 70 0 e
Connection Diagram
N.C.
CD ® tV v+
®
® OUTPUT
NON·INVERTING ® ® ® OFFSET ADJUST
OFFSET ADJUST
INVERTING INPUT
INPUT
8·PIN CERAMIC DIP
Y-PACKAGE
SG143Y/883B
SG143Y
SG343Y
-55°e to 125°e
-55°e to 125°e
ooe to 70 0 e
OFFSET ADJUST
INVERTING INPUT
V·
O'
2
7
N.C.
V+
NON·INVERTING INPUT
3
•
OUTPUT
V·
4
5
OFFSET ADJUST
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
7 - 24
SG7411SG741C
SILICON
GENERAL
OPERATIONAL AMPLIFIER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
SG741 1741 C are pin compatible with the most widely accepted operational amplifiers and provide excellent performance fo a wide
range of applications. Tho SG741 is characterized for operation over
the full military ambient temperature range of -55°C to 125°C and the
SG741 C is designed for the commercial temperature range of O°C
to 70°C.
•
•
•
•
Complete short circuit protection
Offset voltage null capability
High common mode voltage range
High differential input voltage range
HIGH RELIABILITY FEATURES - SG741
• Available to MIL·STD • 883
• SG level "5" processing available
SCHEMATIC DIAGRAM
OFFSET ADJUST
r---~~----~r+------------~------------~---oV+
INVERTING INPUT
0---------+----+-----[
NON-INVERTING (}----------+----£
INPUT
OUTPUT
Rl
5K
~~~0rl~~~~------------+---------------+----4----+----ov-
OFFSET
ADJUST
INVERTING INPUT
OUTPUT
NON-INVERTING INPUT
Optional Balancing Circuit
April 1990
7 - 25
•
SG741/SG741C
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Votage
5G741 ..........................................................................
SG741C ........................................................................
Differential Input Voltage ..................................................
Input Voltage (Note 2) .......................................... ............
±22V
±IBV
±30V
±15V
Operating Junction Temperature
Hermetic (T, J, F Packages) ........................................ IS0°C
Plastic (N Package) .................................................... IS0°C
Storage Temperature Range ............................ -6SoC to IS0°C
Output Short Circuit Duration (Note 3) ........................ Indefinite
Lead Temperature (Soldering, ;0 Seconds) .................. 300°C
Note 1. Exceeding these ratings could cause damage to the device.
Note 2. For supply voltages less than ±15V, the absolute maximum input voltage is equallo the supply voltage.
Note 3. Continuous short circuit is allowed for case temperatures to 125°C and amient temperatures to 70°C.
THERMAL DERATING CURVES
2.5,--,----,----r--,--;-...,--,
1.0
/---/---t----=.....;;:-~~"'--t---/
0~0-~2~5-~50~~75~~~~~~-~175
175
AMBIENT TEMPERATURE - 'C
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 4)
Supply Voltage
SG741 ................................................................ ±SVto±20V
SG741C .............................................................. ±SV to ±ISV
Operating Ambient Temperature Range
SG741 .......................................................... -SsoC to 12SoC
SG741C .............................................................. 0°Ct070°C
Note 4. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise stated, these specifications apply for the operating ambient temperature of TA = 25°C, Vee = +15V, and VEE = -15V. Low duty
cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Input Offset Voltage
Input Offset Current
Input Offset Current
Input Bias Current
Input Bias Current
Input Resistance (Note 5)
Supply Current
Input Noise Voltage
Test Conditions
Rs S;10Kn
Rs s; 10Kn, TA = TMIN to TMAl(
TA = 12SoC
TA = -55°C
O°C S; TA S; 70°C
TA = 125°C
TA = -5SoC
O°C S; TA S; 70°C
f= 10Hz
f= 100KHz
Note 5. These parameters, although guaranteed, are not tested in production.
7- 26
SG741C
SG741
Typ. Max. Min. Typ. Max.
2
1
5
6
6.0
7.S
20
200
20
200
200
500
300
80
80
500
SOO
500
1500
BOO
2
0.3
2
0.3
1.7
1.7
2.B
2.B
5xl0·'6
5xl0" 6
2xl0· '6
2xl0· '6
Min.
Units
mV
mV
nA
nA
nA
nA
nA
nA
nA
nA
Mn
mA
\J2/Hz
V2/Hz
SG7411SG741C
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Test Conditions
Large Signal Voltage Gain
Output Voltage Swing
Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Vs =±15, VOIIT = ±10V, RL ;;:: 2Kn
TA = TMIN to TMAl(
TA = 25°C
Vs = ±15, RL = 10KQ
RL =2Kn
TA = TMIN to TMAl(
TA=TMINtoTMAX
Rs S 10KQ, TA = TMIN to TMAX
SG741C
SG741
Min. Typ. Max. Min. Typ. Max.
25
50
±12
±10
±12
80
15
25
±12
±10
±12
80
160
±14
±13
96
160
±14
±13
96
150
150
Units
V/mV
V/mV
V
V
V
dB
IJ.VIV
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
14-PIN CERAMIC DIP
J-PACKAGE
Part No.
SG741J/883B
SG741J
SG741CJ
14-PIN PLASTIC DIP
N- PACKAGE
SG741CN
8-PIN METAL CAN
T-PACKAGE
SG741T1883B
SG741T
SG741CT
Ambient
Temperature Range
-55°C to 125°C
-55°C to 125°C
O°C to 70°C
O°C to 70°C
-55°C to 125°C
-55°C to 125°C
O°C to 70°C
Connection Diagram
N.C.
OFFSET ADJUST
INVERTING INPUT
NON·INVERTING INPUT
V·
N.C.
N.C.
N.C.
4
5
9
OFFSET ADJUST
N.C.
OFFSET ADJUST '
'(
20
~
.y
-20
24
~
-120
-150
PHASE
>'
~
./
8
-8
~
./
./
4
-4
0
10K
lK
1M
lOOK
tOM
./
L
0
0
5
10
15
20
25
-5
0
SUPPLY VDLTAGE-(V)
FREQUENCY-(Hz)
FIGURE 1.
FREQUENCY RESPONSE
-10
-15
-20
-25
SUPPLY VOLTAGE-(V)
FIGURES.
NEGATIVE VOLTAGE SWING VS. SUPPLY VOLTAGE
FIGURE 2.
POSITIVE VOLTAGE SWING VS. SUPPLY VOLTAGE
,
350
~
;r
iil
250
15
" "-
!!i
-=<
"
"' r-....
in
~
=>
"z
150
I
I-
,.
r-....
it
iii
..,. ~
10
V"
V
6
............
3:
5
....... .......
""
4
.!.
1--1-""
SOU~
~
i
5
~N~
r-..
3
r-....
t- ..............
2
1
-75-50-25
a
25
50
75 lOa 125 150
-75-50-25
TEMPERAlURE-("C)
0
25
50
-75 -50 -25
75 100 125 150
TEMPERA lURE-( "C)
FIGURE 4.
INPUT BIAS CURRENT VS. TEMPERATURE
0
25
50
75
100 125 150
TEMPERAlURE-("C)
FIGURES.
SUPPLY CURRENT VS. TEMPERATURE
FIGURE 6.
CURRENT LIMIT VS. TEMPERATURE
APPLICATION INFORMATION
General usage of the SG1173 requires the same design and
layout considerations used with other op amps. Power supplies
should be adequately bypassed and clamped with Zener diodes
if transients are a problem. Leads to high impedance nodes
should be kept as short as possible to minimize undesirable inputoutput coupling or RF pick-up. In addition to these, the high
current capability of the SG1173 presents some new challenges
that a designer must be aware of. Special care should be taken
to avoid spurious feedback due to ground loops or voltage drops
in high current paths. Kelvin connections should be used when
applicable. When driving inductive loads, protection diode must
be used to clamp the output voltage to the power supplies
(Figure 7). This protects the amplifier from high voltage transients
caused by the stored energy in the inductor. Some loads may
require external load compensation. Examples of this are shown
in Figures 8 and 9. Safe operating area (SOA) is another area
where extreme care must be used. Simultaneous conditions of
high current and high voltage on the part may cause the junction
temperature to exceed the maximum rating. In any application,
the worst case power dissipations should be calculated and
adequate heat sinking must be provided.
RF
+ lis
f
o-~
0-
~4936
-~
~~~"'
1'-." ".,.,
RS
VIN ""
lN4936
1
~+
-Vs
-=
-
10
-=-
FIGURE B· INVERTING AMPLIFIER WITH RC LOAD COMPENSATION
FIGURE 7 • PROTECTION DIODES USED WITH INDUCTIVE LOAD
7 - 31
•
8G117318G217318G3173
APPLICATION INFORMATION (continued)
+vs
+Vs
r---.----.---o You T
TO .1/LF
MOTOR
RS
FIGURE 9 - NON-INVERTING AMPLIFIER WITH CAPACITIVE LOAD COMPENSATION
FIGURE 10 - MOTOR SPEED CONTROL WITH TACHOMETER FEEDBACK
A simple motor control loop is shown in Figure 10. This loop
regulates the speed of the motor by using a tachometer to
generate a voltage proportional to motor speed that is fed back to
the amplifier. If the speed of the motor is S rpm and the
proportionality constant of the tachometer is K volts/rpm then
The new op amp has the capability to drive a loudspeaker directly
allowing it to be used as an amplifier. Standard op amp
configurations can be used to design amplifiers with particular
values of closed loop gain or bandwidth. An example of such a
circuit is shown in Figure 11. This circuit utilizes the op amp in a
non-inverting gain configuration. The midband closed loop gain
is set by RF and Rs. The product of Rs and es set the lower 3dB
frequency. The upper 3dB frequency is a function olthe op amp's
bandwidth and closed loop gain. A capacitor in parallel with Rscan
be used to set the upper 3dB frequency to lower values if desired.
The speed of the motor is set by the input voltage VIN regardless
of the load on the motor. This is because the action of the
feedback loop forces the voltage on the motor to whatever value
is required to maintain the desired speed. If it is shaft position
rather than speed that needs to be regulated then the tachometer
may be replaced by some type of shaft encoder that generates a
voltage proportional to the position olthe motor shaft. In this case
the input voltage will set the shaft angle according to the relation
where co is shaft angle in degrees and H is the proportionality
constant of the shaft encoder in volts/degree.
FIGURE 11 - AUDIO AMPLIFIER
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
5-PIN TO-220 PLASTIC
P-PACKAGE
Part No.
SG2173P
SG3173P
Ambient
Temperature Range
Connection Diagram
-45°C to 85°C
ooe to 70°C
V'"
lflI!1I:::::- ~
v"
OUTPUT
~:::::::3 VEE(Substrate)
.
........... ~ ININ+
Case + Tab arelntemally
connected
5-PIN TO-66 METAL CAN
R- PACKAGE
SG1173R1883B
SG1173R
SG2173R
SG3173R
0
-55°C to 125°C
-55°C to 125°C
-45°C to 85°C
ooe to 70°C
V'"
OUTPUT~ ®
®
®
V"
IN+ ® CD IN.
0
Note 1. Contact factory for JAN· and DESC product availablity.
Silicon General •
CASE IS GROUND
Note: Case and tab are
internally connected to
substrate ground.
Note 2. All packages are viewed from the top.
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
7-32
SG15361SG1436
SILICON
GENERAL
HIGH-VOLTAGE OPERATIONAL AMPLIFIER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1536 series of monolithic amplifiers is designed specifically
for use in high voltage applications up to ±40V and where high
common-mode input ranges, high output voltage swings, and low
input currents are required.
These devices are internally
compensated and are pin compatible with industry standard
operational amplifiers.
•
•
•
•
•
High supply voltage capability
High output voltage swing
High common·mode voltage range
Internal frequency compensation
Input current 35nA maximum over temperature
HIGH RELIABILITY FEATURES
·SG1536
• Available to MIL·STD-883 and DESC SMD
• SG level "S" processing available
CIRCUIT SCHEMATIC
y+
R2
500
INPUT
500
Ra
1.5
L.....14-+--I::-(05
Q6
R2.
26
r-~-+----+---O
07':t--H~-+
02
INPUT
013
R.
7.7K
•
R7
R5
R6
R9
RIO
1K
39K
lK
7.7K
R'5
39K
R20
39K
y-
April 1990
7- 33
R2'
50
OUTPUT
S61536/S61436
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage
SG1536 ........................................................................ ±40V
SG1436 ....................................................................•... ±34V
Differential Input Signal ......•............................. ±(V+ + IV-I - 3) V
Common-Mode Input Swing ............................ ±V., -(IV-I - 3) V
Output Short Circuit Duration
(V+ = IV-I = 28V, Vo = OV) .......................................... 5.0sec
Operating Junction Temperature
Hermetic (T, V-Package) .............................................. 150°C
Storage Temperature Range .•.......................•.. -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL DERATING CURVES
2.5
5.0
2.0
'.0
~
I
~
~
r 3.0
'.5
ii
is
~
~
1\
1.0
I
~
>
(""At",
0.5
0
~
'.99
""10,')
0
~
"'r.
25
'-
50
2.0
i
iIIIo..
1\d)~
-&,.
' "
i~~~
'.0
"""" ~
75
"
\~
'00
~
125
'50
0
175
1"0
25
50
75
'00
~
125
150
'75
CASE TEt.lPERATURE - "C
AMBIENT TEMPERATURE - "c
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage
SG1536 ......•................................................................. ±28V
SG1436 ........................................................................ ±15V
Note 2. Range over which the device is functional.
Operating Ambient Temperature Range (T)
SG1536 .......................................................... -55°C to 125°C
SG1436 .............................................................. O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of T.= 25°C, and Vs = ±28V. Low duty cycle pulse testing
techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Test Conditions
Input Offset Voltage
TA = TMIN to TMAX
Input Offset Current
TA=TMIN
TA=TMAX
Input Bias Current
Differential Input Impedance
Common-Mode Input Impedance
Common-Mode Input Voltage
Range (Peak).
Common-Mode Rejection Ratio
Large Slg.,a1 VoHage Gain
Power Supply Rejection Ratio
Output Impedance
Short Circuit OutPut Current
Output ~oltage Swing (Peak)
=
TA TMIN to TMAI(
Open loop, :s: 5.0Hz
f:s:S.OHz
RL =1OKn,Vo = ±10V
RL =1OOKn,vo =±10V
TA =TMIN to TMAI(
V- constant, Rs :s: 10Kn
V· constant, Rs :s: 10Kn
f:s:5.0Hz
RL = 5.0 Kn, Vs = ±28V
R =5.0 Kn, V~ =±36V
7-34
SG1536
SG1436
Min. Typ. Max. Min. Typ. Max.
2.0
5.0
5.0
10
14
7.0
10
1.0 3.0
5.0
14
7.0
14
4.5
40
8.0
20
15
55
35
10
10
250
250
±25
110
200K
lOOK 500K
50K
15
100
15 100
1.0
±17
±22
±SO
±24
80
±25
100
200K
70K 500K
50K
35
35
1.0
±22
70
200
200
mV
mV
nA
nA
nk
nA
nA
Mn
Mn
V
dB
VN
VN
VN
IlVN
jJ.VIIJ
Kn
'mA'
:£17
±22
±30
Units
..
V
V-
-
SG15361SG1436
ELECTRICAL SPECIFICATIONS (continued)
Parameter
SG1536
SG1436
Min. Typ. Max. Min. Typ. Max.
Test Conditions
Av = +1, RL = 5.0KO, THO s 5%,
Power Bandwidth
23
1.0
2.0
50
18
Vo= 40V POp
Open loop
Unity gain
Open loop, unity gain
Unity Gain Crossover Frequency
Slew Rate
Phase Margin
Gain Margin
Equivalent Input Noise·
Av = 100, Rs = 10KO, f = 1.0KHz,
BW = 1.0 Hz
23
1.0
2.0
50
18
50
2.2
124
Powe! Supply Current
Power Consumption
50
2.6
146
4.0
224
Units
KHz
MHz
V/l1s
deg
dB
5.0
280
nVl-vHz
rnA
mW
CHARACTERISTIC CURVES
70
60
l-
!;
~
d>
,
50
fCF
3
""'
40
.....
30
1
!;
7
46
f-<> Vo
-28V
30
15
20
r
10
=>
0
r-....
a
4
6
10
20
40
100
r200
a
400
~
FREQUENCY (kHz)
±20
±30
'\.
+40
'"
+20
-20
±10
['\.
+60
w
'"
V
a
['\.
+80
z
1l
/
15
~
~
V
iO
10
+100
'"
/
~
=>
+120
/
RL=SKO
20
w
~
+140
V
25
TA" +25 Q C
l1
i;\
10K
r
S
,
35
±40
La
10
FREQUENCY (Hz)
FIGURE 2.
PEAK OUTPUT VOLTAGE SWING VS.
POWER SUPPLY VOLTAGE
FIGURE 3.
OPEN·LooP FREQUENCY RESPONSE
3.2
28 r--r-+--t--r-+--t--r-+~
w
"
;;;
2.8
ii"
0
2.4
N
-"r
2.0
z
w
"'"'
il
~
in
1.6
1.2
,
" "-
0.8
' ........
r
=>
"-
z
-50 -25
0
25
50
FIGURE 4.
OUTPUT SHORT-CIRCUIT CURRENT VS.
TEMPERATURE
t--
0.4
-so
75 100 125
AMBIENT TEMPERATURE (OC)
-25
a
25
50
75 100 125
AMBIENT TEMPERATURE (OC)
FIGURES.
INPUT BIAS CURRENT VS.
TEMPERATURE
7 - 35
I'
100 1.0K 10K 100K 1.0M 10M 100M
POWER SUPPLY VOLTAGE (Vdc)
FIGURE 1.
POWER BANDWIDTH
1'\
•
SG1536/SG1436
TYPICAL APPLICATIONS
R,
100K
+28V
+ Orift due to bios current
Is t:,picallyamV/s
FIGURE 6 - VOLTAGE OFFSET
NULL CIRCUIT
FIGURE 7 - DIFFERENTIAL AMPLIFIER WITH ±20V
COMMON-MODE INPUT VOLTAGE RANGE
FIGURE B - LOW-DRIFT SAMPLE AND HOLD
R,
lOOK
+28V
Vo =44Vp_p
RL== 5K
R,
lOOK
1K
RO=
R1RrC(RJ+R4}
R1(Rn;+R3) -R2R4
FIGURE 9 - TYPICAL NON-INVERTING Xl0 VOLTAGE
AMPLIFIER
FIGURE 10 - VOLTAGE CONTROLLED CURRENT SOURCE OR
TRANSCONDUCTANCE AMPLIFIER WITH 0 TO 40V COMPLIANCE
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
8-PIN METAL CAN
T- PACKAGE
Part No.
SG1536T/883B
SG1536T
SG1436T
'Ambient
Temperature Range
-55°C
-55°C
O°C
to 125°C
to 125°C
to 70°C
Connection Diagram
N,C,
CD ® ® v+
®
® OUTPUT
NON-INVERTING ® ® ® OFFSET ADJUST
OFFSET ADJUST
INVERTING INPUT
INPUT
8-PIN CERAMIC DIP
V-PACKAGE
SG1536Y/883B
SG1536Y
SG1436Y
-55°C
-55°C
O°C
to 125°C
to 125°C
to 70°C
OFFSET ADJUST
INVERTING INPUT
NON-INVERTING INPUT
V-
V-
0
2
7
3
•
4
5
N,C,
V+
OUTPUT
OFFSET ADJUST
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove. CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
7 - 36
SG217213172
SILICON
GENERAL
ADVANCED DATA SHEET
3 AMP POWER OP AMP
LINEAR INTEGRATED CIRCUITS
FEATURES
DESCRIPTION
The SG2172/3172 is a power monolithic operational amplifier capable of
operating with loads to 3A with a power supply range to 1av. Thermal
shutdown and current limit have been provided to insure reliable operation
during heavy loading. In addition, the SG2172/3172's high common mode
rejection, low input offsets, and high open loop gain rival those of much lower
power op amps. Another important feature not provided by competitive power
amps is the low quiescent current (7mA typically) enabling significant power
savings under no load conditions.
o
o
o
o
o
o
o
o
Low quiescent current
3.0A output current
Supply voltage range from 10V to 18V
Internally compensated
Thermal shutdown protection
Current limit protection
Functional replacements for ULN3751,
L 165, and LM675
Available in TO·220, TO·66 packages
The SG2172/3172 is ideal for use with voice coils in Winchester disk drives
and other linear servo applications.
EQUIVALENT CIRCUIT SCHEMATIC
Vee
NON-INV.
INPUT
INV.
INPUT
VOUT
+
Ql0
April 1990
7·37
D4
•
8621721863172
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (Vee-VEE) .................................................... 20V
Differential Input Voltage (Note 2) ....................................... ±20V
Common Mode Voltage (Note 2) ........................................ ±10V
Output Current ..........................................•...................... ±3.5A
Operating Junction Temperature
Hermetic (R-Package) .................................................. 150°C
Plastic (P-Package) ...................................................... 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to ground. All currents are positive into
the specified terminal.
THERMAL DERATING CURVES
Note 2. Eitheror both input voltages must not exceed the magnitude of Vco
orV".
5.0
50
4.0
.0
~
~
I
3.0
~
~
~
Ei
2.0
i
'~~
"
''''~
~
"'~,
~
0
50
<,-,< ~
75
30~3~
c;
20
i
100
"">
"'0
~4~
i
~
25
Ii
I
~~
'0
'«'V '.......
'0
0
~
~/~
'0
~
125
150
0
'75
0
25
50
75
~..,s~C'
~
100
125
150
175
AMBIENT TEMPERATURE - 'C
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Supply Voltage Range (Vee-VEE) .............................. 10V to 18V
Output Current (Continuous) ............................................ ±3.0A
Note 3. Range over which the device is functional.
Operating Ambient Temperature Range
SG2172 ............................................................ -45°C to 85°C
SG3172 .............................................................. O°C to 70°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG2172 with -45°C s T. s 85°C, SG3172 with
O°C ST.s 70°C, Vee = 6V, and VEE = -6V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to
the ambient temperature.)
5G2172/3172
Units
Test Conditions
Parameter
Min. Typ. Max.
V
10
Supply Voltage Range
18
tyee-VEE)
mA
7
12
Quiescent Drain Current
lour = 0
mV
10
Input Offset Voltage
Vour= OV, lOUT = 0
nA
Input Bias Current
1000
VOUT = OV, lOUT = 0
nA
TA= 25°C
500
nA
Input Offset Current
250
Vour = OV, lOUT = 0
nA
TA=25°C
200
V
2.5
Output Saturation Voltage
lOUT = -2A, Vee - Vour
... . .'
V
3.2
lOUT = +2A, VOUT - V!iIi.
A
5
Current Limit
VOUT= OV
dB
Common Mode Rejection Ratio
70
t;.VCM " 6V
dB
74
Power Supply Rejection Ratio
(Vee-VEE) = 10V to 14V
dB
80
Open Loop Voltage Gain
110
'our'" 0 .
0.5
Slew Rate
V/IlS
KHz
Gain Banawith Product
600
175
°C
Thermal Shutdown
~
~
7 - 38
SG2172/SG3172
CHARACTERISTIC CURVES
2.5
60
40
-120 ~
I
Z
,
~~
PHASE
ID
~
I
""
GAIN
20
-150
0
-160
-20
-210
-40
-240
e
~
1.5
z
E
\tC- VEE"'12V
2.0
0
3.5
I I I
E
-90
.....
I"'f-'"
-
~.
~
u
~
~
1.0
u
2.5
~
2.0
is
;=
15
~
a
.5
'95
5l
w
"~
;=
~
10K
1M
lOOK
10M
.5
1.0
1.5
20
SOURCE OUTPUT CURRENT -
2.5
5
3.0
0
200
~
ia
~
125
~
150
~
t'.
iD
r
=>
~
1.0
1.5
2.0
SINK OUTPUT CURRENT -
2.5
30
(A)
FIGURE 3.
SINK SATURATION VOLTAGE VS. OUTPUT CURRENT
14
225
175
.5
(A)
FIGURE 2.
SOURCE VOLTAGE VS, OUTPUT CURRENT
c
-
,-"""
I-'"
.....
0
0
FREOUENCY-(Hz)
FIGURE 1.
FREQUENCY RESPQNSE
'tC- V£E"'12V
1.0
"inz
0
1K
-c-
30
I
-I-'"
3
.!.
"
r-....
..........
100
--
~
z
75
50
-50 -25
0
25
50
75
~
a
>-
"
./
10
-
8
f/
6_
~
~
Ol
./
4
/
.."
2
100 125 150
-50 -25
TEMPERA TURE-( "c)
0
25
50
75
100 125 150
TEMPERATURE-(Oc)
FIGURE 4,
INPUT BIAS CURRENT VS, TEMPERATURE
FIGURES.
SUPPLY CURRENT VS. TEMPERATURE
APPLICATION INFORMATION
General usage olthe SG217213172 requires the same design and
layout considerations used with other op amps. Power supplies
should be adequately bypassed and clamped with Zener diodes
if transients are a problem. Leads to high impedance nodes
should be kept as short as possible to minimize undesirable inputoutput coupling or RF pick-up. In addition to these, the high
current capability of the SG2172/3172 presents some new
challenges that a designer must be aware of. Special care should
be taken to avoid spurious feedback due to ground loops or
voltage drops in high current paths. Kelvin connections should be
used when applicable. When driving inductive loads, protection
diodes must be used to clamp the output voltage to the power
supplies (Figure 7). This protects the amplifier from high voltage
transients caused by the stored energy in the inductor. Some
loads may require external load compensation. Examples of this
are shown in Figures 8 and 9. Safe operating area (SOA) is
another area where extreme care must be used. Simultaneous
conditions of high current and high voltage on the part may cause
the junction temperature to exceed the maximum rating. In any
application, the worst case power dissipations should be
calculated and adequate heat sinking must be provided.
RF
+vcc
r
o-K
W
0-
J
-\tE
RS
VIN
1N4936
4936
1
~~'M
-· I'~·" "".'
-VEE
-=-
-
FIGURE 7 - PROTECTION DIODES USED WITH INDUCTIVE LOAD
1 [)
-=-
FIGURE B· INVERTING AMPLIFIER WITH RC LOAD COMPENSATION
7-39
•
SG21721SG3172
APPLICATION INFORMATION (continued)
+Vcc
+Vcc
±
>----.----.---0 Vo UT
C=.01 TO .1,uF
MOTOR
RS
FIGURE 9 - NON-INVERTING AMPLIFIER WITH CAPACITIVE LOAD COMPENSATION
FIGURE 10· MOTOR SPEED CONTROL WITH TACHOMETER FEEDBACK
A simple motor control loop is shown in Figure 10. This loop
regulates the speed of the motor by using a tachometer to
generate a voltage proportional to motor speed that is fed back to
the amplifier. If the speed of the motor is S rpm and the
proportionality constant of the tachometer is K volts/rpm then
The new op amp has the capability to drive a loudspeaker directly
allowing it to be used as an amplifier. Standard op amp
configurations can be used to design amplifiers with particular
values of closed loop gain or bandwidth. An example of such a
circuit is shown in Figure 11. This circuit utilizes the op amp in a
non-inverting gain configuration. The midband closed loop gain
is set by RF and Rs' The product of Rs and es set the lower 3dS
frequency. The upper 3dS frequency is a function of the op amp's
bandwidth and closed loop gain. A capacitor in parallel with Rscan
be used to set the upper 3dS frequency to lower values if desired.
The speed of the motor is set by the input voltage VIN regardless
of the load on the motor. This is because the action of the
feedback loop forces the voltage on the motor to whatever value
is required to maintain the desired speed. If it is shaft position
rather than speed that needs to be regulated then the tachometer
may be replaced by some type of shaft encoder that generates a
voltage proportional to the position of the motor shaft. In this case
the input voltage will set the shaft angle acconding to the relation
where co is shaft angle in degrees and H is the proportionality
constant of the shaft encoder in volts/degree.
FIGURE 11 - AUDIO AMPLIFIER
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
5-PIN TO-220 PLASTIC
P-PACKAGE
Part No.
SG2172P
SG3172P
Ambient
Temperature Range
Connection Diagram
-45°C to 85°C
ooe to 70°C
V"
OUTPUT
VEE(Substrate)
INV.INPUT
NON-INV.INPUT
Case + Tab are Intemally
connected to VEE
5-PIN TO-66 METAL CAN
R- PACKAGE
SG2172R
SG3172R
o
-45°C to 85°C
ooe to 70°C
V"
OUTPUT @)
NON·INV. INPUT
®
o
Note 1. Contact factory for JAN and DESC product availablity.
®)t"
®
V
-4
,
vs~~rvc
100
/
-2
-6
0~~:;~ovC
/
D
'"
150
10
100
IK
10K
1M
lOOK
10 2
lmA
10'
z
""
FIGURE4.
1
9
~
5
,
8
7~
6
~
-
I- .::::: r-
-
._._-
-
""
0
0
10 6
"~
'z-'
5
4
0
I
J
0
w
2
1
--
I-- - - -
4
2
14
15
SUPPLY VOLTAGE '{:c-VEE -
5
(v)
I--
0
TA=250C
VS=±6V
125
10
.75
5
.25
-...-
SOURCE
I-"' I-"'
V
V
'--'
...- I-"'
-
I-"'
...- I---' .....-
SINK
0
0
10 20
30
40
50
60
70
80 90 100
0
TEMPERA TURE - (Oe)
200
400
500
LOAD CURRENT -
FIGURE 6.
FIGURE 7.
800
(mA)
SATURATION VOLTAGE VS. LOAD CURRENT
SUPPLY CURRENT VS. TEMPERATURE
7·43
8
10
12
FIGURE 6.
SUPPLY CURRENT VS. SUPPLY VOLTAGE
1.5
,
r
~
~
2
m
f'...
(Hz)
>
I-I-
0
u
3
~
~
10 5
10'
I-
VS=±6V
4
0>-
""-
FIGURE 5.
10
TA~~5°C
0
U
OPEN LOOP GAIN VS. FREQUENCY
POWER SUPPLY REJECTION VS. FREQUENCY
..- V
5
'"OC
FREQUENCY -
(Hz)
FR:::CU[NCY
..s.
,
u
u
0
0
6
<
t--
1000
18
SG3272
APPLICATION CIRCUIT
VCC
12V
J:
R2'
LINEAR
ACTUATOR
2.5KO
~2
Rg
~G327
36KO
R7
3.3KO
,--------1
-fi:'.-
R, •
C3
~ 0.221'F
I
I""
0.470
R10
10
V+1-
VCC/2
''~
'" l
",I
I RA
LA
I
L ________ J
R6
10KO
R4'
2.5KO
R3*
36KO
C, T
BUFFERED DAC
INPUT VOLTAGE
RS
R5
10KO
3.3KO
R"
0.22/'F
10
C2T 0.221'F
nh
* 1% TOLERANCE
GROUND
FIGURE 9 • 3.5·INCH WINCHESTER DISK DRIVE HEAD POSITION CONTROL AMPLIFIER
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
SG3272M
8·PIN PLASTIC
M· PACKAGE
Ambient
Temperature Range
Connection Diagram
oDe to 700e
OUTPUT A
1 ' V ' I I INVINPUTA
7 I NON-INV INPUT A
6 I NON-INV INPUT
Vee
OUTPUTB
.,
VEE (GND)
4
.2
I INV INPUT B
5
.1
20·PIN PLASTIC WIDEBODY
BATWING S.O.I.C.
DWW - PACKAGE
SG3272DWW
O°Cto 70°C
V" 0:
OUTPUTB 0:
1
,
2
20 ~ OUTPUT A
19~
N.C.
7
{'
N.C. 0:
8
'3
INV INPUT B 0:
NON-INV INPUT B 0:
9
'2 :0 INV INPUT A
10
11 I l NON-INV INPUT A
N.C. 0:
4
5
V,,(GND) [
6
16
15
Vee (GND)
14
I l N.C.
Note 1. All packages are viewed from the top.
Silicon General .
11861 Western Avenue· Garden Grove. CA 92641 • (714) 898·8121 • TWX: 910·596·1804 • FAX: (714) 893·2570
7·44
THUMB INDEX
SILICON
GENERAL
•
I
TABLE OF CONTENTS
•
I
PART NUMBER INFORMATION
•
I
GENERAL INFORMATION
III
POWER SUPPLY CIRCUITS
•
I
MOTION CONTROL CIRCUITS
•
I
POWER DRIVER AND INTERFACE CIRCUITS
•
I
OPERATION AMPLIFIERS AND COMPARATORS
I
CORE MEMORY CIRCUITS
I
AUTOMOTIVE CIRCUITS
•
III
II I
II I
lEI I
OTHER CIRCUITS
PACKAGE INFORMATION
APPLICATION INFORMATION
SALES OFFICES
8 -1
SELECTION GUIDE
SILICON
GENERAL
CORE MEMORY
SENSE AMPLIFIER
LINEAR INTEGRATED CIRCUITS
Device Type
:':-0
Description.
Key Features
Packages
Dual sense amplifier
• Adjustable input threshold level
.,
SG5524
,
·
J,F
High speed
• TIL or DTL drive compatibility
• Standard logic supply voltage
SG5534
,
Dual sense amplifier
• Adjustable input threshold level
J
• High speed
• TIL or DTL drive compatibility
• Supply Currents
(+Iccl < -20mA
(-ICC> < lBmA
SG55234
Dual sense amplifier
SG55234A
• Adjustable input threshold level
J, F
• High speed
• TIL or DTL drive compatibility
• Standard logic supply voltage
• Threshold voltage matching (L1VTHl:
.SG55236
·SG55236A
Dual sense amplifier I data registers
SG55234
3mV
SG55234A
1.5mV
,
• Threshold voltage matching (L1VTHl:
SG55236
1.5mV
SG55235A
O.BmV
• Adjustable differential-input threshold voltage
• Reference amplifier inherently stable with no external frequency
compensation required
• Built-in data buffer drives 450pF load in 15ns
• Internal reference voltage attenuator makes reference amplifier
less sensitive to noise
January 1990
8-2
F
HE
SELECTION GUIDE
SILICON
CORE MEMORY
GENERAL
MEMORY DRIVERS
LINEAR INTEGRATED CIRCUITS
Device Type
Description
IO{PK)
IO(CONl)
Vc
SG55325
Dual sourcel
0.75A
0.6A
24V
SG75325
Dual sink
Key Features
V cc #1 V cc #2
7V
24V
• Two open emitter, two open collector output
Packages
J, N, F
stages
• Output clamp circuitry on sink transistors
memory driver
• Source base drive externally adjustable
• Fast switching time
• TIL or DTL compatibility
• MIL-M-38510 113001 BEA
QPL
SG55326
Quad sink
SG75326
memory driver
0.75A
0.6A
24V
7V
o
JAN55325J
Four open collector outpul stages
J,N, F
• Output clamp circuitry on all outputs
o
Output transistor base drives externally adjustable
• Fast switching time
o
o
TIL or DTL compatibility
MIL-M-38510 113002 BEA
QPL
SG55327
Quad source
SG75327
memory driver
0.75A
0.6A
24V
7V
24V
JAN 55326J
• Four open emitter output stages
• Can operate as a sink driver
o
Output transistor base drives externally adjustable
• Fast switching time
• TIL or DTL compatibility
December 1988
8-3
J,N, F
SELECTION GUIDE
SILICON
CORE MEMORY
GENERAL
DIODE ARRAYS
LINEAR INTEGRATED CIRCUITS
Device Type
SG576815768A
SG5nO/5770A
. Circuit Diagram
°HHHU
°HHHH
SG577215772A
SG577415n4A
JID[[
SG25768
SG25nO
°HHHHHfU
°HHHHfHH
SG6496/6496A
December 1989
8-4
Key Features
• 60V minimum breakdown voltage
• 500mA current capability per diode
• Maximum reverse recovery time
(t.) of 20ns
• Maximum forward recovery time
(t.) of 40ns
• Reverse current (IR) < 100nA
• JANTXV. JANT« & JAN parts
available
• SG level "S" processing available
• MIL-S-19500/474 QPL parts
available
1N5768
1N5770
1N5772
• Available in hermetic ceramic
DIP (J) and flat (F) packages
SELECTION GUIDE
CORE MEMORY
DIODE ARRAYS
Device Type
SG3212
Circuit Diagram
~
Key Features
• 60V minimum breakdown voltage
• 1A current capability per diode
• Fast switching speeds: typically
less than 15ns
• Low leakage current
~
~
~
SG61 00
SG6101
iHHH
HHHH
8-5
• 75V minimum breakdown
voltage
• 1OOmA current capability per
diode
• Switching speeds less than 5ns
• Low leakage current < 25nA
8-6
H
M±W
SG3212
SILICON
GENERAL
DUAL DIODE BRIDGE
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The Silicon General dual diode bridge features high breakdown and low
forward voltage.
• 60V minimum breakdown voltage
• 1A current capability per diode
• Fast switching speeds: typically less than
15ns
• Low leakage current
Individual diodes within the bridge have 60V minimum breakdown voltage,
can handle 1A of current and typically switch in less than 15 nanoseconds.
The dual bridge configuration is available in ceramic DIP or ceramic flatpack
and can be processed to JANTXV, JANTX, or JAN flows at Silicon General's
MIL-S-19500 facility.
CIRCUIT DIAGRAM
.-----{13
4}--------'
•
April 1990
8-7
SG3212
ABSOLUTE MAXIMUM RATINGS (Note 1 & 2)
Breakdown Voltage (VBA) .................................................... SOV
Output Current (10)' Tc = 25°C
Continuous ......................................................................... 1A
Operating Junction Temperature
Hermetic (J, F Packages) ............................................. 150°C
Storage Temperature Range ............................. -S5°C to 200°C
Lead Temperature (Soldering, 10 Seconds) .................... 300°C
Note 1. Exceeding these ratings could cause damage to the device.
Note 2. Applicable for each diode.
THERMAL DERATING CURVES
2.5
5°1~
2.0
4.0
~
~
,
1.5
~
~
10
~
""~
'"
" ...... "',<,~ ~
0
20~
-,~t,
r"
05
0
25
50
75
'\
30
100
----
~
125
150
10--
0
175
0
~
'~
'%.
~
25
~
~
'ir
--<"'<£tr
50
75
100
~
125
150
175
CASE TEMPERAllJRE - "C
AMBIENT TEMPERATURE - "C
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
MAXIMUM POWEA DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Operating Ambient Temperature Range
SG3212 ........................................................ -55°C to 150°C
Note 3. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of T. = 25°C for each diode. Low duty cycle pulse
testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Test Conditions
Parameter
Breakdown Voltage (VaR)
Forward Voltage (VF)
Reverse Current (IR)
Capacitance (C) (Note 4)
Forward Recovery Time (Iu)
(Note 4)
Reverse Recovery TIme (t")
(Note 4)
IR=10~
Duty Cycle S 2%, 300 Jls pulse
IF= lmA
IF= 10mA
IF= 100mA
IF = 200mA
IF=500mA
IF = lA
IF = 10mA, TA = -55°C
VA =40V
VR= 4OV, TA = 150°C
Vfj = OV, f = lMHz, Pin-to-pin
SG3212
Units
Min. Typ. Max.
SO
75
V
0.S2
0.74
0.92
1.0
1.2
1.5
1.0
100
50
9
V
V
V
V
V
V
V
nA
~
pf
15
2
IF = 500mA, trs 15n5, Vfr = 1.SV, Rs = 50n
10
40
ns
IF = IA = 200mA, i" = 20mA, RL = lOOn
7
20
ns
Note 4. The parameters, although guaranteed, are not 100% tested in production.
8-S
SG3212
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
14-PIN CERAMIC DIP
SG3212J/883B
J - PACKAGE
SG3212J
Ambient
Temperature Range
-55°C to 150°C
-55°C to 150°C
Connection Diagram
14
13
12
11
10
14-PIN CERAMIC FLATPACK
F - PACKAGE
SG3212F/883B
SG3212F
-55°C to 150°C
-55°C to 150°C
14
13
12
11
10
•
Note 1. Consult factory for other packages available.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove. CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
8-9
8 -10
SG5524
SILICON
GENERAL
DUAL SENSE AMPLIFIER
LINEAR INTEGRATEO CIRCUITS
DESCRIPTION
FEATURES
The SG5524 is a monolithic, dual channel sense amplifier designed
for high speed magnetic memory systems. The sense amplifier
inputs can detect low-level differential signals. An adjustable input
threshold level (VREF) allows the designer to tailor the device to suit
a specific application. The outputs are TTUDTL compatible and
feature separate strobes for individual channel control.
•
•
•
•
HIGH RELIABILITY FEATURES - SG5524
The SG5524 is characterized over the full military ambient
temperature range of -55°C to 125°C and is available in both 16-pin
ceramic DIP and 16-pin flatpack packages.
BLOCK DIAGRAM
INPUT 1A1
INPUT 1A2
• Available to MIL-STD·883
• SG level "s" processing available
:t>-------
~ OUTPUT1W
L_--l
+VREF:t2:
. -VREF
STROBE 1S
I
--+
-
I
:=[>______
~STROBE
r---J
INPUT 2A1
Adjustable input threshold voltage
High speed
TTL or DTL drive compatibility
Standard logic supply voltage
_
OUTPUT 2W
INPUT 2A2
POSITIVE LOGIC: W=AS
FUNCTION TABLE
INPUTS
A
S
H
H
L
X
X
L
OUTPUT
w
H
L
L
Definition of Logic Levels
INPUT
H
L
X
A*
VIC?' V TMAX
VIC::; V TMIN
Irrelevant
S
VI
VI ::; V il MAX
Irrelevant
?
V IH MIN
• A is a differential voltage (V,O) between Aland A2.
Forthese circuits, V,O is considered positive regardless of which terminal is positive with respect to the
other.
April 1990
8 -11
2S
SG5524
ABSOLUTE MAXIMUM RATINGS (Notel)
Supply Voltage (+Vee) (Note 2) ............................................ 7.0V
Supply Voltage (-Vee) (Note 2) ........................................... -7.0V
Differential Input Voltage .................................................... ±5V
Voltage Frol)l Any Input to Ground (Note 3) ........................ 5.5V
Off-state Voltage Applied to Open-Collector Outputs ......... 5.5V
Storage Temperature Range ............................. -65°C to 150°C
Operating Junction Temperature (Te)
Hermetic (J, F-Packages) ............................................. 150°C
Lead Temperature (Soldering, 10 seconds) .................... 300°C
Note I. Values beyond which damage may occur.
Note 2. Voltage values, except differential voltages, are with respect to network ground terminals.
Note 3. Strobe and gate input voltages must be zero or positive with respect to network ground terminal.
THERMAL DERATING CURVES
25
5.0
20
40
~
~
11.5
~
i5
1.0
i
"
~
13.0
'~
~
~
~
'~i~
'I.,.
"'c.t;
25
'\I¥.
i
0.5
0
1,\
50
75
is
"~
100
~
~
150
°0
175
°
At.4BIENT TEMPERA.TURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
.........
"'PIIv
1.0
125
~
~ ~C!r) "
,,~
2.0
"
...........
25
"
75
i'- ~
100
125
150
175
CASE TEMPERATURE - "C
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 4)
Supply Voltage (+Vee ) ....................................... 4.75V to 5.25V
Supply Voltage (-Vee) ...................................... -4.75V to -5.25V
Reference Voltage (VREF) ................................... 15mV to 40mV
Operating Ambient Temperature Range:
SG5524 ......................................................... -55°C to 125°C
Note 4. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambienttemperatures for SG5524 with -55°C", T. '" 125°C, +Vcc = 5V, and
-Vco = -5V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Static Section
Differential Input Threshold Voltage (VT)
Common Mode Input Firing VoHage (VICF)
(Note 5)
Differential Input Bias Current (liB)
Differential Input Offset Current
High Level Input Voltage (Strobe Inputs) (V,H)
Low Level Input Voltage (Strobe Inputs (V,l)
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
High Level Input Current (Strobe Inputs) (I'H)
Low Level Input Current (Strobe Inputs) (I'l)
Test Conditions
VREF =15mV
VREF =40mV'
VAEF .. 40 mV, V'IS) = V'H ' TA =25°C
. Common Mode input pulse:
t, s 15ns, \ S 15ns, t., S 50ns
+Vee = 5.25V, -Vee =-5.25V, V,O = OV
TA = -55°C to O°C
TA =O°C to 125°C
+Vee = 5.25V, -Vee = -5.25V, V,O = OV,
TA = 25°C
SG5524
I
I
I Min. Typ. Max. I Units
10
35
15
40
20
45
±2.5
V
100
75
IIA
IIA
0.8
0.5
4.0
0.25
0.4
I1A
V
V
V
V
-1.0
40
.1.0
-1.6
mA
rnA
2
+Vee = 4.75V, -Vee = -4.75V, IOH .. -0.4 mA
+Vee =4:75V, -Vee =-4.75V, IOl =16 rnA
+Vee =5.25V, -Vee = -5.25V
V,H = 2.40V
V,H =5.25V
+Vee = 5.25V, -Vee = -5.25V, V'l = 0.4V
8 -12
2.4
mV
mV
IIA
SG5524
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Static Section (continued)
Short Circuit Output Current (los)
Supply Current from +Vcc (+Icc)
Supply Current from -Vee (-Icc)
Test Conditions
I
I+Vcc - 5.25V. -Vee - -5.25V. TA - 25:C
+Vcc = 5.25V, -Vee = -5.25V, TA = 25 C
+Vcc = 5.25V. -Vee = -5.25V. T = 25°C
Parameter
Dynamic Section
Propagation Delay Times From A 1-A2 to W
Low to High (TPLH)
High to Low (TPHL)
Propagation Delay Times From Strobe to W
Low to High (TPLH)
High to Low (TPHL)
Test Conditions
I
SG5524
I
I Min. I Typ. I Max. I
Units
I 25
21
1- .
1-!o51
-15
-20
mA
mA
mA
I
SG5524
I Units
I Min. Typ. Max. I
C L=15pF. RL=288n, C EXT > 100pF. TA = 25°C
25
20
40
ns
ns
15
20
30
ns
ns
C L=15pF, RL=288n. C EXT ; 100pF, TA = 25°C
Note 5. Common-mode input firing voltage is the minimum common-mode voltage that will exceed the dynamic range of the input at the specified
conditions and cause the logic output to switch. The common·mode input signal is applied when the strobe is high.
TYPICAL APPLICATION
+5Y
I
+Ycc
C:::;I-r--t-{;
+VREF
>--vVv--__._-op-----(
- YREF
>--VVv----O------(3)--J:;..-
~
,--------{j15 STROBE #1
SENSE LINE #1
OUT #1
+Ycc
SENSE LINE #2
, -_ _ _ _~1}1-ST-R-O-BE<#2
~
OUT #2
C:::;I-r--t-{
POWER
GND
-5Y
8 -13
SG5524
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Note Below)
Package
16-PIN CERAMIC DIP
J - PACKAGE
Part No_
SG5524J/883B
SG5524J
Ambient
Temperature Range
-55°C
-55°C
Connection Diagram
to 125°C
to 125°C
Cm
INPUT1A1
INPUT 1A2
-v~
+VREF
INPUT2A1
INPUT2A2
-Vee
16-PIN CERAMIC
FLAT PACK
F- PACKAGE
SG5524F/883B
SG5524F
-55°C
-55°C
to 125°C
to 125°C
C",
+Vcc
STROBE 1S
OUTPUT 1W
GND2
OUTPUT2W
STROBE 2S
N.C.
GND1
INPUT 1A1
INPUT 1A2
+Vcc
STROBE 1S
OUTPUT1W
GND2
+VREF
OUTPUT 2W
INPUT 2A 1
INPUT 2A2
STROBE 2S
N.C.
-Vee ----.--C--_ _~~--- GND 1
Note 1. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove. CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
8 -14
GENERAL
SG5768168A, SG5770170A, SG5772172A, SG5774174A
SG25768, SG25770,
SG6496196A
LINEAR INTEGRATED CIRCUITS
DIODE ARRAY CIRCUITS
SILI[ON
DESCRIPTION
FEATURES
The Silicon General series of diode arrays feature high breakdown, high
speed diodes in a variety of configurations.
• 60V minimum breakdown voltage
• 500mA current capability per diode
• Fast switching speeds: typically less than
10ns
• Low leakage current
Each array configuration consists of either common anode diodes, common
cathode diodes, or a combination of common anode and common cathode
diodes.
HIGH RELIABILITY FEATURES
Individual diodes within the array have 60V minimum breakdown voltage, can
handle 500mA of current and typically switch in less than 10 nanoseconds.
Each of the array configurations is available in ceramic DIP or ceramic
flatpack and can be processed to JANTXV, JANTX, or JAN flows at Silicon
General's MIL-S-19500 facility.
CIRCUIT DIAGRAMS
• MIL-S-19500/474 QPL - 1N5768
- 1N5770
- 1N5772
- 1N5774
• JANTXV, JANTX & JAN available
• SG level "S" processing available
°Hnnn
°nnnn
COMMON CATHODE
SGS7661SGS768A
COMMON ANODE
SGSnOlSGSnOA
COMMON ANODE I COMMON CATHODE
SGsn2lSGSn2A
DUAL COMMON ANODE I COMMON CATHODE
SGS7741SGSn4A
°HHHHfHH °HHHHHfH
COMMON CATHODE
SG25768
COMMON ANODE
SG2SnO
DUAL COMMON ANODE I COMMON CATHODE
SG6496JSG6496A
April 1990
8-15
•
DIODE ARRAY SERIES
ABSOLUTE MAXIMUM RATINGS (Note 1 & 2)
Breakdown Voltage (VeA) .................................................... 60V
Output Current (10)' Tc = 25°C
Continuous ................................................................. 500mA
Operating Junction Temperature
Hermetic (J, F Packages) ............................................. 150°C
Storage Temperature Range ............................. -65°C to 200°C
Note i. Exceeding these ratings could cause damage to the device.
Note 2. Applicable for each diode.
THERMAL DERATING CURVES
2.5 r--;---r--,---r---,---,----,
~
~
~
~
C
~
~
i
2.0
~
i
175
AMBIENT TEMPERATURE - 'C
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Operating Ambient Temperature Range
SG5768, SG5768A ...................................... -55°C to 150°C
SG5770, SG5770A ...................................... -55°C to 150°C
SG5772, SG5772A ...................................... -55°C to 150°C
Note 3. Range over which the device is functional.
Operating Ambient Temperature Range
SG5774, SG5774A ........................................ -55°C to
SG25768 ........................................................ -55°C to
SG25770 ........................................................ -55°C to
SG6496, SG6496A ........................................ -55°C to
150°C
150°C
150°C
150°C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating temperature ofT. = 25°C for each diode. Low duty cycle pulse testing techniques
are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
-Breakdown Voltage (VeA)
Forward Voltage (VF)
Reverse Current (IA)
Capacitance (C) (Note 4)
Forward Reco~ery Time (~r)
(Note 4)
Reverse Recovery Time (tIT)
(Note 4)
Test Conditions
IA = 10J,1A
Duty Cycle s 2%, 300 ~s pulse
IF= 100mA
IF = 200mA
IF=500mA
IF = 10mA, TA = -55°C
VR =40V
VA = 40V, TA = 150°C
VR = OV, f = 1MHz, Pin-to-pin
SG5768A
SG5768
SG25768
Min. Typ. Max. Min. Typ. Max.
60
60
Units
V
4
1.0
1.1
1.5
1.0
100
50
4
V
V
V
V
nA
J,1A
pf
IF = 500mA, trs 15n8, V~ = 1.8V, Rs = 50n
40
40
ns
IF = IR = 200mA, iIT = 20mA, R = 100n
20
20
ns
Note 4. The parameters, although guaranteed, are not 100% tested in production.
8 -16
1.0
1.1
1.3
1.0
100
50
DIODE ARRAY SERIES
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Breakdown Voltage (VBR)
Forward Voltage (V F)
Reverse Current (IR)
Capacitance (C) (Note 4)
Forward Recovery Time (tl,)
(Note 4)
Reverse Recovery Time (trr)
(Note 4)
Parameter
Breakdown Voltage (VBR )
Forward Voltage (VF)
Reverse Current (I R)
Capacitance (C) (Note 4)
Forward Recovery Time (~,)
(Note 4)
Reverse Recovery Time (trr)
(Note 4)
Test Conditions
IR = 10llA, 1OOms pulse, ~ 20% Duty Cycle
Duty Cycle ~ 2%, 300 Ils pulse
IF= 100mA
IF= 200m A
IF= 500mA
IF = 10mA, TA = -5SoC
VR=40V
VR= 40V, TA = 150°C
VR= OV, I = 1MHz, Pin-to-pin
SGS770A
SGS770
SG2S770
Min. Typ. Max. Min. Typ. Max.
60
60
IF = SOOmA, I, ~ 1Sns, VI' = 1.8V, Rs = son
IF = IR = 200mA, iff = 20mA, RL = 100n
Test Conditions
IR = 10llA, 100ms pulse, ~ 20% Duty Cycle
Duty Cycle ~ 2%, 300llS pulse
IF= 100mA
IF = 200mA
IF = 500mA
IF = 10mA, TA = -55°C
VR=40V
VR= 40V, TA = 150°C
VR= OV, I = 1MHz, Pin-to-pin
IF=500mA,t,~
7
IF = IR = 200mA, iff = 20mA, RL = 100n
8 -17
7
V
1.0
1.1
1.3
1.0
100
50
8
1.0
1.1
1.S
1.0
100
50
8
V
V
V
V
nA
IlA
pi
40
40
ns
20
ns
20
7
SG6496A
SG6496
SGS772
SGS772A
SGS774A
SGS774
Min. Typ. Max. Min. Typ. Max.
60
60
15ns, Vfr= 1.8V, Rs=50n
Units
Units
V
1.0
1.1
1.3
1.0
100
SO
8
1.0
1.1
1.5
1.0
100
50
8
V
V
V
V
nA
IlA
pI
40
40
ns
20
ns
20
7
•
DIODE ARRAY SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
14·PIN CERAMIC DIP
J - PACKAGE
Part No.
SG5768AJ
SG5768J
Ambient
Temperature Range
Connection Diagram
4li14110
-55°C to 150°C
-55°C to 150°C
2
3
5
6
7
10-PIN CERAMIC FLATPACK
F-PACKAGE
SG5768AF
SG5768F
-55°C to 150°C
-55°C to 150°C
14-PIN CERAMIC DIP
J - PACKAGE
SG5770AJ
SG5770J
-55°C to 150°C
-55°C to 150°C
10-PIN CERAMIC FLATPACK
F-PACKAGE
SG5770AF
SG5770F
-55°C to 150°C
-55°C to 150°C
14-PIN CERAMIC DIP
J - PACKAGE
SG5772AJ
SG5772J
-55°C to 150°C
-55°C to 150°C
10-PIN CERAMIC FLATPACK
F-PACKAGE
SG5772AF
SG5772F
-55°C to 150°C
-55°C to 150°C
Note 1. Consult factory for other packages available.
2. All packages are viewed from the top.
3. Consult factory for JAN. JAN TX. and JAN TXV product availability.
8-18
13
••••
12
9
8
1_10
2
3
4
5
9
8
7
6
lm 1140
2
3
12
4
11
5
6
7
9
8
13
1010
2
3
4
5
9
·8
7
6
DIODE ARRAY SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION (continued)
Package
Part No.
14-PIN CERAMIC DIP
J-PACKAGE
SG5774AJ
SG5774J
Ambient
Temperature Range
Connection Diagram
1Lch-'.:...J~~bf--l14
-55°C to 150°C
-55°C to 150°C
~
2 [
p13
~P12
4[~Pll
3 [
5 [
6[
7L
14-PIN CERAMIC FLATPACK
F - PACKAGE
SG5774AF
SG5774F
-55°C to 150°C
-55°C to 150°C
~_h10
~p9
8
r.;
'L----,B'
1
2
3
~
I
4
:
~
7
14-PIN CERAMIC DIP
J - PACKAGE
SG2576BJ
Silicon General •
SG6496AF
SG6496F
:0
8
2
13
3
4
5
6
12
11
10
9
7
8
1114
2
3
4
5
20-PIN CERAMIC FLATPACK
SF-PACKAGE
11
1114
SG25770J
14-PIN CERAMIC DIP
J-PACKAGE
13
14
g
13
12
11
10
6
9
7
8
-55°C to 150°C
-55°C to 150°C
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
B -19
•
8-20
SG61OO/SG6101
SILICON
GENERAL
ADVANCED DATA SHEET
DIODE ARRAY CIRCUITS
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG61 00 and SG6101 diode arrays are monolithic, high breakdown, fast
switching speed diode arrays. The SG6100 is configured with 7 straight
through diodes, while the SG61 01 has 8 straight through diodes.
•
•
•
•
These two diode array configurations allow the designer maximum flexibility
for circuit design and board layout. Since each diode within the array has
individual anode and cathode connections the device may be used in a variety
of applications. Also, due to the array's monolithic construction the diode
electrical parameters are very closely matched.
75V minimum breakdown voltage
100mA current capability per diode
Switching speeds less than 5ns
Low leakage current < 25nA
HIGH RELIABILITY FEATURES
• MIL·S·19500/474 QPL planned for Sept. '89
• Equivalent JANS, JANTXV, JANTX, JAN
screening available
Both devices are available in ceramic DIP and flatpack and can be processed
to Silicon General's S level, JANTXV, JANTX, or JAN equivalent flows.
CIRCUIT DIAGRAMS
7· STRAIGHT THROUGH OIOOES
SG6100
8· STRAIGHT THROUGH DIODES
SG6101
April 1990
8 - 21
•
DIODE ARRAY SERIES
ABSOLUTE MAXIMUM RATINGS (Note 1 & 2)
Breakdown Voltage (VOR) ..................................................... 75V
Output Current (10)' Tc = 25·C
Continuous ..............•............................•...................... 300mA
Note 1. Exceeding these ratings could cause damage to the device.
Note 2. Applicable for each diode.
Operating Junction Temperature
Hermetic (J, F Packages) ............................................. 150·C
Storage Temperature Range ............................. -65·C to 200·C
Lead Temperature (Soldering, 10 seconds) ................•... 300·C
THERMAL DERATING CURVES
2.5,...--r----,--,.--r--,--...,---,
~
~
J
3.0 I---I--I-~
iii
;
c
2.0
~~:,-,----t--+--'\i
I
1.01---+---'
175
AMBIENT TEMPERATURE -
CASE TEMPERATURE - "c
'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Operating Ambient Temperature Range
SG6100 ........................................................ -55·C to 150·C
SG6101 ........................................................ -55·C to 150·C
Note 3. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of T. = 25·C for each diode. Low duty cycle pulse testing
techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Breakdown Voltage (VBR)
~orward Voltage (VF)
Revef$El durrent (IR)
Capacitance (C) (Note 4)
Forwarc:! RecOvery Time ("')
(Note 4)
Reverse Bec:overy Time (t,,)
(Note 4)
Test Conditions
IR .. 5/lA, Duty Cycle < 20%
Duty Cycle s 2%, 300 liS pulse
IF" 100mA
IF" 10mA, TA .. -55~C
VR.. 20V
VR.. 40V
VR .. 40V, TA .. 150·C
vR.. OV, I .. 1MHz, Pin-to-pin
SG6100/SG61 01
Units
Min. Typ. Max.
75
V
1.0
1.0
25
100..
50
4
V
V
nA
nA
.~
pI
IF = 590mA, trs 15ns, Vfi = 1.8V, Rs" 50Q
15
ns
IF .. IR .. 200mA, i; .. 20mA, RL = 100Q
5
ns
Note 4. The parameters, although guaranteed, are not 100% tested in production.
8-22
DIODE ARRAY SERIES
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
14-PIN CERAMIC DIP
J- PACKAGE
(continued)
Part No.
Ambient
Temperature Range
SG6100J
-55°C to 150°C
Connection Diagram
1 ~
c---=-
2
3 ,-
13
12
4 ~
11
5
10
9
6
7 ,~
16-PIN CERAMIC DIP
J-PACKAGE
SG6101J
-55°C to 150°C
1
2
r--' 15
14
4
5 ,-
h 12
6 ~
r--'11
7
13
~
r--' 10
B
SG6100F
-55°C to 150°C
3
4
5
6
16-PIN CERAMIC FLATPACK
F-PACKAGE
SG6101F
-55°C to 150°C
-
1
2
B
16
~
3
14-PIN CERAMIC FLATPACK
F-PACKAGE
14
9
14
~
...
"
...
...
"
r*l
13
12
11
10
9
7
B
1
16
2
15
3
14
4
13
5
12
6
11
7
10
B
9
Note 1. Consult factory for other packages available.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
8-23
•
8-24
SG55234/SG55234A/SG5534
SILICON
GENERAL
DUAL SENSE AMPLIFIER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG55234/SG55234A/SG5534 is a monolithic, dual channel sense amplifier
capable of detecting low-level differential-input signals from high speed magnetic
memories. The inputs of the sense amplifier have adjustable threshold levels that allow
the designer to customize the device to the application. Also, to eliminate much of the
threshold voltage adjustments necessary with competitors' sense amplifiers, the
SG55234/SG55234A is tested for VTH matching. This guarantees the different inputs
will trigger within set levels of each other.
•
•
•
•
The outputs of the sense amplifier are TTLJDTL (logic level) compatible and feature
separate strobes for individual channel control.
HIGH RELIABILITY FEATURESSG55234/SG55234A/SG5534
The SG55234/SG55234A/SG5534 is characterized for operation over the full military
ambient temperature range of -55'C to 125'C. The device is available in 16-pin
ceramic DIP or 16-pin flatpack.
~
~
Adjustable input threshold voltage
High speed
TTL or DTL output compatibility
Threshold voltage matching
(L\VTH):
SG55234A 1.5mV
SG55234
3.0mV
Available to MIL-STD-883
SG level "S" processing available
BLOCK DIAGRAM
INPUT lAl
INPUT lA2
:t>~------
~ OUTPUT1W
L - - -l
+VREF:t>
-VREF
' - - - - - - - - < STROBE 1S
--.
I
-
I
INPUT 2 A l : = [ > I - - -
~STROBE
J
2S
~OUTPUT2W
INPUT 2A2
POSITIVE LOGIC: W=AS
FUNCTION TABLE
INPUTS
OUTPUT
A
S
W
H
H
L
X
X
L
L
H
H
Definition of Logic Levels
INPUT
H
L
A* V,D >: VTMfo:X V,D " VTMIN
S
V, >: V'HM'N V, "V'LMfo:X
X
Irrelevant
Irrelevant
• A is a differential voltage (V,O) between A 1 and A2.
For these circuits. V,O is considered positive regardless of which terminal is positive with respect to the
other.
April 1990
8-25
•
SG552341SG55234AISG5534
ABSOLUTE MAXIMUM RATINGS (Note1)
Supply Voltage (+Vee) ......................................................... 7.0V
Supply Voltage (-Vee) ........................................................ -7.0V
Differential Input Voltage .................................................... ±5V
Input Voltage to Ground ..................................................... 5.5V
Note 1. Values beyond which damage may occur.
Operating Junction Temperature (Te)
Hermetic (J, F-Packages) ............................................. 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) ..................... 300°C
THERMAL DERATING CURVES
2.'
2.0
E
~
11.5
~
~
~ ~
is
1.0
I
,-
~
I
i
i5
'~~
~
"
50
75
100
"\.~,
~
2.0
..........
~
Of}
0
J.O
il
~"'~
05
0
'0"
'.0
E
~.-~
~~-iA-
1.0
~
12'
150
0
17'
AMBIENT TtMPERATURE - 'C
~~
,
0
25
50
75
f\.
'~ ~
100
12'
150
175
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage (+Vcc) ....................................... 4.75V to 5.25V
Supply Voltage (-Vee) ..................................... -4.75Vto -5.25V
Reference Voltage (VREF) .................................. 15mV to 40mV
Operating Ambient Temperature Range:
SG55234/SG55234A .................................... -55°C to 125°C
SG5534 ........................................................ -55°C to 125°C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG55234/SG55234A1SG5534 with -55°C,;; T. ,;;
125°C, +Vcc =5V, and -Vcc= -5V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient
temperature.)
SG55234/55234A
Parameter
Test Conditions
SG5534
Units
I Min. Typ.1 Max. I
Static Section
Differential-Input Threshold Voltage (VT) (Note 3)
VREF =15mV
15
SG55234/SG5534
11
mV
19
15
17
SG55234A
13
mV
VAEF = 40mV
40
SG552341SG5534
44
36
mV
40
42
SG55234A
38
mV
Max. Difference Between Any Two Channels (tWT) VAEF = lSmV, TA,:,,2SoC
SG55234
3.0
mV
1.S
SGS5234A
mV
30
Differential-Input Bias Current (liB)
75
+Vce = 5.25V, -Vee = -5.25V, VID = OV
!lA
100
SG5534 only
!lA
Differential:lnput Offset Current (1 10)
O.S
+Vee = S.2SV, -Vee = -S.2SV, VIO = OV
I1A
2.0
High-level Input Voltage (Strobe Inputs) (VIH)
V
Low-Level Input Voltage (Strobe Inputs (V IL)
0.8
V
High-level Output Voltage (VOH)
2.4 4.0
V
+Vee =4.75V,-Vce =-4.7SV, 'OH,,-o.4mA
0.25 0.4
Low-Level Output Voltage (VoJ
V
+Vec = 4.75V, -Vce =-4.7SV, IOL=16 mA
High·Levellnput' Current (Strobe Inputs) (IIH)
+Vcc = 5.25V, -Vee = -5.25V
40
VIH = 2.40V
I1A
1.0
VIH =S.2SV
mA
-1.0 -1.6
Low-Level Input Current (Strobe Inputs) (IlL)
mA
+Vee = 5.2SV, -Vee = -5.25V, VIL = O.4V
Input Clamp Voltage (Strobe Inputs) (Vcol
(SGS534 only) +Vee';' S.2SV, -Vec '" -S.2V,
-1.5V
V
liN =-12mA
8 - 26
SG552341SG55234AISG5534
ELECTRICAL SPECIFICATIONS (continued)
SG55234/55234A
Parameter
Test Conditions
Min.
Static Section (continued)
Short·circuit Output Current (los)
Output Leakage Current (lCEX)
Supply Current from +V cc (+Icc)
Supply Current from
-vcc (-Icc)
+Vcc; 5.25V, -Vcc;
+Vcc; 5.25V, -Vcc;
SG5534 only
+Vcc; 5.25V, -Vcc;
SG5534 only
+Vcc; 5.25V, -Vcc;
SG55340niv
-5.25V, SG55234/234A only
-5.25V, TA ; 25°C
Units
SG5534
Typ. Max.
-2.1
25
-15
-5.25V, TA ; 25°C
-5.25V, TA ; 25°C
rnA
JlA
rnA
rnA
rnA
mA
-3.5
250
40
38
-20
18
SG55234/55234A
Parameter
Test Conditions
Min.
Dynamic Section
Propagation Delay Times From A1-A2 to W
Low to High (TPLH)
High to Low (TPHL)
Propagation Delay Times From Strobe to W
Low to High (TPLH)
High to Low (TPHL)
Differential-Input Overload Recovery
Time (TORO) (Note 4)
Common-Mode-Input Overload Recovery
Time (TORC) (Note 5)
Minimum Cycle Time (TCYC MIN)
SG5534
Typ. Max.
Units
I
C L;15pF, RL;288Q, T A ; 25°C
25
25
40
ns
ns
25
15
30
ns
ns
C L;15pF, RL;288Q, T A ; 25°C
Differential Input Pulse:
V ,O ; 2V, T R ; T F ; 20ns, TA ; 25°C
Common-Mode Input Pulse:
V'c; ±2V, T A ; T F ; 20ns, T A ; 25°C
Note 3. The differential-input threshold voltage (VT) is defined as the DC
differential-input voltage (V ,O ) required to force the output of the
sense amplifier to the logic gate threshold voltage level.
Note 4. Differential-input overload recovery time is the time necessary for
the device to recover from the specified differential·input-overload signal prior to the strobe·enable signal.
TYPICAL APPLICATIONS
20
ns
20
200
ns
ns
Note 5. Common-mode-input overload recovery time is the time necessary for the device to recover from the specified common-modeinput overload signal prior to the strobe-enable signal.
• ; For SG5534 only
+5V
I
+Vcc
~
. -_ _ _--<,i5)-S_TR_O_BE<.,#1
SENSE LINE #1
~~
'4
OUT #1
, -_ _ _--<1J)11_S_TR_O_BE<.,#2 ~
r-~I~-~
OUT #2
SENC::h_+--(7)-_-i
POWER
GNO
-5V
8 - 27
•
SG552341SG55234AISG5534
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Note Below)
Package
Part No.
16-PIN CERAMIC DIP
Ambient
Temperature Range
SG55234J/883B
SG55234J
SG55234AJ/883B
SG55234AJ
J - PACKAGE
-55°C
-55°C
-55°C
-55°C
to
to
to
to
Connection Diagram
125°C
125°C
125°C
125°C
N.C.
INPUT 1A1
INPUT 1A2
,VREF
+VREF
INPUT2A1
INPUT2A2
.Vee
SG55234F/883B
SG55234F
SG55234AF/883B
SG55234AF
16-PIN CERAMIC
FLAT PACK
F-PACKAGE
-55°C
-55°C
-55°C
-55°C
to
to
to
to
125°C
125°C
125°C
125°C
+Vcc
STROBE 1S
OUTPUT 1W
GND2
OUTPUT2W
STROBE 2S
N.C.
GND1
N.C.
INPUT 1A1
+Vcc
STROBE 1S
INPUT 1A2
OUTPUT 1W
GND2
OUTPUT2W
STROBE 2S
-VREF
+VREF
INPUT2A1
INPUT2A2
N.C.
GND1
-Vee
16-PIN CERAMIC DIP
J- PACKAGE
SG5534J/883B
SG5534J
-55°C
-55°C
to
to
125°C
125°C
C""
INPUT 1A1
INPUT 1A2
-VREF
+VREF
INPUT2A1
INPUT2A2
-Vee
SG5534F/883B
SG5534F
16-PIN CERAMIC
FLAT PACK
F- PACKAGE
-55°C
-55°C
to 125°C
to 125°C
Silicon General •
STROBE2S
N.C.
GND1
+Vee
STROBE 1S
INPUT 1A2
OUTPUT 1W
-VREF
GND2
OUTPUT2W
INPUT2A1
STROBE2S
INPUT2A2
N.C.
GND1
-Vee
fro~ the
GND2
OUTPUT2W
COO"
INPUT 1A1
+VREF
Note 1. All packages are viewed
+Vcc
STROBE 1S
OUTPUT 1W
top.
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
8 - 28
SG55236/SG55236A
SILICON,
GENERAL
fl
DUAL SENSE AMPLIFIER/DATA REGISTERS
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG55236/SG55236A is a monolithic, dual channel, high speed sense
amplifier with independently controlled data registers. The input section
features an adjustable differential-input threshold voltage. All four inputs
of the sense amplifier have been screened to guarantee threshold
matching (see Ll.VTH in electrical characteristics).
° Threshold voltage matching (Ll.VTH):
SG55236
1.5mV
SG55236A O.8mV
• Adjustable differential-input threshold voltage
• Reference amplifier Inherently stable with no
external frequency compensation required
• Built-in data register with provisions for
external data inputs
• Built-in data buffer drives 450pF load in 15ns
• Internal reference voltage attenuator makes
reference amplifier less sensitive to noise
Separate detector outputs for each channel allow the designer the
flexibility to use additional output stages if necessary. In addition, each of
the data registers has provisions for external data inputs.
The SG55236A was developed to meet the high speed, tight voltage
threshold matching requirements of today's fast cycle time magnetic
memory systems. Its enhancements are listed in the Electrical
Characteristics.
HIGH RELIABILITY FEATURES - SG55236
~
The SG55236/SG55236A is available in a 24-pin flat pack and is
characterized over the full military ambient temperature range of -55°C to
125°C.
Available to MIL-STD-883
o Radiation data available
~ SG level "5" processing available
BLOCK DIAGRAM
DETECTOR
REGISTER
CHANNEL
SELECT
DETECTOR OUTPUT/
REGISTER INPUT
,C
, W/, RI
I DATA
INPUT
1'0
DIFFERENTIAL
INPUTS
12
L __ ..,
REFERENCE
VOLTAGE
BUFFER
Z~~~
REGISTER
OUTPUT
~REF ~1 -1I
I
STROBE
DATA LOAD
RESET
BUFFER INPUT
REGISTER
OUTPUT
DIfFERENTIAL
INPUTS
BUFFER
OUTPUT
CHANNEL
SELECT
DETECTOR
REGISTER
INPUT
OUTPUT
I See page 4 of this data sheet for Function Tables I
April 1990
8- 29
SG552361SG55236A
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (+v ee ) ........................................................ 7.0V
Supply Voltage (-Vee) ....................................................... -7.0V
Reference Voltage (V AEF) ................................................. ±5.0V
Differential Input Voltage (V,O ) .......................................... ±5.0V
Voltage From Any Input to Ground ................................... 5.25V
Nole 1. Values beyond which damage may occur.
Operating Junction Temperature (T)
Hermetic (J-Package) ................................................... 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering. 10 seconds) ..................... 300°C
THERMAL DERATING CURVES
2.'
50
2.0
40
~, ,.,
~
i "'-t"-.,.,
~
Q
~
.
1.0
~
~~
'I.",
0.'
0
0
" "
75
, "'-
100
'"
"0
~
C
30
20
..........
i
~
........c>.!
"
0
17'
AMBIENT TEt.4PERATURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
0
"
,
~~<",,)
"
75
i'-........
100
'"
'so
'75
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage (+Vee) ....................................... 4.75V to 5.25V
Supply Voltage (-Vee) ..................................... -4.75V to -5.25V
Reference Voltage (V REF) .................................. ±1.5V to ±4.5V
High-Level Output Voltage (VOH ):
Detector and Buffer .......................................................... Vee
High-Level Output Current (l oH ):
Register ..................................................................... -400~A
Low-Level Output Current (lOL):
Register ......................................................................... 16mA
Buffer ............................................................................ 25mA
Detector ....................................................................... 3.2mA
Width of Reset Pulse (tA) .................................................. 115ns
Operating Ambient Temperature Range:
SG55236/SG55236A .................................... -55°C to 125°C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified. these specifications apply over the operating ambient temperatures for SG55236/SG55236A with -55°C S T. S 125°C.
+Vee =4.75V. -Vee =-4.75V. and VREF =±2.1V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures
equal to the ambient temperature.)
I Units
I SG55236A I SG55236
Parameter
Test Conditions
I Min. Typ. Max. I Min. I Typ. Max. I
Static Section
6.0
8.0
7.0
5.0 7.0 9.0
mV
Differential-Input Threshold
+Vee = 5V. -Vee =-5V. TA =25°C
8.5
5.5
7.0
4.5
9.5
mV
7.0
Voltage (VTH)
+Vce =5V ±5%. -Vee =-5V ±5%
o.a
1.5
mV
TA=25°C (See Functional Description)
Delta Threshold Voltage (~WTH)
12
20
40
20
Differential-Input Bias Current (liB)
+Vee =5V. -Vee = -5V. V,O = 0
~
Differential-Input Offset
2.0
0.5
1.0 5.0
Current (1,0)
+Vce =5V. -Vee =-5V. V,O = 0
~
High-Level Input Voltage (V,~
2.0
V
(Strobe and Logic Inputs)
2.0
Low-Level Input Voltage (V,J
0.8
o.a V
(Strobe and Logic Inputs)
High-Level Output Voltage (VOH)
2.4
2.4
V
Register
V,H =2V. V,L =o.av. 10H =-400~A
2.4
V
2.4
Detector
V,H = 2V. V,L =o.av
High-Level Output Current (lOH)
250 ~
250
Buffer
V,H = 2V. V L = o.av. VOH = 4.75V
8-30
SG552361SG55236A
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Static Section (continued)
Low-Level Output Voltage (VOL)
Register
Buffer
Detector
Input Current at Maximum Input
Voltage (Logic Inputs) (liN)
High-Level Input Current (IIH)
Data In or Channel Select
Register Input 2RI
Strobe, Reset, or Buffer Input
Data Load
Low-Level Input Current (IlL)
Data In
Channel Select
Register Input 2RI
Strobe, Reset, or Buffer Input
Data Load
Short-Circuit Output Current (los)
Register
Reference-Input Current (I REF)
I
Test Conditions
SG55236A
I
SG55236I U 't
Min. I Typ. I Max. Min. I Typ. I Max. I m s
VIL = 0.8V, 10L = 16mA
VIL = 0.8V, 10L = 25mA
VIL = 0.8V
0.4
0.5
0.4
0.4
0.5
0.4
V
V
V
+Vee = 5.25V, -Vee =-5.25V, VIH = 5.25V
+Vee = 5.25V, -Vee = -5.25V, VIH = 2.4V
1
1
mA
40
-750
80
160
40
-750
80
lS0
I!A
-2.0
-l.S
-3.0
-3.2
-S.4
-2.0
-1.S
-3.0
-3.2
-S.4
mA
mA
mA
mA
mA
-SO
mA
0.5
55
18
mA
mA
mA
VIH = 2V,
VIH = 2V,
VIH = 2V,
+Vee = 5.25V, -Vee = -5.25V, VIL = 0.4V
+Vee = 5.25V, -Vee =-5.25V, VOUT = OV
+Vee = 5.25V, -Vee = -5.25V,
VREF =-2.1V, TA,= 25 C
+Vee = 5.25V, -Vee = -5.25V, TA, = 25 C
+Vee = 5.25V, -Vee = -5.25V, TA, = 25 C
-20
-SO
0.5
55
18
Q
Supply Current From +Vee (+Iee)
Supply Current From -Vce (-Icc)
-20
Q
Q
!!A
I!A
!!A
SG55236A
I
SG5523S
-I Units
Min. Typ. Max. Min. Typ. I Max. I
See
Figure
Input
Output
1,2
3,4
5,S
3,4
5,S
5,S
5,S
1,2
lAor2A
Strobe
Data Input
Data Load
Reset
Reset
Buffer Input
1A or 2A
Y
y
Y
y
Y
Z
Z
Z
28
lS
17
13
12
100
14
42
40
25
30
25
20
200
35
SO
28
18
17
15
12
100
22
42
50
35
40
35
30
200
55
90
ns
ns
ns
ns
ns
ns
ns
ns
Transition Time
Low to High (TTLH)
V
5,6
High to Low (TTHL)
5,S
Y
Low to High (TTLH)
Z
5,S
High to Low (TTHL)
5,S
Z
Note 3. Unless otherwise specified, +Vee = 5V, -Vee = -5V, VA" = -2.1V, TA = 25'C
10
4
150
15
20
15
185
35
13
7
150
20
35
20
185
50
ns
ns
ns
ns
Parameter
Dynamic Section (Note 3)
Propagation Delay Time
Low to High (TPLH)
High to Low (TPHL)
Low to High (TPLH)
High to Low (TPHL)
8 - 31
SG552361SG55236A
BLOCK DIAGRAM
DETECTOR
DIFFERENTIAl
lA1
BUFFER
REGISTER
CHANNEL
DElECTOR OUTPUT!
SELECT
REGISTER INPUT
1C
1W/1RI
I INPUT
DATA
I 10
,
lZ
INPUTS
~~
REGISTER
OUTPUT
STROBE
L (!l1~----+-+------t-1
DATA. LOAD
R~
R~"~----+-+-----+------+
G ~'~----+-+-----I+------+-----H
BUFFER INPUT
REGISTER
OUTPUT
BU"",
DIFFERENTIAL
INPUTS
OU1l'\JT
DETECTOR
OUTPUT
CHANNEL
SELECT
REGISTER
INPUT
FUNCTION TABLE
FUNCTION TABLE FOR DUAL-CHANNEL
DETECTOR OPERATION
(2W connected to 1W/1 RI)
INPUTS
OUTPUTS
INPUTS
OUTPUT
A
C
S
W/RI'
L
D
R
G
y
Z
lA lC
2A
2C
S
lW·2W
H
H
H
H
H
H
L
L
X
X
X
X
X
X
X
H
H
L
H
H
H
H
H
H
H
L
L
X
X
X
X
X
L
l'
L
H
L
H
L
H
L
H
H
L
H
H
H
X
H
L
L
H
L
L
X
X
X
X
X
l'
H
L
L
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
H
H
L
L
L
H
H
L
L
L
H
H
L
L
H
L
L
L
L
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
L
L
H
L
H
L
H
L
H
L
H
i
i
l'
i
i
i
X
X
X
X
X
X
X
X
J.
J.
H
H
H
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
J.
J.
H
H
H
H
H
H
H
H
J.
J.
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
i
X
H
L
X
X
X
H
L
X
X
X
H
L
X
X
J.
J.
L
X
X
X
L
X J.
H
L
J. H
Any Other
Combination
H
i
i
i
i
H
H = High level (steady state)
L = Low level (steady state)
X = Irrelevant (any input, including transitions)
J. = Transition from high level to low level
i = Transition from low level to high level
, The W/RI column shows the output from the detector resulting
fromtheinputsA,C,andS. In positive logic, W=ACS. Fordual
operation with 2W connected to 2RI,this column represents an
intermediate node and can be ignored.
X
L
H
H
H
For independent operation of register 2, this column is an input
and the A, C, and S columns should be ignored.
X
L
H
H
H
For dual-channel operation with 2W connected to 1Wll Rl,this
column istheresultofW = S(IA· lC + 2A· 2C),asshown in
the table above.
Definition of Logic Levels
•• A is a differential voltage (V'D) between AI
and A2. For these circuits, V'D is considered
positive regardless of which terminal is
positive with respect to the other.
8 - 32
SG552361SG55236A
TEST CIRCUITS AND SWITCHING WAVEFORMS
PROPAGATION DELAY TIMES, DIFFERENTIAL INPUT TO REGISTER OUTPUT AND BUFFER OUTPUT
-5V
OPEN
5V
OPEN
REGISTER
OUWUT
VCC+
5V
5V
IY
1Z
RL(Z)
I
BUFFER
OUWUT
CL(Z) -450pF
(See Note 6)
",------,-..,2Z,-- OPEN
OPEN
f--+-_ _ _ _---cy2"-Y_ OPEN
OPEN-"""",-~-,
FIGURE 1 • TEST CIRCUIT (See Nol. 8)
I
I
~_~~(R)i/
RESET
I
I
STROBE
!
- - - - - - - - - - - - - - - - - - - - - - - - - OV
., 30ns
----I
I--
9/(f.5V:
~~V----------
I
f---135ns----l
I
I
I
I
I
DIFFERENTIAL
INPUT
3.5V
~_':5V
!
I
t---
3.5V
OV
200ns
---j
12mVromv
~~m~---
40mV
OV
: - - - . , 275ns - - : .
I
I
(S..R~~;!~~ ~'--------i-!J6~v__________ __
--I
I
I - - TPLH
VOH
VOL
I
...
g~i~0~ _____J~----+! ~'_5_;_-_-_-_-_-_-_-_-_-_~
I
' - - TPHL
I
FIGURE 2· VOLTAGE WAVEFORMS
Note 4.
5.
6.
7.
s.
The pulse generators have the following characteristics: Zo = 50n, t, = 15ns, ~ = 15ns, t. '"' ~ 115ns, PRR = 500KHz.
All diodes are 1N3064.
CL C'l and CL 'Z) include probe and jig capacitance.
Initially high output condition can be established by repetitive cycling.
Connections are shown for testing channell. To test channel 2, reverse connections of 1C and 2C along with inputs and outputs.
8 - 33
•
SG55236/SG55236A
TEST CIRCUITS AND SWITCHING WAVEFORMS (continued)
PROPAGATION DELAY TIMES, STROBE AND DATA LOAD TO REGISTER OUTPUT
-SY
OPEN
OPEN
5Y
SY
REGISTER
OUlPUT
5Y
RL(y)=820n
I
+
OPEN
CL(y) =SOpF
(See Nol. 10)
(See Note 11)
-::-
SY
OPEN
f--+-------{y'--- OPEN
SY
FIGURE 3 - TEST CIRCUIT (5•• Not. 13)
, - - -.... - - - - - - - - - - - - - - - - - 3.5V
STROBE
1.5~
I
~.5V
~--------------------OV
________- J
I
I
:
REGISTER
i
--1
lIiI
OUTPUT
(See Note 12) ------~i
1.5V
TPLH - - I
I--
I
J--TPHL
/..~------...,...-----.l~:.1
1--
I
i "-
- - - - - - - - -
I
VOH
VOL
I
~
~;;;50ns
I
1.5V~~V----- 3.5V
DATA LOAD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J.
I
~
I
tW(L)
.
OV
i--
FIGURE 4 - VOLTAGE WAVEFORMS
Note 9.
10.
11.
12.
13.
The pulse generators have the following characteristics: Zo = 50n, t, = 15ns, ~ = 15ns, t..(~ l! 35ns, PRR = 500KHz.
CL(y1 includes probe and jig capacitance.
All aiodes are 1N3064.
Initially low output condition can be established by repetitive cycling.
Connections are shown for testing channell. To test channel 2, reverse connections of 1C and 2C along with inputs and outputs.
8-34
SG552361SG55236A
TEST CIRCUITS AND SWITCHING WAVEFORMS (continued)
PROPAGATION DELAY TIMES FROM DATA INPUT RESET AND BUFFER INPUT TO REGISTER OUTPUT AND BUFFER
OUTPUT, TRANSITION TIMES OF REGISTER OUTPUT AND BUFFER OUTPUT
-sv
OPEN
sv
OPEN
REGISTER
au UT
5V
sv
IY
p---cr'~Z------------------~--~~~~
+
•
"e(Z} -4S0pF
(See Note 15)
f-___----------<.::}'2C!.Y- OPEN
2W
2C
2Rl
GND
2D
FIGURE 5· TEST CIRCUIT (See NoIel8)
RESET
~,-1.S_V
__---J/"-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- : V
I
r--
:~
REGISTER
OUTPUT
(See Note 17)
DATA
INPUT
I
I
~II
---l
TTHL
I
~
HTPLH
I.~~
i
I
I
"
:I
OUTPUT _ _ _ _ _
t5~-------------- ::v
: - - 'w(L) - - - :
I
I----
___________ : V
H~20ns
~~!~ --i-!_____J;f.SV
BUFFER
VOH
I [o;.J.I1Qlli5_ _ _ _~''''Qli.53/;J----------------- VOL
I
BUFFER
INPUT
~ mH
~
S07.
I
1.5V
S07.
1.5V
TPLH
/.
---i
:----:
TPHL
--------'siiioi"7.'1"K!-:-::.:--
I
~~_:
1.SV
I
50~
: - TILH
3.5V
" '-________.....J_,.._
;:,.5V- -- - -- OV
-l
:
TTHL
VOH
~ VOL
--l I--
FIGURE 8· VOLTAGE WAVEFORMS
Note 14.
15.
16.
17.
18.
The pulse generators have the following characteristics: Zo = 500, t, = 15ns, ~ = 15ns, I., ~ 40ns, t.. ~ 100ns, PRR = 500KHz.
CL(y) and CLIl) include probe and jig capacitance.
All oiodes are 1N3064.
Initially high output condition can be established by repetitive cycling.
Connections are shown for testing channel 1. To test channel 2, reverse connections of 1C and 2C along with inputs and outputs.
8-35
•
SG55236/SG55236A
FUNCTIONAL DESCRIPTION
SG55236/55236A THRESHOLD VOLTAGE GRADING
The threshold voltages for each of the four sense amplifier inputs
of the SG55236/55236A are compared to ensure that the
maximum difference between channels does not exceed 1.5mV
(SG55236) or O.8mV (SG55236A). Devices that exceed this limit
are rejected. The four threshold voltage values are averaged to
Standard Spec
lorVT
determine the device's "bin" number (see below). The assigned
bin number is marked in the lower right-hand corner of the
devices.
By using devices from the same bin, system
performance is improved and the need for changing out sense
amps due to trigger level differences is reduced.
5mV~E----------------------------------------------~~9mV
Channel-to-channel variation is NOT spec'd
5.4mV
The SG55236/236A
Spec lorVT
6.2mV
7.0mV
7.8mV
8.6mV
5mV~E----~--------~------~r-------~--------~----+' 9mV
Bin 4
Bin 1
Bin 3
Bin 2
SG55236: Channel-to channel variation:;; 1.5mV
SG55236A: Channel-Io-channel variation:;; 0.8mV
Marking Example:
CONNECTION DIAGRAMS & ORDERING INFORMATION
Package
24-PIN CERAMIC
FLAT PACK
F- PACKAGE
Part No,
(See Note Below)
Ambient
Temperature Range
SG55236AF/883B
SG55236AF
SG55236F/883B
SG55236F
-55°C to
-55°C to
-55°C to
-55°C to
125°C
125°C
125°C
125°C
Connection Diagram
1A2
1A1
2A1
2A2
-Vee
GNO
10
20
2RI
~~~~[lD~~~~
N.C.
+v"
1Z
VREf
S
1C
2C
1W/1RI
1Y
2Y~~2Z
2W
G
R
Note 1. All packages are viewed Irom the top.
Silicon General •
11861 Westem Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
8-36
SGSS32S/SG7S32S
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
DUAL SOURCE / DUAL SINK MEMORY DRIVER
DESCRIPTION
FEATURES
The SG55325/SG75325 is a monolithic dual source/dual sink driver
designed to meet the high current and fast switching speed requirements
of magnetic memory systems. Each driver can be independently selected
through separate input logic. Also, each pair of drivers (sink or source pairs)
has a separate strobe input to allow control of either pair of drivers. Each
driver of the SG55325/SG75325 can switch SOOmA.
•
•
•
•
•
•
•
Although used extensively in magnetic memory systems, this versatile
driver has been used to drive relays, lamps, and small motors as well as
being used as the driver in a clock circuit.
The SG55325 is characterized for use over the military ambient
temperature range of -55°e to 125°e. The SG75325 has an operating
ambient temperature range of ooe to 70 oe.
SOOmA output capability
Fast switching times
Output short-circuit protection
24V output capability
Source base drive externally adjustable
TTL or DTL compatabiJity
Input clamping diodes
HIGH RELIABILITY FEATURES - SG55325
•
•
•
•
Available to MIL-STD-883
MIL-M-38510/13001BEA - JAN55325J
Radiation data available
SG level "S" processing available
These devices are available in 1S-pin ceramic DIP, 1S-pin plastic DIP, and
1S-pin flatpack.
BLOCK DIAGRAM
•
SOURCE
W
COLLECTORS
A
S1
S2
'-------y--l
STROBES
April 1990
8 - 37
C
y
GND
SG553251SG75325
ABSOLUTE MAXIMUM RATINGS (Notel)
Supply Voltage (Vcc,) (Note 2) ............................................7.0V
Supply Voltage (VCC2) (Note 2) ............................................ 25V
Input Voltage (any address or strobe input) ....................... 5.5V
Storage Temperature Range ............................. -65·C to 150·C
Note 1. Values beyond which damage may occur.
Note 2. Voltage values are with respect to network ground terminal.
Operating Junction Temperature (Tc)
Hermetic (J, F-Packages) ............................................. 150·C
Plastic (N-Package) ...................................................... 150·C
Storage Temperature Range .............•......•....•.... -65·C to 150·C
Lead Temperature (Soldering, 10 seconds) ..................... 300·C
THERMAL DERATING CURVES
.5
50,\
.0
'.0
I t"-N
b.,~ ~~.~"
~
~
~
~
c
1.0
O.S
0
0
25
so
l'~150
75
tOO
30
,,~
'1,;:"-
02.0
.~~
<"\I ,
'k~<
~
'\
.1
I ~~~
~
'~~~
,
11.5
125
t.O
00
t75
..........
,.
25
AMBIENT TEMPERATURE - "C
75
l\.
~~
tOO
tSO
125
175
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Supply Voltage (Vcc,) ......................................... 4.5Vt05.5V
Supply Voltage (VCC2) ........................................... 15Vt024V
Input Voltage ..............................................•.........
0.4Vto 5V
Note 3. Range over which the device is functional.
REXT (VCC2 = 24V) ............................................................... 1000
Operating Ambient Temperature Range:
SG55325 ...................................................... -55·C to 125·C
SG75325 .............................•...............•............... O·C to 70·C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG55325 with -55°C:;; T. :;; 125°C, SG75325 with
O°C :;; T. :;; 70°C, VCCt = 5.5V, and VCO2 = 24V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal
to the ambient temperature.)
Parameter
Static Section
High·Levellnput Voltage (VIH)
Low-Level Input Voltage (VIL)
Input Clamp Voltage (VIK)
Source-Collectors Terminal
Off-State Current (IOFF)
High-Level Sink Output
Voltage (VOH)
Saturation Voltage (VSAT) (Note 3)
Source. Outputs
Sink Outputs
Input Current (liN)
Address Inputs
Strobe Inputs
Test Conditions
I SG55325
I SG75325
I
I Min. I Typ. I Max. I Min. I Typ. Max.
2
2
VCC , = 4.5V, liN = -10mA, TA = 25°C
-1.3
0.8
-1.7
Vcc , =4.5V
Vcc , = 4.5V, TA = 25°C
3.0
500
150
Vcc , = 4.5V, lOUT = 0
Vcc, = 4.5V, VCC2 = 15V, RL = 240
ISOURCE '" -600mA
ISOURCE '" -aOOmA, TA;" 25°C
ISINK '" -600mA
ISINK .. -aoomA, TA =25°C
At max. input voltage, VIN = 5.5V
8 - 38
19
23
0.43
0.43
19
0.90
0.70
0.90
0.70
-1.3
0.8
-1.7
3.0
200
200
V
V
V
!lA
j!A
V
23
'0.43
Units
0.90
0.75
0.90
0.43 0.75
1
1
2
2
V
V
V
V
mA
mA
SG553251SG75325
ELECTRICAL SPECIFICATIONS (continued)
Parameter
SG55325
SG75325
I
I
I Min. Typ. Max. I Min. Typ. Max.
Test Conditions
Static Section (continued)
High-Level Input Current (I'H)
Address Inputs
Strobe Inputs
Low-Level Input Current (Ill)
Address Inputs
Strobe Inputs
Supply Current
From VCC1
From VCC2
Supply Current From Vee1
Supply Current From VCC2 (Note 4)
V,N = 2.4V
Y'N
3
6
40
80
3
6
40
80
!lA
-1
-2
-1.6
-3.2
-1
-2
-1.6
-3.2
mA
mA
14
7.5
55
22
20
70
14
7.5
55
22
20
70
mA
mA
mA
32
50
32
50
mA
= O.4V
IlA
All sources and sinks off, TA = 25°C
Either sink on, ISINK = 50mA, TA = 25°C
Either source on, ISOURCE = -50mA,
TA = 25°C
To (Outputs)
Parameter
Dynamic Section (Note 6)
Propagation Delay, Low to High
(TPLH)
Propagation Delay, High to Low
(TPHL)
Transition Time, Low to High
(TTLH)
Transition Time, High to Low
(TTHL)
Storage Time (Ts)
Units
Source Collectors
Sink Outputs
Source Collectors
Sink Outputs
Source Outputs
Sink Outputs
Source Outputs
Sink Outputs
Sink Outputs
I SG55325/75325 I
I Min. I Typ. Max. I
Test Conditions
VCC2 = 20V, RL = 1KO
VCC2 = 20V, RL = 1KO
35
20
35
20
55
7
7
50
45
50
45
9
20
30
15
15
Note 4. These parameters must be measured using pulse techniques,
Tw =200ms, duty cycle,; 2%.
Note 5. Under these conditions, not more than one output is to be on at
anyone time.
Note 6. Unless otherwise specified, Vee.
RL = 24Q, and TA =25°C.
= 5V,
Vee2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
= 15V, CL= 25pF,
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Note Below)
Package
Part No.
Ambient
Temperature Range
16-PIN CERAMIC DIP
J-PACKAGE
SG55325J/883B
SG55325J
SG75325J
-55°C to 125°C
-55°C to 125°C
O°C to 70°C
16-PIN PLASTIC DIP
N· PACKAGE
SG75325N
O°C to 70°C
Connection Diagram
SOURCE COLLECTORS [l"i""16p v,"
w [2
15p x
A [3
14p B
STROBE S1 [ 4 13 NODE R
[5
12
c
[6
11
Y
[7
10p
SG55325F/883B
SG55325F
-55°C to 125°C
-55°C to 125°C
SOURCE
COLLECTORS
w
§
1
2
A~3
STROBE S1 '
I
STROBES2 ~
C'
Y
GND
Z
[~P VCC1
GND
16-PIN CERAMIC
FLAT PACK
F-PACKAGE
P
PD
PR'NT
STROBE 52
4
5
6
7
:====:J •
16~VCC2
151=== X
141===
13~
B
NODER
1 2 1 = = = R'NT
",
D
10
Z
i===
9 c=====J VCC1
Note 1. All packages are viewed from the top.
Silicon General.
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
8 - 39
8 - 40
SG553261SG75326
SILICON
GENERAL
QUAD SINK MEMORY DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG55326/SG75326 is a monolithic quad positive-OR sink
driver designed to meet the high current and fast switching speed
requirements of magnetic memory systems. Each driver is independently controlled and capable of sinking up to 600mA.
•
•
•
•
Paired with the SG55327 Quad Source Driver, the SG55326/
SG75326 provides the current drive necessary for many sink!
source applications.
•
•
Although designed specifically for magnetic memory applications,
the SG55326/SG75326 has been used to drive clock circuits,
relays, lamps, and small motors, or any application where a 600mA
sink driver is needed.
The SG55326 is characterized for use over the full military operating ambient temperature range of -55°e to 125°e while the
SG75326 is characterized over the operating ambient temperature
of ooe to 70 oe.
•
•
600mA output current sink capability
24V output capability
Clamp voltage variable to 24V
High-repetition-rate driver compatible with
high-speed magnetic memories
Inputs compatible with TTL level decoders
Minimum time skew between strobe and
output-current rise
Pulse-transformer coupling eliminated
Drive-line lengths reduced
HIGH RELIABILITY FEATURES - SG55326
• Available to MIL-STD-883
• MIL-M-38510/13002BEA - JAN55326J
• SG level "S" processing available
These devices are available in 16-pin ceramic DIP,16-pin plastic
DIP, and 16-pin flatpack.
BLOCK DIAGRAM
CLAMP
W,Z
z
D
s
CLAMP
C
Y
16
X,Y
9
8
GND
w
B
A
April 1990
8-41
x
GND
SG553261SG75326
ABSOLUTE MAXIMUM RATINGS (Notel)
Supply Voltage (Vcc) (Note 2) .............................................. 7.0V
Input Voltage (any address or strobe input) ....................... 5.5V
Output Collector Voltage ..................................................... 25V
Output Clamp Voltage ......................................................... 25V
Note 1. Values beyond which damage may occur.
Note 2. Voltage values are with respect to network ground terminal.
Output Collector Current ................................................. 750mA
Operating Ambient Temperature (Tc)
Hermetic (J, F-Packages) ............................................. 150°C
Plastic (N-Package) ...................................................... 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) .................... 300°C
THERMAL DERATING CURVES
'.0,\
2.01--+--+---If--+-+---I--l
~
4.0 I-~~-+--f--+-+---I---l
'\
•
" :I--t--t---f---j
~30
"~"~.+~~"tt--t---f---l
.~
~ 2.0~...,
'",-
i
'.0
°o
~~'l\.
'~~
25
50
75
100
125
150
175
CASE lEMPERATURE - 'C
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION YS CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Supply Voltage (VCC) ............................................. 4.5V to 5.5V
Output Collector Voltage .................................................... 24V
Output Clamp Voltage (V CLAMP) .............................. 4.5V to 24V
Output Collector Current ................................................ 600mA
Operating Ambient Temperature Range:
SG55326 ...................................................... -55°C to 125°C
SG75326 .................................................... ....•... O°C to 70°C
Note 3. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG55326 with -55°e s T. S 125°C, and SG75326
wnh oDe s T. S 70 0 e. All typical values are measured at T. = 25°e. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
I
SG55326
I
SG75326
J
Parameter
Test Conditions
Min. I Typ. I Max. I Min. Typ. Max. I Units
Static Section
High-Level Input Voltage (VIH)
2
2
V
Low-Level Input Voltage (VIL)
0.8
V
0.8
-1.0 -1.7
-1.0 -1.7
V
Input Clamp Voltage (VIK)
High-Level Output Voltage (VOH)
19
23
V
23
19
0.9
0.9
V
Saturation Voltage (VSAT) (Note 4)
0.43 0.70
0.43 0.75
V
Output-Clamp-Diode Forward
1.5
1.5
V
VCLAMP =OV, ICLAMP = -10mA, TA =25°C
Voltage (VF(CLAMP)
7
mA
Output-Clamp Current (ICLAMP)
5
7
5
One Output On,ISlNK = 50mA, TA =25°C
Input Current (liN)
VIN = 5.5V
Address
1
1
rnA
Strobe
4
4
mA
High-Level Input Current (J IH)
Address
40
40
IJA
Strobe
160
160
IiA
8-42
SG553261SG75326
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Static Section (continued)
Low-Level Input Current (IlL)
Address
Strobe
Supply Current
Supply Current
I
Test Conditions
SG55326
I
SG75326
I Min. I Typ. I Max. I Min. I Typ. I Max.
Units
VIN = 0.4V
All outputs off, all inputs at5V, TA = 25°C
One output on, ISINK = 50mA, TA= 25°C
Parameter
To (Output)
Dynamic Section (Note 5)
Propagation Delay, Low to High (TPLH)
Propagation Delay, High to Low (TPHL)
Transition TIme, Low to High (TTLH)
Transition Time, High to Low (TTHL)
Storage TIme
High-Level Output Voltage (VOH )
-1.0
-4.0
18
58
-1.S
-S.4
25
75
-1.0
-4.0
18
58
mA
mA
mA
mA
I SG55326175326 Units
I Min. I Typ. I Max. I
Test Conditions
W,X, Y,orZ
W,X, Y, orZ
W,X, Y,orZ
W, X, Y, orZ
W, X, Y,orZ
30
25
7.0
10
24
Vs= VCLAMP = 24V, ISINK~ 500mA,
C = 25pF, R =470
Note 4. Under these conditions, not more than one output is to be on at
anyone time.
-1.S
-S.4
25
75
50
50
15
20
35
Vs-25
ns
ns
ns
ns
ns
mV
Note 5. Unless otherwise specified, Vee = 5V, Vs = VelAMP = 15V, CL =
25pF, RL = 24Q, and T. = 25°C.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
16·PIN CERAMIC DIP
J-PACKAGE
16·PIN PLASTIC DIP
N-PACKAGE
Part No.
Ambient
Temperature Range
SG5532SJ/883B
SG5532SJ
SG7532SJ
SG7532SN
Connection Diagram
-55°C to 125°C
-55°C to 125°C
O°C to 70°C
GND
w
A
Z
AOO"
S
N.C.
O°C to 70°C
SG5532SF/883B
SG5532SF
-55°C to 125°C
-55°C to 125°C
o
v"
B
C
x
y
GND (Note 3)
16·PIN CERAMIC
FLAT PACK
F-PACKAGE
CLAMPW,Z
CLAMP X, Y
GND
CLAMPW.Z
W
Z
o
A
A,,,,
55
N.C.
V'"
B
C
x
GND
Y
-----c..'--_--"____- -
CLAMP X. Y
Note 1. All packages are viewed from the top.
Note 2. Contact factory for LCC availability.
Note 3. Pin 8 is in electrical contact with the metal base.
Silicon General • t 1861 Western Avenue. Garden Grove, CA 92641 • (714) 898·8121 • TWX: 910-596·1804. FAX: (714) 893·2570
8-43
•
8-44
SG553271SG75327
SILICON
GENERAL
QUAD SOURCE MEMORY DRIVER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG55327/SG75327 is a monolithic quad source driver
designed to meet the high current and fast switching speed
requirements of magnetic memory systems. Each driver is
independently controlled and capable of sinking up to SOOmA.
•
•
•
•
Paired with the SG5532S Quad Sink Driver, the SG553271
SG75327 provides the current drive necessary for many sink!
source applications.
•
The SG55327/SG75327 has also been used in many non-memory
applications: for example, as the driver for a clock circuit, relay,
lamp, or small motor, or any application where a SOOmA source
driver is needed.
•
•
•
•
Quad source memory drivers
600mA output current capability
VCC2 drive voltage variable to 24V
Output capable of swinging between VCC2 and
ground
High-repetltion-rate driver compatible with
high-speed magnetic memories
Inputs compatible with TTL decoders
Minimum time skew between strobe and
output-current rise
Pulse-transformer coupling eliminated
Drive-line lengths reduced
HIGH RELIABILITY FEATURES - SG55327
The SG55327 is characterized for use over the full military
operating ambient temperature range of -55°G to 125°C while the
SG75327 is characterized from OOG to 700G.
• Available to MIL-STD-883
• Scheduled for MIL-M-38510 QPL listing
• SG level "S" processing available
These devices are available in 1S-pin ceramic DIP, 1S-pin plastic
DIP, and 1S-pin flatpack.
BLOCK DIAGRAM
Call.
W,Z
z
s
D
CalL.
C
Y
16
9
®
CD
VCC2
X,Y
w
A
B
NODE
R
April 1990
8 - 45
x
GND
SG553271SG75327
ABSOLUTE MAXIMUM RATINGS (Notel)
Output Collector Current ................................................. 750mA
Operating Junction Temperature (Tc)
Hermetic (J. F-Packages) ............................................. 150°C
Plastic (N-Package) ...................................................... 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering. 10 seconds) ..................... 300°C
Supply Voltage (VCCl) (Note 2) ............................................. 7.0V
Supply Voltage (VCC2) •••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 25V
Input Voltage (any address or strobe input) .....•................. 5.5V
Output Collector Voltage ....•................................................ 25V
Note 1. Values beyond which damage may occur.
Note 2. Voltage values are with respect to network ground terminal.
THERMAL DERATING CURVES
2.' r----;--,--,..---,--...,----,-....,
J£
~
11.5
;
I
is 1.0
o
~
2.0
i
•.• I---+-+--I--"'....r:~
1•• 1---+-+---"'~--"Ioo.--"~-1f--l
AMBIENT TEMPERATURE - 'C
CASE TEMPERATURE - *C
MAXIMUM POWER DISSIPATION VB AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 3)
Output Collector Current ............................•..........•......... 600mA
Operating Ambient Temperature Range:
SG55327 ....................................................... -55°C to 125°C
SG75327 ............................................................. O°C to 70·C
Supply Voltage (VCC1) ............................................ 4.5V to 5.5V
Supply Voltage (VCC2) ............................................. 4.5V to 24V
Output Collector Voltage .................................................... 24V
Note 3. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified. these specifications apply over the operating ambient temperatures for 8G55327 with -55·e ~ T. ~ 125·e. and 8G75327
with o·e ~ T. ,;; 70·e. Low tluty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient
temperature.)
Parameter
Test Conditions
Static Section
Hlgh-Leve!.)nput Voltage (VoJ
Low-Leve~,I~p~t V~I!all.~ (V,J
Input CIBI"!1P Voltag~. (V.fI() . .
Collectors Terminal Off-State
¢urr~ni (I~~j
Saturatio~,yolUige (V~~nN\lie 4)
'".
. ...
Input cuiT!3nt(il~) . ' "~ _::.
Address
. , .
Strobe .::
High-Level Input Current (ilH)
AddresS. .. " .' '[ ~.',' , ' Strobe
Low-Leveflnput
Address
..
StrobEi ,C"
>. .,.
..
curreni(l.i
"_ -
I SG55327
I
SG75327
I Units
I Min. I Typ. I Max. I Min. I Typ. I Max. I
2
2
0.8
-1.7
VCC1 " 4.5V. lIN'" -lOrnA. TA ='25°0
-1.0
VCC1 '" 4.5V. VCOL " 24V
VCC1 = 4.5Y. VCOL = 24V!.TA = 25°C
VCC1 .. ~.5V. Voor .. OV. ISOURCE " -6OOmA
TA :,.~5·C
VIN =5.5V
SOO
150
0.90
0.43 0.70
1
VIN =0.4V
','
40
..
""
8-46
_.
'.
160
.
...
200
200
0.90
0.43 0.75
...
4
VIN =.2.4V
-1.0
-1.0
-1.6
-4.0
-6.4"
0.8
-1.7
'"
.
V
V
V
IIA
I!A
V
V
1
4
mA
niA
40
'~
160
I!A
-1.6 rnA
4.0. -6.4 ·'mA.
-1.0
SG55327/SG75327
ELECTRICAL SPECIFICATIONS (continued)
Parameter
I
SG55327
I SG75327
I
I Min. I Typ. I Max. I Min. I Typ. Max. I
Test Conditions
Static Section (continued)
Supply Current (ICC(OFF)
From Vcc,
From VCC2
Supply Current (lCC(ON)
Units
All outputs off, all inputs at 5V, TA = 25°C
7.0
13
10
20
7.0
13
10
20
mA
mA
8.0
36
12
55
8.0
36
12
55
mA
mA
One output on, ISOURCE = -50mA,
VCOl = 6V, TA = 25°C
From Vec,
From V"".
Parameter
To (output)
Dynamic Section (Note 5)
Propagation Delay, Low to High (TPLH)
Propagation Delay, High to Low (TPHL)
Transition Time, Low to High (TTLH)
Transition Time, High to Low (TTHL)
High-Level Output Voltage (VOH)
I SG55327175327 J
I Min. I Typ. Max. I
Test Conditions
Coil. W, Z or X, Y
Coli. W, Z or X, Y
W, X, Y, orZ
W, X, Y, orZ
Coil. W, Z or X, Y
Vs = VCC2 = 15V, Rl = 24n
Vs = VCC2 = 15V, Rl = 24n
VCOL = VCC2 = 20V, Rl = lOOn
VCOl = VCC2 = 20V, Rl = loon
Vs = VCC2= 24V, Rl = 47n,
ISINK = 500mA
35
30
30
10
Units
55
55
Vs-25
ns
ns
ns
ns
mV
Note 4. Under these conditions, not more than one output is to be on anyone time.
Note 5. Unless otherwise specified, Vee, = 5V, CL = 25pF, and TA = 25°C.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
16-PIN CERAMIC DIP
J-PACKAGE
SG55327J/883B
SG55327J
SG75327J
16-PIN PLASTIC DIP
N - PACKAGE
SG75327N
16-PIN CERAMIC
FLAT PACK
F-PACKAGE
Ambient
Temperature Range
Connection Diagram
-55°C to 125°C
-55°C to 125°C
O°Cto 70°C
v""
w
A
NODER
RM
O°C to 70°C
B
x
GND (Nole3)
SG55327F/883B
SG55327F
-55°C to 125°C
-55°C to 125°C
v",
w
A
NODER
R.,
B
X
GND
COLLECTORS W, Z
Z
D
s
v""
C
y
COLLECTORS x, Y
COLl.W,Z
Z
D
S
Vee1
C
Y
COLl.X, Y
Note 1. All packages are viewed from the top.
Note 2. Contact factory for LCC.
Note 3. Pin 8 is in electrical contact with the metal base.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
8-47
8- 48
THUMB INDEX
SILICON
GENERAL
•
I
TABLE OF CONTENTS
II
I
PART NUMBER INFORMATION
•
I
GENERAL INFORMATION
III
II I
II I
MOTION CONTROL CIRCUrrS
•
OPERATION AMPLIFIERS AND COMPARATORS
I
III
I
III
III
III
III
POWER SUPPLY CIRCU~TS
!POWER DRIVIER AND
~NTERfACIE C~RCU~TS
CORE MEMORY CIRCUITS
AUTOMOTIVE CIRCUITS
OTHER CIRCUITS
PACKAGE INFORMATION
APPLICATION INFORMATION
SALES OFFICES
9-1
SELECTION GUIDE
AUTOMOTIVE CIRCUITS
SILICON
GENERAL
LOW DROPOUT VOLTAGE REGULATORS
LINEAR INTEGRATED CIRCUITS
Device Type
Output
Current
Output
Voltages
Maximum
Input Voltage
Initial
Tolerance
Key Features
Packages
P
SG29055
O.75A
5V,5V
26V
±5%
• Input I output difierentialless than O.SV at O.SA
SG29055A
O.7SA
SV,SV
26V
±2%
• Dual outputs
SG29085
O.75A
8V,SV
2SV
±5%
• Low quiescent current in the standby mode
SG29085A
O.7SA
8V,SV
26V
±2%
• Reverse battery protection
SG29125
O.7SA
12V,SV
26V
±5%
• -SOY Reverse transient protection
SG29125A
O.7SA
12V,SV
2SV
±2%
• Thermal shutdown protection
• SV 11 OmA standby output
• SOV load dump protection
• ONIOFF switch for high current output
• Available in 5 - pin TO-220 package
I
See General Information Section regarding capabilities for custom automotive circuits
December 1988
9-2
I
;;9
SG29055155A
SILICON
GENERAL
e
LOW DROPOUT DUAL REGULATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG29055/55A is a dual 5V/5V positive voltage regulator. One output is a high
current (up to 750 mAl regulator that can be turned on or off by a high impedance low
current TTL compatible switch. The second or standby output remains on regardless.
The on/off switch not only shuts off the high current output but actually puts the IC in
a micropower mode making possible a low quiescent current. This unique characteristic coupled with an extremely low dropout, (.55V for output current of 10mA) makes
the SG29055/55A well suited for power systems that require standby memory. The
SG29055/55A includes other features which were originally designed for automotive
applications. These include protection from reverse battery installations and double
battery jumps. The high current regulator has overvoltage shutdown to protect both the
internal circuitry and the load during line transients, such as load dump (60V). In
addition, the high current regulator design also has built-in protection for short circuit
and thermal overload. During these fault conditions of the primary regulator the
standby regulator will continue to power its load.
• 2% Internally Trimmed Outputs
• Two regulated outputs
• Output current in excess of
750mA
• Low quiescent current standby
regulator
• Input-output differential less than
O.6VatO.5A
• Reverse battery protection
• SOV load dump protection
• -50V reverse transient protection
• Short circuit protection
• Internal thermal overload protection
• Available in plastic TO-220
• ON/OFF switch for high current
output
The SG29055 is the 5 volt, ±5% version of a family of dual regulators with a standby
output voltage of 5V. Other high current outputs of 8.2V and 12V are available Also
available is the SG29055A which offers an improved output voltage tolerance of ±2%.
They are available in the plastic TO-220 power package and are designed to function
over the automotive ambient temperature range of -40°C to 85°C.
• Required if regulator is located far from power
supply filter.
•• Required for stability. May be increased without
bound. Capacitor must be rated to operate at the
minimum temperature expected for the regulator
system.
TYPICAL APPLICATION CIRCUIT
INPUT VOLTAGE
+
o.WFT
C1'"
SG29055/55A
2
OUTPUT VOLTAGE
(SV. 7S0mA)
OVERVOLTAGE
THERMAL
SHUTDOWN
ON/OFF SWITCH
(for output voltage only)
4
5
STANDBY OUTPUT
(SV. lOrnA)
S.6V
+
3
GROUND
April 1990
9-3
SG290SSISSA
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage (V IN ) .................................... .............. -15V to 2SV
Storage Temperature Range (TSTG) ................... -S5°C to 150°C
ON/OFF Switch ...................................................... -0.3Vto VIN
Operating Junction Temperature (T) .....................:......... 150°C
Note 1. Exceeding these values may destroy this part. The SG290SS/SSA will not function properly at these maximum ratings.
THERMAL DERATING CURVES
5.0
50
4.0
40
~
~
~
~
13.0
,
i5 2.0
g .........
~
i5 20
; r--...
i
~'A
a
I
~
o~
1.0
0
25
50
75
100
AMBIENT TEMPERATURE -
30
10
.........
125
150
a
175
-c
0
'"
25
A
(s..
~~
~0"'\,
~
"
75
100
"-
125
150
175
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Notes 2 & 3)
Reverse Polarity D.C. Input Voltage (VIN)
Input Voltage (VIN) ...................................................... SV to 2SV
ON/OFF Threshold Voltage
(Vo;': -O.SV, lsn load) ........................................... -15V max.
Low Level, VIL (Vour is OFF) .................................. 0.8V max.
Reverse Polarity Transient Input Voltage (V IN)
High Level, VIH (Vour is ON) .................................... 2.0V min.
(1% duty cycle, T ~ lOOms, yo;': -9V, lsn load) .... -50V max.
Load Current (with adequate heatsinking) ......... 5mA to 750mA
Output Capacitor with ESR of 10n max.
Maximum Line Transient (Load Dump) V0 ~ 5.5V ...... 60V max.
(VOUT to GND & VSBto GND) ................................... lOI!F min.
Operating Ambient Temperature Range (T)
Input Capacitor (VIN to GND) ................................... 0.1 IlF min.
SG29055/55A ................................................. -40°C to 8SoC
Note 2. Range over which the device is functional.
Note 3. During 60V load dump, VSB shall not be less than 4.7SV at lOUT = lOrnA.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of T. = 2S'C. V," = 14V. 10 = SOOmA for VOUT and
lOrnA for VSB and are for DC characteristics only. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
I SG290S5/55A
Parameter
Test Conditions
Units
I Min. ITyp. IMax.
Voltage Output (Vour) Section
Output VoHage (Note 4)
6V SVIN S 2SV, 10 S 500mA, -40°C S TA S 85°C
SG29D55
4.75 5.00 S.25
V
SG290S5A
4.90 5.00 5.10
V
Line Regulation
4
25
9V ~ VIN ~ lSV, 10 = SmA
mV
10 50
SV S VIN S 26V, 10 = SmA
mV
Load Regulation
10
50
5mA ~ '0 ~ 500mA
mV
Output Impedance
200
50DmAoc and 1om~MS' 1DOHz - 10kHz
n
Quiescent Current
'0 slOmA, No Load on Standby
3
mA
10 = 500mA, No Load on Standby
55 100
mA
10 = 750mA, No Load on Standby
120
mA
Output Noise Voltage
10Hz -100kHz
100
IlVRMs
Long Term Stability
20
mV/l000hr
Ripple Rejection
Fo= 120Hz
66
dB
Dropout Voltage
0.45 O.S
10 = 500mA
V
0.82
V
'0 = 750mA
Current Limit
0.75 1.4
A
Maximum Operational Input Voltage
26
31
V
Maximum Line Transient
60
70
Vo~5.5V
V
10 = 10mA, Pin 4 =2.4V
10
ON/OFF Switch (IIJ
IlA
ON/OFF Switch (I )
-10
'0 = 10mA, Pin 4 = 0.4V
I!A
9-4
SG290SSISSA
ELECTRICAL SPECIFICATIONS (continued)
Parameter
I SG29055/55A I
I Min·1 TYP·IMax·1
Test Conditions
Standby Output (VSB) Section
Output Voltage (Note 4)
Tracking
Line Regulation
Load Regulation
Output Impedance
Quiescent Current
Output Noise Voltage
Long Term Stability
Ripple Rejection
Dropout Voltage
Current Limit
Maximum Operational Input Voltage
6V ~ V,N ~ 26V, 10 ~ 1OmA, -40°C ~ TA ~ 85°C
VOUT - Standby Output Voltage
6V ~ V,N ~ 26V
lmA ~ 10 ~ 10mA
1mA DC and 1mAAMS ' 100Hz - 10kHz
10 ~ 10mA, VouPFF
10Hz - 100kHz
4.75
Fa; 120Hz
10 ~ 10mA
4.5V
~
25
60
Vn ~ 6V
Units
5.0 5.25
V
50 200
mV
4
50
mV
10
50
mV
1
n
1.2
3
mA
300
/LV AMS
20
mV/l000hr
66
dB
0.55 0.7
V
70
mA
70
V
Note 4. The temperature extremes are guaranteed but not 100% production tested.
TYPICAL CIRCUIT WAVEFORM
60V
\
INPUT
VOLTAGE
PIN 1 (V)
14V
~
26V
I
I
14V
I
4V
OV
ON/OFF
SWITCH
0::
OUTPUT
VOLTAGE
PIN 2 (V)
5V
STANDBY
VOLTAGE
PIN 5 (V)
5V
SYSTEM
CONDITION
OV
~
~
5.0V
II
5.0V
5.0V
1\ ~
I
I
I
TURN
ON
LOAD
DUMP
~
I
I
LINE NOISE,
ETC.
LOWV1N
5.0V
I
~
3.5V
I
Your
SHORT
5.0V
I
THERMAL
SHUTDOWN
I
TURN
OFF
CIRCUIT
APPLICATION NOTES
The advantages of using a low-dropout regulator such as the
SG29055/55A are the need for less "headroom" for full regulation,
and the inherent reverse polarity protection provided by the PNP
output device. A typical NPN regulator design requires an input
to output differential of approximately two volts minimum. This is
due to the 2Vbe + Vcesat olthe NPN Darlington used in the output,
coupled with the voltage drop across the current limit resistor. In
contrast, the "PNP Regulator" uses a single series pass transistor
with its single Vcesat, thus the lower input to output voltage
differential or dropout voltage.
In addition to a low dropout voltage, an important advantage of the
SG29055/55A series is low quiescent current in the standby
mode. When the high current or primary regulator is shut off, the
9-5
regulator enters a micropower mode. Here all but the most
essential circuitry to power the standby output is deactivated. This
allows the lowest possible quiescent current (typical around
1.2mA), a vital factor when used in a battery powered system.
In some applications the regulator output voltage is used not only
as a power supply but also as a voltage reference for control
systems. In such cases not just the temperature stability of the
output is important but also the initial accuracy. The SG29055/
55A fills this need as the internal bandgap reference is trimmed
allowing a typical output voltage tolerance of ±1 %.
SG29055155A
APPLICATION HINTS
EXTERNAL CAPACITORS
To stabilize the outputs and prevent oscillation (perhaps by many
volts) external capacitors are required. The minimum recommended value for the output capacitors is 1O~F, although the
actual size and type will likely vary according to the pallicular
application, e.g., operating temperature range and load. Another
consideration is the effective series resistance (ESR) of the
capacitor. Capacitor ESR will vary by manufacturer. Consequently, some evaluation may be required to determine the
minimum value of the output capacitors. Generally worst case
occurs at the maximum load and minimum ambient temperature.
Since the standby output is shunted with an internal S.SV zener,
the current through the external resistor should be sufficient to
bias internal resistors up to this point. Approximately SO~F will
suffice, resulting in a 10k external resistor for most applications
(Figure 1).
v"
R,
10K
SG29055/55A
The size of the output capacitor can be increased to any value
above the minimum. One possible advantage of this would be to
maintain the output voltage during brief periods of negative input
transients
~ ~Tfr~~~Y
C3
The output capacitors chosen should be rated for the full range of
ambient temperature over which the circuit will be exposed and
expecied io operaie. For example, many aluminum iype elecirolytic capacitors will freeze at -30°C. The effective capacitance is
reduced to zero in such a situation. Capacitors rated for -40°C
operation must be used in order to maintain regulator stability at
that temperature. Tantalum capacitors satisfy this requirement.
FIGURE 1. Disabling Standby Output to Eliminate C3
HIGH CURRENT OUTPUT
The high current regulated outputfeatures fault protection against
overvoltage as well as a thermal shutdown feature. If the input
voltage rises above 33V (load dump), the high current output
shuts down automatically. The internal circuitry is thus protected
and the IC is able to survive higher voltage transients than might
otherwise be expected. The thermal shutdown of the high current
output effectively guards against overheating of the die since this
section of the IC is the principle source of power dissipation on the
chip.
STANDBY OUTPUT
The SG290SS/SSA differs from most fixed voltage regulators in
that it is equipped with two regulator outputs instead of one. The
additional output is intended for use in systems requiring standby
memory circuits. While the high current regulator output can be
controlled with the ON/OFF pin described below, the standby
remains on under all conditions as long as sufficient input voltage
is applied to the IC. Thus, memory and other circuits powered by
this output remain unaffected by positive line transients, thermal
shutdown, etc.
ON/OFF SWITCH
The ON/OFF pin is a high impedance low current switch that
controls the main output voltage (pin 2). This is directly compatible with ailS volt logic families. For use with open collector logic
outputs, a 1OOk resistor from this pin to a SV supply, such as Pin
S, is required.
The standby regulator circuit is designed so that the quiescent
current to the IC is very low «I.SmA) when the other regulator
output is off.
If the standby output is not required it can be disabled. This is
accomplished by connecting a resistor from the standby output to
the supply voltage, thereby also eliminating the requirement for a
more expensive output capacitor to prevent unwanted oscillations. The resistor value depends upon the minimum input
voltage expected for a given system.
CONNECTION DIAGRAM & ORDERING INFORMATION (See Note Below)
Package
5-PIN TO-220 PLASTIC
P- PACKAGE
Part No.
SG290SSP
SG290SSAP
Ambient
Temperature Range
-40°C to 8SoC
-40°C to 85°C
Connection Diagram
r - , - . - -_______ 5
Irl
GND-f
~-j
~:::::::::~
8T ANBY OUTPUT
ON/OFF SWITCH
GROUND
OUTPUT VOLTAGE (V OUT)
INPUT VOLTAGE (V"i
Note: 1. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121 • TWX: 910-596-1804. FAX: (714) 893-2570
9-S
SG29085/85A
SILICON
GENERAL
LOW DROPOUT DUAL REGULATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG29085/85A is a dual 8.2V/5V positive voltage regulator. One output is a high
current (up to 750 mAl regulator that can be turned on or off by a high impedance low
current TTL compatible switch. The second or standby output remains on regardless.
The on/Dff switch not only shuts off the high current output but actually puts the IC in a
micropower mode making possible a low quiescent current. This unique characteristic
coupled with an extremely low dropout, (.55V for output current of 10mA) makes the
SG29085/85A well suited for power systems that require standby memory. The
SG29085/85A includes other features which were originally designed for automotive applications. These include protection from reverse battery installations and double battery
jumps. The high current regulator has overvoltage shutdown to protect both the internal
circuitry and the load during line transients, such as load dump (60V). In addition, the high
current regulator design also has built-in protection for short circuit and thermal overload.
During these fault conditions of the primary regulator the standby regulator will continue
to power its load.
• 2% Internally Trimmed Outputs
• Two regulated outputs
• Output current in excess of
750mA
• Low quiescent current standby
regulator
• Input-output differential less than
O.6VatO.5A
• Reverse battery protection
• 60V load dump protection
• -50V reverse transient protection
• Short circuit protection
• Internal thermal overload protection
• Available in plastiC TO-220
• ON/OFF switch for high current
output
The SG29085 is the 8.2 volt, ±5% version of a family of dual regulators with a standby
output voltage of 5V. Other high current outputs of 5 and 12 volts are available. Also
available is the SG28085A which offers an improved output voltage tolerance of ±2%.
They are available in the plastic TO-220 power package and are designed to function over
the automotive ambient temperature range of -40°C to 85°C.
• Required if regulator is located far from power
supply filter.
.. Required for stability. May be increased without
bound. Capacitor must be rated to operate at the
minimum temperature expected for the regulator
system.
TYPICAL APPLICATION CIRCUIT
INPUT VOLTAGE
SG29085/85A
2
OUTPUT VOLTAGE
(8.2V. 750mA)
OVERVOLTAGE
THERMAL
SHUTDOWN
ON/OFF SWITCH
(for output voltage only)
4
5
STANDBY OUTPUT
(5V. 10mA)
+
3
GROUND
April 1990
9-7
cs..
10~F
•
SG29085185A
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage (VIN) .................................................. -1SV to 2SV
Storage Temperature Range (TSTG) ••••••••••••• , •••• -SsoC to 1S0°C
ONfOFF Switch ...................................................... -0.3V to VIN
Operating Junction Temperature (TJ) ............................... 1S0°C
Note 1. Exceeding these values may destroy this part. The SG290BS and SG290BSA will not function properly at these maximum ratings.
THERMAL DERATING CURVES
50
so
40
40
~
~
13.0
,
~
~
1.0
r-....
~
~
m
o~
0
"
50
"
'00
"
"-
20
i
~
',0
0
6
~. ~",
30
A
rs~~
·0 '0..
~
'0
,,,..........
0
m
150
AMBIENT TEMPERATURE - "C
0
"
50
"
'00
'"
125
CASE TEMPERATURE - 'C
150
m
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Notes 2 & 3)
Input Voltage (VIN) ...................................................... 9V to 2SV
ONfOFF Threshold Voltage
Low Level, VIL (VOUT is OFF) .................................. 0.8V max.
High Level, VIH (VOUT is ON) .................................... 2.0V min.
Load Current (with adequate heatsinking) ......... SmA to 7S0mA
Maximum Line Transient (Load Dump) Vo S S.SV ...... SOV max.
Input Capacitor (VIN to GND) ................................... 0.1 IlF min.
Reverse Polarity D.C. Input Voltage (V IN)
(Vo ~ -O.SV, 1S0 load) ......................:.................... -1SV max.
Reverse Polarity Transient Input Voltage (V IN)
(1% duty cycle, T S 100ms, Vo~ -9V, 1S0 load) ... -SOY max.
Output Capacitor with ESR of 100 max.
(VOUT to GND & VSBto GND) ................................... 10llF min.
Operating Ambient Temperature Range - (T)
SG2908Sf8SA .......................... :...................... -40°C to 85°C
Note 2. Range over which the device is functional.
Note 3. During SOV load dump, VSB shall not be less than 4.7SV at lOUT = 1OmA.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambienttemperature ofT, = 2SoC. Y'N = 14V, 10 = SOOmA for VOUT and 10mA
for VSB and are for DC characteristics only. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to
the ambient temperature.)
I SG29085f85A I Units
Parameter
Test Conditions
I Min. I Typ. IMax. I
Voltage Output (VOUT) Section
Output VoHage(Note 4)
9V S VIN S 2SV, 10 S 500mA, -40°C S TA S 85°C
SG2908S
7.8 8.2 8.S
V
SG29085A
8.0 8.2 8.4
V
Line Regulation
4
2S
9V S VIN S 1SV, 10 = SmA
mV
10
50
9V S VIN S 2SV, 10 = SmA
mV
Load Regulation
SmA S 10 S SOOmA
10
SO
mV
Output Impedance
500mAoc and 10mAms, 100Hz -10kHz
200
a
Quiescent Current
10 S 10mA, No Load on Standby
3
mA
SS 100
10 = SOOmA, N,o Load on Standby
mA
10 = 7S0mA, No Load on Standby
120
mA
Output NOise VoHage
10Hz -100kHz
100
jJ.V RMS
Long Term Stability
20
mVf1000hr
Ripple Rej8ction
66
Fo= 120Hz
dB
Dropout Voltage
O.4S O.S
10= SOOmA
V
0.75 0.82
10 = 750mA
V
1.4
Current Limit
A
Maximum Operational Input Voltage'
60 31
V
Maximum Line Transient
Vo S9V
70
V
ON/OFF SWitch (IIH)
10 10mA, Pin 4 .. 2.4V
10
J.A.A
-10
ON/OFF Switch (IlL)
10 = 10mA, Pin 4 = 0.4V
J.A.A
=
9-8
SG29085185A
ELECTRICAL SPECIFICATIONS (continued)
Parameter
I
Test Conditions
Standby Output (VS8) Section
Output Voltage (Note 4)
Tracking
Line Regulation
Load Regulation
Output Impedance
Quiescent Current
Output Noise Voltage
Long Term Stability
Ripple Rejection
Dropout Voltage
Current Limit
Maximum Operational Input Voltage
SG29085/85A
Min. Typ. Max.
4.75
6V S Y'N S 26V, 10 S 10mA, -40°C S TA S 85°C
Vour - Standby Output Voltage
6VSV ,N S26V
1mA S 10 S 10mA
1mADe and 1mARMS ' 100Hz - 10kHz
10 S 10mA, VOUTOFF
10Hz -100kHz
Fa = 120Hz
loS 10mA
25
60
4.5V S VoS 6V
Units
5.0 5.25
V
50 200
mV
4
50
mV
10
50
mV
1
n
1.2
3
rnA
300
IlVRMS
20
mV/1000hr
66
dB
0.55 0.7
V
70
rnA
70
V
Note 4. The temperature extremes are guaranteed but not 100% production tested.
TYPICAL CIRCUIT WAVEFORM
INPUT
VOLTAGE
PINl (V)
GOV
1\
14V
OV
ON/OFF
SWITCH
0.::
OUTPUT
VOLTAGE
PIN2 (V)
5V
STANDBY
VOLTAGE
PIN5 (V)
5V
OV
~
V
I
8.2V
I
8.2V
\ I~
14V
I
~
I
TURN
ON
I
4V
~
8.2V
I
SYSTEM
CONDITION
~
26V
I
LOAD
DUMP
~
I
I
LINE NOISE.
ETC.
LOWV1N
I
V~
SHORT
CIRCUIT
5.0V
I
THERMAL
SHUTDOWN
I
TURN
OFF
APPLICATION NOTES
The advantages of using a low-dropout regulator such as the
SG29085/85A are the need for less "headroom" for full regulation,
and the inherent reverse polarity protection provided by the PNP
output device. A typical NPN regulator design requires an input
to output differential of approximately two volts minimum. This is
due to the 2Vbe + Vcesat olthe NPN Darlington used in the output,
coupled with the voltage drop across the current limit resistor. In
contrast, the "PNP Regulator" uses a single series pass transistor with its single Vcesat, thus the lower input to output voltage
differential or dropout voltage.
regulator enters a micropower mode. Here all but the most
essential circuitry to power the standby output is deactivated. This
allows the lowest possible quiescent current (typical around
1.2mA), a vital factor when used in a battery powered system.
In addition to a low dropout voltage, an important advantage of the
SG29085/85A series is low quiescent current in the standby
mode. When the high current or primary regulator is shut off, the
9-9
In some applications the regulator output voltage is used not only
as a power supply but also as a voltage reference for control
systems. In such cases not just the temperature stability of the
output is important but also the initial accuracy. The SG29085/
85A fills this need as the internal bandgap reference is trimmed
allowing a typical output voltage tolerance of ±1 %.
SG29085185A
APPLICATION HINTS
EXTERNAL CAPACITORS
To stabilize the outputs and prevent oscillation (perhaps by many
volts) external capacitors are required. The minimum recommended value for the output capacitors is 101lF, although the
actual size and type will likely vary according to the particular
application, e.g., operating temperature range and load. Another
consideration is the effective series resistance (ESR) of the
capacitor. Capacitor ESR will vary by manufacturer. Consequently, some evaluation may be required to determine the
minimum value of the output capacitors. Generally worst case
occurs at the maximum load and minimum ambient temperature.
Since the standby output is shunted with an internal 5.SV zener,
the current through the external resistor should be sufficient to
bias internal resistors up to this point. Approximately SOIlF will
suffice, resulting in a 10k external resistor for most applications
(Figure 1).
v"
R,
10K
SG29085/85A
The size of the output capacitor can be increased to any value
above the minimum. One possible advantage of this would be to
maintain the output voltage during brief periods of negative input
transients
~ ~1~~~~Y
I
I
I
I
±...L..
""'
C3
I
I
I
The output capacitors chosen should be rated forthe full range of
ambient temperature over which the circuit will be exposed and
expected to operate. For example, many aluminum type electrolytic capacitors will freeze at -30°C. The effective capacitance is
reduced to zero in such a situation. Capacitors rated for -40°C
operation must be used in order to maintain regulator stability at
that temperature. Tantalum capacitors satisfy this requirement.
STANDBY OUTPUT
The SG29085/85A differs from most fixed voltage regulators in
that it is equipped with two regulator outputs instead of one. The
additional output is intended for use in systems requiring standby
memory circuits. While the high current regulator output can be
controlled with the ON/OFF pin described below, the standby
remains on under all conditions as long as sufficient input voltage
is applied to the IC. Thus, memory and other circuits powered by
this output remain unaffected by positive line transients, thermal
shutdown, etc.
The standby regulator circuit is designed so that the quiescent
current to the IC is very low «1.5mA) when the other regulator
output is off.
I
-
...L
FIGURE 1. Disabling Standby Output to Eliminate C3
HIGH CURRENT OUTPUT
The high current regulated outputfeatures fault protection against
overvoltage as well as a thermal shutdown feature. If the input
voltage rises above 33V (load dump), the high current output
shuts down automatically. The internal circuitry is thus protected
and the IC is able to survive higher voltage transients than might
otherwise be expected. The thermal shutdown ofthe high current
output effectively guards against overheating of the die since this
section of the IC is the principle source of power dissipation on the
chip.
ON/OFF SWITCH
The ON/OFF pin is a high impedance low current switch that
controls the main output voltage (pin 2). This is directly compatible with all 5 volt logic families. For use with open collector logic
outputs, a lOOk resistor from this pin to a 5V supply, such as Pin
5, is required.
If the standby output is not required it can be disabled. This is
accomplished by connecting a resistor from the standby output to
the supply voltage, thereby also eliminating the requirement for a
more expensive output capacitor to prevent unwanted oscillations. The resistor value depends upon the minimum input
voltage expected for a given system.
CONNECTION DIAGRAM & ORDERING INFORMATION (See Note Below)
Package
5-PIN TO-220 PLASTIC
P- PACKAGE
Part No.
SG29085P
SG29085AP
Ambient
Temperature Range
-40°C to 85°C
-40°C to 85°C
Connection Diagram
STANBY OUTPUT
ON/OFF SWITCH
GROUND
OUTPUT VOLTAGE (V"",)
INPUT VOLTAGE (V.)
Note: 1. All packages are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641. (714) 898-8121. TWX: 910-596-1804. FAX: (714) 893-2570
9 -10
SG291251125A
SILICON
GENERAL
LOW DROPOUT DUAL REGULATOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG29125/125A is a dual 12V/5V positive voltage regulator. One output is a high
current (up to 750 mAl regulator that can be turned on or off by a high impedance low
current TTL compatible switch. The second or standby output remains on regardless.
The on/off switch not only shuts off the high current output but actually puts the IC in
a micropower mode making possible a low quiescent current. This unique characteristic coupled with an extremely low dropout, (.55V for output current of 10mA) makes
the SG29125/125A well suited for power systems that require standby memory. The
SG29125/125A includes other features which were originally designed for automotive
applications. These include protection from reverse battery installations imd double
battery jumps. The high current regulator has overvoltage shutdown to protect both the
internal circuitry and the load during line transients, such as load dump (60V). In
addition, the high current regulator design also has built-in protection for short circuit
and thermal overload. During these fault conditions of the primary regulator the
standby regulator will continue to power its load.
o 2% Internally Trimmed Outputs
• Two regulated outputs
o Output current in excess of
750mA
• Low quiescent current standby
regulator
• Input-output differential less than
O.6Vat O.5A
• Reverse battery protection
• 60V load dump protection
o -50V reverse transient protection
o Short circuit protection
• Internal thermal overload protection
o Available in plastiC TO-220
o ON/OFF switch for high current
output
The SG29125 is the 12 volt, ±5% version of a family of dual regulators with a standby
output voltage of 5V. Other high current outputs of 5 and 8.2 volts are available. Also
available is the SG29125A which offers an improved output voltage tolerance of ±2%.
They are available in the plastic TO-220 power package and are designed to function
over the automotive ambient temperature range of -40°C to 85°C.
TYPICAL APPLICATION CIRCUIT
• Required if regulator is located far from power
supply filter.
•• Required for stability. May be increased without
bound. Capacitor must be rated to operate at the
minimum temperature expected for the regulator
system.
INPUT VOLTAGE
C1'
+
O.1~FT
SG29125/125A
2
OUTPUT VOLTAGE
(12V. 750mA)
OVERVOLTAGE
THERMAL
SHUTDOWN
ON/OFF SWITCH
(for output voltage only)
4
STANDBY OUTPUT
(5V. 10mA)
+
3
GROUND
April 1990
9 -11
C3"
10~F
SG29125/125A
ABSOLUTE MAXIMUM RATINGS (Note I)
Storage Temperature Range (TSTG) .................. -65~C to 150°C
Operating Junction Temperature (T) ............................... 150°C
Input Voltage (V,N) ................................................... -15V to 26V
ON/OFF Switch ....................................................... -0.3V to Y'N
Note I. Exceeding these values may destroy this part. The SG29125 and SG29125A will not function properly at these maximum ratings.
THERMAL DERATING CURVES
5.0
50
.0
'.0
I'!
i"
~
~
,
,
30
is
~
ill
i5
30
........
is
2.0
~
i
~
ill
1S
~,~
0
~~r.
0
"
50
75
(s,
i
,Q.(4Sl;:
1.0
i'-..A A",
20
~ r-......
100
125
150
~c
0
175
AMBIENT TEMPERATURE - "C
,
~
'",
10
0
"
50
75
100
CASE TEMPERATURE -
i'..
125
150
175
'C.
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2 & 3)
Input Voltage (V,N) ..................................................... 13V to 26V
ON/OFF Threshold Voltage
Low Level, V'L (VOUT is OFF) .................................. 0.8V max.
High Level, V ,H (VOUT is ON) .................................... 2.0V min.
Load Current (with adequate heatsinking) ......... 5mA to 750mA
Maximum Line Transient (Load Dump) Va'" 5.5V ..... 60V max.
Input Capacitor (V,N to GND) ................................... 0.1 ",F min.
Reverse Polarity D.C. Input Voltage (V,N)
(Va .. -0.6V, 160 load) ........................................... -15V max.
Reverse Polarity Transient Input Voltage (V,N )
(1 % duty cycle, T", 1OOms, Va .. -9V, 160 load) ... -50V max.
Output Capacitor with ESR of 100 max.
(Vour to GND & VSBto GND) ................................... 10",F min.
Operating Ambient Temperature Range (T)
SG29125/125A ............................................... -40°C to 85°C
Note 2. Range over which the device is functional.
Note 3. During 60V load dump, VSB shall not be less than 4.75V at loUT = lOrnA.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of TA = 25°C, Y'N =14V, 10 = 500mA for VOUT and
lOrnA forVsB and are for DC characteristics only. Low duty cycle pulse testing techniques are used which maintains junction and cae temperatures
equal to the ambient temperature.)
I SG29125/125A I Units
Parameter
Test Conditions
I Min. ITyp. Max. I
Voltage Output (VOUT) Section
Output Voltage (Note 4)
13V '" Y'N '" 26V, 10 ", 500mA, -40°C", TA '" 85°C
SG29125
11.2 12 12.8
V
SG29125A
11.75 12 12,25
V
Line Regulation
4
25
mV
13V", Y'N '" 16V, 10 = 5mA
10
50
mV
13V", Y'N '" 26V, 10 = 5mA
Load Regulation
10
50
mV
5mA '" 10 '" 500mA
Output Impedance
200
500mAac and 10mARMs ' 100Hz - 10kHz
0
10 ", 10mA, No Load on Standby
Quiescent Current
3
mA
10 = 500mA, No Load on Standby
55 100
mA
10 = 750mA, No Load on Standby
120
mA
10Hz • 100kHz
Output Noise Voltage
100
I1V RMs
Long Term Stability
20
mV/l000hr
Ripple Rejection
66
Fa = 120Hz
dB
Dropout Voltage
0.45 0.6.
V
10 =500mA
0.75 0.82
10= 750mA
V
Current Limit
26
1.4
A
31
Maximum Operational Input Voltage
60
V
Maximum Line Transient
70
V
Va'" 13V
10
ON/OFF Switch (I,H)
10 = 10mA, Pin 4
2.4V
-10
ON/OFF Switch (I )
In = 10mA, Pin 4 =0.4V
=
9 -12
~
SG291251125A
ELECTRICAL SPECIFICATIONS (continued)
Parameter
I SG29125/125A I
Test Conditions
Standby Output (VSB) Section
Output Voltage (Note 4)
Tracking
Line Regulation
Load Regulation
Output Impedance
Quiescent Current
Output Noise Voltage
Long Term Stability
Ripple Rejection
Dropout Voltage
Current Limit
Maximum Operational Input Voltage
Min. Typ. Max.
4.75
6V :;; Y'N :;; 26V, 10 :;; 10mA, -40°C:;; TA :;; 85°C
VOUT - Standby Output Voltage
6V:;; Y'N :;;26V
1mA:;; 10 :;; 10mA
1mAcc and 1mAAMS ' 100Hz· 10kHz
10 :;; 10mA, VOUTOFF
10Hz • 100kHz
Fo = 120Hz
10:;;10mA
25
60
4.5V:;; Yo:;; 6V
Units
5.0 5.25
V
50 200
mV
4
50
mV
10
50
mV
1
n
1.2
3
rnA
300
~VRMS
20
mV/1000hr
66
dB
0.55 0.7
V
70
rnA
70
V
Note 4. The temperature extremes are guaranteed but not 100% production tested.
TYPICAL CIRCUIT WAVEFORM
INPUT
VOLTAGE
PIN1 tV)
SOV
14V
14V
OV
ON/OFF
SWITCH
0.::
OUTPUT
VOLTAGE
PIN 2 tV)
~
5V
OV
STANDBY
VOLTAGE
PIN5 tV)
SYSTEM
CONDITION
5.0V
5V
\GJ
I
I
TURN
ON
LOAD
DUMP
LINE NOISE.
ETC.
S~3'RT
THERMAL
SHUTDOWN
TURN
OFF
CIRCUIT
APPLICATION NOTES
The advantages of using a low-dropout regulator such as the
SG29125/125A are the need for less "headroom" for full regulation, and the inherent reverse polarity protection provided by the
PNP output device. A typical NPN regulator design requires an
input to output differential of approximately two volts minimum.
This is due to the 2Vbe + Vcesat of the NPN Darlington used in the
output, coupled with the voltage drop across the current limit
resistor. In contrast, the "PNP Regulator" uses a single series
pass transistor with its single Vcesat, thus the lower inputto output
voltage differential or dropout voltage.
regulator enters a micropower mode. Here all but the most
essential circuitry to power the standby output is deactivated. This
allows the lowest possible quiescent current (typical around
1.2mA), a vital factor when used in a battery powered system.
In some applications the regulator output voltage is used not only
as a power supply but also as a voltage reference for control
systems. In such cases not just the temperature stability of the
output is important but also the initial accuracy. The SG291251
125A fills this need as the internal bandgap reference is trimmed
allowing a typical output voltage tolerance of ±1 %.
In addition to a low dropout voltage, an important advantage of the
SG29125/125A series is low quiescent current in the standby
mode. When the high current or primary regulator is shut off, the
9 -13
SG291251125A
APPLICATION HINTS
EXTERNAL CAPACITORS
To stabilize the outputs and prevent oscillation (perhaps by many
volts) external capacitors are required. The minimum recommended value for the output capacitors is 10IlF, although the
actual size and type will likely vary according to the particular
application, e.g., operating temperature range and load. Another
consideration is the effective series resistance (ESR) of the
capacitor. Capacitor ESR will vary by manufacturer. Consequently, some evaluation may be required to determine the
minimum value of the output capaCitors. Generally worst case
occurs at the maximum load and minimum ambient temperature.
Since the standby output is shunted with an internal5.6V zener,
the current through the external resistor should be sufficient to
bias internal resistors up to this point. Approximately 60IJF will
suffice, resulting in a 10k external resistor for most applications
(Figure 1).
v.
Ro
10K
SG29125/125A
The size of the outpui capaCitor can be increased to any value
above the minimum. One possible advantage of this would be to
maintain the output voltage during brief periods of negative input
transients
---+-----<
STANDBY
I
OUTPUT
I
I
I
I
t..L
,..-,-...C3
I
I
I
The output capacitors chosen should be rated for the full range of
ambient temperature over which the circuit will be exposed and
expected to operate. For example, many aluminum type electrolytic capacitors will freeze at -30·C. The effective capacitance is
reduced to zero in such a situation. Capacitors rated for -40°C
operation must be used in order to maintain regulator stability at
that temperature. Tantalum capacitors satisfy this requirement.
STANDBY OUTPUT
The SG29125/125A differs from most fixed voltage regulators in
that it is equipped with two regulator outputs instead of one. The
additional output is intended for use in systems requiring standby
memory circuits. While the high current regulator output can be
controlled with the ON/OFF pin described below, the standby
remains on under all conditions as long as sufficient input voltage
is applied to the IC. Thus, memory and other circuits powered by
this output remain unaffected by positive line transients, thermal
shutdown, etc.
The standby regulator circuit is designed so that the quiescent
current to the IC is very low «1.5mA) when the other regulator
output is off.
I
-
J...
FIGURE 1. Disabling Standby Output to Eliminate C3
HIGH CURRENT OUTPUT
The high current regulated output features fault protection against
overvoltage as well as a thermal shutdown feature. If the input
voltage rises above 33V (load dump), the high current output
shuts down automatically. The internal circuitry is thus protected
and the IC is able to survive higher voltage transients than might
otherwise be expected. The thermal shutdown of the high current
output effectively guards against overheating of the die since this
section ofthe IC is the principle source of power dissipation on the
chip.
ON/OFF SWITCH
The ON/OFF pin is a high impedance low current switch that
controls the main output voltage (pin 2). This is directly compatible with all 5 volt logic families. For use with open collector logic
outputs, a 1OOk resistor from this pin to a 5V supply, such as Pin
5, is required.
If the standby output is not required it can be disabled. This is
accomplished by connecting a resistor from the standby output to
the supply voltage, thereby also eliminating the requirement for a
more expensive output capacitor to prevent unwanted oscillations. The resistor value depends upon the minimum input
voltage expected for a given system.
CONNECTION DIAGRAM & ORDERING INFORMATION (See Note Below)
Package
5-PIN TO·220 PLASTIC
p. PACKAGE
Part No.
SG29125P
SG29125AP
Ambient
Temperature Range
-40°C to 85°C
-40°C to 85°C
Connection Diagram
........... 5 STAN BY OUTPUT
ONIOFFSWITCH
- 3 GROUND
G N D : : : : : - 2 OUTPUT VOLTAGE (V""')
-.......1 INPUT VOLTAGE (V,,)
~_4
o
Note: 1. All parts are viewed from the top.
Silicon General •
11861 Western Avenue. Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910·596-1804. FAX: (714) 893-2570
9-14
!
,
THUMB INDEX
SILICON
GENERAL
8'
Ell
III
III
I
I
I
I
III
I
III
III
III
TABLE OfF CONTENTS
PART NUMBER INFORMATION
GIE~IERAlINfORMAT~ON
PlQWIEIA SIUJ[PlPlV CIRCllJnrS
MOTIO~ CO~TROl
CIRCUITS
POWIER DRIVIER A~D
OPIERAT~O~
~~TIERfACIE C~RCUITS
AMIPUfllERS AND COMPARATORS
CORE MEMORY
C~RCIUl~TS
AUTOMOT~VIE C~RCU~TS
OTHER CIRCUITS
PACKAGE INfORMATION!
APPLICATION
~NfORMATIONI
SALES OFFICES
10-1
I
I
I
I
I
I
I
I
I
I II
I
I
I
SELECTION GUIDE
OTHER LINEARCIRUITS
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
Device Type
Description
Typlcel Application
Key Features
Pkgs.
SG040
Dual Video
Amplifier
• Tape drives
• Low level audio stage
•
•
•
•
•
•
•
•
J, N, D
SG103/203/303
Voltage Reference
• Power supplies
• Signal conditioners
• Communications
• ±10% initial tolerance (for tighter tolerance contact
factory)
• Bandgap design
co La,·, dynamic impedance from 10J.LA to 10mA (improved over LM1 03)
• -lmVf'C temperature coefficient
• Output voltages: 1.8V, 2.0V, 2.2V, 2.4V, 2.7V, 3.0V,
3.3V, 3.6V, 3.9V, 4.3V, 4.7V, S.lV, S.6V
• Two terminal device
SG1401/2401/3401
High Frequency
Video Amplifier
• IF and RF amplifiers
• Symmetrical non-saturating
limiters
• Oscillators
• Automatic Gain Control
• Pulse and video amplifiication
• Low-level audiO stage~
•
•
•
•
•
•
20dB voltage gain at 100MHz
Sns rise and fall times
Fixed or variable gain
Single power supply voltage
Minimum external components
Symmetrical limiting
T,J
SG1402
Wideband
AmplifierlMultiplier
• High frequency amplifiers
• Modulators
• Automatic gain control
•
•
•
•
•
•
Single power supply voltage
Self-contained biasing
25dB voltage gain
Differential or single ended inputs and outputs
Large bandwidth
Low power dissipation
T,J
SG1503/250313503
2.SV Precision
Voltage Reference
• Power supplies
• Signal conditioners
• Communications
•
•
•
•
•
•
Bandgap design
Output voltage trimmed to ±1%
Input voltage range of 4.5V to 40V
Temperature coefficient of 10ppmf'C
Output current in excess of 10mA
Interchangeable with MC1S03 and ADS80
SG159511495
4 - Quadrant
Multiplier
•
•
•
•
•
•
•
•
•
•
•
Excellent linearity
Adjustable scale factor
Excellent temperature stability
Wide bandwidth
High input voltage range
Wide supply voltage operation
SG159611496
Balanced Modulatorl • AM, SSB, DSB, FSK, and FM
Demodulator
modulation or demodulation
• Phase detection
• Unear mixing and choppings
•
•
•
•
•
•
Excellent carrier suppression
Fully balanced inputs and outputs
Low Offsets and Drift
High common mode rejection
Adjustable gain and signal handling
Useful to 100MHz
Multipliers
Dividers
Square root functions
Phase detectors
Frequency doublers
January 1990
10 - 2
Two selectable independent channels
Wide bandwidth (20MHz) and low noise (SnV/V'Rz)
Input stages each with variable gain adjustment
No frequency compensation required
Internal bias supply provided to user
TTL compatible channel select
Replaces TL040
Available in SOIC and DIP packages
Z
V,T,M
J
J,T,F
SELECTION GUIDE
OTHER LINEAR CIRUITS
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
Device Type
Description
Typical Application
Key Features
Pkgs.
SG510A4/
SG510AR4
Read/Write
• Center-tapped ferrite heads
• Winchester Disk Drive
• Read Mode
- Controlled gain to 100VN
DW,N
Amplifier
- Low input noise
- High Bandwidth> 30M Hz
• Write Mode
- Write current range lOrnA to 40mA
- Programmable write current
- Error flag during fault mode
• Data Protection
SG541
Read Data
• Pin to pin compatible with SSI32P541
• Disk Drives
Processor
N,Q
• Level qualification supports high resolution MFM and
RLL encoded data retrieval
• Wide bandwidth AGC input amplifier
• Supports data rates up to 15 megabits/sec
• Standard 12V ±10% and 5V ±10% supplies
• Supports embedded servo pattern decoding
• Write to read transient suppression
• Fast and slow AGe attack regions for fast transient
recovery
SG3049
Dual High-Frequency • VHF amplifiers
Differential Amplifiers • VHF mixers
• Two differential amplifiers on a common substrate
J
• Independently accessible inputs and outputs
• IF amplifiers
• Balanced quadrature detectors
• Full military temperature range capability
• Sense amplifiers
SG3045/304613821
Transistor Arrays
• High Frequency Amplifiers
• Two NPN matched transistor pairs to ±O.5mV VBE
• Comparators
• 3 uncommited matched NPN transistors
• Relay drivers
• Operation from DC to 300MHz
• Lamp drivers
J, N
• High current gain
• High voltage capabilities (3821/3045)
SG31 83131 83A
Transistor Arrays
• High Frequency Amplifiers
• Five closely matched NPN transistors
• Comparators
• Relay drivers
• 50V VeE voltage (3183A)
• Collector current to 100mA
• Lamp drivers
• Low saturation voltage
January 1990
10 - 3
J, N
10-4
SG040
SILICON
ADVANCED DATA SHEET
GENERAL
LINEAR INTEGRATED CIRCUITS
TWO CHANNEL SELECTABLE VIDEO AMPLIFIER
DESCRIPTION
FEATURES
The SG040 is a two-channel selectable video amplifier intended for use as a preamplifier in the read chain of streaming tape drives. It offers two selectable, wide
bandwidth (20MHz), low noise (5nV/v'RZ) differential input/differential output
pre-stages. Each pre-stage offers variable gain adjustment through the use of
an external resistor or potentiometer. Channel multiplexing occurs based on a
logic "1" or "0" to the SELECT input pin. Special care has been taken to provide
sufficient channel separation between the two input stages. The SG040
typically dissipates less than 150mW and offers a bias supply for the center
tapped magnetic read heads. The SG040 is available in a 16-pin DIP or a 16pin SOIC package.
• Wide bandwidth (20MHz) and low noise
(5nV/v'Hz)
• Input stages each with variable gain
adjustment
• No frequency compensation required
• Internal bias supply provided to user
• TTL compatible channel select
• Replaces TL040
• Available in sOle and DIP packages
BLOCK DIAGRAM
GAIN
4
ADJUST 1B
VCC
IN- 2
~-
"'-
-04
N
~
w
-06
-0 S
-1.0
a
'0
20
30
~
'<
"w
""
40
N
"
i
.........
50
60
V
TA==2SoC
f =100KHz
.;-'-"" !"" rV
-2
;"
g
-6
-8
5
6
7
8
9
10
11
12 13 14 15 16
"AS - (0)
(v)
SUPPLY VOLTAGE -
FIGURE 6.
VOLTAGE GAIN VS. RADJ
120
80
II
ro
~
\
Vee 12V
Rt.. =TKO
110
ro
RAS=on
II-
~
w
"
'te"12V
0
"z
"8"
RL ",KO
RAB""'OO
0
TA=2SoC
3
10'
,cr
1111111
FREQUENCY -
10'
(Hz)
FIGURE 7.
OUTPUT VOLTAGE SWING VS. FREQUENCY
70
TA =2SoC
100
z
z
0
>=
«
0
G
\.
10
w
C>
70
~
10'
z
il
FIGURE 5.
VOLTAGE GAIN VS. SUPPLY VOLTAGE
1\
ro
~
-4
TEMPERA TURE _ (oC)
FIGURE4.
VOLTAGE GAIN VS. TEMPERATURE
10'
YIN =10mVp_p
il
f =lMHz
10'
(Hz)
FIGURE 3.
GAIN VS. FREQUENCY AS A FUNCTION
OF SUPPLY VOLTAGE
RAB""OO
z
\
w
C>
'<
"w
-
RAS",QO
I\.
il
«
----
10'
FREQUENCY -
FIGURE'.
PHASE VS. FREQUENCY AS A FUNCTION
OF SUPPLY VOLTAGE
ro
04
1111111
(Hz)
06
ro
\
RAS=on
TA =2SoC
20 104
10'
1\'
~ !j~~11
I
"AS"OO
1\
';-;-I(;e 6V
~
100
~
VCC==12V
h
\
50
60
w
~
y- ~~~'~'5V
~
80
I
70
60
10 5
10'
FR[QUENCY -
FIGURE 8.
COMMON MODE REJECTION RATIO
VS. FREQUENCY
10 -7
10'
(Hz)
10'
II
,0
;:!
90
\
50
l(;e- 12V
RL =TKO
TA=250C
40
,a,
11111111
FREQUENCY ~ (Hz)
FIGURE 9.
CHANNEL SEPARATION VS. FREQUENCY
,r:J
SG040
CHARACTERISTIC CURVES (continued)
10
V
1/
/
v
v
1/
100
lk
10k
TA =250 C
i
,I
2L-L....L---L--'---'-...L..L-.l-L....lL....L-l
5
6
LOAD RESISTANCE - (0)
FIGURE 10.
OUTPUT VOLTAGE SWING VS. LOAD RESISTANCE
;'
w
a'"'"
/
O~~~-L~=-~~II~
10
>z
/
7
8
9
"
0
11
3
10 11 12 13 14 15 16 17
13
15
17
SUPPLY VOLTAGE - (V)
SUPPLY VOLTAGE - (V)
FIGURE 11.
OUTPUT VOLTAGE SWING VS. SUPPLY VOLTAGE
FIGURE 12.
SUPPLY CURRENT VS. SUPPLY VOLTAGE
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No_
16-PIN CERAMIC DIP
J-PACKAGE
SG040J
16-PIN PLASTIC DIP
N - PACKAGE
SG040N
Ambient
Temperature Range
Connection Diagram
1 IN +
=~ -v
=
=
1 IN - .:: 2
GAIN ADJUST lA
3
GAIN ADJUST 1B
4
BIAS OUTPUT ... 5
SELECT
6
GND :-~ 7
=
;6 J 21N +
15:J 2 IN 14 J GAIN ADJUST 2B
13 J GAIN ADJUST 2A
12::J::J Voc,.
Vee
10:J GNO
11
OUT+ =~::J OUT·
16-PIN NARROW BODY
PLASTIC S.O.I.C.
D- PACKAGE
SG040D
1 IN +
l1NGAIN ADJUST lA
GAIN ADJUST lB
IT 1
IT
IT
IT 4
BIAS OUTPUT IT
SELECT IT
GND IT
7
,. I l
15Il
14 I l
13 I l
21N +
21NGAIN ADJUST 2B
GAIN ADJUST 2A
12::OIl
VCC(A)
11
Vc
10::0
GND
OUT + IT.....,..l.!!..._...:.crIl~ OUT·
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue' Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804 • FAX: (714) 893-2570
10-8
SGI03/SG203/SG303
SILICON
GENERAL
VOLTAGE REFERENCES
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1 03 is a two-terminal integrated circuit designed for analog
and/or digital applications requiring precision voltage reference.
The SG1 03 is an improved version of the National LM1 03 voltage
reference. The design uses the band-gap voltage of the silicon as
an internal reference for a tightly regulated output voltage. The
advantages of this method over single junction zener diodes are:
lower turn on drift, better temperature coefficient, sharper breakdown characteristics (line regulation) and lower dynamic impedance (load regulation). The I.C. is available in thirteen different
voltages ranging from 1.8V to 5.6V (See Table 1). The SG103 is
packaged in a hermetically sealed, modified TO-46 header and is
specified for operation over the full military ambient temperature
range of -55 0 C to +125 0 C.
•
•
•
•
Standard voltage tolerance ±10%
Precision band gap design
Exceptionally sharp breakdown
Low dynamic impedance from 10pA to 10mA
(improved over LM103)
• Improved temperature coefficient
• Low capacitance
• Performance guaranteed over full military
temperature range
HIGH RELIABILITY FEATURES -SG103
~
~
Available to MIL-STO - 883 and OESC SMO
SG level "S" processing available
REFERENCE VOLTAGES
BLOCK DIAGRAM
(+) Cathode
TABLE 1
?
Measured at IR
<
1.2V
BANDGAP
VOL TAGE
=1mA,
Voltage Tolerance ±1 0%
SG103 -1.8*
SG103 - 2.0
SG103 - 2.2
SG103 - 2.4*
SG103 - 2.7*
SG103 - 3.0
SG103 - 3.3
SG103 - 3.6
SG103 - 3.9
SG103 - 4.3
SG103 - 4.7*
SG103 - S.1*
SG103-S.6
* These are the voltages that are currently
available. Contact factory for product
availability for additional voltages.
(-) Anode
April 1990
10· 9
..
SGI03/SG203/SG303
ABSOLUTE MAXIMUM RATINGS (Note 1)
Reference Current .......................................................... 20mA
Forward Current ............................................................ 100mA
Operating Junction Temperature .................................... 150°C
Storage Temperature Range .......................... -65°C to + 150°C
Lead Temperature (Soldering, 10 Seconds) .................. 300°C
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to ground. All currents are positive into the
specified terminal.
THERMAL DERATING CURVES
25
5.0
20
4.0
~
~
~
I
~
1.5
I
6
6
~
~
C
~
~
C
1.0
~
~
0.5
0
0
3.0
2.0,
N~
1.0
I~"
1'0...."(1)
Z (2-PIN HERMETIC TO-46)
25
50
75
100
125
150
0
175
0
25
AMBIENT TEMPERATURE - 'C
50
75
100
CASE TEMPERATURE -
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
125
150
175
"c
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Reference Current ........................................................ <10mA
Forward Current ............................................................ <30mA
Note 2. Range over which the device, is functional
Operating Ambient Temperature Range
SG103 .......................................................... -55°C to 125°C
SG203 .............................................................. -25°C to 85°C
SG303 ................................................................ O°C to 70°C
ELECTRICAL SPECIFICATIONS
(These specifications apply for T. = 25'C and 1.BV < Vz < 5.6V unless stated otherwise. The diode should not be operated with shunt capacitances
between 100 pF and 0.Q1 /IF, unless isolated by at least a 300r.! resistor, as it may oscillate at some currents. For voltages between 4.3V and 5.6V,
the maximum shunt capacitance is 50pF rather than 1OOpF. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.)
Parameter
Reference Voltage Change
Reverse Dynamic Impedance (Note 3)
Reverse Leakage Current
Forward Voltage Drop
Peak-to-Peak Broadband Noise Voltage
Reference Voltage Change with Current
{Note 4)
Reference Voltage Temperature Coefficient
{Note 4)
Test Conditions
10pA:; IR '" 1 ~OpA
100pA '" IR", 1mA
1mA '" IR '" 10mA
IR =3mA
IR =0.3mA
V R = V z -0.2V
IF= 10mA
10Hz", f '" 100 kHz, IR = 1 mA
10pA '" IR '" 1OOpA
100pA", IR", 1mA
1mA",IR ", 10mA
100pA", IR '" 1mA
Note 3. Measured with the peak-to-peak change of reverse current equal to 10% of the DC reverse current.
Note 4. These specifications apply for -55°C < T. < +125°C.
10 -10
SG103{203{303
Min. Typ. Max.
60
120
15
50
50
150
5
25
15
60
2
5
0.7
0.8
1.0
300
200
60
200
-1.0
Units
mV
mV
mV
Q
Q
pA
V
pV
mV
mV
mV
mVrC
SGI03/SG203/SG303
CHARACTERISTIC CURVES
5
/
>
>
/
'I
w
'-'
-<
>::;
1.2
\REF-=47V
3
w
U
Z
0:
W
"W
0:
-<
0.8
>-'
>
0
0:
0.6
-<
3:
0:
0
0.4
"-
II
o
~
-55"0
0
/
W
1.0
0.2
o
o
7
4
8
10
r--r
rr
........
0
-20
0
"'
-30
w
'-'
-<
-40
0
-50
"-
r-...
o
10
100
11
TJ ~ 1-~50C
IIREF=4.7V
>
5
w
'"-::;-<
'\
>::;
>
J.....'i-o'
20
-10
'I
f-
i-"
FIGURE 2.
FORWARD DIODE CHARACTERISTICS
20
!-..
V
FORWARD CURRENT-(mA)
FIGURE 1.
REFERENCE VOLTAGE VS. CURRENT
>E
~
~
REFERENCE CURRENT -(}.LA)
10
~~
'-'
V
0
>
'I
w
1\
-60
0
>
'\
-70
-40
-60
T"j-lJJl
-~-~-~
0
~
~
~
-80
0.01
l00l~l~
JUNCTION TEMPERATURE-(OC)
0.1
10
REFERENCE CURRENT (rnA)
FIGURE 3.
TEMPERATURE DRIFT
FIGURE 4.
REFERENCE VOLTAGE CHANGE VS. CURRENT
II
10 -11
SG103/SG203/SG303
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
2-PIN TO-46 METAL CAN
Z-PACKAGE
Part No.
Ambient
Temperature Range
SG103-x.xZ/8838
SG103-x.xZ
SG203-x.XZ
SG303-x.xZ
-55°C to
-55°C to
-25°C to
O°Cto
125°C
125°C
85°C
70°C
Connection Diagram
(')~w'~t;)
@
(-)ANODE
=
x.x See first page of data sheet for
reference voltages available.
"lIote 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue' Garden Grove. CA92641 • (714) 898-8121 • TWX: 910-596-1804' FAX: (714) 893-2570
10-12
SG51 OA4/SG51 OAR4
SILICON
GENERAL
4 CHANNEL READ/WRITE AMPLIFIER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG51 0A4/SG51 OAR4 is a bipolar monolithic integrated circuit
intended for use with center-tapped ferrite heads commonly used
in Winchester disk drives. It is a 4 channel device which includes
circuitry to accurately read and write data to the heads in addition
to providing data protection. The SG510AR4 includes a 750Q
damping resistor between the x-y head connections.
• Read Mode
Controlled gain to 100VN
- Low input noise < 1.5nVv'FiZ
- High bandwidth> 30MHz
• Write Mode
- Write current range 10-40mA
- Programmable write current
- Error flag during fault mode
• Available In 24-pin sOle and 22-pin plastic DIP
packages
The SG51 OA4/SG51 OAR4 operates from +5V and +12V supplies
and is available in both 22-pin plastic DIP package and the 24-pin
wide body plastic sOle package.
BLOCK DIAGRAM (Pin numbers represent the 24-pin DIP package.)
wus
VCT
R/W
es
ROX
ROY
11
HOX
HOY
12
H1X
MULTIPLEXER
H1Y
H2X
Wlcr2~2------------r---~
H2Y
H3X
17
HSO
HS1
24
23
10
we
TABLE 1 - MODE SELECT
TABLE 2 - HEAD SELECT
CS
R/W
MODE
HS1
HSO
HEAD
0
0
1
0
1
x
Write
Read
Idle
0
0
1
1
0
1
0
1
0
1
2
3
April 1990
10 - 13
H3Y
SG51 OA4/SG51 OAR4
ABSOLUTE MAXIMUM RATINGS (Note 1)
DC Supply Voltage (V001) ...................................... -0.3V to 14V
DC Supply Voltage (V 002) .................................... -0.3V to 14V
DC Supply Voltage (Vcc) ........................................ -0.3Vto SV
Digital Input Voltage Range (VIN) ............ -0.3V to (Vcc + 0.3V)
Head Port Voltage Range (VH) ................ -0.3V \0 (VDDI + 0.3V)
WUS Pin Voltage Range (Vwus) ............................ -0.3V to 14V
Write Current (Zero Peak) (lw) .. ........ .......... .......... .......... SOmA
RDX, RDY Output Current (10) .. ...... ........ .............. .......... -10mA
Vr:;r Output Current (lVCT) ........................ :....................... -60mA
WUS Output Current (lwus) .............................................. 12mA
Operating Junction Temperature
Plastic (N, DW Packages) .......................................... 150°C
Storage Temperature Range ............................ -S5°C to 150°C
Lead Temperature (Soldering, 10 Seconds) .................. 300°C
Note 1. Values beyond which damage may occur. All voltage referenced to GND. Currents into device are positive.
THERMAL DERATING CURVES
~,
2.5
5.0
20~
.ot\.
'\
.........
1.5
~
,
~
~
C
1.0
"'' '.0?t-
0.5
0
25
50
~
~
5
75
2.0
~
1.0
125
150
0
175
AMBIENT TEMPERATURE - "c
~4'\,.
"'" o.. '.0?t-
~
~.,.\o ~J'~
?t-
~
"""~
100
'"
30
~
~
~,r:
'.0;"',£
~
0
~'f\.
..
o
~,
2
0
~q,0
~
"
0
25
50
75
100
CASE TEMPERATURE -
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
"
125
"c
150
175
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
DC Supply Voltage (VDO') .... ...... ............ ..... ....... 10.8V to 13.2V
RCT Resistor (RcT) (Note 3) ................................ 124Qto 13SQ
Write Current (lw) ................................................ 1OmA to 40mA
DC Supply Voltage (VCC) ...................................... 4.5V to 5.5V
Head Inductance (~) ............................................ 5~H to 15~H
Operating Ambient Temperature Range
Damping Resistor (R D) (SG510A4 only) ................ 500Q to 2KQ
SG510A4/SG510AR4 ...................................... 25°C to 70°C
Note 2. Range over which the device is functional.
Note 3. For Iw = 40mA. At other Iw levels refer to Applications Information that follows this specification.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambienttemperatures for SG51 OA4/SG51 OAR4 with 25'C" TA " 70°C and
over recommended operating conditions. Low duty cycle testing techniques are used which maintains junction and case temperatures equal to the
ambient temperature.)
SG510A4
Parameter
Test Conditions
SG510AR4
Units
I Min. I Typ. I Max. I
Power Supply
Read/Idle Mode
35
Supply Current /Ycel
mA
Write Mode
mA
30
Idle Mode
20
mA
Supply Current /Yool" (VOOl + VOD2)
Read Mode
35
mA
Power Dissipation
Write Mode
20+lw mA
Idle Mode, T J = 125°C
400
mW
600
mW
Read Mode, TJ " 125'C
mW
Write Mode, Iw = 40mA, RCT = OQ, TJ = 125°C
800
mW
40mA, R~T" 130Q, T
12S"C
600
Write Mode,
C..
10-14
=
SG51 OA4/SG51 OAR4
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Digital Inputs (HSn, es, R/Wi
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Digital Output (WUS)
Output Low Voltage
Output Leakage
Write Mode
Center Tap Voltage (Vr;r)
Head Current (per side)
Write Current Range
Write Current Constant "K"
Iwc to Head Leakage Current
Unselected Head Leakage Current
RDX, RDY Output Offset Voltage
RDX, RDY Common Mode Output Voltage
RDX, RDY Leakage
Read Mode
Center Tap Voltage
Head Current (per side)
Input Bias Current (per side)
Input Offset Voltage
Common Mode Output Voltage
Test Conditions
SG510A4
SG510AR4
Units
I Min. Typ. Max. I
0.8
V'"
V
100
V
V
mA
IlA
0.5
100
V
IlA
200
40
2.625
!lA
2.0
-0.4
=0.8V
=2.0V
=
=
10l 8mA
V OH 5V
Write Mode
Write Mode, OV:s Vcc:s 3.7V, OV:s VDO':S 8.7V
V
6.0
-200
10
2.375
0.99
Write/Idle Mode
Write/Idle Mode
RDX RDY = 6V, Write/Idle Mode
=
mNmA
85
20
-20
5.3
-100
Read Mode
Read or Idle Mode,
OV:s Vee:s 5.5V, OV:s V oe , :s 13.2V
-200
Read Mode
Read Mode
-440
4.5
mA
100
4.0
!lA
mV
V
!lA
V
200
45
440
6.5
!lA
!lA
mV
V
DYNAMIC SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG51 OA4/SG51 OAR4 with 25·C" TA " lO·C,
Iw =35mA, ~ = 10I'H, Ro =l50Q, f(WOI) =5MHz, CL (ROX, ROy) ,,20pF, and over recommended operating conditions.
Parameter
Write Mode
Differential Head Voltage Swing
Unselected Head Transient Current (Note 4)
Differential Output Capacitance (Note 4)
Differential Output Resistance
WDI Transition Frequency
Read Mode
Differential Voltage Gain
Dynamic Range
Bandwidth (-3dB) (Note 4)
Input Noise Voltage (Note 4)
Differential Input Capacitance (Note 4)
Differential Input Resistance
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Channel Separation
Single Ended Output Resistance (Note 4)
Output Current
Test Conditions
SG510A4
SG510AR4
Units
I Min. Typ. Max. I
7.0
2
15
SG510A4
SG510AR4
WUS= low
V'N =: 1mVpp @ 300KHz, Rl (RDX)= Rl (ROY): 1KQ
DC Input Voltage, V" Where Gain Falls by 10%,
V'N =: V, + 0.5mVpp @ 300KHz
IZsl < 50, V'N = 1mVpp
BW = 15MHz, L,. = 0, RH = 0
f= 5MHz
SG510A4, f 5MHz
SG510AR4, f =: 5MHz
V CM =: Vr;r + 100mVpp@5MHz
100mVpp @ 5MHz on V DO' ' V DDa or V cc
Unselected Channel: V'N 100mVpp @5MHz,
Selected Channel: V'N OmVpp
f=5MHz
AC Coupled Load, RDX to RDY
=
=
=
10 -15
V(pk)
mA(pk)
pF
0
Q
KHz
10K
600
250
960
85
115
VN
-3
30
3
mV
MHz
nV/VHZ
pF
Q
0
dB
dB
1.5
20
2K
460
50
45
860
45
30
2.1
dB
0
mA
II
SG510A4/SG510AR4
DYNAMIC SPECIFICATIONS (continued)
Parameter
Switchl1!9 Characteristics
R/WtoWrite
R/VVto Read
CSto Select
CS to Unseleci
HSO - HS2 to any head
WUS, Safe to Unsafe - TD1
WUS, Unsafe to Safe - TD2
Head Current
Prop. Delay· TD3
Asymmetry
Rise / Fall Time
SG510A4
SG510AR4
Min. Tm, Max.
Test Conditions
De!ay to 90% of write current
Delay to 90% of 100mV, 1OMHz read signal envelope
or to 90% of write current
Delay to 90% of write current or to 90% of 100mV,
10MHz read signal envelope
Delay to 90% decay of write current
Delay to 90% of 100mV, 1OMHz read signal envelope
Iw=35mA
Iw=35mA
LH = O).lH, RH = OQ
From 50% points
WDI has 50% duty cycle and 1ns rise/fall time
10% - 90% points
1.6
Units
1.0
ItS
1.0
ItS
1.0
1.0
1.0
8.0
1.0
ItS
25
2
20
ns
ns
ns
).Is
ItS
).Is
ItS
Note 4. These parameters, although guaranteed over the recommended operating conditions, are not tested in production.
WRiTE MODE TiiviiNG DiAGRAM· FiGURE i
WDI
TD1---I
wus
HEAD
CURRENT
(Ix-Iy)
CIRCUIT OPERATION
The SG510A4/SG510AR4 has the ability to address up to 4
center-tapped ferrite heads and provide write drive or read amplification. Head selection and mode control are accomplished
using the HSn, CS and R/W inputs as shown in tables 1 & 2 on first
page. Internal pull-ups are provided for the CS & RNV inputs to
force the device into a non-writing condition if either control line is
opened accidentally,
WRITE MODE
Taking both CS and R/W low selects write mode which configures
the SG51 OA4/SG51 OAR4 as a current switch and activates the
Write Unsafe (WUS) detector circuitry, Write current is toggled
between the X and Y side ofthe selected head on each high to low
transition ofthe Write Data Input (WDI). Note that preceding read
mode selection initializes the Write Data Flip-Flop, WDFF, to pass
write current through the "X" side ofthe head, The zero-peak write
current magnitude is programmed by an external resistor Rwe
from pin WC to GND and is given by:
'
Iw = KlR we ' where K =Write Current Constant
The Write Unsafe detection Circuitry monitors voltage transitions
at the selected head connections and flags any of the following
conditions as a high level on the Write Unsafe open collector
output:
• Head open
• WDI frequency too low
• Device 'not selected
• Head center tap open
• Device in read mode
• No write current
Two negative transitions on WDI, after the'fault is corrected, will
clear the WUS flag.
10 -16
SG51 OA4/SG51 OAR4
CIRCUIT OPERATION (continued)
To further assure data security a voltage fault detection circuit
prevents application of write current during power loss or power
sequencing.
To enhance write to read recovery time the change in RDX, RDY
common mode voltage is minimized by biasing these outputs to
a level within the read mode range when in write mode.
Power dissipation in write mode may be reduced by placing a
resistor (R CT) between V DO' and V 002' The optimum resistor value
is 150Q x 40 /l w (Iw in mA). At low write currents «15mA) read
mode dissipation is higher than write mode and RCT ' though recommended, may not be considered necessary. In this case V 002
is connected directly to VDO"
READ MODE
Taking C8 low and RNVhigh selects read mode which configures
the 8G51 OA4/8G51 OAR4 as a low noise differential amplifier for
the selected head. The RDX and RDY outputs are driven by
emitter followers and are in phase with the "X" and "Y" head paths.
These outputs should be AC coupled to the load. The intemal
write current source is gated off in read mode eliminating the need
for any external gating.
IDLE MODE
Taking C8 high selects the idle mode which switches the RDX,
RDY outputs into a high impedance state and deactivates the
internal write current source. This facilitates multi-device installations by allowing the read outputs to be wire OR'ed and the write
current programming resistor to be common to all devices.
APPLICATION INFORMATION
+12V
+5V
2K
VCC
MICROPROCESSOR
IbOl Ib02 VCT
WlJS
See Note 2
HOX
R/W
HOY
CS
H1X
SG510M
SG510AR4
ROX
H1Y
H2X
ROY
H2Y
READ
DATA
H3X
SG541 READ DATA PROCESSOR
H3Y
HSn
RWC
See Note 5
NOTES:
1. An external resistor, RCT' given by; RCT = 130 (40/l w) where Iw is the zero-peak write current in mA, can be used to limit internal power
dissipation. Otherwise connect V DD2 to V DD ,.
2. Damping resistors not required on 8G51 OAR4 versions.
3. Limit DC current from RDX and RDY to 1OOI-tA and load capacitance to 20pF. In multi-chip application these outputs can be wireOR'ed.
4. The power bypassing capacitor must be located close to the device with its ground returned directly to device ground, with as short
a path as possible.
5. To reduce ringing due to stray capacitance this resistor should be located close to the D.U.T. Where this is not desirable a series
resistor can be used to buffer a long WC line. In multi-chip applications a single resistor common to all chips may be used.
10-17
II
SG51 OA4/SG51 OAR4
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
22·PIN PLASTIC DIP
N· PACKAGE
Part No.
SG510A4
SG510AR4
Ambient
Temperature Range
25°C to 70°C
25°C to 70°C
Connection Diagram
es[
GND [
HOX [
HOY [
H1X [
H1Y [
H2X [
H2Y [
R/Vi [
SG510A4
SG510AR4
25°C to 70°C
25°C to 70°C
P
P
22
HSO
21
HS1
20p WOI
19p V OO1
6
17
7
•
16p H3X
15b H3Y
14~ wus
RDX [ 11
12 b RDY
esIT1
GND IT 2
HOX IT 3
HOY IT 4
H1XIT 5
H1Y IT
H2X IT 7
H2Y IT
R/ViIT 9
we IT
RDX IT 11
RDY IT 12
•
•
,.
Notes:
3
~
4
5
we [
24·PIN PLASTIC S.D.I.C.
OW· PACKAGE
1
2
,.
9
18p VOM
VCT
P
13P Vee
24Il HSO
23:0 HS1
22Il WDI
21~ V OO1
20
VOD2
19::::0 VCT
18:0 H3X
17:0 HaY
16:0 N.C.
15:0 N.C.
14:0
wus
13:0 Vee
1. All parts are viewed from the top.
Silicon General •
11861 Western Avenue' Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910·596·1804' FAX: (714) 893·2570
10-18
SG541
SILICON
GENERAL
ADVANCED DAm SHEET
READ DATA PROCESSOR
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG541 is a bipolar integrated circuit designed specifically for detection and
qualification of MFM and RLL encoded read signals used in disk drive applications.
This device consists of read and write channels and will handle data rates of up to
15 Megabits/sec. In read mode, the SG541 provides amplification and qualification
of head pre-amplifier outputs. Pulse qualification is accomplished using level qualification of differentiated input zero crossings. An AGe amplifier is used to compensate for variations in head preamp output levels, presenting a constant input level to
the pulse qualification circuitry. The AGC loop can be disabled so that a constant gain
can be used for embedded servo decoding or other processing needs. In write mode
the circuitry is disabled and the AGC gain stage input impedance switched to a lower
level to allow fast setting of the input coupling capacitors during a write to read
transition.
Pin to pin compatible with SSI32P541
Level qualification supports high
resolution MFM and RLL encoded
data retrieval
Wide bandwidth AGC input amplifier
Supports data rates up to 15 megabits/sec
Standard 12V ±10% and 5V ±10% supplies
Supports embedded servo pattern
decoding
Write to read transient suppression
Fast and slow AGC attack regions for
fast transient recovery
The SG541 requires +5V and +12V power supplies and is available in a 24 pin DIP
and 28 pin PLCC.
BLOCK DIAGRAM
OUT+ OUT-
DIN-
DIN+
CIN-
DIF-
CIN+
DlF+
IN+
C OUT
IN-
f----O
RD
III
A GND 0
HOLDB Q----J/
o
D GND
AGC
LEVEL
R/W8
HYS
0 OUT
TRUTH TABLE
R/WB
HOLDB
Mode
1
1
1
0
HOLD - Read amp on, AGe gain held constant Digital section active.
0
X
WRITE - AGe gain switched to maximum. Digital section inactive.
common mode input resistance reduced.
READ - Read amp on. AGe active. Digital section active.
April 1990
10 -19
as
SG541
ABSOLUTE MAXIMUM RATINGS (Note 1)
5V Supply Voltage, Vcc ........................................................ 6V
12VSupplyVoltage, Voo ..................................................... 14V
R/W, IN+, IN-, HOLD ................................. -0.3V to IYcc+ 0.3V)
RD ........... ....................... ........ -0.3V to IYcc + 0.3V) or + 12mA
All others ..................................................... -0.3 to 1Y00+ 0.3\1)
Operating Junction Temperature
Plastic (N, Q Packages) ................................................ 150°C
Storage Temperature Range ............................. -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) .. :................. 300°C
Note 1. Values beyond which damage may occur.
THERMAL DERATING CURVES
'0.0 r--r---,---.---r--,.--r---,
6.01--_----1--+--+--+---+--\
~
I 60~~1_----1--+--+--+---+--\
~
§ f-----'''',.---1~ -t---t--+--+---I
4.0
i
2.0
f--I---1----'; s;;..,:;..;:--+--+---t
°0L-~2~5-~50~~:--~~~~~-~175
175
AMBIENT TEMPERATURE - 'C
CASE 'tEMPERATURE - "c
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
5V Supply Voltage ................................................. 4.5V to 5.5V
. 12V Supply Voltage ............................................ 1O.BV to 13.2V
Operating Ambient Temperature Range
SG541 ................................................................. O°C to 70°C
Note 2: Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG 540 with o'e " T. " lOoe and 4.5V " Vee"
5.5V, 10.8V" V oo " 13.2V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient
temperature.)
Parameter
Power Supply
Supply Current {loJ
Supply Current (100)
Power Dissipation
Logic Signals
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Mode Control
Read to Write Transition Time
Write to Read Transition Time
Read to Hold Transition Time
Write Mode
Common Mode Input Impedance
(both sides)
Test Conditions
I Min.
SG541
U 't
Typ. Max. I m s
Outputs unloaded
Outputs unloaded
Outputs unloaded, TJ = 70·C
-0.3
2.0
0.0
V IL =0.4V
Viii = 2.4V
IQL=4.0mA
In~ = -400!-IA
14
mA
70
730
mA
mW
0.8
V
V
mA
!-IA
V
V
-0.4
100
0.4
2.4
1.0
AGC settling not included, transition to high input resistance
R/WB pin", low
1.2
3.0
1.0
250
10 - 20
f.ls
,",s
,",S
Q
SG541
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Read Mode (Note 3)
Differential Input Resistance
Differential Input Capacitance
Common Mode Input Impedance
(both sides)
Gain Range
Input Noise Voltage
Bandwidth
Maximum Output Voltage Swing
OUT+ to OUT- Pin Current
Output Resistance
Output Capacitance
[(DIN+) - (DIN-)] Input Voltage
Swing vs. AGC Input Level
[(DIN+) - (DIN-)] Input Voltage
Swing Variation
Gain Decay Time (To)
Gain Attack Time (TA)
Fast AGC Capacitor Charge
Current
Slow AGC Capacitor Charge
Current
Fast to Slow Attack Switchover
Point
AGC Capacitor Discharge Current
CMRR (Input Referred)
PSRR (Input Referred)
Hysteresis Comparator
Input Signal Range
Differential Input Resistance
Differential Input Capacitance
Common Mode Input Impedance
Comparator Offset Voltage
Peak Hysteresis Voltage vs.
HYS Pin Voltage (input referred)
HYS Pin Input Current
Level Pin Output Voltage
vs. V[(DIN+) - (DIN-)]
LEVEL Pin Max Output Current
LEVEL Pin Output Resistance
DOUT Pin Output Low Voltage
DOUT Pin Output High Voltage
Test Conditions
V[(IN+) - (IN-)] = 100mVpp @2.5MHz
V[(lN+) - (IN-)] = 100mVpp@ 2.5MHz
R/WB pin high
R/WB pin low
1.0Vpp '" V[(OUT+) - (OUT-)] '" 2.5Vpp
Gain set to maximum
Gain set to maximum -3dB point
Set by AC pin voltage
No DC path to GND
30mVpp '" V[(IN+) - (IN-)] '" 550mVpp,
0.5Vpp '" V[(DIN+) - (DIN-)] '" 1.5Vpp
30mVpp '" V[(IN+) - (IN-)] '" 550mVpp, AGC Fixed,
over supply and temperature
Y'N =300mVpp to 150mVpp at 2.5MHz,
Vour to 90% of final value. Fig. 1a
From Write to Read transition to V OUT at 110% of final value.
Y'N = 400mVpp @ 2.5MHz. Fig. 1b
V[(DIN+) - (DIN-)] = 1.6V, V(AGC) =3.0V
V[(DIN+) - (DIN-)]
= 1.6V, Vary V(AGC) until slow discharge
5G541
I Min. I Typ.
5K
V[(DIN+) - (DIN-)] = 100mVpp @ 2.5MHz
V[(DIN+) - (DIN-)] = 100mVpp @ 2.5MHz
(both sides)
HYS pin at GND, Resistance across DIN+ and DIN- '" 1.5KQ
1.8
0.25
4.0
30
3.0
±3.2
13
8
50
%
J.lS
4
1.3
2.0
J.ls
mA
0.14
0.22
mA
0.2
J.lA
dB
dB
1.5
11
6.0
10
Vpp
KQ
pF
KQ
mV
0.25
·20
VN
J.lA
1.25
4.5
-0.2
40
30
5
2.0
0.16
0.0
0.6 < IV[(DIN+)-(DIN-)]I < t.3Vpp, 10KQ from LEVEL pin to GND
1.5
3.0
v••-4.o
VoD-2.5
10 - 21
0.56 VppN
0.37
At DIN+, DIN· pins, tV < V(HYS) < 3V
1V < V(HYS) < 3V
I(LEVEL) =0.5mA
0.0 '" 10L '" O.SmA
0.0", 10H '" 0.5mA
Q
pF
KQ
KQ
VN
83
30 nV/YHz
MHz
Vpp
mA
Q
32
15
pF
10
{V[(DIN+) - (DIN-)]} ... {V[(DIN+) - (DIN-)] final}
V[(DIN+) - (DIN-)] =O.OV
Read Mode
Hold Mode
V(IN+) =V(IN-) =100mVpp @SMHz, gain at max.
Vee or Voo = 100mVpp @ 5MHz, gain at max.
U 't
Max. I m s
J.IA
VNpp
mA
Q
180
V
v..'2.e
Voo·1.8
V
2.5
SG541
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Active Differentiator
Input Signal Range
Differential Input Resistance
Differential Input Capacitance
Common Mode Input Impedance
Voltage Gain from CIN± to DIF±
DIF+ to DIF- Pin Current
Test Conditions
V[(CIN+) - (CiN-)] = 100mVpp @2.5MHz
V[(CIN+) - (CiN-)] '" 100mVpp @ 2.5MHz
(both sides)
R(DIF+ to DIF-) = 2KQ
Differentiator Impedance must be set as not to clip signals
at this current level.
DIF+, DIF- = AC Coupled
0.0 s 10H s 0.5mA
Comparator Offset Voltage
COUT Pin Output Low Voltage
COUT Pin Output Pulse Voltage
V(high) - V(low)
0.0 s 10 " s 0.5mA
COUT Pin Output Pulse Width
0.0 s 10H s 0.5mA
OU!put Data Characteristics (Note 4)
O-Fllp-Flop Set Up Time (Td1)
Min. delay from V(DIN+, DIN-) exceeding threshold
to V[(DIF+) - (DIF-)] reaching a peak
Propagation Delay (Td3)
Output Data Pulse Width Variation Td5 = 670 Cos' 50pF s Cos s 200pF
Logic Skew Td3 - Td4
Output Rise Time
VOH = 2.4V
Output Fall Time
VnL = OAV
I Min.
SG541
Units
Typ. Max. I
5.8
1.5
11.0
6.0
Vpp
KQ
pF
KQ
VN
2.0
1.7
2.2
Voo·3.0
mA
mV
V
0.4
30
V
ns
±1.3
10.0
0
110
±15
3
14
18
ns
ns
%
ns
ns
. ns
Note 3. AGC Amplifier· Unless otherwise specified, IN+ and IN- are AC coupled, OUT+ and OUT- are loaded differentially with> 600g and each side
is loaded with < 10pF to GND, a 2000pF capacitor is connected beween BYP and GND, OUT+ is AC coupled to DIN+, OUT- is AC coupled to
DIN-, AGC pin voltage is 2.2 VDC.
Note 4. (Ref. Fig. 2) - Unless otherwise specified V[(CIN+) - (CIN-)] = V[(DIN+) - (DIN-)] = 1.0Vpp AC coupled sine wave at 2.5MHz differentiating network
between DIF+ and DIF- is 100g in series with 65pF, V(HYS) = 1.8DC, a 60pF capacitor is connected between as and Vee' RD- is loaded with
a 4Kg resistor to Vee and a 1OpF capacitor to GND.
PIN DESCRIPTION
Pin Name
Description
Pin Name
Description
5 volt power supply
HYS
Hysteresis level setting input to the hysteresis comparator
LEVEL
Provides rectified signal level for input to
the hysteresis comparator
DOUT
Buffered test point for monitoring the flipflop D input
CIN+, CIN-
Analog input to the differentiator
12 volt power supply
AGND, DGND
Analog and Digital ground pins
R/WB
TTL compatible read/write control pin
IN+,IN-
Analog signal input pins
OUT+, OUT-
AGC Amplifier output pins
DIF+, DIF-
Pins for external differentiating network
BYP
The AGC timing capacitor is tied between
this pin and AGND
COUT
Buffered test point for monitoring the clock
input to the flip-flop
TTL compatible pin that holds the AGC gain
when pulled low
as
Connection for read output pulse width
setting capacitor
Reference input voltage level for the AGC
circuit
RD
TTL compatible read output
HOLDB
AGC
DIN+, DIN-
Analog input to the hysteresis comparator
10-22
SG541
TIMING DIAGRAMS
V[(IN+ )-(IN-)]
+HYSTERESIS LEVEL
V[(CIN+ )-(CIN-)]
ond
V[(OIN+ )-(OIN-)]
-HYSTERESIS LEVEL
V[(OUH )-(OUT-)]
(0)
V[(OIF+)-(DlF-)]
V[(IN+ )-(IN-)]
VCOUT
FLIP-FLOP CLOCK
R/W
VOOUT
FLIP-FLOP 0 INPUT
RD OUTPUT
READ DATA
V[(OUH)-(OUT-)]
FIGURE 1 - AGC TIMING DIAGRAMS
FIGURE 2 - TIMING DIAGRAM
TYPICAL APPLICATION
r-_ _ _ _ _ _.~~I~VO
rE?~'~
I
I
I
I
I
I
i
I
i
i OOO1 1'F
I
I
I
I
I
I
I
I
I
I
!R~~~
l
I
I
I
L_
.
~~~~
I
_J
''''''''
II
'--1--------------------+-----------------<3 FEEDB ACK
2.4K
~----~----------~----------~------~~·10
GROUND
(Pin numbers correspond to T-package)
BLOCK DIAGRAM
v----t--
OUTPUT
CF = __
1__ where fc is Low Frequency corner and
2nfc R R is the Gain setting.
AGC DRIVE
Cs
AGC
28 dB
-
=0 to 1OpF to minimize high frequency peaking.
+
: :dB
] ' 0 CF
'------0 10 dB
3 dB 0
(Pin numbers correspond to T-package)
April 1990
See Application Notes for additional information.
10 - 25
SG1401/SG2401/SG3401
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage .................................................................... 20V
AGC Diode Current ............................................................ 5mA
Lead Temperature (Soldering, 10 Seconds) .................... 300'C
Note 1. Exceeding these ratings could cause damage to the device.
Operating Junction Temperature
Hermetic (J, T-Packages) .............................................. 150'C
Plastic (N-Packages) .................................................... 150'C
Storage Temperature Range ............................. -65'C to 150'C
THERMAL DERATING CURVES
::
::
~
~
0
0
F
F
<
<
~
~
"
15
i
175
175
AMBIENT TEMPERATURE -
·c
CASE TEMPERATURE -
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
·c
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage ........................................................... 8V to 18V
Operation Ambient Temperature Range
SG1401 ........................................................ -55'C to 125'C
SG2401/SG3401 ................................................. O'C to 70'C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperatures of TA = 25'C, Vs = +12V, and f = 1MHz. Low duty cycle
pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Supply Voltage
Power Consumption
DC Output Voltage
Peak-to-Peak Output
Voltage Gain
Unity Gain Frequency
Input Resistance
Output Resistance
Input Capacitance
Maximum Power Gain
Temperature Stability (Note 4)
AGC Range
Noise Figure
Test Conditions
No AGC Voltage
Pin 3(4) to AC Ground (Note 3)
Pin 3(4) open (Note 3)
Pin 3(4) coupled to pin 8(11) (Note 3)
Pin 3(4) coupled to pin 9(12) (Note 3)
Pin 3(4) to AC Ground (Note 3)
Pin 3(4) to AC Ground (Note 3)
20dB Gain
20dB Gain
20dB Gain
20dB Gain, RL '" 50Q
20dB Gain, TA =T MIN to T MAX
20dB Gain, Rs = 1 K
Note 3. Numbers in parenthesis refer to dual-in-line package.
Note 4. These parameters, although guaranteed, are not tested in production.
10 - 26
SG1401/SG2401
SG3401
Min. Typ. Max. Min. Typ. Max.
6
20
6
12
20
12
120
90
110
90
8.7
8.7
4
3
2.2
2.2
2.7
3.2
3.2
2.7
10
11
9
11
9
10
18
18
20
21
20
21
26
24
31
28
26
31
200
200
2.5
2.5
25
50
5
5
30
30
±0.5
±1
±1
±2
20
22
22
6
8
6
Units
V
mW
V
V
dB
dB
dB
dB
MHz
KQ
Q
pF
dB
dB
dB
dB
SG1401/SG2401/SG3401
CHARACTERISTIC CURVES
(Pin Numbers correspond to T - Package)
10
,,-
250
15
i
150
~
\
o
.3
I
300
I
~
PIN 3 COUPLED TO P ' " : \
10
30
lOa
PIN J COUPLED TO PIN 9
100
300
LJ
.3
1.0
FIGURE 5.
INPUT IMPEDANCE VS. FREOUENCY
3.0
10
.30
100
300
FREQUENCV-(MHz)
FREQUENCY-(MHz)
FIGURE 6.
OUTPUT IMPEDANCE VS. FREOUENCY
30
30
P'i3 Tf AC ,ROUND
25
'"
20
~
15
~
I
~
\
10
>
w
"
t\-. .... -
~>
10
25
J.3 T1
1
PINI9
100
lK
10K
EXTERNAL PARALLEL RESISTOR-(O)
'"
20
""
15
~
I
1
w
J3r!p)a
"~
0
-50 -25
0
/
25
50
75 100 125
FIGURES.
TEMPERATURE STABILITY
10 - 27
II
1.0
PIN 2 DRIVEN FROM
A VOL1AGE SiURCE
/
-V
AMBIENT TEMPERATURE-(Oc)
/
/
10
>
I I
PIN 3 OPEN
I I
FIGURE 7.
EXTERNAL GAIN CONTROL
10
FREQUENCY-(MHz)
~
--......,
\
10
3
25
l
I
o
15
FIGURE 2.
MAXIMUM OUTPUT VS. SUPPLY VOLTAGE
FIGURE4.
STABILIZED FREOUENCY RESPONSE
I-
PIN B
1
10
FREQUENCY-(MHz)
30
VI
/
J
PIN J
10
SUPPLY VOL TAGE-(V)
".,
PIN .3 0 EN
\
I
~
~
o
\1\
PIN 3 TO PIN 8
.3
15
w
\
PIN .3 TO PIN 9
10
""
"
Cs=o
c,~I"PF
TI AC CROUN~ "
25
'"
20
PIN J OPEN
SUPPLY VOL TAGE-(V)
FIGURE 1.
POWER CONSUMPTION VS. SUPPLY VOLTAGE
GROUN~,,"
PINJjPIN9
'"
I
~
10
PIN .3
V
/
/
x
"
o
/
2
./
50
o
is
V
/
8
AC
25
iO
200
TI
PIN J
~
E
'I
30
5'
11
12
1.3
1.4
AGe VOL TAGE-(V)
FIGURE 9.
GAIN VS. AGe DIODE VOLTAGE
15
SG1401 /SG2401 /SG3401
CHARACTERISTIC CURVES (continued)
30r---,----r--~--_,--~
100
25~--+---~---+--~--~
;r'"
~
il
20
/
15
~
'(
V
/ ; I N 2 DRIVEN FROM
,
5
~
10
e'
'"w
A CURRENT SOURCE
~
0
1
10
100
1K
10K
5
IIII
II~
I
-
"'-
-
""-
::
-
::
-
PIN .3 COUPLED TO PIN 9
3
I
2
I IIIII
III
.5
AGC CURRENT-GIlA)
I
="
1
0
II
30
u
§
10
50
20
>-
V
t.:
~>
I
::j
1
2
3
10
5
I IIII
20 30 50
100
C S BETWEEN PINS C AND E -(PF)
FIGURE 10.
GAIN VS. AGC DIODE CURRENT
FIGURE 11.
UPPER CUTOFF FREQUENCY VS. C, VALUE
APPLICATION INFORMATION
The SG1401 series has been designed tQ provide maximum versatility as a general-purpose, single-ended amplifier. With its
broad frequency capability, this circuit will be useful in a wide
range of applications provided that the usual considerations for
high frequency circuit designs are observed. The following information is presented toward aiding in the optimization of the many
possible configurations of this device.
FIXED GAIN
In the circuit configurations shown in Figure 12, the overall voltage
gain is approximated by resistors R1 and the parallel combination
of R2 and R3, as
Ay ~ 1 + ~ where R = R2 R3
R
R2 + R3
IN
o-+--£~
Utilizing the internal 90 or 460 ohm resistors for higher gain
settings provides the added advantage of maximum temperature
stability since the close tracking of adjacent diffused resistors
keeps their ratio constant. Typical temperature variation of this
circuit is shown in Figure 8.
VARIABLE GAIN
Since the dynamic impedance of a forward-biased diode is
inversely proportional to the current through it, a convenient gain
control can be achieved by using a pair of diodes as a variable
impedance. In the circuit of Figure 13, R3 has been replaced by
two diodes whose impedances act in parallel due to the decoupiing of CD' If the diodes are driven from a voltage source, a
logarithim relationship between gain and control signal is
achieved (see Figure 9); while if a current source is used, the
relationship is linear as shown in Figure 10.
OUT
IN
V
R,
"-
J
""l
OUT
+"Cf
FIGURE 12
R2
With no external connections, the voltage gain is determined
solely by R, and R2 and is 1Yo or 3 dB. Decreasing the effective
value of R2 by capacitively coupling a lower resistor in parallel,
raises the gain. Four fixed gain settings are provided internal to
the circuit; however, any other setting within the maximum gain of
the amplifier is possible with external resistors as shown in Figure
7.
The value of the coupling capacitor, C F is determined by the low
frequency response desired, as its capacitive reactance will add
to the value of the resistance it couples. Therefore, the lower
cutoff frequency will be
"
AGe
+=
Cc
FIGURE 13
There are two limitations on this form of gain control. First, the
diodes' capacitance limits their effectiveness to frequencies below 20MHz and, secondly, the signal voltage across the diodes
should be held to less than 50 millivolts RMS to minimize selfmodulation of al1)plifier gain. Additionally, the AGC current should
be limited to 3mA maximum to keep the diodes out of saturation.
10-28
8G1401 /8G2401 /8G3401
APPLICATION INFORMATION (continued)
HIGH FREQUENCY STABILITY
With the capability of operation at 100MHz, the SG1401 series
also has some susceptibility to external stray reactances; however, with reasonable care, complete stability may be assured.
Some general precautions which should be considered include
the following:
Since the gain of this circuit is reduced by increasing the amount
of feedback, the potential for instability is greatest when the gain
Is at its minimum value. This characteristic and the stabilizing
effects of a 4.7 picofared capacitor between pins 4 and 3 are
illustrated in the frequency response curves presented in Figures
3 & 4. The relationship between the value of e s and the upper
cutoff frequency of a 20dB gain setting is shown in Figure 11.
1. Power supply decoupling close to the circuit terminals (a
0.1 !IF capacitor is usually adequate).
2. Maintain separation of input and output lines.
3. Minimize load capacitance or insert a series resistor (up to
50Q) in the output.
4. Purposely limit the high frequency response with a stabilizing capacitor e s between pins 3 and 4.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
14-PIN CERAMIC DIP
J- PACKAGE
SG1401J/883B
SG1401J
SG2401J
SG3401J
14-PIN CERAMIC DIP
N- PACKAGE
SG2401N
SG3401N
10-PIN METAL CAN
T-PACKAGE
SG1401T/883B
SG1401T
SG2401T
SG3401T
Ambient
Temperature Range
-55°C to 125°C
-55°C to 125°C
OOeto 70°C
OOeto 70°C
ooe to 70°C
ooe to 70°C
-55°C
-55°C
ooe
ooe
to
to
to
to
125°C
125°C
70°C
70°C
Connection Diagram
AGC
N.C.
DIODE DRIVE
FEEDBACK
STABILIZATION
N.C.
OUTPUT
[..--=-;:o:J
[ 2
13:J
[ 3
12:J
[ 4
11::J
[ 5
1O:J
[ •
9:J
GROUND
N.C.
20dB
10dB
INPUT
N.C.
[~:J
+v,
GROUND
AGC
DIODE DRIVE
FEEDBACK
(j) @I
®
®
®
STABILIZATION
20dB
®
0
10dS
INPUT
Gl ® ® +v,
OUTPUT
•
Note 1. Contact factory for JAN and DESC product availablily.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue· Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804· FAX: (714) 893-2570
10-29
10-30
SG1402/SG2402/SG3402
SILICON
GENERAL
VARIABLE GAIN, WIDEBAND
AMPLIFIER / MULTIPLIER
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG1402 is a monolithic four quadrant multiplier offering excellent
frequency response and provision for use as a variable gain amplifier
with both non-inverting and inverting outputs available. In addition to
linear amplification, the device is also ideal for balanced modulation,
pulse or gated amplification, and coincidence detection.
•
•
•
•
•
•
TheSG1402 will operate over the full military ambient temperature range
of -55·C to 125·C while the SG2402 and SG3402 are designed for
O·C to 70·C applications.
Single power supply voltage
Self-contained biasing
25dB voltage gain
Differential or single ended inputs and outputs
Large bandwidth
Low power dissipation
HIGH RELIABILITY FEATURES
-SG1402
9 Available to MIL-STD-883
• SG level "S" processing available
SCHEMATIC DIAGRAM
BIAS
BALANCE ADJ.
CONTROL
CONTROL
II
(Pin numbers correspond to T-package)
+10V
TEST CIRCUIT
OlJ
EXT
SAL
(Pin numbers correspond to T-package)
See Application Notes for additional information.
April 1990
10-31
SG1402/SG2402/SG3402
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage .......... :.......................................................... 18V
Load Current .................................. ;.................................. 15mA
Lead Temperature (Soldering, 10 Seconds) ......... :.......... 300'C
Note 1. Exceeding these ratings could cause damage to the device.
Operating Junction Temperature
Hermetic (J, T-Packages) ............................................•. 150'C
Plastic (N-Packages) .................................................... 150'C
Storage Temperature Range ............................. -65'C to 150'C
THERMAL DERATING CURVES
~
I
1;
~
~
1S
i
20
5.0
2.0
'.0
"t'--~
'>
~
~
I
,0,.1\'''0
......
05
~
Ei
25
50
v t?",
75
100
AMBIENT TEMPERATURE -
125
150
-q
"
%
'>",
20
I--
'?-"~
.o,"'Az.,s~C'
~
k~0
4~
10
'~~
a
"0..
3.0
~
10r-r(,O~~~o/
a
"~
" ~~
~
1;
~.po~
"Do)
1,\\
a
175
a
25
50
"c
75
"~
100
125
150
175
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
MAXIMUM POWER DISSIPATION YS AMBIENT TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Supply Voltage ........................................................ 16V (Note 3)
Note 2. Range over which the device is functional.
Note 3. See Figure 6.
Operation Ambient Temperature Range
SG1402 ........................................................ -55"t to 125'C
SG2402/SG3402 ................................................. O'C to 70'C
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of TA =2S'C, V+ =+1OV. and f =100MHz. Low duty cycle
pulse testing techniques are used which mintains junction and case temperatures equal to the ambient temperature.)
Parameter
Maximum Voltage Gain
Variable Gain Range
Frequency Response
Input Impedance
Output Impedance
Output Voltage Swing
QUiescent DC Levels
Output Offset Voltage
DC Output Shift
Differential Control Voltage
Maximum Gain Variation
with temperature
Equivalent Input Noise
Power Consumption
Test Conditions
Single ended
With external balance
fat3dB
=
3
1.3
RL 100K
RL = lK
Inputs and Balance Adjust
Control Inputs
Outputs
Minimum Gain
Maximum Gain
With max. gain change
For max. gain change
6.5
1.8
1.8
100
4
1.6
3.6
1.8
7.0
100
3
1.3
7.5
100
200
100
=
1
25
65
10 - 32
4
1.6
3.6
1.8
7.0
300
500
200
2
1
85
25
65
Units
dB
dB
MHz
Kg
Kg
200
200
TMIN to T MAX
BW = 10MHz, Rs = 50g
V+= 10V
TA
SG1402/SG2402
SG3402
Min. TVD. Max. Min. TVD. Max.
20
23
25
25
40
55
60
50
40
50
50
1.2
1.2
3
g
Vp-p
Vp-p
V
V
V
mV
mV
mV
mV
dB
~Vrms
65
mW
SG1402/SG2402/SG3402
CHARACTERISTIC CURVES
,,-
$
250
z
E
'I
5
200
i
150
0
w
0
z
lScf'C PHASE SHIFT
w
~
5
FORI
in
a
0
5
10
15
20
""
I
w
"~
DIJERElrJ GJ~
SUPPLY VOLTAGE-(V)
-80
-40
§:
0
w
0
Z
oOc PHASE SHIFT
/
MULTIPLY BY 2
0
-120
25
, II
I
30
+80
""
i
w
"~
25
I
0
~
;;
w
0
z
20
w
I
g
in
DIFFERENTIAL CONTROL
VOLTAGE> 120mV
15
-50 - 25
I
I
I
a
25
50
<{
100 125
AMBIENT TEMPERATURE -
~
5
""
05
1
2
,,\
""
10
20
FREQUENCY -
\
50 100200
MHz
5
~
-10
-20
-30
I
-40
-50
./
/
v+=
~
4
~
3
~
I
I
~
;::"
I
2
g
~
1
/
:>
S
0
-70
10
10'
10 3 10 4
10 5
FREQUENCY -
DC
lOG
tOV
,!-
w
V
-60
1
FIGURE 4.
MAXIMUM GAIN VS. TEMPERATURE
5
~I
l)
"~
75
10
-
FIGURE 3.
FREQUENCY RESPONSE
~
0
\
\
w
+120
0
~
=
OIFF!RENLL COlTRO! = ,Iomv
a
+40
a
I
colma! tmv \
.\
15
DIFFERENnAL CONTROL VOL lAGE - mV
FIGURE 2.
SINGLE·ENDED GAIN CONTROL
z
OIFJRENJAL
20
in
0
FIGURE 1.
MULTIPLIER TRANSFER FUNCTION
""
> lkomv
25
z
\
10
~I~~~RENJIAL clo~~~~~
'Il
V....
\
w
/
0
a.
i"'-,
20
I
10 1 10 8
J
,/
a
.01
0.1
MHz
1
10
100
LOAD RESISTANCE IN K 0
FIGURE 5.
DYNAMIC GAIN RANGE
FIGURE 6.
MAXIMUM OUTPUT VOLTAGE
TYPICAL APPLICATIONS (Pin Numbers correspond to T - Package)
V,N
o---------jf-"-'-
~f-"-'_
~f-"-'-
N
7
+lOV
+lDV
VIN 0
1
3
6/0"..8
9
>
+VOUT
Your
CONTROL
VOLTAGE
- -V
o to 5V
IN914
~~~ >
-=-
10 8
9
-VOUT
6/'"
r-y
10K
lOOK
8AL
AOJ
10K GAIN
CONTROL
==0.1
+VaUT
=PO.l
10K
7
7
FIGURE 7
FIGURES
Single-ended or differential output variable gain amplifier
with manual gain control for output of either phase.
Gated amplifier for gain control without phase change. Balance control may be eliminated if maximum attenuation is not
needed.
10 - 33
II
SG1402/SG2402/SG3402
TYPICAL APPLICATIONS (continued) (Pin Numbers correspond to T - Package)
+10V
Ven
(carrier)
i
I~
I
51
~ ~
01
i'<:---<> +VS
7
Vs <>------11-"0-,-'- - - - I
(modulated
Vm
(modulated
signal)
;,..-"----_ _<> signal)
(modulation)
Vc <>------11-"0-,-,+---1
(corner)
lOOK
SAL
ADJ
D'
FIGURES
FIGURE 10
Modulator circuit with potentiometer adjustable for either
amplitude or balanced modulation.
Balanced demodulator with output filter eliminating need for
external balance.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
14-PIN CERAMIC DIP
J - PACKAGE
Part No.
SG1402J/883B
SG1402J
SG2402J
SG3402J
14-PIN CERAMIC DIP
N - PACKAGE
SG2402N
SG3402N
10-PIN METAL CAN
T-PACKAGE
SG1402T/883B
SG1402T
SG2402T
SG3402T
Ambient
Temperature Range
-55'C to
-55'C to
O'C to
O'Cto
125'C
125'C
70'C
70'C
O'C to 70'C
O'C to 70'C
-55'C to 125'C
-55'C to 125'C
O'C to 70'C
O'C to 70'C
Connection Diagram
v+
N.C.
CONTROL
OUTPUT
BIAS
N.C.
[f1=14p GROUND
~ 2 '3 ~ N.C.
[3
12 P CONTROL
11 ~ OUTPUT
10
INPUT
N.C.
[4
[ 5
[ 6
INPUT [ 7
P
.p
'P
BALANCE ADJ.
GROUND
v+
CONTROL
OUTPUT
CD
@
®
®
®
BIAS
0 ® ®
CONTROL
®
OUTPUT
o
INPUT
BALANCE ADJ.
INPUT
Note '1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue· Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804· FAX: (714) 893-2570
10-34
SG1503/SG2503/SG3503
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
PRECISION 2.5- VOLT REFERENCE
DESCRIPTION
FEATURES
This monolithic integrated circuit is a fully self-contained precision voltage
reference generator, internally trimmed for ±1 % accuracy. Requiring less
than 2mA in quiescent current, this device can deliver in excess of 10mA
with total load- and line-induced tolerances of less than 0.5%. In additon
to voltage accuracy, internal trimming achieves a temperature coefficient
of output voltage of typically 10 ppm/"C. As a result, these references are
excellent choices for application to critical instrumentation and D-to-A
converter systems.
•
•
•
•
•
•
HIGH RELIABILITY FEATURES - SG1503
The SG1503 is specified for operation over the full military ambient
temperature range of -55°e to 125°e , while the SG2503 is designed for25°e to 85°e and the SG3503 for commercial applications of ooe to 70°C.
• Available to MIL-STD·883 and DESC SMD
• Radiation data available
• SG level "S" processing available
Output voltage trimmed to ±1%
Input voltage range of 4.5 to 40V
Temperature coefficent of 10ppm/"C
Quiescent current typically 1.5mA
Output current in excess of 10mA
Interchangeable with MC1503 and AD580
FUNCTIONAL DIAGRAM
Va
•
GND
April1990
10 - 35
SG1503/SG2503/SG3503
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage ...................................................................... 40V
Storage Temperature Range ............................ -65'C to 150'C
Note 1. Exceeding these ratings CQuid cause damage to the device.
Operating Junction Temperature
Hermetic (J, Y - Package) ............................................ 150'C
Plastic (M-Package) ...................................................... 150'C
Lead Temperature (Soldering, 10 Seconds) .................. 300'C
THERMAL DERATING CURVES
2.5
'00,\
ao
2.0
~
~
~
,
I
'.5
is
~
'0
05
L
a
a
iB-P'N JRO'P)
Y
25
50
""1
~
~
~
15 4.0
(~~4
I
~
is
~J,~
~~~>
~
'\~~
6.0
i
J'~
2.0
125
'00
7'
AMBIENT TEMPERA lURE _ -c
150
"r\.
............
_
~(8_PI"'"
0 4•
~
I !ASiC 0;;:;- r===== ~
M (B-PIN p
a
175
a
25
50
75
'00
12,
150
175
CASE TEMPERATURE - 'C
MAXIMUM POWER DISSIPATION va AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Input Voltage .......................................................... 4.5V to 40V
Operating Ambient Temperature Range
SG1503 .......................................................... -55'C to 125'C
SG2503/SG3503 .................................................. O'C to 70'C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply overthe operating ambienllemperatures for SG1503 with -55'C "TA " 125'C, SG2503/SG3503
with O'C "TA " 70'C, V'N= 15V, and IL = OmA. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal
to the ambient temperature.)
Parameter
Output Voltage
Input Voltage
Line Regulation
Load Regulation
Temperature Regulation
Quiescent Current
Short Circuit Current
Ripple Rejection
Output Noise
Voltage Stability
Test Conditions
TA = 25'C
TA = 25°C
Y'N = 5Vto 15V
V,N " 15V to 40V
~II. = 10mA
~IL = 10mA, Y'N = 30V
(SG1503 only)
(SG2503/3503 only)
V'Ne 40V
TA " 25°C
f" 120Hz, TA = 25'C
BW = 10KHz, TA = 25'C
10 - 36
SG3503
SG1503/2503
Units
Min. Typ. Max. Min. Typ. Max.
2.485 2.500 2.515 2.475 2.500 2.525
V
4.7
40
4.7
V
40
4.5
40
V
4.5
40
1
1
mV
3
3
3
5
3
mV
10
mV
3
5
3
10
4
8
4
mV
15
15 ·20
mV
I)
2.,5
mV
5
10
1.5
2.0
1.5
mA
2.0
15
20
30
20
mA
15
30
76
76
dB
p,Vrms
100
100
250
250
IlV/Khr
SG1503/SG2503/SG3503
CHARACTERISTIC CURVES
>
r
0
>
2.50
/'
::0
iO
/
::J
0
-
10,=0
0
i=
~
~
/
VIN=15V
tJ. V IN=10V
z
10=0
e--
I
-20
I
VIN",15V
C)
14
20
/V
/V
/V
RECOMMENDED
Z
~/V
~
'"
~
~
"
r--
0
5
10
11
II
/V
/V
12
12
RX OR Ry-KO
FIGURE 4.
CURRENT LIMITING
18
~/V
"
.....
~
16
FIGURE 3.
MINIMUM INPUT·OUTPUT VOLTAGE
~
\.
0.2
ci
.........
RX OR Ry-KO
TA=250C
\
"
12
10
14
~~:~;OVLAX
13=113'""10mAdc_
f"'.,
0
10
FIGURE 2.
MINIMUM INPUT·OUTPUT VOLTAGE
FIGURE 1.
STANDBY CURRENT
06
r--..
02
INPUT VOL TAGES-(V)
X INPUT VOlTAGE-(V)
~
1\
~
OL-L-L-L-L~~~~-L-L-L~
4-
\
04
z
u
"
0
06
"
I
~
0
-10 -8 -6 -4- -2
13=113"'10mAdc_
i
I
1\
~
~~:~~';,~v ~Jx.
"
I
1\
IV11 OR
FIGURES.
RIPPLE REJECTION
10 - 41
Iv,l-v
16
20
SG1595/SG1495
APPLICATION INFORMATION
. RECOMMENDED ZERO ADJUSTMENT AND SCALE
SETTING PROCEDURE
v+
R
2KO
-=TO PIN 8
Y OFFSET ADJ.
10KO
TO PIN 12
X OFFSET ADJ.
1OKOf
2KO
FOR V+=15V R=10KO
V+=32V R=22KO
Next, set Vx = Vy = 5.000V and adjust the K-factor potentiometer
until the output reads the desired output.
-=-
10KO
With Vx = Vy = OV adjusllhe output offset adjustment until the output
of the external amplifier reads OV. SetVx = 5.000V, Vy = O.OOOV,
and adjust the Y -input offset control until the output amplifier reads
OV. Repeallhis procedureforVx= O.OOOV, Vy = 5.000Vand adjust
the X-input offset control until the output amplifier reads OV. This
procedure should be repeated until complete null is achieved.
-15V
VOUT = 2.500V = K Vx Vy for a K-factor of 0.100.
OFFSET ADJUSTMENTS
FIGURE 6
For best output accuracy, use above network and follow procedure
at right.
When a high degree of accuracy is unnecessary for small output
signals, the above procedure may be simplified by eliminating the
output offset adjustment.
25KO
+15Y~
v-
v+
Rye:
Yxo--
~7
RL
1
SG1595
Vyo-- 4
y-OFFSET 0 - ADJUST
+15Y
OUTPUT OFFSET
1.0MO
ADJUST
RB
R5
2
9
X-OFFSET 0 - - 12
ADJUST
(;)
1 ° 0 Rx
11
~-15Y
-v
R1
SG7~)...s
RL
R6
14
8
3
Y-o-- 7
R7
-=-
RA
EOUT
r-Y4
Rg
13 I-----
I
-=-
-1SV
R13
tJRS
~
-=-
K FACTOR ADJUST
FIGURE 7 • MULTIPLY WITH OP AMP LEVEL SHIFT
SET RESISTOR'
UP TOLERANCE
1
2
3
V+ = 32V, V-= -15V,
-10V"Vx ,,10V,
-10V" Vy " 10V
V+ = 15V, V- = -15V,
-5V "Vx s 5V,
-5V"Vy ,,5V
V+ = 15V, V- = -15V,
-10V" Vx " 10V,
-10V"V,,10V
R,
Rs
R,
R,
R,
R,
R13
RA
Rx
Ry
5%
1%
1%
1%
1%
1%
1%
5%
20% 0.5% 5%
5%
9.1
121
100
11
121
15
13.7
12
5.0
11
15
15
3.0
300
100
100 300
13.7
12
5.0
3.4
B.2
B.2
1.2
121
100
11
910 13.7 13.7
12
5.0
1.5
15
15
, All resistor values are in KQ
10 - 42
R.
R,
SG1595/SG1495
APPLICATION INFORMATION (continued)
product of two sine waves will exhibit a vector error of 1%. A
3° relative phase shift between the input signals will result in a
vector error of 5%.
SUGGESTIONS AND GENERAL PRECAUTIONS
The high frequency performance of the SG1595 is primarily
determined by two conditions. One, by the load resistors and the
associated stray output capacitance of the multiplier and two, the
operational amplifier used at the output. For maximum frequency
of operation, low value load resistors and a wideband high slew
rate operational amplifier should be used.
The normal circuit precautions should be taken to avoid parasitic
oscillation. Leads should be as short as possible and the power
supplies should be decoupled with a 0.11lF high frequency
capacitor. An Re parasitic suppression network of 51 Or.! in series
with a 1OpF from each input to ground can be used to reduce the
Q of a source-tuned circuit, which may cause the oscillation. As
an alternate solution, a 51 Or.! resistor network can be placed in
series with each input of the SG 1595.
Phase shift at higher frequencies due to load resistors and output
stray capacitances and relative phase shift between X and Y
channels should be considered for maximum accuracy. As an
example if the input to output phase shift is only 0.6°, the output
APPLICATION CIRCUITS
OUTPUT OFFSET ADJUST
'"
EIN=COSwT
8.2KO
1<5 VP-PI
Vy
OFFSET ADJUST
INPUT
S,
RX .. S.2KO
SG1595
SG1595
12
OFFSET
AOJUS
ft
10KO
"
-fir
,TI-t.2.:....___~----->----'l·
IOOKO
"
=J.3KO
Rt.,",3.3KO
6.8
KG
Vz
DIVlDE (S'NITCH 51 OPEN)
jOl1-'F--:-
vo=~
+'0
EO""TCOS2wT
J''"'
O. Max. Min. Typ. Max.
40
140
=
Carrier Suppression (Note4)
0.04
20
0.2
100
Units
40
140
"V(rms)
"V(rms)
0.04
20
0.2 mV(rms)
200 mV(rms)
=
50
65
50
65
dB
=
Transadmlttance Bandwidth
=
=
10 - 46
50
50
dB
-50
300
80
300
80
MHz
MHz
8G1596/8G1496
ELECTRICAL SPECIFICATIONS (continued)
Parameter
Voltage Gain, Signal Channel
Input Resistance, Signal Port
Input Capacitance, Signal Port
Single-Ended Output Resistance
Single-Ended Output Capacitance
Input Bias Current
Input Offset Current
Average Temperature Coefficient of
Input Offset Current
Output Offset Current
Average Temperature Coefficient of
Output Offset Current
Signal Port Common-Mode Input
Voltage Range
Signal Port Common-Mode Rejection Ratio
Common-Mode Quiescent Output
Voltage
Differential Output Swing Capability
Positive Supply Current
Negative Supply Current
Power Dissipation
SG1595
SG1495
Min. Typ. Max. Min. Typ. Max.
Test Conditions
VS = 100mV (rms), f = 1.0KHz,
V7 - Ve = 0.5V, TA =TMIN to TMAX
f = 5.0MHz, V7 -Ve =0.5V
f = 5.0MHz, V7 -Va =0.5V
f=10MHz
f=10MHz
(I, +14)/2, TA =T MIN to TMAX
(17 +le)/2, TA =TMIN to TMAX
(I, -1 4), TA "TMIN to TMAX
(17 - Ie)' TA =TMIN to TMAX
2.5
Units
25
25
5.0
5.0
3.5
200
2.0
40
5.0
12
12
0.7
0.7
30
30
7.0
7.0
flA
flA
50
2.0
14
80
nArC
flA
3.5
200
2.0
40
5.0
12
12
0.7
0.7
TA =TMIN to TMAX
(16 -I.),TA=TMIN to TMAX
2.0
14
TA =TMIN to TMAX
90
90
oNcC
f5 = 1.0KHz
5.0
5.0
Vp-p
V7 - V. = 0.5V
-85
·85
dB
8.0
8.0
2.0
3.0
33
8.0
8.0
2.0
3.0
33
V
Vp-p
mA
mA
mW
(16+IJ, TA=TMINtoTMAX
(1 10), TA =TMIN to TMAX
2.5
3.0
4.0
VN
KQ
pF
Kg
4.0
5.0
pF
flA
f1A
Note 4. These parameters are guaranteed by design and process control but are not tested in production.
CHARACTERISTIC CURVES
1.0
+20
111111
0.9
SIGNAL PiT
O.B
Q
j
1.2
f-+--+_+-,.:::SlG::;;NA~L;:;'N:.:jPU;.T
...
...
- ,;;;60_0m;;';V+--l
07
'"'I
z
I
~
I SIDEBAND
"~
0.6
t1:rt:;~oom~
lL /
~
0.5
~3~
04
~ 0.4 f--jI/.:-;...'l'.......
=--=:b...!-...;2~oo"'mv""'*='I="'l
_
::
0.3 h-rrmnr-rnnrmr-rrTTTlnr-rllI'tttttI
02
111111111 sU}!I)~~T I II111111
~
~
:~
5
0.8
--
~
0 0L..-'--...J.SO--'-_'OLO-'--'...J.S-O-'---'200
CARRIER LEVEL (mVRt.ls)
FIGURE 1.
SIDEBANO DUTPUT VS. CARRIER LEVELS
E = 5000
+10
z
TRANSADt.1ITTANCE
!
0
0
+
I
lRANSADMITTANCE
Y21"~IVOUT=O
11111
1.0
10
100
CARRIER FREQUENCY (MHz)
FIGURE 2.
SIDEBAND AND SIGNAL PORT
TRANSADMITTANCES VS. CARRIER LEVELS .
10-47
-10
0
Z
~
1000
RL
11111111
W
R
~
500
_ lK
V~''::"05VdC
-20
in
jVcj,.05VdC
v"
O~~~~~~~-W~LL~
0.1
RE = 2K
§<
IOUT~~:C~SI~~:~AND) V~T-
---ttttt1
0.1
RL" J9K
RL
39K
Rr = 1K
(Standard
Test Circuit)
W
w
u
r""
R~'~1I3.9K
ro
-30
0.01
IIII1I11 AV = HE :Lzr£
11111111
0'
I
1111111
, 0
10
FREQUENCY (MHz)
FIGURE 3.
SIGNAL-PORT FREQUENCY RESPONSE
'00
•
SG1596/SG1496
CHARACTERISTIC CURVES (continued)
a
~
is
10
~!
20
"-<
~
10
>
"
IZ
.....
Zlc
Ww
"g
0'"
g~
'"
~
60
70
0
i
g
>-
40
"iO
15
20mVRMS
'"w
0.1
fc
0.05 0.1
JfC
.....
0.5 10
50 to
CARRIER FREQUENCY - (MHz)
FIGURE 4.
CARRIER SUPPRESSION VS.
FREOUENCY
50
30
Ie - lOmHz
40
....r
60
0.01
005 01
70
0.5 1.0
50
5.0 10
CARRIER FREQUENCY -
r-
.....
I'\.
a
..-r-
...,. .....
100
200
400
300
CARRIER INPUT LEVEL
FIGURES.
CARRIER FEEOTHROUGH VS.
FREOUENCY
= 500KHz
f
I'\.
(MHz)
.....
./
50
~
'"
'~"
w
.....
20
z
1.0
;0
5~ 50
fU
~~c~4 ~
o~
3.0
~
I''II''~
~
" 1.0~~ ~~"'~
~
~" ~
i
......
0.5
0
0
25
50
75
......
1"1...
100
,
125
150
,
"r\'
2.0
1.0
0
175
0
25
50
75
~
100
~
125
150
175
AMBIENT TEMPERATURE - "C
CASE TEMPERATURE - "c
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Notes 1 and 3)
Operating Ambient Temperature Range
SG3049 .......................................................... -55°C to 125°C
Note 3. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures of -55°C" TA ,,125°C. Low duty cycle pulse testing
techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Parameter
Test Conditions
Static Characteristics (Each Transistor)
Breakdown Voltages
Collector-Base (V(SR)CSO)
Collector..substrate (V(BR)c,J
Collector-Emitter (V(eR)cea)
Emitter-Base (V(8R)EBO)
Collector Cutoff Current (lcsal
Base-Emitter Voltag6 (Vee)
Ic = 10~, IE = 0
Ic = 101lA, Is= 0, IE = 0
Ic = lmA, Is = 0
IE = 10~, Ie = 0
Vce =10V,IE =0
VeE = 3V, Ic" 1mA
TA " 25°C
TA=TMlN
TA=TMAJ(
Static Characteristics (Each Differential Amplifier)
Input Offset Voltage (V10)
IE(Q.) :: le(Q.,) " 2mA, VCB " 3V
Input Offset Current (I,al
le(Q 3) = le(Q4) " 2mA, Vce " 3V
Input Bias Current (luJ
le(Q.) " le(Q4) ,,2mA, Vee'" 3V
DC Gain (hFel
IE(Q3) Il e(03)
O.
Q
I.(Q ) IIR(Q )
10 - 52
SG3049
Units
SO
SO
24
7
100
V
V
V
V
nA
O.SO 0.70 0.80
0.72 0.80 0.92
0.50 O.SO 0.70
V
V
V
0.45
0.30
10
5.0
3.0
45
mV
150
150
300
300
I Mln.Typ. I Max. I
20
20
15
5
35
35
~
IlA
SG3049
ELECTRICAL SPECIFICATIONS (continued)
Parameter
5G3049
Min. Typ. Max.
Test Conditions
Dynamic Characteristics (T _ 25°C)
Common-Mode Rejection Ratio (CMRR)
(Each Amplifier)
Automatic Gain Control Range (AGC)
(Single Stage)
Voltage Gain (Av)
(Single Stage, Double-Ended Output)
Gain Bandwidth Product (9
(Single Transistor)
Noise Figure (NF)
(Single Transistor)
(Each Amplifier)
I
Units
Vce= 12V, VEE = -6V, Vx = 3.3V, f = 1KHz (See Figure 2)
80
dB
Vce= 12V, VEE = -6V, Vx = 3.3V, f = 1KHz (See Figure 3)
75
dB
Vce= 12V, VEE = -6V, Vx = 3.3V, f = 1KHz (See Figure 3)
35
dB
Ie = 3mA, VCE = 3V
600
MHz
VCE = 3V, Ie = 1001lA, Rx= 1KQ, f = 1KHz, BW = 15.7KHz
f = 100MHz
3.25
dB
dB
8
TEST CIRCUITS
Vce
Vec
1K
1K
1K
1K
J
O•1J£
j
1'r,"
I
ViN""O.3Vrms
I
~
500n
SOURCE
r--
pJ
}VOUT
\I
I
VIN =1OmVrms
I
~"
1K
SOURCE
soon
0:-
~ }VOUT
rO. 1JLF
P
soon
0:-
~f~r
f-"H!F
Vx VEE
'Ix
CHARACTERISTIC CURVE
160
,,-
140
I
w
u..
120
1\
/
100
VEE
FIGURE 3 - SINGLE-STAGE VOLTAGE GAIN
FIGURE 2 - COMMON·MODE REJECTION RATIO
/
80
1
10
1-(mA)
FIGURE 1 - DC GAIN VS. CURRENT
10-53
100
-
1K
"7
SG3049
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
14·PIN CERAMIC DIP
J-PACKAGE
Part No.
SG3049J/883B
SG3049J
Ambient
Temperature Range
Connection Diagram
-55°C to 125°C
-55°C to 125°C
[11"714
B2
P N.C.
B3 [ 2
1.P N.C.
E3['
12pC2
B5[411PC1
C5 [ •
B1
C6 [ •
• P E4, SUBSTRATE & CASE
B6 [~P B4
lOP
12-PIN METAL CAN
T-PACKAGE
SG3049T/883B
SG3049T
-55°C to 125°C
-55°C to 125°C
B2
B3
E3
B5
C5
®
®G)@
@ C1
@ B1
@
®
®G)®
C6
C2
B6
®
E4, SUBSTRATE & CASE
B4
Note 1. Contact factory for JAN and DESC product availablity,
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue· Garden Grove, CA 92641 • (714) 898-8121 • TWX: 910-596-1804· FAX: (714) 893-2570
10 - 54
SG3183
SILICON
GENERAL
HIGH-CURRENT NPN TRANSISTOR ARRAYS
LINEAR INTEGRATED CIRCUITS
DESCRIPTION
FEATURES
The SG 3183 series of arrays consists of five, closely-matched,
high-current NPN transistors.
Although sharing a common
monolithic substrate, the transistors are connected such that all
terminals are independent, including the substrate bias connector.
With current capability to 100mA per transistor, these arrays are
ideally suited for all types of driving applications including relays,
lamps, and thyristors.
•
•
•
•
High voltage capability
Collector current to 100mA
Low saturation voltage
Closely matched parameters
HIGH RELIABILITY FEATURES - SG3183
• Available to MIL-STD-883
• SG level "S" processing available
BLOCK DIAGRAM
COll.
1
COll.
2
BASE
2
EMITTER
2
SUBSTRATE
BASE
3
COlL.
3
EMITTER
3
Lbi 1 I nJ f
~
l
~
Ql
II
16
15
14
13
1
BASE
EMITTER
COll.
BASE
EMITTER
EMITTER
COll.
1
1
5
5
5
4
4
April 19S0
10 - 55
SG3183
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Maximum Collector Current .......................................... 100mA
Maximum Base Current .................................................. 20mA
Power Dissipation
Any One Transistor .................................................... 500mW
Total Package ............................................................ 750mW
Operating Junction Temperature
Hermetic (J-Packages) ................................................
Plastic (N, D-Package) ................................................
Storage Temperature Range ............................ -65'C to
Lead Temperature (Soldering, 10 Seconds) ..................
150'C
150'C
150'C
300'C
Note 1. Exceeding these ratings could cause damage to the device.
THERMAL DERATING CURVES
2.5 r--,--,--,--,--,---r----.
50",
4.0
AMBIENT TEMPERATURE -
·c
CASE TEMPERATURE -
MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
RECOMMENDED OPERATING CONDITIONS
MAXIMUM POWER DISSIPATION
"C
vs CASE TEMPERATURE
(Note 2)
Operating Ambient Temperature
SG3183 (J-Package) .................................... -55'C to 125'C
SG3183 (N, D-Package) ...................................... O'C to 70'C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply overthe operating ambient temperatures of -55'C s TA s 125'C for the SG3183 (J-package) and
D'C sTA < 7D'Cforthe SG3183 (N & D - packages). Low duty cycle pulse testing techniques are used which maintains junction and case temperatures
equal to the ambient temperature.)
Parameter
Breakdown Voltage
Collector-Substrate (BVcso)
Collector-Base (BVeBo)
Collector-Em iller (BVeED)
Emitter-Base (BVEBO )
Collector Cutoff Current (lCEO)
Collector Cutoff Current (leBo)
DC Forward Current Transfer Ratio (hFE)
Collector-Emitter Saturation Voltage (VCE(SAT})
Base-to-Emiller Voltage (VBE)
For Q, and Q, Matched Pair:
Input Offset Voltage (VIO)
Test Conditions
Ic= 100llA
le= 1001lA
le= 1mA
IE = 1OOIlA
VeE = 10V
Ves ,,10V
Min.
40
40
30
5.0
=
V CE " 3V, Ie 10mA
TA = 25'C
V cE =3V,l e =10mA
TA =25'C
Ie " 50mA, I. " 5mA
VCE =3V, Ie = 10mA
TA " 25"C
V CE =3V, Ic= lmA
40
50
35
40
0.50
0.65
SG3183
Typ. Max.
70
70
40
10
V
V
V
V
IlA
1
!lA
3.0
0.95
0.85
V
V
V
10
5.0
5.0
2.5
mV
mV
IlA
IlA
6.9
100
75
1.7
0.75
TA
=25'C
1.2
T
=25'C
0.7
Input Offset Current (lId
10 - 56
Units
SG3183
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
Part No.
Ambient
Temperature Range
-55·C to 125·C
-55·Cto 125·C
16-PIN CERAMIC DIP
J- PACKAGE
SG3183J/8B3B
SG3183J
16-PIN PLASTIC DIP
N- PACKAGE
SG31B3N
O·C to 70·C
16-PIN SOIC
D- PACKAGE
SG3183D
O·Cto 70·C
Connection Diagram
C1 [-,--=-;s:::J B1
C2[2
,,:::JE1
B2[314:::JC5
E2 [4
13:::J 85
SUBSTRATE [5
12:::J E5
B3[611:::JE4
C3['
10:::JB4
E3 [~:::J C4
C1
C2
B2
E2
SUBSTRATE
B3
C3
E3
IT
IT
IT
IT
IT
IT
IT
IT
1
2
3
4
5
6
7
8
16
fTI
B1
"P:::J
14 t:o
13 P:::J
E1
C5
B5
121=0 E5
11
E4
10
84
9
C4
P:::J
P:::J
PJ
II
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
Silicon General •
11861 Western Avenue' Garden Grove. CA92641 • (714) 898-8121' TWX: 910-596-1804' FAX: (714) 893-2570
10-57
10 - 58
SG3821 /SG3045/SG3046
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
MATCHED NPN TRANSISTOR ARRAYS
DESCRIPTION
FEATURES
These five matched transistors are general purpose NPN
transistors configured with two internally connected to form a
differential amplifier, each with its own associated source
transistor. They are well suited to a wide variety of applications
in low power systems in the DC through VHF range. In addition
to being used as discrete transistors in conventional circuits,
they also provide the very significant inherent integrated circuit
advantages of close electrical and thermal matching. These
transistor arrays offer V BE typically matched to ±0.5mV, less
than 10% variation in hFE' operation from DC to 300M Hz, high
current gain from 101lA to 10mA, and high voltage capability.
•
•
•
•
•
Two matched transistor pairs :to.5mV
Five general purpose matched transistors
Operation from DC to 300M Hz
High current gain
High voltage capabilities
HIGH RELIABILITY FEATURES· SG3821
• Available to MIL·STD·883
• SG level "S" processing available
SCHEMATIC DIAGRAM
• Substrate pin must be connected to the most
negative DC potential- which should also be a good
AC ground - for proper isolation between
transistors.
April 1990
10-59
SG3821/SG3045/SG3046
ABSOLUTE MAXIMUM RATINGS (Note 1)
Collector to SubstrateVoltage .............................................. 40V
Collector to Base Voltage .................................................... 40V
Collector to Emitter Voltage ................................................ 2SV
Storage Temperature Range ............................ -6SoC to 1S0°C
Operating Junction Temperature
Hermetic (J-Package) ...... .......................... ......... ....... 1S0°C
Plastic (N-Package) .. ...... .... ....................... ....... ....... ... 1S0°C
Storage Temperature Range ............................ -6SoC to 1S0°C
Lead Temperature (Soldering, 10 Seconds) .................. 300°C
Note 1. Exceeding'these ratings could cause damage to the device.
THERMAL DERATING CURVES
i,
2.5
50~
2.0
'.0
~
~
"
'5-
, 0
~
~'l-s:"
~
'.0
">
~~
2 . 0 - I--",r,.,. . /:J
"''''<~
~
"'~~~~
0
25
"'~~
~
0.5
0
'\I\.
30
50
75
'00
~~
~
AMBIENT TEMPERATURE -
'25
150
'.0
0
175
"C
0
25
50
75
~
"'~
\.
"~
'00
CASE TEMPERATURE -
MAXIMUM POWER DISSIPATION vs AMelENTTEMPERATURE
'25
,SO
175
we
MAXIMUM POWER DISSIPATION vs CASE TEMPERATURE
RECOMMENDED OPERATING CONDITIONS (Note 2)
Operating Ambient Temperature Range
SG304S, SG3821 .......................................... -SsoC to 12S"C
SG3046 .......... ........ ........................ .................... O°C to 70°C
Note 2. Range over which the device is functional.
ELECTRICAL SPECIFICATIONS
(Unless otherwise specified, these specifications apply for the operating ambient temperature of TA =25°C. Low duty cycle pulse testing techniques
are used which maintains junction and case temperatures equal to the ambient temperature.)
SG3821/3046
SG304S
Parameter
Test Conditions
Units
Min. Typ. Max. Min. Typ. Max.
Breakdown Voltage:
Collector-Substrate (BVcso)
40
20
V
Ie = 1O",A, Ie = 0
Collector-Base {BVcsol
40
Ie = 10!lA, IE = 0
20
V
2S
1S
Collector-Emitter (BVCEO)
V
Ie = 100!lA, Ie = 0
S
V
Emitter-Base (BV_)
S
Ie" 10!lA, Ic = 0
Leakage Current
nA
Collector-Substrate (Iceo)
80
80
Vcs = 20V, Ie = 0
40
Collector-Base (leso)
nA
40
Vce = 20V, Ie = 0
VcE =20V,l s =0
Collector-Emitter (Iceol
SOO
SOO
nA
Forward Current-Transfer Ratio (hFE)
80
80
VeE = SV, le= 10!lA
SO
400
400
50
Vce '" SV, Ie'" 1mA
80
VCE = SV, Ic= 10mA
80
0.5
Base-to-Emitter Voltage fY Bel
Vee" SV,.l e ", 10mA
0.5
V
0.9
O.S
O.S
0.9
V
le= 10mA, le= 1mA
Collector-Emitter Saturation fYCE(SAT])
SOO
Gain·Bandwidth Product
500
MHz
Ves = SV" le= 3mA
Collector-Substrate Capacitance
2.0
2.0
pF
Ves =SV, le= 0
Collector-Base Capacitance
0.4
pF
0.4
Vee'" SV, Ie'" 0
Noise Figure
4
4
dB
f = 1KHz, VCE = SV, le= 100mA, Rs =1kQ
Input Offset Voltage fY ro>
Vee'" SV,le=1mA
.
S
mV
5
4
Input Offset Current (I,ol
2
VeE = SV, le=1mA
!lA
10-60
SG3821/SG3045/SG3046
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
Package
14·PIN CERAMIC DIP
J - PACKAGE
14-PIN PLASTIC DIP
N - PACKAGE
Part No.
SG3821J/883B
SG3821J
SG3821N
SG3045J/883B
SG3045J
SG3046N
Ambient
Temperature Range
-55'C to
-55'C to
O'Cto
-55'C to
-55'C to
125'C
125'C
70'C
125'C
125'C
O'Clo 70'C
Connection Diagram
C1 l-.,-Cr "4 l
B1
13 ~I
12
12 J
COMMON EMITTER 01 ,02 ".;3
11 .1
B2 ~
10
I
C2 "15
B3 _ 6
9J
6l
E3 ..1.
i'
C5
E5, SUBSTRATE AND CASE
85
C4
E4
B4
C3
II
Note 1, Contact factory for JAN and DESC product availablity,
2, All packages are viewed from the top,
Silicon General·
11861 Western Avenue' Garden Grove, CA92641 • (714) 898-8121' TWX: 910-596-1804' FAX: (714) 893-2570
10 - 61
10-62
THUMB INDEX
SILICON
GENERAL
81
III
III
III
III
III
I
0
I
III
III
I
III
III
TABllE OF CONTENTS
PART NUMBER
GENERAL
~NFORMATION
~NFORMATION
[plOWIER SUPlPlV
C~RCU~TS
MOr~ONl
CONTROL
[plOWER
IDR~VIER
OPERAT~ON
CIRCU~TS
AND
~NTIEIRFACIE C~RCUITS
AMPUfllERS AND COMPARATORS
CORlE MIEMORV
C~IRCU~TS
AUTOMOr~VIE C~IRCU~TS
OTHER CIRCUITS
PACKAGE INFORMATION
APIPUCAT~ON
INfORMATION
SALlES OFfICES
11 - 1
I
I
I
I
I
I
I
I
I
I
I III
I
I
THERMAL CHARACTERISTICS
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
No.
of
Pins
Pkg.
Symbol
JEDEC
No.
8J•
SJC
('C!IN)
('C!IN)
Po
25'C
(mW)
Derate
>25'
PLASTIC DUAL-IN-LiNE (DIP)
8
14
16
16
18
20
22
24
24
28
40
M
N
N
W
N
N
N
N
N
N
N
(Batwing)
(Wide)
(Narrow)
No.
of
Pins
(mWI'C)
OM
0
0
OW
OW
OW
DWW
(Batwing)
JEDEC
No.
SJ'
(0C!lN)
8JC
(OC/W)
Po
25°C
(mW)
Derate
>25'
(mWfCl
CERAMIC LEAD LESS CHIP CARRIER
95
65
65
45
60
60
55
52
58
45
40
60
40
40
15*
30
30
27
25
29
20
15
1050
1540
1540
2220
1670
1670
1820
1920
1720
2220
2500
10.5
15.4
15.4
22.2
16.7
16.7
18.2
19.2
17.2
22.2
25.0
20
165
120
120
95
90
86
50
55
50
50
40
35
32
12*
610
830
830
1050
1110
1160
2000
6.1
8.3
8.3
10.5
11.1
11.6
20.0
60
50
55
45
45
4.5*
1.5'
4.0'
2.0*
2.0'
1670
2000
1820
2220
2220
16.7
20.0
18.2
22.2
22.2
80
70
35
20
1250
1430
12.5
14.3
130
80
80
70
50
30
30
25
960
1560
1560
1790
7.7
12.5
12.5
14.3
100
100
85
30
30
25
1250
1250
1470
10.0
10.0
11.8
80
80
70
70
70
860
890
1090
1090
1140
6.9
7.1
8.7
8.7
9.1
L
(LCC)
120
35
1040
8.3
TO-46
TO-52
TO-39
TO-3
TO-66
TO-66 (SM)
TO-3 (SM)
TO-66
TO-99
TO-66
TO-l 00
TO-96 (tall)
TO-l01
440
440
120
35
40
40
35
40
130
130
130
130
80
80
15
3.0
5.0
4.0
2.0
5.0
25
5.0
25
25
25
200
280
1040
3570
3120
3120
3570
3120
960
3120
960
960
960
2.3
. 2.3
8.3
28.6
25.0
25.0
28.6
25.0
7.7
25.0
7.7
7.7
7.7
42
42
3.5*
3.5*
2980
2980
23.8
23.8
METAL CANS
2
3
3
3
3
4
4
5
8
9
10
10
12
PLASTIC SMALL OUTLINE (S.O.I.C.)
8
14
16
16
18
20
20
Pkg.
Symbol
Z
Z
T
K
R
R
K
R
T
R
T
T
T
40
TO-257 (HERMETIC TO-220)
3
3
G
IG
(Non-Iso)
(Isolated)
PLASTIC (POWER)
3
3
5
12
12
P
V
P
S
ST
TO-220
TO-247
TO-220
(SIP)
(SIP)
• = BJT (Junction to Tab)
Note: This data is for reference only as it does not account for thermal
transfer characteristics of variable die sizes.
PLASTIC LEADED CHIP CARRIER
20
28
Q
Q
(PLCC)
(PLCC)
CERAMIC DUAL-IN-L1NE
8
14
16
18
y
J
J
J
TO-116
CERAMIC SIDE BRAZED (DIP)
14
16
18
H
H
H
CERAMIC FLAT PACK (CERPAC)
10
14
16
20
24
F
F
F
F
F
145
140
115
115
110
January 1990
11 -2
MECHANICAL DIMENSIONS
PLASTIC MINI·DIP
a·PIN
"M"SUFFIX
NOTES:
1. 62S-D3 OBSOLETE NEW STD 626-04.
2. DIMENSION "L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
4. DIMENSIONS A AND B ARE DATUMS,
5. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5,1973.
MILLIMETERS
DIM
A
B
C
0
NOTE 4
F
G
H
J
K
L
M
NOTES:
1. LEADS WITHIN O.13mm (0.005)
RADIUS OF TRUE POSITION AT
SEATING PlANE AT MAXIMUM
CONDITION.
2. DIMENSION "L" TO CENTER OF
LEADS WHEN FORMED
PARALLEL.
3. DIMENSION "8" DOES NOT
INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL
PLASTIC DIP
14-PIN
"N" SUFFIX
I
I
e
F
G
H
J
K
L
M
NOTES:
1. LEADS WITHIN 0.13mm (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
CONDITION.
2. DIMENSION "L" TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. DIMENSION "S" DOES NOT INCLUDE MOLD
FLASH.
4. "F" DIMENSION IS FOR FULL LEADS. "HALP
LEADS ARE OPTIONAl AT LEAD POSITIONS 1,B,9,
AND16
5. ROUNDED CORNERS OPTIONAL.
PLASTIC DIP
16·PIN
"N"SUFFIX
I
:_F~_---I
NOTE 5.
?
OPTIONAL LEAD
CONFIG. (1, 8, 9, & 16)
5.10
-
0.38
0.51
0.76
1.52
2.54 Bse
0.76
1.83
0.20
038
3,18
7.62
0.015 0.020
0030 0.060
0.100 Bse
0.030 0.072
0.008 0.015
0.125
0.300 sse
15
-
5.08
0.200
0.51 0.015 0.020
1.52 0.030 0.060
sse 0.100 sse
1.83 0.030 0.072
0.38 0.008 0.015
3,18
0.125
7.62 sse
0.300 SSC
15
15 u
038
0.76
2.54
0.76
0.20
-
TERS
X
94
60
08
0.51
0.76
1 52
2.54 BSe
0.76
1.83
INCHES
MIN
MAX
0.730 0.785
0.240 0.260
0.200
0.015 0.020
0.030 0.060
0.1 DO sse
0.030 0.072
~+Ot·2ij0tt;~0~.3~8~0.~00~8~0~.0~15~
I37~g2 BSe °Ol.~go sse
tM=t~~~1~5~~~~15~
0.38
2.54
064
0.20
3.18
7.62
0.76
11 - 3
sse
15
PLASTIC DIP BATWING
16·PIN
"W"SUFFIX
January 1990
INCHES
MAX
MIN
MAX
10.16
0400
6.60 0240 0.260
5.08
.200
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A 18.54 19.94 0.730 0.785
7.11 0.220 0.280
B 5.59
0
NOTE 4.
MIN
ERS
AX
19.94
6.60
5.08
0.64
BSe
1.52
0.38
INCHES
MIN
MAX
0.730 0.785
0.240 0.260
0.200
0.015 0.025
0.100 BSe
0.025 0.060
0.008 0.015
0.125
BSe
0.300 BSe
15
15
152 0.030 0060
III
MECHANICAL DIMENSIONS
PLASTIC DIP
18·PIN
"N" SUFFIX
NOTES;
1. POSITIONAL TOLERANCE OF
LEADS (0). SHALL BE WITHIN
O.25mm(O.010) AT MAXIMUM
MATERIAL CONDITION, IN
RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION "LO TO CENTER OF
LEADS WHEN FORMED
PARALLEL.
3. DIMENSION "B" DOES NOT
INCLUDE MOLD FLASH.
MILLIMETERS
DIM MIN
MAX
A 22.61
B
6.10
C
3.56
o
0.36
F
G
H
J
K
L
M
N
PLASTIC DIP
.20·PIN
"N" SUFFIX
r:I :::::::::
Ii
· ~,L
~,
MILLIMETERS
DIM MIN
MAX
A 2591 26 42
B
610
660
r,'=:]
G
LSEATING
C
3.56
F
1.27
0- - 0.38
G
f=1.
JMAMWMr~
~
-J ~ o~ ~
H
0.38
2.54
4.57
0.53
178
sse
H
1.02
1.52
J
0.20
0.36
K
318
L
M
N
7.62 Bse
0.38
15
064
0.015
"
PLANE
NOTES:
PLASTIC DIP
22·PIN
"N" SUFFIX
1. PACKAGE DIMENSIONS
CONFORM TO JEDEC
SPECIFICATION MS·010·AA FOR
STANDARD DUAL IN-UNE (DIP)
PACKAGE .400 INCH ROW
SPACING (PLASTIC) 22 LEADS
(ISSUE A. 7/85).
2. DIMENSIONS AND TOLERANCING
PER ANSI V14.SM-1982.
3. THESE POINTS ARE REFERENCE
DATUMS ON THE MOLDED BODY
AND DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD
FLASH AND PROTRUSIONS
SHALL NOT EXCEED 0.010 INCH
(.25mm) ON ANY SIDE.
on::::::::::: lJ
NOTE'.
1
A
1
-'~R:
~
0-11-
PLASTIC DIP (WIDE)
24·PIN
"N" SUFFIX
-I G I-
MILLIMETERS
DIM MIN
MAX
A 27.81 28.19
B 13.21 13.72
4.19
4.83
C
0.56
D 0.43
F
1.14
1.63
G
2.54 SSC
0.25 0.035
J
K 3.05
3.51
L
10.16 10.72
M
15
N
0.51
0.89
INCHES
MIN
MAX
1.095 1.110
0.520 0.540
0.165 0.190
0.017 0.022
0.045 0.064
0.100 8SC
0.010 0.015
0.120 0.138
0.400 0.422
15
0.020 0.035
SmNG
PlANE
f----- A ---.-1
24
12
NOTES:
1. LEADS WITHIN 0.13mm (0.005)
RADIUS OFTRUE POSITION AT
SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO CENTER OF
LEADS WHEN FORMED
PA.RALLEL.
HI-
~.
~e-c
-l--c
Ir='~
w-~ -1-;:=1
SEATINGJI
PLANE
January 1990
11 - 4
DIM
A
B
C
0
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
31.50
13.72
3.56 4.57
0.38 0.53
1.27
178
2.54 SSC
1.02
1,52
0.20
0.36
3.18
15.24 BSC
15
0.38
0.64
-
INCHES
MIN
MAX
1.240
0.540
0.140 0.180
0.015 0.021
0.050 0.070
0.100 SSC
0.040 0.060
0.008 0.014
0.125
0.600 SSC
15
0.015 0.025
MECHANICAL DIMENSIONS
PLASTIC DIP
24-PIN
"N" SUFFIX
(NARROW)
MILLIMETERS
DIM MIN
MAX
A 29.21 29.85
610
686
C
508
0
038 051
F
076 152
G
254 sse
H
076
1 52
J
0.20 038
K
318
762 sse
L
M
15
P
635 660
V 305 356
a
PLASTIC DIP
28-PIN
"N" SUFFIX
I
0200
0.015 0020
0030 0060
a 100 sse
0.030 0060
00080015
0125
0300 GSC
15
0250 0260
0.1200140
I
A
-I
::t
[::::::::::::IJ
DIM
B
~Hf-
C
0
~~pc~
~I--o
INCHES
MIN
MAX
1.150 1 175
0240 0270
+0
V,i
SEATINGn
PLANE
i
'
F
G
H
J
K
L
M
N
ERS
MAX
INCHES
MIN
MAX
3556 1.360 1.440
13.21 0.500 0.520
5.08
0.200
038 056 0015 0.022
0.76 1 52 O.O~O 0.060
2.54 sse
0.100 sse
0.76
1.78 0.030 0.070
020
0.38 00080015
3.18
0125
15.24 sse 0.600 asc
15"
15"
0.51
0.020
-
-
-
PLASTIC DIP
40-PIN
"N" SUFFIX
PLASTIC S.O.I.C.
8-PIN
"OM" SUFFIX
NOTES:
1. ·K·ISSEATINGPlANE.
2. DIMENSION "A" IS DATUM.
MILUMETERS
DIM
A
8
C
0
F
G
J
K
L
P
January 1990
11 - 5
MIN
4.65
3.66
1.73
0.25
0.38
1.27
019
0.13
4.80
5.79
MAX
5.13
414
188
0.46
0.89
sse
0.25
0.25
5.21
6.20
INCHES
MIN
MAX
0.183 0.202
0.144 0.163
0.068 0.074
0.010 0.018
0.015 0.035
0.050 sse
0.007 0.010
0.005 0.010
0.189 0.205
0.228 0.244
II
MECHANICAL DIMENSIONS
PLASTIC S.O.I.C.
14-PIN
"O"SUFFIX
IRRRA~
14
~TI
B
NOTES:
DIM
A
B
C
D
F
G
J
K
L
P
1. DIMENSION W IS DATUM.
P
t;::;::;::;:::;~:;=;:;:7~
---11-- D
PLASTIC S.O.I.C.
16-PIN
"0"SUFFIX
ru--u---u--u-....L.L.i...L..~hl
NOTES:
1. DIMENSION W IS DATUM.
B P
C
D
F
G
---1 I-- D
INCHES
MIN
MAX
0.336 0.344
0.150 0.158
0.053 0.069
0.014 0.018
0.026 0.030
0.050 sse
0.007 0.010
0.004 0.008
0.189 0.205
0.228 0.244
ES
MAX
0.394
0.158
0.069
0.018
0.D20 0.030
0.050 BSC
0.007 0.010
DIM
A
B
1:;::;::::;:;:=:;:=;::;::::;::;::;::::;::r::;8~
---1GI--
MILLIMETERS
MIN
MAX
8.54 8.74
3.81
4.01
1.35 1.75
0.35 0.46
0.67 0.77
1.27 BSC
0.19
0.25
0.10
0.20
4.82
5.21
5.79
6.20
0.004 0.008
0.189 0.205
0.228 0.244
PLASTIC S.O.I.C.
16-PIN WIOEBOOV
"OW"SUFFIX
NOTES:
1. PACKAGE DIMENSIONS
CONFORM TO JEDEC
SPECIFICATION MS-013-AA FOR
STANDARD SMALL OUTLINE (SO)
PACKAGE, 16 LEADS, 7.50mm
A ~
1
'-!-;',-LLJ.-'--LL.l.
r;
9
(.300,,) BODY WIDTH (ISSUE A,
JUNE 19B5).
2. DIMENSIONS AND TOLERANCING
PER ANSI Y14.SM-1982.
NOTE 3.
L
B
1
3. ~~~~~~~:'i."o~~~R:~g;
P
~
ANDDONOTINCLUDEMOLO
FLASH OR PROTRUSIONS. MOLD
FlASH AND PROTRUSIONS
SHALL NOT EXCEED 0 15mm
(.006") ON ANY SIDE.
8
~
--I G I--
--I I--
D
~c
NOTE 3.
~b±u±d2±i±6±uLJSEATING PLANE
PLASTIC S.O.I.C.
18-PIN WIOEBOOV
"OW"SUFFIX
~
J J
NOTE 3.
L
101
B
1
-I GI~
P
~l
0-11-
~&2lJ±2Ld±±ElJ±6-t
K
January 1990
11 - 6
-
t
INCHES
MIN
MAX
0.420
0.295 0.305
0.093 0.104
0.010 0.018
0.025 0.035
0.050 8SC
0.009 0.013
0.004 0.012
0.320 0.340
00
80
0.404 0.419
-
F
(OIl6") ON ANY SIDE.
~c
NOTE 3.
SEATING PLANE
M
NOTES:
1. PACKAGE DIMENSIONS
CONFORM TO JEDEC
SPECIFICATION MS-013-AAFOR
STANDARD SMALL OunlNE (SO)
PACKAGE, 16 lEADS, 7 _SOmm
(.300") BODY WIDTH (ISSUE A,
JUNE '985).
2. DIMENSIONS AND TOLERANCING
PER ANSI Y14.SM-1982.
3. THESE POINTS ARE REFERENCE
DATUMS ON THE MOLDED BODY
AND DO NOT INCLUDE MOLD
FlASH OR PROTRUSIONS. MOLD
FlASH AND PROTRUSIONS
SHAll NOT EXCEEDO.15mm
A~
~:-'-L....'--,--"W-.L.L
=J
-
+~
--jl=fr
t
K
L
MILLIMETERS
DIM MIN
MAX
A
10.67
8 7.49 7.75
C 2.35 2.65
D 0.25 0.46
F
0.64 0.89
1.27 BSC
G
J
0.23
0.32
K 0.10
0.30
8.64
L 8.1.3
00
80
M
P 10.26 10.65
J
~L~
M
+= ~~
-II=Tr
J
F
MILLIMETERS
DIM MIN
A
8 7.49
C 2.35
D 0.25
F D.64
G
1.27
J
0.23
K 0.10
L
8.13
MAX
13.21
7.7S
2.65
0.46
0.89
8SC
0.32
0.30
8.64
MOo
80
80
P 10.26 10.65 0.404 0.419
MECHANICAL DIMENSIONS
PLASTIC S.O.I.C.
20-PIN WIOEBOOY
"OW" SUFFIX
@
NOTE 3.
L
1
B
P
10
~
-I G I-
D -II-
NOTES;
1. PACKAGE DIMENSIONS
CONFORM TO JEDEC
SPECIFICATION MS·013·AA FOR
STANDARD SMALL OUTliNE (SO)
PACKAGE, 20 LEADS, 7.50mm
(.300') BODY WIDTH (ISSUE A.
JUNE 1965).
2. DIMENSIONS AND TOLERANCING
PER ANSI Y14 5M-19S2.
3. THESE POINTS ARE REFERENCE
DATUMS ON THE MOLDED BODY
AND DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS MOLD
FLASH AND PROTRUSIONS
SHALL NOT EXCEED 1Smm
(COBIONANYSIDE
1::=
~
NOTE 3.
~lli6±i±i±ia±iEt2Ut~
L
~
PLASTIC S.O.I.C. BATWING
20-PIN WIOEBOOY
"OWW" SUFFIX
F
J
023
032
K
L
M
P
0.10
8.13
0 . .30
8.64
00
80
1026 10.65
DIM
A
MILLIMETERS
MAX
MIN
1.3 21
INCHES
MAX
MIN
-
0.520
0.295 0.305
0093 0.104
0.010 0018
0025 0.035
0050 BSC
0009 0.01.3
0004 0.012
0.320 0340
Do
80
0.404 0419
r
NOTES:
,. PACKAGE DIMENSIONS
CONFORM TO JEDEC
SPECIFICATION MS-013·AA FOR
STANDARD SMALL OUTLINE (SO)
PACKAGE. 20 LEADS, 750mm
(.300") BODY WIDTH (ISSUE A,
JUNE 1985).
NOTE 3.
L
11
B
D
~
D-n-
~
-IGI-
P
~
NOTE 3
~lli6J5hRhEU±2Ld~
2. DIMENSIONS AND TOLERANCING
PER ANSI V14.5M-1982.
3. THESE POINTS ARE REFERENCE
~~6uo~Sr?O~~~L~~~0~g~oOOY
FLASH OR PROTRUSIONS MOLD
FLASH AND PROTRUSIONS
SHALL NOT EXCEED 15mm
(006') ON ANY SIDE
1::=
L
~
~~
; J f J T~
SEA TING PLANE
F
PLASTIC TO-220
3-PIN
"P" SUFFIX
PLASTIC SIP
3-PIN
"V" SUFFIX
B
C
0
-
~}E3{
F-I8
; J f J T=
"SEATING PLANE
M
G
MILLIMETERS
MAX
MIN
1321
749 7.75
2.35 2.65
0.25 0.46
0.64 0.89
1 27 BSC
DIM
A
B
C
0
F
G
r-t
L
M
M
P
INCHES
MIN
MAX
0520
749 775 0295 0305
236 2.64 0093 0104
025 046 0.010 0018
064 089 0.025 0035
0050 BSC
1.27 SSC
033 0009 0.01.3
~
0.10
0 . .30 0.0040012
864 0320 0340
813
8
8
1026 1064 0.404 0419
r
-18
MILLIMETERS
INCHES
DIM MIN
MAX
MAX
MIN
A 1422 1588 0.560 0625
B 9.65 1067 0.380 0420
C 356 483 0140 0190
051
1 14 0.020 0045
0
F
353 4.09 01.39 0.161
a 100 TYP
G
254 TYP
H
6.35
0250
J
0.30
114 0012 0045
K 12701473 0.500 0.580
114
127 0.045 0050
L
N
508 TYP
0200 TYP
Q
2.54 3 05 0100 0.120
R 2 03 2.92 0.0800115
1 14 1 40 0045 0055
S
T 584 686 0.230 0270
U 0508 1 14 0020 0045
r
TO-247
c
MILLIMETERS
DIM MIN
MAX
A 20.83 21.34
B
16.26
C 4.83 5.33
1.14
1.27
0
E 318
3.43
G
5.08BSC
H
2.79
J
0.51
0.71
K 12.70 20.07
L
3 05 3.56
S
3.81
432
-
W
G--1
January 1990
11 -7
INCHES
MIN
MAX
0.820 0.840
0.640
0.190 0.210
0.045 0.050
0.125 0.135
0.200BSC
0.110
0020 0.028
0500 0790
0120 0140
0.150 0.170
0.135
3.43
III
MECHANICAL DIMENSIONS
PLASTIC TO·220
5·PIN
"P"SUFFIX
NOTES:
1. LEAD SPACING TOLERANCE IS
NON-CUMLATIVE.
2. EACT BODY CONFIGURATION AT
VENDOR'S OPTION WITHIN
LIMITS SHOWN.
3. LEAD GUAGE PLANE IS O.O3O~
(O.76mm) MAX. BELOW SEATING
PLANE.
F
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A 14.23 16.51 0.560 0.650
8
C
D
F
G
J
5
K
N
R
5
T
PLASTIC SIP
12·PIN
"ST" SUFFIX
8-----1
9.66
3.56
0. 4 6
3.56
3.40
10.66
4.82
0.89
4.06
0.380 0.420
0.140 0.190
0.018 0.035
0.140 0.160
0.134
0.31 1.14 0.012 0.045
.12.70 14.73 0.500 0.580
0.268 TYP
6.80 TY?
2.04 2.92 0.060 0.115
1.14 1.39 0.045 0.055
5.85 6.85 0.230 0.270
-
INCHES
MIN
MAX
DIM
A
V
29.97
3.30
0.55
E 3.48
F 0.46
2.54
G
H
1.78
J 0.20
K 7.62
L 7.62
P
Q 11.18
R 1.78
5
T 13.21
U 8.B9
V 27.69
W 19.56
Z 7.37
8
C
0
PLASTIC SIP
12·PIN
"S"SUFFIX
0.535 0565
0170 0.200
0022 0.026
0850
8
C
o
I- s
I
-+- J
~~~
,,~
PLASTIC LEADED CHIP
CARRIER (PLCC)
20·PIN
"Q" SUFFIX
:;
182°
0
23
i
!p
L...1
1
0100 TYP
0.014 0018
1.100
N
Q
R
S
T
U
W
DIM
A
8
C
o
G
J
L
M
N
P
January 1990
11 ·8
0.56
TY?
TYP
0.30
12.70
B.64
27.94
11.43
2.29
1.27
13.72
9.40
28.19
20.32
7.87
0.550 0.570
1.180 1.220
0.130 0.150
0.022 0.026
0.137 0.147
0.018 0.022
0.100 TYP
0.070 TYP
0.008 0.012
0.300 0.500
0.300 0.340
1.100
0.440 0.450
0.070 0.090
0.050
0.520 0.540
0.350 0.370
1.090 1.110
0.770 O.BOO
0.290 0.310
INCHES
MIN
MAX
1 160 1 190
DIM
A
R-j
-
610
2362
203
1.78
660
6.60
0.240 0.270
0930 0960
00800100
0.070 0.090
0260 0280
0.260 0280
0071
INCHES
MIN
MAX
0.362 0.395
0.350 0.356
0.318 0.330
0.026 0.032
0.047 0.053
0.014 0.018
0.160 0.188
0.050
0.060
0.095
Q
3
R
0.025 0.045
M~CHANICAL
DIMENSIONS
II" "gr.~~~,,~,,~,,~,~===--
PLASTIC LEADED CHIP
CARRIER (PLCC)
2a-PIN
"Q" SUFFIX
.
""
"
"
DIM
L{
M~\~'ME:J:J
M:N CHES
12.19 12.70 0 480
J
L
M
-1!
P
o
e
O~3r 6Y~6
406
"'4
O' 76
2' 41
3
R063
'3
.
4.83
1.27
6
1.~4
0.050
NOTES:
1. LEADSWITININ013mm(
RAD OF TRUE POSITION
DIP
TYP
0.014 0.018
0.160 0.190
0,045
0.030 0.050
0.095
36"
O.~25 O.~
0.25
CERAMIC MINI
a-PIN
"Y" SUFFIX
oMt~o
gG ~n~
n:~~ g.!~g g::gg
. 4 0.89 0 025 0035
0.010
~~05)
~~~~~~~~~~O~AXIMUM
2. DIMENSION "L" TO CENTER OF
~~~~.EN FORMED
INCHES
O~~O o~::a
DIM
A
B
C
o
10.92
7.11 0.220 0.280
5.080.1700200
1 02
051
0.015 0.020
B~~8 °O~{go °B~~O
F
G
H
J
6
~6
3"8
0.3000080012
K
737
4.06 0.125 0.160
L
M
N
2 54
.
0.51
1.65 0.045 0.065
7.87 0.290 0.310
15
1.02 0.020
15
a 040
CERAMIC DIP
14-PIN
"J" SUFFIX
DIM
A
B
e
o
F
~
MILLIMETERS
MIN
MAX
INCHES
MIN
MAX
1880 19.94
559 711
508
0.381 0.51
1.02 1 77
2 54 ~S~3
0.740 0785
0220 0280
0200
0.015 0020
0.040 0.070
0100 sse
~ ~ ;~3
CERAMIC DIP
16-PIN
"J" SUFFIX
~d
mMm-r
JI-
..J..C
H
-I G I-
D-I~
January 1990
11 - 9
SEATING
PLANE
737
7.87
g.~~~
N
0.51
0'i6
0.020
MILLIMETERS
DIM MIN
MAX
A 18.80 19.94
5.59
7.11
B
5.08
C
D 0.38
0.51
1.77
F 0.76
2.54 sse
G
H
2.03
J
0.20 0.30
K 3.18
L
7.37 7.B7
M
15
0.76
N 0.51
F\
- Jj Ic' =:i1
0381 0.008
~
J
M
gg~g
0.310
O'~
INCHES
MIN
MAX
0.740 0.7ifu
0.220 0.280
g~~
0.015
0.030 0070
0.100 SSC
-
0.080
O.OOB 0.012
0.125
0.290
°iW
0.020 0030
II
MECHANICAL DIMENSIONS
CERAMIC DIP
l8·PIN
"J" SUFFIX
C:::::]J
I
NOTES:
1. LEADS, TRUE POSITIONED
WITHIN O.25mm (0.010) OIA. AT
SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO CENTER OF
LEADS WHEN FORMED
PARALLEL.
3. DIM "A" & "S" INCLUDES
MENISCUS.
I
A
JL f-- - f-\~~
J~J!r'1
fH F -.j
D-.j
G
MILLIMETERS
DIM MIN
MAX
A
24.38
B 5.59
7.11
C
5.08
0 0.38 0.51
F
0.76
1.78
G
2.54 sse
H
2.03
J
0.20
0.30
K
3.18 5.08
7.37 7.B7
L
M
15
0.51
0.76
N
INCHES
MIN
MAX
0.960
0.220 0.280
0.200
0.15 0.020
0.030 0.070
0.100 Bse
o.OBo
0.008 0.012
0.125 0.200
0.290 0.310
15
0.020 0.030
M
LSEATING
PLANE
CERAMIC SIDE BRAZED (DIP)
l4·PIN
"H"SUFFIX
rF~==n
~--r
MILLIMETERS
~~
L'~ 1'1~
-,-C
J±f~
D-II-
I- G
P
H-r
DIM MIN
MAX
A 18.54 19.81
7.11
8.13
B
C
0.18
D
0.38 0.53
1.78 TYP
E
F
1.02 1.40
G
2.54 TYP
H
1.78 3.05
K
3.18
7.37
L
7.11
8.13
M
064 1.14
N
P 15.00 15,49
0.76
Y
Z 11.81 12.32
-
B
C
0
E
F
G
H
K
L
M
N
P
Y
Z
lE5:1J
I
A
1
~ ~ ~LI~
YY-~
~ ~ ~ ~ ~ ~ ~ ~ \~~
Fl-r
IE
-I
I-G
0.070 TYP
0.040 0.055
0.100 TYP
0.070 0.120
0.125
0.290
0.280 0.320
0.025 0.045
0.590 0.610
0.030
0.465 0.485
I- M--oj
DIM
A
I
MAX
SEATING PLANE
CERAMIC SIDE BRAZED (DIP)
l6·PIN
"H"SUFFIX
CERAMIC SIDE BRAZED (DIP)
l8·PIN
"H"SUFFIX
INCHES
MIN
07300.780
0.280 0.320
0.007
0.015 0.021
o-jl-
P
January 1990
11 ·10
IL
I--M-I
SEATING PLANE
MILLIMETERS
MIN
MAX
19.81 20.32
7.11
8.13
0.18
0.3B 0.53
1.78 TYP
1.02
1.40
2.54 TYP
1.78 3.05
3.18
7.37
7.11
8.13
0.64 1.14
17.53 18.03
0.76
11.81 1232
INCHES
MIN
MAX
0.780 D.8DO
0.280 D.320
0.007
0.015 0.021
0.070 Tyr
0.040 0.055
0.100 TYP
0.07D 0.120
0.125
0.290
0.28D 0.320
0.025 0.045
0.69D 0.71D
0.030
0465 0485
MILLIMETERS
INCHES
DIM MIN
MIN
MAX
MAX
A 22.35 23.37 0.880 0.920
7.11
B
8.13 0.280 0.320
C
0.18
0.007
0.38 0.53 0.015 0.021
0
1.78 TYP
0.070 TYP
E
F
1.02 1.40 0.040 0.055
0.100 TYP
G
2.54 TYP
1.78 3.05 0.070 0.120
H
3.18
0.125
K
L
7.37
0.290
M
7.11
8.13 0.2BO 0.320
N 0.64 1.14 0.025 0.045
P 20.0 7 20.5 7 0.790 0.810
0.76
0.030
Y
Z 11.81 12.3 2 0.465 0.485
MECHANICAL DIMENSIONS
CERAMIC FLATPACK
10-PIN
"F" SUFFIX
NOTES:
1, LEADS ARE WITHIN 0.13(0.005)
RADIUS OF TRUE POSITION
(TP) AT MAXIMUM MATERIAL
CONDITION.
2.
~~~~S~~~~D~~~~~N~SL~
BODYLIE.
AND LEAD IRREGULARI·
TIES
r-";;;o",,,
8
C
D
025
F
0.0760.15300030.006
G
1.27
H 0.51
K 635
L 18.74
N 0.20
R
CERAMIC FLATPACK
14-PIN
"F" SUFFIX
'~
10 :4;
--+--! L!
f - - I
AT THE POINT OF EXIT OF THE
LEAD FROM THE BODY.
4.DIMENsION"R"APPLlESTOALL
FOUR CORNERS.
5. DIMENSION "G' IS THE BASIC
PIN SPACING BETWEEN CEN-
TER LINES IN TWELVE POSI·
TIONS.
11 - 11
0.050 Bse
0.020 0.040
0.250 0.370
0.738 1.000
0.008 0015
0.272
MILLIMETERS
DIM
A
8
C
D
F
F
G
I
H
K
L
N
R
S
NOTES:
1.LEADNO.1ISIDENTIFIEDBYTAB
ON LEAD OR DOT ON COVER.
2.DIMENSIONS 'A" AND 'J'Iill..OW
FOR OFF·CENTER LID, MENIS·
CUS, AND GLASS OVERRUN.
3.THE TRUE·POSITION PIN SPAC·
ING IS LOCATED WITHIN ~.005
INCH (0.127 mm).
4.DIMENSION 'H' SHALL BE MEAS·
URED AT THE POINT OF EXIT OF
THE LEAD FROM THE BODY.
S.DIMENSION 'G' EIGHTEEN
SPACES.
January 1990
1.02
9.40
25.4
0.38
6.91
DIMENSION "N' APPLIES TO
LEADS 1, 7, 8, AND 14.
3. DIMENSION "H' IS MEASURED
NOTES:
1.LEAD NO.1 IOENTIAED BY TAB
ON LEAD OR DOT ON COVER.
2.LEADS WITHIN O.13mm(O.005)
TOTAL OF TRUE POSITION AT
MAXIMUM MATERIAL CaNOl·
TION.
CERAMIC FLATPACK
20-PIN
"SF" SUFFIX
sse
AND GLASS OVERRUN
2.
K
CERAMIC FLATPACK
16-PIN
"F" SUFFIX
6
0238 0.252
1.70 0.057 0067
0.483 0.010 0.019
NOTES:
1. DIMENSION 'E" ALLOWS FOR
OFF·CENTER LID, MENISCUS
!r~-l~ ---l~~
8
INCHES
~DiIM~~aaE~M~'iNaM~A~X~
A
0.290
MIN
MAX
7.11
610
145
6.40
1.70
0048
6.91
0.08 015
1.27 SSC
051
1.02
6.35
9040
19.0 25.4
0.10
0.13
30"
9
0.25
MILLIMETERS
OIM
A
8
C
D
MAX
0.280
0.252
0.057 0.067
0010 0019
0277
0.003 0.006
0.050 sse
0.020 0.040
0.250 0.370
0.750 1.000
0.004
0.005
-
3
90
INCHES
MAX
6.27
1.65
10.16
0.400
6.63 0.247 0.261
1.91 0.065 0.075
0.38
0.08
18.97
N
0.20
1.27
0.51
6.35
0.48
MIN
493
1.14
0.25
6.92
010
MIN
MAX
0.15
0.015 0.019
0.003 0.006
1.02
9040
25.4
0.38
0.250 0370
0.747 1.000
0.008 0.015
esc
MILLIMETERS
F
G
H
J
K
L
0.240
MIN
F
G
H
K
L
DIM
A
8
C
D
E
INCHES
MIN
MAX
7.3.3
509
0.050
esc
0.020 0.040
INCHES
MIN
0.194
1.91 0.045
0.38 0.010
707 0272
0.15 0.004
MAX
0288
0200
0075
0.015
0.278
0006
0030 TYP
0.020 0025
534
0.210
674 738 0.265 0290
18.42 19.85 0724 0.780
076 TYP
050 0.64
-
II
MECHANICAL DIMENSIONS
CERAMIC FLAT
24-PIN
"F" SUFFIX
PACK
NOTES:
1. DIMENSION "L" SHALL BE
MEASURED AT THE POINT OF
EXIT OF THE LEAD FROM THE
BODY.
2. DIMENSION -0. ALLOWS FOR
OFF·CENTER LID, MENISCUS
AND GLASS OVERRUN.
3. THE BASIC PIN SPACING IS 0.050'
(1.27mm) BETWEEN
CENTERLINES. EACH PIN
CENTERLINE SHALL BE LOCATED
WITHIN +/-0.005 (O.13mm) OF ITS
EXACT LONGITUDINAL POSITION
RELATIVE TO PINS 1 AND 24.
4. DIMENSION 'P' APPLIES TO ALL
FOUR CORNERS (LEADS
NUMBER 3,10,15, AND 22).
5. DIMENSION 'R" APPLIES TO
LEADS NUMBER 2,11,14, AND 23.
6. DIMENSION '5" APPLIES TO
LEADS NUMBER 1,2, 11,12, 13,
14,23, AND 24.
CERAMIC LEAD LESS
CHIP CARRIER (LCC)
20-PIN
"L" SUFFIX
NOTES:
1. ALL EXPOSED METALLIZED AREA
SHALL BE GOLD PLATED 60
MICRO·INCH MINIMUM
THICKNESS OVER NICKEL
PLATED UNLESS OTHERWISE
SPECIFIED PURCHASE ORDER.
<>
METAL CAN
2-PIN
"Z" SUFFIX
~
r4S
~
C o OBO
0
E 6.27
G
1.27
J 0.200
K 6.3S0
L 0.510
P 0.130
R 0.100
30
S
-
ERS
MAX
1.900
0.480
0.150
11.18
6.63
SSC
0.380
9.400
1.020
90
MILLIMETERS
MIN
MAX
8.64
9.14
8.128
1 270 TYP
0635 TYP
1.02
1.52
L 1 626 2286
M
1.016 TYP
N 1372 1.68
P
1.168
1.91
2.41
0
R
0.203R
OIM
A
0
G
J
K
INCHES
MIN
MAX
0.065 0.075
0.015 0.019
0003 0.006
0.440
0.247 0.261
0.050 SSC
0.008 0.015
0.250 0.370
0020 0.040
O.OOS
0.004
30
90
INCHES
MIN
MAX
0.340 0.360
0320
0.050 TYP
0025 TYP
0.040 0.060
0064 0.090
0040 TYP
0054 0.066
0.046
0075 0095
O.OOBR
TO-46
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A 5.207 5.842 0.205 0.230
S 4521 4.953 0.178 0.195
C
2.667
0.105
0 0.406 0.533 0.016 0.021
0.381
0.015
E
G
2.54 SSC
0.100 sse
H 0.914 1.14 0.036 0.045
J 0.711 1.092 0.028 0.043
K 12.70
0.500
M
42
480
42°
48 0
P
1.143
0.04S
Q
1.27 TYP
0.050 TYP
R
0.381
0.015
-
-
METAL CAN
3-PIN
"Z" SUFFIX
TO-52
r-IIETERS
INCHES
MIN
MAX
0.205 0.230
0.178 0.195
0.160
0 0.406
0.016 0.021
0.015
E
G
2.54
0.100 SSC
0.036 0.045
H 0.914
J 0.711
0.028 0.043
K 12.70
0.500
420
480
420
480
M
1.143
0.045
P
Q
1.27 TYP
0.050 TYP
R
0.381
0.015
~
1+
S
C
.
5.842
4.953
4.064
0.533
0.381
SSC
1.143
1.092
-
January 1990
11 -12
-
MECHANICAL DIMENSIONS
METAL CAN
3-PIN
"T" SUFFIX
TO-39
TERS
MAX
9.40
851
4.70
0533
1.02
5.08 TYP
0.711 0.864
0.74
1.14
1270
INCHES
MIN
MAX
0.350 0.370
0.315 0335
0.165 0185
0.016 0021
0.040
0.200 TYP
0.028 0.034
0.029 0.045
0.500
45 TYP
45 TYP
254 TYP
0.100 TYP
1.143
0.045
90
TYP
90
0635
METAL CAN
3-TERMINAL
"K" SUFFIX
TO-3
l.-~::;;==~
ET
SEATING
PLANE
METAL CAN
3-TERMINAL
"R" SUFFIX
TYP
0.025
MILLIMETERS
INCHES
DIM MIN
MIN
MAX
MAX
A 2990 3040 1177 1197
B 1943 19.68 0765 0775
C 635 940 0250 0370
097 109 0038 0043
0
E 1 52 343 0060 0135
G 10 67 11.18 0.420_
H
521 572 0205 ~
0225
J 1664 1714 0.655 0675
K 10.16 12.70 0400 0500
Q
3.84 4.09 0.151 0161
S 1257 13.34 0495 0525
T 3.33R 47aR o 131R o lSBR
TO-66
MILLIMETERS
CAN
MAX
0.500
0.340
0.034
0.075
0.962
0.210
0.107
0.590
0.050
0.152
0.350
O.14SR
0.620
157b
U
HYBRID METAL
4-TERMINAL
"K" SUFFIX
INCHES
DIM MIN
MAX
MIN
B 11,94 1270 0.470
C 6.35 8.64 0250
0
0.71
086 0.028
E 1.27
1.91 0.050
F 24.33 24.43 0.958
G 4.83 5.33 0.190
H
2.36 2.72 0.093
J 1448 1499 0.570
K
9.14
0.360
P
1.27
Q
3.61 386 0142
S
8.89
T
3.68R
(SM)
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
A 19 . .30 19.81 0.760
8
1.52
1.65 0.060
C 6.350 11.4.3 0.250
0 10.80 12.06 0.425
E
5.21
5.72 0.205
F 10.67 11.18 0.420
G
H
J
K
3.680
10.0.3
. .396
L
M 1798
N .3007
P 0.970
January 1990
11 - 13
MAX
0.780
0.065
0.450
0475
0.225
0.440
4.190 0.145 0.165
10.29 0 . .395 0.405
.4.39 0.156 0.173
4 . .39R
0.173R
13. .34
0.525
18.49 0.708 0728
30.23 1184 1190
1.090 0.038 004.3
III
MECHANICAL DIMENSIONS
METAL CAN
4-PIN
"R" SUFFIX
(SM)
NOTES:
1. CASE IS ELECTRICALLY
ISOLATED.
2. LOADS MAY BE SOLDERED TO
WITHIN 1/16' OF BASE PROVIDED
TEMPERATURE·TIME EXPOSURE
IS LESS THAN 260 C FOR 10
SECONDS.
COMMON (2)
MILLIMETERS
MIN
MAX
11.94 12.70
6.350 B.6j6
0.711 0.864
1.270 1.905
24.13 24.64
G
5.0B TYP
H 14.48 14.99
K 9.398 9.906
Q 3.607 3.861
S
B.89R
T
3.68R
U
15.75
DIM
B
C
0
E
INCHES
MIN
MAX
0.470 0.500
0.2!::l0 0.340
0.028 0.034
0.050 0.075
0.950 0.970
0,200 TYP
0.570 0.590
0.370 0.390
0.142 0.152
.350R
-
O.14SR
0.620
OUTPUT (1)
METAL CAN
5-PIN
"R" SUFFIX
TO-66
MILLIMETERS
DIM
MIN
MAX
INCHES
MIN
MAX
B
11.94 12.700.4700500
C
D
E
6 35 8 64
0.71 0.86
1.27 1.90
24.33 24.43
F
G
H
K
P
Q
0.250
0.028
0.050
0.958
0.340
0.034
0075
0.962
720 TYP
720 TYP
14.48 14.99 0.570 0.590
9.14
0.360
1.27
3.61
3.86 0.142
4.11R
8.89R
3.6BR
1575
METAL CAN
8-PIN
"T" SUFFIX
TO-99
LF~Bj
~~
C
-.--
T
SEATINC
TTPLANE
E
P
K
'-I~
~
t+B 87.
C
0
E
F
G
H
J
K
M
N
~
-H-- 0
P
METAL CAN
9-PIN'
"R" SUFFIX
4.191
0.406
2.54
5.08
0.711
0.737
12.70
45°
3.556
0.254
INCHES
MIN
MAX
9.398 0.335 0.370
8.509 0 306 0.335
4.699 0.165 0185
0.533 0.016 0.021
1.016
0.040
TYP
0.100 TYP
0.200 TYP
TYP
0.864 0.028 0.034
1.14 0.029 0.045
14.48 0.500 0.570
45° TYP
TYP
4.064 0.140 0160
1.016 0010 0.040
TO-66
MILLIMETERS
MIN
MAX
11.94 1270
6.35 8.636
0.711 0.863
1.270 1.905
2433 24.43
4.826 5334
1447 14.99
2.362 2.718
9.14
36 TYP
1.270
Q 3.607 3.861
R
4.11R
S
8.89R
T
.683R
U
15.75
DIM
B
C
0
E
F
G
H
J
K
L
P
-
Q
January 1990
11 - 14
INCHES
MAX
MIN
0.470 0.500
0250 0.340
0.028 0.034
0.050 0.075
0.958 0.962
0.190 0.210
0.570 0.590
0.093 0.107
0.360
36 TYP
0.0
0142.
MECHANICAL DIMENSIONS
METAL CAN
10-PIN
"T" SUFFIX
TO-100
ES
MAX
0370
D.335
0.185
0021
0.040
D
E
G
H
J
K
M
0.230 TYP
0028 0.034
0029 0.045
0500 0570
36 TYP
0140 0160
0.010 0.040
10-""::=""'>-::'1f'7\/-r
METAL CAN
10-PIN
"T" SUFFIX
TO-96 (TALL)
DIM
A
B
C
D
E
G
H
J
K
M
N
p
METAL CAN
12-PIN
"T" SUFFIX
MILLIMETERS
MAX
MIN
B.a90 9.398
8001 8509
6.604
6.096
0.406 0.533
-
INCHES
MIN
0.350
0315
0.240
0016
1.106
MAX
0.370
0.335
0260
0.021
0.040
5842 TYP
0230 TYP
0711 8.636 0.028 0.034
0737
12.70
36°
3.556
0254
1.143 0.029 0045
14.48 0.500 0.570
TYP
36° TYP
4064 0.140 0160
1.016 00100040
TO-101
.L
-,E
INCHES
DIM
MIN
A
B
MAX
0335 0.370
0.315 0.335
C 4.191 4.6
0.165 0185
o 0406 0.5 0.016 0.021
E
1.016
0.040
G
5.842 TYP
0.230 ryp
H 0.711 0.864 0 028 a 034
J 0.737 1.143 00290.045
K 12.70 14480.500 0570
M
300 TYP
300 TYP
N 3.556 4064 0.140 0.160
P
HERMETIC TO-257
3-PIN ISOLATED
"IG" SUFFIX
3-PIN
"G" SUFFIX
0254 1.016 00100040
F (DIA)
.-~ 16.64
~
MAl
~
Z (RAO)
B
C
D
E
F
G
K
N
R
S
U
V
Z
January 1990
11 -15
.
4.70
071
10 41
3.56
2.54
1270
5.08
2.92
0.89
2.87
5.13
1.40
INCHES
MIN
MAX
0.645 0.655
10.67 0.410 0420
4.95 0.185 0.195
0.81 0.028 0.032
10.67 0.410 0.420
3.81 0140 0.150
TYP
0.100 TYP
0500
TYP
0.200 TYP
3.18 0115 0.125
1.43 0.035 0.045
3.12 0113 0.123
5.38 0.202 0.212
TYP
0055 TYP
II
11 - 16
THUMB INDEX
SILICON
GENERAL
.1
TABLE OF CONTENTS
III
III
III
GENERAL
81
MOTION CONTROL CIIRCUITS
III
POWER DRIVER AND ~INlTIERfACIE C~RCU~TS
.1
III
Ell
III
III
I
III
PART NUMBER INFORMATION
~NfORMATION
POWER SUIPPlV C~IRCIUl~TS
OPERATION AMPUflERS AND COMPARATORS
CORle MEMORY CIRCUITS
AUTOMOT~VE
CIRCUITS
OTHER CIRCUITS
PACKAGE INFORMATION
APPLICATION INFORMATION
SALES OFFICES
12 -1
I
I
I
I
I
I
I
I
I
I
I
I
I
•
SELECTION GUIDE
APPLICATION NOTES
SILICON
GENERAL
LINEAR INTEGRATED CIRCUITS
Device Type
Ref. No.
Page No,
Title
8131401
M-1
- The SG1401 Video Amplifier
12-3
8131402
M-2
- SG1402 Wideband Amplifier./Multiplier
12-7
8G1501A
PS-1
- SG1501A Dual- Polarity Tracking Regulators
12 -13
8131524
PS-2
PS-3
PS-4
- Simplifying Converter Design with a New Integrated Regulating Pulse
Width Modulator
- Deadband with the SG1524 Regulating Pulse Width Modulator
- Improving Switching Regulator Dynamic Response
12-19
12 - 27
12-29
8G1524B
PS-5
PS-6
- Converting 1524 Switching Power Supply Designs to the SG1524B
- A New. Versatile P.W.M. Control Circuit for Switching Power Supplies
12 - 35
12 - 41
8G1525A
PS-7
- Synchronizing the SG1525A PWM
12-47
8131526
PS-8
PS-9
- Digital Current Limiting Techniques for Switching Power Supplies
- FET Enhanced Switched - Mode Design
12 - 49
12-59
8G1525A,8G1526,
813 1527A
PS-10
- Power Supply Circuits Head for Simplicity by Integration
12-63
8131825
PS-11
- SG1825 Design Brief: A 200KHz Current Mode Supply
12-75
813184218131843,
8131844/8131845
PS-1.2
- A Current Mode I.C. Optimized for Single Ended Converters
12-77
8131542, 8131543,
8131544,8133523
PS-13
- Output Supervisory Circuits: A New Family of Power Supply Control Devices
12 - 83
8131548
PS-14
- A Conceptually New Quad Power Fault Monitor Circuit
12 - 91
8131549
PS-15
- Protect Your Switchers with Digital Current Limiting
12 -101
SG1540
PS-16
- Minimizing the Cost and Complexity of Start:Up Circuits for Switching
Power Supplies
12 -105
8133626, 800644
PD-1
- Using the SG3626/SG3644 FET Drivers in the 16 - Pin S.O.I.C. Package
12 -113
8131627, SG1629
PD-2
- Power Switch Drivers: New IC Interface Building Blocks for Switched - Mode
Converters
12 -115
8133635
MC-1
- Use Motor - Drive IC to 80lve Tricky Design Problems
12 -123
8131731
MC-2
MC-3
- Simplified High - Efficiency Motor Drive Systems with New PWM Integrated Circuits
- Simplify Feedback Controllers with a 2 - Quadrant PWM IC
12 -129
12-135
,
January 1990
12-2
APPLICATION NOTES - SG1401
SILICON
GENERAL
M-l
LINEAR INTEGRATED CIRCUITS
THE SG1401 VIDEO AMPLIFIER
ABSTRACT
The SG1401-SG3401 has been designed to provide maximum versatility as a general-purpose, singleended amplifier. With its broad frequency capability, this circuit will be useful in a wide range of
applications provided that the usual considerations for high frequency circuit designs are observed. The
following information is presented toward aiding in the optimization ofthe many possible configurations
of this device.
FIXED GAIN
In the circuit configurations shown in Figure 1, the overall voltage
gain is approximated by resistors R1 and the parallel combination
of R2 and R3, as
R
RR
Av -1+ - ' ,where R = _2_"_
R
R2 + R"
With no external connections, the voltage gain is determined
solely by R1 and R2 and is 1Yo or 3 dB. Decreasing the effective
value of R2 by capacitively coupling a lower resistor in parallel,
raises the gain. Four fixed gain settings are provided internal to
the circuit; however, any other setting within the maximum gain of
the amplifier is possible with external resistors as shown in Figure
2.
30
..........
+VS
25
m
~
I
z
:;;;:
'-'
w
'-'
«
>---'
0
20
"\
,
~
15
\,
10
>
5
0
10
GND
100
'"
1K
.......
-
10K
EXTERNAL PARALLEL RESISTOR-(O)
Figure 2. External Gain Control
Figure 1.
January 1990
12 - 3
APPLICATION NOTES - SG1401
The value of the coupling capacitor, CFis determined by the low
frequency response desired, as its capacitive reactance will add
to the value of the resistance it couples. Therefore, the lower
cutoff frequency will be
~
DIODE
f-c
6K
~
VOUT
R1
1,2K
f _ _l _
-11~
2nRaCF
c
+Vs
CIN
Utilizing the internal 90 or 460 ohm resistors for higher gain
settings provides the added advantage of maximum temperature
stability since the close tracking of adjacent diffused resistors
keeps their ratio constant. Typical temperature variation of this
circuit is shown below:
F,B~ILA,G,C,
~~
:: + CD
CF
2.4K
GND
Figure 4.
30
30
PI~
25
rn
'0
'(
z
r-
E TI AC rOUND
-
rn
'0
'(
z
JETLJ
20
w
'-'
'«
r-'
0
I ""
20
V
«
'-'
:«
'-'
..".
25
w
'-'
«
r-
15
-'
0
/
10
>
PIN E TO PIN F
10
15
>
--'"
5
5
PIN E OPEN
0
1.1
1.0
0
-50 -25
0
25
50
/
75 100 125
1.2
PIN H DRIVEN FROM
A VOLTAGE SOURCE
1.3
1.4
1.5
AGC VOLTAGE-(V)
AMBIENT TEMPERATURE -( °C)
Figure 5. Gain vs. AGC Diode Voltage
Figure 3. Temperature Stability
30
VARIABLE GAIN
Since the dynamic impedance of a forward-biased diode is
inversely proportional to the current through it, a convenient gain
control can be achieved by using a pair of diodes as a variable
impedance. In the circuit of Figure 4, R3 has been replaced by two
diodes whose impedances act in parallel due to the decoupling of
Co' If the diodes are driven from a voltage source, a logarithim
relationship between gain and control Signal is achieved (see
Figure 5); while if a current source is used, the relationship is linear
as shown in Figure 6.
25
rn
'0
'(
z
20
:«
'-'
w
'-'
«
r-
-'
0
15
V
10
>
./
5
There are two limitations on this form of gain control. First, the
diodes' capacitance limits their effectiveness to frequencies below 20MHz and, secondly, the signal voltage across the diodes
should be held to less than 50 mV RMS to minimize selfmodulation of amplifier gain. Additionally, the AGC current should
be limited to 3mA maximum to keep the diodes out of saturation.
/
J
L
V
PIN H DRIVEN FROM
A ICURRENT TOURCE
"
0
0
1
10
100
lK
AGC CURRENT-GuA)
Figure 6. Gain vs. AGC Diode Current
12 - 4
10K
APPLICATION NOTES - SG1401
HIGH FREQUENCY STABILITY
With the capability of operation at 1OOMHz, the SG1401-SG3401
also has some susceptibility to external stray reactances; however, with reasonable care, complete stability may be assured.
Some general precautions which should be considered include
the following:
1. Power supply decoupling close to the circuit terminals
(a 0.1 !IF capacitor is usually adequate).
2. Maintain separation of input and output lines.
3. Minimize load capacitance or insert a series resistor
(up to 50 ohms) in the output.
4. Purposely limitthe high frequency response with a stabilizing capacitor Cs between pins 3 and 4.
30
PIN E Ti AC
25
m
"
'I
z
20
"w
"
15
«
-0:
f...J
0
PIN E Ti AC
,
25
m
"
'I
PIN E
20
J
5
Cs=O
«
"w
"
...J
0
10
>
5
/
PIN E OPEN
50
u...
u...
30
f-
0
::::>
20
r
u
z
10
.3
1.0
3.0
10
30
w
::::>
a
100
w
0::
u...
5
0::
3
n.
n.
2
w
::::>
~
0
~~
f=
~
f-
FREQUENCY-(MHz)
300
I
II~
-
-
"'"
PIN E COUPLED TO PIN G
I IIII
111
.5
IIII
I
"'" '""-
r-
1
300
100
30
Figure 8. Frequency Response
I
//
/
PIN E TO PIN F
10
3.0
FREQUENCY-(MHz)
2-
j,
-0:
f-
1.0
u
15
\1\
~ ~r\
V
r"~
PIN E 0 EN
.3
I
z
\
0
N
\
PIN G
'\
..........
CS='4.7PF
\
PIN G
PIN E TO PIN F
10
100
GROUN~
J
>
Since the gain of this circuit is reduced by increasing the amount
of feedback, the potential for instability is greatest when the gain
is at its minimum value. This characteristic and the stabilizing
effects of a 4.7 pF capacitor between pins 4 and 3 are illustrated
in the frequency response curves presented in Figure 5 and 8.
The relationship between the value of Cs and the upper cutoff
frequency of a 20dB gain setting is shown in Figure 9 below.
30
PIN E
GROUN~ "
2
3
5
10
=
=
~
I
-
IIII
20 30 50
C S BETWEEN PINS C AND E -(PF)
Figure 7. Frequency Response
Figure 9. Upper Cutoff Frequency vs. CsValue
12-5
100
12 - 6
APPLICATION NOTES - SG1402
SILICON
GENERAL
M-2
LINEAR INTEGRATED CIRCUITS
SG1402 WIDEBAND AMPLIFIER/MULTIPLIER
INTRODUCTION
Rapid advances in the state-of-the-art of processing monolithic
linear integrated circuits have made the use of tightly matched
components a practical reality. This in turn has opened the doors
to a new class of circuit characterized by its utility, versatility, and
ease of application. It is now possible to include on a monolithic
chip, many of the components which, because of relatively poor
tolerances, were formerly required to be external to the circuit.
The SG1402, shown schematically in Figure 1, illustrates this
capability both by its inclusion of all necessary biasing networks
and by the nature ofthe circuit itselfwhich requires extremely well
matched co'mponent parameters for successful operation.
the way in which the above diff amps are cross-coupled will show
that while the collector load resistors receive a portion of their
currentfrom each diff amp, the signals will arrive out of phase with
respect to each other. This is because the input voltage, V c ' is
amplified common emitter-with 1800phase shift-through 09and
summed at resistor R7 with the signal which has gone common
collector-common base - with 00 phase shift - through 07 and 05.
Therefore, with the circuit perfectly balanced, the two signals
completely cancel out and the output has zero Signal. This can be
shown mathematically as follows:
Vs
Figure 1. SG1402 Schematic Diagram
Figure 2. Simplified Schematic of the Multiplier Section of the SG1402
HOW IT WORKS
The heart of the SG 1402 is a four quadrant multiplier consisting
of two cross-coupled differential amplifiers which are jOintly controlled by a third differential amplifier. This part of the circuit is
shown in simplified form as Figure 2. The constant current, 10' is
divided by 06 and 010 and divided again by each of the upper diff
amps such that, for balanced operation, transistors 05, 07, 09,
and 012 each have % 10 flowing through them. An examination of
The collector current in one side of a simple differential amplifier
(05 and 07, for example) is:
January 1990
12 - 7
III
APPLICATION NOTES - SG1402
where:
IE.
..IT.
q
= sum of currents in each collector
>
">
= 26 mV at 25°C
V c = different input voltage
20
"~\
z
This equation can be differentiated to obtain the transconductance which, for small values of V c ' is:
10
0
w
0
In a similar manner, the transconductance through 09 is:
z
w
I
w
dic.
qlE.
gm = dvc = 4kT
Vi
o
Av= R dic. + dic.
L dvc
dvc
I
I
I
I
GAI~
FJ J E R L J
MULTIPLY BY 2
-120
-SO
-40
.
ooc
PHASE SHIFT
+40
+SO
/
o
DIFFERENTIAL CONTROL VOLTAGE -
R
= ~ (IE' - IE.)
+120
mV
Figure 3. Differential Gain Control
Since IE. + IE. = 10 , it can be seen that when Vm = 0, IE.= IE. = 'hI:,
and Av = 0. With IE. and IE. being collector currents of another
differential amplifier, the total small-signal gain equation may be
written:
~
/
\
.J
'-'
Z
and the total voltage gain, Av is:
J
180° C PHASE SHIFT
5
~
I
\
w
'-'
0
dic.
qlE.
gm = dvc = 4kT
15
/
J
Av- RL 10 q '1
1
- Vc - 4kT 0+exp(k~)VM 1+eXp (_::.r)VM
+2
>
I
w
+1
'-'
«
I.J
The circuit gain of the SG1402 is less than that predicted by the
above equation due to the local feedback offered by the 200hm
emitter resistors. The actual relationship between Av and VMis
shown in Figure 3 while Figure 4 graphs the full four-quadrant
transfer function between the input voltage, V c' the control voltage, VM ' and the output voltage. Note that the 200hm emitter
resistors provide linearity for ±60 millivolts of input voltage while
the modulating voltage is only linear for approximately half that
value. It should be recognized from Figure 4 that output limiting
occurs at a constant input voltage regardless of the modulating
voltage. In other words, reducing the gain reduces the maximum
peak-to-peak output swing.
0
>
.J
0
«
F
z
W
0::
w
""is
-1
-2
-120
- SO
-40
o
+40
+SO
DIFFERENTIAL INPUT VOLTAGE -
+120
mV
Figure 4. Multiplier Transfer Function
BIASING CIRCUITRY
Key to the utility of the SG1402 is the inclusion of all the biasing
and level shifting circuitry normally required as external components. This is provided by matched current sources and low
impedance voltage sources.
Resistors R1, R2, R3 and R4 are directly across the supply
voltage and establish a current:
Vs - V.EO •
I. = R1+R2+R3+R4 =1mAat10volts
Transistors 014 and 016 have the same geometries and emitter
resistors as 01 and therefore, with the same base voltage, they
each are also conducting one milliamp and provide the loads for
the output emitter followers, 013 and 015. This saves chip area
as a transistor requires less space than a resistor which would
establish the same current.
Transistor 08 has four times the emitter area and Yo the emitter
resistor as 01 and thus defines a current level 10 of 4 milliamps.
The bias voltage levels required at different pOints in the circuit are
all defined by the same resistors which set the current levels but
12 - 8
APPLICATION NOTES - SG1402
~ +r
...L,--4~ : ~~c=-----o
there is no mutual interaction due to the insertion of a2 and a3
which act as low-impedance isolators.
,0.1
Transistors a4 and all serve only as common-base stages to
isolate the load resistor from the collector capacitance of the
parallel diff-amp transistors. Thus, frequency response is improved with only slight increase in circuit complexity.
r
II
CONTROL
VOLTAGE
a
IN914
-=-
o--~f---------1
to 5V
,---
I
+eOUT
,H;..>"--_ _-o-
J.........
eOUT
y~
100K
BAL
ADJ
VARIABLE GAIN AMPLIFICATION
The circuit of Figure 5 shows the simplest application of the
SG1402 as a single-ended, variable-gain amplifier. The signals
at the two outputs are always equal in magnitude and opposite in
phase. As the gain control potentiometer is moved from one end
to the other, each output will start with a maximum signal, reduce
to a minimum when the pot is centered, and increase to maximum
again in the opposite phase as the wiper gets to the other end of
the potentiometer.
Figure 6. Addition of Diode Provides Gain Control Without
Phase Change. Balance May Be Eliminated if Maximum
Attentuation is not Required.
30
rn
20
\
"0
I
Z
«
10
(!)
W
(!)
«
+eOUT
f-
...J
-eOUT
0
0
>
w
>
«
-10
F
...J
10K
w
~
-20
"-
10K GAIN
CONTROL
=i= 0.1
-30 L-~-L~~__L-~-L~~~
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
10K
DC CONTROL VOLTAGE-(V)
Figure 7. Gain Variation as a Function of Control
Voltage with Diode Coupled Input.
Figure 5. Single· Ended Variable-Gain Amplifier Configuration with
Manual Contralto provide Maximum Output of Either Phase.
For applications where a phase change is not desired, the
incorporation of a diode as shown in Figure 6 will allow a DC
control voltage to vary the input-output transfer function from a
gain of +25dB to an attenuation of -25dB. This relationship is
plotted in the graph of Figure 7.
Since this change in transfer function is accomplished with no net
change in either operating currents or bias levels, it is transientfree and extremely fast-reacting. Thus, the circuit of Figure 6 may
also be used as a gated amplifier with the control requirements
compatible with 0 to 5 volt logic levels. The waveform in Figure 8
shows a 1MHz signal controlled with a 10 microsecond pulse.
Figure 8. Gate Amplifier or Pulse Modulator Response.
Input is 10 mVrms, 1 MHz and Control Voltage is
to 5 Volt Square Wave with f = 50 kHz.
o
12 - 9
•
APPLICATION NOTES - SG1402
MODULATION
The multiplying function of the SG1402 can be used to provide
both balanced and amplitude modulation utilizing the basic circuit
shown in Figure 9. With the potentiometer adjusted for optimum
balance, the carrier signal is balanced out producing a doublesideband waveform atthe output. Depending on the amplitude of
the carrier signal, higher frequency harmonics can also be generated; however, if only the lower sideband is used, filtering of the
upper sideband will also eliminate all the harmonics. It should be
noted that this balanced modulation is achieved without the need
for the usual transformers and only capacitive coupling is required. Typical waveforms are shown in Figure 10.
Figure 11. Amplitude Modulator Output Waveform.
(0.2V/cm, 50 l'5/div, fc=1 MHz, f.=10 KHz)
+10V
D"
·c ~
5'~,D.,
By using a signal to modulate itself with the circuit shown in Figure
12, the input is squared and since
(carrier)
""":----0 -I Cs
(modulated
~D.,
(n':'odulaUan)
51
•
1
.;:..-"'-----0 signal)
cos2 rot = % (1 + cos 2rot)
the outputfrequency is twice that ofthe input. Typical waveforms
for this frequency doubler application are shown in Figure 13.
lOOK
SAL
ADJ
+10V
0.1
Figure 9. Balanced Modulator
lOOK
+----'?BAL
ADJ
Figure
1~.
Frequency Doubler
Figure 10. Balanced Modulator Output Waveform.
(O.W/cm, 50 l'5/cm, fc=1 MHz, f.=1 0 KHz)
If the potentiometer is adjusted so that the 'circuit is unbalanced,
then the carrier is included in the output signal and amplitude
modulation as shown in Figure 11 results. The optimum adjustment can most readily be made while observing the output
waveform on an oscilloscope. Care should be taken that neither
signal overdrive the circuit.
Figure 13. Frequency Doubler Input and Output Waveform.
(50mV/cm, 0.2I's/div, f, = 1 MHz, f, = 2 MHz)
12 -10
APPL][CAT][ON NOTES - SG1402
DEMODULATORS
The same features which make the SG1402 an excellent modulator provide superior performance when the circuit is used as a
single or double sideband demodulator. The circuit of Figure 14
illustrates the simplicity of this application. The balance pot is not
necessary since the inserted carrier is eliminated by the low-pass
filter at the output.
'm
(modulot,on)
~---T-----;v.----.---<>
Figure 14. Balanced Demodulatoor
The same general approach may be used for amplitude modulation and a block diagram of a simple AM detector is shown in
Figure 15. Thus, the SG1402 can be used in receivers which
combine SSB and AM to provide complete signal transformation
in either mode of operation.
Figure 15. AM Detector Block Diagram
CONCLUSIONS
With the introduction ofthe SG1402, Silicon General has provided
a powerful tool to the communications engineer and all others
working with information processing. Because of its versatility
and capability, this device opens the way to a much greater
utilization of carrier transmission schemes for data handling in
applications ranging from outer space to home kitchens.
12 - 11
12-12
4
APPLICATION NOTES - SG1501A
SILICON
GENERAL
PS-l
LINEAR INTEGRATED CIRCUITS
SG1501A DUAL - POLARITY TRACKING REGULATORS
CIRCUIT OPERATION
DESIGNER'S CHOICE
The first IC to combine a positive and negative voltage regulator
on a single chip was the SG1501, and this device has since been
supplemented with three new tracking regulator designs - the
SG1502, the SG1501A, and the SG1568.
With four IC's to choose from some discussion of the significant
features of each type is in order. Three of the devices, the
SG1501A, the SG1501 and the SG1568 are factory set at ±15V
regulators while the fourth, the SG1502, is user-adjusted to
provide outputs from ±8V to ±28V.
All four of these tracking regulators operate in a similar manner
which is best visualized through the block diagram shown in
Figure 1. This circuit is fundamentally a tracking regulator. That
is, the negative voltage is regulated and the positive output tracks
the negative. (Note: In the SG1568, the circuit is reversed in that
the negative side tracks the regulated positive output; however,
the principle is the same.) Negative regulation is accomplished by
providing a constant-voltage reference for the negative error
amplifier, but the reference input to the positive error amplifier is
grounded. This amplifierforces its other input, which isthe centertap between equal resistors, to also be at zero volts, thus requiring the positive output to be equal in magnitude but opposite in
polarity to the negative output.
POSITIVE OUTPUT
"
"
GROUND
NEGATIVE OUTPUT
Figure 1. Block Diagram
With this technique, a single adjustment of the negative voltage
divider - which changes the negative output level- will also provide
exactly the same change to the positive output voltage. This
tracking will hold all the way from approximately one volt above the
reference voltage to a maximum value of about two volts less than
the input supply voltage.
The SG1501 and the SG 1501 A are interchangeable and both can
be used by themselves to provide load currents to the maximum
defined by package dissipation, or can be combined with external
pass transistors for currents in excess of two amps. Both devices
feature constant current limiting with the value set by external
resistor. The SG1568 is similar in all respects to the SG1501
except that it is frequency compensated in a slightly different way.
The SG1502 uses the same basic circuit as the SG1501 but has
two important differences. First, the voltage selting resistors are
external to the device providing greater flexibility in adjusting the
output voltage levels to other than ±15V. Secondly, the current
limit circuitry has been changed to allow its use in a fold back
mode. Foldback current limiting provides for a short circuit current
value less than the maximum load current and is a significant
feature when the major power dissipation is in external pass
transistors rather than the IC.
Self-contained thermal shutdown is the primary improvement
offered by the SG1501 A although increases in both the maximum
input voltage and load current have also been made. With thermal
shutdown, temperature sensing circuitry on the chip is deSigned
to turn off the output current when the junction temperature
exceeds a safe limit - typically 170°C. The significance of this
feature is that the designer now need not design around shortcircuit power dissipation limits - the device will take care of itself.
Since short-circuit power is typically more than twice as much as
maximum operating power, this means a two-times, or belter,
improvement in load current is possible. It should be noted that
even with thermal limiting circuitry, the maximum current must be
controlled to allow time for this protection to react.
January 1990
12 -13
•
APPLICATION NOTES - SG1501A
APPLICATIONS
The simplest way to use SG1501 and the SG1501 A is in the basic
circuit shown in Figure 2. In this form, the device will handle 50 to
100mA, depending on the heat sinking (more aboutthis later) and
will provide ±15V outputs with typically less than two millivolts of
sensitivity to either line or load variations. Because of this
excellent line regulation, there is no need for symmetrical input
supply voltage levels. The only requirement is that each level be
greater than its associated output and that the total voltage
between positive and negative supplies be less than 60V (70V for
the SG1501A). The minimum input voltage is defined by the
regulator dropout characteristics shown in Figure 3.
Figure 4. Artificial Ground for use with an
Ungrounded or Single Level Voltage
~~~~VE _ _
RSC
+-_---,
r-'IIIM--~--+--+---,r-- +15V
c,
CURRENT LIMITING
.0'
IVIN
Out
Sense
Stabl Bal
L'-__ l'Q.sJ..T~ ___ J Adj
GROUND
GND
GROUND
Volt
Adj
C2
.0'
'-VI~--+---------<~ -15V
Current sensing is provided by transistors 012 and 013 (see
schematic, Figure 5) which are normally held off by an external
base-to-emitter resistor, Rsc. When the load current passing
through this resistor develops enough voltage, the transistor turns
on and diverts drive current away from the series pass transistors .
The sense voltage is equal to approximately 0.6V at Tj =25°C, but
Figure 2. Basic ±15V, 50 mA Regulator
>
I
....J
...:
5
TA = 25°C
Rse = 0
F
zw
0::
w
4
I-*J:!~-+--=F--I-o_.
lL.
lL.
(5
f-
=>
go
3
=>
~
o
I
2
=>
0.
Z
o
~
-V
POSITIVE REGULA TO!,...
f-
a
Figure 5. SG1501A Schematic Diagram
it is temperature dependent decreasing to 0.4V at 125°C as
shown in Figure 6. Note that it is junction temperature that
determines the sense level, and thus increasing the power dissipation within the circuit can lower the value at which limiting will
occur. The value of the limiting resistor, Rsc, should be selected
by:
NEGATIVE rGULATOR
25
50
LOAD CURRENT
75
100
mA
R
sc
Figure 3. Regulator Dropout Voltage
When operating from a single voltage source, an ungrounded
supply is required. An artificial ground can be provided as shown
in Figure 4. In this circuit, the extemal transistors will conduct as
necessary to accommodate unbalanced load requirements and
while the outputs will float between the two input levels, they will
be held constant with respect to this artificial ground.
Sense Voltage at Maximum Tj
= Allowable Short Circuit Current
where, for maximum regulation, the allowable short circuit current
should be at least 20% more than the maximum expected load
current.
12 -14
A1?Jl>LJICATJION NOTES - SG1501A
The thermal resistance is the resistance to heat flow from the
junction to the ultimate heat sink. For parts mounted in the open,
still air, the thermal resistance (SjA) is equal to 185°C/watt for the
TO-100 metal can and 125°C/watt for the TO-116 ceramic DIP.
Blowing air across the package, or the use of some form of heat
radiator can significantly reduce these numbers. For example,
the use of IERC's model TXBF-032-025B top hat radiator on the
TO-100 package, reduces SjA to 130°C/watt, while their model
LlC-2144-2B radiator for the TO-116 will give an SjA of 50°C watt
for that package. Finally, a perfect heat sink reduces SjA to SjC
which is 50°C/watt for the TO-1 00 and 20°C/watt for the TO-116.
1000
>
E
800
w
G
w
(/)
400
iltGu
(I
z
w
ro;"' .................
(/)
200
SENSE VOL
CURRENT LIMIT =
0
I
-50 -25
I
I
0
25
~AGE
With the above information, the maximum power handling capability of the package can be determined as follows:
I RSC I
50
75
100 125
1.
Calculate the maximum allowable junction temperature
rise:
t.Tj = 150°C - TA (max)
2.
Calculate the power availability:
JUNCTION TEMPERATURE _DC
Figure 6. Current Limiting Characteristics
Under some conditions, a low-level oscillation may be present on
the negative side when the device goes into current limiting.
Should this be a problem, it may be eliminated by by-passing Rsc
with a capacitor whose value is such that the time constant, Rsc
C, is equal to 10 x 10.6 second. This capacitor, as well as the
output capacitors, C3 and C4, must be low ESR types such as
solid tantalum.
Pd = DTj /6jA
3.
From this number, subtract the maximum standby dissipation:
Psb = (V + max)(lsb+) + (V - max)(lsb-)
4.
The remainder can be used to determine the maximum
load current as a function of input-output voltage differential.
POWER CONSIDERATIONS
Although these dual regulators are designed to handle large load
currents and high input voltages, the product of the two can easily
exceed the maximum total device dissipation allowed by the
package. Thefunctionallimitation which should be considered for
each application is that for maximum reliability the junction temperature of the chip should not exceed 170°C. This is usually
derated to give a maximum design operating Tj of 150°C.
The curves of Figure 7 show these relationships for each package
under the assumptions of 25°C ambient, and symmetrical input
and output voltages and load currents.
(/)
w
g
(/)
100
TA
a
To evaluate the maximum junction temperature possible in a
given application, the following three parameters must be known:
1. The power dissipation within the chip
2. The thermal resistance from junction to ambient (or heat
sink)
3. The ambient (or heat sink) temperature
m
R2
20
\.
'\
Rt. =RESISTANCE FROM PIN 9 TO GROUND
0
10
100
lK
NEGATIVE
OUTPUTS
Figure 8. Error Amplifier Connections
"-
Cl
0
5K
For example, the soft start circuit of Figure 9 can be used to hold
Pin 9 to ground - and thus both outputs off - when power is first
applied. As the capaCitor charges, the output pulse slowly
increases from zero to the point where the feedback loop takes
control. The diode then isolates this turn-on circuit from whatever
frequency stabilizing network might also be connected to Pin 9.
""\I\.
Rt.-'"
RL -300Kfl
I
Cl
VREF
5K
Since this amplifier is a transconductance design, the output is a
very high impedance (approximately 5MQ) and can source or sink
only 100~. This makes the output terminal (Pin 9) a very
convenient place to insert any programming signal which is to
override the error amplifier. Internal shutdown and current limit
circuits are connected here, but any other circuit which can sink
100llA can pull this point to ground, thereby shutting off both
outputs.
Figure 6. SG1524 Error Amplifier Schematic
m
OUTPUTS
GND
INVERTING
INPUT
;:::,
POSITIVE
R2
10K
lOOK
\.
1M
FREQUENCY-(Hz)
"
10M
Figure 7. SG1524 Error Amp Frequency Esponse
Figure 9. SG1524 Soft Start Circuitry
12-21
•
APPLICATION NOTES - SG1524
CURRENT LIMITING
The current limiting circuit, while shown in the block diagram as op
amp, is really only a single transistor amplifier as shown in Figure
10. It is frequency compensated and has a second transistor to
provide temperature compensation and a reduction of input
threshold to 200mV. When this threshold is exceeded, the
amplifying transistor turns on and, by pulling the output ofthe error
amplifier toward ground, linearly decreases the output pulse
width.
R2
~~~----~----~--~--~------~--~GROUND
Figure 12. SG1524 Over Voltage Protection
OUTPUT STAGES
The outputs ofthe SG1524 are two identical NPN transistors with
both collectors and emitters uncommitted. These circuits are as
shown in Figure 13 and include an antisaturation network for fast
response and current limiting set for a output current of approximately 100mA.
Figure 10. SG1524 Current Limiting
One consideration in using thi's circuit is that the sense terminals
have a ± 0.3 volt common mode range which requires sensing in
the ground line. However, since differential inputs are available,
fold back current limiting can be implemented as shown in Figure
11.
C 12@
FIF
CLOCK--+-I(;
COMP
+
CURRENT _
LIMIT
SENSE
+
J-__-=============::~~E~11 ~
Figure 13. SG1524 Output Stage
+
The availability of both collectors and emitters allows a maximum
versatility to enable driving either NPN or PNP external transistors; however, it must be remembered that this is only a switch
which closes and opens. Power transistor turn-off drive must be
developed externally. Some suggestions for output drive circuits
are shown in Figure 14.
Figure 11. Foldback Current Limiting
While on the subject of protection circuitry, although overvoltage
protection is not built into the SG1524, it is relatively easy to add
by using the internal shutdown circuit in conjunction with a few
external components as shown in Figure 12.
This circuit will provide a low level sensing and latching function
and while it won't protect against a shorted outpultransistor, it will
remove the drive signals with no power dissipation.
APPLICATIONS
In considering applications for the SG1524, it appears that there
are three general classifications of switching power supply systems. Included in the first are the transformerless voltage multiplier circuits shown in Figure 15. These circuits are primarily used
for low level applications but can step up, step down, or change
the polarity of an input voltage. The switches shown can be either
12-22
APPLICATION NOTES - SG1524
the output stages ofthe SG 1524 or external transistors. Note that
one extra diode is required to protect the emitter-base junction of
switch SA during the times when both switches are open.
v+
+ VIN
~~f-B-q-~--~14I----lvol
Figure 16. Single-Ended Inductor Circuits
The third general classification. of power supply systems are
transformer coupled, two types of which are shown in Figure 17.
The push-pull circuit represents the conventional DC to DC
converter with each switch being controlled for 0-45% duty cycle
modulation. The second transformer circuit is a single-ended
flyback converter, useful at light loads without a separate output
inductor.
Figure 14. Driving External Transistors
To illustrate the use of the SG1524 in each of the above general
classifications, the following Simple, but practical, circuits are
presented:
Figure 15. Capacitor/Diode Output Circuits
For higher current applications, the single-ended inductor circuits
of Figure 16 represent another classification. Here, the two
outputs ofthe SG1524 are connected in parallel, but note thatthis
does not give twice the current as the switches are alternating
internally. This does not affect external performance, however,
and the SG1524 can be used to provide 0-90% duty cycle
modulation in any of the configurations shown.
12 - 23
Figure 17. Transformer Coupled Circuits
II
APPLICATION NOTES - SG1524
Figure 18 shows the use ofthe SG1524 as a low current polarity
converter providing a regulated -5volt output at currents up to
20mA from a single positive input voltage. The external components required include the divider resistors to interface the reference and output voltages 'v".Jith the error amplifier J a resistor!
capacitor to set the operating frequency, and the output diodes
and capacitors. The combination of the built-in current limiting of
the SG 1524 output stages and the capacitor coupling ofthe output
signal provide full protection against short circuits and the current
limit amplifier is more than enough to stabilize the regulating loop
and no additional compensation is required.
Since the currents in the secondary of a flyback transformer are
out of phase with the primary current, current limiting is very
difficultto achieve. In this circuit, protection was provided through
the use of a soft-start circuit. If either output is shorted, the
transforffi6iwill saturate, providing mOie CUiientthrough the drive
transistor. This current is sensed and used to turn on the 2N2222
which resets the soft-start circuit and turn oft the drive signal. Ifthe
short remains, the regulator will repetitively try to start up and reset
with a time constant set by the soft-start circuit. Removing the
short will then allow the regulating loop to re-establish control.
For higher current applications, the single-ended conventional
switching regulator of Figure 20 is shown.
+\5 v
1
I
15K
OK
"f ~
..
INV
V"
C,~
NI
E,
VREF
C,
RT
E,
CT
CL+
OSC
C,
IN'i!16
5K
2+01-'1
3K
01"
0-0--
IN916
IN916
SH ON.
COMP
ONO
~
5V
~
20mA
50~:F=
3K
02
---0
I
RT
CT
CL+
OSC
CL-
SH ON.
001
ONO
50K
Figure 1B. Low Current Polarity Converter
Another low-level circuit is the flyback converter shown in Figure
19.
+5VO-.----+.,....r---;---~--.--........,
Figure 20. 1 Amp, Single-Ended Switching Regulator
In this case, an external PNP Darlington is used to provide a lamp current switch. The SG1524 has the two outputs in parallel,
connected as a grounded emitter amplifier. The current sense
resistor is inserted in the ground line and the voltage across it used
for constant current limiting. Note that in addition to the divider
resistors and frequency setting RrCp a phase compensation
resistor and capaCitor is used to stabilize the loop now that an
inductor has been added.
rlI"--o-l--{}+15V
100
A fourth application would have to be a push-pull, DC to DC
regulating converter as shown in Figure 21.
Figure 19. +5 to ",15 Volt, Flyback Converter
The circuit is designed to develop a regulated ±15volt supply from
a single +5 volt source. Note that the reference terminal is tied to
the input, disabling the internal regulator. The error amplifier
resistors are also tied to the input line so thatthe output regulation
can be no better than the input; however, an external reference
could just as easily have been used.
In this application, the two output stages are connected in parallel
and used as emitter followers to drive a single external transistor.
12 - 24
Figure 21. 5V, 25W, DC to DC Converter
APPLICATION NOTES - SG1524
Here the outputs of the SG1524 are connected as separate
emitter followers driving external transistors. Current limiting in
this application is done in the primary for several reasons: First, it's
easier to live within the ±O.3 volt common mode limits of the
current limit amplifier; second, since this is a step-down application, the current - and therefore the power in the sense resistor is lower; and third, if the output drive were to become nonsymmetrical causing the transformer to approach saturation, the
resultant current spikes will shorten the pulse width on a pulse-bypulse basis, providing a first order correction. Note that the
oscillator is set to run at 40kHz to obtain a 20kHz signal at the
transformer.
The application as shown does not provide input-output isolation
and, of course, thatfeature is difficultto achieve within a single IC.
There are a couple of ways the SG 1524 can be used with isolated
power supply systems, however. The first is shown in Figure 22
where the SG1524 is direct coupled on the secondary side of the
output transformer. The outputs from the IC are transformercoupled back to the primary side to drive the switching transistors.
Of course, a separate start-up power source is needed for the
SG1524 butthat shouldn't present much of a problem remembering that the IC draws less than 1OmA of supply current.
A different method of providing isolation is shown in Figure 23
where the IC is direct coupled on the primary side. Here a
separate reference error amplifier (most easily implemented with
a SG 1532 regulator IC) is connected on the secondary and then
optically coupled back to the primary side.
PHOTOCQUPLER
Figure 23. Input/Output Isolation
As should be evident from the above, the SG1524 was designed
as the first of what will undoubtedly become a larger family of
regulator IC's specifically designed for switching power supplies.
As such, versatility was the primary design goal ofthis device and
hopefully this goal has been achieved to the degree that will allow
the SG1524 to find application to a wide range of power control
systems.
RECTlFlER
FILTER
====== DRIVE SIGNALS
VOLTAGE SENSE
Figure 22. Input/Output Isolation
II
12 -25
12-26
s-
'f,_,lljf@M
APPlL][CAT][ON NOTES - SG1524
SILICON
GENERAL
PS-3
LINEAR INTEGRATED CIRCUITS
DEADBAND WITH THE SG1524 REGULATING PULSE
WIDTH MODULATOR CIRCUIT
ABSTRACT
The SG1524 Regulating P.W.M. integrated circuit provides two outputs which alternate in turning on for
push-pull inverter applications. The internal oscillator sends a momentary blanking pulse to both
outputs at the beginning of each period to provide a dead band so that there cannot be a condition where
both output transistors are on at the same time. The deadtime duration is determined by the width of
the blanking pulse appearing on Pin 3, as measured althe ±O. 7 volt level, and can be controlled by three
techniques:
1. For the 0.3 to 1.0 microseconds, the dead band is controlled by
the timing capacitor, Cp on Pin 7. The relationship between CT
and dead band is shown in Figure 3 on the SG1524 datashee1.
Of course, since CT also determines the oscillator frequency,
the range of control is somewhat limited.
2. Above 1.0 microsecond, a simple one-shot latch similar to the
circuit shown below should be used.
When this circuit is triggered by the positive-going pulse from
the oscillator output, itwililatch for a period determined by CBR B,
providing a well-defined deadtime.
l. _ :
'REF
This circuit will limit the error amplifier's voltage range since its
current source output will supply only 100pa. Another advantage
of this circuit is that it does not change the programmedoscillator
frequency.
In general, it is not recommended to stretch the deadtime by using
external capacitors on Pin 3. There are several reasons for this:
a. It is difficult to obtain well-controlled, repeatable
deadtimes with this approach, since the logic threshold is +0.7 volts. The normal exponential fall of the
pulse trailing edge due to the external capacitor and
internal 3K pull-down resistor results in a poorlydefined crossing of the logic threshold.
10K
~
b. The external capacitor degrades the rise and fall times
ofthe clock to the internal flip-flop. For sufficiently high
values of capacitance, the flip-flop will cease to toggle
properly, especially at higher temperatures.
OSC "-------
'~p
10K
R8~2
10K
GNO
r
I
3. Another way of providing greater dead band is just to limit the
maximum pulse width. This can be done by using a clamp to
limit the output voltage of the error amplifier. A simple way of
achieving this clamp is with the circuit below:
VREFa
COMPo
IN916
In general, if a simple means of stretching deadtime is required,
the best solution is to use the SG1524B device instead of the
earlier 1524. Up to 1OOOpF can be connected to the OSC pin with
no degradation of the flip-flop operation, since the clock to the
toggle flip-flop in the 1524B is generated by the internal doublepulse suppression logic.
5K
GND
January 1990
12 -27
12 - 28
APPLICATION NOTES - SG1524
SILICON
GENERAL
PS-4
LINEAR INTEGRATED CIRCUITS
IMPROVING SWITCHING REGULATOR DYNAMIC RESPONSE
Edited by Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
ABSTRACT
Recent introductions of LSI integrated circuits for P.W.M. control have offered considerable simplification to the job of optimizing the design of switching regulators. In addition to greatly reducing the
necessary circuitry, the linear transfer function of these devices eases the task of stabilizing the
feedback loop and offers several possibilities for improved response. Experimental methods for
evaluating the response characteristics of the P.W.M. switching and output stages can be used to
confirm simplifying assumptions of linear operation. With this data, several approaches to equalization
networks can be compared for performance optimization.
INTRODUCTION
The past few years have seen a major revolution take place in the
field of power supply design. Whether forced upon us by the need
for energy conservation or finally made practical thru recent
advances in semiconductor technology, switching regulators are
now the name ofthe game in voltage control. Novices soon learn,
however, that the implementation of a well-designed switching
supply involves a little more skill than that required for a linear
regulator.
+5V TO All
INTERNAL CIRCUITRY
E,
INV INPUT
Although the theory of switching regulation has long been known,
there is much practical technology - or art - in designing efficient
and reliable systems. This is still true even though recently
introduced semiconductor devices have made the job at least a
little easier. It is the purpose of this discussion to cover a few of
the practical aspects of implementing and stabilizing switching
regulators using these newer devices.
INTEGRATED P.W.M. CONTROL CIRCUITS
Recognizing a rapidly growing market, many component suppliers have introduced new devices designed specifically for switching regulator applications. These include faster power transistors
with improved S.D.A., low E.S.R. electrolytic capacitors, hybrid
power devices which include a matched commutating diode, and
monolithic Ie control devices such as the SG124(1) which contain
all of the P.w.M. control circuitry in a single 16-pin, dual-in-line
package.
Figure 1. SG1524 Block Diagram
From the block diagram shown in Figure 1, it can be seen that the
SG1524 contains the elements necessary to implement either
single-ended switching regulators or DC to DC converters of
several different configurations. This device includes a voltage
reference, error amplifier, constant frequency oscillator, pulse
width modulator, pulse steering logic, dual alternating output
switches, and current limiting and shutdown circuitry. Since many
of the different types of applications for this IC have been discussed earlier(1) it should suffice to review only two of the more
common usages as shown in Figures 2 and 3.
January 1990
12 - 29
•
APPLICATION NOTES - SG1524
The single-sided regulator of Figure 2 is unique because of its
simplicity. This circuit combines an SG1524 with an SM625
hybrid to build a 5 volt, 5amp regulator with all the semiconductor
devices contained in only two packages. This circuit has an
efficiency of over 70% with an input voltage range of20 to 30 volts,
0.1 % line and load regulation, and some added benefits of
constant frequency operation and short circuit protection.
r SM625 ..,
0---+----,--------+:
--r\ ~-:l.J2XlooIT"""---<-U"+5V. SA
u
I
50<
i" '"
5K
, ~5K
II
"
02"
0---
'"
NI
VREf
::Sl
I
I
I
L_____ J
SWITCHING REGULATOR CONTROL
The basic switching regulator control loop which applies to the
most common forms of implementation is illustrated in Figure 4.
In analyzing this control loop stability, the obvious immediate
problem is the transfer function of the P.W.M. and output stage.
A detailed and accurate analysis of the nonlinear characteristics
of this stage is an extremely difficult and complex task if cine is to
account for all the parameters which could possibly be a factor.
(2.3.4) On the other hand, if this stage could be assumed to have a
linear transfer function, analysis becomes a relatively simple
application of basic feedback theory.
1000~f
C,
"
E,
c,
Ce+
osc
Ce-
O---" '"GND C~'~,001
n
I
'"
R2
-0
Figure 4. Basic Regulating Control Loop
Figure 2. SG1524 Single - Ended Switching Regulator
Figure 3 shows the same 5-volt, 5amp output requirement metthis
time with a DC to DC converter. The use of high speed transistors
and Schottky rectifiers keep the efficiency more than 80% significantfor a lOW-VOltage output - while maintaining all the other
benefits included in the single-ended circuit.
A significance of the SG1524 is that it uses a design approach
which makes a linear assumption accurate enough for most
applications. The fact that this device features constant frequency operation, a linear-slope ramp for P.W.M., and fastresponse logic and output circuitry all contribute to minimizing the
errors associated with a linear assumption. Of course, there are
factors external to the IC which could destroy this assumption.
Such things as excessive delay in the switching transistors,
parasitic ringing or oscillation in the power stages, or nonlinear
operation of the magnetics could all cause a resultant nonlinear
performance. A first exercise for the deSigner, then, is to confirm
linear operation of the P.W.M. and output stages of his regulator
by evaluating his early breadboard models.
OUTPUT STAGE ANALYSIS
Figure 3. SG1524 Regulating DC - DC Converter
It should be recognized that the above circuits represent very
basic applications of an IC control Chip. Most practical power
supply systems would probably incorporate many other features
which may be accomplished by interfacing these IC's with a small
amount of external circuitry to add characteristics such as: sift
start, oscillator synchronization, dead-band contrQls, additional
current and/or voltage step-up stages, input-output isolation,
remote overvoltage or overload shutdown, and response modifying cirCUitry. It is this latter subject we wish to explore more fully
below.
The pulse width modulation is accomplished in the SG1524 by
comparing the output of the error amplifier with a linear ramp, or
saw-tooth signal from the oscillator. Because the comparator has
both high gain and high output impedance, and the error amplifier
has a high output impedance, this node (pin-9) becomes a very
convenient place for inserting a test signal. A voltage source
applied as shown in Figure 5 will completely override the error
amplifier and essentially open the loop without actually breaking
any connections. In addition, the test signal is easily managed
because the voltage gain from this point to the output is relatively
low. (A voltage level on pin 9 of from 1 to 4, volts will change the
pulse width from zero to maximum which will yield zero to
maximum output voltage.)
12 - 30
APPLICATION NOTES - SG1524
Regardless of the requirements for minimizing the output ripple,
an additional requirement on the filter is that its cutoff frequency
will be well below the switching frequency if our original goal of
simple linear analysis is to be met. Specifically, the switching
operation introduces a second order lag at one-halfthe switching
frequency and for the output filter to dominate, its cutoff should be
at least an order of magnitude below that number or
1
2,,;v'LC s
Figure 5. Measuring Output Stage Transfer Function
In experimentally attempting to confirm satisfactory operation of
the output stages, the designer hopes to prove that a linear
equivalent circuit model is valid for reasonable analysis. One
such model as proposed by Middlebrook('1 is shown in Figure 6.
This model describes the overall AC and DC transfer function and
input and output impedances in terms of the duty cycle and
modulation constant. This model assumes that the effects of
operating frequency, switching delays, and parasitic elements are
well above the frequencies of interest as defined by the output LC
filter.
f
20
To verify the performance of the resultant hardware, a Bode plot
of the output stage response can be most meaningful. Ideally, a
plot as shown in Figure 7 should show a flat response to the filter
cutoff and then a linear 12dB/octave rolloffwith a 180· phase shift.
II IIIII
IT [lIT
II IIII
II 1"1
10
m
~
I - f-- VOLT AGE GAIN
0
PHASE
I
z
«
<.:J
w
<.:J
""--'
-10
i""
-20
1\
f--
0
>
-30
VIN =Input voltage to converter
NC =Control voltage input
km =P. W.M. constant
=Duty Ratio=\b/VIN =NC/km
o
II 11111
10
Figure 6. Linear Equivalent Circuit
Vi'
w
"'1\
~
100
~
w
0
L=200Jlh
C=1000!'f'
\
--'
<.:J
-100
""w
-150
I
0..
V1
I'
~Iiiii ~
lK
'I
w
z
\ ...... \
II 11111
<.:J
0
-50
i\
""w
II 1111
""
-200
10K
FREQUENCY-(Hz)
Values for the inductor and capacitor are normally calculated on
the basis of output ripple current and voltage as follows:
L=
VINf(.1.'Ll
VO(V,N - Vol
and
where:
Y'N =peak input voltage to the indicator
V0 = output across the capacitor
= switching frequency
f
.1.IL =peak - to - peak current variation in the inductor
.1.V =peak - to - peak ripple voltage across the capacitor
Figure 7. Linaear Output Stage Response
By making these plots with varying input voltage and load current,
factors affecting stability such as leakage inductance, capacitor
E.S.R., and either saturation or discontinuous operation of the
magnetics may be evaluated over the operating conditions of
interest. Figure 8 shows typical plots with less than ideal component parameters. With the characteristics of the output stage
defined, attention can be turned to the error amplifier to develop
an equalizing network which will allow satisfactory closing of the
loop.
°
Note that the actual ripple voltage at the output of the filter will
be .1.Vo' plus .1.IL times the capacitor E. S. R.
12 - 31
•
APPLICATION NOTES - SG1524
CD
"
'(
z
20
~
VII~~20V•• IL=5A
0
f-
0
h
pJASE
.....
-10
,
~
~
,
1\
II III
1111
be connected from output back to the inverting input. (6) In the first
case the voltage gain is:
II 11111
L 2001'h
C=1000JLF
~
8 c- c
~g~ ~:'2i~ r-
~
E.S.R/
,/
2kT
Ay = gmZc = - 7I ~ 0.002Zc
0
Vi'
w
-50
"'"w
w
I"11III
~
'"w
'(
-100
'- 1'00..
-150
-'
"«z
w
Vl
II 11111
10
100
II Jill
lK
II :1111
10K
where Zc is the complex compensation network impedance. If a
feedback approach is used, the gain is:
II 11111 -200
«
I
0..
FREQUENCY-(Hz)
where Zs is the source impedance driving the input. In cases
where relatively low impedances are desired in a feedback
network, it may be necessary to buffer the high output impedance
of the error amplifier. Figure 10c shows the use of an external
emitter follower to provide a low driving impedance for the
feedback network.
Figure 8. Measured Output Stage Response
ERROR AMPLIFIER COMPENSATION
The error amplifier contained within the SG1524 is a transconductance amplifier in that it has a high-impedance, current source
output. The gain is a function of the output loading and can be
reduced from a nominal 80dB by shunt resistance as shown in
Figure 9. Note also in Figure 9 that the uncompensated amplifier
has a single pole at 300Hz and 90 0 of phase shift. The unity gain
cross-over frequency is 3MHz and the large scale slew rate is 0.5
volt per microsecond.
.
80
II 1111
~
70
CD
60
30
"
'(
z
"w
~r
- !?t.
"-
lMO
II 11111
II 1111
Figure 10. Error Amplifier Compensation Networks
~ !\.
~o",
~
300KO.
~
100KO
.....~(
~ ~'Y
Vi'
w
Q
f-
0
........
-30
-40
II I1III
+
_
Ul
w
L=200J.tH
w
C=.:..lOOO,uF
0
-50
1\1\.
'"
lO
w
eI
w
--'
'-'
z
1\r--.. I-- ..
II I11I1
100
10
,
REF
1\
pJASE
-10
RC
\ ~-
V
AMPLITUDE
I I 11111.162m~ I 111111
-100
"'w"
-150
:r:
"-
U1
II 1111
"'"
Figure 13. Series RC Phase Compensation
II I11I1 -200
10K
lK
40
FREQUENCY-(Hz)
30
Figure 11. Closed Loop Frequency Response
INCREIASI~"
Cc
~
\...
m
.:'0,
20
I
10
w
• - _UNCOMPENSA TED
'
_COMPENSATED
Ul
w
0
:::J
f-
::J
\ f"
\ I
":::;
w
180
0
«
1\
135
\
'"w
lO
eI
w
--'
lO
Z
90
\. V
«
w
U1
\ 1/
fpc
fpc
-'--'2rrROCo 2nRCCc
pc
"'"
:r:
"-
-'2rrRCCo
STIMULOUS.
UPPER TRACE'
LOINER TRACE'
TIME BASE'
Figure 14. Phase Compensated Bode Plot
Figure 12. Integrator Compensation Step Response
Figure 13 shows a circuit for accomplishing this by moving the
amplifier pole lower in frequency and adding a zero at the output
filter cutoff frequency. Figure 14 shows the effects ofthis network
on the Bode plot of the error amplifier, and Figure 15 indicates the
improvement in recovery from the same one-amp load change.
Note how the output of the error amplifier overshoots to give a
boost to the output.
Even faster response can be achieved by providing additional
lead networks. For example, another zero may be added by
bypassing the sense feedback resistor. As can be seen in Figure
16, this greatly improves loop response but offers the hazard of
coupling ripple noise directly into the error amplifier.
rI"
"
V'
RC~30KO, Cc~.022mF
~~j~~~D~RS~CE: ~~REO:MJM~T6~T~~.Ng~ri~JJDlV
LOVIER TRACE'
TIME BASE
REGULATOR OUTPUT, 100mV/DIV
5 MILLISECONDS!DIV
Figure 15. Phase Compensated Step Response
12-33
II
APPLICATION NOTES - SG1524
TWO LOOP CONTROL
From the examples presented above, it should be apparent that
the integration method of error amplifier compensation provides
good stability by making the dominate pole so low in frequency
that variations in all other circuit parameters become inconsequential. This technique also provides high accuracy at DC where
high gain can be used and is the type of feedback one would want
to take directly from the output of a regulator since a user might
add additional external capacitance, thereby changing the output
filter characteristics. Another reason for using single-pole compensation is to accomodate the use of a two-stage output filter
which can add phase shifts well beyond 180°.
~~
~OK
5K
~~~OR
With a linear output stage, conventional feedback analysis can be
used to define the best equalizing network achieving a compromise between stability and fast response. In some cases it may
even be desirable to provide separate signal paths for these two
parameters butthis, too, can be adapted to the SG1524 controller
with a minimum of external circuitry.
Obviously, no recipes for optimum performance have been provided herein. Only a few directions which, it is hoped, will pointthe
way toward the development of specific solutions for specific
applications.
o.22mF.
FROM
vo
valid. The SG1524 controller offers benefits in this regard as it
does provide a linear transfer function through its pulse width
modulation scheme. Therefore, experimental techniques can be
used to simply confirm proper operation of the power switches and
output filter.
TO P.W.M.
REF-+--
REFERENCES
: 5K
-=-
1. R.A. Mammano, "Simplifying Converter Design with A
New Integrated Circuit Regulating P.W.M.," Powercon 3
Proceedings, June, 1976
2. F.C. Lee, Y. Yu, and J.E. Triner, "Modeling of Switching
Regulator Power Stages With and Without Zero Inductor
Current Dwell Time," IEEE P.E.S.C., Record, 1976
v
3. A. Capel, J.G. Ferrante, and A. Prajuuk, "State Variable
Stability Analysis of Multi-Loop PWM Controlled Regulator
in Light and Heavy Mode," IEEE P.E.S.C., Record, 1975
I~
II
4. Y. Yu, J. Bless, and A. Schoenfeld, 'The Application of
Standardized Control and Interface Circuits to Three DC to
DC Power Converters," IEEE P.E.S.C:, Record, 1973
STIMULOUS:
UPPER TRACE:
LOWER TRACE:
TIME BASE:
5. A.D. Middlebrook and S.Cuk, "A General Unified Approach to Modeling Switch Converter Power Stages,"
IEEE,P.E.S.C., Record,June 1976
Figure 16. Double Zero Compensated Step Response
The problem of poor response can then be accommodated by
adding a differentiated signal taken from somewhere else in the
I,oop. Ifthe time constants and gain factors are properly selected,
the differentiated Signal can compensate for the error in the
integrated signal taken from the regulated output.
SUMMARY
Although integrated circuit controllers for switching supplies have
removed much ofthe circuit complexity from this type of regulator,
the dynamic analysis ofthe control loop must still be optimized for
each application. This optimization is made easier, however, if a
linear approximation of the switching stages can be shown to be
12- 34
6. J. Graeme, G. Tobey, "Operational Amplifiers, Design and
Applications," McGraw Hill Publishing Co., 1971
7. D.E. Nelson and N.O. Sokal, "Improving Load and Line
Transient Response of Switching Regulators by Feed Forward Techniques," Powercon 2 Proceedings, 1975
I"
•
SILICON
APPLICATION NOTES - SG1524B
GENERAL
PS-5
LINEAR INTEGRATED CIRCUITS
CONVERTING 1524 SWITCHING POWER SUPPLY
DESIGNS TO THE SG1524B
Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
INTRODUCTION
Many power control engineers have designed successful switching power supplies around the SG1524 Pulse Width Modulator
integrated circuit. This application note explains the differences
between this earlier device and the more sophisticated SG1524B.
While the functional pinouts are identical forthetwo devices, there
are some distinct operational differences which the user should
be aware of when designing new supplies or when updating an
existing design. In many cases design changes are minimal (such
as adjustment of frequency compensation) or not required at all.
At the same time the improvements in control architecture and
circuit design of the SG1524B allow the designer to obtain levels
of performance in new power supply designs not possible with the
older device.
insure constant-frequency alternating output pulses to the power
devices.
+5V lO ALL
INTEflNALCIRCUITRY
(RAt.I~~
GENERAL COMPARISON
Figures 1 and 2 show respectively the block diagrams of the
SG1524 and the SG1524B. Both devices were designed for
voltage-mode control, but both can be used to implement currentmode control as well with the addition of an external dual op amp.
For further details see the Silicon General Application Note
"Current Mode Control with the SG1524B."
Figure 1. SG 1524 Block Diagram
The main functional difference between the two circuits is in the
action of the shutdown pin. In the SG1524, a voltage at Pin 10
greater than +0. 7volts will turn on an internal transistor which pulls
the error amplifier output to ground. In the SG1524B, a voltage
greater than +1.2 volts at Pin 10 activates a logic gate which
inhibits the pulse output of the PWM comparator. The error
amplifier output-voltage is not affected directly.
II
Other improvements include the addition of an undervoltage
lockout function and fault suppression logic. These provide
protection against inadequate supply voltage to the controllC and
Figure 2. SG1524B Block Diagram
January 1990
12 - 35
APPLICATION NOTES - SG1524B
INDIVIDUAL SECTION DIFFERENCES
Voltage Reference
The voltage reference is a low-drift bandgap design which provides a precision +5.0 volt references for the control loop. Initial
accuracy is ±1% for the SG1524B/2524B, and ±2% for the
SG3524B. This is a factor of four improvements over the original
reference. Line regulation is typically better by a factor of 3:3mV
instead of 10mV. Load regulation is better by a factor of 4:5mV
rather than 20mV. The temperature coefficient is also lower and
more uniform from device to device. All these features translate
directly into tighter tolerances on the switcher output voltage.
At 25·C the differential drop across the regulator is only 1.2 volts,
as opposed to 2.7 volts for the 1524. Figure 3 shows the
relationship between VINand VREFfor both devices. As a result, the
SG1524B is fully functional with a 6.2 volt supply. Under worse
case conditions of ILOAD =20mA and TA = -55·C, all devices also
guaranteed to function at VIN =7 volts.
The bandgap comparator monitors the reference voltage. It
enables the SG1524B when the reference rises to +4.3 volts. This
arrangement allows OPeration from a +5 volt ±5% supply by
connecting VIN and VREF together.
The action of the undervoltage lockout can be observed with the
test circuit of Figure 4. A 1OOK pull-up resistor is connected from
Compensation to VIN . VIN is swept from 0 to +6.5 volts with 5Hz
triangle waveform from a function generator. An oscilloscope in
>N Mode displaying VIN horizontally and Compensation vertically
will generate the display shown in Figure 5.
SG 15248
TO X AXIS
~
"REF
UN.I.
+6.5/\V
15 "IN
ov
INV. 1
EA 11
Es 14
SHUT 10
10K
-=-
5
I
S'
'I
w
<.:>
«
4
---'
SG15248
0
>
3
COMP
2
J
1
J
0
0
1#
TO Y AXIS
Figure 4. Undervollage Lockout Tesl Circuil
SG1524
#
#.
#
1/
##
2
4
-C.S. 5
GND 6
###
V:'
V# /
U
Z
w
n::
w
Lo..
w
n::
J
##
I-
w
+c.s. 4
6
8
10
SUPPLY VOLTAGE-(V)
Figure 3. Reference Voltage vs. Supply Voltage
Undervoltage Lockout
This circuit has two sections: a controlled current source which
forces the error amp low and the output transistors off, and a
bandgap comparator which overrides the lockout source. The
current source is fully active when VIN is +1.2 volts. Since the error
amp and output driver cannot function until VIN is approximately
3 volts, it is impossible for spurious output pulses to occur when
the supply voltage is too low for normal operation.
12 - 36
APPLICATION NOTES - SG1524B
As VIN slowly sweeps from 0 to 1 volt, the lockout current source
becomes active and pulls the error amp to ground, guaranteeing
0% duty cycle from the controller. From 1 voltto approximately 5.5
volts the controller is inhibited while the internal circuitry stabilizes. At 5.5 volts the bandgap comparator overrides the lockout
current, releasing the output olthe error amp. The reverse portion
of the voltage sweep is identical, except that approximately
200mV of hysteresis can be observed at the comparator trip point.
Oscillator
Error Amplifier
The error amplifier of the SG1524B is, like its predecessor, a
transconductance design with an output impedance of approximately 4 megohms. This allows use of external clamp cirCUitry to
obtain soft-start and duty cycle limit, as on the original 1524. Since
all the voltage gain takes place at the output pin, open-loop gain/
frequency characteristics are easily controlled by shunt reactance
from Pin 9 to ground (Figure 7). Also, this type of amplifier has a
very predictable 1rr variation of open-loop gain with absolute
temperature as shown in Figure 8.
The oscillator of the SG1524B is programmed for frequency with
an external RT and CT in the same manner as the SG1524. Both
initial accuracy and temperature coefficient have been improved
with the "B" version.
fpale=
~
27TROCpale
where RO=Output Impedance
=4x106 0
CD-VTcpale
There are two methods to synchronize multiple units together.
f zero = ::-::--1,--:--_
27TRzera Cpale
l Rzera
A. Program master unit with RT and CT for the desired frequency. Connect the Ct terminal (Pin 7) of the master to
the Ct terminal of the slave. Connect the OSC terminal
(Pin 3) of the master to the OSC terminal of the slave.
Leave the slave RT terminal (Pin 6) open or tied to the
reference. This is the recommended approach if the
PWM controllers are close together (on the same printed
circuit board and within six inches of each other).
where Cpale»CO 120pF
and Rzera«RO
Figure 7. Frequency Compensation of the Error Amplifier
m-
B. Program a master unit for the desired frequency. Select
RT and CT for the slave units such that they free-run at a
frequency 10% slower than the master. Connect all the
oscillator terminals together. This method is recommended if the PWM controllers are not close together,
since it avoids routing a high impedance line (CT) around
a noisy environment.
~
80
..
I
z
«
'-'
60
-
w
'-'
<{
f-
.J
0
>
a..
0
0
To synchronize one or more devices to an external clock frequency, one olthe connections shown in Figure 6 should be used.
The device(s) to be synchronized should free-run 10% slower
than the clock. Pulse width of the external clock should be at least
200nsec, but not longer than the desired deadtime.
40
20
.J
Z
W
a..
0
0
-75 -50 -25
0
25
50
75 100 125 150
JUNCTION TEMPERATURE-(OC)
Figure 8. Open Loop Gain vs. Temperature
The input common mode range is +2.3 to +5.2 volts, so that
existing designs at +2.5 volts will function with no modifications.
For new designs the +5 volt reference may be applied directly to
the non-inverting input, eliminating the necessity for two divider
resistors.
A. TTL LOGIC
B. 5VOL T CMOS LOGIC
Figure 6. Oscillator Sync to an External Clock
Since the lower common mode limit is +2.3 volts forthe 1524B and
+ 1.8 volts forthe 1524, neither amplifier should ever be used in the
12-37
APPLICATION NOTES - SG1524B
non-inverting unity-gain configuration shown in Figure 9. The
error voltage must swing down to +0.5 volts to guarantee 0% duty
cycle from the pulse width modulator, and this violates the
common mode range specification.
the aforementioned delays. If Pin 5 is driven below -O.3v at TA =
+ 125°C the substrate diode will conduct. The 1OOohm resistor will
limit the peak substrate current to a safe value without shifting the
C.L. threshold.
In general, any frequency compensation for the voltage control
loop which works with the SG1524 can also be used with the
SG1524B with no modification.
~+VOUT
I
SG1524B
+C.L.
~
GND.
100
RAW
\)
SUPPL y - -......V\/'v--......- - - - - - - - - t l RETURN
RETURN
RSENSE
Figure 10. Current Sensing in the Ground Line
Current sensing may also be accomplished with a common
emitter or source resistor to ground as shown in Figure 11 ; or it
may be placed in the supply output line, as indicated in Figure 12.
At -55°C the value OfVIN must be at least 2.5 volts greater than the
switcher output voltage.
Figure 9. Non-Inverting Unity-Gain Connection
(Not Recommended)
Current Limit Amplifier
The current limit amplifier of the SG1524B is one of the most
significant areas of change from an applications viewpoint. Like
the original circuit, there is a fixed 200mV threshold designed into
Pins 4 and 5 to permit direct sensing across a current sampling
resistor. Differences in the "B" circuit affect the input bias current,
allowable common mode range, and stability in current-limit.
SG1524B
EB
Input Bias Current
In the SG1524, there is a constant 130llA flowing out of Pin 4,
while the current outof Pin 5 is variable from 0 to 1001lA depending
on the differential in put voltage. Because ofthis characteristic, the
current limit sense terminals must be driven from source impedances less than 20 ohms to avoid modulating the current limit
threshold. The "B" device features bias currents which are
identical at each pin, are independent of current sense voltage,
and are a factor of 10 lower. This allows predictable foldback
current limiting without wasteful low-resistance divider networks.
+C.L.
RSENSE
-C.L.
Figure 11. Sensing Primary Current With an Emiller Resistor
RAW
SUPPLY
Common Mode Range
The guaranteed common mode range of the current sense inputs
is 0 volts to "IN -2.5 volts. Current sensing in a supply ground line
is possible, but the configuration of Figure 10 should be used to
avoid damaging the IC. The 1OOohm resistor is required because
of delays through the controller and storage time in any bipolar
device. The SG1524B will reduce the pulse width as Pin 5 is
driven 200mV below ground, but in practice it is overdriven due to
Figure 12. Current Sensing in the Output Line
12 -38
APPLICATION NOTES - SG1524B
Frequency Compensation
Output Transistors
The original SG1524 current limit amplifier had a typical open loop
gain of44dB and was internally compensated to produce a singlepole rolloffabove 300Hz. The SG1524B exhibits 75dB of gain and
has no internal compensation. The circuit may be used as a
moderate speed comparator, or it may be used as an analog gain
block to override the error amplifier.
The output devices have been redesigned to provide 100mA
continuous and typically 200mA peak, with BVCEX ratings of 60
volts. Saturation voltage is guaranteed both at 10m and 100mA
to ease the interface with external power devices.
Because of the higher gain and bandwidth, designers may find
thatthe control loop will oscillate when the supply goes into current
limiting. The cure is to add frequency compensation externally to
the current limit circuit or to rework the existing voltage loop
compensation. See the Silicon General Application Note "A New,
Versatile P.W.M. Control Circuit for Switching Power Supplies."
For driving bipolar devices the circuit in Figure 14 is recommended. The ouput transistor is used as a phase-splitter to
generate the necessary base drive. Figure 15 illustrates forward
and reverse base current, and collector current of a PMD 20K 120
volt, 14amp Darlington using this driver configuration.
Bipolar Drive
+15V
Shutdown
The shutdown circuit ofthe "B" is illustrated in Figure 13. It has the
following differences compared to the 1524:
A. Logic threshold is + 1.2 volts instead of +0.7 volts for compatibility with TTL logic and improved noise immunity.
TO
LOAD
B. Input current is very low (usually under 100f!A) even at +5
volts input. The pin may be driven directly from TTL logic
(all families) to TTL-output comparators.
C. Response time is very fast, between 35 and 100 nanoseconds depending on output transistor loading.
Figure 14. Driving Power Bi-PolarTransistors with the SG1524
TO LOGIC
SHUTDOWN
+50mA
Q2
o
i/
4K
-50mA
-100mA
Figure 13. Shutdown Circuitry ot the SG1524B
4A
The shutdown pin should never be left floating. Ifnot used, the
pin should be grounded. If the shutdown function is used, the pin
should be driven from a low impedance source to prevent noise
pickup. The internal logic is very fast, and will respond readily to
spurious pickup from the normally noisy environment of a
switcher.
12-39
2A
o
\r ~
.......
'\
i\
Figure 15. Bipolar Turn-Off Waveforms.
Upper Trace: Darlington Base Current @ 200 Nsec/Div.
Lower Trace: Collector Current @200 Nsec/Div.
APPLICATION NOTES - SG1524B
MOSFET Drive
Highly capacitive loads such as presented by the gated of power
MOSFET's can be readily driven with the circuit in Figure 16. At
turn-on, 200mA of charging current is conducted by 01. During
turn-off Dl becomes back-biased by the pull-down resistor. Ql
turns on and provides 500mA of discharge current. Figure 17
shows the turn-off gate voltage and drain current of an IRF130 100
volt, 14amp power MOSFET driven directly with this circuit.
+ 1OV
+5V
CONCLUSION
o
4A
A designer who is familiar with the SG1524 will find it relatively
easy to adapt his designs to use the SG1524B. The immediate
benefits are higher levels of power supply performance, worthwhile reductions in total component count, a greater degree of
protection for the power devices, and lower overall costs.
o
1::::t:::t:-:"""j":::"1"""..J-+--l-+-~f--l
\
\
,
~+-~~-+~_\"
~-+--4---+-~--~-'~+--4---+-~--~
\v
Figure 17. MOSFETS Turn-Off Waveforms.
Upper Trace: Gate Voltage @ 100 Nsec/Div.
Lower Trace: Drain Current @ 100 Nsec/Div.
+15V
Figure 16. Driving Power MOSFETS With the SG1524B
12 -40
SILICON
APPLICATION NOTES - SG1524B
GENERAL
PS-6
LINEAR INTEGRATED CIRCUITS
A NEW, VERSATILE P. W.M. CONTROL CIRCUIT FOR
SWITCHING POWER SUPPLIES
Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
ABSTRACT
A new control circuit for pulse-width-modulated switchmode power supplies is described. This device
offers improved electrical and functional performance over earlier designs, while retaining the familiar
pin-out of the industry-standard SG1524. Innovative circuit design techniques and optimized control
architecture result in improved reference accuracy, protection against inadequate supply voltage,
elimination of harmful output switching transients, improved current limiting, and higher voltage and
current capabilities from the output transistors. A 50kHz power supply utilizing the new controller is
described, and performance characteristics are analyzed.
INTRODUCTION
Since the introduction in 1976 of the first monolithic control chip for
switch mode power supplies, and its subsequent wide acceptance
as the basic building block for high-efficiency regulator designs,
the semiconductor industry has found itself in a bit of quandry
when attempting to define an improved device. On the one hand,
the initial device, being rather simple and straightforward, had a
number of deficiencies when its capabilities were compared with
the total requirements of most switchers. As a result, new, more
complex controllers were introduced with improved reference
accuracy, protection against inadequate or fluctuating supply
voltage, improved current limit circuitry, fault suppression logic,
and a host of other features.
Figure 1. Block Diagram of the SG1524B Pulse Width Modulator
On the other hand, the new controllers, while enthusiastically
accepted first by aerospace designers for sophisticated highperformance supplies and later by major computer and instrumentation manufacturers, lacked the familiar pin-out ofthe earlier
device. As a result it has not been possible until recently to easily
upgrade the performance of an existing design by simply plugging
in a more intelligent pin-for-pin substitute.
The circuit to be described has been under development at Silicon
General for more than two years, and represents an attempt to fit
as much function as possible within the constraints of the original
device pin-out. Designated the SG1524B, the device block
diagram is shown in Figure 1.
FUNCTIONAL DESCRIPTION
A precision +5.00V reference trimmed to an initial ±1 % accuracy
provides a voltage standard for the regulation loop. It also powers
most of the internal control circuitry, eliminating adverse effects
due to fluctuating supply voltage. A high gain error amplifier
compares the reference voltage with the switch mode supply
output voltage, and generates a PWM control voltage at Pin 9.
Thisvoltage is compared against a periodic linear ramp generated
by the oscillator circuit. Oscillator frequency is determined by an
January 1990
12 - 41
II
APPLICATION NOTES - SG1524B
external timing resistor and capacitor, RT and CT' The comparator
output is a fixed-frequency, variable pulsewidth logic signal which
passes through routine logic to one of the two high current output
transistors if the Shutdown pin is LOW.
A current limit amplifier within the IC overrides the PWM control
voltage when the voltage differential at the Current Limit Sense
inputs reaches 200mV. This built-in threshold permits direct
sensing across an external current sampling resistor. On-chip
undervoltage lockout circuitry protects the power semiconductors
in the switch mode supply by guaranteeing orderly start-ups and
shutdowns as supply voltage is switched on and off.
Each control section of this new PWM controller has been either
redesigned for improved performance, or is a completely new
function compared to the original SG1524 design. A detailed
description of each section follows to highlight the major improvements.
Bandgap Reference Regulator
The precision reference uses the predictable base-emitter voltage of NPN transistors to generate the +5V reference voltage,
rather than a zener diode!1.2) The advantages of this design
approach are: lower noise due to elimination of the shot noise
associated with an avalanche device, low turn-on drift, better log
term stability, and operation from a lower supply voltage. The
primary disadvantages are that the bandgap requires more
components, and thermal matching of key devices is necessary
for realizing low thermal drift.
Minimum Supply Voltage
Output Noise Voltage
Long Term Stability
Turn-on Drift
ZENER
REFERENCE
BANDAGE
REFERENCE
8V
75 flVrms
20 mV/1000hrs
5-35 mV
7V
25 flVrms
5 mV/1000hrs
2 mV
amplifier output is released. Since compensation capacitance is
usually present at Pin 9, this provides a measure of built-in soft
start.
During the power-up period of the controller, when the undervoltage lockout is achieved, bias current is freely supplied to all the
internal control circuitry. This insures that all control functions
have stabilized in the proper state when the turn-on voltage is
reached, and it prevents the possibility of start-up glitches.
The lockout circuitry monitors the reference voltage rather than
+V'N to allow the SG1524B to be used with +5V supplies in the
same manner as the original SG1524. lithe +V'N pin is connected
to the V REF pin and +5V ±10% is applied, the control chip will
function normally. When the undervoltage sense circuitry monitors the +V'N pin, this type of operation is not possible due to the
2-3V drop across the internal regulator.
Tp provide jitter-free turn-on and turn-off pOints, the lockout
circuitry has been designed with approximately 500mVof hysteresis. This provides rejection of 120Hz ripple on the +VIN line and
reduces capacitive filtering requirements on the controller supply
voltage.
Error Amplifier
The error amplifier of the SG1524B was designed with three
principle goals in mind: a common-mode range extending from
+2.5V to +VREF' excellent supply voltage and common-mode
noise rejection characteristics, and a minimum voltage gain of
60dB at + 125'C. Like its predecessor, it is a transconductance
amplifier with a high-impedance output to permit external softstart circuitry.
Table 1. Comparison of Zener and Bandgap
Reference Typical Parameters
The ability of the PWM controller to be fully functional with a 7V
supply enhances its usefulness in portable instrumentation applications, where six-cell Ni-Cad battery voltage is defined as endof-life before recharge.
Undervoltage Lockout
Figure 2. Schematic Diagram of the SG1524B Error Amplifier
The undervoltage lockout circuitry prevents spurious turn-on
commands to the external power transistors when the supply
voltage to the integrated circuit is too low for proper operation.
When the reference voltage is less than +4.5V, the outputtransistors are forced to an OFF or nonconducting state. Additionally, the
output of the error amplifier is clamped to ground. When the
supply voltage rises to +7V, the output drivers are enabled and the
Input transistors 01 and 02 are connected as emitter-followers
with their collectors tied to the +5V reference supply. This
configuration provides the required common-mode range, even
with +V'N connected to V REF for operation from a +5V supply. It
also provides current gain to reduce input bias current, and
produces a low impedance source to drive level shifters 03 and
12 - 42
APPLICATION NOTES - SG1524B
04. These PNP devices operate at a forced beta of 1.0, and are
connected common base to maximize frequency response. Input
stage operating current is set up by the 1OOflA bias supply to the
common base. Frequency response is further improved by the
low impedance collector loads 05 and 07. These two devices are
diode-connected and form the input sides of two precision 2-to-1
current mirrors, which provide additional current gain. The output
current of 06 provides the pull-down or sink current for the
amplifier output. The collector current of 08 is referenced to the
+5V supply rail by the Wilson current mirror consisting of 09, 020,
and 011. the collector current of 011 provides the pull-up or
source current for the amplifier output. It can be seen from the
symmetry ofthe circuitthat a differential input voltage is converted
to an output current, with a maximum of ±200J.lA available. The
open-loop voltage gain can be shown to be (3)
Since RL is the parallel combination of the output impedances of
06 and 011, and is typically 4MQ an open-loop voltage gain of
72dB is obtained.
The circuit design of the output stage insures that the maximum
positive output swing never exceeds +4.3V. This is important
when considering loop recovery from momentary overlaods
which drive the PWM to maximum duty cycle. The peak value of
the sawtooth oscillator waveform is +3.4V, and the error amplifier
must slew from positive full scale to less than this voltage to
reduce the duty cycle from maximum. Some error amplifier
designs clamp the output voltage with a 6.3V zener diode, nearly
tripling the recovery time from overload. Since all the voltage gain
ofthe error amplifier takes place atthe output pin, the amplifier can
be easily frequency compensated at this node with shunt reactance to ground. The uncompensated amplifier exhibits an open
loop pole at 350Hz and a typical unity-gain bandwidth of 2MHz.
be separated, making the current limit function unusable. Also,
the internal frequency compensation provided freedom from
oscillation at the expense of response time.
In the new design, input transistors 01 and 02 allow common
mode voltages as low as -0.3V over the operating temperature
range, allowing sensing in the ground line for configurations that
require it. The upper limit is restrained only by the value of +V'N'
to which the level-shifter current sources 11 and 12 are referenced.
The voltage drop across R2 creates a 200mV offset voltage at the
amplifier input which provides the current sense threshold. The
positive 0.2%rC temperature coefficient of R2 is balanced by a
negative tempco for 12, effectively canceling effects of temperature on the current sense threshold.
Since both the allowable common-mode and differential voltages
are much greater with this design, higher current fold back ratios
can be achieved compared to the maximum of 3 or 4 possible with
the earlier part. Also, the bias currents are a factor of 10 lower,
resulting in more consistent limiting thresholds from unit-to-unit
when foldback is employed.
Because there is no internal compensation capacitor, stability in
the current limit mode will depend on external components. Due
to the controller architecture, in which the output ofthe current limit
amplifier overrides the error amplifier, these external frequency
compensation networks may either be shared with the error
amplifier or optimized for the current limit amplifier. The two
choices are shown in the figures. In either case, the designer now
has the freedom to optimize bandwidth for his particular switcher
configuration.
RSENSE
Current Limit
The current limit amplifier has been redesigned to eliminate the
two most common complaints about the original SG1524: limited
input voltage range and slow response time. In the original deSign
the ±1V common-mode range restricted current sensing to the
supply return line only. In many systems, ground returns cannot
Figure 4. Current Limit Compensation in Comon With Error Amp
CcOMP RzERO
Figure 3. High-Gain Current Limit Amplifier
Figure 5. Current Limit With Optimized Frequency Compensation
12 - 43
•
APPLICATION NOTES - SG1524B
Oscillator
The sawtooth oscillator circuitry ofthe SG1524B incorporates the
same design improvements recently applied to the SG1524.
These result in greatly improved external drive and synchronization capability, together with reduced sawtooth undershoot at high
frequencies. hi the original SG1524 design, an external synchronization pulse applied to the OSC pin did not generate a selfsustaining discharge cycle. The extent of the discharge of CT
depended on both the amplitude and duration of the external
pulse. As a result, it was possible to generate erratic sawtooth
waveforms with partial discharge cycles and pulse-to-pulse
modulation of waveform endpOints. The frequency result was
audible noise from subharmonics, transformer saturation, and
destruction of the power transistors.
changes state with every oscillator pulse, irrespective of what the
outputs are doing.
Figure 6 and 7 illustrate the difference in performance between
two PWM controllCs, one with only a data latch and the other with
the full double-pulse suppression logic described above. The
triple-trace photos in each example show an alternating output
pulse sequence interrupted by a SHUTDOWN command, followed a short time later by resumption of outputs from Emitters A
and B. Oscillator frequency is 40kHz for each device, so 20kHz
is obtained at the output transistors.
In the improved design, and external sync pulse which meets the
minimum threshold requirements triggers a positive feedback
circuit. This circuit drives the oscillator to end-of-discharge even
if the external pulse is very narrow. Due to the feedback, there
exists no in-between or quasi-synchronized state; the oscillator
switches smoothly between free-running and synchronized
modes as the external pulse amplitude is varied through the
trigger threshold.
The positive feedback also effectively bootstraps the comparator
gain, providing enhanced voltage swing and output current at Pin
3 to drive peripheral circuits. The improved oscillator design,
together with a fast, DC-coupled toggle flip-flop, permits operation
beyond 500kHz. However, the limitations associated with singletransistor outputs put a practical upper limit of 400kHz on the
device.
HORIZONTAL: 50j.lSEC/DIV
VERTICAL:
(TRACE 1) 5 VOLTS/DIV
(TRACE 2) 10 VOLTS/DIV
Figure 6. Output Sequence Without Double Pulse Suppression
Full Double-Pulse Suppression Logic
z
~~
WO
The PWM logic in the SG1524B insures that the output pulses
always alternate from side to side, regardless of the action of the
shutdown circuit. This is very important in push-pull switcher
configurations where two pulses in succession on one side of the
power transformer primary will cause core saturation and instantaneous failure of the power transistor.
Uf-
«::J
OCI
f-(f)
The logic consists of two sections: a PWM latch circuit and a
memory flip-flop. The latch allows only one pulse through per
oscillator cycle. Once a PWM pulse is terminated, whether due to
the normal PWM process or due to SHUTDOWN going high, the
pulse cannot start again until the beginning of the next oscillator
cycle. Pulse-by-pulse current limiting is easily accomplished now
because of the latch feature and the completely digital (and
therefore very fast) shutdown circuitry.
Figure 7. Output Sequence With Double Pulse Suppression
The memory flip-flop insures that output pulses always alternate
from the output transistors. This is accomplished by generating
a clock to the toggle flip-flop only if a PWM pulse was generated
during the previous cycle. In the original 1524, the toggle flip-flop
In the first case, the PWM pulses are alternating can BABAB when
a SHUTDOWN signal inhibits the outputs for five oscillator cycles.
When output resumes, the output sequence begins BABAB ... Two
pulses have occurred in succession from Emitter B.
HORIZONTAL: 50j.lSEC/DIV
VERTICAL:
(TRACE 1).5 VOLTS/DIV
(TRACE 2) 10 VOL TS/DIV
12-44
APPLICATION NOTES - SG1524B
With the second controllC, the PWM pulses are again alternating
BABAB when a SHUTDOWN signal is received, again inhibiting
output for five oscillator cycles. When SHUTDOWN is removed,
output resumes but with an ABABA... sequence. The potential
double-pulse from Emitter B has been eliminated by the internal
pulse-steering logic.
This side-by-side pulse-routing problem exists for any PWM
controllC with push-pull architecture and a fully digital shutdown
function. In the original 1524 design, recovery from shutdown was
fairly slow since the error amplifier output was pulled to ground for
turn-off. Turn-on was limited by the 1OO~ output current of the
error amp, the internal compensation capacitor in the current limit
circuitry, and any external frequency compensation components.
This created an inherent soft-start characteristic. With digital
shutdown, the error amp voltage is not immediately affected; the
first pulse out after shutdown can be the same width as before
shutdown, making pulse-routing logic an absolute necessity to
guarantee the safety of the power switches.
illustrates full control of a power supply with a single integrated
circuit, resulting in reduction of overall cost and an increase in
supply reliability through reduction of component count.
The circuit illustrated in Figure 8 is a push-pull, +28V to +5V
converter operating at 50kHz. The power supply is unique in that
the only active component is the SG1524B regulating pulse width
modulator; the only other semiconductors required are diodes.
Output Transistors
Figure 8. A Single IC 50 kHz Push-Pull Converter
In response to requests for greater output drive capability, the
output transistors were redesigned for both higher breakdown
voltage and more current.
In a PWM controller with a single-transistor output structure, the
load driven is frequently one end of a center-tapped transformer
primary winding. Since the maximum collector voltage is 2 x VcC'
the absolute maximum rating of 40V for the earlier device restricted the supply voltage to 20V. Consideration given to the
effects of transformer leakage reactance would reduce this voltage still further. The SG1524B output transistors carry BVCEX
ratings of 60V, high enough for use on a standard +28V supply
bus.
Output device geometry was scaled up to allow reliable operation
at continuous collector currents of 100mA. This represents a
factor of two improvement over the earlier device, which was
characterized at only 50mA. As a further aid to the designer, the
data sheet for the new device specifies maximum saturation
voltage at two continuous current levels: 1OmA and 100mA. The
maximum peak current capability of the output transistors is
200mA for IllS.
The anti-saturation clamp circuit around the output transistors
found in the earlier PWM controller has been retained in the
SG1524B to enhance switching speed. Each output transistor is
also guarded against excessive current byprotective circuitry
which limits the maximum continuous currentto 150mA at +25°C.
DESIGN EXAMPLE
The functional usefulness of a new device is best demonstrated
by study of an actual switcher design. The circuit described
The DC-coupled push-pull configuration was chosen because it is
most sensitive to PWM controller anomalies which cause side-toside imbalance. These include start-up problems such as output
from only one driver until the toggle flip-flop begins to be correctly
clocked by the oscillator. During normal operation, side-to-side
imbalance of volt-second product due to unequal propagation
delays in the IC can cause the onset of sore saturation. Finally,
as outlined earlier, when the digital Shutdown control is activated,
double-pulse sequencing can drive the excursion of the transformer core flux past the saturation knee of the BH loop.
Capacitor C3 acts as a high-frequency bypass for the IC supply
line, while C6 is the high current reservoirforthe power stage. The
oscillator is set for 100kHz with C4 and R5. When divided by two
by the action of the internal toggle flip-flop, this becomes 50kHz
at the power transformer. The +5V reference is filtered against
high frequency noise pick-up by R2 and Cl, and applied to the
non-inverting input of the error amp. The inverting input is
connected to the power supply output terminals to form the
negative feedback loop required for regulation. R3 minimizes the
effects of input offset bias current by equalizing the source
impedance seen by each error amp input terminal. Closed loop
stability is provided by frequency compensation components R4
and C2, using the common technique of cancelling one of the two
poles of the LC output filter with a open-loop zero in the error
amplifier. (4)
In the power section of the supply, the two output transistors are
used to directly drive a center-tapped transformer. A snubber
network consisting of C5 and R6 modifies the inductive load line
seen by each transistor. The transformer itself is wound on a small
ferrite core; turns ratio is 3:1. Rectifier diodes 01 and 02 are
12 - 45
II
APPLICATION NOTES - SG1524B
Schottky junction devices to maximize efficiency at +5V output.
Filtering is provided by L1, wound on a permalloy powder toroid,
and C7.
REFERENCE
The improved common mode range of the current limit amp is
used to good advantage here; current sensing is done directly in
the output line. A foldback ratio of 7.5 to 1 is obtained with the
given values R7, R8, and R9. The divider formed by R7 and R8
applies a back-bias of 1.3 volts, or 6.5 times current limit threshold, when the supply output is at +5.0V. Peak output current
before onset of current limiting is 200mA, and short-circuit current
is only 25mA. Rapid turn-off of the control circuit is accomplished
by closing SW1. R1 and Z1 limit the maximum voltage applied to
the Shutdown terminal to less than +5V.
While capable of only limited output power due to thermallimitations of the 16 pin Cerdip package, the supply amply illustrates the
controller ability to perform all the major control functions required
both tluring start-up, normal regulation, and overload.
CONCLUSION
In the past it was often necessary to incorporate additional
components around the 1524 pulse-width modulator to enhance
its capabilities, and to guard against various functional anomalies.
Economically this was feasible due to the relative cost of the
control device compared to the cost of the peripheral components.
With the occurrence of the usual price decline characteristic of
most integrated circuits, the economic balance has shifted. Many
users now pay more for the necessary support circuitry than for
the 1524 itself.
The availability of the SG1524B now gives the designer another
option. In many instances costly additional support components
can be eliminated and a functionally superior device may be
plugged directly into an existing design, with the benefit of
simplicity, greater reliability, and reduced overall cost.
12 - 46
1. Robert J. Widlar "New Developments in IC Voltage Regulators," IEEE J. Solid State Circuits, VOl. SC-6, pp. 2-7,
February, 1971.
2. A.Paul Brokaw, "A Simple Three TerminallC Bandgap Reference," IEEE J. Solid State Circuits, vol. SC-9, pp. 338393, December, 1974.
3. J.E. Solomon, W.R. Davis, P.L. Lee, "A Self-Compensated
Monolithic Amplifier with Low Input Current and High Slew
Rate," IEEE ISSCC Digest, pp. 14-15, February, 1969.
4. Stan Dendinger, "Digital Current Limiting Techniques for
Switching Power Supplies," POWERCONVERSION '80/
Munich, pp. 3A. 4-1 through 3A. 4-10.
APPLICATION NOTES - SG1525
SILICON
GENERAL
PS-7
LINEAR INTEGRATED CIRCUITS
SYNCHRONIZING THE SG1525A PWM
Stan Dendinger
Advanced Products Development
Silicon General, Inc.
1. Synchronizing One Device to an External Clock
A. Program the SG1525A oscillator with RT and CT to free-
A. Program the master unit for desired frequency with RT, Cp
and RD' Connect the CTpin of the master to the CTpin of the
slave, and the OSC pin of the master to the OSC pin of the
slave. Leave the RT and DISCHARGE pins of the slave
open.
run at a frequency 10% slower than the external clock frequency.
B. Drive the SG1525A SYNC terminal (pin 3) with the external clock. Input impedance is 2K. The clock amplitude
should be greater than 2 volts and less than 5 volts. Pulse
width should be at least 300nsec. for reliable triggering,
but it should not exceed the free-running oscillator clock
pulse width by more than 200nsec.
B. Program the master unitfor desired frequency. Program the
slave unit to free-run 10% slower than the master. This is
best done by choosing CT and RD to be the same as the
master, and by increasing the value of RT' Drive the SYNC
pin of the slave with the OSC pin of the master.
2. Synchronizing Multiple Devices to an External Clock
4. Synchronizing Multiple SG1525A to a Master SG1525A
Two different methods are recommended, depending on the
distance between the various SG1525A PWMs. Use method A
if the ICs are within 3 inches of each other and on the same
printed circuit board. Otherwise, use method B.
Again, different techniques are recommended depending on
the physical and electrical distances between the various PWM
circuits. If all of the devices are separated by no more than 3
inches each, and on the same pc board, then the "cluster"
technique described in section 3A (i.e. sharing a master unit's
CTand OSC waveforms with adjacent slave units) will give good
results.
A. Designate one of the SG1525A PWMs as the master unit
and select RT, CT, and RD to free-run 10% slower than the
external sync frequency. Connect all pins together and all
OSC pins together, leaving RT pins and DISCHARGE
pins open on the slave units. Drive the SYNC pin of the
master with a clock pulse as described in Section 1B
above.
If one or more of the devices are remote from the master so that
the CTnode cannot be distributed without the possibility of noise
pick-up, then each remote unit must be synchronized as described in Section 3B above. Note that it is possible to cluster
remote units to decrease the required number oftiming components. In other words, iftwo or more units are close together at
one remote location, one of them can be programmed for the
required 10% slower free-run frequency, and its CT and OSC
waveforms can be shared with its neighbors.
B. Program each ofthe separate devices with RT, Cp and RD
to free-run 10% slower than the external sync frequency.
Drive each of the SYNC pins with the clock described in
Section 1B. (This arrangement avoids routing a highimpedance line [CTl around a noisy environment.)
3. Synchronizing One Slave Unit to a Master SG1525
As in Section 2, two methods are advised, depending on the
distance between the master unit and the slave. Use method
A for short distances, and method B otherwise.
This description covers all the possibilities normally encountered.
NOTE THAT IT IS ALWAYS GOOD ENGINEERING PRACTICE
TO GROUND ANY UNUSED SYNC PINS TO ELIMINATE THE
POSSIBILITY OF NOISE PICK-UP.
January 1990
12 -47
II
12 -48
APPLICATION NOTES - SG1526
SILICON
GENERAL
PS-8
LINEAR INTEGRATED CIRCUITS
DIGITAL CURRENT LIMITING TECHNIQUES FOR
SWITCHING POWER SUPPLIES
Stan Dendinger
Advanced Products Development
Silicon General, Inc.
ABSTRACT
This paper explores the performance benefits gained by digital techniques for current limiting in switchmode power supplies. The necessary control architecture is described along with the several possible
modes of operation. Characteristics of several actual supplies using these techniques are presented.
SUMMARY
Techniques for protecting switching power supplies against
excessive output current demands have traditionally borrowed
the analog approaches of linear voltage regulators. In many
instances, the resulting performance has been unsatisfactory.
Problems such as degraded load regulation, poor response to
overloads, and oscillation at the crossover point between
constant voltage and constant current output are frequently
encountered.
continuously compares a fraction ofthe supply output voltage with
a precision reference voltage. The comparator output is a fixedfrequency, variable duty cycle pulse which drives a power switch.
The power switch in turn chops the DC input voltage at some
ultrasonic frequency. An output filter smoothes the bursts of
energy into a low ripple DC voltage at the output terminals.
L1
A brief analysis of the properties of two coupled closed-loop
control systems provides some insight into the basic limitations of
the analog approach to current limiting. Specific examples using
several currently available pulse width modulator circuits are
shown.
)-..-.fYYY'L.t---O VOUT
~
VOUT=
An evaluation of the benefits of a digital approach shows that with
the proper control architecture, all of the limitation imposed by
analog techniques can be removed, with subsequent benefits to
the power semiconductors. The impact on power device load
lines and improvement in current limit characteristics are
examined. Waveforms from operational switching supplies
illustrate the practical applications of the principles discussed in
this paper.
BACKGROUND
The architecture of almost all fixed-frequency, constant output
voltage switch-mode power supplies can be reduced to the simple
configuration in Figure 1. A sawtooth waveform is compared with
the output voltage from an error amplifier, which in turn
~O~~~OF~\-jN
Figure 1. Basic Architecture of a Constant Voltage
Switching Power Supply.
Under heavy loading, the voltage control loop forces the pulse
width modulator to maximum duty cycle. In order to limit the
maximum current flow and reduce operating stresses on the
power components, it is necessary to limit the energy transfer
through the power switch. The usual method in the past has been
to establish a second feedback control loop. An overcurrent
condition is sensed and the pulse width is reduced by overriding
the voltage control amplifier, as shown in Figure 2.
January 1990
12-49
•
APPLICATION NOTES - SG1526
...
" ,,---
---,
" u-..,. . . __-'
"
r---+--~--~~,
NONINVERTlNG
INPUT
IN'lERTlNG
INPUT
NONIN'JERTlNG
INPUT
IN';[RTlNG
INPUT
Figure 2. The Basic Switching Supply Modified for
Analog Current Limiting.
B. Texas Instruments TL494
In this configuration, a voltage amplifier with a fixed threshold or
offset voltage derives a differential input signal from a current
sense resistor in series with the supply output terminal. As the
output current approaches the pre-determined limit, the amplifier
enters its linear gain region, and its output voltage becomes
increasingly negative. Diode D2 begins to conduct, clamping the
error amp voltage to a low value and reducing the duty cycle ofthe
pulse width modulator.
Examples
This method has been a popular solution to the problem of
providing overcurrent protection. Figure 3 shows the control
architecture of four integrated PWM circuits, all of which employ
this analog approach.
C. Ferranti ZN1066
m
"
Despite the popularity of this technique, experience has shown
thatthere are significant problems which result in degraded output
regulation when compared to ideal current limiting characteristics.
As shown in Figure 4, the supply voltage should be constant over
~·~'~I~·'~
,J,
,J,
r
"
;:MJ-j~
~
L,
~
·rr
,
",
.01---{])4 +StNSE
GROUND
~
-~
m
.
'1
,J,T
"r;--~
D. NEC Electron ILPC1042C
'~----~-1------<
(SUBSl1lAT£)
:. 1,r
1./
~~
®-----j
Figure 3. Four Pulse Width Modulator Circuits
with Analog Current Limiting
~
A. Silicon General SG1524
the full range of rated output current. At some excess current
level, the supply should make a sharp transition to a current
source. In actual practice with an analog current loop, load
12 - 50
APPLICATION NOTES - SG1526
regulation is degraded as the output current approaches the
maximum rating. Furthermore once transition to current limiting
has occurred, appreciable excess current can flow under short
circuit conditions.
If the ratio of chopper frequency to the cutoff frequency of the
output filter is at least 20, then the pulse width modulator may be
modeled simply as a linear gain block. Its transfer function is given
by:
a(s)=~
IDEAL iCURREJT LlMITliNG
100
..........
I
Cl
«
N
75
-"
0
>
:::J
50
[L
f-
:::J
ACTUAL CURRENT LIMITING
0
1-
25
o
s is the complex frequency variable a + jOl
a(O) is the DC open-loop voltage gain
Sc is a double pole at s= _ 1
v'LC
~
f-
f-
where
I
~
w
(Eq.1)
(1-s/s c)2
125
o
~
~~
~~
~~
20
40
60
80
100
OUTPUT CURRENT -
120
A. ERROR AMPLIFIER
o(s)
140
%
=
0(0) (l-s/SB)
(l-S/sA)
1
WHERE s A IS A POLE AT s = - ROCl
Figure 4. Load Regulation Characteristics of Supplies
with Analog Current Limiting.
WHERE s B IS A ZERO AT s
The reason for this non-ideal behavior is found in the finite loop
gain of the current limit amplifier. Not only must the loop gain of
the voltage control be opposed, but also the non-abrupt
conduction ofthe clamp diode must be compensated. Higher gain
can narrow the difference between actual and ideal performance,
but at the risk of oscillation at the crossover point between
constant voltage and constant current. To understand why this is
true, we must analyze the frequency behavior of the gain
elements in the two control loops.
= -
1
Rl Cl
B. PULSE WIDTH MODULATOR
o(s) =
Analysis of the Stability Problem
0(0)
WHERE s C IS A DOUBLE POLE AT s
The three gain elements are the error amplifier, pulse width
modulator, and current limit amplifier. The following notation is
used: open-loop gains and frequencies are designated by lower
case letters (a(s) , Sb). Closed-loop gains and frequencies are
denoted by upper case letters (T(O) , 8,). The frequency
compensation connections shown apply to the 8G1524 and other
transconductance amplifiers.
The same compensation
principles, however, also apply to low-impedance output
amplifiers, where the feedback network is connected between the
output and the inverting input terminal.
:!>-o
C. CURRENT LIMIT AMPLIFIER
0(5)
=
0(0)
(1-5/50)
WHERE sO IS THE SINGLE DOMINANT
OPEN-LOOP POLE
Figure 5. Open-loop Gain Characteristics of the Three Gain Elements.
12 - 51
II
APPLICATION NOTES - SG1526
The error amplifier open-loop response is determined by external
components C1 and R1 (Figure 5), since it is a transconductance
amp with output impedance Ro' To obtain maximum closed-loop
bandwidth for the voltage control loop, the designer must
compensate the amplifier so ihai ii exhibits an open-loop zero
which cancels one of the poles of the low pass filter in the pulse
width modulator.
response time) then the paths of the poles sa and Sc in the voltage
loop will curve towards the jOJ axis, as shown in Figure 7. It can be
seen that the net effect of coupling is that, for sufficiently high loop
gain, the closed-loop poles 8, and 8 2 will cross over into the right
hand plane, resulting in oscillation at the supply output.
jw
x..51__
~
1.0
51
~
~---"
\
\
\
\
Q ~
0.707
"-
\
"-
Q ~0.5~
5;:5~
\
5D
"- \
"- \
"-
S'/-;
5c
"
/
/
/
//
- v--...
jw
Q
x--
/
/
"
~
52
/
/
/
Figure 7. Movement of the Closed-loop Poles of the Voltage Regulation
Loop Towards the Right Hand s-plane due to "Pole Mingling"
52
Figure 6. Trajectories in Complex Frequency Space of the Open-loop
Poles and Zeroes of the Error Amplifier and Pulse Width Modulator as
the Feedback Loop Gain is Increased.
The locations of the open-loop poles and zero for the voltage
regulation loop appear in complex frequency space as shown in
Figure 6. The dominant (lowest frequency) pole of the error
amplifier (s.) , the open loop zero (s,), and the two pulse width
modulator poles (sc) all lie on the negative real axis. Since there
is a pole-zero cancellation, the net open-loop frequency
characteristic is that of a two pole system, i.e.
a'(s) _
a' (0)
=
a' (0)
- (1-s's.) (1-s/sJ
1+a,s+a2s 2
One method frequently used to stabilize the supply is to
narrowband the current limit amplifier. For the case where
(Eq.3)
the closed-loop poles are forced away from the jOJ axis as the
loops become coupled together, and no instability occurs. This
condition is shown in Figure 8.
jw
(Eq.2)
------------------------~----+------"
When feedback is applied around the regulator, the poles move
in complex frequency space along the trajectory shown. For low
values of loop gain, the dominant poles remain real. When the
loop gain T(O) exceeds (a: /4a2)-1, the poles become complex.
They then follow a path parallel to the jOJ axis as T(O) increases.
Note that the poles of the closed-loop transfer function always lie
on the left hand plane, and so there is no stability problem.
However if Q is much greater than unity the transient response
may be unacceptable because of severe ringing.
At the transition point between voltage regulation and current
regulation, the situation is quite different. The two feedback loops
are now coupled together and oppose one another. A three pole
system now exists, since the current limit amplifier now
contributes a pole at Sd' so the positions of the poles in the s-plane
are altered. If the bandwidth of the current limit amplifier is
designed to be large (and ideally it should be to obtain rapid
Figure 8. Movement of the Closed-loop Poles
2
forsd
f-
:::J
50
0f-
:::J
-«i!1~' [\";I
~ER
LAR
0
25
MOSFET
QRETURN
o
o
20
40
60
80
100
120
140
OUTPUT CURRENT - %
Figure 11. Theoretical Current Limiting with Bipolar and
Power MOSFET Devices.
•
APPLICATION NOTES - SG1526
The excess current "tail" may easily be eliminated by foldback
current limiting. This technique pre-biases the current limit
comparator away from the threshold point with a fraction of the
supply output voltage (Figure 12). As the supply voltage goes into
During turn-on, distributed capacitance in the transformer primary
winding causes current overshoot. During turn-off, leakage
reactance contributes some collector voltage overshoot.
current limit, the output voltage falls, reducing the bias on the
_
comparator. Less current is then required through Rse to maintain
limiting. Finally, atfull short circuit only a fraction of the full output
current is available, even with the "tailing" phenomenon.
-
NORMAL TRAJECTORY
.. -
CURRENT OVERLOAD
IMAX I----~-+--..---Io::::--.-_I
fZ
\
W
~ INORMAL I'"-..",;tr-....I""",j""f-.....;::----+-~__l
U
100
~
w
'"
...:
75
f-
a
w
--'
/
R,
a--'
u
RETURN
>
=>
u
I
·2
--'
f-
~- V
n+
'"2
50
o
Q..
f-
li(
=>
a
!
25
POWERT
MyFET
o
o
20
40
60
Vc
COLLECTOR -
2VC
EMITTER VOLTAGE
Figure 13. Prevention of Overeurrent in the Power Switch During
Cyele-by-Cycle Current Limiting.
BIPtAR
80
o
100
OUTPUT CURRENT -
120
140
During a switching cycle where an overload exists, the collector
current rises rapidly due to the low collector load impedance
reflected from the power transformer secondary. Before the
current can reach a destructive level, the conduction cycle is
terminated, protecting the switching device from catastrophic
failure due to damaged metalization or vaporized wire bonds.
However, the collector voltage overshoot during turn-off is now
greater due to the increased energy stored in the leakage
reactance at higher current levels.
%
Figure 12. Reduction of Maximum Current Using
Foldbaek Current Limiting.
The design equations for foldback limiting are straightforward:
(Eq.4)
It can be concluded from the foregoing that pulse-by-pulse current
limiting will protect the power devices from failure due to
excessive current levels, but it offers no protection against
abnormal leakage reactance voltage spikes. Their magnitude
may be limited dueto the impOSition of a maximum value of current
at turn-off, but some type of snubber network or other transient
suppressor may still be required.
where V'Tll is the comparator threshold voltage
(Eq.5)
Impact on Load Lines
Pulse-by-pulse current limiting also has a beneficial effect on
switching device load lines. Data was collected on load line
excursions of a 40kHz forward converter, with line results shown
in Figure 13. The forward configuration was chosen rather than
a flyback design because the output current is always in phase
with the conduction of the principal power transistor. Thus load
changes at the supply output are instantaneously reflected back
to the load line excursion.
It is also apparent that device power dissipation is higher than
normal during overload conditions. To avoid thermal damage an
eventual transition from pulse-by-pulse limiting to "hiccup" mode
current limiting may be desirable. "Hiccup" mode limiting occurs
by discharging the PWM soft-start timing capacitor, causing the
controller to turn off for several hundred milliseconds before
resuming operation. An elegant method for contrOlling this
transition by "fault counting" will be described at the end of this
paper.
The normal load line trajectory indicates some deviation from the
theoretical path due to non-ideal transformer characteristics.
12 - 54
APPLICATION NOTES - SG1526
A Bipolar Example
To verify the actual limiting characteristics of a switch mode
supply with digital current limiting, the 30kHz buck converter in
Figure 14 was constructed. Almost all the control circuitry is
contained within two integrated circuits and a power hybrid. The
SM625 is a 60 volt, 15amp bipolar switch with matched
commutating diode. It is controlled by an SG1524 pulse width
modulator. The 2N2222 transistor provides constant current drive
to the power switch over a wide range of input voltage.
power MOSFETS, and an SG1526 pulse width modulator IC
which incorporates the digital current limiting principles discussed
earlier.
100
~
~
w
'-'
«
75
I..J
0
>
I::::l
0..
I::::l
50
0
25
o
o
~
20
40
60
80
100
OUTPUT CURRENT -
120
140
%
Figure 15. Output Characteristics of the Buck Regulator in Figure 14.
Figure 14. Buck Converter with Digital Current Limiting Using an
SG1524 PWM and SG1549 Current Sense Latch.
Pulse-by-pulse current limiting is provided by an SG1549 Current
Sense Latch. This circuit consists of two voltage comparators and
a sel/reset latch with Q and Q digital outputs. Both comparators
have a 1OOmV threshold voltage. One device has full differential
inputs with a common mode range from +2 to +40 volts. The
second comparator has its 1OOmV threshold referred to ground,
and is intended for sensing the voltage in an emitter resistor. This
current sense configuration is desirable in forward and push-pull
converters where secondary current overloads can be sensed by
the reflection to the primary of the transformer. The two
comparator outputs are ORed together at the SET terminal of the
latch. A clock pulse from the oscillator output of the SG1524 is
used to reset the latch. Maximum turn-off speed is obtained in this
circuit by disabling the 2N2222 at its base with the open-collector
LOW output of the SG1549.
The block diagram of the PWM circuit (Figure 16) illustrates the
differential voltage comparator, AND gate, and data latch that
compromise the components for pulse-by-pulse current limiting.
The comparator has a 1OOmV threshold and 20mV of hystereSiS
to minimize jitter at the decision point. The data latch allows only
one pulse to pass through per each oscillator cycle. The memory
flip-flop provides the double-pulse suppression logic. If the PWM
pulse is gated off for more than one cycle, the flip-flop remembers
which driver was the source for the last pulse. When the output
is again enabled, the first pulse is automatically routed to the other
driver. This prevents two pulses in succession from one driver,
minimizing the possibility of transformer core saturation in pushpull configurations.
Figure 15 shows the output voltage/current curve obtained with
this regulator. The data points agree remarkably well with the
theoretical curve for bipolar devices shown in Figure 11. The
supply exhibits excellent load regulation (20mV) all the way to
maximum load current, with a sharp, well-controlled transition to
current limiting.
A MOSFET Example
To further illustrate the performance obtainable with present high
performance switch mode power supply components, a 100kHz
off-mains supply was designed with full input-output isolation,
12 - 55
Figure 16. Block Diagram of the SG1526 Pulse Width Modulator
•
APPLICATION NOTES - SG1526
The complete schematic of the power supply is shown in Figure
17. A half-bridge configuration was chosen to minimize the drainsource breakdown voltage requirements on the power MOSFETs
when op'erating from the rectified 220 volt European mains.
Power for the SG1526 pulse width modulator is derived from a
small (3 Watt) 50Hz power transfo'rmer. This arrangement
maximizes supply efficiency and allows the voltage regulation
loop to be referenced to the output ground. The two MOSFETs
are driven from the secondary of a small ferrite pot core isolation
transformer. The primary of the transformer is connected directly
to the totem-pole output drivers of the SG1526. The oscillator is
programmed for 200kHz by Rr and Cr and the current sense
network is designed to give a 7 to 1 foldback ratio.
The propagation delay through the overcurrent control loop is of
major importance when attempting pulse-by-pulse limiting at
100kHz. As Figure 19 indicates, the response time through the
SG1526 from comparator to driver output is only 300
nanoseconds. Since this represents only 6% of the maximum
duty cycle at 100kHz, a large fold back ratio is possible.
Data taken on the current limiting characteristics ofthis supply are
shown in Figure 20. As expected, the output voltage regulation
was completely unaffected by the current limit circuit until
maximum load current had been exceeded. Also, the available
output current steadily decreased as the overload increased, as
would be expected from Figure 12. However, there was no
current "tailing" effect from the loop propagation delay. The
explanation appears to be that under prolonged pulse-by-pulse
current limiting the power dissipation in the power MOSFETs is
sufficient for the negative temperature coefficient of
tran1lconductance to override the effect of loop delay.
II, ,.11
I'"
V'h
,
20V
10V
Figure 17. A 100 KHz Oof-line Power Supply Using the
SG1526 for Digital Current Limiting.
OV
Operational waveforms for the supply when operating under
partial load are shown in Figure 18. The two traces show the
unipolar gate drive signals at the pulse width modulator; these
become bipolar when observed on the secondary of the isolation
transformer. Transition edges are sharp and clean due to the
totem-poles' ability to source or sink 200mA peak for charging and
discharging the power MOSFET gate capacitance.
nME BASE: 5 nSEC/DIVIS10N
UPPER WAVEFORM: OVER CURRENT SIGNAL TO
CURRENT SENSE COMPARATOR
LOWER WAVEFORM: SG1526 DRIVER OUTPUT
Figure 19
125
20V r---~--'---'---'----r---r---r--~---'---'
100
~
'I
w
'"-"
«
75
f-
0
>
f:::J
/
50
"f-
:::J
0
25
o
TIME BASE: 5!"5EC/DIVISION
UPPER WAVEFORM: DRIVER A OUTPUT
LOWER WAVEFORM: DRIVER B OUTPUT
/
o
20
V
40
/
I
/
/
/
60
80
120
120
OUTPUT CURRENT-(%)
Figure 20. Measured Output Characteristics of the 100KHz
Switching Supply in Figure 17.
Figure 18
12-56
APPLICATION NOTES - 8G1526
Fault Counting Technique
Fault counting may be utilized to reduce power dissipation in the
One
power switch during prolonged current limiting.
implementation is illustrated in Figure 21, using an inexpensive
CMOS ripple counter and an even less expensive timer circuit.
The 14-bit binary counter accumulates pulse-terminating
commands from the SG1526 comparator. The output of the 14th
stage will go high after 2 '3 or 8192 counts have been accumulated.
At 200kHz (an overcurrent SHUTDOWN pulse can occur during
either phase of the output) this represents 41 milliseconds of
delay. When the counter output goes HIGH, the soft-start timing
capacitor of the SG1526 is discharged. The SG555 timer is
connected as an oscillator to periodically reset the accumulated
count in the MC14020B, which allows a soft-start cycle to begin.
A period greater than 41 milliseconds should be used.
Obviously this technique can be extended even further. Asecond
counter could accumulate "hiccup" cycles and shut the supply off
until manual reset or power re-cycle. This is easily accomplished
with the SG1526 since the SHUTDOWN and RESET terminals
are compatible with both TTL and CMOS logic.
DIGITAL CURRENT LIMITING
• Fast
• No Load Regulation Degradation
• Clean Crossover from Voltage to Current Output
• Multiple Current Limiting Modes Possible
Conclusions
The use of digital current limiting techniques provides enhanced
load regulation, a sharp transition to constant current, and faster
protection to the power semiconductors in a switch-mode power
supply when compared to analog methods. It also offers the
designer flexibility in the choice of crossover criteria from pulseby-pulse mode to "hiccup" mode to total shutdown. The net
benefit to users will be enhanced reliability and increased
performance from switch-mode power supplies.
TO DATA
LATCH
REFERENCES
1. Pederson, D.O: "Electronic Circuits," pp. 341-361, McGrawHill, Inc.
+Vcc
2. Middlebrook, A.D. and Cuk, S.: A General Unified Approach to
Modeling Switch Converter Power Stages," IEEE P.E.S.C.,
Record, June 1976.
Dl
MC14020B
3 014 14 BIT BINARY CK
COUNTER
SG555
llMER
Mammano, A.A.: "Improving Switching Regulator Dynamic
Response," Powercon 4/Boston, 1977.
OUT
Figure 21. Using CMOS Logic as a Fault Counter to Control Transition
from Pulse-by-Pulse Current Limiting to "Hiccup" Mode Current Limiting
4. Perkinson, J.: "Minimizing Power Loss in Switchmode Power
Supplies ..." POWER CONVERSION '79/Munich.
..
12 - 57
12 - 58
APPLICATION NOTES - SG1526
SILICON
GENERAL
PS-9
LINEAR INTEGRATED CIRCUITS
FETs ENHANCE SWITCHED-MODE DESIGNS
ABSTRACT
Switched-mode power supplies are well known for their high levels of efficiency and for their
compactness. Further improvements can be effected by employing power MOSFETs in place of
conventional bipolar transistors. A practical design for a 5V, 20A supply is suggested utilizing the
SG1526.
Many of the basic design concepts relating to power MOSFETs
were outlined in an earlier article "Designing with power
MOSFETs," which was published in the March, 1982 issue of
Electronic Product Design.
~~~~~--~---o~
ii;
...
~
~~~~--+-~---o5
Now let us apply some of the driver techniques discussed in the
earlier article, to a 100kHz, 1OOW switched-mode power supply.
Fig. 1 shows the circuit which is truly universal in that it operates
directly from a mains voltage spanning 85V to 265V r.m.s. without
any mechanical switching requirements. And furthermore, it is
able to perform this task over a wide frequency spread, typically
from 50 to 400Hz.
15V
SIMPLICITY OF DESIGN
At the centre of the design is a 500V, 3A power MOSFET (Q1)
which converts the rectified mains voltage into a tightly-controlled
1OOW d.c. output. Apart from the indicated rectifiers and Zener
diodes, the power FET and its regulating pulse-width modulated
driver Ie (SG1526) are the only active devices needed to achieve
a full-load efficiency of 74 per cent with ±0.5 percent regulation.
This particular design has a maximum output current of 20A d.c.
at 5V with a maximum ripple of 50mV pk. -pk. Transient response
for a step change of 10A load current is 500mV, settling within
250jls.
MORE EFFICIENT
For a given combination of voltage and current ratings, power
MOSFETs can generally switch more efficiently and at much
higher frequencies than their bipolar counterparts. Because
power MOSFETs can be operated at higher frequencies, smaller
transformers and filter capacitors can be used leading to more
compact designs. The circuit shown in Fig. 1, for example,
operates at 100kHz, some two and a half times faster than most
circuits using bipolar transistors.
R.,
()
::;
o
t--__-+--__-<>e:
Figure 1. Versatile 100W Switched-Mode Power Supply Offers 20A
Output with 75 Percent Efficiency and a Tight Performance Spec.;
See Text for Details.
The higher operating frequency also enables the circuitto recover
much more quickly from severe line or load variations. This is
especially important in situations where a system's power-up
signal is used to reset a large number of logic devices simultaneously.
Driving a power MOSFET is in most cases much easier than
driving an equivalent bipolar device, it being voltage rather than
current driven. Some gate drive is of course required, but at a
much lower level than that associated with similarly-rated bipolar
devices.
January 1990
12-59
•
APPLICATION NOTES - SG1526
MODIFICATIONS
The power MOSFET is not directly compatible with the bipolar
power transistor and cannot be used in a switched mode circuit
without modification.
Irrespective ofthe power switching device used, be it a MOSFET
or a bipolar powertransistor, the associated pulse-width modulated switcher cannot normally be left on for more than 50 per cent
ofthe total duty cycle. Under normal circumstances, a 50 per cent
on time occurs only when the input voltage is very low and the
output current is high. Conversely, the shortest on times occur
when the input voltage is near to its peak and the output current
is minimal.
Ideally, the pulse-width modulator should operate over a very
wide duty cycle range to ensure close regulation with wide line and
load extremes. Unfortunately, it has been impracticable to implement this approach in bipolar designs, since the gain of bipolar
transistors decreases rapidly when operated in the short-pulse,
high-current mode.
A power MOSFET's transconductance, on the other hand, does
not vary so widely with current changes. This makes it much
easier to drive a MOSFET directly, using a short duty cycle.
Furthermore, the short conduction time at high input voltage
leaves a relatively long time to reset the associated transformer
and thus reduce the peak voltage across the MOSFET. Also the
designer is able to use 500V rated devices in mains driven
supplies in contrast to the usual 800V rating often needed for
circuits featuring bipolar devices.
The resister/capacitor/diode snubber formed by R/C:lDa conforms in the prinCiple to the approach outlined in the earlier article,
except that it is allowed to float. For more details on this and other
related topics, refer to lriternational Rectifier's application note
AN-939.
Trials have shown that worst-case efficiency occurs at virtually
maximum input voltage with minimum loading. Here efficiency
drops to just under 70 percent, compared with 76 percent at
maximum output. Dissipation is thus around 8W at maximum
output and slightly higher than this value when the supply is lightly
loaded.
OPERATION
The off-screen photographs show how the circuit functions. Fig.
2 demonstrates how the pulse-width modulator controls the
MOSFET's conduction time with respect to various load and line
conditions. At one extreme, the input voltage is down to 85V, while
output is at 20A. Fig. 2a shows the MOSFET on for 4vs which
gives a duty cycle of approximately 44 percent. When operating
at the other extreme, ie 265V input and 5A output, the MOSFET
is on for approximately 1us, which corresponds to a 10 percent
duty cycle. Note how the gate/source waveforms which are
depicted in Fig. 3 relate to the operating levels shown in Fig. 2.
-
IOV
-
IOV
'"
r-
-'
PROTECTION
Some protection is of course necessary. The MOSFET shown in
Fig. 1, for example, features clamping diodes (Zener'diodes 1 and
2) to limit the circuit's maximum gate voltage to 18V. Zener 3
which comprises four series-connected 120V diodes, restricts the
source/drain swing to 450V to give a safe working margin.
-
SOOmV
r-~
r- r-
2/ls
2/ls
10 mV
I
1
'v
(o)
Figure 3. Gate/Source Waveforms. These Were Recorded with the
Unit Under Full Load. (a) with a Line Voltage of 85V and (b) with a Line
Vc;>ltage of 265V. The Upper Traces Show Gate/Source Voltage While
the Lower Show Drain Voltage.
,.
500m~
,...,
I-
Ir
1
L
~
IV
I
2/ls
10
2/ls
V
'\
(
(
"r-
I
1v
1V
IV
(0)
(o)
(b)
(e)
(d)
Figure 2. Switching Waveforms. With an 85V Line and' a 20A Load (a) Shows Drawn Current on the Upper Trace and D(ain Voltage on the Lower.
The Load is Cut to 5A in (b), While (c) and (d) Show the Same Parameters at a 265V Line Voltage with Respective Loads of 20A and 5A.
12 - 60
APPLICATION NOTES - SG1526
Typical voltage waveforms across the output rectifiers are shown
in Fig. 4. Note that while the forward rectifier 01 blocks a peak
voltage (including the commutation transient) of about 12V, 02
has to withstand around 75V for a 5V output, due to the short
conduction cycle. Both of these diodes contribute to the system's
net losses. Indeed, these devices dissipate some 30 to 50 percent
of the switching energy, and represent a major problem in designing low output voltage power supplies. Losses from the rectifier
diodes are approximately the same for both the 5 and 15V supply
designs.
f I'' }
II f Illl ~ Bovill H III ~
w
w
II20vlll§ III, I9 blJ II § III ~
(0)
TRACE
(d)
HOR(ZONTAL
2J1. SEC/DiV
Figure 4. Output Circuit Waveforms. The Upper Traces Show the
Voltage Waveform Appearing Across 01, While the Lower Covers
Rectifier 02. In Both Cases, Load is at 5A; (a) with the Input
Voltage at 85V and (b) at 265V .
•
12 - 61
12 - 62
SILICON
GENERAL
APPLICATION NOTES - SG1525A/SG1526/SG1527A
PS-IO
LINEAR INTEGRATEO CIRCUITS
POWER SUPPLY CIRCUITS HEAD FOR SIMPLICITY
BY INTEGRATION
Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
SUMMARY
The benefits obtained from switching power supplies have become universally recognized by power systems engineers in the
past several years. However, there has been a simultaneous
realization that, too frequently, gains in efficiency and reductions
in weight have been accompanied by an escalating component
count and a decrease in reliability and predictability of performance. To effectively solve these problems, integrated circuit
manufacturers have recently designed new products specifically
for switchers. These devices offer the proven advantages of
monolithic technology: compactness, accuracy, reproducibility,
higher performance through reduction of parasitics, and the
economies of mass production.
This paper reviews the circuit simplifications made possible by
these specialized devices, as typified by the first practical switching regulator control chip, the SG1524 Pulse Width Modulator,
and later by other circuits such as the ZN1 066, the TL494A, and
the MC3420. A second potential area of power supply simplification is the interface between the control circuit and the high power
switching transistors. Two specialized driver circuits, the SG1627
and the SG1629 are described which provide high-level turn-on
and turn-off signals for efficient switching. Finally, some second
and third generation pulse width modulator designs will be discussed. These later devices, designated the SG1525/27 series
and the SG 1526, offer even higher levels of control function
integration compared to earlier designs. The SG1526 in particular
integrates a number of protective control features which substantially increase the reliability of the power semiconductors in "real
world" switching power supplies.
Each of these elements has been available in integrated circuit
form for years, with the well-established benefits of reduced
physical size, greater reliability, and increased performance. In
light of this background, the development of a single monolithic
circuit for switching power supply control appears to be a logical
progression.
One of the first devices available to power supply designers was
the SG1524 Pulse Width Modulator from Silicon General. This
circuit, shown in Figure 1, contained all of the basic control
elements required for a switching regulator. In addition to providing the four basic control elements, the device allowed for pushpull configurations by inclusion of a toggle flip-flop and dual
alternately-gated output transistors. Finally, provision was made
for some abnormal power supply operating conditions. An analog
current limit circuit and a digital shutdown control were included to
provide protection against short circuits and other load faults.
+5VTOALL
INTERNAL CIRCUITRY
"
HISTORICAL PERSPECTIVE
A basic pulse width modulated switching power supply requires
only four control elements: a precision reference voltage, a ramp
oscillator, an error amplifier, and a differential voltage comparator.
January 1990
12-63
Figure 1. SG1524B Pulse Width Modulator Block Diagram
..
APPLICATION NOTES - SG1525A/SG1526/SG1527A
Despite this level of complexity, the device was easy to understand and was quite flexible. As a result, since its introduction in
1976, the SG1524 has been very widely accepted within the
power supply industry, finding its way into a majority of new
designs, including exotic applications in communications satellites and the space shuttle program.
units. Since this capacitance must be charged and discharged by
10 or 12 volts in 10 to 20 nanoseconds, high peak currents are
required. At switching frequencies of 200kHz, considerable
dynamic power dissipation is required ofthe drive circuit to obtain
the high speed switching benefits of these devices.
POWER DRIVER INTEGRATION - SG1627
As experience was gained in applying the SG1524, it became
apparent that there was a gap between output power capabilities
of the control integrated circuit and the drive levels required by the
power semiconductors. Two areas were identified within most
supply configurations where specialized driver functions could be
successfully implemented with monolithic technology.
An Integrated Source/Sink Driver
The first design is a dual500mA totem pole driver with externally
programmable current sourcing. Both inverting and noninverting
logic inputs are available, and may be driven by either an opencollector control circuit or (with a diode) by TTL logic. Connections
to the high current output transistors are brought out separately,
allowing maximum flexibility when interfacing with standard bipolar transistors, the new VMOS power FET's, and transformers.
Figure 3. Driving Bipolar Junction Transistors With a
Totem-Pole Switch Driver
In Figure 4, peak currents in the output stage are limited by R2 ,
while R, helps minimize power in the SG1627. With some power
FETs, a 1000hm resistor in series with the gate lead may also be
necessary to eliminate device oscillations.
To SideS
+Vcc
R,
1K
Source
Collector
VIN
I~V;~: 0----1--+--1--+
NOI1I~~UYt
0----1-,---1
01
6V
02
6V
=
+15V
1/2 SG1627
+-*--<-------o~~~rs~)soost
,-----<>---1
Sink
Collector
J
SInk
Emitter
POWER
'0-----¢-~O-_l~ ~WITCHING
i
Figure 2. Partial Schematic Diagram SG1627 Driver Circuit
Power Bipolar Drive is accomplished with the connection shown
in Figure 3. R2 controls the magnitude of forward base drive, and
is selected to develop a voltage drop of one V BE when the output
Darlington pair is sourcing 350mA. At the same time R3 develops
a 3.5 volt differential, which is stored by C1. During turn-off, sink
transistor 09 saturates, pulling the outputterminal to ground. The
emitter-base junction becomes reverse biased from a low impedance source, allowing stored base charge to be rapidly extracted.
Power FET Drive is possible with a minimum of external components. The source/sink capability ofthe SG1627, together with its
fast edge speeds, makes it an ideal driver for power MOSFET
devices. Although MOSFETs have negligible DC gate current,
input capacitances of 800,-1000pF exist in the higher current
ET
Figure 4. A Source/Sink Driver Provides the Peak Currents
Required by Power Fet's at High Switching Frequencies
Transformer Drive is the third interface area where an integrated
power driver can eliminate components. Most bi-phase transformer drive circuits using grounded emitter transistors require
additional components to resetthe magnetic flux to zero every half
cycle. This is necessary to insure that no net DC excitation is
applied to the transformer primary over many cycles of operation,
thereby avoiding core saturation. These additional components
12 - 64
APPLICATION NOTES - SG1525A/SG1526/SG1527A
may include extra transformer windings, clamp diodes, and antiphase driven clamp resistors. A much less complex circuit can be
achieved with the SG1627, as shown in Figure 5.
N.I.
INV
L
completes the circuitfor returning base drive current. Atthe same
time, external storage capacitor Cs is charged to a negative value
through the high current rectifier diode in the switch driver. When
the secondary voltage is driven to zero, the rectifier diode becomes reverse biased. The resulting positive drive turns on the
Darlington sink transistors, which reverse-biases the base-emitter junction of the power device through the storage capacitor. A
large negative current spike results, minimizing the turn-off time
and power loss in the switching transistors.
SG1629
ISOLATED
LOAD
ro
INV.
TRANSFO~~~~
SECONDARY
II r-_+_________
POWER
SWITCHING
-+_t--_+'lTRANSISTOR
GROUND
Figure 5. The Low Impedence of the SG1627 in Both On
and Off States Allows Direct Transformer Drive With a
Minimum of External Components
Figure 6. SG1629 Floating Switch Driver Block Diagram
03
In this circuit the transformer primary voltage-driven by the
source/sink output structure of the SG1627. Core reset to zero
occurs automatically during deadtime, when both ends of the
primary winding are switched to ground. Resistors R, and R,
serve as over-current protection for the driver in case of control
malfunction or onset of core saturation due to load faults on the
secondary. No center tap is required, resulting in elimination of
winding balance problems.
D~II~~ ('r----+---+-----~
AN INTEGRATED FLATING SWITCH DRIVER - SG1629
~~~~ lr----r--r-,
The second interface considered was that between the secondary
winding of a drive transformer and the base-emitter junction of an
NPN power transistor. This configuration is frequently found in
off-line converters, where a half or full bridge design is chosen
because of the high input supply voltage. In this case the design
problem consisted of providing controlled forward base drive to
the power device during the positive polarity of the secondary
voltage, and a fast negative peak current for rapid switch-off
during the negative portion ofthe cycle. No power other than that
provided by the transformer secondary should be required, so that
the power device can be floated above ground by several hundred
volts.
The circuit shown in Figure 6 is a modification of a discrete design
developed by Pete Wood while at TRW semiconductors'. During
a positive cycle, base current flows from the drive transformer
secondary winding through a source transistor which can be
programmed for current limiting. A center tap on the secondary
+VIN
('r----.---.---+~
01
R2
1K
CURRENT
SENSE
SUBSTRA TE & CASE
Figure 7. SG1629 Floating Switch Driver Schematic Diagram
As the detailed schematic of the SG1629 in Figure 7 indicated, in
addition to the high current Darlington source and sink transistors
the circuit also contains several gating options forthe sink orturnoff section of the driver. Source transistors Q3-Q4 and sink
transistors Q6-Q7 are designed to 2Amp collector currents. Base
drive to the source is provided by R" while Q5 provides current
limiting. On the sink side of the circuit, base drive to Q6-Q7 is
normally provided by a resistor connected to Pin 3. Ql senses the
polarity of the input voltage and gates the source transistor off
between each drive current pulse. This action allows the external
12 - 65
APPLICATION NOTES - SG1525A/SG1526/SG1527A
storage capacitor to be charged even at very low duty cycles,
since the discharge current during the "off' portion of the drive
cycle becomes negligible. The sink gate input is used when the
risetime of base turn-on current is important, and transformer
inductance is a significant limiting factor. Methods for using this
feature are found in the SG1629 application note(2).
The new family of regulating pulse width modulators is designated
the SG1525N1527A series of devices, and the device block
diagram is illustrated in Figure 8.
Power Drive Summary
Two integrated power drive circuits designed specifically for use
in switch-mode power supplies have been reviewed. These
devices provide the necessary power gain between a complex
low-power control circuit and high voltage, high current switching
semiconductors, while offering greater performance in a reduced
volume compared to discrete component design. Monolithic
technology will provide even higher levels of voltage and current
handling capability in the future as soon as semiconductor packaging technology solves the problem of providing large pin-outs in
a high power dissipation package.
"c'u--.......
A SECOND GENERATION PULSE WIDTH MODULATOR
CONTROL CIRCUIT· SG1525A/SG1527A
As switch-mode power supplies gained in popularity, a demand
was made by power supply design engineers for an integrated
circuit that offered all of the functions of a control device and the
interface capabilities of a power driver. The SG1525A series of
pulse width modulators represents a combination control IC and
power drive. The control section is based upon the time-proven
architecture of the SG1524, while the output stage of this device
combines many of the elements ofthe previously discussed 1627
power driver. At the same time, improvements were made within
the architecture of the control chip to include even more functions
than were originally available on the 1524.
The internal reference regulator on the chip is trimmed to an
accuracy of ±1 % compared to the original ±4%. Secondly, the
chip now contains on-Chip shutdown and soft start circuitry. The
only external components required are an external timing capacitor. A third area of improvement is in the common mode range of
the error amplifier. By deSigning the error amplifier so the
common mode range now includes the 5.1 V of the reference, a
reference divider network is no longer necessary, thus eliminating
two external resistors. The oscillator Circuitry has been redesigned to make deadtime control easier and multiple device
synchronization easier. Finally, the output stage has been redesigned so that, instead of a single transistor which is periodically
turned on for pulse width modulation, an output source/sink driver
or totem-pole type design is used. Since this particular driver has
the characteristic of low impedance in both the on and off states,
it becomes much easier now to interface the control circuits with
external power transistors including standard bipolar junction
devices, the new power FETs, and also drive transformers.
I
Figure 8. Block Diagram of a "Second Generation" Pulse Width
Modulator Family: The SG1525N1527A Series
The trimmed reference regulator, which.has an output voltage of
5.1 V, not only acts as the reference terminal for the error amplifier
control loop, but it acts as a power source for all the internal
circuitry, with the exception of the error amplifier and the output
drivers. The oscillator determines the basic operating frequency
ofthe pulse width modulator circuil. An external RT and CTare the
components that are fixed to set this frequency. Additionally,
deadtime is controlled by the insertion of a small amount of
resistance between the discharge terminal (Pin 7) and the CT
terminal (Pin 5) on the oscillator. The oscillator circuit has two
outputs: the ramp waveform, which is applied to the positive input
ofthe pulse width modulation comparator, and a periodic positivegoing pulse at the oscillator output pin which acts as the toggle
signal forthe flip-flop. It is also used as the deadtime control pulse
for the output gating logic.
The totem-pole output drivers are designed to easily interface with
either single ended or push-pull types of switching power supply
configurations. There are two output polarities available with this
series of pulse width modulators. In the 1525A series, the output
gating is designed with NOR logic, which results in a positivegoing output pulse during active time. The 1527A series uses OR
logic, so that the active state is a low ground state. This particular
polarity of output is useful in certain types of proportional base
drive circuits in which feedback from the power transformer is
used to provide base current, thereby compensating for variations
in transistor beta.
12 - 66
APPLICATION NOTES - SG1525A/SG1526/SG1527A
Soft Start Circuit
The equivalent ofthe SG1525N1527A soft start circuitry is shown
in Figure 9. An external capacitor CSOFTSTART provides the timing
element for the soft start cycle. This capacitor is charged via a
50microamp current source internal to the chip. The P.W.M.
comparator has two inverting inputs, and the more negative ofthe
two voltages determines the duty cycle. During undervoltage
conditions on the V'N line, current is forced through the two diodes
in 01 's base circuil. A voltage of approximately FBE appears
across 01 's emitter resistor, resulting in a collector current of
approximately 100pA. Since the charging current available is only
50pA, the soft start capacitor is held in a discharged state.
Because the voltage at pin 8 is 0, the PWM comparator ignores the
signal from the error amplifier, and zero duty cycle is obtained.
When the controller supply rises to 8 volts the discharge current
is turned offc,and the voltage on pin 8 rise linearly, resulting in
gradually increasing duty cycle. Eventually the capacitor charges
up very close to the reference voltage and the duty cycle is
controlled by the error amplifier. Ifthevoltage on the shutdown pin
is raised above ±1.5 volts the capacitor is slowly discharged althe
same rate it is normally charged.
RAUP
2'"
Q"
7.4K
R,
C,
TO
L -____~~----~---+--+_p~
COMPARATOR
SYNC
tl-'Nr+----l-1:<:Ol1
DISCHARGE
OSC
OUTPUT
3K
Figure 10. SG1525N1527A OSCillator Schematic Diagram
When the voltage on Cr is less than +3.3V, the discharge network
does not conduct and CT receives a constant charge via the
current mirror, resulting in a linear increasing Voltage. When the
+3.3V trigger level is reached, the comparator changes state and
turns on the discharge network. This rapidly removes charge from
CT so that voltage falls towards +1V, at which time the comparator
changes state again and another cycle begins. The discharge
time of CT is used to generate the blanking pulse at the oscillator
output pin. The deadtime or pulse width althe oscillator output pin
may be increased from its minimum value of approximately 400 to
500 nanoseconds by a resistor between the discharge pin and Pin
5, which lengthens the discharge time of Cr during the second half
of the oscillator cycle.
BLANKING
TO OUTPUT
A positive pulse at the sync pin will initiate a discharge cycle in the
oscillator. This pin then forms a convenient connection for
synchronizing the IC to a frequency supplied by an external
system clock.
CLOCK
Output Driver
Figure 9. SG1525N1527A Softstart Circuit
Oscillator Description
The circuit for generating of the timing ramp waveform is shown
in Figure 10. The timing capacitor CT receives a constant charge
current from the compound current mirror formed by 01 and 02.
The RT terminal voltage is two VBE less than the reference voltage,
so that a resistor tied from Pin 6 to ground sets up the charging
current for CT' Transistors 05 through 010 form a voltage
comparator which constantly compares the voltage at CT to either
a +3.3V or +1V reference, depending on the state ofthe comparator. The timing capacitor CT is discharged via the Darlington
formed by 03 and 04.
A simplified schematic of the output gating and the power output
stage ofthe 1525A is shown in Figure 11. Transistors 01 , 02, and
03, together with a 500 microamp current source, from a logical
NOR gate where the pulse width modulation signal from the pulse
width modulation comparator, the deadtime pulse from the oscillator, and one side of the toggle flip-flop are combined. 04 is an
amplifier with active load which inverts the output signal from the
NOR gate. 05, in turn, acts as the phase-splittertransistorforthe
push-pull outpul. When 05 is on, its emitter current drives the
base of 08, holding the output low. Althe same time, the collector
of 05 is also low, thereby back-biasing 06 and 07, the output pullup devices. When 05 turns off, its collector voltage rises, turning
on the output Darlington. At the same time, 08 turns off and the
output terminal is pulled up towards the Vc supply. Diode 01 acts
12- 67
•
APPLICATION NOTES - SG1525A/SG1526/SG1527A
to protect the base emitter junction ofthe upper Darlington against
reverse breakdown. D2 acts to provide extra base drive current
to 08 during turn off. If a capacitive load is present on the output
terminal, D2 will turn on and the extra collector current of 05 will
then be routed to 08 so that 08 in turn will be turned on harder,
thus discharging the output capacitance and enabling the output
to fall rapidly to zero.
10V
I
5V
ov
+vc
H'IN
'm'Q)
~
4A
06
~ I"""'"
2A
07
D1
TIME BASE:
D2
;'00
./lA
01
~2~3
l-~5
14
1/
OA
OUTPUT
UPPER TRACE:
LOWER TRACE:
A
"
-
200ns/DIV
POWER FET GATE DRIVE
POWER FET DRAIN CURRENT
Figure 12. SG1525NPower Fet Turn-On Wave Forms
l-
rfB
10V
n'n
5V
PWM
osc
0
\v
ov
Figure 11. SG1525A Pulse Width Modulator Power Output Stage
4A
The source and sink transistors 07 and 08 in this driver are
designed to provide more than 1OOmA of current handling capability. In most cases, the full current capabiiity will not be used in
a steady state condition to drive an external load but rather the
peak current capability can be used to provide rapid charging of
external capacitance loads, thereby providing very fast rise and
fall times at the output driver.
2A
"
OA
TIME BASE:
200ns/DIV
UPPER TIRACE: POWER FET GA TIE DRIVE
LOWER TRACE:
POWER FET DRAIN CURRENT
Figure 13. SG1525NPower Fe! Turn-Off Wave Forms
Figures 12 and 13 illustrate the speed capabilities of the output
drivers when driving power MOSFETs, in this case a pair of
Siliconix VN64GA devices. The upper traces show the driver
output voltage swing for a collector supply of +12 volts. The lower
waveforms are the 0-5amp drain currents of the FETs. Switching
times of 100 nanoseconds were achieved by driving the gates
directly from the totem pole outputs, and by limiting peak currents
to 200mA with a 620hm resistor atthe +Vc terminal. Fastertimes
can be obtained with the higher current SG1627 Power Driver.
N'
I
r'"
u
zw
::J
aw
J
150
0::
"0::
The ultimate frequency capabilities of the output drivers as a
function of ambient temperature for a given VMOS load is shown
in Figure 14. For this graph, a +Vc supply of 12 volts was
assumed. An effective power FET input capacitance of 1000pF
on each driver was also assumed. A thermocouple attached to
the ceramic dual-in-line package allowed junction temperature to
be calculated based on a worst case 6JC of 60°CIW and a 6JA of
1OO°CIW maximum.
200
~
100
a::
D
x
«
50
SG1525/27J
+Vc=12 VOLTS
CL =2X1000pF
::;;
a
-75 -50 -25
a
25
50
75
\
100 125
AMBIENT TEMPERATURE-("c)
Figure 14. SG1525N1527A Power Fe! Drive Capability
12 - 68
APPLICATION NOTES - SG1525A/SG1526/SG1527A
For ambient temperatures below 90°C, the maximum frequency
allowable is determined by the maximum possible oscillator
frequency of 400kHz. Above 90°C operating frequency and
dynamic power dissipation must be reduced to keep the junction
temperature from exceeding +150°C. Different supply voltages,
capacitive loads, and heat sinking will result in other temperature
limits.
and a pulse width modulation comparator. Of particular interest
are some new features in the block diagram: an undervoltage
lockout, soft start circuitry, digital current limit comparator and
digital signal processing logic between the pulse width modulation
comparator and the output power drivers.
It will be noticed in comparing the block diagram ofthe SG1525A/
1527A family to that ofthe SG1524 thatthere is no provision made
directly for current limiting on the 1525A/1527A. The reason for
this is that this chip is designed to interface with a new output
supervisory circuit, the SG1543. This device has an extra
comparator with adjustable offset which can be used for providing
the current limit function in conjunction with the SG1525A/1527A.
Additionally, this particular chip has the capability for providing
under and overvoltage protection for the remainder of the power
supply.
Figure 15. SG1526 High Performance Pulse Width
Modulator Block Diagram
A THIRD GENERATION SWITCHING POWER SUPPLY CONTROL CIRCUIT - SG1526
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The operation of the circuit is as follows: An on-Chip regulator
trimmed to 1% is both reference voltage forthe error amplifier, and
also the stabilized power source for all the internal circuitry, with
the exception of the error amplifier, the current limit comparator,
and the output drivers.
Supply operation to 40 volts
Reference trimmed to ±1%
Sawtooth oscillator with dead band control
PWM comparator with hysteresis
Undervoltage lockout
Programmable soft start
Wide error amp common mode range
Wide current limit common mode range
Two modes of digital current limiting
Double pulse suppression logic
Single pulse metering logic
Symmetry correction capability
TTL/CMOS compatible logic
Dual 100mA source/sink output drivers
The sawtooth oscillator is programmed for a specific frequency
and dead band by values of RT, CT and RD. The resulting ramp
waveform is applied to one side of the pulse width modulation
comparator, which has been designed with a very small amount
of hysteresis to prevent oscillations at the' comparison point. The
other terminal of the PWM comparator is connected to the output
of an error amplifier which has been designed with a common
mode range that includes both ground and the 5V reference.
Table 1. Desirable Features of a High-Performance
Pulse Width Modulator
An ideal circuit for switching power supplies should include not
only the elements necessary for normal pulse modulation operation, but also the full range of abnormal operations. Ideally, the
circuit should contain as many protective features as possible for
the power semiconductors. If a table of parameters were constructed for such device, it would look much like that shown in
Table 1. Analysis ofthefeatures in the table would show that most
of the new features are control related and are therefore ideally
suited for inclusion in an integrated circuit, where a great deal of
complexity can be easily compressed into a very small area. Just
such a device has been designed by Silicon General, and the
block diagram of that device is shown in Figure 15.
As can be seen, the four basic elements ofthe pulse modulator are
present: a reference regulator, error amplifier, sawtooth oscillator,
Also associated with the amplifier is on-Chip soft start circuitry.
This soft start circuitry is controlled not only by an external RESET
terminal, but also by the undervoltage lockout Circuitry. If the
reference voltage should be less than the 5V required for normal
linear operation of the control circuitry, the RESET terminal in the
soft start is held low by the undervoltage lockout, thus preventing
the soft start capacitor from charging. At the same time, the power
output drivers of the device are inhibited. thus making it impossible for spurious output pulses to occur during undervoltage
conditions.
The digital output of the pulse width modulation comparator is
ANDed with the output of the current limit comparator. This
provides very fast response to overcurrent conditions. The
current limit comparator has a fixed input offset of 100mV plus a
slight hysteresis of 20mV to eliminate indecision at the threshold
pOint. The PWM signal from the AND gate is followed by three
levels of pulse processing logic. It first passes through a metering
12 - 69
•
APPLICATION NOTES -SG1525A/SG1526/SG1527A
flip-flop whose function is to allow only one output pulse per
oscillator cycle, thus eliminating oscillations and permitting pulseby-pulse current limiting. The second element is a memory flipflop. This flip-flop is part ofthe double pulse suppression logic and
prevents two pulses in succession from one output driver, independent of conditions on the SHUTDOWN terminal, RESET
terminal or error amplifier inputs. Also included is a toggle flip-flop
which alternately gates first one driver and then the other in the
presence of a PWM signal.
The final elements in the block diagram are the source/sink output
drivers, with a separate collector supply voltage terminal brought
out for additional flexibility.
A simplified version ofthe undeNoltage lockout circuitry is shown
in Figure 16. The circuitry consists of a 1.2V bandgap reference
and a voltage comparator which are fully operational for reference
voltages greater than 2.1 V. When the reference voltage is greater
than 2.1 V, the output transistor is turned on, inhibiting both power
output drivers. It also holds the RESET line controlling the soft
start circuitry in the low state, thus preventing the soft start
capacitor from charging, and guaranteeing zero duty cycle.
R1
TO RESET
"r
TO DRIVER A
TO DRIVER B
1.2V
BANDGAP
REFERENCE
A simplified schematic of the oscillator of the 1526 is shown in
Figure 17. A new approach is taken for controlling deadtime in the
circuit. The principle of operation is similar to the 1524 and 1525
oscillator. A timing capacitor is charged via a constant current
programmed by an external resistance 1\. 'When the capacitor
has charged linearly up to a nominaI3.2V, a voltage comparator
changes state, thereby turning on a discharge network which
reduces the capaCitor voltage very rapidly to the +1V level. The
distinctive difference between the oscillator in the 1525 and that
in the 1526 is that the discharge network is a current source
instead of a semi-saturating Darlington. In the 1526, the discharge circuit is formed by a pompound current mirror, 03, 04,
and 05. The output current of this current mirror is ratioed to the
current charging in CT by a ratio of 30: 1. This results in a charge
time to discharge time ratio of approximately 29: 1 independent of
the value of Cr This ratio can be· modified to give longer
deadtimes by insertion of a small amount of resistance from Pin
11 to ground. With this technique, deadtimes up to 50% or more
are easily obtainable. The oscillator configuration has the advantage that the minimum deadtime for the oscillator is now fixed at
approximately 3% independently of the frequency of the circuit.
Or
""'"
RZ
Figure 17. The SG1526 Oscillator Provides Deadband
Control By Rationing The Charging Currents to CT
Figure 16. The Undervoltage Lockout Circuit Contains a
Bandgap Reference and Comparator Which Becomes
Active at VREF=3 V.e"'2.1 Votts
Resistive divider Rl and R2 is scaled so that when the reference
voltage reaches 4.5 v the comparator changes state, thus releasing the soft start capaCitor and also enabling the power drivers.
Approximately 200mV hysteresis is built into the comparator so
that the transition from lockout to fully on is not accompanied by
indecision and jitter.
Monitoring the reference voltage rather than the input terminal
voltage has an additional benefit. With this particular configuration, this chip can operate on +5V by connecting the VIN terminal
to the VREFERENCE terminal and then regulating the input voltage
between 4.5 and 5.5 volts. This is a desirable feature where other
supply voltages must be generated from a regulated +5V source.
The remainder of the oscilator circuit functions similarly to that of
the 1525. One notable exception is the TLL compatible buffer gate
between the SYNC output pin and the remainder of the circuit.
This enables the port to be bi-directional, driven either by opencollector TTL or by open-drain CMOS, or to itself drive other TTL
or CMOS logic.
Figure 18 contains a brief explanation of the pulse processing
logic in the 1526. The logic consists-of two specialized flip-flops:
a metering or data latch flip-flop, and a set/reset or memory flipflop, The metering flip-flop is basically an asynchronous data
latch which is enabled by a sync pulse from the oscillator during
the beginning of every oscillator cycle. Once the metering flip-flop
is enabled, a PWM signal may pass asynchronously through the
device. However, once the signal is terminated for any reason, no
12-70
APPLICATION NOTES - SG1525A/SG1526/SG1527A
new pulse can propagate through the data latch until a new sync
pulse is received atthe beginning ofthe next oscillator cycle. This
feature allows each individual pulse to be terminated either by the
action ofthe current limit comparator or by external circuitry which
pulls the SHUTDOWN pin low. This feature allows the SHUTDOWN pin to be a convenient input port for a strobe pulse from
symmetry correction circuitry.
cycle. Waveform E is a SHUTDOWN signal from the current limit
comparator. Alternately, this line could also show a digital input
signal from other control logic. The waveform at line F represents
the ANDed output of the PWM comparator and the SHUTDOWN
signal. This acts as the date input to the metering logic flip-flop,
whose output is shown as Waveform G.
SYNC --~---c:1
R Ci
PWM
0U
MEMORY FIF
~~-------PWM
METERING FIF
METERING FLlp·FLOP
DESCRIPTION: ASYNCHRONOUS DATA
LATCH
FUNCTION:
ALLOWS ONLY ONE
PWM PULSE PER
OSCILLATOR PERIOD
BENEFIT:
SUPPRESSES HIGH
FREQUENCY OSCILLA·
TIONS
U
U
II
U
@
®
MEMORY FLlp·FLOP
®
DESCRIPTION: SET·RESET FLlp·FLOP
REMEMBERS WHICH
FUNCTION:
OUTPUT PRODUCED
LAST PULSE
BENEFIT:
INHIBITS DOUBLE
PULSING IN PUSH·PULL
CONFIGURATION
/
®
.....
-- ..... ,
\ tnn
__ i.
\
......
CD
.-"
Figure 18. SG1526 Pulse Processing Logic
@
The function of the memory flip-flop is to generate the clock pulse
for the toggle flip-flop, which alternately gates the two output
power drivers. It operates as follows: Let us assume that the flipflop begins operation in the reset state. When a sync pulse is
received from the oscillator, the Q terminal is then driven low,
generating a clock pulse for the toggle flip-flop, which then
changes state. If a PWM Signal is generated during the oscillator
cycle, then the flip-flop is reset, thus enabling it to generate
another clock at the beginning of the next oscillator cycle. If no
pulse width modulation signal is generated because the duty
cycle has gone to zero or SHUTDOWN has been pulled low, then
the memory flip-flop will not be reset, and when the next sync
pulse occurs, no clock will be generated. In this way, the output
flip-flop is toggled only upon generation of pulse width modulation
signals, thus rendering it impossible for two successive pulses to
be obtained from one output driver.
The operation of the metering logic in the 1526 is shown in more
detail in the timing diagram in Figure 19. The top waveform,
Waveform A, shows the SYNC pulse train from the oscillator. This
pulse train divides four timing periods, T, through T4 , as shown at
the bottom of the timing diagram. Waveform B represents the
ramp signal from the master oscillator, while Waveform C represents the analog output signal from the error amplifier. These two
waveforms are differentially compared in the pulse width modulation comparator, whose output is shown as Waveform D. It can
be seen that the error amplifier output voltage is just slightly less
than the peak of the ramp signal approaching nearly full duty
I
'2
'3
'4
Figure 19. Timing Diagram of the Pulse Processing Logic
Over Four Oscillator Cycles
The first time frame, T" illustrates a normal period of operation~
The error amplifier calls for nearly full duty cycle; the SHUTDOWN
pin stays high, and this output signal then passes unaltered
through the metering logic flip-flop. During the second time frame,
the SHUTDOWN pin is pulled low for several times during the
active pulse period. This results in a series of pulses being applied
to the data input ofthe metering logic flip-flop, but as can be shown
in Waveform G, once the first pulse is terminated no other pulse
can begin until the next oscillator cycle. During time frame Ta, the
SHUTDOWN pin is low, thus preventing and PWM signals from
reaching the metering flip-flop. In the fourth time frame, the
disturbance at the output of the error amplifier causes multiple
ramp crossings, which generates multiple PWM signals during
one oscillator cycle. These Signals reach the data input of the
metering flip-flop, but as before, once the first pulse is terminated,
the remainder of the pulses cannot propagate through the device
to the output drivers.
The combination of source/sink drivers with a separate collector
supply voltage terminal allows the output drivers to be easily
interfaced with all the circuit configurations found in mot switching
power supplies. Figure 20 illustrates the connections for a
common emitter push-pull configuration. In this circuit, the
12 - 71
•
APPLICATION NOTES - SG1525A/SG1526/SG1527A
collector supply to the output source/sink drivers is tied to the
supply voltage through R" iNhich limits the voltage swing of each
driver output, preventing emitter-base breakdown. During the
turn-off cycle, an additional spike of reverse base current is
. generated by the speed-up capacitor C, or C2 •
+v SUPPLY
primary. In this example, the transformer drive capability is used
to interface the control device with the power transistors in a half
bridge configuration.
+V SUPPLY o - - t - - - - - - - - - - 1 > - - - - - - - ,
0---.---------------,
C,
II
T1
RETURNo--~-----------<~--~
RETURN
Figure 22. Low Power Transformers are Driven Directly
by the Output Terminals
Figure 20. Basic Connections For a Push-Pull
Grounded-Emiller Configuration
Buck-type converters are easily interfaced to the totem pole output
devices. Forthis mode of operation it is necessary only to ground
the output terminals A and B, and drive the base of the switching
device with the collector supply terminal. In this configuration, the
upper Darlington resistors are alternately turned on and pull Pin
14 to ground, thus providing up to 100mA of current drive
c?pability on alternate oscillator cycles.
+V SUPPLY
If an additional current drive capability beyond that available in the
1526 is necessary, it is very easy to interface the output totempole drivers with the 1627 dual500mA driver circuit. This is shown
in Figure 23.
r---------,
1/2
+VSUPPLY
r----------,
1/2 SG1627
u-~---.
Figure 23. The Totem-Pole Outputs of the SG1526 can be
Interfaced to the SG1627 Power Driver With
a High-Speed Switching Diode
The logic threshold of the 1627 is a nominal +2V, while the sink
current in the low state is about 1mA. A fast silicon switching diode
such as a 1N914 can be used to provide a sink current path in the
low state, while blocking excessive input curre.nt to the power
driver during the control circuit's high state.
RETURN o-------<>------+_
Figure 21. For Single-Ended Configurations the Vc Terminal is
Alternately Switched to Ground by the Driver Pull-Up Transistors
The totem-pole outputs can also drive a transformer directly, as
illustrated in Figure 22. Since each output driver exhibits a low
impedance, no center tap winding is required on the transformer
The ability of one control port of the 1526 to drive another control
port enables a good deal of flexibility from the: chip. The flyback
converter in Figure 24 illustrates this pOint. Cu~rent limiting in ~
flyback converter is difficult because the overcurrent signal from
12 -72
APPLICATION NOTES - SG1525A/SG1526/SG1527A
the current sense resistor is always out of phase with the conduction of the principle power transistor. In this circuit, the output of
the current limit comparator in the 1526 is used to re-trigger the
soft start circuitry. By choosing the value ofthe soft start capacitor
so that the recovery time of the soft start circuitry is of the order of
one or two cycles, it is possible to provide current limiting with a
minimal number of external components. This same technique
can be used in a push-pull converter where it is desirable for the
pulse width modulation signal to be turned off for multiple oscillator cycles rather than for a single cycle. This allows overstressed
output semiconductors a cool-off period before returning to normal operation.
+VSUPPLY
0---------.,.-----------,
T1
II
CONCLUSION
Several integrated circuits designed specifically for switch-mode
power supply control have been described. A brief review has
been made of past approaches to the integration of switching
power supply control and driver circuitry. A description of a newly
available family of control/driver integrated circuits, the SG1525/
1527 series, has been given. Finally, a sketch of a future high
performance controller circuit, the SG1526, has been drawn.
The future of integrated circuits for switching power supplies
clearly involves greater complexity in the control circuitry to
account for all possible modes of supply operation. The benefits
for the power supply designer will be greater performance and
reliability from switchers with reduced component count and
greater overall manufacturing economies.
REFERENCES
1. Peter N. Wood, "Design of a 5 Volt 1000 Watt Power
Supply," TRW Power Semiconductors Application Note
122A, February, 1976.
SG1526
+c.s.
-c.s.
2. Robert A. Mammano, "Power Switch Drivers: New IC
Interface Building Blocks for Switched-Mode Converters," Powercon 5 Proceedings, May, 1978.
R2
RETURN
o-~~
____--4_ _ _ _ _ _ _ __+_-1
Figure 24. Using the SG1526 in a Flyback Converter
With Current Limiting
II
12-73
12 -74
APPLICATION NOTES - SG1825
SILICON
GENERAL
PS-11
LINEAR INTEGRATED CIRCUITS
SG1825 DESIGN BRIEF: A 200KHz CURRENT-MODE SUPPLY
Reza Amirani and Stan Dendinger
Silicon General, Inc.
INTRODUCTION
To demonstrate the high-speed capabilities of the new SG1825
Pulse Width Modulator, a small 200 KHz switching power supply
was designed and constructed. A push-pull current mode architecture was chosen because of its inherent anti-saturation properties. This choice of more efficient magnetic structure and the
200 KHz switching frequency allowed the transformer bulk to be
minimized.
Peak transformer primary current, which can be scaled to the
output filter inductor current through the turns ratio, is sensed by
a 1.0 ohm resistor in series with the MOSFETsources. After a low
pass filter to remove leading edge peaking, the waveform is
applied to the Ramp input pin. The current pulse is compared to
the output ofthe error amplifier, and the drive to the power devices
is terminated when the peak current exceeds the threshold set by
the outer voltage control loop.
DESIGN SPECIFICATIONS
Slope compensation, required for loop stability above 50% duty
cycle, is implemented by buffering the ramp waveform at the CT
pin with an 2N2222 emitter follower to preserve linearity. The
ramp is summed with the supply output voltage sample at the
inverting input of the error amplifier.
Input Voltage: +22 to +32 VDC
Output Voltage: +5.0 Volts
Output Current: 0.5 to 2.0 Amps
Line Regulation: ± 1%
Load Regulation: ± 1%
Output Noise and Ripple: 50 mV RMS
Full Load Efficiency: 73%
Total Weight: 10 oz.
CIRCUIT DESCRIPTION
The circuit uses a bootstrap winding and the micropower start-up
capabilities of the SG1825 to efficently provide controller supply
voltage. Typical start-up current is only 600 [lA, an improvement
of 2.5 over alternate-source controller ICs.
When the +28 volt input is applied, the 680 [IF start capacitor is
trickle-charged by the 2.7K bleeder. While the controller is in
micropower mode, the driver outputs are switched to ground,
providing protection against leakage currents which could turn on
both power MOSFETs.
At+9.2voltsthe SG1825 turnson, driving the transformer primary
through the two International Rectifier IRF840s. The 50 ohm
series resistor at each gate provides isolation from the CGO kickback voltage, while the 1N5819 Schottky diodes provide a lowimpedance drive atturn-off. The bootstrap winding then becomes
active, providing the low-voltage high-current supply required by
the control device. The turns ratio beween the regulated +5 volt
output and the bootstrap winding is 2/4 or 0.5, resulting in a
nominal 10 volt semi-regulated supply. Since the rectifier filter is
capacitive-input rather than inductive, the actual controller supply
is +15 volts.
Short circuit protection is provided by passing the current waveform through a somewhat narrower bandwidth filter, and applying
it to the dual threshold ILIM/Shutdown pin. At light overloads,
the +1.0 volt threshold will be exceeded, triggering pulse-by-pulse
current limiting. If the output load increases further, the + 1.4 volt
threshold will be crossed. This discharges the sOftstart capacitor, causing a low-frequency "hiccup" mode of current
limit.
The transformer flux swing was chosen to be ± 0.1 Tesla (± 1000
Gauss) to keep losses low in the H7c4 ferrite core. Primary and
bootstrap windings were bifilar wound to minimize leakage inductance, and the high current secondary was quadfilar construction
for the same reason.
CONCLUSION
The completed power supply was bench-tested and met all
design specifications. At 400KHz oscillator frequency the PWM
chip had a wide modulation range, with nearly text-book waveforms. The improved layout and ground partitioning inside the
integrated circuit minimized crosstalk problems between the highcurrent output drivers and the high-speed pulse-processing logic.
Most importantly, the SG1825 controller was functional and wellbehaved down to -55°C, making it particularly well suited to highfrequency military power supplies.
January 1990
12 -75
APPLICATION NOTES - SG1825
APPLICATION CIRCUIT
~7K
1/20
+VOUT
REnJRN
TRANSFORMER T1:
'''"
CORE: TDK PQ20116
FERRITE: H7C4
WINDINGS:
7 TURNS BIFILAR #22 AWG
A. PRIMARY:
B. BOOTSTRAP:
4 TURNS BIFILAR #32 AWG
C. SECONDARY: 2 TURNS QUADFILAR #22 AWG
"'"
FILTER INDUCTOR Tl:
CORE: MAGNETICS, INC MPP 55051-A2
WINDING: 27TURNS #22 AWG
FIGURE 1 - SGI 825 200KHz CURRENT-MODE POWER SUPPLY
12 -76
g
SILICON
GENERAL
APPLICATION NOTES - SG1842/SG1843
S01844/SG1845
PS-12
LINEAR INTEGRATED CIRCUITS
A CURRENT MODE I.C. OPTIMIZED FOR SINGLE
ENDED CONVERTERS
Reza Amirani
Silicon General, Inc.
INTRODUCTION
Recent advances in switched mode power supply (SMPS) technologies have resulted in rapid developments of more advanced
pulsed width modulator (PWM) integrated circuits. Conventional
PWM techniques are now losing some oftheir market share to the
newer PWM circuits that are using current mode technology. One
of these current mode PWM integrated circuits optimized for low
cost, low to mid range output power supplies (15W-250W), is the
SG1842/43/44/45 family of PWM controls. This application note
includes a brief review of voltage mode technique vs. current
mode (constant frequency type), their advantages and disadvantages, that is followed by a functional description of the SG1842/
43/44/45 family of PWM controllers.
'--_ _ _--r_ _ _ H_ _ _-,....vO
I
CURRENT MODE VS. VOLTAGE MODE CONTROL
Let us briefly review the conventional control approach (voltage
mode technique) by referring to Figure 1.
In this method, the small differential voltage between output
voltage (V0) and reference voltage (VR) is being amplified by the
high DC gain of the error amplifier, resulting in an error voltage
(VE)' This voltage is then compared to a fixed frequency sawtooth
with a finite peak to peak magnitude (VM)' The output of the
comparator stage is now a fixed frequency, variable duty cycle
square wave that controls switch element (01) according to the
variations in the magnitude of error voltage. This type of a
converter where a single loop system is incorporated and only
output voltage is being monitored and regulated, is called voltage
mode technique. It is possible to vary the slope of the ramp signal
in proportion to variation of input voltage, in order to improve line
regulation and output dynamic response. This scheme is an
improved version of voltage mode which is referred to as feed
forward technique.
Figure 1. Typical Application of a Voltage mode regulator
The operation is as follows. A clock signal running at a fixed
frequency sets the output of the latch circuitry to go high, turning
on the switch (01). Once the voltage across the sense resistor
(Rs) reaches a threshold set by the error signal (VE)' the output of
the comparator (A2) switches low. This resets the latch, resulting
in termination of the next output pulse and keeping it low until
arrival of the next clock pulse.
Now let us examine current mode method by referring to Figure
2. Notice that unlike the voltage mode, this scheme consists of
two loops; a current loop which detects the switch current, inside
another loop regulating the output voltage, called voltage loop.
r-_JY'''-_ _ _ _.--_-Jt--_ _--.-..VO
Vc
I
ClOCK(VT)~
~~~~~ ~~~;~~~ ~~~~ :r==c=:r=c:::r=
CONTROL VOLTAGE (Ve)
..rL..JL....r
Figure 2. Typical Application of Current Mode Regulator
January 1990
12-77
II
APPLICATION NOTES - SG1842/43/44/45
As a result of this two loop control scheme, current mode controllers offer several performance advantages. The first advantage
over voltage mode is the inherent feed forward capability. Recall
that in the current loop, the ramp voltage fYs) across sense
resistor was generated by the inductor current during switch "ontime", which was also directly proportional to the input voltage
fYIN). Therefore, as VIN increases, the slope of the ramp also
increases, which causes a shorter duration of the switch "ontime". This results in the control loop quickly adjusting itself to any
line pertubations since it does not have to wailfor a command from
the output. As a result of this, current mode regulators have
excellent line regulation and transient response.
Second, pulse-by-pulse current limiting is inherently achieved
whenever using this method. This is because the error signal sets
a limit on inductor peak current. This means that maximum
current or current limit knee point can easily be set by simply
clamping the output of error amplifier. This feature of current
mode controllers is especially important whenever push-pull
center tapped topologys are used, where any imbalance in the
power transistors can cause a net DC current flow in the transformer. This problem sometimes causes transformer saturation
and failure of the power tfansistors.
Finally, current mode controlled regulators can operate in parallel with equal current sharing, due to their inherent current regulating feature. One big advantage of paralleling converters is their
redundant operation for the applications requiring high reliability
power systems.
DESCRIPTION
The 1842/3/4/5 family of PWM controlled ICs are designed for low
cost switched mode power supply applications utilizing current
mode techniques. While they can be used in most DC-DC
applications, they are optimized for single-ended designs such
as Flyback and Forward converters. 1842/44 series are best
suited for off-line applications, whereas 1843/45s are mostly
used in power supplies with low input Voltages. The IC can be
divided into six main sections as shown in Figure 3: undervoltage
lockout and start up; reference oscillator; current sense and PWM
latch; error amplifier; and the output stage. The operation of each
section is described and the differences between the members of
this family are summarized in Table 1 and explained in each
related section.
UVLO
PART #
Third, current mode regulators are easier to stabilize and require
simpler compensation circuitries. This is due to the fact that by
controlling the inductor current, the double poles of control to
output transfer function associated with conventional approach,
are separated with two single poles. As a result, less phase shift
is generated and the required phase boost is less critical for a
stable operation. In fact, many current mode regulators are often
compensated such that the overall loop gain is crossing zero db
gain at a frequency prior to reaching the second pole frequency.
Start-up
Voltage
fYST)
SG1842
SG1843
SG1844
SG1845
Hysterise
Voltage
MAXIMUM
DUTY CYCLE
fYHvsl
6V
0.8V
6V
0.8V
16V
8.4V
16V
8.4V
<100%
<100%
<50%
<50%
TABLE 1
vcc
"REF
GROUND
f--.....-----_-----------o S.OV
SOmA
Vc
"---'-J
OUTPUT
Yrs
POWER GND
COMP
CURRENT SENSE
Figure 3. Devise Block Diagram
12 -78
APPLICATION NOTES - SG1842/43/44/45
UNDERVOLTAGELOCKOUT
The purpose of undervoltage lockout is to maintain a low quiescent current of less than 1mA and to guarantee that the IC is fully
functional before the output stage is activated. Both input voltage
01'N) and reference are monitored by separate comparators with
built-in hysteresis. The input voltage comparator upper and lower
thresholds for 1842/44 is 16V/1 OV and 1843/45 has 8.4V/7.6V
nominal threshold levels. The combination of low start-up current
and large hysteresis make them ideally suited in off line converter
applications. Referring to Figure 4, an efficient start-up circuitry
is implemented using 1842 PWM IC in conjunction with a bootstrap winding off of the power transformer. The operation of the
circuitry is as follows.
DC
racy of 184X/284X is :01%, and 384X series has :02% over their
specified ambient temperature range. The reference is capable
of providing in excess of 20mA for powering any external control
circuitries and has built-in short circuit protection.
5.02
$'
II
'I
w
(!)
~
...J
5.00
0
w
u
z
w
0::
W
U.
W
0::
I--
=
vee
~~
\
15V
/
>
BUSLr--~---------------------------,
'ST
u
w
7:8
0::
«
I
(f)
7.6
(5
0::
::2
«
-'
-'
7.4
100
'"
~
.~
~~
~ ~~
Rr
Rr
Rr
Rr
1
0.001
-
W
Ill.
.'- 1'-1'
10
"
"\.." ~6'Q1).
, I'
,,~I,l
-:"~
30KO
~
= 50K!]
= 70K!]= 100K!]
IV'I
~~
0.01
0.1
CT - (J1.F)
Figure B. Oscillator Timing Diagram
I
.......
",
"
RT = 267
'\
[(1.7 itrm
6
J
-1
('-I) I 0.3" Om" 0.95
1.0m
(1.76)15iil-1
C = 1.86 * Om (fd)
r
f* Rr
II
(;)
u
"-
~~
Given: frequency" f; maximum duty-cycle" Om
Calculate:
8.2
<'
E
'I
I-
1000
for duty cycles above 95% use:
I
u
(f)
Example: A flyback power supply design requires the duty cycle
to be limited to less than 45%. If the switching frequency is
designed to be 50kHz, what are the values of Rr and Cr?
0
7.2
~0~5
0
~
~
~
l001~1~
JUNCTION TEMPERATURE-( °C)
Figure 7. Oscillator Current vs. Temperature
Given: f = 50KHZ
Om =0.45
The oscillator is designed such that many values of Rr and Cr will
give the same frequency, but only one combination will yield a
specific duty cycle at a given frequency (see Figure 8). A set of
formulas are given to determine the values of timing components
for a given frequency and duty cycle. (NOTE: The following
formulas are less accurate at shorter duty cycles and/or higher
frequencies. This will require some adjustment of timing components to correct for this error).
12 - 80
Rr = 267
~
~
As
(1.76).,&-1
1
(1.76)"45 -1
=674'-1
APPLICATION NOTES - SG1842/43/44/45
CURRENT SENSE COMPARATOR AND PWM LATCH
Referring back to the operation of current mode PWM, recall that
the switch peak current is established by the output of the error
amplifier. This current is sensed by an external sense resistor (or
a current transformer), monitored by a C.S. pin and compared
internally with a voltage from the output of the error amplifier. The
output of comparator then goes to a PWM latch that will insure only
a single pulse to appear at the output during any given oscillator
cycle. SG1844/5 series have an additional flip flop stage that will
limit the output to less than 50% duty cycle range as well as
reducing its frequency to half of the oscillator frequency. The
current sense comparator threshold is internally clamped to 1V
nominally which would limit maximum peak switch current to:
V1
oS
I
>-
«
220
/
200
1/
...J
w
0
w
180
/v
(11
z
w
(11
160
V
f-
Z
w
'"'"=>
140
."....
IN3 = 1.1V
V'
u
120
~~
Isp " Peak switch current
V z a internal zener
0.9VsVz s1.1V
0
~
~
~
l00l~l~
JUNCTION TEMPERATURE-(OC)
Figure 10. Current Sense to Output Delay VS. Temperature
Equation 1 is used to calculate the value of sense resistor during
the current limit condition where switch current reaches its maximum level. In normal operation of the converter, the relationship
between peak switch current and error voltage (voltage at pin 1)
is given by:
(1) IsPMAX =
V -2V
E
F
""3*R
where:
s
V E 51 Voltage at pin 1
V F 51 Diode - Forward volt.
0.7V at T J = 25°C
The above equation is plotted in Figure 9. Notice that the gain
becomes non-linear above current sense voltages greater than ~
0.88 volts. It is therefore recommended to operate below this
range during the normal operation. This would insure that overall
closed loop gain of the system will not be affected by the change
in the gain of the current sense stage.
1.0
:;:-
0.9
Y0
0.8
0
0.7
/. '?7
w
0.6
w
0.5
I
z
0.4
f-
0.3
z
w
'"'"=>
u
0.1
0
80
rn
~
~
60
o
~
"'-
z
:;;'
"w
"::;
Ifll
/ VI
0.2
=3(1.1)+1.8 =10K
O.5mA
Figure 11 shows the open loop gain and phase response of the
error amplifier for all devices.
II
(11
w
FMIN
IJ'I'
f-
(11
R
lQq.,t:
(11
'"
The error amplifier has a PNP input differential stage with access
to the Inverting input and the output pin. The N.1. input is internally
biased to 2.5 volts and is not available for any external connections. The amplifier is internally compensated with a bandwidth of
~ 1MHz and a typical DC open loop gain of ~ 90dS. The maximum
input bias current for 384X series is 2!!A, while 184X/284X
devices are rated for 1!!A maximum over their specified range of
ambient temperature. Low value resistor dividers should be used
in order to avoid output voltage errors caused by the input bias
current. The error amplifier can source 0.5mA and sink 2mA of
current. A minimum value of feedback resistor (R F) is given by:
II /
VII
...J
I
ERROR AMPLIFIER
40
~
20
0
>
II II
2.0
0
3.0
4.0
5.0
10
ERROR AMP OUTPUT VOLTAGE-(V)
I'"
Av-
UJ
1.0
-45
100
lK
10K
FREQUENCY -
Figure 9. Current Sense Threshold VS. Error Amplifier Output
~
-90
f'1
-0
~\
lOOK
'tl
I
»
(11
\
1M
-135
'0
~
-180
10M
(Hz)
Figure 11. Error Amplifier Open-Loop Frequency Response
12 - 81
II
APPLICATION NOTES - SG1842/43/44/45
2.5
OUTPUT TRANSISTOR
The output section has been specifically designed for direct drive
of power MOSFETs. It has a totempole configuration which is
capable of up to ±1A of peak current. This will typical result in a
rise and fall time of 50ns into a 1000pf capacitive load. Each
output transistor (source and sink) is capable of supplying 200mA
of continuous current with typical saturation voltages of less than
2.5 volts over -55°C to +125°C junction temperature range. (See
Figure 12 and 13) All parts are designed to minimize the amount
of shoot-thru current which is a result of momentary overlap of
output transistors. This allows a more efficient usage of the IC at
higher frequencies, as well as improving the noise susceptibility
of the device.
:;:-
....-----r--"""T'"---r---..-----,
2.0
'(
w
"«
f-
..J
a
>
z
a
F
«
1.5
1.0
'"'"«
f-
Vl
0.5
o
~-~--~--~-~-~
100
200
300
400
OUTPUT CURRENT-(mAl
~
4.0
1----1f-=~=-=-_;:_::--+---j---:..I
3.0
1----1I----j---+----,."""''-j,j~
Figure 13. Output Saturation Voltage VS. Output
Current and Temperature
I
w
"~
..J
§?
Z
a
F
«
2.0 I-----:A=-::::;;;;;o~~=-+---I-----l
'"~
«
Vl
1.0 .,.'------1I----j---+---j-----1
o
L -__--''----__
100
~
____
200
~
____
300
~
____
400
~
500
OUTPUT CURRENT -(mAl
Figure 12. Output Saturation Voltage vs. Output
Current and Temperature
12-82
500
SILICON
APPLICATION NOTES - SG1542/SG1543/
SG1544/SG3523
GENERAL
PS-13
LINEAR INTEGRATED CIRCUITS
OUTPUT SUPERVISORY CIRCUITS:
A NEW FAMILY OF POWER SUPPLY CONTROL DEVICES
Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
ABSTRACT
This paper describes a series of new monolithic integrated circuits designed to perform all the functions
necessary to monitor and control the outputs of sophisticated power supply systems. Beginning with
a simple over-voltage sensing circuit, these devices range through more versatile and accurate singlefunction units, to all-inclusive devices which contain sensing circuits for both over and under-voltage
conditions, current sensing, SCR crowbar firing, logic outputs, and an accurate independent reference
generator. A description of the operation of each individual element is given together with several
applications which demonstrate their utility.
INTRODUCTION
Recent years have seen the introduction of many sophisticated
integrated circuits for use in controlling the voltage regulation
function of both linear and switching power supply systems. While
these circuits have provided a high degree of performance with a
side benefit of considerable increases in both reliability and cost
savings, they have all addressed the basic function of maintaining
the output voltage constant. Most power supply systems, however, require additional circuitry for monitoring satisfactory performance and providing protection in the event of a fault condition.
These requirements have led to the development of a new class
of power supply element - an Output Supervisory Control Circuit.
OUTPUT
INDICATOR
OUTPUT
GROUND
SENSE 1
SUPERVISORY CONTROL FAMILY MEMBERS
The first integrated circuit developed specifically as a power
supply monitoring device was Motorola's MC3523 available also
as an SG3523 from Silicon General. This device, which is
packaged as an 8-pin minidip, was designed to sense an overvoltage condition, provide an adjustable time delay, and then fire
a high-current SCR crowbar for power supply shutdown. An
improved and interchangeable device, the SG3523A, was later
introduced to provide more tightly specified performance, greater
threshold accuracy, and improved temperature stability. Block
diagrams of these two devices are shown in Figure 1.
SENSE 2
Figure 1. SG3523 Over-Voltage Sensing Circuit. The SG3523
and 3523A conlain an independent reference generator, an input
comparator designed to initiate a selable time delay, and a
second comparator which activates both a crowbar firing current
and a low-level indication signal.
It was soon recognized that with the addition of a few more access
points to this circuit, significant increases in versatility could be
achieved. This led to the development of the SG1542 device
shown in Figure 2. With 14 pins in this OIL package the following
additional features could be offered:
January 1990
12-83
1. Access to the reference generator's output so that one could
take advantage of it's 1% accuracy and 50 ppm T.C.
APPLICATION NOTES - SG1542/SG1543/SG1544/SG3523
2. Uncommitted inputs to the sensing comparator allowing use
for either under or over-voltage sensing as well as the ability
to set threshold levels below 2.6 volts.
3. The addition of a logic level output active when the sensed
voltage is within tolerance, as well as the one which indicates out-of-tolerance.
4. A separate supply terminal for the high current 8CR trigger
allowing greater utilization of this output.
All the functions provide open collector outputs for maximum
flexibility in interfacing with either the power supply or the system
load and, although the 8CR trigger is directly connected only to
the over-voltage sensing circuit, it may be optionally activated by
any of the other outputs or by an external shutdown command.
The 8CR trigger circuit also includes an optional latch with
external reset capability. External capaCitors may be used to
accurately program the sensing circuits for a minimum time
duration of fault before triggering.
UV
UV
SENSE
INDICATE
V+
Vc
VREF
0------1
V,N
GROUND
SCR
TRIGGER
ABOVE
LIMIT
OV
SENSE
SCR.
INV~
TRIGGER
O.V.
INDICATE
C.L
WITHIN
NI
LIMIT
,
(GROUND TO ACTIVATE)
OFFSET /COMP
COMMON
N.t.
SENSE 1
'NV.
SENSE 1
SENSE 2.
Figure 3. The block diagram of the SG1543 Output Supervisory
Circuit includes over-voltage and under-voltage sensing as well as
the capability for current limiting and SCR crowbar triggering.
Figure 2. SG1542 Voltage Sensing and Protection Circuit. The
use of a 14-pin package for the SG1542 provides greater access
to the circuit elements and thus greatly expanded versatility.
Finally, it was decided to build an all-encompassing device which
would include both over and under-voltage sensing as well as a
means for current limiting, all in one integrated circuit. This
resulted in the 16-pin 8G1543, the main subject ofthis paper. The
circuitry ofthe 8G3523, 3523A, and 1542 is equivalentto the OVP
portion ofthe 8G1543 and thus need not be described separately.
Before proceeding with a discussion of the 8G1543, however,
there is one more member of this family worth mentioning. The
8G1544 is identical to the 8G1543, but uses an 18-pin DIL
package to keep the voltage-sensing comparator inputs uncommitted. This adds the ability to sense voltage levels below the
reference voltage to the lengthy list of features offered by the
8G1543. Now, on to a more complete description.
THE SG1543 OUTPUT SUPERVISORY CIRCUIT
To fill the need for this output monitoring and contrOlling function,
the 8G1543 output supervisory circuit shown in Figure 3 was
developed. This devices contains an operational amplifier, a
voltage reference circuit, several comparators, and a high-current
SCR trigger circuit. The functions performed by this device
include over-voltage and under-voltage sensing, current limiting,
and provisions for triggering an external SCR crowbar shutdown.
The 8G1543 circuit may be powered by either the output voltage
to be monitored or a separate bias voltage at any level between
4.5 and 40 volts with a standby current of less than 10mA.
This device is packaged in a standard 16-pin hermetically sealed
ceramic package and is available in both commercial and military
temperature ranges. Before describing in greater detail the
overall functions that this device can perform, it is worth discussing the individual circuits which go into its makeup.
VOLTAGE REFERENCE CIRCUIT
The precision 2.50V reference circuit of the 8G1543 is shown in
Figure 4. This regulator is based upon the well-known band-gap
reference circuit which has the capability of providing very stable
performance over an input voltage range from as low as 4.5V to
as high as 40V. The output is nominally set at 2.5V, but in addition,
is trimmed to remove all effects of production manufacturing
tolerances from the output voltage. In fact, this trimming not only
adjusts the output voltage to within 1% of 2.5V, but in the process,
as shown in Figure 5, also trims the temperature coefficient of
output voltage to better than 50 parts per million per degree C. The
trimming is performed at wafer probe by using controlled energy
sources to blow fusable metal links which short out incremental
values of resistance in the voltage setting network. These
resistors are binarily coded so that three values give eight bits of
12 - 84
APPLICATION NOTES - SG1542/SG1543/SG1544/SG3523
~----~--------------~----~~~N
COMPARATOR SECTION
I;I----,--\i'-=---------------I------ ~I~
Over and under-voltage sensing circuits are identical with only the
input polarity changed between them. The under-voltage circuit
is shown schematically in Figure 6. This configuration in made up
of two comparators in series, each referenced to 2.50 volts, with
the delay terminal at their juncture. The first comparator activates
a current source upon sensing an out-of-tolerance condition and
that current is used to charge an externally selected capacitor to
provide a delay. The second comparator then activates the output
indicating circuit. The overall time delay from input sense to output
indicate, with no external capacitor, is approximately 0.5 microsecond. By adding a capacitor althe delay terminal, the fault must
exist for an interval defined by the time it takes the voltage on the
capacitor to charge from zero to 2.5V before the output comparator can switch. The charging currentforthis capacitor is a constant
250 microamps which provides for a delay of approximately 10
milliseconds per microfarad of capacitance. Since the comparator can discharge in excess of 1OmA, the capacitor is reset in a
fraction of its charge time.
NPN
DIAS
eND
Figure 4. This precision 2.50 volt band-gap reference source is
internally trimmed for ±1 % accuracy in order to eliminate the need
for adjustment potentiometers.
;y
"E
"~
I
DELAY
100
f-
Z
w
U
50
~~~~------'~===-----J:'!
[L
"w
0
u
w
n::
0
::::>
f
w
c.:>
«
60
f-
--"
0
>
tL
0
0
--"
I
z
w
tL
0
40
Figure 11. This typical application for the SG1543 provides linear
foldback current limiting as well as over and under-voltage
protection.
20
In firing an SCR with supply voltages above 5 volts an external
resistor, RG , is used on pin 1 to provide power dissipation limiting
for the SG1543. While the SG1543 will provide up to 400mA of
trigger current, the power limitation of the 16-pin-dual-in-line
package should be held to less than one watt.
0
lK
10K
lOOK
1M
10M
FREQUENCY-(Hz)
In this application, current limiting is performed by sensing the
current in the positive supply line with fold-back provided by the
action of R2 and Ra' A fixed thresholdforthe amplifier is set by R1
which is connected between pin 12 and ground.
Figure 10. C.L. Amplifier Frequency Response. With BOdS gain
and 5MHz bandwidth, the current sense amplifier provides a wide
dynamic response, even when modified with external passive
components.
Diode D1 and resistor Rc are used only if it is necessary to
increase the frequency response by operating the output transistor at higher current and/or isolating the load from Rc and C, when
the amplifier is off.
Although the SG1543 could have been driven from the output
voltage to be monitored, it would lose control when that output
voltage fell to approximately 3V. This would, of course, preclude
the use of the current limit function where short circuit protection
must be provided.
12 - 87
II
APPLICATION NOTES - SG1542/SG1543/SG1544/SG3523
The values for the external components used in conjunction with
the SG1543 application of Figure 11 are determined as follows:
Current limit input threshold, V TH
~ 1~00
9
Cs is determined by the current loop dynamics
Peak current to load, Ip"
Short circuit current, Ise =
V TH
Rse
+
~
Rsc
( __R_2_)
R2 + R3
V TH
Rse
Figure 13. DC Converter With Isolated Current Limiting. Current
limiting for a switching inverter is readily accomplished, even with
a requirement for input-output isolation.
2.5 (R.+R5+R6)
High output voltage limit, Va (High) = ---'-'-'::--"----"'R6
Voltage sensing delay, tD
=10,000 CD
V -5
SRC trigger power limiting resistor, RG > ~
CURRENT SENSING OPTIONS
It is important to remember that all the features of the SG1543
apply equally to either linear or switching power supplies. Figure
12, for example, shows the current sensing amplifier in the
SG1543 used to provide fold back current limiting for a linear
regulator utilizing the SG723. To answer the question of why one
would use the SG1543 for current limiting when that capability is
built into the SG723, there are two important benefits: low sensing
threshold voltage (whatever is selected vs. a fixed 700mV) and
much higher gain for a very sharp transition from voltage to current
feedback.
INPUT
The last application suggests another use for the current sense
amplifier completely disassociated with current. This is shown in
Figure 14 where it is used in conjunction with the very excellent
characteristic of the 2.50 volt reference contained within the
SG1543 to provide an isolated voltage feedback signal. The
SG1543's amplifier provides the gain and the overall loop compensation network, and drives a high-frequency opto-coupler
which feeds into the unity-gain configured error amplifier of the
SG1524. A designer should recognize that there are many
possible variations on this theme, including taking the error signal
from the collector of the opto-coupler, feeding into the output ofthe
SG1524's error amplifier such that this amplifier provides a
startup signal. Then the SG1543 may be powered directly from
the output eliminating the need for an isolated bias supply.
VOLTfG~ 0 - - , - - - - - - ' - - - - - - - - - - , - - - - - - ,
Figure 12. Linear Foldback Current Limiting. The SG1543 is
equally adaptable to either linear or switching supplies. The
circuit above shows a substantially improved current limit function
for a linear SG723 voltage regulator.
Figure 14. The current sense amplifier can also be used in
conjunction with the SG1543's reference to provide a stable,
isolated voltage feedback signal.
Output current limiting for a switching supply which gets its control
from an SG1524 regulating pulse width modulator is shown in
Figure 13. Here, fold back is not included but an optical coupler for
isolation has been added. It should be noted that all the lowcurrent outputs of the SG1543 are equally well suited for driving
optical couplers.
One final possible use for the current limit amplifier is to provide
complete shutdown of the power supply rather than linear voltage
reduction upon sensing an over-current condition. This function
is shown in Figure 15 where the current limit amplifier is used as
a comparator with the output terminal connected to the remote
activation terminal for the SCR trigger. In this case, sensing is
12 - 88
APPLICATION NOTES - SG1542/SG1543/SG1544/SG3523
done in the ground line. There is no offset added to the current limit
amplifier but instead a threshold is provided by the action otA, and
R2 from the 2.50V reference signal. When an over-current
condition is sensed and maintained for a period of time determined by a capacitor Co on pin 12, then the output transistor will
conduct, activating the SCR trigger and shutting down the power
supply.
~~y.------r---10 50"9 COr.lPARAT~
------------------,
"'' 'IN
POSn1\IE
SUPPLY
I
I
I
I
1.4AIN SUPPLY B U S S - - - - - - - - - - - - - - - - r - -
r----------
16
I
I
I
I
I
SO,
·CROIl9AR"
~
I
Figure 16. Sensing Multiple Supply Voltages. Addition of a simple
quad comparator allows multiple voltage sensing of positive or
negative levels.
SUPPL~E~~~-->--.;"""-'f_-----------<-
Figure 15. Overcurrent Shutdown. The current sense amplifier
may also be used as a high-gain comparator to shut down the
supply upon over-current.
SENSING MULTIPLE OUTPUT VOLTAGES
Many power supply systems have several output voltages which
need to be monitored. This is easily done with the SG1543
because of the capability for remote activation and the availability of the reference voltage for use with external Circuitry. A quad
comparator like the SG139 which also has open collector outputs
can be used to monitor several additional output voltages. As
shown in Figure 16, the SG1543 is used to provide both over and
under-voltage protection on a main positive supply. The additional comparators within the SG 139 can be used to monitor either
positive or negative supply voltages depending on whether one
uses the 2.5V signal or ground as the reference potential. The
output comparators of each collector are tied together to the
remote activation terminal such that the operation of any single
comparator in either the SG1543 or the SG139 will activate the
SCR trigger shutdown circuil. Note thatgrounding the remote
activation terminal also provides an output on the over-voltage
indicating circuit; therefore, this output on pin 4 can be used as a
master power supply-condition indicator which will provide a low
signal if any output voltage that is being monitored is outside its
allowable tolerance.
Figure 17. Under Voltage Shutdown. In addition to output
monitoring, the under-voltage circuit can be used to inhibit the
output if the input voltage is too low for satisfactory performance.
As shown in figure 18, the under-voltage circuit can be used to
monitor the AC input voltage to a power supply. An isolation
transformer and rectifier are used to provide a rectified AC signal
to the input of the under-voltage comparator. The signal is
compared with the 2.50V reference, activating the first stage ofthe
comparator with each transition toward zero. With proper selection of the delay capacitor, no output is provided unless some
~11f_-+-""
UNDER-VOLTAGE SENSING
In addition to normal low-output voltage monitoring, the undervoltage sensing circuit has considerable possibilities in monitoring the input voltage to a power supply system. For example, in
Figure 17, this circuit is used to measure the input DC voltage to
an SG723 regulator and keep the output completely off whenever
the input is lower than the minimum required for satisfactory
operation of the SG723. The same protective feature when
applied to a switch-mode regulator, is even more important since
it keeps the switching transistors off until the oscillator stabilizes.
12-89
~~ui
-
25V
PINB~-2.5V
DELAY
Figure 18. SG1543 Input Line MonitorThe under-voltage sensing
circuit can also be used to monitor the AC input voltage and
provide a power failure signal before the power supply output
voltage begins to fall.
II
APPLICATION NOTES - SG1542/SG1543/SG1544/SG3523
number of input pulses are missing at which time the first comparator allows the charging of the capacitor to 2.50 volts which
activates the output circuit. In this way, the under-voltage circuit
provides an immediate indication of failure, even for one or two
cycles. This provides an early warning indication that the power
supply output voltage is going to drop while taking advantage of
the holdup capability provided by normal electrolytic capacitor
storage within the power supply system.
Like other parts of the SG1543, the under-voltage circuit is not
limited to its primary function. Figure 19 demonstrates its use as
an over-temperature indicator by using the well-defined temperature coefficient of a Darlington transistor's V BE as a sensor.
Divider R,-R 2 establishes a fixed threshold equal to the 2N2723's
V BE at the desired temperature limit. Below that limit, the transistor
is off and Rc back-biases the input to the U.V. sensor. Manyother
transistors could be used; however, the small case of the 2N2723
makes good thermal coupling relatively easy.
By providing all of these diagnostic and protective features within
one integrated circuit, a new class of control device has been
generated to provide overall performance monitoring and control
of sophisticated power supply systems. Thus, the SG 1543 further
enhances the inventory of building block components available to
the power supply system designer providing new options in
implementing increased performance at lower cost.
12-90
Figure 19. Over-Temperature Indication. Another use of the
under-voltage circuit is to provide an over-temperature indicalion
using the -4mVrC VBE tempco of the 2N2723 as a sensor.
APPLICATION NOTES - SG1548
SILICON
GENERAL
PS-14
LINEAR INTEGRATED CIRCUITS
A CONCEPTUALLY NEW QUAD POWER FAULT
MONITOR CIRCUIT
by Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
Edited by Reza Amirani
ABSTRACT
A comprehensive fault monitoring system in a single 16-pin IC is described. The new circuit provides
overvoltage and undervoltage supervision of four DC power supplies simultaneously. In addition a
uniquely flexible pin-out permits AC line voltage monitoring, real-time line clock generation, or
programmable switching supply undervoltage lockout protection. All fault thresholds are adjustable to
a high degree of accuracy using a minimum of external passive components. A number of typical
application examples are given to clarify the concepts discussed.
INTRODUCTION
As the complexity of modern electronic systems grows, the
number of supply voltages necessary to support the circuitry has
also increased. Even the simplest home computer typically
requires +5 volts for the logic, :1:12 or :1:15 volts for the analog
circuits, and perhaps +24 or +28 volts for the printer or disk drive.
The task of supervising these multiple voltages for proper tolerance has traditionally required a substantial number of precision
components: a voltage reference, resistors, timing capacitors, op
amps, comparators, and logic gates. An additional penalty was
paid in board space consumption. Consequently, in an attempt to
shave costs, the supervisory function was often eliminated entirely. While this action resulted in meeting budgetforthe supply,
the money saved was often given out again many times overwhen
a system malfunction occurred in the field and a service engineer
had to tediously check each supply voltage.
The availability of a new integrated circuit which can monitor four
DC supplies and the AC line simultaneously now allows the power
systems designer to implement fault monitoring at lower cost and
with much reduced board space. This new device utilizes the
strengths of monolithic linear technology to create preciselymatched components at high density on a silicon chip. Called the
SG1548 Quad Power Fault Monitor, its functional block diagram
is shown in Figure 1.
FUNCTIONAL DESCRIPTION
1I<~O-=------_---.J
The circuit consists of a precision reference regulator, a fault
window generator, analog OR and AND circuitry for selecting
most positive and most negative voltages, threshold comparators, delay logic, open-collector output drivers, an inverting
amplifier, and a mUltipurpose line sense comparator with uncommitted collector and emitter outputs.
Figure 1. Block Diagram of the SG1548 Quad Power Fault Monitor
January 1990
12 - 91
APPLICATION NOTES - SG1548
The most positive voltage at the four Sense inputs is compared
with the upper or overvoltage threshold, and the most negative
input is routed to the undervoltage comparator. The comparator
outputs are connected to their respective output drivers and two
AND logic gates. The drivers are inhibited by the delay logic,
which requires that either an overvoltage fault or undervoltage
fault persists for a pre-set time interval. A single capacitor at the
Delay pin sets the time interval, which is C x 2.5 x 104 seconds. If
a negative voltage must be monitored, it can be mirrored into a
positive voltage using the inverter amplifier. Special clamp
circuitry inside the SG1548 prevents the amplifier from locking up
if Pin 15 is pulled below ground. Now let's look at the operation
of each subset in detail.
VOLTAGE REFERENCE
The reference circuit is a low-drift bandgap design which generates a precise +2.50 volts ±1 % at Pin 3. It isfullyfunctional at input
voltages as low as +4.5 volts, and provides up to 1OmA of output
current. Special p-compensation circuitry provides immunity to
process variations and achieves typical 1mV line and 3mV load
regulation. Internal current limiting protects the Ie against accidental shorts to ground.
percentage of V REF . Op amp A2 is connected as an inverter
working at a common mode voltage equal to VREF' Its transfer
function is given by:
VUPPER
R2
=-R,
{t.V
±
Vas, ± V as2} + V REF ± V as2
[2]
where V as2 is the input offset voltage of A2, and bias current errors
are assumed to be very small.
R .IS nearly 1 , then
If _2
R,
VUPPER = VREF + t.V ± Vas, ± 2Vas2
[3]
Since R1 = R2 = 2K and the resistor match very well over the
temperature, then the above assumptions about bias current error
and resistor ratio are correct. Therefore the limit as to how small
t. V can be is approximately 3 times the offset voltage, neglecting
comparator offsets. If a worst case value of 8mV is assumed, the
smallest value of t. V is 24mV, corresponding to a fault tolerance
of±1%. Since this is the same order as the initial accuracy of the
reference, ±2% is recommended as the tightest setting for the
tolerance window.
DUAL CHANNEL DELAY WITH A SINGLE CAPACITOR
FAULT WINDOW GENERATOR
The fault window generator is the heart of the Quad Power Fault
Monitor. This section generates an upper overvoltage and lower
undervoltage threshold centered about the +2.5 volt reference. A
precision tracking regulator utilizing two operational amplifiers
and a pair of ratioed resistors produce the tracking action, as
shown in Figure 2.
An external voltage derived from the reference is applied to Pin 1.
This voltage represents the lower boundary of the tolerance
window. Op ampA 1 is connected as a unity-gain buffer, providing
a low input bias current and a low impedance outputfordriving the
remaining circuitry. The transfer function through A 1 is simply:
In supervisory circuits, delay is frequently required to reject false
fault reports which could result from switching supply spikes or
transients due to step load changes. The delay circuit in the
SG1548 requires only one capacitor to implement the delay
function for both the overvoltage and undervoltage channels.
The circuit depends on two factors for low false alarm rates:
1. Reports due to noise are of short duration compared to the
program delay.
2. Noise causing false threshold crossings in each channel is
essentially uncorrelated.
[1]
where Vas, isthe input offset voltage ofA1 ,and t.Vissomesmall
----r---
When all four voltages at the Sense pins fall within the set fault
tolerance band, the output of each fault comparator is LOW. The
VUPPER
+f'N
VREF
---I;f-----tN
____ L___
VLOWER
' - - - - - - - - - - - - VLOWER
Figure 2. Generating a Precision Fault Tolerance Window
12- 92
APPLICATION NOTES - SG1548
output of the 2-input NOR gate is HIGH, turning on the discharge
transistor 01. The Delay pin is held at ground. This is below the
+ 1.25 volt trip threshold of the delay comparator, resulting in a
LOW logic level to each of the output AND gates. Since both
inputs must be HIGH to turn on the output drivers, no fault
indication is possible.
O.V fAULT
-,-------.v;;-;---------r,
u.v.
---------------L....J
fAULT
Figure 3. False Alarm Rejection Using a Single Capacitor
When one of the sensed voltages crosses a fault threshold, the
fault comparator switches HIGH, turning off 01. The delay pin
voltage rises linearly from 0 volts as the 50~ current source
charges the daily capacitor. If the fault condition persists long
enough, the capacitor will charge to + 1.25 volts, tripping the delay
comparator, which has hysteresis to eliminate jitter dueto the slow
ramp. The HIGH output level from the comparator enables both
output drivers, permitting an overvoltage and/or undervoltage
indication as appropriate.
UNE SENSE
~COLLECTOR
OUTPUT
+§
Dl
+2.5V
EMITTER OUTPUT
voltage to a positive one is optimized for inverter operation with the
summing node at ground. The amplifier has a minimum open loop
gain of 72dB, and is internally compensated for unity gain stability.
Like the AC line Sense input pin, the Inverting Input pin can be
pulled below ground by nature of the external circuitry. To prevent
the possibility of latch-up under these conditions, clamp circuitry
as illustrated in Figure 5 exists at the pin. These protective
components clamp negative excursions to -0.5VBE or approximately -0.3 volts at +25°C. This prevents the substrate diode from
conducting and activating any parasitic SCRs in the IC. An
additional diode limits the maximum positive input voltage to 1 V BE
to eliminate the possibility of latch up in the direction.
Input offset characteristics are further improved with a special
Kelvin grounding scheme for the non-inverting input. Separate
bounding pads exist at the periphery of the chip for power ground
and the op amp input. The bond wires become common only at
the IC package pin itself, eliminating the errors due to ground
drops in the circuit metalization.
A performance factor called "inversion error" can be defined from
the amplifier's electrical parameters which quantizes the total
deviation from ideal inversion. It includes the effects of input offset
voltage, input bias current, input offset current, and finite openloop voltage gain. For unity-gain operation with perfect 1OKl1 OK
gain setting resistors, the maximum inversion error for the
SG1548 is 26.5mV or 1.06% referred to the +2.5 volts fault
window center. In most applications the error will be less. For
example, if -15 volts is converted to +2.5 volts, the closed loop
gain will be -1/6. The output stage can source at least 5mA, so 6K1
1K gain resistors can be used. With these values the maximum
inversion error falls to 13.5mV or 0.5%. The actual resistor
tolerances will, of course, degrade this further.
Figure 4. Block Diagram of the AC Line Sense Circuit
AC LINE SENSE COMPARATOR
The line Sense section of the SG1548 is a high-gain comparator
with 25mV of hysteresis referenced to the precision +2.5 volt
threshold voltage. The output transistor is rated at 40 volts and
1OmA, and has uncommitted collector and emitter connections for
either inverting or non-inverting operation. A unique clamp diode
structure (01) on the input adds to the versatility of this section,
since it is specified for both forward and reverse conduction at
1mAo (Most junction-isolated integrated circuits can behave
strangely or self-destruct if any pin is driven negative with respect
to the substrate. TheAC Line Sense pin was specifically designed
to operate in this mode, thereby eliminating the need for an
external clamp diode).
INV. INPUT n----1~--__1-_+--__I
INV. OUTPUT
GROUND Q-4~---4~--'-~r--....,
Figure 5. Protective Circuitry at the Inverter Input Terminals
SETIING THE FAULT TOLERANCE
ON-CHIP INVERTING AMPLIFIER
The operational amplifier provided for converting a negative
The fault tolerance window is set by applying a voltage slightly
less than the +2.50 volt reference to the Lower Threshold pin. In
12 - 93
II
APPLICATION NOTES - SG1548
the example shown in Figure 6, a :t2% window is programmed
with the divider network formed by RA and Re' The maximum input
bias current at Pin 1 is 1.0I-lA, so the divider current is chosen to
be three orders of magnitude greater to minimize threshold shifts.
With the resistor values shown, +2.450 volts is applied to Pin 1,
selling up nominal :t50mV threshold values about the +2.500
reference. Resistors should be oflhe same type so thallemperature coefficients will track, maintaining a constant divider ratio.
The allowable voltage range on the adjustment pin is +2.45 volts
to +1.50 volts, corresponding to :t2% and :t40% fault tolerance
bands.
Given: 1. Nominal Input Voltage - VNOM
2. A programmed window tolerance - X%
3. A desired fault tolerance - Y%
1. Calculate: P = (VNOM - 2.5)/2.5
2. Choose R. such that:
R.O!: (5) (V-X) ( P;l)
3. Calculate R1 and R3 by:
R1 = PRo
X
PRo
R3=(X_Y)(~)
SG1548
RA
51.1Q
4. Calculate reference sink current:
I
_ (2.5) (X)
SINK R3
RS
2.49K
ISINK calculated should be less than 500 !!A.
5. Check your calculation by calculating fault tolerance Y:
R/R3
Y=(l +R/R) (X)
Figure 6. Programming .the FauH Tolerance Window
1
[%]
•
This value should be very close to your desired value of Y.
IMPLEMENTING MULTIPLE TOLERANCES
In actual practice, some power supply tolerances may.be more
critical than others. For example, 1)10st +5 volt logic can withstand
:tl 0% variations without malfunction, whereas the analog circuitry
might require :t5% accuracy. Multiple tolerances can easily be
obtained with the SG1548 using the technique shown in Figure 7.
EXAMPLE:
Given: 1. VNOM = 5V
2. X=5%
3.Y=10%
1. Calculate P:
P = 5 - 2.5 = 1
25
"REF
2. Choose R.:
+5V
±10%
R1
1.24K
SG1548
SENSE 1
-15V
±
5%
Rs
6.19K
R.O!: (5) (1~0~5) (2) = .50 KO
VREF
RA
1240
SENSE 2
Choose R. = 1.24K
L. THRESH.
Rs
SENSE 3
3. Calculate R1 and R3:
2.37K
SENSE 4
GROUND
R1 = R. = 1.24K
R = (_5_) ( 1.24 ) = 620 0
3
10 - 5
2
Figure 7. Implementing Multiple Tolerances
Choose R3 = 6190
The Quad Power Fault Monitor is first programmed for the tightest
tolerance required. In this case the +15 volt supply must be held
within ±5% of its nominal value, so RA and Re are chosen such that
±125mV window edges are set at Pin 1, and pin 13 is set at2.5v
by R4 and R5 divider network. Next, the required tolerance of
:t 10% for the +5v input is set by adding a resistor R3 from the
sense pin to the 2.5v reference. In this section a set offormulas
are derived to calculate Rl, R2, and R3 conSidering the effect of
the sink current capability of the reference voltage.
4. Calculate reference sink current:
I
= (2.5 x 0.05) = 202
SINK
619
!!A
5. Check Calculation:
12 - 94
Y = (1 + 1.24/0.619
1 + 1.241 1.24
) (5) = 10.008%
APPLICATION NOTES - SG1548
I~VERTING
A NEGATIVE SUPPLY
Conversion of a negative source to +2.50 volts is straightforward,
as shown in Figure 8. The op amp is operated at a closed loop gain
less than unity. However, since the amplifier is internally compensated for unity gain, it is possible to monitor voltages less than 2.5
volts (gain greater then unity) without additional components for
stability.
SG1548
DELAY
CDELAY
2.49K
FIGURE 10. Suge Limit Circuit for Large Delay Capacitors
5.18K
-5.2V 0--'V'\f\r--{
+2.50V
MONITORING THE AC LINE
FIGURE 8. Inverting and Scaling a Negative Voltage
DETERMINING FAULT DELAY
Fault delay as a function of delay capacitor on Pin 8 is given by the
graph in Figure 9. The line reflects the time required to charge a
given capacitor to +1.25 volts with a nominal501-lA current source.
Delays beyond several hundred milliseconds can be obtained, but
for capacitor values beyond 5ftF, the surge limiting circuit shown
in Figure lOis recommended. The 1000hm resistor limits the
peak discharge current into the SG1548, while the external PNP
transistor provides a high peak-current discharge path for the
delay capacitor.
1s
E
r:s
UJ
0
'::;
::>
"-
""
,
200
r~
"\
\I \~
I \ II \ J
IV
~ n.
~ ~
"""" ......... ......... .......... r-- .........
, "
I
if'
100
50
L
vii'
f=
f:::
/
20
~
0.5
5
~
HORIZONTAL: 10mSEC/DIV.
UPPER TRACE: AC LINE
MIODLE TRACE: PIN 5 AT 5V/DIV.
LOWER TRACE: LINE SENSE OUTPUT AT 5V IDIV.
III
2
1\ {
('
oJ
III
~III
f-
500
Single-cycle AC line dropouts can be detected with the circuit
shown in Figure 11. A positive half cycle is clipped to a precise
level using the internal Zener and a 3K source resistor. The
discharge circuit consisting of 180K and the 0.1 ftF capacitor
control the voltage decay so that the +2.5 volt trip pOint is not
reached with normal sinusoidal line conditions. A single-cycle
dropout will provide an extra 16.7 milliseconds discharge time, as
shown in Figure 12, causing the Line Fault output to switch LOW.
10
20
50
FIGURE 12. Response to a Single-Cycle Line Dropout
CDELAy-(jJF)
FIGURE 9. Graph of Fault Delay vs. Delay Capacitor
5V
3K
LINE FAULT
""' 311 .
6_V_R_M_S_--._1_B_O_K_--{
FIGURE 11. Monitoring the AC Line for Sindle-Cycle Dropout
12 - 95
II
APPLICATION NOTES - SG1548
LINE CLOCK GENERATION
A logic clock derived from the line frequency can be obtained with
a minimal number of components, as illustrated in Figure 13. The
internal clamp diode is used in both forward and reverse conduction modes, with the 10K input resistor limiting peak input current
to less than 1mAo Waveforms obtained with this circuit are shown
in Figure 14.
LINE CLOCK
UNDERVOLTAGE LOCKOUT
Figure 15A and B shows two methods of using the Li.ne Sense
comparator for inhibiting power supply start-up until some minimum supply voltage has been reached. In the first case a HIGHgoing shutdown signal to the PWM control is generated until V,N
causes the voltage at Pin 5 to exceed +2.5 volts. Ifthe PWM is on
the primary side of the power transformer, the Line Sense Output
can directly drive an optocoupler. In the second case the line
sense comparator is used to gate a bias supply ON when the
proper working voltage has been reached.
EXPANDING THE QUAD POWER FAULT MONITOR
The SG1548 is readily expandable to include additional positive
and negative supplies. One half of an inexpensive quad comparator Ie is required for each supply, as shown in Figure 16.
FIGURE 13. Generating an AC Line Clock
Ir\
,I
(\
f'
I \1
,
-, n
'--
Lf-I
r1\)f\
L.. ....
'U
n
M
I'--
,
Lf--I
J
\
\
'-
J
HORIZONTAL: 10mSEC/DIV.
UPPER TRACE: AC LINE
MIDDLE TRACE: PIN 5 AT 5V /DIV.
LOWER TRACE: LINE SENSE OUTPUT AT 5V/DIV.
FIGURE 14. Waveforms Produced by the Line Clock
FIGURE 16. Expanding the SG1548 to Monitor Additional Supplies
PWM
BIAS SUPPLY
'---~_ _
PWM
SHUTDOWN
FIGURE 15A & 156. Using the Line Sense for Undervoltage Lockout
12 - 96
APPLICATION NOTES - SG1548
For an additional positive supply, the comparators are referenced
to the +2.5 volt regulator olthe SG1548. The monitored supply is
divided down by resistors R1 through R3. When the supply drops
a given percent, the upper comparator switches LOW. Since the
fault outputs of the SG1548 are active LOW, the indication from
the quad comparator can be wire-ORed to the undervoltage fault
output line. Similarly, if the supply voltage increases beyond a
preset limit, the overvoltage fault line will be pulled LOW by the
second comparator.
The negative supply is handled similarly, except that the comparators are referenced to ground, and the resistive divider R4
through R6 is returned to the +2.5 volt reference. The 139 quad
comparator will work correctly as long as the inputs are not pulled
below -0.3 volts. If this possibility exists, a Schottky clamp diode
should be used at Pin 10 to preserve the overvoltage indication in
case of a massive negative overdrive at the divider input.
In this case, four DC voltages are monitored: three positive and
one negative. Three different fault tolerances are mechanized,
and the AC line is checked for single-cycle dropout.
The ±15 volt supplies are the most critical, requiring ±5% accuracy. The 1240hm/2.37K divider from the reference sets this
tolerance in the fault window generator. The -15 volt supply is
converted to +2.50 volts with the inversion amplifier on the chip
and applied to one of the Sense inputs. The +5 and +24 volt
supplies are not as critical, requiring ±10% and ±20% respectively. Divider resistors to the reference are used to scale the
effective windows accordingly. The single 5flF capacitor provides
125 milliseconds of delay before an out-of-tolerance fault is
reported.
All this is accomplished with one 16-pin integrated circuit and 14
resistors, 2 capacitors, a low-current diode, and a line isolation
transformer, which can be part of the bias supply.
A COMPREHENSIVE EXAMPLE
CONCLUSION
Each section olthe SG1548 Quad Power Fault Monitor has been
described in detail. Now it is time to put all the pieces together and
show power supply supervision in an actual system. For our
example we will use the hypothetical personal computer mentioned at the beginning of this paper. Figure 17 shows all the
components required.
The opportunity to realize comprehensive power supply fault
monitoring with low component count is a reality with the introduction of the SG1548 Quad Power Fault Monitor. A combination of
flexible architecture combined with innovative circuit design techniques has resulted in a supervisory function with excellent
accuracy and repeatability overthe full military temperature range
of -55'C to +125°C.
FIGURE 17. Monitoring Four DC Supplies and the AC Line
•
12 - 97
APPLICATION NOTES - 8G1548
APPENDIX· A
From the schematic of figure 2, we have:
Derivation of over voltage trip in terms of R" R2, R3, R., R.,
Looking at Figure 1:
Lower Threshold voltage is calculated by:
R
VL = --"-VREF = VREF -/IN
RB+ RA
where IN=
~ VREF
and writing K.C.L. for Vr node, we get:
(1)
I, = 12 + 13
(2)
Vov-Vr=l+ Vr-VREF
R,
R2
R3
RA + RB
ap-amp (U2) is configured as a unity gain follower, therefore:
R,
or:
R,
Vov = (1+-)(VREF +!;.V) + - !;.V
R2
R3
RA
where IN = - - - VREF
RA + RB
Equation (4) can only hold i{the following is true:
Upper threshold is calculated as:
(4)
(4-a) 12 » IBIAS
where: IBIAS is the bias current of U3
comparator
(4-b) 13 < ISINKMAX
where: ISINK MAX is the maximum
sink current capability of
the reference voltage.
and
R
R
Vo=(1 +R)VREf-RVL=2VREF-VL
Derivation of equation for R3:
But VL was calculated to be:
Assumtion:
(2-a)
Vov,
VOV2
x
y
Vo = 2 VREF - (VREF -/IN) = VREF +!;'V
We will call the output of U1 op-amp upper threshold UMIT and
designate it by VU' so:
From the definitions of x and y we get:
(3)
Next we will analyze the circuitry associate with a.v sensing
circuit. We also assume, it is required to have higher threshold
voltage setting than the one being programmed by R., R. divider.
"a.v trip pOint set by R., R. (lower threshold)
",a.v trip point desired (VOV2 > Vov ,)
" percent voltage above nominal for Vov,
" percent voltage above nominal for VOV2
Vov, = (x + 1) V NOM
VOV2 = (y + 1) VNOM
(7)
(8)
We also know that:
R,
(9)
Vov, = (VREF + !;'V)(1 + - )
R2
and from equation (4)
R,
,R,
VOV2 = (VREF + !;'V)(1 + - ) + DV
(10)
R2
R3
Replacing (7) and (8) into (9) and (10) and subtracting (9) from
(10) we get:
(11)
or
R3
Figure 2
12-98
R, R2
=-R, + R2
1
/IN
x -- x -y-X
VREF
(12)
APPLICATION NOTES - SG1548
We also know that the relation between V L and V REF is:
VL = (1 - x) V REF
Using equations (17), (19) and (15) we can calculate R1, R2, and
R3 values.
(13)
To calculate the reference sink current we use:
Since VL is x percentage lower than VREF by R3, R4 divider,
putting (13) into equation (2-a) we get:
!W = XV AEF
I
=~
SINK
R3
R,
Replacing (14) into (12) we get the result:
(15)
or
R,
R,
R,
VOV=VAEF(1+-)+f..V(1 + - + - )
R2
R2
R3
From the inequality of 4-b we get:
~
/:"v
10.3
(20)
putting equation (8) in (20) we get:
R,
R,
R,
VNOM+yVNOM=VAEF(1+-)+f..V(1+-R +-R)
R2
2
3
(16)
(KR)
R,
VOV=(VAEF+f..V)(1 +-)+-f..V
R2
R3
Deriving a set of formulas for R" R2, R3 calculation:
R3 >=
2.5x
R3
To derive the equation for checking we start by equation (4):
(14)
R R
1
R3=(-'_2) ( - - )
R, + R2
y-x
XVAEF
R3
(21)
IBIAS maximum for 1548 comparator is 1mA.
Replacing (16-a) into (21) we get:
we know that:
R2
V NOM =
R+R
,
2
f..V
R,
R,
y=--(1 + - + - )
V NOM
R2
R3
(16-a)
V
-V
R1 = (NOM
REF) R2 = PR 2
V AEF
Replacing (14) and (16-a) into (22) we get:
(17)
Y=
x
(1
R
+Ft)
2
or
x
PR 2
2
P
(~)
where R2 [KR]
x
R
3
(1+~)
R2
(y-:-x) (~) >f..V
or R > (f..V) (J:...±...l)
~
Y = (1 +
From equation (15), (16) and (17) we get:
(18)
From equation (14) we have:
f..V = XV AEF
and replacing VREF by 2.5 in equation 18) we get:
(19)
12 - 99
R
(1 + - ' + - ' )
R2
R3
R
(22)
12-100
APPLICATION NOTES - SG1549
SILICON
riM
GENERAL
PS-15
LINEAR INTEGRATED CIRCUITS
PROTECT YOUR SWITCHERS WITH DIGITAL
CURRENT LIMITING
A New Current Sense Latch IC Provides Pulse-by-Pulse Current Control
Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
INTRODUCTION
Another new class of integrated circuits, designed specifically to
ease the plight of the switch-mode power supply designer, has
just been established with the introduction ofthe SG1549 Current
Sense Latch IC. Although there have been many IC products
developed over the past few years to provide simple methods of
voltage control for switching supplies, the SG1549 is the first to
specifically address and take a fresh approach to the problem of
current control. Almost all existing PWM chips have included
some type of circuit for current limiting, but these have all used the
same techniques as linear regulators; that is, a current sense
amplifier generates an error signal linearly proportional to load
current which, after reaching an established threshold, takes
command away from a voltage control amplifier. Thus, upon
overload, the power supply switches from a voltage feedback loop
to a separate currentfeedback path. Each loop must be stabilized
separately and, because of the output filter, stable performance
along with a reaction fast enough to protect the high-speed
switching transistors is difficult to achieve. What is needed for
optimum protection is a circuit which operates at the switching frequency and immediately turns off the main current-carrying
switching transistors upon current overload. Turn-off must be
rapid, without allowing the transistors any appreciable time in their
linear operating region, and with no oscillation or multiple-pulsing.
would otherwise allow the transistor to return to conduction.
Including a latch means a provision for reset must also be
provided.
All of this and more is offered by the SG1549 Current Sense Latch
IC. From the block diagram of this device, it can be seen that the
circuit includes a comparator with positive feedback, a means for
establishing an input threshold of 1OOmV, a reset circuit, complementary outputs, and a high voltage level-shifting circuit. This
device is designed to be completely compatible with many commonly-used Regulating PWM controllC's such as the SG1524,
MC3420, and the TL494. Requiring only 2mA of supply current,
the enter circuit can be operated from the reference voltage
available with these chips, with reset accomplished by their clock
output signals.
+Vs
HI CM +
INPUT
HI
OUTPUT
La CM
INPUT
A DIGITAL CURRENT LIMITER
The optimum approach to switch-mode current limiting is to treat
each on-cycle as a separate problem. That is, pulse-by-pulse
current limiting. This is implemented by a device-monitoring
current build-up each time the power supply's switching transistor conducts and, upon sensing an overcurrent condition, immediately turning the transistor off and holding it off for the duration
of that normally on period. Such a circuit must have a latch, as
once turn-off is achieved, the removal of the overcurrent signal
CLOCK
RESET
La
OUTPUT
Figure 1. The SG1549 Current Sense Latch IC contains
provision for senSing a current threshhold over a wide voltage
range. Complementary outputs and a latch with reset are also
a part of this new protection circuil.
Although obviously designed for use with switch-mode power
supplies, the SG1549 has broader application as a general
purpose, low-threshold latch. A clock Signal is not the only way to
provide reset; that function may also be accomplished by any
operation which will momentarily pull the reset pin high.
January t 990
12 -101
•
APPLICATION NOTES - SG1549
CIRCUIT OPERATION
For a detailed understanding of the operation of this device, refer
to the schematic of Figure 2. With a +5 volt supply, a threshold
reference is established by a current through R3. This current is
mirrored by Q7 to provide a constant 200JlA through Rll , thereby
holding one inputlo the comparator at 1OOmV above ground. That
same current is mirrored through Q4 to the floating threshold
circuitol Ql-Q3, Dl, and Rl. This portion olthe circuit will convert
a differential voltage between pins 1 and 2 into an identical voltage
across R2. It will do this accurately while allowing the absolute
voltage on pins 1 and 2 to range from 2 to 40 volts with respect to
ground.
between these two chips couldn't be easier. The value for RSC
is determined by dividing the 1OOmV input threshold QY the peak
current desired. High frequency noise, or switching transients can
usually be eliminated by a small capacitor between pins 3 and 4.
The current shutdown command can be coupled into the SG1524
SWITCH
+vrN
o-----,----'lN>--r-----------"
COMP
,---r--------r-------T-T----D',
Rc
Cc
COMMON o--<-------------+----------~----J----0
Figure 3. Using the SG1549 to sense input current to a
simple buck converter and interface directly to a PWM
control Ie such as the SG1524.
~
OUTPUT
Figure 2. The heart of the SG1549 is a high-speed comparator
together with an input thresh hold level-shifting circuit.
Since the other input to the comparator is tied to pin 3, it can be
seen that the comparator will switch when the voltage on pin 3
rises to 1OOmV, regardless of whether that voltage is applied to pin
3 directly or differentially between pins 1 and 2.
Once the comparator switches, positive feedback provided by
Q17 and R14 will hold it latched until a reset signal, effected by
raising pin 7 above 2 volts, momentarily increases the threshold
returning the circuit to its initial state.
Transistor Q17 also provides two outputs: a high-going signal on
pin 6 which can source 2mA and a open-collector saturating
transistor on pin 5 which can sink more than 10mA. With
complementary outputs, a variety of shutdown options are offered. Typical delay times for the SG1549 are lS0nSec from the
LO CM input and 300nSec from HI CM to the outputs.
HIGH LINE SENSING
A very straightforward application of the SG1549 is its use for
current sensing in the input line. This switching regulator is shown
in Figure 3. The switching regulator is shown implemented with
the SG1524 PWM control IC and it can be seen that interfacing
by either connecting the HI-OUT, pin 6 to the SG1524's shutdown
pin or, as shown here, using the LO-OUT pin to pull the compensation terminal low. In either case, activation of the current sense
latch will tend to discharge the compensation capacitor, Cc which
may cause slow recovery from pulse limiting. Keeping the value
of Cc as small as possible within the requirements of voltage loop
stability will minimize this effect; however, slow turn-on from
current limit is often desirable and can be optimized by using the
LO-OUT signal to discharge a soft-start network instead of coupling directly into the SG1524.
Where minimizing turn-off delay is Important, the command from
the SG1549 may be taken directly to the output stage of a
switching regulator. A practical means of accomplishing this is
shown in Figure 4 where the power switch consists of an SM625
15-amp hybrid circuit containing both the power switch and the
commutating diode. This switch is driven by using the SG1524 to
switch a constant current source formed by the 2N2222 transistor
connected with its base to the 5 volt VREF line through a 1k resistor.
By connecting the LO-OUTterminal ofthe SG1549 to the base of
the 2N2222, drive current to the output stage can be interrupted
without the delays inherent in the SG1524.
LOW LINE SENSING
In many types of feed-forward 'or push-pUll converters, current
protection may be provided by senSing through an emitter resistor
referenced to ground on the primary side of an outputtransformer.
The fast-reacting SG1549 can easily sense secondary overload
as reflected back to the primary and, additionally, provide protection from unbalanced transformer saturation. When using the LO
CM inputs as shown in Figure 5, the HI CM inputs should be
shorted together.
12 -102
AlPPLJJ:CATJJ:ON NOTES - S01549
Figure 4. A fullY'protected, high performance single-ended
switching regulator is easily implemented with two IC's and a
hybrid switch. Current control is direct to the power switch for
fastest response.
Figure 6. Fastest turn-off response is achieved by taking
the output of the SG1549 direct to the power switches
through turn-off transistors, 01 and 04
SG1524
A
our
on one period withoutfull recovery in timeforthe next. A maximum
duty-cycle clamp, formed by Rl, R2 and 01 in Figure 6, minimizes
this effect by holding the error amplifier out of saturation when the
feedback voltage begins to fall.
,---....,5.0.
OSC
BOUT
OUTPUT
TRANSFORMER
HI eM
RES
' - - - - - t HI
OUT
R1
+ t---T-"'W'r"i
LO eM
Cl
RSC
LOW
Figure 5. When sensing emitter current, a small input filter is often
useful in eliminating transients to the SG1549
While the LO CM inputs may be connected directly across a sense
resistor, Rsco a small low-pass filter, Rl-Cl, is often helpful in
removing high frequency transients. It must be remembered that
the 5000hm input impedance to the LO CM terminal will cause the
use of Rl to increase the effective threshold; however, this also
offers the possibility of an easily adjustable threshold by incorporating a potentiometer at the input to the SG1549.
Coupling the current shutdown command back to the control
circuit may be done in several ways as described above, but
again, the fastest approach is to go directly to the output switches.
Figure 6 shows such an approach by adding two external shutdown transistors, 01 and 04. In this circuit, these transistors
perform double-duty by the use of C2, R3 and R4 to generate a
positive pulse when the main power switches, 02 and 03, are
commanded off by the SG1524. Turn-off Signals from either the
PWM orthe SG1549are summed together through diodes 02 and
03 to 01 and 04.
One problem often experienced with using pulse-by-pulse current
limiting with a push-pull inverter is half-cycling caused by limiting
Figure 7. An SG1627 provides both power gain for the voltage
control Signal as well as a high-speed interface for the SG1549's
current protection.
Another convenient way to tie the output of the SG1549 into the
PWM control in higher power applications is by using the SG1627
Dual Interface Driver and connecting LO-OUT terminal directly to
the two non-inverting inputs of the SG1627 as shown in Figure 7.
The N.I. inputs of the SG1627 will force the outputs off regardless
of the commands on the inverting inputs, and do so within 100
nanoseconds.
And finally, keep in mind thatthe LO-OUTterminal of the SG1549
will easily drive most high-speed optical couplers shOUld some
type of isolation between current sense and shutdown control be
required.
12 -103
•
12 -104
APPLICATION NOTES - SG1540
SILICON
GENERAL
PS-16
LINEAR INTEGRATED CIRCUITS
MINIMIZING THE COST AND COMPLEXITY OF START-UP
CIRCUITS FOR SWITCHING POWER SUPPLIES
Reza Amirani
Applications Manager
Silicon General, Inc.
INTRODUCTION
Power supply designers are often faced with choosing an optimun
circuit topology based on a specific set of requirements. Though
the hypothetical optimum design may vary substantially from one
set of specifications to another, some of the most important
criteria in many power supply applications are cost, size, weight,
reliability and efficiency. Based on such parameters, designers
often will choose between operating the pulse-width modulation
(PMW) controllC referenced to either the primary-or secondaryside return. In either case, they must provide the dc power needed
to operate that IC. Although a number of ways to generate this
auxiliariy supply voltage exist, some of the most common methods used area60-HZtransformer, linear regulator, self-oscillating
dc chopper or an internal bootstrap.
Auxiliary 60-Hztransformers are used in off-line switchers to step
down the input ac line voltage, which is then rectified and filtered
to power the control IC. Although it is straightforward, this
approach requires the use of low-frequentcy magnetics that are
relatively heavy and occupy a considerable amount of pc-board
real estate.
.
The size of the auxiliary 60-Hz power transformer can be a big
factor in low-power switchers, which are typically very small. In
these instances, the transformer can easily approach 30% of the
total volume occupied by the supply. To accommodate the
transformer, the supply's overall size would have to be increased,
thus increasing its cost as well. Because of this, the PWM control
circuits are not usually powered from an auxiliary 60-Hz transformer unless they must be referenced to the secondary side
return.
Linear Regulators are typically used in dc/dc converters operating
on inputs of less than 60 volts. If the input voltage is less than 30
volts, the designer often chooses a three-terminal voltage regulator. If the input is greater than 30 volts, a discrete series-pass
regulator is usually used, with a zener diode providing the reference voltage.
Unfortunately, both ofthese approaches are inherently inefficient
because of the power being dissipated in the series-pass element. Moreover, as the input voltage increases, the power
dissipation also increases, with a corresponding decrease in
efficiency. And since the input power is derived from the primary
side of the switcher's power transformer, the PWM control circuit
must be referenced to the primary-side return. As a result, the
supply must include additional analog circuits on the secondary
side and provide primary-to-secondary isolation through an optocoupler or isolation transformer.
Self-oscillating dc choppers can be used in either off-line switches
or in dc/dc converters. In either case, the dc applied to the
switching circuit is also applied to a self-oscillating chopper built
around a saturable core. The chopper converts the dc into a highfrequency ac square wave that is stepped down, rectified and
filtered to provide the dc power required by the PWM control
circuits.
Since the frequency of operation is often above the 20-KHz range,
the selected magnetics are much smaller than a comparable 60Hz transformer. The chief disadvantage of this approach is the
need for two high-voltage switching transistors, the cost of which
more than offsets any savings achieved by use of smaller magnetics. Because of this, choppers are usually used only in dc/dc
converters intended for use in telecommunications, aerospace
and other high-reliability applications.
Bootstrapping employs an auxiliary startup power supply and a
special winding on the main power transformer. Once the
supply's operation has stablized, this winding provides all the
power required to operate the PWM control circuits. However,
when ac power is first applied to the supply, the bootstrap winding
provides no output. Instead, the PWM control circuits are powered entirely by the auxiliary startup supply. But as the switching
transistors begin to function, voltage appears across the bootstrap winding. Eventually this winding, with its associated recti-
January 1990
12 -105
APPLICATION NOTES - S61540
fier/filter circuit, takes over the task of powering the PWM control
circuits, and the startup circuit shuts down.
Because the startup circuit must provide power for only the period
required for the switch-mode regulator to stabilize-the supply's
turn-on delay-very little power is dissipated in the start-up circuitry. But this approach requires a relatively large number of
discrete components, especially when the design calls for the
PWM control circuitto be referenced to the secondary-side return.
With the availability of monolithic boostrapping startup circuits,
however, these components can be replaced with a single integrated circuit. Figures 1 and 2 show block diagrams of the
bootstrap method for primary and secondary side operation.
secondary is rectified, filtered and applied to the dc input of the
PWM controllC at pin 14. With the application of dc power at pin
14, the PWM control IC turns on the switching transistors and
power is soon applied to the primary of transformer T1 , the main
power transformer. As a result, voltage is induced in the bootstrap
winding, AB: This voltage is rectified, filtered and applied to pin 14
of the PWM control IC. Because its voltage is higher than that
provided by the SG1540 through transformer T2, it provides all the
power used by the PWM controllC.
PWM
CONTROLLER
SG1526
U2
AC
IN
}--j--'---'-rl15
Figure 3. Schematic Diagram of the Bootstrap Start-up-power Circuits
Figure 1. Primary Side Start-up Circuit
During the period oftime that has elapsed for this to occur, energy
has been drawn out of capaCitor C3 to power the control circuits
through the SG1540. As a result, the voltage across C3 has
decreased. As energy continues to be withdrawn, the voltage
eventually falls below the SG1540's turn-off threshold and its selfcontained chopper turns off. When this happens, transformer T2
no longer provides power to the rectifier connected to its secondary winding. This has no effect on T2 or the SG1540, because
the diodes in the rectifier isolate them 'from voltage being produced by the bootstrap winding.
DC VOLTAGE
II
DRIVE
X1ig
Figure 2. Secondary Side Start-up Circuit
A MONOLITHIC BOOTSTRAPPING STARTUP
A simplified schematic diagram showing how the monolithic
startup circuit, an SG1540 is connected into a typical power
supply, can be found in Figure 3. As can be seen, the PWM control
IC, an SG1526 in this case, receives power from two sources
logically "ORed" at pin 14.
When ac power is first applied, capacitor C3 is charged through
resistor R2. When its voltage reaches the turn-on threshold, .a
self-contained chopper in the SG1540 is turned on with the
resulting high-frequency ac being applied to the primary winding
of transformer T2. The resulting voltage appearing across the
Of course, once the SG1540 turns off, energy is no longer
withdrawn from C3 and, as a result, its voltage increases and the
SG1540 is again turned on. However, because the bootstrap
voltage is higher, the SG1540 does not supply any power to the
PWM control circuits. Instead, it simply alternates between being
on in an idling mode arid being tuned off as the voltage across C3
rises and falls, The primary side operation is the same exceptthe
AB winding is wound on the primary side. (See Figure 5 in the
comparator section.)
EXPLANATION OF THE INTEGRATED CIRCUIT
The SG1540 consists of three main sections, as shown in Figure
4; a micropower bandgap comparator/power switch, a highfrequency square wave oscillator with a 200-milliamp totem-pole
output stage, and a second bandgap comparator with latching
crowbar'to protect against overvoltage faults while starting or
running.
12 -106
APPLICATION NOTES - SG1540
+VIN
0--------------,----,--,
START
HYSTERESIS
OVERVOLTACE
DC OUT
l)----I"-
Figure 4. 1540 Block Diagram
The Comparator Circuit
The operation ofthe circuit is best explained by referring to Figure
5. A micro power comparator (Ul) is referenced to an internal lowdrift bandgap source that provides +2.5 volts to one input of both
the startup and overvoltage comparators. The overall tolerance
of this reference voltage, over the full operating temperature
range, is ±130 millivolts. However, this reference is not available
for any external connections. Also included is a hysteresis
transistor (Ql) faCilitating external programming of turn-on and
turn-off voltage thresholds.
activates the osillator circuitry and through Q3, Q4 transistors
turns the Darlington pair (Q5-Q6) on. When the Darlington pair is
turned on, they provide a path through which the energy stored in
the startup capaCitor CSTAAT can flow to the PWM control circuit.
During the discharge time, the voltage induced in the flyback
winding will be rectified and filtered by Dl and CST to provide the
DC voltage. Note that the startup capacitor must be large enough
to store sufficient energy to generate a bootstrap voltage that can
meet all power requirements of the control circuits in the supply.
The Q5-Q6 Darlington pair is protected against any load transients or short-circuit conditions by internal current limiting. The
maximum allowable output current is determined by the ratio of
base-emillervoltage oftransistor Q7 to the voltage across resistor
R4. A typical value for the short-circuit current is 100 milliamps at
25°C, but as the temperature increases the current-limit threshold
decreases. Figure 6 shows the Darlington saturation voltage vs
load current.
w
<.:l
;::
2.5
1
CJ)
r-
::J
0.
::J
2.0
o
w
I
ILL
RSTART
1.5
o
W
<.:l
;::
/
~
~
..i,..-
"/" , ~ ..-
10
-;;,..s...
°
~
~
TJ
125°C
~ I-"
---.....
-..~
~
'"
1.0
...J
~
z
2
/
TJ ~
0.5
<{
'"~
<7i
0
o
10
20
30
40
50
LOAD CURRENT
Figure 5. Simplified Schematic Diagram of the Comparator Circuit
Figure 6. Output Transistor Voltage v.s. Load Current
When voltage is first applied to the IC, pin 2 is set lower than 2.5
volts by the voltage divider composed of Rl and R2. This causes
the output of the comparator to be switched low. When this
happens, transistors Q3, Q4, Q5 and Q6 are biased off, isolating
startup capacitor CSTAAT from its load. At the same time, transistor
Ql is turned on, plaCing R3 in parallel with R2 and forcing the
voltage at pin to drop even lower. During this time, the quiescent
current drawn by the IC is less than 1 milliamp, which allows the
startup capaCitor voltage to ramp up towards the high-voltage dc
supply through startup resistor RSTAAT '
Once the startup threshold is reached, the base of Ql transistor
switches low and causes Ql to be turned off. This raises the
voltage at pin 2 to a higher value, determined by the R1-R2 voltage
divider. At the same time, the other output of the comparator
Oscillator and AC Output
A simplified schematic block diagram of the oscillator is shown in
Figure 7. The oscillator's frequency is determined by the values
of an external resistor, Rp and capacitor, CT (R7 and C4 in Figure
3). Their values can be obtained from the chart in Figure 8. When
voltage is first applied to the IC, capacitor CT is completely
discharged and switch SI remains open. Even though the input
voltage rises, switch SI remains open until the startup threshold
is reached. When it is reached, the startup comparator (see
Figure 5) changes its output state, causing switch SI to close. As
soon as it closes, capacitor CTrapidly charges through resistor Rl
towards input voltage V ,N • Once the voltage across CTreaches 0.7
volts, the output of comparator Ul changes state.
12 -107
•
APPLICATION NOTES - SG1540
Despitethechange of Ul 's output state, switch Sl remains closed
due·to the action of a latch circuit, and the voltage across CT
continues to rise towards VIN' When it reaches approximately 2.1
volts, the outputof comparator U2 goes high. This resets the latch
circuit and opens switch Sl. When switch Sl opens, capacitor CT
is isolated from VIN and begins to discharge through resistor Rr
As the discharge continues, the voltage across CT decreases and
when it finally falls to 0.7 volts, the output of comparator U2 goes
low, closing switch Sl and beginning the cycle again.
t'
V,N
FROM START UP
2K
51
comparator, composed of 02 and 03 referenced to 2.5 volts, a
latching crowbar circuit, composed of 06 and 07, and a zener
diode, Zl. When the voltage at pin 7 exceeds the threshold set by
the Rl-R2 voltage divider, pin 2 rises above 2.5 volts, causing
transistor 05 to turn on. This, in turn, turns off output transistors
09 and 010 and activates an SCR crowbar. When pin 2 is not
used to program the overvoltage condition, the SCR can still be
activated by allowing the voltage at pin 7 to exceed the zener
diode's nominal 42-volt avalanche voltage. Note that when the
overvoltage circuit Is not being used, pin 2 should be tied to
ground.
CIRCUITRY
R,
------t---------,
R,
R,
2.1V
Figure 9. Simplified Schematic Diagram of the Overvoltage
Protection Circuit in the SG1540
Figure 7. Block Diagram of the Internal Oscillator used to Drive
the SG1540's Chopper Circuit
DESIGN EXAMPLE
The power supply design discussed in this section uses a fairly
common, straight forward circuit. It is intended to show the
application ofthe SG1540 I.C. in one ofthe modes of its application, namely secondary side PWM operation. This mode of
operation was chosen over the primary side, simply to show the
dramatic reduction in the size and weight of the auxiliary supply
compared to applications where 60Hz transformers are being
used.
R,
10
100
lK
10K
lOOK
Circuit Description
OSCillATOR F"REOUENCY-(Hz)
Figure 8. 1540 Oscillator Frequency Chart
A square-wave ac output is generated by driving a flip-flop from
the output of the latch circuit. The flip-flop's output is applied to a
totem-pole output stage. The output transistors have maximum
peak-current capabilities of 200 milliamps, which is enough to
power the control circuits of most switching power supplies during
the startup period. Note that if the oscillator circuit is not being
used, pin 4 should be connected to pin 7.
Overvoltage Circuit
The overvoltage circuitry is intended to protect the IC against any
overvoltage faults during startup and any period it is active. The
circuit is shown schematically in Figure 9 and consists of a
A general description ofthe SG1540 in a typical power supply was
given in section "A MONOLITHIC BOOTSTRAPPING
STARTUP". We will now design a complete power supply using
the same circuit topology of Figure 3 with an SG1540 as the start
up controller. As can be seen from Figure 10, the input rectifier
bridge is arranged for connection either to 117 Vac or220 Vac line.
The circuit uses a pair of 400 volts' MOSFET's in a Half Bridge
circuitry and a pair of high speed rectifiers for the output stage.
The MOSFET's are driven directly from the totem-pole output
stages of an SG1526 control chip through an isolation transformer. This provides the fast current turn-on and turn-off pulses
needed for MOSFET gates.
Current limiting is done with currenttransformer (T4) in series with
the primary of the power transformer: The signal is rectified and
12 -108
F3
R..
241l1/2 W
j
'C,
"18K
,W
CRI
IN40Q4
'CR2
IN4004
,.,
C"
l000pF
--,
R"
200K
PULSE [NQNttRING
PE51505
2SO¢l
en
sv
+C18
"""
1/2 W
T3
20A
o.l~F
25V
R,
47K lW
CRB
BYV26C
C,
"'"
OJV
120VAC
60HZ
220
Ul
R,
39K
'"
~
SG1540
II(C'
1~~~:8
I I
4~
~c
a
co
N.C.
~:4KOT4;OPF
~'II"
,J
C"
.047
PULSE
ENGINEERING
PE63454
~iga
I
C20
Jz
O"I::
Cs
R"
R"
'OK
R"
S.IKO
.1
'"
R"
,
R"
2
'26
'"
51KCI
R"
"C
CR>
IN4004
CR<
IN4004
,.,
Coo
R"
200K
1/2 W
FIGURE 10 - A TYPICAL POWER SUPPLY APPLICATION UTILIZING
THE SG1540 AS THE START-UP CONTROLLER
C"
2 4t-j----\-t-/"ki,,,
25 ~-r~--+--Ir--~-u~~.r~--~
10
~-r~/-t-~--+--+--r--j---r--t-~
5lL:
V
o
vp
= Transformer primary voltage
BM = Maximum flux density of core material
Ac = Cross sectional area of the core
Fs = Frequency of transformer input voltage
200
400
TIME -
600
800
1000
(ms)
Figure 11. Power Supply Start-up Time v.s. Start-up Voltage
For our design we choose a Ferroxcube Pot Core, 905PLOO-3B9
withAc=0.101 cm 2 . Looking at3B9 material we choose BM =0.1T,
and we calculate Np as follows:
N =
15
= 19 Turns
p (4) (0.1) (0.101 x 10.4) (200 x 103)
Choose Np = 25T
Note: R7 and C4 are chosen such that oscillator frequency is at
400KHz, therefore providing an output frequency of
200KHz.
Since transformer has a 1:1 turns ratio, both the primary and
secondary turns are chosen to be equal. Np = Ns = 25 turns of #32
AWGwire.
CONCLUSION
Considerable savings in size, weight, and! or cost can be
achieved by using a bootstrap startup circuit in switch-mode
power supplies. Empirical evidence has shown that bootstrapping a PWM control IC on the primary side results in a startup
current of about 1 milliamp, which means just about any standard
PWM controllC can be used as a primary-side controller. Bootstrapping a secondary-side controller results in a significant
reduction in the size and weight of the auxiliary power transformer
by substituting high-frequency magnetics for the 60-Hz magnetics that would otherwise be required. Moreover, the use of a
monolithic startup circuit, such as the SG1540, in a bootstrap
circuit minimizes both real estate and component requirements.
PERFORMANCE
A summary of the test results of some of the parameters is tabulated here:
Parameter
Line and load regulation
Ripple & noise
Current limit knee
Short circuit current
Parameter
Efficiency at full load
Output load transient
Start uptime
Condition
100
//
VI
~
iii
c 1.01--1--
~
0.5
~V
V
f--t---j--+
°0~~2~'--'~0--=~~~~~~15~0-~'75
CASE TEt.4PERAlURE - 'C
Figure 5. Maximum Power Dissapation vs Case Temperature
~CC_l0V
10K
OPERATION WITH A HEATSINK
I I
20K
SDK
tOOK
200K
soaK
1M
2M
FREQUENCY - HZ
Figure 3. Supply Current vs Switching Frequency
Figures 3 and 4 which are re-printed from the data sheet, can be
used to estimate the AC current consumption. The data, taken
on actual devices, shows that the current consumption can
exceed the worst-case DC value at high frequencies, or with a
sufficiently large capacitive load. In the case of a switching
power supply, the worst-case dissipation will occur at high line
voltage and light load: the driver pulse-width will narrow to a small
value, and the power dissipation of the driver will approach the
sum of the worst-case DC value plus the AC contribution.
The designer will have to determine the exact power dissipation
given the chosen switching/frequency and equivalent input capacitance ofthe power devices; he may conclude that the supply
voltage to the driver will have tei be reduced even further.
Since most power MOSFETs require gate enhancement voltages of 10 to 15 volts, the idea of heatsinking the SOIC may
begin to appear attractive since it offers the beleaguered designer another degree offreedom. From Figure 5, if the case of
the SOIC package (the bottom, which is closest to the internal
copper die-flag of the lead frame) can be held below +80°C, the
driver can dissipate 750mW rather than the previous 500mW.
The additional 50% gain in power dissipation capability may be
adequate to meet the original design goals.
The thermal resistance is best minimized by designing a wide pc
board trace under the SOIC package, and by eliminating the air
gap with thermal grease or a high thermal-conductivity rubber
gasket with double-sided adhesive. More elegant schemes,
such as using a metal-core board of alumina substrate, will allow
even higher dissipation. Finally, airflow across the package in
the range of 200-800 LFPM will reduce the thermal resistance by
15 to 30%, if the goal of miniaturizaiion is not compromised by
the addition of a fan.
12-114
APPLICATION NOTES - SG1627/SG1629
SILICON
GENERAL
PD-2
LINEAR INTEGRATED CIRCUITS
POWER SWITCH DRIVERS: NEW IC INTERFACE BUILDING
BLOCKS FOR SWITCHED-MODE CONVERTERS
Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
ABSTRACT
This paper describes the characteristics and performance of two new integrated
circuit products designed to interface between the control circuitry for switch mode
converters and their high power output stages. The first device develops the high
level turn-on and turn-off commands directly from the outputs of a low power P.W .M.
control circuit while the second is designed as a floating switch to control a high
current switching transistor directly from the secondary of a drive transformer.
INTRODUCTION
Recent years have seen significant developments by component
suppliers which have resulted in the ready availability of many
high performance power transistors and sophisticated control
integrated circuits for switching power supply design. There
existed a gap, however, between the control circuit and the power
switching transistors where a considerable amount of circuitry
was required to adequately condition and amplify the control
signal in such a way as to provide the proper turn-on and turn-off
commands to the power switch. This gap has now been filled with
two new integrated power switch drivers, the SG1627 Dual Output
Driver and the SG1629 High Current Floating Switch Driver.
SG1627
VCC
N.!.
INV.
SOURCE
CURRENT
LIMIT
SINK
SOURCE
N.!.
CURRENT
INV.
LIMIT
GND
SINK
SG1627 DUAL OUTPUT DRIVER
The SG1627 was designed to directly interface between low level
control circuitry and the high current handling devices required in
switching power supplies. As shown in Figure { this is a dual
circuit containing both channels that are required for a push-pull
system. It accepts the P.W.M. signals from a control circuit such
as the SG1524 and provides the conditioning necessary to
develop both turn-on and turn-off commands at currents up to
500mA. Its outputs can be used to directly control an external
power transistor or to interface with driver transformers for additional power amplification. Another feature of this circuit is the
optional ability to provide a constant drive current.
Figure 1. The SG1627 Dual Output Driver is Packaged in a 16-Pin
Cerdip D.I.L. Package.
CIRCUIT DESCRIPTION
Figure 2 shows the schematic for one-half of an SG1627 dual
output driver. It must be remembered that there are two identical
circuits in each 16-pin dual-in-line package. The inputs to this
circuit are switch closures to ground with both inverting and noninverting logic configurations available. The input threshold level
January 1990
12 -115
•
APPLICATION NOTES - SG1627/SG1629
of both logic inputs is 2V, and the logic is powered by an internal
voltage regulator so that input characteristics are unaffected by
power supply voltage which can range from 5 to 30 volts.
3.0
w
2.5
«
r-
Source
-'
Collector
o-----if-".....-4
t-'i++----==-----o ~~~~~niBoost
Sink
D1
D2
6V
6V
0
2.0
0
1.5
>
z
l~nV;~~ O---f---+-f-....
Nonl~~nuyt
>
<..:>
+Vcc
F=
«
r-
«
(f)
Sink
I
°
TJ ~ 25 e
Vee ~ 5V
TJ ~ -55°C'
Vee ~ 5V
o
Figure 2. Schematic Diagram for One-Half of the SG1627
>
COLLECTOR TO EMITTER VOLTAGE -
,
<..:>
«
r-
-'
0
>
z
0
F=
«
4~2~
IJ
55°c
TJ
Vee ~ 20V
o
100
200
300
400
500
COLLECTOR CURRENT - mA
Figure 4. Saturation Characteristics of the SG1627 Sink Transistor
THE TOTEM-POLE OUTPUT CONFIGURATION
One of the simplest uses of the SG1627 is illustrated in Figure
5 where the output is configured to provide a constant 300mA
turn-on command to an external switching transistor together
with a high peak turn-off current. Note that the logic on the
SG1627 is being driven directly from the 5V reference terminal
of an SG1524 P.W.M. control I.e. The logic inputs are directly
connected to the open collector output transistors of the
SG1524 with no additional interfacing components. The output
current of the SG1627 comes from the input voltage, which in
this case is approximately 10V, but the use of R2 provides a
constant source drive regardless of input voltage variations.
VIN = +lDV
Vee TO EMITTER VOLTAGE - - -
3.0
Vee ~ 5V
w
I
1.0
0.5
3.5
\1
\,
Emitter
The output sections of the SG1627 contain both source and sink
transistors, each capable of 500mA, 30V operation. In addition,
the source transistor has the capability of constant current operation by using an external sense resistor between the source
emitter and the current sense terminals . .The source transistor is
in a Darlington configuration which can easily deliver currents to
500mA under all operating conditions but at the cost, however, of
a higher saturation voltage. The sink transistor is designed for
very low saturation voltage: approximately 0.5 volts at 500mA. It
does, however, need greater base drive to meet those high
currents. This can be provided by either raising the supply voltage
above 5V, or by adding a boost drive current through 06. The
saturation characteristics of both source and sink are shown in
Figures 3 and 4.
TJ ~ 125°C
Vee ~ 5V
frO
:::J
Collector
I
3.5
1/2 SG1627
2.5
2.0
Power
"'-+-+~~M--+.--t: Switching
Transistor
1.5
frO
:::J
r-
«
1.0
(f)
0.5
Figure 5. In a 300mA Output "Totem Pole" Configuration, The SG1627 Interfaces Directly With the SG1524
Regulating P.w.M. Control Circuit.
OL.-_--I.._ _.L.-_--I.._ _L--_-l
o
100
200
300
400
500
COLLECTOR CURRENT - mA
Figure 3. Saturation Characteristics of the SG1627
Source Transistor
e,.
Resistor R31s used to build up a voltage drop across capacitor
At turn-off, the energy stored in
provides both a negative
voltage to the base ofthe power switching transistor and the boost
e,
12 -116
APPLICATION NOTES - SG1627/SG1629
VIN = +2DV
drive current necessary to saturate the sink transistor during peak
discharge currents of approximately 500mA. With this magnitude
of reverse base current (lb2), transistor turn-off is greatly accelerated.
R,
,500
There are two considerations to remember in this configuration.
The first is that the maximum output voltage will be less than the
value of Vee because the source transistor operates as an emitter
follower. With Vee = 5 volts in this case, the peak output voltage
is approximately 3 volts. The other consideration is power
dissipation in the source transistor when using it in the constant
current mode since it will absorb any excess voltage after current
limiting.
The performance of this application is illustrated in Figure 6 which
shows the base current into the external switching transistor. One
can see both the constant drive current of about 300mA and the
rapid, peak negative turn-off current in excess of 500mA. Note
thatthe delays through the SG1627 are less than 50 nanoseconds
making a very fast responding circuit.
+4.DV
t5
~
+2.0V
§:
0.0
0::J
"~
+O.5A
I
0-
Q
'"'"
0.0
/
::J
U
I-
-O.SA
Power
Switching
Transistor
Figure 7. Higher Input Voltages Can be Used to Provide Drive
for Higher Sink-Transistor Currents
power boosting circuitry. Maximum flexibility for the use of
external current boosting transistors is maintained by the uncommitted availability of both the collector and emitter terminals of
both the source and sink transistors. Figure 8, for example, shows
the use of an external PNP transistor to boost the source current
to 1amp. The use of the PNP transistor in this configuration still
allows current sensing to be used for constant current operation.
If constant current operation is not required, an NPN emitter
follower booster could also be used. The use of a single boost
transistor as shown in Figure 8 makes a powerful drive circuit as
one can now drive one amp of turn-on current into a switching
power transistor and still have a 500mA ofturn-off current through
the sink transistor.
v
::J
go
::J
o
200ms/DiVISION
1/2 SG1627
,-----(>---*"---{
Figure 6. Output Current Transfer Function
2N6109
or equiv.
Vee
An alternate configuration shown in Figure 7 pictures the SG1627
with a higher value of supply voltage. This offers at least two
advantages: first of all, it allows the output voltage swing to rise
considerably higher remembering that the source as an emitter
follower can rise to approximately 2V below the input supply
voltage. The other benefit is in providing greater drive current for
the sink transistor allowing 500mA saturation without the need for
additional boost current. Because of the large power supply
voltage across the source transistor, power dissipation can be a
problem. This probably means a reduced source current if current
limiting is required, although the use of resistor R, to absorb some'
of the voltage drop will reduce the power dissipation within the
SG1627.
Recognizing the potential for package power limitations, it is
important to consider the use ofthe SG1627 with various types of
12 -117
N.I.
INV.
Power
Switching
Transistor
GROUND
II
Figure 8.1ncreased Source Current With the Use of an
External Boost Transistor
APPLICATION NOTES - SG1627/SG1629
DUAL PHASE OUTPUTS
The SG1627 dees net need te be cemmitted te tetem pele
eperatien. The seurce and sink transisters can be separated and
used independently fer dual eppesite-phase .outputs. Figure 9
shews the eperatien with beth seurce and sink transister emitters
greunded and each used as a cemmen emitter amplifier driving an
external lead resister. Figure 9 alse shews the use .of an external
resister R, te previde additienal drive current beest te the sink
transister. This will allew the sink transister te previde full 500mA
eperatien with .only a 5 velt supply. The respense characteristics
efthis type .of cenfiguratien are shewn in Figure 10, which pictures
the respense .of beth seurce and sink with 24ehm lead resisters te
inputs at beth the inverting and the nen-inverting legic inputs.
Nete again the minimum delay .of beth .outputs; less than 100
nanesecends from input te .output en beth source and sink.
R2 , but veltage switching ceuld as easily be accemplished by
merely sherting together the sense terminals. Te previde greater
efficiency in the magnetic design, a reset winding is added and
shewn being driven by the sink transister. This ensures the
magnetic flux is reset te zero between each pulse. Of ceurse, the
sink transister .opens up every time the seurce transistor drives
the primary winding.
1 /2
-F:;-:;:==t;L=!.__~
SG1627,---{~_ _
Drive Primary
Secondaries
nn
Other
Half
SG1627
Primary Reset
Vee
~
+5V
R,
R3
'DO
2000
1/2 SG1627
,--~>-+----'
Figure 11. Driving an Outside Transformer With the SG1627
Figure 9. Seperate Dual-Phase Outputs With Additional Drive
Current for 500mA Sink Transistor Operation
2V
~
-...,-
I'--r--
,..--
Ir--
i'--r-
r-r-
lV
An additienal illustration of the versatility .of the SG1621 is shewn
in Figure 12, where the nen-inverting logic input is used te provide
a pesitive guarantee that both sides of a push-pull inverter can be
on atthe same time. This circuit is shown using the inverting input
as the primary drive path, which will force the source transistor te
be on when the centrel circuit transister is conducting. The noninverting input is then diode-ceupled to the oppesite side of the
inverter and senses saturatien .of the external pewer switch. If the
collector of the opposite transistor is lew, holding the nen-inverting
input lew, then regardless of what happens at the inverting input
terminal, the output seurce on that side cannot be turned en. The
sink will remain on, holding the output lew until a rising cellector
voltage en the opposite side remeves the non-inverting input at
which time the cemmand signal will then ceme threugh the
II
1-1-
'--I-
r-r-
I--r-
II
200ns/DIVlSION
200ns/DIVISION
Figure 10. Source and Sink Response Characteristics
The use .of the seurce and sink as separate outputs prevides
significant benefitfer driving a transformer, as illustrated in Figure
11. In this example, the primary winding of the transfermer is
driven by the source transistor with its emitter grounded. Constant
current operation is shewn with the inclusien ofthe sense resistor,
12 -118
Figure 12. Simultaneus Conduction of the Two Output Transistors
is Prevented by Gating With the Non-Inverting Inputs
APPLICATION NOTES - SG1627/SG1629
8G1627 and turn on the correct side. This circuit is particularly
useful as a protection against cross-conduction of the output
transistors during transient conditions at power-on or overload.
The above examples have been chosen to illustrate the versatility and performance of this new device designed to interface
between a low level pulse width modulating control circuit and the
high power switching transistors used in all modern-day switching
power supply designs.
In Figure 14, the schematic of the 8G1629 shows two power
Darlington transistor structures, each capable of handling an
excess of 2amps of current: 03/04 as the source. and 06/07
forming the sink. Transistor 05 provides current sensing with
feedback to provide constant current operation. The source
transistor is turned on by conduction of drive current through
resistor R2 • The drive current for the source transistor is gated on
and off through the action of 01 which senses the input voltage
and provide a turn-off of the source transistor between each drive
current pulse.
THE SG1629 HIGH CURRENT FLOATING SWITCH DRIVER
03
A second interface circuit to be discussed in this paper is the
8G1629 illustrated in Figure 13. This device has been designed
to provide an interface between a drive transformer secondary
winding and a high power switching transistor, and again provide
the proper signal conditioning to adequately deliver both turn-on
and turn-off current into the base of that switching transistor. More
importantly, its design is such that it requires no external power
connection but develops all the power for both turn-on and turnoff from the drive transformer and an external storage capacitor.
With this capability, the 8G1629 can be used in floating operation
for bridge inverters at voltages in excess of 300V with respect to
ground. This circuit also contains the capability for constant
current drive operation with a similar type of current sensing circuit
and an external current sensing resistor.
+VIN
01
R2
1K
SOURCE
CLAMP
SINK
DRIVE
SINK
GATE
-VIN
o--+-~I-+--+-~--+--+---+-+--{) ~~~TER
SUBSTRATE & CASE
Figure 14. The Schematic of the SG1629.Transistors 04 and 07
are Designed for Two-Amp Operation.
Figure 13. The SG1629 High-Current, Floating Switch Driver
CIRCUIT OPERATION
The 8G1629 functions with a center-tapped drive transformer
secondary winding such that when a turn-on command is present
and current is flowing in the upper half of the secondary winding
through the source transistor and into the base of the power
switching transistor, a current is also flowing in the lower portion
of the transformer secondary through the high current rectifier to
charge the external capacitor Cs to a negative voltage. When the
drive command terminates, this negative voltage is used to turn on
the sink transistor which then pulls a negative Ib2 current from the
base of the switching power transistor down to the negative
voltage on the capacitor providing again a high peak turn-off
current to speed the response and minimize the power losses in
the switching transistor. For maximum versatility, this circuit also
contains several gating options.
The Darlington sink transistor has its input brought out as a
separate sink drive terminal which gives the user several driving
options. In addition, the sink driving current can be gated by the
use of 02, which has its own input terminal. The diodes D1 and
D2 are high current rectifiers which provide the charging current
for the external capacitor attached to the sink emitter terminal.
The action of transistor 01 to gate the source transistor insures
that there is negligible discharge current (less than 10mA) from
the external capacitor during the off periods of the circuit. This
allows the capacitor to be charged with very narrow drive pulses
separated by relatively long off periods.
The 8G1629 is packaged in both amulti-pin TO-66 power
package and an a-pin minidip. Having no sensitive, low current
circuitry, this device can be operated with a maximum junction
temperature of 175°C which, coupled with a low 6J C thermal
resistance of 5°CIW, gives the TO-66 package a 3 Watt capability in free air and 10 Watts or more with some heat sinking.
Because of the versatility of this device, it was felt that there may
be applications for lower power requirements and thus the
8G1629 will also be available in an a-pin ceramic minidip package
which, of course, has a power dissipation of only aOOmW. With
one pin less in the a-pin minidip package, the sink gate function
is sacrificed.
12 -119
III
APPLICATION NOTES - 8G1627/SG1629
SG1629 APPLICATIONS
The use of the SG1629 can best be demonstrated in an application as shown in Figure 15 where two SG1629's are used to
provide the drive signals for the power transistors in a 5 amp onehalf bridge switching supply. The drive transformer is shown with
10 volt drive signals on the primary winding which, with a 2:1
transformer turns ratio, provides a 5V peak signal on each half of
the secondary. When the drive command is present on one
secondary, it is translated into a constant current through the
source transistor by the use of the sense resistor, Res' which in
this case provides a constant 700mA into the base of the external
NPN transistor. At the same time, the 20 microfarad external
capacitor is being charged with a currentlhrough the rectifier in the
SG1629 and the lower half of the secondary winding. While this
is occurring, the opposite phase signal is being applied to the
lower SG1629 circuit which serves to further enhance the charge
on its external capacitor while maintaining the power switch in the
off state.
SG1629
~¢jj
+Vs
RCS
1.00
' - - 0 7A.
2.0A
lOT
lOT
~
'OT
+10V
I _~
'OT
TO
ORIVER
2213P 3CB
2N6583
~
~~'VER ~
CORE
N
tap and the power transistor emitter, is pictured in Figure 17. Also
shown in this photograph is the input voltage at the base of the
external NPN transistor. Note that at the very first portion of this
waveform, when ,the opposite side is on, there is an additional
negative charge supplied to the capacitor so that we have a
maximum reverse base-to-emittervoltage of close to -4V. During
the off time, the action of the sink transistor maintains a negative
voltage bias of approximately -3V on the base of the power
transistor. When the drive command is given to turn on, the base
voltage goes positive to the 0.7 or so volts necessary to turn it on
and at turn-off, goes negative again. The important action is
shown in Figure 18 which pictures the actual base current of the
power transistor with a scale of one amp per division. Both the
constant turn-on 1.1 of about 3/4 amp and the peak 1.2 of close to
-2amps can be seen along with the collector voltage waveform
with a 5amp resistive load. Remembering that the time base of all
these waveform photographs is 5 microseconds per division, one
can see approximately one microsecond delay between the turnoff signal at the base and the actual turn-off of the collector of the
output transistor. Although this turn-off response is primarily a
function of the transistor design, it is safe to say that any power
switching transistor should perform faster with this form of base
drive.
E::1
1
(
Same SG1629 cirCUit
as above
1~~
__~~__~~__+-++__+--+~
2N6583
20~~~r-~~--+--+-++--r--~1~
~--------------~
10
Figure 15. Use of the SG1629In a 5-Amp Half-Bridge Converter
t--t-tF--F-1-F-rl--H't--t-t41
I
TIME BASE:
When the drive command terminates, the voltage at both ends of
the secondary winding goes to zero. Since there is approximately
-4V at the emitter of the sink transistor while its base is being
driven through the external drive resistor, R., to zero volts, the sink
transistor then immediately turns on and pulls a high current 1.2
pulse out oflhe external transistor and through the capacitor. This
current, of course, only flows as long as it is available from the
stored charge within the base of the external transistor as the
source has been gated off. After that charge is depleted, the sink
transistor remains on insuring a negative reverse voltage at the
base of the switch transistor.
The performance of the SG1629 can be illustrated by the waveform photographs in Figures 16 through 18. In figure 16, the
command signal from one channel of the control circuitry and the
waveform of the drive transformer primary voltage are shown.
The voltage on the secondary winding, referenced to the center-
12 -120
5,L5EC/DIVISION
UPPER TRACE: P.W.M. CONTROL SIGNAL
LOWER TRACE: DRIVE TRANSFORMER PRIMARY
Figure 16. Input Control to the Drive Transformer
5r-"'T"--;r-"'T"--;---.:;::==--r---.-.,..--,
'-l
o~+-tI~+--+"""I-+""'-+--+-.-I
'J"
~
01----+--11--+-1---1---+--11+--+--+--1
TIME BASE:
5"sEC/DIVlSION
UPPER TRACE: DRIVE TRANSFORMER SECONDARY
LOWER TRACE: PO't\£R TRANSISTOR BASE VOL lAGE
Figure 17. The Base Voltage Delivered to the External Power
Switching Transistor by the SG1629
APPLICATION NOTES - 8G1627/8G1629
lA r--r--~~--.---r--r--'-~--'--'
r--H
o
-IA r--+--+--+--~~---r-;r--+--+--;
-IA ~-+--+--+--4---~-+--+--+--4---1
1t7-+-1r-t-+"j---t----.I--+-t--rl
10V
5V ~-+--+--+--4-~--~~~-+--+--;
5V
10V
OV
V
L-~
V
__
~~
__
~U
__
J-~
TIME BASE,
~~~~
__
I--I--I-+~/f-tt\V+-+--+--1----1
~-J
5!'SEC/DIVISION
A
V'
f--I
1--+---1--lV
+--l---+-+--+-++-+
V
TIME BASE,
5!'SEC/DiVISION
UPPER TRACE: TRANSISTOR 8ASE CURRENT
LOWER TRACE: COLLECTOR VOLTAGE WITH Rl =20
UPPER TRACE: TRANSISTOR BASE CURRENT
LOWER TRACE: COLLECTOR VOLTAGE WITH
=20
Rt.
Figure 1B. Base Current and Collector Voltage of the External
Switching Transistor
Figure 19. Operation With Narrow Pulse Widths
Note that one can also see in the collector waveform a soft knee
at turn-on where the power transistor is not saturated instantaneously. This is partially because ofthe turn-on characteristics ofthe
transistor and partially because of the finite rise time of the base
current through the driving circuitry. The rise time is primarily a
function of the leakage inductance of the drive transformer which
opposes a sudden change in currentfrom zero to maximum value.
It is an exercise in transformer design to configure the transformer
to minimize to the greatest extent possible the leakage inductance. This can be done with a minimum number of turns and a
maximum coupling between turns. In the illustration, a ferrite pot
core of approximately 3/4" in diameter was used to configure the
drive transformer. More will be said about turn-on rise time later,
butfirst let's discuss one additional characteristic of concern in the
turn-off circuitry: The operation with very narrow pulse command.
the current sense terminals shorted, there are two V6E voltage
drops between the clamp and the source emitter terminals.
Therefore, the clamp diode Dl will hold the collector on voltage to
approximately one diode drop above the base. This will keep the
switching transistor right atthe threshold of saturation, regardless
of load current variations.
ANTI-SA TURATION CLAMP
D1
Since the charge on the external capaCitor is developed during the
turn-on command, narrow pulse widths accomplish the transfer of
a minimum amount of energy. As the drive command pulse widths
get narrower, there is a point where the voltage on the external
capaCitor begins to fall off. With the circuit components as shown
earlier, this loss of 162 occurs at approximately 2 miscrosecond
pulse widths. Figure 19 shows the base current and collector
voltage waveforms at narrow pulse widths where the 162 has
diminished from 2amps down to approximately 3/4 of an amp.
Further reductions in pulse width bring the 162 current ultimately to
zero. This characteristic is, of course, a function of the time
constants in the total circuit and some compromise or optimization
can be achieved by appropriate selection of capacitor values and
secondary drive voltages.
IMPROVING TURN-ON RESPONSE
The above circuit incorporated constant current drive which is an
advantage ilthe load current happens to be relatively constant but
in many applications this is not the case. The SG1629 may also
be used to provide a base drive proportional to load demand by
adding an anti-saturation clamp diode as shown in Figure 20. With
In applications where maximizing base current rise time is important and secondary transformer inductance is a significant consideration, the use olthe gating functions in the SG1629 can provide
significant benefits. Figure 21 shows the addition of an external
transistor 01 to drive the sink transistor's gate circuit. To explain
Figure 20. Use of the SG1629 in a Load-Dependent
Drive Configuration
12 -121
II
APPLICATION NOTES - SG1627/SG1629
Another method of spreading up the rise time of current into the
base is the use of some reactive components to differentiate the
drive current signal. A simple approach is a capacitor by-pass
around the current sen'se resistor, Rsc ' providing an initial boost
in turn-on current.
GETTING IT ALL TOGETHER
Figure 21. Improving Base Current Turn-On Rise Time
the operation of this circuit, note that the sink transistor's base
drive is now being generated with He connected to the common or
center tap of the drive transformer secondary instead of the
negative inputlerminal. This is essentially zero volts and since the
emitter ofthe sink transistor is attached to the capacitor which has
a negative voltage on it, the sink transistor would normally PE:! on
continuously. Transistor 01 is selected as a relatively slow nongold-doped transistor which has a finite storage time. Its action is
to turn the sink transistor off during the drive command signals, but
to delay that offsignal for some increment in time. Note that before
the commencement of a drive command, the sink transistor is on
by the action of Re' Transistor 01 is also saturated by its base
resistor being connected to the end of the transformer which is
also at zero volts prior to the command signal.
When the drive command is initiated, current begins to build up in
the secondary circuit and the first flow of current is through the
source transistor, through the current limiting resistor, down
through the sink transistor which is still conducting, and back to
the negative terminal on the transformer secondary. The switching transistor is still back-biased while this occurs. Because the
input to transistor 01 is now at a negative voltage, it turns off, but
since it has a finite storage time, that time is used to delay the rise
of the input to the sink gate. Additional delay can be added with
a small capacitor at the sink gate input terminal. When the input
to the sink gate goes high, its output goes low, forcing the sink .
transistor to turn off. Since the source current is already flowing,
turn-off of the sink diverts that current to the base of the output
transistor producing base currents in 01 with rise times of less
than 100 nanoseconds.
The overall simplifications which Silicon General has offered to
the design of switch mode power converters can best be illustrated by Figure 22 which shows the total command signal flow
from the feedback error information to the output of a high current
half-bridge regulating inverter. The SG1524 was designed to
provide all of a switching regulator's P.W.M. control signals with
the only external components required being the divider resistors
to interface with the error amplifier, the overall loop compensation
network, and the resistor and capacitor to set the operating
frequency. The SG1524drivesthe SG1627 directly which, inturn,
provides the signal conditioning to develop the drive and reset
commands to an interstage drive transformer. The secondary
windings of that drive transformer are directly coupled into a pair
of SG1629 floating drivers which are then used to command the
external 5amp switching transistors which form the high power
output stage of the power supply.
Figure 22. Three IC Types Form a Major Portion of the Control
Electronics for a Switch-Mode Half-Bridge Converter.
These circuits have all been designed to offer a maximum degree
of flexibility while incorporating what would otherwise be a substantial amount of discrete circuitry.
Thus, all these new IC's greatly ease the design and manufacturing problems typically inherent in switching 'power supplies and,
at the same time, provide greater repeatability and reliability at
significantly reduced costs.
When the action is reversed at turn-off, there is negligible increase
in delay time between the turn-off signal and the actual turn on of
the sink transistor. Thjs is because 01 is the only device with a
long storage time and it is turning on so storage is not a factor...
12-122
APPLICATION NOTES - SG3635
SILICON
GENERAL
MC-l
LINEAR INTEGRATED CIRCUITS
USE MOTOR-DRIVE Ie TO SOLVE TRICKY
DESIGN PROBLEMS
An IC Driver's Logic-Control Features and High Output Capability Suggest
Elegant Ways to Handle a Variety of Dificult-to-Drive Loads
Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
INTRODUCTION
You can use the SG3635 driver IC in a wide range of applications,
ranging from a switched-mode motor-speed controlier to a datacommunications line driver. The device's input configuration
simplifies interfacing between low-level circuitry (eg, allP or logic
blocks) and the high-power load. And its output stage (see
"Anatomy of a driver IC), capable of driving 40V, 2A loads with
peaks as high as 5A (including reactive loads), provides sinking
and sourcing capability as well as commutation diodes.
filtered by the RC network, drives the 311 comparator, which
compares the output with the speed-setting input and biases the
SG3635 to complete the loop.
When the motor slows down, the SG3635's output, switches on
(Fig 2, trace A), forcing current into the motor (trace B) until the
comparator's inputs balance. Under these conditions, the circuit
oscillates in a controlled manner around setpoint. The 1O-kg, 0.1IlF pair provides positive ac feedback to ensure clean transitions.
CONTROL MOTOR SPEED WITH MINIMUM PARTS COUNT
Fig 1 shows one application of the device in a self-clocking
switched-mode speed-control loop. The mechanically coupled
tachometer detects the motor's speed; its output, scaled and
A
~
~
I
NOTES·
MOTOR- TACHOMETER
GLOBE MODEL 397A120-2
12V MOTOR; 3V/l000-RPM TACH
I'-~
I\-
'-"
oR
I
I
.. =1% FILM RESISTOR
B
Ir
r
If'
TRACE
A
Figure 1. Used in a Closed-Loop Configuration, the SG3635 SelfClocking Driver IC Controls Motor Speed in Proportion to 0 to 10
V Input. The Comparator Weighs the Tachometer's Output
Against the Input Setting, Then Commands the SG3635 to Either
Speed up or Slow Down the Motor
B
If'
HORIZONTAL
5mSEC/OIV
5mSEC/OIV
Figure 2. Switching on in Discrete Increments (trace A), Fig 1's
Driver IC Forces Current (traces B) into the Motor to Speed it up.
Upon Reaching Equilibrium, the Circuit Oscillates Around the
Setpoint
January 1990
12 - 123
•
APPLICATION NOTES - SG3635
The 3.3-kQ resistor from the comparator's offset pin to the 15V
supply provides enough offset to prevent motor turn-on with a OV
speed setting. In this application the driver only sources current:
The sink transistor is never enabled. You could turn the sink
device on to dynamically brake the motor, but the motor's back
EMF would cause considerable power dissipation. The back
EMF appears after the initial inductive spike (clamped by the
internal commutation diode), which appears when the IC's output
switches LOW.
"-......
A
IV
C
What about motor-reversing capability? Fig 3's single-supply
circuit uses two SG3635s in a bridge configuration. The flip flop
generates the necessary complementary instructions to the ICs'
Enable inputs. In this example, the SG3635s' Pulse inputs are
grounded; you could instead pulse-width modulate them to control motor speed.
I
TRACE
A
Figure 4. Large Peak·Reversal Current in Fig 3's Motor is Evident
In Trace A. Traces Band C Showthe Drivers' Output Reversal; the
Outputs Handle the 3A Motor Peaks Cleanly
20V
,
cw
\
NOTES:
MOTOR=CUFTON
PRECISION PRODUCTS
MODEL 13
PWM INPUTS (GROUND
FOR FULL POWER)
HORIZONTAL
50 mSEC/DIV
50 mSEC/DIV
50 mSEC/DIV
B
C
15V
ccw
I---
I
I
B
IC's HIGH-CURRENT OUTPUT YIELDS FAST
MOTOR REVERSAL
20V
I
V
'"
,
-,
.
~gTh~"'MOTORDYNE MODEL'~:~~ ---r --------
...
SERVO POT=SPECTROL MODEL 500-173 f
GEAR REDUCTlON=100: 1
I
I
I
I
I
I
~lr6T,0V
I
_____________ JI
\
, - - - - - - _ TO LEADSCREW-SCANNER DRIVE
Figure 3. This Push/Pull Bridge Configuration Allows Two Driver
IC's to Provide Bidirectional Motor Drive. A Command to the Flip
Flop's Clock Input Causes Instantaneous Reversal. Ground the
SG3635's Pulse Inputs for Full Speed; Apply a Pulse-WidthModulated Input to Control the Speed
Figure 5. Control a Shaft's Angular with This Servo-Loop Circuit. .
Select the Position by Applying Limits to the Comparator Inputs.
The Circu~ Uses Supplies Shifted 15V Negative to Provide a
Ground-Level Bipolar Output to the Motor
Fig 3's circuit is a good test of the IC's peak current capabilities,
because motors present a very difficult load during instantaneous
reversal. Fig 4, trace A shows the current; traces Band C
represent the SG3635's voltage outputs. The motor draws
200mA during a reversal because of the armature's stored energy.
Servoed motor makes position clear
bias the RS flip flop that controls the SG3635. To provide logic
level compatibility with the driver, the flip flop uses OVand -15V
supplies instead of the usual +15V and OV configuration. This
circuit forces the scanner to run continuously between the limits
defined by the VLIMIT inputs. You could control speed by summing
pulse-width modulated signals at the comparator inputs or by
gating the SG3635's inputs.
In addition to controlling speed and direction, you can use the
SG3635 in a simple circuit to control a shaft's position (Fig 5). In
this configuration, the motor drives a mechanical scanner in either
direction between a set of programmed limits. The driver IC's
ground pin is biased at -15V, allowing the device's output to swing
symmetrically about OV.
DRIVE LONG CABLES WITH TOTAL DATA RECOVERY
The 5-kQ pickoff potentiometer detects the scanner's position,
then trips a pair of limit comparators; these comparators in turn
You can also use the driver IC in applications other then motor
control. Consider, for example, the problem of driving long cables
at high data rates - a difficult task because of the rapid buildup of
parasitiC capacitance with increasing cable length. In a remote
data-monitoring application, for instance, a 10,OOO-ft cable displays O.1-f..IF capacitance - a brutal load at high speed, making
receiver-end data recovery difficult.
12 -124
APPLiCATION NOTES - SG3635
Fig 6's circuit provides the drive for this difficult load: the V/F
converter presents a serial, 1OO-kHz square-wave data format to
the SG3635 .. The driver's output (Fig 7, trace A) - somewhat
distorted because of the load - drives the line. Trace B shows the
IC's output current: The 5A peaks at the waveforms's edges
clearly reflect the heavy capacitance.
The square wave's distortion is relatively minor, allowing easy
data recovery. The 311 comparator uses a simple RC network to
set an adaptive amplitude threshold against which to compare the
line output. Because the threshold is derived from the signal,
power-supply shifts produce no undesirable effects.
VALVE-CONTROL CIRCUIT MAINTAINS CONSTANT pH
In another nonmotor-related application, you can use the SG3635
in conjunction with a pH probe as a 3-mode controller (Fig 8). The
FET op amp unloads the probe and routes the signal - via an RC
filter - to the two comparators. The comparators, configured as a
double-ended limit detector, bias the SG3635; the IC then drives
valves that fed either acidic or basic solutions to the chemical
vessel.
"V
'OK
NOlES:
pH PROBE=INGOLD "'ODEl 460-35
.""'~ FILlA RESISTOR
"VAL\lES=HUM'PHREY MODEL T062EI
Figure 6. Regulate a Chemical Solution's Acidity with this 3-mode
Controller Circuit. The SG3635 Drives the Valves that add Either
Acidic or Basic Solution to the Bath. Set the Desired pH with
Potentiometer-Determined Comparator Limits.
.
Figure 6. Driving a Brutal Capacitive Load Presents Little Problem to
the SG3635 Driver. In This Circuit, the IC Drives a 10,000 ft DataCommunications Cable Having O.lIlF Capacitance. The Driver
Transmits Serial lOa-kHz Data to the Recieving Comparator.
A
B
r-~
c
~
D
l
it
'~\
~
E
~
F
f
If pH is correct, both comparator's outputs remain HIGH and
neither valve energizes: The appropriate LOW-switching comparator redresses eventual pH imbalance by turning the necessary valve on.
"
~
r--...
lA
~V
J
,
TRACE VERTICAL
A
5V/DIV
8
200V/DIV
C
3A!DIV
D
5V/DIV
200V/DIV
E
F
3A/DIV
HORIZONTAL
500 nSEC/DIV
500 nSEC/DIV
500 nSEC/DIV
500 nSEC/DIV
500 nSEC/DIV
500 nSEC/DIV
Figure 7. The Effects of Fig 6's Gluttonous Capacitive Load are
Evident in Traces A and B. The 10,000 ft. Line Absorbs SA
Current Peaks During the IC's Switching Transitions. The
Recieving-End Comparator Uses an Adaptive Amplitude
Threshold to Produce a Clean Output.
In a final example of the driver IC's versatility, consider its use as
a high power-transistor driver. Driving these devices at high
speed requires active turn-off techniques to sweep charges from
the base-emitter junction. Moreover, many high-voltage power
transistors need negative base bias to guarantee breakdown
ratings.
Assume, for example, the use of unipolar base drive (Fig 9a) for
a high-power 2N6308. Fig 10, trace A shows the transistor's base
waveform; traces Band C display collector voltage and current,
respectively. Because the base drive is unipolar, the collector
turns off slowly: Voltage and current require about 1.5J.1seC to
settle. What's more, the transistor dissipates considerable power
during turnoff, increasing its vulnerability to secondary breakdown. Inductive loads (eg, flybacktransformers) can exacerbate
the situation.
The solution? Fig 9b's circuit uses an SG3635 to provide bipolar
base drive, thereby shortening turn-off time. The 311 comparator shifts the TLL-command level to bias the driver'S Enable input;
shifting is necessary because the SG3635's ground pin is returned to -15V. The 25Q resistor to ground limits the transistor's
reverse bias. Traces D, E and F show the 2N6308's base voltage
12 -125
APPLICATION NOTES - SG3635
and collector voltage and current, respectively - you can see that
collector turn-off time decreases to 200nsec, greatly reducing the
likelihood of secondary breakdown.
k
A
~
B
200V
2.2JF
(a)
C
+~
:D
10VJl
,......
PI
,P\
It
.........
II
Ir'
OUTPUT
E
OV
""\.
j
,
ZO=500
J
15V -=-
-
TRACE
A
B
C
D
E
F
VERTICAL
5V/DIV
200V/DIV
3A/DIV
5V/DIY
200V/DIY
.3A/DIV
HORIZONTAL
500 nSEC/DIY
500 nSEC/DIV
500 nSEC/DIY
500 nSEC/DIV
500 nSEC/DlY
500 nSEC/DIY
Figure 10. Dramatic Turn-Off-Time Differences Between Unipolarand Bipolar-Base-Drive Circuits (Figs 9a and 9b) are Evident in
This Photo. Long Collector-Voltage (trace B) and -Current (trace
C) ON-to-OFF Transitions Result From the Unipolar Drive (trace
A); the Bipolar Driye (trace D) Increases Turn-Off Speed More
Than Sevenfold.
Figure 9. Using Unipolar Base Drive (a) for a High-Power Transistor can Result in Slow Collector Turn-Off. A Bipolar-Drive Circuit
(b) Shortens Turn·Off Time Considerably by Sweeping out BaseEmitter Change. Moreover, the Negative Base Bias Improves the
Transistor's Breakdown Characteristics
(a)
ANATOMY OF A DRIVER Ie
Figure 11 (8) shows the SG3635 driver IC's internal organization.
The main consideraiion in the IC's design is to make logic-Ievel/
power-load interfaCing as straightforward as possible. The logiccompatible Enable and Pulse inputs operate according to the truth
table shown: Accepting drive from 74C Series circuits operating
at 1OV or more, they're compatible with all TLL forms except 54L.
You can allow the inputs to float to the HIGH state, but you must
force them to ground to produce ZERO.
ENABLE
INPUT ~~-",---,/
OUTPUT
~~~G~ ~--~:'V......,..---------~
ENABLE
1
o
1
o
PULSE
GND
1
1
0
0
(b)
Negative supply voltages are permissible at the ground pin, but
you must restrict the chip's total rail-to-rail voltage to 40V. The
internal regulator stabilizes the IC against supply variations; the
level-shift and interlock features provide proper drive levels and
prevent simultaneous output-device conduction. The output
sinks or sources 2A continuously (5A pk) with ±40Voutput swing;
the commutating diodes handle 5A pk. Finally, the thermalshutdown circuit disables the upper output device if chip temperature exceeds 160°C.
Why the interlock circuitry? It's important to prevent simultaneous
conduction of a source/sink pair's devices (b). This condition
usually arises during switching, when the respective devices are
f------.---t--o+vs
-V
'POTENTIALLY DESTRUCTIVE
SIMULTANEOUS CONDUCTIVE PATH
Figure 11. Providing Logic-to-Power-Drive Translation, the
SG3635 (a) contains both low and high-level circuitry. The
interlock circuitry-an important feature-allows only one power device to conduct at a time, thus avoiding transitional power-supply
short circuits (b) An IC without the interlock can produce large
current pulses (e) during switching. A test circuit (d) verifies the
IC's interlock circuitry; (e) shows no common current flows in the
output devices during switching.
interchanging OFF and ON states. During this Interval, substantial supply current flows through both devices, effectively shorting
12-126
APPLICATION NOTES - SG3635
(d)
the supplies. A common approach to alleviating the problem is
to make the stage switch quickly, minimizing concurrent ON
time.
The widely used 555 timer furnishes this simple solution. However, it still generates considerable supply glitches (c). Trace
B shows the large supply-current spike the IC's output pair produces when switching (trace A). Such a current spike, in conjunction with a supply bus's impedance, can result in unacceptable system noise or device destruction.
SCOPE
~Dooo
PULSE~
INPUT
3
14
.~ t~O
Q
D
74C74
Q
2
E
20W
SG36~~. -!-
U
P
5
4
3~
-=-
(c)
2
--
TEKTRONIX MODEL P6016/131
CURRENT PROBE
NOTES:
RETURN SG3635 LOAD AND GROUND-PIN LEADS SEPARATELY TO SUPPLY
A
B
r-
1\
-
(e)
r\
\1\
"-
"
A
B
TRACE I VERTICAL I HORIZONTAL
A
I~ 20V /DIV vI200nSEC/DIV
B
500mA/DIV 200nSEC/DIV
-V
\
\
j
rI""-
C
The SG3635's interlock circuitry ensures complete turn-off of one
output device before the other begins to turn on. This provision
eliminates supply shorts during switching, even when controlling
high power. To verify this section, use the figure's test circuit (d).
Part (e), trace A shows one phase (Q) olthe 7 4C74's output; trace
b depicts the driver's output.
TRACE I VERTICAL I HORIZONTAL
A
1.10V/DIV 11200nSEC/DIV
20V/OIV
200nSEC/DIV
B
C
100mA/DIV 200nSEC/DIV
When Q switches LOW, the SG3635 unclamps its sink transistor,
then allows the source device to turn on. The reverse holds true
when Q switches HIGH. These intentional turn-on delays account
forthe 200-nsec output-timing skew. Note in trace C - the groundpin-current - that no current ever flows directly through the source/
sink pair.
•
12 -127
12-128
APPLICATION NOTES - SG1731
SILICON
GENERAL
MC-2
LINEAR INTEGRATED CIRCUITS
SIMPLIFIED HIGH-EFFICIENCY MOTOR DRIVE SYSTEMS
WITH NEW PWM INTEGRATED CIRCUITS
Edited by Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
ABSTRACT
This paper describes a new pulse width modulator circuit designed specifically for DC motor control.
I! provides a bi-directional pulse train output in response to the magnitude and polarity of an analog error
signal input. The device is useful as the control element in motor-driven servo systems for precision
positioning and speed control, as well as in audio modulators and amplifiers using carrier frequencies
to 350kHz.
INTRODUCTION
Power management engineers have been aware for a number of
years of the efficiency advantages of switching power supplies
over linear designs. In response to growing production of switchers, the semiconductor industry has spawned a number of pulse
width modulator (PWM) integrated circuits of varying degrees of
complexity for the control of these power supplies.
tional rotation. All of the necessary control elements for two
quadrant operation are found in the PWM circuit to be described,
which is designated the SG1731.
'''s0-------
",0-----:---------,
Perceptive designers soon realized that the same efficiency
advantages apply to motor control. Unfortunately, when they
attempted to utilize existing PWM circuits, they found that the
architecture was not optimized for motor control. so many
auxiliary components had to be added to work around the restrictions of the PWM circuit that totally discrete designs were frequently found to be more economical.
The main difficulty has been that PWM controllers for switching
power supplies were designed to be one quadrant power conditioners; i.e., the polarity of DC output voltage is fixed and proportional to a unipolar reference voltage. A second difficulty has been
that power supply controllers attempt to produce an AC waveform
of variable energy content, since power must be transferred
through a high frequency transformer. This requires that PWM
pulses alternate from side to side with a dual-driver architecture.
The requirements for PWM motor control are different: The
integrated pulse train must have a DC component proportional to
the magnitude of the applied reference voltage, and a polarity
determined by the sign of the reference to accomplish bi-direc-
c, 0--+----+2V~_U-_."""
-~o_---------r_~
r
SUBSTRATE
SHUTDOWN
Figure 1. SG1731 Block Diagram
BLOCK DIAGRAM
The SG1731 contains a triangle waveform oscillator, a wideband
operational amplifier for error voltage generation, a summing!
scaling network for level-shifting the oscillator waveform, externally programmable PWM comparators, and dual ±100mA, ±32
volt totem pole drivers with commutating diodes for full bridge
January 1990
12 -129
II
APPLICATION NOTES - 8G1731
output drive. A TTL-compatible SHUTDOWN terminal forces the
output drivers into a floating high-impedance state when driven
LOW. Supply voltage to the circuit may be either from dual
positive and negative supplies, or single-ended.
With deadband operation, there is a small region around the null
point of the servo loop where no power is applied to the motor.
This conserves power, which may be desirable in some applications, but it also results in loss of both positioning accuracy and
mechanical stiffness.
PULSE WIDTH MODULATION
Pulse width modulation occurs by adding an error voltage to the
triangle waveform, attenuating the resulting signal by a factor of
2, and comparing it to threshold voltages +Vr and -Vr' which are
applied to pins 1 and 8 respectively. Figure 2 illustrates the case
for VI1.< +Vr . When the error voltage is zero, no threshold
crossings occur, and the output drivers remain in the LOW state.
If the error voltage is sufficiently positive, the upper threshold will
be periodically crossed by the shifted triangle waveform and
output driver A will switch to the HIGH state. As the error voltage
becomes larger, the duty cycle of driver A will linearly increase
towards 100%. The same action occurs at output driver B for
negative error voltages.
+VT -
CASE A
ZERO ERROR
VOLTAGE
-
-
-
-
-
-
-
GND?
-Vr - -
-
~+
-
-
'S7
--- -
-
-
-
-
-
-
~
-
"
-
The other possible mode of operation is shown in Figure 3, where
V 11.>Vr' At the loop null point the motor still receives drive pulses,
which provides resistance to armature movement by external
forces. The integrated drive voltage is still zero, since the drive
pulses alternate in polarity with identical pulse widths at the null
point.
CASE A
ZERO ERROR
VOLTAGE
:::--a-~-
-
-
CASE B
POSITIVE ERROR
VOLTAGE
OUTPUT A _ _ _ _ _ _ _ _ _ _ _ _ __
7
- 1-
-Vr - -
-1
-
V
I
-I-
-
"-
OUTPUT A
OUTPUT B _ _ _ _ _ _ _ _ _ _ _ _ __
OUTPUT 8 - - - - - - - - - - - - - -
+VT -
2fJs.-.2fts:.'V
GND ,.
CASE B
POSITIVE ERROR
VOLTAGE
-VT -
-
+Vr -
"
NEGA;~~~RROR
_1_1- ____ 1_1 __ _
VOLTAGE
OUTPUT A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A
-
-
-
-
A
~ ~
~
-l'V'r
- ~
-~
~
-Vr -
-
:~:~::~
OUTPUT 8 - - - - - - - - - - - - - -
+Vr - -
-
GND
-
-
H
F
-
Figure 3. Non-Deadband Operation
CASE C
NEGA TlVE ERROR
VOLTAGE
This is the preferred mode of control in a missile fin actuator
system where aerodynamic forces on the airfoil attempt to move
the motor armature away from the null position. A second
example where deadband operation is not desirable is a switching, or "Class D," audio amplifier. Cross-over distortion would be
unacceptable, and poor speaker damping would also result.
Figure 2. Deadband Operation
4_ OSCILLATOR CIRCUIT
A motor connected across the full bridge formed by drivers A and
B will receive a high frequency pulse train which, when integrated
by the LR time constant of the armature, will result in a voltage
drive proportional tothe magnitude ofthe error signal. The polarity
of the drive signal will be the same as the polarity of the error
voltage.
The triangle oscillator consists of two voltage comparators, a seV
reset flip-flop, a bi-directional 500pA current source, and an
external timing capacitor CT' A positive reference voltage applied
to pin 2 (2V11+) sets the peak value ofthe triangle., and a negative
reference voltage at pin 7 (2VI1-) determines the valley of the
12 -130
APPLICATION NOTES - SG1731
triangle. Normally the reference voltages are equal, so that a
symmetrical waveform about ground results.
The desired oscillator frequency can be obtained by first choosing a peak-to-peak voltage for the triangle waveform, and then
selecting the proper value of CT from Equation 3.
+Vs
As a design aid, the solutions to Equation 3 over the recommended range of T osc and V osc are presented in graphical form
in Figure 5. The lower limit on T osc is 2.85psec, corresponding to
a maximum frequency of 350kHz. The maximum value of V osc'
(2VM)-(2VI!J.-), is 10 volts peak-to-peak for linear waveforms.
>
I
~
10
•
~
<
~
~I
~
Figure 4. SG1731 Oscillator Schematic
Circuit operation is as follows: Transistors 06 and 09 form the set!
reset flip-flop. Assume that 09 is conducting and 06 is off. The
collector voltage of 09will be low compared to that of 06, resulting
in 07 conducting and 08 being off. The current from the 500pA
source will flow into CT and a positive voltage ramp will occur at pin
6. When the voltage exceeds 2VM, the comparator formed by 01
through 04 changes state, turning on 05. This removes base
drive from 09 and the flip-flop will change state. The currentsteering transistor pair 07 and 08 now switch the 1mA discharge
current source onto the CT bus. Since the 500pA charging source
is still active, the net discharge current out of CT is the difference
of the two sources, or 500pA. Since monolithic construction allows
close ratioing of current sources, the discharge rate will closely
match the charge rate. When the voltage on CT falls below 2VI!J., the comparator formed by 011 through 014 will reset the flip-flop
and another charge cycle will begin. Since the values of the
current sources are fixed at a nominal 500pA, the oscillator
frequency may be calculated as follows:
!§
10
20
50
100
200
OSCILLATOR PERIOD -
500
lms 2ms
Sms 10ms 20ms
me
Figure 5. SG1731 Oscillator Period vs. Vesc and C T
ERROR AMPLIFIER
he error amplifier is a high slew rate unit designed for low input
offset voltage and bias current under equilibrium conditions. It
consists of two gain sections, with frequency compensation for
unity closed-loop gain stability in the second stage. The first stage
is formed by transistors 01 through 012. When the differential
input voltage is zero, the emitter voltages of 02 and 03 are equal,
and the collector currents of 05 and 06 are equal to a small
fraction olthe collector current in 04 and 07. The value of current
is set by current sources 09 and 010 and the two 5K emitter
+Vs
For a given capacity and current,
.i!'L
dt
= _1_
C
or
dt= _1- dV
C
where
dV
I
dt
C
vosc peak-to-peak
500 !!A = 5 X 10.4 A
1/2 Tosc (assuming symmetry)
Variable
II
Therefore
2CdV
T osc = 2dt = 5 x 10"
-Vs
Figure 6. SG1731 Error Amp Schematic
12-131
APPLICATION NOTES - SG1731
resistors. Transistors 08, 011 and 012 form a compound current
mirror which converts the full differential voltage gain of the input
stage into a single-ended gain referred to -Vs' A Darlington gain
stage formed by 018 and 020 provides the large voltage swing
required for the amplifier output. When the differential input
voltage is not zero, that voltage appears across the 5K resistors
of the input stage, increasing the operating current. Simultaneously this increased current is sensed by 01 , and current supply
to the output stage is increased proportionally. Since more
current is available to charge the 30pF compensation capacitor,
the amplifier output voltage slews at a much higher rate. When
equilibrium is again reached, the bias currents return to their
normal quiescent levels.
As shown in Figure 7, the error amplifier is capable of excellent
power bandwidth, Full output swing to 200kHz is available, with
slew rates exceeding 15 volts/microsecond. These dynamic
characteristics allow application to audio modulation circuits with
very low transient distortion.
The amplifier frequency-gain plot is a constant SdB/octave roll-off
to unity gain, resulting both in unity· gain stability and good
transient response. Typical DC voltage gain is 11 OdB into a 2K
load, and unity gain crossover frequency is 1 megahertz.
OUTPUT DRIVERS
The output stage is a non-saturating quasi-complementary high
current switch for efficient high frequency operation. Transistors
03,04,05 and OS form a high voltage Schmitt trigger input stage.
The positive feedback produces fast switching times and jitterfree pulse width modulation. 07 and 09 provide output current
sourcing, and 08, 010 and 011 provide currentsinking. Commutation diodes D1 and D2 clamp inductive loads to the supply rails.
Their current capability is the same as the output transistors:
200mA peak.
OUTPUT A
15
:>
'(
w
<.:>
10
1\
«
f-
-'
0
>
5
go
THD<5%
a
::)
/'f!'
0
«
'"
w
-+--t::€=2~
'r--
±VS=±15VOLTS
f::)
FROM PMW
COMPARATOR
-5
Figure 9. Half-Bridge Output Driver Schematic
Ij
a.
-10
TYPICAL APPLICATIONS
10
100
lK
10K
1M
lOOK
Simple Position Servo
FREQUENCY-(Hz)
Figure 7. Error Amp Power Bandwidth
Asimple.low-voltage battery-powered position servo is illustrated
in Figure 10. A resistive divider network sets up the reference
120
I-100
m
80
z
60
i'--..
SGl
.--,--t--®'6 ""\Is
~
"
'(
;j'
<.:>
w
<.:>
«
40
-'
0
>
""
'\
1\
f-
20
a
0.1
10
100
lK
10K 100K
1
Cr 6
~
1M
FREQUENCY-(Hz)
Figure 8. Error Amp Open-Loop Frequency Response
Figure 7. Error Amp Power Bandwidth
12 -132
APPLICATION NOTES - SG1731
voltages for triangle waveform amplitude and PWM thresholds.
Since the circuit is powered by battery, Vl!'. is designed to be less
than +VT (deadband) to conserve power. The 9 volt DC motor is
driven directly from the output drivers, and it in turn drives a
position feedback potentiometer through a geartrain. The position feedback voltage is subtracted from the external position
command voltage in the on-chip error amplifier. The difference
between commanded position and actual position generates an
error voltage which in turn generates a series of PWM pulses to
the motor to correct the difference. Once null has been reached,
no further power is applied to the motor until a new position
command voltage Is received, or the wiper is moved out of position
by external forces.
Figure 12. High Torque Bi-Directional Motor Speed Control Circuit
High Torque Position Servo
Figure 11 illustrates a high power version of the previous position
servo loop. The control circuit is powered from balanced positive
and negative supply voltages, and the output drivers switch the
load between ±32 volt supply rails for maximum output power.
Complimentary emitter follower buffers on each output provide
increased current gain and power handling capability.
PWM Audio Power Amplifier
A complete PWM power audio amplifier is illustrated in this last
application. The circuit reconstructs an amplified version of the
audio input voltage by deriving the feedback signal from the
speaker voice coil. An oscillator frequency of 300kHz was chosen
to maintain a ratio of at least 15 to 1 between the carrier frequency
and the highest modulation frequency (20kHz).
Ratios of at least 10 to 1 are necessary for acceptable linearity, low
distortion and good transient response. An LC output filter
smoothes the pulse width modulated output to the speaker; its
deSign is critical for low distortion. This circuit, consisting of one
integrated circuit and four power transistors, can deliver 150 watts
RMS of power into a 40hm load.
Figure 11. High Torque Position Servo
Motor Speed Control
In Figure 12, a bi-directional motor speed control circuit is derived
from the previous circuit by substituting a tachometer for the
position pot in the motorfeedback circuit. The external command
voltage now represents a speed rather than a position, with
direction of motor rotation a function of command voltage polarity.
Magnetictape drives are an example ofthis configuration, with the
velocity feedback voltage frequently derived from an encoded bit
pattern on the tape.
Figure 13. P.W.M. Audio Power Amplifier
CONCLUSION
A new pulse width modulator integrated circuit designed for motor
control has been described which includes all the circuitry necessary for implementing high efficiency bi-directional controllers.
Inputs and outputs have been designed for maximum flexibility,
allowing the device to be useful in a wide range of position and
speed servo systems.
12-133
II
12-134
APPLICATION NOTES - SG1731
SILICON
GENERAL
MC-3
LINEAR INTEGRATED CIRCUITS
SIMPLIFY FEEDBACK CONTROLLERS WITH A
2-QUADRANT PWM Ie
A 2-Quadrant Pulse-Width-Modulator IC Eliminates Many of the Problems
Arising With Unipolar Devices in Feedback-Control Applications.
Stan Dendinger
Manager, Advanced Product Development
Silicon General, Inc.
INTRODUCTION
The SG1731 pulse-width modulator (PWM) IC brings to motor
controllers and similar applications the efficiency previously limited to switching-power-supply circuitry. As a result, you can use
it to design motor-controller circuits having parts counts smaller
than previously achievable.
Switching-power-supply PWM controllers are designed to be 1quadrant power conditioners, furnishing a dc output voltage with
fixed polarity and amplitude proportional to a unipolar reference
Voltage. Motor controllers, on the other hand, require an integrated pulse train with a dc component proportional to the magnitude of an applied reference voltage and polarity determined by
the reference's sign. Otherwise, they can't produce bidirectional
rotation.
In addition, the architecture of power-supply PWM ICs often
proves inappropriate for motor-control tasks, requiring so many
auxiliary circuits that totally discrete designs often prove more
economical.
PWM power-supply controllers attempt to produce a variableenergy-content ac waveform, because power must be transferred
via a high-frequency transformer. Unlike those from a PWM motor
control IC, the PWM pulses produced by these devices must
alternate and are therefore produced by a dual-driver architecture.
Fig 1 shows the SG1731 's structure. The device contains a
triangle-waveform oscillator whose frequency is determined by
+Vo
14
+-+--+-+,,13 OUTPUT A
+-+--+-+,,12 OUTPUT B
Figure 1. A DC-Motor Pulse-Width-Modulator IC. The SG1731 features 50Hz to 350kHz oscillator range,
adjustable deadband operation, a high-slew-rate error amplifier, a Shutdown input providing floating outputs, and
dual 1OOmA source/sink output drivers capable of operating from supplies to +32V.
January 1990
12 -135
•
APPLICATION NOTES - SG1731
an external capacitance at pin 6 and whose amplitude can be set
through resistor or voltage programming at pins 2 and 7. The IC
also contains a wide-band op amp for error voltage generation, a
summing/scaling network for level-shifting the oscillator waveform, externally programmable PWM comparators and dual
±100mA continuous (±200ma pk), ±32V totem-pole drivers with
commutation diodes for full-bridge output drive. Typical supply
voltages are ±15V, although the device can function at values as
low as ±3.5V. You can use dual- or single-polarity supply
voltages. Pin 15, the Shutdown terminal, forces the output drivers
into high-impedance states when LOW.
ERROR VOLTAGE CONTROLS PULSE-WIDTH
MODULATION
Pulse-width modulation occurs when an error voltage gets added
to the triangle waveform, attenuating the resulting signal by a
factor of two and comparing it with threshold voltages +Vr and -Vr
(pins 1 and 8). Flg2illustratesthecaseforV Vr At the loop null point, the motor receives drive pulses that
resist externally produced armature movement. The integrated
drive voltage is OV with no error voltage (Fig 3a) because the drive
pulses alternate in polarity and have identical widths at the null
point. Figs 3b and 3c show the effects of error voltages on the
oscillator signal.
This is the preferred control mode in a missile-finactuator system,
for example, where aerodynamic forces on the airfoil attempt to
move the motor armature away from the null position.
--
"'"
-
CASE A
-
ZERO ERROR
VOLTAGE
OUTPUT A _ _ _ _ _ _ _ _ _ _ _ _ _ __
OUTPUT 8 _ _ _ _ _ _ _ _ _ _ _ _ _ __
+VT -
-,
CASE B
POSITIVE ERROR
VOLTAGE
-VT -
z:rs:.--z:rs:.,
-
_1_1- ____ 1_1_ ....:. _
CASE B
POSITIVE ERROR
VOLTAGE
OUTPUT A
+Vr - - - -
CASE C
VOLTAGE
~::
OUTPUT A
OUTPUTS
-Vi -
-
-
1-
-1
-
V
I
-I-
-
"-
OUTPUT A
OUTPUT 8 - - - - - - - - - - - - - - -
NEGATIVE ERROR
:::--6:---6:-7
-- -
OUTPUT 8 - - - - - - - - - - - - - -
- - --.....:...-
+VT -
:r:z:s;rz:s:;
~L..-_---IR
-
.
N,e;;~
~
,CRROR
VOLTAGE
-VT _
OUTPUT B
Figure 2. With Oscillator Voltage Less Than Threshold Voltage,
the SG1731 's Outputs Switch LOW to HIGH When the Error
Voltage Shifts Oscillator Output Outside the Threshold
-
-
-
-
-
-
-
-
-
--
A.
~.:\.
=.7....- _.:\.
-l\VIr
- ~-
~
OUTPUT A
•
-
A.
eND
.=1
•
-
F
R
•
Figure 3. With Oscillator VoHage Greater Than Threshold Voltage
in the SG 1731, Leck of a Deadband Provides Resistance to
MotorMovement Caused by External Forces.
12 -136
APPLICATION NOTES - SG1731
You can configure the SG1731 as a bidirectional motor-speed
controller as shown in Fig 4, The motor specified runs directly
from the device's outputs, and the tachometer produces an output
directly proportional to the motor's speed and direction. This highlevel signal gets divided down and filtered by the discrete components associated with the tachometer, then applied to the
SG1731's error-amplifier input. The 1731 internally compares
this signal with the speed-control input's value and provides
output drive of the appropriate phase and magnitude, completing
a speed-control loop. Set the comparator voltages for nondeadband operation. The lowest rotation speed depends on the
motor's friction characteristics.
Instantaneous-direction-reversing applications might require an
optional current-limiting circuit ratherthan ±15V applied directly to
pins 11 and 14. Atthetime of direction reversing, the motor draws
peak currents that could damage the 1731 's output drivers. O,'s
ability to supply current is controlled by O;s state, which in turn
depends on the voltage across the 4'-1 current-sensing resistor. If
the motor current exceeds 200 to 250mA, O2 turns on and 0,
shuts off.
EXTEND CONTROL CAPABILITY WITH HIGH·CURRENT
DRIVERS
Another bidirectional speed-control loop appears in Fig 5. Here,
SG1635 drivers control higher motor power and eliminate the
need for a speed-monitoring tachometer; instead, back EMF
produced by the motor serves as a feedback signal. This
arrangement entails some increase in circuit complexity but
eliminates the tachometer's cost.
The circuit's basic servo mode is similar to that of Fig 4. The 311
comparator (IC,) senses the polarity ofthe input command signal.
Its output goes to the 1635s via a diode and inverter, allowing both
1635s to be OFF, neither sinking no sourcing current, when the
1731 is not producing output pulses. Fig 6 shows the circuit
waveforms. When either 1731 output is HIGH, the other output is
LOW, and the motor is driven. When both outputs are LOW, the
1635s are OFF and the motor is electrically floating.
The motor's inductive turn-off spike gets damped by the 1635s'
internal diodes. After turn-off, the waveform returns to a dc level
15V
0.00151"F
+~
-=-
15V
D~+
-=-
lK
2jJ.F
16
14
0+
-=-
15V
10K
01
-=+~
10
2
10 PIN 11 SG1731
2K
12
MOTOR-TACH
4
10
-15V
SG1731
OPTIONAL
CURRENT
LIMIT
~250mA
-=8
11
NOTES:
MOTOR-TACH:
CANON
CKT-26-TS-3SAE
2K
7
10K
D
-=-
-15V
9
3
lOOK
-10 TO 10 V
SPEED-CONTROL INPUT
Figure 4. In This Bidirectional Motor-Speed Controller, the Tachometer Provides Feedback While the Current-Limiting Circuit
Protects the Outputs From Surge Currents.
12-137
•
APPLICATION NOTES - SG1731
determined by the back EMF ofthe undriven motor, now functioning as a tachometer. This level gets differentially picked off by the
301 A op amp (le3 ) , whose output feeds a switched synchronous
filter. This filter, composed of the FET and the 100-kQ/O.01-IlF
combination, samples the back-EMF value during the motor's
powered interval.
A 311 (lez) gates the FET switch synchronously with the 1731 's
output. The diode-Re network feeding le z allows either output to
actuate the filter. The 1O-kQ/O.02-IlF network's decay time length
(Fig 6, trace D) ensures that the FET drive (trace E) remains OFF
until well after the inductive spike has settled out.
The pure dc filter output feeds back to the 1731 's amplifier to
complete the speed-control loop. The zener-diode bridge clamps
all inputs above approximately ±10V; otherwise the 1731's outputs would saturate at dc and the switched feedback loop would
never operate.
Another SG1731 application appears in Fig 7. Here, two 1731 's
bidirectionally control the speed and shaft position of a printedcircuit-type motor.
The shaft position gets sensed at the output of a geardown
transmission. Slave the 1731 s together to avoid producing
O.04!'f'
.~
15V
2,
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