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TEXAS
INSTRUMENTS

Digital Signal Processing
Applications with the TAfS320 Familv

1990

1990

Digital Signal Processor Products

DigHa/Signa/Processing
Applications with the TMS320 Family
Volume 2
Edited by

Panos Papam/challs, Ph.D.
Digital Signal Processing

Semiconductor Group
Texas Instruments

•

TEXAS

INSTRUMENTS

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to discontinue
any semiconductor product or service identified in this publication without notice.
TI advises its customers to obtain the latest version of the relevant information
to verify, before placing orders, that the information being relied upon is current.
TI warrants performance of its semiconductor products to current specifications
in accordance with Tl's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Unless mandated by government requirements, specific testing of all parameters of
each device is not necessarily performed.
TI assumes no liability for TI applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
Nor does TI warrant or representthat license, either express or implied, is granted
under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.

TRADEMARKS
ADI and AutoCAD are trademarks of Autodesk, Inc.
Apollo and Domain are trademarks of Apollo Computer, Inc.
ATVista is a trademark of Truevision, Inc.
Code View, MS-Windows, MS, and MS-DOS are trademarks of Microsoft Corp.
DEC, DigitalDX, VAX, VMS, and Ultrix are trademarks of Digital Equipment Corp.
DGIS is a trademark of Graphic Software Systems, Inc.
EPIC, XDS, TlGA, and TlGA-340 are trademarks of Texas Instruments, Inc.
GEM is a trademark of Digital Research, Inc.
GSS*CGI is a trademark of Graphic Software Systems, Inc.
HPGL is a registered trademark of Hewlett-Packard Co.
Macintosh and MPWare trademarks of Apple Computer Corp.
NEC is a trademark of NEC Corp.
PC-DOS, PGA, and Micro Channel are trademarks of IBM Corp.
PEPPER is a registered trademark of Number Nine Computer Corp.
PM is a trademark of Microsoft Corp.
PostScript is a trademark of Adobe Systems, Inc.
RTF is a trademark of Microsoft Corp.
Sony is a trademark of Sony Corp.
Sun 3, Sun Workstation, Sun View, Sun Windows, and SPARC are trademarks of
Sun Microsystems, Inc.
UNIX is a registered trademark of AT&T Bell Laboratories.

Copyright © 1990, Texas Instruments Incorporated

CONTENTS
FOREWORD....... ...... ........ ... ........................................ ............. ...

v

PREFACE.......................... .........................................................

vii

PART I. INTRODUCTION
1. The TMS320 Family and Book Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

2. The TMS320 Family of Digital Signal Processors
(Kun-Shan Lin, Gene A. Frantz, and Ray Simar, Jr., reprinted from PROCEEDINGS OF THE IEEE,
Vol. 75, No.9, September 1987) ..........................................................

11

3. The Texas Instruments TMS320C25 Digital Signal Microcomputer
(Gene A. Frantz, Kun-Shan Lin, Jay B. Reimer, and Jon Bradley, reprinted from IEEE Micro Magazine,
Vol. 6, No.6, December 1986) .......................................................... : .

29

PART II. DIGITAL SIGNAL PROCESSING INTERFACE TECHNIQUES
4. Hardware Interfacing to the TMS32OC2x
(George Troullinos and Jon Bradley) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53

5. Interfacing the TMS320 Family to the TLC32040 Family
(Linear Products - Texas Instruments). ... . .. . .. . . .. . . . . .. . . . . .. . . . .. . . . . . . . . . . . . ... . . . . . . .. 107
6. ICC Requirements of a TMS32OC25
(Dave Zalac) ........................................................................ >.

• ••

153

7. An Implementation of a Software UART Using the TMS32OC25
(Dave Zalac). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . .. . . . . . . . . . . . . . . .. . .. . .. . .... 167
8. TMS32OC17 and TMS370c010 Serial Interface
(Peter Robinson). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 189

PART

m. DATA COMMUNICATIONS

9. Theory and Implementation of a Splitband Modem Using the TMS32010
(George Troullinos, Peter Ehlig, Raj Chirayil, Jon Bradley, and Domingo Garcia). . .. . . . . .. . .. . .. .. 221
10. Implementation of an FSK Modem Using the TMS32OC17
(Phil Evans and Al Lovrich). .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. .. . . . . . ... 331
11. An AIl-Digital Automatic Gain Control
(AI Lovrich and Raj Chirayil) ............................................................. 389

PART IV. TELECOMMUNICATIONS
12. General-Purpose Tone Decoding and DTMF Detection
(Craig Marven) ....................................................... , . . . . . . . . . . . . . . . . .. 423

PART V. CONTROL
13. Implementation of PID and Deadbeat Controllers with the TMS320 Family
(lrfan Ahmed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 529

iii

PART VI. TOOLS
14. TMS320 Algorithm Debugging Techniques
(Peter Robinson). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 585
TMS320 BmLIOGRAPHY .................................................................... 597
INDEX .......................................' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 615

iv

Foreword

Much has happened in the TMS320 Family since Volume 1 of Digital Signal Processing
Applications with the TMS320 Family was published, and Volumes 2 and 3 are a timely update to
the family history.
The DSP microcomputers keep changing the perspective of the systems designers by offering more computational power and better interfacing capabilities. The steps of change are coming
more quickly, and the potential impact is greater and greater. Because things change so rapidly in
this area, there is a pressing need for ways to quickly learn how to utilize the new technology. These
new volumes respond to that need.
As with Volume 1, the purpose of these books is to teach us about the issues and techniques
that are important in implementing digital signal processing systems using microprocessors in the
TMS320 Family. Volume 2 highlights the TMS320C25; and Volume 3, the TMS320C30 chip. A
large part of the books is devoted to such matters as characteristics of the TMS320C25 and
TMS320C30 chips, useful program code for implementing special DSP functions, and details on
interfacing the new chips to external devices. The remainder of the books illustrates how these
chips can be used in communications, control, and computer graphics applications.
What these two volumes make clear is how remarkably fast the field of DSP microcomputing
is evolving. IC technologists and designers are simply packing more and more of the right kind of
computing power into affordable microprocessor chips. The high-speed floating-point computing
power and huge address spaces of chips like the TMS320C30 open the door to a whole new class
of applications that were difficult or impractical with earlier generations offixed-point DSP chips.
The signal processing theorists and system designers are clearly being challenged to match the creativity of the chip designers.
The present books differ from Volume 1 in the inclusion of a small section on tools. This is
a hopeful sign, because it is progress in this area that is likely to have the greatest impact on speeding
the widespread apprication of DSP microprocessors. While useful design tools are beginning to
emerge, much more can be done to help system designers manage the complexity of sophisticated
DSP systems, which often involve a unique combination of theory, numerical and symbolic processing algorithms, real-time programming, and mUltiprocessing. No doubt future volumes of Digital Signal Processing Applications with the TMS320 Family will have more to say about this important topic. Until then, Volumes 2 and 3 have much useful information to help system designers
keep up with the TMS320 Family.
Ronald W. Schafer
Atlanta, Georgia
November 14, 1989

Digital Signal Processing Applications with the TMS320 Family, Vol. 2

v

vi

Digital Signal Processing Applications with the TMS320 Family, Vol. 2

Preface

With the advancement of DSP devices, the application of Digital Signal Processing has become more widespread. Areas that were considered outside the domain of DSP devices because
of cost, processing power, or peripheral capabilities (such as graphics, control, and consumer products) have seen applications using digital signal processors. On the other hand, the diverse needs
of the designer have been addressed in the architectures and the performance of the newer devices.
Volume 2 of Digital Signal Processing Applications with the TMS320 Famity contains applications on the first and second generations of the TMS320 Family (fixed-point devices). It is a continuation of Volume 1 in the sense that it addresses the same needs of the designer. The designer
still has the task of selecting the DSP device with the appropriate cost, performance, and support,
developing the DSP algorithm that will solve his problem, and implementing the algorithm on the
processor. This volume tries to help the designer by bringing him up to date in the applications of
newer processors or in different applications of earlier processors.
The objectives remain the same as in Volume 1. First, the application reports can be used as
examples of device use. They can also serve as tutorials in programming the devices. Of course,
the same purpose is served on a more elementary basis by the software and hardware applications
sections of the corresponding user's guides. Second, since the source code of each application is
provided with the report, the designer can take it intact (or extract a portion of it) and place it in
his application.
It is assumed that the reader has exposure to the TMS320 devices or, at least, has the necessary
manuals (such as the appropriate TMS320 user's guides) that will help him understand the explanations in the reports. The reports themselves include as references the necessary background material. Additionally, the Introduction gives a brief overview of the available devices at the time of the
writing, and points to sources of more information.

The reports are grouped by application area. The term report is used here in a broad sense,
since some articles from technical publications are also included. The authors of the reports are either the digital signal processing engineering staff of the Texas Instruments Semiconductor Group
(including both field and factory personnel, and summer students) or third parties.
The source code associated with the reports is also available in electronic form, and the reader
can download it from the TI DSP Electronic Bulletin Board (telephone (713) 274-2323). If more
information is needed, the DSP Hotline can be called at (713) 274-2320.
The editor wishes to thank all the authors and the reviewers for their contribution to this volume of application reports.
Panos E. Papamichalis, Ph.D.
Senior Member of Technical Staff

Digital Signal Processing Applications with the TMS320 Family, Vol. 2

vii

viii

Digital Signal Processing Applications with the TMS320 Family, Vol. 2

Part I. Introduction
1. The TMS320 Family and Book Overview
2.

The TMS320 Family of Digital Signal Processors
(Kun-Shan Lin, Gene A. Frantz, and Ray Simar, Jr., reprinted from
PROCEEDINGS OF THE IEEE, Vol. 75, No.9, September 1987)

3. The Texas Instruments TMS320C25 Digital Signal Microcomputer
(Gene A. Frantz, Kun-Shan Lin, Jay B. Reimer, and Jon Bradley, reprinted
from IEEE Micro Magazine, Vol. 6, No.6, December 1986)

1

2

TMS320 Family and Book Overview
Digital signal processors have found applications in areas where they were not even considered a few years earlier. The two major reasons for such proliferation are an increase in processor
performance and a reduction in cost. Volume 2 of Digital Signal Processing Applications with the
TMS320 Family presents a set of application reports on the first- and second-generation TMS320
devices.

Organization of the Book
The application reports in this book are grouped by subject area:
•
•
•
•

Introduction
DSP Interface Techniques
Data Communications
Telecommunications

• Control
• Tools
• Bibliography
The Introduction contains this overview and two review articles. The first article gives a
general description of the TMS320 family and is reprinted from a special issue of the IEEE Proceedings, while the second article discusses the TMS320C25 device and is reprinted from the IEEE
MicroMagazine. The overview points out how the TMS320 family has grown since the two articles
were published and also introduces newer devices.
The section on DSP Interface Techniques contains articles on interfacing first- and secondgeneration devices with external hardware, such as memories, NO and D/A converters, or microcontroller devices like the TMS370 series. Other articles cover. the implementation of a UART on
the TMS320C25 and the power dissipation of the TMS320C25.
The three articles in the Data Communications section deal with different aspects of modem
implementations. A V.22 design is presented in the first article, a 300-bps FSK modem in the second, and an Automatic Gain Control (AGC) in the third. In all cases, first-generation devices are
considered.
The following three sections contain one article each. In the Telecommunications section,
a generalized tone decoding and DTMF detection method is presented. The Control section article
gives insight into the relatively new application of digital signal processors in digital control. In
the Tools section, the article describes ways to debug the algorithms with the aid of spreadsheets
and other packages.
The Bibliography section contains a list of articles mentioning DSP implementations using
TMS320 devices. The different titles are listed chronologically and are grouped by subject. The
list is not exhaustive, but it gives enough pointers for pursuing practical implementations in representative application areas.
Digital Signal Processing Applications with the TMS320 Family, Vol. 2

3

The TMS320 Family of Processors
The TMS320 Family of digital signal processors started with the TMS32010 in 1982, but it
has been expanded to encompass five generations (at the time of this writing) with devices in each
generation. Figure 1 shows this progression through the generations. The TMS320 devices can be
grouped in two broad categories: fixed-point and floating-point devices. As implied by Figure 1,
the first, second, and fifth generations are the fixed-point devices, while the third and the fourth
geAerations (the last one under development) support floating-point arithmetic.

Figure 1. TMS320 Family Roadmap
Floating-point DSP
. Fixed-point DSP ----,-.....,...,--,
* 1990 NEWTMS320

TMS320C4x
*TMS320C40
TMS320C30

P m

*TMS320C30·26~

e f
r

I

f

0

0

p

r

5

a

C

TMS320C1x

/

m
n i

e

---",---

P
5

__~_ _

*TMS320C31

TMS320C10, ·14
TMS320C10·25
TMS320C15/E15
TMS320C15·25
TMS320C17/E17
TMS320C14/E14

TMS32020
TMS320C25
TMS320E25
TMS320C25·50
*TMS320C26

*TMS320C50
*TMS320C51

Generation

4

Digital Signal Processing Applications with the TMS320 Family, Vol. 2

The following article, "The TMS320 Family of Digital Signal Processors," by Lin, et. aI.,
is reprinted from the proceedings of the IEEE and gives an overview of the TMS320 family. Since
additional devices have been developed from the time the article was written, this section highlights
these newer devices. Table 1 shows a comprehensive list of the currently available TMS320 devices
and their salient characteristics.
Table 1. TMS320 Family Overview
Memory
.Gen

1st

Device

5th

RAM

(ns)

Integer
Integer
Integer
Integer
Intcger
Integer
Integer

144
144
144
256
256
256
256
256
256
256

TMS320C2S·50.
TMS320E25 ,
TMS320C26

Integer
Integer
Integer
Integer
Integer

200
100
80
100
100

544
544
544
544
I.5K

TMS320C30'

Float Pt

60

TMS320C50.

Integer

50

TMS32OC25~

3rd

Integer
Integer
Integer

Time
200
160
280
160
200 .
160
200
160
200
200

TMS320ClO'
TMS32OCIO·25
TMS320CIO·14
TMS320EI4
TMS320C15'
TMS320C15·25 ,
TMS320E15'
TMS320EI5·25
TMS320CI7
TMS320EI7
TMS32020'

2nd

Data
Type

Cycle

t

External DMA

•*

External/lntemai DMA

On·
Chip
ROM

EPROM

I/O
OlT.
Chip

Parallel

Serial

8xl6
8xl6
8xl6
7xl6
8xl6
8><16
8xl6
8xl6
6xl6
6xl6
16xl6
16xl6
16xl6
16xl6

256

128K
128K
128K
128K
128K

I
I
I
I
1

2K

4K

16M

16Mx32

8.5K

2K

128K

16x16

4K
4K
4K
4K
4K
4K
4K
4K
4K
4K

On·
Chip

Package

Timers

4K
4K
4K
4K
4K
4K
4K
4K
4K
4K

1.5K
UK
UK

DMA

1

4

2
2

1
I

DlPIPLCC
DlPIPLCC
DlPIPLCC
CERQUAD
DlPIPLCC
DlPIPLCC
DlP/CERQUAD
DlP/CERQUAD
DlPIPLCC
DlP/CERQUAD

t
t
t
t
t

I
I
I
I
1

PGA
PGAlPLCC
PGAlPLCC
CERQUAD
PLCC

2

~

2

PGA

I

t

I

CLCC

For information on military versions of these devices, contact your local 11 sales office .

Digital Signal Processing Applications with the TMS320 Family, Vol. 2

5

The additions to the first generation are the TMS320C14 and the TMS320E14; the latter is
identical with the former, except that the latter's on-chip program memory is EPROM. The
TMS320C141E14 devices have features that make them suitable for control applications. Figure
2 shows the components of these devices. The memory and the CPU are identical to those of the
TMS320C151E15, while the peripherals reflect the orientation of the devices toward control.

Figure 2. TMS320C14/E14 Key Features

16x16-bit
Multiply

32-bitALU

Watchdog Timer

32-bitACC
0,1 ,4-bit Shift

Timer/Counter 2

16 bit I/O

32-bit P-Reg

2 Auxiliary Registers

SERIAL PORT

4 level H/W Stack

Event Manager

Some of the key features of the TMS320C141E14 are:
• 160-ns instruction cycle time
• Object-code-compatible with the TMS320C15
• Four 16-bit timers
- Two general-purpose timers
- One watchdog timer
- One baud-rate generator
•
•
•
•

16 individual bit-selectable I/O pins
Serial port/USART with codec-compatible mode
Event manager with 6-channel PWM D/A
CMOS technology, 68-pin CERQUAD

The additions to the second generation are the TMS320E25, the TMS320C25-50, and the
TMS320C26. The TMS320E25 is identical to the TMS320C25, except that the 4K-word on-chip
6

Digital Signal Processing Applications with the TMS320 Family, Vol. 2

program memory is EPROM. Since increased speed is very important for the real-time implementation of certain applications, the TMS320C25-50 was designed as a faster version of the
TMS320C25 and has a clock frequency of 50 MHz instead of 40 MHz.
The TMS320C26 is a modification of the TMS320C25 in which the program ROM has been
exchanged for RAM. The memory space of the TMS320C26 has 1.SK words of on-chip RAM and
256 words of on-chip ROM, making it ideal for applications requiring larger RAM but minimal
external memory.
A new generation of higher-performance fixed-point processors has been introduced in the
TMS320 Family: the TMS320C5X devices. This generation shares many features with the first and
the second generations, but it also encompasses significant new features. Figure 3 shows the basic
components of the first device in the fifth generation, the TMS320C50.

Figure 3. TMS320C50 Key Features

Serial Port
Timer
S/WWaitsts
16x16
Inputs
16x16
Outputs

Some of the important features of the TMS320CSO are listed below:
• Source code is upward compatible with the TMS320Clx/C2x devices
• 50/3S-ns instruction cycle time
• 8K words of on-chip program/data RAM
• 2K words boot ROM
• 544 words of data/program RAM
• 128K words addressable total memory
• Enhanced general-purpose and DSP-specific instructions
• Static CMOS, 84-pin CERQUAD
• JTAG serial sClm path
Digital Signal Processing Applications with the TMS320 Family, Vol. 2

7

The software and hardware development tools available for the TMS320 family make the
development of applications easy. Such tools include assemblers, linkers, simulators, and C compilers for software and evaluation modules, software development boards, and extended development systems for hardware. These tools are mentioned in the following paper by Lin, et. a1. The
interested reader can find much more information in additional literature that is published by Texas
Instruments and mentioned in the next section. In partiCular, the TMS320 Family Development Support Reference Guide is an excellent source.
One important addition to the list of tools is the SPOX operating system, developed by Spectron Microsystems. SPOX permits you to write an application in a high-level language (C) and run
it on actual DSP hardware. The operating-system of SPOX hides the details of the interface from
you and lets you concentrate on your algorithm while running it at supercomputer speeds on the
TMS320C30.

References
Texas Instruments publishes an extensive bibliography to help designers use the TMS320 devices effectively. Besides user's guides for corresponding generations, there are manuals for the
software and the hardware tools. The Development Support Reference Guide is particularly useful
because it provides information not only on development tools offered by TI, but also on those produced by third parties. Here is a partial list of the literature available (the literature number is in
parentheses):
• TMS320 Family Development Support Reference Guide (SPRUOllA)
• TMS320Clx User's Guide (SPRU013A)
• TMS320C2x User's Guide (SPRU014)
• TMS320C3x User's Guide (SPRU031)
• TMS320ClxlTMS320C2xAssembly Language Tools User's Guide (SPRU018)
• TMS320C30 Assembly Language Tools User's Guide (SPRU035)
• TMS320C25 C Compiler Reference Guide (SPRU024)
• TMS320C30 C Compiler Reference Guide (SPRU034)
• Digital Signal Processing Applications with the TMS320 Family, Volume 1 (SPRA012)
• Digital Signal Processing Applications with the TMS320 Family, Volume 3 (SPRA017)
You can request this literature by calling the Customer Response Center at 1-800-232-3200,
or the DSP Hotline at 1-713-274-2320.

Contents of Other Volumes of the Application Book
Volume 1
Part I. Digital Signal Processing and the TMS320 Family
• Introduction
• The TMS320 Family
Part II. Fundamental Digital Signal Processing Operations
• Digital Signal Processing Routines

8

Digital Signal Processing Applications with the TMS320 Family, Vol. 2

- Implementation of FIR/lIR Filters with the TMS32010{fMS32020
- Implementation of Fast Fourier Transform Algorithms with the TMS32020
- Companding Routines for the TMS32010{fMS32020
- Floating-Point Arithmetic with the TMS32010
- Floating-Point Arithmetic with the TMS32020
- Precision Digital Sine-Wave Generation with the TMS32010
- Matrix Multiplication with the TMS32010 and TMS32020
• DSP Interface Techniques
- Interfacing to Asynchronous Inputs with the TMS32010
- Interfacing External Memory to the TMS32010
- Hardware Interfacing to the TMS32020
- TMS32020 and MC68000 Interface
Part III. Digital Signal Processing Applications
• Telecommunications
- Telecommunications Interfacing to the TMS32010
- Digital Voice Echo Canceller with a TMS32020
- Implementation of the Data Encryption Standard Using the TMS32010
- 32K-bit/s ADPCM with the TMS32010
- A Real-Time Speech Subband Coder Using the TMS32010
- Add DTMF Generation and Decoding to DSP-~P Designs
• Computers and Peripherals
• Speech Coding/Recognition
- A single-Processor LPC Vocoder
- The Design of an Adaptive Predictive Coder Using a Single-Chip
- Digital Signal Processor
- Firmware-Programmable C Aids Speech Recognition
• Image/Graphics
- A Graphics Implementation Using the TMS32020 and TMS34061
• Digital Control
- Control System Compensation and Implementation with the TMS32010

Volume 3
Part I. Introduction
• Book Overview
• The TMS320 Family of DSP
• The TMS320C30 Floating-Point DSP
Part II. Digital Signal Processing Routines
• Implementation of FFT, DCT, and other Transforms on the TMS320C30
• Doublelength Floating-Point Arithmetic on the TMS320C30
• An 8 x 8 Discrete Cosine Transform Implementation on the TMS320C25 and the
TMS320C30
• Implementation of Adaptive Filters with the TMS320C25 and TMS320C30
• A Collection of Functions for the TMS320C30
Digital Signal Processing Applications with the TMS320 Family, Vol. 2

9

Part III. DSP Interface Techniques
• Hardware Interfacing to the TMS320C30
• TMS320C30 - IEEE Floating-Point Format Converter
Part IV. Telecommunications
• Implementation of a CELP Speech Coder for the TMS320C30 Using SPOX
Part V. Computers
• A Digital Signal Processor Based 3-D Graphics System
Part VI. Tools
• TMS320C30 Applications Board Functional Description

10

Digital Signal Processing Applications with the TMS320 Family, Vol. 2

The TMS320 Family
of
Digital Signal Processors
Kun-Shan Lin
Gene A. Frantz
Ray Simar, Jr.
Digital Signal Processor Products - Semiconductor Group
Texas Instruments

Reprinted from
PROCEEDINGS OF THE IEEE
Vol. 75, No.9, September 1987

11

12

The TMS320 Family of Digital Signal Processors

The TMS320 Family of Digital Signal
Processors
KUN-SHAN LIN, MEMBER,
RAY SIMAR, JR.

IEEE,

GENE A. FRANTZ,

SENIOR MEMBER, IEEE,

AND

This paper begins with a discussion of the characteristics of digital signal processing, which are the driving force behind the design

of digital signal processors. The remainder of the paper describes
the three generations of the TMS320 family of digital signal processors available from Texas Instruments. The evolution in architec-

tural design of these processors and key features of each generation of processors are discussed. More detailed information ;5
provided for the TMS320C25 and TMS320C30, the newest members

in the family. The benefits and cost-performance tradeoffs of these
processors become obvious when applied to digital Signal processing applications, such as telecommunications, data commu·
nications, graphics/image processing, etc.
DIGITAL SIGNAL PROCESSING CHARACTERISTICS

Digital signal processing (DSP) encompasses a broad
spectrum of applications. Some application examples
include digital filtering, speech vocoding, image processing, fast Fourier transforms, and digital audio [1]-[10]. These
applications and those considered digital Signal processing
have several characteristics in common:

mathematically intensive algorithms,

Mathematically Intensive Algorithms

From (1), we can see that to generate every y(n), we have
to compute N multiplications and additions or sums of
products. This computation makes it mathematically intensive, especially when N is large.
At this point it is worthwhile to give the FIR filter some
physical significance. An FIR filter is a common technique
used to eliminate the erratic nature of stock market prices.
When the day-to-day closing prices are plotted, it is sometimes difficult to obtain thedesired information, such as the
trend of the stock, because of the large variations. A simple
way of smoothing the data is to calculate the average closing values of the previous five days. For the new average

value each day, the oldest value is dropped and the newest
value added. Each daily average value (average (n)) would
be the sum of the weighted value of the latest five days,
where the weighting factors (a(i)'s) are 1/5.ln equation form,
the average is determined by
average (n) = ! • dIn - 1) + ! • dIn S
S

real-time operation,

sampled data implementation,
system flexibility.

+

To illustrate these characteristics in this section, we will use
the digital filter as an example. Specifically, we will use the
Finite Impulse Response (FIR) filter which in the time
domain takes the general form of
N

y(n)

= :E

ali) • x(n - i)

(1)

i"'"

where yIn) is the output sample at time n, ali) is the ith coefficient orweighting factor, and x(n - i) is the (n - i)th input
sample.
With this example in mind, we can discuss the various
characteristics of digital signal processing: mathematically
intensive algorithms, real-time processing, sampled data
implementation, and system flexibility. First, let us look at
the concept of mathematically intensive algorithms.
Manuscript received October 6, 1986; revised March 27, 1987.
The authors are with the Semiconductor Group, Texas Instruments Inc., Houston, TX 77521-1445, USA.
IEEE Log Number 871&214.

!5 • dIn

- 3) +

+!'d(n-S)
S

!5 • dIn

2)

- 4)
(2)

where dIn - i) is the daily stock closing price for the (n i)th day. Equation (2) assumes the same form as (1). This is
also the general form of the convolution of two sequences
of numbers, ali) and xli) [5], [6]. Both FIR filtering and convolution are fundamental to digital signal processing.
Rea/-Time Processing

In addition to being mathematically intensive, DSP algorithms must be performed in real time. Real time can be
defined as a process that is accomplished by the DSP without creating a delay noticeabletothe user. In the stock market example, as long as the new average value can be computed prior to the next day when it is needed, it is considered
to be completed in real time. In digital signal processing
applications, processes happen fasterthan on adaily basis.
In the FIR filter example in (1), the sum of products must

©1989-IEEE. Reprinted, with pennission, from PROCEEDINGS OF THE IEEE; Vol. 75, No.9,
pp. 1143-1159; September 1989.

The TMS320 Family of Digital Signal Processors

13

be computed usually within hundreds of microseconds
before the next sample comes into the system. A second
example is in a speech recognition system where a noticeable delay between a word being spoken and being recognized would be unacceptable and not considered realtime; Another example is in image processing, where it is
considered real-time if the processor finishes the processing within the !rame update period. If the pixel information
cannot be updat~d within the frame update period, problems such as flicker, smearing, or missing information will
occur.
Sampled Data Implementation,

The application must be capable of being handled as a
sampled data system in order to be processed by digital
processors, such as digital Signal processors. The stock
market is an example of a sampled data system. That is, a
specific value (c!osing value) is assigned to each sample
period or day. Other periods may be chosen such as hourly
prices or weekly prices. In an FIR filter as shown in (1), the
output y(n) is calculated to be the weighted sum of the previous N inputs. In other words, the input signal is sampled
at periodic intervals (lover the sample rate), multiplied by
weighting factor a(i), and, then added together to give the
output result of y(n). Examples of sampie rates for some typical sampled data applications [2], [4] are shown in Table 1.
Table 1 Sample Rates versus Applications
Nominal

Application
Control

Sample Rate
1 kHz

Speech processing
Audio processing

8 kHz
8-10 kHz
40-48 kHz

Video frame rate
Video pixel rate

14 MHz

Telecommunications

30 Hz

In a typical DSP application, the processor-must be able
to effectively handle sampled data in large quantity and also
perform arithmetic computa'tions in realtime.
System Flexibility

The design of the digital Signal processing system must
be flexible enough to allow improvements in the state of
the art. We may find out after several weeks of using the
average stock price as a means of measuring a particular
stock's value that a different method of obtaining the daily
information is more suited to our needs, e.g., using different daily weightings, a different number of periods over
which to average, or a different procedure for calculating
the result. Enough flexibility'in the system must be available
to allow for these variations. In 'many of the DSP applications, techniques are still in the developmental phase, and
therefore the algorithms tend to change over time. As an
example, speech recognition is presently an inexact technique requiring continual algorithmic modification. From
this example we can see the need for system flexibility so
that the DSP algorithm can be updated. A programmable
DSP system can provide this flexibility to the user.

14

HISTORICAL DSP SOLUTIONS
Over the past several decades, digital signal processing
machines have taken on several evolutions in order to
incorporate these characteristics. large mainframe computers were initially used to process signals in the digital
domain. Typically, because of state-of-the-art limitations,
this was done in nonreal time. As the state of the art
advanced, array processors were added to the processing
task. Because of their flexibility and speed, array processors
have become the accepted solution for the research laboratory, and have been extended to end-applications in
many instances. However, integrated circuittechnology has
matured, thus allowing for the design of faster microprocessors and microcomputers. As a result, many digital signal processing applications have migrated from the array
processor to microprocessor subsystems (i.e., bit-slice
machines) to Single-chip integrated circuit solutions. This
migration has brought the cost of the DSP solution down
to a point that allows pervasive use of the technology. The
increased performance of these highly integrated circuits
has also expanded DSP applications from traditional telecommunications to graphics/image processing, then to
consumer audio processing.
A recent development in DSP technology is the singlechip digital signal processor, su~h as the TMS320 family of
processors. These processors give the designer a DSP solution with its performance attainable only by the array processors a few years ago. Fig. 1 shows the TMS320 family in
graphical form with the y-axis indicating the hypothetical
performance and the x-axis being the evolution of the semiconductor processing technology. The first member of the
family, the TMS32010, was disclosed to the market in 1982
[11], [12]. It gave the system deSigner the first microcomputer capable of performing five million DSP operations
per second (5 MIPS), including the add and multiply functions [13] required in (1). Today there are a dozen spinoffs
from the TMS32010 in th~ first generation of the TMS320
family. Some of these devices are the TMS320Cl0,
TMS320C15, and TMS320C17 [14]. The second generation
of devices include the TMS32020 [15] and TMS320C25 [16].
The TMS320C25 can perform 10 MIPS [16]. In addition,
expanded memory space, combined single-cycle multiplyl
accumulate operation, multiprocessing capabilities, and
expanded 110 functions have given the TMS320C25 a
2 to 4 times performance improvement over its predecessors. The third generation of the TMS320 family of processors, the TMS320C30 [26], [27], has a computational rate of
33 million DSP floating-point operations per second (33
MFlOPS). Its performance (speed, throughput, and precision) has far exceeded the digital Signal processors available today and has reached the level of a supercomputer.
It we look closely at the TMS320 family as shown in Fig.
1, we can see that devices in the same generation, such as
the TMS320Cl0, TMS320C15, and TMS320C17, are assembly
object-code compatible. Devices across generations, such
as the TMS320Cl0 and TMS320C25, are assembly sourcecode compatible. Software investment on DSP algorithms
therefore can be maintained during the system upgrade.
Another point is that since the introduction of the
TMS32010, semiconductor processing technology has
emerged from 3-l'm NMOS to 2-l'm CMOS'to I-I'm CMOS.

The TMS320 Family ofDigital Signal Processors

t------

2.4-l'm NMOS

2.0-l'm CMOS

Fig. 1. The TMS320 family of digital signal processors.

The TMS320 generations of processors have also taken the
same evolution in processing technology. Low power consumption, high performance, and high-density circuit integration are some of the direct benefits of this semiconductor processing evolution.
From Fig. 1, it can be observed that various DSP building
blocks, such as the CPU, RAM, ROM, 110 configurations,
and processor speeds, have been designed as individual
modules and can be rearranged or combined with other
standard cells to meet the needs of specific applications.
Each of the three generations (and future generations) will
evolve in the same manner. As applications become more
sophisticated, semicustom solutions based on the core CPU
will become the solution of choice. An example of this
approach is the TMS320C17/E17, which consists of the
TMS320C10 core CPU, expanded 4K-word program ROM
(TMS320C17) or EPROM (TMS320E17), enlarged data RAM
of 256 words, dual serial ports, companding hardware, and
a coprocessor interface. Furthermore, as integrated circuit
layout rules move into smaller geometry (now at 2 I'm, rapidly going to 1 I'm), not only will the TMS320 devices become
smaller in size, but also multiple CPUs will be incorporated
on the same device along with application-specific 1/0 to
achieve low-cost integrated system solutions.
BASIC TMS320 ARCHITECTURE
As noted previously, the underlying assumption regarding a digital signal processor is fast arithmetic operations
and high throughput to handle mathematically intensive
algorithms in real time. In the TMS320 family [11]-[17], [26],
[27], this is accomplished by using the following basic concepts:
Harvard architecture,
extensive pipelining,
dedicated hardware multiplier,
special DSP instructions,
fast instruction cycle.

The TMS320 Family of Digital Signal Processors

These concepts were designed inlO the TMS320 digital signal processors to handle the vast amount of data charac~
teristic of DSP operations, and to allow most DSP operations to be executed in a Single-cycle instruction.
Furthermore, the TMS320 processors are programmable
devices, providing the flexibility and ease of use of generalpurpose microprocessors. The following paragraphs discuss how each of the above concepts is used in Ihe TMS320
family of devices to make them useful in digital signal processing applications.

Harvard Architecture
The TMS320 utilizes a modified Harvard architecture for
speed and flexibility. In a strict Harvard architecture [18],
[19], the program and data memories lie in two separate
spaces, permitting a full overlap of instruction fetch and
execution. The TMS320 family's modification of the Harvard architecture further allows transfer between program
and data spaces, thereby increasing the flexibility of the
device. This architectural modification eliminates the need
for a separate coefficient ROM and also maximizes the processing power by maintaining two separate bus structures
(program and data) for full-speed execution.

Extensive Pipelining
In conjunction with the Harvard architecture, pipelining
is used extensively to reduce the instruction cycle time to
its absolute minimum, and to increase the throughput of
the processor. The pipeline can be anywhere from two to
four levels deep, depending on which processor in the family is used. The TMS320 family architecture uses a two-level
pipeline for its first generation, a three-level pipeline for its
second generation, and a four-level pipeline for its third
generation of processors. This means that the device is processing from two to four instructions in parallel, and each
instruction is at a different stage in its execution. Fig. 2 shows
an example of a three-level pipeline operation.

15

CLKOUT1
prefetch

decode
execute

N-2

..

N-l

Fig. 2. Three-level pipeline operation.

In pipeline operation, the prefetch, decode, and execute
operations can be handled independently, thus allowing
the execution of instructions to overlap. Duringany instruction cycle, three different instructions are active, each at a
different stage of completion. For example, as the Nth
instruction is being prefetched, the previous (N - 1)th
instruction is being decoded, and the previous (N - 2)th
instruction is being executed. In general, the pipeline is
transparent to the user.

(the closing price five days ago) was dropped and a new one
(today's closing price) was added. Or, each piece of the old
data is delayed or moved one sample period to make room
for the incoming most current sample. This delay is the
function olthe DMOV instruction. Another special instruction in the TMS32010 is the LTD instruction. It executes the
LT, DMOV, and APAC instructions in a single cycle. The LTD
and MPY instruction then reduce the number of instruction
cycles per FIR filter tap from four to two. In the second-generation TMS320, such as the TMS320C25, two more special
instructions have been included (the RPT and MACD
instructions) to reduce the number of cycles per tap to one,
as shown in the follOWing:
RPTK 255

;REPEAT THE NEXT INSTRUCTION 256 TIMES

MACD

;LT, DMOV, MPY, AND APAC

(N

+

1)

Dedicated Hardware Multiplier

Fast Instruction Cycle

As we saw in the general form of an FIR filter, multipli,cation is an important part of digital signal processing. For
each filter tap (denoted by i), a multiplication and an addition must take place. The faster a multiplication can be performed, the higher the performance of the digital signal
processor. In general-purpose microprocessors, the multiplication instruction is constructed by a series of additions, ther')fore taking many instruction cycles. In comparison, tA..bit words of on-chip program ROM and 544 16-bit
words of on·chip data RAM. The RAM is divided into three
separate Blocks (BO, B1, and B2). Ofthe544words, 256words
(block BO) are configurable as either data or program memo
ory by CNFD (configure data memory) or CNFP (configure
program memory) instructions provided for that purpose;
288 words (blocks B1 and B2) are always data memory. A
data memory size of 544 words allows the TMS320C25 to
handle a data array of 512 words while still leaving 32 loca·
tions for intermediate storage. The TMS320C25 provides
64K words of off-chip directly addressable data memory
space as well as a 64K-word off-chip program memory space.
A register file containing eight Auxiliary Registers (AROAR7), which are used for indirect addressing of data memory and for temporary storage, increase the flexibility and
efficiency of the device. These registers may be either
directly addressed by an instruction or indirectly addressed
by a 3·bit Auxiliary Register Pointer (ARP). The auxiliary regIsters and the ARP may be loaded from either data memory
or by an immediate operand defined in the instruction. The
contents of these registers may also be stored into data
memory. The auxiliary register file is connected to the Auxiliary Register Arithmetic Unit (ARAU). Using the ARAU
accessing tables of information does not require the CALU
for address manipulation, thus freeing it for other operations.
Central Arithmetic Logic Unit (CALU): The CALU contains
a 1f>..bit scaling shifter, a 16 x 1f>..bit parallel multiplier, a 32bit Arithmetic Logic Unit (AW), and a 32-bit accumulator.
The scaling shifter has a 1f>..bit input connected to the data
bus and a 32-bit output connected to the ALU. This shifter
produces a left-shift of 0 to 16 bits on the input data, as programmed in the instruction. Additional shifters at the outputs of both the accumulator and the multiplier are suitable
for numerical scaling, bit extraction, extended-precision
arithmetic, and overflow prevention.
The following steps occur in the implementation of a typo
ical ALU instruction:
1) Data are fetched from the RAM on the data bus.
2) Data are passed through the scaling shifter and the
ALU where the arithmetic is performed.
3) The result is moved into the accumulator.
The 32-bit accumulator is split into two 1f>..bit segments
for storage in data memory: ACCH (accumulator high) and
ACCL (accumulator low). The accumulator has a carry bit
to facilitate multiple-precision arithmetic for both addition
and subtract instructions.
Hardware Multiplier: The TMS320C25 utilizes a 16 x 1f>..
bit hardware multiplier, which is capable of computing a
32-bit product during every machine cycle. Two registers
are associated with the multiplier:
a 1f>..bit Temporary Register (TR) that holds one of the
operands for the multiplier, and
a 32-bit Product Register (PR) that holds the product.

The TMS;J20 Family of Digital Signal Processors

The output of the product register can be left-shifted 1 or
4 bits. This is useful for implementing fractional arithmetic
or justifying fractional prpducts. The output of the PR can
also be right-shifted 6 bits to enable the execution of up to
128 consecutive multiple/accumulates without overflow.
An unSigned multiply (MPYU) instruction facilitates
extended-precision multiplication.
I/O Interface: The TMS320C25 110 space consists of 16
input and 16 output ports. These ports provide the full 1f>..
bit parallel 110 interface via the data bus on tne device. A
single input (I N) or output (0 un operation typically takes
two cycles; however, when used with the repeat counter,
the operation becomes single-cycle. 110 devices are mapped
into the I/O address space using the processor's external
address and data buses in the same manner as memorymapped devices. Interfacing to memory and 110 devices of
varying speeds is accomplished by using the READY line.
A Direct Memory Access (DMA) to external program/data
memory is also supported. Another processor can take
complete control of the TMS320C25's external memory by
asserting HOLD low, causing the TMS320C25 to place its
address, data, and control lines in the high-impedance state.
Signaling between tne external processor and the
TMS320C25 can be performed using interrupts. Two modes
of DMA are available on the device. In the first, execution
is suspended during assertion of HOLD. In the second
"concurrent DMA" mode, the TMS320C25 continues to
execute its program while operating from internal RAM or
ROM, thus greatly increasing throughput in data-intensive
applications.
TMS320C2S Software

The majorityol the TMS320C25 instructions (97 out of 133)
are executed in a single instruction cycle. Of the 36 instructions that require additional cycles of execution, 21 involve
branches, calls, and returns that result in a reload of the
program counter and a break in the execution pipeline.
'Another seven of the instructions are two-word, longimmediate instructions. The remaining eight instructions
support I/O, transfers of data between memory spaces, or
provide for additional parallel operation in the processor.
Furthermore, these eight instructions (IN, OUT, BLKD,
8LKP, TBLR, TBLW, MAC, and MACD) become single-cycle
when used in conjunction with the repeat counter. The
functional performance of the instructions explOits the parallelism of the processor, allowing complex and/or numerically intensive computations to be implemented in relativeiy few instructions.
AddreSSing Modes: Since most of the instructions are
coded in a single 1f>..bit word, most instructions can be executed in a single cycle. Three memory addressing modes
are available with the instruction set: direct, indirect, and
immediate addreSSing. Both direct and indirect addreSSing
are used to access data memory. Immediate addressing uses
the contents of the memory addressed by the program
counter.
When using direct addressing, 7 bits of the instruction
word are concatenated with the 9 bits of the data memory
page pointer (DP) to form the 1f>..bit data memory address.
With a 128-word page length, the DP register points to one
of 512 possible data memory pages to obtain a 64K total data
memory space. Indirect addressing is provided by the aux-

21

iliary registers (ARO-AR7). The seven types of indirect
addressing are shown in Table 4. Bit-reversed indexed
addressing modes allow efficient 110 to be performed for
the resequencing of data points in a radix-2 FFT program.

icated to distinct sections of the algorithm, throughput can
be increased via pipelined execution. The TMS320C25 is
capable of allocatjng up to 32K words of data memory as
global memory for multiprocessing applications.
.

Table 4 Addressing Modes of the TMS320C25

THE THIRD GENERATION

Addressing Mode

Operation

OPA
OP' (,NARP)
OP '+(.NARP)
OP ,-(,NARP)
OP 'O+(,NARP)
OP 'O-(,NARP)

direct addressing
indirect; no change to AR.

OP 'BRO+(.NARP)

indirect; ARO is added to current AR
(with reverse carry propagation).
indirect; ARO is subtracted from
current AR (with reverse carry

indirect; current AR is incremented.

indirect; current AR is decremented.
indirect; ARO is added to current AR.
indirect; ARO is subtracted from
current AR.

OP

'BRO~(.NARP)

propagation).
Note: The optional NARP field specifies a new value of the ARP.

TMS32OC25 System Configurations

The flexibility of the TMS320C25 allows systems configurations to satisfy a wide range of application requirements
[16). The TMS320C25 can be used in the following configurations:

a stand-alone system (a single processor using 4K
words of on-chip ROM and 544words of on -chip RAM),
parallel multiprocessing systems with shared global
data memory, or
host/peripheral coprocessing using interface control
Signals.
A minimal processing system is shown in Fig. 6 using
external data RAM and PROM/EPROM. Parallel multiprocessing and host/peripheral coprocessing systems can be
designed by taking advantage of the TMS320C25's direct
memory access and global memory configuration capabilities.
In some digital processing tasks, the algorithm being
implemented can be divided into sections with a distinct
processor dedicated to each section. In this case, the first
and second processors may share global data memory, as
well as the second and third, the third and fourth, etc. Arbitration logic ';'ay be reqUired to determine which section
of the algorithm is executing and which processor has
accesstotheglobal memory. With multiple processors ded-

Of

THE TMS320 FAMllV

The TMS320C30 [26)-[27) is Texas Instruments third-generation member of the TMS320 family of compatible digital
signal processors. With a computatiomil rate of 33 MFLOPS
(million floating-point operations per second), the
TMS320C30 far exceeds the performance of any programmable DSP available today. Total system 'performance has
been maximized through internal parallelism, more than
twenty-fourthousand bytes of on-chip memory, single