1990_TI_Programmable_Logic_Data_Book 1990 TI Programmable Logic Data Book
User Manual: 1990_TI_Programmable_Logic_Data_Book
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-1.!1 TEXAS
INSTRUMENTS
Progratntnable Logic
1990
1990
General Information
~_D_a_ta__S_h_ee_t_s___________________f.~
~_A_P_P_li_c_at_io_n__R_e_p_o_rt_s____________~F_lII
~_D_e_v_e_lo_p_m_e_n_t_s_y_s_t_e_m_s__________-,!_~•
~_M_e_c_h_a_n_ic_a_I_D_a_t_a________________b~
The Programmable Logic
Data Book
TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant information to verify, before placing orders,
that the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. ,Unless mandated by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability for TI applications assistance, customer product
design, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or
relating to any combination, machine, or process in which such
semiconductor products or services might be or are used.
Copyright © 1990, Texas Instruments Incorporated
INTRODUCTION
In this data book, Texas Instruments (TI) presents technical information on TI's broad line of programmable
logic devices (PLDs), including the high-speed 5-ns PAL® circuits and high-density, low-power, Erasable
Programmable Logic Devices (EPLDs). More than 40 PLD functions in industry standard architectures are
available from Texas Instruments. For high-performance applications, TI also offers several high-speed
programmable state machine devices. Where low power and reprogrammability are key considerations,
TI offers its family of EPLDs. This data book includes specifications on existing and future products including:
• High-performance, low-power IMPACT'" and IMPACT-X'" 20- and 24-pin standard
PAL ® circuits including Tl's new 5-ns device
• Tl's high-speed 6-ns programmable address decoder, TIBPAD18N8-6
Flexible, '22V10-architecture macrocell PAL® ICs including TI's enhanced version, the
TIBPAL22VP10
• Fast, 50-MHz programmable state machines, including enhanced versions of the
'82S 105B/167B and TI's complex TIBPLS506
• The TIBPSG507, programmable sequence generator with internal 6-bit counter and 50-MHz
performance
• Higher speed versions of the industry standard EPLD architectures including the 20-ns EP630.
Texas Instruments high-speed programmable bipolar devices utilize TI's advanced IMPACT'" and new
IMPACT-X'" technologies. IMPACT-X'" uses trench isolation and polysilicon emitters to increase performance
and reduce power dissipation compared to traditional processes. For EPLDs, TI utilizes its 1.0 micron highvoltage EPIC'" CMOS technology to combine the benefits of low power and higher speed.
This volume contains design and specification data for 183 device types. Package dimensions are given
in the Mechanical Data section in metric measurement (and parenthetically in inches). In some cases,
package dimensions are included in the actual data sheet.
Several programmable logic application reports have been incorporated into this book to aid in the design
of TI PLDs. User notes also explain considerations for programming and testing of PLDs in a manufacturing
environment.
Complete technical data for any Texas Instrument semiconductor product is available from your nearest
TI field sales office, local authorized TI distributor, or by calling Texas Instruments at 1-800-232-3200.
PAL is a registered trademark of Monolithic Memories Inc.
IMPACT. IMPACT·X, and EPIC are trademarks of Texas Instruments Incorporated.
v
-
vi
General Information
1-1
Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Explanation of Function Tables ................................
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware/Software Manufacturers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIIMPACT'M Design Centers ........................... . . . . . . .
1-2
Page
1-3
1-5
1-10
1-11
1-12
1-13
ALPHANUMERIC INDEX
Page
Page
EP330-15C
EP330-251 .......
EP330-25M .....
2-3
2-3
EPB10DC-25 .. . . . . . , ' . . . . . . , '
..
2-15
EPB10DC-30 . . . . . . . , .
..
2-15
EPB10DC-35
EPB10DI-40 ......
2-15
2-15
EP610JC-25
....................
2-15
EP610JC-30 ..............
2-15
EPB10JI-40 .....
EPB10JC-35
.................
2-15
EPB10lC-25.
EPBl OlC-30 ...
2-15
EPB10lC-35
EPB10Ll-40 ..
2-15
EPB10PC-25 . '" . . . . . . " . . . . . . . .
2-15
EP610PC-30
.. , . . . . . . . . . . . . . . . . .
2-15
2-15
EPB10PI-40 ..
EPB10PC-35
EPB30-20C
EP630-251 ....
2-33
EP630-25M ..
2-33
2-47
EP910DC-30 . . . . . . . , . ... .... .. ,
EP910DC-35
2-47
2-47
EP910DI-45 ..
EP910DC-40
EP910JC-30
2-47
... , ' " ....
2-47
EP910JC-35
EP910JC-40
EP910JI-45
2-47
2-47
EP91 OlC-30 .
2-47
EP910lC-35 ....
EP910Ll-45
2-47
EP910lC-40
EP910PC-30
2-47
EP910PC-35
2-47
EP910PC-40
EP910PI-45
2-47
EP1Bl0JC-35 . . . . . . . . . . . . . .
2-65
EP1Bl0JC-45
EP1Bl0JI-45
2-B5
2-B5
EP1Bl0lC-35 ...
EP1Bl0lC-45
2-B5
EP1Bl0Ll-45
PAl16lBAM
2-B7
PAL lBlBA-2M ....
2-B7
PAL1BR4AM
2-B7
PAL 16R4A-2M ..
2-B7
PAl16RBAM ...
2-B7
PAllBRBA-2M ..
2-B7
PAllBRBAM
2-B7
2-87
PAllBRBA-2M ..
TIBPAD1BNB-7C . . . . . . . . . . . . . . . . . . .
2-99
2-107
TIBPAD1BNB-BC . . . . . . . . . . . . . . . . . . . . .
TIBPAllBlB-7M ......... 2-115
TIBPAllBlB-5C
TIBPAL1BlB-7C
2-131
TIBPAllBlB-l0M ...
TIBPAL16I.,B-l0C
TIBPAl 16lB-12M .....
2-149
TIBPAl16lB-12C
TIBPAllBlB-15M .....
2-1B7
TIBPAllBlB-15C
TIBPAl 1 BlB-20M .....
2-1Bl
TIBPAllBlB-25C
TIBPAl 1 BlB-30M .
2-195
TIBPAllBR4-7M ..
2-115
TIBPAllBR4-5C
TIBPAL1BR4-7C
TIBPAllBR4-10M
2-131
TIBPAL16R4-10C
TIBPAllBR4-12M
2-149
TIBPAL1BR4-12C
TIBPAllBR4-15M
2-1B7
",
",
TIBPAl16R4-15C
TIBPAl16R4-20M
TIBPAllBR4-25C
TIBPAllBR4-30M
TIBPAllBRB-5C
TIBPAllBRB-7M
TIBPAllBRB-7C
TIBPAL1BRB-l0M
TIBPAl lBRB-l OC
TlBPAllBRB-12M
TlBPAllBR6-12C
TlBPAl16RB-15M
TIBPAl 16R6-1 5C
TlBPAl16R6-20M
TIBPAl16R6-25C
TlBPAl16RB-30M
TIBPAllBRB-5C
TlBPAL1BRB-7M .. ' ...
TIBPAllBRB-7C
TIBPAl16RB-l0M
TIBPAllBRB-l0C
TlBPAL1BRB-12M
TIBPAL lBRB-12C
TIBPAL1BRB-15M
TIBPAl lBRB-l 5C
TIBPAllBRB-20M
TlBPAllBRB-25C
TlBPAllBRB-30M
TIBPAl20lB-5C
TIBPAl20lB-7M ...
TlBPAl20lB-7C
TlBPAl20lB-l0M .
TlBPAl20lB-l0C
TIBPAl20lB-12M .
TIBPAl20lB-15C
TIBPAl20lB-20M .
TIBPAl20lB-25C ..
............
TIBPAL20l8-15CNl
TIBPAl20lB-25CNl
................
TlBPAl20R4-7M ...
TIBPAl20R4-5C
TlBPAl20R4-7C
TlBPAl20R4-10M
TlBPAl20R4-10C
TlBPAl20R4-12M
TIBPAl20R4-15C
TlBPAl20R4-20M
TIBPAl20R4-25C .....
. . . . . ... . ..
TlBPAl20R4-15CNl ....
TlBPAl20R4-25CNl .
TlBPAl20RB-7M
TlBPAl20RB-5C
TlBPAl20RB-l0M
TlBPAl20RB-7C
TIBPAl20RB-l0C
TlBPAl20RB-12M
TIBPAl20R6-15C
TIBPAl20RB-20M
TIBPAl20RB-25C .
TIBPAl20RB-15CNl .
TIBPAl20RB-25CNl .
TIBPAL20RB-5C
TlBPAl20RB-7M
TIBPAl20RB-7C
TlBPAl20RB-l0M
TlBPAl20RB-12M
TIBPAl20RB-l0C
TIBPAl20RB-15C
TIBPAl20R6-20M
TIBPAl20RB-25C .
TIBPAl20RB-15CNl ..
TIBPAl20RB-25CNl .
TIBPAl22Vl0C
TIBPAl22Vl0-15C
TIBPAl22Vl0-20M
TIBPAl22Vl0AM.
TIBPAl22Vl0AC
TIBPAl22VP10-20C
TIBPAI.,22VP10-25M
TIBPAlR19lBC
TIBPAlR19R4C
TIBPAlR19R6C
TIBPAlR19RBC
TIBPAl T19lBC.
TIBPAlT19R4C
TEXAS ."
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POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
,'
2-1Bl
2-195
2-115
2-131
2-149
2-1B7
2-1Bl
2-195
2-115
2-131
2-149
2-1B7
2-1Bl
2-195
2-209
2-225
2-243
2-2Bl
2-275
2-2B7
2-2B7
2-209
2-225
2-243
2-2Bl
2-275
2-2B7
2-2B7
2-209
2-225
2-243
2-261
2-275
2-2B7
2-287
2-209
2-225
2-243
2-261
2-275
2-2B7
2-2B7
2-299
2-311
2-299
2-325
2-337
2-337
2-337
2-337
2-349
2-349
1-3
ALPHANUMERIC INDEX
Page
1-4
Page
TIBPALT19R6C ............................ 2-349
TICPAL22Vl0Z-35C. . . . . . . . . . . . . . . . . . . . . . . ..
2-429
TIBPALT19RSC ............................ 2-349
TIEPAL 1OH 16ET6C .........................
2-445
TIBPLS506C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-361
TIEPAL10H16PS-3C .........................
2-451
TIBPSG507C
TIBPSG507M . . . . . . . . . ..
2-375
TIEPAL10H16PS-6C ......................... 2-457
TIBS2S 105BC
TIBS2S105BM ..........
2-391
TIEPAL10H16TE6C ......................... 2-463
TIBS2S167BC
TIB82S167BM ..........
2-403
TIEPAL 10016ET6C. . . . . . . . . . . . . . . . . . . . . . . . ..
2-469
TICPAL16LS-55C ........................... 2-415
TICPA116R4-55C . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-415
TIEPAL10016PS-3C ......................... 2-475
TIEPAL 10016TE6C. . . . . . . . . . . . . . . . . . . . . . . . .. 2-4S1
TICPAL 16R6-55C . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-415
TIFPLAS39C
TICPAL 16RS-55C . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-415
TIFPLAS40C .............................. 2-4S7
TICPAL22Vl0Z-25C. . . . . . . . . . . . . . . . . . . . . . . ..
2-429
TEXAS . "
INSTRUMENTS
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2-4S7
GLOSSARY
INTRODUCTION
These symbols. terms. and definitions are in accordance with those currently agreed upon by the JEDEC Council
of the Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical
Commission (lEC) for international use.
PART 1 - GENERAL CONCEPTS AND CLASSIFICATIONS OF CIRCUIT COMPLEXITY
Chip-Enable Input
A control input that when active permits operation of the integrated circuit for input. internal transfer.
manipulation. refreshing. and/or output of data and when inactive causes the integrated circuit to be in
reduced-power standby mode.
NOTE: See "chip-select input."
Chip-Select Input
A gating input that when inactive prevents input or output of data to or from an integrated circuit.
NOTE: See "chip-select input."
Field-Programmable Logic Array (FPLA)
A user-programmable integrated circuit whose basic logic structure consists of a programmable AND array
and whose outputs feed a programmable OR array.
Gate Equivalent Circuit
A basic unit-of-measure of relative digital-circuit complexity. The number of gate equivalent circuits is that
number of individual logic gates that would have to be interconnected to perform the same function.
Large-Scale Integration (LSI)
A concept whereby a complete major subsystem or system function is fabricated as a single microcircuit.
In this context. a major sybsystem or system. whether digital or linear. is considered to be one that contains
100 or more equivalent gates or circuitry of similar complexity.
Medium-Scale Integration (MSI)
A concept whereby a complete subsystem or system function is fabricated as a single microcircuit. The
subsystem or system is smaller than for LSI. but whether digital or linear. is considered to be one that
contains 12 or more equivalent gates or circuitry of similar complexity.
Memory Cell
The smallest subdivision of a memory into which a unit of data has been or can be entered. in which it
is or can be stored. and from which it can be retrieved.
Memory Integrated Circuit
An integrated circuit consisting of memory cells and usually including associated circuits such as those
for address selection. amplifiers. etc.
Output-Enable Input
A gating input that when active permits the integrated circuit to output data and when inactive causes
the integrated circuit output(s) to be at a high impedance (off).
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1-5
GLOSSARY
Output-Enable Input
A gating input that when active permits the integrated circuit to output data and when inactive causes
the integrated circuit output(s) to be at a high impedance (off).
Programmable Array logic (PAl®)
A user-programmable integrated circuit which utilizes proven fuse link technology to implement logic
functions. Implements sum of products logic by using a programmable AND array whose outputs feed
a fixed OR array.
.
Read/Write Memory
A memory in which each cell may be selected by applying appropriate electronic input signals and the
stored data may be either (a) sensed at appropriate output terminals, or (b) changed in respons'e to other
similar electronic input signals.
Small-Scale Integration (SSI)
Integrated circuits of less complexity than medium-scale integration (MSI)
Typical (TVP)
A calculated value representative of the specified parameter at nominal operating conditions (Vee = 5 V,
T A = 25 o e), based on the measured value of devices processed, to emulate the process distribution.
Very-large-Scale Integration (VlSI)
a
A concept whereby a complete system function is fabricated as single microcircuit, In this context, a
system, whether digital or linear, is considered to be one that contains 3000 or more gates or Circuitry
of similar complexity.
PAL is a registered trademark of Monolithic Memories Inc.
'-6
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GLOSSARY
PART 2 -
OPERATING CONDITIONS AND CHARACTERISTICS (IN SEQUENCE BY lETTER SYMBOLS)
f max
Maximum clock frequency
The highest rate at which the clock input of a bistable circuit can be driven through its required
sequence while maintaining stable transitions of logic level at the output with input conditions
established that should cause changes of output logic level in accordance with the specification.
ICC
Supply current
The current into' the
Vee
supply terminal of an integrated circuit.
ICCH
Supply current, outputs high
The current into' the Vee supply terminal of an integrated circuit when all (or a specified number)
of the outputs are at the high level.
ICCl
Supply current, outputs low
The current into' the Vee supply terminal of an integrated circuit when all (or a specified number)
of the outputs are at the low level.
IIH
High-level input current
The current into' an input when a high-level voltage is applied to that input.
III
low-level input current
The current into' an input when a low-level voltage is applied to that input.
10H
High-level output current
The current into' an output with input conditions applied that, according to the product
specification. will establish a high level at the output.
10l
low-level output current·
The current into * an output with input conditions applied that. according to the product
specification. will establish a low level at the output.
lOS flO)
Short-circuit output current
The current into' an output when that output is short-circuited to ground (or other specified
potential) with input conditions applied to establish the output logic level farthest from ground
potential (or other specified potential).
10ZH
Off-state (high-impedance-state) output current (of a three-state output) with high-level voltage
applied
The current flowing into' an output having three-state capability with input conditions established
that. according to the production specification. will establish the high-impedance state at the output
and with a high-level voltage applied to the output.
NOTE: This parameter is measured with other input conditions established that would cause the
output to be at a low level if it were enabled.
10Zl
Off-state (high-impedance-statel output current (of a three-state output) with low-level voltage
applied
.
The current flowing into' an output having three-state capability with input conditions established
that. according to the product speCification. will establish the high-impedance state at the output
and with a low-level voltage applied to the output.
NOTE: This parameter is measured with other input conditions established that would cause the
output to be at a high level if it were enabled.
*Current out of a terminal is given as a negative value.
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1-7
GLOSSARY
VIH
High-level input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to
represent the binary variables.
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which
operation of the logic element within specification limits is guaranteed.
VIK
Input clamp voltage
An input voltage in a region of relatively low differential resistance that serves to limit the input voltage
swing.
VIL
Low-level input voltage
An input voltage level within the less positive (more negative) of the two ranges of values used to
represent the binary variables.
NOTE: A minimum is specified that is the most-positive value of low-level input voltage for which
operation of the logic element within specification limits is guaranteed.
VOH
High-level output voltage
The voltage at an output terminal with input conditions applied that, according to the product
specification, will establish a high level at the output.
VOL
Low-level output voltage
The voltage at an output terminal with input conditions applied that, according to the product
specification, will establish a low level at the output.
ta
Access time
The time interval between the application of a specific input pulse and the availability of valid signals
at an output.
tdis
Disable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms,
with the three-state output changing from either of the defined active levels (high or low) to a highimpedance (off) state. (tdis = tPHZ or tPLZ).
ten
Enable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms,
with the three-state output changing from a high-impedance (off) state to either of the defined active
levels (high or low). (ten = tpZH or tpzU.
th
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal.
NOTES: 1 . The hold time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the
shortest interval for which correct operation of the digital circuit is guaranteed.
2 . The hold time may have a negative value in which case the minimum limit defines the longest
interval (between the release of the signal and the active transition) for which correct
operation of the digital circuit is guaranteed.
tpd
1-8
Propagation delay time
The time between the specified reference points on the input and output voltage waveforms with
the output changing from one defined level (high or low) to the other defined level. (tpd = tPHL or
tPLH)·
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GLOSSARY
tpHL
Propagation delav time. high-to-Iow level output
The time between the specified reference points on the input and output voltage waveforms with
the output changing from the defined high level to the defined low level.
tPHZ
Disable time (of a three-state output) from high level
The time interval between the specified reference points on the input and the output voltage waveforms
with the three-state output changing from the defined high level to a high-impedance (off) state.
tPLH
Propagation delav time. low-to-high-Ievel output
The time between the specified reference points on the input and output voltage waveforms with
the output changing from the defined low level to the defined high level.
tpLZ
Disable time (of a three-state output) from low level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from the defined low level to a high-impedance (off) state.
tpZH
Enable time (of a three-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from a high-impedance (off) state to the defined high level.
tPZL
Enable time (of a three-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms
with the three-state output changing from a high-impedance (off) state to the defined low level.
tsu
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent
active transition at another specified input terminal.
NOTES: 1 . The setup time is the actual time interval between two signal events and is determined
bV the system in which the digital circuit operates. A minimum value is specified that is
the shortest interval for which correct operation of the digital circuit is guaranteed.
2 . The setup time may have a negative value in which case the minimum limit defines the
longest interval (between the active transition and the application of the other signal) for
which correct operation of the digital circuit is guaranteed.
tw
Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the pulse
waveform.
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1-9
EXPLANATION OF FUNCTION TABLES
The following symbols are used in function tables on TI data sheets.
H
high level (steady state)
L
low level (steady state)
i
transition from low to high level
t
transition from high to low level
value/level or resulting value/level is routed to indicated destination
~
value/level is reentered
X
irrelevant (any input, including transitions)
Z
off (high impedance) state of a 3-state output
a ... h
the level of steady-state inputs A through H respectively
QO
the level of Q before the indicated steady-state input conditions were established
00
complement of QO or level of
established
Qn
JL
1.....[
TOGGLE
0
before the indicated steady-state input conditions were
level of Q before the most recent active transition indicated by t or i
one high-level pulse
one low-level pulse
each output chahges to the complement of its previous level on each transition indicated by
t or i.
If, in the input columns, a row ,contains only the symbols H, L, and/or X, this means the indicated output is
valid whenever the input configuration is achieved and regardless of the sequence in which it is achieved. The
output persists so long as the input configuration is maintained.
If, in the input columns, a row contains H, L, and/or X together with i and/or t, this means the output is valid
whenever the input configuration is achieved but the transition(s) must occur following the achievement of
the steady-state levels. If the output is shown as a level (H, L, QO, or 00), it persists so long as the steady-state
input levels and the levels that terminate indicated transitions are maintained. Unless otherwise indicated, input
transitions in the opposite direction to those shown have no effect at the output. (If the output is shown as
a pulse,
SL or l..S ,the pulse follows the indicated input transition and persists for an interval
dependent on the circuit.)
1-10
TEXAS . "
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ORDERING INFORMATION
PAL@ NUMBERING SYSTEM AND ORDERING INSTRUCTIONS
Factory orders for leadership PAL® circuits described in this catalog should include a nine-part type number
as explained in the example below. Exclude the prefix when ordering standard PALs.
EXAMPLE:
TIB
16
PAL
R
8
-15
C
N
prefix------------'/
TIB
TIC
TIE
= Bipolar PAL
= CMOS PAL
= ECl PAL
Product Family Designator --_..../
Input Register Type - - - - - - - - - - "
No Designator::::: No Input Register
A
=
D-Type Aegister
T : : : Transparent Latch Register
Number of Array Inputs _ _ _ _ _ _ _ _. J
Output Configuration Designator _ _ _ _ _ _ _ _ _J
R ::::: Registered
L ::::: Active Low
X ::::: Exclusive-OR
Number of Outputs in the
Designated Configuration - - - - - - - - - - - - '
Performance Designator - - - - - - - - - - - - - - - '
HIGH SPEED
LOW-POWER
A
-7
A·2
-25
Temperature Range - - - - - - - - - - - - - - - - - - '
C = Commerical (O°C to 70°C)
M
=
Military (- 55°C to 125 eCI
PackageType-----------------------~
N
=
20-Pin Plastic DIP
= 20-Pin Ceramic DIP
= 24-Pin.
= 24·Pin,
JW = 24-Pin,
NW = 24-Pin,
NT
JT
300·mil Plastic DIP
3pO-mil Ceramic Dip
BOO-mil Ceramic DIP
BOO-mil Plastic DIP
FN = Plastic Chip Carrier
FK = Ceramic Chip Carrier
W
=
Ceramic Flat Pack
PAL is a registered trademark of Monolithic Memories Inc.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • I)ALLAS, TEXAS 75265
1-11
HARDWARE/SOFTWARE MANUFACTURERS
ADDRESSES FOR PAL® AND FPLA PROGRAMMING AND SOFTWARE MANUFACTURERSt
adams-macDonald enterprises, Inc.
800 Airport Road
Monterey, CA 93940
(408) 373-3607
LOGICAL DEVICES INC. (CUPL Design Software)
1201 N.W. 65th Place
Ft. Lauderdale, FL 33309
(305) 974-0967
(800) 331-7766
ADVIN SYSTEMS INC.
1050-L East Duane Ave.
Sunnyvale, CA 94086
(408) 984-8600
MINC Incorporated (PLDesigner Software)
1575 York Road
Colorado Springs, CO 80918
(719) 590-1155
ANVIL SOFTWARE
427-3 Amherst St.
Suite 341
Nassua, NH 03063
(617) 641-3861
Micropross
Parc d' acivite des Pres
5, rue Denis Papin
59650 VILLENEUVE D'ASCQ;
FRANCE
(20) 47.90.40
Bytek Corporation
508 Northwest 77th St.
Boca Raton, FL 33487
(407) 994-3520
STAG MICRO SYSTEMS
1600 Wyatt Drive
Santa Clara, CA 95054
(800) 227-8836
BP MICROSYSTEMS
10681 Haddington,
Suite # 190
Houston, TX 77043
(713) 461-9430
System-General Corp.
3FI., No.6, Lane 4,
Tun Hwa N. Rd.,
P.O. Box: 53-591
Taipei, Taiwan, R.O.C.
886-2-9173005
886-2-9111283 FAX
DATA I/O (ABEL Design Software)
10525 Willows Road, N.E.
Redmond, WA 98073-9746
(800) 247-5700
INLAB INC. (proLogic Design Software)
2150-1 West 6th Ave.
Broomfield, CO 80020
(303) 460-0103
(800) 237-6759
System-General America
510 South Paric Victoria
Malpitas, CA 93035
(408) 263-6667
(408) 262-9220 FAX
tTexas Instruments does not endorse or warrant the suppliers referenced. Presently, Texas Instruments has certified DATA 1/0, Sunrise,
Structured Design and Digital Media. Other programmers are now in the certification process. For a current list of certified programmers,
please contact your local TI sales representative.
I
1-12
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DA;LlAS, TEXAS 75265
TI IMPACT™DESIGN AND SERVICE CENTERS
Design and programming assistance is offered by Texas Instruments IMPACT" Design and Service Centers.
The centers are equipped with the latest in software and hardware tools for design, debugging, prototyping,
and production on a local basis. Supported by a professional engineering staff, the centers provide complete
code development, device programming, symbolization, functional and DC parametric testing.
NORTHERN CALIFORNIA
BOSTON
MARSHALL IMPACT CENTER
336 Los Coches Street
Milpitas, CA 95035
(408) 942-4600
HALL-MARK IMPACT CENTER
6 Cook Street
Pinehurst Park
Billerica, MA 01821
(617) 935-9777
IMPACT is a trademark of Texas Instruments Incorporated.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-13
-
1-14
Data Sheets
2-1
-
2-2
EP330
HIGH·PERFORMANCE 8·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE IEPLD\
OCT~8ER 19B~
J OR N PACKAGE
• Programmable Replacement for
Conventional TTL, 74HC, and 20-Pin PAL®
Family
(TOP VIEW)
VCC
• UV-Light-Erasable Cell Technology
Provides:
- Reconflgurable Logic
- Reprogrammable Cells
- Full Factory Testing for 100%
Programming Yields
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
• High-Voltage EPIC'M Process Allows for
Higher Performance as follows:
Maximum tpd: - 25M ... 25 ns
-201 •.. 20 ns
-15C ... 15 ns
FNPACKAGE
• User-Programmable Output Logic
Macrocells Provide Flexibility in Output
Types with:
- Selectable for Registered or
Combinational Operation
- Output Polarity Control
- Independently User Programmable
Feedback Path
(TOP VIEW)
i?u
_d~g
==
W
I/O
I/O
I/O
I/O
I/O
• Programmable Design-Security Bit
Prevents Copying of LogiC Stored in Device
~
a:
0-
t-
• Advanced Software Support Featuring
Schematic Capture, Interactive Netlist,
Boolean Equations, and State-Machine
Design Entry
O
::J
Pin assignments in operating mode
• Package Options Include:
- 20-pin Ceramic Dual-In-Llne (J) - UV-erasable
- 20-pin Plastic Dual-In-Line (N) - One-Time Programmable
- 20-pln Plastic Chip Carrier (FN) - One-Time Programmable
C
o
a:
0-
description
general
The EP330 features advanced· CMOS speed and very low power. It combines the High-Voltage
Enhanced-Processed Implanted CMOS (HVEPIC'M) process with ultraviolet-light-erasable technology. Each
output has an Output-logic-Macrocell (OlM) configuration that allows user definition of the output type. This
EPlD provides a reliable low-power substitute for numerous high-performance TTL PAls.
AVAILABLE OPTIONS
PACKAGE TYPE
SPEED
TA
RANGE
CLASS
CERAMIC
DUAL·IN·LINE
(J)
-55'C to 125'C
25 ns
EP330·25MJB
N/A
N/A
- 40'C to 85 'C
20 ns
EP330·201J
EP330·201N
EP330·201FN
O'C 10 70'C
15 ns
EP330·15CJ
EP330·15CN
EP330-15CFN
PLASTIC
DUAL·IN-LINE
(N)
PLASTIC
CHIP CARRIER
(FN)
EPIC IS a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories, Inc.
PRODUCT PREVIEW documents contain Information on
products In the tormatlve or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products wHhout notice.
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-3
EP330
HIGH-PERFORMANCE 8-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
description (continued)
The EP330 can accommodate up to 18 inputs and up to eight outputs. The 20-pin 300-mil package contains eight
macrocells each using a programmable AND/fixed-OR structure. This AND-OR structure yields eight product
terms for the logic function as well as an individual term for Output Enable.
The EP330 output-logic macrocell allows the user to configure output and feedback paths for combinationa.1 or
registered operation either active high or active low. With a tpd of 15 ns, the EP330 may be configured as a
low-power substitute for popular PAL devices such as the PAL16XXB series or the PAL16XX-15 series.
The CMOS EPROM technology makes it possibleforthe EP330to operate at an active power-consumption level
that is less than 75% of equivalent bipolar devices without sacrificing speed performance. This technology also
facilitates 100% generic testability as well as UV-light erasability. As a result, designs and design modification
can be quickly effected with a given EP330 without the need for post-programming testing.
Programming the EP330 is accomplished with the use ofthe TI EPLD development system, which supports four
different design entry methods. When the design has been entered, the A+PLUS software (which is the heart
of the development system) performs automatic translation into logical equations, performs complete Boolean
minimization, and fits the design directly into an EP330. The device can then be programmed to achieve
customized working silicon within mir]utes at the designer's desk.
'"0
The EP330M is characterized for operation over the full military temperature range of -55°C to 125°C. The
EP3301 is characterized for operation from -40°C to 85°C. The EP330C is characterized for operation from O°C
to 70°C.
::D
o
C
c:
functional description
o-I
'"0
::D
m
m
<
:E
Externally, the EP330 provides ten dedicated inputs (one of which may be used as a synchronous clock input)
and eight I/O pins that may be configured for input, output, or bidirectional operation.
The logic diagram shows the complete EP330, while Figure 1 shows the basic EP330 macrocell. The internal
. architecture is organized with the familiar sum of products (AND-OR) structure. Inputs to the programmable AND
array (shown running vertically in Figure 1) come from two sources: first, the true and complement of the ten
dedicated input pins and second, the true and complement of the eight feedback signals, each one originating
from an I/O architecture-control block. The 36-input AND array encompasses a total of 72 product terms
distributed equally among the eight macrocells. Each product term (shown running horizontally in the logic
diagram) represents a 36-input AND gate.
As shown in the logic diagram, the outputs of eight product terms are ORed together, then the output of the OR
gate is sent as an input to an exclusive-OR gate. The purpose of this exclusive-OR gate is to allow the user to
specify the polarity of the output signal by using the invert-select EPROM cell (active high if the EPROM cell is
programmed and active low if it is not programmed).
The exclusive-OR output then feeds the I/O architecture control block. The control block configures the output
for registered or combinational operation. In the registered configuration, the output is registered via a positive
edge-triggered D-type flip-flop. In this condition, the feedback signal going to the array is also registered and
comes directly from the output of the D-type flip-flop. In the combinational configuration, the output is
nonregistered and the feedback signal comes directly from the I/O pin. In the erased state, the EP330 contains
the same architectural characteristics as the PAL16L8.
2-4
TEXAS .Jf
INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
EP330
HIGH·PERFORMANCE 8·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
logic diagram (positive logic)
12
CLK/I
1
16
20
24
28
32
35
Vb~
DE
0
7
2
19
~
~JARCHITECTURE~
I/O
~
~,ARCHITECTURE~
1/0
18
~
~,ARCHITECTURE~
I/O
17
~
~JARCHITECTURE~
I/O
16
I/O
CONTROL
~~
DE
0
7
3
DE
0
'::"
7
4
I/O
CONTROL
I/O
CONTROL
DE
0
7
5
CONTROL
a..
I-
0
~
::::)
§l>-
7
~JARCHITECTURE~
I{O
15
I/O
CONTROL
C
0
a:
a..
DE
0
7
7
W
a:
I/O
DE
0
6
-==>w
§l>-
~JARCHITECTURE~
I/O
§l>-
~ARCHITECTUR~~
I/O
14
I/O
CONTROL
r
~
DE
0
8
7
13
I/O
CONTROL
I
DE
0
§l>-~J
I
12
I/O
I{O
ARCHITECTURE~
9
7
CONTROL
I
11
~
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-5
EP330
HIGH-PERFORMANCE 8-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
CLOCK
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
OE
}-Ok
VO
J"
12
RCHITECTUR~
CONTROL
h~ ) i\ l\.
l\. 4 ~l\.4
+
~
t
4
~
X. ~
) 4 ~ 4
~44 ~~~
n
••• ••
FEEDBACK
N.OTES: A. This diagram shows one of the eight macrocelis within the EP330.
B. The double·arrow lines (t) show I/O feedback from a macrocell.
FIGURE 1. LOGIC ARRAY MACRO CELL
."
output-enable product term
oC
The output enable (DE) product term determines whether an output signal is allowed to propagate to the output
pin. If the output of the DE product term is low, then the output buffer becomes a high-impedance node, thus
inhibiting the output signal from reaching the output pin. For combinational configurations, this DE product term
can be used to allow for true bidirectional operation.
£1
The EP330 contains eight separate OE product terms, one per I/O pin. If it is desired that all outputs be enabled
or disabled simultaneously, use an identically programmed product term at each of the outputs. If different
outputs are to be enabled under different conditions, different DE product terms for each specific output may
be defined .
:D
c
."
:D
~
1/0 architecture
-
Figure 2 shows the different output configurations that can be chosen for any ofthe eight I/O pins on the EP330.
Because of the individuality of each I/O architecture control block, both registered and combinational output can
be chosen on a given EP330 device.
In the combinational configuration, either active-high or active-low output polarity can be chosen. Pin feedback
or no feedback is also optional. In the registered configuration, the user has control over output polarity and may
choose to use the internal feedback path or no feedback. Any I/O pin can be configured as a dedicated input
by choosing no output and no feedback from the array. In the erased state, the I/O architecture is configured
for a combjnatlonal active-low output with pin feedback.
2-6
TEXAS -If
INSIRUMENTS
POST OFFice BOX 655303 ." DALLAS, TEXAS 75265
EP330
HIGH-PERFORMANCE 8-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
CLOCK
(PIN 1)
OE
AND
ARRAY
36 INPUT
AND
ARRAY
36 INPUT
OUTPUT/POLARITY
FEEDBACK
OUTPUT/POLARITY
FEEDBACK
Combinational/High
Pin, None
D Register/High
D Register, None
Combinational/low
Pin, None
D Register/low
D Register, None
None
Pin
None
D Register
3:
w
~
a:
c..
PAL compatibility
o
Figures 2(a) and 2(b) show how an EP330 can be configured as a drop-in replacement for two commonly used ::;)
(b) Registered Conflgratlon
(a) Combinational Configuration
FIGURE 2. I/O CONFIGURATIONS
~
Tables 1 and 2 provide additional information conceming the EP330 as a replacement for the 20-pin PAL family
of devices,
c
o
a:
TEXAS -If
2-7
members of the 20-pin PAL family: the PAL 16L8 and the PAL16R8. When configured in these manners, the
EP330 is both a functional replacement, as well as a pin-to-pin replacement, for the PAL16L8 and PAL 16R8,
INSJRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
c..
EP330
HIGH·PERFORMANCE 8·MACROCELL
ERASABLE PROGRAMMABLE LOGlC DEVICE (EPLD)
19
--'---CC::::J
36·INPUT
PROGRAMMABLE
AND ARRAY
2
18
3
17
9
12
11
•
"Invert Select" EPROM cell is in the erased state providing active-low outputs.
•
"Combinational Mode" is chosen providing Combinational Output with Input (Pin) Feedback (COIF).
•
8-product-term OR gate compared to 7·product-term OR gate on PALI6L8.
•
Pin feedback to the array at 12 through 19 is not available in PAL16L8.
FIGURE 3. EP330 CONFIGURATION FOR REPLACING A PAL16L8
2-8
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
EP330
HIGH·PERFORMANCE 8·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
19
2
18
3
17
4
16
3=
W
5>
W
5
a:
15
a.
I-
0
6
::J
14
C
0
a:
7
a.
13
8
12
9
11
•
"Invert Select" EPROM cell is in the erased state providing active-low outputs.
•
"Registered Mode" is chosen providing Registered Output with Registered Feedback (RORF).
•
Complement of pin 11 is used as common DE term for all eight output pins.
FIGURE 4. EP330 CONFIGURATION FOR REPLACING A PAL16RB
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-9
EP330
HIGH-PERFORMANCE 8-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
TABLE 1. CONFIGURATIONS FOR 20-PIN PAL
RE~LACEMENT
PAL
EP330
EP330
I/O
OUTPUT/
PART NUMBER
PIN NUMBER
MACROCELL NUMBER
CONFIGURATION MODE
POLARITY
10H8
12-19
1-8
Combinational
Comb/High
None
1018
12-19
1-8
Combinational·
Comb/low
None
12
8
Combinational
None
Pin
13-18
2-7
Combinational
Comb/High
None
19
1
Combinational
None
Pin
12
8
Combinational
None
Pin
13-18
2-7
Combinational
Comb/low
None
Pin
12H6
1216
14H4
14L4
"'tJ
::D
o
16C1
C
c:
o-I
16H2
16L2
"'tJ
::D
~
~
19
.1
Combinational
Non~
12-13
7-8
Combinational
None
Pin
14-17
3-6
Combinational
Comb/High
None
18-19
1-2
Combinational
None
Pin
12-13
7-8
Combinational
None
Pin
14-17
3-6
Combinational
Comb/Low
None
18-19
1-2
Combinational
None
Pin
12-14
6-8
Combinational
None
Pin
15
5
Combinational
Comb/Low
None
16
4
Combinational
Comb/High
None
17-19
1-3
Combinational
None
Pin
12-14
6-8
Combinational
None
Pin
15-16
4-5
Combinational
Comb/High
None
Pin
17-19
1-3
Combinational
None
12-14
6-8
Combinational
None
Pin
15-16
4-5
Combinational
Comb/low
None
17-19
1-3
Combinational
None
Pin
16H8
12
8
Combinational
Comb/High/Z
None
&
13-18
2-7
Combinational
Comb/HighiZ
Comb
16HD8
19
1
Combinational
Comb/High/Z
None
1618
12
8
Combinational
Comb/Low/Z
None
&
13-18
2-7
Combinational
Cdmb/Low/Z
Comb
16LD8
16R4
16R6
16R8
16P8
16RP4
16RP6
16RP8
2-10
FEEDBACK
19
1
Combinational
Comb/Low/Z
None
12-13
7-8
Combinational
Comb/low/Z
Comb
14-17
3-6
Registered
Reg/Low/Z
Reg
18-19
1-2
Combinational
Comb/low/Z
Comb
12
8
2-7
Combinational
Comb/Low/Z
Comb
13-18
Registered
Reg/Low/Z
Reg
19
1
Combinational
Comb/low/Z
Comb
12-19
1-8
Registered
Reg/Low/Z
Reg
12
8
Combinational
Comb/Option/Z
None
13-18
2-7
Combinational
Comb/Option/Z
Comb
19
1
Combinational
Comb/Option/Z
None
12-13
7-8
Combinational
Comb/Option/Z
Comb
14-17
3-6
Registered
Reg/Option/Z
Reg
18-19
1-2
Combinational
Comb/Option/Z
Comb
Comb
12
8
Combinational
Comb/Option/Z
13-18
2-7
Registered
Re/Option/Z
Reg
19
1
Combinational
Comb/Oplion/Z
Comb
12-19
1-8
Registered
Reg/Option/Z
Reg
TEXAS ."
INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
EP330
HIGH-PERFORMANCE 8-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
TABLE 2. DEVICE SPECIFICATIONSt
HIGH-SPEED PAL SERIES 16XXBI-15
HIGH-SPEED EPLD
PARAMETER
SYMBOL
EP330
PAL16LBBI-15
PAL16RBBI-15
45mA
180mA
180mA
tpd
Input to nonregistered output
15 ns
15 ns
NIA
teo1
Clock to output delay
12 ns
12 ns
·12 ns
tsu
fmax
Input setup time
12 ns
15 ns
15 ns
Max frequency
42 MHz
37 MHz
37 MHz
Supply current active
ICC
t
f= 1 MHz
Over commercial temperature range
absolute maximum
ratin~s
over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) ............................................ ,. -0.3 V to 7 V
Instantaneous supply voltage range, Vee (t s 20 ns) ..................................... -2 V to 7 V
Programming supply voltage range, Vpp ........................................... -·0.3 V to 13.5 V
Instantaneous programming supply voltage range, Vpp (t s 20 ns) ...................... -2 V to 13.5 V
Input voltage range, VI ............................................................. -0.3 V to 7 V
Instantaneous input voltage range, VI (t s 20 ns) ......................................... -2 V to 7 V
Vee or GND current range .................................................... -175 mA to 175 mA
Operating free-air temperature, T A ................................................. -·65°C to 135°C
Storage temperature range .............................................. . . . . . . . . .. -·65°C to 150°C
~
Il.
recommended operating conditions
EP330-201
EP330-25M
Supply voltage
W
a:
NOTE 1: All voltage values are with respect to GND terminal.
Vee
;:
UNIT
t;
5.25
V
::l
EP33D-15C
MIN
MAX
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
4.75
VI
Input voltage
0
Vee
0
Vee
0
Vee
V
VIH
High-level input voltage
2
Vee+0.3
2
2
VIL
low-level input voltage (see Note 2)
-0.3
0.8
-0.3
Vee+0.3
0.8
-0.3
Vee+0.3
0.8
V
0
Vee
0
VCC
0
Vec
V
Va
Output voltage
tw
Pulse duration, elK high or low
14
12
10
ns
V
tsu
Setup time, input
20
16
12
ns
th
Hold time, input
0
0
0
ns
tr
Rise time, input
3
3
3
3
3
ns"
C
oa:
Il.
Fall time, input
ns
3
tf
·C
Operating free-air temperature
-55
-40
70
125
85
0
TA
..
NOTE 2: The algebraic convention, In which the more negative value IS designated minimUm, IS used In thiS data sheet for logic voltage levels
only.
TEXAS
-If
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-11
EP330
HIGH-PERFORMANCE 8-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
electrical characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONSt
EP33D-25M
EP330-201
EP33D-15C
MIN
MIN
MIN
High-level output
VOH
VCC=MIN,
voltage
VOL
Low-level output voltage
VCC=MIN,
II
Input current
IOZ
Off·state output current
ICC
Supply current
Ci
Input capacitance
Co
Cclk
C pp
MAX
2.4
IOH=-8mA
MAX
2.4
MAX
2.4
UNIT
V
0.5
0.5
0.5
V
VI = VCCmax or GND
±10
±10
±10
VCC= MAX,
Va = VCC or GND
±10
±10
±10
!lA
!lA
f= 1 MHz,
No load,
Programmed as
an 8-bit counter
70
70
45
mA
VCC=5V,
VI =2V,
f= 1 MHz
10
10
·10
pF
Output capacitance
10
10
10
pF
Clock capacitance
10
10
10
pF
20
20
20
pF
IOL=24 mA
Programming input
capacitance (pin 11)
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER~
f max
EP330-25M
EP330-201
EP330-15C
MIN
MIN
MIN
Maximum frequency
MAX
tpd
Input to nonregistered output delay
Clock input to registered output delay
tpzx
Output enable time
tpxz
Output disable time
tcnt
Minimum clock period (internal)
CL = 35 pF,
See Note 3
See Note 4
Maximum frequency without
42
MAX
30
22
tco
fcnt
t
TEST CONDITIONSt
MAX
42
UNIT
MHz
25
20
15
ns
24
18
12
ns
20
20
15
ns
20
20
15
ns
24
20
15
ns
50
feedback, (1/tcnt>
66.6
MHz
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: Letter symbols for switching characteristics and timing requirements in this data sheet have been chosen for compatibility with those used in other
documentation previously prepared by another supplier for similar products. Any similarity to symbols used on other TI data sheets or to those
shown in glossaries in TI data books is coincidental. The meanings may not be the same.
NOTES: 3. The f max values shown represent the highest frequency of operation without feedback in the pipeline condition.
4. This is for an output voltage change of 500 mV.
PARAMETER MEASUREMENT INFORMATION
functional testing
The EP330 is functionally tested through complete testing of each programmable EPROM bit and all internal
logic elements, thus ensuring 100% programming yield. The erasable nature of the EP330 allows test program
patterns to be used and then erased.
2-12
TEXAS "
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
EP330
HIGH-PERFORMANCE 8-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
PARAMETER MEASUREMENT INFORMATION
r---Vcc
DEVICE -.f------i_-e-- ~~ST
OUTPUT
SYSTEM
CLt
r Includes capacitance. Equivalent loads may be used for testing.
FIGURE 5. DYNAMIC TEST CIRCUIT
design security
The EP330 contains a programmable design-security feature that controls the access to the data programmed
into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be
copied or retrieved. Therefore, a very high level of design control is achieved since programmed data within
EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset by
erasing the cells in the device.
latchup
The EP330 input, I/O, and clock pins have been carefully designed to resist the latchup that is inherent in CMOS
structures. The EP330 pins will not latch up for input voltages between --1 V and Vee + 1 V with currents up
to 250 mA. During transitions, the inputs may undershoot to -2 V for periods of less than 20 ns.
3:
w
~a:
D.
ti
Although the programming pin (pin 11) is designed to resist latchup to the 13.5-V limit, during positive-current
latch-up testing, the verify mode (pin 1) and program mode (pin 11) can be inadvertently entered into, causing ~
current flow in the pins. This should not be construed as latchup.
,.,.,
C
oa:
D.
TEXAS ..If
INSIRUMENlS
POST OFFICE BOX 655303 • DALLD.S, TEXAS 75265
2-13
EP330
HIGH-PERFORMANCE 8·MACROCELL
ERASABLE .PROGRAMMABLE LOGIC DEVICE (EPLD)
PARAMETER MI:ASUREMENT INFORMATION
_________I_NP_U_T_O_R_V_O____
~ _J~~----------------------------__
j+- tpd ---.!
*~------
__________________________
~I-----J
COMBINATIONAL OUTPUT
j4-tpxz-+j
HIGH IMPEDANCE
3·STATE
COMBINATIONAL OR
REGISTERED OUTPUT
'+-tpzx-+'
_ ____
~H~IG~H~IM~P~ED~A~N~C~E~-------I------~fr--------------------~
3.STATE
VAUD OUTPUT
(a) Combinational Mode
"C
tr-.l
:x:J
o
ClK
C
J
14- tw -+i
\\....----'1
!4- tsu --.!~I+--IIO
-++1'-<1-1
MACROCELL 18
1101112]
110-.-........
INPUT
MACROCEU 8
II!
~6
(181 (151
g~~ L.J'~~_IIO
' "1
G8
~
INPUT
11711141 INPUT
-"-'="------D.rI
'--_ _ _.:.e""'-8'.:.:."3"'-1
Pin numbers in ( ) are for DIP packages; pin numbers in [
CLKZ
I are for chip-carrier packages.
When both the true and complement forms of any signal are left intact, a logical false state results on the
output of the AND gate. If both the true and complement connections are open, then a logical "don't care"
applies for that input. If all inputs for the product term are programmed open, then a logical true state results
on the output of the AND gate.
Two dedicated clock inputs provide synchronous clock signals to the EP610 internal registers. Each of the
, clock signals controls a bank of 8 registers. CLK1 controls registers associated with macrocells 9-16, and
CLK2 controls registers associated with macrocells 1-8. The EP610 advanced I/O architecture allows the
number of synchronous registers to be user defined, from one to sixteen. Both dedicated clock inputs are
positive-edge triggered.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TeXAS 75265
2-17
EP610
HIGH·PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
I/O architecture
The EP610 inpuVoutput architecture provides each macrocell with over 50 possible 1/0 configurations. Each
I/O can be configured for combinational or registered output, with programmable output polarity. Four
different types of registers (D, T, JK, and SR) can be implemented into every I/O without any additional logic
requirements. 1/0 feedback selection can also be programmed for registered or input (pin) feedback. Another
benefit of the EP61 0 I/O architecture is its ability to individually clock each internal register from asynchronous
clock signals.
1
2
3
4
•
7
8
•
10
11
12
13
,.
14
16
17
,.
18
20
21
22
23
24
2.
26
27
28
2.
30
31
32
33
34
3.
36
37
38
3.
SYNCHRONOUS
ClOCK
OE/ClK
Vcc~
-,:: '--"
OE
-o--t::~
--'i
OEIClK
elK
}-
I"
~
...
2
3
~
4
=':r-
""}=)""}-
~ 6
~
•
I/O
ARCHrrECTURE
CONTROL
H>~
~
-D-
CLEAR
L)'LJ.
. L ).
).
L
12,
131
1:,L:,t
171
18'
'"
{10J
(111
)'LJ.
)'L)'
~
{141 1151
(161 1111 1181 1191
).
J.
).~·Lf
(201 1211
if;(23}
00---
FEEOBACK
Pin numbers are for dual-in-line packages.
FIGURE 1. LOGIC ARRAY MACROCELL (MACROCELL 1 ILLUSTRATED)
OE/CLK selection
Figure 2 shows the two modes of operation that are provided by the OE/eLK select multiplexer. The operation
. of this multiplexer is controlled by a single EPROM bit and may be individually configured for each EP610 I/O
pin. In Mode 0, the 3-state output buffer is controlled by a single product term. If the output of the AND gate is
true, the output buffer is enabled. If the output of the AND gate is false, the output buffer is in the highimpedance state. In this mode, the macrocell flip-flop may be clocked by its respective synchronous clock
input. After erasure, the OEleLK select multiplexer is configured in Mode O.
In Mode 1, the output-enable buffer is always enabled. The macrocell flip-flop may now be triggered from an
asynchronous clock signal generated by the OEleLK multiplexable product term. This mode allows individual
clocking of flip-flops from any available signal in the AND array. Because both true and complement signals
reside in the AND array, the flip-flop may be configured for positive- or negative-edge-triggered operation.
With the clock now controlled by a product term, gated clock structures are also possible.
2-18
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 75265
EP610
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
MOOEO
MODE 1
OE - P-T arm Controlled
CLK - Synchronous
OE - Enabled
elK - Asynchronous
SYNCHRONOUS'
CLOCK
SYNCHRONOUS
CLOCK
VCC
VCC
110
REGISTER
The register 'is clocked by the synchronous clock signal. which is
common to 11 other Macrocells. The output is enabled by the logic
from the product term.
OUTPUT
BUFFER
The output is permanently enabled and the register is clocked via
the product term. This allows for gated clocks that may be generated
from elsewhere in the EP610.
FIGURE 2. OE/CLK SELECT MULTIPLEXER
output/feedback selection
Figure 3 shows the EP61 0 basic output configurations. Along with combinational output, 4 register types are
available. Each macrocell I/O may be independently configured. All registers have individual asynchronous
clear control from a dedicated product term. When the product term is asserted, the macrocell register will
immediately be loaded with a zero independently of the clock. On power-up, the EP610 performs the clear
function automatically.
When the D or T register is selected, 8 product terms are ORed together and made available to the register
input. The invert select EPROM bit determines output polarity. The feedback-select multiplexer enables
register, I/O (pin), or no feedback to the AND array.
If the JK or SR registers are selected, the 8 product terms are shared between 2 OR gates. The allocation of
product terms for each register input is optimized by the TI EPLD Development System. The invert select
EPROM bit configures output polarity. The feedback-select multiplexer enables registered or no feedback to
the AND array.
Any I/O pin may be configured as a dedicated input by selecting no output and pin feedback. No output is
obtained by disabling the macrocell output buffer. In the erased state, each I/O is configured for
combinational active-low output with input (pin) feedback.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265,
2-19
EP610
HIGH·PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
1/0 SELECTION
FEEDBACK
OUTPUT/POLARITY
Combinational/high
Pin, None
Combinationaillow
Pin, None
None
Pin
(s) COMBINATIONAL
SYNCHRONOUS
CLOCK
VCC
OE/CLK
SELECT
I/O SELECTION
OE
OUTPUT/POLARITY
FEEDBACK
JK Register/high
JK Register/low
JK Register. None
JK Register. None
None
None
JK Register
Pin
FUNCTION TABLE
Q
INPUTS
(b) D-TYPE FLIP-FLOP
FIGURE 3_ I/O CONFIGURATIONS
2-20
TEXAS •
INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS, texAS 75265
OUTPUT
Q
CLR
CLK
D
L
I
I
L
L
L
H
H
L
Lor H
X
X
X
00
H
L
EP610
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SYNCHRONOUS
CLOCK
VCC
OE/CLK
SELECT
I/O SELECTION
ClK
OE
OUTPUT/POLARITY
T Register/high
FEEDBACK
T Register, Pin, None
T Registerllow
T'Register, Pin. None
None
T Register
None
Pin
FUNCTION TABLE
o
1T
INPUTS
CLR
ClK
L
Cl
~~~--------------~R
OUTPUT
I
T
L
QO
L
I
H
00
L
Lor H
00
H
X
X
X
0
L
lei TOGGLE FLIP-FLOP
SYNCHRONOUS
CLOCK
VCC
OE/CLK
SELECT
I/O SELECTION
OUTPUT/POLARITY
FEEDBACK
JK Register/high
JK Register, None
OE
JK Register/low
JK Register. None
None
JK Register
--"""'0
FUNCTION TABLE
INPUTS
Cl
OUTPUT
CLR
CLK
J
K
0
L
t
t
t
t
L
L
L
H
QO
L
L
L
L
L
H
Lor H
X
H
L
H
H
H
00
X
X
X
X
QO
L
Idl J··K FLIP-FLOP
FIGURE 3_ 1/0 CONFIGURATIONS (CONTINUED)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TEXAS 75265
2-21
EP610
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SYNCHRONOUS
CLOCK
VCC
OE/ClK
SELECT
I/O SELECTION
FEEDBACK
OUTPUT/POLARITY
SR Register/high
SR Register/low
SR Register. None
SR Register. None
None
SR Register
FUNCTION TABLE
OUTPUT
INPUTS
ClR
ClK
S
R
Q
L
t
t
t
t
L
L
00
L
L
L
L
H
L
H
L
H
L
H
H
H
Undefined
Lor H
X
X
00
X
X
X
L
FIGURE 3. 1/0 CONFIGURATIONS (CONTINUED)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range. Vee (see Note 1) ..................................... -0.3 V to 7 V
Instantaneous supply voltage range, Vee (t :s; 20 ns) ............................ -2 V to 7 V
Programming supply voltage range, Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 13.5 V
Instantaneous programming supply voltage range, Vpp (t :s; 20 ns) ................. -2 V to 13.5 V
Input voltage range, VI ................................................. -0.3 V to 7 V
Instantaneous input voltage range, VI (t co;; 20 ns) ............................... -2 V to 7 V
Vee or GND current ............................................. -175 mA to 175 mA
Power dissipation at 25°e free-air temperature (see Note 2) .. . . . . . . . . . . . . . . . . . . . . . .. 1000 mW
Operating free-air temperature, TA ...................................... -65°e to 135°e
Storage temperature range ........................................... -65°e to 1500 e
NOTES: 1. All voltage values are with respect to GND terminal.
2. For operation above 25°C free-air temperature, derate to 120 mW at 135°C at the rate of 8.0 mWrC.
2-22
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
EP610
HIGH-PERFORMANCE 16-MACROCElL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
recommended operating conditions
EP6101
PARAMETER
EP610C
MIN
Vee
VI
Supply voltage
0
VIH
High-level input voltage
low-level input voltage (see Note 3)
Output voltage
tr
Rise time
TA
MIN
5.5
4.75
5.25
0
VCC
2
VCC+0.3
4.5
Input voltage
Vil
Vo
tl
MAX
Vee
VCC+0.3
2
0.3
0.8
0.3
0.8
0
VCC
100
0
VCC
250
ClK input
Fall time
MAX
Other inputs
250
ClK input
100
250
Other inputs
250
500
Operating Iree-air temperature
-40
500
85
0
70
UNIT
V
V
V
V
V
ns
ns
°e
Note 3: The algebraic convention, In which the more negative value IS designated minimum, is used in this data sheet lor logic voltage levels
and temperature only.
electrical charateristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDtTIONS
ITIL
ICMOS
High-level output
VOH voltage
IOH
IOH
= -4mA
= -2 mA
EP6101
MtN
TYpt
EP610C
MAX
MIN
2.4
2.4
3.84
3.84
TYpt
MAX
UNIT
V
Val
low-level output voltage
IOl-4mA
0.45
0.45
V
II
Input current
VI
±10
±10
IlA
10Z
Off-state output current
= VCC or GND
Va = VCC or GND
±10
I1A
ICC
Supply current
I Standby
I Non-turbo
ITurbo
±10
I See Note 4
VI = VCC or GND,
No load
= 0, I =
I See Note 5
I See Note 5
Input capacitance
VI
Co
Output capacitance
Cclk
Clock capacitance
Va - 0, I - 1 MHz, TA - 25°C
VI - 0, I - 1 MHz, TA - 25°C
t All typical values are at VCC
0.15
0.02
0.1
3
15
3
10
32
75
32
60
= 25°C
Ci
1 MHz, TA
0.02
mA
20
20
pF
20
20
pF
20
20
pF
= 5 V, TA = 25°C.
NOTES: 4. When in the non-turbo mode, the device automatically goes into the standby mode approximately 100 ns after the last transition.
5. These parameters are measured with device programmed as a 16-bit counter and I = 1 MHz.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-23
EP610
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
combinational mode, turbo bit on
PARAMETERt
TEST CONDITIONS
tpdl
Input to nonregistered output
tpd2
tpzx
1/0 input to nonregistered output
Input to output enable
CL=35pF
tpxz
Input to output disable
tclr
Asynchronous output clear time
CL - 5 pF.
CL-35pF
tio
1/0 input buffer delay
EP61 0·25
MIN
EP61D-30
MAX
MIN
25
See Note 6
EP61 0·35
MAX
MIN
MAX
UNIT
27
30
32
35
37
ns
ns
25
30
35
ns
25
27
30
32
35
37
ns
2
2
2
ns
ns
combinational mode, turbo bit off
PARAMETERt
TEST CONDITIONS
todl
Input to nonregistered output
tpd2
tpzx
1/0 input to nonregistered output
tpxz
Input to output disable
CL = 5 pF.
tclr
tio
Asynchronous output clear time
1/0 input buffer delay
CL-35pF
EP6l 0·25
MIN
CL = 35 pF
Input to output enable
See Note 6
EP6l0·30
MAX
MIN
EP61D-35
MAX
MIN
MAX
UNIT
55
57
60
65
ns
62
67
ns
55
55
60
60
65
65
ns
57
62
67
ns
2
2
2
ns
ns
synchronous clock mode
PARAMETERt
TEST CONDITIONS
f max
Maximum frequency
See Note 7
tcol
Clock to output delay time
tcnt
Minimum clock period (register
feedback to register output)
See Note 5
fcnt
Maximum frequency with feedback
See Note 5
EP6l 0·25
MIN
MAX
EP61 0·30
MIN
MAX
41.7
47.6
EP6l0·35
MIN
MAX
37
MHz
15
17
20
25
30
35
40
33.3
UNIT
28.6
ns
ns
MHz
asynchronous clock mode
PARAMETERt
fmax
Maximum frequency
taco 1
Clock to output
delay time
tacnt
Minimum clock period (register
feedback to register output)
facnt
Maximum frequency with feedback
TEST CONDITIONS
See Note 7
EP6l 0·25
MIN
MAX
47.6
ITurbo bit on
ITurbo bit off
EP61 0·30
MIN
MAX
41.7
27
57
30
35
28.6
UNIT
MHz
37
67
62
33.3
MAX
37
32
25
40
EP61D-35
MIN
ns
ns
MHz
t Letter symbols for switching characteristics and timing requirements in this data sheet have been chosen for compatibility with those used in
other documentation previously prepared by another supplier for similar products. Any similarity to symbols used on other TI data sheets or to
those shown in glossaries in TI data books is coincidental. The meanings may not be the same.
NOTES: 5. These parameters are measured with device programmed as a 16-bit counter and f = 1 MHz.
6. This is for an output voltage change of 500 mY.
7. The f max values shown represent the highest frequency of operation without feedback.
2-24
TEXAS . "
INSTRUMENTSPOST OFFICE BOX,656012 • DALLAS. TEXAS 75265
EP610
HIGH-PERFORMANCE 16-MACOCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
timing requirements over recommended ranges of supply vOltag'e and free-air temperature
synchronous clock mode
PARAMETERt
TEST CONDITIONS
ITurbo bit on
ITurbo bit off
tsu
Input setup time
th
Input hold time
tch
Clock high pulse duration
tcl
Clock low pulse duration
EP61 0-25
MIN
MAX
21
51
0
10
10
EP61 0-30
MIN
MAX
24
54
0
11
11
EP61 0-35
MIN
MAX
27
57
0
.12
12
UNIT
ns
ns
ns
ns
asynchronous clock mode
PARAMETERt
tasu
Input setup time
ITurbo bit on
ITurbo bit off
tah
Input hold time
tach
tacl
Clock high pulse duration
Clock low pulse duration
TEST CONDITIONS
EP610-25
MIN
MAX
8
38
12
10
10
EP61 0-30
MIN
8
38
12
11
11
MAX
EP610-35
MIN
8
38
12
12
12
MAX
UNIT
ns
ns
ns
ns
t Letter symbols for switching characteristics and timing requirements in this data sheet have been chosen for compatibility with those used in
other documentation previously prepared by another supplier for similar products, Any similarity to symbols used on other TI data sheets or to
those shown in glossaries in TI data books is coincidental. The meanings may not be the same,
TEXAS ,.,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-25
EP610
HIGH· PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
functional testing
The EP61 0 is functionally tested including complete testing of each programmable EPROM bit and all internal
logic elements thus ensuring 100% programming yield. As a result, traditional problems associated with fuseprogrammed circuits are eliminated. The erasable nature of the EP610 allows test program patterns to be
used and then erased.
Figure 4 shows the test circuit and the conditions under which dynamic measurements are made. Because
power supply transients can affect dynamic measurements, simultaneous transitions of multiple outputs
should be avoided to ensure accurate measurement. The performance of threshold tests under dynamic
conditions should not be attempted. Large-amplitude fast ground-current transients normally occur as the
device outputs discharge the load capacitances. These transients flowing through the parasitic inductance
between the device ground terminal and the test-system ground can create significant reductions in
observable input noise immunity.
,------Vcc
DEVICE _ _ . - -....- -....-TO
OUTPUT
TEST SYSTEM
340 II
el t
tlncludes jig capacitance
FIGURE 4. DYNAMIC TEST CIRCUIT
design security
The EP61 0 contains a programmable design security feature that controls the access to the data programmed
into the device. If this programmable feature is used, a proprietary design implemented in the device cannot
be copied or retrieved. This enables a high level of design control to be obtained since programmed data
within the EPROM cells is invisible. The bit that controls this function, along with all other program data, may
be reset by erasing the device.
turbo bit
Some EPLDs contain a programmable option to control the automatic power-down feature that enables the
low-standby-power mode of the device. This option is controlled by a turbo bit that can be set using the EPLD
Development System. When the turbo bit is on, the low-standby-power mode is disabled. This renders the
circuit less sensitive to Vee noise transients created by the power-up/power-down cycle when operating in
the low-power mode. The typical lee versus frequency data for both the turbo-bit-on mode and the turbo-bitoff (low-power) mode is shown in Figure 5. All dynamic parameters are tested with the turbo bit on. Figure 6
shows the relationship between the output drive currents and the corresponding output voltages.
2-26
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
EP610
HIGH·PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SUPPLY CURRENT
vs
MAXIMUM FREQUENCY
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
100
100
70
TURBO BIT ON
~
«
10
40
I
C
!
:;
C
!
:;
20
:;
S::l
10
u
CJ
~
a.
a.
TURBO BIT OFF
Jl
IOL
/"""
--
E
I
Vee - 5 V
TA - 25°e
/
I
.............
~H
7
'\.
0
I
~
I
\
.9
0.1
0.01
100
\.
4
Vee - 5 V
TA - 15°e
1 k
10 k 100 k 1 M 10 M 100 M
fmax-Maximum Frequency-Hz
\
2
1
\
o
2
3
4
VO-Output Voltage-V
5
FIGURE 6
FIGURE 5
If the design requires low-power operation, the turbo bit should not be set. When operating in this mode,
some dynamic parameters are subject to increases.
TEXAS •
INSTRUMENTS
PeST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-27
EP610
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
X
INPUT OR 1/0
----------------------,~--------------------[4--tpd---+i
COMBINATIONAL
OUTPUT
__________________________
X
l ,.---------
~I--------J
__
====-t
I4-- tPXZ
COMBINATIONAL OR
)
HIGH-IMPEOANCE STATE
VALID
OUTPUT
REGISTERED OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _~------I,,.....;~--~==~;;,;.:;-
~tpzx--+I
COMBINATIONAL OR _ _ _ _.:.;H;;.;;IG;;.;H;.;.-IM;;;;..:PE;;D;;;A;,;,NC;;;E;;.;S;,;T;;;A;:,;TE;..._ _...;.I,______-CKr--V-A-Ll-D-O-U-TP-U-T--REGISTERED OUTPUT
_
[4---lcl'~
REGISTERED OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
\J ___
ASYNCHRONOUSLY
__IA'"
Cl.E;;;A..
R.;;O.;;UT.;.;P..;;U;.;,T_ _ _
la) COMBINATIONAL MODE
If--Ich---"
ClK1. ClK2
\}I~.'IV
J:I \ \. /
-.../ t,
INPUT OR 1/0
-+I If I*-tcl---.l
'I
14--
I4-lsu~lh~
~
VALID
\'--
.
~I".""''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
I
"'-lco1~
REGISTERED OUTPUT
_____________________
Xl~--------------_
_
VALID OUTPUT
(b) SYNCHRONOUS CLOCK MODE
REGISTERED OUTPUT
____________________Xlr--------------_
•
(e) ASYNCHRONOUS CLOCK MODE
FIGURE 7. SWITCHING WAVEFORMS
2-28
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 •
DAL.l~S.
TEXAS 75265
VALID OUTPUT
EP610
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
MECHANICAL DATA
lr
.24-PIN CERAMIC DIP (CDIP}
l.14 (0.045}
0.97 (0.0381
·:~~~::::Q::::::I~~~'w
I I-- 2.49 (0.0981
--.j
0.13 (0.005}
MIN
MAX
I
~
~
24-PIN DIP PlASTIC (PDIP}
1.40 (0.055}
1tO.51~~N020}
8.26 (0.325}
7.49 (0'295}~
6.86 (0.270}
6.22 (0.245}
0.305 (0.012}
0.203 (0.008}
: :-: ~'7:7'- tl
PIN 1
1.14 (0.045}1i
j~::::::::::]
r
I
31.89 (1.255}
3.68 (0.145}
31.50 (1.2401
3.18 (0.125}
SEATING
4.32 (0.170}
3.56 (0.140}
-t-~
0.51T~p020}
~" -'-i~ li li li ~ ~ li UUli ~ li~- -
~
0.51 (0.020} MIN
Irli'
10-
2.54 (0.1001 SSC
,.''''.~" ~
II
0.41 (0.016} --I~
-'''''
3: 18 (0: 125}
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-29
EP610
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
MECHANICAL DATA
28·PIN CERAMIC LEADED CHIP CARRIER (CLCC)
GLASS
WINDOW
n m~
3.S1 10.1501 R TYP.
12.57 10.495I
12.3210.4851
11.5810.4561
10.92 10.4301
---
, -J1
+ ---
Y~::.L:::j'
Ij.-- 7.62REF
10.3001
I
-----.j
BOTTOM VIEW
1.1410.0451 R
0.S9 10.0351
~12'5710'4961~
12.32T~~4851
VIEW
0'S910'035IX45'1~0'2510'0101
0.1510.0061
JJ.
T7
0.2010. 00SI ...J
-L
IT
0.5310.0211
! 0.43 T· 0 17)
~~~=~=
f
f
0.S1 10.0321
I
NOM
DETAIL "P"
0.66 10.0261
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
2·30
TEXAS ~
INS"TRUMENlS
POST OFFICE BOX 855012 • PALLAS. TEXAS 75265
SEE
DETAIL "P"
/_.----./
10.9210.4301
EP610
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
MECHANICAL DATA
28-PIN PLASTIC LEADED CHIP CARRIER (PLCCI
1.27 10.05011
Bse
SEE
DETAil
"8"
r
/~~
,PIN NO.'
1,1410.045)x45°
I
Ti
/
I
12,57 10.4951
12.32 10.4B51
"-
\
10.92 10.4301
11,58 (0.456)
J'OOI
Lji
Ij.--- 7.62REF
10.3001
I
------.j
I
r-
0.25410.0101
0.203 10.00Bt"1
1.22 10.0481
~
1.07 (0.0421
T""
1.22 (0.0481
1.07 (0.0421
J
o.64 (0.0251
MIN
3.05 (0.1201
2.29 10.0901
4.57 (0.1aOI
4,1910.1651
111
0.51 (0.0201 MIN
~
1.14 (0.0451
1 ~ 0,64 (0.025)
~
DETAIL "B"
r
0.53(0.0211
L0.41 lO.0161
f
f
0.81 (0.0321
0.66 10.0261
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
2-31
-
2-32
EP630
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
D3357, OCTOBER 1989
JT OR NT PACKAGE
ITOPVIEW)
• High-Density (Over 600 Gates)
Replacement for TIL and 74HC
• Low Operating Current:
ICC max, , , 100 mA
CLK
VCC
)
• High Speed:
Propagation Delay Time, .• 20 ns
110
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
• Asynchronous Clocking of All Registers or
Banked Register Operation from
2 Synchronous Clocks
• Sixteen Macrocells with Configurable I/O
Architecture Allowing for up to 20 Inputs
and 16 Outputs
1/0
GND
• Each Output Macrocell User-Programmable
for 0, T, SR, or JK Flip-Flops with Individual
Clear Control or Combinational Operation
CLK2
FZ OR FN PACKAGE
ITOP VIEW)
• UV-Light-Erasable Cell Technology Allows
for:
Reconflgurable Logic
Reprogrammable Cells
Full Factory Testing for 100%
Programming Yields
;;;: U U
o
U U
0
""_u»_""
...J
4
3 2
~
w
1 282726
:>w
25
24
• Programmable Design Security Bit Prevents
Copying of Logic Stored In Device
• Advanced Software Support Featuring
Schematic Capture, Interactive Netlist,
Boolean Equations, and State Machine
Design Entry
7
23
8
22
10
21
20
11
a:
Q.
I-
o
19
::>
12131415161718
• Package Options Include Plastic [for OneTime-Programmable (OTP) Devices] and
Ceramic Dual-In-Line Packages, Ceramic
Quad Flat Packages, and Plastic Chip
Carriers
c
oa:
Q.
NC-No internal connection
AVAILABLE OPTIONS
PACKAGE TYPE
TA
RANGE
SPEED
CLASS
CERAMIC
DUAL-IN-LINE
(JT)
O°C to 70°C
- 40°C 10 B5°C
20
25
EP630-20CJT
EP630-251JT
J-LEADED
CERAMIC
QUAD FLATt
(FZ)
EP630-20CFZ
EP630-251FZ
- 55°C to 125°C
25
EP630-25MJTB
EP630-25MFZB
PLASTICt
DUAL·IN-LiNE
(NT)
PLASTICt
CHIP CARRIER
(FN)
EP630-20CNT
EP630-251NT
EP630-20CFN
EP630-251FN
N/A
N/A
t Contact factory for mechanical data on this package.
fnR~:'U~~!:t'~~E: ~.!:i~~a~i::s:o:feJ:er::!~~
Characlll,isti. data .... ottior opacifications are dasign
goals. Taxas Instruments reserves the right to change
Dr di8continue thase products without notice.
Copyright © 1989. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 15265
2-33
EP630
HIGH· PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
description
general
The Texas Instruments EP630 Erasable Programmable Logic Device is capable of implementing over
600 equivalent gates of SSI and MSI logic functions all in plastic and ceramic space-saving 24-pin, 300-mil
dual-in-line (DIP) packages and 28-pin chip-carrier packages. It uses the familiar sum-of-products logic,
providing a programmable AND with a fixed OR structure. The device accommodates both combinational and
sequential .(registered) logic functions with up to 20 inputs and 16 outputs. The EP630 has a user
·programmable output logic macrocell that allows each output to be configured as a combinational or
registered output and feedback signals active high or active low.
A unique feature of the EP630 is the ability to program D, T, SR, or JK flip-flop operation individually for each
output without sacrificing product terms. In addition, each register can be individually clocked from any of the
input or feedback paths available in the AND array. These features allow a variety of logic functions to be
simultaneously implemented.
The CMOS EPROM technology reduces the power consumption to less than 55% of equivalent bipolar
devices without sacrificing speed performance. Erasable EPROM bits allow for enhanced factory testing.
Design changes can be easily implemented by erasing the device with ultraviolet (UV) light.
Programming the EP630 is accomplished by using the TI EPLD Development System, which supports four
different design entry methods. When the design has been entered, the software performs automatic
translation into logical equations, Boolean minimization, and design fitting directly into an EPLD.
"0
;:g
o
c
c:
(')
functional
The EP630 is an Erasable Programmable Logic Device (EPLD) that uses a CMOS EPROM technology to
implement logic designs in a programmable AND logic array. The device contains a revolutionary
programmable I/O architecture that provides advanced functional capability for user programmable logic.
~
"0
;:g
m
S
m
:E
. Externally, the EP630 provides 4 dedicated data inputs and 16 I/O pins, which may be configured for input,
output, or bidirectional operation. Figure 1 shows the EP630 basic logic array macrocell. The internal
architecture is organized with familiar sum-of-products (AND-OR) structure. Inputs to the programmable AND
array come from true and complement signals from the 4 dedicated data inputs and the 161/0 architecturecontrol blocks. The 40-input AND array encompasses 160 product terms, which are distributed among 16
available macrocells. Each EP630 product term represents a 40-input AND gate.
Each macrocell contains 10 product terms, 8 of which are dedicated for logic implementation. One product
term is used for clear control of the macrocell internal register. The remaining product terms are used for
output enable/asynchronous clock implementation.
There is an EPROM connection at the intersection pOint of each input signal and each product term. In the
erased state, all connections are made. This means both the true and complement forms of all inputs are
connected to each product term. Connections are opened during the programming process. Therefore, any
product term may be connected to the true or complement form of any array input signal.
TEXAS ~
INSTRUMENlS
2-34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
EP630
HIGH·PERFORMANCE 16·MACOCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
functional block diagram
eLK1 111121
INPUT (21131
131141
12611221
I/O----"LJ
H_......~-I/O
~
w
5>
w
a:
Q.
I-
o
::::>
1101112]
1181 {151
IIO-4+1-1:':::]
-,1_";...:"'-,3c..
[171 (141 INPUT
"--_ _ _1:.;.:'6::.."c::'3::.' CLK2
Pin numbers in ( ) are for DIP packages; pin numbers in [
1are for chip-carrier packages.
When both the true and complement forms of any signal are left intact, a logical false state results on the
output of the AND gate. If both the true and complement connections are open, then a logical "don't care"
applies for that input. If all inputs for the product term are programmed open, then a logical true state results
on the output of the AND gate.
Two. dedicated clock inputs provide synchronous clock signals to the EP630 internal registers. Each of the
clock signals controls a bank of 8 registers. ClKl controls registers associated with macrocells 9-16, and
ClK2 controls registers associated with macrocells 1-8. The EP630 advanced I/O architecture allows the
number of synchronous registers to be user defined, from one to sixteen. Both dedicated clock inputs are
positive-edge-triggered.
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75266
2-35
EP630
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
I/O architecture
The EP630 input/output architecture provides each macrocell with over 50 possible I/O configurations. Each
I/O can be configured for combinational or registered output, with programmable output polarity. Four
different types of registers (D, T, JK; and SR) can be implemented into every I/O without any additional logic
requirements. 110 feedback selection can also be programmed for registered or input (pin) feedback. Another
benefit of the EP630 I/O architecture is its ability to individually clock each internal register from asynchronous
clock signals.
1
2
3
4
•
6
7
8
•
'10
11
12
,.
14
13
SYNCHRONOUS
16
18
17
20
"
22
21
24
23
26
2.
28
27
30
2'
31
32
34
33
36
3.
37
38
CLOCK
3.
OE/eLK
Vcc~
-L~
-n-:- ~ ~
OE/eLK
0'
r:---<>-
©
eLK
l~
=}=).=).-
."
::rJ
=}-
o
=}-
-6-
CLEAR
(")
-I
."
::rJ
-c>-~
~
C
c:
I/O
ARCt;llTECTURE
CONTROL
L~
121
31
,., t, '" ,., ,.,
.L
,.,
~
"
(101
1111
L
1141 (15\
(161
"L
\171
teL
-TLf
1181 1191 (201 1211
ttl31
FEED·
BACK
Pin numbers are for dual-in-line packages.
m
-<
--
FIGURE 1. lOGIC ARRAY MACROCEll (MACRO CEll 1 IllUSTRATED)
~ OE/CLK selection
Figure 2 showS the two modes of operation that are provided by the DE/elK select multiplexer. The operation
of this multiplexer is controlled by a single EPROM bit and may be individually configured for each EP630 I/O
pin. In Mode 0, the 3-state output buffer is controlled by a singleproductterm. If the output of the AND gate is
true, the output buffer is enabled. If the output of the AND gate is false, the output buffer is in the highimpedance state. In this mode, the macrocell flip-flop may be clocked by its respective synchronous clock
input. After erasure, the OE/elK select multiplexer is configured in Mode O.
In Mode 1, the output-enable buffer is always enabled. The macrocell flip-flop may now be triggered from an
asynchronous clock signal generated by the DE/elK multiplexable product term. This mode allows individual
clocking of flip-flops from any available signal in the AND array. Because both true and complement signals
reside in the AND array, the flip-flop may be configured for positive- or negative-edge-triggered operation.
With the clock now controlled by a product term, gated clock structures are also possible.
TEXAS ."
INSTRUMENlS
2-36
POST OFFICE BOX 656303 • DALLAS. TeXAS 16265
EP630
HIGH· PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
MODE 0
MODE 1
OE - P-Term Controlled
elK - Synchronous
OE - Enabled
eLK - Asynchronous
SYNCHRONOUS
CLOCK
SYNCHRONOUS
CLOCK
VCC
VCC
The register is clocked by the synchronous clock signal, which is
common to 7 other Macrocells. The output is enabled by the logic
from the product term.
The output is permanently enabled and the register is clocked via
the product term ..This al/ows for gated clocks that may be generated
from elsewhere in the EP630.
FIGURE 2. OE/ClK SELECT MULTIPLEXER
~
output/feedback selection
->w
W
Figure 3 shows the EP630 basic output configurations. Along with combinational output, four register types
are available. Each macrocell I/O may be independently configured. All registers have individual
asynchronous clear control from a dedicated product term. When the product term is asserted, the macrocell
register will immediately be loaded with a zero independently of the clock. On power-up, the EP630 performs
the clear function automatically.
a:
a..
I-
When the D or T register is selected, eight product terms are ORed together and made available to the (.)
register input. The invert select EPROM bit determines output polarity. The feedback-select multiplexer ::l
enables register, I/O (pin), or no feedback to the AND array.
C
If the JK or SR registers are selected, the eight product terms are shared between two OR gates. The
allocation of product terms for each register input is optimized by the TI EPLD Development System. The
invert select EPROM bit configures output polarity. The feedback-select multiplexer enables registered or no
feedback to the AND array.
Any I/O pin may be configured as a dedicated input by selecting no output and pin feedback. No output is
obtained by disabling the macrocell output buffer. In the erased state, each I/O is configured for
combinational active-low output with input (pin) feedback.
TEXAS . "
INSfRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-37
o
a:
a..
EP630
HIGH·PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
I/O SELECTION
(a)
"'tJ,
SYNCHRONOUS
CLOCK
VCC
:JJ
o
OUTPUT/POLARITY
FEEDBACK
Combinational/high
Pin, None
Combinational/low
Pin. None
None
Pin
COMBINATIONAL
OE/ClK
SELECT
C
I/O SELECTION
c:
o
OUTPUT/POLARITY
-t
"'tJ
ClK
:JJ
OE
m
S
m
FEEDBACK
o Register/high
o Register/low
o Register,
None
0 Register
None
Pin
o
Register, Pin. None
FUNCTION TABLE
10
~
o
INPUTS
ClR
ClK
L
C1
L
~~~--------------~R
(b) 0-TYPE FLIP-FLOP
FIGURE 3. I/O CONFIGURATIONS
TEXAS.~
2-38
INSTRUMENlS
POST OFFICE BOX 855303 • DAllAS; TEXAS. 75265
t
t
L
L
H
X
OUTPUT
0
0
L
L
H
H
X
X
00
L
Pin. None
EP630
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SYNCHRONOUS
CLOCK
VCC
OE/CLK
SELECT
I/O SELECTION
FEEDBACK
OUTPUT/POLARITY
T Register/high
T Register/low
OE
T Register. Pin. None
T Register, Pin, None
None
T Register
None
Pin
FUNCTION TABLE
INPUTS
OUTPUT
ClR
ClK
T
Q
L
L
QO
L
T
T
H
Co
L
L
X
Go
H
X
X
L
3:
w
:>w
Ie) TOGGLE FLIP-FLOP
SYNCHRONOUS
CLOCK
VCC
a::
~
OE/ClK
~
SELECT
o
::J
C
I/O SELECTION
OUTPUT/POLARITY
OE
FEEDBACK
JK Register/high
JK Register, None
JK Register/low
JK Register, None
None
JK Register
FUNCTION TABLE
INPUTS
C1
OUTPUT
ClR
ClK
J
K
Q
l
T
T
T
T
L
L
L
H
QO
L
H
L
H
DO
L
L
L
L
H
L
X
H
X
X
X
X
H
00
L
Id) J··K FLIP-FLOP
FIGURE 3. 1/0 CONFIGURATIONS (CONTINUED)
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-39
o
a::
~
EP630
HIGH-PERFORMANCE 16-MACROCELL
.
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SYNCHRONOUS
CLOCK
VCC
OE/ClK
SELECT
I/O SELECTION
OUTPUT/POLARITY
OE
FEEDBACK
SR Register/high
SR Register, Nona
SR Register/low
SR Register. None
None
SR Register
"""---'0
FUNCTION TABLE
C1
OUTPUT
INPUTS
ClR
ClK
S
R
0
L
t
t
t
t
L
L
00
L
L
l
L
H
."
XI
L
H
L
H
l
H
H
H
Undefined
L
X
X
00
X
X
X
L
o
C
c::
(')
Ie) S·R FLlp·FlOP
-t
FIGURE 3. 1/0 CONFIGURATIONS (CONTINUED)
."
XI
m
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
S
m
Supply voltage range, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V
Instantaneous supply voltage range, Vee (t :S 20 ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -:-2 V to 7 V
Programming supply voltage range, Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 13.5 V
Instantaneous programming supply voltage range, Vpp (t :S 20 ns) ................. -2 V to 13.5 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V
Instantaneous input voltage range, VI (t :S 20 ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2 V to 7 V
Vee or GND current . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . . -175 mA to 175 mA
Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°e to 135°e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°e to 1500 e
:e
NOTE 1: All voltage values are w~h respect to GND terminal.
TEXAS •
2-40
INSfRUMENlS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75285
EP630
HIGH·PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
recommended operating conditions
EP630-25M
PARAMETER
MIN
Supply voltage
4.5
Vee
VI
Input voltage
VIH
High-level input voltage
Vil
low-level input voltage (see Note 2)
Va
Output voltage
tr
Rise time
tf
Fall time
TA
Operating
0
MIN
5.5
Vee
Vee +0.3
2
EP630-20C
MAX
MIN
4.5
5.5
4.75
0
vee
0
2
Vee+ 0.3
2
5.25
V
Vee
Vee+ 0 .3
V
V
O.B
-0.3
O.B
-0.3
0.8
0
Vee
100
0
Vee
100
0
Vee
250
Other inputs
250
250
elK input
100
100
250
Other inputs
250
250
500
temperature
-55
125
-40
UNIT
MAX
-0.3
elK input
free~air
EP630-251
MAX
V
ns
500
85
0
V
ns
70
°e
Note 2: The algebraic convention, in which the more negative value is designated minimum, is used in this data sheet for logic voltage levels
only.
electrical charateristics over recommended ranges of supply vOltage and free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
EP6630-25M
MIN
High-level output
VOH voltage
VOL
low-level output voltage
II
Input current
10Z
Off-state output current
lec
Supply current
ITIL
leMOS
IOH - -4mA
2.4
= -2mA
= 4 mA
3.84
10H
EP630-201
MtN
MAX
2.4
EP630-20C
MIN
2.4
3.84
UNIT
MAX
V
3.84
0.45
0.45
0.45
V
VI - VCC or GNP
±10
±10
±10
j.lA
Va - Vec or GND
±10
±10
±10
j.lA
150
150
150
15
15
10
150
150
100
10l
IStandby
I Nonturbo
ITurbo
MAX
VI = VCC or GND,
No load
I See Note 3
I See Note 4
I See Note 4
Ci
Input capacitance
VI - 0, f - 1 MHz, TA - 25°C
eo
Output capacitance
Va
Cclk
Clock capacitance
VI - 0, f - 1 MHz, TA - 25°C
= 0, f = 1 MHz, TA = 25°C
j.lA
mA
20
20
20
pF
20
20
20
pF'
20
20
20
pF
:>w
a:
c..
t-
O
::J
C
oa:
c..
NOTES: 3. When In nonturbo, the device automatically goes Into the standby mode approximately 100 ns after the last tranSItion.
4. These parameters are measured with the device programmed as a 16-bit counter and f = 1 MHz.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 86&303 • DALLAS. TEXAS 75285
3:
w
2-41
EP630
HIGH-PERFORMANCE 16-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
combinational mode, turbo bit on
PARAMETERt
tpdl
TEST CONDITIONS
MAX
Input to nonregistered output delay
110 input to nonregistered output
tpd2
delay
tpzx
Output enable time
tpxz
Output disable time
Asynchronous output clear time
tclr
tio
EP630-25M
MIN
.
CL = 35 pF
CL = 5 pF,
See Note 5
CL - 35 pF
110 input buffer delay
EP630-251
MIN
EP630-20C
MAX
MIN
MAX
UNIT
25
25
20
ns
27
27
22
ns
25
25
20
ns
25
25
20
ns
30
30
25
ns
2
2
2
ns
combinational mode, turbo bit off
PARAMETERt
\gdl
Input to nonregistered output delay
tpd2
1/0 input to nonregistered output
delay
:J:J
tpzx
Output enable time
tpxz
Output disable time
C.
tclr
Asynchronous output clear time
1/0 input buffer delay
"'0
o
c:
o
-f
tio
S
m
~
EP630-25M
MIN
MAX
CL=35pF
CL - 5 pF,
CL-35pF
See Note 5
EP630-251
MIN
EP630-20C
MAX
MIN
MAX
UNIT
40
40
35
42
42
37
ns
40
40
35
40
40
45
45
35
40
ns
ns
2
2
2
ns
ns
ns
synchronous clock mode
"'0
:J:J
TEST CONDITIONS
PARAMETERt
fmax
Maximum frequency
tcol
Clock to output delay time
tcnt
fcnt
Minimum clock period (register
feedback to register output)
Maximum frequency with feedback
TEST CONDITIONS
See Note 6
EP63D-25M
MIN
MAX
50
MAX
50
See Note 4
See Note 4
EP630-251
MIN
EP630-20C
MIN
MAX
MHz
55
18
18
15
25
25
20
40
40
UNIT
ns
ns
MHz
50
asynchronous clock mode
PARAMETERt
f max
Maximum frequency
tacol
Clock to output
delay time
tacnt
Minimum clock period (register
feedback to register output)
facnt
Maximum frequency with feedback
TEST CONDITIONS
See Note 6
EP630-25M
MIN
MAX
EP630-251
MIN
MAX
EP630-20C
MIN
MAX
50
ITurbo btl on
ITurbo btl off
MHz
30
30
25
45
45
40
25
40
UNIT
25
40
20
50
ns
ns
MHz
t Letter symbols for switching characteristics and timing requirements in this data sheet have been chosen for compatibility with those used in
other documentation previously prepared by another supplier for similar products. Any similarity to symbols used on other TI data sheets or to
those shown in glossaries in TI data books is coincidental. The meanings may not be the same .
.NOTES: 4. These parameters are measured with device programmed as a 16-bit counter and f = 1 MHz.
5. This is for an output voltage change of 500 mY.
6. The fmax values shown represent the highest frequency of operation without feedback.
TEXAS ."
2-42
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
EP630
HIGH· PERFORMANCE 16·MACOCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
timing requirements over recommended ranges of supply voltage and free-air temperature
synchronous clock mode
PARAMETERt
tsu
Input setup time
TEST CONDITIONS
ITurbo bit on
1Turbo bit off
th
Input hold time
tch
Clock high pulse duration
tcl
Clock low pulse duration
EP630-25M
MIN
MAX
EP630-251
MIN
MAX
MAX
15
30
0
9
9
20
35
0
10
10
20
35
0
10
10
EP630-20C
MIN
UNIT
ns
ns
ns
ns
asynchronous clock mode
PARAMETERt
ITurbo bit on
ITurbo bit off
tasu
Input setup time
tah
Input hold time
tach
Clock high pulse duration
tacl
Clock low pulse duration
TEST CONDITIONS
EP630-25M
MIN
MAX
10
25
15
10
10
EP630-251
MIN
10
25
15
10
10
MAX
EP630-20C
MIN
8
23
12
9
9
MAX
UNIT
ns
ns
ns
ns
t Letter symbols for switching characteristics and timing requirements in this data sheet have been chosen for compatibility with those used in
other documentation previously prepared by another supplier for similar products. Any similarity to symbols used on other TI data sheets or to
those shown in glossaries in TI data books is coincidental. The meanings may not be the same.
;:
w
:>w
I%:
0..
t-
O
::J
Q
oI%:
0..
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS, TEXAS 76266
2-43
EP630
HIGH· PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
functional testing _
The EP630 is functionally tested including complete testing of each programmable EPROM bit and ali internal
logic elements thus ensuring 100% programming yield. As a result, traditional problems associated with fuse-_
programmed circuits are eliminated. The erasable nature of the EP630 allows test program patterns to be
used and then erased.
Figure 4 shows the test circuit and the conditions under which dynamic measurements are made. Because
power supply transients can affect dynamic measurements, simultaneous transitions of multiple outputs
should be avoided to ensure accurate measurement. The performance of threshold tests under dynamic
conditions should not be attempted. Large-amplitude fast ground-current transients normally occur as the
device outputs discharge the load capacitances. These transients flowing through the parasitic inductance
between the device ground terminal and the test-system ground can create significant reductions in
observable input noise immunity.
,..-----vcc
DEVICE _--._ _...._ _..._TO
OUTPUT
TEST SYSTEM
340 Il
CL t
"'0
::XJ
o
t Includes jig capacitance
Equivalent loads may be used for testing
C
c:
FIGURE 4. DYNAMIC TEST CIRCUIT
(")
-I
"'0
::XJ
design security
The EP630 contains a programmable design security feature that controls the access to the data programmed
into the device. If this programmable feature is used, a proprietary design implemented in the device cannot
be copied or retrieved. This enables a high level of design control to be obtained since programmed data
within the EPROM cells is invisible. The bit that controls this function, along with all other program data, may
be reset by erasing the device.
.
m
<
;n
~
turbo bit
These EPLDs contain a programmable option to control the automatic power-down feature that enables the
low-standby-power mode of the device. This option is controlled by a turbo bit that can be set using the EPLD
Development System. When the turbo bit is on, the low-standby-power mode is disabled. This renders the
circuit less sensitive to Vee noise transients created by the power-up/power-down cycle when operating in
the low-power mode. The typical lee versus frequency data for both the turbo-bit-on mode and the turbo-bitoff (low-power) mode is shown in Figure 5. All dynamic parameters are tested with the turbo bit on. Figure 6
shows the relationship between the output drive currents and the corresponding output voltages.
TEXAS ."
2-44
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
EP630
HIGH·PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SUPPLY CURRENT
vs
MAXIMUM FREQUENCY
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
100
100
70
TURBO BIT ON
~
c(
10
Vee - 5 V
TA - 25°e
40
I
~
~
::I
:;
~
!
CJ
CJ
;
>
Q.
TURBO BIT OFF
Q.
::I
/
20
I
10
5::I
7
I
4
IOL
/""
E
I
-...........
~H
"-
0
'"I
~
'\
\
9
0.1
\
2
0.01
100
Vee - 5 V
TA a 15°e
10 k 100 k
1 M
10 M 100 M
fmax-Maximum Frequency-Hz
1 k
1
o
FIGURE 5
2
4
3
VO-Output Voltage-V
\
5
~
s:w
FIGURE 6
If the design requires low-power operation, the turbo bit should not be set. When operating in this mode,
some dynamic parameters are subject to increases.
a::
a.
....
(.)
::J
Q
o
a::
a.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-45
...
EP630
HIGH·PERFORMANCE 16·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
X
INPUT OR 1/0
---------------------J~-------------------j4--tpd~
COMBINATIONAL
OUTPUT
--------------...;..----""\X
l ,....--------
••
---------------~I------'
~tpxz~
COMBINATIONAL OR
),
HIGH-IMPEDANCE STATE
VALID OUTPUT
~..:.:::::.:;.::::::..=:=;:;;..::~:.:;....
REGISTERED OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~------I
~tPzx---.l
COMBINATIONAL OR _______.;,;H~IG_H_-IM
__
PE;;;D.;,;A_NC_E;..S_T_A_TE
_____...;..II------IK,....-V-A-L-ID-O-U-T-PU-T---REGISTERED OUTPUT
•
j4---telr~
\l
ASYNCHRONOUSLY
REGISTERED OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'A\,_....::C;;:LE;:;;A:.:.:R.;;O~U~TP:..:U;.;T_ _
(al COMBINATIONAL MODE
"'0
~
CLK1, CLK2
~
INPUT OR 1/0
-I
~
-
\
{
~
~t.u-+r-th-.!
~
VALID
I+-tel-.!
V
~",.,_,.".,,.,,.,"7"7"7"7'r?''r?''r?',.,,.,,.,,.,''7''7''7''7'r?'~
I
"'0
~
---A
----.! t, I+-
C
-+I tf
!4- teo 1 ---+I
Xl~-------------•
VALID OUTPUT
REGISTERED OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J.
(bl SYNCHRONOUS CLOCK MODE
m
~
REGISTERED OUTPUT
_________________-..Jx'r--------------•
•
(el ASYNCHRONOUS CLOCK MODE
FIGURE 7. SWITCHING WAVEFORMS
TEXAS
~
INSTRUMENTS
2-46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VALID OUTPUT
EP910
HIGH·PERFORMANCE 24·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
03187, OCTOBER 1988-REVISED AUGUST 1989
DUAL-IN-LiNE PACKAGE
• High-Density (Over 900 Gates)
Replacement for TTL and 74HC
(TOP VIEW)
CLK
I
• Virtually Zero Standby Power .•. Typ 20 J.lA
• High Speed:
Propagation Delay Time ... 30 ns
VCC
I
I
110
1/0
110
1/0
1/0
110
1/0
1/0
110
1/0
110
1/0
I
1/0
110
110
110
110
1/0
110
1/0
110
110
110
110
• Asynchronous Clocking of All Registers or
Banked Register Operation from
2 Synchronous Clocks
• 24 Macrocells with Configurable I/O
Architecture Allowing for Up to 36 Inputs
and 24 Outputs
• Each Output Macrocell User-Programmable
for D, T, SR, or JK Flip-Flops with Individual
Clear Control or Combinational Operation
• UV-Light-Erasable Cell Technology Allows
for:
Reconfigurable Logic
Reprogrammable Cells
Full Factory Testing for 100%
Programming Yields
CLK2
GND
CHIP-CARRIER PACKAGE
(TDPVIEWI
• Programmable Design Security Bit Prevents
Copying of Logic Stored in Device
~
u u
a ___ U»
...J U
"'
• Advanced Software Support Featuring
Schematic Capture, Interactive Netlist,
Boolean Equations, and State Machine
Design Entry
6
5
4
3
2
U
0
___ '"
1 4443424140
39
38
37
• Package Options Include Plastic [For OneTime-Programmable (OTP) Devices] and
Ceramic Dual-In-Line Packages and
J-Leaded Chip Carriers
10
36
11
35
0
12
13
34
33
14
32
15
31
16
30
29
1819202122232425262728
0---00""---0
:::::
zz:::r.::::
:::::
(!)(!ld
NC-No internal connection
AVAILABLE OPTIONS
PACKAGE TYPE
TA
SPEED
CERAMIC
CERAMIC
PLASTIct
PLASTICt
RANGE
CLASS
DUAL-IN·LINE
CHIP CARRIER
DUAL·IN·LINE
CHIP CARRIER
PACKAGE (CDIP)
(CLCC)
PACKAGE (PDIP)
(PLCC)
EP910DC-30
EP910JC-30
EP910PC-30
EP910LC-30
30 ns
O°C _ 70°C
-40°C - 85°C
35 ns
EP910DC-35
EP910JC-35
EP910PC-35
EP910LC-35
40 ns
EP910DC-40
EP910JC-40
EP910PC-40
EP910LC-40
45 ns
EP910DI-45
EP910JI-45
EP910PI-45
EP910Ll-45
"lThis package is for One-Time-Programmable (DTP) devices.
PRODUCTION DATA documonts contain information
current 8S of publication datB. PnHlucts conform to
specifications par the terms of TexIs Instruments
:::~:~~i~air::I:ri ~!:~~~ti:r :I~":a~:::::':~~
not
Copyright @ 1989. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-47
EP910
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
description
general
The Texas Instruments EP910 Erasable Programmable Logic Device is capable of implementing over 900
equivalent gates of SSI and MSllogic functions accommodating up to 36 inputs and 24 outputs all in plastic
and ceramic space-saving 40-pin, 600-mil dual-in-line (DIP) packages and 44-pin chip-carrier packages.
Each of the 24 macrocells contains a programmable-AND, fixed-OR PLA structure that yields 8 product terms
for logic implementation and a single product term for output-enable and asynchronous-clear control
functions. The architecture of the output logic macrocell allows the EP910 user to program output and
feedback paths for both combinational or registered operation, active high or active low.
For increased flexibility, the EP910 also includes programmable registers. Each of the 24 internal registers
may be programmed to be a D, T, SR, or JK flip-flop. In addition, each register may be clocked
asynchronously on an individual basis or synchronously on a banked register basis.
In addition to density and flexibility, the performance characteristics allow the EP91 0 to be used in the widest
possible range of applications. The CMOS EPROM technology reduces the power consumption to less than
20% of equivalent bipolar devices without sacrificing speed performance. Another advantage is 100% generic
testing. The device can be erased with ultraviolet (UV) light. Design changes are no longer costly, nor is there
a need for post-programming testing.
Programming the EP910 is accomplished by using the TI EPLD Development System, which supports four
different design entry methods. When the design has been entered, the software performs automatic
translation into logical equations, Boolean minimization, and design fitting directly into an EP91 O. The device
may then be programmed to achieve customized working silicon within minutes at the designer'S own
desktop.
functional
The EP910 is an Erasable Programmable Logic Device (EPLD) that uses a CMOS EPROM technology to
implement logic designs in a programmable AND-logic array. The device also contains a revolutionary
programmable I/O architecture that provides advanced functional capability for user programmable logiC.
Externally, the EP910 provides 12 dedicated data inputs and 241/0 pins, which may be configured for input,
output, or bidirectional operation. Figure 1 shows the EP910 basic macrocell. The internal architecture is
organized with the familiar sum-of-products (AND-OR) structure. Inputs to the programmable AND array come
from the true and complement signal from 12 dedicated data inputs and 24 feedback signals originating from
each of the 24 I/O architectural control blocks. The 72-input AND array encompasses 240 product terms,
which are distributed among 24 available macrocells. Each EP910 product term represents a 72-input AND
gate.
At the intersection point between each AND array input and each product term, there is an EPROM control
cell. In the erased state, all connections are made. This means both the true and complement of all inputs are
connected to each product term. Connections are opened during the programming process. Therefore, any
product term may be connected to the true or complement form of any array input signal.
2-48
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
-
EP910
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
functional block diagram
elK' 111121
,12) 131
113) [4J
Vee
MACROCElL 12
MACROCELl 24
I
117) 119)
1271 (241 I
I
(181 [201
1261 (23)
I 11911211
[251122)
12411211 ClK2
Pin numbers in parenthesis are for DIP packages. Pin numbers in brackets are for chip-carrier packages.
When both the true and complement of an array input signal are connected, a logical false results on the
output of the AND gate. When both the true and complement forms of any array input signal are programmed
open, then a logical "don't care" results for that input. If all 72 inputs for a given product term are programmed
open, then a logical true state results on the output of the corresponding AND gate. Two dedicated clock
inputs (not available in the AND array) provide the clock signals used for asynchronous clocking of the EP91 0
internal registers. Each of these clock signals is positive-edge triggered and has control over a bank of 12
registers. CLK1 controls registers associated with macrocells 13 through 24. CLK2 controls registers
associated with macrocells 1 through 12. The EP910 advanced I/O architecture allows the number of
synchronous registers to be user defined, from 1 to 24. Both dedicated clock inputs are positive-edge
triggered.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-49
EP910
HIGH·PERFORMANCE 24·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
I/O architecture
The EP910 input/output architecture provides each macrocell with over 50 possible I/O configurations. Each
I/O can be configured for combinational or registered output, with programmable output polarity. Four
different types of registers (D, T, JK, and SR) can be implemented into every I/O without any additional logic
requirements. I/O feedback selection can also be programmed for registered or input (pin) feedback. Another
benefit of the EP91 0 I/O architecture is its ability to individually clock each internal register from asynchronous
clock signals.
01
1
•••
:I
Ii
7
~gMgg_
9
11
•••••••
_.~u_
..... _..• _.. ro
13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
53 55 57 59 61
SYNCHRONOUS
CLOCK
63 65 61 69 71
~1351
(3)
(5\
\7\
~
191
~
111\
~
113\
~
-
'150\
(17)
~
Pin numbers shown are for dual-in-line packages.
(19)
~
-123\
\2&\
\27\
~
(29)
~
(31\
~
- -t33}
137}
(39)
-
~
FIGURE 1. LOGIC ARRAY MACROCELL (MACROCELL 1 ILLUSTRATED)
OE/CLK selection
Figure 2 shows the two modes of operation that are provided by the OE/ClK select multiplexer. The operation
of this multiplexer is controlled by a single EPROM bit and may be individually configured for each of the
EP910 I/O pins. In Mode 0, the 3-state output buffer is controlled by the OE/ClK product term. If the output of
the AND gate is true, the output buffer is enabled. If the output of the AND gate is false, the output buffer is in
the high-impedance state. In this mode, the macrocell flip-flop is clocked by its respective synchronous clock
input signal (ClK1 or ClK2). After erasure, the OE/ClK select multiplexer is configured in Mode O.
In Mode 1, the output-enable buffer is always enabled. The macrocell flip-flop may now be triggered from an
"jasynchronous clock signal generated by the OE/ClK multiplexable product term. This mode allows individual
clocking offlip-flops from any of the 72 available AND array input signals. Because both true and complement
signals reside in the AND array, the flip-flop may be configured for positive- or negative-edge-triggered
operation. With the clock now controlled by a product term, gated clock structures are also possible.
2-50
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
EP91 0
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DElVE (EPLD)
MODE 0
MODE 1
OE -
OE - Enabled
eLK - Asynchronous
P-Term Controlled
ClK - Synchronous
SYNCHRONOUS
CLOCK
SYNCHRONOUS
CLOCK
VCC
VCC
1/0
REGISTER
1/0
REGISTER
The register is clocked by the synchronous clock signal, which is
common to 11 other Macrocells. The output is enabled by the logic
from the product term.
OUTPUT
BUFFER
The output is permanently enabled and the register is clocked via
the product term. This allows for gated clocks that may be generated
from elsewhere in the EP910.
FIGURE 2. OE/ClK SELECT MULTIPLEXER
output/feedback selection
Figure 3 shows the EP91 0 basic output configurations. Along with combinational output, 4 register types are
available. Each macrocell I/O may be independently configured. All registers have individual asynchronousclear control from a dedicated product term. When the product term is asserted, the macrocell register will
immediately be loaded with a zero independently of the clock. On power-up, the EP910 performs the clear
function automatically.
In the combinational configuration, 8 product terms are ORed together to acquire the output signal. The
invert-select EPROM bit controls output polarity and the output-enable buffer is product term controlled. The
feedback-select multiplexer enables registered I/O (pin), feedback, or no feedback to the AND array.
When the D or T register is selected, 8 product terms are ORed together and made available to the register
input. The invert select EPROM bit determines output polarity. The OE/ClK select multiplexer is used to
configure the mode of operation to Mode 0 or Mode 1 (see Figure 2). The feedback-select multiplexer enables
registered I/O (pin) or no feedback to the AND array.
If the JK or SR registers are selected, the 8 product terms are shared among two OR gates whose outputs
feed the two primary register inputs. The allocation of product terms for each register input is optimized by the
TI EPLD Development System. The invert select EPROM bit controls output polarity while the OE(CLK s.elect
multiplexer allows the mode of operation be Mode 0 or Mode 1. The feedback-select multiplexer enables
registered 1(0 (pin) or no feedback to the AND array.
Any 1(0 pin may be configured as a dedicated input by selecting no output and pin feedback. No output is
obtained by disabling the macrocell output buffer. In the erased state, 1(0 is configured for combinational
active-low output with input (pin) feedback.
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 76265
2-51
EP910
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
OE
I/O SELECTION
OUTPUT/POLARITY
FEEDBACK
Combinational/high
Combinational/low
Pin, None
None
Pin
Pin, None
Ie) COMBINATIONAL
SYNCHRONOUS
CLOCK
VCC
OE/CLK
SELECT
I/O SELECTION
OUTPUT/POLARITY
D Register/high
D Register/low
CLK
OE
None
o Register
None
Pin
FUNCTION TABLE
a
10
INPUTS
C1
~--------------------;R
Ib) 0-TYPE FLIP-FLOP
FIGURE 3_ I/O CONFIGURATIONS
2-52
TEXAS ~.
INSTRUMENTS
POST OFFICE BOX
6~5012
FEEDBACK
D Register, Pin, None
D Register, Pin, None
• DALLAS. TEXAS 75265
OUTPUT
a
CLR
CLK
0
L
t
L
L
L
t
H
H
L
Lor H
X
00
H
X
X
L
EP910
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SYNCHRONOUS
CLOCK
VCC
OE/ClK
SELECT
I/O SELECTION
FEEDBACK
OUTPUT/POLARITY
T Register/high
ClK
OE
T Register, Pin, None
T Register/low
T Register, Pin, None
None
T Register
None
Pin
FUNCTION TABLE
r------'Q
1T
C1
INPUTS
ClK
a
t
L
L
t
H
L
Lor H
H
X
X
X
00
00
Co
l
~-------------------;R
OUTPUT
T
ClR
L
(e) TOGGLE FLIP-FLOP
SYNCHRONOUS
CLOCK
VCC
OE/ClK
SELECT
I/O SELECTION
OUTPUT/POLARITY
FEEDBACK
JK Register/high
JK Register, None
OE
JK Register/low
JK Register, None
None
JK Register
...----.Q
C1
FUNCTION TABLE
ClR
L
L
l
L
l
H
K
OUTPUT
Q
L
l
00
L
H
L
H
L
H
H
H
00
X
X
X
X
00
INPUTS
ClK
J
t
t
t
t
Lor H
X
l
(d) J-K FLIP-FLOP
FIGURE 3. I/O CONFIGURATIONS (CONTINUED)
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. ;reXAS 75265
2-53
EP9tO
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SYNCHRONOUS
CLOCK
VCC
OE/ClK
SELECT
I/O SELECTION
OUTPUT/POLARITY
OE
FEEDBACK
SR Register/high
SR Register, None
SA Aegister/low
SA Register, None
None
SA Register
"'----'0
FUNCTION TABLE
OUTPUT
INPUTS
Cl
CLA
ClK
S
A
a
L
l
L
00
L
t
t
t
t
L
Lor H
H
X
X
L
L
l
H
L
H
L
H
H
H
Undefined
X
X
X
00
l
(el S-R FLIP-FLOP
FIGURE 3, I/O CONFIGURATIONS (CONTINUED)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) , , , , , , , , , , , .. , , , . , . , , , , , . , . , , , . , . , . , -0,3 V to 7 V
Instantaneous supply voltage range, Vee (t :s; 20 ns) , , , , , , , , , , , , . , , , , .... , , . , , , , -2 V to 7 V
Programming supply voltage range, Vpp , . , . , . , , . , , , . , , , . , , , , , , , , , . , ... ,. -0,3 V to 13,5 V
Instantaneous programming supply voltage range, Vpp (t :s; 20 ns) , . , ... , . , . , . , , .. , -2 V to 13.5 V
Input voltage range, VI, .. , .. , ..... , . , . , ................. , .. , . , ... , .... , -0.3 V to 7 V
Instantaneous input voltage range, VI (t :s; 20 ns) ........... , .... , . , ............ -2 V to 7 V
Vee or GND current ... , , , ......... , ............................. -250 mA to 250 mA
Power dissipation at 25°e free-air temperature (see Note 2) .................... , . . .. 1200 mW
Operating free-air temperature, TA ...................................... -65°e to 135°e
Storage temperature range ............................................ -65°e to 1500 e
NOTES: 1. All voltage values are with respect to GND terminal.
2. For operation above 25·C free-air temperature. derate to 144 mW at 135·C at the rate of 9.6 mWrC.
2-54
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
EP910
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
recommended operating conditions
EP9101
PARAMETER
Vee Supply voltage
Input voltage
VI
High-level input voltage
Vil
Vo
low-level input voltage (see Note 3)
Output voltage
tr
Rise time
tf
Fall time
TA
Operating free-air temperature
UNIT
MAX
MIN
MAX
4,5
5,5
4,75
5,25
V
Vee
Vee+ O,3
0,8
V
0
VIH
EP910C
MIN
2
-0,3
a
elK input
Other inputs
Vee
Vee+ 0,3
0,8
0
2
-0,3
0
Vee
50
Vee
100
50
elK input
100
100
100
70
50
50
Other inputs
-40
85
0
V
V
V
ns
ns
'e
Note 3: The algebraic convention, in which the more negative value is designated minimum, is used in this data sheet lor logic voltage levels
and temperature only,
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
EP9101
PARAMETER
TEST CONDITIONS
MIN
ITIl
leMOS
TYpt
EP910C
MAX
2.4
3,84
10H = -4mA
High-level output
voltage
VOL
low-level output voltage
10l - 4mA
0.45
II
Input current
VI - Vee or GND
10Z
Off-state output current
Vo = Vee or GND
ICC
Supply current
IStandby
~
ITurbo
ei
Input capacitance
Co
Output capacitance
eclk* Clock capacitance
VI = 0, 1= 1 MHz,
Vo = 0, 1= 1 MHz,
TA = 25'e
TA = 25'e
±10
±10
0,15
30
100
20
20
1=1 MHz,
TA = 25'e
20
I See Note 4
VI = Vee or GND,
ISee Note 5
No load
VI = 0,
I See Note 5
TYpt
MAX
2.4
3,84
VOH
10H = -2mA
MIN
0,02
6
45
UNfT
V
0,02
6
45
0.45
±10
±10
0,1
20
80
20
20
20
V
J.IA
J.IA
mA
pF
pF
pF
t All typical values are at Vee = 5 V, TA = 25'e,
* During programming, the clock capacitance of elK2 is 60 pF maximum,
NOTES: 4, When in the non-turbo mode, the device automatically goes into the standby mode approximately 100 ns after the last transition,
5, These parameters are measured with device programmed as a 16-bit counter, and I = 1 MHz,
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-55
EP910
HIGH· PERFORMANCE 24·MACROCELL
ERASABALE PROGRAMMABLE LOGIC DEVICE (EPLD)
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
combinational mode, turbo bit on
PARAMETERt
EP91 0-30
TEST CONDITIONS
tpdl
tpd2
tpzx
Input to nonregistered output
110 input to nonregistered output
tpxz
Input to output disable
CL - 5 pF,
tclr
tio
Asynchronous output clear time
CL- 35pF
MIN
CL=35pF
Input to output enable
See Note 6
EP91 0-35
MAX
MIN
EP91 0·40
MAX
MIN
MAX
UNIT
30
33
35
38
40
43
ns
ns
30
30
35
40
40
ns
35
33
38
43
ns
3
3
3
ns
1/0 input buffer delay
ns
combinational mode, turbo bit off
PARAMETERt
tpdt
ipd2
tpzx
EP91 0·30
TEST CONDITIONS
Input to nonregistered output
110 input to nonregistered output
MIN
EP91 0·35
MAX
MIN
60
CL = 35 pF
Input to output enable
tpxz
Input to output disable
CL - 5 pF,
lelr
tio
Asynchronous output clear time
CL=35pF
See Note 6
EP91 0·40
MAX
MIN
MAX
UNIT
70
73
ns
63
65
68
60
65
ns
ns
60
65
70
70
63
68
73
ns
3
3
3
ns
1/0 input buffer delay
ns
synchronous clock mode
PARAMETERt
EP91 0·30
TEST CONDITIONS
fmax Maximum frequency
Clock to output delay time
MIN
MAX
41.7
See Note 7
fcnt
Minimum clock period (register feedback to
register output)
Maximum frequency with feedback
See Note 5
See Note 5
MAX
EP91 0-40
MIN
MAX
32.3
37
leol
tcnt
EP91 0-35
MIN
MHz
18
21
24
30
35
40
33.3
28.6
UNIT
25
ns
ns
MHz
asynchronous clock mode
TEST CONDITIONS
PARAMETERt
f max
Maximum frequency
tac01
Clock to output delay time
tacnt
fcnt
See Note 7
EP91 0·30
MIN
MAX
33.3
ITurbo bit on
ITurbo bit off
Minimum clock period (register feedback to
register output)
Maximum frequency wtth feedback
33.3
EP91 0·35
MIN
MAX
31.3
EP91 0-40
MIN
MAX
29.4
UNIT
MHz
33
38
43
63
68
73
ns
30
35
40
ns
28.6
25
MHz
t Letter symbols for switching characteristics and timing requirements in this data sheet have been chosen for compatibility with those used in
other documentation previously prepared by another supplier for similar products. Any Similarity to symbols used on other TI data sheets or to
those shown in glossaries in TI data books is coincidental. The meanings may not be the same.
NOTES: 5. These parameters are measured with device programmed as a 16-bit counter, and f = 1 MHz.
6. This is for an output voltage change of 500 mV.
7. The f max values shown represent the highest frequency of operation without feedback.
2-56
TEXAS •
INSTRUME:NTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
EP910
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
timing requirements over recommended ranges of supply voltage and free-air temperature
synchronous clock mode
TEST
CONDITIONS
PARAMETERt
tsu
Input setup time
th
Input hold time
ITurbo bit on
ITurbo bit off
EP91 0-30
MIN
MAX
EP91 0-35
MIN
MAX
EP91 0-40
MIN
24
27
31
54
57
61
0
0
0
MAX
UNIT
ns
ns
tch
Clock high pulse duration
12
13
15
ns
tcl
Clock low pulse duration
12
13
15
ns
asynchronous clock mode
TEST
CONDITIONS
PARAMETERt
tasu
Input setup time
tah
Input hold time
ITurbo bit on
ITurbo bit off
EP91 0-30
MIN
MAX
EP91 0-35
MIN
MAX
EP91 0-40
MIN
10
10
10
40
40
40
15
15
15
MAX
UNIT
ns
ns
tach
Clock high pulse duration
15
16
17
ns
tacl
Clock low pulse duration
15
16
17
ns
t letter symbols for sWitching characteristics and timing requirements In thiS data sheet have been chosen for compallbility with those used In
other documentation previously prepared by another supplier for similar products. Any similarity to symbols used on other TI data sheets or to
those shown in glossaries in TI data books is coincidental. The meanings may not be the same.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-57
EP910
HIGH· PERFORMANCE 24·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
functional testing
The EP91 0 is functionally tested including complete testing of each programmable EPROM bit and all internal
logic elements thus ensuring 100% programming yield. As a result, traditional problems associated with fuseprogrammed circuits are eliminated. The erasable nature of the EP910 allows test program patterns to be
used and then erased.
Figure 4 shows the dynamic test circuit and the conditions under which dynamic measurements are made.
. Because power supply transients can affect dynamic measurments, simultaneous transitions of multiple
outputs should be avoided to ensure accurate measurement. The performance of threshold tests under
dynamic conditions should not be attempted. Large-amplitude fast-ground-current transients normally occur
as the device outputs discharge the ,load capacitances. These transients flowing through the parasitic
inductance between the device ground terminal and the test-system ground can create significant reductions
in observable input noise immunity.
,------vcc
DEVICE _ _- -...- -....-TO
OUTPUT
TEST SYSTEM
340 !l
Cl t
t Includes jig capacitance
FIGURE 4. DYNAMIC TEST CIRCUIT
design security
The EP91 0 contains a programmable design security feature that controls the access to the data programmed
into the device. If this programmable feature is used, a proprietary design implemented in the device cannot
be copied or retrieved. This enables a high level of design control to be obtained since programmed data
within the EPROM cells is invisible. The bit that controls this function, along with all other program data, may
be reset by erasing the device.
turbo bit
Some EPLDs contain a programmable option to control the automatic power-down feature that enables the
low-stand by-power mode of the device. This option is controlled by a turbo bit that can be set using the TI
EPLD Development System, When the turbo bit is on, the low-stand by-power mode is disabled, This renders
the circuit less sensitive to Vee noise transients created by the power-up/power-down cycle when operating
in the low-power mode. The typical lee versus frequency data for both the turbo-bit-on mode and the turbobit-off (low power) mode is shown in Figure 5. All dynamic parameters are tested with the turbo bit on. Figure 6
shows the relationship between the output drive currents and the corresponding output voltages,
2-58
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
EP910
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SUPPLY CURRENT
OUTPUT CURRENT
vs
vs
MAXIMUM FREQUENCY
OUTPUT VOLTAGE
100
100
TURBO BIT ON
1
-"
~
20
:;
10
!!
:;
u
~
Ii
F.
70 fvee - 5 V~
25°e-
TURBO BIT OFF
§-
Ih
~
7
I
4
-IOL
-~-v:::
I
-.......
~H
0
I
~
0.1
~
Vee - 5 V
TA - 15°e
rTIlil
0.01
100
'\
9
WJIll
1 k
10 k 100 k 1 M 10 M 100 M
fmax-Maximum Frequency-Hz
\
..
_\
2
1
\
o
FIGURE 5
-
2
3
4
VO-Output Voltage-V
5
FIGURE 6
If the design requires low-power operation, the turbo bit should be (disabled) off. When operating in this
mode, some dynamic parameters are subject to increases.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-59
EP910
HIGH-PERFORMANCE 24-MACROCELL
ERASAB~E PROGRAMMABLE LOGIC DEVICE (EPLD)
X
INPUT OR 110
-----------------,~---------------~tpd---+i
\:1'''---------
COMBINATIONAL
OUTPUT ______________________~I~--.------'~
If--tpxz~
,.--=::.;.:;-.:==;;.;;---I
COMBINATIONAL OR
),
VALID OUTPUT
REGISTERED OUTPUT ______________________
~-------:
HIGH-IMPEDANCE STATE
!.--tPZX--+\
COMBINATIONAL OR _________H.,I_GH;.;.-_IM_P,;;E_D_AN;.;.C;,;E;;.S;,.T;.;.A;.;.T_E_______',__________--t:K--V-A-l-ID--O-UT-P-U-T---REGISTERED OUTPUT
•
j4--tcl'~
REGISTERED OUTPUT _____________________________________
~
ASYNCHRONOUSLY
__'I\'-__.;:C;:;:lE:;::A;:.R:.;O~U~T~P,;;;U.;.T_ _
lal COMBINATIONAL MODE
I4-- t ch----'
~II\.,
/
--' tf le-tcl-.l
'!I
''!Ie/
~
ClK', ClK2 - - - /
~ t, 14-I4-tsu-+r-th---.l·
INPUTORIIO~ VALID
~I".~~~~..,.,..,.,..,.,..,.,..,.,..,.,..,.,.,.,.,.,~
I
!4-- tco,---+I
REGISTERED OUTPUT
Xlr------------------
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
•
_
VALID OUTPUT
Ibl SYNCHRONOUS CLOCK MODE
REGISTERED OUTPUT
____________________Xlr------------~---------•
leI ASYNCHRONOUS
•
C~OCK
FIGURE 7. SWITCHING WAVEFORMS
2-60
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
VALID OUTPUT
MODE
EP910
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
MECHANICAL DATA
4O-PIN CERAMIC DIP (COIP)
WINDOW
8.9 10.3501 NOM DIA
r-
15.7 10.6201
13.010.5101
~~rrr~rrrTI<~~~~"~"~~
2.510.0981 MAX
16.00 10.6301
1499105901
j
I---
r
5.710.2251
4.610.1801
~
! I,., \_sp:. .=:E~=~=-G
---L-1-
~ ~:
~. .
r-
r"'~
~(J3~Oi
0.3810.0151
3.210.1251
0.20 10.0081
-J I.-
PIN 1
1.6510.0651
0.97 10.0381
0.13 10.0051
MIN~ ~
53.2 12.0961 MAX
U-
Jl
2.5410.1001
"I
~
0.51 10.0201
0,4110.0161
1.7810.0701
0.38 10.0151
Bse
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
40-PIN PLASTIC DIP (PDIP)
15,37 (0.6051
s~
~
'''''~~~l:::::::=:-:::::::]
"" 'r
1
tL
3.94(0.155)
,,~:M
;;:;:N:·
5371
14-1·---------~:~~:~;::~:-;:~"'::::~~:::~c:.- - - - - - - - - - > 1 :.~: :~:~::
]r-----------------------
u
~LO.51NI!~201
~
f
3,3010,1301
3,05 to., 20)
0,30 10.012)
16.26 (0.640)
15.49 (0.610)
0.20 10.0081
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
2-61
EP910
HIGH-PERFORMANCE 24-MACROCELl
ERASABLE PROGRAMMABLE lOGIC DEVICE (EPLD)
MECHANICAL DATA
44-PIN CERAMIC LEADED CHIP CARRIER (CLCCI
BOTTOM VIEW
1,2710.060)
sse
1
r
TOP
1.02 (0.040))145°
NO M
VIEW
GLASS
~INDOW
7.11 10.280) R NOM
·~n ~
I
~
17,40 10.885)
16.6610.656) [
16.00 10.630)
lJ ,. 6610.6561=1~
t=
'-' '-'
~12'70REF10.5001---.1
~
'-'
'-'
,~
16,00 (0.630)
~:~: :~:~;::
J
17.65 (0.6951
R
17.40 10.685)
0.25 (0.0101
0,15 10.0061
-----.t
~k
0,53 (0.021,
0,43 10.0171
•
0,66 (0.026)
DETAil "PO'
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
2-62
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
EP910
HIGH-PERFORMANCE 24-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
MECHANICAL DATA
44-PIN PLASTIC LEADED CHIP CARRIER (PLCCI
SEE DETAil "8"
~
/
/
I
b
L~
~
1,22
l~
, 6,00 (0.6301
D
h
~
I
16'6610'6561~
16,51 (0.6501
17,65 (0.6951
17,40 (0.6851
)1
J-
17.40 (0.685)
16,6610.6561
16,51 (0.6501
1,14(0.0451 R
0,64 (0.0251
', /
l!t
O'5110'0201 MIN
'I
----l
3.05 IO.,201
2,29 (0.0901
0.64 (0.0251
MIN
4.57 (0.1aOI
4.19 (0.1651
[O'0481~ 0.254 [0.010)
1,07 (0.0421
0.203 (0.008)
~
-
I
~
r-----
1.22 10.0481
1,07 (0.0421
•
0,53 (0.021)
0,41 (0.0161
f
*T
0,81 10.0321
0,66 (0.0261
DETAIL "S"
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TEXAS 75265
2-63
-
2-64
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
03232, FEBRUARY 19S9-REVISED AUGUST 1999
• Erasable, User-Configurable LSI Circuit
Capable of Implementing 2100 Equivalent
Gates of Conventional and Custom Logic
CHIp· CARRIER PACKAGE
(TOP VIEW)
• Speed Equivalent to 74LS TIL with 33-MHz
Clock Rates
9 8765432 1 68 67 66 6564636261
110
I/O
I/O
110
INPUT
INPUT
INPUT
• Virtually Zero Standby Power •.. 35 fLA Typ
• Active Power of 250 mWat 5 MHz
• Programmable Clock Option Allows
Independent Clocking of All Registers
• Forty-eight Macrocells with Configurable
I/O. Architecture Allowing Up to 64 Inputs or
48 Outputs
ClKl
VCC
CLK2
10
11
12
13
14
15
16
17
18
19
INPUT
INPUT
INPUT
20
1/0
23
24
25
26
• Accepts TIL S51 and MSI Based
Macrofunction DeSign Inputs
110
110
110
• TIL/CMOS I/O Compatibility
• 100% Generically Testable - Provides
100% Programming Yield
0
21
22
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
110
I/O
ItO
110
INPUT
INPUT
INPUT
ClK4
vcc
ClK3
INPUT
INPUT
INPUT
I/O
I/O
110
I/O
n~R~~~~M~~D~~~~ac
g~~ggggg~~~gggggg
'"
• CAD Support from the TI EPLD
Development System Featuring Schematic
Capture Design Entry with Extensive
Primitive and Macrofunction Libraries
• Packaged in a 68-Pin J-Leaded, Ceramic
(with Window) and Plastic (One-Time
Programmable) Chip Carrier
AVAILABLE OPTIONS
PACKAGE TYPE
TA
SPEED
CERAMIC
PLASTIC
RANGE
CLASS
CHIP CARRIER
CHIP CARRIER
(CLCC)
(PLCC)
35 ns
EP1810JC·35
EP1810LC·35
45 ns
EP1810JC·45
EP1810LC·45
45 ns
EPI810J)·45
EP1810Ll·45
O°C to 70°C
-40°C to 85°C
description
The EP1810 series of CMOS EPLDs from Texas Instruments offer LSI density, TIL equivalent speed
performance and low power consumption. Each device is capable of implementing over 2100 equivalent
gates of SSI, MSI and custom logiC circuits. The EP1810 series is packaged as a 68-Pin J-Leaded Chip
Carrier, and is available in ceramic (erasable) and plastic (one-time programmable) versions.
The EP181 0 series is designed as an LSI replacement for traditional low-power Schottky TTL logic circuits, Its
speed and density also make it suitable for high-performance complex functions such as dedicated
peripheral controllers and intelligent support chips. Integrated-circuit count and power requirements can be
reduced by several orders of magnitude allowing similar reduction in total size and cost of the system, with
significantly enhanced reliability.
PRODUCTIOII DATA do.umlnll 00.111. informllio.
..mnt II of pulllicotio. dOle. Products .onform 10
specifications par the terms of TaXIS Instruments
:=:~~i;ar.!:I'i =:~ti:r :.~o::~:~9t::.s not
Copyright
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
o- ~ ::v=(t:
II
l
~I~~l
: . D D-l:V =(to l
I
II
0
J
0
c
I.
I
0
Kc
Y:[>-II
I
II
II
II
IIp-~
~
L__
__-1
O
I
II
c
RC
I
IL ____________ II ____________ I
~L
~L
_______
~
FiGURE 1. MACROCELL COMPONENTS
Typical logic functional implemented into a single macrocell. Each EP1810 macrocell can accommodate the
equivalent of 40 gates.
FROM OTHER
MACROCELLS
EP1Sl0
INPUTS
I
•
r,
---------,,
':;;G-;
ARRAV
LOAo-=-I----4~-----~
I
I
I
ENT
I/O PIN
ENP-.-.
~
OATAO--'-----I---------l_~
x>--+----'
L _________________________
CLEAR-+----+-----------------I
~
TO OTHER
MACROCELLS
EQUIVALENT GATES - 40
FIGURE 2. SAMPLE CIRCUIT
2-68
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 76265
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
The EP1810 macrocell architecture is shown in Figures 3 and 4. There are 32 macrocells called local
macrocelis. These macrocelis offer a multiplexed feedback path (pin or internal) which drives the local bus of
the respective quadrant.
There are another 16 macrocelis known as the global macrocells (see Figure 4). These global macrocells
have features that allow each macrocell to implement buried logic functions and, at the same time, serve as
dedicated input pins. Thus, the EP181 0 may have an additional 16 input pins giving a total of 32 inputs. The
global macrocells have the same timing characteristics as the local macrocelis.
•
II ~lOCAL
GLOBAL BUS
QUADRANT
SYNCHRONOUS
CLOCK
BUS----.
V
OE/CLOCK
:;;=
LSELECT
OE
-D£~
DE/eLK
L-~1
is"
i ,
').-
0
~
~
~
t;
5
f
CLK
2
~}~}-
3
4
5
~-
I/O
ARCHITECTURE
CONTROL
r-{>r---
~
~
6
CLEAR
'r • .• if
t
t
'--v--'
GLOBAL
OEDICATED
INPUTS
t16INPUTS)
'
~
.. . . .
...
•
L
-D-LOCAL BUS
'--.r-----1
QUADRANT
A. B. C. D
GLOBAL
FEEDBACK
('6 MACROCELLSI
'--v---"
QUADRANT
LOCAL
FEEOBACK
(12 MACROCEllS)
r::l-
FEEDBACK'i"
SELECT
I
FIGURE 3. LOCAL MACROCELL LOGIC ARRAY
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
2-69
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
QUADRANT
SYNCHRDNOUS
CLOCK
_ - - - - G L O B A L B U S - - - - -.... _ L O C A L BUS---+
CLOCK
v
t..SELECT
OE
S~T
r;=
-rn:::~
OEICLK
-<>-r-2L
~~'--1 [<
©
.,
m 01
i=}--
~
i=}-~
~
Fe}--
...
2
i!
~
5
6
CLEAR
CLK-.Qp
r
110
ARCHITECTURE
CONTROL
r1>r---
r=rJ-
o
0
0
r
l ~
0
0
0
0
Or
'--v------I
GLOBAL
DEDICATED
INPUTS
(16INPUTSI
QUADRANT
A.B.C. D
GLOBAL
FEEDBACK
{16 MACROCELLSI
-D--
f
0
0
o
L:l.
O
LOCAL BUS
GLOBAL BUS
~
'----y-----J
QUADRANT
LOCAL
FEEDBACK
(12 MACROCELLSI
FIGURE 4. GLOBAL MACROCELL LOGIC ARRAY
clock options
Each of the EP181 0 internal flip-flops may be clocked independently or in user defined groups. Any input or
internal logic function may be used as a clock. These clock signals are activated by driVing the flip-flop clock
input with a clock buffer (CLKB) primitive. In this mode, the flip-flops can be configured for positive or negative
edge triggered operation.
Four dedicated system clocks (CLK1-CLK4) also provide clock signals to the flip-flops. System clocks are
connected directly from the EP181 0 external pins. With this direct connection, system clocks give enhanced
clock to output delay times than internally operated clock signals. There is one system clock per EP1810
quadrant. When using system clocks, the flip-flops are positive edge triggered (data transitions occur on the
rising edge of the clock) .
. macrofunction.s
The macrofunctions shown in Figure 5 allow the circuit designer to use popular TTL SSI and MSI building
blocks. Many macrofunctions are standard TTL circuits such as counters, comparators, multiplexers,
decoders, shift registers, etc. and are identified by their familiar TTL part numbers. Macrofunctions are
constructed by combining one or more macrocells. These high-level function blocks may be combined with
low-level gate and flip-flop elements to produce a complete logic design.
An automatic function built into the TI EPLD Development System ensures that the use of macrofunctions
causes no loss of deSign efficiency. The development system analyzes the complete logic schematic and
automatically removes unused gates and flip-flops from any macrofunction employed. This MacroMunching'·
process allows the logic designer to employ macrofunctions without the problems of optimizing their use.
MacroMunching is a trademark of ALTERA Corporation .
2-70
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 76265
EP1810
HIGH-PERFORMANCE 48;MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
All inputs to macrofunctions are designed with intelligent-default input signal levels (VCC or GND). Normally
active high and low signals or unused inputs can simply be left unconnected, further improving productivity
and reducing the burden placed on the designer.
Macrofunctions are TTL compatible SSI and MSI circuits giving the circuit deSigner a high-level approach to
EPLD design. Macrofunctions include input default values to unconnected inputs and MacroMunching'· to
unused outputs. The macrofunction library consists of over 100 components.
74162 FUNCTION TABLE
ACTIVE lOW
SOGN . .
~
I - - - - ;';,:;; - ~ MACROFlINCTION
NAME
vccl
~C:
CLRN
I
I
Vee
Vee
GNO:
CK
:
i L__________ ~--,
I
DEFAULT VALUES
NUMBER OF MACRO
CELLS USED BY THE
OUTPUTS
INPUTS
LON
CLRN
ENP
I
I
X
L
L
H
X
X
I
H
H
X
X
X
I
H
H
L
X
I
I
H
H
H
H
H
H
H
H
CK
RCO
ENT 0 C B A
d
c
b a
~
L
.I.
L
HO~D
I~
1~
bOUNT
HOLD COUNT
COUNT UP
H
t
L
t
L
t
H
L
L
L
L
L
H
H = high level (steady state)
L = low level (steady state)
X = don't care (any input including transitions)
= transition from low to high level
a.b,c,d = level of steady state input at inputs A,B,C,D
...r
FIGURE 5. MACROFUNCTION SYMBOL
design libraries
Texas Instruments provides both primitive and macrofunction libraries within the EPLD Development System.
These libraries are used with the LogiCaps ,. schematic capture design entry to specify the logiC. Elements
from both libraries may be used in the same deSign, allowing full utilization of the EP181 0 resources.
primitive. library
The primitive library consists of 80 low-level logic gates, flip-flop, and I/O symbols. See section on primitive
library in the A+ PLUS" reference guide. Basic gates provided are AND, OR, NAND, NOR, Exclusive OR and
NOR, and NOT functions. De-Morgan's inversion (bubble input) of each gate is included. These logic gates
have a maximum of 12 inputs. Larger gates may be constructed by chaining primitives together. Flip-flops in
the form of D,T,JK and SR types are supplied. Each flip-flop has asynchronous clear capability. To connect
signals to external pins, input and 3-state I/O buffers are available. For the deSigner's convenience,
compound primitives that combine register and I/O buffers, are also supplied.
macrofunction library
The development system macrofunction library encompasses over 100 high-level building blocks that can
greatly increase design productivity. See the ADLlB'· and TTL macrofunctions manual that comes with the
development system. The library contains the most commonly used TTL SSI and MSI functions. In addition, a
number of more specialized macrofunctions have been added. These blocks perform logic functions in an
optimum manner for EPLD implementation. They include counters implemented with toggle flip-flops, inhibit
gates, combinational shift-registers/counters and a variety of useful logic structures not found in standard TTL
devices.
LogiCaps is a trademark of ALTERA Corporation.
A+PLUS is a trademark of ALTERA Corporation.
ADUB is a trademark of ALTERA Corporation.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-71
EP1810
HIGH.PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
starting a design
To get started on an EP181 0 design the following sequence of preliminary steps is suggested. The equations
given will help estimate how to build your system with EP1810s.
partitioning
Partition the complete system into functional blocks. Major functional blocks may be expressed in standard
MSI TTL form for integration within the EP181 O. Should the design require a multiple EPLD solution, the 1/0
connections which interface between the EPLDs should be minimized. The complete schematic should be
structured as a set of subsystems such as counters, shift registers, comparators, etc., to allow easy design
entry.
timing specifications
Knowledge of the base-clock frequency and critical-timing paths are necessary to make the correct choice of
EPlDs. The EP181 0 series can support circuits operating up to 33 MHz. Critical-timing paths are determineq
based upon input buffer, logic array, and output buffer delays. See switching characteristics. Smaller EPLDs,
such as the EP910 or EP610, can be used for circuits that demand higher speed requirements on critical
paths.
estimating a fit
To estimate the amount of logic that will fit into an EP1810, the number of input and output pins and the
number of macrocells must be specified.
To estimate the number of macrocells, determine the number of buried flip-flops (flip-flops that do not drive
output pins) and the number of macrocells used by macrofunctions. Since basic gates are implemented
within the logic array, they usually do not require an entire macrocell. Therefore, they may be safely ignored in
the estimation.
Each member of the macrofunction library has a maximum number of macrocells used to build the function.
This number is shown in the lower right hand corner of the symbol. Refer to the ADLlB'· and TTL
macrofunction manual to determine how many macrocells each macrofunction requires. Note that some
macrofunctions have no macrocell specification. These functions use only a portion of the logic array, thus
other logic coOld be added before the entire macrocell is used.
esUmation formula
The estimation formula is as follows:
1. Determine the number of output pins = OP
2. Determine the number of input pins = IP (if less than 16 enter zero)
3. Determine the number of macrocells = BFF + MR where: BFF = buried flip-flops and MR
function reqUirements.
=
macro-
If OP + IP + BFF + MR < 48, the design will mostlikely fit into an EP181 O. Complete the design using the TI
EPLD Development System.
2-72
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TeXAS 75265
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) ............... . . . . . . . . . . . . . . . . . . .. -0.3 V to 7 V
Instantaneous supply voltage range, Vee (t :s; 20 ns) . . . . . . . . . . . . . . . . . . . . . . . . . .. -2 V to 7 V
Programming supply voltage range, Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 13.5 V
Instantaneous programming supply voltage range, Vpp (t :s; 20 ns) ............... -2 V to 13.5 V
Input voltage range, VI ............................................... -0.3 V to 7 V
Instantaneous input voltage range, VI (t :s; 20 ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -2 V to 7 V
Vee or GND current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -400 mA to 400 mA
Power dissipation at 25°e free-air temperature (see Note 2) .. . . . . . . . . . . . . . . . . . . . . . .. 2000 mW
Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°e to 135°e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°e to 1500 e
NOTES: 1. All voltage values are with respect to GND terminal.
2. For operation above 25'C free-air temperature. derate to 240 mW at 135'C at the rate 01 16 mWrC.
recommended operating conditions
VCC
VI
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage (see Note 3)
Va
Output voltage
Rise time
MAX
MIN
MAX
4.5
5.5
4.75
5.25
V
vCC
VCC+0.3
0.8
V
0
2
-0.3
VCC
VCC+0.3
0.8
a
Fall time
TA
Operating free-air temperature
0
2
0.3
a
VCC
50
CLK input
tf
UNIT
MIN
Input voltage
tr
EP1810C
EP18101
PARAMETER
VCC
100
Other inputs
50
100
CLK input
50
100
Other inputs
50
-40
100
85
0
70
V
V
v
ns
ns
·C
NOTE 3: The algebraic convention, in which the more negative value is designated minimum, is used in this data sheet for logic voltage levels
and temperature only.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
High-level
VOH output voltage
ITIL
ICMOS
TEST CONDITIONS
10H - -4mA
2.4
10H = -2mA
3.84
VOL
II
Low-level output voltage
10L = 4mA
Input current
10Z
Off-state output current
ICC
Supply current
I Standby
INon-turbo
ITurbo
EP18101
Min
TYpt
EP1810C
MAX
MIN
TYpT
MAX
2.4
UNIT
V
3.84
0.45
0.45
V
VI - VCC or GND
~10
±10
J.lA
Va - VCC or GND
±10
±10
J.lA
VI = VCC or GND,
No load
ISee Note 4
ISee Note 5
JSee Note 5
0.035
0.15
0.035
0.15
10
40
10
30
100
240
100
180
mA
Ci
Input capacitance
VI- O.
1 -1 MHz,
TA - 25'C
20
20
pF
Co
Output capacitance
va =0,
f= 1 MHz.
TA = 25'C
20
20
Cclk
Clock capacitance
VI = 0,
1= 1 MHz.
TA = 25'C
25
25
pF
pF
t All typical values are at VCC = 5 V. TA = 25'C.
NOTES: 4. When in the non-turbo mode. the device automatically goes into the standby mode approximately 100 ns after the last transition.
5. These parameters are measured with device programmed as four 12-bit counters and f
1 MHz.
=
INSTRUMENlS
TEXAS "
POST OFFICE BOX 656303 • DALLAS, TEXAS 75265
2-73
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
turbo-bit on
PARAMETERt
TEST CONDITIONS
tpd1(tot)
Input to nonregistered output delay
.tpd2(tot)
tin
I/O input to nonregistered output delay
Input pad and buffer delay
tio
I/O input pad and buffer delay
tlad
Logic array delay
tad
tpzx
Output buffer and pad delay
Output buffer enable time
tpxz
Output buffer disable time
EP1810-35
MIN
CL = 35 pF
CL = 35 pF
CL - 5 pF,
See Note 6
MAX
EP1810-45
MIN
MAX
UNIT
35
45
ns
40
7
50
ns
7
ns
5
19
5
27
ns
ns
9
11
ns
9
11
ns
9
11
ns
turbo-bit off
PARAMETERt
tpd1(tot)
tpd2(tol)
tin
Input to nonregistered output delay
Input pad and buffer delay
tio
I/O input pad and buffer delay
TEST CONDITIONS
I/O input to nonregistered oulput delay
tlad
Logic array delay
tad
tpzx
Output buffer and pad delay
Output buffer enable time
tpxz
Output buffer disable time
CL=35pF
CL=35pF
CL - 5 pF,
See Note 6
EP1810-35
EP1810-45
MIN
MIN
MAX
MAX
UNIT
75
ns
ns
7
80
7
5
5
ns
49
57
11
ns
9
9
11
ns
ns
9
11
ns
65
70
ns
t Letter symbols for switching characteristics and timing requirements in this data sheet have been chosen for compatibility with those used in
other documentation previously prepared by another supplier for similar products. Any similarity to symbols used on other TI data sheets or to
those shown in glossaries in TI data books is coincidental. The meanings may not be the same.
NOTE 6: This capacitance is for an output voltage change of 500 mY.
2-74
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75266
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
synchronous/asynchronous clock mode, turbo-bit on
PARAMETERt
TEST CONDITIONS
f max Maximum frequency
Register set-up time
tsu
th
leh
lei
tic
See Note 7
EP1811l-35
MIN
MAX
EP1810-45
MIN
MAX
UNIT
40
33.3
10
11
ns
Register hold time
15
18
Clock high pulse duration
Clock low pulse duration
12
12
15
15
ns
ns
Clock delay
MHz
19
27
ns
ns
tics
System clock delay
4
Feedback delay
6
8
7
ns
tfd
tclr
24
32
ns
Register clear time nonregistered output
tcnt
Minimum clock period (register output feedback to
register input-internal data)
fcnt
Maximum frequency with feedback
45
35
See Note 5
22.2
28.6
ns
ns
MHz
synchronous/asynchronous clock mode, turbo-bit off
PARAMETERt
TEST CONDITIONS
fmax Maximum frequency
Register set-up time
tsu
th
tch
tcl
tic
See Note 7
EP1810-35
MIN
MAX
EP181 0-45
MIN
MAX
UNIT
40
33.3
11
Register hold time
10
15
18
ns
Clock high pulse duration
12
15
ns
Clock low pulse duration
12
Clock delay
tics
System clock delay
tfd
Feedback delay
tcl r
Register clear time nonregistered output
tcnt
Minimum clock period (register output feedback to
register input-internal data)
fcnt
Maximum frequency with feedback
15
28.6
ns
49
57
ns
4
-24
8
-23
ns
ns
54
62
ns
45
35
See Note 5
MHz
ns
22.2
ns
MHz
t Letter symbols for switching characteristics and timing requirements in this data sheet have been chosen for compatibility with those used in
other documentation previously prepared by another supplier for similar products. Any similarity to symbols used on other TI data sheets or to
those shown in glossaries in TI data books is COincidental. The meanings may not be the same.
NOTES: 5. f max is measured with device programmed as four 12-bit counters.
7. The f max values shown represent the highest frequency of operation without feedback.
B. The negative number shown for this specification is to compensate for the 30 ns that is being added to the tlad parameter in the
turbo·bit off mode. In the non-turbo mode, tfd is not affected by the additional propagation delay because the logic array is already
taken out of the non-turbo mode by the first transition into the array. See section on EPLD delay elements.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-75
EP1810
HIGH·PERFORMANCE 48·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
functional testing
The EP1810 is functionallly tested including complete testing of each programmable EPROM bit and all
internal logic elements thus ensuring 100% programming yield. As a result. traditional problems associated
with fuse-programmed circuits are eliminated. The erasable nature of the EP1810 allows test program
patterns to be used and then erased.
Figure 6 shows the dynamic test circuit and the conditions under which dynamic measurements are made.
Because power supply transients can affect dynamic measurements. simultaneous transitions of multiple
outputs should be avoided to ensure accurate measurement. The performance of threshold tests under
dynamic conditions should not be attempted. Large-amplitude fast-ground-current transients normally occur
as the device outputs discharge the load capacitances. These transients flowing through the parasitic
inductance between the device ground terminal and the test-system ground can create significant reductions
in observable input noise immunity.
...------vcc
DEVICE _ - ._ _......_ _...._TO
OUTPUT
TEST SYSTEM
340
[l
t Includes jig capacitance
FIGURE 6. DYNAMIC TEST CIRCUIT
design security
The EP1810 contains a programmable design security feature that controls the access to the data
programmed into the device. If this programmable feature is used. a proprietary design implemented in the
device cannot be copied or retrieved. This enables a high level of design control to be obtained since
programmed data within the EPROM cells is invisible. The bit that controls this function. along with all other
program data. may be reset by erasing the device.
turbo bit
Some EPLDs contain a programmable option to control the automatic power-down feature that enables the
low-standby-power mode of the device. This option is controlled by a turbo bit that can be set using the TI
EPLD Development System. When the turbo bit is on. the low-standby-power mode is disabled. This renders
the circuit less sensitive to Vee noise transients created by the power-up/power-down cycle when operating
in the low-power mode. The typical ICC versus frequency data for both the turbo-bit-on mode and the turbobit-off (low power) mode is shown in Figure 7. All dynamic parameters are tested with the turbo bit on.
Figure 8 shows the relationship between the output drive currents and the corresponding output voltages.
Figures 7 and 8 show the ICC vs f max • and output current vs output voltage.
2-76
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SUPPLY CURRENT
vs
MAXIMUM FREQUENCY
0.1 L..J...u..uJILLllJ..Lllll....l...IJ.WIII-L.llLWL.!.UJ.UIIL...l...I.wJII
100
1 k
10 k 100 k
1 M 10 M 100 M
fmax-Maximum Frequency-Hz
FIGURE 7
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
100
70
c(
Vee
e
40
l!!
SCo
S
0
I
IOL
L
20
I
:;
CJ
.
~
E
~I:
5 V
TA - 25°e
10
-..........
~
7
"\
4
9
\
2
1
o
2
3
4
VO-Output Voltage-V
5
FIGURE 8
If the design requires low-power operation, the turbo bit should be off (disabled). When operating in this
mode, some dynamic parameters are subject to increases.
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75266
2-77
EP1810
HIGH·PERFORMANCE 48·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
SYSTEM CLOCK DELAY
tics
INPUTS
CLOCK DELAY
INPUT
DELAY
INPUTS
tin
tic
LOGIC ARRAY DELAY
tlad
REGISTER
DELAY
OUTPUT
DELAY
'su
'h
'hs
'od
1/0
'"'.x
REGISTER CLEAR DELAY
telr
1/0
1/0
FEEDBACK
DELAY
INPUT
DELAY
'Id
tjo
NOTE: For combinatorial outputs, the delay between the logic array and the output buffer is zero. (i.e., tsu
FIGURE 9. EPLD MACROCELL DELAY PATHS MODEL
2-78
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655:i03 • DALLAS. TEXAS 75265
=0
or th
= 0)
EP1810
HIGH· PERFORMANCE 48·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE
INPUT MODE
I+--'!- tio
I/O
PIN-----.*I..~:.-----------------
j+tin-tl
INPUT PIN
---,"""","\\:/'
I'\.
I
--------~ ~~---------------------------I..--tlad
LOGIC ARRAY INPUT
-'
--------~I
l!\
:
----------~I'----------~·~-------------
.I
r-tclr
LOGIC ARRAY OUTPUT
\,LI
I'\.
-----------------------~ ~-------------CLOCK MODE
tr .....
I
_tch_
j4--tcl~
I
I
I
~tin-tf
~
CLOCK INTO LOGIC ARRAY
:;
\1
V
CLOCK PIN
t iC
\
---4
OATA FROM LOGIC ARRAY
~
"-
/
\
r--
*
\'---
j+-ts~£th
~ !~
CLOCK FROM LOGIC ARRAY
--.. ~tf
j+"-tfd--tl
REGISTER OUTPUT TO
LOGIC ARRAY
SYSTEM CLOCK MODE
SYSTEM CLOCK PIN
tin
SYSTEM CLOCK
AT REGISTER
DATA FROM
LOGIC ARRAY
\ ......----'/
/
----~
-tt--tf
:
1-1- tics
V~----~\~
1
I+-t.U~th
____~/
\.
w _ _':k~--------------------~I1'\.\..
__
OUTPUT MODE
CLOCK FROM
/
LOGIC ARRAY ________~
\
/
,,'-______....
~tod_tf
L~:.~A~~~~ ==x::=)(
:
I
'0.
tpxz.....
_____________.......... 1 _____---L)!4__---.!,
OUTPUT PIN
X
X_......-__
_
~tpzx
1
...
,,----
)HIGH3~:;:~:NCE(L....-__
tpd IItot) - tin + tlad + tad
tpd2ltot) - tlo + tin + !tad + tad
FIGURE 10. SWITCHING WAVEFORMS
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS, TEXAS 76285
2-79
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
understanding EPLD timing characteristics
introduction
One of the most important benefits of using an EPLD in any design is the integration of complex logic
functions into single chip solutions in most cases. However. when the functional compatibility of a design has
been determined. timing analysis should be completed to ensure AC parameter compatibility.
The purpose of this applications supplement is to discuss the timing delays which exist in the TI EPLDs. The
focus here is on the Inherent delay paths that exist in every EPLD and their relation to the data sheet switching
specifications. This should aid designers in modelling and simulating their logic designs.
gate delays vs EPLD timing characteristics
Accurately modelling the timing characteristics requires an understanding of how a given application is
implemented within the EPLD. Most designs targeted for EPLDs contain basic gates. and TTL
macrofunctions. which are emulated by the EPLD general macrocell structure. The macrocell structure is an
array of logic in an AND/OR configuration with a programmable inversion followed by an optional flip-flop and
feedback. (See Figure 11):
When designing with EPLDs. the term "gate delay" is not a useful measure. Within the EPLD AND array are
product terms. A product term is simply an n-input AND gate where n is the number of connections.
Depending on the logic implemented. a single product term may represent one to several gate equivalents.
Therefore. gate delays do not necessarily provide EPLD timing characteristics.
DEDICATED
FEEDBACK
SIGNALS
INPUTS
",,'~~~
J~7~7~7~7
7\4~ 7J~~7 7~\4
"" ""
~ ~ ~
~ ~ ~
g
-p-QQQQ-
-p-
OPTIONAL
FIXED
INveRTER
~¥r
PROGRAMMABLE
OPTIONAL
REGISTER
I
INVERSION
CONTROL
G~D
FEEDBACK
MUX
I
BIT
FEEDBACK
TO OTHER
MACRQCEllS
AND GATES
FIGURE 11. EPLD MACROCELL
AND/OR/INV structure
The AND portion consists of a column of AND gates, each of which has a very large number of possible inputs
selected by EPROM bits. The EPROM bits serve as electrical switches. An erased bit passes the input into the
AND gate (switch on). while a programmed bit cuts it off (switch off). AU bits are 'initially erased.
2-80
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
The number of possible inputs to an AND gate varies from 40 (EP610) to 88 (EP1810). In the EP610 and
EP910 every dedicated input and its inversion and every macrocell feedback and its inversion are possible
inputs to the AND gate. In the EP181 0 which has local and global bussing, not all of the macrocell feedback is
available at every AND gate. The reason larger devices such as the EP1810 do not have all feedbacks feeding
the AND gates is to preserve the speed characteristics of the device.
Following the AND gates is a fixed 8 input OR function. This structure is called a fixed OR because the AND
functions are hard wired into the OR gates, and cannot be redistributed if unused.
The OR gate feeds a programmable inverter (XOR). A dedicated EPROM bit either programs the inversion
function on or off.
EPLD delay elements
The simplest solution to the architectural requirements is to model time through the logic array as a constant.
This parameter is called tlad. The rest of the elements in the timing model are similar to those found in
conventional logic. There are input and output delay parameters (tin, tio, tad); register parameters (\su, th, tclr,
ths, tics, tiel; and internal connection parameters (tfd). A detailed diagram of an EPlD Macrocell Delay Paths
Model is shown in Figure 9 with a description of the signals.
glossary - Internal delay elements
tclr
Asynchronous register clear time. This is the amount of time it takes for a low signal to appear at
the output of a register alter the transition at the logic array, including the time required to go
through the logic array.
tfd
Feedback delay. In registered applications, this is the delay from the output of the register to the
input of the logic array. In combinational applications, it is the delay from the combinational
feedback to the input of the logic array.
th
Register hold time. This is the internal hold time of the register inside a macrocell: measured from
the register clock to the register data input.
tlad
logic array delay. This parameter incorporates all delay from an input or feedback through the
AND/OR structure.
tic
Clock delay. This delay incorporates all the delay incurred between the output of an input pad or 1/
o pad and the clock input of a register including the time required to go through the logic array.
This delay is differentiated from the system clock delay tics by the need to pass through a ClKB
primitive, which specifies individual register clocking.
tics
System clock delay. This delay incorporates all delays incurred between the output of the input
pad and the clock input of the registers for dedicated clock pins.
tin
Input pad and buffer delay which direct the true and complement data input signals into the AND
array.
tio
I/O input pad delay. This delay applies to I/O pins committed as inputs.
tad
Output buffer and pad delay. For registered applications, this incorporates the clock to output
delay of the flip flop. In combinational applications, it incorporates delay from the output of the
array to the output of the device.
tsu
Register setup time. This is the internal setup time of the register inside a macrocell - measured
from the register data input until the register clock.
txz
Time to 3-state output delay. This delay incorporates the time between a high-to-Iow transition on
the enable input of the 3-state buffer to assertion of a high Impedance value at an output pin.
tzx
3-state to active output delay. This delay incorporates the time between a low-to-high transition on
the enable input of the 3-state buffer to assertion of a high or low logic level at an output pin.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-81
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
explaining the EPLD data sheet specifications
The data sheet for each TI EPLD references timing parameters which characterize the switching operating
specifications. These parameters are measured values, derived from extensive device characterization and
100% device testing. Among the switching characteristics are the following: tac01(tot), tacnt(tot), tah(tot),
tasu (tot) , tc01 (tot), tclr(tot), tcnt(tot), th (tot) , tpd1 (tot), tpd2 (tot) , tPXZ(tot), tPZX(tot), tsu(tot). These
parameters, described below in detail, may be represented by the EPLD internal delay elements. (See
Figure 12)
~tfd*""-tl.d
tpd!totl - tin + tlad + tod
tcntltotl - tfd + tlad + tsu
tacntltot) - tfd + tlad + tsu
tt-tln _______ tlad~txz or tzx--tlll
tp2Xltoti - tin + tlad + tzx
tPXZltotl - tin
+
tlad
+
tXl
~tin'"
tasultot} - (tin
tic
1111
+ ttadl - llin + tiel + tau
INPUT
tclrltotl "" tin + telr + tod
INPUT
CLOCK-..;;;-_ _ _ _ _ _ _ _--'
INPUT
tt-tin
...
t aco 1(totl .. tin
tic
...
+ tic + tod
INPUT
INPUT-;;'N:::P;---------;H>
CLOCK " ' ; ; ; - - - - - - - - - - - '
~tin...,.~I.I__---t,c.----___.!~
~tin
tiC$---~~--tod__tt
...
t co1{tot) .. tin
+ tics + tod
FIGURE 12. TI EPLD TIMING EQUATIONS
2-82
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
glossary - external delay elements
Iac01 (tot)
Defined as the asynchronous clock to output delay. It is the time required to obtain a valid
output after a clock is asserted on an input pin. This delay is the sum of the input delay (tin).
the clock delay (tiel. and the output delay (tod).
tacnt(tot)
Defined as the asynchronous clocked counter period. It is the minimum period a counter can
maintain when asynchronously clocked. This delay is the sum of the feedback delay (tfd)
and the logic array delay (tfad). and the register setup time (tsu).
lah(tot)
Defined as the asynchronous hold time. It is the amount of time required for data to be
present after an asynchronous clock. This value is the difference between the sum of the
input delay (tin). the clock delay (tiel. and the hold time (th) and the sum of the input delay
(tin) and logic array delay (tlad).
tasu(tot)
Defined as asynchronous setup time. It is the time required for data to be present at the input
to the register before an asynchronous clock. This value is the difference between the sum of
the input delay (tin). array delay (lfad) and the register setup time (ts u) and the sum of the
input delay (tin) and the clock delay (tiel.
tc01 (tot)
Defined as system clock to output delay. It is the time required to obtain a valid output after
the system clock is asserted on an input pin. This delay is the sum of the input delay (tin). the
system clock delay (tics). and the output delay (tod).
tclr(tot)
Defined as delay required to clear register. It is the time required to change the output from
high to low through a register clear measured from an input transition. This delay is the sum
of input delay (tin). register clear delay (tclr), and the output delay (tod).
tcnt(tot)
Defined as the system clock counter period. It is the minimum period a counter can maintain.
This delay is the sum of the feedback delay (tfd). the logic array delay (tlad). and the internal
register setup time (tsu).
th(tot)
Defined as hold time for the register. It is the amount of time the data must be valid after the
system clock. It is the difference between the sum of the internal input delay (tin). the system
clock (tics). and the system-clock hold time (ths) and the sum of the input delay (tin) and
logic array delay (tlad).
tpd1 (tot)
Propagation Delay; Defined as the delay from a dedicated input to a non-registered output.
This is the time required for data to propagate through the logic array and appear at the
EPLD external output pin. This delay is the sum of input delay (tin). array delay (tlad) and
output delay (ted).
tpd2(tot)
Propagation Delay; Defined as the delay from 1/0 pin to a nonregistered output. This is the
time required for data from any external 1/0 input to propagate through any combinational
logic and appear at the external output pin of an EPLD. This delay is the sum of the 1/0 delay
(tio). input delay (tin). array delay (tlad). and the output delay (ted).
tPXZ(tot)
Defined as the time to enter into 3-state. It is the time required to change an external output
from a valid high or low logic level to 3-state from an input transition. This delay is the sum of
input delay (tin). array delay (tlad). and the time to activate the 3-state buffer (txz).
tPZX(tot)
Defined as the delay from high impedance to active output. It is the time required to change
an external output from 3-state to a valid high or low logic level measured from an input
transition. This delay is the sum of input delay (tin). array delay (tlad). and the time to deactivate the 3-state buffer (tzx).
tsu(tot)
Defined as set up time for the register. It is the time required for data to be present at the
register before the system clock. This value is the difference between the sum of input delay
(tin). array delay (tlad). and an internal register setup time (ts u) and the sum of the input
delay (tin) and the system clock delay (tics).
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 856303. DALLAS, TEXAS 75285
2-83
EP1810
HIGH·PERFORMANCE 48·MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
conclusion
To understand timing relationships in the EP1810 and all EPLDs, it is very important to break up the internal
paths into meaningful microparameters that model portions of the EPLD architecture. Once internal paths are
decomposed, it is then possible to obtain accurate timing information by summing the appropriate
combinations of these microparameters. The EP1810 data sheet and relevant EPLD data sheets provide
architectural information on which the parameters apply and how the primitives are implemented.The TI EPLD
Development System provides minimized files that aid in the decomposition of designs. The combination of
these elements and the knowledge. of the architecture of each device allow characterization of any timing path
within an EPLD.
2-84
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303,. DALLAS. TEXAS 75266
EP1810
HIGH-PERFORMANCE 48-MACROCELL
ERASABLE PROGRAMMABLE LOGIC DEVICE (EPLD)
MECHANICAL DATA
68·PIN PLASTIC LEADED CHIP CARRIER (PLCC)
1.3 (0.0501
asci
r
~NOl
'lt004~ 45°
24.33109581
~r:r
--;ffif------+ -------;:::m-
~
~{.~~:~;:~.:~I
~
25.27(0995)
25]2(0.9851
tl ~
O.. 5.1 to 020.)
MIN
0.254 1~.~101
0.203 (0.008)
1.2210.0481
1,07 Ufil42)
L....--'.. 0.53 (0.021)
-'--t-7ff>;!~~ ~
0.66(0.0261
DETAIL "8"
68·PIN CLCC CERAMIC
GLASS
WINDOW
7.1(0.280) TYP
102100401 x 45°
1~.____ 20.3~~F8001 _ _ _ _->1
10-_____
24'3310.958131
23,82 (0.930)
Io------~::~; :g:::::
0,89 (0.035)
45°11
* ~=4
L-J.. ~53'O~
11:~~~'!!
x
0.15 (0.008)
0.2010.008)
0.43
~
DETAIL "P"
0.81(0.0321
0,6& (0.0261
~.0171
f
TEXAS . "
2·85
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS, TEXAS
7~265
2-86
PAL 16L8AM, PAL 16L8A·2M, PAL 16R4AM, PAL 16R4A·2M
PAL 16R6AM, PAL 16R6A·2M, PAL 16R8AM, PAL 16R8A·2M
STANDARD HIGH·SPEED PAL® CIRCUITS
02705. FEBRUARY I 984-REVISED AUGUST 1989
•
J OR W PACKAGE
Choice of Operating Speeds
High Speed, A Devices ... 25 MHz
Half Power, A-2 Devices ... 16 MHz
•
Choice of Input/Output Configuration
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
3-STATE
REGISTERED
INPUTS
PAL 1618
10
2
0
6
PAllSR4
8
0
4 13-statel
4
PAllSR6
8
0
S 13-statel
2
PAl16R8
8
0
8 13-statel
0
Q
OUTPUTS
Vee
0
liD
I/O
110
110
110
I/O
1/0 PORTS
DEVICE
o OUTPUTS
(TOPVIEWI
I
0
GND
FK PACKAGE
(TOP VIEWI
U
U
description
>0
These programmable array logic devices feature
high speed and a choice of either standard or
half-power devices. They combine Advanced
Low-Power Schottky t technology with proven
titanium-tungsten fuses. These devices will
provide reliable, high-performance substitutes
for conventional TTL logic. Their easy
programmability allow for quick design of
"custom" functions and typically result in a
more compact circuit board. In addition, chip
carriers are available for further reduction in
board space.
1 20 19
4
18
5
17
6
16
15
14
8
9 1011 12 13
0
Z
-og
r.:J
The Half-Power versions offer a choice of
operating frequency. switching speeds, C1nd
power dissipation. In many cases, these HalfPower devices can result in significant power
reduction from an overall system level.
The PAL 16' M series is characterized for
operation over the full military temperature range
of -55°C to 125°C.
tlntegrated Schottky~Barrier diode-clamped transistor is patented
by Texas Instruments. U.S. Patent Number 3.463.975.
PAL is a registered trademark of Monolithic Memories Inc.
PRODUCTION DATA documenls contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~:~~:~~i;8i~:,~1e ~!:~~~ti:r :'IO::~::::9t:~~s
not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-87
PAL 16R4AM, PAL 16R4A·2M, PAL 16R6AM, PAL 16R6A·2M, PAL 16R8AM, PAL 16R8A·2.
STANDARD HIGH·SPEED PAL@> CIRCUITS
PAL16R4'
PAL16R4'
FK PACKAGE
J OR W PACKAGE
(TOP VIEW}
elK
(TOP VIEW}
Vee
u
-' UO
__ "U>:;::,
1/0
1/0
2
3
1 2019
Q
Q
Q
Q
18
1/0
5
17
Q
6
16
Q
15
Q
14
Q
I/O
I
1/0
GND
BE
9 1011 1213
-
~I~
gg
(!)
PAL16R6'
PAL16R6'
FK PACKAGE
J OR W PACKAGE
(TOP VIEW}
elK
(TOP VIEW}
Vee
u
-' UO
__ "U>:;::,
1/0
Q
3
1 2019
4
Q
5
17
Q
Q
6
16
Q
Q
7
Q
Q
Q
14
8
1/0
GND
2
Q
Q
9 1011 1213
OE
-
~I~
ga
(!)
PAL16R8'
PAL16R8'
FK PACKAGE
J OR W PACKAGE
(TOP VIEW}
elK
(TOP VIEW}
Vee
"-' u
__ u>o
Q
Q
3
Q
Q
Q
Q
Q
Q
GND
2
1 20 19
4
18
5
17
6
16
7
15
8
14
9 10111213
OE
-~I~OO
(!)
2-88
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265
Q
PAL 16lBAM, PAL 16lBA·2M, PAL 16R4AM, PAL 16R4A·2M
STANDARD HIGH·SPEED PAL® CIRCUITS
functional block diagrams (positive logic)
PAL16L8AM
PAL 16L8A·2M
EN >1
&
'<:1k>-----0
p..----O
10
t>
0-........-1/0
16
k>-*f-..........-I/O
0--.+-......-1/0
0--.+.........-1/0
0-*1-.......-1/0
0-*1-.......-1/0
6
PAL16R4AM
PAL 16R4A·2M
De
EN2
..
ClK
&
32X 64
r;&;j)
8
~ 'V
,~
+
~ 'V
l.....-
r+r-+r-+r+I--
rl-
;;'1
C1
_1'"
1-0
10
2'<:1 i""
Q
~
'"""'
Q
~
Q
~
EN
>1
'<:1
~
f--+-
I'--j"""
r+--
r--r
~~
"'
"'
"'
"'
1/0
110
110
I/O
4
rv denotes fused inputs
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265
2·89
PAL l6R6AM, PAL l6R6A·2M, PAL l6RHAM, PAL l6RHA·2M
STANDARD HIGH·SPEED PAL® CIRCUITS
functional block diagrams (positive logic)
PAL16R6AM
PAL 16R6A-2M
DE
-tN2
Cl
r,
ClK
&
32 X 64
;;>1
4-
1-0 2
10
~
~
~
----
~ 'V
Q
Q
~
a
~
f----,
~
f----,
Q
~
I---
r-+r-+-
a
~
f----,
~
-....-:-'6x{>
~ 'V
I"
Q
EN
h
;;'1
'V
I---
I/O
I/O
I...-.-;.. 2
~
6
PAL16R8AM
PAL 16R8A-2M
DE------------------------clfI~__,
CLK------------------------------~
&
32 X 64
8
r;;;,;;,-r""Mi~~--
Q
t---t--"b.~-
Q
t---t--"b.-l--t---+--b--l-t---+--"b--l-t---+--"b--l--
Q
Q
Q
Q
r---t---t-~LQ
8
- denotes fused inputs
2·90
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
PAL 16L8AM, PAL 16L8A·2M
STANDARD HIGH·SPEED PAL® CIRCUITS
1111
FIRST
FUSE
INCREMENT
N UMBERS 0
4
B
12
16
20
24
28
31
0
32
6.
96
128
160
I--
"2
22.
12)"
v-l
1191
~j
(18)
r-1
(171
';~
28.
-
320
352
38.
"6
-
448
(3) .80
o
110
512
54.
576
I--
608
640
672
110
70'
(41 736
768
600
832
66'
6'6
.28
I--
1
(161
V
110
.60
(51 ••2
1024
1056
f--
1088
"20
1152
1184
1216
1
(15)
V
110
(6)'248
1280
1312
1344
1376
1408
-
1440
1472
1
V
(141
110
1
'504
(7 IX
1536
1568
--;
1600
I - --.,
1632
16. .
1696
(8)
1
(131
1/0
1728
1760
1792
1824
1856
-
1888
-
J!!.2016
Fuse number - First Fuse number
1
(121
v
1920
1952
1984
o
(11)
+ Increment
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265
2-91
PAL 16R4AM, PAL 16R4A·2M
STANDARD HIGH·SPEED PAL® CIRCUITS
CLK iUJ"FIRST
FUSE
NUMBERS 0
INCREMENT
8
12
16
20
24
28
0
32
64
.6
128
160
192
31
-.,
~~
(2)~
~
288
,......
,......
320
3.2
364
418
448
(31 480
~
1
~
I
(191
1
I
(181
110
110
,'2
f---;
544
576
60
j'";(j
D-
640
~
672
704
(4) 738
r.:J
(171
i7o' '":J
10
(16)
10
Q
~~
788
8
832
864
896
92
960
(5) ••2
D-
Q
~~
1024
1058
j'";(j
108
1120
)-
1152
(6)
1184
1216
1248
(15)
-V
~~
1344
I----'
1376
1408
1440
D-
1412
"1-"0 '":J
10
(141
V
1536
1
>--
1568
1600
1632
1664
1696
>--
V
1728
8 '760
J.::I
1792
1824
1856
1888
1920
1952
1984
../
I
1
I
(131 1
10
(121
v
(9)2016
~
2-92
Q
....£!.~
1504
Fuse number -
Q
>-
1280
1312
171
':I
10
First Fuse number + Increment
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
110
PAL 16R6AM. PAL 16R6A·2M
STANDARD HIGH·SPEED PAl® CIRCUITS
CLK
111
FIRST
FUSE
INCREMENT
N UMBERS 0
4
8
12
16
20
24
28
31
a
32
64
'6
128
160
"2
1
l2~
~
131
288
320
352
,84
416
448
480
I--
151
>-
>
-
136
>
:-;::t
..-
1181
a
M
10
~
..-
1171
a
b
1161
a
115;
a
b..-
1141
a
t:l
1131
a
.
M
10
I"
~~
\0-
1088
1120
1152
1184
1216
>
\0-
-
1280
1312
\0-
1344
:>-
1376
\0-
1408
1440
1472
1504
\0-
153
\--
1568
\-\0-
1600
1632
1664
1696
181"60
b-
1792
1856
1888
~
1952
1984
1 191 2016
I"
M
10
"i:o
lD
("
~~
J
1824
1920
b
10
t::2.~
I--
1728
M
~~
161 '246
Fuse number - First Fuse number
10
...52.1
168
800
832
864
8'6
.28
.60
9• 2
1024
1056
171
...-1-0
~1
512
544
516
606
640
612
104
141
1191 1/0
VI
-
1121
I
1/0
~
+ Increment
TEXAS " ,
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-93
PAL 16RBAM, PAL 16RBA·2M
STANDARD HIGH·SPEED PAl® CIRCUITS
CLK IIIJ~
FIRST"
,
FUSE
0
NU M8ERS
0
32
60
.6
'28
'60
'92
121~2~
INCREMENT
4
8
12
16
20
24
28
31
t>
>--
----
266
288
320
352
380
0'.
448
131 080
I-
-
>
\-
840
672
700
141 736
>
I--
768
800
"""-
-
960
>
1191
a
r.J
1181
a
~~
'j":Q
10
-V
1024
'05
1088
1120
1152
"84
1216
r;:o
10 1.J::rtJ 1?l a
"
-
1-0
10
r.:J.....
1161
a
r.J
1151
a
':I
(141
a
r.J....
1131
a
r.J
1121
a
~~
I 151 992
>
T-O
10
"
~~
'248
1161
1280
1312
1344
\..-
137
'408
'440
-
1472
1504
>
1536
1568
1600
)--
1832
1664
1696
\..-
1728
;r
1792
1824
1856
1888
1920
1952
1984
10
'T-"ii
10
~~
\....
181'760
.--1-0
~h
1171
I--
D-
....-1-0
10
t:2.~
I 19120 '6
2-94
r.::J
~~
"""-
832
860
896
928
Fuse number - First Fuse number
10
~~
5'2
544
578
608
I
'j":Q
+ Increment
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
~I
PAL 16LBAM, PAL 16LBA-2M, PAL 16R4AM, PAL 16R4A-2M
PAL 16R6AM, PAL 16R6A-2M, PAL 16RBAM, PAL 16RBA-2M
STANDARD HIGH-SPEED PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) ................................. , 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
Storage temperature range ......................................... - 65 DC to 150 DC
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
TA
Operating free-air temperature
I OE input
I
All others
MIN
4.5
2
2
Low-level output current
-55
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOM
5
MAX
5.5
5.5
5.5
0.8
-2
12
125
UNIT
V
V
V
rnA
rnA
°e
2-95
PAL 16LBAM, PAL 16R4AM, PAL 16R6AM, PAL 16R8AM
STANDARD HIGH·SPEED PAl® CIRCUITS
electrical characteristics over recommended operating free·air temperature range
PARAMETER
TEST CONOITIONS
VIK
Vee - 4.5 V,
VOH
Vee
VOL
Vee
Outputs
10ZH
1/0 ports
Outputs
I/O ports
10Zl
II
11/0 ports
IIH
.IAII others
= 4.5
= 4.5
II -
V,
IOH
V,
IOl
= -2 mA
= -12 mA
=
Vee
= 5.5
Vee
=
5.5 V,
VI
=
Vee
=
5.5 V,
VI
= 2.7
=
V,
III
Vee
10S~
Vee - 5.5 V,
lee
Vee
=
5.5 V,
5.5 V,
Vo
Vo
VI
2.4
V
V
0.4
100
-20
-100
0.2
5.5 V
100
V
25
-0.2
I OE input
I All others
= 0.4 V
V,
UNIT
20
= 0.4 V
=0
MAX
-1.5
3.2
0.25
-0.1
-30
Vo - 0.5 V
VI
TYpt
= 2.7V
Vee
5.5 V,
MIN
-18 mA
Outputs open
75
V
~A
~A
mA
~A
mA
-250
mA
180
mA
MAX
UNIT
MHz
timing requirements
MIN
0
fclock
Clock frequency
tw
Pulse duration {see Note 21
tsu
th
Setup time, input or feedback before elK!
lelock high
15
IClock low
20
Hold time, input or feedback after elK!
25
ns
25
ns
0
ns
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified
are only for clock high or clock low, but not for both simultaneously.
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
FROM
TO
TEST CONOITIONS
f max
tpd
I, I/O,
0, I/O
MIN
Typt
MAX
UNIT
25
45
15
30
MHz
ns
tpd
elK!
Q
R1 = 390O,
10
20
ns
ten
DEI
Q
R2 = 750O,
15
25
ns
tdis
DE!
Q
See Figure 1
10
25
ns
ten
1,1/0
0,1/0
14
30
ns
tdis
I, I/O
0, 110
13
30
ns
t All typical values are at Vee = 5 V, TA = 25°e.
~Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Set Vo at 0.5 V
to avoid test equipment degradation.
2-96
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655303 • DAl.LAS, TEXAS 75265
PAL 16L8A-2M, PAL 16R4A-2M, PAL 16R6A-2M, PAL 16R8A-2M
STANDARD HIGH-SPEED PAL ® CIRCUITS
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
= 4.5
= 4.5
VIK
VCC
VOH
VCC
VOL
VCC - 4.5 V,
Outputs
10ZH
1/0 ports
Outputs
10Zl
1/0 ports
II
1/0 ports
IIH
All others
VCC
VCC
=
=
=
V,
II
V,
10H
5.5 V,
5.5 V,
=
Vo
Vo
= 2.7
= 0.4
=
VCC = 5.5 V,
ICC
VCC
=
5.5 V,
5.5 V,
=
VI = 0 V,
V
0.4
100
-100
0.2
100
2.7 V
= 0.5
V
-20
25
I OE input
VI = 0.4 V
Vo
UNIT
20
V
VI
MAX
-1.5
3.2
V
VCC = 5.5 V,
VCC
Typt
0.25
10l - 12 rnA
VI = 5.5 V
10S~
2.4
-2 rnA
VCC = 5.5 V,
III
MIN
-18 rnA
I All
-0.2
-0.1
others
-30
V
75
Outputs open
V
~A
~A
rnA
~A
rnA
-250
mA
90
rnA
timing requirements
fclock
Clock frequency
IClock high
IClock low
tw
Pulse duration, (see Note 21
tsu
Setup time, input or feedback before ClKI
th
Hold time, input or feedback after ClKI
MIN
MAX
UNIT
0
16
MHz
25
ns
25
35
ns
0
ns
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified
are only for clock high or clock low, but not for both simultaneously.
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
FROM
TO
TEST CONDITIONS
fmax
tpd
1,1/0,
0,1/0
tpd
ClKI
Q
Rl
ten
OEI
tdis
OEI
ten
1,1/0
tdis
1,1/0
MIN
Typt
16
25
MAX
UNIT
MHz
25
40
ns
ns
11
35
Q
R2
= 390 Il,
= 750 Il,
20
35
ns
Q
See Figure 1
11
30
ns
0,1/0
25
40
ns
0,1/0
25
35
ns
tAli typical values are at VCC = 5 V, TA = 25°C.
*Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Set
to avoid test equipment degradation.
Va at 0.5
V
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-97
PAL l6LBAM,. PAL l6LBA·2M, PAL l6R4AM, PAL l6R4A·2M
PAL l6R6AM, PAL l6R6A·2M, PAL l6RBAM, PAL l6RBA·2M
STANDARD HIGH·SPEED PAl® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
SV
S1
b
R1
FROM OUTPUT
UNDER TEST
CL
ISee Note A)
-...--4..-.......-
TEST
POINT
R2
LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
~~~~G _ _ _.....15,.~5-_-V-_-_-_-_-_ :
. . Isu""'-
:
DATA
INPUT
HIGH·LEVEL
PULSE
V
'h.--'
.1.5 V
1.5 V
~
-:----3V
LOW·LEVEL
PULSE
0
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
J1.5
tpd
IN-PHASE
OUTPUT
V
-f.---..!
I'
~
I
I
I
1.5 V:
,
I
Ipd~
OUT-OF-PHASE
OUTPUT
\
Ipd
e
~,-~-:
VOH
1.5 V
J/-3V
~---O
~VOH
1.5 V
(See Note 01
3V
~
:
J _____ 0
OUTPUT
CONTROL
(low-level
enabling)
1.5 V
-
"1II
I I
I I
WAVEFORM 1
S1 CLOSED
(See Note B)
WAVEFORM 2
S10PEN
(See Note Bl
!--tdis
I
II
~3.3V
I
1.SV
I I _ _ LVOL+O.SV
~
I
ten~
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
14-
ten....
VOL
~Ipd
1
~'~\1
VOLTAGE WAVEFORMS
PULSE DURATIONS
~5~- - : V
\
~---3V
---./f. .'.5- -v~
0
tw ____
~
I
V
:;r-1.SV
------~
--l-
..: . .
tdis
I
VOL
.t.
T==i=VOH
·~VOH-O.5V
~OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE·STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled
the output control.
s 10 MHz. tr and If S 2 ns. duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch 51 is closed.
by
C. All input pulses have the following characteristics: PRR
E. Equivalent loads may be used for testing.
FIGURE 1
2-98
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAD16NB-7C
HIGH-PERFORMANCE PROGRAMMABLE ADDRESS DECODER
03085, JANUARY 1988-REVISEO AUGUST 1989
•
J OR N PACKAGE
Very-High-Speed Address Decoder /Ideal for
Use with High Speed Processorsl
(TOP VIEW)
Vee
•
1/0 Propagation Delay: 7 ns Max
•
Field Programmable on Standard PLD
Programmers
•
Fully TTL Compatible
•
Security Fuse Prevents Unauthorized
Duplication
•
Dependable Texas Instruments Quality and
Reliabilitv
•
Potentiel Applications
Address Decoders
Code Detectors
Peripheral Selectors
Fault Monitors
Machine State Decoders
0
1/0
1/0
1/0
1/0
1/0
1/0
0
I
GND
FN PACKAGE
(TOP VIEW)
u
u
_>0
3
description
The TIBPAD16N8 is a very-high-speed
Programmable Address Decoder featuring 7 ns
maximum propagation delay, the highest speed
in the TTL programmable logic family. The
TIBPAD16N8 utilizes the IMPACT-X'" process
and proven titanium-tungsten fuse technologv
to provide reliable, high performance substitutes
for conventional TTL logic.
2
1 20 19
4
18
5
17
6
16
15
14
9 1011 12 13
a
The TIBPAD16N8 contains 1 dedicated inputs and 8 outputs. Each output has two product terms, one
of which is used to enable the inverting buffer associated with the respective output. Six of the outputs
are I/O ports, the remaining two are dedicated outputs. Each of the six I/O ports can be individually
programmed as an input or an output; this allows the device to be used for functions requiring up to 16
inputs and 2 outputs or 1 inputs and 8 outputs.
a
The TIBPAD16N8 is supplied with all six I/O ports in the input configuration (output buffers in the highimpedance state). If an I/O port is selected to be an output, it must be programmed accordingly. It is
recommended that all unused outputs on this device remain in the three-state condition for better noise
immunity.
The TIBPAD16N8-7C is characterized for operation from
IMPACT~X
aoc to
75°C.
is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA d.cumo.ts ....toin inlormotion
currant IS af publication dat8. Predacts conform to
spacificati.l. par .... terms of TaXI. Instruments
==::i~8i~r:1~7i
=::i:t lrr:::::£:r~~1 nat
Copyright @ 1989. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-99
TlBPAD16N8·7C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER
functional block diagram (positive logic)
a.
EN :.:1
32x16
'iJb----O
b----o
I>
10
16
6
b4H-+e-1I0
6
2-100
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TIBPAD16NB·7C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER
logic diagram (positive logic)
INCREMENT
FIRST
FUSE
NUM8ERS
,
0
,
1\
4
8
12
16
20
24
r-..
Xl-~
~
J<1-~
~
64
96
(3)
....
128
160
~
192
224
(5)
256
288
(6)
k1&f
320
352
171
".x
...
~
384
416
(8)
31
p.!!l
~
.K...
0
32
(2)
28
".x
....
448
(12)
480
(9)
".x
~
....
o
1/0
I/O
1/0
I/O
1/0
I/O
o
111)
Fuse number = First Fuse number + Increment
TEXAS ."
INSIRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·101
TIBPAD16NB·7C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range .................................... " ooe to 75°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during programming cycle.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.8
V
V
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
10H
High-level output current
-3.2
rnA
10L
TA
low-level output current
24
75
rnA
2
Operating free-air tempe'rature
0
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
2.4
3
0.3
MAX
-1.5
UNIT
VIK
Vee = 4.75 V,
11= -18 rnA
VOH
Vee = 4.75 V,
10H = -3.2 rnA
VOL
II
Vee = 4.75 V,
10L = 24 rnA
Vee = 5.25 V,
VI = 5.5 V
10ZH*
Vce = 5.25 V,
Va = 2.7 V
0.1
rnA
10ZL *
Vee = 5.25 V,
Va = 0.4 V
-0.1
rnA
IIH*
Vee = 5.25 V,
VI = 2.7 V
25
~A
*
Vee = 5.25 V,
VI = 0.4 V
-0.25
rnA
Vee = 5 V,
Vee = 5.25 V,
Va = 0.5 V
Outputs open
VI = 0,
-70
-130
rnA
120
180
IlL
10§
lee
el
Co
-30
V
V
0.5
V
0.2
rnA
VI = 2 V
5
rnA
pF
Va - 2 V
6
pF
t All typical values are at Vee = 5 V, T A = 25 ·e.
1/0 leakage is the worst case 01 10ZL and IlL or 10ZH and IIH.
§ This parameter approximates lOS. The condition Va = 0.5 V takes tester noise into account. Not more than one output should be shorted
*
at a time and duration of the short-circuit should not exceed one second.
switching characteristics with two outputs switching (typical PAD mode) over recommended ranges
of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
FROM
tpd
1,1/0
ten
1,1/0
tdis
1,1/0
TEST
TO
CONDITIONS
0,1/0
2 outputs switching
0,110
0,1/0
Rl = 200 II,
R2 = 39011
See Figure 1
t All typical values are at Vee = 5 V, T A = 25·e
2-102
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
Typt
MAX
UNIT
2
5
7
ns
3
3
8
10
ns
8
10
ns
TIBPAD16NB·7C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications. algorithms. and the latest information on hardware. software. and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available. upon request. from the nearest TI field sales office. local
authorized TI distributor. or by calling Texas Instruments at (214) 997-5666.
PARAMETER MEASUREMENT INFORMATION
sv
S1
b
R1
FROM OUTPUT
UNDER TEST
_+_..._ ....._
TEST
POINT
R2
CL
(See NOle AI
LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
\.1-:;;~---3.SV
.1/,1.SV
INPUT
----"
Ipd
IN-PHASE
OUTPUT
, .
i /1,.--+-:I -.. . .t-:-5~
:L
'''.'
---i-'_--J
,
'"
1.S V
Ipd....1
OUT-OF-PHASE
OUTPUT
(See NOle 01
0.3 V
.,
'\1.SV
.
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
.,
1.SV
VOH
VOL
1.SV
I
I
len ~
J+-
,:
-1- - - - -- 0.3
~ J+- Idis
- - VOL
V
i
I
=3.3 V
WAVEFORM1----r\l1.SV
I'~VOL+O.SV
S1 CLOSED
,~-==:!-= VOL
(See Note BI
ten -+I j414- tdis
-.!
Ipd
p.vVOH
.
~3.SV
Ipd
'I
,..
OUTPUT
CONTROL
(low-level
enablingl
WAVEFORM 2
S1 OPEN
l.
~
(See Note BI
I __,,":-_.t.-= VOH
I
1.S V
LVOH-O.S V
=0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is SO pF for tpd and ten. 5 pF for 'dis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR:s 1 MHz. tr = tf = 2 ns. duty cycle = SO%
D. When measuring propagation delay-times of 3-state outputs, switch Sl is closed.
FIGURE 1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-103
TIBPAD16NB·7C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER
WORST CASE MULTIPLE OUTPUT SWITCHING CHARACTERISTICS
WORST CASE PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
8.0
..
..
c
I
~,..
~
Q
Vcc
7.9 -R1 R2 7.8 -CL TA 7.7
1
- 4.75 V.
2000.
3900.
50 pF.
75°C
7.6
7.5
c
i.
'"
;.
7.4
Q.
7.3
7.2
7.1
7.0
2
4
6
Number of Outputs Switching
FIGURE 2
2-104
TEXAS ~
INSTRUMENTS
.POST OFFICE BOX 655012 • DALLAS, TEXAS 75265 .
8
TIBPAD16NB·7C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER
TYPICAL CHARACTERISTICS
PROPAGAnON DELAY TIME
SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
150'U-N~P~R~O-G~R~A-M~M~E~D-D~E~V-IC~E~--r--'---'
6.5
..T
.E
I\tPH~
6.0
\
j::
\
1:-
~ 5.5
.§
tpLH
......
.'"
tii
a.
2 5.0
IL
90~~
__- L_ _
~
_ _L-~__- L _ _~~
VCC - 5 V.
R1 - 200 Il
R2-3901l
CL - 50 pF.
1 OUTPUT SWITCHING
/
,/
-
7
/
'\
--
jV
I\..
"-V
./
r-.
-----
4.5
-75 -50 -25 0
25 50 75 100 125
TA-Free-Air Temperature- °C
-75 -50 -25 0
25
50 75 100 125
T A - Free-Air Temperature - °C
FIGURE 4
FIGURE 3
PROPAGATION DELAY TIME
PROPAGATION DELAY TIME
vs
vs
SUPPLY VOLTAGE
LOAD CAPACITANCE
24
7.0 -R1
6.8 -R2
.. 6.6 -CL
6.4 -TA
~ 6.2
j:: 6.0
1:- 5.8
~ 5.6 i'..
~
& 5.4
'; ..5.2
~ 5.0
2 4.8
IL 4.6
4.4
4.2
4.0
4.5
i
-
200 Il.
39dll.
50 pF •
25°C
In
c
.
I
E
j::
.
>
a;
..... ~
VCC - 5 V.
R1 - 200 Il.
R2 - 390 Il.
20
TA - 25°C.
18 1 OUTPUT SWITCHING
22
-- -
Q
c
~
.'"
tPHL -
£
tP~H::
4.75
5.25
VCC-Supply Voltage-V
VL
12
8
4
5.5
/
/
14
6
I
I
V t PHL
16
a. 10
r-J
V
~
~
o
FIGURE 5
h
V
.-..I-
tPLH-
~V
,/
V
600
400
200
CL -Load Capecitance-pF
800
FIGURE 6
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-105
-
2-106
T1BPAD18N8-6C
HIGH-PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY
03086. DECEM8ER 1987-REVISED AUGUST 1988
•
J OR N PACKAGE
(TOP VIEW)
Very-High-Speed Address Decoder (Ideal for
Use with High Speed Processors)
Vee
•
I/O Propagation Delay: 6 ns Max
•
Suitable for High Speed NAND-NAND Logic
Implementation
•
Field Programmable on Standard PLD
Programmers
•
Fully TTL Compatible
•
Security Fuse Prevents Unauthorized
Duplication
•
Dependable Texas Instruments Quality and
Reliability
•
Potential Applications
Address Decoders
Random Logic (NAND-NANDI
Code Detectors
Peripheral Selectors
Fault Monitors
Machine State Decoders
I/O
110
110
110
liD
110
110
110
GND
....._ _...rFN PACKAGE
(TOP VIEW)
U
uo
--->=:,
3
2
1 20 19
4
18
5
17
6
16
7
15
8
14
I/O
liD
I/O
liD
liD
9 10 11 12 13
-0-00
z
l?
description
--
The TIBPAD18N8-6C is a very-high-speed Programmable Address Decoder featuring 6-ns maximum
propagation delay, the highest speed in the TTL programmable logic family. The TIBPAD18N8 uses the
IMPACT-X" process and proven titanium-tungsten fuse technology to provide reliable, high-performance
substitutes for conventional TTL logic.
The TIBPAD18N8-6C contains 10 dedicated inputs and 8 product terms, each followed by an inverting
buffer. Each of the eight buffers can be individually programmed so that the corresponding pin can function
either as an input or output, depending on the state of the fuse controlling the output buffer, as indicated
by Table 1. This allows the device to be used for functions requiring up to 17 inputs and a single output
or down to 10 inputs and 8 outputs.
A high-speed feedback path, which does not go through the output buffer, is provided to offer higher
performance operation in designs where feedback is required. The architectural fuse on the internal
multiplexer is used for the selection of this path (see Table 21. This makes the TIBPAD18N8-6C ideal for
the implementation of a very fast NAND-NAND logic. The TIBPAD18N8 is supplied with all eight output
buffers disabled thus establishing all programmable input/output lines as inputs. If an 1/0 line is selected
to be an output it must be programmed accordingly.
The TIBPAD18N8-6C is characterized for operation from O°C to 75°C.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA d...mlnto ••otlin infarmotlo.
..mot II of pu.llollion dote. Producll ...far.. to
.-ilintl........ thlllnni 0' T.... I.strumanto
=H~ai:::I~7i =:~:; :.r::~:.:~ not
Copyright @ 1987, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-107
TIBPAD18N8-6C
HIGH-PERFDRMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY
functional block diagram (positive logic)
10
18x!>
~
~
t>
B
V
8
8
r*-
8x
8
&
36x8
1/0
EN
~
8
L.,8XMUX
8..-
1
8
-
Gl
.".
Table 1. Output Buffer Programming
ARCHITECTURAL
FUSE
Table 2. I/O Multiplexer Programming
ARCHITECTURAL
OPERATION
FUSE
Intact
Input
Intact
(Output Buffer
Blown
in 3-State)
Blown
2-108
Output
TEXAS . "
INSrRUMENlS
POST OFFICE BOX
65~12
• DALLAS. TEXAS 75265
OPERATION
Output Buffer Feedback
Fast Feedback
(pre-output buffer)
TIBPAD18N8·6C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY
logic diagram (positive logic)
INCREMENT
Ir-----------------------A~
o
4
B
12
16
____________________
20
24
2B
32
~\
35
,~
n 296
~~"."
n 297
Ill,
0
,131
Gl
o
r
288
~"."
r
36
1141
"'I
Gl
n 29B
2B9
~
~"".
r
72
,lSI
o
o
Gl
290
~
n~99
~~"""
lOB
(16)
Gl
o
r
291
300
~ 1151
11
...
144
,171
I/O
MUX,
Gl
r
292
11~01
•
~".'"
lBO
IBI
Gl
D
r
293
11~02
~"""
r
216
1(91
o
Gl
294
11~03
~j"""
252
(111
Gl
H'GH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER/ANO ARRAY
Fuse number
o
MUX 1
=
First Fuse number
+
T
295 _
Increment
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-109
TIBPAD18N8-6C
HIGH-PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) ................................................. " 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range ...................................... ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Vee
Supply voltage
VIH
High-level input voltage Isee Note 2)
Vil
10H
low-level input voltage Isee Note 2)
High-level output current
0.8
-3.2
10l
Low-level output current
24
TA
Operating free-air temperature
2
0
75
V
V
rnA
rnA
De
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system andlor
tester noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VIK
Vee
VOH
Vee
VOL
Vee
IOZH*
Vee
10Zl*
II
Vee
IIH
Vee
III
Vee
IO§
Vee
lee
ei
Vee
Vee
= 4.75 V.
= 4.75 V.
= 4.75 V.
= 5.25 V,
= 5.25 V.
= 5.25 V.
= 5.25 V.
= 5.25 V.
= 5.25 V.
= 5.25 V.
=
II
10H
MIN
Typt
2.4
3
0.37
-18 rnA
=
-3.2 rnA
10l - 24 rnA
= 2.7 V
Vo = 0.4 V
VI = 5.5 V
Vo
=2V
Vo = 2 V
VI
eo
V
V
0.5
V
20
~A
-20
~
20
~A
~
-0.25
rnA
-75
-130
rnA
145
180
5
rnA
pF
6
pF
VI
-30
UNIT
20
VI-2.7V
= 0.4 V
Vo = 0.5 V
VI = 4.5 V
MAX
-1.2
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
FROM
I
tpd
(2 outputs
switching)
TEST
TO
CONDITIONS
=
=
=
o Ina feedback)
Rl
o Iwith 1 fast feedback path)
R2
o (with 2 fast feedback paths)
el
50 pF.
See Figure 1
o Iwith 3 fast feedback paths)
20011.
39011.
MIN
Typt
MAX
2
3.5
4.5
6
ns
7
10
ns
5
9.5
6.5
12
14
18
ns
ns
UNIT
t All typical values are at Vee = 5 V. TA = 25 De.
.
* I/O leakage is the worse case of 10Zl and III or IOZH and IIH.
§ This parameter approximates lOS. The condition Vo = 0.5 V takes tester noise into account. Not more than one output should be shorted
at a time and duration of the short circuit should not exceed one second.
2-110
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TlBPAD 1BNB·6C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY
PARAMETER MEASUREMENT INFORMATION
5V
Rl
fROM OUTPUT UNDER TEST
....--<_-4~- TEST
POINT
CL-50pF
(see Note AI
R2
LOAD CIRCUIT
IN-PHASE
OUTPUT
OUT-Of-PHASE
OUTPUT
VOLTAGE WAVEfORMS
PROPAGATION DELAY TIMES
NOTES:
A. CL includes probe and jig capacitance.
B. All input pulses have the following characteristics: PRR ,,; 1 MHz, tr
= tf = 2 ns, duty cycle = 50%.
FIGURE 1
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-111
TlBPAD 18N8·6C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
200
j
E
.!.<:
150
~:::J
125 VCC - 4.5 V
>is.
100
tJ
-L
tPHL
~
-;--- r--
4
i=
.
-
--
>-
~
5.25 V
3
.,o
<:
.
~
I
tJ
~
5
I
~VCC - 5V
VCC - 4.75 V
75
I
~
<:
~VCC -
\ \
a.
:::J
III
..
-
175 VCC - 5.5 V
c(
6
2
R1 - 2000
R2 - 3900
CL - 50 pF
TA - 25°C
2 OUTPUTS SWITCHING
NO FEEDBACK I
Co
£
50
25
I
o
25
50
TA-Free-Air Temperature- °C
4.5
75
5.5
5
Vec-Supply Voltage-V
FIGURE 3
FIGURE 2
PROPAGATION DELAY TIME
PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
LOAD CAPACITANCE
6
6
.,c
tpLH
I
tpLH
5
I
I
tPHL
CD
tpHL
E
4
>.!!
0
3
i=
.,
<:
0g
0
VCC - 5 V
-R1 - 2000
R2-3900
CL-50pF
r- 2 OUTPUTS SWITCHING
NO FEEDBA1CK
o
o
.a.
Q)
2
0
25
VCC - 5 V
R1 - 2000
R2 - 3900
TA - 25°C
NO FEEDBACK
2 OUTPUTS SWITCHING
S!
a..
50
75
o
TA-Free-Air Temperature- DC
100
150
200
CL -Load Capacitance-pF
FIGURE 5
FIGURE 4
2-112
50
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
250
TlBPAD1BNB·6C
HIGH·PERFORMANCE PROGRAMMABLE ADDRESS DECODER/NAND ARRAY
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
NUMBER OF FAST FEEDBACK PATHS
25
In
c
I
GO
E
j::
>
CD
"ii
20
15
c
c
0
';
.'"
10
VCC - 5 V
R1 - 200 {l
R2 - 390 {l
CL - 50 pF
TA - 25°C
2 ~UTP~TS SflTC11NG
0.
e
a.
5
2
3
4
5
6
7
Number of Fast Feedback Paths
FIGURE 6
WORST-CASE PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
8
.,c
.
.
c
.,.
I
E
7
6
j::
5
>
"ii
4
c
0
'"
3
CD
0.
£
2
VCC - 4.75 V
R1 - 200 {l
R2-390{l
CL - 50 pF
TA - 75°C
NO FEEDBACK
2345678
Number of Outputs Switching
FIGURE 7
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-113
..
2-114
TIBPAL 16LB·7M. TlBPAL16R4·7M. TlBPAL 16R6·7M. TlBPAL16RB·7M
TIBPAL 16LB·5C. TIBPAL 16R4·5C. TlBPAL 16R6·5C. TIBPAL 16RB·5C
HIGH·PERFORMANCE IMPACT·XTMPAL® CIRCUITS
03359, OCTOBER 1989
•
TIBPAl16l8'
M SUFFIX ... J PACKAGE
C SUFFIX ... 'J OR N PACKAGE
High·Performance Operation:
f max (no feedback I
TIBPAL 16R'· 7M Series ... 100 MHz
TIBPAL 16R' -5C Series, .. 125 MHz
f max (internal feedback I
TIBPAL16R'-7M Series ... 100 MHz
TIBPAL 16R' -5C Series ... 125 MHz
f max (external feedbackl
TIBPAL16R'-7M Series ... 74 MHz
TIBPAL 16R' -5C Series ... 115 MHz
Propagation Delay
TIBPAL 16L' -7M ... 7 ns Max
TIBPAL 16L'-5C ... 5 ns Max
(TOP VIEW I
Vee
0
1/0
I
GND
•
Functionally Equivalent, but Faster than
EXisting 20-Pin PALs
•
Preload Capability on Output Registers
Simplifies Testing
•
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go Highl
•
I/O
I/O
I/O
I/O
I/O
0
TIBPAl16l8'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEWI
u
_ >u
3
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
2
Security Fuse Prevents Duplication
•
Dependable Texas Instruments Quality and
Reliability
18
17
16
15
14
3-STATE
REGISTERED
I/O
Q OUTPUTS
PORTS
10
2
0
4 13-statel
6 (3-statel
a (3-statel
6
INPUTS
PAL 1618
PAl16R4
a
0
PAl16R6
a
0
PAL 16Ra
a
0
110
I/O
I/O
110
110
a:
0.
IU
9 1011 12 13
o OUTPUTS
DEVICE
:>w
1 20 19
6
•
~
w
0
;:)
C
oa:
Pin assignments in operating mode
4
0.
2
0
description
These Programmable Array Logic devices feature the highest speed yet achieved in a bipolar PAL circuit.
This family of PALs is 100% functionally and pin-for-pin compatible with the industry standard 'PAL 16L8,
'PAL 16R4, 'PAL 16R6, and 'PAL 16R8. The Texas Instruments IMPACT-X'· (Enhanced Implanted Advanced
Composed Technologyl fabrication process has been employed to ensure this ultra-high-performance
operation. This process combines the latest Advanced Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their
easy programmability allows for quick design of custom functions and typically results in a more compact
circuit board. In addition, chip carriers are available for further reduction in board space.
All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow
loading of each register asynchronously to either a high or low state. This feature simplifies testing because
the registers can be set to an initial state prior to executing the test sequence.
The TIBPAL 16' M series is characterized for operation over the full military temperature range of - 55°C
to 125°C. The TIBPAL16' C series is characterized for operation from O°C to 75°C.
IMPACT-XTOI is a trademark of Texas Instruments Incorporated.
PAL® is a registered trademark of Monolithic Memories, Inc.
tlntegrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments, U.S. Patent Number 3,463,975.
rnR~t!!Ufo~::t~~!E: ~::i~~a:::;S:o:feJ~=er!:!~~~
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-115
TIBPAL 16R4·7M, TIBPAL 16R6·7M, TIBPAL 16R8·7M
TIBPAL 16R4·5C, TlBPAL 16R6·5C, TlBPAL 16R8·5C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
TIBPAL 16R4'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE
TIBPAL 1SR4'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
ITOP VIEW)
ITOP VIEWI
elK
>< U
Vee
...J UO
__ u>:::o
110
I/O
3
2
1 20 19
Q
4
Q
5
17
Q
6
16
I/O
Q
GND ......_ _...r-
Q
Q
I/O
I/O
I
Q
14
8
Q
9 1011 1213
OE
-
~Io
gg
c.:>
"tI
T·IBPAL 16RS'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE
TIBPAL16RS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
ITOP VIEW I
ITOP VIEWI
elK
::I:J
>< U
Vee
...J UO
__ u>:::o
I/O
0
Q
C
c:
3
2
1 20 19
Q
Q
(")
Q
-t
I
Q
"tI
I
Q
::I:J
I
-
GND
I/O
OE
m
<
m
:E
18
Q
5
17
Q
6
16
Q
7
15
Q
8
14
Q
9 10 11 12 13
-
~Io
ga
c.:>
TIBPAL 16RS'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE
nBPAL 16RS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
ITOP VIEWI
ITOPVIEW)
elK
>< u
Vee
...J u
__ u>o
Q
Q
3
Q
4
Q
5
Q
6
Q
GND
18
Q
Q
8
Q
""'I._ _..j'-
9 10 11 12 13
OE
- 0lw
zO
c.:>
Pin assignments in operating mode
TEXAS . "
INSTRUMENTS
2-116
1 20 19
7
Q
I
2
POST OFFICE BOX 665303 • DALLAS. TEXAS 75266
a a
TIBPAL 16L8·7M. TIBPAL 16L8·5C. TIBPAL 16R4·7M. TIBPAL 16R4·5C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
functional block diagrams (positive logic)
'PAL 16la
EN ;'1
&
90----0
32 X 64
0----0
16. [>
10
1/0
16
P-4t+.......-1/0
P--.t-+...-
1/0
P-.,........-I/O
3:
w
6
:>w
c::
'PAL 16R4
a..
....
J EN2
0"E
~Cl
ClK
(.)
r,
&
32
x 64
1-0
;'1
-+-
10
;s;c;4
-+-
----
~ 'V
f>+-
r+-
a..
~
0
:---"\
Q
~
EN
;'1
1/0
9
~
r-+f---]
""
""
""
r+-
~
~
4
,
c::
Q
~
~
r---
'V
0
~
--f..8
::J
Q
Q
29
1/0
1/0
1/0
4
rv denotes
~
fused Inputs
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-117
TlBPAL 16R6·7M, TIBPAL 16R6·5C, TlBPAL 16R8,7M, TlBPAL 16R8·5C
HIGH·PERFORMANCE IMPACT·X'M PAl® CIRCUITS
functional block diagrams (positive logic)
'PAL l6R6
OE
-C2
elK
~el
&
32 X 64
;;'1
~
I 0 2\1
lD
~
-:-'i6xi>-..;L 'V
'6
r+
~
0.:- 'V
"'tI
r-----,
P-
r-----,
Q
Q
r-----,
~
Q
r-----..
EN ;;'1
~
:JJ
o
r+-
.~
c:
1/0
..-
'--- 2
6
(')
1/0
\1
f---
C
o
o
~
f---
o
r-----,
p..
'----
I'"'"
r---.
-I
'PAL 16Ra
"'tI
:JJ
m
OE--------------------------aEN:1---,
S
m
elK----------------------------~
:e
&
32
8
x 64
r;;;.;;;lIT"-r:O~b_---- a
r----t----ir~-a
r----t----ir-l-- a
r---t---1-~l--a
,---r----o...-+-- a
r----t----ir-l--a
r---t--iO---:l--a
a
rv denotes
fused inputs
TEXAS ~
2·118
INSTRUMENlS
POST OFFICe BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16LH·7M, TlBPAL 16L8·5C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
FIRST
INCREMENT
~~~BERS ~O~--~4~--~B~--~1~2~~Al~6~~~2~O~--~2~4~--~2~B~,~31
3~ t;-'
- 1-++-1-44 - ::~
!
t
-
160
192-- 224·
-
f--
128
--
119) 0
.
12)~
256·
1
288
320
352384416-- ..
f-
v
11B) II')
448-
I~_.
512-544
1
576·
608--640672
704
v
117) 1/0
1
14) 736
768
800-
1
832
864896
928
960
....
3:
w
5>
w
116) 1/0
a:
J5) 992
0..
1024
1
1056
1088
1120
v
1152
I-
o
115) 1/0
:::l
'184
Q
1216
1248
oa:
-~
1280
1312
1344
r---
1376
1408
~)--_C>ol-.--_1'-'1-'-'-4)
0..
1/0
)---f-"
1440
1472
17)'504
1536-1568
1&00--+
113) 1/0
1632 - 1664
1696
1728
1760
IB) >L
1792
1824
1856
1888
1920
1952
1984
19)2016
112) 0
H----C'-'-J-
768
800
832
864
89
928
96
o
C
c:
n-I
M
10
":J
(171
a
(161
a
'";:] (151
.v
a
V
~1
~1 73.
::D
I/O
-
(31 480
"0
(181
'j':(j
-
>-
10
~
....:!~
151 992
1024
1056
1088
"0
"20
::D
r=>-
1162
1184
1216
m
S
m
:E
161
1344
1376
'40
'440
..- >-
1472
1504
.....-.
1536
1568
'GOO
~
'63
M
10
f---.'
1728
b
1141
a
L-£.!.1
-- 1
V
1664
1696
181
ID
t:!.1
'248
1280
1312
171
M
1131 1
/0
1760
.......,
1792
1824
1856
1888
1920
'95
-
1984
j
v
11211 /0
191 20 '6
~ OE
Fuse number - First Fuse number - Increment
TEXAS ",
INSTRUMENTS
2·120
POST OFFICE BOX 655303 • DALLAS. TeXAS 7,5265
TIBPAL 16R6·7M, TlBPAL 16R6·5C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
CLK .!.!.!-[>
111
FIRST
F USE
INCREMENT
N UMBERS 0
4
8
12
16
20
24
28
31
0
1
32
r--
6.
9.
128
,.0
192
224
r----
v
1191
I/O
1
121~
~
131
141
151
f-----'
288
320
352
)84
"6
448
.80
,.......,V
I--
.>
-
-
..-0
*.1 17 1a
10
~Ol
>--
768
800
.32
8 ••
89.
928
960
992
*~ a
10
~Ol
>--
512
54.
57.
608
640
672
704
73.
..-0
V
M
r:J
10
~
w
1161
rv""
a
1024
P-
,,20
1152
1184
1216
161
10
r:J
10
I(151
V
o
oa:
1280
1312
-
1344
1376
>-- D-
1408
(71
1440
1472
1504
10 r:J
ID
1141
Q"
a
~~
1536
1568
1600
1632
1664
1696
1728
181
1792
1824
'""=
1856
1888
I-'"
1920
1952
1984
.----.
191 201 •
First Fuse number
Ij(j
tAJ131 Q
v
10
~1
>--
1760
Fuse number -
>-
>--
1
I
1121
1111
I/O
OE
+ Increment
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
o
:::>
c
....:2.~
1248
w
a:
Q"
~~
1056
1088
:;
2·121
TIBPAL 16R8·7M. TIBPAL 16R8·5C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
,
ClK II) ....
FIR ST
FU SE
NU MBERS
INCREMENT
0
4
8
12
16
20
24
28
31
-
0
32
64
96
'28
'60
'92
>
--
(2)~
M
10
-;:::t
(19)
v
Q
t£!.~
2~
288
320
352
384
4'6
448
(3) 480
-V
."
:a
c
768
800
832
864
896
92
960
(")
151 992
o
c:
.....
-
."
r-1=0
....-
r.:J.
1171
r.:J.
1161
Q
I->
10
V
Q
~~
....-
.=
- >
"20
1216
161'248
W
10
r.:J. {lSI Q
V
~Il
l---'
1280
1312
1344
1376
1408
;:::::i
b-
'440
1472
M'"
10
r:t
1141
b
{l31
r.:J.
112)
V
a
~1
171'504
1536
1568
>--
1600
1632
1664
;::: p-
1696
1728
M
10
Q
~~
181 1760
1792
1824
1856
0-
'88
1920
1952
1984
f>-
ro
10
V
~
~1
19)20'6
Fuse number - First Fuse number + Increment
TEXAS ."
INSTRUMENTS
2·122
10
~1
1184
:e
1181 Q
....-
1152
S
m
'j';(j"
I->
1024
1056
1088
:a
m
v
t:!.~
r-
5'2
544
576
608
640
672
704
(4) 736
I-ii '"';:J
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
~)
a
TlBPAL16L8-7M. TlBPAL16R4-7M. TIBPAL16R6-7M. TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-XTM PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°C
Storage temperature range ......................................... - 65°C to 1 50°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
5.5
V
vee
Supply voltage
VIH
High-level input voltage Isee Note 2)
Vil
Low-level input voltage (see Note 2)
0.8
V
10H
High-level output current
-2
mA
10l
Low-level output current
Iclock
Clock frequency
tw
Pulse duration, clock (see Note 2)
tsu
2
0
12
mA
100
MHz
6
6
ns
Setup time, input or feedback before elK t
7
ns
th
Hold time, input or leedback alter elK!
0
TA
Operating free-air temperature
I High
I low
ns
-55
25
125
°e
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or
tester noise. Testing these parameters should not be attempted without suitable equipment.
PARAMETER
TEST CONDITIONS
II -
VOH
Vee = 4.5 V,
10H = -2 rnA
Vee = 4.5 V,
IOl=12mA
Vee = 5.5 V,
VO=2.7V
Val
10lH t
lOll t
II
0, Q outputs
1/0 ports
0, Q outputs
1/0 ports
L1/0 ports
MIN
-18 rnA
vee - 4.5 V,
Vee = 5.5 V,
Va = 0.4 V
Vee = 5.5 V,
VI = 5.5 V
2.4
Typt
MAX
UNIT
-0.8
-1.5
V
3.2
0.3
V
0.5
20
100
-20
-250
1
100
V
~A
~A
rnA
~A
Vee = 5.5 v,
VI = 2.7 V
Vee = 5.5 v,
vee = 5 V,
Vee - 5.5 V,
VI = 0.4 V
Va = 0.5 V
Outputs open,
I TA - 25°e and 125°e
VI = 0 V,
OE = VIH
ITA = -55°e
ei
1= 1 MHz,
VI = 2 V
pF
eo
1= 1 MHz,
Va = 2 V
pF
eclk
1= 1 MHz,
VelK - 2 V
pF
IIH
III t
10S§
lee
I All others
25
-0.08 -0.25
-30
-70
-130
120
180
mA
mA
mA
t All typical values are at Vee = 5 V, TA = 25°e.
t 1/0 leakage is the worst case 01 lOll and III or 10lH and IIH, respectively.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. Set Va at 0.5 V
to avoid test equipment ground degradation.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W
s:w
a:
a..
electrical characteristics over recommended operating free-air temperature range
VIK
;:
2-123
I-
o
c
oa:
:::>
a..
TIBPAL16L8·7M, TlBPAL1fiR4·7M, TIBPAL16R6·7M, TIBPAL16R8·7M
HIGH·PERFORMANCE IMPACT·X™ PAL® CIRCUITS
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwisenotedl (see Figure 51
PARAMETER
fmax t
FROM
I
TO
Without feedback
With internal feedback (counter configuration)
MIN
100
TYpt
MAX
UNIT
MHz
100
74
With external feedback
tpd
1.1/0
0,1/0
7
ns
tpd
ClK!
a
6
ns
tpd§
ClK!
Feedback input
3
ns
ten
OE.
OE!
1,1/0
1,1/0
a
a
7.5
ns
7.5
ns
0,1/0
0,1/0
8.5
ns
8:5
ns
!dis
ten
tdis
t All typical values are at VCC ~ 5 V, T A = 25°C.
:tSee section on fmax specifications.
§This parameter applies to TIBPAl 16R4' and nBPAl 16R6' only (see Figure 2 for illustration) and is calculated from the measured f max
with internal feedback in the counter configuration.
"'0
:zJ
o
C
c:
n
-I
"'0
:zJ
m
:S
m
:E
TEXAS ."
2-124
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
T1BPAL 16L8-5C, TIBPAL 16R4-5C, T1BPAL 16R6-5C, TIBPAL 16R8-5C
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to Il disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
to 75°e
Storage temperature range ......................................... - 65 °e to 150 °e
ooe
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNIT
4.5
5
5.25
v
v
v
Vcc
Supply voltage
VIH
High-level input voltage (see Note 2)
Vil
Low-level input voltage (see Note 2J
10H
High-level output current
0.8
-3.2
10l
Low-level output current
24
mA
fclock
Clock frequency
125
MHz
tw
Pulse duration, clock Isee Note 2)
tsu
th
Setup time, input or feedback before elK t
4
Hold time, input or feedback after ClK!
0
TA
Operating free-air temperature
0
2
5.5
0
I High
I low
4
mA
ns
4
25
75
ns
ns
DC
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or
tester noise. Testing these parameters should not be attempted without suitable equipment.
TEST CONDITIONS
MIN
MAX
UNIT
-0.8
-1.5
V
VIK
~
4.75 V,
II
VOH
VCC
~
4.75 V,
10H
VOL
VCC
10l
~
24 mA
0.5
V
Vo
~
2.7 V
100
~A
~
0.4 V
-100
~A
0.2
mA
10ZH*
Vce
= 4.75 V,
= 5.25 V,
10Zl *
II
VCC
~
5.25 V,
Vo
VCC
5.25 V,
VI
IIH*
VCC
5.25 V,
*
VCC
5.25 V,
10S§
VCC
=
=
=
=
=
III
ICC
VCC
-18 mA
Typt
VCC
~
~
-3.2 mA
f
Co
f
Cclk
f
=
=
=
VI
~
2.7 V
25
~A
VI
= 0.4 V
-0.08 -0.25
mA
Vo
5.25 V,
VI
1 MHz,
1 MHz,
0.3
V
5.5 V
5.25 V,
1 MHz,
3.2
=
~
~
0.5 V
OV,
Outputs open
Ci
2.4
=2V
=2V
VClK = 2
-30
-70
-130
rnA
120
180
mA
pF
VI
pF
Vo
pF
V
t All typical values are at VCC = 5 V, TA ~ 25°C.
* I/O leakage is the worst case of 10Zl and III or 10ZH and IIH, respectively.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. Set
Va
at 0.5 V
to avoid test equipment ground degradation.
TEXAS ."
INSlRUMENTS
POST OFFICE BOX 655303· DALLAS, TEXAS 75265
w
a::
a..
electrical characteristics over recommended operating free-air temperature range
PARAMETER
3:
w
:;
2-125
tO
::;)
Q
oa::
a..
TIBPAL 16L8·5C, TlBPAL 16R4·5C, TlBPAL l6R6·5C, TlBPAL 16R8·5C
HIGH·PERFORMANCE IMPACT·X™ PAL® CIRCUITS
switching characteristics over recommended supply voltage and operating free·air temperature ranges
(unless otherwise noted) (see Figure 6)
PARAMETER
TO
FROM
fmax*
MIN
Without feedback
125
With internal feedback (counter configuration)
125
With external feedback
115
Typt
MAX
UNIT
MHz
tod
1,1/0
0,1/0
5
tpd
ClKi
Q
4
ns
tpd!
ClKi
Feedback input
3
ns
ten
OE.
Q
5.5
ns
tdis
OEi
Q
5.5
ns
ten
1,1/0
0,1/0
6.5
ns
tdis
I, I/O
0, I/O
6.5
ns
Skew between registered outputs
tskew'
tAli typical values are at VCC
=
5 V, TA
=
ns
ns
25°C.
iSee section on fmax specifications.
§This parameter applies to TlBPAl 16R4' and TIBPAl 16R6' only (see Figure 2 for illustration) and is calculated from the measured f max
with internal feedback in the counter configuration.
'This parameter is the measurement of the difference between the fastest and slowest tpd (elK-ta-O) observed when multiple registere~
outputs are switching in the same direction .
."
:::D
o
C
c:
o
-I
."
:::D
m
S
m
~
TEXAS .."
INSTRUMENTS
2-126
POST OFFICE BOX 866303 • DALLAS, TEXAS 75265
TlBPAL16l8·7M, TlBPAL16R4·7M, TlBPAL 16R6·7M, TlBPAL16RB·7M
TlBPAL 16LB·5C, TIBPAL 16R4·5C, TlBPAL 16R6·5C, TIBPAL 16R8·5C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications. algorithms. and the latest information on hardware. software. and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available. upon request. from the nearest TI field sales office. local
authorized TI distributor. or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Note 31
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. Each register is preloaded
individually by following the steps given below.
Step
Step
Step
Step
1.
2.
3.
4.
With VCC at 5 volts and Pin 1 at VIL. raise Pin 11 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1. clocking in preload data.
Remove output voltage. then lower Pin 11 to VIL. Preload can be verified by observing
the voltage level at the output pin.
~
w
preload waveforms (see Note 3)
PIN 11
______I
:>w
a:
~tsu~
!+- td --.I
i
I
I
I
I
I
I
I
I
I
I
I
I
I
..J'>-<
I-
I Inn: -r n-- -'.
I
:
REGISTERED I/O_ _ _ _
c:L
d-----1
'-- tw-.l
I
PIN 1
j4- t
'''~
o
~
c
oa:
Vil
c:L
I
B"-O-U-T-P-U-T-- : : :
NOTE 3: td ~ tsu ~ tw ~ 100 ns to 1000 ns.
V'HH = 10.25 V to 10.75 V.
TEXAS ",
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-127
TIBPAL16L8·7M, TIBPAL16R4·7M, TIBPAL16R6·7M, TIBPAL16R8·7M
TIBPAL 16L8·5C, TlBPAL 16R4·5C, TlBPAL 16R6·5C, TlBPAL 16R8·5C
HIGH·PERFORMANCE IMPACT·X'" PAL® CIRCUITS
f max SPECIFICATIONS
f max without feedback. see Figure 1
In this mode. data is presented at the input to the flip-flop and clocked through to the Q output with no
feedback. Under this condition. the clock period is limited by the sum of the data setup time and the data
hold time (tsu +th). However. the minimum f max is determined by the minimum clock period
(twhigh +twlow).
Thus. f max without feedback = (tw high + tw low)
ClK
lOGIC
ARRAY
"U
%I
o
C
c:
(')
-I
"U
%I
S
m
FIGURE 1. f max WITHOUT FEEDBACK
f max with internal feedback, see Figure 2
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition. the period is limited by the internal
delay from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
1
(tsu +tpd ClK-to-FB)
Where tpd ClK-to-FB is the deduced value of the delay from ClK to the input of the logic array.
Thus. f max with internal feedback =
ClK
=e
lOGIC
Q
ARRAY
FIGURE 2. f max WITH INTERNAL FEEDBACK
TEXAS •
INSTRUMENTS
2-128
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
TlBPAL 16L8·7M. TIBPAL16R4·7M. TIBPAL 16R6·7M. TlBPAL16R8·7M
TIBPAL 16L8·5C. TIBPAL 16R4·5C. TIBPAL 16R6·5C. TlBPAL 16RB·5C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
f max SPECIFICATIONS
f max with external feedback, see Figure 3
This configuration is a typical state-machine design with feedback signals sent off-chip. This external
feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest
path defining the period is the sum of the clock-to-output time and the input and setup time for the external
signals Itsu + tpd CLK-to-Q).
Thus, f max with external feedback =
1
Itsu +tpd CLK-to-Q)
CLK
a~-.....-4.NEXT DEVICE
LOGIC
ARRAY
~
I4-r----tsu------1+~-tPd CLK.to.a-+ tsu-1
w
:>w
FIGURE 3. f max WITH EXTERNAL FEEDBACK
IX
a..
tO
::::>
C
oIX
a..
FIGURE 4. PROPAGATION DELAY FROM ClK! to I/O, THRU lOGIC ARRAY
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-129
TIBPAL16L8·7M, TIBPAL16R4·7M, TIBPAL16R6·7M, TIBPAL16R8·7M
TlBPAL 16L8·5C, TlBPAL 16R4·5C, TIBPAL 16R6·5C, TIBPAL 16R8·5C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
5V
S1
b
2000
FROM OUTPUT _ . ._ ...._ ..._
UNDER TEST
CL
(See Note AI
3V
TIMING
,/.,
INPUT _ _ _ _J~~.~V_ _ _ _ 0
TEST
POINT
2000
HIGH'LEVEl~5V
-~;-v-3V
PULSE
.
DATA
~-; -::-: 3 V
INPUT - . / ' 1.5V
~O
"'tJ
LOW· LEVEL
PULSE
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
C
c:
(')
INPUT
-I
"'tJ
tpd
::D
m
S
m
~
-i1.5
IN·PHASE
~OUTPUT
tpd
II
OUT -OF· PHASE
OUTPUT
(See Note D)
I..
I
I
I
I
...
\1~~
V
- - - 3V
!1.5V
~
\1.5
'"
·1
.,
,
14
V
VOL
tpd
• FVOH
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DelAY TIMES
J/.::'""" 3 V
" "
OUTPUT~3V
1.5 V
I
ten -+I
--VOL
-1- - - - _. 0
I+-
, I
WAVEFORM 1
S1 CLOSED
(See Note BI
WAVEFORM 2
S10PEN
1.5 V
I
1
enabling I
tpd
~
I
0
~~'~V_O
(low-level
+--VOH
I
I
1
CONTROL
0
I
1
1
VOLTAGE WAVEFORMS
PULSE DURA TlO!"S
I
·1
I
~,
::D
o
.
I
I.---tw~
!4-th ....
I+-tsu-+j
1
-+l I+-- tdis
I I
25 V
I'
~.
I 1.5V
VOl+0.5V
~
,
'
--~
ten -+I
j+-
- - a - VOl
-+I 14tdis T.
I_-_*--VOH
~
(See Note BI
I
-
1.5 V
-
LVOH-O.5 V
~
0 V
VOL TAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE·STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pf for tpd and ten. 5 pF for tdis'
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR :$ 10 MHz, tr and tf ~ 2 ns, duty cycle ~ 50%.
D. When measuring propagation delay times of 3-5tate outputs, switch 51 is closed.
E. Equivalent loads may be used for testing.
FIGURE 5
TEXAS . "
INSTRUMENTS
2-130
POST OFFiCe BOX 655303 • DALLAS. TeXAS 75265
TIBPAL 16L8·1 OM. TIBPAL 16R4·1 OM. TIBPAL 16R6·1 OM. TIBPAL 16R8·1 OM
TIBPAL16L8· 7C. TIBPAL 16R4·7C. TIBPAL16R6· 7C. TIBPAL 16R8· 7C
HIGH·PERFORMANCE IMPACT-XTMPAL® CIRCUITS
D3115, MAY 19BB-REVISED OCTOBER 19B9
•
ITOP VIEW)
Vee
o
110
110
110
110
110
110
o
GND ......._ _...r-
•
Functionally Equivalent, but Faster than
Existing 20-Pin PALs
•
Preload Capability on Output Registers
Simplifies Testing
•
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•
TIBPAl1SlS'
M SUFFIX .. , J PACKAGE
C SUFFIX ... J OR N PACKAGE
High-Performance Operation:
f max (no feedback)
TIBPAL 16R' -7C Series ... 100 MHz
TIBPAL16R'-10M Series ... 62.5 MHz
f max (internal feedback)
TIBPAL 16R' -7C Series ... 100 MHz
TIBPAL 16R'-10M Series ... 62.5 MHz
f max (external feedback)
TIBPAL16R'·7C Series ... 74 MHz
TlBPAL 16R'-10M Series ... 55.5 MHz
Propagation Delay
TIBPAL 16L' -7C ... 7 ns Max
TIBPAL 16L'-10M ... 10 ns Max
TIBPAllSlS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
ITOP VIEW)
U
_ >u
3
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Security Fuse Prevents Duplication
•
Dependable Texas Instruments Quality and
Reliability
2
0
1 20 19
18
17
16
15
14
I/O
110
110
110
I/O
9 10 11 12 13
DEVICE
INPUTS
3·STATE
REGISTERED
1/0
o OUTPUTS
Q OUTPUTS
PORTS
PAl16l8
10
6
8
4 13·state)
4
PAl16R6
8
2
0
0
0
PA116R4
6 13-statel
2
PAl16R8
8
0
8 13-state)
0
Pin assignments in operating mode
description
These programmable array logic devices feature high speed and functional equivalency when compared
with currently available devices, These IMPACT-X" circuits combine the latest Advanced Low-Power
Schottky t technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes
for conventional TTL logic, Their easy programmability allows for quick design of custom-functions and
typically results in a more compact circuit board. In addition, chip carriers are available for further reduction
in board space.
All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow
loading of each register asynchronously to either a high or low state. This feature simplifies testing because
the registers can be set to an initial state prior to executing the test sequence.
The TIBPAL 16' M series is characterized for operation over the full military temperature range of - 55°C
to 125°C. The TIBPAL16' C series is characterized for operation from OOC to 75°C.
IMPACT-X"" is a trademark of Texas Instruments Incorporated.
PAL@ is a registered trademark of Monolithic Memories, Inc.
tlntegrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments. U.S. Patent Number 3,463,975.
This document contains information on products in
mora than ORa phase of development. The status of,
8ach device is indicated on the pagels) specifying its
electrical charletaristies.
Copyright © 1989, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-131
TIBPAL 16R4·1 OM, TIBPAL 16R6·1 OM, TIBPAL 16R8·1 OM
TIBPAL 16R4·7C, TIBPAL 16R6·7C, TIBPAL 16R8·7C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
TIBPAL l6R4'
TIBPAL16R4'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE
(TOP VIEW)
elK
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
Vee
I/O
3
2
1 20 19
I/O
Q
4
18
I/O
Q
5
17
Q
Q
6
16
15
Q
Q
14
Q
Q
I/O
8
I
I/O
GND '""L_ _..T"" BE
9 1011 1213
-
~Io
gg
<.'J
TIBPAL l6R6'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
TIBPAL 16RIl'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE
(TOP VIEW)
elK
(TOP VIEW)
Vee
110
Q
3
2
1 20 19
Q
4
18
Q
5
17
Q
6
16
8
14
Q
15
Q
I/O
GND'--l._ _....t-'0E
9 1011 1213
TIBPAL16R8'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
TIBPAL l6RS'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE
(TOP VIEW)
elK
Vee
Q
3
Q
Q
2
1 20 19
Q
4
5
17
Q
6
16
18
Q
15
Q
I
GND '""L-=-----=----J-'
14
B
Q
9 101" 12 13
DE
- 0lw
0
zO
<.'J
Pin assignments in operating mode
2-132
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75285
0
TIBPAl 16lB·1 OM, TlBPAl16lB·7C, TlBPAl 16R4·1 OM, TIBPAl16R4·7C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
functional block diagrams (positive logic I
'PAL16l8
EN ~1
&
k>-----o
32 X 64
P----o
16x
t>
10
I/O
16
0-.............-1/0
6
0-.-+.........-1/0
6
'PAlI6R4
OE
EN2
ClK
Cl
r--&
32
1"6.1>
8
4
~ 'V
r-+-
r+'--
x 64
r--+-
~
J
2'<;7
----,
10
r-+r-+r-+t---
'V
1-0
~1
8
----,
----,
----,
EN
a
a
a
a
~1
'<;7
~
I/O
f---y--
"
~
,
f-+-
t--+~
4
...
-"
I/O
I/O
I/O
4
rv
denotes fused inputs
TEXAS . "
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS, TEXAS 75265
2·133
TIBPAL16R6·10M, TlBPAL16R6·7C, TlBPAL16R8·10M, TIBPAL16R8·7C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
functional block diagrams (positive logic)
'PAL16R6
DE--------------------------clE!~--,
CLK------------------------------~
&
32 X 64
r---t----;b-:+--o
r---t----;b-:l-o
r---t----;~l-o
r----t----i-~_o
t----t----;h-..:1--o
....-t--
l-_....:s~~;b-ed-......--~-
110
110
6
.'PAL16R8
DE
CLK
;>1
a
a
a
16
a
a
a
a
a
rv denotes fused inputs
2-134
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16L8·1 OM,TlBPAL 16LB·7C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
111)
FIRST
FUSE
INCREMENT
,
0
N UMBERS
0
32 --
6.-
96-
4
----
--
B
12
16
20
24
- -
2B
31
--
f--
---- --
}--
128160
-f--/
192
22.
119)
V
o
)---
~~
~
256-
~ ~~r~1
288
320
]
-~
352
384
f----f-----'
416 -
448-
1/0
.80
illet--
=::'
512
544
576--
-
1
>---
608
640
>----
672
704
117)
V
1/0
>----
14) : 6
768
1
800~
832
864
896
928
116)
V
960
1/0
--
15) 992
.
~
1024
1056
1088
--
1120
- --
"52
1
>----
115)
V
1/0
•
f---
1184
1216
1248
~
-
1---
-
>---
1280
1312
-
1344
1376
-.,..
1440
1472
17)'504 - -
X
15361568
1600
1632 - 1664-
114)
---
~-----J'-.j
+
-
1/0
f--------j
----
_...
t
1696
1728
-
IB)1760
---
--
1792
1824
1S56
lS88
~1
----,f--/
~
First Fuse number
-..,
j---
t-=J----
-r
113)
1/0
>--
-
1920
1952
1984
Fuse number -
1
V
1408
112)
V
o
Ill)
+ Increment
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-135
TIBPAl 16R4·1 OM, TlBPAl16R4·7C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
ClK (11
FIRST
INCREMENT
FUSE
NUMBERS 0
4
8
12
16
20
24
28
0
32
64
9.
'28
,.0
'92
224
31
1
I
>--
I--"
1
v
(31 480
5'2
5
576
60
640
672
704
~
- >-
(41 736
7.8
800
832
864
896
.28
>-
••
1024
1056
1088
1120
P-
f---'
1152
""
1216
1280
1312
'3'
1376
'40
ro
-;::} (171
10
v
a
~~
'i':o
':l
(161
a
':l
(151
a
T:O ':l
10
(141
a
10
M
10
P-
t--
1440
1472
~~
1504
1536
1568
'600
'63
1664
'696
1728
1
f--
-
v
f--
1760
1BI
1792
1824
1856
1888
1920
r--
'95
'.84
(91 20 '6
-
2-136
I
110
~1
(61'248
Fuse number '""' First Fuse number
(181
~1
(51 992
(71
1/0
v
(2~
25.
288
320
352
384
4'.
448
(191
f-/
I
1
V
I
(131
(121
~
+ Increment
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1/0
1(0
nBPAL 16R6·1 OM. nBPAL 16R6·7C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
ClK .!..!.l{)
II}
F IRST
F USE
N UMBERS 0
INCREMENT
4
8
12
16
20
24
28
0
32
64
96
128
160
192
224
12!t,t----
Jl
1
>-
-
-
V
119}
1
1/0
2~
IJ}
14}
IS}
288
320
352
384
416
448
480
~
-
512
544
516
608
640
672
104
13.
)-
i:O
-;:t.118} Q
v
10
~I
j':(j
~117} Q
).. 10
~~
f--
168
800
832
864
896
928
960
992
V
j':(j
I--
)-
10
':I
116}
':I
lIS}
v
Q
~
~~
f-I--
1024
1056
1088
1120
1248
--
1280
f--
I--
1152
1184
1216
r'j':(i
)-
1312
1344
I--
1472
f--
V
Q
~~
16}
1376
1408
1440
10
j':(j
D-
'";:11 14 }
ID
V
Q
..:2.J
1504
17}
1536
1568
1600
f--
1632
-
1664
1696
1728
18}
p-
'j'";O
':1113}
10
v
Q
~1
1760
1792
>r--
1824
1856
1888
1920
-
1952
1984
19}2016
1
V
I
112}
I/O
--
1152
1184
1216
M
10
'";:1 (15)
v
Q
~1
16)'248
I--
1280
1312
1344
1376
1408
1440
f---'
p.. rr:o
10
f---'
1472
1504
1536
1568
1600
)..-...,
p~
1632
1664
1696
1728
'";:11 14 )
""\..>""
Q
~1
17)
r'j":Q
10
'"j
113)
I.:l.v
112)
Q
~1
18)1160
1792
>--
1824
1856
188
>-
1920
~
10
1952
1984
~~
19)2016
2-138
Q
~
1024
Fuse number - First Fuse number
Q
+ Increment
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALl.AS. TEXAS 75265
l..::),ill)
Q
TlBPAL 16L8·1 OM, TIBPAL 16R4·1 OM, TlBPAL 16R6·1 OM, TIBPAL 16R8·1 OM
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
absolute maximum ratings over operating free· air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 1 50°C
NOTE 1: These ratings applv except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
UNIT
MIN
NOM
MAX
4.5
5
5.5
V
5.5
V
Vee
Supply voltage
VIH
High-level input voltage (see Note 2)
VIL
low-level input voltage (see Note 2)
0.8
V
10H
High-level output' current
-2
rnA
10L
Low-level output current
Iclock
Clock frequency
tw
Pulse duration. clock (see Note2!
2
12
0
tsu
Setup time, input or feedback before CLKi
th
Hold time, input or feedback after eLKt
TA
Operating free-air temperature
I High
8
I Low
8
62.5
rnA
MHz
ns
10
ns
0
ns
55
25
125
~
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or
tester noise. Testing these parameters should not be attempted without suitable equipment.
PARAMETER
TEST CONDITIONS
Vee
~
4.5 V,
II
VOH
Vee
~
4.5 V,
10H
~
VOL
Vee
~
4.5 V,
10L
~
10ZH t
10Zl t
'0, Q outputs
I/O ports
0, Q outputs
I/O ports
II
I/O ports
IIH
I All others
Vee ~ 5.5 V,
~
Vo
~
~
~
5.5 V,
Vo
Vee
~
5.5 V,
VI
~
5.5 V
Vee
~
5.5 V,
VI
~
2.7 V
Vee
~
5.5 V,
VI
Vee
~
5 V,
Vo -
Vee
~
5.5 V,
Outputs open,
V
3.2
100
-20
-250
1
100
25
-0.08 -0.25
-30
~ VIH
2 V
0 V,
BE
ei
1 MHz,
VI
eo
f
~
1 MHz,
Vo
eclk
f
~
1 MHz,
VeLK ~ 2 V
ITA ~ 25 'e and 125 'e
-70
-130
140
220
I TA ~ -55'e
~
2 V
I-
o
::l
V
0.5
20
0.5 V
~
~
UNIT
-1.5
0.3
0.4 V
f
~
MAX
-0.8
0.4 V
IlL t
VI
Typt
2.7 V
Vee
~
2.4
-2 rnA
12 rnA
10S§
lee
MIN
-18 rnA
a:
c..
electrical characteristics over recommended operating free-air temperature range
VIK
->w
W
'e
250
C
o
V
a:
~A
c..
~A
rnA
~A
rnA
rnA
rnA
5
pF
6
pF
6
pF
t All typical values are at Vee ~ 5 V, TA ~ 25'e.
t I/O leakage is the worst case of 10ZL and IlL or 10ZH and IIH, respectively.
§ Not more than one output should be shorted at a time and duration of the short·circuit should not exceed one second. Set Va at 0.5 V
to avoid test equipment ground degradation.
PRODUCT PREVIEW documents contain information
on products in the formative or design ~h8se of
development. Characteristic dati Bnll othar
:::=':::1ri~~ d:ira:;:~rT~::~rl:::~:'~
. products without notica.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
2-139
TIBPAl 16lB·1 OM, TlBPAl 16R4·1 OM, TIBPAl 16R6·1 OM, TIBPAl 16RB·1 OM
HIGH·PERFORMANCE IMPACT·rM PAL@ CIRCuiTS
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted) (see Figure 5)
PARAMETER
FROM
fmax t
TO
MIN
Without feedback
62.5
With internal feedback (counter configuration)
62.5
With external feedback
55.5
tpd
I, I/O
0, I/O
tpd
ClKt
Q
tpd§
ClKt
Feedback input
ten
OE~
Q
tdis
OEt
Q
ten
I, I/O
0, I/O
~is
I, I/O
0, I/O
3
2
2
2
3
2
Typt
MAX
UNIT
MHz
6
10
ns
4
6
ns
5
ns
4
10
ns
4
10
ns
6
10
ns
6
10
ns
t All typical values are at VCC = 5 V, T A = 25°C.
:t:See section on f max .specifications.
§This parameter applies to TlBPAlI6R4' and TIBPAl 16R6' only (see Figure 2 for illustration) and is calculated from the measured f max
with internal feedback in the counter configuration.
"C
:D
o
o
n
c:
-I
"C
:D
m
S
m
~
PRODUCT PREVIEW do••menll .ontain information
on products in the formative or design phase of
development. Characteristic d8t8 anil othar
2-140 ~~:~:sri~~ ~~li::a=::I~r T:i::~:ur:~::
products without Rotica.
-II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIBPAL 16L8·7C. TIBPAL 16R4·7C. TIBPAL 16R6·7C. TIBPAL 16R8·7C
.
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . .
.... ....
. . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . .. oae to 75°e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 °e to 150 ae
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
Vee
Supply voltage
VIH
High-level input voltage (see Note 2)
V)l
Low-level input voltage (see Note 2)
10H
High-level output current
MIN
NOM
MAX
UNIT
4.5
5
5.25
V
5.5
V
2
0.8
-3.2
V
mA
24
mA
100
MHz
10l
Low-level output current
Iclock
Clock frequency
tw
Pulse duration, clock (see Note 2)
tsu
th
Setup time, input or feedback before CLKi
7
ns
Hold time. input or leedback alter elK!
0
ns
TA
Operating free-air temperature
0
0
I High
I low
5
ns
5
25
75
°e
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or
tester noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
-0.8
-1.5
V
0.5
V
Vee
~
4.75 V,
II
VOH
Vee
~
4.75 V,
10H ~ -3.2 mA
VOL
Vee
~
4.75 V.
10l
~
10ZH t
Vee
~
5.25 V.
Vo
~
2.7 V
100
~A
10Zlt
Vo
~
0.4 V
-100
~A
mA
II
Vee -- 5.25 V,
5.25 V.
Vee
IIHt
Vee
III t
Vee
10S§
Vee
Vee
lee
~
-18 mA
2.4
3.2
0.3
24 mA
V
VI
~
5.5 V
0.2
~
5.25 V,
VI
~
2.7 V
25
pA
~
5.25 V,
VI
~
0.4 V
-0.08 -0.25
mA
~
5.25 V,
Vo
~
5.25 V,
Outputs open,
~
VI
~
Typt
VIK
~
-30
0.5 V
0 V
ei
I
~
1 MHz,
VI
eo
I
~
1 MHz,
Vo
eclk
I
~
1 MHz,
VelK ~ 2 V
~
~
2 V
2 V
-70
-130
mA
160
210
mA
5
pF
6
6
pF
pF
t All typical values are at Vee ~ 5 V. TA ~ 25°e.
:t: 110 leakage is the worst case of IOZl and ItL or IOZH and ItH, respectively.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Set
Vo
at 0.5 V
to avoid test equipment ground degradation.
PRODUCTION DATA documanls contain information
current as of publication data. Products conform to
spacifications per the terms of TaXIs Instruments
:~~=~~i~a[;:'~~i ~=::i:f :,~O:::::£:is~ not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-141
TIBPAL 16L8-7C, TIBPAL 16R4-7C, T1BPAL 16R6-7C, TIBPAL 16R8-7C
HIGH-PERFORMANCE IMPACT-XTM PAL® CIRCUITS
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted) (see Figure 6)
PARAMETER
FROM
fmax t
TO
MIN
Without feedback
100
With internal feedback (counter configuration)
100
With external feedback
74
II
1 or 2 outputs switching
8 outputs switching
MHz
7
6
7.5
2
4
6.5
ns
3
ns
4
7.5
ns
4
7.5
ns
3
6
ns
2
6
9
9
tpd
ClK!
Q
tj)d§
ClK!
Feedback input
ten
OEI
Q
2
tdis
OE!
Q
2
ten
1,1/0
0,1/0
tdis
1.1/0
0,1/0
Skew between registered outputs
UNIT
5.5
1,1/0
tskew'
MAX
3
3
tpd
0, I/O
TYpt
0.5
ns
ns
ns
tAli typical values are at VCC ~ 5 V, TA ~ 25°C.
t See section on f max specifications.
§This parameter applies to TIBPAl 16R4' and TIBPAl 16R6' only (see Figure 2 for illustration) and is calculated from the measured f max
with internal feedback in the counter configuration.
'This parameter is the measurement of the difference between the fastes1 and slowest tpd (elK-lo-0J observed when multiple registared
outputs are switching in the same direction.
PRODUCTION DATA dooumont. oontlin informotion
cumnt at publiclltion data. Products confDrm to
lpecillOllio.. par tho
of To... InstrumORts
2-142 :'~~:~~~.i::::e ~:\~~i:r :'Io:::::~~.~. not
I'
te,.,.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
TIBPAL 16L8·1 OM, TIBPAL 16R4·1 OM, TIBPAL 16R6·1 OM, TlBPAL 16R8·1 OM
TIBPAL 16L8·7C, TIBPAL 16R4·7C, TIBPAL 16R6·7C, TIBPAL16R8·7C
HIGH·PERFORMANCE IMPACT·X'" PAL® CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. Each register is preloaded
individually by following the steps given below.
Step
Step
Step
Step
1.
2.
3.
4.
With VCC at 5 volts ano Pin 1 at VIL, raise Pin 11 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing
the voltage level at the output pin.
r\----V.,
preload waveforms (see Note 3)
PIN 11
---J/
...
·-----VIL
I+-tsu~
~td~
!+- td ---.I
If- tw -+I
I
I
PIN 1
i
I
I
- - - - - : - - - - - : 1 - -....·
I
I
L.---....;.--....;.------
>-<. ___
I
I
I
I
I
I
I
I
I
REGISTERED I / O - - - -....
I
I I----r-r----I
V
'"
VIL
I
I
I
IN_P_U_T_ _-.J8'-O-U-T-P-U-T-- : : :
NOTE 3: td ~ tsu ~ tw ~ 100 ns to 1000 ns.
VIHH ~ 10.25 V to 10.75 V.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-143
TIBPAL 16L8·1 OM, TlBPAL 16R4·1 OM, TIBPAL 16R6·1 OM, TlBPAL 16R8·1 OM
TlBPAL 16L8·7C, TIBPAL 16R4·7C, TlBPAL 16R6·7C, TIBPAL 16R8·7C
HIGH·PERFORMANCE IMPACT·X™ PAL® CIRCUITS
f max SPECIFICATIONS
f max without feedback. see Figure 1
In this mode. data is presented at the input to the flip·flop and clocked through to the Q output with no
feedback. Under this condition. the clock period is limited by the sum of the data setup time and the data
hold time (tsu +th). However. the minimum f max is determined by the minimum clock period
(twhigh +twlow).
Thus. f max without feedback =
(tw high +tw low)
or __1__ .
(tsu +th)
CLK
LOGIC
ARRAY
FIGURE 1. f max WITHOUT FEEDBACK
f max with internal feedback. see Figure 2
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition. the period is limited by the internal
delay from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
Thus, f max with internal feedback
=
1
(tsu +tpd ClK-to~FB)
Where tpd ClK-to-FB is the deduced value of the delay from ClK to the input of the logic array.
CLK
LOGIC
Q
ARRAY
r-tsu--~~II4-"-tPd CLK-to-FB ~
FIGURE 2. f max WITH INTERNAL FEEDBACK
2-144
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 76265
TlBPAL 16LB·1 OM, TlBPAL 16R4·1 OM, TlBPAL 16R6·1 OM, TIBPAL 16RB·1 OM
TIBPAL 16LB· 7C, TIBPAL 16R4·7C, TIBPAL 16R6·7C, TIBPAL16RB·7C
HIGH·PERFORMANCE IMPACT·X'M PAL~ CIRCUITS
f max SPECIFICATIONS
f max with external feedback, see Figure 3
This configuration is a typical state-machine design with feedback signals sent off-chip. This external
feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest
path defining the period is the sum of the clock-to-output time and the input and setup time for the external
signals (tsu +tpd CLK-to-Q).
Thus, f max with external feedback =
1
(tsu + tpd CLK-to-Q)
ClK
af--r-I. NEXT DEVICE
lOGIC
ARRAY
I4-r----tsu------t~M..-tpd ClK-to-a-+- tsu-1
FIGURE 3. f max WITH EXTERNAL FEEDBACK
.-
-
>--
-
->0
_
Cl
>--
1
-
-
""'
~
a
1/0
I
FIGURE 4. PROPAGATION DELAY FROM CLKi to I/O, THRU LOGIC ARRAY
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-145
TIBPAl 16l8·1 OM, TIBPAl 16R4·1 OM, TIBPAl 16R6·1 OM, TlBPAl 16R8·1 OM
TIBPAL16l8·7C, TlBPAl16R4·7C, TlBPAl16R6·7C, TIBPAl16R8·7C
HIGH·PERFORMANCE IMPACT·X™ PAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
5V
5V
S1
b
S1
b
39011
20011
fROM OUTPUT
UNDER TEST
_+_..._ ..._
CL
(See Note Al
TEST
POINT
fROM OUTPUT
UNDER TEST
_+_..._ ..._
CL
(See Note Al
39011
LOAD CIRCUIT fOR
C SUffiX DEVICES
TEST
POINT
75011
LOAD CIRCUIT fOR
M SUffiX DEVICES
[3.5VlI3Vl
~---[3.5VlI3VI
TIMING
I 5 V
HIGH·LEVEL
I 5 V
15 V
INPUT _ _ _ _JU _. _ _ _ _ _ [0.3 Vl (01
PULSE
I
.
I'
[0.3 Vl (01
~
I+--tw~
I4-th-+t
.~~
I
DATA~.-1-_-[3.5Vl(3VI
1.5 V
INPUT
1.5 V
[0.3 Vl (01
I
LOW·LEVEL
15 V I S V
PULSE"
- - - -
VOLTAGE WAVEfORMS
SETUP AND HOLD TIMES
,..----.......
INPUT
.!II1.5
..J:
tpd
IN-PHASE
OUTPUT
OUT-Of-PHASE
OUTPUT
ISee Note 01
-
-
-
- - [3.5 Vl (3 VI
\1.5 V
I ' - - - - - [0.3
I..
I
:+--VOH
I
.1
I
I
1".1
I"~
f1.5V
,\1.5 V
.
VOLTAGE WAVEfORMS
PROPAGATION DELAY TIMES
tpd
~
I
1
VOL
tpd
Vl (01
OUTPUT ~[3.5Vl(3VI
CONTROL
1.5V
1.5V
(low·level
I
_1 _ _ _ _ _ _ [0.3 Vl (01
enabling I
I
I
ten
I+-+t 14-- tdis
--+I
- - VOL
i
I :
I
=3.3 V
WAVEfORM1~1.5V
I
.c--VOL+0.5V
I
S1 CLOSED
(See Note BI
FVOH
.
[0.3 Vl (01
VOLTAGE WAVEfORMS
PULSE DURATIONS
1".1
:
tpd
V
I
~I [3.5Vl(3VI
WAVEfORM 2
S10PEN
ten-+!
I
J4-
-+I
__ ..1_
- -"X" ~ tdis T.
' _____ i-=
~
(See Note BI
VOL
VOH
I
1.5 V
LVOH-0.5 V
=0 V
VOLTAGE WAVEfORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten· 5 pF for ldis·
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR '" 10 MHz. tr and tf = 2 ns. duty cycle = 50%. For M suffix. use
the voltage levels indicated in parentheses ( ). For C suffix, use the voltage levels indicated in brackets [ J.
D. When measuring propagation delay times of 3-state outputs, switch 51 is closed.
E. Equivalent loads may be used for t~sting.
FIGURE 5
2-146
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIBPAL 16L8·1 O'M, TIBPAL 16R4·1 OM, TIBPAL 16R6·1 OM, TlBPAL 16R8·1 OM
TIBPAL16L8·7C, TlBPAL16R4·7C, TlBPAL16R6·7C, TIBPAL16R8·7C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
8
200r-~--~--~--+-~r--+--_r--;
15.
160
I
4
r--
.~
.
140
3
!:}
.;:
2
120r-~--~--~--+---r--+--_r--;
100L-~--~--~--~
-75 -50 -25
0
25
o
__~~__~~
50 75 100 125
I
"E
j::
..
;;
5.25
4.75
5
VCC-Supply Voltage-V
FIGURE 6
FIGURE 7
4.5
c
0
7
14
VCC = 5 V
TA = 25°C
R1 = 200 f!
12
R2 = 390 f! ----'----t;,.,.c.'---r-=--i
I
~\, \1
6
4 -
-
Co
2
Ol
0.
o
.,
\10 )
01.00'~
W~...---r-
5 -tPlH (I, 1/0 to 0, 1/0)
3
e
PROPAGAT)ON DELAY TIME
vs
LOAD CAPACITANCE
16r---~--~----~--~--~--~
~
.
5.5
8
>
c
to 0, 1/0)
to 0, 1/0)
TA-Free-Air Temperature- °C
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
.,c
(I, 1/0
(I, 1/0
tPlH (ClK to Q)
TA = 25°C
CL = 50 pF
R1 = 200 f!
R2 = 390 f!
1 OUTPUT SWITCHING
Ol
g.
U
tpHl
tPlH
~PHl (ClK to Q)
)
)
c
Co
::0
CI)
~
6
>
$
U
5
.
!
7
.,
'I
"
~
tjHl TlK to Q)
-I---"
,--:c~O)
tl'lH \
--
II
'I
"E
j::
.
~
10r---~---f--~T7~~~~~~
>
8r---~~~~~~~_r--~----;
tPlH (ClK to Q)
c
.~
6 r--7''-i>o'~~~--='FtPHL (eLK to
I
Ol
:g,
VCC = 5 V
Cl = 50 pF
R1 = 200 f!
R2 - 390 f!
1 OUTPUT SWITCHING
e
tPHl
(I, 1/0
Q)
I
to 0, 110)
4r-~G----*--~~--~---;----;
0.
2r----r--~----+---_r--__i----;
OL---~--~--~----~--~--~
-75 -50 -25
0
25
50 75 100 125
TA-Free-Air Temperature- °C
o
100
200
300
400
500
CL -load Capacitance-pF
600
FIGURE 9
FIGURE 8
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-147
TlBPAl 16l8·1 OM, TlBPAl 16R4·1 OM, TlBPAl 16R6·1 OM, TIBPAl 16R8·1 OM
TIBPAl16l8·7C, TIBPAl16R4·7C, TIBPAl16R6·7C, TlBPAl16R8·7C
HIGH·PERFORMANCE IMPACT·X'" PAL® CIRCUITS
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
FREQUENCY
8-BIT COUNTER MODE
1000
V
~
E
900
I
c:
I
TA =
.."0co
Q
OJ C
TA
~
f..--' ~ V ~/
V
800
lD
'"
:E
"'i
III
~ .....
TA = 25°C
Q.
c:
I
c:
./
,/
'i)j
III
.
~J
II
1CC
0.6
CL - 50 pF
8-Bit Counter
~d
o"c::.:~0
04
.
"U
~ - 0.3
......
= 80°C
.
0
...C
VCC - 5 V
TA = 25°C
R1 = 200 {J
R2 = 390 {J
0.7
a- 0.5
3:
...I
0.8
!!
V'
....V
SKEW BETWEEN OUTPUTSt
vs
NUMBER OF OUTPUTS SWITCHING
.Q
..
3:
700
....
0.2
I
.
0.1
.!f
0
III
3:
....
600
1
4
10
F-Frequency-MHz
2
100
40
3
4
6
7
5
Number of Outputs Switching
FIGURE 10
FIGURE 11
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
8
.
7
.I.
c:
I
6 r-tpHL (I. I/O to O. I/O)
j::
5 -tpLH
.E
+ • ++
(I. I/O to O. I/O)
>
co
a;
C
tpHl \CLK to 0)
4
c:
0
.~
'"
3
co
Q.
...e
VCC = 5 V
TA = 25°C
CL = 50 pF
R1 = 200 {J
R2=390{J
2
o
o
ttH1K~
234
5
6
7
Number of Outputs Switching
FIGURE 12
t Output switching in the same direction (tpLH compared to tpLH/tpHL to tpHL)
2-148
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
8
TlBPAL 16L8·12M, TlBPAL 16R4·12M, TlBPAL 16R6·12M, TlBPAL 16R8·12M
TlBPAL 16L8·1 DC, TlBPAL 16R4·1 DC, TlBPAL 16R6·1 DC, TIBPAL 16R8·1 DC
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
D3023, MAY 1987 - REVISED NOVEMBER 19B9
•
•
TIBPAL16LB'
M SUFFIX ... J PACKAGE
C SUFFIX, .. J OR N PACKAGE
High·Performance Operation:
f max (w/o feedback)
TIBPAL16R'-10C Series ... 62.5 MHz
TIBPAL 16R'-12M Series ... 56 MHz
f max (with feedback)
TIBPAL 16R'-10C Series ... 55.5 MHz
TIBPAL 16R'-12M Series ... 48 MHz
Propagation Delay
TIBPAL 16L-10C ... 10 ns Max
TIBPAL 16L·12M . . . 12 ns Max
ITOP VIEW)
Vee
0
liD
liD
liD
liD
liD
Functionally Equivalent, but Faster than
Existing 20·Pin PALs
liD
I
0
GND
•
Preload Capability on Output Registers
Simplifies Testing
•
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
TIBPAL 16LB'
M SUFFIX, , . FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEWI
U
u
_>0
3
2
1 20 19
•
Security Fuse Prevents Duplication
18
•
Dependable Texas Instruments Quality and
Reliability
17
INPUTS
3·STATE
REGISTERED
I/O
o OUTPUTS
Q OUTPUTS
PORTS
PAL16L8
10
2
0
6
PAL 16R4
8
0
4 (3·state)
4
PAL16R6
8
0
6 (3·state)
2
PAL16RB
8
0
8 (3·state)
0
OEVICE
6
16
liD
7
15
liD
8
14
liD
9 10 11 12 13
Pin assignments in operating mode
description
These programmable array logic devices feature high speed and functional equivalency when compared
with currently available devices. These IMPACT'" circuits combine the latest Advanced Low-Power
Schottky t technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes
for conventional TTL logic. Their easy programmability allows for quick design of custom-functions and
typically results in a more compact circuit board. In addition, chip carriers are available for further reduction
in board space.
All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow
loading of each register asynchronously to either a high or low state. This feature simplifies testing because
the registers can be set to an initial state prior to executing the test sequence.
The TIBPAL 16' M series is characterized for operation over the full military temperature range of - 55 DC
to 125 DC. The TIBPAL16' C series is characterized for operation from 0 DC to 75 DC,
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories, Inc.
tlntegrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments, U.S. Patent Number 3,463,975.
Copyright @ 1989, Texas Instruments Incorporated
PRODUCTION DATA documents contain information
currant as of publication date. Products conform to
specifications per the terms of Texas Instruments
::':=:~~i~ar::1~7e ~!=:~ti:r :1~O;:~:::::t:~~ not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-149
TIBPAL 16R4·12M, TlBPAL 16R6·12M, TlBPAL 16R8·12M
TIBPAL16R4·1 DC, TIBPAL 16R6·1DC, TlBPAL 16R8·1 DC
HIGH~PERFORMANCE IMPACTTMPAL® CIRCUITS
TIBPAL lSR4'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE
(TOP VIEW)
elK
TIBPAllSR4'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
>£
Vee
...J
110
GND ""'l._ _...1"'"
u
uo
_U>;;:,
liD
3
2
1 2019
Q
4
18
110
Q
5
17
Q
Q
6
16
Q
Q
7
15
Q
110
110
8
14
Q
9 1011 1213
DE
-
~I~ ~ ~
(,:J
TIBPAL lSRS'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE
nBPAllSRS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW I
(TOP VIEW)
elK
Vee
>£
U
...J uo
_ _ U>;;:,
110
Q
3
2
1 20 19
Q
GND
18
Q
5
17
Q
6
16
Q
7
15
Q
8
14
110
DE
9 10 11 12 13
TIBPAL lSRS'
M SUFFIX ... J PACKAGE
C SUFFIX ... J OR N PACKAGE
(TOP VIEW)
elK
TISPAllSRS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
>£
Vee
Q
3
2
1 20 19
Q
4
18
Q
5
17
Q
6
16
Q
7
15
Q
8
14
Q
9 1011 12 13
GND ' - _ - - ' r DE
- 20
ClIW a a
(,:J
Pin assignments in operating mode
2·150
U
...J U
__ u>o
Q
I
Q
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TlBPAL 16LB·12M, TIBPAL 16LB·1 OC, TIBPAL 16R4·12M, TIBPAL 16R4·1 OM
HIGH·PERFORMANCE IMPACpMPAL® CIRCUITS
functional block diagrams (positive logic)
'PAl16lS
&
EN "01
b-----o
32 X 64
0..----0
16x!>
10
I/O
16
P--.+........-I/O
........-I/O
o-~
b-e+........-I/O
o..e+.......-I/O
b-e+.......-I/O
6
'PAl16R4
J EN2
oE
1: C1
ClK
r---s;32X 64
J:
;>1
8
t-+-
1-°2'\71,.,.
r--,
10
f-+
~
8
4
r+-
~ "v
P-f~
"v
Q
t----"I
~
Q
1---'1
f-fI--
~
Q
t----"I
EN
;>1
.....
'\7
~
f--,L
"\
~
~
f-+-4
4
rv denotes
I/O
I/O
I/O
f--+-
f
o
-
"'
I/O
fused inputs
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·151
TIBPAl16R6·12M, TlBPAl16R6·1 DC, TIBPAl16R8·12M, TIBPAl16R8,·1 DC
HIGH·PERFORMANCE IMPACT ™PAl® CIRCUITS
functional block diagrams (positive logic)
'PAL 16R6
DE
_"EN2
ClK
~8
32 X 64
'"
;;'1
f-+-
Cl
1-0 2
10
~
-:-~~ 'V
-+~
-
~ 'V
Q
---.,
Q
~
----....
----....
R-
---.,
Q
~
J;....
-
Q
Q
r---.
r---.
I'"
EN ;;'1
-4---
+
\7
.
.
Q
110
110
2
6
'PAL 16RS
DE-------------------------aErU---,
CLK--~------------------------~
r;;;.;;-1--,.....M~~--
Q
t---T---1:r--:t-Q
r--,--b--+-r--I--"'b--+-r--I--"'b--+--
Q
Q
Q
r---r----1tr.-.:~Q
rv denotes
2-152
fused inputs
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TIBPAL 16LB·12M, TlBPAL 16LB·1 OC
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
INCREMENT
FIRST
~~~BERS
0
0-
32 --
4
8
-.
l-
.. -
12
16
20
24
28
31
.
60
96'28 - '60
'92
-
f---
>-
(191 0
,........f-'
220
2320--56
~
288
3523840'6
448
060
0t>t=
512-
677326
(1811/0
f-
1
.-
544
576·
608640 .-
700
(41
(171 1/0
768
BOO832
860
896
928
960
992
I---
(16 1 1/0
1--1-7
~
>--
1024
1058
1088
1120
-
1152
-
11841216
1248
~
~">-_JI»..----,(c:.1=51
1/0
-
1
'376
j
,-'536'~ll·gj·I--lllllml~~1~_~
1280
13'2
,-
'344
11411/0
i">-
~
1472
'440
==::d<}--"(7~It'5~00~=fEt1=~Et~=EEtl==EEt~~Ett=~rft=~=EE=~=t~~~~
'-
1568
~
~
'632--
16641696-
-
v
-t-
1
(1311/0
~~~g~-~-~lt~~!J~~-trt~~··11~+.t~r-!11l~~t1~~t1~~c["t"JrJ:~--·""!"i~~t::-~~JI1 ___r"'
.!!4>t=
=::::j(J--
1192
'856
1984
(91~--1=~+=~~+=~~+=4=~+=~~~-J.--+_
I
I
I"
(121
-
. 1.[ -+
'~:~g
952
--v"b--1
.--.J
.-
,~o
>--V
7~+-t-(.++----+...
0
)-t=-=-=J--
576
p>--
608
640
672
704
(4) 736
7:0
~17) a
10
~~
768
800
832
86.
896
928
>--
p-
I-ii
10
~
(16)
a
I.JV
(15)
a
b
(14)
a
·V
>--
960
~~
(5) 992
>--
1024
1056
1088
1120
1152
1184
1216
>--
b-
>--
b-
----'
1408
1440
~
1412
.......,...
1-0
10
V
~1
----1
(7)'504
10
~~
(6)1~
1280
1312
1344·
1376
i:O
~
1536
1568
1600
16321664
1696
1728
~
..
.-/
J
(13)
~ 1
liD
(8)1760
1792
1
1824
1856
1888
1920
1952
1984
9
~
2016
~
2-154
I
~)
I
Fuse number .. First Fuse number
V
(12)
+
Increment
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
110
TIBPAL 16R6·12M, TIBPAL 16R6·1 DC
HIGH·PERFORMANCE IMPACpMPAL® CIRCUITS
cLKl1),{>----------------______________________________________~
FIRST
INCREMENT
~~~BERS~O------4-----B-----1-2----~1-6-----20-----2-4-----2-8--3--1
~L t1
96 . -
L i··. ~--
!-
~.::=
-
j
:
=}-t=--p.- I---lr- .J.!.!I1
J
·t-mm-ilmEmBf§=W
160
128*'
192--
f---
f--
.--
288 -.
~~~
,
. --t
'r--
_-{j----1
--~--=-t>
---
.--
-2 (18)
\00
+
-- -I~k~
'J
:~= ~~~fi~~~~11~~~};~~~-~-ft~~~~~~~~-"~~~~~C~1~~
~~ .
- = l--tItt=lttt1±1tlt1 r-.---->- "i':'O b
-
!~:
512
. _
Q
_
:~~
v
10
672
704
--
'-~
+-
768
110
~~\-- __
----t=)....--l
256
..
_.
(17)
Q
>-}--
:~~-t>
I-ii
:::
}-10 -
~
(16)
Q
928
::~
-~
c-=
+- _ _
i~::~g~~ag~··-BiEg~~fa-~--En+-
1120=
1152
--:::tt~=t+tt=1+~t
~hl
_~ -.-,--J<.i-k"l-+-_.-..J
-
+.
~-1~ 'j':Q
10
b
1-I-.,J.15) Q
f-"
mr~-j·r-tJrrr~--+~-'ii~+--tl--11~~L;C1h
I~-=t
__
-H-++---+
1280
1312
1344-·
I v
-
T
I--+~..
~!~:-
-
>---<
-
>---c:>
.-1=0
10
~
(14)
--J>o!=
Q
1440
(7)~:~!~HE]Ia3~I--=ifif~3iff-j-ft=tiEfEEtFgf----<~~_tt~
~-=tttl+~·~~~l1jjt~t!t!=3~~=itJ1=~f*~~~~f=3~-~-"
- b
t·· .1568=
16001632--
_.
.--
-
-··,-T7+ , ..
t·-
~:::---I-+-+_i-+---__I__+_I_+__ - -t-:r--~t-
g!~-
+- - H
(8)'~2
~:~:
I
H--
+-
,
H-- t
T"
~b-
f-
-t-
H-T-~
.--
1-0
10
t
>
C
1
t~H't -~~
-+-f-.L.
I
--f-+++-
1888
19201952
1984
-.
+-
t--
>--
-+
+--~
---f++-+--l--i-+-t---r-T'" +
,
-+-- i--+-+'---t--
_
_
-~.:.:J...
(9)~',fl---:::t::!!.-l----+1IIT-t7-:;-:
j
-+ t-t-t-+~+-~
~ t t--t 1 r--J +t-r-tn++ i r l t i i -r tt--t-
)---
Q
~
r-i-.+-+-r-·.~i--+~·~+~~~~~~~I~~~~~~~t-11
:. W
r+
....
t , 4--t-··
(13)
II-
--'~
1/0
~=-J:::J-------- I (l1)OE
•.
~
A
Fuse number - First Fuse number + Increment
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-155
TlBPAL 16R8-12M, TIBPAL16R8·10C
HIGH-PERFORMANCE IMPACTTMPAl® CIRCUITS
I
Fuse number -
2-156
First fuse number
INCREMENT
r-
l-Itt-
8
12
f--t
16
20
f---
.
t-
+ Increment
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TIBPAL 16L8·12M, TlBPAL 16R4·12M, TIBPAL 16R6·12M, TIBPAL 16R8·12M
HIGH·PERFORMANCE IMPACT'MPAl® CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
5.5
V
Vee
Supply voltage
VIH
High-level input voltage Isee Note 21
VIL
Low-level input voltage (see Note 2)
0.8
V
10H
High-level output current
-2
rnA
2
10L
LOW-level output current
fclock
Clock frequency
tw
Pulse duration, clock (see Note 2)
tsu
th
Setup time, input or feedback before CLKt
Hold time, input or feedback after CLKt
TA
Operating free-air temperature
0
I High
I Low
12
rnA
56
MHz
9
9
ns
11
ns
ns
0
-55
25
125
°e
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system andlor
tester noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
Vee
VOH
Vee
VOL
Vee
10ZH~
Vee
10ZL ~
Vee
II
Vee
= 4.5
= 4.5
= 4.5
= 5.5
= 5.5
= 5.5
=
II
V,
= -2 rnA
= 12 rnA
Vo = 2.4 V
Vo = 0.4 V
VI = 5.5 V
V,
V,
V,
IIH~
Vee - 5.5 V,
Vee
10S§
Vee
=
=
lee
Vee
Cin
C out
f
f
eilo
f
=
=
=
eeLK
f
= 1 MHz,
2.4
10H
10L
V,
IlL ~
MIN
-18 rnA
V,
VI
= 2.4 V
5.5 V,
VI
=
5 V,
Vo
= 5.5 V,
VI
= 0.5 V
1 MHz,
1 MHz,
Vila = 2 V
1 MHz,
VeLK
MAX
UNIT
-0.8
-1.5
V
3.2
0.3
0.4 V
= 0,
VI = 2 V
Vo = 2 V
Typt
-30
Outputs open
= 2V
V
0.5
V
100
~A
-100
~A
0.2
rnA
25
~A
-0.08 -0.25
rnA
-70
-250
rnA
140
220
rnA
5
pF
6
pF
7.5
pF
6
pF
t All typical values are at Vee = 5 V, TA = 25°e.
~ 110 leakage is the worst case of 10ZL and IlL or 10ZH and IIH, respectively.
§ Not more than one output should be shorted at a time and duration of the short~circuit should not exceed one second. Set
Vo at 0.5 V
to avoid test equipment ground degradation.
TEXAS ."
INSTRUMENTS
~"(J;)T
mFICE BOX 655012 • DALLAS, TEXAS 75265
2-157
TlBPAL 16LB-12M, TIBPAL 16R4-12M, TIBPAL 16R6-12M, TIBPAL 16RB-12M
HIGH-PERFORMANCE IMPACTTMPAL® CIRCUITS
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
fmax~
I
MIN
TVPt
With Feedback
48
80
Without Feedback
56
85
3
7
12
ns
2
5
10
ns
1
1
3
2
4
4
10
10
14
12
ns
FROM
TEST CONDITIONS
TO
tpd
1,1/0
0,1/0
tpd
ClK!
Q
ten
OEI
OE!
1,1/0
I, I/O
Q
tdis
ten
tdis
Rl
R2
= 390 II,
= 750 Il,
See Figure 1
Q
0,1/0
0,1/0
t All typical values are at VCC = 5 V, TA = 25°C,
t f max (with feedback)
2-158
=
tsu
1
+ tpd (ClK to
Q)
, f max (without feedback)
=
.
tw high
1
+ tw low
TEXAS ~
INSTRUMENTS
POST OFfICE BOX 655012. DALLAS, TEXAS 75265
.
8
8
MAX
UNIT
MHz
ns
ns
ns
TIBPAL 16L8-1 DC, TIBPAL 16R4-1 DC, TlBPAL 16R6-1 DC, TIBPAL 16R8-1 DC
HIGH-PERFORMANCE IMPACT ™ PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) ................................................... 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range ...................................... ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
Vcc
Supply voltage
VIH
V)L
High-level input voltage (see Note 2)
10H
High-level output current
10L
Low-level output current
Iclock
Clock Irequency
tw
Pulse duration, clock (see Note 2)
tsu
Setup time, input or feedback before CLKf
th
Hold time, input or leedback after CLKi
TA
Operating free-air temperature
MIN
NOM
MAX
UNIT
4.75
2
5
5.25
5.5
0.8
-3.2
24
62.5
V
Low-level input voltage (see Note 2)
0
8
8
10
0
0
I High
I Low
V
V
mA
mA
MHz
ns
ns
ns
25
75
°c
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include a/l overshoots due to system and/or
tester noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TVpt
MAX
-1.5
2.4
-0.8
3.2
0.3
UNIT
VIK
Vee = 4.75 V,
11= -18 mA
VOH
Vee - 4.75 V,
10H -
VOL
Vee = 4.75 V,
10L = 24 mA
10ZHt
Vee = 5.25 V,
Va = 2.4 V
10ZL t
VCC = 5.25 V,
Va = 0.4 V
II
Vee = 5.25 V,
VI = 5.5 V
IIHt
Vee = 5.25 V,
VI = 2.4 V
25
~A
IlL t
Vee = 5.25 V,
VI = 0.4 V
-0.08 -0.25
mA
10S§
Vec = 5 V,
Vo = 0
Ice
Vec = 5.25 V,
1 - 1 MHz,
VI = 0,
1 = 1 MHz,
1 = 1 MHz,
1 = 1 MHz,
Va = 2 V
Cin
Caut
Cilo
CCLK
-3.2 mA
-30
Outputs open
VI = 2 V
Vi/o = 2 V
VCLK = 2 V
-70
140
5
6
7.5
6
V
V
0.5
V
100
-100
0.2
~A
-130
180
~A
mA
mA
mA
pF
pF
pF
pF
t All typical values are at VCC = 5 V, TA = 25 °e.
t 1/0 leakage is the worst case 01 10ZL and IlL or 10ZH and IIH, respectively.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-159
TIBPAL 16L8·1 OC, TIBPAL 16R4·1 ~C, TIBPAL 16R6·1 OC, TIBPAL 16R8·1 OC
HIGH·PERFORMANCE IMPACT™PAL® CIRCUITS
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
FROM
TO
TEST CONDITIONS
With Feedback
fmax*
Without Feedback
tpd
1,1/0
0,1/0
tpd
CLKt
ten
OE<
OEt
1,1/0
1,1/0
a
a
a
tdis
ten
tdis
t All typical values are at VCC
* f max (with feedback)
= tsu
Rl
R2
= 390 n,
= 750 n,
See Figure 1
0,1/0
0,1/0
MIN
55.5
62.5
3
TYpt
MAX
80
85
7
10
ns
2
5
8
no
1
1
4
4
8
8
10
10
10
10
3
3
UNIT
MHz
no
no
ns
ns
= 5 V, T A = 25 DC.
1
C K ) ' f max (without feedback)
+tpd( L toO
=
1
h' h i '
tw.g +tw ow
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information'on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
2-160
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TlBPAl16lB·12M, TIBPAl16R4·12M, TIBPAl16R6·12M, TIBPAl16RB·12M
TIBPAl 16lB·1 DC, TlBPAl 16R4·1 DC, TIBPAl 16R6·1 DC, TlBPAl 16RB·1 DC
HIGH·PERFORMANCE IMPACT'MPAL® CIRCUITS
preload procedure for registered outputs (see Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state·machine sequence. Each register is preloaded
individually by following the steps given below.
Step
Step
Step
Step
1.
2.
3.
4.
With Vee at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing
the voltage level at the output pin.
preload waveforms (see Note 3)
PIN 11
i\----"'"
----II
!t-tsu~
jf- t
j+- td ........t
14- tw -+I
I
I
I
PIN 1
I
----~--_:_----I
I
I
...
·----VIL
d---1
I
I
I
I
LI_-_-_-.....;..:_-_:_-_-_-_-_-_-_
I
I
I
I
I
I
I
I
I
I
I
I
VIH
VIL
REGISTERED I / O - - - - - - X
..._ _ _I_N_PU_T_ _....J8'-O-U-TP-U-T-- : : :
NOTE 3: td = tsu = tw = 100 ns to 1000 ns.
VIHH = 10.25 V to 10.75 V.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·161
TlBPAL 16L8·12M. TIBPAL 16R4·12M. TIBPAL 16R6·12M. TIBPAL 16R8·12M
TIBPAL 16L8·1 DC. TlBPAL 16R4·1 DC. TIBPAL 16R6·1 DC. TlBPAL 16R8·1 DC
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
CL
(See Note A)
R2
LOAD CIRCUIT FOR
3-STATE OUTPUTS
[3.5 V] (3 V)
TIMING
INPUT
'/1.5V
4·
[0.3 V] {OJ
HIGH-LEVEL
PULSE
- ------"'I~
,.~
,.~ r.:.:.:
~-:-::-
[3.5 V] (3 V)
~
[0.3 V] {OJ
INPUT
I
-..Ii
tpd
1.5V
- - - \.. 1.5V
,
IN-PHASE
,
OUTPUT,
1/
T
1.5V'
,
I~~,
tpd~
OUT-OF-PHASE
OUTPUT
{See Note OJ
\L' \ 1.5V
----
-
[3.5 V] (3V)
OUTPUT
CONTROL
(low-level
~
1.5 V
[3.5 V] (3 V)
[0.3 V] (OJ
ten
H
VOL
~,tpd
Tv::-:
V OH
1.5V
--VOL
II
~-
--.I!+-
,
t dl
,"
I "\
I
-+!
I
.
I+-
.-
-
-
-
.-+!UI+-
WAVEFORM-l--+'''''V:+ 1.5V - ,
Sl CLOSED
I
(See Note B)
tdl.-.i
ten
WAVEFORM 2
S10PEN
(See Note B)
[3'5V]{3v)
1.5 V
,
enabling)
~V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
[0.3 V] {OJ
VOLTAGE WAVEFORMS
PULSE DURATIONS
1\
[0.3 V] {OJ
i4--+I- tpd
, J __ Va
-l+--+I
[3.5 V] (3 V)
I
LOW-LEVEL~I
I
PULSE
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
L
y
It-- Iw --.I
tsu~th
DATA~1.5V
INPUT
y
v-:t..-I+-
Y..
A L
, -*
----
=3.3V
VOL
VOL +0.5 V
-
~-
1.5 V
[0.3 V] {OJ
OH
L.- VVOH -0.5 V
-OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for t"d and t.n , 5 pF for t dlS '
B. Waveform 1 is for an output with internal conditions such thatthe output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For M suffix. use the voltage levels indicated in parentheses ( ), PRR ~ 10 MHz,
t, and tf S 2 ns, duty cycle = 50%. For C suffix, use the voltage levels indicated in brackets [], PRR s 1 MHz, t f = tf = 2 ns, duty
cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be fused for testing.
FIGURE 1
2-162
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TIBPAL 16R4-1 DC, TIBPAL 16R6-1 DC, TIBPAL 16R8-1 DC
HIGH-PERFORMANCE IMPACTTMPAL® CIRCUITS
metastable characteristics for TIBPAL16R4-1 OC, TIBPAL16R6-10C, and TIBPAL16R8-1 OC
At some point in every system designer's career, he or she is faced with the problem of synchronizing
two digital signals operating at two different frequencies. This problem is typically overcome by
synchronizing one of the signals to the local clock through use of a flip-flop. However, this solution presents
an awkward dilemna since the setup and hold time specifications associated with the flip-flop are sure
to be violated. The metastable characteristics of the flip-flop can influence overall system reliability.
Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and
is said to be in the metastable state if the output hangs up in the region between V,l and V,H. This metastable
condition lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified
maximum propagation delay time (ClK to Q maxi.
From a system engineering standpoint, a designer cannot use the specified data sheet maximum for
propagation delay time when using the flip-flop as a data synchronizer - how long to wait after the specified
data sheet maximum must be known before using the data in order to guarantee reliable system operation.
The circuit shown in Figure 2 can be used to evaluate MTBF (Mean Time Between Failure) and .a.t for a
selected flip-flop. Whenever the Q output of the OUT is between 0.8 V and 2 V, the comparators are in
opposite states. When the Q output of the OUT is higher than 2 V or lower than 0.8 V, the comparators
are at the same logic level. The outputs of the two comparators are sampled a selected time (Lit) after
SClK. The exclusive OR gate detects the occurrence of a failure and increments the failure counter.
NOISE
GENERATOR
... -
:
DATA
IN
OUT
----,
10
VIH
MTBF
COUNTER
COMPARATOR
I
I - h.....-f
I
I
I
I
I
SClK------H~C1
+
Vil
COMPARATOR
:
I
I _____ JI
L
SClK + A t - - - - - - - - - - - - - - - - - - - <....- - - - - - - t
FIGURE 2. METASTABLE EVALUATION TEST CIRCUIT
In order to maximize the possibility of forcing the OUT into a metastable state, the input data signal is
applied so that it always violates the setup and hold time. This condition is illustrated in the timing diagram
in Figure 3. Any other relationship of SClK to data will provide less chance for the device to enter into
the metastable state.
-
DATA
SClK
-
•
I
SClK
+
I
I
-+'__....~--------L----J'---'.~:----
At _ _ _ _
I
I
I
I
~~~
~~~
MTBF _
TIME (SEC)
# FAILURES
tree -
(1,1/0 to 0,1/0)
'"
6~~--+-~-+-~r--+-~--4
Qj
6
0
c
o
c
0
~
[
.,
c
5
-;
i 4........::::t:==:::c:::::::p....-rr""4--j-----j
5
''""
Q.
E
Q.
£
4
4
3~~_~_~_~_~~_-L~
3
- -
------
4.5
-75 -50 -25
0
25
50
75 100 125
T A -Free-Air Temperature- °C
tPHL II,II? to 0,1102-
~
tPlH 11,110 to 0,110)
I
tPHL (CLK to Q ) _
J
tPLH (CLK to Q ) -
4.75
5
5.25
5.5
VCC-Supply Voltage-V
FIGURE 5
FIGURE 6
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
11
VCC _ 5 V
10
R1 - 200 {) --+--+---+--+---+----1
R2 - 390 [J
~
9
~
8 I- T A = 25 °C
~
Cl - 50 pF
See Figure 1
g
i
£
-~ \,,\"\\.
\\,\\0 \0
'
0 \10\ f---
__ --~\\,~
i;'
~
~\\O\ ~
~1
7
6
__
51-""
--~
I
4
1
I
lC~K
to Q) _
tpLH ICLK to Q) - : - -
3L-~_~
1
2
_
_L_~_~~_-L~
3
4
567
8
Number of Outputs Switching
FIGURE 7
'Ii1
TEXAS
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-165
TIBPAl 16l8·1 DC, TIBPAl 16R4·1 DC, TIBPAl 16R6·1 DC, TlBPAl 16R8·1 DC
HIGH·PERFORMANCE IMPACT™PAL® CIRCUITS
TYPICAL CHARACTERISTICS
POWER DISSIPATION
PROPAGATION DELAY TIME
vs
vs
FREQUENCY
a-BIT COUNTER MODE
LOAD CAPACITANCE
b
900
16
VCC - 5 V, TA - 25°C
R1 - 2000, 1 Output Switching--:!.,..--I
f
14
R2 - 3900
See Figure 1
E
j::
12
In
..
I0'l-~7"'---b~-t-----1
0'\
....0
>
.!!!
f---+-- ~~~0~~-7~
~
....~+."
'~
'"
~
'in
8
.!!
~
1----,H~-7"I--____".f<'
"
~
~
S!
D.
6
f---""---¥-~--+---+---+------1
I
700 -TA - 25°C
I
I
c
D.
__
100
200
300
400
500
CL -Load Capacitance-pF
2L-_~_-L_~
o
TAI~
600
L-_~_~
----rr
TA - OOC
C
IV
C.
~I
~ 800
7'
~ 1 0 I----+-----:A~_,;.TI:
VCC - 5 V
1
600·
I I
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
UNPROGRAMMED DEVICE
1701---4---+--+--+--1---+--+---1
~ 1601---+--t-~~f-+--1---+--+------1
I
~1501--~~~-~~~-1---+--+---1
§
u140r-~-~~-+-~~~~~---+---1
~
c.
c.
~1301--~---+~~~~~~~~~--1
I
~1201-----1---+---+---~~~-+~~~
__-L__~__L-~L--L__-L~
-75 -50 -25
0
25 50 75 100 125
TA-Free-Air Temperature- °C
100L-~
FIGURE 10
2-166
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
V
V
.....
~
v
10
4
F-Frequency-MHz
FIGURE 9
FIGURE 8
~
........... ~
...........
40
100
TlBPAl16lS-15M. TIBPAl16R4-15M. TlBPAl16R6-15M. TIBPAl16RS-15M
TIBPAl16lS-12C TIBPAl16R4-12C TIBPAl16R6-12C TIBPAl16RS-12C
HIGH-PERFORMANCE IMPACT™ PAl® CIRCUITS
03338, JANUARY 1986-REVISED AUGUST 1989
•
•
TIBPAL 16LS'
M SUFFIX ... J OR W PACKAGE
C SUFFIX ... J OR N PACKAGE
High-Performance Operation
Propagation Delay
M Suffix, , . 15 ns Max
C Suffix, , , 12 ns Max
(TOP VIEWI
Vee
Functionally Equivalent, but Faster than
PAL16L8B, PAL16R4B, PAL16R6B, and
PAL16R8B
o
•
Power-Up Clear on Registered Devices
(All Registered Outputs are Set High but
Voltage Levels at the Output Pins Go Low)
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Dependable Texas Instruments Quality and
Reliability
DEVICE
INPUTS
3-STATE
REGISTERED
o OUTPUTS
Q OUTPUTS
PAL 1618
10
2
0
liD
I/O
liD
liD
liD
liD
o
GND
- " ' _ _...r-"
TIBPAL 1 6LS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEWI
1/0 PORTS
u
u
__ >0
6
PAL16R4
8
0
4 (3-state)
4
PAL 16R6
8
0
6 (3-statel
2
PAL16R8
8
0
8 (3-state)
0
3
2
1 20 19
4
18
17
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices.
These IMPACT'" circuits combine the latest
Advanced Low-Power SChottky t technology
with proven titanium-tungsten fuses to provide
reliable, high-performance substitutes for
conventional
TTL
logic.
Their
easy
programmability allows for quick design of
"custom" functions and typically results in a
more compact circuit board, In addition, chip
carriers are available for further reduction in
board space.
I/O
I/O
6
16
I/O
7
15
I/O
14
liD
8
9 1011 1213
Pin assignments in operating mode
The TIBPAL16' M series is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The TIBPAL 16' C series
is characterized for operation from DOC to 75°C.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories, Inc.
t Integrated Schottky-Barrier diode-clamped transistor is patented
by Texas Instruments, U.S. Patent Number 3,463,975.
PRODUCTION DATA d.cumants c.ntoin information
curreRt 8S of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
nacessarily include testing of all parameters.
Copyright © 1989, Texas Instruments Incorporated
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-167
TlBPAL 16R4·15M, TlBPAL 16R6·15M, TIBPAL 16R8·15M
TIBPAL 16R4·12C, TlBPAL 16R6·12C, TlBPAL 16R8·12C
HIGH·PERFORMANCE IMPACTTNPAl® CIRCUITS
TIBPAL 16R4'
M SUFFIX •.. J OR W PACKAGE
C SUFFIX ••. J OR N PACKAGE
TIBPAL 16R4'
M SUFFIX •.. FK PACKAGE
C SUFFIX .•• FN PACKAGE
(TOP VIEW)
(TOP VIEW)
Vee
elK
" u
UO
__ ..J
u>::::
110
110
3
2
1 2019
Q
18
Q
17
Q
Q
16
Q
110
Q
7
15
Q
110
110
8
14
Q
9 1011 12 13
GND""L_.......J,.....OE
-
~I~
gg
t:)
TIBPAL 16R6'
M SUFFIX ... J OR W PACKAGE
C SUFFIX ... J OR N PACKAGE
TIBPAL 1SRS'
M SUFFIX ..• FK PACKAGE
C SUFFIX ••. FN PACKAGE
(TOP VIEW)
(TOP VIEW)
" u
UO
__ ..J
u>::::
Vee
elK
110
3
Q
I
2
1 2019
Q
4
18
Q
Q
5
17
Q
Q
6
16
Q
Q
7
15
Q
Q
8
14
Q
110
9 1011 12 13
GND'-1.._ _..J-'0E
-
~I~
gd
t:)
TIBPAL 16RS'
M SUFFIX ... J OR W PACKAGE
C SUFFIX ..• J OR N PACKAGE
TlBPAL 1SRS'
M SUFFIX •.. FK PACKAGE
C SUFFIX .•• FN PACKAGE
(TOP VIEW)
(TOP VIEW)
~.t3
__ u>d
Vee
elK
Q
3
Q
GND
-....._---'r-
Q
5
17
Q
Q
6
16
Q
Q
7
15
Q
Q
8
14
Q
18
9 1011 12 13
DE
-
0IW d d
zO
t:)
Pin assignments in operating mode
2·168
1 2019
4
Q
I
2
Q
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265
TlBPAL 16L8·15M, TIBPAL 16L8·12C, TIBPAL 16R4·15M, TIBPAL 16R4·12C
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
functional block diagrams (positive logic)
'PAL16L8
&
EN ;;'1
"70-------0
32 X64
0-----0
I>
10
0-...........-1/0
16
P-ti.......-I/O
P-ti"'",,-I/O
D-e+......-I/O
o--tH.......-
I/O
o--tH.........-I/O
6
'PAL16R4
OE------------------------------~
CLK------------------------________
~
&
10-------0
32X 64
I>
8
,-r--h--+--
0
t--t--""b--+-o
16
[)---II---- 0
4
4
P - " - - H - t - - I/O
o-.............- t - - I / O
o-..............- t - - I / O
o-.............- t - - I / O
4
rv denotes
fused inputs
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-169
TIBPAL16R6·15M, TIBPAL16R6·12C, TIBPAL16R8·15M, TlBPAL16R8·12C
HIGH·PERFORMANCE IMPACTIMPAl® CIRCUITS
functional block diagrams (positive logic)
'PAL l6R6
_[N2
r, C1
OE
ClK
&
32X 64
-:-c;- -::- 'V
~
2.,...
;;'1
44-
10
1-1 2
~
~ 'V
a
Q
r----,
4-
Q
r----.
~
-
a
r-'
r----.
r----.
Q
r----,
~
Q
;;'1
- EN
~
r----,
'V
f--
~
~
......
~
2
r
I/O
I/O
...
6
~
'PAL l6RS
~------------------------clEi~~
ClK--~------------------------~
r;;;';;1-r:I=~7b---
i--;---"b--+-i--;---"b--+-r--;---b--+-r--;---"b--+-i--;---b--+--
Q
Q
Q
Q
Q
Q
r---r----1~~Q
rv denotes
2-170
fused inputs
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TIBPAL 16L8·15M, TIBPAL 16L8·12C
HIGH·PERFORMANCE IMPACTTM PAl® CIRCUITS
Ill)
FI RST
FUSE
INCREMENT
,
NUMBERS 0
4
0
32
64
96128
160
192
22.
12lbt-~
8
12
16
20
24
28
31
--
-.-
)--:--
I---"
'.-./
------
]
119)
V
o
I---"
;~
288320 - 352
38.
416
448
480
.0ct:
512-
544
~r-....
1
118)
V
1/0
-
-
576·
h
608
640
672
704
14) 736
1
117)
V
1/0
f--
768
800
832
864
896
928
960
IS) 992
------
1024
1056
1088
1120
1152
'184
1216
-:>-
1
116)
V
J
115)
1/0
1/0
I---"
16)'248
1280
1312
1344
1376
1408
1440
1472
>--
1--
~
>--
,........
1
114)
1/0
17)'50'
1536
>--
1568
1600
16321664
1696
>--
1728
IB)1760
=d--
1856
1888
1920
1952
113)
J
1
112)
V
1/0
o
>--
1984
~
Fuse number - First Fuse number
1
+==J--p.
'28
119) 1/0
'60
>--
'92
224
~
256
288
320
352
118) I/O
384
4'6
448
131 480
512-544
576
608
640
672
704
D-
R
117)
-yoa
t'j""1
10
~~
(4) 736
>--
768
800
832
D-
864
896
10
928
960
(5) 992
>--
1024
1056
1088
1120
1152
1184
1216
>-->
>--
16)'248
IT
>-;:.J.
115)
~
(14)
v
10
a
~~
1280
1312
1344
1376
-yo-
1408
1440
1472
1504
a
>--
(7) ;>t.
15361568
1600
1632-
--~
1664
18)
1696
1728
1760
r-
J
I
113) 1/0
--d'J
1792
1824
1856
r/>---r>oln
1888
1920
1952
9
1984
2016
~.
Fuse number
2-172
1 __1
'."1.":'2) 1/0
=
t=---::d
FIRST
INCREMENT
FUSE
NUMBERS 0
4
8
12
16
---)
20
24
28
I
31
j!~~=.fit[atri~~~1f-~H++=ttf:--tiHl_-1-~i~-i~~=E~L=ErtEC- S=~nj~ ~t~1~:E-k3~~~
E~~ c---t
-~-+-- +- ~"--_J
5------d
-==t-
~~: _
-+
"
_
m_' 1 ~ r~
::~~- If~~tt=+~~
320
13'{)t~
t
~
rr= ~
t+-
' __
~
~ "~~~
,~
r--
F1
j--
-
I-
-
-+ ~
736
r=b- '~1
10
}----
--
r---
1~~=§~~-BB3EfB
~
1024
-
~
t=
----'
--
~
"84~~
~
1216
1248
-
~I~-
~-t-, -
b-
'T1~
115 10
1D
~I'l
-~ :J
L...
- t - ,
116 10
1D
'--
1088
~~~~
ITtl
>C1
~
-+-~++++--+++-+
1 OS6
1171 0
~
'~---t>==:
928
I
"
C11'1
r---
~-
~++++-+~4~-4~
::~_--
I
"'J
>----
-f:::=-
672
704
m
:::
~1
- B~~Ffn=f~$4nffFfF~I-~=t=> 1~ ~Io
'1+-t--:;: ~~ "'~~:
~+~~~' -1
" i=ttlLiti__
-1--
512
1/0
,
'
1280-~-
1312
13761344-
1408
14401472
1504
~--=
+-~
15361568
1600-16321664
181
+
}--b-~ ~IO
+-
1696==tEllttEE±t:-+j''
1728
1760
Fuse number -
First Fuse number
---+-
-
~
+ Increment
TEXAS
l!}
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-173
TIBPAL 16R8·15M. TIBPAL 16R8·12C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
CLK~.
--_. . _ - - - - - - -
INCREMENT
FIRST
FU SE
NU MBERS
0
8
4
12
16
20
24
28
31
I
0
32
64
96
128
>
'60
192
'j";'"i
'-;::] (19)
10
V
a
~'1
(2~
';~
288
f---
320
352
384
4'.
448
>
f---
~-
..........
>--
608
640
672
f----'
704
V
a
TT
10
I.J
(17)
a
I.J.....
(16)
a
b
(15)
a
v
~~
(4) 736
768
800
832
864
896
928
All.!)
10
~~
f---
5'2
544
57.
'T=1
~
-
p-
960
T=T
10
~~
5) 992
(X
~
1024
'056
1088
1120
1152
1184
1216
"j':"i'"
I----'
D-
V
~~
(6)'248
'280
1312
"j':"i'"
\--
'344
D-
1376
1408
'440
1472
1536
---\
1568
1800
1832
---1
----"
t>
1664
1696
1728
---1
1792
1824
1856
=>t-
r-~) a
"j':"i'"
'";:J
10
T1
10
I
Fuse number - First Fuse number + Increment
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
a
-~) a
~'1
(9)=:?'·
(13)
V
~1
(8)1780
~
1888
1920
1952
1984
10
~1'1
\--
(7)'504
2-174
10
~)
TIBPAL 16L8-15M, TIBPAL 16R4-15M, TIBPAL 16R6-15M, TIBPAL 16R8-15M
HIGH-PERFORMANCE IMPACTTM PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions (see Note 21
PARAMETER
VCC
Supply voltage
VIH
Vil
High-level input voltage
Low-level input voltage
MIN
NOM
MAX
4.5
5
5.5
V
V
V
2
10H
High-level output current
5.5
0.8
-2
10l
Low-level output current
12
fclock
Clock frequency
tw
Pulse duration, clock (see Note 2)
tsu
Setup time, input or feedback before elKi
th
TA
Hold time, input or feedback after ClK T
0
I High
I low
50
9
mA
mA
MHz
ns
10
15
ns
0
-55
Operating free-air temperature
UNIT
ns
125
°c
NOTE 2: The total clock period of ClK high and ClK low must not exceed clock frequency. fclock. Minimum pulse durations specified
are only for ClK high or ClK low, but not for both simultaneously.
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK
VCC
VOH
Vce
VOL
Vec
10ZH
Outputs
1/0 ports
Outputs
10Zl
II
IIH
1/0 ports
=
=
=
4.5 V,
TEST CONDITIONS
II = -18 mA
10H = -2 mA
4.5 V,
10l
4.5 V,
=
=
5.5 V,
Va
=
2.7 V
VCC
=
5.5 V,
Va
=
0.4 V
Vee
=
=
5.5 V,
5.5 V,
VI
VI
=
=
2.4
Typt
5.5 V,
VI
=
10S*
Vec
5.5 V,
Vo
ICC
VCC
=
=
5.5 V,
VI
= 0.5
= 0,
V
0.5
-250
Pin 1, 11
0.2
All others
0.1
Pin 1, 11
50
1/0 ports
100
20
-0.25
All others
=
V
100
-20
2.7 V
Vee
UNIT
20
5.5 V
III
MAX
-1.5
3.3
0.35
12 mA
Vce
Vee
MIN
1/0 ports
0.4 V
-0.2
All others
-30
V
Outputs open
170
V
~A
~A
mA
~A
mA
-250
mA
220
mA
t All typical values are at Vce = 5 V, T A = 25°e.
tNat more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Set Va at 0.5 V
to avoid test equipment degradation.
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-175
TIBPAL 16L8·15M, TlBPAL 16R4-15M, TlBPAL 16R6-15M, TIBPAL 16R8-15M
HIGH-PERFORMANCE IMPACpM PAL® CIRCUITS
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
FROM
TO
fmax~
!Pd~
1,110
0,110
tDd
CLKt
Q
ten
DEI
OEt
Q
1,110
1,110
0,110
0,110
tdis
ten
tdis
Typt
MAX
8
15
ns
R1 = 3900,
7
12
ns
R2 = 7500,
See Figure 1
8
12
12
ns
ns
15
ns
15
ns
TEST CONDITIONS
MIN
50
Q
UNIT
MHz
7
8
8
tAli typical values are at VCC = 5 V, TA 25°C.
1:Maximum operating frequency and propagation delay are specified for the basic building block. When using feedback, limits must be
calculated accordingly.
2-176
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16L8-12C, TIBPAL 16R4-12C, TIBPAL 16R6-12C, TlBPAL 16RB-12C
HIGH-PERFORMANCE IMPACTTM PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 75°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions (see Note 2)
PARAMETER
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
10H
High-level output current
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
5.5
V
2
0.8
-3.2
10L
Low-level output current
fclock
Clock frequency
tw
Pulse duration, clock Isee Note 21
tsu
Setup time, input or feedback before CLKt
th
Hold time, input or feedback after CLK!
0
TA
Operating free-air temperature
0
0
I High
I Low
V
mA
24
mA
62
MHz
7
ns
8
10
ns
75
ns
DC
NOTE 2: The total clock period of CLK high and CLK low must not exceed clock frequency, fclock. Minimum pulse durations specified
are only for CLK high or CLK low, but not lor both simultaneously.
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
VCC
VOH
VCC
VOL
VCC
10ZH
Outputs
I/O ports
Outputs
10ZL
I/O ports
VCC
Vce
= 4.75
= 4.75
= 4.75
=
=
V,
II = -18 mA
10H = -3.2 mA
V,
IOL
V,
5.25 V,
5.25 V,
Vo
Va
=
=
=
Typt
0.35
5.25 V,
VI
=
5.5 V
IIH
Vce
=
5.25 V,
VI
=
2.7 V
IlL
Vce
5.25 V,
10*
Vee
lec
Vce
=
=
=
= 0.4 V
Va = 0.5 V
VI = 0,
UNIT
V
V
0.5
20
100
-20
0.4 V
=
MAX
-1.5
3.3
2.7 V
Vce
5.25 V,
2.4
24 mA
II
5.25 V,
MIN
-250
~A
~A
Pin 1, 11
0.1
All others
0.1
Pin 1, 11
20
All others
20
-0.2
mA
-125
mA
200
mA
VI
-30
Outputs open
V
170
mA
~A
tAli typical values are at Vee = 5 V, TA = 25 De.
.
+The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.
TEXAS •
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS, TEXAS 75285
2-177
TIBPAL 16L8-12C, TlBPAL 16R4-12C, TIBPAL 16R6-12C, TIBPAL 16R8-12C
HIGH-PERFORMANCE IMPACTTM PAl® CIRCUITS
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
fmax~
tpd~
tod
ten
tdis
ten
tdis
FROM
TO
TEST CONDITIONS
MIN
TYpt
MAX
8
7
8
7
8
8
12
10
10
10
12
12
62
1,1/0
CLKt
OE.
OEt
1,1/0
1,1/0
t All typical values are at VCC
0,1/0
Q
Q
Q
Rl
R2
=
=
500 II,
500 II,
See Figure 1
0,1/0
0,1/0
=
5 V, T A
=
UNIT
MHz
ns
ns
ns
ns
ns
ns
25°C.
:l:Maximum operating frequency and propagation delay are specified for the basic building block. When using feedback, limits must be
calculated accordingly.
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of ·programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 995-5666.
2-178
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TlBPAl16l8·15M, TlBPAl16R4·15M, TIBPAl16R6·15M, TIBPAl16R8·15M
TlBPAl16l8·12C, TIBPAl16R4·12C, TlBPAl16R6·12C, TIBPAl16R8·12C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
5V
S1
b
R1
FROM OUTPUT
UNDER TEST
_+_.._ ..._
TEST
POINT
R2
CL
(See Note A)
LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
/..
TIMING
INPUT _ _ _
---'~
1 5 V
1 5 V
~
.
.
---[3.5VI(3V)
[3.5 VI (3 V)
jf1.5V
_ _ _ _ _ [0.3 VI (0)
HIGH-LEVEL
PULSE
:_
1.5V
1.5V
LOW-LEVEL~I [3.5 VI (3V)
PULSE
1.5V
[0.3 V) (0)
-
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
r----"\
INPUT
../1 1.5 V
tpd
I..
I
~I
I
: f
IN-PHASE
OUTPUT
1
tpd
l1li
- - - - [3.5 VI (3 V)
~
1' - - - - [0.3 V) (0)
I..
~I tpd
1
1 . 5V :
1
I"
OUT-OF-PHASE
OUTPUT
(See Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
+--VOH
~
I
~I
-
1.5V
- -
[0.3 VI (0)
VOLTAGE WAVEFORMS
PULSE DURATIONS
\1.5 V
---I:
[0.3 VI (0)
tw
DATA~.-1---[3.5VI(3V)
INPUT
I
r- 4
I+-th~
1
)4-tsu-+t
VOL
---+I
I!
IIi
VOH
7'1.5 V
--VOL
~3.3
V
WAVEFORM1---r\: 1.5V
l~vOL+0.5V
S1 CLOSED
I ~-==:!-= VOL
(See Note B)
t en -+1 ~
I4- t dis
VOH
WAVEFORM 2
I
S10PEN
1.5 V
LVOH-0.5 V
-.!
tpd
:r.:-:-I
OUTPUT ~[3.5VI (3 V)
CONTROL
1.5 V
1.5 V
(low-level
I
enabling)
1
-1- - - - [0.3 VI (0)
ten
r+~ I+-- tdis
l.
~
(See Note B)
' _____ i-=
~0
V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE·STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis'
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For M suffix, use voltage levels indicated in parentheses (),
PRR :s 10 MHz, tr and tf :S 2 n5 , duty cycle = 50%. For C suffix, use the voltage levels indicated in brackets [ ],
PRR s 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
O. When measuring propagation delay times of 3-state outputs, switch 51 is closed.
E. Equivalent loads may be used for testing.
FIGURE 1
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-179
-
2-180
TIBPAL 16Lo·20M, TIBPAL 16R4·20M, TIBPAL 16R6·20M, TIBPAL 16Ro·20M
TIBPAL 16Lo·15C, TIBPAL 16R4·15C, T1BPAL 16R6·15C, T1BPAL 16Ro·15C
HIGH·PERFORMANCE IMPACpM PAl® CIRCUITS
03340, FEBRUARY 1984- REVISED AUGUST 1989
nBPAl16l8'
M SUFFIX ... J OR W PACKAGE
C SUFFIX ... J OR N PACKAGE
(TOP VIEW)
•
High-Performance Operation
Propagation Delay
M Suffix , , , 20 ns Max
C Suffix. , . 15 ns Max
•
Functionally Equivalent, but Faster than
PAL16L8A, PAL16R4A, PAL16R6A, and
PAL16R8A
•
•
Vee
0
I/O
I/O
I/O
Power-Up Clear on Registered Devices
(All Registered Outputs are Set High but
Voltage Levels at the Output Pins Go Low)
I/O
I/O
I/O
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
INPUTS
3·STATE
REGISTERED
o OUTPUTS
Q OUTPUTS
PAL 16lB
10
2
PAl16R4
PAl16R6
B
B
0
0
0
4 (3·state)
6 (3-state)
4
PAl16RB
B
0
B 13-state)
0
DEVICE
I/O PORTS
0
I
GND
TIBPAl16l8'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
6
U
u
__ >0
2
3
description
These programmable array logic devices feature
high speed and a choice of either standard or
half-power devices, They combine Advanced
Low-Power Schottky t technology with proven
titanium-tungsten fuses. These devices will
provide reliable, high-performance substitutes
for conventional TTL logic. Their easy
programmability allows for quick design of
"custom" functions and typically result in a
more compact circuit board. In addition, chip
carriers are available for further reduction in
board space.
2 1 20 19
4
18
5
17
16
7
15
8
14
9 10 11 12 13
The PAL 16' M series is characterized for
operation over the full military temperature range
of - 55°C to 125°C, The PAL 16' e series is
characterized for operation from ooe to 70°C.
tlntegrated Schottky-Barrier diode·clamped transistor is patented by Texas Instruments, U.S. Patent Number 3.463,975.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.
PRODUCTION DATA d••umants .lHII8in information
.u"ent es of publlcatio. date, Products .onfarm to
specifications per the terms of TaXIS Instruments
:=~::i~·i~:~~i =~~:i:r :.r:.~:::::.:::.s not
Copyright © 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
2-181
TIBPAL 16R4·20M,TIBPAL16R6·20M, TlBPAL 16RB·20M
TIBPAL 16R4·15C, TlBPAL16R6·15C, TIBPAL 16RB·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
TIBPAL 16R4'
M SUFFIX •.. J OR W PACKAGE
C SUFFIX ••• J OR N PACKAGE
TIBPAL 16R4'
M SUFFIX ..• FK PACKAGE
C SUFFIX .•• FN PACKAGE
ITOPVIEW)
(TOP VIEW)
elK
tl 0
__ :J
u>:::
Vee
I/O
110
3
2
1 20 19
Q
4
18
Q
5
17
Q
6
16
Q
7
15
110
110
8
14
9 1011 1213
GND '-L=-----.:...JI-' 6E
TIBPAL 16R6'
M SUFFIX .•. J OR W PACKAGE
C SUFFIX ... J OR N PACKAGE
TISPAL 16R4'
M SUFFIX ... FK PACKAGE
C SUFFIX .•. FN PACKAGE
(TOP VIEW)
(TOP VIEW)
elK
~ u
....I uo
__ u>:::
Vee
I/O
3
Q
2
1 20 19
Q
18
Q
17
Q
16
Q
15
Q
14
110
9 1011 1213
GND .......___I-'0E
TIBPAL 16RS'
M SUFFIX ... J OR W PACKAGE
C SUFFIX ... J OR N PACKAGE
TIBPAL 16RS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
(TOP VIEW)
elK
Vee
Q
Q
3
2
1 20 19
Q
Q
Q
Q
Q
Q
9 10 "
GN D '-L=---'-:":'I-' DE
2-182
TEXAS .",
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265
12 13
TIBPAL 16LB·20M, TlBPAL 16LB·15C, TIBPAL 16R4·20M, TIBPAL 16R4·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
functional block diagrams (positive logic)
'PAL16L8
EN .><1
&
32 X64
vb-----o
b-----o
b-_ _.....-I/O
16
b-.-+.........-
I/O
b-,.;.......-I/O
h-a-I._ _-
I/O
b-+l-
8
a
16
a
4
;;'1
4
V
I/O
I/O
I/O
I/O
4
rv
denotes fused inputs
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-183
TIBPAL 16R6·20M, TIBPAL 16R6·15C, TIBPAL 16R8·20M, TIBPAL 16R8·15C
HIGH·PERFORMANCE IMPACTTM PAl® CIRCUITS
functional block diagrams (positiva logic)
'PAL16R6
~----------------------~~~--,
CLK----------------------------~
r;;;;--r"j":'i'771o--Q
r----t----~~-Q
r----t----~_l_-
Q
r---r--;~~Q
r---r--;~~Q
~-....::2:r-~""""'I--
1/0
P-....t.......--t--
1/0
'PAL16RB
~----------------------~da~__,
CLK--~------------------------_P
&
32 X 64
8
r;;;.;;l-r'i':"~~---
Q
r----r----~~-Q
8
rv denotes fused inputs
2-184
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16LH·20M, TIBPAL 16LH·15C
HIGH·PERFORMANCE IMPACTTM PAl® CIRCUITS
1(1 )
INCREMENT
FI RST
FU SE
0
4
o-
r--
N UMBERS
32 -64
8
12
16
20
24
28
31
--
---
)---
-
.6128
160
,.2
22.
-j
(19)
) - -I-"
o
)--
Ett--2:'288
320-352
384416
448
480
I--
:--'
1
(18)
v
110
illt>t=
512
544
576
608
640
.72
704
-
I-"
1
(17)
v
110
t--
(4);
7.8
800
832
884
8 ••
.28
-I-"
1
(16)
v
110
.60
(5) ••2
1024
1056
1
0--
1088
1120
1152
(15)
v
110
1184
1216
(6)'248
1280
1312
1
1344
1376
1408
1440
(14)
v
1/0
1472
~
(7)'504
1536
1568
1600
)--
'.32-
~
1664
1696
(8)
">
(13)
110
)--
1728
1780
1792
1824
1856
1888
1920
1952
~
1984
(9)201.
Fuse number - First Fuse number
J
1
(12)
V
o
~
+
Increment
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-185
TIBPAL 16R4·20M, TlBPAL 16R4·15C
HIGH·PERFORMANCE IMPACT'M PAL® CIRCUITS
ClK (11 "FIRSr
F
~~BERS
N
INCREMENT
4
'0
0
32
6.
96128- .
160
192
22.
12
8
16
20
24
28
31
-]
f----
---
!--"
v
i
\--A
~
256
288320
352
38.
"6
"8
'80
l
~
~
~--
(181 1/0
V
t::-
f---
512
544
516
608
640
612
10'
(41 136
~
=>-
TT
10
I.J.
,..-
(171
a
~
(161
a
bIv
(151
a
~~
-'A
768
800
832
86'
890
928
960
992
f----
P-
T="T
10
V
~~
\--
1 (51 1::>1.
OA
-
1024
1056
1088
\--
1'20
"52
1184
1216
1248
1 (61
(191 1
/0
b-
T1
10
~
X
1280
1312
1344·
P-
1376
1408
~~
1472
1504
1 JZI
1536
1568
f----
1600
-
1632~
.--
../
10641696
1728
(81
-
1760
l
(131
1/0
Vi
-~
1792
1824
r-
1856
1888
1920
1952
I-...
)-
,.84
2016
9
I%.:_
1
1
Fuse number "'" First Fuse number
2-186
t{>,(14 1a
10
f----
1440
1
"i"'""i"
I
+
I
I
Increment
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
-'-A
j
(121
1
110
~10E
TIBPAL 16R6·20M, TIBPAL 16R6·15C
HIGH·PERFORMANCE IMPACT'M PAl® CIRCUITS
-
-j--
t . -t
. 1-1
f---
J
(121 1/0
rr=---l:I-- J '4'-"0>
Fuse number - First Fuse number + Increment
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2·187
TlBPAL 16RB·20M, TIBPAL 16RB·15C
HIGH·PERFORMANCE IMPACpM PAL@ CIRCUITS
CLK (11-",
INCREMENT
FIRST
~~~BERS
o
4
0
8
12 ,
16
20
24
28
31
32
64
96128
160
192
)--
~
)--
>-
256
288
320
352
38'
"6
T:"i"ro
10
I
~
( 19 1 0
~~
- b-
r:--:;"
1-1
10
r.:J..
v
(181
>-;:l
(17
a
448
~512
544
576608
640
672
70.
(4) 736
T=1
10
~1
768
800
832
86'
896
928
960
~ 992
p-
1024
1066
1088
1120
1152
1164
1216
(61'248
1280
1312
1344-
1376
1408
1440
1472
(7)'50'
--vb-- 1536
1568
1600 - -
1632~
16641696-
r-+
.,.
1-
r--
-j-
1728
t
(81 1760
t+
1192
1824
1~
4
1888-
--
1920
1952
I
(91~b-t
if-+ ;H+ t~: +
r
1---
---vb--f- T t - -t t T I-tt ti-t1-t--
Fuse number - First Fuse number
2-188
b--+-+-----t--
+
Increment
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
10
-VO-)O
TIBPAL 16LB-20M, TlBPAL 16R4-20M, TlBPAL 16R6-20M, TlBPAL 16RB-20M
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°C
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low~level
fclock
Clock frequency
tw
Pulse duration, clock (see Note 21
tsu
Setup time, input or feedback before CLKt
th
Hold time, input or feedback after CLKt
TA
Operating free-air temperature
MIN
NOM
MAX
UNIT
4.5
5
5.5
5.5
0.8
-2
12
41.6
V
2
output current
I
I
High
Low
0
10
11
20
0
-55
V
V
mA
mA
MHz
ns
ns
ns
125
·C
NOTE: 2. The total clock period of elK high and elK low must not exceed clock frequency, fclock. Minimum pulse durations specified
are only for elK high or eLK low, but not for both simultaneously.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-189
TIBPAL 16L8·20M, TlBPAL 16R4·20M, TlBPAL 16R6·20M, TlBPAL 16R8·20M
HIGH·PERFORMANCE IMPACT'M PAL® CIRCUITS
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
Vee
VOH
Vee
VOL
Vee
= 4.5
= 4.5
= 4.5
Vee
Vee
Outputs
10ZH
1/0 ports
Outputs
10Zl
1/0 ports
II
Vee
Vee
IIH
=
V,
II
V,
10H
V,
10l
= -2 rnA
= 12 rnA
=
5.5 V,
Vo
=
2.7 V
=
5.5 V,
Vo
=
0.4 V
=
=
5.5 V,
5.5 V,
=
VI
=
VI
MIN
Typt
2.4
3.2
-18 rnA
0.25
100
-20
-250
5.5 V
2.7 V
Vee
=
lost
Vee
lee
Vee
=
=
VI
=
5.5 V,
Vo
5.5 V,
VI
= 0.5
= 0,
5.5 V,
Pin 1, 11
0.2
All others
0.1
Pin 1, 11
50
1/0 p'orts
100
20
1/0 ports
0.4 V
-0.25
-0.2
All othe!,
-30
V
140
Outputs open
UNIT
V
V
0.4
20
All others
III
MAX
-1.5
V
~A
~
rnA
~A
rnA
-250
rnA
190
mA
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
FROM
TO
TEST CONDITIONS
f max
MIN
TYpt
MAX
10
20
ns
8
15
15
ns
ns
tad
1,1/0
0,1/0
tpd
elKt
Q
Rl
ten
OEi
Q
tdis
ten
OEt
1,110
R2
See Figure 1
15
ns
0,1/0
10
20
ns
tdis
1,1/0
0,1/0
10
20
ns
Q
= 3900,
= 7500.
8
7
tAli typical values are at Vee = 5 V, TA = 25°e.
tNot more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Set
to avoid test equipment degradation.
2-190
UNIT
MHz
41.6
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Va at 0.5 V
TIBPAL 16L8-15C, TlBPAL 16R4-15C, TIBPAL 16R6-15C, TlBPAL 16R8-15C
HIGH-PERFORMANCE IMPACT'M PAl® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output Isee Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN
4.75
2
PARAMETER
vee
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
IOl
Low-level output current
fclock
Clock frequency
tw
Pulse duration, clock (see Note 2)
tsu
Setup time, input or feedback before C;:LKf
I
High
I low
th
Hold time, input or feedback after elK!
TA
Operating free-air temperature
0
8
NOM
5
MAX
5.25
5.5
0.8
-3.2
24
50
V
V
V
mA
mA
MHz
ns
g
15
0
0
UNIT
ns
ns
75
°e
NOTE 2: The total clock period of elK high and elK low must not exceed clock frequency, fclock. Minimum pulse durations specified
are only for elK high or elK low, but not for both simultaneously.
~
TEXAS
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
2-191
TlBPAL 16LO-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TlBPAL 16RO-15C
HIGH-PERFORMANCE IMPACTTM PAL® CIRCUITS
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
V,K
Vee = 4.75 V,
1,=-18rnA
VOH
Vee = 4.75 V,
10H = -3.2 rnA
VOL
10ZH
10Zl
Outputs
I/O ports
Outputs
I/O ports
Vee = 4.75 V,
10l = 24 rnA
Vee = 5.25 V,
Vo = 2.7 V
Vee = 5.25 V,
Vo = 0.4 V
I,
Vee = 5.25 V,
V, = 5.5 V
IIH
Vee = 5.25 V,
V, = 2.7 V
',l
10*
Vee = 5.25 V,
Vee = 5.25 V,
V, = 0.4 V
lee
Vee = 5.25 V,
V, = 0,
MIN
Typt
2.4
3.3
0.35
MAX
-1.5
0.5
20
100
-20
-250
Pin 1, 11
0.1
All others
Pin 1, 11
0.1
All others
20
-0.2
20
-30
Vo = 2.25 V
140
Outputs open
UNIT
V
V
V
pA
pA
rnA
pA
-125
mA
rnA
180
rnA
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
FROM
TO
TEST CONDITIONS
f max
MIN
Typt
MAX
10
15
ted
I, I/O
0,1/0
tDd
elKi
Q
R1
=
=
500!l,
S
8
7
10
10
12
12
ten
OEI
Q
R2
tdis
OEi
Q
See Figure 1
ten
1,1/0
0,1/0
tdis
1,1/0
0,1/0
500!l,
UNIT
MHz
50
ns
ns
ns
10
ns
15
ns
15
ns
t All typical values are at Vee = 5 V, TA = 25 ce.
tThe output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, lOS.
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers,
Complete programming specifications, algorithms. and the latest information on hardware. software. and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available. upon request. from the nearest TI field sales office. local
authorized TI distributor. or by calling Texas Instruments at (214) 995-5666.
2-192
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16L8·20M. TIBPAL 16R4·20M. TIBPAL 16R6·20M. TlBPAL 16R8·20M
TlBPAL 16L8·15C. TIBPAL 16R4·15C. TIBPAL 16R6·15C. TlBPAL 16R8·15C
HIGH·PERFORMANCE IMPACpM PAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
5V
51
b
R1
FROM OUTPUT ~'--0
3
description
These programmable array logic devices feature
high speed and a choice of either standard or
half-power devices. They combine Advanced
Low-Power Schottky t technology with proven
titanium-tungsten fuses. These devices will
provide reliable, high-performance substitutes
for conventional TTL logic. Their easy
programmability allows for quick design of
"custom" functions and typically result in a
more compact circuit board. In addition, chip
carriers are available for further reduction in
board space.
2
1 20 19
4
18
5
17
6
16
8
14
15
I/O
I/O
I/O
I/O
I/O
9 1011 12 13
-0
z
-og
(!)
The PAL 16' M series is characterized for
operation over the full military temperature range
of - 55°C to 125°C. The PAL16' C series is
characterized for operation from OOC to 70°C.
tlntegrated Schottky· Barrier diode-clamped transistor is patented by Texas Instruments, U.S. Patent Number 3,463,975.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Incorporated
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
speCifications per the terms of Texas Instruments
==~~~8i~:I:ri ~:~::ti:r :''i'::~:::;:t:~~S
not
Copyright © 1989, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-195
TIBPAL 16R4·30M, TIBPAL 16R6·30M, TlBPAL 16R8·30M
TIBPAL 16R4·25C, TIBPAL 16R6·25C, TlBPAL 16R8·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTMPAl® CIRCUITS
TIBPAl16R4'
M SUFFIX ... J OR W PACKAGE
C SUFFIX .•• J OR N PACKAGE
TIBPAl16R4'
M SUFFIX •.. FK PACKAGE
C SUFFIX .•. FN PACKAGE
(TOP VIEW)
(TOP VIEW)
elK
::5 ~O
Vee
_ _ U>;:,
1/0
1/0
3
2
1 20 19
Q
Q
18
17
Q
16
Q
15
1/0
1/0
14
9 1011 1213
GND '-I.._....;.Jt-'0E
TIBPAl16R6'
M SUFFIX ... J OR W PACKAGE
C SUFFIX ..• J OR N PACKAGE
TIBPAl16R6'
M SUFFIX ... FK PACKAGE
C SUFFIX ..• FN PACKAGE
(TOP VIEW)
(TOP VIEW)
elK
~
Vee
U
..J UO
_ _ U>;:,
1/0
3
Q
2
1 20 19
Q
18
Q
17
16
Q
Q
15
Q
14
1/0
GND -"'_--.Jr- OE
9 1011 1213
TIBPAL 16RS'
M SUFFIX ... J OR W PACKAGE
C SUFFIX ... J OR N PACKAGE
TlBPAl16RS'
M SUFFIX ..• FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
(TOP VIEW)
elK
Vee
Q
Q
3
1 20 19
4
18
Q
5
17
Q
Q
6
7
15
Q
8
Q
16
14
9 1011 12 13
GND ""1..._....;.Jr-0E
2-196
2
Q
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16LB·30M. TIBPAL 16R4·30M
TIBPAL 16LB·25C. TIBPAL 16R4·25C
LOW·POWER HIGH·PERFORMANCE IMPACpMPAL® CIRCUITS
functional block diagrams (positive logic)
'PAl16lB
EN ~~1
&
p-----O
32 X 64
p.----O
P-..............-I/O
[>
10
16
P-4H--+.....-1/0
D--.t..........-I/O
6
D-.-+......--I/O
6
'PAL 16R4
J EN2
De
'1 C1
ClK
~
&
32
c;-
8
,
4
r+'---
x 64
;>1
-i-l-
1=1
10
~
Q
~
-+-
r+-
'V
~
'V
Q
~
-+-
--I-
Q
2"7
Q
~
EN
;>1
"7
---;-
;+-
""
""
---;-
-i-
'7'"-
r+4
""
I/O
I/O
I/O
I/O
~
4
,
rv
denotes fused inputs
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-197
TlBPAL 16R6·30M, TlBPAL 16R8·30M
TIBPAL 16R6·25C, TIBPAL 16R8·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTMPAl® CIRCUITS
functional block diagrams (positive logic)
'PAL 16R6
De
l.EN2
t, Cl
ClK
~8
~1
10
32X64r+-
-+-
~
~
~
~
p..;L 'V
~
~
~
~
~
Q
Q
r-..:L 'V p...
~
Q
1=1 2
Q
~
~
Q
~
~
r--
Q
~
EN
;;>1
~
'V
r--
~
liD
liD
2
...
6
"""-
'PAL 16RS
De------------------------~~--_,
ClK-----------------------------P
&
8
r;;;>;;l-,.....I=~~--
Q
32 X 64
r---r-I:r--=~Q
r-----t-----~~-Q
r-----t------"b-~-
Q
r-----t------"b-~-Q
r-----t-----"b-~-Q
r-----t------~~-Q
r-----t-----~~-Q
8
rv denotes
2-198
fused inputs
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 65530:i • DALLAS, TeXAS 75266
TIBPAL 16LB·30M, TIBPAL 16LB·25C
LOW·POWER HIGH·PERFORMANCE IMPACpMPAl® CIRCUITS
1(1 )
FI RST
INCREMENT
FU SE
N UMBERS 0
0-
32 -64
96128
4
B
.....
12
16
20
24
2B
31
1-.
>-- h
--
f.-/
160
1
(19)
V
o
>->--
192
224
~
256
>--'k
1
h
1
h
1
288
320--
352
384416
(IB)
V
I/O
448
(3) 480
512544
576·
608
640
672
704
736
(4)
(17)
V
I/O
>--'
768
800
832
864
896
928
f-
I--"
(16)
V
I/O
-
9.0
992
(5) X
1024
1056
1088
h
1120
1152
1
(IS)
V
I/O
1184
1216
(6)'248
1280
1312
).-
1344
1376
1408
).-
1440
'472
(7)'50'
1536
P
1
-
1568
1600
1632-
,."
1
(14)
(13)
~J
1696
1728
1760
(B)X
1192
1824
1856
h
1888
1920
1952
1
(12)
V
I/O
I/O
o
>----'
1984
(9)201.
(11 )
~
Fuse number - First Fuse number
+ Increment
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-199
TlBPAL 16R4·30M. TIBPAL 16R4·25C
LOW·POWER HIGH·PERFORMANCE IMPACrrMPAl® CIRCUITS
CLK 11 I
INCREMENT
FIRST
FUSE
N UMBERS 0
4
o-
8
12
16
24
20
28
j---
32
64
96128'60
'92
224
121~
31
. .+-
-]
)--
I--
t-
'-I
"
256
288
320
352
384
4'6
448
480
J
~
1
'-
-
5'2
544
576
IT
-
608-
)..
~.
640
672
704
736
jQ
}--,
)..
rC:) "
--
1344
1376
1408
1440
1472
1504
~
f-.
)--
~
;=::KJ-.
+.
1~~-
f-
t
1568
-+
----t-
It
I--
t
.. -
~I
Q
V
h.
10
r-.:.J
(141
V
Q
~
J
- 1
_.
1696
1728
1760
1131
1/0
::=:;K}----J
1792
1824
1656
1888
1920
1952
1984
2016
+
..
-t-
.~
-
. .i-
~ ,Lj
+-.~-~'
~
~~-
-j-
J!I.4>r=. +-t+-tt+t t iH-f+++u
++
..~
T
I
I
Fuse number = First Fuse number + Increment
2-200
~
10
I=T
D-
I (71 X
~I Q
~
I-;.I
1280
1312
I
)--->
}--,
+--
I~
10
N
1088
1120
1152
1184
1216·
1248
181
t:£1.~
~~
f--.
1024
1056
1600 - -1632
~I Q
'T1
t-)..
1_151
1664-'
10
-I
768
800832
864
896
928
960
992
I
1181 I 10
~
~
141
I
IA
'tr
1191 I /0
...
i---'
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t--'=---~
I ....---
1121
1/0
L-
b-
992
1024
1066
1088
1120
1152
1184
1216
>-
t> ~
~1
161'248
1280
1312
'344
~I
v
0
1376
1408
'440
1472
111'504
1536~
1568
'600'632- .
16641696
1128
";:] (131
·V
IB)'760
1792
1824
+
'~6
1888
1920
,
~::!
t:-
191~~1 iW i ~
~lt+-tHt::4t-~ ~~ I
I
-
I
+~
rH+--
Fuse number - First Fuse number + Increment
2-202
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0
TIBPAL 16LB·30M, TIBPAL 16R4·30M, TlBPAL 16R6·30M, TIBPAL 16R8·30M
LOW·POWER HIGH·PERFORMANCE IMPACT'MPAl® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . .
... .. ...
. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- 55 De to 125 De
Storage temperature range ...
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
- 65 DC to 150 DC
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
Vee
Supply vollage
VIH
High~level
VIL
Low-level input voltage
input voltage
MIN
NOM
MAX
4.5
5
5.5
V
V
2
UNIT
V
IOH
High-level output current
5.5
0.8
-2
IOL
Low-level output current
12
mA
fciock
Clock frequency
25
MHz
Iw
Pulse duration, clock (see Note 2)
Isu
Ih
Setup time, input or feedback before elK i
Hold time, input or feedback after CLKi
TA
Operating free-air temperature
0
I High
I Low
15
ns
20
ns
25
0
-55
mA
125
ns
De
NOTE 2: The total clock period of elK high and elK low must not exceed clock frequency, fclock. Minimum pulse durations specified
are only for elK high or elK low, but not for both simultaneously.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-203
TIBPAL 16L8-30M, TIBPAL 16R4-30M, TIBPAL 16R6-30M, TIBPAL 16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACTTMPAl® CIRCUITS
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
Vee
~
VOH
Vee
~
VOL
Vee
Outputs
10ZH
10ZL
I/O ports
Outputs
I/O ports
II
~
4.5 V,
4.5 V,
4.5 V,
-18 rnA
IOH ~ -2 rnA
10L ~ 12 rnA
Vee
~
5.5 V,
Vo
~
2.7 V
Vee
~
5.5 V,
Vo
~
0.4 V
Vee
~
5.5 V,
VI
MIN
Typt
~
II
~
2.4
3.2
0.25
Pin I, 11
5.5 V
All other
Pin I, 11
Vee
IIH
~
5.5 V,
~
VI
2.7 V
I/O ports
All other
IlL
Vee
~
5.5 V,
VI
lost
Vee
~
Vo
Vee
~
5.5 V,
5.5 V,
ICC
VI
~
~
~
I/O ports
0.4 V
All other
-30
0.5 V
0,
75
Outputs open
MAX
UNIT
-1.5
V
0.4
20
100
-20
-250
0.2
0.1
50
100
20
-0.25
-0.2
-250
V
V
105
~A
~A
rnA
~
rnA
rnA
rnA
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
FROM
TO
TEST CONDITIONS
f max
Typt
MAX
15
10
15
10
14
13
30
20
25
25
30
30
1,1/0
0,1/0
tDd
eLKt
OE.
Q
Q
tdis
ten
OEt
Q
1,1/0
0,1/0
tdis
1,1/0
0, I/O
Rl ~ 390 Il,
R2 ~ 750 Il,
See Figure 1
ae.
UNIT
MHz
25
tDd
ten
MIN
ns
ns
ns
ns
ns
ns
t All typical values are at Vee ~ 5 V, T A ~ 25
tNat more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Set Va at 0.5 V
to avoid test equipment degradation.
2-204
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAl16lB·25C. TlBPAl16R4·25C. TIBPAl16R6·25C. TIBPAl16RB·25C
lOW·POWER HIGH·PERFORMANCE IMPACpMPAl® CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '
7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 75 °e
Storage temperature range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 °e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
fclock
Clock frequency
tw
Pulse duration, clock (see Note 2)
r High
I Low
tsu
Setup time, input or feedback before CLKi
th
Hold time, input or feedback after CLKt
TA
Operating free-air temperature
MIN
NOM
MAX
UNIT
4.75
2
5
5.25
5.5
0.8
-3.2
24
30
V
0
10
15
20
0
0
V
V
rnA
rnA
MHz
ns
ns
ns
70
°e
NOTE 2: The total clock period of elK high and elK low must not exceed clock frequency, fclock. Minimum pulse durations specified
are only for eLK high or elK low, but not for both simultaneously.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2·205
TlBPAL 16LB·25C, TlBPAL 16R4·25C, TlBPAL 16R6·25C, TlBPAL 16RB·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
electrical characteristics over recommended operating free-air temperature range.
TEST CONDITIONS
PARAMETER
Vee
= 4.75 V,
= 4.75 V,
= 4.75 V,
10l
= 24 rnA
Vee
=
5.25 V,
Vo
= 2.7
Vee
=
5.25 V,
Vo
= 0.4 V
VIK
Vee
VOH
Vee
VOL
Outputs
10ZH
10Zl
1/0 ports
Outputs
1/0 ports
=
Vee
II
5.25 V,
II = -18 rnA
10H - -3.2 rnA
VI
=
IIH
Vee
=
5.25 V,
VI
Vee
=
=
=
5.25 V,
= 0.4 V
Vo = 2.25
VI = 0,
5.25 V,
Vee
5.25 V,
Outputs open
lee
2.4
3.3
MAX
-1.5
100
-20
-250
V
Pin 1, 11
0.1
All others
0.1
Pin 1, 11
·AII others
20
VI
-30
V
75
UNIT
V
V
0.5
20
V
III
lot
Vee
Typt
0.35
5.5 V
= 2.7
MIN
V
~A
~A
rnA
~A
20
-0.2
rnA
-125
rnA
100
rnA
switching characteristics over rec·ommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
FROM
TO
Typt
MAX
15
25
ns
R1 = 5000,
10
15
ns
R2 = 5000,
15
20
ns
See Figure 1
10
20
ns
TEST CONDITIONS
f max
MIN
UNIT
MHz
30
tpd
1,1/0
0,1/0
tad
elKt
ten
tdis
OEJoet
a
a
a
ten
1,1/0
0,1/0
14
25
ns
tdis
1,1/0
0,1/0
13
25
ns
tAli typical values are atVCC = 5V,TA = 25°C.
:t:The output conditions have been chos~n to produce a current that closely approximates one half of the true short-circuit output current, lOS.
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 995-5666.
2-206
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16L8·30M, TIBPAL 16R4·30M, TIBPAL 16R6·30M, TIBPAL 16R8·30M
TIBPAL 16L8·25C, TIBPAL 16R4·25C, TIBPAL 16R6·25C, TIBPAL 16R8·25C
LOW·POWER HIGH·PERFORMANCE IMPACrrMPAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
SV
S1
b
R1
FROM OUTPUT
UNDER TEST
-<........~...._
TEST
POINT
R2
CL
(See Note A)
LOAD CIRCUIT FOR
OUTPUTS
THREE~STATE
./.
TIMING
INPUT
[3.S VI 13 VI
)'i 1.5
HIGH~LEVEL
PULSE
V
- - - - - ' :- - - - - - - - 10.3 VI 101
. . t su .....- th~
'
'[3.SVI13VI
DATA
',5V
-'-~~V-
~
INPUT
[0.3 VI 101
I
J1.5
V
,
LOW LEVEL
PULSE
:
IN~PHASE
1
/'
OUTPUT
I
.
~tpd
:
1.5 V I
I
tpd ~
OUT~OF~PHASE
OUTPUT
[3.S Vl13 VI
I ' - - - - - 10.3 VI 101
tpd~
\1 1.5 V
, [ 0 . 3 VI 101
-----'
:
~
:
[3.5VI13VI
1.5 V
-
- -
-
[0.3 VI 101
VOLTAGE WAVEFORMS
PULSE DURATIONS
--- 15 V
\
I
~ tw
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
----[3.5VI[3VI
~
1.5 V
'{,-~~
C'
I
I4-----+t- tpd
VOH
T' ., \
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1 5 V
I
ten-+l
~
I I
I I
WAVEFORM 1
S1 CLOSED
ISee Note BI
-
- -
[0.3 VI 101
I
-1I
!t-tdis
I
I
~3.3V
I __
I
ten-+!
(See Note B)
- - -
I
:
LVOL+0~5V
~
- - VOL
WAVEFORM 2
S1 OPEN
[3.5VI13VI
1.5 V
I
I
(low-level
enabling)
VOL
~I
1.5 V VOH
(See Note Dj
~
OUTPUT
CONTROL
~
I
_:
tdis .....
---X T
""...-
I _
__
_
VOL
i.v
OH
~
L VOH-0~5
~O
V
V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE~STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and tenl 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For M suffix, use voltage levels indicated in parentheses (),
PRR ::::; 10 MHz, tr = tf ::::; 2 ns, duty cycle = 50%. For C suffix, use the voltage levels indicated in brackets [ L
PRR ::::; 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch Sl is closed.
E. Equivalent loads may be used for testing.
FIGURE 1
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-207
2-208
TIBPAL20L8·7M. TIBPAL20R4·7M. TIBPAL20R6·7M. TIBPAL20R8·7M
TIBPAL20L8·5C. TIBPAL20R4·5C. TIBPAL20R6·5C. TlBPAL20R8·5C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
D3353, OCTOBER 19B9
•
TlBPAL20L8'
M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE
High·Performance Operation:
f max (no feedback)
TlBPAL20R'·5C Series ... 125 MHz
TIBPAL20R'·7M Series ... 100 MHz
f max (internal feedback)
TIBPAL20R'·5C Series ... 125 MHz
TIBPAL20R'·7M Series ... 100 MHz
f max (external feedback)
TIBPAL20R' ·5C Series ... 115 MHz
TIBPAL20R'·7M Series ... 74 MHz
Propagation Delay
TIBPAL20R'·5C Series ... 5 ns Max
TIBPAL20R'·7M Series ... 7 ns Max
(TOP VIEW)
Vee
I
o
1/0
1/0
1/0
1/0
1/0
1/0
o
•
Functionally Equivalent, but Faster than,
Existing 20·Pin PALs
•
Preload Capability on Output Registers
Simplifies Testing
•
Power·Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High
GND '-\.."':"'_.:J-'
•
•
TlBPAL20L8'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
4
DEVICE
I INPUTS
3·STATE
o OUTPUTS
REGISTERED
a OUTPUTS
I/O
PORTS
14
12
12
12
2
0
0
0
0
4 13-st8te buffers)
6 13-state buffers)
8 13-state buffers)
6
4
2
0
3
2
:>w
1 282726
a:
5
25
6
24
I
7
23
GND
8
22
(.)
9
21
10
20
:::l
C
Security Fuse Prevents Duplication
'PAL20L8
'PAL20R4
'PAL20R6
'PAL20R8
~
w
UU
_»_0
uu
11
c.
...
oa:
19
12131415161718
c.
-00--0
ZZ
c.?c.?
description
These programmable array logic devices feature
Pin assignments in operating mode
high speed and functional equivalency when
compared with currently available devices.
These IMPACT·X'" circuits combine the latest
Advanced Low·Power Schottky t technology
with proven titanium-tungsten fuses to provide
reliable, high·performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board.
The TIBPAL20'M series is characterized for operation over the full military temperature range of - 55°C
to 125°C. The TIBPAL20'C series is characterized from OOC to 75°C.
IMPACT-X is a trademark of Texas Instruments Incorporated
PAL is a registered trademark of Monolithic Memories Inc.
t'ntegrated Schottky-Barrier diode-clamped transistor is patented
by Texas Instruments, U.S. Patent Number 3,463,975.
I..
PRODUCT PREVIEW ••••II.nts o:ontain iat.r..lli••
pnd.... in tho farmlllvo or design ph_ at
d•••I.p ....t. Char••t.rlstl. .ata
.thor
splCifil:ltiDnl Ira ••i~goalL Tuu IRltru ..lntI
=.:.:~IIt.2;:'. ngo .r di...llln.. -
=
OIl
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2·209
TIBPAL20R4·7M, TIBPAL20R6·7M, TlBPAL20R8·7M
TIBPAL20R4·5C, TIBPAL20R6·5C, TIBPAL20R8·5C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
TIBPAL20R4'
M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE
(TOP VIEW)
elK
TIBPAL20R4'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
"
Vee
I
1/0
1/0
Q
Q
Q
U
U
U U
0
__ U»_'"
..J
4 3 2
5
Q
1 28 2726
25
110
6
7
24
8
22
9
21
GND
Q
19
1/0
23
1/0
1/0
Q
Q
12131415161718
TlBPAL20R6'
M SUFFIX ... JT PACKAGE
C SUFFIX ..• JT OR NT PACKAGE
(TOP VIEW)
"o::u
elK
c
TIBPAL20R6'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
Vee
I
110
Q
Q
Q
Q
c:
(")
-I
::u
"m
S
m
4 3
I
5
I
6
2
1 282726
1/0
I
~
25
24
Q
23
22
21
Q
GND
Q
20
19
Q
12131415161718
GND ......_--'-.... DE
TIBPAL20R8'
M SUFFIX .•. JT PACKAGE
C SUFFIX ..• JT OR NT PACKAGE
(TOP VIEW)
elK
TlBPAL20R8'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
tl tl
__ :J
u»_O
Vee
I
Q
4 3
2 1 282726
Q
25
24
Q
23
Q
22
21
Q
Q
I
19
I
GND
12131415161718
'-'-_......J... OE
Pin assignments in operating mode
2-210
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75285
Q
Q
TIBPAL20L8·7M, TIBPAL20R4·7M
TIBPAL20L8·5C, TIBPAL20R4·5C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
functional block diagrams (positive logic)
TIBPAl20lB'
EN ~1
&
40 X 64
'\l~---O
1:>----0
14
20
K>-<.-!-........... I/O
...- I / O
~H-
K>-<,-!-",>--I/O
~
w
6
:>w
TIBPAl20R4'
a:
'0E
Q.
EN
ClK
t-
C1
--s;40X64
SiiX'i>
~2
4
r+
0.....-..
-+-
*
8
r-+-
CJ
~l
1-0 '\l
r+r+-
'V
r++
>--
'V
0
r---.
1D
a
~
r-----.
a
::>
c
a:
Q.
0
a
~
EN ~1
1/0
'\l
"7'""
-i-
--"
-i~
---r;-
"'
"'
"'
1/0
1/0
1/0
,
4
rv
denotes fused inputs
TEXAS ~
INSTRUMENTSPOST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-211
TIBPAL20R6·7M, TlBPAL20R8·7M
TIBPAL20R6·5C, TIBPAL20R8·5C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20R6'
DE------------------------W
"
(19)
N
v
liD
1200
(6) ....
v
1240
r---J
1440
1480
1520
1560
(7)
v
8)
\...
(9)
t,)
~
1320
1360
1400
(18)
liD
>j
::J
C
0
a:
Q.
~
1600
1640
1680
1720
1760
1800
1840
1880
a:
Q.
l-
......
1280
~
W
A
(17)
liD
~
1920
1960
2000
2040
2080
2120
2160
2200
1
(16)
1
(15)
1/0
v
A
2240
2280
2320
2360
2400
2440
I ( 10)"
v
2480
2520
.....
o
(14)
~
......
11) ....
(13)
-.r--
-:
Number
Fuse
Fllst Fuse Number -+- Increment
Pin numbers shown are for JT and NT packages.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-213
TIBPAL20R4·7M
TIBPAL20R4·5C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
logic diagram (positive logic)
(1)
CLK
--'-t>
INCREMENT
10
(2)
1\
4
B
16
12
24,
20
2B
32
\
36
(23)
......
I-
FIR ST
FU SE
IIIU MBERS 4g
(3) ...
-
(4)"
80
120
160
200
240
280
.
......
320
360
400
440
480
520
560
600
H
....,
,
-;
960
1000
1040
1120
1160
1200
1240
I-
1600
'-=>....
"
)-
1760
1800
1840
-
1880
....
1920
"
2000
2040
2080
2120
2160
2240
2280
2320
2360
2400
2440
2520
l-
I
11)"
I
I
v
~19
B
10
V
o
fl]
~B )0
n
1.1.
Cl
~
10
(17 )0
~
1
(16
1
(15
.!,14)
I
Fu se Number
First Fuse Number + Increment
Pin numbers shown ar e f 0 r J T and NT packages.
2-214
o
~
2480
10)
1/0
~
2200
""""1.-
I
Cl
1960
(9)
....
"
~
1640
1680
1720
(B)
v
Cl
....
1400
(7) .....
(21)
0
Cl
1280
1320
1360
1440
1480
1520
1560
l
1/0
;r- ~~.,
r-;r-
1080
(~
(22)
~
640
680
720
760
800
840
880
920
5)
l
'"
I
L-
INCREMENT
"0
(~
..
4
8
12
16
20
24
28
32
...
36
"
(231
......
FI RST
FU SE
0
N UMBERS 40
80
120
160
200
240
280
(31
(~
...
(51
...
(61~
...
).-.
H
r
640
680
720
760
800
840
880
920
~r
-rv-'"
DjrJ
'"
960
1000
1040
1080
1120
, 160
1200
t>-
1280
1320
r-L.->-
1440
1480
1520
1560
"
1600
1640
3:
w
5>
w
(1
a:
I.-
~
Q.
t-
O
~
:::>
V
Q
Cl
oa:
f-----J
Q.
~
B
J-
I.-
Cl
1880
'"
1920
1960
2000
2040
)--
2080
2120
2160
~
10
b
(1 6)
I.-
a
Cl
2200
A
'"
2240
2280
(10)~
b
~
To
1840
...
'R
2O )0
V
~Cl
1240
1800
(~
~
t:G
10
Cl
1680
....
o
10
:::..t
1720
1760
(~
1,'0
Cl
1400
...
kl1
(221
.....
320
360
400
440
480
520
560
600
1360
(~
F-
2320
2360
2400
2440
2480
2520
~1
(151
I/O
.J----'
~14)
(1.!!,r-
....
'I
I
~ OE
Fus e Number -;= First Fuse Number + Increment
Pin numbers shown are for JT and NT packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-215
TlBPAL20R8·7M
TlBPAL20R8·5C
HIGH IMPACT·XTM PAL® CIRCUITS
logic diagram (positive logic)
(1 )
C LK
~
INCREMENT
"0
4
8
16
12
"
20
24
28
32
(2)
-;..
FIR ST
FU SE
a
NU MBERS 40
80
120
160
200
240
280
(~
,
(23)
.....
)-~
320
360
400
440
480
520
560
600
r,J-
640
680
720
760
800
840
880
920
J-
1040
10ao
J-
1120
1160
1200
1240
v
()
~~~g
r-
1480
1520
v
..,..
1560
"
1600
1640
1680
1720
1760
r-
1800
(8) ....
~~;g
.....
"
f-
2160
2200
~
10
Q
1:1 (20
-vo-
Q
C1
B
B
1:1 (19
10
v
Q
1(18
IO
Q
v
C1
fl]
1.
fl]
1(17
IO
Q
v
~
lO
(16
v
"
2320
2360
2400
2440
2480
2520
'1
~~ -vo-
Q
(15
Q
C1
.....
"
(14)
1)
"1- - I
-v
4-
3)_
Fus e Number = First Fuse Number + Increment
Pin numbers shown are for JT and NT packages.
2·216
v
1- - - - - '
2280
-;..
1:1(21
C1
C1
2240
10)
~
IO
C1
1920
1960
2000
2040
2080
2120
9) ....
~
C1
1360
1400
1440
(7) ....
Q
~ r-----'
960
1000
6)
~~
C1
(~
4) ...
36
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OE
TIBPAL20LB·7M, TlBPAL20R4·7M, TIBPAL20R6·7M, TlBPAL20RB·7M
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
VCC
Supply voltage
VIH
VIL
High-level input voltage
IOH
High-level output current
MIN
NOM
MAX
4.5
5
5.5
V
5.5
V
O.B
-2
V
mA
2
Low-level input voltage
IOL
low-level output current
fclock
Clock frequency
tw
Pulse duration, clock
tsu
th
TA
Setup time, input or feedback before CLKt
Hold time, input or feedback after CLKt
a
12
mA
100
5
MHz
ns
5
ns
7
ns
a
I High
I Low
-55
Operating free-air temperature
fclock, t w , tsu, and th do not apply for TIBPAL20LB'.
UNIT
25
125
ns
DC
~
w
:>w
a:
0..
tO
;:)
C
oa:
0..
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • OAU.AS, TEXAS 75265
2-217
TIBPAL20L8·7M, TIBPAL20R4·7M, TIBPAL20R6·7M, TlBPAL20R8·7M
HIGH·PERFORMANCE IMPACT·X™ PAl® CIRCUITS
electrical characteristics over recommended free-air operating temperature range
PARAMETER
TEST CONDITIONS
VCC '" 4.5 V,
II'" -18 rnA
VOH
VCC '" 4.5 V,
10H'" -2 rnA
Val
Vcc '" 4.5 V,
10l'" 12 rnA
10ZH
Vcc '" 5.5 V,
Va '" 2.7 V
Vcc'" 5.5 V,
Va", 0.4 V
Vcc '" 5.5 V,
VI '" 5.5 V
Vcc '" 5.5 V,
VI '" 2.7 V
10Zl
I 0, Q outputs
I 1/0 ports
II
1/0 ports
IIH
All others
1/0 ports
III
Vcc '" 5.5 V,
All others
10S~
o:::IJI
C
c:
(")
~
TYpt
-0.8
2.4
0.25
Va - 0.5 V
Vcc'" 5.5 V,
V
100
-20
~A
~A
-0.25
rnA
1
100
rnA
25
-70
V
0.5
-0.1
-30
UNIT
V
3.2
VI'" 0.4 V
Vcc'" 5.5 V,
MAX
-1.5
-0.2
-250
~
rnA
rnA
Outputs open,
VI'" 0,
OE at VIH
Ci
I", 1 MHz,
VI'" 2 V
pF
Co
I", 1 MHz,
Va'" 2 V
pF
Cclk
I", 1 MHz,
VClK '" 2 V
pF
ICC
""0
MIN
VIK
210
t All typical values are at VCC '" 5 V, T A '" 25 ·C.
:t: Not more than one output should be shorted at a time, and duration of the short circuit should not exceed 1 second. Set
to avoid test equipment ground degradation.
Vo
rnA
at 0.5 V
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted I
PARAMETER
""0
::rJ
Irnax§
S
FROM
without leedback
TEST CONDITIONS
TO
with internal leedback
100
(counter configuration)
tpd
1,1/0
0,1/0
tpd
ClK
Q
ten
OE!
Q
Rl '" 2000,
R2 '" 2000,
See Figure 1
UNIT
MHz
74
ns
ns
ns
tdis
OEt
Q
ns
ten
1,1/0
0,1/0
ns
tdis
1,1/0
0,1/0
ns
§See 1m ax SPECIFICATIONS. 1m ax does' not apply lor TlBPAl20l8'.
2-218
MAX
100
with external leedback
~
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20LB-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TlBPAL20RB-5C
HIGH-PERFORMANCE IMPACT-X™ PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) ................................................... 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range ...................................... OOC to 75°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
V
V
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
10H
High-level output current
-3.2
IOL
Low-level output current
24
mA
fclock
Clock frequency
125
MHz
tw
Pulse duration, clock
5.5
2
0.8
0
I High
I Low
mA
4
ns
4
ns
tsu
Setup time. input or feedback before ClKt
4
ns
th
Hold time. input or feedback after CLKt
0
TA
Operating free-air temperature
0
ns
DC
fclock. two tsw and th do not apply for TIBPAL20LS·.
25
75
w
:>==w
~
Q.
I-
o
~
c
o
~
Q.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-219
TIBPAL20L8·5C, TlBPAL20R4·5C, TlBPAL20R6·5C, TlBPAL20R8·5C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
electrical characteristics over recommended free·air operating temperature range
PARAMETER
o
c
c:
n-I
Typt
MAX
UNIT
-0.8
-1.5
V
0.3
0.5
II = -18 rnA
VOH
Vce - 4.75 V.
IOH -
VOL
Vcc = 4.75 V.
10l = 24 rnA
Vcc = 5.25 V.
Vo = 2.7 V
Vcc = 5.25 V.
Vo = 0.4 V
II
Vcc = 5.25 V.
IIH*
vcc = 5.25 V.
III *
10S§
Vcc = 5.25 V.
VI = 0.4 V
Vcc - 5.25 V.
Vo = 0.5 V
ICC
Vcc = 5.25 V.
Outputs open.
VI = O.
OE at VIH
Ci
1= 1 MHz.
VI = 2 V
pF
Co
1= 1 MHz.
Vo = 2 V
pF
Cclk
1= 1 MHz.
VClK = 2 V
pF
10Zl
::a
MIN
Vcc = 4.75 V.
10ZH
'"0
TEST CONDITIONS
VIK
O. Q outputs
110 ports
0, Q outputs
1/0 ports
-3.2 iliA
2.4
V
20
100
V
~A
-2Q
-100
~A
VI = 5.5 V
1
rnA
VI = 2.7 V
25
-0.25
rnA
-130
rnA
210
rnA
-30
-70
~A
t All typical values are at VCC = 5 V. TA = 25°C.
* For 110 ports. the parameters IIH and III include the off-state output current.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed 1 second. Set
Va at 0.5 V
to avoid test equipment ground degradation
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
FROM
TO
TEST CONOITIONS
'"0
::a
m
Imax§
<
-
with internal leedback
:E
UNIT
MHz
115
= 200 D.
= 200 D.
5
ns
4.5
ns
See Figure 1
3
ns
Q
5.5
ns
OEI
Q
ns
ten
1.110
0.110
tdis
1.110
0.110
5.5
6.5
6.5
tpd
1.110
O. 110
tpd
ClK!
Q
tpd
ClK
ten
OEI
tdis
tskew
Rl
R2
Internal
Feedback
ns
ns
ns
Skew between registered outputs
§See 1m ax SPECIFICATIONS. Imax does not apply lor TIBPAl20l8·.
2-220
MJ!.X
125
(counter configuration)
with external feedback
m
MIN
125
without leedback
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAs 75265
TIBPAL20L8·7M. TlBPAL20R4·7M. TIBPAL20R6·7M. TIBPAL20R8·7M
TIBPAL20L8·5C. TIBPAL20R4·5C. TIBPAL20R6·5C. TIBPAL20R8·5C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. Each register is preloaded
individually by following the steps given below.
Step
Step
Step
Step
1.
2.
3.
4.
With VCC at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the voltage
level at the output pin.
~
~
a:
preload waveforms (see Note 3)
~/
PIN 11
I--tsu~
I- t
j+- td ---.I
~ tw-+l
I
PIN 1
I
I
a..
t-
d-1
O
I
____-:- __-:-:_--II
1
. . ._-_-_-_-_-_:_-_-_-_-_-_-_ :::
:
REGISTERED I/O
I
I
I
'>_--<
-----'.
Q
oa:
a..
I
I
:::;)
I
I
I
"M
;t:<'-O-U-T-P-U-T-- vOH
"-. _ _ _ _ _ _ _.J. -
-
Vll
"-.- - - - - VOL
NOTE 3: Id ~ Isu = Iw = 100 ns 10 1000 ns.
VIHH = 10.25 V 1010.75 V.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-221
TIBPAL20LB·7M, TIBPAL20R4·7M, TlBPAL20R6·7M, TIBPAL20R8·7M
TIBPAL20LB·5C, TlBPAL20R4·5C, TIBPAL20R6·5C, TIBPAL20R8·5C
HIGH·PERFORMANCE IMPACT·X TN PAL® CIRCUITS
f max SPECIFICATIONS
f max without feedback. see Figure 1
In this mode. data is presented at the input to the flip-flop and clocked through to the Q output with no
feedback. Under this condition. the clock period is limited by the sum of the data setup time and the data
hold time (tsu + th). However, the minimum f max is determined by the minimum clock period
(twhigh +twlow).
Thus, f max without feedback =
1
or
(tw high + tw low)
(tsu + th)
ClK
lOGIC
ARRAY
"'0
::D
o
C
c:
FIGURE 1. f max WITHOUT FEEDBACK
f max with internal feedback. see Figure 2
o
-I
"'0
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal
delay from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
::D
Thus, f max with internal feedback =
S
m
Where tpd ClK-to-FB is the deduced value of the delay from ClK to the input of the logic array.
m
~
1
(tsu +tpd ClK-to-FB)
ClK
lOGIC
Q
ARRAY
j + - - tsu
---I~W"_ tpd CLK-tO-FB--+!
FIGURE 2. f max WITH INTERNAL FEEDBACK
2-222
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20L8·7M,TIBPAL20R4·7M, TlBPAL20R6·7M, TIBPAL20R8·7M
TIBPAL20L8·5C, TlBPAL20R4·5C, TIBPAL20R6·5C, TIBPAL20R8·5C
HIGH·PERFORMANCE IMPACT·XT. PAL® CIRCUITS
f max SPECIFICATIONS
f max with external feedback. see Figure 3
This configuration is a typical state-machine design with feedback signals sent off-chip. This external
feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest
path defining the period is the sum of the clock-to-output time and the input and setup time for the external
signals (tsu+tpd ClK-to-O).
Thus. f max with external feedback
=
1
(tsu +tpd ClK-to-O)
CLK
LOGIC
ARRAY
ai--....-4.NEXT DEVICE
3:
w
rl4-----tsu---......+l4-tPd CLK.to.a-+ ts u1
:>
w
FIGURE 3. f max WITH EXTERNAL FEEDBACK
a:
Q.
f--,
.........
.....
>8
tr:l
v
a
C1
1
~~l
tO
::J
C
oa:
Q.
110
FIGURE 4. PROPAGATION DELAY FROM ClKt to 1/0. THRU LOGIC ARRAY
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 76265
2-223
TIBPAL20L8·7M, TIBPAL20R4·7M, TIBPAL20R6·7M, TIBPAL20R8·7M
TIBPAL20L8·5C, TIBPAL20R4·5C, TIBPAL20R6·5C, TIBPAL20R8·5C
HIGH·PERFORMANCE IMPACT·XTM PAl@ CIRCUITS
PARAMETER MEASUREMENT INFORMATION
51
R1
FROM OUTPUT_-4II-_"'_"'_ _ TEST
UNDER TEST
POINT
CL
(See Nole A)
R2
LOAD CIRCUIT FOR
3·STATE OUTPUTS
~- •. ~.~
3V
TIMING
INPUT
"'0
::rJ
4-----
It-
tsu~th
~
1.5V
;IV
o
C
I
c:
-I
L1.5V
INPUT
"'0
::rJ
--'1
Ipd
m
I
I
IN.PHASE
OUTPUT
~
I.
I
IJ
T
1_ _ •
Ipd -,.....--...
OUT·OF·PHASE
OUTPUT
(See Nole D)
1.5V
\L' \ 1.SV
0
I4---+a- Ipd
I J - - VOH
I ~V
I
Ipd
!I:"":": VOH
T 1.5V
I
3V
0
OUTPUT~3V
CONTROL
(Iow.level
enabling)
WAVEFORM 1
S1 CLOSED
(See Nole B)
- - VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
---JI
----
I
1.5 V
1.5 V
/I
~---- 0
I"n....l
i+"
I
I I I dls -+! l+I \ ___ L~I_ ~ 2.5V
1.5 V
..L
I.
I ___ 'L
I
.
- L VOL +0.5 V
I
VOL
~I
3 V
0
VOLTAGE WAVEFORMS
PULSE DURATIONS
\-;.~V--3V
~
t.,
LOW.LEVEL~I
.
I
PULSE
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(")
S
m
PULSE~··~·
o
ct--1.5V
DATA
INPUT
o
HIGH.LEVEL
'/1.5 V
. ~
len -rI
WAVEFORM 2
S1 OPEN
(See Nole B)
I!
l
I+-
14-
IdIS-+!
~~ _
-
VOL
I ...i'
~- VOH
£.-=-.
_
_
::H;.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. 3·STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis'
B. Waveform 1 is for an output with intern'al conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR '" 10 MHz. tr = tf '" 2 ns. duty cycle = 50%.
D. When measuring propagation delay times of 3-5tate outputs, switch 51 is closed.
E. Equivalent loads may be used for testing.
FIGURES
2·224
TEXAS .."
INSfRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
TlBPAL20LB·10M, TIBPAL20R4·10M, TIBPAL20R6·10M, TIBPAL20RB·10M
TIBPAL20LB·7C, TIBPAL20R4·7C, TlBPAL20R6·7C, TIBPAL20RB·7C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
D3307, OCTOBER 1989
•
•
Functionally Equivalent, but Faster than
Existing 24·Pin PALs
•
Preload Capability on Output Registers
Simplifies Testing
•
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High!
•
TlBPAL20LB'
M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE
High·Performance Operation:
f max (no feedback!
TIBPAL20R'·7C Series, .. 100 MHz
TIBPAL20R'·10M Series ... 62.5 MHz
f max (internal feedback!
TIBPAL20R'·7C Series ... 100 MHz
TIBPAL20R'·10M Series ... 62.5 MHz
f max (external feedback!
TIBPAL20R·7C Series ... 74 MHz
TIBPAL20R'·10M Series ... 55.5 MHz
Propagation Delay
TIBPAL20L'·7C ... 7 ns Max
TlBPAL20L'·1OM ... 10 ns Max
(TOP VIEW)
Vcc
I
o
110
1/0
1/0
1/0
1/0
1/0
o
TIBPAL20LS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
U
U
___ Uz>_o
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Security Fuse Prevents Duplication
•
Dependable Texas Instruments Quality and
Reliability
4
3
2
1 28 27 26
25
24
23
22
110
110
110
NC
110
19
110
10
110
"
121314 15 16 17 18
DEVICE
'PAL20L8
'PAL20R4
'PAL20R6
'PAL20R8
3-STATE
I INPUTS
o OUTPUTS
14
12
12
12
2
0
0
0
REGISTERED
Q OUTPUTS
1/0
PORTS
0
6
4
NC - No internal connection
2
0
Pin assignments in operating mode
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
--QU--O
ZZ
(!)
description
These programmable array logic devices feature high speed and functional equivalency when compared
with currently available devices. These IMPACT-X~ circuits combine the latest Advanced Low-Power
Schottky t technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes
for conventional TTL logic. Their easy programmability allows for quick design of custom functions and
typically results in a more compact circuit board. In addition, chip carriers are available for further reduction
in board space.
All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow
loading of each register asynchronously to either a high or low state. This feature simplifies testing because
the registers can be set to an initial state prior to executing the test sequence.
The TIBPAL20' M series is characterized for operation over the full military temperature range of - 55°C
to 125°C. The TIBPAL20' C series is characterized for operation from OOC to 75°C.
IMPACT-KIIII is a trademark of Texas Instruments Incorporated.
PAL® is a registered trademark of Monolithic Memories, Inc.
t Integrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments, U.S. Patent Number 3,463,975.
This document contains information on products in
more than ana phase of development. The status of
88ch device is indicated on the pagafs) specifying its
electrical characteristics.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright
© 1989, Texas Instruments Incorporated
2-225
TIBPAL20R4·10M, TIBPAL20R6·10M, TIBPAL20R8·10M
TIBPAL20R4·7C, TIBPAL20R6·7C, TIBPAL20R8·7C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
TIBPAL20R4'
M SUFFIX . .. JT PACKAGE
C SUFFIX . .. JT OR NT PACKAGE
TIBPAL20R4'
M SUFFIX . .. FK PACKAGE
C SUFFIX . .. FN PACKAGE
ITOPVIEW)
(TOP VIEW)
CLK
VCC
~ u t3 0
--uz>_",
I
110
110
4
3 2
1 2827 26
Q
I
5
25
Q
I
6
24
Q
23
Q
22
NC
21
Q
Q
Q
110
110
10
20
Q
110
11
I
4:.:::......-.:.::...
GN 0
110
12131415 1617 18
0E
TIBPAL20R6'
M SUFFIX . .. JT PACKAGE
TIBPAL20R6'
M SUFFIX . .. FK PACKAGE
C SUFFIX . .. FN PACKAGE
nop VIEW)
C SUFFIX . .. JT OR NT PACKAGE
(TOP VIEW)
CLK
I
u ~ 0
__ :J
uz>_'"
110
4321282726
VCC
Q
Q
Q
Q
Q
25
Q
24
Q
I
7
23
Q
NC
8
9
22
NC
Q
19
Q
Q
Q
10
11
1/0
I
12131415 16 17 18
GND L...l:;:""'-..:::Jf.J OE
TIBPAL20R8'
M SUFFIX . .. JT PACKAGE
C SUFFIX . .. JT OR NT PACKAGE
TIBPAL20R8'
M SUFFIX . .. FK PACKAGE
C SUFFIX . .. FN PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
I
VCC
I
Q
4
3
2
1 28 27 26
Q
25
Q
24
Q
23
Q
22
Q
Q
Q
I
Q
I
12131415161718
GND L...l:;:""'-..:::J,.JOE
- -
~ ~Io
-
0
l!J
NC-No internal connection
Pin assignments in operating mode
2-226
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
TlBPAL20L8-10M. TlBPAL20R4-10M
TIBPAL20L8-1C. TIBPAL20R4-1C
HIGH-PERFORMANCE IMPACT-X™ PAl® CIRCUITS
functional block diagrams (positive logic)
TlBPAl20lB'
EN ;;'1
&
vh-----o
b-----o
b-...._ ....-I/O
14
b--e-I_.....-I/O
6
h--6I_.....-
liD
h-a+_4__-
liD
h--a-I_.....-
liD
h--a-I___-
liD
6
TIBPAl20R4'
OE-----------------~
CLK-------------------_________~
&
;;'1
1=0
vb----- 0
10
t--i-----{;=l-
20X C>
12
0
20
h---I--o
vb-....- ......_.J._-
I/O
b-__~......_.J._-
1/0
b-.....J._..._+--
I/O
h-....~...._+_-I/O
4
'V denotes fused inputs
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-227
TIBPAL20R6·10M, TIBPAL20R8·10M
TIBPAL20R6·7C, TlBPAL20R8·7C
LOW·POWER HIGH·PERFORMANCE IMPACT·XT. PAL® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20RS'
~--------~----------------
1/0
(17)
>-- ..
1720
1760
1800
1/0
:>--d
1840
1880
"
1920
1960
2000
2040
2080
2120
(16)
110
2160
2200
"
2240
2280
:>--d
2320
2360
2400
I ( 10)-
(18)
~
V
.....r---'
1600
(9)_
I 10
1520
1560
1640
1680
(8) _
(19)
2440
2480
2520
(15)
o
(14)
v
~
I( 1!.!r-
.....
-
(13)
Fuse Number == First Fuse Number + Increment
Pin numbers shown are for JT and NT packages.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2·229
TIBPAL20R4·10M
TIBPAL20R4·7C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
logic diagram (positive logic)
CLK
~----------------------~I7.N~C~RE~M~E~N~T~---------------------------'
/~O--~4~---B----~1~2~--1~6~~~~--~24----~2~B--~3~2~~3~6~\
,
121~
"
FI RST
FU SE
NU MBERS
~V
141
v
(51
1""1-
0
40
80
120
160
200
240
280
)-
320
360
400
440
480
520
560
600
161
'0
f>'.J
~
V
1560
()
1600
1640
1680
>--
1720
1760
1800
1840
1S80
.....
1920
2040
~
~
'0
2120
2160
2200
2240
2280
2320
11BI
a
' ] 1171
a
V""
'0
c,
v
1161
J
r---..
2360
2400
2440
2480
]-
2520
I
....
1151
"~
1/0
1/0
.....
I
1'2J.r-
a
c,
:J
2080
!
1141
I
r
l
~
31-
use Number = First Fuse Number + Increment
Pin numbers shown are for JT and NT packages
2-230
a
c,
]
1960
2000
1101~
~I
v
~b
-
\-
1280
1520
...
V
1- I---'
"
960
1000
1480
II~
I10
c,
1360
1400
1440
IIBI
1211
D-~r:J ".,
1320
1171
I10
'.J
1120
1160
1200
1240
...
~
1221
~~o
640
680
720
760
800
840
880
920
1040
1080
I
1231
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OE
TIBPAL20R6·10M
TlBPAL20R6·7C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
logic diagram (positive logic)
elK
11 }
v
..
INCREMENT
/
0
4
8
12
16
20
24
28
32
I~
....
4} ....
1231
.A
J]
80
120
160
200
240
280
"
320
360
400
440
480
520
560
600
)-
"'l.....
>-
800
840
880
920
G-
960
1000
1040
1080
L>-
1120
1160
1240
.A
1320
1360
1480
1520
1560
10
~~
Cl
1880
<}
1920
1960
2000
>-~
2040
2080
2120
2160
2200
Cl
1.1
rv--
11 61
o
.A
2240
2280
2320
2360
'~....
~
~!
B
>-
1800
I~
....
~
11
Cl
.A
1840
l!!l.t
12010
"
rv--
10
"
1600
1640
1680
1720
1760
~ iJ
Cl
o
t--
>-
1400
1440
1,'0
Il,.. '"
iJ
10
Cl
"
1280
17}
10
ID
1200
16}
122}
B
Cl
640
680
720
760
15}
"
'"
FI RST
FU SE
0
NU MBERS 40
I~
36
2400
2440
2480
2520
~
115}
1/0
....
,I
111
TT
Fuse Number = First Fuse Number + Increment
Pin numbers shown are for JT and NT packages
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1141
~
+}
I
OE
2-231
TlBPAL20R8·10M
TlBPAL20R8·7C
HIGH IMPACT·XTM PAl® CIRCUITS
logic diagram (positive logic)
c lK
(11
v
INCREMENT
"0
4
8
16
12
"
20
24
28
32
~
FIR ST
FU SE
0
NU M8ERS 40
(31",
v
4)
(51
640
680
720
760
800
840
880
920
-t.
...
(6)",
...r
.;1
'"
)-
(20
B
r~~
V
IO
Q
Q
C1
.....
"
D-
1520
1560
.....
""
1600
1720
)-
1800
)----'
8....
B
10
(18
Q
C1
~
10
:l(17
....
Q
C1
1840
1880
1.....,
1920
1960
2000
r-
2040
2080
2120
2160
2200
J....
(16
1.
(15
A
IO
Q
C1
....
2240
2280
~
2320
2360
2400
2440
2480
...
1
R
.....
1760
10)~
Q
"
960
1000
1040
1080
,120
'160
1200
1240
1680
9)
(21
V
.(.C1
1640
.4-
Wl
b
C1
1440
1480
(8)",
Q
---'
) - J~
1360
1400
4-
(23)
....
C1
mg
(71",
,
>- El]~
80
120
160
200
240
280
320
360
400
440
480
520
560
600
36
vo-
Q
C1
2520
....
.....,
(14)
11 ...
~ 1-1
"1.-
~;31_
OE
Fuse Number =:: First Fuse Number + Increment
Pin numbers shown are f o r J T and NT packages.
2-232
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
TlBPAL20LB-' OM, TIBPAL20R4-' OM, TIBPAL20R6-' OM, TIBPAL20RB-' OM
HIGH-PERFORMANCE IMPACT-XTM PAl® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°e
Storage temperature range ......................................... - 65 °e to 150 °e
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
VCC
V,H
V,L
IOH
lOL
Supply voltage
High-level input voltage (see Note 2)
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
V
V
mA
mA
MHz
ns
ns
ns
ns
2
5.5
O.B
-2
0
62.5
Low-level input voltage (see Note 2)
High~level
output current
low-level output current
12
fclock
Clock frequency
tw
Pulse duration, clock (see Note 2)
tsu
th
Hold time, input or feedback after ClK;
TA
Operating tree-air temperature
LHigh
I low
Setup time, input or feedback before CLKt
8
8
10
0
-55
25
125
~
W
°c
fclock, t w , tsu, and th do not apply for TlBPAl20l8'.
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system andlor
tester noise. Testing these parameters should not be attempted without suitable equipment.
:;
w
a:
c..
I-
(.)
:::;)
Q
oa:
c..
r.R:Uf:'~!~::E: ~::rg~·:::':·:f"d::.r::~~~~
Cha.....ristic data .... DlliBr _ificationl .r. design
goall, r.... I••trum.nts resarves III. right 10 chlnge
Dr discontinue thase products with aut notice.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-233
TIBPAL20L8·10M, TIBPAL20R4-10M, TlBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-XTM PAl® CIRCUITS
electrical characteristics over recommended operating free-air temperature range
PARAMETER
~
4.5 V,
II
VOH
Vee
~
4.5 V,
10H
~
Val
Vee
~
4.5 V,
10l
~
10ZH'
110 ports
0, Q outputs
~
5.5 V,
Va
20
2.7 V
100
-20
-250
~A
~
5.5 V
Vee
~
5.5 V,
VI
~
2.7 V
Ill'
10S§
Vee
Vee
~
5.5 V,
5 V,
VI ~ 0.4 V
Va ~ 0.5 V
Outputs open
lec
Vee ~ 5.5 V,
VI ~ OV,
1- 1 MHz,
I ~ 1 MHz,
I ~ 1 MHz,
VI - 2 V
Va ~ 2 V
6
pF
VelK ~ 2 V
6
pF
110 ports
I All others
~
OE
~
0.4 V
V
VI
VIH
1
100
25
-0.08 -0.25
-30
-70 -130
I TA
I TA
~ 25°e and 125°e
140
~ -55°C
220
250
5
~A
mA
~A
mA
mA
mA
pF
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted) (see Figure 5)
PARAMETER
FROM
Imax'
-I
~
0.5
Va
C
S
m
0.3
V
V
3.2
5.5 V,
eclk
m
12 mA
UNIT
5.5 V,
eo
"tI
2.4
-2 mA
MAX
-1.5
~
Ci
:a
~
-0.8
~
IIH
(')
~
Typt
Vee
110 ports
II
C
Vee
MIN
-18 mA
Vee
10Zl'
o
~
Vec
0, Q outputs
"tI
:a
TEST CONDITIONS
VIK
I
TO
MIN
Without leedback
62.5
With internal feedback (counter configuration)
62.5
With external leedback
55.5
Typt
MAX
UNIT
MHz
tpd
1,1/0
0,110
3
6
10
tpd
ClKi
Q
2
4
8
ns
ns
tpd#
elKi
Feedback input
5
ns
ten
OEI
Q
2
ns
OEi
Q
2
4
4
10
tdis
10
ns
ten
tdis
1,110
0,1/0
1.1/0
0,1/0
3
2
6
6
10
10
ns
ns
tAli typical values are at Vee ~ 5V,TA ~ 25°e.
'110 leakage is the worst case 01 10Zl and III or 10ZH and IIH, respectively.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Set Va at 0.5 V
to avoid test equipment ground degradation.
, See section on f max specifications.
#This parameter applies to TlBPAL20R4' and TIBPAL20R6' only (see Figure 2 for illustration) and is calculated from the measured f max
with internal feedback in the counter configuration.
r.R~'::'Uf:'~~~~!E: ~.::r:.:a:::':":l'·J::.r.::::.c:
Characteristic data and otller specifications a.. dasign
2 -2 34 goals, Taxaslnstruments ,es...es tile right ta chango
or discontinue these products without nDtice.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20LB-7C, TlBPAL20R4-7C, TlBPAL20R6-7C, TIBPAL20RB-7C
HIGH-PERFORMANCE IMPACT-XTM PAl® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 75 °e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins duri~g a programming cycle.
recommended operating conditions
PARAMETER
Vee
Supply voltage
VIH
High-level input voltage (see Note 2)
Vil
Low-level input voltage (see Note 2)
IOH
High-level output current
IOl
Low-level output current
fclock
Clock frequency
tw
Pulse duration, clock (see Note 2)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
5.5
V
2
0.8
-3.2
24
100
0
I
V
mA
mA
MHz
High
5
ns
I low
5
ns
ns
tsu
Setup time, input or feedback before CLKt
7
th
Hold time, input or feedback after elK;
0
TA
Operating free-air temperature
0
25
75
ris
De
fclock. t w , tsu, and th do not apply for TIBPAl20l8'.
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or
tester noise. Testing these parameters should not be attempted without suitable equipment.
PRODUCTION DATA do•• ments contain information
current IS of publicltion date. Products conform to
Ipacifications per the terml of Texil Instruments
=~~:~i~ai~:I'::li ~~:i:; ~~,::.:~:~~ not
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-235
TIBPAL20L8·7C, TIBPAL20R4·7C, T1BPAL20R6·7C, TIBPAL20R8·7C
'HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
electrical characteristics over recommended operating free·air temperature range
PARAMETER
TEST CONDITIONS
= 4.75 V.
= 4.75 V.
= 4.75 V.
VIK
Vee
VOH
Vee
VOL
Vee
10ZH t
10ZL t
Vee - 5.25 V.
II
IIHt
Vee
IlL t
Vee
10S§
Vee
Vee
Vee
=
=
=
=
=
II
=
10H
= -3.2 mA
= 24 mA
2.4
TYpt
MAX
UNIT
-0.8
-1.5
V
3.2
0.3
V
Vo - 2.7 V
100
~A
= 0.4 V
= 5.5 V
VI = 2.7 V
VI = 0.4 V
Va = 0.5 V
-100
~A
0.2
mA
Va
5.25 V.
VI
5.25 V.
5.25 V.
5.25 V.
V
0.5
10L
5.25 V.
MIN
-18 mA
-30
25
~A
-0.08 -0.25
mA
-70
-130
mA
160
210
mA
Vee'" 5.25 V.
Outputs open
VI - 2 V
5
pF
eo
VI = 0 v.
f - 1 MHz.
f - 1 MHz.
=
2 V
6
pF
eclk
f
=
6
pF
lee
ei
=
Vo
1 MHz.
VeLK
2 V
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted) (see Figure 6)
PARAMETER
f max '
"
I
FROM
TO
MIN
Without feedback
100
With internal feedback (counter configuration)
100
With external feedback
74
II
Typt
1 or 2 outputs switching
3
5.5
7
8 outputs switching
3
6
7.5
2
4
6.5
1.1/0
tpd
eLKi
a
tpd"
eLKi
Feedback input
ten
OEI
a
a
2
0.1/0
0,1/0
2
6
tdis
OEi
ten
1,1/0
tdis
1,1/0
tskew l
Skew between registered outputs
UNIT
MHz
tpd
0.1/0
MAX
ns
ns
3
ns
4
7.5
ns
2
4
7.5
ns
3
6
9
9
ns
0.5
ns
ns
t All typical values are at Vee = 5 V, TA = 25°e.
t 1/0 leakage is the worst case of 10ZL and IlL or 10ZH and IIH, respectively.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Set Va at 0.5 V
to avoid test equipment ground degradation.
, See section on f max specifications.
#This parameter applies to TIBPAL20R4' and TlBPAL20R6' only (see Figure 2 for illustration) and is calculated from the measured f max
with internal feedback in the counter configuration.
~ This parameter is the measurement of the difference between the fastest and slowest tpd (CLK-to-Ql observed when multiple registered
outputs are switching in the same direction.
PRODUCTION DATA
documonts contoin info,mation
current as of publication data. Products conform to
spacifications per the terms of Texis Instruments
2-236 ::=~~ir,.i:I~1oi ~:~~~i:; :'lo::s,:~~~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20LB·' OM, TIBPAL20R4·' OM, TIBPAL20R6·' OM, TIBPAL20RB·' OM
TIBPAL20LB·7C, TIBPAL20R4·7C, TIBPAL20R6·7C, TIBPAL20RB·7C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algori~hms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997·5666.
preload procedure for registered outputs (see Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state·machine sequence. Each register is preloaded
individually by following the steps given below.
Step
Step
Step
Step
1.
2.
3.
4.
With VCC at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the voltage
level at the output pin.
preload waveforms (see Note 3)
PIN 11
----J/
~td-1
j4- t su-+j
!+- td -...t
M-tw-./
I
I
I
I
iii
PIN 1
.I_-_-'---~-_-_-_i
.
_-_-_-_-_-__
I
I
I
I
I
I
I
I
--------~~
REGISTERED 110
VIL
I
I
I
~
VIH
I
I
~~--O-UT-P-U-T---VOH
INPUT
~
......- - - - - - - "
- VIL
......- - - - - VOL
NOTE 3: td ~ tsu = tw = '00 ns to 1000 ns.
VIHH = 10.25 V to 10.75 V.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2·237
TIBPAL20L8·' OM, TIBPAL20R4·' OM, TIBPAL20R6·' OM, TIBPAL20R8·' OM
TlBPAL20L8·7C, TIBPAL20R4,7C, TIBPAL20R6·7C, TIBPAL20R8·7C
HIGH·PERFORMANCE IMPACT·XTN PAL@ CIRCUITS
f max SPECIFICATIONS
fmax without feedback. see Figure 1
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no
feedback. Under this condition, the clock period is limited by the sum of the data setup time and the data
hold time (tsu +th). However, the minimum f max is determined by the minimum clock period
(twhigh +twlow).
1
Thus, f max without feedback =
1
or - - - .
(tw high+tw low)
(tsu +th)
FIGURE 1. f max WITHOUT FEEDBACK
f max with internal feedback. see Figure 2
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this conditiQn, the period is limited by the internal
delay from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
Thus, f max with internal feedback =
1
(tsu + tpd ClK-to-FB)
Where tpd ClK-to-FB is the deduced value of the delay from ClK to the input of the logic array.
ClK
lOGIC
Q
ARRAY
r--ISU
---I~~14f-- Ipd elK-Io-FB ~
FIGURE 2. f max WITH INTERNAL FEEDBACK
2-238
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
TlBPAL20LB·10M, TIBPAL20R4·10M, TlBPAL20R6·10M, TlBPAL20RB·10M
TlBPAL20LB·7C, TlBPAL20R4·7C, TIBPAL20R6·7C, TlBPAL20RB·7C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
f max SPECIFICATIONS
f max with external feedback. see Figure 3
This configuration is a typical state-machine design with feedback signals sent off-chip. This external
feedback could go back to the device inputs or to a second device in a mUlti-chip state machine. The slowest
path defining the period is the sum of the clock-to-output time and the input and setup time for the external
signals (t su + tpd CLK-to-Q).
Thus. f max with external feedback =
1
(tsu +tpd CLK-to-Q)
ClK
lOGIC
Q
1--.....-1. NEXT
DEVICE
ARRAY
~r----tsu------'+"'-tpd ClK-to-Q -+tsu...j
FIGURE 3. f max WITH EXTERNAL FEEDBACK
-
~t>y ~.....-
Q
Cl
-!>b= .
I---
J
~ 1
~
1/0
FIGURE 4. PROPAGATION DELAY FROM CLKt to 110. THRU LOGIC ARRAY
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2·239
TlBPAL20L8·' OM,TlBPAL20R4·' OM, TlBPAL20R6·' OM, TlBPAL20R8·' OM
TlBPAL20L8·7C, TIBPAL20R4·7C, TIBPAL20R6·7C, TIBPAL20R8·7C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
CL
R2
(See NoleA)
LOAD CIRCUIT FOR
3·STATE OUTPUTS
[3.5 V] (3 V)
TIMING
INPUT
DATA
INPUT
'/1.5 V
4-----
[0.3 V] (0)
tsu~th
~-:-::-
-.-l' 1.5 V
[3.5 V] (3 V)
~
[0.3 V) (0)
HIGH.LEVEL~
PULSE'
,
[3.5 V] (3 V)
LOW.LEVEL~'
,
PULSE'
1.5V 1.5V
[3.5 V) (3 V)
,
M-Iw
--PI
,
----
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
L
INPUT --./j
1.5V
l\
T
IN.PHASE
I
OUTPUT---'I-.J
Ipd
~Ipd
1/
I
I J __
1.5V I
I
--k--toI
OUT·OF·PHASE
OUTPUT
(See Nole D)
\L
' \ 1.5V
OUTPUT
CONTROL
(Iow·level
enabling)
~
~ Ipd
v:-::
L ~~VV
VOH
1.5 V
I
len
V OH
\::..V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
[0.3 V] (0)
VOLTAGE WAVEFORMS
PULSE DURATIONS
- - - - [3.5 V] (3 V)
" - 1.5V
[0.3 V) (0)
Ipd~
[0.3 V) (0)
-.I
II
CL -
i+"
I I
I "\
I
len
-+!
WAVEFORM 2
S10PEN
-
[0.3 V) (0)
-
LI
~3.3V
}r:-
I
OL
-
I
Io,.-+! l+-
WAVEFORM-1--+I""IV+ 1.5V - I
S1 CLOSED
(See Note B)
[3'5v)(3v)
1.5 V
l
I+-
I
L--~
-
T -
10,.-+1 1+ L
VOL
VOL +0.5 V
\:=E:...
I ..:t
(SeeNOleB)~~___
VOH
:::.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. 3·STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR s 10 MHz, tr and tf S 2 ns, duty cycle = 50%. For M suffix use
the voltage levels indicated in parentheses. For C suffix, use the voltage levels indicated in brackets [ J,
O. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
FIGURES
2·240
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIBPAL20L8·10M, TlBPAL20R4·10M, TIBPAL20R6·10M, TIBPAL20R8·10M
TIBPAL20L8·1C, TIBPAL20R4·1C, TIBPAL20R6·1C, TIBPAL20R8·1C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
8
200~~---+--~--+_--~-+--~~
~>
180
.
~
160
Q.
I
7
6
tPHl (I, 1/0 to 0, 1/01
r--
5
.~
.'"g-
140
u
~
120~~---+--~--+---~-4--~~
__ __ __ __
-75 -50 -25
0
25
50
100~~
~
~
~
L-~
__
75
a:
~PHl (ClK to 0)
I
I
3
tPlH (ClK to 0)
TA = 25°C
CL = 50 pF
R1 = 200 !l
R2 - 390!l
1 OUTPUT SWITCHING
2
o
~~
100 125
4.75
5.25
5
VCC-Supply Voltage-V
4.5
TA-Free-Air Temperature- °C
FIGURE 6
FIGURE 7
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
8
.
c::
I
7
I O~
.,
6
j::
5 ~tPlH (I, 1/0 to 0,1/0)
E
.
>
Qj
a
4
c::
CI
.~
.'"
Q.
!:!
a..
3
2
o
l'\\. \\,
\10 to
t~.:..i--
~ tjHl TlK to 0)
1
tPlH (I, 1/0 to 0, 1/0)
4
c::
o
Q.
::l
VI
..
I'
I
I-"'"
- ---I--
~~~O\
tl'\.l'\ \
VCC - 5 V
Cl-50pF
R1 - 200!l
R2 - 390!l
1 OUTPUT SWITCHING
.
5.5
VCC = 5 V
TA = 25°C ---+----+----+-----1
R1 - 200 !l
R2 = 390 !l ----'----6~_+-__I
14
I'.,
12
j::
10 ~--+---4--_7"~,...::.=+"""""""""::::....,,::=---1
E
.
~
>
8~--+~~~~~~=+--~--~
tpLH (CLK to 0)
c::
.~
6 ~~4,.<~~!:............:=FtPHL (elK to Q)
'"
~
CI
4
a:
I
I
1-~~~--*_-t~P~Hl~(I~,I~/0_rtO-O~,~I,/O~)--___1
2~--~--~----+_--~--~--~
O~--~--~--~----L---~--~
-75 -50 -25
0
25
50 75 100 125
TA-Free-Air Temperature- °C
o
100
200
300
400
500
CL - Load Capacitance - pF
600
FIGURE 9
FIGURE 8
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75286
2·241
TIBPAL20L8·10M, TlBPAL20R4·10M, TIBPAL20R6·10M, TlBPAL20R8·10M
TIBPAL20L8·7C, TIBPAL20R4·7C, TlBPAL20R6·7C, TlBPAL20R8·7C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
FREQUENCY
8-BIT COUNTER MODE
1000
V
I=
III
~J
c
E
II
TA
0
.~
·i
III
is
..,,-
TA
=I O!C
= 25°C
'"c
II
900
I
c
V
V V
V
.....V
BOO
/
..... II~
:2
~
.~
",11
6. -
/
0.5
;3c:o::~ 04.
" 0....
"
! - 0.3
.c
"
Q.
I
0.6
.I!l
~
0
Q
VCC = 5 V
TA = 25°C
R1 = 200 {J
R2 = 390 {J
Cl = 50 pF
B-Bit Counter
0.7
tJl
TA = BOoC
Q;
O.B
I
CC
~
SKEW BETWEEN OUTPUTSt
vs
NUMBER OF OUTPUTS SWITCHING
.....
0.2
I
0.1
~
700
Q.
tJl
~
..."
.!f
600
1
4
10
F-Frequency-MHz
40
0
3
2
100
4
6
7
5
Number of Outputs Switching
FIGURE 10
FIGURE 11
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
B
7
III
C
.
.
I
E
i=
>
a;
Q
..,
J
6 _
tpHl (I. 110 to O. 110)
5 _
tplH (I. I/O to O. 110)
, • + •
4
tPHL\CLK~
3
ttlH (ClK to Q)-
c
..'"
I
0
c.
0
.t
VCC = 5 V
TA = 25°C
Cl = 50 pF
R1 = 200 n
R2 = 390 {J
2
o
+
o
2
3
4
5
6
Number of Outputs Switching
FIGURE 12
tOutput switching in the same direction (tpLH compared to tpLH/tpHL to tPHLl
2-242
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265
7
B
B
TIBPAL20L8·12M, TIBPAL20R4·12M, TIBPAL20R6·12M, TIBPAL20R8·12M
TIBPAL20L8·10C, TIBPAL20R4·10C, TIBPAL20R6·10C, TIBPAL20R8·10C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
03336. OCTOBER 19B9
•
TIBPAL20LB'
M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE
High·Performance Operation:
f max (w/o feedback)
TIBPALZOR'·10C Series ... 71.4 MHz
TIBPAL20R'·12M Series ... 62.5 MHz
f max (internal feedback)
TIBPAL20R'·10C Series ... 58.8 MHz
TIBPAL20R'·12M Series ... 52.6 MHz
f max (external feedback)
TIBPAL20R'·10C Series ... 55.5 MHz
TIBPAL20R'·12M Series ... 48 MHz
Propagation Delay
TIBPAL20L'·10C ... 10 ns Max
TIBPAL20L'·12M ... 12 ns Max
ITOP VIEW)
Vcc
I
o
I/O
110
110
110
110
110
o
I
•
Functionally Equivalent to, but Faster than,
Existing 24·Pin PALs
•
Preload Capability on Output Registers
Simplifies Testing
•
Power·Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•
GN D
'-L':"'''':'::J-'
TlBPAL20LS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
u
u
___ uz>_o
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Security Fuse Prevents Duplication
•
Dependable Texas Instruments Quality and
Reliability
4
3
:2
,
28 27 26
25
I
24
I
23
n
NC
21
10
20
11
19
110
110
110
NC
110
110
110
12 13 14 lS 16 17 18
DEVICE
'PAL20LB
'PAL20R4
'PAL20R6
'PAL20RB
3·STATE
I INPUTS
o OUTPUTS
14
12
12
12
2
0
0
0
REGISTERED
Q OUTPUTS
I/O
PORTS
0
6
4
2
0
4 /3-state buffers)
6 (3-5tate buffers)
8 (3-5tate buffers)
--ou--o
zz
l?
NC - No internal connection
Pin assignments in operating mode
description
These programmable array logic devices feature high speed and functional equivalency when compared
with currently available devices. These IMPACT-X'· circuits combine the latest Advanced Low-Power
Schottky t technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes
for conventional TTL logic. Their easy programmability allows for quick design of custom functions and
typically results in a more compact circuit board. In addition, chip carriers are also available for further
reduction in board space.
Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low
state. This feature simplifies testing because the registers can be set to an initial state prior to executing
the test sequence.
The TIBPAL20'M series is characterized for operation over the full military temperature range of - 55°C
to 125°C. The TIBPAL20'C series is characterized from OOC to 75°C.
IMPACT-X is a trademark of Texas Instruments Incorporated
PAL is a registered trademark of Monolithic Memories Inc.
tlntegrated Schottky-Barrier diode-clamped transistor is patented by Texas Instruments, U.S. Patent Number 3,463,975.
This document contains information on products in
more than one phase of development. The status of
each device is indicated on the pagels) specifying its
electrical charactBristics.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-243
TIBPAL20R4-12M. TIBPAL20R6-12M. TlBPAL20R8-12M
TIBPAL20R4-10C. TIBPAL20R6-10C. TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-XTM PAL® CIRCUITS
TIBPAL20R4'
M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE
TIBPAL20R4'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
(TOP VIEW)
ClK
VCC
:Jut;
I
0
--uz>_:.::
I/O
4
110
3
2
1 28 27 26
Q
Q
Q
Q
1/0
Q
I
2:i
Q
NC
22
NC
1/0
1/0
21
Q
10
20
Q
11
19
1/0
12131415161718
GNO y.:~.......:c::J...' OE
TIBPAL20R6'
M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE
TIBPAL20R6'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
(TOP VIEW)
ClK
25
24
~ u ij e
__ uz>-_
VCC
I
110
4
3
2
1 28 27 26
Q
25
Q
Q
24
Q
22
NC
21
Q
10
20
Q
11
19
Q
Q
Q
Q
Q
I
I
110
I
GN 0 y.:",,-.....:c::J...'
1713;4151617 18
OE
TIBPAL20R8'
M SUFFIX ... JT PACKAGE
C SUFFIX ... JT OR NT PACKAGE
TIBPAL20R8'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
(TOP VIEW)
elK
VCC
I
Q
4
3
2
~
28 27 26
Q
25
Q
24
Q
23
Q
22
Q
21
Q
10
Q
11
I
GNO
20
19
12131415161718
Lt:..::.........:.~ OE
- -
~ ~Io
-
0
C)
NC-No internal connection
Pin assignments in operating mode
2-244
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q
TlBPAL2DLB·12M, TIBPAL2DR4·12M
TIBPAL2DL8·1 DC, TlBPAL2DR4·1 DC
HIGH·PERFORMANCE IMPACT·X'" PAL® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20LB'
EN .. ,
&
'\l[}----O
40X 64
[}----O
'4
20
1:>--.+........-1/0
I:>-...r......-- 1/0
b41tt-+t-1/0
TIBPAL20R4'
OE
EN
C,
CLK
r---s:40 X P4
rwxi>
'2
4
-+'---
~
'V
~
'V
,.,
8
1=0 '\l
---l-
'D
-t-t-i-
-l---c;--+-
o
~
o
~
--,
EN
r---
,.,
'\l
'"
"'\
~
-i-
"'\
--""7
-~
"'\
o
o
1/0
1/0
1/0
1/0
4
I
t\.." denotes fused inputs
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-245
T1BPAL20R6·12M, TIBPAL20R8·12M
TIBPAL20R6·10C, T1BPAL20R8·10C
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
functional block diagrams (positive logic)
TlBPAL20R6'
0e----------------~-------~
1760
1800
1840
c,
Q
Q
Q
(17)
v
Q
....
1880
~
1920
1960
2000
2040
2080
2120
2160
2200
;=J
~ I
2240
2280
2320
2360
2400
2440
2480
2520
(16)
I/O
j
I
(11 ) ..
...
""
I
I
(15)
:J
4-
!,14)
I
'J
I
~
Fuse Number = First Fuse Number + Increment
Pm numbers shown are for JT and NT packages
2-248
,D
c,
1520
(10)
f61rJ ""
.r
1560
(!;
1
.r
1440
1480
I
(21) I
...
.....,
640
680
720
760
800
840
880
920
1360
1400
I (B) ..
r
j
'"
1320
I(~
I /0
1"-
1120
1160
1200
(6) ..
(22)
V
960
1000
1040
1080
I
(23)
.A
""
80
120
160
200
240
280
1(5) ....
1'1
4
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
I/O
TlBPAL20R6·12M
TIBPAL2DR6·1 DC
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
logic diagram (positive logic)
elK
11)
......!C
INCREMENT
"0
II~
"
4
B
12
16
20
24
2B
32
36
"
123)
.A
......
FIR ST
FU SE
0
NU MBERS 40
80
120
160
200
240
280
...,
(3)
II ~
....
(5) ....
....
--=>-
320
360
400
440
480
520
560
600
)--
::r.;-
960
1000
1040
1080
1120
.A
"
1360
1440
1520
1560
~
~
....
119
r----'
~B
V
A
"
~~~g
1680
::r-
1720
1760
1800
1840
1880
....
1920
1960
2000
~
,.
2080
2120
iJ
117
""V"'"
c,
r----'
~
2040
1rl116
V
c,
2160
.A
2200
2240
2280
l
2320
2360
2400
(15)
.A~J
2440
2480
1~
fl]
)0
c,
c,
1480
v
,. ~
~
::r- ,.
~
1240
1400
(9)
~
c,
1320
-;...
o
,.
~I.l""
. . . .::r- ,.
1280
IB)
1.'0
.A -
"
640
680
720
760
800
840
880
920
1200
171
122)
c,
1160
(6) ...
-J
2520
I/O
'"
114)
II 11 )
-'}-+-I
"
113)
L.::}--. OE
Fuse Number = First Fuse Number + Increment
Pin numbers show n are fo r J T and NT packages
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-249
TIBPAL20R8·12M
TlBPAL20R8·10C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
logic diagram (positive logic)
c lK
'....v
(1)
INCREMENT
"0
4
8
16
12
"
20
24
28
32
(2) ....
36
,
(23)
.....
~
FIR ST
FU SE
0
40
80
'20
'60
200
240
280
NU MBERS
(3)"
4)"
v
(5)"
b- ~;J'"
10t-'-v--
....
....
320
360
400
440
480
520
560
600
r"1~
640
680
720
760
800
840
880
920
>-
1080
r-
1120
1160
1200
1240
1400
1440
)-
1480
'520
1560
"1....
1720
)-
1760
1800
1880
"
1920
1960
20DO
2040
LJ-
2080
2120
2160
2200
1....
2240
2280
2320
r-
2360
2400
I
2440
2480
2520
IO
a
(19
'-v--
a
1......
a
~ 1..
10
5
5
10
10
Cl
~
10
Cl
(18
(17
v
a
~
a
~
a
..r----'
(14)
(1 1)
.j- r-I
3)_
OE
Fuse Number = First Fuse Number + Increment
4'
Pin numbers shown are for JT and NT packages
2·250
v
Cl
Cl
1840
1~
~(20
~
1..
~
10
Cl
1600
1640
1680
""""1-
a
"1- r----
m~
(9)
(21
Cl
1360
(8)
i:l.
"V""
..r r----
1040
(7)
~
IO
Cl
960
1000
(6)
a
Cl
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265'
T1BPAL2DLB·12M, T1BPAL2DR4·12M, TIBPAL2DR6·12M, TIBPAL2DRB·12M
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise notedl
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free·air temperature range ...............' . . . . . . . . . . . . . . . . . .. - 55 DC to 125 DC
Storage temperature range ......................................... - 65 DC to 150 DC
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
MIN
4.5
2
Vee
VIH
Vil
IOH
IOl
fclock
Supply vollage
Iw
Pulse duration, clock
Isu
Ih
TA
Setup time, input or feedback before CLKt
High-level input voltage
NOM
5
MAX
5.5
5.5
0.8
-2
12
62.5
25
125
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
I High
I low
Hold lime, inpul or feedback after elK!
Operating free-air temperature
fclock' Iw, Isu' and Ih do not apply for TIBPAl20l8'.
0
9
9
12
0
-55
UNIT
V
V
V
mA
mA
MHz
ns
ns
ns
ns
°e
~
W
:;
w
a:
0..
I-
o
~
c
oa:
0..
PRODUCT PREVIEW d......nll OIl111io infarmati••
on P!'odlCIJ in the Ionn.ti...r daigl ~huo of
d...lop....t, C•• r.ctarllti. data anil olh.r
lpacifiCltiaM Ira dnIa....... T_I iMtru_1I
........ the right to ....... or d"OInll••••_
pr.d.CIJ with.ut loti...
TEXAS •
IN STRUM ENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2·251
TIBPAL20L8-12M •. TlBPAL20R4-12M. TIBPAL20R6-12M. TlBPAL20R8-12M
HIGH-PERFORMANCE IMPACT-XTM PAl® CIRCUITS
electrical characteristics over recommended free-air operating temperature range
PARAMETER
TEST CONDITIONS
VIK
VCC
VOH
VOL
VCC
10ZH
VCC
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
VCC
=
VCC
=
10ZL
VCC
I 0, Q
outputs
11/0 ports
II
I I/O ports
I All others
IIH
."
::u
o
C
c:
(")
m
:$
m
~
=
MIN
-18 rnA
10L
Vo
= -2 rnA
= 12 rnA
= 2.7 V
5.5 V,
Vo
=
5.5 V,
VI
10H
=
=
=
=
5.5 V,
VI = 0.4 V
Vo = 0.5 V
ICC
VCC
5.5 V,
Outputs open,
Ci
f
Co
f
Cclk
f
=
=
=
5.5 V,
3.2
0.25
0.5
V
100
pA
-20
-0.25
pA
rnA
rnA
2.7 V
-30
-70
VI = 0,
OE at VIH
=2V
=2V
VCLK = 2
UNIT
V
V
1
VI
VCC
MAX
-1.5
100
5.5 V,
VCC
-0.8
5.5 V
=
IlL
=
2.4
Typt
0.4 V
VCC
10S*
pA
25
-0.25
rnA
-130
rnA
210
rnA
1 MHz,
VI
7
1 MHz,
Vo
8
pF
12
pF
1 MHz,
V
pF
switching characteristics over recommended operating free-air temperature range (unless otherwise
n.oted)
PARAMETER
FROM
TO
TEST CONDITIONS
without feedback
MIN
Typt
MAX
UNIT
62.5
with internal feedback
frnax§
MHz
52.6
(counter configuration)
-I
."
:zJ
II
with external feedback
48
3
8
12
ns
2
5
10
ns
Q
3
8
10
ns
OE!
Q
2
8
10
ns
ten
I, I/O
0, I/O
3
8
12
ns
tdis
I, I/O
0, I/O
2
8
12
ns
tpd
I, I/O
0, I/O
R = 390 II,
tpd
CLK!
Q
See Figure 1
ten
OE
tdis
t All typical values are at VCC
=
5 V, TA
=
R = 750 II,
25°C.
:J: Not more than one output should be shorted at a time, and duration of the short circuit should not exceed 1 second. S~t
to avoid test equipment ground degradation.
§See f rnax SPECIFICATIONS. f max does not apply for TIBPAL20L8'.
PRODUCT PREVIEW dD"".11111 OIl1111i. i.famalla.
D. prodoOll i. the lor..lli.. Dr ....... ~."" of
dlvaID, •••I. Chor.elorlolic dall ••~ Dlh.r
,;;
2-252 =~::"
~~r.:'",;,T=~~=,:,.:
prodoOll wlthlHll ROIie..
TEXAS •
INSTRUMENlS
POST OFFICE !;lOX 655303 • DALLAS, TeXAS 75265
Vo
at 0.5 V
TlBPAL2DL8·' DC. TlBPAL2DR4·' DC. TIBPAL2DR6·' DC. TIBPAL2DR8·' DC
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 75°C
Storage temperature range ............................... :......... - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
MIN
4.75
2
Supply vollage
VCC
VIH
VIL
IOH
IOL
fclock
Clock frequency
Iw
Pulse duration, clock
Isu
th
TA
Selup lime. inpul or leedback before CLK!
Hold lime, inpul or leedback aller CLK!
Highwlevel input voltage
NOM
5
MAX
5.25
5.5
O.S
-3.2
24
71.4
25
75
Low-level input voltage
High-level output current
Low-level output current
a
I High
I Low
7
7
10
a
a
Operating free-air temperature
UNIT
V
V
V
mA
mA
MHz
ns
ns
ns
ns
°c
Iclock' Iw, Isu, and Ih do nol apply lor TIBPAL20LS'.
PRODUCTlOIi DATA documants contain information
currant 8S of publicatiaR data. Products conform to
specifications par the tarms of Taxas Instrumants
::C::~~i~8{~::ri =:~ti:r :.~o:=::~::-.~s not
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265
2·253
TIBPAL2DLB·1 DC, TlBPAL2DR4·1 DC, TIBPAL2DR6·1 DC, TIBPAL2DRB·1 DC
HIGH·PERFORMANCE IMPACT·XTMPAL® CIRCUITS
electrical characteristics over recommended free-air operating temperature range
PARAMETER
TEST CONDITIONS
MIN
VIK
Vcc = 4.75 V.
II = -18 mA
VOH
VCC = 4.75 V.
10H = -3.2 mA
VCC = 4.75 V.
10L - 24 mA
VOL
0, Q outputs
VCC = 5.25 V,
Vo = 2.7 V
VCC = 5.25 V,
Vo = 0.4 V
II
IIHt
VCC = 5.25 V,
VI = 5.5 V
VI = 2.7 V
IlL t
VCC = 5.25 V,
lOS!
VCC = 5.25 V,
VI = 0.4 V
Vo - 0.5 V
VCC = 5.25 V,
VI = 0,
Outputs open,
OE at VIH
10ZH
10ZL
1/0 ports
0, Q outputs
1/0 ports
VCC = 5.25 V,
ICC
Typt
MAX
~0.8
-1.5
2.4
V
V
0.3
0.5
20
100
-20
-100
0.2
-30
UNIT
-70
V
~A
~
mA
25
~
-0.25
mA
-130
mA
210
mA
Ci
1= 1 MHz,
VI = 2 V
7
Co
1= 1 MHz,
Vo = 2 V
8
pF
pF
Cclk
1= 1 MHz,
VCLK - 2 V
12
pF
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
FROM
TEST CONDITIONS
TO
with internal feedback
Imax'
MIN
MAX
58.8
(counter configuration)
UNIT
MHz
55.5
with external feedback
3
8
10
ns
2
5
8
ns
7
ns
6
6
10
ns
10
ns
B
10
ns
B
10
ns
tpd
I, I/O
0, I/O
tpd
ClK!
Q
R1 = 200O,
tcd#
ClKt
feedback
See Figure 1
ten
DEI
Q
2
tdis
OE!
Q
ten
I, I/O
0, I/O
tdis
I, I/O
0, I/O
2
3
2
tskew
Typt
71.4
without feedback
R2 = 390O,
0.5
Skew between registered outputs
ns
t All typical values are at VCC = 5 V, TA = 25°C.
:j: For 1/0 ports, the parameters IIH and IlL include the off-state output current.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed 1 second.
~ See Imax SPECIFICATIONS. f max does not apply lor TIBPAL20LB'.
#This parameter applies to TlBPAL20R4' and TIBPAL20R6' only (see Figure 2 for illustration) and is calculated from the measured f max
with internal feedback in the counter configuration.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
2 254 specifications par the tarms of Texas Instruments
-
:'~=~i~ai~:1~1e ~!:~:~i:; :,~o::~::::A~r~~S not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20L8·12M, TIBPAL20R4·12M, TlBPAL20R6·12M, TlBPAL20R8·12M
TlBPAL20LB·1 DC, TIBPAL20R4·1 DC, TIBPAL20R6·1 DC, TlBPAL20R8·1 DC
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications. algorithms. and the latest information on hardware. software. and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available. upon request. from the nearest TI field sales office. local
authorized TI distributor. or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. Each register is preloaded
individually by following the steps given below.
Step
Step
Step
Step
1.
2.
3.
4.
With VCC at 5 volts and Pin 1 at V,L. raise Pin 11 to V,HH.
Apply either V,L or V,H to the output corresponding to the register to be preloaded.
Pulse Pin 1. clocking in preload data.
Remove output voltage. then lower Pin 11 to V,L. Preload can be verified by observing the voltage
level at the output pin.
preload waveforms (see Note 3)
~
....._-_-__ _ VIHH
PIN 11
-
VIL
I+-tsu~
PIN 1
t+- td --+I
j+--td-+!
14- tw--.t
I
I
)
I
____-:-__--.,.:_---1
>-<
IL_-_-_-....;..-_-_-.;..:_-_-_-_-_-_-_ VIH
:
I
I
I
I
I
I
I
REGISTERED 1 1 0 - - - -.....
VIL
I
I
I
j:!(r-O-U-T-P-UT-- VOH
"M
_ _ _ _ _ _ _ _J
-
VIL
- - - - - - VOL
~ Isu ~ Iw ~ 100 ns 10 1000 ns.
VIHH ~ 10.25 V 10 10.75 V.
NOTE 3: Id
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-255
TIBPAL20L8·12M, TlBPAL20R4·12M, TIBPAL20R6·12M, TlBPAL20R8·12M
TlBPAL20L8·10C, TIBPAL20R4·10C, TlBPAL20R6·10C, TIBPAL20R8·10C
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
f max SPECIFICATIONS
f max without feedback. see Figure 1
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no
feedback. Under this condition, the clock period is limited by the sum of the data setup time and the data
hold time (tsu +th). However, the minimum f max is determined by the minimum clock period
(twhigh + twlow).
1
Thus, f max without feedback =
1
or - - - .
(tw high+tw low)
(tsu +th)
CLK
LOGIC
ARRAY
FIGURE 1. f max WITHOUT FEEDBACK
f max with internal feedback. see Figure 2
This configuration is m,Ost popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal
delay from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
Thus, f max with internal feedback =
1
(tsu + tpd ClK-to-FB)
Where tpd ClK-to-FB is the deduced value of the delay from ClK to the input of the logic array.
CLK
LOGIC
ARRAY
Q
~t5U---i+"""- tpd CLK-to-FB ~
FIGURE 2. f max WITH INTERNAL FEEDBACK
2-256
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL2DL8·12M, TIBPAL2DR4·12M, TlBPAL2DR6·12M, TIBPAl20R8·12M
TIBPAL2DL8·1 DC, TIBPAL2DR4·1 DC, TIBPAL2DR6·1 DC, TIBPAl2DR8·1 DC
HIGH·PERFORMANCE IMPACT·X"" PAL® CIRCUITS
f max SPECIFICATIONS
f max with external feedback. see Figure 3
This configuration is a typical state-machine design with feedback signals sent off-chip. This external
feedback could go back to the device inputs or to a second device in a mUlti-chip state machine. The slowest
path defining the period is the sum of the clock-to-output time and the input and setup time for the external
signals (tsu +tpd CLK-to-Q).
Thus. f max with external feedback =
1
(tsu + tpd CLK~to-Q)
ClK
QI----.-....
lOGIC
ARRAY
NEXTOEVICE
FIGURE 3. f max WITH EXTERNAL FEEDBACK
l--
-
10
C1
)--
I("
~
....
t+
1=0
">-
Q
F1
~
l-}--
...
r-J
110
)--
X"
....
-I~
...
FIGURE 4. PROPAGATION DELAY FROM CLKt to I/O. THRU LOGIC ARRAY
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-257
TlBPAL20LB·12M, TIBPAL20R4·12M, TIBPAL20R6·12M, TIBPAL20R8·12M
TIBPAL20LB·1 DC, TlBPAL20R4·1 DC, TIBPAL20R6·1 DC, TIBPAL20RB·1 DC
HIGH·PERFORMANCE IMPACT·xrM PAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
SV
S1
~
R1
FROM OUTPUT _ ...._ . ._ ..._
UNDER TEST
CL
ISee No.e AI
TEST
POINT
R2
LOAD CIRCUIT FOR
THREE-STATE DEVICES
[3.5VI13V)
./.
7,1.SV
---~~ - - - 14-- 'h --.t
I+-'su-+t
1
TIMING
INPUT
-
1. S V
1.SV
- [0.3 VI (0)
1. S V
[0.3 VI (0)
,.----....
.LI 1.S V
tpd
I..
1
:
tpd
-
-
~I
1
- - [3.5 VI 13 V)
f1SV
~I
:+-~
14
~I [3.5 VI 13 V)
LOW-LEVEL
1 SV
1 SV
PULSE··
- - - -
OUT·OF-PHASE
OUTPUT
(See Note 01
ten
VOH
VOL
tpd
VOH
1 . SV
--VOL
WAVEFORM 2
S10PEN
14-
--.f I+-- tdis
-33 V
-.
I 1.S V
",-----VOL +0.5 V
~
1
1 __ -Z._
ten---+!
j+-
- -"I ~ I+-tdis T.
' _____ i-=
~
(See Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
----+I
i i iIIi
WAVEFORM 1
S1 CLOSED
(See Note B)
: r . : : 1
F
[0.3 VI (0)
OUTPUT ~[3.5VI(3V)
CONTROL
1.S V
1.S V
(low-level
I
I
.
i
-1- - - ---[0.3 VI (0)
enablmgl
tpd
,
i i i
14
~
14
~I
[0.3 VI (0)
VOLTAGE WAVEFORMS
PULSE DURATIONS
\1.S V
1 ....- - - - [ 0 . 3 VI (0)
---.I:
IN-PHASE
OUTPUT
-
)
~ 'w-----.J
1
1
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
1.SV
I
DATA~rl---[3.5VI13V)
INPUT
~---[3.5VI13V)
HIGH-LEVEL
PULSE
VOL
VOH
I
1.5 V
LVOH-0.5 V
• 0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is SO pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR oS 10 MHz, tr and tf oS 2 ns, duty cycle ~ 50%_ For M suffix, use
the voltage levels indicated in parentheses ( ). For C suffix, use the voltage levels indicated in brackets [ 1D. When measuring propagation delay times of 3~state outputs, switch S 1 is closed.
E. Equivalent loads may be used for testing.
FIGURE 5
2-258
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20LB· t 2M. TIBPAL20R4· t 2M. TIBPAL20R6·12M. TlBPAL20RB·12M
TIBPAL20LB· t ~C. TlBPAL20R4· t ~C. TlBPAL20R6·1 ~C. TIBPAL20RB· t DC
HIGH·PERFORMANCE IMPACT·XTM PAL® CIRCUITS
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE·AIR TEMPERATURE
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
8
200r-~--~--~--+-~r--+---r~
VI
«
T6
E
I
~
-
7
"
180r-~--~--~--+--
~
~
2l
"6.
a.
u
2
a:
120~-4---r--1---+-~r--+---r--;
-75 -50 -25
0
25
50
75
TA e 25·C
CL = 50 pf
R1 = 2000
R2-3900
1 OUTPUT SWITCHING
100 125
4.5
FIGURE 7
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
I
9
I
,
,
8
..E
jPHL (,I, I/O ,to O~ ....
7
tPLH (I, I/O to 0, I/O)
.
a.
E!
a.
5 -
tfHL (~LK t~ 0)
tpLH (CLK to 0)
2
o
I
14~--1----+----r---1---~~~
,../"
-
--
1---1
4
3
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
16~--'----r----r---'---~---'
,
VI
6
VI
.T
E
i=
-::::
~
25
'il
Q
a:
75
8 r----Y~'_;k~"""""I----'--c-::_:_:_'_--=-1
6
r-.....,..,..+:.~-*--'<--I----+----+--~
to
~
50
10r---~--~~~~~~~~--~
cQ
I
0
12~--1----+----~~~~~--~
>
IV
Vcc - 5 V
CL - 50 pf
R1 - 2000
R2-3900
1 OUTPUT SWITCHING
-75 -50 -25
5.5
VCC-Supply Voltage-V
FIGURE 6
10
5.25
5
4.75
TA-free-Air Temperature-·C
-;to
0)
o
100~~--~--~--~~~~--~~
cQ
tpLH (CLK to
3
Cl
S:?
Q
0)
c
....
g.
I
>
"ii
I.
tPHL (CLK to
4
~
::J
.
to O. I/O)
(I. 1/0
5
.!!!
Ul
i=
tPLH
>
::J
~ 160r-~--~~~~~
c
I
tpHL (I, I/O to O. I/O)
100 125
VCC = 5 V -\--t---~----+----l
TA = 25·C
R1 = 200 0 -+---4---+----1
2
R2 = 3900
o ~__1_0_U_T_PU_T__SW
__IT_C_H_IN_G~____...I.__ __ '
4
o
TA-free-Air Temperature-·C
100
200
300
400
500
600
CL -Load Capacitance-pf
FI~URE
FIGURE 8
9
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75266
2-259
TIBPAL20LB·12M, TlBPAL20R4·12M, TlBPAL20R6·12M, TlBPAL20RB·12M
TIBPAL20LB·10C, TIBPAL20R4·10C, TlBPAL20R6·10C, TIBPAL20R8·1 DC
HIGH·PERFORMANCE IMPACT·XTM PAl® CIRCUITS
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
FREQUENCY
a-BIT COUNTER MODE
1000
VCC 1
==E
I
c
Til. -
i.;;;...
Q
----
OJ C
TA - 25°C
800
TA - 80°C
Gi
~
.., ~
...I
,.,... ~ ~
""
,.,... ~
.....
I
~
0.7
~
0.6
.~
VCC - 5 V
TA - 25°C
R1 - 200 n
R2-390n
CL-50pF
8-Bit Counter
(I)
s
S. a 0.5
.....
::J
~
0
;; 0.4
=cj
! -
0.3
j
0.2
~
0
Do.
Q
Do.
0.8
c
900
I
.!!
r
.
~!
I
SKEW BETWEEN OUTPUTS t
vs
NUMBER OF OUTPUTS SWITCHING
700
(I)
~
0.1
j
600
1
o
100
4
10
40
F-Frequency'-MHz
2
3
4
7
6
5
Number of Outputs Switching
FIGURE 10
FIGURE 11
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
10
9
~
I
tpHL \1, \I
8
otlO,lIbl'1+
~.
I
~
i=
.
>-
6
;!l
c
·8
5
~
~
~
Do.
,_
Oto O,II 01
tPLH \1,1/ I
I
7
!_
tCLK
I
\CLK to Ql
rHL~
4
tPLH
3
2
o
o
70 Q)
Vcc - 5 V
TA - 25°C
CL - 50 pF
R1 - 200 n
R2-390n
2345678
Number of Outputs Switching
FIGURE 12
TEXAS ",
INSTRUMENTS
2-260
POST OFFICE BOX 855303 • DALLAS. TeXAS 75285
8
TIBPAL20LB·20M, TIBPAL20R4·20M, TIBPAL20R6·20M, TlBPAL20RB·20M
TlBPAL20LB·15C, TIBPAL20R4·15C, TIBPAL20R6·15C, TIBPAL20R8·15C
HIGH PERFORMANCE IMPACTTMPAL® CIRCUITS
D2920, JUNE 1986-REVISED AUGUST 1989
TIBPAL20LS'
M SUFFIX .•. JT OR W PACKAGE
C SUFFIX ... JT OR NT PACKAGE
•
High Performance: f max (w/o feedback)
TIBPAL20R' C series, .. 45 MHz
TIBPAL20R' M series ... 41.6 MHz
•
High Performance ... 45 MHz Min
Vcc
•
Functionally Equivalent to, but Faster than,
PAL20L8, PAL20R4, PAL20R6, PAL20R8
o
•
Power·Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•
Preload Capability on Output Registers
Simplifies Testing
•
Package Options Include Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•
Reduced ICC of 180 mA Max
DEVICE
I INPUTS
'PAl20l8
'PAl20R4
'PAl20R6
'PAl20R8
14
12
12
12
3·STATE
o OUTPUTS
2
0
0
0
REGISTERED
o OUTPUTS
0
4 (3·state buffers)
6 (3·state buffers)
8 (3-state buffers)
(TOP VIEW)
I
110
110
110
110
I/O
110
o
TlBPAL20LS'
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
u
1/0
PORTS
6
4
2
u u
___ 2>_0
4
2 1 28 27 26
25
I
0
3
24
6
23
22
NC
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices.
These IMPACT'" circuits combine the latest
Advanced Low-Power Schottky t technology
with proven titanium-tungsten fuses to provide
reliable, high performance substitutes for
conventional
TTL
logic.
Their easy
programmability allows for quick design of
custom functions and typically results in a more
compact circuit board. In addition, chip carriers
are also available for further reduction in board
space.
110
110
21
20
19
11
12131415 16 17 18
--Ou--o
zz
(!)
NC - No internal connection
Pin assignments in operating mode
Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low
state. This feature simplifies testing because the registers can be set to an initial state prior to executing
the test sequence.
The TIBPAL20'M series is characterized for operation over the full military temperature range of - 55°C
to 125°C. The TIBPAL20'C is characterized from OOC to 75°C.
IMPACT is a trademark of Texas Instruments Incorporated
PAL is a registered trademark of Monolithic Memories Inc.
t'ntegrated Schottky-Barrier diode-clamped transistor is patented
by Texas Instruments, U.S. Patent Number 3,463,975.
Copyright © 1989, Texas Instruments Incorporated
PRODUCTION DATA documents contain information
currant 8S of publication data. Products conform to
specifications par the terms of Texas Instruments
=~=~~i~8{::1~1i ~~:\~~ti~n :1~O=~:::t:~~S not
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-261
TIBPAL20R4·20M, TIBPAL20R6·20M, TIBPAL20R8·20M
TlBPAL20R4·15C, TIBPAL20R6·15C, TIBPAL20R8·15C
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
TIBPAL20R4'
M SUFFIX . .. JT OR W PACKAGE
C SUFFIX . .. JT OR NT PACKAGE
TIBPAL20R4'
M SUFFIX . .. FK PACKAGE
C SUFFIX . .. FN PACKAGE
(TOP VIEW)
(TOP VIEW)
ClK
VCC
I
~ u ts a
--uZ>_""
I
liD
liD
4
3 2
Q
Q
Q
I 28 27 26.
25
24
23
22
21
liD
liD
20
19
12 1314 15 16'7 18
G NO '-"''---'''I-' DE
TIBPAl20R6'
M SUFFIX . .. JT OR W PACKAGE
C SUFFIX . .. JT OR NT PACKAGE
TIBPAL20R6'
M SUFFIX . .. FK PACKAGE
C SUFFIX . .. FN PACKAGE
(TOP VIEW)
(TOP VIEW)
ClK
VCC
I
liD
4
Q
Q
Q
liD
I
5
I
I
NC
I
6
7
2 I 28 27 26
3
8
9
I
10
I
II
Q
19
Q
121314 IS 16 17 18
TlBPAl20RS'
M SUFFIX . .. JT OR W PACKAGE
C SUFFIX . .. JT OR NT PACKAGE
TlBPAL20RS'
M SUFFIX . .. FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
(TOP VIEW)
ClK
VCC
I
Q
4
Q
I
I
Q
Q
Q
Q
2
I 28 27 26
24
I
23
NC
I
22
9
21
I'
10
20
I
II
I
G NO
3
5
6
19
12131415 161718
o....o..;.:=---=~ DE
--
~ ~I~
-
a
Cl
NC - No internal connection
Pin assignments in operating mode
2-262
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
TlBPAL20LB·20M, TlBPAL20R4·20M
TlBPAL20LB·15C, TIBPAL20R4·15C
HIGH·PERFORMANCE IMPACrrMPAL® CIRCUITS
functional block diagrams (positive logic)
TlBPAL20LB'
EN ~1
&
40X 64
'
12
0
20
t--t---LL-a
4
4
rv
_1-+-+--- 1/0
0-....
b-'iH_I-+-+---
1/0
b-..,I--oIt+-l---
1/0
b-..-1I--01t+-l---
1/0
denotes fused inputs
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-263
TIBPAL20R6·20M, TIBPAL20R8·20M
TIBPAL20R6·15C, TIBPAL20R8·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
functional block diagrams (positive logic)
T1BPAL20R6 '
Oe------------------------------V
1/0
~
.....
1600
1640
1680
'>------v
1720
1760
117)
1/0
1800
1840
I!l.r-
1880
...
~
1920
1960
2000
116)
2040
.7
2080
2120
I/O
V
2160
19) .....
2200
~
.....
2240
2280
2320
2360
I
I
11 O)~
;r
2400
2440
2480
2520
.....
-;...
11
-J
115)
o
114)
......
(13)
!It
.,J----'-'"
Fuse Number = First Fuse Number + Increment
Pin numbers shown are for JT and NT packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265-
2-265
TIBPAL20R4·20M
TlBPAL20R4·15C
HIGH·PERFORMANCE IMPACpM PAL® CIRCUITS
logic diagram (positive logic)
elK
11
!rv
INCREMENT
/0
1\
4
8
16
12
20
13l(-
28
24 ,
32
...
36
,\
FIR ST
FU SE
IIIU M8ERS 4g
80
120
160
200
240
280
~...
123)
.A
'.J
>-
...
)-
560
600
-J-
640
680
720
760
800
840
880
~
121)
LJ
1-
960
1040
)-
1080
1120
',60
1200
-
1240
1280
117)~
1320
>--
1360
1400
1440
>--
1480
1520
1560
D.A
'"
1600
1640
1680
1720
1760
~
lS00
1840
II~
1880
'0
c,
'.0
'0
...
119)
Q
118)
b-po--
117)
Q
Q
c,
~l
2080
2120
2160
2200
116)
1/0
'I-----'
2240
2280
2320
2360
2400
2440
2480
2520
I
Ill)
D:J
I
115)
'-J-
I
~
use Number == First Fuse Number + Increment
Pin numbers shown are for JT and NT packages
TEXAS ,.,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
110
~14)
I
2-266
,
~
1960
2000
2040
110)~
b-po-
f6i
tJ
f6i
'0
'-J
1920
1 19 )
Q
'0
1000
16)
I 10
v
r- ~~
,
""
1~920
..
I 10
-
320
360
400
440
480
520
I~
~
122)
)-
OE
TIBPAL20R6·20M
TIBPAL20R6·15C
HIGH·PERFORMANCE IMPACpM PAL® CIRCUITS
logic diagram (positive logic)
CLK
I2lt>
"0
I ( 2)-
INCREMENT
,.
4
B
12
16
20
24
2B
32
(3)_
4)_
320
360
400
440
480
520
560
600
....
~l
-
"1/""
r- ~rJ
'"
10
)--I
r-
960
1000
1040
'"
1080
)-
-
""
r-
1560
(J-
1600
1640
1680
1720
1760
1800
1880
~
.....
@J
10
IJ....
(1
'0
IJa.-
(1
C1
~
'"
1920
1960
2000
2040
2120
2160
(1 6)
a.-
10
2080
Q
e,
2200
~
2240
~
2280
2320
2360
2400
2440
11)
~
10
~ IJ
r~
D-
1840
...
(20 )Q
e1
1520
1£!r-
b-v
C1
1360
(~
~
'0
C1
~
1480
....
)Q
..,'J-
640
680
720
760
800
840
880
920
1440
(B)_
1/0
e1
1400
'4..-
1/0
"'"
1280
1320
(7)
(22)
~
1120
1160
1200
1240
(6)
(23)
~
80
120
160
200
240
280
(~-
,
"
FIR 5T
FU SE
0
NU MBER5 40
a.-
36
2480
2520
'"
(15)
1/0
,
(14)
....
,J--I
+
Fu S8 Number = First Fuse Number + Increment
Pin numbers shown are for JT and NT packages
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
OE
2·267
TIBPAL20RIi·20M
TIBPAL20RB·15C
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
logic diagram (positive logic)
c LK
I.!lt>
INCREMENT
"0
4
8
16
12
"
20
24
28
32
(21
'--i..
36
,
-
(231
FIR ST
FU SE
a
NU M8ERS 40
fejrJ ""
(31 ...
80
'20
'60
200
240
280
'>-
(41
320
360
400
440
480
520
560
600
640
680
720
760
800
840
880
920
'>-
.
.""1-
(~
'>- c,
1240
'>-
'>-
1800
(181
10
v
Q
(171
10
v
Q
C1
1840
1880
.A
.....
1920
1960
2000
2040
2080
'>-
2120
10
Q
C1
2160
2200
2240
2280
~
2320
2360
2400
2440
C1
2480
2520
~
Q
.A
,
'"
(14 I
(11~
1- ,...1
'"
Fu se Number = First Fuse ftIIumber + Increment
Pin numbers shown are for JT and NT packages
2·268
Q
'J
1600
1680
1720
1760
-t
iJ
-vo-
(191
10
C1
1640
(101
Q
~
1560
.--'-t
(201
'"
~~~g
1520
(91 ...
IJv
C1
1400
1440
1480
(81
@J
10
~
IJ
-~
'J
~
~6
-~
>-
1360
...
Q
C1
1200
(71
~
(211
V
_~
I
110
4
3 2
1 28 27 26
110
25
110
Q
24
Q
Q
23
Q
Q
22
21
20
NC
19
110
Q
110
110
I
GNO
10
11
I
.......- - ' - > - '
Q
1213 14 15 Hi 1l 18
6E
TIBPAL20RS'
FN PACKAGE
(TOP VIEW)
TIBPAL20RS'
JT OR NT PACKAGE
(TOP VIEW)
CLK
Q
VCC
I
110
4
Q
Q
'2
3
1 28 27 26
5
25
Q
6
24
Q
Q
Q
NC
Q
Q
110
I
GN 0 .......""----'.::1-'
I
Q
NC
21
Q
10
20
Q
11
19
Q
1213 1415 16 1718
6E
TIBPAL20RS'
FN PACKAGE
(TOP VIEW)
TlBPAL20RS'
JT OR NT PACKAGE
(TOP VIEW)
CLK
23
n
I
u t5
__ ::i
uz>_o
Q
4
VCC
3 2
1 28 27 26
Q
25
Q
24
Q
23
Q
Q
I
Q
G N 0 .......=--""":'::1-'
21
I
Q
I
22
NC
20
10
19
11
I
12131415 1617 18
6E
- -
~ ~Io
- a
<:J
NC-No internal connection
Pin assignments in operating mode
2-276
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS, TEXAS 75265
TIBPAL20L8·25C. TIBPAL20R4·25C
LOW·POWER HIGH·PERFORMANCE IMPACpM PAl® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20LS'
EN ;'1
&
0..----0
40X64
0..----0
20X I>
14
1/0
20
P-~-++--I/O
P-..t--++--I/O
b--'+ _ _-I/O
0...-+.......-1/0
h-.-+........-I/O
6
TlBPAL20R4'
-'EN
"0E
1.:Cl
ClK
-g;-40X64
1:
+
8
';;:'1
1-0 '"
10
-f"iO'Xi>
12
-f-
-+-
>-f-
-
Q
~
~
'"V
4
'"V
---.
-l-
-+
Q
~
o
o
...--,.
EN
;'1
'"
-;-i-
1/0
1/0
-:;-i-
1/0
---"7
1/0
-~
4
rv
denotes fused inputs
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2·277
TIBPAL20R6·25C, TIBPAL20RB·25C
LOW·POWER HIGH·PERFORMANCE IMPAC7'TM PAL® CIRCUITS
functional block diagrams (positive logic)
TlBPAL20R6'
~----------------------~fEN---'
CLK ......................................................................~
r'?1'ri:ii'ib-- a
,-;--""""1b-+---a
a
t---t---b---+- a
t---r-"""b---+- a
t--;--""""1b-+-a
...+-1-1/0
J-_..2r-~
D-.....-++-~-- I/O
TIBPAL20RS'
~ ~---------..:..------e(E:N-l
CLK ...............- -..........- - - - - - - - - -.....----~
&
40X64
r;;;--rI-iH71b--a
r---1---b~--a
r---1----b~-a
r----1-----b~--a
r--;--""""1b-:t-a
r----1---1b~--a
r--;--""""1b-:t-a
t--~t---b--+-- a
I"\..J denotes fused inputs
2-278
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIBPAL2DLB·25C
LOW·POWER HIGH·PERFORMANCE IMPACpM PAl@ CIRCUITS
logic diagram (positive logic)
(1 )
INCREMENT
/0
1\
4
8
12
16
20
24
28
32
(2)_
36
,
-
~
FI RST
FU SE
0
NU M8ERS 40
(3)_
80
120
160
200
240
280
(4)_
320
360
400
440
480
520
560
600
(5)_
640
680
720
760
800
840
880
920
...
.4-
~
'-
..-
(21)
~
(20)
I/O
V
"
>j
1200
1240
.0-
I /0
(18)
..-
I/O
1520
1560
q----'
1600
1720
"'"
1760
1800
~
(19)
""
1280
1320
1360
1400
1440
1480
1640
1680
(8) _
I/O
~
"60
(7)_
J
V
",-
1080
1120
...,..
o
--
960
1000
1040
(6)
(22)
..-
1840
1880
(17)
..-
I/O
.;.r---'
1920
1960
2000
2040
2080
2120
(9)_
(16)
.-
2160
2200
~
"
2240
2280
2320
2360
..-
2400
2440
2480
I ( 1~
I/O
2520
A
..-
(15)
o
(14)
"
(13)
..
11 )_
....r------
Pin numbers shown are for JT and NT packages.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-279
TlBPAL20R4·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTM PAL@> CIRCUITS
logic diagram (positive logic)
ClK
(1)
-v
INCREMENT
10
(~
1\
4
S
12
16
20
24
2S
32
FIR ST
FU SE
NU MSERS
..
(3)_
(~
~
..
(~
....
4g
1
80
120
160
200
240
280
(7)_
I
"
1
(21) I
V
>-
-
'"
960
1000
1040
1080
1120
1160
1200
1240
>---
-
1280
1320
1360
)--
;M
~
rJ (20)
C,
~
'"
1600
10
c,
1840
1880
1920
1960
2000
2040
2080
2120
<->
2160
2200
tA.r
9)
o
1.
(1S)
o
r:J....
(17)
V
B
10
~
)--
1aoo
o
....
c,
C,
1520
1560
/0
1
A
'J
640
680
720
760
800
840
880
920
1680
1720
1760
(9)_
....
I /0
~
320
360
400
440
480
520
560
600
1640
(S)_
..
(22)
.. r
1440
1480
I
(23)
'"
1400
I
\
A
....
(6)
36
~
J!
o
(16)
I/O
:r-----
2240
2280
2320
2400
2440
2480
2520
(10)
(15)
:r--J!
2360
;.r--'
(14)
(1..!1.r-
1"
"
Pin numbers shown are for JT and NT packages.
2-280
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
I
~
I/O
TlBPAL20R6·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
logic diagram (positive logic)
eLK
(1)~
....
/
0
(2)_
4
8
12
16
INCREMENT
,.
20
24
28
32
FI RST
FU SE
a
NU MBERS 40
I~
(4) ....
(~
(6)
4-
...
l!lt..
I(~
..
110)_
"123)
t>- ~
80
'20
'60
200
240
280
122)
~
1/0
320
360
400
440
480
520
560
600
>- ~rJ ''''
640
680
120
160
800
840
880
920
>-
960
1000
'040
1080
1120
1160
1200
1240
>-
V
10
Q
C1
..-1.
("'l.
....
'280
1320
'360
1400
1440
>-
1480
1520
I~
36
1560
bv
~b
10
120)
a
C1
~
10
(1
"1.?""
C1
R
~
tJv
(1
J...
(1
b...
(1
C1
~ I---'
,6M
1640
'680
1720
1760
'800
1840
1880
~
"
>~
1920
'960
2000
2040
2080
2120
2160
2200
>-
10
C1
I---'
~
10
C1
"
2240
2280
2320
2360
2400
2440
2480
2520
l
115)
-1
1/0
.~
(14)
(1.!1.r-
.~
>-1
~
Pin numbers shown are "for JT and NT packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
OE
2·281
TIBPAL20R8·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
logic diagram (positive logic)
c lK
I"v
(1)
INCREMENT
"0
.
4
8
16
12
"
20
24
28
32
12) ....
36
,
(23)
....
FIR ST
FU SE
0
NU MBERS 40
80
120
160
200
240
3)" 280
)-
320
360
400
440
480
520
560
600
)-
...
I (
4)
-t.
I (5)"
...
I (6) ....
...
(7)"
(B) ...
~
0)"
fl;4l2'
Q
c,
-J
~
~
10
c,
.;"I
"
640
680
720
760
800
840
880
920
)-
960
.1000
1040
1080
1120
1160
1200
1240
)-
(21
Il...
(20
~
fl] ~
c,
....
"
Il...
Q
Q
Q
c,
~~~g
1360
1400
1440
1480
1520
1560
)-
I.J.
~
I.J.
~
Il...
fl]
10
"1-
"
1600
1640
1680
1720
1760
1800
1840
1880
)-
"1~
)-
Q
(17
Q
v
c,
1920
1960
2000
2040
2080
2120
2160
2200
(18
v
c,
(1 6)
Q
c,
...r
2240
2280
2320
2360
2400
2440
2480
2520
~
I.J.
...
~~
....
.
(15
Q
c,
~
(14)
....
1 )....
-t,
I
~.3)_
OE
Pin numbers shown are for JT and NT packages.
2-282
-
TEXAS.
INSTRUMENTS
POST OFfiCE BOX 656303 • DALLAS. TEXAS 75265
TIBPAL20L8-25C, TIBPAL20R4-25C, TIBPAL20R6-25C, TlBPAL20R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACTTM PAL® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 75°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
5.5
V
2
O.B
-3.2
IOL
Low-level output current
fclock
Clock frequency
tw
Pulse duration. clock
tsu
th
Setup time. input or feedback before ClKi
Hold time, input or feedback after ClKi
TA
Operating free-air temperature
0
I High
I low
V
mA
24
mA
33
MHz
15
ns
15
ns
25
0
ns
0
ns
75
·C
fClock, two tsu. and th do not apply for TlBPAl20lB'.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TeXAS 75265
2-283
TIBPAL20LB-25C, TIBPAL20R4·25C, TIBPAL20R6-25C, TIBPAL20RB-25C
LOW-POWER HIGH-PERFORMANCE IMPACT'M PAL® CIRCUITS
electrical characteristics over recommended free-air operating temperature range
PARAMETER
TEST CONDITIONS
VIK
Vee - 4.75 V,
VOH
Vee
Vee
VOL
0, Q outputs
= 4.75 V,
= 4.75 V,
MIN
11- -18 mA
10H
10l
=
5.25 V,
Vo
=
Vee
=
5.25 V,
Vo
= 0.4
II
Vee
Vee
5.25 V,
III ~
Vee
10S§
=
=
=
=
5.25 V,
IIH~
Vee
5.25 V,
Vee - 5.25 V,
VI - 0,
Outputs open,
OE at VIH
10Zl
I/O ports
0, Q outputs
I/O ports
lee
5.25 V,
-0.8
= -3.2 mA
= 24 mA
Vee
10ZH
TYpt
2.4
MAX
-1.5
V
V
3.3
0.3
0.5
20
2.7 V
UNIT
V
pA
100
-20
-0.25
mA
VI
0.1
mA
VI
20
~A
-0.2
mA
-70
-130
mA
75
105
mA
V
= 5.5 V
= 2.7 V
VI = 0.4 V
Vo = 0
-30
~A
t All typical values are at Vee = 5 V, TA = 25°e.
~ For I/O ports, the parameters IIH and III include the off-state output current.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed 1 second.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
FROM
f max '
with feedback
without feedback
TO
TEST CONDITIONS
Typt
25
40
33
50
3
14
10
25
15
ns
ns
MAX
UNIT
MHz
I, I/O
elKt
0,1/0
Q
Rl
ten
OE
Q
el
2
8
15
ns
tdis
ten
OEt
Q
2
8
15
ns
I, I/O
0, I/O
15
25
ns
tdis
I, I/O
0, I/O
3
3
15
25
ns
ted
ted
tAli typical values are at Vee
'f max (with 'feedback)
=
=
5 V, TA
=
=
=
=
200 0,
R2
390O,
50 pF,
See Figure 1
25°e.
1
, f max (without feedbackl
tsu + tpd (elK to Q)
= _-,-,--:c-'_--:-_
tw high + tw low
f max does not apply for TIBPAl20l8'
2-284
MIN
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2
TlBPAl20L8·25C, TIBPAL20R4·25C, TIBPAL20R6·25C, TIBPAL20R8·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware. software. and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available. upon request. from the nearest TI field sales office. local
authorized TI distributor. or by calling Texas Instruments at (2141 997·5666.
PARAMETER MEASUREMENT INFORMATION
SV
Sl
b
Rl
FROM OUTPUT_. ._ ...._ ..._
UNOER TEST
CL
(S •• Note A)
TEST
POINT
R2
L - - _......
LOAO CIRCUIT FOR
THREE-5TATE OUTPUTS
TIMING
INPUT
./.
/,l.SV
3.S V
HIGH-LEVEL
PULSE
~
1.5 V
1.5V
----3.SV
: _ _ tw
_
- - - - " : - - - - - - - - 0.3 V
,..tsu ~ th ~
'
DATA
INPUT
' loS V
' 1.5 V
.
~
0.3 V
-'----3SV
LOW-LEVEL
PULSE
:e--
OUTPUT
CONTROL
OUT -OF-PHASE
OUTPUT
\1.5V
(See Note D)
VOL TAGE WAVEFORMS
PROPAGATION DELAY TIMES
3.5 V
~
1.SV
(low-Ie.el
enabling)
t
tpHL~
tw - :
VOLTAGE WAVEFORMS
PULSE DURATIONS
INPUT -.11.5 V
I
O.3V
~
~l.SV · · l . S V . v ~---0.3V
VOL TAGE WAVEFORMS
SETUP AND HOLD TIMES
tPLH~
IN-PHASE
t
/'1 S
OUTPUT
I
•
. V
:
tpZL
-..lI
I
WAVEFORM 2
51 OPEN
(See Not. B)
~
I
0.3 V
-:- - - - - - - -
II-
-.. II- tpLZ
I I
I It:
WAVEFORM 1
Sl CLOSED
(See Not. B)
3.SV
1.5V
1.5 V
=3.3 V
i :~S
~-=--=----"-;=-=
tPZH ~
...:
r--- tPHZ
~
I
1.5 V
V
VOL
-----t--v
- -- --.-O.S V
OH
"'0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS
NOTES: A. Cl includes probe and jig capacitance and is SO pF for tpd and ten. 5 pF for tdis'
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR :s 1 MHz, tr = tf = 2 ns. duty cycle = SO%.
D. When measuring propagation delay times of 3-5tate outputs, switch Sl is closed.
FIGURE 1
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-285
TIBPAL20L8·25C,TIBPAL20R4·25C, TIBPAL20R6·25C, TIBPAL20R8·25C
LOW·POWER HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
preload procedure for registered outputs (see Note 2)
The output registers of the TIBPAL20R' can be preloaded to any desired state during device testing. This
permits any state to be tested without having to step through the entire state-machine sequence. Each
register is preloaded individually by following the steps given below.
Step
Step
Step
Step
1.
2.
3.
4.
With Vee at 5 V and pin 1 at VIL, raise pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1, clocking in preload data.
Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage
level at the output pin.
preload waveforms (see Notes 2 and 3)
PIN 13 _ _ _
~/ ~'"~
I4-td~
I
PIN 1
~~~
j.-tw--.j
I
-
I I
-1- T - - - - -
VIH
---+-l--i-:_. .11...---:I--~:I---~--VIL
1
I
REGISTERED 1/0
r\----:,~'
I
----iM"'___
IN_PU_T_ _ _
1
I
I
I
J8,.-0-U-T-PU-T--::~
NOTES: 2. Pin numbers shown are for JT and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td = tsu = tw = 100 ns to 1000 ns.
VIHH = 10.25 V to 10.75 V.
2-286
.
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TlBPAL20L8·15CNL, TIBPAL20R4·15CNL, TlBPAL20R6·15CNL, TIBPAL20RB·15CNL
TlBPAL20L8·25CNL, TlBPAL20R4·25CNL, TIBPAL20R6·25CNL, TlBPAL2DRB·25CNL
HIGH·PERFORMANCE IMPACP'PAl® CIRCUITS
03095, JANUARY '9BB-REVISED AUGUST '9B9
•
•
•
TIBPAL20LB' ... FN PACKAGE
High Performance: fmax(w/o feedback)
TIBPAL20R' ·15 Series, , ,45 MHz
TIBPAL20R' ·25 Series. , . 33 MHz
(TOP VIEW)
u
U
____ >_0
·15CNL Devices are Direct Replacements
for MMI PAL20L8BCNL. PAL20R4BCNL.
PAL20R6BCNL. and PAL20R8BCNL
4 3 2 1 282726
NC
25
I
2.
I
23
NC
·25CNL Devices are Direct Replacements
for MMI PAL20L8B·2CNL. PAL20R4B·2CNL.
PAL20R6B·2CNL. and PAL20R8B·2CNL
22
I
I
9
10
NC
l'
21
20
19
12131415161718
•
•
Power·up Clear on Registered Devices (All
Registered Outputs are Set Low. but
Voltage Levels at the Output Pins Go High)
- - - 0 -,.- 0
z
~:
Preload Capability on Output Registers
Simplifies Testing
DEVICE
I INPUTS
3-STATE
a
OUTPUTS
REGiSTERED
1/0
a OUTPUTS
PORTS
,4
2
'PAL20R4
,2
0
4 (3-state buffers!
4
'PAL20R6
,2
0
6 (3-state buffers!
2 '
'2
0
0
6
f;;(
I:J:-
8 (3-state buffers)
NC
5
I
6
a
NC 8
22
a
I
21
20
19
1/0
NC
9
I
10
NC
11
a
g13~,15'6'718
?
ordering information
25 I/O
24
23( a
I 7
'PAL20LB
'PAL20RB
'
TIBPAL20fl4", .. FN PACKAGE
,,",'(TOP VIEW)
Devices with the MMI chip-carr,ietpjn-out shown
here may be ordered by usin~fttle Indicated part
number with the NL suffix. '00 nat include the
package suffix (FN).
•
TlBPAL20RS' ... FN PACKAGE
(TOP VIEW)
~ u
u
0
___ "u>_::::
4 3 2 1 282726
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices.
These IMPACTN circuits combine the latest
Advanced Low-Power Schottkyt technology
with proven titanium-tungsten fuses ta provide
reliable. high-performance substitutes for
conventional
TTL
logic.
Their
easy
programmability allows for quick design of
custom functions and typically results in a more
compact circuit board. In addition. chip carriers
are also available for further reduction in board
space.
NC
5
25~ Q
I
I
NC
6
7
8
2~~ Q
:Q~o
NC
not
TEXAS
19[ NC
TIBPAL20RS' ... FN PACKAGE
(TOP VIEW)
"~ u
___ 0 > _ 0
4 3 2
NC
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.
tlntegrated Schottky·Barrier diode-clamped transistor is patented
by Texas Instruments, U.S. Patent Number 3.463,975.
:':~::i~ai~:I-:li ~:~:~i:r lI~o;:~:::,,~~~s
Q
12131415161718
I
I
5
6
7
NC
8
I
specifications per the terms of Texas Instruments
Q
~~~~
11
I
NC
PRODUCTION DATA documants cantai. infurmatio.
currant IS of publication data. Products conform to
2~~
2~~
24
23
22
21
9
10
11
19
12131415161718
---cw-o
zO
'"
NC-No internal connection
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright @ 1989, Texas Instruments Incorporated
2-287
TIBPAL20L8·15CNL, TIBPAL20R4·15CNL
TlBPAL20L8·25CNL, TIBPAL20R4·25CNL
HIGH·PERFORMANCE IMPACTTMPAL@ CIRCUITS
description (continued)
Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low
state. This feature simplifies testing because the registers can be set to an initial state prior to executing
the test sequence.
The TIBPAL20' CNL series is characterized from 0 ac to 75 ac.
4
"-' denotes fused inputs
2-288
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
TIBPAL20R6·15CNL, TlBPAL20RB·15CNL
TIBPAL20R6·25CNL, TIBPAL20RB·25CNL
HIGH·PERFORMANCE IMPACTTMPAL® CIRCUITS
functional block diagrams (positive logic)
TIBPAL20R6'
ae------------------------~~--I
CLK----------------------------~
r;;;--r-i7o'"'tb---
Q
r---.----1b-+--o
r--t---b.-l-- a
r--t---b--l-- a
r---.----1~:t_o
r--t---b--l-- a
P-4d-....+-l-
1/0
6
TlBPAL20R8'
ae-------------------------dE:;;----,
CLK----------------------------~
&
40 X 64
r---r----1b-+--o
r---r----1b-+--o
r----t--'b--+- a
r---r----1b-+--o
t---r----1b-:t_o
r---r----1~+--Q
r---r-~t>-:+--o
.8
" " denotes fused inputs
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·289
TIBPAL20LB·15CNL, TIBPAL20LB·25CNL
HIGH·PERFORMANCE IMPACT'M PAL® CIRCUITS
logic diagram (positive logic)
11 )
INCREMENT
10
4
8
12
16
II
20
24
28
32
(2) ....
v
(6)
I.-
~
'"
FU SE
0
NU MBERS 40
(4)"
\
-1---
FI RST
(3 )"
36
e>-J
80
120
160
200
240
280
(26)
o
.A
320
360
400
440
480
520
560
600
:r-J
(25)
1/0
~
'"
640
680
720
760
800
840
880
920
(24)
110
:J
'"
960
1000
1040
(23)
1080
.....
1120
1160
I 10
1200
(7)
1240
I.-
1280
4------>
1320
1360
(22)
1400
1440
1480
1520
(9) ....
v
:J
1560
1600
1640
1680
1720
::r
1760
1800
1840
1880
11 0)
I
....,"
12)"
I.-
'"
1920
1960
2000
2040
2080
2120
2160
2200
I
J
(20)
...I
(18)
110
v
2440
2480
2520
-
v
(17)
~
"'"
I 14)"
2-290
110
2240
2400
11 3)
(21)
V
2280
2320
2360
I
1/0
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
o
TIBPAL20R4·15CNL, TIBPAL20R4·25CNL
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
logic diagram (positive logic)
elK
(1)
I"....
INCREMENT
10
.
(~
1\
4
8
12
16
20
24
28
32
\
36
(27)
~
......
FIRST
FU SE
NU M8ERS 4g
(3) ..
-
]
80
120
160
200
240
280
110
r
V
~
(4) ....
320
360
400
440
480
520
560
600
(6)
640
680
720
760
800
840
880
920
1
(7) ....
(9) ...
1280
1320
1360
1400
1440
1480
1520
1560
\-)-
121
1920
1960
2000
2040
2080
2120
2160
2200
Q
1......
-Dj
'1
-~
1V""
)-
10
(23 )Q
V
c,
......
)-
10
(22 )Q
c,
......
1680
1720
1760
10)
~~l
c,
1600
1640
1800
1840
1880
1/0
<} - - '
1120
1160
1200
1240
(25)
.. 1
960
1000
1040
1080
v
(26)
~-
)--
f1j
10
c,
~)
V
Q
~
r-J
(20)
~
(18)
1/0
~
2240
2280
2320
2360
2400
2440
f
2480
13) .... 2520
~~
1/0
......
(17)
I ( 14)"
-t,.
I
1- I
......
6)-
~'
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
DE
2-291
TIBPAL20R6·15CNL, TlBPAL20R6·25CNL
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
logic diagram (positive logic)
elK
,-y
(11
INCREMENT
/
"
0
4
8
12
16
20
24
28
32
(~
36
,
(27)
A
"
FI RST
FU SE
0
NU M8ERS 40
(31~
80
'20
160
200
240
280
4)_
320
360
400
440
480
520
560
600
>-
(6)_
640
680
720
760
800
840
880
920
960
"
...
...
>- ~rJ ""
ID
"1- ~
"
1-
>-
1080
1120
1160
1200
1240
"
1280
1320
1360
1400
1520
1560
"
1600
1640
1680
1720
1760
1800
10)
-t
L>-
1840
1880
.....
1920
1960
2040
2080
2120
~i
ID
(2
Y
Cl
~
IR IJ....
~
(2 2)0
(2 1) 0
,
~
IJ....
(20)
2200
~~
'>
2440
2480
2520
~j
(181
1/0
....r---'
(17)
(1~
....
"
2-292
o
Cl
2160
2240
2280
2320
2360
2400
(13)_
~b
~
(2410
'"
Cl
>-~
2000
121
-i
b
10
>- R IJv
1440
1480
...
o
V
Cl
1040
(91
110
.....
loaD
(71_
(26)
b- Wj
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
I
+
TIBPAL20R8·15CNL, TlBPAL20R8·25CNL
HIGH·PERFORMANCE IMPACT™ PAL® CIRCUITS
logic diagram (positive logic)
c LK
(1 )
v
INCREMENT
"0
4
8
12
16
"
20
24
28
32
~
FIR ST
FU SE
0
NU MBERS 40
80
120
160
200
240
(3) "- 280
~
4)
320
360
400
440
480
520
560
600
(6) .....
640
680
720
760
800
840
880
920
-;..
~
>A
"
I
I..-
a
1](24
10
c,
vo--
Q
I] (23
V
Q
....
"
)--
Q(22
10
c,
1.?'>"
Q
.A
(21
10
c,
1.?'>"
Q
1-
"
1920
1960
(20
1.?'>"
10
2120
2160
2200
a
c,
2240
2280
2320
2360
2400
2440
2480
2520
~
~
1.
>~
1.
>El]
JJ.18
>El]
20ao
12) .....
'"
A
1240
( 10)
10
"
mg
1600
1640
1680
1720
1760
1800
1840
1880
~
>-
1Z00
-;..
V
.r - - '
1080
1120
1160
(9)
(27)
....
10
960
1360
1400
1440
1480
1520
1560
"-
>- D]~
c,
1000
1040
(7)
-1
36
1-
-~
"
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
t-I
~I
2-293
TIBPAL20L8-15CNL, TIBPAL20R4-15CNL, TIBPAL20R6-15CNL, TIBPAL20R8-15CNL
TIBPAL20L8-25CNL, TlBPAL20R4-25CNL, TIBPAL20R6-25CNL, TIBPAL20R8-25CNL
HIGH-PERFORMANCE IMPACpM PAl®CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disable output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 75°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
-26CNL
VCC
VIH
VIL
IOH
IOl
fclock
MIN
4.75
2
Supply voltage
High-level input voltage
low-level input voltage
High-level output current
Low-level output current
Clock frequency
0
15
15
25
I High
I Low
tw
Pulse duration, clock
tsu
th
TA
Setup time. input or feedback before ClK t
Hold time. input or feedback after ClK t
Operating free-air temperature
NOM
5
0
0
tfclock, t w , tsu, and th do not apply for TIBPAl20lB'.
2-294
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 ". DALLAS. TeXAS 75265
-16CNL
MAX
5.25
5.5
O.B
-3.2
24
33
MIN
4.75
2
0
10
12
15
0
76
NOM
5
0
MAX
5.25
5.5
O.B
-3.2
24
45
10
75
UNIT
V
V
V
mA
mA
MHz
ns
ns
ns
ns
·C
TIBPAL20L8·15CNL. TlBPAL20R4·15CNL
TIBPAL20R6·15CNL. TIBPAL20R8·15CNL
HIGH·PERFORMANCE IMPACTTM PAl® CIRCUITS
electrical characteristics over recommended free-air operating temperature range
PARAMETER
TEST CONDITIONS
MIN
VIK
Vee = 4.75 V,
11= -18 mA
VOH
Vee = 4.75 V,
10H = -3.2 mA
Vee = 4.75 V,
10l - 24 mA
VOL
D.
10ZH
10Zl
Q
outputs
Vee = 5.25 V,
I/O ports
0, Q outputs
Vee = 5.25 V,
1/0 ports
-15CNL
Typt
MAX
-0.8
-1.5
2.4
UNIT
V
V
0.3
0.5
20
Vo = 2.7 V
100
Vo = 0.4 V
V
~A
-20
-0.25
mA
mA
~A
II
Vee = 5.25 V,
VI = 5.5 V
0.1
IIH~
Vee = 5.25 V,
VI=2.7V
25
~A
III ~
Vee = 5.25 V.
VI = 0.4 V
-0.25
mA
Vee = 5.25 V,
Vo = 0
VI = 0,
-70
-130
mA
Vee = 5.25 V,
Outputs open,
OE at VIH
120
180
mA
lOS!
lee
-30
t All typical values are at Vee = 5 V, TA = 25°e.
:I: For 110 ports, the parameters I'H and I,L include the off-state output current.
§
Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed 1 second.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
FROM
f max '
Without feedback
TO
TEST CONDITIONS
With feedback
MIN
37
45
-15CNL
Typt
MAX
40
UNIT
MHz
50
12
15
ns
R2 = 390O,
8
12
ns
See Figure 1
10
15
ns
12
ns
0,1/0
8
12
18
ns
0,1/0
12
15
ns
lru!
1,1/0
0,1/0
tpd
elKt
Q
Rl = 200O,
ten
llE
Q
el = 50 pF,
tdis
ten
llEt
1,1/0
Q
tdis
1,1/0
tAli typical values are at Vee = 5 V, TA = 25°e.
'f max (with feedback) =
1
, f max (without feedbackl =
1
tsu + tpd (elK to Q)
tw high + tw low
f max does not apply for TIBPAl20l8'
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-295
TIBPAL20L8·25CNL, TlBPAL20R4·25CNL
TIBPAL20R6·25CNL, TIBPAL20RB·25CNL
HIGH·PERFORMANCE IMPACpM PAl® CIRCUITS
electrical characteristics over recommended free·air operating temperature range
PARAMETER
TEST CONDITIONS
Vee = 4.75 V,
Vee - 4.75 V,
Vee = 4.75 V,
VIK
VOH
VOL
10ZH
0, Q outputs
11= -lB rnA
10H - -3.2 rnA
.10l - 24 rnA
Vee = 5.26 V,
Vo = 2.7 V
Vee = 5.25 V,
Vo = 0.4 V
2.4
-25CNl
TypT MAX
-0.8 -1.5
3.3
0.3
0.5
20
UNIT
V
V
V
pA
II
Vee - 5.25 V,
VI - 5.5 V
100
-20
-0.25
0.1
IIH*
Vee = 5.25 V,
VI = 2.7 V
20
pA
III *
Vee = 5.25 V,
VI = 0.4 V
-0.2
rnA
10S§
Vee = 5.25 V,
Vee = 5.25 V,
Outputs open,
Vo = 0
VI = 0,
OE at VIH
-70
-130
rnA
75
105
rnA
10Zl
1/0 ports
MIN
0, Q outputs
I/O ports
lee
-30
pA
rnA
rnA
t All typical values are at Vee = 5 V, T A = 25 ·e.
* For I/O ports, the parameters IIH and III include the off-state output current ..
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed 1 second.
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
-25CNl
TypT MAX
40
50
33
14
25
3
2
10
15
PARAMETER
FROM
f max '
With feedback
Without feedback
1,1/0
0, I/O
elKt
Q
Rl = 200 Il,
R2 = 390 Il,
ten
DE
Q
el = 50 pF,
See Figure 1
2
B
15
ns
tdis
ten
tdis
DEt
1,1/0
1,1/0
Q
2
0,1/0
0,1/0
3
3
B
15
15
15
25
25
ns
ns
ns
ted
ted
t All typical values are at Vee
'fmax (with feedback) =
lou
=
TO
TEST CONDITIONS
5 V, T A = 25 ·e.
1
+ tpd (elK to
Q)
, f max (without feedback) =
-:-"77"-:-'-:--:-tw high + tw low
f max does not apply for TIBPAl20lB'.
2-296
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
25
UNIT
MHz
ns
ns
TIBPAl20LB·15CNL. TlBPAL20R4·15CNL. TIBPAL20R6·15CNL. TIBPAL20R8·15CNL
TIBPAl20LB·25CNL. TlBPAL20R4·25CNL. TIBPAL20R6·25CNL. TIBPAL20R8·25CNL
HIGH·PERFORMANCE IMPACTTM PAL® CIRCUITS
preload procedure for registered outputs (see Note 2)
The output registers of the TIBPAL20R' can be preloaded to any desired state during device testing. This
permits any state to be tested without having to step through the entire state-machine sequence. Each
register is preloaded individually by following the steps given below.
Step
Step
Step
Step
1.
2.
3.
4.
With Vee at 5 V and pin 1 at VIL, raise pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1, clocking in preload data.
Remove output voltage, then-lower pin 13 to VIL. Preload can be verified by observing the voltage
level at the output pin.
preload waveforms (see Notes 2 and 3)
PIN 13
PIN 1
REGISTERED 1/0
NOTES:
2. Pin numbers shown are for JT and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td = tsu = tw = 100 ns to 1000 ns.
VIHH = 10.25 V to 10.75 V.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-297
TlBPAL20LB·15CNL, TIBPAL20R4·15CNL, TIBPAL20R6·15CNL, TIBPAL20R8·15CNL
TIBPAL20LB·25CNL, TIBPAL20R4·25CNL, TlBPAL20R6·25CNL, TIBPAL20R8·25CNL
HIGH·PERFORMANCE IMPACpM PAL® CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
PARAMETER MEASUREMENT INFORMATION
sv
Sl
b
Rl
FROM OUTPUT_..._ ...~,..._ TEST
UNDER TEST
POINT
R2
LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
TIMING
INPUT
./.
3.S V
HIGH.LEVEL
/fl.5V
- - - - ' :- - - - - - --0.3 V
~ tsu ..,.- th --:
PULSE
lilt-- tw
.
1.5V
1.5V
~
-,----3.5V
DATA
INPUT
~---3.5V.
----""'T 1.5V
LOW·LEVEL
PULSE
0.3 V
.. tw-:
~
I
IN·PHASE
OUTPUT
1 :
+-----+t
I
I·
15V
.
l:t-I
tpHL
OUT -OF-PHASE
OUTPUT
~
VOL
!I:"':":" VOH
T
l .5V
- VOL
VOL TAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
I
tPZL ......
I
Sl CLOSED
lSee Note B}
3.5V
1.5 V
- : - - - - - - - - O.3V
Ie--
.... It--tpLZ
I
I I
I I
I :
WAVEFORM1~1.5V
~3 3 V
i:~5V'
~-------:.!=:: VOL
tpZH ~
...: ~tPH~ T
i
WAVEFORM2~:
-_-_-_c:.{.::=
VOH
Sl OPEN
ISee Note B I
"'0 V
1.5 V
O.S V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE·STATE OUTPUTS
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output'with internal conditions such that the output is low except when disabled by the output control.
Wavefo~m 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR !5 1 MHz, tr == tf == 2 ns, duty cycle == 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
FIGURE 1
2-298
3.SV
1.5 V
_ _ _ _ 0.3V
~
(low-level
enabling)
VOH
~tpLH
\1.5V
lSee Note D}
NOTES;
OUTPUT
CONTROL
0.3 V
~tPHL
tPLH~
V
VOLTAGE WAVEFORMS
PULSE DURATIONS
\~~--3.5V
) •
15
. V
I
VOL TAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT J 1 . 5 V
1.5V~0.3
------e.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 •. DALLAS. TEXAS 75265
TIBPAL22V1 DAM, TlBPAL22V1 DC, TIBPAL22V10AC
HIGH-PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
02943. OCTOBER 1986-REVISED AUGUST 1989
•
Second Generation PAL Architecture
•
Choice of Operating Speeds
TIBPAL22V10AC ... 25 ns Max
TIBPAL22V10AM ... 30 ns Max
TIBPAL22V10C ... 35 ns Max
M SUFFIX ... JT PACKAGE
C SUFFIX ... NT PACKAGE
(TOP VIEW)
ClK/)
•
Increased Logic Power and 10 Outputs
•
Increased Product Terms - Average of 12
per Output
•
Variable Product Term Distribution Allows
More Complex Functions to be Implemented
•
Each Output is User Programmable for
Registered or Combinatorial Operation.
Polarity. and Output Enable Control
Up to 22 Inputs
1
GNO
TTL-Level Preload for Improved Testability
•
Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
•
Fast Programming. High Programming Yield.
and Unsurpassed Reliability Ensured Using
Ti-W Fuses
•
Y.;.;=---...:.::J....
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
•
•
VCC
)/0/0
1/0/0
1/0/0
1/010
110/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
(TOP VIEW)
uO 0
~ u u(5 (5
__ uz>:::,:::,
4
AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features
Dependable Texas Instruments Quality and
Reliability
3
2 1 28 27 26
25
5
6
24
7
23
8
9
21
10
20
22
19
11
•
•
Package Options Include Plastic and
Ceramic Dual-In-Line Packages and Chip
Carriers
1/0/0
1/0/0
1/0/0
NC
1/0/0
1/0/0
1/010
12 13 14 15 16 17 18
--ou-OO
zz
-(!l
Functionally Equivalent to AMOs
AMPAL22V10 and AMPAL22V10A
~~
NC - No internal connection '.
Pin assignments in operating mode
description
The TIBPAL22V10 and TIPPAL22V10A are programmable array logic devices featuring high speed and
functional equivalency when compared to presently available devices. They are implemented with the
familiar sum-of· products (AND-OR) logic structure featuring the new concept "Programmable Output LogiC
Macrocell". These IMPACT'" circuits combine the latest Advanced Low-Power Schottky technology with
proven titanium-tungsten fuses to provide reliable high-performance substitutes for conventional TTL logic.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining
and programming the architecture of each output on an individual basis. Outputs may be registered or
nonregistered and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential
outputs are enabled through the use of individual product terms.
IMPACT is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA dooumonts oontain information
currant I. of publication data. Products conform to
specifications per the terms of Tlxas Instruments.
::~~:~~i;8i~:I~J~ ~!s~~~ti:: :'ID:=::~:~~ not
Copyright © 1989, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-299
TIBPAL22Vl DAM. TIBPAL22Vl ~C. TIBPAL22Vl0AC
HIGIl·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each outputfor an average of 12 product terms per output.
This variable allocation of terms allows far more complex functions to be implemented than in previously
available devices.
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term.
These functions are common to all registers. When the synchronous set product term is a logic 1, the
output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous
reset product term is a logic 1, the output registers are loaded with a logic O. The output logic level after
set or reset depends on the polarity selected during programming. Output registers can be preloaded to
any desired state during testing. Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22V10 and TIBPAL22V10A offer quick design and development of custom LSI functions with
complexities of 500 to 800 equivalent gates. Since each of the ten output pins may be individually configured
as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output
or down to 12 inputs and 10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power
is applied to the device. Registered outputs selected as active-low power-up with their outputs high.
Registered outputs selected as active-high power-up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns.
Once blown, the verification circuitry is disabled and all other fuses will appear to be open.
The M suffix devices are characterized for operation over the full military temperature range of - 55
to 125
The C suffix devices are characterized for operation from 0
to 75
ac.
2-300
ac
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
ac.
ac
TlBPAL22Vl DAM, TIBPAL22Vl DC, TIBPAL22Vl0AC
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
logic diagram (positive logic)
0
FUSE
4
,
12
16
20
24
2B
32
3.
40
ASYNCHRONOUS RESET
ITO ALL REGISTERS)
0
396
IP
[1r'
CELL
P = 5808
~
440
.
880
2
--_.
=8=l
MACRO
CELL
2
-:r
-tr
-IT
p .. 5810
~
924
3
MACRO
CELL
1452
3
-IT
R .. 5809
2
p .. 5912
-vb- __
~
1496
==k-
!J
2112
4
MACRO
CELL
2
p .. 5814
~
~
2156
MACRO
D-2860
5
---l>!;::
2904
=--'d
V-
14
i-- i>
h
16
"""" V-
16
"""" V-
I-- >
h
..u..-
~ rv
1~
...- I-- ~
h
14
L.-
....
h
12
t----.
>
"""" r -
12
V-
~
~
"'-1-- I>
V-
10
"'-f-- I>
h
V-
B
'-I-- I>
h
Ir"
C>
h
r-
EN
~I1010
h
~
EN
p.... 1-++-11010
--...
.... EN
h
~
h
.- EN
h
.- EN
h
"""" EN
h
.... EN
h
~
EN
p-.-. f--1/0/0
h
.... EN
~ f++- 1/0/0
p.... 1-++-11010
EN
rv denotes fused inputs
2·302
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
......
CHI;
......
~
......11010
1/0/0
1/0/0
~ f-- 1/0/0
~ I-++-1/0/0
10
10
CHI;
10
TlBPAL22V1 DAM, TIBPAL22V1 DC, TIBPAL22V1DAC
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
output logic macrocell diagram
r-------OUTPUT LOGIC MACROCELL
I ~--------~--~3
I
AR
R
MUX
2
1-0
'}---t......- - - 1 1 D
,.....!.----t> C1
55
b----4.....- - ; 0
1}
0
GO
3
15
L..-_
_....
FROM CLOCK BUFFER
MUX
51
I
AR _ asynchronous reset
~-
:::hr:::
S8_t_
TEXAS •
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS. TEXAS 75265
I
I
I
I
J
2-303
TIBPAL22V1 DAM, TlBPAL22V1 DC, TIBPAL22V10AC
HIGH·PERFORMANCE IMPACT™ PROGRAMMABLE ARRAY LOGIC
S1 - 0
so - 0
S1 - 0
so - 1
REGISTER FEEDBACK. REGISTERED. ACTIVE-LOW OUTPUT
REGISTER FEEDBACK. REGISTERED. ACTIVE-HIGH OUTPUT
S1 - 1
SO - 0
S1 - 1
SO - 1
110 FEEDBACK. COMBINATIONAL. ACTIVE-LOW OUTPUT
110 FEEDBACK. COMBINATIONAL. ACTIVE-HIGH OUTPUT
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
FUSE SELECT
FEEDBACK AND OUTPUT CONFIGURATION
S1
SO
0
0
0
Register feedback Registered
1
Register feedback Registered
1
0
1/0 feedback
Combinational
Active low
1
1
110 feedback
Combinational
Active high
Active low
Active high
o = unblown fuse.
1 = blown fuse
51 and SO are selectwfunction fuses as shown in the output logic
macrocell diagram.
FIGURE 1. RESULTANT MACROCELL FEEDBACK AND OUTPUT LOGIC AFTER PROGRAMMING
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1) ____ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) ............................... _ .. 5.5 V
Operating free-air temperature range: M suffix .......................... , - 55 °e to 125°e
e suffix .............................. ooe to 75°e
Storage temperature range ............ _ . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65 °e to 150 0 e
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a pre-load cycle.
2-304
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL22V1 DAM
HIGH-PERFORMANCE IMPACT"" PROGRAMMABLE ARRAY LOGIC
recommended operating conditions
TIBPAL22V10AM
Vee
Supply voltage
VIH
V,l
High-level input voltage
10H
High-level output current
MIN
NOM
MAX
4.5
5
5.5
2
UNIT
V
V
5.5
Low-level input voltage
0.8
-2
V
10l
Low-level output current
12
mA
mA
fclock
elock frequency
22
MHz
tw
Pulse duration
Setup time before clockt
tsu
Clock high or low
20
Asynchronous Reset high or low
30
Input
25
Feedback
Synchronous Set
Asynchronous Reset low (inactive)
25
25
ns
30
Hold time, input, set, or feedback after clockt
th
TA
ns
ns
0
-65
Operating free-air temperature
125
°e
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VCC = 4.5 V,
VOH
Vec = 4.5 V,
" =
10H = -2 mA
VOL
Vee = 4.5 V,
IOl=12mA
10ZH
Vee = 5.5 V,
Vo = 2.7V
Vee = 5.5 V,
Vo = 0.4 V
I Any output
I
Any I/O
MIN
TVP*
-18 mA
V,K
10Zl
TIBPAL22V10AM
TEST CONDITIONS
MAX
UNIT
-1.2
2.4
V
3.5
0.25
V
0.5
V
0.1
-100
mA
pA
-250
I,
Vec = 5.5 V,
V, = 5.5 V
1
mA
'IH
I,l
10S§
VCC = 5.5 V,
V, = 2.7 V
Vec = 5.5 V,
V, = 0.4 V
25
-0.25
mA
Vee = 5.5 V,
Vee = 5.5 V,
Vo = 0.5 V
V, = GND,
Outputs open
lee
-30
120
pA
-90
mA
180
mA
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
FROM
TO
fmax t
With feedback
I, I/O
I/O
tpd
I, I/O Iresetl
Q
tpd
Clock
Q
ten
I, I/O
Q
tdis
I, I/O
Q
tsu
TIBPAl22V1 DAM
MIN
+
R1 = 390O,
R2 = 750O,
See Figure 2
UNIT
TVP*
MAX
15
30
ns
15
35
ns
10
20
ns
15
30
ns
15
30
ns
MHz
22
tpd
tfmax and fclock Iwith feedback} =
TEST CONDITIONS
, f max and fclock without feedback can be calculated as f max and
tpd lelK to Q}
fclock Iwithout feedback} = _ _--:.1_ __
tw high + tw low
tAli typical values are at Vce = 5 V, TA = 25°e.
§Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set
0.5 V to avoid test problems caused by test equipment ground degradation.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DAl.LAS, TEXAS 15265
Va
at
2-305
TlBPAL22V1 DC, TIBPAL22V10AC
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
recommended operating conditions
TIBPAL22Vl0C
MIN
NOM
4.75
5
TIBPAL22Vl0AC
UNIT
MAX
5.25
MIN
NOM
MAX
4.5
5
5.25
V
5.5
2
5.5
V
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
10H
10L
High-level output current
0.8
-3.2
Low-level output current
16
16
mA
mA
fclock
Clock frequency t
18
28.5
MHz
tw
Pulse duration
tsu
Setup time before clock;
2
0.8
-3.2
Clock high or low
25
15
Asynchronous Reset high or low
35
25
Input
30
20
Feedback
Synchronous Set
Asynchronous Reset low (inactive)
30
30
20
20
35
25
th
Hold time, input, set, or feedback after clockt
0
TA
Operating free-air temperature
0
ns
ns
0
75
V
ns
0
75
°e
electrical characteristics over recommended operating free-air temperature range
PARAMETER
Vee
Vee
Vee
Vee
VIK
VOH
VOL
10ZH
TIBPAL22Vl0C
TEST CONDITIONS
I Any output
I Any I/O
= 4.75 V,
11= -18 mA
= 4.75 V,
10H = -3.2 mA
= 4.75 V,
10L = 16 mA
Vo = 2.7 V
= 5.25 V,
Vo = 0.4 V
IlL
10S§
Vee
Vee
Vee
Vee
ICC
Vee = 5.25 V,
VI = 5.5 V
VI = 2.7 V
VI = 0.4 V
Vo = 0.5 V
Outputs open
VI = GND,
II
IIH
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
TYP*
2.4
3.5
0.35
Vee = 5.25 V,
10ZL
MIN
TIBPAL22Vl0Ae
MAX
-1.2
MIN
TYP*
2.4
3.5
0.5
0.35
V
V
0.5
V
0.1
-100
-250
-250
1
1
mA
25
25
-0.25
mA
-90
120
UNIT
0.1
-100
-0.25
-30
MAX
-1.2
-30
180
120
mA
p.A
~A
-90
mA
180
mA
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
fmax t
FROM
TO
TEST
eOND!TIONS
With feedback
TIBPAL22Vl0AC
TYP*
MAX
1,1/0
I/O
15
tpd
I, I/O (reset)
Q
tpd
Clock
Q
ten
1,1/0
Q
tdis
1,1/0
Q
Rl = 300 Il,
R2 = 390 Il,
See Figure 2
MIN
28.5
UNIT
TYP*
MAX
35
15
25
ns
15
40
15
30
ns
10
25
10
15
ns
15
35
15
25
ns
15
35
15
25
ns
18
tod
tfmax and fclock (with feedback) =
TIBPAL22Vl0C
MIN
MHz
1
, f max and fciock without feedback can be calculated as f max and
tsu + tpd (elK to Q)
fclock (without feedback) = _ _--'1'--_ _
tw high + tw low
*AII typical values are at Vee = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set Vo at
0.5 V to avoid test problems caused by test equipment ground degradation.
2-306
TEXAS . "
INSTRUMENTS
'POST OFFICE BOX 655303 • DALLAS, TEXAS 15265
TIBPAL22V1 DAM, TIBPAL22V1 DC, TlBPAL22V1DAC
HIGH·PERFORMANCE IMPACT™ PROGRAMMABLE ARRAY LOGIC
preload procedure for registered outputs (see Note 2)
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. Each register is preloaded
individually by following the steps given below.
Step
Step
Step
Step
1.
2.
3.
4.
With Vee at 5 volts and pin 1 at VIL, raise pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1, clocking in preload data.
Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage
level at the output pin.
preload waveforms (see Notes 2 and 3)
PIN 13
--.I
~tsu~
~td--+l
PIN 1
~td-+!
~
I
l l
1
I
I
I
REGISTERED 110
-
---VIH
.
I
I
I
=>--\
~I
INPUT
VIL
I
I
-VIH
/
Vr - - - VoH
\
-VIL
.
NOTES:
-
1
1- - -1- --1
I+--tw-+l
- -
::~H
-
OUTPUT
VOL
2. Pin numbers shown are for JT and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V.
TEXAS •
INSTRUMENTS
reST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-307
TlBPAL22V1 DAM, TIBPAL22V1 DC, TIBPAL22V10AC
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
power-up reset
Following power-up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the VCC's
rise be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable
input and feedback setup times are met.
power-up reset waveforms
r-----------------------------------5V
4
VCC __________ ; ; :
J
1144----tpd t
(600 ns typo , 000 ns MAX)
REGISTE:~~I~~~~~~
/
"I
I
~~5 ~ -
STATE UNKNOWN
-
-
-
- - VOH
------------,------------------------~~~------------VOL
I
/
ACTIVE·LOW
REGISTERED OUTPUT ________J.;..-_ _ _
ST_A_T_E_U_N_KN_O_W_N_ _
VOH
j{.
...JT: ~5 ~
_ _ _ _ _ VOL
t4-- t su*--+t
\1.5 V
CLOCK
CVIH
7:'.5 V
----------------------~~~-----J1- -
-VIL
~tw~
t This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
:t This is the setup time for input or feedback.
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666 .
2-308
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 76265
TIBPAL22V1 DAM, TIBPAL22V1 DC, TIBPAL22V1DAC
HIGH·PERFORMANCE IMPACrr M PROGRAMMABLE ARRAY LOGIC
PARAMETER MEASUREMENT INFORMATION
CL
(See Note A)
R2
LOAD CIRCUIT FOR
3·STATE OUTPUTS
TIMING
INPUT
~ 1.5 V
4·
[0.3 V] (0)
~:-e-:;~
HIGH.LEVEL~
PULSE
I
I
~
tsu~th
---..T l .5V
DATA
INPUT
[3.5 VI (3 V)
[3.5 V] (3 V)
I
[0.3 VI (0)
L
INPUT
-.Ii
tpd
IN.PHASE
OUTPUT
1.5V
- - - - - [3.5 V] (3 V)
\..- 1.5V
[0.3 VI (0)
I~~,
tpd~
I
~I tpd
VOL
OUTPUT
CONTROL
(Iow·level
enabling)
~
I
1.5 V
Ion
[0.3 VI (0)
fI
'-L -
-.I!+-
(See Note B)
ten
I
t dl•
14-
-
-
.-+! l+U
t di
1
-
[0.3 V] (0)
I
I I
I
~
WAVEFORM 2
Sl OPEN
(See Note B)
[3'5VI(3v)
1.5 V
W~~~3,Rs~-6--f:""\.r 1.5-; -:
OUT·OF·PHASE
OUTPUT
(See Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
[3.5 V] (3 V)
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
l\
-I4---+i
14--+1- tpd
I
1/
I J - - VOH
I T 1.5V I ~V
I
I
1.5 V
----
VOLTAGE WAVEFORMS
SETUP AND HOLO TIMES
[0.3 VI (0)
t,.--foI
LOW-LEVEL~I
I
PULSE
[3.5 V] (3 V)
~3.3V
P
-+I I+-
•
-
L-
-r.=--~OOH:.5
I .J
~-
~~ _ ~ _
VOL
VOL +0.5 V
VOH
V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3·STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten,S pF for tdis '
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For M suffix. use the voltage levels indicated in parentheses ( ), PRR ~ 10 MHz.
t, and tf S 2 ns, duty cycle = 50%. For C suffix. use the voltage levels indicated in brackets []. PRR ~ 1 MHz, t, = tf = 2 ns, duty
cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch 81 is closed.
E. Equivalent loads may be fused for testing.
FIGURE 2
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-309
-
2-310
TIBPAL22V10·20M, TIBPAL22V10·15C
HIGH·PERFORMANCE IMPACT·X™ PROGRAMMABLE ARRAY LOGIC
,OCTOBER 1989
M SUFFIX . .. JT PACKAGE
C SUFFIX . .. NT PACKAGE
• Second-Generation PAL Architecture
• Choice of Operating Speeds
(TOP VIEW)
TIBPAL22V10-15C ... 15 ns Max
TIBPAL22V10·20M ... 20 ns Max
• Increased Logic Power and 10 Outputs
• Increased Product Terms per Output
CLK/I
VCC
2
up to 22 Inputs
3
4
5
Average of 12
6
7
• Variable Product Term Distribution Allows
More Complex Functions to be Implemented
8
9
10
• Each Output Is User Programmable for
Registered or Combinatorial Operation,
Polarity, and Output Enable Control
11
GND
• Power-Up Clear on Registered Outputs
12
M SUFFIX. , . FK PACKAGE
C SUFFIX . .. FN PACKAGE
• TTL· Level Preload for Improved Testability
3:
>
W
a:
Q.
-
(TOP VIEW)
• Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
W
~ooQQ
000
_ _ ...J
oz:;:>::::;.::::;.
• Fast Programming, High Programming
Yield, and Unsurpassed Reliability Ensured
Using Ti·W Fuses
• AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features
I/o/a
I/o/a
I/o/a
I/o/a
I/o/a
I/o/a
I/o/a
I/o/a
I/o/a
I/o/a
5
4
3 2 1 282726
25
6
24
7
23
I/o/a
I/o/a
I/o/a
22
NC
9
21
10
20
I/o/a
I/o/a
I/o/a
NC
• Dependable Texas Instruments Quality and
Reliability
11
19
121314 1516 1718
• Package Options Include Plastic and
Ceramic Dual-In-Line Packages and Chip
Carriers
i-
0
::l
C
0
a:
Q.
--00-00
zz
<9
-~~
NC-No internal connection
Pin assignments in operating mode
description
The TIBPAL22V1 0-15C and TIBPAL22V1 0-20M are programmable array logic devices featuring high speed and
functional equivalency when compared to presently available devices. They are implemented with the familiar
sum-ot-products (AND-OR) logic structure featuring the new concept "Programmable Output Logic Macrocell".
These IMPACT-X'" circuits combine the latest Advanced Low·Power Schottky technology with proven
titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered
and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are
enabled through the use of individual product terms.
Further advantages can be seen in the introduction of variable productterm distribution. This technique allocates
from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This variable
allocation of terms allows far more complex functions to be implemented than in previously available devices.
IMPACT-X is a trademark of Texas Instruments Incorporated.
Copyright © 1989, Texas Instruments Incorporated
PRODUCT PREVIEW documents contain information
on products in the formative or design phase of
development,
Characteristic data and other
~::;:!~:t~~~Srr:~ ~~S~~8~::I~~ ~~~~~~~~~~~;:~
products without notice.
TEXAS l!}
INSIRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-311
TIBPAL22V10-20M, TIBPAL22V10-15C
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC
description (continued)
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic O. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22V10' offers quick design and development of custom LSI functions with complexities of 500 to 800
equivalent gates. Since each oftheten output pins may be individually configured as inputs on either a temporary
or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs
are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power-up with their outputs high. Registered
outputs selected as active-high power-up with their outputs low.
"'tJ
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will appear to be open.
:::c
o
The M suffix devices are characterized for operation over the full military temperature range of -55°C to 125°C.
The C suffix devices are characterized for operation from O°C to 75°C.
C
C
o
-I
"'tJ
:::c
m
-
I
,
0
8
4
" "
I
0
I
I
I
20
"
"
28
~
40
36
I
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
~ ~.
!
23
CELL
396
P
,~
:R:
if
880
2
P
~
5810
.f.....:..2!!1.
~
::p-
-~
MACRO
CELL
!=\
1452
3
-~
p
[
MACRO
CELL
V-
=1
p
.. .;»-
+
5812
~
-
2112
m
-
-l11
.:;J\,.-
5809
MACRO
II
I
~
CELL
-vb..
'"
5808
-0
R
440
4
~
m
5814
.. -
-b
~
2156 ::-:
MACRO
,
2860
1t.iP
r
.(:>!,::.
,j
II
'Wi :
2904
.,
3608
6__
,
«
P -
.:;Jt- j
?-----t>b-
,t
4312
a:='1
ItCtr
i
,
_~
t
4840
. MAC'O
CELL
.t-.
p _ 5822
---~+-~
1>\,.
4884
c
j
P - 5818
b~' ,C:'~820 J
!
8
o::)
~111
.:;J
w
a::
CELL
i>
3:
w
:...-::-:
CEll
5324
t
9
5368
P
~
5824
P
~
5825
wiGJJ
l
5720
~
5764
CELL
p
~
5826
P
m
5827
--0
11
~~-
Fuse Number = First Fuse Number + Increment
Inside each MACROCELL the "P" fuse is the polarity fuse and the "R" fuse is the register fuse.
TEXAS
"!1
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SYNCHRONOUS SET
ITO ALL REGISTERS I
"
2-313
TIBPAL22V10-20M, TIBPAL22V10-15C
HIGH-PERFORMANCE IMPACT-X'M PROGRAMMABLE ARRAY LOGIC
functional block diagram (positive logic)
~
r C1
SET
RESET
&
44x132
8
11S
~
>:1
OUTPUT
>--- P. lOGIC
MACROCEll 1"""'"'\
r
h
10
r-c;-
n
~
ClK/1 ~---
..-:;= I>
~
14
~
16
~
EN
..--p.
,-
n
~
EN
..-,- P.
n
~
EN
n
~
EN
n
..- EN
~
..- EN
~
~
~
~EN
~
~
~-
16
~
~
o
1~
'V
>
~::;= >
~
14
-
C
c:
~-
-----
12
-I
-----
10
"'C
l:J
-----
8
o
r
~f--
V-
~I--
m
V-
'-I--
-<
~
r
~
"'C
l:J
V-
-----
>
>
>
P.
CHt; f--I 1010
CHt; .......11010
CHt; .......11010
CHt; -++-11010
C>-4I\ -++-11010
CHt; -++-11010
CHt; -++-11010
EN
~ ........11010
~ ++-11010
EN
10
10
10
'"\... denotes fused inputs
2-314
k-++-I 1010
r- EN
n
12
'V
[>
TEXAS
~
INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75285
TIBPAL22V1 0-20M, TIBPAL22V1 0-1 SC
HIGH-PERFORMANCE IMPACT-X'M PROGRAMMABLE ARRAY LOGIC
output logic macrocell diagram
r---------,
I
,.........,.M=UX~ I
OUTPUT LOGIC MACROCELL
I r-AR---R---I_-O----~----~:
>--+_----110
r-''-----II>C1
SS
I
b----.--,O
1}
0
Go
1S
'-----'
3
FROM CLOCK BUFFER
MUX
I
I
I
I
I =
~-.::hr:::.. se_1_ ____ J
G1
S1
AR
asynchronous rosol
3:
w
G1
a:
D.
t-
O
::::)
o
oa:
D.
TEXAS ..If
INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-315
TIBPAL22V10-20M, TIBPAL22V10-15C
HIGH-PERFORMANCE IMPACT-)('M PROGRAMMABLE ARRAY LOGIC
51 - 0
50 - 0
51 - 0
50 - 1
REGISTER FEEDBACK, REGISTERED, ACTIVE· LOW OUTPUT
REGISTER FEEDBACK, REGISTERED, ACTIVE·HIGH OUTPUT
"'D
::c
o
c
c
o
51 = 1
50 - 1
51 - 1
50 - 0
-I
"'D
::c
I/O FEEDBACK, COMBINATIONAL, ACTIVE·LOW OUTPUT
~
FUSE SELECT
-m
I/O FEEDBACK, COMBINATIONAL, ACTIVE·HIGH OUTPUT
FEEDBACK AND OUTPUT CONFIGURATION
S1
SO
0
0
Register feedback
Registered
Active low
0
1
Register feedback
Registered
Active high
1
0
I/O feedback
Combinational
Active low
1
1
I/O feedback
Combinational
Active high
=e
=
=
o unblown fuse, 1 blown fuse
S1 and SO are select-function fuses as shown in the output logic macrocell
diagram.
FIGURE 1. RESULTANT MACROCELL FEEDBACK AND OUTPUT LOGIC AFTER PROGRAMMING
2-316
TEXAS ~
INSIRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL22V10·20M
HIGH·PERFORMANCE IMPACT·X™ PROGRAMMABLE ARRAY LOGIC
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................ 7 V
Input voltage (see Note 1) ................................................................. 5.5 V
Voltage applied to diabled output (see Note 1) ................................................ 5.5 V
Operating free-air temperature range ............................................... -55°C to 125°C
Storage temperature range ........................................................ -65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
Vee
V,H
Supply vOltage
VIL
Low-level input voltage
10H
High·level output current
10L
Low·level output current
MIN
NOM
MAX
4.5
5
5.5
V
5.5
0.8
-2
V
mA
12
mA
2
High·level input voltage
UNIT
V
Clock high or low
tw
Pulse duration
ns
Asynchronous Reset high or low
Input
Feedback
too
Setup time before clock! t
th
Hold time, input. set, or feedback after clock!
TA
Operating free-air temperature
ns
Synchronous Preset
Asynchronous Reset low (inactive)
t
ns
-55
The values for this parameter can only be obtained with a pulse repetition rate of 1 MHz.
125
°C
w
==
5>
w
a:
c..
I-
o
::l
C
oa:
c..
TEXAS ~
INSfRUMENlS
POST OFFICE BOX 655303 .. DALLAS, TEXAS 75265
2-317
TIBPAL22V10-20M
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC
electrical characteristics over recommended operating free-air temperature range
PARAMETER
UNIT
-1.2
V
0.5
V
Vo=2.7V
0.1
mA
Vo = 0.4 V
-0.1
mA
V, = 5.5 V
1
mA
Vee = 5.5 V,
V, = 2.7V
25
Vee = 5.5 V,
V, = 0.4 V
los!
Vee = 5.5 V,
Vo = 0.5 V
Icc
C,
Vee = 5.5 V,
V,=GND,
f= 1 MHz,
V,=2V
pF
Co
f= 1 MHz,
Vo = 2V
pF
1,=-18mA
V OH
Vee = 4.5 V,
10H = -2 mA
VOL
Vee = 4.5 V,
10L= 12mA
10ZH
Vee = 5.5 V,
10ZL
Vee = 5.5 V,
I,
Vee = 5.5 V,
I'H
I ClK
I All others
MIN
TYpt
MAX
Vee = 4.5 V,
I,L
t
TEST CONDITIONS
v,K
2.4
3.5
0.25
V
~A
-0.15
-0.1
-30
Outputs open
mA
-90
mA
180
mA
All typical values are at Vee = 5 V, T A = 25°C.
:J: Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. Vo is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
"tJ
JJ
o
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
C
FROM
TO
(INPUT)
(OUTPUT)
C
PARAMETER
C')
fmax §
-I
tpd
1,1/0
Ipd
I, I/O (reset)
tpd
Clock
ten
1,1/0
tdis
1,1/0
"tJ
JJ
m
-
<
m
§
fm., (with feedback) =
TEST CONDITIONS
Isu
+
Ipd
I/O
0
0
I/O,Q
1/0,0
(eLK 10 0)
MAX
UNIT
Rl = 390 0,
ns
R2 = 750 0,
ns
See Figure 2
ns
ns
ns
.
==
2-318
MIN
MHz
External feedback
TEXAS ,If
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL22V10-15C
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage (see Note 1) ................................................................. 5.5 V
Voltage applied to a disabled output (see Note 1) ............................................. 5.5 V
Operating free-air temperature range .................................................. Goe to 75°C
Storage temperature range ........................................................ -65°C to 15Goe
NOTE1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
High-level input voltage
V,l
Low-level input voltage
10H
High-level output current
10l
Low·level output current
lw
t'"
t
Supply voltage
Vcc
V,H
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
5.5
V
2
0.8
Pulse duration
Setup time before clock! t
th
Hold time, input, set, or feedback after clock!
TA
Operating free-air temperature
Clock high or low
10
Asynchronous Reset high or low
15
Input
13
Feedback
13
Synchronous Preset
13
Asynchronous Reset low (inactive)
15
0
0
The values for this parameter can only be obtained with a pulse repetition rate of 1 MHz.
V
-3.2
mA
16
mA
ns
ns
ns
75
'C
3=
w
:;
W
IX
a.
I-
U
::J
C
oIX
a.
TEXAS ",
INSJRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-319
TIBPAL22V10 .. 15C
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
V'K
Vee = 4.75 V,
I, =-18 mA
VOH
Vee = 4.75 V,
10H = -3.2 mA
VOL
Vee
10ZH
Vee = 5.25 V,
= 4.75 V,
2.4
TYpt
MAX
UNIT
-1.2
V
3.5
0.35
V
0.5
V
Va = 2.7 V
0.1
mA
Va = 0.4 V
IOL=16mA
-0.1
mA
I,
Vee
= 5.25 V,
V, =5.5V
1
mA
I'H
Vee = 5.25 V,
V, = 2.7 V
25
Vee = 5.25 V,
V, = 0.4 V
10Sl
Vee = 5.25 V,
Va = 0.5 V
Icc
Vce = 5.25 V,
V, =GND,
C,
1= 1 MHz,
V,=2V
pF
Co
f= 1 MHz,
Vo=2V
pF
Vee = 5.25 V,
I ClK
I All others
I'L
t
MIN
!!A
-0.15
-0.1
-30
Outputs open
mA
-90
mA
180
mA
All typical values are at Vee = 5 V, TA = 25°C.
*
Not more than one output should be shorted at a time and the duration 01 the short circuit should not exceed one second. Va is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
fmax §
§ 1m"
2-320
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
External feedback
MIN
MAX
40
UNIT
MHz
15
ns
R1 = 300 0,
20
ns
Q
R2 = 390 0,
12
ns
Clock
I/O
See Figure 2
22
ns
ten
1,1/0
1/0,0
15
ns
tdis
1,1/0
1/0,0
15
ns
tpd
1,1/0
I/O
tpd
I, I/O (reset)
Q
tpd
Clock
tpd'
(with feedback) =
.,----,...-':=-:::-:-:-=
Isu + lpa (eLK 10 Q)
TEXAS .Jf
INSTRUMENTS
POST OfFICE BOX 655303 • DAllAS. TEXAS 75265
TIBPAL22V10-20M. TIBPAL22V1 0-1SC
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC
power-up reset
Following power-up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of Vee be
monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and
feedback setup times are met.
power-up reset waveforms
4
VCC ___________
J
I1rr-----------------------------------
5V
1'114f------tpd t
.1
1600 ns typo 1000 ns MAX)
I
REGISTE:~~I~~~!~~
.LI_____
______
'i.u~~-.5-~---. __-__-_-___- ::~
S_TA_T_E_U_N_K_N_O_W_N
____
I
3:
w
ACTIVE-LOW
REGISTERED OUTPUT
5>
w
a:
CLOCK
Q.
t
to:::>
U
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
*
This is the setup time for input or feedback.
C
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
oa:
Q.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
. TEXAS.Jf
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-321
TIBPAL22V10-20M. TIBPAL22V10-15C
HIGH-PERFORMANCE IMPACT-X™ PROGRAMMABLE ARRAY LOGIC
preload procedure for registered outputs (see Note 2)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to setup through the entire state-machine sequence. Each register is preloaded
individually by following the steps given below:
Step 1.
Step 2.
Step 3.
Step 4.
With Vee at 5 V and pin 1 at VIL, raise pin 13 to VIHH'
Apply either VIL or VIH to the Oli,PUt corresponding to the register to be preloaded.
Pulse pin 1, clocking in preload data.
Remove output voltage, then lower pin 13 to VIL' Preload can be verified by observing the voltage level
at the output pin.
preload waveforms (see Notes 2 and 3)
PIN13~ ~tsu~
*-td--+l
~td~
PIN 1
"
:
I"
*-tw--+l
"
I
1- __ , ___ 1_ I
I
I
1
_
1
=>---\
I'
REGISTERED I/O
~----::~H
I
I
,
I
---VIH
I ,V , . - - - - VOH
\I-VIH
INPUT
-
I
\
-VIL
OUTPUT
VOL
NOTES: 2. Pin numbers shown are for JT and NT packages only. If chip-carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td tsu = Iw 100 ns to 1000 ns. V1HH = 10.25 Vlo 10.75 V.
=
2-322
=
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
TIBPAL22V10-20M, TIBPAL22V1 0-1 SC
HIGH-PERFORMANCE IMPACT-)CM PROGRAMMABLE ARRAY LOGIC
PARAMETER MEASUREMENT INFORMATION
CL
(See Note A)
R2
LOAD CIRCUIT FOR
3-STATE OUTPUTS
TIMING
INPUT
(3 V) [3.5 V]
~ 1.5 V
4·
-.T 1.5V
(3 V) [3.5 V]
~
I
L
,...---...,.
--.Ij
tpd
1.5 V
PULSE
(0) [0.3 VI
(See Note B)
--l+--+I
-
-
-
-
l\
(3 V) [3.5 VI
(0) [0.3 V]
~ tpo
IJ I J - - VOH
T 1.5V I ~V
,~
_,
tpd~
I
f4---+1-1 tpd
OUTPUT
CONTROL
(low-level
-
-
(0) [0.3 V]
(See Note B)
-
VOL
~
I
1.5 V
ten
I I
fI
:..L -
I
tdlS....,
W~~'g'L~~-ri---!i \rl-7.'5V ..
OUT-OF-PHASE
OUTPUT
(See Note D)
t. n
WAVEFORM 2
S10PEN
(See Note C)
I
-+I 14-
l
D.
(3v)[3'5VI
I-
1.5 V
...,.I /'+-
(See Note C)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5V
-
enabling)
I
I
IN-PHASE
OUTPUT--1"'1- J
1.5V
VOLTAGE WAVEFORMS
PULSE DURATIONS
"'- 1.5 V
~
~
a:
I
LOW-LEVEL~I
I
(3 V) [3.5 V]
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
(3 V) [3.5 V]
(0) [0.3 V]
I+--t., ---+I
tsu~th
~~"-:;-
DATA
INPUT
~
- - . ,.~. ~
HIGH-LEVEL
PULSE ----.JI'.~
(0) [0.3 VI
tdlS
-
-
~
:¥;=;:--
-+! I+-
o
(0) [0.3 V]
(See Note B)
-
A -
3.3
:::l
C
oa:
V
VOL
VOL + 0.5 V
L
D.
I -Y
\:=-=--
1.5 V
.~
----
~
V OH
VOH - 0.5 V
-OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C L includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdl,.
B. All input pulses have the following characteristics: For M suffix, use the voltage levels indicated in parentheses (), PRR S 10 MHz,
t, and tfs 2 ns, duty cycle: 50%. For C suffix, use the voltage levels indicated in brackets [I PRR S 1 MHz, t,: tf: 2 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such thalthe output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
D. When measuring propagation delay times of 3-state outputs, switch Sl is closed.
E. Equivalent loads may be used for testing.
FIGURE 2
TEXAS ."
INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-323
..
2-324
TIBPAL22VP10-25M, TIBPAL22VP10-20C
HIGH-PERFORMANCE IMPACpM PROGRAMMABLE ARRAY LOGIC
02943. FEBRUARY 1987-REVISEO OCTOBER 1989
•
M SUFFIX ... JT PACKAGE
C SUFFIX ... NT PACKAGE
Functionally Equivalent to the
T1BPAL22V1 0/1 OA, with Additional
Feedback Paths in the Output Logic
Macrocell
(TOP VIEW)
ClK/)
•
Choice of Operating Speeds:
TIBPAL22VP10-20C ... 20 ns Max
TIBPAL22VP10-25M ... 25 ns Max
•
Variable Product Term Distribution Allows
More Complex Functions to be Implemented
•
Polarity of Each Output is Programmable
•
TTL-Level Preload for Improved Testability
•
Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
GND
•
Fast Programming, High Programming Yield,
and Unsurpassed Reliability Ensured Using
Ti-W Fuses
•
AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features
•
•
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
Package Options Include Plastic and
Ceramic Dual-In-Line Packages and Chip
Carriers
........--~
VCC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
)/O/Q
I/O/Q
I/O/Q
)/O/Q
I/O/Q
I/O/Q
I
NC
)
description
>2
...J
__ u
U
4
1 28 27 26
3
2
Z
uQ Q
UO 0
>':::0:::0
5
25
6
24
7
23
8
9
22
10
20
21
11
The TIBPAL22VP10 is equivalent to the
TIBPAL22V10A but offers additional flexibility
in the output structure. The improved output
macrocell uses the registered outputs as inputs
when in a high-impedance condition. This
provides two additional output configurations for
a total of six possible macrocell configurations
all of which are shown in Figure 1.
19
12 13 14 15 16 17 18
NC-No internal connection
Pin assignments in operating mode
The device contains up to twenty-two inputs and ten outputs. It defines and programs the architecture
of each output on an individual basis. Outputs may be registered or nonregistered and inverting or
noninverting. In addition, the data may be fed back into the array from either the register or the I/O port.
The ten potential outputs are enabled through the use of individual product terms.
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output.
This variable allocation of terms allows far more complex functions to be implemented than in previously
available devices.
IMPACT is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA do.umants oontoin information
.urrant as of publioation data. Preducts .onform to
spacifioatlonl per tho tarms of TaJIII Instruments
=ir:";'.r;.~t,J.; ~::':~:r :I:"::::A:~" not
Copyright @ 1989. Texas Instruments Incorporated
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-325
TlBPAL22VP10-25M, TIBPAL22VP10-20C
HIGH-PERFORMANCE IMPACT"" PROGRAMMABLE ARRAY LOGl'C
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term_
These functions are common to all registers. When the synchronous set product term is a logic 1, the
output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous
reset product term is a logic 1, the output registers are loaded with a logic O. The output logic level after
set or reset depends on the polarity selected during programming. Output registers can be preloaded to
any desired state during testing. Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product terms, the TIBPAL22VP1 0
offers quick design and development of custom LSI functions with complexities of 500 to 800 equivalent
gates. Since each of the ten output pins may be individually configured as inputs on either a temporary
or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10
outputs are possible.
A poWer-up clear function is supplied that forces all registered outputs to a predetermined state after power
is applied to the device. Registered outputs selected as active-low power-up with their outputs high.
Registered outputs selected as active-high power-up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns.
Once blown, the verification circuitry is disabled and all other fuses will appear to be open.
The TIBPAL22VP1 0-25M is characterized for operation over the full military temperature range of - 55°C
to 125°C. The TIBPAL22VP10-20C is characterized for operation from O°C to 75°C.
2-326
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIBPAL22VP10-25M. TIBPAL22VP10-20C
HIGH-PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
functional block diagram (positive logic)
~
r C1
SET
RESET
&
32x44
8
11S
~
~1
~
---..
---..
ClKII
~ rv
-'~
i"""""
h
~ rv
~
1~
-
h
h
---..
---..
MACROCELL
~
r=>
~
r-->
12
EN
~
f--- 1/0/0
~
.......
1/0/0
().,
......
1/0/0
h
~
EN
h
~
EN
~
........
1/0/0
~
EN
~
.......
1/0/0
h
h
.... EN
~
h
.... EN
~r= F>
--...,
I-
EN
'-r= F>
--...,
I-
EN
1-->
V-
.... 1-->
V-
I-I--F>
V-
14
""""
~I1010
EN
EN
14
16
--...,
-
I-
V-
16
--...,
--...,
~
h
> LOGIC
~
10
~
[>
OUTPUT
I-I--F>
r
12
,,"""-
V-
10
F>
r-- 1/0/0
~ r-- 1/0/0
~
f--- 1/0/0
~
f--- 1/0/0
8
---..
10
10
10
"\..... denotes fused inputs
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-327
TlBPAL22VP10-25M. TIBPAL22VP10-20C
HIGH-PERFORMANCE IMPACpM PROGRAMMABLE ARRAY LOGIC
logic diagram (positive logic)
111
FIRST
FUSE
NUMBE
INCREMENT
fo
0
4
8
12
16
I11I111111'
,
20
24
28
3.
32
40
ASYNCHRONOUS RESET
ITO ALL REGISTERS I
AI
o!l=
L;!.
M>
~'
CELL
231
P .. 5808
R_5809
440
3ft>- ~
CEll
P-S810
R_58ll
880
121
..
221
L
924
=Orr
ik
CELL
~
1452
131
~ 211
P-5812
R-sa13
~
1496
~~
CEll
2112
(41-{>t- .
---vL
201
R-581S
~
2156
r.=rr
CELL
P-
1191
P-5816
2860
~~-U='
::::db.-'
P-5818
{1BI
I
-"""\ ~ i--J
-+
3652 -
I
~h
MACRO
_ CELL
J=f . ~
4268
17~
4312
~
p_ 5814
_......d'-r
~
-
J
(171
p_ 5820
R-S82l
~
..
~=-D
m
CELL
(16)
P-5822
4840
I_~l-{>b.: ~+'
~
4884·
~
+
ru
5324
~~----t>t=-
~
CEll
(151
P-5824
Roo 5825
5368
~
=
(14)
CELL
5720
p- 5826
(~-
Roo 5827
5764
-0
Ill)
I
I
I
II
II
II
--
SYNCHRONOUS SET
(TO All REGISTERS)
1131
Fuse Number = First Fuse Number ~ Increment
Inside each MACRO CELL, the "P" fuse is the polarity fuse and the "R" fuse is the register fuse.
TEXAS . "
INSTRUMENTS
2-328
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL22VP10·2SM, TIBPAL22VP10·20C
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
output logic macrocell diagram
OUTPUT LOGIC MACROCELL
--,
r--::":M::":U:::X-"
r-A-R--~R::;I-:O;:~~-'~~~~:
}--+-"'---I10
r-..!--------J> C1
SS
I
I
D----.-------IO
1}
03
GO
15
FROM CLOCK BUFFER
MUX
1}o G0
112/3
3
S2 t
I
S1
AR --aSynChrOnous reset
~- ::hr~se_t_
I
I
I
I
J
t This fuse is unique to the Texas Instruments TIBPAL22VP1 OA. It allows feedback from the 110 port using registered outputs as shown
in the macrocell fusing logic function table.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-329
TlBPAL22VP10·25M, TIBPAL22VP10·20C
HIGH·PERFORMANCE .IMPACT'" PROGRAMMABLE ARRAY LOGIC
S2 - 0
S1 ~ 0
so - 0
REGISTER FEEDBACK. REGISTERED. ACTIVE-LOW OUTPUT
S2 - 0
S1 - 0
SO - 1
REGISTER FEEDBACK. REGISTERED. ACTIVE-HIGH OUTPUT
S2 - 1
S1 - 0
SO - 1
S2 - 1
S1 - 0
SO - 0
I/O FEEDBACK. REGISTERED. ACTIVE-LOW OUTPUTt
I/O FEEDBACK; REGISTERED. ACTIVE-HIGH OUTPUTt
S2 - X
S1 - 1
SO - 0
1/0 FEEDBACK. COMBINATIONAL. ACTIVE-LOW OUTPUT
82 - X
S1 - 1
SO - 1
I/O FEEDBACK. COMBINATIONAL. ACTIVE-HIGH OUTPUT
tThese configurations are unique to the TIBPAL22VP10 and provide added flexibility when comparing it to the TlBPAL22V10 or
TIBPAL22V10A.
FIGURE 1. RESULTANT MACROCELL FEEDBACK AND OUTPUT LOGIC AFTER PROGRAMMING
2-330
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL22VP10·25M. TlBPAL22VP10·20C
HIGH·PERFORMANCE IMPACT'M PROGRAMMABLE ARRAY LOGIC
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
PROGRAM-FUSE SELECT
FEEDBACK AND OUTPUT CONFIGURATION
S2
S1
SO
0
0
0
0
Register feedback Registered
Active low
0
1
Register feedback Registered
Active high
1
0
0
1/0 feedback
Registered
Active low
1
1
1/0 feedback
Registered
Active high
X
0
1
0
1/0 feedback
Combinational Active low
X
1
1
I/O feedback
Combinational Active high
o = unblown fuse,
1 = blown fuse, X = unblown or blown fuse
52, S1, and SO are select-function fuses as shown in the output logic macrocell
diagram.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range: TIBPAL22VP10-25M ................. - 55 °e to 125 °e
TIBPAL22VP10-20e . . . . . . . . . . . . . . . . . . . .. ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 °e
NOTE 1; These ratings apply except for programming pins during a programming cycle or during a pre-load cycle.
recommended operating conditions
TIBPAL22VP10-25M
VCC
Supply voltage
VIH
High-level input voltage
TIBPAL22VP10-20C
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
V
5.5
2
5.5
V
2
VIL
Low-level input voltage
0.8
0.8
10H
High-level output current
-2
-3.2
V
mA
10L
low-level output current
12
16
mA
fclock
Clock frequency t
25
37
MHz
tw
Pulse duration
tsu
Setup time before clock!
Clock high or low
20
10
Reset high
30
20
Input
25
15
Feedback
25
15
Preset
25
15
Reset low (inactive)
30
20
th
Hold time, input, preset, or feedback after clock!
TA
Operating free-air temperature
t fclock Iwith feedback)
=
fclock (without feedback)
tsu
+
0
-55
ns
ns
0
125
0
ns
75
·C
1
, fclock without feedback can be calculated as
tpd (CLK to Q)
tw high
+ tw low
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-331
TlBPAL22VP10-25M
HIGH-PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
Vee
VOH
Vee
VOL
Vee
lOZH
Vee
= 4.5
= 4.5
= 4.5
= 5.5
Vee
=
Vee
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
10Zl
I Any output
I
Any I/O
II
IIH
VCC
III
VCC
lOS~
Vec
ICC
VCC
=
V,
II
V,
10H
V,
lOl
V,
Vo
= -2 mA
= 12 mA
= 2.7 V
5.5 V,
Vo
= 0.4
MIN
Typt
-18 mA
2.4
UNIT
V
3.5
0.25
V
0.5
V
0.1
mA
-100
V
= 5.5 V
VI = 2.7 V
VI = 0.4 V
Vo = 0.5 V
VI = GND,
MAX
-1.2
-250
1
VI
-30
Outputs open
140
~A
mA
25
~A
-0.25
mA
-90
mA
220
mA
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
FROM
TO
TEST CONDITIONS
fmax§
MIN
Typt
25
50
MAX
UNIT
MHz
12
25
ns
12
25
ns
Q
R2
= 50 pF,
= 390O,
= 750O,
8
15
ns
1,1/0
Q
See Figure 2
12
25
ns
1,1/0
0
12
25
ns
ted
tpd
I, I/O
1/0
Cl
I, 1/0 (reset)
Q
Rl
tpd
Clock
ten
tdis
t All typical values are at VCC = 5 V, TA = 25°C.
t Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set Va at
0.5 V to avoid test problems caused by test eQuipment ground degradation.
§ f max (with feedback)
=
tsu
+
1
, f max without feedback can be calculated as
tpd (ClK to 01
1
f max (without feedback) = - - - - - tw high + tw low
TEXAS . "
INSTRUMENTS
2-332
POST OFFICE BOX 865303 • DALLAS. TEXAS 75286
TIBPAL22VP10·20C
HIGH·PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
electrical characteristics over recommended operating free-air temperature range·
PARAMETER
TEST CONDITIONS
= 4.75
= 4.75
=
VIK
Vee
VOH
Vee
VOL
Vee - 4.75 V.
10ZH
Vee
=
5.25 V.
Vo
= 2.7
Vee
=
5.25 V.
Vo
= 0.4
II
Vee
IIH
Vee
III
lOS;
Vee
= 5.25
= 5.25
= 5.25
= 5.25
10Zl
I Any output
I Any I/O
V.
II
V.
10H
V.
V.
V.
Vee
V.
Vee - 5.25 V.
lee
MIN
Typt
2.4
3.5
-18 mA
=
-3.2 mA
0.35
MAX
-1.2
UNIT
V
V
0.5
V
V
0.1
mA
V
-100
-250
~A
1
mA
10l - 16 mA
= 5.5 V
VI = 2.7 V
VI = 0.4 V
Vo = 0.5 V
VI
VI - GND.
-30
Outputs open
140
25
~A
-0.25
-90
mA
210
mA
mA
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
FROM
TO
TEST CONDITIONS
fmax§
MIN
Typt
37
50
MAX
UNIT
MHz
12
20
ns
12
20
ns
Q
R2
= 50 pF.
= 300 II.
= 390 O.
8
12
ns
1.1/0
Q
See Figure 2
12
20
ns
1.1/0
Q
12
20
ns
tpd
1.1/0
110
el
tpd
I. 110 (reset)
Q
R1
tpd
elock
ten
tdis
t All typical values are at Vee = 5 V. T A = 25°e.
:I: Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set
0.5 V to avoid test problems caused by test equipment ground degradation.
§ f max (with feedback)
=
tsu
+
Va
at
1
• f max without feedback can be calculated as
tpd (elK to Q)
{max (without feedback) = _..,..,....,..;-1-----,tw high + tw low
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 76265
2-333
TIBPAL22VP10·25M, TIBPAL22VP10·20C
HIGH·PERFORMANCE IMPACTlM PROGRAMMABLE ARRAY LOGIC
preload procedure for registered outputs (see Note 2)
The output registers of the TIBPAL22VP1 0 can be preloaded to any desired state during device testing.
This permits any state to be tested without having to step through the entire state-machine sequence.
Each register is pre loaded individually by following the steps given below.
Step
Step
Step
Step
1.
2.
3.
4.
With Vee at 5 volts and pin 1 at VIL, raise pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1, clocking in preload data.
Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage
level at the output pin.
preload waveforms (see Notes 2 and 3)
~----VIHH
PIN13~
I4- l d-+l
j+-Isu--+t
I+-Id---+i
PIN 1
i
1
I
I
I
I·
~
I
I
I
I
I
I
~-VIH
REGISTERED 1/0 ~
INPUT
!
-VIL
NOTES:
V,......---VOH
\
OUTPUT
VOL
2. Pin numbers shown are for JT and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td
2-334
VIL
iu-l-hih---:::
I+-Iw-.l
= tsu = tw =
100 ns to 1000 ns. VIHH
=
10.25 V to 10.75 V.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TlBPAL22VP10-25M, TlBPAL22VP10-20C
HIGH-PERFORMANCE IMPACTTM PROGRAMMABLE ARRAY LOGIC
power-up reset
Following power-up, all registers of the TIBPAl22VP10 are reset to zero. The output level depends on
the polarity selected during programming. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it
is important that the VCC's rise be monotonic. Following power-up reset, a low-to-high clock transition
must not occur until all applicable input and feedback setup times are met.
power-up reset waveforms
~-----------------------------------5V
.JJii
4
vcc ___________
I4!OIf------ t pd t
1600 ns typo '000 ns MAX)
REGISTE:;~I~~~~~~
/
~
I
~~5 ~ -
STATE UNKNOWN
-
-
-
- - VOH
----------~---~--------------------~~~------------VOL
I
ACTIVE-LOW
REGISTERED OUTPUT ___________..A.....·______
ST_A_T_E_U_N_K_N_O_W
__
N____
I
Jl
...JT: ~5 ~
VOH
_ _ _ _ _ VOL
r+--tsu* --+I
\1.5 V
CLOCK
CVIH
,'.5V
------------------------------~~----------J1- -
- VIL
14--- tw-----+t
tThis is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
t This is the setup time for input or feedback.
programming information
Texas Instruments Programmable logic Devices can be programmed using widely available software and
inexpensive device programmers.
When the additional fuses are not being used, the TIBPAL22VP10 can. be programmed using the
TIBPAl22V10/10A programming alogrithm. The fuse configuration data can either be from a JEDEC file
(format per JEDEC Standard No.3-A) or a TIBPAl22V10/10A master.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 995-5666.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-335
TIBPAL22VP10-25M, TIBPAL22VP10-20C
HIGH-PERFORMANCE IMPACTTM ·PROGRAMMABLE ARRAY LOGIC
PARAMETER MEASUREMENT INFORMATION
5V
SI
I.
Rl
FROM OUTPUT _ ..._ ...~..._
UNOER TEST
CL
(See Note AI
TEST
POINT
R2
LOAO CIRCUIT FOR
THREE-STATE OUTPUTS
TIMING
INPUT
/..
---[3.5V](3V)
[3.5 V] (3 V)
F,1.5V
_ _ _..J.U - - - - - [0.3 V] (0)
I+-th-+l
)4-tsu-+\
I
DATA ~~-- [3.SV] (3 V)
1.5V
1.5V
INPUT
[0.3 V] (0)
HIGH-LEVEL
PULSE
15 V
15 V
~
. . .
,..----.....
.¥.I 1.5 V
OUT-OF-PHASE
OUTPUT
(See Note D)
- [3.5 V] (3 V)
14
.1
I
I
~
1
I
tpd
-
14.1
: f1.5V:
IN-PHASE
OUTPUT
-
I
14.1
14
\1.5V
.
VOLTAGE WAVEFORMS
PROPAGATION OELAY TIMES
tpd
,t--VOH
I
.1
VOL
tpd
~VOH
.
I
PULSE
1.5V
-
-
1.5V
- - [0.3 V] (0)
VOLTAGE WAVEFORMS
PULSE DURATIONS
\1.5 V
I ' - - - - [ 0 . 3 V] (0)
--...I.
tpd
-
I · [0.3 V] (0)
LOW-LEVEL~I [3.5 V] (3 V)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
I
I
!.-- t w ----"!
- - VOL
OUTPUT ~[3.5V] (3 V)
CONTROL
1.5V
1.5V
(low-level
_1 _ _ _ _ . [0.3 V] (0)
enabling)
I
I
ten
I+..... I+-- tdis
--+t
I!
IIII
=3.3 V
WAVEFORM l - - - r \ : . 1.5 V
~VOL +0.5 V
SI CLOSEO
1 ~-==~-= V
(See Note 8)
ton-+l
i
.....fIoI ~~s_T~_
VOL
WAVEFORM2~--.S10PEN
(See Note B)
1.5 V
OH
LVOH-0.5 V
=0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten. 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For M suffix, use the voltage levels indicated in parentheses ( l.
PRR :s 10 MHz, tr and tf :s; 2 n5, duty cycle = 50%. For C suffix, use the voltage levels indicated in brackets [ ],
PRR s 1 MHz. tr = tf = 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
FIGURE 2
2-336
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPALR19LBC, TlBPALR19R4C, TIBPALR19R6C, TIBPALR19RBC
HIGH-PERFORMANCE REGISTERED-INPUT PAL® CIRCUITS
02709, DECEMBER 19B2-REVISED AUGUST 1989
•
High-Performance Operation ... 30 MHz
•
Preload Capability on Output Registp.rs
DEVICE
110 INPUTS
I INPUTS
'PALRI9L8
'PALRI9R4
'PALRI9R6
'PALRI9R8
11
11
11
11
2
0
0
0
o
•
DIP Options Include Both 300-mil Plastic
and SOO-mil Ceramic
•
Dependable Texas Instruments Quality and
Reliability
3-STATE
OUTPUTS
2
0
0
0
REGISTERED
Q OUTPUTS
1/0 PORTS
0
4 13-state buffers)
6 13-state buffers)
8 13-state buffers)
6
4
2
0
TIBPALR19LB'
JW OR NT PACKAGE
description
These programmable array logic devices feature
high speed and functionality similar to the
TIBPAL 16L8, 16R4, 16R6, 16RS series, but
with the added advantage of Ootype input
registers, If any input register is not desired, it
can be converted to an input buffer by simply
programming the architectural fuse,
ITOP VIEW)
110
110
110
110
GND
0
INCLK
I
TIBPALR19LB'
FN PACKAGE
ITOP VIEW)
43212B2726
lID
lID
110
NC
110
110
110
A C suffix designates commercial-temperature
circuits that are characterized for operation from
DOC to 70°C,
INPUT REGISTER FUNCTION TABLE
X
1/0
1/0
1/0
1/0
1/0
'iiD
Extra circuitrv',/1~~ bee~ provided to allow loading
of each r.~~~~~r ~synchronously to either a high
or low state, This feature simplifies testing
because the registers can be set to an initial state
prior to executing the test sequence,
L
"fli';
',!/Q;
Combining Advanced Low-Power Schottky t
technology, with proven titanium-tungsten
fuses, these devices will provide reliable high
performance substitutes over conventional TTLlogic, Their easy programmability allows ''i¥\'
quick design of custom functionsal1d',ty~i\3ai'iy
result in a more compact c,;irlNit<,b6ilrd, In
addition, chip carriers are, ai)'ellable for further
reduction in board "spa~e. ,"
INPUT
INCLK
0
I
H
L
I
VCC
IjP;':,
liD
110
110
110
OUTPUT OF
INPUT REGISTER
H
25
5
6
24
23
22
21
20
19
9
10
II
1/0
1/0
1/0
NC
12131415161718
L
Qo
NC - No internal connection
t Integrated Schottky-Barrier diode-clamped transistor is patented
by Texas Instruments, U,S, Patent Number 3,463,975,
PAL is a registered trademark of Monolilthic Memories Inc.
PRODUCTION DATA documents contain information
currant 88 of publication datI. Products conform to
spacifications per the terms of Texes Instruments
:~~~:~~i~ai~:;:'~~ ~::i~:i:f :1~o::~:::t:~~S not
Pin assignments in operating mode
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS. TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-337
TIBPALR19R4C, TlBPALR19R6C, TIBPALR19R8C
HIGH·PERFORMANCE REGISTERED·INPUT PAL® CIRCUITS
TlBPALR19R4'
JW OR NT PACKAGE
TIBPALR19R4'
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
OUTCLK
110
VCC
110
110
110
4
Q
110
110
110
NC
110
110
110
Q
110
110
110
liD
110
Q
Q
110
110
INCLK
GND L.C;:.........:::~
DE
3 2
1 282726
5
25
24
6
7
8
9
10
22
21
11
12 131415161718
TIBPALR19RS'
JW OR NT PACKAGE
TlBPALR19RS'
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
OUTCLK
110
110
110
110
VCC
110
110
Q
4
Q
110
110
110
NC
110
110
110
Q
Q
110
110
110
110
110
GND
Q
Q
110
INCLK
DE
3 2
1 282726
D5
25
24
Q6
g7
23
Q
NC
9
22
21
10
20
Q
19[
Q
8
11
12 131415161718
TIBPALR19RS'
JW OR NT PACKAGE
TIBPALR19RS'
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
OUTCLK
liD
110
110
liD
110
VCC
110
Q
Q
4321282726
Q
Q
Q
Q
110
110
110
Q
Q
INCLK
GND _;;......:..:;... DE
12 131415161718
gg~~I~dd
Pin assignments in operating mode
(!)
;!;
NC-No internal connection
2·338
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DAlLAS, 'TEXAS 75265
Q
Q
Q
TlBPALR19L8C, TIBPALR19R4C
HIGH·PERFORMANCE REGISTERED·INPUT PAL® CIRCUITS
functional block diagrams (positive logic)
'PALR19L8
EN ;>1
'iJ
0
0
1/0
110
110
110
110
110
6
'PALR19R4
OE------------------------------~~
OUTCLK--------------------------------;>
1---0
INCLK -------{>
t--t--i--+--
11
0
t:>-,-----"'-I--I/O
I:>-....+---OH-I--I/O
t:>-.-+---H-I-- I/O
t:>-.-+---H-I--
1/0
4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·339
TIBPALR19R6C, TIBPALR19R8C
HIGH·PERFORMANCE REGISTERED·INPUT PAL® CIRCUITS
functional block diagrams (positive logic)
'PALR19R6
oE--------------------~~~-,
OUTCLK---------------------------i>
o
&
o
INCLK -----i>
o
o
o
o
1-_...2.~~....,~I-I/O
b-ti..........---j!--I/O
'PALR19R8
OE----------------------~fiNr__,
OUTCLK---------------------------i>
o
t---r--1=~0
INCLK---t>
o
o
t--r-""1---+-0
"
o
1--t--1--4--0
a
8
2-340
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TlSPALR 19L8C
HIGH-PERFORMANCE REGISTERED-INPUT PAL® CIRCUITS
logic diagram (positive logic)
11)
INCREMENT
"o@~o
~
4
12
16
20
,
24
28
32
36
J
123),
IC2
2D
MIl
24r
~
ACT UAL FUSE
NUM BER
FIRST
FUSE NUMBERS
,.3.
L-.
00
114
110 @L
152
190
:~2
~
~~I
304
MO
Ml
342
380
fJ
:~:
2434
IID~
494
532
510
~2
~~
Me)
Ml
121),
10
l
120),
10
l
119),
l
118),
l
(17),
1
116)
l
115)
950
988
EP
19~
H~
1216
b
1264
1292
2437 1330
Me
M1
1558
1596
2438 ~:~~
~
0
v
v
10
10
10
tI~
1~2 lH:
1/0,!!l
,~
20
1824
_ 2439
~~~:
~
:~2
~3g~
v
MO
M1
1/0
~
I/D!!l1i}- ::::
2168
2204
2440 U3~
v
(10)fttJ~
1~2 m!
I/D~
122)
v
:::
~
I/D!2!..JJ~
l~2 ~~
I/U~
De2
l
~~
MO
M1
~
~
684
I/D.@..Ii!f~
~2
2436
~
l
::
Ml
2435
10
MI
a
11,
~~
MI
2441
110 I!.!;
g,2
MD
MI
w;:
__2_44_2_+--_ _ _A_c_T_U_A_L_F_U_S_E_N_U_M_B_E_R_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-+-<~~1"-14),NCLK
Fuse Numbers = First Fuse Number + Increment
Pin numbers shown are for JW and NT packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
~3),
2-341
TlBPALR19R4C
HIGH·PERFORMANCE REGISTERED·INPUT PAL® CIRCUITS
logic diagram (positive logic)
OUTCLK (1)
INCREMENT
,
A
i
110
!3l
~o
4
8
16
12
20
24
28
32
0C2
102
20
24t _
304
342
380
t
MO
Ml
2435
110
oc,
!&
le2
608
646
684
~~~
,~
20
912
MO
960
Ml
~r
OC2
~~
Ml
-=
110
ill.
1178
1406
tIff
1482
MO
Ml
1558
1596
1520
2438 1634
110 ~
~n~
OC2
I/O ~
20
MO
Ml
2440
1824
1862
1900
110
(l!!!
p--I~ ~
Q
~
l
(161
I/O
1
2090
2128
2168
2204
1
~~:~
jt
I[
OC2
Q
1786
2439 1938
_
1976
OC2
le2
Q
el
(I'"
~jr
102
20
MIl
Ml
Q
~
p-
1292
OC2
Ie,
-=
1/0
1216
1254
2437 n~g
20
(211
P-- ~ ~191
988
1064
MO
I/O
el
2436 1026
I/O ~
(221
r
v
I
>B~'
670
OC2
le2
20
J
J
-= 2434 :~=
494
I/O ~
ACTUAL FUSE
NUMBER
it
l1=
fll
OC2
102
MIl
Ml
I/O
1
""
20
(231
MO
_ :33
@L
J
102
20
FIRST
FUSE NUMBERS
'--+ 00
38
7.
162
190
110
36
2394
le2
20
(151
I/O
I
MO
Ml
2441
110
(!!l
le2
20
MO
Ml
-= 2442+-- ACTUAL FUSE NUMBERS
~
2-342
IINCLK
IDE
Fuse Numbers = First Fuse Number + Increment
Pin numbers shown are for JW and NT packages.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TIBPALR19R6C
HIGH·PERFORMANCE REGISTERED·INPUT PAL® CIRCUITS
logic diagram (positive logic)
OUTCLK~(I~)~==============================================================~~
INCREMENT
,
.
ill
110
12
ttri:'
16
20
24
28
32
36
J
Ie,
(23)
'D
i 0
110
MIl
M
Ml
2432
2433
TL-,--~
ACTUAL FUSE
NUMBER
L-
FIRST
FUSE NUMBERS
~~
L.-.
76
"'
'52
@lrtfJ'~' :::
110
MO
M1
342
380
:J~
2434
I/D~r#J~
~~' :::
MO
M1
646
684
~~~
2435
.~~~,~' m
1/0-
~
~~
M1
988
2436 ~g~:
110
~rtD~
~~2 ::!:
MO
1254
M1
110 ill
1292
~~
:;:7 ~!
MO
M1
1558
1596
2438 ~~~~
1~2 1m
I/D'~rJ~
,-
20
MO
M1
1824
1862
1900
_ 2439 a~:
I/D~~~~2
MO
M1
2440
::::
2168
2204
~~:~
(10)ftiJ~
,g'i' ~U!
I/D~
~
Ml
2441
I/D!!.!.iJf
I
Ml
_ 2442 _ _ ACTUAL FUSE NUMBERS
w;:---------------------------------I-<~}-(~14)INCLK
Fuse Numbers
=
First Fuse Number
+
Increment
~)OE
Pin numbers shown are for JW and NT packages.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·343
TlBPALR19RBC
HIGH·PERFORMANCE REGISTERED·INPUT PAL® CIRCUITS
logic diagram (positive logic)
OUTCLK~(1~1~==============================================================~~
INCREMENT
I
A
i
c,
110
@..
~
16
12
4
20
28
24
32
0
~
-oc,
~;f-_-+
_ _ _--"'12:::c311/D
MD
Ml
24;2 ~
2433
'-----+-- ~S~~~~ FUSE
FIRST
FUSE NUMBERS
'------+
36 \
00
38
7.
11,
152
110
1!l
frfD'!:
MO
M1
2434
110
342
380
:Ag
~fJJ~
::f' :::
MO
M1
110
!:
@.
646
684
2435
~~~
MO
M1
950
988
~~
l?/ :::
2436 ~g~:
liD
110
!!!..~~
l~ ::::
ill
MO
M1
1254
1292
MO
1558
2438
~~~
t1~
:;7 !~~
Ml
110
1596
!!!!rJ~
l~2 :::
t:V
~~g~
t>-~~IO
_ 2439 ~~~~
I/O
!!!!.~.
:~2 ::::
MO
M1
2168
2204
t> ~~IQ
2440 ~~;~
I/D(~~~~'mi
Ml
2441
110
(wiJ!2
I
I
II
Ml
2442 __
ACTUAL
FUSE
NUMBERS
'-"'--_
__
__
___
__
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _+d/1.!..'.1141INCLK
~
~310E
Fuse Numbers = First Fuse Number + Increment
Pin numbers shown are for JW and NT packages.
2-344
TEXAS
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DAlLM1;. TEXAS 75265
TIBPALR19LBC, TIBPALR19R4C, TIBPALR19R6C, TlBPALR19RBC
HIGH·PERFORMANCE REGISTERED·INPUT PAl® CIRCUITS
absolute maximum ratings over operating free·air temperature range (unless otherwise
noted I
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range ...................................... oDe to 70 De
Storage temperature range ......................................... - 65 De to 150 De
NOTE 1: These ratings apply e>ccept for programming pins during a programming cycle or during preload cycle.
recommended operating conditions
VCC
Supply voltage
VIH
VIL
High-level input voltage
IOH
High-level output current
MIN
4.75
2
Low-level input voltage
IOL
Low-level output current
fclock
Clock frequency
INCLK
OUTCLK
INCLK high
tw
INCLK low
OUTCLK high
Pulse duration, clock
OUTCLK low
Data before INCLKt
tsu
Setup time
th
Hold time
TA
Operating free-air temperature
Data before OUTCLKt
INCLKt before OUTCLKt (See Note 2f
Data after INCLKt
Data after OUTCLKt
0
0
15
15
15
15
10
25
25
5
0
0
NOM
MAX
UNIT
5
5.25
5.5
0.8
-3.2
24
30
30
V
V
V
mA
mA
MHz
ns
ns
ns
70
°c
NOTE 2: This setup time ensures the output registers will see stable data from the input registers.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-345
TIBPALR19L8C, TIBPALR19R4C, TIBPALR19R6C, TIBPALR19R8C
HIGH·PERFORMANCE REGISTERED·INPUT PAL® CIRCUITS
electrical characteristics over recommended free·air operating temperature range
PARAMETER
TEST CONDITIONS
= 4.75 V,
= 4.75 V,
VOH
Vcc
Vcc
VOL
Vcc - 4.75 V,
VIK
Outputs
10ZH
10Zl
1/0 ports
Outputs
1/0 ports
II
MIN
=
10H
Typt
-18 rnA
=
-3.2 rnA
2.4
Vcc
=
5.25 V,
VIH
= 2.7
Vcc
=
5.25 V,
VIH
= 0.4 V
-250
V
~
~
0.2
110 Inputs
VCC
=
5.25 V,
VI
=
0.1
5.5 V
rnA
0.1
OE Input
40
110 Inputs
VCC
=
5.25 V,
VI
= 2.7
20
V
All others
~A
20
-0.4
OE Input
110 Inputs
III
V
0.5
100
-20
All others
IIH
V
20
V
O! Input
II
UNIT
3.3
0.35
10l - 24 rnA
MAX
-1.5
VCC
=
5.25 V,
VI
= 0.4
-0.6
V
rnA
-0.2
All others
=
10*
VCC
ICC
VCC = 5.25 V,
Outputs open
5.25 V,
Vo
VI
= 2.25 V
= OV,
-30
150
-125
rnA
210
rnA
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TYP*
MAX
15
25
ns
1/0,0
20
35
ns
20
35
ns
OUTClKi
1/0,0
Q
10
20
ns
ten
OE.
Q
10
20
ns
ten
1,1/0
1/0,0
14
25
ns
tan
ten
I/O§
1/0,0
1/0,0
27
40
ns
INClKt
27
40
ns
tdis
OE!
Q
11
20
ns
~is
1,1/0
1/0,0
12
25
ns
tdis
I/O§
1/0,0
13
30
ns
~is
INClK!
1/0,0
13
26
ns
f rnax
FROM
TO
tDd
INClKi
1,1/0
1/0,0
1/0,0
tDd
I/O§
tDd
tDd
INClKt
TEST CONDITIONS
MIN
Rl
R2
CL
=
=
=
50011,
50011,
50 pF,
See Figure 1
UNIT
MHz
30
t All typical values are VCC = 5 V, T A = 25 ·C.
:l:The output conditions have been chosen to produce a current that closely approximates one half the true short~circuit current, lOS.
§Input configured as an input buffer.
2-346
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DAUAS, TEXAS 75265
TIBPALR19LBC, TlBPALR19R4C, TlBPALR19R6C, TIBPALR19RBC
HIGH·PERFORMANCE REGISTERED·INPUT PAL® CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications. algorithms. and the latest information on hardware. software. and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available. upon request. from the nearest TI field sales office. local
authorized TI distributor. or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Note 3)
Step
Step
Step
Step
Step
Step
Step
1
Pin 13 to VIH. Pin 1 to VIL. and VCC to 5 volts.
Pin 14 to VIHH
At Q outputs. apply VIL to preload a low and VIH to preload a high.
Pin 14 to VIL.
Remove the voltages applied to the outputs.
Pin 13 to VIL
Check the output states to verify preload.
2
3
4
5
6
7
preload waveforms (see Note 3)
5V
vcc
ov
J
OUTPUTS DISABLED
VIH
I
PIN 13 (DE)
VIL
tdis
VIHH
------.---
VOL
ENABLE PRELOAD
I
I
I
I
100 ns
MIN
I
I
\
:I ~I
VIL
Q
~ten
I
PIN 14 (lNCLK)
VOH
)
I
--i++!
I
I
jf---tWl----.1
VIH
II
_I
~I
'(
XXXXXXXXX)
I
I
I
I
I
VERIFY
)-{
I
I
VIL
xm
security fuse programming (see Note 3)
Vcc
~
I
PIN1 _ _ _ _
~tw3-.1
!...~_th_-.j.:J:I\--n----I
PIN 13
u
!.-tw3..1
Il:l:l& 0 v
:
:6
___ : ___ n
:
I-th-l~'
, ~th.j- I
__________________________
I
I
~I
V
V
- - - 16 V
OV
NOTE 3: Pin numbers shown are for JW and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-347
TIBPALR19L8C, TIBPALR19R4C, TlBPALR19R6C, TlBPALR19R8C
HIGH·PERFORMANCE REGISTERED·INPUT PAl® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
5V
Sl
L
_+_._..._
Rl
FROIiII OUTPUT
UNDER TEST
TEST
POINT
R2
CL
(See Note Al
LOAD CIRCUIT FOR
THREE·STATE OUTPUTS
TIIiIIING
INPUT
./.
F,1.5V
------,U - -
-
I4-th-+t
)4-tsu-+j
I
---3.5V
3.5 V
HIGH·LEVEL
PULSE
15V
15 V
~
.
.
- - - 0.3 V
DATA
~~;v-3.5V
INPUT..../' 1.5 V
~
0.3 V
LOW-LEVEL
PULSE
tpd
I..
I
:
IN·PHASE
OUTPUT
tpd
I
...
3.5
I·
~I
0.3 V
~I
f1.5V :+-I~
I..
tpd
I
I
~I
I"
OUT·OF·PHASE
OUTPUT
(See Note DI
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
I
~I
I
3.5V
- - --0.3V
VOLTAGE WAVEFORMS
PULSE DURATIONS
\1-:; -; - -- V
-.J!1.5V
0.3 V
I
15V
15 V
~
.
.
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
Ltw---.l
1
OUTPUT
CONTROL
(low·level
enablingl
~3.5V
1.5 V
I
I
ten
VOH
VOL
tpd
~I VOH
T l . 5V
--VOL
---+I
14-
I I
WAVEFORM 1
Sl CLOSED
(See Note BI
WAVEFORM 2
S10PEN
1.5 V
I·
-1- - - - _. 0.3 V
-+I I+-- tdis
I I
-33 V
I 1.5 V
III-'
~VOL + 0.5 V
~
I
ten-+!
j4-
-= =
-.! .... tdis l.
-= VOL
~
I
(See Note BI
I _ _ _ :t.-VOH
-
1.5 V
-
LVOH-0.5 V
~O
V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten. 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR s 1 MHz. tr = tf = 2 ns. duty cycle = 50%.
D. When measuring propagation delay times of 3-st8te outputs, switch S1 is closed.
FIGURE 1
2-348
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TIBPALT19L8C, TIBPAL T19R4C, TlBPAL T19R6C, TIBPALT19R8C
HIGH·PERFORMANCE LATCHED·INPUT PAL® CIRCUITS
02709. DECEMBER 1982-REVISED AUGUST 1989
•
High-Performance Operation . . . 30 MHz
•
Preload Capability on Output Registers
•
DIP Options Include Both 300-mil Plastic
and 600-mil Ceramic
•
Dependable Texas Instruments Quality and
Reliability
3-STATE
DEVICE
110 INPUTS
I INPUTS
o OUTPUTS
'PALT19L8
'PALT19R4
'PALT19R6
'PALT19R8
11
11
11
11
2
0
0
0
2
0
0
0
REGISTERED
Q OUTPUTS
1/0 PORTS
0
6
4 13-state buffers)
6 13-state buffers)
8 13-state buffers)
4
2
0
description
TIBPALT19LB'
JW OR NT PACKAGE
These programmable array logic devices feature
high speed and functionality similar to the
TIBPAL l6l8. l6R4. l6R6. l6R8 series. but
with the added advantage of Ootype transparent
latches on the inputs. If any input register is not
desired. it can be converted to an input buffer
by simply programming the architectural fuse.
ITOP VIEW)
lID
I/O
I/O ~,'::'~F!:
Combining Advanced Low-Power Schottkyt
technology. with proven titanium-tungsten
fuses. these devices will· provide reliable high '*'''\
performance substitutes over conventional T ~V
logic. Their easy programmability all
quick design of custom functio
ally
oard. In
result in a more compact
addition. chip carriers
reduction in boar
een provided to allow loading
of each r
er asynchronously to either a high
or low state. This feature simplifies testing
because the registers can be set to an initial state
prior to executing the test sequence.
I/O
I/O
lID
lID
GND'-I:.~":'::'I-'
TIBPALT19LB'
FN PACKAGE
ITOP VIEW)
00
u
u
Uo
::::;;:;;_2>:::'::0
4 3 2 1 28 2726
110
5
25
24
23
22
21
6
A C suffix designates commercial-temperature
circuits that are characterized for operation from
OOC to 70°C.
10
11
I/O
I/O
I/O
NC
I/O
I/O
I/O
12 131415161718
INPUT LATCH FUNCTION TABLE
INLE
0
o C 0 u
::::::Z2
<.?
LATCH OUTPUT
L
L
L
L
H
H
H
X
NC
-IW
~
0
-
No internal connection
Pin assignments in operating mode
Qo
t Integrated Schottky-Barrier diode-clamped transistor is patented
by Texas Instruments, U.S_ Patent Number 3,463.975.
PAL is a trademark of Monolithic Memories Inc.
PRODUCTION DATA d.....nts ...toin 1......lIlon
of p.bUoIIloa dote. Praduots ........ to
spaciflcotloM per 110. _
of T.... Instr.m....
••1'l'0III11
:=~·f:~'::li
=::i:: =.:~:.s
oot
Copyright @ 1989. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-349
TlBPALT1UR4C. TIBPALHUR6C. TIBPAL T1URBC
HIGH·PERFORMANCE LATCHED'INPUT PAL@ CIRCUITS
TIBPALT19R4'
JW OR NT PACKAGE
TIBPALT19R4'
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
OUTCLK
110
110
110
lID
110
110
110
110
110
110
GND
"
--'
U
I-
VCC
110
110
110
U
ao::Juuoo
"'~OZ>~~
4
Q
3 2
1 28 2726
25
24
Q
Q
Q
23
22
NC
110
110
INLE
DE
21
lID
lID
10
11
20
19
110
Q
Q
NC
Q
Q
110
12131415161718
0 0 0 UI W IW 0
:::::::::;zzo~::::
<:l
_
TIBPALT19RS'
JW OR NT PACKAGE
TIBPALT19RS'
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
OUTCLK
110
110
"'i
VCC
110
110
Q
Q
Q
Q
Q
Q
110
INLE
lID
lID
110
110
110
110
GND
U
I-
U
oo::lUUOO
~~OZ>~~
4
3 2
1 28 2726
5
25
24
6
23
22
21
10
11
DE
Q
Q
Q
NC
Q
Q
Q
12 13 14 151617 18
0 0 0 UIWIW 0
::::::::::ZZO~::::,
<:l
_
T1BPALT19RB'
JW OR NT PACKAGE
TIBPALT19RB'
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
OUTCLK
110
110
110
110
110
I/O
GND
'"--'U
VCC
110
Q
Q
Q
Q
Q
Q
Q
Q
INLE
DE
IU
oo::JUUQ
::::::::::02>::::0
4
3 2
1 282726
21
10
11
Q
Q
12131415161718
0 0 0 UIWI W 0
:::::;:;;;zzo~
<:l
_
Pin assignments in operating mode
2-350
NC-No internal connection
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Q
Q
Q
NC
Q
TlBPAL T19L8C, TIBPALT19R4C
HIGH·PERFORMANCE LATCHED·INPUT PAL@ CIRCUITS
functional block diagrams (positive logic)
'PAlT19l8
EN"1'IJ~_ _ _
&
O
~---O
b-_......_I/O
b--.+-+_ 1/0
~-'+-+_I/O
b-~""'_I/O
b-~""'_I/O
'PAlT19R4
OE--------------------------------~
OUTCLK--------------------------------4>
,1----
Q
I--t--i-~--
Q
b-....----.....- I - -
I/O
b-......l---o_-I--- I/O
b-....+---...-+--
I/O
b-....+---....-+--
I/O
4
4
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2·351
TIBPALT19R6C, TlBPALT19R8C
HIGH·PERFORMANCE LATCHED·INPUT PAL@ CIRCUITS
functional block diagrams (positive logic)
'PALT19R6
a
a
a
a
a
a
1--.....sz.f>""'~-+-...-T-"O
P-~-+....- t - I / O
6
'PALT19RB
8
2·352
TEXAS . "
INSfRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TlBPALT19L8C
HIGH·PERFORMANCE LATCHED·INPUT PAL@ CIRCUITS
logic diagram (positive logic)
1(1)
INCREMENT
I
1/0@..~2f! tt=t~~~~:H~~~~~~=itit=iiit=f~~~==~~
12
16
20
24
28
32
36 '
'0
2D
MO
MO
M'
M'
2432
2433
~
L.
~
ACTUAL
FUSE NUMBER
FIRST
FUSE NUMBERS
g~
7.
(22)0
"'
152
190
~~
I/O !:!LfpD,g.2
MO
M'
2434
f1D
I/D~
1M02~2
M1
2435
I/O
(5)
=-
304
342
3.0
tt "
4'.
456
2D
~
684
~~
912
120)
)
950
988
~rN~
~r-2 ::::
1'0'10
1254
Ml
g:
2437
1
I/O
570
608
646
2436 ~g::
I/O
(21)
532
frIJ~
,~~2 m
MO
M1
J
494
119)
I/O
I/O
~
1292
>-)
118)
J
117)
I/O
(7)~~
,'{',2 m~
'
I/O,
-
_
110
2D
1520
MO
1558
M1
1596
2438
1634
1672
~ft2
tt "
@..[NJ- ::::
:
f~
~;~~
_ 2439 ~i~:
I/D~~~g.2
::::
MO
2168
1'0'11
2204
(16)
1
2440 ~~:~
(15)
I/O
I/O
0
'(101~~
'2D~ 2 m:
1/0-
MO
M'
2441
I/O
(.!!1l},g,2
MO
M'
LE~~2_4_42__+--_____
A_C_T_U_A_L_F_U_SE__N_U_M_B_E_R_S__________________________________________~-<~(~14)INLE
V
Fuse Number
= First Fuse Number
~3)1
+ Increment
Pin numbers shown are for JW and NT packages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-353
TIBPALT19R4C
HIGH·PERFORMANCE LATCHED·INPUT PAL@ CIRCUITS
logic diagram (positive logic)
OUTCLKL(l~)~==============================================================~~
.
INCREMENT
i
liD
~ntr='g.,
M.
4
12
8
16
20
24
28
32
\
;J
'C'02
0
~
~
ACTUAL
FUSE NUMBER
~~
76
11.
)
i;2 :;
~
Ml
2434
~ )
380
:~:
rttJ =
I/D~ ~'
Ml
110
2435
~:~
")-
798
MO
988
./
r1iJ
rJ~
19.' ~~
OC2
~
MO
Ml
2437
110
110
110
ill
1216
1264
1292
1330
MO
, ...
Ml
1596
2438
~:~
>-
~
~
Ml
2204
2242
(19)
b.
J
2280
I/D(.!!!J~~
f iii:
(17)
rv""
!P~
~ ~~
:;9 !~ !
2168
c,
c,
1~15
MO
c,
~~
l!!tin Hi:
2440
~
iJ.
[V"
.5O
2436 ;:::
lID!!!.
ei~)
Q
c,
~IJIf/ :::
~
H:
M1
1/0
J
53'
.7'
684
1/0
(211
494
"='
_
(22)
~
l~
UI
ffi
110
2432
2433
110
(23)
MD
M,
FIRST
FUSE NUMBERS
L.
36
(16)
(15)
J
Q
Q
Q
110
110
M'
2441
110
(!lliJ'~'
MD
M'
~________________________________________________________________
2442+-ACTUAL FUSE NUMBERS
~~/1~(14)ffiIT£
~
~)OE
Fuse Number = First Fuse Number + Increment
Pin numbers shown are for JW and NT packages.
2-354
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPALT19R6C
HIGH·PERFORMANCE LATCHED·INPUT PAL@CIRCUITS
logic diagram (positive logic)
OUTCLK (1)
.
INCREMENT
I
1/0
~
~
4
12
8
16
20
,
24
28
32
lC'
'0
MO
(23),
lC'
'0
MO
Ml
~
ACTUAL
FUSE NUMBER
L-. 7.
11.
l
152
190
(22)
J
~
~r
0C2
~
lC'
2D
304
MO
342
Ml
380
2434
":'
---'----
--\.)----
:~:
494
fhl1~) a
Cl
~00'
lC'
2D
MO
Ml
608
...
684
2435
722
7.0
F~
ftfj":'
798
20
2436
912
950
988
~g::
1102
fIV'"
00'
I/O,~
1216
1254
1292
2437
1330
-=-
2D
1520
1558
2438
1634
Ml
r- ~
1596
~~~~
OC2
1788
lC'
_
20
1824
MO
1862
Ml
1900
2439
1938
1976
~
~r
110,~
OC,
lC'
2D
-::
,~
II o
2128
2188
Ml
2204
2242
2280
2318
2440
~
jf
00'
~I a
-
tbtj ~)
a
Cl
2090
MO
~) a
Cl
~.-
,@!.
110
~
1482
MO
-=-
J-
Cl
~r
lC'
~
~19) a
Cl
'H
1368
1406
OC2
>-
1178
lC'
20
MO
Ml
:[!,J20) a
Cl
87'
00'
lC'
MO
Ml
":'
I/O,ill.
I/O
..-1
570
110.~
10
2432
~ 2433
FIRST
FUSE NUMBERS
00
38
I/O,~
J
,
Ml
110
36
'394
lC2
'0
~
(IS)
I
1/0
~~
,11
2441
(111
110
lC2
20
MO
Ml
,
_ 2442 _ _ ACTUAL FUSE NUMBERS -
(1
l(jm
Fuse Number = First Fuse Number + Increment
Pin numbers shown are for JW and NT packages.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-355
TIBPALT19R8C
HIGH·PERFORMANCE LATCHED·INPUT PAL@CIRCUITS
logic diagram (positive logic)
OUTCLK (1)
INCREMENT
,
A
i
110
@.
~.
4
12
8
16
20
24
28
32
oc,
36
J
(23)
1C'
'0
MO
102
20
~ :33
2432
ACTtAL ~
FUSE NUMBER
FIRST
FUSE NUMBERS
L-~
".7.
~
152
19Q
QfJ~
oc,
liD @!.
1C,
ZD
304
MIt
342
Mt
380
2~34
!&
C1
608
MO
646
M1
684
Nil
2436
110 ~
110
.!Z!.
874
912
950
988
1026
1064
OC2
,C,
2D
1178
MO
1254
1216
Ml
1292
2437
1330
DC2
1482
t> ~ I.lrv-
(18
lI'=
1C'
_
20
MO
1520
1568
Ml
1596
1634
1672
2438
!!!l
t> ~ ~
P
~'"
DC2
110
C1
1C2
2D
...
102
~
Ml
C1
1786
~
1824
1862
1900
_ 2439 ~;~:
110
"">-
r#J~
DCZ
110 ~
~o
~
D- ~
~
~fr
~f
oel
110 ~
')-
~~~
2435
C,
~
f#.J~
DC'
'C2
20
~~
t>- ~
:~
570
110
110
M'
1C'
20
(!I!)
3=\
2090
2128
MID
2168
Ml
2204
2242
h
~t
DC2
1C2
20
~
~
C1
2394
~
b
115
I"V"'"
MO
M1
2441
liD
iJ
(!!!
1C'
'0
MO
M1
~ 2442 -
I~31Of
ACTUAL FUSE NUMBERS
(1
1141mu
Fuse Number = First Fuse Number + Increment
Pin numbers shown are for JW and NT packages.
2·356
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL T19L8C, TlBPAL T19R4C, TIBPALT19R6C, TIBPALT19R8C
HIGH-PERFORMANCE LATCHED-INPUT PAL@ CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during preload cycle.
recommended operating conditions
VCC
Supply voltage
VIH
VIL
High-level input voltage
IOH
High-level output current
MIN
4.75
2
Low-level input voltage
low-Jevel output current
IOL
fclock Clock frequency
OUTCLK
INLE low
tw
OUTCLK high
Pulse duration
OUTCLK low
Data before INLE !
tsu
Setup time
Data before OUTCLKt
INLE low before OUTCLKt (See Note 21
Data after INLE !
th
Hold time
TA
Operating free-air temperature
Data after OUTCLKt
0
15
15
15
10
25
30
5
0
0
NOM
MAX
5
5.25
5.5
0.8
-3.2
24
30
UNIT
V
V
V
mA
mA
MHz
ns
ns
ns
70
°c
NOTE 2: This setup time ensures the output registers will see stable data from the input latches.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-357
TIBPAlT19l8C. TlBPAlT19R4C. TlBPAlT19R6C. TIBPAlT19R8C
HIGH·PERFORMANCE lATCHED·INPUT PAl@ CIRCUITS
electrical characteristics over recommended free-air operating temperature range
PARAMETER
TEST CONDITIONS
VIK
Vee - 4.75 V,
VOH
Vee
VOL
Vee
Outputs
10ZH
I/O ports
Outputs
110 ports
10Zl
OE Input
II
All others
OE Input
=
=
4.75 V,
10H
4.75 V,
10l
= -3.2 rnA
= 24 rnA
Vee
=
5.25 V,
VIH
=
2.7 V
Vee
=
5.25 V,
VIH
=
0.4 V
Vee
=
5.25 V,
VI
=
40
2.7 V
Vee
=
5.25 V,
VI
=
0.4 V
10*
Vee
=
5.25 V,
Vo
ICC
Vee = 5.25 V,
Outputs open
= 2.25 V
= OV,
20
-0.4
-0.2
-30
150
UNIT
V
V
0.5
0.2
0.1
=
VI
0.35
5.5 V
VI
All others
3.3
-250
5.25 V,
III
2.4
MAX
-1.5
100
-20
=
All others
OE Input
Typt
20
Vee
IIH
MIN
-18 rnA
II -
V
p.A
p.A
rnA
p.A
rnA
-125
rnA
210
rnA
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
f max
Typt
MAX
1/0,0
15
25
ns
I/O§
1/0,0
25
40
ns
INlE!
OUTelKt
110,0
Q
28
40
20
ns
10
14
20
ns
25
ns
30
40
ns
30
40
ns
ns
ns
FROM
ted
OUTelKt
1,110
ted
ted
ted
TO
TEST CONDITIONS
Q
MIN
30
Rl
=
=
=
500 Il,
UNIT
MHz
10
ns
'en
ten
OEI
Q
1,110
110,
ten
I/O§
110,0
ten
INlEI
110,
tdis
OEt
1,1/0
Q
11
110,0
12
20
25
a
a
14
25
ns
14
25
ns
tdis
tdis
I/O§
110,
tdis
INlEI
1/0,
t All typical values are Vee
=
5 V, TA
=
R2
a
el
500 Il,
50 pF,
See Figure 1
a
25°C.
:t: The output conditions have been chosen to produce a current that closely approximates one half the true short-circuit current, lOS§ Input configured as an input buffer or INLE low.
2-358
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIBPALT19L8C. TIBPALT19R4C. TlBPALT19R6C. TIBPALT19R8C
HIGH·PERFORMANCE LATCHED·INPUT PAL@CIRCUITS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Note 3)
Step
Step
Step
Step
Step
Step
Step
1
Pin 13 to VIH, Pin 1 to VIL. and VCC to 5 volts.
Pin 14 to VIHH
At Q outputs, apply VIL to preload a low and VIH to preload a high.
Pin 14 to VIL.
Remove the voltages applied to the outputs.
Pin 13 to VIL
Check the output states to verify preload.
2
3
4
5
6
7
preload waveforms (see Note 3)
5V
vcc
ov
J
OUTPUTS DISABLED
VIH
VIL
tdis
vlHH
--1++!
------,--
VOL
ENABLE PRELOAD
I
I
I
I
100 ns
MIN
I
I
I
I
t--' w1 ---+1 VIH
~I
I
I: I
>--<
I(
XXXXXXXXX)
I
I
\
: ~
VIL
Q
~'en
I
PIN 14 (lNCLKI
VOH
~
(
PIN 13 (DEI
VERIFY
I
I
VIL
xm:
security fuse programming (see Note 3)
DJ.J5 ov
vcc~
~~~
I
:
j.-'h"[ r--\,-------------- -------,------ 16V
PIN 1 _ _ _ _I:......_..:;V
\
' 0V
I
I..t w3...1
:
k-I 'h-j J----\.j.th.j-- - - -- 16 V
-:JV
P'N 13 _~ _ _ _ _ _ _ _ _ _ _ _
\'
,
0 V
NOTE 3: Pin numbers shown are for JW and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-359
TlBPALT19L8C, TIBPALT19R4C, TlBPALT19R6C, TIBPALT19R8C
HIGH·PERFORMANCE LATCHED·INPUT PAL@ CIRCUITS
PARAMETER MEASUREMENT INFORMATION
SV
Sl
L
Rl
FROM OUTPUT
UNDER TEST -
...-
. .-
TEST
POINT
. .-
CL
(See Note AI
R2
LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
TIMING
INPUT
/.
----~--- ---0.3V
1SV
1SV
~
.
.
---3.SV
3.S V
7,l.SV
HIGH-LEVEL
PULSE
Ltw--..l
I4-th~
1
~t.u+t
.
~~-;;-:;3.SV
DATA
INPUT~l.SV
~
1
LOW-LEVEL
PULSE
I
1 SV
1SV
~
.
.
0.3 V
.!II1.S V
----"
tpd I.
~I
1
I
\1~ ~ I.
I.
tpd
OUT-OF-PHASE
OUTPUT
(See Note 01
I.
VOLTAGE WAVEFORMS
PULSE DURATIONS
- - 3.S V
0.3 V
~I tpd
r------i:-""""'I+ - -
:1 f1.5V 1
IN-PHASE
OUTPUT
~I
1
~
14
~
'\l.S V
.
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
I
OUTPUT
CONTROL
(low-level
enablingl
~3.5V
1.5 V
I
ten~
VOL
tpd
--VOL
-1- - - - -- 0.3
I+-
11
WAVEFORM 1
Sl CLOSED
(See Note Bt
WAVEFORM 2
S10PEN
(See Note Bt
1.5 V
I
1
VOH
l;;/OH
.
3.SV
----0.3V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
0.3V
1
V
~ ~tdis
11
-33 V
1 1.S V
III-'
~VOL + 0.5 V
~
I
-=
=
-= VOL
ten-+! J+...., .... tdis l.
~
I_--i.-VOH
I
-
1.S V
-
LVOH-0.5 V
~O V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten,S pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR oS 1 MHz, tr = If = 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch 51 is closed.
FIGURE 1
2-360
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
T1BPLS506C
13 x 97 x 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
03090. DECEMBER 19B7 - REVISED NOVEMBER 1989
•
•
•
•
•
•
•
•
JT OR NT PACKAGE
ITOPVIEW)
50-MHz Max Clock Rate
2 Transition Complement Array Terms
ClK
16-Bit Internal State Registers
VCC
)0
11
12
13
14
15
00
01
02
03
8-Bit Output Registers
Outputs Programmable for Registered or
Combinational Operation
Ideal for Waveform Generation and HighPerformance State Machine Applications
Programmable Output Enable
Programmable Clock Polarity
16
17
18
19
110
111
112/0E
07
06
05
04
GND
description
FK OR FN PACKAGE
(TOP VIEW)
The TIBPLS506 is a TTL field-programmable
state machine of the Mealy type. This state
machine (logic sequencer) contains 97 product
terms (AND terms) and 48 sum terms (OR
terms). The product and sum terms are used to
control the 16-bit internal state registers and the
8-bit output registers.
4 3 2
The outputs of the internal state registers
(PO-P15) are fed back and combined with the 13
inputs (10-112) to form the AND array. In
addition, two sum terms are complemented and
fed back to the AND array, which allows any
product terms to be summed, complemented,
and used as inputs to the AND array.
12
13
14
5
NC
8
6
1 282726
25
24
23
9
22
21
10
20
11
19
12131415161718
"',""OUq-It)Ul
OOzzOOO
t!)
NC - No internal connection
The eight output cells can be individually
programmed for registered or combinational
operation. Nonregistered operation is selected by
blowing the output mUltiplexer fuse. Registered
output operation is selected by leaving the
output multiplexer fuse intact.
Pin 17 can be programmed to function as an input andlor an output enable. Blowing the output enable
fuse lets pin 1 7 function as an output enable but does not disconnect pin 1 7 from the input array. When
the output enable fuse is intact, pin 17 functions only as an input with the outputs being permanently
enabled.
The state and output registers are synchronously clocked by the fuse programmable clock input. The clock
polarity fuse selects either postive- or negative-edge triggering. Negative-edge triggering is selected by
blowing the clock polarity fuse. Leaving this fuse intact selects positive-edge triggering. After power-up,
the device must be initialized to the desired state. When the output multiplexer fuse is left intact, registered
operation is selected.
The TIBPLS506C is characterized for operation from OOC to 75°C.
UNLESS OTHERWISE IOTED this documont contains
PRODUCTIOII DATA information currant a• •,
publicatiDn dllte. Products cDnform to spacificltioRI
per the tanns of TaXI. Instruments stl.dard
:=':t.:-:~U-::D:lr~=.::.- not RlCessarily
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright @ 1989, Texas Instruments Incorporated
2-361
TIBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
logic diagram (positive logic)
r--Sllil9wnN II\IIIU .. ONIf .• - - - ,
0:.
III
~
~
2
:!::
0990L
....
....
Ol9&
0698
OZlt
OL8!
.......,
....
OBLe
."'.
GUS
-....
OZgE:
OL .. £
....
•m
.. ""
...."
NOTES: A. All inputs to AND gates, exclusive-OR gates. and multiplexters with a blown link assume the logic-1 state.
B. All OR gate inputs with a blown link assume the logic-O state.
2·362
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIBPLS506C
13 x 97 x 8 FIELD· PROGRAMMABLE LOGIC SEQUENCER
logic diagram (continued)
8
II
~
8
8
&
~;:. ~ ~~ ~ ~ ~ ~~ ~ ~;:. ~ ~:. ~ ~;:. ~ ~;:.~
=r-
ffi ;. ~,
8
:t'
m$ , "
,iiiliiiii
Qj) )l~ £~IJ ll~ QIJ lQ £ J lll~ l~l Illl l~l
ll~ 1~/J lO l~l
:
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
~
Ill~ l~l
QIl
~
~ ~
I
2-363
TlBPLS5D6C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
S-R FUNCTION TABLE (8e8 Note ·11
ClK POLARITY FUSE
ClK
INTACT
INTACT
f
f
f
f
BLOWN
S
l
R
l
L
H
L
H
H
l
H
H
INDETERMINATE
j
L
l
BLOWN
BLOWN
j
l
H
j
BLOWN
j
H
H
H
00
l
H
INDETERMINATE
INTACT
INTACT
NOTE 1:
"00 is the state
l
STATE REGISTER
00
of the S-R registers before the active clock
edge.
functional block diagram (positive logic)
ClK -------\~.........
~------------------~
16
2
;,,1
97.50
16
8.MUX
.------1;G1
EN
10-111
8
11210E
''\..J
2-364
8
denotes fused inputs.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • O.Allo1\S., TEX·AS 75265
'il 8
00-07
TIBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEOUENCER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to disabled output (see Note 2) ................................... 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 75°C
Storage temperature range .......................................... - 65°C to 1 50°C
NOTE 2: These ratings apply except when programming pins during a programming cycle or during diagnostic testing.
recommended operating conditions
VCC
Supply voltage
VIH
High-level input voltage, VCC - 5.25 V
VIL
Low-level input voltage.
IOH
High-level output current
IOl
Low-level output current
Vee
th
Hold time after ClK
TA
Operating free-air temperature
MAX
UNIT
5
5.25
V
5.5
V
0.8
= 4.75 V
Clock high
Clock low
Setup time before elK t input or feedback to SMA inputs
tsu
NOM
2
Pulse duration
tw
MIN
4.75
With C-array
25
at S-A inputs
16
mA
ns
6
15
Input or feedback
mA
6
Without C-array
V
-3.2
ns
0
ns
75
0
°C
tThe active edge of elK is determined by the programmed state of elK polarity fuse.
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VIK
VCC = 4.75 V,
II = -18 mA
VOH
VCC = 4.75 V,
IOH = -3.2 mA
VOL
VCC - 4.75 V,
II
VCC = 5.25 V.
IOl - 16 mA
VI = 5.5 V
MIN
TYP*
2.4
3
0.37
MAX
- 1.2
UNIT
V
V
0.5
V
0.1
mA
IIH
VCC = 5.25 V.
VI=2.7V
20
~A
III
IO§
VCC = 5.25 V.
VI = 0.4 V
-0.25
mA
VCC = 5.25 V.
Vo = 0.5 V
-130
mA
IOZH
VCC = 5.25 V.
Vo = 2.7 V
20
~A
IOZl
VCC = 5.25 V.
Vo = 0.4 V
-20
~A
ICC
Ci
VCC = 5.25 V.
See Note 3.
210
mA
f = 1 MHz.
VI = 2 V
7
pF
Co
f = 1 MHz.
Vo = 2 V
11
pF
Cclk
f = 1 MHz.
VI = 2 V
14
pF
-30
Outputs open
156
*AII typical values are at VCC = 5 V. TA = 25°C.
§This parameter approximates lOS- The condition Va = 0.5 V takes tester noise into account. Not more than one output should be shorted
at a time and duration of the short circuit should not exceed one second.
NOTE 3: When the clock is programmed for negative-edge, then VI = 4.75 V. When the clock is programmed for positive-edge, then VI = O.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-365
·TIBPLS506C
13 x 97 x 8 FIELD-PROGRAMMABLE· LOGIC SEOUENCER
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
tpd§
Typt
50
65
With C-array
33
50
TO
fmax*
tpd§
MIN
Without C-array
FROM
ClKi
TEST CONDITIONS
ClK!
Q (registered)
ClK.
tpd
I or Feedback
Q (nonregistered)
ten
OE.
Q
tdis
OEi
Q
tAll typical values are at VCC
=
5 V. TA
=
= 300 II.
27
R2 = 390 II.
See Figure 3
9
28
3
10
Cl
=
5 pF
UNIT
MHz
8
R1
Q (nonregistered)
ClK.
MAX
ns
ns
4
11
10
22
ns
2
6
10
ns
2
6
10
ns
25°C.
1
tfmax, with external feedback, can be calculated as
elK
Q' f max is independent of the internal programmed configuration
and the number of product terms used.
tsu + tpd
to
§The ac.tive edge of eLK is determined by the programmed state of the elK polarity fuse .
2-366
.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TlBPLS506C
13 x 97 x 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
(J)
timing model
o
Dedicated inputs
Output pin
t m in(2j min clock period for this path
INTERNAL SRs
Feedback Lines
t 5u (a) I to internal S or
R.
Data
through C array
t m in(3) min clock period, this path
t 5u (2) I to internal S or R
CLK INTERNAL
OUTPUT
SRs
t m in(1) min clock period, this path
t pd(31 elK INTERNAL to output response
tsu(b) or tmin(c)
Ipdlbl or Ipdlcl
Ipdl21 CLK 10 Q pin
tsu( 1) I to Output S or R
tpd( 1) I to output pin
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-367
TIBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE .LOGIC SEQUENCER
glossary-timing model
tpd( 1) - Maximum time interval from the time a signal edge is received at any input pin to the time any
logically affected combinational output pin delivers a response.
tpd(2)' - Maximum time interval from a positive edge on the clock input pin to data delivery on the output
pin corresponding to any output SR register.
tpd(3)' - Maximum time interval from the positive edge on the clock input pin to the response on any
logically affected combinationally configured output (at the pin), where data origin is any internal
SR register.
tpd(b) - Maximum time interval from the time a signal edge is received at any input pin to the time any
logically affected combinational output pin delivers a response, where data passes through a
C ARRAY once before reaching the affected output.
tpd(c)* - Maximum time interval from the positive edge on the clock input pin to the response on any
logically affected combinationally configured output (at the pin), where data origin is any internal
SR register and data passes once through a C ARRAY before reaching an affected output.
tsu( 1) - Minimum time interval that must be allowed between the data edge on any dedicated input
and the active clock edge on the clock input pin when data affects the S or R line of any output
SR register.
tsu(2) - Minimum time interval that must be allowed between the data edge on any dedicated input
and the active clock edge on the clock input pin when data affects the S or R line of any internal
SR register.
tsu(a) - Minimum time interval that must be allowed between the data edge on any dedicated input
and the active clock edge on the clock input pin when data passes once through a C ARRAY
before reaching an affected S or R line on any internal SR register.
tsu(b) - Minimum time interval that must be allowed between the data edge on any dedicated input
and the active clock edge on the clock input pin when data passes once through a C ARRAY
before reaching an affected S or R line on any output SR register.
tmin( 1) - Minimum clock period (or 1/[maximum frequency]) that the device will accomodate when using
feedback from any internal SR register or counter bit to feed .the S or R line of any output SR
register.
t m in(2) - Minimum clock period (or 1/[maximum frequency]) that the device will accomodate when using
feedback from any internal SR register to feed the S or R line of any internal SR register.
t m in(3) - Minimum clock period (or 1/[maximum frequency]) that the device will accomodate when using
feedback from any internal SR register to feed the S or R line of any internal SR register and
data passes once through a C ARRAY before reaching an affected S or R line on any internal
SR register.
tmin(c) - Minimum clock period (or 1/[maximum frequency]) that the device will accomodate when using
feedback from any internal SR register to feed the S or R line of any output SR register and
data passes once through a C ARRAY before reaching an affected S or R line on any output
SR register.
2-368
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
TIBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
PARAMETER VALUES FOR TIMING MOOEL
Ipdll) ~ 22 ns
I p d(2)' ~ 10 ns
I p d(3)' ~ 27 ns
I m in(l)
~
20 ns
~
25 ns
I m in(2)
I m in(3)
~
20 ns
25 ns
Isulb) ~ 25 ns
Imin(c)
~
25 ns
Isull)
Is u (2)
~
~
15 ns
15 ns
Isul a )
~
INTERNAL NOOE NUMBERS
00-07
RESET 25-32
CO
Cl
65
66
SET 33-48
PO-PI5
RESET 49-64
diagnostics
A diagnostic mode is provided with these devices that allows the user to inspect the contents of the state
registers_ The step-by-step procedures required to use the diagnostics follow.
1. Disable all outputs by taking pin 17 (OE) high (see Note 4).
2. Take pin 8 (00) double high to enable the diagnostics test sequence.
3. Apply appropriate levels of voltage to pins 11 (03). 13 (04). and 14 (05) to select the desired
state register (see Table 1).
The voltage level monitored on pin 9 will indicate the state of the selected state register.
NOTE 4: If pin 17 is being used as an input to the array, then pin 7 (5) must be taken double high before pin 17 is taken high.
diagnostics waveforms
15 _ _ _ _ _. . J / , . - - - - - - - - - - - - - - - - - - - - - - VIHH
(PIN 7)
.
1
OE
r------------------------VIH
(PIN 17) _ _ _ _-J~
~100ns~ ,._ _ _........
-:J
~~ Z7727"l';,"'j ?;,r"ry,777h"I'2"""Wj///!//JlIf
"I
tPIN
- -- -- -- -- - - - - - -- - -
VIHH
\- - - - - - - - - - - - ~:~
j.-l00 ns-+f
03.04.05
(PINS 11.
_ j(~-------------VOHH
13.14)Wl/J//I/I11!//////////////////;1~--1
- - - -- - - - -- -- -- -VOH
VOL
1+--100 ns--+l
IPIN~~1I/I///////J//////I///I//J//////I///II/I/J/////&,"'1;,,.,.,I'h,.,.,I'h..,..,I'h,.,.,1;,..,..,I'h..,..,7h""'1;''''''''/h"T"1Z~~~
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
2-369
TlBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEOUENCER
TABLE 1. ADDRESSING STATE REGISTERS
DURING DIAGNOSTICS t
REGISTER BINARY ADDRESS
BURIED REGISTER
PIN 11
PIN 13
PIN 14
L
L
L
Cl
L
L
L
L
H
HH
CO
L
H
H
H
HH
HH
HH
L
L
L
L
L
H
H
H
H
H
H
H
H
H
tVIHH
=
SELECTED
P15
L
P14
H
HH
PO
Pl
L
P2
H
HH
P3
P4
L
L
P5
L
H
HH
P6
L
P8
L
H
H
H
HH
HH
HH
P7
H
HH
Pl0
L
Pll
H
HH
P13
P9
P12
10.25 V min, 10.5 V nom, 10.75 V max
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
reasonably priced device programmers.
Complete programming specifications, algorithms, and the latest information on firmware, software, and
hardware updates are available upon request. Information on programmers that are capable of programming
Texas· Instruments programmable logic is also available, upon request, from the nearest TI sales office,
local authorized Texas Instruments distirbutor, or by calling Texas Instruments at (214) 997·5666.
2·370
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
TYPICAL APPLICATIONS
f max
When the TIBPLS506 is used with two or more devices linked to build a "multi-device" state machine
(see Figure 1). the maximum operating frequency for this state machine is limited to the sum of tpd CLK-Q
(10 ns) of the first '506 and tsu (15 ns), of the second '506, for a clock period of 25 ns. This results
in an f max of 40 MHz (1/25 ns).
CLK (40 MHz)
[1>'506
ll>'506
OUTPUT
DATA
OATA
Ipd ClK-Q
I4----- l su
~
Ipd ClK-Q
~
~
Isu
~
~25 ns----l+~--25 ns~
FIGURE 1
Figure 2 shows the '506 used in a system environment where it is operated at 50 MHz, the highest clock
rate possible without compromising data integrity. At the input of the '506, the system clock period is
limited to the sum of tpd CLK-Q of device A and tsu of the '506. At the output of the '506, the system
clock period is limited to the sum of tpd CLK-Q of the '506 and tsu of device B.
For this system to operate at 50 MHz, a system clock period of 20 ns must be met. Given that tsu for
the '506 is 15 ns minimum, tpd CLK-Q of device A cannot exceed 5 ns (15 ns + 5 ns = 20 ns). On the
output side of the '506, tpd CLK-Q of 10 ns must be allowed. In order to meet the system clock period
of 20 ns, tsu for device B must not exceed 10 ns (10 ns + 10 ns) = 20 ns). Under these circumstances,
a system frequency of 50 MHz (1/20 ns) can be realized.
ClK
(50 MHzl
Lt> 506
A
B
DATA
OUTPUT
Ipd ClK-Q'
14
"14
I+----
Ipd ClK-Q
Isu
15 ns
20 ns
~
10 ns
~
~
Isu'---.t
20 ns
------.t
* External device parameters (tpd CLK-Q of device A .s; 5 ns, and tsu of device B
:s
10 ns)
FIGURE 2
TEXAS
"!1
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-371
T1BPLS506C
13 x 97 x 8 FIELD-PROGRAMMABLE LOGIC SEOUENCER
PARAMETER MEASUREMENT INFORMATION
5V
Sl
I.
Rl
fROM OUTPUT _ ...._ ..._ ..._
UNDER TEST
TEST
POINT
R2
CL
ISee Note AI
LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
./.
TIMING
;rl.5V
INPUT _ _ _--'U _ _ -
---0.3 V
1 5 V
15 V
~
.
.
---3.5V
3.5 V
HIGH· LEVEL
PULSE
I
I4-th-+t
I
DATA
~~-;::3.5V
INPUT - - . / ' 1.5V~
0.3 V
1
LOW· LEVEL
PULSE
\1~ ~ -
.!I1;5 V
----"
tpd
I
IN·PHASE
OUTPUT
tpd
OUT-Of-PHASE
OUTPUT
ISee Note DI
1
14
tpd
r---::----.+ - - VOH
1
~
:
f1.5V
1
14.1
1
14
,\1.5 V
.
VOLTAGE WAVEFORMS
PROPAGATION DelAY TIMES
NOTES:
- - 3.5 V
0.3 V
~I
I
~I
VOL
OUTPUT
CONTROL
Ilow-ievel
enabling I
~3.5V
1.5 V
I
1
ten ---+I
I+-
!
- - VOL
1.5 V
I
-1- - -
-
- - 0.3 V
-+I I+-- tdis
:
~3.3
1
1
V
WAVEFORM1--r\: 1.5V
II~vOL+0.5V
Sl CLOSED
I ~-==:!-= VOL
ISee Note BI
'en -.I
14- 'dis
WAVEFORM 2
S10PEN
.
---..!
l.
I-_-_-~-=
~
ISee Note BI
I
1.5 V
VOH
LVOH-0.5 V
~
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE·STATE OUTPUTS
A. CL includes probe gnd jig capacitance and is 50 pF for tpd and ten. 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR :s 1 MHz, tT = tf = 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch 51 is closed.
FIGURE 3
2-372
3.5V
- - --0.3V
i+-
tpd
FVOH
.
I
VOLTAGE WAVEfORMS
PULSE DURATIONS
I.
14.1
1
1 5 V
15 V
~
.
.
VDLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
0.3 V
1
!.--tw--+l
I4- t su-+j
TEXAS
~
INSTRUMENTS
POST OFFICE BOX '655303 • DALLAS, TEXAS 75265
TIBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
200
-- -
175
~
,.
150
I
/
~
c:
I!!
125
:;
c;.
Vee = 5.25 V /
100 - V e e = 5V I
Q.
Co
::I
en
I
u
9
t:--
l'
/
Vee = 4.75 V
75
50
25
o
o
25
50
75
T A - Free-Air Temperature - De
FIGURE 4
POWER DISSIPATION
vs
FREQUENCY
1000
950
~
E 900
I
c:
--
0
.~
Co
'wIn 850
.,
i--""
TA - oDe
C
........ i--""
~
~
800
0
TA - 25 De
~
--
1 I
750
TA - 50 De
I I
700
1
2
4
7
10
20
~
....
i--""~
40 70
100
F-Frequency-MHz
FIGURE 5
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-373
TIBPLS506C
13 x 97 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
TYPICAL CHARACTERISTICS
PROPAGATION DELAY
vs
LOAD CAPACITANCE
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
20
30 VCC = 5 V
R1 = 300!l
18
16
tPH~ (I or F~edbacJ to 01
E 14
tPLH (I Or Feedback to 0)
III
25
III
t:
..E
t:
I
a,
i=
.
0;
0
>-
10
o-m
.2
1ii
8
.,
Co
6
c:
.'"
~
D.
20~---r~~~~
i=
>- 12
15r-~-r--~~~-t~~.
c:
o
tPLH (CLK to 0) -
4
2
o
.
~ 10~-.~~--+----+----+----+---;
Co
tPHL (CLK to 0)
R1 = 300!l
R2 = 390!l
CL=50pF
TA = 25°C
£.
5~---r---4----+----r---,~~
O~
4.75
__
o
5.25
5
~
__
~
100
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
I
I
tpLH (I or Feedback to 0)
E
i= 12
-
III
16
..E
14 C-tPLt (I o! feelack
c:
I
i=
>-
>-
.
~
600
fa
0)
12
ID
.0 10
0;
10
.,.
8
0
..,
8
'"
6
D.
4
0
c:
tPLH (CLK to 01-
o
.'"
~
D.
R1 - 300 !l
R2 = 39011
CL - 50 pF
o
0
Co
tpHL (CLK 0)
VCC = 5 V
2
25
50
75
tPLH (CLK to 0)
6
VCC - 5 V 4 R1 - 300!l
R2 = 39011
2 CL-50pF
0 TA = 25°C
o
TA -Free-Air Temperature- °C
2
' - - - tPHL%(CLK+to 0) I - -
3
4
5
6
Number of Outputs Switching
FIGURE 9
FIGURE 8
2-374
__
tpHL (I or Feedback to 0)
-=
.!!!
~
~
500
18
I
tpHL (I or Feedback to 0)
16
I
co 14
Co
__
20
18
...
~
400
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
20
c:
____
300
FIGURE 7
FIGURE 6
c:
~
CL -Load Capacitance-pF
VCC-Supply Voltage-V
III
__
200
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
7
8
TIBPSG507M, TlBPSG507C
13 x 80 x 8 PROGRAMMABLE SE~UENCE GENERATOR
03029. MAY 19B7 - REVISED NOVEMBER 19B9
M SUFFIX ... , JT PACKAGE
C SUFFIX .... JT OR NT PACKAGE
•
58-MHz Max Clock Rate
•
Ideal for Waveform Generation and HighPerformance State Machine Applications
•
6-Bit Internal Binarv Counter
•
8-Bit Internal State Register
•
Programmable Clock Polarity
•
Outputs Programmable for Registered or
Combinatorial Operation
•
6-Bit Counter Simplifies Logic Equation
Development in State Machine Designs
•
Programmable Output Enable
(TOP VIEW I
ClK
VCC
10
16
17
18
19
110
111
112/0E
07
06
05
04
13
14
15
00
01
02
03
GND
M SUFFIX . . . . FK PACKAGE
C SUFFIX .
. FK OR FN PACKAGE
description
The TIBPSG507 is a 13 x 80 x 8 Programmable
Sequence Generator (PSG) that offers the
system designer unprecedented flexibility in a
high-performance field-programmable logic
device. Applications such as waveform
generators, state machines, dividers, timers, and
simple logic reduction are all possible with a PSG.
By utilizing the built-in binary counter, the PSG
is capable of generating complex timing
controllers. The binary counter also simplifies
logic equation development in state machine and
waveform generator applications.
The PSG507 contains 80 product (AND) terms,
a 6-bit binary counter with control logic, eight
SIR state holding registers, and eight outputs.
The eight outputs can be individually
programmed for either registered or
combinatorial operation. The clock input is fuse
programmable for either positive- or negativeedge operation.
(TOP VIEWI
4
6
7
8
01
3
2 1 28 27 26
25
24
23
18
19
110
22
NC
9
21
10
11
20
19
111
112/0E
07
121314151617 18
",<'lOU",""''''
OOzzOOO
10-1 11
1121OE
f+-- 'U
1CT-0
1R
~ 'U
~
'-----
12
1S
54x80
~
13xl>
1
-
C1/2,3+
~
G3
W- 'U
~ 'U
1CT-0
~C1
~ 'U
~
8x
p+- 'U
8
~ 'U
8
1S
8
IR
8
L-f';C1
8x
8
rv-LY
8
1S
IR
OUTPUT CELL
1 MUX
~
8
~
,Gl
" ~QO-
EN
f"\." denotes fused inputs
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-377
TlBPSG507M. TlBPSG507C
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
logic diagram (positive logic)
c"i.'!. _
•
, f;,..
i
.
"
;;
.
;
~
~
~
BINARY COUNTER
~
FUNCTIONAL
-,-
;;
lOGIC SYMBOL
eTR 6
CNT/HlDl--{ G2
SCLR1_ 1CY_O
i
;;
CU<-
;;
Cl/2,3+
_'HLOO----<
G3
SCLRO- 1CT-O
C,.
~
~ilfR
:
~ ~
I:::
~
- ""',"'~
I:::'
I;::" ~
1I:::
~
FFc,
'"
:':"::
"
"
~
I;::" !:::Fe,
I~
I:::
F:tk
--R ~"
~
,~
u:::..
It
~"
:,==
~
lr-,.
I;:::: t±!'
I~
t.;:::;.
I~
~
~
~~
~
~
, 0'
=--'~ ,t;i-l
~.r '"
;::::"-le:"JW
=-.J~
~~-'I"
;::..
'"':I>:e'
I_~"---I"
r::: ~'c,W
""---'~
~~~o.
::R~-'-'--O'
I_~~o,
r:::
:-:P:c,
L"
2-378
=--->: ".,
TEXAS
"'!1
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
I
--co
f---C1
f--C2
f---C3
_04
f - - - C5
TIBPSG507M
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
absolute maximum ratings
Supply voltage, Vee (see Note 3) ............................................. " 7 V
Input voltage, VI (see Note 3) ................................................ 5.5 V
Voltage applied to a disabled output (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range ......................................... - 65°C to 1 50°C
NOTE 3: These ratings apply except for programming pins during a programming cycle or during the diagnostic mode.
recommended operating conditions
PARAMETER
VCC
Supply voltage
VIH
Hi9h~level
NOM
MAX
4.5
5
5.5
V
5.5
V
V
2
input voltage
0.8
-2
8
VIL
Low-level input voltage
IOH
High-level output current
IOL
low-level output current
tw
Pulse duration
tsu
Setup time before elK active transition t
UNIT
MIN
Clock high
rnA
rnA
ns
Clock low
Input or feedback to SIR inputs
Input or feedback to SCLRO
~
w
ns
Input or feedback to CNT/HOLDO
5>
w
Input or feedback at SIR inputs
th
Hold time after elK active transition t
Input or feedback at SCLO
ns
a::
Q.
Input or feedback at CNT/HLDO
TA
-55
Operating free-air temperature
125
·C
tlnternal setup and hold times, tsu feedback to SCLR1, feedback to "CiiIi/HLD1; th feedback at SCLRl and feedback at CNT/HLD1, are
guaranteed by f max specifications. The active transition of elK is determined by the programmed state of the eLK polarity fuse.
....
(J
::::>
o
oa::
Q.
PRODUCT PREVIEW documents contain information
on products in the formativa Dr design phase of
development. Characteristic data and other
specifications are design goals. Texas Instruments
reserves the right to change or discontinue these
products without notice.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-379
,T1BPSG507M
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOL
II
VCC
IIH
IlL
lot
Vce
Vcc
VCC
=
=
5.5 V,
10ZH
5.5 V,
UIO ports
10ZL All others
VCC
=
5.5 V,
Va
ICC
Ci
VCC = 5.5 V,
f = 1 MHz,
Co
f
f
VCC
VCC
fmax§
V,
V,
5.5 V,
= 0.4
VI
=
1 MHz,
Vo
=
1 MHz,
VI
2.4
MAX
UNIT
-1.2
V
3.2
0.25
-30
V
0.5
V
0.1
20
mA
-0.25
mA
-130
mA
20
pA
-250
V
See Note 4,
I
FROM
TO
6,Bit counter with SCLR1 or CNT/HLD1
-20
156
Outputs open
=2V
=2V
=2V
230
7
pA
pA
mA
pF
11
pF
14
pF
TEST CONDITIONS
6-Bit counter with SCLRO or CNT IHLDO
MIN
Typt
MAX
UNIT
MHz
SIR registers
(')
-I
tpd'
:z:J
m
~
=
V,
Typt
switching characteristics over recommended supply voltage and operating free-air temperature range
(unless otherwise noted)
C
---~ CAS1
....... W
W_
WAIT
=:
AO·AS
RAS
RASI
CAS
CASI
RfW
MSEL
MSEL
A22
MCI
MCI
ALE
HSA ~
OE
*"
IrM'_"'~ *"
'-""""
,-"L
cs
AO·AS
I--
1--_
r-
r--
CAS2
W
'--""""
AO·AS
.......
ADDRESS
RAS2
RAS3
MEMORY BANK SIGNALS
.......
SELO.l
BANK2
1 MEG x 32 BITS
TMS4Cl027
BANK3
1 MEG x 32 BITS
TMS4Cl027
CAS3
W
DATA
For detailed information, please see the "SYSTEMS SOLUTION FOR STATIC COLUME OECODE" Application Report,
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-385
TlBPSG507M, TIBPSG507C
13 x BOx B PROGRAMMABLE SEQUENCE GENERATOR
diagnostics
A diagnostics mode is provided with these devices that allows the user to inspect the contents of the state
registers. The following are the step-by-step procedures required for the diagnostics.
1. Disable all outputs by taking OE (pin 17) high. (Note: If pin 17 is being used as an input to the array, then
pin 15 or pin 7 must be taken. to double high first before pin 17 is taken high.)
2. Take 00 (pin 8) double high to enable the diagnostics test sequence.
3. Apply appropriate levels of voltage to pins 11, 13 and 14 to select the desired state register, (see Table 1)
4. The voltage level monitored on pin 9 will indicate the state of the selected state register.
diagnostics waveforms
JI'"----------------------- VIHHt
15 _ _ _ _ _
(PIN 71
.
OE _______~------------------------------------------------VIH
(PIN 171
'I
1
14--100 ns-+!
{PIN
_ _ _ _ _ _ _ _ _ _ VIHH t
~ ~s;::s:s:s~sus;::s:s:"Cs;::s:s:::s:s=sus:::s:s*(,.----------"'\
-- -
I
14--100 ns-+!
I
Q3. Q4. Q5
(PINS 11. 13. 14) S S S S S S S S S S S S S S S
(PIN09') S S S
tVIHH
=
Ss
S
.J
I
I
1+--100 ns-+(
Ss s s s s s s Ss s s s s s s s , ) , '
I
S •
10.25 V min. 10.5 V nom, and 10.75 V max
TABLE 1. ADDRESSING STATE REGISTERS DURING DIAGNOSTICS
REGISTER BINARY ADDRESS
PIN 11
2-386
PIN 13
PIN 14
BURRIED REGISTER SELECTED
L
L
L
L
L
H
SCLRO
SCLRl
L
L
HH
CliffIHLDO
L
H
L
CNTIHLDl
L
H
PO
L
H
H
HH
L
HH
L
P2
L
HH
H
L
HH
HH
P3
P4
H
H
L
L
L
H
P5
P6
H
L
HH
P7
H
H
CO
H
H
L
H
H
H
HH
H
H
HH
HH
L
C2
C3
H
HH
H
HH
C4
C5
Pl
Cl
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
-
-
-
-VIH
VIL
TlBPSG507M, TIBPSG507C
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
TYPICAL APPLICATIONS
f max
When the TIBPSG507 is used with two or more devices linked to build a "multi-device" state machine
(see Figure 1), the maximum operating frequency for this state machine is limited to the sum of tpd CLK-Q
(10 ns) of the first '507 and tsu (12 ns). of the second '507, for a clock period of 22 ns. This results
in an f max of 45 MHz (1/22 ns).
CLK (45 MHzl
LI>'507
L>'507
OUTPUT
DATA
DATA
tpd CLK-O
I4- t su
~
1+-----22
tpd CLK-O
~
~
tsu
nS--~+'---22
~
ns-----.j
FIGURE 1
Figure 2 shows the TIBPSG507 used in a system environment where it is operated at 58 MHz, the highest
clock rate possible without compromising data integrity. At the input of the' 507, the system clock period
is limited to the sum of tpd CLK-Q of device A and tsu of the '507. At the output of the '507, the system
clock period is limited to the sum of tpd CLK-Q of the '507 and tsu of device B.
For this system to operate at 58 MHz, a system clock period of 17.2 ns must be met. Given that tsu for
the '507 is 12 ns minimum, tpd CLK-Q of device A cannot exceed 5.2 ns (12 ns + 5.2 ns = 17.2 ns).
On the output side of the '507, tpd CLK-Q of 10 ns must be allowed. In order to meet the system clock
period of 17.2 ns, tsu for device B must not exceed 7.2 ns (10 ns + 7.2 ns) = 17.2 ns). Under these
circumstances, a system frequency of 58 MHz (1/17.2 ns) can be realized.
CLK (58 MHz)
L>'507
A
OUTPUT
DATA
tpd CLK-O"
14
'su
~14 12 ns
1+----17.2 ns
B
tpd CLK·O
~ 10 ns
~..
1Jit4
tsu*-tJII
17.2 ns----.j
• External device parameters (tpd CLK-Q of device A :s -5.2 ns, and tsu of device B
:s 7.2 ns)
FIGURE 2
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
2-387
TlBPSG507M, TlBPSG507C
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
PARAMETER MEASUREMENT INFORMATION
CL
(See Nole A)
R2
LOAD CIRCUIT fOR
3-STATE OUTPUTS
[3.5 V] (3 V)
TIMING
INPUT
'/1.5 V
4---
[0.3 V] (0)
~
"~"I\--..
[3.5 V] (3 V)
LOW-LEVEL~I
I
1.5 V 1.5 V
PULSE
[3.5 V] (3 V)
HIGH-LEVEL
PULSE----"I··~"
*t.,---.I
I
I
t$U~th
~-:"-:.~
[3.5 V] (3 V)
DATA~1.5V
[0.3 V] (0)
INPUT
----
VOLTAGE WAVEfORMS
SETUP AND HOLD TIMES
.L 1.SV
INPUT
-..!i
Ipo
I
I
)11.5
L..
_.
,.....--..,
[3.5 V] (3 V)
-
[0.3 V] (0)
~ Ipd
V
I
I
I
J __ VOH
~V
~I Ipd
VOL
OUTPUT
CONTROL
(low-level
~
I
[0.3 V] (0)
[3'5v](3v)
.
1.5V
1.5V
/I'
enabling)
len
I I
W~~~L~~~6
:
(See Nole B)
ten
c.L -
-.l I+-
I
-+I
WAVEFORM 2
S10PEN
(See Nole B)
-
:g::;-*
\:=-:..
E..:....-
I+-
-
,-+! ~
U
,~V -:
I
-
[0.3 V] (0)
I
I di
_........,I~~r+
OUT-Of·PHASE
OUTPUT
(See Nole D)
VOLTAGE WAVEfORMS
PROPAGATION DELAY TIMES
[0.3 V] (0)
VOLTAGE WAVEfORMS
PULSE DURATIONS
l\
....J4..--+i
IN-PHASE
OUTPUT---jl-..J
tpd
- - \... 1.5V
- ----
10i,-+I
1.5~_
I+I
_
_
~ -
L..
- 3.3 V
VOL
VOL +0.5 V
VOH
:OOH;.5V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. 3·STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten' 5 pF for tdis'
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For M suffix, use voltage levels indicated in parentheses (),
PRR " 10 MHz, tr and tf " 2 ns, duty cycle = 50%. For C suffix, use the voltage levels indicated in brackets [I.
PRR " 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
FIGURE 3
2·388
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIBPSG507M, TIBPSG507C
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
200
ct
E
C.J
>
is.
a.
:-- ..::::::
~
150
I
E
!
:;
--
Vee - 5.5 V
175
~ee
125
-"...
l
- 4.5, "'-
~ ~ t:::::: ~ ~
100
Vee - 5
C.J
~
Y\
-.......::
Vee = 4.75 V
75
'"I
In
l\--r---::::::::::::
= 5.25 V \
Vee
~ 1'-0..
50
25
o
-75 -50 -25
0
25
50
75
100 125
TA-Free-Air Temperature- °e
FIGURE 4
POWER DISSIPATION
vs
FREQUENCY
1000
950
i!:
T
900
I:
o
.~
.~ 850
.!!l
TA
o
;
..... ~
800
f.
- --
:,.....
= ooe
TA - 25°e
-
~
II
750
TA - 50 0 e
I I
700
1
10
.... ~
20 30405080100
F - Frequencv - MHz
FIGURE 5
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
2-389
TIBPSG507M, TIBPSG507C
13 x 80 x 8 PROGRAMMABLE SEQUENCE GENERATOR
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
20
..
c
.,I
E
j::
.
>"i
Q
c
18
16
14
30 VCC _ 5 V,
--
I
12
E 20
~
I .I
tPlH (ClK to 01
'"...
III
6
~
R1 ~ 300 n,
4
R2 - 390 n,
2 Cl - 50 pF,
TA - 25°C
1----+-~~-::::1I"''''''-
15r-~-+-~~~-t~~
c
.2
~
10~~~~-~-~--~-~--;
III
...
tpHl (ClK to 01
o
4.5
I
GO
j::
>III
10
£
5~-4---+---;---+---4---~
o~
5
4.75
o
5.5
5.25
n,
n,
:!!
I
-r---i::
tPl~ (I or Feedback toW
8
11.
R1 - 300
25 R2 - 390
tP~l (I o~ FeeJback Ito 01
.2
:;;
PROPAGATION DELAY
vs
LOAD CAPACITANCE
__
~
__
100
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
14
>-
.,
c
0
"s
....'"
~
11.
tplH (I or Feedback to 01
16
.,
14 r-tPlt (I
E
j::
>IV
'ii
10
Q
tplH (ClK to 01
8
6
o
tpHl (ClK to 01
- 5 V,
300 n,
390 n,
50 pF
-75 -50 -25
__
~
600
c
.
L-
-
10
tplH (ClK to 01
·8
8
...'"
£
6 VCC - 5 V, 4 R1 - 300 n,
R2 - 390 n,
2 Cl~50pF
IV
o
0
25
50
75
o~ feelack fa 01
12
100 125
-
tPHl:(ClK;to 01 r--
TA - 25°C
o
2
3
4
5
6
Number of Outputs Switching
TA -Free-Air Temperature- °C
FIGURE 9
FIGURE 8
2-390
~
500
tpHl (I or Feedback to 01
In
c
I
12
4 VCC
R1 2 R2 Cl -
__
18
tPHl (I or Feedback to 01
.!l!
Q
~
400
20
18
GO
E
j::
__
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
20
c
I
~
300
FIGURE 7
FIGURE 6
16
__
Cl -load Capacitance-pF
VCC-SuppIV Voltage-V
..
~
200
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7
8
TIB82S105BM, TIB82S105BC
16 x 48 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
02897, SEPTEMBER 1985-REVISEO AUGUST 19B9
M SUFFIX, .. J PACKAGE
C SUFFIX ... N PACKAGE
•
50-MHz Clock Rate
•
Power-On Preset of All Flip-Flops
•
6-Bit Internal State Register with 8-Bit
Output Register
(TOP VIEW)
•
Power Dissipation ... 600 mW Typical
•
Programmable Asynchronous Preset or
Output Control
•
Functionally Equivalent to, but Faster than
82S105At
elK
Vee
18
17
16
15
14
19
110
111
13
112
12
113
114
11
10
description
The TIB82S 105B is a TTL field-programmable
state machine of the Mealy type. This state
machine (logic sequencer) contains 48 product
terms (AND terms) and 14 pairs of sum terms
(OR terms). The product and sum terms are used
to control the 6-bit internal state register and the
8-bit output register.
The outputs of the internal state register
(PO-P5) are fed back and combined with the 16
inputs (10-115) to form the AND array. In
addition a single sum term is complemented and
fed back to the AND array, which allows any of
the product terms to be summed,
complemented, and used as an input to the AND
array.
The state and output registers are positive-edgetriggered SIR flip-flops. These registers are
unconditionally preset high on power-up. Pin 19
can be used to preset both registers or, by
blowing the proper fuse, be converted to an
output control function.
115
07
06
PRE/DE
05
01
04
02
GND
03
00
M SUFFIX ... FK PACKAGE
C SUFFIX ... FN PACKAGE
(TOP VIEW)
><:
U
~~!:::d~~~
4
3
2
1 28 2726
25
110
24
111
23
112
8
22
113
114
9
21
10
20
115
11
19
PRE/DE
12131415161718
The TIB82S 105BM is characterized for operation
over the full military temperature range of
-55°C to 125°C. The TIB82S105BC is
characterized for operation from OOC to 75°C.
t Power-up preset and asynchronous preset functions are not
identical to 82S 105A. See Recommended Operating Conditions.
PRODUCTION DATA documents contain information
currant as of publication data. Products conform to
spacifications per the terms of Texas Instruments
:~~=~~i~ai~:1~18 ~!:~~:ti:fn l!IO::::::~rO:S not
Copyright
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
© 1989, Texas Instruments Incorporated
2-391
TIB82S105BM, TIB82S105BC
16 x 48 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
functional block diagram (positive logic)
PRE/DE - - - -....r~
P---------------------~
EN
S
CLK---------------------+-~_t>
>1
8
8
48 X 29
&
8
16XC>
10-115 _...,...1!!:6_~
48
"v
6XC>
6
6
C>
1R
'V
6
'V denotes fused inputs.
timing diagram
Vee
.J
I
PRE
OPTIONAL
OE
10-115
elK
I
I
I
I
I
I
PO-P5
2·392
m
1
:
1
1
I
1
11------I
X,-i-:--i-:-;-:
---!4=t "il i
.l-_ _....J
su
i
I
I
I
I
I
I
,..-.,r-----.lr------:I--..\.;.....- ..,.J!~=======
--J/
I
I
I
00-07
I~~--~-------~tsu--.l
---1--('--_____
i
STATE
REG
INTERNAL
r---I
--~I----------~I;
I
I
I
---Y'\\..._---JY
y....-I
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
I
00-07
TIB82S105BM, TIB82S105BC
16 x 48 x 8 FIELD-PROGRAMMABLE LOGIC SEOUENCER
WITH 3-STATE OUTPUTS OR PRESET
logic diagram (positive logic)
N
<0
m
)0
11
o
191
N
N
m
~
00
00
W
N
N
cg
~
m
~
o
N
.." 0
0
111
12
16)
13
15)
14
14)
15
13)
I.
17
18
19
110
III
112
(13
114
115
. - - FIRST FUSE NUMBER
~ INCREMENT
181
r
4
8
ACTUAL
P
12
12)
3552
I
(27)
FUSE
NUMBER
{191
16
PRE/DE
(261
(25)
20
124)
P
(23)
E
24
1221
(21)
28
(20}
32
PO
Pl
P2
P3
36
P4
40
P5
44
I
PO
--i,~1L
48
~Pl
rl;~1t
t;"S1P2
52
~~~r:
~P3
H;~lSt
==P4
"
~~1~t
56
~P5
~~1l
r-t,~~l
60
I"1"S"""1
--t,~lS~
"
64
a
68
~
t;S'"1-
1(16)
1(151
I
=
73r-t.~1l
~
01
02
I
~h~
~
ti~1~
00
I
I
'7S'
NOTES:
1(17)
~~1l.-
~~1~
72
(18)
)
03
1(13)
04
1(121
as
I
1(11)
06
I
1
(10)
(1)
01
CLK
1. All AND gate inputs with a blown link float to a logic 1.
2. All OR gate inputs with a blown link float to a logic O.
3. Fuse Numbers = First Fuse Number + Increment.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-393
TI882S105BM
16 x 48 x 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH ]-STATE OUTPUTS OR PRESET
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125 °e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 4: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
IOl
Low-level output current
fclock
Clock frequency t
tw
Pulse duration
tsu
tsu
th
TA
1 thru 48 product terms without C-arrayf
1 thru 48 product terms with C-array
Clock high or low
Preset
Setup time before ClK!,
Without C-array
1 thru 48 product terms
With C-array
Setup time. Preset low (inactive) before CLK!§
Hold time, input after ClK!
Operating free-air temperature
MIN
4.5
2
0
0
12
18
25
40
10
0
-55
NOM
5
MAX
5.5
5.5
0.8
-2
12
40
25
UNIT
V
V
V
mA
mA
MHz
ns
ns
ns
125
ns
·C
tThe maximum clock frequency is independent of the internal programmed configuration. If an output is fed back externally to an input,
the maximum clock frequency must be calculated.
.
tThe C-array is the single sum term that is complemented and fed back to the AND array.
§After Preset goes inactive, normal clocking resumes on the first low-to-high clock transition.
2-394
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665303· DALLAS, TEXAS'76266
TIB82S105BM
16 x 48 x 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
electrical characteristics over recommended operating free-air temperature range (unless otherwise
notedl
PARAMETER
TEST CONDITIONS
VIK
Vee - 4.5 V,
VOH
VOL
II
Vee
IIH
Vee
Vee
Vee
III
Vee
105*
Vee
10ZH
Vee
Vee
10Zl
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
Vee
PRE/OE input at GND,
lee
MIN
-18 mA
10H = -2 mA
10l = 12 mA
VI = 5.5 V
VI = 2.7 V
VI = 0.4 V
Vo = 0.5 V
Vo = 2.7 V
Vo = 0.4 V
VI = 4.5 V,
TYpt
II -
2.4
3.2
0.25
-30
120
Outputs open
MAX
UNIT
-1.2
V
V
0.4
25
20
-0.25
-250
20
-20
mA
180
mA
V
~A
~A
mA
~A
~A
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise notedl
PARAMETER
FROM
TO
TEST CONDITIONS
I Without e
MIN
TYpt
MAX
40
25
20
ns
UNIT
tpd
elKt
Q
Rl = 39011,
70
45
8
tpd
PREt
Q
R2 = 75011,
12
25
ns
tpd
Q
See Figure 3
0
10
ns
ten
Veet
OE.
OEt
Q
25
15
ns
tdis
10
5
§
f max
I
array
With e array
tAli typical values are at Vee
=
5 V, TA
Q
=
MHz
ns
25 ·e.
:t:Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed 1 second. Set Va at 0.5 V
to avoid test equipment ground degradation.
§fmax is independent of the internal programmed configuration and the number of product terms used.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-395
1IB82S105BC
16 x 48 x 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 75 °e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 4: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High-level output current
IOl
low-level output current
fclock
Clock frequency t
tw
Pulse duration
tsu
MIN
4.75
2
1 thru 48 product terms without C-array +
1 thru 48 product terms with C-array
Clock high or low
Preset
Setup time before ClK!,
Without C-array
1 thru 48 product terms
With C-array
tsu
Setup time, Preset low linactive) before ClK!9
th
Hold time, input after ClK!
TA
Operating free-air temperature
0
0
10
15
15
30
8
0
0
NOM
5
MAX
5.25
5.5
0.8
-3.2
24
50
30
UNIT
V
V
V
rnA
rnA
MHz
ns
ns
ns
ns
75
°c
tThe maximum clock frequency is independent of the internal programmed configuration. If an output is fed back externally to an input,
the maximum clock frequency must be calculated.
tThe C~array is the single sum term that is complemented and fed back to the AND array.
§After Preset goes inactive, normal clocking resumes on the first low~to-high clock transition.
2-396
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIB82S105BC
16 x 48 x 8 FIELD-PROGRAMMABLE LOGIC SEOUENCER
WITH 3-STATE OUTPUTS OR PRESET
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
II
~
Vee - 4.75 V,
VOH
Vee
~
4.75 V,
IOH
~
Val
II
Vee
~
4.75 V,
IOl
~
Vee
~
5.25 V,
IIH
Vee - 5.25 V,
Vee ~ 5.25 V,
VI ~ 5.5 V
VI - 2.7 V
III
lot
~
~
VI
-3.2 mA
~
2.25 V
~
Va
~
2.7 V
~
5.25 V,
Va
~
0.4 V
IOZl
Vee
lee
Vee ~ 5.25 V,
PRE/OE input at GND,
VI
2.4
3
~
0.37
0.4 V
Va
IOZH
TVPt
24 mA
5.25 V,
5.25 V,
Vee
Vee
MIN
-18mA
VIK
-30
4.7 V,
120
Outputs open
MAX
-1.2
UNIT
V
V
0.5
V
25
20
-0.25
p.A
p.A
rnA
-112
mA
20
-20
p.A
180
rnA
p.A
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
§
f max
FROM
TO
TEST CONDITIONS
I Without e array
I With C array
MIN
TVpt
50
30
70
MAX
UNIT
MHz
45
tpd
elK!
Q
R1
~
500 II,
8
15
ns
tpd
PRE!
Q
R2
~
500 II,
12
20
ns
tpd
Vee!
Q
See Figure 3
0
10
ns
ten
OEI
Q
10
20
ns
tdis
OE!
Q
5
10
ns
tAli typical values are at Vee ~ 5 V, TA ~ 25°e.
:t:The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit current, lOS.
§fmax is independent of the internal programmed configuration and the number of product terms used.
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-397
TIB82S10SBM. 1IB82S10SBC
16 x 48 x 8 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
diagnostics
A diagnostics mode is provided with these devices that allows the user to inspect the contents of the
state register. When 10 (pin 9) is held at 10 V, the state register bits PO-P5 will appear at the 00-05
outputs and 06-07 will be high. The contents of the output register will remain unchanged.
diagnostics waveforms
~~----------------------------------------------------VIH
I1-M5
--.If\.
I ......---------------------------------------vl
I
*
r-------,----------+10V
I
I
""""\V
I
'I
I
,
I+--th-+l
I
:
I
I4-- t su
1
-
-
I
I
I
I
_______
l\
-4 - ) (
-
,\
I
-------Vll
'......
t- - - - - - - - - -
VIH
I'
, I ......-----~--------Vll
tw~
,
I
.14
INTERNAL
______
STATE R E G I S T E R ,
PS
PO-P5 -- -
: ' \ - \ - - - - - - - VIH
!,
10~
elK
~8.0V
II
rl - - - - -- ...!I - - - - -- I
-I -
I
:
i
QO-Q5----Q-n---+:-~*
--------TI-~
-VOH
I
NS
+ - - - - - ..., - - - - - - -- VOL
I 4 - - - t pd
Qn+l
---+:
X
I
I+--tpd~
NS
EVOH
VOL
r.-tpd~
----------------------------0 V
OPTIONAL
OE
PS
2·398
= Present state.
NS
= Next state
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS, TEXAS 15265
TlB82S105BM. TIB82S105BC
16 x 48 x 8 FIELD·PROGRAMMABLE LOGIC SEOUENCER
WITH 3·STATE OUTPUTS OR PRESET
test array
A test array that consists of product lines 48 and 49 has been added to these devices to allow testing
prior to programming. The test array is factory programmed as shown below. Testing is accomplished
by connecting 00-07 to 18-115. PRE/OE to GND. and applying the proper input signals as shown in the
timing diagram. Product lines 48 and 49 MUST be deleted during user programming to avoid interference
with the programmed logic function.
TEST ARRAY PROGRAM
OPTION PRE/OE
ANO
PRODUCT
LINE
C
48
49
C
x-
,,,,,,
IH
OR
INPUT
PRESENT STATE
NEXT STATE
OUT
(In)
(PS)
(NS)
(an)
5 4 3 2 , 0 9181716151413121' 10 51 4 13 12 111 0 51 41312 1'1 0 716151413121'10
H H H H H H HIHIHIHIHIHIH IHIHIH HIHIHIHIHIH LILILILILIL LILjLjLILILILIL
- X L L L L L L LILIL ILILILIL ILILIL LILILILILIL HIHIHIHIHIH HIHIHIHIHIHIHIH
test array waveforms
~---------------------------------------------------5V
VCC~
___ _
I4-I W
-
-
-
-
-
-
-
-
h .'________________. . . IL
ClK
---....:..--------------~,
I
10-17 ___-+-1________---',
'*" +I
,
1
,
!
Ipd
~~:-------:::
\J
1
1
RE~~~:=
I
:::
~
ao-a7 ___-Jf,i-i- - - - -.........~
INTERNAL
....I~
+:____
L.I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
J4.-.-.+t- Ipd
Ipd
VIH
,VIL
*-Isu ......... lh-.l
STATE
- ----oV
-+t
I
I;-_--_--_-_~~:
TEST ARRAY DELETED
OPTION PRE/OE
PRODUCT
LINE
48
49
x =
C
-
C , , , , , ,
IH
OR
AND
INPUT
PRESENT STATE
NEXT STATE
OUT
(In)
(PS)
(NS)
(an)
4 3 2 , o 9181716151413121' 10 51 4 13 12 111 0 51 4131 2 1'Lo 7L6151413121'lo
-1-1-1-1-1- -1-1-1-1-1-1-1· t - I l ·1 j I I
5
- H H H H H H HIHIHIHIHIHIHIHIHIH HIHIHIHIHIH
X L L L L L L LILILILILILILILILIL LILILILILIL - ! - i - I I I
Fuse intact, -
= Fuse blown
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-399
TlB82S 105BM, TIB82S 105BC
16 x 48 x 8 FIELD·PROGRAMMABLE LOGIC SEOUENCER
WITH 3·STATE OUTPUTS OR PRESET
TIB82S105B. 82S105A COMPARISON
The Texas Instruments TIB82S 105B is a 16 x 48 x 8 Field-Programmable Logic Sequencer that is functionally
equivalent to the Signetics 82S105A. However, the TIB82S105B is designed for a maximum speed of 50 MHz
with the preset function being made conventional. As a result the TIB82S105B differs from the 82S105A in
speed and in the preset recovery function.
The TIB82S 105B is a high-speed version of the original 82S 105A. The TIB82S 105B features increased switching
speeds with no increase in power. The maximum operating frequency is increased from 20 MHz to 50 MHz
and does not decrease as more product terms are connected to each sum (OR) line. For instance, if all 48 product
tems were connected to a sum line on the original 82S 105A, the f max would be about 15 MHz. The f max
for the TIB82S105B remains at 50 MHz regardless of the programmed configuration. In addition, the preset
recovery sequence was changed to a conventional recovery sequence, providing quicker clock recovery times.
This is explained in the following paragraph.
The TIB82S 1 05B and the 82S 105A are equipped with power-up preset and asynchronous preset functions.
The power-up preset causes the registers to go high during power-up. The asynchronous preset inhibits clocking
and causes the registers to go high whenever the preset pin is taken high. After a power-up preset occurs,
the minimum setup time from power-up to the first clock pulse must be met in order to assure that clocking
is not inhibited. In a similar manner after an asynchronous preset, the preset input must return low (inactive)
for a given time, tsu, before clocking.
The Signetics 82S 105A was designed in such a way that after both power-up preset and asynchronous preset
it requires that a high-to-Iow clock transition occur before a clocking transition (low-to-high) will be recognized.
This is shown in Figure 1. The Texas Instruments TIB82S1 05B does not require a high-to-Iow clock transition
before clocking can be resumed, it only requires that the preset be inactive 8 ns (preset inactive-state setup
time) before the clock rising edge. See Figure 2.
The TIB82S105B, with an f max of 50 MHz, is ideal for systems in which the state machine must run several
times faster than the system clock. It is recommended that the TlB82S 105B be used in new designs. However.
if the TIB8251058 is used to replace the 825105A. then the customer must understand that clocking will begin
with the first clock rising edge after preset.
TABLE 3. SPEED DIFFERENCES
PARAMETER
f max
tpd, elK to
2-400
Q
B2S105A
TIBB2S105B
SIGNETICS
TIONLY
20 MHz
50 MHz
20 ns
15 ns
TEXAS . . ,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIB82S105BM, TIB82S105BC
16 x 48 x 8 FIELD· PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
Vee
PRE
-I'i
I
~tsu-+f
If--tsu-+l
I
I
I
rJ~--~~----------
--~I-----+I----------~
I
eLK
:
REGISTERS
OJ
I
:
:
I
~
__xy
I
~_X::
FIGURE 1. 82S105A PRESET RECOVERY OPERATION
Vee
...J1
PRE
I
I
I
""""-tsu
I
I
r--:I~: ____________________
--~I--------------------~!~.
eLK
I
REGISTERS:J
I
\ ......._ _
..JX~_____'X..Y
\__~X'--___>C
FIGURE 2. TIB82S105B PRESET RECOVERY OPERATION
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2·401
TIB82S 105BM. TIB82S 105BC
16 x 48 x 8 FIELD·PRDGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
PARAMETER MEASUREMENT INFORMATION
5V
SI
b
Rl
FROM OUTPUT ~.-...................... TEST
UNOER TEST
POINT
R2
CL
ISee Note AI
LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
TIMING
INPUT
./.
... t su " " "
HIGH LEVEL
PULSE
LOW-LEVEL
PULSE
[0.3 VI (0)
~tpd
/'
I
1.5 V :
,
I
tpd~
OUT-OF-PHASE
OUTPUT
(See Note DI
\1
~,-,:-;:
~
VOH
OUTPUT
CONTROL
(low-level
f
~
1.5V
1.5V
:
-
- -
-
[3.5 VI (3 V)
[0.3 VI (0)
~
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
15 V
:
J_ -
14-
ten-+!
VOH
I
WAVEFORM 1
SI CLOSED
(See Note BI
-+II
I
!t-tdis
I
II
1.5 V
I
I
:,
~~ ~
tdis .....
it l .5V
------~
~3.3V
( I _ _ £,:"VOL +0.5 V
- - - X - VOL
~
ten-+!
WAVEFORM 2
S10PEN
(See Note BI
- - - [ 0 . 3 VI (0)
I
I
~
VOL
[3'5VI(3V)
15 V
I I
1 . 5V
-
~
enabling)
VOL
~tpd
1 . 5V
'
VOLTAGE WAVEFORMS
PULSE DURATIONS
- - - - [ 3 . 5 v I (3 V)
\1.5V
I ......_ - - [0.3 VI (0)
tpd~
[0.3 VI (0)
,
,
-:~---[3.5VI(3V)
IN-PHASE
OUTPUT:
~
: . - - tw ---.:
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT J l . 5 V
:
~.-~~,-[3.5VI (3 V)
~1.5V
th .....
1.5 V
1.5 V
~
'
DATA
INPUT
[3_5 VI (3 V)
7,1.5V
---~-:- - - - - - --[0.3 VI (0)
T
i.
Jf==i= VOH
I
·~VOH-0.5V
~OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the folloyving characteristics: For M suffix. use the voltage levels indicated in parentheses ( ),
PRR '" 10 MHz, tr and tf '" 2 ns, duty cycle = 50%. For C suffix, use the voltage levels indicated in [ I. PRR '" 1 MHz,
tr = tf = 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
FIGURE 3
2-402
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TlB82S167BM. TIB82S167BC
14 x 48 x 6 FIELD· PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
02896, JANUARY 1985 - REVISED AUGUST 1989
•
Programmable Asynchronous Preset or
Output Control
•
Power-On Preset of All Flip-Flops
•
8-Bit Internal State Register with 4-Bit
Output Register
•
Power Dissipation ... 600 mW Typical
•
Functionally Equivalent to, t but Faster than
82S167A
M SUFFIX, .. JT PACKAGE
C SUFFIX .. , NT PACKAGE
(TOP VIEWI
CLK
description
16
VCC
17
16
18
14
19
13
110
12
111
11
112
10
113
00
The TIB82S 167B is a TTL field-programmable
state machine of the Mealy type. This state
machine (logic sequencer) contains 48 product
terms (AND terms) and 12 pairs of sum terms
(OR terms), The product and sum terms are used
to control the 8-bit internal state register and the
4-bit output register.
PRE/OE
01
P1
02
PO
GNO
03
M SUFFIX ... FK PACKAGE
C SUFFIX, .. FN PACKAGE
(TOP VIEWI
The outputs of the internal state register (PO-P7)
are fed back and combined with the 14 inputs
(10-113) to form the AND array, In addition the
first two bits of the internal state register (PO-P1 )
are brought off-chip to allow the output register
to be extended to 6 bits if desired. A single sum
term is complemented and fed back to the AND
array, which allows any of the product terms to
be summed, complemented, and used as inputs
to the AND array,
4
3
2
1 28 2726
5
11
19
6
25
24
110
111
7
23
8
22
NC
9
21
112
10
20
113
11
19
12131415161718
The state and output registers are positive-edgetriggered SIR flip-flops. These registers are
unconditionally preset high on power-up. PREIOE
can be used as PRE to preset both registers or,
by blowing the proper fuse, be converted to an
output control function, OE.
...-NOUMO..-
ddzzOc..c..
(!)
NC-No internal connection
The TIB82S 167BM is characterized for operation
over the full military temperature range of
-55°C to 125°C. The TIB82S167BC is
characterized for operation from
to 75°C,
ooe
t Power up preset and asynchronous preset functions
are not identical to 82S167A.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
~~~~::~~i~ar::,~~~ ~!:~~~ti:fn :IIO::~:::::t!~~S not
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1989, Texas Instruments Incorporated
2-403
TIB82S167BM, 1IB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
functional block diagram (positive logic)
PRE/liE
rig
--'
LEN
~s
eLK
,e1
;;.1
&
45 X 48
14xI>
10-113
14
2XI>
~
~
48 X 25
4
'V
'V
2X
1S 1=1
2
2
P-- 'V
~ 'V
~
r
4X
1S I = 1 'Q
1R
4
4
2
'Q
1R
'V
y1
6XI>
-
4#-
r
I>
-
'V
'V
6X
1S 1=1
6
6
'V
1R
-
]
6
2
""" denotes fused inputs
timing diagram
Vee
~
PRE
I
I
I
II
--I~------~
OPTIONAL
10-113
~~-ts-u~~------
:
rh
--~I~----------~------~I
I
I
I
-+<
X: :
I
I
I
i
.......________---''--____..J
~tsu=+l
.
eLK
.~-----
I
I
i
I
TEXAS ."
INSTRUMENTS
2-404
POST OFACE BOX 656303 • DALLAS. TEXAS 76285
:
00-03
PO, P1
TIB82S167BM. TIB82S167BC
14 x 48 x 6 FIELD· PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
logic diagram
.....
10
o
8
......FIRST FUSE NUMBER
INCREMENT
<::0
0-
7
12
•
,
ACTU
4
FUSE NUMBER
5
,.
I
4
8
2
12
19
'"
"
22
'6
"
20
20
"
2.
"
'" "
~
,
23
P
PO
28
"
32
P2
PRE/OE
,t
P3
36
P4
P5
40
P6
P7
44
C
C
'is
'-"48~
~
~i~
~
~~
52
~
56
~
-'"'
60
,. ~C:
~~~
~
tt~
'is'
~~
t£~~~
rfi
~~
'is'
64
~
~.9
47
...
40 39
...
32 31
...
!4 23
...
1615
...
8
7
...
~
0
I
I
I
I
"
r-r~
I
I
~
'iT"
I
I
,.
~68
I
I
~
"
,.
"
"
'0
9
,
P
P
Q
Q
Q
Q
C
NOTES: 1. All AND gate inputs with a blown link float to the high level.
2. All OR gate inputs with a blown link float to the low level.
3. Fuse Number = First Fuse Number + Increment
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 76265
2-405
TlB82S167BM
14 x 48 x 6 FIELO;PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. 5.5 V
Voltage applied to a disabled output (see Note 3) ........................-. . . . . . . . .. 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 3: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
VCC
Supply voltage
VIH
High-level input voltage
Vil
10H
Low-level input voltage
High-level output current
10l
Low-level output current
fclock
tw
tsu
Clock frequency t
Pulse duration
MIN
NOM
MAX
4.5
5
5.5
V
5.5
V
0.8
-2
mA
2
1 thru 48 product terms without C-arrayi
1 thru 48 product terms with C-array
0
12
40
0
25
Clock high or low
12
Preset
Setup time before ClK!,
Without C-array
18
25
1 thru 48 product terms
With C-array
40
Setup time. Preset low (inactivel before ClK! §
tsu
th
Hold time. input atter ClK!
TA
Operating free-air temperature
V
mA
MHz
ns
ns
10
ns
0
-55
UNIT
ns
125
·C
tThe maximum clock frequency is independent of the internal programmed configuration. If an output is 'fed back externally to an input,
the maximum clock frequency must be calculated.
iThe C-array is the single sum term that is complemented and fed back to the AND array.
§After Preset goes inactive, normal clocking resumes on the first low-to-high clock transition.
TEXAS ."
INSTRUMENTS
2-406
POST OFFICE BOX 655303 • DAlLAS. TEXAS 76286
TlB82S167BM
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEOUENCER
WITH 3·STATE OUTPUTS OR PRESET
electrical characteristics over recommended operating free·air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VIK
Vee = 4.5 V,
II = -18 mA
VOH
Vee = 4.5 V,
IOH = -2 mA
Val
II
Vee = 4.5 V,
IOl = 12 mA
VI = 5.5 V
Vee = 5.5 V,
Vee = 5.5 V,
IIH
MIN
Typt
2.4
3.2
0.25
MAX
-1.2
UNIT
V
V
0.4
V
~A
VI=2.7V
25
20
= 0.4 V
-0.25
mA
-250
mA
~A
VI
IOS~
Vee = 5.5 V,
Vee - 5.5 V,
IOZH
Vee = 5.5 V,
Va = 2.7 V
20
~
IOZl
Vee = 5.5 V,
Va
-20
~
lee
Vee = 5.5 V,
PRE/OE input at GND,
= 0.4 V
VI = 4.5 V,
Outputs open
160
mA
III
Va - 0.5 V
-30
90
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
§
f max
FROM
TO
TEST CONDITIONS
I Without e
I
array
With e array
MIN
Typt
40
70
25
45
MAX
UNIT
MHz
tpd
elK!
Q
Rl = 390O,
10
20
tpd
PRE!
Q
R2 = 750O,
8
25
ns
ns
tpd'
Vee!
Q
See Figure 3
0
15
ns
ten
OEI
Q
10
25
ns
tdis
OE!
Q
5
15
ns
t All typical values are at Vee = 5 V, T A = 25 De.
tNat more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second. Set
0.5 V to avoid test equipment ground degradation.
§fmax is independent of the internal programmed configuration and the number of product terms used.
'This parameter is guaranteed but not tested.
Va
at
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-407
TIB82S167BC
14 x 48 x 6 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR ,PRESET
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Voltage applied to a disabled output (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range ...................................... ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 0 e
NOTE 3: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
PARAMETER
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
fclock
Clock frequency t
tw
tsu
Pulse duration
1 thru 48 product terms without C-arrayt
1 thru 48 product terms with C-array
Clock high or low
Setup time before CLKt,
Preset
Without C-array
1 thru 48 product terms
With C-array
tsu
Setup time, Preset low (inactive) before CLK! §
th
Hold time, input after CLK!
TA
Operating free-air temperature
MIN
NOM
MAX
UNIT
4.75
2
5
5.25
5.5
0.8
-3.2
24
50
30
V
0
0
10
15
15
30
8
0
0
V
V
mA
mA
MHz
ns
ns
ns
ns
75
·C
tThe maximum clock frequency is independent of the internal programmed configuration. If an output is fed back externally to an input.
the maximum clock frequency must be calculated.
+The C-array is the single sum term that is complemented and fed back to the AND array.
§After Preset goes inactive, normal clocking resumes on the first low-to-high clock transition.
TEXAS . "
INSTRUMENTS
2-408
POST OFFICE BOX 656303 • DALLAS, TEXAS 75265
TIB82S167BC
14 x 48 x 6 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VIK
Vee = 4.75 V,
VOH
Vee - 4.75 V,
Val
II
Vee = 4.75 V,
IIH
Vee
III
Vee = 5.25 V,
Vee
= 5.25
= 5.25
V,
V,
lot
Vee = 5.25 V,
IOZH
Vee = 5.25 V,
IOZl
Vee = 5.25 V,
ICC
Vee = 5.25 V,
PRE/OE input at GND,
MIN
rnA
IOH - -3.2 rnA
IOl = 24 rnA
TYpt
11= -18
2.4
3
0.37
MAX
UNIT
-1.2
V
V
0.5
V
5.5 V
25
~A
VI = 2.7 V
20
-0.25
-112
pA
rnA
rnA
20
~
VI
=
= 0.4 V
Va = 2.25 V
Va = 2.7 V
Va = 0.4 V
VI = 4.5 V,
VI
-30
90
Outputs open
-20
~
160
rnA
switching characteristics over recommended supply voltage and operating free-air temperature ranges
(unless otherwise noted)
PARAMETER
f
§
max
FROM
TO
TEST CONDITIONS
I Without e
I
array
With e array
MHz
ns
20
ns
See Figure 3
0
10
ns
Q
10
20
Q
5
10
ns
ns
tpd
PREi
Q
R2
tpd
Veei
OEI
Q
OEi
=
UNIT
8
R1 = 500 II,
5 V, T A
MAX
500 II,
Q
=
70
45
15
elKi
t All typical values are at Vee
TYpt
50
30
10
tpd
ten
tdis
MIN
=
25°e.
*The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit current, lOS.
§fmax is independent of the internal programmed configuration and the number of product terms used.
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997·5666.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
2·409
TlB82S167BM, TlB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEOUENCER
WITH 3·STATE OUTPUTS OR PRESET
diagnostics
A diagnostics mode is provided with these devices that allows the user to inspect the contents of the
state register. When 10 (pin 9) is held at 10 V, the state register b.its P2-P7 will appear at the 00-03 and
PO-P1 outputs. The contents of the registers, 00-03, and PO-P1 remain unchanged.
diagnostics waveforms
~~---------------------------VIH
11-113
----A
1
---------------------------Vll
I
1
1
10
r------,----------+10V
---WI
1
I
INTERNAL
:---,-I1
____ _
P2-P7- -
00-03. PO-Pl
I+--th-+l
1
--iI
t4-- tsu
STATE REGISTER
-
I1•\
.j.' I
~-------~/I
elK
~8.0V
-;:.
...--------~I I
1
I
"I -
--
-l -
I
I
-:s- - - I
V- T ~+ - - - - 1
~
----on---+:-""""'\)K
IH
'
Vil
1
- - - - - - - t- - - - - - - - - -
I 1
tw-----4i
PS
I
:\
1
~.
1
V
I 4 - - tpd
--+:
an + 1
'"
-------TI-....J 1
I
1
I
1
-t -
VIH
Vil
------
-
-
-
I+--tpd~
NS
-
E
-VOH
-
VOL
VOH
VOL
I4-tpd-+l
OPTIONAL
OE
----------------------------0 V
PS = Present State
NS = Next State
2-410
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TIB82S167BM. TIB82S167BC
14 x 48 x 6 FIELD-PROGRAMMABLE LOGIC SEQUENCER
WITH 3-STATE OUTPUTS OR PRESET
test array
A test array that consists of product lines 48 and 49 has been added to these devices to allow testing
prior to programming. The test array is factory programmed as shown below. Testing is accomplished
by connecting QO-Q3 to 110-113, PRE/OE to GND, and applying the proper input signals as shown in the
timing diagram. Product lines 48 and 49 must be deleted during user programming to avoid interference
with the programmed logic function.
test array program
OPTION PRE/OE
AND
INPUT
PRODUCT
LINE
C
C
48
X -
49
- X
IH
DR
PRESENT STATE
NEXT STATE
OUTPUT
(On)
(PS)
Un)
INS)
1 1 1 1 1 1
S 4 3 2 1 0 91817161s1413121110 sI413121110 sl413121110 716151413121110
H H H H H H HIHIHIHIHIHIHIHIHIH HIHIHIHIHIH LI LiLI L IL[L L IL IL I L I L I L I L I L
L L L L L L LILI LILILILILILILIL LILILILILIL HIHIHIHIHIH HIHIHIHIHIHIHIH
test array waveforms
.--J ___ _
:
n<--___--iIC
r--------------------------------------------------
Vce
CLK
-
I
I
I
I
I
I
-
:
I! I
-
-
- -
-
-
-
14- tpd ~
00·03
I
,
i
~ tpd
tpd
...f4--+j
/orII -----~\JI
_ _ _-oJ,
i
INTERNAL
STATE
- ----oV
J+-tw-+t
,~tsU-+r-th~
10·19
-
SV
I
/
~:::
A----VOH
:----VOL
I
,
\J
REG~~~!;----JI
VIH
V,L
/ ____ :~:
test array deleted
OPTION PRE/OE
AND
PRODUCT
x
LINE
C
C
48
-
-
49
-
1 1 1 1 1 1
IH
OR
INPUT
PRESENT STATE
NEXT STATE
OUTPUT
Un)
IPS)
(NS)
(an)
S 4 3 2 1 0 9181 7 161514131 2 1 1 10 s141312111° sl41 3 12J1jo 7161s14 1312 11 10
H H H H H H HIHIHIHIHIHIHIHIHIH HIHIHIHIHIH
X L L L L L L LjLjLILIL/LILILILIL LIL/LILIL/L
= Fuse intact, -
-1-1-1-1-1- -1-1-1-1-1-1-1-
-1-1-1-1-1- -1-1-1-1-1-1-1:. .
=
Fuse blown
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DA1.LAS, TEXAS 75265
2-411
TIB82S167BM, TIB82S1.67BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
TlB82S167B, 82S167A COMPARISON
The Texas Instruments TIB82S i 67B is a 14 x 48 x 6 Field·Programmable Logic Sequencer that is fUnctionally
equivalent to the Signetics 82S167A. However, the TIB82S167B is designed for a maximum speed of 50 MHz
with the preset function being made conventional. As a result the TIB82S 167B differs from the 82S 167A in
speed and in the preset recovery function.
The TIB82S 167B is a high-speed version of the original 82S167 A. The TIB82S167B features increased switching
speeds with no increase in power. The maximum operating frequency is increased from 20 MHz to 50 MHz
and does not decrease as more product terms are connected to each sum (OR) line. For instance, if all 48 product
tems were connected to a sum line on the original 82S167A, the f max would be about 15 MHz. The f max
for the TIB82S 167B remains at 50 MHz regardless of the programmed configuration. In addition, the preset
recovery sequence was changed to a conventional recovery sequence, providing quicker clock recovery times.
This is explained in the following paragraphs.
The TIB82S167B and the 82S167A are equipped with power-up preset and asynchronous preset functions.
The power-up preset causes the registers to go high during power-up. The asynchronous preset inhibits clocking
and causes the registers to go high whenever the preset pin is taken high. After a power-up preset occurs,
the minimum setup time from power-up to the first clock pulse must be met in order to assure that clocking
is not inhibited. In a similar manner after an asynchronous preset, the preset input must return low (inactive)
for a given time, tsu, before clocking.
The Signetics 82S 167 A was designed in such a way that after both power-up preset and asynchronous preset
it requires that a high-to-Iow clock transition occur before a clocking transition (low-to-high) will be recognized.
This is shown in Figure 1. The Texas Instruments TIB82S167B does not require a high-to-Iow clock transition
before clocking can be resumed, it only requires that the preset be inactive 8 ns (preset inactive-state setup
time) before the clock rising edge. See Figure 2.
The TlB82S167B, with an f max of 50 MHz, is ideal for systems in which the state machine must run several
times faster than the system clock. It is recommended that the TIB82S 167B be used in new designs. However,
if the TI8825 7678 is used to replace the 825167A. then the customer must understand that clocking will begin
with the first clock rising edge after preset.
SPEED DIFFERENCES
PARAMETER
f max
tpd, elK to Q
82S167A
TI882S1678
SIGNETICS
TIONlY
20 MHz
50 MHz
20 ns
15 ns
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 76265
TIB82S167BM, TIB82S167BC
14 x 48 x 6 FIELD· PROGRAMMABLE LOGIC SEQUENCER
WITH 3·STATE OUTPUTS OR PRESET
Vee
--I:
I4-- t su-.j
I
jf--tsu -+I
PRE
I
I
elK
REGISTERS
I
r-l
i
I
I
---+------rl------------~,
____v
:J
I
I
I
I
I
~_X=
FIGURE 1. 82S167A PRESET RECOVERY OPERATION
Vee
--"l
~tsu
I
I
I
i
PRE
I
elK
REGISTERS
---,'--~,
J
I
r-l :
\~
~~------------------
___.JX'"_____XY
''-_..JX,-__C
FIGURE 2. TIB82S167B PRESET RECOVERY OPERATION
TEXAS •
INSTRUMENTS
POST OFFice BOX 655303 • DAllAS. TEXAS 75265
2-413
TIB82S167BM. TlB82S167BC
14 x 48 x 6 FIELD·PROGRAMMABLE LOGIC SEOUENCER
WITH 3·STATE OUTPUTS OR PRESET
PARAMETER MEASUREMENT INFORMATION
CL
(See Nota A)
R2
LOAD CIRCUIT FOR
3·STATE OUTPUTS
[3.5 V] (3 V)
TIMING
INPUT
4·
[0.3 V] (0)
~Iw~
tsu~th
~-:.-:'-
--.I' 1.5 V
DATA
INPUT
HIGH-LEVEL~
PULSE
I
I
.,( 1.5 V
I
[3.5 V] (3 V)
~
----
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
L
INPUT
-.Ii
tpd
1.5 V
-l+---+f
I
1/
T
IN.PHASE
I
OUTPUT--'I-.J
I~
_,
tpd~
1\
~ tpd
1.5 V I
I
OUTPUT
CONTROL
(low-level
enabling)
~
1.5V
VOL
I I
__.-;.1. . . . .
W~~~L~Rs~6
OUT·OF·PHASE
OUTPUT
(See Note D)
: \
I
ten
-+I
WAVEFORM 2
S1 OPEN
(See Note B)
[3'5v](3v)
II
-+!!+-
:.l.. -
-
I
t dls -+! I+-
-
-
__ Ll_
:~
T -
1.5 V
(See Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
[0.3 V] (0)
1.5V
I
ten
VOH
~V
~I tpd
[3.5 V] (3 V)
VOLTAGE WAVEFORMS
PULSE DURATIONS
- - - - - [3.5VJ(3V)
"'- 1.5 V
[0.3 V] (0)
IJ- -
[0.3 V] (0)
I
LOW-LEVEL~I
I
1.5 V 1.5 V
PULSE
[0.3 V] (0)
[3.5 V] (3 V)
tdls
Y
I+-
15 V
.:.- _
-+I I+-
L..
[0.3 V] (0)
~3.3V
VOL
c..-
VOL +0.5 V
I ..Y
~- VOH
_
_
_
V
~ V
_ :H:;.5
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C L includes probe. and jig capacitance and is 50 pF for tpd and teo' 5 pF for t d;,.
B. Waveform 1 is for an output with internal conditions such thatthe output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For M suffix, use the voltage levels indicated in parentheses (), PRR s 10 MHz,
t, and" s 2 ns, duty cycle = 50%. For C suffix, use the voltage levels indicated in brackets [J, PRR s 1 MHz, t, = tf = 2 ns, duty
cycle = 50%.
D. When measuring propagation delay times of 3·state outputs, switch S1 is closed.
E. Equivalent loads may be fused for testing.
FIGURE 3
TEXAS ."
INSTRUMENTS
2·414
POST OFFICE BOX 6.56303 •
DAll~S.
TEXAS 75265
TlCPAl16l8-55C, TICPAl16R4-55C
TlCPAl16R6-55C, TICPAl16R8-55C
STANDARD CMOS PAl® CIRCUITS
D3062, NOVEMBER 19B7-REVISED OCTOBER 1989
•
Standard 20-Pin PAL Family
TICPAL 16L8'
J OR N PACKAGE
•
Virtually Zero Standby Power
•
Propagation Delay . . . 55 ns Max
•
TTL- and HC-Compatible Inputs and Outputs
(TOP VIEW)
•
Preload Capability to Aid Testing
•
Fully Tested for High Programming Yield
Before Packaging
•
Greater than 2000-V Input Protection for
Electrostatic Discharge
•
Devices in the 'J' Package Can Be Erased
and Reprogrammed More Than Once
VCC
0
110
110
110
110
110
I/O
0
GND
TICPAL16R4'
J OR N PACKAGE
ITOPVIEW)
ClK
DEVICE
INPUTS
PAL16L8
10
PAL16R4
8
PAL 16R6
8
PAL 16R8
8
3-STATE
REGISTERED
o OUTPUTS a
2
0
0
0
OUTPUTS
PORTS
0
6
413-5tatel
4
6 13-5tatel
2
0
8 13-5tatel
VCC
110
110
110
Q
Q
Q
Q
1/0
110
GND ......_ _,....DE
description
TICPAl16R6'
These PAL devices provide reliable, highperformance substitutes for conventional TTL
and HCT logic. They are also compatible with HC
logic over the VCC range of 4.75 V to 5.25 V.
Their easy programmability allows for quick
design of "custom" functions and typically
result in a more compact circuit board. Static
power dissipation for these devices is negligible.
J OR N PACKAGE
ITOP VIEW)
ClK
vce
I/O
Q
Q
Q
Q
Q
The output registers of these devices are Ootype
flip-flops that store data on the low-to-high
transition of the clock input. The registered
outputs may be disabled by taking OE high,
whereas the nonregistered outputs may be
disabled through the use of individual product
terms_ Unused inputs must always be connected
to an appropriate logic level, preferably either
VCC or ground.
Q
1/0
DE
I
GND
TlCPAl16R8'
J OR N PACKAGE
ITOP VIEW)
elK
vce
Q
Q
Q
Q
Q
Q
Q
Q
GND
DE
The dotted circles represent windows found only in the J package.
PAL@ is a registered trademark of Monolithic Memories Inc.
PRODUCTION DATA documants conlain inlormalio.
current as of publication data. Products conform to
specifications paf the tarms of Taxas Instruments
~:~~:~~8[n~I~1~ ~:~::i:; :'i:=:::::t:~S not
Copyright © 1989. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-415
TlCPAl16lB·55C, TlCPAl16R4·55C
TlCPAl16R6·55C, TICPAl16RB·55C
STANDARD CMOS PAl® CIRCUITS
description (continued)
The programming cell consists of a floating-gate device like those used in EPROMs. All terms are initially
connected. The unwanted terms are programmed out to provide the desired function. The output of a
given AND gate is low if both the true and complement cells of a term are connected, and high if all related
cells are programmed. Programming can be done manually but is usually achieved through the use of
commercially available programming equipment.
This TICPAL 16' series has internal electrostatic discharge (ESD) protection circuits and has been classified
with a 2000-V ESD rating tested under MIL-STD-8838, Method 3015.1. However, care should be exercised
in handling these devices, as exposure to ESD may result in a degradation of the device parametric
performance.
The floating gate programmable cells allow these PALs to be fully programmed and tested before assembly
to assure high field programming yield and functionality. They are then erased by ultraviolet light before
packaging.
All devices in this series contain a security feature. Once the security cell is programmed, additional
programming and verification cannot be performed. This prevents easy duplication of a design.
The TICPAL 16'C series is characterized for operation from O°C to 75°C.
erasure
The TICPAL 16' (JL package) series can be erased after programming by exposure to ultraviolet light that
has a wavelength of 253.7 nm (2537 A). The recommended minimum exposure dose (UV intensity x
exposure time) is fifteen w·s·cm - 2. The lamp should be located about 2.5 cm (1 inch) above the chip
during erasure. It should be noted that normal ambient light contains the correct wavelength for erasure.
Therefore, when using the TICPAL 16' series (JL package), the window should be covered with an opaque
label.
2-416
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
TICPAL 16L8·55C, TICPAL 16R4·55C
STANDARD CMOS PAL® CIRCUITS
functional block diagrams (positive logic)
TICPAl16lS'
EN ".1
&
32 X 64
\710-----0
10-----0
10--'+-++--1/0
kr-4t+-++--
1/0
kr-4t+.....+--1/0
IO--.+-++-- 1/0
kr-4t+.....+--1/0
6
TICPAl16R4'
EN2
DE
,
ClK
".1
&
32
C1
x 64 --!!,..
2\7
1D
Q
-.!!,..
~
S
~
Q
-.!!,..
[>
r-----..
Q
-.!!,..
4
r+-
~
-
r--
p
Q
r--
EN
~
".1
\7
""'\
f--
P
f--
~
"-
"-
f--
~
"-
110
1/0
1/0
1/0
4
4
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
2-417
TICPAl16R6·55C, TlCPAl16R8·55C
STANDARD CMOS PAl® CIRCUITS
functional block diagrams (positive logic)
TICPAl16R6
OE
_~N2
~C1
ClK
&
32
x 64
--.!,..
>1
2\1
10
Q
-1!...-.
~
~
Q
-1!...-.
~
I>~
~
Q
-1!...-.
~
~
~
~
'--
~
Q
-
Q
~
Q
--.!,..
-.2.,.-
EN
~
",
'V
7--=--..-
1
1
2
6
110
110
TICPAl16RB
OE-------------------------d~--_,
ClK
---------------i>
r;;--r-~--Q
&
32 X 64
r----t----i-~-Q
r----t----i-~-Q
r----t----1-~-Q
r----t----1-~-Q
r----t----1-~-Q
r----t----i-~-Q
r----t----1-~-Q
B
2-418
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TlCPAl16lB·55C
STANDARD CMOS PAl® CIRCUITS
logic diagram (positive logic)
1(1 )
FIRST
INCRE.MENT
~~~BERS
o
'0
4
B
12
lS
20
24
2B
31
32
6'
96
J
(19) 0
J
(1B) 1/0
fJ--V
128'60
'92
22'
(21N--
~
288
320-352
38.
/"
-V
4'6
448- -
(3) 480
512544
576608
6.0
-'">'--_-Vr'J~--'-.:(1--'-'7)
1/0
672
704
(4)~6
768
BOO
J
832
864- 896
928960
(5) 992
-V
(lS) 1/0
1024
1056
1088
'120
'152
'184
1216
(15) 1/0
(S)'248
1280
1312
'344
,14) 1/0
1376
1408
'440
1472
I (7)'50'
1536
1568
1600
1632-1664
1696
,13) 1/0
17281760
I (B)
1792
1824
1856
1888
1920
1952
1984
I
I--
h
(12) 0
.,..;--_V
(~0'6
~~ _______
(1_1)
I
Fuse number - First Fuse number + Increment
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-419
TlCPAl16R4·55C
STANDARD CMOS PAl® CIRCUITS
logic diagram (positive logic)
CLK~--------____~_________________________
.
FIRST
INCREMENT
~~~BERS
a
'0
4
8
12
16
20
24
I
28
31
32
64
--
••
~
128-- '80
'92
j
(19)
I
>--
(2~
'1:>---266
288
320
362
384
416
448
(3) 480
I-
h.
1
v
>--
(18)
544
(4)~6
-
768
800
832
864
896
928
960
(5) 9.2
)---
>f6r~
Cl
~
(16
~
r.:J....
(15)
>tg
r.:J.v
(14
Cl
1024
1056
1088
1120
1152
1184
1216
>->--P-
1280
1312
\---
'344
1376
'408
1440
\--
1472
1504
Cl
-:,r
(7)
15361568
1600
>--
+-
16321664
1696
1128
1760
J!I)
!---"
,....,-
1792
1824
1856
k -h
1888
1920
1952
'9"
I-
J
(13)
~
Fuse number
=
1
(12)
.. 1
~
T
First Fuse number + Increment
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
1/0
1
2016
~
2-420
Q
Cl
(6)'248
9
'"
r.:J....
I-b-
1/0
1
6'2
576
608
640
672
704
1/0
1/0
TICPAL 16R6·55C
STANDARD CMOS PAL® CIRCUITS
logic diagram (positive logic)
CLK(~
- - - - - _ . - - - - - - - - - - - - - - - - - --FIRST
...
--------
INCREMENT
~~BERS
F
N
4
'0
8
-LI
0
32
64
96-
-
12
-
16
20
24
.
28
31
-
)-
f---'
e-}-b-
~
256_
288
320 __
352
384416
448
~I
~~""
1/0
Q
t-
-
..
512
544-·576
608
640
672
704
736
--t>'>--'>---
(41~
Y;
Y;
~
....
(171
~
(161
Q
Cl
'----'
768
800
832
86'
896
928
960
--b-
V
Q
Cl
~:
>--
1024
>--
1056
1088
>-P>-
1120
',52
1184
1216
1248
t=
1280
1312
1344
1316
-
1408
1440
1472
(71
(191
Cl
480
~.-
(6)
1
.
128
160
192
224
>
~
b
~
~
(151
~
Q
Cl
(141
~
Q
Cl
1504
-
.I-
1536
1568
1600
.--
t-
16321664-
'-b~ tJ....
-
1696
1131 Q
1728-
J.BI
1760
,
1792
j-.>-
1824
1856
1888
1952
i ,
1984
(9~_
f
I
I
(+t-------4--+-+-
+-+1+ i--+r++-Tr
II II. I
Fuse number ... First Fuse number
J
1121
:=:=-----d<1-----
~I
~ ~ ~J
1920
I
1/0
+ Increment
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-421
TlCPAl16RB·55C
STANDARD CMOS PAl@ CIRCUITS
logic diagram (positive logic)
-
CLK1!lp
FIRST
FUSE
NU MBERS
0
--- . - - - _ . _ - -
INCREMENT
,
4
8
12
16
20
24
I
0
28
32
64
96-'28
31
>---
fblr;] ""
\-p-
'60
'92
Q
Cl
(2~
Vb-
>--
256
288
320
~
>-
352
384
4'6
448
t-
5'2
54'
>--
576608
;.-=:
640
672
>
\-
704
(41
(181 Q
fbl
~(17
...
Cl
L-,\-
~6
768
800
832
864
896
928
>--->
960
tt
tt
tt
'"";::) (161
v
Cl
(51 992
>1024
1056
1088
1120
1152
1184
1216
-~
p-
>-;]
(15
~
....
(14
Cl
(61'248
1280
\------,
1312
'344
>--- >
1376
'408
'440
1472
Cl
(71'504
1536
'588
1600
>--
16321664
\-
1696
1728 .
">-
fbl
~(13
Cl
(81 1760
1792
1824
>~f2 '"
'856
1888
1920
1952
t-
'984
Cl
(912~
I
I
Fuse number - First Fuse number
2-422
...
Cl
480
Ek-
~
+
I
~
I
Increment
. TEXAS'"
INSTRUMENTS
'POST OFFICE BOX 665303. DAUAS. TEXAS 7628&
Q
TlCPAl16l8·55C, TlCPAl16R4·55C
TlCPAl16R6·55C, TlCPAl16R8·55C
STANDARD CMOS PAl® CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC ........................................... -0.5 V to 7 V
Input voltage range, VI ....................................... - 0.5 V to VCC +0.5 V
Input clamp current, 11K (VI < 0 or VI > Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vcc) ............................. ±20 mA
Continuous output current, 10 (VO = 0 to Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 35 mA
Continuous current through VCC pin. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70 mA
Continuous current through GND pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 200 mA
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 75°C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds (J package) ............ 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (N package) ............ 260°C
recommended operating conditions
MIN
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
4.75
2
NOM
MAX
UNIT
5.25
V
V
0.8
I Clock high
I Clock low
tw
Pulse duration
tsu
Setup time, input or feedback before elK I
th
Hold time, input or feedback after CLK I
TA
Operating free-air temperature range
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 6515303 • DALLAS. TEXAS 76265
20
20
40
0
0
V
ns
ns
ns
75
°c
2-423
TlePAl16l8·55C, TlCPAl16R4·55C
TICPAl16R6·55C, TlCPAl16R8·55C
STANDARD CMOS PAl® CIRCUITS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
Vee
~
4.75 V.
10H
~
Vee
~
4.75 V.
10l
~
24 rnA (lor TTL)
Vee
~
4.75 V.
10l
~
4 rnA (lor CMOS)
Vee - 5.25 V.
Vee ~ 5.25 V.
IIH
Vee
~
5.25 V.
III
Vee
~
5.25 V.
lee(standbvl
Vee - 5.25 V.
ICC (operating)
I
Vee ~ 5.25 V.
I ~ 1 MHz to 25 MHz
*alec
VI ~ 0.5 V or 2.4 V.
Vee 5.25 V.
Other inputs at 0 V or VCC
TA
~
25°C.
Typt
0.5
0.4
Vo - 0.4 V
VI ~ Vee
VI ~ 0
VI - 0 or Vee.
VI ~ 0 to Vee.
~
pA
10
pA
-10
pA
1.4
pA
pA
rnA
.. MHz
2
1 MHz
V
10
-10
100
10 - 0
10 ~ O.
UNIT
V
3.86
Vo - 2.4 V
I
MAX
4
-4 rnA (for CMOS)
10ZH
10Zl
Ci
MIN
10H - 3.2 rnA (lor TTL)
Vee - 4.75 V.
3
rnA
pf
6
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) R1 = 200 n, R2 = 390 n, CL - 50 pf
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
frnax§
MIN
with leedback
16
w/o feedback
25
Typt
MAX
35
15
55
ns
22
ns
MHz
t~d
I. 1/0. or leedback
tpd
elKt
o or I/O
Q
ten
OEi
Q
15
25
ns
tdis
OEt
Q
15
25
ns
ten
tdis
lor 1/0
Qor 1/0
35
55
ns
I or 1/0
Qor 1/0
35
55
ns
tAli typical values are at Vee ~ 5 V. TA ~ 25°C.
*This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 or Vee.
§Irnax(with feedback)
2-424
UNIT
~
1
; Irnax(without feedback)
tsu + tpd (ClK to Q)
~~
tsu
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 865303 • DALLAS. TEXAS 76286
TlCPAl16l8-55C. TlCPAl16R4-55C
TlCPAl16R6-55C. TICPAl16R8-55C
STANDARD CMOS PAl® CIRCUITS
preload procedure for registered outputs
The output registers can be preloaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. All of the registers may
be preloaded simultaneously by following the steps below.
Step 1.
With Vee at 5 V and Pin 11 at VIH. raise Pin 1 to VIHH.
Step 2.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3.
Lower Pin 1 to VIL. then remove the output voltage. Preload can be verified by lowering Pin 11
to VIL and observing the voltage level at the output pins.
preload waveforms
\,-------'~
""'~
---.I
,
td
\,..-----VIL
:.-
'
I
I
I
I
~ 'V
V-'"
.J\.....~,:_______________..!:---~
vlL
-.:
I
I
~
PIN 11
I
I
td
I+-
--.:
I
I
:i44-----t preload _
I
I
1
td
I+-
I
,
I
,
~s----~~1
I,
,
i\ -:- -
I
VIH
VIL
I
~
td,.....
~,
'I
""-'
REGISTERED 1/0
,
---J8""---------------1L
VOH
VOL
preload parameters. T A
PARAMETERt
VIHH
Preload voltage on pin 1
IIHH
Av/At
Preload input current at pin 1
td
Setup and hold times
MIN
NOM
MAX
UNIT
12.5
3.2
13
4
13.5
4.8
mA
50
Voltage ramping (VIHHI
2
V
V/~s
~s
t Other test parameters and conditions are shown in recommended operating conditions and electrical characteristics tables.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-425
TICPAl16lB·55C, TICPAl16R4·55C
TICPAl16R6·55C, TICPAl16RB·55C
STANDARD CMOS PAl® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
Vcc
Sl
b
Rl
fROM OUTPUT _ ...._ _..._ _...._ TEST
UNDER TEST
POINT
R2
CL;: ::::
ISee Note AI
NOTES:
A. CL = includes probe and jig capacitance.
B. When measuring propagation times of 3-5tate outputs, 51 is closed.
FIGURE 1. LOAD CIRCUIT FOR THREE·STATE OUTPUTS
\~~ -
-
-----3.5V
INPUT 3 , 1 . 5 V
I.
I
J+-- tPLH--+f
I
I
IN·PHASE
OUTPUT
OUT·Of·PHASE
OUTPUT
:
~3V
I4--tPHL--.....,
I
Y,.5V
l
I
,::v--VOH
I
I
I+--tPHL~
I+--tPLH~
.
I'
.
' - _ _ _ _ _ _ _ _ _ _ _- J
VOL
VOH
1.5 V
-
-
- - VOL
VOLTAGE WAVEfORMS
NOTES:
A. When measuring propagation times of 3.-5tate outputs, S 1 is closed.
B. All input pulses are supplied by generators having the following characteristics: PRR :5 1 MHz, Zo
=
FIGURE 2. PROPAGATION DELAY TIMES, OUTPUT RISE AND FALL TIMES
2·426
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
50
n,
tr
=
6 ns.
TlCPAl16l8·55C, TlCPAl16R4·55C
TlCPAl16R6·55C, TICPAl16R8·55C
STANDARD CMOS PAl® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
f.5V
ClK
, , - ---3.5V
'----0.3 V
1
.....I - - - - - - t h - - - - - - - t ·...1
~tsu--.l
DATA
INPUT
~I
I
2.7 V
2.7 V
I
I
I I
~~~
1\1
I
------3.5V
I 1.5 V
I
0.3 V
I
~~~
1.5 V
0.3 V
0.3 V
VOLTAGE WAVEFORMS
NOTE:
Phase relationship between waveforms was chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR :s: 1 MHz, Zo = tr = 6 n5 , tf = 6 ns.
FIGURE 3. SETUP AND HOLD TIMES. AND INPUT RISE AND FALL TIMES
I
~
OE
1\1.5 V
.
3.5V
1.5 V
...J+ - - - - - - - - - - 0.3
I \.. _ _ _ _ _ _ _ _ _
OUTPUT
WAVEFORM 1
51 CLOSED
(See Note B)
:
V
14--- tplZ--+I
I+-- tpZl ~
I I
I
\1.5V
I
.....---~VCC
:
Y-£-0.5V
I.
1
-
1
I
Kt-O~;-VOH
I
I+--- tPZH---.I
OUTPUT
WAVEFORM 2
51 OPEN _ _ _ _ _ _ _ _....J
(See Note B)
.
I
1.5 V
t - - -- VOL
I
~O V
~tpHZ---.t
ten - tpZl or tpZH
tdis = tPlZ or tpHZ
VOLTAGE WAVEFORMS
NOTES:
A. All input pulses are supplied by generators having the following characteristics: PAR:s: 1 MHz, Zo = 50 fi, tr = 6 n5, tf = 6 ns.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
FIGURE 4. ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-427
TICPAl16lB·55C, TlCPAl16R4·55C
TlCPAl16R6·55C, TlCPAl16RB·55C
STANDARD CMOS PAL® CIRCUITS
PARAMETER MEASUREMENT INFORMATION
H'~~-~~~EL
_ _ _ _....,/,1.5
v
~5 ~
\"
'~4~----tw------~~
-
-
-
-
3.5 V
,-,- - - - - 0.3 V
...
i41------ t w - - - - - -...'
----""\ I
LOW-LEVEL
PULSE
,
\.5V
f5~
3.5 V
_ _ _ _ 0.3V
VOLTAGE WAVEFORMS
NOTES:
A. All input pulses are supplied by generators having the following characteristics: PRR
B. For clock inputs, f max is measured with input duty cycle == 50%.
FIGURE 5, PULSE DURATIONS
2-428
TEXAS . "
INSTRUMENlS
POST OFFlCE BOX 655303 • DALLAS. TEXAS 75265
:s
1 MHz, Zo == 50 fl, tr == 6 ns.
TICPAL22V10Z-25C, TlCPAL22V10Z-35C
EPIC ™ CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
D3323. SEPTEMBER 1989-REVISED DECEMBER 1989
•
24-Pin Advanced CMOS PAL
•
Virtually Zero Standby Power
JT AND NT PACKAGE
(TOP VIEW)
CLKJI
•
Propagation Delay Time
25 ns . . . Turbo Mode
35 ns ... Zero-Power Mode
•
Variable Product Term Distribution Allows
More Complex Functions to Be Implemented
.•
Each Output Is User· Programmable for
Registered or Combinatorial Operation,
Polarity, and Output Enable Control
•
Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
GND ......_....;.J-'
•
Preload Capability on All Registered Outputs
Allows for Improved Device Testing
•
UV Light Erasable Cell Technology Allows
for:
Reconfigurable Logic
Reprogrammable Cells
Full Factory Testing for
Guaranteed 100% Yields
•
•
VCC
1/0/0
1/010
110/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
1/0/0
FN PACKAGE
(TOP VIEW)
;;z
uQ Q
--' u >
UO 0
__ u·z
::::,::::,
4
3
2
1 28 27 26
25
6
24
23
Programmable Design Security Bit Prevents
Copying of Logic Stored in Device
Package Options Include Plastic DIP and
Chip. Carrier [for One-Time-Programmable
(OTP) Devices] and Ceramic Dual-In-Line
Windowed Package
1/0/0
1/0/0
110/0
22
NC
9
21
10
20
1/0/0
1/0/0
1/0/0
11
19
121314151617 18
description
NC- No internal connection
This CMOS PAL device features variable product
Pin assignments in operating mode
terms, flexible outputs, and virtually zero
standby power. It combines Tl's EPIC m. (Enhanced Processed Implanted CMOS) process with ultravioletlight-erasable EPROM technology. Each output has an OLM (Output Logic Macrocell) configuration allowing
for user definition of the output type. This PAL provides reliable, low-power substitutes for numerous highperformance TTL PALs with gate complexities between 300 and 800 gates.
The 'PAL22V10Z has 12 dedicated inputs and ten user-definable outputs. Individual outputs can be
programmed as registered or combinational and inverting or noninverting as shown in the Output Logic
Macrocell (OLM) diagram. These ten outputs are enabled through the use of individual product terms.
The variable product-term distribution on this device removes rigid limitation to a maximum of eight product
terms per output. This technique allocates from 8 to 16 logical product terms to each output for an average
of 12 product terms per output. The variable allocation of product terms allows for far more complex
functions to be implemented in this device than in previously available devices.
EPIC is a trademark of Texas Instruments
Incor~orated.
PRODUCTIOI DATA documents contain infarmation
curr••t as af publication dat•. Products confarm to
spacificatiDRs par the terms of TIXIS Instrumants
::=~i;~~r:1~1i ~=::i:r :.r::::~:rO:S not
Copyright © 1989. Texas Instruments Incorporated
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-429
TICPAL22V10Z-25C, TlCPAL22V10Z-35C
EPIC TM CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
description (continued)
With features such as the programmable OlMs and the variable product-term distribution, the
TICPAl22V10Z offers quick design and development of custom lSI functions. Since each of the ten output
pins may be individually configured as inputs on either a temporary or permanent basis, functions requiring
up to 21 inputs and a single output or down to 12 inputs and 10 outputs can be implemented with this
device.
Design complex·ity is enhanced by the addition of synchronous set and asynchronous reset product terms.
These functions are common to all registers. When the synchronous set product term is a logic 1, the
output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous
reset product term is a logic 1, the output registers are loaded with a logic 0 independently of the clock.
The output logic level after set or reset will depend on the polarity selected during programming.
Output registers of this device can be preloaded to any desired state during testing, thus allowing for full
logical verification during product testing.
The TICPAl22Vl0Z has internal electrostatic discharge (ESD) protection circuits and has been classified
with a 2000-V ESD rating tested under Mll-STD-883C, Method 3015.6. However, care should be exercised
in handling these devices, as exposure to ESD may result in a degradation of the device parametric
performance.
The floating gate programmable cells allow these PAL devices to be fully programmed and tested before
assembly to a.ssure high field programming yield and functionality. They are then erased by ultraviolet light
before packaging.
The TICPAl22V10Z-25C and TICPAl22V10Z-35C are characterized for operation from OOC to 75°C.
design security
The 'PAl22V1 OZ contains a programmable design security cell. Programming this cell will disable the read
verify and programming circuitry protecting the design from being copied. The security cell is usually
programmed after the design is finalized and released to production. A secured device will verify as if every
location in the device is programmed. Because programming is accomplished by storing an invisible charge
instead of opening a metal link, the '22V1 OZ cannot be copied by visual inspection. Once a secured device
is fully erased, it can be reprogrammed to any desired configuration.
2-430
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 76265
TICPAL22V10Z·25C, TlCPAL22V10Z·35C
EPle™ CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
functional block diagram (positive logic)
--t>
r
C1
J1S
SET
RESET
&
44.132
8
~
;,,1
OUTPUT
>----- P lOGIC
~ MACRO CELL
---...
C>
h
r- EN
---...
~
EN
r-
---...
~
EN
>-c-->
---...
V-
EN
h
V- EN
h
~
>
---...
r- EN
>-- >
V-
---...
V-
>-c-- >
---...
V- EN
h
V-
~I 10/G,
10
---...
r'""""[)
ClK/1
rE-
--<~
~
~
'\.,
h
14
h
---...
~
~
1~
'\.,
'"----
---...
---..
h
h
->
~
12
->
V-
16
>-c--p
V-
16
~-P
r-
14
~-
r
12
10
V-
8
-c-- f>
V-
h
D-4t;
f++-I10/G
D-4t;
f---!10/G
D-4t;
f++-I 10/G
C>-4I: ......110/G
~ .......110/G
EN
~ .......110/G
p...; r++110/G
EN
p...; f++-I10/G
~ f++1 10/G
EN
10
10
'\....,
10
denotes programmable cell inputs
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-431
TICPAL22V10Z·25C, TlCPAL22V10Z·35C
EPICTM CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
logic diagram (positive logic)
1
FIRSTCELl
0
NUMBER
4
8
,.
12
INCREMENT
20
24
28
32
3'
,
40
ASYNCHRONOUS RESET
0
I TO ALL REGISTERSI
:go
~
~.
23
CELL
P-580B
R-5809
=
44.
3:§,.
:!l3
~.
CELL
P·SS10
2
R·5811
92.
~J
MACRO
CELL
P-S812
R-58l3
3
-
1496
h
.
S
~~
MACRO
CELL
P·5814
R·581S
L-2156
~n
MACRO
CEll
,
P-SSt6
~
2904
~n
MACRO
--
p-
_.
,
CELL
P-sstS
R·58t9
'---
3652
~
W
~
-......
.L;:,t.c
4312
~~
MACRO
CELL
P-6820
~
~J
MACRO
CELL
,
P-S822
~
4884
'IE
:V
GlJ
CELL
P-5824
9
R-5825
5368
~~
CELL
I.
11
"
.
p-582e
R-5827
o
Programmable Cell Number = First Cell Number
2-432
+
Increment
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•
SYNCHRONOUS SET
lTD ALL REGISTERS}
TlCPAL22V10Z·25C. TlCPAL22V10Z·35C
EPICTM CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
output logic macrocell (OlM) description
A great amount of architectural flexibility is provided by the user-configurable macroce" output options.
The macroce" consists of a D-type flip-flop and two select multiplexers. The D-type flip-flop operates like
a standard TTL D-type flip-flop. The input data is latched on the low-to-high transition of the clock input.
The Q and Q outputs are made available to the output select multiplexer. The asynchronous reset and
synchronous set controls are available in a" flip-flops.
The select multiplexers are controlled by programmable cells. The combination of these programmable
cells will determine which macroce" functions are implemented. It is this user control of the architectural
structure that provides the generic flexibility of this device.
output logic macrocell diagram
OUTPUT LOGIC MACROCELL
-,
r--:M:-::-:UX~"'"
r-A-R--~R::::::~~r-;:--~:
I
I
~-+-""---I1D
,.--'----i>C1
ss
1:)----<._---10
1}
0
GO
3
1S
FROM CLOCK BUFFER
MUX
G1
I
I
I
I
-::hr:::se_t_
AR ""' asynchronous reset
~
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
J
2-433
TICPAL22V10Z·25C, TlCPAL22V10Z·35C
EPIC™ CMOS PROGRAMMABLE ARRAY LOGIC CIRCUIlS
output logic macrocell options
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
CELL
SELECT
S1
SO
0
0
0
1
0
1
1
1
FEEDBACK AND OUTPUT CONFIGURATION
o = erased cell
Register feedback
Registered
Active low
Register feedback
Registered
Active high
I/O feedback
Combinational
Active low
I/O feedback
Combinational
Active high
1
= programmed
cell
81 and SO are select-function cells as shown in the output logic macrocell
diagram.
S1 = 0
SO - 0
SI - 0
SO - 1
REGISTER FEEDBACK. REGISTERED. ACTIVE-LOW OUTPUT
REGISTER FEEDBACK. REGISTERED. ACTIVE-HIGH OUTPUT
SI - 1
SO - 0
I/O FEEDBACK. COMBINATIONAL. ACTIVE-LOW OUTPUT
2-434
SI - 1
SO - 1
I/O FEEDBACK. COMBINATIONAL. ACTIVE-HIGH OUTPUT
TEXAS . "
INSTRUMENTS
POST OfFICE BOX 655303 • DAllAS. TEXAS 75265
TlCPAL22V10Z-25C. TICPAL22V10Z-35C
EPICTM CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Supply voltage range, vee. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5 to 7 V
Input voltage range, V, (see Note 1) ............................... -0.5 to Vee + 0.5 V
Input diode current, 11K (V, < 0 or V, > Vee). . . . . .
± 20 mA
Output diode current, 10K (VO < 0 or Vo > Vee) . . . . . . . . . . . . . . . . . . . . . . . . .
±20 mA
eontinuous output current, 10 (VO = 0 to Vee) . . . . . . . . . . . . . . . . . . . . . . . . . . .
±40 mA
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: FN or NT package ........ 260 0 e
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: JT package ............. 300 0 e
Operating free-air temperature range ..................................... ooe to 75°e
Storage temperature range ......................................... - 65 °e to 150 0 e
tStresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended
operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Note 1: This rating applies except during programming and preload cycles.
recommended operating conditions
-25C
VCC
Supply voltage
VIH
High-level input voltage
Vil
Low-level input voltage
IOH
High~level
IOl
output current
Low-level output current
tw
Pulse duration
ClK low
Asynchronous reset inactive
Input or feedback
Setup time, zero-power mode
Asynchronous reset inactive
Synchronous preset inactive
th
Hold time
TA
Operating free-air temperature
NOM
MAX
4.75
2
5
5.25
4.75
2
5
5.25
Input or feedback
10
10
20
17
20
20
25
30
30
0
0
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
75
15
15
25
25
30
30
35
40
40
0
0
UNIT
V
V
0.8
-3.2
-4
16
4
0.8
-3.2
-4
16
4
Driving CMOS
Synchronous preset inactive
tsu
MIN
Driving CMOS
Asynchronous reset
Setup time, turbo mode
MAX
Driving TTL
Input or feedback
tsu
NOM
Driving TTL
elK high
-35C
MIN
V
mA
mA
ns
ns
ns
ns
ns
ns
75
·C
2-435
TICPAL22V10Z-25C, TICPAL22V10Z-35C
EPIC 1M CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
-25C
TEST CONDITIONS
=
=
4.75
Vee
4.75
Vee - 4.75
Vee = 4.75
Vee = 5.25
Vee = 5.25
Vee = 5.25
Vce = 5.25
Vee = 5.25
Vee = 5.25
Vee
VOH
VOL
10ZH
10Zl
IIH
III
10*
VI
Ci
f
10H
V,
V,
V,
V,
V,
V,
V,
V,
I All
= 2 V,
= 1 MHz
=
=
Typt
4.8
4.7
0.25
0.07
0.01
-0.01
0.01
-0.01
-30
-45
10
-35C
MAX
4
3.86
-3.2 rnA for TTL
10H
-4 rnA for eMOS
10l - 16 rnA for TTL
10l = 4 rnA for eMOS
Vo = 2.7 V
Vo = 0.5 V
VI = 5.25 V
VI = 0.5 V
Vo = 0.5 V
VI = 0 or Vee,
V,
V,
Outputs open §
lec
(Zero-power mode)
MIN
MIN
MAX
4
3.86
UNIT
0.5
0.4
10
-10
10
-10
-90
4.8
4.7
0.25
0.07
0.D1
-0.D1
0.01
-0.D1
-30
-45
0.5
0.4
10
-10
10
-10
-90
~
mA
100
10
100
~
6
10
inputs
I All 1/0 pins
Typt
V
V
6
10
V
V
~A
~A
~
pF
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (see Figure 4)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
-25C
Without feedback
f max '
With feedback
Turbo mode
tpd
tpd
Asynchronous
Zero-power mode
RESET
elKt
Turbo mode
ten
Zero-power mode
Turbo mode
tdis
Zero-power mode
50
28.5
66
55
16
21
18
23
10
15
20
15
17
Q
0
1.1/0
I. 0, 110
1,1/0
1,0,1/0
= 5 V, TA = 25 ac.
tThis parameter approximates lOS. The condition Vo
TYpt
0,1/0
1,1/0
Zero-power mode
Turbo mode
tpd
MIN
-35C
t All typical values are at Vce
= 0.5
V takes tester noise into account.
§Disabled outputs are tied to GND or Vec.
'f max (with feedback)
2-436
=
tsu
1
+ tpd (ClK to 0)
; f max (without feedback)
=
tw(hi)
1
+ tw(low)
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MIN
TYpt
33
20
25
35
30
40
18
47
38
22
28
.24
31
14
35
45
40
50
25
25
35
25
35
21
27
21
25
35
45
35
45
MAX
MAX
UNIT
MHz
ns
ns
ns
ns
ns
TICPAL22V10Z·25C, TlCPAL22V10Z·35C
EPIC 1M CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
preload procedure for registered outputs
The output registers can be pre loaded to any desired state during device testing. This permits any state
to be tested without having to step through the entire state-machine sequence. Each register is preloaded
individually by following the steps given below. The output level depends on the polarity selected during
programming.
Step
Step
Step
Step
1. With VCC at 5 volts and pin 1 at V'L, raise pin 8 to V,HH.
2. Apply either VIL or V,H to the output corresponding to the register to be preloaded.
3. Pulse pin 1, clocking in preload data.
4. Remove output voltage, then lower pin 8 to V,L. Preload can be verified by observing the voltage
level at the output pin.
preload waveforms (see Note 2)
PIN 8
~-
/
---f
~tsu-+t
~td---+l
eLK/1
:1
t4- t d-+l
-
-
I'
I
I
I
REGISTERED 1/0 ~
)
1
VIH
\J -VIH
INPUT
I
- vlL
~
tsu
~
tw
~
VIL
!- - -1:- ----
~
NOTE 2: td
VIHH
iii
i+-tw-+l
•
I
I
-
VIL
I
I
V , . . - - - VOH
\
OUTPUT
' - - - - - - VOL
100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V.
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specification, algorithms, and the lastest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-437
TICPAL22V10Z-25C, T1CPAL22V10Z-35C
EPICTM CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
PARAMETER MEASUREMENT INFORMATION
SV
~
Sl
(See Note Al
3000
fROM OUTPUT _
UNDER TEST
...._ _~_ _..._ TEST
POINT
3900
CL
(See Note BI
NOTES: A. When measuring propagation times of 3-state outputs, S1 is closed.
B. CL includes probe and jig capacitance and is 50 pF for tpd and ten and 5 pF for tdis.
FIGURE 1. LOAD CIRCUIT FOR THREE-STATE OUTPUTS
INPUT
ISee Notes A and BI
----Ii.Ll
tpd
=
tPLH or tpHL
I
I
OUT·Of·PHASE
OUTPUT
-
-
-
-
-
I
I
-
3.5 V
0.3 V
I
1
:
-
I+--tPHL~
j4--tPLH--+!
IN·PHASE
OUTPUT
~S ~
\
5 V
I
'V:v--VOH
11.SV
I
I
I+--tPHL~
I+--tPLH~
\1.5
.
I
VOL
I
V
'-------------
VOH
1.S V
-
-
- - VOL
VOLTAGE WAVEFORMS
NOTES: A. When measuring propagation times of 3-state outputs, S1 is closed.
B. All input pulses are supplied by generators having the fol/owing characteristics: PRR =::;: 1 MHz, Zo = 500, tr = tf
FIGURE 2. PROPAGATION DELAY TIMES. OUTPUT RISE AND FALL TIMES
2-438
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
= 2 ns.
TICPAL22V1DZ-25C, TlCPAL22V1DZ-35C
EPICTM CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
PARAMETER MEASUREMENT INFORMATION
ClK
(See Notes A and BI
'\----
f·sV
____________J
~14~-------th--------~.~1
3.S V
0.3 V
~tsu--+l
DATA
INPUT
(See Note Al
I
-----------_1
~I
~I
I
1.S V
0.3 V
,-----3.SV
2.7 V
2.7 V
I
-----------------l
I I
~~~
loS V
~0:,;;.3::...:V--- 0.3 V
~q~
VOLTAGE WAVEFORMS
FIGURE 3. SETUP AND HOLD TIMES. AND INPUT RISE AND FALL TIMES
DATA=>(
, . - - - - - - - - - - 3.S V
...JXI
INPUT
....
l._S_V_ _ _ _ _ _ _ _ _ _
(See Note A l l .
(
I I
I
I
\15 V
I
0.3 V
14--- tplZ--+I
I+-- tpZl ---..,
OUTPUT
WAVEFORM 1
Sl CLOSED
(See Note CI
1.S V
.
I
,,-._ _ _
:
1-£-0.5
I.
1
-
I
I
I+--- tPZH----..I
V
f" - - -- VOL
...y
wAv~1~~~~~ _ _ _ _ _ _ _ _~1"1-.s-v-----1-----"K-L0~:- (See Note CI
I
.
2.BV
I
VOH
0 V
14--- tpHZ---+I
ten = tpZl
0'
tpZH
tdis - tplZ or tpHZ
VOLTAGE WAVEFORMS
FIGURE 4. ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
HI~~'~:~EL _ _ _ _ _Jf,1.5 V
\115 -: -----
~14~----tw------~~
3.5 V
\..- - - - - - - - - 0.3 V
MI4~-----tw------~.1
I
LOW-LEVEL
PULSE
\.SV
1
fs~
3.S V
----0.3V
VOLTAGE WAVEFORMS
FIGURE 5. PULSE DURATIONS
NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR:s 1 MHz, Zo = 500, tr = tf = 2 ~s.
B. For clock inputs, f max is measured with input duty cycle = 50%
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-439
TICPAL22V10Z-25C, TICPAL22V10Z-35C
EPIC TM CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
special design features
True CMOS Outputs: Each TICPAL22V10Z output is designed with a P-channel pull-up transistor and an
N-channel pull-down transistor, a true CMOS output with rail-to-rail output switching. This provides direct
interface to CMOS logie, memory, or ASIC devices without the need for a pull-up resistor. The CMOS
output has 16-mA drive capability, which makes the TICPAL22V1 OZ an ideal substitute for bipolar PALs.
The electrical characteristics of this device show the output under both CMOS and TTL conditions.
Simultaneous Switching: High-performance CMOS devices often have output glitches on nonswitched
outputs when a large number of outputs are switched simultaneously. This glitch is commonly referred
to as "ground bounce" and is most noticeable on outputs held at VOL (low-level output voltage). Ground
bounce is caused by the voltage drop across the inductance in the package lead when current is switched
(dv ex I x di/dt).
One solution is to restrict the number of outputs that can switch simultaneously. Another solution is to
change the device pinout such that the ground is located on a low-inductance package pin. TI opted for
a third option in order to maintain pinout compatibility and eliminate functional constraints. This option
controls the output transistor turn-on characteristics and puts a limit on the instantaneous current available
to the load, much like the lOS resistor in a TTL circuit.
Wake-Up Features: The TICPAL22V1 OZ employs input signal transition detection techniques to powerup the device from the standby-power mode. The transition detector monitors all inputs, II0s, and feedback
paths. Whenever a transition is sensed, the detector activates the power-up mode. The device will remain
in the power-up mode until the detector senses that the inputs and outputs have been static for about
40 ns; thereafter, the device returns to the standby mode.
Turbo Mode or Zero-Power Mode: When the turbo cell is programmed, the device will be set to the power-up
mode. Therefore, the delay associated with its transition detection and power up will be eliminated. This
is how the faster propagation delays and shorter setup times are obtained in the turbo mode. The turbo
mode and the associated speed increase can be effectively simulated with the turbo cell erased, if a series
of adjacent input, 1/0, or feedback edges occur with an interval of about 25 ns or less between these
adjacent edges. Under these conditions, the TICPAL22V1 OZ will never have the opportunity to power down
due to the frequency of the adjacent edges.
Power Dissipation: Power dissipation of the TICPAL22V10Z is defined by three contributing factors, and
the total power dissipation is the sum of all three.
Standby Power: The product of VCC and the standby ICC. The standby current is the reverse current
through the diodes that are reversed biased. This current is very small, and for circuits that remain
in static condition for a long time, this low amount of current can become a major performance
advantage.
Dynamic Power: The product of VCC and the dynamiC current. This dynamic current flows through
the device only when the transistors are switching from one logiC level to the other. The total dynamic
current for the TICPAL22V1 OZ is dependent upon the users' configuration of the PAL and the operating
frequency. Output loading can be a source of additional power dissipation.
Interface Power: The product of ICC (interface) and VCC. The total interface power is dependent
on the number of inputs at the TTL VOH level. The interface power can be eliminated by the addition
of a pull-up resistor.
Even though power dissipation is a function of the user's device configuration and the operating
frequency, the TICPAL22V10Z is a lower powered solution than either the quarter-powered or halfpowered bipolar devices. The virtually zero standby power feature makes the TICPAL22V10Z the
device of choice for low-duty-cycle and battery-powered applications.
2-440
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TICPAL22V10Z·25C, TICPAL22V10Z·35C
EPICTM CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
programming and erasability
Programming of the TICPAL22V1 OZ is achieved through floating-gate avalanche injection techniques. The
charge trapped on the floating gate remains after power has been removed, allowing for the nonvolatility
of the programmed data. The charge can be removed by exposure to light with wavelengths of less than
400 nm (4000 A). The recommended erasure wavelength is 253.7 nm (2537 AI. with erasure time of
60 to 90 minutes, using a light source with a power rating of 12000 ".W/cm 2 placed within 2.5 cm (1 inch)
of the device.
The TICPAL22V1 0 is designed for programming endurance of 1000 write/erase cycles with a data retention
of ten years. To guarantee maximum data retention, the window on the device should be covered by an
opaque label. The fluorescent light in a room can erase a unit in three years or, in the case of a direct
sunlight, erasure can be complete in one week.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-441
TlCPAL22V10Z-25C, TICPAL22V10Z-35C
EPIC'" CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
400
1.4
!-VCC = 5 V
200 I- TA = 25°C
~ 1.1
i'..
..,'"
"i
c
60
--.:::: ~
.,'"
~
..
2
..,..
40
Q.
~ ......
.......
Do.
u
.!:!
20
(ij
Turbo Bit off:
0
. - ClK to
~
I
1 k
10 k
100 k
1 M
10 M 100 M
a
A = I Turbo ~ode
4.75
I
5
VCC-Supply Voltage-V
Fclock - Clock Frequency- Hz
FIGURE 9
FIGURE 8
TEXAS
~
- • = Zero-Power Mode
Z
0.90
100
2-442
~
til
a.
1.1
I
.!.
!
:;
u
75
TA -Free-Air Temperature- °C
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5.25
TICPAL22V1DZ-25C. TlCPAL22V1DZ-35C
EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
TM
DELTA PROPAGATION TIME
vs
LOAD CAPACITANCE
NORMALIZED PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
30
1.2
.,c:
.
I
VCC - 5 V
CL-50pF
R1 = 300 Il
R2-3901l
1.15
E
i=
....
a;
~
1.1
Q
c:
0
"i
.'"
~
1.05
Co
e
a..
".!:!"
iii 0.95
E
4
/'
/
..
20
...I
.!!
~~
Q
c:
..,0
..
'"
V"
15
/V
Co
e
a.. 10
:!
Qj
Q
25
50
5
P~
0
o
75
Z
/t"
tPLHL
o=
0.9
o
25
.-CLKtoQ
Zero-Power Mode
{J = Turbo Mode
V
0
z
.,c:
VCC = 5 V
TA = 25°C
R1 = 300 Il
R2 - 390 Il
~
V
f--V
~V
100 200 300 400 500 600 700 800
TA -Free-Air Temperature- °C
CL -Load Capacitance-pF
FIGURE 10
FIGURE 11
DELTA PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
1.5
VCC = 5 V
TA - 25°
CL - 50 pF
R1 = 300 Il
R2 = 390 Il
Registered Macrocell
In
c:
....I
Qj
Q
..,.oc:
tpHL
.'"
Co
£ 0.5
tpLH
--I I--
o
o
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
FIGURE 12
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-443
•
2-444
TIEPAl10H16ET6C
ECl-TO-TTL IMPACT-XTM PAL ® TRANSLATOR CIRCUIT
1989
JTPACKAGE
• ECl 10KH Programmable logic with
ECl-to-TTl Translation
(TOP VIEW)
• ECl Control Inputs
GND
LE
• 3-State TTL Outputs
0
0
0
• Reliable Titanium-Tungsten Fuses
• Package Options Include Both 300-mil
Ceramic DIP and Plastic Chip Carrier
GND
GND
0
0
0
description
The
TIEPAL10H16ET6C
combines
the
IMPACT-X'" (Advanced Implanted, Advanced
Composed)
technology
with
proven
titanium-tungsten fuses to provide a reliable
high-performance substitute for conventional ECl
1OKH logic. Easy programmability allows for quick
design of custom functions with increased logic
density.
The TIEPAl 1OH16ET6C accepts ECl input levels
and provides TTL output levels, making it ideal for
interfacing ECl circuits with TTL circuits. It has
latched outputs controlled by a latch Enable (lE)
input at the ECl inputs. The 3-state outputs are
enabled by an Output Enable (OE) input from a
single ECl input. The TTL outputs are designed
for 24-mA low-level output current.
The TIEPAL10H16ET6C is provided with an
output polarity fuse that, if blown, will allow an
output to assume a logic high when the
implemented equation is satisfied. However, when
the output polarity fuse is intact and the
implementation equation is satisfied, the output
will assume a logic low.
OE
VEE
VCC
FN PACKAGE
(TOP VIEW)
o
__ :$'~
5
6
7
NC
4
8
9
10
aI~
3=
w
0
0
~
3 2 1 282726
25
24
23
22
21
20
a:
a.
~
11
19
121314 15161718
:::l
C
o
a:
a.
NC-No internal connection
The TIEPAL10H16ET6C is equipped with a security fuse. When the security fuse is blown, additional
programming and verification cannot be performed. This safeguards against easy duplication of a design.
The three GND pins must all be tied externally to an adequate ground plane for proper operation of this device.
The TIEPAl1 OH16ET6C is characterized for operation from O°C to 75°C.
PAL is a registered trademark of Monolithic Memories, Inc.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW documents contain information on
::.
g~a~~~:':~t:~~:!!:~~~I~~h~~ ~e:~Hrcft~:~: ~~~~~"n";~~::
Texas Instrumenl$ reserves the right to change or
discontinue these products without notice.
-If
INSIRUMENTS
TEXAS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
Copyright © 1989. Texas Instruments Incorporated
2-445
TIEPAL10H16ET6C
ECL-TO-TTL IMPACT-X™ PAL ® TRANSLATOR CIRCUIT
logic diagram t
INCREMENT
r~0~--~4--~---1-2--JA~i6~~2~0--~~~~2~8~31~'
24 G
I;
II
1280
-
1504
m
1
17
o
ECUTTL
16
o
~ENECUTTL
15
o
~
~
.
-~p1DJF
~
=;~F
ECUTTL
= First Fuse Number + Increment
An exclusive-NOR input grounded through an intact polarity fuse is at an Eel high logic level.
TEXAS ."
INSTRUMENTS
POST OFFICE
o
~~r>"
~~~F
2-446
20
"
ECUTTL
ECUTTL
10~
Fuse Number
o
~
11~
t
21
~
~
w
W
5
25
6
24
7
23
8
22
NC
9
21
o
10
20
1/0
11
19
Veeo
a::
ato
::::>
121314 15 16 17 18
c
wu
~2
oa::
NC - No internal connection
a-
The TIEPAL1 OH 16P8-3 is equipped with a
security fuse. Once the security fuse is blown,
additional programming and verification cannot
be performed. This prevents easy duplication of
a design.
This device is characterized for operation from OOC to 75°C; this temperature range is designated by a
"c" suffix in the part number (TIEPAl10H16P8-3CJT).
ExCl is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.
PRODUCT PREVIEW d••um••" ....tai. i.fo,mati••
DR products in the fonnativl or dBsign ,hasl of
development. Characteristic data anll othar
=~i:.at!=:1r~:t
d:i:h.:::'!,T3i!::~~:~:~::'~
preducts without nDtica.
Copyright
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
© 1989. Texas Instruments Incorporated
2-451
TlEPAl1 OH 16P8·3C
HIGH·PERFORMANCE ExCLTMPAL® CIRCUIT
functional block diagram (positive logic)
8
&
32 X 64
'"
8
8
12
4,
16X[>
16
16
rv
8
rv
8
8
8
8
4
""0
:tJ
o
C
c:
o
-I
""0
:tJ
m
-<
m
:a:
2·452
TEXAS ...,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
-
-1
rv
o
........ rv
o
........ rv
o
........
o
I'\.
........ rv
1/0
........ rv
1/0
........ rv
1/0
........ rv
Vee
1/0
TlEPAll0H16P8-3C
HIGH-PERFORMANCE EXCCM PAL® CIRCUIT
logic diagram (positive logic)
[281124)
VCC
INCREMENT
I
0
32
[2111)
1\
4
12
8
28
24
16
20
20
24
16
12
8
28
[271123)
---t>t=
[3112)
FIRST FUSE
NUMBERS
[26][22)
0
32
~811
""
'"
'"0
192
224
[4)(3)
[/0
[5114)
4
\
32
0
no
''"
l~
I/O
FIRST FUSE
NUMBERS
256
I
[25][21)
%2
]~:
'"
,eo
T
~
"2
->
W
-l
'"
,ce
676
~
on
'"
no
'"
[24)(20)
o
W
c:
c..
20'
o
....
800
832
[6][5)
eo,
86'
u
::::>
o
o
%,
'"
"2
2051
1024
1056
1088
112.0
1152
1184
1216
1248
o
~
[21][18)
~1I
(20][17)
o
c:
c..
[9][7)
~
1536
1568
1600
1632
1664
1696
1728
1760
(10][8)
I/O
T~J~
I
1792
1824
1856
1888
1920
1952
1~~~
[191116)
~
[11][9)
(18][15)
(12][10)
(17)(14)
(13][11)
I/O
....
....
~
Fuse Number = First Fuse Number + Increment
NOTE: Pin numbers in [ 1 are for the FK package; pin numbers in
[16][13)
l ) are for JT package.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-453
TIEPAL 10H16PIl·3C
HIGH·PERFORMANCE ExClTM PAl® CIRCUIT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
(see Note 1)
Supply voltage, VEE (see Note 2) ....................................... 0 V to -6.5 V
Input voltage, VI (see Note 3) ............................................ 0 V to VEE
Output current . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 50 rnA
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 75 DC
Storage temperature range ......................................... - 65 DC to 150 DC
NOTES:
1. These ratings apply except for programming pins during a programming cycle.
2. All voltage values are with respect to Vee and VCCO, i.e., these pins are all assumed to be at 0 volts.
3. VI should never be more negative than VEE.
recommended operating conditions (see Note 4)
VEE
MIN
-4.94
Supply voltage
TA
VIH
High-level input voltage
TA
TA
TA
"tJ
:xJ
o
C
C
o
-I
Vll
Low-level input voltage
TA
TA
TA
= ooe
= 25°C
= 75°C
= ooe
= 25°C
= 75°C
NOM
-5.2
-1.17
Operating free-air temperature
MAX
-5.46
UNIT
V
-0.84
-1.13
-0.81
-1.07
-1.95
-0.735
-1.48
-1.95
-1.48
-1.95
-1.45
0
75
V
V
°e
NOTE 4: The algebraic convention, in which the more negative li';'it is designated as minimum and the less negative limit is designated
as maximum, is used in this data sheet for logic voltage levels only. For other quantities, e.g. supply voltages and currents,
the normal magnitude convention is used.
1
electrical characteristics over recommended supply voltage range at specified free-air temperature
.
"tJ (see Notes 4 and 5)
:xJ
m
PARAMETER
:::m
TEST CONDITIONS
ooe
VOH
VI
:E
VOL
IIH
III
lEE
VI
=
=
VIHmin or Vllmax
VIHmin or Vllmax
VI
VI
= VIHmax
=
Vllmin
All inputs open
MIN
-1.02
TYP
MAX
25°C
-0.98 -0.895
75°e
ooe
-0.92
-0.735
-1.95
-1.63
25°C
-1.95
75°C
ooe
-1.95
-0.81
-1.63
-1.79
V
V
-1.60
220
25°C
220
75°C
ooe
220
25°C
75°C
ooe to 75°C
UNIT
-0.84
~
0.5
~A
0.5
0.3
-220
mA
NOTES: 4. The algebraic convention, in which the more negative limit is designated as minimum and the less negative limi.t is designated
as maximum, is used in this data sheet for logic voltage levels only. For other quantities, e.g., supply voltages and currents,
the normal magnitude convention is used·.
5. Each 10KH PAL has been designed to meet these specifications after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse air flow greater than 150 meters (500 feet) per minute
is maintained. Outputs are terminated through a 50-ohm resistor to -2 V.
2-454
TEXAS
~
INSlRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TlEPAl1 OH 16P8-3C
HIGH-PERFORMANCE ExClTM PAl@ CIRCUIT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(see Note 5)
PARAMETER
FROM
TO
(INPUT)
10UTPUT)
I, 1/0,
tpd
t,
0' feedback
TYP
MAX
UNIT
TEST CONDITIONS
MIN
1
3
ns
See Figures 1 and 2
0.7
1.5
ns
0.7
1.5
ns
0, I/O
tf
NOTE 5: Each 10KH PAL has been designed to meet these specifications after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse air flow greater than 150 meters (500 feet) per minute
is maintained. Outputs are terminated through a 50-ohm resistor to - 2 V.
PROGRAMMING INFORMATION
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
~
-w
>
W
PARAMETER MEASUREMENT INFORMATION
a:
INPUT
.$1" 5 - 0 - % - - - \ ; ' ; -
~
I
~
tpLH 1IN·PHASE
1
OUTPUT
I
f
-
l:t-I
50%
1
tPHL ~
1
OUT '()F.pHASE
\ 50%
OUTPUT.
I
t-
VIL
~IPHL
-j
c.
VIH
VOH
\:.. o;n",
~
I
vOL
I4---*-tPLH
OUTPUT
WAVEFORM
F
I VOH
50%
VOL
BOA
20%
1
I I
I 1
I,~
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1\.0%1--
:
1 1
I+-
120%1
1 1
VOH
V
OL
O
:::J
C
o
a:
c.
--.I I+- If
VOLTAGE WAVEFORMS
RISE TIME AND FALL TIME
FIGURE 1. VOLTAGE WAVEFORMS
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
2-455
TlEPAl1 OH 16P8·3C
HIGH·PERFORMANCE ExCLTM PAL® CIRCUIT
PARAMETER MEASUREMENT INFORMATION
2.00 V ± 0.01 V
O.lI'F
q
INPUT
OUTPUT
UNDER
TEST
t-t-t----++........... UNDER
TEST
v._ .,v{
"'0
:x:J
o
or
VIL min
C
C
+2
V
} {
ALL
OTHER
INPUTS
(')
VEE
-I
r
"'0
m
:e
'::'
251'F
:x:J
:S
m
."
OTHER
OUTPUTS
O.lI'F
q
-3.20 V ± 0.01 V
NOTES: A. The offset voltage generator has the following characteristics: Pulse amplitude
t r = tf = 1 ns.
= 800 mV poP, PRR s
1 MHz, tw
B. RT is a 50-0 terminator internal to the oscilloscope.
C. CL :::so 3 pF, includes fixture and stray capacitance.
D. Coax has 50-IJ impedance and the coax to oscilloscope channel A and to channel 8 must be of equal lengths.
E. All unused outputs are loaded with 50-IJ ± 1 % resistors to ground.
F. All unused inputs should be connected to either high or low levels consistent with the logic function required.
G. All fixture wire lengths or unterminated stubs should not exceed 6 mm (1/4 inch).
FIGURE 2. LOAD CIRCUIT
2-456
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
= 500 ns,
TlEPAl10H16PB-6C
HIGH-PERFORMANCE IMPACpMECl PAl® CIRCUIT
02916, MAY 1987-REVISEO SEPTEMBER 1989
TIEPAL10H16P8-6". JT PACKAGE
(TOP VIEW)
•
ECl 10KH PAL
•
High-Performance Operation
Propagation Delay , . , 6 ns Max
•
Replacement for Conventional ECl logic
•
24-Pin, 300-Mil Package
•
Vee
I
1/0
1/0
a
a
Reliable Titanium-Tungsten Fuses
veeo
a
Veeo
a
description
1/0
1/0
This IMPACr" ECl PAL device uses proven
titanium-tungsten fuses to provide reliable, highperformance substitutes for conventional EGl
logic. Its easy programmability allows for quick
design of "custom" functions and typically
results in a more compact board. In addition, chip
carriers are available for further reduction in
board space.
TIEPAL 10H16P8-6 ... FK PACKAGE
nop VIEW)
u
u u
z>_
The TIEPAl1 OH 16P8-6 is provided with output
polarity fuses. Each output remains active-high
when the fuse is intact and is active·low when
the fuse is blown.
The TIEPAl 10H16P8-6 has 12 dedicated inputs,
four standard outputs, and four 1/0 ports. It
should be noted that with emitter-coupled
outputs, a high level overrides a low level.
Therefore, in order to use an 110 port as an input,
the related output must be forced to a low level
either through satisfying preprogrammed
equations or permanently by programming.
The TIEPAL1 OH16P8-6 is equipped with a
security fuse. Once the security fuse is blown,
additional programming and verification cannot
be performed. This prevents easy duplication of
a design.
4
3
2
1 28 27 26
1/0
a
25
24
6
Veeo
23
Vee a
Ne
a
8
22
9
21
Ne
a
1/0
I
10
20
1/0
11
19
121314151617 18
wu
~z
NC - No internal connection
This device is characterized for operation from OOG to 75°G; this temperature range is designated by a
"G" suffix in the part number (TIEPAL1 OH16P8-6GJT).
IMPACT is a trademark of Texas Instruments Incorporated
PAL is a registered trademark of Monolithic Memories Inc.
PRODUCTION DATA doc.menls contain information
currant IS of publication date. Products conform to
specifications par the terms of Taxas Instruments
:~~=~i~at::I~Ji ~~:~~~i:r :1~D::~:::t:~~ nat
~
TEXAS
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright © 1989. Texas Instruments Incorporated
2-457
TlEPAl10H16PB·6C
HIGH·PERFORMANCE IMPACpMECl PAl® CIRCUIT
functional block diagram (positive logic)
8
&
32 X 64
;;"
8
8
12
4,
16X&>
16
16
-
=1
o
...- tV
...- tV
o
8
tV
~
'\.
~
tV
~
tV
~
tV
~
tV
8
tV
B
B
vee
4
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
o
~
8
2·458
o
tV
1/0
1/0
1/0
1/0
TlEPAl10H16P8-6C
HIGH-PERFORMANCE IMPACT'MECL PAL@ CIRCUIT
logic diagram (positive logic)
1281124)
VCC
INCREMENT
1\
!
0
32
[2111)
4
12
8
28
24
16
20
16
20
24
12
8
28
4
\
32
0
~
[3112)
FIRST FUSE
NUMBERS
0
%
128
160
192
224
1Q8!I
t
1/0
[261122)
-u
"'
[4113)
[5114)
[271123)
K
X
1/0
F)RST FUSE
NUMBERS
256
'"
:120
Tg<
[251121)
l!,2
384
""
''"
"eo
I
~12
544
en
~
[241120)
=3~2
[211118)
j~-!
[201117)
,<0
''"
672
'"
736
a
7G8
a
"'0
832
[6115)
'"
9n
896
%6
2051
a
'"
~
a
[9117)
2053
1536
1568
1600
1632
1664
1696
1728
1760
'](
[10118)
1/0
l~
I
I
[191116)
[11119)
[181115)
[121110)
;..
[131111)
:::
[171114)
~.
....
Fuse Number . . ,. . First Fuse Number
1/0
[161113)
+ Increment
NOTE: Pin numbers in [ 1 are for the FK package; pin numbers in ( } are for JT package.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-459
TlEPAl1 OH 16PB-6C
HIGH-PERFORMANCE IMPACT™ECL PAL® CIRCUIT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
(see Note, 1 )
Supply voltage, VEE (see Note 2) , ...................................... 0 V to - 6.5 V
Input voltage, VI (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 V to VEE
Output current ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 50 mA
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 75°C
Storage temperature range ......................................... - 65°C to 1 50°C
NOTES:
1. These ratings apply except for programming pins during a programming cycle.
2. All voltage values are with respect to
Vee and VCCO. i.e., these pins are all assumed to be at 0 volts.
3. VI should never be more negative than VEE.
recommended operating conditions (see Note 4)
VEE
Supply voltage
TA - OOC
VIH
High-level input voltage
TA
TA
TA
VIL
Low-level input voltage
TA
TA
TA
= 25°C
= 75°C
= OOC
= 25°C
= 75°C
Operating free-air temperature
MIN
NOM
MAX
-4.94
-5.2
-5.46
-1.170
-0.840
-1.130
-0.810
-1.070
-0.735
-1.950
-1.480
-1.950
-1.480
-1.950
-1.450
0
75
UNIT
V
V
V
°C
NOTE 4: The algebraic convention, in which the more negative limit is designated as minimum and the less negative limit is designated
as maximum, is used in this data sheet for logic voltage levels only. For other quantities, e.g., supply voltages and currents,
the normal magnitude convention is used.
electrical characteristics over recommended supply voltage range at specified free-air temperature,
Vee = Veeo = 0 (see Notes 4 and 5)
PARAMETER
VOH
VOL
IIH
IlL
lEE
TEST CONOITIONS
VI
VI
=
=
VIHmin or VILmax
VIHmin or VILmax
VI
VI
= VIHmax
=
VILmin
All inputs open
TA
O°C
MIN
MAX
-1.020
-0.840
25°C
-0.980
-0.810
75°C
-0.920
-0.735
O°C
-1.950
-1.630
25°C
-1.950
-1.630
75°C
OOC
-1.950
-1.600
V
V
220
25°C
220
75°C
220
O°C
0.5
25°C
0.5
75°C
0.3
OOC to 75°C
UNIT
~A
pA
-240
rnA
NOTES: 4. The algebraic convention, in which the more negative limit is designated as minimum and the less negative limit is designated
as maximum, is used in this data sheet for logic voltage levels only. For other quantities, e.g., supply voltages and currents,
the normal magnitude convention is used.
5. Each 10KH PAL@ has been designed to meet these specificati'ons after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse air flow greater than 150 meters (500 feet) per minute
is maintained. Outputs are terminated through a 50-ohm resistor to - 2 V.
2-460
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 ,. DALLAS. TEXAS 75265
TlEPAl10H16P8·6C
HIGH·PERFORMANCE IMPACTTMECL PAL® CIRCUIT
switching characteristics over recommended ranges of supply voltage and operating free·air temperature
(see Notes 4 and 5)
FROM
TO
(INPUT)
(OUTPUT)
I, 110, or feedback
Q
PARAMETER
tpd
TEST CONDITIONS
See Figures 1 and 2
tr
tf
MIN
TYP
MAX
2
4
0.7
0.7
1
6
2.2
2.2
1
UNIT
ns
ns
ns
NOTES: 4. The algebraic convention, in which the more negative limit is designated as minimum and the less negative limit is designated
as maximum, is used in this data sheet for logic voltage levels only. For other quantities, e.g., supply voltages and currents.
the normal magnitude convention is used.
5. Each 10KH PAL(!l has been designed to meet these specifications after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse air flow greater than 150 meters (500 feet) per minute
is maintained. Outputs are terminated through a 50-ohm resistor to - 2 V.
PROGRAMMING INFORMATION
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 995·5666.
PARAMETER MEASUREMENT INFORMATION
$,~5-0-%--"""'\;~- -
INPUT
--.Jt
J....-
tpLH 1IN-PHASE
OUTPUT
1
,
,
~tPHL
-;
"
OUT '()F-PHASE
OUTPUT
VOH
I
VOL
I
tpHL~
VIL
l:t-)L "nq,
50% I
•
VIH
I
~
~tpLH
1
50%
\
OUTPUT
WAVEFORM
~I VOH
T
•
1 1
50%
-
801:I
20%
I 1
t r -,< I+-
VOL
~---VOH
(80%)
I
)
I ,
(20%)
v
OL
I )
-+I
I4-tf
VOLTAGE WAVEFORMS
RISE TIME ANO FALL TIME
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
FIGURE 1. VOLTAGE WAVEFORMS
TEXAS
"I
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. leXAS 75265
2-461
TIEPAL 1OH 16PS·6C
HIGH·PERFORMANCE IMPACTTMECL PAL® CIRCUIT
PARAMETER MEASUREMENT INFORMATION
2.00 V ± 0.01 V
0.1 "F
q
INPUT
OUTPUT
UNDER ~-4------t-+4~~
TEST
1--t-t-----+-+-4H UNDER
TEST
VIH max + 2 V {
or
VIL min + 2 V
}
ALL
OTHER
INPUTS
ALL
{
OTHER
OUTPUTS
0.1 "F
q
-3.20 V ± 0.01 V
NOTES: A. The offset voltage generator has the following characteristics: Pulse amplitude = 800 mV P·P. PRR s 1 MHz, tw = 500 ns,
tr = tf = 1 ns.
B. RT is a 50-0 terminator internal to the oscilloscope.
C.
D.
E.
F.
G.
CL :S 3 pF, includes fixture and stray capacitance.
Coax has 50-0 impedance and the coax to oscilloscope channel A and to channel B must be of equal lengths.
All unused outputs are loaded with 50-0 ± 1 % resistors to ground.
All unused inputs should be connected to either high or low levels consistent with the logic function required.
All fixture wire lengths or unterminated stubs should not exceed 6 mm (1/4 inch).
FIGURE 2. LOAD CIRCUIT
2-462
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TIEPAl10H16TE6C
TTL·TO·ECl IMPACT·X™ PAL ® TRANSLATOR CIRCUIT
JTPACKAGE
• ECl 10H Programmable logic with
TTl-to-ECl Translation
(TOP VIEW)
Vee
• ECl Control Inputs
I
• a-State ECl Outputs
• IMPACT-X'· Process with Reliable
Titanium-Tungsten Fuses
• Package Options Include Both a~O-mil
Ceramic DIP and Plastic Chip Carrier
description
The
TIEPAL10H16TE6C
combines
the
IMPACT-X'· (Advanced Implanted, Advanced
Composed Technology) process with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
ECL 10H logic. Easy programmability allows for
quick design of custom functions with increased
logic density.
The TIEPAl 1OH 16TE6C accepts TTL input levels
and provides ECL output levels, making it ideal for
interfacing TTL with ECl circuits. It has latched
outputs, which are controlled from an ECl Latch
Enable input, LEo The outputs are enabled from a
single ECL input, CE.
The TIEPAL10H16TE6C is provided with an
output polarity fuse that, if blown, allows an output
to assume a logic high when the implemented
equation is satisfied. However, when the output
polarity fuse is intact and the implemented
equation is satisfied, the output will assume a logic
low.
24
23
22
21
20
19
18
17
16
15
14
13
GND
LE
0
0
0
GND
GND
0
0
0
OE
GND
FN PACKAGE
;:
(TOP VIEW)
80 ~Iw
->WW
__ :>Z
-=
C1
~
/~"o
1539
~
>~ :L.)o--" o
TIL/ECLI.
~
C1
1540
"o
x">~C1
1541:L,)o-~
TIL/ECl~
TIL/ECl
Fuse Number = First Fuse Number + Increment
Pin numbers shown are for the JT package.
An exclusive-NOR input grounded through an intact polarity fuse is at an Eel high logic level.
2-464
1536
10
?~>~
~
TIL/EClL
..-----.
10
l
~
TIL/EClt
1280
9
GNO
o
>~-~
=L..,.»-=
"
1024
"tJ1
m
TIL/EClL
0768
I
23
TIL/ECL{::
IRST FUSE
NUMBER
4
rr-
TIL/ECY::
TEXAS ..If
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
~o
TIEPAL10H16TE6C
TTl-TO-ECl IMPACT-X™ PAL ® TRANSLATOR CIRCUIT
FUNCTION TABLE
INPUTS
OUTPUTS
OE
LE
ARRAY DATA
ot
0*
l
l
H
H
H
L
L
L
l
l
H
l
H
H
H
X
00
00
H
X
l
L
H
l
l
00
00
L
H
H
l
l
l
L
l
FEEDBACK
l
X = Don't care
t
= Polarity fuse blown
*=
ARRAY
DATA
Polarity fuse intact
---------110
o
C1
~
FEEDBACK - - - - - - - Q
FEEDBACK - - - - - - - 1
W
~
a:
FIGURE 1. SIMPLIFIED LOGIC DIAGRAM (EACH OUTPUT)
Q.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (see
Note 1)
ECl supply voltage range, VEE (see Note 2) .......................................... -7 V to 0.5 V
TTL supply voltage range, Vee ...................................................... -0.5 V to 7 V
ECl input voltage range ............................................................. VEE to 0.5 V
TTL input voltage ......................................................................... 5.5 V
Operating free-air temperature range, T A .............................................. O°C to 75°C
Storage temperature range ........................................................ -65'C to 150°C
t-
O
:::)
c
oa:
Q.
NOTES: 1. These ratings apply except for programming pins during a programming cycle.
2. All voltage values are with respect to the GND pins connected together.
TEXAS ."
INSIRUMENlS
POST OFFICE BOX 655303 • DAL.LAS. TEXAS 75265
2-465
TIEPAl10H16TE6C
TTL·TO·ECl IMPACT·XTM PAL ® TRANSLATOR CIRCUIT
recommended operating conditions (see Note 3)
MIN
NOM
MAX
UNIT
TTL supply voltage, VCC
4.75
5
5.25
V
ECl supply voltage, VEE
-4.95
-5.2
-5.46
V
2
5.5
V
-1.17
-0.84
TTL high·level input voltage, VIH
ECl high-level input voltage, VIH
I
(LE and OE inputs)
TA=O·C
I
I
TA = 25·C
-1.13
-0.81
TA = 75·C
-1.07
-0.735
I
I
I
TA = O·C
-1.95
-1.48
TA = 25·C
-1.95
-1.48
TA = 75·C
-1.95
-1.45
TTL low-level input voltage, Vil
0.8
(LE and OE inputs)
ECl low-level input voltage, Vil
'"'D
1::J
oC
V
V
V
Pulse duration, lE high, tw
3
ns
Setup time, data before lE! , tsu
4
ns
Hold time, data after lE!, th
0
Operating free-air temperature, TA
0
ns
75
·C
electrical characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted) (see Note 4)
PARAMETER
c:
TEST CONDITIONS
VCC=4.75V,
VIK
MIN
VI=-18mA
TA=O·C
VEE = -5.46 V,
VOH
£1
'"'D
1::J
VEE = -5.46 V,
VOL
~
IIHt
-
VI = VILmax or VIHmin
VI = Vilmax or VIHmin
I
VCC = 5.25 V,
VI = 2.7V
lE,OE
VEE = -5.46 V,
VI =VIHmax
I
VCC = 5.25 V,
VI = 0.4 V
lE,OE
VEE = -4.94 V,
VI =Vllmin
VCC =5.25V
VEE =-5.46V
lilt
ICC+ IEE~
-1.02
MAX
UNIT
-1.5
V
-0.84
TA = 25·C
-0.98
-0.81
TA=75·C
-0.92
-0.735
TA=O·C
-1.95
-1.63
TA = 25·C
-1.95
-1.63
TA = 75·C
-1.95
-1.6
20
220
-200
0.5
-220
V
V
!lA
!lA
rnA
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(see Note 4)
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
tpd
lEI
0
tpd
I or Feedback
0
ten
OE
0
tdis
OE
0
TEST CONDITIONS
MIN
TYP
5
See Figures 2 and 3
MAX
UNIT
ns
6
ns
4
ns
5
ns
t For ECl inputs, measure one input at a time with the other inputs open.
*
All inputs and outputs are open.
NOTES: 3. The algebraic convention, in which the more negative limit is deSignated as minimum and the less negative limit is designated as
maximum, is used in this data sheet for logic voltage levels only. For other quantities, e.g., supply voltages and currents, the normal
magnitude convention is used.
4. Each device has been designed to meet these specifications after thermal equilibrium has been established. The circu~ is in a test
socket or mounted on a printed circuit board and transverse airflow greater than 150 meters (500 feet) per minute is maintained. Outputs
are terminated through a 50-a resistor to -2 V.
2-466
TEXAS ."
INSIRUMENlS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
TIEPAl10H16TE6C
TTL·TO·ECl IMPACT·X™ PAL ® TRANSLATOR CIRCUIT
PARAMETER MEASUREMENT INFORMATION
INP~
t
3.5V
I
IpLH
IN-PHASE
OUTPUT
III
~I
I
....j{
I
I
I
I'
1
50%
I·
1
I
~
.L-...i• i
tpHL 1OUT·OF-PHASE
OUTPUT
3.5V---- 5.5V
I
14
I
\k'
.
2.3V
~I
IpHL
I
~50%
~II1
OUTPUT~O%
- - - - - VOH
WAVEFORM
VOL
50%
- -
20%
I
I
**-
IpLH
F'
50%
'------I.
VOH
1 80%
20%
1
Ir
~L
--.:-:.- If
VOLTAGE WAVEFORM
RISE TIME AND FALL TIME
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
FIGURE 2. VOLTAGE WAVEFORMS
~
~
a:
a.
o
;:)
c
o
a:
a.
TEXAS
..If
INSlRUMENlS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
2-467
TIEPAL10H16TE6C
TTL·TO·ECL IMPACT';'X™ PAL ® TRANSLATQR CIRCUIT
PARAMETER MEASUREMENT INFORMATION
2.00 V '" 0.01 V
25~F
.r+
7V
Vee
GND
INPUT
UNDER
TEST
~.,v{
'"'C
::a
o
c
or
VILmln+2V
}A~
OTHER
INPUTS
c:
-
~
A~{
OTHER
OUTPUTS
"::"
o-I
~
~
OUTPUT
UNDER
TEST
VEE
25 ~F
pr
0.1~
-3.20 V ,,0.01 V
==
NOTES: A. The offset voltage generator has the following characteristics: Pulse amplttude =800 mV poP, PRR" 1 MHz, tw =500 ns, tr tf 1 ns.
B. RT is a 50-0 terminator internal to the oscilloscope.
C. CL ~ 3 pF, includes fixture and stray capacitance.
D. The coaxial cables have 50-0 impedance and the cable lengths to oscilloscope channel A and to channel B must be equal.
E.AII unused outputs are loaded with 50-g" 1% resistors to ground.
F.AII unused inputs should be connected to either high or low levels consistent with the logic function required.
G.AII fixture wire lengths or unterminated stubs should not exceed 6 mm (1/4 inch).
FIGURE 3. TEST CIRCUIT
2-468
. TEXAS.
INSIRUMENlS
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
TIEPAL10016ET6C
ECL·TO·TTL IMPACT·XTM PAL ® TRANSLATOR CIRCUIT
OCTOBER 1989
• ECl 100K Programmable logic with
ECl-to-TTL Translation
JTPACKAGE
(TOP VIEW)
• ECl Control Inputs
• 3-State TTL Outputs
Vce
I
I
I
• IMPACT-X'· Process with Reliable
Titanium-Tungsten Fuses
• Package Options Include Both 300-mil
Ceramic DIP and Plastic Chip Carrier
I
description
1
2
3
4
5
6
7
B
The
TIEPAL10016ET6C
combines
the
IMPACT-X'· (Advanced Implanted, Advanced
Composed Technology) process with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
ECl 100K logic. Easy programmability allows for
quick design of custom functions with increased
logic density.
VEE
GND
GND
0
0
0
OE
Vcc
FN PACKAGE
(TOP VIEW)
~
~
IX:
~Iw--'0
__ ::> Z C!J
80
The TIEPAl 10016ET6C accepts ECl input levels
and provides TTL output levels, making it ideal for
interfacing ECl with TTL circuits. It has latched
outputs, which· are controlled by an ECl latch
Enable input, lE. The 3-state outputs are enabled
input from a Single ECl input, DE. The TTL
outputs are designed for 24-mA low-level output
current.
The TIEPAl10016ET6C is provided with an output
polarity fuse that, if blown, allows an output to
assume a logic high when the implemented
equation is satisfied. However, when the output
polarity fuse is intact and the implementation
equation is satisfied, the output will assume a logic
low.
9
10
11
12
GND
LE
0
0
0
4 321 282726
5
25
6
24
7
23
8
22
9
21
10
20
11
19
121314 1516 1718
0
0
GND
NC
GND
D.
ti
0
0
;:)
c
oIX:
- - WO 0IWO
~Z.y 0
NC - No internal connection
D.
The TIEPAl1 0016ET6C is equipped with a security fuse that, when blown, prevents additional programming
and design verification. This safeguards against easy duplication of a design.
The three GND pins must all be tied externally to an adequate ground plane for proper operation of this device.
The TIEPAl1 0016ET6C is characterized for operation from O°C to 85°C.
IMPACT-X is a trademark of Texas Instruments Incorporated
PAL is a registered trademark of Monolithic Memories Inc.
PROOUCT PREVIEW documents contain Information on
products In the formative or design phase of development.
Char'cterlatlc data and other specHlcatlons are design
goals. rexa. Instruments reserves the right to change or
discontinue these products without notice.
Copyright © 1989, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • CALLAS. TEXAS 75265
2-469
TIEPAl10016ET6C
ECl-TO-TTL IMPACT-X™ PAL ® TRANSLATOR CIRCUIT
logic diagram
~
, 0
:~
INCREMENT
___~___~______--JA~___~___~___~~
12
16
20
24
28 31 '
~!.
N
J<
)-~F
C1
)-
:c
6
..... 736
I
o
c
c:
o-I
768
1024
"tJ1
..... 1248
8;»1.
y
:c
m
1.
1280
-m=EI
" 1504
10
":x
y
11
":x
y
A
o
---
~ ENECLJTTL
21
o
20
o
"F
,,=
10
~
ECLJTTL
17
o
~
~
>~F~
ECLJTTL
16
o
N
~
~P9F~
ECLJTTL
15
o
)-~F ~
Fuse Number = First Fuse Number + Increment
An exclusive-NOR input grounded through an intact polarity fuse is at an Eel logic-high level.
2-470
22
~.- ~~
N
992
7
ECLJTTL
~)-~F ~
512
"tJ
~3
~
480
I 5
24 GND
TEXAS ..If
INSIRUMENlS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
14
TIEPAl10016ET6C
ECl·TO·TTl IMPACT·X™ PAL ® TRANSLATOR CIRCUIT
FUNCTION TABLE
INPUTS
OUTPUTS
OE
LE
DATA IN
ot
0*
FEEDBACK
L
L
H
H
L
H
L
L
L
L
H
L
L
H
00
00
H
H
X
X
H
L
H
H
L
L
Z
Z
Z
Z
Z
Z
00
00
H
L
X = Don't care
t = Polarity fuse blown
:j: = Polarity fuse intact
~~~:Y----------------fC~ID1~--1
LE-{>~---t:~
o
~
CV'hr-----------'
w
FEEDBACK __________
FEEDBACK
-N"
5>
w
a::
FIGURE 1. SIMPLIFIED LOGIC DIAGRAM (EACH OUTPUT)
c.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (see
Note 1)
::l
ECl supply voltage, VEE ........................................................... -7 V to 0.5 V
TTL supply voltage, Vee ............................................................ -0.5 V to 7 V
Input voltage range ................................................................. VEE to 0.5 V
Operating free-air temperature range .................................................. DoC to 85°C
Storage temperature range ........................................................ -65'C to 150°C
t:i
C
0
a::
C.
NOTE 1: These ratings apply except for programming pins during a programming cycle.
TEXAS ."
INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-471
TIEPAL 10016ET6C
ECL-TO-TIL IMPACT-X™ PAL ® TRANSLATOR CIRCUIT
recommended operating conditions (see Note 2)
MIN
NOM
MAX
TIL supply voltage, VCC
4.5
5
5.5
V
ECL supply voltage, VEE
-4.2
-4.5
-4.8
V
High-level input voltage, VIH
Low-level input voltage, VIL
"'C
::D
VEE=-4.2V
-1.15
-0.88
VEE=-4.5V
-1.165
-0.88
VEE=-4.8V
-1.165
-0.88
VEE =-4.2V
-1.81
-1.475
VEE =-4.5V
-1.81
-1.475
VEE =-4.8V
-1.81
-1.49
UNIT
V
V
High-level output current, 10H
-3.2
mA
Low-level output current, 10L
24
mA
Pulse duration, LE high, tw
3
ns
Setup time, data before LEt, tsu
4
ns
Hold time, data after LE! , th
0
Operating free-air temperature, T A
0
ns
85
'c
electrical characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted) (see Note 3)
o
PARAMETER
VOH
VCC= 4.5 V,
VI = VIHmin or VILmax
IOH=-2mA
VEE
-4.2 V to -4.8 V
c:
VOL
IIHt
VCC= 4.5 V,
VI = VIHmin or VILmax
IOL=24 mA
-4.2 V to -4.8 V
0.5
V
-4.8V
220
C
o-t
"'C
::D
m<
_
TEST CONDITIONS
MAX
MIN
2.4
UNIT
V
liLt
VI =VILmin
10ZH
VCC = 5.5 V,
VI = 2.7V
-4.2 V to -4.8 V
20
10ZL
VCC=5.5V,
VI = 0.4 V
-4.2 V to -4.8 V
-20
!lA
!lA
!lA
!lA
10S+
VCC=5.5V,
Vo =0
-4.2 V to -4.8 V
-100
mA
ICC + lEE
VCC=5.5V,
Pins 1 and 13 are tied together
-240
mA
VI =VIHmax
-4.2V
0.5
-40
-4.8V
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
m (see Note 3)
:e
FROM
TO
(IN PUn
(OUTPUn
tpd
LE~
0
tpd
I or Feedback
0
ten
OE
0
tdis
OE
0
PARAMETER
TEST CONDITIONS
R1 =200'1,
R2 = 200 '1,
See Figure 1
MIN
TYP
MAX
UNIT
5
ns
6
ns
4
ns
5
ns
t Measure one input at a time. Ensure that ali other inputs are open.
*
Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTES: 2. The algebraic convention, in which the' more negative limit is designated as minimum and the less negative limit is designated as
maximum, is used in this data sheet for logic voltage levels only. For other quan@es, e.g., supply voltages and currents, the normal
magnitude convention is used.
3. Each device has been designed to meet these specifications after thermal equilibrium has been established. The circuit is in a test
socket or mounted on a printed circuit board and transverse air flow greater than 150 meters (500 feet) per minute is maintained.
2-472
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
TIEPAL10016ET6C
ECL-TO-TTL IMPACT-X™ PAL ® TRANSLATOR CIRCUIT
PARAMETER MEASUREMENT INFORMATION
sv
SI
~
Rl
CL
(See Note A)
R2
LOAD CIRCUIT FOR
3-STATE OUTPUTS
TIMING
INPUT
VIH
t:::~--~
HIGH·LEVEL ~
PULSE
I
I
VIL
I+-- tw ---+I
tsu~th
DATA
INPUT
50%
I
I
VIH
LOW.LEVEL~
SO%
VIL
PULSE
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
.£1 SO%
--.Ii
---r_..JI
{
' \ I.SV
.
CONTROL
(Iow.level
enabling)
~tpHL
'\=.
~ tpLH
!r.':: VOH
T I.SV
.
-
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
~
~
tt
VIH
VIL
a.
OUTPUT~VIH
VIH
....---1-1--..1- - VOH
1
)L I.S V
1
VOL
tPHL--l4--+i
OUT·OF·PHASE
OUTPUT
(See Note D)
-
VIL
II I.S V
----
VIL
VOLTAGE WAVEFORMS
PULSE DURATIONS
I
tpL~
IN·PHASE
OUTPUT
\-;O~ -
I
I
VIH
SO%
ten
WAVEFORM 1
SI CLOSED
(See Note B)
-.I
I+I
I I tdis~ I+-
\rI- V -
I
WAVEFORM 2
S10PEN
(See Note B)
VIL
--!-: ~S iJz:;- ~
- VOL
ten
-+I
r-
I-
o
50%
~ ___ _
1
tdls-.l
::J
C
2.S V
ott
a.
- . - VOL
i_
4
3
o
25
6
24
Veeo
Ne
o
I/O
~
2 1 28 27 26
I/O
23
22
8
9
W
I/O
0
:;
Veeo
w
a:
Q.
Ne
21
0
10
20
I/O
11
19
I-
o
c
oa:
Q.
121314151617 18
:::>
wu - -
~z
NC-No internal connection
The TIEPAL1 0016P8-3 is equipped with a security fuse. Once the security fuse is blown, additional
programming and verification cannot be performed. This prevents easy duplication of a design.
This device is characterized for operation from ooC to 85°C; this temperature range is designated by a
.. c .. suffix in the part number (TIEPAl1 0016P8-3CJT).
ExCL is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.
Copyright © 1989, Texas Instruments Incorporated
PRODUCT PREVIEW documenll •••tli. informati••
on products i. the formative or dasign ,ha. of
development. Characteristic data anil othar
=:.at:::sr~r:t dt'::a=::~rT~::~~::~:::
pradlets without notice.
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-475
TlEPAl10016PB·3C
HIGH·PERFORMANCE ExCL™PAL® CIRCUIT
functional block diagram (positive logic)
8
&
32 X 64
"
8
- b.
--
'V
8
--
'V
12
4,
16XC>
16
16
8/
'V
I'V
8
'V
'V
8
8
~
'V
~
'V
~
'V
8
4
"'0
:D
o
C
c:
n-I
"'0
::D
S
m
~
TEXAS •
2-476
INSJRUMENTS
PO~T
OFFICE BOX 656012 • DALLAS. TEXAS 75265
Vee
-1
o
o
o
o
110
110
1/0
1/0
TIEPAL 10016P8·3C
HIGH·PERFORMANCE ExCC· PAL® CIRCUIT
logic diagram (positive logic)
[281124)
VCC
INCREMENT
(\
I
0
32
(2]11)
4
12
8
28
24
16
20
16
20
24
12
8
28
4
\
32
0
-t>t=
(3]12)
[27){23)
A
0
FIRST FUSE
NUMBERS
""
96
(25]121)
'"
'"0
192
m
1
m
FIRST FUSE
NUMBERS
m
(5]14)
110
I/O
m8l
...
[4113)
I
[26){22)
')(
320
l52
19i
1
~~:
'"
'00
~
'"
eoo
'"
on
'"
~
'"no
768
(241120)
o
a:
Q.
eoo
o
....
so,
'"
'",eo
(6115)
o
'"
2051
992
:::>
1024
1056
1088
1120
1152
~
1184
1216
1248
o
->w
W
m
(21){18)
o
c
o
a:
Q.
(9117)
2053
1536
1568
1600
1632
1664
~1I
1696
1728
1760
110
)
I 2055
(11119)
(12){10)
[131111)
I
110
(10]18)
I
I
(20]117)
...
X
....
....
A
[19]116)
...;
(17){14)
[18){15)
~
(161113)
Fuse Number = First Fuse Number + Increment
NOTE: Pin numbers in [ 1 are for the FK package; pin numbers in ( ) are for JT package.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-477
TlEPAl10016PB·3C
HIGH·PERFORMANCE ExCLTM PAL® CIRCUIT
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
(see Note 1)
Supply voltage, VEE (see Note 2) ....................................... 0 V to -6.5 V
Input voltage, VI (see Note 3) ............................................ 0 V to VEE
Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 50 mA
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 85°C
Storage temperature range ......................................... - 65°C to 150°C
NOTES:
1. These ratings apply except for programming pins during a programming cycle.
2. All voltage values are with respect to Vee and Veeo. i.e., these pins are all assumed to be at 0 volts.
3. VI should never be more negative than VEE.
recommended operating conditions (see Note 4)
I
I
VEE
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
VEE - -4.2
VEE = -4.5
VEE = -4.8
VEE = -4.2
VEE - -4.5
VEE = -4.8
:
."
:u
o
c
c:
MIN
-4.2
-1.15
-1.165
-1.165
-1.81
-1.81
-1.81
0
V
V
V
V
V
V
NOM
-4.5.
MAX
-4.8
-0.88
-0.88
-0.88
-1.475
-1.475
-1.49
8.5
UNIT
V
V
V
De
electrical characteristics over recommended supply voltage range,' T A - 0 °C to 85 DC (unless otherwise
noted) (see Notes 4 and 5)
o
PARAMETER
"tI
VOH
-t
:u
m
S
~
TEST CONDITIONS
VI
= VIHmin
VEE =
VEE =
VEE =
VEE -
or VILmax
= VIHmin or VILmax
VOL
VI
IIH
IlL
lEE
VI = VIHmax
VI - VILmin
All inputs open
VEE
VEE
=
=
-4.2 V
-4.5 V
-4.8 V
-4.2 V
-4.5V
-4.8 V
Typt
MIN
-1.03
-1.035 -0.955
-1.045
-1.81
-1.81
-1.81
MAX
-0.87
-0.88
-0.88
-1.595
-1.700 -1.61
-1.61
220
UNIT
V
V
p.A
~A
0.5
-220
mA
tTypical values are at Vee = 4.5 V, TA = 25 De.
NOTES: 4. The algebraic convention, in which the more negative limit is designated as minimum and the less negative limit is designated
as maximum. is used in this data sheet for logic voltage levels only. For other quantities, e.g., supply voltages and currents,
the normal magnitude convention is used.
5. Each l00KH PAL has been designed to meet these specifications after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse air flow greater than 150 meters (500 feet) per minute
is maintained. Outputs are terminated through a 50-ohm resistor to - 2 V.
2-478
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 656012 •
D~UAS.
TEXAS 75285
TlEPAl10016P8·3C
HIGH·PERFORMANCE ExClTM PAl@ CIRCUIT
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(see Note 5)
FROM
(INPUT)
TO
(OUTPUT)
I. 1/0. 0' feedback
0.110
PARAMETER
tpd
t,
TEST CONDITIONS
See Figures 1 and 2
tf
MIN
MAX
1
3
UNIT
0.7
1.5
ns
0.7
1.5
ns
ns
NOTE 5: Each l00KH PAL has been deSigned to meet these specifications after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse air flow greater than 150 meters (500 feet) per minute
is maintained. Outputs are terminated through a 50-ohm resistor to - 2 V.
PROGRAMMING INFORMATION
Comptete programming specifications. algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
3:
w
:>w
PARAMETER MEASUREMENT INFORMATION
INPUT
.LI"5-0-%---\;;- -
~
I
tPLH"';"~
IN·PHASE
OUTPUT
1
a:
a..
VIH
l-
VIL
~tPHL
f---+I-""'"'\~-;;;.;;
I
50%:
I
I
tPHL ~
OUT '()F.pHASE
OUTPUT
-
~
e.)
VOH
VOL
I4-----+1-tPLH
1
\ 50%
•
OUTPUT
WAVEFORM
F
I VOH
50%
_ VOL
801:
i
20%
I
I
I 1
t r -+'
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
I+-
~---VOH
180%1
I
I
1
(20%)
I
I 1
-+I I+-tf
V
OL
::>
c
oa:
a..
VOLTAGE WAVEFORMS
RISE TIME AND FALL TIME
FIGURE 1. VOLTAGE WAVEFORMS
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-479
TlEPAl10016P8·3C
HIGH·PERFORMANCE ExCL™ PAL® CIRCUIT
PARAMETER MEASUREMENT INFORMATION
2.00 V ± 0.01 V
r
251'F
INPUT
TEST
VIH max + 2 V {
or
VIL min + 2 V
::u
o
C
c:
q
OUTPUT
UNDER ~-i--------t-+4~~
TEST
~t-t-------~-r-4~UNDER
"tJ
0.11'F
}
ALL
OTHER
INPUTS
ALL
{
OTHER
OUTPUTS
CO)
-I
0.11'F
q
"tJ
::u
m
S
~
-2.50 V ± 0.01 V
NOTES: A. The offset voltage generator has the following characteristics: Pulse amplitude = .800 mV P-P. PRR
t r = tf = 1 ns.
:s
1 MHz, tw = 500 ns,
B. RT is a 50-0 terminator internal to the oscilloscope.
C. CL :S 3 pF, includes fixture and stray capacitance.
D. Coax has 50-0 impedance and the coax to oscilloscope channel A and to channel B must be of equal lengths.
E. All unused outputs are loaded with 50-0 ± 1 % resistors to ground.
F. All unused inputs should be connected to either high or low levels consistent with the logic function required.'
G. All fixture wire lengths or unterminated stubs should not exceed 6 mm (1/4 inch).
FIGURE 2. LOAD CIRCUIT
2-480
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 6550t2 • DALLAS, TEXAS 75265
TIEPAl10016TE6C
TTL·TO·EClIMPACT-X™ PAL ® TRANSLATOR CIRCUIT
OCTOBER 1989
JTPACKAGE
(TOP VIEW)
• ECl Programmable logic with TTl-to-ECl
Translation
• ECl Control Inputs
VCC
1 U
24
GND
2
23
lE
!!
~~
g
5
6
7
8
20
19
18
17
16
15
14
II
• 3-State ECl Outputs
• Impact-X'· Process with Reliable
Titanium-Tungsten Fuses
• Package Options Include Both 300-mil
Ceramic DIP and Plastic Chip Carrier
9
description
10
11
The
TIEPAL10016TE6C
combines
the
IMPACT-X'· (Advanced Implanted, Advanced
Composed Technology) process with proven
titanium-tungsten fuses to provide reliable
high-performance substitutes for conventional
ECl 100K logic. Easy programmability allows for
quick design of custom functions with increased
logic density.
VEE
12
13
0
0
OE
GND
FNPACKAGE
(TOP VIEW)
__
The TIEPAl1 0016TE6C accepts TTL input levels
and provides ECloutput levels, making it ideal for
interfacing TTL with ECl circuits. It has latched
outputs, which are controlled from an ECl Latch
Enable input, LEo The outputs are enabled from a
single ECl input, OE.
The TIEPAl10016TE6C is provided with an output
polarity fuse that, if blown, will allow an output to
assume a logic high when the implemented
equation is satisfied. However, when the output
polarity fuse is intact and the implemented
equation is satisfied, the output will assume a logic
low.
....._ - - '
0
GND
GND
0
5
U
~~
4 321
3:
[ij
-
Cl
W
t§ I~ 0
282726
25
24
23
22
21
6
7
8
9
10
20
11
19
121314 15161718
0
0
a:
a.
GND
NC
GND
I-
0
0
0
::J
C
--UUClIWO
0
~Zt§0
a:
a.
NC-No internal connection
The TIEPAl1 0016TE6C is equipped with a security fuse that, when blown, prevents additional programming
and design verification. This safeguards against easy duplication of a design.
The four GND pins must all be tied externally to an adequate ground plane for proper operation of this device.
The TIE PAL10016TE6C is characterized for operation from O·C to 85·C.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Monolithic Memories Inc.
PRODUCT PREVIEW documents contain Information on
products In the formative or de.lg" pha.. ofdevelopment.
Characteristic data and other .paeHlcatlon. are design
goals. Texas Instruments reserve. the right to change or
discontinUe these products wtthout notice.
Copyright © 1989, Texas Instruments Incorporated
TEXAS ."
INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-481
TIEPAl10016TE6C
TTL·TO·ECl IMPACT·X™ PAL ® TRANSLATOR CIRCUIT
logic diagram
INCREMENT
'0
2
3
8
12
16
20
24
28
24
~GN o
TTLJEC"':;:
23
TTLJEClJ:;::
FIRSTFUSE
NUMBER
4
4
0000
.J(
TTLJECll
0256
5
oC
..,.
TTLJECl
1536
1537
0512
'"0 6
:x:J1
>~-=
=t..»-= o
>~
-<:
TTLJECl
.J(
l
~o
=t..»-=
F~_~
1538
~o
0768
C:I
7
~
1024
'"01 8
:x:J
m
:$1
m
==:1
TTLJECLl
1280
9
10
11
~
/~"o
~
TTLJECLl
TTLJECLl
J<
1539
-<>~
C1
"o
1540:::L.):>--
~>~C1
1 5 4 1 : . L ) o"
~
TTLJECl~
TTLJECl
Fuse Number = First Fuse Number + Increment
Pin numbers shown are for the JT package.
An exclusive-NOR input grounded through an intact polarity fuse is at an Eel high logic level.
2-482
C1
TEXAS -If
INSlRUMENlS
POST OFFICE BOX 656303 • DALlAS, TEXAS 75265
~o
o
TIEPAl10016TE6C
TTL·TO·ECl IMPACT·X™ PAL ® TRANSLATOR CIRCUIT
FUNCTION TABLE
INPUTS
ot
6*
FEEDBACK
L
H
L
H
L
L
L
H
L
H
H
X
00
00
X
L
L
H
L
L
L
L
00
00
L
L
L
LE
L
L
H
H
H
OUTPUTS
ARRAY DATA
H
OE
L
H
L
= Don't care
1" = Polarity fuse blown
= Polarity fuse intact
X
*
ARRAY-----------------fIIDD~--~------~~~
DATA
~--~--,
o
Cl
FEEDBACK
~
~
a:
-----------0
FEEDBACK ------------)
FIGURE 1. SIMPLIFIED LOGIC DIAGRAM (EACH OUTPUT)
a..
t-
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (see
Note 1)
ECl supply voltage range, VEE (see Note 2) .......................................... -8 V to 0.5 V ~
TTL supply voltage range, Vee ...................................................... -0.5 V to 7 V
C
ECl input voltage range ............................................................. VEE to 0.5 V
TTL input voltage ......................................................................... 5.5 V
O
Operating free-air temperature range, T A ........................................... ,.. DoC to 85°C
Storage temperature range ........................................................ -65°C to 150°C
oa:
a..
NOTES: 1. These ratings apply except for programming pins during a programming cycle.
2. All voltage values are with respect to the GND pins connected together.
TEXAS -If
INSIRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-483
TIEPAl10016TE6C
TTl-TO-ECl IMPACT-X™ PAL ® TRANSLATOR CIRCUIT
recommended operating conditions (see Note 3)
MIN
NOM
MAX
UNrr
TTL supply voltage, VCC
4.75
5
5.25
V
ECl supply voltage, VEE
-4.2
-4.5
-4.8
V
2
5.5
V
TTL high-level input voltage, VIH
I
I
I
ECl high-level input voltage, VIH (LE and OE inputs)
VEE--4.2V
-1.15
-0.88
VEE=-4.5V
-1.165
-0.88
VEE =-4.8V
-1.165
-0.88
VEE=-4.2V
-1.81
-1.475
VEE =-4.5V
-1.81
-1.475
VEE =-4.8V
-1.81
-1.49
TTL low-level input voltage, Vil
0.8
I
I
ECl low-level input voltage, Vil (LE and OE inputs)
I
Pulse duration, lE high, tw
V
V
V
3
4
ns
Setup time, data before lEt, tsu
Hold time, data after lE t , th
0
Operating free-air temperature, TA
0
ns
·C
ns
85
""C electrical characteristics over recommended ranges of supply voltage and free-air temperature
:c
(unless otherwise noted) (see Note 4)
o
PARAMETER
C
~
""C
:c
~
VOH
c:
-~
TEST CONDITIONS
VCC = 4.75 V,
VIK
VI = Vilmax or VIHmin
VI = Vilmax or VIHmin
VOL
I
IIHt
LE,OE
I
lilt
LE,OE
ICC + IEEl
VCC = 5.25 V,
VI=VIHmax
. VCC = 5.25 V,
MIN
VI=-18mA
UNIT
-1.5
V
VEE=-4.2V
-1.03
-0.87
VEE=-4.5V
-1.035
-0.88
VEE=-4.8V
-1.045
-0.88
VEE =-4.2V
-1.81
-1.595
VEE=-4.5V
-1.81
-1.81
VEE=-4.8V
-1.81
-1.61
20
VI=2.7V
220
VEE = -4.2 V to -4.8 V
-200
VI =0.4V
VEE = -4.2 V to -4.8 V
VI =Vllmin
VCC=5.25V
MAX
0.5
-220
VEe = -4.2 V to -4.8 V
V
V
;.IA
;.IA
mA
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(see Note 4)
FROM
TO
(OUTPUT)
tpd
(INPUT)
LEj
tpd
I or Feedback
ten
OE
0
0
0
tdis
OE
0
PARAMETER
TEST CONDITIONS
MIN
TYP
5
See Figures 2 and 3
MAX
UNrr
ns
6
ns
4
ns
5
ns
t For ECl inputs, measure one input at a time with the other inputs open.
:I: All inputs and outputs are open.
NOTES: 3. The algebraic convention, in which the more negative limit is designated as minimum and the less negative IimH is designated as
maximum, is used in this data sheet for logic voltage levels only. For other quantities, e.g., supply voltages and currents, the normal
magnitude convention is used.
4. Each device has been designed to meet these specHications after thermal equilibrium has been established. The circuit is in a test
socket or mounted on a printed circuit board and transverse airflow greater than 150 meters (500feet) perminute is maintained. Outputs
are terminated through a 50-0 resistor to -2 V;
2-484
TEXAS ."
INSIRUMENTS
POST OfFICE eox 8&6303 • DAUAS, TEXAS 75285
TIEPAl10016TE6C
TTl-TO-ECl IMPACT-X™ PAL@ TRANSLATOR CIRCUIT
PARAMETER MEASUREMENT INFORMATION
INP~
IpLH
IN-PHASE
OUTPUT
3.5V
1
I.!I
1
1
\
1
I..
~I
IpHL
1
1
1
....Jt,..--..;.I-""~---
uv
~I
I'
50%
--+I-J·
1
\.!
I"
VOH
50%
1
1
1
IpHL ,...-..:
OUT-OF-PHASE
OUTPUT
; ; v - - - - 5.5V
VOL
I
~i
OUTPUT~O%
80%--- vOH
WAVEFORM
IpLH
20%
! I r - VOH
50%
50%
.....- - - - - " - - - VOL
7""
1\
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
I
I
20%
I I
1
1
-.J.--l..-
Ir
~
VOL
If
VOLTAGE WAVEFORM
RISE TIME AND FALL TIME
FIGURE 2. VOLTAGE WAVEFORMS
3:
w
:>
w
a:
D..
I-
o
::J
C
oa:
D..
TEXAS ..,
INSIRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-485
...
TIE PAL 10016TE6C
TTL-TO-ECl IMPACT-X™ PAL ® TRANSLATOR CIRCUIT
PARAMETER MEASUREMENT INFORMATION
2.00 V ± 0.01 V
r+
25",F
0.1 ",F
~
7V
Vee
GND
INPUT
UNDER
TEST
~m"'l
"'D
::XJ
2v
or
VUmln+2
v
oo
OUTPUT
UNDER
TEST
A~
} OTHER
INPUTS
c:
-=-
o-I
VEE
25 ",F
P
"'D
::XJ
m
<
m
-
:e
~'l
OTHER
OUTPUTS
0.1 ",F
~
-2.50 V ± 0.01 V
NOTES: A. The offset voltage generator has the following characteristics: Pulse amplitude = 800 mV p.p, PRR ~ 1 MHz, tw = 500 ns, tr = tf = 1 ns.
B. RT is a 5O.g terminator intemal to the oscilloscope.
.
C. CL ~ 3 pF, includes fixture and stray capacitance.
D. Coax has 50·g impedance and the coax to oscilloscope channel A and to channel B must be of equal lengths.
E. All unused outputs are loaded with 50·g ± 1% resistors to ground.
F. All unused inputs should be connected to either high or low levels consistent with the logic function required.
G.AII fixture wire lengths or unterminated stubs should nol exceed 6 mm (1/4 inch).
FIGURE 3. TEST CIRCUIT
2-486
TEXAS ~
INSIRUMENlS
POST OFFICE
epx 655303 •
DALLAS. TEXAS 75265
TIFPLA839C. TIFPLA840C
14 x 32 x 6 FIELD-PROGRAMMABLE LOGIC ARRAYS
02708. JUNE 1984-AEVISED AUGUST 1989
LOGIC FUNCTION
•
Input-to-Output Propagation
Delay . . . 10 ns Typical
f(l)
•
24-Pin, 300-mil Slim Line Packages
fill
•
Power Dissipation ... 650 mW Typical
•
Programmable Output Polarity
= PO + Pl , , , P31
= PO' Pi' ...
for polarity link intact
·m for polarity link open
where PO through P31 are product terms
JT OR NT PACKAGE
(TOP VIEW)
description
The'FPLA839 (3-state outputs) and the
'FPLA840 (open-collector outputs) are TTL fieldprogrammable logic arrays containing 32 product
terms (AND terms) and six sum terms (OR
terms). Each of the sum-of-products output
functions can be programmed either high true or
low true. The true condition of each output
function is activated by the programmed logical
minterms of 14 input variables. The outputs are
controlled by two chip-enable pins to allow
output inhibit and expansion of terms.
:'\'
',,""'GND
These devices provide high-speed data-path
logic replacement where several conventional
.. ,>.
SSI functions can be designed into a single \';~;\}
package.
,::;.";; \ (
,,'«"ll'j.
........_--'-'-"-'
FN PACKAGE
(TOP VIEW)
!."<;N
The 'FPLA839C and 'FPLA84q6:;>~r'e
characterized for operation from,Q,
&
o
28X J2
32
14
o
o
o
o
o
...... denotes fused inputs.
tFPLA839 has J-stata ('V) outputs; FPLA840 has open-collactor (Q) outputs.
absolute maximum ratings
Supply voltage, Vee (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Off-state output voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70°C
Storage temperature range ......................................... - 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
2-488
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
TlFPLA839C. TIFPLA840C
14 x 32 x 6 FIELD·PROGRAMMABLE LOGIC ARRAYS
logic diagram
8
0
1
7
•
I NCREMENT
~~X~~~-r+-~-+~~-r+-~~~~~~~~~~-r+-~ 2
3
~
6
~~X~-r~-r+-r+-+-r~-r+-r+~-r~r+-r~~-r~-r+-r+~
5
6
7
X
4
~vX-~-r~r+-r~~-r~-+-r~~-r+-r+-r~~-r+-r+-r~-
3
4
5
8
9
~~X~-r~-r+-r+-+-r~-r+-r+~-r~-+-r~~-r~-r+-r+- 10
II
~
2
12
13
X
14
15
16
17
18
19
20
~~Hrrr~~~-rHrrr~-rHr~~"~~-r
20
21
~~~-rr+-rr-r+~-+~-r-r~-r~-rr-r+~-rr+1-
22
23
24
25
17
OEI
OE2
_1~3~
26
27
__________________________________________________________~
Fuse number = first fuse number
+
increment
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·489
TIFPLA839C, TIFPLA840C
14 x 32 x 6 FIELD·PROGRAMMABLE LOGIC ARRAYS
recommended operating conditions
Supply voltage, Vee
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
V
Low-level input voltage, VIL
I 'FPLA840
I 'FPLA839
High-level output voltage, VOH
High-level output current, 10H
Low-level output current, IOL
0
Operating free-air temperature, T A
0.8
V
5.5
V
-3.2
rnA
24
rnA
70
·e
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
Vee ~ 4.75 V,
VIK
10H
I 'FPLA840
VOH I 'FPLA839
Vee
~
4.75 V,
II
~
MIN
Typt
-18 rnA
~
VOH
MAX
-1.5
5.5 V
0.1
UNIT
V
rnA
Vee ~ 4.75 V,
10H ~ -3.2 rnA
10L ~ 24 rnA
II
Vee"" 4.75 V,
Vee ~ 5.25 V,
IIH
Vee ~ 5.25 V,
IlL
Vee
10'
Vee ~ 5.25 V,
Vo
10ZH
Vee ~ 5.25 V,
Vo ~ 2.7 V
10ZL
Vee ~ 5.25 V,
Vo ~ 0.4 V
-20
~A
lee
Vee ~ 5.25 V,
VI
130
180
rnA
Typt
MAX
UNIT
10
20
10
20
8
15
Typt
MAX
10
25
10
20
8
15
VOL
~
5.25 V,
2.4
3
0.37
V
0.5
V
0.1
rnA
VI
~
VI
~
2.7 V
20
~A
VI
~
0.4 V
-0.5
rnA
-112
rnA
20
~
5.5 V
~
~
2.25 V
0 V,
-30
OE inputs at VIH
'FPlA839 switching characteristics
PARAMETER
FROM
TO
tpd
Input
Output
ten
Pin 1 or Pin 13
Output
TEST CONDITIONS
Rl
~
50011,
R2
eL
~
50 pF,
See Figure 1
~
MIN
50011,
tdis
ns
ns
'FPlA840 switching characteristics
PARAMETER
FROM
TO
tpd
Input
Output
Pin 1 or Pin 13
Output
ten
TEST CONDITIONS
Rl
~
50011,
R2
eL
~
50 pF,
See Figure 1
~
50011,
tdis
MIN
UNIT
ns
ns
t All typical values are at Vee ~ 5 V, T A ~ 25 ·C.
+The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit current, lOS.
2-490
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TIFPLA839C, TIFPLA840C
14 x 32 x 6 FIELD·PROGRAMMABLE LOGIC ARRAYS
programming information
Texas Instruments Programmable Logic Devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas
Instruments Programmable Logic is also available, upon request, from the nearest TI field sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997·5666.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2·491
TlFPLA839C. TIFPLA840C
14 x 32 x 6 FIELD-PROGRAMMABLE LOGIC ARRAYS
PARAMETER MEASUREMENT INFORMATION
5 V for tpd
7 V fa. ten and tdis
SI
b
Rl
FROM OUTPUT
UNDER TEST
_-+_.._ .._
CL
TEST
POINT
R2
ISee Note A)
LOAD CIRCUIT FOR
THREE-STATE OUTPUTS
TIMING
INPUT
J.
1 SV
15 V
~
.
.
---3.SV
3.S V
HIGH·LEVEL
PULSE
F,1.5 V
~tw--J
- - - - - ' U - - - - - - 0.3 V
I4-th-+l
1
1
I+-tsu-+l
DATA
~~;::3.5V
INPUT..../' 1.5V
~
0.3 V
LOW·LEVEL
PULSE
1 SVIS V
~
.
.
\1~~---3.SV
.L l . SV
1
----"
tpd
I,.
1
IN· PHASE
OUTPUT
:1
tpd I,.
OUT·OF·PHASE
OUTPUT
ISee Note D)
1•
~I
0.3 V
I,.
~I
1
I
tpd
1,..--+:---.+ - - VOH
f1.5V 1 ~
14
~I
'\1.SV
.
~I
VOL
tpd
F/OH
.
I
3.SV
- - --0.3V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT
0.3V
1
- - VOL
OUTPUT
CONTROL
~3.SV
I.SV
(low·level
enabling I
-1- - - - -- 0.3 V
I+I :
ten ~
WAVEFORM
SI CLOSED
ISee Note BI
l---r\:
I.SV
-+I 14-- Idis
: 1
~3.3 V
II~vOL+o.sv
I ~-==~-=
ten~!+-'-+I I4-ldis 'f.
VOL
I _ _ _ l.-VOH
WAVEFORM 2
S10PEN
~
I
--
1.5 V
LVOH-O.S V
~0
ISee Nole B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5V
I
1
V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES. THREE·STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is SO pF for tpd and len. 5 pF for tdis'
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR :s 1 MHz. tr = tf ~ 2 ns. duty cycle = SO%.
D. When measuring propagation delay times of 3-state outputs, switch 51 is closed.
FIGURE 1
2-492
TEXAS ",
INSfRUMENTS
POST OFFICE BOX 655012 •
DALL~S,
TEXAS 75265
Application Reports
3-1
'"
Contents
Introduction to Designing with Programmable Logic . . . . . . . . . . . . . . . ..
Programmable Logic Device Design Software Support ...............
Programming Texas Instruments Programmable Logic Devices .........
Test Considerations for PLDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A Designer's Guide to the TIBPSG507 . . . . . . . . . . . . . . . . . . . . . . . . . ..
System Solutions for Static Column Decode ......................
Programmable Frequency Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EP1810 as a Bar Code Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
.3-2
Page
3-3
3-37
3-53
3-61
3-75
3-125
3-153
3-163
Introduction to Designing with
Programmable Logic
l!1
TEXAS
INSTRUMENTS
3-3
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products, including
SNJ and SMJ devices, to current specifications in accordance with
TI's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems such testing
necessary to support this warranty. Unless mandated by
government requirements, specific testing of all parameters of
each device is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes
no liability for TI applications assistance, customer's product
design, or infringement of patents or copyrights or third parties
by or arising from use of semiconductor devices described herein.
Nor does TI warrant or represent that any license, either express
or implied, is granted under any patent right, copyright, or other
intellectual property right of TI covering or relating to any
combination, machine or process in which such semiconductor
devices might be or are used.
Copyright © 1989, Texas Instruments Incorporated
3-4
Contents
Title
Page
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-7
Programmable Logic Advantages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-7
Symbology for PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Family Architectures ................................................
PLD Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Output Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Example Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PLD Implementation ................................................
PLD Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Clock Selector Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-Bit Binary Counter Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Binary/Decade Count Details .........................................
Fuse Map Details ..' . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PLD Design Software ...............................................
3-7
3-8
3-13
3-16
3-19
3-20
3-20
3-21
3-21
3-26
3-29
3-30
3-32
3-5
List of Illustrations
Figure
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Page
Basic Symoblogy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Basic Symbology Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROM Architecture .........................................
PAL® Architecture. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .
FPLA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIBPAL16L8 Logic Diagram .................................
TIBPAL16R8 Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polarity Selection ...........................................
Output Macrocell Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Resultant Macrocell Feedback and Output Logic
After Programming ...........................' . . . . . . . . . . . . .
PLD Process Flow Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Counter Implementation With Standard Logic. . . . . . . . . . . . . . . . . . ..
TffiPAL16R4 Logic Diagram. . .. . .. . .. . ... . . .. . .. . . . .... . ....
Karnaugh Map for CLKOUT .................................
Karnaugh Map for CLKOUT .................................
Karnaugh Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programmed TIBPAL16R4 ...................................
Source File for ABEL .......................................
ABEL Output Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-8
3-8
3-9
3-11
3-12
3-14
3-15
3-16
3-17
3-18
3-19
3-21
3-23
3-24
3-25
3-27
3-31
3-33
3-34
List of Tables
Table
1
2
3
4
Page
Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL is a registered trademark of Monolithic Memories Incorporated.
3-6
3-20
3-23
3-26
3-29
Introduction
The purpose of this application report is to provide the first time user of programmable
logic with a basic understanding of this powerful technology. The term Programmable
Logic Device (PLD), refers to any device supplied with an uncommitted logic array, which
the user programs to his own specific function.
Programmable Logic Advantages
Programmable logic devices (PLDs) offer many advantages to the system designer
who presently is using several standard catalog SSI and MSI functions. Listed below are
just a few of the benefits which are achievable when using programmable logic.
• Package Count Reduction: Several MSIISSI functions can be replaced with
one PLD. This reduces system power requirements.
• PC Board Area Reduced: Fewer devices consume less PC board space.
• Circuit Flexibility: Programmability allows for minor circuit changes without
changing PC boards.
• Improved Reliability: With fewer PC interconnects, overall system reliability
increases.
• Shorter Design Cycle: When compared with standard-cell or gate-array
approaches, custom functions can be implemented much more quickly.
• Proprietary Design Protection (fuse protection): Circuit can be protected by
blowing the security fuse.
The PLD will fill the gap between standard logic and large scale integration. The
versatility of these devices provide a very powerful tool for the system designer.
Symbology for PLDs
In order to keep the PLDs easy to understand and use, a special convention has been
adopted. Figure 1 is the representation for a 3-input AND gate. Note that only one line
is shown as the input to the AND gate. This line is commonly referred to as the product
line. The inputs are shown as vertical lines, and at the intersection of these lines are the
programmable fuses. An X represents an intact fuse. This makes that input, part of the
product term. No X represents a blown fuse. This means that input will not be part of
the product term (in Figure 1, input B is not part of the product term). A dot at the
intersection of any line represents a hard-wire connection.
3-7
INPUT TERMS
ABC
PRODUCT
LINE
-ttt-D-
OUTPUT
F
A'C
=
Figure 1. Basic Symbology
In Figure 2, we will extend the symbology to develop a simple 2-input programmable
AND array feeding an OR gate. Notice that buffers have been added to the inputs, which
provide both true and complement outputs to the product lines. The intersection of the
input terms form a 4 X 3 programmable AND array. From the above symbology, we can
see that the output of the OR gate is programmed to the following equation, AB + AB.
Note that the bottom AND gate has an X marked inside the gate symbol. This means that
all fuses are left intact, which results in that product line not having any effect on the
sum term. In other words, the output of the AND gate will be a logic O.When all the
fuses are. blown on a product line, the output of the AND gate will always be a logic
1. This has the effect of locking up the output of the OR gate to a logic level 1.
INPUT TERMS
~
A
INPUTS
B
PRODUCT
LINES
Figure 2. Basic Symbology Example
Family Architectures
The PROM was the first widely used programmable logic family. Its basic architecture
is an input decoder configured from AND gates, combined with a programmable OR matrix
on the outputs. As shown in Figure 3, this allows every output to be programmed
3-8
16 WORDS X 4 BITS
c
D
B
A
"OR" ARRAY
(PROGRAMMABLE)
~
,.
R
F<
I-J
,
R
F<
L.I
i'
/
\
I
V
"AND" ARRAY
(FIXED)
?yyy
03
02
01 00
Figure 3. PROM Architecture
3-9
individually from every possible input combination. In this example, a PROM with 4 inputs
has 24 , or 16 possible input combinations. With the output word width being 4 bits, each
of the 16 X 4 bit words can be programmed individually. Applications such as data storage
tables, character generators, and code converters are just a few design examples which
are ideally suited for the PROM. In general, any application which requires every input
combination to be programmable is a good candidate for a PROM. However, PROMs
have difficulty accomodating large numbers of input variables. Eventually, the size of
the fuse matrix will become prohibitive because for each input variable added, the size
of the fuse matrix doubles.
To overcome the limitation of a restricted number of inputs, the PAL utilizes a slightly
different architecture as shown in Figure 4. The same AND-OR implementation is used
as with PROMs, but now the input AND array is programmable instead of the output
OR array. This has the effect of restricting the output OR array to a fixed number of input
AND terms. The trade-off is that now, every output is not programmable from every input
combination, but more inputs can be added without doubling the size of the fuse matrix.
For example, if we were to expand the inputs on the PAL shown in Figure 4 to 10 and
on the PROM in Figure 3 to 10, we would see that the fuse matrix required for the PAL
would be 20 X 16 (320 fuses) vs 4 X 1024 (4096 fuses for the PROM). It is important
to realize that not every application requires every output to be programmable from
every input combination. This is what makes the PAL a viable product family.
The FPLA goes one step further in offering both a programmable AND array and
a programmable OR array (Figure 5). This feature makes the FPLA the most versatile
device of the three, but often impractical in most low complexity applications. For
applications in which complex timing control is required, Texas Instruments offers several
programmable state machines based on the FPLA architecture. Several of these devices
incorporate internal state registers or on-chip binary counters to aid in generating complex
timing sequences.
Another type of programmable logic device (PLD) is the erasable PLD. Based on
the traditional PAL ® architecture, these devices typically offer a higher level of flexibility
in the input and output configuration, register selection, and clocking options. CMOS
EPLDs provide a higher level of density over standard PLDs and have lower power
dissipation characteristics than bipolar PLDs. All programmable logic approaches discussed
have their own unique advantages and limitations. The best choice depends on the
complexity of the function being implemented and the current cost of the devices themselves.
It is important to realize that a circuit solution may exist for more than one of these logic
families.
3-10
c
D
-
A
B
"OR" ARRAY
FIXED
~
,.
:r
F'\
F=<
l..-I
1\
V
F<
LJ
/
\
V
"AND" ARRAY
(PROGRAMMABLE)
Figure 4. PAL® Architecture
3-11
c
D
B
A
"OR" ARRAY
(PROGRAMMABLE)
1\
,..
I
\
J
V
"AND" ARRAY
(PROGRAMMABLE)
99
Figure 5. FPLA Architecture
3-12
,
PLD Options
Figure 6 shows the logic diagram of the popular TIBPAL16L8. Its basic architecture
is the same as discussed in the previous section, but with the addition of some special
circuit features. First, notice that the PAL has 10 simple inputs. In addition, 6 of the outputs
operate as I/O ports. This allows feedback into the AND array. One AND gate in each
product term controls each 3-state output. The architecture used in this PAL makes it very
useful in generating all sorts of combinational logic.
Another important feature about the logic diagram and all other block diagrams
supplied from individual datasheets are that there are no Xs marked at every fuse location.
From the previous convention, we stated that everywhere there was an intact fuse, there
was an X. However, in order to make the logic diagram useful when generating specific
functions, it is supplied with no Xs. This allows the user to insert the XS wherever an
intact fuse is desired.
The basic concept of the TIBPAL16L8 can be expanded further to include D-type
flip-flops on the outp'uts. An example of this is shown in Figure 7 with the TIBPAL16R8.
This added feature allows the device to be configured as a counter, simple storage register,
or similar clocked function.
Circuit variations which are available on other members of the TI PLD family are
explained in the following paragraphs.
3-13
INPUT LINES
RODUCT,
LINES
0
0
4
8
12
16
20
24
28
31
·•••
·•
u-J
(19)
o
~
(2),,-~
.....
'8
··•
·
·•
·•
1
......
(3) 15
(18)
v
liD
A
16
1
r-
(17)
v
f-----,
liD
•
~
(4)';;
24
••
r-
··•
-
h
f-"
1
..
(16)
1
(15)
110
~
(5) 31
X
32
,
·••
·•
~
f--"
lJ-I).-
v
1
(6) 39
40
1(7)
·•••
·
·••
·
·••
·•
1
I-- h
>---
v
47
48
I (8)
f--
~
(14)
1/0
1
1
(13)
v
liD
I
55
,
"56
~v-J
(12)
r-
(11)
>---
63
I (9) ;>L.
A
I
I
Figure 6. TIBPAL16L8 Logic Diagram
3-14
1/0
o
CLK (11
~
P
I
INPUT LINES
RL~~E~CT
'0
0
0
0
0
o
0
0
4
B
12
16
20
24
2B
31
~>---"
~
I-
1--
D-
fn~'"
Q
C1
(21 .... ~
'b-
B
0
0
0
0
0
0
>--
(31~15
\--
D-
0
0
0
0
0
D-
~
tJ;
(171
~
(161
b
...
(151
tv""
Q
'>--->
0
0
0
0
0
0
-
~
_D-
....
Q
C1
(51 31
32
f-----'
~
0
0
0
0
0
0
I
t-J
C1
(41 23
24
...
C1
16
o
D
tr:lJ1BI Q
Eb-
fn
Q
C1
(61 39
>---"
40
0
0
D-
o
0
0
0
I--
48
0
C
C1
47
I (71 ')[
.
b--v"'"(141 Q
c
I--
~I
Q
....
->-
0
0
0
0
C1
-
55
1 181
56
~
0
0
0
0
0
0
I--
63
I (91 ~
L
ptQ~'"
C1
A
~
Figure 7. TIBPAL16R8 Logic Diagram
3-15
Output Macrocell
PLDs equipped with the output macrocell offer total output flexibility. Figures 8
and 9 show examples of these types of features as implemented in the TffiPAL22V10
device. Fuses SO and S1 allow selection between registered or combinational outputs.as
well as output polarity. Figure 10 illustrates the user options.
The user options are as follows:
1. Clock Polarity Select. The clock signal can be inverted via a clock polarity
select fuse. This allows the transition of the register outputs to be on either
the positive or negative edge of the clock pulse.
2. Internal-State Registers. Several devices offer internal~state registers, which
are often called buried registers. With the internal-state register, the output
of the register is fed back into the AND array rather than to an output pin.
This feature can be used for timing control sequences.
3. Variable Product Terms. Some PAL® device architectures vary the number
of product terms associated with each output pin. This allows better utilization
of the programmable array.
ENABLE
10
INPUTS
PO
o
o
In
o
o
r:>-+-+--'t-.. :
o
Pn
Figure 8. Polarity Selection
3·16
OUTPUT LOGIC MACROCELL
MUX
r--------------e~----~3
2
......--=---'""1
h---4.----IO
1
O
FROM CLOCK BUFFER
MUX
l
0
G-
3
.,
1~----~~----4-----4-----~
G1
I
I
I
S1
AR = asynchronous reset
~= SynCh~US~
-
__
J
I
Figure 9. Output Macrocell Diagram
3-17
REGISTER FEEDBACK. REGISTERED.
ACTIVE-LOW OUTPUT
REGISTER FEEDBACK. REGISTERED.
ACTIVE-HIGH OUTPUT
S1 - 1
SO
S1 = 1
=0
t-----'
SO - 1
1/0 FEEDBACK. COMBINATIONAL.
ACTIVE-HIGH OUTPUT
1/0 FEEDBACK. COMBINATIONAL.
ACTIVE-LOW OUTPUT
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
FUSE SELECT
S1
SO
0
0
1
1
0
1
0
1
FEEDBACK AND OUTPUT CONFIGURATION
Register feedback
Registered
Register feedback
Registered
Active low
Active high
I/O feedback
Combinational
Active low
110 feedback
Combinational
Active high
o
= unblown fuse. 1 = blown fuse
51 and SO are select-function fuses as shown in the output logic macrocell
diagram.
Figure 10. Resultant Macrocell Feedback and Output Logic After Programming
3-18
Design Example
The easiest way to demonstrate the unique capabilities of the PLD is through a design
example. Through this example, the reader will gain the basic understanding needed to
apply a PLD in his own application. In some cases, this goal may only be to reduce existing
logic, but th~ overall approach will be the same.
GENERATE
LOGIC EQUATIONS
Figure 11. PLD Process Flow Diagram
3-19
Example Requirements
This example will generate a 4-bit binary counter which is fed by one of four clocks.
There are two lines available for selecting the clocks, SELl and SELO. Table 1 shows
the required input for the selection of the clocks. In addition, it is desired that the counter
be able to switch from binary to decade count. This feature is controlled by an input called
BD. When BD is high, the counter will count in binary. When low, the counter will count
in decade.
Table 1. Clock Selection
SEL1
SELO
OUTPUT
0
0
1
1
0
1
0
1
ClKA
ClKB
ClKC
ClKD
Figure 12 shows this example is implemented using standard logic. As shown, three
MSI functions are required. The 'LS162 is used to generate the 4-bit counter while the
clock selection is handled by the 'LS253. The 'LS688 is an 8-bit comparator which is
used for selecting either the binary or decade count. In this example, only five of the eight
comparator inputs are used. Four are used for comparing the counter outputs, while the
other is used for the BD input. The comparator is hard wired to go low whenever the
BD input is low and the counter output is "9". The P = Q output is then fed back to the
synchronous clear input on the 'LS162. This will reset the counter to zero whenever this
condition occurs.
PLD Implementation
As stated before, the problem in programming a PAL is not in programming the
fuses, but rather what fuses need to be programmed to generate a particular function.
Fortunately, this problem has been greatly simplified by computer software. But before
we examine these techniques, it is beneficial to explore the methods used in generating
the logic equations. This will help develop an understanding and appreciation for these
advanced software packages.
From digita1logic theory, we know that almost any type of logic can be implemented
in either AND-OR-INVERT or AND-NOR form. This is the basic concept used in the
PLD. This allows classical techniques, such as Karnaugh Maps1 to be used in generating
specific logic functions. As with the separate component example (see Figure 12), it is
easier to break it into separate functions. The first one that we will look at is the clock
selector, but remember that the overall goal will be to reduce this design example into
one PLD.
3-20
'lS253
ClK A . ClK S
'lS162
SElO
SEl1
ClKC
ClK D
--
0o
0
ClK
ClK
-
OUT
02
ClR
03
'lS688
VCC
~
~
SD
~
PO 00
P1 01
P2 02
P3 03
P4 04
P5
P6
05
06
P7
07
-p=o
~
-
Vc C
"::F
I
Figure 12. Counter Implementation with Standard Logic
PLD Selection
Before proceeding with the design for the clock selector, the first question which
needs to be addressed is which PLD to use. As discussed earlier, there are several different
types of output architectures. Looking at our example, we can see that four flip-flops with
feedback will be required in the 4-bit counter, plus input clock and clear lines. In addition,
seven inputs plus two simple outputs will be required in the clock selector and comparator.
With this information in hand, we can see that the TIBPAL16R4 (Figure 13) will handle
our application.
Clock Selector Details
The first step in determining the logic equation for the clock selector is to generate
a function table with all the possible input combinations. This is shown in Table 2. From
this table, the Karnaugh map can be generated and is shown in Figure 14. The minimized
equation for CLKOUT comes directly from this.
3-21
Table 2. Function Table
SELl SELO CLKA CLKS CLKC CLKD CLKOUT SEL1 SELO CLKA CLKS CLKC CLKD CLKOUT
3-22
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
1
1
1
0
1
0
0
1
1
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
0
1
0
0
1
1
1
0
1
0
0
1
0
0
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
0
1
1
1
1
0
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
0
0
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
1
f
0
1
1
0
1
1
1
0
1
0
0
1
1
1
1
1
1
0
1
1
1
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
1
1
1
0
0
1
1
1
0
1
0
1
0
0
1
1
1
0
1
0
0
0
0
1
0
1
0
1
1
1
1
0
1
0
1
1
0
1
0
1
1
0
1
1
1
0
1
1
0
0
0
1
0
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
1
0
1
1
1
0
0
1
1
0
1
1
0
1
0
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
1
1
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
\
__- -________________________________________________~
CLK~
INPUT LINES
PRODUCT.~--------------------h·------------------~
LINES
0
0
4
8
12
16
20
24
28
31'
•
·•••
(21~2-...
V
(191 1
/0
>-~
~
·•••
·
··••
1
I-L-/
1
(181
v
I/O
(3) 15
')f
16
:>- ~~"" Q
•
Cl
(4) 23
·•
·•
···•••
··
·
··••
·
·•••
·
24
-
>---p--
I
(6) 39
(7 47
I..'.!..!
48
I (8)
55
D-
(151
~
}--
:r>tbJ;
_
r.:tv (141
Q
Cl
'\---
h'\---
~ Q
Cl
j---
~
I--
)--
1
~
(13)
I/O
1
'>(
---cf'-J
56
I
b
Q
I--
')f
40
(16)
v
C1
(5) 31
32
~
~
(91 63
!--'
1
v
(121
I/O
1
L..
~
Figure 13. TIBPAL16R4 Logic Diagram
3-23
It is important to notice that the equation derived from the Karnaugh map is stated in ANDOR notation. The PLD that we have selected is implemented in AND-NOR logic. This
means we either have to do DeMorgan's theorem on the equation or solve the inverse
ofthe Karnaugh map. Figure 15 shows the inverse of the Karnaugh map and the resulting
equation. This equation can be easily implemented in the TmPAL16R4.
so
SO,A,B
A
r----1
S1.C.D
c[
CLKOUT
A
'1 r;-
1
1
1 1
1
1
1
1
1
1
1 1
1
1
=S1S0AMU + s1soiBn + s1soiMci + s1sol~«D
CLKOUT = S1S0A + SlSOB + S1SOC + S1S0D
Figure 14. Karnaugh Map for CLKOUT
3-24
so
SO,A,B
A
A
,.--,
,.--,
S1,C,D
1
c[
1
1
1
1 1
1
1
1
1
1
1
1
-
1
1
-1
1
1
1
1
1
1
1
1
---
-
-
111
1
1
1
J
111
1
1
1
I
-
CLKOUT = S1S0A + S1S0B + S1S0C + S1S0D
Figure 15. Karnaugh Map for CLKOUT
3-25
4-Bit Binary Counter Details
The same basic procedure used in determining the equations for the clock selector
is used in determining the equations for the 4-bit counter. The only difference is that now
we are dealing with a present state, next state situation. This means a D-type flip-flop
will be required in actual circuit implementation. As before, the truth table is generated
first and is shown in Table 3.
Table 3. Truth Table
PRESENT STATE
NEXT STATE
CLR
03
02
01
00
03
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
x
x
x
x
0:2
0
0
01
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
0
1
1
1
1
0
0
1
0
1
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
b
0
1
1
0
0
1
1
0
0
1
1
0
00
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
From the truth table, the equations for each output can be derived from the Karnaugh
map. This is shown in Figure 16. Note that the inverse of the truth table is being solved
so that the equation will come out in AND-NOR logic form.
3·26
CLR
CLR,03,02
03
03
,---,
01,00 " "
1
1
1
1
1 ~
1
1
1
1
1
1 1
1
1
1
1
1
1
11
1
1
1
1
I
1
~HMCHOO
00 = CLRMfHCHCM +
00 = CLR + 00
(a) Karnaugb Map for QO
CLR
CLR,03,02
01'OO~
03
r--1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
L--.....J
1)1
1
1
11
11
1
1
1
~
02
02
01 = CLRMMCHCM + ~HM0100 + C:l:«MCH0100
01
=i l l + 0100 + 0100
(b) Karnaugb Map for Ql
Figure 16. Karnaugb Maps
3-27
CLR
CLR,03,02
01,00
~
03
r--I
/-
I
I
\
/'"
03
.---,
-.....
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 1(1
It...!.. ~
--
0
'-----" .........
1\
J
1..1
..,/'-.. --../
L---J
02
02 = CLRHH@1&e +
1
1
L--.J
02
~1H0201&e
+ Ct:«fH020100
+~M02@100
02 = CLR + 0201 + 020100 + 0200
(c) Karnaugh Map for Q2
CLR
CLR,03,02
01,00
~
,I
\
03
r--I
03
r:::::::l
1
---
1
1
1
1
1
1
1J 1
1
I
1
1
~ r;1
1
--.....
/
I
1
1
1
1J
1
\
1
1..1
1J
L---.J
02
03
=
CLRMfHt!HM + Gt.cR0302@1M + ~03M01M
+ e:t:.II03&iC!H00 + Ct:«03020100
03 = CLR + 0302 + 0301 + 0300 + 03020100
(d) Karnaugh Map for Q3
Figure 16. Karnaugb Maps (Continued)
3-28
Binary IDecade Count Details
Recalling from the example requirements that the counter should count in decade
whenever the BD input is low, we can again generate a truth table for this function (Table 4).
Since the counter is already designed to count in binary, we can use this feature to simplify
our design. What we desire is a circuit whose output goes low, whenever the BD input
is equal to a logic level "0", and the counter output is equal to "9". This output can
then be fed back to the CLR input of the counter so that it will reset whenever the BD
input is low. Whenever the BD input is high, the output of the circuit should be a high
since the counter will automatically count in binary. Notice that Q shown in the truth
table is the function we desire.
Table 4. Truth Table
BO Q3 Q2 Q1 QO
QQ
0
0
0 1
0 1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0 1
1
1
BO Q3 Q2 Q1 QO
QQ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0 1
0 1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
1
0
0
0
0
0
0
1
1
1
0 1
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
In this particular example, a Karnaugh map is not required because the equation
cannot be further simplified. The resulting equation is given below.
BD OUT=BDQ3Q2QIQO
3-29
Fuse Map Details
Now that the logic equations have been defined, the next step will be to specify which
fuses need to be programmed. Before we do this however, we first need to label the input
and output pins on the TlBPALl6R4. By using Figure 12 as a guide, we can make the
following pin assignments in Figure 17.
PIN:
1 CLK
2 SELO
3 SELl
4 CLKA
5 CLKB
6 CLKC
7 CLKD
8 CLR
9 BD
10 GND
20
19
18
17
16
15
14
13
12
11
VCC
CLKOUT
NC
QO
Ql
Q2
Q3
NC
BD OUT
OE
With this information defined, we now need to insert the logic equations into the
logic diagram as shown in Figure 17.
It is now probably obvious to the reader, that inserting the logic equations into the
logic diagram is a tedious operation. Fortunately, several software programs are available
to perform this task automatically. All that is required is telling the program which device
has been selected and defining the input and output pins with their appropriate logic
equations. The program will then generate a fuse map for the device selected. This
information can then be down loaded into the selected device programmer.
3-30
ClK
1!lt>
PRODUCT,
liNES
0
0
0
0
0
0
0
0
SElO
INPUT LINES
4
8
12
16
20
24
28
31
}--
)->(
-
f-/
1
v
(2),,;
eo
>--
0
0
0
0
0
h
r-- I--'"
-
(3) 15
:x
SEll
I
1
v
(19) elK OUT
(18) NC
I
16
0
0
0
0
0
0
ClK A
(4) 23
1.:>L
24
0
0
0
0
0
0
(5) 31
ClK B
32
0
0
0
0
0
0
(6) 39
:x
ClKC
40
0
0
0
0
0
0
ClK 0 (7)
47
:x
48
1
0
0
0
0
0
0
ClR
~
55
(8) ....
(13) NC
I
56
0
0
0
0
0
0
BO
63
(9) X
Figure 17. Programmed TIBPAL16R4
3-31
PLD Design Software
Software packages such as ABELTN, CUPLTN, and proLogic™ not only generate the
fuse map, but they also help in developing the logic equations. In most cases, they can
generate the logic equations from simply providing the program with either a truth table
or state diagram. In addition, they can test the logic equations against a set of test vectors.
This helps to ensure the that designer gets the desired function.
Several software packages are described in further detail in this data book. The
Programmable Logic Device Design Software Support section provides a detailed summary
of the capabilities of several of these popular design tools.
As an example, we will approach our previous design utilizing DATA IIO's ABELTN
package. The purpose here is not to teach the reader how to use ABEL1M, but rather to
give them a basic overview of this powerful software package. Figure 18 shows the source
file required by ABELTM. Note that the 4-bit counter has been described with a state diagram
table. When the ABEUM program is compiled, the logic equations will be generated from
this. The equations for CLK OUT and BD OUT are given in their final form to demonstrate
how ABELTM will handle these. Also notice that test vectors are included for checking
the logic equations. This is especially important when only the logic equations are given.
Figure 19 shows some of the output documentation generated by the program. Notice
that the equations generated for the counter match the ones generated by the Karnaugh
maps. A pinout for the device has also been generated and displayed. The fuse map for
the device has not been shown; however, the standard JEDEC fuse map thus generated
can be down loaded into the device programmer to program the selected PLD.
ABEL is a trademark of Data 110 Corporation
CUPL is a trademark of LOGICAL DEVICES, INC.
proLogic is a trademark of Inlab Inc ..
3-32
module SD_COUNT flan '-r2'
titl~ '4-bit bin~ry/d~cade
ICI
count~r
device 'P16R4',
const~nt
pin assiqnm.nts and
CLK_.IN,8ELO,SELl,CLKA
CU:B, r:ucC . cum
CLR.BD_IN.OE
StL_OUT.CLK_OUT
03,02,01.00
CK, L, H. X, Z
OUTPUT
t:'olJntQr
~~~lar~tions
pin
1,:'>.::1.4,
pin
5 • ~" 7
~
pin 8,9,11;
r,in 12.19,
pin 14,15,16,17~
• C. , 0 . 1 , • X. , • Z. ,
[Q3.0~, lH ,OOJ;
!'ot~tes
SO=~bOOOO;
~4=Ab0100~
;
S5=~bOl01,
S8=Ab1000,
S9:- Ab1001;
52=~b00101
S6=AbOt101
S7=Ab01 11,
SII:- Abl0111
SI=~bOOOl
S3=AbOOll
~
StO~Abl0l0;
S12=Abl100;
S13= .... b1101 ;
S14=Abll10;
S15= .... b1111;
PQllattl)n'i
r.locl< ! t. '01 I!c (0):
5
ta te_.0:1 i "''lNl.m [03,02,1)1 ,flO)
State SO:
IF CLR
St:
St~te
IF CLR
State S2:
IF CLR
St",te 83:
IF CLR
State S4:
IF CLR
S5:
St~te
IF CLR
IF CLR
St~te
S6:
S7:
IF CLR
St~te
St~te
S8:
IF CLR
S9:
St~te
IF CLR
IF CLR
St~te S10:
St~te S11:
IF CLR
IF CLR
St'lte S12:
IF CLR
State St3:
IF CLR
St~te S14:
IF CLR
state S15:
tE'!lt_vect<>rs
(eCLKA,
[ L
[
[
[
H
X
X
C X
[ X
(
X
[ X
'cloc'(
CLl~B.
X
X
L
H
Sl;
S2;
S3;
S4:
S5:
S6;
S7;
SA:
S9;
S10;
Sl1;
S12;
S13;
S14;
SIS;
SO;
~p.l""ctor'
CU~C.
X
X
X
X
X
L
H·
X
X
X
X
0 THEN 50 ELSE
0 THEN SO ELSE
0 THEN SO ELSE
0 THEN SO ELSE
0 THEN SO ELSE
0 THEN SO ELSE
0 THEN SO ELSE
0 THEN SO ELSE
0 THE"N SO ELSE
0 THEN SO ELSE
0 THEN SO ELSE
0 THEN SO ELSE
0 THEN ·~O ELSE
0 THEN SO ELSF.:
0 THEN SO ELSE
0 THEN SO ELSE
X
CLKD. SELl, SELO] - ) CLK_OUT)
X
L,
L 1 -)
L;
)(
L,
L ] ->
H;
)(
L,
H 1 -)
L;
X
L,
H ] -)
H;
X
H,
L 1 -)
L;
X
H,
L ] -)
H:
H ] -)
H,
L;
L
H,
H ] -)
H
H;
Figure 18. Source File for ABEL
3-33
test_vector-o;
([CLK_IN,
(
CK,
(
CK,
(
CK,
(
CK,
(
CK,
[
CK,
(
CK,
[
CK,
[
(
CK,
f'::K ..
(
CK,
CK,
CK,
(
CJ(,
(
(
CK,
£ond
r
GK,
(
CK,
[
X,
'counter'
OE, CLR, BD_IN] -> [OUTPUT, BD_OUTJ I
] -> (
X
SO,
H ];
L
L,
] -:> (
H,
si, H h
L
X
H 1;
L
X
J -)- r
52,
H,
] -:>
H,
S3,
H 1;
L
X
] ->
H,
54,
H ];
L
X
] ->
H ];
H,
X
S5,
L
] -:> r
X
S6,
H ];
L ,
H,
] -> (
H,
X
H ];
L
87.
] -> (
X
L
H,
S8.
H 1;
L
H,
L J -> r 89. L J;
H,
H ];
X
J -:>
S10,
L
H,
X
1 -> ( SI 1.
H J;
L
H,
X
H ];
L
J -:> ( S12,
X
H J;
L
H,
J -:> ( 513.
X
H,
L
J -> ( S14,
H 1;
H
H J.
H,
S15.
L
->
H,
I
X
H 1;
->
SO.
X
H
1 ->
Z
H h
X.
.
BD_COUNT
Figure 18. Source File for ABEL (Continued)
Pa.ge 1
-
ABEL(tml Ver-sion 1.00
Document Gener-a.tor
4-bit binary/decr.lde counter
Equations for Module BD_COUNT
D(>vice ICt
Reduced Equations:
eLK_OUT = '«SELl ~ SELO ~ !CLKD
# (SELl llc !SELO llc !CLKC
# (!SELl llc SELO ~ !CLKB
# !SELI llc !SELO llc !CLKAIIII;
BD_OllT = !(Q3
ll<
!Q2 II< '01 II< 00 llc !BD_INI;
03 := '«03 llc Q2 ~ Q1
tt ('03 llc '02
# (' 03 t. '01
# ('03 II< '00
# 'CLR)))));
~
00
02 := '«02 llc 01 II< 00 # ('Q2 llc '01 # (!02 llc !OO •
01 .- '«01 llc 00 •
00 := '«DO #
(!01 II< !OO #
!CLR)));
!CLR));
Figure 19. ABEL Output Documentation
3-34
!CLR))));
Page 2
ASELCtm) Version 1.00 - Document Generator
4-bit binary/decade counter
Chip diagram for Module SO_COUNT
Device.> ICt
P16R4
ClK_IN
SELO
SEll
ClKA
ClKB
ClKC
ClKO
ClR
BO_IN
GNO
00
01
02
03
BO_OUT
OE
end of module SO_COUNT
Figure 19. ABEL Output Documentation (Continued)
Reference
1. H. Troy Nagle, Jr., B.D. Carroll, and David Irwin, An Introduction to Computer
Logic. New Jersey: Prentice-Hall, Inc., 1975.
3-35
..
3-36
Programmable Logic Device
Design Software Support
~
TEXAS
INSTRUMENTS
3-37
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service Identified In this
publication without notice. TI advises its customers to obtain the latest
version of the relevant Information to verify, before placing orders, that
the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability forTI applications aSSistance, customer product
deSign, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represents that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1989, Texas Instruments Incorporated
Printed in the U.S.A.
TRADEMARKS
ABEL is a trademark of DATA 1/0 Corporation
CUPL is a trademark of LOGICAL DEVICES, INC.
PLDeslgner is a trademark of MINC INCORPORATED
proLoglc is a trademark of Inlab Incorporated
IBM and PC-DOS are trademarks of International Business Machines
Corporation
MS-DOS is a trademark of Microsoft Corporation
3-38
Programmable Logic Device
Design Software Support
~
~~mr~~~-~*Jl1!::;W~~~S:ii!;!:e~~
INTRODUCTION
There are a number of logic design software products available to the design engineer, intended to make logic design easier and less cumbersome. With these software products, complex designs can be described using Boolean equations, truth
tables, state machine diagrams and schematic capture methods available on most
CAD systems.
The ultimate function of these software products is to generate a JEDEC file of the
original design to be programmed into the targeted Programmable Logic Device
(PLD). However, most S/W vendors provide more than a JEDEC file as an output from
the software. This section seeks to describe the attributes of a few ofthe popular logic
design products. We recommend that the reader contact the specific manufactures
to obtain the latest and most comprehensive information available.
ABEL 1M - Advanced Boolean Expression Language
by DATA I/O Corporation:
ABEL consists of a special-purpose, high-level language that is used to describe
logic deSigns, and a language processor that converts logic descriptions to programmer load files - or JEDEC files. These files contain the information necessary to program and test programmable logic devices.
Features of ABEL design language:
Universal syntax for all PLDs
High-level, structered design language
Flexible forms for logic description
Boolean Equations
Truth Tables
State Diagrams
Test Vectors for Simulation and functional testing of programmed parts
Time-Saving Macros and Directives
3-39
Some powerful features of the ABEL language processor:
Syntax checking
•
Verification that a design can be implemented with a chosen part
Logic Reduction
Design Simulation
•
Automatic design documentation
Creation of programmer load files in JEDEC format
Between the ABEL design language and the language processor it becomes rather
easy to design and test logic functions to be implemented with a PLD. For example,
a three-Input AND function with the inputs Q, R, and S and an output P could be designed using a truth table like this:
truth_table "3-input AND gate"
([ Q, R, S ] -> P)
0, .X., .X.] -> 0
x, .0., .x.] -> 0
X, .X., .0.] -> 0
1, 1, 1 ] -> 1 ;
The" .X." in the table Indicate "don't care" conditions, and the output P is setto 1 only
when all three Inputs equal 1. The output could also be specified in simple Boolean
operators and achieve the same result. This Is done here, where "&" Is the logical
AND operator:
p ,;, Q & R &
3-40
s;
More Boolean Operators
Operator
Example
!A
Description
NOT: ones complement
&
A & B
AND
#
A # B
$
A $ B
OR
XOR: exclusive OR
!$
A !$ B
XNOR:exclusive NOR
ABEL allows designs to be described in the best possible manner to suit the logic
to be implemented or In a manner suitable to the logic designer. In most cases the
same description can be used for many different devices simply by changing the device specified.
TIle logic design process using ABEL is shown in Figure 1. Beginning with the design
concept, the designer creates the ABEL source file required by the language processor In order for it to generate the programmer load file. With the help of a text editor,
the designer can create the source file which contains complete description of the
logic design. TIle source file may also be created using DASH-ABEL to convert a
DASH-generated schematic of a design
3-41
Logic Design Steps:
The source file is presented to the language processor which performs the several
functions to produce a programmer load file (in JEDEC) format and all the required
design documentation (see Figure 1.).
PARSE
checks the syntax of the source file and flags any errors.
TRANSFORM
converts the logic description to an intermediate form.
REDUCE
performs logic reduction.
FUSEMAP
creates the (JEDEC) programmer load file, which can then be
downloaded
to the logic programmer to program parts, or used to generate
test vectors.
DOCUMENT
generates a listing of the source file, a drawing of the logic
device pin assignments, and a listing of the programmer
load file.
Figure 1. Logic Design Steps with ABEL
3·42
DESIGN EXAMPLES
The following two design examples highlight two design entry methods, Boolean
equations and State Diagrams.
Three-State Sequencer
The following design is a simple sequencer that demonstrates the use of ABEL state
diagrams. The design is implemented in a TIBPAL16R4-1 0 device (P16R4). There is
no limit to the number of states that can be processed by ABEL, but the number of
transitions and the path of the transitions is limited.
Figure 2. shows the sequencer design, with a bubble diagram showing the transitions
and the desired outputs. The state machine starts in state A and remains in that state
until the 'start' input becomes high. It then transitions from state A to state B, from
state B to state C, and back to state A. It remains in state A until the 'start' Input is
high again. If the 'reset' input is high, the state machine returns to state A at the next
clock cycle. If this reset to state A occurs during state B, an 'abort' synchronous output goes high, and remains high until the machine is again started.
During states Band C, asynchronous outputs 'in_B' and 'in_C' become high to indicate the current state. Activation of the 'hold' input will cause the machine to hold in
state B or C until 'hold' is no longer high or 'reset' becomes high.
default with abort = 0
reset with abort: = 1
hold & !reset
with abort: = 0
default with abort = 0
hold & ! reset
with abort: = 0
Figure 2. State Machine Bubble Diagram
3-43
Design Methodology
Tlle sequencer Is described by using a STATE_DIAGRAM section In the ABEL source
file. Tlle ABEL source file for the sequencer Is shown in Figure 3. In this example, the
design is given a title, the target device is specified, and pin declarations are made.
The FLAG statement is used to select the level of reduction required. Constants are
declared to simplify the state diagram notation. Tlle two state registers are grouped
into a set called 'sreg'. Tlle three states A, B, and C are declared with appropriate
values specified for each.
For larger state machines with more state bits, careful numbering of states can dramatically reduce the logic required to implement the design. Using constant declarations to specify state values saves time when iater changes to these values are made.
The state diagram begins with the STATE_DIAGRAM statement that names the set
of signals to be used for the state register. The set to be used is 'sreg'.
Within the STATE DIAGRAM, IF-THEN-ELSE statements are used to Indicate the
transitions between states, and the input conditions that cause each transition. In
addition, equations are written in each state that indicate the outputs required for
each state or transition.
For example, state A reads:
state A:
in_B = 0;
in_C = 0;
if (start & !reset) then B with abort := 0;
else A with abort :=0;
This means that if the machine is in state A and 'start' is high, but 'reset' is low, then
the machine will advance to state B, but in another input condition the machine will
remain in sate A.
The equations for 'in_B' and 'in_C' indicate that those outputs should remain low
while the machine Is in state A, while the equations for 'abort', specified with the
"with" keyword, indicate that 'abort' should go low if the machine transitions to state
B, but should remain at its previous value if the machine stays in state A.
Test Vectors
The specification of the test vectors for this design is Similar to those of any other
synchronous designs. The first vector puts the machine into a known state (state A),
and the following vectors exercise the functions ofthe machine. Tlle A, B, and C constants are used in the vectors to indicate the value of the current state, thus improving
the readability of the vectors.
3-44
title '8-bit barrel shifter
Gerri t Barrera
Data I/O corp
Redmond WA
module sequence
flag , -r3'
title 'state machine example
device
d1
D. B. Pellerin - Data I/O';
'p16r4' ;
pin
pin
pin
pin
q1,qO
clock,enab. start ,hold, reset
abort
in_B, in_c
sreg
"state Values ...
A = 0;
17 oct 1987'
14,15;
1,11,4,2,3;
17;
12,13 ;
[q1,qO] ;
B = 1;
state_diagram sreg;
state A:
in_B = 0;
C = 2;
" Hold in state A until start is active.
in_C = 0;
IF (start &. I reset) THEN B WITH abort : = 0;
ELSE A WITH abort : = abort;
state B:
" Advance to state C unless reset is active
" or hold is active. Turn on abort indicator
in_C :::: 0:
II
if reset.
IF (reset) THEN A WITH abort : = 1;
ELSE IF (hold) THEN B WITH abort : = 0;
ELSE C WITH abort : = 0;
in_B = 1;
state C:
in_B = O'
in_C = 1;
II
Go back to A unless hold is active
Reset overrides hold.
IF (hold &. ! reset) THEN C WITH abort : = 0;
ELSE A WITH abort : = 0;
[qo, q1] = IRESET
test_vectors ([clock, enab, start ,reset ,hold]->[sreg, abort, in_B, in_C])
[.c.
0
0
0
0 ]->[ A
0
0
0];
[ . c.
0
0
0
0 ]-> [ A
0
0
0] ;
[.c.
0
0
0 ]->[ B O O ] ;
[.c.
0
0
0
0 ]->[ C O O
];
.c.
.c.
o
o
1
o
o
o
.c.
.c.
o
o
o
o
o
o
o
.c.
o
o
1
o
o
.c.
o
o
.c.
.c.
o
o
o
o
o
o
o
o
]->[
]->[
]->[
]->[
A
B
o
o
1
A
1
o
]->[
]->[
]->[
]->[
B
o
B
B
C
o
o
o
A
o ];
o ];
o ];
o ];
o ];
o
1
o ];
o 1;
o
o
1 ];
end
Figure 3. The ABEL Source File for Sequencer
3-45
8-Bit Barrel Shifter
This design example highlights the use of Boolean equations as design entry format
using ABEL. It Is an 8-bit barrel shifter that includes a shift amount selector, an output
control, and a device enable. The target device forthis design is the TIBPAL.20R8-XX.
This design Is described by only one Boolean equation. Figure 4. shows a block diagram of the design.
07 06 05 04 03 02 01 00
12
E
11
ClK
10
OC
07 06 05 04 03 02 01
ao
Figure 4. Block Diagram: 8-Bit Barrel Shifter
Design Specification
As shown In the block diagram above, the barrel shifter has 8 inputs (00-07), eight
outputs (00-07), three select lines (10-12), a clock (ClK), an output control (OC), and
an enable (E). On each clock pulse when E is high, the outputs show the inputs shifted
by n bits to the right, where n Is specified by the select lines. The bit shifted out of
the barrel shifter on the right is shifted in on the left, actually performing a rotate. When
E is low, the shifter outputs are then preset to 1.
The output control, when high, sets all outputs to high impedance, without affecting
the shift. This means that if a shift is selected while the output control is high, the shift
still occurs, but it Is not seen at the outputs. If the OC Is then set low, the shifted data
will appear on the outputs.
Design Methodology
Figures 5. and 6. show a simplified block diagram and the source file listing of the
design respectively. Pins have been assigned so that the shifter outputs can be associated with the registered outputs of the targeted PlO. The inputs, outputs, and select
lines are then assigned to sets which simplify notation.
In!ut
SeI~~lK
~OC
Output
Figure 5. Simplified Block Diagram: 8-BIt Barrel Shifter
3-46
One Boolean equation is used to describe the entire function of the barrel shifter. The
equation is expressed in the sum of products form and assigns a value to the output
set. Each product in the equation corresponds to one of the possible shifts and defines the outputs for that shift.
Thus, the product term,
(Sel==O) & ! [D7,D6,D5,D4,D3,D2,Dl,DO]
defines that for a shift of 0, the inputs are transferred without a shift directly to the outputs. Similarly, the product term,
(Sel==5) & ! [D4,D3,D2,Dl,DO,D7,D6,D5]
defines that for a shift of 5, output 07 gets the value of input 04, 06 gets 03 and so
on, corresponding to the correct shift of five places. Notice that the low-order input
bits have been "wrapped around", shifted out of the right side and into the left side.
Sel can have only one value at a time, thus only one of the "Sel= =" relational statements can be true at a given time, and only one of the product terms contributes to
the sum of products. The OR of all the product terms is AN Oed with the enable E so
that when E is low, all the outputs are preset to 1.
Both the output sets on the left side of the equation and the inputs on the right side
of the equation are expressed as negative logic, which, in effect, gives active high
logic. This is done to compensate for the 'PAl20RS's inverted outputs. The inverse
of the inputs is available on the device.
3-47
module
barrel
title 'a-bit barrel shifter
Data I/O Corp
Gerrit Barrera
device
P7096
Redmond WA
D7, D6, D5, D4, D8, D2, Dl, 00
Q7 ,Q6,Q5,Q4,Q8,Q2, Ql,QO
15,18,17,18;19,20,21,22;
Clk,OC,E,l2,l1,IO
Input
output
sel
H,L,C,Z
17 Oct 1987'
'P20R8' ;
Pin 2,3,4,5,6,7,8,9j
Pin
Pin 1,13,28,10,11,14;
[07,06,05 ,04,OS,02,Ol,OO];
[Q7 ,Q6,Q5 ,Q4,Q8,Q2,Ql,QO];
[12,11,10] ;
1,0, .C., .Z.;
equations
,output != E & (
(Sel == 0) & '[07,06,05,04,OS,02,Ol,OO]
# ( S e l l ) & '[00,07,06,05,04,08,02,01]
# (Sel
2) & '[01,00,07,06,05,04,03,02]
# (Sel
8) & '[02,01,00,07,06,05,04,03]
# (Sel
4) & ! [08,02,01,00,07,06,05,04]
# (Sel
5) & '[04,OS,02,Ol,OO,07,06,05]
# (Sel
6) & '[05,04,03,02,01,00,07,06]
# (Sel
7) & '[06,05,04,03,02,01,00,07])
test_vectors
([Clk,OC, E. sel,
Input]
C, L, H, 0, -b10000000]
c, L, H, 1, -b10000000]
C, L, H,
2, -b10000000]
C, L, H,
S, -b10000000]
C, L, H,
4, -b10000000]
L, H, 5, -b10000000]
C,
C, L, H, 6, -blOOOOOOO]
C, L, H,
7, -b10000000]
->
->
->
->
->
->
->
->
->
output)
-bl0000000; .. Shift 0
-bOl000000; .. Shift 1
-b00100000;
Shift
-bOO010000;
Shift
-bOOO01000;
Shift 4
-bOOOOOlOO;
Shift 5
-bOOOOO010;
Shift
-bOOOOOOOl;
Shift
-bOllllll1 ;
-blOll1111 ;
-bll101111 ;
-bll111110;
..
..
..
..
C,
C,
L,
L,
L,
L,
H,
H,
H,
H,
0,
1,
8,
7,
-bOlllllll]
-bOlllllll]
-b01111111]
-b01111111]
->
->
->
->
C,
C,
C,
C,
L,
L,
L,
H,
H,
H,
L,
H,
1,
1,
0,
0,
-bOOOOOO01]
-blll11110]
-bOOOOOOOO]
-bOOOOOOOO]
-> -b10000000; .. Shift 1/Wrap
-> -b0l111111 ; " Shift l/Wrap
-> -b11111111 ;
Preset
II Test High Z
->
z;
C,
c,
..
..
..
shift 0
Shift
Shift
Shift
end
Figure 6. ABEL Source File for the 8-Blt Barrel Shifter
3-48
OTHER PLD DESIGN SOFTWARE PRODUCTS
Below is a short list of some of the popular PLD design software products available
to logic designers. They are all PC based and can be Installed on your IBM PC 1M or
compatible.
CUPL ™
-
by Logical Devices Inc.
PLDesigner 1M
-
by MINC Inc.
proLogic TM
-
by IN lAB Inc.
CUPL
CUPL, like ABEL, is a universal Computer Aided Design (CAD) tool that supports
PLDs. It has utility flies thatfacilitate conversion of designs done in other design software environment to the CUPL design environment. CUPL also produces a standard
programmer load file in JEDEC format, thus making it compatible with logic programmers that accept JEDEC flies.
Features of CUPL design language:
Flexible forms for design description
Boolean Equations
Truth Tables
State Diagrams
Expression substitutions or time saving Macros
This involves the assignment of names to
equations and having the software do the
substitution any time the assigned name
is encountered during the compile process
Shorthand Features offered by CUPL
List Notation; This nested directive [A4,A3,A2,A 1,AO]
can be represented as [A4..0]
Bit Fields; A group of bits may be assigned to a name
as in
FIELD ADDR
=
[A4 .. 0]
Also available in CUPL are the use of
Distributive property - where A & (B # C)
Is replaced with A & B # A & C
DeMorgans Theorem - where
is replaced with ! A # ! B
! (A & B)
3-49
Some features of the CUPL language processor:
CUPL provides design templates which allow designers to just "fill-inthe-blanks· when originating a design. Free form comments can also
be used throughout the design.
3-50
•
Error checking with detailed error messages directs designers to the
source of problems during debugging.
•
logic Reduction Capabilities available on CUPL offers a choice of
several minimization levels from just fitting a design into a target
device to the absolute minimum.
•
Design Simulation is accomplished using the CSIM feature. This feature
allows designers to check the workability of their designs before a part
Is programmed. Functional simulation can be done at the programmer
when test vectors are provided.
PLDesigner
The PLDeslgner is a universal logic design synthesis tool for designing with PLDs.
It features:
A high-level behavioral language
Algorithmic design entry for state machine designs
Waveform design entry for glue logic
Design Simulation with automatic test vector generation
Automatic device selection and design partitioning across multiple
device architectures
A device library of over 2,000 devices.
A fundamental difference between PLDesigner and other products is that the "deSign
phase" is separate from the "device selection phase". You can complete a design
before a device, or devices, are selected. This allows you to concentrate on design
and simulation. No longer is it necessary to limit your design to a single device, or
to select a device before starting the design.
System Requirements
PLDesigner runs on an IBM PC 1M or compatible with an MS-DOS 1M or PC-DOS 1M
operating system, version 2.0 or later. 640K RAM memory and a hard disk are recommended: A CGA, EGA, Hercules, or monochrome display may be used. A mouse and
printer are optional.
Logic Design Steps with PLDesigner
Edit {
Design
'----,r----'
Compile {
Design
Partition
System
Program {
Test
Devices
* Indicates modules that
generate documentation
3-51
pro Logic
proLoglc Is a logic design software tool used to design and program Texas Instruments PLDs. This design software development package quickly converts your logic
design to a programmer load file In the standard JEDEC format. proLogic has the flexibility to allow you to describe your logic design in any of the following formats:
•
Boolean Equations
•
Truth Table
•
State Diagrams
It should be noted here that, not only can a design be entered in any of the above
methods, you can design various sections of the design in any of the three formats
shown above, and proLogic has the ability to unify the various sections and process
them as one design.
The proLoglc compiler Is capable of performing functional simulation when test vectors are provided. The simulator uses the fuse list portion from the JEDECfileto create
a functional device model. It can then execute the simulation vectors against this
model. The results are automatically placed In a file for evaluation.
PLD design flow using proLogic design software:
I Texas Instruments I
I Device Library I
START
DESIGN ENTRY
BOOLEAN
EQUATIONS
STATE
MACHINES
TRUTH
TABLES
(.PLD)
OPTIONAL
TEST
VECTORS
,
~
-VI
,..
proLogic
Complier
FINISH
l
~
-"-y
JEDEC
File
(.JED)
~
Listing File (.LS1)
Reduced logiC
Equations
Fuse Plot
I
'
.I
r1
,..
proLoglc
Simulator
I
f,
I I
OPTIONAL
~>
Vector Simulation
File
(.TS1)
3-52
DEVICE
PROGRAMMER
I
Programming Texas Instruments
Programmable Logic Devices
•
TEXAS
INSTRUMENTS
3-53
IMPORTANT NOTICE
~xas
Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises Its customers to obtain the latest
version of the relevant Information to verify, before placing orders, that
the Information being relied upon is current.
T1 warrants performance of its semiconductor products to current
specifications in accordance with n's standard warranty. Testing and
other quality control techniques are utilized to the extent n deems
necessary to support this warranty. Unless mandated by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
T1 assumes no lIabllityforn applications assistance, customer product
design, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represents that any license,
either express or Implied, Is granted under any patent right, copyright,
mask work right, or other Intellectual property right of TI covering or ralatlngto any combination, machine, or process In which such semiconductor products or services might be or are used.
Copyright © 1989, Texas Instruments Incorporated
3-54
Programming Texas Instruments
Programmable Logic Devices
This report is intended to introduce the reader to the fuse technologies used In Texas
Instruments PLDs, the measures taken by TI to provide devices with the highest possible programming yields, and the steps users can take to ensure good programmability.
HOW A FUSE IS PROGRAMMED
Programming Algorithm
Each programmable logic device family requires a unique algorithm for fuse programming and verification on commercial programming equipment. The algorithm is
a combination of voltage and timing required for addressing and programming fuses
in the user array.
The PLD's programming circuitry is enabled by pulsing one or more pins to a super
voltage level (10.5 volts). Once the programming circuitry is enabled, inputs become
addressing nodes for the input and product lines within the PLD. The actual fuse link
is at the intersection of the input and product lines. Once the fuse is addressed, the
tUse can be programmed by pulsing the output associated with the location of the
fuse link. A fuse can be verified to be programmed by enabeling the programming
circuitry, supplying the fuse address to the device's inputs, and reading the level of
the device's output.
Bipolar Fuse Technology
Figure 1 shows a top and side view of a fuse in a bipolar PLD before it is programmed.
Titanium-Tungsten (TiW) is used for the "fuse" or metal link programming element.
The ideal thickness for this programming element is about 500 Angstroms. TitaniumTungsten is also used as a barrier metal over contacts to prevent direct aluminum
contact to silicon. To prevent aluminum diffusion during high temperature processing,
the ideal thickness of the barrier metal is about 2000 Angstroms. TI's two-step link
process allows both the barrier thickness and the fuse thickness to be at the ideal.
The net result is a higher reliability and better programming yields.
When a device is programmed, the fuse location is selected. The fuse element at the
selected location is then opened by the programmer passing a current through the
Titanium-tungsten fuse element that violates the current density limit for the element.
This current flow heats the fuse element to approximately 2,100 degees Celcius at
which point the element is in a molten state. The metal migration which results from
the heat of this out-of-limit current stress causes a gap in the fuse element.
As shown in Figure 2, the high temperature at the fuse element's gap causes two actions to occur. The fuse element's TiW material oxidizes so as to leave the metal on
both sides of the gap non-conductive. Also, the heat associated with programming,
causes the Silicon Dioxide (Si02l above the fusing element to flow into the gap. This
proven fuse technology has eliminated the fears of fuse grow back as a failure mechanism in PLDs.
3-55
TlW (Fuse)
Figure 1. Before Programming
TlW (Fuse)
~VIEW
'--________/01!
TIW
Figure 2. After Programming
EPLD Programming Technology
Texas Instruments CMOS PLDs employ a process technology similar to EPROM devices. When compared to the bipolar fusible link technology, the FAMOS (Floatlnggate, Avalance-Injection MOS) transistor used by EPROMS replaces the fusible link.
This permits the programmability function in the sam!;! way as the fuse.
The FAMOS transistor resembles an ordinary MOS transistor except for the addition
of a floating gate buried in the insulator between the substrate and the ordinary select-gate electrode as shown in Figure 3. The programming of the FAMOS structure
is performed by capacitively coupling the select gate in series with the floating gate.
Hot electron injection onto the floating gate occurs by pulling the select gate to the
programming voltage and the drain of the FAMOS transistor to the programming voltage minus several threshold drops. As shown in Figure 4, this serves to alter the
threshold voltage of the select gate.
Once programmed, the FAMOS transistor retains the electron charge or data pattem,
until exposed to an integrated dose of ultravioletlighl with a wavelength of 2,537 ang-
3-56
stroms. lllis uv light will "erase" the charge by giving the electrons enough energy
to scatter from the floating gate. lllis retums the threshold voltage of the select gate
back to its original value or unprogrammed state. After erasure, the device is ready
tor reprogramming. llle reprogrammablity feature of Erasable PLDs allows the devices to be used for many programming iterations which are often required in the
user's design and prototyping stages.
INTERPOLY
OXIDE
ACCESS
/GATE
~~~
~~r
OXIDE
-~~TE)f
SI
D
= FLOATING
a. Cell Topology
""'---
OXIDE
~
= ACCESS
b. Cell Cross-Section
Figure 3. Views of an Floating Gate EPROM Cell
t
!Zw
'\ ERASED
STATE
a:
a:
:;)
o
z
~c
SELECT GATE VOLTAGE - - - .
The threshold voltage determines whether it is sensed as the nonconducting programmed state or erased. The change in threshold corresponds to the shift shown in the select-gate voltage to drain current
transfer characteristic.
Figure 4. Drain Current vs Gate Voltage
3-57
PROGRAMMER APPROVAL
Programming Algorithm Specifications
In order to achieve satisfactory programming yields for PLDs, it is critical that device
programmers adhere to the programming algorithm specifications as defined byTexas Instruments. Each specification contains detailed step-by-step programming
procedures, input and product line addressing procedures, waveform diagrams, and
minimum and maximum voltage and timing tables. Becuase of the complexity of the
programming algorithms and the need to control and update the specifications, Texas Instruments maintains programming algorithms in a specificaiton system seperate
from the PLD Data Book.
TI currently sends specifications and specification updates to most programmer and
software manufacturers, and challenges each to work with TI to provide our mutual
customer with approved programming support to guarantee them with the best possible programming yield.
Texas Instruments reserves the right to approve programming algorithms contained
in commercial programming eqUipment, and recommends that customers only use
approved programming support.
Approved programming support means that TI has evaluated the programming algorithm, has verified critical timing paths and voltage levels, and has performed yield
analysis testing. Approvals are granted by device and are thoroughly documented.
These measures are taken to ensure that Tl's customers receive the best possible
programming yields when using TI PLDs.
3-58
Evaluation and Approval Methods
Programmers are evaluated byTl's programmable logic applications. The evaluation
includes the following:
Measure voltage levels for accuracy and repeatability
Measure critical timing paths
Evaluate system power supply and grounding
Yield analysis
Templates and oscilliscope printouts are used to document all measurements and
are maintained permanently on file. Approvals are granted by device or algorithm and
documented by letter to the programmer manUfacturer.
Approved Programmer Support
Approved programmer support is documented in the 'TI Programming Reference
Guide', and on the TI PLO Bulletin Board (214)997-5665. To subscribe to the Programming Reference Guide, simply contact the TI PLD Hotline (214)997-5666 or your
local TI field sales representative.
Texas Instruments recommends that customers use only approved programming
support. Approved programming support ensures the user...
The best possible programming yield is being achieved because the
programming algorithms were evaluated and closely scrutinized.
TI guarantees 100% programming yield if approved programmers are
used, any fallout can be returned for full credit.
TI applications engineers are available to interface with programmer
manUfacturers for you on any programming issues or concerns.
3-59
HELPFUL HINTS FOR GOOD PROGRAMMABILITY
1)
Follow accepted standards for ESP protection - remember the additional
handling requirements In customizing PLOs make them more suscePtible to
ESO damage.
Equipment. personnel and work surfaces should be grounded
Air Ionization Is recommended when handling statiC sensitive devices
outside of protective containers.
2) Misaligned contactors and wom sockets can contribute to poor programming
yield. Be aware of the manufacturers specification for number of Insertions and
be sure sockets are replaced frequently to ensure proper contact.
3) Ensure you are using the latest update. Most programmer manufacturers offer
update and repair services to their users. The cost of the service is typically not
much more than the cost of a single update and the manufacturer may update
four or more times per year. TI recommends the user subscribe to this service.
Revisions could improve yield. TI continuously works with programmer
manufacturers on yield improvement.
New devices may be supported.
4) Programming equipment should be calibrated. Calibration Is typically Included
with the update and repair services previously discussed. TI recommends no
less than two calibrations per year.
Highest possible yields
Avoid device damage
5) Verify the correct family pinout codes or device entry codes are being used. It
Is Important to understand that different algorithms may be needed for different
speed versions of the same function.
6)
3-60
Use only TI evaluated and approved programming equipment to ensure the
highest possible programming yield and quality level.
Test Considerations for PLDs
."
TEXAS
INSTRUMENTS
3-61
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service Identified In this
publication without notice. 11 adVises its customers to obtain the latest
version of the relevant information to verify, before placing orders, that
the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with Tl's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by govemment
reqUirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability forTI applications aSSistance, customer product
deSign, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represents that any license,
either express or implied, Is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relatingto any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1989, Texas Instruments Incorporated
TRADEMARKS
Logic Fingerprint is a trademark of DATA I/O Corporation.
3-62
Test Considerations for PLDs
PLD architecture establishes some unique characteristics. Because PLDs do not
have the functional needs for address pins as found In a PROM, the array must be
addressed for programming through the use of super voltages (10.5 volts). Since the
programming and verification circuitry are not the same as the functional circuitry,
verification of the array fuses does not ensure total functionality. For this reason,
there are two customer yield points to be considered for a PLD, 1) programmability
yield, and 2) functionality after programming. TI thoroughly tests PLDs in its factory;
however, many users find the need to test after programming to achieve the highest
quality levels.
The objective of this report is to provide the PLD user with an insight as to what kind
of testing is performed at TI prior to shipment of programmable logic devices, and
to assist you in the evaluation of your testing alternatives after programmIng.
DESIGNED-IN FACTORY TESTABILITY
Texas Instruments has designed testability into its bipolar PLDs through the addition
ottest input and test product lines. Utilizing the same circuitry as the main array fuses,
a test pattern Is programmed Into the test array fuses which address and program at
least one fuse in each input and product line. In addition to verification of the main
fuse array, the test lines provide a further programmability checkpoint for each device. These same test lines enable TI to do functional, dc, and ac parametric testing
on every packaged device.
Figures 1 and 2 are simplified diagrams of the test circuitry for the TIBPAL16XX series
devices. Note that the test lines allow testing of actual input and output circuitry;
therefore, ali guaranteed specifications can be tested. AC testing through the test circuitry Is closely correlated to worst case paths and should eliminate the need for ac
testing at the customers incoming inspection.
3-63
I
TEST INPUT BUFFER
By using the test Input lines, all
outputs may be toggled and
speed can be checked from
one input·to all outputs.
STANDARD
OUTPUT
BUFFER
STANDARD
OUTPUT
BUFFER
··•
P19
P18
P17 - P13
STANDARD
OUTPUT
BUFFER
P12
Figure 1. AddHlonallnput Lines
I
INPUT
BUFFER
I
INPUT
BUFFER
I
INPUT
BUFFER
J
rEEDBACK~
BUFFER
TEST
OUTPUT
BUFFER
By using the test product lines
TI can cheCk every input and
Implement dynamic test from
every Input to one output.
Figure 2. Additional Product Lines
3-64
USER TESTABILITY FEATURES
In addition to the designed-in testability features used in factory testing, features
were also added to simplify user testability. Table 1 lists user testability features offered on TI programmable logic devices and associated software products available
to assist the user with testing PLD's.
Register Pre-Load
This feature allows the user to pre-load the output registers to known states prior to
applying data at inputs and/or I/O's and clocking.
Pre-load can be implemented by writing pre-load vectors in more popular logic compilers following logic equations or can be automatically generated by using automatic vector generation software. Most commercial programmers used for functional test
support the use of pre-load vectors.
The real advantage of register pre-load is that it allows the user to fully test the more
complex codes.
Power-Up Clear, Set or Reset
Power-up clear, set, or reset enables the user to know the state of the register at
power-up. Again, this is a key feature for testability as it allows the user writing test
vectors or the automatic vector generation software with a starting point for register
intensive designs. Table 1 shows the power-up state of the register and resulting
state at the output.
The user can also contribute to the testability of his design by utilizing other features
of the PLD.
Unused Inputs / Product Lines
Unused inputs and product lines can be used to implement set, reset, clear, etc...
functions to register intensive designs which are often hard to test. Often register designs have unused input pins, as well as product lines available for implementing
these functions.
Enable on Combinational Outputs
Combinational outputs have one product line available for implementing the enable/
disable function. The key advantage here can be seen during board testing where
devices need to be isolated from each other. By disabling the output of the PLD, the
user can force input conditions from the extemal source to the devices being driven
by the PLD.
3-65
..
Table 1: User Testability Features
DEVICE
FAMILY
SPEED
REGISTERED
DESIGNATOR PRELOAD
TIBPAD16NS
TIBPAD1SNS
-7
TIBPAL16LS
TIBPAL16R4
TIBPAL16R6
TIBPAL16RS
-7/-10
-7/-10
-7/-10
-7/-10
TIBPAL16LS
TIBPAL16R4
TIBPAL16R6
TIBPAL16RS
-6
-12/-15/-25
-12/-15/-25
-12/-15/-25
-12/-15/-25
REGISTERED POWER-UP
POWER-UP
OUTPUTS AT REGISTER AT OUTPUT
NA
NA
o
o
NA
NA
NA
NA
NA
YES
YES
YES
o
NA
L
NA
L
L
H
H
NA
o
NA
H
H
H
NA
L
4
4
TIBPAL20LS
TIBPAL20R4
TIBPAL20R6
TIBPAL20RS
-7/-10
-7/-10
-7/-10
-7/-10
NA
YES
YES
YES
o
TIBPAL20LS
TIBPAL20R4
TIBPAL20R6
TIBPAL20RS
-15/-25
-15/-25
-15/-25
-15/-25
NA
YES
YES
YES
-/A
-15
-20
YES
YES
YES
101010*
L
L
-85,-55
-85,-55
-85,-55
-85,-55
NA
YES
YES
YES
o
-25
YES
10*
-3,-6
-3,-6
NA
NA
o
TIBPAL22V10
TIBPAL22V10
TIBPAL22VP10
TICPAL16LS
TICPAL16R4
TICPAL16R6
TICPAL16RS
TICPAL22V10Z
TIEPAL10H16PS
TIEPAL10016PS
TIBS2S105
TIBS2S167
1.0
2.23
2.23
2.23
2.23
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
NA
L
L
L
2.23
2.28
2.23
2.23
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
NA
2.23
2.23
2.23
2.23
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
H
L
o
NA
NA
4
L
H
L
L
H
2.28
2.28
2.23
2.23
2.23
2.28
2.23
1.0
1.0
1.0
1.0
L
H/L
H/L
H/L
NA
NA
NA
NA
NA
NA
NA
NA
2.23
2.23
2.28
2.23
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
2.28
1.0
1.0
L
4
o
16244S*
H
NA
NA
NA
NA
2.23
2.23
H
H
H
2.23
2.23
2.23
2.23
H
SS*
-25, -80, -35
-80, -85, -40
-85, -45
1.3
H
H
H
B
B
TIBPSG507
TIBPLS506
EP610
EP910
EP1S10
4
L
H
L
H
NA
NA
NA
NA
NA
NA
- = USER CONFIGURABLE
NA = NOT APPLI CABLE
NOTE: ALL CIIOS PLDS ARE ERASABLE FOR REPEATED PROGRAMIIABILITY.
3-66
VECTOR GENERATION
SOFTWARE SUPPORT
ANVIL (-- DATA I/O --)
ArG
PLDTEST PLDTEST+
2.28
2.28
PLD TESTING OPTIONS
Fuse Verification / Checksum
Checksum testing verifies array fuses to be intact or blown. Each fuse location is assigned a value of 1, 2, 4, 8, 16, 32, 64, or 128. The checksum is the sum (in hexadecimal) ofthe values of positions with blown fuses. As previously discussed, checksum
testing or fuse verification only tests for the state of the fuse and exercises programming circuitry only. Functional circuitry is not tested.
Structured Vector Testing
Structured vector testing, utilizing the software packages shown in Table 1 or generated manually at design conception, allow the user to apply structured test vectors
(see Figure 3) to the device either on device programmers or testers. Figure 4 shows
how to implement pre-load into your vector test.
Fault coverage of structured vectors is graded and documented so the user knows
how much coverage he has for his design. A fault is simply a potential for device failures. Faults graded include logic faults as well as fuse faults.
logic Faults - Check affected gates for S-A-O, or stuck low, and S-A-l, or stuck
high. Figure 5 Illustrates logic faults. Fuse Faults - Check each fuse for intact or blown
Structured vectors are generic so they can be applied to all manufacturers PlDs of
Iike function (e. g. 16l8, 22Vl0, etc ...). Structured vector testing ensures the functionality of the design, and can be performed right on the device programmer. Structured
vector testing should be considered the minimum amount of testing required prior to
application.
Signature Analysis / Logic FingerprintTM / Random Vector Test
Signature analysis or fingerprint testing is sometimes seen as an alternative to structured vector testing. The test applies a pre-determined or psuedo-random vector set
to the inputs of a "known good" device and memorizes the output responses. Subsequent devices are tested against the master. Potential problems exist with this type
of testing.
Master device could be defective resulting in the acceptance of bad devices
and/or rejection of good devices.
Registered devices may never initialize
Outputs may never be put in the correct states to ensure correct feedback
(only structured vectors ensure correct feedback)
Oscillating conditions not controlled (structured vectors can void oscillations)
Different manufacturers use different power-up / pre-load conditions
Percent of coverage is unknown
The best case could yield an adequate functional test while the worst case may test
little or nothing. The problem is there is no way to detemnine which case you have
as grading Is not available.
3-67
VOOOl
V0002
PIN 1
PIN2
ClXOOlOlONOLLHZHLllN*
COXlOOOOlN~LLHHLLllN*
_-----Itt
J
-
PIN 20-----------------------------------SYMBOLOGY
C = CLOCK
H = EXPECT HIGH
o
L = EXPECT LOW
Z = HIGH-IMPEDANCE
X = DON'T CARE
= DRIVE LOW
1 = DRIVE HIGH
N
=
NO CONNECT
1
.
Figure 3. Test Vectors (Standard JEDEC Form)
DISABLE REGISTERS
P INDICATES PRE-LOAD ~
VOOOl
V0002
r
FORCE REGISTER TO
KNOWN STATE
~
r
PXXXXXXXXNlOOllOOllN*
COXIOOOOlNOLLHHLLHHN*
Y
APPLY INPUT
CONDITIONS AND CLOCK ---------'-
vL
1
EXPECT OUTPUT
CONDITIONS
ENABLE REGISTERS
Figure 4. Pre-Load Implementation - '16R8
• STRUCTURED TEST VECTORS CAN BE APPLIED TO DETECT
S - A - 1 FAULT: Circuit node Ignores input stimuli
remains at a high or "1" state
1t
1t
1 (ACTUAL)
o (EXPECTED)
S - A - 0 FAULT: Circuit node ignores input stimuli
remains at a low or "0" state
o
1
1
0
tot
o
(ACTUAL)
1 (EXPECTED)
t = NODES CHECKED
Figure 5. Faun Grading
3-68
DC Parametric Testing
DC parametric testing includes structured vector or functional testing as described
previously plus the testing of critical current/voltage parameters to ensure they meet
the specifications prescribed by the TI data book.
The testing of dc parametrics, such as input and I/O leakage currents, output high
and low voltages under dc loading, power supply current, etc ... will only improve the
quality of the PLD going Into the application by ensuring that devices which are functional were not damaged due to ESD (electrostatic discharge) or EOS (electrical
overstress) during the customization process.
DC parametric testing can not presently be performed on device programmers and
therefore requires the use of automatic test equipment (ATE). de parametric testing
coupled with structured vector testing should provide the user an "optimum" test with
a "medium" investment.
ACTesting
AC testing ensures that the PLD meets all the speed requirements of the design. A
good ac test measures propagation delay time through all possible paths and, when
coupled with functional and dc parametric testing, provides the ultimate PLD test.
There are two types of ac testing to be considered: functional ac and measurement
ac testing. Functional ac testing becomes a popular test method for PLDs. This method applies structured test vectors and sets strobes to ensure transistions occur with
proper timing. Functional ac does a good job of simulating the actual design if structured vectors with good coverage are used.
In contrast, measurement ac testing tests and measures all speed parameters utilizing all possible input and output combinations. This type of testing is typically only
available from the factory as it requires another level of vector grading and dedicated
engineering resources.
AC testing usually requires a large investment by the user in not only hardware, but
also in engineering time in the development of extenSive test programs, bench to
tester correlation, load boards, vector software, etc...
Texas Instruments performs extenSive worst case code characterization prior to device release. Each device shipped from TI undergoes ac testing using the device's
test rows and test columns. Many users find post programming ac test does not justify
the payback in terms of a higher level of quality.
3-69
WHY TEST AFTER PROGRAMMING?
As previously discussed, verification of the fuse array following programming does
not ensure total functionality; therefore, the user must determine what amount of testing is required after programming. The following concems should be considered.
Programming
Programming exposes the device to super voltages (up to 10.75 volts) and currents
high enough to overstress devices. TI PLDs are designed to withstand these conditions; however, all leakage current parameters should be tested to eliminate the risk
of electrical overstress.
An uncalibrated programmer can expose devices to voltages/currents outside specified ranges.
Handling
In addition to programming, most users designate their custom function which was
programmed into the PLD through labeling or marking. The added handling required
to program and customize the PLD increases the chances for ESD (electro-static discharge) damage unless strict adherence to ESD protection procedures is observed.
Custom Function
TI goes to extreme measures to ensure device functionality and performance; however, each user design is a custom function and should be treated as such during final
testing prior to application.
Test vs Rework
Figure 6 compares the impact of testing on board rework and, consequently, manufacturing cost. This illustration compares no testing vs. functional and dc parametric
testing. Using conservative figures for rework cost, the data shows rework cost due
to untested PLDs can exceed one dollar per PLD used. A Similar analysis ofthe reader's application may show a cost savings which would result from testing after programming.
3-70
Rework without test
Rework with functional
and dc parametric
testing
o
o
10
PLDs PER BOARD
20 ASSUME:
10 PAls per board
$50 Rework cost per board
200 Boards per month
Rework costs due to untested PLDs:
- 20% X 200 X 50 = $2000
- 10% X 200 X 50 = $1000
Rework without test
2K
Rework with functional
and dc parametric
testing
1K
o
o
100
200
BOARDS PER MONTH
Figure 6. Test vs Rework
3·71
TI PROGRAMMING AND TEST SERVICES
What services are offered by your PLD manufacturer? Texas Instruments provides its
customers with a three phase service program which provides for programmed and
tested PLDs ofthe highest quality (see Figure 7) direct from the factory or through Tl's
authorized distributors.
Factory Programmed and Tested PLDs
TI has the capability to support run rates greater than 1000 parts per code per month
with factory programmed and tested PLDs. TI generates structured test vectors and
performs 100% functional, dc parametric, and ac testing on PLDs programmed to
your custom logic function. Custom symbolization is also included in the factory programmed PLD flow, thereby delivering ship-to-stock and/or ship-to-WIP product.
Impact DeSign and Services Centers
Texas Instruments took the leadership role in the provision of program and test services to its customers by implementing the Impact Center approach in 1986. The Impact Centers offer the customer a local "quick turn" production resource with factory
quality programming, marking, and testing on TI owned and maintained eqUipment.
Strict adherence to Tl's ESD protection gUidelines is maintained. Production specifications remain under TI control and operations are continuously audited by TI.
Endorsed Program and Test Centers
An extenSion of the Impact Center philosophy, an endorsed center is a distributor
funded program and test facility which meets or exceeds TI specifictions. Each center has the capability to program, mark, and test PLDs. Production flows are approved to guarantee the user receives devices of ship-to-stock quality. The centers
are audited bi-annually to ensure compliance.
Tables 2 lists the Tllmpact Centers. An updated listing for Endorsed Centers may be
obtained through theTI PLD Bulletin Board (214) 997-5665, theTI PLD Hotline (214)
997-5666 or your local TI Sales Representative.
3-72
CUSTOMAC
TESTING
CUSTOM DC
TESTING
LESS
THAN
50
PPM
CUSTOM
FUNCTIONAL
TESTING
LESS
THAN
400
PPM
PROGRAMMING
LESS
THAN
FUNCTIONAL,
DC,ANDAC
USING TEST LINES
LESS
THAN
10 K
PPM
1K
PPM
TI FACTORY
PROGRAMMED
PLDs
IMPACTOR
ENDORSED
CENTER
DISTRIBUTOR
(PROGRAM
ONLy)
UNPROGRAMMED
PAls
Figure 7. TI Programmable Logic Services
Table 2. TI Impact Design and Services Centers
NORTHERN CALIFORNIA
BOSTON
MARSHALL IMPACT CENTER
HALL-MARK IMPACT CENTER
336 LOS COCHES STREET
6 COOK STREET
MILPITAS, CA 95035
PINEHURST PARK
(408) 942-4600
BILLERICA, MA 01821
(617)935-9777
3-73
3-74
A Designer's Guide to the
TIBPSG507
Robert K. Breuninger and Loren E. Schiele
with Contributions by
Joshua K. Peprah
TEXAS
INSTRUMENTS
3-75
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
such testing necessary to support this warranty. Unless mandated
by government requirements, specific testing of all parameters of each
device is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices describ·ed herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.
Copyright © 1987, Texas Instruments Incorporated
3-76
Contents
Title
Page
INTRODUCTION
3-81
FUNCTIONAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-81
THEORY OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1: Waveform Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2: Refresh Timer. . .. ... ... . .. . .. . . ... .. . .. .... . ..... . . .... .... .. . .. . .. .. . ... .. . .. ...
Example 3: Dynamic Memory Timing Controller. .. . ... .. . ....... .... . ... .. . . .. . .. ...... ... .. . ...
3-81
3-83
3-86
3-89
DESIGNER NOTES ...........................................................................
Obtairiing Maximum Counter Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expanding the 6-Bit Counter ..................................................................
Software Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-95
3-95
3-95
3-95
Appendixes
A
B
C
ABELFiles ................................................................................
CUPL Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
'PSG507 Fuse Numbers... ... ... . .... .. .. . .. ... .. .... . .. . .. . . ... . .. . ... .. ... ... ... . .. .. . ....
3-101
3-111
3-123
3-77
3-78
List of Illustrations
Figure
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Title
PSG Architecture
Clock Generator Timing Requirements ....................................................
SCLR at COUNT 11 ..................................................................
Waveform Generator ..................................................................
Refresh Timer Requirements ............................................................
Expanding to 7-Bit Binary Counter .......................................................
Refresh Timer ........................................................................
Memory Timing Controller .............................................................
Flow Chart: Dynamic Memory Timing Controller ..........................................
Access Cycle .........................................................................
Refresh/Access Grant Cycle ............................................................
Counter Control Logic .................................................................
Memory Timing Controller .............................................................
Registered SCLR Example ..............................................................
Expanding the 9-Bit Counter ............................................................
Resetting after COUNT 383 ............................................................
Holding the 9-Bit Counter at COUNT 383 ................................................
Page
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3-82
3-83
3-84
3-85
3-86
3-87
3-88
3-89
3-90
3-91
3-92
3-93
3-94
3-96
3-97
3-98
3-99
3-79
3-80
INTRODUCTION
The tenn PSG stands for Programmable Sequence Generator.
The PSG is the newest member of the programmable logic
family. It combines the powerful benefits of programmable
array logic (PALs) with the specialized world of Field
Programmable Logic Sequencers (FPLSs).
Applications such as wavefonn generators, state
machines, timers, and simple logic reduction are all possible
with a PSG. By utilizing the built-in binary counter, the PSG
is capable of generating complex timing controllers. In short,
the PSG offers the system designer an extremely powerful
building block.
The purpose of this application report is to describe
the functional operation of the PSG507 and demonstrate how
it can be applied in real-world applications. Three design
examples that highlight the features and flexibility of the PSG
will be discussed.
on the next active clock edge. When either CNT/HLDO or
CNT/HLDI is taken active high, the counter is held at the
present count and is not allowed to advance on each active
clock edge. The SCLR feature overrides the CNT/HLD
feature when both functions are simultaneously active high.
The functional benefit of both these features will be further
clarified in the examples shown later in this appliction report.
The eight internal state registers feed back into the
AND array. These registers can be used to store input data,
to keep track of binary count sequences, or they can be used
as output registers when connected to a nonregistered output
cell. The state registers differ from the output registers in
that they feed back into the input array. They can also be
used to override an operating sequence such as demonstrated
in the designer notes located at the end of this application
report. By using extra state registers, the 6-bit counter can
be expanded as shown in the second example. Other uses
of the internal state registers will become apparent upon
reading the examples shown.
FUNCTIONAL DESCRIPTION
THEORY OF OPERATION
Figure 1 shows the architecture of the PSG507. Major
features include 13 inputs, eight programmable registered
or nonregistered outputs, eight SIR state registers, and a 6-bit
binary counter with control logic. The clock input is fuseprogrammable for selection of positive or negative edge
triggering.
The binary counter, state registers, and output cells are
synchronously clocked by the fuse-programmable clock
input. The clock polarity fuse selects either positive or
negative edge triggering. Negative edge triggering is selected
by blowing the clock polarity fuse. Leaving this fuse intact
selects positive edge triggering.
Each output cell on the PSG can be configured for
registered or nonregistered operation through the output
multiplexer fuse. Nonregistered operation is selected by
blowing the output multiplexer fuse. Leaving this fuse intact
selects registered operation.
The PSG507 has 13 inputs, each providing a true and
complement input to the AND array. Pin 17 functions as
either an input and/or an output enable. Blowing the output
enable fuse lets pin 17 function as an output enable but does
not disconnect pin 17 from the input array. When the output
enable fuse is intact, pin 17 functions only as an input with
the outputs being permanently enabled.
The 6-bit binary counter is controlled by a synchronous
clear and a count/hold function. Each control function has
a nonregistered and registered option. When either SCLRO
or SCLRI is taken active high, the counter resets to zero
The PSG architecture is capable of operating in many
different modes. When comparing the operation of a PSG
to a PAL, the outputs in both devices can be configured as
an AND/OR function of the inputs. One major difference
between a PSG and a PAL is that a programmable OR array
is used in the PSG. This allows a selected number of AND
terms to be connected to each output as compared to a fixed
number of AND tenns assigned to each output on a PAL.
The programmable OR array is the more efficient in that it
lets the user assign the exact number of AND terms to each
output as required by the application.
Another major difference between the PAL architecture
and that of a PSG is that the output cells on a PSG are not
fed back into the input array. Typically, output feedback is
used for building a counter or for holding state infonnation.
Since the architecture of the PSG already includes state
registers and a binary counter, the requirement for output
feedback is eliminated in most applications. This is a benefit
to the user because valuable output cells and AND terms are
not wasted when generating these functions.
When a Field Programmable Logic Sequencer is
compared to a PSG, the most obvious difference is the
addition of a binary counter. Most state machine designs can
be simplified by referencing all or part of each sequence to
a binary count. This technique is highlighted in the third
example shown in this application note. A comparison will
also reveal that the output cells on a PSG can be configured
3-81
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3-82
,--,~~a7
for nonregistered· operation. This permits the outputs to be
directly fed from the counter, AND/OR array, or state
registers. Example I highlights this feature.
In short, the outputs of a PSG can be controlled by any
or all of the following conditions:
to the master clock (PSG CLK) of the PSG. As shown in
the timing diagram, at count 11 (10112) the sequence is
repeated. By using the SCLRO function, a logic equation can
be defined to reset the counter at count 11. This concept is
demonstrated in Figure 3.
With the binary counter programmed to clear at 11,
it is a simple matter to decode the outputs from the binary
count. With the REF CLK equal to the inverse of binary
count zero (CO), REF CLK can be directly generated from
the binary counter. A product term is required to connect
CO to the output cell. The output register is bypassed by
blowing the output multiplexer fuse. Figure 4 shows how
CO can be connected.
SYS CLK and PCLK are decoded from the present state
of the binary counter through the SIR outputs. Since the SIR
register holds its present state until changed, product terms
have to be used only during output transitions. For example,
when the binary counter reaches one, a product term is used
to reset the SYS CLK on the next clock transition. Below is a
summary of the product terms required to control SYS CLK
and PCLK. Note that the output transitions are set up in the
previous clock cycle. Also note that only one product term
is used regardless of how many output terms switch. This
is demonstrated at count 5 and count 11. Figure 4 also shows
how SYS CLK and PCLK are connected.
• Present state of the inputs
• Present state of the binary counter
• Present state of the state holding registers
The key to understanding state machine design when
using a PSG is to realize that different states can be assigned
for each sequence. In other words, the assigned state
determines which sequence is in operation. The length of
each sequence is controlled by the SCLR function. Once the
count sequence has been programmed to the desired length,
each output can be easily decoded from the present state of
the binary counter. The user will soon discover that complex
state machines are easily developed when using this
technique. This technique is demonstrated in Example 3.
Example 1: Waveform Generator
The first example demonstrates a design for a simple
clock generator used for driving a microprocessor operating
at 5 MHz (required duty cycle of33.5% high, 66.5% low).
In addition to the 5 MHz system clock (SYS CLK) , a
reference clock (REF CLK) operating at 15 MHz (50% duty
cycle) and a peripheral clock (PCLK) operating at 2.5 MHz
(50% duty cycle) are required for other timing controllers
and peripherals throughout the system. Both clocks must be
in close phase with the SYS CLK to guarantee synchronous
operation within the system.
The above example demonstrates one of the many uses
of the binary counter in the PSG. State registers are not used
in this particular application, only the binary counter and
three outputs. A 30 MHz clock, typically generated from
a crystal, is used for driving the binary counter of the PSG.
The three generated clock signals are decoded from the
binary count. The unused inputs and outputs are still available
for other sequential or combinational applications.
Figure 2 shows the timing diagram for the above
application. For reference, a decimal count has been assigned
o
2
3
4
5
CNT
CNT
CNT
CNT
1:
5:
7:
II:
Reset SYS CLK
Set SYS CLK, reset PCLK
Reset SYS CLK
Set SYS CLK, set PCLK
This simple application demonstrates the basic concept
of building a waveform generator using the PSG. This
concept will be expanded further in Example 3 when a
memory timing controller is developed. The basic rules for
building a waveform generator are summarized below.
• Program the counter to reset to zero after the
desired count length is reached.
• Generate the logic equations to control the
outputs from the present state of the binary
counter.
6
7
8
9
10
11
o
PSG CLK
(30 MHz)
REF CLK
(15 MHz)
SYS CLK
PCLK
r
L-_ _ _ _ _ _ _ _ _ _.....
(5 MHz)
. . .________________.....f"72.5
MHz)
Figure 2. Clock Generator Timing Requirements
(Example 1 - Waveform Generator)
3-83
11
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(Example 1 - Waveform Generator)
3-84
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Figure 4. Waveform Generator
(Example 1)
3-85
Example 2: Refresh Timer
The second example demonstrates a design for a refresh
timer used for signaling to a memory controller that it shoUld
execute a refresh cycle. As required by the dynamic memory,
every row (256 on TMS4256) must be addressed once every
4 ms. One method used to guarantee that this requirement
is met is to refresh one row at least once every 15.6 p.s. With
a 5 MHz system clock, the timer should be set for a division
rate of approximately 77 clock cycles. This condition will
generate a refresh request every 15.4 p.s.
The memory controller executes the refresh request
(REFREQ) immediately if it is not involved in an access
cycle. If the memory controller is executing an access cycle,
then the refresh request will not be honored until the access
cycle is completed. A refresh complete input (RFC) is
required on the refresh timer to acknowledge when the
refresh cycle has been completed by the memory controller.
It is important that the timer does not stop, even though a
refresh complete signal has not been received. This
guarantees the refresh requirement is not violated. This also
assumes the memory controller will complete the refresh
request sometime in the next 77 clock cycles.
Figure 5 shows the timing diagram for the above
application. A decimal count has been assigned to the PSG's
master clock (PSG CLK) for reference. The counter is held
at zero until the reset input is taken inactive low. Once the
counter reaches 76 (equal to 77 clock cycles) the REFREQ
output is driven active (low). The REFREQ output returns
inactive high on the first positive clock edge after RFC goes
active high. RFC is the signal from the memory controller
that tells the refresh timer when the refresh operation has
been completed. The REFREQ output remains low until the
RFC signal has been received.
In order to generate a refresh request every 77 clock
cycles, a 7-bit counter is required. Since the internal counter
of the PSG is 6 bits, one of the state holding registers is
required to expand the counter to 7 bits. As shown in
Figure 6, only two product terms are required to expand to
7 bits; one product term to set the register when the 6-bit
counter reaches its full count (63), and one product term to
reset the register after count 76. Since both the binary counter
and the added register need to be reset after count 76, a single
product line can be used for both. (For additional details on
expanding the 6-bit counter of the PSG, see the designer notes
at the end of this application report.)
Figure 7 shows the fuse map for the entire refresh
timer. The refresh timer is initialized by taking the RESET
input high. When RESET is taken high, a single product line
is activated and all other product lines are disabled. On the
next active clock edge, the binary counter and C6 are cleared
and the REFREQ output is set high. The refresh timer will
begin counting when RESET returns low. When the 7-bit
counter reaches 76, a product line goes active (high) and on
the next clock edge forces C6 and the 6-bit counter to zero.
Note that the output register holding REFREQ is also reset
to zero. The RFC input is connected to a product line which
in tum is connected to the set input of the REFREQ output
register. On the next active clock edge after RFC is taken
high the REFREQ output will return high.
PSG ClK
RESET
RFC _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
Figure 5. Refresh Timer Requirements
(Example 2 - Refresh Timer)
3-86
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(Example 2 - Refresh Timer)
3-87
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00-15
00-015
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Figure 8. Memory Timing Controller
(Example 3)
3-89
Figure 9 shows a detailed flow chart for the intended
application. Note that two sequences are executed and three
states are used. State 0 (STO) provides an initalization and
holding state, while state I (STl) is assigned to the access
sequence. The access sequence consists of 10 clock cycles
as shown in Figure 10. State 2 (ST2) is assigned to the
refreshlaccess grant sequence (Figure 11). This particular
sequence takes 20 clock cycles, with a logical decision being
made between count 9 and count 10. If at count 9 RDY is
low, the counter will continue on and execute the access grant
sequence. If ROY is high, the controller will clear the counter
and return to state O.
START
STATE 2
SET PO - L, P1 - H
STATE 0
CNT,PO.P1 - L
RAS.ROY,MC1,CAS - H
MSEL.RFC - L
EXECUTE REFRESH
SEQUENCE (Figure 11)
NOTE:
IF ALE· MilO - H
THEN SET ROY - L
IF RESET - H
GO TO STATE 0
YES
YES
NO
NO
YES
STATE 1
SET PO - H,P1 - L
ACCESS GRANT
EXECUTE ACCESS
SEQUENCE (Figure 10)
NOTE:
IF RESET - H
GO TO STATE 0
NOTE:
IF RESET - H
GO TO STATE 0
Figure 9. Flow Chart: Dynamic Memory Timing Controller
3-90
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STO
STO
STO
ST1
0
0
0
0
0
ST1
ST1
ST1
STl
ST1
Z
3
4
5
REF CLK
IST1 ST1
7
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MSEL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--I
__________________________....;14-- ta(cl---.t
'L____________- J
CAS
REFREQ - H. RESET - L
MCl - H. RFC - L. ROY - H
Figure 10. Access Cycle
Developing the logic equations for this application
becomes a simple matter when referencing the sequences to
a decimal count (Figures 10 and II). It is important to realize
that each sequence has been referenced to a state. This allows
the same binary counter to be used for each sequence, even
though each sequence is of a different length.
The first step in implementing the above application
is to define the logic equations which will make the binary
counter perform as described in the flow chart of Figure 9.
As will become evident, these equations fall directly from
the flow chart. After the counter has been made to perform
as described, the outputs can be easily decoded from the
binary count and the present state of the state holding
registers.
Figure 12 shows a fuse map for step I as described
above. Initalization is performed by taking the reset input
high. When this condition occurs, all product lines except
the reset product line are forced inactive. When the reset
product line is active, the counter and state holding registers
(PO and PI) are reset to zero on the first active clock edge.
The CNTIHLD I register is set high, which places the counter
in the hold mode. The RDY, MCI, RAS, and CAS outputs
are driven high on the same active clock edge_ Since the RDY
output does not feed back to the AND array, a buried state
register, BRDY, is used to monitor the RDY output and is
also set high. MSEL and RFC are driven low.
Controlling the binary counter is a simple matter and
normally takes only a couple of logic equations. For each
sequence, a start and stop condition must be defined. In the
case of STl, when the condition RESET = L, ALE = H,
MIlO = H, REFREQ = H, PO = L, and PI = L occurs,
STO (PI = L, PO = L) changes to STi (PI = L, PO = H),
and the CNT/HLDI register is driven low to let the counter
advance on the next active clock edge. When the counter
reaches nine, STI returns to STO and the counter is cleared
and put back into the hold condition.
In the case of ST2, when the condition RESET = L,
REFREQ = L, PO = L, and PI = L occurs, STO changes
to ST2 (PI = H, PO = L) and the CNT/HLDI register is
driven low to let the counter advance on the next active clock
3-91
Refresh Sequence
Access Sequence
edge. As shown in the flow chart, if M/IO and ALE go high
while in state 2, ROY and BROY will be reset low on the
next active clock edge. When the counter reaches nine, if
ROY (BROY) is high the state registers are returned to STO
and the counter is cleared and placed back into the hold
condition. If ROY (BROY) is low, the counter advances on
until it reaches 19. ST2 then returns to STO with the counter
being cleared and placed back into the hold condition.
With the binary counter programmed to execute the
flow chart in Figure 9, it is now a simple matter of decoding
the outputs to perform as required in Figures 10 and 11. This
is the same technique used in Example 1, except now a state
has been assigned to each sequence. Below is a summary
of the switching requirements for both the access (ST I) and
the refresh sequence (ST2).
STl
STl
STl
STl
CNT
CNT
CNT
CNT
0:
1:
2:
9:
Reset RAS
Set MSEL
Reset CAS
Set RAS,
Reset
MSEL,
Set CAS
ST2 CNT 0:
ST2 CNT 1:
ST2 CNT 5:
ST2
ST2
ST2
ST2
ST2
CNT
CNT
CNT
CNT
CNT
Reset MCI
Set RFC,
Reset RAS
Reset RFC
6:
7:
10:
11:
12:
Set RAS
Set MCI
Reset RAS
Set MSEL
Reset CAS,
Set ROY,
Set BROY
ST2 CNT 19: Set RAS,
Reset MSEL,
Set CAS
Note that the transition changes are set up in the
previous clock cycle, just as in Example 1. Figure 13 shows
a complete fuse map for the memory controller.
i4-----REFRESH C Y C l E - - - - - I _ - - - - - A C C E S S CYCLE IF REQUIREO'----~
ClK
AlE __________
Mlm
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STO
I
ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
I
*
ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2 STO STO
~
11
12
13
14
15
16
17
18
19
0
0
OSC
MC1----------,~
~
-
-
-
-
-
-
-
-
-
-
-
------------...,- - - - Tn
- - - -,
"t - ' - \
RFC ______________
;
ROY
I
________________-Jr--ri---------------------------------------------
-
- -
- -I, . . - - - - - - - - - - - - - - - - - - - - - - - - - - - -
_____________________________________________________
MSEl ___________________________________________.J
~--------------------------------------------'L
__________________
-IF ROY - H. RETURN STO
Figure 11. Refresh/Access Grant Cycle
3-92
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Figure 12. Counter Control Logic
(Example 3 - Dynamic Memory Timing Controller)
3-93
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II
~f--=
r:-t-i"
II
~r-MSEl
r-r-::f.:
~~r-=
~r-
i
j
j
I
Figure 13. Memory Timing Controller
(Example 3)
3-94
;::~r-
DESIGNER NOTES
Obtaining Maximum Counter Performance
As with any programmable logic device, there are
usually several different methods for implementing anyone
application. In some cases, device performance is affected.
On the PSG, maximum counter frequency is affected by how
the designer controls the 6-bit counter.
For example, in the waveform generator example
shown at the beginning of this application note, the counter
was reset to zero after reaching count II by using the
nonregistered SCLRO function. By using the registered
SCLRI function, a higher operating frequency is obtainable.
This method requires an additional "AND" term as
shown in Figure 14, but does provide maximum
·performance. Note that during the 10th clock cycle the set
input on the SCLRI register is high. On the next active clock
edge, the counter advances to II and the SCLRI register
is set high. This causes the counter to be reset on the next
active clock edge. At the same time, the SCLRI register is
reset low to allow the counter to advance past zero.
In effect, the setup time requirement for SCLRI is
performed in the previous clock cycle. When using the
SCLRO method, the setup time must be added to the fmax
equation. This results in a lower f max . The same tradeoffs
apply with the CNT/HLD function. The PSG507 data sheet
specifies f max for both methods.
Expanding the 6-Bit Counter
In Example 2, the six bit counter had to be expanded
to 7 bits. This was accomplished by adding one of the state
registers to the most significant bit of the counter. It should
be noted that the synchronous clear and count hold functions
must be controlled through the set and reset inputs of the
added bits. The designer must be aware of certain limitations
when trying to perform this function. Figure 15 shows three
additional bits being added to the 6-bit counter. Note that
every bit added requires two additional "AND" terms.
A problem can arise on certain counts when trying to
generate a synchronous clear before reaching the full binary
count (all outputs high). The designer must ensure that both
Sand R are not high simultaneously. For example,let's say
we want the 9-bit counter to return to zero at count 383
(1011111112). At count 383, the SIR register used for C7
is being told to set. Therefore, any reset command would
result in both Sand R being high simultaneously.
This problem, only seen on a few data words, can be
solved by using another state register to control the counter
reset. This method is similar to that used above to obtain
maximum operating frequency. Figure 16 shows the 9-bit
counter returning to zero after count 383. Notice that at
count 382 the extra SIR register is being told to reset on the
next active clock edge. At count 383 the six product lines
controlling C6, C7, and C8 are disabled by the feedback from
the extra register, in particular the S input on C7. At
count 383, the 9-bit counter will return to zero and the extra
register is set high.
An extra register may also be needed to achieve the
count/hold function when using an expanded counter. During
certain counts the added bits will change state, even though
the 6-bit counter is programmed to hold. For example,let's
say we want the 9-bit counter to hold at count 383. Even
though the 6-bit counter can be held at 111111, C6 and C7
will advance on the next active clock edge. In order to hold
C6 and C7 where they are, an extra register is used to disable
the product lines responsible for the transition from count
383 to 384. Since the counter. is on hold, the extra hold
register can only be reset from an input pin or a state
register(s) transition (not on thll next count). In this example,
an input pin is used to reset the extra register and the
CNT/HOLD register. When the CONTINUE input is taken
low, the counter will continue to advance. The system must
guarantee that the continue input will not be low during count
382 to avoid the indeterminant set = H, reset = H state.
Figure 17 shows this 9-bit counter.
It is also important to note that when using extra
registers a reset input may be necessary to set the extra
registers high after powerup, since all SIR registers powerup clear. This requirement would not be necessary if the
phase of the extra register was reversed. This is easily
accomplished by using the inverted feedback from the extra
register. However, it is good state machine design practice
to include a reset input that forces all SIR registers to a known
state.
Software Support
The PSG507 is supported by two software packages;
CUPL, which was created by and is supported by Assisted
Technologies, a division of Personal CAD Syste~s
Incorporated, and ABEL, which was created by and IS
supported by FutureNet, a division of Data 1/0 Corporation.
Each of these software packages can be used to reduce
equations and to generate a fuse map necessary to program
the PSG507. Appendices A and B show the ABEL and CUPL
files for Examples I, 2, and 3. In addition, a PSG507
template is shown for each software packa~e. Thes.e
templates provide software information that wdl make It
easier for the designer to create the source files.
Test vectors are included with the ABEL and CUPL
source files so software simulation can be performed on the
computer. Ifthe proper instruction is provided, the software
will attach the test vectors to the end of the fuse map. This
allows programming equipment to run a functional test on
each device immediately after programming.
3-95
10
COUNT 11"""\
f
f"/
l~
~1
C3
C4
CS
SCLRO
-'"
r
;::;:::
;::;,
~
oolHLOO
~"-.
If
1!!.
-II
~
~
~
:;=
:=:::
==
~~
~~r-
~r;:::~r-
~r-
~r~r-
u=t=r-
.~~rFigure 14. Registered SCLR Example
(Designer Notes)
3-96
rC~~N!_255
~----~
--
-
- -- --
-
-~-.
---------
Cg~~:~,2,~5
-COUN~~127
__
___
,NT 53
C5
f!
II r:=:r;=
t--
SCLRO
H>.
- CNTIHLOO
t-t.
r-lf
;::-
c.
C7
{ } C8
;::J[
~
-n~
.-f::
;::~
:=::::r,.
~~~~-
~~-
~~;::~-
~~~~Figure 15. Expanding to 9-Bit Counter
3-97
COUNT;::il
COUNT
COUNT 38211COUNT 383-
,COUNT 255
rCOUN;C~::;NT_
_C62~NT 63
f
I C6
f'(
II
r----
r=s=
I
SCLRO
---~
H:
- OOIHLOO
~
-;:: f::-t:
':'=
~
~
C6
C,
_,,6-
H:
H:
K::
~IC~>
~r-
;::~r-
~r~r-
~tt
~
~~r-
~r~~rFigure 16. Resetting after Count 383
(Expanding the 6-Bit Counter)
3-98
COUNT 255-
,COUNT 255
,COUNT 127
,COUNT 127
,COUNT 63
COUNT 511COUNT 382-
~-
CONTINUE:-:
C6
0
,I ,c::::s:
co
Cl
C2
C3
c.
CS
SClRO
~
1i
:=:-
~
Ii
- OOll.',I'"
~
~
C8
~
:0
::f.
~
~
i
I
I
~
~r~r~r-
~r-
1
~~r. ~~rI
:~:F~~~r-
I
,
~I~
Figure 17. Holding the 9-Bit Counter at Count 383
(Expanding the 6-Bit Counter)
3-99
•
3-100
Appendix A. ABEV" Files
n "
n n
n
n n
n n
n n n n "
n n
"
n "
" ABEL (tm) TEMPLATE FOR THE TI PSGS07
" This file provides the PSGS07 designer quick access to the information
" needed to write an ABEL source file. To use this file as a template, make "
a copy and delete this box from your new file.
" NODES: The PSG counter bits, counter control bits and state register bits"
are accessed through the use of nodes. Any valid identifier can
be used for node names. The node numbers are specific and must be "
used as shown below. Nodes that will not be used do not have to be "
declared.
" OUTPUT STRUCTURE:
The default output stucture is registered. The output"
type is determined by usage, i.e. QO := (COUNT==7);
will cause QO to remain registered and QO = (COUNT==7);"
will cause QO to be combinatorial. When an output is
used as nonregistered, ABEL will automatically program "
the associated reset fuses as required in the PSGS07
data sheet. Unused product terms can be left
connected to either side of an output register .
• CLOCK POLARITY:
The default clock polarity is active on the rising edge.
The statement fuses [7360]=1; can be used to blow the
clock polarity fuse so that the clock will be active on
the falling edge (fuses [7360]=0; is the default). 7360
is the clock polarity fuse number.
" OUTPUT ENABLE:
The output enable fuse is blown by using the equation
enable output = len; where output is a defined output pin
or set of outputs and en is assigned to pin 17. The
default condition is permantly enabled with pin 17 an
input. If desired the default condition can be specified"
with enable output = en; This fuse can also be blown by
the statement: fuses [7361]=1;
" SET NOTATION:
Set notation is often used to represent control, buried
state, and output registers. This is done to simplify
equations. The sets shown below (QO = [QO, QO r];) are
in the form; New register name = [set input, reset input]. "
Note that the ouput register pin name specifies the set
input.
n
The sets 'high' and'low' (high=[l,O]; and low=[O,l];) can"
be used to set or reset the SiR registers.
Example:
Q1 := high & 10; will cause pin 9 to go high on the next
clock edge if input pin 7 is high.
During simulation of a PSG507 design the ABEL 2.10a
simulator will advance the counter on each clock depending "
on the state of the counter hold and clear functions.
If counter bits are included on the output side of a test
vector simulation errors will occur. Counter bits included"
on the input side of the test vectors are ignored. The
pow.erup condition (counter bits and all registers low) is
recognized by the simulator.
" SIMULATION:
ABEL is a trademark of Data I/O Corporation
n
"
n
n
n
n
n
n •
n •
n n n
n n n n •
•
•
n n •
n n
"
n •
•
n •
•
•
•
3-101
Module PSGFILE
title 'ABEL TEMPLATE FILE FOR THE TEXAS INSTRUMENTS PSG507'
PSG device 'F507';
• Input pin assignments
CLK
pin
1;
IO
pin
7;
Il
pin
6;
I2
pin
5;
I3
pin
4;
I4
pin
3;
IS
pin
2;
I6
pin 23;
I7
pin 22;
pin 21;
I8
I9
pin 20;
pin 19;
IlO
III
pin 18;
Il2_0E
pin 17;
• Output
QO
Q1
Q2
Q3
Q4
Q5
Q6
Q7
• comments
pin and node assignments
pin
node 47;
8; QOJ
pin
9; Q1 r
hode 48;
pin 10; Q2-r
node 49;
node 50;
pin 11; Q3-r
pin 13; Q4-r
node 51;
pin 14; Q5-r
node 52;
pin 15; Q6-r
node 53;
pin 16; Q7:::r
node 54;
• comments
• Internal counter bits & control - node declarations
CO,C1,C2,C3,C4,C5 node 55,56,57,58,59,60;
SCLRO
trol
SCLR1
CNTHOLDO
CNTHOLD1
node 25;
• Buried
PO
P1
P2
P3
P4
P5
P6
P7
state registers - node declarations
node 31; PO r
node 39;
• buried
node 32; P1-r
node 40;
• buried
node 33; P2-r
node 41;
• buried
node 34; P3-r
node 42;
• buried
node 35; P4-r
node 43;
• buried
node 36; P5-r
node 44;
• buried
node 37; P6-r
node 45;
• buried
node 38; P7:::r
node 46;
• buried
@page
3-102
node 26;
node 28;
node 29;
• nonregistered counter clear conSCLR1_r
node 27;
CNTHOLD1 r node 30;
• registered counter clear control
• nonregistered count/hold control
• registered count/hold control
state
state
state
state
state
state
state
state
register
register
register
register
register
register
register
register
00
[00, 00 r];
01[01, 01-r];
02[02, 02-r];
03[03, 03-r];
04[04, 04-r];
05[OS, OS-r];
06[06, 06-r];
07[07, 07=r];
SCLR1
= [SCLR1, SCLR1 r];
CNTHOLD1_ = [CNTHOLD1, CNTHOLDl_r];
• Intermediate declarations for simplification
[II20E,Il1,II0,I9,I8,I7,I6,IS,I4,I3,I2,Il,IO];
INPUTS
OUTPUTS
[07,Q6,05,04,03,02,01,00];
[P7,P6,P5,P4,P3,P2,Pl,PO];
STATE_
COUNT
[CS,C4,C3,C2,Cl,CO];
1, 0, .X., .Z.;
H,L,X,Z
[1,
0];
high
[0, 1];
low
ck
.C.;
• Use .K. for falling edge, .C. for rising edge clock.
• DEVICE FUNCTION can be specified using state diagrams, equations,
• and truth tables.
test vectors ' optional header
([CLK, INPUTS] -> [OUTPUTS, STATE ]l
[ ck,
] -> [
-] ;
[ ck,
] -> [
];
[ ck,
] -> [
];
end PSGFILE
'count xx
'count xx
·count xx
3-103
Module PSG EX1
title 'ABEL EXAMPLE 11 (Waveform Generator) for the
PSG507 DESIGNERS GUIDE, Texas Instruments, August 26, 1987'
PSG1 device 'F507';
• Input pin assignments
PSG_CLK pin
1;
• Output
REF CLK
SYS-CLK
PCLK
pin and node assignments
8;
pin
9;
node 48;
pin
node 49;
pin 10;
REF CLK IsType ' com' ;
• REF_CLK is combinational
• Internal counter bits & control - node declarations
CO
node 55;
C1
node 56;
C2
node 57;
C3
node 58;
SCLRO node 25;
• Intermediate declarations for simplification
COUNT
[C3,C2,C1,CO];
H,L,clk = 1, 0, .C.;
equations
REF CLK
!CO;
SYS-CLK
.= (COUNT==5) f (COUNT==ll);
SYS-CLK r := (COUNT==l) f (COUNT==7);
PCLK - := (COUNT==l1);
PCLK r
.= (COUNT==5);
SCLRO
= (COUNT=l1);
• High on cnt 5 and 11
Low on cnt 1 and 7
• High on cnt 11
• Low on cnt 5
n Counter cleared after cnt 11
n
The PSG507 has powerup clear of counter· and registers. Six clocks
• are required after powerup for this design to initialize. This
n design could be initialized after one clock by setting SYS CLK and
• PCLK high at COUNTO. i.e. SYS CLK := COUNTO f COUNT5 f COuNT11; and
n PCLK :- COUNTO f·COUNT11;
-
n
3-104
test vectors
([PSG CLK
[
[
[
[
[
[
elk
elk
elk
elk
elk
elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
[ elk
COUNT]
0 ]
1 ]
2 ]
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
0
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
[REF_CLK, SYS_CLK, PCLK])
[
L
L
L ];
[
H
L
L ];
[
L
L
L ];
[
H
L
L ];
];
[
L
L
L
[
];
H
H
L
[
];
L
H
L
[
];
H
L
L
L ];
[
L
L
];
[
H
L
L
[
];
L
L
L
[
[
[
[
[
[
[
[
[
[
[
[
[
[
L
H
H
H
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
H
H
·L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
];
];
];
];
];
];
];
];
];
];
];
];
];
];
end PSG EX1
3-105
Module PSG EX2
title 'ABEL EXAMPLE 12 (Refresh-Timer) for the
PSGS07 DESIGNERS GUIDE, Texas Instruments, August 26, 1987'
PSG2 device 'F507';
• Input
PSG CLK
RESET
RFC
pin assignments
pin 1;
pin 2;
pin 3;
• Output pin and node assignments
REFREQ pin
8; REFREQ_r node 47;
• Internal counter bits & control - node declarations
CO node 55; C1 node 56; C2 node 57;
C3 node 58; C4 node 59; C5 node 60;
SCLRO node 25;
• Buried register
C6 node 31; C6_r node 39; • 7th counter bit
• Intermediate declarations for simpl£fication
COUNT
[C6,C5,C4,C3,C2,C1,CO];
H,L,clk,X - 1, 0, .C., .X.;
.. *
equations
REFREQ
RFC
RESET;
REFREQ_r := (COUNT-76) &
:- (COUNT=63) &
C6
:= (COUNT--76) &
C6 r
SCLRO
= (COUNT=76) &
clear
test_vectors
@REPEAT 76
@REPEAT 20
end PSG_EX2
3-106
!RESET;
!RESET;
!RESET f RESET;
!RESET t RESET;
•
•
•
•
•
([PSG_CLK,RESET,RFC]
[ clk
X]
H
[ clk
L ]
L
[
L ]
clk
L
[
clk
L
L ]
[ clk
H ]
L
[ clk
L ]
L
[ clk
X ]
H
set input
reset input
set input
reset input
synchronous nonregistered
->
->
->
->
->
->
->
->
REFREQ )
H
H
L
L
H
H
H
·CNTO
·CNTl-76
·CNTO
·CNTl-20
·CNT21
·CNT22
·CNTO
Module PSG EX3
title 'ABEL EXAMPLE 13 (Dynamic Memory Timing Controller)
for the PSG507 DESIGNERS GUIDE, Texas Instruments, August 26, 1987'
PSG3 device 'F507';
• Input pin assignments
OSC
pin
1;
RESET
pin
2;
ALE
pin
3;
MIO
pin
4;
REFREQ
pin
5;
• Output
ROY
MC1
RFC
RAS
MSEL
CAS
pin and node assignments
pin
8; ROY r
node 47;
pin
9; MC1-r
node 48;
pin 10; RFC r
node 49;
pin 11; RAS-r
node 50;
pin 13; MSEL r
node 51;
pin 14; CAS r
node 52;
• Internal counter
node 55;
CO
node 58;
C3
SCLRO
node 25;
CNTHOLD1 node 29;
node 31;
PO
PI
node 32;
BROY
node 33;
•
•
•
•
•
OSCILLATOR
RESET - INITIALIZES WHEN HIGH
ADDRESS LATCH ENABLE
MEMORY I/O
REFRESH REQUEST
•
•
•
•
•
•
READY
MODE CONTROL
REFRESH COMPLETE
ROW ADDRESS STROBE
MULTIPLEXER SELECT
COLUMN ADDRESS STROBE
bits & control, and state reg - node declarations
C1 node 56; C2 noae 57;
C4 node 59;
CNTHOLD1 r node 30; •
PO r
node 39; •
pCr
node 40; •
BRDY r
node 41; •
COUNT/HOLD CONTROL REGISTER
BURIED STATE REGISTER
BURIED STATE REGISTER
BURIED READY SIGNAL
• Set notation is used to represent control, buried state, and output
n registers. This is done to simplify the equations.
The following
• sets are in the form; register name = [set input, reset inputJ. Note
• that the ouput register pin name specifies the set input.
ROY
= [ROY, ROY r];
MC1[MC1, MCCr];
RFC[RFC, RFC-r];
RAS[RAS, RAS-r];
MSEL
[MSEL, MSEL rJ;
CAS [CAS, CAS rl;
BROY
[BROY, BRDY_rJ;
• Intermediate declarations for simplification.
The sets 'high' and 'low' are used to set or reset the SIR
• registers. Example: MC1 := high & RESET; will cause pin 9
• to go high on the next clock edge if input pin 2 is high.
high
[1, OJ;
low
[0, 1J;
COUNT
[C4,C3,C2,C1,COJ;
STATE
= [P1,PO];
n STATE REGISTER SET DEFINED
H,L,clk,X = 1, 0, .C., .X.;
@page
n
3-107
equations
enable MCl
=
1;
·outputs always enabled, pin 12 is only an input
• Initialization when RESET is high[ BRDY,RDY,MC1,RAS,CAS]
:= RESET;
[PO_r,P1_r,MSEL_r,RFC_r] := RESET;
• Counter controls defined
SCLRO ~
RESET
f (STATE ==1) & (COUNT==9)
f (STATE-==2) & (COUNT==9) & BRDY
f (STATE===2) & (COUNT==19);
CNTHOLD1
RESET
t (STATE ==1) & (COUNT==9)
f (STATE- 2) & (COUNT==9) & BRDY
# (STATE===2) , (COUNT==19);
CNTHOLD1 r =
(STATE ==0) & ALE & MIO & REFREQ
# (STATE=--O) , !REFREQ & !RESET;
&
!RESET
• Execution of access and refresh sequences
state diagram STATE
• NEXT
State 0:
- case
• STATE
RESET=H
0;
ALE & MIO & REFREQ & !RESET
1;
2;
! REFREQ & !RESET
REFREQ & (!ALE f !MIO)
0;
endcase;
• ACCESS CYCLE
State 1:
RAS
:= (COUNT==O)
low & !RESET;
MSEL_ := (COUNT=-1) & high & !RESET;
CAS
low
!RESET;
:= (COUNT==2)
RAS- := (COUNT==9) & high;
MSEL "= (COUNT==9) & low;
& high;
CAS
- i:=f (COUNT==9)
(COUNT==9) t RESET then 0 else 1;
,
,
• REFRESH CYCLE WITH ACCESS GRANT
State 2:
RDY:= low & ALE & MIO & !RESET;
BRDY := low & ALE & MIO & !RESET;
MC1 - := (COUNT==O) & low & !RESET;
RFC- := (COUNT=-l) & high & !RESET;
RAS- := (COUNT==1) & low & !RESET;
MC1- := (COUNT==3) & high;
RFC- := (COUNT=-5) & low;
RAS- := (COUNT==G) & high;
RAS- :- (COUNT==10)' low & !RESET;
RDY- := (COUNT==11)' high;
BRDY "= (COUNT==11) & high;
MSEL- "= (COUNT==11)' high' !RESET;
CAS - := (COUNT-12), low '!RESET;
RAS- := (COUNT-19)' high;
MSEL
(COUNT==19), low;
CAS_- :- (COUNT==19)' high;
if (COUNT-9) & BRDY then 0 else 2;
if (COUNT==19)# RESET then 0 else 2;
@paqe
"2
3-108
test vectors ' ACCESS SEQUENCE '
([OSC,RESET,ALE,MIO,REFREQ,COUNT]
x x
X
X
[elk, H
[elk, L , L , H , H
o
o
H
[elk, L , H , H
o
[elk, L , X I X , X
X
1
[elk, L , X , X
2
[elk, L , X , X, X
3; @REPEAT 6
@CONST ent
[elk, L , X 1 X , X
lent
ent + 1; }
@CONST ent
X
9
[elk, L I X I X
L
L
H
o
[elk, L
->
->
->
->
->
->
->
[RDY,MC1,RFC,RAS,MSEL,CAS,STATE ])
[H
H, L , H , L , H , 0 -];
[H
H, L ,H
L ,H, 0
];
[ H , H , L , H ,L , H , 1
];
[H
H, L ,L
L ,H, 1
];
[H
H, L , L , H , H , 1
];
[H
H, L , L , H , L , 1
];
->
H,H,L,L,H
, L ,
1
];
->
H, H, L , H, L
H, H, L , H, L
, H ,
, H ,
o
o
];
];
->
test vectors ' REFRESH WITH ACCESS FOLLOWING'
([OSC,RESET,ALE,MIO,REFREQ,COUNT] -> [RDY,MCl,RFC,RAS,MSEL,CAS,STATE ])
[elk, H
X
X
X
X
-> [ H , H , L , H ,L , H , 0 -];
[elk, L , X , X
L
0
-> [ H , H , L , H ,L , H , 2
];
[elk, L , L , L
X
0
->
H , L , L , H ,L , H , 2
];
[elk, L
L, L
X
1
-> [ H , L , H , L ,L , H , 2
];
[elk, L , L , L , X
2
->[H,L,H,L,L ,H, 2
];
[elk, L , L , L, X
3
-> [ H , H , H , L ,L , H , 2
];
[elk, L , H , H
X
4
-> [ L , H , H , L ,L ,H,
2
];
[elk,
L ,X, X
X
5
-> [ L , H , L , L ,L , H , 2
];
[elk, L , X , X, X
6
-> [ L , H , L ,H
L ,H, 2
];
[elk, L , X , X
X
7
-> [ L , H , L , H ,L , H , 2
];
[elk, L , X , X, X
8
-> [ L , H , L , H ,L , H , 2
];
[elk, L , X , X
X
9
-> [ L , H , L , H ,L , H , 2
];
[elk, L , X , X
X
10
-> [ L , H ,L
L, L , H , 2
];
[elk, L X , X, X
11
-> [ H , H , L , L , H , H ,
2
];
[ elk, L , X , X, X
12
- > [ H , H , L , L , H ,L, 2
];
@CONST ent ~13; @REPEAT 6
[elk, L , X , X, X
,ent
->
H, H , L , L ,H , L , 2
];
@CONST ent
ent + l;}
[elk, L , X , X, X
,19
->
H, H , L ,H
L ,H, 0
];
r
test vectors ' REFRESH WITHOUT ACCESS FOLLOWING'
([OSC,RESET,ALE,MIO,REFREQ,COUNT] -> [RDY,MC1,RFC,RAS,MSEL,CAS,STATE ])
[elk, H , X , X
X
X] -> [ H , H , L , H ,L , H , 0 -];
[elk, L X , X
L
0 ] -> [ H , H , L , H ,L , H , 2
];
[elk, L , L , L, X
0 ] -> [ H , L , L , H ,L , H , 2
];
[elk, L
L, L
X
1 ] -> [ H , L , H ,L
L ,H, 2
];
[elk, L , L , L, X
2 ] -> [ H , L , H , L ,L , H , 2
];
[elk, L ,L
L
X
3 ] -> [ H , H , H , L ,L , H , 2
];
[elk, L , L , H
X
4 ] -> [ H , H , H , L ,L , H , 2
];
[elk, L , H , L
X
5 ] -> [ H , H , L , L ,L , H , 2
];
[elk, L , H , L, X
6 ] -> [ H , H , L ,H
L ,H, 2
];
[elk, L , H , L
X
7 ] -> [ H , H , L , H ,L , H , 2
1;
[elk, L , H , L, X·
8 1 -> [ H , H , L , H ,L , H , 2
];
[elk, L , H , L, X
9 1 -> [ H , H , L , H ,L , H , 0
1;
@page
3-109
test vectors ' RESET DURING REFRESH '
([OSC,RESET,ALE,MIO,REFREQ,COUNTI -> [RDY,MC1,RFC,RAS,MSEL,CAS,STATE II
[elk,
[elk,
[elk,
[elk,
[elk,
[elk,
H , X ,
LX,
L , L ,
L , L ,
L , L ,
H , X ,
end PSG EX3
3-110
X,
X,
L,
L,
L,
X,
X
L
X
X
X
X
,.
X
0
0
1
2
3
->
->
->
->
I ->
I ->
I
I
I
I
[
[
[
[
[
[
H
H
H
H
H
H
,
,
,
,
,
,
H
H
L
L
L
H
,
,
,
,
L ,
L ,
L ,
H ,
H,
, L ,
H
H
H
L
L
H
,
,
,
,
,
,
L
L
L
L
L
L
,
,
,
,
,
,
H,
H,
H
H,
H
H,
0
2
2
2
2
0
-I;
I;
I;
I;
I;
I;
Appendix B. CUPL'" Source and Simulation Files
/***************************************************** ***********************1
f* CUPL (tm) TEMPLATE FOR THE TI PSG507
*/
f*
/*
/*
/*
/*
/*
This file provides the PSGS07 designer quick access to the information
needed to write a CUPL source file. By copying this file and deleting
this box from the new file a fill-in-the-blanks template will be left
for use in creating a source file.
*/
*/
*f
*/
*f
*/
f* 6-BIT COUNTER: The 6-bit counter is accessed through use of the PINNODE *f
statement. The pinnode statement is used to assign
*f
/*
variables to the internal node numbers. i.e. pinnode
*f
f*
[33 .. 38] = [CO .. C5].CNT. These variables can then
*f
f*
be used in the same manner as input pins.Using the
*f
/*
field statement, i.e. field COUNTER = [CO .. C5].CNT;
*f
f*
allows an equation like QO = COUNTER'd'3 I COUNTER'd'7; *f
f*
This equation causes the nonregistered output QO to be *f
f*
high only during counts 3 and 7.
*f
f*
*f
f* COUNTER CONTROLS: Clear and hold functions SCLRO, SCLR1, CNTHOLDO,
*f
f*
and CNTHOLDl are specified using the PINNODE
*f
f*
statement. Any valid variable can be used as a node
*f
f*
n~e, i.e. pinnode [39 .. 42] = [CLRO,CLR1,HLDO,HLD1];
*f
f*
These variables can then be used in the same manner
*f
/*
as an output pin.
*f
/*
*f
f* STATE REGISTERS: Buried .registers are assigned using the NODE state- *f
f*
ment, i.e. node [PO .. P7];. The actual registers
*f
/*
used are chosen by software in the order specified.
*f
f*
*f
f* OUTPUT STRUCTURE: Each output can be defined as either registered or
*f
f*
nonregistered. The structure assignment is automatic
*/
f*
and is determined by usage. QO.s = COUNTER'd'77;
*f
f*
causes the QO output to remain registered while
*f
f*
QO = COUNTER'd'77; causes the QO output to be non*f
f*
registered. When using nonregistered outputs CUPL
*/
f*
will automatically program the associated reset fuse
*f
/*
/*
/*
/*
for each product term used as required in the PSG507
data sheet.
*/
*"
*f
/****************************************************************************/
3-111
/**************************************************************************/
1*
1*
1* CLOCK POLARITY: The default clock polarity is active on the rising
1*
edge. The equation OUTPUT.ckmux = !CLK; will cause
1*
the clock to be active on the falling edge. The
1*
default can be specified by OUTPUT.ckmux = CLK;
1*
1* OUTPUT ENABLE: The default condition is outputs always enabled. The
1*
output enable fuse at pin 17 can be blown using the
1*
.oe extention. If pin 17 - EN; the fuse will be blown
1*
by the equation OUTPUTS.oe = EN; where OUTPUTS is a
1*
defined set of outputs. A single output can also be
1*
used to blow the fuse, QO.oe = EN;
1*
1* SIMULATION:
During simulation of a PSG design the CUPL 2.1Sa
1*
simulator will advance the counter on each clock
1*
depending on the state of the counter hold and clear
1*
functions. The powerup condition (counter bits and
1*
all registers low) is recognized by the simulator.
1*
1* CUPL is a trade mark of Personal CAD Systems, Inc.
*1
*1
*1
*1
*1
*1
*1
*1
*1
*/
*1
*1
*1
*1
*1
*/
*1
*/
*/
*/
*/
/**************************************************************************/
3·112
NAME
PARTNO
DATE
REV
DESIGNER
COMPANY
ASSEMBLY
LOCATION
XXXXX ;
XXXXX ;
XX/XX/XX
XX;
XXXXX
XXXXX
XXXXX
XXXXX
/**************************************************************************/
1*
*/
/*
*/
/*
*/
/**************************************************************************/
/* Allowable Target Device Types: TEXAS INTSRUMENTS PSGS07
*1
/**************************************************************************/
/**
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
Inputs
1
2
3
4
5
6
7
17
18
19
20
21
22
23
/**
pin
pin
pin
pin
pin
pin
pin
pin
Outputs
8
9
10
**/
CLK
/* PSG's clock input
/*
1*
1*
/*
/*
/*
1* input and/or output enable
*/
*/
*/
*/
*/
*/
*/
*/
/*
/*
/*
/*
/*
/*
*1
/*
/*
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
**/
11
13
14
15
16
/** Node Declarations **1
pinnode [33 .. 38)
[CO .. 5)
pinnode 39
SCLRO
pinnode 40
SCLR1
pinnode 41
= CNTHOLDO
pinnode 42
CNTHOLD1
node
[PO •. P7)
1*
1*
/*
/*
/*
/*
/* BUILT-IN 6-BIT COUNTER
/* COUNTER CLEAR - non registered
1* COUNTER CLEAR - registered
1* COUNTER HOLD - non registered
/* COUNTER HOLD - registered
/* BURIED STATE REGISTERS
/** Declarations and Intermediate Variable Definitions **1
field COUNTER
= [CS .. O)
/* 6-BIT COUNTER
*/
*/
*1
*1
*/
*/
*1
/** Logic Equations **/
/** End of File **1
3-113
PSG EXl;
Partno
TIOe01;
Date
08/26/87;
Rev
02;
Designer Schiele/Woolhiser;
Company
Texas Instruments/Personnal CAD Systems;
Assembly None;
Location None;
Name
/********************************************************************/
/* Waveform Generator
*/
/*
*/
/* This is the first example from "A Designer's Guide to the
*/
/* PSGS07", by R. Breuninger. In this example a waveform generator */
/* which generates three clocks, running at lS, S, and 2.SMHz, is
*/
/* implemented for the PSGS07 using CUPL. In this implementation */
/* the built-in counter feature of the PSGS07 is utilized to divide */
/* a 30MHz master clock to generate the three output waveforms. The */
/* built-in counter is accessed by defining the variable list
*/
/* [CO .. S] as PINNODE's and then using the list where ever the
*/
/* counter values are needed. The synchronous clear function, SCLRO */
/* is also accessed through use of the pinnode statement.
*/
/********************************************************************/
/* Allowable Target Device Types:
TI PSGS07
*/
/********************************************************************/
/**
Inputs
**/
PSG_CLK;
pin 1
/**
Outputs
/* 30MHz MASTER CLOCK
*/
REF CLK;
SYS-CLK;
PCLK;
/* lSMHz REFERENCE CLOCK
/* SMHz SYSTEM CLOCK
/* 2.SMHz PERIPHERAL CLOCK
*/
[CO .. 3];
SCLRO;
/* BUILT-IN COUNTER
/* COUNTER SYNCHRONOUS CLEAR
*/
**/
pin 8
pin 9
pin 10
~
pinnode [33 .. 36]
pinnode 39
*/
*/
*/
/** Declarations and Intermediate Variable Definitions **/
field COUNTER
[C3 .. 0] .CNT;
/**[SYS_CLK, PCLK, CO .. 3].CKMDX
**/
/** Logic Equations **/
REF CLK
SYS-CLK.r
SYS-CLK.s
PCLK.r
PCLK.s
SCLRO
ICO.CNT;
COUNTER:'d'l t COUNTER:'d'7;
COUNTER:'d'S # COUNTER:'d'll;
COUNTER:' d' 5;
- COUNTER:'d'll;
COUNTER:' d' 11;
/* The PSGS07 has powerup clear of counter and registers. Six clocks
/* are required after powerup for this design to initialize. This
/*_design could be initialized after one clock by setting SYS CLK and
/* PCLK high at COUNT O. i.e. SYS CLK.s a COUNTER:'d'O t COuNTER:'d'5
/* t COUNTER:'d'11; and PCLK.s a-COUNTER:'d'O t COUNTER:'d'll;
/** End of file **/
3-114
*/
*/
*/
*/
*/
Name
Partno
Date
Rev
Designer
Company
Assembly
Location
PSG EX1;
TIOOO1;
08/26/87;
02;
Schiele/Woolhiser;
Texas Instruments/Personnal CAD Systems;
None;
None;
1***************************************************** ***************/
/*
*/
/* Waveform Generator
*/
/*
*1
1* CUPL simulation file for Example 1 from "A Designer's Guide to *1
/* the PSG507".
*1
/********************************************************************/
/* Allowable Target Device Types:
TI PSG507
*1
/********************************************************************/
ORDER: PSG_CLK, %7,. REF_CLK, %9, SYS_CLK, %6, PCLK;
BASE: DECIMAL;
VECTORS:
$msg" ";
$msg" PSG CLK REF CLK
SYS_ CLK PCLK ";
$msg" ---------------------------------------- " ,.
P
0
X
0
0
H
c
L
H
H
C
H
c
c
c
c
c
c
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
H
H
C
C
H
c
L
L
L
L
L
C
H
H
H
L
L
L
L
L
L
L
H
1*
1*
1*
1*
0 */
1 *1
2 *1
3
*1
/* 4 */
1* 5 */
1* 6 */
1*
7
*1
/* 8 *1
/* 9 *1
/* 10 */
/* 11 */
1* 0 */
3-115
PSG EX2;
Partno
TI0002;
-Date
08/26/87;
Rev
02;
Schiele/Woolhiser;
Designer
Company Texas Instruments/Personal CAD Systems;
Assembly None;
Location None;
Nania
/**************************************************************************/
1*
1*
1*
1*
1*
1*
1*
1*
1*
Refresh Timer
This is the second example from "A Designer's Guide to the PSG507", by
R. Breuninger. In this example a dynamic memory refresh timer, which
generates a refresh request every 15.4 uS, is implemented for the TI
PSG507 using CUPL. In this implementation the built-in 6-bit counter
is extended by using one of the buried state registers as the 7th bit.
*1
*1
*1
*1
*1
*1
*1
*1
*1
1***************************************************** *********************/
1* Allowable Target Device Types:
TI PSG507
*1
1***************************************************** *********************/
1** Inputs **1
pin 1
pin 2
pin 4
1** Outputs
pin 8
**1
PSG CLK;
RESET;
RFC;
1* 5MHz SYSTEM CLOCK
*1
1* SYNCHRONOUS RESET OR INITIALIZE *1
1* REFRESH COMPLETE
*1
REFREQ;
1* REFRESH REQUEST
*I
1* BUILT-IN 6-BIT COUNTER
1* COUNTER CLEAR CONTROLS
*1
*1
*1
1** Node Declarations **1
pinnode [33 .• 38]
[CO .. 5];
SCLRO;
pinnode 39
C6;
node
/* EXTENSION TO 6-BIT COUNTER
1** Declarations and Intermediate Variable Definitions **1
field 6BIT
[CO .. 5] •CNT;
1* 6 BIT COUNTER
field COUNTER
- [6BIT,C6];
1* FULL 7-BIT COUNTER
1** Logic Equations **1
REFREQ.s
REFREQ.r
RFC # RESET;
COUNTER:'d'76 & !RESET;
1* EXTEND BUILT-IN 6-BIT COUNTER BY ADDING A BURIED STATE REGISTER */
C6.s
C6.r
COUNTER:'d'63 & !RESET;
COUNTER:'d'76 # RESET;
1* BUILT-IN COUNTER CONTROL */
SCLRO
= COUNTER:'d'76
1** End of file **1
3-116
# RESET;
*I
*/
PSG EX2;
Partno
TI0002;
08/26/87 ;
Date
02;
Rev
Designer Schiele/Woolhiser;
Texas InstrumentslPersonal CAD Systems;
Company
Assembly None;
Location None;
Name
1***************************************************** *********************/
1* Refresh Timer
*1
1*
1* CUPL simulation file for example 2 from "A Designer's Guide to the
1* PSG507 n • This simulation file uses the $REPEAT directive to generate
1* many of the test vectors in the counter sequence.
*1
*1
*1
*1
1***************************************************** *********************/
1* Allowable Target Device Types:
TI PSG507
*1
1***************************************************** *********************/
ORDER:' PSG_CLK,%6,RESET,%4,RFC,%4,C6,%5,REFREQ;
BASE: DECIMAL;
VECTORS:
$msg" ";
$msg" NORMAL REFRESH CYCLE WITH REFRESH COMPLETE SIGNAL";
$msg" ";
-------INPUTS-------- -OUTPUT-wi
$msg"
PSG CLK RESET RFC C6
REFREQ" ;
$msg"
$msg"
---=---------------------------------"; I*COUNT*I
1
C
X
L
H
1* 0 */
X
L
H
0
C
1* 1 */
$repeat 74;
0
X
1*2-75 */
C
* *
$msg "end repeat";
H
H
C
0
0
1* 76 *1
L
L
0
0
C
1* 0 *1
C
0
0
L
L
1* 1 *1
L
C
0
0
L
1* 2 *1
1
H
C
0
L
1* 3 *1
L
H
C
0
0
1* 4 *1
$msg" ";
$msg" CHECK RESET FUNCTION AFTER REFREQ=L ";
$msg" "i
$msg"
-------INPUTS-------- -OUTPUT-a ;
REFREQ ";
PSG CLK RESET RFC C6
$msg"
$msg"
---=---------------------------------";
L
1
H
C
X
X
L
H
C
0
$repeat 74;
0
X
C
*
*
$msg "end repeat";
H
0
H
C
0
L
L
0
0
C
$repeat 29;
0
0
C
* *
$msg "end repeat";
0
L
L
C
0
L
H
1
0
C
I*COUNT*I
1* 0 *1
1* 1 *1
1*2-75 *1
1* 76 *1
1* 0 *1
1*1-30 *1
1* 31 *1
1* 0 *1
3-117
NaBie
Partno
·Date
Rev
Designer
Company
Assembly
Location
PSG Ex3;
TI0003;
08/26/87;
02;
Schiele/Woolhiser;
Texas Instruments/Personnal CAD Systems;
None;
None;
/**************************************************************************/
1*
1* Dynamic Memory Timing Controller
1*
1* This is the third example from "A Designer's Guide to the PSG507", by
1* R. Breuninger. In this example a dynamic memory timing controller,
/* which generates the control signals (ROY, MC1, RFC, RAS, CAS, MSEL)
*1
*1
*1
*1
*1
*1
1* necessary for accessing and refreshing dynamic memory, is implemented */
1* for the TI PSG507 using CUPL.
*/
/**************************************************************************/
/* Allowable Target Device Types: TI PSG507
*1
1***************************************************** *********************/
1** Inputs **1
PIN
PIN
PIN
PIN
PIN
REF CLK;
RESET;
ALE;
MIO;
REFREQ;
1
2
3
4
5
1** Outputs **/
PIN
PIN
PIN
PIN
PIN
PIN
8
9
10
11
13
14
=
=
=
=
=
ROY;
MC1;
RFC;
RAS;
MSEL;
CAS;
1** Node Declarations **1
[CO .. 4];
pinnode [33 •• 37]
SCLRO;
pinnode 39
SCLR1;
pinnode 40
CNTHOLDO;
pinnode 41
CNTHOL01;
pinnode 42
[PO .• 1];
node
node
BROY;
1** Declarations
field COUNTER
field STATE
$define STO
$define ST1
$define ST2
3-118
1* OSCILLATOR
*/
/* RESET - INITIALIZE
/* ADDRESS LATCH ENABLE
/* MEMORY I/O
1* REFRESH REQUEST
*1
*1
/* READY
/* MODE CONTROL
1* REFRESH COMPLETE
1* ROW ADDRESS STROBE
1* MULTIPLEXER SELECT
1* COLUMN ADDRESS STROBE
*1
*1
*1
*1
*1
1*
1*
1*
1*
1*
1*
1*
*1
*1
*1
*1
*1
*1
*1
BUILT-IN COUNTER
COUNTER HOLD non-registered
COUNTER HOLD registered
COUNTER HOLD non-refistered
COUNTER HOLD registered
BURIED STATE REGISTERS
BURIED READY SIGNAL
and Intermediate Variable Definitions **1
[CO •• 4].CNT;
[P1 .. 0];
'b'OO
'b'Ol
'b'10
*/
*/
*/
sequence STATE (
present STO:
/* INITIALIZE AND HOLD */
i f (RESET)
i f (ALE & MIO & REFREQ & !RESET)
if(!REFREQ & !RESET)
default
next
next
next
next
STO
STI
ST2
STO
present STl:
/* ACCESS CYCLE */
i f (RESET)
if (COUNTER:'d'O) &
if(COUNTER:'d'l) &
i f (COUNTER: 'd' 2) &
if (COUNTER:'d'9) &
default
next
next
next
next
next
next
STO;
STI out !RAS;
STI out MSEL;
STI out !CAS;
STO out [RAS,IMSEL,CAS];
STl;
!RESET
!RESET
I RESET
I RESET
present ST2:
/* REFRESH/ACCESS GRANT CYCLE */
i f (RESET)
next STO;
if (COUNTER:'d'O) & IRESET
next ST2 out IMCl;
if (COUNTER:'d'1) & IRESET
next ST2 out [RFC, !RAS];
if(COUNTER:'d'3) & IRESET
next ST2 out MCl;
if(COUNTER:'d'S) & !RESET
next ST2 out !RFC;
if(COUNTER:'d'6) & lRESET
next ST2 out RAS;
if (COUNTER:'d'9) & BROY
next STO;
if (COUNTER:'d' 10) & I RESET
next ST2 out lRAS;
if (COUNTER:'d'll) & I RESET
next ST2 out [BROY,MSEL] ;
if(COUNTER:'d'12) & !RESET
next ST2 out [ROY, !CAS];
if (COUNTER:'d'19)
next STO out [RAS,IMSEL,CAS];
default
next ST2; }
append BROY.r
append ROY.r
=
=
STATE:ST2
STATE:ST2
&
&
ALE
ALE
&
&
MIO
MIO
&
&
I RESET;
I RESET;
1* BUILT-IN COUNTER CONTROL EQUATIONS, WRITTEN *1
/* OUTSIDE THE STATE MACHINE
SCLRO
= RESET
t STATE:STI
t STATE:ST2
t STATE:ST2
CNTHOLDl. s
= RESET
t STATE:STI
f STATE:ST2
f STATE:ST2
CNTHOLDl.r
STATE:STO
*I
FOR CLARITY.
1* Clear counter on RESET *1
1* and transitions to STO.*I
& COUNTER:'d'9
& COUNTER:'d'9 & BROY
& COUNTER:'d'19;
1* Set count hold while
1* clearing the counter.
& COUNTER:'d'9
& COUNTER:'d'9 & BROY
& COUNTER:'d'19;
& ALE & MIO
& REFREQ & I RESET
1* Reset count hold
f STATE:STO & lREFREQ & lRESET;I* on transition to STl,2
APPEND BROY.s
APPEND ROY.s
APPEND Mel.s
I~*
=
=
=
RESET
RESET
RESET
APPEND RAS.s
APPEND CAS.s
APPEND PO. r
=
=
=
RESET
RESET
RESET
APPEND Pl.r
APPEND MSEL.r
APPEND RiC.r
=
*1
*1
*1
*1
RESET;
= RESET;
= RESET;
End of file **1
3-119
Name
Partno
Date
Rev
Designer
COIIIpany
Assembly
Location
PSG EX3;
TI0003;
08/26/87;
02;
Schiele/Woolhiser;
Texas Instruments/Personnal CAD Systems;
None;
None;
/**************************************************************************/
1*
*1
/* Dynamic Memory Timing Controller
*/
/*
*/
1* CUPL simulation file for Example 3 from "A Designer's Guide to the
*/
1* PSG507".
*/
1***************************************************** *********************/
/* Allowable Target Device Types: TI PSG507
*/
1***************************************************** *********************/
ORDER:
REF_CLK,%4,RESET,%4,ALE,%3,MIO,%4,REFREQ,%9,RDY,%3,
MC1,%3,RFC,%3,RAS,%3,MSEL,%4,CAS,%3,STATE;
BASE: DECIMAL;
VECTORS:
$msg"
";
$msg"
";
$msg"ACCESS TIMING CYCLE ";
$msg"
";
$msg"
------------ INPUT
------------ OUTPUT ----------- "
$msg"
CLK RESET ALE MIO REFREQ
RDY Mel RFC RAS MSEL CAS STATE
$msg"
-----------------------------------------------------------/*RESET*/ C
1
X X
X
H
H
L H L
H
"0"
H
1
L H L
H
C
0
0 1
H
"0"
L H L
C
0
1
1
1
H
H
H
"1"
X
H
L L L
0
X
X
H
H
"1"
C
L L H
H
"1"
X
X
H
H
C
0
X
X
X
X
H
H L L H
L "1"
C
0
X
X
L L H
H
H
0
X
L "1"
C
X
L "1"
0
X
X
H
H
L L H
C
H
X
X
X
H H L L
L
"1"
C
0
L "1"
0
X
X
X
H
H
L L H
C
X
H
H L L H
L "1"
C
0
X X
L "1"
X
0
X
X
H H L L H
C
X
H
H L H L
H
0
X
X
C
"0"
1
H
H
L H L
H
"0"
C
0
0
0
$msg"
";
$msg"
";
$msg"REFRESH WITH ACCESS FOLLOWING ";
$msg"
";
$msg"
------------ INPUT ---------------- OUTPUT ----------- "
RDY Mel RFC RAS MSEL CAS STATE
CLK RESET ALE MIO REFREQ
$msg"
$msg"
-----------------------------------------------------------H
H
L H L
H
1
it
X
X
/*RESET*/ C
"0"
H
H H L H L
0
X
X
0
C
"2"
L
H
X
H
L L H
0
0
0
C
"2"
H "2"
0
X
H L H L L
C
0
0
H "2"
X
H
L H L L
0
0
0
C
H
X
H H H L L
"2"
0
C
0
0
3-120
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
"2"
"2"
"2"
"2"
"2"
"2"
"2"
"2"
"2"
"2"
"2"
"2"
"2"
"2"
"2"
"0"
$msg"
";
$msg"
";
$msg" REFRESH WITHOUT ACCESS FOLLOWING ";
$msg"
";
$msg n
------------ OUTPUT ----------- "
------------ INPUT
$msg n
CLK RESET ALE MIO REFREQ
RDY MCl RFC RAS MSEL CAS STATE
$msgn
-----------------------------------------------------------non
1
X
X
X
H
H
L
H
L
H
/*RESET*/ C
"2n
0
X
X
0
H
H
L
H
L
H
C
"2n
X
H
L
L
H
L
H
C
0
0
0
X
H
L
H
L
L
H
"2"
0
0
C
0
n2 n
X
H
L
H
L
L
H
C
0
0
0
"2n
X
H
H
H
L
L
H
0
0
C
0
"2n
X
H
L
H
C
0
0
1
H
H
L
1
X
H
H
L
L
L
H
"2"
C
0
0
H
0
1
0
X
H
H
L
H
L
"2"
C
X
H
H
L
H
L
H
"2"
C
0
1
0
n2"
H
L
H
0
1
0
X
H
H
L
C
C
0
1
0
X
H
H
L
H
L
H
"0"
$msg"
";
$msg"
";
$msg" RESET DURING REFRESH";
$msg"
";
$msg"
------------ INPUT
------------ OUTPUT ----------- "
RDY Mel RFC RAS MSEL CAS STATE
CLK RESET ALE MIO REFREQ
$msg"
$msg"
-----------------------------------~-----------------------/*RESET*/
C
C
C
C
C
C
1
0
0
0
0
1
X
X
X
X
X
0
0
0
0
0
X
X
X
X
X
X
0
0
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
H
H
L
H
H
H
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
"0·
"2"
"2"
"2"
"2"
"0"
3-121
3-122
Appendix C. PSG507 Fuse Numbers
111
10
11
"14
121~
M
~
....
000
N,
~;;;
M,
~<-
~~
~~
I
I
13
I
" ",,17
""
I
16
"'
"'
11210E
0
I
I
"2G
II~
"
co
e,
e2
e3
e4
es
I
SCLRO
'-' f-+
CNrIHCOO
,
,~
i
:
~
'-'
>-+=
"
'-'
>-+
"
f-I>
"
!:: f-I>
I
!::
,
f--{'
P3
,.
;::: f--{'
"
;::: f--{'
P6
!:::
f--{'
=~~ao
e n62
';:::~~a,
I
I
I'
II
I
,
~"""
I,
;:::~
i
~~a3
I
I
,
!
II
I
I
I
I
II
I
I
~G~a4
~!=}:
I'
~""
Hi'
'
I
~~"'''
;:::f'{"
IT
,
0
0
.
N
~~
~s
I
I
.. .
.oo
as
. ~~ [lJ~~'"''
I
I Ii
.~H"
II
'"~
I
3-123
•
3-124
System Solutions for
Static Column Decode
Robert K. Breuninger, Loren Schiele,
and Joshua K. Peprah
~
TEXAS
INSTRUMENTS
3-125
...
IMPORTANT NOTICE
Texas Instruments (Til reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with Tl's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
such testing necessary to support this warranty. Unless mandated
by government requirements, specific testing of all parameters of each
device is not necessarily performed.
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.
Copyright
3-126
©
1987, Texas Instruments Incorporated
Contents
Title
INTRODUCTION. . . .. . .. . . . . . . . . .. . .. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
STATIC COLUMN DECODE...................................................................
TYPICAL MEMORY CONTROLLER........... .................................................
TIMING CONTROLLER DETAILS. . . .. . . .. . . . . . . .. . . .. . . . . . . . . . . . . . . . .. . . . . . . .. . .. .. . . . . . . . . . . .
NORMAL ACCESS SEQUENCE............... ........................................ .........
HIGH-SPEED ACCESS SEQUENCE.......................................... ...................
EXTENDED ACCESS SEQUENCE............. ........ ................................ .........
NORMAL/EXTENDED REFRESH SEQUENCES..................................................
SOFTWARE SUPPORT.......................................................................
SUMMARy ................................................................................. .
Page
3-129
3-129
3-131
3-131
3-133
3-133
3-134
3-134
3-138
3-138
Appendixes
A
B
ABEL'· Files. . . . . .. . . . . . . . .. ... . . . . . . . .. .. . . . . . . . . . . . . . . . . . . .. . . . . . . .. . .. . ... . . . . . . . .. .. . .
CUPL'" Files........................................ ......................... .. ...........
3-139
3-145
ABEL is a trademark of DATA 110
CUPL is a trademark of Personal CAD Systems, Inc.
3-127
List of lllustrations
Figure
Title
Page
1
2
3
4
5
6
7
8
9
Static Column Decode Mode Read Cycle Timing.. . ... . .. . .. . ..... .... . .. .. . . . . . .. .. .... . . . .
68020/6301 Static Column Memory Controller. . ... . .. . .. . ... . . . . . ... . . .. .. .. . . . . . .. . ... . .. .
ALS6310 Static Column/Page Mode Access Detector ........................................
Timing Controller Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Access Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-Speed Access Cycle ...............................................................
Extended Access Cycle .................................................................
Normal Refresh/Access Grant Cycle ......................................................
Extended Refresh Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-129
3-130
3-131
3-132
3-133
3-134
3-135
3-136
3"-137
3-128
INTRODUCTION
The ncw 32-bit microprocessors are capable of addressing
4G bytes of physical memory and typically feature clock
frequencies greater than 16 Mhz. However, clock speed
alone docs not guarantee increased system perfonnance; if
the processor must wait Il)r data, then memory bandwidth
will be the limiting factor.
This situation exists between today's microprocessors
and the access times of affordable DRAMs. One solution to
optimizing system pert()rmance is to mix and match memory,
using lower cost dynamic RAM in conjunction with fast,
more expensive static RAM caches. However, this approach
is only attractive to high end systems where cost and board
space is a less signitlcant factor.
Another approach to improving system performance
is to utilize the new accessing modes available on certain
I meg DRAMs, such as static column decode. This method
docs not improve system performance as much as caches,
but it docs involve less hardware, resulting in lower system
cost. This approach can also be used in systems already using
caches, further improving system performance.
This application note describes the theory of using static
column decode and also describes how it might be
implemented in a typical system. In addition, it highlights
three new products from Texas Instruments. The
SN74ALS6300 "Selectable Refresh Timer", the
SN74ALS6310 "Static Column Access Detector", and the
TIBPSG507 "Programmable Sequence Generator".
STATIC COLUMN DECODE
The TMS4C 1027 is a 1.048,576-bit X I dynamic
RAM featuring static column decode. Static column decode
allows high-speed read and write operations by reducing the
number of required signal setup, hold, and transition timings.
This is achieved by first strobing the row and column
addresses in the normal manner by taking RAS and CAS low.
If RAS and CAS are kept low, new data can be accessed
by simply changing the column addresses, assuming the new
address is in the same row. If the new address is not in the
same row, then a normal access cycle must be performed.
Figure I is a timing diagram taken from the
TMS4C I 027 datasheet showing static column decode mode
read cycle timing.
If the assumption is made that the majority of memory
references tend to be sequential, which is a similar
assumption made when using caches, then it is logical to
assume that a large percentage of memory accesses will be
within the same row. The trick is how to implement a timing
controller which will take full advantage of the static column
mode of operation.
~
\+-tw(RH)
ItoI_r-------------tw(RL)P-------------+t~1 I
RAS
~j
!{
_
VIH
I
II
VIL
Y:"'---I
I
I ~I- - - - - - - - - - - - - - - - - - - - - - - - - - -
~
I
J+-tt
I_
.1
Ii
~
I I
td(RLCL)rd
: I
j,J.:",,:---VIH
I I
I I4---th(RLCAI~
~
tsu(RA)~
I4l-
I
I I I
I
t+-th(RA)
I
i+--tc(rd)SC~
I
I
III
I I
VIL
j+-th(RHCA)
I I
I
~
I
I
I+--tsu(CAR)-+i
jrl_ _ _",,1
I I
II
COLUMN
AO·A9
I
I I
!+-+i-tdIRLCA)
I I
j+-tsu(RLrd)
I I
I
I I
1
I I
I I
I
I
I
I
i+--ta(R)--+i
I
I \+-taICA)-+j
th(CAQ)~
I
I
rc:-:-:-::::-:L
1
Q-------{
Figure l. Static Column Decode Mode Read Cycle Timing
3-129
Cf
~
Col
o
DRAM
CONTROLLER
74ALS6301
v~
lE
DYNAMIC RAM
00
\
0
0
TIMER
~O
REFRESH
RATE
o t---
TIMING
CONTROllER
TIBPSG507
REFRESH
SO-S3
09
t---
CASO
.....
ClK
RFC
'"-
SYSClK
ClK
OSC
101M
101M IA2Z
~
DSACK
R/W
Riw
AS
AS
STATIC COLUMN
DETECT
SN74AlS63l0
' - P.ClK
\
-----I
,-----t
I----t
f----.
SYS RST
Al0-Al9
W
r-
~ RST
~
I---t
I----t
f
MSEl
\
CASi
MCl
r----t
I- ~
CASl
cs
CASl
.....-
A20
AZl
00
0
W
I I I 1
wI--
7
I-f--CAS2 1-1--
0
0
0
A9
0
0
0
BANK 2
1MEG X 32 BITS
132) TMS4Cl027
l
,
W
I I I I
\
AO
~
0
0
0
AO
0
0
0
BANK 3
1MEG X 32 BITS
132) TMS4Cl027
A9
Al9
SElO
RAS3
RAS3
SEL'
CAS3
CAS3
W
00_. e031
Figure 2. 68020 Static Column Memory Controller
I
A9
CAS2
~
BO
AO
RAS2
RAS2
I
1
BANK 1
1MEG X 32 BITS
132) TMS4Cl027
A9
RASl
liASl l-
AO
r
0
0
0
t--
MCO
OE
AO
Bl
ROW
Al0-Al9
COLUMN
AO-A9
J
I I I 1
RASI
~
HSA
I
BANKO
1 MEG X 32 BITS
132) TMS4Cl 027
A9
RASO
SELECT
SYS ClK
IOSC/2)
0
0
0
RASO ~
CASO
REFREO
.,
AO
QO •• _031
J
TYPICAL MEMORY CONTROLLER
Figure 2 shows a block diagram of a memory system
utilizing static column decode. The ALS63 10 is a new circuit
offered by Texas Instruments which detects if the present
row being accessed is the same as last row accessed. This
is the fundamental requirement for implementing static
column decode. Note that the row addresses from the 68020
are used as the most significant bits (A IO-A 19) and the
column addresses are used as the least significant bits
(AO-A9). Figure 3 shows a block diagram of the ALS6310.
In circuit operation, when address strobe (AS) from
the 68020 is taken low, the present row (AIO-AI9) and bank
address (BO, B I) is clocked into the first register of the
ALS631O. The previous bank and row address, stored in the
first register, is clocked into the second register at the same
time. The two addresses are then compared to see if they
are equal. If they are equal, the high speed access output
(HSA) will be logically low. If not, HSA will be high.
The function of the PSGS07 is to generate the required
memory timing control signals (RAS, CAS, etc.) for the
ALS630 I dynamic memory controller. The ALS630 I is
responsible for multiplexing row and column addresses into
DRAM. The ALS6301 is also capable of driving 4 banks
of 1M-byte memory.
Supporting the PSG507 is the ALS6300 refresh timer.
This device is responsible for generating a refresh request
signal (REFREQ) every IS.S flS. The input select lines are
hardwired to match the microprocessor clock frequency. The
refresh complete input (RFC), resets the REFREQ signal
after the timing controller completes the refresh cycle.
TIMING CONTROLLER DETAILS
Figure 4 shows a typical flow chart for implementing
static column decode. As stated before, the PSGS07 is
responsible for implementing the flow chart shown in
Figure 4. A breakdown of this flow chart reveals 9 states
(STO-ST8), associated with S different sequences. States STO,
STI, ST3. and ST4 are holding and transition states, leading
into the various sequences. The five possible sequences are
listed below.
ST2 Normal Access Sequence
STS Extended Access Sequence
ST6 High-Speed Access Sequence
ST7 Normal Refresh Sequence
ST8 Extended Refresh Sequence
Notice that the HSA signal from the ALS6310 decides
if the timing controller will execute STS, the Extended Access
Sequence. or ST6, the High-Speed Access Sequence. A brief
description of each sequence follows.
ClKEN----_.---------------------------------,
ClK--.-~----------------------------,
PRESENT ADDRESS
REGISTER
PREVIOUS ADDRESS
10
AO-A9
BO-B3
Figure 3. ALS6310 Static Column Page Mode Access Detector
3-131
NO
Fi~ure
3-132
4.
Til11in~
Controller Flowchart
NORMAL ACCESS SEQUENCE
HIGH-SPEED ACCESS SEQUENCE
The normal access sequence is shown in Figure 5. This
sequence begins hy executing a normal RAS/CAS cycle.
Notice that a wait state of one clock cycle is needed to
guarantee that data is valid tl)r the 68020. This is the problem
mentioned in the introduction: if all access cycles had to be
performed in this manner, then the processor would face a
wait state every access cycle. As will be shown later, this
wait state can be eliminated if the next address is from the
For a high-speed access sequence to be executed, two
conditions must be met. The RAS and CAS inputs must
already be low. and secondly, the static column access
detector must be indicating the present row is the same as
the last row (HSA = L). The bank addresses must also be
unchanged as detected by the ALS631O.
Figure 6 shows the timing diagram for the high-speed
access sequence. Notice that no wait states are required. If
the assumption is made that the majority of memory
references are sequential, then this sequence will be the one
typically used. In other words, this sequence is similar to
accessing data from a static RAM, or just like taking data
from cache.
same row.
Notice also, at the end of this sequence, the RAS and
CAS output signals are left active low. Here we are making
the assumption that the next access cycle will be a high-speed
access. We will not know if this assumption is true until the
next address is presented hy the 68020. At that time. the
ALS63 10 will signal the timing controller if it can execute
a high-speed access.
ST2
CNT3
ST2
CNT4
53
SW
r-~--~L-
54
____________________
ADX \SSSSSSSSSSX
ST3
CNTO
so
55
~
__
51
~-------'L
xSSS\SSSSS
VALID PROCESSOR ADDRESS
R/W \\\\\\\\\\\lC
RASI
ST2
CNT5
"")(ssssssS\\
VALID R W siGNAL
----------------------------~----------------------------~-------------------------
MSEL ______________________~-----r------------------:_-------------------
CAS I ----------------------------T---------------L-____________~------------------------MAOR SSSSSSSSSSSSSSSSX
00-031
ROW ADDRESS
X
COLUMN ADDRESS
I
I
I
:
:
I
_________________________________________+I__~I.:=====~.I~T~A:I~C~I:1~::~[ffi~mur::::::::::::
:
VALID READ DATA
I4----TA
ICAI~
DSACK--------------------------------------------L-____________________
~r_---------------
W------------------------------------------~~~~~~------------
Figure 5. Normal Access Cycle
3-133
5T4
CNTO
5T3
CNTO
5T4
CNT1
5T6
CNT2
5T6
CNT3
5T6
CNT4
5T3
CNTO
05C
I
I
51
52 I
53
54
55
50
5Y5ClK----Jr----~~L_~____S_~~I~~__~__~~-=~--1___~__Jr--~--~
50
51
__~__~r
A5~r----------~L___~______________~_____l------------~L
ADX \\ \ \ \ \ \ \ \ \ \ \X'-_________...:V.,:A"'LI:::.D:.,;PR..:O",C:=;ES",S:.:;:O;;.R.,:A;::DDe;R:;;E::;SS:-,-_ _ _ _ _ _ _-'X\ \
\\\\\\\
RAID--------------------------L--------------M5El-------------------------~---------------
CA51-------------------------~-----------------
MADR \ \ \ \ \ \ \ \ \\ \ \ \ \ \\ \
xssss:
X'-__________....;C::.::O::::lU:::M:::N=AD::.::D::;R:=;ES:.::S~_ _ _ _ _ _ _ _ _ _
I
I+----TA
00031
ICI~
~~~~~~~~~~~~~~~~I_______~~~I~~~~_ _- - - - - - - - -
\\\\\\\\\\\\\\\\\\\\\\\\\\X
VALID MEMORY DATA
s_----------
D 5 A C K - - - - - - - - - - - - - - - - l L_ _ _ _ _ _ _ _ _ _ _ _ _ _
w---------------------------IC~~~-----------
Figure 6. High-Speed Access Cycle
EXTENDED ACCESS SEQUENCE
NORMAL/EXTENDED REFRESH SEQUENCES
The extended access sequence is executed if the
ALS63 10 detects a difference between the present, and last
row addresses .. This cycle is called extended because RAS
and CAS are presently low and both must be brought high to
strobe in the new row and column addresses. The precharge
time of the DRAM has to be met before taking RAS and CAS
low. From the timing diagram in Figure 7, it can be seen
that wait states of three clock cycles are generated when
executing this timing sequence.
In systems where sequential data is not the general rule,
it would be more efficient to execute only normal access
sequences, since this generates fewer wait states. The system
designer must understand what type of memory accesses will
be used. For example, the designer may want only to enter
the high-speed access portion of the flow chart when the
system is performing DMA access cycles.
Figures 8 and 9 show the timing diagrams for the
normal and extended refresh sequences. The refresh sequence
selected is a function of the present condition of RAS and
CAS. IfRAS and CAS are presently low, an extended refresh
cycle is performed. If RAS and CAS are presently high, a
normal refresh cycle is executed. At the end of each refresh
sequence. the controller checks to see if an access request
has been generated. If there has been an access request, the
controller will perform an access grant sequence at the end
of the refresh cycle before returning to normal process flow.
Referring back to Figure I, there is a maximum time
that RAS and CAS can be held low, tw(RL)P. For the
TMS4CI027, tw(RL)P must not exceed 100 JJ.s. Since our
refresh timer forces a refresh cycle every 15.5 JJ.S, tw(RL)P
cannot be violated. If the designer chooses to use a different
refresh scheme, then tw(RL)P must be considered.
3-134
ST4
CNTO
ST3
CNTO
ST4
CNT1
ST5
CNT2
ST5
CNT4
ST5
CNT3
ST5
CNT5
ST5
CNT6
ST5
CNT7
ST5
CNT8
ST5
CNT9
ST3
CNTO
ST5
CNT10
OSC
1
SYS ClK
--.J
SO
S1
S2 :
SW
SW
SW
SW
SW
SW
S3
S4
S5
r
r
AS-----I
ADX
SSSSSSSSSSSX
HSA___
XS
VALID PROCESSOR ADDRESS
_
~
I
I
I
R/W
SSSSSSSSSSSSlC - - - - - - - - - - - - - - - - - -
-VAUDiiTWDATA -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
_1- -
-
::xs
I
I
I
~
RASI ____________________________
MSEl
CASI ______________________________-"
MADR \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
\JC
COL
X
ROW ADDRESS
X
COL ADDRESS
I
00-031 \ \ \ \ \ \ \ \ \ \ \ \ \ \
I
I
1
14
I
\SS\\ \\ \\\S \\\ \\\ W
L
Figure 7. Extended Access Cycle
~
W
01
ICA1----':
r
,-------T
W
Cf
!
( V A L I D MEMORY DATA
* - TA
DSACK
lot TA ICI
I
I
Cf
w
~
O'l
STO
CNTO
ST7
CNTO
ST7
CNT1
ST7
CNT2
ST7
CNT3
ST7
CNT4
ST7
CNT5
ST7
CNT6
ST7
CNT7
ST7
CNT8
ST7
CNT9
ST7
CNT10
ST7
CNT11
ST7
CNT12
ST7
CNT13
ST7
CNT14
ST3
CNTO
asc
S1
S2
SW
SW
SW
SW
SW
SW
SW
SW
SW
S3
S5
SO
SYS ClK
AS
REFREO
r-
-.I
~:L~
______________________________________Jr--------t-------------------------------------------------t----------
RFC
-L-I-----------------------------------------------t
AGREo----------lL____________________________________________
ADX
S\ \\ \ \\X
XSS
VALID PROCESSOR ADDRESS
j
I
HSA \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
DDNT CARE
\\ \\\\ \\\\ \ \ \\\ \\ \ \\ \ \\\ \\ \\\\\\ \ \ \ \\\\
I
R/W \ \\\ \ \\ \
lC - - - - - - - - - - - - - - - - -
VAliD RiW DinA - -
-
- -
- -
-
- -
-
- - - - -
- - - L -
:-xs:s
I
-.I
M C 1 - - - - - - - - - - - - ' L____________________________
RASI----------------~
MADR \ \'\ \ \ \ \ \ \ \ \ \ \ \ \ \ \X
___________________F------------------L___________________~-----ROW REFRESH ADDRESS
X
X
ROW ADDRESS
COL ADDRESS
I
MSEl ____________________________________________________________________
I
I
~
CASI
00-031
------------------------------------------------------------------------------------------rl~~~~~
I+-TA
DSACK
W
(CI_
H~AUUATA
.,-----.--
Figure 8. Normal Refresh/Access Grant Cycle
ST3
CNTO
STS
CNTO
STS
CNT1
STS
CNT2
STS
CNT3
STl
STl
STl
STl
CNTO
CNTl
CNT2
CNT3
ST7
CNT4
ST7
CNTS
ST7
CNT6
STO
CNTO
STO
CNTO
OSC
r
SYSCLK-..J
AS-------T--------------------------------------------------------------~
REFREO
r_--t----------------
RFC------------------------------------------------------------~____________
AGREO-------------------------------------------------------------------------------------------i------------------ADX
STIR\:U\3U\3UTI'\S\ \\ \ \\ \ \ \ \\ \ \\\ \
DDNT CARE
\\ \\ \\ \\\ \ \\ \\ \ \ \ \\\ \\\ \ \\ \ \ \ \ \ \ \ \ \\ \\
HSA
lD. D DD. \\~\"_u\\\,,\\\\\ \,\\",\\\\\\\
DONT CARE
\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'\\'\\\.
R/W \ \ \Y\\'\\\\\\'\\TIu\\\\\\\\\'\\\ \ \ \ \ \ \
DONT CARE
\\\\\ \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
MCl
RASI ______________________
r-----------------------,~
MADR \ \ ' \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \~ll\'\\\\\\\\
____________________
\\\\\\X
~
ROW REFRESH ADDRESS
X\\\\\\\\\\\
MSEL
CASI __________________________
~
00-031 ' \ \' . \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \)
DSACK --------------------------------------------------------------_______________________________________________________
't'
W
-.J
W------------------------------------------------------------------------------------------Figure 9. Extended Refresh Cycle
SOFTWARE SUPPORT
SUMMARY
The PSG507 is supported by two software packages.
CUPL which was created by and is supported by Assisted
Technologies, a division of Personal CAD Systems Inc. and
ABEL which was created by and is supported by FutureNet
a division of Data liD Corp. Both of these software packages
have been used to reduce equations and to generate the
fusemap necessary to program the PSG507. Appendices A
and B show the ABEL'· and CUPL"' source files for the
described static column memory timing controller are
attached to assist the designer in programming the PSG507.
Since only 54% (43 out of 80) ofthe PG507's product
terms were used in this design, it will be easy to modify or
add to the sequences used to meet specific system
requirements. For detailed information on designing with the
PSG507 see "A Designer's Guide to the PSG507"
application report.
Static column decode offers the system designer a
method for improving system performance in applications
where the microprocessor can outperform conventional
DRAM access times. By utilizing the ALS6310 "Static
Column Access Detector", the ALS6300 "Refresh Timer",
and the TIBPSG507 "Programmable Sequence Generator"
a high performance memory timing controller can be easily
developed to take full advantage of static column decode.
3-138
APPENDIX A
module SCDECODE
title 'ABEL EXAMPLE FOR THE STATIC COLUMN DECODER
JOSH PEPRAH, TEXAS INSTRUMENTS, OCT 29, 1987'
DECODE device 'F507';
" Input pin assignments
pin 1;
OSC
RESET
pin 2;
pin 3;
A22
pin 4;
RW
REFREQ
pin 5;
pin 6;
AS
pin 7;
HSA
SYSCLK
pin 17;
" OSCILLATOR
" SYSTEM RESET - WHEN LOti
n IO/MmlRY - MEMORY ACCESS
" READ / WRITE ENABLE
n REFRESH REQUEST
n ADDR STROBE - ACCESS REO
n HIGH SPEED ACCESS
n SYSm! CLOCK - (OSC/2)
" Output pin and node assignments
RFC
pin 8; RFC r
WI
pin 9; WI r
MSEL
pin 10; MSEL-r
CASI
pin 11; CASI-r
Mel
pin 13; Mel
tI
pin 14; tI rDSACK
pin 15; DSACK r
r
node
node
node
node
node
47;
48;
49;
50;
51;
node 53;
" REFRESH COMPLETE
" ROti ADDRESS STROBE
" MULTIPLEXER SELECT
n COLUMN ADDRESS STROBE
" MODE CONTROL
node 52; "WRITE
" DATA STROBE ACKNOWLEDGE
" Internal counter bits & control, and state reg - node declarations
CO,C1,C2,C3,C4,C5 node 55,56,57,58,59,60;
SCLRO
node 25;
CNTHOLDO node 28;
CNTHOLD1 node 29; CNTHOLD1J node 30; " COUNT/HOLD CONTROL REGISTER
" Buried state registers - node declarations
PO
PI
P2
P3
AGREQ
node
node
node
node
node
31;
32;
33;
34;
35;
node
PO r
pCr
node
P2-r
node
P3-r
node
AGRE(r node 43;
39;
40;
41;
42;
" STATE REGISTER
" STATE REGISTER
n STATE REGISTER
" STATE REGISTER
" ACCESS GRANT REQUEST STATUS REGISTER
Set notation is used to represent control, buried state, and output
registers. This is done to sbDplify the equations. The following
n sets are in the form;
register name = [set input, reset input]. Note
" that the ouput register pin name specifies the set input.
n
n
RFC
WI
MSELCASIMel tI
DSACK
AGRE(
=
=
=
=
=
=
=
=
[RFC, RFC r];
[WI, WI r];
[MSEL, MSEL-r];
[CASI, CASI-r];
[Mel, Mel rl;
[tI, tI r];-
[DSACK, DSACK r];
[AGREQ, AGRE(r];
3-139
•
"
"
"
Intemediate declarations for simplification.
The sets ' high' and' low' are used to set or reset the SiR
registers. Example: RASI : = high & RESET; will cause pin 9
to go high on the next clock edge if input pin 6 is high.
high
low
COUNT
STATE
H,L,cU,X
= [1,
.. [0,
0);
1);
= [C3, C2, C1, CO);
= [P3, P2, P1, PO);
" STATE REGISTER SET DEFINED
= 1, 0, .C., .X.;
equations
enable RFC .. 1; "outputs always enabled, pin 17 is only an input
n
Initialization when RESET is low
[RASI,CASI,RFC,II,AGREQ,DSACK,MC1,SCLRO) := !RESET;
[MSELJ,PO_r,P1J,P2_r,P3J)
:= !RESET;
n
Counter controls defined
SCLRO
CNTHOLD1
.. !RESET
t [STATE ==2)
t (STATE-==4)
t (STATE-==5)
t (STATE-==6)
t (STATE-==7)
t (STATE-=7)
t (STAT(=8)
&
&
&
&
&
&
&
(COUNT==5)
(COUNT==O) & A22
(COUNT==10)
(COUNT==4)
(COUNT==6) & (A22 t AGREQ)
(COUNT==14)
(COUNT==3);
.= !RESET
t
t
t
t
t
t
(STATE ==2)
(STATE-=4)
(STATE-=5)
(STATE-=6)
(STATE- ==7)
(STATE-==7)
f (STAT(==8)
(COUNT=5)
(COUNT==O) & A22
(COUNT==10)
(COUNT==4)
, (COUNT=6) & (A22 t AGREQ)
& (COUNT==14)
& (COUNT==3);
&
&
&
&
CNTHOLD1 r := (STATE ==0) & !RErREQ & RESET
1 (STATE ==1) & !A22 & RESET
# (STATE-==3) & !REFREO , RESET
t (STAT(==3) & REFREQ & AS & SYSCLK & RESET;
n Execution of access and refresh sequences
state diagram STATE
State 0:
case
!RESET
REFREQ & (!AS t !SYSCLK)
REFREQ & AS & SYSCLK & RESET
!REFREQ & RESET
endcase;
3-140
n
n
NEXT
STATE
: 0;
: 0;
: 1;
: 7;
" NORMAL ACCESS CYCLE
State 1;
" NEXT
" STATE
case
(COUNT==O) & !A22
(COUNT==O) & A2 2
endcase;
; 2;
: 0;
State 2:
RAS I
MSELCASIDSACK-
:= (COUNT==O) & 1011 & RESET;
;= (COUNT==l) & high;
:= (COUNT=2) & low & RESET;
:= (COUNT==2) & 1011 & RESET;
II - := (COUNT==3) & low & RESET;
11- := (COUNT==5) & high;
DSACK := (COUNT==5) & high;
if (COUm==5) then 3 else 2;
"HOLDING STATE
State 3;
case
(!AS t !SYSCLK) & REFREQ & RESET
REFREQ & AS & SYSCLK & RESET
!REFREQ & RESET
endcase;
" NEXT
" STATE
: 3;
: 4;
: 8;
State 4:
CASI
RASI
MSEL
RASI
DSACK
MSEL
CASI-
:=
:=
;=
:=
:=
;=
;=
(COUNT==O)
(COUNT==O)
(COUNT==O)
(COUNT==l)
(COUNT==l)
(COUNT==l)
(COUNT==l)
high & A22;
high & A22;
1011 & A22;
& high & HSA;
low & !HSA;
low & HSA;
& high & HSA;
&
" NEXT
case
(COUNT==O)
(COUNT==O)
(COUNT==l)
(COUNT==l)
endcase;
&
&
&
&
A22
!A22
HSA
!HSA
& RESET
& RESET
& RESET
& RESET
;
:
:
;
" STATE
0;
4;
5;
6;
"EXTENDED ACCESS CYCLE
State 5;
RASI
MSELCAS(
DSACK
;=
;=
:=
;=
(COUNT==5) & low & RESET;
(COUNT==6) & high & RESET;
(COUNT==7) & 1011 & RESET;
(COUNT==7) & low & RESET;
II; = (COUNT==8) & 1011 & RESET;
11- ;= (COUNT==10) & high;
DSACK := {COUNT==10) & high;
inCOUNT==10) & RESET then 3 else 5;
3-141
"HIGH SPEED ACCESS
State 6:
II := (C00NT==2) & low & RESET;
11- := (COONT==4) & high;
DSACK := (C00NT==4) & high;
if- (C00NT==4) then 3 else 6;
"NORMAL REFRESH CYCLE
State 7:
AGREQ := AS
& low & RESET;
IICC := (COONT==O) & low & RESET;
RASC := (COuNT-I) & low & RESET;
RFC- := (COONT==3) & low & RESET;
RFC- := (COUNT=5) & high;
RASI- := (COUNT==5) & high;
IIC( := (COUNT=6) & high;
RASI := (COUNT==9) & low & RESET;
MSEL- := (COUNT=10) & high & RESET;
CASI- := (COUNT=l1) & low & RESET;
DSACK- := (COUNT==l1) & low & RESET;
11:= (COUNT==12) & low & RESET;
11- := (COUNT==14) & high;
DSACK := (COUNT=14) & high;
if (COUNT=6) & (A22 # AGREQ) then 0 else 7;
if (COUNT=14) then 3 else 7;
"EXTENDED REFRESH CYCLE
State 8:
RASI := (COONT==I) & high;
MSEL- := (COUNT==l) & low;
CASI- := (COUNT==l) & high;
if (COUNT==3) then 7 else 8;
test vectors ' NORMAL ACCESS CYCLE'
([OSC, RESET,A22, RII,REFREQ,AS, HSA, SYSCLK,COUNT]
[elk,
L , X , X, X
, X,
[elk,
H , X , X, H
, L,
[elk,
H , X , X, H
, H,
[elk,
H , L , X, X
, X,
[elk,
H , X , X, X
, X,
[elk,
H , X , X, X
, X,
[elk,
H , X , X, X
, X,
[elk,
8 , X , X, X
, X,
[clk,
8 , X , X, X
, X,
[elk,
H , X , X, X
, X,
-) [RFC, RASI,MSEL, CASI,MC1, !I, DSACK, STATE])
X, X, X ] -) [ H, H, L, H ,-H ,H,
X, X, 0 ] -> [ H, H, L, H, H ,H,
X, H, 0 ] -> [ H, H, L, H, H ,H,
X, X, 0 ] -> [ H, H, L, H, H ,H,
X, X, 0 ] -> [ H, L, L, H, H ,H,
X, X, 1 ] -) [ H, L, H, H, 8 ,8,
X, X, 2 ] -> [ H, L, H, L, H ,H,
X, X, 3 ] -> [ 8, L, H, L, H ,L,
X, X, 4 ] -> [ H, L, H, L, 8 ,L,
X, X, 5 ] -> [ H, L, 6, L, H ,8,
,
L
H
,
,
,
,
,
,
,
,
,
0
0
I
2
2
2
2
2
2
3
test vectors ' HOLDING STATE 4 !lU8 EXTENDED ACCESS REQUEST'
([OSC,RESET,A22,RII, REFREQ, AS, 8SA, SYSCLK, COUNT] -) [RFC, RASI,MSEL,CASI,MC1, II, DSACK, STATE ])
[elk,
H , H , X, H
, H, X, H, 0 ] -> [ 8, L, H, L,- 8 ,H, H
lelk,
8 , L , X, X
, X, X, X, 0 ] -) [ H, L, H, L, H ,H, H
[elk,
H , X , X, X
, X, H, X, 1 ] -> [ H, H, L, H, H ,H, H
,
,
,
4
4
5
3-142
H
H
H
H
H
H
L
L
];
];
];
];
];
];
];
];
];
1;
test vectors 'EXTENDED ACCESS'
([OSC, RESET,A22, RII, REFREQ, AS, HSA, SYSCLK, COUNT]
[elk,
, X,
H , X , X, X
[elk,
, X,
H , X , X, X
[clk,
, X,
H , X , X, X
[elk,
, X,
H , X , X, X
[elk,
H , X , X, X
, X,
[elk,
, X,
H , X , X, X
[elk,
, X,
H , X , X, X
[elk,
, X,
H , X , X, X
[elk,
H , X , X, X
, X,
-) [RFC, RASI,MSEL,CASI,MCl, II,DSACK, STATEJ)
X , X , 2 ] -) [ H , H , L , H , H ,H,
X, X , 3 ] -) [ H , H , L , H , H ,H,
X , X , 4 ] -) [ H , H , L , H , H ,H,
X , X , 5 ] -) [ H , L , L , H , H ,H,
X , X , 6 ] -) [ H , L , H , H , H ,H,
X , X , 7 ] -) [ H , L , H , L , H ,H,
X, X , 8 ] -) [ H , L , H , L , H ,L,
X , X , 9 ] -) [ H , L , H , L , H ,L,
X , X , 10 ] -) [ H , L , H , L , H ,H,
test vectors 'HOLDING STATE 4 IIITH HIGH SPEED
([OSe, RESET, A22, RII, REFREQ,AS, HSA, SYSCLK, COUNT]
[elk,
, H,
H , H , X, H
[elk,
, X,
H , L , X, X
[elk,
, L , X, X
, X,
ACCESS REQUEST'
-) [RFC, RASI,MSEL, CASI,MCl, II,DSACK, STATEJ)
X , H , 0 ] -) [ H , L , H , L , H ,H, H
X , X , 0 ] -) [ H , L , H , L , H ,H, H
L , X , 1 ] -) [ H , L , H , L , H ,H, L
test vectors 'HIGH SPEED ACCESS'
([OSe,RESET,A22,RII, REFREQ,AS,HSA,SYSCLK,COUNT]
[elk,
H , X , X, X
, X,
[elk,
H , X , X, X
, X,
[elk,
, X,
H , X , X, X
-) [RFC, RASI,MSEL,CASI,MC1, II,DSACK,STATE ])
] -) [ H , L , H , L ,-H ,L, L
X, X ,
] -) [ H , L , H , L , H ,L, L
X, X ,
] -) [ H , L , H , L , H ,H, H
X, X ,
H
H
H
H
H
L
L
L
H
test vectors 'NON-MEMORY ACCESS FOLLOIIED BY REFRESH REQUEST'
([OSC, RESET, A22, RII, REFREQ,AS, HSA, SYSCLK,COUNT] -) [RFC, RASI,MSEL,CASI,MC1, II,DSACK, STATEJ)
[elk,
, H, X, H , 0 ] -) [ H , L , H , L , H ,H,
H , H , X, H
[elk,
H , H , X, X
, X, X , X , 0 ] -) [ H , H , L , H , H ,H,
[elk,
, L, X , X , 0 ] -) [ H , H , L , H , H ,H,
H , X , X, H
[elk,
, X, X, L , 0 ] -) [ H , H , L , H , H ,H,
H , X, X, H
[elk,
, X, X , X , 0 ] -) [ H , H , L , H , H ,H,
H , X , X, L
H
H
H
H
H
test vectors 'NORMAL REFRESH CYCLE'
([OSe,RESET,A22, RII, REFREQ, AS, HSA, SYSCLK,COUNT]
[elk,
H , X , X, X
, L,
[elk,
, L,
H , X , X, X
[elk,
H , X , X, X
, L,
[elk,
, L,
H , X , X, X
[elk,
H , X , X, X
, L,
[elk,
, L,
H , X , X, H
[elk,
, L,
H , X , X, X
H
H
H
H
H
H
H
-) [RFC,RASI,MSEL,CASI,MC1, II,DSACK, STATE])
X , X , 0 ] -) [ H , H , L , H ,-L ,H,
X, X ,
] -> [ H , L , L , H , L ,H,
X, X ,
] -> [ H , L , L , H , L ,H,
X, X ,
] -) [ L , L , L , H , L ,H,
] -> [ L , L , L , H , L ,H,
X, X ,
X, X ,
] -> [ H , H , L , H , L ,H,
X, X ,
] -> [ H , H , L , H , H ,H,
,
,
,
,
,
,
,
,
,
5
5
5
5
5
5
5
5
3
];
];
];
];
];
];
];
];
];
,
,
];
];
];
,
];
];
];
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
4
0
0
0
7
];
];
];
];
];
];
];
];
];
];
];
];
3-143
test vectors ' NORMAL REFRESH CYCLE FOLLOltED BY ACCESS GRANT REQUEST'
((OSC,RESET,A22,RII,REFREQ,AS,HSA,SYSCLK,COUNTI -> [RFC,RASI,MSEL,CASI,MCl,II,DSACK,STATE ))
[elk, H , X , X, L
, X, X, X, 0 I -> [ H ,
H, L, H, H ,H~ H
, L, X, X, 0 I -> [ H ,
H, L, H, L ,H, H
[elk, H , X , X, X
[elk, H , X , X, X
, L, X, X, 1 I -> [ H ,
L, L, H, L ,H, H
[elk, H , X , X, X
, H, X, X, 2 I -> [ H ,
L, L, H, L ,H, H
, H, X, X, 3 I -> [ L ,
L, L, H, L ,H, 8
[elk, H , X , X, X
[elk, H , X , X, X
, L, X, X, 4 I -> [ L ,
L, L, 8, L ,H, H
[elk, H , L , X, H
, L, X, X, 5 ) -> [ H ,
H, L, H, L ,8, H
[elk, H , L , X, X
, L, X, X, 6 ) -> [ H ,
H, L, H, H ,8, H
[elk, H , L , X, X
, L, X, X, 7 ) -> [ 8 ,
H, L, H, H ,H, 8
[elk, H , L , X, X
, L, X, X, 8 I -> [ H ,
H, L, H, H ,H, 8
[elk, H , L , X, X
, L, X, X, 9 I -> [ 8 ,
L, L, H, H , H, H
[elk, H , L , X, X
, L, X, X, 10 ) ~> [ H ,
L, H, H, H ,H, H
[elk, H , L , X, X
, L, X, X, 11 ) -> [ 8 ,
L, H, L, H ,H, L
[elk, H , L , X, X
, L, X, X, 12 I -> [ H ,
L, H, L, H ,L, L
[elk, H , L , X, X
, L, X, X, 13 ) -> [ 8 ,
L, H, L, H ,L, L
, L, X, X, 14 I -> [ H ,
L, H, L, H ,8, H
[elk, 8 , L , X, X
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
test vectors ' 80LDING STATE 3 WITH EXTENDED REFRESH REQUEST'
((OSC,RESET,A22,Rlf, REFREQ, AS, HSA, SYSCLK,COUNTI -> [RFC,RASI,MSEL,CASI,MCI,II,DSACK,STATE II
[elk,
H , X , X, 8
, X, X, L, 0 I -> [ 8, L, H, L,- H ,H, H
[elk,
H , X , X, H
, L, X, X, 0 I -> [ 8, L, H, L, 8 ,H, H
[elk,
H , X , X, L
, X, X, X, 0 I -> [ 8, L, H, L, H , H, 8
test vectors ' EXTENDED REFRESH CYCLE'
((OSC,RESET,A22,RII, REFREQ,AS, HSA, SYSCLK, COUNT)
[elk,
H , X , X, X
, X,
[elk,
H , X , X, X
, X,
[elk,
H , X , X, X
, X,
[elk,
H , X , X, X
, X,
end SCDECODE
3-144
-> [RFC, RASI,MSEL, CASI,MCl, II, DSACK, STATE II
X, X, 0 ) -> [ H, L, H, L ,-H ,H,
X, X, 1 I -> [ H, H, L, H, H ,H,
X,
X,
X, 2 I -> [ 8, 8, L,
X, 3 I -> [ H, H, L,
H
H
H, H ,H, H
H, H ,H, H
7
7
7
7
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
Ii
7
7
7
7
7
7
7
7
7
7
7
3
,
,
,
,
,
,
,
3
3
8
Ii
Ii
Ii
Ii
APPENDIX B
NAME
PAR TNO
OA TE
SCDECOOE:
T10004:
05/07/87 :
REV
01 :
DESIGNER 8reuninger/Peprah:
COMPANY
Texas Instruments:
ASSE~8L Y None;
lOCATION Dallas:
/*
I I . ' I • • • I f 1.1. I I I
/'
f"'"
I"
I'
*' f • • I t • • • • • • • I I • • • 1.1 • • • • • I •• I . I I I f • • I I "
' I I , t • • • • • f I I I I I 1/
Static Column Decode
'/
'/
/'
/'
/'
/'
/'
/'
This is an example of how the PSGI01 can be used to generate the
required memory timing control signals (RAS. CAS. HSEL etc! for static
column decode implementation using the ALS6JOI. ALS6JI0 and the ALS6JO
ALS6300. in a system environment.
/'
/'
'/
'/
'/
'/
'/
'/
'/
/ ' . 1 • • • 1. I • • ' • • • • t •• I . I I . I I I . I • • • • • • 1 • • • 1 I • • • • • • • • • • " . I i i I t ' 1 I I I 111,1' • • • • • • • • • • • • • 1 ' . ' /
"
I
j*' f
Allowable Target Device Types:
• • • • • • • • • • • • • • • • • • • • • • , 1'1 • • • • • • •
TEXAS INTSRUMENTS
PSGI07
* , •••••• IlIt • • • • • • 1 " " 1 "
'/
11 • • • ' •• 1 •• ' I • • • • f . " . I . 1 . 1 ,
/" Inputs "/
pi n
pi n
pi n
pi n
pi n
pi n
pi n 1
pi n 18
OSC
RESET
A1Z
RW
REfREQ
AS
HSA
SYSCLK
/'
/'
/'
/'
Osci Ilator
System Reset - when low
IO!!M - Memory access
Read / Write Enab Ie
/' Refresh Request
/' Addr Strobe - access request
/' High Speed Access
/' System Clock - (OSC/1)
'/
'/
'/
'/
'/
'/
'/
'/
RFC
RASI
HSEL
CAS I
HCI
/'
/'
/'
/'
/'
/'
/'
Refresh Comp I ete
Row Address Strobe
Hu I tip I exer Se I ect
Co I umn Address Strobe
Hode Contro I
Wr ite
Data Strobe Acknow I edge
'/
'/
'/
'/
/'
/'
/'
/'
/'
/'
Built-in .-Bit counter
Counter Cc I ear- non regi stered
Counter Hold - non registered
Counter Hold - registered
Buried State Registers
Access Grant Request
'/
'/
'/
'/
'/
'/
/" Outputs "/
pi n
pi n
pi n
pi n
pi n
pi n
pi n
8
9
10
II
13
14
15
DSACK
/" Node Declarations "/
pi nnode [33 •• 38J
[CO •• 5J
pi nnode 39
SClRO
pinnode 41
CNTHOlOO
pi nnode 42
CNTHOlD I
node
[P3 •• 0J
node
AGREQ
'/
'/
'/
3-145
j" Declarations and Intermediate Variable Definition "/
field COUNT
" [C5 .. 0J
field STATE
[PJ.,OJ
$define STO
'b'OOOO
$define 5TI
'b'OOOI
$define STI
'b'OOlO
$define ST3
'b'OOII
$define 514
'b'OIOO
$define 5TS
'b'OIOI
$define 5T6
'b'OIIO
$define Sll
'b'OIlI
$define 5T8
'b'IOOO
/' SU ILT -I N COUNTER CONTROL EQUAT IONS '/
SCLRO
CNTHOlD I, s
CNTHOLDl,r
3-146
" ! RESET
# STI & COUNT:'d'S
, ST4 & COUNT:'d'O
# ST5 & COUNT:'d'IO
# 5T6 & COUNT:'d'4
# 5ll & COUNT:'d'6 & IA1Z ! AGREQI
f Sll & COUNT:'d'14
# ST8 & COUNT:'d'3;
/' Clear counter when RESET is low
/' and during transitions at the end
/' the indicated states and counts,
/'
/'
I'
/'
/'
" ! RESET
# STI & CDUNT:'d'S
# 514 & CDUNT:'d'O
# 5TS ! COUNT:'d'IO
# ST6 ! COUNT:'d'4
# STJ ! COUNT:'d'6 & IA22 & AGREO)
t STJ & COUNT:'d'14
# ST8 & CDUNT:'d'l;
/'
/'
/'
/'
/'
/'
"STO
# STI
# STJ
# STJ
/'
/'
/'
/'
&
&
!
&
!
!REFREQ & RESET
!AZZ & RESET
!REFREQ & RESET
REFREQ & AS
SYSCLK & RESET,
'I
'/
'/
'/
'/
'/
'/
'/
/' Set count hold while clearing
/' the counters accordingly,
Reset
Reset
Reset
Reset
/" State ~achine Equations "/
sequence STATE [
present STO:
iflREFREQ & I !AS # !SYSCLK))
if(REFREQ & AS & SYSCLK & RESET)
ifl!REFREQ & RESET)
default
next
next
next
next
present ST!:
ifICOUNT:'d'O & !A22)
ifICOUNT:'d'O & Am
default
next STZ,
next STO,
next5TI,
present ST1:
/' NORML ACCESS CYCLE '/
ifICOUNT:'d'O) & RESET
if(COUNT:'d' I)
ifICOUNT:'d'Z) & RESET
ifICOUNT:'d'J) & RESET
ifICOUNT:'d'S)
defau I t
next
next
next
next
next
next
count
count
count
count
hold
hold
hold
hold
on
on
on
on
STO,
STI,
Sll;
5TO;
STI out
ST2 out
STI out
5T2 out
513 out
ST2,
!RA5I,
MSEL;
[!CASI, !DSACKJ;
!w;
[W, 05ACK J;
transition
transition
transition
transition
'I
'/
'/
'/
'/
'/
'/
'/
to
to
to
to
Sll
ST2
ST8
ST4
'I
'/
'I
'/
present STJ:
I' HOLDING STATE
'I
ifl!~S # !SYSCLKI & REFREQ & RfSET
iflREFREQ & ~S & 5YSCLK & RESET I
ifl!REFREQ & RESET I
default
next
next
next
next
STl
5T 4
ST8
STJ;
present S14:
ifICOUNT:'d'OI
ifICOUNT:'d'OI
ifICOUNT:'d'll
ifICOUNT:'d' II
default
next
next
next
next
next
STO out [R~SI,!MSEL,C~SI);
ST4;
ST5 out [R~SI,!MSEL,CASI);
516 out ! DSACK;
514;
next
next
next
next
next
next
ST5 out !R~SI;
5T5 out MSEL;
ST5 out [!C~SI,!DSACK);
ST5 out !W;
STJ out [W,OSACK);
ST5;
& An & RESET
& !m & RESET
& HSA & RESET
& !HS~ & RESET
present 5T5:
I' EXTENDED ACCESS CYCLE 'I
ifICOUNT:'d'51 & RESET
ifICOUNT:'d'61 & RESET
ifICOUNT:'d'11 & RESET
ifiCOUNT:'d'81 & RESET
ifICOUNT: 'd' 101 & RESET
defaul t
present ST6:
I' HIGH SPEED ACCESS
'/
ifICOUNT: 'd'ZI & RESET
if I COUN T: ' d' 41
def au I t
next ST6 out !w;
next STJ out [W,DSACK);
next ST6;
present ST1:
I' NORMAL REFRESH CYCLE' I
i f ~S
ifICOUNT:'d'DI & RESET
ifICOUNT:'d'll & RESET
ifiCOUNT:'d'31 & RESET
ifiCOUNT:'d'51
ifICOUNT:'d'6) & I~ZZ # AGREQ)
ifICOUNT:'d'6) & !~ZZ & !~GREQ
ifICOUNT:'d'91 & RESET
ifICOUNT: 'd' 101 & RESET
ifICOUNT:'d'lll & RESET
ifICOUNT:'d'IZI & RESET
if (COUNT:' d' 14)
default
next
next
next
next
next
next
next
next
next
next
next
next
next
ST7 out
ST7 out
ST1 out
ST1 out
ST7 out
STO out
ST1 out
ST1 out
ST1 out
ST1 out
ST7 out
STJ out
ST7;
! ~GREQ;
! MCU
!RASI;
!RFC;
[RFC,R~Si
1;
MC U
MC 1_;
!RASI;
MSEL;
[!C~SI,!DS~CK1;
!W;
[W,DS~CK1;
present ST8:
I' EXTENDED REFRESH CYCLE
•I
if (COUNT:' d' I )
if(COUNT: 'd'l)
default
APPEND
APPEND
APPEND
APPEND
APPEND
RASl.s
W.s
MCI_.s
PO_.r
Pl_.r
= !RESET; APPEND
= !RESET; APPEND
= !RESET APPEND
= !RESET APPEND
= !RESET
next ST8 out
next ST7;
next ST8; )
CASl.s
~GREQ.s
SCLRO
PI.r
= !RESET; ~PPEND
= !RESET; APPEND
!RESET; APPEND
!RESET; APPEND
[R~Sl,!MSEL,C~SI1;
RFC.s = !RESET;
DSACK.s = !RESET;
MSEL.r = !RESET;
P2.r
= !RESET;
3-147
HAKE
PARTNO
DATE
SCDECODE;
TlO004;
05/01/81 ;
~HIGNER ~~e&ninger/Peprah;
COHPANY Texas Instrullents;
ASSEHBL Y None;
LOCATION Dal las;
111111,., ••• ' II. II "'1'11-'11'" ••••••••• 111"'1'1'11 ••••• I ••••
"'II"
II II ' . I " l l l l l I l f " , I , ' "
""/*
'/
*/
CUPL simulation file for the Static Column Decode Application
*,
, ' •••• 1 .11 •• l l l f l f l l . I I •••••••••••• III •• '11"
/'
I
*,
/' Static Colulln Decode
Allowable Target Device Types:
1111'"
•••• ".1"
I.' If
f.,., '1IIf 11".1 •• l i l t 1.111/
'/
TEXAS INTSRUHENTS PSG501
j" •• IIIII." •• , ••••••••••••• f • • • • • • • • • • "1"'" 'I ".'1 , •• '1"" 'If"" ••••••••• ".11 •••• '111'/
ORDER: OSC. \4.RESET. \4.AZZ. \3. RW. ~3 .REFREQ. ~5 .AS. \2 .HSA. \5. SYSCLK. \3 .COUNT.
~Z. RFC. ~4.RASI. ~4. HSEL. ~4 .CASI. ~3 .KC 1_.12.W .13. DSACK. ~4. STATE;
BASE: DECIHAL;
VECTORS:
$msg'
';
$msg" ';
$msg'NORHAL ACCESS CYCLE";
$msg' ";
$msg"
------------------ INPUT ------------------ -------------- OUTPUT --------------- ';
$msg"
OSC. RESET .A2Z.RW .REFREQ.AS .HSA. SYSCLK .COUNT RFC.RAS I. HSEL .CASI. HC I, W. OSACK. STATE' ';
_________________ - ____________ • ____ • ________ - ________ • ______ . _ . _._ • • _._ ._____ _____ II.
,
$msg'
X
X
X
'X'
'0'
X
0
X
'0'
H
"0"
X
I
'0'
H
'I"
I
X
'0'
H
X
X
"2"
X
X
'0'
H
"2'
X
X
X
H
'I'
'2'
X
X
'2'
L
X
'Z'
'3'
X
X
X
L
"Z"
' 4'
X
X
"Z"
'5'
X
X
"3'
$msg' ';
$msg' ';
$msg'HOLDING STATE 4 WITH EXTENDED ACCESS REQUEST";
$msg' .;
$msg'
---------- -------- INPUT - ---- ---------- --- -- - ---- --- ------ OUTPUT -- --- -------- ';
$msg'
OSC.RESET. A22 .RW.REfREQ. AS.HSA .SYSCLK .COUNT RFC.RASI.HSEL .CASI •HC I.W, OSACK.STATE ";
_____________ __ ____ _______ _________ __ ____ __ ___ __ ____ _______ ____ ______________ _____ n;
$msg'
'0 '
X
"4"
'0'
X
X
'I'
"5'
'.'
3-148
$msg" ";
$msg" ';
$msg'EXTENDED ACCESS';
$msg" ';
$msg"
------------------ INPUT ------------------ ------------- OUTPUT ---------------- "
$msg"
OSC,RESET ,A22,RUEFREQ,AS,HSA,SYSCLK,COUNT RFC,RASI ,HSEL,CASI ,HCI ,W,DSACK,STATE '
$msg"
-- --------------- -- --- ---- ----------- ------ --- --- --- ---------- -- --------------- -- - ,
"5"
x X X ' 2'
"5"
X
X
X X
'3 '
H
'4 '
X
"5'
X
X
H
X
' 5'
H
'5"
X
X
'6'
X
X
H
"5'
X
'7'
X
X
H
"5'
X
'S'
X
X
H
'5"
'9'
X
X
H
"5'
X
X ' 10'
H
"3"
$msg' ";
$msg" ';
$msg"HOLD I NG STATE 4 WITH HIGH SPEED ACCESS REQUEST";
$msg" ";
$msg"
------------------ INPUT ---------'--------- -------------- OUTPUT --------------- "
$msg"
OSC,RESET, m, RW, REFREQ, AS,HSA, SYSCLK,COUNT RFC ,RAS I, MSEL ,CAS I, HC I, W, OSACK, STATE "
$msg"
, 0'
H "4"
X
'0 '
X
H "4"
X
'I'
L
"6"
$msgH .;
$msg" ";
$msg"HIGH SPEED ACCESS";
$msg" ";
$msg"
------------------ INPUT ------------------ -------------- OUTPUT --------------- ,
$msg"
OSC, RESET, A22 ,RW ,REFREQ, AS ,HSA, SYSCLK,COUNT RFC ,RAS I, MSEL, CASI ,HC I, W, DSACK, STATE "
- - -- - - - - - - -- - - - - - - - -- - - - - - - -- - - - --- -- - -- - - - - - - - -- -- - -- - - -- - - -- -- --- - -- - - - -- - "
$msg"
'6"
'2 '
'3'
"6"
'4 '
"3"
-
-- -- -
$msg" ";
$msg" ";
$msg"NON-MEHORY ACCESS FOLLOWED BY REFRESH REQUEST";
$msgH ";
$msg"
------------------ INPUT ------------------ -------------- OUTPUT --------------- "
$msg"
OSC, RESET, A22 ,RW, REFREQ,AS ,HSA ,SYSCLK ,COUNT RFC ,RASI ,HSEL, CAS I, HC I, W,OSACK, STATE "
$ms g"
- --- -- ------- ------- - --- -- -- --- -- --- -- --- -- --- --- --- - -- ---- -- --- ---- ---- -- - -- ----'0'
"4"
'0'
"0"
, 0'
"0'
'0'
"0"
'0'
"7"
3-149
$msg" ";
$msg" ';
$msg"NORm REFRESH CYCLE';
$msg' ';
$msg'
------------------ INPUT ------------------ -------------- OUTPUT --------------- •
$msg'
OSC,RESET ,A22,RW ,REFREQ.AS .HSA. SYSCLK,COUNT RFC ,RAS I .HSEL .CASI ,KC I ,W. DSACK,STATE •
- ......... ... ...... ...... ... ...... --_ ............ .................................
...... ......
...
...
...... -_... "
$msg'
'0'
x X X
H
H
'1"
X
X X X
X
'I'
L
H
H
"1"
X X X
X
' 2'
L
H
H
'1"
'3 '
X X X
X
L
H
H
'1"
' 4'
X X X
L
H
H
X
'7'
H
H
'5'
X X I
X
H
"7'
'6'
X X X
X
H
H
H
'0'
--- -_ --_ -_ -_ -_
-_
-- -_ --_ ------ -_ -- -- ---_ --
$msg" ';
Smsg' ';
$msg'NORHAL REFRESH CYCLE FOLLOWED BY ACCESS GRANT REQUEST";
Smsg' ";
$msg"
------------------ INPUT ------------------ -------------- OUTPUT --------------- •
$msg'
OSC,RESET.m .RW .REFREQ. AS,HSA. SYSCLK. COUNT RFC .RASI. KSEL ,CASI .HC I. W.DSACK. STATE •
............ ...
............ ............... ............ .................................... ...... ............ ...... .................................... -_............... "
$msg"
' 0'
X
e
X X
X
H
H
H H
'7'
'0'
X X
X
X
H H
H
H H "7"
e
e
X X
X
X
H
H
H H
'I'
"7'
e
X X
X
X
'2'
H
H L H H
"7'
'3'
X
e
X X
X
L
H L H H
'7"
'4 '
e
X X
X
L
H L H H
"7"
X
'5'
e
0 X
X
X
H
H L
H
"7"
'6'
H H
H
e
0 X
X
X
H
"1"
'7'
X
e
0 X
X
H H H H
'7"
'8'
e
X
X
H
H H
"7'
'9'
X
e
L
H H
'7'
e
X
' 10'
L
H
'7'
e
X
'II'
L
L
"7'
e
'12 '
H
'7"
l
e
'13'
H
"1"
L
'14 '
e
L
H
'3'
-- -_
-_ -- -_
-_
--
--
-_ --_
-_ --
$msg" ';
$msg' ';
$msg'HOLD I NG STATE 3 WITH EXTENDED REFRESH REQUEST';
$msg' ';
$msg'
------------------ INPUT ------------------ -------------- OUTPUT --------------- ,
$msg'
OSc. RESET. A22 ,RW. REFREQ.AS. HSA. SYSCLK .COUNT RFC .RAS I. mL .CASI. HC I. W, DSACK •STATE •
$msg"
--- ------ ----- ---- --------- --- ------- - - -- -- -- --- ------- ----- -------- ---- -- --- ----, 0'
H
'3'
'0'
H
'3"
, 0'
H
"s·
3-150
$msg"
';
$msg" ";
$msg'EXTENDED REfRESH CYCLE";
$msg" ";
$msg"
------------------ INPUT ------------------ -------------- OUTPUT --------------- "
$msg"
OSC. RESET. A22 .RW.R£fREQ .AS .HSA. SYSCLK. COUNT RfC .RAS I.HSEL. CAS!. HC I. W. DSACK. STATE "
$msg"
-- -- --- - -- ---- --- - -- - - -- -- - - - - - -- - - -- - - - - - - - - - - - - -- -- -- -- - - - - - - - -- - --- -- - --- - -- - -, 0'
'S"
H
'S"
'I'
, 2'
H
"S"
'3'
"7"
H
3-151
..
3-152
Programmable Frequency Divider
~
TEXAS
INSTRUMENTS
3-153
'III
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service Identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant information to verify, before placing orders, that
the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability forTI applications aSSistance, customer product
deSign, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represents that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1989, Texas Instruments Incorporated
3-154
Prog"rammable FreCJpencfw Divider
A Single Chip Solution and A Multiple Chip Solution
INTRODUCTION
The purpose of this application report is to provide a comparison between the EP61 0
and the TIBPAL22V1 0 architecture capabilities and also illustrate some of the latest
PLD (Programmable Logic Device) design tools offered by Texas Instruments. First,
a brief description ofthe EP61 0 and 22V1 0 device architectures will be given followed
by two unique implementation examples. The first with one EP610 and the second
using two TIBPAL22V1 0 devices. Finally, a comparison will be made between the two
designs.
DEVICE ARCHITECTURES
Although the EP61 0 and TIBPAL22V1 0 are both available in the same package types,
the device architectures are considerably different. Both devices utilize a programmabie" AND", fixed "OR" type of architecture common to all programmable logic devices. The EP610 has eight programmable "AND" terms, called Product Terms, per
output while the '22V1 0 can utilize up to 16 product terms on some outputs. The main
difference between the two devices which makes the EP610 better suited for this
application is the number of registers available in each device. The EP610 has 16
registers available while the '22V10 has only 10, one per macrocell. A complete description of the device architectures and macro cell capabilities can be found in the
device data sheets.
DESIGN METHODOLOGY
In the first example, design development will be accomplished using theTI EPLD Development System. The design will be entered in a schematic format using multiple,
4 bit frequency dividers and multiplexers for output control. The design will then be
automatically fitted into an EP610 using the A + PLUS software.
The second example will illustrate how to implement the same application with TI's
proLogic software. This example will consist of a 12 bit counter and the control logic
which allows anyone of the 12 counter bits to be routed to a single output thus creating a progammable frequency divider.
3-155
SOLUTION 1: Single Chip Frequency Divider Implemented Using EP610
Figure 1 shows the schematic which was entered using the TI EPLD Development
System to implement the EP610 design. Three 4 bit frequency dividers were used to
implement the 12 bit division. Notice that the divide by 16 bit output of each device
was fed to the clock Input of the next. By feeding these ouputs to each successive
stage, a 21 to 212 frequency divider can be Implemented.
The next level is a multiplexing level which routes the appropriate divided output to
the final output, FDIV. TIlis task is accomplished using an 8 to 1 and a 4 to 1 multiplexer. Some extra control logic is also necessary to provide the final level of multiplexing
to the output. The input signals A, B, C, and D are used to select the desired frequency
division. TIle table below illustrates how the device will function:
INPUT
ABC D
o
o
o
0 0 0
0 0 1
0 1 0
•
•
•
1 0 1 0
1 o 1 1
FREQUENCY DIVISION
DIVIDE BY:
21
22
28
•
•
•
211
212
Finally, the design is compiled using the A + PLUS software and a standard JEDEC
file is produced which can then be programmed into a single EP610.
3-156
"
I
f
________ J
3-157
SOLUTION 2: Multiple Chip Frequency Divider Implemented Using Two
TIBPAL22V10 Devices
In this next example two TIBPAL22V1 0 devices will be used to implementthe frequency divider. Program Listings 1 and 2 show the proLogic codes developed for this
application. The code shown in Listing 1 is for device A which provides the 10 lower
bits of the 12 bit counter. First, the pin aSSignments are made which include a clock,
clear, and 10 counter outputs. Next, the D input to each register is specified using
Boolean equations followed by output enable and polarity configurations. Finally,
test vectors are specified which allows the code to be Simulated before actually programming a device.
The next proLogic code shown in Listing 2 is for the B device which provides the two
most significant bits of the 12 bit counter as well as the mutliplexing control for the
outputs. The clock inputforthe B device is driven by the 09 output from the A device.
It can be seen from the Boolean equations in Listing B that 12 productterms are needed to implementthe FDIVoutput. Each of these "AND" terms is refered to as a Product
Term. This is why the '22V10 was chosen for this application since as many as 16
product terms are available in this architecture where most PALs have a maximum
of 8 per output.
Diagrams of both solution 1 and 2 along with device pin outs are shown in Figure 2.
A complete copy of the proLogic software and manual explaining syntax, design
entry methods, device support and simulation can be obtained from your local TI
sales office or by calling the TI Programmable Logic applications hotline at (214)
997-5666.
3-158
Listing 1: Device A
title
{
Device:
TIBPAL22V10
Application:
12 Bit Programmable Frequency Oi vider: Device A
Source:
Kyle Newman
Texas Instruments
9/89
}
include p22vlO;
1* specify that target device is TIBPAL22V10 */
define
/* define input pins
define
define
define
define
define
define
define
define
define
define
define
CLK = pin!
CLR = pin2
QO
Ql
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
*/
1* define output pins */
pin14
pin15
pin16
pin17
pin18
pin19
pin20
pin23
pin22
pin21
1* define equations to implement lower 10 bits of counter */
&
QO.d
! (QO.q)
Q1. d
( I QO. q & Q1. q
QO. q & ! Q1. q) & ! CLR ;
Q2.d
(IQO.q & Q2.q
IQ1.q & Q2.q
Q3.d
(!QO.q & Q3.q
IQ1.q & Q3.q
!Q2.q & Q3.q
QO.q & Q1.q & Q2.q & IQ3.q) & !CLR
Q4.d
!CLR ;
= (IQO.q & Q4.q
I IQ1.q & Q4.q
I !Q2.q & Q4.q
I !Q3.q & Q4.q
I QO.q & Q1.q &
Q2.q & Q3.q &
I
QO.q & Q1.q & !Q2.q) & !CLR
IQ4.q) & !CLR
Q5.d
(!QO.q & Q5.q
IQ1.q & Q5.q
IQ2.q & Q5.q
IQ3.q & Q5.q
IQ4.q & Q5.q
QO.q & Q1.q & Q2.q & Q3.q & Q4.q & !Q5.q) & !CLR;
Q6.d
(!QO.q & Q6.q
!Q1.q & Q6.q
!Q2.q & Q6.q
IQ4.q & Q6.q
!Q3.q & Q6.q
IQ5. q & Q6.q
QO.q & Ql.q & Q2.q & Q3.q & Q4.q & Q5.q & !Q6.q) & !CLR;
Q7.d
(IQO.q &
!Q1.q
I I Q2. q
!Q3. q
I
I
Q7.q
& Q7.q
& Q7. q
& Q7. q
3-159
•
IQ4.q & Q7.q
IQ5.q & Q7.q
IQ6.q & Q7.q
QO. q & Q1. q & Q2. q & Q8. q & Q4. q & Q5. q & Q6. q & I Q7 • q) & ! CLR;
QB.d
=
I
I
I
I
I
I
I
(IQO.q & QB.q
IQ1.q & QB.q
IQ2.q & Q8.q
IQ4.q & Q8.q
IQ8.q & Q8.q
IQ5.q & Q8.q
!Q6.q & QB.q
!Q7.q & QB.q
QO.q & Q1.q & Q2.q & Q8.q & Q4.q & Q5.q & Q6.q & Q7.q &
I
IQB.q) &
ICLR;
Q9.d
(IQO.q & Q9.q
IQ1.q & Q9.q
IQ2.q & Q9.q
IQ8.q & Q9.q
!Q4.q & Q9.q
!Q5.q & Q9.q
!Q6.q & Q9.q
IQ7.q & Q9.q
IQ8.q & Q9.q
QO . q & Q1. q & Q2. q & Q8. q & Q4. q & Q5. q & Q6. q & Q7. q & Q8. q &
!eLR;
I
I
I
I
I
I
I
I
1* permanently enable all counter outputs *1
QO.oe
1;
Q1.oe
1; Q2.oe
1 ; Q8.oe
1;
Q5.oe = 1;
Q6.oe = 1; Q7.oe
1; Qa.oe = l '
=
1*
QO
Q5
1*
define outputs as active high
q;
= q;
Q1
Q6
q;
= q;
Q2
Q7
q;
= q;
Q8
Q8
=
q;
q;
Q4.oe
Q9.oe
I Q9 . q) &
1;
l'
*1
Q4
Q9
q;
q;
define some test vectors to verify that counter is working properly
CLR
Q8
Q2
Q1
QO
1* eLK
*1
01
test _vectors {
pin1
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
3-160
pin2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
pin17
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
pin16
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
pin15
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
pin14;
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
1* RESET *1
1* RESET *1
1*
'1
1*
*1
1°
'1
4
*1
1°
1*
*1
1*
*1
1*
*1
1*
*1
1*
*1
10 *1
1*
11 *1
1*
12 *1
1*
18 01
1*
14 *1
1*
15 *1
1*
0
I'
*1
1° RESET *1
Listing 2: Device B
ti tle {
Device:
TIBPAL22V10
Application:
12 Bit Programmable Frequency Divider:
Device B
2 MSB and Multiplexing Control
Kyle Newman
Source:
include p22v10;
define
define
CLK
CLR
define
A
B
C
D
define
define
define
define
define
define
define
define
define
define
define
define
define
define
,"
,"
,"
,"
,"
'","
,"
pinS
pin4
pin5
pin6
pin7
pinS
ping
pin10
pinl!
pin13
pin14
pin15
pin16
pin17
Q10
Qll
define
FDIV = pin18 ;
pin19
pin20
Q11.d
(!Q10.q &. Qll.q
QO
Q1
Q2
Q3
Q4
Q5
Q6
Q7
QB
Q9
QlO.q
Q11.q
. . etc
define counter inputs from device A
define 2 MSB of 12 bit counter
divided output
"'"'*'
*'
*'
*'
*1
*'
Q10.q &. !Q11.q) &. !CLR ;
= 1;
&. !A &. !B &. !C &.
D
&. !A &. !B &. C &. !D
&. !A & IB &. C &. D
&. !A &. B &. IC &. ID
&. !A &.
&. !A &.
&. !A &.
&.
&.
&.
&.
A
A
A
A
&.
&.
&.
&.
B
B
B
IB
IB
!B
IB
&. !C &.
&.
&.
&.
&.
&.
&.
C
C
!C
!C
C
D
&. !D
&.
D
&. !D
&. D
Q11.oe
= 1;
Qll
= q;
,*,*
&. !D
C &.
D;
FDIV.oe
define outputs as active high
= q;
*/
&. !A &. !B &. !C &. !D
permanently enable all outputs
Q10.oe
Q10
Q Output
divide by 2
4
define equations to control multiplexing of outputs
FDIV
/*
Select Input
ABCD = 0
1
*'
"'"'
define equations to implement 2 14SB of counter *1
I (Ql0.q) &. !CLR
/*
select inputs for multiplexing outputs
'*
Q10.d
1*
clock input is from Q9 on device A
clear goes to pin 2 on both devices
1*
define
1*
9'89
'" specify that target device is TIBPAL22V10
pinl
pin2
QO
Q1
Q2
Q8
Q4
Q5
Q6
Q7
Q8
Q9
Texas Instruments
" . q" was used on these terms
because they are internal feedbaoks
"'*'
*/
= 1;
*/
3-161
""
CLK
ClR
ClK
ClR
A
B
C
D
(1)
(1)
22V10
QO-Q9
(3)
(14 - 23)
A
EP610
(3)
(2)
(18)
(11)
FDIV
(14)
Q9
(23)
(21)
L>
SOLUTION 1
22V10
'---(2)
A
(7-11,13-17)
(18)
B
(11)
B
FDIV
(14)
C
(23)
D
SOLUTION 2
( ) denotes Pin Number
Figure 2. EP610 vs TIBPAL22V10 Solution
CONCLUSION
Following is a brief comparison of the two design implementations discussed in the
applications note.
SOLUTION 1
SOLUTION 2
DEVICETVPE
EP610
TlBPAL22V10
PACKAGE
24 PIN DIP
24 PIN DIP
MAX Icc
60mA
180mA
PROPAGATION DELAY
25ns
20ns-25ns
MAX CLOCK FREQUENCY
40 MHz
28.5 MHz
PRICE PER PACKAGE
1.7X
X
NUMBER OF DEVICES
1
2
From this comparison, it can be seen that the EP61 0 is a better solution for this application. Not all applications will yield these results between a EP610 and a 22V10.
However in register intensive applications such as the frequency divider, an EP610
can offer considerable savings in power consumption and package count while providing enhanced performance at a comparable price.
3-162
EP1810 as a Bar Code Decoder
~
TEXAS
INSTRUMENTS
3-163
..
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant information to verify, before placing orders, that
the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by govemment
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability forti applications aSSistance, customer product
deSign, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represents that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
AB27 Rev 2.0
Copyright © 1987, 1988, ALTERA Corporation
Printed with permission from ALTERA Corporation, 1989
3-164
FEATURES
• Description of a generic Barcode
• Description of a Bar Code Decoder EPLD
• State machine implements controller functions
• Functional simulation verifies design before
commitment to silicon
• TTL MacroFunctions simplify and speed up the
design task
3-165
3-166
EP1810 as a Bar Code Decoder
i
::
!
is
INTRODUCTION
The following Applications Brief describes a bar code decoder implemented in an
EP1810. The EP181 0 decodes a generic bar code, stores the decoded data byte,
and alerts a microprocessor that data is ready. This Application Brief describes a
generic bar code decoder, the various design methodologies used to implement the
design and the functional simulation used to verify the design before programming
devices. The final design is specified by a mix of design entry formats: state machine
design entry is used to specify an intemal controller, while schematic capture and
TTL macrofunctions are used to define additional functions.
WHAT IS BAR CODE?
Bar code, a means of representing binary data or program information, has beco(l1e
popular due to its great flexibility and cost effectiveness. For many applications bar
code yields superior results when compared to optical character recognition, particularly for success on a first time read. Bar code is suitable in many applications
where magnetic stripe or other media would be impractical. Bar code has several
variations; this Application Brief covers a common version with some advanced features.
PHYSICAL SPECIFICATIONS OF BAR CODE
Although many versions of bar code exist to support the variety of applications
served, there is enough in common to treat a meaningful generic case (Figure 1).
All bar codes have "zero", "one", and space characters; the "zero" and space character are the same width, while the "one" is twice that width. All bar codes have a
header and a taii. The generic bar code has a header consisting of a zero-zero sequence, followed by a checksum byte. The tail is a one-zero sequence. Data follows the header and terminates with the tail. All bar codes have maximum limits on
the number of data bytes.
One requirement for accurate bar code detection is that the reader, usually a light
pen, scan the bar code at a relatively constant speed. For this reason bar codes
are of modest width; its easier to move a light pen at reasonably constant speed over
shorter distances than over longer ones. Before reading the bar code, the light pen
is inactive or in a white region. As the light pen reaches the dark region of the header,
the light pen output goes high. If the light pen's speed varies by too much, then the
mis-read should be detected by verification against the checksum.
3-167
A generic barcode has ·0", "1", and space characters. Bar code sequences consist of START and
STOP bars, data and checksum bytes.
~~'O' ~ ~·1·
IIIIIIII
~~·S"
11111111111111111111
V
~ "--y-/
START BYTE 1
BARS
'--v-' '--y--/ Y
BYTE 2 BYTE 3
BYTE 4 STOP
BARS
Figure 1. Sample Barcode
BAR CODE DECODER OVERVIEW
Figure 2 shows a bar code decoder implemented in an EP181 O. The bar code data
is fed into the EP181 0 through the IN Input. The data is used by the sync counter
to determine the input data read rate, and by the state machine to decode incoming
data, which Is stored in a shift register. Once 8 bits of data have been shifted into
the shift register, an open collector interrupt back to the microprocessor (INTO) goes
low. Various status outputs (OIR, ACT, and ERR) indicate the current state of the bar
code decoder.
The bar code decoder conSists of 5 different modules: a sync counter, a controller
state machine, a byte counter, a shift register, and a microprocessor Interface.
Sync Counter
The bar code decoder uses the bar code header's leading single width dark region
to measure the fundamental width of a "zero". When the light pen passes over the
first dark region, the sync counter begins counting. The sync counter stops counting
only when the light pen has completed reading the dark region (ie. when it reads the
beginning of light region). The count value thus reflects the amount of time required
to read the width of a space or "zero" bar. It takes tWice the count value to read a
"one" bar.
The count value is used to sample the bar code data. Since the light pen scanning
speed will vary somewhat over the bar code label, the count value is only approximately correct at measuring width. For this reason it is best not to sample data on
the edges of the light and dark regions, but rather in the center of these regions. The
first sampling occurs in the middle of the space width following the leading dark region when the sync counter reaches half of its sync value. The counter is reset and
subsequent samples occur when the sync counter reaches the full sync value.
3-168
A barcode decoder implemented in an EP1810 consists of Syn Counter,
State Controller, Byte Counter, Status Outputs, and Shift Register sections.
A@2
c~~~~~~~~~~-~~-
INP
B@1i
c:::>-----------~~~---------.,.
INP
C@i4
c>-----INP
elK
c:::::>-INP
CLR@3
D~23
Figure 2. Bar Code Decoder Schematic
3-169
The values of the data samples correspond to the bar encoded data. If "dark-light"
is read, then the light pen has passed over a single width dark region followed by
a single width light region, indicating a "zero". If a "dark-dark-light" Is read, then
the light pen has passed over two adjacent dark regions followed by a light region,
indicating a "one". If any other combinations starting with "dark" are read, or if two
adjacent "light"s are read, then the code is Invalid.
The sync counter Is implemented by four Macro-Functions (8COUNT, 2 of 74157s,
and the 74374) and terminal count circuitry comprised of logic and an NOCF primitive.
Byte counter specification
The byte counter counts the number of bits shifted in, and if they are a multiple of
8, alerts the microprocessor that a full byte is ready to be read. The byte counter
is implemented using a Gray code sequence, a sequence which only has one bit
change between any two count transitions, so that its outputs will be glitch-free; preventing spurious outputs from inadvertently Interrupting the micro-processor. Figure
3 shows the byte counter implemented using the state machine format.
3-170
An 8 stage gray counter is implemented using the high level state machine
format (SMF)
%GRAY3 3 BIT GRAY COUNTER%
PART: EP1810J
INPUTS:
OUTPUTS:
NETWORK:
EQUATIONS:
TCNT = TCNTEN*/G2*/G1*/GO;
MACHINE: GRAY3
CLOCK: GCLK
STATES: [ G2 G1 GO
[
SO
0 0 0
S1
0 0 1
S2
0 1 1
S3
0 1 0
1 1 0
S4
S5
1 1 1
1 0 1
S6
1 0 0
S7
SO:
S1:
S2:
S3:
S4:
S5:
S6:
S7:
S1
S2
S3
S4
S5
S6
S7
SO
%STATES MAKES UNCONDITIONAL%
%TRANSITION TO NEXT STATE %
END$
Figure 3. Byte Counter State Machine File
The byte counter has an open collector output back to the microprocessor (INTO),
fashioned by connecting the input of a 3-state driver to ground and selectivelyenabling the 3-state (TCN1).
Shift register specification
Input data is stored in a 74164 shift register. The shift register clock is fed from the
state controller state machine to assure that data is latched at the appropriate time.
The 74164 outputs should be buffered and connected to the microprocessor bus.
The shift register is implemented by a 74164 macrofunction and CONF output primitive.
3-171
Bar Code Decoder Status Information
Special outputs allow extemal devices to determine the status of the bar code decoder. If active, the DIR signal indicates that the tail was read before the header.
In this instance all data and checksum words would be reversed, and the microprocessor would have to make the compensating transformations. The ability to read
bar codes backwards as well as forwards is a practical requirement, permitting bar
codes to be read upside down as well as scanned from right to left.
The ACT signal indicated that a bar code is being scanned in. This is useful for a
variety of error handling or initialization tasks: for example a microprocessor may
poll on this signal and enter special routines dedicated to bar code reading.
The ERR signal indicates an illegal sequence of light and dark regions was encountered during the decoding process: perhaps the bar code is unreadable, or the scan
rate was not uniform enough. The microprocessor may use ERR to dump illegal
reads without computing and comparing a checksum against the checksum byte
passed to the microprocessor by the bar code.
The status information is comprised of the open collector CONF output, and the
SONF and RORF status flags.
State controller specification
The bar code decoding process requires intelligence to determine if a header is valid, and to convert the light and dark bar code regions to machine readable data.
Beyond data conversion, the bar code decoder must coordinate activities of sync
counter, shift register, byte counter, and status generation circuitry. The simplest
means of achieving these aims Is to create a centralized state controller state machine. Figure 4 shows the state diagram for the state controller, implemented using
the high level state machine syntax shown in figure 5. The algorithm for Figure 4 is
as follows:
IDLE - the machine idles until a dark region is read by the input device (eg. light pen)
at which time the sync counter is started.
SYNC - The sync counter counts up while in this state. The machine stays in this
state until reading the first light region. The sync count corresponds to the width of
the first dark bar.
LATCH - The machine latches the count value into a holding register. Hereafter the
sync countwill expire on every modulus of the latched count, and cause the reading
of the input stream.
HDR1, HDR2, FWD, REV, ERR - The machine begins reading the rest of the header
bits. Bear in mind that we get two different sequences depending if we read a 0-0
sequence or a 0-1 sequence. The 0-0 sequence is a forward read, while the 0-1
sequence is a backward read. If there are any improper reads we will go to ERR.
Direction status is latched dependent on either state FWD or REV. At the end of this
we begin the reading of data and checksum bytes into the shift register.
ACT1, ACT2, ACT3, ACT4 - These are the ac;tive reading states. The ACT1- ACT3
lOOp indicates a "0" was read. The ACTI-ACT2-ACT4100p corresponds to the reading of a "1". Reading is stopped when a long white space is read indicating the end
of the bar code.
3-172
POWER UP - - - - - - - ,
Barcode decoding activities
are coordinated by the State
Controller. This state diagram
describes the behavior of the
BARCTL portion of the State
Controller.
else
ZERO
*IIN
else
IN*ZERO
IIN*ZERO
IN*ZERO
else
IIN*ZERO
Figure 4. Controller State Diagram
3-173
% Bar Code Controller %
PART: EP1800J
INPUTS:
OUTPUTS:
EQUATIONS:
NETWORK:
DIRS = FWD;
ACTD = I IDLF ;
SYNCCLR = IDLK • /IN;
SYNCEN = IDLE;
DCLK
ACT2 + ACT3;
BSEL = ILATCH;
DIRR = IDLE;
ERRD = ERR' IIDLE;
SYNCUP = SYNC;
SYNCLATCH = LATCH;
TENB = ACT2 + ACT3 + ACT4;
MACHINE: BARCTL
CLOCK: CLK
STATES: [Q3 Q2 Q1 QO]
IDLE
[ 0 0 0 0]
SYNC
[
0 0
1]
LATCH [ 0
1 1 1]
HDR1
[
0
1]
HDR2
[
1]
FWD
[ 0
0 1]
REV
[ 0
0]
ACT1
[ 0
0 0]
ACT2
[
0 0]
ACT3
[ 0 0
0]
ACT4
[ 0 0
1]
[ 1
ERR
0]
IDLE:
IF IN THEN SYNC
SYNC:
IF lIN THEN LATCH
LATCH:
HDR1
HDR1:
IF IN' ZERO THEN HDR2
IF lIN • THEN ERR
HDR2:
IF IN • ZERO THEN REV
IF /IN • ZERO THEN FDW
FDW:
IF ZERO THEN ACT1
REV:
IF IN • ZERO THEN ERR
IF /IN • ZERO THEN ACTl
ACTl:
IF IN • ZERO THEN ACT2
IF /IN • ZERO THEN ACT3
ACT2:
IF IN • ZERO THEN ERR
IF /IN • ZERO THEN ACT4
ACT3 :
IF IN • ZERO THEN ACT1
IF /IN • ZERO THEN IDLE
ACT3 :
IF IN • ZERO THEN ACT1
IF /IN • ZERO THEN IDLE
ERR:
IF ZERO THEN ACTl
END$
Figure 5. Controller State Machine Described Using the State Machine Format
3-174
IMPLEMENTATION OF THE BAR CODE DECODER
Figure 2 shows a LogiCaps schematic of the Bar Code Decoder. The sync counter
is implemented by four MacroFunctions (8Count, 2 of 74157s, and the 743474) and
terminal count circuitry comprised of logic and an NOCF primitive. The byte counter
is implemented in state machine format In a file named GRAY3.SMF (Fig 4). The shift
register is Implemented with MacroFunctlon 74164 and CONF output primitives. The
microprocessor interface consists of a CONF configured as an open collector output
and status flags Implemented by SONF and RORF primitives. The State controller
was implemented in a state machine file named BARCTL.SMF (Fig 5). The state machines are outlined on the schematic for documentation purposes only. The borders
are not required for design processing.
DESIGN PROCESSING
Design input is contained in three separate files, of two different formats. LogiCaps
generates the bar.adffile, whereas barctl.smf and gray3.smf are state machine files.
Linking all the design information is done in the A + PLUS Design Processor (ADP)
section of the A + PLUS development software. This is done by answering all the
prompts as in Figure 6.
ADP automatically links the names between the various input files and create an output file bar.jed for device programming. Device utilization, given after processing,
indicated that 38 of the 48 macrocells were used, 2 of the 7 inputs, and 36 percent
ofthe available logic.
APLUS
ADP
FORMAT
Adf
FILE NAME:
MIN
INV CTL
LEF ANAL
bar barctl.smf gray3.smf
yes
no
yes
Figure 6. Multiple Design Processing Prompts
SIMULATION VERIFIES OPERATION BEFORE PROGRAMMING A DEVICE
Simulation was run on the device to assure proper operation. In this instance a serial
input stream corresponding to a valid bit stream is read by the design. It properly
sequences through the states, latches the data, and interrupts a processor. The anticipated simulation data is shown in Figure 7. The controller state machine isverified
by comparing the QO-Q3 outputs, and the state table values in Figure 5.
3-175
The Simulator will be driven with a data Input emulating the previous sequence. Design behavior Is verified by monitoring for the co"ect response from the Functional SlmulatOl
ENCODED
BIT
0
o
""""TIo,11
CYCLE
4
5
8 10 12
.....................
FIND
HEADER
...
ACTIVE
FLAG
SET
o
o
I
16 18 20 22
...
STORE
~.
I
26 28 30 32
...
...
~.
~.
STORE STORE
o
o
I
36 38 40 42
...
...
~.
~.
STORE STORE
...
...
~.
~.
I
56 58 60
...
...
~.
~.
STORE STORE
...
INTERRUP
TO
PROCESSOR
DIR
FLAG
SET
Figure 7. Anticipated Simulation Data
3-176
I
46 48 50 52
STORE STORE
...
o
...
STORE
~.
Development Systems
4-1
Contents
Page
EPLD Development System Summary ...........................
EPLD Design Software Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Third-Party Software Tools .......................... . . . . . . . ..
4-2
4~3
4-15
4-23
EPLD Development System Summary
Part Number: EP-APLUS
~
TEXAS
INSTRUMENTS
4-3
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant information to verify,before placing orders, that
the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by govemment
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability forTI applications assistance, customer product
deSign, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represents that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1989, Texas Instruments Incorporated
All Rights reserved
Copyright © 1989, Altera Corporation
All Rights reserved
TRADEMARKS
A+PLUS, LoglcMap, LogiCaps, MacroMunchlng, SALSA, and
ASAP are trademarks of Altera Corporation.
IBM, XT, AT, and PC-DOS are trademarks of Intemational Business
Machines, Inc.
MS-DOS is a trademark of Microsoft Corporation.
4-4
FEATURES:
o
Complete Design Solution for TI EPLDs
• Development Software
• Programming Hardware
• Device Samples
o
Supports Multiple Design Entry methods
• Schematic Capture Entry
• Netlist Entry
• Boolean Equation Entry
• State Machine Entry
o
o
o
Device Fitter Optimizes Device Resources
Support for User-Defined MacroFunctions
Automatic Pin Assignments
GENERAL DESCRIPTION:
The Texas Instruments (TI) Erasable Programmable Logic Device (EPLD) Development System is a consolidated Computer Assisted Engineering (CAE) tool that transforms a logic design into a programmed device. The development system supports
a variety of input formats that can be used individually or combined together to meet
the needs of a particular design task. The system includes design entry, design processing, functional simulation and device programming.
The A + PLUS T. software, which is at the heart of this system, includes a design processor which transforms the input format to optimized code used to program the targeted EPLD. The design processor implements logic minimization, automatic EPLD
part selection, architecture optimizations and design fitting. The system also includes LogicMap TO software for device programming.
4-5
: -DEsiGN ENTRY-: ,- -----DEsiGN PROC"E-SSI-NG- ------: ,- -OUTPUi--ANO- --~
SCHEMATIC
, :
EXPANDER
LDQIC
DESIGN
AND
AND
MINIMIZER
FITTER
MACROMUNCHER
TRANSLATOR
FLATTENER
::
,,
SIMULATION
,,
FUNCTIONAL
,,
'I
,,
SIMULATOR
I
I
JEDEC
FORMAT
TI
EPLD
PROGRAMMER
I
ENTRY
l
_______________
, :
J
1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
It
I.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1
.!
Figure 1. The TI EPLD Development System
FUNCTIONAL DESCRIPTION:
As can be seen in the detailed block diagram of the TI EPLD Development System,
in Figure 2, the A + PLUS software accepts four different design entry formats: Schematic Capture, Nellist, Boolean Equations, or State Machine input. The designer Is
not restricted to just one design entry format but has the freedom to "mix and match"
different formats to best meet the needs of the overall logic design.
The design entry format is converted to an A + PLUS Design File (ADF) which is the
common entry format for the A+ PLUS software. The ADF is then submitted to the
A+ PLUS Design Processor (ADP). The ADP is composed of a set of modules integrated together that produce an industry standard JEDEC code used to program the
EPLD.
The ADP also produces documentation showing minimized logic and EPLD utilization. Once the JEDEC file is produced, the user may functionally simulate the design.
Finally the user can program the chosen EPLD with the LogicMap programming software and the hardware provided with this system. TI qualified third party programmers can also be used for production volume programming.
4-6
Schematic Capture
Logic Designs may be entered from schematic drawings by using the LogiCaps TN
or other schematic capture packages. Schematic capture design entry allows the
user to quickly construct a wide range of logic circuits. Designs entered with this
method use library primitives in the form of low level functions (input, basic gates,
flip-flops, I/O primitives) to high level TIL MacroFunctions. LogiCaps is mouse driven and supports hard copy printouts and plots. As required the schematic representation is converted to an ADF file and processed by the A + PLUS Design Processor.
LogiCaps Is a high performance schematic capture package that has been optimized
for entering designs destined for TI EPLDs. It is the primary design entry platform for
any member of the TI EPLD family. When used in conjunction with TIL and user defined MacroFunction libraries, LogiCaps becomes the essential tool for the design
of high density EPLDs.
The TI design library is a collection of high level MSI building blocks which allow the
LogiCaps user to enter designs in a "block manner". An initial primitive symbol Iibrary contains basic gates, flip-flops and I/O symbols as well as the most commonly
used TIL SSI and MSI functions. Other design libraries include an extenSive TIL 7400
series symbol library, and user-defined libraries. In addition each library also contains logic functions not available in standard TIL or CMOS devices. Examples include counters implemented with toggle flip-flops, combination up/down counter
with left/right shift register, and inhibit gates.
Netlist Entry
The A + PLUS software directly supports netlist entry from third party schematic capture packages via the the A + PLUS Design File (ADF). Using a standard text editor,
a netlist which describes the circuit Is created by using a Simple, high-Ievel,design
language.
The netlist may contain basiC gates, I/O architectures, boolean equations, and TIL
MacroFunction descriptions. In addition, user defined comments and white space
may be freely used throughout the ADF file. The completed file is then submitted to
the design processor. This entry method also permits circuit designers to utilize netlist outputs (e.g from workstations or other schematic capture packages) that have
been translated into ADF format.
Boolean Equations
The A + PLUS Design Processor compiles Boolean equation designs that are written
in a simple design language. The source for the design may be created with any convenient text editor. The language supports free-form entry of all syntactical elements.
Boolean equations need not be entered in sum-of-products form since the design
processor will expand equations automatically. The multi-pass design processor/
compiler has the ability to support intermediate equations. This feature allows for significant reduction in the size ofthe Boolean equation source code and allows the designer to define the logic in the most natural conceptual manner.
State Machine
Designs that are easily represented with state diagrams may be entered via the state
machine approach. This method uses a high level language featuring IF-THEN con-
4-7
•
structs, Case statements and truth tables. this design entry supports both Mealy and
Moore state machines. Outputs of the state machine may be defined conditionally
or unconditionally allowing flexible output structures that can be merged with other
portions of the design. In addition, multiple state. machines may be linked within the
same design. Boolean equations can also be employed, thus offering the definition
of high level Intermediate logic expression. The software will also select the optimum
flip-flops for the particular design.
DESIGN PROCESSING
The A + PLUS Design Processor (ADP) consists of a series of modules that translate
design Information from a variety of input sources into a JEDEC Standard File used
to program the EPLD. this process is automatic and requires little or no assistance
from the circuit designer.
Design Flattening
The design processor accepts design files from one or more ofthe design entry methods already described. Once the design has been submitted, the first function of the
ADP Is to "flatten" the design from high-level MacroFunctions to low level gate primitives. In order for designs to be flattened, information from the MacroFunction Behavioral Library is transferred to the design flattener, which In tum decomposes all MacroFunctions to their primitive gate equivalents.
MacroMunching
1M
And Default Modes
Once the design is flattened, the design processor analyzes the complete logic Circuit and removes unused gates and flip-flops from any MacroFunction utilized. This
"MacroMuncher" allows the logic designer to freely use the high-level building
blocks from the MacroFunction Symbol Libraries without the headaches of optimizing their use.
When MacroFunctions with unconnected inputs are detected, the design processor
assigns "intelligent" default values. In general, active-high inputs default to ground
(GND) and active-low inputs default to the supply voltage Nee> when left uncon~
nected. This default mode is activated simply by leaving unused inputs without connections, thus eliminating "busy work" and enhancing productivity.
Once the design has been flattened or "munched", and all default values have been
assigned, a secondary design file, (SDF file) is produced for further processing.
Translation/Minimization
The Translator takes the SDF file and checks for logic completeness and consistency.
For example, the Translator validates that no two logic function outputs are shorted
and that all logic nodes have an origin. In the event that the designer has chosen an
EPLD name of "AUTO", the Translator will automatically select the appropriate EPLD
based on the logic requirements of the design.
LogiC minimization of designs is provided by the Minimizer module. Minimization
phases Include Boolean minimization with a SALSA ™ (Speedy A + PLUS Logic Simplifying Algorithm) that yields superior results to other heuristic reduction techniques.
DeMorgan's theorem Inversion can be applied automatically to equations. The processor contains algorithms based on artificial intelligence techniques to select can-
4-8
didate equations that will best be represented by a complemented AND/OR function.
This feature significantly reduces product-term demands that can be generated by
complex logic functions. For TI EPLDs with selectable flip-flop, the Minimizer checks
which type of flip-flops yields a more efficient solution and converts architecture if
necessary. The minimized logic can then be passed to the Analyzer module which
converts the file into human-readable format allowing the designer to examine the
minimized logic.
Design Fitting
The fully minimized design is now transferred to the Fitter. This fitting routine relies
on algorithms based on artificial intelligence software techniques in order to fit the
logic requirements of the design into the specified EPLD providing full pin assignments automatically.
The Fitter module matches the requests ofthe design with the resources of the EPLD.
The Fitter process encompasses all EPLD architectural attributes such as variable
product term distribution, programmable flip-flops, local and global busses and I/O
requirements. If the designer specifies a pin assignment, the Fitter matches the request. If no pin assignments are made, the Fitterfinds an optimized fit for the design.
The Fitter produces a Utilization Report that shows which of the EPLD's resources
were used up by the design and how. Finally, the Assembler module converts the
fitted requests into an image for the part in a JEDEC Standard File.
4-9
•
,......................................................... .. -r .................................................................................................. DESIGN ENTRY
DESIGN PROCESSING
MACRO
FUNCTION
SYMBOL
LIBRARY
MACRO
FUNCOON
BEHAVIORAL
UBRARY
ADLIB
SCHEMATIC
CAPTURE
ENTRY
&
TTL
LogiCaps
MacroFunctions
DESIGN PROCESSOR
MACROFUNCTJON
A+PLUS
NETLIST
ENTRY
FLATIENER
SECONDARY
r-~~r----------t-~
D~GN
•
MACROMUNCHER
FILE
.SDF
BOOLEAN
EQUATION
ENTRY
STATE
MACHINE
ENTRY
... _--------------------------_
,
....
_------------------------------ .. ------------- ..... ---
Figure 2. The TI EPLD Development System
4-10
DESIGN SIMULATION
1
1- -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
COMMAND
FILE
.CMD
...
VECTOR
FILE
VEC
LOGIC
PROGRAMMER
PROGRAMMING EPLD
4-11
•
Design Simulation
Once the design has been fitted to the specified EPLD and a JEDEC file has been
produced, the A + PLUS functional simulator allows the designer to test the logical
operation of the design. This software package requires the use of any general purpose text editor and is completely compatible with the A + PLUS Development System. As a result, users may now enter designs on the EPLD Development System,
have them automatically fitted and optimized, then perform logic simulation without
needing to commit a device to hardware.
A complete set of simulation commands allows the user to check critical logic within
a design in a succinct and straightforward manner. Users can specify commands to
occur at particular events such as during a given circuit condition or at an absolute
simulation timestep. Nodes may be forced to a chosen logic state to verify proper
circuit behavior from any initial condition. The input waveforms from the VECTOR file
containing logic values that are to be applied to the inputs, can be superseded by
another pattern at any point in time.
For debugging purposes simulation breakpOints can be set to halt execution when
a specified event occurs. This "break" command provides designers the ability to
detect illegal states. Once a break condition is met, a command sUb-list is activated
to provide status information or to enter into a separate procedure. For example, a
breakpoint might signal an illegal state, display the current output waveform on the
screen, enter a legal state and continue with the simulation.
Device Programming - With LogicMap II
LogicMap II is the interface software that programs EPLDs from JEDEC files created
by the A + PLUS Design Processor. The program uses the A + PLUS Super Adaptive
Programming algorithm (ASAP 1M ) which significantly reduces device programming
times. LogicMap II fully calibrates the programming environment and checks out the
programming hardware when initiated. In addition the program allows the designer
to review the JEDEC object code generated by the Processor in a structured manner.
The program is fully menu driven and provides views of the device object code
through a series of hierarchical windows. This feature permits low-level observation
and editing of the deSign, viewed from a perspective similar to that of the logic diagram of the device in the data sheet. Individual EPROM bits may be examined or
changed if desired, however this mode of editing is not recommended.
Hardware - Logic Programmer
LogicMap software is used to drive the programming hardware comprised of a software-configured programming card that occupies a single slot in the computer. Programming signals are transmitted to an external programming unit via a 30 inch ribbon
cable and connector. The programming unit contains zero-insertion-force sockets
for easy device insertion. All programing waveforms and voltages are derived by the
programming card so that no additional power sources are necessary. A programming indicator lamp on the programming unit is illuminated when the unit is active.
For ordering information about Texas Instruments EPLD Development System contact yourTl field sales representative, local authorized distributor, or call the customer
response center at 1-800-232-3200. For applications questions contact the Programmable Logic Applications Group at (214) 997-5666.
4-12
RECOMMENDED COMPUTER CONFIGURATION
CJ
IBM~ xrm or ATm Personal Computer, or Compatible, with:
- Either Monochrome, CGA, EGA with extended memory or Hercules
- 640 K bytes of main memory (RAM)
- 20 M Byte Hard Disk Drive and Floppy-Disk Drive
- MS-DOS TN or PC-DOS TN versions 3.2 or later releases
- Full-Card slot for programming Card
- Serial 3-Button Mouse
DEVELOPMENT SYSTEM CONTENTS
CJ
CJ
TI Part Number: EP-APLUS
Software:
- A + PLUS programs and support files
- LogiCaps Schematic Capture Program
- 7400 Series TIL MacroFunction Library
- State Machine Entry Program
- Functional Simulation Program
CJ
Documentation:
- A + PLUS Reference Manual and User Guide
- LogiCaps Manual
- MacroFunction Reference Manual
- Functional Simulation User Guide
- State Machine Entry User Guide
CJ
Software Warranty:
- 12 Month Extended Software Warranty and Update Service
CJ
Hardware:
- Software Controlled Programmer Interface Card
- EPLD Master Programming Unit
- EPLD Device Adapters
CJ
EP610 DIP adapter
(PLEDBOO/610)
EP610 J-Lead adapter
(PLEJBOO/610)
EP910 DIP adapter
(PLED900/910)
EP910 J-Lead adapter
(PLEJ900/910)
EP1810 J-Lead adapter
(PLEJ1800/1810)
EPLD Device Samples
EP610DC
EP910DC
EP1810JC
All contents are packaged in a box measuring 18.5" X 15.5" X 10.5 ".
4-13
•
4-14
EPLD Design Software Summary
Part Number: EP-APLUS-S/W
~
TEXAS
INSTRUMENTS
4-15
•
IMPORTANT NOTICE
Texas Instruments (fl) reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant infOrmation to verify, before placing orders, that
the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by govemment
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability forTI applications assistance, customer product
design, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represents that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1989, Texas Instruments Incorporated
TRADEMARKS
LoglCaps is a registered trademark of Altera Corporation.
A + PLUS is a trademark of Altera Corporation.
IBM and PC-DOS are trademarks of Intemational Business Machines
Inc.
MS-DOS is a trademark of Microsoft Corporation.
4-16
iii!
I
iiSI
,E~LP
Design Software Summary
As the software
only package of the TI EPLD Development System, the
EP-APLUS-S/W extends the TJ EPLD Development System to additional satellite
design stations without the expense of additional programming hardware. It also
fills the needs of design engineers with third party programming hardware already
installed.
Designs are entered and processed through the A + PLUS 1M Design Processor. The
resulting JEDEC file is then transferred to a development system that contains
programming hardware or to a third party programmer where the design is
physically mapped (programmed) into the device.
Features:
o
Complete CAD software
• Offers ease of designing
with TI EPLDs
• Consists of the following pieces:
• LogiCaps® Schematic Capture
Software
o
Software Designed to run on
IBM-XT1M orAT™ compatible PC
with following configuration
• Monochrome, CGA, EGA
with extended memory or
Hercules Display
• 640K bytes of system
memory (RAM)
• MacroFunction Library
• A + PLUS, Assembly Software
• 20M bytes hard drive and
floppy drive
• MS-DOS 1M or PC-DOS 1M
Versions 3.2 or later releases
• Seri.al 3-Button Mouse
4-17
•
LogiCaps Schematic Capture Software
Contents:
LogiCaps Schematic Capture Diskettes
Printer/Plotter Interface
Standard Symbol Library
LogiCaps Manual
Features:
0
Graphical Entry of Logic Schematics
0
Easy Mouse, Key and Menu Commands
0
0
Directly Interfaces with the
A+PLUS software system
Extensive on-line documentation
0
Dual window display capability
0
Orthogonal Rubberbanding of lines
0
Multiple ZOOM levels
0
Area Editing, Save and Load
0
Tag and Drag editing
0
User definable functions (MACROs)
0
Draw schematics up to 90"x90"
0
Schematic plotting with HP7475,7580
and 7585 plotters
0
Standard Symbol Lbrary contains
30 MacroFunctions and over 80
MacroPrimitives
Description:
LogiCaps is a fast and powerful schematic entry tool for capturing designs destined for TI EPLDs. Schematic diagrams are drawn on the screen of a PC using a
mouse; then, with a single command, a netlist file is generated ready for logic
syntheSiS and eventual generation of a JEDEC file to be programmed into silicon.
LogiCaps complements the A + PLUS software to form a complete interactive EPLD
development system.
An engineer could start with a blank "sheet" on a PC, then in minutes transform a
circuit idea into a working, user configured integrated circuit.
The most frequently used functions - drawing and connecting lines, moving and
copying objects, and just getting around in the drawing - are done by simple mouse
motion or pressing a mouse button. Functions used less often are executed by
pressing a single key, while those functions rarely used or requiring more data are
selected from a nested command menu system. No command requires more than
three key presses to execute, unless a file name or some other text is needed.
4-18
MacroFunction Library
Contents:
TTL MacroFunction Lbrary Diskettes
ADLIB (A + PLUS Design Librarian) Diskettes
TTL MacroFunction User Manual
ADLIB manual
Features:
o
o
o
100+ Different MacroFunctions
Allows High Level Design Entry
o
o
Used with LogiCaps Schematic
Entry
MacroMunching of unused Gates
User Definable Symbols and
MacroFunctions with ADLIB
Description:
The MacroFunctions facilitate easy designing and incresed productivity. They are
high level building blocks that allow the user to design at TTL level. This ability
aids a first time user since the TTL functions will already be familiar. The experienced EPLD user will also benefit by being able to increase design productivity with
the use of MSI function blocks.
Most MacroFunctions are commonly used 7400 series SSI and MSI TTL parts. A few
particular ones have been developed specifically to suit logic designs with the
TI EPLD architecture. These have been designed by EPLD design experts and contain inner logic behavior to maximize EPLD speed and utilization.
These MacroFunctions are very versatile and can be used together with user designed MacroFunctions and/or low level logic primitives depending on the logic
needed. The inputs and outputs of the EPLD to be programmed are specified
with A + PLUS I/O design primitives.
4-19
•
A+ PLUS Assembly Software
Contents:
A + PWS Diskettes
ADp, A + PWS Design Processor, Diskettes
FSIM, Functional Simulator, Diskettes
SMV, State Machine Converter, Diskettes
Install Diskettes
A + PLUS Reference Guide
A + PLUS User Guide, includes
FSIM and SMV Manuals
Features: A + PLUS, PLSME (SMV)
The A + PWS programs and support files make the following possible;
o
o
o
Boolean Equation Entry and
Netlist Entry of Logic Designs
o
o
MacroFunctlon Design Capability
Interactive Netlist Design Entry
Design Flattening & Logic
Minimization for complete
Optimization of EPLD designs
Automatic Pin Assignment and part
selection
The SMV program is the means whereby programmable logic state machine
designs are entered (PLSME - Programmable Logic State Machine Entry
incorporates SMV) in addition the following benefits are possible;
o
o
o
o
Multiple State Definition allowed
in one file
Standard Format Allows Design to
be Merged with Other State Machines,
Schematic Entry, Boolean Equations,
or Netllst Entry within a Single EPLD
Human readable format eases the
maintenance of complex designs
Truth Table Option allows the
Specification of Random Logic
From functional definition
o
0
o
Truth Table Option allows the
Specification of Random Logic
From functional definition
Sophisticated minimization
algorithms in A + PLUS Perform
automatic reduction to improve
device utilization
Outputs of State Machines can be
either conditionally or
unconditionally defined
Description - A + PLUS, PLSME (SMV)
The PLSME and the A + PLUS development software automatically transform high
level state machine descriptions into device programming files. PLSME provides
a state machine entry option in addition to the traditional entry methods (LogiCaps
Schematic Capture, Boolean Equations) currently available to A + PLUS. Design information is entered using any standard text editor. It is then processed by the
state machine converter to a standard A + PWS Design File (ADF). This common
intermediate format allows the linking of multiple state machines, schematic,
Boolean, or netlist entered design files.
4-20
Features: FSIM
o
o
o
o
Simulation of BUS Structures
Interactive Debugging ability with
Break, Force, Save and Restore
Commands
Functional Simulation for Tl's
Entire Family of EPLDs
Easy Definition of Inputs using
State Table, Vector Patterns or
Predefined Patterns
o
o
o
Output formats include state table
or graphic waveforms for
on-screen display or hard
copy printout
Ability to access buried nodes
within the design
Back-end integration with
A + PLUS Environment using
JEDEC File for Simulation
Description - FSIM
FSIM, the A + PLUS Functional Simulator, provides a convenient and easy-to- use
tool for testing the logical operation of any EPLD design. This software require
the use of any general purpose text editor and is completely compatible with
the A+ PLUS development system. Consequently users may now enter designs,
have them automatically fitted and optimized, then perform logic Simulation without needing to commit a device to hardware.
A complete set of simulation commands allows the user to check critical logic
within a design in a succinct and straightfoward manner. Users can specify commands to occur at particular events, such as during a given circuit condition or
at an absolute simulation timestep. Nodes may be forced to a chosen logic state
to verify proper circuit behavior from any initial condition. The input waveforms
from the VECTOR file can be superseded by another pattem at any point in time.
For debugging purposes simulation breakpoints can be set to halt execution when
a specified event occurs. This "break" command provides designers with the ability
to detect illegal states. Once a break condition is met a command sub-list is
activated to provide status information or to enter into a separate procedure. For
example, a breakpoint might signal an illegal state, display the current output
waveform on the screen, enter a legal state and continue with the Simulation.
4-21
•
4-22
Third-Party Software Tools
Available for Designs with EPLDs
TEXAS
INSTRUMENTS
4-23
II
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant Information to verify, before placing orders, that
the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability forTI applications aSSistance, customer product
deSign, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represents that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other Intellectual property right of n covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1989, Texas Instruments Incorporated
TRADEMARKS
DATA I/O and PLDtest are registered trademark of DATA 1/0
Corporation.
FutureNet is a registered trademark of FutureNet, a DATA 1/0
Corporation.
Vlew/ogle Is a registered trademark of View/ogic Systems, Inc.
Verllog is a registered trademark of Gateway Design Automation
Corp.
LoglCaps and A+PLUS are trademarks of Altera Corporation.
Dash4 is a trademark of FutureNet, a DATA 1/0 Corporation.
OrCADISDT and SOT III are trademarks of OrCAD Systems
Corporation.
ATG is a trademark of Anvil Software.
ABEL is a trademark of DATA 1/0 Corporation.
CUPL is a trademark of LOGICAL DEVICES, INC.
PLDeslgner Is a trademark of MINC INCORPORATED.
QulckSlm, PLD Synthesis, NETED, and Mentor Graphics are
trademarks of Mentor Graphics Corporation
DLS2 is a trademark of Daisy Systems Corp.
ValldSlm Is a trademark of Vaild Logic Systems Inc.
4-24
Third-Party Software Development Tool
Available for Designs with EPLDs
....
"'-'10
~
........................................................................................................................................................................................................................................................................
THIRD-PARTY SOFTWARE DEVELOPMENT TOOLS AVAILABLE FOR
DESIGNS WITH EPLDs FROM TEXAS INSTRUMENTS
The third-party support tools listed below appear to meet the specifications published by their manufacturers. Texas Instruments does not accept any responsibility
for the suitability or accuracy of these products for use with TI EPLDs. Similar
TI products are listed for completeness.
Schematic Capture Software
VENDOR
PRODUCT
TI- EP330, 610, 630, 910, and
EP1810
Texas
Instruments
DEVICES SUPPORTED
LogiCaps'"
ALTERA - EP310, 320, 330, 512,
600,610,630,900,910,1210,
1800, 1810, and EPB1400
DATA 1/0 ®-
DASH4'·
FutureNet®
EP31 0, 320,600,610,900, 910,
1210, 1800,andEP1810
OrCAD
SOT III'"
EP310,320,600,610,9oo, 910,
View/ogic@
Altera ASIC Design
Kit
EP310,320,600,610,900,910,
1210, 1800,andEP1810
Mentor Graphics TM
PLD SyntheSiS '"
EP310, 320, 600,610, 900,910,
1210, 1800, and EP1810
1210, 1800, and EP1810
MINC
PLDesigner TM
EP310,320,600,610, 900,910,
1210, 1800, and EP1810
DATA I/O - FutureNet
DATA I/O - FutureNet's DASH 4.1 SchematiC Capture package can be used to capture the circuit logic of a design. The output of this package is a standard PLD file.
Phone (800) 247-5700 - For more information
4-25
•
OrCAD Netlist Interface to A + PLUS:
OrCAD Systems, a manufacturer and vendor of schematic capture software, has
developed a netllst interface to A+ PLUS 1M as part of their schematic capture
software, the OrCAD/SDT 1M • The Interface translates designs generated with OrCAD's SOT editor Into a netllst format which Is then translated into an ADF file to
be processed by A + PLUS.
Support for Tl's logic symbol and MacroFunctlon libraries is also available with
this interface. Existing OrCAD customers with valid software warranty agreements,
will receive the Interface as part of a general product update. New OrCAD customers
will receive the interface when they purchase the OrCAD/SDT package. It is an integral part of the package.
With thiS interface capability, designs done In the OrCAD/SDT schematic capture
environment can now be processed by A + PLUS. For more information on availability of this Interface, OrCAD/SDT upgrade and related Issues, please contact;
Phone (503) 640-9488 - For more information
View/og/c Altera ASIC Design Kit
Viewloglc has developed a product called The Altera ASIC Design Kit which supports
the TI EPLD product family. The kit provides EPLD library primitives and macro's for
schematic capture and functional Simulation of TI EPLD Designs. An ADF netHst is
produced and can be downloaded to the A + PLUS system for design processing and
device programming.
Phone (BOO) 480-0881 - For more information
Mentor Graphics
Mentor Graphics' PLD Synthesis tool offers the capability of using their NETED 1M
Schematic Capture package to capture the TI EPLD Design. After capture you may
specify the TI EPLD as the target device for programming. The software is fully integrated into the mentor Graphic Design enviorment.
Phone (503) 626-7000 - For more information
MINC Inc.
A number of Schematic Editors may be used to capture a TI EPLD Design for development using MINC's PLDesigner. OrCAD, Mentor, Intergraph, Teradyne, and Cadnetix
editor's are all supported. Additional language and waveform entry options are included. MINC's software operates on Apollo, Sun, NEC9801, PC and PC-compatable platforms.
Phone (719) 590-1155 - For more information
4-26
ALTERNATIVE DESIGN SOFTWARE FOR TI EPLDs:
While it is highly recommended that EPLD designs be processed by the TI EPLD
Development System, there are logic design software packages on the market that
can process TI EPLD designs.
The following is a short list of altemative design software packages.
Software
Version
Devices Supported
Vendor
3.1
EP610,EP910,EP1810
DATAI{O
CUPL'"
3.0
EP610, EP910,EP1810
LOGICAL DEVICES
PLDesigner
1.6
EP610, EP910,EP1810
MINC
ABEL
T•
TEST VECTOR GENERATION AND FAULT GRADING
The following software packages allow design Simulation to be performed by generating test vectors to act as stimuli to the inputs ofthe design and compare subsequent output responses with expected respones according to the particular design.
The programmer load file, in the JEDEC format, is the required input or source file
for the generation of such vectors.
VENDOR
PRODUCT
REVISION
DEVICES SUPPORTED
Anvil
ATG'"
2.23 and UP
EP310, 320, 600, 610,
900,910, and EP1210
DATA I/O
PLDtest@
1.3 and UP
EP310, 320, 600, 610,
900, and EP910
BOARD LEVEL SIMULATION
EPLD models developed by Logic Automation Inc. (LAI) , enable the designer to
do board level Simulation of the entire design, including the individual EPLDs. Such
simulation tasks can only be accomplished using workstations as platforms. The
various workstation platforms capable of simulating with LAI EPLD models are
shown below.
VENDOR
PLATFORM
DEVICES SUPPORTED
MENTOR - QuickSim '"
Logic
DAISY _ DLS2 T.
Automation
VALID - ValidSim T.
EP310,320,600,610,
910, 1800, and 1810
GATEWAY - Verilog@
4-27
...
General-Purpose EPLD Behavioral Simulation Models from
Logic Automation Inc. (LAI):
Most designers have design verification requirements that involve simulation
of a complete system. However existing EPLD design verification tools like
PLFSIM (used with A + PLUS), can only simulate the logic integrated Into the EPLD,
and not the entire system design. "JYpically these overall system simulation requirements are met using tools available atthe workstation level, such as simulation tools
offered by Mentor, Daisy and Valid.
In order to accurately represent logic and timing information integrated into an
EPLD, a model must be constructed in the appropriate simulation format. Logic
Automation Inc., based in Portland, Oregon, has a contract with Texas Instruments
to construct models of nearly everyTI Programmable Logic Device, Including the
current line of EPLDs. LAI has been provided with specific architectural information
forthe EP61 0, EP910, and EP1810 general-purpose EPLDs which Includes macrocell configuration and all ac timing parameters.
LAI has constructed behavioral simulation models, based on the detailed information
supplied, for the Mentor, Valid, Daisy and Gateway simulators.
For more information on system simulation involving the
n EPLDs, please
contact:
LAI, Applications Dept
19545 N.w. Von Neumann Drive
P.O. Box 310
Beaverton,Oregon 97075
1el: (503) 690-6900
These are some of the Third-Parties who support TI EPLD Design Development in
some way. While the n A + PLUS System is recommended, this extensive additional
support offers you, the deSigner, choices. These choices can make integration of TI
EPLDs into your Design Environment easier. Call the TI Hotline or the local Third-Party vendor if you have questions regarding Third-Party support tools.
TI Holline: Phone (214) 997-5666
TI Bulletin Board: Phone (214) 997-5665
4-28
Mechanical Data
5-1
•
5-2
MECHANICAL DATA
FK020 and FK028 ceramic chip carrier packages
Each of these hermetically sealed chip carrier packages has a three-layer ceramic base with a metal lid
and braze seal. The packages are intended for surface mounting on solder lands on 1,27 (O.050-inch)
centers. Terminals require no additional cleaning or processing when used in soldered assembly.
FK package terminal assignments conform to JEDEC Standards 1 and 2.
FK020 and FK028
128-terminal package shown)
CERAMIC CHIP CARRIERS
JEDEC
OUTLINE
DESIGNA TlON'
NO.OF
TERMINALS
MS004CB
20
MS004CC
28
A
MIN
MAX
MIN
MAX
8,69
(0.3421
11,23
(0.4421
9,09
(0.3581
11.63
(0.4581
7,80
(0.3071
10,31
(0.4061
9,09
(0.3581
11.63
(0.4581
·AII dimensions and notes for the specified JEDEC outline apply,
0,5 1 10.020 1-+1
0,25 (0.0101
",
r,
J-.-1----r::
0,51 10,0201
0,25 (0,0101
1,1410.0451
---..L 0,89 10,0351
~I
1---+
I
0.71 (0.028)
0.56 (0.022)"1
2.0310.080)
1,6310.064)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-3
..
MECHANICAL DATA
FN020, FN028, FN044, FN068, and FN084 plastic chip carrier packages
Each of these chip carrier packages consists of a circuit mounted on a lead frame artd encapsulated within
an electrically nonconductive plastic compound. The compound withstands soldering temperatures with
no deformation, and circuit performance characteristics remain stable when the devices are operated in
high-humidity conditions. The packages are intended for surface mounting on solder lands on 1,27 (0.050)
centers. Leads require no additional cleaning or processing when used in soldered assembly.
FN020. FN028, FN044, FN052. FN068, and FN084
120-terminal package used for illiustration)
o
)+10.18 (0007)«11
•
a (J)I
FH- ISee Note
0-E(I)1
A- 01 (See Note B I - +
~
1+10,18
1.22 (0.048) 2 PLACES
w
I!
W
a.
~
...
~ i~. L
~
z
W s '"
~~
~ ~
... --t
I I
-
1.42 (0 056)
II
1.07iii042i
I
~
~TYP
~ 'I':~'~ ~;" O
~
~t!.
~ SIDES~
-G-
1",
1
(See Note FJ
(See Note C)
I
(j
SEATING PLANE
V~'::"~E~20)R MAxn A
I+- +I j4ffi. (See Note C)
I-I.r-
t.
9
10
11
12
13
--J k
1
(See Note FJ
1+10,38
(O.~'5)@lo
ECSlI
1+!o,JlI (o.OI')~!.-G@1
~
__~~~~J
~~=====j=~
0)
(O.OO7)l1)!B(J)!O-E@!
1.lI(D,002 ../IN)I'1
1.07 (0.042)
A1
-
0,51 (0.020) MIN
ISee Note C)
SUM OF DAM BAR PROTRUSIONS-...,--~~"
TO BE 0,17 (0.007) MAXIMUM
PER LEAD
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. All dimensions conform to JEDEC Specification MO-047AA/AF. Dimensions and tolerancing are per ANSI Y14.5M-1982.
B. Dimensions 01 and E1 do not include mold flash protrusion. Protrusion shall not exceed 0,25 10.010) on any side.
C. Datums ID-EI and IF-GI for center leads are determined at datum I-H-I
D. Datum
E::l
is located at top of leads where they exit plastic body.
E. Location to datums
0
F. Determined at seating plane
5-4
j"d
~-B-I
to be determined at datum
EB:j
-C
TEXAS . "
INSIRUMENlS
POST OFFICE BOX 655303 • DALLAS. TEXAS 76266
MECHANICAL DATA
FN020. FN028. FN044. FN068. and FN084 plastic chip carrier packages (continued)
JEOEC
NO.
OUTLINE
OF
PINS
MO-047AA
20
MO-047AB
28
MO-047AC
44
MO-047AD
52
MO-047AE
MO-047AF
68
84
A
0, E
A,
MIN
MAX
MIN
4.19
10.165)
4.57
10.180)
2,29
10.090)
MAX
3,05'
10.120)
0,. E,
MIN
MAX
MIN
9,78
10.385)
10.03
10.395)
8,89
10.350)
MAX
9,04
MIN
7,37
5,08 10.200)
10.390)
10.92
10.430)
7,62 10.300)
14.99
10.590)
16.00
10.630)
12,7010.500)
17.53
10.690)
18.54
10.730)
23,62
10.290)
10.456)
16,66
4,19
4,57
2,29
3,05
12,32
12,57
10.180)
10.090)
10.120)
10.485)
10.495)
11,43
10.450)
4,19
4,57
3,05
17,40
10.165)
10.180)
2.29
10.090)
10.120)
10.685)
17.65
10.695)
16.51
10.650)
4.19
5,08
10.200)
2.29
10.090)
3,30
19.94
19,20
10.785)
20,19
10.795)
19,05
10.130)
10.750)
5,08
3,30
10.130)
25.02
10.985)
25,27
10.995)
24,13
10.950)
10.756)
24,33
10.656)
10.165)
10.200)
2.29
10.090)
4,19
5,08
2,29
3,30
30,10
30,35
29,21
29,41
10.165)
10.200)
10.090)
10.130)
11.185)
11.195)
11.150)
11.158)
10.958)
03. E3 BASIC
MAX
8,38
10.330)
10.356)
11,58
10.165)
10.165)
4,19
D2. E2
(s•• Not. F)
9,91
22,61
10.890)
27,69
11.090)
10.930)
28,70
11.130)
15,24 10.600)
20,32 10.800)
25,40 11.000)
NOTES: A. All dimensions conform to JEOEC Specification MO-047AA/AF. Dimensions and to)erancing are per ANS) Y14.5M-1982.
F. Determined at seating plane
I-c-I
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 76265
5-5
MECHANICAL DATA
J020 ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during sc;>ldering. Solder-coated leads require no additional cleaning or
processing when used in soldered assembly.
J020
..
24,7610.975)
"0 - - - - - 23,62 10.930) -----<·~I
@@@@@@@@@@
g
Ii.
I
Ii.
~:~~:~:~~~:
7,62 (O.30D)
0000®00®®@
6,22 (0.245)
1
1.78 (D.07DI MAX 20 PLACES
1,27 (0.050) NOM
~ _S!t~~~G "'3"',3"-0~ltL' '30," )
~~~..L::...L"-'::::""n..D...D....cWCo...Lo..,
'.:1'
(See Note AI
I
I
L
II
i
I
7.11 (0.280)
P
'
I.
!
,,I--r~"~~': ~~·ni!II1~·~·'ird:l-I~rll
i
1,0210_0401
0.25100101
ttl-----.i
fo-
.
2.34 (0 092)
11410.0451
1.14100451
0.13 100051
4 PLACES
J UU
~
I
12.95 105101------1
MAX
000000000@
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS ANO PARENTHETICALLY IN INCHES
NOTES: A. Leads are within 0,13 (0.005) radius of true position (T.P.) at maximum material condition.
B. This dimension determines a zone within which all body and lead irregularities lie.
C. Index point is provided on cap for terminal identification only.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-11
MECHANICAL DATA
W024 ceramic flat package
This hermetically sealed flat package consists of an electrically non conductive ceramic base and cap and
a lead frame. Hermetic sealing is accomplished with glass. Leads require no additional cleaning or processing
when used in soldered assembly.
W024
~:~~: :~ ~~~:
24 LEADS
@@@@@@)@)@@@)@@
'.27100501
-,H---......
r
°42~L(~i:°E~OI_
r-
K
1 2~2(~~g~:·P.
•[
ISe. No" AI
10.16 (04001
---TIS"N~T
~
f"\
0,483 10.019\
ft-~
24 LEADS
1 )
10,161O.400)
(See Note BI
30,5 {1 200)
2'4.1iii9Soi
BAse ANO - ' "
SEATING PLANE
10,1 (0.395)
-1:=--- --- --8.5~~~~~cr~~~~~cr~~~~
--] ·.fHf ff.
ft ff.l=f.
~::lllllill
....
W'23104851MIN
1 0 - - - - - 1 6 , 2 (0.635) MAX
1111111
rn
-----01
Falls Within JEDEC MO·019AA Dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Leads are within 0,13 (0.0051 radius of true position (T.P.I at maximum material condition.
B. This dimension determines a zone within which all body and lead irregularities lie.
C. Index point is provided on cap for terminal identification only.
5-12
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 666303 • DALLAS. TEXAS 75266
•
..
TI Worldwide
Sales Offices
ALABAMA: Huntsville: 500 Wynn Drive, Suite 514,
Huntsville, AL 35805, (2051 837-7530.
ARIZONA: Phoenix: 8825 N. 23rd Ave., Phoenix.
AZ 85021, (6021 995-1007;TUCSON: 818 W. Miracle
Mile, Suite 43, Tucson. AZ 86105, 16021 292-2640.
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Australia ltd.: 6-10 Talavera Rd., North Ryde
(Sydney), New South Wales, Australia 2113,
2 + 887-1122; 5th Floor, 418 St. KHda Road,
Melbourne. Victoria, Australia 3004, 3 + 267·4677;
171 Philip Highwav, Elizabeth, South Australia 5112,
8 + 255-2066.
AUSTRIA: Texas Instruments Ges.m.b.H.:
Industriestrabe 8/16, A-2345 Brunn/Geblfge,
2236-846210.
BELGIUM: Texas Instruments N.V. Belgium S.A.: 11,
Avenue Jules Bondetlaan 1 1,1140 Brussels, Belgium,
(02) 242-3080.
BRAZIL: Texas Instruments Electronicos do Brasil
ltda.: Rua Paes leme, 524-7 Andar Pinheiros, 05424
Sao Paulo, Brazil, 0815-6166.
DENMARK: Texas Instruments AIS, Mairelundvej 46E,
2730 Herlev, Denmark, 2 - 91 7400.
FINLAND: Texas Instruments Finland OY:
Ahertajantie 3, P.O. Box 81, ESPOO, Finland, (90)
0-461-422.
FRANCE: Texas Instruments France: Paris Office, BP
67 8-io Avenue Morane·Saulnier, 78141 VelizyVillacoublay cedex (1) 30 70 1003.
GERMANY (Fed. Republic of Germany): Texas
Instruments Deutschland GmbH: Haggenystrasse "
B050 Freising, 8161 + 80-4591: Kurfuerstendamm
195/196,1000 Beriin 15, 30+882-7365; III. Hagen
43/Kibbelstrasse, .19, 4300 Essen, 201-24250;
Kirchhorsterstrasse 2, 3000 Hannover 51,
511 + 648021; Maybachstrabe 1" 7302 Ostfildern
2-Netingen, 711 +34030.
IRELAND: Texas Instruments /Ireland 1 limited:
71B Harcourt Street, Stitlorgan, County Dublin, Eire,
1 781677.
ITALY: Texas Instruments Italla S.p.A. Divisione
Semiconduttori: Viale Europa, 40, 20093 Cologne
Monzese lMilano\, 102\ 253001; Via Castetlo della
Magtiana, 38, 00148 Aoma, (06) 5222651;
Via Amendola, 17,40100 Bologna, (051) 554004.
JAPAN: Tokyo Marketing/Sales (Headquarters):
Texas Instruments Japan ltd., MS Shibaura Bldg., 9F,
4-13-23 Shibaura, Minato-ku, Tokyo 108, Japan,
03-769-8700. Texas Instruments Japan Lid.: NisshoIwal Bldg. 5F, 30 Imabashi 3-chome, Higashi-ku,
Osaka 541. Japan, 06-294·1881; Daini Toyota West
Bldg. 7F, 10-27 Meieki 4-chome, Nakamura-ku,
Nagoya 450, 052-583-8691; Daiichi Seimai Bldg. SF,
3-10 Oyama-cha, KanazaWB 920, Ishikawa-ken,
0762-23·5471; Daiichl Olympic Tachikawa Bldg. 6F,
1-25-12 Akebono-cho, Tachikawa 190, Tokyo,
0425-27-6426; Matsumoto Showa Bldg. 6F, 2·11
Fukashl l-chome, Matsumoto 390, Nagano-ken,
0263-33·1060; Yokohama Nishiguchi KN 8ldg. 6F,
2-8-4 Kita-Saiwai-cho, NIShi-ku, Yokohama 220,
045-322-6741; Nihon Seimei Kyoto Yasaka Bldg. 5F,
843-2 Higashi Shiokohjidori, Nishinotoh-in Higashi-lru,
ShlOkouji, ShimoQyo-ku, Kyoto 600, 075-341·7713;
2597-1, Aza Harudal, Oaza Yasaka, Kltsuki 873, Oitaken, 09786-3-3211; Miho Plant, 2350 Kihara Mihomura, Inashiki-gun 300-04, Ibaragi-ken,
0298·85-2541.
KOREA: Texas Instruments Korea Ltd., 2Bth Ft., Trade
Tower, 1159, Samsung-Dong, Kangnam-ku, Seoul,
Korea 2+551-2810.
MEXICO: Texas Instruments de MeXICO S.A.: Alfonso
Reyes -115, Col. Hlpodromo Condesa, MeXICO, D.F.,
Mexico 06120,525/525·3860.
MIDDLE EAST: Texas Instruments: No. 13, 1 st Floor
Mannai Bldg .. Diplomatic Area, P.O. Box 26335,
Manama Bahrain, Arabian Gulf, 973 + 274681.
NETHERLANDS: Texas Instruments Holland B.V.,
19 Hogehilweg, 1100 AZ Amsterdam-Zuidoost,
Holland 20 + 5602911.
NORWAY: Texas Instruments Norway A/S: PB106,
Refstad 0585, Oslo 5, Norway, 12\ 155090
PEOPLES REPUBLIC OF CHINA: Texas Ins\!uments
China Inc., 8eijing Representative Office, 7-05 Citic
Bldg., 19 Jianguomenwai Dajja, Beijmg, China, (B61)
5002255, Ext. 3750.
PHILIPPINES: Texas Instruments ASia ltd.: 14th Floor,
B(I- lepanto Bldg., Paseo de Roxas, Makati, Metro
Manila, Philippines, 817-60-31.
PORTUGAL: Texas Instruments EqUipamento
Electrolllco (Ponugall. lda.: Rua Eng. Frederico Ulrich,
2650 Moreira Da Maia, 4470 Maia, Ponugal,
2-948-1003.
SINGAPORE I + INDIA, INDONESIA, MALAYSIA,
THAILAND): Texas Instruments Singapore (PTE) ltd.,
Asia Pacific DiviSion, 101 Thompson Rd. 123-01,
United Square, Singapore 1130, 350-B100.
SPAIN: Texas Instruments Espana, S.A.: CIJose
Lazaro Galdiano No.6, Madrid 28036,1/458.14.58.
SWEDEN: Texas Instruments International Trade
Corporation (Sverigefilialen): S- 1 64-93, Stockholm,
Sweden, 8 - 752-5800.
SWITZERLAND: Texas Instruments, Inc., Reidstrasse
6, CH-8953 Dietikon (Zuerich) Switzerland,
'·7402220.
TAIWAN: Texas Instruments Supply Co., 9th Floor
Bank Tower, 205 Tun Hwa N. Rd., Taipei, Taiwan,
RepubliC of China, 2 + 713-9311.
NORTH CAROLINA: Charlotte: 8 Woodlawn Green,
Woodlawn Rd., Charlotte, NC 28210, (704)
527-0933; Raleigh: 2809 Highwoods Blvd., Suite 100,
Raleigh, NC 27625, (919) 876-2725.
OHIO: Beachwood: 23775 Commerce Park Ad.,
Beachwood, OH 44122, (216\ 464-6100;
Be.....rcreek: 4200 Colonel Glenn Hwy.,
Beavercreek, OH 45431, (513) 427-6200.
HONG KONG: Texas Instruments Hong Kong ltd., 8th
Floor, World Shipping Ctr., 7 Canton Rd., Kowloon,
Hong Kong, (852\ 3-7351223.
UNITED KINGDOM: Texas Instruments limited:
Manton lane, Bedford, MK41 7PA, England, 0234
270111.
TEXAS
INSTRUMENTS
A-189
TI Sales Offices TI Distributors
MARYLAND: Arrow/Kierulff (301) 995-6002;
Hall-Mark (301) 968-9800; Marshall (301) 235-9464;
Schweber (301) 840-5900; Zeus (301) 997-1118.
ALABAMA: Huntsville (205) 837-7530.
MASSACHUSETTS Arrow/Klerultf (508) 658-0900;
Half-Mark (506) 667-0902; Marshall (508) 658-0810;
Schweber (617) 275-5100; Time (617) 532-6200;
Wyle (617) 273-7300; Zeus (617) 863-8800.
ARIZONA: Phoenix (602) 995·1007;
Tucson (602) 292·2640.
CALIFORNIA: Irvine (714) 660-1200;
Roseville (916) 786·9208;
San Diego (619) 278·9601;
Santa Clara (408) 980·9000;
Torrance (213) 217.7010;
Woodland Hills (818) 704·7759.
COLORADO: Aurora (303) 368·8000.
CONNECTICUT: Wallingford (203) 269-0074.
FLORIDA:
Altamonte Springs (305) 260-2116;
Ft. Lauderdale (305) 973·8502;
Tampa (813) 885-7411.
GEORGIA: Norcross (404) 662.7900.
ILLINOIS: Arlington Heights (312) 640·2925.
INDIANA: Carmel (317) 573·6400;
Ft. Wayne (219) 424·5174.
IOWA: Cedar Rapids (319) 395-9550.
TI AUTHORIZED DISTRIBUTORS
Arrow/Klerulff ElectroniCS Group
Arrow (Canada)
Future Electronics (Canada)
GRS Electronics Co., Inc.
Hall·Mark Electronics
Marshall Industries
Newark Electronics
Schweber Electronics
Time Electronics
Wyle laboratories
Zeus Components
-OBSOLETE PRODUCT ONLYRochester ElectroniCS, Inc.
Newburyport, Massachusetts
(508) 462·9332
MARYLAND: Columbia (301) 964·2003.
MICHIGAN: Farmington Hills (313) 553-1569;
Grand Rapids (616) 957-4200.
MINNESOTA: Eden Prairie (612) 828-9300.
MISSOURI: St. Louis (314) 569-7600.
NEW JERSEY: Iselin (201) 750-1050.
NEW MEXICO: Albuquerque (505) 345-2555.
NEW YORK: East Syracuse (315) 463-9291;
Melville (516) 454-6600;
Pittsford (716) 385-6770;
Poughkeepsie (914) 473-2900.
NORTH CAROLINA: Charlotte (704) 527-0933;
Raleigh (919) 876-2725.
OHIO: Beachwood (216) 464-6100;
Beaver Creek (513) 427-6200.
OREGON: Beaverton (503) 643-6758.
PENNSYLVANIA: Blue Bell (215) 825-9500.
PUERTO RICO: Hato Rey (609) 753-8700.
TENNESSEE: Johnson City (615) 461-2192.
TEXAS: Austin (512) 250-7655;
Houston (713) 778-6592;
Richardson (214) 680-5082;
San Antonio (512) 496-1779.
UTAH: Murray (801) 266-6972.
WASHINGTON: Redmond (206) 881-3080.
WISCONSIN: Brookfield (414) 782-2899.
CANADA: Nepean, Ontario (613) 726-1970;
Richmond Hili, Ontario (416) 884-9181;
5t. Laurent, Quebec (514) 336-1860.
ALABAMA: Arrow/KierutH (205) 837-6955;
Hall-Mark (205) 837-8700; MarShall (205) 881-9235;
Schweber (205) 895-0480.
ARIZONA: ArrowiKlerutff (602) 437-0750;
Halt·Mark (602) 437·1200; Marshall (602) 496-0290;
Schweber (602) 431-0030; Wyte (602) 866-2888.
CALIFORNIA: Los Angeles/Orange County:
Arrow/Kierulff (818) 701-7500, (714) 838-5422;
Half-Mark (818) 773-4500, (714) 669-4100;
Marshall (818) 407-0101, (818) 459·5500,
(714) 458-5395; Schweber (818) 880-9686;
(714) 863-0200, (213) 320-8090; Wyte (818) 880-9000.
ra':;a~;~~~~3~;!~_u,;at~1 U,~~~~~~~a(f;18) a89-3838;
Marshall (916) 635-9700; Schweber (916) 364-0222;
Wyle (916) 638·5282;
Ssn Diego: Arrow/Kierulff (619) 565-4800;
Half-Mark (619) 268-1201; Marshall (619) 578-9600;
Schweber (619) 450-0454; Wyle (619) 565-9171;
San Francisco Bay Area: Arrow/Kierulff (408) 745-6600,
Hall-Mark (408) 432-0900; Marshall (408) 942-4600;
Schweber (408) 432-7171; Wyle (408) 727-2500;
Zeus (408) 998·5121.
COLORADO: Arrow/KierulH (303) 790-4444;
Hail·Mark (303) 790-1662; Marshall (303) 451-8383;
Schweber (303) 799-0258; Wyle (303) 457-9953.
CONNETICUT: Arrow/Kierulff (203) 265-7741;
Hall-Mark (203) 271-2844; Marshall (203) 265-3822;
Schweber (203) 264-4700.
FLORIDA: Ft. Lauderdale:
Arrow/KierulH (305) 429-8200; Hall-Mark (305) 971-9280;
Marshall (305) 977-4880; Schweber (305) 977-7511;
Orlando; Arrow/Kierulff (407) 323-0252;
Hall·Mark (407) 830-5855; Marshall (407) 767-8585;
Schweber (407) 331-7555; Zeus (407) 365-3000;
Tampa: Hall·Mark (813) 530-4543;
Marshall (813) 576-1399; Schwebp.r (813) 541-5100.
GEORGIA: Arrow/Kierulff (404) 449-8252;
Half-Mark (404) 447-8000; Marshall (404) 923·5750;
Schweber (404) 449-9170.
TI Regional
Technology Centers
CALIFORNIA: Irvine (714) 660-8105;
Santa Clara (408) 748-2220;
GEORGIA: Norcross (404) 662-7945.
ILLINOIS Arlington Heights (312) 640-2909.
MASSACHUSETTS: Waltham (617) 895-9196.
~~~_~~~~~~:2t;~~~d~6ti~u~~~~~~rl ~~~2~ ~~~-2211;
Schweber (612) 941-5280.
MISSOURI: St. Louis: Arrow/Kierulff (314) 567-6888;
Hall-Mark (314) 291-5350; Marshall (314) 291-4650;
Schweber (314) 739-0526.
NEW HAMPSHIRE: Arrow/Kierulff (603) 668-6968;
Schweber (603) 625-2250.
NEW JERSEY: Arrow/Kierultf (201) 538-0900,
(609) 596-8000; GAS Electronics (609) 964~8560;
Hall·Mark (201) 575-4415, (201) 882·9773,
(609) 235-1900; Marshall (201) 882-0320,
(609) 234-911)0; Schweber (201) 227-7880.
NEW MEXICO: Arrow/Kierultf (505) 243-4566.
:~:WT~~~I:ff (~~~ kS~~~~~; Hall-Mark (516) 737-0600;
KANSAS: Overland Park (913) 451·4511.
MASSACHUSETTS: Waltham (617) 895-9100.
MICHIGAN: Detroit: Arrow/Kierulff (313) 462-2290;
Hall-Mark (313) 462-1205; Marshall (313) 525-5850;
Newark (313) 967-0600; Schweber (313) 525-8100;
Grand Rapids: Arrow/Klerulff (616) 243-0912.
ILLINOIS: Arrow/Kieruttf (312) 250·0500;
Haft-Mark (312) 860-3800; Marshall (312) 490-0155;
Newark (312) 784-5100; Schweber (312) 364·3750.
INDIANA: Indianapolis: Arrow/Kierutff (317) 243·9353;
Hall-Mark (317) 872-8875; Marshall (317) 297-0483;
Schweber (317) 843-1050.
IOWA: Arrow/Kierultf (319) 395-7230;
Schweber (319) 373-1417.
KANSAS: Kansas City: Arrow/KierurH(913) 541-9542;
Hall-Mark (913) 888-4747; Marshall (913) 492-3121;
Schweber (913) 492-2922.
Marshall (516) 273-2424; Schweber (516) 334-7474;
Zeus (914) 937-7400;
Rochester: Arrow/Kierulff (716) 427-0300;
Hall-Mark (716) 425-3300; Marshall (716) 235-7620;
Schweber (716) 424-2222;
Syracuse: Marshall (607) 798-1611.
NORTH CAROLINA: Arrow/Kierulff (919) 876-3132,
(919) 725-8711; Hall-Mark (919) 672-0712;
Marshall (919) 878-9882; Schweber (919) 876·0000.
OHIO: Cleveland: Arrow/Klerulff (216) 248-3990;
Hall-Mark (216) 349-4632; Marshall (216) 248-1788;
Schweber (216) 464.2970;
Columbus: Hall-Mark (614) 888-3313;
Dayton: Arrow/Kierulff (513) 435-5563;
Marshall (513) 898-4480; Schweber (513) 439·1800.
OKLAHOMA: Arrow/Kierultf (916) 252-7537;
Schweber (918) 622-8003.
OREGON: Arrow/Kierulff (503) 645-6456;
Marshall (503) 644-5050; Wyle (503) 640-6000.
r2~~~:2Y8~~:0~I;AGA~r~I:~~rl~~~~~ ~;~;~ :~~:~g~~;
Marshall (412) 963-0441; Schweber (215) 441-0600,
(412) 963-6804.
TEXAS: Austin: Arrow/Kierulff (512) 835-4180;
Hall-Mark (512) 258-8848; Marshall (512) 837-1991;
Schweber (512) 339-0088; Wyle (512) 834-9957;
Dallas: Arrow/KJerulff (214) 380-6464;
Hall-Mark (214) 553-4300; Marshall (214) 233-5200;
Schweber (214) 661-5010; Wyle (214) 235·9953;
Zeus (214) 783-7010;
EI Paso: Marshall (915) 593-0706;
Houston: Arrow/Kierulff (713) 530-4700;
Halt-Mark (713) 781-6100; Marshall (713) 895-9200;
Schweber (713) 784-3600; Wyle (713) 879-9953.
UTAH: Arrow/Kierulff (801) 973-6913;
Half-Mark (801) 972-1008; Marshall (801) 485-1551;
Wyle (801) 974-9953.
WASHINGTON: Arrow/Klerulff (206) 575-4420;
Marshall (206) 486-5747; Wyle (206) 881-1150.
WISCONSIN: Arrow/Kierultf (414) 792-0150;
Hall-Mark (414) 797-7844; Marshall (414) 797-8400;
Schweber (414) 784-9020. '
CANADA: Calgary: Future (403) 235-5325;
Edmonton: Future (403) 438-2858;
Montreal: Arrow Canada (514) 735-5511;
Future (514) 694·7710;
Ottawa: Arrow Canada (613) 226-6903;
Future (613) 820·8313;
Quebec City: Arrow Canada (418) 871·7500;
Toronlo: Arrow Canada (416) 672-7769;
Future (416) 638-4771; Marshall (416) 674-2161;
Vancouver: Arrow Canada (604) 291·2986;
Future (604) 294-1166.
TEXAS: Richardson (214) 680-5066.
CANADA: Nepean, Ontario (613) 726-1970.
Customer
Response Center
TEXAS
INSTRUMENTS
TOLL FREE: (800) 232-3200
OUTSIDE USA: (214) 995-6611
(8:00 a.m. - 5:00 p.m. CST)
A-189
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